ST25W01M1TR [STMICROELECTRONICS]
SERIAL 1K 128 x 8 EEPROM; 串行1K 128 ×8 EEPROM
| 型号： | ST25W01M1TR |
| 厂家： | 
ST |
| 描述： | SERIAL 1K 128 x 8 EEPROM |
| 文件： | 总16页 (文件大小：147K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ST24/25C01, ST24C01R
ST24/25W01
SERIAL 1K (128 x 8) EEPROM
NOT FOR NEW DESIGN
1 MILLION ERASE/WRITE CYCLES with
40 YEARS DATA RETENTION
SINGLE SUPPLY VOLTAGE:
– 3V to 5.5V for ST24x01 versions
– 2.5V to 5.5V for ST25x01 versions
– 1.8V to 5.5V for ST24C01R version only
HARDWARE WRITE CONTROL VERSIONS:
ST24W01 and ST25W01
TWO WIRE SERIAL INTERFACE, FULLY I2C
BUS COMPATIBLE
8
8
1
1
PSDIP8 (B)
0.25mm Frame
SO8 (M)
150mil Width
BYTE and MULTIBYTE WRITE (up to 4
BYTES)
PAGE WRITE (up to 8 BYTES)
BYTE, RANDOM and SEQUENTIAL READ
MODES
Figure 1. Logic Diagram
SELF TIMED PROGRAMMING CYCLE
AUTOMATIC ADDRESS INCREMENTING
ENHANCED ESD/LATCH UP
PERFORMANCES
ST24C/W01 are replaced by the M24C01
ST25C/W01 are replaced by the M24C01-W
ST24C01R is replaced by the M24C01-R
V
CC
DESCRIPTION
This specification covers a range of 1K bits I2C bus
EEPROM products, the ST24/25C01, the
ST24C01R and the ST24/25W01. In the text, prod-
ucts are referred to as ST24/25x01, where "x" is:
"C" for Standard version and "W" for hardware
Write Control version.
3
E0-E2
SDA
ST24x01
ST25x01
ST24C01R
SCL
MODE/WC*
Table 1. Signal Names
E0-E2
SDA
SCL
Chip Enable Inputs
Serial Data Address Input/Output
Serial Clock
V
SS
AI00839D
Multibyte/Page Write Mode
(C version)
MODE
WC
VCC
VSS
Write Control (W version)
Supply Voltage
Ground
Note: WC signal is only available for ST24/25W01 products.
November 1997
1/16
This is information on a product still in production but not recommended for new design
ST24/25C01, ST24C01R, ST24/25W01
Figure 2A. DIP Pin Connections
Figure 2B. SO Pin Connections
ST24x01
ST25x01
ST24x01
ST25x01
ST24C01R
ST24C01R
E0
E1
E2
1
2
3
4
8
V
E0
E1
E2
1
2
3
4
8
V
CC
MODE/WC
CC
7
MODE/WC
7
6
5
SCL
6
5
SCL
V
SDA
V
SDA
SS
SS
AI00840D
AI00841E
Table 2. Absolute Maximum Ratings (1)
Symbol
TA
Parameter
Value
Unit
°C
Ambient Operating Temperature
Storage Temperature
–40 to 125
–65 to 150
TSTG
°C
TLEAD
Lead Temperature, Soldering
(SO8 package)
40 sec
215
260
°C
(PSDIP8 package) 10 sec
VIO
Input or Output Voltages
Supply Voltage
–0.6 to 6.5
–0.3 to 6.5
4000
V
V
V
V
VCC
Electrostatic Discharge Voltage (Human Body model) (2)
Electrostatic Discharge Voltage (Machine model) (3)
VESD
500
Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other
relevant quality documents.
2. MIL-STD-883C, 3015.7 (100pF, 1500 Ω).
3. EIAJ IC-121 (Condition C) (200pF, 0 Ω).
tional data bus and serial clock. The memories
DESCRIPTION (cont’d)
carry a built-in 4 bit, unique device identification
code (1010) corresponding to the I2C bus defini-
The ST24/25x01 are 1K bit electrically erasable
tion. This is used together with 3 chip enable inputs
programmable memories (EEPROM), organized
(E2, E1, E0) so that up to 8 x 1K devices may be
as 128 x 8 bits. They are manufactured in SGS-
attached to the I2C bus and selected individually.
THOMSON’s Hi-Endurance Advanced CMOS
The memories behave as a slave device in the I2C
technology which guarantees an endurance of one
protocol with all memory operations synchronized
million erase/write cycles with a data retention of
by the serial clock. Read and write operations are
40 years. The memories operate with a power
initiated by a START condition generated by the
supplyvalueaslowas1.8VfortheST24C01Ronly.
bus master. The START condition is followed by a
Both Plastic Dual-in-Line and Plastic Small Outline
packages are available.
The memories are compatible with the I2C stand-
ard, two wire serial interface which uses a bi-direc-
stream of 7 bits (identification code 1010), plus one
read/write bit and terminated by an acknowledge
bit.
2/16
ST24/25C01, ST24C01R, ST24/25W01
Table 3. Device Select Code
Device Code
Chip Enable
RW
b0
Bit
b7
1
b6
b5
1
b4
0
b3
b2
b1
Device Select
0
E2
E1
E0
RW
Note: The MSB b7 is sent first.
Table 4. Operating Modes (1)
Mode
RW bit
MODE
Bytes
Initial Sequence
START, Device Select, RW = ’1’
Current Address Read
’1’
’0’
’1’
’1’
’0’
’0’
’0’
X
1
START, Device Select, RW = ’0’, Address,
reSTART, Device Select, RW = ’1’
Similar to Current or Random Mode
START, Device Select, RW = ’0’
START, Device Select, RW = ’0’
START, Device Select, RW = ’0’
Random Address Read
X
1
Sequential Read
Byte Write
X
X
1 to 128
1
4
8
Multibyte Write (2)
VIH
VIL
Page Write
Notes: 1. X = VIH or VIL
2. Multibyte Write not available in ST24/25W01 versions.
When writing data to the memory it responds to the
8 bits received by asserting an acknowledge bit
during the 9th bit time. When data is read by the
bus master, it acknowledges the receipt of the data
bytes in the same way. Data transfers are termi-
nated with a STOP condition.
Serial Data (SDA). The SDA pin is bi-directional
and is used to transfer data in or out of the memory.
It is an open drain output that may be wire-OR’ed
with other open drain or open collector signals on
thebus. Aresistormust beconnectedfromtheSDA
bus line to VCC to act as pull up (see Figure 3).
Power On Reset: VCC lock out write protect. In
order to prevent data corruption and inadvertent
write operations during power up, a Power On
Reset (POR) circuit is implemented. Until the VCC
voltage has reached the POR threshold value, the
internal reset is active, all operations are disabled
and the device will not respond to any command.
In the same way, when VCC drops down from the
operating voltage to below the POR threshold
value, all operations are disabled and the device
will not respond to any command. A stable VCC
must be applied before applying any logic signal.
Chip Enable (E0 - E2). These chip enable inputs
are used to set the 3 least significant bits (b3, b2,
b1) of the 7 bit device select code. These inputs
may be driven dynamically or tied to VCC or VSS to
establish the device select code.
Mode (MODE). The MODE input is available on pin
7 (see also WC feature) and may bedrivendynami-
cally. It must be at VIL or VIH for the Byte Write
mode, VIH for Multibyte Write mode or VIL for Page
Write mode. When unconnected, the MODE input
is internally read as VIH (Multibyte Write mode).
Write Control (WC). An hardware Write Control
feature (WC) is offered only for ST24W01 and
ST25W01 versions on pin 7. This feature is usefull
to protect the contents of the memory from any
erroneous erase/write cycle. The Write Control sig-
nal is used to enable (WC = VIH) or disable (WC =
VIL) the internal write protection. When uncon-
nected, the WC input is internally read as VIL and
the memory area is not write protected.
SIGNAL DESCRIPTIONS
Serial Clock (SCL). The SCL input pin is used to
synchronize all data in and out of the memory. A
resistor can be connected from the SCL line to VCC
to act as a pull up (see Figure 3).
3/16
ST24/25C01, ST24C01R, ST24/25W01
SIGNAL DESCRIPTION (cont’d)
Stop Condition. STOPis identified bya lowto high
transition of the SDA line while the clock SCL is
stable in the high state. A STOP condition termi-
nates communication between the ST24/25x01
and the bus master. A STOP condition at the end
of a Read command, after and only after a No
Acknowledge, forces the standby state. A STOP
condition at the end of a Write command triggers
the internal EEPROM write cycle.
The devices with this Write Control feature no
longer support the Multibyte Write mode of opera-
tion, however all other write modes are fully sup-
ported.
Refer to the AN404 Application Note for more de-
tailed information about Write Control feature.
Acknowledge Bit (ACK). An acknowledge signal
is used to indicate a successfull data transfer. The
bus transmitter, either master or slave, will release
the SDAbus after sending 8 bits of data. During the
9th clock pulse period the receiver pulls the SDA
bus low to acknowledge the receipt of the 8 bits of
data.
Data Input. During data input the ST24/25x01
sample the SDA bus signal on the rising edge of
the clock SCL. Note that for correct device opera-
tion the SDAsignal must be stable during the clock
low to high transition and the data must change
ONLY when the SCL line is low.
DEVICE OPERATION
I2C Bus Background
The ST24/25x01 support the I2C protocol. This
protocol defines any device that sends data onto
the bus as a transmitter and any device that reads
the data as a receiver. The device that controls the
data transfer is known as the master and the other
as the slave. The master will always initiate a data
transfer and will provide the serial clock for syn-
chronisation. The ST24/25x01 are always slave
devices in all communications.
Start Condition. START is identified by a high to
low transition of the SDA line while the clock SCL
is stable in the high state. A START condition must
precede any command for data transfer. Except
during a programming cycle, the ST24/25x01 con-
tinuously monitor the SDA and SCL signals for a
START condition and will not respond unless one
is given.
Memory Addressing. To start communication be-
tween the bus master and the slave ST24/25x01,
the master must initiate a STARTcondition. Follow-
ing this, the master sends onto the SDA bus line 8
bits (MSB first) corresponding to the device select
code (7 bits) and a READ or WRITE bit.
Figure 3. Maximum RL Value versus Bus Capacitance (CBUS) for an I2C Bus
20
V
CC
16
R
R
L
L
12
SDA
C
BUS
MASTER
SCL
8
4
C
BUS
V
= 5V
CC
0
100
200
(pF)
300
400
C
AI01100
BUS
4/16
ST24/25C01, ST24C01R, ST24/25W01
Table 5. Input Parameters (1) (TA = 25 °C, f = 100 kHz )
Symbol
CIN
Parameter
Input Capacitance (SDA)
Test Condition
Min
Max
8
Unit
pF
CIN
Input Capacitance (other pins)
6
pF
ZWCL
ZWCH
WC Input Impedance (ST24/25W01)
WC Input Impedance (ST24/25W01)
V
IN ≤ 0.3 VCC
IN ≥ 0.7 VCC
5
20
kΩ
kΩ
V
500
Low-pass filter input time constant
(SDA and SCL)
tLP
100
ns
Note: 1. Sampled only, not 100% tested.
Table 6. DC Characteristics
(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C; VCC = 3V to 5.5V, 2.5V to 5.5V or 1.8V to 5.5V)
Symbol
Parameter
Test Condition
Min
Max
Unit
ILI
Input Leakage Current
0V ≤ VIN ≤ VCC
±2
µA
0V ≤ VOUT ≤ VCC
ILO
Output Leakage Current
±2
µA
SDA in Hi-Z
V
CC = 5V, fC = 100kHz
Supply Current (ST24 series)
Supply Current (ST25 series)
2
1
mA
mA
µA
(Rise/Fall time < 10ns)
ICC
VCC = 2.5V, fC = 100kHz
VIN = VSS or VCC
VCC = 5V
,
100
Supply Current (Standby)
(ST24 series)
ICC1
ICC2
ICC3
ICC4
V
IN = VSS or VCC
,
300
5
µA
µA
µA
µA
µA
µA
µA
VCC = 5V, fC = 100kHz
VIN = VSS or VCC
CC = 2.5V
,
V
Supply Current (Standby)
(ST25 series)
V
IN = VSS or VCC
,
50
20
60
10
20
VCC = 2.5V, fC = 100kHz
VIN = VSS or VCC
VCC = 3.6V
,
Supply Current (Standby)
(ST24C01R)
V
IN = VSS or VCC
,
VCC = 3.6V, fC = 100kHz
V
IN = VSS or VCC
CC = 1.8V
,
V
Supply Current (Standby)
(ST24C01R)
V
IN = VSS or VCC
,
VCC = 1.8V, fC = 100kHz
VIL
Input Low Voltage (SCL, SDA)
Input High Voltage (SCL, SDA)
–0.3
0.3 VCC
VCC + 1
V
V
VIH
0.7 VCC
Input Low Voltage
(E0-E2, MODE, WC)
VIL
–0.3
0.5
V
V
Input High Voltage
(E0-E2, MODE, WC)
VIH
V
CC – 0.5
VCC + 1
Output Low Voltage (ST24 series)
Output Low Voltage (ST25 series)
IOL = 3mA, VCC = 5V
0.4
0.4
V
V
IOL = 2.1mA, VCC = 2.5V
VOL
Output Low Voltage
(ST24C01R)
IOL = 1mA, VCC = 1.8V
0.3
V
5/16
ST24/25C01, ST24C01R, ST24/25W01
Table 7. AC Characteristics
(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C; VCC = 3V to 5.5V, 2.5V to 5.5V or 1.8V to 5.5V)
Symbol
tCH1CH2
tCL1CL2
tDH1DH2
tDL1DL1
Alt
tR
Parameter
Min
Max
1
Unit
µs
ns
Clock Rise Time
Clock Fall Time
Input Rise Time
Input Fall Time
tF
300
1
tR
µs
ns
tF
300
(1)
tCHDX
tSU:STA
tHIGH
tHD:STA
tHD:DAT
tLOW
tSU:DAT
tSU:STO
tBUF
tAA
Clock High to Input Transition
Clock Pulse Width High
4.7
4
µs
µs
µs
µs
µs
ns
tCHCL
tDLCL
tCLDX
tCLCH
tDXCX
tCHDH
tDHDL
Input Low to Clock Low (START)
Clock Low to Input Transition
Clock Pulse Width Low
4
0
4.7
250
4.7
4.7
0.3
300
Input Transition to Clock Transition
Clock High to Input High (STOP)
Input High to Input Low (Bus Free)
Clock Low to Next Data Out Valid
Data Out Hold Time
µs
µs
µs
ns
(2)
tCLQV
3.5
tCLQX
fC
tDH
fSCL
tWR
Clock Frequency
100
10
kHz
ms
(3)
tW
Write Time
Notes: 1. For a reSTART condition, or following a write cycle.
2. The minimum value delays the falling/rising edge of SDA away from SCL = 1 in order to avoid unwanted START and/or STOP
conditions.
3. In the Multibyte Write mode only, if accessed bytes are on two consecutive 8 bytes rows (6 address MSB are not constant) the
maximum programming time is doubled to 20ms.
AC MEASUREMENT CONDITIONS
DEVICE OPERATION (cont’d)
Input Rise and Fall Times
Input Pulse Voltages
≤ 50ns
0.2VCC to 0.8VCC
The 4 most significant bits of the device select code
are the device type identifier, corresponding to the
I2C bus definition. For these memories the 4 bits
are fixed as 1010b. The following 3 bits identify the
specific memory on the bus. They are matched to
the chip enable signals E2, E1, E0. Thus up to 8 x
1K memories can be connected on the same bus
giving a memory capacity total of 8K bits. After a
START condition any memory on the bus will iden-
tify the device code and compare the following 3
bits to its chip enable inputs E2, E1, E0.
Input and Output Timing Ref. Voltages 0.3VCC to 0.7VCC
Figure 4. AC Testing Input Output Waveforms
0.8V
CC
0.7V
CC
0.3V
CC
The 8th bit sent is the read or write bit (RW), this
bit is set to ’1’ for read and ’0’ for write operations.
If a match is found, the corresponding memory will
acknowledge the identification on the SDA bus
during the 9th bit time.
0.2V
CC
AI00825
6/16
ST24/25C01, ST24C01R, ST24/25W01
Figure 5. AC Waveforms
tCHCL
tDLCL
tCLCH
SCL
tDXCX
tCHDH
SDA IN
tCHDX
tCLDX
SDA
tDHDL
START
CONDITION
SDA
STOP &
BUS FREE
INPUT CHANGE
SCL
tCLQV
tCLQX
DATA VALID
SDA OUT
DATA OUTPUT
tDHDL
SCL
tW
SDA IN
tCHDH
tCHDX
STOP
WRITE CYCLE
START
CONDITION
CONDITION
AI00795
7/16
ST24/25C01, ST24C01R, ST24/25W01
Figure 6. I2C Bus Protocol
SCL
SDA
START
SDA
SDA
STOP
CONDITION
INPUT CHANGE
CONDITION
1
2
3
7
8
9
SCL
SDA
ACK
MSB
START
CONDITION
1
2
3
7
8
9
SCL
SDA
MSB
ACK
STOP
CONDITION
AI00792
Write Operations
For the ST24/25W01 versions, any write command
with WC = 1 (during a period of time from the
START condition untill the end of the Byte Address)
will not modify data and will NOT be acknowledged
on data bytes, as in Figure 9.
The Multibyte Write mode (only available on the
ST24/25C01 and the ST24C01R versions) is se-
lected when the MODE pin is at VIH and the Page
Write mode when MODE pin is at VIL. The MODE
pin may be driven dynamically with CMOS input
levels.
Byte Write. In the Byte Write mode the master
sends one data byte, which isacknowledged by the
memory. The master then terminates the transfer
by generating a STOP condition. The Write mode
is independant of the state of the MODE pin which
could be left floating if only this mode was to be
used. However it is not a recommended operating
mode, as this pin has to be connected to either VIH
or VIL, to minimize the stand-by current.
Following a START condition the master sends a
device select code with the RW bit reset to ’0’. The
memory acknowledges this and waits for a byte
address. The byte address of 7 bits (the Most
Significant Bit is ignored) provides access to any of
the 128 bytes of the memory. After receipt of the
byte address the device again responds with an
acknowledge.
8/16
ST24/25C01, ST24C01R, ST24/25W01
Multibyte Write. For the Multibyte Write mode, the
MODE pin must be at VIH. The Multibyte Write
mode can be started from any address in the
memory. The master sends from one up to 4 bytes
of data, whichare eachacknowledgedbythemem-
ory. The transfer is terminated by the master gen-
erating a STOP condition. The duration of the write
cycle is tW = 10ms maximum except when bytes
are accessed on 2 rows (that is have different
values for the 5 most significant address bits A6-
A2), the programming time is then doubled to a
maximum of 20ms. Writing more than 4bytes in the
Multibyte Write mode may modify data bytes in an
adjacent row (one row is 8 bytes long). However,
the Multibyte Write can properly write up to 8
consecutive bytes only if the first address of these
8bytesisthefirst address ofthe row, the7 following
bytes being written in the 7 following bytes of this
same row.
Page Write. For the Page Write mode, the MODE
pin must be at VIL. The Page Write mode allows up
to 8 bytes to be written in a single write cycle,
provided that they are all located in the same ’row’
in the memory: that is the 5 most significant mem-
ory address bits (A7-A3) are the same. The master
sends from one up to 8 bytes of data, which are
each acknowledged by the memory. After each
byteis transfered,theinternalbyte addresscounter
(3 least significant bits only) is incremented. The
transfer is terminated by the master generating a
STOP condition. Care must be taken to avoid ad-
dress counter ’roll-over’ which could result in data
being overwritten. Note that, for any write mode,
the generationby the masterof the STOP condition
starts the internal memory programcycle. All inputs
are disabled until the completion of this cycle and
the memory will not respond to any request.
Figure 7. Write Cycle Polling using ACK
WRITE Cycle
in Progress
START Condition
DEVICE SELECT
with RW = 0
ACK
Returned
NO
First byte of instruction
with RW = 0 already
decoded by ST24xxx
YES
Next
Operation is
Addressing the
Memory
NO
YES
Send
Byte Address
ReSTART
STOP
Proceed
WRITE Operation
Proceed
Random Address
READ Operation
AI01099B
9/16
ST24/25C01, ST24C01R, ST24/25W01
Figure 8. Write Modes Sequence (ST24/25C01 and ST24C01R)
ACK
ACK
ACK
ACK
BYTE WRITE
DEV SEL
BYTE ADDR
DATA IN
R/W
ACK
BYTE ADDR
ACK
MULTIBYTE
AND
DEV SEL
DATA IN 1
DATA IN 2
PAGE WRITE
R/W
ACK
ACK
DATA IN N
AI00793
Minimizing System Delays by Polling On ACK.
During the internal write cycle, the memory discon-
nects itself from the bus in order to copy the data
from the internal latches to the memory cells. The
maximum value of the write time (tW) is given in
the AC Characteristics table, since the typical time
is shorter, the time seen by the system may be
reduced by an ACK polling sequence issued by the
master. The sequence is as follows:
Read Operations
Read operationsareindependentof the stateofthe
MODE pin. On delivery, the memory content is set
at all "1’s" (or FFh).
Current Address Read. The memory has an inter-
nal byte address counter. Each time a byte is read,
this counter is incremented. For the Current Ad-
dress Read mode, following a START condition,
the master sends a memory address with the RW
bit set to ’1’. The memory acknowledges this and
outputs the byte addressed by the internal byte
address counter. This counter is then incremented.
The master does NOT acknowledge the byte out-
put, but terminates the transfer with a STOP con-
dition.
– Initial condition: a Write is in progress (see Fig-
ure 7).
– Step 1: the Master issues a START condition
followed by a Device Select byte (1st byte of
the new instruction).
– Step 2: if the memory is busy with the internal
write cycle, no ACK will be returned and the
master goes back to Step 1. If the memory
has terminated the internal write cycle, it will
respond with an ACK, indicating that the mem-
ory is ready to receive the second part of the
next instruction (the first byte of this instruc-
tion was already sent during Step 1).
Random Address Read. A dummy write is per-
formed to load the address into the address
counter, see Figure 10. This is followed by another
START condition from the master and the byte
address is repeated with the RW bit set to ’1’. The
memory acknowledges this and outputs the byte
addressed. The master have to NOT acknowledge
the byte output, but terminates the transfer with a
STOP condition.
10/16
ST24/25C01, ST24C01R, ST24/25W01
Figure 9. Write Modes Sequence with Write Control = 1 (ST24/25W01)
WC
ACK
ACK
NO ACK
DATA IN
BYTE WRITE
DEV SEL
BYTE ADDR
R/W
WC
ACK
ACK
NO ACK
PAGE WRITE
DEV SEL
BYTE ADDR
DATA IN 1
DATA IN 2
R/W
WC (cont'd)
NO ACK
NO ACK
PAGE WRITE
(cont'd)
DATA IN N
AI01161B
ically incremented after each byte output. After a
count of the last memory address, the address
counter will ’roll- over’andthememory will continue
to output data.
Acknowledge in Read Mode. In all read modes
theST24/25x01waitforan acknowledgeduringthe
9th bit time. If the master does not pull the SDAline
low during this time, the ST24/25x01 terminate the
data transfer and switches to a standby state.
Sequential Read. This mode can be initiated with
either a Current Address Read or a Random Ad-
dress Read. However, in this case the master
DOES acknowledge the data byte output and the
memory continues to output the next byte in se-
quence. To terminate the stream of bytes, the
master must NOT acknowledge the last byte out-
put, but MUST generate a STOP condition. The
output data is from consecutive byte addresses,
with the internal byte address counter automat-
11/16
ST24/25C01, ST24C01R, ST24/25W01
Figure 10. Read Modes Sequence
ACK
NO ACK
DATA OUT
CURRENT
ADDRESS
READ
DEV SEL
R/W
ACK
ACK
ACK
NO ACK
DATA OUT
RANDOM
ADDRESS
READ
DEV SEL *
BYTE ADDR
DEV SEL *
R/W
R/W
ACK
ACK
ACK
NO ACK
SEQUENTIAL
CURRENT
READ
DEV SEL
DATA OUT 1
DATA OUT N
R/W
ACK
ACK
ACK
ACK
SEQUENTIAL
RANDOM
READ
DEV SEL *
BYTE ADDR
DEV SEL * DATA OUT 1
R/W
R/W
ACK
NO ACK
DATA OUT N
AI00794C
Note:
* The 7 Most Significant bits of DEV SEL bytes of a Random Read (1st byte and 3rd byte) must be identical.
12/16
ST24/25C01, ST24C01R, ST24/25W01
ORDERING INFORMATION SCHEME
Example:
ST24C01
M
1
TR
Operating Voltage
Range
ST24C01
ST24W01
ST25C01
ST25W01
ST24C01R
3V to 5.5V
3V to 5.5V
Standard
Hardware Write Control
2.5V to 5.5V Standard
2.5V to 5.5V Hardware Write Control
1.8V to 5.5V Standard
Package
Temperature Range
Option
B
PSDIP8
1
0 to 70 °C
TR Tape & Reel
Packing
0.25mm Frame
5 * –20 to 85 °C
M
SO8 150mil Width
6
–40 to 85 °C
3 * –40 to 125 °C
Notes: 3 * Temperature range on special request only.
5 * Temperature range for ST24C01R only.
Parts are shipped with the memory content set at all "1’s" (FFh).
For a list of available options (Operating Voltage, Range, Package, etc...) refer to the current Memory
Shortform catalogue.
For further information on any aspect of this device, please contact the SGS-THOMSON Sales Office
nearest to you.
13/16
ST24/25C01, ST24C01R, ST24/25W01
PSDIP8 - 8 pin Plastic Skinny DIP, 0.25mm lead frame
mm
Min
3.90
0.49
3.30
0.36
1.15
0.20
9.20
–
inches
Min
Symb
Typ
Max
5.90
–
Typ
Max
0.232
–
A
A1
A2
B
0.154
0.019
0.130
0.014
0.045
0.008
0.362
–
5.30
0.56
1.65
0.36
9.90
–
0.209
0.022
0.065
0.014
0.390
–
B1
C
D
E
7.62
2.54
0.300
0.100
E1
e1
eA
eB
L
6.00
–
6.70
–
0.236
–
0.264
–
7.80
–
0.307
–
10.00
3.80
0.394
0.150
3.00
8
0.118
8
N
PSDIP8
A2
A
L
A1
e1
B
C
eA
eB
B1
D
N
1
E1
E
PSDIP-a
Drawing is not to scale.
14/16
ST24/25C01, ST24C01R, ST24/25W01
SO8 - 8 lead Plastic Small Outline, 150 mils body width
mm
Min
1.35
0.10
0.33
0.19
4.80
3.80
–
inches
Min
Symb
Typ
Max
1.75
0.25
0.51
0.25
5.00
4.00
–
Typ
Max
0.069
0.010
0.020
0.010
0.197
0.157
–
A
A1
B
0.053
0.004
0.013
0.007
0.189
0.150
–
C
D
E
e
1.27
0.050
H
h
5.80
0.25
0.40
0°
6.20
0.50
0.90
8°
0.228
0.010
0.016
0°
0.244
0.020
0.035
8°
L
α
N
CP
8
8
0.10
0.004
SO8
h x 45˚
C
A
B
CP
e
D
N
1
E
H
A1
α
L
SO-a
Drawing is not to scale.
15/16
ST24/25C01, ST24C01R, ST24/25W01
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express
written approval of SGS-THOMSON Microelectronics.
© 1997 SGS-THOMSON Microelectronics - All Rights Reserved
Purchase of I2C Components by SGS-THOMSON Microelectronics, conveys a license under the Philips
I2C Patent. Rights to use these components in an I2C system, is granted provided that the system conforms to
the I2C Standard Specifications as defined by Philips.
SGS-THOMSON Microelectronics GROUP OF COMPANIES
Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -
Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
16/16
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