ST52E440F3D6 [STMICROELECTRONICS]
8-BIT INTELLIGENT CONTROLLER UNIT ICU Timer/PWM, Analog Comparator, Triac/PWM Timer, WDG; 8 - BIT智能控制单元ICU定时器/ PWM ,模拟比较器,三端双向可控硅/ PWM定时器,看门狗型号: | ST52E440F3D6 |
厂家: | ST |
描述: | 8-BIT INTELLIGENT CONTROLLER UNIT ICU Timer/PWM, Analog Comparator, Triac/PWM Timer, WDG |
文件: | 总94页 (文件大小:1121K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ST52T400/T440/E44S0 T52T400/T440/E440/T441
8-BIT INTELLIGENT CONTROLLER UNIT (ICU)
®
Timer/PWM, Analog Comparator, Triac/PWM Timer, WDG
PRELIMINARY DATASHEET
Memories
■ Up to 8 Kbytes EPROM/OTP
■ 128/256 bytes of RAM
■ Readout Protection
Core
■ Register File Based Architecture
■ 55 instructions
■ Hardware multiplication and division
■ Decision Processor for the implementation of
Fuzzy Logic algorithms
Clock and Power Supply
■ Up to 20 MHz clock frequency.
■ On-chip Power On Reset (POR) and Brown Out
Detector (BOD)
■ Power Saving features
Interrupts
■ 6 interrupt vectors
■ Top Level External Interrupt (INT)
I/O Ports
■ 13 or 21 I/O PINs configurable in Input and
■ 6-channels Analog Comparator with 16-bit
Output mode
Timer (not available in ST52T400)
■ High current sink/source in all pins. Triac Driver
■ Triac/PWM Driver Timer with zero crossing
output can supply 50 mA
detector and high current capability for:
– PWM mode
Peripherals
■ Programmable 8-bit Timer/PWMs with internal
16-bit Prescaler featuring:
– Burst Mode
– Phase Angle Partialization mode
– PWM output
– Input capture
Development tools
■ High level Software tools
– Output compare
– Pulse generator mode
■ Watchdog timer
■ Emulator
■ Low cost Programmer
■ Gang Programmer
Rev. 2.9 - November 2002
1/94
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
ST52T400/T440/E440/T441
ST52T400/T440/E440/T441 Type List
Triac
Driver/
PWM
NVM
(bytes)
RAM
(bytes)
TIMER/
PWM
Analog
Comparator
POR,
BOD
ST52 Device
WDT
Pull up
I/Os
Package
SO20,
PDIP20
ST52T400Fmpy
ST52T400Gmpy
ST52T440Fmpy
ST52T440Gmpy
1/2/4/8K
1/2/4/8K
1/2/4/8K
1/2/4/8K
128/256
128/256
128/256
128/256
13
21
13
21
1
1
No
1
1
Yes
Yes
Yes
SO28,
PDIP28
SO20,
PDIP20
4 ch
Yes
SO28,
PDIP28
Yes
6 ch
4 ch
6 ch
ST52E440F3D6
ST52E440G3D6
8K
8K
256
256
13
21
CDIP20W
CDIP28W
SO20,
PDIP20
ST52T441Fmpy
ST52T441Gmpy
1/2/4/8K
1/2/4/8K
128/256
128/256
13
21
SO28,
PDIP28
1
1
Yes
Yes
No
ST52E441F3D6
ST52E441G3D6
8K
8K
256
256
13
21
CDIP20W
CDIP28W
Note: devices with 1-2K NVM have 128 RAM; devices with 4-8K NVM have 256 RAM
COMMON FEATURES
Temperature Range
Operating Supply
CPU Frequency
ST52T400
-40 to + 85 °C
2.7 to 5.5 V
ST52x440/ST52x441
-40 to + 85 °C
4.5 to 5.5 V
Up to 20 MHz
Up to 20 MHz
Legend:
Sales code:
ST52tnnncmpy
Memory type (t):
Subfamily (nnn):
Pin Count (c):
F=FLASH, T=OTP, E=EPROM
400, 410, 420, 430, 440, 441
Y=16 pins, F=20 pins, G=28 pins, K=32/34 pins, J=42/44 pins
0=1 Kb, 1=2 Kb, 2=4 Kb, 3=8 Kb
Memory Size (m):
Packages (p):
B=PDIP, D=CDIP, M=PSO, T=TQFP
Temperature (y):
0=+25, 1=0 +70, 3=-40 +125, 5=-10 +85, 6=-40 +85, 7=-40 +105
2/94
TABLE OF CONTENTS
ST52T400/T440/E440/T441
TABLE OF CONTENTS
1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
1.2 Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
1.2.1 Memory Programming Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.2.2 Working Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.3 Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
2 INTERNAL ARCHITECTURE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.1 Control Unit and Data Processing Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
2.1.1 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.1.2 Flags. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.2 Address Spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
2.2.1 Ram and Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.2.2 Input Registers Bench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.2.3 Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.2.4 Output Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.3 Fuzzy Computation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
2.3.1 Fuzzy Inference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.3.2 Fuzzyfication Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.3.3 Inference Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.3.4 Defuzzyfication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.3.5 Input Membership Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.3.6 Output Singleton. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.3.7 Fuzzy Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.4 Arithmetic Logic Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
2.4.1 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.4.2 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3 EPROM Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.1 EPROM Programming Phase Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
3.1.1 EPROM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.1.2 EPROM Locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.1.3 EPROM Writing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.1.4 EPROM Reading/Verify Margin Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.1.5 Stand by Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.1.6 ID code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.2 Eprom Erasure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
4 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.1 Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
4.2 Global Interrupt Request Enabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
4.3 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
4.4 Interrupt Maskability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
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ST52T400/T440/E440/T441
4.5 Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
4.6 Interrupts and Low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
4.7 Interrupt RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
5 CLOCK, RESET & POWER SAVING MODE. . . . . . . . . . . . . . . . . . . . . . . . . . 42
5.1 Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
5.2 Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
5.2.1 External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.2.2 Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.2.3 Power-on Reset (POR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.2.4 Brown-Out Detector (BOD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.3 Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
5.3.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.3.2 Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
6.2 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
6.3 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
6.4 Alternate Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
6.5 I/O Port Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
7 ANALOG COMPARATOR (ST52x440/441). . . . . . . . . . . . . . . . . . . . . . . . . . . 50
7.1 Analog Module Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
7.2 Comparator Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
7.3 A/D Converter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
7.3.1 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
8 WATCHDOG TIMER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
8.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
8.2 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
9 PWM/TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
9.1 Timer Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
9.2 PWM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
9.3 Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
10TRIAC/PWM DRIVER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
10.1 TRIAC/PWM Driver Setting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
10.2 PWM Mode Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
10.3 Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
10.4 Phase Angle Partialization Working Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
11 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
11.1 Parameter Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
11.1.1 Minimum and Maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
11.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
11.1.3 Typical curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
11.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
11.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
11.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
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TABLE OF CONTENTS
11.3 Recommended Operating Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
11.4 Supply Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
11.5 Brown-Out Detector characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
11.6 Clock and Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
11.7 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
11.8 ESD Pin Protection Strategy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
11.8.1 Standard Pin Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
11.9 Port Pin Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
11.9.1 General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
11.10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
11.11Control Pin Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
11.11.1 RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
11.11.2 Power on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
11.11.3 VPP pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
11.12 Analog Comparator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
11.13 Triac Driver Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
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ST52T400/T440/E440/T441
1 GENERAL DESCRIPTION
or external START/STOP signals and clock.
An internal programmable WATCHDOG is avail-
able to avoid loop errors and to reset the ICU.
An Analog Comparator with a 6 channel multi-
plexer is available on ST52x440/441 family
devices. This analog peripheral allows easy imple-
mentation of a high resolution A/D conversion. By
using only an external capacitor this peripheral
may be configured in order to achieve up to 12 bit
A/D converter resolution. It includes a 2.5 V band-
gap reference for A/D conversion calibration,
which can be used externally for signal condition-
ing.
An on-chip TRIAC driver peripheral allows the
direct management of power devices, implement-
ing two different operating modes: Burst Mode
(i.e. Thermal Applications), Phase Angle Partial-
ization (i.e. Motors Control by Triacs). The TRIAC
Driver also generates a PWM signal.
1.1 Introduction
ST52x400/440/441 are 8-bit Intelligent Control
Units (ICU) of the ST Five Family, which are able
to perform both boolean and fuzzy algorithms in
an efficient manner, in order to reach the best per-
formances that the two methodologies allow.
ST52x400/440/441 is produced by STMicroelec-
tronics using the reliable high performance CMOS
process, including integrated-on-chip peripherals
that allow maximization of system reliability,
decreasing system costs and minimizing the
number of external components.
The flexible I/O configuration of ST52x400/440/
441 allows for an interface with a wide range of
external devices, like D/A converters or power
control devices.
ST52x400/440/441 pins are configurable, allowing
the user to set the input or output signals on each
single pin.
A hardware multiplier (8 bit by 8 bit with 16 bit
result) and divider (16 bit over 8 bit with 8 bit
result and 8 bit remainder) is available to imple-
ment complex functions by using a single instruc-
tion, optimizing program memory utilization and
computational speed.
Fuzzy Logic dedicated structures in ST52x400/
440/441 ICU’s can be exploited to model complex
sys
tems with high accuracy in a useful and easy way.
Fuzzy Expert Systems for overall system manage-
ment and fuzzy Real time Controls can be
designed to increase performances at highly com-
petitive costs.
The linguistic approach characterizing Fuzzy
Logic is based on a set of IF-THEN rules, which
describe the control behavior, as well as on Mem-
bership Functions, which are associated to input
and output variables.
The ST52x400/440/441 family also includes an
on-chip Power-on-Reset (POR), which provides
an internal chip reset during power up situation
and a Brown-Out Detector (BOD), which resets
the ICU if the voltage source V
dips below
a
DD
minimum value.
In order to optimize energy consumption, two dif-
ferent power saving modes are available: Wait
mode and Halt mode.
Program Memory (EPROM/OTP) addressing
capability addresses up to 8 Kbytes of memory
locations to store both program instructions and
permanent data.
EPROM can be locked by the user to prevent
external undesired operations.
Operations may be performed on data stored in
RAM, allowing the direct combination of new input
and feedback data. All bytes of RAM are used like
Register File.
OTP (One Time Programmable) version devices
are fully compatible with the EPROM windowed
version, which may be used for prototyping and
pre-production phases of development.
A powerful development environment consisting
of a board and software tools allows an easy con-
Up to 334 Membership Functions, with triangular
and trapezoidal shapes, or singleton values are
available to describe fuzzy variables.
The TIMER/PWM peripheral allows the manage-
ment of power devices and timing signals, imple-
menting different operating modes and high
frequency PWM (Pulse With Modulation) controls.
Input Capture and Output Compare functions are
available on the TIMER.
figuration and use of ST52x400/440/441.
TM
The VISUAL FIVE
software tool allows devel-
opment of projects through a user-friendly graphi-
cal interface and optimization of generated code.
The programmable Timer has a 16 bit Internal
Prescaler and an 8 bit Counter. It can use internal
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ST52T400/T440/E440/T441
1.2 Operational Description
ST52x400/440/441 ICU can work in two modes:
Table 1.1 Control Signals Setting
■ Memory Programming Phase
Control
Signal
Pro-
gramming
Reset
Working
■ Working Phase
according to RESET and Vpp signals levels (see
pins description) .
Note: When RESET=0 it is advisable not to use
the sequence “101010“ to port PA ( 7 : 2 ).
RESET
Vpp
0
0
0
1
0
5V /12V
1.2.1 Memory Programming Phase.
The ST52x400/440/441 memory is loaded in the
Memory Programming Phase. All fuzzy and stan-
dard instructions are written inside the memory.
This phase starts by setting the control signals as
illustrated in (see Table 1.1).
When this phase starts, the ST52x400/440/441
core is set to RESET status; then 12V are
applied to the Vpp pin in order to start EPROM
programming. A signal applied to PB1 is used to
increment the memory address; the data is sup-
plied to PORT A (see EPROM programming for
further details).
1.2.2 Working Mode.
The processor starts the working phase following
the instructions, which have been previously
loaded in the memory.
ST52x400/440/441’s internal structure includes a
computational block, CONTROL UNIT (CU)/DATA
PROCESSING UNIT (DPU), which allows pro-
cessing of boolean functions and fuzzy algo-
rithms.
The CU/DPU can manage up to 334 different
Membership Functions for the fuzzy rules ante-
cedent part. The rule consequents are “crisp” val-
ues (real numbers). The maximum number of
rules that can be defined is limited by the dimen-
sions of the implemented standard algorithm.
EPROM is then shared between fuzzy and stan-
dard algorithms. The Membership Function data is
stored inside the first 1024 memory locations. The
Fuzzy rules are parts of the program instructions.
The Control Unit (CU) reads the information and
the status deriving from the peripherals.
Arithmetic calculus can be performed on these
values by using the internal CU and the 128/256
bytes of RAM, which supports all computations.
The peripheral input can be fuzzy and/or arith-
metic output, or the values contained in Data RAM
and EPROM locations.
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ST52T400/T440/E440/T441
Figure 1.1 ST52x400/440/441 Block Diagram
MAIN1
MAIN2
I/O PORT
ANALOG
COMPARATOR
TRIAC DRIVER
TROUT
USER PROGRAM
EPROM
8 KBytes
WATCHDOG
TIMER/PWM
CONTROL
INT
TSTRT
TRES
TCLK
UNIT
PC
CU Input
Registers
TOUT
256 Bytes
RAM
TOUTN
ALU &
DECISION
PROCESSOR
POWER SUPPLY and BOD
OSCILLATOR
PowerOnReset
RESET
VDD
VPP
VSS
OSCIN
OSCOUT
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ST52T400/T440/E440/T441
Figure 1.2 ST52x400 SO28 Pin Configuration
OSCOUT
Vdd
1
28
27
26
25
24
23
22
21
20
19
OSCIN
Vss
2
Vpp
RESET
3
4
PC0
PC4
PC3
PB7
PB6
PB5
PB4
PB3
PC1
5
6
PC2
7
PA7/INT
PA6/TRES/TOUT
PA5/TCLK
PA4/TSTRT
PA3
8
9
10
11
12
13
18
17
16
PB2
PB1
PB0
Vss
PA2/MAIN2/TOUTN
PA1/MAIN1
PA0/TROUT
14
15
Figure 1.3 ST52x400 PDIP28 Pin Configuration
OSCOUT
1
28
27
26
25
24
23
22
21
20
19
18
Vdd
OSCIN
Vpp
2
Vss
3
RESET
PC4
PC3
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
Vss
4
PC0
5
PC1
6
PC2
7
PA7/INT
PA6/TRES/TOUT
PA5/TCLK
PA4/TSTRT
PA3
8
9
10
11
12
13
17
16
PA2/MAIN2/TOUTN
PA1/MAIN1
PA0/TROUT
14
15
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ST52T400/T440/E440/T441
Figure 1.4 ST52x400 SO20 Pin Configuration
Figure 1.5 ST52x400 PDIP20 Pin Configuration
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ST52T400/T440/E440/T441
Figure 1.6 ST52x440/441 SO28 Pin Configuration
OSCOUT
Vdd
1
28
27
26
25
24
23
22
21
20
19
OSCIN
Vss
2
Vpp
RESET
3
PC4
PC0
4
PC3
PC1
5
PB7/CS
PB6/BG
PB5/AC5
PB4/AC4
PB3/AC3
PB2/AC2
PB1/AC1
PB0/AC0
GNDA
6
PC2
7
PA7/INT/ACSYNC
PA6/TRES/TOUT
PA5/TCLK
PA4/TSTRT
PA3/ACSTRT
PA2/MAIN2/TOUTN
PA1/MAIN1
PA0/TROUT
8
9
10
11
12
13
14
18
17
16
15
Figure 1.7 ST52x440/441 PDIP28 Pin Configuration
OSCOUT
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vdd
OSCIN
Vpp
2
Vss
3
RESET
PC4
PC3
4
PC0
5
PC1
PB7/CS
PB6/BG
PB5/AC5
PB4/AC4
PB3/AC3
PB2/AC2
PB1/AC1
PB0/AC0
GNDA
6
PC2
7
PA7/INT/ACSYNC
PA6/TRES/TOUT
PA5/TCLK
PA4/TSTRT
PA3/ACSTRT
PA2/MAIN2/TOUTN
PA1/MAIN1
PA0/TROUT
8
9
10
11
12
13
14
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ST52T400/T440/E440/T441
Figure 1.8 ST52x440/441 SO20 Pin Configuration
Figure 1.9 ST52x440/441 PDIP20 Pin Configuration
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ST52T400/T440/E440/T441
Table 1.2 SO28 and DIP28 Pin Configuration - ST52x400
PIN SO28/DIP28
NAME
OSCOUT
OSCIN
Programming Phase
Working Phase
Oscillator Output
Oscillator Input
1
2
EPROM Programming
Power supply (12V±5%)
EPROM V or Vss
3
Vpp
DD
4
5
6
7
8
9
PC4
PC3
PB7
PB6
PB5
PB4
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
PHASE signal (PHASE)
Configuration INCREMENT
(INC_CONF)
10
11
12
13
PB3
PB2
PB1
PB0
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Configuration RESET
(RST_CONF)
Address INCREMENT
(INC_ADD)
Address Reset
(RST_ADD)
14
15
Vss
This pin must be tied to Digital Ground
Digital I/O - TRIAC Driver Output
PA0/TROUT
I/O EPROM Data
I/O EPROM Data
Digital I/O
Zero Crossing Detection pin 1
16
PA1/MAIN1
Digital I/O
Zero Crossing Detection pin 2
Complementary Timer Output
PA2/MAIN2/
TOUTN
17
I/O EPROM Data
18
19
20
PA3
I/O EPROM Data
I/O EPROM Data
I/O EPROM Data
Digital I/O
PA4/TSTRT
PA5/TCLK
Digital I/O - Timer external start
Digital I/O - Timer external clock
Digital I/O
Timer external reset - Timer output
21
22
PA6/TRES/TOUT
PA7/INT
I/O EPROM Data
I/O EPROM Data
Digital I/O
External Interrupt
23
24
25
26
27
28
PC2
PC1
Digital I/O
Digital I/O
PC0
Digital I/O
RESET
General Reset
Digital Ground
General Reset
Digital Ground
Digital Power Supply
V
SS
DD
V
Digital Power Supply
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ST52T400/T440/E440/T441
Table 1.3 SO20 and DIP20 Pin Configuration - ST52x400
PIN SO20/DIP20
NAME
Programming Phase
Working Phase
Digital Power Supply
Oscillator Output
Oscillator Input
1
2
3
V
Digital Power Supply
DD
OSCOUT
OSCIN
EPROM Programming
Power supply (12V±5%)
EPROM V or Vss
4
Vpp
DD
5
6
PB7
PB3
PHASE signal (PHASE)
Digital I/O
Digital I/O
Configuration INCREMENT
(INC_CONF)
Configuration RESET
(RST_CONF)
7
8
9
PB2
PB1
PB0
Digital I/O
Digital I/O
Digital I/O
Address INCREMENT
(INC_ADD)
Address Reset
(RST_ADD)
10
11
Vss
This pin must be tied to Digital Ground
Digital I/O - TRIAC Driver Output
PA0/TROUT
I/O EPROM Data
I/O EPROM Data
Digital I/O
Zero Crossing Detection pin 1
12
PA1/MAIN1
Digital I/O
Zero Crossing Detection pin 2
Complementary Timer Output
PA2/MAIN2/
TOUTN
13
I/O EPROM Data
14
15
16
PA3
I/O EPROM Data
I/O EPROM Data
I/O EPROM Data
Digital I/O
PA4/TSTRT
PA5/TCLK
Digital I/O - Timer external start
Digital I/O - Timer external clock
Digital I/O
Timer external reset - Timer output
17
18
PA6/TRES/TOUT
I/O EPROM Data
I/O EPROM Data
Digital I/O
External Interrupt
PA7/INT
RESET
19
20
General Reset
Digital Ground
General Reset
Digital Ground
V
SS
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ST52T400/T440/E440/T441
Table 1.4 SO28 and DIP28 Pin Configuration - ST52x440/441
PIN SO28/DIP28
NAME
OSCOUT
OSCIN
Programming Phase
Working Phase
Oscillator Output
Oscillator Input
1
2
EPROM Programming
Power supply (12V±5%)
EPROM V or Vss
3
Vpp
DD
4
5
6
7
PC4
PC3
Digital I/O
Digital I/O
PB7/CS
PB6/BG
PHASE signal (PHASE)
Digital I/O - Capacitor connection
Digital I/O - Bandgap reference
Digital I/O
Analog Comparator Channel 5
8
PB5/AC5
PB4/AC4
PB3/AC3
PB2/AC2
PB1/AC1
PB0/AC0
Digital I/O
Analog Comparator Channel 4
9
Configuration INCREMENT
(INC_CONF)
Digital I/O
Analog Comparator Channel 3
10
11
12
13
Configuration RESET
(RST_CONF)
Digital I/O
Analog Comparator Channel 2
Address INCREMENT
(INC_ADD)
Digital I/O
Analog Comparator Channel 1
Address Reset
(RST_ADD)
Digital I/O
Analog Comparator Channel 0
14
15
GNDA
Analog Ground
Analog Ground
PA0/TROUT
I/O EPROM Data
Digital I/O - TRIAC Driver Output
Digital I/O
Zero Crossing Detection pin 1
16
17
18
PA1/MAIN1
I/O EPROM Data
I/O EPROM Data
I/O EPROM Data
PA2/MAIN2/
TOUTN
Digital I/O
Zero Crossing Detection pin 2
Digital I/O
Analog Comp. counter external start
PA3/ACSTRT
19
20
PA4/TSTRT
PA5/TCLK
I/O EPROM Data
I/O EPROM Data
Digital I/O - Timer external start
Digital I/O - Timer external clock
Digital I/O
Timer external reset - Timer output
21
22
PA6/TRES/TOUT
I/O EPROM Data
I/O EPROM Data
PA7/INT/
ACSYNC
Digital I/O - External Interrupt
Analog Comparator counter ready
23
24
25
26
27
28
PC2
PC1
Digital I/O
Digital I/O
PC0
Digital I/O
RESET
General Reset
Digital Ground
General Reset
Digital Ground
Digital Power Supply
V
SS
DD
V
Digital Power Supply
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ST52T400/T440/E440/T441
Table 1.5 SO20 and DIP20 Pin Configuration - ST52x440/441
PIN SO20/DIP20
NAME
Programming Phase
Working Phase
Digital Power Supply
Oscillator Output
Oscillator Input
1
2
3
V
Digital Power Supply
DD
OSCOUT
OSCIN
EPROM Programming
Power supply (12V±5%)
EPROM V or Vss
4
Vpp
DD
5
6
PB7/CS
PHASE signal (PHASE)
Digital I/O - Capacitor connection
Configuration INCREMENT
(INC_CONF)
Digital I/O
Analog Comparator Channel 3
PB3/AC3
Configuration RESET
(RST_CONF)
Digital I/O
Analog Comparator Channel 2
7
8
9
PB2/AC2
PB1/AC1
PB0/AC0
Address INCREMENT
(INC_ADD)
Digital I/O
Analog Comparator Channel 1
Address Reset
(RST_ADD)
Digital I/O
Analog Comparator Channel 0
10
11
GNDA
Analog Ground
Analog Ground
PA0/TROUT
I/O EPROM Data
Digital I/O - TRIAC Driver Output
Digital I/O
Zero Crossing Detection pin 1
12
13
14
PA1/MAIN1
I/O EPROM Data
I/O EPROM Data
I/O EPROM Data
Digital I/O
Zero Crossing Detection pin 2
Complementary Timer Output
PA2/MAIN2/
TOUTN
Digital I/O
Analog Comp. counter external start
PA3/ACSTRT
15
16
PA4/TSTRT
PA5/TCLK
I/O EPROM Data
I/O EPROM Data
Digital I/O - Timer external start
Digital I/O - Timer external clock
Digital I/O
Timer external reset - Timer output
17
18
PA6/TRES/TOUT
I/O EPROM Data
I/O EPROM Data
PA7/INT/
ACSYNC
Digital I/O - External Interrupt
Analog Comparator counter ready
19
20
RESET
General Reset
Digital Ground
General Reset
Digital Ground
V
SS
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ST52T400/T440/E440/T441
1.3 Pin Description
ACSTRT, ACSYNC(*). These pins are used to
synchronize the 16-bit counter of the Analog Com-
parator with an external ramp generator. The
ACSTRT input is used to start the counter. The
ACSYNC output is set when the counter is ready
to start a new count.
ST52x400/440/441 pins can be set in digital input
mode, digital output mode or in Alternate Func-
tions. The pin configuration is achieved by means
of the configuration registers. The functions of the
ST52x400/440/441 pins are described below:
V
Main Power Supply Voltage (5V ± 10%).
DD.
BG(*). A Bandgap Reference value of 2.5V is
available on this pin. It can be used for analog sig-
nal conditioning.
V
. Digital circuit Ground. All Vss pins must be
SS
connected to ground (see ST52T400 pin-out).
TOUT, TOUTN.These pins output the signal gen-
erated by the TIMER peripheral. The T0OUTN
signal is the complement of the T0OUT one.
GNDA. Analog circuit ground of the Analog Com-
parator. Must be tied to V
.
SS
V
. Main Power Supply for internal EPROM pro-
PP
TRES, TSTRT, TCLK . These pins are related to
the TIMER peripheral and are used for Input Cap-
ture and event counting. The TRES pin is used to
set/reset the Timer; the TSTRT pin is used to start/
stop the counter. The Timer can be driven by the
internal clock or by an external signal connected
to the TCLK pin.
gramming and MODE selector. During the Pro-
gramming phase V must be set at 12V. In the
PP
Working phase V must be equal to V
.
PP
SS
OSCin and OSCout. These pins are internally
connected to the on-chip oscillator circuit. A quartz
crystal or a ceramic resonator can be connected
between these two pins in order to allow the cor-
rect operations of ST52x400/440/441 with various
stability/cost trade-offs. An external clock signal
can be applied to OSCin: in this case OSCout
must be grounded.
TROUT, MAIN1, MAIN2. These pins are related to
the TRIAC DRIVER peripheral. TROUT outputs
the signal generated by the peripheral. In order to
drive a TRIAC directly without the use of addi-
tional components, the TROUT pin can supply up
to 50 mA (2V voltage drop). MAIN1 and MAIN2
pins are used to detect the zero crossing of the
Power Line voltage.
RESET. This signal is used to reset the
ST52x400/440/441 and re-initialize the registers
and control signals. It also allows the user to
select the working mode of the device.
(*) Not available in ST52x400 devices
PA0-PA7, PB0-PB7,PC0-PC4. These lines are
organized as I/O ports. Each pin can be config-
ured as an input or output. During the Program-
ming phase the ports are used for EPROM data
read/write operations.
AC0-AC5(*). These pins are used to input the
analog signals to the Analog Comparator. An ana-
log multiplexer is available to switch these inputs
to the Analog Comparator.
CS(*). This pin outputs the current generated in
the Analog Comparator peripheral by a current
generator, allowing charging of an external capac-
itor to obtain a voltage ramp for the A/D conver-
sion.
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ST52T400/T440/E440/T441
2 INTERNAL ARCHITECTURE
ST52x400/440/441 is composed of the following
blocks and peripherals:
parts of the CU in order to have only one part of
the system activated during working mode.
The CU structure is highly flexible, designed with
the objective of easily adapting the core of the
microcontroller to market needs. New instructions
sets or new peripherals can be easily included
without changing the structure of the microcontrol-
ler, maintaining code compatibility.
■ Control Unit (CU)
■ Data Processing Unit (DPU)
■ ALU
■ Decision Processor (DP)
■ EPROM
The CU reads and decodifies the instructions
stored on the EPROM (Fetch). According to the
instructions type, the Arbiter activates one of the
main blocks of the CU. Afterwards, all the control
signals for the DPU are generated.
A set of 55 different arithmetic, DP and logic
instructions is available. The arithmetic instruc-
tions operate to all the RAM addresses without the
need of using special registers.
■ 256 Byte RAM
■ Clock Oscillator
■ Analog Multiplexer and Analog Comparator
■ 1 PWM / Timer
■ 1 Triac/PWM Driver
■ Digital I/O port
2.1 Control Unit and Data Processing Unit
The Control Unit (CU) formally includes five main
The DPU receives, stores and sends the instruc-
tions coming from the EPROM, RAM or from the
peripherals in order to execute them.
blocks. Each block decodes a set of instructions,
generating the appropriate control signals. The
main parts of the CU are shown in Figure 2.1.
The five different parts of the CU manage Load-
ing, Logic/Arithmetic, Jump, Control and Decision
Processor (DP) instructions sets.
The block called “Collector” manages the signals
deriving from the different parts of the CU then
defines the signals for the Data Processing Unit
(DPU) and for the different peripherals of the ICU.
The block called “Arbiter” manages the different
2.1.1 Program Counter.
The Program Counter (PC) is a 13-bit register that
contains the address of the next memory location
to be processed by the core. This memory loca-
tion may be an opcode, an operand or an address
of an operand.
Figure 2.1 CU Block Diagram
MicroCode
Loading
Instruction Set
C
O
L
Logic Arithmetic
Instruction Set
A
R
B
L
I
T
E
Jump
Instruction Set
E
C
T
Control
Signals
R
O
R
Control
Instruction Set
Decision Processor
Clock Master
Instruction Set
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ST52T400/T440/E440/T441
Figure 2.2 Data Processing Unit (DPU)
CU
PROGRAM COUNTER
add_EPR
EPROM
INPUTS
PERIPHERALS
M
U
X
PERIPHERALS
RAM
128 Bytes
ADDRESS RAM
STACK POINT
REGISTERS
MULTIPLEXER
ACCUMULATOR
FLAGS REG.
ALU
Figure 2.3 CU/DPU Block Diagram
R A M D a ta 8 B it
R A M A d d r.
8 B it
R A M
R A M
D a ta O u t
8 B it
E
P
R
O
M
D
P
U
T o P e rip h e ra ls
C
U
M ic ro c o d e
F ro m
P e rip h e ra ls
C o n tro l S ig n a ls
E P R O M A d d re s s
20/94
ST52T400/T440/E440/T441
The 13-bit length allows the direct addressing of
8192 bytes in the program space: jump and call
instruction support the absolute addressing in all
the memory.
ing.
These flags are restored from the Flag Stack auto-
matically when a RETI instruction is executed.
If the ICU was in the normal mode before an inter-
rupt, after the RETI instruction is executed, the
normal flags are restored.
Note: A CALL subroutine is a normal mode exe-
cution. For this reason a RET instruction, conse-
quent to a CALL instruction, doesn’t affect the
normal mode set of flags.
Flags are not cleared during context switching and
remain in the state they were located in at the end
of the last interrupt routine switching.
The Carry flag is set when an overflow occurs dur-
ing arithmetic operations, otherwise it is cleared.
The Sign flag is set when an underflow occurs
during arithmetic operations, otherwise it is
cleared.
After having read the current instruction address,
the PC value is incremented. The result of this
operation is shifted back into the PC.
The PC can be changed in the following ways:
■ JP (Jump) instruction PC = Jump Address
■ Interrupt
PC = Interrupt Vector
PC = Pop (stack)
PC = Reset Vector
PC = PC + 1
■ RETI instruction
■ Reset
■ Normal Instruction
2.1.2 Flags.
The ST52x400/440/441 core includes different
sets of flags that correspond to 2 different modes:
normal mode and interrupt mode. Each set of
flags consist of a CARRY flag (C), ZERO flag (Z)
and SIGN flag (S). One set of flags (CN, ZN, SN)
is used during normal operation and one is used
during interrupt mode (CI, ZI, SI). Formally, the
user has to manage only one set of flags: C, Z and
S.
The ST52x400/440/441 core uses the flags that
correspond to the actual mode: as soon as an
interrupt is generated, the ST FIVE core uses the
interrupt flags instead of the normal flags.
2.2 Address Spaces
ST52x400/440/441 has four separate address
spaces:
■ RAM: 128 or 256 Bytes
■ 20 Input Registers
■ 6 Output Registers
■ 21 Configuration Registers
■ Program memory: up to 8K Bytes
The Program Memory will be described in further
details in the EPROM section
Each interrupt level has its own set of flags, which
is saved in the Flag Stack during interrupt servic-
Figure 2.4 Address Spaces Description
ST FIVE CORE
PROGRAM MEMORY
ON CHIP PERIPHERALS
DATA RAM
OUTPUT
REGISTER
NON VOLATILE MEMORY
LDFR
DP
REGISTERS
LDPR
PERIPHERAL
BLOCK
LDRE
PROGRAM
COUNTER
PERIPHERAL
BLOCK
CONFIGURATION
REGISTERS
INPUT REGISTERS
LDCR
LDRI
CU
DPU
ALU
PERIPHERAL
BLOCK
LDCE
LDPE
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ST52T400/T440/E440/T441
2.2.1 Ram and Stack.
2.2.2 Input Registers Bench.
RAM consists of 128 (G0/G1/F0/F1 types) or 256
(G2/G3/F2/F3 types) general purpose 8-bit regis-
ters.
The Input Registers (IR) bench consists of 20 8-bit
registers containing data deriving from the periph-
erals and parallel ports.
All the registers in RAM can be specified by using
a decimal address, e.g. 0 identifies the first regis-
ter of RAM.
All the registers can be specified by using a deci-
mal address, e.g. 0 identifies the first register of
the IR.
To read or write in the RAM registers, the LOAD
instructions must be used (see Table 2.5).
When the instructions like Interrupt request or
CALL are executed, a STACK is used to push the
PC. The STACK is push directly in the RAM. For
each level of stack 2 bytes of RAM are used. The
values of this stack are stored from the last RAM
register (address 255). The maximum level of
stack must be less than 128. When a subroutine
call or interrupt request occurs, the contents of
each level is shifted into the next level while the
content of the PC is shifted into the first level.
When a subroutine or interrupt return occurs (RET
or RETI instructions), the first level register is
shifted back into the PC and the value of each
level is popped back into the previous level. These
operating modes are illustrated in Figure 2.5.
The assembler instruction: LDRI reg,inp_teg loads
the value in the inp IR to the register (RAM loca-
tion) identified by the address reg.
The first input register is dedicated to store the
value of the stack pointer. The next 12 registers of
the IR are dedicated to the 6 (for ST52X440G/
441G) or the 4 converted values (for ST52X440F/
441F) in case of converted values coming from
the Analog Comparator (in ST52x400 devices
these registers are not used). Each of these val-
ues are stored on two bytes because of the reso-
lution of the A/D conversion process. The last 7
registers contain data from the I/O ports and
PWM/Timers. Table 2.1 summarizes the IR
address and the relative peripheral. In order to
simplify the concept
a mnemonic name is
assigned to the registers. The same name is used
in VISUAL FIVE development tools.
Figure 2.5 Stack Operation
PROGRAM COUNTER
RAM
REG 0
REG 1
REG 2
REG 3
REG 4
REG 5
WHEN CALL OR
INTERRUPT REQ.
OCCURS
WHEN RETI OR RET
OCCURS
Stack
Pointer
STACK LEVEL n
..........................
STACK LEVEL 2
STACK LEVEL 1
REG 252
REG 253
REG 254
REG 255
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ST52T400/T440/E440/T441
2.2.3 Configuration Registers.
2.2.4 Output Registers.
The ST52x400/440/441 Configuration Registers
allow the configuration of all the blocks of the ICU.
Table 2.2 describes the functions and the related
peripherals of the 21 Configuration Registers
available: in order to simplify the concept a mne-
monic name is assigned to each Configuration
The Output Registers (OR) consist of 6 registers
containing data for the ICU peripherals including I/
O Ports.
All registers can be specified by using a decimal
address, e.g. 1 identifies the second OR.
By using the LOAD type instructions the Output
Registers (OR) may be set with values stored in
the Program Memory (LDPE) or in the RAM
(LDPR).
The assembler instruction LDPE out,mem loads
the Output Register out with the contents of mem-
ory location mem, inside the currently set memory
page. The assembler instruction LDPR out,reg
loads the Output Register out with the contents of
register (RAM location) reg.
Register. The same name is used in VISUAL
TM
FIVE
development tools. By using the load
instructions the Configuration Registers may be
set by using values stored in the Program Memory
(EPROM) or in the RAM.
The assembler instruction LDCE conf,mem loads
the Configuration Register conf with the contents
of memory location mem, inside the currently set
memory page.
Table 2.3 describes the OR: in order to simplify the
concept a mnemonic name is assigned to each of
the Output Registers. The same name is used in
The assembler instructions LDCR conf,reg loads
the Configuration Register conf with the contents
of the register (RAM location) reg.
Use and meaning of each register will be
described in further details in the corresponding
section.
TM
VISUAL FIVE
development tools. Use and
meaning of each register will be described in fur-
ther details in the corresponding section.
Table 2.1 Input Registers
IR MNEMONIC NAME
STACK_POINTER
AC_CHAN0H(*)
AC_CHAN0L(*)
AC_CHAN1H(*)
AC_CHAN1L(*)
AC_CHAN2H(*)
AC_CHAN2L(*)
AC_CHAN3H(*)
AC_CHAN3L(*)
AC_CHAN4H (*)(**)
AC_CHAN4L (*)(**)
AC_CHAN5H (*)(**)
AC_CHAN5L (*)(**)
AC_STATUS(*)
PORT_A
PERIPHERAL REGISTER
ADDRESS
STACK POINTER
0
1
Analog Comparator CHANNEL 0 High Byte
Analog Comparator CHANNEL 0 Low Byte
Analog Comparator CHANNEL 1 High Byte
Analog Comparator CHANNEL 1 Low Byte
Analog Comparator CHANNEL 2 High Byte
Analog Comparator CHANNEL 2 Low Byte
Analog Comparator CHANNEL 3 High Byte
Analog Comparator CHANNEL 3 Low Byte
Analog Comparator CHANNEL 4 High Byte
Analog Comparator CHANNEL 4 Low Byte
Analog Comparator CHANNEL 5 High Byte
Analog Comparator CHANNEL 5 Low Byte
Analog Comparator Status Register
PORT A INPUT REGISTER
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
PORT_B
PORT B INPUT REGISTER
PORT_C (**)
PORT C INPUT REGISTER
TRIAC_COUNT
PWM_COUNT
TRIAC DRIVER COUNTER Value
PWM/TIMER COUNTER Value
PWM_STATUS
TIMER STATUS REGISTER
(*) Not used on ST52x400xx versions
(**) Not used on ST52x400F/440F441F versions
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ST52T400/T440/E440/T441
Table 2.2 Configuration Registers Description
CONFIGURATION REGISTER
REG_CONF 0
PERIPHERAL
INTERRUPT MASK
ANALOG COMPARATOR
WATCHDOG TIMER
ANALOG COMPARATOR
PORT A
DESCRIPTION
Interrupts mask setting, Polarity, Brown Out
AC Configuration Register 1
REG_CONF 1(*)
REG_CONF 2
Watchdog Timer Configuration
AC Configuration Register 2
REG_CONF 3(*)
REG_CONF 4
PORT A digital pin I/O direction
PWM/TIMER Working mode Configuration
REG_CONF 5
PWM/TIMER
PWM/TIMER Prescaler configuration and
output waveform selection.
REG_CONF 6
PWM/TIMER
REG_CONF 7
REG_CONF 8
PWM/TIMER
PWM/TRIAC
PWM/TIMER Prescaler settings
PWM/TRIAC Prescaler settings
PWM/TRIAC Prescaler configuration and
output waveform selection.
REG_CONF 9
PWM/TRIAC
REG_CONF 10
REG_CONF 11
PWM/TRIAC
PORT C
PWM/TRIAC Working mode Configuration
PORT C digital pin I/O direction
PORT A Alternate function settings
PORT B digital pin I/O direction
PORT B settings for digital or analog pin
Analog Comparator Prescaler settings
Analog Comparator in A/D working mode
Interrupt priorities
REG_CONF 12
PORT A
REG_CONF 13
PORT B
REG_CONF 14(*)
REG_CONF 15(*)
REG_CONF 16(*)
REG_CONF 17
PORT B
ANALOG COMPARATOR
ANALOG COMPARATOR
INTERRUPT
INTERRUPT
TRIAC
REG_CONF 18
Interrupt priorities
REG_CONF 19
TRIAC Pulses Width Configuration
TRIAC Pulses Width Configuration
REG_CONF 20
TRIAC
(*) Not used on ST52x400xx versions
Table 2.3 Output Registers
OR MNEMONIC NAME
PORT_A
PERIPHERAL REGISTER
ADDRESS
PORT A OUTPUT REGISTER
PORT B OUTPUT REGISTER
PORT C OUTPUT REGISTER
TIMER/PWM COUNTER Value
PWM/TIMER RELOAD Value
not used
0
1
2
3
4
5
6
7
8
9
PORT_B
PORT_C (**)
PWM_COUNT
PWM_RELOAD (*)
not used
not used
not used
TRIAC_COUNT
TRIAC DRIVER COUNTER Value
(*)Used if Peripheral has been programmed in PWM Mode (**) Not used on ST52x400F/440F/441F versions
24/94
ST52T400/T440/E440/T441
2.3 Fuzzy Computation
ST FIVE’s Fuzzy main features are:
Figure 2.6 Alpha Weight Calculation
■ Up to 8 Inputs with 8-bit resolution;
■ 1 Kbyte of Program/Data Memory available to
store more than 300 to Membership Functions
(Mbfs) for each Input;
j-th Mbf
1
■ Up to 128 Outputs with 8-bit resolution;
■ Possibility to process fuzzy rules with an
ij
UNLIMITED number of antecedents
α
■ UNLIMITED number of Rules and Fuzzy Blocks.
The limits on the number of Fuzzy Rules and
fuzzy Blocks are only related to the program mem-
ory size.
i-th INPUT VARIABLE
Input Value
2.3.1 Fuzzy Inference .
The block diagram illustrated in Figure 2.7
describes the different steps performed during a
fuzzy algorithm. The ST FIVE Core allows the
implementation of a MAMDANI type fuzzy infer-
ence with crisp consequents. Inputs for fuzzy
inference are stored in 8 dedicated Fuzzy input
registers. The instruction LDFR is used to set the
input fuzzy registers with values stored in the Reg-
ister File. The result of a fuzzy inference is stored
directly in a location of the Register File.
2.3.2 Fuzzyfication Phase.
In this phase the intersection (alpha weight)
between the input values and the related Mbfs is
performed (Figure 2.6).
8 Fuzzy input registers are available for fuzzy
inferences.
After loading the input values by using the LDFR
assembler instruction, the user can start fuzzyn-
ference by using the assembler instructionFUZZY.
During fuzzyfication: input data is transformed in
the activation level (alpha weight) of the Mbfs. i
Figure 2.7 Fuzzy Inference
1
2
11
1m
INFERENCE
PHASE
DEFUZZYFICATION
FUZZYFICATION
n1
N rules -1
N rules
nm
Input Values
Output Values
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ST52T400/T440/E440/T441
2.3.3 Inference Phase.
Figure 2.9 Output Membership Functions
The Inference Phase manages the alpha weights
obtained during the fuzzyfication phase to com-
pute the truth value (Ω) for each rule.
This is a calculation of the maximum (for the OR
operator) and/or minimum (for the AND operator)
performed on alpha values according to the logical
connectives of fuzzy rules.
j-th Singleton
1
ω
ij
Several conditions may be linked together by lin-
guistic connectives AND/OR, NOT operator and
brackets.
ω
i0
ω
in
The truth value ω and the related output singleton-
move to the Defuzzyfication phase in order to
complete the inference calculation.
0
X
i-th OUTPUT
X
X
in
ij
i0
Figure 2.8 Fuzzyfication
2.3.4 Defuzzyfication.
In this phase the output crisp values are deter-
mined by implementing the consequent part of the
rules.
IF INPUT 1 IS X1 OR INPUT 2 IS X2 THEN .......
Each consequent Singleton X is multiplied by its
i
weight values ω , calculated by the Fuzzy Infer-
i
1
α
ence Unit, in order to compute the upper part of
the defuzzification.
Each output value is deduced from the conse-
α2
X1
Input 1
X2
Input
2
OR = Max
quent crisp values (X ) by carrying out the follow-
i
ing defuzzification formula:
where:
N
IF INPUT 1 IS X1 AND INPUT 2 IS X2 THEN ......
Xijωij
j
---------------------
Yi =
N
1
α
α2
ωij
j
X1
Input 1
X2
Input
2
i = 0,1 identifies the current output variable
N = number of the active rules on the current out-
put
ω =weight of the j-th singleton
ij
Xij = abscissa of the j-th singleton
Fuzzy outputs are stored in the RAM location i-th
specified in the assembler instruction OUT i.
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ST52T400/T440/E440/T441
2.3.5 Input Membership Function.
ST FIVE allows the management of triangular
Mbfs. In order to define an Mbf, three different
types of data must be stored on the Program/Data
Memory:
2.3.6 Output Singleton.
ST FIVE uses a particular kind of membership
function called Singleton for its output variables. A
Singleton doesn’t have a shape, like a traditional
Mbf, and is characterized by a single point identi-
fied by the couple (X, w), where the w is calcu-
lated by the Inference Unit as described before.
Often, a Singleton is simply identified with its Crisp
Value X.
the vertex of the Mbf: V;
the length of the left semi-base: LVD;
the length of the right semi-base: RVD;
In order to reduce the size of the memory area
and the computational effort the vertical dimension
of the vertex is set to 15 (4 bits).
2.3.7 Fuzzy Rules.
By using the previous memorization method differ-
ent kinds of triangular Membership Functions may
be stored. Figure 4.6 illustrates a typical example
of Mbfs that can be defined in ST FIVE.
Each Mbf is then defined storing 3 bytes in the first
1 Kbyte of the program memory.
The Mbf is memorized by using the following
instruction:
MBF n_mbf lvd v rvd
Rules can have the following structures:
if A op B op C...........then Z
if (A op B) op (C op D op E...)...........then Z
where op is one of the possible linguistic opera-
tors (AND/OR)
In the first case the rule operators are managed
sequentially; in the second one, the priority of the
operator is fixed by the brackets.
Each rule is codified by using an instruction set,
the inference time for a rule with 4 antecedents
and 1 consequent is about 3 microseconds.
where
n_mbf identifies Mbf, lvd, v, and rvd, which are the
parameters that describe the Mbf’s shape.
Figure 2.11 Example of valid Mbfs
Figure 2.10 Mbfs Parameters
1 5
In p ut M b f
0
V
In pu t V a ria b le
R V D
L V D
O utp u t S in g leto n
1 5
w
0
X
O u tp u t V a riab le
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ST52T400/T440/E440/T441
The assembler Instruction Set, which manages fuzzy instructions is reported in the following table:
Table 2.4 Fuzzy Instruction Set
Instruction
MBF n_mbf Ivd v rvd
LDP n m
Description
Stores the Mbf n_mbf with the shape identified by the parameters Ivd, v and rvd
Fixes the alpha value of the input n with the Mbf m and stores it in internal registers
Calculates the complementary alpha value of the input n with the Mbf m. and stores the
result in internal registers
LDN n m
Implements the Fuzzy operation AND between the last two values stored in internal
registers
FZAND
Implements the Fuzzy operation OR between the last two values stored in internal regis-
ters
FZOR
LDK
Stores the result of the last Fuzzy operation executed in internal registers
Loads the result of the last performed Fuzzy operation (stored in the temporary register
K) in the temporary buffer M.
SKM
LDM
Copies the value of register M in the data stack
CON crisp
OUT n_out
FUZZY
Multiplies the crisp value with the last ω weight
Performs Defuzzyfication and stores the currently Fuzzy output in the RAM n_out location
Starts the Fuzzy algorithm
28/94
ST52T400/T440/E440/T441
Example 1:
IF Input IS NOT Mbf AND Input is Mbf OR Input IS Mbf THEN Crisp
1
1
1
4
12
3
8
is codified by the following instructions:
LDN 1 1 calculates the NOT α value of Input with Mbf and stores the result in internal registers
LDP 4 12 fixes the α value of Input with M and stores the result in internal registers
1
1
4
12
FZAND
LDK
adds the NOT α and α values obtained with the operations LDN1 1 and LDP 4 12
stores the result of the operation FZAND in internal registers
LDP 3 8
fixes the α value of Input with Mbf and stores the result in internal registers
3 8
FZOR
implements the operation OR between the results obtained with the operations LDK and
LDP
CON crisp multiplies the result of the last Ω operation with the crisp value Crisp
1
1
Example 2, the priority of the operator is fixed by the brackets:
IF (Input IS Mbf AND Input IS NOT Mbf ) OR (Input IS Mbf OR Input IS NOT Mbf ) THEN Crisp
2
3
1
4
15
1
6
6
14
LDP 3
LDN 4 15
fixes the α value of Input3 with Mbf1 and stores the result in internal registers
calculates the NOT α value of Input with Mbf and stores the result in internal registers
4
15
FZAND
adds NOT α and α values obtained with the operations LDP 3 1 and LDN 4 15 SKM
stores the result of the operation FZAND in internal registers
LDP 1 6
fixes the α value of Input with Mbf and stores the result in internal registers
1 6
LDN 2 14 calculates the NOT α value of Input with Mbf and stores the result in internal registers
6
14
FZOR
implements the operation OR between the α and NOT α values obtained with the two previ-
ous operations (LDP 1 6 and LDN 2 14)
LDK
LDM
FZOR
stores the result of the operation OR in internal registers
copies the value of the memory register M in internal registers
implements the operation OR between the last two values stored in internal registers (LDK
and LDM)
CON crisp multiplies the result of the last Ω operation with the crisp value Crip
2
2
At the end of the fuzzy rule, by using the instruction OUT RAM_reg, a byte is written. Afterwards, the con-
trol of the algorithm goes returns to the CU.
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ST52T400/T440/E440/T441
2.4 Arithmetic Logic Unit
ST52x400/440/441 supplies 46 instructions that
PGSET.
Direct: the operands of these instructions are
specified with the direct addresses. The operands
can refer, according to the opcode, to addresses
belonging to the different addressing spaces.
Example: SUB, LDRE.
Indirect: data addresses that are required are
found in the locations specified as operands. Both
source and/or destination operands can be
addressed indirectly. The operands can refer,
(according to the opcode) to addresses belonging
to different addressing spaces. Examples: LDRE
(reg1),(reg2).
perform computations and control the device.
Computational time required for each instruction
consists of one clock pulse for each Cycle plus 2
clock pulses for the decoding phase. Total compu-
tation time for each instruction is reported in Table
2.5
The ALU of the ST52x400/440/441 can perform
multiplication (MULT) and division (DIV). Multipli-
cation is performed by using 8 bit operands stor-
ing the result in 2 registers (16 bit values).
Division is performed between a 16 bit dividend
and an 8 bit divider, the result and the remainder
are stored in two 8-bit registers.
WARNING: If the LSB of the multiplication result
is 0, the Zero flag is set although the result is not
0.
2.4.2 Instruction Types.
ST FIVE supplies the following instruction types:
■ Load Instructions
■ Arithmetic and Logic Instructions
■ Jump Instructions
2.4.1 Addressing Modes.
ST52x400/440/441 instructions allow the following
addressing modes:
Inherent: this instruction type does not require an
operand because the opcode specifies all the
information necessary to carry out the instruction.
Examples: NOP, RET.
Immediate: these instructions have an operand as
a source immediate value. Examples: LDRC,
■ Interrupt Management Instructions
■ Control Instructions
The instructions are listed in Table 2.5, Table 2.6
and Table 2.7.
Table 2.5 Arithmetic & Logic Instruction Set
Load Instructions
Bytes Cycles
Mnemonic
LDCE
LDCR
LDFR
Instruction
Z
-
-
-
-
-
-
-
-
-
-
-
-
S
-
-
-
-
-
-
-
-
-
-
-
-
C
-
-
-
-
-
-
-
-
-
-
-
-
LDCE confx,memx
LDRC confx,regx
LDFR fuzzyx,regx
LDPE outx,memx
LDPE outx,(regx)
LDPR outx,regx
LDRC regx,const
LDRE regx,memx
LDRE (regx),(regy)
LDRI regx,inpx
3
3
3
3
3
3
3
3
3
3
3
2
17
14
14
17
17
14
14
16
18
15
16
9
LDPE
LDPE
LDPR
LDRC
LDRE
LDRE
LDRI
LDRR
PGSET
LDRR regx, regy
PGSET const
30/94
ST52T400/T440/E440/T441
Table 2.6 Arithmetic and Logic Instruction Set (Continued)
Arithmetic Instructions
Mnemonic
Instruction
Bytes
Cycles
Z
S
C
ADD
ADDO
AND
ADD regx, regy
ADDO regx, regy
AND regx, regy
ASL regx
3
3
3
2
2
2
3
2
3
2
3
3
3
2
17
20
17
15
15
15
26
15
19
15
17
17
20
15
I
I
I
I
I
I
I
I
I
I
I
I
I
I
-
I
I
I
-
-
I
-
I
ASL
ASR
ASR regx
-
-
I
DEC
DEC regx
I
DIV
DIV regx, regy
INC regx
I
INC
-
-
-
-
I
I
MULT
NOT
MULT regx, regy
NOT regx
-
-
-
-
I
OR
OR regx, regy
SUB regx, regy
SUBO regx, regy
MIRROR regx
SUB
SUBO
MIRROR
I
-
-
Jump Instructions
Mnemonic
Instruction
Bytes
Cycles
Z
S
C
CALL
JP
CALL addr
JP addr
3
3
3
3
3
3
3
3
1
18
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
12
JPC
JPC addr
JPNC addr
JPNS addr
JPNZ addr
JPS addr
JPZ addr
RET
10/12
10/12
10/12
10/12
10/12
10/12
13
JPNC
JPNS
JPNZ
JPS
JPZ
RET
Interrupt Instructions Set
Mnemonic
Instruction
Bytes
Cycles
Z
S
C
HALT
MEGI
MDGI
RETI
RINT
UDGI
UEGI
WAITI
HALT
MEGI
1
1
1
1
2
1
1
1
7/15
7/15
6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MDGI
RETI
12
RINT const
UDGI
8
6
UEGI
7/15
7/14
WAITI
31/94
ST52T400/T440/E440/T441
Table 2.7 Control Instructions Set
Control Instructions set
Mnemonic
FUZZY
Instruction
FUZZY
Bytes
Cycles
Z
-
S
-
C
-
1
1
1
1
5
6
7
6
NOP
NOP
-
-
-
WDTRFR
WDTSLP
WDTRFR
WDTSLP
-
-
-
-
-
-
Notes:
| flag affected
- flag not affected
regx, regy: Register File addresses
memx, memy: Program/Data Memory addresses
confx, confy: Configuration Registers addresses
outx: Output Registers addresses
inpx: Input Registers addresses
const: constant value
fuzzyx: Fuzzy Input Register
addr: Program instructions address
Figure 2.12 Multiplication
Figure 2.13 Division
RAM
0
1
2
RAM
0
1
2
i
i-1
i
i+1
j-1
j
j-1
j
j+1
j+1
253
254
255
253
254
255
X
REG. j
LSB
REG. i
MSB
:
REG. j
REG. j+1
REG. i
16 Bit
REMAINDER
QUOTIENT
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ST52T400/T440/E440/T441
3 EPROM PROGRAMMING
memory reading. A software identification code
(max 64 bytes), called ID CODE may also be writ-
ten in order to distinguish which software version
is stored in the memory.
There are 64 kbits of memory space with an 8-bit
internal parallelism (8 kbytes) addressed by a 13-
bit bus. The data bus is of 8 bits.
EPROM memory provides an on-chip user-pro-
grammable non-volatile memory, which allows fast
and reliable storage of user data.
EPROM memory can be locked by the user. In
fact, a memory location, called Lock Cell, is
devoted to lock the EPROM and to prevent
Memory has a double supply: V
is equal to
PP
12V±5% in Programming Phase or to V during
SS
Table 3.1 EPROM Control Register
Working Phase. V is equal to 5V±10%.
DD
The ST52x400/440/441 EPROM memory is
divided into three main blocks (see Figure 3.1):
OPERATION
REGISTER VALUE
Stand By
0
•
Interrupt Vectors memory block (3 through 14)
contains the addresses for the interrupt rou-
tines. Each address is composed of three
bytes.
Memory
Reading / Verify
1
2
Memory Unlock and
Lock Status Reading
•
Mbfs Setting memory block (15 through 1024)
contains the coordinates of the vertexes of
every Mbf defined in the program. If this part of
the memory is not used to store the Mbfs set-
ting, it can be use to store the instruction set on
the user program.
Memory
Writing
3
Memory
Lock
4
•
The Program Instruction Set memory block
(1024 through 8191) contains the instruction
set of the user program.
ID CODE
Writing
5
Memory Lock Status
Reading / Verify
9
ID CODE
Reading / Verify
10
Figure 3.1 Program Memory Organization
2000h
PROGRAM INSTRUCTIONS
AND PERMANENT DATA
0400h
0015h
PROGRAM INSTRUCTIONS
AND PERMANENT DATA
MEMBERSHIP FUNCTIONS
PARAMETERS
INTERRUPT VECTORS
RESET VECTOR
0003h
0000h
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ST52T400/T440/E440/T441
The locations 0, 1 and 2 contain the jump instruc-
tion to the first code line. This instruction is auto-
matically inserted by the Assembler tool. The
operations that can be performed on EPROM dur-
ing the Programming Phase are: Stand By, Mem-
ory Writing, Reading and Verify/Margin Mode,
Memory Lock, IDCode Writing and Verify.
the control signals applied during Programming
Mode.
The signals RST_ADD, RST_CONF and PHASE
are active on level, the others are active on rising
edge.
The signals RST_ADD and PHASE are active low,
signal on RST_CONF is active high.
The operations above are managed by using the
4-bit EPROM Control Register. The reading phase
Data in/out digital signals are transferred through
the pins of Port A.
is executed with V = 5V±5%, while the verify/
The memory may be locked by means of the
Memory Lock Status flag, that is used to enable
EPROM operations.
PP
Margin Mode phase needs V = 12V±5%. The
PP
Blank Check must be a reading operation with
If Memory Lock Status flag is 1 all EPROM opera-
tions are enabled, otherwise, it is only possible to
read (and verify) the OTP code and the Memory
Lock Status flag.
Only If EPROM is not locked by means of Lock
Cell (see paragraph EPROM Locking), may
EPROM operations be enabled, changing the
Memory Lock Status flag from 0 to 1.
The signal RST_ADD (PB0) resets the memory
address register and the Memory Lock Status flag.
Therefore, when the RST_ADD becomes high,
the memory must be unlocked in order to read or
write.
V
= 5V±5%.
PP
Table 3.1 illustrates the EPROM Control Register
codes used to select the operation. Programming
of the EPROM Control Register is described
below.
3.1 EPROM Programming Phase Procedure
Programming mode is selected by applying
12V±5% voltage or 5V±5% voltage to the V pin
PP
and setting the RESET pin =Vss
If the V voltage is 5V±5% only reading may be
PP
performed.
RST_ADD (PB0), INC_ADD (PB1), RST_CONF
(PB2), INC_CONF (PB3) and PHASE (PB7) are
The signal RST_CONF (PB2) resets the EPROM,
Figure 3.2 EPROM Programming Timing
DATA
DATA
DATA
DATA
OUT
DATA
OUT
DATA
OUT
DATA
IN
PA(0:7)
RST_ADD
RST_CONF
INC_ADD
INC_CONF
PHASE
100nS
10 S
µ
MEMORY UNLOCK
MEMORY WRITING
MEMORY VERIFY
MARGIN MODE
LOCATION ADDRESS =1
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ST52T400/T440/E440/T441
INC_ADD (PB1) signal increments the memory
address.Control Register. When RST_CONF is
high, the DATA I/O Port A is in output, other-
wise it is always in input.
The signal applied on INC_CONF (PB3) incre-
ments the EPROM Control Register value. To
select the operation it must be provided as many
signal edges as the value to be written in the reg-
ister (see Table 3.1).
3.1.3 EPROM Writing. When the memory is
blank, all the bits are at logic level “1". The data is
introduced by programming only the zeros in the
desired memory location; however, all input data
must contain both ”1” and “0". The only way to
change “0" into ”1” is to erase the whole memory
(by exposure to UV light) and reprogram it.
The memory is in Writing mode when the EPROM
Control Register value is 3.
The signal on PHASE (PB7) validates the opera-
tion selected by means of the EPROM Control
Register value.
The V
voltage must be 12V±5%, with stable
PP
data on the data bus PB(0:7). The signals timing is
the following (see Figure 3.2):
1) RST_ADD and RST_CONF change from low to
high level,
2) two pulses on INC_CONF signal load the Mem-
ory Unlock operation code,
3) a negative pulse (100 ns) on the PHASE signal
validates the Memory Unlock operation,
4) a negative pulse on RST_CONF signal resets
the EPROM Control Register,
5) three positive pulses on INC_CONF load the
Memory Writing operation code,
6) a train of positive pulses on INC_ADD signal
increments the memory location address up to the
requested value (generally this is a sequential
operation and only one pulse is used),
7) a negative pulse (10 µs) on the PHASE signal
validates the Memory Writing operation.
3.1.1 EPROM Operation. In order to execute an
EPROM operation (see Table 3.1), the corre-
sponding identification value must be loaded in
the EPROM Control Register. The signal timing is
the following: RST_ADD= high and PHASE= high,
RST_CONF changes from low to high level, to
reset the EPROM Control Register, and
INC_CONF signal generates a number of positive
pulses equal to the value to be loaded. After this
sequence, a negative pulse of the PHASE signal
will validate the selected operation. The minimum
PHASE signal pulse width must be 10 µs for the
EPROM Writing Operation and 100 ns for the oth-
ers.
When RST_CONF is high, the DATA I/O Port A is
enabled in output and the reading/verify operation
results are available.
3.1.4 EPROM Reading/Verify Margin Mode.
The reading phase is executed with V = 5V±5%,
After a writing operation, when RST_CONF is
high, Port A is in output without valid data.
PP
instead of verify phase that needs V = 12V±5%.
PP
The Memory Verify operation is available in order
to verify the correctness of the data written. The
Memory Verify Margin Mode operation may be
executed immediately after the writing of each
byte and in this case (see Figure 3.2):
3.1.2 EPROM Locking. The Memory Lock oper-
ation, which is identified with the number 4 in the
EPROM Control Register, writes “0" in the Mem-
ory Lock Cell.
At the beginning of an External Operation, when
RST_ADD signal changes from low level to high
level, the Memory Lock Status flag is “0", therefore
it is necessary to unlock it before proceeding.
In order to unlock the Memory Lock Status flag the
operation, which is identified with the number 2 in
the EPROM Control Register must be executed
(see Figure 3.2).
The Memory Lock Status flag can be changed.
Therefore, after a Memory Lock operation, exter-
nal operations cannot be executed except reading
(or verify) the OTP Code and the Memory Lock
Status.
1) one positive pulse on RST_CONF signal resets
the Control Register, if it was not already reset
2) one positive pulse on INC_CONF loads the
Memory Reading/Verify operation code,
3) one negative pulse (100 ns) on the PHASE sig-
nal validates the Memory Reading/Verify opera-
tion,
4) a negative pulse on RST_CONF signal puts in
the PB(0:7) port the value stored in the actual
memory address and resets the EPROM Control
Register.
Then, if any error in writing occurred, the user has
to repeat the EPROM writing.
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ST52T400/T440/E440/T441
3.1.5 Stand by Mode. EPROM has a standby
mode which reduces the active current from 10mA
(Programming mode) to less than 100 µA. Mem-
ory is placed in standby mode by setting PHASE
signal at high level or when the EPROM Control
Register value is 0 and PHASE signal is low.
3.1.6 ID code. A software identification code,
called ID code may be written to distinguish which
software version is stored in the memory.
64 Bytes are dedicated to store this code by using
the address values from 0 to 63.
The ID Code may be read or verified even if the
Memory Lock Status is “0".
The signals timing is the same as that of a normal
operation.
3.2 Eprom Erasure
Thanks to the transparent window available in the
CDIP28W package, its memory contents may be
erased by exposure to UV light.
Erasure begins when the device is exposed to
light with a wavelength shorter than 4000Å. It
should be noted that sunlight, as well as some
types of artificial light, includes wavelengths in the
3000-4000Å range which, on prolonged exposure,
can cause erasure of memory contents. It is thus
recommended that EPROM devices be fitted with
an opaque label over the window area in order to
prevent unintentional erasure.
The recommended erasure procedure for EPROM
devices consists of exposure to short wave UV
light having a wavelength of 2537Å. The minimum
recommended integrated dose (intensity x expo-
2
sure time) for complete erasure is 15Wsec/cm .
This is equivalent to an erasure time of 5-10 min-
utes using a UV source having an intensity of
2
12mW/cm at a distance of 25mm (1 inch) from
the device window.
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ST52T400/T440/E440/T441
4 INTERRUPTS
The Control Unit (CU) responds to peripheral
Figure 4.1 Interrupt Flow
events and external events via its interrupt chan-
nels.
NORMAL
PROGRAM
FLOW
When such an events occur, if the related interrupt
is not masked and according to a priority order,
the current program execution can be suspended
to allow the CU to execute a specific response
routine.
INTERRUPT
SERVICE
ROUTINE
INTERRUPT
Each interrupt is associated with an interrupt vec-
tor that contains the memory address of the
related interrupt service routine. Each vector is
located in the Program Space (EPROM Memory)
at a fixed address (see Interrupt Vectors Figure
4.2).
RETI
INSTRUCTION
4.1 Interrupt Operation
If there are pending interrupts at the end of an
Figure 4.2 Interrupt Vectors Mapping
arithmetic or logic instruction, the one with the
highest priority is passed. Passing an interrupt
means to store the arithmetic flags and the current
PC in the stack and execute the associated Inter-
rupt routine, whose address is located in three
bytes of the EPROM memory location between
address 3 and 20.
The Interrupt routine is performed as a normal
code checking, at the end of each instruction, if a
higher priority interrupt has to be passed. An Inter-
rupt request with the higher priority stops the
lower priority Interrupt. The Program Counter and
the arithmetic flags are stored in the stack.
With the instruction RETI (Return from Interrupt)
the arithmetic flags and Program Counter (PC) are
restored from the top of the stack, which was pre-
viously described in Section 2.2.1.
0
1
2
RESET
INT_AC
3
4
5
6
7
INT_TIMER/PWM
INT_TRIAC/F
INT_TRIAC/R
INT_TRIAC/P
INT_EXT
8
9
INTERRUPT
VECTORS
10
11
12
13
14
15
16
17
18
19
20
Figure 4.3 Global Interrupt Request Generation
An Interrupt request cannot stop fuzzy rule pro-
cessing, but this is passed only after the end of a
fuzzy rule or at the end of a logic, or arithmetic
instruction.
Global Interrupt
Global Interrupt
Pending
Request
REMARK: A fuzzy routine can be interrupted only
in the Main program. When a Fuzzy function is
running inside another interrupt routine an inter-
rupt request can cause side effects in the Control
Unit. For this reason, in order to use a Fuzzy func-
tion inside an interrupt routine, the user MUST
include the Fuzzy function between an UDGI
(MDGI) instruction and and UEGI (MEGI) instruc-
tion (see the following paragraphs), in order to dis-
able the interrupt request during the execution of
the fuzzy function.
User Global
Interrupt Mask
Macro Global
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4.2 Global Interrupt Request Enabling
When an Interrupt occurs, it generates a Global
Table 4.1 Configuration Register 0
Description
Interrupt Pending (GIP), which can be masked by
software. After a GIP, a Global Interrupt Request
(GIR) will be generated and an Interrupt Service
Routine associated to the interrupt with higher pri-
ority will start. In order to avoid possible conflicts
between interrupt masking set in the main pro-
gram, or inside macros, the GIP is masked
through the User Global Interrupt Mask or the
Macro Global Interrupt Mask (see Figure 4.3).
UEGI/UDGI instruction switches the User Global
Interrupt Mask on/off, enabling/disabling the GIR
for the main program.
Bit
Name
Value
Description
External Interrupt
Masked
0
0
MSKE
External Interrupt
Not Masked
1
0
Analog
Comparator
Interrupt
Masked
1
MSKAC(*)
Analog
Comparator
Interrupt Not
Masked
MEGI/MDGI instructions switches the Macro Glo-
bal Interrupt Mask on/off in order to ensure that
the macro will not be broken.
1
0
PWM/TIMER
Interrupt
4.3 Interrupt Sources
ST52x400/440/441 manages interrupt signals
Masked
2
3
MSKTM
generated by the internal peripherals (PWM/
TIMER, TRIAC Driver and Analog Comparator) or
deriving from the External Interrupt on pin PA7.
The External Interrupt can be programmed to be
active on the rising or falling edge of INT/PA7 sig-
nal by setting the PEXTINT bit of the Configura-
tion Register to 0.
PWM/TIMER
Interrupt
Not Masked
1
0
1
TRIAC Falling
Edge Interrupt
MSKTRF
TRIAC Falling
Edge Interrupt
Not Masked
WARNING: Changing the interrupt priority an
interrupt request is generated.
TRIAC Rising
Edge Interrupt
Masked
0
1
Each peripheral can be programmed in order to
generate the associated interrupt; further details
are described in the related chapter.Configuration
Register 0 is also used to enable/disable the
Brown-Out (see the related chapter).
4
5
MSKTRR
MSKTRP
TRIAC Rising
Edge Interrupt
Not Masked
TRIAC Pulse
Interrupt Masked
0
1
4.4 Interrupt Maskability
The interrupts can be masked by configuring the
Configuration Register 0 by means of an LDCR or
an LDCE instruction. The interrupt is enabled
when the bit associated to the mask interrupt is
“1". Viceversa, when the bit is ”0", the interrupt is
masked and is kept pending.
TRIAC Pulse
Interrupt Not
Masked
External
Interrupt active
on Rising Edge
0
1
For example:
6
7
PEXTINT
MSKBR
LDRC 10,6
(loads the constant 6 in the RAM
External
Interrupt active
on Falling Edge
Register 10)
LDCR 0,10 (sets REG_CONF0 with the value
stored in RAM Register 10)
the result is REG_CONF0=00000110, enabling
the interrupts coming from the Analog Comparator
(INT_AC) and from the PWM/TIMER (INT_PWM/
TIMER).
Brown-Out
Disabled
0
1
Brown-Out
Enabled
Reset Configuration ‘00000000’
(*) Not Used in ST52x400 devices
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ST52T400/T440/E440/T441
Table 4.2 Interrupts Description
Peripheral
Code
Mask-
able
Vector
Addresses
Name
Description
Priority
INT_AC(*)
INT_PWM/TIMER
INT_TRIAC/F
INT_TRIAC/R
INT_TRIAC/P
INT_EXT
Analog Comparator
PWM/TIMER
Int
Int
Int
Int
Int
Ext
Programmable
Programmable
Programmable
Programmable
Programmable
Highest
000
001
010
011
100
-
yes
yes
yes
yes
yes
yes
3-5
6-8
TRIAC Falling Edge
TRIAC rising edge
TRIAC Pulse
9-11
12-14
15-17
18-20
External Interrupt (INT)
(*) Used only in ST52x440/441 devices
Figure 4.4 Interrupt Configuration Register 0
REG_CONF0
Interrupts Mask
D7 D6 D5 D4 D3 D2 D1 D0
MSKE: Ext. Int.
MSKAC: An. Comp. Int.
MSKTM: Timer Int.
MSKTRF: Triac Fall. Int.
MSKTRR: Triac Ris. Int.
MSKTRP: Triac Pulse Int.
PEXTINT: Ext. Int. Ris/Fall.
MSKBR: Brown Out En.
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ST52T400/T440/E440/T441
Figure 4.5 Interrupt Configuration Registers 17 and 18
Interrupts Priority
REG_CONF18
REG_CONF17
D15 D14 D13 D12 D11 D10
D8
D0
D7 D6 D5 D4 D3 D2 D1
D9
INT 1
INT 2
INT 3
INT 4
INT 5
Not Used
4.5 Interrupt Priority
■ Level 5: INT_TRIAC/PWM_F (TRIAC/PWM_F
Seven priority levels are available: level 6 has the
lowest priority, level 0 has the highest priority.
Level 6 is associated to the Main Program, levels
5 to 1 are programmable by means of the priority
Code: 010)
Table 4.3 Conf. Registers 17-18 Description
registers
called
REG_CONF17
and
Bit
Name
INT1
INT2
INT4
INT5
INT6
Value
Level
High
REG_CONF18; whereas the higher level is
related to the External Interrupt (INT_EXT).
PWM/Timer, TRIAC/PWM and Analog Block are
identified by a three-bit Peripheral Code (see
Table 4.2); in order to set the i-th priority level the
user must write the peripheral label i in the related
INTi priority level.
0, 1, 2
3, 4, 5
6, 7, 8
9, 10, 11
12, 13,
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
MediumHigh
MediumLow
Low
Very Low
REMARK: The Interrupt priority must be set at the
beginning of the main program, because at the
RESET REG_CONF1=’00000000’, this condition
could generate wrong operations. Further,
changing the priority levels must be avoided in
interrupt service routines.
For instance:
LDRC 10,193 (loads the value 193=’11000001’
in the RAM Register 10)
LDRC 11,168 (loads the value 168=’10101000’
in the RAM Register 11)
LDCR 17,10 (REG_CONF17= ‘11000001’)
LDCR 18,11 (REG_CONF18= ‘10101000’)
thus defining the following priority levels:
When a source provides an Interrupt request, and
the request processing is also enabled, the CU
changes the normal sequential flow of a program
by transferring program control to a selected ser-
vice routine.
When an interrupt occurs the CU executes a
JUMP instruction to the address loaded in the
related location of the Interrupt Vector and the
flags are saved.
■ Level 1: INT_PWM/TIMER (PWM/TIMER Code:
001)
■ Level 2: INT_ADC (ADC Code: 000)
■ Level 3: INT_TRIAC/PWM_R (TRIAC/PWM
Code: 011)
■ Level 4: INT_TRIAC/Ph (TRIAC/Ph Code: 100)
When the execution returns to the original pro-
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ST52T400/T440/E440/T441
gram, the flags are restored and the program con-
tinues from the instruction immediately following
the interrupted instruction.
WARNING: If an interrupt is reset, with the RINT
instruction within its own interrupt routine, the
priority level of the interrupt becomes the lowest
and the routine can be immediately interrupted by
a lower priority interrupt request.
4.6 Interrupts and Low power mode
All interrupts allow the processor to leave WAIT
Table 4.4 RINT Instruction Code
mode. Only an External Interrupt request allows
the processor to leave HALT mode: if the interrupt
is masked, the related interrupt routine is not ser-
viced and the program continues from the first
instruction after the HALT instruction.
Peripheral Name
Analog Comparator (*)
PWM/TIMER
Value
0
1
2
3
4
5
TRIAC/F
4.7 Interrupt RESET
When an interrupt request is sent but the interrupt
INT_TRIAC/R
is masked, it isn’t serviced and remains pending,
so that when the interrupt is enabled it is serviced
immediately. In order to avoid this from happen-
ing, the pending interrupt request can be reset
with the instruction RINT j, which resets the
interrupt j-th where j identify the peripherals as
described in the following table (see Table 4.4).
The assembler instruction:
INT_TRIAC/P
External Interrupt
(*) Not Used in ST52x400 devices
RINT 2
Resets the TRIAC/PWM_F interrupt.
Figure 4.6 Example of a sequence of Interrupt Requests
INT2 INT0 INT4
INT1
INT3
PRIORITY
LEVEL
0
1
2
3
4
5
6
INT0
INT1
INT2
INT2
INT2
INT3
INT4
MAIN PROGRAM
MAIN PROGRAM
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5 CLOCK, RESET & POWER SAVING MODE
The different clock generator options connection
methods are illustrated in Oscillator Connec-
tions.When an external clock is used, it must be
connected to the pin OSCin while OSCout should
be left floating.
5.1 Clock System
The ST52x400/440/441 Clock Generator module
generates the internal clock for the internal Con-
trol Unit, ALU and on-chip peripherals and is
designed to require a minimum of external compo-
nents.
The ST52x400/440/441 oscillator circuit gener-
ates an internal clock signal with the same period
and phase as at the OSCin input pin. The maxi-
mum frequency allowed is 20 MHz.
The crystal oscillator start-up time is a function of
many variables: crystal parameters (especially
R ), oscillator load capacitance (CL), IC parame-
s
ters, environment temperature, supply voltage.
It must be observed that the crystal or ceramic
lead and circuit connections must be as short as
possible. Typical values for CL1, CL2 are 10pF for
a 20 MHz crystal.
The system clock may be generated by using
either a quartz crystal, ceramic resonator (CER-
ALOC), or an external clock.
Figure 5.1 Oscillator Connections
CRYSTAL CLOCK
EXTERNAL CLOCK
ST52X440
ST52X440
OSCin
OSCout
OSCin
OSCout
Cl1
10pF
Cl2
10pF
CLOCK
INPUT
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ST52T400/T440/E440/T441
5.2 Reset
There are four sources of Reset:
- RESET pin (external source)
- WATCHDOG (internal source)
- POWER ON Reset (Internal source)
- BROWN OUT Reset (Internal source)
When a Reset event happens, all the registers are
set to the reset value and the user program
restarts from the beginning.
If an external resistor is connected to the RESET
pin a minimum value of 10KΩ must be used.
After a RESET procedure is completed, the core
reads the instruction stored in the first 3 bytes of
the EPROM, which contains a JUMP instruction to
the EPROM address containing the first instruc-
tion of the user program. The Assembler tool auto-
matically generates this Jump instruction with the
first instruction address.
5.2.1 External Reset.
5.2.3 Power-on Reset (POR).
The Reset pin is an input pin. An internal reset
does not affect this pin.
A Power-On Reset is generated by an on-chip
detection circuit. This circuit ensures that the
device is not started until Vdd has reached the
nominal level of 2.3V and allows the clock oscilla-
tor to stabilize.
Once 2.3V are reached, the Power-On circuit gen-
erates an internal RST signal that releases the
internal reset to the CPU and invokes a delay
counter of 1.000.000 CPU clock cycles, during
which the device is kept in RESET after Vdd has
risen.
A Reset signal originated by external sources is
recognized istantaneously. The RESET pin may
be used to ensure Vdd has risen to a point where
the MCU can operate correctly before the user
program is run. In working mode the Reset must
be set to ‘1’ (see Table 1.1)
5.2.2 Reset Operation.
The duration of a RESET condition is fixed at
1.000.000 internal CPU clock cycles (or 4096 in
case of BOD).
A correct operation of Power-on detector is guar-
anteed if the slew rate of Vdd is 0.05 V/ms.
Following a Power-On Reset event, or after exit-
ing Halt Mode, a 1.000.000 CPU clock cycle delay
period is initiated in order to allow the oscillator to
stabilize and to ensure that recovery has taken
place from the Reset state.
A Pull up resistor of 100 KΩ guarantees that
RESET pin is at level “1” when no HALT or
Power-On events occurred.
Note: The power supply must fall below 0 V for
the internal POR circuit to detect the next rise of
Vdd.
At power on the POR is enabled by default.
POR is designed exclusively to cope with power-
up conditions and should not be used to detect a
drop in the power supply voltage, for which the
Brown-out Detector can be used instead.
Figure 5.2 Reset Block Diagram
Vdd
WATCHDOG RESET
WATCHDOG
INTERNAL RESET
COUNTER x
RESET
1.000.000
Vdd
Vdd
POWER-ON
RESET
BROWN-
OUT
COUNTER x
4096
BROWN-OUT RESET
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5.2.4 Brown-Out Detector (BOD).
5.3.2 Halt Mode.
The on-chip Brown-Out Detector circuit prevents
the processor from falling into an unpredictable
state if the power supply drops below a certain
level.
When Vdd drops below the Brown-out detection
level, the Brown-out causes an internal proces-
sor reset RST that remains active as long as Vdd
remains below the Brown-Out Trigger Level.
Brown-Out resets the entire device except the
Power-on Detector and the Brown-out itself.
Enabling/disabling the Brown-out detector can be
performed by setting the software of the control bit
BOD of REG_CONF0 (Table 4.1).
Halt mode is the MCU’s lowest power consump-
tion mode, which is entered by executing the
HALT instruction. The internal oscillator is turned
off, causing all internal processing to be stopped,
including the operations of the on-chip peripher-
als.
Halt mode cannot be used when the watchdog
is enabled. If the HALT instruction is executed
while the watchdog system is enabled, it will be
skipped without modifying the normal CPU opera-
tions.
The ICU can exit Halt mode after an external inter-
rupt or reset. The oscillator is then turned on and
stabilization time is provided before restarting
CPU operations. Stabilization time is 4096 CPU
clock cycles after the interrupt and 1.000.000 after
the Reset.
When Vdd increases above the Trigger Level, the
Brown-Out reset is turned off after a delay of 4096
CPU clock cycles, which ensures stabilization of
the oscillator.
The Brown-Out falling voltage level typical value is
3.8V and the corresponding rising voltage activa-
tion level is 4.1V.
After the start up delay, the CPU restarts opera-
tions by serving the external interrupt routine.
Reset makes the ICU exit from HALT mode and
restart, after the delay, from the beginning of the
user program after the delay.
A minimum hysteresis of 250mV for the trigger is
guaranteed for spike free brown-out detection.
Brown-Out circuit detects a drop if Vdd voltage
stays below the safe threshold for longer than 100
Clock cycles before activation/deactivation of the
Brown-Out in order to filter voltage spikes.
Brown-Out function is disabled by default and is
not active when in HALT mode.
Warning: if the External Interrupt is disabled, the
ICU exits from the Halt mode and jumps to the
lower priority interrupt routine.
Figure 5.3 WAIT Flow Chart
Remark: for higher frequencies, the device needs
Supply Voltage higher than the BOD threshold.
For this reason the BOD cannot work in this range
of frequencies. See Electrical Characteristic
Chapter in this Datasheet.
5.3 Power Saving Modes
There are two Power Saving modes: WAIT and
HALT mode. These conditions may be entered by
using the WAIT and HALT instructions.
5.3.1 Wait Mode.
Wait mode places the MCU in a low power con-
sumption by stopping the CPU. All peripherals and
the watchdog remain active. During WAIT mode,
the Interrupts are enabled. The MCU will remain in
Wait mode until an Interrupt or a RESET occurs,
whereupon the Program jumps to the interrupt
service routine or, if a RESET occurs, at the
beginning of the user program.
Remark: in Wait mode the CPU clock does’t stop.
44/94
ST52T400/T440/E440/T441
Figure 5.4 HALT Flow Chart
HALT INSTRUCTION
YES
WATCHDOG
ENABLED
NO
HALT INSTRUCTION
SKIPPED
OSCILLATOR
PERIPHERALS CLOCK
CPU CLOCK
OFF
OFF
OFF
NO
YES
NO
EXTERNAL
INTERRUPT
RESET
YES
OSCILLATOR
PERIPHERALS CLOCK
CPU CLOCK
ON
ON
ON
OSCILLATOR
PERIPHERALS CLOCK
CPU CLOCK
ON
ON
ON
1000000 CPU CLOCK
4096 CPU CLOCK
CYCLES DELAY
CYCLES DELAY
EXTERNAL
INTERRUPT
ENABLED
NO
YES
RESET CPU
AND RESTART
USER PROGRAM
RESTART PROGRAM
SERVICING THE
EXTERNAL
RESTART PROGRAM
SERVICING THE
LOWER PRIORITY
INTERRUPT ROUTINE
INTERRUPT ROUTINE
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ST52T400/T440/E440/T441
6 I/O PORTS
internal pull-up resistor (22 kΩ). The 441 device
doesn’t have internal pull-up resistor. This
pull-up resistor is automatically excluded
when the pin is configured as Analog Input or,
in MAIN1 and MAIN2 pins, when the Triac
Driver is configured in Phase Angle Partializa-
tion or Burst mode.
Each single port pin can be programmed in input
or output or Alternate Function, so that in the
same port there can be both input and output pins.
The port pins are write/read in parallel at the same
time: when reading output pins, the port buffer
contents are read; when writing an input pin the
value is written in the buffer.
6.1 Introduction
ST52x400/440/441 devices offer flexible individu-
ally programmable multi-functional input/output
lines. Refer to Chapter 1 for specific pin alloca-
tions.
21 I/O lines, grouped in 3 different ports, are avail-
able for ST52x400G/440G/441G devices:
PORT A = 8-bit ports (PA0 - PA7 pins)
PORT B = 8-bit ports (PB0 - PB7 pins)
PORT C = 5-bit port (PC0 - PC4 pins)
13 I/O lines, grouped in 2 different ports are avail-
able for ST52x400F/440F/441F devices:
PORT A = 8-bit ports (PA0 - PA7 pins)
Each port is configured by using Configuration
Registers indicated in Table 6.1. The first is used
to define if a pin is an Input or an Output, the sec-
ond defines the Alternate functions.
PORT B = 5 -bit ports (PB0 - PB3 and PB7 pins)
These I/O lines can be programmed to provide
Digital Input/Output or Analog Input, or to connect
input/output signals to the on-chip peripherals as
Alternate Pin Functions.
The input buffers are TTL compatible with Schmitt
Trigger in ports A and C while port B is CMOS
compatible without Schmitt trigger and it is used
for the Analog Inputs.
Table 6.1 I/O Port Configuration Register
(*)
PORT A
PORT B
PORT C
Reg_Conf 4
Reg_Conf 12
Reg_Conf 13
Reg_Conf 14
Reg_Conf 11**
Reg_Conf 11
The output buffer can supply up to 8 mA.
(*)
Not available in ST52x400F/440F/441F
All the port pins of 400/440 devices have an
Figure 6.1 Ports A and C Functional Blocks
(**) Only in ST52x440F/441F
Vcc
22 k
TTL
TO INPUT REGISTER
and PERIPHERALS
PORT A PIN
or PORT C PIN
FROM PERIPHERAL
FROM OUTPUT REGISTER
FROM CONFIGURATION REGISTER
FROM CONFIGURATION REGISTER
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ST52T400/T440/E440/T441
Figure 6.2 Port B Functional Blocks
Vcc
FROM CONFIGURATION REGISTER
22 k
CMOS
TO INPUT REGISTER
PORT B PIN
TO A/D CONVERTER
FROM OUTPUT REGISTERS
FROM CONFIGURATION REGISTER
6.2 Input Mode
The input configuration is selected setting the cor-
responding configuration register bit in
the Input Registers (see Table 6.2), but the single
bit of the Input Register (IR) cannot be read
directly and the value in a RAM location must be
copied. Digital data is stored in a RAM location by
using the assembler instruction:
LDRI regx,inpy
Then, each single bit can be examined by using
AND and OR operators with a suited mask value.
REG_CONF4, REG_CONF13 and, where appli-
cable, REG_CONF11 (see Paragraph I/O Port
Configuration Registers) to “1”. To use Port A and
B pins as digital input, the corresponding bits in
REG_CONF12 and REG_CONF14 must be set
according to the values shown in Table 6.4, Table
6.5 and Table 6.6.
6.3 Output Mode
The output pin configuration is selected by setting
the corresponding configuration register bit to “0”
(REG_CONF4, REG_CONF13 and, where appli-
cable, REG_CONF11) (see paragraph I/O Port
Configuration Registers). in order to use Port A
and B pins as digital output, the corresponding bits
in REG_CONF12 and REG_CONF14 must be set
according to the values illustrated in Tables - Port
A - REG_CONF 4, - Port A - REG_CONF 12 and
Analog Inputs REG_CONF 14.
Table 6.2 Input Register and I/O Ports
(*)
PORT A
PORT B
PORT C
IR 14
IR 15
IR 16
(*)
Not used for ST52x400F/440F/441F
Table 6.3 Output Register and I/O Ports
(*)
PORT A
PORT B
PORT C
Digital data is transferred to the related I/O Port by
means of the Output register (see Table 6.3), by
using the assembler instructions LDPE or LDPR
that respectively take the value to be transferred
to the ports from EPROM and RAM.
OR 0
OR 1
OR 2
(*)
Not used for ST52x400F/440F/441F
Digital input data is automatically stored in
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ST52T400/T440/E440/T441
6.4 Alternate Functions.
Port A and B pins in ST52x400/440/441 are con-
Timer/PWM Alternate Functions
Pins of Port A can be configured to be I/Os of the
on-chip TIMER/PWM of ST52x400/440/441. The
configuration of these pins is performed by using
Configuration Registers REG_CONF4 and
REG_CONF12 (Tables - Port A - REG_CONF 4
and - Port A - REG_CONF 12).
If a pin has to be a TIMER Input (TSTRT, TCLK,
TRES) the related bit of REG_CONF4 must be set
to “1” and of REG_CONF12 must be set to “1”.
If, instead it must be a TIMER Output (TOUT,
TOUTN), REG_CONF12 related bit must be set to
“0” and the related bit of REG_CONF4 be set to
“0”.
figurable to be used with different functions (Alter-
nate Functions) related to the use of peripherals.
To configure a pin in Alternate Function the related
configuration registers must be set according to
the values shown in Tables - Port A - REG_CONF
4, - Port A - REG_CONF 12 and Analog Inputs
REG_CONF 14.
For example: if pin PA5/TCLK has to be used as
an external PWM/Timer Clock, REG_CONF4[(5)]
bit must be set to ‘1’.
When the signal is an input of an on-chip
peripheral, the related I/O pin has to be config-
ured in Input Mode.
When a pin of Port B is used as an Analog Input,
the related I/O pin is automatically set in threes-
tate. The analog multiplexer (controlled by the
Analog Comparator Configuration Register)
switches the analog voltage present on the
selected pin to the common analog rail, which is
connected to the ADC input.
It is recommended that the voltage level or loading
on any port pin not be changed while conversion
is running. Furthermore, it is recommended not to
have clocking pins located close to a selected
analog pin.
TRIAC Driver Alternate Function
When using the on-chip TRIAC, to have the
TRIAC Output on pin PA0, bit REG_CONF12[0]
must be set to “0” and REG_CONF4[0] to “0”.
When a synchronization with the Mains voltage is
necessary, in case either the Phase Angle Partial-
ization or the Burst Modes is chosen, to have
MAIN1 and MAIN2 as Inputs on PortA, it is neces-
sary to set bits 1 and 2 of REG_CONF4 to “1”.
Table 6.4 - Port A - REG_CONF 4
Bit
0
Name
D0
Value
Pin Description
PA0
6.5 I/O Port Configuration Registers
The I/O mode for each bit of the three ports are
X
X
X
X
X
X
X
X
1
D1
PA1/MAIN1
PA2/MAIN2
PA3/ACSTRT(*)
PA4/TSTRT
PA5/TCLK
PA6/TRES
PA7/INT
selected by using Configuration Registers 4, 12,
13 and 11 (Table 6.1). The structure of these reg-
isters is illustrated in tables - Port A - REG_CONF
4, - Port A - REG_CONF 12, - Port B -
REG_CONF 13, Analog Inputs REG_CONF 14
and - Port C - REG_CONF 11. Each bit of the con-
figuration registers sets the I/O mode of the
related port pin.
2
D2
3
D3
4
D4
5
D5
6
D6
7
D7
X = 0 Pin set as Digital Output
X = 1 Pin set as Alternate Function Input
Analog Comparator Inputs
Pins PB0-PB7 for ST52x440G/441G and PB0-
PB3 and PB7 in ST52x440F/441F can be config-
ured to be Analog Inputs by setting the related bit
in REG_CONF 14 to “1” (Table 6.7) and the
related bit in REG_CONF13 to “1” (Table 6.6).
These analog inputs are connected to the on chip
Analog Comparator.
Reset Configuration ‘1111’
(*) Not available in ST52x400xx
If the BandGap Reference (BG) is needed as an
Output for ST52x440G/441G REG_CONF13[6]
must be set to “0” and REG_CONF14[6] to “1”.
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ST52T400/T440/E440/T441
Table 6.7 Analog Inputs REG_CONF 14
Table 6.5 - Port A - REG_CONF 12
Bit
0
Name
D0
Value
Pin Description
PB0/AC0(*)
Bit
Name
Value
Pin Description
X
X
X
X
X
X
X
X
0
1
2
3
4
5
6
7
D0
D1
D2
D3
D4
D5
D6
D7
X
X
X
X
PA0/TROUT
PA6/TOUT
PA2/TOUTN
PA7/ACSYNC(*)
not used
1
D1
PB1/AC1(*)
2
D2
PB2/AC2(*)
3
D3
PB3/AC3(*)
4
D4
PB4/AC4(*)(**)
PB5/AC5(*)(**)
PB6/BG(*)(**)
PB7/CS(*)(**)
not used
5
D5
not used
6
D6
not used
7
D7
X = 0 Pin set as Alternate Function Output
X = 1 Pin set as Digital I/O
X = 0 Pin set as Digital I/O
X = 1 Pin set as Analog Input
Reset Configuration ‘1111’
Reset Configuration ‘00000000’
(*) Not available in ST52x400xx
(*) Not available in ST52x400xx
(**) Not available in ST52x440F/441F
Table 6.6 - Port B - REG_CONF 13
Table 6.8 - Port C - REG_CONF 11
Bit
0
Name
D0
Value
Related Pin
PB0
Bit
0
Name
D0
Value
Related Pin
PC0(*)
X
X
X
X
X
X
X
X
X
X
X
X
X
1
1
D1
PC1(*)
PC2(*)
PC3(*)
PC4(*)
1
D1
PB1
2
D2
PB2
2
D2
3
D3
PB3
3
D3
4
D4
PB4(*)
PB5(*)
PB6(*)
PB7
4
D4
(**)
5
D5
5
D5
6
D6
6
D6
not used
not used
7
D7
7
D7
X = 0 Pin set as Output
X = 1 Pin set as Input
X = 0 Pin set as Digital Output
X = 1 Pin set as Digital Input
Reset Configuration ‘11111111’
(*) Not available in ST52x400F/440F/441F
Reset Configuration ‘11111111’
(*)
Not used in ST52x400F/440F/441F
(**) Must be set to 1
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ST52T400/T440/E440/T441
7 ANALOG COMPARATOR (ST52X440/441)
7.2 Comparator Mode
In Analog Comparator mode, REG_CONF3[(0)] is
set to “0”. The AC inputs are available on the
external pins. The reference signal must be con-
nected to the CS pin, the signal to be compared
goes to the analog input AC0.
When the input becomes lower than the refer-
ence, the Analog Comparator output changes to
value “1”. The output can be read on the less sig-
nificative bit of Input Register 1 AC_CHAN0H
(Table 2.1).
7.1 Analog Module Overview
The ST52x440/441 includes an Analog Compara-
tor (AC) among its peripherals.
The Analog Comparator is endowed with analog
and digital elements in order to also allow the user
to make use of it as a single slope Analog to Digi-
tal converter. In particular, ST52x440/441 is
endowed with:
■ Analog Comparator;
■ 7 channels analog mux (6 external lines, 1
7.3 A/D Converter Mode
To use the Analog Comparator for A/D Conver-
internal voltage reference);
■ a current source providing 7 programmable
sion, REG_CONF3[(0)] bit must be set to “1”.
In A/D Mode either the insertion of an external
capacitor to pin CS or the connection to an exter-
nal signal to generate the reference ramp may be
chosen.
In the first case REG_CONF16[(1)] bit must be set
to “0”. The internal current generator, utilized to
charge the capacitor, provides 7 possible current
values;
■ 16 bit Timer with a Capture Register and 12 bit
Prescaler;
The Analog Comparator peripheral can also be
used as a single slope A/D, supplying a ramp sig-
nal to the pin CS. The selection of the working
mode, as either Analog Comparator or single
slope A/D can be performed via the
REG_CONF3[(0)] bit.
values,
which
can
be
selected
via
REG_CONF3[(7:5)]. The current values are in the
range between 0 to 70µA with step of 10µA.
The capacitor should have a low voltage coeffi-
Figure 7.1 Analog Peripheral Block Diagram
A/D Configuration Registers
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
CLK
AC0
AC1
AC2
12 bit Presc.
Timer CLK
AC3
AC4
-
Stop Count
Start
16 bit Timer
AC5
+
Converted
Value
NDA
G
Bandgape Ref.=2.5V
CS
Current Sel.
7
6
5
4
3
2
1
0
A/D Configuration Registers
Vcc
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ST52T400/T440/E440/T441
cient for optimum results (recommended capaci-
tance values range is 10-1000 nF). The optimum
linearity in conversion can be obtained if the volt-
age level on the selected input channel does not
exceed a maximum of 3 V. In the second case, if
an external ramp generator is used, the
REG_CONF16[(1)] bit must be set to “1”.
The 16 bit Timer, directly triggered by the output of
the Analog Comparator, allows the measurement
of the conversion time that is proportional to the
analog value.
The device clock is divided by an internal 12 bit
Prescaler to generate the appropriate Timer clock
that allows the desired resolution to be obtained
with a reasonable conversion time.
When an appropriate value of the capacitor is
selected, the conversion should be complete
before the full count is reached. A timer overflow
flag is set once the Timer reaches its maximum
count value.
must be configured to trigger the signal when it
crosses the compared value from low to high
(REG_CONF3[(2)]=0); vice versa, using a falling
ramp, the polarity should be set to trigger the sig-
nal
in
crossing
from
high
to
low
(REG_CONF3[(2)]=1).
When the Capacitor is used, it generates a rising
ramp. For this reason the polarity must be config-
ured to trigger the crossing from low to
high(REG_CONF3[(2)]=0).
In order to synchronize the external ramp signal
and the timer, the ACSTRT and ACSYNC pin
have to be used. The input pin ACSTRT is used to
start the timer when the external ramp is started
(ACSTRT=1). The ACSYNC output pin provides
the handshake signal, which (when ACSYNC=1)
furnishes information indicating that the timer is
ready to receive the start signal.
If the input signal is too high, the counter may
overflow. When this happens, bit 0 of the Input
Register 13 AC_STATUS (Table 2.1) is set to 1
and an interrupt is generated at the end of count.
If the counter is configured in down counting, the
bit is set when the counter goes in underflow.
Generally, the maximum conversion time of the A/
D converter depends on the capacitor chosen and
the charge current. The maximum conversion time
can be calculated by using the following formula:
C(nF) × FullScale(V)
Ch argeCurrent(uA)
7.3.1 Operating Modes.
---------------------------------------------------------
ConversionTime(ms) =
In order to avoid the errors introduced by the A/D
components drift, a periodic conversion of the
internal reference signals can be performed in
order to calibrate the converted values. Two differ-
ent internal voltage references are available:
1) Bandgap voltage, this reference voltage can
also be used externally for analog signal condi-
tioning.
C is the capacitance in nF, FullScale is the maxi-
mum voltage recommended for the input signal,
which is 3 V, and ChargeCurrent is the configured
value of the current for charging the capacitor.
To obtain the desired resolution, the prescaler
value has to be set in accordance to the following
formula:
2) GNDA.
C(nF) × CKM(MHz) × FullScale(V) × 103
Setting the REG_CONF1[(0)] to “1” the peripheral
converts the reference signal after converting
each analog signal. In order to choose the refer-
ence, REG_CONF3[(1)] should be configured.
To ensure secure and stable measurements, sev-
eral measurements on the same channel and
mediating the obtained results are recommended.
The conversion of each single channel may be
repeated up to three times by configuring the
REG_CONF1[(7:6)].
--------------------------------------------------------------------------------------------------------------
P =
– 1
Ch argeCurrent(uA) × 2RESOLUTION
CMK indicates the Master Clock frequency and
Resolution is the number of bits that should con-
tain the converted values. Recommended values
for the resolution are in the range between 8-14
bits.
After the Capacitor is charged, it is discharged in a
number of clock cycles equivalent to (P+1) x 410.
When the external ramp generator is used, a ris-
ing ramp or a falling ramp may be chosen. In this
case, the timer counter should be specified to be
either an up counter (REG_CONF3[(3)]=0) or a
down counter (REG_CONF3[(3)]=1).
The analog multiplexer allows the user to work in
four different modes:
– Single Channel Single Conversion
– Single Channel Multiple Conversions
– Multiple Channels Single Conversion
– Multiple Channels Multiple Conversions
By using a rising ramp the Analog Comparator
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ST52T400/T440/E440/T441
The four modes are selected by configuring
REG_CONF1[(2)] to choose among the conver-
sion of a single channel or a sequence of chan-
nels and REG_CONF1[(1)] to perform the
conversion once or continuously.
The Analog Comparator in A/D Converter Mode
supplies an interrupt source. The interrupt signal
can be generated either after the end of the each
channel conversion (REG_CONF3[(4)]=0) or after.
the
end
of
the
conversion
sequence
REG_CONF1[(5:3)] bits allows the user to choose
the channel to be converted in Single Channel
mode or the last channel to be converted (starting
from AC0) in Multiple Channels mode.
To start the conversion, REG_CONF16[(0)] must
be set to “1” and to “0” to stop it.
Note: in Single conversion modes, the Start bit
REG_CONF16[(0)] must be reset to 0 before
starting another conversion; in Comparator Mode
it must be set to ‘”0”.
(REG_CONF3[(4)]=1).
Table 7.3 Configuration Register 3
Bit
Name
Value
Description
0
1
0
1
0
1
0
1
Comparator Mode
A/D Mode
0
MODE
Reference= GNDA
Reference = 2.42 V
Rising crossing
Falling crossing
Up Counter
1
2
3
REFV
POL
Table 7.1 Configuration Register 1
Bit
Name
Value
Description
UPDW
Down Counter
0
Convert only data
0
REFM
Interrupt after each
conversion
Convert data and
reference value
0
1
4
5
INT
Interrupt after the end
of the conversion
cycle
0
Single Conversion
Continuous Conversion
Single Channel
Multiple Channel
Channel 0 AC0
Channel 1 AC1
Channel 2 AC2
Channel 3 AC3
Channel 4 AC4
Channel 5 AC5
Not used
1
1
CONV
SEQ
1
000
001
010
011
100
101
110
111
Current generator off
10 µA charge current
20 µA charge current
30 µA charge current
40 µA charge current
50 µA charge current
60 µA charge current
70 µA charge current
0
2
3
1
000
001
010
011
100
101
110
111
00
CUR
4
6
7
CHAN
5
Reset Configuration Value = “00000000”
Not used
Table 7.4 Configuration Register 16
6
7
One Conversion
Two Conversion
Three Conversion
Not Used
Bit
Name
Value
Description
01
NBCV
0
A/D Converter Stopped
A/D Converter Started
Capacitor ramp
10
0
STRT
1
11
Reset Configuration Value = “00000000”
0
1
ADM
OD
1
External ramp generator
Table 7.2 Configuration Register 15
2
3
Not used
Bit
Name
Description
7:0
PRES(7:0)
Timer Prescaler (7:0)
7:4
PRES(11:8
Timer Prescaler (11:8)
Reset Configuration Value = “00000000”
Reset Configuration Value = “00000000”
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ST52T400/T440/E440/T441
Figure 7.2 Configuration Register 1
REG_CONF 1
Analog Comparator
D7 D6 D5 D4 D3 D2 D1 D0
REFM: Reference conversion on/off
CONV: Single/Continuous Conversion mode
SEQ: Single/Multiple Channel mode
CHAN: Active Channel(s) Number
NBCV: Number of Conversion
Figure 7.3 Configuration Register 3
REG_CONF 3
Analog Comparator
D7 D6 D5 D4 D3 D2 D1 D0
MODE: Working mode
REFV: Reference voltage
POL: Crossing polarity
UPDW: Up/Down Counter
INT: Interrupt type
CUR: Charge Current
Figure 7.4 Configuration Register 15
REG_CONF 15
Analog Comparator
D7 D6 D5 D4 D3 D2 D1 D0
PRES(7:0): Timer Prescaler (7:0)
Figure 7.5 Configuration Register 16
REG_CONF 16
Analog Comparator
D7 D6 D5 D4 D3 D2 D1 D0
STRT: Converter Start/Stop
ADMOD: Capacitor/external ramp mode
Not used
PRES(11:8): Timer Prescaler (11:8)
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ST52T400/T440/E440/T441
8 WATCHDOG TIMER
frequency divided by a fixed Prescaler with a divi-
sion factor of 500, to obtain WDT CLK signal that
is used to fix the WDT Timeout period (Figure
8.1).
8.1 Functional Description
The Watchdog Timer (WDT) is used to detect the
occurrence of a software fault, usually generated
by external interference or by unforeseen logical
conditions, which causes the application program
to abandon its normal sequence. The WDT circuit
generates an MCU reset on expiry of a pro-
grammed time period (Timeout), unless the pro-
gram refreshes the WDT before the end of the
programmed time period itself.
16 different time delays can be selected by using
the WDT configuration register REG_CONF2 as
in Table 8.2.
WDT is activated by the assembler instruction
WDTRFR.
At the end of the programmed time delay, WDT
starts a reset cycle pulling the reset pin low.
During normal operation, when WDT is active, the
application program has to refresh this peripheral
at regular intervals to prevent an MCU reset. WDT
refresh is performed by the WDTRFR assembler
instruction.
To stop WDT during the user program executions
instruction WDTSLP has to be used.
WDT working frequency is equal to Master Clock
Table 8.1 Watchdog Timing range (CLKM=20
MHz)
WDT Timeout period (ms)
min
0.025
max
234.375
With a Master Clock of 20MHz, for instance, a
WDT Timeout period can be defined between
0.025ms and 234.375ms, depending on WDT
REG_CONF2 values.
Timeout delay values at different Master Clock fre-
quencies can be calculated as the product of WDT
clock number pulses (Table 8.2) by WDT CLK
period (Table 8.4).
Warning: changing the REG_CONF2 value when
the WDT is active, a WDT reset is generated and
the CPU is restarted. To avoid this side effect, use
the WDTSLP instruction before changing the
REG_CONF2.
Figure 8.1 Watchdog Block Diagram
REG_CONF 2
D3
D2
D1 D0
WDT
WDTRFR
RESET
WTD CLK
RESET
RESET
PRESCALER
GENERATOR
PRES CLK = CLK MASTER
WDTSLP
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ST52T400/T440/E440/T441
8.2 Register Description
Table 8.3 Timeout Values with CLKM=5 MHz
WDT Timeout period can be set by setting the first
4 bits of REG_CONF2: this allows 16 different val-
ues of WDT Clock pulse number to be defined.
The WDT CLK is derived from the Master Clock
divided by 500. Timeout is then obtained by multi-
plying the WDT CLK period for the number of
Bit
Name
Value
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
x
Timeout Values
0.1
62.5
0
125
pulses
defined
in
configuration
register
187.5
250
REG_CONF2. Table 8.4 illustrates the pulse
length for typical values of Master Clock.
Table 8.3 illustrates the timeout WDT values when
Master Clock is 5 MHz.
312.5
375
1
2
437.5
500
D(3:0)
Table 8.2 WDT REG_CONF2
Timeout Values (WDT
562.5
625
Bit
Name
Value
CLK pulses)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
1
625
687.5
750
0
1250
1875
2500
3125
3750
4375
5000
5625
6250
6875
7500
8125
8750
9375
Not Used
812.5
875
3
937.5
Not Used
4-7
NC
1
2
Reset Configuration ‘0000’
D(3:0)
Table 8.4 Typical WDT CLK PERIOD
MASTERCLK
(MHz)
WDT CLK
(KHz)
WDT CLK
PERIOD (ms)
4
5
8
0.125
0.1
3
10
16
20
40
8
0.0625
0.05
10
20
0.025
4-7
NC
x
Reset Configuration ‘0000’
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ST52T400/T440/E440/T441
9 PWM/TIMER
ST52x400/440/441 on-chip PWM/TIMER periph-
9.1 Timer Mode
Timer Mode is selected by setting the TxMODE bit
erals consist of an 8-bit counter with a 16-bit pro-
grammable prescaler that provide a maximum
of REG_CONF5[7].
The TIMER can receive three signals as inputs:
Timer Clock (TCLK), Timer Reset (TRES) and
Timer Start (TSTRT) (Figure 9.1). Each of these
signals can be generated internally or externally
by setting TSTR, TRST, TCLK bits of
REG_CONF7 register as illustrated in Table 9.3.
TMRCLK is the Prescaler output, which incre-
ments the Counter value on the rising edge. TMR-
CLK is obtained from the internal clock signal
(CLKM) or from the external signal provided on
the PA5/TCLK pin.
24
count of 2 (Figure 9.1).
The TIMER has two different working modes:
■ Timer Mode
■ PWM (Pulse Width Modulation) Mode that can
be selected by setting register REG_CONF5[7]
bit TMODE.
The Timer has an Autoreload Function in PWM
Mode. Its output TOUT is available, with its com-
plementary signal TOUTN on external pins by set-
ting PA6 and PA2 bits of REG_CONF4 and
REG_CONF12 (see tables - Port A - REG_CONF
4 and - Port A - REG_CONF 12).
The TIMER can also use an external START/
STOP signal (Input capture), an external RESET
and external CLOCK signals: PA4/TSTRT, PA6/
TRES and PA5/TCLK pins. To use TSTRT, TRES,
TCLK external signals the related pins PA4, PA6
and PA5 must be configured in Input Mode by set-
ting registers REG_CONF4 and REG_CONF12
(see table - Port A - REG_CONF 4 and - Port A -
REG_CONF 12).
The content of the 8-bit counter of the TIMER is
incremented on the Rising Edge of the 16-bit pres-
caler output (PRESCOUT) and it can be read at
any instant of the counting phase, which is then
saved in a RAM memory location. The PWM/
Timer Counter value can be read from the Input
Register PWM_COUNT (Input Registers 18, see
Table 2.1). The PWM/Timer Status can be read
from the Input Register PWM_STATUS (Input
Registers 19. See Table 2.1). This register indi-
cates if the TIMER is in START/STOP (bit 1) and
in SET/RESET bit(0).
NOTE: The external clock signal, applied on
TCLK pin, must have a frequency, which is at least
two times smaller than the internal master clock.
The prescaler output can be selected by setting
PRESC bits of REG_CONF6 register (Table 9.2).
TRES resets the content of the TIMER 8-bit
counter to zero. It is generated internally by set-
ting the TIRST bit of REG_CONF5(Table 9.1).
TSTRT signal starts and stops the Timer counting
only if the peripheral is configured in Timer mode.
It is generated internally by setting the TSTR bit of
REG_CONF5(Table 9.1).
TIMER START/STOP can be provided externally
from the TSTRT pin (Input Capture). In this case,
TSTRT signal allows the ICU to work in two differ-
ent modes by setting the TESTR configuration bit
of REG_CONF5 register.
LEVEL: When the TSTRT signal is high the Timer
starts counting. When the TSTRT is low the count-
ing stops and the current value is stored in the
PWMCOUNT Input Register.
Figure 9.1 Timer Peripheral Block Diagram
16-BIT PRESCALER
BIT 5
CLKM
BIT 14
BIT 15
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
PRESCx
17 - 1 MULTIPLEXER
TMRCLK
TxRES
8-BIT COUNTER
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
TxSTRT
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ST52T400/T440/E440/T441
Figure 9.2 Timer 0 External START/STOP Mode
s ta rt
s ta r t
s to p
L e v e l
s to p
s ta r t
s ta r t
E d g e
R e s e t
C lo c k
C o u n te d
V a lu e
2
0
1
3
4
4
0
1
EDGE: After the reset, on the first TSTRT rising
edge, the TIMER starts counting and, at the next
rising edge, it stops. In this manner, the period of
an external signal may be measured.
The Timer output signal waveform type can be
selected by setting the correspondent TMRW bit
of REG_CONF6.
The Timer output signal, TIMEROUT, is a signal
with a frequency equal to the 16 bit-Prescaler out-
put signal, TMRCLK, divided by the Output Regis-
ter PWM_COUNT value (8 bit) (Output Registers
9, Table 2.3), that is the value to count.
TIMEROUT waveform can be of two types:
type 1: TOUT waveform equal to a square wave
with a 50% duty-cycle
9.2 PWM Mode
PWM working mode is obtained by setting the cor-
respondent TMODE bit of REG_CONF5 to “1”.
TIMEROUT, in PWM Mode, consists of a signal,
with a fixed period, whose duty cycle can be mod-
ified by the user.
TIMEROUT signal is available on TOUT pin and
TIMEROUT complementary signal is available on
TOUTN pin, setting the relative bits on PORT A,
REG_CONF12[1] and REG_CONF12[2], to “0”
and REG_CONF4[6] and REG_CONF4[2] to “0”.
The PWM TIMEROUT period can be fixed by set-
ting the 16-bit prescaler output and an initial
autoreload 8-bit counter value stored in the Output
Register PWM_RELOAD, as illustrated in Figure
9.4. The Output Register PWM_RELOAD value is
automatically reloaded in the Counter when it
restarts counting.
type 2: TOUT waveform equal to a pulse signal
with the pulse duration equal to the Prescaler out-
put signal.
Figure 9.3 TIMEROUT Signal Type
Prescout*Counter
Timer Output
Type 1
NOTE: the Start/Stop and Set/Reset signals
should be moved together in PWM mode. If the
Start/Stop bit is reset during the PWM mode work-
ing, the TxOUT signal keeps its status until the
next start.
Type 2
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ST52T400/T440/E440/T441
Figure 9.4 PWM Mode with Auto Reload
255
compare
value
reload
register
0
t
t
PWM
Output
Ton
T
The 16-bit Prescaler divides the master clock,
CLKM or the external signal TCLK. The Prescaler
output can be selected setting the PRESC bit of
REG_CONF6.
NOTE: The external clock signal, applied on
TCLK pin, must have a frequency that is at least
two times smaller than the internal master clock.
When the Counter reaches the Peripheral Regis-
ter PWM_COUNT value (Compare Value), the
TIMEROUT signal changes from high to low level,
up to the next counter start.
NOTE. If the PWM_RELOAD value increases, the
duty cycle resolution decreases.
By using a 20 MHz Master Clock a PWM fre-
quency in the range between 1.2 Hz to 78.43 Khz
may be obtained.
NOTE: The Timer, before using a new value of the
counter or of the reload, has to complete the previ-
ous counting. If the counter/reload value is
changed during counting, the new value of the
timer counter is used only at the end of the previ-
ous counting phase. This happens both in Timer
and in PWM mode.
The period of the PWM signal is obtained by using
the following formula:
T= (255-PWM_RELOAD)*TMRCLK
WARNING: loading new values of the reload in
the PWM_x_RELOAD registers, the PWM/Timer is
immediately set on-fly. This can cause some side
effects during the current counting cycle. The next
cycles work normally. This occurs both in Timer
and in PWM mode.
where TMRCLK is the output of the 16-bit pres-
caler. The duty cycle of the PWM signal is
controlled by the Output Register PWM_COUNT:
Ton =(PWM_COUNT- PWM_RELOAD)* TMRCLK
If the Output Register PWM_COUNT value is 255
the TIMEROUT signal is always at high level.
If the Output Register PWM_COUNT is 0, or less
than the PWM_RELOAD value, TIMEROUT sig-
nal is always at low level.
When the Timer is in Reset, or when the device is
reset, the TOUT pin goes to threestate: it is rec-
ommended to use a pull-up or a pull-down resistor
if this output is used to drive an external device.
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ST52T400/T440/E440/T441
9.3 Timer Interrupt
The TIMER can be programmed to generate an
The Interrupt mode can be selected by means of
INTSL and INTE bits of the REG_CONF5.
Interrupt request until the end of the count or when
there is an Timer Stop signal (TSTRT). The Timer
can generate programmable Interrupts into 4 dif-
ferent modes:
NOTE: the interrupt on TIMEROUT rising edge is
also generated after the Start.
WARNING: If the PWM/Timer is configured with
the Interrupt on Stop and the Start/Stop is
configured as external, a low signal in the STRT
pin determines a PWM/Timer interrupt even if the
peripheral is off. If the interrupt is configured on
falling edge, a reset signal generates an interrupt
request.
Interrupt mode 1: Interrupt on Timer Stop.
Interrupt mode 2: Interrupt on Rising Edge of
TIMEROUT.
Interrupt mode 3: Interrupt on Falling Edge of
TIMEROUT.
Interrupt mode 4: Interrupt on both edges of
TIMEROUT.
Table 9.1 Configuration Register 5 Description
Bit
Name
Value
0
Description
Internal RESET
0
TIRST
1
Internal SET
0
External RESET on Level
External RESET on Edge
Internal STOP
1
2
3
4
5
6
7
TERST
TISTR
TESTR
1
0
1
Internal START
0
External START on Level
External START on Edge
TIMER Interrupt on TIMEROUT Falling Edge
TIMER Interrupt on TIMEROUT Rising Edge
TIMER Interrupt on Both Edges of TIMEROUT
- not used
1
00
01
10
11
0
INTE
TIMER Interrupt on Counter Stop
TIMER Interrupt on TIMEROUT Edges
TIMER MODE
INTSL
1
0
TMODE
1
PWM MODE
Reset Configuration = “00000000”
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ST52T400/T440/E440/T441
Figure 9.5 Configuration Register 5
REG_CONF 5
TIMER
D7 D6 D5 D4 D3 D2 D1 D0
TIRST: Timer Internal RESET
TERST: Timer External RESET on Edge/Level
TISTR: Timer Internal START
TESTR: Timer External START on Edge/Level
INTE: Timer Interrupt on TIMER0OUT Rising/Falling Edge
INTSL: Timer Interrupt Source selection
TMODE: Timer working mode
Reset Configuration = “00000000”
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Table 9.2 Configuration Register 6 Description
Bit
Name
Value
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
0
Description
TIMER Clock = CLKM / 1
TIMER Clock = CLKM / 2
TIMER Clock = CLKM / 4
TIMER Clock = CLKM / 8
TIMER Clock = CLKM / 16
TIMER Clock = CLKM / 32
TIMER Clock = CLKM / 64
TIMER Clock = CLKM / 128
TIMER Clock = CLKM / 256
TIMER Clock = CLKM / 512
TIMER Clock = CLKM/1024
TIMER Clock = CLKM/2048
TIMER Clock = CLKM/4096
TIMER Clock = CLKM/8192
TIMER Clock=CLKM/16384
TIMER Clock=CLKM/32768
TIMER Clock=CLKM /65536
TIMEROUT Pulse type waveform
TIMEROUT Square type waveform
Not used
0
1
2
3
PRESC
4
5
TMRW
1
6
7
-
-
-
-
Not used
Figure 9.6 Configuration Register 6
REG_CONF 6
TIMER
D7 D6 D5 D4 D3 D2 D1 D0
PRESC: Timer Prescaler
TMRW: TIMEROUT waveform
not used
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ST52T400/T440/E440/T441
Table 9.3 Configuration Register 7 Description
Bit
Name
Value
00
01
10
11
00
01
10
11
0
Description
TIMER RESET Internal
TIMER RESET External
TIMER RESET External or Internal
Not used
0
TRST
1
2
3
4
TIMER START Internal
TIMER START External
TIMER START External or Internal
Not used
TSTR
TCLK
TIMER Clock Internal
TIMER Clock External
Must be kept to “0”
Not used
1
5
6
7
NC
NC
NC
0
-
-
Not used
Reset Configuration = “00000000”
Figure 9.7 Configuration Register 7
REG_CONF 7
TIMER
D6 D5
D3
D0
D2 D1
D7
D4
TRST: Timer RESET Mode
TSTR: Timer START Mode
TCLK: Timer Clock Source
Not used
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ST52T400/T440/E440/T441
10 TRIAC/PWM DRIVER
ST52x400/440/441 offers a peripheral able to
Figure 10.1 illustrates the internal structure of the
Triac/PWM Driver.
generate a TROUT signal on PA0 pin (able to sup-
ply up to 25 mA), to drive an external device, like a
TRIAC, an IGBT or a Power MOS. A Triac/PWM
driver can perform 3 different working modes
according to REG_CONF10(3:2) bits, MODE (see
Table 10.3):
PWM Mode
The PWM working mode selection can be
obtained by setting REG_CONF10(3:2) bits,
MODE, at “00" value.
In this working mode, the peripheral provides a
signal with a fixed period and a variable duty cycle
on the TROUT pin.
The PWM period can be generated starting from
the internal master clock or an external clock sig-
nal applied in MAIN1 pin.
MODE = “00”:
MODE = “01":
PWM
Burst Mode Triac Control
(Thermal Regulations)
In both cases, the clock signal is divided by a 16-
bit Prescaler, managed by REG_CONF8 and
REG_CONF9 (Figure 10.2).
MODE = “1x":
Phase Angle Partialization
Triac Control (Motor Control)
At each period, the duty cycle is fixed by an 8-bit
value loaded in the TRIAC_COUNT register (Out-
put Register 9). The duty cycle is proportional to
the value: loading 50% duty cycle is obtained,
loading 0 the output will be low (off) during all the
period, loading 255 will be high (on).
By Using a 20 Mhz clock PWM frequencies in the
range between 1.2 Hz to 78.4 Mhz may be
obtained.
The Triac/PWM Driver can be initialized by using a
value fixed by a control algorithm, and stored in
the Register File. The value is loaded in the
TRIAC_COUNT register (Output Register 9) by
using the LDPR instruction and it can be read by
using the LDRI instruction addressing the Input
Register 17.
Figure 10.1 TRIAC/PWM Driver Block Diagram
TRIACOUT
REG_PERIPH_9
MCLK
8
POL
TRIAC/PWM DRIVER
CORE
REG_CONF8
REG_CONF9
PRESCALER
16 bit
Tck
16
PROGRAMMABLE
COUNTER
MCLK
EXTCLK
PRECLK
50/60 Hz
MODE
START
RESET
÷2
MAIN1
MAIN2
PULSE
GENERATOR
0
1
2
3
4
5
6
7
REG_CONF10
Tck
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ST52T400/T440/E440/T441
Burst Mode
Phase Angle Partialization Mode
The Burst principle is based on turning the TRIAC
device on and off for a fixed integer number of
mains voltage periods, in order to control the
power transferred to the load.
In Burst Mode the peripheral provides a signal,
with a fixed period T containing an integer number
of pulses corresponding to the main voltage zero
crossings, with a Duty Cycle that is proportional to
the number of pulses that keep the TRIAC on (Fig-
ure 10.4).
The user can define the period T by means of the
internal 16-bit prescaler, setting REG_CONF8 and
REG_CONF9 (Figure 10.2). T is proportional to
the main voltage period and is in the range [5.10,
334233.6]s if the main frequency is 50Hz.
The duty cycle is fixed at each period by an 8-bit
value loaded in the TRIAC_COUNT register (Out-
put Register 9). The duty cycle is proportional to
the value: loading 50% duty cycle is obtained,
loading 0 the output will be low (off) during all the
period, loading 255 will be high (on).
Phase Angle Partialization method is based on
turning on the TRIAC device only for a part (Phase
Angle) of each main voltage period. When the
phase angle is large, the energy (power) supplied
to the load is low, viceversa when the phase angle
is small, the energy supplied to the load is high.
In order to work in Phase Angle Partialization
mode, the zero-crossing of main voltage must be
detected by using an external inserting circuitry
connected to the MAIN1 and MAIN2 pins or,
optionally, only on MAIN1 pin (Figure 10.10).
In this working mode, the peripheral provides eight
pulses after the time corresponding to the Phase
Angle on the TROUT pin, obtained by setting the
TRIAC_COUNT 8-bit register (Output Register 9)
and
the
Prescaler
(REG_CONF8
and
REG_CONF9). By modifying the TRIAC_COUNT
register the Phase Angle is controlled.
10.1 TRIAC/PWM Driver Setting
The TRIAC/PWM Peripheral can be SET or
The width and the polarity of the pulses can be
programmed according to the TRIAC device and
the circuit characteristics.
In order to work in Burst mode, the pre-post zero-
crossing of main voltage must be detected by
using an external inserting circuitry connected to
the MAIN1 and MAIN2 pins (Figure 10.5).
This kind of TRIAC control is mainly used for ther-
mal regulation.
RESET through REG_CONF10(7) bit TCRST
(Table 10.3) in all three working modes.
If the TRIAC/PWM Peripheral is SET and only in
PWM mode, it is possible to START or STOP the
internal counter of the peripheral without resetting
it, through REG_CONF10(5) bit TCST (Table
10.3), in order to use the peripheral as an addi-
tional Timer. In the other modes the TCST bit
must be kept to “1”.
NOTE: if TCRST is 0 (reset status) the TROUT
pin output is in tristate.
Figure 10.2 TRIAC/PWM Configuration Registers 8 and 9
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ST52T400/T440/E440/T441
10.2 PWM Mode Settings
By using the 16-bit Prescaler (REG_CONF8 and
The value Ton depends on the value set by the
user in the TRIAC_COUNT Register (Output Reg-
ister 9) by using the LDPR instruction. Ton and the
corresponding duty cycle can be calculated from
the following formulas:
REG_CONF9), the PWM period can be generated
by dividing the internal master clock, an external
clock signal applied to pin MAIN1, or the mains
voltage frequency, using the circuit of Figure
10.10.
Ton=TRIAC_COUNT * Tck
Duty=TRIAC_COUNT / 255
NOTE: The external clock signal applied on
MAIN1 pin must have a frequency that is at least
two times smaller than the internal master clock.
The clock source can be selected by using
REG_CONF10(4) bit, CKSL (Table 10.3).
The period T of the PWM signal Tb (see Figure
10.4) can be calculated with the following formula:
T= 255*Tck
The TRIAC_COUNT value can be changed on fly
but it is updated only at the end of the signal
period. If TRIAC_COUNT value is 255 then Toff is
zero and TROUT signal is always equal to one
during the period T.
According to REG_CONF10(0) configuration reg-
ister bit, POL, the firing pulses polarity must be
set.
where Tck is the period of the signal in output of
the 16-bit prescaler, according to the value stored
in REG_CONF8 and REG_CONF9 pair (Figure
10.2).
By using a 20 MHz clock master a PWM fre-
quency in the range 1.2 Hz to 78.4KHz may be
obtained (Table 10.1).
IN PWM mode, it is possible to generate a pro-
grammable Interrupt in four different ways:
1) No Interrupt;
2) Interrupt on rising edge of the signal Tb
(INT_R).
3) Interrupt on falling edge of the signal Tb
(INT_F)
4) Interrupt on both edges of the signal Tb.
The Interrupt sources described above are always
Table 10.1 PWM Frequencies
active;
they
can
be
masked
through
REG_CONF0(5:3) bits, INTSL (see Table 4.1).
1/T
MCLK
Frequencies
min
max
NOTE: If the Interrupt on the rising edge (INT_R)
is not masked through REG_CONF0(4), the first
Interrupt after the start occurs with a delay of a
time period T. If TRIAC_COUNT is 255 or 0, the
first interrupt after the start (either INT_R and
INT_F) occurs at time T. In any case for
TRIAC_COUNT equal to 255 or 0, INT_R and
INT_F coincide and occur at each control period T.
5 MHz
10 MHz
20 MHz
1.2 Hz
0.6 Hz
0.3 Hz
19.6 KHz
39.2 KHz
78.4 KHz
Figure 10.3 PWM Working Mode
T = 255 * Tck
Ton = INIT_VALUE* Tck
Toff
TRIACOUT
65/94
ST52T400/T440/E440/T441
10.3 Burst Mode
When working in Burst mode, the synchronization
and cannot be changed on fly.
The first pulse is obtained during the first zero
crossing of the main voltage and the last one is
generated after clock pulses included in the time
period TRIAC_COUNT*Tck, where Tck is the
Prescaler output, generated by using the main
voltage frequency applied to MAIN1 and MAIN2
pins. This guarantees synchronization with the
mains voltage frequency.
Ranges of the Tb signal period depend on the
power line frequency and Prescaler (Table 10.2).
In order to drive a Triac in Burst Mode a pulse
sequence must be generated, which must be cen-
tered on the zero crossing of the power line as
illustrated in Figure 10.7. Therefore, the pre zero
crossing and the post zero crossing of the power
line must be detected.
with the mains is mandatory, therefore
REG_CONF10(4) bit CKSL must be set to “1”.
(Table 10.3).
A square wave Tb is generated with a duty cycle
proportional to the power the user needs to trans-
fer to the load. A pulse is generated for each zero
crossing of the mains voltage included in the Ton
of the fixed period T. Figure 10.4 illustrates the
typical Burst Control working mode. The period T
of the signal Tb (Figure 10.4) is:
T = 255*Tck
The signal Tck is generated by programming the
16-bit
Prescaler
by
REG_CONF8
and
REG_CONF9 (Figure 10.2). Tck is equal to the
mains voltage frequency (50 or 60 Hz) divided by
N+1, where N is an integer value in the range [0,
To detect the zero-crossing and also obtain the
main voltage frequency, the user must generate
MAIN1 and MAIN2 signals by using the circuit
illustrated in Figure 10.5.
MAIN1 and MAIN2 signals are used in the block
called PULSE GENERATOR of the peripheral
(see Figure 10.1).
16
2
-1].
The value Ton is proportional to the value con-
tained in TRIAC_COUNT Register (Output Regis-
ter 9)
The number of generated pulses N_PULSES in
TROUT pin is equal to:
N_PULSES = 2*[(N+1)*TRIAC_COUNT]
where N is the value stored in the 16-bit prescaler.
Therefore it is:
Table 10.2 TROUT Signal Period
T
Power Line
Frequency
Ton = TRIAC_COUNT*Tck
The TRIAC_COUNT can be changed on fly and
takes effect from the following period; the Pres-
caler value N instead is fixed since the beginning
min
max
50 Hz
60 Hz
5.10 s
4.25 s
334233.60 s
278528.05 s
Figure 10.4 Burst Working Mode
T = 255 * Tck
Ton
Tb
1.5
1
0.5
0
Power
Line
-0.5
-1
-1.5
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ST52T400/T440/E440/T441
In particular, the pulses are generated by using
the rising edge of the signal MAIN1 and the falling
edge of the signal MAIN2. Figure 10.6 illustrates
the generation of the Triac pulses Tp.
The first firing pulse for the Triac is generated on
the zero crossing of the power line, while the next
pulses are centered on the zero crossing. Gener-
ally, the Triac firing pulses start 1/2 Tp before the
zero crossing and the length of the pulses is Tp,
see Figure 10.6.
T = T
* UTP
CLKM
P
The value Tp is in the range [0, 3.2] ms when the
clock master is 20 MHz.
According to REG_CONF10(0) configuration reg-
ister bit, POL, the firing pulses polarity may be set;
in order to obtain positive or negative gate Triac
currents, allowing to work respectively in I and IV
quadrants, or in the II and III quadrants (see Fig-
ure 10.6).
The pulses polarity can be changed on fly with
immediate effect.
The length Tp of the pulses is programmable by
using
REG_CONF19
a
16 bit value UTP, obtained with
bits, UTPMSB, and
Working in the II and III quadrant the peripheral
implements the following procedure:
REG_CONF20, UTPLSB (see Figure 10.12 and
Table 10.5):
1) The firing pulse is set to “1" on the rising edge
Figure 10.5 Burst Mode Zero Crossing Circuit
Figure 10.6 Burst Mode Zero Crossing Circuit
Figure 10.7 Burst Mode Zero Crossing
1
0.5
Power
0.5
Line
0
Main Voltage
0
(0.5)
-0.5
(1)
Positive Ig
II and III quadrants
Tp
Tp
Tp
Triac Gate
-1
Current
TRIACOUT
-1.5
I and IV quadrants
Ig
Negative
Triac Gate
Current
MAIN1
½ Tp
½ Tp
Tp
MAIN2
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ST52T400/T440/E440/T441
of MAIN1.
(Figure 10.9) and T1 is:
T1 =TRIAC_COUNT* T
2) The firing pulse is reset to “0" after the time Tp
fixed by program.
* (N+1)
CKLM
being T
master clock period and N the Pres-
CKLM
3) On the falling edge of MAIN2 the firing pulse is
set to “1"
4) The firing pulse is reset to “0" after the time Tp
fixed by program.
It is possible to generate a programmable Inter-
rupt in the following ways:
1) No Interrupt;
2) Interrupt on the rising edge of the signal Tb
(INT_R)
3) Interrupt on the falling edge of the signal Tb
(INT_F)
4) Interrupt on both edges of the signal Tb.
5) Interrupt on each Triac pulse (INT_P)
If pulse width or TRIAC_COUNT are set to zero,
no pulse on TROUT pin is generated and INT_P
interrupt does not occur.
caler value (Configuration Registers 8 and 9).
NOTE: The user must verify that time T1 is not
larger than a fixed time Tmax (8ms at 50 Hz) in
order to avoid the firing of the Triac in the second
half period of the mains voltage and to choose a
suitable Prescaler value to avoid the shifting of the
pulse sequence in the following semi-period.
In order to avoid problems for the Triac firing when
the load is inductive 8 different pulses are gener-
ated by the peripheral (Figure 10.10). Their width,
equal the semiperiod Ti/2, is programmable by
using registers REG_CONF19 (UTPMSB) and
REG_CONF20 (UTPLSB) and is provided by the
formula:
Ti/2 = T
*UTP
CLKM
NOTE: the choice of UTP value must be done by
the user paying attention to the fact that the dura-
tion of the 8 pulses train must be such that added
to T1, it does not fall into the second half period of
the mains voltage. In fact by using a clock master
equal to 20 MHz and the full 16 bit value by
ConfReg19 and 20, the pulse width would be in
the range [0.2, 3.28] ms.
The duty cycle of Ti pulse is always 50%. The
choice of the pulse width must be done according
to TRIAC device specifics and must be set from
the beginning of the program. To change width
during program execution it is necessary to
RESET the peripheral.
The Interrupt sources described above are always
active;
they
can
be
masked
through
REG_CONF0(5:3) bits, INTSL (see Table 4.1).
10.4 Phase Angle Partialization Working Mode
In this mode Triac is controlled each semi-period
of the mains voltage. The power transferred to the
load is proportional to the CURRENT FLOW
ANGLE γ. This kind of Triac control is suitable to
drive the Triac with inductive load (i.e. universal or
monophase motors). Figure 10.8 illustrates the
relation between the Phase Angle α and the Cur-
rent Flow Angle γ .
The peripheral allows to control the Phase Angle
or equivalently time T1 (see Figure 10.9). It is pos-
sible to change Time T1 setting the contents of the
TRIAC_COUNT register (Output Register 9). T1 is
proportional to the value loaded in the
TRIAC_COUNT register.
According to REG_CONF10(0) configuration reg-
ister bit, POL, the firing pulses polarity must be
set.
A programmable interrupt may be generated in
four different ways:
1) no Interrupt;
Different circuits for the zero crossing detection
may be used, but MAIN1 signal rising edge must
always be synchronized with the mains voltage
zero crossing and MAIN2 signal falling edge must
be synchronized with the following mains voltage
zero crossing.
By using the external circuit illustrated in Figure
10.10, only one synchronization signal from the
mains may be used, MAIN1. In this case,
REG_CONF10(6) must be set to “1”, MAIN2 sig-
nal coincides internally with MAIN1 and MAIN2 pin
is left free for other functions. If main voltage fre-
quency is equal to 50 Hz, then Tr is equal to 20 ms
2) Interrupt on the rising edge of the signal MAIN1
(INT_R)
3)Interrupt on the falling edge of the signal MAIN2
(INT_F)
4) Interrupt on both the edges of the signal MAIN1
5) Interrupt on rising edge of first pulse after T1
(INT_P)
If UTP is 0, TROUT signal remains at 0 (or 1, if
POL=1), however after the time T1, the interrupt
INT_P is generated.
The Interrupt sources described above are always
active;
they
can
be
masked
through
REG_CONF0(5:3) bits, INTSL (see Table 4.1).
68/94
ST52T400/T440/E440/T441
Figure 10.8 Phase angle Partialization Mode
.
VA2-A1
1
0.5
L
Load
0
Il
A2
α
1.5
(0.5)
Phase Angle
Il1
A1
(1)
N
0.5
(1.5)
0
(0.5)
(1)
γ
Current Flow Angle
Table 10.3 Configuration Register 10
Table 10.4 Configuration Register 19
Bit
Name
Value
Description
Set Positive Output
Pulse Polarity
0
Bit
Name
Value
Description
0
POL
Output Impulse
Width most
significative bit
Set Negative Output
Pulse Polarity
0 - 7
UTPMSB
1
1
2
-
-
Not used
PWM Mode
00
01
1X
0
Table 10.5 Configuration Register 20
MODE
Burst Mode
Bit
Name
Value
Description
3
4
Phase Partialization
Internal Clock Master
Output Impulse
Width least
0 - 7
UTPLSB
CKSL
TCST
External Clock
on Main1
significative bit
1
Reset Configuration = “00000000”
0
1
Triac Stop
Triac Start
5
6
7
Figure 10.9 Phase Angle Partialization Mode
Set MAIN2 as
Alternate Function
Tr
0
1
Mai1n.s5
Voltage
Tr/2
IOSL
1
MAIN2 coinciding with
MAIN1
Ti
0.5
0
0
1
Triac Reset
Triac Set
T1
TCRST
T1
(0.5)
(1)
Reset Configuration = “00000000”
Tmax
(1.5)
8 mS
10 mS
20 mSec
69/94
ST52T400/T440/E440/T441
Figure 10.10 Phase Angle Partialization Zero Crossing Circuit
VDD
A/C – D/C
Adaptor
MAIN1
J1
1
2
220 k
220 V
AC
Figure 10.11 TRIAC/PWM Configuration Registers 10
REG_CONF10
TRIAC/PWM
D7 D6 D5 D4 D3 D2 D1 D0
POL: Pulses polarity
Not Used
MODE: Peripheral working mode
CKSL: Clock Selector
TCST: TRIAC Stop
IOSL: MAIN2 Selector
TCRST: TRIAC Set/Reset
70/94
ST52T400/T440/E440/T441
Figure 10.12 TRIAC/PWM Configuration Registers 19 and 20
REG_CONF19
TRIAC/PWM
D7 D6 D5 D4 D3 D2 D1 D0
UTPMSB: Output Pulse Width
REG_CONF20
TRIAC/PWM
D7 D6 D5 D4 D3 D2 D1 D0
UTPLSB: Output Pulse Width
71/94
ST52T400/T440/E440/T441
11 ELECTRICAL CHARACTERISTICS
11.1.4 Loading capacitor. The loading condition
used for pin parameter measurement is illustrated
in Figure 11.1.
11.1 Parameter Conditions
Unless otherwise specified, all voltages are
11.1.5 Pin input voltage.
referred to V
ss.
Input voltage measurement on a pin of the device
is described in Figure 11.2
11.1.1 Minimum and Maximum values.
Unless otherwise specified, the minimum and
maximum values are guaranteed in the worst
conditions of environment temperature, supply
voltage and frequencies production testing on
100% of the devices with an environmental
Figure 11.2 Pin input Voltage
temperature at T =25°C and T =T max (given by
A
A
A
the selected temperature range).
Data is based on characterization results, design
simulation and/or technology characteristics are
indicated in the table footnotes and are not tested
in production. The minimum and maximum values
are based on characterization and refer to sample
tests, representing the mean value plus or minus
three times the standard deviation (mean ±3Σ).
ST52 PIN
11.1.2 Typical values.
Unless otherwise specified, typical data is based
VIN
on T =25°C, V =5V (for the 4.5≤V ≤5.5V
A
DD
DD
voltage range). They are provided only as design
guidelines and are not tested.
11.1.3 Typical curves.
Unless otherwise specified, all typical curves are
provided only as design guidelines and are not
tested.
Figure 11.1 Pin loading conditions
11.2 Absolute Maximum Ratings
Stresses above those listed as “absolute maximum
ratings” may cause permanent damage to the
device. This is a stress rating only.
Functional operation of the device under these
conditions is not implied. Exposure to maximum
rating conditions for extended periods may affect
device reliability.
ST52 PIN
CL
72/94
ST52T400/T440/E440/T441
Table 11.1 Voltage Characteristics
Symbol
Ratings
Supply voltage
Maximum Value
Unit
V
V
-V
6.5
50
DD SS
Variation between digital and analog ground pins
Input voltage on Vpp
mV
|V
-V
|
SSA SS
V
-0.3 to 13
SS
V
IN
V
1) & 2)
V
-0.3 to V +0.3
Input voltage on any other pin
SS
DD
V
Electro-static discharge voltage
4000
DESD
Table 11.2 Current Characteristics
Symbol
Ratings
Total current in V power lines (source)
Maximum Value
Unit
3)
I
100
VDD
DD
3)
I
100
Total current in V ground lines (sink)
VSS
SS
Output current sunk by any standard I/O and control pin
Output current source by any I/Os and control pin
25
-25
±5
±5
±5
I
IO
mA
Injected current on V pin
PP
Injected current on RESET pin
I
INJ(PIN)
Injected current on OSCin and OSCout pins
4)
±5
Injected current on any other pin
4)
ΣI
±20
Total Injected current (sum of all I/O and control pins)
INJ(PIN)
Table 11.3 Thermal Characteristics
Symbol
Ratings
Maximum Value
-65 to +150
150
Unit
°C
T
Storage temperature range
STG
T
J
Maximum junction temperature
°C
Notes:
1. Connecting RESET and I/O Pins directly to VDD or VSS could damage the device if the unintentional internal reset is generated
or an unexpected change of I/O configuration occurs (for example, due to the corrupted program counter). In order to guarantee
safe operation, this connection has to be performed via a pull-up or pull-down resistor (typical: 4.7k Ω for RESET, 10K Ω for I/Os).
Unused I/O pins must be tied in the same manner to VDD or VSS according to their reset configuration.
2. When the current limitation is not possible, the VIN absolute maximum rating must be respected, otherwise refer to I INJ(PIN)
specification. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSSto I INJ(PIN) specification.
A positive injection is VIN>VDD while a negative injection is induced by VIN<VSS.
3. All power (VDD) and ground (VSS) lines must always be connected to the external supply.
4. When several inputs are submitted to a current injection, the maximum ΣI
injected currents (instantaneous values).
is the absolute sum of the positive and negative
INJ(PIN)
73/94
ST52T400/T440/E440/T441
11.3 Recommended Operating Condition
Operating condition: VDD=5V±10%; TA=0/125°C (unless otherwise specified).
Table 11.4 Recommended Operating Conditions
Symbol
Parameter
Operating Supply
Programming Voltage
Output Voltage
Test Condition
Min.
2.7
Typ.
Max
5.5
Unit
2)
Refer to Figure 11.3
V
DD
V
11.4
12
12.6
PP
V
V
V
V
O
SS
DD
V
Analog Ground
V
-0.3
V
V
+0.3
SS
SSA
SS
SS
1)2)
Oscillator Frequency
1
20
MHz
f
OSC
Notes:
1. It is reccomendend to insert a capacitor beetwen V
and V
for improving noise rejection. Rec-
DD
SS
comended values are 10 µF (electrolytic or tantalum) and/or 100 nF (ceramic).
2. A lower V decreasing f
(see Figure 11.3). Data illustrated in the figure are characterized but not
osc
DD
tested.
Figure 11.3 fosc Maximum Operating Frequency versus VDD supply (*)
20
18
16
14
Functionality not guaranteed in this area
12
10
8
Functionality guaranteed in this area
6
4
2
0
Functionality not guaranteed in this area
3.5 4.5 5.5
0
1
1.5
2
2.5
3
0.5
4
5
Vdd (V)
(*) Only digital parts of the device: the Analog Comparator cannot work with supply voltage lower
than 4.5 V.
74/94
ST52T400/T440/E440/T441
11.4 Supply Current Characteristics
The test condition in RUN mode for all the IDD
measurements are:
Supply current is mainly a function of the operating
voltage and frequency. Other factors such as I/O
pin loading and switching rate, oscillator type,
internal code execution pattern and temperature,
also have an impact on the current consumption.
OSCin = external square wave, from rail to rail;
OSCout = floating;
All I/O pins tristated pulled to VDD
TA=25°C
Table 11.5 Supply Current in RUN and WAIT Mode
3)
Symbol
Parameter
Conditions
Typ
Unit
Max
f
f
=2 Mhz
=4 Mhz
6.48
7.95
9.08
15.5
28.3
4.4
6.48
8.16
9.27
15.6
28.92
4.41
6.09
6.89
12.31
23.07
osc
osc
1)
Supply current in RUN mode
f
=5 Mhz,
osc
f
f
=10
=20
osc
osc
V
=5V±5%
DD
I
mA
DD
f
f
f
=2 MHz
=4 MHz
=5 MHz
TA=25°C
osc
osc
osc
6.0
2)
Supply current in WAIT mode
6.6
f
f
=10
=20
12.2
23.0
osc
osc
Notes:
1. CPU running with memory access, all I/O pins in input mode with a static value at V
peripherals switched off; clock input (OSCin driven by external square wave).
(no load), all
DD
2. CPU in WAIT mode with all I/O pins in input mode with a static value at V (no load), all peripherals
DD
switched off; clock input (OSCin driven by external square wave).
3. Data based on characterization results, tested in production at V
and f
.
oscmax
DDmax
Figure 11.4 Typical IDD in RUN vs fosc
Figure 11.5 Typical IDD in WAIT vs fosc
35
30
25
20
15
10
5
30
25
20
15
10
5
0
0
2.0
3.0
4.0
5.0
6.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD [ V]
VDD [V]
2MHz
4MHz
5MHz
10MHz
20MHz
2MHz
4MHz
5MHz
10MHz
20MHz
75/94
ST52T400/T440/E440/T441
Table 11.6 Supply Current in HALT Mode
1)
Symbol
Parameter
Conditions
Max
Unit
Typ
2)
I
3.0 V≤ VDD ≤ 5.5 V
0.6
0.68
µA
DD
Supply current in HALT mode
Notes:
1. Typical data is based on TA = 25 °C
2. All I/O pins in input mode with a static value at VDD (no load)
11.5 Brown-Out Detector characteristics
Table 11.7 Brown-out detector
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
V
BOD
BOD Threshold low
BOD Threshold high
3.8
4.1
L
BOD
V
H
clock
cycles
t
Duration of filtered noise
100
BODL
Notes:
1. Data based on characterization results
2. Measurement done with dV/dt fixed
76/94
ST52T400/T440/E440/T441
11.6 Clock and Timing Characteristics
Operating Conditions: VDD=5V ±5%, TA=0/125°C, unless otherwise specified
Table 11.8 General Timing Parameters
Symbol
Parameters
Oscillator Frequency
Clock High
Test Condition
Min
1
Typ.
Max
20
Unit
f
MHz
osc
t
25
25
250
250
CLH
t
Clock Low
CLL
SET
HLD
t
Setup
See Fig. 11.6
See Fig. 11.6
5
5
t
Hold
t
Minimum Reset Pulse
Minimum External
Input Rise Time
Input Fall Time
Output Rise Time
Output Fall
f
f
=20MHz
=20MHz
100
100
WRESET
osc
osc
nS
t
WINT
t
See Fig. 11.7
See Fig. 11.7
15
15
IR
t
IF
t
C
C
=10pF
=10pF
10
10
OR
LOAD
LOAD
t
OF
Figure 11.6 Data Input Timing
Figure 11.7 I/O Rise and Fall Timing
tCLL
tCLH
50%
tCP
50%
Data
tSET tHLD
50%
Clock
77/94
ST52T400/T440/E440/T441
11.7 Memory Characteristics
Subject to general operating conditions for VDD, fosc and TA, unless otherwise specified.
Table 11.9 RAM and Registers
Symbol
Parameter
Conditions
Min.
Typ.
Max
Max
20
Unit
Data retention
HALT mode (or
RESET)
VRM
1.6
V
1)
mode
Table 11.10 EPROM Program Memory
Symbol
Parameter
Conditions
Min.
Typ.
Unit
Lamp
wavelength
2537 A
Watt,
WERASE
UV lamp
15
2)
sec/cm
UV lamp is
placed 1 inch
from the device
window without
any interposed
filters
2)
tERASE
10
20
min.
Erase time
tRET
Data Retention
years
TA =+55°C
Notes:
1. Minimum VDD supply voltage without losing data stored into RAM (in HALT mode or under RESET) or
into hardware registers (only in HALT mode). Guaranteed by construction, not tested in production.
2. Data is provided only as a guideline.
78/94
ST52T400/T440/E440/T441
11.8 ESD Pin Protection Strategy
presented in Figure 11.8 and Figure 11.9 for
standard pins.
In order to protect an integrated circuit against
Electro-Static Discharge the stress must be
controlled to prevent degradation or destruction of
the circuit elements. Stress generally affects the
circuit elements, which are connected to the pads
but can also affect the internal devices when the
supply pads receive the stress. The elements that
are to be protected must not receive excessive
current, voltage, or heating within their structure.
11.8.1 Standard Pin Protection
In order to protect the output structure the following
elements are added:
- A diode to V (3a) and a diode from V (3b)
DD
SS
- A protection device between V and V (4)
DD
SS
In order protect the input structure the following
elements are added:
An ESD network combines the different input and
output protections. This network works by allowing
safe discharge paths for the pins subject to ESD
stress. Two critical ESD stress cases are
- A resistor in series with pad (1)
- A diode to V (2a) and a diode from V (2b)
DD
SS
- A protection device between V and V (4)
DD
SS
Figure 11.8 Safe discharge path subjected to ESD stress
VDD
VDD
(3a)
(2a)
(1)
OUT
(4)
IN
Main path
Path to avoid
(3b)
(2b)
VSS
VSS
Figure 11.9 Negative Stress on a Standard Pad vs. VDD
VDD
VDD
(3a)
(2a)
(1)
OUT
(4)
IN
Main path
(3b)
(2b)
VSS
VSS
79/94
ST52T400/T440/E440/T441
11.9 Port Pin Characteristics
11.9.1 General Characteristics.
Subject to general operating condition for V , f
and T unless otherwise specified.
DD osc,
A ,
1)
Symbol
Parameter
Condition
Min
Max
1.5
Unit
Typ
CMOS type low level input voltage.
Port B pins. (See Fig 11.13)
V
IL
TTL type Schmitt trigger low level
input voltage. Port A and Port C
pins. (See Fig. 11.12)
0.8
CMOS type high level input voltage.
Port B pins. (See Fig 11.13)
3.3
2.2
V
V
IH
TTL type Schmitt trigger high level
input voltage. Port A and Port C
pins. (See Fig. 11.12)
2)
V
1
Schmitt trigger voltage hysteresis
hys
I
I
V
≤V ≤V
DD
Input leakage current
±1
L
SS
IN
µA
3)
Floating input mode
200
Static current consumption
S
Notes:
1. Unless otherwise specified, typical data is based on T =25 °C and V =5 V
A
DD
2. Hysteresis voltage between Schmitt trigger switching level. Based on characterization results, not
tested in production.
80/94
ST52T400/T440/E440/T441
Subject to general operating conditions for VDD, fosc, and TA, unless otherwise specified.
Table 11.11 Output Voltage Levels
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
V
0.4
+
Output low level voltage for standard I/O
pin when 8 pins are sunk at same time.
V
V
=5V, I =+8mA
SS
1)
DD
IO
V
OL
V
Output high level voltage for standard I/
O pin when 8 pins are sourced at same
time.
V
0.5
-
=5V, I =- 8mA
DD
2)
DD
IO
V
OH
Notes:
1. The I current sunk must always respects the absolute maximum rating specified in Section 11.2 and the sum of I
IO
IO
(I/O ports and control pins) must not exceed I
VSS
2. The I sourced current must always respect the absolute maximum rating specified in Section 11.2 and the sum of I
IO
IO
(I/O ports and control pins) must not exceed I
VDD.
Figure 11.10 TTL-Level input Schmitt Trigger
Figure 11.11 Port B pins CMOS-level input
5
4
5
4
V =5V
DD
V(V)
o
V = 5V
DD
TA = 25°C
(TYPICAL)
V (V)
o
3
2
1
TA = 25°C
(TYPICAL)
3
2
1
0.5 0.8 1.0
1.5
V(V)
2.0 2.5
0
2.0
3.3
5.0
0
i
V (V)
i
81/94
ST52T400/T440/E440/T441
Subject to general operating condition for VDD, fosc, and TA, unless otherwise specified.
Table 11.12 Output Driving Current
Symbol
RS
Parameter
Input protection resistor
Pin Capacitance
Test Conditions
All input Pins
All input Pins
All input Pins
Min
Typ
1
Max
Unit
kΩ
CS
5
pF
Rpu
Pull-up resistor (*)
22
kΩ
(*) ST52T400 and ST52X440 only
Figure 11.12 Port A and Port C pin Equivalent Circuit (ST52T400 and ST52X440)
DD
V
DD
V
Device
RPU
Input/Output
S
R
VIN
S
C
VOUT
V
SS
V
SS
Figure 11.13 Port B Pin Equivalent Circuit (ST52T400 and ST52X440)
VDD
VDD
Device
RPU
Input/Output
R
S
VIN
S
C
VOUT
VSS
VSS
When the triac-driver is configured in burst-mode or phase partialization the pull-up in main1 and main2
pins are disabled.
When the Port B pin is configured as analog input the pull-up is disabled.
82/94
ST52T400/T440/E440/T441
Figure 11.14 Port A and Port C pin Equivalent Circuit (ST52T441)
VDD
Device
Input/Output
S
R
V
IN
S
C
OUT
V
SS
V
SS
V
Figure 11.15 Port B Pin Equivalent Circuit (ST52T441)
VDD
Device
Input/Output
S
R
V
IN
S
C
OUT
V
SS
V
SS
V
83/94
ST52T400/T440/E440/T441
11.11 Control Pin Characteristics
11.11.1 RESET pin.
Subject to general operating conditions for VDD, fosc, and TA, unless otherwise specified
Table 11.13 Reset pin
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
3)
2.2
2.8
1)
V
V
V
V
= 5 V
= 5 V
= 5 V
Input low level voltage
IL
DD
DD
DD
3)
3)
1)
V
V
Input high level voltage
IH
0.6
2)
V
Schmitt trigger voltage hysteresis
Duration of filtered noise
Reset pulse duration
hys
t
100
FN
nS
t
500
RST
11.11.2 Power on reset.
Table 11.14 Power on reset
Symbol
Parameter
Power on reset
Conditions
Min
2.25
Typ
2.30
Max
2.38
Unit
POR
V
11.11.3 V pin.
PP
Subject to general operating conditions for V
f
, and T ,unless otherwise specified.
DD, osc A
4)
Table 11.15 V
Symbol
pin
PP
Parameter
Input low level voltage
Conditions
Min
Typ
Max
Unit
3)
V
V
0.2
IL
SS
V
3)
V
V
-0.1
12.6
Input high level voltage
IH
DD
Notes:
1. Data is based on characterization results, not tested in production.
2. Hysteresis voltage between Schmitt trigger switching level.
Based on characterization results not tested in production.
3. Data is based on design simulation and/or technology characteristics, not tested in production.
4. In working mode V must be tied to V
PP
SS
84/94
ST52T400/T440/E440/T441
11.12 Analog Comparator Characteristics
Operating conditions: VDD = 5 V, fosc = 0,TA = 90°C unless otherwise specified
Table 11.16 Analog Comparator Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Res
Resolution
A/D Converter mode
8
bit
PBx in analogic input
I =10uA Cs=10nF
2.52
2.62
V
V
G
fosc = 4 MHz
PBx in analogic input
V
I =10uA Cs=10nF
Band Gap voltage
BG
G
fosc = 10 MHz
PBx in analogic input
I =10uA Cs=10nF
fosc = 20 MHz
2.67
2.4
V
G
Input differential voltage
range [-100, +100] mV
V
Input offset voltage
1.8
10
mV
OFF
I
I
I
10 µA (*)
20 µA (*)
40 µA (*)
8.2
9.7
10.5
21.6
43.3
µA
µA
µA
G =
G =
G =
Capacitor charging current
I
16.7
33.3
19.4
38.0
CS
(measured I
)
G
(*) fosc = 1,5,10, 20 MHz , V = 5 V, VPBO = 2 V, Resolution = 8 bit, C = 22nF, TA = 25°C.
DD
S
11.13 Triac Driver Characteristics
Operating conditions: VDD = 5 V, fosc = 0,TA = 90°C
Table 11.17 Triac Driver Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
V
+ 0.7
SS
Output low level voltage when
V
V
= 5 V, I = +50 mA
OL
DD IO
I
= 50 mA
IO
V
Output high level voltage
when I = 50 mA
V
0.9
-
DD
V
V
= 5 V, I = -50 mA
DD IO
OH
IO
Notes:
1. The I current sunk must always respects the absolute maximum rating specified in Section 11.2 and the sum of I
IO
IO
(I/O ports and control pins) must not exceed I
VSS
2. The I sourced current must always respect the absolute maximum rating specified in Section 11.2 and the sum of I
IO
IO
(I/O ports and control pins) must not exceed I
VDD.
85/94
ST52T400/T440/E440/T441
Table 11.18 S020 PACKAGE MECHANICAL DATA
mm
inch.
TYP.
DIM
MIN
2.35
0.1
TYP.
MAX
2.65
0.3
MIN
MAX
0.104
0.012
0.020
0.013
0.512
0.299
A
A1
B
C
D
E
e
0.093
0.004
0.013
0.009
0.496
0.291
0.33
0.23
12.6
7.4
0.51
0.32
13
7.6
1.27
0.050
H
h
10
0.25
0.4
10.65
0.75
1.27
0.394
0.010
0.016
0.419
0.030
0.050
L
K
0° (min.) 8° (max.)
86/94
ST52T400/T440/E440/T441
Table 11.19 SOP28 PACKAGE MECHANICAL DATA
mm
inch.
DIM
MIN
1.55
0.10
0.20
0.18
9.80
5.79
TYP.
MAX
1.75
0.25
0.30
0.25
9.98
6.20
MIN
TYP.
MAX
0.069
0.010
0.012
0.010
0.393
0.244
A
a1
b
0.061
0.004
0.008
0.007
0.386
0.228
b1
D
F
e
0.64
0.025
E
3.80
0.40
8°
3.98
0.90
0.15
0.016
8°
0.157
0.035
L
S
87/94
ST52T400/T440/E440/T441
Table 11.20 PDIP28 PACKAGE MECHANICAL DATA
mm
inch.
TYP.
DIM
MIN
TYP.
MAX
MIN
MAX
A
A1
A2
B
5.08
0.200
0.38
3.56
0.38
0.015
0.140
0.015
4.06
0.51
0.160
0.020
B1
C
1.52
0.060
0.20
0.30
0.008
1.450
0.012
1.470
D
36.83
37.34
D2
E
33.02
15.24
1.300
0.600
E1
e1
eA
eB
L
13.59
13.84
0.535
0.545
2.54
0.100
0.590
14.99
15.24
3.18
1.78
0°
17.78
3.43
2.08
10°
0.600
0.125
0.070
0°
0.700
0.135
0.082
10°
S
α
N
28
28
88/94
ST52T400/T440/E440/T441
Table 11.21 DIP20 PACKAGE MECHANICAL DATA
mm
inch.
DIM
MIN
0.508
1.39
TYP.
MAX
MIN
TYP.
MAX
a1
B
b
0.020
0.055
1.65
0.065
0.45
0.25
0.018
0.010
b1
D
E
e
25.4
1.000
8.5
2.54
22.86
0.335
0.100
0.900
e3
F
7.1
0.279
0.155
I
3.93
L
3.3
0.130
Z
1.34
0.053
89/94
ST52T400/T440/E440/T441
Table 11.22 CDIP28W PACKAGE MECHANICAL DATA
mm
inch.
TYP.
DIM
MIN
TYP.
MAX
5.72
1.40
4.57
4.50
0.56
MIN
MAX
0.225
0.055
0.180
0.177
0.022
A
A1
A2
A3
B
0.51
3.91
3.89
0.41
0.020
0.154
0.153
0.016
B1
C
1.45
0.057
0.23
0.30
0.009
1.437
0.012
1.470
D
36.50
37.34
D2
E
33.02
15.24
1.300
0.600
E1
e
13.06
13.36
0.514
0.526
2.54
0.100
0.590
eA
eB
L
14.99
16.18
3.18
1.52
18.03
4.10
2.49
0.637
0.125
0.060
0.710
0.161
0.098
S
8.89
28
0.350
28
α
4°
11°
4°
11°
N
90/94
ST52T400/T440/E440/T441
Table 11.23 CDIP20W PACKAGE MECHANICAL DATA
mm
inch.
DIM
MIN
TYP.
MAX
MIN
TYP.
MAX
A
A1
B
3.63
0.143
0.38
3.56
1.14
0.20
24.89
0.015
0.140
0.045
0.008
0.980
0.46
12.70
0.25
25.40
22.86
7.49
2.54
6.60
9.73
1.14
3.30
12.70
4.22
0.56
1.78
0.018
0.500
0.010
1.000
0.900
0.295
0.100
0.260
0.383
0.045
0.130
0.500
0.166
0.022
0.070
0.014
1.020
B1
C
0.36
D
25.91
D1
E1
e
6.99
8.00
0.275
0.315
G
6.35
9.47
6.86
9.98
0.250
0.373
0.270
0.393
G1
G2
L
2.92
3.81
0.115
0.150
S
Ν
20
91/94
ST52T400/T440/E440/T441
ORDERING INFORMATION
Each device is available for production in user
ging and prototyping which features the maximum
memory size and peripherals of the family. Care
must be taken to only use resources available on
the target device.In order to obtain a list of part
numbers see ST52T400/T440/E440/T441 Sales
Type List at the beginning of the datasheet.
programmable version (OTP) as well as in factory
programmed version (FASTROM). OTP devices
are shipped to customers with a default blank con-
tent FFh, while FASTROM factory programmed
parts contain the code sent by the customer.
There is one common EPROM version for debug-
Figure 11.16 Device Type Codes
ST52 t nnn c m p y
TEMPERATURE RANGE:
= -40 to 85 °C
6
PACKAGES:
B
M
= PDIP
= PSO
MEMORY SIZE:
0
1
2
3
= 1 Kb
= 2 Kb
= 4 Kb
= 8 Kb
PIN COUNT:
F
G
= 20 pin
= 28 pin
SUBFAMILY:
400
440
MEMORY TYPE:
T
E
= OTP
= EPROM
FAMILY
92/94
ST52T400/T440/E440/T441
93/94
Full Product Information at http://www.st.com/five
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to
change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
© 2002 STMicroelectronics – Printed in Italy – All Rights Reserved
STMicroelectronics GROUP OF COMPANIES
Australia - Brazil - China - Canada - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta
- Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A.
http://www.st.com
94/94
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