ST52F500F0B6 [STMICROELECTRONICS]
8-BIT, FLASH, 24MHz, MICROCONTROLLER, PDIP20, PLASTIC, DIP-20;
| 型号： | ST52F500F0B6 |
| 厂家： | 
ST |
| 描述： | 8-BIT, FLASH, 24MHz, MICROCONTROLLER, PDIP20, PLASTIC, DIP-20 光电二极管 |
| 文件： | 总94页 (文件大小：578K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ST52F500/F503/F504
ST52F500/F503/F504
8-BIT INTELLIGENT CONTROLLER UNIT (ICU)
2
Two Timer/PWMs, I C, SPI
TARGET SPECIFICATION
Memories
■ Up to 8 Kbytes Single Voltage Flash Memory
■ Up to 512 bytes of RAM
■ Up to 4 Kbytes Data EEPROM
■ In Situ Programming in Flash devices (ISP)
■ Single byte and Page modes and In Application
Programming for writing data in Flash memory
■ Readout protection and flexible write protection
Core
■ Register File based architecture
■ 107 basic instructions
■ Hardware multiplication and division
■ Decision Processor for the implementation of
Fuzzy Logic algorithms
■ Deep System and User Stacks
Clock and Power Supply
■ Up to 24 MHz clock frequency
■ Programmable Oscillator modes:
Peripherals
■ 2 Programmable 16 bit Timer/PWMs with
internal 16-bit Prescaler featuring:
– 10 MHz Internal Oscillator
– External Clock/ Oscillator
– External RC Oscillator
■ Power-On Reset (POR)
– PWM output
– Input capture
■ Programmable Low Voltage Detector (PLVD)
– Output compare
– Pulse generator mode
■ Watchdog timer
with 3 configurable thresholds
■ Power Saving features
2
■ I C Peripheral with master and slave mode
Interrupts
■ 3-wire SPI Peripheral supporting Single
■ 8 interrupt vectors with one SW Trap
■ Non-Maskable Interrupt (NMI)
Master and Multi Master SPI modes
■ Two Port Interrupts with up to 16 sources
Development tools
■ High level Software tools
■ ‘C’ Compiler
I/O Ports
■ From 10 up to 22 I/O PINs configurable in pull-
up, push-pull, weak pull-up, open-drain and
high-impedance
■ Emulator
■ Low cost Programmer
■ Gang Programmer
■ High current sink/source in all pins
Rev 1.12 - September 2002
1/94
This is preliminary information on a new product foreseen to be developed. Details are subject to change without notice.
ST52F500/F503/F504
2/94
ST52F500/F503/F504
TABLE OF
CONTENTS
TABLE OF CONTENTS
1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
1.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
1.2.1 Memory Programming Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.2.2 Working Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.3 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
2 INTERNAL ARCHITECTURE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.1 Control Unit and Data Processing Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
2.1.1 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.1.2 Flags. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2 Arithmetic Logic Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
2.3 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
3 ADDRESSING SPACES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1 Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
3.2 Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
3.3 Program/Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
3.4 System and User Stacks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
3.5 Input Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
3.6 Output registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
3.7 Configuration Registers & Option Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
4 MEMORY PROGRAMMING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.1 Program/Data Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
4.2 Memory Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
4.2.1 Programming Mode start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.2.2 Fast Programming procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.2.3 Random data writing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.2.4 Option Bytes Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.3 Memory Verify. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
4.3.1 Fast read procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.3.2 Random data reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.4 Memory Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
4.5 ID Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
4.6 Error cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
4.7 In-Situ Programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
4.8 In-Application Programming (IAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
4.8.1 Single byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.8.2 Block write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.8.3 Memory Corruption Prevention. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.8.4 Option Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.8.5 Input Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
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5 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.1 Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
5.2 Global Interrupt Request Enabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
5.3 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
5.4 Interrupt Maskability and Priority Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
5.5 Interrupt RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
5.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
6 CLOCK, RESET & POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . 41
6.1 Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
6.2 Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
6.2.1 External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.2.2 Reset Procedures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.3 Programmable Low Voltage Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
6.4 Power Saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
6.4.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
6.4.2 Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
6.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
6.5.1 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6.5.2 Option Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
7 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
7.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
7.2 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
7.3 Output Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
7.4 Interrupt Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
7.5 Alternate Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
7.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
7.6.1 Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
7.6.2 Input Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
7.6.3 Output Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
8 FUZZY COMPUTATION (DP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
8.1 Fuzzy Inference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
8.2 Fuzzyfication Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
8.3 Inference Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
8.4 Defuzzyfication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
8.5 Input Membership Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
8.6 Output Singleton . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
8.7 Fuzzy Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
9 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
9.1 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
9.2 Instruction Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
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10 WATCHDOG TIMER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
10.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
10.2 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
11 PWM/TIMERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
11.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
11.2 Timer Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
11.3 PWM Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
11.3.1 Simultaneous Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
11.4 Timer Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
11.5 PWM/Timer 0 Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
11.5.1 PWM/Timer 0 Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
11.5.2 PWM/Timer 0 Input Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
11.5.3 PWM/Timer 0 Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
11.6 PWM/Timer 1 Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
11.6.1 PWM/Timer 1 Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
11.6.2 PWM/Timer 1 Input Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
11.6.3 PWM/Timer 1 Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
12 I2C BUS INTERFACE (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
12.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
12.2 Main Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
12.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
12.3.1 Mode Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
12.3.2 Communication Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
12.3.3 SDA/SCL Line Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
12.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
12.4.1 Slave Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
12.4.2 Master Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
12.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
12.5.1 I2C Interface Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
12.5.2 I2C Interface Input Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
12.5.3 I2C Interface Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
13 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . 83
13.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
13.2 Main Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
13.3 General description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
13.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
13.4.1 Master Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
13.4.2 Slave Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
13.4.3 Data Transfer Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
13.4.4 Write Collision Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
13.4.5 Master Mode Fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
13.4.6 Overrun Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
5/94
ST52F500/F503/F504
13.4.7 Single Master and Multimaster Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
13.4.8 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
13.5 SPI Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
13.5.1 SPI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
13.5.2 SPI Input Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
13.5.3 SPI Output Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
6/94
ST52F500/F503/F504
1 GENERAL DESCRIPTION
1.1 Introduction
ST52F500/F503/F504 are devices of ST FIVE
family of 8-bit Intelligent Controller Units (ICU),
which can perform, both boolean and Fuzzy
algorithms in an efficient manner, in order to reach
the best performances that the two methodologies
allow.
An internal programmable WATCHDOG is
available to avoid loop errors and reset the ICU.
ST52F500/F503/F504 supply different peripherals
to implement the most common serial
2
communication protocols. I C and SPI peripherals
allow the implementation of synchronous serial
2
protocols. I C peripherals can work both in master
and slave mode. SPI implements Single and Multi
Master modes using 3-wire.
Produced by STMicroelectronics using the reliable
high performance CMOS process for Single
Voltage Flash versions, ST52F500/F503/F504
include integrated on-chip peripherals that allow
maximization of system reliability, and decreased
system costs in order to minimize the number of
external components.
The flexible I/O configuration of ST52F500/F503/
F504 allow one to interface with a wide range of
external devices (for example D/A converters or
power control devices), and to communicate with
the most common serial standards.
ST52F500/F503/F504 pins are configurable. The
user can set input or output signals on each single
pin in 8 different modes, reducing the need for
external components in order to supply a suitable
interface with the port pins.
Up to 8 interrupt vectors are available, which allow
synchronization with peripherals and external
devices. Non-Maskable Interrupt and S/W TRAP
are available. All interrupts have configurable
priority levels and are maskable excluding the
Non-Maskable Interrupt, which has fixed top level
priority. Two versatile Port Interrupts are available
for synchronization with external sources.
The ST52F500/F503/F504 also include an on-chip
Power-on-Reset (POR), which provides an internal
chip reset during power up situation and a
Programmable Low Voltage Detector (PLVD),
which causes the ICU to reset if the voltage source
V
dips below a threshold. Three programmable
DD
thresholds are available, allowing to work with
different supply voltages (from 2.4 to 5.5 V).
In order to optimize energy consumption, two
different power saving modes are available: Wait
mode and Halt mode.
Internal Oscillator at 10 MHz ± 1% is available.
External clock, quartz oscillator or RC oscillator are
also applicable. The device always starts with the
Internal Oscillator, then it reads an Option Byte
where the clock mode to be used is programmed.
A hardware multiplier and divider, together with a
wide instruction set, allow the implementation of
complex functions by using a single instruction.
Therefore, program memory utilization and
computational speed is optimized.
Fuzzy Logic dedicated structures in ST52F500/
F503/F504 ICU’s can be exploited to model
complex system with high accuracy in a useful and
simple manner.
Fuzzy Expert Systems for overall system
management and Fuzzy Real time Controls can be
designed to increase performance at competitive
costs.
The linguistic approach characterizing Fuzzy Logic
is based on a set of IF-THEN rules, which describe
the control behavior and on Membership Functions
associated with input and output variables.
Program Memory addressing capability addresses
up to 8 Kbytes of memory location to store both
program instructions and data.
Memory can be locked by the user in order to
prevent external undesired operations.
Operations may be performed on data stored in
RAM, allowing direct combination of new inputs
and feedback data. All RAM bytes are used like
Register File.
An additional RAM bench is added to the Program
Memory addressing space in order to allow the
management of the System/User Stacks and user
data storage.
Up to 340 Membership Functions, with triangular
and trapezoidal shapes, or singleton values are
available to describe fuzzy variables.
The Timer/PWM peripheral allows one to manage
power devices and timing signals, by implementing
different operating modes and high frequency
PWM (Pulse Width Modulation) controls. Input
Capture and Output Compare functions are
available on the Timers.
ST52F500/F503/F504 supply the system stack
and the user stack located in the additional RAM
bench. The user stack can be located anywhere in
the additional RAM by writing the top address in
the configuration registers, in order to avoid
overlap with other data.
The Timer has a 16-bit programmable internal
Prescaler and a 16-bit Counter, which can use
internal or external START/STOP signals and
clock.
Single Voltage Flash allows the user to reprogram
the devices on-board by means of the In Situ
Programming (ISP) feature. It is possible to store in
safe way up to 4K of data in the available EEPROM
7/94
ST52F500/F503/F504
memory benches. Permanent data, both in Flash
and EEPROM can be managed by means of the
In-Application-Programming (IAP) feature. Single
byte and Page write modes aresupported. Flexible
write protection, of permanent data or program
instructions, is also available.
Data and commands are transmitted by using the
2
2
I C protocol, implemented using the internal I C
peripheral. The In-Situ Programming protocol
(ISP) uses the following pins:
■ SDA and SCL for transmission
■ Vpp for entering in the mode
The Instruction Set composed of up to 107
instructions allows code compression and high
speed in the program implementation.
■ RESET for starting the protocol in a stable status
■ Vdd and Vss for the power supply.
The Internal clock is used in this phase.
A powerful development environment consisting of
a board and software tools allows an easy
configuration and use of ST52F500/F503/F504.
1.2.2 Working Mode.
The Visual FIVE software tool allows the
development and debugging of projects via a user-
friendly graphical interface and optimization of
generated microcode.
Third-party Hardware Emulators and ‘C’ Compiler
are available to speed-up the application
implementation and time-to-market.
The processor starts the working phase following
the instructions, which have been previously
loaded in the first locations of the memory. The first
instruction must be a jump to the first program
instruction, skipping the data (interrupt vectors,
Membership Functions, user data) stored in the
first memory page.
ST52F500/F503/F504’s internal structure includes
two computational blocks, the CONTROL UNIT
(CU) and the DATA PROCESSING UNIT (DPU),
which performs boolean functions. The DECISION
PROCESSOR (DP) block cooperates with these
blocks to perform Fuzzy algorithms.
1.2 Functional Description
ST52F500/F503/F504 ICU’s can work in two
modes according to the Vpp signal levels:
■ Memory Programming Mode
The DP can manage up to 340 different
Membership Functions for the antecedent part of
fuzzy rules. The consequent terms of the rules are
“crisp” values (real numbers). The maximum
number of rules that can be defined is limited by
the dimensions of the standard algorithm
implemented.
■ Working Mode
During Working Mode Vpp must be tied to Vss. To
enter the Memory Programming Mode, the Vpp pin
must be tied to Vdd.
A RESET signal must be applied to the device to
switch from one mode to the other.
The Program/Data Memory is shared between
Fuzzy and standard algorithms. Within this
memory, the user data can be stored both in non
volatile memory as well as in the RAM locations.
1.2.1 Memory Programming Mode.
The ST52F500/F503/F504 memory is loaded in
the Memory Programming Mode. All instructions
and data are written inside the memory during this
phase.
The Control Unit (CU) reads information and the
status of the peripherals.
Arithmetic calculus can be performed on these
values by using the internal CU and Register File,
which supports all computations. The peripheral
inputs can be Fuzzy and/or arithmetic output
values contained in the Register File or Program/
Data Memory.
The Option Bytes are loaded during this phase by
using the programming tools. The Option Bytes
can only be loaded in this phase and cannot be
modified run-time.
8/94
ST52F500/F503/F504
Table 1.1 ST52F500/F503/F504 Devices Summary
Device
NVM
RAM
EEPROM
Timers
ADC
Comms
I/O
Package
1/2/4/8 K
FLASH
I2C
ST52F500Ympy
256/512
-
2X16-bit
-
10
Dip/So 16
1/2/4/8 K
FLASH
I2C SPI
I2C SPI
ST52F50 0Fmpy
ST52F500Gmpy
ST52F503Ympy
ST52F50 3Fmpy
ST52F503Gmpy
ST52F504Ympy
ST52F50 4Fmpy
ST52F504Gmpy
256/512
256/512
256/512
256/512
256/512
512
-
2X16-bit
2X16-bit
2X16-bit
2X16-bit
2X16-bit
2X16-bit
2X16-bit
2X16-bit
-
-
-
-
-
-
-
-
14
22
10
14
22
10
14
22
Dip/So 20
Dip/So 28
Dip/So 16
Dip/So 20
Dip/So 28
Dip/So 16
Dip/So 20
Dip/So 28
1/2/4/8 K
FLASH
-
1/2/4/8 K
FLASH
I2C
128/256
128/256
128/256
1/2/4/8 K
FLASH
I2C SPI
I2C SPI
I2C
1/2/4/8 K
FLASH
512/1024/
2048/4096
4K FLASH
4K FLASH
4K FLASH
512/1024/
2048/4096
I2C SPI
I2C SPI
512
512/1024/
2048/4096
512
Note: devices with1-2K Flash have 256 RAM / 128 EEPROM
COMMON FEATURES
Watchdog
ST52F500/F503/F504
Yes
Other Features
NMI, PLVD, POR
From -40° to +85°
2.4 - 5.5 V
Temperature Range
Operating Supply
CPU Frequency
from 1 to 24 MHz.
Legend:
Sales code:
ST52tnnncmpy
F=FLASH, T=OTP, E=EPROM
500, 503, 504, 510, 513, 514, 520, 521, 530
Memory type (t):
Subfamily (nnn):
Pin Count (c):
Y=16 pins, F=20 pins, G=28 pins, K=32/34 pins, J=42/44 pins
0=1 Kb, 1=2 Kb, 2=4 Kb, 3=8 Kb Flash (ST52x500 & ST52x503)
0=512, 1=1024, 2=2048, 3=4096 bytes EEPROM (ST52x504)
Memory Size (m):
Packages (p):
B=PDIP, D=CDIP, M=PSO, T=TQFP
Temperature (y):
0=+25, 1=0 +70, 3=-40 +125, 5=-10 +85, 6=-40 +85, 7=-40 +105
9/94
ST52F500/F503/F504
Figure 1.1 ST52F500/F503/F504 Block Diagram
MEMORY
FLASH
ISP/IAP
I2C
DATA RAM
256 bytes
PA7:0
PORT A
DATA
EEPROM
TIMER/PWM 0
TIMER/PWM 1
MEMORY
INTERFACE
CORE
ALU &
DPU
PB7:0
PC5:0
PORT B
SPI
DECISION
PROCESSOR
CONTROL
UNIT
Register File
256 bytes
Input
registers
PORT C
WATCHDOG
PC
FLAGS
POWER SUPPLY
POWER ON
RESET
OSCILLATOR
& PLVD
VDD VPP
VSS
OSCIN OSCOUT
RESET
10/94
ST52F500/F503/F504
Figure 1.2 ST52F500/F503/F504 SO28/DIP28 Pin Configuration
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
28
Vdd
Vdd
Vss
Vss
2
2
27
26
25
24
23
22
21
20
19
18
17
16
15
OscOut
RESET
OscOut
RESET
SO28
PDIP28
3
3
OscIn
Vpp
PA0/SCL
PA1/SDA
PA2/T1OUT
PA3/TRES
PA4/TSTRT
PA5/TCLK
PA6/T0OUT
PA7/INT
PC5
OscIn
Vpp
PA0/SCL
PA1/SDA
PA2/T1OUT
PA3/TRES
PA4/TSTRT
PA5/TCLK
PA6/T0OUT
PA7/INT
PC5
4
4
5
5
PB0/SCK
PB1/MOSI
PB2/MISO
PB3/SS
PB4
PB0/SCK
PB1/MOSI
PB2/MISO
PB3/SS
PB4
6
6
7
7
8
8
9
9
10
11
12
13
14
10
11
12
13
14
PB5
PB5
PB6
PB6
PC4
PC4
PB7
PB7
PC3
PC3
PC0
PC0
PC2
PC2
PC1
PC1
Figure 1.3 ST52F500/F503/F504 SO20/DIP20 Pin Configuration
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
1
20
19
18
17
16
15
14
13
12
11
Vdd
Vdd
Vss
Vss
2
OscOut
OscOut
RESET
RESET
SO20
PDIP20
3
OscIn
Vpp
PA0/SCL
OscIn
Vpp
PA0/SCL
PA1/SDA
PA2/T1OUT
PA3/TRES
PA4/TSTRT
PA5/TCLK
PA6/T0OUT
PA7/INT
4
PA1/SDA
5
PB0/SCK
PB1/MOSI
PB2/MISO
PB3/SS
PB4
PA2/T1OUT
PA3/TRES
PA4/TSTRT
PA5/TCLK
PA6/T0OUT
PA7/INT
PB0/SCK
PB1/MOSI
PB2/MISO
PB3/SS
PB4
6
7
8
9
10
PB5
PB5
11/94
ST52F500/F503/F504
Figure 1.4 ST52F500/F503/F504 SO16/DIP16 Pin Configuration
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Vdd
Vdd
Vss
Vss
OscOut
OscOut
RESET
RESET
SO16
PDIP16
OscIn
Vpp
PA0/SCL
OscIn
Vpp
PA0/SCL
PA1/SDA
PA2/T1OUT
PA3/TRES
PA4/TSTRT
PA5/TCLK
PA1/SDA
PB0
PA2/T1OUT
PA3/TRES
PA4/TSTRT
PA5/TCLK
PB0
PB1
PB1
PA7/INT
PA6/T0OUT
PA7/INT
PA6/T0OUT
12/94
ST52F500/F503/F504
Table 1.2 ST52F500/F503/F504 Pin List
SO28
SO20
SO16
NAME
Programming Phase
Working Phase
DIP28 DIP20 DIP16
1
2
3
4
1
2
3
4
1
2
3
4
Vdd
OSCOUT
OSCIN
Vpp
Digital Power Supply
Digital Power Supply
Oscillator Output
Oscillator Input
Programming Mode Selector
Programming Mode Selector
5
6
7
8
5
6
7
8
5
6
-
PB0/SCK
PB1/MOSI
PB2/MISO
PB3/SS
Digital I/O, SPI Serial Clock
Digital I/O, SPI Master out Slave in
Digital I/O, SPI Master in Slave out
Digital I/O, SPI Slave Select
-
9
9
10
-
-
-
-
-
-
-
-
-
-
PB4
PB5
PB6
PB7
PC0
PC1
PC2
PC3
PC4
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
10
11
12
13
14
15
16
17
-
-
-
-
-
-
18
19
20
21
22
23
24
25
26
27
28
-
-
PC5
Digital I/O
11
12
13
14
15
16
17
18
19
20
7
PA7/INT
Digital I/O, Non Maskable Interrupt
Digital I/O, Timer/PWM 0 output
Digital I/O, Timer/PWM 0 clock
Digital I/O, Timer/PWM 0 start/stop
Digital I/O, Timer/PWM 0 Reset
Digital I/O, Timer/PWM 1 output
8
PA6/T0OUT
PA5/TCLK
PA4/TSTRT
PA3/TRES
PA2/T1OUT
PA1/SDA
PA0/SCL
RESET
9
10
11
12
13
14
15
16
2
Serial Data I/O
Serial Clock
Digital I/O, I C Serial Data I/O
2
Digital I/O, I C Serial Clock
General Reset
Digital Ground
General Reset
Digital Ground
Vss
13/94
ST52F500/F503/F504
1.3 Pin Description
ST52F500/F503/F504 pins can be set in digital
input mode, digital output mode, interrupt mode or
in Alternate Functions. Pin configuration is
achieved by means of the configuration registers.
The functions of the ST52F500/F503/F504 pins
are described below:
PA0-PA7, PB0-PB7,PC0-PC5. These lines are
organized as I/O ports. Each pin can be configured
as an input, output (with pull-up, push-pull, weak-
pull-up, open-drain, high-impedance), or as an
interrupt source.
T0OUT, T1OUT. These pins output the signals
generated by the PWM/Timer 0 and PWM/Timer 1
peripheral.
V
V
V
Main Power Supply Voltage.
DD.
TRES, TSTRT, TCLK . These pins are related to
the PWM/Timer 0 peripheral and are used for Input
Capture and event counting. The TRES pin is used
to set/reset the Timer; the TSTRT pin is used to
start/stop the counter. The Timer can be driven by
the internal clock or by an external signal
connected to the TCLK pin.
. Digital circuit Ground.
SS
. Programming/Working mode selector. During
the Programming phase V must be set to V
PP
.
PP
DD
In Working phase V must be equal to V
.
PP
SS
OSCin and OSCout. These pins are internally
connected to the on-chip oscillator circuit. A quartz
crystal or a ceramic resonator can be connected
between these two pins in order to allow correct
use of ST52F500/F503/F504 with various stability/
cost trade-offs. An external clock signal can be
applied to OSCin: in this case OSCout must be
grounded. To reduce costs, an RC circuit can be
applied to the OSCin pin to establish the internal
clock frequency, instead of the quartz. Without any
connection, the device can work with its internal
clock generator (10 MHz)
INT. This pin is used as input for the Non-Maskable
(top level) interrupt. The interrupt signal is detected
only if the pin is configured in Alternate Function.
SCL, SDA. These pin are used respectively as
2
Serial Clock and Serial Data I/O in I C peripheral
protocol. They are used also in Programming
Mode to receive and transmit data.
SCK, MISO, MOSI, SS. These pins are used by
the Serial Peripheral Interface (SPI) peripheral.
SCK is the serial clock line. MISO (Master In Slave
Out) and MOSI (Master Out Slave In) are the serial
data lines, which work in input or in output
depending on if the device is working in slave or
master mode. The SS pin allows the selection of
the device master/slave mode.
RESET. This signal is used to reset the ST52F500/
F503/F504 and re-initialize the registers and
control signals. It is also used when switching from
the Programming Mode to Working Mode and vice
versa.
14/94
ST52F500/F503/F504
2 INTERNAL ARCHITECTURE
2.1 Control Unit and Data Processing Unit
The Control Unit (CU) decodes the instructions
stored in the Program Memory and generates the
appropriate control signals. The main parts of the
CU are illustrated in Figure 2.1.
ST52F500/F503/F504’s architecture is Register
File based and is composed of the following blocks
and peripherals:
■ Control Unit (CU)
■ Data Processing Unit (DPU)
■ Decision Processor (DP)
■ ALU
The five different parts of the CU manage Loading,
Logic/Arithmetic, Jump, Control and the Fuzzy
instruction set.
The block called “Collector” manages the signals
deriving from the different parts of the CU. The
collector defines the signals for the Data
Processing Unit (DPU) and Decision Processor
(DP), as well as for the different peripherals of the
ICU.
■ Memory Interface
■ up to 256 bytes Register File
■ Program/Data Memory
■ Data EEPROM
The block called “Arbiter” manages the different
parts of the CU, so that only one part of the system
is activated during working mode.
■ Interrupts Controller
■ Clock Oscillator
The CU structure is extremely flexible and was
designed with the purpose of easily adapting the
core of the microcontroller to market needs. New
instruction sets or new peripherals can easily be
included without changing the structure of the
microcontroller, maintaining code compatibility.
A set of 107 different instructions is available. Each
instruction requires a number of clock pulses to be
performed that depends on the complexity of the
instruction itself. The clock pulses to execute the
instructions are driven directly by the masterclock,
which has the same frequency of the oscillator
signal supplied.
■ PLVD and POR
■ Digital I/O ports
■ Timer/PWMs
2
■ I C
■ SPI
Figure 2.1 CU Block Diagram
MicroCode
Loading
Instruction Set
C
O
L
Logic Arithmetic
Instruction Set
A
R
B
L
I
T
E
Jump
Instruction Set
E
C
T
Control
Signals
R
O
R
Control
Instruction Set
Decision Processor
Clock Master
Instruction Set
15/94
ST52F500/F503/F504
Figure 2.2 Data Processing Unit (DPU)
Interrupts Unit
PROGRAM COUNTER
Memory Address
Control Unit
Program Memory
Input Registers
Peripherals
Peripherals
REGISTER
FILE
DECISION
PROCESSOR
REGISTERS
REGISTER FILE
ADDRESS
256 Bytes
ACCUMULATOR
FLAGS REG.
ALU
The DPU receives, stores and sends the
instructions deriving from the Program/Data
Memory, Register File or from the peripherals. It is
controlled by the CU on the basis of the decoded
instruction. The Fuzzy registers store the partial
results of the fuzzy computation. The accumulator
register is used by the ALU and is not accessible
directly: the instructions used by the ALU can
address all the Register File locations as
operands, allowing a more compact code and a
faster execution.
The PC can be changed in the following ways:
■ JP (Jump)
■ Interrupt
■ RETI
PC = Jump Address
PC = Interrupt Vector
PC = Pop (stack)
■ RET
PC = Pop (stack)
■ CALL
PC = Subroutines address
PC = Reset Vector
■ Reset
■ Normal Instruction PC = PC + 1
The following addressing modes are available:
inherent, immediate, direct, indirect, bit direct.
2.1.2 Flags.
The ST FIVE core includes different sets of flags
that correspond to 2 different modes: normal mode
and interrupt mode. Each set of flags consist of a
CARRY flag (C), ZERO flag (Z) and SIGN flag (S).
Each set is stacked: one set of flags is used during
normal operation and other sets are used during
each level of interrupt. Formally, the user has to
manage only one set of flags: C, Z and S since the
flag stack operation is performed automatically.
2.1.1 Program Counter.
The Program Counter (PC) is a 16-bit register that
contains the address of the next memory location
to be processed by the core. This memory location
may be both an instruction or data address.
The Program Counter’s 16-bit length allows the
direct addressing of a maximum of 64 Kbytes in the
Program/Data Memory space.
16/94
ST52F500/F503/F504
Each interrupt level has its own set of flags, which
is saved in the Flag Stack during interrupt
servicing. These flags are restored from the Flag
Stack automatically when a RETI instruction is
executed.
2.2 Arithmetic Logic Unit
The 8-bit Arithmetic Logic Unit (ALU) performs
arithmetic calculations and logic instructions such
as: sum, subtraction, bitwise AND, OR, XOR, bit
set and reset, bit test and branch, right/left shift and
rotate (see the Chapter 9 Instruction Set for further
details).
In addition, the ALU of ST52F500/F503/F504 can
perform multiplication (MULT) and division (DIV).
Multiplication is performed by using 8 bit operands
storing the result in 2 registers (16 bit values); the
division instruction addresses the MSB of the
dividend (the LSB is stored in the next address):
the result and remainder are stored in these source
addresses (see Figure 2.3 and Figure 2.4).
If the ICU was in normal mode before an interrupt,
after the RETI instruction is executed, the normal
flags are restored.
Note: A subroutine CALL is a normal mode
execution. For this reason a RET instruction,
consequent to a CALL instruction, doesn’t affect
the normal mode set of flags.
Flags are not cleared during context switching and
remain in the state they were in at the exit of the
last interrupt routine switching.
In order to manage signed type values, the ALU
also performs addition and subtraction with offset
The Carry flag is set when an overflow occurs
during arithmetic operations, otherwise it is
cleared.The Sign flag is set when an underflow
occurs during arithmetic operations, otherwise it is
cleared.
(ADDO
and SUBO). These instructions
respectively subtract and add 128 to the overall
result, in order to manage values logically in the
range between -128,127.
The flags, related to the current context, can be
checked by reading the FLAGS Input Register 38
(026h).
Figure 2.4 Division
Figure 2.3 Multiplication
RAM
RAM
000h
001h
002h
000h
001h
002h
i-1
i
i
i+1
j-1
j
j-1
j
j+1
j+1
0FDh
0FEh
0FFh
0FDh
0FEh
0FFh
X
REG. j
LSB
REG. i
MSB
:
REG. j
REG. j+1
REG. i
16 Bit
REMAINDER
QUOTIENT
17/94
ST52F500/F503/F504
2.3 Register Description
Flags Register (FLAG)
Input Register 38 (026h) Read Only
Reset Value: 0000 0000 (00h)
7
0
C
-
-
-
-
-
Z
S
Bit 7-3: Not Used
Bit 2: Z Zero flag
Bit 1: S Sign flag
Bit 0: C Carry flag
18/94
ST52F500/F503/F504
3 ADDRESSING SPACES
3.2 Register File
The Register File consists of up to 256 general
purpose 8-bit RAM locations called “registers” in
order to recall the functionality.
The Register File exchanges data with all the other
addressing spaces and is used by the ALU to
perform all the arithmetic and logic instructions.
These instructions have any Register File address
as operands.
ST52F500/F503/F504
addressing spaces:
has
six
separate
■ Register File
■ Program/Data Memory
■ Stacks
■ Input Registers
■ Output Registers
■ Configuration Registers
Data can be moved from one location to another by
using the LDRR instruction; see further ahead for
information on the instruction used to move data
between the Register File and the other
addressing spaces.
Each space is addressed by a load type instruction
that indicates the source and the destination space
in the mnemonic code (see Figure 3.1).
3.3 Program/Data Memory
3.1 Memory Interface
The Program/Data Memory consists of both non-
volatile memory (Flash, EEPROM) and RAM
memory benches.
Non-volatile memory (NVM) is mainly used to store
the user program and can also be used to store
permanent data (constant, look-up tables).
Each RAM bench consists of 128/256 locations
used to store run-time user data. At least one
bench is present in the devices. RAM benches are
also used to implement both System and User
Stacks.
The read/write operation in the space addresses
are managed by the Memory Interface, which can
recognize the type of memory addressed and set
the appropriate access time and mode.
In addition, the Memory Interface manages the In
Application Programming (IAP) functions in Flash
devices like writing cycle and memory write
protection.
Figure 3.1 Addressing Spaces
STFive CORE
PROGRAM/DATA MEMORY
ON CHIP PERIPHERALS
REGISTER FILE
DECISION
PROCESSOR
REGISTERS
OUTPUT
REGISTERS
NON VOLATILE MEMORY
LDFR
LDER
LDPR
LDCNF
GETPG
PERIPHERAL
BLOCK
LDRE
PGSETR
PROGRAM
COUNTER
PERIPHERAL
CONFIGURATION
BLOCK
RAM BANKS
AND STACKS
REGISTERS
INPUT REGISTERS
LDCR
LDRI
CU
DPU
ALU
PERIPHERAL
BLOCK
LDCE
LDPE
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ST52F500/F503/F504
NVM is always located beginning after the first
locations of the addressing space. RAM banks are
always located after NVM.
NVM is organized in accordance to the following
blocks (see Figure 3.2):
■ Mbfs Setting block (just after the interrupt
vectors) contains the coordinates of the vertexes
of every Mbf defined in the program. The last
address that can be assigned to this block is
1023. This area is dynamically assigned
according to the size of the fuzzy routines. The
memory area that remains unused, if any, is
assigned to the Program Instructions block.
■ Reset Vector block (from address 0 to 2)
contains an absolute jump instruction to the first
user program instruction. The Assembler tool
automatically fills these locations with correct
data.
■ The Program Instructions block (just after the
last Mbf data through the last NVM address)
contains the instruction of the user program and
the permanent data.
■ Interrupt Vectors block (from location 3 up to
32) contains the interrupt vectors. Each address
is composed of three bytes (the jump opcode
and the 16 bit address). Interrupt vectors are set
by using IRQ pseudo-instruction (see the
Programming Manual).
■ Option bytes block (from location 3000h to
307Fh) is the addressing space reserved for the
option bytes. In ST52F500/F503/F504, only the
location from 3000h to 3007h are used.
Figure 3.2 Program/Data Memory Organization
FFFFh
~
~
307Fh
SPACE NOT
ADDRESSABLE
OPTION BYTES
3000h
~
~
20FFh
SYSTEM STACK
RAM
BENCH
DATA
USER STACK
2000h
PROGRAM INSTRUCTIONS
AND PERMANENT DATA
NON
VOLATILE
MEMORY
0400h
PROGRAM INSTRUCTIONS
AND PERMANENT DATA
MEMBERSHIP FUNCTIONS
PARAMETERS
0021h
0003h
0000h
INTERRUPT VECTORS
RESET VECTOR
20/94
ST52F500/F503/F504
Flash and EEPROM are programmed electrically
just applying the supply voltage (2.4 V to 5.5 V) and
it is also erased electrically; this feature allows the
user to easily reprogram the memory without
taking the device off from the board (In Situ
Programming ISP). Data and commands are
transmitted through the I C serial communication
protocol. Data can also be written run-time with the
In Application Programming (IAP)
3.4 System and User Stacks
The System and User Stacks are located in the
Program/Data memory in the RAM benches.
System Stacks are used to push the Program
Counter (PC) after an Interrupt Request or a
Subroutine Call. After a RET (Return from a
subroutine) or a RETI (Return from an interrupt)
the PC that is saved is popped from the stack and
restored. After an interrupt request, the flags are
also saved in a reserved stack inside the core, so
each interrupt has its own flags.
The System Stack is located in the last RAM bench
starting from the last address (255) inside the
bench page. The System Stack Pointer (SSP) can
be read and modified by the user. For each level of
stack 2 bytes of the RAM are used. The SSP points
to the first currently available stack position. When
a subroutine call or interrupt request occurs, the
content of the PC is stored in a couple of locations
pointed to by the SSP that is decreased by 2.
2
NVM can be locked by the user during the
programming phase, in order to prevent external
operation such as reading the program code and
assuring protection of user intellectual property.
Flash and EEPROM pages can be protected by
unintentional writings.
The operations that can be performed on the NVM
during the Programming Phase, ISP and IAP are
described in detail in the Section 4.
Figure 3.3 System and User Stack
RAM BENCH
PROGRAM COUNTER
20FFh
SYSTEM STACK
RETI
LOCATION ADRESS
PAGE NUMBER
LSB
20FEh
LEVEL 1
MSB
SYSTEM STACK
LEVEL 2
SYSTEM STACK
IRQ
POINTER
SYSTEM STACK
LEVEL 3
REGISTER FILE
SYSTEM STACK
LEVEL 4
POP X
REGISTER X
USER DATA
CONFIGURATION REGISTERS
USER STACK LEVEL 4
USER STACK LEVEL 3
USER STACK LEVEL 2
USER STACK
POINTER
PUSH X
USER STACK TOP LSB
USER STACK TOP MSB
USER STACK LEVEL 1
2001h
2000h
21/94
ST52F500/F503/F504
When a return occurs (RET or RETI instruction),
the SSP is increased by 2 and the data stored in
the pointed locations couple is restored back into
the PC.
The current SSP can be read and write in the
couple of Configuration Registers 44 02Ch (MSB:
page number, always 32 020h) and 45 02Dh (LSB:
location address) (see Figure 3.3). In ST52F500/
F503/F504 the user can only consider the LSB
because the MSB is always the same.
further details on this instruction. The Input
Registers are read-only registers.
In order to simplify the concept, a mnemonic name
is assigned to each register. The same name is
used in Visual FIVE development tools. The list of
the Input Registers is shown in Table 3.1.
3.6 Output registers
The ST52F500/F503/F504 Output Registers
bench consists of a file of 8-bit registers containing
data sent to the Peripherals and the I/O Ports (for
example: Timer Counters, data to be transmitted
by the serial communication peripherals, data to be
sent to the Port pins in output, etc.).
The registers are located inside the Peripherals
and Ports, which allow flexibility and modularity in
the design of new family devices.
The User Stack is used to store user data and is
located beginning from a RAM bench location set
by the user (USTP) by writing the couple of
Configuration Registers 5 005h (MSB: page
number) and 6 005h (LSB: location address) (see
Figure 3.3). Register 5, which is the page number,
must always be set to a value between 32 (020h)
and 255 (0FFh): values higher than 32 always
address RAM on page 32.
This feature allows a flexible use of the User Stack
in terms of dimension and to avoid overlaps. The
User Stack Pointer (USP) points to the first
currently available stack location. When the user
stores a byte value contained in the Register File
by using the PUSH instruction, the value is stored
in the position pointed to by the USP that is
increased (the User Stack order is opposite to the
System Stack one). When the user takes a value
from the User Stack with the POP instruction, the
USP is decreased and the value pointed to is
copied in the specified Register File location.
The Output Registers are write only. In order to
access the configuration Register the user can use
the following instructions:
■ LDPI: loads the immediate value in the specified
Output Register.
■ LDPR: loads the contents of the specified
Register File location into the output register
specified. This instruction allows computed data
to be sent to Peripherals and Ports.
■ LDPE direct: loads the contents of the specified
Program/Data Memory location into the output
register specified. This instruction allows data to
be sent to Peripherals and Ports from a table.
By writing the USTP, the new address is
automatically written in the USP. The current USP
can be read from the Input Registers 11 0Bh
(MSB: page number, always 32 020h) and 12 0Ch
(LSB: location address) (see Figure 3.3). In
ST52F500/F503/F504 the user can only consider
the LSB because the MSB is always the same.
■ LDPE indirect: loads the contents of the
Program/Data Memory location whose address
is contained in the specified Register File
location into the output register specified. This
instruction allows data to be sent to Peripherals
and Ports from a table pointed to by a register.
Note: The user must pay close attention to avoid
overlapping user and Stacks data. The User Stack
Top location and the System Stack Pointer should
be configured with care in order to have enough
space between the two stacks.
See the Programming manual for further details
about these instructions.
In order to simplify the concept, a mnemonic name
is assigned to each register. The same name is
used in Visual FIVE development tools. The list of
the Output Registers is shown in Table 3.2.
3.5 Input Registers
The ST52F500/F503/F504 Input Registers bench
consists of a file of 8-bit registers containing data
or the status of the peripherals. For example, the
Input Registers contain data converted by the
ADC, Ports, serial communication peripherals,
Timers, etc.
3.7 Configuration Registers & Option Bytes
The
ST52F500/F503/F504
Configuration
Registers bench consists of a file of 8-bit registers
that allows the configuration of all the ICU blocks.
The registers are located inside the block they
configure in order to obtain greater flexibility and
modularity in the design of new family devices. In
the Configuration Registers, each bit has a
The Input Registers can be accessed by using the
LDRI instruction that loads the specified Register
File address with the contents of the specified
Input Register. See the Programming Manual for
22/94
ST52F500/F503/F504
peculiar use, so the logic level of each of them
must be considered.
■ LDCR: loads the Configuration Register
specified with the contents of the specified
Register File location, allowing a parametric
configuration.
Some special configuration data, that needs to be
load at the start-up and not further changed, are
stored in Option Bytes. These are loaded only
during the device programming phase. See Table
3.3 and Section 4 for a detailed description of the
Option Bytes.
The Configuration Registers are readable and
writable; the addresses refer to the same register
both in read and in write. In order to access the
Configuration Register the user can work in
several modes by utilizing the following
instructions:
■ LDCE: loads the Configuration Register
specified with the contents of the specified
Program/Data Memory location, allowing the
configuration data to be taken from a table.
■ LDCNF: loads the
Register File location
specified with the contents of the Configuration
Register indicated, allowing for the inspection of
the configuration of the device (permitting safe
run-time modifications).
■ LDCI: loads the immediate value in the
Configuration Register specified and is the most
commonly used to write configuration data.
In order to simplify the concept, a mnemonic name
is assigned to each register. The same name is
used in Visual FIVE development tools. The list of
the Configuration Registers is shown in Table 3.4.
23/94
ST52F500/F503/F504
Table 3.1 Input Registers
Mnemonic
Description
Port A data Input Register
Address
00h
PORT_A_IN
PORT_B_IN
PORT_C_IN
-
0
1
2
3
4
5
6
Port B data Input Register
Port C data Input Register
Not Used
01h
02h
03h
04h
05h
06h
-
Not Used
SPI_IN
I2C_IN
Serial Peripheral Interface data Input Register
2
I C Interface data Input Register
2
I2C_SR1
7
07h
I C Interface Status Register 1
2
I2C_SR2
8
08h
09h
0Ah
0Bh
0Ch
I C Interface Status Register 2
-
Not Used
9
-
Not Used
10
11
12
USP_H
USP_L
User Stack Pointer (MSB)
User Stack Pointer (LSB)
0Dh-
014h
-
Not Used
13-20
PWM0_COUNT_IN_H
PWM0_COUNT_IN_L
PWM0_STATUS
PWM/Timer 0 Counter Input Register (MSB)
PWM/Timer 0 Counter Input Register (LSB)
PWM/Timer 0 Status Register
21
22
23
24
25
26
27
28
29
30
015h
016h
017h
018h
019h
01Ah
01Bh
01Ch
01Dh
01Eh
PWM0_CAPTURE_H
PWM0_CAPTURE_L
PWM1_COUNT_IN_H
PWM1_COUNT_IN_L
PWM1_STATUS
PWM/Timer 0 Capture Register (MSB)
PWM/Timer 0 Capture Register (LSB)
PWM/Timer 1 Counter Input Register (MSB)
PWM/Timer 1 Counter Input Register (LSB)
PWM/Timer 1 Status Register
PWM1_CAPTURE_H
PWM1_CAPTURE_L
PWM/Timer 1 Capture Register (MSB)
PWM/Timer 1 Capture Register (LSB)
01Fh-
025h
-
Not Used
31-37
FLAGS
-
Flag Register
38
39
40
026h
027h
028h
Not Used
IAP_SR
In Application Programming Status Register
24/94
ST52F500/F503/F504
Table 3.2 Output Registers
Mnemonic
PORT_A_OUT
PORT_B_OUT
PORT_C_OUT
-
Description
Port A data Output Register
Address
0
1
2
3
4
5
6
00h
01h
02h
03h
04h
05h
06h
Port B data Output Register
Port C data Output Register
Not Used
-
Not Used
SPI_OUT
Serial Peripheral Interface data Output Register
2
I2C_OUT
I C Interface data Output Register
PWM0_COUNT_OUT_H
PWM0_COUNT_OUT_L
PWM0_RELOAD_H
PWM/Timer 0 Counter Output Register (MSB)
PWM/Timer 0 Counter Output Register (LSB)
PWM/Timer 0 Reload Register (MSB)
PWM/Timer 0 Reload Register (LSB)
7
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
8
9
PWM0_RELOAD_L
10
11
12
13
14
PWM1_COUNT_OUT_H
PWM1_COUNT_OUT_L
PWM1_RELOAD_H
PWM/Timer 1 Counter Output Register (MSB)
PWM/Timer 1 Counter Output Register (LSB)
PWM/Timer 1 Reload Register (MSB)
PWM/Timer 1 Reload Register (LSB)
PWM1_RELOAD_L
Table 3.3 Option Bytes
Mnemonic
Description
Oscillator Control Register
Clock Parameters
Address
OSC_CR
0
1
2
3
4
5
6
7
00h
01h
02h
03h
04h
05h
06h
07h
CLK_SET
OSC_SET
Oscillator Set-Up
PLDV_CR
Programmable Low Voltage Detector Control Register
HW/SW Watchdog selector
First Page Write Protected
First Page not Write Protected
Wake Up from Halt Time
WDT_EN
PG_LOCK
PG_UNLOCK
WAKEUP
25/94
ST52F500/F503/F504
Table 3.4 Configuration Registers
Mnemonic
Description
Interrupt Mask Register
Interrupts Polarity
Address
00h
INT_MASK
INT_POL
INT_PRL_H
INT_PRL_M
INT_PRL_L
USTP_H
USTP_L
WDT_CR
-
0
1
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
Interrupt Priority Register (higher priority)
Interrupt Priority Register (medium priority)
Interrupt Priority Register (lower priority)
User Stack Top Pointer (MSB)
User Stack Top Pointer (LSB)
Watchdog Configuration Register
not used
2
3
4
5
6
7
8
PWM0_CR1
PWM0_CR2
PWM0_CR3
PWM1_CR1
PWM1_CR2
-
PWM/Timer 0 Configuration Register 1
PWM/Timer 0 Configuration Register 2
PWM/Timer 0 Configuration Register 3
PWM/Timer 1 Configuration Register 1
PWM/Timer 1 Configuration Register 2
Not Used
9
10
11
12
13
14
15
-
Not Used
2
I2C_CR
16
17
18
19
010h
011h
012h
013h
I C Interface Control Register
2
I2C_CCR
I2C_OAR1
I2C_OAR2
I C Interface Clock Control Register
2
I C Interface Own Address Register 1
2
I C Interface Own Address Register 2
SPI_CR
Serial Peripheral Interface Control Register
Serial Peripheral Interface Control-Status Register
Not Used
20
21
22
23
24
25
014h
015h
016h
017h
018h
019h
SPI_STATUS_CR
-
-
Not Used
PORT_A_PULLUP
PORT_A_OR
Port A Pull Up enable/disable Register
Port A Option Register
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ST52F500/F503/F504
Table 3.4 Configuration Registers
Mnemonic
Description
Address
PORT_A_DDR
PORT_A_AF
Port A Data Direction Register
26
27
28
29
30
31
32
33
34
01Ah
01Bh
01Ch
01Dh
01Eh
01Fh
020h
021h
022h
Port A Alternate Function selection Register
Port B Pull Up enable/disable Register
Port B Option Register
PORT_B_PULLUP
PORT_B_OR
PORT_B_DDR
PORT_B_AF
Port B Data Direction Register
Port B Alternate Function selection Register
Port C Pull Up enable/disable Register
Port C Option Register
PORT_C_PULLUP
PORT_C_OR
PORT_C_DDR
Port C Data Direction Register
023h-
02Bh
-
Not Used
35-43
SSP_H
System Stack Pointer (MSB)
System Stack Pointer (LSB)
CPU Clock Prescaler
44
45
46
02Ch
02Dh
02Eh
SSP_L
CPU_CLK
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ST52F500/F503/F504
4 MEMORY PROGRAMMING
Remark: the memory contents are protected by
the Error Correction Code (ECC) algorithm that
uses a 4-bit redundancy to correct one bit errors.
ST52F500/F503/F504 provides an on-chip user
programmable non-volatile memory, which allows
fast and reliable storage of user data.
Program/Data Memory addressing space is
composed by a Single Voltage Flash Memory and
4.1 Program/Data Memory Organization
The Program/Data Memory is organized as
described in Section 3.3. The various sales types
have different amounts of each type of memory.
Table 4.1 describes the memory benches amount
and page allocation for each sales type.
a
RAM memory bench. The ST52F503/504
devices also have a Data EEPROM bench to store
permanent data with long term retention and a high
number of write/erase cycles.
All the Program Data memory addresses can
execute code, including RAM and EEPROM
benches.
Remark: some devices have RAM or EEPROM
memory benches of 128 bytes. The address range
inside the page of these benches is between 128
to 255.
The memory is programmed by setting the V pin
pp
equal to V . Data and commands are transmitted
dd
The addressing spaces are organized in pages of
256 bytes. Each page is composed by blocks of 32
bytes. Memory programming is performed one
block at a time in order to speed-up the
programming time (about 2.5 ms per block).
The whole location address is composed as
follows:
2
through the I C serial communication protocol. The
same procedure is used to perform “In-Situ” the
programming of the device after it is mounted in
the user system. Data can also be written in run-
time with the In-Application Programming (IAP).
The Memory can be locked by the user during the
programming phase, in order to prevent external
operation such as reading the program code and
assuring protection of user intellectual property.
Flash and EEPROM pages can be protected by
unintentional writings.
15
8
7
5
4
0
Page address
Block address address inside the block
Table 4.1 Sales Type Memory Organization
Flash Memory
Device
RAM Memory
Amount
EEPROM Memory
Amount
Pages
Page
32*
32*
32
Amount
Page(s)
ST52F500x0xx
ST52F500x1xx
ST52F500x2xx
ST52F500x3xx
ST52F503x0xx
ST52F503x1xx
ST52F503x2xx
ST52F503x3xx
ST52F504x0xx
ST52F504x1xx
ST52F504x2xx
ST52F504x3xx
1024 bytes
2048 bytes
4096 bytes
8192 bytes
896 bytes
0 to 3
128 bytes
128 bytes
256 bytes
256 bytes
128 bytes
128 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
-
-
-
0 to 7
-
0 to 15
0 to 31
0 to 3
-
-
32
-
-
32*
32*
32
128 bytes
128 bytes
256 bytes
256 bytes
512 bytes
3*
1920 bytes
3840 bytes
7936 bytes
4096 bytes
4096 bytes
4096 bytes
4096 bytes
0 to 7
7*
0 to 14
0 to 30
0 to 15
0 to 15
0 to 15
0 to 15
15
32
31
32
16-17
16-19
16-23
16-31
32
1024 bytes
2048 bytes
4096 bytes
32
32
(*) Addresses range from 128 to 255 inside the page
28/94
ST52F500/F503/F504
4.2 Memory Programming
1.
V
is set to V
PP DD
The Programming procedure writes the user
program and data into the Flash Memory,
EEPROM and Option Bytes. The programming
2. The device is Reset (RESET=V
)
SS
3. The Reset is released (RESET=V
)
DD
procedures are entered by setting the V pin
4. The internal oscillator starts at 10 MHz
pp
equal to V and releasing the Reset signal. The
dd
5. The memory is turned on
following pins are used in Programming mode:
2
6. The I C Interface and Ports are initialized
■ V
■ V
■ V
used to switch to programming mode
PP
DD
SS
2
7. The I C Interface is configured to work as
device supply
Slave, Receiver, 7-bit address and waits for
data
device ground
■ RESET device reset
8. The Start signal is sent to the chip followed by
the Slave Address 1010000 and the direction
bit set to 0 (the addressed slave waits for da-
ta). The device sends the acknowledge
2
■ SCL
■ SDA
I C serial clock
2
I C serial data
During the device programming, the internal clock
is used, so the OSCin and OSCout pins don’t have
to be considered.
9. The Programming Mode code 00000000 is
sent and acknowledged
10. A command code is sent to the device
11. The procedure related to the command is ex-
ecuted
4.2.1 Programming Mode start. The following
sequence starts the Programming Mode:
Table 4.2 Programming Mode Commands
Command
Code
Data in Data out Erase
Description
Write the currently addressed block with the 32 bytes
BlockWrite
00000001
32
-
-
Yes following the command. The Block locations are erased
before being written.
Write the byte addressed by the next data sent in the
currently addressed page.
ByteWrite
BlockErase
ByteErase
00000010
00000011
00000100
2
1
1
Yes
Erase the block addressed by the next data sent and inside
the currently addressed page.
Yes
Erase the byte addressed by the next data sent and inside
the currently addressed page.
Yes
Read the byte addressed by the next data sent and inside
ByteRead
00000101
00001001
1
1
-
the current page. The read data is sent by the device after
the re-send of the Slave Address with the R/W bit changed.
GlobalErase
-
-
-
-
Yes All the memory is erased.
Write the currently addressed block with the 32 bytes
following the command. The Block locations aren’t erased.
FastBlockWrite 00001011
32
1
No
SetPage
00001100
00001101
-
-
The currently addressed page is set with the next data sent.
Read the memory location currently addressed. The read
data is sent by the device after the command is
acknowledged. The current memory absolute address is
post-incremented.
ReadData
-
1
The current block address is incremented modulo
8
IncBlock
00001111
00010011
-
-
-
-
-
(address 0 follows after address 7 and the Page is post-
incremented)
This command is followed by a status data byte. Mostly
used in error condition and to check if the device is locked
ReadStatus
1
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Figure 4.1 Commands and Data Communication Sequences
Programming mode start sequence
S
10100000
A
00000000
A
Command
A
Data1
A
.....
DataN
A
P
Execution of commands for writing data:
Command
A
Data1
A
.....
DataN
A
Command
A
Data1
A
..... DataN
A
P
Execution of commands for reading data:
Command
A
Address
A
P
S
10100001
A
Data read NA P
S=Start, P=Stop, A=Acknowledge, NA=Non-acknowledge
From Slave to Master
From Master to Slave
The generic procedure of commands execution,
with the data communication in both directions is
displayed in Figure 4.1.
5. After the device acknowledges the 32nd byte,
it holds the SCL line until the parallel writing of
the 32 byte is completed (about 2.5 ms)
Remark: the Slave Address 1010000 must be sent
after a Stop (i.e. each time the data direction
changes, to specify the R/W bit). For example: if a
command to send data to the device has been
executed, a command for receiving data must be
followed by the slaveaddress and the R/W bit must
be set to 1. The Programming Mode code doesn’t
need to be specified again .
6. The Block Pointer is incremented by sending
the IncBlock command
7. The procedure is repeated from point 3 until
there is data to be sent to the memory
Note: the Block Pointer assumes values between
0 to 7 (there are 8 blocks in a page). When the
Block Pointer is equal to 7, the IncBlock command
puts this pointer to 0 and increments the Page
Pointer. The Page Pointer, after page writing is
completed, does’t have to be incremented in the
procedure above described.
Warning: After entering the Programming Mode,
the currently pointed address is the Page 48, Block
3, byte 0 (Lock Byte).
The list of the available commands in
Programming Mode is showed in Table 4.2
4.2.3 Random data writing. A single byte can be
written in a specified memory location by using the
following procedure:
1. The Programming Mode is entered with the
sequence described in Section 4.2.1
4.2.2 Fast Programming procedure. The
fastest way to program the device memory is the
use of the FastBlockWrite command. The following
procedure can be used to write the memory with a
new program and new data, starting from the first
memory location:
2. The SetPage command is sent, followed by
the page number where the data should be
written
1. The Programming Mode is entered with the
sequence described above
3. The ByteWrite command is sent followed by
two bytes
2. The memory is erased (all bits are put to 0)
with the GlobalErase command. The device
holds the SCL line low, releasing it after the
command is completed (about 2 ms). This
command also unlocks the device if locked.
4. The first bytes that follows the ByteWrite com-
mand is the address inside the pointed page
where the data must be written.
3. The FastBlockWrite command is sent and the
device acknowledges it
5. The second byte is the data to be written
6. The device held the SCL line low until the data
is not stored in the memory (about 4.5 ms: 2
ms for erasing and 2.5 for writing)
4. The 32 bytes of data to be written in the first
memory Block are sent in a sequence. The
device acknowledges each of them
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ST52F500/F503/F504
A similar procedure can be used to write a single
block:
from Programming Mode or re-sending the Slave
Address again.
1. The SetPage command is sent, followed by
the page number where the data should be
written
The commands ByteErase and BlockErase, used
instead of ByteWrite and BlockWrite, erase (put all
bit to 0) the specified memory location or block.
2. The IncBlock command is sent as many times
as the block number inside the page (for ex-
ample: to address the block 3 the IncBlock
must be sent 3 times)
4.2.4 Option Bytes Programming. The Option
Byte addresses cannot be accessed with a
sequential procedure like the one described in
Section 4.2.2. Actually, the pointers are
automatically incremented up to the last block or
address in page 31. A further increment sets all the
pointers to 0.
3. The WriteBlock command is sent followed by
the 32 data bytes to be written.
4. After the 32th byte is sent, the device holds
the SCL line low until all the data are not
stored in the memory (about 4.5 ms: 2 ms for
erasing and 2.5 for writing: the same time for
a single byte)
The Option Byte addresses (located at page 48,
block 0, addresses 0-7) must be accessed with a
direct addressing procedure as the one described
in Section 4.2.3.
If the Fast Programming procedure is used, it must
be followed by a Random Block Writing procedure
to program the Option Bytes. The other 24 bytes of
the block can be written with dummy values.
The procedures described previously can be
repeated as many time as needed, without exiting
Figure 4.2 Programming Procedures
Fast Programming Procedure
S
10100000
A
00000000
A
GlobalErase
A
FastBlockWrite
A
Data0
A
A
.....
..... Data31
A
IncBlock
A
FastBlockWrite
A
..... Data31
..... ..... Data31
A
P
Random Byte Writing Procedure
..... SetPage
A
Page Address
A
ByteWrite
IncBlock
A
Byte Address
..... IncBlock
A
Data
A
Command .....
Random Block Writing Procedure
..... SetPage
A
Page Address
A
A
A
BlockWrite
A
Data0
A
.....
..... Data31
A
Command .....
Option Byte Writing Procedure
..... SetPage
A
00110000
A
WriteBlock
A
Option Byte 0
A
..... Option Byte 7
A
.....
..... Dummy 0
A
..... Dummy 23
A
P
S=Start, P=Stop, A=Acknowledge, NA=Non-acknowledge
From Slave to Master From Master to Slave
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Figure 4.3 Reading and Erasing Procedures
Fast Reading Procedure
S
10100000
A
00000000
A
ReadData
A
P
S
10100001
A
Data read NA
P
.....
.....
S
10100000
A
ReadData
A
P
S
10100001
A
Data read NA
P
..... Data read NA
P
Random Byte Reading Procedure
..... SetPage
A
Page Address
A
ByteRead
A
Byte Address
A
P
S
10100001
A
.....
..... Data read NA
P
S
10100000
A
Command .....
Byte Erasing Procedure
..... SetPage
A
Page Address
A
A
ByteErase
IncBlock
A
Byte Address
..... IncBlock
A
Command .....
Block Erasing Procedure
..... SetPage
A
Page Address
A
A
BlockErase
A
Command .....
S=Start, P=Stop, A=Acknowledge, NA=Non-acknowledge
From Slave to Master From Master to Slave
4.3 Memory Verify
To verify the memory contents or just to read part
of data stored in memory, the ByteRead and the
ReadData command can be used. The first
instruction needs the specification of the address;
the second one allows the sequential reading of
consecutive memory locations.
5. The Slave Address with the R/W byte set to 1
(10100001) is sent. The device receives the
Slave Address and acknowledges it.
6. The device sends the data to be read in the
serial data line SDA. The current absolute ad-
dress is post-incremented.
2
Since the device is “Slave” for the I C protocol,
after receiving a command for reading, it must be
configured as Slave Transmitter to send the data.
In order to do so, the Slave Address (1010000)
must be sent again with the R/W byte set to 1, as
stated by the communication protocol.
7. The Master device doesn’t send the acknowl-
edge and generates a stop condition.
8. To read the next data, the Master generates a
Start condition followed by the Slave Address
with the R/W byte set to 0 (10100000). The
device receives the Slave Address and ac-
knowledges it.
4.3.1 Fast read procedure. The memory can be
read sequentially by using the following procedure:
1. The Programming mode is entered with the
sequence described in Section 4.2.1
9. The sequence restarts from point 3 until there
is data to be read.
2. The pointers address the memory location 0
Remark: for the same reasons explained in
Section 4.2.4 the Option Bytes cannot be read with
this procedure: they can be read with a direct
addressing procedure as the one explained in the
next section.
3. The ReadData command is sent and the de-
vice acknowledges it.
4. The Master generates a Stop condition fol-
lowed by a Start condition
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4.3.2 Random data reading. To read a specified
memory location, the following procedure should
be used:
1. The Programming mode is entered with the
sequence described in Section 4.2.1
4.4 Memory Lock
The Program/Data Memory space can be locked to
inhibit the reading of contents and protect the
intellectual property.
To lock the device, the user must set all the bit of
the Lock Byte to ‘1’. The Lock Byte is located on
Page 48 (030h), Block 3, byte 0 inside the block i.e.
byte 96 (060h) inside the page.
After writing 255 (0FFh) into the Lock Byte, with the
procedure described in the Section 4.2.3, the
memory is locked and the only command allowed
are the following:
– GlobalErase: this command, writing ‘0’ in all the
memory, also unlock the device.
– ReadData: the only block that can be read is the
Block 3 in Page 48 (030h); this allows the read-
ing of the Lock Byte and the ID Code locations
(see Section 4.5).
– ReadStatus: this command allows the detection
of an error condition in Programming mode op-
eration (see Section 4.6). It can also be used to
check if the device is locked.
2. The SetPage command is sent, followed to
the page number where the data to be read is
located
3. The ByteRead command is sent, followed by
an address inside the page
4. The Master generates a Stop condition fol-
lowed by a Start condition
5. The Slave Address with the R/W byte set to 1
(10100001) is sent. The device receives the
Slave Address and acknowledges it.
6. The device sends the data to be read in the
serial data line SDA.
7. The Master device doesn’t send the acknowl-
edge and generates a stop condition.
8. To send the next command, the Master
should generate a Start condition followed by
the Slave Address with the R/W byte set to 0
(10100000).
Remark: the Lock Byte is checked when entering
the Programming Mode. For this reason after
writing the Lock Byte, all the commands can be
carried out until the Programming mode is exited.
Figure 4.4 Device Lock Procedure
Device Lock Procedure
..... SetPage
A
00110000
A
ByteWrite
A
01100000
A
11111111
A
Command .....
Device Lock and ID Code Writing Procedure
..... SetPage
A
00110000
A
IncBlock
A
IncBlock
A
IncBlock
A
BlockWrite
A
.....
..... 11111111
A
ID Code 1
A
ID Code 2
A
..... ID Code 31
A
Command .....
Device Lock Reading Procedure
..... SetPage
A
00110000
A
ByteRead
A
01100000
A
P
S
10100001
A
.....
..... Lock Byte NA
P
S
10100000
A
Command .....
S=Start, P=Stop, A=Acknowledge, NA=Non-acknowledge
From Slave to Master From Master to Slave
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Figure 4.5 Error Handling Procedure
Wrong command/data case handling:
Wrong Command/Data
A
Command/Data NA ReadStatus
A
P
S
10100001
A
Status Byte NA
P
S=Start, P=Stop, A=Acknowledge, NA=Non-acknowledge
From Slave to Master
From Master to Slave
When the device is locked, if memory reading is
attempted, with the exception of the Lock Byte and
ID Code block, the device returns no data and an
error sequence.
If memory writing is attempted in any memory
location, the device doesn’t carry out the command
and returns an error sequence.
To unlock the device the GlobalErase command
must be executed before any writing or reading
command.
4.6 Error cases
If a wrong command or data is sent to the device,
it generates an error condition by not sending the
acknowledge after the first successive data or
command. Figure 4.5 shows the error sequence.
The error case can be handled by using the
ReadStatus command. This command can be sent
after the error condition is detected; the device
returns a Status Byte containing the error code.
The ReadStatus command sequence is showed in
Figure 4.5. The list of the error codes is illustrated
in Table 4.3.
4.5 ID Code
Remark: after the ReadStatus command
execution or after any error, the Start Sequence
must be carried out before sending a new
command.
Block 3 in Page 48 (030h) can also be read if the
device is locked. The first byte of the block is the
Lock Byte, the other 31 locations are available to
the user for writing data, as for example
identification codes to distinguish the firmware
version loaded in the device.
The ID Code must be written before locking the
device: after the device is locked it can only be
read. The use of the Block writing procedure is the
fastest way: the ID Code is written together the
Lock Byte, which is sent first, then the 31 bytes of
ID Code follow.
The Most Significative Bit of the error codes
indicates (when set to ‘1’) that the memory is
locked. When a command, that is not allowed
when the memory is locked, is sent, the “Not
Allowed” code is sent. If another code is sent with
the MSB to ‘1’ it indicates that the error condition is
not caused by the memory lock, but by the event
related with the code sent.
Note: the ID Code cannot be modified if the device
is locked: it can only be read.
Warning: when the data writing into a non existing
location is attempted, no error condition is
generated. The user must take care in specifying
the correct page address.
Table 4.3 Error codes
Name
Code
Description
Wrong Direction
Stop Missed
x0000001
x0000010
x0000011
x0000100
x0000101
x0000110
x0010000
A transmit direction, not correct in the running sequence, has been set
The Master missed generating a necessary Stop Condition
The Master missed to send necessary data to the device
The data sent by the Master hasn’t been received correctly by the device
The Master sent a wrong command code
Data Missing
Receive Error
Wrong Command
Not Allowed
A command not allowed when the device is locked has been sent
A code different form the Programming mode code (00000000) has been sent
Wrong Mode
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4.7 In-Situ Programming (ISP)
4.8.2 Block write. This procedure allows the
writing of 32 bytes in parallel. These bytes should
belong to the same block.
Before the writing in the Program/Data memory,
data must be buffered in the Register File in the
first 32 locations (0-31, 00h-020h) by using the
normal instructions to load the Register File
locations.
The Program/Data Memory can be programmed
using the ISP mode. This mode allows the device
to be programmed when it is mounted in the user
application board.
This feature can be implemented by adding a
minimum number of components and board
impact.
Then the data writing starts by using the BLKSET
instruction. The destination block is addressed by
specifying the memory page with the PGSET or
PGSETR instruction before to start the writing; the
block inside the page is addressed with the
argument of the BLKSET instruction.
Example:
PGSET 5
BLKSET 4
The programming procedures and pins used are
identical to the ones described before for the
standard Programming Mode. All the features
previously described in this chapter are applicable
in ISP mode.
If RESET, SCL and SDA pins are used in the user
application board for other purposes, it is
recommended to use a serial resistor to avoid a
conflict when the other devices force the signal
level.
The ISP can be applied by using the standard tools
for the device programming. The ST52F500
Starter Kit supplies a cable to perform the ISP. The
user application board should supply a suited
connector type for the cable (see Starter Kit User
Manual).
This instruction sequence writes the contents of
the first 32 bytes of the Register File in the
locations 1408-1439 (0580h-059Fh).
Warning: the user should be careful in specifying
the correct page and block: the addressing of an
not existing block can cause the unwanted writing
of a different block.
As soon as the BLKSET instruction is executed,
the data writing starts and is performed in about
4.5 ms.
This procedure may also be used to write few data,
taking in account that all the 32 byte are written in
the block anyway.
4.8 In-Application Programming (IAP)
The In Application Programming Mode (IAP)
allows the writing of user data in the Flash and
EEPROM memories when the user program is
running.
There are two ways to write data in IAP mode:
single byte write and Block write. Both procedures
take about 4.5 ms to complete the writing: the
Block write allows the writing of 32 byte in parallel.
4.8.3 Memory Corruption Prevention.
The user can protect some pages (or all the
memory) from unintentional writings. The only
constraint is that the protected pages must be
consecutive.
Two Option Bytes allow the specification of the
page to be protected: PG_LOCK (Option Byte 5)
and PG_UNLOCK (Option Byte 6). PG_LOCK is
used to specify the first protected page;
PG_UNLOCK is used to specify the first page not
protected after the protected ones. The pages
between the two addresses are protected.
Remark: during data writing, the execution of the
user program is stopped until the procedure is
completed. Interrupt requests stop the writing
operation and the data may be not stored. The bit
ABRT in the IAP_SR Input register signals that the
data writing hasn’t been completed. To assure
writing completion, the user should globally disable
the interrupts (UDGI instruction) before starting
IAP data writing.
When writing in a protected page is attempted, the
procedure is aborted and the bit PRTCD of
IAP_SR Input register is set.
If the PG_LOCK and PG_UNLOCK have the same
value, no page is protected. By default, the two
Option Bytes are programmed with the value 0, so
the memory is not write protected by default.
In Programming Mode the protection is not
considered and the pages can be written unless
the device is locked.
4.8.1 Single byte write. Writing of a single byte in
the Non-Volatile Program/Data memory is
performed by using the LDER instruction (both
direct and indirect addressing). The memory page
should be indicated before the LDER instruction
with the PGSET or PGSETR instruction. The byte
address inside the page is specified by the LDER
instruction itself.
As soon as the instruction is executed, the data
writing starts and is performed in about 4.5 ms.
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ST52F500/F503/F504
4.8.4 Option Bytes.
4.8.5 Input Register.
First Protected Page (PG_LOCK)
Option Byte 5 (05h)
IAP Status Register (IAP_SR)
Input Register 40 (028h) Read only
Reset Value: 0000 0000 (00h)
Reset Value: 0000 0000 (00h)
7
0
7
0
LCK7
LCK6
LCK5
LCK4
LCK3
LCK2
LCK1
LCK0
-
-
-
-
-
-
PRTCD ABRT
Bit 7-2: Not Used
Bit 1: PRTCD Page Protected
Bit 7-0: LCK7-0 First Page write protected
In this register the address of first page to be
protected in writing is specified. The pages
following this one are protected up to the page
specified by the PG_UNLOCK Option Byte (not
included among the protected ones).
0: The writing has been completed
1: The writing has been aborted because the
page is protected.
Bit 0: ABRT Writing operation aborted
0: The writing has been completed
First Page not Protected (PG_UNLOCK)
Option Byte 6 (06h)
1: The writing has been aborted because an
interrupt or another unspecified cause
occurred.
Reset Value: 0000 0000 (00h)
7
0
The ABRT and PRTCD bits are reset after the next
successful data writing in the Flash of EEPROM
memory.
UNLCK7 UNLCK6 UNLCK5 UNLCK4 UNLCK3 UNLCK2 UNLCK1 UNLCK0
Bit 7-0: UNLCK7-0 First Page not write protected
In this register the address of first page not write
protected after the protected ones is specified. The
pages following this one aren’t protected.
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5 INTERRUPTS
Figure 5.1 Interrupt Flow
The Control Unit (CU) responds to peripheral
events and external events through its interrupt
channels.
When such events occur, if the related interrupt is
not masked and doesn’t have a priority order, the
current program execution can be suspended to
allow the CU to execute a specific response
routine.
NORMAL
PROGRAM
FLOW
INTERRUPT
SERVICE
ROUTINE
INTERRUPT
Each interrupt is associated with an interrupt
vector that contains the memory address of the
related interrupt service routine. Each vector is
located in the Program/Data Memory space at a
fixed address (see Figure 3.2 Program/Data
Memory Organization).
RETI
INSTRUCTION
5.1 Interrupt Processing
If interrupts are pending at the end of an arithmetic
or logic instruction, the interrupt with the highest
priority is acknowledged. When the interrupt is
acknowledged the flags and the current PC are
saved in the stacks and the associated Interrupt
routine is executed. The start address of this
routine (Interrupt Vector) is located in three bytes
of the Program/Data Memory between address 3
and 32 (03h-020h). See Table 5.1 for the list of the
Interrupt Vector addresses.
5.2 Global Interrupt Request Enabling
When an Interrupt occurs, it generates a Global
Interrupt Pending (GIP). After a GIP a Global
Interrupt Request (GIR) will be generated and
Interrupt Service Routine associated with the
interrupt with higher priority will start.
The Interrupt routine is performed as a normal
code. At the end of each instruction, the CU checks
if a higher priority interrupt has sent an interrupt
request. An Interrupt request with a higher priority
stops lower priority Interrupts. The Program
Counter and the flags are stored in their own
stacks.
With the instruction RETI (Return from Interrupt)
the flags and the Program Counter (PC) are
restored from the top of the stacks. These stacks
have already been described in Paragraph 3.4.
An Interrupt request cannot stop fuzzy rule
processing, but only after the end of a fuzzy rule or
at the end of a logic or arithmetic instruction,
unless a Global Interrupt Disable instruction has
been executed before (see below).
In order to avoid possible conflicts between the
interrupt masking set in the main program, or
inside high level language compiler macros, the
GIP is put in AND through the User Global Interrupt
Mask or the Macro Global Interrupt Mask (see
Figure 5.2).
The UEGI/UDGI instruction switches the User
Global Interrupt Mask enabling/disabling the GIR
for the main program.
MEGI/MDGI instructions switch the Macro Global
Interrupt Mask on/off in order to ensure that the
macro will not be interrupted.
Figure 5.2 Global Interrupt Request
Remark: A fuzzy routine can be interrupted only in
the Main program. When a Fuzzy function is
running inside another interrupt routine an interrupt
request can cause side effects in the Control Unit.
For this reason, in order to use a Fuzzy function
inside an interrupt routine, the user MUST include
the Fuzzy function between an UDGI (MDGI)
instruction and an UEGI (MEGI) instruction (see
the following paragraphs), in order to disable the
interrupt request during the execution of the fuzzy
function.
Global Interrupt
Global Interrupt
Pending
Request
User Global
Interrupt Mask
Macro Global
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5.3 Interrupt Sources
5.4 Interrupt Maskability and Priority Levels
ST FIVE manages interrupt signals generated by
the internal peripherals or generated by software
by the TRAP instruction or coming from the Port
pins. There are two kinds of interrupts coming from
the Port pins: the NMI and the Ports Interrupts.
Interrupts can be masked by the corresponding
INT_MASK Configuration Register 0 (00h). An
interrupt is enabled when the mask bit is “1”. Vice
versa, when the bit is “0”, the interrupt is masked
and the eventual requests are kept pending.
NMI (Not Maskable Interrupt) is associated with pin
PA7 when it is configured as Alternate Function.
This interrupt source doesn’t have a configurable
level priority and cannot be masked. The fixed
priority level is lower than the software TRAP and
higher than all the other interrupts. The NMI can be
configured to be active on the rising or the falling
edge.
The Port Interrupts sources are connected with
Port A and Port B pins. The pins belonging to the
same Port are associated with the same interrupt
vector: there is one vector for Port A and one for
Port B. In order to use one port pin as interrupt, it
must be configured as an interrupt source (see I/O
Ports chapter). In this manner, up to 16 Port
Interrupt sources are available. By reading the Port
the sources that belong to the same Port can be
discriminated. The Port Interrupts can be
configured to be active on the rising or the falling
edge.
All the interrupts, with the exception of the NMI and
TRAP that have fixed level priority, have a config-
urable priority level. The configuration of the prior-
ity levels is completed by writing three consecutive
Configuration
Registers:
INT_PRIORITY_H,
INT_PRIORITY_M, INT_PRIORITY_L, addresses
from 2 to 4 (02h-04h). The 24 bits of these registers
are divided into 8 groups of three bits: each group
is associated with a priority level. The three bits of
each group are written with the code number asso-
ciated with the interrupt source. See Table 5.1 to
know the codes.
Remark: The priority levels Configuration
Registers must be programmed with different
values for each 3-bit groups to avoid erroneous
operation. For this reason the Interrupt priority
must be fixed at the beginning of the main
program, because the reset values of the
Configuration Registers correspond to an
undefined configuration (all zeros). During
program execution the interrupt priority can only be
modified within the Main Program: it cannot be
changed within an interrupt service routine.
Warning: changing the NMI or Port Interrupt
polarity an interrupt request is generated.
All the interrupt sources are filtered, in order to
avoid false interrupt requests caused by glitches.
5.5 Interrupt RESET
When an interrupt is masked, all requests are not
acknowledged and remain pending. When the
pending interrupt is enabled it is immediately
serviced. This event may be undesired; in order to
avoid this a RINT instruction may be inserted
followed by the code number that identifies the
interrupt to reset the pending request. See Table
5.1 to know the codes.
The Trap instruction is something between a
interrupt and a call: it generated an interrupt
request at top priority level and the control is
passed to the associated interrupt routine which
vector is located in the fixed addresses 30-32. This
routine cannot be interrupted and it is serviced
even if the interrupts are globally disabled.
Note: Similarly to the CALL instruction, after a
TRAP the flags are not stacked.
Figure 5.3 Example of Interrupt Requests
INT2 INT0 INT4
INT1
INT3
PRIORITY
LEVEL
0
1
2
3
4
5
6
INT0
INT1
INT2
INT2
INT2
INT3
INT4
MAIN PROGRAM
MAIN PROGRAM
38/94
ST52F500/F503/F504
5.6 Register Description
Bit 7-5: Not Used
Interrupt Mask Register (INT_MASK)
Configuration Register 0 (00h) Read/Write
Reset Value: 0000 0000 (00h)
Bit 4-3: See Timer 0 Registers Description
Bit 2: POLPB Port B Interrupt Polarity
0: The Port B interrupt is triggered on the
rising edge of the applied external signal.
1: The Port B interrupt is triggered on the
falling edge of the applied external signal.
7
0
-
MSKPB MSKPA MSKI2C MSKSPI
-
MSKT1 MSKT0
Bit 1: POLPA Port A Interrupt Polarity
Bit 7: MSKPB Interrupt Mask Port B
0: Port B interrupt masked
0: The Port A interrupt is triggered on the
rising edge of the applied external signal.
1: The Port A interrupt is triggered on the
falling edge of the applied external signal.
1: Port B interrupt enabled
Bit 6: MSKPA Interrupt Mask Port A
0: Port A interrupt masked
Bit 0: POLNMI Non Maskable Interrupt Polarity
1: Port A interrupt enabled
0: The NMI is triggered on the rising edge of
the applied external signal.
2
Bit 5: MSKI2C Interrupt Mask I C Interface
1: The NMI is triggered on the falling edge of
the applied external signal.
2
0: I C Interface interrupt masked
2
1: I C Interface interrupt enabled
High Priority Register (INT_PRL_H)
Configuration Register 2 (02h) Read/Write
Reset Value: 0000 0000 (00h)
Bit 4: MSKSPI Interrupt Mask SPI
0: SPI interrupt masked
1: SPI interrupt enabled
7
0
Bit 3: Not used
PRL23 PRL22 PRL21 PRL20 PRL19 PRL18 PRL17 PRL16
Bit 2: MSKT1 Interrupt Mask PWM/Timer 1
0: Pwm/Timer 1 interrupt masked
1: Pwm/Timer 1 interrupt enabled
Medium Priority Register (INT_PRL_M)
Configuration Register 3 (03h) Read/Write
Reset Value: 0000 0000 (00h)
Bit 1: MSKT0 Interrupt Mask Pwm/Timer 0
0: Pwm/Timer 0 interrupt masked
1: Pwm/Timer 0 interrupt enabled
7
0
PRL15 PRL14 PRL13 PRL12 PRL11 PRL10
PRL9
PRL8
Bit 0: Not used
Low Priority Register (INT_PRL_L)
Configuration Register 4 (04h) Read/Write
Reset Value: 0000 0000 (00h)
Interrupt Polarity Register (INT_POL)
Configuration Register 1 (01h) Read/Write
Reset Value: 0000 0000 (00h)
7
0
7
0
PRL7
PRL6
PRL5
PRL4
PRL3
PRL2
PRL1
PRL0
-
-
-
T0RPOL RESPOL STRPOL POLPA POLNMI
39/94
ST52F500/F503/F504
These three register are used to configure the
priority level of each interrupt source. The 24 bits
of these registers (PRL24-PRL0) are divided into 8
groups of three bits: each group is associated with
a priority level (from level 1, the highest, to level 8,
the lowest: level 0 is fixed for the NMI that can be
interrupted only by the TRAP) . The three bits of
each group are written with the code number
associated with the interrupt source (see Table
5.1).
PRL11-PRL9:Interrupt priority level 4
PRL14-PRL12: Interrupt priority level 5
PRL17-PRL15: Interrupt priority level 6
PRL20-PRL18: Interrupt prioritylevel 7
PRL23-PRL21: Interrupt priority level 8 (lowest)
Example: writing the code 110 into PRL8-PRL6
bits the priority level 3 is assigned to the Port A
Interrupt.
PRL2-PRL1: Interrupt priority level 1 (highest)
PRL5-PRL3: Interrupt priority level 2
PRL8-PRL6: Interrupt priority level 3
Warning: the Priority Level configuration registers
must be always configured.
Table 5.1 Interrupt sources paramethers
Interrupt Source
PWM/Timer 0
PWM/Timer 1
SPI
Priority type
Programmable
Programmable
Programmable
Programmable
PRL code
001
RINT code
Maskable
Yes
Vector Addresses
6-8 (06h-08h)
1
2
4
5
010
Yes
9-11 (09h-0Bh)
100
Yes
15-17 (0Fh-011h)
18-20 (012h-014h)
2
101
Yes
I C Interface
Port A
Port B
NMI
Programmable
Programmable
Fixed
110
6
7
8
-
Yes
Yes
No
21-23 (015h-017h)
24-26 (018h-01Ah)
27-29 (01Bh-01Dh)
30-32 (01Eh-020h)
111
-
-
TRAP
Fixed to highest
No
40/94
ST52F500/F503/F504
6 CLOCK, RESET & POWER SAVING MODES
6.1 Clock
The ST52F500/F503/F504 Clock Generator
module generates the internal clock for the internal
Control Unit, ALU and on-chip peripherals. The
Clock is designed to require a minimum of external
components.
be floating. In this case, Option Byte 1 bits must be
written with 0 (000).
The crystal oscillator start-up time is a function of
many variables: crystal parameters (especially
R ), oscillator load capacitance (CL), IC
s
parameters, environment temperature and supply
voltage.
The crystal or ceramic leads and circuit
connections must be as short as possible. Typical
values for CL1, CL2 are 10pF for a 20 MHz crystal.
ST52F500/F503/F504 devices supply the internal
oscillator in four clock modes:
■ External oscillator
■ External clock
The clock signal can also be generated by an
external RC circuit offering additional cost savings.
Figure 6.1 illustrates the possible connections.
Frequency is a function of resistor, capacitance,
supply voltage and operating temperature; some
indicative values when Vdd=5V and T=25°, are
shown in Table 6.1.
■ External RC oscillator
■ Internal clock
The device always starts in internal clock mode,
excluding any external clock source. After the
start-up phase the clock is configured according to
the userdefinition programmed in the Option Bytes
0 (OSC_CR). The internal clock generator can
supply an internal clock signal with a fixed
frequency of 10 MHz ± 1%, without the need for
external components. In order to obtain the
maximum accuracy, the frequency can be
calibrated by configuring the related Option byte 2
(OSC_SET).
The clock signal generates two internal clock
signals: one for the CPU and one for the
peripherals. The CPU clock frequency can be
reduced, in order to decrease current consuption,
by settingthe CPU_CLK Configuration Register 46
(02Eh). The CPU clock can be reduced up to 64
times (see Register Description).
Table 6.1 RC Oscillator indicative frequencies
The external oscillator mode uses a quartz crystal
or a ceramic resonator connected to OSCin and
OSCout as illustrated in Figure 6.1. This figure also
illustrates the connection of an external clock.
The ST52F500/F503/F504 oscillator circuit
generates an internal clock signal with the same
period and phase as the OSCIN input pin. The
maximum frequency allowed is 24 MHz.
When the external oscillator is used, the loop gain
can be adapted to the various frequencies values
by configuring the three bits of the Option Byte 1
CLK_SET (see Register Decription, Table 6.2).
When an external clock is used, it must be
connected to the pin OSCIN while OSCOUT can
f
(KHz)
C (pF)
R(Ω)
9.5K
10K
Variation
6.6%
7.1%
5.3%
3.3%
2.8%
7.5%
8%
osc
5000
4870
3000
1360
724
20 pF
20K
50K
100K
10K
1720
926
20K
100 pF
50K
424
11.2%
15%
100K
248
Figure 6.1 Oscillator Connections
RC CIRCUIT CLOCK
CRYSTAL CLOCK
EXTERNAL CLOCK
ST FIVE
ST FIVE
ST FIVE
OSCin
OSCout
OSCin
OSCout
OSCin
OSCout
R
C
Cl1
10pF
Cl2
10pF
CLOCK
INPUT
Vdd
Vss
41/94
ST52F500/F503/F504
6.2 Reset
After this level has been reached, the internal
oscillator (10 MHZ) is started and a delay period of
4.096 clock cycles is initiated, in order to allow the
oscillator to stabilize and to ensure that recovery
has taken place from the Reset state.
Four Reset sources are available:
■ RESET pin (external source)
■ WATCHDOG (internal source)
■ POWER ON Reset (Internal source)
■ PLVD Reset (Internal source)
If the device has been configured to work with the
internal clock, the user program is started,
otherwise the Option Byte 7 (WAKEUP) is read
and another count is started before running the
user program. The count duration depends on the
contents of the Option Byte 7 (WAKEUP), that
works as a prescaler, according to the follwing
formula:
When a Reset event occurs, the user program
restarts from the beginning.
6.2.1 External Reset. Reset is an input pin. An
internal reset does not affect this pin. A Reset
signal originated by external sources is
recognized immediately. The RESET pin may be
used to ensure Vdd has risen to a point where the
ICU can operate correctly before the user program
is run. Reset must be set to Vdd in working mode.
A Pull up resistor of 100 KΩ guarantees that the
RESET pin is at level “1” when no HALT or Power-
On events occur. If an external resistor is
connected to the RESET pin a minimum value of
10KΩ must be used.
Delay = 4096 × (WAKEUP + 1) × Tclk
This delay has been introduced in order to ensure
that the oscillator has become stable after its
restart.
If the Reset is generated by the PLVD or the
Watchdog, the oscillator is not turned off; for this
reason the CPU is then restarted immediately,
without the delay.
After a RESET procedure is completed, the core
reads the instruction stored in the first 3 bytes of
the Program/Data Memory, which contains a
JUMP instruction to the first instruction of the user
program. The Assembler tool automatically
generates this Jump instruction with the first
instruction address.
6.2.2 Reset Procedures. After the Reset pin is
set to Vdd or following a Power-On Reset event,
the device is not started until the internal supply
voltage has reached the nominal level of 2.5 V
(corresponding roughly to Vdd=2.8 V).
Figure 6.2 Reset Block Diagram
W ATCHDOG RESET
Vdd
WATCHDOG
CLK_MODE
RST_DELAY
INTERNAL RESET
COUNTER x
RESET
4096
Vdd
Vdd
POWER-ON
RESET
PLVD
PLVD RESET
42/94
ST52F500/F503/F504
6.3 Programmable Low Voltage Detector
The ICU can exit Halt mode upon reception of an
NMI, a Port Interrupt or a Reset. The internal
oscillator (10 MHZ) is started and a delay period of
4.096 clock cycles is initiated, in order to allow the
oscillator to stabilize and to ensure that recovery
has taken place from the Reset state.
The on-chip Programmable Low Voltage Detector
(PLVD) circuit prevents the processor from falling
into an unpredictable status if the power supply
drops below a certain level.
When Vdd drops below the detection level, the
PLVD causes an internal processor Reset that
remains active as long as Vdd remains below the
trigger level.
If the device has been configured to work with the
internal clock, the user program is started,
otherwise the Option Byte 7 (WAKEUP) is read
and another count is started before running the
user program. The count duration depends on the
contents of the Option Byte 7 (WAKEUP), that
works as prescaler, according to the follwing
formula:
The PLVD resets the entire device except the
Power-on Detector and the PLVD itself.
The PLVD can be enabled/disabled at reset by
setting the Option Byte 2 (PLVD_CR) bits.
When Vdd increases above the Trigger Level, the
PLVD reset is deactivated and the user program is
started from the beginning.
Delay = 4096 × (WAKEUP + 1) × Tclk
The detection levels are programmable by means
of the Option Byte 2 (PLVD_CR). There are three
levels for the PLVD falling voltages (2.9V, 3.4V,
3.9V) and for rising voltages (3.1V, 3.65V, 4.2V).
The hysteresis for each level are respectively 200
mV, 250 mV and 300 mV.
The PLVD circuit will only detect a drop if Vdd
voltage stays below the safe threshold for at least
5µs before activation/deactivation of the LVD in
order to filter voltage spikes.
This delay has been introduced in ordet to ensure
that the oscillator has become stable after it is
restarted.
After the start up delay, by exiting with the NMI or
a Port interrupt, the CPU restarts operations by
serving the associated interrupt routine.
Warning: if the Port Interrupt is masked, the ICU
exits from the Halt mode and jumps to the lower
priority interrupt routine.
Remark: the PLVD function isn’t active when it is
in HALT mode. In that case the device is reset if the
Vdd voltage stays below the threshold of 2 V.
Figure 6.3 WAIT Flow Chart
WAIT ISTRUCTION
6.4 Power Saving modes
There are two types of Power Saving modes:
WAIT and HALT mode. These conditions may be
entered by using the WAIT or HALT instructions.
OSCILLATOR
ON
PERIPHERALS CLOCK
CPU CLOCK
ON
OFF
ENAB.
INTERRUPTS
6.4.1 Wait Mode. Wait mode places the ICU in a
low power consumption status by stopping the
CPU. All peripherals and the watchdog remain
active. During WAIT mode the Interrupts are
enabled. The ICU remains in Wait mode until an
Interrupt or a RESET occurs, whereupon the
Program Counter jumps to the interrupt service
routine or, if a Reset occurs, to the beginning of the
user program.
YES
NO
RESET
NO
CPU CLOCK
ON
INTERRUPT
PROGRAM COUNTER RESET
6.4.2 Halt Mode. Halt mode is the lowest ICU
power consumption mode, which is entered by
executing the HALT instruction. The internal
oscillator is turned off, causing all internal
processing to be terminated, including the
operations of the on-chip peripherals. Halt mode
cannot be used when the watchdog is enabled. If
the HALT instruction is executed while the
watchdog system is enabled, it will be skipped
without modifying the normal CPU operations.
CPU CLOCK
ON
JUMP TO INT. ROUTINE
NORMAL PROGRAM FLOW
43/94
ST52F500/F503/F504
Figure 6.4 HALT Flow Chart
HALT INSTRUCTION
YES
WATCHDOG
ENABLED
NO
HALT INSTRUCTION
SKIPPED
OSCILLATOR
PERIPHERALS CLOCK
CPU CLOCK
OFF
OFF
OFF
NO
YES
NO
NMI or PORT
INTERRUPT
RESET
YES
OSCILLATOR
PERIPHERALS CLOCK
CPU CLOCK
ON
ON
ON
OSCILLATOR
PERIPHERALS CLOCK
CPU CLOCK
ON
ON
ON
4096 INTERNAL CLOCK
4096 INTERNAL CLOCK
CYCLES DELAY
CYCLES DELAY
INTERNAL
CLOCK ?
INTERNAL
CLOCK ?
YES
YES
NO
NO
4096 X (WAKEUP+1)
CLOCK CYCLES
DELAY
4096 X (WAKEUP+1)
CLOCK CYCLES
DELAY
RESET CPU
AND RESTART
USER PROGRAM
RESTART PROGRAM
SERVICING THE
INTERRUPT ROUTINE (*)
(*) Warning: if the Port Interrupt is masked, the ICU exits from the
Halt mode and jumps to the lower priority interrupt routine.
44/94
ST52F500/F503/F504
6.5 Register Description
Bit 7-2: Not Used
The following section describes the Register which
are used to configure the Clock, Reset and PLVD.
Bit 1-0: CKMOD1-0 Clock Mode
00: Internal Oscillator
6.5.1 Configuration Register.
01: External Clock or quartz
1x: External RC oscillator
CPU Clock Prescaler (CPU_CLK)
Configuration Register 46 (02Eh) Read/Write
Reset Value: 0000 0000 (00h)
External Clock Parameters (CLK_SET)
Option Byte 1 (01h)
7
0
Reset Value: 0000 0000 (00h)
-
-
CPUCK5 CPUCK4 CPUCK3 CPUCK2 CPUCK1 CPUCK0
7
0
-
-
-
-
-
CKPAR2 CKPAR1 CKPAR0
Bit 7-6: Not Used
Bit 7-3: Not Used
Bit 5-0: CPUCK5-0 CPU Clock Prescaler bits
The CPU Clock frequency is divided by a
factor described in the following table
Bit 2-0: CKPAR2-0 Oscillator Gains
These three bits enable/disable the loop
gains when a external clock or quartz are
used for generating the clock. The
following table decribes the possible
configuration options. Table 6.2 illustrates
the reccomended values for the most
common frequencies used, time to start the
oscillations and the settling time to have a
duty cycle of 40%-60% (at steady state it is
50%).
CPUCK5-0
000000
000001
000010
000100
001000
010000
100000
others
CPU Clock
=f
f
CPU OSC
f
=f
/2
CPU OSC
f
=f
/4
/8
CPU OSC
f
=f
CPU OSC
CKPAR2-0
000
Enabled Gain Stages
f
f
f
f
=f
/16
/32
/64
/64
CPU OSC
No Gains (External Clock Mode)
=f
CPU OSC
001
1 gain stage enabled
not allowed
=f
CPU OSC
010
=f
CPU OSC
011
3 gain stage enabled
not allowed
100
101
4 gain stage enabled
not allowed
6.5.2 Option Bytes.
110
Clock Mode (OSC_CR)
Option Byte 0 (00h)
111
6 gain stage enabled
Reset Value: 0000 0000 (00h)
Warning: If an External Clock is used instead of a
quartz or ceramic resonator, it is reccomended that
no gain be enabled (CKPAR2-0=000) in order lo
lower the current consuption.
7
0
-
-
-
-
-
-
CKMOD1CKMOD0
45/94
ST52F500/F503/F504
Table 6.2 Recomended Gains for the most common frequencies
Recommend
Gain Stages
Oscillation
Start Times*
Settling Times for
40%-60% duty-cycle*
Frequency
CKPAR2-0
External Clock
5 MHz
0
1
3
6
000
001
011
111
-
-
100 µs
80 µs
110 µs
85 µs
143 µs
10 MHz
20 MHz
133 µs
(*) Values by design (not characterized)
Bit 7-2: Not Used
Internal Oscillator Calibration (OSC_SET)
Option Byte 2 (02h)
Reset Value: 0000 0000 (00h)
Bit 1-0: PLVD1-0 PLVD detection levels
00: PLVD disabled
01: Lowest detection level
10: Medium detection level
11: Highest detection level
7
0
-
-
OSPAR5 OSPAR4 OSPAR3 OSPAR2 OSPAR1 OSPAR0
Bit 7-6: Not Used
Wake-Up Time Prescaler (WAKEUP)
Option Byte 7 (07h)
Reset Value: 0000 0000 (00h)
Bit 5-0: OSPAR5-0 Internal Oscillator Parameters
These bits are used in order to calibrate the
precision of the internal oscillator working
at 10 MHz. The six bits enable some
current generators with steps of 5 µA
corresponding to interval of frequency of
100KHz.
7
0
WK7
WK6
WK5
WK4
WK3
WK2
WK1
WK0
Bit 7-0: WK7-0 Wake-up prescaler
Warning: the maximum configuration value
allowed is 101000 (40). The value coresponding to
the 10 MHz by design is 010100 (20).
This byte determinates the time delay for
the stabilization of the oscillator after an
External Reset or a POR and after the
wake-up from Halt. The time delay is
computed according to the following
formula:
PLVD Control Register (PLVD_CR)
Option Byte 3 (03h)
Delay = 4096 × (WAKEUP + 1) × Tclk
Reset Value: 0000 0000 (00h)
7
0
Warning: the value 255 for WAKEUP is not
allowed. If the internal clock is used as clock
source the prescaler is not used.
-
-
-
-
-
-
PLVD1 PLVD0
46/94
ST52F500/F503/F504
7 I/O PORTS
7.2 Input Mode
The pins configured as input can be read by
accessing the corresponding Port Input Register
by means of the LDRI instruction. The addresses
for Port A , B and C are respectively 0 (00h), 1
(01h), and 2 (02h).
When executing the LDRI instruction all the signals
connected to the input pins of the Port are read and
the logical value is copied in the specified Register
File location. If some pins are configured in output,
the port buffer contents, which are the last written
logical values in the output pins, are read.
7.1 Introduction
ST52F500/F503/F504 are characterized by
flexible individually programmable multi-functional
I/O lines. The ST52F500/F503/F504 supplies
devices with up to 3 Ports (named from A to C) with
up to 22 I/O lines.
Each pin can be used as a digital I/O or can be
connected with a peripheral (Alternate Function).
The I/O lines belonging to Port A and Port B can
also be used to generate Port Interrupts.
The I/O Port pins can be configured in the following
modes:
7.3 Output Mode
■ Input high impedance (reset state)
■ Input with pull-up
The pins configured as output can be written by
accessing the corresponding Port Output Register
by means of the LDPR, LDPI and LDPE
instructions. The addresses for Port A , B and C
are respectively, 0 (00h), 1 (01h), and 2 (02h).
■ Output with pull-up
■ Output push-pull
When executing the above mentioned instructions,
the Port buffer is written and the Port pin signals
are modified. If some pins are configured as input
or as interrupt, the values are ignored.
■ Output with weak pull-up
■ Output open drain
■ Interrupt with pull-up
■ Interrupt without pull-up
7.4 Interrupt Mode
These eight modes can be selected by
programming three Configuration Registers for
each Port. All the pins that belong to the same Port
can be configured separately by setting the
corresponding bits in the three registers (see
Register Description).
To avoid side effects, the Configuration Registers
register are latched only when the Direction
Register (PORT_x_DDR) is written. For this
reason this register must be always written when
modifying the pin configuration.
The pins configured as Interrupt Mode can
generate a Port Interrupt request. Only Port A and
Port B pins can be configured in this mode.
An Interrupt vector is associated to each Port:
there are two Port Interrupts available but more
pins of the ports can act as source at the same
time.
The Configuration Registers switch the signals
deriving from interrupt pins to an OR gate that
generates the interrupt request signal. The signal
deriving from the pins can be read, allowing the
discrimination of the interrupt sources when more
than one pin can generate the interrupt signal.
All the I/O digital pinsare TTL compatible and have
a Schmitt Trigger. The output buffer can supply
high current sink (up to 8mA).
The interrupt trigger can be configured either in the
rising or falling edge of the external signal.
Figure 7.2 Analog Pin
Figure 7.1 Digital Pin
PU LL UP
ENABLE
D I GIT AL OU T
E N ABL E
DA T A
UT
POR T A, C, D ,E
PIN
PAD
O
DA T A
I N
47/94
ST52F500/F503/F504
7.5 Alternate Functions
The Alternate Function allows the pins to be
connected with the peripheral signals or NMI. Not
all Port pins have an Alternate Function
associated.
A Configuration Register (PORT_x_AF) for each
Port is used to switch from the Digital I/O function
or the Alternate Function.
When an on-chip peripheral is configured to use a
pin, the correct I/O mode of the related pin should
be selected by selecting one of the appropriate
modes. See the Registers description in order to
obtain the right configurations.Some peripherals,
as for example the I C peripheral, directly drive the
pin configuration according to the current function,
overriding the user configuration.
2
Some pins can have two Alternate Functions: one
input function and one output function. To switch
between the two functions, the PORT_x_AF must
be configured in Alternate Function mode and the
PORT_x_DDR Configuration Register must be
switched in Input mode or in Output mode.
NMI is considered an Alternate Function. For this
reason an NMI interrupt request can’t be
generated unless the PA7 pin is configured in
Alternate Function and in one of the Input modes.
7.6 Register Description
In order to configure the Port’s pins, the three
Configuration
Registers
PORT_x_PULLUP,
PORT_x_OR and PORT_x_DDR must be
configured. The combination of these three
registers determine the pin’s configuration,
according to the scheme shown in Table 7.1.
In order to select between the digital functions or
Alternate functions PORT_x_AF register must be
configured. Each bit of the configuration registers
configures the pin of the corresponding position
(example: PORT_A_DDR bit 5 configures the pin
PA5).
Figure 7.3 Port Pin Architecture
Vdd
EN
D
CONF. REG.
CONF. REG.
E
C
O
D
E
R
SEL
PU
CONF. REG.
INT
CONF. REG.
ENABLE
REGISTER
FILE
FF
DIGITAL
PORT PIN
ALTERNATE
FUNCTION
DATA
INTERRUPT
POLARITY
TO INPUT
REGISTER
IRQ
48/94
ST52F500/F503/F504
7.6.1 Configuration Registers.
Bit 7: AFA7 Alternate Function PA7
0: Digital I/O
1: INT
Port A Pull-Up Register (PORT_A_PULLUP)
Configuration Register 24 (018h) Read/Write
Reset Value: 0000 0000 (00h)
Bit 6: AFA6 Alternate Function PA6
0: Digital I/O
7
0
1: T0OUT
PUA7
PUA6
PUA5
PUA4
PUA3
PUA2
PUA1
PUA0
Bit 5: AFA5 Alternate Function PA5
0: Digital I/O
Bit 7-0: PUA7-0 Port A pull-up (see Table 7.1)
0: Port A pin without pull-up
1: TCLK
1: Port A pin with pull-up
Bit 4: AFA4 Alternate Function PA4
0: Digital I/O
1: TSTRT
Port A Option Register (PORT_A_OR)
Configuration Register 25 (019h) Read/Write
Reset Value: 0000 0000 (00h)
Bit 3: AFA3 Alternate Function PA3
0: Digital I/O
1: TRES
7
0
Bit 2: AFA2 Alternate Function PA2
0: Digital I/O
ORA7
ORA6
ORA5
ORA4
ORA3
ORA2
ORA1
ORA0
1: T1OUT
Bit 7-0: ORA7-0 Port A option (see Table 7.1)
Bit 1: AFA1 Alternate Function PA1
0: Digital I/O
1: SDA
Port A Data Direction Register (PORT_A_DDR)
Configuration Register 26 (01Ah) Read/Write
Reset Value: 0000 0000 (00h)
Bit 0: AFA0 Alternate Function PA0
0: Digital I/O
1: SCL
7
0
DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0
Table 7.1 Pin mode configuration
MODE
PU
0
OR
0
DDR
Bit 7-0: DDRA7-0 Port A direction (see Table 7.1)
0: Port A pin configured as input
Input high impedance
Input with pull-up
0
0
0
0
1
1
1
1
1: Port A pin configured as output
1
0
Interrupt without pull-up
Interrupt with pull-up
Output push-pull
0
1
Port A Alternate Fuction (PORT_A_AF)
Configuration Register 27 (01Bh) Read/Write
Reset Value: 0000 0000 (00h)
1
1
0
0
7
0
Output with pull-up
Output open drain
Output weak pull-up
1
0
AFA7
AFA6
AFA5
AFA4
AFA3
AFA2
AFA1
AFA0
0
1
1
1
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ST52F500/F503/F504
Port B Pull-Up Register (PORT_B_PULLUP)
Configuration Register 28 (01Ch) Read/Write
Reset Value: 0000 0000 (00h)
Bit 7-4: Not Used
Bit 3: AFB3 Alternate Function PB3
0: Digital I/O
1: SS
7
0
PUB7* PUB6* PUB5** PUB4** PUB3** PUB2** PUB1
PUB0
Bit 2: AFB2 Alternate Function PB2
(*) Not used in 20 pin package devices
(**) Not used in 16 pin package devices
0: Digital I/O
1: SDI
Bit 7-0: PUB7-0 Port B pull-up (see Table 7.1)
0: Port B pin without pull-up
Bit 1: AFB1 Alternate Function PB1
1: Port B pin with pull-up
0: Digital I/O
1: SDO
Port B Option Register (PORT_B_OR)
Configuration Register 29 (01Dh) Read/Write
Reset Value: 0000 0000 (00h)
Bit 0: AFB0 Alternate Function PB0
0: Digital I/O
1: SCK
7
0
ORB7* ORB6* ORB5** ORB4** ORB3** ORB2** ORB1
ORB0
Port C Pull-Up Register (PORT_C_PULLUP)
Configuration Register 32 (020h) Read/Write
Reset Value: 0000 0000 (00h)
(*) Not used in 20 pin package devices
(**) Not used in 16 pin package devices
Bit 7-0: ORB7-0 Port B option (see Table 7.1)
7
0
-
-
PUC5
PUC4
PUC3
PUC2
PUC1
PUC0
Port B Data Direction Register (PORT_B_DDR)
Configuration Register 30 (01Eh) Read/Write
Reset Value: 0000 0000 (00h)
Note: This register is not used in 16/20 pin devices
Bit 7-6: Not Used
7
0
Bit 5-0: PUC5-0 Port C pull-up (see Table 7.1)
0: Port C pin without pull-up
DDRB7* DDRB6* DDRB5** DDRB4** DDRB3** DDRB2** DDRB1 DDRB0
(*) Not used in 20 pin package devices
(**) Not used in 16 pin package devices
1: Port C pin with pull-up
Bit 7-0: DDRB7-0 Port B direction (see Table 7.1)
0: Port B pin configured as input
Port C Option Register (PORT_C_OR)
Configuration Register 33 (021h) Read/Write
Reset Value: 0000 0000 (00h)
1: Port B pin configured as output
7
0
Port B Alternate Fuction (PORT_B_AF)
Configuration Register 31 (01Fh) Read/Write
Reset Value: 0000 0000 (00h)
-
-
ORC5
ORC4
ORC3
ORC2
ORC1
ORC0
7
0
Note: This register is not used in 16/20 pin devices
Bit 7-6: Not Used
-
-
-
-
AFB3
AFB2
AFB1
AFB0
Note: This register is not used in 16 pin devices
Bit 5-0: ORC5-0 Port C option (see Table 7.1)
50/94
ST52F500/F503/F504
Port C Data Direction Register (PORT_C_DDR)
Configuration Register 34 (022h) Read/Write
Reset Value: 0000 0000 (00h)
The logical level applied in the Port B pins,
configured as digital input, can be achieved by
reading this register.
7
0
Port C Data Input Register (PORT_C_IN)
Input Register 2 (02h) Read only
Reset Value: XXXX XXXX
-
-
DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0
7
0
Note: This register is not used in 16/20 pin devices
-
-
PCI5
PCI4
PCI3
PCI2
PCI1
PCI0
Bit 7-6: Not Used
Note: This register is not used in 16/20 pin devices
Bit 7-6: Not Used
Bit 5-0: DDRC5-0 Port C direction (see Table 7.1)
0: Port C pin configured as input
1: Port C pin configured as output
Note: in order to achieve low current consuption,
the port pins must be configured as input pull-up,
even though they are not existing in the package.
For example in 20 pin devices, the pins PB6-7 and
PC0-7 must be configured in input pull-up.
Bit 5-0: PCI5-0 Port C Input data
The logical level applied in the Port C pins,
configured as digital input, can be achieved by
reading this register.
7.6.2 Input Registers.
7.6.3 Output Registers.
Port A Data Input Register (PORT_A_IN)
Input Register 0 (00h) Read only
Reset Value: XXXX XXXX
Port A Data Output Register (PORT_A_OUT)
Output Register 0 (00h) Write only
Reset Value: 0000 0000 (00h)
7
0
7
0
PAI7
PAI6
PAI5
PAI4
PAI3
PAI2
PAI1
PAI0
PAO7
PAO6
PAO5
PAO4
PAO3
PAO2
PAO1
PAO0
Bit 7-0: PAI7-0 Port A Input data
Bit 7-0: PAO7-0 Port A Output data
The logical level applied in the Port A pins,
configured as digital input, can be achieved by
reading this register.
The logical values written in these register bits are
put in the Port A pins configured as digital output.
Port B Data Output Register (PORT_B_OUT)
Output Register 1 (01h) Write only
Reset Value: 0000 0000 (00h)
Port B Data Input Register (PORT_B_IN)
Input Register 1 (01h) Read only
Reset Value: XXXX XXXX
7
0
7
0
PBO7* PBO6* PBO5** PBO4** PBO3** PBO2** PBO1
PBO0
PBI7*
PBI6*
PBI5**
PBI4** PBI3**
PBI2**
PBI1
PBI0
(*) Not used in 20 pin package devices
(**) Not usedin 16 pin package devices
(*) Not used in 20 pin package devices
(**) Not used in 16 pin package devices
Bit 7-0: PBO7-0 Port B Input data
Bit 7-0: PBI7-0 Port B Input data
51/94
ST52F500/F503/F504
The logical values written in these register bits are
put in the Port B pins configured as digital output.
Note: This register is not used in 16/20 pin devices
Bit 7-6: Not Used
Port C Data Output Register (PORT_C_OUT)
Output Register 2 (02h) Write only
Reset Value: 0000 0000 (00h)
Bit 5-0: PCO5-0 Port C Input data
The logical values written in these register bits are
put in the Port C pins configured as digital output.
7
0
-
-
PCO5
PCO4
PCO3
PCO2
PCO1
PCO0
52/94
ST52F500/F503/F504
8 FUZZY COMPUTATION (DP)
Figure 8.2 Alpha Weight Calculation
The ST52F500/F503/F504 Decision Processor
(DP) main features are:
j-th Mbf
1
■ Up to 8 Inputs with 8-bit resolution;
■ 1 Kbyte of Program/Data Memory available to
store more than 300 to Membership Functions
(Mbfs) for each Input;
ij
α
■ Up to 128 Outputs with 8-bit resolution;
i-th INPUT VARIABLE
■ Possibility of processing fuzzy rules with an
UNLIMITED number of antecedents;
■ UNLIMITED number of Rules and Fuzzy Blocks.
The limits on the number of Fuzzy Rules and
Fuzzy program blocks are only related to the
Program/Data Memory size.
After loading the input values by using the LDFR
assembler instruction, the user can start the fuzzy
inference by using the FUZZY assembler
instruction. During fuzzyfication: input data is
transformed in the activation level (alpha weight) of
the Mbf’s.
8.1 Fuzzy Inference
The block diagram shown in Figure 8.1 describes
the different steps performed during a Fuzzy
algorithm. The ST52F500/F503/F504 Core allows
for the implementation of a Mamdami type fuzzy
inference with crisp consequents. Inputs for fuzzy
inference are stored in 8 dedicated Fuzzy input
registers. The LDFR instruction is used to set the
Input Fuzzy registers with values stored in the
Register File. The result of a Fuzzy inference is
stored directly in a location of the Register File.
8.3 Inference Phase
The Inference Phase manages the alpha weights
obtained during the fuzzyfication phase to compute
the truth value (ω) for each rule.
This is a calculation of the maximum (for the OR
operator) and/or minimum (for the AND operator)
performed on alpha values according to the logical
connectives of Fuzzy Rules.
Several conditions may be linked together by
linguistic connectives AND/OR, NOT operators
and brackets.
The truth value ω and the related output singleton
are used by the Defuzzyfication phase, in order
to complete the inference calculation.
8.2 Fuzzyfication Phase
In this phase the intersection (alpha weight)
between the input values and the related Mbfs
(Figure 8.2) is performed.
Eight Fuzzy Input registers are available for Fuzzy
inferences.
Figure 8.1 Fuzzy Inference
1
2
11
1m
INFERENCE
PHASE
DEFUZZYFICATION
FUZZYFICATION
n1
N rules -1
N rules
nm
Input Values
Output Values
53/94
ST52F500/F503/F504
Figure 8.3 Fuzzyfication
8.5 Input Membership Function
The Decision Processor allows the management of
triangular Mbfs. In order to define an Mbf, three
different parameters must be stored on the
Program/Data Memory (see Figure 8.4):
IF INPUT 1 IS X1 OR INPUT 2 IS X2 THEN .......
1
α
■ the vertex of the Mbf: V;
α2
■ the length of the left semi-base: LVD;
■ the length of the right semi-base: RVD;
X1
Input 1
X2
Input
2
OR = Max
In order to reduce the size of the memory area and
the computational effort the vertical range of the
vertex is fixed between 0 and 15 (4 bits)
By using the previous memorization method
different kinds of triangular Membership Functions
may be stored. Figure 8.5 shows some examples
of valid Mbfs that can be defined in ST52F500/
F503/F504.
IF INPUT 1 IS X1 AND INPUT 2 IS X2 THEN .......
1
α
Each Mbf is then defined storing 3 bytes in the first
Kbyte of the Program/Data Memory.
α2
The Mbf is stored by using the following instruction:
X1
Input 1
X2
Input
2
MBF n_mbf lvd v rvd
where:
n_mbf is a tag number that identifies the Mbf
8.4 Defuzzyfication
lvd, v, and rvd are the parameters that describe the
Mbf’s shape as described above.
In this phase the output crisp values are
determined by implementing the consequent part
of the rules.
Each consequent Singleton X is multiplied by its
Figure 8.4 Mbfs Parameters
i
weight values ω , calculated by the Decision
i
processor, in order to compute the upper part of
the Defuzzyfication formula.
15
Each output value is obtained from the consequent
Input Mbf
crisp values (X ) by carrying out the following
i
Defuzzyfication formula:
N
Xijωij
0
j
V
Input Variable
RVD
---------------------
Yi =
N
LVD
ωij
j
where:
i = identifies the current output variable
N = number of the active rules on the current
output
Output Singleton
15
w
ω = weight of the j-th singleton
ij
X = abscissa of the j-th singleton
ij
The Decision Processor outputs are stored in the
RAM location i-th specified in the assembler
instruction OUT i.
0
X
Output Variable
54/94
ST52F500/F503/F504
Figure 8.5 Example of valid Mbfs
Figure 8.6 Output Membership Functions
j-th Singleton
1
ω
ij
ω
i0
ω
in
0
X
i-th OUTPUT
X
X
in
ij
i0
8.7 Fuzzy Rules
Rules can have the following structures:
if A op B op C...........then Z
if (A op B) op (C op D op E...) ...........then Z
where op is one of the possible linguistic operators
(AND/OR)
8.6 Output Singleton
The Decision Processor uses a particular kind of
membership function called Singleton for its output
variables. A Singleton doesn’t have a shape, like a
traditional Mbf, and is characterized by a single
point identified by the couple (X, w), where w is
calculated by the Inference Unit as described
earlier. Often, a Singleton is simply identified with
its Crisp Value X.
In the first case the rule operators are managed
sequentially; in the second one, the priority of the
operator is fixed by the brackets.
Each rule is codified by using an instruction set, the
inference time for a rule with 4 antecedents and 1
consequent is about 3 microseconds at 20 MHz.
The Assembler Instruction Set used to manage the
Fuzzy operations is reported in the table below.
Table 8.1 Fuzzy Instructions Set
Instruction
Description
MBF n_mbf Ivd v rvd
IS n m
Stores the Mbf n_mbf with the shape identified by the parameters Ivd, v and rvd
Fixes the alpha value of the input n with the Mbf m
Calculates the complementary alpha value of the input n with the Mbf m.
Implements the Fuzzy operation AND
ISNOT n m
FZAND
FZOR
Implements the Fuzzy operation OR
CON crisp
Multiplies the crisp value with the last ω weight
Performs Defuzzyfication and stores the currently Fuzzy output in the register
n_out
OUT n_out
FUZZY
Starts the computation of a sigle fuzzy variable
Modify the priority in the rule evaluation
(
)
55/94
ST52F500/F503/F504
Example 1:
IF Input IS NOT Mbf AND Input is Mbf OR Input IS Mbf THEN Crisp
1
1
1
4
12
3
8
is codified by the following instructions:
calculates the NOT α value of Input with Mbf and stores the result in internal registers
ISNOT 1 1
FZAND
IS 4 12
FZOR
1
1
implements the operation AND between the previous and the next alpha value evaluated
fixes the α value of Input with Mbf and stores the result in internal registers
4
12
implements the operation OR between the previous and the next alpha value evaluated
fixes the α value of Input with Mbf and stores the result in internal registers
IS 3 8
3
8
CON crisp multiplies the result of the last
Ω
operation with the crisp value crisp
1
1
Example 2, the priority of the operator is fixed by the brackets:
IF (Input IS Mbf AND Input IS NOT Mbf ) OR (Input IS Mbf OR Input IS NOT Mbf ) THEN Crisp
2
3
1
4
15
1
6
6
14
(
parenthesis open to change the priority
fixes the α value of Input with Mbf and stores the result in internal registers
IS 3 1
3
1
FZAND
implements the operation AND between the previous and the next alpha value evaluated
calculates the NOT α value of Input with Mbf and stores the result in internal registers
ISNOT 4 15
4
15
)
parenthesis closed
FZOR
implements the operation OR between the previous and the next alpha value evaluated
parenthesis open to change the priority
(
fixes the α value of Input with Mbf and stores the result in internal registers
IS 1 6
FZOR
ISNOT 2 14
)
1
6
implements the operation OR between the previous and the next alpha value evaluated
calculates the NOT α value of Input with Mbf and stores the result in internal registers
6
14
parenthesis closed
CON crisp multiplies the result of the last
Ω operation with the crisp value crisp
2
2
At the end of the fuzzy rules related to the current Fuzzy Variable, by using the instruction OUT reg, the
specified register is written with the computed value. Afterwards, the control of the algorithm returns to the
CU. The next Fuzzy Variable evaluation must start again with a FUZZY instruction.
56/94
ST52F500/F503/F504
9 INSTRUCTION SET
operands can refer (according to the opcode) to
addresses belonging to the different addressing
spaces. Example: SUB, LDRE.
ST52F500/F503/F504 supplies 107 (98 + 9 Fuzzy)
instructions that perform computations and control
the device. Computational time required for each
instruction consists of one clock pulse for each
Cycle plus 2 clock pulses for the decoding phase.
Total computation time for each instruction is
reported in Table 9.1
The ALU of ST52F500/F503/F504 can perform
multiplication (MULT) and division (DIV).
Multiplication is performed by using 8 bit operands
storing the result in 2 registers (16 bit values), see
Figure 2.3.
■ Indirect: data addresses that are required are
found in the locations specified as operands.
Both source and/or destination operands can be
addressed indirectly. The operands can refer,
(according to the opcode) to addresses
belonging to different addressing spaces.
Examples: LDRR(reg1),(reg2);
LDER mem_addr,(reg1).
■ Bit Direct: operands of these instructions directly
address the bits of the specified Register File
locations. Examples: BSET, BTEST.
Division is performed between a 16 bit dividend
and an 8 bit divider, the result and the remainder
are stored in two 8-bit registers (see Figure 2.4).
9.2 Instruction Types
9.1 Addressing Modes
ST52F500/F503/F504 supplies the following
instruction types:
■ Load Instructions
ST52F500/F503/F504 instructions allow the
following addressing modes:
■ Inherent: this instruction type does not require
an operand because the opcode specifies all the
information necessary to carry out the
■ Arithmetic and Logic Instructions
■ Bitwise instructions
instruction. Examples: NOP, SCF.
■ Jump Instructions
■ Immediate: these instructions have an operand
as a source immediate value. Examples: LDRC,
ADDI.
■ Interrupt Management Instructions
■ Control Instructions
■ Direct: the operands of these instructions are
The instructions are listed in Table 9.1
specified with the direct addresses. The
Table 9.1 Instruction Set
Load Instructions
Bytes Cycles
(*)
Mnemonic
BLKSET
GETPG
LDCE
Instruction
Z
-
-
-
-
-
-
-
-
-
-
-
S
-
-
-
-
-
-
-
-
-
-
-
C
-
-
-
-
-
-
-
-
-
-
-
BLKSET const
2
GETPG regx
2
3
3
3
3
3
3
3
3
3
7
8/9
7
LDCE confx,memy
LDCI confx, const
LDCNF regx, conf
LDCR confx, regy
LDER memx, regy
LDER (regx),(regy)
LDER (regx), regy
LDER memx,(regy)
LDFR fuzzyx, regy
LDCI
LDCNF
LDCR
7
8
LDER
10
11
10
11
8
LDER
LDER
LDER
LDFR
57/94
ST52F500/F503/F504
Load Instructions (continued)
LDPE
LDPE
LDPI
LDPE outx, memy
3
3
3
3
3
3
3
3
3
3
3
3
3
3
2
2
2
2
8/9
9/10
7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LDPE outx, (regy)
LDPI outx, const
LDPR outx, regy
LDRC regx, const
LDRE regx, memy
LDRE (regx), (regy)
LDRE (regx), memy
LDRE regx, (regy)
LDRI regx, inpx
LDRR regx, regy
LDRR (regx), (regy)
LDRR (regx), regy
LDRR regx, (regy)
PGSET const
LDPR
LDRC
LDRE
LDRE
LDRE
LDRE
LDRI
8
7
8/9
10/11
9/10
9/10
7
LDRR
LDRR
LDRR
LDRR
PGSET
PGSETR
POP
9
10
9
10
4
PGSETR regx
5
POP regx
7
PUSH
PUSH regx
8
Arithmetic Instructions
Mnemonic
ADD
Instruction
ADD regx, regy
ADDC regx, regy
ADDI regx, const
ADDIC regx, const
ADDO regx, regy
ADDOC regx, regy
ADDOI regx, const
ADDOICregx,cons
AND regx, regy
ANDI regx,const
CP regx, regy
Bytes
Cycles
Z
S
C
3
3
3
3
3
3
3
3
3
3
3
3
2
9
9
I
I
I
I
I
I
I
I
I
I
I
I
I
-
-
-
-
I
I
I
I
-
-
I
I
I
I
I
I
I
I
I
I
I
-
-
-
-
-
ADDC
ADDI
8
ADDIC
ADDO
ADDOC
ADDOI
ADDOIC
AND
8
11
11
10
10
9
ANDI
8
CP
8
CPI
CPI regx,const
DEC regx
7
DEC
7
58/94
ST52F500/F503/F504
Arithmetic Instructions (continued)
DIV
INC
DIV regx, regy
INC regx
3
2
2
3
2
3
3
3
3
3
3
3
3
3
3
1
1
1
1
1
1
3
3
16
7
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
-
-
I
-
-
I
I
I
I
-
-
-
-
-
-
I
I
I
MIRROR
MULT
NOT
MIRROR regx
MULT regx, regy
NOT regx
7
-
-
-
-
-
-
-
-
I
11
7
OR
OR regx, regy
ORI regx, const
SUB regx, regy
SUBI regx, const
SUBIS regx, const
SUBO regx, regy
SUBOI regx,
SUBOISregx,const
SUBOS regx, regy
SUBS regx, regy
RCF
9
ORI
8
SUB
9
SUBI
SUBIS
SUBO
SUBOI
SUBOIS
SUBOS
SUBS
RCF
8
I
8
I
11
10
10
11
9
I
I
I
I
I
I
I
I
-
I
4
-
I
RSF
RSF
4
-
-
I
RZF
RZF
4
-
-
I
SCF
SCF
4
SSF
SSF
4
-
-
-
-
SZF
SZF
4
-
-
-
XOR
XOR regx, regy
XORI regx, cons
9
XORI
8
Bitwise Instructions
Mnemonic
ASL
Instruction
ASL regx
Bytes
Cycles
Z
I
S
-
I
C
I
2
2
3
3
3
3
3
2
7
7
8
8
8
7
7
7
ASR
ASR regx
I
-
-
-
-
-
-
I
BNOT
BRES
BSET
BTEST
MTEST
RLC
BNOT regx, bit
BRES regx, bit
BSET regx, bit
BTEST regx, bit
MTEST regx,const
RLC regx
I
-
-
-
-
-
-
I
I
I
I
I
59/94
ST52F500/F503/F504
Bitwise Instructions (continued)
ROL
ROR
RRS
ROL regx
2
2
2
7
7
7
I
I
I
-
I
I
I
-
-
ROR regx
RRS regx
Jump Instructions
Mnemonic
CALL
JP
Instruction
CALL addr
JP addr
Bytes
Cycles
11
Z
-
-
-
-
-
-
-
-
-
S
-
C
-
3
3
3
3
3
3
3
3
1
6
-
-
JPC
JPC addr
JPNC addr
JPNS addr
JPNZ addr
JPS addr
JPZ addr
RET
5/6
5/6
5/6
5/6
5/6
5/6
8
-
-
JPNC
JPNS
JPNZ
JPS
-
-
-
-
-
-
-
-
JPZ
-
-
RET
-
-
Interrupt Management Instructions
Mnemonic
HALT
MEGI
MDGI
RETI
Instruction
HALT
Bytes
Cycles
Z
-
-
-
-
-
-
-
-
-
S
-
C
-
1
1
1
1
2
1
1
1
1
4/13
6/11
5
MEGI
-
-
MDGI
-
-
RETI
9
-
-
RINT
RINT INT
UDGI
6
-
-
UDGI
5
-
-
UEGI
UEGI
6/11
9
-
-
TRAP
WAITI
TRAP
-
-
WAITI
7/10
-
-
Control Instructions
Mnemonic
Instruction
Bytes
Cycles
Z
S
C
FUZZY
FUZZY
1
1
1
1
4
-
-
-
NOP
NOP
5
6
5
-
-
-
-
-
-
-
-
-
WDTRFR
WDTSLP
WDTRFR
WDTSLP
60/94
ST52F500/F503/F504
Notes:
regx, regy:
memx, memy:
confx, confy:
outx:
Register File Address
Program/Data Memory Addresses
Configuration Registers Addresses
Output Registers Addresses
Input Registers Addresses
Constant value
inpx:
const:
fuzzyx:
I
Fuzzy Input Registers
flag affected
-
flag not affected
(*) The instruction BLKSET determines the start of a 32 byte block writing in Flash or EEPROM Program/
Data Memory. During this phase (about 4 ms), the CPU is stopped to executing program instructions. The
duration of the BLKSET instruction can be identified with this time.
61/94
ST52F500/F503/F504
10 WATCHDOG TIMER
The working frequency of WDT (PRES CLK in the
Figure 10.1) is equal to the clock master. The clock
master is divided by 500, obtaining the WDT CLK
signal that is used to fix the timeout of the WDT.
According to the WDT_CR Configuration Register
values, a WDT delay between 0.1ms and 937.5ms
can be defined when the clock master is 5 MHz. By
changing the clock master frequency the timeout
delay can be calculated according to the
configuration register values. The first 4 bits of the
WDT_CR register are used, obtaining 16 different
delays.
10.1 Functional Description
The Watchdog Timer (WDT) is used to detect the
occurrence of a software fault, usually generated
by external interference or by unforeseen logical
conditions, which causes the application program
to abandon its normal sequence. The WDT circuit
generates an ICU reset on expiry of a programmed
time period, unless the program refreshes the
WDT before the end of the programmed time
delay. Sixteen different delays can be selected by
using the WDT configuration register.
After the end of the delay programmed by the
configuration register, if the WDT is active, it starts
a reset cycle pulling the reset signal low.
Table 10.1 Watchdog Timing Range (5 MHz)
WDT timeout period (ms)
Once the WDT is activated, the application
program has to refresh the counter (by the
WDTRFR instruction) during normal operation in
order to prevent an ICU reset.
min
0.1
max
937.5
In ST52F500/F503/F504 devices it is possible to
choose between “Hardware” or “Software”
Watchdog. The Hardware WDT allows the
counting to avoid unwanted stops for external
interferences. The first mode is always enabled
unless the Option Byte 4 (WDT_EN) is written with
a special code (10101010b): only this code can
switch the WDT in “Software” Mode, the other 255
possibilities keep the “Hardware” Mode enabled.
10.2 Register Description
SW Watchdog Enable (WDT_EN)
Option Byte 4 (04h)
Reset Value: 0000 0000 (00h)
7
0
When the software mode is enabled, it is possible
to stop the WDT during the user program
executions by using the WDTSLP instruction.
WDTEN7 WDTEN6 WDTEN5 WDTEN4 WDTEN3 WDTEN2 WDTEN1 WDTEN0
When the WDT is in Hardware Mode, neither the
WDTSLP instruction nor external interference can
stop the counting. The “Hardware” WDT is always
enabled after a Reset.
Bit 7-0: WDTEN7-0 SW Watchdog Enable byte
Writing the code 10101010 in this byte the
Software Watchdog mode is enabled.
Figure 10.1 Watchdog Block Diagram
Configuration Register
D3 D2 D1 D0
WDT
RESET
WDTRFR
RESET
WTD CLK
RESET
PRESCALER
GENERATOR
PRES CLK = CLK MASTER
WDTSLP
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ST52F500/F503/F504
Watchdog Control Register (WDT_CR)
Configuration Register 7 (07h) Read/Write
Reset Value: 0000 0001 (00h)
Bit 3-0: D3-0 Watchdog Clock divisor factor bits
The Watchdog Clock (WDT CLK) is divided
by the numeric factor determined by these
bits, according with Table 10.2 and the
following formula:
7
0
5 × 105 × DivisionFactor
-
-
-
-
D3
D2
D1
D0
---------------------------------------------------------------- -
Timeout(ms) =
Clock(MHz)
Bit 7-4: Not Used
Table 10.2 Watchdog Timeout configuration examples
Timeout Values (ms)
WDT_CR(3:0)
Division Factor
5 MHz
10 MHz
20MHz
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
1
0.1
0.05
0.025
625
62.5
125
31.25
62.5
15.625
31.25
1250
1875
2500
3125
3750
4375
5000
5625
6250
6875
7500
8125
8750
9375
187.5
250
93.75
125
46.875
62.5
312.5
375
156.25
187.5
218.75
250
78.125
93.75
437.5
500
109.375
125
562.5
625
281.25
312.5
343.75
375
140.625
156.25
171.875
187.5
687.5
750
812.5
875
406.25
437.5
468.75
203.125
218.75
234.375
937.5
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ST52F500/F503/F504
11 PWM/TIMERS
11.1 Introduction
ST52F500/503/504 offers two on-chip PWM/Timer
peripherals. All ST52F500/503/504 PWM/Timers
have the same internal structure. The timer
The Input Registers couple PWMx_CAPTURE_x
store the counter value after the last Stop signal
(only Timer Mode). The counter value is not stored
after a Reset Signal.
The peripheral status can also be read from the
Input Registers (one for each Timer). These
registers report START/STOP, SET/RESET
status, TxOUT signal and the counter overflow
flag. This last signal is set after the first EOC and it
is reset by a Timer RESET (internal or external).
consists of
a 16-bit counter with a 16-bit
programmable Prescaler, giving a maximum count
32
of 2 (see Figure 11.1).
Each timer has two different working modes, which
can be selected by setting the correspondent bit
TxMOD of the PWMx_CR1 Configuration
Register: Timer Mode and PWM (Pulse Width
Modulation) Mode.
11.2 Timer Mode
Timer Mode is selected writing 0 in the TxMOD bit.
Each Timer requires three signals: Timer Clock
(TMRCLKx), Timer Reset (TxRES) and Timer Start
(TxSTRT) (see Figure 11.1). Each of these signals
can be generated internally, and/or externally only
for Timer 0, by using T0RES, T0STRT and T0CLK
pins.
The Prescaler output (PRESCOUT) increments
the Counter value on the rising edge. PRESCOUT
is obtained from the internal clock signal (CLKM)
or, only for TIMER0, from the external signal
provided on the apposite pin.
All the Timers have Autoreload Functions; in PWM
Mode the reload value can be set by the user.
Each timer output is available on the apposite
external pins configured in Alternate Function and
in one of the Output modes.
PWM/Timer 0 can also use external START/STOP
signals in order to perform Input capture and
Output compare, external RESET signal, and
external CLOCK to count external events:
T0STRT, T0RES and T0CLK pins. In addition, the
START/STOP and RESET signals have
configurable polarity (falling or rising edge).
Note: The external clock signal applied on the
T0CLK pin must have a frequency that is at least
two times smaller than the internal master clock.
Remark: To use T0RST, T0STR, T0CLK external
signals the related pins must be configured in
Alternate Function and in one of Input modes.
The prescaler output period can be selected by
setting the TxPRESC bits with one of the 17
division factors available. TMRCLK frequency is
divided by a factor equal to the power of two of the
For each timer, the contents of the 16-bit counter
are incremented on the Rising Edge of the 16-bit
prescaler output (PRESCOUT) and it can be read
at any instant of the counting phase by accessing
the Input Registers PWMx_COUNT_IN_x; the
value is stored in two 8-bit registers (MSB and
LSB) for each PWM/Timer.
16
prescaler values (up to 2 ).
TxRES resets the content of the 16-bit counter to
zero. It is generated by writing 0 in the TxRES bit
of the PWMx_CR1 Configuration Register and/or it
can be driven by the T0RES pin if configured (only
Timer0).
Figure 11.1 PWM/Timer Counter block diagram
16-BITPRESCALER
BIT 5
TMRCLKx
BIT 14
BIT15
BIT 0
BIT 1
BIT 2
BIT3
BIT 4
PRESCx
17 - 1 MULTIPLEXER
PRESCOUT
TxRES
16-BIT COUNTER
BIT 3 BIT 4 BIT 5
BIT 0
BIT 1
BIT 2
BIT 14
BIT15
TxSTRT
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ST52F500/F503/F504
Figure 11.2 Timer 0 External Start/Stop Mode
start
start
stop
Level
stop
start
start
Edge
Reset
Clock
Counted
Value
2
0
1
3
4
4
0
1
TxSTRT signal starts/stops the Timer from
counting only if the peripherals are configured in
Timer mode. The Timers are started by writing 1 in
the TXSTRT bit of the PWMx_CR1 and are
stopped by writing 0. This signal can be generated
internally and/or externally by forcing the T0STRT
pin (only TIMER0).
TIMER 0 START/STOP can be given externally on
the T0STRT pin. In this case, the T0STRT signal
allows the user to work in two different configurable
modes:
Note: the contents of these registers upgrades the
Timer counter after it stops counting. Since the
register couple is written in two steps this can
cause side effects. In order to avoid this, the user
should write the MSB before writing the LSB:
actually, the 16-bit value is latched in parallel when
the LSB is written. By writing only the LSB (and
MSB equal to 0), the PWM/Timer is used as with
an 8 bit counter.
There can be two types of TxOUT waveforms:
■ type 1: TxOUT waveform equal to a square
wave with a 50% duty-cycle
■ LEVEL (Time Counter): If the T0STRT signal is
high, the Timer starts counting. When the
T0STRT is low the timer stops counting and the
16-bit current value is stored in the
■ type 2: TxOUT waveform equal to a pulse signal
with the pulse duration equal to the Prescaler
output signal.
PWM0_COUNT_IN_x Input Registers couple.
■ EDGE (Period Counter): After reset, on the first
T0STRT rising edge, TIMER 0 starts counting
and at the next rising edge it stops. In this
manner the period of an external signal may be
measured.
Figure 11.3 TxOUT Signal Types
The same modes are available for the T0RES pin
signal.
Prescout*Counter
Timer Output
The polarity of the T0SRTR Start/Stop signal can
be changed by setting the STRPOL and RESPOL
bits in the INT_POL Configuration Register (01h bit
3 and 4). When these bits are set, the PWM/Timer
0 is Started/Set on the low level or in the falling
edge of the signal applied in the pins.
The Timer output signal, TxOUT, is a signal with a
frequency equal to the one of the 16 bit-Prescaler
output signal, PRESCOUTx, divided by a 16-bit
counter set by writing the Output Register couple
PWMx_COUNT_OUT_x.
Type 1
Type 2
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ST52F500/F503/F504
Figure 11.4 PWM Mode with Reload
65535
Reload
Value
Counter
Value
0
t
PWM
Output
Ton
t
T
11.3 PWM Mode
Ton
-------
T
PWMxCOUNT
PWMxRELOAD
The PWM working mode for each timer is obtained
by setting the TxMOD bit of the Configuration
Register PWMx_CR1.
-----------------------------------------
=
dcycle
=
Note: the PWM_x_COUNT value must be lower
than or equal to the PWM_X_RELOAD value.
When it is equal, the TxOUT signal is always at
high level. If the Output Register PWM_x_COUNT
is 0, TxOUT signal is always at a low level.
The TxOUT signal in PWM Mode consists of a
signal with a fixed period, whose duty cycle can be
modified by the user.
The TxOUT period is fixed by setting the 16-bit
Prescaler bits (TxPRESC) in the PWMx_CR2 and
the 16-bit Reload value by writing the relative
Output Registers couple PWMx_RELOAD_x. The
16-bit Prescaler divides the master clock CLKM by
powers of two, determining the maximum length
period.
Reload determines the maximum value that the
counter can count before starting a new period.
The use of the two 16-bit values allows the TxOUT
period to be set with more precision when needed.
By setting the Reload value the counting resolution
decreases. In order to obtain the maximum
resolution, Reload value should be set to 0FFFFh
and the period corresponds to the one established
by the Prescaler value.
The value set in the 16-bit counter by writing the
Counter Output Registers couple, determines the
duty-cycle: when count reaches the Counter value
the TxOUT signal changes from high to low level.
By using a 24 MHz clock a PWM frequency that is
close to 100 Khz can be obtained.
The TIMER0 clock CLKM can also be supplied
with an external signal, applied on the T0CLK pin,
which must have a frequency that is at least two
times smaller than the internal master clock.
Note: he Timers have to complete the previous
counting phase before using a new value of the
Counter. If the Counter value is changed during
counting, the new values of the timer Counter are
only used at the end of the previous counting
phase. The Counter buffer is written in two steps
(one byte per time) and is latched only after the
LSB is written. In order to avoid side effects, the
user should write the MSB before writing the LSB.
By only writing the LSB, the PWM/Timer is used as
with a 8 bit counter. The same mechanism is
applied to the two bytes of Reload but, differently
of the Counter it is set immediately. Nevertheless,
it is recommended that the Reload value be written
when the Timer is stopped in order to avoid
incongruence with the Counter value. The same
recommendation is made when reading the two
bytes of the counter: It is performed in two steps,
so if the timer is running, the carry of the LSB to the
MSB can cause the wrong 16-bit value reading. A
Reload value greater than 1 must always be used.
The period of the PWM signal is obtained by using
the following formula:
TxPRESC
T=PWMx RELOAD * 2
TMRCLKx
-
where TxPRES equals the value set in the
TxPRESC bits of the PWMx_CR2 Configuration
Register and TMRCLKx is the period of the Timer
clock that drives the Prescaler.
The duty cycle of the PWM signal is obtained by
the following formula:
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ST52F500/F503/F504
When the Timers are in Reset status, or when the
device is reset, the TxOUT pins goes in threestate.
If these outputs are used to drive external devices,
it is recommended that the related pins be left in
the default configuration (Input threestate) or
change them in this configuration.
11.5 PWM/Timer 0 Register Description
The following registers are related to the use of the
PWM/Timer 0.
11.5.1 PWM/Timer 0 Configuration Registers.
In PWM mode the PWM/Timers can only be Set or
Reset: Start/Stop signals do not affect the Timers.
TxRES resets the content of the 16-bit counter to
PWM/Timer 0 Control Register 1 (PWM0_CR1)
Configuration Register 9 (09h) Read/Write
Reset Value: 0000 0000 (00h)
zero. It is generated by writing
0 in the
corresponding TxRES bit of the PWMx_CR1
Configuration Register and/or it can be driven by
the T0RES pin if it is configured (only Timer0).
7
0
Warning: in PWM mode, the TxSTRT signal must
be kept to 1 when the Timer is in Set state. This
can be achieved by writing 1 in the related bit of the
Configuration Register
T0MOD T0IES
T0IEF
T0IER STRMOD T0STRT RESMOD T0RES
Bit 7: T0MOD PWM/Timer 0 Mode
0: Timer Mode
11.3.1 Simultaneous Start. The PWM/Timers
can be started simultaneously when working in
PWM mode. The T0SYNC and T1SYNC bits in
PWM0_CR3 Configuration Registers mask the
reset of each timer; after enabling each single
PWM/Timer. They are started by putting off the
mask with a single writing in the PWM0_CR3
Register.
1: PWM Mode
Bit 6: T0IES Interrupt on Stop signal Enable
0: interrupt disabled
1: interrupt enabled
Simultaneous start is also possible in Timer mode.
The timers start counting simultaneously, but the
output pulses are generated according to the
modality configured (square or pulse mode).
Bit 5: T0IEF Interrupt on T0OUT falling Enable
0: interrupt disabled
1: interrupt enabled
11.4 Timer Interrupts
Bit 4: T0IES Interrupt on T0OUT rising Enable
0: interrupt disabled
The PWM/Timer can be programmed to generate
an Interrupt Request, both on the falling and the
rising of the TxOUT signal and when there’s a
STOP signal (external or internal).
By using the TxIES, TxIER and TxIEF bits of the
Configuration Registers PWMx_CR1, the interrupt
sources can be switched on/off. All the interrupt
sources may be activated at the same time:
sources can be distinguished by reading the
PWMx_STATUS Input Register.
1: interrupt enabled
Bit 3: STRMOD Start signal mode
0: start on level
1: start on edge
Bit 2: T0STRT PWM/Timer 0 Start bit
0: Timer 0 stopped
The interrupt on the falling edge corresponds to
half of a counting period in Timer mode when the
waveform is set to Square Wave and to the end of
the Ton phase in PWM mode.
1: Timer 0 started
Bit 1: RESMOD Reset signal mode
0: start on level
Note: when the PWM Counter is set to 0 or 65535,
the interrupt occurs at the end of each control
period.
1: start on edge
In order to be active, the PWM/Timers interrupts
must be enabled by writing the Interrupt Mask
Register (INT_MASK) in the Configuration
Register Space, bits MSKT0 And MSKT1.
Bit 0: T0RES PWM/Timer 0 Reset bit
0: PWM/Timer 0 reset
1: PWM/Timer 0 set
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ST52F500/F503/F504
PWM/Timer 0 Control Register 2 (PWM0_CR2)
Configuration Register 10 (0Ah) Read/Write
Reset Value: 0000 0000 (00h)
Bit 3-2: RESSRC PWM/Timer 0 Reset source
00: Internal from T0STRT bit
01: External from T0STRT pin
10: Both internal and external
7
4
0
-
-
T0WAV
T0PRESC
Interrupt Polarity Register (INT_POL)
Configuration Register 1 (01h) Read/Write
Reset Value: 0000 0000 (00h)
Bit 7-6: Not Used
7
0
Bit 5: T0WAV T0OUT Waveform
0: pulse (type2)
-
-
LVD_EN RESPOL STRPOL POLPB POLPA POLNMI
1: square (type1)
Bit 7-6: Not Used
Bit 4-0: T0PRESC PWM/Timer 0 Prescaler
The PWM/Timer 0 clock is divided by a
T0PRESC
Bit 5: See LVD Registers Description
factor equal to 2
. The maximum
value allowed for T0PRESC is 10000
(010h).
Bit 4: RESPOL Reset signal polarity
0: Reset on low level/falling edge
1: Reset on high level/rising edge
PWM/Timer 0 Control Register 3 (PWM0_CR3)
Configuration Register 11 (0Bh) Read/Write
Reset Value: 0000 0000 (00h)
Bit 3: STRPOL Start signal polarity
0: Start on high level/rising edge
1: Start on low level/falling edge
7
0
T0SYNC
-
T1SYNC T0CKS
STRSRC
RESSRC
Bit 2-0: See Interrupt Registers Description
Bit 7: T0SYNC PWM/Timer 0 Set/Reset mask
0: Set/Reset activated
11.5.2 PWM/Timer 0 Input Registers.
1: Set/Reset masked
PWM/Timer 0 Counter High Input Register
(PWM0_COUNT_IN_H)
Bit 6: not used
Input Register 21 (015h) Read only
Reset Value: 0000 0000 (00h)
Bit 5: T1SYNC PWM/Timer 1 Set/Reset mask
0: Set/Reset activated
7
0
1: Set/Reset masked
T0CI15 T0CI14 T0CI13 T0CI12 T0CI11 T0CI10 T0CI9
T0CI8
Bit 4: T0CKS PWM/Timer 0 Clock Source
0: Internal clock
1: External Clock from T0CLK
Bit 7-0: T0CI15-8 PWM/Timer 0 Counter MSB
Bit 3-2:STRSRC PWM/Timer 0 Start signal source
00: Internal from T0STRT bit
In this register the current value of the Timer 0
Counter MSB can be read.
01: External from T0STRT pin
10: Both internal and external
68/94
ST52F500/F503/F504
PWM/Timer 0 Counter Low Input Register
(PWM0_COUNT_IN_L)
Bit 7-0: T0CP15-8 PWM/Timer 0 Capture MSB
Input Register 22 (016h) Read only
Reset Value: 0000 0000 (00h)
In this register the counter value after the last stop
can be read.
7
0
PWM/Timer 0 Capture Low Input Register
(PWM0_CAPTURE_L)
T0CI7
T0CI6
T0CI5
T0CI4
T0CI3
T0CI2
T0CI1
T0CI0
Input Register 25 (019h) Read only
Reset Value: 0000 0000 (00h)
Bit 7-0: T0CI7-0 PWM/Timer 0 Counter MSB
7
0
In this register the current value of the Timer 0
Counter LSB can be read.
T0CP7 T0CP6 T0CP5 T0CP4 T0CP3 T0CP2 T0CP1 T0CP0
PWM/Timer 0 Status Register (PWM0_STATUS)
Input Register 23 (017h) Read only
Reset Value: 0000 0000 (00h)
Bit 7-0: T0CP7-0 PWM/Timer 0 Capture LSB
In this register the counter value after the last stop
can be read.
7
0
-
-
-
-
T0OVFL T0OUT T0RST T0SST
11.5.3 PWM/Timer 0 Output Registers.
Bit 7-4: Not Used
PWM/Timer 0 Counter High Output Register
(PWM0_COUNT_OUT_H)
Output Register 7 (07h) Write only
Reset Value: 0000 0000 (00h)
Bit 3: T0OVFL PWM/Timer 0 counter overflow flag
0: no overflow occurred since last reset
1: overflow occurred
7
0
Bit 2: T0OUT T0OUT pin value
0: T0OUT pin is at logical level 0
1: T0OUT pin is at logical level 1
T0CO15 T0CO14 T0CO13 T0CO12 T0CO11 T0CO10 T0CO9 T0CO8
Bit 7-0: T0CO15-8 PWM/Timer 0 Counter MSB
Bit 2: T0RST Reset Status
0: PWM/Timer 0 is reset
1: PWM/Timer 0 is set
This register is used to write the Timer 0 Counter
value (MSB).
Note: this register is latched after writing the LSB
part (PWM_COUNT_OUT_L: see below). For this
reason this register must be written before the
LSB.
Bit 2: T0SST Start Status
0: PWM/Timer 0 is stopped
1: PWM/Timer 0 is running
PWM/Timer 0 Counter Low Output Register
(PWM0_COUNT_OUT_L)
PWM/Timer 0 Capture High Input Register
(PWM0_CAPTURE_H)
Input Register 24 (018h) Read only
Reset Value: 0000 0000 (00h)
Output Register 8 (08h) Write only
Reset Value: 0000 0000 (00h)
7
0
7
0
T0CO7 T0CO6 T0CO5 T0CO4 T0CO3 T0CO2 T0CO1 T0CO0
T0CP15 T0CP14 T0CP13 T0CP12 T0CP11 T0CP10 T0CP9 T0CP8
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ST52F500/F503/F504
Bit 7-0: T0CO7-0 PWM/Timer 0 Counter MSB
11.6 PWM/Timer 1 Register Description
The following registers are related to the use of the
PWM/Timer 1.
This register is used to write the Timer 0 Counter
value (LSB).
Note:
writing
this
register,
the
11.6.1 PWM/Timer 1 Configuration Registers.
PWM0_COUNT_OUT_x couple is latched in the
internal registers of the peripherals. For this
reason, this register should be written after the
MSB one.
PWM/Timer 1 Control Register 1 (PWM1_CR1)
Configuration Register 12 (0Ch) Read/Write
Reset Value: 0000 0000 (00h)
PWM/Timer 0 Reload High Output Register
(PWM0_RELOAD_H)
7
0
Output Register 9 (09h) Write only
Reset Value: 1111 1111 (0FFh)
T0MOD T0IES
T0IEF
T0IER
-
T0STRT
-
T0RES
7
0
Bit 7: T1MOD PWM/Timer 1 Mode
0: Timer Mode
T0REL15T0REL14 T0REL13 T0REL12 T0REL11T0REL10 T0REL9 T0REL8
1: PWM Mode
Bit 7-0: T0REL15-8 PWM/Timer 0 Reload MSB
Bit 6: T1IES Interrupt on Stop signal Enable
0: interrupt disabled
This register is used to write the Timer 0 Reload
value (MSB).
1: interrupt enabled
Note: this register is latched after writing the LSB
part (PWM0_RELOAD_L: see below). For this
reason, this register must be written before the
LSB.
Bit 5: T1IEF Interrupt on T1OUT falling Enable
0: interrupt disabled
1: interrupt enabled
Bit 4: T1IES Interrupt on T1OUT rising Enable
0: interrupt disabled
PWM/Timer 0 Reload Low Output Register
(PWM0_RELOAD_L)
1: interrupt enabled
Output Register 10 (0Ah) Write only
Reset Value: 1111 1111 (0FFh)
Bit 3: not used
7
0
Bit 2: T1STRT PWM/Timer 1 Start bit
0: Timer 0 stopped
T0REL7 T0REL6 T0REL5 T0REL4 T0REL3 T0REL2 T0REL1 T0REL0
1: Timer 0 started
Bit 7-0: T0REL7-0 PWM/Timer 0 Reload LSB
Bit 1: not used
This register is used to write the Timer 0 Reload
value (LSB).
Bit 0: T1RES PWM/Timer 1 Reset bit
0: PWM/Timer 0 reset
Note:
by
writing
this
register,
the
1: PWM/Timer 0 set
PWM0_RELOAD_x couple is latched in the
internal registers of the peripherals. For this reason
this register should be written after the MSB one.
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ST52F500/F503/F504
PWM/Timer 1 Control Register 2 (PWM1_CR2)
Configuration Register 13 (0Dh) Read/Write
Reset Value: 0000 0000 (00h)
In this register the current value of the Timer 0
Counter LSB can be read.
7
4
0
PWM/Timer 1 Status Register (PWM1_STATUS)
Input Register 28 (01Ch) Read only
Reset Value: 0000 0000 (00h)
-
-
T1WAV
T1PRESC
7
0
Bit 7-6: Not Used
-
-
-
-
T1OVFL T1OUT T1RST T1SST
Bit 5: T1WAV T1OUT Waveform
0: pulse (type2)
Bit 7-4: Not Used
1: square (type1)
Bit 3: T1OVFL PWM/Timer 1 counter overflow flag
0: no overflow occurred since last reset
1: overflow occurred
Bit 4-0: T1PRESC PWM/Timer 1 Prescaler
The PWM/Timer 1 clock is divided by a
T1PRESC
factor equal to 2
. The maximum
value allowed for T1PRESC is 10000
(010h).
Bit 2: T1OUT T1OUT pin value
0: T1OUT pin is at logical level 0
1: T1OUT pin is at logical level 1
11.6.2 PWM/Timer 1 Input Registers.
Bit 2: T1RST Reset Status
0: PWM/Timer 1 is reset
1: PWM/Timer 1 is set
PWM/Timer 1 Counter High Input Register
(PWM1_COUNT_IN_H)
Input Register 26 (01Ah) Read only
Reset Value: 0000 0000 (00h)
Bit 2: T1SST Start Status
0: PWM/Timer 1 is stopped
1: PWM/Timer 1 is running
7
0
T1CI15 T1CI14 T1CI13 T1CI12 T1CI11 T1CI10 T1CI9
T1CI8
PWM/Timer 1 Capture High Input Register
(PWM1_CAPTURE_H)
Input Register 29 (01Dh) Read only
Reset Value: 0000 0000 (00h)
Bit 7-0: T1CI15-8 PWM/Timer 1 Counter MSB
In this register the current value of the Timer 1
Counter MSB can be read.
7
0
T1CP15 T1CP14 T1CP13 T1CP12 T1CP11 T1CP10 T1CP9 T1CP8
PWM/Timer 1 Counter Low Input Register
(PWM1_COUNT_IN_L)
Bit 7-0: T1CP15-8 PWM/Timer 1 Capture MSB
Input Register 27 (01Bh) Read only
Reset Value: 0000 0000 (00h)
In this register the counter value after the last stop
can be read.
7
0
T1CI7
T1CI6
T1CI5
T1CI4
T1CI3
T1CI2
T1CI1
T1CI0
PWM/Timer 1 Capture Low Input Register
(PWM1_CAPTURE_L)
Bit 7-0: T1CI7-0 PWM/Timer 1 Counter MSB
Input Register 30 (01Eh) Read only
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Reset Value: 0000 0000 (00h)
PWM/Timer 1 Reload High Output Register
(PWM1_RELOAD_H)
7
0
Output Register 13 (0Dh) Write only
Reset Value: 1111 1111 (0FFh)
T1CP7 T1CP6 T1CP5 T1CP4 T1CP3 T1CP2 T1CP1 T1CP0
7
0
Bit 7-0: T1CP7-0 PWM/Timer 1 Capture LSB
T1REL15 T1REL14 T1REL13 T1REL12T1REL11 T1REL10 T1REL9 T1REL8
In this register the counter value after the last stop
can be read.
Bit 7-0: T1REL15-8 PWM/Timer 0 Reload MSB
This register is used to write the Timer 1 Reload
value (MSB).
11.6.3 PWM/Timer 1 Output Registers.
Note: this register is latched after writing the LSB
part (PWM1_RELOAD_L: see below). For this
reason, this register must be written before the
LSB.
PWM/Timer 1 Counter High Output Register
(PWM1_COUNT_OUT_H)
Output Register 11 (0Bh) Write only
Reset Value: 0000 0000 (00h)
PWM/Timer 1 Reload Low Output Register
(PWM0_RELOAD_L)
7
0
Output Register 14 (0Eh) Write only
Reset Value: 1111 1111 (0FFh)
T1CO15 T1CO14 T1CO13 T1CO12 T1CO11 T1CO10 T1CO9 T1CO8
7
0
Bit 7-0: T1CO15-8 PWM/Timer 1 Counter MSB
T1REL7 T1REL6 T1REL5 T1REL4 T1REL3 T1REL2 T1REL1 T01REL0
This register is used to write the Timer 1 Counter
value (MSB).
Bit 7-0: T1REL7-0 PWM/Timer 1 Reload LSB
Note: this register is latched after writing the LSB
part (PWM1_COUNT_OUT_L: see below). For this
reason, this register must be written before the
LSB.
This register is used to write the Timer 1 Reload
value (LSB).
PWM/Timer 1 Counter Low Output Register
(PWM1_COUNT_OUT_L)
Output Register 12 (0Ch) Write only
Reset Value: 0000 0000 (00h)
Note:
by
writing
this
register,
the
PWM1_RELOAD_x couple is latched in the
internal registers of the peripherals. For this
reason, this register should be written after the
MSB one.
7
0
T1CO7 T1CO6 T1CO5 T1CO4 T1CO3 T1CO2 T1CO1 T1CO0
Bit 7-0: T1CO7-0 PWM/Timer 0 Counter MSB
This register is used to write the Timer 1 Counter
value (LSB).
Note:
by
writing
this
register,
the
PWM1_COUNT_OUT_x couple is latched in the
internal registers of the peripherals. For this reason
this register should be written after the MSB one.
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2
2
12 I C BUS INTERFACE (I C)
12.3 General Description
In addition to receiving and transmitting data, this
interface converts it from serial to parallel format
and vice versa, using either an interrupt or polled
handshake. The interrupts are enabled or disabled
via software. The interface is connected to the I C
bus by a data pin (SDA) and by a clock pin (SCL).
12.1 Introduction
The I C Bus Interface serves as an interface
2
2
between the microcontroller and the serial I C bus,
2
providing bothmultimaster and slave functions and
2
controls all I C bus-specific sequencing, protocol,
2
arbitration and timing. The
I Bus Interface
The interface can be connected both with a
2
2
2
supports fast I C mode (400kHz).
standard I C bus and a Fast I C bus. This
selection is made via software.
12.2 Main Features
2
■ Parallel-bus/I C protocol converter
12.3.1 Mode Selection.
■ Multi-master capability
The interface can operate in the following four
modes:
■ 7-bit/10-bit Addressing
– Slave transmitter/receiver
– Master transmitter/receiver
By default, it operates in slave mode.
■ Transmitter/Receiver flag
■ End-of-byte transmission flag
■ Transfer problem detection
The interface automatically switches from slave to
master after it generates a START condition and
from master to slave in case of arbitration loss or a
2
I C Master Features:
■ Clock generation
STOP
generation,
providing
Multi-Master
2
capability.
■ I C bus busy flag
■ Arbitration Lost Flag
12.3.2 Communication Flow.
■ End of byte transmission flag
■ Transmitter/Receiver Flag
■ Start bit detection flag
In Master mode, Communication Flow initiates
data transfer and generates the clock signal. A
serial data transfer always begins with a start
condition and ends with a stop condition. Both start
and stop conditions are generated in master mode
by software.
■ Start and Stop generation
2
I C Slave Features:
In Slave mode the interface is capable of
recognizing its own address (7 or 10-bit) and the
General Call address. The General Call address
detection may be enabled or disabled by software.
■ Stop bit detection
2
■ I C bus busy flag
■ Detection of misplaced start or stop condition
Data and addresses are transferred as 8-bit bytes,
(MSB first). The first byte(s) follow the start
condition is the address (one in 7-bit mode, two in
10-bit mode), which is always transmitted in
Master mode.A 9th clock pulse follows the 8 clock
cycles of a byte transfer, during which the receiver
must send an acknowledge bit to the transmitter.
Refer to Figure 12.1.
2
■ Programmable I C Address detection
■ Transfer problem detection
■ End-of-byte transmission flag
■ Transmitter/Receiver flag
2
Figure 12.1 I C BUS Protocol
SDA
MSB
ACK
SCL
1
2
8
9
START
STOP
CONDITION
CONDITION
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Acknowledge may be enabled and disabled via
software.
When the I2C cell is enabled, the SDA and SCL
pins must be configured as floating open-drain I/O.
2
The I C interface address and/or general call
The value of the external pull-up resistance used
depends on the application.
address can be selected via software.
2
The speed of the I C interface may be selected
2
between Standard (0-100KHz) and Fast I C (100-
12.4 Functional Description
400KHz).
2
By default the I C interface operates in Slave
mode (M/SL bit is cleared) except when it initiates
a transmit or receive sequence.
12.3.3 SDA/SCL Line Control.
First, the interface frequency must be configured
using the related bits of the Configuration
Registers.
Transmitter mode: the interface holds the clock line
low before transmission, in order to wait for the
microcontroller to write the byte in the Data
Register.
Receiver mode: the interface holds the clock line
low after reception to wait for the microcontroller to
read the byte in the Data Register.
12.4.1 Slave Mode.
As soon as a start condition is detected, the
address is received from the SDA line and sent to
the shift register; then it is compared with the
address of the interface or the General Call
address (if selected by software).
SCL frequency is controlled by a programmable
2
clock divider which depends on the I C bus mode.
2
Figure 12.2 I C Interface Block Diagram
DATA REGISTER
SDA
DATA CONTROL
SDA
DATA SHIFT REGISTER
COMPARATOR
OWN ADDRESS REGISTER (OAR)
SCL
CLOCK CONTROL
SCL
CLOCK CONTROL REGISTER (I2C_CCR)
CONTROL REGISTER (I2C_CR)
STATUS REGISTER 1 (I2C_SR1)
STATUS REGISTER 2 (I2C_SR2)
CONTROL LOGIC
INTERRUPT
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Note: In 10-bit addressing mode, the comparison
includes the header sequence (11110xx0) and the
two most significant bits of the address.
Closing slave communication
After the last data byte is transferred a Stop
Condition is generated by the master. The
interface detects this condition and sets:
– EVF and STOPF bits with an interrupt if the ITE
bit is set.
Header matched (10-bit mode only): the interface
generates an acknowledgement pulse if the ACK
bit is set.
Afterwards, the interface waits for a read of the
I2C_SR2 register (see Figure 12.3 Transfer
sequencing EV4).
Address not matched: the interface ignores it and
waits for another Start condition.
Address matched: the interface generates in
sequence:
Error Cases
– Acknowledge pulse if the ACK bit is set.
– BERR: Detection of a Stop or a Start condition
during a byte transfer. In this case, the EVF and
the BERR bits are set with an interrupt if the ITE
bit is set.
If it is a Stop then the interface discards the data,
released the lines and waits for another Start
condition.
– EVF and ADSL bits are set with an interrupt if the
ITE bit is set.
Afterwards, the interface waits for the I2C_SR1
register to be read, holding the SCL line low (see
Figure 12.3 Transfer sequencing EV1).
Next, in 7-bit mode read the I2C_IN register to
determine from the least significant bit (Data
Direction Bit) if the slave must enter Receiver or
Transmitter mode.
If it is a Start then the interface discards the data
and waits for the next slave address on the bus.
– AF: Detection of a non-acknowledge bit. In this
case, the EVF and AF bits are set with an inter-
rupt if the ITE bit is set.
In 10-bit mode, after receiving the address
sequence the slave is always in receive mode. It
will enter transmit mode on receiving a repeated
Start condition followed by the header sequence
with matching address bits and the least significant
bit set (11110xx1).
Note: In both cases, the SCL line is not held low;
however, SDA line can remain low due to possible
«0» bits transmitted last. At this point, both lines
must be released by software.
Slave Receiver
Following reception of the address and after the
I2C_SR1 register has been read, the slave
receives bytes from the SDA line into the I2C_IN
register via the internal shift register. After each
byte, the interface generates the following in
sequence:
How to release the SDA / SCL lines
Set and subsequently clear the STOP bit while
BTF is set. The SDA/SCL lines are released after
the current byte is transferred.
– Acknowledge pulse if the ACK bit is set
– EVF and BTF bits are set with an interrupt if the
ITE bit is set.
Afterwards, the interface waits for the I2C_SR1
register to be read followed by a read of the I2C_IN
register, holding the SCL line low (see Figure
12.3 Transfer sequencing EV2).
12.4.2 Master Mode.
To switch from default Slave mode to Master mode
a Start condition generation is needed.
Start condition
Setting the START bit while the BUSY bit is
cleared causes the interface to switch to Master
mode (M/SL bit set) and generates a Start
condition.
Once the Start condition is sent:
– The EVF and SB bits are set by hardware with
an interrupt if the ITE bit is set.
Afterwards, the master waits for a read of the
I2C_SR1 register followed by a write in the
I2C_OUT register with the Slave address, holding
the SCL line low (see Figure 12.3 Transfer
sequencing EV5).
Slave Transmitter
Following the address reception and after the
I2C_SR1 register has been read, the slave sends
bytes from the I2C_OUT register to the SDA line
via the internal shift register.
The slave waits for a read of the I2C_SR1 register
followed by a write in the I2C_OUT register,
holding the SCL line low (see Figure 12.3
Transfer sequencing EV3).
When the acknowledge pulse is received:
– The EVF and BTF bits are set by hardware with
an interrupt if the ITE bit is set.
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Slave address transmission
In order to close the communication: before
reading the last byte from the I2C_IN register, set
the STOP bit to generate the Stop condition. The
interface automatically goes back to slave mode
(M/SL bit cleared).
At this point, the slave address is sent to the SDA
line via the internal shift register.
In 7-bit addressing mode, one address byte is sent.
In 10-bit addressing mode, sending the first byte
including the header sequence causes the
following event:
– The EVF bit is set by hardware with interrupt
generation if the ITE bit is set.
Note: In order to generate the non-acknowledge
pulse after the last data byte received, the ACK bit
must be clearedjust before reading the second last
data byte.
Afterwards, the master waits for a read of the
I2C_SR1 register followed by a write in the
I2C_OUT register, holding the SCL line low (see
Figure 12.3 Transfer sequencing EV9).
Master Transmitter
Following the address transmission and after the
I2C_SR1 register has been read, the master sends
bytes from the I2C_OUT register to the SDA line
via the internal shift register.
The second address byte is sent by the interface.
After completion of this transfer (and acknowledge
from the slave if the ACK bit is set):
The master waits for a read of the I2C_SR1
register followed by a write in the I2C_OUT
register, holding the SCL line low (see Figure
12.3 Transfer sequencing EV8).
– The EVF bit is set by hardware with interrupt
generation if the ITE bit is set.
Afterwards, the master waits for a read of the
I2C_SR1 register followed by a write in the
I2C_CR register (for example set PE bit), holding
the SCL line low (see Figure 12.3 Transfer
sequencing EV6).
When the acknowledge bit is received, the
interface sets:
– EVF and BTF bits with an interrupt if the ITE bit
is set.
Next, the master must enter Receiver or
Transmitter mode.
In order to close the communication: after writing
the last byte to the I2C_OUT register, set the
STOP bit to generate the Stop condition. The
interface automatically returns to slave mode (M/
SL bit cleared).
Note: In 10-bit addressing mode, in order to switch
the master to Receiver mode, software must
generate a repeated Start condition and resend the
header sequence with the least significant bit set
(11110xx1).
Error Cases
– BERR: Detection of a Stop or a Start condition
during a byte transfer. In this case, the EVF and
BERR bits are set by hardware with an interrupt
if ITE is set.
Master Receiver
Following the address transmission and after
I2C_SR1 and I2C_CR registers have been
accessed, the master receives bytes from the SDA
line into the I2C_IN register via the internal shift
register. After each byte the interface generates in
sequence:
– Acknowledge pulse if the ACK bit is set
– EVFand BTF bits are set by hardware with an in-
terrupt if the ITE bit is set.
– AF: Detection of a non-acknowledge bit. In this
case, the EVF and AF bits are set by hardware
with an interrupt if the ITE bit is set. To resume,
set the START or STOP bit.
– ARLO: Detection of an arbitration lost condition.
In this case the ARLO bit is set by hardware
(with an interrupt if the ITE bit is set and the in-
terface automatically goes back to slave mode
(the M/SL bit is cleared).
Afterwards, the interface waits for a read of the
I2C_SR1 register followed by a read of the I2C_IN
register, holding the SCL line low (see Figure
12.3 Transfer sequencing EV7).
Note: In all these cases, the SCL line is not held
low; however, the SDA line can remain low due to
possible «0» bits transmitted last. Both lines must
be released via software.
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Figure 12.3 Tranfer Sequencing
7-bit Slave receiver:
S
Address
A
Data1
A
Data1
Data1
Data2
EV3
A
Data2
Data2
DataN
A
P
.....
EV1
EV2
A
EV2
A
EV2
NA
EV4
7-bit Slave transmitter:
S
Address
A
DataN
P
.....
.....
EV1 EV3
EV3
EV3-1
EV4
7-bit Master receiver:
S
Address
A
A
A
DataN NA
P
EV5
EV6
EV7
A
EV7
A
EV7
A
7-bit Master transmitter:
S
Address
A
Data1
Data1
Data2
DataN
P
.....
EV5
EV6 EV8
EV8
EV8
EV8
10-bit Slave receiver:
S
Header
A
Address
A
A
DataN
A
P
.....
A
EV1
A
EV2
EV2
EV4
10-bit Slave transmitter:
S
Header
Data1
DataN
A
P
r
.....
EV1 EV3
EV3
A
EV3-1
A
EV4
P
10-bit Master transmitter:
S
Header
A
Address
A
Data1
DataN
DataN
.....
EV5
EV9
EV6 EV8
EV8
EV8
10-bit Master receiver:
S
Header
A
Data1
A
A
P
r
.....
EV5
EV6
EV7
EV7
Legend:
S=Start, P=Stop, A=Acknowledge, NA=Non-acknowledge
EVx=Event (with interrupt if ITE=1)
EV1: EVF=1, ADSL=1, cleared by reading I2C_SR1 register.
EV2: EVF=1, BTF=1, cleared by reading I2C_SR1 register followed by reading I2C_IN register.
EV3: EVF=1, BTF=1, cleared by reading I2C_SR1 register followed by writing I2C_OUT register.
EV3-1: EVF=1, AF=1, BTF=1; AF is cleared by reading I2C_SR1. BTF is cleared by releasing
the lines (STOP=1, STOP=0) or by writing I2C_OUT register (I2C_OUT=FFh). Note: If lines are
released by STOP=1, STOP=0, the subsequent EV4 is not seen.
EV4: EVF=1, STOPF=1, cleared by reading I2C_SR2 register.
EV5: EVF=1, SB=1, cleared by reading I2C_SR1 register followed by writing I2C_OUT register.
EV6: EVF=1, cleared by reading I2C_SR1 register followed by writing I2C_CR (for example PE=1
EV7: EVF=1, BTF=1, cleared by reading I2C_SR1 register followed by reading I2C_IIN register.
EV8: EVF=1, BTF=1, cleared by reading I2C_SR1 register followed by writing I2C_OUT register.
EV9: EVF=1, ADD10=1, cleared by reading I2C_SR1 register followed by writing I2C_OUT registe
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Figure 12.4 Event Flags and Interrupt Generation
ITE
ADD10
BTF
ADSL
SB
INTERRUPT
EVF
AF
STOPF
ARLO
BERR
*
* EVF can also be set by EV6 or an error from the I2C_SR2 register.
Enable
Control
Bit
Exit
from
Wait
Exit
from
Halt
Event
Flag
Interrupt Event
10-bit Address Sent Event (Master Mode)
End of Byte Transfer Event
ADD10
BTF
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
No
Address Matched Event (Slave Mode)
Start Bit Generation Event (Master Mode)
Acknowledge Failure Event
ADSEL
SB
ITE
AF
Stop Detection Event (Slave Mode)
Arbitration Lost Event (Multimaster configuration)
Bus Error Event
STOPF
ARLO
BERR
2
Note: The I C interrupt events are connected to
the same interrupt vector. They generate an
interrupt if the corresponding Enable Control Bit
(ITE) is set and the Interrupt Mask bit (MSKI2C) in
the INT_MASK Configuration Register is
unmasked (set to 1, see Interrupts Chapter).
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12.5 Register Description
– In Slave Mode
In the following sections describe the registers
used by the I C Interface are described.
0: No Start generation
1: Start generation when the bus is free
2
2
12.5.1 I C Interface Configuration Registers.
Bit 2: ACK Acknowledge enable
This bit is set and cleared by software. It is
also cleared by hardware when the interface
is disabled (PE=0).
2
I C Control Register (I2C_CR)
Configuration Register 16 (010h) Read/Write
Reset Value: 0000 0000 (00h)
0: No acknowledge returned
1: Acknowledge returned after an address
byte or a data byte is received
7
0
-
-
PE
ENGC START
ACK
STOP
ITE
Bit 1: STOP Reset signal mode
This bit is set and cleared by software. It is
also cleared by hardware in master mode.
Note: This bit is not cleared when the
interface is disabled (PE=0).
Bit 7-6: Not Used
Bit 5: PE Peripheral Enable.
This bit is set and cleared by software
0: peripheral disabled
– In Master Mode
0: No Stop generation
1: peripheral enabled
1: Stop generation after the current byte
transfer or after the current Start condition
is sent. The STOP bit is cleared by
hardware when the Stop condition is sent.
Notes:
– When PE=0, all the bits of the I2C_CR register
and the SR register except the Stop bit are reset.
All outputs are released while PE=0
– In Slave Mode
– When PE=1, the corresponding I/O pins are se-
lected by hardware as alternate functions.
0: No Start generation
2
1: Release the SCL and SDA lines after the
current byte transfer (BTF=1). In this
mode the STOP bit has to be cleared by
software.
– To enable the I C interface, write the I2C_CR
register TWICE with PE=1 as the first write only
activates the interface (only PE is set).
Bit 4: ENGC Enable General Call
Bit 0: ITE Interrupt Enable
0: Interrupt disabled
1: Interrupt enabled
This bit is set and cleared by software. It is
also cleared by hardware when the interface
is disabled (PE=0).
0: General Call disabled
1: General Call enabled
Note: The 00h General Call address is
acknowledged (01h ignored).
2
I C Clock Control Register (I2C_CCR)
Configuration Register 17 (011h) Read/Write
Reset Value: 0000 0000 (00h)
Bit 3: START Generation of a Start Condition
This bit is set and cleared by software. It is
also cleared by hardware when the interface
is disabled (PE=0) or when the Start
condition is sent (with interrupt generation if
ITE=1).
7
0
FM/SM
CC6
CC5
CC4
CC3
CC2
CC1
CC0
2
Bit 7: FM/SM Fast/Standard I C Mode.
– In Master Mode
This bit is set and cleared by software. It is
not cleared when the interface is disabled
(PE=0).
0: No Start generation
1: Repeated Start generation
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2
2
0: Standard I C Mode
I C Own Address Register 2 (I2C_OAR2)
2
1: Fast I C Mode
Configuration Register 19 (013h) Read/Write
Reset Value: 0000 0000 (00h)
Bit 6-0: CC6-CC0 7-bit clock divider
7
2
0
-
These bits select the speed of the bus (F
)
SCL
2
depending on the I C mode. They are not
cleared when the interface is disabled
(PE=0).
-
-
-
-
-
ADD9
ADD8
Bit 7-3: Not Used
bit 7-1: ADD8-ADD8 Interface address.
– Standard mode (FM/SM=0): F
<= 100kHz
SCL
F
SCL
= f
/(3x([CC6..CC0]+9))
CPU
2
These are the most significant bits of th I C
bus address of the interface (10-bit mode
only). They are not cleared when the
interface is disabled (PE=0).
– Fast mode (FM/SM=1): F
> 100kHz
SCL
F
= f
/(2x([CC6..CC0]+7))
SCL
CPU
Warning: For safety reason, CC6-CC0 bits must
be configured with a value >= 3 for the Standard
mode and >=2 for the Fast mode.
Bit 0: Reserved
2
12.5.2 I C Interface Input Registers.
2
I C Own Address Register 1 (I2C_OAR1)
Configuration Register 18 (012h) Read/Write
Reset Value: 0000 0000 (00h)
2
I C Data Input Register (I2C_IN)
Input Register 6 (06h) Read only
Reset Value: 0000 0000 (00h)
7
0
7
0
ADD7
ADD6
ADD5
ADD4
ADD3
ADD2
ADD1
ADD0
I2CDI7 I2CDI6 I2CDI5 I2CDI4 I2CDI3 I2CDI2 I2CDI1 I2CDI0
7-bit Addressing Mode
bit 7-1: ADD7-ADD1 Interface address.
bit 7-0: I2CDI7-I2CDI0 Received data.
2
These bits define the I C bus address of the
interface. They are not cleared when the
interface is disabled (PE=0).
These bits contain the byte to be received from the
bus in Receiver mode: the first data byte is
received automatically in the I2C_IN register using
the least significant bit of the address.
Bit 0: ADD0 Address direction bit.
This bit is “don’t care”, the interface
acknowledges either 0 or 1. It is not cleared
when the interface is disabled (PE=0).
Then, the next data bytes are received one by one
after reading the I2C_IN register.
Note: Address 01h is always ignored.
2
I C Status Register 1 (I2C_SR1)
Input Register 7 (07h) Read only
Reset Value: 0000 0000 (00h)
10-bit Addressing Mode
bit 7-0: ADD7-ADD0 Interface address.
2
These are the least significant bits of the I C
bus address of the interface. They are not
cleared when the interface is disabled
(PE=0).
7
0
EVF
ADD10
TRA
BUSY
BTF
ADSL
M/SL
SB
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Bit 7: EVF Event Flag
This bit is set by hardware as soon as an
0: No communication on the bus
1: Communication ongoing on the bus
event occurs. It is cleared by software
reading I2C_SR2 register in case of error
event or as described in Figure 12.3. It is also
cleared by hardware when the interface is
disabled (PE=0).
0: No event
1: One of the following events has occurred:
– BTF=1 (Byte received or transmitted)
Bit 3: BTF Byte transfer finished
This bit is set by hardware as soon as a byte
is correctly received or transmitted with
interrupt generation if ITE=1. It is cleared by
software reading I2C_SR1 register followed
by a read of I2C_IN or write of I2C_OUT
registers. It is also cleared by hardware when
the interface is disabled (PE=0).
– ADSL=1 (Address matched in Slave
mode while ACK=1)
–
Following a byte transmission, this bit is
set after reception of the acknowledge
clock pulse. In case an address byte is
sent, this bit is set only after the EV6
event (see Figure 12.3). BTF is cleared
by reading I2C_SR1 register followed by
writing the next byte in I2C_OUT register.
– SB=1 (Start condition generated in Mas-
ter mode)
– AF=1 (No acknowledge received after
byte transmission)
– STOPF=1 (Stop condition detected in
Slave mode)
– ARLO=1 (Arbitration lost in Master
mode)
–
Following a byte reception, this bit is set
after transmission of the acknowledge
clock pulse if ACK=1. BTF is cleared by
reading I2C_SR1 register followed by
reading the byte from I2C_IN register.
– BERR=1 (Bus error, misplaced Start or
Stop condition detected)
The SCL line is held low while BTF=1.
0: Byte transfer not done
– Address byte successfully transmitted in
Master mode.
1: Byte transfer succeeded
Bit 6: ADD10 10 bit addressing in Master Mode
This bit is set by hardware when the master
has sent the first byte in 10-bit address mode.
It is cleared by software reading I2C_SR2
register followed by a write in the I2C_OUT
register of the second address byte. It is also
cleared by hardware when the peripheral is
disabled (PE=0).
Bit 2: ADSL Address matched (Slave Mode)
This bit is set by hardware as soon as the
slave address received matched with the
OAR register content or a general call is
recognized. An interrupt is generated if
ITE=1. It is cleared by software reading
I2C_SR1 register or by hardware when the
interface is disabled (PE=0).
The SCL line is held low while ADSL=1.
0: Address mismatched or not received
1: Received address matched
0: No ADD10 event occurred
1: The Master has sent the first address byte
Bit 5: TRA Transmitter/Receiver
When BTF is set, TRA=1 if a data byte has
been transmitted. It is cleared automatically
when BTF is cleared. It is also cleared by
hardware after detection of Stop condition
(STOPF=1), lossof bus arbitration (ARLO=1)
or when the interface is disabled (PE=0).
Bit 1: M/SL Master/Slave
This bit is set by hardware as soon as the
interface is in Master mode (writing
START=1). It is cleared by hardware after
detecting a Stop condition on the bus or a
loss of arbitration (ARLO=1). It is also
cleared when the interface is disabled
(PE=0).
0: Data byte received (if BTF=1)
1: Data byte transmitted
Bit 4: BUSY Bus busy
0: Slave mode
1: Master mode
This bit is set by hardware on detection of a
Start condition and cleared by hardware on
detection of a Stop condition. It indicates a
communication in progress on the bus. This
information is still updated when the interface
is disabled (PE=0).
Bit 0: SB Start bit (Master Mode)
This bit is set by hardware as soon as the
Start condition is generated (following a write
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START=1). An interrupt is generated if
ITE=1. It is cleared by software reading
I2C_SR1 register followed by writing the
address byte in I2C_OUT register. It is also
cleared by hardware when the interface is
disabled (PE=0).
The SCL line is not held low while ARLO=1.
0: No arbitration lost detected
1: Arbitration lost detected
Bit 1: BERR Bus error.
0: No Start condition
1: Start condition generated
This bit is set by hardware when the interface
detects a misplaced Start or Stop condition.
An interrupt is generated if ITE=1. It is
cleared by software reading I2C_SR2
register or by hardware when the interface is
disabled (PE=0).
2
I C Status Register 2 (I2C_SR2)
The SCL line is not held low while BERR=1.
0: No misplaced Start or Stop condition
1: Misplaced Start or Stop condition
Input Register 8 (08h) Read only
Reset Value: 0000 0000 (00h)
7
0
Bit 0: GCAL General Call (Slave mode).
This bit is set by hardware when a general
call address is detected on the bus while
ENGC=1. It is cleared by hardware detecting
a Stop condition (STOPF=1) or when the
interface is disabled (PE=0).
0: No general call address detected on bus
1: general call address detected on bus
-
-
-
AF
STOPF ARLO
BERR
GCAL
Bit 7-5: Reserved.
Bit 4: AF Acknowledge failure.
This bit is set by hardware when an
acknowledge is returned. An interrupt is
generated if ITE=1. It is cleared by software
reading the I2C_SR2 register or by hardware
when the interface is disabled (PE=0).
The SCL line is not held low while AF=1.
0: No acknowledge failure
2
12.5.3 I C Interface Output Registers.
2
I C Data Output Register (I2C_OUT)
1: Acknowledge failure
Output Register 6 (06h) Read only
Reset Value: 0000 0000 (00h)
Bit 3: STOPF Stop detection (Slave mode).
7
0
This bit is set by hardware when a Stop
condition is detected on the bus after an
acknowledge (if ACK=1). An interrupt is
generated if ITE=1. It is cleared by software
reading I2C_SR2 register or by hardware
when the interface is disabled (PE=0).
I2CDO7 I2CDO6 I2CDO5 I2CDO4 I2CDO3 I2CDO2 I2CDO1 I2CDO0
bit 7-0: I2CDO7-I2CDO0 Data to be transmitted.
The SCL line is not held low while STOPF=1.
0: No Stop condition detected
These bits contain the byte to be transmitted in the
bus in Transmitter mode: Byte transmission start
automatically when the software writes in the
I2C_OUT register.
1: Stop condition detected
Bit 2: ARLO Arbitration lost.
This bit is set by hardware when the interface
loses the arbitration of the bus to another
master. An interrupt is generated if ITE=1. It
is cleared by software reading I2C_SR2
register or by hardware when the interface is
disabled (PE=0).
After an ARLO event the interface switches
back automatically to Slave mode (M/SL=0).
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13 SERIAL PERIPHERAL INTERFACE (SPI)
13.1 Introduction
A basic example of interconnections between a
single master and a single slave is illustrated in
Figure 13.1
The Serial Peripheral Interface (SPI) allows full-
duplex, synchronous, serial communication with
external devices. An SPI system may consist of a
master, one or more slaves, or a system, in which
devices may be either masters or slaves.
SPI is normally used for communication between
the ICU and external peripherals or another ICU.
The MOSI pins are connected together as the
MISO pins. In this manner, data is transferred
serially between master and slave (most significant
bit first).
When the master device transmits data to a slave
device via the MOSI pin, the slave device responds
by sending data to the master device via the MISO
pin. This implies full duplex transmission with both
data out and data in synchronized with the same
clock signal (which is provided by the master
device via the SCK pin).
The transmitted byte is replaced by the byte
received and eliminates the need for separate
transmit-empty and receiver-full bits. A status flag
is used to indicate that the I/O operation is
complete.
Four possible data/clock timing relationships may
be chosen (see Figure 13.4), but master and slave
must be programmed with the same timing mode.
Refer to the Pin Description section in this
datasheet for the device-specific pin-out.
13.2 Main Features
■ Full duplex, three-wire synchronous transfers
■ Master or slave operation
■ Four master mode frequencies
■ Maximum slave mode frequency = CKM/4.
■ Four programmable master bit rates
■ Programmable clock polarity and phase
■ End of transfer interrupt flag
13.4 Functional Description
■ Write collision flag protection
Figure 13.2 shows the serial peripheral interface
(SPI) block diagram.
■ Master mode fault protection capability.
This interface contains 3 dedicated registers:
– A Control Register (SPI_CR)
13.3 General description
– A Status Register (SPI_STATUS_CR)
– A Data Register for transmission (SPI_OUT)
– A Data Register for reception (SPI_OUT)
SPI is connected to external devices through 4
alternate pins:
– MISO: Master In / Slave Out pin
– MOSI: Master Out / Slave In pin
– SCK: Serial Clock pin
13.4.1 Master Configuration.
– SS: Slave select pin (if not done through soft-
ware)
In a master configuration, the serial clock is
generated on the SCK pin.
Figure 13.1 SPI Master Slave
SLAVE
MASTER
MSBit
LSBit
MSBit
LSBit
MISO
MOSI
MISO
MOSI
8-BIT SHIFT REGISTER
8-BIT SHIFT REGISTER
SPI
CLOCK
GENERATOR
SCK
SS
SCK
SS
+5V
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Figure 13.2 Serial Peripheral Interface Block Diagram
Internal Bus
Read
IT
Read Buffer
request
SPI_IN
MOSI
SPI_STATUS_CR
MISO
8-Bit Shift Register
SPI_OUT
SPIF WCOL OR MODF
SOD SSM SSI
-
Write
SPI
STATE
CONTROL
SCK
SS
SPI_CR
MSTR
CPHA SPR1 SPR0
SPIE SPE SPR2
CPOL
MASTER
CONTROL
SERIAL
CLOCK
GENERATOR
Procedure
The data byte is loaded in parallel into the 8-bit shift
register (from the internal bus) during a write cycle
and then shifted out serially to the MOSI pin most
significant bit first.
– Select the SPR0, SPR1 and SPR2 bits to define
the serial clock baud rate (see SPI_CR register).
– Select the CPOL and CPHA bits to define one of
the four relationships between the data transfer
and the serial clock (see Figure 13.4).
When data transfer is complete:
– The SPIF bit is set by hardware
– The SS pin must be connected to a high level
signal during the complete byte transmit se-
quence.
– An interrupt is generated if the SPIE bit is set.
During the last clock cycle the SPIF bit is set, a
copy of the data byte received in the shift register
is moved to a buffer. When the SPI_IN register is
read, the SPI peripheral returns this buffered
value. Clearing the SPIF bit is performed by the
following software sequence:
– The MSTR and SPE bits must be set (they re-
main set only if the SS pin is connected to a high
level signal).
In this configuration the MOSI pin is a data output
and to the MISO pin is a data input.
1. An access to the SPI_STATUS_CR register
while the SPIF bit is set
2. A read to the SPI_IN register.
Transmit sequence
Transmit sequence begins when a byte is written in
the SPI_OUT register.
Note: While the SPIF bit is set, all writes to the
SPI_OUT register are inhibited until the
SPI_STATUS_CR register is read.
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13.4.2 Slave Configuration.
(shifted in serially). The serial clock is used to
synchronize data transfer during a sequence of
eight clock pulses.
In slave configuration, the serial clock is received
on the SCK pin from the master device.
The SS pin allows individual selection of a slave
device; the other slave devices that are not
selected do not interfere with SPI transfer.
The value of the SPR0, SPR1 and SPR2 bits is not
used for data transfer.
Procedure
Clock Phase and Clock Polarity
Four possible timing relationships may be chosen
by software, using the CPOL and CPHA bits.
– For correct data transfer, the slave device must
be in the same timing mode as the master de-
vice (CPOL and CPHA bits). See Figure 13.4.
The CPOL (clock polarity) bit controls the steady
state value of the clock when data isn’t being
transferred. This bit affects both master and slave
modes.
The combination between the CPOL and CPHA
(clock phase) bits select the data capture clock
edge.
– The SS pin must be connected to a low level sig-
nal during the complete byte transmit sequence.
– Clear the MSTR bit and set the SPE bit to assign
the pins to alternate function.
In this configuration the MOSI pin is a data input
and the MISO pin is a data output.
Figure 13.4, shows an SPI transfer with the four
combinations of the CPHA and CPOL bits. The
diagram may be interpreted as a master or slave
timing diagram where the SCK pin, the MISO pin,
the MOSI pin are directly connected between the
master and the slave device.
Transmit Sequence
The data byte is loaded into the 8-bit shift register
(from the internal bus) during a write cycle and
then shifted out serially to the MISO pin most
significant bit first.
The SS pin is the slave device select input and can
be driven by the master device.
The master device applies data to its MOSI pin-
clock edge before the capture clock edge.
The transmit sequence begins when the slave
device receives the clock signal and the most
significant bit of the data on its MOSI pin.
When data transfer is complete:
– The SPIF bit is set by hardware
– An interrupt is generated if SPIE bit is set.
CPHA bit is set
The second edge on the SCK pin (falling edge if
the CPOL bit is reset, rising edge if the CPOL bit is
set) is the MSBit capture strobe. Data is latched on
the occurrence of the second clock transition.
During the last clock cycle the SPIF bit is set, a
copy of the data byte received in the shift register
is moved to a buffer. When the SPI_IN register is
read, the SPI peripheral returns the buffer value.
A write collision should not occur even if the SS pin
stays low during a transfer of several bytes (see
Figure 13.3).
The SPIF bit is cleared by the following software
sequence:
1. An access to the SPI_STATUS_CR register
while the SPIF bit is set.
CPHA bit is reset
2. A read to the SPI_IN register.
The first edge on the SCK pin (falling edge if CPOL
bit is set, rising edge if CPOL bit is reset) is the
MSBit capture strobe. Data is latched on the
occurrence of the first clock transition.
Note: While the SPIF bit is set, all writes to the
SPI_OUT register are inhibited until the
SPI_STATUS_CR register is read.
The SPIF bit can be cleared during a second
transmission; however, it must be cleared before
the second SPIF bit in order to prevent an overrun
condition (see Section 13.4.6).
The SS pin must be toggled high and low between
each byte transmitted (see Figure 13.3).
In order to protect the transmission from a write
collision a low value on the SS pin of a slave device
freezes the data in its SPI_OUT register and does
not allow it to be altered. Therefore, the SS pin
must be high to write a new data byte in the
SPI_OUT without producing a write collision.
Depending on the CPHA bit, the SS pin has to be
set to write to the SPI_OUT register between each
data byte transfer to avoid a write collision (see
Section 13.4.4).
13.4.3 Data Transfer Format.
13.4.4 Write Collision Error.
During an SPI transfer, data is simultaneously
transmitted (shifted out serially) and received
A write collision occurs when the software tries to
write to the SPI_OUT register while a data transfer
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is taking place with an external device. When this
occurs, the transfer continues uninterrupted; and
the software writing will be unsuccessful.
WCOL bit
The WCOL bit in the SPI_STATUS_CR register is
set if a write collision occurs.
Write collisions can occur both in master and slave
mode.
No SPI interrupt is generated when the WCOL bit
is set (the WCOL bit is a status flag only).
The WCOL bit is cleared by a software sequence
(see Section 13.5).
Note: a “read collision” will never occur since the
data byte received is placed in a buffer, in which
access is always synchronous with the ICU
operation.
13.4.5 Master Mode Fault.
Master mode fault occurs when the master device
has its SS pin pulled low, then the MODF bit is set.
In Slave mode
When the CPHA bit is set:
Master mode fault affects the SPI peripheral in the
following ways:
– The MODF bit is set and an SPI interrupt is
generated if the SPIE bit is set.
– The SPE bit is reset. This blocks all output from
the device and disables the SPI peripheral.
The slave device will receive a clock (SCK) edge
prior to the latch of the first data transfer. This first
clock edge will freeze the data in the slave device
SPI_OUT register and output the MSBit on to the
external MISO pin of the slave device.
The SS pin low state enables the slave device, but
the output of the MSBit onto the MISO pin does not
take place until the first data transfer clock edge
occurs.
– The MSTR bit is reset, forcing the device into
slave mode.
Clearing the MODF bit is done through a software
sequence:
When the CPHA bit is reset:
1. A read or write access to the SPI_STATUS_CR
register while the MODF bit is set.
2. A write to the SPI_CR register.
Data is latched on the occurrence of the first clock
transition. The slave device doesn’t have a way of
knowing when that transition will occur; therefore,
the slave device collision occurs when software
attempts to write the SPI_OUT register after its SS
pin has been pulled low.
For this reason, the SS pin must be high, between
each data byte transfer, in order to allow the CPU
to write in the SPI_OUT register without generating
a write collision.
Note: To avoid any multiple slave conflicts in the
case of a system comprising several MCUs, the
SS pin must be pulled high during the clearing
sequence of the MODF bit. The SPE and MSTR
bits may be restored to their original state during or
after this clearing sequence.
Hardware does not allow the user to set the SPE
and MSTR bits, while the MODF bit is set (except
in the MODF bit clearing sequence).
In Master mode
In a slave device the MODF bit can’t be set, but in
a multi master configuration the device can be in
slave mode with this MODF bit set.
Collision in the master device is defined as a write
of the SPI_OUT register, while the internal serial
clock (SCK) is in the process of transfer.
The MODF bit indicates that there might have been
a multi-master conflict for system control and
allows a proper exit from system operation to a
reset or default system state using an interrupt
routine.
The SS pin signal must always be high on the
master device.
Figure 13.3 CHPA/SS Timing Diagram
Byte 3
MOSI/MISO
Master SS
Byte 1
Byte 2
Slave SS
(CPHA=0)
Slave SS
(CPHA=1)
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Figure 13.4 Data Clock Timing Diagram
CPHA =1
CPOL = 1
CPOL = 0
Bit 4
Bit 4
Bit3
Bit 2
Bit 2
Bit 1
Bit 1
LSBit
LSBit
MSBit Bit 6
Bit 5
Bit 5
MISO
(from master)
Bit3
MSBit
Bit 6
MOSI
(from slave)
SS
(to slave)
CAPTURE STROBE
CPHA =0
CPOL = 1
CPOL = 0
Bit 4
Bit 4
Bit3
Bit 2
Bit 2
Bit 1
Bit 1
LSBit
LSBit
MISO
(from master)
MSBit
Bit 6
Bit 6
Bit 5
Bit 5
Bit3
MOSI
(from slave)
MSBit
SS
(to slave)
CAPTURE STROBE
Note: This figure should not be used as a replacement for parametric information.
Refer to the Electrical Characteristics chapter.
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Figure 13.5 Clearing the WCOL bit (Write Collision Flag) Software Sequence
Clearing sequence after SPIF = 1 (end of a data byte transfer)
Read SPI_STATUS_CR
Read SPI_STATUS_CR
1st Step
2nd Step
OR
THEN
THEN
SPIF =0
SPIF =0
Read SPI_IN
WCOL=0 if no transfer has started
WCOL=1 if a transfer has started
before the 2nd step
Write SPI_IN
WCOL=0
Clearing sequence before SPIF = 1 (during a data byte transfer)
Read SPI_STATUS_CR
1st Step
THEN
Note: Writing in SPI_OUT regis-
2nd Step
Read SPI_IN
ter instead of reading in SPI_IN
do not reset WCOL bit
WCOL=0
13.4.6 Overrun Condition.
The SS pins are pulled high during reset since the
master device ports will be forced to be inputs at
that time, thus disabling the slave devices.
An overrun condition occurs when the master
device has sent several data bytes and the slave
device hasn’t cleared the SPIF bit issued from the
previous data byte transmitted.
Note: In order to prevent a bus conflict on the
MISO line the master allows only one active slave
device during a transmission.
In this case, the receiver buffer contains the byte
sent after the SPIF bit was last cleared. A read to
the SPI_IN register returns this byte. All other
bytes are lost.
For more security, the slave device may respond to
the master with the data byte received. Then the
master will receive the previous byte back from the
slave device if all MISO and MOSI pins are
connected and the slave has not written its
SPI_OUT register.
This condition is not detected by the SPI
peripheral.
13.4.7 Single Master and Multimaster Configu-
rations.
Other transmission security methods can use ports
for handshake lines or data bytes with command
fields.
There are two types of SPI systems:
– Single Master System
– Multimaster System
Multi-master System
A multi-master system may also be configured by
the user. Transfer of master control could be
implemented using a handshake method through
the I/O ports or by an exchange of code messages
through the serial peripheral interface system.
Single Master System
A typical single master system may be configured,
using an ICU as the master and four ICUs as
slaves (see Figure 13.6).
The master device selects the individual slave
devices by using four pins of a parallel port to
control the four SS pins of the slave devices.
The multi-master system is principally handled by
the MSTR bit in the SPI_CR register and the
MODF bit in the SPI_STATUS_CR register.
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Figure 13.6 Single Master Configuration
SS
SS
SS
SS
SCK
SCK
SCK
Slave
SCK
Slave
MCU
Slave
MCU
Slave
MCU
MCU
MOSI MISO
MOSI MISO
MOSI MISO
MOSI MISO
MOSI MISO
SCK
Master
MCU
5V
SS
13.4.8 Interrupts
Enable
Control
Bit
Exit
from
Wait
Exit
from
Halt
Event
Flag
Interrupt Event
SPI End of Transfer Event
Master Mode Fault Event
SPIF
Yes
Yes
No
No
SPIE
MODF
Note: The SPI interrupt events are connected to
the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding
Enable Control Bit (SPIE) and the interrupt mask
bit (MSKSPI) in the INT_MASK Configuration
Register is set.
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13.5 SPI Register Description
Bit 3: CPOL Clock polarity.
In the following sections describe the registers
used by the SPI. In the 16 pin devices the SPI is
not present and the described register aren’t used
This bit is set and cleared by software. This
bit determines the steady state of the serial
Clock. The CPOL bit affects both the master
and slave modes.
0: The steady state is a low value at the SCK
pin.
13.5.1 SPI Configuration Registers.
1: The steady state is a high value at the SCK
pin.
SPI Control Register (SPI_CR)
Configuration Register 20 (014h) Read/Write
Reset Value: 0000 0000 (00h)
Note: SPI must be disabled by resetting the SPE
bit if CPOL is changed at the communication byte
boundaries.
7
0
SPIE
SPE
SPR2
MSTR
CPOL
CPHA
SPR1
SPR2
Bit 2: CPHA Clock phase.
This bit is set and cleared by software.
0: The first clock transition is the first data
capture edge.
1: The second clock transition is the first
capture edge.
Bit 7: SPIE Serial peripheral interrupt enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SPI interrupt is generated whenever
SPIF=1 or MODF=1 in SPI_STATUS_CR
Bit 1-0: SPR1-SPR0 Serial peripheral rate.
These bits are set and cleared by software.
Used with the SPR2 bit, they select one of six
baud rates to be used as the serial clock
when the device isa master(see Table 13.1).
Bit 6: SPE Serial peripheral output enable.
This bit is set and cleared by software. It is
also cleared by hardware when, in master
mode, SS=0 (see Section 13.4.5 Master
Mode Fault).
These 2 bits have no effect in slave mode.
0: I/O port connected to pins
1: SPI alternate functions connected to pins
Remark: It is recommended to write the SPI_CR
register after the SPI_STATUS_CR register.
Note: The SPE bit is cleared by reset, so the SPI
peripheral is not initially connected to the pins.
Table 13.1 Serial Peripheral Baud Rate
Serial Clock
SPR2 SPR1 SPR0
Bit 5: SPR2 Divider Enable.
f
f
f
/2
/4
/8
1
0
0
1
0
0
0
0
0
1
1
1
0
0
1
0
0
1
This bit is set and cleared by software and it
is cleared by reset. It is used with the
SPR[1:0] bits to set the baud rate. Refer to
Table 13.1.
0: Divider by 2 enabled
1: Divider by 2 disabled
CPU
CPU
CPU
f
/16
/32
/64
CPU
f
CPU
f
Note: This bit has no effect in slave mode.
CPU
Bit 4: MSTR Master/Slave mode select.
This bit is set and cleared by software. It is
also cleared by hardware when, in master
mode, SS=0 (see Section 13.4.5 Master
Mode Fault).
SPI Control-Status Register (SPI_STATUS_CR)
Configuration Register 21 (015h) Read/Write
Reset Value: 0000 0000 (00h)
0: Slave mode is selected
7
0
1: Master mode is selected, the function of
the SCK pin changes from an input to an
output and the functions of the MISO and
MOSI pins are reversed.
SPIF
WCOL
OR
MODF
-
SOD
SSM
SSI
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Bit 7: SPIF Serial Peripheral data transfer flag.
Bit 2: SOD SPI output disable
(read only)
This bit is set and cleared by software. When
set, it disables the alternate function of the
SPI output (MOSI in master mode / MISO in
slave mode)
This bit is set by hardware when a transfer
has been completed. An interrupt is
generated if SPIE=1 in the SPI_CR register.
It is cleared by a software sequence (an
access to the SPI_STATUS_CR register
followed by a read or write to the SPI_IN/
SPI_OUT registers).
0: SPI output not disable
1: SPI output disable.
Bit 1: SSM SS mode selection
0: Data transfer is in progress or has been
approved by a clearing sequence.
1: Data transfer between the device and an
external device has been completed.
This bit is set and cleared by software. When
set, it disables the alternate function of the
SPI Slave Select pin and use the SSI bit
value instead of.
Note: While the SPIF bit is set, all writes to the
SPI_OUT register are inhibited.
0: SS pin used by the SPI.
1: SS pin not used (I/O mode), SSI bit value
is used.
Bit 6: WCOL Write Collision status (read only).
This bit is set by hardware when a write to the
SPI_OUT register is done during a transmit
sequence. It is cleared by a software
sequence (see Figure 13.5).
Bit 0: SSI SS internal mode
This bit is set and cleared by software. It
replaces pin SS of the SPI when bit SSM is
set to 1. SSI bit is active low slave select
signal when SSM is set to 1.
0: No write collision occurred
1: A write collision has been detected
0 : Slave selected
1 : Slave not selected.
Bit 5: OR SPI overrun error (read only).
This bit is set by hardware when the byte
currently being received in the shift register is
ready to be transferred into the SPI_IN
register while SPIF = 1 (See Section 13.4.6
Overrun Condition). An interrupt is generated
if SPIE = 1 in SPI_CR register. It is cleared by
Remark: It is recommended to write the
SPI_STATUS_CR register before the SPI_CR
register.
a
software sequence (read of the
13.5.2 SPI Input Register.
SPI_STATUS_CR register followed by a
read in SPI_IN or write of the SPI_OUT
register).
0: No overrun error.
1: Overrun error detected.
SPI Data Input Register (SPI_IN)
Input Register 5 (05h) Read only
Reset Value: 0000 0000 (00h)
7
0
Bit 4: MODF Mode Fault flag (read only).
This bit is set by hardware when the SS pin is
pulled low in master mode (see Section
13.4.5 Master Mode Fault). An SPI interrupt
can be generated if SPIE=1 in the SPI_CR
register. This bit is cleared by a software
SPIDI7 SPIDI6 SPIDI5 SPIDI4 SPIDI3 SPIDI2 SPIDI1 SPIDI0
bit 7-0: SPIDI7-SPIDI0 Received data.
sequence
(An
access
to
the
SPI_STATUS_CR register while MODF=1
followed by a write to the SPI_CR register).
The SPI_IN register is used to receive data on the
serial bus.
0: No master mode fault detected
Note: During the last clock cycle the SPIF bit is set,
a copy of the data byte received in the shift register
is moved to a buffer. When the user reads the
serial peripheral data I/O register, the buffer is
actually being read.
1: A fault in master mode has been detected
Bit 3: Not used.
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ST52F500/F503/F504
Warning: A read to the SPI_IN register returns the
value located in the buffer and not the contents of
the shift register (see Figure 13.2).
13.5.3 SPI Output Register.
SPI Data Output Register (SPI_OUT)
Output Register 5 (05h) Read only
Reset Value: 0000 0000 (00h)
7
0
SPIDO7 SPIDO6 SPIDO5 SPIDO4 SPIDO3 SPIDO2 SPIDO1 SPIDO0
bit 7-0: SPIDO7-SPIDO0 Data to be transmitted.
The SPI_OUT register is used to transmit data on
the serial bus. In the master device only a write to
this register will initiate transmission/reception of
another byte.
Warning: A write to the SPI_OUT register places
data directly into the shift register for transmission.
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Full Product Information at http://www.st.com/five
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