ST52F503F2M6_技术文档

ST52F500/F503

67ꢀꢁ)ꢀꢂꢂꢃ)ꢀꢂꢄ

®

8-BIT INTELLIGENT CONTROLLER UNIT (ICU)

Two Timer/PWMs, I²C, SPI

0HPRULHV

I Up to 8 Kbytes Single Voltage Flash Memory

I 256 bytes of Register File

I 256 bytes of RAM

I Up to 256 bytes of Data EEPROM

I In Situ Programming in Flash devices (ISP)

I Single byte and Page modes and In Application

Programming for writing data in Flash memory

I Readout protection and flexible write protection

&RUH

I Register File based architecture

I 107 basic instructions

I Hardware multiplication and division

I Decision Processor for the implementation of

Fuzzy Logic algorithms

I Deep System and User Stacks

&ORFNꢅDQGꢅ3RZHUꢅ6XSSO\

I Up to 20 MHz clock frequency

I Programmable Oscillator modes:

– 10 MHz Internal Oscillator

– External Clock/ Oscillator

I Power-On Reset (POR)

3HULSKHUDOV

I 2 Programmable 16 bit Timer/PWMs with

internal 16-bit Prescaler featuring:

– PWM output

I Programmable Low Voltage Detector (PLVD)

– Input capture

with 3 configurable thresholds

– Output compare

I Power Saving features

– Pulse generator mode

I Watchdog timer

I I²C Peripheral with master and slave mode

,QWHUUXSWV

I 8 interrupt vectors with one SW Trap

I 3-wire SPI Peripheral supporting Single

I Non-Maskable Interrupt (NMI)

Master and Multi Master SPI modes

I Two Port Interrupts with up to 16 sources

'HYHORSPHQWꢅWRROV

I High level Software tools

,ꢃ2ꢅ3RUWV

I From 10 up to 22 I/O PINs configurable in pull-

up, push-pull, weak pull-up, open-drain and

high-impedance

I ‘C’ Compiler

I In-Circuit debugger

I Low cost Programmer

I Gang Programmer

I High current sink/source in all pins

Rev 2.4 - Jan 2005

1/123

This is preliminary information on a new product foreseen to be developed. Details are subject to change without notice.

67ꢀꢁ)ꢀꢂꢂꢃ)ꢀꢂꢄ

ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ

7$%/(ꢅ2)ꢅ

&217(176

7$%/(ꢅ2)ꢅ&217(176

ꢆꢅ*(1(5$/ꢅ'(6&5,37,21 ꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅ ꢅꢈ

1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

1.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

1.2.1 Memory Programming Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.2.2 Working Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.3 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

ꢁꢅ,17(51$/ꢅ$5&+,7(&785(ꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅ ꢅꢆꢉ

2.1 Control Unit and Data Processing Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

2.1.1 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.1.2 Flags. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.2 Arithmetic Logic Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

2.3 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

ꢄꢅ$''5(66,1*ꢅ63$&(6ꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅ ꢅꢁꢄ

3.1 Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

3.2 Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

3.3 Program/Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

3.4 System and User Stacks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

3.5 Input Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

3.6 Output registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

3.7 Configuration Registers & Option Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

3.8 Fuzzy registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

ꢊꢅ0(025<ꢅ352*5$00,1*ꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅ ꢅꢄꢁ

4.1 Program/Data Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

4.2 Memory Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

4.2.1 Programming Mode start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

4.2.2 Fast Programming procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4.2.3 Random data writing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4.2.4 Option Bytes Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

4.3 Memory Verify. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

4.3.1 Fast read procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

4.3.2 Random data reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

4.4 Memory Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

4.5 ID Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

4.6 Error cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

4.7 In-Situ Programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

4.8 In-Application Programming (IAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

4.8.1Single byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

4.8.2 Block write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

4.8.3 Memory Corruption Prevention. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

4.8.4 Option Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

4.8.5 Input Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

2/123

67ꢀꢁ)ꢀꢂꢂꢃ)ꢀꢂꢄ

ꢀꢅ,17(558376 ꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅ ꢅꢊꢆ

5.1 Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

5.2 Global Interrupt Request Enabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

5.3 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

5.4 Interrupt Maskability and Priority Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

5.5 Interrupt RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

5.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

ꢋꢅ&/2&ꢌꢍꢅ5(6(7ꢅꢎꢅ32:(5ꢅ6$9,1*ꢅ02'(6 ꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅ ꢅꢊꢀ

6.1 Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

6.2 Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

6.2.1 External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

6.2.2 Reset Procedures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

6.3 Programmable Low Voltage Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

6.4 Power Saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

6.4.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

6.4.2 Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

6.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

6.5.1 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

6.5.2 Option Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

ꢈꢅ,ꢃ2ꢅ32576 ꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅ ꢅꢀꢆ

7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

7.2 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

7.3 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

7.4 Interrupt Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

7.5 Alternate Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

7.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

7.6.1 Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

7.6.2 Input Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

7.6.3 Output Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

ꢏꢅ)8==<ꢅ&20387$7,21ꢅꢐ'3ꢑꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅ ꢅꢀꢈ

8.1 Fuzzy Inference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

8.2 Fuzzyfication Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

8.3 Inference Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

8.4 Defuzzyfication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

8.5 Input Membership Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

8.6 Output Singleton . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

8.7 Fuzzy Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

ꢉꢅ,16758&7,21ꢅ6(7ꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅ ꢅꢋꢆ

9.1 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

9.2 Instruction Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

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ꢆꢂꢅ:$7&+'2*ꢅ7,0(5ꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅ ꢅꢋꢋ

10.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

10.2 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

ꢆꢆꢅ3:0ꢃ7,0(56ꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅ ꢅꢋꢏ

11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

11.2 Timer Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

11.3 PWM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

11.3.1 Simultaneous Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

11.4 Timer Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

11.5 PWM/Timer 0 Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

11.5.1 PWM/Timer 0 Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

11.5.2 PWM/Timer 0 Input Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

11.5.3 PWM/Timer 0 Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

11.6 PWM/Timer 1 Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

11.6.1 PWM/Timer 1 Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

11.6.2 PWM/Timer 1 Input Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

11.6.3 PWM/Timer 1 Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

ꢆꢁꢅ,ꢁ&ꢅ%86ꢅ,17(5)$&(ꢅꢐ,ꢁ&ꢑꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅ ꢅꢈꢈ

12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

12.2 Main Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

12.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

12.3.1 Mode Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

12.3.2 Communication Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

12.3.3 SDA/SCL Line Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

12.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

12.4.1 Slave Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

12.4.2 Master Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

12.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

12.5.1 I2C Interface Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

12.5.2 I2C Interface Input Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

12.5.3 I2C Interface Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

ꢆꢄꢅ6(5,$/ꢅ3(5,3+(5$/ꢅ,17(5)$&(ꢅꢐ63,ꢑ ꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅ ꢅꢏꢈ

13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87

13.2 Main Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87

13.3 General description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87

13.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87

13.4.1 Master Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

13.4.2 Slave Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

13.4.3 Data Transfer Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

13.4.4 Write Collision Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

13.4.5 Master Mode Fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

13.4.6 Overrun Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

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13.4.7 Single Master and Multimaster Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

13.4.8 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

13.5 SPI Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94

13.5.1 SPI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

13.5.2 SPI Input Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

13.5.3 SPI Output Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

ꢆꢊꢅ(/(&75,&$/ꢅ&+$5$&7(5,67,&6 ꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅ ꢅꢉꢈ

14.1 Parameter Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97

14.1.1 Minimum and Maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

14.1.2 Typical curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

14.1.3 Typical values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

14.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

14.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

14.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98

14.3 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99

14.4 Supply Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100

14.5 Clock and Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103

14.6 Power on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103

14.7 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104

14.8 Programmable Low Voltage Detector (PLVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105

14.9 Internal oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105

14.10 Port Pin Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106

14.10.1 General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

14.10.2Output Driving Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

14.11 Control Pins Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108

14.11.1 RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

14.11.2 VPP pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

14.12 EMC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109

14.12.1 Functional EMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

14.12.2 Absolute Electrical Sensitivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

14.12.3 Electro-Static Discharge (ESD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

14.12.4 Static and Dynamic Latch-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

14.12.5 ESD Pin Protection Strategy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

14.13 I2C Interface Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112

14.14 SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113

ꢆꢀ3$&ꢌ$*(ꢅ&KDUDFWHULVWLFV ꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅ ꢅꢆꢆꢀ

15.1 SO16 Package Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115

15.2 SO20 Package Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116

15.3 PDIP20 Package Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117

15.4 SO28 Package Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118

15.5 SDIP32 Package Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119

ꢆꢋꢅ,03257$17ꢅ127(6ꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅ ꢅꢆꢁꢂ

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16.1 SILICON IDENTIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120

16.2 SILICON LIMITATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120

16.2.1 EEPROM writing error flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

16.2.2 CPU Prescaler after RESET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

16.2.3 I2C GENERAL CALL flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

16.2.4 HALT not skipped . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

ꢆꢈꢅ5(9,6,21ꢅ+,6725< ꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅꢇꢅ ꢅꢆꢁꢆ

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67ꢀꢁ)ꢀꢂꢂꢃ)ꢀꢂꢄ

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ST52F500/F503 are devices of ST FIVE family of

8-bit Intelligent Controller Units (ICU), which can

perform, both boolean and Fuzzy algorithms in an

efficient manner, in order to reach the best

performances that the two methodologies allow.

Produced by STMicroelectronics using the reliable

high performance CMOS process for Single

Voltage Flash versions, ST52F500/F503 include

integrated on-chip peripherals that allow

maximization of system reliability, and decreased

system costs in order to minimize the number of

external components.

The flexible I/O configuration of ST52F500/F503

allow one to interface with a wide range of external

devices (for example D/A converters or power

control devices), and to communicate with the

most common serial standards.

An internal programmable WATCHDOG is

available to avoid loop errors and reset the ICU.

ST52F500/F503 supply different peripherals to

implement

the

most

common

serial

communication protocols. I²C and SPI peripherals

allow the implementation of synchronous serial

protocols. I²C peripherals can work both in master

and slave mode. SPI implements Single and Multi

Master modes using 3-wire.

Up to 8 interrupt vectors are available, which allow

synchronization with peripherals and external

devices. Non-Maskable Interrupt and S/W TRAP

are available. All interrupts have configurable

priority levels and are maskable excluding the

Non-Maskable Interrupt, which has fixed top level

priority. Two versatile Port Interrupts are available

for synchronization with external sources.

The ST52F500/F503 also include an on-chip

Power-on-Reset (POR), which provides an internal

chip reset during power up situation and a

Programmable Low Voltage Detector (PLVD),

which causes the ICU to reset if the voltage source

ST52F500/F503 pins are configurable. The user

can set input or output signals on each single pin

in 8 different modes, reducing the need for external

components in order to supply a suitable interface

with the port pins.

V

_DDdips below a threshold. Three programmable

thresholds are available, allowing to work with

different supply voltages (from 2.4 to 5.5 V).

In order to optimize energy consumption, two

different power saving modes are available: Wait

mode and Halt mode.

Internal Oscillator at 10 MHz ± 1% is available.

External clock or quartz oscillator are also

applicable. The device always starts with the

Internal Oscillator, then it reads an Option Byte

where the clock mode to be used is programmed.

Program Memory addressing capability addresses

up to 8 Kbytes of memory location to store both

program instructions and data.

Memory can be locked by the user in order to

prevent external undesired operations.

A hardware multiplier and divider, together with a

wide instruction set, allow the implementation of

complex functions by using a single instruction.

Therefore, program memory utilization and

computational speed is optimized.

Fuzzy Logic dedicated structures in ST52F500/

F503 ICU’s can be exploited to model complex

system with high accuracy in a useful and simple

manner.

Fuzzy Expert Systems for overall system

management and Fuzzy Real time Controls can be

designed to increase performance at competitive

costs.

The linguistic approach characterizing Fuzzy Logic

is based on a set of IF-THEN rules, which describe

the control behavior and on Membership Functions

associated with input and output variables.

Operations may be performed on data stored in

RAM, allowing direct combination of new inputs

and feedback data. All RAM bytes are used like

Register File.

Up to 340 Membership Functions, with triangular

and trapezoidal shapes, or singleton values are

available to describe fuzzy variables.

The Timer/PWM peripheral allows one to manage

power devices and timing signals, by implementing

different operating modes and high frequency

PWM (Pulse Width Modulation) controls. Input

Capture and Output Compare functions are

available on the Timers.

The Timer has a 16-bit programmable internal

Prescaler and a 16-bit Counter, which can use

internal or external START/STOP signals and

clock.

An additional RAM bench is added to the Program

Memory addressing space in order to allow the

management of the System/User Stacks and user

data storage.

ST52F500/F503 supply the system stack and the

user stack located in the additional RAM bench.

The user stack can be located anywhere in the

additional RAM by writing the top address in the

configuration registers, in order to avoid overlap

with other data.

Single Voltage Flash allows the user to reprogram

the devices on-board by means of the In Situ

Programming (ISP) feature. It is possible to store in

safe way up to 4K of data in the available EEPROM

7/123

67ꢀꢁ)ꢀꢂꢂꢃ)ꢀꢂꢄ

memory benches. Permanent data, both in Flash

and EEPROM can be managed by means of the

In-Application-Programming (IAP) feature. Single

byte and Page write modes are supported. Flexible

write protection, of permanent data or program

instructions, is also available.

The Instruction Set composed of up to 107

instructions allows code compression and high

speed in the program implementation.

Data and commands are transmitted by using the

I²C protocol, implemented using the internal I²C

peripheral. The In-Situ Programming protocol

(ISP) uses the following pins:

I SDA and SCL for transmission

I Vpp for entering in the mode

I RESET for starting the protocol in a stable status

I Vdd and Vss for the power supply.

The Internal clock is used in this phase.

A powerful development environment consisting of

a board and software tools allows an easy

configuration and use of ST52F500/F503.

ꢆꢇꢁꢇꢁꢅꢅ:RUNLQJꢅ0RGHꢇ

The Visual FIVE software tool allows the

development and debugging of projects via a user-

friendly graphical interface and optimization of

generated microcode.

Third-party Hardware Emulators and ‘C’ Compiler

are available to speed-up the application

implementation and time-to-market.

The processor starts the working phase following

the instructions, which have been previously

loaded in the first locations of the memory. The first

instruction must be a jump to the first program

instruction, skipping the data (interrupt vectors,

Membership Functions, user data) stored in the

first memory page.

ST52F500/F503’s internal structure includes two

computational blocks, the CONTROL UNIT (CU)

and the DATA PROCESSING UNIT (DPU), which

performs boolean functions. The DECISION

PROCESSOR (DP) block cooperates with these

blocks to perform Fuzzy algorithms.

ꢆꢇꢁꢅꢅ)XQFWLRQDOꢅ'HVFULSWLRQ

ST52F500/F503 ICU’s can work in two modes

according to the Vpp signal levels:

I Memory Programming Mode

The DP can manage up to 340 different

Membership Functions for the antecedent part of

fuzzy rules. The consequent terms of the rules are

“crisp” values (real numbers). The maximum

number of rules that can be defined is limited by

the dimensions of the standard algorithm

implemented.

I Working Mode

During Working Mode Vpp must be tied to Vss. To

enter the Memory Programming Mode, the Vpp pin

must be tied to Vdd.

A RESET signal must be applied to the device to

switch from one mode to the other.

The Program/Data Memory is shared between

Fuzzy and standard algorithms. Within this

memory, the user data can be stored both in non

volatile memory as well as in the RAM locations.

ꢆꢇꢁꢇꢆꢅꢅ0HPRU\ꢅ3URJUDPPLQJꢅ0RGHꢇ

The ST52F500/F503 memory is loaded in the

Memory Programming Mode. All instructions and

data are written inside the memory during this

phase. The Option Bytes are loaded during this

phase by using the programming tools. The Option

Bytes can only be loaded in this phase and cannot

be modified run-time.

The Control Unit (CU) reads information and the

status of the peripherals.

Arithmetic calculus can be performed on these

values by using the internal CU and Register File,

which supports all computations. The peripheral

inputs can be Fuzzy and/or arithmetic output

values contained in the Register File or Program/

Data Memory.

8/123

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I²C

ST52F500YmM6

ST52F500FmM6

ST52F500FmB6

4/8 K FLASH

256

-

2X16-bit

10

14

So 16

So 20

Dip 20

I²C SPI

-

I²C SPI

ST52F500GmM6

4/8 K FLASH

256

2X16-bit

22

So 28

I²C SPI

I²C

ST52F500KmB6

ST52F503YmM6

ST52F503FmM6

ST52F503FmB6

ST52F503GmM6

ST52F503KmB6

4/8 K FLASH

256

-

2X16-bit

22

10

14

22

SDip 32

So 16

256

I²C SPI

So 20

Dip 20

So 28

SDip 32

Watchdog

Yes

Other Features

NMI, PLVD, POR, ISP, IAP, Internal Oscillator

From -40° to +85°

Temperature Range

Operating Supply

CPU Frequency

2.8 - 5.5 V

from 1 to 20 MHz.

/HJHQGꢒ

F=FLASH

500, 503

Y=16 pins, F=20 pins, G=28 pins, K=32 pins

2=4 Kb, 3=8 Kb Flash

B=PDIP/SDIP, M=PSO

0=+25, 1=0 +70, 3=-40 +125, 5=-10 +85, 6=-40 +85, 7=-40 +105

9/123

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MEMORY

I²C

FLASH

ISP/IAP

DATA RAM

256 bytes

PA7:0

PORT A

DATA

EEPROM

TIMER/PWM 0

TIMER/PWM 1

MEMORY

INTERFACE

CORE

ALU &

DPU

PB7:0

PC5:0

PORT B

SPI

DECISION

PROCESSOR

CONTROL

UNIT

Register File

256 bytes

Input

registers

PORT C

WATCHDOG

PC

FLAGS

POWER SUPPLY

POWER ON

RESET

OSCILLATOR

& PLVD

VDD VPP

VSS

OSCIN OSCOUT

RESET

10/123

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1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

1

20

Vdd

Vss

2

19

OscOut

RESET

SO20

DIP20

3

18

OscIn

Vpp

PA0/SCL

OscIn

Vpp

PA0/SCL

4

17

PA1/SDA

5

16

PB0/SCK

PB1/MOSI

PB2/MISO

PB3/SS

PB4

PA2/T1OUT

PA3/TRES

PA4/TSTRT

PA5/TCLK

PA6/T0OUT

PA7/INT

PB0/SCK

PB1/MOSI

PB2/MISO

PB3/SS

PB4

PA2/T1OUT

6

15

PA3/TRES

7

14

PA4/TSTRT

8

13

PA5/TCLK

9

12

11

PA6/T0OUT

PA7/INT

10

PB5

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1

16

15

14

13

12

11

10

9

Vdd

Vss

2

OscOut

RESET

SO16

3

OscIn

PA0/SCL

4

Vpp

PA1/SDA

PA2/T1OUT

PA3/TRES

PA4/TSTRT

PA5/TCLK

5

PB0

6

PB1

7

PA7/INT

8

PA6/T0OUT

11/123

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1

Vdd

Vss

32

31

30

29

28

27

26

25

24

23

22

21

2

VssIO

1

28

27

26

25

24

23

22

21

20

19

18

17

16

15

Vdd

OscOut

OscIn

VddIO

Vss

SDIP32

3

2

OscOut

RESET

SO28

4

3

OscIn

Vpp

PA0/SCL

PA1/SDA

PA2/T1OUT

PA3/TRES

PA4/TSTRT

PA5/TCLK

PA6/T0OUT

PA7/INT

PA0/SCL

PA1/SDA

PA2/T1OUT

PA3/TRES

PA4/TSTRT

PA5/TCLK

PA6/T0OUT

PA7/INT

PC5

5

4

Vpp

6

5

PB0/SCK

PB1/MOSI

PB2/MISO

PB3/SS

PB4

PB0/SCK

PB1/MOSI

PB2/MISO

PB3/SS

PB4

7

6

8

7

9

8

10

11

12

13

14

9

10

11

12

13

14

PB5

PC5

PB6

PC4

PB7

20

19

18

17

PB7

PC4

PC0

PC3

PC2

PC1

15

16

PC2

N.C.

12/123

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7DEOHꢅꢆꢇꢁꢅ 67ꢀꢁ)ꢀꢂꢂꢃ)ꢀꢂꢄꢅ6',3ꢄꢁꢅ3LQꢅ/LVW

1

2

3

4

Vdd

VddIO

Digital Power Supply

Digital I/O Ports Power Supply

Oscillator Output

OSCOUT

OSCIN

Oscillator Input

5

6

7

Vpp

Programming Mode Selector

Digital I/O, SPI Serial Clock

PB0/SCK

PB1/MOSI

A

Digital I/O, SPI Master out Slave in

Digital I/O, SPI Master in Slave out

8

PB2/MISO

A

9

PB3/SS

PB4

PB5

PB6

PB7

PC0

PC1

N.C

A

Digital I/O, SPI Slave Select

Digital I/O

10

11

12

13

14

15

16

17

18

19

20

21

Digital I/O

Not Connected

Digital I/O

N.C

PC2

PC3

PC4

PC5

A

Digital I/O

22

23

24

25

26

27

28

29

30

31

32

PA7/INT

PA6/T0OUT

PA5/TCLK

PA4/TSTRT

PA3/TRES

PA2/T1OUT

PA1/SDA

PA0/SCL

RESET

A

B

Digital I/O, Non Maskable Interrupt

Digital I/O, Timer/PWM 0 output

Digital I/O, Timer/PWM 0 clock

Digital I/O, Timer/PWM 0 start/stop

Digital I/O, Timer/PWM 0 Reset

Digital I/O, Timer/PWM 1 output

2

Serial Data I/O

Serial Clock

Digital I/O, I C Serial Data I/O

2

Digital I/O, I C Serial Clock

General Reset

Digital Ground

General Reset

Digital I/O Ports Ground

Digital Ground

VssIO

Vss

13/123

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1

2

3

4

Vdd

OSCOUT

OSCIN

Vpp

Digital Power Supply

Oscillator Output

Oscillator Input

Programming Mode Selector

5

6

7

8

PB0/SCK

PB1/MOSI

PB2/MISO

PB3/SS

A

Digital I/O, SPI Serial Clock

Digital I/O, SPI Master out Slave in

Digital I/O, SPI Master in Slave out

Digital I/O, SPI Slave Select

9

PB4

PB5

PB6

PB7

PC0

PC1

PC2

PC3

PC4

A

B

A

Digital I/O

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

PC5

A

B

Digital I/O

PA7/INT

Digital I/O, Non Maskable Interrupt

Digital I/O, Timer/PWM 0 output

Digital I/O, Timer/PWM 0 clock

Digital I/O, Timer/PWM 0 start/stop

Digital I/O, Timer/PWM 0 Reset

Digital I/O, Timer/PWM 1 output

PA6/T0OUT

PA5/TCLK

PA4/TSTRT

PA3/TRES

PA2/T1OUT

PA1/SDA

PA0/SCL

RESET

2

Serial Data I/O

Serial Clock

Digital I/O, I C Serial Data I/O

2

Digital I/O, I C Serial Clock

General Reset

Digital Ground

General Reset

Digital Ground

Vss

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1

2

3

4

Vdd

OSCOUT

OSCIN

Vpp

Digital Power Supply

Oscillator Output

Oscillator Input

Programming Mode Selector

5

6

PB0

A

B

A

Digital I/O

PB1

Digital I/O

7

PA7/INT

PA6/T0OUT

PA5/TCLK

PA4/TSTRT

PA3/TRES

PA2/T1OUT

PA1/SDA

PA0/SCL

RESET

Digital I/O, Non Maskable Interrupt

Digital I/O, Timer/PWM 0 output

Digital I/O, Timer/PWM 0 clock

Digital I/O, Timer/PWM 0 start/stop

Digital I/O, Timer/PWM 0 Reset

Digital I/O, Timer/PWM 1 output

8

9

10

11

12

13

14

15

16

2

Serial Data I/O

Serial Clock

Digital I/O, I C Serial Data I/O

2

Digital I/O, I C Serial Clock

General Reset

Digital Ground

General Reset

Digital Ground

Vss

15/123

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1

2

3

4

Vdd

OSCOUT

OSCIN

Vpp

Digital Power Supply

Oscillator Output

Oscillator Input

Programming Mode Selector

5

6

7

8

PB0

PB1

A

Digital I/O

PB2/MISO

PB3/SS

Digital I/O, SPI Master in Slave out

Digital I/O, SPI Slave Select

9

PB4

B

A

Digital I/O

10

11

12

13

14

15

16

17

18

19

20

PB5

Digital I/O

PA7/INT

PA6/T0OUT

PA5/TCLK

PA4/TSTRT

PA3/TRES

PA2/T1OUT

PA1/SDA

PA0/SCL

RESET

Digital I/O, Non Maskable Interrupt

Digital I/O, Timer/PWM 0 output

Digital I/O, Timer/PWM 0 clock

Digital I/O, Timer/PWM 0 start/stop

Digital I/O, Timer/PWM 0 Reset

Digital I/O, Timer/PWM 1 output

2

Serial Data I/O

Serial Clock

Digital I/O, I C Serial Data I/O

2

Digital I/O, I C Serial Clock

General Reset

Digital Ground

General Reset

Digital Ground

Vss

16/123

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1

2

3

4

Vdd

OSCOUT

OSCIN

Vpp

Digital Power Supply

Oscillator Output

Oscillator Input

Programming Mode Selector

5

6

7

8

PB0/SCK

PB1/MOSI

PB2/MISO

PB3/SS

A

B

Digital I/O, SPI Serial Clock

Digital I/O, SPI Master out Slave in

Digital I/O, SPI Master in Slave out

Digital I/O, SPI Slave Select

9

PB4

B

A

B

Digital I/O

10

11

12

13

14

15

16

17

18

19

20

PB5

Digital I/O

PA7/INT

PA6/T0OUT

PA5/TCLK

PA4/TSTRT

PA3/TRES

PA2/T1OUT

PA1/SDA

PA0/SCL

RESET

Digital I/O, Non Maskable Interrupt

Digital I/O, Timer/PWM 0 output

Digital I/O, Timer/PWM 0 clock

Digital I/O, Timer/PWM 0 start/stop

Digital I/O, Timer/PWM 0 Reset

Digital I/O, Timer/PWM 1 output

2

Serial Data I/O

Serial Clock

Digital I/O, I C Serial Data I/O

2

Digital I/O, I C Serial Clock

General Reset

Digital Ground

General Reset

Digital Ground

Vss

17/123

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3$ꢂꢓ3$ꢈꢍꢅ 3%ꢂꢓ3%ꢈꢍ3&ꢂꢓ3&ꢀ.ꢅ These lines are

organized as I/O ports. Each pin can be configured

as an input, output (with pull-up, push-pull, weak-

pull-up, open-drain, high-impedance), or as an

interrupt source.

ST52F500/F503 pins can be set in digital input

mode, digital output mode, interrupt mode or in

Alternate Functions. Pin configuration is achieved

by means of the configuration registers. The

functions of the ST52F500/F503 pins are

described below:

7ꢂ287ꢍꢅ 7ꢆ287. These pins output the signals

generated by the PWM/Timer 0 and PWM/Timer 1

peripheral.

9

Main Power Supply Voltage.

75(6, 76757ꢍꢅ7&/ꢌꢅ. These pins are related to

the PWM/Timer 0 peripheral and are used for Input

Capture and event counting. The TRES pin is used

to set/reset the Timer; the TSTRT pin is used to

start/stop the counter. The Timer can be driven by

the internal clock or by an external signal

connected to the TCLK pin.

I/O Ports Power Supply Voltage. It is

reccomended to connect this pin with a supply

voltage de-coupled with V_DDin order to improve

the immunity from the noise generated by the I/O

switching.

9

. Digital circuit Ground.

,17. This pin is used as input for the Non-Maskable

(top level) interrupt. The interrupt signal is detected

only if the pin is configured in Alternate Function.

. I/O Ports Ground. See V_DDIO

. Programming/Working mode selector. During

the Programming phase V_PPmust be set to V_DD

In Working phase V_PPmust be equal to V_SS

.

6&/ꢍꢅ 6'$. These pin are used respectively as

Serial Clock and Serial Data I/O in I²C peripheral

protocol. They are used also in Programming

Mode to receive and transmit data.

.

26&LQ and 26&RXWꢇ These pins are internally

connected to the on-chip oscillator circuit. A quartz

crystal or a ceramic resonator can be connected

between these two pins in order to allow correct

use of ST52F500/F503 with various stability/cost

trade-offs. An external clock signal can be applied

to OSCin: in this case OSCout can be floating.

Without any connection, the device can work with

its internal clock generator (10 MHz)

6&ꢌꢍꢅ0,62ꢍꢅ026,ꢍꢅ66. These pins are used by

the Serial Peripheral Interface (SPI) peripheral.

SCK is the serial clock line. MISO (Master In Slave

Out) and MOSI (Master Out Slave In) are the serial

data lines, which work in input or in output

depending on if the device is working in slave or

master mode. The SS pin allows the selection of

the device master/slave mode.

5(6(7. This signal is used to reset the ST52F500/

F503 and re-initialize the registers and control

signals. It is also used when switching from the

Programming Mode to Working Mode and vice

versa.

18/123

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The Control Unit (CU) decodes the instructions

stored in the Program Memory and generates the

appropriate control signals. The main parts of the

CU are illustrated in Figure 2.1.

The five different parts of the CU manage Loading,

Logic/Arithmetic, Jump, Control and the Fuzzy

instruction set.

The block called “Collector” manages the signals

deriving from the different parts of the CU. The

collector defines the signals for the Data

Processing Unit (DPU) and Decision Processor

(DP), as well as for the different peripherals of the

ICU.

The block called “Arbiter” manages the different

parts of the CU, so that only one part of the system

is activated during working mode.

The CU structure is extremely flexible and was

designed with the purpose of easily adapting the

core of the microcontroller to market needs. New

instruction sets or new peripherals can easily be

included without changing the structure of the

microcontroller, maintaining code compatibility.

A set of 107 different instructions is available. Each

instruction requires a number of clock pulses to be

performed that depends on the complexity of the

instruction itself. The clock pulses to execute the

instructions are driven directly by the masterclock,

which has the same frequency of the oscillator

signal supplied.

ST52F500/F503’s architecture is Register File

based and is composed of the following blocks and

peripherals:

I Control Unit (CU)

I Data Processing Unit (DPU)

I Decision Processor (DP)

I ALU

I Memory Interface

I up to 256 bytes Register File

I Program/Data Memory

I Data EEPROM

I Interrupts Controller

I Clock Oscillator

I PLVD and POR

I Digital I/O ports

I Timer/PWMs

I I²C

I SPI

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MicroCode

Loading

Instruction Set

C

O

L

Logic Arithmetic

Instruction Set

A

R

B

L

I

T

E

Jump

Instruction Set

E

C

T

Control

Signals

R

O

R

Control

Instruction Set

Decision Processor

Clock Master

Instruction Set

19/123

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The DPU receives, stores and sends the

instructions deriving from the Program/Data

Memory, Register File or from the peripherals. It is

controlled by the CU on the basis of the decoded

instruction. The Fuzzy registers store the partial

results of the fuzzy computation. The accumulator

register is used by the ALU and is not accessible

directly: the instructions used by the ALU can

address all the Register File locations as

operands, allowing a more compact code and a

faster execution.

The PC can be changed in the following ways:

I JP (Jump)

I Interrupt

I RETI

PC = Jump Address

PC = Interrupt Vector

PC = Pop (stack)

I RET

PC = Pop (stack)

I CALL

PC = Subroutines address

PC = Reset Vector

I Reset

I Normal Instruction PC = PC + instr. lenght

The following addressing modes are available:

inherent, immediate, direct, indirect, bit direct.

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The ST FIVE core includes different sets of flags

that correspond to 2 different modes: normal mode

and interrupt mode. Each set of flags consist of a

CARRY flag (C), ZERO flag (Z) and SIGN flag (S).

Each set is stacked: one set of flags is used during

normal operation and other sets are used during

each level of interrupt. Formally, the user has to

manage only one set of flags: C, Z and S since the

flag stack operation is performed automatically.

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The Program Counter (PC) is a 16-bit register that

contains the address of the next memory location

to be processed by the core. This memory location

may be both an instruction or data address.

The Program Counter’s 16-bit length allows the

direct addressing of a maximum of 64 Kbytes in the

Program/Data Memory space.

20/123

67ꢀꢁ)ꢀꢂꢂꢃ)ꢀꢂꢄ

Each interrupt level has its own set of flags, which

is saved in the Flag Stack during interrupt

servicing. These flags are restored from the Flag

Stack automatically when a RETI instruction is

executed.

If the ICU was in normal mode before an interrupt,

after the RETI instruction is executed, the normal

flags are restored.

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The 8-bit Arithmetic Logic Unit (ALU) performs

arithmetic calculations and logic instructions such

as: sum, subtraction, bitwise AND, OR, XOR, bit

set and reset, bit test and branch, right/left shift and

rotate (see Chapter 9 Instruction Set for further

details).

In addition, the ALU of ST52F500/F503 can

perform multiplication (MULT) and division (DIV).

Multiplication is performed by using 8 bit operands

storing the result in 2 registers (16 bit values); the

division instruction addresses the MSB of the

dividend (the LSB is stored in the next address):

the result and remainder are stored in these source

addresses (see Figure 2.3 and Figure 2.4).

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Flags are not cleared during context switching and

remain in the state they were in at the exit of the

last interrupt routine switching.

The Carry flag is set when an overflow occurs

during arithmetic operations, otherwise it is

cleared.The Sign flag is set when an underflow

occurs during arithmetic operations, otherwise it is

cleared.

In order to manage signed type values, the ALU

also performs addition and subtraction with offset

(ADDO

and

SUBO).

These

instructions

respectively subtract and add 128 to the overall

result, in order to manage values logically in the

range between -128,127.

The flags, related to the current context, can be

checked by reading the FLAGS Input Register 38

(026h).

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RAM

000h

001h

002h

000h

001h

002h

i-1

i

i+1

j-1

j

j-1

j

j+1

0FDh

0FEh

0FFh

0FDh

0FEh

0FFh

X

REG. j

LSB

REG. i

MSB

:

REG. j

REG. j+1

REG. i

16 Bit

REMAINDER

QUOTIENT

21/123

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Input Register 38 (026h) Read Only

Reset Value: 0000 0000 (00h)

7

0

C

-

Z

S

Bit 7-3: Not Used

Bit 2: =ꢅ Zero flag

Bit 1: 6ꢅSign flag

Bit 0: &ꢅCarry flag

22/123

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The Register File consists of 256 general purpose

8-bit RAM locations called “registers” in order to

recall the functionality.

The Register File exchanges data with all the other

addressing spaces and is used by the ALU to

perform all the arithmetic and logic instructions.

These instructions have any Register File address

as operands.

ST52F500/F503 has six separate addressing

spaces:

I Register File

I Program/Data Memory and stacks

I Input Registers

I Output Registers

Data can be moved from one location to another by

using the LDRR instruction; see further ahead for

information on the instruction used to move data

between the Register File and the other

addressing spaces.

I Configuration Registers

I Fuzzy Registers

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3URJUDPꢀPHPRU\ꢁ

Each space is addressed by a load type instruction

that indicates the source and the destination space

in the mnemonic code (see Figure 3.1).

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The Program/Data Memory consists of both non-

volatile memory (Flash, EEPROM) and RAM

memory benches.

Non-volatile memory (NVM) is mainly used to store

the user program and can also be used to store

permanent data (constant, look-up tables).

Each RAM bench consists of 256 locations used to

store run-time user data. At least one bench is

present in the devices. RAM benches are also

used to implement both System and User Stacks.

NVM & RAM locations can be accessed by means

of the LDER and LDRE instructions.

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The read/write operation in the space addresses

are managed by the Memory Interface, which can

recognize the type of memory addressed and set

the appropriate access time and mode.

In addition, the Memory Interface manages the In

Application Programming (IAP) functions in Flash

devices like writing cycle and memory write

protection.

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REGISTER FILE

DECISION

PROCESSOR

REGISTERS

OUTPUT

REGISTERS

NON VOLATILE MEMORY

LDFR

LDER

LDPR

LDCNF

GETPG

PERIPHERAL

BLOCK

LDRE

PGSETR

PROGRAM

COUNTER

PERIPHERAL

BLOCK

RAM BANKS

AND STACKS

CONFIGURATION

REGISTERS

INPUT REGISTERS

LDCR

LDRI

CU

DPU

ALU

PERIPHERAL

BLOCK

LDCE

LDPE

23/123

67ꢀꢁ)ꢀꢂꢂꢃ)ꢀꢂꢄ

NVM is always located beginning after the first

locations of the addressing space. RAM banks are

always located after NVM.

NVM is organized in accordance to the following

blocks (see Figure 3.2):

I 5HVHWꢀ 9HFWRUꢀ EORFN (from address 0 to 2)

contains an absolute jump instruction to the first

user program instruction. The Assembler tool

automatically fills these locations with correct

data.

I 0EIVꢀ 6HWWLQJꢀ EORFNꢀ (just after the interrupt

vectors) contains the coordinates of the vertexes

of every Mbf defined in the program. The last

address that can be assigned to this block is

1023. This area is dynamically assigned

according to the size of the fuzzy routines. The

memory area that remains unused, if any, is

assigned to the Program Instructions block.

I 7KHꢀ 3URJUDPꢀ ,QVWUXFWLRQVꢀ EORFNꢀ (just after the

last Mbf data through the last NVM address)

contains the instruction of the user program and

the permanent data.

I ,QWHUUXSWꢀ 9HFWRUVꢀ EORFN (from location 3 up to

32) contains the interrupt vectors. Each address

is composed of three bytes (the jump opcode

and the 16 bit address). Interrupt vectors are set

by using IRQ pseudo-instruction (see the

Programming Manual).

I 2SWLRQꢀ E\WHVꢀ EORFN (from location 3000h to

307Fh) is the addressing space reserved for the

option bytes. In ST52F500/F503, only the

location from 3000h to 3007h are used.

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24/123

67ꢀꢁ)ꢀꢂꢂꢃ)ꢀꢂꢄ

Flash and EEPROM are programmed electrically

just applying the supply voltage and they are also

erased electrically; this feature allows the user to

easily reprogram the memory without taking the

device off from the board (In Situ Programming

ISP). Data and commands are transmitted through

the I²C serial communication protocol. Data can

also be written run-time with the In Application

Programming (IAP)

NVM can be locked by the user during the

programming phase, in order to prevent external

operation such as reading the program code and

assuring protection of user intellectual property.

Flash and EEPROM pages can be protected by

unintentional writings.

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The System and User Stacks are located in the

Program/Data memory in the RAM benches.

System Stacks are used to push the Program

Counter (PC) after an Interrupt Request or a

Subroutine Call. After a RET (Return from a

subroutine) or a RETI (Return from an interrupt)

the PC that is saved is popped from the stack and

restored. After an interrupt request, the flags are

also saved in a reserved stack inside the core, so

each interrupt has its own flags.

The System Stack is located in the last RAM bench

starting from the last address (20FFh) inside the

bench page. The System Stack Pointer (SSP) can

be read and modified by the user. For each level of

stack 2 bytes of the RAM are used. The SSP points

to the first currently available stack position. When

a subroutine call or interrupt request occurs, the

content of the PC is stored in a couple of locations

pointed to by the SSP that is decreased by 2.

The operations that can be performed on the NVM

during the Programming Phase, ISP and IAP are

described in detail in the Section 4.

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SYSTEM STACK

LEVEL 1

SYSTEM STACK

LEVEL 2

SYSTEM STACK

LEVEL 3

SYSTEM STACK

LEVEL 4

USER STACK LEVEL 4

USER STACK LEVEL 3

USER STACK LEVEL 2

USER STACK LEVEL 1

25/123

67ꢀꢁ)ꢀꢂꢂꢃ)ꢀꢂꢄ

When a return occurs (RET or RETI instruction),

the SSP is increased by 2 and the data stored in

the pointed locations couple is restored back into

the PC.

The current SSP can be read and write in the

couple of Configuration Registers 44 02Ch (MSB:

page number, always 32 020h) and 45 02Dh (LSB:

location address) (see Figure 3.3). In ST52F500/

F503 the user can only consider the LSB because

the MSB is always the same.

The User Stack is used to store user data and is

located beginning from a RAM bench location set

by the user (USTP) by writing the couple of

Configuration Registers 5 005h (MSB: page

number) and 6 006h (LSB: location address) (see

Figure 3.3). Register 5, which is the page number,

must always be set to a value between 32 (020h)

and 255 (0FFh): values higher than 32 always

address RAM on page 32.

Input Registers contain data converted by the

Ports, serial communication peripherals, Timers,

etc.

The Input Registers can be accessed by using the

LDRI instruction that loads the specified Register

File address with the contents of the specified

Input Register. See the Programming Manual for

further details on this instruction. The Input

Registers are read-only registers.

In order to simplify the concept, a mnemonic name

is assigned to each register. The same name is

used in Visual FIVE development tools. The list of

the Input Registers is shown in Table 3.1.

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The ST52F500/F503 Output Registers bench

consists of a file of 8-bit registers containing data

sent to the Peripherals and the I/O Ports (for

example: Timer Counters, data to be transmitted

by the serial communication peripherals, data to be

sent to the Port pins in output, etc.).

The registers are located inside the Peripherals

and Ports, which allow flexibility and modularity in

the design of new family devices.

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UHVHWꢁ

This feature allows a flexible use of the User Stack

in terms of dimension and to avoid overlaps. The

User Stack Pointer (USP) points to the first

currently available stack location. When the user

stores a byte value contained in the Register File

by using the PUSH instruction, the value is stored

in the position pointed to by the USP that is

increased (the User Stack order is opposite to the

System Stack one). When the user takes a value

from the User Stack with the POP instruction, the

USP is decreased and the value pointed to is

copied in the specified Register File location.

By writing the USTP, the new address is

automatically written in the USP. The current USP

can be read from the Input Registers 11 0Bh

(MSB: page number, always 32 020h) and 12 0Ch

(LSB: location address) (see Figure 3.3). In

ST52F500/F503 the user can only consider the

LSB because the MSB is always the same.

The Output Registers are write only. In order to

access the configuration Register the user can use

the following instructions:

I LDPI: loads the immediate value in the specified

Output Register.

I LDPR: loads the contents of the specified

Register File location into the output register

specified. This instruction allows computed data

to be sent to Peripherals and Ports.

I LDPE direct: loads the contents of the specified

Program/Data Memory location into the output

register specified. This instruction allows data to

be sent to Peripherals and Ports from a table.

I LDPE indirect: loads the contents of the

Program/Data Memory location whose address

is contained in the specified Register File

location into the output register specified. This

instruction allows data to be sent to Peripherals

and Ports from a table pointed to by a register.

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7RSꢀORFDWLRQꢀDQGꢀWKHꢀ6\VWHPꢀ6WDFNꢀ3RLQWHUꢀVKRXOG

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See the Programming manual for further details

about these instructions.

In order to simplify the concept, a mnemonic name

is assigned to each register. The same name is

used in Visual FIVE development tools. The list of

the Output Registers is shown in Table 3.2.

ꢄꢇꢀꢅꢅ,QSXWꢅ5HJLVWHUVꢅ

The ST52F500/F503 Input Registers bench

consists of a file of 8-bit registers containing data

or the status of the peripherals. For example, the

26/123

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I LDCE: loads the Configuration Register

specified with the contents of the specified

Program/Data Memory location, allowing the

configuration data to be taken from a table.

The ST52F500/F503 Configuration Registers

bench consists of a file of 8-bit registers that allows

the configuration of all the ICU blocks.

The registers are located inside the block they

configure in order to obtain greater flexibility and

modularity in the design of new family devices. In

the Configuration Registers, each bit has a

particular use, so the logic level of each of them

must be considered.

I LDCNF: loads the

Register File location

specified with the contents of the Configuration

Register indicated, allowing for the inspection of

the configuration of the device (permitting safe

run-time modifications).

Some special configuration data, that needs to be

load at the start-up and not further changed, are

stored in Option Bytes. These are loaded only

during the device programming phase. See Table

3.3 and Section 4 for a detailed description of the

Option Bytes.

The Configuration Registers are readable and

writable; the addresses refer to the same register

both in read and in write. In order to access the

Configuration Register the user can work in

several modes by utilizing the following

instructions:

In order to simplify the concept, a mnemonic name

is assigned to each register. The same name is

used in Visual FIVE development tools. The list of

the Configuration Registers is shown in Table 3.4.

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The Decision Processor for Fuzzy computation is

accessed by means of 8 dedicated registers.

These registers are used to load values in input to

the Decision Processor.

The values are loaded in the Fuzzy Register by

mean of the LDFR instruction. This instruction set

the specified Fuzzy Register (addresses from 0 to

7) with the value stored in the specified address of

the Register File.

I LDCI: loads the immediate value in the

Configuration Register specified and is the most

commonly used to write configuration data.

I LDCR: loads the Configuration Register

specified with the contents of the specified

Register File location, allowing a parametric

configuration.

See Chapter 8 FUZZY COMPUTATION (DP) for

further informations.

27/123

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7DEOHꢅꢄꢇꢆꢅ ,QSXWꢅ5HJLVWHUV

PORT_A_IN

PORT_B_IN

PORT_C_IN

-

Port A data Input Register

Port B data Input Register

Port C data Input Register

Not Used

0

1

2

3

4

5

6

00h

01h

02h

03h

04h

05h

06h

-

Not Used

SPI_IN

I2C_IN

Serial Peripheral Interface data Input Register

2

I C Interface data Input Register

2

I2C_SR1

7

07h

I C Interface Status Register 1

2

I2C_SR2

8

08h

09h

0Ah

0Bh

0Ch

I C Interface Status Register 2

-

Not Used

9

-

Not Used

10

11

12

USP_H

USP_L

User Stack Pointer (MSB)

User Stack Pointer (LSB)

0Dh-

014h

-

Not Used

13-20

PWM0_COUNT_IN_H

PWM0_COUNT_IN_L

PWM0_STATUS

PWM/Timer 0 Counter Input Register (MSB)

PWM/Timer 0 Counter Input Register (LSB)

PWM/Timer 0 Status Register

21

22

23

24

25

26

27

28

29

30

015h

016h

017h

018h

019h

01Ah

01Bh

01Ch

01Dh

01Eh

PWM0_CAPTURE_H

PWM0_CAPTURE_L

PWM1_COUNT_IN_H

PWM1_COUNT_IN_L

PWM1_STATUS

PWM/Timer 0 Capture Register (MSB)

PWM/Timer 0 Capture Register (LSB)

PWM/Timer 1 Counter Input Register (MSB)

PWM/Timer 1 Counter Input Register (LSB)

PWM/Timer 1 Status Register

PWM1_CAPTURE_H

PWM1_CAPTURE_L

PWM/Timer 1 Capture Register (MSB)

PWM/Timer 1 Capture Register (LSB)

01Fh-

025h

-

Not Used

31-37

FLAGS

-

Flag Register

38

39

40

026h

027h

028h

Not Used

IAP_SR

In Application Programming Status Register

28/123

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7DEOHꢅꢄꢇꢁꢅ 2XWSXWꢅ5HJLVWHUV

PORT_A_OUT

PORT_B_OUT

PORT_C_OUT

-

Port A data Output Register

Port B data Output Register

Port C data Output Register

Not Used

0

1

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

2

3

-

Not Used

4

SPI_OUT

Serial Peripheral Interface data Output Register

5

2

I2C_OUT

6

I C Interface data Output Register

PWM0_COUNT_OUT_H

PWM0_COUNT_OUT_L

PWM0_RELOAD_H

PWM0_RELOAD_L

PWM1_COUNT_OUT_H

PWM1_COUNT_OUT_L

PWM1_RELOAD_H

PWM1_RELOAD_L

PWM/Timer 0 Counter Output Register (MSB)

PWM/Timer 0 Counter Output Register (LSB)

PWM/Timer 0 Reload Register (MSB)

PWM/Timer 0 Reload Register (LSB)

7

8

9

10

11

12

13

14

PWM/Timer 1 Counter Output Register (MSB)

PWM/Timer 1 Counter Output Register (LSB)

PWM/Timer 1 Reload Register (MSB)

PWM/Timer 1 Reload Register (LSB)

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OSC_CR

Oscillator Control Register

Clock Parameters

0

1

2

3

4

5

6

7

00h

01h

02h

03h

04h

05h

06h

07h

CLK_SET

OSC_SET

PLDV_CR

WDT_EN

Oscillator Set-Up

Programmable Low Voltage Detector Control Register

HW/SW Watchdog selector

First Page Write Protected

First Page not Write Protected

Wake Up from Halt Time

PG_LOCK

PG_UNLOCK

WAKEUP

29/123

67ꢀꢁ)ꢀꢂꢂꢃ)ꢀꢂꢄ

7DEOHꢅꢄꢇꢊꢅ &RQILJXUDWLRQꢅ5HJLVWHUV

INT_MASK

INT_POL

INT_PRL_L

INT_PRL_M

INT_PRL_H

USTP_H

USTP_L

WDT_CR

-

Interrupt Mask Register

0

1

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

010h

Interrupts Polarity

Interrupt Priority Register (lower priority)

Interrupt Priority Register (medium priority)

Interrupt Priority Register (higher priority)

User Stack Top Pointer (MSB)

User Stack Top Pointer (LSB)

Watchdog Configuration Register

not used

2

3

4

5

6

7

8

PWM0_CR1

PWM0_CR2

PWM0_CR3

PWM1_CR1

PWM1_CR2

-

PWM/Timer 0 Configuration Register 1

PWM/Timer 0 Configuration Register 2

PWM/Timer 0 Configuration Register 3

PWM/Timer 1 Configuration Register 1

PWM/Timer 1 Configuration Register 2

Not Used

9

10

11

12

13

14

15

16

-

Not Used

2

I2C_CR

I C Interface Control Register

2

I2C_CCR

17

18

011h

012h

I C Interface Clock Control Register

2

I2C_OAR1

I C Interface Own Address Register 1

2

I2C_OAR2

19

20

21

22

23

24

25

013h

014h

015h

016h

017h

018h

019h

I C Interface Own Address Register 2

SPI_CR

Serial Peripheral Interface Control Register

Serial Peripheral Interface Control-Status Register

Not Used

SPI_STATUS_CR

-

Not Used

PORT_A_PULLUP

PORT_A_OR

Port A Pull Up enable/disable Register

Port A Option Register

30/123

67ꢀꢁ)ꢀꢂꢂꢃ)ꢀꢂꢄ

7DEOHꢅꢄꢇꢊꢅ &RQILJXUDWLRQꢅ5HJLVWHUV

PORT_A_DDR

PORT_A_AF

Port A Data Direction Register

26

27

28

29

30

31

32

33

34

01Ah

01Bh

01Ch

01Dh

01Eh

01Fh

020h

021h

022h

Port A Alternate Function selection Register

Port B Pull Up enable/disable Register

Port B Option Register

PORT_B_PULLUP

PORT_B_OR

PORT_B_DDR

PORT_B_AF

Port B Data Direction Register

Port B Alternate Function selection Register

Port C Pull Up enable/disable Register

Port C Option Register

PORT_C_PULLUP

PORT_C_OR

PORT_C_DDR

Port C Data Direction Register

023h-

02Bh

-

Not Used

35-43

SSP_H

System Stack Pointer (MSB)

System Stack Pointer (LSB)

CPU Clock Prescaler

44

45

46

02Ch

02Dh

02Eh

SSP_L

CPU_CLK

31/123

67ꢀꢁ)ꢀꢂꢂꢃ)ꢀꢂꢄ

ꢊꢅꢅ0(025<ꢅ352*5$00,1*

Flash and EEPROM pages can be protected by

unintentional writings.

ST52F500/F503 provides an on-chip user

programmable non-volatile memory, which allows

fast and reliable storage of user data.

Program/Data Memory addressing space is

composed by a Single Voltage Flash Memory and

a RAM memory bench. The ST52F503 devices

also have a Data EEPROM bench to store

permanent data with long term retention and a high

number of write/erase cycles.

5HPDUNꢀꢁ WKHꢀ PHPRU\ꢀ FRQWHQWVꢀ DUHꢀ SURWHFWHGꢀ E\

WKHꢀ (UURUꢀ &RUUHFWLRQꢀ &RGHꢀ ꢉ(&&ꢊꢀ DOJRULWKPꢀ WKDW

XVHVꢀDꢀꢋꢌELWꢀUHGXQGDQF\ꢀWRꢀFRUUHFWꢀRQHꢀELWꢀHUURUVꢁ

ꢊꢇꢆꢅ3URJUDPꢃ'DWDꢅ0HPRU\ꢅ2UJDQL]DWLRQꢅ

The Program/Data Memory is organized as

described in Section 3.3. The various sales types

have different amounts of each type of memory.

Table 4.1 describes the memory benches amount

and page allocation for each sales type.

The addressing spaces are organized in pages of

256 bytes. Each page is composed by blocks of 32

bytes. Memory programming is performed one

block at a time in order to speed-up the

programming time (about 2.5 ms per block).

All the Program Data memory addresses can

execute code, including RAM and EEPROM

benches.

The memory is programmed by setting the V_pppin

equal to V_dd. Data and commands are transmitted

through the I²C serial communication protocol. The

same procedure is used to perform “In-Situ” the

programming of the device after it is mounted in

the user system. Data can also be written in run-

time with the In-Application Programming (IAP)

instructions.

The whole location address is composed as

follows:

15

8

7

5

4

0

The Memory can be locked by the user during the

programming phase, in order to prevent external

operation such as reading the program code and

assuring protection of user intellectual property.

Page address

Block address address inside the block

7DEOHꢅꢊꢇꢆꢅ 6DOHVꢅ7\SHꢅ0HPRU\ꢅ2UJDQL]DWLRQꢅ

ST52F500c2p6

ST52F500c3p6

ST52F503c2p6

4096 bytes

8192 bytes

3840 bytes

7936 bytes

0 to 15

0 to 31

0 to 14

0 to 30

256 bytes

32

-

256 bytes

15

31

ST52F503c3p6

legend:

c: Y=16 pins, F=20 pins, G=28 pins, K=32/34 pin

p: B=DIP, M=SO

32/123

67ꢀꢁ)ꢀꢂꢂꢃ)ꢀꢂꢄ

ꢊꢇꢁꢅ0HPRU\ꢅ3URJUDPPLQJ

ꢊꢇꢁꢇꢆꢅ3URJUDPPLQJꢅ0RGHꢅVWDUWꢇ The following

sequence starts the Programming Mode:

The Programming procedure writes the user

program and data into the Flash Memory,

EEPROM and Option Bytes. The programming

procedures are entered by setting the V_pppin

equal to V_ddand releasing the Reset signal. The

following pins are used in Programming mode:

1.

2. The device is Reset (RESET=V_SS

3. The Reset is released (RESET=V_DD

V_PPis set to V_DD

)

4. The internal oscillator starts at 10 MHz

I V_PP

I V_DD

I V_SS

used to switch to programming mode

device supply

5. The memory is turned on

6. The I²C Interface and Ports are initialized

7. The I²C Interface is configured to work as

Slave, Receiver, 7-bit address and waits for

data

device ground

I RESET device reset

I SCL

I SDA

I²C serial clock

I²C serial data

8. The Start signal is sent to the chip followed by

the Slave Address 1010000 and the direction

bit set to 0 (the addressed slave waits for da-

ta). The device sends the acknowledge

During the device programming, the internal clock

is used, so the OSCin and OSCout pins don’t have

to be considered.

9. The Programming Mode code 00000000 is

sent and acknowledged

5HPDUNꢀꢁ 7KHꢀ 2SWLRQꢀ %\WHVꢀ PXVWꢀ EHꢀ DOZD\V

SURJUDPPHGꢂꢀRWKHUZLVHꢀWKHVHꢀE\WHVꢀZLOOꢀꢀEHꢀORDGHG

ZLWKꢀ

XQSUHGLFWDEOHꢀ

YDOXHVꢂꢀ

GHWHUPLQLQJ

10. A command code is sent to the device

XQSUHGLFWDEOHꢀGHYLFHꢀFRQILJXUDWLRQꢁ

11. The procedure related to the command is ex-

ecuted

7DEOHꢅꢊꢇꢁꢅ 3URJUDPPLQJꢅ0RGHꢅ&RPPDQGV

Write the currently addressed block with the 32 bytes

Yes following the command. The Block locations are erased

before being written.

BlockWrite

00000001

32

-

Write the byte addressed by the next data sent in the

currently addressed page.

ByteWrite

BlockErase

ByteErase

00000010

00000011

00000100

2

1

Yes

Erase the block addressed by 3 MSB of the next data sent

and inside the currently addressed page.

Yes

Erase the byte addressed by the next data sent and inside

the currently addressed page.

Yes

Read the byte addressed by the next data sent and inside

the current page. The read data is sent by the device after

the re-send of the Slave Address with the R/W bit changed.

The current memory absolute address is post-incremented.

ByteRead

00000101

00001001

1

-

GlobalErase

-

Yes All the memory is erased.

Write the currently addressed block with the 32 bytes

following the command. The Block locations aren’t erased.

FastBlockWrite 00001011

32

1

No

SetPage

00001100

00001101

-

The currently addressed page is set with the next data sent.

Read the memory location currently addressed. The read

data is sent by the device after the command is

acknowledged. The current memory absolute address is

post-incremented.

ReadData

-

1

The current block address is incremented modulo 8

(address 0 follows after address 7 and the Page is post-

incremented)

IncBlock

00001111

00010011

-

This command is followed by a status data byte. Mostly

used in error condition and to check if the device is locked

ReadStatus

1

33/123

67ꢀꢁ)ꢀꢂꢂꢃ)ꢀꢂꢄ

)LJXUHꢅꢊꢇꢆꢅꢅ&RPPDQGVꢅDQGꢅ'DWDꢅ&RPPXQLFDWLRQꢅ6HTXHQFHV

3URJUDPPLQJꢅPRGHꢅVWDUWꢅVHTXHQFH

S

10100000

A

00000000

A

Command

A

Data1

A

.....

DataN

A

P

([HFXWLRQꢅRIꢅFRPPDQGVꢅIRUꢅZULWLQJꢅGDWDꢒ

Command

A

Data1

A

.....

DataN

A

Command

A

Data1

A

..... DataN

A

P

([HFXWLRQꢅRIꢅFRPPDQGVꢅIRUꢅUHDGLQJꢅGDWDꢒ

Command

A

Address

A

P

S

10100001

A

Data read NA P

S=Start, P=Stop, A=Acknowledge, NA=Non-acknowledge

From Slave to Master

From Master to Slave

The generic procedure of commands execution,

with the data communication in both directions is

displayed in Figure 4.1.

5. After the device acknowledges the 32nd byte,

it holds the SCL line until the parallel writing of

the 32 byte is completed (about 2.5 ms)

5HPDUNꢀꢁWKHꢀ6ODYHꢀ$GGUHVVꢀꢍꢅꢍꢅꢅꢅꢅꢀPXVWꢀEHꢀVHQW

DIWHUꢀ Dꢀ 6WRSꢀ ꢉLꢁHꢁꢀ HDFKꢀ WLPHꢀ WKHꢀ GDWDꢀ GLUHFWLRQ

FKDQJHVꢂꢀWRꢀVSHFLI\ꢀWKHꢀ5ꢆ:ꢀELWꢊꢁꢀ)RUꢀH[DPSOHꢎꢀLIꢀD

FRPPDQGꢀ WRꢀ VHQGꢀ GDWDꢀ WRꢀ WKHꢀ GHYLFHꢀ KDVꢀ EHHQ

H[HFXWHGꢂꢀDꢀFRPPDQGꢀIRUꢀUHFHLYLQJꢀGDWDꢀPXVWꢀEH

IROORZHGꢀE\ꢀWKHꢀVODYHꢀDGGUHVVꢀDQGꢀWKHꢀ5ꢆ:ꢀELWꢀPXVW

EHꢀVHWꢀWRꢀꢍꢁꢀ7KHꢀ3URJUDPPLQJꢀ0RGHꢀFRGHꢀGRHVQ¶W

QHHGꢀWRꢀEHꢀVSHFLILHGꢀDJDLQꢀꢁ

6. The Block Pointer is incremented by sending

the ,QF%ORFN command

7. The procedure is repeated from point 3 until

there is data to be sent to the memory

1RWHꢀꢁWKHꢀ%ORFNꢀ3RLQWHUꢀDVVXPHVꢀYDOXHVꢀEHWZHHQ

ꢅꢀWRꢀꢐꢀꢉWKHUHꢀDUHꢀꢏꢀEORFNVꢀLQꢀDꢀSDJHꢊꢁꢀ:KHQꢀWKH

%ORFNꢀ3RLQWHUꢀLVꢀHTXDOꢀWRꢀꢐꢂꢀWKHꢀ,QF%ORFNꢀFRPPDQG

SXWVꢀ WKLVꢀ SRLQWHUꢀ WRꢀ ꢅꢀ DQGꢀ LQFUHPHQWVꢀ WKHꢀ 3DJH

3RLQWHUꢁꢀ 7KHꢀ 3DJHꢀ 3RLQWHUꢂꢀ DIWHUꢀ SDJHꢀ ZULWLQJꢀ LV

FRPSOHWHGꢂꢀGRHV¶WꢀKDYHꢀWRꢀEHꢀLQFUHPHQWHGꢀLQꢀWKH

SURFHGXUHꢀDERYHꢀGHVFULEHGꢁ

:DUQLQJꢀꢁ$IWHUꢀHQWHULQJꢀWKHꢀ3URJUDPPLQJꢀ0RGHꢂ

WKHꢀFXUUHQWO\ꢀSRLQWHGꢀDGGUHVVꢀLVꢀWKHꢀ3DJHꢀꢋꢏꢂꢀ%ORFN

ꢇꢂꢀE\WHꢀꢅꢀꢉ/RFNꢀ%\WHꢊꢁ

The list of the available commands in

Programming Mode is showed in Table 4.2

ꢊꢇꢁꢇꢄꢅ5DQGRPꢅGDWDꢅZULWLQJꢇ A single byte can be

written in a specified memory location by using the

following procedure:

1. The Programming Mode is entered with the

sequence described in Section 4.2.1

ꢊꢇꢁꢇꢁꢅ)DVWꢅ3URJUDPPLQJꢅSURFHGXUHꢇ The

fastest way to program the device memory is the

use of the )DVW%ORFN:ULWH command. The following

procedure can be used to write the memory with a

new program and new data, starting from the first

memory location:

2. The 6HW3DJH command is sent, followed by

the page number where the data should be

written

1. The Programming Mode is entered with the

sequence described above

3. The %\WH:ULWH command is sent followed by

2. The memory is erased (all bits are put to 0)

with the *OREDO(UDVH command. The device

holds the SCL line low, releasing it after the

command is completed (about 2 ms). This

command also unlocks the device if locked.

two bytes

4. The first bytes that follows the ByteWrite com-

mand is the address inside the pointed page

where the data must be written.

5. The second byte is the data to be written

3. The )DVW%ORFN:ULWH command is sent and the

device acknowledges it

6. The device held the SCL line low until the data

is not stored in the memory (about 4.5 ms: 2

ms for erasing and 2.5 for writing)

4. The 32 bytes of data to be written in the first

memory Block are sent in a sequence. The

device acknowledges each of them

34/123

67ꢀꢁ)ꢀꢂꢂꢃ)ꢀꢂꢄ

A similar procedure can be used to write a single

block:

1. The 6HW3DJH command is sent, followed by

the page number where the data should be

written

The commands ByteErase and BlockErase, used

instead of ByteWrite and BlockWrite, erase (put all

bit to 0) the specified memory location or block.

ꢊꢇꢁꢇꢊꢅ2SWLRQꢅ%\WHVꢅ3URJUDPPLQJꢇ The Option

Byte addresses cannot be accessed with a

sequential procedure like the one described in

Section 4.2.2. Actually, the pointers are

automatically incremented up to the last block or

address in page 31. A further increment sets all the

pointers to 0.

The Option Byte addresses (located at page 48,

block 0, addresses 0-7) must be accessed with a

direct addressing procedure as the one described

in Section 4.2.3.

If the Fast Programming procedure is used, it must

be followed by a Random Block Writing procedure

to program the Option Bytes. The other 24 bytes of

the block can be written with dummy or user

values. The blocks 0, 1, 2 and 3 of Page 48 can be

used for writing data as well (see Section 4.5) and

for locking the device (see Section 4.4).

2. The ,QF%ORFN command is sent as many times

as the block number inside the page (for ex-

ample: to address the block 3 the ,QF%ORFN

must be sent 3 times)

3. The %ORFN:ULWH command is sent followed by

the 32 data bytes to be written.

4. After the 32th byte is sent, the device holds

the SCL line low until all the data are not

stored in the memory (about 4.5 ms: 2 ms for

erasing and 2.5 for writing: the same time for

a single byte)

The procedures described previously can be

repeated as many time as needed, without exiting

from Programming Mode or re-sending the Slave

Address again.

)LJXUHꢅꢊꢇꢁꢅꢅ3URJUDPPLQJꢅ3URFHGXUHV

)DVWꢅ3URJUDPPLQJꢅ3URFHGXUH

S

10100000

A

00000000

A

GlobalErase

A

FastBlockWrite

A

Data0

A

.....

..... Data31

A

IncBlock

A

FastBlockWrite

A

..... Data31

..... ..... Data31

A

P

5DQGRPꢅ%\WHꢅ:ULWLQJꢅ3URFHGXUH

..... SetPage

A

Page Address

A

ByteWrite

IncBlock

A

Byte Address

A

Data

A

Command .....

5DQGRPꢅ%ORFNꢅ:ULWLQJꢅ3URFHGXUH

..... SetPage

A

Page Address

A

..... IncBlock

A

BlockWrite

A

Data0

A

.....

..... Data31

A

Command .....

2SWLRQꢅ%\WHꢅ:ULWLQJꢅ3URFHGXUH

..... SetPage

A

00110000

A

BlockWrite

A

Option Byte 0

A

..... Option Byte 7

A

.....

..... Dummy 0

A

..... Dummy 23

A

P

S=Start, P=Stop, A=Acknowledge, NA=Non-acknowledge

From Slave to Master From Master to Slave

35/123

67ꢀꢁ)ꢀꢂꢂꢃ)ꢀꢂꢄ

)LJXUHꢅꢊꢇꢄꢅꢅ5HDGLQJꢅDQGꢅ(UDVLQJꢅ3URFHGXUHV

)DVWꢅ5HDGLQJꢅ3URFHGXUH

S

10100000

A

00000000

A

ReadData

A

P

S

10100001

A

Data read NA

P

.....

S

10100000

A

ReadData

A

P

S

10100001

A

Data read NA

P

..... Data read NA P

5DQGRPꢅ%\WHꢅ5HDGLQJꢅ3URFHGXUH

..... SetPage

A

Page Address

A

ByteRead

A

Byte Address

A

P

S

10100001

A

.....

..... Data read NA

P

S

10100000

A

Command .....

%\WHꢅ(UDVLQJꢅ3URFHGXUH

..... SetPage

A

Page Address

A

ByteErase

BlockErase

A

Byte Address

A

Command .....

%ORFNꢅ(UDVLQJꢅ3URFHGXUH

..... SetPage

A

Page Address

A

Block Address (*)

A

Command .....

(*) Block address is specified by the 3 most significative bits of the whole given address (less significative bits are don’t care)

S=Start, P=Stop, A=Acknowledge, NA=Non-acknowledge

From Slave to Master

From Master to Slave

ꢊꢇꢄꢅ0HPRU\ꢅ9HULI\

To verify the memory contents or just to read part

of data stored in memory, the %\WH5HDG and the

5HDG'DWD command can be used. The first

instruction needs the specification of the address;

the second one allows the sequential reading of

consecutive memory locations.

Since the device is “Slave” for the I²C protocol,

after receiving a command for reading, it must be

configured as Slave Transmitter to send the data.

In order to do so, the Slave Address (1010000)

must be sent again with the R/W byte set to 1, as

stated by the communication protocol.

5. The Slave Address with the R/W byte set to 1

(10100001) is sent. The device receives the

Slave Address and acknowledges it.

6. The device sends the data to be read in the

serial data line SDA. The current absolute ad-

dress is post-incremented.

7. The Master device doesn’t send the acknowl-

edge and generates a stop condition.

8. To read the next data, the Master generates a

Start condition followed by the Slave Address

with the R/W bit set to 0 (10100000). The de-

vice receives the Slave Address and acknowl-

edges it.

ꢊꢇꢄꢇꢆꢅ)DVWꢅUHDGꢅSURFHGXUHꢇ The memory can be

read sequentially by using the following procedure:

1. The Programming mode is entered with the

sequence described in Section 4.2.1

9. The sequence restarts from point 3 until there

is data to be read.

2. The pointers address the memory location 0

5HPDUNꢀꢁ IRUꢀ WKHꢀ VDPHꢀ UHDVRQVꢀ H[SODLQHGꢀ LQ

6HFWLRQꢀꢋꢁꢄꢁꢋꢀWKHꢀ2SWLRQꢀ%\WHVꢀFDQQRWꢀEHꢀUHDGꢀZLWK

WKLVꢀ SURFHGXUHꢎꢀ WKH\ꢀ FDQꢀ EHꢀ UHDGꢀ ZLWKꢀ Dꢀ GLUHFW

DGGUHVVLQJꢀSURFHGXUHꢀDVꢀWKHꢀRQHꢀH[SODLQHGꢀLQꢀWKH

QH[WꢀVHFWLRQꢁꢀ

3. The 5HDG'DWDꢀcommand is sent and the de-

vice acknowledges it.

4. The Master generates a Stop condition fol-

lowed by a Start condition

36/123

67ꢀꢁ)ꢀꢂꢂꢃ)ꢀꢂꢄ

ꢊꢇꢄꢇꢁꢅ5DQGRPꢅGDWDꢅUHDGLQJꢇ To read a specified

memory location, the following procedure should

be used:

1. The Programming mode is entered with the

sequence described in Section 4.2.1

ꢊꢇꢊꢅ0HPRU\ꢅ/RFN

The Program/Data Memory space can be locked to

inhibit the reading of contents and protect the

intellectual property.

To lock the device, the user must set all the bit of

the Lock Byte to ‘1’. The Lock Byte is located on

Page 48 (030h), Block 3, byte 0 inside the block i.e.

byte 96 (060h) inside the page.

After writing 255 (0FFh) into the Lock Byte, with the

procedure described in the Section 4.2.3, the

memory is locked and the only command allowed

are the following:

2. The 6HW3DJH command is sent, followed to

the page number where the data to be read is

located

3. The %\WH5HDG command is sent, followed by

an address inside the page

4. The Master generates a Stop condition fol-

lowed by a Start condition

– *OREDO(UDVH: this command, writing ‘0’ in all the

memory, also unlock the device.

5. The Slave Address with the R/W byte set to 1

(10100001) is sent. The device receives the

Slave Address and acknowledges it.

– 5HDG'DWD: the only block that can be read is the

Block 3 in Page 48 (030h); this allows the read-

ing of the Lock Byte and the ID Code locations

(see Section 4.5).

– 5HDG6WDWXV: this command allows the detection

of an error condition in Programming mode op-

eration (see Section 4.6). It can also be used to

check if the device is locked. The most significa-

tive bit return the Lock Bit (0=unlocked,

1=locked).

6. The device sends the data to be read in the

serial data line SDA. The address pointer is

incremented.

7. The Master device doesn’t send the acknowl-

edge and generates a stop condition.

8. To send the next command, the Master

should generate a Start condition followed by

the Slave Address with the R/W byte set to 0

(10100000).

5HPDUNꢀꢁWKHꢀ/RFNꢀ%\WHꢀLVꢀFKHFNHGꢀZKHQꢀHQWHULQJ

WKHꢀ 3URJUDPPLQJꢀ 0RGHꢁꢀ )RUꢀ WKLVꢀ UHDVRQꢀ DIWHU

ZULWLQJꢀ WKHꢀ /RFNꢀ %\WHꢂꢀ DOOꢀ WKHꢀ FRPPDQGVꢀ FDQꢀ EH

FDUULHGꢀRXWꢀXQWLOꢀWKHꢀ3URJUDPPLQJꢀPRGHꢀLVꢀH[LWHGꢁ

)LJXUHꢅꢊꢇꢊꢅꢅ'HYLFHꢅ/RFNꢅ3URFHGXUH

'HYLFHꢅ/RFNꢅ3URFHGXUH

..... SetPage

A

00110000

A

ByteWrite

A

01100000

A

11111111

A

Command .....

'HYLFHꢅ/RFNꢅDQGꢅ,'ꢅ&RGHꢅ:ULWLQJꢅ3URFHGXUH

..... SetPage

A

00110000

A

IncBlock

A

IncBlock

A

IncBlock

A

BlockWrite

A

.....

..... 11111111

A

ID Code 1

A

ID Code 2

A

..... ID Code 31

A

Command .....

'HYLFHꢅ/RFNꢅ5HDGLQJꢅ3URFHGXUH

..... ReadStatus

A

P

S

10100001

A

Status Byte (*) NA

P

S

10100000

A

Command .....

(*) The most significative bit return the Lock Bit (0=unlocked, 1=locked)

S=Start, P=Stop, A=Acknowledge, NA=Non-acknowledge

From Slave to Master

From Master to Slave

37/123

67ꢀꢁ)ꢀꢂꢂꢃ)ꢀꢂꢄ

)LJXUHꢅꢊꢇꢀꢅꢅ(UURUꢅ+DQGOLQJꢅ3URFHGXUH

Wrong command/data case handling:

Wrong Command/Data

A

Command/Data NA

P

S

10100000

A

ReadStatus A P S .....

..... 10100001

A

Status Byte NA

P

S=Start, P=Stop, A=Acknowledge, NA=Non-acknowledge

From Slave to Master

From Master to Slave

When the device is locked, if memory reading is

attempted, with the exception of the Lock Byte and

ID Code block, the device returns no data and an

error sequence. If memory writing is attempted in

any memory location, the device doesn’t carry out

the command and returns an error sequence.

To unlock the device the *OREDO(UDVH command

must be executed before any writing or reading

command.

ꢊꢇꢋꢅ(UURUꢅFDVHV

If a wrong command or data is sent to the device,

it generates an error condition by not sending the

acknowledge after the first successive data or

command. Figure 4.5 shows the error sequence.

The error case can be handled by using the

5HDG6WDWXV command. This command can be sent

after the error condition is detected; the device

returns a Status Byte containing the error code.

The 5HDG6WDWXV command sequence is showed in

Figure 4.5. The list of the error codes is illustrated

in Table 4.3.

ꢊꢇꢀꢅ,'ꢅ&RGH

Block 3 on Page 48 (030h) can also be read if the

device is locked. The first byte of the block is the

Lock Byte, the following 21 locations (bytes 1-21)

are available to the user for writing data, as for

example identification codes to distinguish the

firmware version loaded in the device.

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H[HFXWLRQꢀ RUꢀDIWHUꢀDQ\ꢀHUURUꢂꢀ WKHꢀ 6WDUWꢀ6HTXHQFH

PXVWꢀ EHꢀ FDUULHGꢀ RXWꢀ EHIRUHꢀ VHQGLQJꢀ Dꢀ QHZ

FRPPDQGꢁ

The Most Significative Bit of the error codes

indicates (when set to ‘1’) that the memory is

locked. When a command, that is not allowed

when the memory is locked, is sent, the “1RW

$OORZHG´ꢀcode is sent. If another code is sent with

the MSB to ‘1’ it indicates that the error condition is

not caused by the memory lock, but by the event

related with the code sent.

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ꢉE\WHVꢀꢄꢄꢀWRꢀꢇꢍꢊꢂꢀEHFDXVHꢀWKH\ꢀDUHꢀꢀUHVHUYHGꢁ

The ID Code must be written before locking the

device: after the device is locked it can only be

read. The blocks 0, 1 and 2 on Page 48 can be

also be used for writing data, but they cannot be

accessed when the device is locked.

:DUQLQJꢀꢁZKHQꢀWKHꢀGDWDꢀZULWLQJꢀLQWRꢀDꢀQRQꢀH[LVWLQJ

ORFDWLRQꢀ LVꢀ DWWHPSWHGꢂꢀ QRꢀ HUURUꢀ FRQGLWLRQꢀ LV

JHQHUDWHGꢁꢀ7KHꢀXVHUꢀPXVWꢀWDNHꢀFDUHꢀLQꢀVSHFLI\LQJ

WKHꢀFRUUHFWꢀSDJHꢀDGGUHVVꢁ

1RWHꢀꢁWKHꢀ,'ꢀ&RGHꢀFDQQRWꢀEHꢀPRGLILHGꢀLIꢀWKHꢀGHYLFH

LVꢀORFNHGꢎꢀLWꢀFDQꢀRQO\ꢀEHꢀUHDGꢁ

7DEOHꢅꢊꢇꢄꢅ (UURUꢅFRGHV

Device Locked

Wrong Command

Not Allowed

xyyyyyyy

x0000101

x0000110

x0010000

x=lock bit (1=device locked), yyyyyyy=error code

The Master sent a wrong command code

A command not allowed when the device is locked has been sent

A code different form the Programming mode code (00000000) has been sent

Wrong Mode

38/123

67ꢀꢁ)ꢀꢂꢂꢃ)ꢀꢂꢄ

ꢊꢇꢈꢅ,Qꢓ6LWXꢅ3URJUDPPLQJꢅꢐ,63ꢑ

The Program/Data Memory can be programmed

using the ISP mode. This mode allows the device

to be programmed when it is mounted in the user

application board.

This feature can be implemented by adding a

minimum number of components and board

impact.

The programming procedures and pins used are

identical to the ones described before for the

standard Programming Mode. All the features

previously described in this chapter are applicable

in ISP mode.

If RESET, SCL and SDA pins are used in the user

application board for other purposes, it is

recommended to provide an adequate isolation to

avoid a conflict when the other devices force the

signal level.

ꢊꢇꢏꢇꢁꢅ%ORFNꢅZULWHꢇ This procedure allows the

writing of 32 bytes in parallel. These bytes should

belong to the same block.

Before the writing in the Program/Data memory,

data must be buffered in the Register File in the

first 32 locations (0-31, 00h-020h) by using the

normal instructions to load the Register File

locations.

Then the data writing starts by using the BLKSET

instruction. The destination block is addressed by

specifying the memory page with the PGSET or

PGSETR instruction before to start the writing; the

block inside the page is addressed with the

argument of the BLKSET instruction.

Example:

PGSET 5

BLKSET 4

The ISP can be applied by using the standard tools

for the device programming. The ST52F500/F503

Starter Kit supplies a cable to perform the ISP. The

user application board should supply a suited

connector type for the cable (see Starter Kit User

Manual).

This instruction sequence writes the contents of

the first 32 bytes of the Register File in the

locations 1408-1439 (0580h-059Fh).

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WKHꢀFRUUHFWꢀSDJHꢀDQGꢀEORFNꢎꢀWKHꢀDGGUHVVLQJꢀRIꢀDQ

QRWꢀH[LVWLQJꢀEORFNꢀFDQꢀFDXVHꢀWKHꢀXQZDQWHGꢀZULWLQJ

RIꢀDꢀGLIIHUHQWꢀEORFNꢁ

As soon as the BLKSET instruction is executed,

the data writing starts and is performed in about

4.5 ms.

This procedure may also be used to write few data,

taking in account that all the 32 byte are written in

the block anyway.

ꢊꢇꢏꢅ,Qꢓ$SSOLFDWLRQꢅ3URJUDPPLQJꢅꢐ,$3ꢑ

The In Application Programming Mode (IAP)

allows the writing of user data in the Flash and

EEPROM memories when the user program is

running.

There are two ways to write data in IAP mode:

single byte write and Block write. Both procedures

take about 4.5 ms to complete the writing: the

Block write allows the writing of 32 byte in parallel.

ꢊꢇꢏꢇꢄꢅ0HPRU\ꢅ&RUUXSWLRQꢅ3UHYHQWLRQꢇ

The user can protect some pages (or all the

memory) from unintentional writings. The only

constraint is that the protected pages must be

consecutive.

Two Option Bytes allow the specification of the

page to be protected: PG_LOCK (Option Byte 5)

and PG_UNLOCK (Option Byte 6). PG_LOCK is

used to specify the first protected page;

PG_UNLOCK is used to specify the first page not

protected after the protected ones. The pages

between the two addresses are protected.

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$%57ꢀLQꢀWKHꢀ,$3B65ꢀ,QSXWꢀUHJLVWHUꢀVLJQDOVꢀWKDWꢀWKH

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WKHꢀ LQWHUUXSWVꢀ ꢉ8'*,ꢀ LQVWUXFWLRQꢊꢀ EHIRUHꢀ VWDUWLQJ

,$3ꢀGDWDꢀZULWLQJꢁ

When writing in a protected page is attempted, the

procedure is aborted and the bit PRTCD of

IAP_SR Input register is set.

If the PG_LOCK and PG_UNLOCK have the same

value, no page is protected.

In Programming Mode the protection is not

considered and the pages can be written unless

the device is locked.

ꢊꢇꢏꢇꢆꢅ6LQJOHꢅE\WHꢅZULWHꢇ Writing of a single byte in

the Non-Volatile Program/Data memory is

performed by using the LDER instructions (both

direct and indirect addressing). The memory page

should be indicated before the LDER instruction

with the PGSET or PGSETR instruction. The byte

address inside the page is specified by the LDER

instruction itself.

As soon as the instruction is executed, the data

writing starts and is performed in about 4.5 ms.

39/123

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)LUVWꢅ3URWHFWHGꢅ3DJHꢅꢐ3*B/2&ꢌꢑ

,$3ꢅ6WDWXVꢅ5HJLVWHUꢅꢐ,$3B65ꢑ

Option Byte 5 (05h)

Input Register 40 (028h) Read only

7

0

7

0

LCK7

LCK6

LCK5

LCK4

LCK3

LCK2

LCK1

LCK0

-

PRTCD ABRT

Bit 7-2: Not Usedꢅ

Bit 1: 357&'ꢅPage Protected

Bit 7-0: /&ꢌꢈꢓꢂꢅFirst Page write protected

In this register the address of first page to be

protected in writing is specified. The pages

following this one are protected up to the page

specified by the PG_UNLOCK Option Byte (not

included among the protected ones).

0: The writing has been completed

1: The writing has been aborted because the

page is protected.

Bit 0: $%57ꢅWriting operation aborted

0: The writing has been completed

)LUVWꢅ3DJHꢅQRWꢅ3URWHFWHGꢅꢐ3*B81/2&ꢌꢑ

Option Byte 6 (06h)

1: The writing has been aborted because an

interrupt or another unspecified cause

occurred.

7

0

The ABRT and PRTCD bits are reset after the next

successful data writing in the Flash of EEPROM

memory.

UNLCK7 UNLCK6 UNLCK5 UNLCK4 UNLCK3 UNLCK2 UNLCK1 UNLCK0

Bit 7-0: 81/&ꢌꢈꢓꢂꢅFirst Page not write protected

In this register the address of first page not write

protected after the protected ones is specified. The

pages following this one aren’t protected.

40/123

67ꢀꢁ)ꢀꢂꢂꢃ)ꢀꢂꢄ

ꢀꢅꢅ,17(558376

)LJXUHꢅꢀꢇꢆꢅꢅꢅ,QWHUUXSWꢅ)ORZ

The Control Unit (CU) responds to peripheral

events and external events through its interrupt

channels.

When such events occur, if the related interrupt is

not masked and doesn’t have a priority order, the

current program execution can be suspended to

allow the CU to execute a specific response

routine.

NORMAL

PROGRAM

FLOW

INTERRUPT

SERVICE

ROUTINE

INTERRUPT

Each interrupt is associated with an interrupt

vector that contains the memory address of the

related interrupt service routine. Each vector is

located in the Program/Data Memory space at a

fixed address (see Figure 3.2 Program/Data

Memory Organization).

RETI

INSTRUCTION

ꢀꢇꢆꢅꢅ,QWHUUXSWꢅ3URFHVVLQJ

If interrupts are pending at the end of an arithmetic

or logic instruction, the interrupt with the highest

priority is acknowledged. When the interrupt is

acknowledged the flags and the current PC are

saved in the stacks and the associated Interrupt

routine is executed. The start address of this

routine (Interrupt Vector) is located in two bytes of

the Program/Data Memory between address 3 and

32 (03h-020h). See Table 5.1 for the list of the

Interrupt Vector addresses.

ꢀꢇꢁꢅꢅ*OREDOꢅ,QWHUUXSWꢅ5HTXHVWꢅ(QDEOLQJ

When an Interrupt occurs, it generates a Global

Interrupt Pending (GIP). After a GIP a Global

Interrupt Request (GIR) will be generated and

Interrupt Service Routine associated with the

interrupt with higher priority will start.

The Interrupt routine is performed as a normal

code. At the end of each instruction, the CU checks

if a higher priority interrupt has sent an interrupt

request. An Interrupt request with a higher priority

stops lower priority Interrupts. The Program

Counter and the flags are stored in their own

stacks.

With the instruction RETI (Return from Interrupt)

the flags and the Program Counter (PC) are

restored from the top of the stacks. These stacks

have already been described in Paragraph 3.4.

An Interrupt request cannot stop fuzzy rule

processing. The request is acknowledged only

after the end of a fuzzy rule or at the end of a logic

or arithmetic instruction, unless a Global Interrupt

Disable instruction has been executed before.

In order to avoid possible conflicts between the

interrupt masking set in the main program, or

inside high level language compiler macros, the

GIP is put in AND through the User Global Interrupt

Mask or the Macro Global Interrupt Mask (see

Figure 5.2).

The UEGI/UDGI instruction switches the User

Global Interrupt Mask enabling/disabling the GIR

for the main program.

MEGI/MDGI instructions switch the Macro Global

Interrupt Mask on/off in order to ensure that the

macro will not be interrupted.

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UXQQLQJꢀLQVLGHꢀDQRWKHUꢀLQWHUUXSWꢀURXWLQHꢀDQꢀLQWHUUXSW

UHTXHVWꢀFDQꢀFDXVHꢀVLGHꢀHIIHFWVꢀLQꢀWKHꢀ&RQWUROꢀ8QLWꢁ

)RUꢀWKLVꢀUHDVRQꢂꢀLQꢀRUGHUꢀWRꢀXVHꢀDꢀ)X]]\ꢀIXQFWLRQ

LQVLGHꢀDQꢀLQWHUUXSWꢀURXWLQHꢂꢀWKHꢀXVHUꢀ0867ꢀLQFOXGH

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LQVWUXFWLRQꢀ DQGꢀ DQꢀ 8(*,ꢀ ꢉ0(*,ꢊꢀ LQVWUXFWLRQꢀ ꢉVHH

WKHꢀIROORZLQJꢀSDUDJUDSKVꢊꢂꢀLQꢀRUGHUꢀWRꢀGLVDEOHꢀWKH

LQWHUUXSWꢀUHTXHVWꢀGXULQJꢀWKHꢀH[HFXWLRQꢀRIꢀWKHꢀIX]]\

IXQFWLRQꢁꢁ

Global Interrupt

Pending

Request

User Global

Interrupt Mask

Macro Global

41/123

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ꢀꢇꢄꢅꢅ,QWHUUXSWꢅ6RXUFHV

ꢀꢇꢊꢅꢅ,QWHUUXSWꢅ0DVNDELOLW\ꢅDQGꢅ3ULRULW\ꢅ/HYHOV

ST52F500/F503 manages interrupt signals

generated by the internal peripherals or generated

by software by the TRAP instruction or coming

from the Port pins. There are two kinds of

interrupts coming from the Port pins: the NMI and

the Ports Interrupts.

NMI (Not Maskable Interrupt) is associated with pin

PA7 when it is configured as Alternate Function.

This interrupt source doesn’t have a configurable

level priority and cannot be masked. The fixed

priority level is lower than the software TRAP and

higher than all the other interrupts. The NMI can be

configured to be active on the rising or the falling

edge.

The Port Interrupts sources are connected with

Port A and Port B pins. The pins belonging to the

same Port are associated with the same interrupt

vector: there is one vector for Port A and one for

Port B. In order to use one port pin as interrupt, it

must be configured as an interrupt source (see I/O

Ports chapter). In this manner, up to 16 Port

Interrupt sources are available. By reading the Port

the sources that belong to the same Port can be

discriminated. The Port Interrupts can be

configured to be active on the rising or the falling

edge, by using the INT_POL register.

Interrupts can be masked by the corresponding

INT_MASK Configuration Register 0 (00h). An

interrupt is enabled when the mask bit is “1". Vice

versa, when the bit is “0”, the interrupt is masked

and the eventual requests are kept pending.

All the interrupts, with the exception of the NMI and

TRAP that have fixed level priority, have a

configurable priority level. The configuration of the

priority levels is completed by writing three

consecutive Configuration Registers: INT_PRL_L,

INT_PRL_M, INT_PRL_H, addresses from 2 to 4

(02h-04h). The 24 bits of these registers are

divided into 8 groups of three bits: each group is

associated with a priority level. The three bits of

each group are written with the code number

associated with the interrupt source. See Table 5.1

to know the codes.

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5HJLVWHUVꢀ PXVWꢀ EHꢀ SURJUDPPHGꢀ ZLWKꢀ GLIIHUHQW

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'XULQJꢀSURJUDPꢀH[HFXWLRQꢀWKHꢀLQWHUUXSWꢀSULRULW\ꢀFDQ

RQO\ꢀEHꢀPRGLILHGꢀZLWKLQꢀWKHꢀ0DLQꢀ3URJUDPꢎꢀLWꢀFDQQRW

EHꢀFKDQJHGꢀZLWKLQꢀDQꢀLQWHUUXSWꢀVHUYLFHꢀURXWLQHꢁꢀ,Q

DGGLWLRQꢀWKHꢀLQWHUUXSWVꢀPXVWꢀEHꢀGLVDEOHGꢀE\ꢀPHDQV

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WKHꢀLQWHUUXSWVꢀPXVWꢀEHꢀGLVDEOHGꢀEHIRUHꢀWKHꢀSULRULW\

UHJLVWHUꢀFRQILJXUDWLRQꢁ

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SRODULW\ꢀDQꢀLQWHUUXSWꢀUHTXHVWꢀLVꢀJHQHUDWHGꢁ

All the interrupt sources are filtered, in order to

avoid false interrupt requests caused by glitches.

The Trap instruction is something between a

interrupt and a call: it generated an interrupt

request at top priority level and the control is

passed to the associated interrupt routine which

vector is located in the fixed addresses 31-32. This

routine cannot be interrupted and it is serviced

even if the interrupts are globally disabled.

ꢀꢇꢀꢅꢅ,QWHUUXSWꢅ5(6(7

When an interrupt is masked, all requests are not

acknowledged and remain pending. When the

pending interrupt is enabled it is immediately

serviced, if it has proper priority. This event may be

undesired; in order to avoid this a RINT instruction

may be inserted followed by the code number that

identifies the interrupt to reset the pending request.

The RINT instruction has no effect if the interrupt is

being serviced

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75$3ꢀWKHꢀIODJVꢀDUHꢀQRWꢀVWDFNHGꢁ

)LJXUHꢅꢀꢇꢄꢅꢅꢅ([DPSOHꢅRIꢅ,QWHUUXSWꢅ5HTXHVWV

See Table 5.1 to know the codes.

INT2 INT0 INT4

INT1

INT3

PRIORITY

LEVEL

0

1

2

3

4

5

6

INT0

INT1

INT2

INT3

INT4

MAIN PROGRAM

42/123

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ꢀꢇꢋꢅꢅ5HJLVWHUꢅ'HVFULSWLRQ

Bit 7-5: Not Usedꢅ

,QWHUUXSWꢅ0DVNꢅ5HJLVWHUꢅꢐ,17B0$6ꢌꢑ

Configuration Register 0 (00h) Read/Write

Reset Value: 0000 0000 (00h)

Bit 4-3: See Timer 0 Registers Description

Bit 2: 32/3%ꢅPort B Interrupt Polarity

0: The Port B interrupt is triggered on the

rising edge of the applied external signal.

1: The Port B interrupt is triggered on the

falling edge of the applied external signal.

7

0

-

MSKPB MSKPA MSKI2C MSKSPI

-

MSKT1 MSKT0

Bit 1: 32/3$ꢅPort A Interrupt Polarity

Bit 7: 06ꢌ3%ꢅInterrupt Mask Port B

0: Port B interrupt masked

0: The Port A interrupt is triggered on the

rising edge of the applied external signal.

1: The Port A interrupt is triggered on the

falling edge of the applied external signal.

1: Port B interrupt enabled

Bit 6: 06ꢌ3$ꢅInterrupt Mask Port A

0: Port A interrupt masked

Bit 0: 32/10,ꢅNon Maskable Interrupt Polarity

1: Port A interrupt enabled

0: The NMI is triggered on the rising edge of

the applied external signal.

1: The NMI is triggered on the falling edge of

the applied external signal.

Bit 5: 06ꢌ,ꢁ&ꢅInterrupt Mask I²C Interface

0: I²C Interface interrupt masked

1: I²C Interface interrupt enabled

/RZꢅ3ULRULW\ꢅ5HJLVWHUꢅꢐ,17B35/B/ꢑ

Configuration Register 2 (02h) Read/Write

Reset Value: 1111 1010 (FAh)

Bit 4: 06ꢌ63,ꢅInterrupt Mask SPI

0: SPI interrupt masked

1: SPI interrupt enabled

7

0

Bit 3: Not used

PRL23 PRL22 PRL21 PRL20 PRL19 PRL18 PRL17 PRL16

Bit 2: 06ꢌ7ꢆꢅInterrupt Mask PWM/Timer 1

0: Pwm/Timer 1 interrupt masked

1: Pwm/Timer 1 interrupt enabled

0HGLXPꢅ3ULRULW\ꢅ5HJLVWHUꢅꢐ,17B35/B0ꢑ

Configuration Register 3 (03h) Read/Write

Reset Value: 1100 0110 (0C6h)

Bit 1: 06ꢌ7ꢂꢅInterrupt Mask Pwm/Timer 0

0: Pwm/Timer 0 interrupt masked

1: Pwm/Timer 0 interrupt enabled

7

0

PRL15 PRL14 PRL13 PRL12 PRL11 PRL10

PRL9

PRL8

Bit 0: Not used

+LJKꢅ3ULRULW\ꢅ5HJLVWHUꢅꢐ,17B35/B+ꢑ

Configuration Register 4 (04h) Read/Write

Reset Value: 1000 1000 (088h)

,QWHUUXSWꢅ3RODULW\ꢅ5HJLVWHUꢅꢐ,17B32/ꢑ

Configuration Register 1 (01h) Read/Write

Reset Value: 0000 0000 (00h)

7

0

7

0

PRL7

PRL6

PRL5

PRL4

PRL3

PRL2

PRL1

PRL0

-

RESPOL STRPOL POLPB POLPA POLNMI

43/123

67ꢀꢁ)ꢀꢂꢂꢃ)ꢀꢂꢄ

These three register are used to configure the

priority level of each interrupt source. The 24 bits

of these registers (PRL23-PRL0) are divided into 8

groups of three bits: each group is associated with

a priority level (from level 1, the highest, to level 8,

the lowest: level 0 is fixed for the NMI that can be

interrupted only by the TRAP) . The three bits of

each group are written with the code number

associated with the interrupt source (see Table

5.1).

35/ꢆꢆꢓ35/ꢉ:Interrupt priority level 4

35/ꢆꢊꢓ35/ꢆꢁ: Interrupt priority level 5

35/ꢆꢈꢓ35/ꢆꢀ: Interrupt priority level 6

35/ꢁꢂꢓ35/ꢆꢏ: Interrupt prioritylevel 7

35/ꢁꢄꢓ35/ꢁꢆ: Interrupt priority level 8 (lowest)

Example: writing the code 110 into PRL8-PRL6

bits the priority level 3 is assigned to the Port A

Interrupt.

35/ꢁꢓ35/ꢂ: Interrupt priority level 1 (highest)

35/ꢀꢓ35/ꢄ: Interrupt priority level 2

35/ꢏꢓ35/ꢋ: Interrupt priority level 3

:DUQLQJꢀꢁWKHꢀ3ULRULW\ꢀ/HYHOꢀFRQILJXUDWLRQꢀUHJLVWHUV

PXVWꢀEHꢀDOZD\VꢀFRQILJXUHGꢀZLWKꢀFRQVLVWHQWꢀYDOXHVꢁ

7DEOHꢅꢀꢇꢆꢅ ,QWHUUXSWꢅVRXUFHVꢅSDUDPHWKHUV

PWM/Timer 0

PWM/Timer 1

SPI

Programmable

Fixed

001

010

100

101

110

111

-

1

2

4

5

6

7

8

-

Yes

No

6-8 (06h-08h)

9-11 (09h-0Bh)

15-17 (0Fh-011h)

18-20 (012h-014h)

21-23 (015h-017h)

24-26 (018h-01Ah)

27-29 (01Bh-01Dh)

30-32 (01Eh-020h)

2

I C Interface

Port A

Port B

NMI

TRAP

Fixed to highest

-

No

44/123

67ꢀꢁ)ꢀꢂꢂꢃ)ꢀꢂꢄ

ꢋꢅꢅ&/2&ꢌꢍꢅ5(6(7ꢅꢎꢅ32:(5ꢅ6$9,1*ꢅ02'(6

ꢋꢇꢆꢅꢅ&ORFNꢅ

The ST52F500/F503 Clock Generator module

generates the internal clock for the internal Control

Unit, ALU and on-chip peripherals. The Clock is

designed to require a minimum of external

components.

The ST52F500/F503 oscillator circuit generates an

internal clock signal with the same period and

phase as the OSCIN input pin. The maximum

frequency allowed is 20 MHz.

When the external oscillator is used, the loop gain

can be adapted to the various frequencies values

by configuring the three bits of the Option Byte 1

CLK_SET (see Register Decription, Table 6.1).

ST52F500/F503 devices supply the internal

oscillator in four clock modes:

I External oscillator

I External clock

I Internal clock

When an external clock is used, it must be

connected to the pin OSCIN while OSCOUT can

be floating. In this case, Option Byte 1 bits must be

written with 0 (000).

The crystal oscillator start-up time is a function of

many variables: crystal parameters (especially

R_s), oscillator load capacitance (CL), IC

parameters, environment temperature and supply

voltage.

The device always starts in internal clock mode,

excluding any external clock source. After the

start-up phase the clock is configured according to

the user definition programmed in the Option Byte

0 (OSC_CR). The internal clock generator can

supply an internal clock signal with a fixed

frequency of 10 MHz ± 1%, without the need for

external components. In order to obtain the

maximum accuracy, the frequency can be

calibrated by configuring the related Option byte 2

(OSC_SET).

The crystal or ceramic leads and circuit

connections must be as short as possible. Typical

values for CL1, CL2 are 10pF for a 20 MHz crystal.

Figure 6.1 illustrates the possible connections.

The clock signal generates two internal clock

signals: one for the CPU and one for the

peripherals. The CPU clock frequency can be

reduced, in order to decrease current consuption,

by setting the CPU_CLK Configuration Register 46

(02Eh). The CPU clock can be reduced up to 64

times (see Register Description).

The external oscillator mode uses a quartz crystal

or a ceramic resonator connected to OSCin and

OSCout as illustrated in Figure 6.1. This figure also

illustrates the connection of an external clock.

)LJXUHꢅꢋꢇꢆꢅꢅꢅ2VFLOODWRUꢅ&RQQHFWLRQV

CRYSTAL CLOCK

EXTERNAL CLOCK

ST FIVE

OSCin

OSCout

OSCin

OSCout

Cl1

10pF

Cl2

10pF

CLOCK

INPUT

45/123

67ꢀꢁ)ꢀꢂꢂꢃ)ꢀꢂꢄ

ꢋꢇꢁꢅꢅ5HVHW

Four Reset sources are available:

I RESET pin (external source)

After this level has been reached, the internal

oscillator (10 MHZ) is started and a delay period of

4096 clock cycles is initiated, in order to allow the

oscillator to stabilize and to ensure that recovery

has taken place from the Reset state.

If the device has been configured to work with the

internal clock, the user program starts, otherwise

the Option Byte 7 (WAKEUP) is read and another

count starts before running the user program. The

duration of the count depends on the contents of

the Option Byte 7 (WAKEUP), that works as a

prescaler, according to the follwing formula:

I WATCHDOG (internal source)

I POWER ON Reset (Internal source)

I PLVD Reset (Internal source)

When a Reset event occurs, the user program

restarts from the beginning.

ꢋꢇꢁꢇꢆꢅꢅ([WHUQDOꢅ5HVHWꢇ Reset is an input pin. An

internal reset does not affect this pin. A Reset

signal originated by external sources is

recognized immediately. The RESET pin may be

used to ensure Vdd has risen to a point where the

ICU can operate correctly before the user program

is run. Reset must be set to Vdd in working mode.

'HOD\ = 4096 × (:$ꢀ(83 + 1) × 7FON

This delay has been introduced in order to ensure

that the oscillator has become stable after its

restart.

An internal Pull up resistor guarantees that the

RESET pin is at level “1” when no HALT or Power-

On events occur. (see Table 16.9) and Table 16.15

for more details.

If the Reset is generated by the PLVD or the

Watchdog, the oscillator is not turned off; for this

reason the CPU is then restarted immediately,

without the delay.

After a RESET procedure is completed, the core

reads the instruction stored in the first 3 bytes of

the Program/Data Memory, which contains a

JUMP instruction to the first instruction of the user

program. The Assembler tool automatically

generates this Jump instruction with the first

instruction address.

ꢋꢇꢁꢇꢁꢅꢅ5HVHWꢅ3URFHGXUHVꢇ After the Reset pin is

set to Vdd or following a Power-On Reset event,

the device is not started until the external supply

voltage has reached a threshold level (typical

value Vdd=2.6 V, see electrical characteristics).

)LJXUHꢅꢋꢇꢁꢅꢅ5HVHWꢅ%ORFNꢅ'LDJUDP

CKMOD1:0

4096 x TCLK

(WAKEUP+1) x

4096 x TCLK

TCLK = Internal Clock period (100 ns)

CKMOD1:0 = see Option Byte 0 (OSC_CR)

WAKEUP = see Option Byte 7 (WAKEUP)

46/123

67ꢀꢁ)ꢀꢂꢂꢃ)ꢀꢂꢄ

ꢋꢇꢄꢅꢅ3URJUDPPDEOHꢅ/RZꢅ9ROWDJHꢅ'HWHFWRUꢅ

watchdog system is enabled, it will be skipped

without modifying the normal CPU operations.

The on-chip Programmable Low Voltage Detector

(PLVD) circuit prevents the processor from falling

into an unpredictable status if the power supply

drops below a certain level.

When Vdd drops below the detection level, the

PLVD causes an internal processor Reset that

remains active as long as Vdd remains below the

trigger level.

The PLVD resets the entire device except the

Power-on Detector and the PLVD itself.

The PLVD can be enabled/disabled at reset by

setting the Option Byte 3 (PLVD_CR) bits.

The ICU can exit Halt mode upon reception of an

NMI, a Port Interrupt or a Reset. The internal

oscillator (10 MHZ) is started and a delay period of

4096 clock cycles is initiated, in order to allow the

oscillator to stabilize and to ensure that recovery

has taken place from the Reset state.

If the device has been configured to work with the

internal clock, the user program is started,

otherwise the Option Byte 7 (WAKEUP) is read

and another count is started before running the

user program. The count duration depends on the

contents of the Option Byte 7 (WAKEUP), that

works as prescaler, according to the follwing

formula:

When Vdd increases above the Trigger Level, the

PLVD reset is deactivated and the user program is

started from the beginning.

The detection levels are programmable by means

of the Option Byte 3 (PLVD_CR). There are three

levels for the PLVD falling voltages (2.9V, 3.4V,

3.9V) and for rising voltages (3.1V, 3.65V, 4.2V).

The hysteresis for each level are respectively 200

mV, 250 mV and 300 mV.

'HOD\ = 4096 × (:$ꢀ(83 + 1) × 7FON

This delay has been introduced in ordet to ensure

that the oscillator has become stable after it is

restarted.

After the start up delay, by exiting with the NMI or

a Port interrupt, the CPU restarts operations by

serving the associated interrupt routine.

The PLVD circuit will only detect a drop if Vdd

voltage stays below the safe threshold for at least

5µs before activation/deactivation of the PLVD in

order to filter voltage spikes.

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SULRULW\ꢁLQWHUUXSWꢁURXWLQHꢂ

5HPDUNꢀꢁWKHꢀ3/9'ꢀIXQFWLRQꢀLVQ¶WꢀDFWLYHꢀZKHQꢀLWꢀLV

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9GGꢀYROWDJHꢀVWD\VꢀEHORZꢀꢀWKHꢀWKUHVKROGꢀRIꢀ3RZHU

2Qꢀ5HVHWꢁ

)LJXUHꢅꢋꢇꢄꢅꢅꢅ:$,7ꢅ)ORZꢅ&KDUW

WAIT ISTRUCTION

ꢋꢇꢊꢅꢅ3RZHUꢅ6DYLQJꢅPRGHV

There are two types of Power Saving modes:

WAIT and HALT mode. These conditions may be

entered by using the WAIT or HALT instructions.

OSCILLATOR

ON

PERIPHERALS CLOCK

CPU CLOCK

ON

OFF

ENAB.

ꢋꢇꢊꢇꢆꢅꢅ:DLWꢅ0RGHꢇ Wait mode places the ICU in a

low power consumption status by stopping the

CPU. All peripherals and the watchdog remain

active. During WAIT mode the Interrupts are

enabled. The ICU remains in Wait mode until an

Interrupt or a RESET occurs, whereupon the

Program Counter jumps to the interrupt service

routine or, if a Reset occurs, to the beginning of the

user program.

INTERRUPTS

YES

NO

RESET

NO

CPU CLOCK

ON

INTERRUPT

PROGRAM COUNTER RESET

ꢋꢇꢊꢇꢁꢅꢅ+DOWꢅ0RGHꢇ Halt mode is the lowest ICU

power consumption mode, which is entered by

executing the HALT instruction. The internal

oscillator is turned off, causing all internal

processing to be terminated, including the

operations of the on-chip peripherals. Halt mode

cannot be used when the watchdog is enabled. If

the HALT instruction is executed while the

CPU CLOCK

ON

JUMP TO INT. ROUTINE

NORMAL PROGRAM FLOW

47/123

67ꢀꢁ)ꢀꢂꢂꢃ)ꢀꢂꢄ

)LJXUHꢅꢋꢇꢊꢅꢅꢅ+$/7ꢅ)ORZꢅ&KDUW

if the Port Interrupt is masked, the ICU exits from the

Halt mode and jumps to the lower priority interrupt routine.

48/123

67ꢀꢁ)ꢀꢂꢂꢃ)ꢀꢂꢄ

ꢋꢇꢀꢅ5HJLVWHUꢅ'HVFULSWLRQ

Bit 7-2: Not Usedꢅ

The following section describes the Register which

are used to configure the Clock, Reset and PLVD.

Bit 1: Must be set to 0

ꢋꢇꢀꢇꢆꢅ&RQILJXUDWLRQꢅ5HJLVWHUꢇ

Bit 0: &ꢌ02'ꢅ Clock Mode

0: Internal Oscillator

1: External Clock or quartz

&38ꢅ&ORFNꢅ3UHVFDOHUꢅꢐ&38B&/ꢌꢑ

Configuration Register 46 (02Eh) Read/Write

Reset Value: 0000 0000 (00h)

([WHUQDOꢅ&ORFNꢅ3DUDPHWHUVꢅꢐ&/ꢌB6(7ꢑ

Option Byte 1 (01h)

7

0

-

CPUCK5 CPUCK4 CPUCK3 CPUCK2 CPUCK1 CPUCK0

7

0

-

CKPAR2 CKPAR1 CKPAR0

Bit 7-6: Not Usedꢅ

Bit 7-3: Not Usedꢅ

Bit 5-0: &38&ꢌꢀꢓꢂꢅCPU Clock Prescaler bits

The CPU Clock frequency is divided by a

factor described in the following table

Bit 2-0: &ꢌ3$5ꢁꢓꢂꢅ Oscillator Gains

These three bits enable/disable the loop

gains when a external clock or quartz are

used for generating the clock. The

following table decribes the possible

configuration options. Table 6.1 illustrates

the reccomended values for the most

common frequencies used, time to start the

oscillations and the settling time to have a

duty cycle of 40%-60% (at steady state it is

50%).

f

=f

000000

000001

000010

000100

001000

010000

100000

others

CPU OSC

f

=f

/2

CPU OSC

=f

/4

/8

CPU OSC

=f

CPU OSC

f

=f

/16

/32

/64

CPU OSC

No Gains (External Clock Mode)

000

001

010

011

100

101

110

111

=f

CPU OSC

1 gain stage enabled

not allowed

=f

CPU OSC

=f

CPU OSC

3 gain stage enabled

not allowed

6 gain stage enabled

not allowed

ꢋꢇꢀꢇꢁꢅ2SWLRQꢅ%\WHVꢇ

&ORFNꢅ0RGHꢅꢐ26&B&5ꢑ

Option Byte 0 (00h)

8 gain stage enabled

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TXDUW]ꢀRUꢀFHUDPLFꢀUHVRQDWRUꢂꢀLWꢀLVꢀUHFFRPHQGHGꢀWKDW

QRꢀJDLQꢀEHꢀHQDEOHGꢀꢉ&C3$5ꢄꢌꢅ ꢅꢅꢅꢊꢀLQꢀRUGHUꢀOR

ORZHUꢀWKHꢀFXUUHQWꢀFRQVXPSWLRQꢁ

7

0

-

CKMOD

49/123

67ꢀꢁ)ꢀꢂꢂꢃ)ꢀꢂꢄ

7DEOHꢅꢋꢇꢆꢅ 5HFRPPHQGHGꢅ*DLQꢅ6WDJHVꢅIRUꢅWKHꢅPRVWꢅFRPPRQꢅIUHTXHQFLHV

External Clock

1 MHz

0

1

3

6

8

000

001

011

101

111

-

367 µs

84 µs

75 µs

79 µs

110 µs

352 µs

165 µs

27 µs

10 µs

9 µs

5 µs

8 µs

7 µs

11 µs

4 MHz

8 MHz

10 MHz

12 MHz

16 MHz

20 MHz

(1) The recommended values have been chosen to have the best tradeoff beetwen start time and current

consumption. Higher gains give shorter Start times; lower gains give less current consumption.

(2) Indicative values by design at 25° Celsius, V =2.6 V. Not Tested in production.

DD

,QWHUQDOꢅ2VFLOODWRUꢅ&DOLEUDWLRQꢅꢐ26&B6(7ꢑ

Bit 7-2: Not Usedꢅ

Option Byte 2 (02h)

Bit 1-0: 3/9'ꢆꢓꢂꢅ PLVD detection levels

00: Lowest detection level

01: Highest detection level

10: PLVD disabled

7

0

-

OSPAR5 OSPAR4 OSPAR3 OSPAR2 OSPAR1 OSPAR0

11: Medium detection level

Bit 7-6: Not Usedꢅ

:DNHꢓ8Sꢅ7LPHꢅ3UHVFDOHUꢅꢐ:$ꢌ(83ꢑ

Option Byte 7 (07h)

Bit 5-0: 263$5ꢀꢓꢂꢅ Internal Oscillator Parameters

These bits are used in order to calibrate the

precision of the internal oscillator working

at 10 MHz. The six bits enable some

current generators with steps of 0.05 µA

corresponding to interval of frequency of

100KHz.

7

0

WK7

WK6

WK5

WK4

WK3

WK2

WK1

WK0

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WRꢀWKHꢀꢍꢅꢀ0+]ꢀE\ꢀGHVLJQꢀLVꢀꢅꢍꢅꢍꢅꢅꢀꢉꢄꢅꢊꢁꢀ/RDGLQJ

YDOXHVꢀRYHUꢀꢋꢅꢀWKHꢀRVFLOODWRUꢀLVꢀVWRSSHGꢁ

Bit 7-0: :ꢌꢈꢓꢂꢅ Wake-up prescaler

This byte determinates the time delay for

the stabilization of the oscillator after an

External Reset or a POR and after the

wake-up from Halt. The time delay is

computed according to the following

formula:

3/9'ꢅ&RQWUROꢅ5HJLVWHUꢅꢐ3/9'B&5ꢑ

Option Byte 3 (03h)

'HOD\ = 4096 × (:$ꢀ(83 + 1) × 7FON

7

-

0

:DUQLQJꢀꢁ ꢀ ,Iꢀ WKHꢀ LQWHUQDOꢀ FORFNꢀ LVꢀ XVHGꢀ DVꢀ FORFN

VRXUFHꢀWKHꢀSUHVFDOHUꢀLVꢀQRWꢀXVHGꢁ

-

PLVD1 PLVD0

50/123

67ꢀꢁ)ꢀꢂꢂꢃ)ꢀꢂꢄ

ꢈꢅꢅ,ꢃ2ꢅ32576

ꢈꢇꢁꢅꢅ,QSXWꢅ0RGH

The pins configured as input can be read by

accessing the corresponding Port Input Register

by means of the LDRI instruction. The addresses

for Port A , B and C are respectively 0 (00h), 1

(01h), and 2 (02h).

When executing the LDRI instruction all the signals

connected to the input pins of the Port are read and

the logical value is copied in the specified Register

File location. If some pins are configured in output,

the port buffer contents, which are the last written

logical values in the output pins, are read.

ꢈꢇꢆꢅꢅ,QWURGXFWLRQ

ST52F500/F503 are characterized by flexible

individually programmable multi-functional I/O

lines. The ST52F500/F503 supplies devices with

up to 3 Ports (named from A to C) with up to 22 I/

O lines.

Each pin can be used as a digital I/O or can be

connected with a peripheral (Alternate Function).

The I/O lines belonging to Port A and Port B can

also be used to generate Port Interrupts. The I/O

Port pins can be configured in the following modes:

I Input high impedance (reset state)

I Input with pull-up

ꢈꢇꢄꢅꢅ2XWSXWꢅ0RGH

The pins configured as output can be written by

accessing the corresponding Port Output Register

by means of the LDPR, LDPI and LDPE

instructions. The addresses for Port A , B and C

are respectively, 0 (00h), 1 (01h), and 2 (02h).

When executing the above mentioned instructions,

the Port buffer is written and the Port pin signals

are modified. If some pins are configured as input

or as interrupt, the values are ignored.

I Output with pull-up

I Output push-pull

I Output with weak pull-up

I Output open drain

I Interrupt with pull-up

I Interrupt without pull-up

These eight modes can be selected by

programming three Configuration Registers for

each Port. All the pins that belong to the same Port

can be configured separately by setting the

corresponding bits in the three registers (see

Register Description).

To avoid side effects, the Configuration Registers

are latched only when the Data Direction Register

(PORT_x_DDR) is written. For this reason this

register must be always written when modifying the

pin configuration. All the I/O digital pins are TTL

compatible and have a Schmitt Trigger. The output

buffer can supply high current sink (up to 8mA).

ꢈꢇꢊꢅꢅ,QWHUUXSWꢅ0RGH

The pins configured as Interrupt Mode can

generate a Port Interrupt request. Only Port A and

Port B pins can be configured in this mode.

An Interrupt vector is associated to each Port:

there are two Port Interrupts available but more

pins of the ports can act as source at the same

time.

The Configuration Registers switch the signals

deriving from interrupt pins to an OR gate that

generates the interrupt request signal. The signal

deriving from the pins can be read, allowing the

discrimination of the interrupt sources when more

than one pin can generate the interrupt signal.

The interrupt trigger can be configured either in the

rising or falling edge of the external signal by using

the INT_POL register.

1RWHꢀꢁ:LWKꢀWKHꢀDLPꢀWRꢀUHGXFHꢀFXUUHQWꢀFRQVXPSWLRQ

LWꢀLVꢀUHFRPPHQGHGꢀWKDWꢀQRꢀIORDWLQJꢀSLQVꢀDUHꢀOHIWꢑꢀDOO

XQXVHGꢀ SLQVꢀ PXVWꢀ EHꢀ NHSWꢀ DWꢀ IL[HGꢀ YROWDJHꢁ

)XUWHKUPRUHꢀ LWꢀ LVꢀ UHFRPPHQGHGꢀ WKDWꢀ ELWVꢀ RIꢀ ,2

&RQILJXUDWLRQꢀ5HJLVWHUVꢀUHODWHGꢀWRꢀQRWꢀXVHGꢀRUꢀQRQ

DYDLODEOHꢀSRUWꢆSLQVꢀDUHꢀVHWꢀDVꢀ,QSXWꢀ3XOOꢌ8Sꢁ

)LJXUHꢅꢈꢇꢆꢅꢅꢅ'LJLWDOꢅ3LQ

PULL UP

ENABLE

DIGITAL OUT

ENABLE

DATA

OUT

PORT A,C,D,E

PAD

DATA

IN

51/123

67ꢀꢁ)ꢀꢂꢂꢃ)ꢀꢂꢄ

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When an on-chip peripheral is configured to use a

pin, the correct I/O mode of the related pin should

be selected by selecting one of the appropriate

modes. See the Registers description in order to

obtain the right configurations.Some peripherals,

as for example the I²C peripheral, directly drive the

pin configuration according to the current function,

overriding the user configuration.

The Alternate Function allows the pins to be

connected with the peripheral signals or NMI. Not

all Port pins have an Alternate Function

associated.

A Configuration Register (PORT_x_AF) for each

Port is used to switch from the Digital I/O function

or the Alternate Function.

Some pins can have two Alternate Functions: one

input function and one output function. To switch

between the two functions, the PORT_x_AF must

be configured in Alternate Function mode and the

PORT_x_DDR Configuration Register must be

switched in Input mode or in Output mode.

NMI is considered an Alternate Function. For this

reason an NMI interrupt request can’t be

generated unless the PA7 pin is configured in

Alternate Function and in one of the Input modes.

ꢈꢇꢋꢅꢅ5HJLVWHUꢅ'HVFULSWLRQ

In order to configure the Port’s pins, the three

Configuration

Registers

PORT_x_PULLUP,

PORT_x_OR and PORT_x_DDR must be

configured. The combination of these three

registers determine the pin’s configuration,

according to the scheme shown in Table 7.1.

In order to select between the digital functions or

Alternate functions PORT_x_AF register must be

configured. Each bit of the configuration registers

configures the pin of the corresponding position

(example: PORT_A_DDR bit 5 configures the pin

PA5).

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Vdd

EN

D

CONF. REG.

E

C

O

D

E

R

SEL

PU

CONF. REG.

INT

CONF. REG.

ENABLE

REGISTER

FILE

FF

DIGITAL

PORT PIN

ALTERNATE

FUNCTION

DATA

INTERRUPT

POLARITY

TO INPUT

REGISTER

IRQ

52/123

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Bit 7: $)$ꢈꢅAlternate Function PA7

0: Digital I/O

1: INT

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Configuration Register 24 (018h) Read/Write

Reset Value: 0000 0000 (00h)

Bit 6: $)$ꢋꢅAlternate Function PA6

0: Digital I/O

7

0

1: T0OUT

PUA7

PUA6

PUA5

PUA4

PUA3

PUA2

PUA1

PUA0

Bit 5: $)$ꢀꢅAlternate Function PA5

0: Digital I/O

Bit 7-0: 38$ꢈꢓꢂꢅPort A pull-up (see Table 7.1)

0: Port A pin without pull-up

1: TCLK

1: Port A pin with pull-up

Bit 4: $)$ꢊꢅAlternate Function PA4

0: Digital I/O

1: TSTRT

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Configuration Register 25 (019h) Read/Write

Reset Value: 0000 0000 (00h)

Bit 3: $)$ꢄꢅAlternate Function PA3

0: Digital I/O

1: TRES

7

0

Bit 2: $)$ꢁꢅAlternate Function PA2

0: Digital I/O

ORA7

ORA6

ORA5

ORA4

ORA3

ORA2

ORA1

ORA0

1: T1OUT

Bit 7-0: 25$ꢈꢓꢂꢅPort A option (see Table 7.1)

Bit 1: $)$ꢆꢅAlternate Function PA1

0: Digital I/O

1: SDA

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Configuration Register 26 (01Ah) Read/Write

Reset Value: 0000 0000 (00h)

Bit 0: $)$ꢂꢅAlternate Function PA0

0: Digital I/O

1: SCL

7

0

DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0

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Bit 7-0: ''5$ꢈꢓꢂꢅPort A direction (see Table 7.1)

0: Port A pin configured as input

Input high impedance

Input with pull-up

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1: Port A pin configured as output

Interrupt without pull-up

Interrupt with pull-up

Output push-pull

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Configuration Register 27 (01Bh) Read/Write

Reset Value: 0000 0000 (00h)

7

0

Output with pull-up

Output open drain

Output weak pull-up

AFA7

AFA6

AFA5

AFA4

AFA3

AFA2

AFA1

AFA0

53/123

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Configuration Register 28 (01Ch) Read/Write

Reset Value: 0000 0000 (00h)

Bit 7-4: Not Usedꢅ

Bit 3: $)%ꢄꢅAlternate Function PB3

0: Digital I/O

1: SS

7

0

PUB7* PUB6* PUB5** PUB4** PUB3** PUB2** PUB1

PUB0

Bit 2: $)%ꢁꢅAlternate Function PB2

0: Digital I/O

(*) Pin not available in 16/20 pin package devices. Set to ‘1’

(**) Pin not available in 16 pin package devices. Set to ‘1’

1: MISO

Bit 7-0: 38%ꢈꢓꢂꢅPort B pull-up (see Table 7.1)

0: Port B pin without pull-up

Bit 1: $)%ꢆꢅAlternate Function PB1

0: Digital I/O

1: Port B pin with pull-up

1: MOSI

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Configuration Register 29 (01Dh) Read/Write

Reset Value: 0000 0000 (00h)

Bit 0: $)%ꢂꢅAlternate Function PB0

0: Digital I/O

1: SCK

7

0

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Configuration Register 32 (020h) Read/Write

Reset Value: 0000 0000 (00h)

ORB7* ORB6* ORB5** ORB4** ORB3** ORB2** ORB1

ORB0

(*) Pin not available in 16/20 pin package devices. Set to ‘0’

(**) Pin not available in 16 pin package devices. Set to ‘0’

7

0

Bit 7-0: 25%ꢈꢓꢂꢅPort B option (see Table 7.1)

-

PUC5

PUC4

PUC3

PUC2

PUC1

PUC0

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Configuration Register 30 (01Eh) Read/Write

Reset Value: 0000 0000 (00h)

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ꢍꢈꢆꢄꢅꢀSLQꢀGHYLFHV

Bit 7-6: Not Usedꢅ

7

0

Bit 5-0: 38&ꢀꢓꢂꢅPort C pull-up (see Table 7.1)

0: Port C pin without pull-up

DDRB7* DDRB6* DDRB5** DDRB4** DDRB3** DDRB2** DDRB1 DDRB0

(*) Pin not available in 16/20 pin package devices. Set to ‘0’

(**) Pin not available in 16 pin package devices. Set to ‘0’

1: Port C pin with pull-up

Bit 7-0: ''5%ꢈꢓꢂꢅPort B direction (see Table 7.1)

0: Port B pin configured as input

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Configuration Register 33 (021h) Read/Write

Reset Value: 0000 0000 (00h)

1: Port B pin configured as output

7

0

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Configuration Register 31 (01Fh) Read/Write

Reset Value: 0000 0000 (00h)

-

ORC5

ORC4

ORC3

ORC2

ORC1

ORC0

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ꢍꢈꢆꢄꢅꢀSLQꢀGHYLFHV

7

0

Bit 7-6: Not Usedꢅ

-

AFB3

AFB2

AFB1

AFB0

Bit 5-0: 25&ꢀꢓꢂꢅPort C option (see Table 7.1)

1RWHꢀꢁ7KLVꢀUHJLVWHUꢀLVꢀQRWꢀXVHGꢀLQꢀꢍꢈꢀSLQꢀGHYLFHV

54/123

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Configuration Register 34 (022h) Read/Write

Reset Value: 0000 0000 (00h)

Bit 7-0: 3%,ꢈꢓꢂꢅPort B Input data

The logical level applied in the Port B pins,

configured as digital input, can be achieved by

reading this register.

7

0

-

DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0

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Input Register 2 (02h) Read only

Reset Value: XXXX XXXX

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Bit 7-6: Not Usedꢅ

7

0

Bit 5-0: ''5&ꢀꢓꢂꢅPort C direction (see Table 7.1)

0: Port C pin configured as input

-

PCI5

PCI4

PCI3

PCI2

PCI1

PCI0

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Bit 7-6: Not Usedꢅ

1: Port C pin configured as output

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HYHQꢀWKRXJKꢀWKH\ꢀDUHꢀQRWꢀH[LVWLQJꢀLQꢀWKHꢀSDFNDJHꢁ

)RUꢀH[DPSOHꢀLQꢀꢄꢅꢀSLQꢀGHYLFHVꢂꢀWKHꢀSLQVꢀ3%ꢈꢌꢐꢀDQG

3&ꢅꢌꢐꢀPXVWꢀEHꢀFRQILJXUHGꢀLQꢀLQSXWꢀSXOOꢌXSꢁ

Bit 5-0: 3&,ꢀꢓꢂꢅPort C Input data

The logical level applied in the Port C pins,

configured as digital input, can be achieved by

reading this register.

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Input Register 0 (00h) Read only

Reset Value: XXXX XXXX

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Output Register 0 (00h) Write only

Reset Value: 0000 0000 (00h)

7

0

PAI7

PAI6

PAI5

PAI4

PAI3

PAI2

PAI1

PAI0

7

0

Bit 7-0: 3$,ꢈꢓꢂꢅPort A Input data

PAO7

PAO6

PAO5

PAO4

PAO3

PAO2

PAO1

PAO0

The logical level applied in the Port A pins,

configured as digital input, can be achieved by

reading this register.

Bit 7-0: 3$2ꢈꢓꢂꢅPort A Output data

The logical values written in these register bits are

put in the Port A pins configured as digital output.

3RUWꢅ%ꢅ'DWDꢅ,QSXWꢅ5HJLVWHUꢅꢐ3257B%B,1ꢑ

Input Register 1 (01h) Read only

Reset Value: XXXX XXXX

7

0

P

7*

PBI6*

PBI5** PBI4** PBI3** PBI2**

PBI1

PBI0

(*) Not used in 16/20 pin package devices

(**) Not used in 16 pin package devices

55/123

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3RUWꢅ%ꢅ'DWDꢅ2XWSXWꢅ5HJLVWHUꢅꢐ3257B%B287ꢑ

Output Register 1 (01h) Write only

Reset Value: 0000 0000 (00h)

3RUWꢅ&ꢅ'DWDꢅ2XWSXWꢅ5HJLVWHUꢅꢐ3257B&B287ꢑ

Output Register 2 (02h) Write only

Reset Value: 0000 0000 (00h)

7

0

7

0

P

7* PBO6* PBO5** PBO4** PBO3** PBO2** PBO1

PBO0

-

PCO5

PCO4

PCO3

PCO2

PCO1

PCO0

(*) Not used in 16/20 pin package devices

(**) Not used in 16 pin package devices

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Bit 7-6: Not Usedꢅ

Bit 7-0: 3%2ꢈꢓꢂꢅPort B Input data

The logical values written in these register bits are

put in the Port B pins configured as digital output.

Bit 5-0: 3&2ꢀꢓꢂꢅPort C Input data

The logical values written in these register bits are

put in the Port C pins configured as digital output.

56/123

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The ST52F500/F503 Decision Processor (DP)

main features are:

j-th Mbf

1

I Up to 8 Inputs with 8-bit resolution;

I 1 Kbyte of Program/Data Memory available to

store more than 300 to Membership Functions

(Mbfs) for each Input;

ij

α

I Up to 128 Outputs with 8-bit resolution;

i-th INPUT VARIABLE

I Possibility of processing fuzzy rules with an

UNLIMITED number of antecedents;

I UNLIMITED number of Rules and Fuzzy Blocks.

The limits on the number of Fuzzy Rules and

Fuzzy program blocks are only related to the

Program/Data Memory size.

After loading the input values by using the LDFR

assembler instruction, the user can start the fuzzy

inference by using the FUZZY assembler

instruction. During fuzzyfication: input data is

transformed in the activation level (alpha weight) of

the Mbf’s.

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The block diagram shown in Figure 8.1 describes

the different steps performed during a Fuzzy

algorithm. The ST52F500/F503 Core allows for the

implementation of a Mamdami type fuzzy inference

with crisp consequents. Inputs for fuzzy inference

are stored in 8 dedicated Fuzzy input registers.

The LDFR instruction is used to set the Input Fuzzy

registers with values stored in the Register File.

The result of a Fuzzy inference is stored directly in

a location of the Register File.

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The Inference Phase manages the alpha weights

obtained during the fuzzyfication phase to compute

the truth value (ω) for each rule.

This is a calculation of the maximum (for the OR

operator) and/or minimum (for the AND operator)

performed on alpha values according to the logical

connectives of Fuzzy Rules.

Several conditions may be linked together by

linguistic connectives AND/OR, NOT operators

and brackets.

The truth value ω and the related output singleton

are used by the Defuzzyfication phase, in order

to complete the inference calculation.

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In this phase the intersection (alpha weight)

between the input values and the related Mbfs

(Figure 8.2) is performed.

Eight Fuzzy Input registers are available for Fuzzy

inferences.

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1

2

11

1m

INFERENCE

PHASE

DEFUZZYFICATION

FUZZYFICATION

n1

N rules -1

N rules

nm

Input Values

Output Values

57/123

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The Decision Processor allows the management of

triangular Mbfs. In order to define an Mbf, three

different parameters must be stored on the

Program/Data Memory (see Figure 8.4):

IF ,1387ꢁꢂ IS X1 OR ,1387ꢁꢃꢁIS X2 THEN .......

α

I the vertex of the Mbf: 9;

α2

I the length of the right semi-base: 59';

I he length of the left semi-base: /9';

In order to reduce the size of the memory area and

the computational effort the vertical range of the

vertex is fixed between 0 and 15 (4 bits)

By using the previous memorization method

different kinds of triangular Membership Functions

may be stored. Figure 8.5 shows some examples

of valid Mbfs that can be defined in ST52F500/

F503.

IF ,1387ꢁꢂ IS X1 AND ,1387ꢁꢃꢁIS X2 THEN .......

α

Each Mbf is then defined storing 3 bytes in the first

Kbyte of the Program/Data Memory.

α2

The Mbf is stored by using the following instruction:

0%) QBPEIꢀꢀOYGꢀꢀYꢀꢀUYG

where:

QBPEI is a tag number that identifies the Mbf

ꢏꢇꢊꢅꢅ'HIX]]\ILFDWLRQ

OYG, Y, and UYG are the parameters that describe the

Mbf’s shape as described above.

In this phase the output crisp values are

determined by implementing the consequent part

of the rules.

Each consequent Singleton X_iis multiplied by its

weight values ω_i, calculated by the Decision

processor, in order to compute the upper part of

the Defuzzyfication formula.

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15

Each output value is obtained from the consequent

crisp values (X_i) by carrying out the following

Defuzzyfication formula:

Input Mbf

; ω

∑

0

V

Input Variable

RVD

---------------------

< =

LVD

ω

∑

where:

i = identifies the current output variable

N = number of the active rules on the current

output

ω_ij= weight of the j-th singleton

Output Singleton

15

w

X_ij= abscissa of the j-th singleton

The Decision Processor outputs are stored in the

RAM location i-th specified in the assembler

instruction OUT i.

0

X

Output Variable

58/123

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)LJXUHꢅꢏꢇꢋꢅꢅꢅ2XWSXWꢅ0HPEHUVKLSꢅ)XQFWLRQV

j-th Singleton

1

ω

ij

ω

i0

ω

in

0

X

i-th OUTPUT

ij

i0

in

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Rules can have the following structures:

if A op B op C...........then Z

if (A op B) op (C op D op E...) ...........then Z

where RS is one of the possible linguistic operators

(AND/OR)

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The Decision Processor uses a particular kind of

membership function called Singleton for its output

variables. A Singleton doesn’t have a shape, like a

traditional Mbf, and is characterized by a single

point identified by the couple (X, w), where w is

calculated by the Inference Unit as described

earlier. Often, a Singleton is simply identified with

its Crisp Value X.

In the first case the rule operators are managed

sequentially; in the second one, the priority of the

operator is fixed by the brackets.

Each rule is codified by using an instruction set, the

inference time for a rule with 4 antecedents and 1

consequent is about 3 microseconds at 20 MHz.

The Assembler Instruction Set used to manage the

Fuzzy operations is reported in the table below.

7DEOHꢅꢏꢇꢆꢅ )X]]\ꢅ,QVWUXFWLRQVꢅ6HW

Stores the Mbf QBPEI with the shape identified by the parameters ,YG, Y and UYG

Fixes the alpha value of the input n with the Mbf m

Calculates the complementary alpha value of the input n with the Mbf m.

Implements the Fuzzy operation AND

Implements the Fuzzy operation OR

Multiplies the crisp value with the last ω weight

Performs Defuzzyfication and stores the currently Fuzzy output in the register

QBRXW

Starts the computation of a sigle fuzzy variable

Modify the priority in the rule evaluation

59/123

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([DPSOHꢅꢆ:

,)ꢀ,QSXW ꢀ,6ꢀ127ꢀ0EI ꢀ$1'ꢀ,QSXW ꢀLVꢀ0EI ꢀ25ꢀ,QSXW ꢀ ,6ꢀ0EI ꢀ7+(1ꢀ&ULVS

is codified by the following instructions:

calculates the NOT α value of Input₁with Mbf₁and stores the result in internal registers

,6127ꢅꢅꢆꢅꢅꢆ

)=$1'

,6ꢅꢅꢊꢅꢅꢆꢁ

)=25

implements the operation AND between the previous and the next alpha value evaluated

fixes the α value of Input₄with Mbf₁₂and stores the result in internal registers

implements the operation OR between the previous and the next alpha value evaluated

fixes the α value of Input₃with Mbf₈and stores the result in internal registers

,6ꢅꢅꢄꢅꢅꢏ

&21ꢅFULVS multiplies the result of the last Ω operation with the crisp value FULVS

([DPSOHꢅꢁ, the priority of the operator is fixed by the brackets:

,)ꢀꢉ,QSXW ꢀ,6ꢀ0EI ꢀ$1'ꢀ,QSXW ꢀ,6ꢀ127ꢀ0EI ꢊꢀ25ꢀꢉ,QSXW ꢀ,6ꢀ0EI ꢀ25ꢀ,QSXW ,6ꢀ127ꢀ0EI ꢊꢀ7+(1ꢀ&ULVS

ꢐ

parenthesis open to change the priority

fixes the α value of Input₃with Mbf₁and stores the result in internal registers

,6ꢅꢅꢄꢅꢅꢆ

)=$1'

implements the operation AND between the previous and the next alpha value evaluated

calculates the NOT α value of Input₄with Mbf₁₅and stores the result in internal registers

,6127ꢅꢅꢊꢅꢅꢆꢀ

ꢑ

parenthesis closed

)=25

implements the operation OR between the previous and the next alpha value evaluated

parenthesis open to change the priority

ꢐ

fixes the α value of Input₁with Mbf₆and stores the result in internal registers

,6ꢅꢅꢆꢅꢅꢋ

)=25

implements the operation OR between the previous and the next alpha value evaluated

calculates the NOT α value of Input₆with Mbf₁₄and stores the result in internal registers

,6127ꢅꢅꢁꢅꢅꢆꢊꢅ

ꢑ

parenthesis closed

&21ꢅFULVS multiplies the result of the last Ω operation with the crisp value FULVS

At the end of the fuzzy rules related to the current Fuzzy Variable, by using the instruction 287 UHJ, the

specified register is written with the computed value. Afterwards, the control of the algorithm returns to the

CU. The next Fuzzy Variable evaluation must start again with a FUZZY instruction.

60/123

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ꢉꢅꢅ,16758&7,21ꢅ6(7

operands can refer (according to the opcode) to

addresses belonging to the different addressing

spaces. Example: SUB, LDRE.

ST52F500/F503 supplies 107 (98 + 9 Fuzzy)

instructions that perform computations and control

the device. Computational time required for each

instruction consists of one clock pulse for each

Cycle plus 2 clock pulses for the decoding phase.

Total computation time for each instruction is

reported in Table 9.1

The ALU of ST52F500/F503 can perform

multiplication (MULT) and division (DIV).

Multiplication is performed by using 8 bit operands

storing the result in 2 registers (16 bit values), see

Figure 2.3.

I Indirect: data addresses that are required are

found in the locations specified as operands.

Both source and/or destination operands can be

addressed indirectly. The operands can refer,

(according to the opcode) to addresses

belonging to different addressing spaces.

Examples: LDRR(reg1),(reg2);

LDER mem_addr,(reg1).

I Bit Direct: operands of these instructions directly

address the bits of the specified Register File

locations. Examples: BSET, BTEST.

Division is performed between a 16 bit dividend

and an 8 bit divider, the result and the remainder

are stored in two 8-bit registers (see Figure 2.4).

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ST52F500/F503 supplies the following instruction

types:

I Load Instructions

ST52F500/F503 instructions allow the following

addressing modes:

I Inherent: this instruction type does not require

an operand because the opcode specifies all the

information necessary to carry out the

I Arithmetic and Logic Instructions

I Bitwise instructions

instruction. Examples: NOP, SCF.

I Jump Instructions

I Immediate: these instructions have an operand

as a source immediate value. Examples: LDRC,

ADDI.

I Interrupt Management Instructions

I Control Instructions

I Direct: the operands of these instructions are

The instructions are listed in Table 9.1

specified with the direct addresses. The

7DEOHꢅꢉꢇꢆꢅ ,QVWUXFWLRQꢅ6HW

BLKSET

GETPG

LDCE

LDCI

BLKSET const

GETPG regx

2

3

(*)

7

-

LDCE confx,memy

LDCI confx, const

LDCNF regx, conf

LDCR confx, regy

LDER memx, regy

LDER (regx),(regy)

LDER (regx), regy

LDER memx,(regy)

LDFR fuzzyx, regy

8/10

7

LDCNF

LDCR

LDER

LDFR

7

8

11

12

11

12

8

61/123

67ꢀꢁ)ꢀꢂꢂꢃ)ꢀꢂꢄ

LDPE

LDPI

LDPE outx, memy

LDPE outx, (regy)

LDPI outx, const

LDPR outx, regy

LDRC regx, const

LDRE regx, memy

LDRE (regx), (regy)

LDRE (regx), memy

LDRE regx, (regy)

LDRI regx, inpx

LDRR regx, regy

LDRR (regx), (regy)

LDRR (regx), regy

LDRR regx, (regy)

PGSET const

3

2

8/10

9/11

7

-

LDPR

LDRC

LDRE

LDRI

8

7

8/10

10/12

9/11

9/12

7

LDRR

PGSET

PGSETR

POP

9

10

9

10

4

PGSETR regx

5

POP regx

7

PUSH

PUSH regx

8

ADD

ADDC

ADDI

ADD regx, regy

ADDC regx, regy

ADDI regx, const

ADDIC regx, const

ADDO regx, regy

ADDOC regx, regy

ADDOI regx, const

ADDOICregx,cons

AND regx, regy

ANDI regx,const

CP regx, regy

3

9

I

-

I

-

I

-

3

2

8

ADDIC

ADDO

ADDOC

ADDOI

ADDOIC

AND

8

11

10

9

ANDI

8

CP

8

CPI

CPI regx,const

7

DEC

DEC regx

7

62/123

67ꢀꢁ)ꢀꢂꢂꢃ)ꢀꢂꢄ

DIV

INC

DIV regx, regy

INC regx

3

2

3

2

3

1

3

16

7

I

-

I

-

I

-

I

MIRROR

MULT

NOT

MIRROR regx

MULT regx, regy

NOT regx

7

-

I

11

7

OR

OR regx, regy

ORI regx, const

SUB regx, regy

SUBI regx, const

SUBIS regx, const

SUBO regx, regy

SUBOI regx,

SUBOISregx,const

SUBOS regx, regy

SUBS regx, regy

RCF

9

ORI

8

SUB

9

SUBI

SUBIS

SUBO

SUBOI

SUBOIS

SUBOS

SUBS

RCF

8

I

8

I

11

10

11

9

I

-

I

4

-

I

RSF

4

-

I

RZF

4

-

I

SCF

4

SSF

4

-

SZF

4

-

XOR

XOR regx, regy

XORI regx, cons

9

XORI

8

ASL

ASR

ASL regx

ASR regx

2

3

2

7

8

7

I

-

I

-

I

BNOT

BRES

BSET

BTEST

MTEST

RLC

BNOT regx, bit

BRES regx, bit

BSET regx, bit

BTEST regx, bit

MTEST regx,const

RLC regx

-

63/123

67ꢀꢁ)ꢀꢂꢂꢃ)ꢀꢂꢄ

ROL

ROR

RRS

ROL regx

ROR regx

RRS regx

2

7

I

-

I

-

CALL

JP

CALL addr

JP addr

3

1

11

6

-

JPC

JPC addr

JPNC addr

JPNS addr

JPNZ addr

JPS addr

JPZ addr

RET

5/6

8

JPNC

JPNS

JPNZ

JPS

JPZ

RET

HALT

MEGI

MDGI

RETI

HALT

MEGI

1

2

1

4/13

6/11

5

-

MDGI

RETI

9

RINT

UDGI

UEGI

TRAP

WAITI

RINT INT

UDGI

6

5

UEGI

6/11

9

TRAP

WAITI

7/10

FUZZY

NOP

FUZZY

NOP

1

4

6

5

-

WDTRFR

WDTSLP

WDTRFR

WDTSLP

64/123

67ꢀꢁ)ꢀꢂꢂꢃ)ꢀꢂꢄ

1RWHVꢒ

regx, regy:

memx, memy:

confx, confy:

outx:

Register File Address

Program/Data Memory Addresses

Configuration Registers Addresses

Output Registers Addresses

Input Registers Addresses

Constant value

inpx:

const:

fuzzyx:

I

Fuzzy Input Registers

flag affected

-

flag not affected

ꢐꢔꢑꢅ The instruction BLKSET determines the start of a 32 byte block writing in Flash or EEPROM Program/

Data Memory. During this phase (about 4 ms), the CPU is stopped to executing program instructions. The

duration of the BLKSET instruction can be identified with this time.

65/123

67ꢀꢁ)ꢀꢂꢂꢃ)ꢀꢂꢄ

ꢆꢂꢅꢅ:$7&+'2*ꢅ7,0(5

The working frequency of WDT (PRES CLK in the

Figure 10.1) is equal to the clock master. The clock

master is divided by 500, obtaining the WDT CLK

signal that is used to fix the timeout of the WDT.

According to the WDT_CR Configuration Register

values, a WDT delay between 0.1ms and 937.5ms

can be defined when the clock master is 5 MHz. By

changing the clock master frequency the timeout

delay can be calculated according to the

configuration register values. The first 4 bits of the

WDT_CR register are used, obtaining 16 different

delays.

ꢆꢂꢇꢆꢅꢅ)XQFWLRQDOꢅ'HVFULSWLRQ

The Watchdog Timer (WDT) is used to detect the

occurrence of a software fault, usually generated

by external interference or by unforeseen logical

conditions, which causes the application program

to abandon its normal sequence. The WDT circuit

generates an ICU reset on expiry of a programmed

time period, unless the program refreshes the

WDT before the end of the programmed time

delay. Sixteen different delays can be selected by

using the WDT configuration register.

After the end of the delay programmed by the

configuration register, if the WDT is active, it starts

a reset cycle pulling the reset signal low.

7DEOHꢅꢆꢂꢇꢆꢅ:DWFKGRJꢅ7LPLQJꢅ5DQJHꢅꢐꢀꢅ0+]ꢑ

Once the WDT is activated, the application

program has to refresh the counter (by the

WDTRFR instruction) during normal operation in

order to prevent an ICU reset.

min

0.1

max

937.5

In ST52F500/F503 devices it is possible to choose

between “Hardware” or “Software” Watchdog. The

Hardware WDT allows the counting to avoid

unwanted stops for external interferences. The first

mode is always enabled unless the Option Byte 4

ꢆꢂꢇꢁꢅꢅ5HJLVWHUꢅ'HVFULSWLRQ

6:ꢅ:DWFKGRJꢅ(QDEOHꢅꢐ:'7B(1ꢑ

Option Byte 4 (04h)

(WDT_EN) is written with

a special code

(10101010b): only this code can switch the WDT in

“Software” Mode, the other 255 possibilities keep

the “Hardware” Mode enabled.

7

0

The WDT is started and refreshed by using the

WDTRFR instruction. When the software mode is

enabled, the WDTSLP instruction stops the WDT

avoiding timeout resets.

WDTEN7 WDTEN6 WDTEN5 WDTEN4 WDTEN3 WDTEN2 WDTEN1 WDTEN0

When the WDT is in Hardware Mode, neither the

WDTSLP instruction nor external interference can

stop the counting. The “Hardware” WDT is always

enabled after a Reset.

Bit 7-0: :'7(1ꢈꢓꢂꢅSW Watchdog Enable byte

Writing the code 10101010 in this byte the

Software Watchdog mode is enabled.

)LJXUHꢅꢆꢂꢇꢆꢅꢅꢅ:DWFKGRJꢅ%ORFNꢅ'LDJUDP

Configuration Register

D3 D2 D1 D0

WDT

WDTRFR

RESET

WTD CLK

RESET

PRESCALER

GENERATOR

PRES CLK = CLK MASTER

WDTSLP

66/123

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:DWFKGRJꢅ&RQWUROꢅ5HJLVWHUꢅꢐ:'7B&5ꢑ

Configuration Register 7 (07h) Read/Write

Reset Value: 0000 0001 (01h)

Bit 3-0: 'ꢄꢓꢂꢅWatchdog Clock divisor factor bits

The Watchdog Clock (WDT CLK) is divided

by the numeric factor determined by these

bits, according with Table 10.2 and the

following formula:

7

0

5 × 10⁵× 'LYLVLRQ)DFWRU

-

D3

D2

D1

D0

----------------------------------------------------------------

7LPHRXW(PV) =

&ORFN(0+])

Bit 7-4: Not Usedꢅ

7DEOHꢅꢆꢂꢇꢁꢅ:DWFKGRJꢅ7LPHRXWꢅFRQILJXUDWLRQꢅH[DPSOHV

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

1

0.1

62.5

125

0.05

0.025

15.625

31.25

625

31.25

62.5

1250

1875

2500

3125

3750

4375

5000

5625

6250

6875

7500

8125

8750

9375

187.5

250

93.75

125

46.875

62.5

312.5

375

156.25

187.5

218.75

250

78.125

93.75

437.5

500

109.375

125

562.5

625

281.25

312.5

343.75

375

140.625

156.25

171.875

187.5

687.5

750

812.5

875

406.25

437.5

468.75

203.125

218.75

234.375

937.5

67/123

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ꢆꢆꢅꢅ3:0ꢃ7,0(56

ꢆꢆꢇꢆꢅꢅ,QWURGXFWLRQ

ST52F500/503 offers two on-chip PWM/Timer

peripherals. All ST52F500/503 PWM/Timers have

the same internal structure. The timer consists of a

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HIIHFWVꢂꢀWKHꢀYDOXHVꢀVWRUHGꢀLQVLGHꢀWKHVHꢀUHJLVWHUVꢀDUH

IUR]HQꢂꢀ DQGꢀ QHZꢀ XSGDWHVꢀ FDQQRWꢀ EHꢀ VWRUHGꢂꢀ XQWLO

ERWKꢀWKHꢀYDOXHVꢀDUHꢀUHDGꢁꢀꢀ

The peripheral status can also be read from the

Input Registers PWMx_STATUS. These registers

report START/STOP, SET/RESET status, TxOUT

signal and the counter overflow flag. This last

signal is set after the first EOC and it is reset by a

Timer RESET (internal or external).

16-bit counter with

a

16-bit programmable

Prescaler, giving a maximum count of 2³²(see

Figure 11.1).

Each timer has two different working modes, which

can be selected by setting the correspondent bit

TxMOD of the PWMx_CR1 Configuration

Register: Timer Mode and PWM (Pulse Width

Modulation) Mode.

All the Timers have Autoreload Functions; in PWM

Mode the reload value can be set by the user.

Each timer output is available on the apposite

external pins configured in Alternate Function and

in one of the Output modes.

PWM/Timer 0 can also use external START/STOP

signals in order to perform Input capture and

Output compare, external RESET signal, and

external CLOCK to count external events: TSTRT,

TRES and TCLK pins. In addition, the START/

STOP and RESET signals have configurable

polarity (falling or rising edge).

ꢆꢆꢇꢁꢅꢅ7LPHUꢅ0RGHꢅ

Timer Mode is selected writing 0 in the TxMOD bit.

Each Timer requires three signals: Timer Clock

(TMRCLKx), Timer Reset (TxRES) and Timer Start

(TxSTRT) (see Figure 11.1). Each of these signals

can be generated internally, and/or externally only

for Timer 0, by using TRES, TSTRT and TCLK

pins.

The Prescaler output (PRESCOUT) increments

the Counter value on the rising edge. PRESCOUT

is obtained from the internal clock signal (CLKM)

or, only for TIMER0, from the external signal

provided on the apposite pin.

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VLJQDOVꢀ WKHꢀ UHODWHGꢀ SLQVꢀ PXVWꢀ EHꢀ FRQILJXUHGꢀ LQ

$OWHUQDWHꢀ)XQFWLRQꢀDQGꢀLQꢀRQHꢀRIꢀ,QSXWꢀPRGHVꢁꢀ

The prescaler output period can be selected by

setting the TxPRESC bits with one of the 17

division factors available. TMRCLK frequency is

divided by a factor equal to the power of two of the

prescaler values (up to 2¹⁶).

For each timer, the contents of the 16-bit counter

are incremented on the Rising Edge of the 16-bit

prescaler output (PRESCOUT) and they can be

read at any instant of the counting phase by

accessing

the

Input

Registers

TxRES resets the content of the 16-bit counter to

zero. It is generated by writing 0 in the TxRES bit

of the PWMx_CR1 Configuration Register and/or it

can be driven by the TRES pin if configured (only

Timer0).

PWMx_COUNT_IN_x; the value is stored in two 8-

bit registers (MSB and LSB) for each PWM/Timer.

The Input Registers couple PWMx_CAPTURE_x

store the counter value after the last Stop signal

(only Timer Mode). The counter value is not stored

after a Reset Signal.

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BIT 5

BIT 14

BIT 15

BIT 0

BIT 1

BIT 2

BIT 3

BIT 4

BIT 0

BIT 1

BIT 2

BIT 3

BIT 4

BIT 5

BIT 14

BIT 15

68/123

67ꢀꢁ)ꢀꢂꢂꢃ)ꢀꢂꢄ

)LJXUHꢅꢆꢆꢇꢁꢅꢅꢅ7LPHUꢅꢂꢅ([WHUQDOꢅ6WDUWꢃ6WRSꢅ0RGH

start

stop

Level

stop

start

Edge

Reset

Clock

Counted

Value

2

0

1

3

4

0

1

TxSTRT signal starts/stops the Timer from

counting only if the peripherals are configured in

Timer mode. The Timers are started by writing 1 in

the TXSTRT bit of the PWMx_CR1 and are

stopped by writing 0. This signal can be generated

internally and/or externally by forcing the TSTRT

pin (only TIMER0).

TIMER 0 START/STOP can be given externally on

the TSTRT pin. In this case, the T0STRT signal

allows the user to work in two different configurable

modes:

I LEVEL (Time Counter): If the T0STRT signal is

high, the Timer starts counting. When the

T0STRT is low the timer stops counting and the

16-bit current value is stored in the

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ELWꢀFRXQWHUꢁ

:DUQLQJꢀꢁ LQꢀ 7LPHUꢀ 0RGHꢀ WKHꢀ 5HORDGꢀ 5HJLVWHU

FRXSOHꢀPWMx_RELOAD_x ꢉVHHꢀ3:0ꢀPRGHꢊꢀPXVW

EHꢀ VHWꢀ WRꢀ WKHꢀ KLJKHUꢀ YDOXHꢀ ))))Kꢀ ꢉꢈꢃꢃꢇꢃꢊ

RWKHUZLVHꢀLWꢀFDQꢀDIIHFWꢀWKHꢀFRXQWꢀGXUDWLRQꢁ

There can be two types of TxOUT waveforms:

I type 1: TxOUT waveform equal to a square

wave with a 50% duty-cycle

PWM0_COUNT_IN_x Input Registers couple.

I EDGE (Period Counter): After reset, on the first

T0STRT rising edge, TIMER 0 starts counting

and at the next rising edge it stops. In this

manner the period of an external signal may be

measured.

I type 2: TxOUT waveform equal to a pulse signal

with the pulse duration equal to the Prescaler

output signal.

The same above mentioned modes, can be used

to reset the Timer0 by using the TRES pin signal.

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The polarity of the T0SRTR Start/Stop signal can

be changed by setting the STRPOL and RESPOL

bits in the INT_POL Configuration Register (01h bit

3 and 4). When these bits are set, the PWM/Timer

0 is Started/Set on the low level or in the falling

edge of the signal applied in the pins.

Prescout*Counter

Timer Output

Type 1

The Timer output signal, TxOUT, is a signal with a

frequency equal to the one of the 16 bit-Prescaler

output signal, PRESCOUTx, divided by a 16-bit

counter set by writing the Output Register couple

PWMx_COUNT_OUT_x.

Type 2

69/123

67ꢀꢁ)ꢀꢂꢂꢃ)ꢀꢂꢄ

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65535

Reload

Value

Counter

Value

0

t

PWM

Output

Ton

t

T

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7

3:0[&2817

3:0[5(/2$'

The PWM working mode for each timer is obtained

by setting the TxMOD bit of the Configuration

Register PWMx_CR1.

The TxOUT signal in PWM Mode consists of a

signal with a fixed period, whose duty cycle can be

modified by the user.

--------

7

-----------------------------------------

=

G

=

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The TxOUT period is fixed by setting the 16-bit

Prescaler bits (TxPRESC) in the PWMx_CR2 and

the 16-bit Reload value by writing the relative

Output Registers couple PWMx_RELOAD_x. The

16-bit Prescaler divides the master clock CLKM by

powers of two, determining the maximum length

period.

Reload determines the maximum value that the

counter can count before starting a new period.

The use of the two 16-bit values allows the TxOUT

period to be set with more precision when needed.

By decreasing the Reload value the counting

resolution decreases. In order to obtain the

maximum resolution, Reload value should be set

to 0FFFFh and the period corresponds to the one

established by the Prescaler value.

The value set in the 16-bit counter by writing the

Counter Output Registers couple, determines the

duty-cycle: when count reaches the Counter value

the TxOUT signal changes from high to low level.

The period of the PWM signal is obtained by using

the following formula:

T=PWMx_-RELOAD * 2^TxPRESC*TMRCLKx

By using a 20 MHz clock a PWM frequency that is

close to 305 Khz can be obtained with a reload

equal to FFFFh and the Prescaler set to 0000h.

The TIMER0 clock CLKM can also be supplied

with an external signal, applied on the TCLK pin,

which must have a frequency that is at least two

times smaller than the internal master clock.

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&RXQWHUꢀ LWꢀ LVꢀ VHWꢀ LPPHGLDWHO\ꢁꢀ 1HYHUWKHOHVVꢂꢀ LWꢀ LV

UHFRPPHQGHGꢀ WKDWꢀ WKHꢀ 5HORDGꢀ YDOXHꢀ EHꢀ ZULWWHQ

ZKHQꢀ WKHꢀ 7LPHUꢀ LVꢀ VWRS S HGꢀ LQꢀ RUGHUꢀ WRꢀ DYRLG

LQFRQJUXHQFHꢀ ZLWKꢀ WKHꢀ &RXQWHUꢀ YDOXHꢁꢀ 7KHꢀ VDPH

UHFRPPHQGDWLRQꢀ LVꢀ PDGHꢀ ZKHQꢀ UHDGLQJꢀ WKHꢀ WZR

E\WHVꢀRIꢀWKHꢀFRXQWHUꢎꢀ,WꢀLVꢀSHUIRUPHGꢀLQꢀWZRꢀVWHSVꢂ

VRꢀLIꢀWKHꢀWLPHUꢀLVꢀUXQQLQJꢂꢀWKHꢀFDUU\ꢀRIꢀWKHꢀ/6%ꢀWRꢀWKH

06%ꢀFDQꢀFDXVHꢀWKHꢀZURQJꢀꢍꢈꢌELWꢀYDOXHꢀUHDGLQJꢁꢀ$

5HORDGꢀYDOXHꢀJUHDWHUꢀWKDQꢀꢍꢀPXVWꢀDOZD\VꢀEHꢀXVHGꢁ

where TxPRESC equals the value set in the

TxPRESC bits of the PWMx_CR2 Configuration

Register and TMRCLKx is the period of the Timer

clock that drives the Prescaler.

The duty cycle of the PWM signal is obtained by

the following formula:

70/123

67ꢀꢁ)ꢀꢂꢂꢃ)ꢀꢂꢄ

When the Timers are in Reset status, or when the

device is reset, the TxOUT pins goes in threestate.

If these outputs are used to drive external devices,

it is recommended that the related pins be left in

the default configuration (Input threestate) or

change them in this configuration.

ꢆꢆꢇꢀꢅꢅ3:0ꢃ7LPHUꢅꢂꢅ5HJLVWHUꢅ'HVFULSWLRQ

The following registers are related to the use of the

PWM/Timer 0.

ꢆꢆꢇꢀꢇꢆꢅꢅ3:0ꢃ7LPHUꢅꢂꢅ&RQILJXUDWLRQꢅ5HJLVWHUVꢇ

In PWM mode the PWM/Timers can only be Set or

Reset: Start/Stop signals do not affect the Timers.

TxRES resets the content of the 16-bit counter to

zero. It is generated by writing 0 in the

corresponding TxRES bit of the PWMx_CR1

Configuration Register and/or it can be driven by

the TRES pin if it is configured (only Timer0).

3:0ꢃ7LPHUꢅꢂꢅ&RQWUROꢅ5HJLVWHUꢅꢆꢅꢐ3:0ꢂB&5ꢆꢑ

Configuration Register 9 (09h) Read/Write

Reset Value: 0000 0000 (00h)

7

0

ꢆꢆꢇꢄꢇꢆꢅꢅ6LPXOWDQHRXVꢅ6WDUWꢇ

T0MOD T0IES

T0IEF

T0IER STRMOD T0STRT RESMOD T0RES

The PWM/Timers can be started simultaneously.

The T0SYNC and T1SYNC bits in PWM0_CR3

Configuration Registers mask the reset of each

timer. After enabling each single PWM/Timer, they

are started by putting off the mask with a single

writing in the PWM0_CR3 Register.

Bit 7: 7ꢂ02'ꢅPWM/Timer 0 Mode

0: Timer Mode

1: PWM Mode

The timers start counting simultaneously, but the

output pulses are generated according to the

modality configured (square or pulse mode).

Bit 6: 7ꢂ,(6ꢅInterrupt on Stop signal Enable

0: interrupt disabled

1: interrupt enabled

ꢆꢆꢇꢊꢅꢅ7LPHUꢅ,QWHUUXSWV

The PWM/Timer can be programmed to generate

an Interrupt Request, both on the falling and the

rising of the TxOUT signal and when there’s a

STOP signal (external or internal).

Bit 5: 7ꢂ,()ꢅInterrupt on T0OUT falling Enable

0: interrupt disabled

1: interrupt enabled

By using the TxIES, TxIER and TxIEF bits of the

Configuration Registers PWMx_CR1, the interrupt

sources can be switched on/off. All the interrupt

sources may be activated at the same time:

sources can be distinguished by reading the

PWMx_STATUS Input Register.

The interrupt on the falling edge corresponds to

half of a counting period in Timer mode when the

waveform is set to Square Wave and to the end of

the Ton phase in PWM mode.

Bit 4: 7ꢂ,(5ꢅInterrupt on T0OUT rising Enable

0: interrupt disabled

1: interrupt enabled

Bit 3: 67502'ꢅStart signal mode

0: start/stop on level

1: start/stop on edge

1RWHꢀꢁZKHQꢀWKHꢀ3:0ꢀ&RXQWHUꢀLVꢀVHWꢀWRꢀꢅꢀRUꢀꢈꢃꢃꢇꢃꢂ

WKHꢀ LQWHUUXSWꢀ RFFXUVꢀ DWꢀ WKHꢀ HQGꢀ RIꢀ HDFKꢀ FRQWURO

SHULRGꢁꢀ

Bit 2: 7ꢂ6757ꢅPWM/Timer 0 Start bit

0: Timer 0 stopped

1: Timer 0 started

In order to be active, the PWM/Timers interrupts

must be enabled by writing the Interrupt Mask

Register (INT_MASK) in the Configuration

Register Space, bits MSKT0 And MSKT1.

Bit 1: 5(602'ꢅReset signal mode

0: set/reset on level

1: set/reset on edge

1RWHꢀꢁ ,QWHUUXSWꢀ RQꢀ 7[287ꢀ 5LVLQJꢀ (GJHꢎꢀ WKHꢀ ILUVW

ULVLQJꢀHGJHꢀGRHVQ¶WꢀJLYHꢀDQꢀLQWHUUXSWꢁ

Bit 0: 7ꢂ5(6ꢅPWM/Timer 0 Reset bit

0: PWM/Timer 0 reset

1: PWM/Timer 0 set

71/123

67ꢀꢁ)ꢀꢂꢂꢃ)ꢀꢂꢄ

3:0ꢃ7LPHUꢅꢂꢅ&RQWUROꢅ5HJLVWHUꢅꢁꢅꢐ3:0ꢂB&5ꢁꢑ

Configuration Register 10 (0Ah) Read/Write

Reset Value: 0000 0000 (00h)

Bit 1-0: 5(665&ꢅPWM/Timer 0 Reset source

00: Internal from T0RES bit

01: External from TRES pin

10: Both internal and external

7

4

0

-

T0WAV

T0PRESC

,QWHUUXSWꢅ3RODULW\ꢅ5HJLVWHUꢅꢐ,17B32/ꢑ

Configuration Register 1 (01h) Read/Write

Reset Value: 0000 0000 (00h)

Bit 7-6: Not Usedꢅ

7

0

Bit 5: 7ꢂ:$9ꢅT0OUT Waveform

0: pulse (type2)

-

RESPOL STRPOL POLPB POLPA POLNMI

1: square (type1)

Bit 7-5: Not Usedꢅ

Bit 4-0: 7ꢂ35(6&ꢅPWM/Timer 0 Prescaler

The PWM/Timer 0 clock is divided by a

factor equal to 2^T0PRESC. 7KHꢅ PD[LPXP

YDOXHꢅ DOORZHGꢅ IRUꢅ 7ꢂ35(6&ꢅ LVꢅ ꢆꢂꢂꢂꢂ

ꢐꢂꢆꢂKꢑ.

Bit 4: 5(632/ꢅReset signal polarity

0: Set/Reset on low level/rising edge

1: Set/Reset on high level/falling edge

Bit 3: 67532/ꢅStart signal polarity

0: Start on high level/rising edge

1: Start on low level/falling edge

3:0ꢃ7LPHUꢅꢂꢅ&RQWUROꢅ5HJLVWHUꢅꢄꢅꢐ3:0ꢂB&5ꢄꢑ

Configuration Register 11 (0Bh) Read/Write

Reset Value: 0000 0000 (00h)

Bit 2-0: See Interrupt Registers Description

7

0

T1SYNC

-

T0SYNC T0CKS

STRSRC

RESSRC

ꢆꢆꢇꢀꢇꢁꢅꢅ3:0ꢃ7LPHUꢅꢂꢅ,QSXWꢅ5HJLVWHUVꢇ

Bit 7: 7ꢆ6<1&ꢅPWM/Timer 1 Set/Reset mask

0: Set/Reset activated

3:0ꢃ7LPHUꢅ ꢂꢅ &RXQWHUꢅ +LJKꢅ ,QSXWꢅ 5HJLVWHU

ꢐ3:0ꢂB&2817B,1B+ꢑ

1: Set/Reset masked

Input Register 21 (015h) Read only

Reset Value: 0000 0000 (00h)

Bit 6: not used

7

0

Bit 5: 7ꢂ6<1&ꢅPWM/Timer 0 Set/Reset mask

0: Set/Reset activated

T0CI15 T0CI14 T0CI13 T0CI12 T0CI11 T0CI10 T0CI9

T0CI8

1: Set/Reset masked

Bit 4: 7ꢂ&ꢌ6ꢅPWM/Timer 0 Clock Source

0: Internal clock

Bit 7-0: 7ꢂ&,ꢆꢀꢓꢏꢅPWM/Timer 0 Counter MSB

1: External Clock from TCLK

In this register the current value of the Timer 0

Counter MSB can be read.

Bit 3-2: 67565&ꢅPWM/Timer 0 Start signal source

00: Internal from T0STRT bit

:DUQLQJꢀꢁ %RWKꢀ RIꢀ WKHꢀ 3:0[B&2817B,1B[

UHJLVWHUVꢀ PXVWꢀ EHꢀ DOZD\Vꢀ UHDGꢁꢀ 7Rꢀ DYRLGꢀ VLGH

HIIHFWVꢂꢀWKHꢀYDOXHVꢀVWRUHGꢀLQVLGHꢀWKHVHꢀUHJLVWHUVꢀDUH

IUR]HQꢂꢀ DQGꢀ QHZꢀ XSGDWHVꢀ FDQQRWꢀ EHꢀ VWRUHGꢂꢀ XQWLO

ERWKꢀWKHꢀYDOXHVꢀDUHꢀUHDGꢁꢀꢀ

01: External from TSTRT pin

10: Both internal and external

72/123

67ꢀꢁ)ꢀꢂꢂꢃ)ꢀꢂꢄ

3:0ꢃ7LPHUꢅ ꢂꢅ &RXQWHUꢅ /RZꢅ ,QSXWꢅ 5HJLVWHU

ꢐ3:0ꢂB&2817B,1B/ꢑ

3:0ꢃ7LPHUꢅ ꢂꢅ &DSWXUHꢅ +LJKꢅ ,QSXWꢅ 5HJLVWHU

ꢐ3:0ꢂB&$3785(B+ꢑ

Input Register 22 (016h) Read only

Reset Value: 0000 0000 (00h)

Input Register 24 (018h) Read only

Reset Value: 0000 0000 (00h)

7

0

7

0

T0CI7

T0CI6

T0CI5

T0CI4

T0CI3

T0CI2

T0CI1

T0CI0

T0CP15 T0CP14 T0CP13 T0CP12 T0CP11 T0CP10 T0CP9 T0CP8

Bit 7-0: 7ꢂ&3ꢆꢀꢓꢏꢅPWM/Timer 0 Capture MSB

Bit 7-0: 7ꢂ&,ꢈꢓꢂꢅPWM/Timer 0 Counter LSB

In this register the counter value after the last stop

can be read.

In this register the current value of the Timer 0

Counter LSB can be read.

:DUQLQJꢀꢁ %RWKꢀ RIꢀ WKHꢀ 3:0[B&2817B,1B[

UHJLVWHUVꢀ PXVWꢀ EHꢀ DOZD\Vꢀ UHDGꢁꢀ 7Rꢀ DYRLGꢀ VLGH

HIIHFWVꢂꢀWKHꢀYDOXHVꢀVWRUHGꢀLQVLGHꢀWKHVHꢀUHJLVWHUVꢀDUH

IUR]HQꢂꢀ DQGꢀ QHZꢀ XSGDWHVꢀ FDQQRWꢀ EHꢀ VWRUHGꢂꢀ XQWLO

ERWKꢀWKHꢀYDOXHVꢀDUHꢀUHDGꢁꢀꢀ

3:0ꢃ7LPHUꢅ ꢂꢅ &DSWXUHꢅ /RZꢅ ,QSXWꢅ 5HJLVWHU

ꢐ3:0ꢂB&$3785(B/ꢑ

Input Register 25 (019h) Read only

Reset Value: 0000 0000 (00h)

7

0

3:0ꢃ7LPHUꢅꢂꢅ6WDWXVꢅ5HJLVWHUꢅꢐ3:0ꢂB67$786ꢑ

Input Register 23 (017h) Read only

Reset Value: 0000 0000 (00h)

T0CP7 T0CP6 T0CP5 T0CP4 T0CP3 T0CP2 T0CP1 T0CP0

Bit 7-0: 7ꢂ&3ꢈꢓꢂꢅPWM/Timer 0 Capture LSB

7

0

In this register the counter value after the last stop

can be read.

-

T0OVFL T0OUT T0RST T0SST

Bit 7-4: Not Usedꢅ

Bit 3: 7ꢂ29)/ꢅPWMꢃTimer 0 counter overflow flag

0: no overflow occurred since last reset

1: overflow occurred

ꢆꢆꢇꢀꢇꢄꢅꢅ3:0ꢃ7LPHUꢅꢂꢅ2XWSXWꢅ5HJLVWHUVꢇ

3:0ꢃ7LPHUꢅ ꢂꢅ &RXQWHUꢅ +LJKꢅ 2XWSXWꢅ 5HJLVWHU

ꢐ3:0ꢂB&2817B287B+ꢑ

Bit 2: 7ꢂ287ꢅT0OUT pin value

0: T0OUT pin is at logical level 0

1: T0OUT pin is at logical level 1

Output Register 7 (07h) Write only

Reset Value: 0000 0000 (00h)

7

0

Bit 1: 7ꢂ567ꢅReset Status

0: PWM/Timer 0 is reset

1: PWM/Timer 0 is set

T0CO15 T0CO14 T0CO13 T0CO12 T0CO11 T0CO10 T0CO9 T0CO8

Bit 7-0: 7ꢂ&2ꢆꢀꢓꢏꢅPWM/Timer 0 Counter MSB

This register is used to write the Timer 0 Counter

value (MSB).

Bit 0: 7ꢂ667ꢅStart Status

0: PWM/Timer 0 is stopped

1: PWM/Timer 0 is running

1RWHꢀꢁWKLVꢀUHJLVWHUꢀLVꢀODWFKHGꢀDIWHUꢀZULWLQJꢀWKHꢀ/6%

SDUWꢀꢉ3:0B&2817B287B/ꢎꢀVHHꢀEHORZꢊꢁꢀ)RUꢀWKLV

UHDVRQꢀ WKLVꢀ UHJLVWHUꢀ PXVWꢀ EHꢀ ZULWWHQꢀ EHIRUHꢀ WKH

/6%ꢁ

73/123

67ꢀꢁ)ꢀꢂꢂꢃ)ꢀꢂꢄ

3:0ꢃ7LPHUꢅ ꢂꢅ &RXQWHUꢅ /RZꢅ 2XWSXWꢅ 5HJLVWHU

ꢐ3:0ꢂB&2817B287B/ꢑ

Output Register 8 (08h) Write only

Reset Value: 0000 0000 (00h)

1RWHꢀꢁ

E\ꢀ

ZULWLQJꢀ

WKLVꢀ

UHJLVWHUꢂꢀ

WKH

3:0ꢅB5(/2$'B[ꢀ FRXSOHꢀ LVꢀ ODWFKHGꢀ LQꢀ WKH

LQWHUQDOꢀUHJLVWHUVꢀRIꢀWKHꢀSHULSKHUDOVꢁꢀ)RUꢀWKLVꢀUHDVRQ

WKLVꢀUHJLVWHUꢀVKRXOGꢀEHꢀZULWWHQꢀDIWHUꢀWKHꢀ06%ꢀRQHꢁ

7

0

ꢆꢆꢇꢋꢅꢅ3:0ꢃ7LPHUꢅꢆꢅ5HJLVWHUꢅ'HVFULSWLRQ

T0CO7 T0CO6 T0CO5 T0CO4 T0CO3 T0CO2 T0CO1 T0CO0

The following registers are related to the use of the

PWM/Timer 1.

Bit 7-0: 7ꢂ&2ꢈꢓꢂꢅPWM/Timer 0 Counter LSB

ꢆꢆꢇꢋꢇꢆꢅꢅ3:0ꢃ7LPHUꢅꢆꢅ&RQILJXUDWLRQꢅ5HJLVWHUVꢇ

This register is used to write the Timer 0 Counter

value (LSB).

3:0ꢃ7LPHUꢅꢆꢅ&RQWUROꢅ5HJLVWHUꢅꢆꢅꢐ3:0ꢆB&5ꢆꢑ

Configuration Register 12 (0Ch) Read/Write

Reset Value: 0000 0000 (00h)

1RWHꢀꢁ

ZULWLQJꢀ

WKLVꢀ

UHJLVWHUꢂꢀ

WKH

3:0ꢅB&2817B287B[ꢀ FRXSOHꢀ LVꢀ ODWFKHGꢀ LQꢀ WKH

LQWHUQDOꢀ UHJLVWHUVꢀ RIꢀ WKHꢀ SHULSKHUDOVꢁꢀ )RUꢀ WKLV

UHDVRQꢂꢀ WKLVꢀ UHJLVWHUꢀ VKRXOGꢀ EHꢀ ZULWWHQꢀ DIWHUꢀ WKH

06%ꢀRQHꢁ

7

0

T1MOD T1IES

T0IEF

T1IER

-

T1STRT

-

T1RES

3:0ꢃ7LPHUꢅ ꢂꢅ 5HORDGꢅ +LJKꢅ 2XWSXWꢅ 5HJLVWHU

ꢐ3:0ꢂB5(/2$'B+ꢑ

Output Register 9 (09h) Write only

Reset Value: 1111 1111 (0FFh)

Bit 7: 7ꢆ02'ꢅPWM/Timer 1 Mode

0: Timer Mode

7

0

1: PWM Mode

T0REL15 T0REL14 T0REL13 T0REL12 T0REL11 T0REL10 T0REL9 T0REL8

Bit 6: 7ꢆ,(6ꢅInterrupt on Stop signal Enable

0: interrupt disabled

1: interrupt enabled

Bit 7-0: 7ꢂ5(/ꢆꢀꢓꢏꢅPWM/Timer 0 Reload MSB

Bit 5: 7ꢆ,()ꢅInterrupt on T1OUT falling Enable

0: interrupt disabled

This register is used to write the Timer 0 Reload

value (MSB).

1: interrupt enabled

1RWHꢀꢁWKLVꢀUHJLVWHUꢀLVꢀODWFKHGꢀDIWHUꢀZULWLQJꢀWKHꢀ/6%

SDUWꢀ ꢉ3:0ꢅB5(/2$'B/ꢎꢀ VHHꢀ EHORZꢊꢁꢀ )RUꢀ WKLV

UHDVRQꢂꢀ WKLVꢀ UHJLVWHUꢀ PXVWꢀ EHꢀ ZULWWHQꢀ EHIRUHꢀ WKH

/6%ꢁ

Bit 4: 7ꢆ,(5ꢅInterrupt on T1OUT rising Enable

0: interrupt disabled

1: interrupt enabled

3:0ꢃ7LPHUꢅ ꢂꢅ 5HORDGꢅ /RZꢅ 2XWSXWꢅ 5HJLVWHU

ꢐ3:0ꢂB5(/2$'B/ꢑ

Bit 3: not used: it must be left at reset status

Output Register 10 (0Ah) Write only

Reset Value: 1111 1111 (0FFh)

Bit 2: 7ꢆ6757ꢅPWM/Timer 1 Start bit

0: PWM/Timer 1 stopped

7

0

1: PWM/Timer 1 started

T0REL7 T0REL6 T0REL5 T0REL4 T0REL3 T0REL2 T0REL1 T0REL0

Bit 1: not used: it must be left at reset status

Bit 7-0: 7ꢂ5(/ꢈꢓꢂꢅPWM/Timer 0 Reload LSB

Bit 0: 7ꢆ5(6ꢅPWM/Timer 1 Reset bit

0: PWM/Timer 1 reset

This register is used to write the Timer 0 Reload

value (LSB).

1: PWM/Timer 1 set

74/123

67ꢀꢁ)ꢀꢂꢂꢃ)ꢀꢂꢄ

3:0ꢃ7LPHUꢅꢆꢅ&RQWUROꢅ5HJLVWHUꢅꢁꢅꢐ3:0ꢆB&5ꢁꢑ

Configuration Register 13 (0Dh) Read/Write

Reset Value: 0000 0000 (00h)

Bit 7-0: 7ꢆ&,ꢈꢓꢂꢅPWM/Timer 1 Counter LSB

In this register the current value of the Timer 1

Counter LSB can be read.

:DUQLQJꢀꢁ %RWKꢀ RIꢀ WKHꢀ 3:0[B&2817B,1B[

UHJLVWHUVꢀ PXVWꢀ EHꢀ DOZD\Vꢀ UHDGꢁꢀ 7Rꢀ DYRLGꢀ VLGH

HIIHFWVꢂꢀWKHꢀYDOXHVꢀVWRUHGꢀLQVLGHꢀWKHVHꢀUHJLVWHUVꢀDUH

IUR]HQꢂꢀ DQGꢀ QHZꢀ XSGDWHVꢀ FDQQRWꢀ EHꢀ VWRUHGꢂꢀ XQWLO

ERWKꢀWKHꢀYDOXHVꢀDUHꢀUHDGꢁꢀꢀ

7

4

0

-

T1WAV

T1PRESC

Bit 7-6: Not Usedꢅ

3:0ꢃ7LPHUꢅꢆꢅ6WDWXVꢅ5HJLVWHUꢅꢐ3:0ꢆB67$786ꢑ

Input Register 28 (01Ch) Read only

Reset Value: 0000 0000 (00h)

Bit 5: 7ꢆ:$9ꢅT1OUT Waveform

0: pulse (type2)

1: square (type1)

7

0

-

T1OVFL T1OUT T1RST T1SST

Bit 4-0: 7ꢆ35(6&ꢅPWM/Timer 1 Prescaler

The PWM/Timer 1 clock is divided by a

factor equal to 2^T1PRESC. 7KHꢅ PD[LPXP

YDOXHꢅ DOORZHGꢅ IRUꢅ 7ꢆ35(6&ꢅ LVꢅ ꢆꢂꢂꢂꢂ

ꢐꢂꢆꢂKꢑ.

Bit 7-4: Not Usedꢅ

Bit 3: 7ꢆ29)/ꢅPWMꢃTimer 1 counter overflow flag

0: no overflow occurred since last reset

1: overflow occurred

ꢆꢆꢇꢋꢇꢁꢅꢅ3:0ꢃ7LPHUꢅꢆꢅ,QSXWꢅ5HJLVWHUVꢇ

Bit 2: 7ꢆ287ꢅT1OUT pin value

0: T1OUT pin is at logical level 0

1: T1OUT pin is at logical level 1

3:0ꢃ7LPHUꢅ ꢆꢅ &RXQWHUꢅ +LJKꢅ ,QSXWꢅ 5HJLVWHU

ꢐ3:0ꢆB&2817B,1B+ꢑ

Input Register 26 (01Ah) Read only

Reset Value: 0000 0000 (00h)

Bit 1: 7ꢆ567ꢅReset Status

0: PWM/Timer 1 is reset

1: PWM/Timer 1 is set

7

0

T1CI15 T1CI14 T1CI13 T1CI12 T1CI11 T1CI10 T1CI9

T1CI8

Bit 0: 7ꢆ667ꢅStart Status

0: PWM/Timer 1 is stopped

1: PWM/Timer 1 is running

Bit 7-0: 7ꢆ&,ꢆꢀꢓꢏꢅPWM/Timer 1 Counter MSB

In this register the current value of the Timer 1

Counter MSB can be read.

:DUQLQJꢀꢁ %RWKꢀ RIꢀ WKHꢀ 3:0[B&2817B,1B[

UHJLVWHUVꢀ PXVWꢀ EHꢀ DOZD\Vꢀ UHDGꢁꢀ 7Rꢀ DYRLGꢀ VLGH

HIIHFWVꢂꢀWKHꢀYDOXHVꢀVWRUHGꢀLQVLGHꢀWKHVHꢀUHJLVWHUVꢀDUH

IUR]HQꢂꢀ DQGꢀ QHZꢀ XSGDWHVꢀ FDQQRWꢀ EHꢀ VWRUHGꢂꢀ XQWLO

ERWKꢀWKHꢀYDOXHVꢀDUHꢀUHDGꢁꢀꢀ

3:0ꢃ7LPHUꢅ ꢆꢅ &DSWXUHꢅ +LJKꢅ ,QSXWꢅ 5HJLVWHU

ꢐ3:0ꢆB&$3785(B+ꢑ

Input Register 29 (01Dh) Read only

Reset Value: 0000 0000 (00h)

7

0

3:0ꢃ7LPHUꢅ ꢆꢅ &RXQWHUꢅ /RZꢅ ,QSXWꢅ 5HJLVWHU

ꢐ3:0ꢆB&2817B,1B/ꢑ

T1CP15 T1CP14 T1CP13 T1CP12 T1CP11 T1CP10 T1CP9 T1CP8

Input Register 27 (01Bh) Read only

Reset Value: 0000 0000 (00h)

Bit 7-0: 7ꢆ&3ꢆꢀꢓꢏꢅPWM/Timer 1 Capture MSB

7

0

In this register the counter value after the last stop

can be read.

T1CI7

T1CI6

T1CI5

T1CI4

T1CI3

T1CI2

T1CI1

T1CI0

75/123

67ꢀꢁ)ꢀꢂꢂꢃ)ꢀꢂꢄ

3:0ꢃ7LPHUꢅ ꢆꢅ &DSWXUHꢅ /RZꢅ ,QSXWꢅ 5HJLVWHU

ꢐ3:0ꢆB&$3785(B/ꢑ

Input Register 30 (01Eh) Read only

Reset Value: 0000 0000 (00h)

1RWHꢀꢁ

E\ꢀ

ZULWLQJꢀ

WKLVꢀ

UHJLVWHUꢂꢀ

WKH

3:0ꢍB&2817B287B[ꢀ FRXSOHꢀ LVꢀ ODWFKHGꢀ LQꢀ WKH

LQWHUQDOꢀUHJLVWHUVꢀRIꢀWKHꢀSHULSKHUDOVꢁꢀ)RUꢀWKLVꢀUHDVRQ

WKLVꢀUHJLVWHUꢀVKRXOGꢀEHꢀZULWWHQꢀDIWHUꢀWKHꢀ06%ꢀRQHꢁ

3:0ꢃ7LPHUꢅ ꢆꢅ 5HORDGꢅ +LJKꢅ 2XWSXWꢅ 5HJLVWHU

ꢐ3:0ꢆB5(/2$'B+ꢑ

7

0

Output Register 13 (0Dh) Write only

Reset Value: 1111 1111 (0FFh)

T1CP7 T1CP6 T1CP5 T1CP4 T1CP3 T1CP2 T1CP1 T1CP0

7

0

Bit 7-0: 7ꢆ&3ꢈꢓꢂꢅPWM/Timer 1 Capture LSB

T1REL15 T1REL14 T1REL13 T1REL12 T1REL11 T1REL10 T1REL9 T1REL8

In this register the counter value after the last stop

can be read.

Bit 7-0: 7ꢆ5(/ꢆꢀꢓꢏꢅPWM/Timer 1 Reload MSB

This register is used to write the Timer 1 Reload

value (MSB).

ꢆꢆꢇꢋꢇꢄꢅꢅ3:0ꢃ7LPHUꢅꢆꢅ2XWSXWꢅ5HJLVWHUVꢇ

1RWHꢀꢁWKLVꢀUHJLVWHUꢀLVꢀODWFKHGꢀDIWHUꢀZULWLQJꢀWKHꢀ/6%

SDUWꢀ ꢉ3:0ꢍB5(/2$'B/ꢎꢀ VHHꢀ EHORZꢊꢁꢀ )RUꢀ WKLV

UHDVRQꢂꢀ WKLVꢀ UHJLVWHUꢀ PXVWꢀ EHꢀ ZULWWHQꢀ EHIRUHꢀ WKH

/6%ꢁ

3:0ꢃ7LPHUꢅ ꢆꢅ &RXQWHUꢅ +LJKꢅ 2XWSXWꢅ 5HJLVWHU

ꢐ3:0ꢆB&2817B287B+ꢑ

Output Register 11 (0Bh) Write only

Reset Value: 0000 0000 (00h)

7

0

3:0ꢃ7LPHUꢅ ꢆꢅ 5HORDGꢅ /RZꢅ 2XWSXWꢅ 5HJLVWHU

ꢐ3:0ꢂB5(/2$'B/ꢑ

Output Register 14 (0Eh) Write only

Reset Value: 1111 1111 (0FFh)

T1CO15 T1CO14 T1CO13 T1CO12 T1CO11 T1CO10 T1CO9 T1CO8

Bit 7-0: 7ꢆ&2ꢆꢀꢓꢏꢅPWM/Timer 1 Counter MSB

7

0

T1REL7 T1REL6 T1REL5 T1REL4 T1REL3 T1REL2 T1REL1 T01REL0

This register is used to write the Timer 1 Counter

value (MSB).

1RWHꢀꢁWKLVꢀUHJLVWHUꢀLVꢀODWFKHGꢀDIWHUꢀZULWLQJꢀWKHꢀ/6%

SDUWꢀꢉ3:0ꢍB&2817B287B/ꢎꢀVHHꢀEHORZꢊꢁꢀ)RUꢀWKLV

UHDVRQꢂꢀ WKLVꢀ UHJLVWHUꢀ PXVWꢀ EHꢀ ZULWWHQꢀ EHIRUHꢀ WKH

/6%ꢁ

Bit 7-0: 7ꢆ5(/ꢈꢓꢂꢅPWM/Timer 1 Reload LSB

This register is used to write the Timer 1 Reload

value (LSB).

3:0ꢃ7LPHUꢅ ꢆꢅ &RXQWHUꢅ /RZꢅ 2XWSXWꢅ 5HJLVWHU

ꢐ3:0ꢆB&2817B287B/ꢑ

1RWHꢀꢁ

E\ꢀ

ZULWLQJꢀ

WKLVꢀ

UHJLVWHUꢂꢀ

WKH

3:0ꢍB5(/2$'B[ꢀ FRXSOHꢀ LVꢀ ODWFKHGꢀ LQꢀ WKH

LQWHUQDOꢀ UHJLVWHUVꢀ RIꢀ WKHꢀ SHULSKHUDOVꢁꢀ )RUꢀ WKLV

UHDVRQꢂꢀ WKLVꢀ UHJLVWHUꢀ VKRXOGꢀ EHꢀ ZULWWHQꢀ DIWHUꢀ WKH

06%ꢀRQHꢁ

Output Register 12 (0Ch) Write only

Reset Value: 0000 0000 (00h)

7

0

T1CO7 T1CO6 T1CO5 T1CO4 T1CO3 T1CO2 T1CO1 T1CO0

Bit 7-0: 7ꢆ&2ꢈꢓꢂꢅPWM/Timer 1 Counter LSB

This register is used to write the Timer 1 Counter

value (LSB).

76/123

67ꢀꢁ)ꢀꢂꢂꢃ)ꢀꢂꢄ

ꢆꢁꢅꢅ, &ꢅ%86ꢅ,17(5)$&(ꢅꢐ, &ꢑ

ꢆꢁꢇꢆꢅꢅ,QWURGXFWLRQ

ꢆꢁꢇꢄꢅꢅ*HQHUDOꢅ'HVFULSWLRQ

In addition to receiving and transmitting data, this

interface converts it from serial to parallel format

and vice versa, using either an interrupt or polled

handshake. The interrupts are enabled or disabled

via software. The interface is connected to the I²C

bus by a data pin (SDA) and by a clock pin (SCL).

The interface can be connected both with a

standard I²C bus and a Fast I²C bus. This

selection is made via software.

The I²C Bus Interface serves as an interface

between the microcontroller and the serial I²C bus,

providing both multimaster and slave functions and

controls all I²C bus-specific sequencing, protocol,

arbitration and timing. The

I²Bus Interface

supports fast I²C mode (400kHz).

ꢆꢁꢇꢁꢅꢅ0DLQꢅ)HDWXUHV

I Parallel-bus/I²C protocol converter

ꢆꢁꢇꢄꢇꢆꢅꢅ0RGHꢅ6HOHFWLRQꢇ

I Multi-master capability

The interface can operate in the following four

modes:

– Slave transmitter/receiver

– Master transmitter/receiver

By default, it operates in slave mode.

I 7-bit/10-bit Addressing

I Transmitter/Receiver flag

I End-of-byte transmission flag

I Transfer problem detection

I Aknowledge Failure Flag

The interface automatically switches from slave to

master after it generates a START condition and

from master to slave in case of arbitration loss or a

I²C Master Features:

STOP

generation,

providing

Multi-Master

capability.

I Clock generation

I I²C bus busy flag

ꢆꢁꢇꢄꢇꢁꢅꢅ&RPPXQLFDWLRQꢅ)ORZꢇ

I Arbitration Lost Flag

In Master mode, Communication Flow initiates

data transfer and generates the clock signal. A

serial data transfer always begins with a start

condition and ends with a stop condition. Both start

and stop conditions are generated in master mode

by software.

I End of byte transmission flag

I Transmitter/Receiver Flag

I Start bit detection flag

I Start and Stop generation

In Slave mode the interface is capable of

recognizing its own address (7 or 10-bit) and the

General Call address. The General Call address

detection may be enabled or disabled by software.

I²C Slave Features:

I Stop bit detection

I I²C bus busy flag

Data and addresses are transferred as 8-bit bytes,

(MSB first). The first byte following the start

condition is the address (one in 7-bit mode, two in

10-bit mode), which is always transmitted in

Master mode.A 9th clock pulse follows the 8 clock

cycles of a byte transfer, during which the receiver

must send an acknowledge bit to the transmitter.

Refer to Figure 12.1.

I Detection of misplaced start or stop condition

I Programmable I²C Address detection

I Transfer problem detection

I End-of-byte transmission flag

I Transmitter/Receiver flag

)LJXUHꢅꢆꢁꢇꢆꢅꢅꢅ, &ꢅ%86ꢅ3URWRFRO

SDA

MSB

ACK

SCL

1

2

8

9

START

STOP

CONDITION

77/123

67ꢀꢁ)ꢀꢂꢂꢃ)ꢀꢂꢄ

Acknowledge may be enabled and disabled via

software.

The I²C interface address and/or general call

address can be selected via software.

When the I²C cell is enabled, the SDA and SCL

pins must be configured as open-drain with or

without pull-up. The value of the external pull-up

resistance used depends on the application.

The speed of the I²C interface may be selected

between Standard (0-100KHz) and Fast I²C (100-

400KHz).

ꢆꢁꢇꢊꢅꢅ)XQFWLRQDOꢅ'HVFULSWLRQ

By default the I²C interface operates in Slave

mode (M/SL bit is cleared) except when it initiates

a transmit or receive sequence.

ꢆꢁꢇꢄꢇꢄꢅꢅ6'$ꢃ6&/ꢅ/LQHꢅ&RQWUROꢇ

First, the interface frequency must be configured

using the related bits of the Configuration

Registers.

7UDQVPLWWHUꢀPRGH: the interface holds the clock line

low before transmission, in order to wait for the

microcontroller to write the byte in the Data

Register.

ꢆꢁꢇꢊꢇꢆꢅꢅ6ODYHꢅ0RGHꢇ

5HFHLYHUꢀPRGH: the interface holds the clock line

low after reception to wait for the microcontroller to

read the byte in the Data Register.

SCL frequency is controlled by a programmable

clock divider which depends on the I²C bus mode.

As soon as a start condition is detected, the

address is received from the SDA line and sent to

the shift register; then it is compared with the

address of the interface or the General Call

address (if selected by software).

)LJXUHꢅꢆꢁꢇꢁꢅꢅꢅ, &ꢅ,QWHUIDFHꢅ%ORFNꢅ'LDJUDP

DATA REGISTER

SDA

DATA CONTROL

SDA

DATA SHIFT REGISTER

COMPARATOR

OWN ADDRESS REGISTER (OAR)

SCL

CLOCK CONTROL

SCL

CLOCK CONTROL REGISTER (I2C_CCR)

CONTROL REGISTER (I2C_CR)

STATUS REGISTER 1 (I2C_SR1)

STATUS REGISTER 2 (I2C_SR2)

CONTROL LOGIC

INTERRUPT

78/123

67ꢀꢁ)ꢀꢂꢂꢃ)ꢀꢂꢄ

1RWHꢀꢁ,QꢀꢍꢅꢌELWꢀDGGUHVVLQJꢀPRGHꢂꢀWKHꢀFRPSDULVRQ

LQFOXGHVꢀWKHꢀKHDGHUꢀE\WHꢀꢉꢍꢍꢍꢍꢅ[[ꢅꢊꢀZKHUHꢀ[[ꢀDUH

WKHꢀWZRꢀPRVWꢀVLJQLILFDQWꢀELWVꢀRIꢀWKHꢀDGGUHVVꢁ

&ORVLQJꢅVODYHꢅFRPPXQLFDWLRQ

After the last data byte is transferred a Stop

Condition is generated by the master. The

interface detects this condition and sets:

+HDGHUꢀPDWFKHGꢅ(10-bit mode only): the interface

generates an acknowledgement pulse if the ACK

bit is set.

– EVF and STOPF bits with an interrupt if the ITE

bit is set.

Afterwards, the interface waits for a read of the

I2C_SR2 register (see Figure 12.3 Transfer

sequencing EV4).

$GGUHVVꢀQRWꢀPDWFKHG: the interface ignores it and

waits for another Start condition.

$GGUHVVꢀ PDWFKHG: the interface generates in

sequence:

(UURUꢅ&DVHV

– Acknowledge pulse if the ACK bit is set.

– %(55: Detection of a Stop or a Start condition

during a byte transfer. In this case, the EVF and

the BERR bits are set with an interrupt if the ITE

bit is set.

If it is a Stop then the interface discards the data,

releases the lines and waits for another Start

condition.

– EVF and ADSL bits are set with an interrupt if the

ITE bit is set.

Afterwards, the interface waits for the I2C_SR1

register to be read, KROGLQJꢅWKHꢅ6&/ꢅOLQHꢅORZꢅ(see

Figure 12.3 Transfer sequencing EV1).

Next, in 7-bit mode read the I2C_IN register to

determine from the least significant bit (Data

Direction Bit) if the slave must enter Receiver or

Transmitter mode.

If it is a Start then the interface discards the data

and waits for the next slave address on the bus.

– $): Detection of a non-acknowledge bit. In this

case, the EVF and AF bits are set with an inter-

rupt if the ITE bit is set.

In 10-bit mode, after receiving the address

sequence the slave is always in receive mode. It

will enter transmit mode on receiving a repeated

Start condition followed by the header sequence

with matching address bits and the least significant

bit set (11110xx1).

1RWHꢀꢁ,QꢀERWKꢀFDVHVꢂꢀWKHꢀ6&/ꢀOLQHꢀLVꢀQRWꢀKHOGꢀORZꢑ

KRZHYHUꢂꢀ6'$ꢀOLQHꢀFDQꢀUHPDLQꢀORZꢀGXHꢀWRꢀSRVVLEOH

©ꢅªꢀELWVꢀWUDQVPLWWHGꢀODVWꢁꢀ$WꢀWKLVꢀSRLQWꢂꢀERWKꢀOLQHV

PXVWꢀEHꢀUHOHDVHGꢀE\ꢀVRIWZDUHꢁ

6ODYHꢅ5HFHLYHU

Following reception of the address and after the

I2C_SR1 register has been read, the slave

receives bytes from the SDA line into the I2C_IN

register via the internal shift register. After each

byte, the interface generates the following in

sequence:

+RZꢅWRꢅUHOHDVHꢅWKHꢅ6'$ꢅꢃꢅ6&/ꢅOLQHV

Set and subsequently clear the STOP bit while

BTF is set. The SDA/SCL lines are released after

the current byte is transferred.

– Acknowledge pulse if the ACK bit is set

– EVF and BTF bits are set with an interrupt if the

ꢆꢁꢇꢊꢇꢁꢅꢅ0DVWHUꢅ0RGHꢇ

ITE bit is set.

To switch from default Slave mode to Master mode

a Start condition generation is needed.

Afterwards, the interface waits for the I2C_SR1

register to be read followed by a read of the I2C_IN

register, KROGLQJ WKHꢅ 6&/ꢅ OLQHꢅ ORZꢅ (see Figure

12.3 Transfer sequencing EV2).

6WDUWꢅFRQGLWLRQ

Setting the START bit while the BUSY bit is

cleared causes the interface to switch to Master

mode (M/SL bit set) and generates a Start

condition.

Once the Start condition is sent:

– The EVF and SB bits are set by hardware with

6ODYHꢅ7UDQVPLWWHU

Following the address reception and after the

I2C_SR1 register has been read, the slave sends

bytes from the I2C_OUT register to the SDA line

via the internal shift register.

The slave waits for a read of the I2C_SR1 register

followed by a write in the I2C_OUT register,

KROGLQJꢅ WKHꢅ 6&/ꢅ OLQHꢅ ORZ (see Figure 12.3

Transfer sequencing EV3).

an interrupt if the ITE bit is set.

Afterwards, the master waits for a read of the

I2C_SR1 register followed by a write in the

I2C_OUT register with the Slave address, KROGLQJ

WKHꢅ 6&/ꢅ OLQHꢅ ORZꢅ (see Figure 12.3 Transfer

sequencing EV5).

When the acknowledge pulse is received:

– The EVF and BTF bits are set by hardware with

an interrupt if the ITE bit is set.

79/123

67ꢀꢁ)ꢀꢂꢂꢃ)ꢀꢂꢄ

6ODYHꢅDGGUHVVꢅWUDQVPLVVLRQ

At this point, the slave address is sent to the SDA

line via the internal shift register.

In order to close the communication: before

reading the last byte from the I2C_IN register, set

the STOP bit to generate the Stop condition. The

interface automatically goes back to slave mode

(M/SL bit cleared).

In 7-bit addressing mode, one address byte is sent.

In 10-bit addressing mode, sending the first byte

including the header sequence causes the

following event:

1RWHꢀꢁ,QꢀRUGHUꢀWRꢀJHQHUDWHꢀWKHꢀQRQꢌDFNQRZOHGJH

SXOVHꢀDIWHUꢀWKHꢀODVWꢀGDWDꢀE\WHꢀUHFHLYHGꢂꢀWKHꢀ$&CꢀELW

PXVWꢀEHꢀFOHDUHGꢀMXVWꢀEHIRUHꢀUHDGLQJꢀWKHꢀVHFRQGꢀODVW

GDWDꢀE\WHꢁ

– The EVF and ADD10 bit is set by hardware with

interrupt generation if the ITE bit is set.

Afterwards, the master waits for a read of the

I2C_SR1 register followed by a write in the

I2C_OUT register, KROGLQJꢅWKHꢅ6&/ꢅOLQHꢅORZ (see

Figure 12.3 Transfer sequencing EV9).

The second address byte is sent by the interface.

After completion of this transfer (and acknowledge

from the slave if the ACK bit is set):

0DVWHUꢅ7UDQVPLWWHU

Following the address transmission and after the

I2C_SR1 register has been read, the master sends

bytes from the I2C_OUT register to the SDA line

via the internal shift register.

The master waits for a read of the I2C_SR1

register followed by a write in the I2C_OUT

register, KROGLQJꢅ WKH 6&/ꢅ OLQHꢅ ORZꢅ (see Figure

12.3 Transfer sequencing EV8).

– The EVF bit is set by hardware with interrupt

generation if the ITE bit is set.

Afterwards, the master waits for a read of the

I2C_SR1 register followed by a write in the

I2C_CR register (for example set PE bit), KROGLQJ

WKHꢅ 6&/ꢅ OLQHꢅ ORZ (see Figure 12.3 Transfer

sequencing EV6).

When the acknowledge bit is received, the

interface sets:

– EVF and BTF bits with an interrupt if the ITE bit

is set.

Next, the master must enter Receiver or

Transmitter mode.

In order to close the communication: after writing

the last byte to the I2C_OUT register, set the

STOP bit to generate the Stop condition. The

interface automatically returns to slave mode (M/

SL bit cleared).

1RWHꢀꢁ,QꢀꢍꢅꢌELWꢀDGGUHVVLQJꢀPRGHꢂꢀLQꢀRUGHUꢀWRꢀVZLWFK

WKHꢀ PDVWHUꢀ WRꢀ 5HFHLYHUꢀ PRGHꢂꢀ VRIWZDUHꢀ PXVW

JHQHUDWHꢀDꢀUHSHDWHGꢀ6WDUWꢀFRQGLWLRQꢀDQGꢀUHVHQGꢀWKH

KHDGHUꢀVHTXHQFHꢀZLWKꢀWKHꢀOHDVWꢀVLJQLILFDQWꢀELWꢀVHW

ꢉꢍꢍꢍꢍꢅ[[ꢍꢊꢁ

(UURUꢅ&DVHV

– %(55: Detection of a Stop or a Start condition

during a byte transfer. In this case, the EVF and

BERR bits are set by hardware with an interrupt

if ITE is set.

– $): Detection of a non-acknowledge bit. In this

case, the EVF and AF bits are set by hardware

with an interrupt if the ITE bit is set. To resume,

set the START or STOP bit.

– $5/2: Detection of an arbitration lost condition.

In this case the ARLO bit is set by hardware

(with an interrupt if the ITE bit is set and the in-

terface automatically goes back to slave mode

(the M/SL bit is cleared).

0DVWHUꢅ5HFHLYHU

Following the address transmission and after

I2C_SR1 and I2C_CR registers have been

accessed, the master receives bytes from the SDA

line into the I2C_IN register via the internal shift

register. After each byte the interface generates in

sequence:

– Acknowledge pulse if the ACK bit is set

– EVFand BTF bits are set by hardware with an in-

terrupt if the ITE bit is set.

Afterwards, the interface waits for a read of the

I2C_SR1 register followed by a read of the I2C_IN

register, KROGLQJꢅ WKHꢅ 6&/ꢅ OLQHꢅ ORZꢅ (see Figure

12.3 Transfer sequencing EV7).

1RWHꢀꢁ,QꢀDOOꢀWKHVHꢀFDVHVꢂꢀWKHꢀ6&/ꢀOLQHꢀLVꢀQRWꢀKHOG

ORZꢑꢀKRZHYHUꢂꢀWKHꢀ6'$ꢀOLQHꢀFDQꢀUHPDLQꢀORZꢀGXHꢀWR

SRVVLEOHꢀ©ꢅªꢀELWVꢀWUDQVPLWWHGꢀODVWꢁꢀ%RWKꢀOLQHVꢀꢀPXVW

EHꢀUHOHDVHGꢀYLDꢀVRIWZDUHꢁ

80/123

67ꢀꢁ)ꢀꢂꢂꢃ)ꢀꢂꢄ

)LJXUHꢅꢆꢁꢇꢄꢅꢅ7UDQIHUꢅ6HTXHQFLQJ

ꢈꢓELWꢅ6ODYHꢅUHFHLYHUꢒ

S

Address A

Data1

A

Data2

A

DataN

A

P

.....

EV1

EV2

EV4

ꢈꢓELWꢅ6ODYHꢅWUDQVPLWWHUꢒ

S

Address A

Data1

A

NA

P

EV1

EV3

A

EV3

A

EV3-1

EV4

ꢈꢓELWꢅ0DVWHUꢅUHFHLYHUꢒ

S

Address

A

Data1

Data2

DataN NA

DataN

P

.....

EV5

EV6

EV7

A

EV7

A

EV7

A

ꢈꢓELWꢅ0DVWHUꢅWUDQVPLWWHUꢒ

S

Address

A

Data1

Data2

.....

P

.....

EV5

EV6 EV8

EV8

ꢆꢂꢓELWꢅ6ODYHꢅUHFHLYHUꢒ

S

Header

A

Address A

A

DataN

A

P

EV1

A

EV2

A

EV2

EV4

ꢆꢂꢓELWꢅ6ODYHꢅWUDQVPLWWHUꢒ

S

Header

Data1

DataN

NA

P

r

.....

A

EV1

EV3

EV3-1

EV4

EV8

EV7

ꢆꢂꢓELWꢅ0DVWHUꢅWUDQVPLWWHUꢒ

S

Header

A

Address A

Data1

DataN

A

P

.....

EV5

EV9

EV6 EV8

A

EV8

ꢆꢂꢓELWꢅ0DVWHUꢅUHFHLYHUꢒ

S

Header

Data1

A

P

r

.....

EV5

EV6

EV7

Legend:

S=Start, P=Stop, A=Acknowledge, NA=Non-acknowledge, S_r=Intermediate Start without a previous Sto

EVx=Event (with interrupt if ITE=1)

EV1: EVF=1, ADSL=1, cleared by reading I2C_SR1 register.

EV2: EVF=1, BTF=1, cleared by reading I2C_SR1 register followed by reading I2C_IN register.

EV3: EVF=1, BTF=1, cleared by reading I2C_SR1 register followed by writing I2C_OUT register.

EV3-1: EVF=1, AF=1, BTF=1, SCL=0; AF is cleared by reading I2C_SR2. BTF is cleared

by releasing the lines (STOP=1,STOP=0) or by readyng I2C_SR1 and writing I2C_OUT register

(I2C_OUT=FFh).Note: If lines are released by STOP=1, STOP=0, the subsequent EV4 is not seen.

I2C_SR1 and I2C_SR2 registers can be read only after the falling edge of the ninth data clock cycle

EV4: EVF=1, STOPF=1, cleared by reading I2C_SR2 register.

EV5: EVF=1, SB=1, cleared by reading I2C_SR1 register followed by writing I2C_OUT register.

EV6: EVF=1, cleared by reading I2C_SR1 register followed by writing I2C_CR (for example PE=1)

EV7: EVF=1, BTF=1, cleared by reading I2C_SR1 register followed by reading I2C_IN register.

EV8: EVF=1, BTF=1, cleared by reading I2C_SR1, followed by writing I2C_OUT register or an S_r.

EV9: EVF=1, ADD10=1, cleared by reading I2C_SR1 register followed by writing I2C_OUT register

81/123

67ꢀꢁ)ꢀꢂꢂꢃ)ꢀꢂꢄ

)LJXUHꢅꢆꢁꢇꢊꢅꢅ(YHQWꢅ)ODJVꢅDQGꢅ,QWHUUXSWꢅ*HQHUDWLRQ

ITE

ADD10

BTF

ADSL

SB

INTERRUPT

EVF

AF

STOPF

ARLO

BERR

*

* EVF can also be set by EV6 or an error from the I2C_SR2 register.

10-bit Address Sent Event (Master Mode)

End of Byte Transfer Event

ADD10

BTF

Yes

No

Address Matched Event (Slave Mode)

Start Bit Generation Event (Master Mode)

Acknowledge Failure Event

ADSEL

SB

ITE

AF

Stop Detection Event (Slave Mode)

Arbitration Lost Event (Multimaster configuration)

Bus Error Event

STOPF

ARLO

BERR

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82/123

67ꢀꢁ)ꢀꢂꢂꢃ)ꢀꢂꢄ

ꢆꢁꢇꢀꢅꢅ5HJLVWHUꢅ'HVFULSWLRQ

– In Slave Mode

In the following sections describe the registers

0: No Start generation

1: Start generation when the bus is free

used by the I²C Interface are described.

ꢆꢁꢇꢀꢇꢆꢅꢅ, &ꢅ,QWHUIDFHꢅ&RQILJXUDWLRQꢅ5HJLVWHUVꢇ

Bit 2: $&ꢌꢅAcknowledge enable

This bit is set and cleared by software. It is

also cleared by hardware when the interface

is disabled (PE=0).

, &ꢅ&RQWUROꢅ5HJLVWHUꢅꢐ,ꢁ&B&5ꢑ

Configuration Register 16 (010h) Read/Write

Reset Value: 0000 0000 (00h)

0: No acknowledge returned

1: Acknowledge returned after an address

byte or a data byte is received

7

0

-

PE

ENGC START

ACK

STOP

ITE

Bit 1: 6723ꢅGeneration of a Stop Condition

This bit is set and cleared by software. It is

also cleared by hardware in master mode.

Note: This bit is not cleared when the

interface is disabled (PE=0).

Bit 7-6: Not UsedꢇꢅThey must be held to 0.ꢅ

Bit 5: 3(ꢅPeripheral Enable.

This bit is set and cleared by software

0: peripheral disabled

– In Master Mode

0: No Stop generation

1: peripheral enabled

1: Stop generation after the current byte

transfer or after the current Start condition

is sent. The STOP bit is cleared by

hardware when the Stop condition is sent.

1RWHVꢀꢁ

– When PE=0, all the bits of the I2C_CR register

and the SR register except the Stop bit are reset.

All outputs are released while PE=0

– In Slave Mode

– When PE=1, the corresponding I/O pins are se-

0: No actions performed

lected by hardware as alternate functions.

– To enable the I²C interface, write the I2C_CR

register 7:,&(ꢅwith PE=1 as the first write only

activates the interface (only PE is set).

1: Release the SCL and SDA lines after the

last byte transfer (BTF=1) in slave

transmitter mode. In this mode the STOP

bit has to be cleared by software.

Bit 4: (1*&ꢅEnable General Call

Bit 0: ,7(ꢅInterrupt Enable

0: Interrupt disabled

1: Interrupt enabled

This bit is set and cleared by software. It is

also cleared by hardware when the interface

is disabled (PE=0).

0: General Call disabled

1: General Call enabled

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, &ꢅ&ORFNꢅ&RQWUROꢅ5HJLVWHUꢅꢐ,ꢁ&B&&5ꢑ

Configuration Register 17 (011h) Read/Write

Reset Value: 0000 0000 (00h)

Bit 3: 67$57ꢅGeneration of a Start Condition

This bit is set and cleared by software. It is

also cleared by hardware when the interface

is disabled (PE=0) or when the Start

condition is sent (with interrupt generation if

ITE=1).

7

0

FM/SM

CC6

CC5

CC4

CC3

CC2

CC1

CC0

Bit 7: )0ꢃ60ꢅFast/Standard I²C Mode.

– In Master Mode

This bit is set and cleared by software. It is

not cleared when the interface is disabled

(PE=0).

0: No Start generation

1: Repeated Start generation

83/123

67ꢀꢁ)ꢀꢂꢂꢃ)ꢀꢂꢄ

1: Standard I²C Mode (recommended up to 100

kHz)

0: Fast I²C Mode (recommended up to 400 kHz)

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Configuration Register 19 (013h) Read/Write

Reset Value: 0000 0000 (00h)

7

2

0

-

Bit 6-0: &&ꢋꢓ&&ꢂꢅ7-bit clock divider

These bits select the speed of the bus (F_SCL

)

-

ADD9

ADD8

depending on the I²C mode. They are not

cleared when the interface is disabled

(PE=0). The speed can be computed as

follows:

Bit 7-3: Not Usedꢅ

bit 2-1: $''ꢉꢓ$''ꢏ Interface address.

– Standard mode (FM/SM=1): F_SCL<= 100kHz

F_SCL= f_CPU/(3x[CC6..CC0]+11)

– Fast mode (FM/SM=0): F_SCL> 100kHz

F_SCL= f_CPU/(2x[CC6..CC0]+9)

These are the most significant bits of th I²C

bus address of the interface (10-bit mode

only). They are not cleared when the

interface is disabled (PE=0).

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EHꢀFRQILJXUHGꢀZLWKꢀDꢀYDOXHꢀ! ꢀꢇꢀIRUꢀWKHꢀ6WDQGDUG

PRGHꢀDQGꢀ! ꢄꢀIRUꢀWKHꢀ)DVWꢀPRGHꢁ

Bit 0: Reserved, it must be left to 0.ꢅ

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Configuration Register 18 (012h) Read/Write

Reset Value: 0000 0000 (00h)

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Input Register 6 (06h) Read only

Reset Value: 0000 0000 (00h)

7

0

7

0

ADD7

ADD6

ADD5

ADD4

ADD3

ADD2

ADD1

ADD0

I2CDI7 I2CDI6 I2CDI5 I2CDI4 I2CDI3 I2CDI2 I2CDI1 I2CDI0

7-bit Addressing Mode

bit 7-1: $''ꢈꢓ$''ꢆ Interface address.

bit 7-0: ,ꢁ&',ꢈꢓ,ꢁ&',ꢂ Received data.

These bits define the I²C bus address of the

interface. They are not cleared when the

interface is disabled (PE=0).

These bits contain the byte to be received from the

bus in Receiver mode: the first data byte is

received automatically in the I2C_IN register using

the least significant bit of the address.

Then, the next data bytes are received one by one

after reading the I2C_IN register.

Bit 0: $''ꢂ $GGUHVVꢀGLUHFWLRQꢀELWꢁ

This bit is “don’t care”, the interface

acknowledges either 0 or 1. It is not cleared

when the interface is disabled (PE=0).

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, &ꢅ6WDWXVꢅ5HJLVWHUꢅꢅꢆꢅꢐ,ꢁ&B65ꢆꢑ

Input Register 7 (07h) Read only

Reset Value: 0000 0000 (00h)

10-bit Addressing Mode

bit 7-0: $''ꢈꢓ$''ꢂ Interface address.

These are the least significant bits of the I²C

bus address of the interface. They are not

cleared when the interface is disabled

(PE=0).

7

0

EVF

ADD10

TRA

BUSY

BTF

ADSL

M/SL

SB

84/123

67ꢀꢁ)ꢀꢂꢂꢃ)ꢀꢂꢄ

Bit 7: (9)ꢅEvent Flag

This bit is set by hardware as soon as an

This information is not updated when the

interface is disabled (PE=0).

0: No communication on the bus

event occurs. It is cleared by software

reading I2C_SR2 register in case of error

event or as described in Figure 12.3. It is also

cleared by hardware when the interface is

disabled (PE=0).

1: Communication ongoing on the bus

Bit 3: %7)ꢅByte transfer finished

This bit is set by hardware as soon as a byte

is correctly received or transmitted with

interrupt generation if ITE=1. It is cleared by

software reading I2C_SR1 register followed

by a read of I2C_IN or write of I2C_OUT

registers. It is also cleared by hardware when

the interface is disabled (PE=0).

0: No event

1: One of the following events has occurred:

– BTF=1 (Byte received or transmitted)

– ADSL=1 (Address matched in Slave

mode while ACK=1)

– SB=1 (Start condition generated in Mas-

ter mode)

– Following a byte transmission, this bit is

set after reception of the acknowledge

clock pulse. In case an address byte is

sent, this bit is set only after the EV6

event (see Figure 12.3). BTF is cleared

by reading I2C_SR1 register followed by

writing the next byte in I2C_OUT register.

– Following a byte reception, this bit is set

after transmission of the acknowledge

clock pulse if ACK=1. BTF is cleared by

reading I2C_SR1 register followed by

reading the byte from I2C_IN register.

– AF=1 (No acknowledge received after

byte transmission)

– STOPF=1 (Stop condition detected in

Slave mode)

– ARLO=1 (Arbitration lost in Master

mode)

– BERR=1 (Bus error, misplaced Start or

Stop condition detected)

– ADD10=1 Address byte successfully

transmitted in Master mode.

The SCL line is held low while BTF=1.

0: Byte transfer not done

Bit 6: $''ꢆꢂꢅ10 bit addressing in Master Mode

1: Byte transfer succeeded

This bit is set by hardware when the master

has sent the first byte in 10-bit address mode.

It is cleared by software reading I2C_SR1

register followed by a write in the I2C_OUT

register of the second address byte. It is also

cleared by hardware when the peripheral is

disabled (PE=0).

Bit 2: $'6/ꢅAddress matched (Slave Mode)

This bit is set by hardware as soon as the

slave address received matched with the

OAR register content or a general call is

recognized. An interrupt is generated if

ITE=1. It is cleared by software reading

I2C_SR1 register or by hardware when the

interface is disabled (PE=0).

0: No ADD10 event occurred

1: The Master has sent the first address byte

Bit 5: 75$ꢅTransmitter/Receiver

The SCL line is held low while ADSL=1.

0: Address mismatched or not received

1: Received address matched

When BTF is set, TRA=1 if a data byte has

been transmitted. It is cleared automatically

when BTF is cleared. It is also cleared by

hardware after detection of Stop condition

(STOPF=1), loss of bus arbitration (ARLO=1)

or when the interface is disabled (PE=0).

Bit 1: 0ꢃ6/ꢅMaster/Slave

This bit is set by hardware as soon as the

interface is in Master mode (writing

START=1). It is cleared by hardware after

detecting a Stop condition on the bus or a

loss of arbitration (ARLO=1). It is also

cleared when the interface is disabled

(PE=0).

0: Data byte received (if BTF=1)

1: Data byte transmitted

Bit 4: %86<ꢅBus busy

This bit is set by hardware on detection of a

Start condition and cleared by hardware

either on detection of a Stop condition or

when a bus error occurs. It indicates a

communication in progress on the bus.

0: Slave mode

1: Master mode

85/123

67ꢀꢁ)ꢀꢂꢂꢃ)ꢀꢂꢄ

Bit 0: 6%ꢅStart bit (Master Mode)

After an ARLO event the interface switches

back automatically to Slave mode (M/SL=0).

The SCL line is not held low while ARLO=1.

0: No arbitration lost detected

This bit is set by hardware as soon as the

Start condition is generated (following a write

START=1). An interrupt is generated if

ITE=1. It is cleared by software reading

I2C_SR1 register followed by writing the

address byte in I2C_OUT register. It is also

cleared by hardware when the interface is

disabled (PE=0).

1: Arbitration lost detected

Bit 1: %(55ꢅ%XVꢀHUURUꢁ

This bit is set by hardware when the interface

detects a misplaced Start or Stop condition.

An interrupt is generated if ITE=1. It is

cleared by software reading I2C_SR2

register or by hardware when the interface is

disabled (PE=0).

The SCL line is not held low while BERR=1.

0: No misplaced Start or Stop condition

1: Misplaced Start or Stop condition

0: No Start condition

1: Start condition generated

, &ꢅ6WDWXVꢅ5HJLVWHUꢅꢅꢁꢅꢐ,ꢁ&B65ꢁꢑ

Input Register 8 (08h) Read only

Reset Value: 0000 0000 (00h)

7

0

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GHWHFWꢀDꢀEXVꢀHUURUꢀꢉ%86<ꢀELWꢀFOHDUHGꢀE\ꢀKDUGZDUHꢊꢁ

-

AF

STOPF ARLO

BERR

GCAL

Bit 0: *&$/ꢅ*HQHUDOꢀ&DOOꢀꢉ6ODYHꢀPRGHꢊꢁ

Bit 7-5: Reserved.

Bit 4: $)ꢅ$FNQRZOHGJHꢀIDLOXUH.

This bit is set by hardware when a general

call address is detected on the bus while

ENGC=1. It is cleared by hardware detecting

a Stop condition (STOPF=1) or when the

interface is disabled (PE=0).

0: No general call address detected on bus

1: general call address detected on bus

This bit is set by hardware when no

acknowledge is returned. An interrupt is

generated if ITE=1. It is cleared by software

reading the I2C_SR2 register or by hardware

when the interface is disabled (PE=0).

The SCL line is not held low while AF=1.

0: No acknowledge failure

1: Acknowledge failure

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Bit 3: 6723)ꢅ6WRSꢀGHWHFWLRQꢀꢉ6ODYHꢀPRGHꢊꢁ

, &ꢅ'DWDꢅ2XWSXWꢅ5HJLVWHUꢅꢐ,ꢁ&B287ꢑ

Output Register 6 (06h) Write only

Reset Value: 0000 0000 (00h)

This bit is set by hardware when a Stop

condition is detected on the bus after an

acknowledge (if ACK=1). An interrupt is

generated if ITE=1. It is cleared by software

reading I2C_SR2 register or by hardware

when the interface is disabled (PE=0).

7

0

I2CDO7 I2CDO6 I2CDO5 I2CDO4 I2CDO3 I2CDO2 I2CDO1 I2CDO0

The SCL line is not held low while STOPF=1.

0: No Stop condition detected

1: Stop condition detected

bit 7-0: ,ꢁ&'2ꢈꢓ,ꢁ&'2ꢂ Data to be transmitted.

Bit 2: $5/2ꢅ$UELWUDWLRQꢀORVW.

These bits contain the byte to be transmitted in the

bus in Transmitter mode: Byte transmission start

automatically when the software writes in the

I2C_OUT register.

This bit is set by hardware when the interface

loses the arbitration of the bus to another

master. An interrupt is generated if ITE=1. It

is cleared by software reading I2C_SR2

register or by hardware when the interface is

disabled (PE=0).

86/123

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A basic example of interconnections between a

single master and a single slave is illustrated in

Figure 13.1

The Serial Peripheral Interface (SPI) allows full-

duplex, synchronous, serial communication with

external devices. An SPI system may consist of a

master, one or more slaves, or a system, in which

devices may be either masters or slaves.

SPI is normally used for communication between

the ICU and external peripherals or another ICU.

The MOSI pins are connected together as the

MISO pins. In this manner, data is transferred

serially between master and slave (most significant

bit first).

When the master device transmits data to a slave

device via the MOSI pin, the slave device responds

by sending data to the master device via the MISO

pin. This implies full duplex transmission with both

data out and data in synchronized with the same

clock signal (which is provided by the master

device via the SCK pin).

The transmitted byte is replaced by the byte

received and eliminates the need for separate

transmit-empty and receiver-full bits. A status flag

is used to indicate that the I/O operation is

complete.

Four possible data/clock timing relationships may

be chosen (see Figure 13.4), but master and slave

must be programmed with the same timing mode.

Refer to the Pin Description section in this

datasheet for the device-specific pin-out.

ꢆꢄꢇꢁꢅꢅ0DLQꢅ)HDWXUHV

I Full duplex, three-wire synchronous transfers

I Master or slave operation

I Four master mode frequencies

I Maximum slave mode frequency = fCKM/4.

I Four programmable master bit rates

I Programmable clock polarity and phase

I End of transfer interrupt flag

ꢆꢄꢇꢊꢅꢅ)XQFWLRQDOꢅ'HVFULSWLRQ

I Write collision flag protection

Figure 13.2 shows the serial peripheral interface

(SPI) block diagram.

I Master mode fault protection capability.

This interface contains 4 dedicated registers:

– A Control Register (SPI_CR)

– A Status Register (SPI_STATUS_CR)

– A Data Register for transmission (SPI_OUT)

– A Data Register for reception (SPI_IN)

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SPI is connected to external devices through 4

alternate pins:

– MISO: Master In / Slave Out pin

– MOSI: Master Out / Slave In pin

– SCK: Serial Clock pin

ꢆꢄꢇꢊꢇꢆꢅꢅ0DVWHUꢅ&RQILJXUDWLRQꢇ

– SS: Slave select pin (if not done through soft-

In a master configuration, the serial clock is

generated on the SCK pin.

ware)

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SLAVE

MASTER

MSBit

LSBit

MSBit

LSBit

MISO

MOSI

MISO

MOSI

8-BIT SHIFT REGISTER

SPI

CLOCK

GENERATOR

SCK

SS

SCK

SS

+5V

87/123

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)LJXUHꢅꢆꢄꢇꢁꢅꢅꢅ6HULDOꢅ3HULSKHUDOꢅ,QWHUIDFHꢅ%ORFNꢅ'LDJUDPꢅ

Internal Bus

Read

Read Buffer

IT

request

SPI_IN

MOSI

SPI_STATUS_CR

MISO

8-Bit Shift Register

SPI_OUT

SPIF WCOL OR MODF

SOD SSM SSI

-

Write

SPI

STATE

CONTROL

SCK

SS

SPI_CR

MSTR

SPR0

SPIE SPE SPR2

CPOL CPHA SPR1

MASTER

CONTROL

SERIAL

CLOCK

GENERATOR

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The data byte is loaded in parallel into the 8-bit shift

register (from the internal bus) during a write cycle

and then shifted out serially to the MOSI pin most

significant bit first.

When data transfer is complete:

– The SPIF bit is set by hardware

– Select the SPR0, SPR1 and SPR2 bits to define

the serial clock baud rate (see SPI_CR register).

– Select the CPOL and CPHA bits to define one of

the four relationships between the data transfer

and the serial clock (see Figure 13.4).

– The SS pin must be connected to a high level

signal during the complete byte transmit se-

quence, if this pin is used.

– The MSTR and SPE bits must be set (they re-

main set only if the SS pin is connected to a high

level signal).

– An interrupt is generated if the SPIE bit is set.

During the last clock cycle the SPIF bit is set, a

copy of the data byte received in the shift register

is moved to a buffer. When the SPI_IN register is

read, the SPI peripheral returns this buffered

value. Clearing the SPIF bit is performed by the

following software sequence:

In this configuration the MOSI pin is a data output

and to the MISO pin is a data input.

1. An access to the SPI_STATUS_CR register

while the SPIF bit is set

2. A read to the SPI_IN register.

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Transmit sequence begins when a byte is written in

the SPI_OUT register.

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88/123

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ꢆꢄꢇꢊꢇꢁꢅꢅ6ODYHꢅ&RQILJXUDWLRQꢇ

In slave configuration, the serial clock is received

on the SCK pin from the master device.

(shifted in serially). The serial clock is used to

synchronize data transfer during a sequence of

eight clock pulses.

The SS pin allows individual selection of a slave

device; the other slave devices that are not

selected do not interfere with SPI transfer.

The value of the SPR0, SPR1 and SPR2 bits is not

used for data transfer.

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Four possible timing relationships may be chosen

by software, using the CPOL and CPHA bits.

– For correct data transfer, the slave device must

be in the same timing mode as the master de-

vice (CPOL and CPHA bits). See Figure 13.4.

The CPOL (clock polarity) bit controls the steady

state value of the clock when data isn’t being

transferred. This bit affects both master and slave

modes.

The combination between the CPOL and CPHA

(clock phase) bits select the data capture clock

edge.

Figure 13.4, shows an SPI transfer with the four

combinations of the CPHA and CPOL bits. The

diagram may be interpreted as a master or slave

timing diagram where the SCK pin, the MISO pin,

the MOSI pin are directly connected between the

master and the slave device.

– The SS pin must be connected to a low level sig-

nal during the complete byte transmit sequence,

if this pin is used.

– Clear the MSTR bit and set the SPE bit to assign

the pins to alternate function.

In this configuration the MOSI pin is a data input

and the MISO pin is a data output.

7UDQVPLWꢅ6HTXHQFH

The data byte is loaded into the 8-bit shift register

(from the internal bus) during a write cycle and

then shifted out serially to the MISO pin most

significant bit first.

The transmit sequence begins when the slave

device receives the clock signal and the most

significant bit of the data on its MOSI pin.

The SS pin is the slave device select input and can

be driven by the master device.

The master device applies data to its MOSI pin-

clock edge before the capture clock edge.

When data transfer is complete:

– The SPIF bit is set by hardware

– An interrupt is generated if SPIE bit is set.

During the last clock cycle the SPIF bit is set, a

copy of the data byte received in the shift register

is moved to a buffer. When the SPI_IN register is

read, the SPI peripheral returns the buffer value.

&3+$ꢅELWꢅLVꢅVHW

The second edge on the SCK pin (falling edge if

the CPOL bit is reset, rising edge if the CPOL bit is

set) is the MSBit capture strobe. Data is latched on

the occurrence of the second clock transition.

A write collision should not occur even if the SS pin

stays low during a transfer of several bytes (see

Figure 13.3).

The SPIF bit is cleared by the following software

sequence:

1. An access to the SPI_STATUS_CR register

while the SPIF bit is set.

&3+$ꢅELWꢅLVꢅUHVHW

2. A read to the SPI_IN register.

The first edge on the SCK pin (falling edge if CPOL

bit is set, rising edge if CPOL bit is reset) is the

MSBit capture strobe. Data is latched on the

occurrence of the first clock transition.

The SS pin must be toggled high and low between

each byte transmitted (see Figure 13.3).

In order to protect the transmission from a write

collision a low value on the SS pin of a slave device

freezes the data in its SPI_OUT register and does

not allow it to be altered. Therefore, the SS pin

must be high to write a new data byte in the

SPI_OUT without producing a write collision.

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The SPIF bit can be cleared during a second

transmission; however, it must be cleared before

the second SPIF bit in order to prevent an overrun

condition (see Section 13.4.6).

Depending on the CPHA bit, the SS pin has to be

set to write to the SPI_OUT register between each

data byte transfer to avoid a write collision (see

Section 13.4.4).

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During an SPI transfer, data is simultaneously

transmitted (shifted out serially) and received

89/123

67ꢀꢁ)ꢀꢂꢂꢃ)ꢀꢂꢄ

A write collision occurs when the software tries to

write to the SPI_OUT register while a data transfer

is taking place with an external device. When this

occurs, the transfer continues uninterrupted; and

the software writing will be unsuccessful.

Write collisions can occur both in master and slave

mode.

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:&2/ꢅELW

The WCOL bit in the SPI_STATUS_CR register is

set if a write collision occurs.

No SPI interrupt is generated when the WCOL bit

is set (the WCOL bit is a status flag only).

The WCOL bit is cleared by a software sequence

(see Section 13.5).

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Master mode fault occurs when the master device

has its SS pin pulled low, then the MODF bit is set.

Master mode fault affects the SPI peripheral in the

following ways:

– The MODF bit is set and an SPI interrupt is

generated if the SPIE bit is set.

,Qꢅ6ODYHꢅPRGH

When the CPHA bit is set:

The slave device will receive a clock (SCK) edge

prior to the latch of the first data transfer. This first

clock edge will freeze the data in the slave device

SPI_OUT register and output the MSBit on to the

external MISO pin of the slave device.

– The SPE bit is reset. This blocks all output from

the device and disables the SPI peripheral.

– The MSTR bit is reset, forcing the device into

slave mode.

Clearing the MODF bit is done through a software

sequence:

The SS pin low state enables the slave device, but

the output of the MSBit onto the MISO pin does not

take place until the first data transfer clock edge

occurs.

When the CPHA bit is reset:

1. A read or write access to the SPI_STATUS_CR

register while the MODF bit is set.

2. A write to the SPI_CR register.

Data is latched on the occurrence of the first clock

transition. The slave device doesn’t have a way of

knowing when that transition will occur; therefore,

the slave device collision occurs when software

attempts to write the SPI_OUT register after its SS

pin has been pulled low.

For this reason, the SS pin must be high, between

each data byte transfer, in order to allow the CPU

to write in the SPI_OUT register without generating

a write collision.

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Hardware does not allow the user to set the SPE

and MSTR bits, while the MODF bit is set (except

in the MODF bit clearing sequence).

In a slave device the MODF bit can’t be set, but in

a multi master configuration the device can be in

slave mode with this MODF bit set.

,Qꢅ0DVWHUꢅPRGH

Collision in the master device is defined as a write

of the SPI_OUT register, while the internal serial

clock (SCK) is in the process of transfer.

The SS pin signal must always be high on the

master device.

The MODF bit indicates that there might have been

a multi-master conflict for system control and

Byte 3

Byte 2

MOSI/MISO

Master SS

Byte 1

Slave SS

(CPHA=0)

Slave SS

(CPHA=1)

90/123

67ꢀꢁ)ꢀꢂꢂꢃ)ꢀꢂꢄ

allows a proper exit from system operation to a

reset or default system state using an interrupt

routine.

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C

CPOL = 1

CPOL = 0

MSBit

Bit 6

Bit 5

MISO

(from master)

MOSI

(from slave)

SS

(to slave)

CAPTURE STROBE

C

CPOL = 1

CPOL = 0

MISO

(from master)

MSBit

Bit 6

Bit 5

MOSI

(from slave)

MSBit

SS

(to slave)

CAPTURE STROBE

Note: This figure should not be used as a repla

Refer to the Electrical Characteristics chapter.

91/123

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Clearing sequence after SPIF = 1 (end of a data byte transfer)

Read SPI_STATUS_CR

1st Step

2nd Step

OR

THEN

SPIF =0

Read SPI_IN

WCOL=0 if no transfer has started

WCOL=1 if a transfer has started

before the 2nd step

Write SPI_OUT

WCOL=0

Clearing sequence before SPIF = 1 (during a data byte transfer)

Read SPI_STATUS_CR

1st Step

THEN

Note: Writing in SPI_OUT regis-

2nd Step

Read SPI_IN

ter instead of reading in SPI_IN

do not reset WCOL bit

WCOL=0

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An overrun condition occurs when the master

device has sent several data bytes and the slave

device hasn’t cleared the SPIF bit issued from the

previous data byte transmitted.

In this case, the receiver buffer contains the byte

sent after the SPIF bit was last cleared. A read to

the SPI_IN register returns this byte. All other

bytes are lost.

For more security, the slave device may respond to

the master with the data byte received. Then the

master will receive the previous byte back from the

slave device if all MISO and MOSI pins are

connected and the slave has not written its

SPI_OUT register.

This condition is not detected by the SPI

peripheral.

Other transmission security methods can use ports

for handshake lines or data bytes with command

fields.

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0XOWLꢓPDVWHUꢅ6\VWHP

A multi-master system may also be configured by

the user. Transfer of master control could be

implemented using a handshake method through

the I/O ports or by an exchange of code messages

through the serial peripheral interface system.

There are two types of SPI systems:

– Single Master System

– Multimaster System

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The multi-master system is principally handled by

the MSTR bit in the SPI_CR register and the

MODF bit in the SPI_STATUS_CR register.

A typical single master system may be configured,

using an ICU as the master and four ICUs as

slaves (see Figure 13.6).

The master device selects the individual slave

devices by using four pins of a parallel port to

control the four SS pins of the slave devices.

The SS pins are pulled high during reset since the

master device ports will be forced to be inputs at

that time, thus disabling the slave devices.

92/123

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SS

SCK

Slave

SCK

Slave

MCU

SCK

Slave

MCU

Slave

MCU

MOSI MISO

SCK

Master

MCU

5V

SS

ꢆꢄꢇꢊꢇꢏꢅꢅ,QWHUUXSWV

SPI End of Transfer Event

Master Mode Fault Event

SPIF

Yes

No

SPIE

MODF

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93/123

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Bit 3: &32/ Clock polarity.

In the following sections describe the registers

used by the SPI.

This bit is set and cleared by software. This

bit determines the steady state of the serial

Clock. The CPOL bit affects both the master

and slave modes.

0: The steady state is a low value at the SCK

pin.

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Configuration Register 20 (014h) Read/Write

Reset Value: 0000 0000 (00h)

1: The steady state is a high value at the SCK

pin.

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7

0

SPIE

SPE

SPR2

MSTR

CPOL

CPHA

SPR1

SPR0

Bit 2: &3+$ Clock phase.

This bit is set and cleared by software.

0: The first clock transition is the first data

capture edge.

1: The second clock transition is the first

capture edge.

Bit 7: 63,( Serial peripheral interrupt enable.

This bit is set and cleared by software.

0: Interrupt is inhibited

1: An SPI interrupt is generated whenever

SPIF=1 or MODF=1 in SPI_STATUS_CR

Bit 1-0: 635ꢆ-635ꢂ Serial peripheral rate.

These bits are set and cleared by software.

Used with the SPR2 bit, they select one of six

baud rates to be used as the serial clock

when the device is a master (see Table 13.1).

Bit 6: 63( Serial peripheral output enable.

This bit is set and cleared by software. It is

also cleared by hardware when, in master

mode, SS=0 (see Section 13.4.5 Master

Mode Fault).

These 2 bits have no effect in slave mode.

0: I/O port connected to pins

1: SPI alternate functions connected to pins

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Bit 5: 635ꢁꢅDivider Enable.

Serial Clock

f_CKM/2 ¹⁾

f_CKM/4

SPR2 SPR1 SPR0

This bit is set and cleared by software and it

is cleared by reset. It is used with the

SPR[1:0] bits to set the baud rate. Refer to

Table 13.1.

0: Divider by 2 enabled

1: Divider by 2 disabled

1

0

1

0

1

0

1

0

1

f_CKM/8

f_CKM/16

f_CKM/32

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f

_CKM/64

Bit 4: 0675 Master/Slave mode select.

This bit is set and cleared by software. It is

also cleared by hardware when, in master

mode, SS=0 (see Section 13.4.5 Master

Mode Fault).

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Configuration Register 21 (015h) Read/Write

Reset Value: 0000 0000 (00h)

0: Slave mode is selected

7

0

1: Master mode is selected, the function of

the SCK pin changes from an input to an

output and the functions of the MISO and

MOSI pins are reversed.

SPIF

WCOL

OR

MODF

-

SOD

SSM

SSI

94/123

67ꢇꢈ)ꢇꢉꢉꢊ)ꢇꢉꢅ

Bit 7: 63,) Serial Peripheral data transfer flag.

Bit 2: 62' SPI output disable

(read only)

This bit is set and cleared by software. When

set, it disables the alternate function of the

SPI output (MOSI in master mode / MISO in

slave mode)

0: SPI output not disable

1: SPI output disable.

This bit is set by hardware when a transfer

has been completed. An interrupt is

generated if SPIE=1 in the SPI_CR register.

It is cleared by a software sequence (an

access to the SPI_STATUS_CR register

followed by a read or write to the SPI_IN/

SPI_OUT registers).

Bit 1: 660 SS mode selection

0: Data transfer is in progress or has been

approved by a clearing sequence.

1: Data transfer between the device and an

external device has been completed.

This bit is set and cleared by software. When

set, it disables the alternate function of the

SPI Slave Select pin and use the SSI bit

value instead of.

0: SSꢀpin used by the SPI.

1: SS pin not used (I/O mode), SSI bit value

is used.

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Bit 6: :&2/ Write Collision status (read only).

This bit is set by hardware when a write to the

SPI_OUT register is done during a transmit

sequence. It is cleared by a software

sequence (see Figure 13.5).

Bit 0: 66, SS internal mode

This bit is set and cleared by software. It

replaces pin SS of the SPI when bit SSM is

set to 1. SSI bit is active low slave select

signal when SSM is set to 1.

0: No write collision occurred

1: A write collision has been detected

0 : Slave selected

1 : Slave not selected.

Bit 5: 25 SPI overrun error (read only).

This bit is set by hardware when the byte

currently being received in the shift register is

ready to be transferred into the SPI_IN

register while SPIF = 1 (See Section 13.4.6

Overrun Condition). It is cleared by a

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LQꢀVODYHꢀPRGHꢁ

software

sequence

(read

of

the

SPI_STATUS_CR register followed by a

read in SPI_IN or write of the SPI_OUT

register).

0: No overrun error.

1: Overrun error detected.

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63,ꢀ'DWDꢀ,QSXWꢀ5HJLVWHUꢀꢂ63,B,1ꢃ

Input Register 5 (05h) Read only

Reset Value: 0000 0000 (00h)

Bit 4: 02') Mode Fault flag (read only).

7

0

This bit is set by hardware when the SS pin is

pulled low in master mode (see Section

13.4.5 Master Mode Fault). An SPI interrupt

can be generated if SPIE=1 in the SPI_CR

register. This bit is cleared by a software

SPIDI7 SPIDI6 SPIDI5 SPIDI4 SPIDI3 SPIDI2 SPIDI1 SPIDI0

bit 7-0: 63,',ꢋꢁ63,',ꢉ Received data.

sequence

(An

access

to

the

SPI_STATUS_CR register while MODF=1

followed by a write to the SPI_CR register).

0: No master mode fault detected

The SPI_IN register is used to receive data on the

serial bus.

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1: A fault in master mode has been detected

Bit 3: Not used.

95/123

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63,ꢀ'DWDꢀ2XWSXWꢀ5HJLVWHUꢀꢂ63,B287ꢃ

Output Register 5 (05h) Write only

Reset Value: 0000 0000 (00h)

7

0

SPIDO7 SPIDO6 SPIDO5 SPIDO4 SPIDO3 SPIDO2 SPIDO1 SPIDO0

bit 7-0: 63,'2ꢋꢁ63,'2ꢉ Data to be transmitted.

The SPI_OUT register is used to transmit data on

the serial bus. In the master device only a write to

this register will initiate transmission/reception of

another byte.

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ꢄꢌꢆꢄꢆꢈꢀ7\SLFDOꢀFXUYHVꢆ

Unless otherwise specified, all typical curves are

provided only as design guidelines and are not

tested.

Unless otherwise specified, all voltages are

referred to V_ss.

ꢄꢌꢆꢄꢆꢄꢀꢀ0LQLPXPꢀDQGꢀ0D[LPXPꢀYDOXHVꢆ Unless

otherwise specified, the minimum and maximum

values are guaranteed in the worst conditions of

environment temperature, supply voltage and

frequencies by tests in production on 100% of the

devices with an environmental temperature at

T_A=25°C and T_A=T_Amax (given by the selected

temperature range).

Data are based on characterization results, design

simulation and/or technology characteristics are

indicated in the table footnotes and are not tested

in production. The minimum and maximum values

are based on characterization and refer to sample

tests, representing the mean value plus or minus

three times the standard deviation (mean 3Σ).

ꢄꢌꢆꢄꢆꢅꢀꢀ7\SLFDOꢀYDOXHVꢆ

Unless otherwise specified, typical data is based

on T_A=25°C, V_DD=5V. They are provided only as

design guidelines and are not tested.

ꢄꢌꢆꢄꢆꢌꢀꢀ/RDGLQJꢀFDSDFLWRUꢆ The loading condition

used for pin parameter measurement is illustrated

in Figure 14.1.

ꢄꢌꢆꢄꢆꢇꢀꢀ3LQꢀLQSXWꢀYROWDJHꢆ

Input voltage measurement on a pin of the device

is described in Figure 14.2

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ST52 PIN

C_L

V_IN

97/123

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Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device.

This is a stress rating only. Functional operation of the device under these conditions is not implied.

Exposure to maximum rating conditions for extended periods may affect device reliability.

7DEOHꢀꢄꢌꢆꢄꢀ9ROWDJHꢀ&KDUDFWHULVWLFV

V

-V

Supply voltage

6.5

DD SS

1) 2)

V

-0.3 to V +0.3

V

SS

DD

V

Input voltage on any pin

IN

V

Electrostatic discharge voltage

2000

DESD

7DEOHꢀꢄꢌꢆꢈꢀ&XUUHQWꢀ&KDUDFWHULVWLFV

3)

I

100

Total current in V power lines (source)

VDD

DD

3)

I

Total current in V ground lines (sink)

VSS

SS

Output current sunk by any standard I/O and control pin

Output current source by any I/Os and control pin

Injected current on RESET pin

20

-20

± 5

I

IO

mA

2)

Injected current on OSCin and OSCout pins

± 5

I

INJ(PIN)

4)

Injected current on any other pin

4)

ΣI

± 20

Total Injected current (sum of all I/O and control pins)

INJ(PIN)

7DEOHꢀꢄꢌꢆꢅꢀ7KHUPDOꢀ&KDUDFWHULVWLFV

T

Storage temperature range

-65 to +150

150

STG

°C

T

J

Maximum junction temperature

1RWHVꢍ

1. Connecting I/O Pins directly to VDD or VSS could damage the device if the unintentional internal reset

is generated or an unexpected change of I/O configuration occurs (for example, due to the corrupted

program counter). In order to guarantee safe operation, this connection has to be performed via a pull-

up or pull-down resistor (typical: 10K Ω for I/Os). Unused I/O pins must be tied in the same manner to

VDD or VSS according to their reset configuration.

2. When the current limitation is not possible, the VIN absolute maximum rating must be respected, other-

wise refer to IINJ(PIN) specification. A positive injection is induced by VIN>VDD while a negative injec-

tion is induced by VIN<VSS to IINJ(PIN) specification. A positive injection is VIN>VDD while a negative

injection is induced by VIN<VSS. Data by design.

3. All power (VDD) and ground (VSS) lines must always be connected to the external supply.

4. When several inputs are submitted to a current injection, the maximum ΣI_INJ(PIN)is the absolute sum of

the positive and negative injected currents (instantaneous values). Data by design.

98/123

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Operating condition: T^A=-40 to 85°C (unless otherwise specified).

7DEOHꢀꢄꢌꢆꢌꢀ2SHUDWLQJꢀ&RQGLWLRQV

f

= 1 to 20MHz

osc

2.8

2.7

5.5

TA=-40 to 85°C

Operating Supply Voltage in Working mode

f

= 1 to 20MHz

osc

1)

5.5

V

DD

TA= 0 to 85°C

Operating Supply Voltage in ISP mode

Operating Supply Voltage in IAP mode

Temperature range

f

= 1 to 20MHz

2.8

-40

1

5.5

85

osc

T

°C

A

External clock frequency

20

MHz

f

OSC

1RWHVꢍ

1. It is recommendend to insert a capacitor beetwen V_DDand V_SSfor improving noise rejection. recom-

mended values are 10 µF (electrolytic or tantalum) and/or 100 nF (ceramic).

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ꢈꢉ

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LQꢀWKLVꢀDUHD

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TBD

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ꢉ

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ꢄ

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ꢈ

ꢈꢆꢋ ꢈꢆꢎ ꢅ

ꢅꢆꢇ

ꢌ

ꢌꢆꢇ

ꢇ

ꢇꢆꢇ

ꢏ

9GG ꢂ9ꢃ

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IURPꢀꢉ&ꢀWRꢀꢎꢇ&

99/123

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ꢄꢌꢆꢌꢀꢀ6XSSO\ꢀ&XUUHQWꢀ&KDUDFWHULVWLFV

The test condition in RUN mode for all the I_DD

measurements are, unless otherwise specified:

OSCin = external square wave, from rail to rail;

OSCout = floating;

All I/O pins in input to VSS

T^A=-40 to 85°C

Supply current is mainly a function of the operating

voltage and frequency. Other factors such as I/O

pin loading and switching rate, oscillator type,

internal code execution pattern and temperature,

also have an impact on the current consumption.

7DEOHꢀꢄꢌꢆꢇꢀ6XSSO\ꢀ&XUUHQWꢀLQꢀ581ꢐꢀ:$,7ꢀDQGꢀ6/2:ꢀ0RGHꢐꢀꢇꢐꢇꢀ9ꢀVXSSO\ꢀYROWDJHꢀ ꢆ

f

= 1 Mhz

2.17

3.79

5.85

9.87

4.0

4.8

osc

f

= 5 Mhz,

osc

1)

Supply current in RUN mode

f

= 10 MHz

6.8

osc

f

=20 MHz

11.5

6.0

osc

4)

V

=5.5V

f

=10 MHz

DD

intosc

5.30

f

=1 Mhz

1.61

2.23

2.97

4.43

2.7

3.0

osc

mA

f

=5 MHz

osc

2)

I

Supply current in WAIT mode

DD

f

=10 MHz

=20 MHz

4.6

osc

f

5.85

3.0

4)

=10 MHz

intosc

2.50

f

=1 Mhz

1.95

3.06

4.34

6.75

3.9

4.5

5.5

8.6

4.5

osc

V

=5.5V

f

=5 MHz

osc

DD

3)

Supply current in SLOW mode

f

=f

/64

CPU OSC

f

=10 MHz

=20 MHz

osc

4)

=10 MHz

intosc

3.98

1RWHVꢍ

1. CPU running with memory access, all I/O pins in input mode with a static value at V_SS(no load), all pe-

ripherals switched off; external clock input.

2. CPU in WAIT mode with all I/O pins in input mode with a static value at V_SS(no load), all peripherals

switched off; external clock input.

3. CPU running with memory access, all I/O pins in input mode with a static value at V_SS(no load), all pe-

ripherals switched off; external clock input, CPU clock frequency divided 64 times by using the related

Configuration Register.

4. Device driven by Internal oscillator at 10 MHz.

5. Not tested in production

100/123

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f

=1 Mhz

2.2

3.7

5.7

9.5

2.9

3.8

osc

f

=5 Mhz,

osc

1)

Supply current in RUN mode

f

=10 MHz

=20 MHz

=10 MHz

6.0

osc

10.0

5.4

4)

f

V

=2.8V

DD

intosc

4.93

f

=1 Mhz

1.5

2.0

osc

mA

f

=5 MHz

2.07

2.8

2.4

3.0

4.4

2.7

osc

2)

I

Supply current in WAIT mode

DD

f

=10 MHz

=20 MHz

osc

f

4.2

4)

=10 MHz

intosc

2.35

f

=1 Mhz

2.07

3.03

4.24

6.6

2.7

3.2

4.6

7.0

4.0

osc

V

=2.8V

f

=5 MHz

osc

DD

3)

Supply current in SLOW mode

f

=f

/64

CPU OSC

f

=10 MHz

=20 MHz

osc

4)

=10 MHz

intosc

3.55

1RWHVꢍ

1. CPU running with memory access, all I/O pins in input mode with a static value at V_SS(no load), all pe-

ripherals switched off; external clock input.

2. CPU in WAIT mode with all I/O pins in input mode with a static value at V_SS(no load), all peripherals

switched off; external clock input.

3. CPU running with memory access, all I/O pins in input mode with a static value at V_SS(no load), all pe-

ripherals switched off; external clock input, CPU clock frequency divided 64 times by using the related

Configuration Register.

4. Device driven by Internal oscillator at 10 MHz.

5. Not tested in production.

7DEOHꢀꢄꢌꢆꢋꢀ6XSSO\ꢀ&XUUHQWꢀLQꢀ+$/7ꢀ0RGHꢆ

VDD = 5.5 V, T=25°C

15

10

25

13

1)

I

µA

DD

Supply current in HALT mode

2)

VDD = 2.8 V , T=25°C

1RWHVꢍ

1. All I/O pins in input mode with a static value at V_SS(no load), PLVD switched off.

2. Not Tested in production

101/123

67ꢇꢈ)ꢇꢉꢉꢊ)ꢇꢉꢅ

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12

10,5

9

5MHz

7,5

6

10MHz

20MHz

1MHz

4,5

3

1,5

0

2,7

3,2

3,7

4,2

4,7

5,2

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6

4,5

3

5MHz

10MHz

20MHz

1MHz

1,5

0

2,7

3,2

3,7

4,2

4,7

5,2

9GG ꢂ9ꢃ

102/123

67ꢇꢈ)ꢇꢉꢉꢊ)ꢇꢉꢅ

ꢄꢌꢆꢇꢀꢀ&ORFNꢀDQGꢀ7LPLQJꢀ&KDUDFWHULVWLFV

Operating Conditions: VDD=2.8 V to 5.5 V, TA=-40° to 85°C, unless otherwise specified. Values by design.

7DEOHꢀꢄꢌꢆꢎꢀ*HQHUDOꢀ7LPLQJꢀ3DUDPHWHUV

f

Oscillator Frequency

1

2

20

MHz

osc

Minimum External

Interrupt Pulse Width

t

WINT

CPU

clock

cycle

Instruction time

4

8

16

28

t

INST

t

Interrupt reaction time

12

20

INT

ꢄꢌꢆꢏꢀꢀ3RZHUꢀRQꢀUHVHW

7DEOHꢀꢄꢌꢆꢑꢀ3RZHUꢀRQꢀUHVHW

1)

V

TA=25°C

2.55

0.05

2.56

2.70

V

Power on reset

POR

2)

V

1000

V/s

V

Slope

DDslp

DD

1. Measured with V_DDslope = 0.05 V/s. Internal Reset is released if V_DDgoes above V_POR. Notice that

there is not hysteresis on POR.

2. Suggested V_DDslope for correct working of the device. Not tested in production.

103/123

67ꢇꢈ)ꢇꢉꢉꢊ)ꢇꢉꢅ

ꢄꢌꢆꢋꢀꢀ0HPRU\ꢀ&KDUDFWHULVWLFV

Operating Conditions: VDD=2.8 V to 5.5 V, TA=-40° to 85°C, unless otherwise specified.

7DEOHꢀꢄꢌꢆꢄꢉꢀ5$0ꢀDQGꢀ5HJLVWHUVꢀ

V

VRM

PLVD disabled

V

Data retention mode

DDmin

7DEOHꢀꢄꢌꢆꢄꢄꢀ)ODVKꢀ3URJUDPꢊ'DWDꢀ0HPRU\

V_DD= 2.8 V - 5.5 V

2.5

5

Programming time for 1/32 bytes

Virgin Flash

ISP mode

V_DD= 2.8 V - 5.5 V

t

ms

prog

Programming time for 1/32 bytes

Programming time for 8 Kbytes

Not Virgin Flash

IAP mode

V_DD= 2.8 V - 5.5 V

Fast Programming Mode

ISP mode

640

t

TA=55°C

TA=25°C

10

years

cycle

Data retention

RET

N

Write/erase cycles

300000

RW

7DEOHꢀꢄꢌꢆꢄꢈꢀ((3520ꢀ'DWDꢀ0HPRU\

t

5

ms

TA=25°C

TA=55°C

TA=25°C

prog

Programming time for 1/32 bytes

t

10

years

cycle

Data retention

RET

N

Write/erase cycles

300000

RW

1RWHVꢍ

1. Minimum V^DDsupply voltage that avoids the loosing of data stored into RAM or into hardware registers.

Below the specified threshold the device is turned off and it is turned on only after the V^DDgoes above

the POR threshold, as consequence the device is reset by the POR and the RAM is put to all 0. Guar-

anteed by design, not tested in production.

2. Flash/EEPROM can be programmed at signle byte or at 32 bytes blocks. In working mode (In Applica-

tion Programming) the time includes the erase operation before the writing.

3. The data retention time increases when the T_Adecreases.

4. Not tested in production, guaranteed by design.

104/123

67ꢇꢈ)ꢇꢉꢉꢊ)ꢇꢉꢅ

ꢄꢌꢆꢎꢀ3URJUDPPDEOHꢀ/RZꢀ9ROWDJHꢀ'HWHFWRUꢀꢂ3/9'ꢃ

Operating Conditions: TA= 25°C, unless otherwise specified.

High Threshold

4.18

3.64

3.05

3.83

3.30

2.77

4.22

3.70

3.11

3.96

3.40

2.85

4.33

3.76

Reset release threshold

V

Medium Threshold

Low Threshold

LVDT+

1)

(V rise)

DD

3.15

V

3.96

High Threshold

Medium Threshold

Low Threshold

Reset threshold

V

3.46

2.87

LVDT-

1)

(V fall)

DD

Int.

clock

cycle

2)

t

Not detected by the PLVD

50

Filtered glitch on V

g

DD

1RWHVꢍ

1. Measured with V_DDslope in the range from 0.2 V/s to 4000 V/s . Values from validation. Not tested in

production.

2. Duration of the glitch not detected by the PLVD. Values by design, not tested in production.

ꢄꢌꢆꢑꢀ,QWHUQDOꢀRVFLOODWRU

The frequency of the internal oscillator is centered at 10 MHz but can be subject to variation due to process

spread: this may be calibrated by using the related option byte.

Operating Conditions: V^DD=2.8 V to 5.5 V, TA=-40° to 85°C, unless otherwise specified.

T_A= 25°C, VDD = 5.0 V

f

Internal operating frequency

Thermal drift of the internal

8

10

12

MHz

oscint

Not calibrated

T_A=-40°C

12

3

Thdr

f

T_A=0°C

T_A=85°C

T_A=25°C

%

osc

1)

oscillator

5

Step of calibration

100

kHz

cal

1RWHVꢍ

1. Drift values in temperature are calculated with respect to internal oscillator frequency value at T_A=25°

C .

105/123

67ꢇꢈ)ꢇꢉꢉꢊ)ꢇꢉꢅ

ꢄꢌꢆꢄꢉꢀꢀ3RUWꢀ3LQꢀ&KDUDFWHULVWLFV

ꢄꢌꢆꢄꢉꢆꢄꢀꢀ*HQHUDOꢀ&KDUDFWHULVWLFV

Operating Conditions: V^DD=2.8 V to 5.5 V, TA=-40° to 85°C, unless otherwise specified.

0.73

1.08

1.05

1.60

0.89

1.15

1.20

1.67

0.5

1.02

1.20

1.40

1.70

VDD=2.8 V, TA= 25°C

VDD=5.0 V, TA= 25°C

VDD=2.8 V, TA= 25°C

VDD=5.0 V, TA= 25°C

1)

V

Input low level voltage

IL

1)

V

IH

Input high level voltage

2)

V

Schmitt trigger voltage hysteresis

hys

1)

I

V

≤V ≤V

SS IN DD

0.1

1

µA

kΩ

L

Input leakage current

3)

R

6.4

15.5

31.8

Internal Pull-up resistor

PU

4)

R

Input protection resistor

0.3

5

S

4)

t

f(IO)out

r(IO)out

Output high to low level fall time

C = 50 pF

between 10% and 90%

L

ns

4)

t

5

Output low to high level rise time

CPU

clock

cycle

4)

t

2

w(IT)in

External interrupt pulse time

1RWHVꢍ

1. Data from Characterization. Not tested in production.

2. Hysteresis voltage between Schmitt trigger switching level. Data by design.

3. Values of the Pull-up resistrors depends on V (see Figure 14.7).

DD

4. Data based on design simulation and/or technology characteristics, not tested in production.

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5ꢀꢀ3XOOꢀ83ꢀꢀ#ꢀ7 ꢈꢇ&ꢀ

28

26

24

22

20

18

16

14

12

10

2,7

3,2

3,7

4,2

4,7

5,2

106/123

67ꢇꢈ)ꢇꢉꢉꢊ)ꢇꢉꢅ

)LJXUHꢀꢄꢌꢆꢎꢀꢀ3RUWꢀSLQꢀ(TXLYDOHQWꢀ&LUFXLW

ꢄꢌꢆꢄꢉꢆꢈꢀ2XWSXWꢀ'ULYLQJꢀ&XUUHQW

Operating Conditions: V^DD=2.8 V to 5.5 V, TA=25°C, unless otherwise specified.

7DEOHꢀꢄꢌꢆꢄꢅꢀ2XWSXWꢀ9ROWDJHꢀ/HYHOVꢀIRUꢀFODVVꢀ$ꢀSLQV

I

=+8mA

= 2.8 V

Output low level voltage for standard I/O

pin when 8 pins are sunk at same time.

IO

1)

0.40

2.50

0.55

V

OL

V

DD

V

I

=- 8mA

= 2.8 V

Output high level voltage for standard I/O

pin when 8 pins are sourced at same time.

IO

2)

2.33

V

OH

V

DD

7DEOHꢀꢄꢌꢆꢄꢌꢀ2XWSXWꢀ9ROWDJHꢀ/HYHOVꢀIRUꢀFODVVꢀ%ꢀSLQV

I

=+4mA

Output low level voltage for standard I/O

pin when 8 pins are sunk at same time.

IO

1)

0.22

2.64

0.33

V

OL

V

= 2.8 V

DD

V

I

=- 4mA

= 2.8 V

Output high level voltage for standard I/O

pin when 8 pins are sourced at same time.

IO

2)

2.42

V

OH

V

DD

1RWHVꢍ

1. The I_IOsunk current must always respect the absolute maximum rating specified in Section 14.2 and

the sum of I_IO(I/O ports and control pins) must not exceed I_VSS. Data from characterization; not tested

in production.

2. The I_IOsourced current must always respect the absolute maximum rating specified in Section 14.2 and

the sum of I_IO(I/O ports and control pins) must not exceed I_VDD. Data from characterization; not tested

in production.

3. Class A indicates an 8 mA driving capability of the output buffer while Class B indicates a 4 mA driving

capability of the output buffer. See General Description chapter for a complete description of class A

and B pins for every package.

107/123

67ꢇꢈ)ꢇꢉꢉꢊ)ꢇꢉꢅ

ꢄꢌꢆꢄꢄꢀꢀ&RQWUROꢀ3LQVꢀ&KDUDFWHULVWLFV

ꢄꢌꢆꢄꢄꢆꢄꢀꢀ5(6(7ꢀSLQꢆ

Operating Conditions: V^DD=2.8 V to 5.5 V, TA=25°C, unless otherwise specified.

7DEOHꢀꢄꢌꢆꢄꢇꢀ5HVHWꢀSLQ

V

= 2.8 V

= 5.5 V

= 2.8 V

= 5.5 V

= 2.8 V

1.18

2.34

1.63

3.22

0.45

100

DD

1)

V

Input low level voltage

IL

V

1)

V

IH

Input high level voltage

2)

V

t

Schmitt trigger voltage hysteresis

hys

3)

FN

Duration of noise

ns

1)

t

500

Reset pulse duration

RST

4)

R

V

= 2.8 V to 5.5 V

13.9

15.8

29.7

kΩ

Pull-up resistor

PURES

DD

1RWHVꢍ

1. Data by design, not tested in production.

2. Hysteresis voltage between Schmitt trigger switching level. Based on simulation results not tested in

production.

3. Max duration of the noise that is filtered by the pin. Data by design, not tested in production.

4. Values of the Pull-up resistors depends on V_DD. Not tested in production.

ꢄꢌꢆꢄꢄꢆꢈꢀꢀ9 SLQꢆ

Operating Conditions: V^DD=2.8 V to 5.5 V, TA=25°C, unless otherwise specified.

7DEOHꢀꢄꢌꢆꢄꢏꢀꢀ9 ¹⁾SLQꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ

V

= 2.8 V

= 5.5 V

= 2.8 V

= 5.5 V

1.18

2.34

1.63

3.22

DD

2)

V

IL

Input low level voltage

V

2)

V

Input high level voltage

IH

1RWHVꢍ

1. In working mode V_PPmust be tied to V_SS

2. Data is based on design simulations, not tested in production.

108/123

67ꢇꢈ)ꢇꢉꢉꢊ)ꢇꢉꢅ

ꢄꢌꢆꢄꢈꢀꢀ(0&ꢀ&KDUDFWHULVWLFV

Susceptibility tests are performed on a sample

basis during product characterization.

I (6': Electro-Static Discharge (positive and

negative) is applied on all pins of the device until

a functional disturbance occurs. This test

conforms with the IEC 1000-4-2 standard.

ꢄꢌꢆꢄꢈꢆꢄꢀ)XQFWLRQDOꢀ(06ꢀꢆ (Electro

Magnetic

I )7%: A burst of Fast Transient Voltage (positive

and negative) is applied to V_DDand V_SSthrough

a 100 pF capacitor, until a functional disturbance

occurs. This test conforms with the IEC 1000-4-

4 standard.

Susceptibility)

Based on a simple running application on the

product (toggling two LEDs through I/O ports), the

product is stressed by two electromagnetic events

until a failure occurs (indicated by the LEDs).

A device reset allows normal operation to be

resumed.

V

=5 V, T =25°C, f = 8 MHz SDIP32

Voltage limits to be applied on any I/O

pin to induce a functional disturbance

DD

osc

A

V

2B

3B

FESD

conform with IEC 1000-4-2

Fast transient voltage burst limits to be

applied through 100 pF on V and V

DD SS

pins to induce a functional disturbance

=5 V, T =25°C, f = 8 MHz SDIP32

DD

osc

A

V

FFTB

conform with IEC 1000-4-4

1RWHVꢍ

1. Data based on characterization results, not tested in production.

2. It is suggested to insert decoupling capacitors (10 nF and 100 nF electrolytic) on the power supply lines

to obtain a good price vs. EMC performance tradeoff. They have to be put as close as possible to the

device power supply pins.

ꢄꢌꢆꢄꢈꢆꢈꢀ$EVROXWHꢀ(OHFWULFDOꢀ6HQVLWLYLW\ꢆ Based

on three different tests (ESD, LU and DLU) using

specific measurement methods, the product is

stressed in order to determine its performance in

terms of electrical sensitivity.

ꢄꢌꢆꢄꢈꢆꢅꢀ(OHFWURꢁ6WDWLFꢀ'LVFKDUJHꢀꢂ(6'ꢃꢆ

Electro-Static Discharges (3 positive then 3 nega-

tive pulses separated by 1 second) are applied to

the pins of each sample according to each

pincombination. The sample size depends of the

number of supply pins of the device (3 parts*(n+1)

supply pin). The model imulated is the Human

Body Model. This test conforms to the JESD22-

A114A/A115A standard. See Figure 14.9.

1)

Electro-static discharge voltage

(Human Body Model)

V

T_A=25°C

2

kV

ESD(HBM)

)LJXUHꢀꢄꢌꢆꢑꢀꢀ7\SLFDOꢀ(TXLYDOHQWꢀ(6'ꢀ&LUFXLWV

S1

^{R = 1500}Ω

HIGH VOLTAGE

PULSE

HIGH VOLTAGE

PULSE

S2

67ꢀ),9(

C_L= 100 pF

GENERATOR

109/123

67ꢇꢈ)ꢇꢉꢉꢊ)ꢇꢉꢅ

ꢄꢌꢆꢄꢈꢆꢌꢀ6WDWLFꢀDQGꢀ'\QDPLFꢀ/DWFKꢁXSꢆ

I DLU: Electro-Static Discharges (one positive

then one negative test) are applied to each pin

of 3 samples when the micro is running to

assess the latch-up performance in dynamic

mode. Power supplies are set to the typical

values, the oscillator is connected as near as

possible to the pins of the micro and the

component is put in reset mode. This test

conforms to the IEC1000-4-2 and SAEJ1752/3

standards and is described in Figure 14.10.

I /8: 3 complementary static tests are required

on 10 parts to assess the latch-up performance.

A supply overvoltage (applied to each power

supply pin), a current injection (applied to each

input, output and configurable I/O pin) and a

power supply switch sequence are performed on

each sample. This test conforms to the EIA/

JESD 78 IC latch-up standard.

1)

T_A=25°C

T_A=85°C

A

LU

Static latch-up class

DLU

V

=5.5V, f

= 8 MHz, T =25°C

OSC A

Dynamic latch-up class

A

DD

)LJXUHꢀꢄꢌꢆꢄꢉꢀꢀ6LPSOLILHGꢀ'LDJUDPꢀRIꢀWKHꢀ(6'ꢀ*HQHUDWRUꢀIRUꢀ'/8

R_CH= 50 MΩ

R_D= 330 Ω

DISCHARGE TIP

V_DD

V_SS

C_S= 150 pF

HV RELAY

67ꢀ),9(

ESD

GENERATOR

DISCHARGE

RETURN CONNECTION

1RWHVꢍ

1. Class description: Class A is an STMicroelectronics internal specification. All its limits are higher than

the JEDEC specification, that means when a device belongs to Class A it exceeds the JEDEC standard.

Class B strictly covers all the JEDEC criteria (international standard).

ꢄꢌꢆꢄꢈꢆꢇꢀꢀ(6'ꢀ3LQꢀ3URWHFWLRQꢀ6WUDWHJ\ꢆ In order

to protect an integrated circuit against Electro-

Static Discharge the stress must be controlled to

prevent degradation or destruction of the circuit

elements. Stress generally affects the circuit

elements, which are connected to the pads but can

also affect the internal devices when the supply

pads receive the stress. The elements that are to

be protected must not receive excessive current,

voltage, or heating within their structure.

An ESD network combines the different input and

output protections. This network works by allowing

safe discharge paths for the pins subject to ESD

stress. Two critical ESD stress cases are

presented in Figure 14.11 and Figure 14.12 for

standard pins.

6WDQGDUGꢀ3LQꢀ3URWHFWLRQ

In order to protect the output structure the following

elements are added:

- A diode to V_DD(3a) and a diode from V_SS(3b)

- A protection device between V_DDand V_SS(4)

In order protect the input structure the following

elements are added:

- A resistor in series with pad (1)

- A diode to V_DD(2a) and a diode from V_SS(2b)

- A protection device between V_DDand V_SS(4)

110/123

67ꢇꢈ)ꢇꢉꢉꢊ)ꢇꢉꢅ

)LJXUHꢀꢄꢌꢆꢄꢄꢀ6DIHꢀGLVFKDUJHꢀSDWKꢀVXEMHFWHGꢀWRꢀ(6'ꢀVWUHVV

VDD

(3a)

(2a)

(1)

OUT

(4)

IN

Main path

Path to avoid

(3b)

(2b)

VSS

)LJXUHꢀꢄꢌꢆꢄꢈꢀ1HJDWLYHꢀ6WUHVVꢀRQꢀDꢀ6WDQGDUGꢀ3DGꢀYVꢆꢀ9''

VDD

(3a)

(2a)

(1)

OUT

(4)

IN

Main path

(3b)

(2b)

VSS

111/123

67ꢇꢈ)ꢇꢉꢉꢊ)ꢇꢉꢅ

ꢄꢌꢆꢄꢅꢀ, &ꢀ,QWHUIDFHꢀ&KDUDFWHULVWLFV

Subject to general operating conditions for VDD,

f^osc, and TA, unless otherwise specified.

Refer to I/O port characteristics for more details on

the input/output alternate function characteristics

(SDA and SCL). The I²C interface meets the

requirements of the Standard I²C communication

protocol described in the following table.

7DEOHꢀꢄꢌꢆꢄꢋꢀ, &ꢀ,QWHUIDFHꢀ&KDUDFWHULVWLFV

1)

t

SCL clock low time

SCL clock high time

SDA setup time

4.7

1.3

w(SCLL)

µs

ns

µs

t

4.0

0.6

w(SCLH)

t

250

100

su(SDA)

3)

2)

3)

t

SDA data hold time

0

900

h(SDA)

t

r(SDA)

20+0.1C

SDA and SCL rise time

SDA and SCL fall time

1000

300

b

t

r(SCL)

t

f(SDA)

300

400

t

f(SCL)

t

START condition hold time

4.0

4.7

4.0

4.7

0.6

1.3

h(STA)

t

Repeated START condition setup time

STOP condition setup time

su(STA)

t

ns

ms

pF

su(STO)

t

STOP to START condition time (bus free)

Capacitive load for each bus line

w(STO:STA)

C

400

b

)LJXUHꢀꢄꢌꢆꢄꢅꢀꢀ, &ꢀ%XVꢀDQGꢀ7LPLQJꢀ'LDJUDPꢀ⁴⁾

1RWHVꢍ

1. Data based on standard I²C protocol requirements, not tested in production.

2. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the

undefinited region of the falling edge of SCL.

3. The maximum hold time of the START condition has only to be met if the interface does not stretch the

low period of the SCL signal.

4. Measurement points are done at levels: 0.3xV_DDand 0.7xV_DD

.

112/123

67ꢇꢈ)ꢇꢉꢉꢊ)ꢇꢉꢅ

ꢄꢌꢆꢄꢌꢀ63,ꢀ&KDUDFWHULVWLFV

Subject to general operating conditions for VDD,

f^osc, and TA, unless otherwise specified.

Refer to I/O port characteristics for more details on

the input/output alternate function characteristics

(SS, SCK, MOSI, MISO ).

f

/64

f

/4

Master

CPU

f

SPI clock frequency

MHz

SCK

Slave

0

CPU

t

r(SCK)

SPI clock rise and fall time

see I/O port pin description

f(SCK)

t

SS setup time

SS hold time

Slave

120

su(SS)

t

h(SS)

t

Master

Slave

100

90

w(SCKH)

SCK high and low time

Data input setup time

Data input hold time

w(SCKL)

t

Master

Slave

100

su(MI)

t

su(SI)

ns

t

Master

Slave

100

h(MI)

t

h(SI)

t

Slave

0

120

240

120

Data output access time

Data output disable time

Data output valid time

Data output hold time

Data output valid time

Data output hold time

a(SO)

t

dis(SO)

t

v(SO)

Slave (after enable edge)

t

0

h(SO)

t

0.25

v(MO)

CLK

cycle

Master (before capture edge)

t

h(MO)

)LJXUHꢀꢄꢌꢆꢄꢌꢀꢀ63,ꢀ6ODYHꢀ7LPLQJꢀ'LDJUDPꢀZLWKꢀ&3+$ꢀ ꢀꢉꢀ³⁾ꢀ

1RWHVꢍ

1. Data based on design simulation and/or characterisation results, not tested in production.

2. When the SPI is disabled it has its alternate function capability released. In this case, the pin status de-

pends on the I/O port configuration.

3. Measurement points are done at levels: 0.3xV_DDand 0.7xV_DD

.

113/123

67ꢇꢈ)ꢇꢉꢉꢊ)ꢇꢉꢅ

)LJXUHꢀꢄꢌꢆꢄꢇꢀꢀ63,ꢀ6ODYHꢀ7LPLQJꢀ'LDJUDPꢀZLWKꢀ&3+$ꢀ ꢀꢉꢀ ꢀ

)LJXUHꢀꢄꢌꢆꢄꢏꢀꢀ63,ꢀ0DVWHUꢀ7LPLQJꢀ'LDJUDP

1RWHVꢍ

1. Measurement points are done at levels: 0.3xV_DDand 0.7xV_DD

.

2. When the SPI is disabled it has its alternate function capability released. In this case, the pin status de-

pends on the I/O port configuration.

114/123

67ꢇꢈ)ꢇꢉꢉꢊ)ꢇꢉꢅ

ꢄꢇꢀ3$&ꢒ$*(ꢀ&+$5$&7(5,67,&6

ꢄꢇꢆꢄꢀ62ꢄꢏꢀ3DFNDJHꢀ'DWD

7DEOHꢀꢄꢇꢆꢄꢀ62ꢄꢏꢀ3$&ꢒ$*(ꢀ0(&+$1,&$/ꢀꢀ'$7$

A

A1

B

C

D

E

H

e

2.35

0.10

2.65

0.30

0.093

0.004

0.013

0.009

0.398

0.291

0.394

0.104

0.012

0.020

0.013

0.413

0.299

0.419

0.33

0.51

0.23

0.32

10.10

7.40

10.50

7.60

10.00

10.65

1.27

0.050

h

0.25

0°

0.75

8°

0.010

0°

0.030

8°

α

L

0.40

1.27

0.016

0.050

Number of pins

N

16

D

h x 45×

L

A

C

A1

a

e

B

H

E

115/123

67ꢇꢈ)ꢇꢉꢉꢊ)ꢇꢉꢅ

ꢄꢇꢆꢈꢀ62ꢈꢉꢀ3DFNDJHꢀ'DWD

7DEOHꢀꢄꢇꢆꢈꢀ62ꢈꢉꢀ3$&ꢒ$*(ꢀ0(&+$1,&$/ꢀꢀ'$7$

A

A1

B

C

D

E

e

2.35

0.1

2.65

0.3

0.093

0.004

0.013

0.009

0.496

0.291

0.104

0.012

0.020

0.013

0.512

0.299

0.33

0.23

12.6

7.4

0.51

0.32

13

7.6

1.27

0.050

H

h

10

0.25

0.4

0°

10.65

0.75

1.27

8°

0.394

0.010

0.016

0°

0.419

0.030

0.050

8°

L

α

D

h x 45×

L

A

c

A1

α

e

B

E

H

116/123

67ꢇꢈ)ꢇꢉꢉꢊ)ꢇꢉꢅ

ꢄꢇꢆꢅꢀ3',3ꢈꢉꢀ3DFNDJHꢀ'DWDꢀ

7DEOHꢀꢄꢇꢆꢅꢀ3',3ꢈꢉꢀ3$&ꢒ$*(ꢀ0(&+$1,&$/ꢀ'$7$

A

A1

A2

b

5.33

0.210

0.38

2.92

0.36

1.14

0.20

24.89

0.13

0.015

0.115

0.014

0.045

0.008

0.980

0.005

3.30

0.46

1.52

0.25

26.16

4.95

0.56

1.78

0.36

26.92

0.130

0.018

0.060

0.010

1.030

0.195

0.022

0.070

0.014

1.060

b2

c

D

D1

e

2.54

0.100

eB

E1

L

10.92

7.11

0.430

0.280

0.150

6.10

2.92

6.35

3.30

0.240

0.115

0.250

0.130

3.81

N

20

A2

A

L

A1

c

b

eB

b2

e

D

20

1

11

E1

10

117/123

67ꢇꢈ)ꢇꢉꢉꢊ)ꢇꢉꢅ

ꢄꢇꢆꢌꢀ62ꢈꢎꢀ3DFNDJHꢀ'DWD

7DEOHꢀꢄꢇꢆꢌꢀ62ꢈꢎꢀ3$&ꢒ$*(ꢀ0(&+$1,&$/ꢀ'$7$

A

A1

B

C

D

E

e

2.35

0.10

0.33

0.23

17.70

7.40

2.65

0.30

0.51

0.32

18.10

7.60

0.093

0.004

0.013

0.009

0.697

0.291

0.104

0.012

0.020

0.013

0.713

0.299

1.27

0.050

H

h

10.00

0.25

0°

10.65

0.75

8°

0.394

0.010

0°

0.419

0.030

8°

α

L

0.40

1.27

0.016

0.050

Number of Pins

N

28

D

h x 45×

L

A

C

A1

α

e

B

E

H

118/123

67ꢇꢈ)ꢇꢉꢉꢊ)ꢇꢉꢅ

ꢄꢇꢆꢇꢀ6',3ꢅꢈꢀ3DFNDJHꢀ'DWD

7DEOHꢀꢄꢇꢆꢇꢀ6',3ꢅꢈꢀ3$&ꢒ$*(ꢀ0(&+$1,&$/ꢀ'$7$

A

A1

A2

b

3.56

0.51

3.05

0.36

0.76

0.20

27.43

9.91

7.62

3.76

5.08

0.140

0.020

0.120

0.014

0.030

0.008

1.080

0.390

0.300

0.148

0.200

3.56

0.46

4.57

0.58

1.40

0.36

28.45

11.05

9.40

0.140

0.018

0.040

0.010

1.100

0.410

0.350

0.070

0.400

0.180

0.023

0.055

0.014

1.120

0.435

0.370

b1

C

1.02

0.25

D

27.94

10.41

8.89

E

E1

e

1.78

eA

eB

eC

L

10.16

12.70

1.40

3.81

0.500

0.055

0.150

2.54

3.05

0.100

0.120

N

32

E

eC

A2

A

A1

L

E1

C

eA

eB

b

b2

e

D

119/123

67ꢇꢈ)ꢇꢉꢉꢊ)ꢇꢉꢅ

ꢄꢏꢀꢀ,03257$17ꢀ127(6

ꢄꢏꢆꢈꢆꢅꢀ,ꢈ&ꢀ*(1(5$/ꢀ&$//ꢀIODJꢆ

'HVFULSWLRQ.

ꢄꢏꢆꢄꢀ6,/,&21ꢀ,'(17,),&$7,21

The General Call Flag, Bit0 on ,ꢈ&ꢀ 6WDWXV

5HJLVWHUꢀꢈꢀꢂ,ꢈ&B65ꢈꢃ [Input Register 8 (08h)] is

not reset if a second Start condition occurs without

a Stop condition or if the peripheral is not disabled

setting to zero Bit5, PE Peripheral enable, on ,ꢈ&

&RQWUROꢀ 5HJLVWHUꢀ ꢂ,ꢈ&B&5ꢃ [Configuration

Register 16 (010h)].

This document describes the limitations that apply

to ST52F500/F503 devices, silicon revision U.

This is identifiable on:

Device package, by the last letter of Trace Code

marked on device package.

On the box, by the last 3 digits of the ,QWHUQDO

6DOHVꢀ7\SH printed on the box label.

:RUNDURXQG.

None. The user has to guarantee that every

communication (start condition) ends with a stop

condition.

Trace Code

Internal Sales Type on

Part Number marked on

box label

device

52F50yxxxx$U3

52F50yxxxx$A3

ꢄꢏꢆꢈꢆꢌꢀ+$/7ꢀQRWꢀVNLSSHGꢆ

'HVFULSWLRQ.

ST52F50yxxxx

Legend: y= 0,3;

“xxxxxxxxxU”

When the Hardware WDT is enabled, if HALT

instruction is preceded by wdtslp instruction or if

none of wdtslp and wdtrfr instruction occurred, Halt

is not skipped.

ꢄꢏꢆꢈꢀ6,/,&21ꢀ/,0,7$7,216

:RUNDURXQG.

The user should avoid using HALT instruction

when hardware WatchDog is used.

ꢄꢏꢆꢈꢆꢄꢀ((3520ꢀZULWLQJꢀHUURUꢀIODJꢆ

'HVFULSWLRQ

When an instruction for writing data ("lder") is

located in a write protected page, (clearly to write

data in an unprotected page of Program/Data

Memory) the writing error flag %LWꢀꢄꢍꢀ357&'ꢀ3DJH

3URWHFWHG of IAP Status Register (IAP_SR) [Input

Register 40 (028h)] is always set even if the writing

is successful.

:RUNDURXQGꢀ

Once the PRTCD bit is set it is anyway possible to

verify the correct writing of a data byte reading the

target location with the instruction "ldre" and

comparing it with the data byte intended to store.

ꢄꢏꢆꢈꢆꢈꢀ&38ꢀ3UHVFDOHUꢀDIWHUꢀ5(6(7ꢆ

'HVFULSWLRQ

The Reset caused by the Watchdog does not reset

the CPU Prescaler Configuration Register

CPL_CLK [Configuration Register 46 (02Eh)] so

the CPU continues to run with the frequency used

before the reset.

:RUNDURXQG

Software workaround can be used: if the user

thinks that a Watchdog Reset is possible, he

should take care of writing the CPU Prescaler

Configuration Register as first instruction after a

WDG reset.

120/123

67ꢇꢈ)ꢇꢉꢉꢊ)ꢇꢉꢅ

ꢄꢋꢀꢀ5(9,6,21ꢀ+,6725<

7DEOHꢀꢄꢋꢆꢄꢀ

'DWH

5HYLVLRQ

'HVFULSWLRQꢀRIꢀ&KDQJHV

Document pagination modified

All hyperlink coloured in blue

All references to RC external oscillator removed

“Clock and Power Supply” on page 1 Up to 24 MHz became Up to 20 MHz

Table 1.2 ST52F500/F503 SDIP32 Pin List on page 13 modified

Table 1.3 ST52F500/F503 SO28 Pin List on page 14 modified

Table 1.4 ST52F500/F503 SO16 Pin List on page 15 modified

Table 1.5 ST52F500/F503 SO20 Pin List on page 16 modified

Table 1.6 ST52F500/F503 DIP20 Pin List on page 17 modified

Figure 3.2 Program/Data Memory Organization on page 24 modified

Table 4.1 Sales Type Memory Organization on page 32 modified

Table 4.2 Programming Mode Commands on page 33 ByteRead

command description modified

Table 4.3 Error codes on page 38 modified

May 04

2.0

(next to

last:

revision

1.20)

Section 4.3.2 Random data reading on page 37 point 6 modified

Section 5.6 Register Description on page 43ꢀ+LJKꢀ3ULRULW\ꢀ5HJLVWHUꢀ

ꢂ,17B35/B+ꢃꢀ(PRL24-PRL0) became (PRL23-PRL0)

Section 6.2.1 External Reset on page 46 “An internal pull up...” sentence

modified

Section 6.5.2 Option Bytes on page 49 Modified programming of the

PLVD_CR (1:0) bits according with the modification made in cut 1.2

Section 7.1 Introduction on page 51 Added note

Section 7.6.1 Configuration Registers on page 53 some notes modiifed

Section 8.5 Input Membership Function on page 58 Rows 6 and 7

exchanged

Section 10.2 Register Description on page 66 WDT_CR exadecimal value

modified to 1

Section 11.5.1 PWM/Timer 0 Configuration Registers on page 71 modified

(STRMOD, RESMOD, RESPOL) description

Section 11.6.2 PWM/Timer 1 Input Registers on page 75 3:0ꢊ7LPHUꢀꢄꢀ

6WDWXVꢀ5HJLVWHUꢀꢂ3:0ꢄB67$786ꢃ bit description modified

Section 12.3.2 Communication Flow on page 77 small modifications

Section 12.5.2 I2C Interface Input Registers on page 84 “Bit 4: BUSY Bus

busy” modified. “Bit 1: %(55ꢀ%XVꢀHUURU´ꢀadded note

Chapter 14 ELECTRICAL CHARACTERISTICS on page 97 added

Chapter 15 PACKAGE Characteristics on page 115 added

Chapter 16 IMPORTANT NOTES on page 120 added

Chapter 17 REVISION HISTORY on page 121 added

Eliminated old references to ST52F504 sales type.

July 04

2.1

121/123

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5HYLVLRQ

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Section Memories on page 1 “Up to 4 Kbytes Data EEPROM” replaced by

“Up to 256 bytes of Data EEPROM”

Section Development tools on page 1 Emulator removed. In-Circuit

debugger added.

Section COMMON FEATURES on page 9 Operating Supply modifiied.

Section 11.4 Timer Interrupts on page 71 added note.

Table 13.1 Serial Peripheral Baud Rate on page 94 added note.

Chapter 14 ELECTRICAL CHARACTERISTICS on page 97 modified.

Dec 04

2.2

Disclaimer on last page modified.

Dec 04

Jan 05

2.3

2.4

Table on Section 14.10.1 General Characteristics on page 106 R_PUMax

Value modified.

122/123

67ꢇꢈ)ꢇꢉꢉꢊ)ꢇꢉꢅ

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics.

All other names are the property of their respective owners

STMicroelectronics group of companies

Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -

Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America

123/123


型号：	ST52F503F2M6
厂家：	ST
描述：	8-BIT, FLASH, 24MHz, MICROCONTROLLER, PDSO20, PLASTIC, SO-20 光电二极管
文件：	总123页 (文件大小：2095K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ST52F503F2M6 [STMICROELECTRONICS]

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