ST52F514G1M6 [STMICROELECTRONICS]
8-BIT, FLASH, 20MHz, MICROCONTROLLER, PDSO28, PLASTIC, SO-28;
| 型号： | ST52F514G1M6 |
| 厂家： | 
ST |
| 描述： | 8-BIT, FLASH, 20MHz, MICROCONTROLLER, PDSO28, PLASTIC, SO-28 时钟 微控制器 光电二极管 外围集成电路 |
| 文件： | 总137页 (文件大小：2529K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ST52F510/F513/F514
®
ST52F510/F513/F514
8-BIT INTELLIGENT CONTROLLER UNIT (ICU)
Two Timer/PWMs, ADC, I2C, SPI, SCI
PRELIMINARY DATA
Memories
I Up to 8 Kbytes Single Voltage Flash Memory
I 256 bytes of Register File
I 256 bytes of RAM
I Up to 4 Kbytes Data EEPROM
I In Situ Programming in Flash devices (ISP)
I Single byte and Page modes and In Application
Programming for writing data in Flash memory
I Readout protection and flexible write protection
Core
I Register File based architecture
I 107 basic instructions
I Hardware multiplication and division
I Decision Processor for the implementation of
LFBGA36
Fuzzy Logic algorithms
I Deep System and User Stacks
Peripherals
I On-chip 10-bit A/D Converter with 8 channel
Clock and Power Supply
I Up to 20 MHz clock frequency
analog multiplexer and Autocalibration.
I 2 Programmable 16 bit Timer/PWMs with
I Programmable Oscillator modes:
– 10 MHz Internal Oscillator
– External Clock/ Oscillator
I Power-On Reset (POR)
internal 16-bit Prescaler featuring:
– PWM output
– Input capture
– Output compare
– Pulse generator mode
I Watchdog timer
I Programmable Low Voltage Detector (PLVD)
with 3 configurable thresholds
I Power Saving features
I Serial Communication Interface (SCI) with
asynchronous protocol (UART).
I I2C Peripheral with master and slave mode
Interrupts
I 8 interrupt vectors with one SW Trap
I 3-wire SPI Peripheral supporting Single
I Non-Maskable Interrupt (NMI)
Master and Multi Master SPI modes
I Two Port Interrupts with up to 16 sources
Development tools
I High level Software tools
I/O Ports
I From 10 up to 22 I/O PINs configurable in pull-
up, push-pull, weak pull-up, open-drain and
high-impedance
I ‘C’ Compiler
I Emulator
I Low cost Programmer
I Gang Programmer
I High current sink/source in all pins
Rev. 2.3 - May 2004
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This is preliminary information on a new product foreseen to be developed. Details are subject to change without notice.
ST52F510/F513/F514
TABLE OF
CONTENTS
TABLE OF CONTENTS
1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
1.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
1.2.1 Memory Programming Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.2.2 Working Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.3 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
2 INTERNAL ARCHITECTURE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.1 Control Unit and Data Processing Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
2.1.1 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.1.2 Flags. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.2 Arithmetic Logic Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
2.3 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
3 ADDRESSING SPACES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.1 Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
3.2 Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
3.3 Program/Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
3.4 System and User Stacks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
3.5 Input Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
3.6 Output registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
3.7 Configuration Registers & Option Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
3.8 Fuzzy registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
4 MEMORY PROGRAMMING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.1 Program/Data Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
4.2 Memory Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
4.2.1 Programming Mode start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.2.2 Fast Programming procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.2.3 Random data writing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.2.4 Option Bytes Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.3 Memory Verify. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
4.3.1 Fast read procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.3.2 Random data reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.4 Memory Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
4.5 ID Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
4.6 Error cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
4.7 In-Situ Programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
4.8 In-Application Programming (IAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
4.8.1 Single byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.8.2 Block write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.8.3 Memory Corruption Prevention. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.8.4 Option Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.8.5 Input Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
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5 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.1 Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
5.2 Global Interrupt Request Enabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
5.3 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
5.4 Interrupt Maskability and Priority Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
5.5 Interrupt RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
5.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
6 CLOCK, RESET & POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . 47
6.1 Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
6.2 Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
6.2.1 External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.2.2 Reset Procedures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.3 Programmable Low Voltage Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
6.4 Power Saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
6.4.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.4.2 Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
6.5.1 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6.5.2 Option Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
7 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
7.2 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
7.3 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
7.4 Interrupt Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
7.5 Alternate Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
7.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
7.6.1 Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
7.6.2 Input Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
7.6.3 Output Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
8 FUZZY COMPUTATION (DP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
8.1 Fuzzy Inference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
8.2 Fuzzyfication Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
8.3 Inference Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
8.4 Defuzzyfication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
8.5 Input Membership Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
8.6 Output Singleton . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
8.7 Fuzzy Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
9 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
9.1 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
9.2 Instruction Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
10 10-bit A/D CONVERTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
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10.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
10.3 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
10.3.1 One Channel Single Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
10.3.2 Multiple Channels Single Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
10.3.3 One Channel Continuous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
10.3.4 Multiple Channels Continuous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
10.4 Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
10.5 A/D Converter Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
10.5.1 A/D Converter Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
10.5.2 Input Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
11 WATCHDOG TIMER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
11.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
11.2 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
12 PWM/TIMERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
12.2 Timer Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
12.3 PWM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
12.3.1 Simultaneous Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
12.4 Timer Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
12.5 PWM/Timer 0 Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
12.5.1 PWM/Timer 0 Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
12.5.2 PWM/Timer 0 Input Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
12.5.3 PWM/Timer 0 Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
12.6 PWM/Timer 1 Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
12.6.1 PWM/Timer 1 Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
12.6.2 PWM/Timer 1 Input Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
12.6.3 PWM/Timer 1 Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
13 SERIAL COMMUNICATION INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
13.1 SCI Receiver block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
13.1.1 Recovery Buffer Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
13.1.2 SCDR_RX Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
13.2 SCI Transmitter Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
13.3 Baud Rate Generator Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
13.4 SCI Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
13.4.1 SCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
13.4.2 SCI Input Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
13.4.3 SCI Output Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
14 I2C BUS INTERFACE (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
14.2 Main Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
14.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
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14.3.1 Mode Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
14.3.2 Communication Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
14.3.3 SDA/SCL Line Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
14.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
14.4.1 Slave Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
14.4.2 Master Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
14.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
14.5.1 I2C Interface Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
14.5.2 I2C Interface Input Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
14.5.3 I2C Interface Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
15 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . 99
15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
15.2 Main Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
15.3 General description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
15.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
15.4.1 Master Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
15.4.2 Slave Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
15.4.3 Data Transfer Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
15.4.4 Write Collision Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
15.4.5 Master Mode Fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
15.4.6 Overrun Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
15.4.7 Single Master and Multimaster Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
15.4.8 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
15.5 SPI Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
15.5.1 SPI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
15.5.2 SPI Input Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
15.5.3 SPI Output Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
16 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
16.1Parameter Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
16.1.1 Minimum and Maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
16.1.2 Typical curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
16.1.3 Typical values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
16.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
16.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
16.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
16.3 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
16.4 Supply Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
16.5 Clock and Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
16.6 Power on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
16.7 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
16.8 Programmable Low Voltage Detector (PLVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
16.9 Internal oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
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16.10 Port Pin Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
16.10.1 General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
16.10.2 Output Driving Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
16.11 Control Pins Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
16.11.1 RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
16.11.2 VPP pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
16.12 EMC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
16.12.1 Functional EMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
16.12.2 Absolute Electrical Sensitivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
16.12.3 Electro-Static Discharge (ESD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
16.12.4 Static and Dynamic Latch-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
16.12.5 ESD Pin Protection Strategy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
16.13 I2C Interface Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
16.14 SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
16.15 10-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
17 PACKAGE Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
17.1 SO16 Package Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
17.2 SO20 Package Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
17.3 PDIP20 Package Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
17.4 SO28 Package Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
17.5 SDIP32 Package Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
17.6 LFBGA36 Package Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
18 IMPORTANT NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
18.1 SILICON IDENTIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
18.2 SILICON LIMITATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
18.2.1 EEPROM writing error flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
18.2.2 CPU Prescaler after RESET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
18.2.3 SCI synchronization in case of consecutive bytes reception . . . . . . . . . . . . . . . . . . . . . 135
18.2.4 I2C GENERAL CALL flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
18.2.5 HALT not skipped . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
19 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
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1 GENERAL DESCRIPTION
1.1 Introduction
ST52F510/F513/F514 are devices of ST FIVE
family of 8-bit Intelligent Controller Units (ICU),
which can perform, both boolean and Fuzzy
algorithms in an efficient manner, in order to reach
the best performances that the two methodologies
allow.
An internal programmable WATCHDOG is
available to avoid loop errors and reset the ICU.
ST52F510/F513/F514 includes a 10-bit, self-
calibrating, Analog to Digital Converter with an 8-
analog channel Multiplexer. Single/Multiple
channels and Single/Sequence conversion modes
are supported. External reference can be supplied
to obtain more stability and precision in the
conversion.
Produced by STMicroelectronics using the reliable
high performance CMOS process for Single
Voltage Flash versions, ST52F510/F513/F514
include integrated on-chip peripherals that allow
maximization of system reliability, and decreased
system costs in order to minimize the number of
external components.
The flexible I/O configuration of ST52F510/F513/
F514 allow one to interface with a wide range of
external devices (for example D/A converters or
power control devices), and to communicate with
the most common serial standards.
ST52F510/F513/F514 pins are configurable. The
user can set input or output signals on each single
pin in 8 different modes, reducing the need for
external components in order to supply a suitable
interface with the port pins.
ST52F510/F513/F514 supply different peripherals
to implement the most common serial
communication protocols. SCI allows the
performance
of
serial
asynchronous
communication (UART). I2C and SPI peripherals
allow the implementation of synchronous serial
protocols. I2C peripherals can work both in master
and slave mode. SPI implements Single and Multi
Master modes using 3-wire.
Up to 8 interrupt vectors are available, which allow
synchronization with peripherals and external
devices. Non-Maskable Interrupt and S/W TRAP
are available. All interrupts have configurable
priority levels and are maskable excluding the
Non-Maskable Interrupt, which has fixed top level
priority. Two versatile Port Interrupts are available
for synchronization with external sources.
The ST52F510/F513/F514 also include an on-chip
Power-on-Reset (POR), which provides an internal
chip reset during power up situation and a
Programmable Low Voltage Detector (PLVD),
which causes the ICU to reset if the voltage source
DD dips below a threshold. Three programmable
thresholds are available, allowing to work with
different supply voltages (from 2.7 to 5.5 V).
In order to optimize energy consumption, two
different power saving modes are available: Wait
mode and Halt mode.
Internal Oscillator at 10 MHz ± 1% is available.
External clock or quartz oscillator are also
applicable. The device always starts with the
Internal Oscillator, then it reads an Option Byte
where the clock mode to be used is programmed.
Program Memory addressing capability addresses
up to 8 Kbytes of memory location to store both
program instructions and data.
Memory can be locked by the user in order to
prevent external undesired operations.
A hardware multiplier and divider, together with a
wide instruction set, allow the implementation of
complex functions by using a single instruction.
Therefore, program memory utilization and
computational speed is optimized.
Fuzzy Logic dedicated structures in ST52F510/
F513/F514 ICU’s can be exploited to model
complex system with high accuracy in a useful and
simple manner.
Fuzzy Expert Systems for overall system
management and Fuzzy Real time Controls can be
designed to increase performance at competitive
costs.
The linguistic approach characterizing Fuzzy Logic
is based on a set of IF-THEN rules, which describe
the control behavior and on Membership Functions
associated with input and output variables.
Up to 340 Membership Functions, with triangular
and trapezoidal shapes, or singleton values are
available to describe fuzzy variables.
The Timer/PWM peripheral allows one to manage
power devices and timing signals, by implementing
different operating modes and high frequency
PWM (Pulse Width Modulation) controls. Input
Capture and Output Compare functions are
available on the Timers.
The Timer has a 16-bit programmable internal
Prescaler and a 16-bit Counter, which can use
internal or external START/STOP signals and
clock.
V
Operations may be performed on data stored in
RAM, allowing direct combination of new inputs
and feedback data. All RAM bytes are used like
Register File.
An additional RAM bench is added to the Program
Memory addressing space in order to allow the
management of the System/User Stacks and user
data storage.
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ST52F510/F513/F514
ST52F510/F513/F514 supply the system stack
and the user stack located in the additional RAM
bench. The user stack can be located anywhere in
the additional RAM by writing the top address in
the configuration registers, in order to avoid
overlap with other data.
Single Voltage Flash allows the user to reprogram
the devices on-board by means of the In Situ
Programming (ISP) feature. It is possible to store in
safe way up to 4K of data in the available EEPROM
memory benches. Permanent data, both in Flash
and EEPROM can be managed by means of the
In-Application-Programming (IAP) feature. Single
byte and Page write modes are supported. Flexible
write protection, of permanent data or program
instructions, is also available.
The Instruction Set composed of up to 107
instructions allows code compression and high
speed in the program implementation.
A powerful development environment consisting of
a board and software tools allows an easy
configuration and use of ST52F510/F513/F514.
The Visual FIVE software tool allows the
development and debugging of projects via a user-
friendly graphical interface and optimization of
generated microcode.
Third-party Hardware Emulators and ‘C’ Compiler
are available to speed-up the application
implementation and time-to-market.
this phase by using the programming tools. The
Option Bytes can only be loaded in this phase and
cannot be modified run-time.
Data and commands are transmitted by using the
I2C protocol, implemented using the internal I2C
peripheral. The In-Situ Programming protocol
(ISP) uses the following pins:
I SDA and SCL for transmission
I Vpp for entering in the mode
I RESET for starting the protocol in a stable status
I Vdd and Vss for the power supply.
The Internal clock is used in this phase.
1.2.2 Working Mode.
The processor starts the working phase following
the instructions, which have been previously
loaded in the first locations of the memory. The first
instruction must be a jump to the first program
instruction, skipping the data (interrupt vectors,
Membership Functions, user data) stored in the
first memory page.
ST52F510/F513/F514’s internal structure includes
two computational blocks, the CONTROL UNIT
(CU) and the DATA PROCESSING UNIT (DPU),
which performs boolean functions. The DECISION
PROCESSOR (DP) block cooperates with these
blocks to perform Fuzzy algorithms.
The DP can manage up to 340 different
Membership Functions for the antecedent part of
fuzzy rules. The consequent terms of the rules are
“crisp” values (real numbers). The maximum
number of rules that can be defined is limited by
the dimensions of the standard algorithm
implemented.
1.2 Functional Description
ST52F510/F513/F514 ICU’s can work in two
modes according to the Vpp signal levels:
I Memory Programming Mode
I Working Mode
The Program/Data Memory is shared between
Fuzzy and standard algorithms. Within this
memory, the user data can be stored both in non
volatile memory as well as in the RAM locations.
The Control Unit (CU) reads information and the
status of the peripherals.
During Working Mode Vpp must be tied to Vss. To
enter the Memory Programming Mode, the Vpp pin
must be tied to Vdd.
A RESET signal must be applied to the device to
switch from one mode to the other.
Arithmetic calculus can be performed on these
values by using the internal CU and Register File,
which supports all computations. The peripheral
inputs can be Fuzzy and/or arithmetic output
values contained in the Register File or Program/
Data Memory.
1.2.1 Memory Programming Mode.
The ST52F510/F513/F514 memory is loaded in
the Memory Programming Mode. All instructions
and data are written inside the memory during this
phase. The user Option Bytes are loaded during
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ST52F510/F513/F514
Table 1.1 ST52F510/F513/F514 Devices Summary
Device
NVM
RF
RAM
EEPROM
Timers
ADC
Comms
SCI I2C
I/O
Package
10-bit
2 Ch
ST52F510YmM6
4/8 K FLASH
256
256
-
2X16-bit
10
So 16
10-bit
6 Ch
SCI I2C
ST52F510FmM6
ST52F510FmB6
ST52F510GmM6
ST52F510KmB6
ST52F513YmM6
ST52F513FmM6
ST52F513FmB6
ST52F513GmM6
ST52F513KmB6
ST52F514FmM6
ST52F514FmB6
ST52F514GmM6
ST52F514KmB6
ST52F513G3H6
4/8 K FLASH
4/8 K FLASH
4/8 K FLASH
4/8 K FLASH
4/8 K FLASH
4/8 K FLASH
4/8 K FLASH
4/8 K FLASH
4/8 K FLASH
4 K FLASH
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
-
2X16-bit
2X16-bit
2X16-bit
2X16-bit
2X16-bit
2X16-bit
2X16-bit
2X16-bit
2X16-bit
2X16-bit
2X16-bit
2X16-bit
2X16-bit
2X16-bit
14
14
22
22
10
14
14
22
22
14
14
22
22
22
So 20
Dip 20
So 28
10-bit
6 Ch
SCI I2C
-
-
10-bit
8 Ch
SCI I2C SPI
SCI I2C SPI
SCI I2C
10-bit
8 Ch
-
256
SDip 32
So 16
10-bit
2 Ch
10-bit
6 Ch
SCI I2C
256
So 20
10-bit
6 Ch
SCI I2C
256
Dip 20
So 28
10-bit
8 Ch
SCI I2C SPI
SCI I2C SPI
SCI I2C
256
10-bit
8 Ch
256
SDip 32
So 20
10-bit
6 Ch
1024 / 4096
1024 / 4096
1024 / 4096
1024 / 4096
256
10-bit
6 Ch
SCI I2C
4 K FLASH
Dip 20
So 28
10-bit
8 Ch
SCI I2C SPI
SCI I2C SPI
SCI I2C SPI
4 K FLASH
10-bit
8 Ch
4 K FLASH
SDip 32
LFBGA36
10-bit
8 Ch
8 K FLASH
COMMON FEATURES
Watchdog
ST52F510/F513/F514
Yes
Other Features
NMI, PLVD, POR, ISP, IAP, Internal Oscillator
From -40° to +85°
Temperature Range
Operating Supply
CPU Frequency
2.7 - 5.5 V
from 1 to 20 MHz.
Legend:
Sales code:
ST52tnnncmpy
F=FLASH
510, 513, 514
Memory type (t):
Subfamily (nnn):
Pin Count (c):
Y=16 pins, F=20 pins, G=28/36 pins, K=32/34 pins
2=4 Kb, 3=8 Kb Flash (ST52F510 & ST52F513)
1=1024, 3=4096 EEPROM (only ST52F514)
Memory Size (m):
Packages (p):
B=PDIP/SDIP, M=PSO, H=LFGBA
Temperature (y):
0=+25, 1=0 +70, 3=-40 +125, 5=-10 +85, 6=-40 +85, 7=-40 +105
9/137
ST52F510/F513/F514
Figure 1.1 ST52F510/F513/F514 Block Diagram
I2C
MEMORY
PA7:0
FLASH
ISP/IAP
PORT A
DATA RAM
256 bytes
TIMER/PWM 0
TIMER/PWM 1
DATA
EEPROM
MEMORY
INTERFACE
ADC
CORE
ALU &
DPU
PB7:0
PC5:0
PORT B
DECISION
PROCESSOR
CONTROL
UNIT
SPI
PORT C
SCI
Register File
256 bytes
Input
registers
PC
FLAGS
WATCHDOG
POWER SUPPLY
POWER ON
RESET
OSCILLATOR
& PLVD
VDD VPP
VSS
OSCIN OSCOUT
RESET
10/137
ST52F510/F513/F514
Figure 1.2 ST52F510/F513/F514 SO20/DIP20 Pin Configuration
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
1
20
Vdd
Vdd
Vss
Vss
2
19
OscOut
OscOut
RESET
RESET
SO20
DIP20
3
18
17
16
15
14
13
12
11
OscIn
Vpp
PA0/SCL
OscIn
Vpp
PA0/SCL
4
PA1/SDA
PA1/SDA
5
PA2/T1OUT
PA3/RX
PA2/T1OUT
PA3/RX
PB0/VREF/AIN0
PB1/AIN1
PB2/AIN2
PB3/AIN3
PB4/AIN4
PB5/AIN5
PB0/VREF/AIN0
PB1/AIN1
6
7
PA4/TSTRT
PA5/TCLK/TX
PA6/T0OUT
PA7/INT
PA4/TSTRT
PA5/TCLK/TX
PA6/T0OUT
PA7/INT
PB2/AIN2
8
PB3/AIN3
9
PB4/AIN4
10
PB5/AIN5
Figure 1.3 ST52F510/F513/F514 SO16 Pin Configuration
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Vdd
Vss
OscOut
RESET
SO16
OscIn
Vpp
PA0/SCL
PA1/SDA
PA2/T1OUT
PA3/RX
PB0/VREF/AIN0
PB1/AIN1
PA7/INT
PA4/TSTRT
PA5/TCLK/TX
PA6/T0OUT
11/137
ST52F510/F513/F514
Figure 1.4 ST52F510/F513/F514 SDIP32/DIP28 Pin Configuration
1
Vdd
VddIO
32
31
30
29
Vss
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vdd
OscOut
Vss
2
VssIO
RESET
2
RESET
OscOut
3
SDIP32
SO28
3
OscIn
PA0/SCL
4
OscIn
PA0/SCL
4
Vpp
PA1/SDA
PA2/T1OUT
PA3/RX
5
Vpp
PA1/SDA
PA2/T1OUT
PA3/RX
28
27
26
25
24
23
22
21
20
19
18
17
5
PB0/VREF/AIN0
PB1/AIN1
PB2/AIN2
PB3/AIN3
6
PB0/VREF/AIN0
PB1/AIN1
PB2/AIN2
PB3/AIN3
PB4/AIN4
PB5/AIN5
PB6/AIN6
PB7AIN7
PC0/SCK
PC1/MOSI
N.C.
6
7
7
PA4/TSTRT
PA5/TCLK/TX
PA6/T0OUT
PA7/INT
8
PA4/TSTRT
8
9
PA5/TCLK/TX
PA6/T0OUT
PA7/INT
9
PB4/AIN4
PB5/AIN5
PB6/AIN6
PB7/AIN7
PC0/SCK
PC1/MOSI
10
11
12
13
14
15
16
10
11
12
13
14
PC5/TRES
PC4/TX
PC5/TRES
PC4/TX
PC3/SS
PC3/SS
PC2/MISO
PC2MISO
N.C.
Figure 1.5 ST52F510/F513/F514 LFBGA36 Pin Configuration (view through package)
1
2
3
4
5
6
N.C.
Vpp
VddIO
Vss
RESET
VssIO
N.C.
PA0/SCL
A
B
C
D
E
F
PB0
VREF
AIN0
N.C.
OSCIN
Vdd
N.C.
PB1
AIN1
PB2
AIN2
PB4
AIN4
PA2
T1OUT
OSCOUT
PB3
AIN3
PB5
AIN5
PC3
SS
PA1
SDA
PA3
RX
PA4
TSTRT
PA5
TX
TCLK
PB7
AIN7
PC1
MOSI
PC4
TX
PA6
T0OUT
N.C.
N.C.
PB6
AIN6
PC0
SCK
PC2
MISO
PC5
TRES
PA7
INT
12/137
ST52F510/F513/F514
See Section Output Driving Current in Electrichal characteristics chapter for Class explanation
Table 1.2 ST52F510/F513/F514 SDIP32 Pin List
SDIP32
NAME
Programming Phase
Working Phase
Class
1
2
3
4
Vdd
VddIO
Digital Power Supply
Digital Power Supply
Digital Power Supply
Digital I/O Ports Power Supply
Oscillator Output
OSCOUT
OSCIN
Oscillator Input
5
6
7
8
Vpp
Programming Mode Selector
Programming Mode Selector
Digital I/O, A/D Voltage Reference, Analog Input
Digital I/O, Analog Input
PB0/VREF/AIN0
PB1/AIN1
A
A
A
PB2/AIN2
Digital I/O, Analog Input
9
PB3/AIN3
PB4/AIN4
PB5/AIN5
PB6/AIN6
PB7/AIN7
PC0/SCK
PC1/MOSI
N.C
A
A
A
A
A
A
A
Digital I/O, Analog Input
Digital I/O, Analog Input
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Digital I/O, Analog Input
Digital I/O, Analog Input
Digital I/O, Analog Input
Digital I/O, SPI Serial Clock
Digital I/O, SPI Master out Slave in
Not Connected
N.C
Not Connected
PC2/MISO
PC3/SS
A
A
A
A
A
A
A
A
A
A
B
B
Digital I/O, SPI Master in Slave out
Digital I/O, SPI Slave Select
Digital I/O, SCI Transmission
Digital I/O, Timer/PWM 0 Reset
Digital I/O, Non Maskable Interrupt
Digital I/O, Timer/PWM 0 output
Digital I/O, Timer/PWM 0 clock
Digital I/O, Timer/PWM 0 start/stop
Digital I/O, SCI Reception
Digital I/O, Timer/PWM 1 output
PC4/TX
PC5/TRES
PA7/INT
PA6/T0OUT
PA5/TCLK/TX
PA4/TSTRT
PA3/RX
PA2/T1OUT
PA1/SDA
PA0/SCL
RESET
2
Serial Data I/O
Serial Clock
Digital I/O, I C Serial Data I/O
2
Digital I/O, I C Serial Clock
General Reset
Digital Ground
Digital Ground
General Reset
Digital I/O Ports Ground
Digital Ground
VssIO
Vss
13/137
ST52F510/F513/F514
Table 1.3 ST52F510/F513/F514 SO28 Pin List
SO28
NAME
Class
Programming Phase
Working Phase
1
2
3
4
Vdd
OSCOUT
OSCIN
Vpp
Digital Power Supply
Digital Power Supply
Oscillator Output
Oscillator Input
Programming Mode Selector
Programming Mode Selector
5
6
7
8
PB0/VREF/AIN0
PB1/AIN1
A
A
A
A
Digital I/O, A/D Voltage Reference, Analog Input
Digital I/O, Analog Input
PB2/AIN2
Digital I/O, Analog Input
PB3/AIN3
Digital I/O, Analog Input
9
PB4/AIN4
PB5/AIN5
PB6/AIN6
PB7/AIN7
PC0/SCK
PC1/MOSI
PC2/MISO
PC3/SS
A
A
B
A
A
A
A
A
A
A
A
A
A
A
A
A
B
B
Digital I/O, Analog Input
Digital I/O, Analog Input
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Digital I/O, Analog Input
Digital I/O, Analog Input
Digital I/O, SPI Serial Clock
Digital I/O, SPI Master out Slave in
Digital I/O, SPI Master in Slave out
Digital I/O, SPI Slave Select
Digital I/O, SCI Transmission
Digital I/O, Timer/PWM 0 Reset
Digital I/O, Non Maskable Interrupt
Digital I/O, Timer/PWM 0 output
Digital I/O, Timer/PWM 0 clock
Digital I/O, Timer/PWM 0 start/stop
Digital I/O, SCI Reception
PC4/TX
PC5/TRES
PA7/INT
PA6/T0OUT
PA5/TCLK/TX
PA4/TSTRT
PA3/RX
PA2/T1OUT
PA1/SDA
PA0/SCL
RESET
Digital I/O, Timer/PWM 1 output
2
Serial Data I/O
Serial Clock
Digital I/O, I C Serial Data I/O
2
Digital I/O, I C Serial Clock
General Reset
Digital Ground
General Reset
Digital Ground
Vss
14/137
ST52F510/F513/F514
Table 1.4 ST52F510/F513/F514 SO16 Pin List
SO16
NAME
Class
Programming Phase
Working Phase
1
2
3
4
Vdd
OSCOUT
OSCIN
Vpp
Digital Power Supply
Digital Power Supply
Oscillator Output
Oscillator Input
Programming Mode Selector
Programming Mode Selector
5
6
PB0/VREF/AIN0
PB1/AIN1
PA7/INT
A
A
B
B
B
B
A
A
A
A
Digital I/O, A/D Voltage Reference, Analog Input
Digital I/O, Analog Input
7
Digital I/O, Non Maskable Interrupt
Digital I/O, Timer/PWM 0 output
8
PA6/T0OUT
PA5/TCLK/TX
PA4/TSTRT
PA3/RX
9
Digital I/O, Timer/PWM 0 clock, SCI transmission
Digital I/O, Timer/PWM 0 start/stop
Digital I/O, SCI Reception
10
11
12
13
14
15
16
PA2/T1OUT
PA1/SDA
PA0/SCL
Digital I/O, Timer/PWM 1 output
2
Serial Data I/O
Serial Clock
Digital I/O, I C Serial Data I/O
2
Digital I/O, I C Serial Clock
RESET
General Reset
Digital Ground
General Reset
Digital Ground
Vss
15/137
ST52F510/F513/F514
Table 1.5 ST52F510/F513/F514 LFBGA 6X6 Pin List
LFBGA36
A1
A2
A3
A4
A5
A6
B1
B2
B3
B4
B5
B6
C1
C2
C3
C4
C5
C6
D1
D2
D3
D4
D5
D6
E1
E2
E3
E4
E5
E6
F1
NAME
N.C.
Class
Programming Phase
Working Phase
Not Connected
Vpp
Programming Mode Selector
Digital Power Supply
Digital Ground
Programming Mode Selector
Digital I/O Ports Power Supply
Digital Ground
VddIO
Vss
RESET
General Reset
General Reset
2
PA0/SCL
N.C.
B
A
Serial Clock
Digital I/O, I C Serial Clock
Not Connected
Digital I/O, A/D Voltage Reference, Analog Input
Oscillator Input
PB0/VREF/AIN0
OSCIN
Vdd
Digital Power Supply
Digital Ground
Digital Power Supply
VssIO
Digital I/O Ports Ground
Not Connected
N.C.
PB1/AIN1
PB2/AIN2
PB4/AIN4
OSCOUT
N.C.
A
A
A
Digital I/O, Analog Input
Digital I/O, Analog Input
Digital I/O, Analog Input
Oscillator Output
Not Connected
PA2/T1OUT
PB3/AIN3
PB5/AIN5
PC3/SS
PA1/SDA
PA3/RX
PA4/TSTRT
N.C.
A
A
A
A
A
A
A
Digital I/O, Timer/PWM 1 output
Digital I/O, Analog Input
Digital I/O, Analog Input
Digital I/O, SPI Slave Select
2
Serial Data I/O
Digital I/O, I C Serial Data I/O
Digital I/O, SCI Reception
Digital I/O, Timer/PWM 0 start/stop
Not Connected
Digital I/O, Analog Input
PB7/AIN7
PC1/MOSI
PC4/TX
PA5/TCLK/TX
PA6/T0OUT
N.C.
A
A
A
A
B
Digital I/O, SPI Master out Slave in
Digital I/O, SCI Transmission
Digital I/O, Timer/PWM 0 clock, SCI transmission
Digital I/O, Timer/PWM 0 output
Not Connected
F2
PB6/AIN6
PC0/SCK
PC2/MISO
PC5/TRES
PA7/INT
A
A
A
A
A
Digital I/O, Analog Input
F3
Digital I/O, SPI Serial Clock
Digital I/O, SPI Master in Slave out
Digital I/O, Timer/PWM 0 Reset
F4
F5
F6
Digital I/O, Non Maskable Interrupt
16/137
ST52F510/F513/F514
Table 1.6 ST52F510/F513/F514 SO20 Pin List
SO20
NAME
Class
Programming Phase
Working Phase
1
2
3
4
Vdd
OSCOUT
OSCIN
Vpp
Digital Power Supply
Digital Power Supply
Oscillator Output
Oscillator Input
Programming Mode Selector
Programming Mode Selector
5
6
7
8
PB0/VREF/AIN0
PB1/AIN1
A
A
A
A
Digital I/O, A/D Voltage Reference, Analog Input
Digital I/O, Analog Input
PB2/AIN2
Digital I/O, Analog Input
PB3/AIN3
Digital I/O, Analog Input
9
PB4/AIN4
PB5/AIN5
PA7/INT
B
B
B
B
A
A
A
A
A
A
Digital I/O, Analog Input
Digital I/O, Analog Input
10
11
12
13
14
15
16
17
18
19
20
Digital I/O, Non Maskable Interrupt
Digital I/O, Timer/PWM 0 output
Digital I/O, Timer/PWM 0 clock, SCI transmission
Digital I/O, Timer/PWM 0 start/stop
Digital I/O, SCI Reception
PA6/T0OUT
PA5/TCLK/TX
PA4/TSTRT
PA3/RX
PA2/T1OUT
PA1/SDA
PA0/SCL
RESET
Digital I/O, Timer/PWM 1 output
2
Serial Data I/O
Serial Clock
Digital I/O, I C Serial Data I/O
2
Digital I/O, I C Serial Clock
General Reset
Digital Ground
General Reset
Digital Ground
Vss
17/137
ST52F510/F513/F514
Table 1.7 ST52F510/F513/F514 DIP20 Pin List
DIP20
NAME
Class
Programming Phase
Working Phase
1
2
3
4
Vdd
OSCOUT
OSCIN
Vpp
Digital Power Supply
Digital Power Supply
Oscillator Output
Oscillator Input
Programming Mode Selector
Programming Mode Selector
5
6
7
8
PB0/VREF/AIN0
PB1/AIN1
A
A
B
B
Digital I/O, A/D Voltage Reference, Analog Input
Digital I/O, Analog Input
PB2/AIN2
Digital I/O, Analog Input
PB3/AIN3
Digital I/O, Analog Input
9
PB4/AIN4
PB5/AIN5
PA7/INT
B
B
B
B
B
B
A
A
B
B
Digital I/O, Analog Input
Digital I/O, Analog Input
10
11
12
13
14
15
16
17
18
19
20
Digital I/O, Non Maskable Interrupt
Digital I/O, Timer/PWM 0 output
Digital I/O, Timer/PWM 0 clock, SCI transmission
Digital I/O, Timer/PWM 0 start/stop
Digital I/O, SCI Reception
PA6/T0OUT
PA5/TCLK/TX
PA4/TSTRT
PA3/RX
PA2/T1OUT
PA1/SDA
PA0/SCL
RESET
Digital I/O, Timer/PWM 1 output
2
Serial Data I/O
Serial Clock
Digital I/O, I C Serial Data I/O
2
Digital I/O, I C Serial Clock
General Reset
Digital Ground
General Reset
Digital Ground
Vss
18/137
ST52F510/F513/F514
1.3 Pin Description
VREF, AIN0-AIN7. These pins are used to input
the analog signals into the A/D Converter. An
analog multiplexer is available to switch these
inputs to the A/D Converter. The pin VREF is used
to input an external A/D Reference Voltage.
ST52F510/F513/F514 pins can be set in digital
input mode, digital output mode, interrupt mode or
in Alternate Functions. Pin configuration is
achieved by means of the configuration registers.
The functions of the ST52F510/F513/F514 pins
are described below:
T0OUT, T1OUT. These pins output the signals
generated by the PWM/Timer 0 and PWM/Timer 1
peripheral.
VDD. Main Power Supply Voltage.
TRES, TSTRT, TCLK . These pins are related to
the PWM/Timer 0 peripheral and are used for Input
Capture and event counting. The TRES pin is used
to set/reset the Timer; the TSTRT pin is used to
start/stop the counter. The Timer can be driven by
the internal clock or by an external signal
connected to the TCLK pin.
VDDIO. I/O Ports Power Supply Voltage. It is
reccomended to connect this pin with a supply
voltage de-coupled with VDD in order to improve
the immunity from the noise generated by the I/O
switching.
VSS. Digital circuit Ground.
INT. This pin is used as input for the Non-Maskable
(top level) interrupt. The interrupt signal is detected
only if the pin is configured in Alternate Function.
VSSIO. I/O Ports Ground. See VDDIO
VPP. Programming/Working mode selector. During
the Programming phase VPP must be set to VDD
.
SCL, SDA. These pin are used respectively as
Serial Clock and Serial Data I/O in I2C peripheral
protocol. They are used also in Programming
Mode to receive and transmit data.
In Working phase VPP must be equal to VSS
.
OSCin and OSCout. These pins are internally
connected to the on-chip oscillator circuit. A quartz
crystal or a ceramic resonator can be connected
between these two pins in order to allow correct
use of ST52F510/F513/F514 with various stability/
cost trade-offs. An external clock signal can be
applied to OSCin: in this case OSCout can be
floating. Without any connection, the device can
work with its internal clock generator (10 MHz)
TX, RX. Serial data output of SCI Transmitter block
(TX) and Serial data input of the SCI Receiver
block (RX).
SCK, MISO, MOSI, SS. These pins are used by
the Serial Peripheral Interface (SPI) peripheral.
SCK is the serial clock line. MISO (Master In Slave
Out) and MOSI (Master Out Slave In) are the serial
data lines, which work in input or in output
depending on if the device is working in slave or
master mode. The SS pin allows the selection of
the device master/slave mode.
RESET. This signal is used to reset the ST52F510/
F513/F514 and re-initialize the registers and
control signals. It is also used when switching from
the Programming Mode to Working Mode and vice
versa.
PA0-PA7, PB0-PB7,PC0-PC5. These lines are
organized as I/O ports. Each pin can be configured
as an input, output (with pull-up, push-pull, weak-
pull-up, open-drain, high-impedance), or as an
interrupt source.
19/137
ST52F510/F513/F514
2 INTERNAL ARCHITECTURE
2.1 Control Unit and Data Processing Unit
The Control Unit (CU) decodes the instructions
stored in the Program Memory and generates the
appropriate control signals. The main parts of the
CU are illustrated in Figure 2.1.
The five different parts of the CU manage Loading,
Logic/Arithmetic, Jump, Control and the Fuzzy
instruction set.
The block called “Collector” manages the signals
deriving from the different parts of the CU. The
collector defines the signals for the Data
Processing Unit (DPU) and Decision Processor
(DP), as well as for the different peripherals of the
ICU.
The block called “Arbiter” manages the different
parts of the CU, so that only one part of the system
is activated during working mode.
The CU structure is extremely flexible and was
designed with the purpose of easily adapting the
core of the microcontroller to market needs. New
instruction sets or new peripherals can easily be
included without changing the structure of the
microcontroller, maintaining code compatibility.
A set of 107 different instructions is available. Each
instruction requires a number of clock pulses to be
performed that depends on the complexity of the
instruction itself. The clock pulses to execute the
instructions are driven directly by the masterclock,
which has the same frequency of the oscillator
signal supplied.
ST52F510/F513/F514’s architecture is Register
File based and is composed of the following blocks
and peripherals:
I Control Unit (CU)
I Data Processing Unit (DPU)
I Decision Processor (DP)
I ALU
I Memory Interface
I up to 256 bytes Register File
I Program/Data Memory
I Data EEPROM
I Interrupts Controller
I Clock Oscillator
I PLVD and POR
I Digital I/O ports
I Analog Multiplexer and A/D Converter
I Timer/PWMs
I I2C
I SPI
I SCI
Figure 2.1 CU Block Diagram
MicroCode
Loading
Instruction Set
C
O
L
Logic Arithmetic
Instruction Set
A
R
B
L
I
T
E
Jump
Instruction Set
E
C
T
Control
Signals
R
O
R
Control
Instruction Set
Decision Processor
Clock Master
Instruction Set
20/137
ST52F510/F513/F514
Figure 2.2 Data Processing Unit (DPU)
Interrupts Unit
PROGRAM COUNTER
Memory Address
Program Memory
Input Registers
Peripherals
Control Unit
Peripherals
REGISTER
FILE
DECISION
PROCESSOR
REGISTERS
REGISTER FILE
ADDRESS
256 Bytes
ACCUMULATOR
FLAGS REG.
ALU
The DPU receives, stores and sends the
instructions deriving from the Program/Data
Memory, Register File or from the peripherals. It is
controlled by the CU on the basis of the decoded
instruction. The Fuzzy registers store the partial
results of the fuzzy computation. The accumulator
register is used by the ALU and is not accessible
directly: the instructions used by the ALU can
address all the Register File locations as
operands, allowing a more compact code and a
faster execution.
The PC can be changed in the following ways:
I JP (Jump)
I Interrupt
I RETI
PC = Jump Address
PC = Interrupt Vector
PC = Pop (stack)
I RET
PC = Pop (stack)
I CALL
PC = Subroutines address
PC = Reset Vector
I Reset
I Normal Instruction PC = PC + instr. lenght
The following addressing modes are available:
inherent, immediate, direct, indirect, bit direct.
2.1.2 Flags.
The ST FIVE core includes different sets of flags
that correspond to 2 different modes: normal mode
and interrupt mode. Each set of flags consist of a
CARRY flag (C), ZERO flag (Z) and SIGN flag (S).
Each set is stacked: one set of flags is used during
normal operation and other sets are used during
each level of interrupt. Formally, the user has to
manage only one set of flags: C, Z and S since the
flag stack operation is performed automatically.
2.1.1 Program Counter.
The Program Counter (PC) is a 16-bit register that
contains the address of the next memory location
to be processed by the core. This memory location
may be both an instruction or data address.
The Program Counter’s 16-bit length allows the
direct addressing of a maximum of 64 Kbytes in the
Program/Data Memory space.
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ST52F510/F513/F514
Each interrupt level has its own set of flags, which
is saved in the Flag Stack during interrupt
servicing. These flags are restored from the Flag
Stack automatically when a RETI instruction is
executed.
If the ICU was in normal mode before an interrupt,
after the RETI instruction is executed, the normal
flags are restored.
2.2 Arithmetic Logic Unit
The 8-bit Arithmetic Logic Unit (ALU) performs
arithmetic calculations and logic instructions such
as: sum, subtraction, bitwise AND, OR, XOR, bit
set and reset, bit test and branch, right/left shift and
rotate (see Chapter 9 Instruction Set for further
details).
In addition, the ALU of ST52F510/F513/F514 can
perform multiplication (MULT) and division (DIV).
Multiplication is performed by using 8 bit operands
storing the result in 2 registers (16 bit values); the
division instruction addresses the MSB of the
dividend (the LSB is stored in the next address):
the result and remainder are stored in these source
addresses (see Figure 2.3 and Figure 2.4).
Note: A subroutine CALL is a normal mode
execution. For this reason a RET instruction,
consequent to a CALL instruction, doesn’t affect
the normal mode set of flags.
Flags are not cleared during context switching and
remain in the state they were in at the exit of the
last interrupt routine switching.
The Carry flag is set when an overflow occurs
during arithmetic operations, otherwise it is
cleared. The Sign flag is set when an underflow
occurs during arithmetic operations, otherwise it is
cleared.
In order to manage signed type values, the ALU
also performs addition and subtraction with offset
(ADDO
and
SUBO).
These
instructions
respectively subtract and add 128 to the overall
result, in order to manage values logically in the
range between -128,127.
The flags, related to the current context, can be
checked by reading the FLAGS Input Register 38
(026h).
Figure 2.4 Division
Figure 2.3 Multiplication
RAM
RAM
000h
001h
002h
000h
001h
002h
i-1
i
i
i+1
j-1
j
j-1
j
j+1
j+1
0FDh
0FEh
0FFh
0FDh
0FEh
0FFh
X
REG. j
LSB
REG. i
MSB
:
REG. j
REG. j+1
REG. i
16 Bit
REMAINDER
QUOTIENT
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ST52F510/F513/F514
2.3 Register Description
Flags Register (FLAG)
Input Register 38 (026h) Read Only
Reset Value: 0000 0000 (00h)
7
0
C
-
-
-
-
-
Z
S
Bit 7-3: Not Used
Bit 2: Z Zero flag
Bit 1: S Sign flag
Bit 0: C Carry flag
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ST52F510/F513/F514
3 ADDRESSING SPACES
3.2 Register File
The Register File consists of 256 general purpose
8-bit RAM locations called “registers” in order to
recall the functionality.
The Register File exchanges data with all the other
addressing spaces and is used by the ALU to
perform all the arithmetic and logic instructions.
These instructions have any Register File address
as operands.
ST52F510/F513 has six separate addressing
spaces:
I Register File
I Program/Data Memory and Stacks
I Input Registers
I Output Registers
Data can be moved from one location to another by
using the LDRR instruction; see further ahead for
information on the instruction used to move data
between the Register File and the other
addressing spaces.
I Configuration Registers
I Fuzzy Registers
Note: stack is in the same address space of
Program memory.
Each space is addressed by a load type instruction
that indicates the source and the destination space
in the mnemonic code (see Figure 3.1).
3.3 Program/Data Memory
The Program/Data Memory consists of both non-
volatile memory (Flash, EEPROM) and RAM
memory benches.
Non-volatile memory (NVM) is mainly used to store
the user program and can also be used to store
permanent data (constant, look-up tables).
Each RAM bench consists of 256 locations used to
store run-time user data. At least one bench is
present in the devices. RAM benches are also
used to implement both System and User Stacks.
NVM & RAM locations can be accessed by means
of the LDER and LDRE instructions.
3.1 Memory Interface
The read/write operation in the space addresses
are managed by the Memory Interface, which can
recognize the type of memory addressed and set
the appropriate access time and mode.
In addition, the Memory Interface manages the In
Application Programming (IAP) functions in Flash
devices like writing cycle and memory write
protection.
Figure 3.1 Addressing Spaces
STFive CORE
PROGRAM/DATA MEMORY
ON CHIP PERIPHERALS
REGISTER FILE
DECISION
PROCESSOR
REGISTERS
OUTPUT
REGISTERS
NON VOLATILE MEMORY
LDFR
LDER
LDPR
LDCNF
GETPG
PERIPHERAL
BLOCK
LDRE
PGSETR
PROGRAM
COUNTER
PERIPHERAL
BLOCK
RAM BANKS
AND STACKS
CONFIGURATION
REGISTERS
INPUT REGISTERS
LDCR
LDRI
CU
DPU
ALU
PERIPHERAL
BLOCK
LDCE
LDPE
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ST52F510/F513/F514
NVM is always located beginning after the first
locations of the addressing space. RAM banks are
always located after NVM.
NVM is organized in accordance to the following
blocks (see Figure 3.2):
I Reset Vector block (from address 0 to 2)
contains an absolute jump instruction to the first
user program instruction. The Assembler tool
automatically fills these locations with correct
data.
I Mbfs Setting block (just after the interrupt
vectors) contains the coordinates of the vertexes
of every Mbf defined in the program. The last
address that can be assigned to this block is
1023. This area is dynamically assigned
according to the size of the fuzzy routines. The
memory area that remains unused, if any, is
assigned to the Program Instructions block.
I The Program Instructions block (just after the
last Mbf data through the last NVM address)
contains the instruction of the user program and
the permanent data.
I Interrupt Vectors block (from location 3 up to
32) contains the interrupt vectors. Each address
is composed of three bytes (the jump opcode
and the 16 bit address). Interrupt vectors are set
by using IRQ pseudo-instruction (see the
Programming Manual).
I Option bytes block (from location 3000h to
307Fh) is the addressing space reserved for the
option bytes. In ST52F510/F513, only the
location from 3000h to 3007h are used.
Figure 3.2 Program/Data Memory Organization
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ST52F510/F513/F514
Flash and EEPROM are programmed electrically
just applying the supply voltage and they are also
erased electrically; this feature allows the user to
easily reprogram the memory without taking the
device off from the board (In Situ Programming
ISP). Data and commands are transmitted through
the I2C serial communication protocol. Data can
also be written run-time with the In Application
Programming (IAP)
NVM can be locked by the user during the
programming phase, in order to prevent external
operation such as reading the program code and
assuring protection of user intellectual property.
Flash and EEPROM pages can be protected by
unintentional writings.
3.4 System and User Stacks
The System and User Stacks are located in the
Program/Data memory in the RAM benches.
System Stacks are used to push the Program
Counter (PC) after an Interrupt Request or a
Subroutine Call. After a RET (Return from a
subroutine) or a RETI (Return from an interrupt)
the PC that is saved is popped from the stack and
restored. After an interrupt request, the flags are
also saved in a reserved stack inside the core, so
each interrupt has its own flags.
The System Stack is located in the last RAM bench
starting from the last address (20FFh) inside the
bench page. The System Stack Pointer (SSP) can
be read and modified by the user. For each level of
stack 2 bytes of the RAM are used. The SSP points
to the first currently available stack position. When
a subroutine call or interrupt request occurs, the
content of the PC is stored in a couple of locations
pointed to by the SSP that is decreased by 2.
The operations that can be performed on the NVM
during the Programming Phase, ISP and IAP are
described in detail in the Section 4.
Figure 3.3 System and User Stack
RAM BENCH
PROGRAM COUNTER
20FFh
SYSTEM STACK
RETI
LOCATION ADRESS
PAGE NUMBER
LSB
20FEh
LEVEL 1
MSB
SYSTEM STACK
LEVEL 2
SYSTEM STACK
IRQ
POINTER
SYSTEM STACK
LEVEL 3
REGISTER FILE
SYSTEM STACK
LEVEL 4
POP X
REGISTER X
USER DATA
CONFIGURATION REGISTERS
USER STACK LEVEL 4
USER STACK LEVEL 3
USER STACK LEVEL 2
USER STACK
POINTER
PUSH X
USER STACK TOP LSB
USER STACK TOP MSB
USER STACK LEVEL 1
2001h
2000h
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ST52F510/F513/F514
When a return occurs (RET or RETI instruction),
the SSP is increased by 2 and the data stored in
the pointed locations couple is restored back into
the PC.
The current SSP can be read and write in the
couple of Configuration Registers 44 02Ch (MSB:
page number, always 32 020h) and 45 02Dh (LSB:
location address) (see Figure 3.3). In ST52F510/
F513 the user can only consider the LSB because
the MSB is always the same.
The User Stack is used to store user data and is
located beginning from a RAM bench location set
by the user (USTP) by writing the couple of
Configuration Registers 5 005h (MSB: page
number) and 6 006h (LSB: location address) (see
Figure 3.3). Register 5, which is the page number,
must always be set to a value between 32 (020h)
and 255 (0FFh): values higher than 32 always
address RAM on page 32.
Input Registers contain data converted by the
ADC, Ports, serial communication peripherals,
Timers, etc.
The Input Registers can be accessed by using the
LDRI instruction that loads the specified Register
File address with the contents of the specified
Input Register. See the Programming Manual for
further details on this instruction. The Input
Registers are read-only registers.
In order to simplify the concept, a mnemonic name
is assigned to each register. The same name is
used in Visual FIVE development tools. The list of
the Input Registers is shown in Table 3.1.
3.6 Output registers
The ST52F510/F513 Output Registers bench
consists of a file of 8-bit registers containing data
sent to the Peripherals and the I/O Ports (for
example: Timer Counters, data to be transmitted
by the serial communication peripherals, data to be
sent to the Port pins in output, etc.).
The registers are located inside the Peripherals
and Ports, which allow flexibility and modularity in
the design of new family devices.
Note: In ST52F510/F513 MSB doesn’t have to be
set or read because the RAM is only 256 bytes.
The LSB of the user stack is equal to 0 at reset.
The LSB of the system stack is equal to 255 at
reset.
This feature allows a flexible use of the User Stack
in terms of dimension and to avoid overlaps. The
User Stack Pointer (USP) points to the first
currently available stack location. When the user
stores a byte value contained in the Register File
by using the PUSH instruction, the value is stored
in the position pointed to by the USP that is
increased (the User Stack order is opposite to the
System Stack one). When the user takes a value
from the User Stack with the POP instruction, the
USP is decreased and the value pointed to is
copied in the specified Register File location.
By writing the USTP, the new address is
automatically written in the USP. The current USP
can be read from the Input Registers 11 0Bh
(MSB: page number, always 32 020h) and 12 0Ch
(LSB: location address) (see Figure 3.3). In
ST52F510/F513 the user can only consider the
LSB because the MSB is always the same.
The Output Registers are write only. In order to
access the configuration Register the user can use
the following instructions:
I LDPI: loads the immediate value in the specified
Output Register.
I LDPR: loads the contents of the specified
Register File location into the output register
specified. This instruction allows computed data
to be sent to Peripherals and Ports.
I LDPE direct: loads the contents of the specified
Program/Data Memory location into the output
register specified. This instruction allows data to
be sent to Peripherals and Ports from a table.
I LDPE indirect: loads the contents of the
Program/Data Memory location whose address
is contained in the specified Register File
location into the output register specified. This
instruction allows data to be sent to Peripherals
and Ports from a table pointed to by a register.
Note: The user must pay close attention to avoid
overlapping user and Stacks data. The User Stack
Top location and the System Stack Pointer should
be configured with care in order to have enough
space between the two stacks.
See the Programming manual for further details
about these instructions.
In order to simplify the concept, a mnemonic name
is assigned to each register. The same name is
used in Visual FIVE development tools. The list of
the Output Registers is shown in Table 3.2.
3.5 Input Registers
The ST52F510/F513 Input Registers bench
consists of a file of 8-bit registers containing data
or the status of the peripherals. For example, the
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ST52F510/F513/F514
3.7 Configuration Registers & Option Bytes
I LDCE: loads the Configuration Register
specified with the contents of the specified
Program/Data Memory location, allowing the
configuration data to be taken from a table.
The ST52F510/F513 Configuration Registers
bench consists of a file of 8-bit registers that allows
the configuration of all the ICU blocks.
The registers are located inside the block they
configure in order to obtain greater flexibility and
modularity in the design of new family devices. In
the Configuration Registers, each bit has a
particular use, so the logic level of each of them
must be considered.
I LDCNF: loads the
Register File location
specified with the contents of the Configuration
Register indicated, allowing for the inspection of
the configuration of the device (permitting safe
run-time modifications).
Some special configuration data, that needs to be
load at the start-up and not further changed, are
stored in Option Bytes. These are loaded only
during the device programming phase. See Table
3.3 and Section 4 for a detailed description of the
Option Bytes.
The Configuration Registers are readable and
writable; the addresses refer to the same register
both in read and in write. In order to access the
Configuration Register the user can work in
several modes by utilizing the following
instructions:
In order to simplify the concept, a mnemonic name
is assigned to each register. The same name is
used in Visual FIVE development tools. The list of
the Configuration Registers is shown in Table 3.4.
3.8 Fuzzy registers
The Decision Processor for Fuzzy computation is
accessed by means of 8 dedicated registers.
These registers are used to load values in input to
the Decision Processor.
The values are loaded in the Fuzzy Register by
mean of the LDFR instruction. This instruction set
the specified Fuzzy Register (addresses from 0 to
7) with the value stored in the specified address of
the Register File.
I LDCI: loads the immediate value in the
Configuration Register specified and is the most
commonly used to write configuration data.
I LDCR: loads the Configuration Register
specified with the contents of the specified
Register File location, allowing a parametric
configuration.
See Chapter 8 FUZZY COMPUTATION (DP) for
further informations.
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ST52F510/F513/F514
Table 3.1 Input Registers
Mnemonic
Description
Port A data Input Register
Address
PORT_A_IN
PORT_B_IN
PORT_C_IN
-
0
1
2
3
4
5
6
00h
01h
02h
03h
04h
05h
06h
Port B data Input Register
Port C data Input Register
Not Used
-
Not Used
SPI_IN
I2C_IN
Serial Peripheral Interface data Input Register
2
I C Interface data Input Register
2
I2C_SR1
7
07h
I C Interface Status Register 1
2
I2C_SR2
8
08h
09h
0Ah
0Bh
0Ch
I C Interface Status Register 2
-
Not Used
9
-
Not Used
10
11
12
USP_H
USP_L
User Stack Pointer (MSB)
User Stack Pointer (LSB)
0Dh-
014h
-
Not Used
13-20
PWM0_COUNT_IN_H
PWM0_COUNT_IN_L
PWM0_STATUS
PWM/Timer 0 Counter Input Register (MSB)
PWM/Timer 0 Counter Input Register (LSB)
PWM/Timer 0 Status Register
21
22
23
24
25
26
27
28
29
30
015h
016h
017h
018h
019h
01Ah
01Bh
01Ch
01Dh
01Eh
PWM0_CAPTURE_H
PWM0_CAPTURE_L
PWM1_COUNT_IN_H
PWM1_COUNT_IN_L
PWM1_STATUS
PWM/Timer 0 Capture Register (MSB)
PWM/Timer 0 Capture Register (LSB)
PWM/Timer 1 Counter Input Register (MSB)
PWM/Timer 1 Counter Input Register (LSB)
PWM/Timer 1 Status Register
PWM1_CAPTURE_H
PWM1_CAPTURE_L
PWM/Timer 1 Capture Register (MSB)
PWM/Timer 1 Capture Register (LSB)
01Fh-
023h
-
Not Used
31-35
SCI_IN
Serial Communication Interface RX data Input Register
Serial Communication Interface Status Register
Flag Register
36
37
38
39
40
024h
025h
026h
027h
028h
SCI_STATUS
FLAGS
AD_OVF
IAP_SR
10-bit A/D Converter Overflow Register
In Application Programming Status Register
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Table 3.1 Input Registers
Mnemonic
CHAN0_H
CHAN0_L
Description
Address
41
10-bit A/D Converter Channel 0 data Input Register (MSB)
10-bit A/D Converter Channel 0 data Input Register (LSB)
10-bit A/D Converter Channel 1 data Input Register (MSB)
10-bit A/D Converter Channel 1 data Input Register (LSB)
10-bit A/D Converter Channel 2 data Input Register (MSB)
10-bit A/D Converter Channel 2 data Input Register (LSB)
10-bit A/D Converter Channel 3 data Input Register (MSB)
10-bit A/D Converter Channel 3 data Input Register (LSB)
10-bit A/D Converter Channel 4 data Input Register (MSB)
10-bit A/D Converter Channel 4 data Input Register (LSB)
10-bit A/D Converter Channel 5 data Input Register (MSB)
10-bit A/D Converter Channel 5 data Input Register (LSB)
10-bit A/D Converter Channel 6 data Input Register (MSB)
10-bit A/D Converter Channel 6 data Input Register (LSB)
10-bit A/D Converter Channel 7 data Input Register (MSB)
10-bit A/D Converter Channel 7 data Input Register (LSB)
029h
02Ah
02Bh
02Ch
02Dh
02Eh
02Fh
030h
031h
032h
033h
034h
035h
036h
037h
038h
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
CHAN1_H
CHAN1_L
CHAN2_H
CHAN2_L
CHAN3_H
CHAN3_L
CHAN4_H
CHAN4_L
CHAN5_H
CHAN5_L
CHAN6_H
CHAN6_L
CHAN7_H
CHAN7_L
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Table 3.2 Output Registers
Mnemonic
Description
Port A data Output Register
Address
PORT_A_OUT
0
1
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
017h
PORT_B_OUT
Port B data Output Register
Port C data Output Register
Not Used
PORT_C_OUT
-
2
3
-
Not Used
4
SPI_OUT
Serial Peripheral Interface data Output Register
5
2
I2C_OUT
6
I C Interface data Output Register
PWM0_COUNT_OUT_H
PWM0_COUNT_OUT_L
PWM0_RELOAD_H
PWM0_RELOAD_L
PWM1_COUNT_OUT_H
PWM1_COUNT_OUT_L
PWM1_RELOAD_H
PWM1_RELOAD_L
SCI_OUT
PWM/Timer 0 Counter Output Register (MSB)
PWM/Timer 0 Counter Output Register (LSB)
PWM/Timer 0 Reload Register (MSB)
7
8
9
PWM/Timer 0 Reload Register (LSB)
10
11
12
13
14
23
PWM/Timer 1 Counter Output Register (MSB)
PWM/Timer 1 Counter Output Register (LSB)
PWM/Timer 1 Reload Register (MSB)
PWM/Timer 1 Reload Register (LSB)
Serial Communication Interface TX data Output Register
Table 3.3 Option Bytes
Mnemonic
Description
Oscillator Control Register
Clock Parameters
Address
OSC_CR
0
1
2
3
4
5
6
7
00h
01h
02h
03h
04h
05h
06h
07h
CLK_SET
OSC_SET
Oscillator Set-Up
PLDV_CR
Programmable Low Voltage Detector Control Register
HW/SW Watchdog selector
First Page Write Protected
First Page not Write Protected
Wake Up from Halt Time
WDT_EN
PG_LOCK
PG_UNLOCK
WAKEUP
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Table 3.4 Configuration Registers
Mnemonic
Description
Interrupt Mask Register
Interrupts Polarity
Address
INT_MASK
INT_POL
INT_PRL_L
INT_PRL_M
INT_PRL_H
USTP_H
USTP_L
0
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
010h
1
2
Interrupt Priority Register (lower priority)
Interrupt Priority Register (medium priority)
Interrupt Priority Register (higher priority)
User Stack Top Pointer (MSB)
3
4
5
User Stack Top Pointer (LSB)
6
WDT_CR
AD_CR1
PWM0_CR1
PWM0_CR2
PWM0_CR3
PWM1_CR1
PWM1_CR2
-
Watchdog Configuration Register
10-bit A/D Converter Control Register 1
PWM/Timer 0 Configuration Register 1
PWM/Timer 0 Configuration Register 2
PWM/Timer 0 Configuration Register 3
PWM/Timer 1 Configuration Register 1
PWM/Timer 1 Configuration Register 2
Not Used
7
8
9
10
11
12
13
14
15
16
-
Not Used
2
I2C_CR
I C Interface Control Register
2
I2C_CCR
17
18
011h
012h
I C Interface Clock Control Register
2
I2C_OAR1
I C Interface Own Address Register 1
2
I2C_OAR2
19
20
21
22
23
24
25
013h
014h
015h
016h
017h
018h
019h
I C Interface Own Address Register 2
SPI_CR
Serial Peripheral Interface Control Register
Serial Peripheral Interface Control-Status Register
Serial Communication Interface Control Register 1
Serial Communication Interface Control Register 2
Port A Pull Up enable/disable Register
SPI_STATUS_CR
SCI_CR1
SCI_CR2
PORT_A_PULLUP
PORT_A_OR
Port A Option Register
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ST52F510/F513/F514
Table 3.4 Configuration Registers
Mnemonic
Description
Address
PORT_A_DDR
PORT_A_AF
Port A Data Direction Register
26
27
28
29
30
31
32
33
34
35
01Ah
01Bh
01Ch
01Dh
01Eh
01Fh
020h
021h
022h
023h
Port A Alternate Function selection Register
Port B Pull Up enable/disable Register
Port B Option Register
PORT_B_PULLUP
PORT_B_OR
PORT_B_DDR
PORT_B_AF
Port B Data Direction Register
Port B Alternate Function selection Register
Port C Pull Up enable/disable Register
Port C Option Register
PORT_C_PULLUP
PORT_C_OR
PORT_C_DDR
PORT_C_AF
Port C Data Direction Register
Port C Alternate Function selection Register
024h-
02Ah
-
Not Used
36-42
SCI_CR3
SSP_H
Serial Communication Interface Control Register 3
System Stack Pointer (MSB)
43
44
45
46
47
02Bh
02Ch
02Dh
02Eh
02Fh
SSP_L
System Stack Pointer (LSB)
CPU_CLK
AD_CR2
CPU Clock Prescaler
10-bit A/D Converter Control Register 2
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4 MEMORY PROGRAMMING
Flash and EEPROM pages can be protected by
unintentional writings.
ST52F510/F513 provides an on-chip user
programmable non-volatile memory, which allows
fast and reliable storage of user data.
Program/Data Memory addressing space is
composed by a Single Voltage Flash Memory and
a RAM memory bench. The ST52F513/514
devices also have a Data EEPROM bench to store
permanent data with long term retention and a high
number of write/erase cycles.
Remark: the memory contents are protected by
the Error Correction Code (ECC) algorithm that
uses a 4-bit redundancy to correct one bit errors.
4.1 Program/Data Memory Organization
The Program/Data Memory is organized as
described in Section 3.3. The various sales types
have different amounts of each type of memory.
Table 4.1 describes the memory benches amount
and page allocation for each sales type.
The addressing spaces are organized in pages of
256 bytes. Each page is composed by blocks of 32
bytes. Memory programming is performed one
block at a time in order to speed-up the
programming time (about 2.5 ms per block).
All the Program Data memory addresses can
execute code, including RAM and EEPROM
benches.
The memory is programmed by setting the Vpp pin
equal to Vdd. Data and commands are transmitted
through the I2C serial communication protocol. The
same procedure is used to perform “In-Situ” the
programming of the device after it is mounted in
the user system. Data can also be written in run-
time with the In-Application Programming (IAP)
instructions.
The whole location address is composed as
follows:
15
8
7
5
4
0
The Memory can be locked by the user during the
programming phase, in order to prevent external
operation such as reading the program code and
assuring protection of user intellectual property.
Page address
Block address address inside the block
Table 4.1 Sales Type Memory Organization
Flash Memory
Device
RAM Memory
EEPROM Memory
Amount
Pages
0 to 15
0 to 31
0 to 14
0 to 30
0 to 15
0 to 15
Amount
Page
32
Amount
Page(s)
ST52F510c2p6
ST52F510c3p6
ST52F513c2p6
ST52F513c3p6
ST52F514c1p6
4096 bytes
8192 bytes
3840 bytes
7936 bytes
4096 bytes
4096 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
-
-
-
32
-
32
256 bytes
256 bytes
15
32
31
32
1024 bytes
4096 bytes
16-19
16-31
ST52F514c3p6
legend:
c: Y=16 pins, F=20 pins, G=28 pins, K=32/34 pin
p: B=DIP, M=SO, T=TQFP
32
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ST52F510/F513/F514
4.2 Memory Programming
4.2.1 Programming Mode start. The following
sequence starts the Programming Mode:
The Programming procedure writes the user
program and data into the Flash Memory,
EEPROM and Option Bytes. The programming
procedures are entered by setting the Vpp pin
equal to Vdd and releasing the Reset signal. The
following pins are used in Programming mode:
1.
2. The device is Reset (RESET=VSS
3. The Reset is released (RESET=VDD
VPP is set to VDD
)
)
4. The internal oscillator starts at 10 MHz
I VPP
I VDD
I VSS
used to switch to programming mode
device supply
5. The memory is turned on
6. The I2C Interface and Ports are initialized
7. The I2C Interface is configured to work as
Slave, Receiver, 7-bit address and waits for
data
device ground
I RESET device reset
I SCL
I SDA
I2C serial clock
I2C serial data
8. The Start signal is sent to the chip followed by
the Slave Address 1010000 and the direction
bit set to 0 (the addressed slave waits for da-
ta). The device sends the acknowledge
During the device programming, the internal clock
is used, so the OSCin and OSCout pins don’t have
to be considered.
9. The Programming Mode code 00000000 is
sent and acknowledged
Remark: The Option Bytes must be always
programmed, otherwise these bytes will be loaded
with
unpredictable
values,
determining
10. A command code is sent to the device
unpredictable device configuration.
11. The procedure related to the command is ex-
ecuted
Table 4.2 Programming Mode Commands
Command
Code
Data in Data out Erase
Description
Write the currently addressed block with the 32 bytes
BlockWrite
00000001
32
-
-
Yes following the command. The Block locations are erased
before being written.
Write the byte addressed by the next data sent in the
currently addressed page.
ByteWrite
BlockErase
ByteErase
00000010
00000011
00000100
2
1
1
Yes
Erase the block addressed by 3 MSB of the next data sent
and inside the currently addressed page.
Yes
Erase the byte addressed by the next data sent and inside
the currently addressed page.
Yes
Read the byte addressed by the next data sent and inside
the current page. The read data is sent by the device after
the re-send of the Slave Address with the R/W bit changed.
The current memory absolute address is post-incremented.
ByteRead
00000101
00001001
1
1
-
GlobalErase
-
-
-
-
Yes All the memory is erased.
Write the currently addressed block with the 32 bytes
following the command. The Block locations aren’t erased.
FastBlockWrite 00001011
32
1
No
SetPage
00001100
00001101
-
-
The currently addressed page is set with the next data sent.
Read the memory location currently addressed. The read
data is sent by the device after the command is
acknowledged. The current memory absolute address is
post-incremented.
ReadData
-
1
The current block address is incremented modulo 8
(address 0 follows after address 7 and the Page is post-
incremented)
IncBlock
00001111
00010011
-
-
-
-
-
This command is followed by a status data byte. Mostly
used in error condition and to check if the device is locked
ReadStatus
1
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ST52F510/F513/F514
Figure 4.1 Commands and Data Communication Sequences
Programming mode start sequence
S
10100000
A
00000000
A
Command
A
Data1
A
.....
DataN
A
P
Execution of commands for writing data:
Command
A
Data1
A
.....
DataN
A
Command
A
Data1
A
..... DataN
A
P
Execution of commands for reading data:
Command
A
Address
A
P
S
10100001
A
Data read NA P
S=Start, P=Stop, A=Acknowledge, NA=Non-acknowledge
From Slave to Master
From Master to Slave
The generic procedure of commands execution,
with the data communication in both directions is
displayed in Figure 4.1.
5. After the device acknowledges the 32nd byte,
it holds the SCL line until the parallel writing of
the 32 byte is completed (about 2.5 ms)
Remark: the Slave Address 1010000 must be sent
after a Stop (i.e. each time the data direction
changes, to specify the R/W bit). For example: if a
command to send data to the device has been
executed, a command for receiving data must be
followed by the slave address and the R/W bit must
be set to 1. The Programming Mode code doesn’t
need to be specified again .
6. The Block Pointer is incremented by sending
the IncBlock command
7. The procedure is repeated from point 3 until
there is data to be sent to the memory
Note: the Block Pointer assumes values between
0 to 7 (there are 8 blocks in a page). When the
Block Pointer is equal to 7, the IncBlock command
puts this pointer to 0 and increments the Page
Pointer. The Page Pointer, after page writing is
completed, does’t have to be incremented in the
procedure above described.
Warning: After entering the Programming Mode,
the currently pointed address is the Page 48, Block
3, byte 0 (Lock Byte).
The list of the available commands in
Programming Mode is showed in Table 4.2
4.2.3 Random data writing. A single byte can be
written in a specified memory location by using the
following procedure:
1. The Programming Mode is entered with the
sequence described in Section 4.2.1
4.2.2 Fast Programming procedure. The
fastest way to program the device memory is the
use of the FastBlockWrite command. The following
procedure can be used to write the memory with a
new program and new data, starting from the first
memory location:
2. The SetPage command is sent, followed by
the page number where the data should be
written
1. The Programming Mode is entered with the
sequence described above
3. The ByteWrite command is sent followed by
2. The memory is erased (all bits are put to 0)
with the GlobalErase command. The device
holds the SCL line low, releasing it after the
command is completed (about 2 ms). This
command also unlocks the device if locked.
two bytes
4. The first bytes that follows the ByteWrite com-
mand is the address inside the pointed page
where the data must be written.
5. The second byte is the data to be written
3. The FastBlockWrite command is sent and the
device acknowledges it
6. The device held the SCL line low until the data
is not stored in the memory (about 4.5 ms: 2
ms for erasing and 2.5 for writing)
4. The 32 bytes of data to be written in the first
memory Block are sent in a sequence. The
device acknowledges each of them
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ST52F510/F513/F514
A similar procedure can be used to write a single
block:
1. The SetPage command is sent, followed by
the page number where the data should be
written
The commands ByteErase and BlockErase, used
instead of ByteWrite and BlockWrite, erase (put all
bit to 0) the specified memory location or block.
4.2.4 Option Bytes Programming. The Option
Byte addresses cannot be accessed with a
sequential procedure like the one described in
Section 4.2.2. Actually, the pointers are
automatically incremented up to the last block or
address in page 31. A further increment sets all the
pointers to 0.
The Option Byte addresses (located at page 48,
block 0, addresses 0-7) must be accessed with a
direct addressing procedure as the one described
in Section 4.2.3.
If the Fast Programming procedure is used, it must
be followed by a Random Block Writing procedure
to program the Option Bytes. The other 24 bytes of
the block can be written with dummy or user
values. The blocks 0, 1, 2 and 3 of Page 48 can be
used for writing data as well (see Section 4.5) and
for locking the device (see Section 4.4).
2. The IncBlock command is sent as many times
as the block number inside the page (for ex-
ample: to address the block 3 the IncBlock
must be sent 3 times)
3. The BlockWrite command is sent followed by
the 32 data bytes to be written.
4. After the 32th byte is sent, the device holds
the SCL line low until all the data are not
stored in the memory (about 4.5 ms: 2 ms for
erasing and 2.5 for writing: the same time for
a single byte)
The procedures described previously can be
repeated as many time as needed, without exiting
from Programming Mode or re-sending the Slave
Address again.
Figure 4.2 Programming Procedures
Fast Programming Procedure
S
10100000
A
00000000
A
GlobalErase
A
FastBlockWrite
A
Data0
A
A
.....
..... Data31
A
IncBlock
A
FastBlockWrite
A
..... Data31
..... ..... Data31
A
P
Random Byte Writing Procedure
..... SetPage
A
Page Address
A
ByteWrite
IncBlock
A
Byte Address
A
Data
A
Command .....
Random Block Writing Procedure
..... SetPage
A
Page Address
A
A
..... IncBlock
A
BlockWrite
A
Data0
A
.....
..... Data31
A
Command .....
Option Byte Writing Procedure
..... SetPage
A
00110000
A
BlockWrite
A
Option Byte 0
A
..... Option Byte 7
A
.....
..... Dummy 0
A
..... Dummy 23
A
P
S=Start, P=Stop, A=Acknowledge, NA=Non-acknowledge
From Slave to Master From Master to Slave
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ST52F510/F513/F514
Figure 4.3 Reading and Erasing Procedures
Fast Reading Procedure
S
10100000
A
00000000
A
ReadData
A
P
S
10100001
A
Data read NA
P
.....
.....
S
10100000
A
ReadData
A
P
S
10100001
A
Data read NA
P
..... Data read NA P
Random Byte Reading Procedure
..... SetPage
A
Page Address
A
ByteRead
A
Byte Address
A
P
S
10100001
A
.....
..... Data read NA
P
S
10100000
A
Command .....
Byte Erasing Procedure
..... SetPage
A
Page Address
A
A
ByteErase
BlockErase
A
Byte Address
A
Command .....
Block Erasing Procedure
..... SetPage
A
Page Address
A
Block Address (*)
A
Command .....
(*) Block address is specified by the 3 most significative bits of the whole given address (less significative bits are don’t care)
S=Start, P=Stop, A=Acknowledge, NA=Non-acknowledge
From Slave to Master
From Master to Slave
4.3 Memory Verify
To verify the memory contents or just to read part
of data stored in memory, the ByteRead and the
ReadData command can be used. The first
instruction needs the specification of the address;
the second one allows the sequential reading of
consecutive memory locations.
Since the device is “Slave” for the I2C protocol,
after receiving a command for reading, it must be
configured as Slave Transmitter to send the data.
In order to do so, the Slave Address (1010000)
must be sent again with the R/W byte set to 1, as
stated by the communication protocol.
5. The Slave Address with the R/W byte set to 1
(10100001) is sent. The device receives the
Slave Address and acknowledges it.
6. The device sends the data to be read in the
serial data line SDA. The current absolute ad-
dress is post-incremented.
7. The Master device doesn’t send the acknowl-
edge and generates a stop condition.
8. To read the next data, the Master generates a
Start condition followed by the Slave Address
with the R/W byte set to 0 (10100000). The
device receives the Slave Address and ac-
knowledges it.
4.3.1 Fast read procedure. The memory can be
read sequentially by using the following procedure:
1. The Programming mode is entered with the
sequence described in Section 4.2.1
9. The sequence restarts from point 3 until there
is data to be read.
2. The pointers address the memory location 0
Remark: for the same reasons explained in
Section 4.2.4 the Option Bytes cannot be read with
this procedure: they can be read with a direct
addressing procedure as the one explained in the
next section.
3. The ReadData command is sent and the de-
vice acknowledges it.
4. The Master generates a Stop condition fol-
lowed by a Start condition
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ST52F510/F513/F514
4.3.2 Random data reading. To read a specified
memory location, the following procedure should
be used:
1. The Programming mode is entered with the
sequence described in Section 4.2.1
4.4 Memory Lock
The Program/Data Memory space can be locked to
inhibit the reading of contents and protect the
intellectual property.
To lock the device, the user must set all the bit of
the Lock Byte to ‘1’. The Lock Byte is located on
Page 48 (030h), Block 3, byte 0 inside the block i.e.
byte 96 (060h) inside the page.
After writing 255 (0FFh) into the Lock Byte, with the
procedure described in the Section 4.2.3, the
memory is locked and the only command allowed
are the following:
2. The SetPage command is sent, followed to
the page number where the data to be read is
located
3. The ByteRead command is sent, followed by
an address inside the page
4. The Master generates a Stop condition fol-
lowed by a Start condition
– GlobalErase: this command, writing ‘0’ in all the
memory, also unlock the device.
5. The Slave Address with the R/W byte set to 1
(10100001) is sent. The device receives the
Slave Address and acknowledges it.
– ReadData: the only block that can be read is the
Block 3 in Page 48 (030h); this allows the read-
ing of the Lock Byte and the ID Code locations
(see Section 4.5).
– ReadStatus: this command allows the detection
of an error condition in Programming mode op-
eration (see Section 4.6). It can also be used to
check if the device is locked. The most significa-
tive bit return the Lock Bit (0=unlocked,
1=locked).
6. The device sends the data to be read in the
serial data line SDA. The address pointer is
incremented.
7. The Master device doesn’t send the acknowl-
edge and generates a stop condition.
8. To send the next command, the Master
should generate a Start condition followed by
the Slave Address with the R/W byte set to 0
(10100000).
Remark: the Lock Byte is checked when entering
the Programming Mode. For this reason after
writing the Lock Byte, all the commands can be
carried out until the Programming mode is exited.
Figure 4.4 Device Lock Procedure
Device Lock Procedure
..... SetPage
A
00110000
A
ByteWrite
A
01100000
A
11111111
A
Command .....
Device Lock and ID Code Writing Procedure
..... SetPage
A
00110000
A
IncBlock
A
IncBlock
A
IncBlock
A
BlockWrite
A
.....
..... 11111111
A
ID Code 1
A
ID Code 2
A
..... ID Code 31
A
Command .....
Device Lock Reading Procedure
..... ReadStatus
A
P
S
10100001
A
Status Byte (*) NA
P
S
10100000
A
Command .....
(*) The most significative bit return the Lock Bit (0=unlocked, 1=locked)
S=Start, P=Stop, A=Acknowledge, NA=Non-acknowledge
From Slave to Master
From Master to Slave
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ST52F510/F513/F514
Figure 4.5 Error Handling Procedure
Wrong command/data case handling:
Wrong Command/Data
A
Command/Data NA
P
S
10100000
A
ReadStatus A P S .....
..... 10100001
A
Status Byte NA
P
S=Start, P=Stop, A=Acknowledge, NA=Non-acknowledge
From Slave to Master
From Master to Slave
When the device is locked, if memory reading is
attempted, with the exception of the Lock Byte and
ID Code block, the device returns no data and an
error sequence. If memory writing is attempted in
any memory location, the device doesn’t carry out
the command and returns an error sequence.
To unlock the device the GlobalErase command
must be executed before any writing or reading
command.
4.6 Error cases
If a wrong command or data is sent to the device,
it generates an error condition by not sending the
acknowledge after the first successive data or
command. Figure 4.5 shows the error sequence.
The error case can be handled by using the
ReadStatus command. This command can be sent
after the error condition is detected; the device
returns a Status Byte containing the error code.
The ReadStatus command sequence is showed in
Figure 4.5. The list of the error codes is illustrated
in Table 4.3.
4.5 ID Code
Block 3 on Page 48 (030h) can also be read if the
device is locked. The first byte of the block is the
Lock Byte, the following 21 locations (bytes 1-21)
are available to the user for writing data, as for
example identification codes to distinguish the
firmware version loaded in the device.
Remark: after the ReadStatus command
execution or after any error, the Start Sequence
must be carried out before sending a new
command.
The Most Significative Bit of the error codes
indicates (when set to ‘1’) that the memory is
locked. When a command, that is not allowed
when the memory is locked, is sent, the “Not
Allowed” code is sent. If another code is sent with
the MSB to ‘1’ it indicates that the error condition is
not caused by the memory lock, but by the event
related with the code sent.
Warning: do not perform writing on the last 8 bytes
(bytes 22 to 31), because they are reserved.
The ID Code must be written before locking the
device: after the device is locked it can only be
read. The blocks 0, 1 and 2 on Page 48 can be
also be used for writing data, but they cannot be
accessed when the device is locked.
Warning: when the data writing into a non existing
location is attempted, no error condition is
generated. The user must take care in specifying
the correct page address.
Note: the ID Code cannot be modified if the device
is locked: it can only be read.
Table 4.3 Error codes
Name
Code
Description
Device Locked
Wrong Command
Not Allowed
xyyyyyyy
x0000101
x0000110
x0010000
x=lock bit (1=device locked), yyyyyyy=error code
The Master sent a wrong command code
A command not allowed when the device is locked has been sent
A code different form the Programming mode code (00000000) has been sent
Wrong Mode
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ST52F510/F513/F514
4.7 In-Situ Programming (ISP)
The Program/Data Memory can be programmed
using the ISP mode. This mode allows the device
to be programmed when it is mounted in the user
application board.
This feature can be implemented by adding a
minimum number of components and board
impact.
The programming procedures and pins used are
identical to the ones described before for the
standard Programming Mode. All the features
previously described in this chapter are applicable
in ISP mode.
If RESET, SCL and SDA pins are used in the user
application board for other purposes, it is
recommended to provide an adequate isolation to
avoid a conflict when the other devices force the
signal level.
4.8.2 Block write. This procedure allows the
writing of 32 bytes in parallel. These bytes should
belong to the same block.
Before the writing in the Program/Data memory,
data must be buffered in the Register File in the
first 32 locations (0-31, 00h-020h) by using the
normal instructions to load the Register File
locations.
Then the data writing starts by using the BLKSET
instruction. The destination block is addressed by
specifying the memory page with the PGSET or
PGSETR instruction before to start the writing; the
block inside the page is addressed with the
argument of the BLKSET instruction.
Example:
PGSET 5
BLKSET 4
The ISP can be applied by using the standard tools
for the device programming. The ST52F510/F513
Starter Kit supplies a cable to perform the ISP. The
user application board should supply a suited
connector type for the cable (see Starter Kit User
Manual).
This instruction sequence writes the contents of
the first 32 bytes of the Register File in the
locations 1408-1439 (0580h-059Fh).
Warning: the user should be careful in specifying
the correct page and block: the addressing of an
not existing block can cause the unwanted writing
of a different block.
4.8 In-Application Programming (IAP)
As soon as the BLKSET instruction is executed,
the data writing starts and is performed in about
4.5 ms.
This procedure may also be used to write few data,
taking in account that all the 32 byte are written in
the block anyway.
The In Application Programming Mode (IAP)
allows the writing of user data in the Flash and
EEPROM memories when the user program is
running.
There are two ways to write data in IAP mode:
single byte write and Block write. Both procedures
take about 4.5 ms to complete the writing: the
Block write allows the writing of 32 byte in parallel.
4.8.3 Memory Corruption Prevention.
Remark: during data writing, the execution of the
user program is stopped until the procedure is
completed. Interrupt requests stop the writing
operation and the data may be not stored. The bit
ABRT in the IAP_SR Input register signals that the
data writing hasn’t been completed. To assure
writing completion, the user should globally disable
the interrupts (UDGI instruction) before starting
IAP data writing.
The user can protect some pages (or all the
memory) from unintentional writings. The only
constraint is that the protected pages must be
consecutive.
Two Option Bytes allow the specification of the
page to be protected: PG_LOCK (Option Byte 5)
and PG_UNLOCK (Option Byte 6). PG_LOCK is
used to specify the first protected page;
PG_UNLOCK is used to specify the first page not
protected after the protected ones. The pages
between the two addresses are protected.
When writing in a protected page is attempted, the
procedure is aborted and the bit PRTCD of
IAP_SR Input register is set.
If the PG_LOCK and PG_UNLOCK have the same
value, no page is protected.
4.8.1 Single byte write. Writing of a single byte in
the Non-Volatile Program/Data memory is
performed by using the LDER instructions (both
direct and indirect addressing). The memory page
should be indicated before the LDER instruction
with the PGSET or PGSETR instruction. The byte
address inside the page is specified by the LDER
instruction itself.
In Programming Mode the protection is not
considered and the pages can be written unless
the device is locked.
As soon as the instruction is executed, the data
writing starts and is performed in about 4.5 ms.
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ST52F510/F513/F514
4.8.4 Option Bytes.
4.8.5 Input Register.
First Protected Page (PG_LOCK)
Option Byte 5 (05h)
IAP Status Register (IAP_SR)
Input Register 40 (028h) Read only
Reset Value: 0000 0000 (00h)
7
0
7
0
LCK7
LCK6
LCK5
LCK4
LCK3
LCK2
LCK1
LCK0
-
-
-
-
-
-
PRTCD ABRT
Bit 7-2: Not Used
Bit 1: PRTCD Page Protected
Bit 7-0: LCK7-0 First Page write protected
In this register the address of first page to be
protected in writing is specified. The pages
following this one are protected up to the page
specified by the PG_UNLOCK Option Byte (not
included among the protected ones).
0: The writing has been completed
1: The writing has been aborted because the
page is protected.
Bit 0: ABRT Writing operation aborted
0: The writing has been completed
First Page not Protected (PG_UNLOCK)
Option Byte 6 (06h)
1: The writing has been aborted because an
interrupt or another unspecified cause
occurred.
7
0
The ABRT and PRTCD bits are reset after the next
successful data writing in the Flash of EEPROM
memory.
UNLCK7 UNLCK6 UNLCK5 UNLCK4 UNLCK3 UNLCK2 UNLCK1 UNLCK0
Bit 7-0: UNLCK7-0 First Page not write protected
In this register the address of first page not write
protected after the protected ones is specified. The
pages following this one aren’t protected.
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ST52F510/F513/F514
5 INTERRUPTS
Figure 5.1 Interrupt Flow
The Control Unit (CU) responds to peripheral
events and external events through its interrupt
channels.
When such events occur, if the related interrupt is
not masked and doesn’t have a priority order, the
current program execution can be suspended to
allow the CU to execute a specific response
routine.
NORMAL
PROGRAM
FLOW
INTERRUPT
SERVICE
ROUTINE
INTERRUPT
Each interrupt is associated with an interrupt
vector that contains the memory address of the
related interrupt service routine. Each vector is
located in the Program/Data Memory space at a
fixed address (see Figure 3.2 Program/Data
Memory Organization).
RETI
INSTRUCTION
5.1 Interrupt Processing
If interrupts are pending at the end of an arithmetic
or logic instruction, the interrupt with the highest
priority is acknowledged. When the interrupt is
acknowledged the flags and the current PC are
saved in the stacks and the associated Interrupt
routine is executed. The start address of this
routine (Interrupt Vector) is located in two bytes of
the Program/Data Memory, plus another byte for
the JUMP or RETI opcode, between address 3 and
32 (03h-020h). See Table 5.1 for the list of the
Interrupt Vector addresses.
The Interrupt routine is performed as a normal
code. At the end of any instruction, the CU checks
if a higher priority interrupt has sent an interrupt
request. An Interrupt request with a higher priority
stops lower priority Interrupts. The Program
Counter and the flags are stored in their own
stacks.
With the instruction RETI (Return from Interrupt)
the flags and the Program Counter (PC) are
restored from the top of the stacks. These stacks
have already been described in Paragraph 3.4.
An Interrupt request cannot stop fuzzy rule
processing. The request is acknowledged only
after the end of a fuzzy rule or at the end of a logic
or arithmetic instruction, unless a Global Interrupt
Disable instruction has been executed before.
5.2 Global Interrupt Request Enabling
When an Interrupt occurs, it generates a Global
Interrupt Pending (GIP). After a GIP a Global
Interrupt Request (GIR) will be generated and
Interrupt Service Routine associated with the
interrupt with higher priority will start.
In order to avoid possible conflicts between the
interrupt masking set in the main program, or
inside high level language compiler macros, the
GIP is put in AND through the User Global Interrupt
Mask or the Macro Global Interrupt Mask (see
Figure 5.2).
The UEGI/UDGI instruction switches the User
Global Interrupt Mask enabling/disabling the GIR
for the main program.
MEGI/MDGI instructions switch the Macro Global
Interrupt Mask on/off in order to ensure that the
macro will not be interrupted.
Figure 5.2 Global Interrupt Request
Global Interrupt
Remark: A fuzzy routine can be interrupted only in
the Main program. When a Fuzzy function is
running inside another interrupt routine an interrupt
request can cause side effects in the Control Unit.
For this reason, in order to use a Fuzzy function
inside an interrupt routine, the user MUST include
the Fuzzy function between an UDGI (MDGI)
instruction and an UEGI (MEGI) instruction (see
the following paragraphs), in order to disable the
interrupt request during the execution of the fuzzy
function.
Global Interrupt
Pending
Request
User Global
Interrupt Mask
Macro Global
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ST52F510/F513/F514
5.3 Interrupt Sources
5.4 Interrupt Maskability and Priority Levels
ST52F510/F513/F514 manages interrupt signals
generated by the internal peripherals or generated
by software by the TRAP instruction or coming
from the Port pins. There are two kinds of
interrupts coming from the Port pins: the NMI and
the Ports Interrupts.
NMI (Not Maskable Interrupt) is associated with pin
PA7 when it is configured as Alternate Function.
This interrupt source doesn’t have a configurable
level priority and cannot be masked. The fixed
priority level is lower than the software TRAP and
higher than all the other interrupts. The NMI can be
configured to be active on the rising or the falling
edge.
The Port Interrupts sources are connected with
Port A and Port B pins. The pins belonging to the
same Port are associated with the same interrupt
vector: there is one vector for Port A and one for
Port B. In order to use one port pin as interrupt, it
must be configured as an interrupt source (see I/O
Ports chapter). In this manner, up to 16 Port
Interrupt sources are available. By reading the Port
the sources that belong to the same Port can be
discriminated. The Port Interrupts can be
configured to be active on the rising or the falling
edge, by using the INT_POL register.
Interrupts can be masked by the corresponding
INT_MASK Configuration Register 0 (00h). An
interrupt is enabled when the mask bit is “1". Vice
versa, when the bit is “0”, the interrupt is masked
and the eventual requests are kept pending.
All the interrupts, with the exception of the NMI and
TRAP that have fixed level priority, have a
configurable priority level. The configuration of the
priority levels is completed by writing three
consecutive Configuration Registers: INT_PRL_L,
INT_PRL_M, INT_PRL_H, addresses from 2 to 4
(02h-04h). The 24 bits of these registers are
divided into 8 groups of three bits: each group is
associated with a priority level. The three bits of
each group are written with the code number
associated with the interrupt source. See Table 5.1
to know the codes.
Warning: The priority levels Configuration
Registers must be programmed with different
values for each 3-bit groups to avoid erroneous
operation. After the RESET the priority registers
are loaded with a default priority configuration.
Each time the priority is modified, each priority
register must be configured with consistent values.
During program execution the interrupt priority can
only be modified within the Main Program: it cannot
be changed within an interrupt service routine. In
addition the interrupts must be disabled by means
of the UDGI instruction. In order to avoid side effect
the interrupts must be disabled before the priority
register configuration.
Warning: changing the NMI or Port Interrupt
polarity an interrupt request is generated.
All the interrupt sources are filtered, in order to
avoid false interrupt requests caused by glitches.
The Trap instruction is something between a
interrupt and a call: it generated an interrupt
request at top priority level and the control is
passed to the associated interrupt routine which
vector is located in the fixed addresses 31-32. This
routine cannot be interrupted and it is serviced
even if the interrupts are globally disabled.
5.5 Interrupt RESET
When an interrupt is masked, all requests are not
acknowledged and remain pending. When the
pending interrupt is enabled it is immediately
serviced, if it has proper priority. This event may be
undesired; in order to avoid this a RINT instruction
may be inserted followed by the code number that
identifies the interrupt to reset the pending request.
The RINT instruction has no effect if the interrupt is
being serviced
Note: Similarly to the CALL instruction, after a
TRAP the flags are not stacked.
Figure 5.3 Example of Interrupt Requests
See Table 5.1 to know the codes.
INT2 INT0 INT4
INT1
INT3
PRIORITY
LEVEL
0
1
2
3
4
5
6
INT0
INT1
INT2
INT2
INT2
INT3
INT4
MAIN PROGRAM
MAIN PROGRAM
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ST52F510/F513/F514
5.6 Register Description
Interrupt Polarity Register (INT_POL)
Configuration Register 1 (01h) Read/Write
Reset Value: 0000 0000 (00h)
Interrupt Mask Register (INT_MASK)
Configuration Register 0 (00h) Read/Write
Reset Value: 0000 0000 (00h)
7
0
-
-
-
RESPOL STRPOL POLPB POLPA POLNMI
7
0
MSKPB MSKPA MSKI2C MSKSPI MSKSCI MSKT1 MSKT0 MSKAD
Bit 7-5: Not Used
Bit 4-3: See Timer 0 Registers Description
Bit 7: MSKPB Interrupt Mask Port B
0: Port B interrupt masked
Bit 2: POLPB Port B Interrupt Polarity
1: Port B interrupt enabled
0: The Port B interrupt is triggered on the
rising edge of the applied external signal.
Bit 6: MSKPA Interrupt Mask Port A
0: Port A interrupt masked
1: The Port B interrupt is triggered on the
falling edge of the applied external signal.
1: Port A interrupt enabled
Bit 1: POLPA Port A Interrupt Polarity
Bit 5: MSKI2C Interrupt Mask I2C Interface
0: I2C Interface interrupt masked
0: The Port A interrupt is triggered on the
rising edge of the applied external signal.
1: The Port A interrupt is triggered on the
falling edge of the applied external signal.
1: I2C Interface interrupt enabled
Bit 4: MSKSPI Interrupt Mask SPI
0: SPI interrupt masked
Bit 0: POLNMI Non Maskable Interrupt Polarity
0: The NMI is triggered on the rising edge of
the applied external signal.
1: SPI interrupt enabled
1: The NMI is triggered on the falling edge of
the applied external signal.
Bit 3: MSKSCI Interrupt Mask SCI
0: SCI interrupt masked
1: SCI interrupt enabled
Low Priority Register (INT_PRL_L)
Configuration Register 2 (02h) Read/Write
Reset Value: 1111 1010 (FAh)
Bit 2: MSKT1 Interrupt Mask PWM/Timer 1
0: Pwm/Timer 1 interrupt masked
1: Pwm/Timer 1 interrupt enabled
7
0
Bit 1: MSKT0 Interrupt Mask Pwm/Timer 0
0: Pwm/Timer 0 interrupt masked
1: Pwm/Timer 0 interrupt enabled
PRL23 PRL22 PRL21 PRL20 PRL19 PRL18 PRL17 PRL16
Medium Priority Register (INT_PRL_M)
Configuration Register 3 (03h) Read/Write
Reset Value: 1100 0110 (C6h)
Bit 0: MSKAD Interrupt Mask A/D Converter
0: A/D interrupt masked
1: A/D interrupt enabled
7
0
PRL15 PRL14 PRL13 PRL12 PRL11 PRL10
PRL9
PRL8
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ST52F510/F513/F514
High Priority Register (INT_PRL_H)
Configuration Register 4 (04h) Read/Write
Reset Value: 1000 1000 (088h)
PRL2-PRL0: Interrupt priority level 1 (highest)
PRL5-PRL3: Interrupt priority level 2
PRL8-PRL6: Interrupt priority level 3
PRL11-PRL9:Interrupt priority level 4
PRL14-PRL12: Interrupt priority level 5
PRL17-PRL15: Interrupt priority level 6
PRL20-PRL18: Interrupt prioritylevel 7
PRL23-PRL21: Interrupt priority level 8 (lowest)
7
0
PRL7
PRL6
PRL5
PRL4
PRL3
PRL2
PRL1
PRL0
These three register are used to configure the
priority level of each interrupt source. The 24 bits
of these registers (PRL23-PRL0) are divided into 8
groups of three bits: each group is associated with
a priority level (from level 1, the highest, to level 8,
the lowest: level 0 is fixed for the NMI that can be
interrupted only by the TRAP) . The three bits of
each group are written with the code number
associated with the interrupt source (see Table
5.1).
Example: writing the code 110 into PRL8-PRL6
bits the priority level 3 is assigned to the Port A
Interrupt.
Warning: the Priority Level configuration registers
must be always configured with consistent values.
Table 5.1 Interrupt sources paramethers
Interrupt Source
A/D Converter
PWM/Timer 0
PWM/Timer 1
SCI
Priority type
Programmable
Programmable
Programmable
Programmable
Programmable
Programmable
Programmable
Programmable
Fixed
PRL code
000
001
010
011
100
101
110
111
-
RINT code
Maskable
Yes
Vector Addresses
3-5 (03h-05h)
0
1
2
3
4
5
6
7
8
-
Yes
6-8 (06h-08h)
Yes
9-11 (09h-0Bh)
Yes
12-14 (0Ch-0Eh)
15-17 (0Fh-011h)
18-20 (012h-014h)
21-23 (015h-017h)
24-26 (018h-01Ah)
27-29 (01Bh-01Dh)
30-32 (01Eh-020h)
SPI
Yes
2
Yes
I C Interface
Port A
Port B
NMI
Yes
Yes
No
TRAP
Fixed to highest
-
No
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ST52F510/F513/F514
6 CLOCK, RESET & POWER SAVING MODES
6.1 Clock
The ST52F510/F513/F514 Clock Generator
module generates the internal clock for the internal
Control Unit, ALU and on-chip peripherals. The
Clock is designed to require a minimum of external
components.
The ST52F510/F513/F514 oscillator circuit
generates an internal clock signal with the same
period and phase as the OSCIN input pin. The
maximum frequency allowed is 20 MHz.
When the external oscillator is used, the loop gain
can be adapted to the various frequencies values
by configuring the three bits of the Option Byte 1
CLK_SET (see Register Decription, Table 6.1).
ST52F510/F513/F514 devices supply the internal
oscillator in four clock modes:
I External oscillator
I External clock
I Internal clock
When an external clock is used, it must be
connected to the pin OSCIN while OSCOUT can
be floating. In this case, Option Byte 1 bits must be
written with 0 (000).
The crystal oscillator start-up time is a function of
many variables: crystal parameters (especially
Rs), oscillator load capacitance (CL), IC
parameters, environment temperature and supply
voltage.
The device always starts in internal clock mode,
excluding any external clock source. After the
start-up phase the clock is configured according to
the user definition programmed in the Option Byte
0 (OSC_CR). The internal clock generator can
supply an internal clock signal with a fixed
frequency of 10 MHz ± 1%, without the need for
external components. In order to obtain the
maximum accuracy, the frequency can be
calibrated by configuring the related Option byte 2
(OSC_SET).
The crystal or ceramic leads and circuit
connections must be as short as possible. Typical
values for CL1, CL2 are 10pF for a 20 MHz crystal.
Figure 6.1 illustrates the possible connections.
The clock signal generates two internal clock
signals: one for the CPU and one for the
peripherals. The CPU clock frequency can be
reduced, in order to decrease current consuption,
by setting the CPU_CLK Configuration Register 46
(02Eh). The CPU clock can be reduced up to 64
times (see Register Description).
The external oscillator mode uses a quartz crystal
or a ceramic resonator connected to OSCin and
OSCout as illustrated in Figure 6.1. This figure also
illustrates the connection of an external clock.
Figure 6.1 Oscillator Connections
CRYSTAL CLOCK
EXTERNAL CLOCK
ST FIVE
ST FIVE
OSCin
OSCout
OSCin
OSCout
Cl1
10pF
Cl2
10pF
CLOCK
INPUT
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ST52F510/F513/F514
6.2 Reset
Four Reset sources are available:
I RESET pin (external source)
After this level has been reached, the internal
oscillator (10 MHZ) is started and a delay period of
4096 clock cycles is initiated, in order to allow the
oscillator to stabilize and to ensure that recovery
has taken place from the Reset state.
If the device has been configured to work with the
internal clock, the user program starts, otherwise
the Option Byte 7 (WAKEUP) is read and another
count starts before running the user program. The
duration of the count depends on the contents of
the Option Byte 7 (WAKEUP), that works as a
prescaler, according to the follwing formula:
I WATCHDOG (internal source)
I POWER ON Reset (Internal source)
I PLVD Reset (Internal source)
When a Reset event occurs, the user program
restarts from the beginning.
6.2.1 External Reset. Reset is an input pin. An
internal reset does not affect this pin. A Reset
signal originated by external sources is
recognized immediately. The RESET pin may be
used to ensure Vdd has risen to a point where the
ICU can operate correctly before the user program
is run. Reset must be set to Vdd in working mode.
Delay = 4096 × (WAKEUP + 1) × Tclk
This delay has been introduced in order to ensure
that the oscillator has become stable after its
restart.
An internal Pull up resistor guarantees that the
RESET pin is at level “1” when no HALT or Power-
On events occur. See Table 16.9 and Table 16.15
for more details.
If the Reset is generated by the PLVD or the
Watchdog, the oscillator is not turned off; for this
reason the CPU is then restarted immediately,
without the delay.
After a RESET procedure is completed, the core
reads the instruction stored in the first 3 bytes of
the Program/Data Memory, which contains a
JUMP instruction to the first instruction of the user
program. The Assembler tool automatically
generates this Jump instruction with the first
instruction address.
6.2.2 Reset Procedures. After the Reset pin is
set to Vdd or following a Power-On Reset event,
the device is not started until the external supply
voltage has reached a threshold level (typical
value Vdd=2.6 V, see electrical characteristics).
Figure 6.2 Reset Block Diagram
WATCHDOG RESET
WATCHDOG
CKMOD1:0
INTERNAL CLOCK SOURCES
INTERNAL RESET
4096 x TCLK
RESET
(WAKEUP+1) x
4096 x TCLK
EXTERNAL CLOCK
Vdd
PROGRAMMABLE LOW VOLTAGE DETECTOR RESET
PLVD
POWER-ON
RESET
TCLK = Internal Clock period (100 ns)
CKMOD1:0 = see Option Byte 0 (OSC_CR)
WAKEUP = see Option Byte 7 (WAKEUP)
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ST52F510/F513/F514
6.3 Programmable Low Voltage Detector
watchdog system is enabled, it will be skipped
without modifying the normal CPU operations.
The on-chip Programmable Low Voltage Detector
(PLVD) circuit prevents the processor from falling
into an unpredictable status if the power supply
drops below a certain level.
When Vdd drops below the detection level, the
PLVD causes an internal processor Reset that
remains active as long as Vdd remains below the
trigger level.
The PLVD resets the entire device except the
Power-on Detector and the PLVD itself.
The PLVD can be enabled/disabled at reset by
setting the Option Byte 3 (PLVD_CR) bits.
The ICU can exit Halt mode upon reception of an
NMI, a Port Interrupt or a Reset. The internal
oscillator (10 MHZ) is started and a delay period of
4.096 clock cycles is initiated, in order to allow the
oscillator to stabilize and to ensure that recovery
has taken place from the Reset state.
If the device has been configured to work with the
internal clock, the user program is started,
otherwise the Option Byte 7 (WAKEUP) is read
and another count is started before running the
user program. The count duration depends on the
contents of the Option Byte 7 (WAKEUP), that
works as prescaler, according to the follwing
formula:
When Vdd increases above the Trigger Level, the
PLVD reset is deactivated and the user program is
started from the beginning.
The detection levels are programmable by means
of the Option Byte 3 (PLVD_CR). There are three
levels for the PLVD falling voltages (2.9V, 3.4V,
3.9V) and for rising voltages (3.1V, 3.65V, 4.2V).
The hysteresis for each level are respectively 200
mV, 250 mV and 300 mV.
Delay = 4096 × (WAKEUP + 1) × Tclk
This delay has been introduced in ordet to ensure
that the oscillator has become stable after it is
restarted.
After the start up delay, by exiting with the NMI or
a Port interrupt, the CPU restarts operations by
serving the associated interrupt routine.
The PLVD circuit will only detect a drop if Vdd
voltage stays below the safe threshold for at least
5µs before activation/deactivation of the PLVD in
order to filter voltage spikes.
Note: if the Port Interrupt is masked, the ICU
doesn’t exit the Halt mode with this interrupt.
Remark: the PLVD function isn’t active when it is
in HALT mode. In that case the device is reset if the
Vdd voltage stays below the threshold of Power
On Reset.
Figure 6.3 WAIT Flow Chart
WAIT ISTRUCTION
6.4 Power Saving modes
There are two types of Power Saving modes:
WAIT and HALT mode. These conditions may be
entered by using the WAIT or HALT instructions.
OSCILLATOR
ON
PERIPHERALS CLOCK
CPU CLOCK
ON
OFF
ENAB.
6.4.1 Wait Mode. Wait mode places the ICU in a
low power consumption status by stopping the
CPU. All peripherals and the watchdog remain
active. During WAIT mode the Interrupts are
enabled. The ICU remains in Wait mode until an
Interrupt or a RESET occurs, whereupon the
Program Counter jumps to the interrupt service
routine or, if a Reset occurs, to the beginning of the
user program.
INTERRUPTS
YES
NO
RESET
NO
CPU CLOCK
ON
INTERRUPT
PROGRAM COUNTER RESET
6.4.2 Halt Mode. Halt mode is the lowest ICU
power consumption mode, which is entered by
executing the HALT instruction. The internal
oscillator is turned off, causing all internal
processing to be terminated, including the
operations of the on-chip peripherals. Halt mode
cannot be used when the watchdog is enabled. If
the HALT instruction is executed while the
CPU CLOCK
ON
JUMP TO INT. ROUTINE
NORMAL PROGRAM FLOW
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ST52F510/F513/F514
Figure 6.4 HALT Flow Chart
HALT INSTRUCTION
YES
WATCHDOG
ENABLED
NO
HALT INSTRUCTION
SKIPPED
OSCILLATOR
PERIPHERALS CLOCK
CPU CLOCK
OFF
OFF
OFF
YES
NO
YES
NO
NMI or PORT
INTERRUPT
PORT INTERRUPT
MASKED
RESET
YES
NO
OSCILLATOR
PERIPHERALS CLOCK
CPU CLOCK
ON
ON
ON
OSCILLATOR
PERIPHERALS CLOCK
CPU CLOCK
ON
ON
ON
4096 INTERNAL CLOCK
4096 INTERNAL CLOCK
CYCLES DELAY
CYCLES DELAY
INTERNAL
CLOCK ?
INTERNAL
CLOCK ?
YES
YES
NO
NO
4096 X (WAKEUP+1)
CLOCK CYCLES
DELAY
4096 X (WAKEUP+1)
CLOCK CYCLES
DELAY
RESET CPU
AND RESTART
USER PROGRAM
RESTART PROGRAM
SERVICING THE
INTERRUPT ROUTINE
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ST52F510/F513/F514
6.5 Register Description
Bit 7-2: Not Used
The following section describes the Register which
are used to configure the Clock, Reset and PLVD.
Bit 1: Must be set to 0
6.5.1 Configuration Register.
Bit 0: CKMOD Clock Mode
0: Internal Oscillator
CPU Clock Prescaler (CPU_CLK)
Configuration Register 46 (02Eh) Read/Write
Reset Value: 0000 0000 (00h)
1: External Clock or quartz
External Clock Parameters (CLK_SET)
Option Byte 1 (01h)
7
0
-
-
CPUCK5 CPUCK4 CPUCK3 CPUCK2 CPUCK1 CPUCK0
7
0
-
-
-
-
-
CKPAR2 CKPAR1 CKPAR0
Bit 7-6: Not Used
Bit 7-3: Not Used
Bit 5-0: CPUCK5-0 CPU Clock Prescaler bits
The CPU Clock frequency is divided by a
factor described in the following table
Bit 2-0: CKPAR2-0 Oscillator Gains
These three bits enable/disable the loop
gains when a external clock or quartz are
used for generating the clock. The
following table decribes the possible
configuration options. Table 6.1 illustrates
the reccomended values for the most
common frequencies used, time to start the
oscillations and the settling time to have a
duty cycle of 40%-60% (at steady state it is
50%).
CPUCK5-0
000000
000001
000010
000100
001000
010000
100000
others
CPU Clock
=f
f
CPU OSC
f
f
f
=f
/2
CPU OSC
=f
/4
/8
CPU OSC
=f
CPU OSC
CKPAR2-0
000
Enabled Gain Stages
f
f
f
f
=f
/16
/32
/64
/64
CPU OSC
No Gains (External Clock Mode)
=f
CPU OSC
001
1 gain stage enabled
not allowed
=f
CPU OSC
010
=f
CPU OSC
011
3 gain stage enabled
not allowed
100
101
6 gain stage enabled
not allowed
6.5.2 Option Bytes.
110
Clock Mode (OSC_CR)
Option Byte 0 (00h)
111
8 gain stage enabled
Warning: If an External Clock is used instead of a
quartz or ceramic resonator, it is reccomended that
no gain be enabled (CKPAR2-0=000) in order lo
lower the current consumption.
7
0
-
-
-
-
-
-
-
CKMOD
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ST52F510/F513/F514
Table 6.1 Recomended Gain Stages for the most common frequencies
Recommend
Oscillation
Settling Times for
Frequency
CKPAR2-0
1)
2)
2)
Gain Stages
Start Times
40% duty-cycle
External Clock
1 MHz
0
1
1
3
3
6
6
8
000
001
001
011
011
101
101
111
-
-
367 µs
84 µs
27 µs
10 µs
9 µs
5 µs
8 µs
7 µs
11µs
4 MHz
8 MHz
75 µs
10 MHz
12 MHz
16 MHz
20 MHz
79 µs
110 µs
352 µs
165 µs
(1) The recommended values have been chosen to have the best tradeoff beetwen start time and current
consumption. Higher gains give shorter Start times; lower gains give less current consumption.
(2) Indicative values by design at 25° Celsius, V =2.6 V. Not Tested in production.
DD
Internal Oscillator Calibration (OSC_SET)
Bit 7-2: Not Used
Option Byte 2 (02h)
Bit 1-0: PLVD1-0 PLVD detection levels
00: Lowest detection level
01: Highest detection level
10: PLVD disabled
7
0
-
-
OSPAR5 OSPAR4 OSPAR3 OSPAR2 OSPAR1 OSPAR0
11: Medium detection level
Bit 7-6: Not Used
Wake-Up Time Prescaler (WAKEUP)
Option Byte 7 (07h)
Bit 5-0: OSPAR5-0 Internal Oscillator Parameters
These bits are used in order to calibrate the
precision of the internal oscillator working
at 10 MHz. The six bits enable some
current generators with steps of 0.05 µA
corresponding to interval of frequency of
100KHz.
7
0
WK7
WK6
WK5
WK4
WK3
WK2
WK1
WK0
Warning: the maximum configuration value
allowed is 101000 (40). The value corresponding
to the 10 MHz by design is 010100 (20). Loading
values over 40 the oscillator is stopped.
Bit 7-0: WK7-0 Wake-up prescaler
This byte determinates the time delay for
the stabilization of the oscillator after an
External Reset or a POR and after the
wake-up from Halt. The time delay is
computed according to the following
formula:
PLVD Control Register (PLVD_CR)
Option Byte 3 (03h)
Delay = 4096 × (WAKEUP + 1) × Tclk
7
-
0
Warning: If the internal clock is used as clock
source the prescaler is not used.
-
-
-
-
-
PLVD1 PLVD0
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7 I/O PORTS
7.2 Input Mode
The pins configured as input can be read by
accessing the corresponding Port Input Register
by means of the LDRI instruction. The addresses
for Port A , B and C are respectively 0 (00h), 1
(01h), and 2 (02h).
When executing the LDRI instruction all the signals
connected to the input pins of the Port are read and
the logical value is copied in the specified Register
File location. If some pins are configured in output,
the port buffer contents, which are the last written
logical values in the output pins, are read.
7.1 Introduction
ST52F510/F513/F514 are characterized by
flexible individually programmable multi-functional
I/O lines. The ST52F510/F513/F514 supplies
devices with up to 3 Ports (named from A to C) with
up to 22 I/O lines.
Each pin can be used as a digital I/O or can be
connected with a peripheral (Alternate Function).
The I/O lines belonging to Port A and Port B can
also be used to generate Port Interrupts. The I/O
Port pins can be configured in the following modes:
I Input high impedance (reset state)
I Input with pull-up
7.3 Output Mode
The pins configured as output can be written by
accessing the corresponding Port Output Register
by means of the LDPR, LDPI and LDPE
instructions. The addresses for Port A , B and C
are respectively, 0 (00h), 1 (01h), and 2 (02h).
When executing the above mentioned instructions,
the Port buffer is written and the Port pin signals
are modified. If some pins are configured as input
or as interrupt, the values are ignored.
I Output with pull-up
I Output push-pull
I Output with weak pull-up
I Output open drain
I Interrupt with pull-up
I Interrupt without pull-up
These eight modes can be selected by
programming three Configuration Registers for
each Port. All the pins that belong to the same Port
can be configured separately by setting the
corresponding bits in the three registers (see
Register Description).
To avoid side effects, the Configuration Registers
are latched only when the Data Direction Register
(PORT_x_DDR) is written. For this reason this
register must be always written when modifying the
pin configuration. All the I/O digital pins are TTL
compatible and have a Schmitt Trigger. The output
buffer can supply high current sink (up to 8mA).
7.4 Interrupt Mode
The pins configured as Interrupt Mode can
generate a Port Interrupt request. Only Port A and
Port B pins can be configured in this mode.
An Interrupt vector is associated to each Port:
there are two Port Interrupts available but more
pins of the ports can act as source at the same
time.
The Configuration Registers switch the signals
deriving from interrupt pins to an OR gate that
generates the interrupt request signal. The signal
deriving from the pins can be read, allowing the
discrimination of the interrupt sources when more
than one pin can generate the interrupt signal.
The interrupt trigger can be configured either in the
rising or falling edge of the external signal by using
the INT_POL register
Note: With the aim to reduce current consumption
it is recommended that no floating pins are left; all
unused pins must be kept at fixed voltage.
Furtehrmore it is recommended that bits of IO
Configuration Registers related to not used or non
available port/pins are set as Input Pull-Up.
Figure 7.1 Digital Pin
Figure 7.2 Analog Pin
PULL UP
ENABLE
DIGITAL OUT
ENABLE
DATA
OUT
PORT A,C,D,E
PIN
PAD
DATA
IN
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ST52F510/F513/F514
7.5 Alternate Functions
The Alternate Function allows the pins to be
connected with the peripheral signals or NMI. Not
all Port pins have an Alternate Function
associated.
A Configuration Register (PORT_x_AF) for each
Port is used to switch from the Digital I/O function
or the Alternate Function.
When an on-chip peripheral is configured to use a
pin, the correct I/O mode of the related pin should
be selected by selecting one of the appropriate
modes. See the Registers description in order to
obtain the right configurations.Some peripherals,
as for example the I2C peripheral, directly drive the
pin configuration according to the current function,
overriding the user configuration.
Some pins can have two Alternate Functions: one
input function and one output function. To switch
between the two functions, the PORT_x_AF must
be configured in Alternate Function mode and the
PORT_x_DDR Configuration Register must be
switched in Input mode or in Output mode.
NMI is considered an Alternate Function. For this
reason an NMI interrupt request can’t be
generated unless the PA7 pin is configured in
Alternate Function and in one of the Input modes.
7.6 Register Description
In order to configure the Port’s pins, the three
Configuration
Registers
PORT_x_PULLUP,
PORT_x_OR and PORT_x_DDR must be
configured. The combination of these three
registers determine the pin’s configuration,
according to the scheme shown in Table 7.1.
In order to select between the digital functions or
Alternate functions PORT_x_AF register must be
configured. Each bit of the configuration registers
configures the pin of the corresponding position
(example: PORT_A_DDR bit 5 configures the pin
PA5).
Figure 7.3 Port Pin Architecture
Vdd
EN
D
CONF. REG.
CONF. REG.
E
C
O
D
E
R
SEL
PU
CONF. REG.
INT
CONF. REG.
ENABLE
REGISTER
FILE
FF
DIGITAL
PORT PIN
ALTERNATE
FUNCTION
DATA
INTERRUPT
POLARITY
TO INPUT
REGISTER
IRQ
54/137
ST52F510/F513/F514
7.6.1 Configuration Registers.
Bit 7: AFA7 Alternate Function PA7
0: Digital I/O
1: INT
Port A Pull-Up Register (PORT_A_PULLUP)
Configuration Register 24 (018h) Read/Write
Reset Value: 0000 0000 (00h)
Bit 6: AFA6 Alternate Function PA6
0: Digital I/O
7
0
1: T0OUT
PUA7
PUA6
PUA5
PUA4
PUA3
PUA2
PUA1
PUA0
Bit 5: AFA5 Alternate Function PA5
0: Digital I/O
Bit 7-0: PUA7-0 Port A pull-up (see Table 7.1)
0: Port A pin without pull-up
1: TCLK
1: Port A pin with pull-up
Bit 4: AFA4 Alternate Function PA4
0: Digital I/O
1: TSTRT
Port A Option Register (PORT_A_OR)
Configuration Register 25 (019h) Read/Write
Reset Value: 0000 0000 (00h)
Bit 3: AFA3 Alternate Function PA3
0: Digital I/O
1: RX
7
0
Bit 2: AFA2 Alternate Function PA2
0: Digital I/O
ORA7
ORA6
ORA5
ORA4
ORA3
ORA2
ORA1
ORA0
1: T1OUT
Bit 7-0: ORA7-0 Port A option (see Table 7.1)
Bit 1: AFA1 Alternate Function PA1
0: Digital I/O
1: SDA
Port A Data Direction Register (PORT_A_DDR)
Configuration Register 26 (01Ah) Read/Write
Reset Value: 0000 0000 (00h)
Bit 0: AFA0 Alternate Function PA0
0: Digital I/O
1: SCL
7
0
DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0
Table 7.1 Pin mode configuration
MODE
PU
0
OR
0
DDR
Bit 7-0: DDRA7-0 Port A direction (see Table 7.1)
0: Port A pin configured as input
Input high impedance
Input with pull-up
0
0
0
0
1
1
1
1
1: Port A pin configured as output
1
0
Interrupt without pull-up
Interrupt with pull-up
Output push-pull
0
1
Port A Alternate Fuction (PORT_A_AF)
Configuration Register 27 (01Bh) Read/Write
Reset Value: 0000 0000 (00h)
1
1
0
0
7
0
Output with pull-up
Output open drain
Output weak pull-up
1
0
AFA7
AFA6
AFA5
AFA4
AFA3
AFA2
AFA1
AFA0
0
1
1
1
55/137
ST52F510/F513/F514
Port B Pull-Up Register (PORT_B_PULLUP)
Configuration Register 28 (01Ch) Read/Write
Reset Value: 0000 0000 (00h)
Bit 7: AFB7 Alternate Function PB7
0: Digital I/O
1: AIN7
7
0
Bit 6: AFB6 Alternate Function PB6
0: Digital I/O
1: AIN6
PUB7* PUB6* PUB5** PUB4** PUB3** PUB2** PUB1
PUB0
(*) Pin not available in 16/20 pin package devices. Set to ‘1’
(**) Pin not available in 16 pin package devices. Set to ‘1’
Bit 5: AFB5 Alternate Function PB5
Bit 7-0: PUB7-0 Port B pull-up (see Table 7.1)
0: Port B pin without pull-up
0: Digital I/O
1: AIN5
1: Port B pin with pull-up
Bit 4: AFB4 Alternate Function PB4
0: Digital I/O
1: AIN4
Port B Option Register (PORT_B_OR)
Configuration Register 29 (01Dh) Read/Write
Reset Value: 0000 0000 (00h)
Bit 3: AFB3 Alternate Function PB3
7
0
0: Digital I/O
1: AIN3
ORB7* ORB6* ORB5** ORB4** ORB3** ORB2** ORB1
ORB0
(*) Pin not available in 16/20 pin package devices. Set to ‘0’
(**) Pin not available in 16 pin package devices. Set to ‘0’
Bit 2: AFB2 Alternate Function PB2
0: Digital I/O
1: AIN2
Bit 7-0: ORB7-0 Port B option (see Table 7.1)
Bit 1: AFB1 Alternate Function PB1
Port B Data Direction Register (PORT_B_DDR)
Configuration Register 30 (01Eh) Read/Write
Reset Value: 0000 0000 (00h)
0: Digital I/O
1: AIN1
Bit 0: AFB0 Alternate Function PB0
0: Digital I/O
7
0
1: AIN0 / VREF
DDRB7* DDRB6* DDRB5** DDRB4** DDRB3** DDRB2** DDRB1 DDRB0
(*) Pin not available in 16/20 pin package devices. Set to ‘0’
(**) Pin not available in 16 pin package devices. Set to ‘0’
Port C Pull-Up Register (PORT_C_PULLUP)
Configuration Register 32 (020h) Read/Write
Reset Value: 0000 0000 (00h)
Bit 7-0: DDRB7-0 Port B direction (see Table 7.1)
0: Port B pin configured as input
7
0
1: Port B pin configured as output
-
-
PUC5
PUC4
PUC3
PUC2
PUC1
PUC0
Port B Alternate Fuction (PORT_B_AF)
Configuration Register 31 (01Fh) Read/Write
Reset Value: 0000 0000 (00h)
Note: The corresponding pins are not available in
16/20 pin devices.
7
0
Bit 7-6: Not Used
AFB7
AFB6
AFB5
AFB4
AFB3
AFB2
AFB1
AFB0
Bit 5-0: PUC5-0 Port C pull-up (see Table 7.1)
0: Port C pin without pull-up
1: Port C pin with pull-up
56/137
ST52F510/F513/F514
Port C Option Register (PORT_C_OR)
Configuration Register 33 (021h) Read/Write
Reset Value: 0000 0000 (00h)
Bit 5: AFC5 Alternate Function PC5
0: Digital I/O
1: TRES
Bit 4: AFC4 Alternate Function PC4
7
0
0: Digital I/O
1: TX
-
-
ORC5
ORC4
ORC3
ORC2
ORC1
ORC0
Note: The coresponding pins are not available in
Bit 3: AFC3 Alternate Function PC3
16/20 pin devices.
0: Digital I/O
1: SS
Bit 7-6: Not Used
Bit 2: AFC2 Alternate Function PC2
0: Digital I/O
Bit 5-0: ORC5-0 Port C option (see Table 7.1)
1: MISO
Port C Data Direction Register (PORT_C_DDR)
Configuration Register 34 (022h) Read/Write
Reset Value: 0000 0000 (00h)
Bit 1: AFC1 Alternate Function PC1
0: Digital I/O
1: MOSI
7
0
Bit 0: AFC0 Alternate Function PC0
-
-
DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0
0: Digital I/O
1: SCK
Note: The coresponding pins are not available in
16/20 pin devices.
7.6.2 Input Registers.
Bit 7-6: Not Used
Port A Data Input Register (PORT_A_IN)
Input Register 0 (00h) Read only
Reset Value: XXXX XXXX
Bit 5-0: DDRC5-0 Port C direction (see Table 7.1)
0: Port C pin configured as input
1: Port C pin configured as output
7
0
Note: in order to achieve low current consuption,
the port pins must be configured as input pull-up,
even though they are not existing in the package.
For example in 20 pin devices, the pins PB6-7 and
PC0-7 must be configured in input pull-up.
PAI7
PAI6
PAI5
PAI4
PAI3
PAI2
PAI1
PAI0
Bit 7-0: PAI7-0 Port A Input data
Port C Alternate Fuction (PORT_C_AF)
Configuration Register 35 (023h) Read/Write
Reset Value: 0000 0000 (00h)
The logical level applied in the Port A pins,
configured as digital input, can be achieved by
reading this register.
7
0
Port B Data Input Register (PORT_B_IN)
Input Register 1 (01h) Read only
Reset Value: XXXX XXXX
-
-
AFC5
AFC4
AFC3
AFC2
AFC1
AFC0
Note: The coresponding pins are not available in
16/20 pin devices.
7
0
PBI7*
PBI6*
PBI5** PBI4** PBI3** PBI2**
PBI1
PBI0
Bit 7-6: Not Used
(*) Not used in 16/20 pin package devices
(**) Not used in 16 pin package devices
57/137
ST52F510/F513/F514
Bit 7-0: PBI7-0 Port B Input data
The logical values written in these register bits are
put in the Port A pins configured as digital output.
The logical level applied in the Port B pins,
configured as digital input, can be achieved by
reading this register.
Port B Data Output Register (PORT_B_OUT)
Output Register 1 (01h) Write only
Reset Value: 0000 0000 (00h)
Port C Data Input Register (PORT_C_IN)
Input Register 2 (02h) Read only
Reset Value: XXXX XXXX
7
0
PBO7* PBO6* PBO5** PBO4** PBO3** PBO2** PBO1
PBO0
7
0
(*) Not used in 16/20 pin package devices
(**) Not used in 16 pin package devices
-
-
PCI5
PCI4
PCI3
PCI2
PCI1
PCI0
Note: This register is not used in 16/20 pin devices
Bit 7-6: Not Used
Bit 7-0: PBO7-0 Port B Input data
The logical values written in these register bits are
put in the Port B pins configured as digital output.
Bit 5-0: PCI5-0 Port C Input data
Port C Data Output Register (PORT_C_OUT)
Output Register 2 (02h) Write only
Reset Value: 0000 0000 (00h)
The logical level applied in the Port C pins,
configured as digital input, can be achieved by
reading this register.
7
0
-
-
PCO5
PCO4
PCO3
PCO2
PCO1
PCO0
7.6.3 Output Registers.
Note: This register is not used in 16/20 pin devices
Bit 7-6: Not Used
Port A Data Output Register (PORT_A_OUT)
Output Register 0 (00h) Write only
Reset Value: 0000 0000 (00h)
7
0
Bit 5-0: PCO5-0 Port C Input data
PAO7
PAO6
PAO5
PAO4
PAO3
PAO2
PAO1
PAO0
The logical values written in these register bits are
put in the Port C pins configured as digital output.
Bit 7-0: PAO7-0 Port A Output data
58/137
ST52F510/F513/F514
8 FUZZY COMPUTATION (DP)
Figure 8.2 Alpha Weight Calculation
The ST52F510/F513/F514 Decision Processor
(DP) main features are:
j-th Mbf
1
I Up to 8 Inputs with 8-bit resolution;
I 1 Kbyte of Program/Data Memory available to
store more than 300 to Membership Functions
(Mbfs) for each Input;
ij
α
I Up to 128 Outputs with 8-bit resolution;
i-th INPUT VARIABLE
I Possibility of processing fuzzy rules with an
UNLIMITED number of antecedents;
I UNLIMITED number of Rules and Fuzzy Blocks.
The limits on the number of Fuzzy Rules and
Fuzzy program blocks are only related to the
Program/Data Memory size.
After loading the input values by using the LDFR
assembler instruction, the user can start the fuzzy
inference by using the FUZZY assembler
instruction. During fuzzyfication: input data is
transformed in the activation level (alpha weight) of
the Mbf’s.
8.1 Fuzzy Inference
The block diagram shown in Figure 8.1 describes
the different steps performed during a Fuzzy
algorithm. The ST52F510/F513/F514 Core allows
for the implementation of a Mamdami type fuzzy
inference with crisp consequents. Inputs for fuzzy
inference are stored in 8 dedicated Fuzzy input
registers. The LDFR instruction is used to set the
Input Fuzzy registers with values stored in the
Register File. The result of a Fuzzy inference is
stored directly in a location of the Register File.
8.3 Inference Phase
The Inference Phase manages the alpha weights
obtained during the fuzzyfication phase to compute
the truth value (ω) for each rule.
This is a calculation of the maximum (for the OR
operator) and/or minimum (for the AND operator)
performed on alpha values according to the logical
connectives of Fuzzy Rules.
Several conditions may be linked together by
linguistic connectives AND/OR, NOT operators
and brackets.
The truth value ω and the related output singleton
are used by the Defuzzyfication phase, in order
to complete the inference calculation.
8.2 Fuzzyfication Phase
In this phase the intersection (alpha weight)
between the input values and the related Mbfs (see
Figure 8.2) is performed.
Eight Fuzzy Input registers are available for Fuzzy
inferences.
Figure 8.1 Fuzzy Inference
1
2
11
1m
INFERENCE
PHASE
DEFUZZYFICATION
FUZZYFICATION
n1
N rules -1
N rules
nm
Input Values
Output Values
59/137
ST52F510/F513/F514
Figure 8.3 Fuzzyfication
8.5 Input Membership Function
The Decision Processor allows the management of
triangular Mbfs. In order to define an Mbf, three
different parameters must be stored on the
Program/Data Memory (see Figure 8.4):
IF INPUT 1 IS X1 OR INPUT 2 IS X2 THEN .......
1
α
I the vertex of the Mbf: V;
α2
I the length of the right semi-base: RVD;
I the length of the left semi-base: LVD;
X1
Input 1
X2
Input
2
OR = Max
In order to reduce the size of the memory area and
the computational effort the vertical range of the
vertex is fixed between 0 and 15 (4 bits)
By using the previous memorization method
different kinds of triangular Membership Functions
may be stored. Figure 8.5 shows some examples
of valid Mbfs that can be defined in ST52F510/
F513/F514.
IF INPUT 1 IS X1 AND INPUT 2 IS X2 THEN .......
1
α
Each Mbf is then defined storing 3 bytes in the first
Kbyte of the Program/Data Memory.
α2
The Mbf is stored by using the following instruction:
X1
Input 1
X2
Input
2
MBF n_mbf lvd v rvd
where:
n_mbf is a tag number that identifies the Mbf
8.4 Defuzzyfication
lvd, v, and rvd are the parameters that describe the
Mbf’s shape as described above.
In this phase the output crisp values are
determined by implementing the consequent part
of the rules.
Each consequent Singleton Xi is multiplied by its
weight values ωi, calculated by the Decision
processor, in order to compute the upper part of
the Defuzzyfication formula.
Figure 8.4 Mbfs Parameters
15
Each output value is obtained from the consequent
crisp values (Xi) by carrying out the following
Defuzzyfication formula:
Input Mbf
N
Xijωij
∑
0
j
V
Input Variable
RVD
---------------------
Yi =
N
LVD
ωij
∑
j
where:
i = identifies the current output variable
N = number of the active rules on the current
output
ωij = weight of the j-th singleton
Output Singleton
15
w
Xij = abscissa of the j-th singleton
The Decision Processor outputs are stored in the
RAM location i-th specified in the assembler
instruction OUT i.
0
X
Output Variable
60/137
ST52F510/F513/F514
Figure 8.5 Example of valid Mbfs
Figure 8.6 Output Membership Functions
j-th Singleton
1
ω
ij
ω
i0
ω
in
0
X
X
X
i-th OUTPUT
ij
i0
in
8.7 Fuzzy Rules
Rules can have the following structures:
if A op B op C...........then Z
if (A op B) op (C op D op E...) ...........then Z
where op is one of the possible linguistic operators
(AND/OR)
8.6 Output Singleton
The Decision Processor uses a particular kind of
membership function called Singleton for its output
variables. A Singleton doesn’t have a shape, like a
traditional Mbf, and is characterized by a single
point identified by the couple (X, w), where w is
calculated by the Inference Unit as described
earlier. Often, a Singleton is simply identified with
its Crisp Value X.
In the first case the rule operators are managed
sequentially; in the second one, the priority of the
operator is fixed by the brackets.
Each rule is codified by using an instruction set, the
inference time for a rule with 4 antecedents and 1
consequent is about 3 microseconds at 20 MHz.
The Assembler Instruction Set used to manage the
Fuzzy operations is reported in the table below.
Table 8.1 Fuzzy Instructions Set
Instruction
Description
MBF n_mbf Ivd v rvd
IS n m
Stores the Mbf n_mbf with the shape identified by the parameters Ivd, v and rvd
Fixes the alpha value of the input n with the Mbf m
Calculates the complementary alpha value of the input n with the Mbf m.
Implements the Fuzzy operation AND
ISNOT n m
FZAND
FZOR
Implements the Fuzzy operation OR
CON crisp
Multiplies the crisp value with the last ω weight
Performs Defuzzyfication and stores the currently Fuzzy output in the register
n_out
OUT n_out
FUZZY
Starts the computation of a sigle fuzzy variable
Modify the priority in the rule evaluation
(
)
61/137
ST52F510/F513/F514
Example 1:
IF Input1 IS NOT Mbf1 AND Input4 is Mbf12 OR Input3 IS Mbf8 THEN Crisp1
is codified by the following instructions:
calculates the NOT α value of Input1 with Mbf1 and stores the result in internal registers
ISNOT 1 1
FZAND
IS 4 12
FZOR
implements the operation AND between the previous and the next alpha value evaluated
fixes the α value of Input4 with Mbf12 and stores the result in internal registers
implements the operation OR between the previous and the next alpha value evaluated
fixes the α value of Input3 with Mbf8 and stores the result in internal registers
IS 3 8
CON crisp1 multiplies the result of the last Ω operation with the crisp value crisp1
Example 2, the priority of the operator is fixed by the brackets:
IF (Input3 IS Mbf1 AND Input4 IS NOT Mbf15) OR (Input1 IS Mbf6 OR Input6 IS NOT Mbf14) THEN Crisp2
(
parenthesis open to change the priority
fixes the α value of Input3 with Mbf1 and stores the result in internal registers
IS 3 1
FZAND
implements the operation AND between the previous and the next alpha value evaluated
calculates the NOT α value of Input4 with Mbf15 and stores the result in internal registers
ISNOT 4 15
)
parenthesis closed
FZOR
implements the operation OR between the previous and the next alpha value evaluated
parenthesis open to change the priority
(
fixes the α value of Input1 with Mbf6 and stores the result in internal registers
IS 1 6
FZOR
ISNOT 2 14
)
implements the operation OR between the previous and the next alpha value evaluated
calculates the NOT α value of Input6 with Mbf14 and stores the result in internal registers
parenthesis closed
CON crisp2 multiplies the result of the last Ω operation with the crisp value crisp2
At the end of the fuzzy rules related to the current Fuzzy Variable, by using the instruction OUT reg, the
specified register is written with the computed value. Afterwards, the control of the algorithm returns to the
CU. The next Fuzzy Variable evaluation must start again with a FUZZY instruction.
62/137
ST52F510/F513/F514
9 INSTRUCTION SET
operands can refer (according to the opcode) to
addresses belonging to the different addressing
spaces. Example: SUB, LDRE.
ST52F510/F513/F514 supplies 107 (98 + 9 Fuzzy)
instructions that perform computations and control
the device. Computational time required for each
instruction consists of one clock pulse for each
Cycle plus 2 clock pulses for the decoding phase.
Total computation time for each instruction is
reported in Table 9.1
The ALU of ST52F510/F513/F514 can perform
multiplication (MULT) and division (DIV).
Multiplication is performed by using 8 bit operands
storing the result in 2 registers (16 bit values), see
Figure 2.3.
I Indirect: data addresses that are required are
found in the locations specified as operands.
Both source and/or destination operands can be
addressed indirectly. The operands can refer,
(according to the opcode) to addresses
belonging to different addressing spaces.
Examples: LDRR(reg1),(reg2);
LDER mem_addr,(reg1).
I Bit Direct: operands of these instructions directly
address the bits of the specified Register File
locations. Examples: BSET, BTEST.
Division is performed between a 16 bit dividend
and an 8 bit divider, the result and the remainder
are stored in two 8-bit registers (see Figure 2.4).
9.2 Instruction Types
9.1 Addressing Modes
ST52F510/F513/F514 supplies the following
instruction types:
I Load Instructions
ST52F510/F513/F514 instructions allow the
following addressing modes:
I Inherent: this instruction type does not require
an operand because the opcode specifies all the
information necessary to carry out the
I Arithmetic and Logic Instructions
I Bitwise instructions
instruction. Examples: NOP, SCF.
I Jump Instructions
I Immediate: these instructions have an operand
as a source immediate value. Examples: LDRC,
ADDI.
I Interrupt Management Instructions
I Control Instructions
I Direct: the operands of these instructions are
The instructions are listed in Table 9.1
specified with the direct addresses. The
Table 9.1 Instruction Set
Load Instructions
Bytes Cycles
(*)
Mnemonic
BLKSET
GETPG
LDCE
Instruction
Z
-
-
-
-
-
-
-
-
-
-
-
S
-
-
-
-
-
-
-
-
-
-
-
C
-
-
-
-
-
-
-
-
-
-
-
BLKSET const
2
GETPG regx
2
3
3
3
3
3
3
3
3
3
7
8/10
7
LDCE confx,memy
LDCI confx, const
LDCNF regx, conf
LDCR confx, regy
LDER memx, regy
LDER (regx),(regy)
LDER (regx), regy
LDER memx,(regy)
LDFR fuzzyx, regy
LDCI
LDCNF
LDCR
7
8
LDER
11
12
11
12
8
LDER
LDER
LDER
LDFR
63/137
ST52F510/F513/F514
Load Instructions (continued)
LDPE
LDPE
LDPI
LDPE outx, memy
3
3
3
3
3
3
3
3
3
3
3
3
3
3
2
2
2
2
8/10
9/11
7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LDPE outx, (regy)
LDPI outx, const
LDPR outx, regy
LDRC regx, const
LDRE regx, memy
LDRE (regx), (regy)
LDRE (regx), memy
LDRE regx, (regy)
LDRI regx, inpx
LDRR regx, regy
LDRR (regx), (regy)
LDRR (regx), regy
LDRR regx, (regy)
PGSET const
LDPR
LDRC
LDRE
LDRE
LDRE
LDRE
LDRI
8
7
8/10
10/12
9/11
9/11
7
LDRR
LDRR
LDRR
LDRR
PGSET
PGSETR
POP
9
10
9
10
4
PGSETR regx
5
POP regx
7
PUSH
PUSH regx
8
Arithmetic Instructions
Mnemonic
ADD
Instruction
ADD regx, regy
ADDC regx, regy
ADDI regx, const
ADDIC regx, const
ADDO regx, regy
ADDOC regx, regy
ADDOI regx, const
ADDOICregx,const
AND regx, regy
ANDI regx,const
CP regx, regy
Bytes
Cycles
Z
I
I
I
I
I
I
I
I
I
I
I
I
I
S
-
-
-
-
I
C
I
3
3
3
3
3
3
3
3
3
3
3
3
2
9
9
ADDC
ADDI
I
8
I
ADDIC
ADDO
ADDOC
ADDOI
ADDOIC
AND
8
I
11
11
10
10
9
I
I
I
I
I
I
I
-
-
I
-
-
-
-
-
ANDI
8
CP
8
CPI
CPI regx,const
7
I
DEC
DEC regx
7
I
64/137
ST52F510/F513/F514
Arithmetic Instructions (continued)
DIV
INC
DIV regx, regy
INC regx
3
2
2
3
2
3
3
3
3
3
3
3
3
3
3
1
1
1
1
1
1
3
3
16
7
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
-
-
I
-
-
I
I
I
I
-
-
-
-
-
-
I
I
I
MIRROR
MULT
NOT
MIRROR regx
MULT regx, regy
NOT regx
7
-
-
-
-
-
-
-
-
I
11
7
OR
OR regx, regy
ORI regx, const
SUB regx, regy
SUBI regx, const
SUBIS regx, const
SUBO regx, regy
SUBOI regx, const
SUBOISregx,const
SUBOS regx, regy
SUBS regx, regy
RCF
9
ORI
8
SUB
9
SUBI
SUBIS
SUBO
SUBOI
SUBOIS
SUBOS
SUBS
RCF
8
I
8
I
11
10
10
11
9
I
I
I
I
I
I
I
I
-
I
4
-
I
RSF
RSF
4
-
-
I
RZF
RZF
4
-
-
I
SCF
SCF
4
SSF
SSF
4
-
-
-
-
SZF
SZF
4
-
-
-
XOR
XOR regx, regy
XORI regx, cons
9
XORI
8
Bitwise Instructions
Mnemonic
ASL
Instruction
ASL regx
Bytes
Cycles
Z
I
S
-
I
C
I
2
2
3
3
3
3
3
2
7
7
8
8
8
7
7
7
ASR
ASR regx
I
-
-
-
-
-
-
I
BNOT
BRES
BSET
BTEST
MTEST
RLC
BNOT regx, bit
BRES regx, bit
BSET regx, bit
BTEST regx, bit
MTEST regx,const
RLC regx
I
-
-
-
-
-
-
I
I
I
I
I
65/137
ST52F510/F513/F514
Bitwise Instructions (continued)
ROL
ROR
RRS
ROL regx
2
2
2
7
7
7
I
I
I
-
I
I
I
-
-
ROR regx
RRS regx
Jump Instructions
Mnemonic
CALL
JP
Instruction
CALL addr
JP addr
Bytes
Cycles
11
Z
-
-
-
-
-
-
-
-
-
S
-
C
-
3
3
3
3
3
3
3
3
1
6
-
-
JPC
JPC addr
JPNC addr
JPNS addr
JPNZ addr
JPS addr
JPZ addr
RET
5/6
5/6
5/6
5/6
5/6
5/6
8
-
-
JPNC
JPNS
JPNZ
JPS
-
-
-
-
-
-
-
-
JPZ
-
-
RET
-
-
Interrupt Management Instructions
Mnemonic
HALT
Instruction
HALT
Bytes
Cycles
Z
-
-
-
-
-
-
-
-
-
S
-
C
-
1
1
1
1
2
1
1
1
1
4/13
6/11
5
MEGI
MDGI
RETI
MEGI
-
-
MDGI
-
-
RETI
9
-
-
RINT
RINT INT
UDGI
6
-
-
UDGI
5
-
-
UEGI
UEGI
6/11
9
-
-
TRAP
WAITI
TRAP
-
-
WAITI
7/10
-
-
Control Instructions
Mnemonic
Instruction
Bytes
Cycles
Z
S
C
FUZZY
FUZZY
1
1
1
1
4
-
-
-
NOP
NOP
6
6
5
-
-
-
-
-
-
-
-
-
WDTRFR
WDTSLP
WDTRFR
WDTSLP
66/137
ST52F510/F513/F514
Notes:
regx, regy:
memx, memy:
confx, confy:
outx:
Register File Address
Program/Data Memory Addresses
Configuration Registers Addresses
Output Registers Addresses
Input Registers Addresses
Constant value
inpx:
const:
fuzzyx:
I
Fuzzy Input Registers
flag affected
-
flag not affected
(*) The instruction BLKSET determines the start of a 32 byte block writing in Flash or EEPROM Program/
Data Memory. During this phase (about 4 ms), the CPU is stopped to executing program instructions. The
duration of the BLKSET instruction can be identified with this time.
67/137
ST52F510/F513/F514
10 10-BIT A/D CONVERTER
10.1 Introduction
The pre-charging process starts by starting the
peripheral by setting to 1 the STR bit of the AD_CR
Configuration Register. To speed-up the
calibration procedure, the pre-charging phase can
be skipped when not necessary (for example when
consecutive single conversions are performed).
The user can disable the pre-charging by setting
the PRECH bit in the AD_CR Configuration
Register.
The A/D peripheral converts the input voltage with
a process of successive approximations using a
fixed clock frequency derived from the 10 MHz
internal oscillator, divided by a factor that depends
on the speed mode: about 1.6 MHz in Fast Mode
and 800 kHz in Slow Mode. The speed mode is
chosen by the SCK bit of the AD_CR Configuration
Register.
The conversion range is found between the analog
VSS and the A/D VREF references. The VREF can
be either internal, derived from the VDD, or external
by using the VREF pin. The external reference
voltage allows the application of more precise and
stable reference voltages. The two modes are
selected by using the REF bit of the AD_CR
Configuration Register.
ST52F510/F513/F514 A/D Converter is a 10-bit
analog to digital converter with up to 8 analog
inputs. The A/D converter offers a typical
conversion time of 10 µs in fast mode and of 20 µs
in slow mode. This period also includes the time of
the integral Sample and Hold circuitry, which
minimizes the need for external components and
allows quick sampling of the signal for the
minimum warping effect and integral conversion
error.
In addition the peripheral performs a calibration
procedure in order to get the maximum precision
allowed in the data of conversion. The calibration
procedure is performed in two phases: the pre-
charging phase and the tuning phase. The pre-
charging process can be executed, after the
peripheral start, to set-up the internal references
and to speed-up the tuning process. The tuning
process is carried-out during the channels
conversion.
Note: The user must be take in account both the
pre-charging time and some dummy conversion (at
least 20) for the tuning before starting the data
acquisition. It is recommended to repeat this
procedure at the start-up and after a long time
peripheral stop.
Remark: the voltage applied to the VREF pin must
be in the range 2.7V - VDD
.
The external reference voltage VREF is applied to
the analog pin PB0. This pin shares the alternate
functions with the first analog channel Ain0: if the
Figure 10.1 A/D Converter Structure
CONFIGURATION REGISTERS
REF
CH0
CH1
CH2
SCK
SEQ CONT RESOL INT0
INT1
POW PRECH STR
: 6
Internal
Oscillator
10 MHz
CONTROL
LOGIC
: 12
A/D
clock
Ain0
Ain1
Ain2
Ain3
Ain4
Ain5
Ain6
Ain7
SUCCESSIVE APPROXIMATION A/D CONVERTER
INPUT REGISTERS
MSB
MSB
MSB
MSB
MSB
MSB
MSB
MSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
AUTO-ZERO /
AUTO-CALIBRATION
COMPARATOR
SUCCESSIVE
APPROXIMATION
REGISTER
SAMPLE
&
HOLD
ANALOG
MUX
STATUS REGISTER
DAC
RESISTIVE
REFERENCE
LADDER
VREF
VREF
VDD
68/137
ST52F510/F513/F514
external reference mode is chosen the Ain0
channel is not used and the first channel of the
conversion sequence becomes Ain1.
The converter uses a fully differential analog input
configuration for a better noise immunity and
precision performances.
10.2 Functional Description
The conversion is monotonic, meaning that the
result never decreases if the analog input doesn’t
and never increases if the analog input doesn’t.
If input voltage is less than Vss (voltage supply
low) then the result is equal to 00h.
Up to 8 multiplexed Analog Inputs are available. A
single signal or a group of signals can be
converted sequentially by simply programming the
starting address of the last analog channel to be
converted. Single or continuous conversion modes
are available.
The A/D converter is linear and the digital result of
the conversion is provided by the following
formula:
(2n – 1) × InputVoltage
------------------------------------------------------------
Digitalresult =
ReferenceVoltage
The result of the conversion of each A/D channel is
stored in the 8-bit Input Register pairs (addresses
from 41 to 56 (029h-038h)) according to the 8-bit or
10-bit mode. The resolution of conversion (8 or 10
bit) can be chosen by programming the RESOL bit
of the AD_CR Configuration Register. In 8-bit
mode the eight most significative bits (9:2) of the
result of conversion is stored in the least
significative byte of the register pair and the most
significative is put to zero. In 10-bit mode the two
most significative bits (9:8) are stored in the most
significative byte of the register pair; the other bits
(7:0) are stored in the least significative byte.
Where Reference Voltage is Vref - Vss and n is 8 or
10 according with the conversion mode used.
The accuracy of the conversion is described in the
Electrical Characteristics Section of the device
datasheets.
The A/D converter is not affected by the WAIT
mode.
When the ICU enters HALT mode with the A/D
converter enabled, the converter is disabled until
HALT mode is exited and the start-up delay has
elapsed.
In 10-bit mode the result of the conversion must be
read in two steps: the MSB and the LSB. The
peripheral has been designed to avoid the side
effects that can occur when the register are
modified between the reading of the two bytes. In
fact the latching of the input register pair is
disabled after the reading of the first byte and it is
enabled again after the reading of the second byte.
User should pay attention to complete the two
readings to guarantee the data of the conversion to
be latched.
When the converted signal is higher than VREF, an
overflow occurs. In this case the 8/10 bits result are
all set to 1 and the A/D Overflow Register bit
(address 39 027h) corresponding to the channel is
set to 1. The bit is reset at the next conversion
having no overflow occurrence.
10.3 Operating Modes
Four main operating modes can be selected by
setting the values of the CONT and SEQ bit in the
A/D Configuration Register AD_CR.
10.3.1 One Channel Single Mode. In this mode
(CONT=0, SEQ=0), the A/D provides an EOC
signal after the end of the conversion of the
specified channel; then the A/D waits for a new
start event. The channel is identified by the bits
CH2-CH0 in the Configuration Register AD_CR,
while the bit STR is used to command the Start/
Stop.
10.3.2 Multiple Channels Single Mode. In this
mode (CONT=0, SEQ=1) the A/D provides an
EOC signal after the end of the channels sequence
conversion identified by the three AD_CR
Configuration Register bits CH2-0; then A/D waits
for a new start event.
ST52F510/F513/F514 Interrupt Unit provides one
maskable channel for the End of Conversion and
for the overflow control. It is possible to set the
interrupt source on EOC or on overflow or on both
by programming the INT0 and INT1 bits in the
AD_CR Configuration Registers.
10.3.3 One Channel Continuous Mode. In this
mode (CONT=1, SEQ=0) a continuous conversion
flow is entered by a start event on the selected
channel. At the end of each conversion, the
relative Input Register is updated with the last
conversion result, while the former value is lost.
The conversion continues until a stop command is
executed by writing a ‘0’ in the apposite AD_CR
Configuration Register bit STR.
Note: the A/D Converter interrupts are not enabled
unless the bit 0 (MSKAD) of the Configuration
Register 0 (INT_MASK) is enabled (set to 1).
A Power-Down programmable bit (POW) allows
the A/D converter to be set to a minimum
consumption idle status. A stabilization time is
required, after the Power On, before accurate
conversions can be performed.
69/137
ST52F510/F513/F514
10.3.4 Multiple Channels Continuous Mode.
Bit 3: SEQ One/Multiple Channel Mode
0: One Channel Mode
In this mode (CONT=1, SEQ=1) a continuous
conversion flow is entered by a start event on the
selected channel sequence. The CH2-0 bits
indicate the last channel of the sequence.
At the end of each conversion the relative Input
Registers are updated with the last conversion
results, while the former values are lost.
1: Multiple Channel Mode
Bit 2: POW A/D Converter Power Down/Up
0: Power down
1: Power up
The conversion continues until a stop command is
executed by writing a ‘0’ in the apposite AD_CR
Configuration Register bit STR.
Bit 1: CONT Single/Continuous Mode
0: Single Mode
1: Continuous Mode
10.4 Power Down Mode
Before enabling any A/D operation modes, set the
Power On bit (POW) of the Configuration Register
AD_CR to ‘1’ and then start the A/D Converter by
setting the STR bit. It is suggested to execute the
pre-charging after the Power on to speed-up the
auto calibration process. Clearing the Power On bit
is useful when the A/D is not used, reducing the
total chip power consumption. This state is also the
reset configuration and it is forced by hardware
when the core is in HALT state (after a HALT
instruction execution).
Bit 0: STR A/D Converter Start bit
0: A/D Converter stopped
1: A/D Converter started
A/D Converter Control Register 2 (AD_CR2)
Configuration Register 47 (02Fh) Read/Write
Reset Value: 0000 0000 (00h)
7
0
-
-
-
PRECH
REF
RESOL
INT1
INT0
10.5 A/D Converter Register Description
The following registers are related to the use of the
A/D Converter.
Bit 7-5: not used
Bit 4: PRECH Pre-charging process on/off
0: Pre-charge on (default)
1: Pre-charge off
10.5.1 A/D Converter Configuration Registers.
A/D Converter Control Register 1 (AD_CR1)
Configuration Register 8 (08h) Read/Write
Reset Value: 0000 0000 (00h)
Bit 3: REF Voltage Reference (VREF) source
0: Internal from Vdd
1: External from VREF pin
7
0
Bit 2: RESOL 8/10 bits resolution
CH2
CH1
CH0
SCK
SEQ
POW
CONT
STR
0: 10 bits
1: 8 bits
Bit 7-5: CH2-CH0 Channel Number
Bit 1: INT1 Overflow interrupt mask
0: interrupt disabled
The number specified identifies the number
of channels to be converted (Multiple
Channel mode) or the channel to be
converted (One Channel mode)
1: interrupt enabled (if MSKAD=1)
Bit 0: INT0 End of Conversion interrupt mask
0: interrupt disabled
Bit 4: SCK A/D speed mode
0: Slow mode (800 kHz)
1: Fast mode (1600 kHz)
1: interrupt enabled (if MSKAD=1)
70/137
ST52F510/F513/F514
10.5.2 Input Registers.
A/D Channel 3 data MSB (CHAN3_H)
A/D Converter Overflow Register (AD_OVF)
Input Register 39 (027h) Read only
Reset Value: 0000 0000 (00h)
Input Register 47 (02Fh) Read only
Reset Value: 0000 0000 (00h)
A/D Channel 3 data LSB (CHAN3_L)
Input Register 48 (030h) Read only
Reset Value: 0000 0000 (00h)
7
0
OVF7
OVF6
OVF5
OVF4
OVF3
OVF2
OVF1
OVF0
A/D Channel 4 data MSB (CHAN4_H)
Input Register 49 (031h) Read only
Reset Value: 0000 0000 (00h)
Bit 7-0: OVF7-OVF0 Overflow Flag
0: no overflow occurred in the last conversion
1: overflow occurred in the last conversion
A/D Channel 4 data LSB (CHAN4_L)
Input Register 50 (032h) Read only
Reset Value: 0000 0000 (00h)
A/D Converter Data Registers
The converted digital values of the analog level
applied to AIN0-7 pins, are buffered in the following
register couples:
A/D Channel 5 data MSB (CHAN5_H)
Input Register 51 (033h) Read only
Reset Value: 0000 0000 (00h)
A/D Channel 0 data MSB (CHAN0_H)
Input Register 41 (029h) Read only
Reset Value: 0000 0000 (00h)
A/D Channel 5 data LSB (CHAN5_L)
Input Register 52 (034h) Read only
Reset Value: 0000 0000 (00h)
A/D Channel 0 data LSB (CHAN0_L)
Input Register 42 (02Ah) Read only
Reset Value: 0000 0000 (00h)
A/D Channel 6 data MSB (CHAN6_H)
Input Register 53 (035h) Read only
Reset Value: 0000 0000 (00h)
A/D Channel 1 data MSB (CHAN1_H)
Input Register 43 (02Bh) Read only
Reset Value: 0000 0000 (00h)
A/D Channel 6 data LSB (CHAN6_L)
Input Register 54 (036h) Read only
Reset Value: 0000 0000 (00h)
A/D Channel 1 data LSB (CHAN1_L)
Input Register 44 (02Ch) Read only
Reset Value: 0000 0000 (00h)
A/D Channel 7 data MSB (CHAN7_H)
Input Register 55 (037h) Read only
Reset Value: 0000 0000 (00h)
A/D Channel 2 data MSB (CHAN2_H)
Input Register 45 (02Dh) Read only
Reset Value: 0000 0000 (00h)
A/D Channel 7 data LSB (CHAN7_L)
Input Register 56 (038h) Read only
Reset Value: 0000 0000 (00h)
A/D Channel 2 data LSB (CHAN2_L)
Input Register 46 (02Eh) Read only
Reset Value: 0000 0000 (00h)
71/137
ST52F510/F513/F514
11 WATCHDOG TIMER
The working frequency of WDT (PRES CLK in the
Figure 11.1) is equal to the clock master. The clock
master is divided by 500, obtaining the WDT CLK
signal that is used to fix the timeout of the WDT.
According to the WDT_CR Configuration Register
values, a WDT delay between 0.1ms and 937.5ms
can be defined when the clock master is 5 MHz. By
changing the clock master frequency the timeout
delay can be calculated according to the
configuration register values. The first 4 bits of the
WDT_CR register are used, obtaining 16 different
delays.
11.1 Functional Description
The Watchdog Timer (WDT) is used to detect the
occurrence of a software fault, usually generated
by external interference or by unforeseen logical
conditions, which causes the application program
to abandon its normal sequence. The WDT circuit
generates an ICU reset on expiry of a programmed
time period, unless the program refreshes the
WDT before the end of the programmed time
delay. Sixteen different delays can be selected by
using the WDT configuration register.
After the end of the delay programmed by the
configuration register, if the WDT is active, it starts
a reset cycle pulling the reset signal low.
Table 11.1 Watchdog Timing Range (5 MHz)
WDT timeout period (ms)
Once the WDT is activated, the application
program has to refresh the counter (by the
WDTRFR instruction) during normal operation in
order to prevent an ICU reset.
min
0.1
max
937.5
In ST52F510/F513/F514 devices it is possible to
choose between “Hardware” or “Software”
Watchdog. The Hardware WDT allows the
counting to avoid unwanted stops for external
interferences. The first mode is always enabled
unless the Option Byte 4 (WDT_EN) is written with
a special code (10101010b): only this code can
switch the WDT in “Software” Mode, the other 255
possibilities keep the “Hardware” Mode enabled.
11.2 Register Description
SW Watchdog Enable (WDT_EN)
Option Byte 4 (04h)
7
0
The WDT is started and refreshed by using the
WDTRFR instruction. When the software mode is
enabled, the WDTSLP instruction stops the WDT
avoiding timeout resets.
WDTEN7 WDTEN6 WDTEN5 WDTEN4 WDTEN3 WDTEN2 WDTEN1 WDTEN0
When the WDT is in Hardware Mode, neither the
WDTSLP instruction nor external interference can
stop the counting. The “Hardware” WDT is always
enabled after a Reset.
Bit 7-0: WDTEN7-0 SW Watchdog Enable byte
Writing the code 10101010 in this byte the
Software Watchdog mode is enabled.
Figure 11.1 Watchdog Block Diagram
Configuration Register
D3 D2 D1 D0
WDT
WDTRFR
RESET
WTD CLK
RESET
RESET
PRESCALER
GENERATOR
PRES CLK = CLK MASTER
WDTSLP
72/137
ST52F510/F513/F514
Watchdog Control Register (WDT_CR)
Configuration Register 7 (07h) Read/Write
Reset Value: 0000 0001 (01h)
Bit 3-0: D3-0 Watchdog Clock divisor factor bits
The Watchdog Clock (WDT CLK) is divided
by the numeric factor determined by these
bits, according with Table 11.2 and the
following formula:
7
0
5 × 105 × DivisionFactor
-
-
-
-
D3
D2
D1
D0
----------------------------------------------------------------
Timeout(ms) =
Clock(MHz)
Bit 7-4: Not Used
Table 11.2 Watchdog Timeout configuration examples
Timeout Values (ms)
WDT_CR(3:0)
Division Factor
5 MHz
10 MHz
20MHz
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
1
0.1
0.05
0.025
625
62.5
125
31.25
62.5
15.625
31.25
1250
1875
2500
3125
3750
4375
5000
5625
6250
6875
7500
8125
8750
9375
187.5
250
93.75
125
46.875
62.5
312.5
375
156.25
187.5
218.75
250
78.125
93.75
437.5
500
109.375
125
562.5
625
281.25
312.5
343.75
375
140.625
156.25
171.875
187.5
687.5
750
812.5
875
406.25
437.5
468.75
203.125
218.75
234.375
937.5
73/137
ST52F510/F513/F514
12 PWM/TIMERS
12.1 Introduction
ST52F510/513/514 offers two on-chip PWM/Timer
peripherals. All ST52F510/513/514 PWM/Timers
have the same internal structure. The timer
consists of a 16-bit counter with a 16-bit
programmable Prescaler, giving a maximum count
of 232 (see Figure 12.1).
Each timer has two different working modes, which
can be selected by setting the correspondent bit
TxMOD of the PWMx_CR1 Conf. Register: Timer
Mode and PWM (Pulse Width Modulation) Mode.
All the Timers have Autoreload Functions; in PWM
Mode the reload value can be set by the user.
Warning: Both of the PWMx_COUNT_IN_x
registers must be always read. To avoid side
effects, the values stored inside these registers are
frozen, and new updates cannot be stored, until
both the values are read.
The peripheral status can also be read from the
Input Registers PWMx_STATUS. These registers
report START/STOP, SET/RESET status, TxOUT
signal and the counter overflow flag. This last
signal is set after the first EOC and it is reset by a
Timer RESET (internal or external).
12.2 Timer Mode
Timer Mode is selected writing 0 in the TxMOD bit.
Each Timer requires three signals: Timer Clock
(TMRCLKx), Timer Reset (TxRES) and Timer Start
(TxSTRT) (see Figure 12.1). Each of these signals
can be generated internally, and/or externally only
for Timer 0, by using TRES, TSTRT and TCLK
pins.
The Prescaler output (PRESCOUT) increments
the Counter value on the rising edge. PRESCOUT
is obtained from the internal clock signal (CLKM)
or, only for TIMER0, from the external signal
provided on the apposite pin.
Each timer output is available on the apposite
external pins configured in Alternate Function and
in one of the Output modes.
PWM/Timer 0 can also use external START/STOP
signals in order to perform Input capture and
Output compare, external RESET signal, and
external CLOCK to count external events: TSTRT,
TRES and TCLK pins. In addition, the START/
STOP and RESET signals have configurable
polarity (falling or rising edge).
Remark: To use TRES, TSTRT, TCLK external
signals the related pins must be configured in
Alternate Function and in one of Input modes.
Note: The external clock signal applied on the
TCLK pin must have a frequency that is at least two
times smaller than the internal master clock.
For each timer, the contents of the 16-bit counter
are incremented on the Rising Edge of the 16-bit
prescaler output (PRESCOUT) and they can be
read at any instant of the counting phase by
The prescaler output period can be selected by
setting the TxPRESC bits with one of the 17
division factors available. TMRCLK frequency is
divided by a factor equal to the power of two of the
prescaler values (up to 216).
TxRES resets the content of the 16-bit counter to
zero. It is generated by writing 0 in the TxRES bit
of the PWMx_CR1 Configuration Register and/or it
can be driven by the TRES pin if configured (only
Timer0).
accessing
the
Input
Registers
PWMx_COUNT_IN_x; the value is stored in two 8-
bit registers (MSB and LSB) for each PWM/Timer.
The Input Registers couple PWMx_CAPTURE_x
store the counter value after the last Stop signal
(only Timer Mode). The counter value is not stored
after a Reset Signal.
Figure 12.1 PWM/Timer Counter block diagram
16-BIT PRESCALER
BIT 5
TMRCLKx
BIT 14
BIT 15
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
PRESCx
17 - 1 MULTIPLEXER
PRESCOUT
TxRES
16-BIT COUNTER
BIT 3 BIT 4 BIT 5
BIT 0
BIT 1
BIT 2
BIT 14
BIT 15
TxSTRT
74/137
ST52F510/F513/F514
Figure 12.2 Timer 0 External Start/Stop Mode
start
start
stop
Level
stop
start
start
Edge
Reset
Clock
Counted
Value
2
0
1
3
4
4
0
1
TxSTRT signal starts/stops the Timer from
counting only if the peripherals are configured in
Timer mode. The Timers are started by writing 1 in
the TXSTRT bit of the PWMx_CR1 and are
stopped by writing 0. This signal can be generated
internally and/or externally by forcing the TSTRT
pin (only TIMER0).
TIMER 0 START/STOP can be given externally on
the TSTRT pin. In this case, the T0STRT signal
allows the user to work in two different configurable
modes (see Figure 12.2):
I LEVEL (Time Counter): If the T0STRT signal is
high, the Timer starts counting. When the
T0STRT is low the timer stops counting and the
16-bit current value is stored in the
Note: the contents of these registers upgrades the
Timer counter after it stops counting. Since the
register couple is written in two steps this can
cause side effects. In order to avoid this, the user
should write the MSB before writing the LSB:
actually, the 16-bit value is latched in parallel when
the LSB is written. By writing only the LSB (and
MSB equal to 0), the PWM/Timer is used as an 8
bit counter.
Warning: in Timer Mode the Reload Register
couple PWMx_RELOAD_x (see PWM mode) must
be set to the higher value FFFFh (65535)
otherwise it can affect the count duration.
There can be two types of TxOUT waveforms:
I type 1: TxOUT waveform equal to a square
wave with a 50% duty-cycle
PWM0_COUNT_IN_x Input Registers couple.
I EDGE (Period Counter): After reset, on the first
T0STRT rising edge, TIMER 0 starts counting
and at the next rising edge it stops. In this
manner the period of an external signal may be
measured.
I type 2: TxOUT waveform equal to a pulse signal
with the pulse duration equal to the Prescaler
output signal.
The same above mentioned modes, can be used
to reset the Timer0 by using the TRES pin signal.
Figure 12.3 TxOUT Signal Types
The polarity of the T0SRTR Start/Stop signal can
be changed by setting the STRPOL and RESPOL
bits in the INT_POL Configuration Register (01h bit
3 and 4). When these bits are set, the PWM/Timer
0 is Started/Set on the low level or in the falling
edge of the signal applied in the pins.
Prescout*Counter
Timer Output
Type 1
The Timer output signal, TxOUT, is a signal with a
frequency equal to the one of the 16 bit-Prescaler
output signal, PRESCOUTx, divided by a 16-bit
counter set by writing the Output Register couple
PWMx_COUNT_OUT_x.
Type 2
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Figure 12.4 PWM Mode with Reload
65535
Reload
Value
Counter
Value
0
t
PWM
Output
Ton
t
T
12.3 PWM Mode
Ton
--------
T
PWMxCOUNT
The PWM working mode for each timer is obtained
by setting the TxMOD bit of the Configuration
Register PWMx_CR1.
-----------------------------------------
=
dcycle
=
PWMxRELOAD
Note: the PWM_x_COUNT value must be lower
than or equal to the PWM_X_RELOAD value.
When it is equal, the TxOUT signal is always at
high level. If the Output Register PWM_x_COUNT
is 0, TxOUT signal is always at a low level.
The TxOUT signal in PWM Mode consists of a
signal with a fixed period, whose duty cycle can be
modified by the user.
The TxOUT period is fixed by setting the 16-bit
Prescaler bits (TxPRESC) in the PWMx_CR2 and
the 16-bit Reload value by writing the relative
Output Registers couple PWMx_RELOAD_x. The
16-bit Prescaler divides the master clock CLKM by
powers of two, determining the maximum length
period.
Reload determines the maximum value that the
counter can count before starting a new period.
The use of the two 16-bit values allows the TxOUT
period to be set with more precision when needed.
By decreasing the Reload value the counting
resolution decreases. In order to obtain the
maximum resolution, Reload value should be set
to 0FFFFh and the period corresponds to the one
established by the Prescaler value.
The value set in the 16-bit counter by writing the
Counter Output Registers couple, determines the
duty-cycle: when count reaches the Counter value
the TxOUT signal changes from high to low level.
The period of the PWM signal is obtained by using
the following formula:
T=PWMx-RELOAD * 2TxPRESC *TMRCLKx
where TxPRESC equals the value set in the
TxPRESC bits of the PWMx_CR2 Configuration
Register and TMRCLKx is the period of the Timer
clock that drives the Prescaler.
The duty cycle of the PWM signal is obtained by
the following formula:
By using a 20 MHz clock a PWM frequency that is
close to 305 Khz can be obtained with a reload
equal to FFFFh and the Prescaler set to 0000h.
The TIMER0 clock CLKM can also be supplied
with an external signal, applied on the TCLK pin,
which must have a frequency that is at least two
times smaller than the internal master clock.
Note: The Timers have to complete the previous
counting phase before using a new value of the
Counter. If the Counter value is changed during
counting, the new values of the timer Counter are
only used at the end of the previous counting
phase. The Counter buffer is written in two steps
(one byte per time) and is latched only after the
LSB is written. In order to avoid side effects, the
user should write the MSB before writing the LSB.
By only writing the LSB, the PWM/Timer is used as
an 8 bit counter. The same mechanism is applied
to the two bytes of Reload but, differently of the
Counter it is set immediately. Nevertheless, it is
recommended that the Reload value be written
when the Timer is stopped in order to avoid
incongruence with the Counter value. The same
recommendation is made when reading the two
bytes of the counter: It is performed in two steps,
so if the timer is running, the carry of the LSB to the
MSB can cause the wrong 16-bit value reading. A
Reload value greater than 1 must always be used.
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When the Timers are in Reset status, or when the
device is reset, the TxOUT pins goes in threestate.
If these outputs are used to drive external devices,
it is recommended that the related pins be left in
the default configuration (Input threestate) or
change them in this configuration.
12.5 PWM/Timer 0 Register Description
The following registers are related to the use of the
PWM/Timer 0.
12.5.1 PWM/Timer 0 Configuration Registers.
In PWM mode the PWM/Timers can only be Set or
Reset: Start/Stop signals do not affect the Timers.
TxRES resets the content of the 16-bit counter to
zero. It is generated by writing 0 in the
corresponding TxRES bit of the PWMx_CR1
Configuration Register and/or it can be driven by
the TRES pin if it is configured (only Timer0).
PWM/Timer 0 Control Register 1 (PWM0_CR1)
Configuration Register 9 (09h) Read/Write
Reset Value: 0000 0000 (00h)
7
0
T0MOD T0IES
T0IEF
T0IER STRMOD T0STRT RESMOD T0RES
12.3.1 Simultaneous Start.
The PWM/Timers can be started simultaneously.
Bit 7: T0MOD PWM/Timer 0 Mode
0: Timer Mode
The T0SYNC and T1SYNC bits in PWM0_CR3
Configuration Registers mask the reset of each
timer. After enabling each single PWM/Timer, they
are started by putting off the mask with a single
writing in the PWM0_CR3 Register.
The timers start counting simultaneously, but the
output pulses are generated according to the
modality configured (square or pulse mode).
1: PWM Mode
Bit 6: T0IES Interrupt on Stop signal Enable
0: interrupt disabled
1: interrupt enabled
12.4 Timer Interrupts
Bit 5: T0IEF Interrupt on T0OUT falling Enable
0: interrupt disabled
The PWM/Timer can be programmed to generate
an Interrupt Request, both on the falling and the
rising of the TxOUT signal and when there’s a
STOP signal (external or internal).
By using the TxIES, TxIER and TxIEF bits of the
Configuration Registers PWMx_CR1, the interrupt
sources can be switched on/off. All the interrupt
sources may be activated at the same time:
sources can be distinguished by reading the
PWMx_STATUS Input Register.
1: interrupt enabled
Bit 4: T0IER Interrupt on T0OUT rising Enable
0: interrupt disabled
1: interrupt enabled
Bit 3: STRMOD Start signal mode
0: start/stop on level
The interrupt on the falling edge corresponds to
half of a counting period in Timer mode when the
waveform is set to Square Wave and to the end of
the Ton phase in PWM mode.
1: start/stop on edge
Bit 2: T0STRT PWM/Timer 0 Start bit
0: Timer 0 stopped
Note: when the PWM Counter is set to 0 or 65535,
the interrupt occurs at the end of each control
period.
1: Timer 0 started
In order to be active, the PWM/Timers interrupts
must be enabled by writing the Interrupt Mask
Register (INT_MASK) in the Configuration
Register Space, bits MSKT0 And MSKT1.
Bit 1: RESMOD Reset signal mode
0: set/reset on level
1: set/reset on edge
Bit 0: T0RES PWM/Timer 0 Reset bit
0: PWM/Timer 0 reset
1: PWM/Timer 0 set
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PWM/Timer 0 Control Register 2 (PWM0_CR2)
Configuration Register 10 (0Ah) Read/Write
Reset Value: 0000 0000 (00h)
Bit 1-0: RESSRC PWM/Timer 0 Reset source
00: Internal from T0RES bit
01: External from TRES pin
10: Both internal and external
7
4
0
-
-
T0WAV
T0PRESC
Interrupt Polarity Register (INT_POL)
Configuration Register 1 (01h) Read/Write
Reset Value: 0000 0000 (00h)
Bit 7-6: Not Used
7
0
Bit 5: T0WAV T0OUT Waveform
0: pulse (type2)
-
-
-
RESPOL STRPOL POLPB POLPA POLNMI
1: square (type1)
Bit 7-5: Not Used
Bit 4-0: T0PRESC PWM/Timer 0 Prescaler
The PWM/Timer 0 clock is divided by a
factor equal to 2T0PRESC. The maximum
value allowed for T0PRESC is 10000
(010h).
Bit 4: RESPOL Reset signal polarity
0: Set/Reset on low level/rising edge
1: Set/Reset on high level/falling edge
Bit 3: STRPOL Start signal polarity
0: Start on high level/rising edge
1: Start on low level/falling edge
PWM/Timer 0 Control Register 3 (PWM0_CR3)
Configuration Register 11 (0Bh) Read/Write
Reset Value: 0000 0000 (00h)
Bit 2-0: See Interrupt Registers Description
7
4
2
0
T1SYNC
-
T0SYNC T0CKS
STRSRC
RESSRC
Bit 7: T1SYNC PWM/Timer 1 Set/Reset mask
0: Set/Reset activated
12.5.2 PWM/Timer 0 Input Registers.
1: Set/Reset masked
PWM/Timer 0 Counter High Input Register
(PWM0_COUNT_IN_H)
Input Register 21 (015h) Read only
Reset Value: 0000 0000 (00h)
Bit 6: not used
Bit 5: T0SYNC PWM/Timer 0 Set/Reset mask
0: Set/Reset activated
7
0
1: Set/Reset masked
T0CI15 T0CI14 T0CI13 T0CI12 T0CI11 T0CI10 T0CI9
T0CI8
Bit 4: T0CKS PWM/Timer 0 Clock Source
0: Internal clock
Bit 7-0: T0CI15-8 PWM/Timer 0 Counter MSB
1: External Clock from TCLK
In this register the current value of the Timer 0
Counter MSB can be read.
Bit 3-2: STRSRC PWM/Timer 0 Start signal source
00: Internal from T0STRT bit
Warning: Both of the PWMx_COUNT_IN_x
registers must be always read. To avoid side
effects, the values stored inside these registers are
frozen, and new updates cannot be stored, until
both the values are read.
01: External from TSTRT pin
10: Both internal and external
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PWM/Timer 0 Counter Low Input Register
(PWM0_COUNT_IN_L)
PWM/Timer 0 Capture High Input Register
(PWM0_CAPTURE_H)
Input Register 22 (016h) Read only
Reset Value: 0000 0000 (00h)
Input Register 24 (018h) Read only
Reset Value: 0000 0000 (00h)
7
0
7
0
T0CI7
T0CI6
T0CI5
T0CI4
T0CI3
T0CI2
T0CI1
T0CI0
T0CP15 T0CP14 T0CP13 T0CP12 T0CP11 T0CP10 T0CP9 T0CP8
Bit 7-0: T0CP15-8 PWM/Timer 0 Capture MSB
Bit 7-0: T0CI7-0 PWM/Timer 0 Counter LSB
In this register the counter value after the last stop
can be read.
In this register the current value of the Timer 0
Counter LSB can be read.
Warning: Both of the PWMx_COUNT_IN_x
registers must be always read. To avoid side
effects, the values stored inside these registers are
frozen, and new updates cannot be stored, until
both the values are read.
PWM/Timer 0 Capture Low Input Register
(PWM0_CAPTURE_L)
Input Register 25 (019h) Read only
Reset Value: 0000 0000 (00h)
7
0
PWM/Timer 0 Status Register (PWM0_STATUS)
Input Register 23 (017h) Read only
Reset Value: 0000 0000 (00h)
T0CP7 T0CP6 T0CP5 T0CP4 T0CP3 T0CP2 T0CP1 T0CP0
Bit 7-0: T0CP7-0 PWM/Timer 0 Capture LSB
7
0
In this register the counter value after the last stop
can be read.
-
-
-
-
T0OVFL T0OUT T0RST T0SST
Bit 7-4: Not Used
Bit 3: T0OVFL PWM/Timer 0 counter overflow flag
0: no overflow occurred since last reset
1: overflow occurred
12.5.3 PWM/Timer 0 Output Registers.
PWM/Timer 0 Counter High Output Register
(PWM0_COUNT_OUT_H)
Bit 2: T0OUT T0OUT pin value
0: T0OUT pin is at logical level 0
1: T0OUT pin is at logical level 1
Output Register 7 (07h) Write only
Reset Value: 0000 0000 (00h)
7
0
Bit 1: T0RST Reset Status
0: PWM/Timer 0 is reset
1: PWM/Timer 0 is set
T0CO15 T0CO14 T0CO13 T0CO12 T0CO11 T0CO10 T0CO9 T0CO8
Bit 7-0: T0CO15-8 PWM/Timer 0 Counter MSB
This register is used to write the Timer 0 Counter
value (MSB).
Bit 0: T0SST Start Status
0: PWM/Timer 0 is stopped
1: PWM/Timer 0 is running
Note: this register is latched after writing the LSB
part (PWM_COUNT_OUT_L: see below). For this
reason this register must be written before the
LSB.
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PWM/Timer 0 Counter Low Output Register
(PWM0_COUNT_OUT_L)
Output Register 8 (08h) Write only
Reset Value: 0000 0000 (00h)
Note:
by
writing
this
register,
the
PWM0_RELOAD_x couple is latched in the
internal registers of the peripherals. For this reason
this register should be written after the MSB one.
7
0
12.6 PWM/Timer 1 Register Description
T0CO7 T0CO6 T0CO5 T0CO4 T0CO3 T0CO2 T0CO1 T0CO0
The following registers are related to the use of the
PWM/Timer 1.
Bit 7-0: T0CO7-0 PWM/Timer 0 Counter LSB
12.6.1 PWM/Timer 1 Configuration Registers.
This register is used to write the Timer 0 Counter
value (LSB).
PWM/Timer 1 Control Register 1 (PWM1_CR1)
Configuration Register 12 (0Ch) Read/Write
Reset Value: 0000 0000 (00h)
Note:
writing
this
register,
the
PWM0_COUNT_OUT_x couple is latched in the
internal registers of the peripherals. For this
reason, this register should be written after the
MSB one.
7
0
T1MOD T1IES
T1IEF
T1IER
-
T1STRT
-
T1RES
PWM/Timer 0 Reload High Output Register
(PWM0_RELOAD_H)
Output Register 9 (09h) Write only
Reset Value: 1111 1111 (0FFh)
Bit 7: T1MOD PWM/Timer 1 Mode
0: Timer Mode
7
0
1: PWM Mode
T0REL15 T0REL14 T0REL13 T0REL12 T0REL11 T0REL10 T0REL9 T0REL8
Bit 6: T1IES Interrupt on Stop signal Enable
0: interrupt disabled
1: interrupt enabled
Bit 7-0: T0REL15-8 PWM/Timer 0 Reload MSB
Bit 5: T1IEF Interrupt on T1OUT falling Enable
0: interrupt disabled
This register is used to write the Timer 0 Reload
value (MSB).
1: interrupt enabled
Note: this register is latched after writing the LSB
part (PWM0_RELOAD_L: see below). For this
reason, this register must be written before the
LSB.
Bit 4: T1IER Interrupt on T1OUT rising Enable
0: interrupt disabled
1: interrupt enabled
PWM/Timer 0 Reload Low Output Register
(PWM0_RELOAD_L)
Bit 3: not used: it must be left at reset status
Output Register 10 (0Ah) Write only
Reset Value: 1111 1111 (0FFh)
Bit 2: T1STRT PWM/Timer 1 Start bit
0: Timer 1 stopped
7
0
1: Timer 1 started
T0REL7 T0REL6 T0REL5 T0REL4 T0REL3 T0REL2 T0REL1 T0REL0
Bit 1: not used: it must be left at reset status
Bit 7-0: T0REL7-0 PWM/Timer 0 Reload LSB
Bit 0: T1RES PWM/Timer 1 Reset bit
0: PWM/Timer 1 reset
This register is used to write the Timer 0 Reload
value (LSB).
1: PWM/Timer 1 set
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PWM/Timer 1 Control Register 2 (PWM1_CR2)
Configuration Register 13 (0Dh) Read/Write
Reset Value: 0000 0000 (00h)
Bit 7-0: T1CI7-0 PWM/Timer 1 Counter LSB
In this register the current value of the Timer 1
Counter LSB can be read.
Warning: Both of the PWMx_COUNT_IN_x
registers must be always read. To avoid side
effects, the values stored inside these registers are
frozen, and new updates cannot be stored, until
both the values are read.
7
5
0
-
-
T1WAV
T1PRESC
Bit 7-6: Not Used
PWM/Timer 1 Status Register (PWM1_STATUS)
Input Register 28 (01Ch) Read only
Reset Value: 0000 0000 (00h)
Bit 5: T1WAV T1OUT Waveform
0: pulse (type2)
1: square (type1)
7
0
-
-
-
-
T1OVFL T1OUT T1RST T1SST
Bit 4-0: T1PRESC PWM/Timer 1 Prescaler
The PWM/Timer 1 clock is divided by a
factor equal to 2T1PRESC. The maximum
value allowed for T1PRESC is 10000
(010h).
Bit 7-4: Not Used
Bit 3: T1OVFL PWM/Timer 1 counter overflow flag
0: no overflow occurred since last reset
1: overflow occurred
12.6.2 PWM/Timer 1 Input Registers.
Bit 2: T1OUT T1OUT pin value
0: T1OUT pin is at logical level 0
1: T1OUT pin is at logical level 1
PWM/Timer 1 Counter High Input Register
(PWM1_COUNT_IN_H)
Input Register 26 (01Ah) Read only
Reset Value: 0000 0000 (00h)
Bit 1: T1RST Reset Status
0: PWM/Timer 1 is reset
1: PWM/Timer 1 is set
7
0
T1CI15 T1CI14 T1CI13 T1CI12 T1CI11 T1CI10 T1CI9
T1CI8
Bit 0: T1SST Start Status
0: PWM/Timer 1 is stopped
1: PWM/Timer 1 is running
Bit 7-0: T1CI15-8 PWM/Timer 1 Counter MSB
In this register the current value of the Timer 1
Counter MSB can be read.
Warning: Both of the PWMx_COUNT_IN_x
registers must be always read. To avoid side
effects, the values stored inside these registers are
frozen, and new updates cannot be stored, until
both the values are read.
PWM/Timer 1 Capture High Input Register
(PWM1_CAPTURE_H)
Input Register 29 (01Dh) Read only
Reset Value: 0000 0000 (00h)
7
0
PWM/Timer 1 Counter Low Input Register
(PWM1_COUNT_IN_L)
T1CP15 T1CP14 T1CP13 T1CP12 T1CP11 T1CP10 T1CP9 T1CP8
Input Register 27 (01Bh) Read only
Reset Value: 0000 0000 (00h)
Bit 7-0: T1CP15-8 PWM/Timer 1 Capture MSB
7
0
In this register the counter value after the last stop
can be read.
T1CI7
T1CI6
T1CI5
T1CI4
T1CI3
T1CI2
T1CI1
T1CI0
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PWM/Timer 1 Capture Low Input Register
(PWM1_CAPTURE_L)
Input Register 30 (01Eh) Read only
Reset Value: 0000 0000 (00h)
Note:
by
writing
this
register,
the
PWM1_COUNT_OUT_x couple is latched in the
internal registers of the peripherals. For this reason
this register should be written after the MSB one.
7
0
PWM/Timer 1 Reload High Output Register
(PWM1_RELOAD_H)
T1CP7 T1CP6 T1CP5 T1CP4 T1CP3 T1CP2 T1CP1 T1CP0
Output Register 13 (0Dh) Write only
Reset Value: 1111 1111 (0FFh)
Bit 7-0: T1CP7-0 PWM/Timer 1 Capture LSB
7
0
In this register the counter value after the last stop
can be read.
T1REL15 T1REL14 T1REL13 T1REL12 T1REL11 T1REL10 T1REL9 T1REL8
Bit 7-0: T1REL15-8 PWM/Timer 1 Reload MSB
12.6.3 PWM/Timer 1 Output Registers.
This register is used to write the Timer 1 Reload
value (MSB).
PWM/Timer 1 Counter High Output Register
(PWM1_COUNT_OUT_H)
Output Register 11 (0Bh) Write only
Reset Value: 0000 0000 (00h)
Note: this register is latched after writing the LSB
part (PWM1_RELOAD_L: see below). For this
reason, this register must be written before the
LSB.
7
0
T1CO15 T1CO14 T1CO13 T1CO12 T1CO11 T1CO10 T1CO9 T1CO8
PWM/Timer 1 Reload Low Output Register
(PWM0_RELOAD_L)
Output Register 14 (0Eh) Write only
Reset Value: 1111 1111 (0FFh)
Bit 7-0: T1CO15-8 PWM/Timer 1 Counter MSB
This register is used to write the Timer 1 Counter
value (MSB).
7
0
T1REL7 T1REL6 T1REL5 T1REL4 T1REL3 T1REL2 T1REL1 T01REL0
Note: this register is latched after writing the LSB
part (PWM1_COUNT_OUT_L: see below). For this
reason, this register must be written before the
LSB.
Bit 7-0: T1REL7-0 PWM/Timer 1 Reload LSB
This register is used to write the Timer 1 Reload
value (LSB).
PWM/Timer 1 Counter Low Output Register
(PWM1_COUNT_OUT_L)
Output Register 12 (0Ch) Write only
Reset Value: 0000 0000 (00h)
Note:
by
writing
this
register,
the
PWM1_RELOAD_x couple is latched in the
internal registers of the peripherals. For this
reason, this register should be written after the
MSB one.
7
0
T1CO7 T1CO6 T1CO5 T1CO4 T1CO3 T1CO2 T1CO1 T1CO0
Bit 7-0: T1CO7-0 PWM/Timer 1 Counter LSB
This register is used to write the Timer 1 Counter
value (LSB).
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13 SERIAL COMMUNICATION INTERFACE
sampling time, a logic level 0 is sampled after three
logic levels of 1.
The Serial Communication Interface (SCI)
integrated into ST52F510/F513/F514 provides a
general purpose shift register peripheral, several
widely distributed devices to be linked, through
their SCI subsystem. SCI gives a serial interface
providing communication with the speed from less
than 300 up to over 115200 baud, and a flexible
character format.
SCI is a full-duplex UART-type asynchronous
system with standard Non Return to Zero (NRZ)
format for the transmitted/received bit. The length
of the transmitted word is 10/11 bits (1 start bit, 8/
9 data bits, 1 stop bit).
The recognition of the START bit forces the SCI
Receiver Block to start a data acquisition
sequence.
The data acquisition sequence is configured by the
apposite Configuration Register, allowing the
following data frame formats (see Figure 13.1):
Figure 13.1 SCI transmitted word structures
STOP
DATA
START
6
4
4
3
3
2
2
1
1
0
10
9
8
8
5
7
7
SCI is composed of three modules: Receiver,
Transmitter and Baud-Rate Generator.
STOP
DATA
START
13.1 SCI Receiver block
6
5
0
9
The SCI Receiver block manages the
synchronization of the serial data stream and
stores the data characters. The SCI Receiver is
mainly composed of two sub-systems: Recovery
Buffer Block and SCDR_RX Block.
SCI receives data deriving from the RX pin and
drives the Recovery Buffer Block, which is a high-
speed shift register operating at a clock frequency
(CLOCK_RX) 16 times higher than the fixed baud
rate (CLOCK_TX). This sampling rate, higher than
the Baud Rate clock, detects the START condition,
Noise error and Frame error.
I 8 bit length, 1 stop bit, no parity bit
I 8 bit length, 2 stop bit, no parity bit
I 8 bit length, 1 stop bit, with parity bit
I 9 bit length, 1 stop bit, no parity bit
The parity bit (if used) can be configured for even
or odd parity check. If the 9-bit length format is
configured, this bit is used in transmission for the
ninth bit (see below). The ninth bit received can be
read in the R8 bit of the SCI Status Register,
address 37 (035h) bit 2 (see Figure 13.3).
When the SCI Receiver is in IDLE status, it is
waiting for the START condition, which is obtained
with a logic level of 0, consecutive to a logic level
1. This condition is detected if, with the fixed
Figure 13.2 SCI Block Diagram
SCI
SCI Receiver
Register File
RX
TX
RECOVERY BUFFER
SCDR_RX
LDRI
IR
SCI Transmitter
SHIFT REGISTER
SCDR_TX
Program/Data
Memory
LDPR/LDPE/LDPI
OR
MCLK
Baud-Rate
Generator
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ST52F510/F513/F514
Recognition of a STOP condition transfers data
received from the Recovery Buffer to the
SCDR_RX buffer, adding the eventual ninth data
bit. After this operation, RXF flag (bit 5) of SCI
Status Input Register is set to logic level 1. The
Control Unit reads data from the SCDR_RX buffer
(in read-only mode) by reading the SCI_IN Input
Register (address 36 024h) with the LDRI
instruction and provides a reset at logic level 0 to
the RXF flag.
The procedure described above, allows SCI not to
becomes IDLE, because of a limited noise due to
an erroneous sampling, the transmission is
recognized as correct and the noise flag error is
set.
At the end of the cycle of the reception of a bit, the
Recovery Buffer Block will repeat the same steps 9
times: one step for each bit received, plus one for
the stop acquisition (10 times in case of 9-bit data,
double stop or parity check).
If data of the Recovery Buffer is ready to be
transferred into the SCDR_RX buffer, but the
previous one has not been read by the Core, an
OVERRUN Error takes place: the SCI Status
Register flag OVERR (bit 4) indicates the error
condition. In this case, information that is stored in
the SCDR_RX buffer is not altered, but the one
that has caused the OVERRUN error can be
overwritten by new data deriving from the serial
data line.
At the end of data reception the Recovery Buffer
Block will supply information about eventual frame
errors by setting the 1 FRERR flag (bit 6) of the SCI
Status Register to 1.
A frame error can occur if the parity check hasn’t
been successfully achieved or if the STOP bit has
not been detected.
If the Recovery Buffer Block receives 10
consecutive bits at logic level 0, a Line Break
condition occurs and the related Interrupt Request
is sent.
13.1.1 Recovery Buffer Block .
This block is structured as a synchronized finite
state machine on the CLOCK_RX signal.
When the Recovery Buffer Block is in IDLE state it
waits for the reception of the correct 1 and 0
sequence representing START.
Recognition takes place by sampling the input RX
at CLOCK_RX frequency, which has a frequency
that is 16 times higher than CLOCK_TX. For this
reason, while the external transmitter sends a
single bit, the Recovery Buffer Block samples 16
states (from SAMPLE1 to SAMPLE16).
Analysis of the RX input signal is carried out by
checking three samples for each bit received.
If these three samples are not equal, then the
noise error flag, NSERR (bit 7), of SCI Status
Register is set to 1 and the data received value will
be the one assumed by the majority of the
samples.
13.1.2 SCDR_RX Block.
It is a finite state machine synchronized with the
clock master signal, fCKM.
The SCDR_RX block waits for the signal of
complete reception from the Recovery Buffer in
order to load the word received. Moreover, the
SCDR_RX block loads the values of FRERR and
NSERR flag bits of the Status Register, and sets
the RXF flag to 1.
By using the LDRI instruction data is transferred to
Register File and RXF flag is reset to 0, to indicate
that the SCDR_RX block is empty.
If new data arrives before the previous one has
been transferred to Register File, the overrun error
occurs and the OVERR flag of Status Register is
set to 1.
Figure 13.3 SCI Status Register
SCI_STATUS Input Register 37
D7 D6 D5 D4 D3 D2 D1 D0
TXEND - END TRANSMISSION
TXEM
R8
- TRANSMISSION DATA REGISTER EMPTY
- RECEIVED NINTH BIT
NOT USED
OVERR - OVERRUN ERROR
RXF
- RECEIVE DATA REGISTER FULL
FRERR - FRAME ERROR
NSERR - NOISE ERROR
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13.2 SCI Transmitter Block
13.3 Baud Rate Generator Block
The SCI Transmitter Block consists of the following
blocks: SCDR_TX and SHIFT REGISTER,
synchronized, respectively, with the clock master
signal (fCKM) and the CLOCK_TX.
The Baud Rate Generator Block performs the
division of the clock master signal (fCKM) in a set
of synchronism frequencies for the serial bit
reception/transmission on the external line.
The whole block receives the settings for the
following transmission modes through the
Configuration Register:
Reception frequency (CLOCK_RX) is 16 times
higher
than
the
transmission
frequency
(CLOCK_TX).
I 8 bit length, 1 stop bit, no parity bit
I 8 bit length, 2 stop bit, no parity bit
I 8 bit length, 1 stop bit, with parity bit
I 9 bit length, 1 stop bit, no parity bit
To adapt the Baud Rate Generator to the clock
master frequency supplied by the user, a 12-bit
Prescaler must be programmed by loading the
Configuration Registers SCI_CR2 (PRESC_H bit
11:8 of the 12 bit prescaler) and SCI_CR3
(PRESC_L bit 7:0 of the 12 bit prescaler). The
prescaler allows the programming of all standard
Baud Rates by using the most common clock
master sources.
In case of 9 bit frame transmission, the most
significative bit arrives through the bit PAR/T8 (bit
2) of the SCI_CR1 Configuration Register. In an 8-
bit transmission, instead, this bit is used to
configure the data format: in particular to choose
the polarity control (even or odds) to implement the
parity check (see above).
The Prescaler value can be obtained by the
following formula:
CKM
16 × BAUD
After a RESET, the SCDR_TX block is in IDLE
state until it receives an enabling signal by writing
the TXSTRT bit of the SCI_CR2 Configuration
Register.
----------------------------
PRESC = round
Where fCKM is the clock master frequency
(expressed in Hz) and BAUD is the desired Baud
Rate (expressed in bit/second). The obtained
value is rounded to the nearest integer value. This
rounding can cause an error in the obtained Baud
Rate. This error must be lower than 3%. To verify
that the PRESC value satisfies this constrain, the
obtained Baud Rate must be computed by
inverting the previous formula:
The data is loaded on the Peripheral Register
SCI_OUT (address 23 017h) by using the
instruction LPPR, LDPI or LDPE. If the
transmission is enabled (TXTSTRT bit of the
SCI_CR2 configuration register), the data to be
transmitted is transferred from the Output Register
to SCDR_TX block and the TXEM flag (bit 1) of the
SCI Status Register is reset to 0 to indicate
SCDR_TX block is full.
If the core supplies new data, this could not be
loaded in the SCDR_TX block until the current data
has not been unloaded on the Shift Register block.
Meaning that only when TXEM is 1 data can be
loaded in the SCDR_TX Block.
When the SHIFT REGISTER Block loads the data
to be transmitted on an internal buffer, the TXEND
flag (bit 0) of the SCI Status Register is reset to 0
to indicate the beginning of a new transmission. At
the end of transmission TXEND is set to 1, allowing
new data coming from SCDR_TX to be loaded in
the SHIFT REGISTER.
CKM
16 × PRESC
-------------------------------
BAUD =
then the following relation can be used to verify
that the difference with the desired Baud Rate is
lower than 3%:
BAUD – BAUD
------------------------------------------
< 0,03
BAUD
It is important to underline that TXEND = 1 does
not mean SCDR_TX is ready to receive a new
data. For this reason, it is better to utilize the TXEM
signal to synchronize the load instruction to the
SCI TRANSMITTER block
If the TXSTRT bit is reset, the transmission is
stopped, but the SCI Transmitter block completes
the transmission in progress before resetting.
Table 13.1 shows the recommended Prescaler
values for common clock master frequencies. To
get more precision in Baud Rate, standard quartz
frequencies for serial communication can be used.
The corresponding Prescaler values for these
frequencies are showed in the Table 13.2.
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Table 13.1 Recommended Prescaler values for common frequencies (Baud/MHz)
1
52
26
13
-
4
208
104
52
26
13
-
5
260
130
65
33
16
8
8
417
208
104
52
26
13
-
10
521
260
130
65
12
625
313
156
78
16
833
417
208
104
52
20
1042
521
260
130
65
1200
2400
4800
9600
19200
38400
57600
115200
-
33
39
-
16
20
26
33
-
-
-
11
13
17
22
-
-
-
-
-
-
-
11
Table 13.2 Recommended Prescaler values for serial communication quartz (Baud/MHz)
1.843
96
48
24
12
6
2.458
128
64
32
16
8
3.686
192
96
48
24
12
6
4.915
256
128
64
32
16
8
6.144
320
160
80
40
20
10
-
7.373
384
192
96
9.830
512
256
128
64
11.059
576
288
144
72
12.288
640
320
160
80
14.746
768
384
192
96
19.661
1024
512
256
128
64
1200
2400
4800
9600
48
19200
38400
57600
115200
24
32
36
40
48
3
4
12
16
18
20
384
16
32
2
-
4
-
8
-
12
13
21
1
-
2
-
-
4
-
6
-
8
-
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13.4 SCI Register Description
SCI Control Register 2 (SCI_CR2)
The following registers are related to the use of the
SCI peripheral.
Configuration Register 23 (017h) Read/Write
Reset Value: 0000 0000 (00h)
7
4
2
0
13.4.1 SCI Configuration Registers.
PRESC_H
-
RXSTRT TXSTRT
SCI Control Register 1 (SCI_CR1)
Configuration Register 22 (016h) Read/Write
Reset Value: 0000 0000 (00h)
Bit 7-4: PRESC_H Baud Rate prescaler (bit 11:8)
These bits are the higher part of the
prescaler (see SCI_CR3 Configuration
Register) which determinates the baud rate
of the communication, according to Table
13.1 and Table 13.2, as explained in
Paragraph 13.3.
7
2
0
RXFINT OVRINT BRKINT TXEMINTTXENINT PAR/T8
FRM
Bit 7: RXFINT SCDR_RX buffer full interrupt mask
0: interrupt disabled
Bit 3-2: not used
1: interrupt enabled
Bit 1: RXSTRT Reception enable
0: RX disabled
Bit 6: OVRINT Overrun interrupt mask
0: interrupt disabled
1: RX enabled
1: interrupt enabled
Bit 0: TXSTRT Transmission enable
0: TX disabled
Bit 5: BRKINT Break interrupt mask
0: interrupt disabled
1: TX enabled
1: interrupt enabled
SCI Control Register 3 (SCI_CR3)
Configuration Register 43 (02Bh) Read/Write
Reset Value: 0000 0000 (00h)
Bit 4: TXEMINT SCDR_TX buffer empty interrupt
0: interrupt disabled
1: interrupt enabled
7
0
Bit 3: TXENINT TX end interrupt mask
0: interrupt disabled
PRESC_L
1: interrupt enabled
Bit 7-0: PRESC_L Baud Rate prescaler (bit 7:0)
These bits are the lower part of the
prescaler (see SCI_CR2 Configuration
Register) which determinates the baud rate
of the communication, according to Table
13.1 and Table 13.2, as explained in
Paragraph 13.3.
Bit 2: PAR/T8 Parity type selection or TX 9th bit
0: parity odd if enabled, else TX 9th bit=0
1: parity even if enabled, else TX 9th bit=1
Bit 1-0: FRM Frame type selection
00: 8 bit, no parity, 1 stop bit
01: 8 bit, no parity, 2 stop bit
10: 8 bit, parity, 1 stop bit
11: 9 bit, no parity, 1 stop bit
Note: the SCI interrupts are not enabled unless the
bit 3 (MSKSCI) of the Configuration Register 0
(INT_MASK) is enabled (set to 1).
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13.4.2 SCI Input Registers.
Bit 4: OVERR Overrun error
0: overrun error not occurred
1: overrun error occurred
SCI RX data Input Register (SCI_IN)
Input Register 36 (024h) Read only
Reset Value: 0000 0000 (00h)
Bit 3: not used
7
0
Bit 2: R8 Received 9th bit
0: RX 9th bit=0
RX7
RX6
RX5
RX4
RX3
RX2
RX1
RX0
1: RX 9th bit=1
Bit 7-0: RX7-0 RX Data
Bit 1: TXEM TX data register empty
0: TX data register full
In this register the last received serial data can be
read.
1: TX data register empty
Bit 0: TXEND TX end flag
0: data transferred to the shift register
1: data transmission completed
SCI Status Register (SCI_STATUS)
Input Register 37 (025h) Read only
Reset Value: 0000 0011 (03h)
7
0
13.4.3 SCI Output Register.
NSERR FRERR
RXF
OVERR
-
R8
TXEM TXEND
SCI TX data Output Register (SCI_OUT)
Output Register 23 (017h) Write only
Reset Value: 0000 0000 (00h)
Bit 7: NSERR Noise error
0: noise error not occurred
1: noise error occurred
7
0
TX7
TX6
TX5
TX4
TX3
TX2
TX1
TX0
Bit 6: FRERR Frame error
0: frame error not occurred
1: frame error occurred
Bit 7-0: TX7-0 TX Data
In this register the serial data to be transmitted can
be written.
Bit 5: RXF RX data register full
0: RX data register already read
1: RX data register full but not read yet
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14 I2C BUS INTERFACE (I2C)
14.1 Introduction
14.3 General Description
In addition to receiving and transmitting data, this
interface converts it from serial to parallel format
and vice versa, using either an interrupt or polled
handshake. The interrupts are enabled or disabled
via software. The interface is connected to the I2C
bus by a data pin (SDA) and by a clock pin (SCL).
The interface can be connected both with a
standard I2C bus and a Fast I2C bus. This
selection is made via software.
The I2C Bus Interface serves as an interface
between the microcontroller and the serial I2C bus,
providing both multimaster and slave functions and
controls all I2C bus-specific sequencing, protocol,
arbitration and timing. The
I2Bus Interface
supports fast I2C mode (400kHz).
14.2 Main Features
I Parallel-bus/I2C protocol converter
14.3.1 Mode Selection.
I Multi-master capability
The interface can operate in the following four
modes:
– Slave transmitter/receiver
– Master transmitter/receiver
By default, it operates in slave mode.
I 7-bit/10-bit Addressing
I Transmitter/Receiver flag
I End-of-byte transmission flag
I Transfer problem detection
I Aknowledge Failure Flag
The interface automatically switches from slave to
master after it generates a START condition and
from master to slave in case of arbitration loss or a
I2C Master Features:
STOP
generation,
providing
Multi-Master
capability.
I Clock generation
I I2C bus busy flag
14.3.2 Communication Flow.
I Arbitration Lost Flag
In Master mode, Communication Flow initiates
data transfer and generates the clock signal. A
serial data transfer always begins with a start
condition and ends with a stop condition. Both start
and stop conditions are generated in master mode
by software.
I End of byte transmission flag
I Transmitter/Receiver Flag
I Start bit detection flag
I Start and Stop generation
In Slave mode the interface is capable of
recognizing its own address (7 or 10-bit) and the
General Call address. The General Call address
detection may be enabled or disabled by software.
I2C Slave Features:
I Stop bit detection
I I2C bus busy flag
Data and addresses are transferred as 8-bit bytes,
(MSB first). The first byte following the start
condition is the address (one in 7-bit mode, two in
10-bit mode), which is always transmitted in
Master mode.A 9th clock pulse follows the 8 clock
cycles of a byte transfer, during which the receiver
must send an acknowledge bit to the transmitter.
Refer to Figure 14.1.
I Detection of misplaced start or stop condition
I Programmable I2C Address detection
I Transfer problem detection
I End-of-byte transmission flag
I Transmitter/Receiver flag
Figure 14.1 I2C BUS Protocol
SDA
MSB
ACK
SCL
1
2
8
9
START
STOP
CONDITION
CONDITION
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Acknowledge may be enabled and disabled via
software.
The I2C interface address and/or general call
address can be selected via software.
When the I2C cell is enabled, the SDA and SCL
pins must be configured as open-drain with or
without pull-up. The value of the external pull-up
resistance used depends on the application.
The speed of the I2C interface may be selected
between Standard (0-100KHz) and Fast I2C (100-
400KHz).
14.4 Functional Description
By default the I2C interface operates in Slave
mode (M/SL bit is cleared) except when it initiates
a transmit or receive sequence.
14.3.3 SDA/SCL Line Control.
First, the interface frequency must be configured
using the related bits of the Configuration
Registers.
Transmitter mode: the interface holds the clock line
low before transmission, in order to wait for the
microcontroller to write the byte in the Data
Register.
14.4.1 Slave Mode.
Receiver mode: the interface holds the clock line
low after reception to wait for the microcontroller to
read the byte in the Data Register.
SCL frequency is controlled by a programmable
clock divider which depends on the I2C bus mode.
As soon as a start condition is detected, the
address is received from the SDA line and sent to
the shift register; then it is compared with the
address of the interface or the General Call
address (if selected by software).
Figure 14.2 I2C Interface Block Diagram
DATA REGISTER
SDA
DATA CONTROL
SDA
DATA SHIFT REGISTER
COMPARATOR
OWN ADDRESS REGISTER (OAR)
SCL
CLOCK CONTROL
SCL
CLOCK CONTROL REGISTER (I2C_CCR)
CONTROL REGISTER (I2C_CR)
STATUS REGISTER 1 (I2C_SR1)
STATUS REGISTER 2 (I2C_SR2)
CONTROL LOGIC
INTERRUPT
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Note: In 10-bit addressing mode, the comparison
includes the header byte (11110xx0) where xx are
the two most significant bits of the address.
Closing slave communication
After the last data byte is transferred a Stop
Condition is generated by the master. The
interface detects this condition and sets:
Header matched (10-bit mode only): the interface
generates an acknowledgement pulse if the ACK
bit is set.
– EVF and STOPF bits with an interrupt if the ITE
bit is set.
Afterwards, the interface waits for a read of the
I2C_SR2 register (see Figure 14.3 Transfer
sequencing EV4).
Address not matched: the interface ignores it and
waits for another Start condition.
Address matched: the interface generates in
sequence:
Error Cases
– Acknowledge pulse if the ACK bit is set.
– BERR: Detection of a Stop or a Start condition
during a byte transfer. In this case, the EVF and
the BERR bits are set with an interrupt if the ITE
bit is set.
If it is a Stop then the interface discards the data,
releases the lines and waits for another Start
condition.
– EVF and ADSL bits are set with an interrupt if the
ITE bit is set.
Afterwards, the interface waits for the I2C_SR1
register to be read, holding the SCL line low (see
Figure 14.3 Transfer sequencing EV1).
Next, in 7-bit mode read the I2C_IN register to
determine from the least significant bit (Data
Direction Bit) if the slave must enter Receiver or
Transmitter mode.
If it is a Start then the interface discards the data
and waits for the next slave address on the bus.
– AF: Detection of a non-acknowledge bit. In this
case, the EVF and AF bits are set with an inter-
rupt if the ITE bit is set.
In 10-bit mode, after receiving the address
sequence the slave is always in receive mode. It
will enter transmit mode on receiving a repeated
Start condition followed by the header sequence
with matching address bits and the least significant
bit set (11110xx1).
Note: In both cases, the SCL line is not held low;
however, SDA line can remain low due to possible
«0» bits transmitted last. At this point, both lines
must be released by software.
Slave Receiver
Following reception of the address and after the
I2C_SR1 register has been read, the slave
receives bytes from the SDA line into the I2C_IN
register via the internal shift register. After each
byte, the interface generates the following in
sequence:
How to release the SDA / SCL lines
Set and subsequently clear the STOP bit while
BTF is set. The SDA/SCL lines are released after
the current byte is transferred.
– Acknowledge pulse if the ACK bit is set
– EVF and BTF bits are set with an interrupt if the
14.4.2 Master Mode.
ITE bit is set.
To switch from default Slave mode to Master mode
a Start condition generation is needed.
Afterwards, the interface waits for the I2C_SR1
register to be read followed by a read of the I2C_IN
register, holding the SCL line low (see Figure
14.3 Transfer sequencing EV2).
Start condition
Setting the START bit while the BUSY bit is
cleared causes the interface to switch to Master
mode (M/SL bit set) and generates a Start
condition.
Once the Start condition is sent:
– The EVF and SB bits are set by hardware with
Slave Transmitter
Following the address reception and after the
I2C_SR1 register has been read, the slave sends
bytes from the I2C_OUT register to the SDA line
via the internal shift register.
The slave waits for a read of the I2C_SR1 register
followed by a write in the I2C_OUT register,
holding the SCL line low (see Figure 14.3
Transfer sequencing EV3).
an interrupt if the ITE bit is set.
Afterwards, the master waits for a read of the
I2C_SR1 register followed by a write in the
I2C_OUT register with the Slave address, holding
the SCL line low (see Figure 14.3 Transfer
sequencing EV5).
When the acknowledge pulse is received:
– The EVF and BTF bits are set by hardware with
an interrupt if the ITE bit is set.
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Slave address transmission
At this point, the slave address is sent to the SDA
line via the internal shift register.
In order to close the communication: before
reading the last byte from the I2C_IN register, set
the STOP bit to generate the Stop condition. The
interface automatically goes back to slave mode
(M/SL bit cleared).
In 7-bit addressing mode, one address byte is sent.
In 10-bit addressing mode, sending the first byte
including the header sequence causes the
following event:
Note: In order to generate the non-acknowledge
pulse after the last data byte received, the ACK bit
must be cleared just before reading the second last
data byte.
– The EVF and ADD10 bit is set by hardware with
interrupt generation if the ITE bit is set.
Afterwards, the master waits for a read of the
I2C_SR1 register followed by a write in the
I2C_OUT register, holding the SCL line low (see
Figure 14.3 Transfer sequencing EV9).
The second address byte is sent by the interface.
After completion of this transfer (and acknowledge
from the slave if the ACK bit is set):
Master Transmitter
Following the address transmission and after the
I2C_SR1 register has been read, the master sends
bytes from the I2C_OUT register to the SDA line
via the internal shift register.
The master waits for a read of the I2C_SR1
register followed by a write in the I2C_OUT
register, holding the SCL line low (see Figure
14.3 Transfer sequencing EV8).
– The EVF bit is set by hardware with interrupt
generation if the ITE bit is set.
Afterwards, the master waits for a read of the
I2C_SR1 register followed by a write in the
I2C_CR register (for example set PE bit), holding
the SCL line low (see Figure 14.3 Transfer
sequencing EV6).
When the acknowledge bit is received, the
interface sets:
– EVF and BTF bits with an interrupt if the ITE bit
is set.
Next, the master must enter Receiver or
Transmitter mode.
In order to close the communication: after writing
the last byte to the I2C_OUT register, set the
STOP bit to generate the Stop condition. The
interface automatically returns to slave mode (M/
SL bit cleared).
Note: In 10-bit addressing mode, in order to switch
the master to Receiver mode, software must
generate a repeated Start condition and resend the
header sequence with the least significant bit set
(11110xx1).
Error Cases
– BERR: Detection of a Stop or a Start condition
during a byte transfer. In this case, the EVF and
BERR bits are set by hardware with an interrupt
if ITE is set.
– AF: Detection of a non-acknowledge bit. In this
case, the EVF and AF bits are set by hardware
with an interrupt if the ITE bit is set. To resume,
set the START or STOP bit.
– ARLO: Detection of an arbitration lost condition.
In this case the ARLO bit is set by hardware
(with an interrupt if the ITE bit is set and the in-
terface automatically goes back to slave mode
(the M/SL bit is cleared).
Master Receiver
Following the address transmission and after
I2C_SR1 and I2C_CR registers have been
accessed, the master receives bytes from the SDA
line into the I2C_IN register via the internal shift
register. After each byte the interface generates in
sequence:
– Acknowledge pulse if the ACK bit is set
– EVFand BTF bits are set by hardware with an in-
terrupt if the ITE bit is set.
Afterwards, the interface waits for a read of the
I2C_SR1 register followed by a read of the I2C_IN
register, holding the SCL line low (see Figure
14.3 Transfer sequencing EV7).
Note: In all these cases, the SCL line is not held
low; however, the SDA line can remain low due to
possible «0» bits transmitted last. Both lines must
be released via software.
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Figure 14.3 Transfer Sequencing
7-bit Slave receiver:
S
Address
A
Data1
A
Data2
Data2
A
A
DataN
DataN
A
P
.....
.....
EV1
EV2
EV2
EV2
EV4
7-bit Slave transmitter:
S
Address
A
Data1
A
NA
P
EV1
EV3
A
EV3
A
EV3-1
EV4
7-bit Master receiver:
S
Address
A
Data1
Data2
DataN NA
DataN
P
.....
EV5
EV6
EV7
A
EV7
A
EV7
A
7-bit Master transmitter:
S
Address
A
Data1
Data1
Data2
.....
P
.....
EV5
EV6 EV8
EV8
EV8
EV8
10-bit Slave receiver:
S
Header
A
Address
A
A
DataN
A
P
EV1
A
EV2
A
EV2
EV4
10-bit Slave transmitter:
S
Header
Data1
DataN
NA
P
r
.....
A
EV1
EV3
EV3-1
EV4
EV8
EV7
10-bit Master transmitter:
S
Header
A
Address
A
Data1
DataN
DataN
A
P
.....
EV5
EV9
EV6 EV8
A
EV8
10-bit Master receiver:
S
Header
Data1
A
A
P
r
.....
EV5
EV6
EV7
Legend:
S=Start, P=Stop, A=Acknowledge, NA=Non-acknowledge, Sr=Intermediate Start without a previous Sto
EVx=Event (with interrupt if ITE=1)
EV1: EVF=1, ADSL=1, cleared by reading I2C_SR1 register.
EV2: EVF=1, BTF=1, cleared by reading I2C_SR1 register followed by reading I2C_IN register.
EV3: EVF=1, BTF=1, cleared by reading I2C_SR1 register followed by writing I2C_OUT register.
EV3-1: EVF=1, AF=1, BTF=1, SCL=0; AF is cleared by reading I2C_SR2. BTF is cleared
by releasing the lines (STOP=1,STOP=0) or by readyng I2C_SR1 and writing I2C_OUT register
(I2C_OUT=FFh).Note: If lines are released by STOP=1, STOP=0, the subsequent EV4 is not seen.
I2C_SR1 and I2C_SR2 registers can be read only after the falling edge of the ninth data clock cycle
EV4: EVF=1, STOPF=1, cleared by reading I2C_SR2 register.
EV5: EVF=1, SB=1, cleared by reading I2C_SR1 register followed by writing I2C_OUT register.
EV6: EVF=1, cleared by reading I2C_SR1 register followed by writing I2C_CR (for example PE=1)
EV7: EVF=1, BTF=1, cleared by reading I2C_SR1 register followed by reading I2C_IN register.
EV8: EVF=1, BTF=1, cleared by reading I2C_SR1, followed by writing I2C_OUT register or an Sr.
EV9: EVF=1, ADD10=1, cleared by reading I2C_SR1 register followed by writing I2C_OUT register
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Figure 14.4 Event Flags and Interrupt Generation
ITE
ADD10
BTF
ADSL
SB
INTERRUPT
EVF
AF
STOPF
ARLO
BERR
*
* EVF can also be set by EV6 or an error from the I2C_SR2 register.
Enable
Control
Bit
Exit
from
Wait
Exit
from
Halt
Event
Flag
Interrupt Event
10-bit Address Sent Event (Master Mode)
End of Byte Transfer Event
ADD10
BTF
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
No
Address Matched Event (Slave Mode)
Start Bit Generation Event (Master Mode)
Acknowledge Failure Event
ADSEL
SB
ITE
AF
Stop Detection Event (Slave Mode)
Arbitration Lost Event (Multimaster configuration)
Bus Error Event
STOPF
ARLO
BERR
Note: The I2C interrupt events are connected to the same interrupt vector. They generate an interrupt if
the corresponding Enable Control Bit (ITE) is set and the Interrupt Mask bit (MSKI2C) in the INT_MASK
Configuration Register is unmasked (set to 1, see Interrupts Chapter).
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14.5 Register Description
– In Slave Mode
In the following sections describe the registers
used by the I2C Interface are described.
0: No Start generation
1: Start generation when the bus is free
14.5.1 I2C Interface Configuration Registers.
Bit 2: ACK Acknowledge enable
This bit is set and cleared by software. It is
also cleared by hardware when the interface
is disabled (PE=0).
I2C Control Register (I2C_CR)
Configuration Register 16 (010h) Read/Write
Reset Value: 0000 0000 (00h)
0: No acknowledge returned
1: Acknowledge returned after an address
byte or a data byte is received
7
0
-
-
PE
ENGC START
ACK
STOP
ITE
Bit 1: STOP Generation of a Stop Condition
This bit is set and cleared by software. It is
also cleared by hardware in master mode.
Note: This bit is not cleared when the
interface is disabled (PE=0).
Bit 7-6: Not Used. They must be held to 0.
Bit 5: PE Peripheral Enable.
This bit is set and cleared by software
0: peripheral disabled
– In Master Mode
0: No Stop generation
1: peripheral enabled
1: Stop generation after the current byte
transfer or after the current Start condition
is sent. The STOP bit is cleared by
hardware when the Stop condition is sent.
Notes:
– When PE=0, all the bits of the I2C_CR register
and the SR register except the Stop bit are reset.
All outputs are released while PE=0
– In Slave Mode
– When PE=1, the corresponding I/O pins are se-
0: No actions performed
lected by hardware as alternate functions.
– To enable the I2C interface, write the I2C_CR
register TWICE with PE=1 as the first write only
activates the interface (only PE is set).
1: Release the SCL and SDA lines after the
last byte transfer (BTF=1) in slave
transmitter mode. In this mode the STOP
bit has to be cleared by software.
Bit 4: ENGC Enable General Call
Bit 0: ITE Interrupt Enable
0: Interrupt disabled
1: Interrupt enabled
This bit is set and cleared by software. It is
also cleared by hardware when the interface
is disabled (PE=0).
0: General Call disabled
1: General Call enabled
Note: The 00h General Call address is
acknowledged (01h ignored).
I2C Clock Control Register (I2C_CCR)
Configuration Register 17 (011h) Read/Write
Reset Value: 0000 0000 (00h)
Bit 3: START Generation of a Start Condition
This bit is set and cleared by software. It is
also cleared by hardware when the interface
is disabled (PE=0) or when the Start
condition is sent (with interrupt generation if
ITE=1).
7
0
FM/SM
CC6
CC5
CC4
CC3
CC2
CC1
CC0
Bit 7: FM/SM Fast/Standard I2C Mode.
– In Master Mode
This bit is set and cleared by software. It is
not cleared when the interface is disabled
(PE=0).
0: No Start generation
1: Repeated Start generation
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1: Standard I2C Mode (recommended up to
100 kHz)
0: Fast I2C Mode (recommended up to 400
kHz)
I2C Own Address Register 2 (I2C_OAR2)
Configuration Register 19 (013h) Read/Write
Reset Value: 0000 0000 (00h)
7
2
0
-
Bit 6-0: CC6-CC0 7-bit clock divider
-
-
-
-
-
ADD9
ADD8
These bits select the speed of the bus (FSCL
)
depending on the I2C mode. They are not
cleared when the interface is disabled
(PE=0). The speed can be computed as
follows:
Bit 7-3: Not Used
bit 2-1: ADD9-ADD8 Interface address.
– Standard mode (FM/SM=1): FSCL <= 100kHz
FSCL = fCPU/(3x[CC6..CC0]+11)
– Fast mode (FM/SM=0): FSCL > 100kHz
FSCL = fCPU/(2x[CC6..CC0]+9)
These are the most significant bits of th I2C
bus address of the interface (10-bit mode
only). They are not cleared when the
interface is disabled (PE=0).
Bit 0: Reserved, it must be left to 0.
Warning: For safety reason, CC6-CC0 bits must
be configured with a value >= 3 for the Standard
mode and >=2 for the Fast mode.
14.5.2 I2C Interface Input Registers.
I2C Data Input Register (I2C_IN)
Input Register 6 (06h) Read only
Reset Value: 0000 0000 (00h)
I2C Own Address Register 1 (I2C_OAR1)
Configuration Register 18 (012h) Read/Write
Reset Value: 0000 0000 (00h)
7
0
7
0
I2CDI7 I2CDI6 I2CDI5 I2CDI4 I2CDI3 I2CDI2 I2CDI1 I2CDI0
ADD7
ADD6
ADD5
ADD4
ADD3
ADD2
ADD1
ADD0
bit 7-0: I2CDI7-I2CDI0 Received data.
7-bit Addressing Mode
bit 7-1: ADD7-ADD1 Interface address.
These bits define the I2C bus address of the
interface. They are not cleared when the
interface is disabled (PE=0).
These bits contain the byte to be received from the
bus in Receiver mode: the first data byte is
received automatically in the I2C_IN register using
the least significant bit of the address.
Then, the next data bytes are received one by one
after reading the I2C_IN register.
Bit 0: ADD0 Address direction bit.
This bit is “don’t care”, the interface
acknowledges either 0 or 1. It is not cleared
when the interface is disabled (PE=0).
Note: Address 01h is always ignored.
I2C Status Register 1 (I2C_SR1)
Input Register 7 (07h) Read only
Reset Value: 0000 0000 (00h)
10-bit Addressing Mode
bit 7-0: ADD7-ADD0 Interface address.
7
0
These are the least significant bits of the I2C
bus address of the interface. They are not
cleared when the interface is disabled
(PE=0).
EVF
ADD10
TRA
BUSY
BTF
ADSL
M/SL
SB
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Bit 7: EVF Event Flag
This bit is set by hardware as soon as an
This information is not updated when the
interface is disabled (PE=0).
0: No communication on the bus
event occurs. It is cleared by software
reading I2C_SR2 register in case of error
event or as described in Figure 14.3. It is also
cleared by hardware when the interface is
disabled (PE=0).
1: Communication ongoing on the bus
Bit 3: BTF Byte transfer finished
This bit is set by hardware as soon as a byte
is correctly received or transmitted with
interrupt generation if ITE=1. It is cleared by
software reading I2C_SR1 register followed
by a read of I2C_IN or write of I2C_OUT
registers. It is also cleared by hardware when
the interface is disabled (PE=0).
0: No event
1: One of the following events has occurred:
– BTF=1 (Byte received or transmitted)
– ADSL=1 (Address matched in Slave
mode while ACK=1)
– SB=1 (Start condition generated in Mas-
ter mode)
– Following a byte transmission, this bit is
set after reception of the acknowledge
clock pulse. In case an address byte is
sent, this bit is set only after the EV6
event (see Figure 14.3). BTF is cleared
by reading I2C_SR1 register followed by
writing the next byte in I2C_OUT register.
– Following a byte reception, this bit is set
after transmission of the acknowledge
clock pulse if ACK=1. BTF is cleared by
reading I2C_SR1 register followed by
reading the byte from I2C_IN register.
– AF=1 (No acknowledge received after
byte transmission)
– STOPF=1 (Stop condition detected in
Slave mode)
– ARLO=1 (Arbitration lost in Master
mode)
– BERR=1 (Bus error, misplaced Start or
Stop condition detected)
– ADD10=1 Address byte successfully
transmitted in Master mode.
The SCL line is held low while BTF=1.
0: Byte transfer not done
Bit 6: ADD10 10 bit addressing in Master Mode
1: Byte transfer succeeded
This bit is set by hardware when the master
has sent the first byte in 10-bit address mode.
It is cleared by software reading I2C_SR1
register followed by a write in the I2C_OUT
register of the second address byte. It is also
cleared by hardware when the peripheral is
disabled (PE=0).
Bit 2: ADSL Address matched (Slave Mode)
This bit is set by hardware as soon as the
slave address received matched with the
OAR register content or a general call is
recognized. An interrupt is generated if
ITE=1. It is cleared by software reading
I2C_SR1 register or by hardware when the
interface is disabled (PE=0).
0: No ADD10 event occurred
1: The Master has sent the first address byte
Bit 5: TRA Transmitter/Receiver
The SCL line is held low while ADSL=1.
0: Address mismatched or not received
1: Received address matched
When BTF is set, TRA=1 if a data byte has
been transmitted. It is cleared automatically
when BTF is cleared. It is also cleared by
hardware after detection of Stop condition
(STOPF=1), loss of bus arbitration (ARLO=1)
or when the interface is disabled (PE=0).
Bit 1: M/SL Master/Slave
This bit is set by hardware as soon as the
interface is in Master mode (writing
START=1). It is cleared by hardware after
detecting a Stop condition on the bus or a
loss of arbitration (ARLO=1). It is also
cleared when the interface is disabled
(PE=0).
0: Data byte received (if BTF=1)
1: Data byte transmitted
Bit 4: BUSY Bus busy
This bit is set by hardware on detection of a
Start condition and cleared by hardware
either on detection of a Stop condition or
when a bus error occurs. It indicates a
communication in progress on the bus.
0: Slave mode
1: Master mode
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Bit 0: SB Start bit (Master Mode)
After an ARLO event the interface switches
back automatically to Slave mode (M/SL=0).
The SCL line is not held low while ARLO=1.
0: No arbitration lost detected
This bit is set by hardware as soon as the
Start condition is generated (following a write
START=1). An interrupt is generated if
ITE=1. It is cleared by software reading
I2C_SR1 register followed by writing the
address byte in I2C_OUT register. It is also
cleared by hardware when the interface is
disabled (PE=0).
1: Arbitration lost detected
Bit 1: BERR Bus error.
This bit is set by hardware when the interface
detects a misplaced Start or Stop condition.
An interrupt is generated if ITE=1. It is
cleared by software reading I2C_SR2
register or by hardware when the interface is
disabled (PE=0).
The SCL line is not held low while BERR=1.
0: No misplaced Start or Stop condition
1: Misplaced Start or Stop condition
0: No Start condition
1: Start condition generated
I2C Status Register 2 (I2C_SR2)
Input Register 8 (08h) Read only
Reset Value: 0000 0000 (00h)
7
0
Note: Also a polling on BUSY bit has to be done to
detect a bus error (BUSY bit cleared by hardware).
-
-
-
AF
STOPF ARLO
BERR
GCAL
Bit 0: GCAL General Call (Slave mode).
Bit 7-5: Reserved.
Bit 4: AF Acknowledge failure.
This bit is set by hardware when a general
call address is detected on the bus while
ENGC=1. It is cleared by hardware detecting
a Stop condition (STOPF=1) or when the
interface is disabled (PE=0).
0: No general call address detected on bus
1: general call address detected on bus
This bit is set by hardware when no
acknowledge is returned. An interrupt is
generated if ITE=1. It is cleared by software
reading the I2C_SR2 register or by hardware
when the interface is disabled (PE=0).
The SCL line is not held low while AF=1.
0: No acknowledge failure
1: Acknowledge failure
14.5.3 I2C Interface Output Registers.
Bit 3: STOPF Stop detection (Slave mode).
I2C Data Output Register (I2C_OUT)
Output Register 6 (06h) Write only
Reset Value: 0000 0000 (00h)
This bit is set by hardware when a Stop
condition is detected on the bus after an
acknowledge (if ACK=1). An interrupt is
generated if ITE=1. It is cleared by software
reading I2C_SR2 register or by hardware
when the interface is disabled (PE=0).
7
0
I2CDO7 I2CDO6 I2CDO5 I2CDO4 I2CDO3 I2CDO2 I2CDO1 I2CDO0
The SCL line is not held low while STOPF=1.
0: No Stop condition detected
1: Stop condition detected
bit 7-0: I2CDO7-I2CDO0 Data to be transmitted.
Bit 2: ARLO Arbitration lost.
These bits contain the byte to be transmitted in the
bus in Transmitter mode: Byte transmission start
automatically when the software writes in the
I2C_OUT register.
This bit is set by hardware when the interface
loses the arbitration of the bus to another
master. An interrupt is generated if ITE=1. It
is cleared by software reading I2C_SR2
register or by hardware when the interface is
disabled (PE=0).
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15 SERIAL PERIPHERAL INTERFACE (SPI)
15.1 Introduction
A basic example of interconnections between a
single master and a single slave is illustrated in
Figure 15.1
The Serial Peripheral Interface (SPI) allows full-
duplex, synchronous, serial communication with
external devices. An SPI system may consist of a
master, one or more slaves, or a system, in which
devices may be either masters or slaves.
SPI is normally used for communication between
the ICU and external peripherals or another ICU.
The MOSI pins are connected together as the
MISO pins. In this manner, data is transferred
serially between master and slave (most significant
bit first).
When the master device transmits data to a slave
device via the MOSI pin, the slave device responds
by sending data to the master device via the MISO
pin. This implies full duplex transmission with both
data out and data in synchronized with the same
clock signal (which is provided by the master
device via the SCK pin).
The transmitted byte is replaced by the byte
received and eliminates the need for separate
transmit-empty and receiver-full bits. A status flag
is used to indicate that the I/O operation is
complete.
Four possible data/clock timing relationships may
be chosen (see Figure 15.4), but master and slave
must be programmed with the same timing mode.
Refer to the Pin Description section in this
datasheet for the device-specific pin-out.
15.2 Main Features
I Full duplex, three-wire synchronous transfers
I Master or slave operation
I Four master mode frequencies
I Maximum slave mode frequency = fCKM/4.
I Four programmable master bit rates
I Programmable clock polarity and phase
I End of transfer interrupt flag
15.4 Functional Description
I Write collision flag protection
Figure 15.2 shows the serial peripheral interface
(SPI) block diagram.
I Master mode fault protection capability.
This interface contains 4 dedicated registers:
– A Control Register (SPI_CR)
15.3 General description
– A Status Register (SPI_STATUS_CR)
– A Data Register for transmission (SPI_OUT)
– A Data Register for reception (SPI_IN)
SPI is connected to external devices through 4
alternate pins:
– MISO: Master In / Slave Out pin
– MOSI: Master Out / Slave In pin
– SCK: Serial Clock pin
15.4.1 Master Configuration.
– SS: Slave select pin (if not done through soft-
In a master configuration, the serial clock is
generated on the SCK pin.
ware)
Figure 15.1 SPI Master Slave
SLAVE
MASTER
MSBit
LSBit
MSBit
LSBit
MISO
MOSI
MISO
MOSI
8-BIT SHIFT REGISTER
8-BIT SHIFT REGISTER
SPI
CLOCK
GENERATOR
SCK
SS
SCK
SS
+5V
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Figure 15.2 Serial Peripheral Interface Block Diagram
Internal Bus
Read
Read Buffer
IT
request
SPI_IN
MOSI
SPI_STATUS_CR
MISO
8-Bit Shift Register
SPI_OUT
SPIF WCOL OR MODF
SOD SSM SSI
-
Write
SPI
STATE
CONTROL
SCK
SS
SPI_CR
MSTR
SPR0
SPIE SPE SPR2
CPOL CPHA SPR1
MASTER
CONTROL
SERIAL
CLOCK
GENERATOR
Procedure
The data byte is loaded in parallel into the 8-bit shift
register (from the internal bus) during a write cycle
and then shifted out serially to the MOSI pin most
significant bit first.
When data transfer is complete:
– The SPIF bit is set by hardware
– Select the SPR0, SPR1 and SPR2 bits to define
the serial clock baud rate (see SPI_CR register).
– Select the CPOL and CPHA bits to define one of
the four relationships between the data transfer
and the serial clock (see Figure 15.4).
– The SS pin must be connected to a high level
signal during the complete byte transmit se-
quence, if this pin is used.
– The MSTR and SPE bits must be set (they re-
main set only if the SS pin is connected to a high
level signal).
– An interrupt is generated if the SPIE bit is set.
During the last clock cycle the SPIF bit is set, a
copy of the data byte received in the shift register
is moved to a buffer. When the SPI_IN register is
read, the SPI peripheral returns this buffered
value. Clearing the SPIF bit is performed by the
following software sequence:
In this configuration the MOSI pin is a data output
and to the MISO pin is a data input.
1. An access to the SPI_STATUS_CR register
while the SPIF bit is set
2. A read to the SPI_IN register.
Transmit sequence
Transmit sequence begins when a byte is written in
the SPI_OUT register.
Note: While the SPIF bit is set, all writes to the
SPI_OUT register are inhibited until the
SPI_STATUS_CR register is read.
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15.4.2 Slave Configuration.
In slave configuration, the serial clock is received
on the SCK pin from the master device.
(shifted in serially). The serial clock is used to
synchronize data transfer during a sequence of
eight clock pulses.
The SS pin allows individual selection of a slave
device; the other slave devices that are not
selected do not interfere with SPI transfer.
The value of the SPR0, SPR1 and SPR2 bits is not
used for data transfer.
Procedure
Clock Phase and Clock Polarity
Four possible timing relationships may be chosen
by software, using the CPOL and CPHA bits.
– For correct data transfer, the slave device must
be in the same timing mode as the master de-
vice (CPOL and CPHA bits). See Figure 15.4.
The CPOL (clock polarity) bit controls the steady
state value of the clock when data isn’t being
transferred. This bit affects both master and slave
modes.
The combination between the CPOL and CPHA
(clock phase) bits select the data capture clock
edge.
Figure 15.4, shows an SPI transfer with the four
combinations of the CPHA and CPOL bits. The
diagram may be interpreted as a master or slave
timing diagram where the SCK pin, the MISO pin,
the MOSI pin are directly connected between the
master and the slave device.
– The SS pin must be connected to a low level sig-
nal during the complete byte transmit sequence,
if this pin is used.
– Clear the MSTR bit and set the SPE bit to assign
the pins to alternate function.
In this configuration the MOSI pin is a data input
and the MISO pin is a data output.
Transmit Sequence
The data byte is loaded into the 8-bit shift register
(from the internal bus) during a write cycle and
then shifted out serially to the MISO pin most
significant bit first.
The transmit sequence begins when the slave
device receives the clock signal and the most
significant bit of the data on its MOSI pin.
The SS pin is the slave device select input and can
be driven by the master device.
The master device applies data to its MOSI pin-
clock edge before the capture clock edge.
When data transfer is complete:
– The SPIF bit is set by hardware
– An interrupt is generated if SPIE bit is set.
During the last clock cycle the SPIF bit is set, a
copy of the data byte received in the shift register
is moved to a buffer. When the SPI_IN register is
read, the SPI peripheral returns the buffer value.
CPHA bit is set
The second edge on the SCK pin (falling edge if
the CPOL bit is reset, rising edge if the CPOL bit is
set) is the MSBit capture strobe. Data is latched on
the occurrence of the second clock transition.
A write collision should not occur even if the SS pin
stays low during a transfer of several bytes (see
Figure 15.3).
The SPIF bit is cleared by the following software
sequence:
1. An access to the SPI_STATUS_CR register
while the SPIF bit is set.
CPHA bit is reset
2. A read to the SPI_IN register.
The first edge on the SCK pin (falling edge if CPOL
bit is set, rising edge if CPOL bit is reset) is the
MSBit capture strobe. Data is latched on the
occurrence of the first clock transition.
The SS pin must be toggled high and low between
each byte transmitted (see Figure 15.3).
In order to protect the transmission from a write
collision a low value on the SS pin of a slave device
freezes the data in its SPI_OUT register and does
not allow it to be altered. Therefore, the SS pin
must be high to write a new data byte in the
SPI_OUT without producing a write collision.
Note: While the SPIF bit is set, all writes to the
SPI_OUT register are inhibited until the
SPI_STATUS_CR register is read.
The SPIF bit can be cleared during a second
transmission; however, it must be cleared before
the second SPIF bit in order to prevent an overrun
condition (see Section 15.4.6).
Depending on the CPHA bit, the SS pin has to be
set to write to the SPI_OUT register between each
data byte transfer to avoid a write collision (see
Section 15.4.4).
15.4.3 Data Transfer Format.
15.4.4 Write Collision Error.
During an SPI transfer, data is simultaneously
transmitted (shifted out serially) and received
A write collision occurs when the software tries to
write to the SPI_OUT register while a data transfer
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is taking place with an external device. When this
occurs, the transfer continues uninterrupted; and
the software writing will be unsuccessful.
WCOL bit
The WCOL bit in the SPI_STATUS_CR register is
set if a write collision occurs.
Write collisions can occur both in master and slave
mode.
No SPI interrupt is generated when the WCOL bit
is set (the WCOL bit is a status flag only).
The WCOL bit is cleared by a software sequence
(see Section 15.5).
Note: a “read collision” will never occur since the
data byte received is placed in a buffer, in which
access is always synchronous with the ICU
operation.
15.4.5 Master Mode Fault.
Master mode fault occurs when the master device
has its SS pin pulled low, then the MODF bit is set.
In Slave mode
When the CPHA bit is set:
Master mode fault affects the SPI peripheral in the
following ways:
– The MODF bit is set and an SPI interrupt is
generated if the SPIE bit is set.
– The SPE bit is reset. This blocks all output from
the device and disables the SPI peripheral.
The slave device will receive a clock (SCK) edge
prior to the latch of the first data transfer. This first
clock edge will freeze the data in the slave device
SPI_OUT register and output the MSBit on to the
external MISO pin of the slave device.
The SS pin low state enables the slave device, but
the output of the MSBit onto the MISO pin does not
take place until the first data transfer clock edge
occurs.
– The MSTR bit is reset, forcing the device into
slave mode.
Clearing the MODF bit is done through a software
sequence:
1. A read or write access to the SPI_STATUS_CR
register while the MODF bit is set.
When the CPHA bit is reset:
Data is latched on the occurrence of the first clock
transition. The slave device doesn’t have a way of
knowing when that transition will occur; therefore,
the slave device collision occurs when software
attempts to write the SPI_OUT register after its SS
pin has been pulled low.
For this reason, the SS pin must be high, between
each data byte transfer, in order to allow the CPU
to write in the SPI_OUT register without generating
a write collision.
2. A write to the SPI_CR register.
Note: To avoid any multiple slave conflicts in the
case of a system comprising several MCUs, the
SS pin must be pulled high during the clearing
sequence of the MODF bit. The SPE and MSTR
bits may be restored to their original state during or
after this clearing sequence.
Hardware does not allow the user to set the SPE
and MSTR bits, while the MODF bit is set (except
in the MODF bit clearing sequence).
In Master mode
In a slave device the MODF bit can’t be set, but in
a multi master configuration the device can be in
slave mode with this MODF bit set.
Collision in the master device is defined as a write
of the SPI_OUT register, while the internal serial
clock (SCK) is in the process of transfer.
The MODF bit indicates that there might have been
a multi-master conflict for system control and
allows a proper exit from system operation to a
reset or default system state using an interrupt
routine.
The SS pin signal must always be high on the
master device.
Figure 15.3 CHPA/SS Timing Diagram
Byte 3
Byte 2
MOSI/MISO
Master SS
Byte 1
Slave SS
(CPHA=0)
Slave SS
(CPHA=1)
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Figure 15.4 Data Clock Timing Diagram
CPHA =1
CPOL = 1
CPOL = 0
Bit 4
Bit 4
Bit3
Bit 2
Bit 2
Bit 1
Bit 1
LSBit
LSBit
MSBit
MSBit
Bit 6
Bit 6
Bit 5
Bit 5
MISO
(from master)
Bit3
MOSI
(from slave)
SS
(to slave)
CAPTURE STROBE
CPHA =0
CPOL = 1
CPOL = 0
Bit 4
Bit 4
Bit3
Bit 2
Bit 2
Bit 1
Bit 1
LSBit
LSBit
MISO
(from master)
MSBit
Bit 6
Bit 6
Bit 5
Bit 5
Bit3
MOSI
(from slave)
MSBit
SS
(to slave)
CAPTURE STROBE
Note: This figure should not be used as a replacement for parametric information.
Refer to the Electrical Characteristics chapter.
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ST52F510/F513/F514
Figure 15.5 Clearing the WCOL bit (Write Collision Flag) Software Sequence
Clearing sequence after SPIF = 1 (end of a data byte transfer)
Read SPI_STATUS_CR
Read SPI_STATUS_CR
THEN
1st Step
2nd Step
OR
THEN
SPIF =0
SPIF =0
Read SPI_IN
WCOL=0 if no transfer has started
WCOL=1 if a transfer has started
before the 2nd step
Write SPI_OUT
WCOL=0
Clearing sequence before SPIF = 1 (during a data byte transfer)
Read SPI_STATUS_CR
1st Step
THEN
Note: Writing in SPI_OUT regis-
2nd Step
Read SPI_IN
ter instead of reading in SPI_IN
do not reset WCOL bit
WCOL=0
15.4.6 Overrun Condition.
The SS pins are pulled high during reset since the
master device ports will be forced to be inputs at
that time, thus disabling the slave devices.
An overrun condition occurs when the master
device has sent several data bytes and the slave
device hasn’t cleared the SPIF bit issued from the
previous data byte transmitted.
In this case, the receiver buffer contains the byte
sent after the SPIF bit was last cleared. A read to
the SPI_IN register returns this byte. All other
bytes are lost.
Note: In order to prevent a bus conflict on the
MISO line the master allows only one active slave
device during a transmission.
For more security, the slave device may respond to
the master with the data byte received. Then the
master will receive the previous byte back from the
slave device if all MISO and MOSI pins are
connected and the slave has not written its
SPI_OUT register.
This condition is not detected by the SPI
peripheral.
15.4.7 Single Master and Multimaster Configu-
rations.
Other transmission security methods can use ports
for handshake lines or data bytes with command
fields.
There are two types of SPI systems:
– Single Master System
– Multimaster System
Multi-master System
A multi-master system may also be configured by
the user. Transfer of master control could be
implemented using a handshake method through
the I/O ports or by an exchange of code messages
through the serial peripheral interface system.
The multi-master system is principally handled by
the MSTR bit in the SPI_CR register and the
MODF bit in the SPI_STATUS_CR register.
Single Master System
A typical single master system may be configured,
using an ICU as the master and four ICUs as
slaves see (Figure 15.6).
The master device selects the individual slave
devices by using four pins of a parallel port to
control the four SS pins of the slave devices.
104/137
ST52F510/F513/F514
Figure 15.6 Single Master Configuration
SS
SS
SS
SS
SCK
SCK
SCK
Slave
SCK
Slave
MCU
Slave
MCU
Slave
MCU
MCU
MOSI MISO
MOSI MISO
MOSI MISO
MOSI MISO
MOSI MISO
SCK
Master
MCU
5V
SS
15.4.8 Interrupts
Enable
Control
Bit
Exit
from
Wait
Exit
from
Halt
Event
Flag
Interrupt Event
SPI End of Transfer Event
Master Mode Fault Event
SPIF
Yes
Yes
No
No
SPIE
MODF
Note: The SPI interrupt events are connected to
the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding
Enable Control Bit (SPIE) and the interrupt mask
bit (MSKSPI) in the INT_MASK Configuration
Register is set.
105/137
ST52F510/F513/F514
15.5 SPI Register Description
Bit 3: CPOL Clock polarity.
In the following sections describe the registers
used by the SPI.
This bit is set and cleared by software. This
bit determines the steady state of the serial
Clock. The CPOL bit affects both the master
and slave modes.
0: The steady state is a low value at the SCK
pin.
15.5.1 SPI Configuration Registers.
SPI Control Register (SPI_CR)
Configuration Register 20 (014h) Read/Write
Reset Value: 0000 0000 (00h)
1: The steady state is a high value at the SCK
pin.
Note: SPI must be disabled by resetting the SPE
bit if CPOL is changed at the communication byte
boundaries.
7
0
SPIE
SPE
SPR2
MSTR
CPOL
CPHA
SPR1
SPR0
Bit 2: CPHA Clock phase.
This bit is set and cleared by software.
0: The first clock transition is the first data
capture edge.
1: The second clock transition is the first
capture edge.
Bit 7: SPIE Serial peripheral interrupt enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SPI interrupt is generated whenever
SPIF=1 or MODF=1 in SPI_STATUS_CR
Bit 1-0: SPR1-SPR0 Serial peripheral rate.
Bit 6: SPE Serial peripheral output enable.
These bits are set and cleared by software.
Used with the SPR2 bit, they select one of six
baud rates to be used as the serial clock
when the device is a master (see Table 15.1).
This bit is set and cleared by software. It is
also cleared by hardware when, in master
mode, SS=0 (see Section 15.4.5 Master
Mode Fault).
These 2 bits have no effect in slave mode.
0: I/O port connected to pins
1: SPI alternate functions connected to pins
Remark: It is recommended to write the SPI_CR
register after the SPI_STATUS_CR register when
working in master mode, vice versa when working
in slave mode.
Note: The SPE bit is cleared by reset, so the SPI
peripheral is not initially connected to the pins.
Bit 5: SPR2 Divider Enable.
This bit is set and cleared by software and it
is cleared by reset. It is used with the
SPR[1:0] bits to set the baud rate. Refer to
Table 15.1.
0: Divider by 2 enabled
1: Divider by 2 disabled
Table 15.1 Serial Peripheral Baud Rate
Serial Clock
fCKM/2
SPR2 SPR1 SPR0
1
0
0
1
0
0
0
0
0
1
1
1
0
0
1
0
0
1
fCKM/4
fCKM/8
Note: This bit has no effect in slave mode.
fCKM/16
fCKM/32
fCKM/64
Bit 4: MSTR Master/Slave mode select.
This bit is set and cleared by software. It is
also cleared by hardware when, in master
mode, SS=0 (see Section 15.4.5 Master
Mode Fault).
SPI Control-Status Register (SPI_STATUS_CR)
Configuration Register 21 (015h) Read/Write
Reset Value: 0000 0000 (00h)
0: Slave mode is selected
1: Master mode is selected, the function of
the SCK pin changes from an input to an
output and the functions of the MISO and
MOSI pins are reversed.
7
0
SPIF
WCOL
OR
MODF
-
SOD
SSM
SSI
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ST52F510/F513/F514
Bit 7: SPIF Serial Peripheral data transfer flag.
Bit 2: SOD SPI output disable
(read only)
This bit is set and cleared by software. When
set, it disables the alternate function of the
SPI output (MOSI in master mode / MISO in
slave mode)
0: SPI output not disable
1: SPI output disable.
This bit is set by hardware when a transfer
has been completed. An interrupt is
generated if SPIE=1 in the SPI_CR register.
It is cleared by a software sequence (an
access to the SPI_STATUS_CR register
followed by a read or write to the SPI_IN/
SPI_OUT registers).
Bit 1: SSM SS mode selection
0: Data transfer is in progress or has been
approved by a clearing sequence.
1: Data transfer between the device and an
external device has been completed.
This bit is set and cleared by software. When
set, it disables the alternate function of the
SPI Slave Select pin and use the SSI bit
value instead of.
0: SS pin used by the SPI.
1: SS pin not used (I/O mode), SSI bit value
is used.
Note: While the SPIF bit is set, all writes to the
SPI_OUT register are inhibited.
Bit 6: WCOL Write Collision status (read only).
This bit is set by hardware when a write to the
SPI_OUT register is done during a transmit
sequence. It is cleared by a software
sequence (see Figure 15.5).
Bit 0: SSI SS internal mode
This bit is set and cleared by software. It
replaces pin SS of the SPI when bit SSM is
set to 1. SSI bit is active low slave select
signal when SSM is set to 1.
0: No write collision occurred
1: A write collision has been detected
0 : Slave selected
1 : Slave not selected.
Bit 5: OR SPI overrun error (read only).
This bit is set by hardware when the byte
currently being received in the shift register is
ready to be transferred into the SPI_IN
register while SPIF = 1 (See Section 15.4.6
Overrun Condition). It is cleared by a
Remark: It is recommended to write the SPI_CR
register after the SPI_STATUS_CR register when
working in master mode, vice versa when working
in slave mode.
software
sequence
(read
of
the
SPI_STATUS_CR register followed by a
read in SPI_IN or write of the SPI_OUT
register).
15.5.2 SPI Input Register.
0: No overrun error.
1: Overrun error detected.
SPI Data Input Register (SPI_IN)
Input Register 5 (05h) Read only
Reset Value: 0000 0000 (00h)
Bit 4: MODF Mode Fault flag (read only).
This bit is set by hardware when the SS pin is
pulled low in master mode (see Section
15.4.5 Master Mode Fault). An SPI interrupt
can be generated if SPIE=1 in the SPI_CR
register. This bit is cleared by a software
7
0
SPIDI7 SPIDI6 SPIDI5 SPIDI4 SPIDI3 SPIDI2 SPIDI1 SPIDI0
sequence
(An
access
to
the
bit 7-0: SPIDI7-SPIDI0 Received data.
SPI_STATUS_CR register while MODF=1
followed by a write to the SPI_CR register).
The SPI_IN register is used to receive data on the
serial bus.
0: No master mode fault detected
1: A fault in master mode has been detected
Note: During the last clock cycle the SPIF bit is set,
a copy of the data byte received in the shift register
is moved to a buffer. When the user reads the
serial peripheral data I/O register, the buffer is
actually being read.
Bit 3: Not used.
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ST52F510/F513/F514
Warning: A read to the SPI_IN register returns the
value located in the buffer and not the contents of
the shift register (see Figure 15.2).
15.5.3 SPI Output Register.
SPI Data Output Register (SPI_OUT)
Output Register 5 (05h) Write only
Reset Value: 0000 0000 (00h)
7
0
SPIDO7 SPIDO6 SPIDO5 SPIDO4 SPIDO3 SPIDO2 SPIDO1 SPIDO0
bit 7-0: SPIDO7-SPIDO0 Data to be transmitted.
The SPI_OUT register is used to transmit data on
the serial bus. In the master device only a write to
this register will initiate transmission/reception of
another byte.
Warning: A write to the SPI_OUT register places
data directly into the shift register for transmission.
108/137
ST52F510/F513/F514
16 ELECTRICAL CHARACTERISTICS
16.1 Parameter Conditions
16.1.2 Typical curves.
Unless otherwise specified, all typical curves are
provided only as design guidelines and are not
tested.
Unless otherwise specified, all voltages are
referred to Vss.
16.1.1 Minimum and Maximum values. Unless
otherwise specified, the minimum and maximum
values are guaranteed in the worst conditions of
environment temperature, supply voltage and
frequencies by tests in production on 100% of the
devices with an environmental temperature at
TA=25°C and TA=TAmax (given by the selected
temperature range).
Data are based on characterization results, design
simulation and/or technology characteristics are
indicated in the table footnotes and are not tested
in production. The minimum and maximum values
are based on characterization and refer to sample
tests, representing the mean value plus or minus
three times the standard deviation (mean 3Σ).
16.1.3 Typical values.
Unless otherwise specified, typical data is based
on TA=25°C, VDD=5V. They are provided only as
design guidelines and are not tested.
16.1.4 Loading capacitor. The loading condition
used for pin parameter measurement is illustrated
in Figure 16.1.
16.1.5 Pin input voltage.
Input voltage measurement on a pin of the device
is described in Figure 16.2
Figure 16.2 Pin input Voltage
Figure 16.1 Pin loading conditions
ST52 PIN
ST52 PIN
CL
VIN
109/137
ST52F510/F513/F514
16.2 Absolute Maximum Ratings
Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device.
This is a stress rating only. Functional operation of the device under these conditions is not implied.
Exposure to maximum rating conditions for extended periods may affect device reliability.
Table 16.1 Voltage Characteristics
Symbol
Ratings
Max Values
Unit
V
-V
Supply voltage
6.5
DD SS
1) 2)
V
-0.3 to V +0.3
V
SS
DD
V
Input voltage on any pin
IN
V
Electrostatic discharge voltage
2000
DESD
Table 16.2 Current Characteristics
Symbol
Ratings
Max Values
100
Unit
3)
I
Total current in V power lines (source)
VDD
DD
3)
I
100
Total current in V ground lines (sink)
VSS
SS
Output current sunk by any standard I/O and control pin
Output current source by any I/Os and control pin
Injected current on RESET pin
20
-20
± 5
I
IO
mA
2)
Injected current on OSCin and OSCout pins
± 5
± 5
I
INJ(PIN)
4)
Injected current on any other pin
4)
ΣI
± 20
Total Injected current (sum of all I/O and control pins)
INJ(PIN)
Table 16.3 Thermal Characteristics
Symbol
Ratings
Max Values
-65 to +150
150
Unit
T
Storage temperature range
Maximum junction temperature
STG
°C
T
J
Notes:
1. Connecting I/O Pins directly to VDD or VSS could damage the device if the unintentional internal reset
is generated or an unexpected change of I/O configuration occurs (for example, due to the corrupted
program counter). In order to guarantee safe operation, this connection has to be performed via a pull-
up or pull-down resistor (typical: 10K Ω for I/Os). Unused I/O pins must be tied in the same manner to
VDD or VSS according to their reset configuration.
2. When the current limitation is not possible, the VIN absolute maximum rating must be respected, other-
wise refer to IINJ(PIN) specification. A positive injection is induced by VIN>VDD while a negative injec-
tion is induced by VIN<VSS to IINJ(PIN) specification. A positive injection is VIN>VDD while a negative
injection is induced by VIN<VSS.
3. All power (VDD) and ground (VSS) lines must always be connected to the external supply.
4. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of
the positive and negative injected currents (instantaneous values).
110/137
ST52F510/F513/F514
16.3 Operating Conditions
Operating condition: TA=-40 to 85°C (unless otherwise specified).
Table 16.4 Operating Conditions
Symbol
Parameter
Test Condition
Min.
2.8
2.8
2.8
-40
1
Max
5.5
5.5
5.5
85
Unit
Operating Supply Voltage in Working mode
Operating Supply Voltage in ISP mode
Operating Supply Voltage in IAP mode
Ambient temperature range
f
f
f
= 1 to 20MHz
= 1 to 20MHz
= 1 to 20MHz
osc
osc
osc
V
V
DD
T
°C
A
1)
External clock frequency
20
MHz
f
OSC
Notes:
1. It is recommendend to insert a capacitor beetwen VDD and VSS for improving noise rejection. recom-
mended values are 10 µF (electrolytic or tantalum) and/or 100 nF (ceramic).
Figure 16.3 fosc Maximum Operating Frequency versus VDD supply
20
Functionality not guaranteed
in this area
Functionality guaranteed in this area
10
1
0
0.5
1
1.5
2
2.7 2.8 3
3.5
4
4.5
5
5.5
6
Vdd (V)
Functionality guaranteed in this area
from 0°C to 85°C
111/137
ST52F510/F513/F514
16.4 Supply Current Characteristics
The test condition in RUN mode for all the IDD
measurements are, unless otherwise specified:
OSCin = external square wave, from rail to rail;
OSCout = floating;
All I/O pins in input to VSS
TA=-40 to 85°C
Supply current is mainly a function of the operating
voltage and frequency. Other factors such as I/O
pin loading and switching rate, oscillator type,
internal code execution pattern and temperature,
also have an impact on the current consumption.
Table 16.5 Supply Current in RUN, WAIT and SLOW Mode, 5,5 V supply voltage 5)
.
3)
Symbol
Parameter
Conditions
Typ
Unit
Max
f
=1 Mhz
3.75
4.50
6.5
osc
f
=5 Mhz,
osc
1)
Supply current in RUN mode
f
=10 MHz
=20 MHz
osc
osc
f
10.90
4)
V
=5.5V
f
f
f
=10 MHz
DD
intosc
5.60
f
=1 Mhz
2.50
osc
mA
f
=5 MHz
2.85
4.00
5.55
osc
2)
I
Supply current in WAIT mode
DD
f
=10 MHz
=20 MHz
osc
osc
f
4)
=10 MHz
intosc
2.70
f
=1 Mhz
3.70
4.25
5.20
8.10
osc
V
=5.5V
f
=5 MHz
osc
DD
3)
Supply current in SLOW mode
f
=f
/64
CPU OSC
f
f
=10 MHz
=20 MHz
osc
osc
4)
=10 MHz
intosc
4.20
Notes:
1. CPU running with memory access, all I/O pins in input mode with a static value at VSS (no load), all pe-
ripherals switched off; clock input.
2. CPU in WAIT mode with all I/O pins in input mode with a static value at VSS (no load), all peripherals
switched off; clock input.
3. CPU running with memory access, all I/O pins in input mode with a static value at VSS (no load), all pe-
ripherals switched off; clock input, CPU clock frequency divided 64 times by using the related Configu-
ration Register.
4. Device driven by Internal oscillator at 10 MHz.
5. Not tested in production
112/137
ST52F510/F513/F514
Table 16.6 Supply Current in RUN, WAIT and SLOW Mode, 2.8 V supply voltage 5)
.
3)
Symbol
Parameter
Conditions
Typ
Unit
Max
f
=1 Mhz
2.60
3.50
5.00
9.10
osc
f
=5 Mhz,
osc
1)
Supply current in RUN mode
f
f
=10 MHz
=20 MHz
=10 MHz
osc
osc
4)
f
f
f
V
=2.8V
DD
intosc
5.00
f
=1 Mhz
1.80
2.20
2.70
4.10
osc
mA
f
=5 MHz
osc
2)
I
Supply current in WAIT mode
DD
f
=10 MHz
=20 MHz
osc
osc
f
4)
=10 MHz
intosc
2.40
f
=1 Mhz
2.45
2.85
4.20
6.35
osc
V
=2.8V
f
=5 MHz
osc
DD
3)
Supply current in SLOW mode
f
=f
/64
CPU OSC
f
f
=10 MHz
=20 MHz
osc
osc
4)
=10 MHz
intosc
3.65
Notes:
1. CPU running with memory access, all I/O pins in input mode with a static value at VSS (no load), all pe-
ripherals switched off; clock input.
2. CPU in WAIT mode with all I/O pins in input mode with a static value at VSS (no load), all peripherals
switched off; clock input.
3. CPU running with memory access, all I/O pins in input mode with a static value at VSS (no load), all pe-
ripherals switched off; clock input, CPU clock frequency divided 64 times by using the related Configu-
ration Register.
4. Device driven by Internal oscillator at 10 MHz.
5. Not tested in production.
Table 16.7 Supply Current in HALT Mode 2)
.
Symbol
Parameter
Conditions
VDD = 5.5 V
VDD = 2.8 V
Max
Unit
Typ
13.5
9.5
1)
I
µA
Supply current in HALT mode
DD
Notes:
1. All I/O pins in input mode with a static value at VSS (no load), PLVD switched off.
2. Not Tested in production
113/137
ST52F510/F513/F514
Figure 16.4 Typical IDD in RUN vs fosc
12
10.5
9
7.5
6
5MHz
10MHz
20MHz
1MHz
4.5
3
1.5
0
2.7
3.2
3.7
4.2
4.7
5.2
Vdd (V)
Figure 16.5 Typical IDD in WAIT vs fosc
6
4,5
3
5MHz
10MHz
20MHz
1MHz
1,5
0
2,7
3,2
3,7
4,2
4,7
5,2
Vdd (V)
114/137
ST52F510/F513/F514
16.5 Clock and Timing Characteristics
Operating Conditions: VDD=2.8 V to 5.5 V, TA=-40° to 85°C, unless otherwise specified. Values by design.
Table 16.8 General Timing Parameters
Symbol
Parameters
Test Condition
Min
Typ.
Max
Unit
f
Oscillator Frequency
1
20
MHz
osc
Minimum External
Interrupt Pulse Width
t
2
WINT
CPU
clock
cycle
Instruction time
4
8
16
28
t
INST
t
Interrupt reaction time
12
20
INT
16.6 Power on reset
Table 16.9 Power on reset
Symbol
Parameter
Conditions
Min
Typ
2.56
Max
Unit
1)
V
TA=25°C
TA=25°C
2.55
0.05
2.70
V
Power on reset
POR
2)
V
1000
V/s
V
Slope
DDslp
DD
1. Measured with VDD slope = 0.05 V/s. Internal Reset is released if VDD goes above VPOR. Notice that
there is not hysteresis on POR.
2. Suggested VDD slope for correct working of the device. Not tested in production.
115/137
ST52F510/F513/F514
16.7 Memory Characteristics
Operating Conditions: VDD=2.8 V to 5.5 V, TA=-40° to 85°C, unless otherwise specified.
Table 16.10 RAM and Registers
Symbol
Parameter
Conditions
Min.
Typ.
Max
Max
Unit
1)
V
VRM
PLVD disabled
V
Data retention mode
DDmin
Table 16.11 Flash Program/Data Memory
Symbol
Parameter
Conditions
Min.
Typ.
Unit
VDD = 2.8 V - 5.5 V
2)
2)
2.5
Programming time for 1/32 bytes
Virgin Flash
ISP mode
VDD = 2.8 V - 5.5 V
t
5
ms
prog
Programming time for 1/32 bytes
Programming time for 8 Kbytes
Not Virgin Flash
IAP mode
VDD = 2.8 V - 5.5 V
Fast Programming Mode
ISP mode
640
3)
t
TA=55°C
TA=25°C
10
years
cycle
Data retention
RET
N
Write/erase cycles
TBD
RW
Table 16.12 EEPROM Data Memory
Symbol
Parameter
Conditions
TA=25°C
TA=55°C
TA=25°C
Min.
Typ.
Max
Unit
ms
2)
t
5
prog
Programming time for 1/32 bytes
3)
t
10
years
cycle
Data retention
RET
N
Write/erase cycles
TBD
RW
Notes:
1. Minimum VDD supply voltage that avoids the loosing of data stored into RAM or into hardware registers.
Below the specified threshold the device is turned off and it is turned on only after the VDD goes above
the POR threshold, as consequence the device is reset by the POR and the RAM is put to all 0. Guar-
anteed by design, not tested in production.
2. Flash/EEPROM can be programmed at signle byte or at 32 bytes blocks. In working mode (In Applica-
tion Programming) the time includes the erase operation before the writing.
3. The data retention time increases when the TA decreases.
4. Not tested in production, guaranteed by design.
116/137
ST52F510/F513/F514
16.8 Programmable Low Voltage Detector (PLVD)
Operating Conditions: VDD=2.8 V to 5.5 V, TA= 25°C, unless otherwise specified.
Symbol
Parameter
Conditions
High Threshold
Medium Threshold
Low Threshold
High Threshold
Medium Threshold
Low Threshold
Min
4.18
3.64
3.05
3.83
3.30
2.77
Typ
4.22
3.70
3.11
3.96
3.40
2.85
Max
4.33
3.76
3.15
3.96
3.46
2.87
Unit
Reset release threshold
V
LVDT+
1)
(V rise)
DD
V
Reset threshold
V
LVDT-
1)
(V fall)
DD
Int.
clock
cycle
2)
t
Not detected by the PLVD
50
Filtered glitch on V
g
DD
Notes:
1. Measured with VDD slope in the range from 0.2 V/s to 4000 V/s .
2. Duration of the glitch not detected by the PLVD. Values by design, not tested in production.
16.9 Internal oscillator
The frequency of the internal oscillator is centered at 10 MHz but can be subject to variation due to process
spread: this may be calibrated by using the related option byte.
Operating Conditions: VDD=2.8 V to 5.5 V, TA=-40° to 85°C, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
TA= 25°C, VDD =5.5 V
f
Internal operating frequency
10
MHz
oscint
Not calibrated
TA=-40°C
TA=0°C
12
3
Thermal drift of the internal
Thdr
%
osc
1)
oscillator
TA=85°C
TA=25°C
2
f
Step of calibration
100
kHz
cal
Notes:
1. Drift values in temperature are referred to TA=25° C internal oscillator frequency value.
117/137
ST52F510/F513/F514
16.10 Port Pin Characteristics
16.10.1 General Characteristics
Operating Conditions: VDD=2.8 V to 5.5 V, TA=-40° to 85°C, unless otherwise specified.
1)
Symbol
Parameter
Condition
Min
Max
Unit
Typ
1.2
1.7
0.5
2)
V
Input low level voltage
IL
2)
V
V
Input high level voltage
IH
3)
V
Schmitt trigger voltage hysteresis
hys
2)
I
V
≤V ≤V
DD
1
µA
kΩ
Input leakage current
L
SS
IN
4)
R
V
= 2.8 V to 5.5 V
13.6
15.5
31.5
Internal Pull-up resistor
PU
DD
5)
R
Input protection resistor
0.3
5
S
5)
t
Output high to low level fall time
Output low to high level rise time
f(IO)out
C = 50 pF
between 10% and 90%
L
ns
5)
t
5
r(IO)out
CPU
clock
cycle
5)
t
2
External interrupt pulse time
w(IT)in
Notes:
1. Typical data are based on TA=25 °C and VDD=5.5 V
2. Data from Characterization. Not tested in production.
3. Hysteresis voltage between Schmitt trigger switching level. Data by design.
4. Values of the Pull-up resistrors depends on V (see Figure 16.7).
DD
5. Data based on design simulation and/or technology characteristics, not tested in production.
Figure 16.6 Level input Schmitt Trigger 5)
Figure 16.7 Internal Pull-up resistor Vs Vdd 5)
R Pull UP @ T=25ºC
R Pull UP (K Ohm)
5
4
28
26
24
22
20
18
16
14
12
10
V = 5V
DD
V (V)
o
TA = 25°C
3
2
1
(TYPICAL)
2,7
3,2
3,7
4,2
4,7
5,2
0
0.5
1.5
1.7
2.5
1.2
Vdd (V)
V (V)
i
118/137
ST52F510/F513/F514
Figure 16.8 Port pin Equivalent Circuit
16.10.2 Output Driving Current
Operating Conditions: VDD=2.8 V to 5.5 V, TA=25°C, unless otherwise specified.
Table 16.13 Output Voltage Levels for class A pins3)
Symbol
Parameter
Conditions
=+8mA
Min
Typ
Max
Unit
I
Output low level voltage for standard I/O
pin when 8 pins are sunk at same time.
IO
1)
0.41
0.43
V
OL
V
= 2.8 V
DD
V
I
=- 8mA
= 2.8 V
Output high level voltage for standard I/O
pin when 8 pins are sourced at same time.
IO
2)
2.33
2.35
V
OH
V
DD
Table 16.14 Output Voltage Levels for class B pins3)
Symbol
Parameter
Conditions
=+4mA
Min
Typ
Max
Unit
I
Output low level voltage for standard I/O
pin when 8 pins are sunk at same time.
IO
1)
0.25
0.33
V
OL
V
= 2.8 V
DD
V
I
=- 4mA
= 2.8 V
Output high level voltage for standard I/O
pin when 8 pins are sourced at same time.
IO
2)
2.42
2.45
V
OH
V
DD
Notes:
1. The IIO sunk current must always respect the absolute maximum rating specified in Section 16.2 and
the sum of IIO (I/O ports and control pins) must not exceed IVSS. Data from characterization; not tested
in production.
2. The IIO sourced current must always respect the absolute maximum rating specified in Section 16.2 and
the sum of IIO (I/O ports and control pins) must not exceed IVDD. Data from characterization; not tested
in production.
3. Class A indicates an 8 mA driving capability of the output buffer while Class B indicates a 4 mA driving
capability of the output buffer. See General Description chapter for a complete description of class A
and B pins for every package.
119/137
ST52F510/F513/F514
16.11 Control Pins Characteristics
16.11.1 RESET pin.
Operating Conditions: VDD=2.8 V to 5.5 V, TA=25°C, unless otherwise specified.
Table 16.15 Reset pin
Symbol
Parameter
Conditions
Min
Typ
1.18
2.34
1.63
3.22
0.45
100
Max
Unit
V
V
V
V
V
= 2.8 V
= 5.5 V
= 2.8 V
= 5.5 V
= 2.8 V
DD
DD
DD
DD
DD
1)
V
Input low level voltage
IL
V
1)
V
IH
Input high level voltage
2)
V
t
Schmitt trigger voltage hysteresis
hys
3)
FN
Duration of noise
ns
1)
t
500
Reset pulse duration
RST
4)
R
V
= 2.8 V to 5.5 V
13.9
15.8
29.7
kΩ
Pull-up resistor
PURES
DD
Notes:
1. Data by design, not tested in production.
2. Hysteresis voltage between Schmitt trigger switching level. Based on simulation results not tested in
production.
3. Max duration of the noise that is filtered by the pin. Data by design, not tested in production.
4. Measures at TA=-40°C to 85°C, typical data are based on TA=25 °C and VDD=5.5 V. Values of the Pull-
up resistors depends on V
.
DD
16.11.2 VPP pin.
Operating Conditions: VDD=2.8 V to 5.5 V, TA=25°C, unless otherwise specified.
Table 16.16 VPP1) pin
Symbol
Parameter
Conditions
Min
Typ
1.18
2.34
1.63
3.22
Max
Unit
V
V
V
V
= 2.8 V
= 5.5 V
= 2.8 V
= 5.5 V
DD
DD
DD
DD
2)
V
Input low level voltage
IL
V
2)
V
Input high level voltage
IH
Notes:
1. In working mode VPP must be tied to VSS
2. Data is based on design simulations, not tested in production.
120/137
ST52F510/F513/F514
16.12 EMC Characteristics
Susceptibility tests are performed on a sample
basis during product characterization.
I ESD: Electro-Static Discharge (positive and
negative) is applied on all pins of the device until
a functional disturbance occurs. This test
conforms with the IEC 1000-4-2 standard.
16.12.1 Functional EMS . (Electro
Susceptibility)
Based on a simple running application on the
product (toggling two LEDs through I/O ports), the
product is stressed by two electromagnetic events
until a failure occurs (indicated by the LEDs).
Magnetic
I FTB: A burst of Fast Transient Voltage (positive
and negative) is applied to VDD and VSS through
a 100 pF capacitor, until a functional disturbance
occurs. This test conforms with the IEC 1000-4-
4 standard.
A device reset allows normal operation to be
resumed.
Symbol
Parameter
Conditions
Level/Class
V
V
=5 V, T =25°C, f = 8 MHz SDIP32
Voltage limits to be applied on any I/O
pin to induce a functional disturbance
DD
osc
A
V
2B
FESD
conform with IEC 1000-4-2
Fast transient voltage burst limits to be
applied through 100 pF on V and V
SS
=5 V, T =25°C, f = 8 MHz SDIP32
DD
osc
A
V
3B
FFTB
DD
conform with IEC 1000-4-4
pins to induce a functional disturbance
Notes:
1. Data based on characterization results, not tested in production.
2. It is suggested to insert decoupling capacitors (10 nF and 100 nF electrolytic) on the power supply lines
to obtain a good price vs. EMC performance tradeoff. They have to be put as close as possible to the
device power supply pins.
16.12.2 Absolute Electrical Sensitivity. Based
on three different tests (ESD, LU and DLU) using
specific measurement methods, the product is
stressed in order to determine its performance in
terms of electrical sensitivity.
16.12.3 Electro-Static Discharge (ESD).
Electro-Static Discharges (3 positive then 3 nega-
tive pulses separated by 1 second) are applied to
the pins of each sample according to each
pincombination. The sample size depends of the
number of supply pins of the device (3 parts*(n+1)
supply pin). The model imulated is the Human
Body Model. This test conforms to the JESD22-
A114A/A115A standard. See Figure 16.9.
1)
Symbol
Parameter
Conditions
Unit
Maximum value
Electro-static discharge voltage
(Human Body Model)
V
TA=25°C
2
kV
ESD(HBM)
Figure 16.9 Typical Equivalent ESD Circuits
S1
R = 1500 Ω
HIGH VOLTAGE
S2
ST FIVE
PULSE
CL = 100 pF
GENERATOR
HUMAN BODY MODEL
121/137
ST52F510/F513/F514
16.12.4 Static and Dynamic Latch-up.
I DLU: Electro-Static Discharges (one positive
then one negative test) are applied to each pin
of 3 samples when the micro is running to
assess the latch-up performance in dynamic
mode. Power supplies are set to the typical
values, the oscillator is connected as near as
possible to the pins of the micro and the
component is put in reset mode. This test
conforms to the IEC1000-4-2 and SAEJ1752/3
standards and is described in Figure 16.10.
I LU: 3 complementary static tests are required
on 10 parts to assess the latch-up performance.
A supply overvoltage (applied to each power
supply pin), a current injection (applied to each
input, output and configurable I/O pin) and a
power supply switch sequence are performed on
each sample. This test conforms to the EIA/
JESD 78 IC latch-up standard.
1)
Symbol
LU
Parameter
Static latch-up class
Dynamic latch-up class
Conditions
TA=25°C
TA=85°C
Class
A
A
DLU
V
=5.5V, f
= 8 MHz, T =25°C
A
DD
OSC
A
Figure 16.10 Simplified Diagram of the ESD Generator for DLU
RCH= 50 MΩ
RD= 330 Ω
DISCHARGE TIP
VDD
VSS
CS= 150 pF
HV RELAY
ST FIVE
ESD
GENERATOR
DISCHARGE
RETURN CONNECTION
Notes:
1. Class description: Class A is an STMicroelectronics internal specification. All its limits are higher than
the JEDEC specification, that means when a device belongs to Class A it exceeds the JEDEC standard.
Class B strictly covers all the JEDEC criteria (international standard).
16.12.5 ESD Pin Protection Strategy. In order
to protect an integrated circuit against Electro-
Static Discharge the stress must be controlled to
prevent degradation or destruction of the circuit
elements. Stress generally affects the circuit
elements, which are connected to the pads but can
also affect the internal devices when the supply
pads receive the stress. The elements that are to
be protected must not receive excessive current,
voltage, or heating within their structure.
An ESD network combines the different input and
output protections. This network works by allowing
safe discharge paths for the pins subject to ESD
stress. Two critical ESD stress cases are
presented in Figure 16.11 and Figure 16.12 for
standard pins.
Standard Pin Protection
In order to protect the output structure the following
elements are added:
- A diode to VDD (3a) and a diode from VSS (3b)
- A protection device between VDD and VSS (4)
In order protect the input structure the following
elements are added:
- A resistor in series with pad (1)
- A diode to VDD (2a) and a diode from VSS (2b)
- A protection device between VDD and VSS (4)
122/137
ST52F510/F513/F514
Figure 16.11 Safe discharge path subjected to ESD stress
VDD
VDD
(3a)
(2a)
(1)
OUT
(4)
IN
Main path
Path to avoid
(3b)
(2b)
VSS
VSS
Figure 16.12 Negative Stress on a Standard Pad vs. VDD
VDD
VDD
(3a)
(2a)
(1)
OUT
(4)
IN
Main path
(3b)
(2b)
VSS
VSS
123/137
ST52F510/F513/F514
16.13 I2C Interface Characteristics
Subject to general operating conditions for VDD,
fosc, and TA, unless otherwise specified.
Refer to I/O port characteristics for more details on
the input/output alternate function characteristics
(SDA and SCL). The I2C interface meets the
requirements of the Standard I2C communication
protocol described in the following table.
Table 16.17 I2C Interface Characteristics
2
2
Standard mode I C
Fast mode I C
Symbol
Parameter
Unit
1)
1)
1)
1)
Min
Max
Min
Max
t
SCL clock low time
4.7
4.0
250
1.3
0.6
100
w(SCLL)
µs
t
SCL clock high time
SDA setup time
w(SCLH)
t
su(SDA)
3)
2)
3)
t
SDA data hold time
0
0
900
h(SDA)
t
t
r(SDA)
ns
20+0.1C
20+0.1C
SDA and SCL rise time
SDA and SCL fall time
1000
300
300
300
b
b
r(SCL)
t
t
f(SDA)
f(SCL)
t
START condition hold time
4.0
4.7
4.0
4.7
0.6
0.6
0.6
1.3
h(STA)
µs
t
Repeated START condition setup time
STOP condition setup time
su(STA)
t
ns
ms
pF
su(STO)
t
STOP to START condition time (bus free)
Capacitive load for each bus line
w(STO:STA)
C
400
400
b
Figure 16.13 I2C Bus and Timing Diagram 4)
Notes:
1. Data based on standard I2C protocol requirements, not tested in production.
2. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the
undefinited region of the falling edge of SCL.
3. The maximum hold time of the START condition has only to be met if the interface does not stretch the
low period of the SCL signal.
4. Measurement points are done at levels: 0.3xVDD and 0.7xVDD
.
124/137
ST52F510/F513/F514
16.14 SPI Characteristics
Subject to general operating conditions for VDD,
fosc, and TA, unless otherwise specified.
Refer to I/O port characteristics for more details on
the input/output alternate function characteristics
(SS, SCK, MOSI, MISO ).
Symbol
Parameter
SPI clock frequency
Condition
Min
/128
Max
Unit
f
f
f
/4
Master
Slave
CPU
CPU
CPU
f
MHz
SCK
/4
0
t
t
r(SCK)
SPI clock rise and fall time
see I/O port pin description
f(SCK)
t
SS setup time
SS hold time
Slave
Slave
120
120
su(SS)
t
h(SS)
t
t
Master
Slave
100
90
w(SCKH)
SCK high and low time
Data input setup time
Data input hold time
w(SCKL)
t
Master
Slave
100
100
su(MI)
t
su(SI)
ns
t
Master
Slave
100
100
h(MI)
t
h(SI)
t
Slave
Slave
0
120
240
120
Data output access time
Data output disable time
Data output valid time
Data output hold time
Data output valid time
Data output hold time
a(SO)
t
dis(SO)
t
v(SO)
Slave (after enable edge)
t
0
h(SO)
t
0.25
0.25
v(MO)
CLK
cycle
Master (before capture edge)
t
h(MO)
Figure 16.14 SPI Slave Timing Diagram with CPHA = 0 3)
Notes:
1. Data based on design simulation and/or characterisation results, not tested in production.
2. When the SPI is disabled it has its alternate function capability released. In this case, the pin status de-
pends on the I/O port configuration.
3. Measurement points are done at levels: 0.3xVDD and 0.7xVDD
.
125/137
ST52F510/F513/F514
Figure 16.15 SPI Slave Timing Diagram with CPHA = 0 3)
Figure 16.16 SPI Master Timing Diagram
Notes:
1. Measurement points are done at levels: 0.3xVDD and 0.7xVDD
.
2. When the SPI is disabled it has its alternate function capability released. In this case, the pin status de-
pends on the I/O port configuration.
126/137
ST52F510/F513/F514
16.15 10-BIT ADC CHARACTERISTICS
Operating Conditions: VDD=2.8 V to 5.5 V, TA=-40° to 85°C, unless otherwise specified.
1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Min=slow mode Max=fast
mode, TA=25°
f
ADC clock frequency
f
/12
f
/ 6
MHz
ADC
oscint
oscint
2)
V
External reference voltage
External input resistor
Internal input resistor
V
V
DD
V
Ω
REF
SS
3)
R
400
AIN
R
C
t
1.0
kΩ
pF
µs
ns
µs
µs
ns
µs
ADC
ADC
Internal sample and hold capacitor
Stabilization time after ADC enable
Sample capacitor loading time
Conversion time
9
4)
400
STAB
LOAD
t
Slow mode = 800 kHz
Fast mode = 1600 kHz
600
20
t
CONV
4)
t
Stabilization time after ADC enable
Sample capacitor loading time
Conversion time
200
STAB
LOAD
CONV
t
600
10
t
Notes:
1. Data by design. They are given only as design guidelines and are not tested.
2. When V is selected as Internal it corresponds to V . When Vref is External it must be <= V
and >=V , and
SS
REF
DD
DD
Channel 0 cannot be used because AIN0 pin is the Input for V
.
REF
3. Any added external serial resistor will downgrade the ADC accuracy. Data by design, not tested in production.
4. Approximated value corresponding to about 20 conversion cycles, that is recommended at A/D start-up to ensure a
correct conversion.
Table 16.18 ADC Accuracy with VDD=5.0 V
Symbol
Parameter
Conditions
Typ
4.5
1
Max
Unit
1)
|E |
Total unadjusted error
T
1)
E
Offset error
1.8
5
VDD=5V, TA=-40° to 85°C
Typical values at TA=25°C
O
LSB
1)
|E |
Gain Error
3
G
1)
|E |
Differential linearity error
2.5
3.5
D
Notes:
1. Data based on characterization results over the whole temperature range, monitored in production.
127/137
ST52F510/F513/F514
Figure 16.17 ADC Accuracy Characteristics
Digital Result ADCDR
E
G
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line
1023
V
– V
1022
1021
REF
SS
1LSB
= -----------------------------------
IDEAL
1024
(2)
E =Total Unadjusted Error: maximum deviation
T
E
between the actual and the ideal transfer curves.
T
(3)
7
6
5
4
3
2
1
E =Offset Error: deviation between the first actual
O
(1)
transition and the first ideal one.
E =Gain Error: deviation between the last ideal
G
transition and the last actual one.
E
E
O
L
E =Differential Linearity Error: maximum deviation
D
between actual steps and the ideal one.
E =Integral Linearity Error: maximum deviation
L
E
between any actual transition and the end point
correlation line.
D
1 LSB
IDEAL
V
(LSB
)
IDEAL
in
0
1
2
3
4
5
6
7
1021 1022 1023 1024
V
V
DDA
SSA
128/137
ST52F510/F513/F514
17 PACKAGE CHARACTERISTICS
17.1 SO16 Package Data
Table 17.1 SO16 PACKAGE MECHANICAL DATA
mm
inch.
DIM
MIN
2.35
0.10
0.33
0.23
10.10
7.40
10.00
TYP.
MAX
2.65
0.30
0.51
0.32
10.50
7.60
10.65
MIN
TYP.
MAX
0.104
0.012
0.020
0.013
0.413
0.299
0.419
A
A1
B
C
D
E
H
e
0.093
0.004
0.013
0.009
0.398
0.291
0.394
1.27
0.050
h
0.25
0°
0.75
8°
0.010
0°
0.030
8°
α
L
0.40
1.27
0.016
0.050
Number of pins
N
16
D
h x 45×
L
A
C
A1
a
e
B
H
E
129/137
ST52F510/F513/F514
17.2 SO20 Package Data
Table 17.2 SO20 PACKAGE MECHANICAL DATA
mm
inch.
TYP.
DIM
MIN
2.35
0.1
TYP.
MAX
2.65
0.3
MIN
MAX
0.104
0.012
0.020
0.013
0.512
0.299
A
A1
B
C
D
E
e
0.093
0.004
0.013
0.009
0.496
0.291
0.33
0.23
12.6
7.4
0.51
0.32
13
7.6
1.27
0.050
H
h
10
0.25
0.4
0°
10.65
0.75
1.27
8°
0.394
0.010
0.016
0°
0.419
0.030
0.050
8°
L
α
D
h x 45×
L
A
c
A1
α
e
B
E
H
130/137
ST52F510/F513/F514
17.3 PDIP20 Package Data
Table 17.3 PDIP20 PACKAGE MECHANICAL DATA
mm
inch.
DIM
MIN
TYP.
MAX
MIN
TYP.
MAX
A
A1
A2
b
5.33
0.210
0.38
2.92
0.36
1.14
0.20
24.89
0.13
0.015
0.115
0.014
0.045
0.008
0.980
0.005
3.30
0.46
1.52
0.25
26.16
4.95
0.56
1.78
0.36
26.92
0.130
0.018
0.060
0.010
1.030
0.195
0.022
0.070
0.014
1.060
b2
c
D
D1
e
2.54
0.100
eB
E1
L
10.92
7.11
0.430
0.280
0.150
6.10
2.92
6.35
3.30
0.240
0.115
0.250
0.130
3.81
Number of Pins
20
N
A2
A1
A
L
c
b
eB
b2
e
D
20
1
11
E1
10
131/137
ST52F510/F513/F514
17.4 SO28 Package Data
Table 17.4 SO28 PACKAGE MECHANICAL DATA
mm
inch.
TYP.
DIM
MIN
2.35
0.10
0.33
0.23
17.70
7.40
TYP.
MAX
2.65
0.30
0.51
0.32
18.10
7.60
MIN
MAX
0.104
0.012
0.020
0.013
0.713
0.299
A
A1
B
C
D
E
e
0.093
0.004
0.013
0.009
0.697
0.291
1.27
0.050
H
h
10.00
0.25
0°
10.65
0.75
8°
0.394
0.010
0°
0.419
0.030
8°
α
L
0.40
1.27
0.016
0.050
Number of Pins
N
28
D
h x 45×
L
A
C
A1
α
e
B
E
H
132/137
ST52F510/F513/F514
17.5 SDIP32 Package Data
Table 17.5 SDIP32 PACKAGE MECHANICAL DATA
mm
inch.
DIM
MIN
3.56
0.51
3.05
0.36
0.76
0.20
27.43
9.91
7.62
TYP.
MAX
MIN
TYP.
MAX
A
A1
A2
b
3.76
5.08
0.140
0.020
0.120
0.014
0.030
0.008
1.080
0.390
0.300
0.148
0.200
3.56
0.46
4.57
0.58
1.40
0.36
28.45
11.05
9.40
0.140
0.018
0.040
0.010
1.100
0.410
0.350
0.070
0.400
0.180
0.023
0.055
0.014
1.120
0.435
0.370
b1
C
1.02
0.25
D
27.94
10.41
8.89
E
E1
e
1.78
eA
eB
eC
L
10.16
12.70
1.40
3.81
0.500
0.055
0.150
2.54
3.05
0.100
0.120
N
32
E
eC
A2
A
A1
L
E1
C
eA
eB
b
b2
e
D
133/137
ST52F510/F513/F514
17.6 LFBGA36 Package Data
Table 17.6 LFBGA36 PACKAGE MECHANICAL DATA
mm
inch.
TYP.
DIM
MIN
TYP.
MAX
MIN
0.048
0.011
MAX
A
A1
A2
b
1.210
0.270
1.700
0.067
1.120
0.500
6.000
4.000
6.000
4.000
0.800
1.000
0.044
0.020
0.236
0.157
0.236
0.157
0.031
0.039
0.450
5.750
0.550
6.150
0.018
0.226
0.022
0.242
D
D1
E
5.750
6.150
0.226
0.242
E1
e
0.720
0.850
0.880
1.150
0.120
0.028
0.033
0.035
0.045
0.005
f
ddd
134/137
ST52F510/F513/F514
18 IMPORTANT NOTES
18.2.3 SCI synchronization in case of consecu-
tive bytes reception.
Description.
The SCI looses synchronization in data reception
when two bytes are received consecutively,
without an idle time of at least 3/16 of bit time (3
SCI CLOCK_RX cycles).
18.1 SILICON IDENTIFICATION
This document describes the limitations that apply
to ST52F510/F513/F514 devices, silicon revision
U.
This is identifiable on:
Device package, by the last letter of Trace Code
marked on device package.
On the box, by the last 3 digits of the Internal
Sales Type printed on the box label.
Workaround.
To avoid lost of synchronization when two
consecutive bytes are received by the SCI, an idle
time corresponding to 3 CLOCK_RX cycles must
be guaranteed between the stop bit of each byte
and the start bit of the successive byte by the
Transmitter device.
As an implementation suggestion, this can be
achieved by configuring the external Transmitter
device with 2 Stop bits and the ST5 SCI configured
as a receiver with 1 Stop bit.
Trace Code
Internal Sales Type on
Part Number marked on
box label
device
52F51yxxxx$Uz
52F51yxxxx$A3
ST52F51yxxxx
“xxxxxxxxxU”
Legend: y= 0,3,4; z= 3,4,5
18.2.4 I2C GENERAL CALL flag.
18.2 SILICON LIMITATIONS
Description.
The General Call Flag, Bit0 on I2C Status
Register 2 (I2C_SR2) [Input Register 8 (08h)] is
not reset if a second Start condition occurs without
a Stop condition or if the peripheral is not disabled
setting to zero Bit5, PE Peripheral enable, on I2C
Control Register (I2C_CR) [Configuration
Register 16 (010h)].
18.2.1 EEPROM writing error flag.
Description
When an instruction for writing data ("lder") is
located in a write protected page, (clearly to write
data in an unprotected page of Program/Data
Memory) the writing error flag Bit 1: PRTCD Page
Protected of IAP Status Register (IAP_SR) [Input
Register 40 (028h)] is always set even if the writing
is successful.
Workaround.
None. The user has to guarantee that every
communication (start condition) ends with a stop
condition.
Workaround
Once the PRTCD bit is set it is anyway possible to
verify the correct writing of a data byte reading the
target location with the instruction "ldre" and
comparing it with the data byte intended to store.
18.2.5 HALT not skipped.
Description.
When the Hardware WDT is enabled, if HALT
instruction is preceded by wdtslp instruction or if
none of wdtslp and wdtrfr instruction occurred, Halt
is not skipped.
Workaround.
The user should avoid using HALT instruction
when hardware WatchDog is used.
18.2.2 CPU Prescaler after RESET.
Description
The Reset caused by the Watchdog does not reset
the CPU Prescaler Configuration Register
CPL_CLK [Configuration Register 46 (02Eh)] so
the CPU continues to run with the frequency used
before the reset.
Workaround
Software workaround can be used: if the user
thinks that a Watchdog Reset is possible, he
should take care of writing the CPU Prescaler
Configuration Register as first instruction after a
WDG reset.
135/137
ST52F510/F513/F514
19 REVISION HISTORY
Table 19.1
Date
Revision
Description of Changes
Table 4.1 Sales Type Memory Organization on page 34 modified
Table 4.3 Error codes on page 40 modified
Section 5.6 Register Description on page 45 High Priority Register
(INT_PRL_H) (PRL24-PRL0) became (PRL23-PRL0)
Section 12.6.2 PWM/Timer 1 Input Registers on page 81 PWM/Timer 1
Status Register (PWM1_STATUS) bit description modified
Section 13.4.3 SCI Output Register on page 88 row 2 “input register”
became “output register”
Section 14.3.2 Communication Flow on page 89 small modifications
Table in Section 16.12.1 Functional EMS on page 121 changed, Note 2
eliminated
April 04
2.1
Section 16.12.3 Electro-Static Discharge (ESD) on page 121 changed
Table in Section 16.12.3 Electro-Static Discharge (ESD) on page 121
changed
Figure 16.9 Typical Equivalent ESD Circuits on page 121 modified
Chapter 18 IMPORTANT NOTES on page 135 added
Chapter 19 REVISION HISTORY on page 136 added
Figure 3.2 Program/Data Memory Organization on page 25 modified
Section 12.5.1 PWM/Timer 0 Configuration Registers on page 77
modified (STRMOD, RESMOD, RESPOL) description
April 04
May 04
2.2
2.3
All hyperlink coloured in blue
Document pagination modified
All references to RC external oscillator removed
Section 14.5.2 I2C Interface Input Registers on page 96 “Bit 4: BUSY
Bus busy” modified. “Bit 1: BERR Bus error” added note
136/137
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