ST52T301P_技术文档

ST52T301/E301

8-Bit OTP/EPROM DuaLogic MCUs WITH ADC,

UART, TIMER, TRIAC & PWM DRIVER

ADVANCED DATA SHEET

High Speed dedicatedstructuresforFuzzyLogic

(3.5 s to compute a 4 In x 1 Outrule)

µ

Capability to perform simple boolean and

arithmetic operations

Up to4 Input,2OutputConfigurableVariablesfor

each Fuzzy Algorithm and up to 300 Rules

Up to16 Triangularand TrapezoidalMembership

Functions for each Input variable

CLCC44-W

Up to 256 Singleton Membership Functions for

all Consequents

Program and Data EPROM: 2 Kbytes

16 general purpose registers available as

Register File

PLCC44

Working Clock Frequencies:5, 10 and 20MHz

On-Chip Clock Oscillator driven by Quartz

Crystal or Ceramic Resonator

One external interrupt

1.1 GENERAL DESCRIPTION

Standard TTL compatibleinput

CMOS compatible output

(1)

ST52E301

and ST52T301

devices are

DuaLogic

membersof the W.A.R.P.familyof 8-bit

microcontrollers. They are able to perform, in an

efficientway,both booleanand fuzzyalgorithms,in

order to reach the best performancesthat the two

methodologiesallow.

4 channel 8 bit Analog to Digital Converter

Bandgap reference 2.5V

Digital 8 bit I/O port indepedentlyprogrammable

with handshakesignal

TheST52E301is theerasableEPROMversionand

the ST52T301 is the OTP version.

Serial Communication Interface with

asynchronousprotocol (UART)

The ST52x301 is completely developed and

producedby STMicroelectronics using the reliable

high performance CMOSM5E (O.7µm) process.

ProgrammableTimer with internal Prescaler

Thanks to Fuzzy Logic, ST52x301 allows to

describea problemusing alinguisticmodelinstead

ofa mathematicalmodel.In thisway it is veryuseful

and easy to modelize complex system with very

high accuracy.

Internal Power Fuzzy Control to drive external

Triac (up to 25mA source, 50 mA sink current)

Internal Fuzzy controlled PWM to drive an

external power device

The linguistic approach is based on a set of

IF-THEN rules, describing the control behaviour,

and on Membership Functions associated to input

and output variables.

Software tools and Emulators availability

Windowed and One Time Programmable (OTP)

Memory parts available for prototyping and

production phases

Fuzzy Inference is a set of operations which

computes the output values according with the

truth values of the involvedrules.

44 pinPlastic(PLCC44) and Ceramic Windowed

Leaded Chip Carrier (CLCC44-W)

July 1998

1/99

Note: (1) Formerly W.A.R.P.3TC

ST52T301/E301

Figure 1. ST52x301 Architectural Block Diagram

ALU

-

FUZZY

REGISTER

FILE

CONTROL

UNIT

SYSTEM

REGISTERS

CORE

OSCILLATO R

A/D

CONVERTER

PROG.TIMER

WITH

PRESCALER

PARALLEL

I/O PORT

2kBytes

EPROM

TRIAC/PWM

DRIVER

BAND-GAP

REFERENCE

SCI

The flexible I/O configuration of ST52x301 allows

to interface with a wide range of external devices,

like D/A converters, power control devices (SCRs,

TRIACs) and external sensors.

channel fast multiplexer (32µs conversion

time/channel).

It is possibleto perform operations on data stored

in the Register File (16 bytes),allowing to manage

new inputs and feedbackoutputs.

TheOTP (OneTime Programmable) deviceis fully

compatible with the EPROM windowed version,

which may be used to create prototype systems

and for the pre-production phases.

The TRIAC/PWM Driver peripheral allows to

manage directly power devices, implementing

three different operating modes: Burst Mode

(i.e.Thermal Applications), Phase Angle

Partialization (i.e. Motors Control by TRIACs) and

high frequency PWM controls.

The Fuzzy Core includes the fuzzifier (ALPHA

calculator), the inferenceunit and the defuzzifier.

It allows to manage upto 300 Rules(4 Inputs and

1 Output).The rules could be shared in different

fuzzy subroutines that can be activated by user

defined conditions.

A programmable Timer with Internal Prescaler,

using both internal or external clock, is available.

The microcontroller configuration is stored in the

internal EPROM.

The I/O capabilities, demanded from

microcontroller applications, are fulfilled by

ST52x301with 4 Analog Inputs, an asynchronous

Peripheral interface (UART) and an 8-bit I/O

communicationport inorderto transferdatafrom/to

the on-chip Register File.

A

powerful development environment,

FUZZYSTUDIO 3.0, consisting of a board

an d s of twa re t ool s, a ll ow s an easy

configuration and use of ST52x301.

ST 52 x3 0 1 i s f u l l y s up po r t ed b y

FUZZYSTUDIO3.0 software tools allowing

to graphically design a project and obtain an

optimized microcode.

The voltage reference provides biasing to the

analog portion of the internal circuitry. Theinternal

referenceis a 2.5V Bandgapreference.

ST52x301 exploits a SGS-THOMSON patented

strategy to store the MFs in its internal memory.

The voltage reference can supply up to 0.1 mA of

current to power external circuitry.

ST52x301 includes an 8-bit sampling Analog to

Digital (A/D) Converter with a 4 analog

2/99

ST52T301/E301

Figure 2. CLCC44-W Pin Configuration

Figure 3. PLCC44 Pin Configuration

3/99

ST52T301/E301

Table 1. PLCC44 and CLCC44-W Pin Configuration

1

NAME

not connected

AV_DD

TYPE

Programming Phase

-

Working Phase

-

2

Analog V_DD

3

AV_SS

Analog Ground

4

EV_DD

EPROM Digital Power Supply

EPROM Digital Ground

EPROM Programming

EPROM Digital Power Supply

EPROM Digital Ground

5

EV_SS

6

V_PP

EPROM V_DD(5V ±10%)

Power supply (12V

±5%)

7

V_DD

V_SS

Digital Power Supply

Digital Ground

Digital Power Supply

Digital Ground

Digital I/O

8

9

P0

I/O

O

I/O EPROM Data

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

P1

Digital I/O

P2

Digital I/O

P3

Digital I/O

P4

Digital I/O

P5

Digital I/O

P6

Digital I/O

P7

Digital I/O

READY

P8

I/O port Handshaking Signal

Digital Output

O

TEST

MAIN2

MAIN1

V_DD

I

(must be set to 0)

Zero Crossing/Prescaler Output

Zero Crossing

Digital Power Supply

Digital Ground

Triac/PWM Driver Output Pulses

Functionment Mode Selector

General Reset

External Interrupt

Output Timer

I/O

I

Digital Power Supply

Digital Ground

V_SS

TRIACOUT

MODE

RESET

CE/INT

TIMEROUT

ERES / TRES

OE / TCTRL

OSCout

OSCin

CADD / TCLK

V_SS

O

I

Functionment Mode Selector

General Reset

I

Chip Enable EPROM

O

I

EPROM Address Counter Reset

EPROM Output Enable

Oscillator Output

External TimerReset

Timer Start/Stop Signal

Oscillator Output

Oscillator Input

Timer External Clock

Digital Ground

Digital Power Supply

SCI Output

I

I/O

I

Oscillator Input

EPROM Change Address Clock

Digital Ground

V_DD

Digital Power Supply

TxD

O

I

RxD

SCI Input

not connected

AIN3

-

Ainp

Aout

Analog Input

AIN2

Analog Input

AIN1

Analog Input

AIN0

Analog Input

BG

Band Gap Output

4/99

ST52T301/E301

1.2 PIN DESCRIPTION

V_DD,EV_DD,V_SSEV_SS,AV_DD, AV_SS,V_PP

avoid noise disturbances, the power supply of the

digitalpart is keptseparatedfrom the powersupply

of the analog part.

RxD

. Serial data input of the SCI receiver

block.

.

,

In order to

TRES,TCLK,TCTRL, TIMEROUT.These pins are

related with the internal Programmable Timer.The

Timer can be reset externally by using TRES. In

Working Mode, TRES resets the address counter

of the Timer.TRES is active at low level

The Timer Clock can be the internal clock or can

be supplied externally by using the pin TCLK.

AnexternalStart/Stopsignalcan beusedtocontrol

theTimer throughthe pinTCTRL.TheTimeroutput

is available on the pin TIMEROUT.

V_DD.Main Power Supply Voltage (5V 10%).

V_SS. Digital circuit Ground.

EV_DD.EPROM Main Power Supply Voltage (5V

10%).

EV

_SS. EPROM Digital circuit Ground.

AV_DD. Analog V_DDof the Analog to Digital

Converter.

MAIN1 MAIN2 TRIACOUT

. ST52x301 is able to

,

drive a TRIAC in two different modes: Burst mode

or Phase Angle Partialization control mode.

The Burst mode is used for thermal regulation.

MAIN1 and MAIN2 signals are used to detect the

zero crossing of the main voltage.

ThepulsetodrivetheTRIACis givenbyTRIACOUT

pin.

It is possible to use the same pins to implement a

PWM Driver. In this case it is possible to fix the

periodof PWMand to changethe duty cycle on fly.

The PWM output is given by TRIACOUT pin.

AV_SS.AnalogV_SSoftheAnalogtoDigitalConverter.

Must be tied to V_SS.

V_PP. Main Power Supply for the internal EPROM

(12.5V 5%).

OSCin and OSCout. These pins are internally

connected with the on-chip oscillator circuit. A

quartz crystal or a ceramic resonator can be

connectedbetweenthesetwopinsin ordertoallow

the correct operations of ST52x301 with various

stability/cost trade-offs. An external clock signal

canbe appliedtoOSCin,in thiscase OSCoutmust

be grounded.

CE OE ERES CADD V

_PP. These pins are used

,

to manage the EPROM during the Programming

phase. During the Programming phase

(programming) V_PPmust be set at 12V. In the

RESET

. This signal is used to restart ST52x301at

the beginningof itsprogram.It alsoallowsto select

the program mode for the EPROM.

Working phase V_PPmust be equal to V_DD

.

INT

edge.

. External interrupt active on rising or falling

ERES in Programming Mode resets the address

counter of the EPROM;it is active at high level.

In the Working phase OE, CE and CADDare used

like handshakingsignals for the parallel port.

AIN0-AIN3. These 4 lines are connected to the

inputs of the analog multiplexer. They allow to

acquire 4 analog inputs.

MODE

. It selects the functionment mode

BG

.A Voltageequal to 2.5Vis availableon thispin.

(Programming or Working mode).

It can be used for Analog signal conditioning.

TEST. It enables the testing functionalities;during

theProgrammingand Workingphaseit mustbe set

to 0.

P0-P7.These8 linesareorganizedas oneI/Oport.

During the Programming phase such port is used

for the EPROM data read/write.

READY. Handshakesignal of the parallel port.

P8. Digital output.

TxD. Serial data output of the SCI transmitter

block.

5/99

ST52T301/E301

2 INTERNAL ARCHITECTURE

2.1 CONTROL UNIT

ST52x301 is made up by the following blocks and

peripherals:

The Control Unit (CU) manages: Registers File,

Input Registers, Configuration Registers, ALU,

Accumulator and Multiplexer inputs. Moreover the

CU drives the Fuzzy Core and the peripherals

(Triac/PWM Driver and Timer).

Control Unit

Fuzzy Core

ALU

The CU reads the stored instructions on the

EPROM (Fetch) and decodifies them. If the

instructions are arithmetic or logic, the CU runs

them directly, sending the control signals to the

related blocks. If there is a STOP instruction, the

CU transfersthe control to the Fuzzy Core.

EPROM

Clock Oscillator

Analog Multiplexer and A/D Converter

PrescalerTimer

Bandgap

The Fuzzy Core (FC) will read the next instruction

(thatmustbe a fuzzyinstruction)from the EPROM.

The FC mantains the control of the program until

the next STOP instruction. Then the FC transfers

the control to the CU.

Triac / PWM Driver

Digital I/O port

Thesecharacteristicsallow to mixfuzzyalgorithms

with mathematical and logic instructions.

Serial CommunicationInterface

Figure 2.1 shows a flow-chart reasuming the logic

behaviourof the instructions management.

ST52x301 Operating Modes

ST52x301works in two modes, Programming and

Working Modes, dependingon the control signals

level RESET, TEST and MODE.

Table 2.1. Control Signals setting

The Operating modes are selected by setting the

control signal level as specified in the Control

Signals Setting table.

Control

Signal

Programming

Reset

Working

RESET

0

1

0

1

0

TEST

MODE

Figure 2.1. Computation Algorithm Flow Chart

CU

Readsfromthe EPROM

and

Decodifies the instruction

No

CU

STOP?

executesinstruction

Yes

FuzzyCore

Readsfromthe EPROM

and

Decodifiesthe instruction

Yes

No

Fuzzy Core

executesinstruction

STOP?

6/99

ST52T301/E301

Figure 2.2. ST52x301 Block Diagram

TxD

MAIN1

SCI

(UART)

TRIAC/PWM

DRIVER

RxD

MAIN2

TRIACOUT

P0..P7

I/O

PARALLEL PORT

P8

READY

TCTRL

TRES

8 BIT

A/D CONVERTER

AIN0..AIN3

TIMER

TCLK

EPROM

2 KBytes

TIMEROUT

CONTROL

UNIT

Peripheral

Register

PC

PERIPH_REG_0

ALU

FLAGS

PERIPH_REG_1

PERIPH_REG_2

Register File

Input

Registers

ADC_OUT_0

ADC_OUT_1

ADC_OUT_2

ADC_OUT_3

TMR_OUT

Reg 0

Reg 1

Reg 15

FUZZY CORE

Configuration

Registers

TMR_ADC_ST

INP_PORT

SCI_IN

REG_CONF0

REG_CONF1

SCI_ST

FUZZY_OUT_0

REG_CONF15

FUZZY_OUT_1

POWER SUPPLY

VDD VPP VSS

RESET

OSCILLATOR

OSCin

OSCout

7/99

ST52T301/E301

It is not possibileto stopthe fuzzy inferencebefore

the end of the defuzzificationof one output.Aset of

26 different arithmetic and logic instructions is

available.Eachinstructionrequiresfrom4 to7clock

pulses to be performed.

The Carry flag is set when a carry or a borrow

occurs during arithmetic operations,otherwise it is

cleared.

The switching between the two sets of flags is

automatically performed when an interrupt or a

RETI instruction occur.

2.1.1 Program Counter

2.2 ADDRESS SPACES

W.A.R.P3TC has four separate address spaces:

The Program Counter (PC) is a 11-bit register that

contains the address of the next memory location

to be processed bythe core.This memory location

may be anopcode,an operandor an addressof an

operand.

Register File: 16 8-bit registers

Input Registers:11 8-bit registers

Configuration Registers:16 8-bit registers

PeripheralRegisters: 3 8-bit registers

Program memory up to 2K Bytes

The 11-bit length allows the direct addressing

mode of 2048 bytes in the programspace.

After having read the current instruction address,

the PC value is incremented. To execute relative

jumps the PCand theoffsetare shiftedthroughthe

Fuzzy Core or the ALU, where they will be added.

The result of this operation is shifted back into the

PC.

The Program memory will be described in further

detail in the MEMORYsection

2.2.1 Register File

The PC can be changed in the following ways:

JP (Jump) instruction PC = Jump Address

The Register File (RF) consists of 16 general

purpose 8-bit registers Reg0 to Reg15.

Allthe registersin theRF can be specifiedby using

a decimal address,

Interrupt

PC = InterruptVector

PC = Pop (stack)

PC = Reset Vector

PC = PC + 1

RETI instruction

Reset

e.g. 0 identify the first register of the RF, called

Reg0.

Reg0:3 are directly connected to the FC input. It

means that the input values of the fuzzyalgorithm

must be loaded into these registers by the user.

Normal Instruction

These registers are used as temporary registers

during the macros’computation.

2.1.2 Flags

TheST52x301 coreincludestwo pairsof flagsthat

correspondto 2 differentmodes:normal mode and

interrupt mode.Each pair consist of a CARRY flag

and a ZEROflag.One pair (CN, ZN)is used during

normal operation and one is used during the

interrupt mode (CI, ZI).

The ST52x301 core uses the pair of flags that

correspond to the actual mode: as soon as an

interruptis generated,the ST52x301coreuses the

interruptflagsinsteadof thenormalflags.Whenthe

RETI instruction is executed the normal flags are

restoredif the MCUwas in the normal modebefore

the interrupt. It should be observed that each flag

set can only be addressedin its own routine.

The flags are not cleared during the context

switching and remain in the state they were at the

exit of the last routine switching.

8/99

ST52T301/E301

Figure 2.3. Address Spaces description

CO RE

O N-CHIP PERIPHERALS

Program Mem ory

Configuration

Registers

LDC F

Input Registers

AL U

PE RIPHER AL

BL OC K

P eripheral Registers

F U ZZY

C OR E

R egister File

LD R I

LDP R

LD R C

LD R R

(1

)

LD C F CR i, x

Figure 2.4. Register File description

Register File

Fuzzy Core

Register

Reg0

Reg1

Reg2

Reg3

Reg4

Description

FUZZY_IN_0

FUZZY_IN_1

FUZZY_IN_2

FUZZY_IN_3

Free

Reg5

Reg6

Free

Reg7

Free

Reg8

Reg9

Reg10

Reg11

Reg12

Reg13

Reg14

Reg15

Free

9/99

ST52T301/E301

2.2.2 Input Registers Bench

the Timer status. For details about TMR_ST,

pleaserefer to Timer description.

The Input Registers(IR) bench consists of 11 8-bit

registers containing data or status of the

peripherals.

Data read by the Parallel I/O Port are stored

automatically in the 6-th register, INP_PORT.

Alltheregisterscan bespecifiedbyusinga decimal

address,e.g. 0 identifiesthe first registerof the IR.

The first four registers (ADC_OUT_0:3) of the IR

are dedicated to the 4 converted values coming

from the ADC.

Data read by the SCI are stored automatically in

the 7-th registerSCI_IN and SCI status is storedin

the SCI_ST register. For details about SCI_ST,

please refer to SCI description.

TheFuzzyCore writes the computedoutputvalues

in the FUZZY_OUT_0:1 registers.

TMR_OUT registers contains the current counted

value by the internal Timer; whereas TMR_ST is

Figure 2.5. Input Registers Bench description

10/99

ST52T301/E301

Figure 2.6. TMR_ADC_ST Registers

Figure 2.7. SCI_ST Registers

11/99

ST52T301/E301

2.2.3 Configuration Registers

The ST52x301 setting permits to configure all

blocks.Table2.2describesthe relatedblocktoeach

bit of the Configuration Registers.

Useandmeaningof eachregisterwill be described

in further details in the corresponding section.

Table 2.2. ConfigurationRegisters description

Register

Peripheral

Bit 7

Bit 6

Bit 5

IO5

Bit 4

IO4

Bit 3

IO3

Bit 2

IO2

Bit 1

IO1

Bit 0

IO0

PARALLEL

PORT

IO7

IO6

REG_CONF0

SCI, CORE,

I/O PORT

REG_CONF1

REG_CONF2

REG_CONF3

REG_CONF4

REG_CONF5

REG_CONF6

REG_CONF7

REG_CONF8

REG_CONF9

REG_CONF10

REG_CONF11

REG_CONF12

REG_CONF13

REG_CONF14

REG_CONF15

RDRF

OVR

BRK

TDRE

TXC

ECKF

P8 OUT

ADRST

TE

ADC

SCI

not used

IADD

M

1

BRSL

T8

RE

TIMER

TRIAC

TMLSB

TMMSB

not used

POL

TMS

CKSL

TMEL

IESL

TMST

INTF

TMRST

INTSL

not used

FZSL

INPSL

INTR

TCLSB

TRIAC

TCMSB

TCMSK

UTPLSB

TRIAC

IOSL

PSF

CKSL

MODE

TCST

TCRST

POL

TRIAC

INTSL

TCTRS

TRIAC

FZSL

EXTI

INPSL

UTPMSB

TRIAC

INTERRUPT

not used

MSKTC MSKTM MSKSCI MSKAD

MSKE

INT4

INT3

INT2

INT1

12/99

ST52T301/E301

2.2.4 Peripheral Registers

Table 2.3. Peripheral Register description

Peripheral Registers contain the initialization

valuesforthe Timer,Triac/PWM Driver and Parallel

Port.

Peripheral Register

Peripheral

Timer

PERIPH_REG_0

The peripheral initialization value is kept from a

location of the Register File, by using a LDPR

instruction, or from FUZZY_OUT_0/1 Input

Register according with the related Configuration

Registers.

Triac/PWM Driver

Parallel Port

PERIPH_REG_1

PERIPH_REG_2

Table 2.3 describes the related peripheral to each

ConfigurationRegister.

Useandmeaningof eachregisterwill be described

in further details in the corresponding section.

13/99

ST52T301/E301

2.4 FUZZY CORE

Figure 2.8. Alpha Weigth calculation

ST52x301Fuzzy Core main features are:

Up to 4 Inputs with 8-bit resolution

Up to 16 Membership Functions(Mbfs) for each

Input (64 possibleMbfs)

j-th Mbf

1

Up to 2 Outputs with 8-bit resolution

Possibility to process fuzzy rules with a max.

number of 8 antecedents

ij

α

2.4.1 Internal Structure

i-th INPUT VARIABLE

The block diagram shown in figure 2.9 describes

thestructureofST52x301FuzzyCore.Inthisfigure

wecandistinguishdifferentfunctionalblocks:Alpha

Calculator, Inference Unit and Defuzzifier. These

blocks allow to perform a MAMDANI type fuzzy

inferencewith crisp consequents.It is important to

underline that the fuzzy inference is performed by

using as inputsthe first4 locationsof theRegisters

File.

Input Value

Notice that the inputs for this block come from the

first four locationsof the Register File;it means the

user, to evaluate a fuzzy function, must load the

input values in these registers.

Alpha Calculator performs what is called

: the input data are transformed in

activation level (alpha weight) of the Mbfs.

2.4.2 Alpha Calculator Unit

This block performsthe intersection(alpha weight)

betweenthe input values and the related Mbfs(fig.

2.8).

fuzzification

Figure 2.9. Fuzzy Core Block Diagram

14/99

ST52T301/E301

2.4.3 Inference Unit

Figure 2.11.

Itmanagesthe alphaweightsobtainedbytheAlpha

Calculator Unit to computethe truth value ( ω ) for

each rule.

This is a calculation of the maximum (for the OR

operator) and/or minimum (for the AND operator)

performedon alphavalues accordingto the logical

connectivesof fuzzy rules.

j-th Singleton

1

ω

ij

It is possibileto link together up to eight conditions

by linguistic connectives AND/OR, NOT operator

and brackets.

ω

i0

ω

in

Each rule can have at maximum 8 alpha weights

(however they are connected).

0

X

i-th OUTPUT

VARIABLE

X

in

The truth value ω and the related output singleton

are passed to the Defuzzifier to complete the

inferencecalculation.

ij

i0

Figure 2.10.

2.4.4 Defuzzifier

This block consists of a Multiplier, two Adders and

one Divider. It generates the output crisp values

implementing the consequentpart of the rules.

IF INPUT 1 IS X1 OR INPUT 2 IS X2 THEN .......

In this phase each consequent Singleton X_iis

multiplied by its weight values ω_i, calculatedby the

Inference Unit in order to compute the upper part

of the defuzzification.

α1

α2

Eachoutputvalue(FUZZY_OUT0,FUZZY_OUT1)

is deduced from the consequentcrisp values (X_i)

by using the defuzzification formula:

Input

1

X1

X2

Input

2

OR = Max

N

IF INPUT 1 IS X1 AND INPUT 2 IS X2 THEN .......

X_ijω_ij

∑

j

α1

Y_i=

α2

N

Input

1

X1

X2

Input

2

ω_ij

∑

j

where:

i = 0,1 identifies the current output variable

N =numberof theactiveruleson thecurrentoutput

ω_ij=weigth of the j-th singleton

Xij = abscissa of the j-th singleton

The two fuzzy outputs are stored in the location 9

and 10 of the Input Registers (FUZZY_OUT_0,

FUZZY_OUT_1).

15/99

ST52T301/E301

2.4.5 Input Membership Function

The Mbf is memorized by using the following

instruction:

ST52x301 allows to manage triangular Mbfs. In

order to definea Mbf it is necessary to store three

different data on the memory:

DATA n m lvd v rvd

where

the vertex of the Mbf: V;

the lenght of the left semi-base: LVD;

the lenght of the right semi-base: RVD;

n identifies the input, m identifies the Mbf among

the16 possibleMbfs, lvd, v, rvdare the parameters

describing the Mbf’s shape.

In order to reduce the dimension of the memory

area and the computational effort the vertical

dimension of the vertex is fixed to 15 (4 bits)

2.4.6 Output Singleton

ST52x301uses forthe outputvariablesa particular

kind of membership function called Singleton. A

Singleton has not a shape, like a traditional Mbf,

and it is characterized by a single point identified

by the couple (X, ω), where the ω is calculated by

the Inference Unit as described before.

By using the previous memorization method it is

possible to store different kinds of triangular

Memberships Functions. In the following figure is

shown a typical example of Mbfs that can be

defined in ST52x301

Each Mbf is then defined storing 3 bytes.To store

all the information related with the fuzzy project

Mbfs, it is necessary to use 192 bytes of the

memory (3 bytes*16Mbfs*4 Inputs = 192 bytes).

Oftena Singletonis simply identified with its Crisp

Value X.

Figure 2.12. Mbfs Parameters

Figure 2.13. Example of valid Mbfs

15

Input Mbf

0

V

LVD

Input Variable

RVD

Output Singleton

15

w

0

X

OutputVariable

16/99

ST52T301/E301

2.4.7 Fuzzy Rules.

The rules can havethe following structures:

if A op B op C...........thenZ

if (A op B) op ( C op D op E...) ...........thenZ

where op is one of the possiblelinguistic operators

(AND/OR)

Each rule is codifiedby using an istructionset, the

inference time for a rule with 4 antecedentsand 1

consequentis about 3 microseconds.

The assembler Instruction Set allowing to manage

the fuzzy instructions are reported in the following

table:

In the first case the rule operators are managed

sequentially;in the second one, the priority of the

operatoris fixed by the brakets.

Table 2.4. Fuzzy Instructions Set

Instruction

Description

DATA n m lvd v rvd

LDP n m

LDN n m

FZAND

FZOR

Stores the Mbf m of the input n with the shape identified by the parameters lvd, v and rvd.

Fixes the alpha value of the input n with the Mbf m and stores it in the data stack.

Calculates the negated alpha value of the input n with the Mbf m and store the result in the data

stack.

Implements the fuzzy operation AND between the last two valuesstored in the data stack.

Implements the fuzzy operation OR between the last two values stored in the data stack.

Stores the result of the last fuzzy operation executed in the data stack.

Stores the result of the last fuzzy operation executed in the memory register M.

Copies the value of the register M in the data stack.

LDK

SKM

LDM

CON crisp

OUT n_out

STOP

Multiplies the crisp value with the last weight.

ω

Performs the defuzzification.

Ends the fuzzy algorithm.

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ST52T301/E301

Example 1:

IF Input₁IS NOT Mbf₁AND Input₄is Mbf₁₂OR Input₃IS Mbf₈THENCrisp₁

is codified by the following instructions

LDN 1 1

LDP 4 12

FZAND

LDK

calculates the NOT α valueof Input₁with Mbf₁and stores the result in the data stack

fixes the α value of Input₄with M₁₂and stores the result in the data stack

adds the NOT α and α values obtained with the operations LDN1 1 and LDP 4 12

stores the result of the operationFZAND in the data stack

LDP 3 8

FZOR

fixes the α value of Input₃with Mbf₈and stores the result in the data stack

implements the operation OR betweenthe results obtained with the operationsLDK

and LDP

CON crisp₁

multiplies the result of the last Ω operation with the crisp value Crisp₁

Example 2, the priority of the operator is fixed by the brakets:

IF (Input₃IS Mbf₁AND Input₄IS NOT Mbf₁₅) OR (Input₁IS Mbf₆OR Input₆IS NOT Mbf₁₄) THEN Crisp₂

LDP 3 1

fixes the α value of Input₃with Mbf₁and stores the result in the data stack

LDN 4 15

calculates the NOT α value of Input₄with Mbf₁₅and stores the result in the data

stack

FZAND

SKM

LDP 1 6

LDN 2 14

adds NOT α and α values obtained with the operations LDP 3 1 and LDN 4 15

stores the result of the operationFZAND in the memory register M

fixes the α value of Input₁with Mbf₆and stores the result in the data stack

calculates the NOT α value of Input₆with Mbf₁₄and stores the result in the data

stack

FZOR

implements the operation OR betweenthe α and NOT α values obtained with the

two previous operations(LDP 1 6 and LDN 2 14)

LDK

stores the result of the operationOR in the data stack

LDM

FZOR

copies the value of the memory register M in the data stack

implements the operation OR betweenthe last two valuesstored in the data stack

(LDK and LDM)

CON crips₂

multiplies the result of the last Ω operation with the crisp value Crip₂

At the end of the fuzzy rules set a byte,to identify

the output involved in the rules, and the STOP

istruction must be inserted.

When the STOP instruction is performed, the

control of the algorithm goes back to the CU.

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ST52T301/E301

2.5 ARITHMETIC LOGIC UNIT

The computational time required for each

instruction consists of one clock pulse for each

Cycle plus 3 clock pulses for the decoding phase.

The 8-bit Arithmetic Logic Unit (ALU) allows to

perform arithmetic calculations and logic

instructions which can be divided into 4 groups:

Load, Arithmetic, Jump and Program Control

instructions(refer to the ST52x301 Assembler Set

for further details ).

Table 2.5. Arithmetic & Logic Instructions Set

Load Instructions

Bytes

Menmonic

LDCF

Instruction

LDCF conf, const

LDRC reg, const

LDRI reg, inp

Cycles

Z

-

S

-

2

1

2

6

LDRC

LDRI

-

LDPR

LDPR per, reg

LDRR regi, regj

-

LDRR

-

Arithmetic Instructions

Mnemonic

ADD

Instruction

ADD regi, regj

AND regi, regj

SUB regi, regj

SUBO regi, regj

Bytes

Cycles

Z

I

S

I

2

7

AND

I

-

SUB

I

SUBO

I

Jump Instructions

Mnemonic

JP

Instruction

JP addr

Bytes

Cycles

Z

-

S

-

2

6

JPNS

JPNZ

JPS

JPNS addr

JPNZ addr

JPS addr

JPZ addr

-

JPZ

-

SCI Instructions

Bytes

Mnemonic

SRX

Instruction

SRX regi

STX regi

Cycles

Z

-

S

-

2

5

STX

-

Notes:

I affected

- not affected

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ST52T301/E301

Table 2.6. Arithmetic & Logic Instructions Set (Continue)

Program Control Instructions

Bytes Cycles

Mnemonic

RETI

Instruction

RETI

Z

I

S

I

1

5

RINT

RINT int

STOP

1

2

4

6

-

STOP

WAITI

UDGI

UEGI

MDGI

MEGI

IRQ

WAITI

UDGI

UEGI

MDGI

MEGI

IRQ int label

IRQM mask

IRQP cost

IRQM

IRQP

Notes:

I affected

- not affected

20/99

ST52T301/E301

3 EPROM

3.1 EPROM ProgrammingPhase Procedure

Programming mode is selected by applying

12V±5% voltage to the V_PPpin and set the control

signal as following:

The EPROM memory provides an on-chip

user-programmable non-volatile memory, that

allows fast and reliable storage of user data.

There are 16K bits of memory space with an 8-bit

internal parallelism (2Kbytes) addressed by an

11-bit bus.The data bus is of 8 bits.

RESET:0, TEST:0, MODE:1.

CADD, ERES, OE and CE are the control signals

used during the Programming Mode. CADD is

active on edge, the others are active on level (OE,

CE are active low, ERES is active high).

The memory has a double supply: V_PPis equal to

12V±5% in Programming Phase and 5V±10%

during Working Phase.V_DDis equal to 5V±10%.

The EPROM memory of ST52x301 is divided in

three main blocks (see Figure 3.1):

3.1.1EPROM Writing

When the memory is blank, all the bits are at logic

level ”1”. The data are introduced by programming

only the zeros in the desired memory location;

however all input data must contain both ”1” and

”0”.

Mbfs Setting with (0 through 191) contains the

coordinatesof the vertexesof every Mbf defined

in the program.

Interrupt Vectors (192 through 201) contain the

addresses for the interrupt routines.

Each address is composed of two bytes.

Theonly way to change ”0” into ”1” is to erase the

whole memory ( by exposure to Ultra Violet light)

and reprogram it.

The memory is in Writing mode when:

CE = LOW

Program Instruction Set (202 through 2048)

contains the instructionset of the user program.

It can be composed of more Boolean and Fuzzy

Algorithms

OE = HIGH

The operation that can be performed, during

Programming Phase, on the EPROM are: Writing,

Verify, Writing Inhibit, Standbyand Erasing.

with stable data on the data bus P(0:7).

The total programming pulse width (CE = 0 V) is,

typically, 50 µs (bymeansof 5pulsesof 10 µs), but

beforeactivatingsuch pulse, it is suggestedto wait

for at least 2 µs after V_PPrises at 12 V . After the

disactivationof the pulse it is suggestedto wait for

Figure 3.2 shows the signals timing in

Programming Mode.

Figure 3.1. Memory Map

2048

Fuzzy Algorithm

Boolean Algorithm

Program

InstructionsSet

· · ·· · ·

Fuzzy Algorithm

Boolean Algorithm

202

201

INT_EXT

INT_TRIAC

INT_TIMER

INT_SCI

Interrupt Vectors

Mbfs Setting

INT_ADC

192

191

Mbf Parameters

0

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ST52T301/E301

at least 2 µs before updating the data and the

to less than 100 µA. The Memory is placed in

standby mode by setting CE at HIGH Logic Level

(V_PPmight be equal to 5 V too). When in standby

mode, the outputs are in high impedance state.

address.

The data updating for the next programming is

performed, directly by the user, on the data bus

P(0:7) while the address is incremented through

the pin CADD.

3.2 Eprom Erasure

Thanks to the transparent window present in the

CLCC44-W package,its memory contentsmay be

erased by exposure to UV light.

3.1.2 EPROM Verify

A Verify mode is available in order to verify the

correctness of the data written. It is possible to

activate the Verify mode immediately after the

writing of each byte:

Erasurebegins when the device is exposed to light

witha wavelengthshorter than 4000Å.It shouldbe

noted that sunlight, as well as some types of

artificial light, includes wavelengths in the

3000-4000Årange which, on prolonged exposure,

can cause erasure of memory contents.It is thus

recommended that EPROM devices be fitted with

an opaque label over the window area in order to

prevent unintentionalerasure.

CE = HIGH

OE = LOW

Then, if any error in writing occured, the user has

to repeat the EPROM writing.

The data, during this phase, are avalaible on the

bus P(0:7)

The recommended erasure procedurefor EPROM

devicesconsistsof exposureto shortwaveUV light

having a wavelength of 2537Å. The minimum

recommended integrated dose (intensity x

expo-sure time) for complete erasure is

15Wsec/cm2 .

3.1.3 Writing Inhibit

It occursbetween the Writing and Verify Mode:

CE = HIGH

OE = HIGH

This is equivalent to an erasure time of 15-20

minutes using a UV source having an intensity of

12mW/cm 2 at a distance of 25mm (1 inch) from

the device window.

3.1.4 Standby Mode

The EPROM has a standby mode which reduces

theactivecurrentfrom10mA(Programmingmode)

Figure 3.2.EPROM Programming Timing

Writing

Inhibit

Verify

DATA IN

DATA OUT

P(0:7)

CE

INPUT

PORT

2us typ.

50us typ.

OUTPUT

PORT

3us min.

min 2us

OE

CADD

ERES

RESET

12V

5V

VPP

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ST52T301/E301

4 INTERRUPTS

Figure 4.1.Interrupt Flow

The Control Unit (CU) responds to peripheral

events and external events through its interrupt

channels.

When such an eventoccurs,if it is not maskedand

according to a priority order, the current program

execution can be suspended to allow the CU to

execute a specific response routine.

NORMAL

PROGRAM

FLOW

INTERRUPT

SERVICE

ROUTINE

Eachinterrupt isassociatedwithan interruptvector

that contains the memory address of the related

interrupt service routine.Each vector is located in

the Program Space (EPROM Memory) at a fixed

address (see Interrupt Vectorstable fig.4.2).

INTERRUPT

4.1 Interrupt Functionment

If, at the end of an arithmetic or logic instruction,

there are pending interrupts, the one with the

highest priority is passed. To pass an interrupt

means to storethe arithmeticflags and the current

PC in the stack and execute the associated

Interrupt routine, whose address is located in one

of the EPROM memory location between address

192 and 201.

RETI

INSTRUCTION

TheInterruptroutineisperformedasanormalcode

checking,at the end of eachinstruction, if a higher

priority interrupt has to be passed. An Interrupt

request with the higher priority stops the lower

priority Interrupt. The Program Counter and the

arithmetic flags are stored in the stack.

Figure 4.2.Interrupt Vectors Mapping

202

With the instruction RETI (Return from Interrupt)

the arithmetic flags and ProgramCounter(PC)are

restored from the top of the stack.This stack, used

for the Interrupt priority, is a LIFO queue.

201

INT_EXT

200

199

INT_TRIAC

198

197

An Interrupt request cannot stop the processing of

the fuzzy rules but this is passed only after the

definitionof the fuzzyoutputor atthe end of a logic

or arithmeticinstruction.

INT_TIMER

INT_SCI

InterruptVectors

196

195

194

193

192

191

4.2 Global Interrupt Request Enabling

When an Interrupt occurs, it generates a Global

Interrupt Pending(GIP), that can be hanged up by

software. After a GIP a Global Interrupt Request

(GIR) will be generate and Interrupt Service

Routine associated to the interrupt with higher

priority will start.

INT_ADC

In order to avoid possible conflicts between

interruptmaskingset in the main programor inside

macros, the GIP is hanged up through the User

Global Interrup Mask or the Macro Global Interrup

Mask (see fig.4.3).

Figure 4.3.Global Interrupt Request generation

Global Interrupt

Pending

Request

UEGI/UDGI instruction switches on/off the User

GlobalInterrupMaskenabling/disablingtheGIRfor

the main program.

User Global

InterruptMask

Macro Global

InterruptMask

MEGI/MDGI instructions set the Macro Global

InterruptMaskinorder toassurethatthe macrowill

not be broken.

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ST52T301/E301

4.3 Interrupt Sources

Table 4.1. Configuration Register 14 Description

ST52x301managesinterruptsignalsgeneratedby

the internal peripherals (Timer, Triac/PWM

Driver,Analog to Digital Converter and Serial

Communication Port) or coming from the INT pin.

Bit

Name

Value

Description

External Interrupt

0

Masked

0

MSKE

The polarity of the External Interrupt is

programmed by the EXTI bit of the REG_CONF14

(see Table 4.1 and fig. 4.4). EXTI=0 means that

INT_EXT is active on rising edge, otherwise it is

active on falling edge.

External Interrupt

Not Masked

1

0

1

0

1

0

1

0

1

A/D Converter Interrupt

Masked

1

2

3

4

MSKAD

MSKSCI

MSKTM

MSKTC

Each peripheral can be programmed in order to

generatethe associateinterrupt;further detailsare

described in the related chapter.

A/D Converter Interrupt

Not Masked

SCI Interrupt

Masked

4.4 Interrupt Maskability

The interrupts can be masked by configuring the

REG_CONF14.The interrupt is enabled when the

bit associated to the mask interrupt is ”1”.

Viceversa, when the bit is ”0”, the interrupt is

masked and is kept pendent.

SCI Interrupt

Not Masked

TIMER Interrupt

Masked

For example LDCF 14, 6

TIMER Interrupt

Not Masked

(CONF_REG14 =00000110) enables interrupts

comingfrom the ADC(INT_ADC)and fromthe SCI

(INT_SCI).

TRIAC/ PWM Interrupt

Masked

4.5 Interrupt Priority

Six priority levels are available: level 5 has the

lowest priority, level 0 has the highest priority.

TRIAC/ PWM Interrupt

Not Masked

Level5 is associatedto the MainProgram, levels 4

to 1 are programmable by means of the priority

register called REG_CONF15 (see fig.4.5);

whereas the higher level is related to the external

interrupt (INT_EXT).

5

6

not used

-

Active on Rising Edge

Active on Falling Edge

0

1

Timer, Triac/PWM Driver, SCI and ADC are

identifiedby a two bits Peripheral Code (see Table

4.2); in order to set the i-th priority level the user

must write the peripheral label i in the related INTi

priority level.

7

EXTI

Table 4.2. InterruptsDescription

Peripheral

Code

EPROM

Locations

Name

Description

Priority

Maskable

INT_EXT

External Interrupt (INT)

Ext

Int

Highest

-

yes

200-201

INT_ADC

INT_SCI

ADC

Programmable

00

01

10

11

192-193

194-195

196-197

198-199

SCI

INT_TIMER

INT_TRIAC

TIMER

TRIAC

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ST52T301/E301

Figure 4.4. Interrupt Configuration Register 14

REG_CONF14

Interrupt

D6 D5 D4 D3 D2 D1 D0

D7

MSKE - External Interrupt Mask

MSKAD - ADC Interrupt Mask

MSKSCI - SCI Interrupt Mask

MSKTM - TIMERInterrupt Mask

MSKTC - TRIAC Interrupt Mask

not used

EXTI

- External Interrupt Polarity

Figure 4.5. Interrupt Configuration Register 15

REG_CONF15

Interrupt

D6 D5 D4 D3 D2 D1 D0

D7

INT1

- HIGH Level Interrupt

INT2

INT3

INT4

- MEDIUM-HIGH Level Interrupt

- MEDIUM-LOW Level Interrupt

- LOW Level Interrupt

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ST52T301/E301

i.e. LDCF 15, 201 (REG_CONF15=11001001)

Table 4.3. Configuration Register 15 Description

define the following priority levels:

Bit

Name

INT1

Value

Level

Level 1: INT_SCI(SCI Code: 01)

Peripheral

Code

High

0, 1

Level 2: INT_TIMER(TIMER Code:10)

Level 3: INT_ADC(ADC Code:00)

Level 4: INT_TRIAC(TRIAC Code: 11)

Peripheral

Code

Medium-High

Medium-Low

Low

2, 3

4, 5

6, 7

INT2

INT3

INT4

Peripheral

Code

When a source provides an Interrupt request, and

the request processing is also enabled, the CU

changes the normal sequential flow of a program

bytransferingprogramcontrol toa selectedservice

routine.

Peripheral

Code

Whenan interruptoccurs theCUexecutesa JUMP

instruction to the address loaded in the related

location of the InterruptVector

Whenthe executionreturnstotheoriginalprogram,

it begins immediately following the interrupted

instruction.

4.6 Interrupt RESET

An eventuallypending interrupts can be reset with

the instruction RINT inti which resets the i-th

interrupt

Figure 4.6. Example of a Sequenceof InterruptRequests

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ST52T301/E301

5 CLOCK

ST52x301 can work by using a 5, 10 or 20 MHz

clock.

TheST52x301ClockGeneratormodule generates

the internal clock for theinternal ControlUnit, ALU,

Fuzzy Core and on-chip peripherals and it is

designed to require a minimum of external

components.

Thesystemclock maybe generatedbyusingeither

a quartz crystal, or a ceramic resonator

(CERALOC); or, at least, by means of an external

clock.

The different clock generator options connection

methodsare shown in Figure 5.1.

When an external clock is used, it must be

connectedon thepin OSCinwhileOSCoutmust be

grounded.

The crystal oscillator start-up time is a function of

manyvariables:crystalparameters(especiallyR_S),

oscillator load capacitance (CL), IC parameters,

ambient temperature, supply voltage.

It must be observed that the crystal or ceramic

leads and circuit connections must be as short as

possible.Typical values for CL1, CL2 are 10pF for

a 20 MHz crystal.

Figure 5.1. Oscillator Connections

27/99

ST52T301/E301

6. A/D CONVERTER

The A/D Converter, at the end of the conversion,

willsend a signal(end-of-conversion)whichcan be

used like an interrupt signal. The user can select

the priority of the A/D interrupt and mask it (see

”Interrupt Routine” chapter)

The A/D Converter of ST52x301is an 8-bit analog

to digital converter with up to 4 analog inputs

offering 8 bit resolution with a total accuracy of 2

LSB and a typical conversion time of 32 µs.

The conversion starts writing ”1” on

REG_CONF2(0).The A/D is reset by writing ”0” in

REG_CONF2(0).

The conversion range is 0 - 2.5 V.

The A/D peripheralconverts the input voltage with

a process of successive approximations using a

fixed clock frequencyderived from the oscillator.

Theconverted dataare automaticallystoredin four

8-bit Input Registers.

The ADC uses 5 registers: one Configuration

Register, REG_CONF2, and four Data Registers.

These 4 registersare the first4 InputRegisters.

By performing an instruction:

LDRI regj ingi

theanaloginput”ingi”is loadedintheregister”regj”

of the Register File.

The A/D converter drives the analog Multiplexer in

order to sequentiallypick up the external inputs to

be put in output and stored automatically in 4 8-bit

registers.

Table 6.1.

It is possibileto configuretheMultiplexerbymeans

of the register REG_CONF2, in order to select the

number of analog inputs to convert.

CONF_REG2 (3:2)

00

INPUT SEQUENCE

Ain0

For example, if the bit 3 and bit 2 of REG_CONF2

are configured at 10, then the Multiplexer will

sequentially pick up only the inputs 0,1 and 2.

Ain 0, Ain1

01

10

11

Ain 0, Ain 1, Ain 2

Ain 0, Ain 1, Ain 2, Ain 3

Table 6.1 shows the convertion sequences

according to the possible values of the two bit

REG_CONF2 (3:2).

Figure 6.1. A/D Converter Structure

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ST52T301/E301

The power consumption of the device can be

reduced by turning off the A/D converter,

Toswitchoff theA/DconvertertheCONF_REG2(0)

bit must be reset to ”0”.

The A/D Converter features a sample and hold.

The input voltage Ain, which has to be converted

must be constant,for 12.8 µs.

An internal bandgap reference is available on pin

44, BG. By using this signal as reference for the

signal to be converted, the conversion accuracy is

not strongly related with the variation of the power

supply.

The power supply of the A/D converter (AV_DDand

AV_SS) in order to avoidinterferencesis mantained

separatedfromthe powersupplyof thedigitalcore.

Figure 6.2. ConfigurationRegister REG_CONF2

ADC

Configuration Register

REG_CONF2

D7 D6 D5 D4 D3 D2 D1 D0

Reset ADC

Must be 1

ADC input selection

Not used

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ST52T301/E301

7.TIMER

TSTART starts/stops the Prescaler counting.It can

be given on the pin TCTRL or it is forcedby TMST

bit of REG_CONF6 register.

ST52x301 offers one on-chip Timer peripheral.

TheTimerconsists of an 8-bit counter with a 16-bit

programmable prescaler, thus giving a maximum

count of 2²⁴, and control logic that allows

configuring the functionment and the type of

peripheral outputs. Figure 7.2 shows the Timer

block diagram and Figure 7.3 shows the internal

structure of the Timer.

The TSTART signal allows to work in two different

modes:

LEVEL (Time Counter)

: If the TSTART signal is

high the Timer starts the count.When the TSTART

is low the count is stoppedand the current valueis

stored in the TMR_OUT register of the Input

registerBench, then it can be transferredto the j-th

location of the Registers File by using the

instruction:

Thecontentofthe 8-bitcountercan be read/written

andis incrementedon the RisingEdge of the16-bit

prescaleroutput(PRESCOUT).Moreover,it can be

read under program control at any instant of the

counting phase and loaded in a location of the

RegisterFile.Theprescalercan be givenanyvalue

between 0 and FFFFh setting the 4-th (TMLSB)

and 5-th (TMMSB) locations of the Configuration

Registers Bench.

LDRI reg-j 4

EDGE(Period Counter)

: After the reset, when the

firstedge of the TSTART signal appears,the Timer

starts the count, at the next TSTART the Timer is

stopped.In this way it is possible to measure the

period of an external signal.

7.1 Timer Functionment

The functionment modality is set by the TMEL

configurationbit of REG_CONF6register.

The Timer requiresthree signals:TMRCLK, TRST

andTSTART(see Figure7.3).Eachof themcan be

generatedinternally or externally,this possibility is

programmableby the user.

The starting value of the Counter can be either a

value contained in the Register File or directly a

Fuzzy Output.If INPSL (REG_CONF7(3)) is set to

”1” then the value comes from one of the locations

of the Register File (LDRP 0, reg-i); on the

contrary it is generated by the Fuzzy Core. The

choice between the two possible fuzzy outputs is

set by the FZSL configurationbit of REG_CONF6

register

TMRCLK increments the counted value of the

Prescaler. It can be, by setting CKSL of

REG_CONF6 register, the internal clock signal

(CLKM) or the signal provided on the pin TCLK.

TRSTresetstozerothe contentofthe 8bitcounter.

It is generated by the TRES or RESET external

signalsor itis forcedbyTMRSTbit ofREG_CONF6

register.

FZSL=0/1 means the starting value is the loaded

from the FUZZY_OUT_0/1.

Figure 7.1.Timer Functionalities

start

stop

Level

start

stop

Edge

Reset

Clock

Counted

Value

0

1

2

3

0

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ST52T301/E301

Figure 7.2.Timer Peripheral Block Diagram

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ST52T301/E301

Figure 7.3.Timer Internal Structure

32/99

ST52T301/E301

7.2 Timer Interrupt

Figure 7.4.TIMEROUT Signal Type

It is possible to enable the Timer Interrupt by

softwarecontrol.TheTimer can be programmedto

generate an Interrupt request until the end of the

count or when there is an externalTSTART signal.

The Timer can generate programmable Interrupts

in to 4 different modes:

Prescout*Counter

Timer Output

Type 1

Interrupt mode 1

: Interrupt on counter Stop.

Interrupt mode 2

TIMEROUT.

Interrupt mode 3

TIMEROUT.

Interrupt mode 4

TIMEROUT.

: Interrupt on Rising Edge of

: Interrupt on Falling Edge of

: Interrupt on both edges of

Type 2

InordertoprogramtheinterruptmodeINTSL,INTF

and INTR bits of the REG_CONF7 must be set

followingtheindicationsshownin theTable7.1.The

Timer interrupt can be used to exit the MCU from

the WAIT mode.

Table 7.1.Timer Interrupt Setting

INTERRUPT

INTSL

INTF

INTR

MODE

1

2

3

4

1

0

X

1

0

1

X

0

1

7.3 Timer Configuration

TheTimer configurationneeds to set 4 registersof

the Configuration Register Bench.

CONF_REG4:

TMLSB contains the less significative bits of the

Prescaler starting value.

CONF_REG5:

TMMSB containsthe moresignificative bits of the

Prescaler starting value

Figure 7.5.Timer Configuration Register 4 and 5

REG_CONF4

Timer

D6

D5 D4 D3 D2 D1 D0

D7

TMLSB - Prescaler Init Value

Less Significative Bits

REG_CONF5

Timer

D5 D4 D3 D2 D1 D0

TMMSB - Prescaler Init Value

More Significative Bits

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ST52T301/E301

CONF_REG6:

TMRST sets the internalINR signal.

TMST sets the internalINS signal.

Table 7.2. Configuration Register 6 Description

Bit

Name

Value

0

Description

Stop

Start

Stop

Start

IESL

selects the source of the TRES and

TSTART signals.

0

TMRST

1

0

1

0

1

0

1

0

1

0

1

0

1

IESL=”0”signalsarethe internalINRand

INS.

IESL=”1” signals come from the TRES

and TCTRL pins.

1

2

3

4

5

TMST

IESL

TMEL selects the TSTART signal allowing to

work inLevelMode or inEdge Mode like

previously described.

Internal Signals

External Signals

on Edge

TMEL=”0” means Edge Mode

TMEL=”1” means Level Mode.

TMEL

CKSL

TMS

CKSL selectsthe sourceoftheTMRCLK(work-

on Level

ing Timer frequency).

CKSL=”0”, the TMRCLK is the internal

MCLK divided by the Prescaler starting

value.

CKSL=”1”, the TMRCLK is an external

clock by TCLK pin.

Internal Timer Clock

External Timer Clock

Pulse Wave (Type 2)

Square Wave (Type 1)

Positive Polarity

Negative Polarity

TMS

TIMEROUT is a signal with frequency

equal to the working Timer frequency

divided by the starting value of the Pres-

caler (16 bit) and Counter (8 bit). The

Timeroutputcan be eithera squarewave

with duty-cycle 50% or a pulse signal

(withthepulsedurationequaltothePres-

caler output signal period).

6

7

POL

not

used

-

TMS=”1”, TIMEROUT is a squarewave

TMS= ”0”, TIMEROUT is a pulse signal.

POL

defines the polarity of the Timer output

signal (TIMEROUT).

Figure 7.6.Timer ConfigurationRegister 6

REG_CONF6

Timer

D6

D5 D4 D3 D2 D1 D0

D7

TMRST - Internal Timer Reset

TMST - Internal Timer Start

IESL

- Internal/External Signals Selector

TMEL

CKSL

TMS

- Edge/Level Timer Abilitation

- Internal/External Clock Select

- Timer Output Shape

POL

- Timer Output Polarity

not used

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ST52T301/E301

CONF_REG7:

INTSL It allows to select the interrupt mode for

Table 7.3. Configuration Register 7 Description

the Timer.

Bit

Name

Value

0

Description

INTSL=”0” Interrupt is generated on the

falling edge of the Counter Stop.

INT_TMR on Falling Edge of

Counter Stop

0

INTSL

INTSL=”1” the interrupt is generated on

the edgesof TIMEROUT.

INT_TMR on Edges of

TIMEROUT

1

0

1

0

1

0

1

0

1

INTF

INTR

NO INT_TMR on Falling

Edge of TIMEROUT

INPSL selects the source of the value of the

Counterbetweena locationof the Regis-

ter File and the Fuzzy Core.

1

2

3

4

INTF

INTR

INT_TMR on Falling Edge of

TIMEROUT

INPSL=”0”, Counter value coming from

the FC.

INPSL=”1”, Counter value coming from

the RF.

FZSL=”0”,thevalueoftheTimerCounter

is equal to FUZZY_OUT_0

FZSL=”1”,thevalueoftheTimerCounter

is equal to FUZZY_OUT_1

NO INT_TMR on Rising

Edge of TIMEROUT

INT_TMR on Rising Edge of

TIMEROUT

FZSL

Timer Data Input coming

from the Fuzzy Core

INPSL

FZSL

Timer Data Input coming

from a Register File location

Timer Data Input coming

from FUZZY_OUT_0

Timer Data Input coming

from FUZZY_OUT_1

5

6

7

not used

-

Figure 7.7.Timer ConfigurationRegister 7

REG_CONF7

Timer

D6 D5 D4 D3 D2 D1 D0

D7

INTSL - Interrupt GeneratorSelector

INTF

INTR

- Interrupton TIMEROUTFallingEdge

- Interrupton TIMEROUTRising Edge

INPSL - Input Data Selector

FZSL

- Fuzzy Input Selector

not used

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ST52T301/E301

8 I/O PORT

Figure 8.1.

ST52x301 is provided with dedicated lines for

input/output.These lines, grouped into an 8-bit I/O

Port P(0:7),can be programmedto provideparallel

input/output with a handshake line (READY) to

carry data in/out.

TTL

CMOS

INP_PORT(i)

The I/O Port is not able to perform operations on

the single bit, and the communication cannot be

performedat the same time in input and output.

P(0:7)

I/O PIN

PERIPH_REG_2(i)

REG_CONF0(i)

TRISTATE

It is possible to program the parallel port direction

by using the register REG_CONF0 in order to set

which bits are in input and which are in output.

IO(i)

OUT

The port has an internal register

(PERIPH_REG_2) dedicated to hold output data

coming from the Register File through an LDPR

instruction.

P8

OUTPUT PIN

REG_CONF1(0)

Inputdataareautomaticallystoredin theIN_PORT

register, 6-th location of the Input Register.

P8 pin is a digital output line available directly

connected to the OUT bit of the REG_CONF1;

then it can be set by using a LDCF instruction.

(see table 8.2 and Figure 8.8)

Figure 8.2.

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ST52T301/E301

8.1 I/O PORT CONFIGURATION

Table 8.1. Configuration Register 0 Setting

REG_CONF0 allows dynamic change in I/O Port

configurationduringprogram execution setting the

communication direction of each bit.

Bit

Name

Value

0

Description

Input Pin

0

IO0

IOi

setting equal to ”0” configuresthe i-thbit

of the P(0:7) I/O Port in input. Data com-

ing from external digital devices are

storedin the 6-thlocation(INP_PORT)of

the Inputregister bench.

Output Pin

Input Pin

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

3

4

5

6

7

IO1

IO2

IO3

IO4

IO5

IO6

IO7

Output Pin

Input Pin

IOi=”1” sets the i-th bit of the port in

output.Data stored in the i-th location of

the RegisterFile is written on the port by

using the instruction:

Output Pin

Input Pin

LDPR 2, regi

Output Pin

Input Pin

Output Pin

Input Pin

Output Pin

Input Pin

Output Pin

Input Pin

Output Pin

Figure 8.3. ConfigurationRegister 0

REG_CONF0

I/O Port

D6

D4 D3 D2 D1 D0

D5

D7

IO0

IO1

- I/O Communication Direction Bit

IO2

IO3

- I/O Communication Direction Bit

IO4

IO5

IO6

IO7

- I/O Communication Direction Bit

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ST52T301/E301

8.2 INPUT HANDSHAKE

Figure 8.4.One Line Input Handshake

Figure8.5 illustrates the timing associatedwith the

READY Handshake signal, when the instruction

LDRI reg 6 is performed.

When the LDRI instruction is executedto read the

port, ST52x301 resets the READY signal to

indicate that it is not possible to change the input

data during this phase of reading.

EXTERNAL

PERIPHERAL

W.A.R.P.3TC

P(7:0)

TosynchronizethetransmissionwithREADYsignal

will prevent the INP_PORT data from changing

while ST52x301 is reading the port.

DATA

I/O

PORT

READY

READ PORT signal representedin figure 8.5 is an

ST52x301internal signal.

IOP

x

0

REG_CONF1

Input data on the port are continuously sampled

and are strobed into the port only when READY is

set.

Figure 8.5.One Line Input HandshakeTiming

CLK

READ PORT

PIO(7:0)

DATAIN

NEW DATA IN

READY

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ST52T301/E301

8.3 OUTPUT HANDSHAKE

Figure 8.6.One Line Output Handshake

Figure8.7 illustrates the timing associatedwith the

READY Handshake signal, when the instruction

LDPR 2 reg is performed.

WhenREADYis resetno significantdata areonthe

output port pins,because ST52x301 is writing into

the PERIPH_REG_2.

When the data is ready in PERIPH_REG_2,

READY signal is set.

Therising edgeof READYsignal can be usedas a

latching signal.

No peripheral acknowledge is waited for.

If the signal READY is high, it means that the data

out is stillnot read.In thiscase, the followingLDPR

instruction is stored in a one register peripheral

stack.

If the READY is maintained high, the following

LDPR instructions store the data coming from the

Registers File on the same register stack.

Figure 8.7.One Line Output Handshake Timing

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ST52T301/E301

Table 8.2 ConfigurationRegister 1 Setting

Itmeansthateach LDPRinstructiondeletesthe old

value contained in the parallel port stack register

andrewritea newvalue on the samestackregister.

Only the last LDPR instruction is executed if the

READY signal is maintained high during several

LDRP instructions.

Bit

0

Name

P8

Value

-

Description

Digital Output Bit

5 MHz

00

01

10

11

1

2

10 MHz

20 MHz

ECKF

TXC

SCI End Transmission

Interrupt Disabled

0

1

3

4

SCI End Transmission

Interrupt Enabled

SCI TransmissionData

Register Empty Interrupt

Disabled

0

1

TDRE

SCI TransmissionData

Register Empty Interrupt

Enabled

SCI Break Error Interrupt

Disabled

0

1

0

1

0

1

5

6

7

BRK

OVR

SCI Break Error Interrupt

Enabled

SCI Overrun Error Interrupt

Disabled

SCI Overrun Error Interrupt

Enabled

SCI Received Data Register

Full Interrupt Disabled

RDRF

SCI Received Data Register

FullInterrupt Enabled

Figure 8.8.

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ST52T301/E301

9 SERIAL COMMUNICATION INTERFACE

Figure 9.1.SCI transmitted word structures

The Serial Communication Interface (SCI)

integrated into the fuzzy processor ST52x301

provides a general purpose shift register

peripheral, that allows to link several widely

distributed MCUs, through their SCI subsystem.

The SCI gives a serial interface providing

communication with common baud rates, up to

38400 Hz, and flexible character format.

The SCI is a full-duplex UART-type asynchronous

system with standard Non Return to Zero (NRZ)

format for the transmitted/received bit. The length

of the transmittedword is 10/11 bits (1 start bit, 8/9

data bits, 1 stop bit).

The SCI is composed of three modules:Receiver,

Transmitter and Baud-Rate Generator and it is

configured by means of ConfigurationRegisters 3

and 1.

9.1 SCI RECEIVER BLOCK

The SCI Receiver block manages the

synchronization of the serial data stream and

stores the data characters. The SCI Receiver is

mainly formed by two sub-systems: Recovery

BufferBlock and SCDR_RX Block.

The RE configuration bit set to ”1” (Configuration

Register 3) enablesthe SCI Receiver.

The SCI receives data coming from the RxD pin

and drives the Recovery Buffer Block, that is a

high-speed shift register operating at a clock

frequency (CLOCK_RX) 16 times higher than the

fixed baud rate (CLOCK_TX). This sampling rate,

higher than the Baud Rate clock, allows to detect

Figure 9.2. SCI Block Diagram

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ST52T301/E301

Table 9.1 ConfigurationRegister 3 Setting

theSTARTcondition,theNoiseerrorand theFrame

error.

Bit

Name

Value

Description

When the SCI Receiver is in IDLE status, it is

waiting for the START condition, that is obtained

with a logic level 0, consecutive to a logic level 1.

Thisconditionis detected,if,with thefixedsampling

time, three logic levels 0 are sampled after three

logic levels 1.

Transmission DISABLED

0

TE

Transmission ENABLED

Receiver DISABLED

Receiver ENABLED

8, No Parity,1 bit stop

8, No Parity,2 bit stop

8, Parity, 1 bit stop

1

0

The recognition of the START bit forces the SCI

Receiver Block to enter in an data acquisition

sequence,accordingto serial mode.

1

2

3

RE

1

The2 bits, M, ofthe ConfigurationRegister3 allow

todefinetheserialmodewith theconventionshown

in table 9.2.

00

01

10

11

Thebit, T8,in caseof M= 10is usedto setthe parity

checkto perform,as indicatedin the previoustable

9.2.

M

The recognition of STOP condition allows to

transferthe receiveddata, from Recovery Bufferto

SCDR_RX buffer, adding the eventual ninth data

bit,accordingto themeaningshowninthe previous

table 9.2. After this operation, RXF flag of SCI

StatusInputRegister8 (fig.9.3) is set to logiclevel

1.The ControlUnit readsthe data from SCDR_RX

buffer (in read-only mode) with SRX instruction

and provides a reset at logic level 0 to RDRF flag.

9, No Parity,1 bit stop

Parity Odd, if Parity is

0

1

selected (M = 10); otherwise

9th Data bit

4

5

T8

Parity Even, if Parity is

selected (M = 10); otherwise

9th Data bit

If a data of Recovery Buffer is ready to be

transferredinto SCDR_RX buffer,but the previous

one was not yet read by the Core, an OVERRUN

Error takesplace:the status flag OVERRindicates

the error condition. In this case the information

stored in SCDR_RX buffer is not altered, but the

one that has caused the OVERRUN error can be

overwritten by a new data coming from the serial

data line.

600 Hz

000

001

010

011

100

101

110

111

1200 Hz

2400 Hz

BRSL

4800 Hz

Recovery Buffer Block

6

7

This block is structured as a synchronised finite

state machine on the CLOCK_RX signal falling

edge.

9600 Hz

19200 Hz

38400 Hz

External Clock

When the Recovery BufferBlock is in IDLE state it

waits for the reception of the correct 1 and 0

sequence representing the START.

The recognition takes place by sampling the input

RxD at CLOCK_RX frequency, that has a

frequency 16 times higher than CLOCK_TX. For

this reason, while the external transmitter sends a

single bit, the Recovery Buffer Block samples 16

states (from SAMPLE1 to SAMPLE16).

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ST52T301/E301

Table 9.2 ConfigurationRegister 1 Setting

The analysis of RxD input signal is carried out

looking three samples for each bits received.0

Bit

0

Name

P8

Value

-

Description

Digital Output Bit

Ifthesethreesamples arenotequal, thenthenoise

error flag, NSERR, of Input Register 8 is set to 1

and the received data value will be the one

assumed by the majority of the samples.

5 MHz

00

01

10

11

1

2

10 MHz

20 MHz

By means of the procedure described above, to

avoid SCI becomes IDLE, because of a limited

noise due to an erroneous sampling, the

transmissionis recognizedascorrectandthe noise

flag error is set.

At the end of the cycle relative to the reception of

a bit, Recovery Buffer Block will repeat the same

steps 9 times: one step for each received bit, plus

oneforthe stopacquisition(10timesin caseof9-bit

data, double stop or parity check).

ECKF

TXC

SCI End Transmission

Interrupt Disabled

0

1

3

4

SCI End Transmission

Interrupt Enabled

SCI Transmission Data

Register Empty Interrupt

Disabled

0

1

Attheendof datareception,RecoveryBufferBlock,

will supply information on eventualframe errors by

setting to 1 FRERR flag bit of Input Register 8.

TDRE

SCI Transmission Data

Register Empty Interrupt

Enabled

A frame error can occur if the parity check has not

been successfully achieved or if STOP bit has not

been detected.

If Recovery Buffer Block receives 10 consecutive

bits at logic level 0, a break error occurres, and

interrupt routine request starts.

SCI Break Error Interrupt

Disabled

0

1

0

1

0

1

5

6

7

BRK

OVR

SCI Break Error Interrupt

Enabled

SCI Overrun Error Interrupt

Disabled

SCDR_RX block

It is a finite state machine synchronized with the

falling edgeof the clock master signal, CKM.

SCI Overrun Error Interrupt

Enabled

The SCDR_RX block waits the signal of complete

reception, from the Recovery Buffer, to load the

word received. Moreover, the SCDR_RCX block

loads the values of FRERR and NSERR flag bits

(Input Register 8), and sets the RXF flag to 1.

SCI Received Data Register

Full Interrupt Disabled

RDRF

SCI Received Data Register

FullInterrupt Enabled

Using SRX instruction the data are transferred to

RegisterFile and RXF flag is resetto 0, to indicate

SCDR_RX block is empty.

If a new data arrives before the previous one has

been transferred to Register File, an overrun error

occurres and OVERR flag, of Input Register 8, is

set to 1.

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ST52T301/E301

Figure 9.3. SCI Status Input Register

9.2 SCI TRANSMITTER BLOCK

reset to 0 to indicate the beginning of a new

transmission.At the end of transmission TXEND is

set to 1, allowing to load in the SHIFT REGISTER

a new data coming from SCDR_TX.

It is important to underline that TXEND = 1 does

notmean SCDR_TXis readyto receivea newdata.

Forthis reasonit is bettertoutilisethe TXEMsignal

to synchronize the STX instruction to the SCI

TRANSMITTER block

If ST52x301 core resets TE to 0, the transmission

is interrupted, but the SCI Transmitter block

completes the transmission in progress before to

reset.

TheSCI TransmitterBlock consistsof the following

underblocks: SCDR_TX and SHIFT REGISTER,

synchronized, respectively, with the clock master

signal (CKM) and the CLOCK_TX.

The whole block receives through Configuration

Register 3 (M bits) the settings for the following

transmissionmodes (see table 9.1):

8-bit word and a single stop signal

8-bitwordplusa paritybit anda singlestop signal

8-bit word plus a doublestop signal

9-bit word

In case of 9 bit frame transmission, the most

significative bit arrives through T8 of the

ConfigurationRegister 3.

In an 8-bit transmission, instead, T8 is used to

configure the SCI, according to information

containedin M(seetable9.1):in particularto chose

the polaritycontrol(even or odds)toimplement the

parity check.

9.3 Baud Rate Generator Block

The Baud Rate Generator Block performs the

division of the clock master signal (CKM), in a set

of synchronism frequencies for the serial bit

reception/transmissionon the external line.

Table9.1.showsthe setof frequenciesselected by

means of BRSL (Configuration Register 3).

Reception frequency (CLOCK_RX) is 16 times

higherthan transmission frequency(CLOCK_TX) .

If BRSL is equal to 111, CLOCK_RX and

CLOCK_TX signals coincide with clock master,

CKM.

After a RESET signal, RST, the SCDR_TXblock is

inIDLEstateuntil it receivesenablingsignal,TE=1,

of Configuration Register 3.

If TE=1, using STX instruction the data, to be

transmitted, are transferred from Register File to

SCDR_TX block and the flag of Input Register 8,

TXEM, is reset to 0, to indicate SCDR_TX block is

full.

If the core supplies a new data, this could not be

loaded inthe SCDR_TXblockuntilthe currentdata

has not beenunloadedon the Shift Registerblock.

Thismeans thatonlywhen TXEMis 1, it is possible

to load data in the SCDR_TX Block.

When the SHIFT REGISTER Block loads the data

to be transmitted on an internal buffer, TXEND is

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ST52T301/E301

10 TRIAC/PWMDRIVER

The Triac/PWM Driver can be initialized by using a

valuefixedbya controlalgorithm,thatcanbe either

the output of a fuzzy inference or the result of an

arithmetic calculus stored in the Register File.

ST52x301 offers a peripheral able to generate a

signal on pin 24, TRIACOUT, to drive an external

device, like a TRIAC, a IGBT or a Power Mos.

Triac/PWM driver can perform 3 different working

modes according to REG_CONF10 bits, MODE

(see Table 10.4):

In the latter case, by using the LDPR 1,reg-i

instruction, the value, containedin the i-th register

of Register File, is stored in the Triac Driver/PWM

peripheral register PERIPH_REG_1.

MODE = ”01”:

MODE = ”10”:

PWM

Burst Mode Triac Control

(Thermal Regulations)

Figure 10.1 shows the internal structure of

Triac/PWM Driver.

Note: in this case CKSL of REG_CONF10 must

PWM Mode

be set to ”1x”. (see Table 10.4)

The PWM working mode is obtained by setting

REG_CONF10 bits, MODE, at ”01” value.

MODE = ”11”:

Phase Angle Partialization

Triac Control (Motor Control)

Itconsistsof a signal,withfixedperiod, whoseduty

cycle can be modified.

Figure 10.1. TRIAC/PWM Driver Simplified Block Diagram

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ST52T301/E301

The PWM period can be generated, internally, by

dividing the masterclock or, externally,by using an

external clock signal.

In order to work in Burst mode, it is necessary to

detect the pre-post zero-crossing of main voltage,

by using an external inserting circuitry.

Inboth cases,the clocksignalis dividedbya 16-bit

Prescaler, managed by REG_CONF8 and

REG_CONF9 (see Figure 10.2).

Thedutycycleis fixedby a value,thatcan be either

the output of a fuzzy inference or the result of an

arithmetic calculus. In the first case, it can be

loaded directly in the register of the peripheral,

otherwise it can be stored in one location of the

Register File for further manipulations and then

used for the control of the PWM.

The user can define the period T, by means of the

internal 16-bit prescaler, setting REG_CONF8 and

REG_CONF9(see Figure 10.2).T is proportionalto

the main voltage period, it is in the range 0 to 21.8

sec (if the main frequencyis 50Hz).

The width and the polarity of the pulses can be

programmed according to the Triac and the circuit

characteristics.

Phase Angle Partialization Mode

Thismethodis basedon turningon the TRIAC only

for a part (phase angle) of each main voltage

period. When the phase angle is large the energy

(power)suppliedto the loadis low,viceversa,when

the phase angleis small the energy suppliedto the

load is high.

Burst Mode

It is based on turning on and off the TRIAC, for a

fixed integer number of main voltage periods, in

order to control the power transferred to the load.

For this reason a Burst Mode TRIAC control

consistsof a signal, with a period, T, containingan

integernumberof the main voltageperiods, whose

duty cycle is proportional to the number of periods

in whichthe TRIACis ON(Duty Cycle).This kind of

Triac control is mainly used for thermal regulation.

The phase angle can be fixed bya fuzzyalgorithm

or by a value stored in the Register File.

The phase angle is an 8-bit value.

The peripheral is programmable in order to work

with a main voltage frequencyof 50 or 60 Hz.

Thedutycycleisfixedbya valuethatcan bedirectly

the output of a fuzzy inference or the result of an

arithmetic calculus.

Figure 10.2. TRIAC/PWM ConfigurationRegister 8 and 9

REG_CONF8

TRIAC / PWM

D7 D6 D5 D4 D3 D2 D1 D0

TCLSB - Prescaler init value

Least Significative Bits

REG_CONF9

TRIAC / PWM

D7 D6 D5 D4 D3 D2 D1 D0

TCMSB - Prescaler init value

Most Significative Bits

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ST52T301/E301

10.1 PWM GENERATOR WORKING MODE

coming from Register File, according with the

INPSL and FZSL configuration bits of

REG_CONF12(see Table10.6 and Figure 10.12).

When REG_CONF10 (3:2) bits, MODE, are ”01”,

the peripheral is programmed to work in PWM

Mode.

The Ton is equal to:

By using the 16-bit prescaler,the PWM period can

be generatedby dividing the internal masterclock,

or an external clock signal applied on the pin

MAIN1,or themainvoltagefrequency,by usingthe

circuit shown in Figure 10.6.

Ton= INIT_VALUE*Tck.

It means the Ton can be fixed by the control

algorithm that can be either the output of a fuzzy

inferenceor the result of an arithmetic calculus.In

thesecondcase,the data,storedin thei-th location

of the Register File, can be loaded by using the

instruction:

NOTE: The external clock signal, applied on

MAIN1 pin,must havea frequencyat leastthree

time smaller than the internal master clock.

LDPR 1, reg-i.

The clock source can be selected by using

REG_CONF10(5:4)bits,CKSL(seeTable10.4and

Figure 10.9).If the clock source selectedis not the

mainvoltagefrequency(CKSL=1x),MAIN2pin can

be configured as input or output, by using

REG_CONF10(7) bit, IOSL (see Table 10.4).

If the INIT_VALUEis 255 the Toff is equal to Tck.

Table 10.1.MODE - Triac/PWMWorking Mode

Settings

Value

Description

If MAIN2 is an output, on this pin it is possible to

get the prescaler output signal Tck.

PWM Driver

01

Burst Mode Control ⁽¹⁾

The period of the PWM signal is obtainedby using

the following relation:

10

Phase Angle Control

T=256*Tck

11

where Tck is the output of the 16-bit prescaler

managedbyREG_CONF8and REG_CONF9(see

Figure 10.2).

Note: ⁽¹⁾REG_CONF10(5) must be set to ”1”

NOTE. In PWM working mode, the value N,

stored in the 16-bit prescaler, must be in the

range from 2 to 2¹⁶-1

Table 10.2. PWM Frequencies

MCLK

1/T

Frequency

min

max

By using a 20 MHz clock master it is possible to

obtain a PWM frequency in the range 1.2 Hz to

26.04 KHz.

5 MHz

10 MHz

20 MHz

0.3Hz

0.6 Hz

1.2 Hz

6.51 kHz

13.02 kHz

26.04 kHz

The value Ton is proportional to a value,

INIT_VALUE,that can be a fuzzyoutput or a value

Figure 10.3. PWM Functionament

T = 256 * Tck

Ton = INIT_VALUE* Tck

Toff

TRIACOUT

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ST52T301/E301

10.2 BURST MODE

usingthe mainvoltagefrequencyappliedto MAIN1

and MAIN2 pins.

When REG_CONF10 (3:2) bits, MODE, are ”10”

the peripheral is programmed to work in BURST

MODE.

Theperipheralcanbeprogrammed inordertowork

with50 or 60 Hz mainvoltagefrequency,by setting

the REG_CONF10(6) bit, PSF (see Table 10.4).

Notice that when you are working in Burst mode

CKSL must be set to ”1x”

.(see Table 10.4)

Ranges of the Tb signal period depend on the

powerline frequency(see Table 10.3).

A square wave, Tb, is generated with a duty cycle

proportional to the power the user intends to

transferon the load.A pulse is generatedfor each

zero crossing of the main voltage included in the

Ton of the fixed period. Figure 10.4 shows the

typicalBurstControlworking mode.TheperiodT of

thesignal Tb (seeFigure10.4)is equalto 256*Tck.

In order to drive a Triac in BurstMode it is required

to generate a sequence of pulse, that must be

centred on the zero crossing of the power line as

shown in the Figure 10.7. For this reason, the pre

zero crossing and the post zero crossing of the

power line must be detected.

To detect the zero-crossing and get also the main

voltage frequency, the user must generate MAIN1

and MAIN2 signals, by using the circuit shown in

Figure 10.6.

ThesignalTckisgeneratedprogrammingthe16-bit

Prescaler, by REG_CONF8 and REG_CONF9

(see Figure 10.2).Tck is equal to the main voltage

frequency (50 or 60 Hz) divided by N+1, where N

value is from 0 to 2¹⁶-1.

The value Ton is proportional to a value,

INIT_VALUE,that can be a fuzzyoutput or a value

coming from Register File, according with the

INPSL and FZSL configuration bits of

REG_CONF12 (see Table 10.6 and Figure 10.12).

MAIN1 and MAIN2 signals are used in the block

called PULSEGENERATOR of the peripheral(see

Figure 10.1).

In particular the pulses are generatedby using the

rise edge of the signal MAIN1 and the falling edge

of the signal MAIN2.

Figure 10.5 shows the generation of the Triac

pulses Tp .

On TRIACOUT pin is generated a sequence of

pulses, programmed, by using REG_CONF11(0)

bit, POL (see Table 10.5), in order to be positive or

negative, to drive the Triac in different quadrants.

The number of generatedpulses, N_PULSES, is:

The first firing pulse for the Triac is generated on

the zero crossing of the power line, while the next

pulses are centred on the zero crossing.

N_PULSES = 2 [(N+1)*INIT_VALUE - N]

where N is the value stored in the 16-bit pescaler.

Then Ton = (N_PULSES / 2)* T_{POWER LINE}

The first pulse is obtained during the first zero

crossing of the main voltage and the last one is

generated after INIT_VALUE*Tck clock pulses,

where Tck is the Prescaler output, generated by

Table 10.3. TRIACOUT Signal Period

T

Power Line

Frequency

min

max

50 Hz

60 Hz

5.12 s

4.26 s

335544 s

279620 s

Figure 10.4. Burst Working Mode

T = 256 * Tck

Ton

Tb

1.5

1

0.5

0

Power

Line

-0.5

-1

-1.5

TRIACOUT

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ST52T301/E301

Normally the Triac firing pulses start 1/3 Tp before

thezerocrossing and the lengthof thepulsesisTp,

see Figure 10.5.

T_P

MCLK

Frequency

min

max

5 MHz

10 MHz

20 MHz

0.0012 ms

0.0006 ms

0.0003 ms

19.6608 ms

9.8304 ms

4.9152 ms

The length Tp of the pulses is programmable by

usingUTP value,that is a14-bits number,obtained

with REG_CONF12(5:0) bits, UTPMSB, and

REG_CONF13, UTPLSB (see figure 10.12 and

table 10.6):

pulses polarity; in order to obtain positive or

negative gate Triac currents, allowing to work

respectively in I and IV quadrants, or in the II and

III quadrants (see Figures 10.5 and 10.12).

UTP(13:0) = [UTPMSB(5:0) UTPLSB(7:0)]

T_P= T_MCLK* UTP

To increase the immunity of the peripheralagainst

the electrical noise of the main voltage, a

programmable masking time, by using

REG_CONF11(5:2)bits, TCMSK (see Table 10.5)

The value Tp is in the range 0 to 4.9 ms when the

clock master is 20 MHz.

According to REG_CONF11(0) configuration

register bit, POL, it is possible to set the firing

Figure 10.5. Burst Mode pulse polarity

Figure 10.7 Burst Mode Zero Crossing

1.5

1

0.5

Power

0.5

0

Line

Main Voltage

0

(0.5)

II and III quadrants

-0.5

Positive⁽¹⁾

Ig

Triac Gate

Current

MASK

T

Tp

MASK

T

Tp

-1

TRIACOUT

-1.5

Ig

Negative

Triac Gate

MAIN1

I and IV quadrants

2/3 Tp

Current

1/3 Tp

MAIN2

Tp

Figure 10.6 Burst Mode Zero Crossing Circuit

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ST52T301/E301

and Figure 10.11), is introduced after each firing

pulse (see Figure 10.7):

TCMSK

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

MaskingTime

0 µs

Masking time =(2^TCMSK*200 +100) nS.

If TCMSK is 0 then Masking time is 0.

0.5 µs

In fact, to avoid the detection of electrical noise,

during the masking time no signal, coming from

MAIN1 and MAIN2, is taken into account.

0.9 µs

1.7 µs

Working in the II and III quadrant the peripheral

implements the following procedure:

3.3 µs

6.5 µs

1) Thefiring pulse is set to ”1”on therising edge of

MAIN1.

12.9 µs

25.7 µs

51.3 µs

102.5 µs

204.9 µs

409.7 µs

819.3 µs

1638.9 µs

3276.9 µs

6553.7 µs

2) The firing pulse is reset to ”0” after the time Tp

fixed by program.

3) The firing pulse is reset to ”0”for a time equal to

the fixed masking time.

4) On the falling edge of MAIN2 the firing pulse is

set to ”1”

5) The firing pulse is reset to ”0” after the time Tp

fixed by program.

6) The firing pulse is reset to ”0”for a time equalto

the fixed masking time.

Following this approach it is possible to filter

electrical noise and oscillations on the signal

MAIN1 and MAIN2.

It is possibleto generatea programmableInterrupt

in four different ways:

10.3 PHASE ANGLE PARTIALIZATION WORK-

ING MODE

1) No Interrupt;

When REG_CONF10 (3:2) bits, MODE, are ”11”

the peripheral is programmed to work in PHASE

ANGLE PARTIALIZATION mode.

2) Interrupt on the rising edge of the signal Tb.

3) Interrupt on the falling edge of the signal Tb.

4) Interrupt on both the edgeof the signal Tb.

In this mode Triac is controlled each period of the

main voltage.The power transferredto the load is

proportional to the CURRENT FLOW ANGLE γ.

ThiskindofTriac controlis suitabletodrivetheTriac

TheInterruptis programmablebyusingthe register

REG_CONF11(7:6), INTSL (see Table 10.5).

Figure 10.8. Phase Angle Partialization Mode

1.5

V

A2-A1

1

0.5

L

Load

0

Il

A2

α

1.5

(0.5)

Phase Angle

Il¹

A1

(1)

N

0.5

(1.5)

0

(0.5)

(1)

γ

Current Flow Angle

180 ⁰

360⁰

(1.5)

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ST52T301/E301

with inductive load (i.e. universal or monophase

motors). In the figure 10.8 is shown the relation

between the Phase Angle α and the Current flow

must be synchronized with the following main

voltagezero crossing, always.

Theperipheralcanbeprogrammedinordertowork

with50 or60 Hz main voltagefrequencyby setting

the REG_CONF10(6) bit, PSF (see Table 10.4).

If mainvoltagefrequencyis equalto 50 Hz, thenTr,

see figure 10.9, is equal to 20 mSec and T1 is:

T1 = PERIPH_REG_1(0:7)*(1/25.5)ms.

Thelength of the semiperiodTi/2 is programmable

by using the registers REG_CONF12(0:5) and

REG_CONF13,(seefigure10.12).By usinga clock

master equal to 20 MHz the pulse width is in the

range from 0.2 to 250 µs. The duty cycle of Ti is

always 50 %.

In order to avoid problemsfor the Triac firing when

the load is inductive 8 different pulses are

generatedby the peripheral.

If the time T1 is bigger than a fixedtime Tmax then

nopulsesaregeneratedand theTriacis maintained

off.This featurewas implemented in order to avoid

the firing of the Triac in the second half period of

the main voltage. The firing pulses are generated

when the contents of the PERIPH_REG_1 is less

or equal to 204, otherwise they are not generated.

angleγ . Theperipheralallows to controlthe Phase

AngleorequivalentlythetimeT1 (seeFigure10.9).

ItispossibletochangeTimeT1settingthe contents

of the peripheral register PERIPH_REG_1. This

value could be directly loaded by using one of the

two fuzzy outputsor by using a value coming from

theRegistersFile, accordingwith INPSLand FZSL

configurationbits ofREG_CONF12(seeTable10.6

and Figure 10.13).

In orderto synchronizethe peripheralwiththe zero

crossing of the main voltage the two pins MAIN1

and MAIN2 must be connected together if the

externalcircuitistheoneshownintheFigure10.10.

It is possible to use different circuits for the zero

crossing detection, but the MAIN1 signal rising

edge must be synchronized with a main voltage

zero crossing and the MAIN2 signal falling edge

Figure 10.9 Phase Angle Partialization mode

Tr

Mai₁n_.s₅

Voltage

Tr/2

When the frequency of the main voltage is 50 Hz,

T1max is equal to 8 mSec.

It is possible to generatea programmableinterrupt

in four different ways:

1

Ti

0.5

0

T1

1) no Interrupt;

T1

(0.5)

(1)

2) Interrupt on the rising edge of the signal MAIN1

3)Interrupt on the falling edge of the signal MAIN2

4) Interrupton boththe edgesof the signal MAIN1.

TheInterruptis programmablebyusing the register

REG_CONF11(7:6), INTSL

Tmax

(1.5)

8 mS

10 mS

20 mSec

10.4.TRIAC/PWM DRIVER PROGRAMMING

Figure 10.10 Phase Angle Partialization Zero Crossing

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ST52T301/E301

It is possible SET or RESET the TRIAC/PWM

Peripheral by using the REG_CONF10(0) bit,

TCRST (see Table 10.4).

If TRIAC/PWM Peripheral is SET, It is possible

START or STOP it, by using the REG_CONF10(1)

bit, TCST (see Table 10.4), to start or stop the

internal counter without resetting it.

Itis possibletoenabletheTRIACOUT, byusingthe

REG_CONF11(0) bit, TCTRS (see Table 10.5 and

Figure 10.11).

IFTCTRSis 0 theTRIAC/PWM Peripheraloutput

is in tristate status.

Table 10.5 ConfigurationRegister 11 Description

Bit

Name

Value

0

Description

Output pulse Polarity =

positive

0

POL

Output pulse Polarity =

negative

1

TRIACOUT status = Tristate

TRIACOUT status = Enabled

0

1

TCTRS

TCMSK

2

3

4

5

Masking time

=(2^TCMSK*200 +100) nS.

TCMSK=0 Masking time=0

→

No Interrupt source selected

00

01

6

Interrupt on falling edge of

the TRIAC/PWM signal, or of

the Main Voltage

Table 10.4 ConfigurationRegister 10 Description

Bit

Name

Value

0

Description

Triac Reset

INTSL

Interrupt on rising edge of

the TRIAC/PWM signal, or of

the Main Voltage

0

TCRST

10

11

Triac Set

1

7

Triac Stop

0

Interrupt on both of edges of

the TRIAC/PWM signa,l or of

the Main Voltage

1

2

3

4

5

6

7

TCST

Triac Start

1

not used

00

01

10

11

00

01

PWM signal Generator

Burst Mode ⁽¹⁾

Phase Partialization

Clock Master

MODE

Table 10.6. ConfigurationRegister 12 Description

Bit

Name

Value

Description

Output Impulse Width most

significative bits

UTPMSB

0 ÷ 5

External Clock on MAIN1

CKSL

TRIAC/PWM Input from

Fuzzy Output

0

1

0

1

Main Voltage Frequency

1x

6

7

INPSL

FZSL

TRIAC/PWM Input from

Register File

Main Power at 50 Hz

Main Power at 60 Hz

MAIN2 Input pin

0

1

0

1

PSF

TRIAC/PWM Input from

Fuzzy Output 1

TRIAC/PWM Input from

Fuzzy Output 2

IOSL

MAIN2 Output pin

Note: ⁽¹⁾CKSL must be set to ”1x”

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ST52T301/E301

Figure 10.11.TRIAC/PWM ConfigurationRegister 10

Figure 10.12 TRIAC/PWM Configuration Register 11

Figure 10.13 TRIAC/PWM Configuration Registers 12 and 13

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ST52T301/E301

11 ELECTRICAL CHARACTERISTICS

Absolute MaximumRatings

This product contains devicesto protect the inputs

against damage due to high static voltages,

however it is advised to take normal precaution to

avoid any voltage higher than maximum rated

voltagees.

Forproperoperationit is recommendedthatV_Iand

V_Omust be higherthan V_SSand smaller than V_DD

.

Reliability is enhanced if unused inputs are

connectedto an appropriated logic voltage level

Table 11.1. Absolute Maximum Ratings

Symbol

Parameter

Value

Unit

Supply Voltage

Input Voltage

Output Voltage

V_DD

-0.5 to 7

V

V_I

V_SS-0.3 to V_DD+0.3 ⁽¹⁾

13

V

V_O

Analog Supply Voltage

V

_DDA, V_SSA

V_PP

V

EPROM Programming Voltage

Standard Output Source Sink Current ⁽²⁾

TRIACOUT Output Source Sink Current

Operating Temperature

V

mA

°C

20

±

I_O

±80 ⁽³⁾

0 to +85

T_OPT

T_STG

Storage Temperature

-65 to +150

Note: Stresses above those listed in the Table ”Absolute Maximum Ratings” may cause permanent damage to the device.

These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating

sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect

device reliability.Refer also to the SGS-THOMSON SURE Program and other relevant quality documents.

1.Within these limits, clamping diodes are garanteed to be not conductive.

2. All except TRIACOUT pin

3.For not more than 1 sec.

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ST52T301/E301

VSS or VDD) RECOMMENDED OPERATING CONDITIONS

(

(OperatingCondition:V_DD=5V±5%-T_A=0 °C to 85 °C, unless otherwise specified)

Table 11.2. RecommendedOperation Condition

Symbol

Parameters

Test Conditions

Min

Typ

Max

Unit

Operating Supply Voltage

V_DD

4.75

5.0

5.25

V

Programming Voltage

Ouput Voltage

V_PP

V_O

11.4

V_SS

VSS

5

12

12.6

VDD

V_DD

20

V

Analog Supply Voltage

Oscillator Frequency ⁽¹⁾

V

_DDA, V_SSA

f_OSC

V

Vss ≤ V_SSA< V_DDA≤ V_DD

10

MHz

Notes:

1. For correct behaviour of some peripherals, it is possible to work only withone of the 5 - 10 - 20 MHz frequencies.

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ST52T301/E301

DC ELECTRICAL CHARACTERISTICS

(OperatingCondition:V_DD=5V±5%-T_A=0 °C to 85 °C, unless otherwise specified)

Table 11.3 DC Electrical Characteristics

Symbol

Parameter

Test Conditions

Min

Typ

Max

Unit

TTL type Schmitt trig. Low Level Input

Voltage

VDD =4.75 V

see fig.11.6

0.7

V

V_IL

CMOS type Schmitt trig. Low Level Input

Voltage

V

_DD=4.75 V

1.2

V

see fig.11.7

TTL type Schmitt trig. High Level Input

Voltage

V

_DD=5.25 V

2

see fig.11.6

V_IH

CMOS type Schmitt trig. High Level Input

Voltage

V

_DD=5.25 V

3.5

see fig.11.7

Standard Low Level Output Voltage

TRIACOUT Low Level Output Voltage

Standard High Level Output Voltage⁽¹⁾

TRIACOUT High Level Output Voltage⁽¹⁾

TTL type Schmitt trig. Hysteresis Voltage

CMOS type Schmitt trig.Hysteresis Voltage

Low Level Leakage Input Current

I_OL=4mA

0.4

V

V_OL

V_OH

V_Hys

I

_OL=50mA

2

I_OL=-4mA

I_OL=50mA

see fig.11.6

see fig.11.7

V_I=V_SS

V_DD-0.5

V_DD-2

1.2

2.0

-1

I_IL

I_IH

I_OL

µ

A

High Level Leakage Input Current

V_I=V_DD

+4

µA

Tri-State Output Leakage Current

V_O=V_SSor V_DD

mA

±10

V

_PPconnected with

V_DD;

Supply Current in RESET mode

Supply Current in RUN mode

11

3

mA

V_RESET=V_SS

F_OSC= 10 MHz

I_DD

V

_PPconnected with

V_DD;

F_OSC= 10 MHz

_PPconnected with

V_DD;

V_RESET=V_SS

F_OSC= 10 MHz

Analog Supply Current in RESET mode

Analog Supply Current in RUN mode

I_DDA

V

_PPconnected with

V_DD;

10

F_OSC= 10 MHz

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ST52T301/E301

AC ELECTRICAL CHARACTERISTICS

(OperatingCondition:V_DD=5V±5%-T_A=0 °C to 85 °C, unless otherwise specified)

Table 11.4. AC Electrical Characteristics

Symbol

Parameter

Input protection Resistor

Test Conditions

Min

Typ

Max

Unit

R_S

All Input Pins

1

kΩ

Input Capacitance

C_IN

All Input Pins

All Ouput Pins

10

pF

Output Capacitance

C_OUT

Table 11.5. Timing Parameters

Symbol

f_OSC

t_CLH

Parameters

Test Conditions

Min

Typ

Max

Unit

MHz

ns

Oscillator Frequency

Clock High

20

25

t_CLL

Clock Low

ns

t_SET

Setup

see fig 11.1

see fig.11.1

5

ns

t_HLD

Hold

ns

t_WRESET

t_WINT

t_IR

Minimum Reset Pulse Width

Minimum External Interrupt Pulse Width

Input Rise Time

100

ns

see fig.11.2

15

ns

t_IF

Input Fall Time

ns

C_LOAD=10 pF

see fig.11.2

t_OR

t_OF

Output Rise Time

Output Fall

10

ns

CLOAD=10 pF

see fig.11.2

Figure 11.1. Data Input Timing

Figure 11.2. I/O Rise and Fall Timing

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ST52T301/E301

Figure 11.3. Input Pin Equivalent Circuit

Figure 11.4. Equivalent Tristate Output Circuit

Figure 11.5. EquivalentOutput Circuit

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ST52T301/E301

Figure 11.6. TTL-level Input Schmitt Trigger

Figure 11.7. CMOS-level Input Schmitt Trigger

Note:Only for RETE1 and RETEIO signals

TIMER CHARACTERISTICS

(OperatingCondition:V_DD=5V±5%-T_A=0 °C to 85 °C, unless otherwise specified)

Table 11.7. Timer Characteristics

Symbol

Parameter

Min

Typ

Max

Unit

Resolution

t_RES

1/F_OSC

s

µ

External Input Frequency on timer

Internal Input Frequency on timer

20

f_IN

t_W

MHz

Pulse Width on TIMEROUT pin

1/F_OSC

s

µ

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ST52T301/E301

A/D CONVERTER CHARACTERISTICS

(OperatingCondition:V_DD=5V±5%-T_A=0 °C to 85 °C, unless otherwise specified)

Table 11.8. A/D Converter Characteristics

Symbol

Parameter

Test Conditions

Min

Typ

Max

Unit

Resolution

Res

8

bit

F_OSC> 5 MHz

Total Accuracy ⁽¹⁾

A_TOT

F

_OSC> 10 MHz

_OSC> 20 MHz

2

±

LSB

F

Conversion Time

t_C

F_OSC=5 - 10 - 20 MHz

32

µs

Conversion Range

V_AN

V_SSA

2.5

V

Conversion result=

00 Hex

Zero Scale Voltage

V_ZI

V_SSA

V

Conversion result=

FF Hex

Full Scale Voltage (bandgap)

V_FS

2.474

Full Scale Voltage (bandgap) precision

v/s V_DDAvariation

1

%

V

∆

%

FS

VDDA=5V 5%

±

Analog Input Current during Conversion

Analog Input Capacitance

AD_I

f_OSC= 20 MHz

2

µΑ

(2)

AC_IN

ASI

2

1

pF

Analog Source Impedance

kΩ

Ω

Output Reference Impedance

Output Reference Load

ORI

ORL

100

0.1

10

mA

pF

Analog Reference Load Capacitance

ORLC

Source-Off and Drain-Off Leakage Currents are in the range of nA.

Notes: 1. Noise at V_DDA,V_SSA<40 mV

2.Excluding Pad Capacitance.

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ST52T301/E301

INSTRUCTION SET

ADD

Addition

Format:

ADD regi, regj

Operation:

regi <- regi + regj

Description: The contentsof the Register File j-th register specified as source is added to the destina-

tion i-th register, leaving the result in the destination register.The result is 255 if overflow

occurs.

Flags:

Z set if result is zero, cleared otherwise.

S set if overflow, cleared otherwise.

Bytes:

2

7

Cycles:

Example:

If the register 4 containsthe value 45 and the register 11 contains the value 15, then the

instruction

ADD 4,11

1001000

0100|1011

causes the register 4 of the Register File to be loaded with the value 60.

If the register 4 contains the value 200 and the register 11 containsthe value 100, the in-

struction causes the register 4 to be loaded with the value 44 (result-256) and the S flag

to be set

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ST52T301/E301

AND

Logical AND

Format:

AND regi, regj

regi <- regi AND regj

Operation:

Description: The instruction logically ANDs the contents of the RegisterFile j-th register specified as

source and the destinationi-th register in the Register File, leaving the result in the desti-

nation register.

Flags:

Z set if result is zero, cleared otherwise.

S not affected.

Bytes:

2

7

Cycles:

Example:

If the register 4 containsthe value 10011100and the register 12 containsthe value

01010101, then the instruction

AND 4,12

10010001 0100|1100

causes the register 4 of the Register File to be loaded with the value 00010100.

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ST52T301/E301

CON

Consequent

Format:

CON cost

Operation:

Dividend Register <- Dividend Register + cost*teta

Divisor <- Divisor + teta

Description: This intruction computes the values to add in the defuzzification registers, at the end of

the single rule. The specified constantis the crisp value representingthe output crisp

membership function:it is multiplied by the last fuzzy operation result.

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ST52T301/E301

DATA

Membership Functions data

Format:

DATA var mbf lvd vtx rvd

Operation:

ADM location 16*var+mbf

<- lvd

<- vtx

<- rvd

ADM location 16*var+mbf+64

ADM location 16*var+mbf+128

Description: This instruction is a pseudoinstruction (it does not correspond to any operation executed

by the processor) that allows to store membership functions data in the ADM (Antece-

dent Data Memory).The var and the mbf data identify the membership function.The lvd

data is the left semibase distance of the M.F., the vtx data is the position of the vertex

and rvd is the right semibase distance.

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ST52T301/E301

FZAND

Fuzzy AND

Format:

FZAND

K <- stack0 AND stack1

Operation:

Description: This instruction computes the AND operation between the two values stored in the fuzzy

stack, previously loaded with LDP, LDN or LDK instructions,and storesit in the register

K.

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ST52T301/E301

FZOR

Fuzzy OR

Format:

FZOR

Operation:

K <- stack0 OR stack1

Description: This instruction computes the OR operation between the two values stored in the fuzzy

stack, previously loaded with LDP, LDN or LDK instructions and stores it in the register K.

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ST52T301/E301

IRQ

InterruptVector

Format:

IRQ int label

interrupt vector <- label

Operation:

(PC = Program Counter)

Description: This instruction allows to specify the interrupt int service routine start address at label lo-

cation.

Flags:

Z,S not affected.

Bytes:

2

6

Cycles:

Example:

The instruction:

IRQ 1 IntRout1

determinates that if interrupt 1 is serviced, the programcounter (PC) is loaded with the

memory address value labelled with IntRout1.

Remark:

The instruction IRQ is a dummy instruction used to store data in the chip memory.It is

neither stored in memory nor executed.A series of IRQ instructions must be ended by a

dummy end operation.

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ST52T301/E301

IRQM

Mask Interrupt

Format:

IRQM mask

interrupt mask register <- mask

Operation:

Description: The interrupts are masked with the specified mask.

Flags:

Z,S not affected.

Bytes:

2

6

Cycles:

Example:

The instruction:

IRQM 10

1011|1110 00001010

enablesthe interrupts 1 and 3 and disables all the others.

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ST52T301/E301

IRQP

Interrupt Priority

Format:

IRQP cost

Operation:

interrupt priority register <- cost

Description: The interrupts priority is set according the specified values.

Flags:

Z,S not affected.

Bytes:

2

6

Cycles:

Example:

The instruction:

IRQP 198

1011|1111 11|00|01|10

determines the interrupt 2 to have highest priority, interrupt 1 mediumpriority and inter-

rupt 0 lower priority.

Remark:

each couples of bits must have different values, that is interrupts must have different

priority level.enablesthe interrupts 1 and 3 and disables all the others.

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ST52T301/E301

JP

Unconditional Jump

Format:

JP addr

Operation:

PC <- addr

(PC = ProgramCounter)

Description: The instruction replaces the PC value with the specified value causing an unconditional

jump to another location in the program memory.

Flags:

Z,S not affected.

Bytes:

2

6

Cycles:

Example:

The instruction:

JP 1123

1010|0100 01100011

causes the PC to be loaded with the value 1123 and the program to continue

from that location.

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ST52T301/E301

JPNS

Jump on Non Sign Flag

Format:

JPNS addr

Operation:

if S=0,PC <- addr

(PC = ProgramCounter)

Description: If the S flag is cleared then the PC value is replaced with the specifiedvalue, causing a

jump to another location in the program memory.

Flags:

Z,S not affected.

Bytes:

2

Cycles:

Example:

6

If the S flag is cleared then the instruction:

JPNS 1123

1111|0100 01100011

causes the PC to be loaded with the value 1123 and the program to continue from that

location.

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ST52T301/E301

JPNZ

Jump on Non Zero Flag

Format:

JPNZ addr

Operation:

if Z=0, PC <- addr

(PC = ProgramCounter)

Description: If the Z flag is cleared then the PC value is replaced with the specified value, causing a

jump to another location in the program memory.

Flags:

Z,S not affected.

Bytes:

2

Cycles:

Example:

6

If the Z flag is cleared then the instruction:

JPNZ 1123

1101|0100 01100011

causes the PC to be loaded with the value 1123 and the program to continue from that

location.

72/99

ST52T301/E301

JPS

Jump on Sign Flag

Format:

JPS addr

Operation:

if S=1,PC <- addr

(PC = ProgramCounter)

Description: If the S flag is set then the PC value is replaced with the specified value, causing a jump

to another location in the programmemory.

Flags:

Z,S not affected.

Bytes:

2

Cycles:

Example:

6

If the S flag is set then the instruction:

JPS 1123

1110|0100 01100011

causes the PC to be loaded with the value 1123 and the program to continue from that

location.

73/99

ST52T301/E301

JPZ

Jump on Zero Flag

Format:

JPZ addr

Operation:

if Z=1, PC <- addr

(PC = Program Counter)

Description: If the Z flag is set then the PC value is replaced with the specified value, causing a jump

to another location in the programmemory.

Flags:

Z,S not affected.

Bytes:

2

Cycles:

Example:

6

If the Z flag is set then the instruction:

JPZ 1123

1110|0100 01100011

causes the PC to be loaded with the value 1123 and the program to continue from that

location.

74/99

ST52T301/E301

LDCF

Load Constant into Configuration Register

Format:

LDCF conf, const

conf <- const

Operation:

Description: The immediate constant value (const) specified as source is loaded into the destination

peripheral configuration register (conf).

Flags:

Z,S not affected.

Bytes:

2

Cycles:

Example:

6

The instruction:

LDCF 5,43

1011|0101 00101011

causes the peripheral configurationregister 5 to be loaded with the value43.

75/99

ST52T301/E301

LDK

Load Stack with K register

Format:

LDK

Operation:

stack0 <- K

Description: This instruction loads in the stack the value temporarily stored in the registerK that is

the result of the last fuzzy operation.

76/99

ST52T301/E301

LDM

Load Stack with M register

Format:

LDM

Operation:

stack0 <- M

Description: This instruction loads in the stack the value temporarily stored in the registerM with a

SKM operation.

77/99

ST52T301/E301

LDN

Load Negative alpha value

Format:

LDN var mbf

Operation:

stack <- 15 - computed alpha value related to mbf M.F.of varVariable

Description: This instruction performs the fuzzyfication and loads in the stack the negated alpha

value of the M.F.mbf of var Variable.

78/99

ST52T301/E301

LDP

Load Positive alpha value

Format:

LDP var mbf

Operation:

stack <- computed alpha value related to mbf M.F.of var Variable

Description: This instruction performs the fuzzyfication and loads in the stack the alpha value of the

M.F.mbf of varVariable.

79/99

ST52T301/E301

LDPR

Load Register into Peripheral Register

Format:

LDPR per, reg

Operation:

per <- reg

Description: The contentsregister specified as source (reg) is loaded into the destinationperipheral

register (per).

Flags:

Z, S not affected.

Bytes:

1

Cycles:

Example:

5 (6 if parallel port with H/S is addressed)

If the register 7 of the Register File contains the value 25 then the instruction:

LDPR 2,7

01|10|0111

causes the register 2 of the Peripheral Register (i.e. parallel port) to be loaded with the

value 25.

80/99

ST52T301/E301

LDRC

Load constant into Register

Format:

LDRC reg, const

reg <- const

Operation:

Description: The immediate constant value specified as source is loaded into the destinationregister

in the Register File.

Flags:

Z,S not affected.

Bytes:

2

Cycles:

Example:

6

The instruction:

LDRC 5,43

1000|0101 00101011

causes the register 5 of the Register File to be loaded with the value 43.

81/99

ST52T301/E301

LDRI

Load Input register into Register file

Format:

LDRI reg, inp

reg <- inp

Operation:

Description: The contentsof a input register specified as source (inp) is loaded into the destination

register in the Register File (reg).

Flags:

Z,S not affected.

Bytes:

2

Cycles:

Example:

6

If the register 2 of the A/D converter contains the value 25 then the instruction:

LDRI 5,2

000|xxxxx 0101|0010

x = don’t care

causes the register 5 of the Register file to be loaded with the value 25.

82/99

ST52T301/E301

LDRR

Load Register into Register

Format:

LDRR regi, regj

regj <- regi

Operation:

Description: The contentsof the Register File j-th register specified as source is loaded into the desti-

nation i-th register.

Flags:

Z,S not affected.

Bytes:

2

Cycles:

Example:

6

If the register 2 of the Register File contains the value 25 then the instruction:

LDRR 5,2

100101100101|0010

causes the register 5 of the Register file to be loaded with the value 25.

83/99

ST52T301/E301

MDGI

Macro Disable Global Interrupt

Format:

MDGI

Operation:

MGI bit <- 0

Description: All the interrupts are disabledby this instruction.This instruction is used by FUZZYSTU-

DIO 3.0 Compiler macros to disableinterrupt during macro execution.

Flags:

Z,S not affected.

Bytes:

1

Cycles:

Example:

4

After the instruction:

MDGI

10011010

all the interrupts cannot be acknowledged and remain pending

84/99

ST52T301/E301

MEGI

Macro Enable Global Interrupt

Format:

MDGI

Operation:

MGI bit <- 1

Description: The not masked interrupts are enabledby this instruction only if a UDGI instruction has

not specified before, not followedby a UEGI instruction.This instruction is used by

FUZZYSTUDIO 3.0 Compiler macros to disable interrupt during macro execution.

Flags:

Z,S not affected.

Bytes:

1

Cycles:

Example:

4

After the instruction:

MEGI

10011011

not masked interrupts can be acknowledged if the interrupts are not globally disabledby

the UDGI instruction

85/99

ST52T301/E301

OUT

Output computation

Format:

OUT const

Operation:

Output Register const <- defuzzyficationresult of the const output

Description: This instruction performs the defuzzyfication of the specified output (const can assume

only the values 0 or 1) and loads in the correspondent Fuzzy Output Register the result.

86/99

ST52T301/E301

RETI

Return from Interrupt

Format:

RETI

Operation:

PC <- stack

Z <- stack

S <- stack

Description: This instruction resumes the program executionexactly at the point it was left when an in-

terrupt occurred.Z and S flag are set to the status they had when the interrupt service

routine was started.

Flags:

Z,S restored to the original setting before an interrupt occured.

Bytes:

1

5

Cycles:

Example:

If the PC stack contains the value 1123 and the program is processingan interrupt ser-

vice routine, then the instruction

RETI

10010101

causes the PC to be loaded with the value 1123 and the flags to be restored to the

status beforethe interrupt occurred.

87/99

ST52T301/E301

RINT

Reset Interrupt

Format:

RINT int

Operation:

cancel pending interrupt n. int

Description: The specified pending interrupt is cancelled if not currently in service.

Flags:

Z,S not affected.

Bytes:

1

Cycles:

Example:

4

The instruction:

RINT

2

0001|x|010

x = don’t care

causes the bit 2 of the interrupt pending register to be cleared so that the interrupt 2 is

not acknowledged.

Remark:

The use of RINT istruction has no effectif a specifiedinterrupt has already been aknowl-

edged and related service routine has not been completed.

88/99

ST52T301/E301

SKM

Store K register in M register

Format:

SKM

Operation:

M <- K

Description: This instruction stores the result of the last performed fuzzy operation(stored in the tem-

porary register K) in the temporary bufferM.

89/99

ST52T301/E301

SRX

SCI Reception

Format:

SRX regi

Operation:

regi <- SCDR_RX

Description: The contentsof the SCDR_RX block of the SCI receiver block, is transferredin the Reg-

ister File i-th register specified as destination.

Flags:

Z,S not affected.

Bytes:

2

5

Cycles:

Example:

If the SCDR_RX block of the SCI receiver block containsthe value 45, then the instruc-

tion

SRX 4

00101101

causes the register 4 of the Register File to be loaded with the value 45.

90/99

ST52T301/E301

STOP

Stop Program Execution

Format:

STOP

Operation:

Stop section

Description: This instruction separates arithmetic instructions and fuzzy instructions.Also it ends a

IRQ specificationsection.

Flags:

Z,S not affected.

Bytes:

1

Cycles:

Example:

4

The instruction:

STOP

10010111

if put after arithmetic instructions, it allows to start a block of fuzzy instruction and vice

versa.

91/99

ST52T301/E301

STX

SCITransmission

Format:

STX regi

Operation:

SCDR_TX <- regi

Description: The contentsof the Register File i-th register specified as source is transferred in the

SCDR_TX block of the SCI transmitter block, to be transmitted.

Flags:

Z,S not affected.

Bytes:

2

Cycles:

Example:

5

If the register 4 containsthe value 45, then the instruction

STX 4

00101101

causes the serial transmission of 45.

92/99

ST52T301/E301

SUB

Subtraction

Format:

SUB regi, regj

regi <- regi -regj

Operation:

Description: The contentsof the Register File j-th register specified as source is subtractedfrom the

destinationi-th register, leaving the result in the destinationregister.

Flags:

Z set if result is zero, cleared otherwise.

S set if underflow,cleared otherwise.

Bytes:

2

7

Cycles:

Example:

If the register 4 containsthe value 45 and the register 11 contains the value 15, then the

instruction

SUB 4,11

10010010 0100|1011

causes the register 4 of the Register File to be loaded with the value 30.

If the register 4 contains the value 100 and the register 11 containsthe value 200, the in-

struction causes the register 4 to be loaded with the value 156 (result+256) and the S

flag to be set.

93/99

ST52T301/E301

SUBO

Subtraction with Offset

Format:

SUBO regi, regj

Operation:

regi <- regi - regj +128

Description: The contents of the Register File register specified as source are subtractedfrom the

destinationregister in the Register File, the value 128 is added to the result that is stored

in the destinationregister.This operation allows the use of the signed byte considering

the values between0 and 127 as negative,128 as 0, and the values between 129 and

255 as positive.

Flags:

Z set if result is zero or if overflow occurs, cleared otherwise.

S set if underflowor overflow, cleared otherwise.

Bytes:

2

7

Cycles:

Example:

If the register 4 containsthe value 45 and the register 11 contains the value 15, then the

instruction

SUBO 4,11

10010011 0100|1011

causes the register 4 of the Register File to be loaded with the value 158. The value 45

correspondsto -83, the value 11 correspondsto -113; so the operation is equivalentto

perform -83 - (-113) = 30.As a matterof fact the result 158 corresponds to the value 30.

If the register 4 containsthe value 50 and the register 11 contains the value 200, the in-

struction causes the register 4 to be loaded with the value 234 (result+256) and the S

flag to be set.

If the register 4 containsthe value 200 and the register 11 contains the value 50, the in-

struction causes the register 4 to be loaded with the value 22 (result-256) and the S and

Z flags to be set.

94/99

ST52T301/E301

UDGI

User Disable Global Interrupt

Format:

UDGI

Operation:

UGI bit <- 0

Description: All the interrupt are disabled by this instruction.

Flags:

Z,S not affected.

Bytes:

1

Cycles:

Example:

4

After the instruction:

UDGI

10011000

all the interrupts cannot be acknowledged and remain pending.

95/99

ST52T301/E301

UEGI

User Enable Global Interrupt

Format:

UEGI

Operation:

UGI bit <- 1

Description: All the interrupts are enabledby this instruction.

Flags:

Z,S not affected.

Bytes:

1

Cycles:

Example:

4

After the instruction:

UEGI

10011001

not masked interrupts can be acknowledged if the interrupt are not globally disabled by

the MDGI instruction.

96/99

ST52T301/E301

WAITI

Wait for interrupt

Format:

WAITI

Operation:

Wait state

Description: This instruction causes the program to stop, without halting the peripherals, until an inter-

rupt occurs..

Flags:

Z,S not affected.

Bytes:

1

Cycles:

Example:

4

The instruction:

WAITI

10010100

halts the program executionleaving the peripherals running on, until an interrupt occurs.

97/99

ST52T301/E301

CLCC44 PACKAGE MECHANICAL DATA

mm

inch.

DIM

MIN

17.27

16.33

TYP

MAX

17.78

16.81

MIN

.680

.643

TYP

MAX

.662

A

B

C

12.01

13.03

1.30

.475

.513

0.52

C1

c1

D

1.82

2.23

0.72

.640

.088

.660

d1

d2

E

0.889

2.362

.035

.093

16.26

16.76

e

1.27

.050

.500

.017

.030

.038

.020

.040

.030

e3

F

12.50

0.431

0.762

0.965

0.508

1.016

0.762

F1

F2

M

M1

R

98/99

ST52T301/E301

PLCC44 PACKAGEMECHANICAL DATA

mm

inch.

TYP

DIM

MIN

17.4

16.51

3.65

4.2

TYP

MAX

17.65

16.65

3.7

MIN

MAX

0.695

0.656

1.146

0.180

0.108

A

B

0.685

0.650

0.144

0.165

0.102

C

D

4.57

2.74

d1

d2

E

2.59

0.68

0.027

14.99

16

0.590

0.630

e

1.27

0.46

0.71

0.050

0.500

0.018

0.028

e3

F

F1

G

0.101

0.004

M

M1

1.16

1.14

0.046

0.045

99/99

ST52T301/E301

ORDERING INFORMATION

PART NUMBER

PACKAGE

ST52E301/C

ST52T301/P

CLCC44-W

PLCC44

Full Product Information at http://www.st.com

Information furnished is believed to be accurateand reliable.However, STMicroelectronics assumes no responsibility for the consequences of

use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to

change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in lifesupport devicesor systems withoutexpress written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics

FUZZYSTUDIO is a registered trademarkof STMicroelectronics

DuaLogic

is a trademark of STMicroelectronics

MS-DOS , Microsoft andMicrosoftWindows areregistered trademarks ofMicrosoftCorporation.

MATLAB is a registered trademark of Mathworks Inc.

STMicroelectronics GROUP OF COMPANIES

Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands -

Singapore - Spain - Sweden- Switzerland - Taiwan- Thailand - United Kingdom - U.S.A.


型号：	ST52T301P
厂家：	ST
描述：	8-Bit OTP/EPROM DuaLogic] MCUs WITH ADC, UART, TIMER, TRIAC & PWM DRIVER 8位OTP / EPROM DuaLogic ]的MCU与ADC ， UART ，定时器， TRIAC和PWM驱动器驱动器三端双向交流开关可编程只读存储器电动程控只读存储器
文件：	总100页 (文件大小：496K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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