ST52T410G0M6_技术文档

ST52T410/T420/

E420

ST52T410/T420/E420

®

8-BIT INTELLIGENT CONTROLLER UNIT (ICU)

Three Timer/PWMs, ADC, WDG

PRELIMINARY DATASHEET

Memories

Up to 4 Kbytes OTP

128 bytes of RAM

Readout Protection

Core

Register File Based Architecture

55 instructions

Hardware multiplication and division

Decision Processor for the implementation of

Fuzzy Logic algorithms

Clock and Power Supply

Up to 20 MHz clock frequency.

Power Saving features

Interrupts

Up to 5 interrupt vectors

Top Level External Interrupt (INT)

I/O Ports

19 I/O PINs configurable in Input and Output

mode

High current sink/source in all pins.

Peripherals

Development tools

3 Programmable 8-bit Timer/PWMs with internal

16-bit Prescaler featuring:

High level Software tools

Emulator

– PWM output

Low cost Programmer

Gang Programmer

– Input capture

– Output compare

– Pulse generator mode

On-chip 8-bit Sample and Hold A/D Converter

with 8-channel analog multiplexer (ST52T420/

E420 only)

Watchdog timer

Rev. 1.6 - November 2002

1/84

ST52T410/T420/E420

ST52T410/ST52x420 Device Summary

Timers

Operating

Supply

Device

NVM

RAM

ADC

SCI

Watchdog

I/O

Package

PWM

3x8-bit

ST52T420G0py

ST52T420G1py

ST52T420G2py

ST52E420G2D6

ST52T410G0py

ST52T410G1py

ST52T410G2py

1K OTP

2K OTP

4K OTP

4K EPROM

1K OTP

2K OTP

4K OTP

128

8-Ch

-

Yes

3.0-5.5 V

2.7-5.5 V

19

Dip/So 28

Cdip 28

Dip/So 28

2/84

ST52T410/T420/E420

TABLE

TENTS

OF

CON-

TABLE OF CONTENTS

1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

1.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

1.2.1 Memory Programming Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.2.2 Working mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.3 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

2 INTERNAL ARCHITECTURE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.1 ST52T410/ST52x420 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

2.2 Control Unit and Data Processing Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

2.2.1 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.2.2 Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.3 Address Spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

2.3.1 RAM and STACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.3.2 Input Registers Bench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.3.3 Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.3.4 Output Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.4 Arithmetic Logic Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

3 EPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.1 EPROM Programming Phase Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

3.1.1 EPROM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.1.2 EPROM Locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.1.3 EPROM Writing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.1.4 EPROM Read/Verify Margin Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.1.5 Stand by Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.1.6 ID code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.2 Eprom Erasure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

4 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.1 Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

4.2 Global Interrupt Request Enabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

4.3 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

4.4 Interrupt Maskability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

4.5 Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

4.6 Interrupts and Low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

4.7 Interrupt RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

5 CLOCK, RESET & POWER SAVING MODE. . . . . . . . . . . . . . . . . . . . . . . . . . 34

5.1 System Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

5.2 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

5.3 Power Saving Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

5.3.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

5.3.2 Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

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ST52T410/T420/E420

6 FUZZY COMPUTATION (DP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

6.1 Fuzzy Inference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

6.2 Fuzzyfication Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

6.3 Inference Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

6.4 Defuzzyfication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

6.5 Input Membership Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

6.6 Output Singleton . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

6.7 Fuzzy Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

7 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

7.2 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

7.3 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

7.4 Alternate Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

7.5 I/O Port Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

8 A/D CONVERTER (ST52X420 ONLY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

8.2 Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

8.2.1 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

8.2.2 Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

8.3 A/D Registers Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

9 WATCHDOG TIMER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

9.1 Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

9.2 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

10 PWM/TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

10.1 Timer Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

10.2 PWM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

10.3 Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

11 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

11.1 Parameter Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

11.1.1 Minimum and Maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

11.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

11.1.3 Typical curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

11.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

11.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

11.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

11.3 Recommended Operating Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

11.4 Supply Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

11.5 Clock and Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

11.6 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

11.7 ESD Pin Protection Strategy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

11.7.1 Standard Pin Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

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11.7.2 Multi-supply Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

11.8 Port Pin Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

11.8.1 General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

11.9 Control Pin Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

11.9.1 RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

11.9.2 VPP pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

11.10 8-bit A/D Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

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1 GENERAL DESCRIPTION

1.1 Introduction

ST52T410/ST52x420 are 8-bit Intelligent Control

Units (ICU) of the ST Five Family, which can

perform both boolean and fuzzy algorithms in an

efficient manner, in order to reach the best

performances that the two methodologies allow.

ST5 2T410 /ST5 2x42 0 are p rodu ced b y

STMicroelectronics using the reliable high

performance CMOS process, including integrated-

on-chip peripherals that allow maximization of

system reliability, decreasing system costs and

minimizing the number of external components.

The flexible I/O configuration of ST52x400/440

allows for an interface with a wide range of external

devices, like D/A converters or power control

devices.

ST52x420 includes an 8-bit Analog to Digital

Converter with an 8-analog channel Multiplexer.

Single/Multiple channels and Single/Sequence

conversion modes are supported.

In order to optimize energy consumption, two

different power saving modes are available: Wait

mode and Halt mode.

Program Memory (EPROM/OTP) addressing

capability addresses up to 8 Kbytes of memory

locations to store both program instructions and

permanent data.

EPROM can be locked by the user to prevent

external undesired operations.

Operations may be performed on data stored in

RAM, allowing the direct combination of new input

and feedback data. All bytes of RAM are used like

Register File.

OTP (One Time Programmable) version devices

are fully compatible with the EPROM windowed

version, which may be used for prototyping and

pre-production phases of development.

ST52T410/ST52x420 pins are configurable,

allowing the user to set the input or output signals

on each single pin.

A powerful development environment consisting of

a board and software tools allows an easy

configuration and use of ST52T410/ST52x420.

TM

A hardware multiplier (8 bit by 8 bit with 16 bit

result) and a divider (16 bit over 8 bit with 8 bit

result and 8 bit remainder) are available to

implement complex functions by using a single

instruction. The program memory utilization and

computational speed is optimized.

Fuzzy Logic dedicated structures in ST52T410/

ST52x420 ICU’s can be exploited to model

complex systems with high accuracy in a useful

and easy way.

The VISUAL FIVE

software tool allows

development of projects through a user-friendly

graphical interface and optimization of generated

code.

1.2 Functional Description

ST52T410/ST52x420 ICUs can work in two

modes:

Fuzzy Expert Systems for overall system

management and fuzzy Real time Controls can be

designed to increase performances at highly

competitive costs.

■ Memory Programming Mode

The linguistic approach characterizing Fuzzy Logic

is based on a set of IF-THEN rules, which describe

the control behavior, as well as on Membership

Functions, which are associated to input and

output variables.

Up to 334 Membership Functions, with triangular

and trapezoidal shapes, or singleton values are

available to describe fuzzy variables.

■ Working Mode

according to RESET and Vpp signals levels (see

pins description).

Note: When RESET=0 it is advisable not to use

the sequence “101010“ to port PA (7 : 2).

1.2.1 Memory Programming Mode.

Th e Timer /PW M pe riph era l allo ws the

management of power devices and timing signals,

implementing different operating modes and high

frequency PWM (Pulse With Modulation) controls.

Input Capture and Output Compare functions are

available on the TIMER.

The programmable Timer has a 16 bit Internal

Prescaler and an 8 bit Counter. It can use internal

or external Start/Stop signals and clock.

The ST52T410/ST52x420 memory is loaded in the

Memory Programming Phase. All fuzzy and

standard instructions are written inside the

memory.

This phase starts by setting the control signals as

illustrated below:

RESET

TEST

V

PP

12V/V

DD

An internal programmable Watchdog is available

to avoid loop errors and to reset the ICU.

V

ss

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ST52T410/T420/E420

When this phase starts, the ST52T410/ST52x420

core are set to RESET status; then 12V are applied

to the Vp p pin in o rder to start EPROM

programming. A signal applied to PB1 is used to

increment the memory address; the data is

supplied to PORT A (see EPROM programming for

further details).

processing of boolean functions and fuzzy

algorithms.

The CU/DPU can manage up to 334 different

Membership Functions for the fuzzy rules

antecedent part. The rule consequents are “crisp”

values (real numbers). The maximum number of

rules that can be defined is limited by the

dimensions of the implemented standard

algorithm.

1.2.2 Working mode.

EPROM is then shared between fuzzy and

standard algorithms. The Membership Function

data is stored inside the first 1024 memory

locations. The Fuzzy rules are parts of the program

instructions.

Below are the control signals of this mode:

RESET

TEST

V

PP

V

DD

SS

The Control Unit (CU) reads the information and

the status deriving from the peripherals.

The processor starts the working phase following

the instructions, which have been previously

loaded in the memory.

ST52T410/ST52x420’s internal structure includes

a computational block, CONTROL UNIT (CU) /

DATA PROCESSING UNIT (DPU), which allows

Arithmetic calculus can be performed on these

values by using the internal CU and the 128 bytes

of RAM, which supports all computations. The

peripheral input can be fuzzy and/or arithmetic

output, or the values contained in Data RAM and

EPROM locations.

Figure 1.1 ST52x420 SO28 Pin Configuration

V^DD

1

28

27

26

25

24

23

22

21

20

19

18

17

16

15

RESET

2

OSCOUT

VSS

SO28

3

OSCIN

VPP

4

TEST

PA0/T0RES

5

INT/PC0

PA1/T0OUT

PA2/T1OUT

PA3/T2OUT

PA4/T0STRT

PA5/T0CLK

PA6

6

T0OUT/PC1

7

T1OUT/PC2

8

T2OUT/PC3

9

Ain0/PB0

10

Ain1/PB1

11

PA7/PB7/Ain7

PB6/Ain6

Ain2/PB2

12

Ain3/PB3

13

PB5/Ain5

V^DDA

14

PB4/Ain4

GNDA

8/84

ST52T410/T420/E420

Figure 1.2 ST52x420 PDIP28 Pin Configuration

VDD

VSS

1

28

27

26

25

24

23

22

21

20

19

18

17

16

15

RESET

2

OSCOUT

OSCIN

PDIP28

3

VPP

4

TEST

PA0/T0RES

5

INT/PC0

T0OUT/PC1

T1OUT/PC2

T2OUT/PC3

Ain0/PB0

Ain1/PB1

Ain2/PB2

Ain3/PB3

V^DDA

PA1/T0OUT

PA2/T1OUT

PA3/T2OUT

PA4/T0STRT

PA5/T0CLK

PA6

6

7

8

9

10

11

12

13

14

PA7/PB7/Ain7

PB6/Ain6

PB5/Ain5

PB4/Ain4

GNDA

Figure 1.3 ST52T410 SO28 Pin Configuration

V^DD

1

28

RESET

2

27

26

25

24

23

22

21

20

19

18

17

16

15

OSCOUT

VSS

SO28

3

OSCIN

TEST

VPP

4

PA0/T0RES

5

INT/PC0

T0OUT/PC1

T1OUT/PC2

T2OUT/PC3

PB0

PA1/T0OUT

PA2/T1OUT

6

7

PA3/T2OUT

PA4/T0STRT

PA5/T0CLK

PA6

8

9

10

11

12

13

14

PB1

PA7/PB7

PB6

PB2

PB3

PB5

V^DDA

PB4

GNDA

9/84

ST52T410/T420/E420

Figure 1.4 ST52410 PDIP28 Pin Configuration

VDD

VSS

1

28

27

26

25

24

23

22

21

20

19

18

17

16

15

RESET

2

OSCOUT

PDIP28

3

OSCIN

TEST

VPP

4

PA0/T0RES

5

INT/PC0

T0OUT/PC1

T1OUT/PC2

T2OUT/PC3

PB0

PA1/T0OUT

PA2/T1OUT

6

7

PA3/T2OUT

PA4/T0STRT

PA5/T0CLK

PA6

8

9

10

11

12

13

14

PB1

PA7/PB7

PB6

PB2

PB3

PB5

V^DDA

PB4

GNDA

10/84

ST52T410/T420/E420

Table 1.1 ST52T410/ST52x420 SO28 & PDIP28 Pin list

SO28

NAME

Programming Phase

Working Phase

Pins

1

RESET

OSCOUT

OSCIN

General Reset

Oscillator Output

2

3

Oscillator Input

4

TEST

Must be tied to Vss

5

INT/PC0

PHASE signal (PHASE)

External interrupt, Digital I/O

Timer/PWM 0 output, Digital I/O

Timer/PWM 1 output, Digital I/O

Timer/PWM 2 output, Digital I/O

Analog Input (*), Digital I/O

Analog Power Supply (*)

Analog Ground (*)

6

T0OUT/PC1

T1OUT/PC2

T2OUT/PC3

Ain0/PB0

Ain1/PB1

Ain2/PB2

Ain3/PB3

V^DDA

7

8

9

Address Reset (RST_ADD)

Address Increment (INC_ADD)

Configuration Reset (RST_CONF)

Configuration Increment

Analog Power Supply

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

GNDA

Analog Ground

Ain4/PB4

Ain5/PB5

Ain6/PB6

Ain7/PB7/PA7

PA6

Analog Input (*), Digital I/O

Digital I/O

I/O EPROM Data

T0CLK/PA5

T0STRT/PA4

T2OUT/PA3

T1OUT/PA2

T0OUT/PA1

T0RES/PA0

Timer/PWM 0 clock, Digital I/O

Timer/PWM 0 start/stop, Digital I/O

Timer/PWM 2 compl. output, Digital I/O

Timer/PWM 1 compl. output, Digital I/O

Timer/PWM 0 compl. output, Digital I/O

Timer/PWM 0 Reset, Digital I/O

EPROM VDD or Vss

EPROM Programming Power

26

V^PP

supply (12V ± 5%)

27

28

V^ss

Digital Ground

VDD

Digital Power Supply

(*) ST52x420 only

11/84

ST52T410/T420/E420

1.3 Pin Description

Ain0-Ain7. These 8 lines are connected to the

input of the analog multiplexer. They allow the

acquisition of 8 analog input (ST52x420 only).

During the Programming phase, Ain0, Ain1, Ain2

and Ain3 are used to manage EPROM operation.

V

, V , V

, GNDA, V . In order to avoid

DD

SS

DDA PP

noise disturbances, the power supply of the digital

part is kept separate from the power supply of the

analog part.

PA0-PA7, PB0-PB7, PC0-PC3. These lines are

organized as I/O port. Each pin can be configured

as input or output. PA7/PB7 are tied to the same

output. During Programming phase PA port is used

for EPROM read/write data.

V

Main Power Supply Voltage (5V± 10%).

DD.

In the ST52x410 version the two V pins must be

connected togheter.

V

DD

. Digital circuit ground.

SS

In the ST52x410 version the two V pins must be

connected togheter.

T0RES, T0CLK, T0STRT. These pins are related

with the internal Programmable Timer/PWM 0.

This Timer can be reset externally by using

T0RES. In Working Mode, T0RES resets the

address counter of the Timer. T0RES is active at

low level.

The Timer 0 Clock can be the internal clock or can

be supplied externally by using pin T0CLK.

An external Start/Stop signal can be used to

control the Timer through T0STRT pin.

SS

V

. Analog V

of the Analog to Digital

DDA

DD

Converter.

GNDA. Analog V

Converter. Must be tied to V

of the Analog to Digital

SS

SS.

V

. Main Power Supply for internal EPROM

PP

(12.5V±5%, in programming phase) and Operating

MODE selector. During the Programming phase

(programming), V

must be set at 12V. In the

PP

Working phase V must be equal to V

.

T0OUT, T1OUT, T2OUT. The TIMER/PWM

PP

SS

outputs are available on these pins.

OSCin and OSCout. These pins are internally

connected with the on-chip oscillator circuit. A

quartz crystal or a ceramic resonator can be

connected between these two pins in order to allow

the correct operations of ST52T410/ST52x420

with various stability/cost trade-off. An external

clock signal can be applied to OSCin, in this case

OSCout must be floating.

T0OUT, T1OUT, T2OUT. The TIMER/PWM

complementary outputs are available on these

pins.

TEST. During the Programming and Working

phase it must be set to Vss.

INT. This pin is used to start the External Interrupt

routine.

RESET. This signal is used to restart ST52T410/

ST52x420 at the beginning of its program and to

select the program mode for EPROM.

12/84

ST52T410/T420/E420

Figure 1.5 ST52X420 Block Diagram

TIMER/PWM 0

PROGRAM

MEMORY

TIMER/PWM 1

TIMER/PWM 2

EPROM

CORE

INTERRUPTS

CONTROLLER

PA7:0

PC3:0

PB7:0

PORT A

PORT C

ALU &

DPU

DECISION

PROCESSOR

CONTROL

UNIT

PORT B

ADC

Register File

128 bytes

Input

registers

VDDA

GNDA

WATCHDOG

PC

FLAGS

POWER SUPPLY

OSCILLATOR

RESET CIRCUIT

VDD VPP

VSS

OSCIN OSCOUT

RESET

13/84

ST52T410/T420/E420

Figure 1.6 ST52X410 Block Diagram

PROGRAM

MEMORY

TIMER/PWM 0

EPROM

TIMER/PWM 1

TIMER/PWM 2

CORE

INTERRUPTS

CONTROLLER

ALU &

DPU

PA7:0

PC3:0

PB7:0

PORT A

PORT C

DECISION

PROCESSOR

CONTROL

UNIT

Register File

128 bytes

Input

registers

PORT B

WATCHDOG

PC

FLAGS

POWER SUPPLY

OSCILLATOR

RESET CIRCUIT

VDD VPP VSS

OSCIN OSCOUT

RESET

14/84

ST52T410/ST52T420/E420

2 INTERNAL ARCHITECTURE

ST52T410/ST52x420 are made up of the following

blocks and peripherals:

parts of the CU so that only one part of the system

is activated during working mode.

The CU structure is very flexible. It was designed

with the purpose of easily adapting the core of the

microcontroller to market needs. New instruction

sets or new peripherals can be easily included

■ Control Unit (CU) and Data Processing Unit

(DPU)

■ ALU / Fuzzy Core

■ EPROM

without

changing

the

structure

of

the

microcontroller, maintaining code compatibility.

The CU reads the instructions stored on EPROM

(Fetch) and decodes them. According to the

instruction types, the arbiter activates one of the

main blocks of the CU. Afterwards, all the control

signals for the DPU are generated.

■ 128 Byte RAM

■ Clock Oscillator

■ Analog Multiplexer and A/D Converter

(ST52x420 only)

A set of 46 different arithmetic, fuzzy and logic

instructions is available. Each instruction requires

6 (fuzzy instructions) to 26 (DIVISION) clock

pulses to be performed.

■ 3 PWM / Timers

■ Digital I/O port

The DPU receives, stores and sends instructions

deriving from EPROM, RAM or peripherals in order

to execute them.

2.1 ST52T410/ST52x420 Operating Modes

ST52T410/ST52x420 works in two modes,

Programming and Working Modes, depending on

the control signals level RESET, TEST and V

PP

2.2.1 Program Counter.

The Operating modes are selected by setting the

control signal level as specified in the Control

Signals Setting table.

The Program Counter (PC) is a 12-bit register that

contains the address of the next memory location

to be processed by the core. This memory location

may be an opcode, operand, or an address of an

operand.

Table 2.1 Control Signals Setting

The 12-bit length allows direct addressing of a

maximum of 4,096 bytes in the program space.

After having read the current instruction address,

the PC value is incremented. The result of this

operation is shifted back into the PC.

Control

Signal

Pro-

gramming

Reset

Working

RESET

TEST

V^SS

VSS

VDD

VSS

The PC can be changed in the following ways:

VSS

■ JP (Jump)PC = Jump Address

■ InterruptPC = Interrupt Vector

■ RETIPC = Pop (stack)

V^SS

VSS

VPP

12 V

■ RETPC = Pop (stack)

■ CALLPC = Subroutines address

■ ResetPC = Reset Vector

2.2 Control Unit and Data Processing Unit

■ Normal InstructionPC = PC + 1

The Control Unit (CU) formally includes five main

blocks. Each block decodes a set of instructions,

generating the appropriate control signals. The

main parts of the CU are illustrated in Figure 2.1.

The five different parts of the CU manage Loading,

Logic/Arithmetic, Jump, Control and the Fuzzy

instruction set.

The block called “Collector” manages the signals

deriving from the different parts of the CU, defining

the signals for the Data Processing Unit (DPU) and

the different peripherals of the microcontroller.

The block called “Arbiter” manages the different-

2.2.2 Flags.

The ST52T410/ST52x420 core includes a differ-

ent set of flags that correspond to 2 different

modes: normal mode and interrupt mode. Each

set of flags consists of a CARRY flag (C), ZERO

flag (Z) and SIGN flag (S).

One set (CN, ZN, SN) is used during normal

operation and one is used during interrupt mode

(CI, ZI, SI). Formally, the user has to manage

only one set of flags: C, Z and S.

15/84

ST52T410/ST52T420/E420

Figure 2.1 Data Processing Unit (DPU)

Figure 2.2 CU/DPU Block Diagram

16/84

ST52T410/ST52T420/E420

The ST52T410/ST52x420 core uses flags that

correspond to the actual mode. As soon as an

interrupt is generated the ST52T410/ST52x420

core uses the interrupt flags instead of the normal

flags.

■ RAM: 128 Bytes

■ Input Registers: 18 8-bit registers

■ Output Registers 9 8-bit registers

■ Configuration Registers: 17 8-bit registers

Each interrupt level has its own set of flags, which

is saved in the STACK together with the Program

Counter. These flags are restored from the STACK

automatically when a RETI instruction is executed.

■ Program memory up to 4K Bytes

Program memory will be described in further

details in the MEMORY section

If the MCU was in normal mode before an interrupt,

the normal flags are restored when the RETI

instruction is executed.

2.3.1 RAM and STACK.

RAM memory consists of 128 general purpose 8-

bit RAM registers.

Note: A CALL subroutine is a normal mode

execution. For this reason, a RET instruction,

consequent to a CALL instruction does not affect

the normal mode set of flags.

Flags are not cleared during context switching and

remain in the state they were at the end of the last

interrupt routine switching.

The Carry flag is set when an overflow occurs

during arithmetic operations, otherwise it is

cleared.

The Sign flag is set when an underflow occurs

during arithmetic operations, otherwise it is

cleared.

All the registers in RAM can be specified by using

a decimal address. For example, 0 identifies the

first register of RAM.

To read or write RAM registers LOAD instructions

must be used. See Table 2.5

Each interrupt level has its own set of flags, which

is saved in the STACK together with the Program

Counter. These flags are restored from the STACK

automatically when a RETI instruction is executed.

When the instructions like Interrupt request or

CALL are executed, a STACK level is used to push

the PC.

The STACK is located in RAM. For each level of

stack, 2 bytes of RAM are used. The values of this

stack are stored from the last RAM register

(address 127). The maximum level of stack

must be less than 128.

2.3 Address Spaces

ST52T410/ST52x420 has four separate address

spaces:

Figure 2.3 Address Spaces Description

17/84

ST52T410/ST52T420/E420

The STACK POINTER indicates the first level

available to store data. When a subroutine call or

interrupt request occurs, the content of the PC and

the current set of flags are stored into the level

located by the STACK POINTER.

When a interrupt return occurs (RETI instruction),

the data stored in the highest stack level is

restored back into the PC and current flags.

All the registers can be specified by using a

decimal address (for example, 0 identifies the first

register of the IR).

The assembler instruction:

LDRI RAM_Reg. IR_i

loads the value of the i-th IR in the RAM location

identified by the RAM_Reg address.

Instead, when a subroutine return occurs (RET

instruction) the data stored in the highest stack

level are restored in the PC not affecting the flags.

These operating modes are illustrated in Figure

2.4.

Note: The user must pay close attention to avoid

overwriting RAM locations where the STACK could

be stored.

The first input register is dedicated to store the

value of the stack pointer. The next 8 registers

(ADC_OUT_0:7) of the IR are dedicated to the 8

converted values deriving from the ADC

(ST52x420 only). The last 9 Input Registers

contain data from the I/O ports and PWM/Timers.

The following table summarizes the IR address

and the relative peripherals. In order to simplify the

concept, a mnemonic name is assigned to the

registers. The same name is used in

2.3.2 Input Registers Bench.

®

The Input Registers (IR) bench consists of 18 8-bit

registers containing data or the status of the

peripherals.

VISUALSTUDIO development tools

Figure 2.4 Stack Operation

18/84

ST52T410/ST52T420/E420

Table 2.2 Input Registers

IR MNEMONIC NAME

PERIPHERAL REGISTER

ADDRESS

STACK_POINTER

CHAN 0 (*)

STACK POINTER

A/D CHANNEL 0 (*)

0

1

CHAN 1 (*)

A/D CHANNEL 1 (*)

2

CHAN 2 (*)

A/D CHANNEL 2 (*)

3

CHAN 3 (*)

A/D CHANNEL 3 (*)

4

CHAN 4 (*)

A/D CHANNEL 4 (*)

5

CHAN 5 (*)

A/D CHANNEL 5 (*)

6

CHAN 6 (*)

A/D CHANNEL 6 (*)

7

CHAN 7 (*)

A/D CHANNEL 7 (*)

8

PORT_A

PORT A INPUT REGISTER

PORT B INPUT REGISTER

PORT C INPUT REGISTER

PWM/TIMER 0 COUNTER

PWM/TIMER 0 STATUS REGISTER

PWM/TIMER 1 COUNTER

PWM/TIMER 1 STATUS REGISTER

PWM/TIMER 2 COUNTER

PWM/TIMER 2 STATUS REGISTER

9

PORT_B

10

11

12

13

14

15

16

17

PORT_C

PWM_ 0_COUNT

PWM_ 0_ STATUS

PWM_ 1_ COUNT

PWM_ 1_ STATUS

PWM_ 2_ COUNT

PWM_ 2_ STATUS

2.3.3 Configuration Registers.

instructions, the Configuration Registers can be

set by using values stored in the Program Memory

(EPROM) or in RAM.

Use and meaning of each register will be described

in further details in the corresponding section.

The ST52T410/ST52x420 configuration Registers

allow the configuration of all the blocks of the fuzzy

microcontroller. Table 2.3 describes the functions

and the related peripherals of each of the

Configuration Registers. By using the load

Table 2.3 Configuration Registers

CONFIGURATION REGISTER

PERIPHERAL

INTERRUPT MASK

DESCRIPTION

REG_CONF 0

REG_CONF 1

REG_CONF 2

REG_CONF 3 (*)

Interrupts mask setting

INTERRUPT PRIORITY

Watchdog Timer Configuration

A/D configuration

INTERRUPT PRIORITY

WATCHDOG TIMER

A/D CONVERTER

Set the relative bit like digital input

or digital output

REG_CONF 4

PORT A

19/84

ST52T410/ST52T420/E420

Table 2.3 Configuration Registers (continued)

CONFIGURATION REGISTER

PERIPHERAL

DESCRIPTION

PWM/Timer 0 Working mode

Configuration

REG_CONF 5

PWM/TIMER 0

PWM/TIMER 0 Prescaler

configuration and output waveform

selection.

REG_CONF 6

PWM/TIMER 0 Working Mode

Configuration

REG_CONF 7

REG_CONF 8

PWM/TIMER 0

PWM/TIMER 1

PWM/TIMER 1 Working Mode

Configuration

PWM/TIMER 1 Prescaler

configuration and output waveform

selection.

REG_CONF 9

REG_CONF 10

REG_CONF 11

PWM/TIMER 1

PWM/TIMER 2

PWM/TIMER 2 Working Mode

Configuration

PWM/Timer 2 Prescaler

configuration and output waveform

selection.

Set the bit 0,1 and 2 like Digital I/O

or complementary Timers Output.

REG_CONF 12

REG_CONF 13

PORT A

PORT B

Set the relative bit like digital input

or digital output.

Set the relative I/O like Digital or

Analog (*).

REG_CONF 14

REG_CONF 15

REG_CONF 16

PORT B

PORT C

Set the relative I/O like digital input

or digital output

Set the relative I/O like Digital I/O

or Timers Output

(*) ST52x420 only

2.3.4 Output Registers.

The Output Registers (OR) consist of 9 registers

containing data for the microcontroller peripherals

including the I/O Ports.

All registers can be specified by using a decimal

address (for example, 1 identifies the second OR).

loads the value of the RAM location identified by

the address RAM_Reg in the OR i-th Table 2.4

describes OR.

In order to simplify the concept, a mnemonic name

is assigned to OR. The same names are used in

TM

VISUALFIVE 5.0 development tools.

Use and meaning of each register will be described

in further details in the corresponding section.

By using LOAD instructions the Output Registers

(OR) may be set by using values stored in the

Program Memory (LDPE) or in RAM (LDPR)

The assembler instruction:

LDPR OR_i RAM_Reg.

20/84

ST52T410/ST52T420/E420

Table 2.4 Output Registers

OR MNEMONIC NAME

PORT_ A

PERIPHERAL REGISTER

PORT A OR

ADDRESS

0

1

2

3

4

5

6

7

8

PORT_ B

PORT B OR

PORT_C

PORT C OR

PWM_0_COUNT

PWM_0_RELOAD

PWM_1_COUNT

PWM_1_RELOAD

PWM_ 2_ COUNT

PWM_2_RELOAD

TIMER/PWM 0 COUNTER

TIMER/PWM 0 RELOAD REGISTER

TIMER/PWM 1 COUNTER

TIMER/PWM 1 RELOAD REGISTER

TIMER/PWM 2 COUNTER

TIMER/PWM 2 RELOAD REGISTER

2.4 Arithmetic Logic Unit

The ALU of the ST52T410/ST52x420 can perform

multiplication (MULT) and division (DIV).

Multiplication is performed by using 8 bit operands

storing the result in 2 registers (16 bit values), see

Figure 2.5 and Figure 2.6.

WARNING 1: The current page register value

set with the PGSET instruction is lost after a

jump, call, or an interrupt jump.

The 8-bit Arithmetic Logic Unit (ALU) allows the

performance of arithmetic calculations and logic

instructions, which can be divided into 5 groups:

Load, Arithmetic, Jump, Interrupts and Program

Control instructions (refer to the ST52T410/

ST52x420 Assembler Set for further details).

WARNING 2: If the LSB of the multiplication

result is 0, the Zero flag is set although the

result is not 0.

The computational time required for each

instruction consists of one clock pulse for each

Cycle plus 3 clock pulses for the decoding phase.

Table 2.5 Load instructions

Load Instructions

Bytes

Mnemonic

Instruction

Cycles

Z

S

C

LDCE

LDCR

LDFR

LDPE

LDPR

LDRC

LDRE

LDCE conf, EPROM

LDCR conf, RAM

3

17

14

17

14

16

18

-

LDFR FUZZY_i_RAM RAM

LDPE per, EPROM

LDPE per, (RAM)

LDPR reg, RAM

LDRC RAM, const

LDRE RAMi, EPROMi

LDRE (RAMi), (RAMj)

21/84

ST52T410/ST52T420/E420

Table 2.5 Load instructions

LDRI

LDRR

LDRI RAM, inp_reg

3

2

15

16

9

-

LDRR RAMi, RAMj

PGSET const

PGSET

Table 2.6 Arithmetic & Logic instructions set

Arithmetic Instructions

Bytes

Mnemonic

Instruction

Cycles

Z

S

C

ADD

ADDO

AND

ADD regi, regj

ADDO regi, regj

AND regi, regj

ASL regi

3

2

3

2

3

2

3

2

17

20

17

15

26

15

19

15

17

20

15

I

-

I

-

I

-

I

ASL

ASR

ASR regi

-

I

DEC

DEC regi

I

DIV

DIV regi, regj

INC regi

I

INC

-

I

MULT

NOT

MULT regi, regj

NOT regi

-

I

OR

OR regi, regj

SUB regi, regj

SUBO regi, regj

MIRROR regi

SUB

SUBO

MIRROR

I

-

Table 2.7 Jump Instruction Set

Jump instructions

mnemonic

CALL

JP

instruction

bytes

cycles

18

z

-

s

-

c

-

CALL addr

JP addr

3

1

12

JPC

JPC addr

JPNC addr

JPNS addr

JPNZ addr

JPS addr

JPZ addr

RET

10/12

13

JPNC

JPNS

JPNZ

JPS

JPZ

RET

22/84

ST52T410/ST52T420/E420

Table 2.8 Interrupt Instructions Set

Interrupt Instructions

Mnemonic

HALT

Instruction

HALT

Bytes

Cycles

7/15

6

Z

-

S

-

C

-

1

2

1

MEGI

MDGI

RETI

MEGI

-

MDGI

-

RETI

12

-

RINT

RINT INT

UDGI

8

-

UDGI

6

-

UEGI

7/15

7/14

-

WAITI

-

Table 2.9 Control Instructions Set

Control Instructions

Mnemonic

FUZZY

Instruction

FUZZY

Bytes

Cycles

Z

-

S

-

C

-

1

5

6

7

6

NOP

-

WDTRFR

WDTSLP

WDTRFR

WDTSLP

-

Notes:

I affected

- not affected

Figure 2.5 Multiplication

Figure 2.6 Division

23/84

ST52T410/ST52T420/E430

3 EPROM

■ Mbfs Setting memory block (18 through

MemAdd) contains the coordinates of the

vertexes of every Mbf defined in the program.

EPROM memory provides an on-chip user-

programmable non-volatile memory, which allows

fast and reliable storage of user data.

EPROM memory can be locked by the user. In

fact, a memory location called Lock Cell is devoted

to lock EPROM and avoid external operations. A

software identification code, called ID CODE,

distinguishes which software version is stored in

the memory.

■ The maximum value of MemAdd is 1023. This

area is dynamically assigned according to the

size of the fuzzy routines. The unused memory

area, if any, is assigned to the Program

Instruction Set memory block.

■ The Program Instructions Set memory block

(MemAdd through 4095) contains the instruction

set of the user program.

32 kbits of memory space with an 8-bit internal

parallelism (up to 4 kbytes) addressed by a 12-bit

bus are available. The data bus is 8 bits.

Locations 0, 1 and 2 contain the address of the first

microcode instruction.The operations that can be

performed on EPROM during the Programming

Phase are: Stand By, Memory Writing, Reading

and Verify/Margin Mode, Memory Lock, IDCode

Writing and Verify.

Memory has a double supply: V

12V±5% in Programming Phase or to V during

is equal to

SS

PP

Working Phase. V is equal to 5V±10%.

DD

ST52T410/ST52x420 EPROM memory is divided

into three main blocks (see Figure ):

■ Interrupt Vectors memory block (3 through 17)

contains the addresses for the interrupt routines.

Each address is composed of three bytes.

Figure 3.1 Program Memory Organization

24/84

ST52T410/ST52T420/E430

The operations above are managed by using the

internal 4-bit EPROM Control Register. The

Table 3.1 EPROM Control Register

reading phase is executed with V = 5V±5%, while

PP

OPERATION

Stand By

REGISTER VALUE

the verify/Margin Mode phase needs

V

=

PP

12V±5%. The Blank Check must be a reading

0

1

operation with V = 5V±5%.

PP

Table 3.1 illustrates EPROM Control Register

codes used to identify the operation running.

Memory Reading/Verify

Memory Unlock and

Lock Status Reading

2

3.1 EPROM Programming Phase Procedure

The Programming mode is selected by applying

Memory Writing

Memory Lock

3

4

5

12V±5% voltage or 5V±5% voltage to the V pin

PP

and setting the control signal as following:

RESET =Vss

TEST =Vss

ID CODE Writing

If the V voltage is 5V±5% only reading may be

performed.

PP

Memory Lock Status

Reading/Verify

9

RST_ADD, INC_ADD, RST_CONF, INC_CONF

and PHASE are the control signals used during the

Programming Mode.

ID CODE Reading/

Verify

10

PHASE, RST_CONF and RST_ADD signals are

active on level, the others are active on rising

edge.

Figure 3.2 Eprom Programming Timing

VALID

DATA

VALID

DATA

VALID

DATA

OUT

DATA

OUT

DATA

OUT

DATA

IN

PA(0:7)

RST_ADD

RST_CONF

INC_ADD

INC_CONF

PHASE

100nS

10 S

µ

MEMORY UNLOCK

MEMORY WRITING

LOCATION ADDRESS =1

MEMORY VERIFY

MARGIN MODE

25/84

ST52T410/ST52T420/E430

PHASE and RST_ADD signals are active low,

RST_CONF signal is active high.

3.1.2 EPROM Locking.

The Memory Lock operation, which is identified

with the number 4 in the EPROM Control Register,

writes “0" in the Memory Lock Cell.

Port A is used for the memory data I/O. (See Table

3.1 for pin reference on the different packages).

Memory may be locked by means of the Memory

Lock Status, which is a flag used to enable

EPROM operations.

At the beginning of an External Operation, when

the RST_ADD signal changes from low level to

high level, the Memory Lock Status is “0", therefore

it must be unlocked before proceeding.

In order to unlock the Memory Lock Status the

operation, which is identified by the number 2 in

the EPROM Control Register must be executed

(see Figure 3.2).

Memory Lock Status can be changed only if

Memory Lock Cell is “1". After a Memory Lock

operation external operations cannot be executed

except to read (or verify) the OTP Code and the

Memory Lock Status.

If Memory Lock Status is 1 all EPROM operations

are enabled, otherwise the user may only read

(and verify) the OTP code and the Memory Lock

Status.

Only if EPROM is not locked by means of Lock Cell

(see EPROM Locking may EPROM operations be

enabled by changing the Memory Lock Status from

0 to 1.

RST_ADD signal resets the memory address

register and the Memory Lock Status. When the

RST_ADD becomes high, the memory must be

unlocked in order to read or write.

3.1.3 EPROM Writing.

INC_ADD signal increments the memory address.

When the memory is blank, all bits are at logic level

“1". Data is introduced by programming only the

zeros in the desired memory location. However, all

input data must contain both ”1" and “0".

The only way to change “0" into ”1" is to erase the

entire memory (by exposure to Ultra Violet light)

and reprogram it.

RST_CONF signal resets the EPROM Control

Register. When RST_CONF is high, the DATA I/

O Port A is in output, otherwise it is always in

input.

INC_CONF signal increments the EPROM Control

Register value.

PHASE signal validates the operation selected by

means of the EPROM Control Register value.

The memory is in Writing mode when the EPROM

Control Register value is 3.

The V voltage must be 12V±5%, with stable data

PP

on the data bus PA(0:7).

3.1.1 EPROM Operation.

The timing signals are the following (see Figure ):

1) RST_ADD and RST_CONF change from low to

high level,

2) two pulses on INC_CONF signal load the

Memory Unlock operation code,

3) a negative pulse (100 ns) on the PHASE signal

validates the Memory Unlock operation,

4) a negative pulse on RST_CONF signal resets

the EPROM Control Register,

5) three positive pulses on INC_CONF load the

Memory Writing operation code,

6) a train of positive pulses on INC_ADD signal

increments the memory location address up to the

requested value (generally this is a sequential

operation and only one pulse is used),

In order to execute an EPROM operation (See

Table 3.1), the corresponding identification value

must be loaded in the EPROM Control Register.

The signal timing is the following: RST_ADD= high

and PHASE= high, RST_CONF changes from low

to high level, to reset the EPROM Control Register,

and INC_CONF signal generates a number of

positive pulses equal to the value to be loaded.

After this sequence, a negative pulse of the

PHASE signal will validate the operation selected.

The minimum PHASE signal pulse width must be

10 µs for EPROM Writing Operation and 100 ns for

the others.

When RST_CONF is high, DATA I/O Port A is

enabled in output and the reading/verifying

operation results are available.

After a writing operation, when RST_CONF is high,

Port A is in output without valid data.

7) a negative pulse (10 µs) on the PHASE signal

validates the Memory Writing operation.

26/84

ST52T410/ST52T420/E430

3.1.4 EPROM Read/Verify Margin Mode.

The read phase is executed with V = 5V±5%,

3.1.6 ID code.

A software identification code, called ID code may

be written in order to distinguish which software

version is stored in the memory.

PP

instead of the verify phase that needs V

=

PP

12V±5%.

The Memory Verify operation is available in order

to verify the accuracy of the data written. A

Memory Verify Margin Mode operation can be

executed immediately after writing each byte, in

this case (see Figure 3.2):

1) a positive pulse on RST_CONF signal resets the

EPROM Control Register, if it wasn’t already reset;

64 Bytes are dedicated to store this code by using

the address values from 0 to 63.

The ID Code may be read or verified even if the

Memory Lock Status is “0".

The timing signals are the same as that of a normal

operation.

3.2 Eprom Erasure

2) one positive pulse on INC_CONF loads the

Memory Read/Verify operation code;

The transparent window available in the

CSDIP32W package, allows the memory contents

to be erased by exposure to UV light.

3) a negative pulse (100 ns) on the PHASE signal

validates the Memory Reading / Verify operation;

Erasure begins when the device is exposed to light

with a wavelength shorter than 4000Å. Sunlight, as

well as some types of artificial light, includes

wavelengths in the 3000-4000Å range which, on

prolonged exposure can cause erasure of memory

contents. Therefore, it is recommended that

EPROM devices be fitted with an opaque label

over the window area in order to prevent

unintentional erasure.

The erasure procedure recommended for EPROM

devices consists of exposure to short wave UV

light having a wavelength of 2537Å. The minimum

integrated dose recommended (intensity x expo-

sure time) for complete erasure is 15Wsec/cm 2.

4) a negative pulse on RST_CONF signal puts in

the PA(0:7) port the value stored in the actual

memory address and resets the EPROM Control

Register;

If an error occurred writing, the user has to repeat

EPROM writing.

3.1.5 Stand by Mode.

EPROM has a standby mode, which reduces the

active current from 10mA (Programming mode) to

less than 100 µA. Memory is placed in standby

mode by setting the PHASE signal at a high level

or when the EPROM Control Register value is 0

and the PHASE signal is low.

This is equivalent to an erasure time of 15-20

minutes using a UV source having an intensity of

12mW/cm 2 at a distance of 25mm (1 inch) from

the device window.

27/84

ST52T410/ST52T420/E420

4 INTERRUPTS

Figure 4.1 Interrupt Flow

The Control Unit (CU) responds to peripheral

events and external events via its interrupt

channels.

When such an events occur, if the related interrupt

is not masked and according to a priority order, the

current program execution can be suspended to

allow the CU to execute a specific response

routine.

NORMAL

PROGRAM

FLOW

INTERRUPT

SERVICE

ROUTINE

Each interrupt is associated with an interrupt

vector that contains the memory address of the

related interrupt service routine. Each vector is

located in the Program Space (EPROM Memory)

at a fixed address (see Interrupt Vectors Table

4.2).

INTERRUPT

RETI

INSTRUCTION

4.1 Interrupt Operation

If there are pending interrupts at the end of an

arithmetic or logic instruction, the one with the

highest priority is passed. Passing an interrupt

means storing the arithmetic flags and the current

PC in the stack and executing the associated

Interrupt routine, whose address is located in three

bytes of the EPROM memory location between

address 2 and 17.

Figure 4.2 Interrupt Vectors mapping

3

4

INT_ADC

5

6

The Interrupt routine is performed as a normal

code, checking if a higher priority interrupt has to

be passed at the end of each instruction. An

Interrupt request with the higher priority stops the

lower priority Interrupt. The Program Counter and

the arithmetic flags are stored in the stack.

With the RETI (Return from Interrupt) instruction

the arithmetic flags and Program Counter (PC) are

restored from the top of the stack. This stack was

already described in section RAM and STACK.

7

INT_PWM/TIMER0

8

9

INTERRUPT

VECTORS

10

11

12

13

14

15

16

17

_PWM/TIMER1

INT

INT_PWM/TIMER2

INT_EXT

An Interrupt request cannot stop processing of the

fuzzy rule, but this is passed only after the end of a

fuzzy rule or at the end of a logic, or arithmetic

instruction.

NOTE: A fuzzy routine can only be interrupted

in the Main program. An interrupt request

cannot stop a Fuzzy function that is running

inside another interrupt routine. In order to use

a Fuzzy function inside an interrupt routine, the

user MUST include the Fuzzy function between

an UDGI (MDGI) instruction and an UEGI

Figure 4.3 Global Interrupt Request generation

Global Interrupt

Pending

Request

(MEGI) instruction (see the

following

paragraphs), so that the interrupt request may

be disabled during the execution of the fuzzy

function.

User Global

Interrupt Mask

4.2 Global Interrupt Request Enabling

When an Interrupt occurs, it generates a Global

Interrupt Pending (GIP), that can be masked by

software. After a GIP a Global Interrupt Request

(GIR) will be generated and Interrupt service

Macro Global

28/84

ST52T410/ST52T420/E420

Routine associated to the interrupt with higher

priority will start.

Table 4.1 Configuration Register 0

Description

In order to avoid possible conflicts between

interrupt masking set in the main program, or

inside high level language compiler macros, the

GIP is hung up through the User Global Interrupt

Mask or the Macro Global Interrupt Mask (see

Figure 4.2).

UEGI/UDGI instruction switches on/off the User

Global Interrupt Mask, enabling/disabling the GIR

for the main program.

Bit

Name

Value

Description

External Interrupt

Masked

0

1

0

1

0

1

0

1

0

MSKE

External Interrupt

Not Masked

MEGI/MDGI instructions switch the Macro Global

Interrupt Mask on/off, in order to ensure that the

macro will not be broken.

A/D Converter (*)

Interrupt

Masked

1

2

3

4

MSKAD

MSKTM0

MSKTM1

MSKTM2

A/D Converter (*)

Interrupt

4.3 Interrupt Sources

ST52T410/ST52x420 manages interrupt signals

generated by the internal peripherals (PWM/

Timers and Analog to Digital Converter) or coming

from the INT/PC0 pin. The External Interrupt is

active on the rising of INT/PC0 signal.

Each peripheral can be programmed in order to

generate the associated interrupt; further details

are described in the related chapter.

Not Masked

PWM/TIMER 0

Interrupt

Masked

PWM/TIMER 0

Interrupt

Not Masked

PWM/TIMER 1

Interrupt

4.4 Interrupt Maskability

Masked

The interrupts can be masked by configuring the

REG_CONF 0 by means of LDCR, or LDCE,

instruction. The interrupt is enabled when the bit

associated to the mask interrupt is “1". Viceversa,

when the bit is ”0", the interrupt is masked and is

kept pendent.

PWM/TIMER 1

Interrupt

Not Masked

PWM/TIMER 2

Interrupt

Masked

For example:

LDRC 10,6 //load the constant 6 in the

RAM Register 10

LDCR 0, 10 // set the CONF_REG 0 with

the value stored in the RAM Register

10

PWM/TIMER 2

Interrupt

Not Masked

1

-

5

6

4

Not used

the result is CONF_REG0 =00000110 enabling the

interrupts deriving from the ADC (INT_ADC)

(ST52x420 only) and from the PWM/TIMER 0

(INT_PWM/TIMER0).

-

(*) ST52x420 only

Reset Configuration ‘000000’

29/84

ST52T410/ST52T420/E420

Table 4.2 Interrupts Description

Peripheral

Code

EPROM

Locations

Name

Description

ADC

Priority

Maskable

yes

INT_ADC (*)

Int

Programmable

00

01

3-5

6-8

INT_PWM/

TIMER0

PWM/TIMER 0

yes

INT_PWM/

TIMER1

PWM/TIMER 1

PWM/TIMER 2

Int

Programmable

Highest

10

11

-

yes

9-11

12-14

15-17

INT_PWM/

TIMER2

External

Interrupt (INT)

INT_EXT

Ext

(*) ST52x420 only

Figure 4.4 Interrupt Configuration Register 0

REG_CONF 0

7

0

not used not used not usedMSKTM2MSKTM1MSKTM0 MSKAD MSKE

EXTERNAL INT.

A/D CONV. INT.

PWM/TIMER 0 INT.

PWM/TIMER 1 INT.

PWM/TIMER 2 INT.

NOT USED

30/84

ST52T410/ST52T420/E420

Figure 4.5 Interrupt Configuration Register 1

REG_CONF 1

7

0

LOW

LOW MEDL MEDL MEDH MEDH HIGH

HIGH

PRIORITY HIGH

PRIORITY MED. HIGH

PRIORITY MED. LOW

PRIORITY LOW

4.5 Interrupt Priority

Six priority levels are available: level 5 has the

lowest priority, level 0 has the highest priority.

Table 4.3 Conf. Register 1

Level 5 is associated to the Main Program, levels 4

to 1 are programmable by means of the priority

registers called REG_CONF1 (see Figure 4.5 and

Table 4.3); whereas the higher level is related to

the external interrupt (INT_EXT).

Bit

Name

Value

Level

Peripheral

Code

0, 1

INT1

High

PWM/Timers and ADC are identified by a two-bit

Peripheral Codes (see Table 4.2); in order to set

the i-th priority level the user must write the

peripheral label i in the related INTi priority level.

Peripheral

Code

2,3

4,5

INT2

INT3

Medium-High

Medium-Low

Peripheral

Code

i.e.

LDRC 10, 201 //(load the value

201=’11001001’ in the RAM Register 10)

■ Level 3: INT_ADC (ADC Code: 00) (ST52x420

LDCR 1, 10 // set the REG_CONF1=

‘11001001’

only)

■ Level 4: INT_PWM/TIMER0 (PWM/TIMER 2

Code: 11)

The following priority levels are defined:

■ Level 1: INT_PWM/TIMER0 (PWM/TIMER 0

Code: 01)

■ Level 2: INT_PWM/TIMER0 (PWM/TIMER 1

Code: 10)

31/84

ST52T410/ST52T420/E420

Figure 4.6 Example of a sequence of Interrupt requests

PRI2

PRI0

PRI1

PRI3

PRI4

PRIORITY

LEVEL

0

1

2

3

4

5

PRI0

PRI1

PRI2

PRI3

PRI4

MAIN PROGRAM

Note: The Interrupt priority must be fixed at the

beginning of the main program because at the

RESET REG_CONF1=’00000000’ it could

When an interrupt occurs the CU executes a JUMP

instruction to the address loaded in the related

location of the Interrupt Vector.

generate

erroneous

operations.

During

When the execution returns to the original program

it immediately begins following the instruction that

was interrupted.

program execution the interrupt priority can

only be modified with the following procedure:

STEP 1:

Mask the interrupts by means of a UDGI (or

MDGI) instruction

Table 4.4 RINT Instruction code

STEP 2:

Peripheral Name

Value

Change the REG_CONF 1 values to modify the

interrupt priority

STEP 3:

Reset all the pending interrupt instructions by

means of RINT instructions.

STEP 4:

INT_ADC (*)

PWM/TIMER 0

PWM/TIMER 1

PWM/TIMER 2

INT_EXT

0

1

2

3

4

Unmask the interrupts by means of a UEGI (or

MEGI) instruction

When a source provides an Interrupt request and

the request processing is also enabled, the CU

changes the normal sequential flow of a program

by transferring program control to a selected

service routine.

(*) ST52x420 only

32/84

ST52T410/ST52T420/E420

4.6 Interrupts and Low power mode

All interrupts allow the processor to leave the WAIT

low power mode. Only the external Interrupt allows

the processor to leave the HALT low power mode.

Note: The RINT command must be preceded

from a UDGI (or MDGI) command and followed

by a UEGI (or MEGI) command.

4.7 Interrupt RESET

WARNING: If an interrupt is reset, with the RINT

instruction within its own interrupt routine, the

priority level of the interrupt becomes the

lowest and the routine can be immediately

An eventually pending interrupt can be reset with

the instruction RINT j, which resets the interrupt

j-th where j identifies the peripherals as described

in the following table (see Table 4.4).

The assembler instruction:

RINT 2

interrupted by

request.

a

lower priority interrupt

Resets the PWM/Timer 1 interrupt.

33/84

ST52T410/ST52T420/E420

5 CLOCK, RESET & POWER SAVING MODE

5.1 System Clock

The ST52T410/ST52x420 Clock Generator

module generates the internal clock for the internal

Control Unit, ALU and on-chip peripherals and it is

designed to require a minimum number of external

components.

Note: The crystal or ceramic leads and circuit

connections must be as short as possible. Typical

values for CL1, CL2 are 10pF for a 20 MHz crystal.

5.2 RESET

There are two Reset sources:

- RESET pin (external source.)

- WATCHDOG (internal source)

When a Reset event happens, the user program

restarts from the beginning.

The ST52T410/ST52x420 oscillator circuit

generates an internal clock signal with the same

period and phase as that of the OSCin input pin.

The maximum frequency allowed is 20 Mhz.

The Reset pin is an input. An internal reset does

not affect this pin.

A Reset signal originated by external sources is

recognized instantaneously. The RESET pin may

The system clock may be generated by using

either a quartz crystal, ceramic resonator or an

external clock.

The different methods of the clock generator are

illustrated in Figure 5.1.

When an external clock is used, it must be

connected on the OSCin pin, while OSCout can be

floating.

be used to ensure V has risen to a point where

DD

the MCU can operate correctly before the user

program runs. In working mode Reset must be set

to ‘1’ (see Table 2.1).

The crystal oscillator start-up time is a function of

many variables: crystal parameters (especially

5.3 Power Saving Mode

R ), oscillator load capacitance (CL), IC

parameters, environment temperature, supply

voltage.

There are two Power Saving modes: WAIT and

HALT mode. These conditions may be entered

using the WAIT or HALT instructions.

s

5.3.1 Wait Mode

Figure 5.1 Oscillator Connections

Wait mode places the MCU in low power

consumption by stopping the CPU. All peripherals

CRYSTAL CLOCK

EXTERNAL CLOCK

ST52X420

OSCin

OSCout

OSCin

OSCout

FLOATING

Cl2

10pF

Cl1

10pF

CLOCK

INPUT

34/84

ST52T410/ST52T420/E420

and the watchdog remain active. During WAIT

mode, Interrupts are enabled. The MCU will

remain in Wait mode until an Interrupt or a RESET

occurs, whereupon the Program Counter jumps to

the interrupt service routine or, if a RESET occurs,

at the beginning of the user program.

Halt mode cannot be used when the watchdog

is enabled.

If the HALT instruction is executed while the

watchdog system is enabled, it will be skipped

without modifying the normal CPU operations.

The ICU can exit Halt mode after an external inter-

REMARK: In Wait mode the CPU clock does not

stop.

rupt or reset. The oscillator is then turned on and

stabilization time is provided before restarting

CPU operations. Stabilization time is 4096 CPU

clock cycles after the interrupt and 1.000.000 after

the Reset.

After the start up delay, the CPU restarts opera-

tions by serving the external interrupt routine.

Reset makes the ICU exit from HALT mode and

restart, after the delay, from the beginning of the

user program after the delay.

5.3.2 Halt Mode

Halt mode is MCU’s lowest power consumption

mode, which is entered by executing the HALT

instruction. The internal oscillator is turned off,

causing all internal processing to stop, including

the operations of the on-chip peripherals.

Figure 5.2 Reset Block Diagram

Warning: if the External Interrupt is disabled, the

ICU exits from the Halt mode and jumps to the

lower priority interrupt routine.

Figure 5.4 WAIT Flow Chart

RESET

INTERNAL

RESET

WATCHDOG RESET

Figure 5.3 Simple Reset Circuit

Vcc

100

F

10k

RESET

2.2k

1 F

35/84

ST52T410/ST52T420/E420

Figure 5.5 HALT Flow Chart

HALT INSTRUCTION

YES

WATCHDOG

ENABLED

NO

HALT INSTRUCTION

SKIPPED

OSCILLATOR

PERIPHERALS CLOCK

CPU CLOCK

OFF

NO

YES

NO

EXTERNAL

INTERRUPT

RESET

YES

OSCILLATOR

PERIPHERALS CLOCK

CPU CLOCK

ON

OSCILLATOR

PERIPHERALS CLOCK

CPU CLOCK

ON

1000000 CPU CLOCK

4096 CPU CLOCK

CYCLES DELAY

EXTERNAL

INTERRUPT

ENABLED

NO

YES

RESET CPU

AND RESTART

USER PROGRAM

RESTART PROGRAM

SERVICING THE

EXTERNAL

RESTART PROGRAM

SERVICING THE

LOWER PRIORITY

INTERRUPT ROUTINE

36/84

ST52T410/T420/E420

6 FUZZY COMPUTATION (DP)

Figure 6.2 Alpha Weight Calculation

The ST52T410/ST52x420 Decision Processor

(DP) main features are:

j-th Mbf

1

■ Up to 8 Inputs with 8-bit resolution;

■ 1 Kbyte of Program/Data Memory available to

store more than 300 to Membership Functions

(Mbfs) for each Input;

ij

α

■ Up to 128 Outputs with 8-bit resolution;

i-th INPUT VARIABLE

■ Possibility of processing fuzzy rules with an

UNLIMITED number of antecedents;

■ UNLIMITED number of Rules and Fuzzy Blocks.

The limits on the number of Fuzzy Rules and

Fuzzy program blocks are only related to the

Program/Data Memory size.

After loading the input values by using the LDFR

assembler instruction, the user can start the fuzzy

inference by using the FUZZY assembler

instruction. During fuzzyfication: input data is

transformed in the activation level (alpha weight) of

the Mbf’s.

6.1 Fuzzy Inference

The block diagram shown in Figure 6.1 describes

the different steps performed during a Fuzzy

algorithm. The ST52T410/ST52x420 Core allows

for the implementation of a Mamdani type fuzzy

inference with crisp consequents. Inputs for fuzzy

inference are stored in 8 dedicated Fuzzy input

registers. The LDFR instruction is used to set the

Input Fuzzy registers with values stored in the

Register File. The result of a Fuzzy inference is

stored directly in a location of the Register File.

6.3 Inference Phase

The Inference Phase manages the alpha weights

obtained during the fuzzyfication phase to compute

the truth value (ω) for each rule.

This is a calculation of the maximum (for the OR

operator) and/or minimum (for the AND operator)

performed on alpha values according to the logical

connectives of Fuzzy Rules.

Several conditions may be linked together by

linguistic connectives AND/OR, NOT operators

and brackets.

The truth value ω and the related output singleton

are used by the Defuzzyfication phase, in order

to complete the inference calculation.

6.2 Fuzzyfication Phase

In this phase the intersection (alpha weight)

between the input values and the related Mbfs

(Figure 6.2) is performed.

Eight Fuzzy Input registers are available for Fuzzy

inferences.

Figure 6.1 Fuzzy Inference

1

2

11

1m

INFERENCE

PHASE

DEFUZZYFICATION

FUZZYFICATION

n1

N rules -1

N rules

nm

Input Values

Output Values

37/84

ST52T410/T420/E420

Figure 6.3 Fuzzyfication

6.5 Input Membership Function

The Decision Processor allows the management of

triangular Mbfs. In order to define an Mbf, three

different parameters must be stored on the

Program/Data Memory (see Figure 6.4):

IF INPUT 1 IS X1 OR INPUT 2 IS X2 THEN .......

1

α

■ the vertex of the Mbf: V;

α2

■ the length of the left semi-base: LVD;

■ the length of the right semi-base: RVD;

X1

Input 1

X2

Input

2

OR = Max

In order to reduce the size of the memory area and

the computational effort the vertical range of the

vertex is fixed between 0 and 15 (4 bits)

By using the previous memorization method

different kinds of triangular Membership Functions

may be stored. Figure 6.5 shows some examples

of valid Mbfs that can be defined in ST52T410/

ST52x420.

IF INPUT 1 IS X1 AND INPUT 2 IS X2 THEN .......

1

α

Each Mbf is then defined storing 3 bytes in the first

Kbyte of the Program/Data Memory.

α2

The Mbf is stored by using the following instruction:

X1

Input 1

X2

Input

2

MBF n_mbf lvd v rvd

where:

n_mbf is a tag number that identifies the Mbf

6.4 Defuzzyfication

lvd, v, and rvd are the parameters that describe the

Mbf’s shape as described above.

In this phase the output crisp values are

determined by implementing the consequent part

of the rules.

Each consequent Singleton X is multiplied by its

Figure 6.4 Mbfs Parameters

i

weight values ω , calculated by the Decision

i

processor, in order to compute the upper part of

the Defuzzyfication formula.

15

Each output value is obtained from the consequent

Input Mbf

crisp values (X ) by carrying out the following

i

Defuzzyfication formula:

N

X_ijω_ij

0

j

V

Input Variable

RVD

---------------------

Y_i=

N

LVD

ω_ij

j

where:

i = identifies the current output variable

N = number of the active rules on the current

output

Output Singleton

15

w

ω = weight of the j-th singleton

ij

X = abscissa of the j-th singleton

ij

The Decision Processor outputs are stored in the

RAM location i-th specified in the assembler

instruction OUT i.

0

X

Output Variable

38/84

ST52T410/T420/E420

Figure 6.5 Example of valid Mbfs

Figure 6.6 Output Membership Functions

j-th Singleton

1

ω

ij

ω

i0

ω

in

0

X

i-th OUTPUT

X

in

ij

i0

6.7 Fuzzy Rules

Rules can have the following structures:

if A op B op C...........then Z

if (A op B) op (C op D op E...) ...........then Z

where op is one of the possible linguistic operators

(AND/OR)

6.6 Output Singleton

The Decision Processor uses a particular kind of

membership function called Singleton for its output

variables. A Singleton doesn’t have a shape, like a

traditional Mbf, and is characterized by a single

point identified by the couple (X, w), where w is

calculated by the Inference Unit as described

earlier. Often, a Singleton is simply identified with

its Crisp Value X.

In the first case the rule operators are managed

sequentially; in the second one, the priority of the

operator is fixed by the brackets.

Each rule is codified by using an instruction set, the

inference time for a rule with 4 antecedents and 1

consequent is about 3 microseconds at 20 MHz.

The Assembler Instruction Set used to manage the

Fuzzy operations is reported in the table below.

Table 6.1 Fuzzy Instructions Set

Instruction

Description

MBF n_mbf Ivd v rvd Stores the Mbf n_mbf with the shape identified by the parameters Ivd, v and rvd

LDP n m

LDN n m

Fixes the alpha value of the input n with the Mbf m and stores it in internal registers

Calculates the complementary alpha value of the input n with the Mbf m. and stores the result

in internal registers

FZAND

FZOR

LDK

Implements the Fuzzy operation AND between the last two values stored in internal registers

Implements the Fuzzy operation OR between the last two values stored in internal registers

Stores the result of the last Fuzzy operation executed in internal registers

Loads the result of the last performed Fuzzy operation (stored in the temporary register K) in

the temporary buffer M.

SKM

LDM

Copies the value of register M in the data stack

CON crisp

OUT n_out

FUZZY

Multiplies the crisp value with the last ω weight

Performs Defuzzyfication and stores the currently Fuzzy output in the RAM n_out location

Starts the Fuzzy algorithm

39/84

ST52T410/T420/E420

Example 1:

IF Input IS NOT Mbf AND Input is Mbf OR Input IS Mbf THEN Crisp

1

4

12

3

8

is codified by the following instructions:

calculates the NOT α value of Input with Mbf and stores the result in internal registers

LDN 1 1

1

fixes the α value of Input with Mbf and stores the result in internal registers

LDP 4 12

FZAND

LDK

4

12

implements the operation AND between the results obtained with the previous instructions

stores the result of the previous operation in internal DPU registers

fixes the α value of Input with Mbf and stores the result in internal registers

LDP 3 8

FZOR

3

8

implements the operation OR between the results obtained with the previous instructions

CON crisp multiplies the result of the last Ω operation with the crisp value crisp

1

Example 2, the priority of the operator is fixed by the brackets:

IF (Input IS Mbf AND Input IS NOT Mbf ) OR (Input IS Mbf OR Input IS NOT Mbf ) THEN Crisp

3

1

4

15

1

6

14

2

fixes the α value of Input with Mbf and stores the result in internal registers

LDP 3 1

3

1

calculates the NOT α value of Input with Mbf and stores the result in internal registers

LDN 4 15

FZAND

SKM

4

15

implements the operation AND between the results obtained with the previous instructions

stores the result of the previous operation in register M

fixes the α value of Input with Mbf and stores the result in internal registers

LDP 1 6

1

6

calculates the NOT α value of Input with Mbf and stores the result in internal registers

LDN 2 14

FZOR

LDK

6

14

implements the operation OR between the results obtained with the previous instructions

stores the result of the previous operation in internal DPU registers

LDM

copies the value of the register M in internal DPU registers

FZOR

implements the operation OR between the last two values stored in DPU registers

CON crisp multiplies the result of the last Ω operation with the crisp value crisp

2

At the end of the fuzzy rule, by using the instruction OUT RAM_reg, a byte is written. Afterwards, the

control of the algorithm returns to the CU.

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ST52T410/ST52T420/E420

7 I/O PORTS

Each port is configured by using two configuration

registers. The first is used to determine if a pin is

an input or output, while the second defines the

Alternate functions.

7.1 Introduction

ST52T410/ST52x420 devices feature flexible

individually programmable multi-functional input/

output lines. Refer to the following figure for

specific pin allocations.

7.2 Input Mode

The input configuration is selected by setting the

corresponding configuration register bit to “1”

(REG_CONF 4, 13 and 15) (see paragraph I/O

Port Configuration Registers). The ports are

configured by using the configuration registers

illustrated in the following table.

19 I/O lines, grouped in 3 different ports are

available on the ST52T410/ST52x420:

PORT A = 7 or 8-bit ports (PA0 - PA7 pins)

PORT B = 7 or 8-bit ports (PB0 - PB7 pins)

PORT C = 4-bit port (PC0 - PC3 pins)

PIN 18 can be configured to belong to port A or to

port B.

.

Table 7.1 I/O Port Configuration Registers.

These I/O lines can be programmed to provide

digital input/output and analog input, or to connect

input/output signals to the on-chip peripherals as

alternate pin functions.

PORT A

PORT B

PORT C

Reg_Conf 4

Reg_Conf 13

Reg_Conf 15

Input buffers are TTL compatible with Schmitt

trigger in port A and C while port B is CMOS

compatible without Schmitt trigger.

The output buffer can supply up to 8 mA.

The port cannot be configured to be used

contemporaneously as input and output.

Digital input data is automatically stored in the

Input Registers, but it cannot be read directly. In

order to read a single bit of the IR its value must be

copied in a RAM location. Digital data is stored in a

RAM location by using the assembler instruction:

LDRI RAM_Reg Input_i

Figure 7.1 Ports A & C Functional Blocks

TTL

TO INPUT REGISTER

and PERIPHERALS

PORT A PIN

or PORT C PIN

FROM PERIPHERAL

FROM OUTPUT REGISTER

FROM CONFIGURATION REGISTER

41/84

ST52T410/ST52T420/E420

Figure 7.2 Port B Functional Blocks

FROM CONFIGURATION REGISTER

CMOS

TO INPUT REGISTER

PORT B PIN

TO A/D CONVERTER

FROM OUTPUT REGISTERS

FROM CONFIGURATION REGISTER

7.4 Alternate Functions

Several ST52T410/ST52x420

configurable to be used with different functions

(see Table 1.1).

pins

are

Table 7.2 Input Register and I/O Ports

PORT A

PORT B

PORT C

When an on-chip peripheral is configured to use a

pin, the correct I/O mode of the related pin must be

selected.

IR 9

IR 10

IR 11

7.3 Output Mode

For example: if pin 20 (PA5/T0CLK) has to be used

as an external PWM/Timer0 clock, the Reg_Conf

4(5) bit must be set to ‘1’.

When the signal is an on-chip peripheral input the

related I/O pin has to be configured in Input Mode.

The output configuration is selected by setting the

corresponding configuration register bit to “0”

(REG_CONF 4, 13 and 15) (see paragraph I/O

Port Configuration Registers).

Digital data is transferred to the related I/O Port by

means of the Output register via the assembler

instructions LDPE or LDPR.

When a pin is used as an A/D Converter input the

related I/O pin is automatically set in tristate. The

analog multiplexer (controlled by the A/D

configuration Register) switches the analog

voltage present on the selected pin to the common

analog rail, which is connected to the ADC input

(ST52x420 only).

Table 7.3 Output Register and I/O Ports

It is recommended that the voltage level not be

changed or that any port pins not be loaded while

conversion is running. Furthermore, it is

recommended that clocking pins not be located

close to a selected analog pin (ST52x420 only).

PORT A

OR 0

PORT B

OR 1

PORT C

OR 2

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ST52T410/ST52T420/E420

7.5 I/O Port Configuration Registers

The I/O mode for each bit of the three ports is

selected by using the Configuration Registers 4,

13 and 15 (See Table 7.1) The structure of these

registers is illustrated in the following tables.

Each bit of the configuration registers determines

the I/O mode of the related port pin.

Table 7.5 Ports B REG_CONF 13

Bit

Name

Value

Description

Set the pin PB0/Ain0

in Output Mode

0

D0

Set the pin PB0/Ain0

in Input Mode

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Table 7.4 Ports A REG_CONF 4

Set the pin PB1/Ain1

in Output Mode

Bit

Name

Value

Description

1

2

3

4

5

6

7

D1

D2

D3

D4

D5

D6

D7

Set the pin PA0/T0RES

in Output Mode

Set the pin PB1/Ain1

in Input Mode

0

D0

Set the pin PA0/T0RES

in Input Mode

Set the pin PB2/Ain2

in Output Mode

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Set the pin PA1/T0OUT

in Output Mode

Set the pin PB2/Ain2

in Input Mode

1

2

3

4

5

6

7

D1

D2

D3

D4

D5

D6

D7

Set the pin PA1/T0OUT

in Input Mode

Set the pin PB3/Ain3

in Output Mode

Set the pin PA2/T1OUT

in Output Mode

Set the pin PB3/Ain3

in Input Mode

Set the pin PA2/T1OUT

in Input Mode

Set the pin PB4/Ain4

in Output Mode

Set the pin PA3/T2OUT

in Output Mode

Set the pin PB4/Ain4

in Input Mode

Set the pin PA3/T2OUT

in Input Mode

Set the pin PB5/Ain5

in Output Mode

Set the pin PA4/T0STRT

in Output Mode

Set the pin PB5/Ain5

in Input Mode

Set the pin PA4/T0STRT

in Input Mode

Set the pin PB6/Ain6

in Output Mode

Set the pin PA5/T0CLK

in Output Mode

Set the pin PB6/Ain6

in Input Mode

Set the pin PA5/T0CLK

in Input Mode

Set the pin PB7/PA7/

Ain7 in Output Mode

Set the pin PA6 in

Output Mode

Set the pin PB7/PA7/

Ain7 in Input Mode

Set the pin PA6 in Input

Mode

Reset Configuration ‘11111111’

Set the pin PB7/PA7/

Ain7 in Output Mode

Set the pin PB7/PA7/

Ain7 in Input Mode

Reset Configuration ‘11111111’

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ST52T410/ST52T420/E420

Analog Input Option. The PB0-PB7 pins can be

configured to be analog inputs according to the

codes programmed in the configuration register

REG_CONF 14 (See Table 7.7) (ST52x420 only).

These analog inputs are connected to the on-chip

8-bit Analog to Digital Converter.

Table 7.6 Port C REG_CONF 15

Bit

Name

Value

Description

Set the pin INT/PC0 in

Output Mode

0

D0

Table 7.7 Analog Inputs (REG_CONF 14)

Set the pin INT/PC0 in

Input Mode

1

0

1

0

1

0

1

Bit

Name

Value

Description

0

pin PB0/Ain0 Digital I/O

Set the pin T0OUT/

PC1 in Output Mode

0

D0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

pin PB0/Ain0 Analog

pin PB1/Ain1 Digital I/O

pin PB1/Ain1 Analog

pin PB2/Ain2 Digital I/O

pin PB2/Ain2 Analog

pin PB3/Ain3 Digital I/O

pin PB3/Ain3 Analog

pin PB4/Ain4 Digital I/O

pin PB4/Ain4 Analog

pin PB5/Ain5 Digital I/O

pin PB5/Ain5 Analog

pin PB6/Ain6 Digital I/O

pin PB6/Ain6 Analog

pin PB7/Ain7 Digital I/O

pin PB7/Ain7 Analog

1

2

3

4

5

6

7

D1

D2

D3

D4

D5

D6

D7

Set the pin T0OUT/

PC1 in Input Mode

1

2

3

4

5

6

7

D1

D2

D3

D4

D5

D6

D7

Set the pin T1OUT/

PC2 in Output Mode

Set the pin T1OUT/

PC2 in Input Mode

Set the pin T2OUT/

PC3 in Output Mode

Set the pin T2OUT/

PC3 in Input Mode

Not used

Reset Configuration ‘11111111’

Reset Configuration

‘11111111’

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ST52T410/ST52T420/E420

PWM/Timers Alternate Functions

The pins of Port A and C can be configured to be I/

O of the three PWM/Timers available on the

ST52T410/ST52x420. The configuration of these

pins is performed by using the Configuration

Registers REG_CONF 12 and REG_CONF 16 if

the related pin has to be output. When the related

pin has to be used as an input peripheral the

configuration is performed by the relative

peripheral configuration registers (See PWM/

Timer Session).

Table 7.9 PWM/Timers REG_CONF 12

Bit

Name

Value

Description

Pin PA1/T0OUT is

configured as

PWM/Timer 0

1

complementary output

0

PA1

Pin PA1/T0OUT is

configured as

Port A Digital I/O

Warning: in order to use PC1, PC2 and PC3

pins as standard I/O pins, the PWM/Timers

must be configured in Timer mode

0

1

0

1

0

1

Table 7.8 PWM/Timers REG_CONF 16

Pin PA2/T1OUT is

configured as

PWM/Timer 1

Bit

Name

Value

Description

complementary output

1

PA2

Pin T0OUT/PC1 is

configured as Port C

Digital I/O

1

Pin PA2/T1OUT is

configured as

Port A Digital I/O

0

PC1

Pin T0OUT/PC1 is

configured as PWM/

Timer 0 output T0OUT

0

1

0

1

Pin PA3/T2OUT is

configured as

PWM/Timer 2

PinT1OUT/PC2 is

configured as Port C

Digital I/O

complementary output

2

PA3

Pin PA3/T2OUT is

configured as

Port A Digital I/O

1

PC2

Pin T1OUT/PC2 is

configured as PWM/

Timer 1 output T1OUT

Pin T2OUT/PC3 is

configured as Port C

Digital I/O

PORT A bits = 8

3

PASZ

NC

2

PC3

NC

Pin T2OUT/PC3 is

configured as PWM/

Timer 2 output T2OUT

0

x

PORT A bits = 7

Not Used

0

3-7

X

Not Used

4-7

Reset Configuration ‘0000’

Reset Configuration ‘00000000

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ST52T410/ST52T420/E420

Figure 7.3 Configuration Register 12

REG_CONF 12

DIGITAL PORT

D7 D6 D5 D4 D3 D2 D1 D0

PA1T: Pin PA1/T0OUT setting

PA2T: Pin PA2/T1OUT setting

PA3T: Pin PA3/T2OUT setting

PA78: PORT A size

not used

Figure 7.4 Configuration Register 16

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ST52T410/ST52T420/E420

8 A/D CONVERTER (ST52X420 ONLY)

8.1 Introduction

precision performance, along with one separate

supply (V

rejection.

), allowing the best supply noise

DDA

The A/D Converter of ST52x420 is an 8-bit analog

to digital converter with up to 8 analog inputs

offering 8 bit resolution with a total accuracy of 1

LSB and a typical conversion time of 8.2 µs with a

20 MHz clock. This period also includes the 5.1 µs

of the integral Sample and Hold circuitry, which

minimizes the need for external components and

allows quick sampling of the signal for a minimum

warping effect and Integral conversion error.

Up to 8 multiplexed Analog Inputs are available. A

group of signals can be converted sequentially by

simply programming the starting address of the

last analog channel to be converted.

Single or continuous conversion mode are

available.

The result of the conversion is stored in an 8-bit

Input Register (from IR 1 to IR 8).

Conversion is performed in 82 A/D clock

pulses.

The A/D converter is controlled via the

Configuration Register REG_CONF 3.

The A/D clock is derived from the clock master.

The maximum A/D clock frequency has to be 10

MHz. When the master clock is higher than 10

MHz it has to be divided by 2 using the SCK bit of

the A/D configuration register REG_CONF 3 (See

Table 8.1).

The A/D peripheral converts the input voltage with

a process of successive approximations using a

fixed clock frequency derived from the oscillator.

A Power-Down programmable bit allows the A/D

converter to be set to a minimum consumption idle

status.

The ST52x420 Interrupt Unit provides one

maskable channel for the End of Conversion

(EOC).

8.2 Operational Description

The conversion is monotonic, meaning that the

result never decreases if the analog input doesn’t

and never increases if the analog input doesn’t.

The conversion range is between the analog

V

and V references.

SS

DD

The converter uses a fully differential analog input

configuration for the best noise immunity and

If input voltage is greater than or equal to V

dda

(Voltage Reference high) then the result is equal to

FFh (full scale) without an overflow indication.

Figure 8.1 A/D Converter Structure

CONFIGURATION REGISTER 3

STR LP POW SEQ SCK CH0 CH1 CH2

INPUT REGISTER

1 ÷ 8

A/D CHANNEL 0

A/D CHANNEL 1

A/D CHANNEL 2

A/D CHANNEL 3

A/D CHANNEL 4

A/D CHANNEL 5

A/D CHANNEL 6

A/D CHANNEL 7

PB0/AIN0

PB1/AIN1

PB2/AIN2

PB3/AIN3

PB4/AIN4

PB5/AIN5

PB6/AIN6

PB7/PA7/AIN7

CONTROL

LOGIC

ANALOG

MUX

SAMPLE

&

HOLD

SUCCESSIVE APPROXMATION

A/D CONVERTER

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ST52T410/ST52T420/E420

If input voltage is less than V (voltage reference

low) then the result is equal to 00h.

The A/D converter is linear and the digital result of

the conversion is provided by the following

formula:

8.2.1 Operating Modes.

SS

Four main operating modes can be selected by

setting the values of the LP and SEQ bit in the A/D

configuration Register.

One Channel Single Mode

In this mode (SEQ = ‘0’’, LP = ‘0’) the A/D provides

an EOC signal after the end of channel i-th

conversion; then the A/D waits for a new start

event. Channel i-th is identified by the bit CH0,

CH1, CH2.

255inputVoltage

referenceVoltage

-----------------------------------------------

Digitalresult =

Where Reference Voltage is V - V .

The accuracy of the conversion is described in the

Electrical Characteristics Section.

i.e CH(2:0) = ‘011’ means conversion of channel 3

then stop.

Multiple Channels Single Mode

dda

ss

The A/D converter is not affected by the WAIT

mode.

When the MCU enters HALT mode with A/D

converter enabled, the converter is disabled until

HALT mode is terminated and the start-up delay

has elapsed. A stabilization period is also required

before accurate conversions can be performed.

In this mode (SEQ = ‘1’, LP = ‘0’) the A/D provides

an EOC signal after the end of the channels

sequence conversion identified by the bit CH0,

CH1, CH2; then the A/D waits for a new start event.

i.e. CH(2:0) = ‘011’ means conversion of channels

0,1,2 and 3 then stop.

Figure 8.2 Conf. Register (REG_CONF 3)

REG_CONF 3

D 7

D0

CH2 CH1 CH0 SCK SEQPOW LP STR

START/STOP

CONVERSION MODE SEL.

ON/OFF A/D

CONVERSION MODE SEL.

CLOCK SELECTOR

CHANNELS SEL.

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ST52T410/ST52T420/E420

One Channel Continuous Mode

setting CH2=0 CH1=0 CH0=0 only channel 0 is

converted.

In this mode (SEQ = ‘0’’, LP = ‘1’) a continuous

conversion flow is entered by a starting event on

the channel selected by the CH0, CH1, CH2 bits

For example: CH(2:0) = ‘011’ means continuous

conversion of channel 3. At the end of each

conversion the relative IR is updated with the last

conversion result, while the former value is lost.

b4 = SCK: Master clock divider. ST52x420 can

work with a clock frequency up to 20 MHz. The

SCK must be set to ‘1’ when the ST52x420 clock is

higher then 10 MHz. It is useful to set SCK = ‘1’

even when the clock master is lower than 10 MHz

and a high accuracy is required.

b3 = SEQ: Multiple/Single channel. When SEQ is

set to ‘0’ the channel identified by CH(2:0) is

converted. If SEQ is set to ‘1’ the group of channels

identified by CH(2:0) are converted.

b2= POW: Power Up/ Power Down. A logical ‘1’

enables the A/D logic and analog circuitry.

Logical level ‘0’ disables all power consuming

logic, allowing a low power idle status.

b1 = LP: Continuous/Single. When this bit is set to

‘1’ (continuous mode), the first conversion

sequences are started by the STR bit then a

continuous conversion flow is processed.

To stop the conversion STR has to be set to ‘0’.

Multiple Channels Continuous Mode

In this mode (SEQ = ‘1’’, LP = ‘1’) a continuous

conversion flow is entered by a starting event on

the channels selected by the CH0, CH1, CH2 bits.

i.e CH(2:0) = ‘011’ means continuous conversion

of channel 0,1,2 and 3.

At the end of each conversion the relative IRs are

updated with the last conversion results, while the

former values are lost.

To stop the conversion STR has to be set to ‘0’.

When LP=’0’ (single mode) only one sequence of

conversions is started when STR is set.

8.2.2 Power Down Mode.

b0 = STR: Start/Stop. A logical level ‘1’ enables

starting a conversion sequence; a logical level ‘0’

stops the conversion. When the A/D is running in

the Single Modes (LP=’0’), this bit is hardware

reset at the end of a conversion sequence.

Before enabling any A/D operation mode, set the

POW bit of the A/D configuration register to ‘1’ at

least 60 µs before the first conversion starts to

enable the biasing circuit inside the analog section

of the converter. Clearing the POW bit (POW = ‘0’)

is useful when the A/D is not used, reducing the

total chip power consumption. This state is also the

reset configuration and it is forced by hardware

when the core is in HALT state (after a HALT

instruction execution).

Table 8.1 A/D Conf. Register (Reg_Conf 3)

Bit

0

Name

STR

Value

0

Description

Stop Conversion

Start Conversion

Single Conversion

Continuous

1

8.3 A/D Registers Description

The result of the conversions of the 8 available

channels are loaded in the 8 Input Register from

decimal address 1 to decimal address 8. (IR (1:8)

see Table 2.2)). Every IR(1:8) is reloaded with a

new value at the end of the conversion of the

correspondent analog input.

By using the assembler instruction:

LDRI RAM_Reg. IR_i

the value stored in the i-th IR is transferred on the

RAM location RAM_Reg.

0

1

2

3

4

LP

1

0

A/D OFF

POW

SEQ

SCK

1

A/D ON

0

Single Channel Conv.

Multiple Channels Conv

Clock not Divided

Clock Divided

Channel 0

1

0

1

The A/D configuration register is the REG_CONF

3. Figure 7.2 illustrates the structure of this

register, which manages the A/D logic operation.

The A/D configuration register (REG_CONF 3) is

programmable as following:

000

001

010

011

100

101

110

111

5

6

7

Channel 1

Channel 2

b7-b5

= CH2, CH1, CH0: Last Conversion

Channel 3

CH(2:0)

Address. These 3 bits define the last analog input.

The first analog input is converted, then the

address is incremented for the successive

conversion until the channel identified by CH0-

CH2 is converted. The (CH2, CH1, CH0) bits

define the group of channels to be scanned. When

Channel 4

Channel 5

Channel 6

Channel 7

49/84

ST52T410/ST52T420/E420

9 WATCHDOG TIMER

The working frequency of the WDT (PRES CLK in

the Figure 9.1) is equal to the clock master. The

clock master is divided by 500, obtaining the WDT

CLK signal, which is used to fix the timeout of the

WDT.

9.1 Operational Description

The Watchdog Timer (WDT) is used to detect the

occurrence of a software fault, usually generated

by external interference or by unforeseen logical

conditions, which cause the application program to

abandon its normal sequence. The WDT circuit

Table 9.1 Watchdog Timing range (CLK=5

MHz)

generates an MCU reset on expiry of

a

programmed time period, unless the program

refreshes the WDT before the end of the

programmed time delay.

WDT timeout period (ms)

min

0.1

16 different delays can be selected by using the

WDT configuration register.

max

937.5

After the end of the delay programmed by the

configuration register if the WDT is activated (by

using the assembler instruction WDTSFR), it starts

a reset cycle pulling the reset pin low.

Once the WDT has been activated the application

program has to refresh this peripheral (by the

WDTSFR instruction) at regular intervals during

normal operation in order to prevent an MCU reset.

According to the WDT configuration register

values, a WDT delay may be defined between 0.1

ms and 937.5 mS when the clock master is 5 MHz.

By changing the clock master frequency the

timeout delay can be calculated according to the

configuration register values REG_CONF 2, as

described in the following section.

Warning: changing the REG_CONF2 value when

the WDT is active, a WDT reset is generated and

the CPU is restarted. To avoid this side effect, use

the WDTSLP instruction before changing the

REG_CONF2.

In order to stop the WDT during user program

execution the instruction WDTSLP has to be used.

Figure 9.1 Watchdog Block Diagram

REG_CONF 2

D3 D2

D1 D0

WDT

WDTRFR

RESET

WTD CLK

RESET

PRESCALER

GENERATOR

PRES CLK = CLK MASTER

WDTSLP

50/84

ST52T410/ST52T420/E420

9.2 Register Description

Table 9.3 Timeout Values with CLK = 5 MHz

The WDT timeout is defined by setting the value of

the REG_CONF 2. The first 4 bits of this register

are used, obtaining 16 different delays as

illustrated in Table 9.2. In Table 9.2 timeout is

expressed by using the number of WDT CLK. The

WDT CLK is derived from the clock master by a

division factor of 500. Timeout is obtained by

multiplying the WDT CLK pulse length for the

number of pulses defined by the configuration

register REG_CONF 2. Table 9.4 illustrates the

pulse lengths for typical values of the clock master.

Bit

Name

Value

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

x

Timeout Values (ms)

0.1

62.5

0

125

187.5

250

312.5

375

1

2

D (3:0)

Table 9.3 illustrates the timeout WDT values when

the Master Clock is 5 MHz.

437.5

500

562.5

625

Table 9.2 WDT REG_CONF 2

Bit

Name

Value

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

x

Timeout Values (WDT)

687.5

750

1

625

812.5

875

3

0

1250

1875

2500

3125

3750

4375

5000

5625

6250

6875

7500

8125

8750

9375

Not Used

937.5

Not Used

4-7

NC

1

2

Reset Configuration ‘0000’

D(3:0)

Table 9.4 Typical WDT CLK Pulse Length

WDT CLK

PULSE

LENGTH (ms)

MASTER CLK

(MHz)

WDT CLK

(KHz)

4

5

8

0.125

0.1

10

16

20

40

3

8

0.0625

0.05

10

20

0.025

4-7

NC

Reset Configuration ‘0000’

51/84

ST52T410/ST52T420/E420

10 PWM/TIMER

ST52T410/ST52x420 offers three on-chip PWM/

Timer peripherals:TIMER0, TIMER1 and TIMER2.

Note: In order to use T0RST, T0STR, T0CLK

external signals the related pins must be

configured in Input Mode by setting

REG_CONF4 and REG_CONF7 registers (see

Table 7.4 and Table 10.3)

For each timer, the content of the 8-bit counter is

incremented on the Rising Edge of the 16-bit

prescaler output (PRESCOUT) and it can be read

at any instant of the counting phase, saved in a

location of RAM memory. The PWM/Timer x

Counter value can be read from the Input Register

The ST52T410/ST52x420 timers have the same

internal structure. The timer consists of an 8-bit

counter with a 16-bit programmable prescaler,

24

giving a maximum count of 2 (see Figure 10.1).

Figure 10.1 Timer Peripheral Block Diagram

16-BIT PRESCALER

BIT 5

CLKM

BIT 14

BIT 15

BIT 0

BIT 1

BIT 2

BIT 3

BIT 4

PRESCx

17 - 1 MULTIPLEXER

TMRCLK

TxRES

8-BIT COUNTER

BIT 0

BIT 1

BIT 2

BIT 3

BIT 4

BIT 5

BIT 6

BIT 7

TxSTRT

PWM_x_COUNT (Input Registers 12, 14 or 16.

See Table 2.2).

Next, the generic timer is called Timer x, where x

can be 0, 1 or 2.

The PWM/Timer x Status can be read from the

Input Register PWM_x_STATUS (Input Registers

13, 15 or 17. See Table 2.2 and Table 10.10).

Each timer has two different working modes, which

can be selected by setting the correspondent

TxMODE bits of REG_CONF5, REG_CONF8 and

REG_CONF10 registers: Timer Mode and PWM

(Pulse Width Modulation) Mode.

All Timers have Autoreload Functions in PWM

Mode.

10.1 Timer Mode

Timer Mode is selected by fixing the TxMODE bit

of

REG_CONF5,

REG_CONF8

and

Each timer output is available, with its

complementary signal on external pins by setting

PAx and PCx bits of REG_CONF12 and

REG_CONF16 (see Table 10.8 and Table 10.9).

Note: In order to enable timer output (TxOUT or

TxOUT) the related pin must be configured in

Output Mode by setting REG_CONF4 and

REG_CONF15 registers (see Table 7.4 and

Table 7.6)

REG_CONF10 equal to 0 (see Table 10.1, Table

10.4 and Table 10.6).

Each TIMERx requires three signals: Timer Clock

(TMRCLKx), Timer Reset (TxRES) and Timer Start

(TxSTRT) (see Figure 10.1). Each of these signals

can be generated internally, or, only for Timer 0,

externally by setting T0RST, T0STR, T0CLK bits of

REG_CONF7 register.

TMRCLKx is the Prescaler

x output, which

In particular, TIMER0 can also use external

START/STOP signals (Input capture and Output

compare), external RESET signal and external

CLOCK: PA4/T0STRT, PA0/T0RES and PA5/

T0CLK pins.

increments the Counter x value on the rising edge.

TMRCLKx is obtained from the internal clock

signal (CLKM) or, only for TIMER0, from the

external signal provided on the PA5/T0CLK pin.

52/84

ST52T410/ST52T420/E420

Figure 10.2 Timer 0 External START/STOP Mode

start

stop

Level

stop

start

Edge

Reset

Clock

Counted

Value

2

0

1

3

4

0

1

NOTE: The external clock signal applied on the

T0CLK pin must have a frequency at least two

times smaller than the internal master clock.

When TxMSK is 1 the TIMER x is reset.

REMARK: to use the simultaneus start, the

prescalers of the Timers must have the same

value. Simultaneus start cannot be used in

Timer mode

The prescaler output can be selected by setting the

PRESCx bit of REG_CONF6, REG_CONF9 and

REG_CONF11 registers (see Table 10.2, Table

10.5 and Table 10.7).

REMARK: The first period of the TxOUT signal

is one clock cycle shorter.

Figure 10.3 TIMEROUT Signal Type

TxRES resets the content of the 8-bit counter x to

zero. It is generated by the TIRSTx and TxMSK

bits of REG_CONF5, REG_CONF7, REG_CONF8

and REG_CONF10 registers (see Table 10.1,

Table 10.3, Table 10.4 and Table 10.6).

Prescout*Counter

Timer Output

Type 1

TxSTRT signal starts/stops Timer x counting only

if the peripherals are configured in Timer mode.

This signal is forced by setting the correspondent

TISTRx bit of REG_CONF5, REG_CONF8 and

REG_CONF10 registers (see Table 10.1, Table

10.4 and Table 10.6).

Type 2

TxMSK bits mask the reset of each timer and can

be utilized to synchronize a simultaneous start of

the timers by means (for example), of the following

procedure, which starts three timers:

TIMER 0 START/STOP can be provided externally

on the T0STRT pin. In this case, the T0STRT

signal allows the user to work in two different

modes by setting the TESTR configuration bit of

REG_CONF5 register (see Figure 10.2) (Input

capture):

1) TIRST0 = TIRST1 = TIRST2 = 0,

2) TISTR0 = TISTR1 = TISTR2 = 0,

3) T0MSK = T1MSK = T2MSK = 1,

4) TIRST0 = TIRST1 = TIRST2 = 1,

5) TISTR0 = TISTR1 = TISTR2 = 1,

6) T0MSK = T1MSK = T2MSK = 0,

53/84

ST52T410/ST52T420/E420

Figure 10.4 PWM Mode with Auto Reload

255

compare

value

reload

register

0

t

PWM

Output

Ton

T

LEVEL (Time Counter): If the T0STRT signal is

high the Timer starts counting. When T0STRT is

low the counting ceases and the current value is

stored in the PWM_0_COUNT Input Register.

TMRWx bit of REG_CONF6, REG_CONF9 and

REG_CONF11 registers (see Table 10.2, Table

10.5 and Table 10.7)

WARNING:

in

Timer

Mode

the

EDGE(Period Counter): After reset, on the first

T0STRT rising edge, TIMER 0 starts counting and

at the next rising edge it stops. In this manner, the

period of an external signal may be measured.

Timer x output signal, TIMERxOUT is a signal with

a frequency equal to the 16 bit-Prescaler x output

signal, TMRCLKx, divided by the Output Register

PWM_x_COUNT value (8 bit) (Output Registers 3,

5 or 7. See Table 2.4), which is the value to count.

PWM_x_RELOAD output register (see below)

must be set to 0.

10.2 PWM Mode

For each timer, PWM working mode is obtained by

setting the correspondent TxMODE bits of

REG_CONF5, REG_CONF8 and REG_CONF10

registers to 1 (see Table 10.1, Table 10.4 and

Table 10.6).

REMARK: The first period of the TxOUT signal

is shorter than the other periods for a time

interval which is [0.5*TMRCLK-CLKM].

There can be two types of TIMERxOUT waveform:

type 1: TIMERxOUT waveform equal to a square

wave with a 50% duty-cycle.

TIMERxOUT, in PWM Mode consists of a signal

with a fixed period, whose duty cycle can be

modified by the user.

The TIMERxOUT signal can be available on the

TxOUT pin and the TIMERxOUT inverted signal

can be available on the TxOUT pin by setting the

PxSL bits of REG_CONF12 and REG_CONF16

(see Table 10.8 and Table 10.9)

type 2: TIMERxOUT waveform equal to a pulse

signal with the pulse duration equal to the

Prescaler x output signal.

For each Timer x, the TIMERxOUT waveform type

can be selected by setting the correspondent

54/84

ST52T410/ST52T420/E420

The PWM TIMERxOUT period can be determined

by setting the 16-bit prescaler x output and an

initial autoreload 8-bit counter value stored in the

Output Register PWM_x_RELOAD, as illustrated

in Figure 10.4.

NOTE: the Start/Stop and Set/Reset signals

should be moved together in PWM mode. If the

Start/Stop bit is reset during the PWM mode

working, the TxOUT signal keeps its status

until the next start.

By using a 20 MHz clock master a PWM frequency

in the range 1.2 Hz to 78.43 Khz can be obtained.

WARNING: loading new values of the counter

or of the reload in the Output Registers, the

PWM/Timer registers are immediately set on-

fly. This can cause some side effects during

the current counting cycle. The next cycles

work normally. This occurs both in Timer and

in PWM mode.

When the Timers are in Reset, or when the

device is reset, TxOut pins go in threestate. If

these outputs are used to drive external

devices it is recommended to put a pull-up or a

pull-down resistor.

The Output Register PWM_x_RELOAD value is

automatically reloaded when Counter x restarts

counting.

The 16-bit Prescaler x divides the master clock,

CLKM, or, only for TIMER0, the external T0CLK

signal, by the 16-bit Prescaler x.

10.3 Timer Interrupt

NOTE: The external clock signal, applied on

T0CLK pin must have a frequency at least two

times smaller than the internal master clock.

The Prescaler x output can be selected by setting

PRESCx bit of REG_CONF6, REG_CONF9 and

REG_CONF11 registers (see Table 10.2, Table

10.5 and Table 10.7).

TIMERx can be programmed to generate an

Interrupt request at the end of the count or when

there is an external TSTART signal. The Timer can

generate programmable Interrupts into 4 different

modes:

Interrupt mode 1: Interrupt on counter Stop.

Interrupt mode 2: Interrupt on Rising Edge of

When Counter x reaches the Peripheral Register

TIMEROUT.

PWM_x_COUNT

value

(Compare

Value),

Interrupt mode 3: Interrupt on Falling Edge of

TIMEROUT.

Interrupt mode 4: Interrupt on both edges of

TIMEROUT.

Interrupt mode can be selected by means of

INTSLx and INTEx bits of the REG_CONF5,

REG_CONF8 and REG_CONF10 registers (see

Table 10.1, Table 10.4 and Table 10.6).

TIMERxOUT signal changes from high to low level,

up to the next counter start.

The period of the PWM signal is obtained by using

the following equation:

T = (255 - PWM _x_RELOAD)x TMR CLKx

where TMRCLKx is the output of the 16-bit

prescaler x.

The duty cycle of the PWM signal is controlled by

the Output Register PWM_x_COUNT:

NOTE: the interrupt on TIMEROUT rising edge

is also generated after the Start.

Ton =(PWM_x_COUNT- PWM_x_RELOAD)*

TMRCLKx

If the Output Register PWM_x_COUNT value is

255 the TIMERxOUT signal is always at a high

level.

WARNING: the first interrupt after starting

PWM is not generated if the counter value is 0,

255, or lower than the reload value. If the PWM/

Timer is configured with the Interrupt on Stop

and the Start/Stop is configured as external, a

low signal in the STRT pin determines a PWM/

Timer interrupt even if the peripheral is off. If

the interrupt is configured on falling edge, a

reset signal generates an interrupt request.

If the Output Register PWM_x_COUNT is 0, or

less

than

the

PWM_x_RELOAD

value,

TIMERxOUT signal is always at a low level.

NOTE. If PWM_x_RELOAD value increases the

duty cycle resolution decreases. PWM cannot

work with a PWM_x_RELOAD value equal to

255.

55/84

ST52T410/ST52T420/E420

Table 10.1 Configuration Register 5 Description

Bit

Name

Value

Description

0

1

0

1

0

1

0

1

PWM/TIMER 0 Internal RESET

PWM/TIMER 0 Internal SET

External RESET on Level

External RESET on Edge

PWM/TIMER 0 Internal STOP

PWM/TIMER 0 Internal START

External START on Level

External START on Edge

TIRST0

1

2

3

TERST

TISTR0

TESTR

TIMER0 Interrupt on TIMER Interrupt on

TIMEROUT Falling Edge

00

01

4

5

6

7

TIMER0 Interrupt on

TIMER0OUT Rising Edge

INTE0

10

11

TIMER0 Interrupt on Both Edges of TIMER0OUT

- not used

TIMER0 Interrupt on

Counter Stop

0

1

INTSL0

TIMER0 Interrupt on

TIMER0OUT

0

1

TIMER MODE

PWM MODE

T0MODE

Figure 10.5 Configuration Register 5

REG_CONF 5

TIMER 0

D7 D6 D5 D4 D3 D2 D1 D0

TIRST0: Timer 0 Internal RESET

TERST: Timer 0 External RESET on Edge/Level

TISTR0: Timer 0 Internal START

TESTR: Timer 0 External START on Edge/Level

INTE0: Timer 0 Interrupt on TIMER0OUT Rising/Falling Edge

INTSL0: Timer 0 Interrupt Source selection

T0MODE: Timer 0 working mode

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ST52T410/ST52T420/E420

Table 10.2 Configuration Register 6 Description

Bit

Name

Value

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

Description

TIMER0 Clock = CLKM / 1

TIMER0 Clock = CLKM / 2

TIMER0 Clock = CLKM / 4

TIMER0 Clock = CLKM / 8

TIMER0 Clock = CLKM / 16

TIMER0 Clock = CLKM / 32

TIMER0 Clock = CLKM / 64

TIMER0 Clock = CLKM / 128

TIMER0 Clock = CLKM / 256

TIMER0 Clock = CLKM / 512

TIMER0 Clock = CLKM/1024

TIMER0 Clock = CLKM/2048

TIMER0 Clock = CLKM/4096

0

1

2

PRESC0

3

01101

TIMER0 Clock = CLKM/8192

TIMER0 Clock=CLKM/16384

TIMER0 Clock=CLKM/32768

TIMER0 Clock=CLKM /65536

TIMER0OUT Waveform equal to pulse wave

TIMER0OUT Waveform equal to square wave

- not used

01110

4

5

01111

10000

0

1

-

TMRW0

6

7

-

- not used

Figure 10.6 Configuration Register 6

REG_CONF 6

TIMER 0

D7 D6 D5 D4 D3 D2 D1 D0

PRESC0: Timer 0 Prescaler

TMRW0: TIMER0OUT waveform

not used

57/84

ST52T410/ST52T420/E420

Table 10.3 Configuration Register 7 Description

Bit

Name

Value

00

01

10

11

Description

TIMER0 RESET

0

TIMER0 RESET External

TIMER0 RESET External or Internal

- not used

T0RST

1

00

01

10

11

TIMER0 START Internal

TIMER0 START External

TIMER0 START External or Internal

- not used

2

3

T0STR

T0CLK

T0MSK

0

TIMER0 Clock Internal

TIMER0 Clock External

4

5

1

TIMER 0 reset synchronization mask.

TIMER 0 RESET enabled

0

1

0

1

0

1

TIMER0 reset synchronization mask.

TIMER0 RESET masked

TIMER2 reset synchronization mask.

TIMER2 RESET enabled

6

7

T2MSK

T1MSK

TIMER2 reset synchronization mask.

TIMER2 RESET masked

TIMER1 reset synchronization mask.

TIMER1 RESET enabled

TIMER1 reset synchronization mask.

TIMER1 RESET masked

Figure 10.7 Configuration Register 7

REG_CONF 7

TIMER 0, TIMER 1, TIMER2

D7 D6 D5 D4 D3 D2 D1 D0

T0RST: Timer 0 RESET Mode

T0STR: Timer 0 START Mode

T0CLK: Timer 0 Clock Source

T0MSK: Timer 0 RESET Mask

T2MSK: Timer 2 RESET Mask

T1MSK: Timer 1 RESET Mask

58/84

ST52T410/ST52T420/E420

Table 10.4 Config. Register 8 Description

Bit

Name

Value

Description

0

1

-

PWM\TIMER 1 Internal RESET

PWM\TIMER 1 Internal SET

- not used

0

TIRST1

1

2

-

0

1

-

PWM/TIMER 1 Internal STOP

PWM/TIMER 1 Internal START

- not used

TISTR1

3

4

-

00

TIMER1 Interrupt on TIMER1OUT Falling Edge

01

10

11

0

TIMER1 Interrupt on TIMER1OUT Rising Edge

TIMER1 Interrupt on Both Edges of TIMER1OUT

- not used

INTE1

5

TIMER1 Interrupt on Counter Stop

TIMER1 Interrupt on TIMER1OUT

TIMER MODE

6

7

INTSL1

1

0

T1MODE

1

PWM MODE

Figure 10.8 Configuration Register 8

REG_CONF 8

TIMER 1

D7 D6 D5

D3

D0

D2 D1

D4

TIRST1: Timer 1 RESET

- not used

TISTR1: Timer 1 START

- not used

INTE1: Timer 1 Interrupt on TIMER1OUT Rising/Falling Edge

INTSL1: Timer 1 Interrupt Source selection

T1MODE: Timer 1 working mode

59/84

ST52T410/ST52T420/E420

Table 10.5 Config. Register 9 Description

Bit

Name

Value

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

10000

0

Description

TIMER1 Clock = CLKM / 1

TIMER1 Clock = CLKM / 2

TIMER1 Clock = CLKM / 4

TIMER1 Clock = CLKM / 8

TIMER1 Clock = CLKM / 16

TIMER1 Clock = CLKM / 32

TIMER1 Clock = CLKM / 64

TIMER1 Clock = CLKM / 128

TIMER1 Clock = CLKM / 256

TIMER1 Clock = CLKM / 512

TIMER1 Clock =CLKM / 1024

TIMER1 Clock =CLKM / 2048

TIMER1 Clock =CLKM / 4096

TIMER1 Clock =CLKM / 8192

TIMER1 Clock =CLKM/16384

TIMER1 Clock=CLKM /32768

TIMER1 Clock=CLKM /65536

TIMER1OUT Waveform equal to pulse wave

TIMER1OUT Waveform equal to square wave

- not used

0

1

2

3

PRESC1

4

5

TMRW1

1

6

7

-

- not used

Figure 10.9 Configuration Register 9

REG_CONF 9

TIMER 1

D7 D6 D5 D4 D3 D2 D1 D0

PRESC1: Timer 1 Prescaler

TMRW1: TIMER1OUT waveform

not used

60/84

ST52T410/ST52T420/E420

Table 10.6 Config. Register 10 Description

Bit

Name

Value

Description

0

1

PWM/TIMER 2 Internal RESET

PWM/TIMER 2 Internal SET

- not used

0

TIRST2

1

2

-

0

PWM/TIMER 2 Internal STOP

PWM/TIMER 2 Internal START

- not used

TISTR2

1

3

4

-

00

TIMER2 Interrupt on TIMER2OUT Falling Edge

01

TIMER2 Interrupt on TIMER2OUT Rising Edge

INTE2

10

11

0

TIMER2 Interrupt on Both Edges of TIMER2OUT

- not used

5

6

7

TIMER2 Interrupt on Counter Stop

TIMER2 Interrupt on TIMER2OUT

TIMER MODE

INTSL2

1

0

T2MODE

1

PWM MODE

Figure 10.10 Configuration Register 10

REG_CONF 10

TIMER 2

D7 D6 D5

D3

D0

D2 D1

D4

TIRST2: Timer 2 RESET

- not used

TISTR2: Timer 2 START

- not used

INTE2: Timer 2 Interrupt on TIMER2OUT Rising/Falling Edge

INTSL2: Timer 2 Interrupt Source selection

T2MODE: Timer 2 working mode

61/84

ST52T410/ST52T420/E420

Table 10.7 Config. Register 11 Description

Bit

Name

Value

Description

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

10000

0

TIMER2 Clock = CLKM / 1

TIMER2 Clock = CLKM / 2

TIMER2 Clock = CLKM / 4

TIMER2 Clock = CLKM / 8

TIMER2 Clock = CLKM / 16

TIMER2 Clock = CLKM / 32

TIMER2 Clock = CLKM / 64

TIMER2 Clock = CLKM / 128

TIMER2 Clock = CLKM / 256

TIMER2 Clock = CLKM / 512

TIMER2 Clock = CLKM /1024

TIMER2 Clock = CLKM/ 2048

TIMER2 Clock = CLKM/ 4096

TIMER2 Clock = CLKM/ 8192

TIMER2 Clock= CLKM/16384

TIMER2 Clock =CLKM/32768

TIMER2 Clock =CLKM/65536

TIMER2OUT Waveform equal to pulse wave

TIMER2OUT Waveform equal to square wave

- not used

0

1

2

3

PRESC2

4

5

TMRW2

1

6

7

-

- not used

Figure 10.11 Configuration register 11

REG_CONF 11

TIMER 2

D7 D6 D5 D4 D3 D2 D1 D0

PRESC2: Timer 2 Prescaler

TMRW2: TIMER2OUT waveform

not used

62/84

ST52T410/ST52T420/E420

Table 10.8 Config. Register 12 Description

Bit

Name

Value

Description

0

1

0

1

0

1

0

1

-

Pin PA1/T0OUT equal to PORT A Digital I/O

Pin PA1/ T0OUT equal to T0OUT

Pin PA2/ T1OUT equal to PORT A Digital I/O

Pin PA2/ T1OUT equal to T1OUT

Pin PA3/ T2OUT equal to PORT A Digital I/O

Pin PA3/ T2OUT equal to T2OUT

PORT A bits = 7

0

PA1

1

2

3

PA2

PA3

PASZ

PORT A bits = 8

4

5

6

7

-

- not used

-

- not used

-

- not used

-

- not used

Figure 10.12 Configuration Register 12

REG_CONF 12

DIGITAL PORT

D5

D7 D6

D4 D3 D2 D1 D0

PA1: Pin PA1/T0OUT setting

PA2: Pin PA2/T1OUT setting

PA3: Pin PA3/T2OUT setting

PASZ: PORT A size

not used

63/84

ST52T410/ST52T420/E420

Table 10.9 Config. Register 16 Description

Bit

Name

Value

Description

1

0

1

0

1

0

-

Pin T0OUT/PC1 equal to PORT C Digital I/O

Pin T0OUT/PC1 equal to T0OUT

Pin T1OUT/PC2 equal to PORT C Digital I/O

Pin T1OUT/PC2 equal to T1OUT

Pin T2OUT/PC3 equal to PORT C Digital I/O

Pin T2OUT/PC3 equal to T2OUT

- not used

0

PC1

1

PC2

2

PC3

-

3-7

Figure 10.13 Configuration Register 16

64/84

ST52T410/ST52T420/E420

Table 10.10 Input Registers 13.

PWM_0_STATUS

Table 10.12 Input Registers 17.

PWM_2_STATUS

Bit

Name

Value

Description

Bit

Name

Value

Description

0

STR0

0

1

0

TIMER 0 is STOP

TIMER 0 START

TIMER 0 is RESET

0

STR2

0

1

0

TIMER 2 is STOP

TIMER 2 is START

TIMER 2 is RESET

1

RST0

1

RST2

TIMER 0 is NOT

RESET

TIMER 2 is NOT

RESET

1

2

3

4

5

6

7

-

- not used

2

3

4

5

6

7

-

- not used

Table 10.11 Input Registers 15.

PWM_1_STATUS

Bit

Name

Value

Description

TIMER 1 is STOP

TIMER 1 is START

TIMER 1 is RESET

TIMER 1 is NOT

- not used

0

STR1S

0

1

0

1

-

1

RST1S

2

3

4

5

6

7

-

- not used

-

- not used

-

- not used

-

- not used

-

- not used

65/84

ST52T410/ST52T420/E420

11 ELECTRICAL CHARACTERISTICS

11.1.4 Loading capacitor. The loading condition

used for pin parameter measurement is illustrated

in Figure 11.1.

11.1 Parameter Conditions

Unless otherwise specified, all voltages are

11.1.5 Pin input voltage.

referred to V

ss.

Input voltage measurement on a pin of the device

is described in Figure 11.2

11.1.1 Minimum and Maximum values.

Unless otherwise specified, the minimum and

maximum values are guaranteed in the worst

conditions of environment temperature, supply

voltage and frequencies production testing on

100% of the devices with an environmental

Figure 11.2 Pin input Voltage

temperature at T =25°C and T =T max (given by

A

the selected temperature range).

Data is based on characterization results, design

simulation and/or technology characteristics are

indicated in the table footnotes and are not tested

in production. The minimum and maximum values

are based on characterization and refer to sample

tests, representing the mean value plus or minus

three times the standard deviation (mean ±3Σ).

ST52 PIN

11.1.2 Typical values.

Unless otherwise specified, typical data is based

V_IN

on T =25°C, V =5V (for the 4.5≤V ≤5.5V

A

DD

voltage range). They are provided only as design

guidelines and are not tested.

11.1.3 Typical curves.

Unless otherwise specified, all typical curves are

provided only as design guidelines and are not

tested.

Figure 11.1 Pin loading conditions

11.2 Absolute Maximum Ratings

Stresses above those listed as “absolute maximum

ratings” may cause permanent damage to the

device. This is a stress rating only.

Functional operation of the device under these

conditions is not implied. Exposure to maximum

rating conditions for extended periods may affect

device reliability.

ST52 PIN

C_L

66/84

ST52T410/ST52T420/E420

Table 11.1 Voltage Characteristics

Symbol

Ratings

Maximum Value

Unit

V

-V

Supply voltage

6.5

50

DD SS

V

Analog reference voltage(V ≥V

)

V

-V

DD

DDA

DDA SSA

Variation between different digital power pins

Variation between digital and analog ground pins

Input voltage on Vpp

|∆V

|and |∆V

|

SSA

DDA

mV

V

50

|V

-V

|

SSA SSX

V

-0.3 to 13

SS

V

IN

1) & 2)

V

-0.3 to V +0.3

SS

DD

Input voltage on any other pin

V

Electro-static discharge voltage

2000

DESD

Table 11.2 Current Characteristics

Symbol

Ratings

Maximum Value

Unit

3)

I

100

±16

±5

VDD

Total current in V power lines (source)

DD

3)

I

VSS

Total current in V ground lines (sink)

SS

I

Standard Output Source Sink current

IO

Injected current on V pin

PP

mA

Injected current on RESET pin

±5

I

INJ(PIN)

Injected current on OSCin and OSCout pins

±5

4)

±5

Injected current on any other pin

Total Injected current (sum of all I/O and control

ΣI

±20

INJ(PIN)

4)

pins)

Table 11.3 Thermal Characteristics

Symbol

Ratings

Maximum Value

-25 to +85

-65 to +150

150

Unit

°C

T

Operating temperature

A

T

Storage temperature range

Maximum junction temperature

°C

STG

T

°C

J

Notes:

1. Connecting RESET and I/O Pins directly to VDD or VSS could damage the device if the unintentional internal reset is generated

or an unexpected change of I/O configuration occurs (for example, due to the corrupted program counter). In order to guarantee

safe operation, this connection has to be performed via a pull-up or pull-down resistor (typical: 4.7k Ω for RESET, 10K Ω for I/Os).

Unused I/O pins must be tied in the same manner to VDD or VSS according to their reset configuration.

2. When the current limitation is not possible, the VIN absolute maximum rating must be respected, otherwise refer to I INJ(PIN)

specification. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSSto I INJ(PIN) specification.

A positive injection is VIN>VDD while a negative injection is induced by VIN<VSS.

3. All power (VDD) and ground (VSS) lines must always be connected to the external supply.

4. When several inputs are submitted to a current injection, the maximum ΣI

injected currents (instantaneous values).

is the absolute sum of the positive and negative

INJ(PIN)

67/84

ST52T410/ST52T420/E420

11.3 Recommended Operating Condition

Operating condition: VDD=5V±10%; TA= -25/85°C (unless otherwise specified).

Table 11.4 Recommended Operating Conditions

Symbol

Parameter

Test Condition

Min.

4.75

11.4

Typ.

5.0

12

Max

5.25

12.6

Unit

1)2)

Refer to Figure 11.3

V

Operating Supply

DD

V

Programming Voltage

Output Voltage

PP

V

O

SS

DD

1)

V

≤V

DDA, SSA

SS

SSA

DDA DD

Analog Supply Voltage

1)2)

Oscillator Frequency

1

20

MHz

f

OSC

Notes:

1. The maximum difference between V and V

and between V and V must be less than 0.6 V

DDA,

SS

SSA,

DD

in module. The minimum value of V

is 3 V.

DDA

2. V depend on f_{OSC ,}see Figure 11.3

DD

3. The f_OSCmin allowed to use the A/D Converter is 2 MHz

4. Lower V decreasing f (see Figure 11.3). Data illustrated in the figure are characterized but not test-

DD

osc

ed.

Figure 11.3 fosc Maximum Operating Frequency versus VDD supply

20

18

16

14

Functionality not guarateed in this area

12

10

8

Functionality guarateed in this area

6

4

2

0

Functionality not guarateed in this area

3.5 4.5 5.5

0

1

1.5

2

2.5

3

0.5

4

5

Vdd (V)

68/84

ST52T410/ST52T420/E420

11.4 Supply Current Characteristics

The test condition in RUN mode for all the IDD

measurements are:

Supply current is mainly a function of the operating

voltage and frequency. Other factors such as I/O

pin loading and switching rate, oscillator type,

internal code execution pattern and temperature,

also have an impact on the current consumption.

OSCin = external square wave, from rail to rail;

OSCout = floating;

All I/O pins tristated pulled to VDD

TA=25°C

Table 11.5 Supply Current in RUN and WAIT Mode

3)

Symbol

Parameter

Conditions

Typ

Unit

Max

f

=2 Mhz

=4 Mhz

=5 Mhz

=8 Mhz

4.34

7.66

8.75

12.67

15.04

27.3

1.14

3.38

3.63

5.63

6.29

13.22

4.34

7.72

8.81

12.89

15.13

27.48

1.16

3.39

3.71

5.68

6.31

13.3

osc

1)

Supply current in RUN mode

f

=10

=20

osc

V

=5V±5%

DD

osc

I

mA

DD

f

=2 MHz

=4 MHz

=5 MHz

TA=25°C

osc

2)

Supply current in WAIT mode

f

=8 Mhz

osc

f

=10

osc

=20

Notes:

1. CPU running with memory access, all I/O pins in input mode with a static value at V or V (no load),

DD

SS

all peripherals switched off; clock input (OSCin driven by external square wave).

2. CPU in WAIT mode with all I/O pins in input mode with a static value at V

peripherals switched off; clock input (OSCin driven by external square wave).

or V (no load), all

SS

DD

3. Data based on characterization results, tested in production at V

and f

.

oscmax

DDmax

Figure 11.4 Typical IDD in RUN vs fosc

Figure 11.5 Typical IDD in WAIT vs fosc

14

12

10

8

35

30

25

20

15

10

5

6

4

2

0

2

2.5

3

3.5

4

4.5

5

5.5

6

2

2.5

3

3.5

4

4.5

5

5.5

6

VDD[V]

2MHz

4MHz

5MHz

8MHz

10MHz

20MHz

2MHz

4MHz

5MHz

8MHz

10MHz

20MHz

69/84

ST52T410/ST52T420/E420

Table 11.6 Supply Current in HALT Mode

1)

Symbol

Parameter

Conditions

Max

Unit

Typ

2)

I

3.0 V≤ VDD ≤ 5.5 V

1

10

µA

DDA

Supply current in HALT mode

Notes:

1. Typical data is based on TA = 25 °C

2. All I/O pins in input mode with a static value at VDD or VSS (no load)

Table 11.7 On-Chip Peripheral

3

4

Symbol

Parameter

Conditions

Unit

Typ

Max

fosc=20MHz, V

= 5 ±5% V,

DDA

I

ADC Supply current when converting

1

2

mA

VssA = Vss

=V

DDA

V

SSA

SS

Notes:

3. Typical data is based on T =25°C, V

=5 V.

DDA

A

4. Data is based on characterization results and isn’t tested in production.

70/84

ST52T410/ST52T420/E420

11.5 Clock and Timing Characteristics

Operating Conditions: VDD=5V ±5%, TA=-25/85°C, unless otherwise specified

Table 11.8 General Timing Parameters

Symbol

Parameters

Oscillator Frequency

Clock High

Test Condition

Min

1

Typ.

Max

20

Unit

f

MH

osc

t

25

500

CLH

t

Clock Low

CLL

SET

HLD

t

Setup

See Figure 11.6

5

t

Hold

t

Minimum Reset Pulse Width

f

=20MHz

100

WRESET

osc

nS

Minimum External Interrupt

Pulse Width

t

f

WINT

t

Input Rise Time

Input Fall Time

Output Rise Time

Output Fall

See Figure 11.7

15

IR

t

IF

t

C

=10pF

10

OR

LOAD

t

OF

Figure 11.6 Data Input Timing

Figure 11.7 I/O Rise and Fall Timing

t_CLL

t_CLH

50%

t_CP

50%

Data

t_SETt_HLD

50%

Clock

71/84

ST52T410/ST52T420/E420

11.6 Memory Characteristics

Subject to general operating conditions for VDD, fosc and TA, unless otherwise specified.

Table 11.9 RAM and Registers

Symbol

Parameter

Conditions

Min.

Typ.

Max

15

Unit

Data retention

HALT mode (or

RESET)

VRM

1.6

V

1)

mode

Table 11.10 EPROM Program Memory

Symbol

Parameter

Conditions

Min.

Typ.

Unit

Lamp

wavelength

2537 A

Watt,

WERASE

UV lamp

15

2)

sec/cm

UV lamp is

placed 1 inch

from the device

window without

any interposed

filters

2)

tERASE

7

min.

Erase time

t^RET

Data Retention

20

years

TA =+55°C

Notes:

1. Minimum VDD supply voltage without losing data stored into RAM (in HALT mode or under RESET) or

into hardware registers (only in HALT mode). Guaranteed by construction, not tested in production.

2. Data is provided only as a guideline.

72/84

ST52T410/ST52T420/E420

11.7 ESD Pin Protection Strategy

presented in Figure 11.8 and Figure 11.9 for

standard pins.

In order to protect an integrated circuit against

Electro-Static Discharge the stress must be

controlled to prevent degradation or destruction of

the circuit elements. Stress generally affects the

circuit elements, which are connected to the pads

but can also affect the internal devices when the

supply pads receive the stress. The elements that

are to be protected must not receive excessive

current, voltage, or heating within their structure.

11.7.1 Standard Pin Protection

In order to protect the output structure the following

elements are added:

- A diode to V (3a) and a diode from V (3b)

DD

SS

- A protection device between V and V (4)

DD

SS

In order protect the input structure the following

elements are added:

An ESD network combines the different input and

output protections. This network works by allowing

safe discharge paths for the pins subject to ESD

stress. Two critical ESD stress cases are

- A resistor in series with pad (1)

- A diode to V (2a) and a diode from V (2b)

DD

SS

- A protection device between V and V (4)

DD

SS

Figure 11.8 Safe discharge path subjected to ESD stress

VDD

(3a)

(2a)

(1)

OUT

(4)

IN

Main path

Path to avoid

(3b)

(2b)

VSS

Figure 11.9 Negative Stress on a Standard Pad vs. VDD

VDD

(3a)

(2a)

(1)

OUT

(4)

IN

Main path

(3b)

(2b)

VSS

73/84

ST52T410/ST52T420/E420

11.7.2 Multi-supply Configuration.

illustrated in Figure 11.10 is implemented in order

to protect the device against ESD.

When several types of ground (V , V

,...) and

SSA

SS

power supply (V , V

,...) are available for any

DD

DDA

reason (better noise immunity...), the structure

Figure 11.10 ESD Protection for Multisupply Configuration

VDD

VDDA

(4)

VDDA

VSS

(4)

VSSA

BACK TO BACK DIODE

BETWEEN GROUNDS

74/84

ST52T410/ST52T420/E420

11.8 Port Pin Characteristics

11.8.1 General Characteristics.

Subject to general operating condition for V , f

and T unless otherwise specified.

A ,

DD osc,

1)

Symbol

Parameter

Condition

Min

Max

2

Unit

Typ

CMOS type low level input voltage.

Port B pins. (See Figure 11.13)

V

IL

TTL type Schmitt trigger low level

input voltage. Port A and Port C

pins. (See Figure 11.12)

0.8

CMOS type high level input voltage.

Port B pins. (See Fig 11.13)

3.3

2.2

V

IH

TTL type Schmitt trigger high level

input voltage. Port A and Port C

pins. (See Fig. 11.12)

2)

V

1.4

Schmitt trigger voltage hysteresis

hys

I

V

≤V ≤V

DD

Input leakage current

-1

4

L

SS

IN

µA

3)

Floating input mode

200

Static current consumption

S

Notes:

1. Unless otherwise specified, typical data is based on T =25 °C and V =5 V

A

DD

2. Hysteresis voltage between Schmitt trigger switching level. Based on characterization results, not

tested in production.

3. Configuration is not recommended, all unused pins must be kept at a fixed voltage: using the output

mode of the I/O for example or an external pull-up or pull-down resistor (see Figure 11.11). Data based

on design simulation and/or technology characteristics is not tested in production.

Figure 11.11 Recommended configuration for unused pins

VDD

ST52

UNUSED I/O PORT

10k

UNUSED I/O PORT

ST52

75/84

ST52T410/ST52T420/E420

Subject to general operating conditions for VDD, fosc, and TA, unless otherwise specified.

Table 11.11 Output Voltage Levels

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V

0.4

+

Output low level voltage for standard I/O

pin when 8 pins are sunk at same time.

SS

1)

V

=5V, I =+8mA

V

DD

IO

OL

V

Output high level voltage for standard I/

O pin when 8 pins are sourced at same

time.

V

0.5

-

DD

2)

=5V, I =- 8mA

V

DD

IO

OH

Notes:

1. The I current sunk must always respects the absolute maximum rating specified in Section 11.2 and the sum of I

IO

(I/O ports and control pins) must not exceed I

VSS

2. The I sourced current must always respect the absolute maximum rating specified in Section 11.2 and the sum of I

IO

(I/O ports and control pins) must not exceed I

VDD.

Figure 11.13 Port B pins CMOS-level input

Figure 11.12 TTL-Level input Schmitt Trigger

5

4

5

4

V =5V

DD

V(V)

o

V = 5V

DD

V (V)

o

T_A= 25°C

(TYPICAL)

3

2

1

T_A= 25°C

(TYPICAL)

3

2

1

0.5 0.8 1.0

1.5

V(V)

2.0 2.5

0

2.0

3.3

5.0

0

i

V (V)

i

76/84

ST52T410/ST52T420/E420

Subject to general operating condition for VDD, fosc, and TA, unless otherwise specified.

Table 11.12 Output Driving Current

Symbol

RS

Parameter

Test Conditions

All input Pins

Min

Typ

1

Max

Unit

kΩ

Input protection resistor

Pin Capacitance

CS

5

pF

Figure 11.14 Port A and Port C pin Equivalent Circuit

VDD

Device

Input/Output

S

R

V

IN

S

C

OUT

V

SS

V

SS

V

Figure 11.15 Port B Pin Equivalent Circuit

VDD

Device

Input/Output

S

R

V

IN

S

C

OUT

V

SS

V

SS

V

77/84

ST52T410/ST52T420/E420

11.9 Control Pin Characteristics

11.9.1 RESET pin.

Subject to general operating conditions for VDD, fosc, and TA, unless otherwise specified

Table 11.13 Reset pin

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

1)

V

= 5 V

0.8

Input low level voltage

IL

DD

1)

V

2.2

V

Input high level voltage

IH

2)

V

1.4

30

Schmitt trigger voltage hysteresis

General reset pulse duration

External reset pulse hold time

hys

t

w(RSTL)out

µS

t

20

h(RSTL)int

11.9.2 V pin.

PP

Subject to general operating conditions for V

f

, and T ,unless otherwise specified.

DD, osc A

4)

Table 11.14 V

Symbol

PP

Parameter

Input low level voltage

Conditions

Min

Typ

Max

0.2

Unit

3)

V

IL

SS

V

3)

V

-0.1

12.6

Input high level voltage

IH

DD

Notes:

1. Data is based on characterization results, not tested in production.

2. Hysteresis voltage between Schmitt trigger switching level.

Based on characterization results not tested in production.

3. Data is based on design simulation and/or technology characteristics, not tested in production.

4. In working mode V must be tied to V

PP

SS

78/84

ST52T410/ST52T420/E420

11.10 8-bit A/D Characteristics

Subject to general operating conditions for VDD, fosc, and TA, unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

8

Max

Unit

bit

Res

Resolution

1)

A

1 MHz<f

< 20 MHz

±1

LSB

µS

V

TOT

Total Accuracy

ADC

t

Conversion Time

82/f

160/f

ADC

C

ADC

V

Conversion Range

V

DDA

AN

SSA

Conversion result =

00 Hex

V

Zero Scale Voltage

Full Scale Voltage

V

ZI

SSA

Conversion result =

FF Hex

V

FS

DDA

Analog Input Current

during Conversion

AD

f

=20MHz

ADC

1

µA

I

AC

Analog Input Capacitance

ADC Clock frequency

25

pF

IN

f

/2

f

osc

MHz

ADC

osc

Notes:

1. Noise on V

, V

< 40 mV

DDA

SSA

79/84

ST52T410/ST52T410/E420

Table 11.15 PS028 PACKAGE MECHANICAL DATA

mm

inch.

TYP.

DIM

MIN

TYP.

MAX

2.65

0.3

MIN

MAX

0.104

0.012

0.019

0.013

A

a1

b

0.1

0.004

0.014

0.009

0.35

0.23

0.49

0.32

b1

C

0.5

0.020

c1

D

45°(typ.)

17.7

10

18.1

0.697

0.394

0.713

0.419

E

10.65

e

1.27

0.050

0.65

e3

F

16.51

7.4

0.4

7.6

0.291

0.016

0.299

0.050

L

1.27

S

8°(max)

L

b

e

e3

D

E

15

28

1

14

80/84

ST52T410/ST52T420/E420

Table 11.16 Plastic DIP28 PACKAGE MECHANICAL DATA

mm

inch

DIM

MIN

TYP.

MAX

MIN

TYP.

MAX

A

A1

A2

B

5.08

0.200

0.38

3.56

0.38

0.015

0.140

0.015

4.06

0.51

0.160

0.020

B1

C

1.52

0.060

0.20

0.30

0.008

1.450

0.012

1.470

D

36.83

37.34

D2

E

33.02

15.24

1.300

0.600

E1

e1

eA

eB

L

13.59

13.84

0.535

0.545

2.54

0.100

0.590

14.99

15.24

3.18

1.78

0°

17.78

3.43

2.08

10°

0.600

0.125

0.070

0°

0.700

0.135

0.082

10°

S

α

N

28

C

B1

e1

B

eA

eB

D2

D

S

N

1

81/84

ST52T410/ST52T410/E420

Table 11.17 CERAMIC DIP28 WINDOWED PACKAGE MECHANICAL DATA

mm

inch.

DIM

MIN

TYP.

MAX

38.10

13.36

5.08

MIN

TYP.

MAX

1.469

0.526

0.177

A

B

13.05

3.90

3.18

0.50

0.514

0.153

0.125

0.020

C

D

E

1.78

0.070

e3

F

33.02

1.300

2.29

0.40

1.17

0.22

1.52

16.17

4d

2.79

0.55

1.42

0.31

2.49

18.32

15d

0.90

0.18

0.110

0.22

G

I

0.48

0.58

L

0.010

0.060

0.637

0.012

0.098

0.721

M

N

N1

P

15.40

15.80

5.71

7.36

0.606

0.275

0.616

0.225

0.285

Q

Diam.

6.86

C

b

P

E

N1

L

M

I

F

D

N

G

e3

A

28

Diam.

B

1

82/84

ST52T410/ST52T420/E420

ORDERING INFORMATION

Each device is available for production in user programmable version (OTP) as well as in factory pro-

grammed version (FASTROM). OTP devices are shipped to the customer with a default blank content

FFh, while FASTROM factory programmed parts contain the code sent by the customer. There is one

common EPROM version for debugging and prototyping, which features the maximum memory size and

peripherals of the family. Care must be taken only to use resources available on the target device.

Figure 11.16 Device Types Selection Guide

ST52 t nnn c m p y

TEMPERATURE RANGE:

6 = -40 to 85 °C

PACKAGES:

B = PDIP

M = PSO

D = CDIP

MEMORY SIZE:

0 = 1 Kb

1 = 2 Kb

2 = 4 Kb

PIN COUNT:

G = 28 pin

SUBFAMILY:

410, 420

MEMORY TYPE:

T = OTP

E = EPROM

FAMILY

PART NUMBER

ST52T410G0B6

ST52T410G0M6

ST52T410G1B6

ST52T410G1M6

ST52T410G2B6

ST52T410G2M6

ST52T420G0B6

ST52T420G0M6

ST52T420G1B6

ST52T420G1M6

ST52T420G2B6

ST52T420G2M6

ST52T420G2D6

TEMPERATURE RANGE

-40 to +85 °C

PACKAGE

PDIP

PSO

PDIP

PSO

PDIP

PSO

PDIP

PSO

PDIP

PSO

PDIP

PSO

CDIP

83/84

Full Product Information at http://www.st.com/five

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to

change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics

STMicroelectronics GROUP OF COMPANIES

Australia - Brazil - China - Canada - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta

- Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A.

http://www.st.com

84/84


型号：	ST52T410G0M6
厂家：	ST
描述：	8-BIT INTELLIGENT CONTROLLER UNIT ICU Three Timer/PWMs, ADC, WDG 8 - BIT智能控制单元ICU三个定时器/的PWM ， ADC ， WDG
文件：	总84页 (文件大小：904K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ST52T410G0M6 [STMICROELECTRONICS]

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