ST5451_技术文档

ST5451

ISDN HDLC AND GCI CONTROLLER

MONOLITHIC ISDN ORIENTED HDLC AND

GCI CONTROLLER.

GCI AND W/DSI COMPATIBLE.

µ

FULLY CONTROLLING GCI AND GCI-SCIT

M & C/I CHANNELS MANAGEMENT.

FULLY SUPPORTING LAPB AND LAPD PRO-

TOCOL ON B OR D CHANNEL.

EASILY INTERFACEABLE WITH ANY KIND

OF STANDARD NON MULTIPLEXED OR

MULTIPLEXEDBUS MICROPROCESSOR.

SO28

DMA ACCESS WITH MULTIPLEXED BUS µP

CAN HANDLE AND STORE AT THE SAME

TIME TWO FRAMES IN TRANSMISSION

(64bytes FIFO Tx) AND EIGHT FRAMES IN

RECEPTION (64bytes FIFO Rx)

ORDERING NUMBER: ST5451D

COMPATIBLE WITH ALL THE STMicroelec-

tronics ISDN PRODUCT FAMILY.

PIN CONNECTION (Top view)

GENERAL DESCRIPTION

ST5451 HDLC and GCI controller is a CMOS cir-

cuit fully developed by STMicroelectronics and

diffused in advanced 1.2 µm HCMOS3 technol-

ogy.

The device is intended to be used mainly in ISDN

applications, in Terminal (TE) and in Line Termi-

nations (LT).

ST5451 can handle HDLC packets either on

16Kbit/s D channel or 64 Kbit/s B channel; it can

work with a wide range of PCM signals go-

ing from GCI (General Circuit Interface) to DSI

(Digital System Interface) to any PCM-like

stream.

ST5451 is a complete GCI controller designed to

comply with the GCI and GCI-SCIT (Special Cir-

cuit Interface for Terminal) completely handling

Monitor (M) and Command/Indicate (C/I) chan-

nels.

ST5451 can be easily controlled by many differ-

ent kind of microprocessors or microcontrollers

having either non-multiplexed or multiplexed bus

structure.

ST5451 can be used in connection with ST5420/1

S Interface Devices (SID-µW and SID-GCI) and

ST5080 Programmable ISDN Combo (PIC) in

Terminals and with ST5410 U Interface Device

(UID) in Line Terminations.

1/34

March 2000

T

is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without

ST5451

BLOCK DIAGRAM

PIN DESCRIPTION

NAME

TYPE

FUNCTION

CS

1

I

Chip Select. A low level enables ST5451 for read/write operations.

Interrupt request is asserted by ST5451 when it request a service.

Open drain output.

INT

MULT

I/M

25

O

Multiplexed Bus. Indicates the P bus interface selected.

µ

2

I

MULT = 1: multiplexed bus and DMA available.

MULT = 0: address and data bus separated.

Intel/Motorola. When MULT = 1 this pin selects either Intel or

Motorola 6805 bus.

4

I

2/34

ST5451

DEMULTIPLEXED MICROPROCESSOR BUS INTERFACE (MULT = 0)

NAME

A0/A5

D0/D7

R/W

3-8

TYPE

FUNCTION

I

I/O

I

Address Bus. To transfer addresses from µP to ST5451.

Data Bus. To transfer data between P and ST5451.

µ

17-24

27

Read/Write. ”1” indicates a read operation; ”0” a write operation.

Enable. Read/write operations are synchronized with this signal; its

falling edge marks the end of an operation.

E

26

I

MULTIPLEXED MICROPROCESSOR BUS INTERFACE (MULT = 1 I/M = 1)

NAME

TYPE

FUNCTION

Address Data Bus. To transfer addresses and data between µP

and ST5451.

AD0/AD7

17-24

I/O

WR

RD

27

26

3

I

Write. This signal indicates a write operation.

Read. This signal indicates a read operation.

ALE

Falling edge latches the address from the external A/D Bus.

MULTIPLEXED MICROPROCESSOR BUS INTERFACE (MULT = 1; I/M = 0)

NAME

AD0/AD7

R/W

17-24

27

TYPE

FUNCTION

Address Data Bus. To transfer addresses and data between

and ST5451.

P

µ

I/O

I

Read/Write. ”1” Indicates a write operation; ”0” a write operation.

Data Strobe. Read/Write operations are synchronized with this

signal: its falling edge marks the end of an operation.

DS

26

Address Strobe. Falling edge latches the address from the external

A/D Bus.

AS

3

I

DMA (direct memory access): only when MULT = 1

NAME

TYPE

FUNCTION

DMA REQ X

DMA REQ R

7

5

O

Direct Memory Access Requests: these outputs are asserted by

the device to request an exchange of byte from the memory.

Direct Memory Access Acknowledge: these inputs are asserted by

the DMA controller to signal to the HDLC controller that a byte is

being transferred in response to a previous transfer request.

DMA ACK X

DMA ACK R

8

6

I

GCI INTERFACE

NAME

TYPE

FUNCTION

Data output for B and D channels. In GCI mode it outputs B1,

B2, M and C/I channels. In TE mode (GCI-SCIT) it can invert to

input data for M’ and C/I’ channels (See Table 2).

D_OUT

15

I/O

Data input for B and D channels. In GCI mode it inputs B1, B2, M

and C/I channels. In TE mode (GCI-SCIT) it can invert to output

data for M’ and C/I’ channels (See Table 2).

D_IN

C_LK

FS

12

11

13

I/O

Data Clock. It determines the data shift rate for GCI channels on

the module interface.

I

Frame synchronization. This signal is a 8 kHz signal for frame

synchronization. The front edge gives the time reference of the first

bit in the frame.

Data Enable. In TE mode, this pin is a normally low input pulsing

high to indicate the active bit times for D channel transmit at DOUT

pin. It is intended to be gated with CLK to control the shifting of

data from HDLC controller to S interface device.

DEN

10

I

3/34

ST5451

NON GCI INTERFACE

NAME

TYPE

FUNCTION

Data output. Digital output for serial data. Three modes:

- HDLC Protocol multiplexed link

- HDLC Protocol non multiplexed link

D_OUT

15

O

- Non HDLC protocol (transparent Mode).

D_IN

12

11

I

Data input. Digital input for serial data. Three modes (See D_OUT).

Data Clock. It determines the data shift rate. Two modes: Single or

double bit rate.

C_LK

Frame synchronization. Used in mode HDCL protocol multiplexed

link. Don’t care in other modes. The rising edge gives the time

reference of the first bit of the frame.

FS

13

10

I

DEN

Data Enable. When high, enable the data transfer. on D_OUT

OTHERS

NAME

V_DD

V_SS

28

14

16

9

TYPE

FUNCTION

Positive power supply = 5V +5%

Signal ground

I

R_ST

Reset

ST

Special Test. (Reserved) must be tied to V_SS

This value is set by a programmable register

- Address Field recognition

4 SAPI and/or 3 TEI may be recognized. Sev-

eral programmable registers indicate the recog-

nized address types.

2 - FUNCTIONS

2 - 1 - Basic HDLC Functions

2 - 1 - 1 - In Receive Direction:

- Channel selection

In GCI channel B1 or B2 or D may be selected.

B1 or B2 may be selected without M and C/I

channels

- Flag detection

A zero followed by six consecutiveones and an-

other zero is recognizedas a flag

2 - 1 - 2 - In Transmit Direction:

- Shift control in TE mode

D channeldata are signalled by DEN pin.

- Flag generation

A flag is generated at the beginning and at the

end of every frame.

- Zero delete

A zero, after five consecutive ones within an

HDLC frame, is deleted

- CRC checking

The CRC field is checked according to the gen-

erator polynomial

- Zero insert

A zero is inserted after five consecutive ones

within an HDLC frame

- CRC generation

The CRC field of the transmitted frame is gener-

ated according to the generatorpolynomial

X

¹⁶+ X¹²+ X⁵+ 1

X¹⁶+ X¹²+ X⁵+ 1

- Check for abort

Seven or more consecutiveones are interpreted

as an abort flag

- Abort sequencegeneration

An HDLC frame may be terminated with an

abort sequence under microprocessor control

- Check for idle

Fifteen or more consecutive ones are inter-

preted as ”idle”

- Interframetime fill

- Minimum lenght checking

Flags or idle (consecutive ones) may be trans-

mitted during the interframe time. A programma-

ble bit selects the mode.

HDLC frames with less than n bytes between

start and end flag are ignored: allowed val-

ues are 3 ≤ n ≤ 6.

4/34

ST5451

2 - 2 - FIFO Structure

used, structured in 2 blocks of 32 bytes. ST5451

is requested to transmit after 32 bytes have been

written into the FIFO.

2 - 2 - 1 - Receive FIFO Structure

In receive direction, a 64 byte FIFO memory is

used. It is divided in 8 blocks of 8 bytes automat-

ically chained.

If a transmission request does not include a mes-

sage end, the HDLC controller will request the

next data block by an interrupt.

In case of a frame length of 64 bytes or less, the

whole frame can be stored in the FIFO. After the

first 32 bytes have been received µP is inter-

rupted and may read the available data.

2 - 3 - Microprocessor Interface

Three types of microprocessor interfaces are

available (MULT and I/M control pins set the de-

sired interface).

In case of frames longer than 64 bytes, the µP is

interrupted to read out the FIFO by 32 byte block.

- Motorola non multiplexed families.

- Motorola multiplexed family (6805 type)

- Intel family.

In case of several short frames, up to eight may be

stored inside the FIFO. After an interrupt, one frame

is available for the µP. The eventual other seven

frames arequeuedand transferredone by one.

You can connect ST5451 to a Direct Memory Ac-

cess Controller as MC68440 or MC6450 (dual or

quad channels).

2 - 2 - 2 - TransmitFIFO Structure

In transmit direction, a 64 byte FIFO memory is

A programmable register indicates DMA Interface

enabling.

TABLE 1

- ST5451 Internal Registers

Address Hexa

Read

Write

00

1F

20

21

22

23

24

25

26

27

28

29

2A

2B

2C

2D

2E

2F

30

31

32

33

34

3E

Receive FIFO

Transmit FIFO

-

ISTA0

ISTA1

ISTA2

STAR

MODE

RFBC

CA

ISTA0

ISTA1

ISTA2

CMDR

MODE

TSR

CA

CB

CC

CD

CE

CF

CIR1

CIR2

MONR1

-

CIX1

CIX2

MONX1/0

MONX1/1

MONX2/0

MONX2/1

MASK0

MASK1

MASK2

CCR

MONR2

-

CCR

5/34

ST5451

TABLE 2 - CHANNEL ASSIGNMENT SELECT

6/34

ST5451

entered into the XFIFO.

Transmit Data Underrun

3 - REGISTER DESCRIPTION

XDU

For all the register pictures MSB is on the left and

LSB on the right

Ifnot otherwisestatedbitareconsideredactiveat1.

A transmitted frame was terminated

with an abort sequence because no

data were available for transmission in

XFIFO and no XME command was is-

sued. It is not possible to transmit

frame when that interrupt remains un-

acknowledgedand XRES has not been

set.

FIFOS

RFIFO (read), XFIFO (write).

EXI2

EXI1

ExtendedInterrupt 2

The interrupt reason is indicated in reg-

ister ISTA2

The address range of the two FIFOs are identical.

All the 32 addresses give access to the ”current”

FIFO location.

Extented Interrupt1

The interrupt reason is indicated in reg-

ister ISTA1.

When the closing Flag of a receive frame is de-

tected, a status byte is available in the RFIFO.

This byte has the following format:

ISTA1

Interrupt Status Register 1

After RESET 01H

(GCI mode only)

RBC RDO CRC RAB

0

RBC

RDO

Receive Byte Count.

The length of the received frame is n

time 8 bits (n=3,4,5,...)

0

CIC1 EOM1 XAB1 RMR1 RAB1 XMR1

Receive Data Overflow

A part of the frame has not been lost

because the receiveFIFO was full

CIC1

Comman/IndicateChange

A change in the value of CIR1 is de-

tected

CRC

RAB

CRC Check

ThereceivedCRCbyteswere notcorrect

EOM1

XAB1

End of Message 1 (monitor channel)

MON1 has received an end of mes-

sage.

Receive Abort

The received frame was not aborted

Monitor Transmit ABORT

The received byte has not been de-

tected in two successiveframes.

MON1 has sent an ABORT (A bit) to

the remote transmitter.

A status byte equal to D0H indicates a correctly

received frame

RMR1

RAB1

XMR1

Receive Monitor Register 1 ready

A byte has been received in register

MONR1.

ISTA0

Interrupt Status Register 0

After RESET 10H

RME RPF RFO XPR XDU EXI2 EXI1

RME

0

Receive Abort

MON1 received an ABORT from the re-

mote receiver.

Receive Message End

One complete frame of length less than

or equal to 32 bytes, or the last part of

a frame of length greater than 32 bytes

is stored in the RFIFO.

Transmit Monitor Register 1 ready

A byte can be stored in register

MONX1

RPF

RFO

Receive Pool Full

32 bytes of a frame are in RFIFO. The

frame is not yet completely received.

ISTA2

Interrupt Status Register 2

After RESET 01H

(GCI and TE mode only)

Receive Frame Overflow

A complete frame was lost because no

storage space was available in the

RFIFO.

0

CIC2 EOM2 XAB2 RMR2 RAB2 XMR2

CIC2

Command/IndicateChange

A change in the value of CIR2 is de-

tected.

XPR

Transmit Pool Ready

One data block (32 bytes max) may be

7/34

ST5451

EOM2

CMDR

CommandRegister

After Reset 00

End of Message2 (monitor channel)

MON2 has received an end of mes-

sage.

XHF XME RMC RMD RHR XRES M2RES M1RES

XAB2

Monitor Transmit ABORT

XHF

XME

HDLC frame transmission can start.

The received byte has not been de-

tected in two successive frames.

MON2 has sent an ABORT (A bit) to

the remote transmitter.

Transmit Message End

The last part of the frame was entered

in XFIFOand can be sent.

RMR2

RAB2

XMR2

Receive Monitor Register 2 ready

A byte has been received in register

MONR2.

RMC

RMD

Receive Message Complete

Reaction to RPF or RME interrupt. The

received frame (or one pool of data)

has been read and the corresponding

RFIFO is free.

Receive ABORT

MON2 received an ABORT from the re-

mote receiver.

Receive Message Delete

Reaction to RPF or RME interrupt. The

entire frame will be ignored. The part of

frame already stored is deleted.

Transmit Monitor Register 2 ready

A byte can be stored in register

MONX2.

RHR

Reset HDLC receiver

XRES

Reset HDLC transmitter

XFIFO is cleared and the transmitted

frame (if any) is aborted.

MASK0, MASK1, MASK2

After Reset FF; the three mask registers MASK0,

MASK1, MASK2 are associated respectively to

the three interrupt registers ISTA0, ISTA1,and

ISTA2.

Each interrupt source in ISTA registers can be se-

lectively masked by setting to ”1” the correspond-

ing bit in MASK1. Interrupt sources (masked or

not) are indicated when ISTA is read by the mi-

croprocessor. When an interrupt source is not

masked, INT goes low.

M2RES Monitor 2 Reset

Reset MONITOR and C/I channels (TX

and RX).

M1RES Monitor 1 Reset

Reset MONITOR and C/I channels (TX

and RX).

*

For the four first bits (XHF, XME, RMC,

RMD), the reset is done by the device;

the other bits level sensitive

STAR

Status Register

After Reset 48H

MODE

HDLC Mode Register

After Reset 00

XDOV XFW IDLE RLA DCIO

0

XDOV

Transmit Data Overflow

More than 32 bytes have been written

into the XFIFO.

DMA FL1 FL0

ITF RAC CAC NHF FLA

DMA

DMA Interfaceactivation

Frame Length

XFW

IDLE

XFIFO Write enable

Data can be entered into the XFIFO.

FL1/0

Minimum frame length accepted

IDLE State

FL1

FL0

15 or more consecutive ones have

been detected on the input data line.

3 bytes

4 bytes

5 bytes

6 bytes

0

1

0

1

0

1

RLA

Receive Line Active

Frames or interframe flags are being

received

ITF

InterframeTime Fill

ITF= 1 : Flags are transmitted

ITF= 0 : IDLE is transmitted

DCIO

D and C/I Channels are occupied

RAC

RAC= 1 : Activate RX

RAC= 0 : deactivateRX

8/34

ST5451

MONX1 Monitor Transmit Register 1

After reset FFH

CAC

Channel Activation

CAC = 1 : Activate RX and TX

CAC = 0 : deactivate RX and TX

(GCI only)

M1

M2

M3

M4

M5

M6

M7

M8

NHF

FLA

HDLC Function Select

NHF = 1 : disable HDLC function

The value written in MONX1 is trans-

mitted in the outgoing Monitor channel

according to GCI transfer protocol.

XMR1 interrupt indicates when MONX1

is again available.

Flag

FLA = 1 : transmit shared flags

FLA = 0 : transmit two flags between

consecutive frames.

RFBC

Receive Frame Byte Counter

After reset 00

MONR1

Monitor Receive Register 1

After reset FFH

(GCI only)

RDC7 RDC6 RDC5 RDC4 RDC3 RDC2 RDC1 RDC0

M1

M2

M3

M4

M5

M6

M7

M8

RDC 0/7 Receive Data Count

The value read from MONR1 gives the

value of the byte received in the moni-

tor channel according to GCI transfer

protocol. RMR1 interrupt indicates

when a new byte is available in

MONR1 register.

Total number of bytes of received

frame without CRC.

RDC 0/4 Indicate the number of bytes in the cur-

rent block available in RFIFO.

RDC 5/7 Indicate the number of 32 bytes blocks

received. If the frame exceeds 223

bytes, RDC 5/7 hold the value ”111”,

only RDC 4/0 continue to count modulo

32.

CIX2

Command/IndicateTransmit Register 2

After Reset FFH

(GCI and TE mode only)

See Table 3.

The contents of the register are valid after an

RME interrupt. The µP must read N+1 bytes to

transfer the number of bytes received and the

status byte into the memory.

1

P1

P2

P3

P4

P5

P6

P1/P6

Code transmitted permanently in the

2nd GCI C/I channel.

CIX1

Command/Indicate TransmitRegister 1

CIR2

Command/IndicateReceive Register 2

After reset FFH

(GCI and TE mode selected only)

After reset FFH

(GCI only)

1

C1

C2

C3

C4

1

P1

P2

P3

P4

P5

P6

C1, C2, C3, C4:

P1/P6

The contents of the 2nd C/I channel;

they are the different requests received

from TE peripheral devices to µP.

Six peripherals can make a simultane-

ous request.

Code to be transmitted permanently

in the outgoing GCI C/I channel.

CIR1

Command/Indicate Receive Register 1

After reset FFH

(GCI only)

MONX2

Monitor Transmit Register 2

After reset FFH

(GCI and TE mode only)

1

C1

C2

C3

C4

The value written in MONX2 is trans-

mitted in the 2nd GCI M channel to a

peripheral (if PI= 1; register CF).

C1, C2, C3, C4:

Incoming GCI C/I channel.

9/34

ST5451

TABLE 3

N (number of bytes in the

frame received without CRC)

Counter

n (number of 32 bytes blocks

received )

7 6 5

n

4 3 2 1 0

m

N

1 Min

2

n

0

1

2

6

7

000

001

010

110

111

00001

00010

00011

11110

11111

00000

00001

11110

11111

00000

11110

11111

00000

00001

-

3

30

31

32

33

62

63

64

222

223

224

256

257

-

MONR2

Monitor Receive Register 2

After reset FFH

CA

ConfigurationnRegister A

After reset 00

(GCI and TE mode only)

CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0

The value read from MONR2 gives the

value of the byte received from M

channel in 2nd GCI channel.

CA0

CA1

CA2

CA3

CA4

CA5

CA6

CA7

SAPI 0 is recognized

SAPI 63

CA0 = 1

CA1 = 1

CA2 = 1

CA3 = 1

CA4 = 1

CA5 = 1

CA6 = 1

CA7 = 1

SAPI x

TSR

Time Slot Register

After reset 00

SAPI y

TEI 127

TEI z

TSR7 TSR6 TSR5 TSR4 TSR3 TSR2 TSR1 TSR0

TEI t

In GCI mode (MDS1= 1 in CF Register)

a) CCS=1 in CF Reg. (64 Kbit/s)

Then: TSR2 indicates B1 or B2

TSR4/7 indicate position of

GCI channel

Address filter active

CB

CC

Configuration register B

After reset 00

Content of CB indicate SAPI x value

b) CCS=0 in CF Reg. (16 Kbit/s)

Then: TSR4/7 indicate position of

GCI and its D channel

High Order 6 Bits

SAPI

0

In Multiplexed Mode

(MDS1=0 in CF Register)

a) CCS=1 in CF Reg. (64 Kbit/s)

Then: TSR2/7 indicate channel

position in the 64 time slots

multiplex

Configuration Register C

After reset 00

Content of CC indicate SAPI y value

High Order 6 Bits

b) CCS=0 in CF Reg. (16 Kbit/s)

Then: TSR0/7 indicate channel

position in the 256 time slots

multiplex.

SAPI

0

10/34

ST5451

SC = 1 means ”an 8Kbit/s or 56Kbit/s

CD

CE

Configuration Register D

After reset 00

Content of CD indicate TEI z value.

subchannelinside a 16Kbit/sor

64kbit/sis used”(seeMAS/SSC)

7 High Order Bits

PI

Peripheral Interface (only if TE=1)

PI = 1: CIX2, CIR2, MONX2, MONR2,

active

TEI

0

Configuration Register E

After reset 00

Content of CE indicate TEI t value.

VZDOUT When level 1 device is inactive (i.e.

CIR1 = DI = 1111) and GCI has to be

waken up (i.e. TIM = 0000 in CIX1),

DOUT is set to zero requiring FS

and CLK if VZ DOUT=1.

7 High Order Bits

TEI

MDS1

Mode Bit 1

MDS1 = 1:GCI mode

MDS1 = 0: Multiplexed mode

CF

Configuration Register F

After 00

MDS0

Mode Bit 0

MDS0 = 1: Multiplexer and Demulti-

plexer are active.

TE MAS/SSC CCS CMS/SC PI VZDOUT MDS1 MDS0

MDS=0 No multiplexer.

TE

TE mode

TE = 1 : the frame is constitued by

three GCI channels (GCI-SCIT)

CCR

Configuration Register 00

After reset 00

TLP ADDR AD3 AD2 AD1 AD0 CRS TRI

MAS/SSC If CCS = 0, TE = 1, MDS0 and MDS1 = 1

(i.e. GCI mode, TE mode, 16 Kbit/s)

MAS/SSc is MAS and:

TLP

Test Loop

TLP = 1: The transmitter is internally

connected to the receiver; the transmit

output is not activated.The digital inter-

face must be activated to provide the

bit clock and frame Synchro.

MAS = 0 means ”Slave device”

MAS = 1 means ”Master device”

If SC = 1 (i.e. a sub-channel is se-

lected) MAS/SSC is SSC; if 16Kb is se-

lected SSC chooses between first on

second bit of the stream while, if 64Kb

is selected SSC chooses between first

or last seven bits of the stream (see

TABLE 2 and CMS/SC)

ADDR

Address Recognized

If TE = 1 and PI = 1

ADDR = 1: The first byte received in

MONR2 is compared with AD0/3. If

equal the message is accepted, other-

wise is ignored.

ADDR = 0: The message is always ac-

cepted.

CCS

Channel Capacity Selection

CCS = 1: 64 Kb/s

CCS = 0: 16 Kb/s.

AD0/3

AD0/2

CRS

When PI = 1, is the component ad-

dress.

CMS/SC If CCS = 0, TE = 1, MDS0 and MDS1 = 1

(i.e. GCI mode, TE mode, 16Kbit/s)

CMS/SC is CMS (Contention mode se-

lection) and:

Address bit used to access D and C/I

channels (TE = CMS =1, CCS = 0).

CMS = 1 means ”D and C/I channel

access procedure active”

CMS = 0 means ”D and C/Z channel

Clock Rate Selection

CRS = 1: Clock frequency is twice the

data rate (GCI).

CRS = 0: Clock frequency and data

rate are identical.

access procedure active”

If CCS = 1 and TE = 1 CMS/SC is SC

(Subchannel)and:

SC = 0 means ”16Kbit/sor 64Kbit/sis

TRI

Tristate

TRI = 1: DOUT in tristate

TRI = 0: DOUT in open drain.

used”

11/34

ST5451

leted and the remainder frame is ignored by the

HDLC Controller.

The last block of the frame generates the RME in-

terrupt.

RFBC register bits 0 to 4 indicate the number of

bytes currently stored in the RFIFO. Bits 5 to 7 in-

dicate the total number of 32 byte blocks already

received. Bits 5 to 7 do not overflow. When the

counter status 7 has been reached, it indicates a

frame length greater than 223 bytes (see Table

3).

RFBC register is valid only after the RME inter-

rupt and remains valid until RMC acknow-

ledgement by µP.

At each read access by the µP, RFBC 5/7 bits re-

main unchanged, RFBC 0/4 bits are decreased to

reach value 0 when the whole block is read.

Interrupts are queued inside the device. They are

sent one by one to the microprocessor after each

acknowledgement RMC. If a frame is lost be-

cause the RFIFO was full, a RFO interrupt is gen-

erated.

4 - WORKING PROCEDURES

4 - 1 - RECEIVE FRAME

Recognized frame (by means of SAPI and/or TEI

identification), having a minimum length is stored

in the RFIFO with all bytes between the opening

flag and CRC field.

When the frame is less than or equal to 32 bytes,

is transferred in one block, and just after the re-

ceiving completion interrupt (RME), a status byte

is appended at the end. The frame and its status

byte remain stored until µP acknowledgement

(RMC).

When the frame is longer than 32 bytes, blocks of

32 bytes plus one remainder block of lenght 1 to

32 are transferred to the microprocessor. The re-

ceiving 32 byte block generates a RPF interrupt

and the data in RFIFO remains valid until µP ac-

knowledgement(RMC).

The µP can ignore a received frame by meaning

RMD (Receive Memory Delete), reaction to RPF

or RME. The part of frame already stored is de-

Figure 1:

Receiving of an HDCL frame

12/34

ST5451

transmitted, the CRC field and the closing flag are

added. The HDLC controller then generates a

new XPR interrupt.

If the XFIFO becomes empty while XME com-

mand has not been set, an abort sequence is

generated, followed by interframe time fill and

XDU interrupt is generated.

4- 2 - TRANSMIT FRAME

After polling bit XFW or after a XPR interrupt, up

to 32 bytes may be stored in XFIFO. Transmis-

sion begins after that XHF command is issued by

µP. ST5451 will request another data block by an

XPR interrupt if the XFIFO contains less than 32

bytes.

A frame may be aborted by XRES command as

well.

When XME is set, all remaining XFIFO bytes are

Figure 2:

Transmission of an HDCL frame

13/34

ST5451

that one device in the terminal wants to send a

message. Up to six peripherals may generate

such an interruptto the microprocessor.

ST5451 writes at every frame the six bits of C/I’

channel coming from peripheralsin registerCIR’.

This value is compared with the previous one and

if a new one appears during two consecutive

frames, is loaded in register CIR2 and CIC2 inter-

rupt (ISTA2 register) is generated.

4 - 3 - COMMAND/INDICATE PROCEDURE

The exchange of information in the C/I channel

runs as follows:

The two circuits (i.e. ST5421 and ST5451) con-

nected on the GCI interface send one each other

a permanentfour bit command code in C/I field.

RECEIVE C/I

The ST5451 stores on every frame the four bits of

C/I channel coming from level 1 circuit in a first

register CIR. This value is compared with the pre-

vious one. If a one new appears during two con-

secutive frames, this new value is loaded in regis-

ter CIR1 and a CIC1 interrupt is generated.

µP may send a message on M’ channel (DIN be-

comes an output) to allow the peripheral device to

transmit.

MESSAGETRANSMISSION ON M’ CHANNEL

ST5451 sets interrupt XMR2 (ISTA2 register) if

register MONX2/0 is available. Writing MONX2/0

generates a message transmission. When the

TRANSMIT C/I

The transmit register CIX1 can be written at any

time by the µP. Its content is continuously sent in

the C/I channel.

Note: The TIM command (0000) forces a low

level on DOUT, if CIR1 = DI (1111) when VZ

DOUT = 1 to require FS and CLK.

last byte is stored in

register MONX2/1,

ST5451sends End of Message to remote periph-

eral.

If an ABORT is received, interrupt RAB2 (ISTA2

register) is issued. Then microprocessor may

send its message again.

MESSAGERECEPTION ON M’ CHANNEL

4 - 4 - MONITOR CHANNEL

Interrupt bit RMR2 (ISTA2 register) is generated

when a new byte is available in MONR2 register.

ST5451 sets interrupt bit XAB2 (ISTA2 register) if

it does not read twice the same byte; in this case,

it sends an ABORT to remote peripheral.

The controller generates interrupt bit EOM2

(ISTA2 register) when End Of Message is re-

ceived.

The GCI Monitor channel procedure allows full

duplex data transmission with acknowledgement

using A bit.

MESSAGE RECEIVING

An interrupt (bit RMR1 in ISTA1 register) is gen-

erated when a new byte is available in register

MONR1.

ST5451 generates an interrupt bit (XAB1 in

ISTA1) if it does not read twice the same bytes

meanwhile sending an ABORT to the remote

transmitter.

4 - 6 - ACCESS PROCEDURE TO D AND C/I

CHANNELS (GCI and TE mode selected only)

Up to eight HDLC controllers may be connected

to D channel and C/I channel. A contention reso-

lution mechanism is used if bit CMS (Contention

Mode Selection) is set.

The mechanism allows to give an access without

losing data.

It performs an interrupt (EOM in ISTA1) also

when it has received an End Of Message. Ac-

knowledgementto remote transmitter is sent if:

- the byte was received twice with the same value

- the microprocessor reads the previous byte

stored in register MONR1.

An access request may be generated, if CIX1

(Command/Indicate Register 1) contains a differ-

ent code from DI (1111). During the procedure, M

channel (with A and E bits) may be used. On in-

put DIN, the GCI controller checks the CMS4 bit

(CMS channel - Third GCI channel)(see Fig. 4).

CMS4 indicates the status of C/I and D channels

CMS4= 1 ”channels free”; CMS4= 0 channels oc-

cupied.

If the channels are free, the HDLC controller

starts transmitting its individual address AD2 on

CMS1, AD1 on CMS2, AD0 on CMS3. If an erro-

neous address is detected, the procedure is ter-

minated immediately. If the complete address can

be read without error, the D and C/I channels are

occupied: the ST5451 transmits CMS4 = 0: The

HDLC controller which has the lowest address

has priority over the others.

This procedure performs flow control between S

interface device and µP.

MESSAGE TRANSMISSION

ST5451generates an interrupt (XMR1 in ISTA1)

when register MONX1 is available.

Writing register MONX1/0 generates a message

transmission. When the last byte is stored in the

register MONX1/1, ST5451 sends the End of

Message to remote receiver. If an Abort is re-

ceived, one interrupt (RAB1) is generated.

4 - 5 - M’ and C/I’ CHANNELS

The procedure allows a full duplex data transmis-

sion between microprocessor and the peripheral

devices connected on C/I’ local and M’ channel

throughGCI-SCIT channel 1.

Receive Interrupt on C/I’ (DOUT is an input).

A new value on C/I’ indicates to ST5451 master

The access request is withdrawn if the HDLC

controller transmits code DI = 1111. the CMS4 bit

(CMS field) is set.

14/34

ST5451

Figure 3: GCI-SCIT Frame Timing

Figure 4:

GCI-SCIT Channels Timing

15/34

ST5451

by the µP except the FIFOS.

4 - 7 - DMA ACCESS

FRAME RECEPTION:

The HDLC controller has a DMA interface which

is activated by DMA bit in MODE register.The

DMA interface is available only when multiplexed

bus is selected.

ST 5451 asserts DMA REQR or DMA REQX to

request an exchangeof bytes between the FIFOS

and the external memory.

The external DMA controller asserts DMA ACKR

or DMA ACKX to access the FIFOS.

These signals are equivalent to E/DS/RD func-

tions.

When one block has been stored in RFIFO, DMA

REQ R pin goes low and RPF (or RME) interrupts

the µP. The DMA controller reads the RFIFO. Af-

ter the RME interrupt, the frame length will be

available in RFBC register. The block is acknow-

ledged by RMC command.

FRAME TRANSMISSION:

When a 32 byte block is free in XFIFO, DMA re-

quest goes low and XPR interrupts the µP. The

DMA controller can write data in the XFIFO. At

the end of the frame, the µP send XME to HDLC

controller; CRC and closing flag will be sent by

the HDLC controller.

During DMA access, CS/CE pin must be inactive;

AS and E/DS/RD signals can be present.

Outside DMA Access, all registers are accessible

Figure 5: D and C/I channelsAccess Procedure

16/34

ST5451

processor write a byte into the block and erase

this bit into ISTA0; if another block is free, XPR

get high again immediately.

The processing order of the microprocessor is in

non DMA Mode:

4 - 8 - INTERRUPT PROCEDURE

4 - 8 - 1 - HDLCCHANNELS

4 - 8 - 1 - 1 - RECEIVEDIRECTION

RRE and RPF interrupts

- Put Mask0 on ISTA0 (if upper level Mask Off)

- Write at least one byte into FIFOX

- Write ISTA0 to erase XPR

- Write XHF to ”1” for launching the transmit

operation of block (a block is not necessarily

32 bytes)

RPF bit (register ISTA0) set high to indicate the

HDLC controller has received a block of 32 bytes

which is not a complete message.

This bit remains high until it is erased by the mi-

croprocessor.

or write XME to ”1” for launching the trans-

mit of a short frame or of the last part of a

frame

As for each bit of ISTA0 register, except the ex-

tension bits of ISTA1 and ISTA2 (EXI1, EXI2), the

way to erase RPF is to write a ”0” at its location

and to write a ”1” at the location of the others (for

example 7FH into ISTA0 to erase RME). The

processing order is:

- Removemasks

In DMA Mode two general cases are possible:

1) The external DMA controller works by ”pages”

less or equal to 32 bytes. The ”process” of the

DMAC is a short frame transmission and the

processor must give an XME at the end of the

DMAC process (refer to figure 2).

- put Mask0 on ISTA0 (if Mask Off)

- (Read FIFOR) X 32

- Write ISTA0 to erase RPF (BFH)

- Write RMC to ”1” for asking for another block

of the frame

2) The DMA controller works by ”pages” of more

than 32 bytes. It’s process is the transfer of the

whole frame.

(NB: RMC, RMD are automatically erased

by the controller)

- Remove Mask0

The circuit doesn’t need an XHF at the end of an

intermediate 32 byte block; since it has reached

32 bytes written into the current fifo, it begins the

transfer and toggles on the second fifo as soon as

the first is full. (At this moment an XME is possi-

ble if the 32^ndbyte was the end of the frame -

case 1) and then, a 33^rdwrite operation into the

fifo generates an internal XHF and the frame fol-

lowing blocks are expected.

RME bit (register ISTA0) set high to indicate the

HDLC controller has received a short frame or the

last block of a large frame. The message is now

complete, the bit remains high until it is erased by

the microprocessor. The processing order is:

- put Mask0 on ISTA0 (if upper level Mask Off)

- Read RFBC with a mask on the 3 most sig-

nificant bits, to know the number ”N” of

transfers to do

- In the two cases the flow control is done be-

tween DMAC and ST5451 by the way of

REQX and ACKX signals

- (Read FIFOR) x N for data

- Read FIFOR for status on the frame

- Write ISTA0 to erase RME (7FH)

- Write RMC or RMD to ”1” for asking for an-

other frame.

The processingorder is:

- Put Mask0

- Give order to DMAC to begin transfer

- Wait for DMAC end of process

- Write ISTA to erase on XPR

- Write XME to signal the end of the frame to

the ST5451 (otherwise the ST5451 will put

”underrun” interrupt, as soon as its two

blocks are free).

RF0 interrupts

RF0 is a bit of the interrupt register ISTA0 set

high to indicate an overflow of the receive FIFO

has been detected, either because more than 8

frames cannot be stored or because more than

64 bytes can’t be stored. This information is also

stored into the status of the concerned frame

(RDO).

The processing order of the microprocessor is:

- Looking for RPF and RME bits and pop - up

the frames. Then look for the status and

throw down the frame concerned. In general

case, only one frame is lost.

XDU Interrupt

XDU is a bit of the interrupt register ISTA0 com-

ing high to indicate HDLC controller has detected

an underrun (a frame is being transmitted and no

more bytes are available into the FIFO).

The HDLC controller finish the frame by transmit-

ting an ”Abort” and no more data can be transmit-

ted even in NHF mode. To be sure XDU is seen

by the MIcroprocessor, XDU interrupt bit must be

erased in ISTA0 in addition of XRES security pro-

cedure

4 - 8 - 1 - 2 - TRANSMIT DIRECTION

XPR Interrupt

XPR is a bit of the interrupt register ISTA0 coming

high to indicate HDLC controller has a free block

of 32 bytes. This bit remains high until the micro-

The transmit control is frozen and the only way to

reinitialize a transmit session is to write an XRES,

after erasing XDU.

17/34

ST5451

4 - 8 - 2 - M CHANNELS INTERRUPTS EOM,

RMR, XMR, RAB

Receive Direction

RMR 1/2 is a bit of interrupt register ISTA 1/2

coming high to indicate the M (or M’) channel

controller has received a valid byte on receiving

channel (two identical consecutivebytes).

4 - 8 - 3 - CI CHANNEL INTERRUPTS

CIC 1/2 is a bit of ISTA 1/2 interrupt register com-

ing high to indicate a valid byte has been de-

tected by the command indicate receive control-

ler, and readable into CIR 1/2 register. The

processing order is:

1. Erasing CIC bit

2. Reading CIR register.

The microprocessor processing order is;

If this order is inverted, a next byte may be un-

seen by the microprocessor. It is recommended

to work with ”Ping Pong” protocol on CI channels,

as non flow control is done.

1. Erasing RMR 1/2 interrupt into ISTA 1/2

2. Read MONR 1/2 register.

This order can’t be inverted because, as long as

MONR isn’t read, the receive state machine is

locked in wait state, a new byte can’t be acknow-

ledged and so, a new interrupt can’t be done.

More, if MONR is read first, the receive state ma-

chine is ready for receiving a new byte and create

another interrupt. So, if the interrupt bit corre-

sponding to the previous frame isn’t erased be-

fore a new byte arrives, this byte won’t be seen

(the microprocessor won’t be informed) and the

controllerwill be locked waiting for MONR read.

XAB 1/2 is a bit of the interrupt register coming

high to indicate the receive controller has de-

tected an abort (two conscutive bytes not identi-

cal) as long as this interrupt isn’t erased, the re-

ceiver is locked in wait state.

4 - 9 - SOFTWARE RESET PROCEDURES

4 - 9 - 1 - XRES (Transmit Direction)

XRES is a level sensitive command of CMDR

which initialize the transmit process.

- XPR interrupt bit is erased

- XDU interrupt bit is not erased (security pro-

cedure)

- All data in FIFOs are lost

- After an XRES, the microprocessor must wait

for an XPR before writing new data.

The processingorder is:

- Writing a ”1” into XRES (CMDR)

- Writing a ”0” into XRES (CMDR)

- Read ISTA0 waiting XPR or enable XPR in-

terrupt

EOM 1/2 is a bit of the interrupt register coming

high to indicate the receive controller has de-

tected an end of message. As long as the inter-

rupt isn’t erased, the receiver is locked in wait

state.

4 - 9 - 2 - RHR (Receive Direction)

RHR is a level sensitive command of CMDR,

which reinitialize the receive process.

- RME, RPF bits are erased

Transmit Direction

XMR 1/2 is a bit of the interrupt register coming

high to indicate a byte can be written into MONX.

The processing order is:

1. Erasing XMR bit

2. Writing a new byte into MONX.

- RFO bit is erased

- All frames in FIFO R are lost

- If RHR is released (got down) at the time a

frame is on line, the HDLC controller waits

for a flag.

If this order is inverted, the new byte will be trans-

mitted and a new XMR may be erased before be-

ing seen by the microprocessor.

RAB 1/2 is a bit of the interrupt register coming

high to indicate the remote receiver has reported

an abort detection. The processing order is:

4 - 9 - 3 - M1RES, M2RES M/CI channels

MRES is a level sensitive command of CMDR

which initialize the M/CI channel protocole in both

directions.

XMR, RAB, RMR, CIC, XAB, EOM bits are

erased by MRES.

1. Erasing RAB bit

2. Erasing XMR bit

After a clock programming (bit CRS), it’s neces-

sary to put MRES bit to initialize properly the M

protocol.

3. Writing a new byte into MONX.

If a write operation of the new byte is done before

the RAB erasing, the byte will be lost and the

transmitter will stay waiting for it.

18/34

ST5451

nel LAPB packet data are processedby the same

µP. A DMA controller performs device to memory

transfers. It is a typical work station application.

Fig. 9 and 10 illustrate 2 typical applications in

NT2 or exchange.

An NT2 or LT in fig.9 with eight D channelcontrol-

lers connected to the GCI interface handle sub-

scriber 0 to 7. Any GCI compatible transceiver (S

or U) may be used to do the subscriber line inter-

face; a GCI compatible exchange circuit may im-

plement the system interface. This is one decen-

tralizedapplication.

Fig. 10 illustrates a centralized application. Using

a switching net work, it is possible to connect:

up to thirty two 64 Kbit/s channels on a 2 Mb/s

PCM highway to 32 B channel controllers

up to sixty four 64 Kbit/s channels on a 4 Mb/s

PCM highway to 64 B channel controllers

up to two hundred fifty six D channelson a 4 Mb/s

highway to 256 D channel controllers.

TYPICAL APPLICATIONS

ST5451 HDLC controller may be used in TE,

NT2, NT12 or LT.

Figures 6 to 8 illustrate three typical applications

in multifunctionalTE.

The D channel containing only signalling is proc-

essed by the LAPD controller and routed via a

parallel µP interface to the terminal processor.

The support of the LAPD protocol which is imple-

mented by the HDLC controller device allows in

cost senstive applications the use of a low cost

microprocessor. See fig. 6.

Fig. 7 illustrates a configuration in which the D

channel containing signalling data (SAPI s) as

well as packet switched data (SAPI p) is proc-

essed by two controllers and two independentmi-

croprocessors.

Fig. 8 illustrates a configuration in which one mi-

croprocessor is connected to two controllers via a

DMA controller.

D channelwith LAPD signalling data and B chan-

Figure 6: Low cost GCI terminal application

19/34

ST5451

Figure 7: LAPB and LAPD protocol on the same D channel handlended with 2 differentµPs

S - INT

Figure 8: LAPB and LAPD protocol handling an B and D channel

S - INT

20/34

ST5451

FIgure 9: Decentralized D channel handling in NT2 or LT

Figure 10:

CentralizedD channel handling in NT2 or LT

21/34

ST5451

Figure 11: HDCLFrame Transmission Procedure

22/34

ST5451

Figure 12: HDCLFrame Transmission Procedure in D Channel

23/34

ST5451

Figure 13: S Activation and Deactivation procedure

24/34

ST5451

ELECTRICAL CHARACTERISTICS

°

±

(T from 0 to 70 C, V_DD= 5 0.25V).

Symbol

Parameter

Supply Current

Test Condition

Min.

Typ.

Max.

Unit

I_S

CLK Freq. = 4MHz

CLK Freq. = 2MHz

NO CLK Freq.

–

4

2

20

–

4

300

mA

µA

STATIC CHARACTERISTICS - GCI INTERFACE(T from 0 to 70°C, V_DD= 5 ± 0.25V).

Symbol

VIH

Parameter

Condition

Min.

2.4

Max.

Unit

V

High Level Input Voltage

Low Level Input Voltage

Maximum leakage current : ± 10 µA

VDD+0,4

0,8

VIL

VSS-0,4

2,4

V

VOH

VOL

High Level Output Voltage IOH = -0,4 µA

Low Level Output Voltage IOL = 2mA

Low Level Output Voltage IOL = 7mA

V

0,45

V

D_OUT. D_in. INT

C

Input/Output Capacity

Load Capacity DIN/DOUT

Load Capacity INT

10

pF

C_OUT

150

100

Load Capacity AD0/7

DYNAMIC ELECTRICAL CHARACTERISTICS - GCI Interface

Symbol

FSync

F_CLK

t_WCH

t_WCL

t_RC

Parameter

Min.

Typ.

Max.

Unit

KHz

ns

8 KHz

8

64 x n x FSync 1

n

8

≤

512

80

4096

≤

Period of CLK High

Period of CLK Low

Rise Time of CLK

Full Time of CLK

80

ns

10

ns

t_FC

ns

t_HCF

Hold Time: CLK - FS

0

ns

t_SFC

Set-up Time: FS - CLK

30

ns

t_DCD

t_DCZ

Delay Time: CLK High to data valid. out: 150 pF

Delay Time: to Data Disabled

80

ns

0

ns

t_DFD

Delay Time: FSync. High to data valid. count: 150 pF. Applies

only if Sync rises later than CLK raising edge.

ns

t_SDC

t_HDC

Set-up Time: Data valid to CLK receive edge.

Hold Time: CLK low to data invalid.

30

ns

25/34

ST5451

DYNAMIC ELECTRICAL CHARACTERISTICS - Double Clock Interface

Symbol

FSync

F_CLK

t_WCH

t_WCL

t_RC

Parameter

64

≤

Min.

Typ.

Max.

Unit

KHz

ns

8 KHz

8

16 x n x FSync 1

n

128

50

8192

≤

Period of CLK High

Period of CLK Low

Rise Time of CLK

Full Time of CLK

50

ns

10

ns

t_FC

ns

t_HCF

Hold Time: CLK - FS

Set-up Time: FS - CLK

0

ns

t_SFC

30

ns

t_DCD

t_DCZ

Delay Time: CLK High to data valid. out: 150 pF

Delay Time: to Data Disabled

80

ns

0

ns

t_DFD

Delay Time: FSync. High to data valid. count: 150 pF. Applies

only if Sync rises later than CLK raising edge.

ns

t_SDC

t_HDC

Set-up Time: Data valid to CLK receive edge.

Hold Time: CLK low to data invalid.

30

ns

ELECTRICAL CHARACTERISTICS - Single Clock Interface

Symbol

FSync

F_CLK

t_WCH

t_WCL

t_RC

Parameter

Min.

Typ.

Max.

Unit

KHz

ns

8 KHz

8

8 x n x FSync 1

n

64

≤

64

80

4096

≤

Period of CLK High

Period of CLK Low

Rise Time of CLK

Full Time of CLK

ns

10

ns

t_FC

ns

t_HCF

Hold Time: CLK - FS

Set-up Time: FS - CLK

0

ns

t_SFC

100

ns

t_DCD

t_DCZ

Delay Time: CLK High to data valid. out: 150 pF

Delay Time: to Data Disabled

80

ns

0

ns

t_DFD

Delay Time: FSync. High to data valid. count: 150 pF. Applies

only if Sync rises later than CLK raising edge.

ns

t_SDC

t_HDC

Set-up Time: Data valid to CLK receive edge.

Hold Time: CLK low to data invalid.

30

ns

26/34

ST5451

Figure 14:

GCI Timing

Figure 15:

SingleClock Diagram

27/34

ST5451

Figure 16:

µ

Non-multiplexed P bus timing

READ CYCLE (Non-multiplexed mode)

Symbol

t_EAH

t_AES

Parameter

Min.

10

Max.

Unit

ns

Address Hold After E

R/W Hold After E

Address to E Setup

R/W to E. Setup

10

ns

20

ns

t_AES

20

ns

t_ACC

t_DF

Data Delay from E

Output Float Delay

Minimum Width of E

110

25

ns

t_WE

110

ns

WRITE CYCLE (Non-multiplexed mode)

Symbol

t_EAH

t_AES

Parameter

Min.

10

Max.

Unit

ns

Address Hold After

R/W Hold After E

10

Address to E Setup

R/W to E.CS Setup

Data to End of E Setup

End of E.CS to Data hold

Minimum Width of E

20

t_AES

20

t_DES

t_EDH

t_WE

35

10

60

t_RW

Minimum Width of RESET

100

28/34

ST5451

Figure 17:

µ

MultiplexedIntel-like P bus timing

READ CYCLE (Multiplexed Intel Mode)

Symbol

t_LA

Parameter

Min.

10

Max.

Unit

ns

Address Hold After ALE

Address to ALE Setup

Data Delay from RD

RD Pulse Width

t_AL

20

t_RD

110

25

t_RR

110

t_DF

Output Float Delay

RD Control Interval

ALE Pulse Width

t_RI

70

30

20

10

t_WA

t_CSS

t_CSH

CE to RD or WR set-up t_CSS

CE hold after RD to WR t_CSH

WRITE CYCLE (Multiplexed Intel Mode)

Symbol

t_ww

Parameter

Min.

60

Max.

Unit

ns

WR Pulse Width

t_DW

Data Setup to WR

Data Hold after WR

WR Control Interval

35

ns

t_WD

10

ns

t_WI

70

ns

29/34

ST5451

Figure 18:

µ

MultiplexedMotorola-like P bus timing

Symbol

t_WAS

t_WDS

t_ASDS

t_RWS

t_RWH

t_CSS

Parameter

AS Pulse Width

Min.

30

Max.

Unit

ns

DS Pulse Width

110

10

AS low to DS high

RW to DS setup

20

RW hold after DS

10

CS to DS setup

20

t_CSH

CS hold after DS

10

t_AAS

Address to AS setup

Address hold after AS

20

t_AAH

10

READ CYCLE

Symbol

Parameter

Min.

Max.

110

25

Unit

ns

t_DV

t_DF

Data Valid after DS

Output Flat Delay

ns

WRITE CYCLE

Symbol

Min.

35

Max.

Unit

ns

t_DWS

t_DWH

Data to DS setup

Data Hold after DS

10

ns

30/34

ST5451

DMA BUS TIMING (Reception Mode)

Symbol

t_ACC

Parameter

Min.

Max.

110

25

Unit

ns

Data Delay from ACKR

Output Float Delay

t_DF

ns

t_WAR

Minimum width ACKR

REQR Delay from ACKR

110

70

ns

t_DRAR

80

ns

Figure 19: DMAframe reception timing

Figure 20:

DMAframe transmission timing

DMA BUS TIMING

(Transmission Mode)

Symbol

Parameter

Min.

35

Max.

Unit

ns

t_DAS

t_DAH

Data Setup to ACKX

Data Hold from ACKX

10

ns

t_WAX

t_DRAX

Minimum width ACKX

REQX Delay from ACKX

60

ns

70

ns

80

ns

31/34

ST5451

DEN TIMING

Symbol

Parameter

Min.

Max.

30

Unit

ns

t_DRCS

t_DRCH

t_DFCS

t_DRCH

DEN setup to CLK

DEN Hold from CLK

DEN Setup to CLK

DEN Hold from CLK

30

ns

30

ns

30

ns

Figure 21: DEN Timing

32/34

ST5451

mm

inch

DIM.

OUTLINE AND

MECHANICAL DATA

MIN. TYP. MAX. MIN. TYP. MAX.

A

a1

b

2.65

0.3

0.104

0.012

0.019

0.013

0.1

0.004

0.35

0.23

0.49 0.014

0.32 0.009

b1

C

c1

D

E

0.5

0.020

45° (typ.)

17.7

10

18.1 0.697

10.65 0.394

0.713

0.419

e

1.27

0.050

0.65

e3

F

16.51

7.4

0.4

7.6

0.291

0.299

0.050

L

1.27 0.016

SO28

S

8 ° (max.)

33/34

ST5451

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is

granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are

subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products

are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics

2000 STMicroelectronics – Printed in Italy – AllRights Reserved

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34/34


型号：	ST5451
厂家：	ST
描述：	ISDN HDLC AND GCI CONTROLLER ISDN和HDLC控制器GCI 综合业务数字网控制器
文件：	总34页 (文件大小：269K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ST5451 [STMICROELECTRONICS]

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