ST6210CM1 [STMICROELECTRONICS]
8-BIT OTP/EPROM MCUs WITH A/D CONVERTER, OSCILLATOR SAFEGUARD, SAFE RESET AND 20 PINS; 8位OTP / EPROM微控制器与A / D转换器，振荡器保障，国家外汇管理局复位和20引脚
| 型号： | ST6210CM1 |
| 厂家： | 
ST |
| 描述： | 8-BIT OTP/EPROM MCUs WITH A/D CONVERTER, OSCILLATOR SAFEGUARD, SAFE RESET AND 20 PINS |
| 文件： | 总70页 (文件大小：737K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ST62T08C/T09C
ST62T10C/T20C/E20C
8-BIT OTP/EPROM MCUs WITH A/D CONVERTER,
OSCILLATOR SAFEGUARD, SAFE RESET AND 20 PINS
■
■
■
■
■
■
■
3.0 to 6.0V Supply Operating Range
8 MHz Maximum Clock Frequency
-40 to +125°C Operating Temperature Range
Run, Wait and Stop Modes
5 Interrupt Vectors
Look-up Table capability in Program Memory
Data Storage in Program Memory:
User selectable size
■
■
■
Data RAM: 64bytes
User Programmable Options
12 I/O pins, fully programmable as:
– Input with pull-up resistor
PDIP20
– Input without pull-up resistor
– Input with interrupt generation
– Open-drain or push-pull output
– Analog Input (except ST62T08C)
4 I/O lines can sink up to 20mA to drive LEDs or
TRIACs directly
8-bit Timer/Counter with 7-bit programmable
prescaler
■
■
PSO20
■
■
■
■
■
Digital Watchdog
Oscillator Safe Guard
Low Voltage Detector for Safe Reset
8-bit A/D Converter with up to 8 analog inputs
On-chip Clock oscillator can be driven by Quartz
Crystal Ceramic resonator or RC network
CDIP20W
■
■
■
Power-on Reset
One external Non-Maskable Interrupt
(See end of Datasheet for Ordering Information)
ST626x-EMU2 Emulation and Development
System (connects to an MS-DOS PC via a
parallel port)
DEVICE SUMMARY
OTP
(Bytes) (Bytes)
EPROM
Analog
inputs
DEVICE
I/O Pins
ST62T08C
ST62T09C
ST62T10C
ST62T20C
ST62E20C
1036
1036
1836
3884
-
-
12
12
12
12
12
-
-
4
8
8
8
-
-
3884
Rev. 2.6
September 1998
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Table of Contents
Document
Page
ST62T08C/T09C/ST62T10C/T20C/E20C . . . . . . . . . . . . . . . . . . 1
1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . 4
1.2 PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.3 MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.3.2 Program Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.3.3 Data Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.3.4 Stack Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.3.5 Data Window Register (DWR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.4 PROGRAMMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.4.1 Option Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.4.2 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.4.3 EPROM Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 12
2.2 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . 14
3.1 CLOCK SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1.1 Main Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1.2 Low Frequency Auxiliary Oscillator (LFAO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1.3 Oscillator Safe Guard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2 RESETS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.2.1 RESET Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.2.2 Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.2.3 Watchdog Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2.4 LVD Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2.5 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2.6 MCU Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.3 DIGITAL WATCHDOG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.3.1 Digital Watchdog Register (DWDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.3.2 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.4 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . 26
3.4.1 Interrupt request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.4.2 Interrupt Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.4.3 Interrupt Option Register (IOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.4.4 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.5 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.5.1 WAIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.5.2 STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.5.3 Exit from WAIT and STOP Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.1 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.1.1 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.1.2 Safe I/O State Switching Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.1.3 I/O Port Option Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
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4.1.4 I/O Port Data Direction Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.1.5 I/O Port Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.2 TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.2.1 Timer Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.2.2 Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.2.3 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.2.4 Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.3 A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.3.1 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5 SOFTWARE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5.1 ST6 ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5.2 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5.3 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
6 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.1 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.2 RECOMMENDED OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.3 DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6.4 AC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6.5 A/D CONVERTER CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.6 TIMER CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
7 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
7.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
7.2 .ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
ST62P08C/P09C/ST62P10C/P20C . . . . . . . . . . . . . . . . . . . . . . 61
1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 62
1.2 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
1.2.1 Transfer of Customer Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
1.2.2 Listing Generation and Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
ST6208C/09C/ST6210C/20C . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 66
1.2 ROM READOUT PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
1.3 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
1.3.1 Transfer of Customer Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
1.3.2 Listing Generation and Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
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ST62T08C/T09C ST62T10C/T20C/E20C
1 GENERAL DESCRIPTION
1.1 INTRODUCTION
The ST62T08C,T09C,T10C,T20C and ST62E20C
devices are low cost members of the ST62xx 8-bit
HCMOS family of microcontrollers, which is target-
ed at low to medium complexity applications. All
ST62xx devices are based on a building block ap-
proach: a common core is surrounded by a
number of on-chip peripherals.
tionality selecting as ROM options the options de-
fined in the programmable option bytes of the
OTP/EPROM versions.
OTP devices offer all the advantages of user pro-
grammability at low cost, which make them the
ideal choice in a wide range of applications where
frequent code changes, multiple code versions or
last minute programmability are required.
The ST62E20C is the erasable EPROM version of
the ST62T08C,T09C,T10C and T20C device,
which may be used to emulate the
ST62T08C,T09C,T10C and T20C device, as well
as the respective ST6208C,09C,10C,20C ROM
devices.
These compact low-cost devices feature a Timer
comprising an 8-bit counter and a 7-bit program-
mable prescaler,an 8-bit A/D Converter with up to
8 analog inputs and a Digital Watchdog timer,
making them well suited for a wide range of auto-
motive, appliance and industrial applications.
OTP and EPROM devices are functionally identi-
cal. The ROM based versions offer the same func-
Figure 1. Block Diagram
8-BIT
A/D CONVERTER
PA0..PA3 (20mA Sink)
PORT A
TEST
TEST/V
NMI
PP
PB0..PB7 / Ain (*)
PORT B
INTERRUPT
PROGRAM
DATA ROM
USER
SELECTABLE
MEMORY
1036 Bytes
(ST62T08C,T09C)
:
1836 Bytes
(ST62T10C)
TIMER
TIMER
DATA RAM
64 Bytes
3884 Bytes
(ST62T20C, E20C)
DIGITAL
WATCHDOG
PC
STACK LEVEL 1
STACK LEVEL 2
STACK LEVEL 3
STACK LEVEL 4
STACK LEVEL 5
STACK LEVEL 6
8 BIT CORE
POWER
RESET
RESET
OSCILLATOR
SUPPLY
V
V
OSCin OSCout
DD SS
(*) Analog input availability depend on versions
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ST62T08C/T09C ST62T10C/T20C/E20C
1.2 PIN DESCRIPTIONS
and V . Power is supplied to the MCU via
V
up resistors, open-drain or push-pull outputs. PA0-
PA3 can also sink 20mA for direct LED driving.
DD
SS
these two pins. V
is the power connection and
DD
V
is the ground connection.
SS
PB0-PB7. These 8 lines are organized as one I/O
port (B). Each line may be configured under soft-
ware control as inputs with or without internal pull-
up resistors, interrupt generating inputs with pull-
up resistors, open-drain or push-pull outputs. PB0-
PB3 can be used as analog input to the A/D con-
verter on the ST62T10C, T20C and E20C, while
PB4-PB7 can be used as analog inputs for the A/D
converter on the ST62T09C, T10C, T20C and
E20C.
OSCin and OSCout. These pins are internally
connected to the on-chip oscillator circuit. A quartz
crystal, a ceramic resonator or an external clock
signal can be connected between these two pins.
The OSCin pin is the input pin, the OSCout pin is
the output pin.
RESET. The active-low RESET pin is used to re-
start the microcontroller. Internal pull-up is provid-
ed at this pin.
Figure 2. ST62T08C,T09C, T10C, T20C and
E20C Pin Configuration
TEST/VPP. The TEST must be held at VSS for nor-
mal operation. If TEST pin is connected to a
+12.5V level during the reset phase, the EPROM
programming Mode is entered.
V
V
DD
SS
1
2
20
19
18
17
16
15
14
13
12
11
NMI. The NMI pin provides the capability for asyn-
chronous interruption, by applying an external non
maskable interrupt to the MCU. The NMI input is
falling edge sensitive. The user can select as op-
tion the availability of an on-chip pull-up at this pin.
TIMER
OSCin
OSCout
NMI
PA0/20 mA Sink
PA1/20 mA Sink
PA2/20 mA Sink
PA3/20 mA Sink
3
4
TIMER. This is the timer I/O pin. In input mode it is
connected to the prescaler and acts as external
timer clock input or as control gate input for the in-
ternal timer clock. In output mode the timer pin out-
puts the data bit when a time-out occurs. The user
can select as option the availability of an on-chip
pull-up at this pin.
5
6
V
/TEST
PB0/Ain*
PB1/Ain*
PB2/Ain*
PB3/Ain*
PB4/Ain*
PP
7
RESET
8
Ain*/PB7
Ain*/PB6
Ain*/PB5
9
10
PA0-PA3. These 4 lines are organized as one I/O
port (A). Each line may be configured under soft-
ware control as inputs with or without internal pull-
up resistors, interrupt generating inputs with pull-
*Analog input availability depend on device
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ST62T08C/T09C ST62T10C/T20C/E20C
1.3 MEMORY MAP
1.3.1 Introduction
Briefly, Program space contains user program
code in OTP and user vectors; Data space con-
tains user data in RAM and in OTP, and Stack
space accommodates six levels of stack for sub-
routine and interrupt service routine nesting.
The MCU operates in three separate memory
spaces: Program space, Data space, and Stack
space. Operation in these three memory spaces is
described in the following paragraphs.
Figure 3. Memory Addressing Diagram
PROGRAM SPACE
DATA SPACE
0000h
000h
RAM / EEPROM
BANKING AREA
0-63
03Fh
040h
DATA READ-ONLY
WINDOW
MEMORY
PROGRAM
MEMORY
07Fh
080h
081h
082h
083h
084h
X REGISTER
Y REGISTER
V REGISTER
W REGISTER
RAM
DATA READ-ONLY
MEMORY
WINDOW SELECT
0C0h
0FF0h
DATA RAM
INTERRUPT &
RESET VECTORS
0FFFh
BANK SELECT
ACCUMULATOR
0FFh
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ST62T08C/T09C ST62T10C/T20C/E20C
MEMORY MAP (Cont’d)
1.3.2 Program Space
Program Space comprises the instructions to be
executed, the data required for immediate ad-
dressing mode instructions, the reserved factory
test area and the user vectors. Program Space is
addressed via the 12-bit Program Counter register
(PC register)Program Memory Protection.
In the EPROM parts, READOUT PROTECTION
option can be disactivated only by U.V. erasure
that also results into the whole EPROM context
erasure.
Note: Once the Readout Protection is activated, it
is no longer possible, even for STMicroelectronics,
to gain access to the OTP contents. Returned
parts with a protection set can therefore not be ac-
cepted.
The Program Memory in OTP or EPROM devices
can be protected against external readout of mem-
ory by selecting the READOUT PROTECTION op-
tion in the option byte.
Figure 4. Program Memory Map
ST62T08C,T09C
ST62T10C
ST62T20C,E20C
0000h
0000h
0000h
*
RESERVED
07Fh
080h
NOT IMPLEMENTED
NOT IMPLEMENTED
07FFh
0800h
*
RESERVED
087Fh
0880h
USER
0AFFh
0B00h
PROGRAM MEMORY
(OTP/EPROM)
3872 BYTES
*
RESERVED
0B9Fh
0BA0h
USER
PROGRAM MEMORY
(OTP)
USER
PROGRAM MEMORY
(OTP)
1824 BYTES
1024 BYTES
0F9Fh
0FA0h
0FEFh
0FF0h
0FF7h
0FF8h
0FFBh
0FFCh
0FFDh
0FFEh
0FFFh
0F9Fh
0FA0h
0FEFh
0FF0h
0FF7h
0FF8h
0FFBh
0FFCh
0FFDh
0FFEh
0FFFh
0F9Fh
0FA0h
0FEFh
0FF0h
0FF7h
0FF8h
0FFBh
0FFCh
0FFDh
0FFEh
0FFFh
*
*
*
RESERVED
RESERVED
RESERVED
INTERRUPT VECTORS
RESERVED
INTERRUPT VECTORS
RESERVED
INTERRUPT VECTORS
*
RESERVED
NMI VECTOR
NMI VECTOR
NMI VECTOR
USER RESET VECTOR
USER RESET VECTOR
USER RESET VECTOR
(*) Reserved areas should be filled with 0FFh
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ST62T08C/T09C ST62T10C/T20C/E20C
MEMORY MAP (Cont’d)
1.3.3 Data Space
Table 1. ST6208C/09C/10C/20C Data Memory
Space
Data Space accommodates all the data necessary
for processing the user program. This space com-
prises the RAM resource, the processor core and
peripheral registers, as well as read-only data
such as constants and look-up tables in OTP/
EPROM.
000h
RESERVED
03Fh
040h
DATA ROM WINDOW AREA
64 BYTES
07Fh
1.3.3.1 Data ROM
X REGISTER
Y REGISTER
V REGISTER
W REGISTER
080h
081h
082h
083h
084h
0BFh
0C0h
0C1h
0C2h
0C3h
0C4h
0C5h
0C6h
0C7h
0C8h*
0C9h*
0CAh
0CBh
0CCh
0CDh
0CEh
0CFh
0D0h
0D1h
0D2h
0D3h
0D4h
0D5h
0D6h
0D7h
0D8h
0D9h
All read-only data is physically stored in program
memory, which also accommodates the Program
Space. The program memory consequently con-
tains the program code to be executed, as well as
the constants and look-up tables required by the
application.
DATA RAM 60 BYTES
PORT A DATA REGISTER
PORT B DATA REGISTER
RESERVED
The Data Space locations in which the different
constants and look-up tables are addressed by the
processor core may be thought of as a 64-byte
window through which it is possible to access the
read-only data stored in OTP/EPROM.
RESERVED
PORT A DIRECTION REGISTER
PORT B DIRECTION REGISTER
RESERVED
1.3.3.2 Data RAM
RESERVED
In ST6208C/09C/10C/20C devices, the data
space includes 60 bytes of RAM, the accumulator
(A), the indirect registers (X), (Y), the short direct
registers (V), (W), the I/O port registers, the pe-
ripheral data and control registers, the interrupt
option register and the Data ROM Window register
(DRW register).
INTERRUPT OPTION REGISTER
DATA ROM WINDOW REGISTER
RESERVED
PORT A OPTION REGISTER
PORT B OPTION REGISTER
RESERVED
1.3.4 Stack Space
RESERVED
Stack space consists of six 12-bit registers which
are used to stack subroutine and interrupt return
addresses, as well as the current program counter
contents.
A/D DATA REGISTER(except ST62T08C)
A/D CONTROL REGISTER (except ST62T08C)
TIMER PRESCALER REGISTER
TIMER COUNTER REGISTER
TIMER STATUS CONTROL REGISTER
RESERVED
WATCHDOG REGISTER
RESERVED
0FEh
0FFh
ACCUMULATOR
* WRITE ONLY REGISTER
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ST62T08C/T09C ST62T10C/T20C/E20C
Data Window Register (DWR)
MEMORY MAP (Cont’d)
1.3.5 Data Window Register (DWR)
The Data read-only memory window is located from
address 0040h to address 007Fh in Data space. It
allows direct reading of 64 consecutive bytes locat-
ed anywhere in program memory, between ad-
dress 0000h and 0FFFh (top memory address de-
pends on the specific device). All the program
memory can therefore be used to store either in-
structions or read-only data. Indeed, the window
can be moved in steps of 64 bytes along the pro-
gram memory by writing the appropriate code in the
Data Window Register (DWR).
Address: 0C9h
—
Write Only
7
0
-
-
DWR5 DWR4 DWR3 DWR2 DWR1 DWR0
Bits 6, 7 = Not used.
Data read-only memory
These are the Data read-
Bit 5-0 = DWR5-DWR0:
Window Register Bits.
only memory Window bits that correspond to the
upper bits of the data read-only memory space.
The DWR can be addressed like any RAM location
in the Data Space, it is however a write-only regis-
ter and therefore cannot be accessed using single-
bit operations. This register is used to position the
64-byte read-only data window (from address 40h
to address 7Fh of the Data space) in program
memory in 64-byte steps. The effective address of
the byte to be read as data in program memory is
obtained by concatenating the 6 least significant
bits of the register address given in the instruction
(as least significant bits) and the content of the
DWR register (as most significant bits), as illustrat-
ed in Figure 5 below. For instance, when address-
ing location 0040h of the Data Space, with 0 load-
ed in the DWR register, the physical location ad-
dressed in program memory is 00h. The DWR reg-
ister is not cleared on reset, therefore it must be
written to prior to the first access to the Data read-
only memory window area.
Caution: This register is undefined on reset. Nei-
ther read nor single bit instructions may be used to
address this register.
Note: Care is required when handling the DWR
register as it is write only. For this reason, the
DWR contents should not be changed while exe-
cuting an interrupt service routine, as the service
routine cannot save and then restore the register’s
previous contents. If it is impossible to avoid writ-
ing to the DWR during the interrupt service routine,
an image of the register must be saved in a RAM
location, and each time the program writes to the
DWR, it must also write to the image register. The
image register must be written first so that, if an in-
terrupt occurs between the two instructions, the
DWR is not affected.
Figure 5. Data read-only memory Window Memory Addressing
13 12 11 10
9
3
8
2
7
1
6
0
5
5
4
4
3
3
2
2
1
1
0
0
PROGRAM SPACE ADDRESS
READ
DATA ROM
WINDOW REGISTER
CONTENTS
7
6
5
4
DATA SPACE ADDRESS
:
(DWR)
40h-7Fh
0
1
IN INSTRUCTION
Example:
1
0
0
1
1
0
0
0
0
0
1
DWR=28h
DATA SPACE ADDRESS
:
1
1
1
1
1
0
0
0
0
0
0
59h
ROM
ADDRESS:A19h
1
0
0
1
VR01573C
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ST62T08C/T09C ST62T10C/T20C/E20C
1.4 PROGRAMMING MODES
1.4.1 Option Bytes
LVD. LVD RESET enable.When this bit is set, safe
RESET is performed by MCU when the supply
voltage is too low. When this bit is cleared, only
power-on reset or external RESET are active.
The two Option Bytes allow configuration capabili-
ty to the MCUs. Option byte’s content is automati-
cally read, and the selected options enabled, when
the chip reset is activated.
PROTECT.
Readout Protection.
This bit allows the
protection of the software contents against piracy.
When the bit PROTECT is set high, readout of the
OTP contents is prevented by hardware.. When
this bit is low, the user program can be read.
It can only be accessed during the programming
mode. This access is made either automatically
(copy from a master device) or by selecting the
OPTION BYTE PROGRAMMING mode of the pro-
grammer.
OSCIL.
Oscillator selection
. When this bit is low,
the oscillator must be controlled by a quartz crys-
tal, a ceramic resonator or an external frequency.
When it is high, the oscillator must be controlled by
an RC network, with only the resistor having to be
externally provided.
The option bytes are located in a non-user map.
No address has to be specified.
EPROM Code Option Byte (LSB)
D5. Reserved. Must be cleared to zero.
D4. Reserved. Must be set to one.
7
0
PRO-
TECT
NMI
PULL PULL
TIM
OS-
GEN
OSCIL
-
-
WDACT
NMI PULL. NMI Pull-Up. This bit must be set high
to configure the NMI pin with a pull-up resistor.
When it is low, no pull-up is provided.
TIM PULL.TIM Pull-Up. This bit must be set high
to configure the TIMER pin with a pull-up resistor.
When it is low, no pull-up is provided.
EPROM Code Option Byte (MSB)
15
8
EXTC-
NTL
WDACT. This bit controls the watchdog activation.
When it is high, hardware activation is selected.
The software activation is selected when WDACT
is low.
-
-
-
-
-
-
LVD
D15-D10. Reserved. Must be cleared
EXTCNTL. External STOP MODE control.. When
EXTCNTL is high, STOP mode is available with
watchdog active by setting NMI pin to one.. When
EXTCNTL is low, STOP mode is not available with
the watchdog active.
OSGEN. Oscillator Safe Guard. This bit must be
set high to enable the Oscillator Safe Guard.
When this bit is low, the OSG is disabled.
The Option byte is written during programming ei-
ther by using the PC menu (PC driven Mode) or
automatically (stand-alone mode)
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ST62T08C/T09C ST62T10C/T20C/E20C
Table 4. ST62T20C,E20C Program Memory Map
PROGRAMMING MODES (Cont’d)
1.4.2 Program Memory
EPROM/OTP programming mode is set by a
Device Address
Description
+12.5V voltage applied to the TEST/V pin. The
PP
0000h-007Fh
0080h-0F9Fh
0FA0h-0FEFh
0FF0h-0FF7h
0FF8h-0FFBh
0FFCh-0FFDh
0FFEh-0FFFh
Reserved
User ROM
Reserved
programming
flow
of
the
ST62T08C,T09C,T10C,T20C/E20C is described
in the User Manual of the EPROM Programming
Board.
Interrupt Vectors
Reserved
NMI Interrupt Vector
Reset Vector
Table 2. ST62T08C, T09C Program Memory Map
Device Address
Description
Note: OTP/EPROM devices can be programmed
with the development tools available from STMi-
croelectronics (ST62E2X-EPB or ST622X-KIT).
0000h-0B9Fh
0BA0h-0F9Fh
0FA0h-0FEFh
0FF0h-0FF7h
0FF8h-0FFBh
0FFCh-0FFDh
0FFEh-0FFFh
Reserved
User ROM
Reserved
1.4.3 EPROM Erasing
Interrupt Vectors
Reserved
NMI Interrupt Vector
Reset Vector
The EPROM of the windowed package of the
MCUs may be erased by exposure to Ultra Violet
light. The erasure characteristic of the MCUs is
such that erasure begins when the memory is ex-
posed to light with a wave lengths shorter than ap-
proximately 4000Å. It should be noted that sun-
lights and some types of fluorescent lamps have
wavelengths in the range 3000-4000Å.
Table 3. ST62T10C Program Memory Map
Device Address
Description
0000h-087Fh
0880h-0F9Fh
0FA0h-0FEFh
0FF0h-0FF7h
0FF8h-0FFBh
0FFCh-0FFDh
0FFEh-0FFFh
Reserved
User ROM
Reserved
It is thus recommended that the window of the
MCUs packages be covered by an opaque label to
prevent unintentional erasure problems when test-
ing the application in such an environment.
Interrupt Vectors
Reserved
NMI Interrupt Vector
Reset Vector
The recommended erasure procedure of the
MCUs EPROM is the exposure to short wave ul-
traviolet light which have a wave-length 2537A.
The integrated dose (i.e. U.V. intensity x exposure
time) for erasure should be a minimum of 30W-
2
sec/cm . The erasure time with this dosage is ap-
proximately 30 to 40 minutes using an ultraviolet
2
lamp with 12000µW/cm power rating. The
ST62E20C should be placed within 2.5cm (1Inch)
of the lamp tubes during erasure.
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ST62T08C/T09C ST62T10C/T20C/E20C
2 CENTRAL PROCESSING UNIT
2.1 INTRODUCTION
The CPU Core of ST6 devices is independent of the
I/O or Memory configuration. As such, it may be
thought of as an independent central processor
communicating with on-chip I/O, Memory and Pe-
ripherals via internal address, data, and control
buses. In-core communication is arranged as
shown in Figure 6; the controller being externally
linked to both the Reset and Oscillator circuits,
while the core is linked to the dedicated on-chip pe-
ripherals via the serial data bus and indirectly, for
interrupt purposes, through the control registers.
Indirect Registers (X, Y). These two indirect reg-
isters are used as pointers to memory locations in
Data space. They are used in the register-indirect
addressing mode. These registers can be ad-
dressed in the data space as RAM locations at ad-
dresses 80h (X) and 81h (Y). They can also be ac-
cessed with the direct, short direct, or bit direct ad-
dressing modes. Accordingly, the ST6 instruction
set can use the indirect registers as any other reg-
ister of the data space.
Short Direct Registers (V, W). These two regis-
ters are used to save a byte in short direct ad-
dressing mode. They can be addressed in Data
space as RAM locations at addresses 82h (V) and
83h (W). They can also be accessed using the di-
rect and bit direct addressing modes. Thus, the
ST6 instruction set can use the short direct regis-
ters as any other register of the data space.
2.2 CPU REGISTERS
TheST6FamilyCPUcorefeaturessixregistersand
three pairs of flags available to the programmer.
These are described in the following paragraphs.
Accumulator (A). The accumulator is an 8-bit
general purpose register used in all arithmetic cal-
culations, logical operations, and data manipula-
tions. The accumulator can be addressed in Data
space as a RAM location at address FFh. Thus the
ST6 can manipulate the accumulator just like any
other register in Data space.
Program Counter (PC). The program counter is a
12-bit register which contains the address of the
next ROM location to be processed by the core.
This ROM location may be an opcode, an oper-
and, or the address of an operand. The 12-bit
length allows the direct addressing of 4096 bytes
in Program space.
Figure 6. ST6 Core Block Diagram
0,01 TO 8MHz
RESET
OSCin
OSCout
INTERRUPTS
CONTROLLER
DATA SPACE
DATA
CONTROL
SIGNALS
FLAG
VALUES
OPCODE
ADDRESS/READ LINE
ADDRESS
2
RAM/EEPROM
PROGRAM
DATA
ROM/EPROM
256
ROM/EPROM
DECODER
B-DATA
A-DATA
DEDICATIONS
ACCUMULATOR
Program Counter
and
12
FLAGS
6 LAYER STACK
ALU
RESULTS TO DATA SPACE (WRITE LINE)
VR01811
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ST62T08C/T09C ST62T10C/T20C/E20C
CPU REGISTERS (Cont’d)
However, if the program space contains more than
4096 bytes, the additional memory in program
space can be addressed by using the Program
Bank Switch register.
automatically selected after the reset of the MCU,
the ST6 core uses at first the NMI flags.
Stack. The ST6 CPU includes a true LIFO hard-
ware stack which eliminates the need for a stack
pointer. The stack consists of six separate 12-bit
RAM locations that do not belong to the data
space RAM area. When a subroutine call (or inter-
rupt request) occurs, the contents of each level are
shifted into the next higher level, while the content
of the PC is shifted into the first level (the original
contents of the sixth stack level are lost). When a
subroutine or interrupt return occurs (RET or RETI
instructions), the first level register is shifted back
into the PC and the value of each level is popped
back into the previous level. Since the accumula-
tor, in common with all other data space registers,
is not stored in this stack, management of these
registers should be performed within the subrou-
tine. The stack will remain in its “deepest” position
if more than 6 nested calls or interrupts are execut-
ed, and consequently the last return address will
be lost. It will also remain in its highest position if
the stack is empty and a RET or RETI is executed.
In this case the next instruction will be executed.
The PC value is incremented after reading the ad-
dress of the current instruction. To execute relative
jumps, the PC and the offset are shifted through
the ALU, where they are added; the result is then
shifted back into the PC. The program counter can
be changed in the following ways:
- JP (Jump) instructionPC=Jump address
- CALL instructionPC= Call address
- Relative Branch Instruction.PC= PC +/- offset
- Interrupt
- Reset
PC=Interrupt vector
PC= Reset vector
- RET & RETI instructionsPC= Pop (stack)
- Normal instructionPC= PC + 1
Flags (C, Z). The ST6 CPU includes three pairs of
flags (Carry and Zero), each pair being associated
with one of the three normal modes of operation:
Normal mode, Interrupt mode and Non Maskable
Interrupt mode. Each pair consists of a CARRY
flag and a ZERO flag. One pair (CN, ZN) is used
during Normal operation, another pair is used dur-
ing Interrupt mode (CI, ZI), and a third pair is used
in the Non Maskable Interrupt mode (CNMI, ZN-
MI).
Figure 7. ST6 CPU Programming Mode
l
b7 X REG. POINTER b0
INDEX
REGISTER
SHORT
DIRECT
ADDRESSING
MODE
b7 Y REG. POINTER b0
The ST6 CPU uses the pair of flags associated
with the current mode: as soon as an interrupt (or
a Non Maskable Interrupt) is generated, the ST6
CPU uses the Interrupt flags (resp. the NMI flags)
instead of the Normal flags. When the RETI in-
struction is executed, the previously used set of
flags is restored. It should be noted that each flag
set can only be addressed in its own context (Non
Maskable Interrupt, Normal Interrupt or Main rou-
tine). The flags are not cleared during context
switching and thus retain their status.
V REGISTER
W REGISTER
b7
b7
b0
b0
b0
b0
b7 ACCUMULATOR
PROGRAM COUNTER
b11
SIX LEVELS
STACK REGISTER
The Carry flag is set when a carry or a borrow oc-
curs during arithmetic operations; otherwise it is
cleared. The Carry flag is also set to the value of
the bit tested in a bit test instruction; it also partici-
pates in the rotate left instruction.
NORMAL FLAGS
INTERRUPT FLAGS
NMI FLAGS
C
C
C
Z
Z
Z
The Zero flag is set if the result of the last arithme-
tic or logical operation was equal to zero; other-
wise it is cleared.
Switching between the three sets of flags is per-
formed automatically when an NMI, an interrupt or
a RETI instructions occurs. As the NMI mode is
VA000423
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ST62T08C/T09C ST62T10C/T20C/E20C
3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES
3.1 CLOCK SYSTEM
The MCU features a Main Oscillator which can be
driven by an external clock, or used in conjunction
with an AT-cut parallel resonant crystal or a suita-
ble ceramic resonator, or with an external resistor
Figure 8. Oscillator Configurations
CRYSTAL/RESONATOR CLOCK
CRYSTAL/RESONATOR option
(R
). In addition, a Low Frequency Auxiliary Os-
NET
cillator (LFAO) can be switched in for security rea-
sons, to reduce power consumption, or to offer the
benefits of a back-up clock system.
ST6xxx
The Oscillator Safeguard (OSG) option filters
spikes from the oscillator lines, provides access to
the LFAO to provide a backup oscillator in the
event of main oscillator failure and also automati-
OSC
OSC
in
out
cally limits the internal clock frequency (f ) as a
INT
function of V , in order to guarantee correct oper-
ation. These functions are illustrated in Figure 9,
Figure 10, Figure 11 and Figure 12.
C
DD
C
L1n
L2
Figure 8 illustrates various possible oscillator con-
figurations using an external crystal or ceramic res-
onator, an external clock input, an external resistor
EXTERNAL CLOCK
CRYSTAL/RESONATOR option
(R
), or the lowest cost solution using only the
NET
ST6xxx
LFAO. C an C should have a capacitance in the
range 12 to 22 pF for an oscillator frequency in the
L1
L2
4-8 MHz range.
OSC
OSC
NC
out
in
The internal MCU clock frequency (f ) is divided
INT
by 12 to drive the Timer, the A/D converter and the
Watchdog timer, and by 13 to drive the CPU core,
as may be seen in Figure 11.
RC NETWORK
RC NETWORK option
With an 8MHz oscillator frequency, the fastest ma-
chine cycle is therefore 1.625µs.
A machine cycle is the smallest unit of time needed
to execute any operation (for instance, to increment
the Program Counter). An instruction may require
two, four, or five machine cycles for execution.
ST6xxx
OSC
NC
OSC
out
in
3.1.1 Main Oscillator
The oscillator configuration may be specified by se-
lectingtheappropriate option.WhentheCRYSTAL/
RESONATORoptionisselected,itmustbeusedwith
a quartz crystal, a ceramic resonator or an external
signalprovidedontheOSCinpin.WhentheRCNET-
WORK option is selected, the system clock is gen-
erated by an external resistor.
R
NET
INTEGRATED CLOCK
CRYSTAL/RESONATOR option
OSG ENABLED option
The main oscillator can be turned off (when the
OSG ENABLED option is selected) by setting the
OSCOFF bit of the ADC Control Register. The
Low Frequency Auxiliary Oscillator is automatical-
ly started.
ST6xxx
OSC
OSC
out
in
NC
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ST62T08C/T09C ST62T10C/T20C/E20C
3.1.3 Oscillator Safe Guard
CLOCK SYSTEM (Cont’d)
Turning on the main oscillator is achieved by re-
setting the OSCOFF bit of the A/D Converter Con-
trol Register or by resetting the MCU. Restarting
the main oscillator implies a delay comprising the
oscillator start up delay period plus the duration of
The Oscillator Safe Guard (OSG) affords drastical-
ly increased operational integrity in ST62xx devic-
es. The OSG circuit provides three basic func-
tions: it filters spikes from the oscillator lines which
would result in over frequency to the ST62 CPU; it
gives access to the Low Frequency Auxiliary Os-
cillator (LFAO), used to ensure minimum process-
ing in case of main oscillator failure, to offer re-
duced power consumption or to provide a fixed fre-
quency low cost oscillator; finally, it automatically
limits the internal clock frequency as a function of
supply voltage, in order to ensure correct opera-
tion even if the power supply should drop.
the software instruction at f
clock frequency.
LFAO
3.1.2 Low Frequency Auxiliary Oscillator
(LFAO)
The Low Frequency Auxiliary Oscillator has three
main purposes. Firstly, it can be used to reduce
power consumption in non timing critical routines.
Secondly, it offers a fully integrated system clock,
without any external components. Lastly, it acts as
a safety oscillator in case of main oscillator failure.
The OSG is enabled or disabled by choosing the
relevant OSG option. It may be viewed as a filter
whose cross-over frequency is device dependent.
This oscillator is available when the OSG ENA-
BLED option is selected. In this case, it automati-
cally starts one of its periods after the first missing
edge from the main oscillator, whatever the reason
(main oscillator defective, no clock circuitry provid-
ed, main oscillator switched off...).
Spikes on the oscillator lines result in an effectively
increased internal clock frequency. In the absence
of an OSG circuit, this may lead to an over fre-
quency for a given power supply voltage. The
OSG filters out such spikes (as illustrated in Figure
9). In all cases, when the OSG is active, the maxi-
User code, normal interrupts, WAIT and STOP in-
structions, are processed as normal, at the re-
duced f
frequency. The A/D converter accura-
LFAO
mum internal clock frequency, f , is limited to
INT
cy is decreased, since the internal frequency is be-
f
, which is supply voltage dependent. This re-
OSG
low 1MHz.
lationship is illustrated in Figure 12.
At power on, the Low Frequency Auxiliary Oscilla-
tor starts faster than the Main Oscillator. It there-
fore feeds the on-chip counter generating the POR
delay until the Main Oscillator runs.
When the OSG is enabled, the Low Frequency
Auxiliary Oscillator may be accessed. This oscilla-
tor starts operating after the first missing edge of
the main oscillator (see Figure 10).
The Low Frequency Auxiliary Oscillator is auto-
matically switched off as soon as the main oscilla-
tor starts.
Over-frequency, at a given power supply level, is
seen by the OSG as spikes; it therefore filters out
some cycles in order that the internal clock fre-
quency of the device is kept within the range the
ADCR
particular device can stand (depending on V ),
Address: 0D1h
—
Read/Write
DD
and below f
: the maximum authorised frequen-
OSG
7
0
cy with OSG enabled.
ADCR ADCR ADCR ADCR ADCR OSC ADCR ADCR
OFF
Note. The OSG should be used wherever possible
as it provides maximum safety. Care must be tak-
en, however, as it can increase power consump-
tion and reduce the maximum operating frequency
7
6
5
4
3
1
0
Bit 7-3, 1-0= ADCR7-ADCR3, ADCR1-ADCR0:
ADC Control Register.
These bits are not used.
to f
.
OSG
Bit 2 = OSCOFF. When low, this bit enables main
oscillator to run. The main oscillator is switched off
when OSCOFF is high.
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ST62T08C/T09C ST62T10C/T20C/E20C
CLOCK SYSTEM (Cont’d)
Figure 9. OSG Filtering Principle
(1)
(2)
(3)
(4)
(1) Maximum Frequency for the device to work correctly
(2)
Actual Quartz Crystal Frequency at OSCin pin
(3)
(4)
Noise from OSCin
Resulting Internal Frequency
VR001932
Figure 10. OSG Emergency Oscillator Principle
Main
Oscillator
Emergency
Oscillator
Internal
Frequency
VR001933
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ST62T08C/T09C ST62T10C/T20C/E20C
CLOCK SYSTEM (Cont’d)
Figure 11. Clock Circuit Block Diagram
POR
Core
: 13
OSG
TIMER 1
M
U
X
f
MAIN
OSCILLATOR
INT
Watchdog
: 12
LFAO
: 1
Main Oscillator off
Figure 12. Maximum Operating Frequency (f
) versus Supply Voltage (V
)
DD
MAX
Maximum FREQUENCY (MHz)
8
4
7
6
5
4
3
2
1
3
f
OSG
2
1
f
Min
OSG
2.5
3
3.6
4
4.5
5
5.5
6
SUPPLY VOLTAGE (V
)
DD
VR01807
Notes:
1. In this area, operation is guaranteed at the
quartz crystal frequency.
area is guaranteed at the quartz crystal frequency.
When the OSG is enabled, access to this area is
prevented. The internal frequency is kept a f
OSG.
2. When the OSG is disabled, operation in this
area is guaranteed at the crystal frequency. When
the OSG is enabled, operation in this area is guar-
4. When the OSG is disabled, operation in this
area is not guaranteed
anteed at a frequency of at least f
When the OSG is enabled, access to this area is
OSG Min.
prevented. The internal frequency is kept at f
OSG.
3. When the OSG is disabled, operation in this
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ST62T08C/T09C ST62T10C/T20C/E20C
3.2 RESETS
The MCU can be reset in four ways:
– by the external Reset input being pulled low;
– by Power-on Reset;
is executed immediately following the internal de-
lay.
To ensure correct start-up, the user should take
care that the VDD Supply is stabilized at a suffi-
cient level for the chosen frequency (see recom-
mended operation) before the reset signal is re-
leased. In addition, supply rising must start from
0V.
– by the digital Watchdog peripheral timing out.
– by Low Voltage Detection (LVD)
3.2.1 RESET Input
The RESET pin may be connected to a device of
the application board in order to reset the MCU if
required. The RESET pin may be pulled low in
RUN, WAIT or STOP mode. This input can be
used to reset the MCU internal state and ensure a
correct start-up procedure. The pin is active low
and features a Schmitt trigger input. The internal
Reset signal is generated by adding a delay to the
external signal. Therefore even short pulses on
As a consequence, the POR does not allow to su-
pervise static, slowly rising, or falling, or noisy
(presenting oscillation) VDD supplies.
An external RC network connected to the RESET
pin, or the LVD reset can be used instead to get
the best performances.
Figure 13. Reset and Interrupt Processing
the RESET pin are acceptable, provided V
has
DD
completed its rising phase and that the oscillator is
running correctly (normal RUN or WAIT modes).
The MCU is kept in the Reset state as long as the
RESET pin is held low.
RESET
NMI MASK SET
INT LATCH CLEARED
( IF PRESENT )
If RESET activation occurs in the RUN or WAIT
modes, processing of the user program is stopped
(RUN mode only), the Inputs and Outputs are con-
figured as inputs with pull-up resistors and the
main Oscillator is restarted. When the level on the
RESET pin then goes high, the initialization se-
quence is executed following expiry of the internal
delay period.
SELECT
NMI MODE FLAGS
If RESET pin activation occurs in the STOP mode,
the oscillator starts up and all Inputs and Outputs
are configured as inputs with pull-up resistors.
When the level of the RESET pin then goes high,
the initialization sequence is executed following
expiry of the internal delay period.
PUT FFEH
ON ADDRESS BUS
YES
IS RESET STILL
3.2.2 Power-on Reset
PRESENT?
The function of the POR circuit consists in waking
up the MCU by detecting around 2V a dynamic
(rising edge) variation of the VDD Supply. At the
beginning of this sequence, the MCU is configured
in the Reset state: all I/O ports are configured as
inputs with pull-up resistors and no instruction is
executed. When the power supply voltage rises to
a sufficient level, the oscillator starts to operate,
whereupon an internal delay is initiated, in order to
allow the oscillator to fully stabilize before execut-
ing the first instruction. The initialization sequence
NO
LOAD PC
FROM RESET LOCATIONS
FFE/FFF
FETCH INSTRUCTION
VA000427
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RESETS (Cont’d)
3.2.3 Watchdog Reset
ues, allowing hysteresis effect. Reference value in
case of voltage drop has been set lower than the
reference value for power-on in order to avoid any
parasitic Reset when MCU start's running and
sinking current on the supply.
The MCU provides a Watchdog timer function in
order to ensure graceful recovery from software
upsets. If the Watchdog register is not refreshed
before an end-of-count condition is reached, the
internal reset will be activated. This, amongst oth-
er things, resets the watchdog counter.
As long as the supply voltage is below the refer-
ence value, there is a internal and static RESET
command. The MCU can start only when the sup-
ply voltage rises over the reference value. There-
fore, only two operating mode exist for the MCU:
RESET active below the voltage reference, and
running mode over the voltage reference as
shown on the Figure 14, that represents a power-
up, power-down sequence.
The MCU restarts just as though the Reset had
been generated by the RESET pin, including the
built-in stabilisation delay period.
3.2.4 LVD Reset
The on-chip Low Voltage Detector, selectable as
user option, features static Reset when supply
voltage is below a reference value. Thanks to this
feature, external reset circuit can be removed
while keeping the application safety. This SAFE
RESET is effective as well in Power-on phase as
in power supply drop with different reference val-
Note: When the RESET state is controlled by one
of the internal RESET sources (Low Voltage De-
tector, Watchdog, Power on Reset), the RESET
pin is tied to low logic level.
Figure 14. LVD Reset on Power-on and Power-down (Brown-out)
V
DD
V
Up
V
dn
RESET
RESET
time
VR02106A
3.2.5 Application Notes
No external resistor is required between V
the Reset pin, thanks to the built-in pull-up device.
and
Direct external connection of the pin RESET to
must be avoided in order to ensure safe be-
DD
V
DD
haviour of the internal reset sources (AND.Wired
structure).
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ST62T08C/T09C ST62T10C/T20C/E20C
RESETS (Cont’d)
3.2.6 MCU Initialization Sequence
Figure 15. Reset and Interrupt Processing
When a reset occurs the stack is reset, the PC is
loaded with the address of the Reset Vector (locat-
ed in program ROM starting at address 0FFEh). A
jump to the beginning of the user program must be
coded at this address. Following a Reset, the In-
terrupt flag is automatically set, so that the CPU is
in Non Maskable Interrupt mode; this prevents the
initialisation routine from being interrupted. The in-
itialisation routine should therefore be terminated
by a RETI instruction, in order to revert to normal
mode and enable interrupts. If no pending interrupt
is present at the end of the initialisation routine, the
MCU will continue by processing the instruction
immediately following the RETI instruction. If, how-
ever, a pending interrupt is present, it will be serv-
iced.
RESET
JP:2 BYTES/4 CYCLES
JP
RESET
VECTOR
INITIALIZATION
ROUTINE
RETI: 1 BYTE/2 CYCLES
RETI
VA00181
Figure 16. Reset Block Diagram
V
DD
ST6
INTERNAL
RESET
f
CK
OSC
COUNTER
R
PU
AND. Wired
1)
ESD
R
RESET
RESET
RESET
ON RESET
POWER
WATCHDOG RESET
LVD RESET
VR02107A
1) Resistive ESD protection. Value not guaranteed.
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ST62T08C/T09C ST62T10C/T20C/E20C
RESETS (Cont’d)
Table 5. Register Reset Status
Register
Address(es)
0DCh
Status
Comment
Oscillator Control Register
Port Data Registers
fINT = fOSC; OSG disabled
I/O are Input with pull-up
I/O are Input with pull-up
I/O are Input with pull-up
Interrupt disabled
0C0h to 0C1h
0C4h to 0C5h
0CCh to 0CDh
0C8h
Port Direction Register
Port Option Register
00h
Interrupt Option Register
TIMER Status/Control
0D4h
TIMER disabled
X, Y, V, W, Register
Accumulator
080H TO 083H
0FFh
Data RAM
084h to 0BFh
0C9h
Undefined
As written if programmed
Data ROM Window Register
A/D Result Register
0D0h
TIMER Counter Register
TIMER Prescaler Register
Watchdog Counter Register
A/D Control Register
0D3h
0D2h
0D8h
0D1h
FFh
7Fh
FEh
40h
Max count loaded
A/D in Standby (When available)
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ST62T08C/T09C ST62T10C/T20C/E20C
3.3 DIGITAL WATCHDOG
The digital Watchdog consists of a reloadable
downcounter timer which can be used to provide
controlled recovery from software upsets.
When the Watchdog is disabled, low power Stop
mode is available. Once activated, the Watchdog
cannot be disabled, except by resetting the MCU.
The Watchdog circuit generates a Reset when the
downcounter reaches zero. User software can
prevent this reset by reloading the counter, and
should therefore be written so that the counter is
regularly reloaded while the user program runs
correctly. In the event of a software mishap (usual-
ly caused by externally generated interference),
the user program will no longer behave in its usual
fashion and the timer register will thus not be re-
loaded periodically. Consequently the timer will
decrement down to 00h and reset the MCU. In or-
der to maximise the effectiveness of the Watchdog
function, user software must be written with this
concept in mind.
In the HARDWARE option, the Watchdog is per-
manently enabled. Since the oscillator will run con-
tinuously, low power mode is not available. The
STOP instruction is interpreted as a WAIT instruc-
tion, and the Watchdog continues to countdown.
However, when the EXTERNAL STOP MODE
CONTROL option has been selected low power
consumption may be achieved in Stop Mode.
Execution of the STOP instruction is then gov-
erned by a secondary function associated with the
NMI pin. If a STOP instruction is encountered
when the NMI pin is low, it is interpreted as WAIT,
as described above. If, however, the STOP in-
struction is encountered when the NMI pin is high,
the Watchdog counter is frozen and the CPU en-
ters STOP mode.
Watchdog behaviour is governed by two options,
known as “WATCHDOG ACTIVATION” (i.e.
HARDWARE or SOFTWARE) and “EXTERNAL
STOP MODE CONTROL” (see Table 6).
When the MCU exits STOP mode (i.e. when an in-
terrupt is generated), the Watchdog resumes its
activity.
In the SOFTWARE option, the Watchdog is disa-
bled until bit C of the DWDR register has been set.
Table 6. Recommended Option Choices
Functions Required
Stop Mode & Watchdog
Stop Mode
Recommended Options
“EXTERNAL STOP MODE” & “HARDWARE WATCHDOG”
“SOFTWARE WATCHDOG”
Watchdog
“HARDWARE WATCHDOG”
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ST62T08C/T09C ST62T10C/T20C/E20C
Figure 17. Watchdog Counter Control
DIGITAL WATCHDOG (Cont’d)
The Watchdog is associated with a Data space
register (Digital WatchDog Register, DWDR, loca-
tion 0D8h) which is described in greater detail in
Section 3.3.1 Digital Watchdog Register (DWDR).
This register is set to 0FEh on Reset: bit C is
cleared to “0”, which disables the Watchdog; the
timer downcounter bits, T0 to T5, and the SR bit
are all set to “1”, thus selecting the longest Watch-
dog timer period. This time period can be set to the
user’s requirements by setting the appropriate val-
ue for bits T0 to T5 in the DWDR register. The SR
bit must be set to “1”, since it is this bit which gen-
erates the Reset signal when it changes to “0”;
clearing this bit would generate an immediate Re-
set.
D0
C
D1
SR
RESET
D2
D3
D4
D5
D6
D7
T5
T4
T3
T2
T1
T0
It should be noted that the order of the bits in the
DWDR register is inverted with respect to the as-
sociated bits in the down counter: bit 7 of the
DWDR register corresponds, in fact, to T0 and bit
2 to T5. The user should bear in mind the fact that
these bits are inverted and shifted with respect to
the physical counter bits when writing to this regis-
ter. The relationship between the DWDR register
bits and the physical implementation of the Watch-
dog timer downcounter is illustrated in Figure 17.
Only the 6 most significant bits may be used to de-
fine the time period, since it is bit 6 which triggers
the Reset when it changes to “0”. This offers the
user a choice of 64 timed periods ranging from
3,072 to 196,608 clock cycles (with an oscillator
frequency of 8MHz, this is equivalent to timer peri-
ods ranging from 384µs to 24.576ms).
8
÷
÷
OSC 12
2
VR02068A
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ST62T08C/T09C ST62T10C/T20C/E20C
DIGITAL WATCHDOG (Cont’d)
3.3.1 Digital Watchdog Register (DWDR)
3.3.2 Application Notes
Address: 0D8h
—
Read/Write
The Watchdog plays an important supporting role
in the high noise immunity of ST62xx devices, and
should be used wherever possible. Watchdog re-
lated options should be selected on the basis of a
trade-off between application security and STOP
mode availability.
Reset status: 1111 1110b
7
0
T0
T1
T2
T3
T4
T5
SR
C
When STOP mode is not required, hardware acti-
vation without EXTERNAL STOP MODE CON-
TROL should be preferred, as it provides maxi-
mum security, especially during power-on.
Watchdog Control bit
Bit 0 = C:
If the hardware option is selected, this bit is forced
high and the user cannot change it (the Watchdog
is always active). When the software option is se-
lected, the Watchdog function is activated by set-
ting bit C to 1, and cannot then be disabled (save
by resetting the MCU).
When STOP mode is required, hardware activa-
tion and EXTERNAL STOP MODE CONTROL
should be chosen. NMI should be high by default,
to allow STOP mode to be entered when the MCU
is idle.
When C is kept low the counter can be used as a
7-bit timer.
The NMI pin can be connected to an I/O line (see
Figure 18) to allow its state to be controlled by soft-
ware. The I/O line can then be used to keep NMI
low while Watchdog protection is required, or to
avoid noise or key bounce. When no more
processing is required, the I/O line is released and
the device placed in STOP mode for lowest power
consumption.
This bit is cleared to “0” on Reset.
Software Reset bit
Bit 1 = SR:
This bit triggers a Reset when cleared.
When C = “0” (Watchdog disabled) it is the MSB of
the 7-bit timer.
This bit is set to “1” on Reset.
When software activation is selected and the
Watchdog is not activated, the downcounter may
be used as a simple 7-bit timer (remember that the
bits are in reverse order).
Downcounter bits
Bits 2-7 = T5-T0:
It should be noted that the register bits are re-
versed and shifted with respect to the physical
counter: bit-7 (T0) is the LSB of the Watchdog
downcounter and bit-2 (T5) is the MSB.
The software activation option should be chosen
only when the Watchdog counter is to be used as
a timer. To ensure the Watchdog has not been un-
expectedly activated, the following instructions
should be executed within the first 27 instructions:
These bits are set to “1” on Reset.
jrr 0, WD, #+3
ldi WD, 0FDH
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ST62T08C/T09C ST62T10C/T20C/E20C
DIGITAL WATCHDOG (Cont’d)
These instructions test the C bit and Reset the
MCU (i.e. disable the Watchdog) if the bit is set
(i.e. if the Watchdog is active), thus disabling the
Watchdog.
Figure 18. A typical circuit making use of the
EXERNAL STOP MODE CONTROL feature
In all modes, a minimum of 28 instructions are ex-
ecuted after activation, before the Watchdog can
generate a Reset. Consequently, user software
should load the watchdog counter within the first
27 instructions following Watchdog activation
(software mode), or within the first 27 instructions
executed following a Reset (hardware activation).
SWITCH
NMI
I/O
It should be noted that when the GEN bit is low (in-
terrupts disabled), the NMI interrupt is active but
cannot cause a wake up from STOP/WAIT modes.
VR02002
Figure 19. Digital Watchdog Block Diagram
RESET
Q
RSFF
7
8
-2
-2
-12
R
SET
S
DB1.7 LOAD SET
OSCILLATOR
CLOCK
8
DB0
WRITE
RESET
DATA BUS
VA00010
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ST62T08C/T09C ST62T10C/T20C/E20C
3.4 INTERRUPTS
The CPU can manage four Maskable Interrupt
sources, in addition to a Non Maskable Interrupt
source (top priority interrupt). Each source is asso-
ciated with a specific Interrupt Vector which con-
tains a Jump instruction to the associated interrupt
service routine. These vectors are located in Pro-
gram space (see Table 7).
ically reset by the core at the beginning of the non-
maskable interrupt service routine.
Interrupt request from source #1 can be config-
ured either as edge or level sensitive by setting ac-
cordingly the LES bit of the Interrupt Option Regis-
ter (IOR).
Interrupt request from source #2 are always edge
sensitive. The edge polarity can be configured by
setting accordingly the ESB bit of the Interrupt Op-
tion Register (IOR).
When an interrupt source generates an interrupt
request, and interrupt processing is enabled, the
PC register is loaded with the address of the inter-
rupt vector (i.e. of the Jump instruction), which
then causes a Jump to the relevant interrupt serv-
ice routine, thus servicing the interrupt.
Interrupt request from sources #3 & #4 are level
sensitive.
In edge sensitive mode, a latch is set when a edge
occurs on the interrupt source line and is cleared
when the associated interrupt routine is started.
So, the occurrence of an interrupt can be stored,
until completion of the running interrupt routine be-
fore being processed. If several interrupt requests
occurs before completion of the running interrupt
routine, only the first request is stored.
Interrupt sources are linked to events either on ex-
ternal pins, or on chip peripherals. Several events
can be ORed on the same interrupt source, and
relevant flags are available to determine which
event triggered the interrupt.
The Non Maskable Interrupt request has the high-
est priority and can interrupt any interrupt routine
at any time; the other four interrupts cannot inter-
rupt each other. If more than one interrupt request
is pending, these are processed by the processor
core according to their priority level: source #1 has
the higher priority while source #4 the lower. The
priority of each interrupt source is fixed.
Storage of interrupt requests is not available in lev-
el sensitive mode. To be taken into account, the
low level must be present on the interrupt pin when
the MCU samples the line after instruction execu-
tion.
At the end of every instruction, the MCU tests the
interrupt lines: if there is an interrupt request the
next instruction is not executed and the appropri-
ate interrupt service routine is executed instead.
Table 7. Interrupt Vector Map
Interrupt Source
Interrupt source #0
Interrupt source #1
Interrupt source #2
Interrupt source #3
Interrupt source #4
Priority
Vector Address
(FFCh-FFDh)
(FF6h-FF7h)
(FF4h-FF5h)
(FF2h-FF3h)
(FF0h-FF1h)
1
2
3
4
5
Table 8. Interrupt Option Register Description
SET
Enable all interrupts
Disable all interrupts
GEN
CLEARED
Rising edge mode on inter-
rupt source #2
SET
ESB
3.4.1 Interrupt request
Falling edge mode on inter-
rupt source #2
CLEARED
SET
All interrupt sources but the Non Maskable Inter-
rupt source can be disabled by setting accordingly
the GEN bit of the Interrupt Option Register (IOR).
This GEN bit also defines if an interrupt source, in-
cluding the Non Maskable Interrupt source, can re-
start the MCU from STOP/WAIT modes.
Level-sensitive mode on in-
terrupt source #1
LES
Falling edge mode on inter-
rupt source #1
CLEARED
NOT USED
OTHERS
Interrupt request from the Non Maskable Interrupt
source #0 is latched by a flip flop which is automat-
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ST62T08C/T09C ST62T10C/T20C/E20C
INTERRUPTS (Cont’d)
3.4.2 Interrupt Procedure
MCU
– Automatically the MCU switches back to the nor-
mal flag set (or the interrupt flag set) and pops
the previous PC value from the stack.
The interrupt procedure is very similar to a call pro-
cedure, indeed the user can consider the interrupt
as an asynchronous call procedure. As this is an
asynchronous event, the user cannot know the
context and the time at which it occurred. As a re-
sult, the user should save all Data space registers
which may be used within the interrupt routines.
There are separate sets of processor flags for nor-
mal, interrupt and non-maskable interrupt modes,
which are automatically switched and so do not
need to be saved.
The interrupt routine usually begins by the identify-
ing the device which generated the interrupt re-
quest (by polling). The user should save the regis-
ters which are used within the interrupt routine in a
software stack. After the RETI instruction is exe-
cuted, the MCU returns to the main routine.
Figure 20. Interrupt Processing Flow Chart
The following list summarizes the interrupt proce-
dure:
INSTRUCTION
MCU
FETCH
– The interrupt is detected.
INSTRUCTION
– The C and Z flags are replaced by the interrupt
flags (or by the NMI flags).
– The PC contents are stored in the first level of
the stack.
EXECUTE
INSTRUCTION
– The normal interrupt lines are inhibited (NMI still
active).
– The first internal latch is cleared.
LOAD PC FROM
NO
INTERRUPT VECTOR
WAS
(FFC/FFD)
THE INSTRUCTION
A RETI ?
–TheassociatedinterruptvectorisloadedinthePC.
YES
?
IS THE CORE
ALREADY IN
NORMAL MODE?
SET
WARNING: In some circumstances, when a
maskable interrupt occurs while the ST6 core is in
NORMAL mode and especially during the execu-
tion of an "ldi IOR, 00h" instruction (disabling all
maskable interrupts): if the interrupt arrives during
the first 3 cycles of the "ldi" instruction (which is a
4-cycle instruction) the core will switch to interrupt
mode BUT the flags CN and ZN will NOT switch to
the interrupt pair CI and ZI.
YES
INTERRUPT MASK
NO
CLEAR
INTERRUPT MASK
PUSH THE
PC INTO THE STACK
SELECT
PROGRAM FLAGS
SELECT
INTERNAL MODE FLAG
User
"POP"
– User selected registers are saved within the in-
terrupt service routine (normally on a software
stack).
THE STACKED PC
CHECK IF THERE IS
AN INTERRUPT REQUEST
AND INTERRUPT MASK
NO
– The source of the interrupt is found by polling the
interrupt flags (if more than one source is associ-
ated with the same vector).
?
YES
VA000014
– The interrupt is serviced.
– Return from interrupt (RETI)
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ST62T08C/T09C ST62T10C/T20C/E20C
INTERRUPTS (Cont’d)
3.4.3 Interrupt Option Register (IOR)
Bit 5 = ESB: Edge Selection bit.
The Interrupt Option Register (IOR) is used to en-
able/disable the individual interrupt sources and to
select the operating mode of the external interrupt
inputs. This register is write-only and cannot be
accessed by single-bit operations.
The bit ESB selects the polarity of the interrupt
source #2.
Global Enable Interrupt
Bit 4 = GEN:
. When this bit
is set to one, all interrupts are enabled. When this
bit is cleared to zero all the interrupts (excluding
NMI) are disabled.
Address: 0C8h
—
Write Only
Reset status: 00h
When the GEN bit is low, the NMI interrupt is ac-
tive but cannot cause a wake up from STOP/WAIT
modes.
7
-
0
-
This register is cleared on reset.
LES ESB GEN
-
-
-
3.4.4 Interrupt Sources
Interrupt sources available on the ST62E20C/
T20C are summarized in the Table 9 with associ-
ated mask bit to enable/disable the interrupt re-
quest.
Unused
Bit 7, Bits 3-0 =
.
Level/Edge Selection bit
Bit 6 = LES:
.
When this bit is set to one, the interrupt source #1
is level sensitive. When cleared to zero the edge
sensitive mode for interrupt request is selected.
Table 9. Interrupt Requests and Mask Bits
Address
Interrupt
vector
Peripheral
Register
Mask bit
Masked Interrupt Source
Register
C8h
All Interrupts, excluding
GENERAL
IOR
GEN
I
NM
TIMER
TSCR
D4h
ETI
EAI
TMZ: TIMER Overflow
EOC: End of Conversion
Vector 3
Vector 4
Vector 1
Vector 2
A/D CONVERTER(*) ADCR
D1h
Port PAn
Port PBn
ORPA-DRPA
ORPB-DRPB
C4h-CCh
C5h-CDh
ORPAn-DRPAn PAn pin
ORPBn-DRPBn PBn pin
*Except ST62T08C
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ST62T08C/T09C ST62T10C/T20C/E20C
INTERRUPTS (Cont’d)
Figure 21. Interrupt Block Diagram
V
DD
FF
INT #0 - NMI (FFC,D)
NMI
CLK
CLK
Q
Q
CLR
I
Start
0
FF
0
PBE
PORT A
CLR
INT #1 (FF6,7)
MUX
FROM REGISTER
SINGLE BIT ENABLE
PORT A,B
I Start
1
1
PBE
RESTART FROM
STOP/WAIT
IOR REG. C8H, bit 6
V
DD
PORT B
Bits
PBE
PBE
FF
INT #2 (FF4,5)
CLK
CLR
Q
IOR REG. C8H, bit 5
I Start
2
TMZ
ETI
INT #3 (FF2,3)
INT #4 (FF0,1)
TIMER
ADC(*)
EAI
EOC
GEN
VA0426T
(*)Except on ST62T08C
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ST62T08C/T09C ST62T10C/T20C/E20C
3.5 POWER SAVING MODES
The WAIT and STOP modes have been imple-
mented in the ST62xx family of MCUs in order to
reduce the product’s electrical consumption during
idle periods. These two power saving modes are
described in the following paragraphs.
If the WAIT mode is exited due to a Reset (either
by activating the external pin or generated by the
Watchdog), the MCU enters a normal reset proce-
dure. If an interrupt is generated during WAIT
mode, the MCU’s behaviour depends on the state
of the processor core prior to the WAIT instruction,
but also on the kind of interrupt request which is
generated. This is described in the following para-
graphs. The processor core does not generate a
delay following the occurrence of the interrupt, be-
cause the oscillator clock is still available and no
stabilisation period is necessary.
In addition, the Low Frequency Auxiliary Oscillator
(LFAO) can be used instead of the main oscillator
to reduce power consumption in RUN and WAIT
modes.
3.5.1 WAIT Mode
The MCU goes into WAIT mode as soon as the
WAIT instruction is executed. The microcontroller
can be considered as being in a “software frozen”
state where the core stops processing the pro-
gram instructions, the RAM contents and peripher-
al registers are preserved as long as the power
supply voltage is higher than the RAM retention
voltage. In this mode the peripherals are still ac-
tive.
3.5.2 STOP Mode
If the Watchdog is disabled, STOP mode is availa-
ble. When in STOP mode, the MCU is placed in
the lowest power consumption mode. In this oper-
ating mode, the microcontroller can be considered
as being “frozen”, no instruction is executed, the
oscillator is stopped, the RAM contents and pe-
ripheral registers are preserved as long as the
power supply voltage is higher than the RAM re-
tention voltage, and the ST62xx core waits for the
occurrence of an external interrupt request or a
Reset to exit the STOP state.
WAIT mode can be used when the user wants to
reduce the MCU power consumption during idle
periods, while not losing track of time or the capa-
bility of monitoring external events. The active os-
cillator (main oscillator or LFAO) is not stopped in
order to provide a clock signal to the peripherals.
Timer counting may be enabled as well as the
Timer interrupt, before entering the WAIT mode:
this allows the WAIT mode to be exited when a
Timer interrupt occurs. The same applies to other
peripherals which use the clock signal.
If the STOP state is exited due to a Reset (by acti-
vating the external pin) the MCU will enter a nor-
mal reset procedure. Behaviour in response to in-
terrupts depends on the state of the processor
core prior to issuing the STOP instruction, and
also on the kind of interrupt request that is gener-
ated.
If the power consumption has to be further re-
duced, the Low Frequency Auxiliary Oscillator
(LFAO) can be used in place of the main oscillator,
if its operating frequency is lower. If required, the
LFAO must be switched on before entering the
WAIT mode.
This case will be described in the following para-
graphs. The processor core generates a delay af-
ter occurrence of the interrupt request, in order to
wait for complete stabilisation of the oscillator, be-
fore executing the first instruction.
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ST62T08C/T09C ST62T10C/T20C/E20C
POWER SAVING MODE (Cont’d)
3.5.3 Exit from WAIT and STOP Modes
tered will be completed, starting with the
execution of the instruction which follows the
STOP or the WAIT instruction, and the MCU is
still in the interrupt mode. At the end of this rou-
tine pending interrupts will be serviced in accord-
ance with their priority.
The following paragraphs describe how the MCU
exits from WAIT and STOP modes, when an inter-
rupt occurs (not a Reset). It should be noted that
the restart sequence depends on the original state
of the MCU (normal, interrupt or non-maskable in-
terrupt mode) prior to entering WAIT or STOP
mode, as well as on the interrupt type.
– In the event of a non-maskable interrupt, the
non-maskable interrupt service routine is proc-
essed first, then the routine in which the WAIT or
STOP mode was entered will be completed by
executing the instruction following the STOP or
WAIT instruction. The MCU remains in normal in-
terrupt mode.
Interrupts do not affect the oscillator selection,
consequently, when the LFAO is used, the user
program must manage oscillator selection as soon
as normal RUN mode is resumed.
3.5.3.1 Normal Mode
Notes:
If the MCU was in the main routine when the WAIT
or STOP instruction was executed, exit from Stop
or Wait mode will occur as soon as an interrupt oc-
curs; the related interrupt routine is executed and,
on completion, the instruction which follows the
STOP or WAIT instruction is then executed, pro-
viding no other interrupts are pending.
To achieve the lowest power consumption during
RUN or WAIT modes, the user program must take
care of:
– configuring unused I/Os as inputs without pull-up
(these should be externally tied to well defined
logic levels);
3.5.3.2 Non Maskable Interrupt Mode
– placing all peripherals in their power down
modes before entering STOP mode;
If the STOP or WAIT instruction has been execut-
ed during execution of the non-maskable interrupt
routine, the MCU exits from the Stop or Wait mode
as soon as an interrupt occurs: the instruction
which follows the STOP or WAIT instruction is ex-
ecuted, and the MCU remains in non-maskable in-
terrupt mode, even if another interrupt has been
generated.
– selecting the Low Frequency Auxiliary Oscillator
(provided this runs at a lower frequency than the
main oscillator).
When the hardware activated Watchdog is select-
ed, or when the software Watchdog is enabled, the
STOP instruction is disabled and a WAIT instruc-
tion will be executed in its place.
3.5.3.3 Normal Interrupt Mode
If all interrupt sources are disabled (GEN low), the
MCU can only be restarted by a Reset. Although
setting GEN low does not mask the NMI as an in-
terrupt, it will stop it generating a wake-up signal.
If the MCU was in interrupt mode before the STOP
or WAIT instruction was executed, it exits from
STOP or WAIT mode as soon as an interrupt oc-
curs. Nevertheless, two cases must be consid-
ered:
The WAIT and STOP instructions are not execut-
ed if an enabled interrupt request is pending.
– If the interrupt is a normal one, the interrupt rou-
tine in which the WAIT or STOP mode was en-
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ST62T08C/T09C ST62T10C/T20C/E20C
4 ON-CHIP PERIPHERALS
4.1 I/O PORTS
The MCU features Input/Output lines which may
be individually programmed as any of the following
input or output configurations:
be also written by user software, in conjunction
with the related option registers, to select the dif-
ferent input mode options.
– Input without pull-up or interrupt
– Input with pull-up and interrupt
– Input with pull-up, but without interrupt
– Analog input
Single-bit operations on I/O registers are possible
but care is necessary because reading in input
mode is done from I/O pins while writing will direct-
ly affect the Port data register causing an unde-
sired change of the input configuration.
The Data Direction registers (DDRx) allow the
data direction (input or output) of each pin to be
set.
– Push-pull output
– Open drain output
The lines are organised as bytewise Ports.
The Option registers (ORx) are used to select the
different port options available both in input and in
output mode.
Each port is associated with 3 registers in Data
space. Each bit of these registers is associated
with a particular line (for instance, bits 0 of Port A
Data, Direction and Option registers are associat-
ed with the PA0 line of Port A).
All I/O registers can be read or written to just as
any other RAM location in Data space, so no extra
RAM cells are needed for port data storage and
manipulation. During MCU initialization, all I/O reg-
isters are cleared and the input mode with pull-ups
and no interrupt generation is selected for all the
pins, thus avoiding pin conflicts.
The DATA registers (DRx), are used to read the
voltage level values of the lines which have been
configured as inputs, or to write the logic value of
the signal to be output on the lines configured as
outputs. The port data registers can be read to get
the effective logic levels of the pins, but they can
Figure 22. I/O Port Block Diagram
RESET
V
DD
S
CONTROLS
IN
DATA
DIRECTION
REGISTER
V
DD
INPUT/OUTPUT
DATA
REGISTER
SHIFT
REGISTER
OPTION
REGISTER
S
OUT
TO INTERRUPT
TO ADC
VA00413
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ST62T08C/T09C ST62T10C/T20C/E20C
4.1.1.2 Interrupt Options
I/O PORTS (Cont’d)
4.1.1 Operating Modes
Each pin may be individually programmed as input
or output with various configurations.
All input lines can be individually connected by
software to the interrupt system by programming
the OR and DR registers accordingly. The inter-
rupt trigger modes (falling edge, rising edge and
low level) can be configured by software as de-
scribed in the Interrupt Chapter for each port.
This is achieved by writing the relevant bit in the
Data (DR), Data Direction (DDR) and Option reg-
isters (OR). Table 10 illustrates the various port
configurations which can be selected by user soft-
ware.
4.1.1.3 Analog Input Options
4.1.1.1 Input Options
Some pins can be configured as analog inputs by
programming the OR and DR registers according-
ly. These analog inputs are connected to the on-
Pull-up, High Impedance Option. All input lines
can be individually programmed with or without an
internal pull-up by programming the OR and DR
registers accordingly. If the pull-up option is not
selected, the input pin will be in the high-imped-
ance state.
ONLY ONE
chip 8-bit Analog to Digital Converter.
pin should be programmed as an analog input at
any time, since by selecting more than one input
simultaneously their pins will be effectively short-
ed.
Table 10. I/O Port Option Selection
DDR
OR
0
DR
0
Mode
Input
Option
0
0
0
0
1
1
With pull-up, no interrupt
0
1
Input
No pull-up, no interrupt
1
0
Input
With pull-up and with interrupt
1
1
Input
Analog input (when available)
0
X
X
Output
Output
Open-drain output (20mA sink when available)
Push-pull output (20mA sink when available)
1
Note: X = Don’t care
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ST62T08C/T09C ST62T10C/T20C/E20C
I/O PORTS (Cont’d)
4.1.2 Safe I/O State Switching Sequence
outputs, it is advisable to keep a copy of the data
register in RAM. Single bit instructions may then
be used on the RAM copy, after which the whole
copy register can be written to the port data regis-
ter:
Switching the I/O ports from one state to another
should be done in a sequence which ensures that
no unwanted side effects can occur. The recom-
mended safe transitions are illustrated in Figure
23. All other transitions are potentially risky and
should be avoided when changing the I/O operat-
ing mode, as it is most likely that undesirable side-
effects will be experienced, such as spurious inter-
rupt generation or two pins shorted together by the
analog multiplexer.
SET bit, datacopy
LD a, datacopy
LD DRA, a
Warning: Care must also be taken to not use in-
structions that act on a whole port register (INC,
DEC, or read operations) when all 8 bits are not
available on the device. Unavailable bits must be
masked by software (AND instruction).
Single bit instructions (SET, RES, INC and DEC)
should be used with great caution on Ports Data
registers, since these instructions make an implicit
read and write back of the entire register. In port
input mode, however, the data register reads from
the input pins directly, and not from the data regis-
ter latches. Since data register information in input
mode is used to set the characteristics of the input
pin (interrupt, pull-up, analog input), these may be
unintentionally reprogrammed depending on the
state of the input pins. As a general rule, it is better
to limit the use of single bit instructions on data
registers to when the whole (8-bit) port is in output
mode. In the case of inputs or of mixed inputs and
The WAIT and STOP instructions allow the
ST62xx to be used in situations where low power
consumption is needed. The lowest power con-
sumption is achieved by configuring I/Os in input
mode with well-defined logic levels.
The user must take care not to switch outputs with
heavy loads during the conversion of one of the
analog inputs in order to avoid any disturbance to
the conversion.
Figure 23. Diagram showing Safe I/O State Transitions
Interrupt
pull-up
Input
Analog
010*
011
001
Input
pull-up (Reset
state)
000
100
Input
Output
Open Drain
Output
Open Drain
101
111
Output
Push-pull
Output
Push-pull
110
Note *. xxx = DDR, OR, DR Bits respectively
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ST62T08C/T09C ST62T10C/T20C/E20C
I/O PORTS (Cont’d)
4.1.3 I/O Port Option Registers
ORA/B (CCh PA, CDh PB) Read/Write
4.1.5 I/O Port Data Registers
DRA/B (C0h PA, C1h PB) Read/Write
7
0
7
0
Px7
Px6
Px5
Px4
Px3
Px2
Px1
Px0
Px7
Px6
Px5
Px4
Px3
Px2
Px1
Px0
Port A and B Option Register
Bit 7-0 = Px7 - Px0:
bits.
Bit 7-0 =
bits.
:
Px7 - Px0 Port A and B Data Registers
Note: X = Don’t care
4.1.4 I/O Port Data Direction Registers
DDRA/B (C4h PA, C5h PB) Read/Write
7
0
Px7
Px6
Px5
Px4
Px3
Px2
Px1
Px0
Port A and B Data Direction
Bit 7-0 = Px7 - Px0:
Registers bits.
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ST62T08C/T09C ST62T10C/T20C/E20C
I/O PORTS (Cont’d)
Table 11. I/O Port Option Selections
MODE
AVAILABLE ON(1)
SCHEMATIC
PA0-PA3
Input
PB0-PB7
Data in
Interrupt
PA0-PA3
PB0-PB7
Input
Data in
with pull up
Interrupt
Input
PA0-PA3
PB0-PB7
with pull up
with interrupt
Data in
Interrupt
PB0-PB3
(ST62T10C,T20C,E20C)
Analog Input
PB4-PB7
ADC
(All except ST62T08C)
Open drain output
5mA
PB0-PB7
PA0-PA3
Data out
Open drain output
20mA
Push-pull output
5mA
PB0-PB7
PA0-PA3
Data out
Push-pull output
20mA
Note 1. Provided the correct configuration has been selected.
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ST62T08C/T09C ST62T10C/T20C/E20C
4.2 TIMER
The MCU features an on-chip Timer peripheral,
consisting of an 8-bit counter with a 7-bit program-
mable prescaler, giving a maximum count of 2 .
The peripheral may be configured in three different
operating modes.
The prescaler input can be the internal frequency
f
divided by 12 or an external clock applied to
INT
15
the TIMER pin. The prescaler decrements on the
rising edge. Depending on the division factor pro-
grammed by PS2, PS1 and PS0 bits in the TSCR.
The clock input of the timer/counter register is mul-
tiplexed to different sources. For division factor 1,
the clock input of the prescaler is also that of timer/
counter; for factor 2, bit 0 of the prescaler register
is connected to the clock input of TCR. This bit
changes its state at half the frequency of the pres-
caler input clock. For factor 4, bit 1 of the PSC is
connected to the clock input of TCR, and so forth.
The prescaler initialize bit, PSI, in the TSCR regis-
ter must be set to “1” to allow the prescaler (and
hence the counter) to start. If it is cleared to “0”, all
the prescaler bits are set to “1” and the counter is
inhibited from counting. The prescaler can be
loaded with any value between 0 and 7Fh, if bit
PSI is set to “1”. The prescaler tap is selected by
means of the PS2/PS1/PS0 bits in the control reg-
ister.
Figure 24 shows the Timer Block Diagram. The
external TIMER pin is available to the user. The
content of the 8-bit counter can be read/written in
the Timer/Counter register, TCR, while the state of
the 7-bit prescaler can be read in the PSC register.
The control logic device is managed in the TSCR
register as described in the following paragraphs.
The 8-bit counter is decremented by the output
(rising edge) coming from the 7-bit prescaler and
can be loaded and read under program control.
When it decrements to zero then the TMZ (Timer
Zero) bit in the TSCR is set to “1”. If the ETI (Ena-
ble Timer Interrupt) bit in the TSCR is also set to
“1”, an interrupt request is generated as described
in the Interrupt Chapter. The Timer interrupt can
be used to exit the MCU from WAIT mode.
Figure 25 illustrates the Timer’s working principle.
Figure 24. Timer Block Diagram
DATABUS 8
8
8
8
6
5
4
3
2
b1
b7
b6
b5
b4
b3
b2
b0
8-BIT
COUNTER
STATUS/CONTROL
REGISTER
SELECT
1 OF 7
PSC
TMZ ETI TOUT
PSI
PS1
PS0
DOUT
PS2
1
0
3
TIMER
INTERRUPT
LINE
LATCH
SYNCHRONIZATION
LOGIC
:12
fOSC
VA00009
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ST62T08C/T09C ST62T10C/T20C/E20C
TIMER (Cont’d)
4.2.1 Timer Operating Modes
The user can select the desired prescaler division
ratio through the PS2, PS1, PS0 bits. When the
TCR count reaches 0, it sets the TMZ bit in the
TSCR. The TMZ bit can be tested under program
control to perform a timer function whenever it
goes high. The low-to-high TMZ bit transition is
used to latch the DOUT bit of the TSCR and trans-
fer it to the TIMER pin. This operating mode allows
external signal generation on the TIMER pin.
There are three operating modes, which are se-
lected by the TOUT and DOUT bits (see TSCR
register). These three modes correspond to the
two clocks which can be connected to the 7-bit
prescaler (f
the output mode.
÷ 12 or TIMER pin signal), and to
INT
4.2.1.1 Gated Mode
(TOUT = “0”, DOUT = “1”)
In this mode the prescaler is decremented by the
Table 12. Timer Operating Modes
TOUT
DOUT
Timer Pin
Input
Timer Function
Event Counter
Gated Input
Output “0”
Timer clock input (f
÷ 12), but ONLY when the
INT
signal on the TIMER pin is held high (allowing
pulse width measurement). This mode is selected
by clearing the TOUT bit in the TSCR register to
“0” (i.e. as input) and setting the DOUT bit to “1”.
0
0
1
1
0
1
0
1
Input
Output
Output
Output “1”
4.2.1.2 Event Counter Mode
(TOUT = “0”, DOUT = “0”)
4.2.2 Timer Interrupt
In this mode, the TIMER pin is the input clock of
the prescaler which is decremented on the rising
edge.
When the counter register decrements to zero with
the ETI (Enable Timer Interrupt) bit set to one, an
interrupt request is generated as described in the
Interrupt Chapter. When the counter decrements
to zero, the TMZ bit in the TSCR register is set to
one.
4.2.1.3 Output Mode
(TOUT = “1”, DOUT = data out)
The TIMER pin is connected to the DOUT latch,
hence the Timer prescaler is clocked by the pres-
caler clock input (f
÷ 12).
INT
Figure 25. Timer Working Principle
7-BIT PRESCALER
BIT0
BIT1
BIT2
BIT3
BIT4
BIT5
BIT6
CLOCK
PS0
PS1
PS2
2
0
1
3
4
6
7
5
8-1 MULTIPLEXER
BIT7
BIT2
BIT0
BIT1
BIT3
BIT4
BIT5
BIT6
8-BIT COUNTER
VA00186
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ST62T08C/T09C ST62T10C/T20C/E20C
TIMER (Cont’d)
4.2.3 Application Notes
Bit 4 = DOUT: Data Output
Data sent to the timer output when TMZ is set high
(output mode only). Input mode selection (input
mode only).
The user can select the presence of an on-chip
pull-up on the TIMER pin as option.
TMZ is set when the counter reaches zero; howev-
er, it may also be set by writing 00h in the TCR
register or by setting bit 7 of the TSCR register.
The TMZ bit must be cleared by user software
when servicing the timer interrupt to avoid unde-
sired interrupts when leaving the interrupt service
routine. After reset, the 8-bit counter register is
loaded with 0FFh, while the 7-bit prescaler is load-
ed with 07Fh, and the TSCR register is cleared.
This means that the Timer is stopped (PSI=“0”)
and the timer interrupt is disabled.
Prescaler Initialize Bit
Bit 3 = PSI:
Used to initialize the prescaler and inhibit its count-
ing. When PSI=“0” the prescaler is set to 7Fh and
the counter is inhibited. When PSI=“1” the prescal-
er is enabled to count downwards. As long as
PSI=“0” both counter and prescaler are not run-
ning.
Prescaler Mux. Se-
Bit 2, 1, 0 = PS2, PS1, PS0:
lect.
These bits select the division ratio of the pres-
caler register.
If the Timer is programmed in output mode, the
DOUT bit is transferred to the TIMER pin when
TMZ is set to one (by software or due to counter
decrement). When TMZ is high, the latch is trans-
parent and DOUT is copied to the timer pin. When
TMZ goes low, DOUT is latched.
Table 13. Prescaler Division Factors
PS2
0
PS1
0
PS0
0
Divided by
1
2
0
0
1
0
1
0
4
A write to the TCR register will predominate over
the 8-bit counter decrement to 00h function, i.e. if a
write and a TCR register decrement to 00h occur
simultaneously, the write will take precedence,
and the TMZ bit is not set until the 8-bit counter
reaches 00h again. The values of the TCR and the
PSC registers can be read accurately at any time.
0
1
1
8
1
0
0
16
32
64
128
1
0
1
1
1
0
1
1
1
4.2.4 Timer Registers
Timer Counter Register TCR
Timer Status Control Register (TSCR)
Address: 0D3h
—
Read/Write
Address: 0D4h
—
Read/Write
7
0
7
0
D7
D6
D5
D4
D3
D2
D1
D0
TMZ
ETI
TOUT DOUT PSI
PS2
PS1
PS0
Counter Bits.
Bit 7-0 = D7-D0:
Timer Zero bit
Bit 7 = TMZ:
A low-to-high transition indicates that the timer
count register has decrement to zero. This bit must
be cleared by user software before starting a new
count.
Prescaler Register PSC
Address: 0D2h
—
Read/Write
7
0
Enable Timer Interrupt
Bit 6 = ETI:
When set, enables the timer interrupt request
(vector #3). If ETI=0 the timer interrupt is disabled.
If ETI=1 and TMZ=1 an interrupt request is gener-
ated.
D7
D6
D5
D4
D3
D2
D1
D0
Bit 7 = D7: Always read as "0".
Bit 6-0 = D6-D0: Prescaler Bits.
Timers Output Control
Bit 5 = TOUT:
When low, this bit selects the input mode for the
TIMER pin. When high the output mode is select-
ed.
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ST62T08C/T09C ST62T10C/T20C/E20C
4.3 A/D CONVERTER (ADC)
The A/D converter peripheral is an 8-bit analog to
digital converter with analog inputs as alternate I/O
functions (the number of which is device depend-
ent), offering 8-bit resolution with a typical conver-
sion time of 70us (at an oscillator clock frequency
of 8MHz).
sion to allow stabilisation of the A/D converter.
This action is also needed before entering WAIT
mode, since the A/D comparator is not automati-
cally disabled in WAIT mode.
During Reset, any conversion in progress is
stopped, the control register is reset to 40h and the
ADC interrupt is masked (EAI=0).
The ADC converts the input voltage by a process
of successive approximations, using a clock fre-
quency derived from the oscillator with a division
factor of twelve. With an oscillator clock frequency
less than 1.2MHz, conversion accuracy is de-
creased.
Figure 26. ADC Block Diagram
INTERRUPT
CLOCK
Selection of the input pin is done by configuring
the related I/O line as an analog input via the Op-
tion and Data registers (refer to I/O ports descrip-
tion for additional information). Only one I/O line
must be configured as an analog input at any time.
The user must avoid any situation in which more
than one I/O pin is selected as an analog input si-
multaneously, to avoid device malfunction.
Ain
CONVERTER
RESET
AV
AV
DD
SS
RESULT REGISTER
8
CONTROL REGISTER
8
The ADC uses two registers in the data space: the
ADC data conversion register, ADR, which stores
the conversion result, and the ADC control regis-
ter, ADCR, used to program the ADC functions.
CORE
CORE
CONTROL SIGNALS
VA00418
A conversion is started by writing a “1” to the Start
bit (STA) in the ADC control register. This auto-
matically clears (resets to “0”) the End Of Conver-
sion Bit (EOC). When a conversion is complete,
the EOC bit is automatically set to “1”, in order to
flag that conversion is complete and that the data
in the ADC data conversion register is valid. Each
conversion has to be separately initiated by writing
to the STA bit.
4.3.1 Application Notes
The A/D converter does not feature a sample and
hold circuit. The analog voltage to be measured
should therefore be stable during the entire con-
version cycle. Voltage variation should not exceed
±1/2 LSB for the optimum conversion accuracy. A
low pass filter may be used at the analog input
pins to reduce input voltage variation during con-
version.
The STA bit is continuously scanned so that, if the
user sets it to “1” while a previous conversion is in
progress, a new conversion is started before com-
pleting the previous one. The start bit (STA) is a
write only bit, any attempt to read it will show a log-
ical “0”.
When selected as an analog channel, the input pin
is internally connected to a capacitor C of typi-
ad
cally 12pF. For maximum accuracy, this capacitor
must be fully charged at the beginning of conver-
sion. In the worst case, conversion starts one in-
struction (6.5 µs) after the channel has been se-
lected. In worst case conditions, the impedance,
ASI, of the analog voltage source is calculated us-
ing the following formula:
The A/D converter features a maskable interrupt
associated with the end of conversion. This inter-
rupt is associated with interrupt vector #4 and oc-
curs when the EOC bit is set (i.e. when a conver-
sion is completed). The interrupt is masked using
the EAI (interrupt mask) bit in the control register.
6.5µs = 9 x C x ASI
ad
Ω
(capacitor charged to over 99.9%), i.e. 30 k in-
cluding a 50% guardband. ASI can be higher if C
has been charged for a longer period by adding in-
structions before the start of conversion (adding
more than 26 CPU cycles is pointless).
The power consumption of the device can be re-
duced by turning off the ADC peripheral. This is
done by setting the PDS bit in the ADC control reg-
ister to “0”. If PDS=“1”, the A/D is powered and en-
abled for conversion. This bit must be set at least
one instruction before the beginning of the conver-
ad
40/70
128
ST62T08C/T09C ST62T10C/T20C/E20C
A/D CONVERTER (Cont’d)
Since the ADC is on the same chip as the micro-
processor, the user should not switch heavily load-
ed output signals during conversion, if high preci-
sion is required. Such switching will affect the sup-
ply voltages used as analog references.
up the microcontroller could also be done using
the Timer interrupt, but in this case the Timer will
be working and the resulting noise could affect
conversion accuracy.
A/D Converter Control Register (ADCR)
Address: 0D1h
—
Read/Write
7
0
lated reference voltage is present on the V and
DD
EAI
EOC
STA
PDS
D3
D2
D1
D0
V
pins (power supply voltage variations must be
less than 5V/ms). This implies, in particular, that a
SS
suitable decoupling capacitor is used at the V
pin.
DD
Enable A/D Interrupt.
“1” the A/D interrupt is enabled, when EAI=0 the
interrupt is disabled.
Bit 7 = EAI:
If this bit is set to
The converter resolution is given by::
End of conversion. Read Only
Bit 6 = EOC:
. This
read only bit indicates when a conversion has
been completed. This bit is automatically reset to
“0” when the STA bit is written. If the user is using
the interrupt option then this bit can be used as an
interrupt pending bit. Data in the data conversion
register are valid only when this bit is set to “1”.
V
DD – VSS
---------------------------
256
The Input voltage (Ain) which is to be converted
must be constant for 1µs before conversion and
remain constant during conversion.
: Start of Conversion. Write Only
. Writ-
Bit 5 = STA
ing a “1” to this bit will start a conversion on the se-
lected channel and automatically reset to “0” the
EOC bit. If the bit is set again when a conversion is
in progress, the present conversion is stopped and
a new one will take place. This bit is write only, any
attempt to read it will show a logical zero.
Conversion resolution can be improved if the pow-
er supply voltage (V ) to the microcontroller is
DD
lowered.
In order to optimise conversion resolution, the user
can configure the microcontroller in WAIT mode,
because this mode minimises noise disturbances
and power supply variations due to output switch-
ing. Nevertheless, the WAIT instruction should be
executed as soon as possible after the beginning
of the conversion, because execution of the WAIT
: Power Down Selection.
Bit 4 = PDS
This bit acti-
vates the A/D converter if set to “1”. Writing a “0” to
this bit will put the ADC in power down mode (idle
mode).
Bit 3-0 = D3-D0. Not used
instruction may cause a small variation of the V
DD
voltage. The negative effect of this variation is min-
imized at the beginning of the conversion when the
converter is less sensitive, rather than at the end
of conversion, when the less significant bits are
determined.
A/D Converter Data Register (ADR)
Address: 0D0h
—
Read only
7
0
The best configuration, from an accuracy stand-
point, is WAIT mode with the Timer stopped. In-
deed, only the ADC peripheral and the oscillator
are then still working. The MCU must be woken up
from WAIT mode by the ADC interrupt at the end
of the conversion. It should be noted that waking
D7
D6
D5
D4
D3
D2
D1
D0
: 8 Bit A/D Conversion Result.
Bit 7-0 = D7-D0
41/70
129
ST62T08C/T09C ST62T10C/T20C/E20C
5 SOFTWARE
5.1 ST6 ARCHITECTURE
The ST6 software has been designed to fully use
the hardware in the most efficient way possible
while keeping byte usage to a minimum; in short,
to provide byte efficient programming capability.
The ST6 core has the ability to set or clear any
register or RAM location bit of the Data space with
a single instruction. Furthermore, the program
may branch to a selected address depending on
the status of any bit of the Data space. The carry
bit is stored with the value of the bit when the SET
or RES instruction is processed.
bits of the opcode with the byte following the op-
code. The instructions (JP, CALL) which use the
extended addressing mode are able to branch to
any address of the 4K bytes Program space.
An extended addressing mode instruction is two-
byte long.
Program Counter Relative. The relative address-
ing mode is only used in conditional branch in-
structions. The instruction is used to perform a test
and, if the condition is true, a branch with a span of
-15 to +16 locations around the address of the rel-
ative instruction. If the condition is not true, the in-
struction which follows the relative instruction is
executed. The relative addressing mode instruc-
tion is one-byte long. The opcode is obtained in
adding the three most significant bits which char-
acterize the kind of the test, one bit which deter-
mines whether the branch is a forward (when it is
0) or backward (when it is 1) branch and the four
less significant bits which give the span of the
branch (0h to Fh) which must be added or sub-
tracted to the address of the relative instruction to
obtain the address of the branch.
5.2 ADDRESSING MODES
The ST6 core offers nine addressing modes,
which are described in the following paragraphs.
Three different address spaces are available: Pro-
gram space, Data space, and Stack space. Pro-
gram space contains the instructions which are to
be executed, plus the data for immediate mode in-
structions. Data space contains the Accumulator,
the X,Y,V and W registers, peripheral and Input/
Output registers, the RAM locations and Data
ROM locations (for storage of tables and con-
stants). Stack space contains six 12-bit RAM cells
used to stack the return addresses for subroutines
and interrupts.
Bit Direct. In the bit direct addressing mode, the
bit to be set or cleared is part of the opcode, and
the byte following the opcode points to the ad-
dress of the byte in which the specified bit must be
set or cleared. Thus, any bit in the 256 locations of
Data space memory can be set or cleared.
Immediate. In the immediate addressing mode,
the operand of the instruction follows the opcode
location. As the operand is a ROM byte, the imme-
diate addressing mode is used to access con-
stants which do not change during program execu-
tion (e.g., a constant used to initialize a loop coun-
ter).
Bit Test & Branch. The bit test and branch ad-
dressing mode is a combination of direct address-
ing and relative addressing. The bit test and
branch instruction is three-byte long. The bit iden-
tification and the tested condition are included in
the opcode byte. The address of the byte to be
tested follows immediately the opcode in the Pro-
gram space. The third byte is the jump displace-
ment, which is in the range of -127 to +128. This
displacement can be determined using a label,
which is converted by the assembler.
Direct. In the direct addressing mode, the address
of the byte which is processed by the instruction is
stored in the location which follows the opcode. Di-
rect addressing allows the user to directly address
the 256 bytes in Data Space memory with a single
two-byte instruction.
Short Direct. The core can address the four RAM
registers X,Y,V,W (locations 80h, 81h, 82h, 83h) in
the short-direct addressing mode. In this case, the
instruction is only one byte and the selection of the
location to be processed is contained in the op-
code. Short direct addressing is a subset of the di-
rect addressing mode. (Note that 80h and 81h are
also indirect registers).
Indirect. In the indirect addressing mode, the byte
processed by the register-indirect instruction is at
the address pointed by the content of one of the in-
direct registers, X or Y (80h,81h). The indirect reg-
ister is selected by the bit 4 of the opcode. A regis-
ter indirect instruction is one byte long.
Inherent. In the inherent addressing mode, all the
information necessary to execute the instruction is
contained in the opcode. These instructions are
one byte long.
Extended. In the extended addressing mode, the
12-bit address needed to define the instruction is
obtained by concatenating the four less significant
42/70
130
ST62T08C/T09C ST62T10C/T20C/E20C
5.3 INSTRUCTION SET
The ST6 core offers a set of 40 basic instructions
which, when combined with nine addressing
modes, yield 244 usable opcodes. They can be di-
vided into six different types: load/store, arithme-
tic/logic, conditional branch, control instructions,
jump/call, and bit manipulation. The following par-
agraphs describe the different types.
Load & Store. These instructions use one, two or
three bytes in relation with the addressing mode.
One operand is the Accumulator for LOAD and the
other operand is obtained from data memory using
one of the addressing modes.
For Load Immediate one operand can be any of
the 256 data space bytes while the other is always
immediate data.
All the instructions belonging to a given type are
presented in individual tables.
Table 14. Load & Store Instructions
Flags
Instruction
LD A, X
Addressing Mode
Short Direct
Bytes
Cycles
Z
C
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
1
1
1
1
1
1
1
1
2
2
1
1
1
1
2
3
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
∆
LD A, Y
LD A, V
LD A, W
LD X, A
LD Y, A
Short Direct
Short Direct
Short Direct
Short Direct
Short Direct
Short Direct
Short Direct
Direct
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
LD V, A
LD W, A
LD A, rr
LD rr, A
Direct
LD A, (X)
LD A, (Y)
LD (X), A
LD (Y), A
LDI A, #N
LDI rr, #N
Indirect
Indirect
Indirect
Indirect
∆
Immediate
Immediate
∆
*
Notes:
X,Y. Indirect Register Pointers, V & W Short Direct Registers
# . Immediate data (stored in ROM memory)
rr. Data space register
∆. Affected
* . Not Affected
43/70
131
ST62T08C/T09C ST62T10C/T20C/E20C
INSTRUCTION SET (Cont’d)
Arithmetic and Logic. These instructions are
used to perform the arithmetic calculations and
logic operations. In AND, ADD, CP, SUB instruc-
tions one operand is always the accumulator while
the other can be either a data space memory con-
tent or an immediate value in relation with the ad-
dressing mode. In CLR, DEC, INC instructions the
operand can be any of the 256 data space ad-
dresses. In COM, RLC, SLA the operand is always
the accumulator.
Table 15. Arithmetic & Logic Instructions
Flags
Instruction
ADD A, (X)
Addressing Mode
Indirect
Bytes
Cycles
Z
∆
∆
∆
∆
∆
∆
∆
∆
∆
*
C
∆
∆
∆
∆
∆
∆
∆
∆
∆
*
1
1
2
2
1
1
2
2
2
3
1
1
1
2
2
1
1
1
1
2
2
1
1
1
1
1
1
2
2
1
1
1
2
1
1
2
2
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
ADD A, (Y)
ADD A, rr
ADDI A, #N
AND A, (X)
AND A, (Y)
AND A, rr
ANDI A, #N
CLR A
Indirect
Direct
Immediate
Indirect
Indirect
Direct
Immediate
Short Direct
Direct
CLR r
COM A
Inherent
Indirect
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
*
CP A, (X)
CP A, (Y)
CP A, rr
CPI A, #N
DEC X
Indirect
Direct
Immediate
Short Direct
Short Direct
Short Direct
Short Direct
Direct
DEC Y
*
DEC V
*
DEC W
*
DEC A
*
DEC rr
Direct
*
DEC (X)
DEC (Y)
INC X
Indirect
*
Indirect
*
Short Direct
Short Direct
Short Direct
Short Direct
Direct
*
INC Y
*
INC V
*
INC W
*
INC A
*
INC rr
Direct
*
INC (X)
Indirect
*
INC (Y)
Indirect
*
RLC A
Inherent
Inherent
Indirect
∆
∆
∆
∆
∆
∆
SLA A
SUB A, (X)
SUB A, (Y)
SUB A, rr
SUBI A, #N
Indirect
Direct
Immediate
Notes:
X,Y.Indirect Register Pointers, V & W Short Direct RegistersD. Affected
# . Immediate data (stored in ROM memory)* . Not Affected
rr. Data space register
44/70
132
ST62T08C/T09C ST62T10C/T20C/E20C
INSTRUCTION SET (Cont’d)
Conditional Branch. The branch instructions
achieve a branch in the program when the select-
ed condition is met.
Control Instructions. The control instructions
control the MCU operations during program exe-
cution.
Bit Manipulation Instructions. These instruc-
tions can handle any bit in data space memory.
One group either sets or clears. The other group
(see Conditional Branch) performs the bit test
branch operations.
Jump and Call. These two instructions are used
to perform long (12-bit) jumps or subroutines call
inside the whole program space.
Table 16. Conditional Branch Instructions
Flags
Instruction
Branch If
Bytes
Cycles
Z
*
*
*
*
*
*
C
*
JRC e
C = 1
1
1
1
1
3
3
2
2
2
2
5
5
JRNC e
C = 0
Z = 1
*
JRZ e
*
JRNZ e
Z = 0
*
JRR b, rr, ee
JRS b, rr, ee
Bit = 0
Bit = 1
∆
∆
Notes
:
b.
e.
3-bit address
rr. Data space register
∆ . Affected. The tested bit is shifted into carry.
5 bit signed displacement in the range -15 to +16<F128M>
ee. 8 bit signed displacement in the range -126 to +129
* . Not Affected
Table 17. Bit Manipulation Instructions
Flags
Instruction
Addressing Mode
Bytes
Cycles
Z
C
*
SET b,rr
Bit Direct
Bit Direct
2
2
4
4
*
*
RES b,rr
*
Notes:
b.
3-bit address;
* . Not<M> Affected
rr. Data space register;
Table 18. Control Instructions
Flags
Instruction
Addressing Mode
Bytes
Cycles
Z
*
C
*
NOP
Inherent
Inherent
Inherent
Inherent
Inherent
1
1
1
1
1
2
2
2
2
2
RET
*
*
RETI
∆
*
∆
*
STOP (1)
WAIT
*
*
Notes:
1.
This instruction is deactivated<N>and a WAIT is automatically executed instead of a STOP if the watchdog function is selected.
∆ . Affected
*.
Not Affected
Table 19. Jump & Call Instructions
Instruction
Flags
Addressing Mode
Bytes
Cycles
Z
*
C
*
CALL abc
JP abc
Extended
Extended
2
2
4
4
*
*
Notes:
abc. 12-bit address;
* . Not Affected
45/70
133
ST62T08C/T09C ST62T10C/T20C/E20C
Opcode Map Summary. The following table contains an opcode map for the instructions used by the ST6
LOW
LOW
0
1
2
3
4
5
6
7
0000
0001
0010
0011
0100
0101
0110
0111
HI
HI
2
JRNZ 4
CALL 2
abc
ext 1
CALL 2
abc
ext 1
CALL 2
abc
ext 1
CALL 2
abc
ext 1
CALL 2
abc
ext 1
CALL 2
abc
ext 1
CALL 2
abc
ext 1
CALL 2
abc
ext 1
CALL 2
abc
ext 1
CALL 2
abc
ext 1
CALL 2
abc
ext 1
CALL 2
abc
ext 1
CALL 2
abc
ext 1
CALL 2
abc
ext 1
CALL 2
abc
ext 1
CALL 2
abc
JRNC 5
e
pcr 3
JRNC 5
e
pcr 3
JRNC 5
e
pcr 3
JRNC 5
e
pcr 3
JRNC 5
e
pcr 3
JRNC 5
e
pcr 3
JRNC 5
e
pcr 3
JRNC 5
e
pcr 3
JRNC 5
e
pcr 3
JRNC 5
e
pcr 3
JRNC 5
e
pcr 3
JRNC 5
e
pcr 3
JRNC 5
e
pcr 3
JRNC 5
e
pcr 3
JRNC 5
e
pcr 3
JRNC 5
e
JRR 2
b0,rr,ee
bt 1
JRS 2
b0,rr,ee
bt 1
JRR 2
b4,rr,ee
JRZ
2
JRC 4
LD
0
0
e
e
e
e
e
e
e
e
e
e
e
e
#
x
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
a,(x)
0000
0000
1
2
pcr 2
JRNZ 4
pcr
JRZ 4
1
prc 1
JRC 4
ind
LDI
INC 2
1
1
a,nn
0001
0001
1
2
pcr 2
JRNZ 4
pcr 1
JRZ
sd 1
2
prc 2
JRC 4
imm
CP
2
2
#
a,(x)
0010
0010
1
2
pcr 2
JRNZ 4
bt 1
JRS 2
pcr
JRZ 4
1
prc 1
JRC 4
ind
CPI
LD 2
3
3
b4,rr,ee
e
bt 1
a,x
#
a,nn
0011
0011
1
2
pcr 2
JRNZ 4
pcr 1
JRZ
sd 1
2
prc 2
JRC 4
imm
ADD
a,(x)
JRR 2
b2,rr,ee
bt 1
JRS 2
b2,rr,ee
bt 1
JRR 2
b6,rr,ee
bt 1
JRS 2
b6,rr,ee
bt 1
JRR 2
b1,rr,ee
bt 1
JRS 2
b1,rr,ee
bt 1
JRR 2
b5,rr,ee
bt 1
JRS 2
b5,rr,ee
bt 1
JRR 2
b3,rr,ee
bt 1
JRS 2
b3,rr,ee
bt 1
JRR 2
b7,rr,ee
bt 1
JRS 2
b7,rr,ee
4
4
e
e
e
e
e
e
e
e
e
e
e
e
0100
0100
1
2
pcr 2
JRNZ 4
pcr
JRZ 4
1
prc 1
JRC 4
ind
ADDI
INC 2
5
5
y
a,nn
0101
0101
1
2
pcr 2
JRNZ 4
pcr 1
JRZ
sd 1
2
prc 2
JRC 4
imm
INC
6
6
#
(x)
#
0110
0110
1
2
pcr 2
JRNZ 4
pcr
JRZ 4
1
prc 1
JRC
ind
LD 2
7
7
a,y
#
0111
0111
1
2
pcr 2
JRNZ 4
pcr 1
JRZ
sd 1
2
prc
JRC 4
LD
ind
8
8
(x),a
#
1000
1000
1
2
pcr 2
pcr
JRZ 4
1
prc 1
JRC
RNZ
e
4
INC 2
9
9
v
1001
1001
1
2
pcr 2
JRNZ 4
pcr 1
JRZ
sd 1
2
prc
JRC 4
AND
a,(x)
A
1010
A
1010
e
e
e
e
e
e
#
1
2
pcr 2
JRNZ 4
pcr
JRZ 4
1
prc 1
JRC 4
ind
ANDI
LD 2
B
1011
B
1011
a,v
#
a,nn
1
2
pcr 2
JRNZ 4
pcr 1
JRZ
sd 1
2
prc 2
JRC 4
imm
SUB
C
1100
C
1100
a,(x)
1
2
pcr 2
JRNZ 4
pcr
JRZ 4
1
prc 1
JRC 4
ind
SUBI
INC 2
D
1101
D
1101
w
a,nn
1
2
pcr 2
JRNZ 4
pcr 1
JRZ
sd 1
2
prc 2
JRC 4
imm
DEC
E
1110
E
1110
#
(x)
#
1
2
pcr 2
JRNZ 4
pcr
JRZ 4
1
prc 1
JRC
ind
LD 2
F
1111
F
1111
a,w
1
pcr 2
ext 1
pcr 3
bt 1
pcr 1
sd 1
prc
Abbreviations for Addressing Modes: Legend:
dir
sd
Direct
Short Direct
#
e
b
rr
nn
Indicates Illegal Instructions
5 Bit Displacement
3 Bit Address
1byte dataspace address
1 byte immediate data
Cycle
Mnemonic
2
JRC
prc
Operand
imm Immediate
e
inh
ext
b.d
bt
Inherent
Extended
Bit Direct
Bit Test
1
Bytes
abc 12 bit address
ee 8 bit Displacement
Addressing Mode
pcr
ind
Program Counter Relative
Indirect
46/70
134
ST62T08C/T09C ST62T10C/T20C/E20C
Opcode Map Summary (Continued)
LOW
LOW
8
9
A
1010
B
1011
C
1100
D
1101
E
1110
F
1111
1000
1001
HI
HI
2
JRNZ 4
JP 2
JRNC 4
e
pcr 2
JRNC 4
e
pcr 2
JRNC 4
e
pcr 2
JRNC 4
e
pcr 2
JRNC 4
e
pcr 2
JRNC 4
e
pcr 2
JRNC 4
e
pcr 2
JRNC 4
e
pcr 2
JRNC 4
e
pcr 2
JRNC 4
e
pcr 2
JRNC 4
e
pcr 2
JRNC 4
e
pcr 2
JRNC 4
e
pcr 2
JRNC 4
e
pcr 2
JRNC 4
e
pcr 2
JRNC 4
e
RES 2
b0,rr
b.d 1
SET 2
b0,rr
b.d 1
RES 2
b4,rr
JRZ 4
LDI 2
JRC 4
LD
0
0
e
e
e
e
e
e
e
e
e
abc
abc
abc
abc
abc
abc
abc
abc
abc
abc
abc
abc
abc
abc
abc
abc
e
e
e
rr,nn
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
a,(y)
a,rr
0000
0000
1
2
pcr 2
JRNZ 4
ext 1
JP 2
pcr 3
JRZ 4
imm 1
DEC 2
prc 1
JRC 4
ind
LD
1
1
x
0001
0001
1
2
pcr 2
JRNZ 4
ext 1
JP 2
pcr 1
JRZ 4
sd 1
COM 2
prc 2
JRC 4
dir
CP
2
2
a
a,(y)
a,rr
0010
0010
1
2
pcr 2
JRNZ 4
ext 1
JP 2
b.d 1
SET 2
pcr
JRZ 4
1
prc 1
JRC 4
ind
CP
LD 2
3
3
b4,rr
e
b.d 1
x,a
0011
0011
1
2
pcr 2
JRNZ 4
ext 1
JP 2
pcr 1
JRZ 2
sd 1
RETI 2
prc 2
JRC 4
dir
ADD
a,(y)
RES 2
b2,rr
b.d 1
SET 2
b2,rr
b.d 1
RES 2
b6,rr
b.d 1
SET 2
b6,rr
b.d 1
RES 2
b1,rr
b.d 1
SET 2
b1,rr
b.d 1
RES 2
b5,rr
b.d 1
SET 2
b5,rr
b.d 1
RES 2
b3,rr
b.d 1
SET 2
b3,rr
b.d 1
RES 2
b7,rr
b.d 1
SET 2
b7,rr
4
4
e
e
e
e
e
e
e
e
e
e
e
e
0100
0100
1
2
pcr 2
JRNZ 4
ext 1
JP 2
pcr 1
JRZ 4
inh 1
DEC 2
prc 1
JRC 4
ind
ADD
5
5
y
a,rr
(y)
rr
0101
0101
1
2
pcr 2
JRNZ 4
ext 1
JP 2
pcr 1
JRZ 2
sd 1
STOP 2
prc 2
JRC 4
dir
INC
6
6
0110
0110
1
2
pcr 2
JRNZ 4
ext 1
JP 2
pcr 1
JRZ 4
inh 1
LD 2
prc 1
JRC 4
ind
INC
7
7
y,a
0111
0111
1
2
pcr 2
JRNZ 4
ext 1
JP 2
pcr 1
JRZ
sd 1
2
prc 2
JRC 4
dir
LD
8
8
#
v
(y),a
rr,a
1000
1000
1
2
pcr 2
ext 1
JP 2
pcr
JRZ 4
1
prc 1
JRC 4
ind
LD
RNZ
e
4
DEC 2
9
9
1001
1001
1
2
pcr 2
JRNZ 4
ext 1
JP 2
pcr 1
JRZ 4
sd 1
RCL 2
prc 2
JRC 4
dir
AND
a,(y)
A
1010
A
1010
e
e
e
e
e
e
a
1
2
pcr 2
JRNZ 4
ext 1
JP 2
pcr 1
JRZ 4
inh 1
LD 2
prc 1
JRC 4
ind
AND
B
1011
B
1011
v,a
a,rr
1
2
pcr 2
JRNZ 4
ext 1
JP 2
pcr 1
JRZ 2
sd 1
RET 2
prc 2
JRC 4
dir
SUB
C
1100
C
1100
a,(y)
1
2
pcr 2
JRNZ 4
ext 1
JP 2
pcr 1
JRZ 4
inh 1
DEC 2
prc 1
JRC 4
ind
SUB
D
1101
D
1101
w
a,rr
(y)
rr
1
2
pcr 2
JRNZ 4
ext 1
JP 2
pcr 1
JRZ 2
sd 1
WAIT 2
prc 2
JRC 4
dir
DEC
E
1110
E
1110
1
2
pcr 2
JRNZ 4
ext 1
JP 2
pcr 1
JRZ 4
inh 1
LD 2
prc 1
JRC 4
ind
DEC
F
1111
F
1111
w,a
1
pcr 2
ext 1
pcr 2
b.d 1
pcr 1
sd 1
prc 2
dir
Abbreviations for Addressing Modes: Legend:
dir
sd
Direct
Short Direct
#
e
b
rr
nn
Indicates Illegal Instructions
5 Bit Displacement
3 Bit Address
1byte dataspace address
1 byte immediate data
Cycle
Mnemonic
2
1
JRC
prc
Operand
imm Immediate
e
inh
ext
b.d
bt
Inherent
Extended
Bit Direct
Bit Test
Bytes
abc 12 bit address
ee 8 bit Displacement
Addressing Mode
pcr
ind
Program Counter Relative
Indirect
47/70
135
ST62T08C/T09C ST62T10C/T20C/E20C
6 ELECTRICAL CHARACTERISTICS
6.1 ABSOLUTE MAXIMUM RATINGS
This product contains devices to protect the inputs
against damage due to high static voltages, how-
ever it is advisable to take normal precaution to
avoid application of any voltage higher than the
specified maximum rated voltages.
Power Considerations.The average chip-junc-
tion temperature, Tj, in Celsius can be obtained
from:
Tj=TA + PD x RthJA
Where:TA = Ambient Temperature.
For proper operation it is recommended that V
I
RthJA =Package thermal resistance (junc-
tion-to ambient).
and V be higher than V and lower than V .
O
SS
DD
Reliability is enhanced if unused inputs are con-
nected to an appropriate logic voltage level (V
PD = Pint + Pport.
DD
or V ).
SS
Pint =IDD x VDD (chip internal power).
Pport =Port power dissipation (determined
by the user).
Symbol
Parameter
Value
Unit
V
V
Supply Voltage
Input Voltage
Output Voltage
-0.3 to 7.0
DD
(1)
(1)
V
V
V
- 0.3 to V + 0.3
V
I
SS
DD
V
- 0.3 to V + 0.3
V
O
SS
DD
IV
IV
Total Current into V (source)
80
100
mA
mA
°C
°C
DD
SS
DD
Total Current out of V (sink)
SS
Tj
Junction Temperature
Storage Temperature
150
T
-60 to 150
STG
Notes:
-
Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
- (1) Within these limits, clamping diodes are guarantee to be not conductive. Voltages outside these limits are authorised as long as injection
current is kept within the specification.
48/70
136
ST62T08C/T09C ST62T10C/T20C/E20C
6.2 RECOMMENDED OPERATING CONDITIONS
Value
Unit
Symbol
Parameter
Test Conditions
6 Suffix Version
1 Suffix Version
3 Suffix Version
Min.
Typ.
Max.
-40
0
-40
85
70
TA
Operating Temperature
°C
V
125
f
f
= 4MHz, 1 & 6 Suffix
= 4MHz, 3 Suffix
3.0
3.0
3.6
4.5
6.0
6.0
6.0
6.0
OSC
OSC
VDD
Operating Supply Voltage
fosc= 8MHz , 1 & 6 Suffix
fosc= 8MHz , 3 Suffix
V
V
V
V
= 3.0V, 1 & 6 Suffix
= 3.0V , 3 Suffix
= 3.6V , 1 & 6 Suffix
= 3.6V , 3 Suffix
0
0
0
0
4.0
4.0
8.0
4.0
DD
DD
DD
DD
2)
f
Oscillator Frequency
MHz
OSC
IINJ+
IINJ-
Pin Injection Current (positive) VDD = 4.5 to 5.5V
Pin Injection Current (negative) VDD = 4.5 to 5.5V
+5
-5
mA
mA
Notes:
1. Care must be taken in case of negative current injection, where adapted impedance must be respected on analog sources to not affect the
A/D conversion. For a -1mA injection, a maximum 10 KΩ is recommended.
2.An oscillator frequency above 1MHz is recommended for reliable A/D results
Figure 27. Maximum Operating FREQUENCY (Fmax) Versus SUPPLY VOLTAGE (VDD)
Maximum FREQUENCY (MHz)
1 & 6 Suffix version
8
FUNCTIONALITY IS NOT
3 Suffix version
GUARANTEED IN
7
THIS AREA
6
5
4
3
2
1
2.5
3
3.6
4
4.5
5
5.5
6
SUPPLY VOLTAGE (VDD)
The shaded area is outside the recommended operating range; device functionality is not guaranteed under these conditions.
49/70
137
ST62T08C/T09C ST62T10C/T20C/E20C
6.3 DC ELECTRICAL CHARACTERISTICS
(T = -40 to +125°C unless otherwise specified)
A
Value
Typ.
Symbol
Parameter
Test Conditions
Unit
V
Min.
Max.
x 0.3
V
Input Low Level Voltage
All Input pins
IL
V
DD
V
Input High Level Voltage
All Input pins
IH
V
x 0.7
V
DD
(1)
Hysteresis Voltage
All Input pins
V
V
= 5V
= 3V
0.2
0.2
DD
DD
V
V
Hys
V
LVD Threshold in power-on
LVD threshold in powerdown
4.1
3.8
4.3
up
V
3.5
dn
Low Level Output Voltage
All Output pins
V
V
= 5.0V; I = +10µA
0.1
0.8
DD
DD
OL
= 5.0V; I = + 3mA
OL
V
V
V
V
V
= 5.0V; I = +10µA
0.1
0.8
1.3
OL
DD
DD
DD
OL
Low Level Output Voltage
20 mA Sink I/O pins
= 5.0V; I = +7mA
OL
= 5.0V; I = +15mA
OL
High Level Output Voltage
All Output pins
V
V
= 5.0V; I = -10µA
4.9
3.5
DD
DD
OH
V
V
OH
= 5.0V; I = -3.0mA
OH
All Input pins
RESET pin
40
100
350
350
900
R
Pull-up Resistance
ΚΩ
PU
IL
150
Input Leakage Current
All Input pins but RESET
V
V
= V (No Pull-Up configured)
IN
IN
SS
0.1
-16
1.0
= V
I
I
DD
µA
Input Leakage Current
RESET pin
V
V
= V
-8
-30
10
IH
IN
IN
SS
= V
DD
Supply Current in RESET
Mode
V
=V
RESET SS
3.5
3.5
1.5
20
mA
mA
mA
µA
f
=8MHz
OSC
Supply Current in
V
V
=5.0V f =8MHz
(2)
DD
INT
RUN Mode
Supply Current in WAIT
I
=5.0V
f
=8MHz
INT
(3)
DD
DD
Mode
Supply Current in STOP
Mode, with LVD disabled
I
=0mA
=5.0V
LOAD
(3)
V
DD
Supply Current in STOP
Mode, with LVD enabled
I
V
=0mA
=5.0V
LOAD
500
(3)
DD
Retention EPROM Data Retention
TA = 55°C
10
years
Notes:
(1) Hysteresis voltage between switching levels
(2) All peripherals running
(3) All peripherals in stand-by
50/70
138
ST62T08C/T09C ST62T10C/T20C/E20C
DC ELECTRICAL CHARACTERISTICS (Cont’d)
(T = -40 to +85°C unless otherwise specified))
A
Value
Unit
Symbol
Parameter
Test Conditions
Min.
+50 mV 4.1
dn
Typ.
Max.
V
LVD Threshold in power-on
LVD threshold in powerdown
V
4.3
V
V
up
V
3.6
3.8
V
-50 mV
dn
up
V
V
V
= 5.0V; I = +10µA
0.1
0.8
1.2
DD
DD
DD
OL
Low Level Output Voltage
All Output pins
= 5.0V; I = + 5mA
OL
= 5.0V; I = + 10mAv
OL
V
V
V
V
V
V
= 5.0V; I = +10µA
0.1
0.8
1.3
2.0
OL
OH
DD
DD
DD
DD
OL
Low Level Output Voltage
20 mA Sink I/O pins
= 5.0V; I = +10mA
OL
= 5.0V; I = +20mA
OL
= 5.0V; I = +30mA
OL
High Level Output Voltage
All Output pins
V
V
= 5.0V; I = -10µA
4.9
3.5
DD
DD
OH
V
I
V
= 5.0V; I = -5.0mA
OH
Supply Current in STOP
Mode, with LVD disabled
I
=0mA
=5.0V
LOAD
10
µA
(*)
DD
V
DD
Note:
(*) All Peripherals in stand-by.
6.4 AC ELECTRICAL CHARACTERISTICS
(T = -40 to +125°C unless otherwise specified)
A
Value
Typ.
Symbol
Parameter
Test Conditions
Unit
Min.
100
200
Max.
800
(1)
t
Supply Recovery Time
ms
REC
f
Internal frequency with LFAO active
400
kHz
LFAO
V
= 3V
2
2
4
DD
Internal Frequency with OSG
enabled
f
f
MHz
2)
V
V
= 3.6V
= 4.5V
OSG
OSC
DD
DD
VDD=5.0V
Internal frequency with RC oscillator R=47kΩ
4
2.7
800
5
3.2
850
5.8
3.5
900
MHz
MHz
kHz
f
2) 3)
RC
and OSG disabled
R=100kΩ
R=470kΩ
C
Input Capacitance
Output Capacitance
All Inputs Pins
10
10
pF
pF
IN
C
All Outputs Pins
OUT
Notes:
1. Period for which V has to be connected at 0V to allow internal Reset function at next power-up.
DD
2 An oscillator frequency above 1MHz is recommended for reliable A/D results.
3. Measure performed with OSCin pin soldered on PCB, with an around 2pF equivalent capacitance.
51/70
139
ST62T08C/T09C ST62T10C/T20C/E20C
6.5 A/D CONVERTER CHARACTERISTICS
(T = -40 to +125°C unless otherwise specified)
A
Value
Typ.
8
Symbol
Parameter
Test Conditions
Unit
Min.
Max.
Res
Resolution
Total Accuracy
Bit
f
f
> 1.2MHz
> 32kHz
±2
±4
(1) (2)
OSC
OSC
A
LSB
TOT
f
f
= 8MHz (T < 85°C)
= 4 MHz
70
140
OSC
OSC
A
t
Conversion Time
Zero Input Reading
Full Scale Reading
µs
C
Conversion result when
= V
ZIR
00
Hex
Hex
V
IN
SS
Conversion result when
V
FSR
FF
= V
IN
DD
Analog Input Current During
Conversion
AD
V
= 4.5V
1.0
5
µA
I
DD
AC
Analog Input Capacitance
2
pF
IN
Notes:
1. Noise at VDD, VSS <10mV
2. With oscillator frequencies less than 1MHz, the A/D Converter accuracy is decreased.
6.6 TIMER CHARACTERISTICS
(T = -40 to +125°C unless otherwise specified)
A
Value
Typ.
Symbol
Parameter
Test Conditions
Unit
Min.
Max.
f
t
Input Frequency on TIMER Pin
Pulse Width at TIMER Pin
MHz
IN
W
V
V
= 3.0V
>4.5V
1
125
µs
ns
DD
DD
52/70
140
ST62T08C/T09C ST62T10C/T20C/E20C
Figure 28.. RC frequency versus Vcc
10
R=47K
R=100K
R=470K
1
0.1
3
3.5
4
4.5
5
5.5
6
VDD (volts)
This curves represents typical variations and is given for guidance only
Figure 29. LVD thresholds versus temperature
4.2
4.1
4
Vup
Vdn
3.9
3.8
3.7
3.6
-40°C
25°C
95°C
125°C
Temp
This curves represents typical variations and is given for guidance only
53/70
141
ST62T08C/T09C ST62T10C/T20C/E20C
Figure 30. Idd WAIT versus Vcc at 8 Mhz for OTP devices
1.2
1
0.8
0.6
0.4
0.2
0
T = -40°C
T = 25°C
T = 95°C
T = 125°C
3V
4V
5V
6V
Vdd
This curves represents typical variations and is given for guidance only
Figure 31. Idd STOP versus Vcc for OTP devices
8
6
4
2
0
T = -40°C
T = 25°C
T = 95°C
T = 125°C
-2
3V
4V
5V
6V
Vdd
This curves represents typical variations and is given for guidance only
Figure 32. Idd STOP versus Vcc for ROM devices
2
1.5
1
T = -40°C
T = 25°C
T = 95°C
T = 125°C
0.5
0
-0.5
3V
4V
5V
6V
Vdd
This curves represents typical variations and is given for guidance only
54/70
142
ST62T08C/T09C ST62T10C/T20C/E20C
Figure 33. Idd WAIT versus Vcc at 8Mhz for ROM devices
0.8
0.6
0.4
0.2
0
T = -40°C
T = 25°C
T = 95°C
T = 125°C
3V
4V
5V
6V
Vdd
This curves represents typical variations and is given for guidance only
Figure 34. Idd RUN versus Vcc at 8 Mhz for ROM and OTP devices
5
4
3
2
1
T = -40°C
T = 25°C
T = 95°C
T = 125°C
3V
4V
5V
6V
Vdd
This curves represents typical variations and is given for guidance only
Figure 35. Vol versus Iol on all I/O port at Vdd=5V
8
6
4
2
0
T = -40°C
T = 25°C
T = 95°C
T = 125°C
0
10
20
30
40
Iol (mA)
This curves represents typical variations and is given for guidance only
55/70
143
ST62T08C/T09C ST62T10C/T20C/E20C
Figure 36. Vol versus Iol on all I/O port at T=25°C
8
6
4
2
0
Vdd = 3.0V
Vdd = 4.0V
Vdd = 5.0V
Vdd = 6.0V
0
10
20
30
40
Iol (mA)
This curves represents typical variations and is given for guidance only
Figure 37. Vol versus Iol for High sink (20mA) I/Oports at T=25°C
5
4
3
2
1
0
Vdd = 3.0V
Vdd = 4.0V
Vdd = 5.0V
Vdd = 6.0V
0
10
20
30
40
Iol (mA)
This curves represents typical variations and is given for guidance only
Figure 38. Vol versus Iol for High sink (20mA) I/O ports at Vdd=5V
5
4
3
2
1
0
T = -40°C
T = 25°C
T = 95°C
T = 125°C
0
10
20
30
40
Iol (mA)
This curves represents typical variations and is given for guidance only
56/70
144
ST62T08C/T09C ST62T10C/T20C/E20C
Figure 39. Voh versus Ioh on all I/O port at 25°C
6
4
Vdd = 3.0V
Vdd = 4.0V
Vdd = 5.0V
Vdd = 6.0V
2
0
-2
0
10
20
30
40
Ioh (mA)
This curves represents typical variations and is given for guidance only
Figure 40. Voh versus Ioh on all I/O port at Vdd=5V
6
4
2
T = -40°C
T = 25°C
T = 95°C
T = 125°C
0
-2
0
10
20
30
40
Ioh (mA)
This curves represents typical variations and is given for guidance only
57/70
145
ST62T08C/T09C ST62T10C/T20C/E20C
7 GENERAL INFORMATION
7.1 PACKAGE MECHANICAL DATA
Figure 41. 20-Pin Plastic Dual In-Line Package, 300-mil Width
mm
Min Typ Max Min Typ Max
5.33 0.210
inches
Dim.
A
A2 2.92 3.30 4.95 0.115 0.130 0.195
0.36 0.46 0.56 0.014 0.018 0.022
b2 1.14 1.52 1.78 0.045 0.060 0.070
b
c
D
e
0.20 0.25 0.36 0.008 0.010 0.014
24.89 26.92 0.980 1.060
2.54
0.100
E1 6.10 6.35 7.11 0.240 0.250 0.280
L
2.92 3.30 3.81 0.115 0.130 0.150
Number of Pins
PDIP20
N
20
Figure 42. 20-Pin Ceramic Side-Brazed Dual In-Line Package
mm
Min Typ Max Min Typ Max
3.63 0.143
inches
Dim.
A
A1 0.38
0.015
B
3.56 0.46 0.56 0.140 0.018 0.022
B1 1.14 12.70 1.78 0.045 0.500 0.070
C
D
0.20 0.25 0.36 0.008 0.010 0.014
24.89 25.40 25.91 0.980 1.000 1.020
D1
22.86
0.900
E1 6.99 7.49 8.00 0.275 0.295 0.315
e
2.54
0.100
G
6.35 6.60 6.86 0.250 0.260 0.270
G1 9.47 9.73 9.98 0.373 0.383 0.393
G2
L
1.14
0.045
2.92 3.30 3.81 0.115 0.130 0.150
S
12.70
4.22
0.500
0.166
Ø
CDIP20W
Number of Pins
20
N
58/70
146
ST62T08C/T09C ST62T10C/T20C/E20C
PACKAGE MECHANICAL DATA (Cont’d)
Figure 43. 20-Pin Plastic Small Outline Package, 300-mil Width
mm
inches
Typ
Dim.
A
Min Typ Max Min
Max
2.35
2.65 0.0926
0.0040
0.1043
A1 0.10
B
C
D
E
e
0.33
0.51 0.0130
0.32
0.0200
0.0125
0.5118
0.2992
4.98
7.40
13.00 0.1961
7.60 0.2914
1.27
0.050
H
h
10.01
0.25
0°
10.64 0.394
0.74 0.010
0.419
0.029
8°
K
L
8°
0°
0.41
1.27 0.016
0.10
0.050
0.004
G
SO20
Number of Pins
N
20
7.2 .ORDERING INFORMATION
Table 20. OTP/EPROM VERSION ORDERING INFORMATION
Program
Memory (Bytes)
Analog
input
Sales Type
ST62E20CF1
I/O
Temperature Range
Package
3884 (EPROM)
8
0 to +70°C
CDIP20W
PDIP20
PSO20
PDIP20
PSO20
PDIP20
PSO20
PDIP20
PSO20
PDIP20
PSO20
ST62T08CB6
ST62T08CM6
ST62T09CB6
ST62T09CM6
ST62T10CB6
ST62T10CM6
ST62T20CB6
ST62T20CM6
ST62T20CB3
ST62T20CM3
1036 (OTP)
None
1036 (OTP)
1836 (OTP)
3884 (OTP)
3884 (OTP)
4
8
-40 to + 85°C
12
-40 to + 125°C
59/70
147
ST62T08C/T09C ST62T10C/T20C/E20C
Notes:
60/70
148
ST62P08C/P09C
ST62P10C/P20C
8-BIT FASTROM MCUs WITH A/D CONVERTER,
OSCILLATOR SAFEGUARD, SAFE RESET AND 20 PINS
■
■
■
■
■
■
■
3.0 to 6.0V Supply Operating Range
8 MHz Maximum Clock Frequency
-40 to +125°C Operating Temperature Range
Run, Wait and Stop Modes
5 Interrupt Vectors
Look-up Table capability in Program Memory
Data Storage in Program Memory:
User selectable size
■
■
Data RAM: 64bytes
12 I/O pins, fully programmable as:
PDIP20
– Input with pull-up resistor
– Input without pull-up resistor
– Input with interrupt generation
– Open-drain or push-pull output
– Analog Input (except ST62P08C)
■
■
4 I/O lines can sink up to 20mA to drive LEDs or
TRIACs directly
PSO20
8-bit Timer/Counter with 7-bit programmable
prescaler
■
■
■
■
■
Digital Watchdog
Oscillator Safe Guard
Low Voltage Detector for Safe Reset
(See end of Datasheet for Ordering Information)
8-bit A/D Converter with up to 8 analog inputs
On-chip Clock oscillator can be driven by Quartz
Crystal Ceramic resonator or RC network
■
■
■
Power-on Reset
One external Non-Maskable Interrupt
ST626x-EMU2 Emulation and Development
System (connects to an MS-DOS PC via a
parallel port)
DEVICE SUMMARY
ROM
Analog
inputs
DEVICE
I/O Pins
(Bytes)
1036
1036
1836
3884
ST62P08C
ST62P09C
ST62P10C
ST62P20C
12
12
12
12
-
4
8
8
Rev. 2.6
September 1998
61/70
149
ST62P08C/P09C ST62P10C/P20C
1 GENERAL DESCRIPTION
1.1 INTRODUCTION
ment for the production of the specific customer
MCU.
The ST62P08C,P09C,P10C,P20C are the Factory
Advanced Service Technique ROM (FASTROM)
versions of ST62T08C,T09C,T10C,T20C OTP de-
vices.
The STMicroelectronics Sales Organization will be
pleased to provide detailed information on con-
tractual points.
They offer the same functionality as OTP devices,
selecting as FASTROM options the options de-
fined in the programmable option byte of the OTP
version.
Table 1. ROM Memory Map for ST62P08C,P09C
Device Address
Description
0000h-0B9Fh
0BA0h-0F9Fh
0FA0h-0FEFh
0FF0h-0FF7h
0FF8h-0FFBh
0FFCh-0FFDh
0FFEh-0FFFh
Reserved
User ROM
Reserved
1.2 ORDERING INFORMATION
Interrupt Vectors
Reserved
NMI Interrupt Vector
Reset Vector
The following section deals with the procedure for
transfer of customer codes to STMicroelectronics.
1.2.1 Transfer of Customer Code
Customer code is made up of the ROM contents
and the list of the selected FASTROM options.
The ROM contents are to be sent on diskette, or
by electronic means, with the hexadecimal file
generated by the development tool. All unused
bytes must be set to FFh.
Table 2. ROM Memory Map for ST62P10C
Device Address
Description
0000h-087Fh
0880h-0F9Fh
0FA0h-0FEFh
0FF0h-0FF7h
0FF8h-0FFBh
0FFCh-0FFDh
0FFEh-0FFFh
Reserved
User ROM
Reserved
The selected options are communicated to STMi-
croelectronics using the correctly filled OPTION
LIST appended.
Interrupt Vectors
Reserved
NMI Interrupt Vector
Reset Vector
1.2.2 Listing Generation and Verification
When STMicroelectronics receives the user’s
ROM contents, a computer listing is generated
from it. This listing refers exactly to the ROM con-
tents and options which will be used to produce
the specified MCU. The listing is then returned to
the customer who must thoroughly check, com-
plete, sign and return it to STMicroelectronics. The
signed listing forms a part of the contractual agree-
Table 3. ROM Memory Map for ST62P20C
Device Address
Description
0000h-007Fh
0080h-0F9Fh
0FA0h-0FEFh
0FF0h-0FF7h
0FF8h-0FFBh
0FFCh-0FFDh
0FFEh-0FFFh
Reserved
User ROM
Reserved
Interrupt Vectors
Reserved
NMI Interrupt Vector
Reset Vector
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150
ST62P08C/P09C ST62P10C/P20C
ORDERING INFORMATION (Cont’d)
Table 4. ROM version Ordering Information
Sales Type
ROM
Analog inputs
Temperature Range
Package
ST62P08CB1/XXX
ST62P08CB6/XXX
ST62P08CB3/XXX (*)
0 to +70°C
-40 to + 85°C
-40 to + 125°C
PDIP20
1036 Bytes
None
ST62P08CM1/XXX
ST62P08CM6/XXX
ST62P08CM3/XXX (*)
0 to +70°C
-40 to + 85°C
-40 to + 125°C
PSO20
PDIP2
ST62P09CB1/XXX
ST62P09CB6/XXX
ST62P09CB3/XXX (*)
0 to +70°C
-40 to + 85°C
-40 to + 125°C
1036 Bytes
1836 Bytes
3884 Bytes
4
8
8
ST62P09CM1/XXX
ST62P09CM6/XXX
ST62P09CM3/XXX (*)
0 to +70°C
-40 to + 85°C
-40 to + 125°C
PSO20
PDIP20
PSO20
PDIP20
PSO20
ST62P10CB1/XXX
ST62P10CB6/XXX
ST62P10CB3/XXX (*)
0 to +70°C
-40 to + 85°C
-40 to + 125°C
ST62P10CM1/XXX
ST62P10CM6/XXX
ST62P10CM3/XXX (*)
0 to +70°C
-40 to + 85°C
-40 to + 125°C
ST62P20CB1/XXX
ST62P20CB6/XXX
ST62P20CB3/XXX (*)
0 to +70°C
-40 to + 85°C
-40 to + 125°C
ST62P20CM1/XXX
ST62P20CM6/XXX
ST62P20CM3/XXX (*)
0 to +70°C
-40 to + 85°C
-40 to + 125°C
(*)
Advanced information
63/70
151
ST62P08C/P09C ST62P10C/P20C
ST62P08C/P09C/P10C/P20C FASTROM MICROCONTROLLER OPTION LIST
Customer . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact
Phone No . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
STMicroelectronics references
Device:
[ ] ST62P08C [ ] ST62P09C
[ ] ST62P10C
[ ] ST62P20C
Package:
[ ] Dual in Line Plastic [ ] Small Outline Plastic with conditionning:
[ ] Standard (Stick)
[ ] Tape & Reel
Temperature Range:
[ ] 0°C to + 70°C
[ ] - 40°C to + 85°C
[ ] - 40°C to + 125°C
Oscillator Source Selection: [ ] Crystal Quartz/Ceramic resonator
[ ] RC Network
Watchdog Selection:
Readout Protection:
[ ] Software Activation
[ ] Hardware Activation
[ ] Disabled
[ ] Enabled
External STOP Mode Control[ ] Enabled
[ ] Disabled
[ ] Disabled
[ ] Disabled
[ ] Disabled
[ ] Disabled
LVD Reset
[ ] Enabled
[ ] Enabled
[ ] Enabled
[ ] Enabled
TIMER pin pull-up
NMI pin pull-up
OSG
Comments :
Supply Operating Range in the application:
Oscillator Fequency in the application:
Notes
Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Date . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
64/70
152
ST6208C/09C
ST6210C/20C
8-BIT ROM MCUs WITH A/D CONVERTER,
OSCILLATOR SAFEGUARD, SAFE RESET AND 20 PINS
■
■
■
■
■
■
■
3.0 to 6.0V Supply Operating Range
8 MHz Maximum Clock Frequency
-40 to +125°C Operating Temperature Range
Run, Wait and Stop Modes
5 Interrupt Vectors
Look-up Table capability in Program Memory
Data Storage in Program Memory:
User selectable size
■
■
Data RAM: 64bytes
12 I/O pins, fully programmable as:
PDIP20
– Input with pull-up resistor
– Input without pull-up resistor
– Input with interrupt generation
– Open-drain or push-pull output
– Analog Input (except ST6208C)
■
■
4 I/O lines can sink up to 20mA to drive LEDs or
TRIACs directly
PSO20
8-bit Timer/Counter with 7-bit programmable
prescaler
■
■
■
■
■
Digital Watchdog
Oscillator Safe Guard
Low Voltage Detector for Safe Reset
(See end of Datasheet for Ordering Information)
8-bit A/D Converter with up to 8 analog inputs
On-chip Clock oscillator can be driven by Quartz
Crystal Ceramic resonator or RC network
■
■
■
Power-on Reset
One external Non-Maskable Interrupt
ST626x-EMU2 Emulation and Development
System (connects to an MS-DOS PC via a
parallel port)
DEVICE SUMMARY
ROM
Analog
inputs
DEVICE
I/O Pins
(Bytes)
1036
1036
1836
3884
ST6208C
ST6209C
ST6210C
ST6220C
12
12
12
12
-
4
8
8
Rev. 2.6
September 1998
65/70
153
ST6208C/09C ST6210C/20C
1 GENERAL DESCRIPTION
1.1 INTRODUCTION
1.2 ROM READOUT PROTECTION
The ST6210C/20C are mask programmed ROM
version of ST62T08C,T09C,T10C,T20C OTP de-
vices.
If the ROM READOUT PROTECTION option is
selected, a protection fuse can be blown to pre-
vent any access to the program memory content.
They offer the same functionality as OTP devices,
selecting as ROM options the options defined in
the programmable option byte of the OTP version.
In case the user wants to blow this fuse, high volt-
age must be applied on the TEST pin.
Figure 1. Programming wave form
Figure 2. Programming Circuit
0.5s min
TEST
5V
47mF
15
14V typ
10
100nF
5
V
SS
V
DD
TEST
150 µs typ
PROTECT
100mA
max
14V
TEST
100nF
ZPD15
15V
VR02003
4mA typ
t
VR02001
Note: ZPD15 is used for overvoltage protection
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ST6208C/09C ST6210C/20C
ST6208C/09C/10C/20C MICROCONTROLLER OPTION LIST
Customer . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact
Phone No . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
STMicroelectronics references
Device:
[ ] ST6208C
[ ] ST6209C
[ ] ST6210C
[ ] ST6220C
Package:
[ ] Dual in Line Plastic [ ] Small Outline Plastic with conditionning:
[ ] Standard (Stick)
[ ] Tape & Reel
Temperature Range:
Special Marking:
[ ] 0°C to + 70°C
[ ] No
[ ] - 40°C to + 85°C
[ ] - 40°C to + 125°C
[ ] Yes "_ _ _ _ _ _ _ _ _ _ _ "
Authorized characters are letters, digits, '.', '-', '/' and spaces only.
Maximum character count: DIP20:
SO20:
10
8
Oscillator Source Selection: [ ] Crystal Quartz/Ceramic resonator
[ ] RC Network
Watchdog Selection:
[ ] Software Activation
[ ] Hardware Activation
ROM Readout Protection: [ ] Disabled (Fuse cannot be blown)
[ ] Enabled (Fuse can be blown by the customer)
No part is delivered with protected ROM.
The fuse must be blown for protection to be effective.
Note:
External STOP Mode Control[ ] Enabled
[ ] Disabled
[ ] Disabled
[ ] Disabled
[ ] Disabled
[ ] Disabled
LVD Reset
[ ] Enabled
[ ] Enabled
[ ] Enabled
[ ] Enabled
TIMER pin pull-up
NMI pin pull-up
OSG
Comments :
Supply Operating Range in the application:
Oscillator Fequency in the application:
Notes
Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Date . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
67/70
155
ST6208C/09C ST6210C/20C
1.3 ORDERING INFORMATION
The following section deals with the procedure for
transfer of customer codes to STMicroelectronics.
Table 1. ROM Memory Map for ST6208C,09C
Device Address
Description
1.3.1 Transfer of Customer Code
0000h-0B9Fh
0BA0h-0F9Fh
0FA0h-0FEFh
0FF0h-0FF7h
0FF8h-0FFBh
0FFCh-0FFDh
0FFEh-0FFFh
Reserved
User ROM
Reserved
Customer code is made up of the ROM contents
and the list of the selected mask options. The
ROM contents are to be sent on diskette, or by
electronic means, with the hexadecimal file gener-
ated by the development tool. All unused bytes
must be set to FFh.
Interrupt Vectors
Reserved
NMI Interrupt Vector
Reset Vector
The selected mask options are communicated to
STMicroelectronics using the correctly filled OP-
TION LIST appended.
Table 2. ROM Memory Map for ST6210C
Device Address
Description
1.3.2 Listing Generation and Verification
0000h-087Fh
0880h-0F9Fh
0FA0h-0FEFh
0FF0h-0FF7h
0FF8h-0FFBh
0FFCh-0FFDh
0FFEh-0FFFh
Reserved
User ROM
Reserved
When STMicroelectronics receives the user’s
ROM contents, a computer listing is generated
from it. This listing refers exactly to the mask which
will be used to produce the specified MCU. The
listing is then returned to the customer who must
thoroughly check, complete, sign and return it to
STMicroelectronics. The signed listing forms a
part of the contractual agreement for the creation
of the specific customer mask.
Interrupt Vectors
Reserved
NMI Interrupt Vector
Reset Vector
Table 3. ROM Memory Map for ST6220C
The STMicroelectronics Sales Organization will be
pleased to provide detailed information on con-
tractual points.
Device Address
Description
0000h-007Fh
0080h-0F9Fh
0FA0h-0FEFh
0FF0h-0FF7h
0FF8h-0FFBh
0FFCh-0FFDh
0FFEh-0FFFh
Reserved
User ROM
Reserved
Interrupt Vectors
Reserved
NMI Interrupt Vector
Reset Vector
68/70
156
ST6208C/09C ST6210C/20C
ORDERING INFORMATION (Cont’d)
Table 4. ROM version Ordering Information
Sales Type
ROM
Analog inputs
Temperature Range
Package
ST6208CB1/XXX
ST6208CB6/XXX
ST6208CB3/XXX
0 to +70°C
-40 to + 85°C
-40 to + 125°C
PDIP20
1036 Bytes
None
ST6208CM1/XXX
ST6208CM6/XXX
ST6208CM3/XXX
0 to +70°C
-40 to + 85°C
-40 to + 125°C
PSO20
PDIP2
ST6209CB1/XXX
ST6209CB6/XXX
ST6209CB3/XXX
0 to +70°C
-40 to + 85°C
-40 to + 125°C
1036 Bytes
1836 Bytes
3884 Bytes
4
8
8
ST6209CM1/XXX
ST6209CM6/XXX
ST6209CM3/XXX
0 to +70°C
-40 to + 85°C
-40 to + 125°C
PSO20
PDIP20
PSO20
PDIP20
PSO20
ST6210CB1/XXX
ST6210CB6/XXX
ST6210CB3/XXX
0 to +70°C
-40 to + 85°C
-40 to + 125°C
ST6210CM1/XXX
ST6210CM6/XXX
ST6210CM3/XXX
0 to +70°C
-40 to + 85°C
-40 to + 125°C
ST6220CB1/XXX
ST6220CB6/XXX
ST6220CB3/XXX
0 to +70°C
-40 to + 85°C
-40 to + 125°C
ST6220CM1/XXX
ST6220CM6/XXX
ST6220CM3/XXX
0 to +70°C
-40 to + 85°C
-40 to + 125°C
69/70
157
ST6208C/09C ST6210C/20C
Notes:
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
1998 STMicroelectronics - All Rights Reserved.
Purchase of I2C Components by STMicroelectronics conveys a license under the Philips I2C Patent. Rights to use these components in an
I2C system is granted provided that the system conforms to the I2C Standard Specification as defined by Philips.
STMicroelectronics Group of Companies
Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands -
Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
http://www.st.com
70/70
158
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