ST6260BB3 [STMICROELECTRONICS]
8-BIT OTP/EPROM MCUs WITH A/D CONVERTER, AUTO-RELOAD TIMER, EEPROM AND SPI; 8位OTP / EPROM微控制器与A / D转换器，自动重载定时器， EEPROM和SPI
| 型号： | ST6260BB3 |
| 厂家： | 
ST |
| 描述： | 8-BIT OTP/EPROM MCUs WITH A/D CONVERTER, AUTO-RELOAD TIMER, EEPROM AND SPI |
| 文件： | 总75页 (文件大小：534K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ST62T53B/T60B/T63B
ST62E60B
R
8-BIT OTP/EPROM MCUs WITH A/D CONVERTER,
AUTO-RELOAD TIMER, EEPROM AND SPI
■ 3.0 to 6.0V Supply Operating Range
■ 8 MHz Maximum Clock Frequency
■
-40 to +125°C Operating Temperature Range
■
Run, Wait and Stop Modes
■ 5 Interrupt Vectors
■ Look-up Table capability in Program Memory
■
Data Storage in Program Memory:
User selectable size
■ Data RAM: 128 bytes
■ DataEEPROM:64/128bytes(noneonST62T53B)
PDIP20
■
User Programmable Options
■ 13 I/O pins, fully programmable as:
– Input with pull-up resistor
– Input without pull-up resistor
– Input with interrupt generation
– Open-drain or push-pull output
– Analog Input
PSO20
■ 6 I/O lines can sink up to 20mA to drive LEDs or
TRIACs directly
■
8-bit Timer/Counter with 7-bit programmable
prescaler
■ 8-bit Auto-reload Timer with 7-bit programmable
prescaler (AR Timer)
■
Digital Watchdog
■ 8-bit A/D Converter with 7 analog inputs
■ 8-bit Synchronous Peripheral Interface (SPI)
CDIP20W
■
On-chip Clock oscillator can be driven by Quartz
Crystal Ceramic resonator or RC network
■ User configurable Power-on Reset
■ One external Non-Maskable Interrupt
(See end of Datasheet for Ordering Information)
■
ST626x-EMU2 Emulation and Development
System (connects to an MS-DOS PC via a
parallel port).
DEVICE SUMMARY
EPROM
DEVICE
OTP (Bytes)
EEPROM
(Bytes)
ST62T53B
ST62T60B
ST62T63B
ST62E60B
1836
3884
1836
-
-
-
-
-
128
64
Rev. 2.4
3884
128
April 1998
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1
Table of Contents
ST62T53B/T60B/T63B / ST62E60B . . . . . . . . . . . . . . . . . . . . . .1
1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
1.2 PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
1.3 MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
1.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
1.3.2 Program Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
1.3.3 Data Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
1.3.4 Stack Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
1.3.5 Data Window Register (DWR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.3.6 Data RAM/EEPROM Bank Register (DRBR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.3.7 EEPROM Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
1.4 PROGRAMMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
1.4.1 Option Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
1.4.2 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
1.4.3 EEPROM Data Memory (except ST62T53B). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.4.4 EPROM Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
2 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
2.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
2.2 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . 18
3.1 CLOCK SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
3.1.1 Main Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
3.2 RESETS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
3.2.1 RESET Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
3.2.2 Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
3.2.3 Watchdog Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
3.2.4 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
3.2.5 MCU Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.3 DIGITAL WATCHDOG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
3.3.1 Digital Watchdog Register (DWDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.3.2 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
3.4 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
3.4.1 Interrupt request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
3.4.2 Interrupt Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
3.4.3 Interrupt Option Register (IOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.4.4 Interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
3.5 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
3.5.1 WAIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
3.5.2 STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
3.5.3 Exit from WAIT and STOP Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
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Table of Contents
4 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
4.1 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
4.1.1 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
4.1.2 Safe I/O State Switching Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.2 TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
4.2.1 Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
4.2.2 Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
4.2.3 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
4.2.4 Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
4.3 AUTO-RELOAD TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
4.3.1 AR Timer Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
4.3.2 Timer Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
4.3.3 AR Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
4.4 A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
4.4.1 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
4.5 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.5.1 SPI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
4.6 SPI TIMING DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
5 SOFTWARE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
5.1 ST6 ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
5.2 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
5.3 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
6 ELECTRICAL CHARACTERISTICS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
6.1 ABSOLUTE MAXIMUM RATINGS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
6.2 RECOMMENDED OPERATING CONDITIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6.3 DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
6.4 AC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
6.5 A/D CONVERTER CHARACTERISTICS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
6.6 TIMER CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
6.7 SPI CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
6.8 ARTIMER ELECTRICAL CHARACTERISTICS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
7 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
7.1 PACKAGE MECHANICAL DATA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
7.2 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
ST62P53B/P60B/P63B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
1.2 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
1.2.1 Transfer of Customer Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
1.2.2 Listing Generation and Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
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Table of Contents
ST6253B/60B/63B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
1.2 ROM READOUT PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
1.3 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
1.3.1 Transfer of Customer Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
1.3.2 Listing Generation and Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
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ST62T53B/T60B/T63B ST62E60B
1 GENERAL DESCRIPTION
1.1 INTRODUCTION
The ST62T53B, ST62T60B, ST62T63B and
ST62E60B devices are low cost members of the
ST62xx 8-bit HCMOS family of microcontrollers,
which is targeted at low to medium complexity ap-
plications. All ST62xx devices are based on a
building block approach: a common core is sur-
rounded by a number of on-chip peripherals.
fined in the programmable option byte of theOTP/
EPROM versions.
OTP devices offer all the advantages of user pro-
grammability at low cost, which make them the
ideal choice in a wide range of applications where
frequent code changes, multiple code versions or
last minute programmability are required.
The ST62E60B is the erasable EPROM version of
the ST62T60B device, which may be used to em-
ulate the ST62T53B, ST62T60B and ST62T63B
devices, as well as the respective ST6253B,
ST6260B and ST6263B ROM devices.
These compact low-cost devices feature a Timer
comprising an 8-bit counter and a 7-bit program-
mable prescaler, an 8-bit Auto-Reload Timer,
EEPROM data capability (except ST62T53B), a
serial port communication interface, an 8-bit A/D
Converter with 7 analog inputs and a Digital
Watchdog timer, making them well suited for a
wide range of automotive, appliance and industrial
applications.
OTP and EPROM devices are functionally identi-
cal. The ROM based versions offer the same func-
tionality selecting as ROM options the options de-
Figure 1. Block Diagram
8-BIT
PA0..PA3 / Ain
PORT A
PORT B
A/D CONVERTER
TEST/V
PP
TEST
PB0..PB3 / 20 mA Sink
PB6 / ARTimin / 20 mA Sink
PB7 / ARTimout / 20 mA Sink
NMI
INTERRUPT
DATA ROM
USER
SELECTABLE
PC2 / Sin / Ain
PC3 / Sout / Ain
PC4 / Sck / Ain
PORT C
PROGRAM
MEMORY
1836 bytesOTP
DATA RAM
128 Bytes
AUTORELOAD
TIMER
(ST62T53B,T63B)
3884 bytesOTP
(ST62T60B)
3884 bytesEPROM
(ST62E60B)
DATA EEPROM
64 Bytes
(ST62T63B)
TIMER
128Bytes
(ST62T60B/E60B)
SPI (SERIAL
PERIPHERAL
PC
INTERFACE )
STACK LEVEL 1
STACK LEVEL 2
STACK LEVEL 3
STACK LEVEL 4
STACK LEVEL 5
STACK LEVEL 6
DIGITAL
WATCHDOG
8 BIT CORE
POWER
RESET
RESET
OSCILLATOR
SUPPLY
V
V
OSCin OSCout
DD SS
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ST62T53B/T60B/T63B ST62E60B
1.2 PIN DESCRIPTIONS
V
and V . Power is supplied to the MCU via
PB6/ARTIMin, PB7/ARTIMout. These pins are ei-
ther Port B I/O bits or the Input and Output pins of
the AR TIMER. To be used as timer input function
PB6 has to be programmed as input with or with-
out pull-up. A dedicated bit in the AR TIMER Mode
Control Register sets PB7 as timer output function.
PB6-PB7 can also sink 20mA for direct LED driv-
ing.
DD
SS
these two pins. V is the power connection and
DD
V
is the ground connection.
SS
OSCin and OSCout. These pins are internally
connected to the on-chip oscillator circuit. A quartz
crystal, a ceramic resonator or an external clock
signal can be connected between these two pins.
The OSCin pin is the input pin, the OSCout pin is
the output pin.
PC2-PC4
. These 3 lines are organized as one I/O
port (C). Each line may be configured under soft-
ware control as input with or without internal pull-
up resistor, interrupt generating input with pull-up
resistor, analog input for the A/D converter, open-
drain or push-pull output.
PC2-PC4 can also be used as respectively Data
in, Data out and Clock I/O pins for the on-chip SPI
to carry the synchronous serial I/O signals.
RESET. The active-low RESET pin is used to re-
start the microcontroller.
TEST/V .
The TEST must be held at V for nor-
PP
SS
mal operation. If TEST pin is connected to a
+12.5V level during the reset phase, the EPROM/
OTP programming Mode is entered.
NMI.
The NMI pin provides the capability for asyn-
chronous interruption, by applying an external non
maskable interrupt to the MCU.The NMI input is
falling edge sensitive.It is provided with an on-chip
pullup resistor and Schmitt trigger characteristics.
Figure 2. ST62T53/T60B/T63B/E60B Pin
Configuration
PA0-PA3. These 4 lines are organized as one I/O
port (A). Each line may be configured under soft-
ware control as inputs with or without internal pull-
up resistors, interrupt generating inputs with pull-
up resistors, open-drain or push-pull outputs, ana-
log inputs for the A/D converter.
1
2
20
19
18
17
16
15
14
13
12
11
PB0
PB1
PC2 / Sin / Ain
PC3 / Sout / Ain
PC4 / Sck / Ain
NMI
V
/TEST
3
PP
4
PB2
PB3
5
RESET
PB0-PB3. These 4 lines are organized as one I/O
port (B). Each line may be configured under soft-
ware control as inputs with or without internal pull-
up resistors, interrupt generating inputs with pull-
up resistors, open-drain or push-pull outputs.
PB0-PB3 can also sink 20mA for direct LED
driving.
6
ARTIMin/PB6
ARTIMout/PB7
Ain/PA0
OSCout
7
OSCin
8
PA3/Ain
V
DD
9
PA2/Ain
V
10
PA1/Ain
SS
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ST62T53B/T60B/T63B ST62E60B
1.3 MEMORY MAP
1.3.1 Introduction
Briefly, Program space contains user program
code in OTP and user vectors; Data space con-
tains user data in RAM and in OTP, and Stack
space accommodates six levels of stack for sub-
routine and interrupt service routine nesting.
The MCU operates in three separate memory
spaces: Program space, Data space, and Stack
space. Operation in these three memory spaces is
described in the following paragraphs.
Figure 3. Memory Addressing Diagram
PROGRAM SPACE
DATA SPACE
0000h
000h
RAM / EEPROM
BANKING AREA
0-63
03Fh
040h
DATA READ-ONLY
WINDOW
MEMORY
PROGRAM
MEMORY
07Fh
080h
081h
082h
083h
084h
X REGISTER
Y REGISTER
V REGISTER
W REGISTER
RAM
DATA READ-ONLY
MEMORY
WINDOW SELECT
0C0h
0FF0h
DATA RAM
INTERRUPT &
RESET VECTORS
0FFFh
BANK SELECT
ACCUMULATOR
0FFh
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7
ST62T53B/T60B/T63B ST62E60B
MEMORY MAP (Cont’d)
1.3.2 Program Space
Program Space comprises the instructions to be
executed, the data required for immediate ad-
dressing mode instructions, the reserved factory
test area and the user vectors. Program Space is
addressed via the 12-bit Program Counter register
(PC register).
In the EPROM parts, READOUT PROTECTION
option can be disactivated only by U.V. erasure
that also results into the whole EPROM context
erasure.
Note:
Once the Readout Protection is activated, it
is no longer possible, even for SGS-THOMSON,
to gain access to the OTP contents. Returned
parts with a protection set can therefore not be ac-
cepted.
1.3.2.1 Program Memory Protection
The Program Memory in OTP or EPROM devices
can be protected against external readout of mem-
ory by selecting the READOUT PROTECTION op-
tion in the option byte.
Figure 5. ST62T53B/T63B Program
Memory Map
Figure 4. ST62E60B/T60B Program
Memory Map
0000h
0000h
*
RESERVED
007Fh
0080h
*
RESERVED
087Fh
0880h
USER
PROGRAM MEMORY
(OTP/EPROM)
3872 BYTES
USER
PROGRAM MEMORY
(OTP)
1824 BYTES
0F9Fh
0FA0h
0FEFh
0FF0h
0FF7h
0FF8h
0FFBh
0FFCh
0F9Fh
0FA0h
0FEFh
0FF0h
0FF7h
0FF8h
0FFBh
0FFCh
*
RESERVED
*
RESERVED
INTERRUPT VECTORS
INTERRUPT VECTORS
RESERVED
RESERVED
NMI VECTOR
0FFDh
0FFEh
0FFFh
NMI VECTOR
0FFDh
0FFEh
0FFFh
USER RESET VECTOR
USER RESET VECTOR
(*) Reserved areas should be filled with 0FFh
(*) Reserved areas should be filled with 0FFh
8/75
8
ST62T53B/T60B/T63B ST62E60B
MEMORY MAP (Cont’d)
1.3.3 Data Space
Table 2. ST62T53B, T60B, T63B and ST62E60B
Data Memory Space
Data Space accommodates all the data necessary
for processing the user program. This space com-
prises the RAM resource, the processor core and
peripheral registers, as well as read-only data
such as constants and look-up tables in OTP/
EPROM.
000h
RAM and EEPROM
03Fh
040h
DATA ROM WINDOW AREA
07Fh
1.3.3.1 Data ROM
X REGISTER
Y REGISTER
V REGISTER
W REGISTER
080h
081h
082h
083h
084h
All read-only data is physically stored in program
memory, which also accommodates the Program
Space. The program memory consequently con-
tains the program code to be executed, as well as
the constants and look-up tables required by the
application.
DATA RAM 60 BYTES
0BFh
0C0h
0C1h
0C2h
0C3h
0C4h
0C5h
0C6h
0C7h
0C8h*
0C9h*
0CAh
0CBh
0CCh
0CDh
0CEh
0CFh
0D0h
0D1h
0D2h
0D3h
0D4h
0D5h
0D6h
0D7h
0D8h
0D9h
0DAh
0DBh
0DCh*
0DDh
0DEh
0DFh
0E0h
0E1h
0E2h
0E3h
0E7h
0E8h*
0E9h
PORT A DATA REGISTER
PORT B DATA REGISTER
PORT C DATA REGISTER
RESERVED
The Data Space locations in which the different
constants and look-up tables are addressed by the
processor core may be thought of as a 64-byte
window through which it is possible to access the
read-only data stored in OTP/EPROM.
PORT A DIRECTION REGISTER
PORT B DIRECTION REGISTER
PORT C DIRECTION REGISTER
RESERVED
INTERRUPT OPTION REGISTER
DATA ROM WINDOW REGISTER
1.3.3.2 Data RAM/EEPROM
In ST62T53B, T60B, T63B and ST62E60B devic-
es, the data space includes 60 bytes of RAM, the
accumulator (A), the indirect registers (X), (Y), the
short direct registers (V), (W), the I/O port regis-
ters, the peripheral data and control registers, the
interrupt option register and the Data ROM Win-
dow register (DRW register).
RESERVED
PORT A OPTION REGISTER
PORT B OPTION REGISTER
PORT C OPTION REGISTER
RESERVED
A/D DATA REGISTER
A/D CONTROL REGISTER
Additional RAM and EEPROM pages can also be
addressed using banks of 64 bytes located be-
tween addresses 00h and 3Fh.
TIMER PRESCALER REGISTER
TIMER COUNTER REGISTER
TIMER STATUS CONTROL REGISTER
AR TIMER MODE CONTROL REGISTER
AR TIMER STATUS/ CONTROL REGISTER1
AR TIMER STATUS/ CONTROL REGISTER2
WATCHDOG REGISTER
AR TIMER RELOAD/CAPTURE REGISTER
AR TIMER COMPARE REGISTER
AR TIMER LOAD REGISTER
1.3.4 Stack Space
Stack space consists of six 12-bit registers which
are used to stack subroutine and interrupt return
addresses, as well as the current program counter
contents.
Table 1. Additional RAM/EEPROM Banks
OSCILLATOR CONTROL REGISTER
MISCELLANEOUS
Device
RAM
EEPROM
RESERVED
ST62T53B
1 x 64 bytes
1 x 64 bytes
1 x 64 bytes
-
SPI DATA REGISTER
SPI DIVIDER REGISTER
SPI MODE REGISTER
ST62T60B/E60B
ST62T63B
2 x 64 bytes
1 x 64 bytes
RESERVED
DATA RAM/EEPROMREGISTER
RESERVED
EEPROM CONTROL REGISTER
(except ST62T53B)
0EAh
0EBh
0FEh
0FFh
RESERVED
ACCUMULATOR
* WRITE ONLY REGISTER
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9
ST62T53B/T60B/T63B ST62E60B
MEMORY MAP (Cont’d)
1.3.5 Data Window Register (DWR)
Data Window Register (DWR)
The Data read-only memory window is located from
address 0040h to address 007Fh in Data space. It
allows direct reading of 64 consecutive bytes locat-
ed anywhere in program memory, between ad-
dress 0000h and 0FFFh (top memory address de-
pends on the specific device). All the program
memory can therefore be used to store either in-
structions or read-only data. Indeed, the window
can be moved in steps of 64 bytes along the pro-
gram memory by writing the appropriate code in the
Data Window Register (DWR).
Address: 0C9h
—
Write Only
7
0
-
-
DWR5 DWR4 DWR3 DWR2 DWR1 DWR0
Bits 6, 7 = Not used.
Bit 5-0 = DWR6-DWR0: Data read-only memory
Window Register Bits. These are the Data read-
only memory Window bits that correspond to the
upper bits of the data read-only memory space.
The DWR can be addressed like any RAM location
in the Data Space, it is however a write-only regis-
ter and therefore cannot be accessed using single-
bit operations. This register is used to position the
64-byte read-only data window (from address 40h
to address 7Fh of the Data space) in program
memory in 64-byte steps. The effective address of
the byte to be read as data in program memory is
obtained by concatenating the 6 least significant
bits of the register address given in the instruction
(as least significant bits) and the content of the
DWR register (as most significant bits), as illustrat-
ed in Figure 6 below. For instance, when address-
ing location 0040h of the Data Space, with 0 load-
ed in the DWR register, the physical location ad-
dressed in program memory is 00h. The DWR reg-
ister is not cleared on reset, therefore it must be
written to prior to the first access to the Data read-
only memory window area.
Caution: This register is undefined on reset. Nei-
ther read nor single bit instructions may be used to
address this register.
Note: Care is required when handling the DWR
register as it is write only. For this reason, the
DWR contents should not be changed while exe-
cuting an interrupt service routine, as the service
routine cannot save and then restore the register’s
previous contents. If it is impossible to avoid writ-
ing to the DWR during the interrupt service routine,
an image of the register must be saved in a RAM
location, and each time the program writes to the
DWR, it must also write to the image register. The
image register must be written first so that, if an in-
terrupt occurs between the two instructions, the
DWR is not affected.
Figure 6. Data read-only memory Window Memory Addressing
13 12 11 10
9
3
8
2
7
1
6
0
5
5
4
4
3
3
2
2
1
1
0
0
PROGRAM SPACE ADDRESS
READ
DATA ROM
WINDOW REGISTER
CONTENTS
7
6
5
4
DATA SPACE ADDRESS
:
(DWR)
40h-7Fh
0
1
IN INSTRUCTION
Example:
0
0
0
0
0
0
0
1
1
1
1
DWR=28h
DATA SPACE ADDRESS
:
1
1
1
1
1
0
0
0
0
0
0
59h
ROM
ADDRESS:A19h
1
0
0
1
VR01573C
10/75
10
ST62T53B/T60B/T63B ST62E60B
MEMORY MAP (Cont’d)
1.3.6 Data RAM/EEPROM Bank Register
(DRBR)
Data Space. The number of banks has to be load-
ed in the DRBR register and the instruction has to
point to the selected location as if it was in bank 0
(from 00h address to 3Fh address).
Address: E8h
—
Write only
7
0
This register is not cleared during the MCU initiali-
zation, therefore it must be written before the first
access to the Data Space bank region. Refer to
the Data Space description for additional informa-
tion. The DRBR register is not modified when an
interrupt or a subroutine occurs.
DRBR
4
DRBR DRBR
-
-
-
-
-
1
0
Bit 7-5 = These bits are not used
Bit 4 - DRBR4. This bit, when set, selects RAM
Page 2.
Notes
:
Care is required when handling the DRBR register
as it is write only. For this reason, it is not allowed
to change the DRBR contents while executing in-
terrupt service routine, as the service routine can-
not save and then restore its previous content. If it
is impossible to avoid the writing of this register in
interrupt service routine, an image of this register
must be saved in a RAM location, and each time
the program writes to DRBR it must write also to
the image register. The image register must be
written first, so if an interrupt occurs between the
two instructions the DRBR is not affected.
Bit 3-2 - Reserved. These bits are not used.
Bit 1 - DRBR1. This bit, when set, selects
EEPROM Page 1.
Bit 0 - DRBR0. This bit, when set, selects
EEPROM Page 0.
The selection of the bank is made by programming
the Data RAM Bank Switch register (DRBR regis-
ter) located at address E8h of the Data Space ac-
cording to Table 1. No more than one bank should
be set at a time.
The DRBR register can be addressed like a RAM
Data Space at the address E8h; nevertheless it is
a write only register that cannot be accessed with
single-bit operations. This register is used to select
the desired 64-byte RAM/EEPROM bank of the
In DRBR Register, only 1 bit must be set. Other-
wise two or more pages are enabled in parallel,
producing errors.
Table 3. Data RAM Bank Register Set-up
DRBR
00
ST62T53B
None
ST62T60B/E60B
None
ST62T63B
None
01
Not Available
Not Available
Not Available
RAM Page 2
Reserved
EEPROM Page 0
EEPROM Page 1
Not Available
RAM Page 2
Reserved
EEPROM Page 0
Not Available
Not Available
RAM Page 2
Reserved
02
08
10h
other
11/75
11
ST62T53B/T60B/T63B ST62E60B
MEMORY MAP (Cont’d)
1.3.7 EEPROM Description
(PMODE). In BMODE, one byte is accessed at a
time, while in PMODE up to 8 bytes in the same
row are programmed simultaneously (with conse-
quent speed and power consumption advantages,
the latter being particularly important in battery
powered circuits).
EEPROM memory is located in 64-byte pages in
data space. This memory may be used by the user
program for non-volatile data storage.
Data space from 00h to 3Fh is paged as described
in Table 4. EEPROM locations are accessed di-
rectly by addressing these paged sections of data
space.
General Notes:
Data should be written directly to the intended ad-
dress in EEPROM space. There is no buffer mem-
ory between data RAM and the EEPROM space.
The EEPROM does not require dedicated instruc-
tions for read or write access. Once selected via the
Data RAM Bank Register, the active EEPROM
page is controlled by the EEPROM Control Regis-
ter (EECTL), which is described below.
When the EEPROM is busy (E2BUSY = “1”)
EECTL cannot be accessed in write mode, it is
only possible to read the status of E2BUSY. This
implies that as long as the EEPROM is busy, it is
not possible to change the status of the EEPROM
Control Register. EECTL bits 4 and 5 are reserved
and must never be set.
Bit E20FF of the EECTL register must be reset prior
to any write or read access to the EEPROM. If no
bank has been selected, or if E2OFF is set, any ac-
cess is meaningless.
Care is required when dealing with the EECTL reg-
ister, as some bits are write only. For this reason,
the EECTL contents must not be altered while ex-
ecuting an interrupt service routine.
Programming must be enabled by setting the
E2ENA bit of the EECTL register.
The E2BUSY bit of the EECTL register is set when
the EEPROM is performing a programming cycle.
Any access to the EEPROM when E2BUSY is set
is meaningless.
If it is impossible to avoid writing to this register
within an interrupt service routine, an image of the
register must be saved in a RAM location, and
each time the program writes to EECTL it must
also write to the image register. The image register
must be written to first so that, if an interrupt oc-
curs between the two instructions, the EECTL will
not be affected.
Provided E2OFF and E2BUSY are reset, an EEP-
ROM location is read just like any other data loca-
tion, also in terms of access time.
Writing to the EEPROM may be carried out in two
modes: Byte Mode (BMODE) and Parallel Mode
Table 4. . Row Arrangement for Parallel Writing of EEPROM Locations
Dataspace
addresses.
Banks 0 and 1.
Byte
0
1
2
3
4
5
6
7
ROW7
ROW6
ROW5
ROW4
ROW3
ROW2
ROW1
ROW0
38h-3Fh
30h-37h
28h-2Fh
20h-27h
18h-1Fh
10h-17h
08h-0Fh
00h-07h
Up to 8 bytes in each row may be programmed simultaneously in Parallel Write mode.
The number of available 64-byte banks (1 or 2) is device dependent.
12/75
12
ST62T53B/T60B/T63B ST62E60B
MEMORY MAP (Cont’d)
Additional Notes on Parallel Mode:
EEPROM Control Register (EECTL)
Address: EAh Read/Write
If the user wishes to perform parallel program-
ming, the first step should be to set the E2PAR2
bit. From this time on, the EEPROM will be ad-
dressed in write mode, the ROW address will be
latched and it will be possible to change it only at
the end of the programming cycle, or by resetting
E2PAR2 without programming the EEPROM. Af-
ter the ROW address is latched, the MCU can only
“see” the selected EEPROM row and any attempt
to write or read other rows will produce errors.
—
Reset status: 00h
7
0
E2O
FF
E2PA E2PA E2BU E2E
R1 R2 SY NA
D7
D5
D4
D7
Bit 7 =
: Unused.
Bit 6 =E2OFF: Stand-by Enable Bit.WRITE ONLY.
If this bitis settheEEPROM is disabled (any access
will be meaningless) and the power consumption of
the EEPROM is reduced to its lowest value.
The EEPROM should not be read while E2PAR2
is set.
As soon as the E2PAR2 bit is set, the 8 volatile
ROW latches are cleared. From this moment on,
the user can load data in all or in part of the ROW.
Setting E2PAR1 will modify the EEPROM regis-
ters corresponding to the ROW latches accessed
after E2PAR2. For example, if the software sets
E2PAR2 and accesses the EEPROM by writing to
addresses 18h, 1Ah and 1Bh, and then sets
E2PAR1, these three registers will be modified si-
multaneously; the remaining bytes in the row will
be unaffected.
Bit 5-4 = D5-D4: Reserved. MUST be kept reset.
E2PAR1
Bit 3 =
: Parallel Start Bit. WRITE ONLY.
Once in Parallel Mode, as soonasthe user software
sets the E2PAR1 bit, parallel writing of the 8 adja-
cent registers will start. This bit is internally reset at
the end of the programming procedure. Note that
less than 8 bytes can be written if required, the un-
defined bytes being unaffected by the parallel pro-
gramming cycle; this is explained in greater detail in
the Additional Notes on Parallel Mode overleaf.
Note that E2PAR2 is internally reset at the end of
the programming cycle. This implies that the user
must set the E2PAR2 bit between two parallel pro-
gramming cycles. Note that if the user tries to set
E2PAR1 while E2PAR2 is not set, there will be no
programming cycle and the E2PAR1 bit will be un-
affected. Consequently, the E2PAR1 bit cannot be
set if E2ENA is low. The E2PAR1 bit can be set by
the user, only if the E2ENA and E2PAR2 bits are
also set.
Bit 2 = E2PAR2: Parallel Mode En. Bit. WRITE
ONLY. This bit must be set by the user program in
order to perform parallel programming. If E2PAR2
is set and the parallel start bit (E2PAR1) is reset,
up to 8 adjacent bytes can be written simultane-
ously. These 8 adjacent bytes are considered as a
row, whose address lines A7, A6, A5, A4, A3 are
fixed while A2, A1 and A0 are the changing bits, as
illustrated in Table 4. E2PAR2 is automatically re-
set at the end of any parallel programming proce-
dure. It can be reset by the user software before
starting the programming procedure, thus leaving
the EEPROM registers unchanged.
Bit 1 = E2BUSY: EEPROM Busy Bit. READ ON-
LY. This bit is automatically set by the EEPROM
control logic when the EEPROM is in program-
ming mode. The user program should test it before
any EEPROM read or write operation; any attempt
to access the EEPROM while the busy bit is set
will be aborted and the writing procedure in
progress will be completed.
Bit 0 = E2ENA: EEPROM Enable Bit.WRITE ON-
LY. This bit enables programming of the EEPROM
cells. It must be set before any write to the EEP-
ROM register. Any attempt to write to the EEP-
ROM when E2ENA is low is meaningless and will
not trigger a write cycle.
13/75
13
ST62T53B/T60B/T63B ST62E60B
1.4 PROGRAMMING MODES
1.4.1 Option Byte
lator must be controlled by an RC network, with
only the resistor having to be externally provided.
The Option Byte allows configuration capability to
the MCUs. Option byte’s content is automatically
read, and the selected options enabled, when the
chip reset is activated.
D0. Reserved. Must be cleared to zero.
The Option byte is written during programming ei-
ther by using the PC menu (PC driven Mode) or
automatically (stand-alone mode)
It can only be accessed during the programming
mode. This access is made either automatically
(copy from a master device) or by selecting the
OPTION BYTE PROGRAMMING mode of the pro-
grammer.
1.4.2 Program Memory
EPROM/OTP programming mode is set by a
+12.5V voltage applied to the TEST/V pin. The
PP
programming flow of the ST62E60B/T60B and
ST62T63B is described in the User Manual of the
EPROM Programming Board.
The option byte is located in a non-user map. No
address has to be specified.
EPROM Code Option Byte
The MCUs can be programmed with the
ST62E6xB EPROM programming tools available
from SGS-THOMSON.
7
0
-
PRO- EXTC- PB2-3 PB0-1
TECT NTL PULL PULL
WDACT DELAY OSCIL
Table 5.ST62E60B/T60B Program Memory Map
Device Address
Description
PROTECT. This bit allows the protection of the
software contents against piracy. When the bit
PROTECT is set high, readout of the OTP con-
tents is prevented by hardware. No programming
equipment is able to gain access to the user pro-
gram. When this bit is low, the user program can
be read.
0000h-007Fh
0080h-0F9Fh
0FA0h-0FEFh
0FF0h-0FF7h
0FF8h-0FFBh
0FFCh-0FFDh
0FFEh-0FFFh
Reserved
User ROM
Reserved
Interrupt Vectors
Reserved
NMI Interrupt Vector
Reset Vector
EXTCNTL
. This bit selects the External STOP
Table 6. ST62T53B/T63B Program
Memory Map
Mode capability. When EXTCNTL is high, pin NMI
controls if the STOP mode can be accessed when
the watchdog is active. In addition, PB0 is forced
as open drain output. When EXTCNTL is low, the
STOP instruction is processed as a WAIT as soon
as the watchdog is active.
Device Address
Description
0000h-087Fh
0880h-0F9Fh
0FA0h-0FEFh
0FF0h-0FF7h
0FF8h-0FFBh
0FFCh-0FFDh
0FFEh-0FFFh
Reserved
User ROM
Reserved
Interrupt Vectors
PB2-3 PULL
. When set this bit removes pull-up at
Reserved
NMI Interrupt Vector
Reset Vector
reset on PB2-PB3 pins. When cleared PB2-PB3
pins have an internal pull-up resistor at reset.
PB0-1 PULL
reset on PB0-PB1 pins. When cleared PB0-PB1
pins have an internal pull-up resistor at reset.
. When set this bit removes pull-up at
Note: OTP/EPROM devices can be programmed
with the development tools available from
WDACT
. This bit controls the watchdog activation.
SGS-THOMSON
ST626X-KIT).
(ST62E6X-EPB
or
When it is high, hardware activation is selected.
The software activation is selected when WDACT
is low.
DELAY. This bit enables the selection of the delay
internally generated after pin RESET is released.
When DELAY is low, the delay is 2048 cycles of
the oscillator, it is of 32768 cycles when DELAY is
high.
1.4.3 EEPROM Data Memory (except ST62T53B)
EEPROM datapages are supplied inthevirgin state
FFh. Partial or total programming of EEPROM data
memory can be performed either through the appli-
cation software, or through an external program-
mer. Any SGS-THOMSON tool used for the pro-
gram memory (OTP/EPROM) can also be used to
program the EEPROM data memory.
OSCIL
. When this bit is low, the oscillator must be
controlled by a quartz crystal, a ceramic resonator
or an external frequency. When it is high, the oscil-
14/75
14
ST62T53B/T60B/T63B ST62E60B
PROGRAMMING MODES(Cont’d)
1.4.4 EPROM Erasing
prevent unintentional erasure problems when test-
ing the application in such an environment.
The EPROM of the windowed package of the
MCUs may be erased by exposure to Ultra Violet
light. The erasure characteristic of the MCUs is
such that erasure begins when the memory is ex-
posed to light with a wave lengths shorter than ap-
proximately 4000Å. It should be noted that sun-
lights and some types of fluorescent lamps have
wavelengths in the range 3000-4000Å.
The recommended erasure procedure of the
MCUs EPROM is the exposure to short wave ul-
traviolet light which have a wave-length 2537A.
The integrated dose (i.e. U.V. intensity x exposure
time) for erasure should be a minimum of 15W-
2
sec/cm . The erasure time with this dosage is ap-
proximately 15 to 20 minutes using an ultraviolet
2
lamp with 12000µW/cm power rating. The
It is thus recommended that the window of the
MCUs packages be covered by an opaque label to
ST62E60B should be placed within 2.5cm (1Inch)
of the lamp tubes during erasure.
15/75
15
ST62T53B/T60B/T63B ST62E60B
2 CENTRAL PROCESSING UNIT
2.1 INTRODUCTION
The CPU Core of ST6 devices is independent of the
I/O or Memory configuration. As such, it may be
thought of as an independent central processor
communicating with on-chip I/O, Memory and Pe-
ripherals via internal address, data, and control
buses. In-core communication is arranged as
shown in Figure 7; the controller being externally
linked to both the Reset and Oscillator circuits,
while the core is linked to the dedicated on-chip pe-
ripherals via the serial data bus and indirectly, for
interrupt purposes, through the control registers.
Indirect Registers (X, Y).These two indirect reg-
isters are used as pointers to memory locations in
Data space. They are used in the register-indirect
addressing mode. These registers can be ad-
dressed in the data space as RAM locations at ad-
dresses 80h (X) and 81h (Y). They can also be ac-
cessed with the direct, short direct, or bit direct ad-
dressing modes. Accordingly, the ST6 instruction
set can use the indirect registers as any other reg-
ister of the data space.
Short Direct Registers (V, W). These two regis-
ters are used to save a byte in short direct ad-
dressing mode. They can be addressed in Data
space as RAM locations at addresses 82h (V) and
83h (W). They can also be accessed using the di-
rect and bit direct addressing modes. Thus, the
ST6 instruction set can use the short direct regis-
ters as any other register of the data space.
2.2 CPU REGISTERS
The ST6 Family CPU core featuressixregisters and
three pairs of flags available to the programmer.
These are described in the following paragraphs.
Accumulator (A). The accumulator is an 8-bit
general purpose register used in all arithmetic cal-
culations, logical operations, and data manipula-
tions. The accumulator can be addressed in Data
space as a RAM location at address FFh. Thus the
ST6 can manipulate the accumulator just like any
other register in Data space.
Program Counter (PC). The program counter is a
12-bit register which contains the address of the
next ROM location to be processed by the core.
This ROM location may be an opcode, an oper-
and, or the address of an operand. The 12-bit
length allows the direct addressing of 4096 bytes
in Program space.
Figure 7. ST6 Core Block Diagram
0,01 TO 8MHz
RESET
OSCin
OSCout
INTERRUPTS
CONTROLLER
DATA SPACE
DATA
CONTROL
SIGNALS
FLAG
VALUES
OPCODE
ADDRESS/READ LINE
ADDRESS
2
RAM/EEPROM
PROGRAM
DATA
ROM/EPROM
256
ROM/EPROM
DECODER
B-DATA
A-DATA
DEDICATIONS
ACCUMULATOR
Program Counter
and
12
FLAGS
6 LAYER STACK
ALU
RESULTS TO DATA SPACE (WRITE LINE)
VR01811
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ST62T53B/T60B/T63B ST62E60B
CPU REGISTERS (Cont’d)
However, if the program space contains more than
4096 bytes, the additional memory in program
space can be addressed by using the Program
Bank Switch register.
automatically selected after the reset of the MCU,
the ST6 core uses at first the NMI flags.
Stack. The ST6 CPU includes a true LIFO hard-
ware stack which eliminates the need for a stack
pointer. The stack consists of six separate 12-bit
RAM locations that do not belong to the data
space RAM area. When a subroutine call (or inter-
rupt request) occurs, the contents of each level are
shifted into the next higher level, while the content
of the PC is shifted into the first level (the original
contents of the sixth stack level are lost). When a
subroutine or interrupt return occurs (RET or RETI
instructions), the first level register is shifted back
into the PC and the value of each level is popped
back into the previous level. Since the accumula-
tor, in common with all other data space registers,
is not stored in this stack, management of these
registers should be performed within the subrou-
tine. The stack will remain in its “deepest” position
if more than 6 nested calls or interrupts are execut-
ed, and consequently the last return address will
be lost. It will also remain in its highest position if
the stack is empty and a RET or RETI is executed.
In this case the next instruction will be executed.
The PC value is incremented after reading the ad-
dress of the current instruction. To execute relative
jumps, the PC and the offset are shifted through
the ALU, where they are added; the result is then
shifted back into the PC. The program counter can
be changed in the following ways:
- JP (Jump) instructionPC=Jump address
- CALL instructionPC= Call address
- Relative Branch Instruction.PC= PC +/- offset
- Interrupt
- Reset
PC=Interrupt vector
PC= Reset vector
- RET & RETI instructionsPC= Pop (stack)
- Normal instructionPC= PC + 1
Flags (C, Z). The ST6 CPU includes three pairs of
flags (Carry and Zero), each pair being associated
with one of the three normal modes of operation:
Normal mode, Interrupt mode and Non Maskable
Interrupt mode. Each pair consists of a CARRY
flag and a ZERO flag. One pair (CN, ZN) is used
during Normal operation, another pair is used dur-
ing Interrupt mode (CI, ZI), and a third pair is used
in the Non Maskable Interrupt mode (CNMI, ZN-
MI).
Figure 8. ST6 CPU Programming Mode
l
b7 X REG. POINTER b0
INDEX
REGISTER
SHORT
DIRECT
ADDRESSING
b7 Y REG. POINTER b0
The ST6 CPU uses the pair of flags associated
with the current mode: as soon as an interrupt (or
a Non Maskable Interrupt) is generated, the ST6
CPU uses the Interrupt flags (resp. the NMI flags)
instead of the Normal flags. When the RETI in-
struction is executed, the previously used set of
flags is restored. It should be noted that each flag
set can only be addressed in its own context (Non
Maskable Interrupt, Normal Interrupt or Main rou-
tine). The flags are not cleared during context
switching and thus retain their status.
MODE
b7
b7
V REGISTER
W REGISTER
b0
b0
b7 ACCUMULATOR
PROGRAM COUNTER
b0
b0
b11
SIX LEVELS
STACK REGISTER
The Carry flag is set when a carry or a borrow oc-
curs during arithmetic operations; otherwise it is
cleared. The Carry flag is also set to the value of
the bit tested in a bit test instruction; it also partici-
pates in the rotate left instruction.
NORMAL FLAGS
INTERRUPT FLAGS
NMI FLAGS
C
C
C
Z
Z
Z
The Zero flag is set if the result of the last arithme-
tic or logical operation was equal to zero; other-
wise it is cleared.
Switching between the three sets of flags is per-
formed automatically when an NMI, an interrupt or
a RETI instructions occurs. As the NMI mode is
VA000423
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ST62T53B/T60B/T63B ST62E60B
3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES
3.1 CLOCK SYSTEM
The MCU features a Main Oscillator which can be
driven by an external clock, or used in conjunction
with an AT-cut parallel resonant crystal or a suita-
ble ceramic resonator, or with an external resistor
Figure 9. Oscillator Configurations
CRYSTAL/RESONATOR CLOCK
CRYSTAL/RESONATOR option
(R
).
NET
Figure 9 illustrates various possible oscillator con-
figurations using an external crystal or ceramic res-
onator, an external clock input, an external resistor
ST6xxx
(R
). C anC should have a capacitance in the
OSC
out
OSC
NET
L1 L2
in
range 12 to 22 pF for an oscillator frequency in the
4-8 MHz range.
Aprogrammable divider isprovidedin ordertoadjust
the internal clock of the MCU to the best power con-
sumption and performance trade-off.
C
C
L1n
L2
The internal MCU clock frequency (f ) drives di-
INT
rectly the AR TIMER while it is divided by 12 to
drive the TIMER, the A/D converter and the
Watchdog timer, and by 13 to drive the CPU core,
as may be seen in Figure 10.
EXTERNAL CLOCK
CRYSTAL/RESONATOR option
With an 8MHz oscillator frequency, the fastest ma-
chine cycle is therefore 1.625µs.
A machine cycle is the smallest unit of time needed
to execute any operation (for instance, to increment
the Program Counter). An instruction may require
two, four, or five machine cycles for execution.
ST6xxx
OSC
OSC
out
in
3.1.1 Main Oscillator
NC
The oscillator configuration may be specified by se-
lecting theappropriate option. WhentheCRYSTAL/
RESONATORoptionisselected,itmustbeusedwith
a quartz crystal, a ceramic resonator or an external
signalprovided ontheOSCinpin.WhentheRCNET-
WORK option is selected, the system clock is gen-
erated by an external resistor.
RC NETWORK
RC NETWORK option
ST6xxx
OSC
OSC
in
out
NC
R
NET
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ST62T53B/T60B/T63B ST62E60B
CLOCK SYSTEM (Cont’d)
Oscillator Control Registers
Note: Care is required when handling the OSCR
register as some bits are write only. For this rea-
son, it is not allowed to change the OSCR contents
while executing interrupt service routine, as the
service routine cannot save and then restore its
previous content. If it is impossible to avoid the
writing of this register in interrupt service routine,
an image of this register must be saved in a RAM
location, and each time the program writes to
OSCR it must write also to the image register. The
image register must be written first, so if an inter-
rupt occurs between the two instructions the
OSCR is not affected.
Address: DCh
—
Write only
7
0
OSCR OSCR
3
-
-
-
-
RS1
RS0
2
Bit 7-4. These bits are not used.
Bit 3. Reserved. Cleared at Reset. THIS BIT
MUST BE SET TO 1 BY USER PROGRAM to
achieve lowest power consumption.
Bit 2. Reserved. Must be kept low.
RS1-RS0. These bits select the division ratio of
the Oscillator Divider in order to generate the inter-
nal frequency. The following selctions are availa-
ble:
RS1
RS0
Division Ratio
0
0
1
1
0
1
0
1
1
2
4
4
Figure 10. Clock Circuit Block Diagram
POR
Core
f
OSC
OSCin
: 13
f
SPI
OSC
Timer
f
MAIN
OSCILLATOR
INT
OSCILLATOR
DIVIDER
Watchdog
: 12
ADC
AR Timer
: 1
OSCout
RS0, RS1
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ST62T53B/T60B/T63B ST62E60B
3.2 RESETS
The MCU can be reset in three ways:
– by the external Reset input being pulled low;
– by Power-on Reset;
The internal delay is generated by an on-chip coun-
ter. The internal reset line is released 2048 internal
clock cycles after release of the external reset.
Notes:
– by the digital Watchdog peripheral timing out.
3.2.1 RESET Input
To ensure correct start-up, the user should take
care that the reset signal is not released before the
The RESET pin may be connected to a device of
the application board in order to reset the MCU if
required. The RESET pin may be pulled low in
RUN, WAIT or STOP mode. This input can be
used to reset the MCU internal state and ensure a
correct start-up procedure. The pin is active low
and features a Schmitt trigger input. The internal
Reset signal is generated by adding a delay to the
external signal. Therefore even short pulses on
V
level is sufficient to allow MCU operation at
DD
the chosen frequency (see Recommended Oper-
ating Conditions).
A proper reset signal for a slow rising V supply
can generally be provided by an external RC net-
work connected to theRESET pin.
DD
Figure 11. . Reset and Interrupt Processing
the RESET pin are acceptable, provided V has
DD
RESET
completed its rising phase and that the oscillator is
running correctly (normal RUN or WAIT modes).
The MCU is kept in the Reset state as long as the
RESET pin is held low.
NMI MASK SET
INT LATCH CLEARED
( IF PRESENT )
If RESET activation occurs in the RUN or WAIT
modes, processing of the user program is stopped
(RUN mode only), the Inputs and Outputs are con-
figured as inputs with pull-up resistors and the
main Oscillator is restarted. When the level on the
RESET pin then goes high, the initialization se-
quence is executed following expiry of the internal
delay period.
SELECT
NMI MODE FLAGS
PUT FFEH
If RESET pin activation occurs in the STOP mode,
the oscillator starts up and all Inputs and Outputs
are configured as inputs with pull-up resistors.
When the level of the RESET pin then goes high,
the initialization sequence is executed following
expiry of the internal delay period.
ON ADDRESS BUS
YES
IS RESET STILL
PRESENT?
3.2.2 Power-on Reset
The function of the POR circuit consists in waking
up the MCU at an appropriate stage during the
power-on sequence. At the beginning of this se-
quence, the MCU is configured in the Reset state:
all I/O ports are configured as inputs with pull-up
resistors and no instruction is executed. When the
power supply voltage rises to a sufficient level, the
oscillator starts to operate, whereupon an internal
delay is initiated, in order to allow the oscillator to
fully stabilize before executing the first instruction.
The initialization sequence is executed immediate-
ly following the internal delay.
NO
LOAD PC
FROM RESET LOCATIONS
FFE/FFF
FETCH INSTRUCTION
VA000427
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ST62T53B/T60B/T63B ST62E60B
RESETS (Cont’d)
3.2.3 Watchdog Reset
in Non Maskable Interrupt mode; this prevents the
initialisation routine from being interrupted. The in-
itialisation routine should therefore be terminated
by a RETI instruction, in order to revert to normal
mode and enable interrupts. If no pending interrupt
is present at the end of the initialisation routine, the
MCU will continue by processing the instruction
immediately following the RETI instruction. If, how-
ever, a pending interrupt is present, it will be serv-
iced.
The MCU provides a Watchdog timer function in
order to ensure graceful recovery from software
upsets. If the Watchdog register is not refreshed
before an end-of-count condition is reached, the
internal reset will be activated. This, amongst oth-
er things, resets the watchdog counter.
The MCU restarts just as though the Reset had
been generated by the RESET pin, including the
built-in stabilisation delay period.
Figure 12. . Reset and Interrupt Processing
3.2.4 Application Notes
No external resistor is required between V and
the Reset pin, thanks to the built-in pull-up device.
DD
RESET
The POR circuit operates dynamically, in that it
triggers MCU initialization on detecting the rising
JP:2 BYTES/4 CYCLES
JP
edge of V . The typical threshold is in the region
DD
RESET
VECTOR
of 2 volts, but the actual value of the detected
threshold depends on the way in which V rises.
DD
The POR circuit is NOT designed to supervise
static, or slowly rising or falling V
.
DD
3.2.5 MCU Initialization Sequence
INITIALIZATION
ROUTINE
When a reset occurs the stack is reset, the PC is
loaded with the address of the Reset Vector (locat-
ed in program ROM starting at address 0FFEh). A
jump to the beginning of the user program must be
coded at this address. Following a Reset, the In-
terrupt flag is automatically set, so that the CPU is
RETI: 1 BYTE/2 CYCLES
RETI
VA00181
Figure 13. . Reset Block Diagram
V
DD
ST6
INTERNAL
RESET
f
CK
OSC
300kΩ
COUNTER
RESET
RESET
RESET
2.8kΩ
ON RESET
POWER
WATCHDOG RESET
VA0200B
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ST62T53B/T60B/T63B ST62E60B
RESETS (Cont’d)
Table 7. Register Reset Status
Register
Address(es)
Status
Comment
Oscillator Control Register
EEPROM Control Register
Port Data Registers
0DCh
0EAh
fINT = fOSC; user must set bit 3 to 1
EEPROM disabled (if available)
I/O are Input with pull-up
I/O are Input with pull-up
I/O are Input with pull-up
Interrupt disabled
0C0h to 0C2h
0C4h to 0C6h
0CCh to 0CEh
0C8h
Port Direction Register
Port Option Register
Interrupt Option Register
TIMER Status/Control
0D4h
00h
TIMER disabled
AR TIMER Mode Control Register
0D5h
AR TIMER stopped
AR TIMER Status/Control 1 Register 0D6h
AR TIMER Status/Control 2Register 0D7h
AR TIMER Compare Register
0DAh
Miscellaneous Register
SPI Registers
0DDh
SPI Output not connected to PC3
SPI disabled
0E0h to 0E2h
X, Y, V, W, Register
Accumulator
080H TO 083H
0FFh
Data RAM
084h to 0BFh
0E8h
Data RAM Page REgister
Data ROM Window Register
EEPROM
0C9h
Undefined
00h to 03Fh
0D0h
As written if programmed
A/D Result Register
AR TIMER Load Register
0DBh
AR TIMER Reload/Capture Register 0D9h
TIMER Counter Register
TIMER Prescaler Register
Watchdog Counter Register
A/D Control Register
0D3h
0D2h
0D8h
0D1h
FFh
7Fh
FEh
40h
Max count loaded
A/D in Standby
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ST62T53B/T60B/T63B ST62E60B
3.3 DIGITAL WATCHDOG
The digital Watchdog consists of a reloadable
downcounter timer which can be used to provide
controlled recovery from software upsets.
When the Watchdog is disabled, low power Stop
mode is available. Once activated, the Watchdog
cannot be disabled, except by resetting the MCU.
The Watchdog circuit generates a Reset when the
downcounter reaches zero. User software can
prevent this reset by reloading the counter, and
should therefore be written so that the counter is
regularly reloaded while the user program runs
correctly. In the event of a software mishap (usual-
ly caused by externally generated interference),
the user program will no longer behave in its usual
fashion and the timer register will thus not be re-
loaded periodically. Consequently the timer will
decrement down to 00h and reset the MCU. In or-
der to maximise the effectiveness of the Watchdog
function, user software must be written with this
concept in mind.
In the HARDWARE option, the Watchdog is per-
manently enabled. Since the oscillator will run con-
tinuously, low power mode is not available. The
STOP instruction is interpreted as a WAIT instruc-
tion, and the Watchdog continues to countdown.
However, when the EXTERNAL STOP MODE
CONTROL option has been selected low power
consumption may be achieved in Stop Mode.
Execution of the STOP instruction is then gov-
erned by a secondary function associated with the
NMI pin. If a STOP instruction is encountered
when the NMI pin is low, it is interpreted as WAIT,
as described above. If, however, the STOP in-
struction is encountered when the NMI pin is high,
the Watchdog counter is frozen and the CPU en-
ters STOP mode.
Watchdog behaviour is governed by two options,
known as “WATCHDOG ACTIVATION” (i.e.
HARDWARE or SOFTWARE) and “EXTERNAL
STOP MODE CONTROL” (seeTable 8).
When the MCU exits STOP mode (i.e. when an in-
terrupt is generated), the Watchdog resumes its
activity.
In the SOFTWARE option, the Watchdog is disa-
bled until bit C of the DWDR register has been set.
Table 8. Recommended Option Choices
Functions Required
Stop Mode & Watchdog
Stop Mode
Recommended Options
“EXTERNAL STOP MODE” & “HARDWARE WATCHDOG”
“SOFTWARE WATCHDOG”
Watchdog
“HARDWARE WATCHDOG”
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ST62T53B/T60B/T63B ST62E60B
DIGITAL WATCHDOG (Cont’d)
The Watchdog is associated with a Data space
register (Digital WatchDog Register, DWDR, loca-
tion 0D8h) which is described in greater detail in
Section 3.3.1 Digital Watchdog Register (DWDR).
This register is set to 0FEh on Reset: bit C is
cleared to “0”, which disables the Watchdog; the
timer downcounter bits, T0 to T5, and the SR bit
are all set to “1”, thus selecting the longest Watch-
dog timer period. This time period can be set to the
user’s requirements by setting the appropriate val-
ue for bits T0 to T5 in the DWDR register. The SR
bit must be set to “1”, since it is this bit which gen-
erates the Reset signal when it changes to “0”;
clearing this bit would generate an immediate Re-
set.
Figure 14. Watchdog Counter Control
D0
C
D1
SR
RESET
D2
D3
D4
D5
D6
D7
T5
T4
T3
T2
T1
T0
It should be noted that the order of the bits in the
DWDR register is inverted with respect to the as-
sociated bits in the down counter: bit 7 of the
DWDR register corresponds, in fact, to T0 and bit
2 to T5. The user should bear in mind the fact that
these bits are inverted and shifted with respect to
the physical counter bits when writing to this regis-
ter. The relationship between the DWDR register
bits and the physical implementation of the Watch-
dog timer downcounter is illustrated inFigure 14.
Only the 6 most significant bits may be used to de-
fine the time period, since it is bit 6 which triggers
the Reset when it changes to “0”. This offers the
user a choice of 64 timed periods ranging from
3,072 to 196,608 clock cycles (with an oscillator
frequency of 8MHz, this is equivalent to timer peri-
ods ranging from 384µs to 24.576ms).
8
÷
2
÷
OSC 12
VR02068A
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ST62T53B/T60B/T63B ST62E60B
DIGITAL WATCHDOG (Cont’d)
3.3.1 Digital Watchdog Register (DWDR)
3.3.2 Application Notes
Address: 0D8h
—
Read/Write
The Watchdog plays an important supporting role
in the high noise immunity of ST62xx devices, and
should be used wherever possible. Watchdog re-
lated options should be selected on the basis of a
trade-off between application security and STOP
mode availability.
Reset status: 1111 1110b
7
0
T0
T1
T2
T3
T4
T5
SR
C
When STOP mode is not required, hardware acti-
vation without EXTERNAL STOP MODE CON-
TROL should be preferred, as it provides maxi-
mum security, especially during power-on.
Bit 0 = C: Watchdog Control bit
If the hardware option is selected, this bit is forced
high and the user cannot change it (the Watchdog
is always active). When the software option is se-
lected, the Watchdog function is activated by set-
ting bit C to 1, and cannot then be disabled (save
by resetting the MCU).
When STOP mode is required, hardware activa-
tion and EXTERNAL STOP MODE CONTROL
should be chosen. NMI should be high by default,
to allow STOP mode to be entered when the MCU
is idle.
When C is kept low the counter can be used as a
7-bit timer.
The NMI pin can be connected to an I/O line (see
Figure 15) to allow its state to be controlled by soft-
ware. The I/O line can then be used to keep NMI
low while Watchdog protection is required, or to
avoid noise or key bounce. When no more
processing is required, the I/O line is released and
the device placed in STOP mode for lowest power
consumption.
This bit is cleared to “0” on Reset.
SR
: Software Reset bit
Bit 1 =
This bit triggers a Reset when cleared.
When C = “0” (Watchdog disabled) it is the MSB of
the 7-bit timer.
This bit is set to “1” on Reset.
When software activation is selected and the
Watchdog is not activated, the downcounter may
be used as a simple 7-bit timer (remember that the
bits are in reverse order).
Bits 2-7 = T5-T0: Downcounter bits
It should be noted that the register bits are re-
versed and shifted with respect to the physical
counter: bit-7 (T0) is the LSB of the Watchdog
downcounter and bit-2 (T5) is the MSB.
The software activation option should be chosen
only when the Watchdog counter is to be used as
a timer. To ensure the Watchdog has not been un-
expectedly activated, the following instructions
should be executed within the first 27 instructions:
These bits are set to “1” on Reset.
jrr 0, WD, #+3
ldi WD, 0FDH
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ST62T53B/T60B/T63B ST62E60B
DIGITAL WATCHDOG (Cont’d)
These instructions test the C bit and Reset the
MCU (i.e. disable the Watchdog) if the bit is set
(i.e. if the Watchdog is active), thus disabling the
Watchdog.
Figure 15. A typical circuit making use of the
EXERNAL STOP MODE CONTROL feature
In all modes, a minimum of 28 instructions are ex-
ecuted after activation, before the Watchdog can
generate a Reset. Consequently, user software
should load the watchdog counter within the first
27 instructions following Watchdog activation
(software mode), or within the first 27 instructions
executed following a Reset (hardware activation).
SWITCH
NMI
I/O
It should be noted that when the GEN bit is low (in-
terrupts disabled), the NMI interrupt is active but
cannot cause a wake up from STOP/WAIT modes.
VR02002
Figure 16. Digital Watchdog Block Diagram
RESET
Q
RSFF
7
8
-2
-2
-12
R
SET
S
DB1.7 LOAD SET
OSCILLATOR
CLOCK
8
DB0
WRITE
RESET
DATA BUS
VA00010
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ST62T53B/T60B/T63B ST62E60B
3.4 INTERRUPTS
The CPU can manage four Maskable Interrupt
sources, in addition to a Non Maskable Interrupt
source (top priority interrupt). Each source is asso-
ciated with a specific Interrupt Vector which con-
tains a Jump instruction to the associated interrupt
service routine. These vectors are located in Pro-
gram space (seeTable 9).
ically reset by the core at the beginning of the non-
maskable interrupt service routine.
Interrupt request from source #1 can be config-
ured either as edge or level sensitive by setting ac-
cordingly the LES bit of the Interrupt Option Regis-
ter (IOR).
Interrupt request from source #2 are always edge
sensitive. The edge polarity can be configured by
setting accordingly the ESB bit of the Interrupt Op-
tion Register (IOR).
When an interrupt source generates an interrupt
request, and interrupt processing is enabled, the
PC register is loaded with the address of the inter-
rupt vector (i.e. of the Jump instruction), which
then causes a Jump to the relevant interrupt serv-
ice routine, thus servicing the interrupt.
Interrupt request from sources #3 & #4 are level
sensitive.
In edge sensitive mode, a latch is set when a edge
occurs on the interrupt source line and is cleared
when the associated interrupt routine is started.
So, the occurrence of an interrupt can be stored,
until completion of the running interrupt routine be-
fore being processed. If several interrupt requests
occurs before completion of the running interrupt
routine, only the first request is stored.
Interrupt sources are linked to events either on ex-
ternal pins, or on chip peripherals. Several events
can be ORed on the same interrupt source, and
relevant flags are available to determine which
event triggered the interrupt.
The Non Maskable Interrupt request has the high-
est priority and can interrupt any interrupt routine
at any time; the other four interrupts cannot inter-
rupt each other. If more than one interrupt request
is pending, these are processed by the processor
core according to their priority level: source #1 has
the higher priority while source #4 the lower. The
priority of each interrupt source is fixed.
Storage of interrupt requests is not available in lev-
el sensitive mode. To be taken into account, the
low level must be present on the interrupt pin when
the MCU samples the line after instruction execu-
tion.
At the end of every instruction, the MCU tests the
interrupt lines: if there is an interrupt request the
next instruction is not executed and the appropri-
ate interrupt service routine is executed instead.
Table 9. Interrupt Vector Map
Interrupt Source
Interrupt source #0
Interrupt source #1
Interrupt source #2
Interrupt source #3
Interrupt source #4
Priority
Vector Address
(FFCh-FFDh)
(FF6h-FF7h)
(FF4h-FF5h)
(FF2h-FF3h)
(FF0h-FF1h)
1
2
3
4
5
Table 10. Interrupt Option Register Description
SET
Enable all interrupts
Disable all interrupts
GEN
CLEARED
Rising edge mode on inter-
rupt source #2
SET
ESB
3.4.1 Interrupt request
Falling edge mode on inter-
rupt source #2
CLEARED
SET
All interrupt sources but the Non Maskable Inter-
rupt source can be disabled by setting accordingly
the GEN bit of the Interrupt Option Register (IOR).
This GEN bit also defines if an interrupt source, in-
cluding the Non Maskable Interrupt source, can re-
start the MCU from STOP/WAIT modes.
Level-sensitive mode on in-
terrupt source #1
LES
Falling edge mode on inter-
rupt source #1
CLEARED
NOT USED
OTHERS
Interrupt request from the Non Maskable Interrupt
source #0 is latched by a flip flop which is automat-
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ST62T53B/T60B/T63B ST62E60B
IINTERRUPTS (Cont’d)
3.4.2 Interrupt Procedure
MCU
– Automatically the MCU switches back to the nor-
mal flag set (or the interrupt flag set) and pops
the previous PC value from the stack.
The interrupt procedure is very similar to a call pro-
cedure, indeed the user can consider the interrupt
as an asynchronous call procedure. As this is an
asynchronous event, the user cannot know the
context and the time at which it occurred. As a re-
sult, the user should save all Data space registers
which may be used within the interrupt routines.
There are separate sets of processor flags for nor-
mal, interrupt and non-maskable interrupt modes,
which are automatically switched and so do not
need to be saved.
The interrupt routine usually begins by the identify-
ing the device which generated the interrupt re-
quest (by polling). The user should save the regis-
ters which are used within the interrupt routine in a
software stack. After the RETI instruction is exe-
cuted, the MCU returns to the main routine.
Figure 17. Interrupt Processing Flow Chart
The following list summarizes the interrupt proce-
dure:
INSTRUCTION
MCU
FETCH
– The interrupt is detected.
INSTRUCTION
– The C and Z flags are replaced by the interrupt
flags (or by the NMI flags).
EXECUTE
– The PC contents are stored in the first level of
the stack.
INSTRUCTION
– The normal interrupt lines are inhibited (NMI still
active).
– The first internal latch is cleared.
LOAD PC FROM
INTERRUPT VECTOR
NO
WAS
(FFC/FFD)
THE INSTRUCTION
A RETI ?
–The associatedinterrupt vectorisloaded inthePC.
YES
IS THE CORE
ALREADY IN
NORMAL MODE?
SET
WARNING: In some circumstances, when a
maskable interrupt occurs while the ST6 core is in
NORMAL mode and especially during the execu-
tion of an ”ldi IOR, 00h” instruction (disabling all
maskable interrupts): if the interrupt arrives during
the first 3 cycles of the ”ldi” instruction (which is a
4-cycle instruction) the core will switch to interrupt
mode BUT the flags CN and ZN will NOT switch to
the interrupt pair CI and ZI.
YES
INTERRUPT MASK
?
NO
CLEAR
INTERRUPT MASK
PUSH THE
PC INTO THE STACK
SELECT
PROGRAM FLAGS
SELECT
INTERNAL MODE FLAG
User
”POP”
– User selected registers are saved within the in-
terrupt service routine (normally on a software
stack).
THE STACKED PC
CHECK IF THERE IS
AN INTERRUPT REQUEST
AND INTERRUPT MASK
NO
– The source of the interrupt is found by polling the
interrupt flags (if more than one source is associ-
ated with the same vector).
?
YES
VA000014
– The interrupt is serviced.
– Return from interrupt (RETI)
28/75
28
ST62T53B/T60B/T63B ST62E60B
IINTERRUPTS (Cont’d)
3.4.3 Interrupt Option Register (IOR)
Bit 5 = ESB: Edge Selection bit.
The Interrupt Option Register (IOR) is used to en-
able/disable the individual interrupt sources and to
select the operating mode of the external interrupt
inputs. This register is write-only and cannot be
accessed by single-bit operations.
The bit ESB selects the polarity of the interrupt
source #2.
Bit 4 = GEN: Global Enable Interrupt. When this bit
is set to one, all interrupts are enabled. When this
bit is cleared to zero all the interrupts (excluding
NMI) are disabled.
Address: 0C8h
— Write Only
Reset status: 00h
When the GEN bit is low, the NMI interrupt is ac-
tive but cannot cause a wake up from STOP/WAIT
modes.
7
0
-
This register is cleared on reset.
-
LES ESB GEN
-
-
-
3.4.4 Interrupt sources
Interrupt sources available on these MCUs are
summarized in the Table 11 with associated mask
bit to enable/disable the interrupt request.
Bit 7, Bits 3-0 = Unused.
LES Level/Edge Selection bit.
Bit 6 =
:
When this bit is set to one, the interrupt source #1
is level sensitive. When cleared to zero the edge
sensitive mode for interrupt request is selected.
Table 11. Interrupt Requests and Mask Bits
Address
Interrupt
vector
Peripheral
Register
Mask bit
GEN
Masked Interrupt Source
Register
GENERAL
TIMER
A/D CONVERTER ADCR
IOR
C8h
I
All Interrupts, excluding NM
TMZ: TIMER Overflow
TSCR1
D4h
D1h
ETI
EAI
Vector 4
Vector 4
EOC: End of Conversion
OVIE
CPIE
EIE
OVF: AR TIMER Overflow
CPF: Successful compare
EF: Active edge on ARTIMin
AR TIMER
ARMC
D5h
Vector 3
SPI
SPIMOD
E2h
SPIE
SPRUN: End of Transmission
Vector 2
Vector 1
Vector 1
Vector 2
Port PAn
Port PBn
Port PCn
ORPA-DRPA
ORPB-DRPB
ORPC-DRPC
C0h-C4h
C1h-C5h
C2h-C6h
ORPAn-DRPAn PAn pin
ORPBn-DRPBn PBn pin
ORPCn-DRPCn PCn pin
29/75
29
ST62T53B/T60B/T63B ST62E60B
INTERRUPTS (Cont’d)
Figure 18. Interrupt Block Diagram
FROM REGISTER PORT A,B,C
SINGLE BIT ENABLE
PBE
V
DD
PORT A
FF
CLK
CLR
Q
0
PBE
PORT B
Bits
INT #1 (FF6,7)
MUX
1
I
Start
1
RESTART FROM
STOP/WAIT
IOR REG. C8H, bit 6
FF
PORT C
Bits
INT #2 (FF4,5)
PBE
CLK
Q
CLR
SPIDIV Register
I
Start
2
SPINT bit
SPIE bit
IOR REG. C8H, bit 5
OVF
SPIMOD Register
OVIE
CPF
CPIE
INT #3 (FF2,3)
AR TIMER
EF
EIE
TMZ
ETI
TIMER1
ADC
INT #4 (FF0,1)
NMI (FFC,D)
V
DD
EOC
EAI
FF
CLK
CLR
Q
NMI
I Start
0
Bit GEN (IOR Register)
VA0426K
30/75
30
ST62T53B/T60B/T63B ST62E60B
3.5 POWER SAVING MODES
The WAIT and STOP modes have been imple-
mented in the ST62xx family of MCUs in order to
reduce the product’s electrical consumption during
idle periods. These two power saving modes are
described in the following paragraphs.
of the processor core prior to the WAIT instruction,
but also on the kind of interrupt request which is
generated. This is described in the following para-
graphs. The processor core does not generate a
delay following the occurrence of the interrupt, be-
cause the oscillator clock is still available and no
stabilisation period is necessary.
3.5.1 WAIT Mode
The MCU goes into WAIT mode as soon as the
WAIT instruction is executed. The microcontroller
can be considered as being in a “software frozen”
state where the core stops processing the pro-
gram instructions, the RAM contents and peripher-
al registers are preserved as long as the power
supply voltage is higher than the RAM retention
voltage. In this mode the peripherals are still ac-
tive.
3.5.2 STOP Mode
If the Watchdog is disabled, STOP mode is availa-
ble. When in STOP mode, the MCU is placed in
the lowest power consumption mode. In this oper-
ating mode, the microcontroller can be considered
as being “frozen”, no instruction is executed, the
oscillator is stopped, the RAM contents and pe-
ripheral registers are preserved as long as the
power supply voltage is higher than the RAM re-
tention voltage, and the ST62xx core waits for the
occurrence of an external interrupt request or a
Reset to exit the STOP state.
WAIT mode can be used when the user wants to
reduce the MCU power consumption during idle
periods, while not losing track of time or the capa-
bility of monitoring external events. The active os-
cillator is not stopped in order to provide a clock
signal to the peripherals. Timer counting may be
enabled as well as the Timer interrupt, before en-
tering the WAIT mode: this allows the WAIT mode
to be exited when a Timer interrupt occurs. The
same applies to other peripherals which use the
clock signal.
If the STOP state is exited due to a Reset (by acti-
vating the external pin) the MCU will enter a nor-
mal reset procedure. Behaviour in response to in-
terrupts depends on the state of the processor
core prior to issuing the STOP instruction, and
also on the kind of interrupt request that is gener-
ated.
If the WAIT mode is exited due to a Reset (either
by activating the external pin or generated by the
Watchdog), the MCU enters a normal reset proce-
dure. If an interrupt is generated during WAIT
mode, the MCU’s behaviour depends on the state
This case will be described in the following para-
graphs. The processor core generates a delay af-
ter occurrence of the interrupt request, in order to
wait for complete stabilisation of the oscillator, be-
fore executing the first instruction.
31/75
31
ST62T53B/T60B/T63B ST62E60B
POWER SAVING MODE(Cont’d)
3.5.3 Exit from WAIT and STOP Modes
– If the interrupt is a normal one, the interrupt rou-
tine in which the WAIT or STOP mode was en-
tered will be completed, starting with the
execution of the instruction which follows the
STOP or the WAIT instruction, and the MCU is
still in the interrupt mode. At the end of this rou-
tine pending interrupts will be serviced in accord-
ance with their priority.
The following paragraphs describe how the MCU
exits from WAIT and STOP modes, when an inter-
rupt occurs (not a Reset). It should be noted that
the restart sequence depends on the original state
of the MCU (normal, interrupt or non-maskable in-
terrupt mode) prior to entering WAIT or STOP
mode, as well as on the interrupt type.
– In the event of a non-maskable interrupt, the
non-maskable interrupt service routine is proc-
essed first, then the routine in which the WAIT or
STOP mode was entered will be completed by
executing the instruction following the STOP or
WAIT instruction. The MCU remains in normal in-
terrupt mode.
Interrupts do not affect the oscillator selection.
3.5.3.1 Normal Mode
If the MCU was in the main routine when the WAIT
or STOP instruction was executed, exit from Stop
or Wait mode will occur as soon as an interrupt oc-
curs; the related interrupt routine is executed and,
on completion, the instruction which follows the
STOP or WAIT instruction is then executed, pro-
viding no other interrupts are pending.
Notes:
To achieve the lowest power consumption during
RUN or WAIT modes, the user program must take
care of:
3.5.3.2 Non Maskable Interrupt Mode
If the STOP or WAIT instruction has been execut-
ed during execution of the non-maskable interrupt
routine, the MCU exits from the Stop or Wait mode
as soon as an interrupt occurs: the instruction
which follows the STOP or WAIT instruction is ex-
ecuted, and the MCU remains in non-maskable in-
terrupt mode, even if another interrupt has been
generated.
– configuring unused I/Os as inputs without pull-up
(these should be externally tied to well defined
logic levels);
– placing all peripherals in their power down
modes before entering STOP mode;
When the hardware activated Watchdog is select-
ed, or when the software Watchdog is enabled, the
STOP instruction is disabled and a WAIT instruc-
tion will be executed in its place.
3.5.3.3 Normal Interrupt Mode
If the MCU was in interrupt mode before the STOP
or WAIT instruction was executed, it exits from
STOP or WAIT mode as soon as an interrupt oc-
curs. Nevertheless, two cases must be consid-
ered:
If all interrupt sources are disabled (GEN low), the
MCU can only be restarted by a Reset. Although
setting GEN low does not mask the NMI as an in-
terrupt, it will stop it generating a wake-up signal.
The WAIT and STOP instructions are not execut-
ed if an enabled interrupt request is pending.
32/75
32
ST62T53B/T60B/T63B ST62E60B
4 ON-CHIP PERIPHERALS
4.1 I/O PORTS
The MCU features Input/Output lines which may
be individually programmed as any of the following
input or output configurations:
be also written by user software, in conjunction
with the related option registers, to select the dif-
ferent input mode options.
– Input without pull-up or interrupt
– Input with pull-up and interrupt
– Input with pull-up, but without interrupt
– Analog input
Single-bit operations on I/O registers are possible
but care is necessary because reading in input
mode is done from I/O pins while writing will direct-
ly affect the Port data register causing an unde-
sired change of the input configuration.
The Data Direction registers (DDRx) allow the
data direction (input or output) of each pin to be
set.
– Push-pull output
– Open drain output
The lines are organised as bytewise Ports.
The Option registers (ORx) are used to select the
different port options available both in input and in
output mode.
Each port is associated with 3 registers in Data
space. Each bit of these registers is associated
with a particular line (for instance, bits 0 of Port A
Data, Direction and Option registers are associat-
ed with the PA0 line of Port A).
All I/O registers can be read or written to just as
any other RAM location in Data space, so no extra
RAM cells are needed for port data storage and
manipulation. During MCU initialization, all I/O reg-
isters are cleared and the input mode with pull-ups
and no interrupt generation is selected for all the
pins, thus avoiding pin conflicts.
The DATA registers (DRx), are used to read the
voltage level values of the lines which have been
configured as inputs, or to write the logic value of
the signal to be output on the lines configured as
outputs. The port data registers can be read to get
the effective logic levels of the pins, but they can
Figure 19. I/O Port Block Diagram
RESET
V
DD
S
CONTROLS
IN
DATA
DIRECTION
REGISTER
V
DD
INPUT/OUTP UT
DATA
REGISTER
SHIFT
REGISTER
OPTION
REGISTER
S
OUT
TO INTERRUPT
TO ADC
VA00413
33/75
33
ST62T53B/T60B/T63B ST62E60B
I/O PORTS (Cont’d)
4.1.1 Operating Modes
4.1.1.2 Interrupt Options
Each pin may be individually programmed as input
or output with various configurations.
All input lines can be individually connected by
software to the interrupt system by programming
the OR and DR registers accordingly. The inter-
rupt trigger modes (falling edge, rising edge and
low level) can be configured by software as de-
scribed in the Interrupt Chapter for each port.
This is achieved by writing the relevant bit in the
Data (DR), Data Direction (DDR) and Option reg-
isters (OR). Table 12 illustrates the various port
configurations which can be selected by user soft-
ware.
4.1.1.3 Analog Input Options
4.1.1.1 Input Options
Some pins can be configured as analog inputs by
programming the OR and DR registers according-
ly. These analog inputs are connected to the on-
chip 8-bit Analog to Digital Converter.ONLY ONE
pin should be programmed as an analog input at
any time, since by selecting more than one input
simultaneously their pins will be effectively short-
ed.
Pull-up, High Impedance Option. All input lines
can be individually programmed with or without an
internal pull-up by programming the OR and DR
registers accordingly. If the pull-up option is not
selected, the input pin will be in the high-imped-
ance state.
Table 12. I/O Port Option Selection
DDR
OR
0
DR
0
Mode
Input
Option
0
0
0
0
1
1
With pull-up, no interrupt
0
1
Input
No pull-up, no interrupt
1
0
Input
With pull-up and with interrupt
1
1
Input
Analog input (when available)
0
X
X
Output
Output
Open-drain output (20mA sink when available)
Push-pull output (20mA sink when available)
1
Note: X = Don’t care
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34
ST62T53B/T60B/T63B ST62E60B
I/O PORTS (Cont’d)
4.1.2 Safe I/O State Switching Sequence
outputs, it is advisable to keep a copy of the data
register in RAM. Single bit instructions may then
be used on the RAM copy, after which the whole
copy register can be written to the port data regis-
ter:
Switching the I/O ports from one state to another
should be done in a sequence which ensures that
no unwanted side effects can occur. The recom-
mended safe transitions are illustrated in Figure
20. All other transitions are potentially risky and
should be avoided when changing the I/O operat-
ing mode, as it is most likely that undesirable side-
effects will be experienced, such as spurious inter-
rupt generation or two pins shorted together by the
analog multiplexer.
SET bit, datacopy
LD a, datacopy
LD DRA, a
Warning: Care must also be taken to not use in-
structions that act on a whole port register (INC,
DEC, or read operations) when all 8 bits are not
available on the device. Unavailable bits must be
masked by software (AND instruction).
Single bit instructions (SET, RES, INC and DEC)
should be used with great caution on Ports Data
registers, since these instructions make an implicit
read and write back of the entire register. In port
input mode, however, the data register reads from
the input pins directly, and not from the data regis-
ter latches. Since data register information in input
mode is used to set the characteristics of the input
pin (interrupt, pull-up, analog input), these may be
unintentionally reprogrammed depending on the
state of the input pins. As a general rule, it is better
to limit the use of single bit instructions on data
registers to when the whole (8-bit) port is in output
mode. In the case of inputs or of mixed inputs and
The WAIT and STOP instructions allow the
ST62xx to be used in situations where low power
consumption is needed. The lowest power con-
sumption is achieved by configuring I/Os in input
mode with well-defined logic levels.
The user must take care not to switch outputs with
heavy loads during the conversion of one of the
analog inputs in order to avoid any disturbance to
the conversion.
Figure 20. Diagram showing Safe I/O State Transitions
Interrupt
pull-up
Input
Analog
010*
011
001
Input
pull-up (Reset
state)
000
100
Input
Output
Open Drain
Output
Open Drain
101
111
Output
Push-pull
Output
Push-pull
110
Note *. xxx = DDR, OR, DR Bits respectively
35/75
35
ST62T53B/T60B/T63B ST62E60B
I/O PORTS (Cont’d)
Table 13. I/O Port Option Selections
MODE
AVAILABLE ON(1)
SCHEMATIC
PA0-PA3
Input
PB0-PB3, PB6-PB7
PC2-PC4
Data in
Interrupt
PA0-PA3
Input
PB0-PB3, PB6-PB7
PC2-PC4
Data in
with pull up
Interrupt
Input
PA0-PA3
with pull up
with interrupt
PB0-PB3, PB6-PB7
PC2-PC4
Data in
Interrupt
PA0-PA3
PC2-PC4
Analog Input
ADC
Open drain output
5mA
PA0-PA3
PC2-PC4
Data out
PB0-PB3, PB6-PB7
Open drain output
20mA
Push-pull output
5mA
PA0-PA3
PC2-PC4
Data out
PB0-PB3, PB6-PB7
Push-pull output
20mA
Note 1. Provided the correct configuration has
been selected.
36/75
36
ST62T53B/T60B/T63B ST62E60B
I/O PORTS (Cont’d)
Figure 21. Peripheral Interface Configuration of SPI, Timer 1 and AR Timer
V
DD
PP/OD
OUT
1
0
MUX
PC3/Sout
DR
b0
MISC.
REGISTER
OR
DR
IN
PC2/Sin
SPI
CLOCK IN
CLOCK OUT
1
0
MUX
PC4/SCK
DR
OR
SPCLK
MOD REGISTER
IN
OR
DR
TOUT
TIMER 1
OUT
1
0
MUX
PC1/TIM1
ARTIMin
ARTIMin
DR
AR TIMER
PWMOE
OR
PP/OD
ARTIMout
1
0
MUX
ARTIMout
DR
VR0C1661
37/75
37
ST62T53B/T60B/T63B ST62E60B
4.2 TIMER
The MCU features an on-chip Timer peripheral,
consisting of an 8-bit counter with a 7-bit program-
mable prescaler, giving a maximum count of 2 .
The prescaler input is the internal frequency (f )
INT
divided by 12. The prescaler decrements on the
rising edge. Depending on the division factor pro-
grammed by PS2, PS1 and PS0 bits in the TSCR
(see Figure 14), the clock input of the timer/coun-
ter register is multiplexed to different sources. For
division factor 1, the clock input of the prescaler is
also that of timer/counter; for factor 2, bit 0 of the
prescaler register is connected to the clock input of
TCR. This bit changes its state at half the frequen-
cy of the prescaler input clock. For factor 4, bit 1 of
the PSC is connected to the clock input of TCR,
and so forth. The prescaler initialize bit, PSI, in the
TSCR register must be set to allow the prescaler
(and hence the counter) to start. If it is cleared, all
the prescaler bits are set and the counter is inhib-
ited from counting. The prescaler can be loaded
with any value between 0 and 7Fh, if bit PSI is set.
The prescaler tap is selected by means of the
PS2/PS1/PS0 bits in the control register.
15
Figure 22 shows the Timer Block Diagram. The
content of the 8-bit counter can be read/written in
the Timer/Counter register, TCR, which can be ad-
dressed in Data space as a RAM location at ad-
dress 0D3h. The state of the 7-bit prescaler can be
read in the PSC register at address 0D2h. The
control logic device is managed in the TSCR reg-
ister as described in the following paragraphs.
The 8-bit counter is decrement by the output (ris-
ing edge) coming from the 7-bit prescaler and can
be loaded and read under program control. When
it decrements to zero then the TMZ (Timer Zero)bit
in the TSCR is set. If the ETI (Enable Timer Inter-
rupt) bit in the TSCR is also set, an interrupt re-
quest is generated. The Timer interrupt can be
used to exit the MCU from WAIT mode.
Figure 23 illustrates the Timer’s working principle.
Figure 22. Timer Block Diagram
.
DATA BUS
8
8
8
6
5
b7 b6 b5
b4 b3 b2 b1 b0
8-BIT
4
STATUS/CONTROL
REGISTER
SELECT
1 OF 7
3
2
1
0
PSC
TMZ ETI D5
D4 PSI PS2 PS1 PS0
f
INT
12
3
/
INTERRUPT
LINE
VR02070A
.
38/75
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ST62T53B/T60B/T63B ST62E60B
TIMER (Cont’d)
4.2.1 Timer Operation
zero, the TMZ bit in the TSCR register is set to
one.
The Timer prescaler is clocked by the prescaler
clock input (f
÷ 12).
4.2.3 Application Notes
INT
The user can select the desired prescaler division
ratio through the PS2, PS1, PS0 bits. When the
TCR count reaches 0, it sets the TMZ bit in the
TSCR. The TMZ bit can be tested under program
control to perform a timer function whenever it
goes high.
TMZ is set when the counter reaches zero; howev-
er, it may also be set by writing 00h in the TCR
register or by setting bit 7 of the TSCR register.
The TMZ bit must be cleared by user software
when servicing the timer interrupt to avoid unde-
sired interrupts when leaving the interrupt service
routine. After reset, the 8-bit counter register is
loaded with 0FFh, while the 7-bit prescaler is load-
ed with 07Fh, and the TSCR register is cleared.
This means that the Timer is stopped (PSI=“0”)
and the timer interrupt is disabled.
4.2.2 Timer Interrupt
When the counter register decrements to zero with
the ETI (Enable Timer Interrupt) bit set to one, an
interrupt request associated with Interrupt Vector
#3 is generated. When the counter decrements to
Figure 23. Timer Working Principle
7-BIT PRESCALER
BIT3
BIT0
BIT1
BIT2
BIT4
BIT5
BIT6
CLOCK
PS0
PS1
PS2
2
0
1
3
4
5
6
7
8-1 MULTIPLEXER
BIT7
BIT0
BIT1
BIT2
BIT3
BIT4
BIT5
BIT6
8-BIT COUNTER
VA00186
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39
ST62T53B/T60B/T63B ST62E60B
TIMER (Cont’d)
A write to the TCR register will predominate over
the 8-bit counter decrement to 00h function, i.e. if a
write and a TCR register decrement to 00h occur
simultaneously, the write will take precedence,
and the TMZ bit is not set until the 8-bit counter
reaches 00h again. The values of the TCR and the
PSC registers can be read accurately at any time.
PSI=“0” both counter and prescaler are not run-
ning.
Bit 2, 1, 0 = PS2, PS1, PS0: Prescaler Mux. Se-
lect.
These bits select the division ratio of the pres-
caler register.
Table 14. Prescaler Division Factors
PS2
0
PS1
0
PS0
0
Divided by
4.2.4 Timer Registers
1
2
0
0
1
Timer Status Control Register (TSCR)
0
1
0
4
Address: 0D4h
— Read/Write
0
1
1
8
7
0
1
0
0
16
32
64
128
1
0
1
TMZ
ETI
D5
D4
PSI
PS2
PS1
PS0
1
1
0
1
1
1
Bit 7 = TMZ: Timer Zero bit
A low-to-high transition indicates that the timer
count register has decrement to zero. This bit
must be cleared by user software before starting a
new count.
Timer Counter Register (TCR)
Address: 0D3h
—
Read/Write
7
0
Bit 6 = ETI: Enable Timer Interrup
D7
D6
D5
D4
D3
D2
D1
D0
When set, enables the timer interrupt request
(vector #3). If ETI=0 the timer interrupt is disabled.
If ETI=1 and TMZ=1 an interrupt request is gener-
ated.
Bit 7-0 = D7-D0: Counter Bits.
D5
Bit 5 =
: Reserved
Prescaler Register PSC
Must be set to “1”.
Bit 4 = D4
Address: 0D2h
—
Read/Write
7
0
Do not care.
Bit 3 = PSI: Prescaler Initialize Bit
D7
D6
D5
D4
D3
D2
D1
D0
Used to initialize the prescaler and inhibit its count-
ing. When PSI=“0” the prescaler is set to 7Fh and
the counter is inhibited. When PSI=“1” the prescal-
er is enabled to count downwards. As long as
D7
: Always read as ”0”.
Bit 7 =
Bit 6-0 = D6-D0: Prescaler Bits.
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ST62T53B/T60B/T63B ST62E60B
4.3 AUTO-RELOAD TIMER
The Auto-Reload Timer (AR Timer) on-chip pe-
ripheral consists of an 8-bit timer/counter with
compare and capture/reload capabilities and of a
7-bit prescaler with a clock multiplexer, enabling
the prescaler and counter contents are frozen.
When TEN is set, the AR counter runs at the rate
of the selected clock source. The counter is
cleared on system reset.
the clock input to be selected as f , f
or an
INT INT/3
The AR counter may also be initialized by writing
to the ARLR load register, which also causes an
immediate copy of the value to be placed in the AR
counter, regardless of whether the counter is run-
ning or not. Initialization of the counter, by either
method, will also clear the ARPSC register, where-
upon counting will start from a known value.
external clock source. A Mode Control Register,
ARMC, two Status Control Registers, ARSC0 and
ARSC1, an output pin, ARTIMout, and an input
pin, ARTIMin, allow the Auto-Reload Timer to be
used in 4 modes:
– Auto-reload (PWM generation),
4.3.2 Timer Operating Modes
– Output compare and reload on external event
(PLL),
Four different operating modes are available for
the AR Timer:
– Input capture and output compare for time meas-
urement.
Auto-reload Mode with PWM Generation.
This
– Input capture and output compare for period
measurement.
mode allows a Pulse Width Modulated signal to be
generated on the ARTIMout pin with minimum
Core processing overhead.
The AR Timer can be used to wake the MCU from
WAIT mode either with an internal or with an exter-
nal clock. It also can be used to wake the MCU
from STOP mode, if used with an external clock
signal connected to the ARTIMin pin. A Load reg-
ister allows the program to read and write the
counter on the fly.
The free running 8-bit counter is fed by the pres-
caler’s output, and is incremented on every rising
edge of the clock signal.
When a counter overflow occurs, the counter is
automatically reloaded with the contents of the Re-
load/Capture Register, ARCC, and ARTIMout is
set. When the counter reaches the value con-
tained in the compare register (ARCP), ARTIMout
is reset.
4.3.1 AR Timer Description
The AR COUNTER is an 8-bit up-counter incre-
mented on the input clock’s rising edge. The coun-
ter is loaded from the ReLoad/Capture Register,
ARRC, for auto-reload or capture operations, as
well as for initialization. Direct access to the AR
counter is not possible; however, by reading or
writing the ARLR load register, it is possible to
read or write the counter’s contents on the fly.
On overflow, the OVF flag of the ARSC0 register is
set and an overflow interrupt request is generated
if the overflow interrupt enable bit, OVIE, in the
Mode Control Register (ARMC), is set. The OVF
flag must be reset by the user software.
When the counter reaches the compare value, the
CPF flag of the ARSC0 register is set and a com-
pare interrupt request is generated, if the Compare
Interrupt enable bit, CPIE, in the Mode Control
Register (ARMC), is set. The interrupt service rou-
tine may then adjust the PWM period by loading a
new value into ARCP. The CPF flag must be reset
by user software.
The AR Timer’s input clock can be either the inter-
nal clock (from the Oscillator Divider), the internal
clock divided by 3, or the clock signal connected to
the ARTIMin pin. Selection between these clock
sources is effected by suitably programming bits
CC0-CC1 of the ARSC1 register. The output of the
AR Multiplexer feeds the 7-bit programmable AR
Prescaler, ARPSC, which selects one of the 8
available taps of the prescaler, as defined by
PSC0-PSC2 in the AR Mode Control Register.
Thus the division factor of the prescaler can be set
to 2n (where n = 0, 1,..7).
The PWM signal is generated on the ARTIMout
pin (refer to the Block Diagram). The frequency of
this signal is controlled by the prescaler setting
and by the auto-reload value present in the Re-
load/Capture register, ARRC. The duty cycle of
the PWM signal is controlled by the Compare Reg-
ister, ARCP.
The clock input to the AR counter is enabled by the
TEN (Timer Enable) bit in the ARMC register.
When TEN is reset, the AR counter is stopped and
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AUTO-RELOAD TIMER(Cont’d)
Figure 24. . AR Timer Block Diagram
DATA BUS
8
DDRB7
DRB7
AR COMPARE
REGISTER
8
PB7/
ARTIMout
CPF
COMPARE
8
R
S
PWMOE
OVF
OVF
f
INT
M
U
X
OVIE
8-Bit
7-Bit
f
/3
INT
AR PRESCALER
LOAD
AR COUNTER
TCLD
PS0-PS2
CC0-CC1
EIE
EF
AR TIMER
INTERRUPT
8
CPF
CPIE
8
8
PB6/
ARTIMin
SL0-SL1
AR
AR
EF
RELOAD/CAPTURE
REGISTER
LOAD
SYNCHRO
REGISTER
8
8
DATA BUS
VR01660A
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AUTO-RELOAD TIMER(Cont’d)
It should be noted that the reload values will also
affect the value and the resolution of the duty cycle
of PWM output signal. To obtain a signal on ARTI-
Mout, the contents of the ARCP register must be
greater than the contents of the ARRC register.
The ARTC counter is initialized by writing to the
ARRC register and by then setting the TCLD (Tim-
er Load) and the TEN (Timer Clock Enable) bits in
the Mode Control register, ARMC.
Enabling and selection of the clock source is con-
trolled by the CC0, CC1, SL0 and SL1 bits in the
Status Control Register, ARSC1. The prescaler di-
vision ratio is selected by the PS0, PS1 and PS2
bits in the ARSC1 register.
The maximum available resolution for the ARTI-
Mout duty cycle is:
Resolution = 1/[255-(ARRC)]
Where ARRC is the content of the Reload/Capture
register. The compare value loaded in the Com-
pare Register, ARCP, must be in the range from
(ARRC) to 255.
In Auto-reload Mode, any of the three available
clock sources can be selected: Internal Clock, In-
ternal Clock divided by 3 or the clock signal
present on the ARTIMin pin.
Figure 25. . Auto-reload Timer PWM Function
COUNTER
255
COMPARE
VALUE
RELOAD
REGISTER
000
t
PWM OUTPUT
t
VR001852
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AUTO-RELOAD TIMER(Cont’d)
Capture Mode with PWM Generation. In this
mode, the AR counter operates as a free running
8-bit counter fed by the prescaler output. The
counter is incremented on every clock rising edge.
the count is incremented on every clock rising
edge.
Each counter overflow sets the ARTIMout pin. A
match between the counter and ARCP (Compare
Register) resets the ARTIMout pin and sets the
compare flag, CPF. A compare interrupt request is
generated if the related compare interrupt enable
bit, CPIE, is set. A PWM signal is generated on
ARTIMout. The CPF flag must be reset by user
software.
An 8-bit capture operation from the counter to the
ARRC register is performed on every active edge
on the ARTIMin pin, when enabled by Edge Con-
trol bits SL0, SL1 in the ARSC1 register. At the
same time, the External Flag, EF, in the ARSC0
register is set and an external interrupt request is
generated if the External Interrupt Enable bit, EIE,
in the ARMC register, is set. The EF flag must be
reset by user software.
Initialization of the counter is as described in the
previous paragraph. In addition, if the external AR-
TIMin input is enabled, an active edge on the input
pin will copy the contents of the ARRC register into
the counter, whether the counter is running or not.
Each ARTC overflow sets ARTIMout, while a
match between the counter and ARCP (Compare
Register) resets ARTIMout and sets the compare
flag, CPF. A compare interrupt request is generat-
ed if the related compare interrupt enable bit,
CPIE, is set. A PWM signal is generated on ARTI-
Mout. The CPF flag must be reset by user soft-
ware.
Notes:
The allowed AR Timer clock sources are the fol-
lowing:
AR Timer Mode
Auto-reload mode
Capture mode
Clock Sources
f
f
f
f
, f
, ARTIMin
INT INT/3
The frequency of the generated signal is deter-
mined by the prescaler setting. The duty cycle is
determined by the ARCP register.
, f
INT INT/3
Capture/Reset mode
External Load mode
, f
INT INT/3
, f
INT INT/3
Initialization and reading of the counter are identi-
cal to the auto-reload mode (see previous descrip-
tion).
The clock frequency should not be modified while
the counter is counting, since the counter may be
set to an unpredictable value. For instance, the
multiplexer setting should not be modified while
the counter is counting.
Enabling and selection of clock sources is control-
led by the CC0 and CC1 bits in the AR Status Con-
trol Register, ARSC1.
Loading of the counter by any means (by auto-re-
load, through ARLR, ARRC or by the Core) resets
the prescaler at the same time.
The prescaler division ratio is selected by pro-
gramming the PS0, PS1 and PS2 bits in the
ARSC1 Register.
Care should be taken when both the Capture inter-
rupt and the Overflow interrupt are used. Capture
and overflow are asynchronous. If the capture oc-
curs when the Overflow Interrupt Flag, OVF, is
high (between counter overflow and the flag being
reset by software, in the interrupt routine), the Ex-
ternal Interrupt Flag, EF, may be cleared simul-
taneusly without the interrupt being taken into ac-
count.
In Capture mode, the allowed clock sources are
the internal clock and the internal clock divided by
3; the external ARTIMin input pin should not be
used as a clock source.
Capture Mode with Reset of counter and pres-
caler, and PWM Generation.This mode is identi-
cal to the previous one, with the difference that a
capture condition also resets the counter and the
prescaler, thus allowing easy measurement of the
time between two captures (for input period meas-
urement on the ARTIMin pin).
The solution consists in resetting the OVF flag by
writing 06h in the ARSC0 register. The value of EF
is not affected by this operation. If an interrupt has
occured, it will be processed when the MCU exits
from the interrupt routine (the second interrupt is
latched).
Load on External Input. The counter operates as
a free running 8-bit counter fed by the prescaler.
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AUTO-RELOAD TIMER(Cont’d)
4.3.3 AR Timer Registers
AR Mode Control Register (ARMC)
Address: D5h — Read/Write
Reset status: 00h
ARSC0 register is also set, an interrupt request is
generated.
Bit 1-0 = ARMC1-ARMC0: Mode Control Bits 1-0.
These are the operating mode control bits. The fol-
lowing bit combinations will select the various op-
erating modes:
7
0
ARMC1
ARMC0
Operating Mode
Auto-reload Mode
Capture Mode
TCLD
TEN PWMOE
EIE
CPIE OVIE ARMC1 ARMC0
0
0
0
1
The AR Mode Control Register ARMC is used to
program the different operating modes of the AR
Timer, to enable the clock and to initialize the
counter. It can be read and written to by the Core
and it is cleared on system reset (the AR Timer is
disabled).
Capture Mode with Reset
of ARTC and ARPSC
1
1
0
1
Load on External Edge
Mode
AR Timer Status/Control Registers ARSC0 &
ARSC1. These registers contain the AR Timer sta-
tus information bits and also allow the program-
ming of clock sources, active edge and prescaler
multiplexer setting.
TLCD
: Timer Load Bit. This bit, when set,
Bit 7 =
will cause the contents of ARRC register to be
loaded into the counter and the contents of the
prescaler register, ARPSC, are cleared in order to
initialize the timer before starting to count. This bit
is write-only and any attempt to read it will yield a
logical zero.
ARSC0 register bits 0,1 and 2 contain the interrupt
flags of the AR Timer. These bits are read normal-
ly. Each one may be reset by software. Writing a
one does not affect the bit value.
TEN: Timer Clock Enable. This bit, when
set, allows the timer to count. When cleared, it will
stop the timer and freeze ARPSC and ARTSC.
Bit 6 =
AR Status Control Register 0 (ARSC0)
Address: D6h
— Read/Clear
Bit 5 = PWMOE: PWM Output Enable. This bit,
when set, enables the PWM output on the ARTI-
Mout pin. When reset, the PWM output is disabled.
7
0
D7
D6
D5
D4
D3
EF
CPF
OVF
Bit 4 = EIE: External Interrupt Enable. This bit,
when set, enables the external interrupt request.
When reset, the external interrupt request is
masked. If EIE is set and the related flag, EF, in
the ARSC0 register is also set, an interrupt re-
quest is generated.
Bits 7-3 = D7-D3: Unused
Bit 2 = EF: External Interrupt Flag.This bit is set by
any active edge on the external ARTIMin input pin.
The flag is cleared by writing a zero to the EF bit.
Bit 3 = CPIE: Compare Interrupt Enable. This bit,
when set, enables the compare interrupt request.
If CPIE is reset, the compare interrupt request is
masked. If CPIE is set and the related flag, CPF, in
the ARSC0 register is also set, an interrupt re-
quest is generated.
Bit 1 = CPF: Compare Interrupt Flag.This bit is set
if the contents of the counter and the ARCP regis-
ter are equal. The flag is cleared by writing a zero
to the CPF bit.
Bit 0 = OVF: Overflow Interrupt Flag.This bit is set
by a transition of the counter from FFh to 00h
(overflow). The flag is cleared by writing a zero to
the OVF bit.
Bit 2 = OVIE: Overflow Interrupt. This bit, when
set, enables the overflow interrupt request. If OVIE
is reset, the compare interrupt request is masked.
If OVIE is set and the related flag, OVF in the
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AUTO-RELOAD TIMER(Cont’d)
AR Status Control Register 1(ARSC1)
Address: D7h — Read/Write
AR Load Register ARLR. The ARLR load register
is used to read or write the ARTC counter register
“on the fly” (while it is counting). The ARLR regis-
ter is not affected by system reset.
7
0
AR Load Register (ARLR)
PS2
PS1
PS0
D4
SL1
SL0
CC1
CC0
Address: DBh — Read/Write
Bist 7-5 = PS2-PS0: Prescaler Division Selection
Bits 2-0. These bits determine the Prescaler divi-
sion ratio. The prescaler itself is not affected by
these bits. The prescaler division ratio islisted inthe
following table:
7
0
D7
D6
D5
D4
D3
D2
D1
D0
D7-D0
: Load Register Data Bits. These
Bit 7-0 =
are the load register data bits.
Table 15. . Prescaler Division Ratio Selection
PS2
0
PS1
0
PS0
0
ARPSC Division Ratio
AR Reload/Capture Register
. The ARRC reload/
1
capture register is used to hold the auto-reload
value which is automatically loaded into the coun-
ter when overflow occurs.
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
2
4
8
AR Reload/Capture (ARRC)
16
32
64
128
Address: D9h
— Read/Write
7
0
D7
D6
D5
D4
D3
D2
D1
D0
D4
Bit 4 =
: Reserved. Must be kept reset.
Bit 7-0 = D7-D0: Reload/Capture Data Bits. These
are the Reload/Capture register data bits.
Bit 3-2 =SL1-SL0: Timer Input Edge Control Bits 1-
0. These bits control the edge function of the Timer
input pinfor external synchronization. Ifbit SL0 is re-
set, edge detection is disabled; if set edge detection
is enabled. If bit SL1 is reset, the AR Timer input pin
is rising edge sensitive; if set, it is falling edge sen-
sitive.
AR Compare Register. The CP compare register
is used to hold the compare value for the compare
function.
AR Compare Register (ARCP)
SL1
X
SL0
0
Edge Detection
Disabled
Address: DAh — Read/Write
0
1
Rising Edge
Falling Edge
7
0
1
1
D7
D6
D5
D4
D3
D2
D1
D0
CC1-CC0
Bit 1-0 =
: Clock Source Select Bit 1-0.
These bits select the clock source for the AR Timer
through the AR Multiplexer. The programming of
the clock sources is explained in the followingTable
16:
Bit 7-0 = D7-D0: Compare Data Bits. These are
the Compare register data bits.
Table 16. . Clock Source Selection.
CC1
CC0
Clock Source
0
0
1
1
0
1
0
1
Fint
Fint Divided by 3
ARTIMin Input Clock
Reserved
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4.4 A/D CONVERTER (ADC)
The A/D converter peripheral is an 8-bit analog to
digital converter with analog inputs as alternate I/O
functions (the number of which is device depend-
ent), offering 8-bit resolution with a typical conver-
sion time of 70us (at an oscillator clock frequency
of 8MHz).
sion to allow stabilisation of the A/D converter.
This action is also needed before entering WAIT
mode, since the A/D comparator is not automati-
cally disabled in WAIT mode.
During Reset, any conversion in progress is
stopped, the control register is reset to 40h and the
ADC interrupt is masked (EAI=0).
The ADC converts the input voltage by a process
of successive approximations, using a clock fre-
quency derived from the oscillator with a division
factor of twelve. With an oscillator clock frequency
less than 1.2MHz, conversion accuracy is de-
creased.
Figure 26. ADC Block Diagram
INTERRUPT
CLOCK
Selection of the input pin is done by configuring
the related I/O line as an analog input via the Op-
tion and Data registers (refer to I/O ports descrip-
tion for additional information). Only one I/O line
must be configured as an analog input at any time.
The user must avoid any situation in which more
than one I/O pin is selected as an analog input si-
multaneously, to avoid device malfunction.
Ain
CONVERTER
RESET
AV
AV
DD
SS
RESULT REGISTER
8
CONTROL REGISTER
8
The ADC uses two registers in the data space: the
ADC data conversion register, ADR, which stores
the conversion result, and the ADC control regis-
ter, ADCR, used to program the ADC functions.
CORE
CORE
CONTROL SIGNALS
VA00418
A conversion is started by writing a “1” to the Start
bit (STA) in the ADC control register. This auto-
matically clears (resets to “0”) the End Of Conver-
sion Bit (EOC). When a conversion is complete,
the EOC bit is automatically set to “1”, in order to
flag that conversion is complete and that the data
in the ADC data conversion register is valid. Each
conversion has to be separately initiated by writing
to the STA bit.
4.4.1 Application Notes
The A/D converter does not feature a sample and
hold circuit. The analog voltage to be measured
should therefore be stable during the entire con-
version cycle. Voltage variation should not exceed
±1/2 LSB for the optimum conversion accuracy. A
low pass filter may be used at the analog input
pins to reduce input voltage variation during con-
version.
The STA bit is continuously scanned so that, if the
user sets it to “1” while a previous conversion is in
progress, a new conversion is started before com-
pleting the previous one. The start bit (STA) is a
write only bit, any attempt to read it will show a log-
ical “0”.
When selected as an analog channel, the input pin
is internally connected to a capacitor C of typi-
ad
cally 12pF. For maximum accuracy, this capacitor
must be fully charged at the beginning of conver-
sion. In the worst case, conversion starts one in-
struction (6.5 µs) after the channel has been se-
lected. In worst case conditions, the impedance,
ASI, of the analog voltage source is calculated us-
ing the following formula:
The A/D converter features a maskable interrupt
associated with the end of conversion. This inter-
rupt is associated with interrupt vector #4 and oc-
curs when the EOC bit is set (i.e. when a conver-
sion is completed). The interrupt is masked using
the EAI (interrupt mask) bit in the control register.
6.5µs = 9 x C x ASI
ad
(capacitor charged to over 99.9%), i.e. 30 kΩ in-
cluding a 50% guardband. ASI can be higher if C
has been charged for a longer period by adding in-
structions before the start of conversion (adding
more than 26 CPU cycles is pointless).
The power consumption of the device can be re-
duced by turning off the ADC peripheral. This is
done by setting the PDS bit in the ADC control reg-
ister to “0”. If PDS=“1”, the A/D is powered and en-
abled for conversion. This bit must be set at least
one instruction before the beginning of the conver-
ad
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A/D CONVERTER (Cont’d)
Since the ADC is on the same chip as the micro-
processor, the user should not switch heavily load-
ed output signals during conversion, if high preci-
sion is required. Such switching will affect the sup-
ply voltages used as analog references.
up the microcontroller could also be done using
the Timer interrupt, but in this case the Timer will
be working and the resulting noise could affect
conversion accuracy.
A/D Converter Control Register (ADCR)
The accuracy of the conversion depends on the
Address: 0D1h
—
Read/Write
quality of the power supplies (V and V ). The
DD
SS
user must take special care to ensure a well regu-
lated reference voltage is present on the V and
SS
7
0
DD
EAI
EOC
STA
PDS
D3
D2
D1
D0
V
pins (power supply voltage variations must be
less than 5V/ms). This implies, in particular, that a
suitable decoupling capacitor is used at the V
pin.
DD
EAI
: Enable A/D Interrupt.If this bit is set to
“1” the A/D interrupt is enabled, when EAI=0 the
interrupt is disabled.
Bit 7 =
The converter resolution is given by::
Bit 6 = EOC: End of conversion. Read Only. This
read only bit indicates when a conversion has
been completed. This bit is automatically reset to
“0” when the STA bit is written. If the user is using
the interrupt option then this bit can be used as an
interrupt pending bit. Data in the data conversion
register are valid only when this bit is set to “1”.
V
DD – VSS
----------------------------
256
The Input voltage (Ain) which is to be converted
must be constant for 1µs before conversion and
remain constant during conversion.
Bit 5 = STA: Start of Conversion. Write Only. Writ-
ing a “1” to this bit will start a conversion on the se-
lected channel and automatically reset to “0” the
EOC bit. If the bit is set again when a conversion is
in progress, the present conversion is stopped and
a new one will take place. This bit is write only, any
attempt to read it will show a logical zero.
Conversion resolution can be improved if the pow-
er supply voltage (V ) to the microcontroller is
DD
lowered.
In order to optimise conversion resolution, the user
can configure the microcontroller in WAIT mode,
because this mode minimises noise disturbances
and power supply variations due to output switch-
ing. Nevertheless, the WAIT instruction should be
executed as soon as possible after the beginning
of the conversion, because execution of the WAIT
Bit 4 = PDS: Power Down Selection. This bit acti-
vates the A/D converter if set to “1”. Writing a “0” to
this bit will put the ADC in power down mode (idle
mode).
Bit 3-0 = D3-D0. Not used
instruction may cause a small variation of the V
DD
voltage. The negative effect of this variation is min-
imized at the beginning of the conversion when the
converter is less sensitive, rather than at the end
of conversion, when the less significant bits are
determined.
A/D Converter Data Register (ADR)
Address: 0D0h
—
Read only
7
0
The best configuration, from an accuracy stand-
point, is WAIT mode with the Timer stopped. In-
deed, only the ADC peripheral and the oscillator
are then still working. The MCU must be woken up
from WAIT mode by the ADC interrupt at the end
of the conversion. It should be noted that waking
D7
D6
D5
D4
D3
D2
D1
D0
D7-D0: 8 Bit A/D Conversion Result.
Bit 7-0 =
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4.5 SERIAL PERIPHERAL INTERFACE (SPI)
The SPI peripheral is an optimized synchronous
serial interface with programmable transmission
modes and master/slave capabilities supporting a
wide range of industry standard SPI specifications.
The SPI interface may also implement asynchro-
nous data transfer, in which case processor over-
head is limited to data transfer from or to the shift
register on an interrupt driven basis.
mode is defined by the serial clock being supplied
externally on the SCK pin by the external Master
device.
For maximum versatility the SPI may be pro-
grammed to sample data either on the rising or on
the falling edge of SCK, with or without phase shift
(clock Polarity and Phase selection).
The Sin, Sout and SCK signals are connected as
alternate I/O pin functions.
The SPI may be controlled by simple user soft-
ware to perform serial data exchange with low-
cost external memory, or with serially controlled
peripherals to drive displays, motors or relays.
For serial input operation, Sin must be configured
as an input. For serial output operation, Sout is se-
lected as an output by programming Bit 0 of the
Miscellaneous Register: clearing this bit will set
the pin as a standard I/O line, while setting the bit
will select the Sout function.
The SPI’s shift register is simultaneously fed by
the Sin pin and feeds the Sout pin, thus transmis-
sion and reception are essentially the same proc-
ess. Suitable setting of the number of bits in the
data frame can allow filtering of unwanted leading
data bits in the incoming data stream.
An interrupt request may be associated with the
end of a transmission or reception cycle; this is de-
fined by programming the number of bits in the
data frame and by enabling the interrupt. This re-
quest is associated with interrupt vector #2, and
can be masked by programming the SPIE bit of
the MOD register. Since the SPI interrupt is
“ORed” with the port interrupt source, an interrupt
flag bit is available in the DIV register allowing dis-
crimination of the interrupt request.
The SPI comprises an 8-bit Data/Shift Register,
DSR, a Divide register, DIV, a Mode Control Reg-
ister MOD, and a Miscellaneous register, MISCR.
The SPI may be operated either in Master mode or
in Slave mode.
Master mode is defined by the synchronous serial
clock being supplied by the MCU, by suitably pro-
gramming the clock divider (DIV register). Slave
Figure 27. SPI Block Diagram
CPU
SPI
DIVIDER
CYCLE
CLOCK
SCK
Sin
FILTER
FILTER
CLOCK
Sout
SHIFT
8
REGISTER
DATA BUS
VR001693
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SERIAL PERIPHERAL INTERFACE SPI(Cont’d)
4.5.1 SPI Registers
or the signal provided at SCK pin by an external
device (slave mode). If SPCLK is low and the SCK
pin is configured as input, the slave mode is se-
lected. If SPCLK is high and the SCK pin is config-
ured as output, the master mode is selected. In
this case, the phase and polarity of the clock are
controlled by CPOL and CPHA.
SPI Mode Control Register (MOD)
Address: E2h
— Read/Write
Reset status: 00h
7
0
Bit 3 = SPIN: Input Selection
SPRUN SPIE CPHA SPCLK SPIN SPSTRT EFILT CPOL
This bit enables the transfer of the data input to the
Shift Register in receive mode. If this bit is cleared
the Shift Register input is 0. If this bit is set, the
Shift Register input corresponds to the input signal
present on the Sin pin.
The MOD register defines and controls the trans-
mission modes and characteristics.
This register is read/write and all bits are cleared
at reset. Setting SPSTRT = 1 and SPIN = 1 is not
allowed and must be avoided.
Bit 2 = SPSTRT: Start Selection
This bit selects the transmission or reception start
mode. If SPSTRT is cleared, the internal start con-
dition occurs as soon as the SPRUN bit is set. If
SPSTRT is set, the internal start signal is the logic
“AND” between the SPRUN bit and the external
signal present on the Sin pin; in this case transmis-
sion will start after the latest of both signals provid-
ing that the first signal is still present (note that this
implies a rising edge). After the transmission or re-
cetion has been started, it will continue even if the
Sin signal is reset.
Bit 7 = SPRUN: SPI Run. This bit is the SPI activity
flag. This can be used in either transmit or receive
modes; it is automatically cleared by the SPI at the
end of a transmission or reception and generates
an interrupt request (providing that the SPIE Inter-
rupt Enable bit is set). The Core can stop transmis-
sion or reception at any time by resetting the
SPRUN bit; this will also generate an interrupt re-
quest (providing that the SPIE Interrupt enable bit
is set). The SPRUN bit can be used as a start con-
dition parameter, in conjunction with the SPSTRT
bit, when an external signal is present on the Sin
pin. Note that a rising edge is then necessary to in-
itiate reception; this may require external data in-
version.
EFILT
: Enable Filters
Bit 1 =
This bit enables/disables the input noise filters on
the Sin and SCK inputs. If it is cleared to zero the
filters are enabled, if set to one the filters are disa-
bled. These noise filters will eliminate any pulse on
Sin and SCK with a pulse width smaller than one
to two Core clock periods (depending on the oc-
currence of the signal edge with respect to the
Core clock edge). For example, if the ST6260B/
65B runs with an 8MHz crystal, Sin and SCK will
be delayed by 125 to 250ns.
Bit 6 = SPIE: SPI Interrupt Enable. This bit is the
SPI Interrupt Enable bit. If this bit is set the SPI in-
terrupt (vector #2) is enabled, when SPIE is reset,
the interrupt is disabled.
Bit 5 = CPHA: Clock Phase Selection. This bit se-
lects the clock phase of the clock signal. If this bit
is cleared to zero the normal state is selected; in
this case Bit 7 of the data frame is present on Sout
pin as soon as the SPI Shift Register is loaded. If
this bit is set to one the shifted state’ is selected; in
this case Bit 7 of data frame is present on Sout pin
on the first falling edge of Shift Register clock. The
polarity relation and the division ratio between
Shift Register and SPI base clock are also pro-
grammable; refer to DIV register and Timing Dia-
grams for more information.
Bit 0 = CPOL: Clock Polarity
This bit controls the relationship between the data
on the Sin and Sout pins and SCK. The CPOL bit
selects the clock edge which captures data and al-
lows it to change state. It has the greatest impact
on the first bit transmitted (the MSB) as it does (or
does not) allow a clock transition before the first
data capture edge.
Refer to the timing diagrams at the end of this sec-
tion for additional details. These show the relation-
ship between CPOL, CPHA and SCK, and indicate
the active clock edges and strobe times.
SPCLK
: Base Clock Selection
Bit 4=
This bit selects the SPI base clock source. It is ei-
ther the core cycle clock (f /13) (Master mode)
INT
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50
ST62T53B/T60B/T63B ST62E60B
Table 18. Burst Mode Bit Clock Periods
SERIAL PERIPHERAL INTERFACE SPI(Cont’d)
SPI DIV Register (DIV)
Address: E1h
— Read/Write
DIV6-DIV3
Number of bits sent
Reset status: 00h
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Reserved (not to be used)
1
2
3
4
5
6
7
8
9
7
0
SPINT DOV6 DIV5
DIV4
DIV3
CD2
CD1
CD0
The SPIDIV register defines the transmission rate
and frame format and contains the interrupt flag.
Bits CD0-CD2, DIV3-DIV6 are read/write while
SPINT can be read and cleared only. Write access
is not allowed if SPRUN in the MOD register is set.
Bit 7 = SPINT: Interrupt Flag. It is automatically set
to one by the SPI at the end of a transmission or
reception and an interrupt request can be generat-
ed depending on the state of the interrupt mask bit
in the MOD control register. This bit is read-only
and must be cleared by user software at the end of
the interrupt service routine.
10
11
12
13
14
15
Refer to the
description of the
DIV6-DIV3 bits in
the DIV Register
DIV6-DIV3
: Burst Mode Bit Clock Period
Bit 6-3 =
SPI Data/Shift Register (SPIDSR)
Address: E0h Read/Write
Selection.Definethenumber ofshiftregister bitsthat
are transmitted or received ina frame. The available
selections are listed inFigure 18. The normal max-
imum setting is 8 bits, since the shift register is 8 bits
wide. Note that by setting a greater number of bits,
in conjunction with the SPIN bit in the MOD register,
unwanted data bits may be filtered from the data
stream.
—
Reset status: XXh
7
0
D7
D6
D5
D4
D3
D2
D1
D0
SPIDSR is read/write, however write access is not
allowed if the SPRUN bit of Mode Control register
is set to one.
Bit 2-0 = CD2-CD0: Base/Bit Clock Rate Selec-
tion. Define the division ratio between the core
clock (f
divided by 13) and the clock supplied to
INT
the Shift Register in Master mode.
Data is sampled into SPDSR on the SCK edge de-
termined by the CPOL and CPHA bits. The affect
of these setting is shown in the following diagrams.
Table 17. Base/Bit Clock Ratio Selection
CD2-CD0
Divide Ratio (decimal)
Divide by 1
The Shift Register transmits and receives the Most
Significant Bit first.
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
Divide by 2
Divide by 4
Divide by 8
Divide by 16
Divide by 32
Divide by 64
Divide by 256
Bit 7-0 = DSR7-DSR0: Data Bits. These are the
SPI shift register data bits.
0
0
Miscellaneous Register (MISCR)
Address: DDh
— Write only
1
1
Reset status: xxxxxxxb
1
7
0
1
-
-
-
-
-
-
-
D0
Note
: For example, when an 8MHz CPU clock is
used, asynchronous operation at 9600 Baud is
possible (8MHz/13/64). Other Baud rates are
available by proportionally selecting division fac-
tors depending on CPU clock frequency.
D7-D1
Bit 7-1 =
: Reserved.
Bit 0 = D0: Bit 0. This bit, when set, selects the
Sout pin as the SPI output line. When this bit is
cleared, Sout acts as a standard I/O line.
Data setup time on Sin istypically 250ns min, while
data hold time is typically 50ns min.
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ST62T53B/T60B/T63B ST62E60B
SERIAL PERIPHERAL INTERFACE SPI(Cont’d)
4.6 SPI Timing Diagrams
Figure 28. CPOL = 0 Clock Polarity Normal, CPHA = 0 Phase Selection Normal
SPRUN
SCK
Sin
Sampling
Sout
b7
b6
b5
b4
b3
b2
b1
b0
VR001694
Figure 29. CPOL = 1 Clock Polarity Inverted, CPHA = 0 Phase Selection Normal
SPRUN
SCK
Sin
Sampling
Sout
b7
b6
b5
b4
b3
b2
b1
b0
VR0A1694
52/75
52
ST62T53B/T60B/T63B ST62E60B
SERIAL PERIPHERAL INTERFACE SPI(Cont’d)
Figure 30. CPOL = 0 Clock Polarity Normal, CPHA = 1 Phase Selection Shifted
SPRUN
SCK
Sin
Sampling
Sout
b7
b6
b5
b4
b3
b2
b1
b0
VR0B1694
Figure 31. CPOL = 1 Clock Polarity Inverted, CPHA = 1 Phase Selection Shifted
SPRUN
SCK
Sin
Sampling
Sout
b7
b6
b5
b4
b3
b2
b1
b0
VR0C1694
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ST62T53B/T60B/T63B ST62E60B
5 SOFTWARE
5.1 ST6 ARCHITECTURE
The ST6 software has been designed to fully use
the hardware in the most efficient way possible
while keeping byte usage to a minimum; in short,
to provide byte efficient programming capability.
The ST6 core has the ability to set or clear any
register or RAM location bit of the Data space with
a single instruction. Furthermore, the program
may branch to a selected address depending on
the status of any bit of the Data space. The carry
bit is stored with the value of the bit when the SET
or RES instruction is processed.
bits of the opcode with the byte following the op-
code. The instructions (JP, CALL) which use the
extended addressing mode are able to branch to
any address of the 4K bytes Program space.
An extended addressing mode instruction is two-
byte long.
Program Counter Relative. The relative address-
ing mode is only used in conditional branch in-
structions. The instruction is used to perform a test
and, if the condition is true, a branch with a span of
-15 to +16 locations around the address of the rel-
ative instruction. If the condition is not true, the in-
struction which follows the relative instruction is
executed. The relative addressing mode instruc-
tion is one-byte long. The opcode is obtained in
adding the three most significant bits which char-
acterize the kind of the test, one bit which deter-
mines whether the branch is a forward (when it is
0) or backward (when it is 1) branch and the four
less significant bits which give the span of the
branch (0h to Fh) which must be added or sub-
tracted to the address of the relative instruction to
obtain the address of the branch.
5.2 ADDRESSING MODES
The ST6 core offers nine addressing modes,
which are described in the following paragraphs.
Three different address spaces are available: Pro-
gram space, Data space, and Stack space. Pro-
gram space contains the instructions which are to
be executed, plus the data for immediate mode in-
structions. Data space contains the Accumulator,
the X,Y,V and W registers, peripheral and Input/
Output registers, the RAM locations and Data
ROM locations (for storage of tables and con-
stants). Stack space contains six 12-bit RAM cells
used to stack the return addresses for subroutines
and interrupts.
Bit Direct
. In the bit direct addressing mode, the
bit to be set or cleared is part of the opcode, and
the byte following the opcode points to the ad-
dress of the byte in which the specified bit must be
set or cleared. Thus, any bit in the 256 locations of
Data space memory can be set or cleared.
Immediate. In the immediate addressing mode,
the operand of the instruction follows the opcode
location. As the operand is a ROM byte, the imme-
diate addressing mode is used to access con-
stants which do not change during program execu-
tion (e.g., a constant used to initialize a loop coun-
ter).
Bit Test & Branch. The bit test and branch ad-
dressing mode is a combination of direct address-
ing and relative addressing. The bit test and
branch instruction is three-byte long. The bit iden-
tification and the tested condition are included in
the opcode byte. The address of the byte to be
tested follows immediately the opcode in the Pro-
gram space. The third byte is the jump displace-
ment, which is in the range of -127 to +128. This
displacement can be determined using a label,
which is converted by the assembler.
Direct. In the direct addressing mode, the address
of the byte which is processed by the instruction is
stored in the location which follows the opcode. Di-
rect addressing allows the user to directly address
the 256 bytes in Data Space memory with a single
two-byte instruction.
Short Direct
. The core can address the four RAM
Indirect
. In the indirect addressing mode, the byte
registers X,Y,V,W (locations 80h, 81h, 82h, 83h) in
the short-direct addressing mode. In this case, the
instruction is only one byte and the selection of the
location to be processed is contained in the op-
code. Short direct addressing is a subset of the di-
rect addressing mode. (Note that 80h and 81h are
also indirect registers).
processed by the register-indirect instruction is at
the address pointed by the content of one of the in-
direct registers, X or Y (80h,81h). The indirect reg-
ister is selected by the bit 4 of the opcode. A regis-
ter indirect instruction is one byte long.
Inherent. In the inherent addressing mode, all the
information necessary to execute the instruction is
contained in the opcode. These instructions are
one byte long.
Extended. In the extended addressing mode, the
12-bit address needed to define the instruction is
obtained by concatenating the four less significant
54/75
54
ST62T53B/T60B/T63B ST62E60B
5.3 INSTRUCTION SET
Load & Store
The ST6 core offers a set of 40 basic instructions
which, when combined with nine addressing
modes, yield 244 usable opcodes. They can be di-
vided into six different types: load/store, arithme-
tic/logic, conditional branch, control instructions,
jump/call, and bit manipulation. The following par-
agraphs describe the different types.
. These instructions use one, two or
three bytes in relation with the addressing mode.
One operand is the Accumulator for LOAD and the
other operand is obtained from data memory using
one of the addressing modes.
For Load Immediate one operand can be any of
the 256 data space bytes while the other is always
immediate data.
All the instructions belonging to a given type are
presented in individual tables.
Table 19. Load & Store Instructions
Flags
Instruction
LD A, X
Addressing Mode
Short Direct
Bytes
Cycles
Z
C
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
1
1
1
1
1
1
1
1
2
2
1
1
1
1
2
3
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
∆
LD A, Y
LD A, V
LD A, W
LD X, A
LD Y, A
Short Direct
Short Direct
Short Direct
Short Direct
Short Direct
Short Direct
Short Direct
Direct
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
LD V, A
LD W, A
LD A, rr
LD rr, A
Direct
LD A, (X)
LD A, (Y)
LD (X), A
LD (Y), A
LDI A, #N
LDI rr, #N
Indirect
Indirect
Indirect
Indirect
∆
Immediate
Immediate
∆
*
Notes:
X,Y. Indirect Register Pointers, V & W Short Direct Registers
# . Immediate data (stored in ROM memory)
rr. Data space register
∆. Affected
* . Not Affected
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55
ST62T53B/T60B/T63B ST62E60B
INSTRUCTION SET (Cont’d)
Arithmetic and Logic. These instructions are
used to perform the arithmetic calculations and
logic operations. In AND, ADD, CP, SUB instruc-
tions one operand is always the accumulator while
the other can be either a data space memory con-
tent or an immediate value in relation with the ad-
dressing mode. In CLR, DEC, INC instructions the
operand can be any of the 256 data space ad-
dresses. In COM, RLC, SLA the operand is always
the accumulator.
Table 20. Arithmetic & Logic Instructions
Flags
Instruction
ADD A, (X)
Addressing Mode
Indirect
Bytes
Cycles
Z
∆
∆
∆
∆
∆
∆
∆
∆
∆
*
C
∆
∆
∆
∆
∆
∆
∆
∆
∆
*
1
1
2
2
1
1
2
2
2
3
1
1
1
2
2
1
1
1
1
2
2
1
1
1
1
1
1
2
2
1
1
1
2
1
1
2
2
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
ADD A, (Y)
ADD A, rr
ADDI A, #N
AND A, (X)
AND A, (Y)
AND A, rr
ANDI A, #N
CLR A
Indirect
Direct
Immediate
Indirect
Indirect
Direct
Immediate
Short Direct
Direct
CLR r
COM A
Inherent
Indirect
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
*
CP A, (X)
CP A, (Y)
CP A, rr
CPI A, #N
DEC X
Indirect
Direct
Immediate
Short Direct
Short Direct
Short Direct
Short Direct
Direct
DEC Y
*
DEC V
*
DEC W
*
DEC A
*
DEC rr
Direct
*
DEC (X)
DEC (Y)
INC X
Indirect
*
Indirect
*
Short Direct
Short Direct
Short Direct
Short Direct
Direct
*
INC Y
*
INC V
*
INC W
*
INC A
*
INC rr
Direct
*
INC (X)
Indirect
*
INC (Y)
Indirect
*
RLC A
Inherent
Inherent
Indirect
∆
∆
∆
∆
∆
∆
SLA A
SUB A, (X)
SUB A, (Y)
SUB A, rr
SUBI A, #N
Indirect
Direct
Immediate
Notes:
X,Y.Indirect Register Pointers, V & W Short Direct RegistersD. Affected
# . Immediate data (stored in ROM memory)* . Not Affected
rr. Data space register
56/75
56
ST62T53B/T60B/T63B ST62E60B
INSTRUCTION SET (Cont’d)
Conditional Branch. The branch instructions
achieve a branch in the program when the select-
ed condition is met.
Control Instructions. The control instructions
control the MCU operations during program exe-
cution.
Bit Manipulation Instructions. These instruc-
tions can handle any bit in data space memory.
One group either sets or clears. The other group
(see Conditional Branch) performs the bit test
branch operations.
Jump and Call. These two instructions are used
to perform long (12-bit) jumps or subroutines call
inside the whole program space.
Table 21. Conditional Branch Instructions
Flags
Instruction
Branch If
Bytes
Cycles
Z
*
*
*
*
*
*
C
*
JRC e
C = 1
1
1
1
1
3
3
2
2
2
2
5
5
JRNC e
C = 0
Z = 1
Z = 0
Bit = 0
Bit = 1
*
JRZ e
*
JRNZ e
*
JRR b, rr, ee
JRS b, rr, ee
∆
∆
Notes
:
b.
e.
3-bit address
rr. Data space register
∆ . Affected. The tested bit is shifted into carry.
5 bit signed displacement in the range -15 to +16<F128M>
ee. 8 bit signed displacement in the range -126 to +129
* . Not Affected
Table 22. Bit Manipulation Instructions
Flags
Instruction
Addressing Mode
Bytes
Cycles
Z
C
*
SET b,rr
Bit Direct
Bit Direct
2
2
4
4
*
*
RES b,rr
*
Notes:
b.
3-bit address;
* . Not<M> Affected
rr. Data space register;
Table 23. Control Instructions
Flags
Instruction
Addressing Mode
Bytes
Cycles
Z
*
C
*
NOP
Inherent
Inherent
Inherent
Inherent
Inherent
1
1
1
1
1
2
2
2
2
2
RET
*
*
RETI
∆
*
∆
*
STOP (1)
WAIT
*
*
Notes:
1.
This instruction is deactivated<N>and a WAIT is automatically executed instead of a STOP if the watchdog function is selected.
∆ . Affected
*.
Not Affected
Table 24. Jump & Call Instructions
Instruction
Flags
Addressing Mode
Bytes
Cycles
Z
*
C
*
CALL abc
JP abc
Extended
Extended
2
2
4
4
*
*
Notes:
abc. 12-bit address;
* . Not Affected
57/75
57
ST62T53B/T60B/T63B ST62E60B
Opcode Map Summary.The following table contains an opcode map for the instructions used by the ST6
LOW
LOW
0
0000
1
0001
2
0010
3
0011
4
0100
5
6
7
0101
0110
0111
HI
HI
2
JRNZ
4
CALL
abc
ext
CALL
abc
ext
CALL
abc
ext
CALL
abc
ext
CALL
abc
ext
CALL
abc
ext
CALL
abc
ext
CALL
abc
ext
CALL
abc
ext
CALL
abc
ext
CALL
abc
ext
CALL
abc
ext
CALL
abc
ext
CALL
abc
ext
CALL
abc
ext
CALL
abc
2
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
5
JRR
b0,rr,ee
bt
JRS
b0,rr,ee
bt
JRR
b4,rr,ee
bt
JRS
b4,rr,ee
bt
JRR
b2,rr,ee
bt
JRS
b2,rr,ee
bt
JRR
b6,rr,ee
bt
JRS
b6,rr,ee
bt
JRR
b1,rr,ee
bt
JRS
b1,rr,ee
bt
JRR
b5,rr,ee
bt
JRS
b5,rr,ee
bt
JRR
b3,rr,ee
bt
JRS
b3,rr,ee
bt
JRR
b7,rr,ee
bt
JRS
b7,rr,ee
2
JRZ
2
JRC
4
LD
0
0
e
e
e
e
e
e
e
e
e
e
e
#
x
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
a,(x)
0000
0000
1
2
pcr
JRNZ
2
4
1
2
3
5
1
2
pcr
JRZ
1
2
prc
JRC
1
4
ind
LDI
4
1
INC
sd
1
0001
1
a,nn
0001
1
2
pcr
JRNZ
2
4
1
2
3
5
1
2
pcr
JRZ
1
2
prc
JRC
2
4
imm
CP
2
0010
2
#
a,(x)
0010
1
2
pcr
JRNZ
2
4
1
2
3
5
1
2
e
1
2
pcr
JRZ
1
2
prc
JRC
1
4
ind
CPI
4
1
LD
sd
3
0011
3
a,x
#
a,nn
0011
1
2
pcr
JRNZ
2
4
1
2
3
5
pcr
JRZ
1
2
prc
JRC
2
4
imm
ADD
a,(x)
4
0100
4
e
e
e
e
e
e
e
e
e
e
e
e
0100
1
2
pcr
JRNZ
2
4
1
2
3
5
1
2
pcr
JRZ
1
2
prc
JRC
1
4
ind
ADDI
4
1
INC
sd
5
0101
5
y
a,nn
0101
1
2
pcr
JRNZ
2
4
1
2
3
5
1
2
pcr
JRZ
1
2
prc
JRC
2
4
imm
INC
6
0110
6
#
(x)
#
0110
1
2
pcr
JRNZ
2
4
1
2
3
5
1
2
pcr
JRZ
1
2
prc
JRC
1
ind
4
1
LD
sd
7
0111
7
a,y
#
0111
1
2
pcr
2
4
1
2
3
5
1
2
pcr
JRZ
1
2
prc
JRC
JRNZ
pcr
4
1
LD
ind
8
1000
8
e
(x),a
#
1000
1
2
2
4
1
2
3
5
1
2
pcr
JRZ
1
2
prc
JRC
RNZ
e
pcr
JRNZ
4
1
INC
sd
9
1001
9
v
1001
1
2
2
4
1
2
3
5
1
2
pcr
JRZ
1
2
prc
JRC
4
AND
a,(x)
A
1010
A
1010
e
e
e
e
e
e
#
1
2
pcr
JRNZ
2
4
1
2
3
5
1
2
pcr
JRZ
1
2
prc
JRC
1
4
ind
ANDI
4
1
LD
sd
B
1011
B
1011
a,v
#
a,nn
1
2
pcr
JRNZ
2
4
1
2
3
5
1
2
pcr
JRZ
1
2
prc
JRC
2
4
imm
SUB
C
1100
C
1100
a,(x)
1
2
pcr
JRNZ
2
4
1
2
3
5
1
2
pcr
JRZ
1
2
prc
JRC
1
4
ind
SUBI
4
1
INC
sd
D
1101
D
1101
w
a,nn
1
2
pcr
JRNZ
2
4
1
2
3
5
1
2
pcr
JRZ
1
2
prc
JRC
2
4
imm
DEC
E
1110
E
1110
#
(x)
#
1
2
pcr
JRNZ
2
4
1
2
3
5
1
2
pcr
JRZ
1
2
prc
JRC
1
ind
4
1
LD
sd
F
1111
F
1111
a,w
1
pcr
2
ext
1
pcr
3
bt
1
pcr
1
prc
Abbreviations for Addressing Modes: Legend:
dir
sd
Direct
Short Direct
#
e
b
rr
nn
abc
ee
Indicates Illegal Instructions
5 Bit Displacement
3 Bit Address
1byte dataspace address
1 byte immediate data
12 bit address
Cycle
Mnemonic
2
1
JRC
prc
Operand
imm Immediate
e
inh
ext
b.d
bt
Inherent
Extended
Bit Direct
Bit Test
Bytes
Addressing Mode
8 bit Displacement
pcr
ind
Program Counter Relative
Indirect
58/75
58
ST62T53B/T60B/T63B ST62E60B
Opcode Map Summary(Continued)
LOW
LOW
8
1000
9
1001
A
1010
B
1011
C
1100
D
1101
E
1110
F
1111
HI
HI
2
JRNZ
4
JP
2
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
4
RES
b0,rr
b.d
SET
b0,rr
b.d
RES
b4,rr
b.d
SET
b4,rr
b.d
RES
b2,rr
b.d
SET
b2,rr
b.d
RES
b6,rr
b.d
SET
b6,rr
b.d
RES
b1,rr
b.d
SET
b1,rr
b.d
RES
b5,rr
b.d
SET
b5,rr
b.d
RES
b3,rr
b.d
SET
b3,rr
b.d
RES
b7,rr
b.d
SET
b7,rr
2
JRZ
4
LDI
2
JRC
4
LD
0
0
e
e
e
e
e
e
e
e
abc
abc
abc
abc
abc
abc
abc
abc
abc
abc
abc
abc
abc
abc
abc
abc
e
e
e
rr,nn
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
a,(y)
a,rr
0000
0000
1
2
pcr
JRNZ
2
4
ext
JP
1
2
2
4
1
2
pcr
JRZ
3
4
imm
DEC
1
2
prc
JRC
1
4
ind
LD
1
0001
1
x
0001
1
2
pcr
JRNZ
2
4
ext
JP
1
2
2
4
1
2
pcr
JRZ
1
4
sd
COM
1
2
prc
JRC
2
4
dir
CP
2
0010
2
a
a,(y)
a,rr
0010
1
2
pcr
JRNZ
2
4
ext
JP
1
2
2
4
1
2
e
1
2
pcr
JRZ
1
2
prc
JRC
1
4
ind
CP
4
LD
3
0011
3
x,a
0011
1
2
pcr
JRNZ
2
4
ext
JP
1
2
2
4
pcr
JRZ
1
2
sd
RETI
1
2
prc
JRC
2
4
dir
ADD
a,(y)
4
0100
4
e
e
e
e
e
e
e
e
e
e
e
e
0100
1
2
pcr
JRNZ
2
4
ext
JP
1
2
2
4
1
2
pcr
JRZ
1
4
inh
DEC
1
2
prc
JRC
1
4
ind
ADD
5
0101
5
y
a,rr
(y)
rr
0101
1
2
pcr
JRNZ
2
4
ext
JP
1
2
2
4
1
2
pcr
JRZ
1
2
sd
STOP
1
2
prc
JRC
2
4
dir
INC
6
0110
6
0110
1
2
pcr
JRNZ
2
4
ext
JP
1
2
2
4
1
2
pcr
JRZ
1
4
inh
LD
1
2
prc
JRC
1
4
ind
INC
7
0111
7
y,a
0111
1
2
pcr
2
4
ext
JP
1
2
2
4
1
2
pcr
JRZ
1
sd
1
2
prc
JRC
2
4
dir
LD
JRNZ
pcr
8
1000
8
e
#
v
(y),a
rr,a
1000
1
2
2
4
ext
JP
1
2
2
4
1
2
pcr
JRZ
1
2
prc
JRC
1
4
ind
LD
RNZ
e
pcr
JRNZ
4
DEC
9
1001
9
1001
1
2
2
4
ext
JP
1
2
2
4
1
2
pcr
JRZ
1
4
sd
RCL
1
2
prc
JRC
2
4
dir
AND
a,(y)
A
1010
A
1010
e
e
e
e
e
e
a
1
2
pcr
JRNZ
2
4
ext
JP
1
2
2
4
1
2
pcr
JRZ
1
4
inh
LD
1
2
prc
JRC
1
4
ind
AND
B
1011
B
1011
v,a
a,rr
1
2
pcr
JRNZ
2
4
ext
JP
1
2
2
4
1
2
pcr
JRZ
1
2
sd
RET
1
2
prc
JRC
2
4
dir
SUB
C
1100
C
1100
a,(y)
1
2
pcr
JRNZ
2
4
ext
JP
1
2
2
4
1
2
pcr
JRZ
1
4
inh
DEC
1
2
prc
JRC
1
4
ind
SUB
D
1101
D
1101
w
a,rr
(y)
rr
1
2
pcr
JRNZ
2
4
ext
JP
1
2
2
4
1
2
pcr
JRZ
1
2
sd
WAIT
1
2
prc
JRC
2
4
dir
DEC
E
1110
E
1110
1
2
pcr
JRNZ
2
4
ext
JP
1
2
2
4
1
2
pcr
JRZ
1
4
inh
LD
1
2
prc
JRC
1
4
ind
DEC
F
1111
F
1111
w,a
1
pcr
2
ext
1
pcr
2
b.d
1
pcr
1
sd
1
prc
2
dir
Abbreviations for Addressing Modes: Legend:
dir
sd
Direct
Short Direct
#
e
b
rr
nn
abc
ee
Indicates Illegal Instructions
5 Bit Displacement
3 Bit Address
1byte dataspace address
1 byte immediate data
12 bit address
Cycle
Mnemonic
2
1
JRC
prc
Operand
imm Immediate
e
inh
ext
b.d
bt
Inherent
Extended
Bit Direct
Bit Test
Bytes
Addressing Mode
8 bit Displacement
pcr
ind
Program Counter Relative
Indirect
59/75
59
ST62T53B/T60B/T63B ST62E60B
6 ELECTRICAL CHARACTERISTICS
6.1 ABSOLUTE MAXIMUM RATINGS
This product contains devices to protect the inputs
against damage due to high static voltages, how-
ever it is advisable to take normal precaution to
avoid application of any voltage higher than the
specified maximum rated voltages.
Power Considerations.The average chip-junc-
tion temperature, Tj, in Celsius can be obtained
from:
Tj=TA + PD x RthJA
Where:TA = Ambient Temperature.
For proper operation it is recommended that V
I
RthJA =Package thermal resistance(junc-
tion-to ambient).
and V be higher than V and lower than V .
O
SS
DD
Reliability is enhanced if unused inputs are con-
nected to an appropriate logic voltage level (V
PD = Pint + Pport.
DD
or V ).
SS
Pint =IDD x VDD (chip internal power).
Pport =Port power dissipation (determined
by the user).
Symbol
Parameter
Value
Unit
V
V
Supply Voltage
Input Voltage
Output Voltage
-0.3 to 7.0
DD
(1)
(1)
V
V
V
- 0.3 to V
+ 0.3
+ 0.3
V
I
SS
SS
DD
V
- 0.3 to V
V
O
DD
I
IV
IV
Current Drain per Pin Excluding V , V
±10
50
mA
mA
mA
°C
°C
O
DD SS
Total Current into V (source)
DD
SS
DD
Total Current out of V (sink)
50
SS
Tj
Junction Temperature
Storage Temperature
150
T
-60 to 150
STG
Notes:
-
Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
- (1) Withinthese limits,clamping diodes are guarantee to be not conductive. Voltages outside these limits are authorised as long as injection
current is kept within the specification.
60/75
60
ST62T53B/T60B/T63B ST62E60B
6.2 RECOMMENDED OPERATING CONDITIONS
Value
Unit
Symbol
Parameter
Test Conditions
6 Suffix Version
1 Suffix Version
3 Suffix Version
Min.
Typ.
Max.
-40
0
-40
85
70
TA
Operating Temperature
°C
V
125
f
= 2MHz
3.0
4.5
6.0
6.0
OSC
VDD
Operating Supply Voltage
fosc= 8MHz
V
V
V
= 3V
= 4.5V, 1 & 6 Suffix
= 4.5V, 3 Suffix
0
0
0
4.0
8.0
4.0
DD
DD
DD
2)
f
Oscillator Frequency
MHz
OSC
IINJ+
IINJ-
Pin Injection Current (positive) VDD = 4.5 to 5.5V
Pin Injection Current (negative) VDD = 4.5 to 5.5V
+5
-5
mA
mA
Notes:
1. Care must be taken in case of negative current injection, where adapted impedance must be respected on analog sources to not affect the
A/D conversion. For a -1mA injection, a maximum 10 KΩ is recommended.
2. An oscillator frequency above 1MHz is recommended for reliable A/D results.
Figure 32. Maximum Operating FREQUENCY (Fmax) Versus SUPPLY VOLTAGE (V )
DD
Maximum FREQUENCY (MHz)
8
7
6
5
4
3
2
1
FUNCTIONALITY IS NOT
GUARANTEED IN
THIS AREA
1 & 6 Suffix Version
3 Suffix Version
2.5
3
3.5
4
4.5
5
5.5
6
SUPPLY VOLTAGE (V )
DD
The shaded area is outside the recommended operating range; device functionality is not guaranteed under these conditions.
61/75
61
ST62T53B/T60B/T63B ST62E60B
6.3 DC ELECTRICAL CHARACTERISTICS
(T = -40 to +125°C unless otherwise specified)
A
Value
Typ.
Symbol
Parameter
Test Conditions
Unit
V
Min.
Max.
x 0.3
V
Input Low Level Voltage
All Input pins
IL
V
DD
V
Input High Level Voltage
All Input pins
IH
V
x 0.7
V
DD
(1)
Hysteresis Voltage
All Input pins
V
V
= 5V
= 3V
0.2
0.2
DD
DD
V
V
V
Hys
Low Level Output Voltage
All Output pins
V
V
= 5.0V; I = +10µA
0.1
0.8
DD
DD
OL
= 5.0V; I = + 3mA
OL
V
V
V
V
= 5.0V; I = +10µA
0.1
0.8
1.3
OL
DD
DD
DD
OL
Low Level Output Voltage
20 mA Sink I/O pins
= 5.0V; I = +7mA
OL
= 5.0V; I = +15mA
OL
High Level Output Voltage
All Output pins
V
V
= 5.0V; I = -10µA
4.9
3.5
DD
DD
OH
V
V
OH
= 5.0V; I = -3.0mA
OH
All Input pins
RESET pin
40
100
350
200
900
R
Pull-up Resistance
ΚΩ
PU
150
Input Leakage Current
All Input pins but RESET
V
V
= V (No Pull-Up configured)
SS
IN
IN
0.1
-16
1.0
= V
I
I
DD
IL
A
µ
Input Leakage Current
RESET pin
V
V
= V
= V
-8
-30
10
IH
IN
IN
SS
DD
Supply Current in RESET
Mode
V
=V
RESET SS
3.5
6.6
1.5
20
mA
mA
mA
µA
f
=8MHz
OSC
Supply Current in
V
V
=5.0V
f
=8MHz, T < 85°C
(2)
DD
INT
A
RUN Mode
I
DD
Supply Current in WAIT
=5.0V
f
=8MHz, T < 85°C
(3)
DD
INT
A
Mode
Supply Current in STOP
I
V
=0mA
=5.0V
LOAD
(3)
Mode
DD
Notes:
(1) Hysteresis voltage between switching levels
(2) All peripherals running
(3) All peripherals in stand-by
DC ELECTRICAL CHARACTERISTICS (Cont’d)
(T = -40 to +85°C unless otherwise specified)
A
Value
Typ.
Symbol
Parameter
Test Conditions
Unit
V
Min.
Max.
0.1
0.8
Low Level Output Voltage
All Output pins
V
V
= 5.0V; I = +10µA
DD
DD
OL
= 5.0V; I = + 5mA
OL
V
V
V
V
= 5.0V; I = +10µA
0.1
0.8
1.3
OL
DD
DD
DD
OL
Low Level Output Voltage
20 mA Sink I/O pins
= 5.0V; I = +10mA
OL
= 5.0V; I = +20mA
OL
High Level Output Voltage
All Output pins
V
V
= 5.0V; I = -10µA
4.9
3.5
DD
DD
OH
V
I
V
OH
= 5.0V; I = -5.0mA
OH
Supply Current in STOP
I
=0mA
=5.0V
LOAD
10
A
µ
(3)
DD
Mode
V
DD
62/75
62
ST62T53B/T60B/T63B ST62E60B
6.4 AC ELECTRICAL CHARACTERISTICS
(T = -40 to +125°C unless otherwise specified)
A
Value
Unit
Symbol
Parameter
Test Conditions
Min.
100
Typ.
Max.
(1)
t
Supply Recovery Time
ms
ns
REC
Minimum Pulse Width (V = 5V)
DD
T
RESET pin
NMI pin
100
100
WR
TA = 25°C
TA = 85°C
TA = 125°C
5
10
20
10
20
30
T
EEPROM Write Time
ms
WEE
(2)
Endurance
Retention
EEPROM WRITE/ERASE Cycle
EEPROM Data Retention
Input Capacitance
QA LOT Acceptance
TA = 55°C
300,000 1 million
10
cycles
years
pF
C
All Inputs Pins
All Outputs Pins
10
10
IN
C
Output Capacitance
pF
OUT
Notes:
1. Period for which V has to be connected at 0V to allow internal Reset function at next power-up.
DD
2. Sampled but not tested
6.5 A/D CONVERTER CHARACTERISTICS
(T = -40 to +125°C unless otherwise specified)
A
Value
Typ.
8
Symbol
Parameter
Test Conditions
Unit
Min.
Max.
Res
Resolution
Total Accuracy
Bit
f
> 1.2MHz
> 32kHz
2
±
±4
(1) (2)
OSC
A
LSB
TOT
f
OSC
f
= 8MHz, T < 85°C
= 4MHz
70
140
OSC
A
t
Conversion Time
Zero Input Reading
Full Scale Reading
µs
C
f
OSC
Conversion result when
= V
ZIR
00
Hex
Hex
V
IN
SS
Conversion result when
V
FSR
FF
= V
IN
DD
Analog Input Current During
Conversion
AD
AC
V
= 4.5V
1.0
5
µA
I
DD
Analog Input Capacitance
2
pF
IN
Notes:
1. Noise at AV , AV <10mV
DD
SS
2. With oscillator frequencies less than 1MHz, the A/D Converter accuracy is decreased.
63/75
63
ST62T53B/T60B/T63B ST62E60B
6.6 TIMER CHARACTERISTICS
(T = -40 to +125°C unless otherwise specified)
A
Value
Typ.
Symbol
Parameter
Test Conditions
Unit
Min.
Max.
fINT
---------
4
f
Input Frequency on TIMER Pin
Pulse Width at TIMER Pin
MHz
IN
V
V
= 3.0V
>4.5V
1
125
s
µ
ns
DD
DD
t
W
6.7 SPI CHARACTERISTICS
(T = -40 to +125°C unless otherwise specified)
A
Value
Symbol
Parameter
Test Conditions
Unit
Min.
Typ.
Max.
500
F
Clock Frequency
Set-up Time
Hold Time
Applied on Scl
Applied on Sin
Applied onSin
kHz
ns
CL
t
250
50
SU
t
ns
h
6.8 ARTIMER ELECTRICAL CHARACTERISTICS
(T = -40 to +125°C unless otherwise specified)
A
Value
Typ
Symbol
Parameter
Test Conditions
Unit
Min
Max
fINT
---------
4
RUN and WAIT Modes
STOP mode
f
Input Frequency on ARTIMin Pin
MHz
IN
2
64/75
64
ST62T53B/T60B/T63B ST62E60B
7 GENERAL INFORMATION
7.1 PACKAGE MECHANICAL DATA
Figure 33. 20-Pin Plastic Dual In-Line Package, 300-mil Width
mm
inches
Dim.
Min Typ Max Min Typ Max
A
3.93
-
0.155
-
A1 0.254
0.010
-
A2
B
-
-
-
0.45
0.018
B1 1.39
1.65 0.055
25.4
0.065
1.000
0.280
C
D
0.25
0.010
0.900
e3
E1
e
22.86
7.1
2.54
8.5
-
0.100
eB
0.335
K1
K2
L
-
-
-
-
-
-
-
-
-
-
-
3.3
0.130
Number of Pins
N
20
Figure 34. .20-Pin Plastic Small Outline Package, 300-mil Width
mm
inches
Dim.
A
L
h
Min Typ Max Min Typ Max
h
2.35
2.65 0.093
0.30 0.004
0.51 0.013
0.32 0.009
13.00 0.496
0.104
0.012
0.020
0.013
0.512
-
A
A1 0.10
C
B
C
0.33
0.23
12.60
-
e
A1
D1
B
E2
E2
D1
D
E1
E
D
D1
E
-
-
-
-
N
10.00
10.65 0.394
7.60 0.291
0.419
0.299
-
E1 7.40
E2
e
-
-
-
-
-
1.27
0.050
h
0.25
0.40
0°
0.75 0.010
1.27 0.016
8°
0.030
0.050
L
1
N / 2
Number of Pins
N
20
65/75
65
ST62T53B/T60B/T63B ST62E60B
PACKAGE MECHANICAL DATA(Cont’d)
Figure 35. 20-Pin Ceramic Dual In Line Package, 300-mil Width
mm
inches
Dim.
A
Min Typ Max Min Typ Max
2.35
2.65 0.093
0.30 0.004
0.51 0.013
0.32 0.009
13.00 0.496
0.104
0.012
0.020
0.013
0.512
-
A1 0.10
B
C
0.33
0.23
12.60
-
D
D1
E
-
-
-
-
10.00
10.65 0.394
7.60 0.291
0.419
0.299
-
E1 7.40
E2
e
-
-
-
-
-
1.27
0.050
h
0.25
0.40
0°
0.75 0.010
1.27 0.016
8°
0.030
0.050
L
Number of Pins
N
20
7.2 ORDERING INFORMATION
Table 25. OTP/EPROM VERSION ORDERING INFORMATION
Program
Sales Type
EEPROM (Bytes)
Temperature Range
Package
Memory (Bytes)
ST62T53BB6
ST62T53BB3
-40 to + 85°C
-40 to + 125°C
PDIP20
PSO20
PDIP20
PSO20
1836 (OTP)
-
ST62T53BM6
ST62T53BM3
-40 to + 85°C
-40 to + 125°C
ST62T60BB6
ST62T60BB3
-40 to + 85°C
-40 to + 125°C
3884 (OTP)
128
ST62T60BM6
ST62T60BM3
-40 to + 85°C
-40 to + 125°C
ST62T63BB6
ST62T63BM6
ST62E60BF1
PDIP20
PSO20
CDIP20
1836 (OTP)
64
-40 to + 85°C
0 to +70°C
3884 (EPROM)
128
66/75
66
R
ST62P53B/P60B/P63B
8-BIT FASTROM MCUs WITH A/D CONVERTER,
AUTO-RELOAD TIMER, EEPROM AND SPI
■ 3.0 to 6.0V Supply Operating Range
■ 8 MHz Maximum Clock Frequency
■
-40 to +125°C Operating Temperature Range
■
Run, Wait and Stop Modes
■ 5 Interrupt Vectors
■ Look-up Table capability in Program Memory
■
Data Storage in Program Memory:
User selectable size
■ Data RAM: 64/128 bytes
■ DataEEPROM:64/128bytes(noneonST62T53B)
PDIP20
■
13 I/O pins, fully programmable as:
– Input with pull-up resistor
– Input without pull-up resistor
– Input with interrupt generation
– Open-drain or push-pull output
– Analog Input
■ 6 I/O lines can sink up to 20mA to drive LEDs or
PSO20
TRIACs directly
■ 8-bit Timer/Counter with 7-bit programmable
prescaler
(See end of Datasheet for Ordering Information)
■ 8-bit Auto-reload Timer with 7-bit programmable
prescaler (AR Timer)
■
■ Digital Watchdog
■
8-bit A/D Converter with 7 analog inputs
■ 8-bit Synchronous Peripheral Interface (SPI)
■ On-chip Clock oscillator can be driven by Quartz
Crystal Ceramic resonator or RC network
■
User configurable Power-on Reset
■ One external Non-Maskable Interrupt
■ ST626x-EMU2 Emulation and Development
System (connects to an MS-DOS PC via a
parallel port).
DEVICE SUMMARY
DEVICE
ROM (Bytes)
1836
EEPROM
ST62P53B
ST62P60B
ST62P63B
-
3884
128
64
1836
Rev. 2.4
April 1998
67/75
67
ST62P53B/P60B/P63B
1 GENERAL DESCRIPTION
1.1 INTRODUCTION
options which will be used to produce the specified
MCU. The listing is then returned to the customer
who must thoroughly check, complete, sign and
return it to SGS-THOMSON. The signed listing
forms a part of the contractual agreement for the
production of the specific customer MCU.
The ST62P53B, ST62P60B and ST62P63B are
F
A
S
T
the actory dvanced ervice echnique ROM
(FASTROM) versions of ST62T53B, ST6260B
and ST62T63B OTP devices.
They offer the same functionality as OTP devices,
selecting as FASTROM options the options de-
fined in the programmable option byte of the OTP
version.
The SGS-THOMSON Sales Organization will be
pleased to provide detailed information on con-
tractual points.
Table 1. ROM Memory Map for ST62P60B
1.2 ORDERING INFORMATION
Device Address
Description
The following section deals with the procedure for
transfer of customer codes to SGS-THOMSON.
0000h-007Fh
0080h-0F9Fh
0FA0h-0FEFh
0FF0h-0FF7h
0FF8h-0FFBh
0FFCh-0FFDh
0FFEh-0FFFh
Reserved
User ROM
Reserved
1.2.1 Transfer of Customer Code
Interrupt Vectors
Reserved
NMI Interrupt Vector
Reset Vector
Customer code is made up of the ROM contents
and the list of the selected FASTROM options.
The ROM contents are to be sent on diskette, or
by electronic means, with the hexadecimal file
generated by the development tool. All unused
bytes must be set to FFh.
Table 2. ROM Memory Map for ST62P53B/P63B
The selected options are communicated to SGS-
THOMSON using the correctly filled OPTION LIST
appended.
Device Address
Description
0000h-087Fh
0880h-0F9Fh
0FA0h-0FEFh
0FF0h-0FF7h
0FF8h-0FFBh
0FFCh-0FFDh
0FFEh-0FFFh
Reserved
User ROM
Reserved
1.2.2 Listing Generation and Verification
Interrupt Vectors
Reserved
NMI Interrupt Vector
Reset Vector
When SGS-THOMSON receives the user’s ROM
contents, a computer listing is generated from it.
This listing refers exactly to the ROM contents and
Table 3. FASTROM version Ordering Information
Sales Type
ROM (Bytes)
EEPROM (Bytes)
Temperature Range
0 to + 70°C
Package
ST62P53BB1/XXX
ST62P53BB6/XXX
ST62P53BB3/XXX (*)
-40 to + 85°C
-40 to + 125°C
PDIP20
1836
-
ST62P53BM1/XXX
ST62P53BM6/XXX
ST62P53BM3/XXX (*)
0 to + 70°C
-40 to + 85°C
-40 to + 125°C
PSO20
PDIP20
PSO20
PDIP20
PSO20
ST62P60BB1/XXX
ST62P60BB6/XXX
ST62P60BB3/XXX (*)
0 to + 70°C
-40 to + 85°C
-40 to + 125°C
3884
1836
128
64
ST62P60BM1/XXX
ST62P60BM6/XXX
ST62P60BM3/XXX (*)
0 to + 70°C
-40 to + 85°C
-40 to + 125°C
ST62P63BB1/XXX
ST62P63BB6/XXX
ST62P63BB3/XXX (*)
0 to + 70°C
-40 to + 85°C
-40 to + 125°C
ST62P63BM1/XXX
ST62P63BM6/XXX
ST62P63BM3/XXX (*)
0 to + 70°C
-40 to + 85°C
-40 to + 125°C
(*)
Advanced information
68/75
68
ST62P53B/P60B/P63B
ST62P53B, ST62P60B and ST62P63B FASTROMMICROCONTROLLER OPTION LIST
Customer . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact
Phone No . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SGS-THOMSON Microelectronics references
Device:
[ ] ST62P53B[ ] ST62P60B
[ ] ST62P63B
Package: [ ] Dual in Line Plastic[ ] Small Outline Plastic with conditioning
[ ] Standard (Stick)
[ ] Tape & Reel
Temperature Range:[ ] 0°C to +70°C[ ] - 40°C to +85°C
Oscillator Source Selection:[ ] Crystal Quartz/Ceramic resonator
[ ] RC Network
Watchdog Selection:[ ] Software Activation
[ ] Hardware Activation
POR Reset Delay[ ] 32768 cycles
[ ] 2048 cycles
PB0..PB1 Pull-Up at RESET[ ] Enabled
[ ] Disabled
PB2..PB3 Pull-Up at RESET[ ] Enabled
[ ] Disabled
Readout Protection: [ ] Disabled
[ ] Enabled
External STOP Mode Control:[ ] Enabled
[ ] Disabled
Comments : Supply Operating Range in the application:
Oscillator Fequency in the application:
Notes
Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Date . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
69/75
69
ST62P53B/P60B/P63B
Notes:
70/75
70
R
ST6253B/60B/63B
8-BIT ROM MCUs WITH A/D CONVERTER,
AUTO-RELOAD TIMER, EEPROM AND SPI
■ 3.0 to 6.0V Supply Operating Range
■ 8 MHz Maximum Clock Frequency
■
-40 to +125°C Operating Temperature Range
■
Run, Wait and Stop Modes
■ 5 Interrupt Vectors
■ Look-up Table capability in Program Memory
■
Data Storage in Program Memory:
User selectable size
■ Data RAM: 64/128 bytes
■ DataEEPROM:64/128bytes(noneonST62T53B)
PDIP20
■
13 I/O pins, fully programmable as:
– Input with pull-up resistor
– Input without pull-up resistor
– Input with interrupt generation
– Open-drain or push-pull output
– Analog Input
■ 6 I/O lines can sink up to 20mA to drive LEDs or
PSO20
TRIACs directly
■ 8-bit Timer/Counter with 7-bit programmable
prescaler
(See end of Datasheet for Ordering Information)
■ 8-bit Auto-reload Timer with 7-bit programmable
prescaler (AR Timer)
■
■ Digital Watchdog
■
8-bit A/D Converter with 7 analog inputs
■ 8-bit Synchronous Peripheral Interface (SPI)
■ On-chip Clock oscillator can be driven by Quartz
Crystal Ceramic resonator or RC network
■
User configurable Power-on Reset
■ One external Non-Maskable Interrupt
■ ST626x-EMU2 Emulation and Development
System (connects to an MS-DOS PC via a
parallel port).
DEVICE SUMMARY
DEVICE
ST6253B
ST6260B
ST6263B
ROM (Bytes)
1836
EEPROM
-
3884
128
64
1836
Rev. 2.4
April 1998
71/75
71
ST6253B/60B/63B
1 GENERAL DESCRIPTION
1.1 INTRODUCTION
1.2 ROM READOUT PROTECTION
The ST6253B, ST6260B and ST6263B are mask
programmed ROM versions of ST62T53B,
ST6260B and ST62T63B OTP devices.
If the ROM READOUT PROTECTION option is
selected, a protection fuse can be blown to pre-
vent any access to the program memory content.
They offer the same functionality as OTP devices,
selecting as ROM options the options defined in
the programmable option byte of the OTP version.
In case the user wants to blow this fuse, high volt-
age must be applied on the TEST pin.
Figure 1. Programming wave form
Figure 2. Programming Circuit
0.5s min
TEST
100 s max
5V
47
F
m
15
14V typ
10
100nF
5
V
SS
t
V
DD
TEST
150 s typ
PROTECT
100mA
max
TEST
14V
100nF
ZPD15
15V
4mA typ
VR02003
t
VR02001
Note: ZPD15 is used for overvoltage protection
72/75
72
ST6253B/60B/63B
ST6253B, ST6260B and ST6263BMICROCONTROLLER OPTION LIST
Customer . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact
Phone No . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SGS-THOMSON Microelectronics references
Device:
[ ] ST6253B[ ] ST6260B
[ ] ST6263B
Package: [ ] Dual in Line Plastic[ ] Small Outline Plastic with conditioning
[ ] Standard (Stick)
[ ] Tape & Reel
Temperature Range:[ ] 0°C to +70°C[ ] - 40°C to +85°C
Special Marking:[ ] No
[ ] Yes ”___________”
Authorized characters are letters, digits, ’.’, ’-’, ’/’ and spaces only.
Maximum character count:DIP20: 10
SO20 : 8
Oscillator Source Selection:[ ] Crystal Quartz/Ceramic resonator
[ ] RC Network
Watchdog Selection:[ ] Software Activation
[ ] Hardware Activation
POR Reset Delay[ ] 32768 cycles
[ ] 2048 cycles
PB0..PB1 Pull-Up at RESET[ ] Enabled
[ ] Disabled
PB2..PB3 Pull-Up at RESET[ ] Enabled
[ ] Disabled
ROM Readout Protection:[ ] Disabled (Fuse cannot be blown)
[ ] Enabled (Fuse can be blown by the customer)
Note: No part is delivered with protected ROM. The fuse must be blown for protec-
tion to be effective.
External STOP Mode Control:[ ] Enabled
[ ] Disabled
Comments : Supply Operating Range in the application:
Oscillator Fequency in the application:
Notes
Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Date . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
73/75
73
ST6253B/60B/63B
1.3 ORDERING INFORMATION
The following section deals with the procedure for
transfer of customer codes to SGS-THOMSON.
The SGS-THOMSON Sales Organization will be
pleased to provide detailed information on contrac-
tual points.
1.3.1 Transfer of Customer Code
Customer code is made up of the ROM contents
and the list of the selected mask options. The ROM
contents are to be sent on diskette, or by electronic
means, with the hexadecimal file generated by the
development tool. All unused bytes must be set to
FFh.
Table 1. ROM Memory Map for ST6260B
Device Address
Description
0000h-007Fh
0080h-0F9Fh
0FA0h-0FEFh
0FF0h-0FF7h
0FF8h-0FFBh
0FFCh-0FFDh
0FFEh-0FFFh
Reserved
User ROM
Reserved
Interrupt Vectors
Reserved
NMI Interrupt Vector
Reset Vector
The selected mask options are communicated to
SGS-THOMSON using the correctly filled OPTION
LIST appended.
1.3.2 Listing Generation and Verification
Table 2. ROM Memory Map for ST6253B/63B
When SGS-THOMSON receives the user’s ROM
contents, a computer listing is generated from it.
This listing refers exactly to the mask which will be
used to produce the specified MCU. The listing is
then returned to the customer who must thoroughly
check, complete, sign and return it to SGS-THOM-
SON. The signed listing forms a part of the contrac-
tual agreement for the creation of the specific cus-
tomer mask.
Device Address
Description
0000h-087Fh
0880h-0F9Fh
0FA0h-0FEFh
0FF0h-0FF7h
0FF8h-0FFBh
0FFCh-0FFDh
0FFEh-0FFFh
Reserved
User ROM
Reserved
Interrupt Vectors
Reserved
NMI Interrupt Vector
Reset Vector
Table 3. ROM version Ordering Information
Sales Type
ROM (Bytes)
EEPROM (Bytes)
Temperature Range
0 to + 70°C
Package
ST6253BB1/XXX
ST6253BB6/XXX
ST6253BB3/XXX
-40 to + 85°C
-40 to + 125°C
PDIP20
1836
-
ST6253BM1/XXX
ST6253BM6/XXX
ST6253BM3/XXX
0 to + 70°C
-40 to + 85°C
-40 to + 125°C
PSO20
PDIP20
PSO20
PDIP20
PSO20
ST6260BB1/XXX
ST6260BB6/XXX
ST6260BB3/XXX
0 to + 70°C
-40 to + 85°C
-40 to + 125°C
3884
1836
128
64
ST6260BM1/XXX
ST6260BM6/XXX
ST6260BM3/XXX
0 to + 70°C
-40 to + 85°C
-40 to + 125°C
ST6263BB1/XXX
ST6263BB6/XXX
ST6263BB3/XXX
0 to + 70°C
-40 to + 85°C
-40 to + 125°C
ST6263BM1/XXX
ST6263BM6/XXX
ST6263BM3/XXX
0 to + 70°C
-40 to + 85°C
-40 to + 125°C
74/75
74
ST6253B/60B/63B
Notes:
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously
supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems
without the express written approval of SGS-THOMSON Microelectronics.
1998 SGS-THOMSON Microelectronics - All rights reserved.
Purchase of I2C Components by SGS-THOMSON Microelectronics conveys a license under the Philips I2C Patent. Rights to use these
components in an I2C system is granted provided that the system conforms to the I2C Standard Specification as defined by Philips.
SGS-THOMSON Microelectronics Group of Companies
Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -
Singapore Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
75/75
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