ST62T03C6 [STMICROELECTRONICS]
8-BIT MCUs WITH A/D CONVERTER, TWO TIMERS, OSCILLATOR SAFEGUARD & SAFE RESET;
| 型号： | ST62T03C6 |
| 厂家： | 
ST |
| 描述： | 8-BIT MCUs WITH A/D CONVERTER, TWO TIMERS, OSCILLATOR SAFEGUARD & SAFE RESET |
| 文件： | 总100页 (文件大小：968K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ST6200C/ST6201C/ST6203C
8-BIT MCUs WITH A/D CONVERTER,
TWO TIMERS, OSCILLATOR SAFEGUARD & SAFE RESET
■ Memories
– 1K or 2K bytes Program memory (OTP,
EPROM, FASTROM or ROM) with read-out
protection
– 64 bytes RAM
■ Clock, Reset and Supply Management
– Enhanced reset system
PDIP16
– Low Voltage Detector (LVD) for Safe Reset
– Clock sources: crystal/ceramic resonator or
RC network, external clock, backup oscillator
(LFAO)
SO16
– Oscillator Safeguard (OSG)
– 2 Power Saving Modes: Wait and Stop
■ Interrupt Management
– 4 interrupt vectors plus NMI and RESET
– 9 external interrupt lines (on 2 vectors)
■ 9 I/O Ports
SSOP16
– 9 multifunctional bidirectional I/O lines
– 4 alternate function lines
– 3 high sink outputs (20mA)
■ 2 Timers
– Configurable watchdog timer
– 8-bit timer/counter with a 7-bit prescaler
■ Analog Peripheral
CDIP16W
(See Section 11.5 for Ordering Information)
– 8-bit ADC with 4 input channels (except on
ST6203C)
■ Instruction Set
■ Development Tools
– Full hardware/software development package
– 8-bit data manipulation
– 40 basic instructions
– 9 addressing modes
– Bit manipulation
Device Summary
ST62T00C(OTP)
ST6200C(ROM)
ST62T01C(OTP)
ST6201C(ROM)
ST62T03C(OTP)
ST6203C(ROM)
Features
ST62E01C(EPROM)
ST62P00C(FASTROM)
ST62P01C(FASTROM)
ST62P03C(FASTROM)
Program memory - bytes
1K
2K
1K
-
2K
RAM - bytes
64
Operating Supply
3.0V to 6V
Analog Inputs
4
4
Clock Frequency
Operating Temperature
Packages
8MHz Max
-40°C to +125°C
PDIP16 / SO16 / SSOP16
CDIP16W
Rev. 3.2
July 2001
1/100
1
Table of Contents
ST6200C/ST6201C/ST6203C . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3 MEMORY MAPS, PROGRAMMING MODES AND OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . 8
3.1 MEMORY AND REGISTER MAPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1.2 Program Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1.3 Readout Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1.4 Data Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1.5 Stack Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1.6 Data ROM Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2 PROGRAMMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2.1 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2.2 EPROM Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3 OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5 CLOCKS, SUPPLY AND RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.1 CLOCK SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.1.1 Main Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.1.2 Oscillator Safeguard (OSG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.1.3 Low Frequency Auxiliary Oscillator (LFAO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.1.4 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.2 LOW VOLTAGE DETECTOR (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.3 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.3.2 RESET Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.3.3 RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.3.4 Watchdog Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.3.5 LVD Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.4 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.5 INTERRUPT RULES AND PRIORITY MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.6 INTERRUPTS AND LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.7 NON MASKABLE INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.8 PERIPHERAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.9 EXTERNAL INTERRUPTS (I/O PORTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.9.1 Notes on using External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.10 INTERRUPT HANDLING PROCEDURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.10.1Interrupt Response Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.11 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
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Table of Contents
6 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.2 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.3 STOP MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.4 NOTES RELATED TO WAIT AND STOP MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.4.1 Exit from Wait and Stop Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.4.2 Recommended MCU Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.2.1 Digital Input Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.2.2 Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.2.3 Output Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.2.4 Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.2.5 Instructions NOT to be used to access Port Data registers (SET, RES, INC and DEC)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.2.6 Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.3 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.4 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.5 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8.1.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8.1.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.1.4 Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.1.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.1.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.1.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8.2 8-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
8.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
8.2.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
8.2.3 Counter/Prescaler Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
8.2.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
8.2.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
8.2.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
8.3 A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
8.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
8.3.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
8.3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
8.3.4 Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
8.3.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
8.3.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
8.3.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
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9 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
9.1 ST6 ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
9.2 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
9.3 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
10 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
10.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
10.1.1Minimum and Maximum Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
10.1.2Typical Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
10.1.3Typical Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
10.1.4Loading Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
10.1.5Pin Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
10.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
10.2.1Voltage Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
10.2.2Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
10.2.3Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
10.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
10.3.1General Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
10.3.2Operating Conditions with Low Voltage Detector (LVD) . . . . . . . . . . . . . . . . . . . . . 61
10.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
10.4.1RUN Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
10.4.2WAIT Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
10.4.3STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
10.4.4Supply and Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
10.4.5On-Chip Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
10.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
10.5.1General Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
10.5.2External Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
10.5.3Crystal and Ceramic Resonator Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
10.5.4RC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
10.5.5Oscillator Safeguard (OSG) and Low Frequency Auxiliary Oscillator (LFAO) . . . . . 71
10.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
10.6.1RAM and Hardware Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
10.6.2EPROM Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
10.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
10.7.1Functional EMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
10.7.2Absolute Electrical Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
10.7.3ESD Pin Protection Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
10.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
10.8.1General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
10.8.2Output Driving Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
10.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
10.9.1Asynchronous RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
10.9.2NMI Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
10.10 TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
10.10.1Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
10.10.28-Bit Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
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1
Table of Contents
10.11 8-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
11 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
11.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
11.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
11.3 SOLDERING AND GLUEABILITY INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
11.4 PACKAGE/SOCKET FOOTPRINT PROPOSAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
11.5 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
11.6 TRANSFER OF CUSTOMER CODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
11.6.1FASTROM version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
11.6.2ROM VERSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
12 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
13 ST6 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
14 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
15 TO GET MORE INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
5/100
1
ST6200C/ST6201C/ST6203C
1 INTRODUCTION
The ST6200C, 01C and 03C devices are low cost
members of the ST62xx 8-bit HCMOS family of mi-
crocontrollers, which is targeted at low to medium
complexity applications. All ST62xx devices are
based on a building block approach: a common
core is surrounded by a number of on-chip periph-
erals.
mable option bytes of the OTP/EPROM versions
in the ROM option list (See Section 11.6 on page
92).
The ST62P00C, P01C and P03C are the Factory
Advanced Service Technique ROM (FASTROM)
versions of ST62T00C, T01 and T03C OTP devic-
es.
The ST62E01C is the erasable EPROM version of
the ST62T00C, T01 and T03C devices, which may
be used during the development phase for the
ST62T00C, T01 and T03C target devices, as well
as the respective ST6200C, 01C and 03C ROM
devices.
They offer the same functionality as OTP devices,
but they do not have to be programmed by the
customer (See Section 11 on page 86).
These compact low-cost devices feature a Timer
comprising an 8-bit counter with a 7-bit program-
mable prescaler, an 8-bit A/D Converter with 4 an-
alog inputs (depending on device, see device
summary on page 1) and a Digital Watchdog tim-
er, making them well suited for a wide range of au-
tomotive, appliance and industrial applications.
OTP and EPROM devices are functionally identi-
cal. OTP devices offer all the advantages of user
programmability at low cost, which make them the
ideal choice in a wide range of applications where
frequent code changes, multiple code versions or
last minute programmability are required.
For easy reference, all parametric data are located
in Section 10 on page 58.
The ROM based versions offer the same function-
ality, selecting the options defined in the program-
Figure 1. Block Diagram
8-BIT *
A/D CONVERTER
V
PP
PA1..PA3 (20mA Sink)
PORT A
NMI
INTERRUPTS
PB0..PB1
PORT B
PB3, PB5..PB7 / Ain*
DATA ROM
USER
PROGRAM
:
SELECTABLE
MEMORY
(1K or 2K Bytes)
TIMER
DATA RAM
64 Bytes
WATCHDOG
TIMER
PC
STACK LEVEL 1
STACK LEVEL 2
STACK LEVEL 3
STACK LEVEL 4
STACK LEVEL 5
STACK LEVEL 6
8-BIT CORE
POWER
RESET
RESET
OSCILLATOR
SUPPLY
V
V
OSCin OSCout
DD SS
* Depending on device. Please refer to I/O Port section.
6/100
4
ST6200C/ST6201C/ST6203C
2 PIN DESCRIPTION
Figure 2. 16-Pin Package Pinout
V
V
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
DD
SS
PA1/20mA Sink
OSCin
it1
PA2/20mA Sink
PA3/20mA Sink
PB0
OSCout
NMI
V
PP
RESET
Ain*/PB7
Ain*/PB6
PB1
it2
PB3/Ain*
PB5/Ain*
it2
itX associated interrupt vector
* Depending on device. Please refer to I/O Port section.
Table 1. Device Pin Description
Main Function
(after Reset)
Pin n°
Pin Name
Alternate Function
1
2
3
4
V
S
I
Main power supply
External clock input or resonator oscillator inverter input
DD
OSCin
OSCout
NMI
O
I
Resonator oscillator inverter output or resistor input for RC oscillator
Non maskable interrupt (falling edge sensitive)
Must be held at Vss for normal operation, if a 12.5V level is applied to the pin
during the reset phase, the device enters EPROM programming mode.
5
V
PP
6
7
RESET
I/O Top priority non maskable interrupt (active low)
PB7/Ain*
I/O Pin B7 (IPU)
Analog input
Analog input
Analog input
Analog input
8
PB6/Ain*
I/O Pin B6 (IPU)
9
PB5/Ain*
I/O Pin B5 (IPU)
10
11
12
13
14
15
16
PB3/Ain*
I/O Pin B3 (IPU)
PB1
I/O Pin B1 (IPU)
PB0
I/O Pin B0 (IPU)
PA3/ 20mA Sink
PA2/ 20mA Sink
PA1/ 20mA Sink
I/O Pin A3 (IPU)
I/O Pin A2 (IPU)
I/O Pin A1 (IPU)
V
S
Ground
SS
Legend / Abbreviations for Table 1:
* Depending on device. Please refer to I/O Port section.
I = input, O = output, S = supply, IPU = input pull-up
The input with pull-up configuration (reset state) is valid as long as the user software does not change it.
Refer to Section 7 "I/O PORTS" on page 36 for more details on the software configuration of the I/O ports.
7/100
ST6200C/ST6201C/ST6203C
3 MEMORY MAPS, PROGRAMMING MODES AND OPTION BYTES
3.1 MEMORY AND REGISTER MAPS
3.1.1 Introduction
Briefly, Program space contains user program
code in OTP and user vectors; Data space con-
tains user data in RAM and in OTP, and Stack
space accommodates six levels of stack for sub-
routine and interrupt service routine nesting.
The MCU operates in three separate memory
spaces: Program space, Data space, and Stack
space. Operation in these three memory spaces is
described in the following paragraphs.
Figure 3. Memory Addressing Diagram
PROGRAM SPACE
000h
DATA SPACE
000h
RESERVED
03Fh
040h
DATA ROM
WINDOW
PROGRAM
MEMORY
07Fh
080h
081h
082h
083h
084h
X REGISTER
Y REGISTER
V REGISTER
W REGISTER
(see Figure 4)
RAM
0BFh
0C0h
HARDWARE
0FF0h
CONTROL
REGISTERS
INTERRUPT &
(see Table 2)
RESET VECTORS
0FFFh
ACCUMULATOR
0FFh
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1
ST6200C/ST6201C/ST6203C
MEMORY MAP (Cont’d)
Figure 4. Program Memory Map
ST62T03C,T00C
ST62T01C, E01C
0000h
0000h
NOT IMPLEMENTED
NOT IMPLEMENTED
07FFh
0800h
*
RESERVED
087Fh
0880h
0AFFh
0B00h
*
RESERVED
0B9Fh
0BA0h
USER
PROGRAM MEMORY
USER
PROGRAM MEMORY
1824 BYTES
1024 BYTES
0F9Fh
0F9Fh
0FA0h
0FEFh
0FF0h
0FF7h
0FF8h
0FFBh
0FFCh
0FFDh
0FFEh
0FFFh
0FA0h
0FEFh
*
*
RESERVED
RESERVED
0FF0h
0FF7h
INTERRUPT VECTORS
INTERRUPT VECTORS
RESERVED*
0FF8h
0FFBh
RESERVED*
0FFCh
NMI VECTOR
0FFDh
NMI VECTOR
0FFEh
0FFFh
USER RESET VECTOR
USER RESET VECTOR
(*) Reserved areas should be filled with 0FFh
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1
ST6200C/ST6201C/ST6203C
MEMORY MAP (Cont’d)
3.1.2 Program Space
such as constants and look-up tables in OTP/
EPROM.
Program Space comprises the instructions to be
executed, the data required for immediate ad-
dressing mode instructions, the reserved factory
test area and the user vectors. Program Space is
addressed via the 12-bit Program Counter register
(PC register). Thus, the MCU is capable of ad-
dressing 4K bytes of memory directly.
3.1.4.1 Data ROM
All read-only data is physically stored in program
memory, which also accommodates the Program
Space. The program memory consequently con-
tains the program code to be executed, as well as
the constants and look-up tables required by the
application.
3.1.3 Readout Protection
The Program Memory in in OTP, EPROM or ROM
devices can be protected against external readout
of memory by setting the Readout Protection bit in
the option byte (Section 3.3 on page 15).
The Data Space locations in which the different
constants and look-up tables are addressed by the
processor core may be thought of as a 64-byte
window through which it is possible to access the
read-only data stored in OTP/EPROM.
In the EPROM parts, Readout Protection option
can be desactivated only by U.V. erasure that also
results in the whole EPROM context being erased.
3.1.4.2 Data RAM
The data space includes the user RAM area, the
accumulator (A), the indirect registers (X), (Y), the
short direct registers (V), (W), the I/O port regis-
ters, the peripheral data and control registers, the
interrupt option register and the Data ROM Win-
dow register (DRWR register).
Note: Once the Readout Protection is activated, it
is no longer possible, even for STMicroelectronics,
to gain access to the OTP or ROM contents. Re-
turned parts can therefore not be accepted if the
Readout Protection bit is set.
3.1.4 Data Space
3.1.5 Stack Space
Data Space accommodates all the data necessary
for processing the user program. This space com-
prises the RAM resource, the processor core and
peripheral registers, as well as read-only data
Stack space consists of six 12-bit registers which
are used to stack subroutine and interrupt return
addresses, as well as the current program counter
contents.
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1
ST6200C/ST6201C/ST6203C
MEMORY MAP (Cont’d)
Table 2. Hardware Register Map
Register
Reset
Address
Block
Register Name
X,Y index registers
Remarks
Status
Label
080h
to 083h
CPU
X,Y,V,W
xxh
R/W
V,W short direct registers
1) 2) 3)
0C0h
0C1h
DRA
DRB
Port A Data Register
Port B Data Register
00h
00h
R/W
R/W
I/O Ports
1) 2) 3)
0C2h
0C3h
Reserved (2 Bytes)
2)
0C4h
0C5h
DDRA
DDRB
Port A Direction Register
Port B Direction Register
00h
00h
R/W
R/W
I/O Ports
2)
0C6h
0C7h
Reserved (2 Bytes)
0C8h
0C9h
CPU
IOR
Interrupt Option Register
xxh
xxh
Write-only
Write-only
ROM
DRWR
Data ROM Window register
0CAh
0CBh
Reserved (2 Bytes)
2)
0CCh
0CDh
ORA
ORB
Port A Option Register
Port B Option Register
00h
00h
R/W
R/W
I/O Ports
2)
0CEh
0CFh
Reserved (2 bytes)
0D0h
0D1h
ADR
ADCR
A/D Converter Data Register
A/D Converter Control Register
xxh
40h
Read-only
Ro/Wo
ADC
7Fh
0FFh
0D2h
0D3h
0D4h
PSCR
TCR
TSCR
Timer 1 Prescaler Register
Timer 1 Downcounter Register
Timer 1 Status Control Register
R/W
R/W
R/W
Timer 1
00h
0FEh
xxh
0D5h
to 0D7h
Reserved (3 Bytes)
Watchdog Register
Watchdog
Timer
0D8h
WDGR
R/W
R/W
0D9h
to 0FEh
Reserved (38 Bytes)
Accumulator
0FFh
CPU
A
Legend:
x = undefined, R/W = Read/Write, Ro = Read-only Bit(s) in the register, Wo = Write-only Bit(s)
in the register.
Notes:
1. The contents of the I/O port DR registers are readable only in output configuration. In input configura-
tion, the values of the I/O pins are returned instead of the DR register contents.
2. The bits associated with unavailable pins must always be kept at their reset value.
3. Do not use single-bit instructions (SET, RES...) on Port Data Registers if any pin of the port is configured
in input mode (refer to Section 7 "I/O PORTS" on page 36 for more details).
4. Depending on device. See device summary on page 1.
11/100
1
ST6200C/ST6201C/ST6203C
MEMORY MAP (Cont’d)
3.1.6 Data ROM Window
3.1.6.1 Data ROM Window Register (DRWR)
The Data read-only memory window is located
from address 0040h to address 007Fh in Data
space. It allows direct reading of 64 consecutive
bytes located anywhere in program memory, be-
tween address 0000h and 0FFFh.
The DRWR can be addressed like any RAM loca-
tion in the Data Space.
This register is used to select the 64-byte block of
program memory to be read in the Data ROM win-
dow (from address 40h to address 7Fh in Data
space). The DRWR register is not cleared on re-
set, therefore it must be written to before access-
ing the Data read-only memory window area for
the first time.
There are 64 blocks of 64 bytes in a 4K device:
– Block 0 is related to the address range 0000h to
003Fh.
– Block 1 is related to the address range 0040h to
007Fh.
Address: 0C9h
—
Write Only
and so on...
Reset Value = xxh (undefined)
All the program memory can therefore be used to
store either instructions or read-only data. The
Data ROM window can be moved in steps of 64
bytes along the program memory by writing the
appropriate code in the Data ROM Window Regis-
ter (DRWR).
7
0
-
-
DRWR5 DRWR4 DRWR3 DRWR2 DRWR1 DRWR0
Figure 5. Data ROM Window
Bits 7:6 = Reserved, must be cleared.
PROGRAM
DATA SPACE
SPACE
0000h
000h
Bit 5:0 = DRWR[5:0] Data read-only memory Win-
dow Register Bits. These are the Data read-only
memory Window bits that correspond to the upper
bits of the data read-only memory space.
040h
07Fh
Caution: This register is undefined on reset, it is
write-only, therefore do not read it nor access it us-
ing Read-Modify-Write instructions (SET, RES,
INC and DEC).
DATA ROM
WINDOW
64-BYTE
ROM
0FFFh
0FFh
12/100
1
ST6200C/ST6201C/ST6203C
MEMORY MAP (Cont’d)
3.1.6.2 Data ROM Window memory addressing
tion is automatically handled by the ST6 develop-
ment tools.
In cases where some data (look-up tables for ex-
ample) are stored in program memory, reading
these data requires the use of the Data ROM win-
dow mechanism. To do this:
Please refer to the user manual of the correspod-
ing tool.
3.1.6.3 Recommendations
1. The DRWR register has to be loaded with the
64-byte block number where the data are located
(in program memory). This number also gives the
start address of the block.
Care is required when handling the DRWR regis-
ter as it is write only. For this reason, the DRWR
contents should not be changed while executing
an interrupt service routine, as the service routine
cannot save and then restore the register’s previ-
ous contents. If it is impossible to avoid writing to
the DRWR during the interrupt service routine, an
image of the register must be saved in a RAM lo-
cation, and each time the program writes to the
DRWR, it must also write to the image register.
The image register must be written first so that, if
an interrupt occurs between the two instructions,
the DRWR is not affected.
2. Then, the offset address of the byte in the Data
ROM Window (corresponding to the offset in the
64-byte block in program memory) has to be load-
ed in a register (A, X,...).
When the above two steps are completed, the
data can be read.
To understand how to determine the DRWR and
the content of the register, please refer to the ex-
ample shown in Figure 6. In any case the calcula-
Figure 6. Data ROM Window Memory Addressing
DATA SPACE
000h
PROGRAM SPACE
0000h
040h
OFFSET
21h
DATA
061h
07Fh
0400h
64 bytes
OFFSET
0421h
DATA
DRWR
0FFh
10h
07FFh
DATA address in Program memory : 421h
DRWR content : 421h / 3Fh (64) = 10H data is located in 64-bytes window number 10h
64-byte window start address : 10h x 3Fh = 400h
Register (A, X,...)content : Offset = (421h - 400h) + 40h ( Data ROM Window start address in data space) = 61h
13/100
1
ST6200C/ST6201C/ST6203C
3.2 PROGRAMMING MODES
3.2.1 Program Memory
EPROM/OTP programming mode is set by a
Note: OTP/EPROM devices can be programmed
with the development tools available from
STMicroelectronics (please refer to Section 12 on
page 95).
+12.5V voltage applied to the TEST/V pin. The
PP
programming flow of the ST62T00C, T01/E01C
and T03C is described in the User Manual of the
EPROM Programming Board.
3.2.2 EPROM Erasing
The EPROM devices can be erased by exposure
to Ultra Violet light. The characteristics of the MCU
are such that erasure begins when the memory is
exposed to light with a wave lengths shorter than
approximately 4000Å. It should be noted that sun-
light and some types of fluorescent lamps have
wavelengths in the range 3000-4000Å.
Table 3. ST6200C/03C Program Memory Map
Device Address
Description
0000h-0B9Fh
0BA0h-0F9Fh
0FA0h-0FEFh
0FF0h-0FF7h
0FF8h-0FFBh
0FFCh-0FFDh
0FFEh-0FFFh
Reserved
User ROM
Reserved
It is thus recommended that the window of the
MCU packages be covered by an opaque label to
prevent unintentional erasure problems when test-
ing the application in such an environment.
Interrupt Vectors
Reserved
NMI Interrupt Vector
Reset Vector
The recommended erasure procedure is exposure
to short wave ultraviolet light which have a wave-
length 2537Å. The integrated dose (i.e. U.V. inten-
sity x exposure time) for erasure should be a mini-
Table 4. ST6201C Program Memory Map
2
Device Address
Description
mum of 30W-sec/cm . The erasure time with this
dosage is approximately 30 to 40 minutes using an
ultraviolet lamp with 12000µW/cm power rating.
The EPROM device should be placed within
2.5cm (1inch) of the lamp tubes during erasure.
0000h-087Fh
0880h-0F9Fh
0FA0h-0FEFh
0FF0h-0FF7h
0FF8h-0FFBh
0FFCh-0FFDh
0FFEh-0FFFh
Reserved
User ROM
Reserved
2
Interrupt Vectors
Reserved
NMI Interrupt Vector
Reset Vector
14/100
1
ST6200C/ST6201C/ST6203C
3.3 OPTION BYTES
Each device is available for production in user pro-
grammable versions (OTP) as well as in factory
coded versions (ROM). OTP devices are shipped
to customers with a default content (00h), while
ROM factory coded parts contain the code sup-
plied by the customer. This implies that OTP de-
vices have to be configured by the customer using
the Option Bytes while the ROM devices are facto-
ry-configured.
0: Low Voltage Detector disabled
1: Low Voltage Detector enabled.
LSB OPTION BYTE
Bit 7 = PROTECT Readout Protection.
This option bit enables or disables external access
to the internal program memory.
0: Program memory not read-out protected
1: Program memory read-out protected
The two option bytes allow the hardware configu-
ration of the microcontroller to be selected.
The option bytes have no address in the memory
map and can be accessed only in programming
mode (for example using a standard ST6 program-
ming tool).
In masked ROM devices, the option bytes are
fixed in hardware by the ROM code (see Section
11.6.2 "ROM VERSION" on page 93). It is there-
fore impossible to read the option bytes.
Bit 6 = OSC Oscillator selection.
This option bit selects the main oscillator type.
0: Quartz crystal, ceramic resonator or external
clock
1: RC network
Bit 5 = Reserved, must be always cleared.
Bit 4 = Reserved, must be always set.
The option bytes can be only programmed once. It
is not possible to change the selected options after
they have been programmed.
Bit 3 = NMI PULL NMI Pull-Up on/off.
This option bit enables or disables the internal pull-
up on the NMI pin.
0: Pull-up disabled
1: Pull-up enabled
In order to reach the power consumption value in-
dicated in Section 10.4, the option byte must be
programmed to its default value. Otherwise, an
over-consumption will occur.
MSB OPTION BYTE
Bit 2 = Reserved, must be always set.
Bits 15:11 = Reserved, must be always cleared.
Bit 1 = WDACT Hardware or software watchdog.
This option bit selects the watchdog type.
0: Software (watchdog to be enabled by software)
1: Hardware (watchdog always enabled)
Bit 10 = Reserved, must be always set.
Bit 9 = EXTCNTL External STOP MODE control.
0: EXTCNTL mode not available. STOP mode is
not available with the watchdog active.
1: EXTCNTL mode available. STOP mode is avail-
able with the watchdog active by setting NMI pin
to one.
Bit 0 = OSGEN Oscillator Safeguard on/off.
This option bit enables or disables the oscillator
Safeguard (OSG) feature.
0: Oscillator Safeguard disabled
1: Oscillator Safeguard enabled
Bit 8 = LVD Low Voltage Detector on/off.
This option bit enable or disable the Low Voltage
Detector (LVD) feature.
MSB OPTION BYTE
LSB OPTION BYTE
15
8
7
0
EXT
PRO-
TECT
NMI
PULL
WD OSG
Reserved
CTL
LVD
OSC Res. Res.
Res.
X
ACT
EN
Default
Value
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
15/100
1
ST6200C/ST6201C/ST6203C
4 CENTRAL PROCESSING UNIT
4.1 INTRODUCTION
tions. The accumulator can be addressed in Data
Space as a RAM location at address FFh. Thus
the ST6 can manipulate the accumulator just like
any other register in Data Space.
The CPU Core of ST6 devices is independent of the
I/O or Memory configuration. As such, it may be
thought of as an independent central processor
communicating with on-chip I/O, Memory and Pe-
ripherals via internal address, data, and control
buses.
Index Registers (X, Y). These two registers are
used in Indirect addressing mode as pointers to
memory locations in Data Space. They can also
be accessed in Direct, Short Direct, or Bit Direct
addressing modes. They are mapped in Data
Space at addresses 80h (X) and 81h (Y) and can
be accessed like any other memory location.
4.2 MAIN FEATURES
■ 40 basic instructions
Short Direct Registers (V, W). These two regis-
ters are used in Short Direct addressing mode.
This means that the data stored in V or W can be
accessed with a one-byte instruction (four CPU cy-
cles). V and W can also be accessed using Direct
and Bit Direct addressing modes. They are
mapped in Data Space at addresses 82h (V) and
83h (W) and can be accessed like any other mem-
ory location.
■ 9 main addressing modes
■ Two 8-bit index registers
■ Two 8-bit short direct registers
■ Low power modes
■ Maskable hardware interrupts
■ 6-level hardware stack
4.3 CPU REGISTERS
Note: The X and Y registers can also be used as
The ST6FamilyCPUcorefeaturessixregistersand
three pairs of flags available to the programmer.
These are described in the following paragraphs.
Short Direct registers in the same way as V and W.
Program Counter (PC). The program counter is a
12-bit register which contains the address of the
next instruction to be executed by the core. This
ROM location may be an opcode, an operand, or
the address of an operand.
Accumulator (A). The accumulator is an 8-bit
general purpose register used in all arithmetic cal-
culations, logical operations, and data manipula-
Figure 7. CPU Registers
7
0
ACCUMULATOR
SIX LEVEL
STACK
RESET VALUE = xxh
7
0
0
X INDEX REGISTER
Y INDEX REGISTER
RESET VALUE = xxh
7
CN ZN
CI ZI
CNMI ZNMI
NORMAL FLAGS
INTERRUPT FLAGS
NMI FLAGS
RESET VALUE = xxh
7
0
0
V SHORT INDIRECT
REGISTER
RESET VALUE = xxh
7
W SHORT INDIRECT
REGISTER
RESET VALUE = xxh
11
0
PROGRAM COUNTER
RESET VALUE = RESET VECTOR @ 0FFEh-0FFFh
x = Undefined value
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ST6200C/ST6201C/ST6203C
CPU REGISTERS (Cont’d)
The 12-bit length allows the direct addressing of
4096 bytes in Program Space.
Z : Zero flag
This flag is set if the result of the last arithmetic or
logical operation was equal to zero; otherwise it is
cleared.
0: The result of the last operation is different from
zero
However, if the program space contains more than
4096 bytes, the additional memory in program
space can be addressed by using the Program
ROM Page register.
1: The result of the last operation is zero
The PC value is incremented after reading the ad-
dress of the current instruction. To execute relative
jumps, the PC and the offset are shifted through
the ALU, where they are added; the result is then
shifted back into the PC. The program counter can
be changed in the following ways:
Switching between the three sets of flags is per-
formed automatically when an NMI, an interrupt or
a RETI instruction occurs. As NMI mode is auto-
matically selected after the reset of the MCU, the
ST6 core uses the NMI flags first.
– JP (Jump) instruction
– CALL instruction
PC = Jump address
PC = Call address
Stack. The ST6 CPU includes a true LIFO (Last In
First Out) hardware stack which eliminates the
need for a stack pointer. The stack consists of six
separate 12-bit RAM locations that do not belong
to the data space RAM area. When a subroutine
call (or interrupt request) occurs, the contents of
each level are shifted into the next level down,
while the content of the PC is shifted into the first
level (the original contents of the sixth stack level
are lost). When a subroutine or interrupt return oc-
curs (RET or RETI instructions), the first level reg-
ister is shifted back into the PC and the value of
each level is popped back into the previous level.
– Relative Branch InstructionPC = PC +/- offset
– Interrupt
– Reset
PC = Interrupt vector
PC = Reset vector
– RET & RETI instructions PC = Pop (stack)
– Normal instruction PC = PC + 1
Flags (C, Z). The ST6 CPU includes three pairs of
flags (Carry and Zero), each pair being associated
with one of the three normal modes of operation:
Normal mode, Interrupt mode and Non Maskable
Interrupt mode. Each pair consists of a CARRY
flag and a ZERO flag. One pair (CN, ZN) is used
during Normal operation, another pair is used dur-
ing Interrupt mode (CI, ZI), and a third pair is used
in the Non Maskable Interrupt mode (CNMI, ZN-
MI).
Figure 8. Stack manipulation
PROGRAM
COUNTER
The ST6 CPU uses the pair of flags associated
with the current mode: as soon as an interrupt (or
a Non Maskable Interrupt) is generated, the ST6
CPU uses the Interrupt flags (or the NMI flags) in-
stead of the Normal flags. When the RETI instruc-
tion is executed, the previously used set of flags is
restored. It should be noted that each flag set can
only be addressed in its own context (Non Maska-
ble Interrupt, Normal Interrupt or Main routine).
The flags are not cleared during context switching
and thus retain their status.
ON RETURN
FROM
ON
LEVEL 1
LEVEL 2
LEVEL 3
LEVEL 4
LEVEL 5
LEVEL 6
INTERRUPT,
OR
INTERRUPT,
OR
SUBROUTINE
CALL
SUBROUTINE
Since the accumulator, in common with all other
data space registers, is not stored in this stack,
management of these registers should be per-
formed within the subroutine.
C : Carry flag.
This bit is set when a carry or a borrow occurs dur-
ing arithmetic operations; otherwise it is cleared.
The Carry flag is also set to the value of the bit
tested in a bit test instruction; it also participates in
the rotate left instruction.
0: No carry has occured
1: A carry has occured
Caution: The stack will remain in its “deepest” po-
sition if more than 6 nested calls or interrupts are
executed, and consequently the last return ad-
dress will be lost.
It will also remain in its highest position if the stack
is empty and a RET or RETI is executed. In this
case the next instruction will be executed.
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ST6200C/ST6201C/ST6203C
5 CLOCKS, SUPPLY AND RESET
5.1 CLOCK SYSTEM
The main oscillator of the MCU can be driven by
any of these clock sources:
Table 5 illustrates various possible oscillator con-
figurations using an external crystal or ceramic
resonator, an external clock input, an external re-
– external clock signal
sistor (R
the LFAO.
), or the lowest cost solution using only
NET
– external AT-cut parallel-resonant crystal
– external ceramic resonator
For more details on configuring the clock options,
refer to the Option Bytes section of this document.
– external RC network (R
).
NET
The internal MCU clock frequency (f ) is divided
In addition, an on-chip Low Frequency Auxiliary
Oscillator (LFAO) is available as a back-up clock
system or to reduce power consumption.
INT
by 12 to drive the Timer, the Watchdog timer and
the A/D converter, by 13 to drive the CPU core and
the SPI and by 1 or 3 to drive the ARTIMER, as
shown in Figure 9.
An optional Oscillator Safeguard (OSG) filters
spikes from the oscillator lines, and switches to the
LFAO backup oscillator in the event of main oscil-
lator failure. It also automatically limits the internal
With an 8 MHz oscillator, the fastest CPU cycle is
therefore 1.625µs.
clock frequency (f ) as a function of V , in order
to guarantee correct operation. These functions
are illustrated in Figure 10, and Figure 11.
INT
DD
A CPU cycle is the smallest unit of time needed to
execute any operation (for instance, to increment
the Program Counter). An instruction may require
two, four, or five CPU cycles for execution.
Figure 9. Clock Circuit Block Diagram
OSCILLATOR SAFEGUARD (OSG)
SPI
: 13
f
OSG
CORE
OSC
filtering
8-BIT TIMER
WATCHDOG
0
1
Oscillator
Divider
f
MAIN
OSCILLATOR
INT
: 12
*
ADC
LFAO
: 1
: 3
OSCOFF BIT
(ADCR REGISTER)
8-BIT ARTIMER
8-BIT ARTIMER
*
OSG ENABLE OPTION BIT (See OPTION BYTE SECTION)
* Depending on device. See device summary on page 1.
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ST6200C/ST6201C/ST6203C
CLOCK SYSTEM (Cont’d)
5.1.1 Main Oscillator
Table 5. Oscillator Configurations
The oscillator configuration is specified by select-
ing the appropriate option in the option bytes (refer
to the Option Bytes section of this document).
When the CRYSTAL/RESONATOR option is se-
lected, it must be used with a quartz crystal, a ce-
ramic resonator or an external signal provided on
the OSCin pin. When the RC NETWORK option is
selected, the system clock is generated by an ex-
ternal resistor (the capacitor is implemented inter-
nally).
Hardware Configuration
External Clock
ST6
OSCin
OSCout
NC
EXTERNAL
CLOCK
The main oscillator can be turned off (when the
OSG ENABLED option is selected) by setting the
OSCOFF bit of the ADC Control Register (not
available on some devices). This will automatically
start the Low Frequency Auxiliary Oscillator
(LFAO).
2)
Crystal/Resonator Clock
ST6
OSCin
OSCout
The main oscillator can be turned off by resetting
the OSCOFF bit of the A/D Converter Control Reg-
ister or by resetting the MCU. When the main os-
cillator starts there is a delay made up of the oscil-
lator start-up delay period plus the duration of the
C
C
L2
L1
software instruction at a clock frequency f
.
LOAD
CAPACITORS
LFAO
3)
Caution: It should be noted that when the RC net-
work option is selected, the accuracy of the fre-
quency is about 20% so it may not be suitable for
some applications (For more details, please refer
to the Electrical Characteristics Section).
RC Network
ST6
OSCin
NC
OSCout
R
NET
LFAO
ST6
OSCin
OSCout
NC
Notes:
1. To select the options shown in column 1 of the above
table, refer to the Option Byte section.
2.This schematic are given for guidance only and are sub-
ject to the schematics given by the crystal or ceramic res-
onator manufacturer.
3. For more details, please refer to the Electrical Charac-
teristics Section.
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ST6200C/ST6201C/ST6203C
CLOCK SYSTEM (Cont’d)
5.1.2 Oscillator Safeguard (OSG)
imum internal clock frequency, f , is limited to
INT
OSG
f
, which is supply voltage dependent.
The Oscillator Safeguard (OSG) feature is a
means of dramatically improving the operational
integrity of the MCU. It is available when the OSG
ENABLED option is selected in the option byte (re-
fer to the Option Bytes section of this document).
5.1.2.2 Management of Supply Voltage
Variations
Over-frequency, at a given power supply level, is
seen by the OSG as spikes; it therefore filters out
some cycles in order that the internal clock fre-
quency of the device is kept within the range the
The OSG acts as a filter whose cross-over fre-
quency is device dependent and provides three
basic functions:
particular device can stand (depending on V ),
DD
and below f
cy with OSG enabled.
: the maximum authorised frequen-
OSG
– Filtering spikes on the oscillator lines which
would result in driving the CPU at excessive fre-
quencies
5.1.2.3 LFAO Management
– Management of the Low Frequency Auxiliary
Oscillator (LFAO), (useable as low cost internal
clock source, backup clock in case of main oscil-
lator failure or for low power consumption)
When the OSG is enabled, the Low Frequency
Auxiliary Oscillator can be used (see Section
5.1.3).
– Automatically limiting the f
a function of supply voltage, to ensure correct
operation even if the power supply drops.
clock frequency as
Note: The OSG should be used wherever possible
as it provides maximum security for the applica-
tion. It should be noted however, that it can in-
crease power consumption and reduce the maxi-
INT
5.1.2.1 Spike Filtering
mum operating frequency to f
Characteristics section).
(see Electrical
OSG
Spikes on the oscillator lines result in an effectively
increased internal clock frequency. In the absence
of an OSG circuit, this may lead to an over fre-
quency for a given power supply voltage. The
OSG filters out such spikes (as illustrated in Figure
10). In all cases, when the OSG is active, the max-
Caution: Care has to be taken when using the
OSG, as the internal frequency is defined between
a minimum and a maximum value and may vary
depending on both V and temperature. For pre-
DD
cise timing measurements, it is not recommended
to use the OSG.
Figure 10. OSG Filtering Function
f
f
f
f
OSC< OSG
OSC> OSG
f
f
OSC
OSG
f
INT
Figure 11. LFAO Oscillator Function
MAIN OSCILLATOR
STOPS
MAIN OSCILLATOR
RESTARTS
f
f
OSC
LFAO
f
INT
INTERNAL CLOCK DRIVEN BY LFAO
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ST6200C/ST6201C/ST6203C
CLOCK SYSTEM (Cont’d)
5.1.3 Low Frequency Auxiliary Oscillator
(LFAO)
The Low Frequency Auxiliary Oscillator is auto-
matically switched off as soon as the main oscilla-
tor starts.
The Low Frequency Auxiliary Oscillator has three
main purposes. Firstly, it can be used to reduce
power consumption in non timing critical routines.
Secondly, it offers a fully integrated system clock,
without any external components. Lastly, it acts as
a backup oscillator in case of main oscillator fail-
ure.
5.1.4 Register Description
ADC CONTROL REGISTER (ADCR)
Address: 0D1h
—
Read/Write
Reset value: 0100 0000 (40h)
This oscillator is available when the OSG ENA-
BLED option is selected in the option byte (refer to
the Option Bytes section of this document). In this
case, it automatically starts one of its periods after
the first missing edge of the main oscillator, what-
ever the reason for the failure (main oscillator de-
fective, no clock circuitry provided, main oscillator
switched off...). See Figure 11.
7
0
ADCR ADCR ADCR ADCR ADCR OSC ADCR ADCR
OFF
7
6
5
4
3
1
0
Bit 7:3, 1:0 = ADCR[7:3], ADCR[1:0] ADC Control
Register.
These bits are used to control the A/D converter (if
available on the device) otherwise they are not
used.
User code, normal interrupts, WAIT and STOP in-
structions, are processed as normal, at the re-
duced f
frequency. The A/D converter accura-
LFAO
Bit 2 = OSCOFF Main Oscillator Off.
0: Main oscillator enabled
1: Main oscillator disabled
cy is decreased, since the internal frequency is be-
low 1.2 MHz.
At power on, until the main oscillator starts, the re-
set delay counter is driven by the LFAO. If the
main oscillator starts before the 2048 or 32768 cy-
cle delay has elapsed, it takes over.
Note: The OSG must be enabled using the OS-
GEN option in the Option Byte, otherwise the OS-
COFF setting has no effect.
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ST6200C/ST6201C/ST6203C
5.2 LOW VOLTAGE DETECTOR (LVD)
The on-chip Low Voltage Detector is enabled by
setting a bit in the option bytes (refer to the Option
Bytes section of this document).
The LVD Reset circuitry generates a reset when
is below:
V
DD
– VIT+ when V is rising
DD
The LVD allows the device to be used without any
external RESET circuitry. In this case, the RESET
pin should be left unconnected.
– VIT- when V is falling
DD
The LVD function is illustrated in Figure 12.
If the LVD is enabled, the MCU can be in only one
of two states:
If the LVD is not used, an external circuit is manda-
tory to ensure correct Power On Reset operation,
see figure in the Reset section. For more details,
please refer to the application note AN669.
– Over the input threshold voltage, it is running un-
der full software control
The LVD generates a static Reset when the supply
voltage is below a reference value. This means
that it secures the power-up as well as the power-
down keeping the ST6 in reset.
– Below the input threshold voltage, it is in static
safe reset
In these conditions, secure operation is guaran-
teed without the need for external reset hardware.
The VIT- reference value for a voltage drop is lower
than the VIT+ reference value for power-on in order
to avoid a parasitic reset when the MCU starts run-
ning and sinks current on the supply (hysteresis).
During a Low Voltage Detector Reset, the RESET
pin is held low, thus permitting the MCU to reset
other devices.
Figure 12. Low Voltage Detector Reset
V
DD
V
hyst
V
V
IT+
IT-
RESET
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ST6200C/ST6201C/ST6203C
5.3 RESET
5.3.1 Introduction
The RESET vector fetch phase duration is 2 clock
cycles.
The MCU can be reset in three ways:
■ A low pulse input on the RESET pin
■ Internal Watchdog reset
When a reset occurs:
– The stack is cleared
– The PC is loaded with the address of the Reset
vector. It is located in program ROM starting at
address 0FFEh.
■ Internal Low Voltage Detector (LVD) reset
5.3.2 RESET Sequence
The basic RESET sequence consists of 3 main
phases:
■ Internal (watchdog or LVD) or external Reset
A jump to the beginning of the user program must
be coded at this address.
– The interrupt flag is automatically set, so that the
CPU is in Non Maskable Interrupt mode. This
prevents the initialization routine from being in-
terrupted. The initialization routine should there-
fore be terminated by a RETI instruction, in order
to go back to normal mode.
event
■ A delay of 2048 or 32768 clock (f ) cycles
INT
(selected through the option bytes)
■ RESET vector fetch
The reset delay allows the oscillator to stabilise
and ensures that recovery has taken place from
the Reset state.
Figure 13. RESET Sequence
V
DD
V
V
IT+
IT-
WATCHDOG
RESET
WATCHDOG UNDERFLOW
LVD
RESET
RESET PIN
INTERNAL
RESET
RUN
RUN
RUN
RUN
RESET
RESET
RESET
2048 CLOCK CYCLE (f
) DELAY
INT
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RESET (Cont’d)
5.3.3 RESET Pin
If the RESET pin is grounded while the MCU is in
RUN or WAIT modes, processing of the user pro-
gram is stopped (RUN mode only), the I/O ports
are configured as inputs with pull-up resistors and
the main oscillator is restarted. When the level on
the RESET pin then goes high, the initialization se-
quence is executed at the end of the internal delay
period.
The RESET pin may be connected to a device on
the application board in order to reset the MCU if
required. The RESET pin may be pulled low in
RUN, WAIT or STOP mode. This input can be
used to reset the internal state of the MCU and en-
sure it starts-up correctly. The pin, which is con-
nected to an internal pull-up, is active low and fea-
tures a Schmitt trigger input. A delay (2048 clock
cycles) added to the external signal ensures that
even short pulses on the RESET pin are accepted
If the RESET pin is grounded while the MCU is in
STOP mode, the oscillator starts up and all the I/O
ports are configured as inputs with pull-up resis-
tors. When the RESET pin level then goes high,
the initialization sequence is executed at the end
of the internal delay period.
as valid, provided V
has completed its rising
DD
phase and that the oscillator is running correctly
(normal RUN or WAIT modes). The MCU is kept in
the Reset state as long as the RESET pin is held
low.
A simple external RESET circuitry is shown in Fig-
ure 15. For more details, please refer to the appli-
cation note AN669.
Figure 14. Reset Block Diagram
INTERNAL
RESET
f
INT
V
DD
R
PU
RESET
1)
R
ESD
WATCHDOG RESET
LVD RESET
1) Resistive ESD protection.
2) The reset delay value is selected through the option bytes.
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ST6200C/ST6201C/ST6203C
RESET (Cont’d)
5.3.4 Watchdog Reset
Figure 16. Reset Processing
The MCU provides a Watchdog timer function in
order to be able to recover from software hang-
ups. If the Watchdog register is not refreshed be-
fore an end-of-count condition is reached, a
Watchdog reset is generated.
RESET
2048 OR 32768
CLOCK CYCLE
DELAY
After a Watchdog reset, the MCU restarts in the
same way as if a Reset was generated by the RE-
SET pin.
INTERNAL
RESET
Note: When a watchdog reset occurs, the RESET
pin is tied low for very short time period, to flag the
reset phase. This time is not long enough to reset
external circuits.
NMI MASK SET
INT LATCH CLEARED
(IF PRESENT)
For more details refer to the Watchdog Timer
chapter.
SELECT
NMI MODE FLAGS
5.3.5 LVD Reset
Two different RESET sequences caused by the in-
ternal LVD circuitry can be distinguished:
■ Power-On RESET
PUT FFEh
■ Voltage Drop RESET
ON ADDRESS BUS
During an LVD reset, the RESET pin is pulled low
when V <VIT+ (rising edge) or V <VIT- (falling
DD
DD
edge).
YES
For more details, refer to the LVD chapter.
IS RESET STILL
PRESENT?
Caution: Do not externally connect directly the
RESET pin to VDD, this may cause damage to the
component in case of internal RESET (Watchdog
or LVD).
NO
LOAD PC
FROM RESET LOCATIONS
FFEh/FFFh
Figure 15. Simple External Reset Circuitry
V
V
DD
DD
FETCH INSTRUCTION
R
C
RESET
ST62xx
R > 4.7 K
Typical: R = 10K
C = 10nF
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5.4 INTERRUPTS
The ST6 core may be interrupted by four maska-
ble interrupt sources, in addition to a Non Maska-
ble Interrupt (NMI) source. The interrupt process-
ing flowchart is shown in Figure 18.
struction to the associated interrupt service rou-
tine.
When an interrupt source generates an interrupt
request, the PC register is loaded with the address
of the interrupt vector, which then causes a Jump
to the relevant interrupt service routine, thus serv-
icing the interrupt.
Maskable interrupts must be enabled by setting
the GEN bit in the IOR register. However, even if
they are disabled (GEN bit = 0), interrupt events
are latched and may be processed as soon as the
GEN bit is set.
Interrupt are triggered by events either on external
pins, or from the on-chip peripherals. Several
events can be ORed on the same interrupt vector.
On-chip peripherals have flag registers to deter-
mine which event triggered the interrupt.
Each source is associated with a specific Interrupt
Vector, located in Program space (see Table 7). In
the vector location, the user must write a Jump in-
Figure 17. Interrupts Block Diagram
V
DD
VECTOR #0
NMI
LATCH
CLEARED BY H/W
AT START OF VECTOR #0 ROUTINE
I/O PORT REGISTER
“INPUT WITH INTERRUPT”
CONFIGURATION
PA1..PA3
LATCH
0
VECTOR #1
CLEARED BY H/W
AT START OF
1
VECTOR #1 ROUTINE
LES BIT
(IOR REGISTER)
EXIT FROM
STOP/WAIT
PB0..PB1
PB3
PB5..PB7
I/O PORT REGISTER
“INPUT WITH INTERRUPT”
CONFIGURATION
VECTOR #2
LATCH
ESB BIT
(IOR REGISTER)
CLEARED
BY H/W AT START OF
VECTOR #2 ROUTINE
TMZ BIT
ETI BIT
VECTOR #3
VECTOR #4
TIMER
(TSCR REGISTER)
EAI BIT
EOC BIT
A/D CONVERTER *
(ADCR REGISTER)
GEN BIT
(IOR REGISTER)
* Depending on device. See device summary on page 1.
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5.5 INTERRUPT RULES AND PRIORITY
MANAGEMENT
5.7 NON MASKABLE INTERRUPT
This interrupt is triggered when a falling edge oc-
curs on the NMI pin regardless of the state of the
GEN bit in the IOR register. An interrupt request
on NMI vector #0 is latched by a flip flop which is
automatically reset by the core at the beginning of
the NMI service routine.
■ A Reset can interrupt the NMI and peripheral
interrupt routines
■ The Non Maskable Interrupt request has the
highest priority and can interrupt any peripheral
interrupt routine at any time but cannot interrupt
another NMI interrupt.
■ No peripheral interrupt can interrupt another. If
more than one interrupt request is pending,
these are processed by the processor core
according to their priority level: vector #1 has the
highest priority while vector #4 the lowest. The
priority of each interrupt source is fixed by
hardware (see Interrupt Mapping table).
5.8 PERIPHERAL INTERRUPTS
Different peripheral interrupt flags in the peripheral
control registers are able to cause an interrupt
when they are active if both:
– The GEN bit of the IOR register is set
– The corresponding enable bit is set in the periph-
eral control register.
5.6 INTERRUPTS AND LOW POWER MODES
Peripheral interrupts are linked to vectors #3 and
#4. Interrupt requests are flagged by a bit in their
corresponding control register. This means that a
request cannot be lost, because the flag bit must
be cleared by user software.
All interrupts cause the processor to exit from
WAIT mode. Only the external and some specific
interrupts from the on-chip peripherals cause the
processor to exit from STOP mode (refer to the
“Exit from STOP“ column in the Interrupt Mapping
Table).
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5.9 EXTERNAL INTERRUPTS (I/O Ports)
External interrupt vectors can be loaded into the
PC register if the corresponding external interrupt
occurred and if the GEN bit is set. These interrupts
allow the processor to exit from STOP mode.
This is due to the vector #2 circuitry.The worka-
round is to discard this first interrupt request in the
routine (using a flag for example).
Masking of One Interrupt by Another on Vector
#2.
The external interrupt polarity is selected through
the IOR register.
When two or more port pins (associated with inter-
rupt vector #2) are configured together as input
with interrupt (falling edge sensitive), as long as
one pin is stuck at ’0’, the other pin can never gen-
erate an interrupt even if an active edge occurs at
this pin. The same thing occurs when one pin is
stuck at ’1’ and interrupt vector #2 is configured as
rising edge sensitive.
External interrupts are linked to vectors #1 and #
2.
Interrupt requests on vector #1 can be configured
either as edge or level-sensitive using the LES bit
in the IOR Register.
Interrupt requests from vector #2 are always edge
sensitive. The edge polarity can be configured us-
ing the ESB bit in the IOR Register.
To avoid this the first pin must input a signal that
goes back up to ’1’ right after the falling edge. Oth-
erwise, in the interrupt routine for the first pin, de-
activate the “input with interrupt” mode using the
port control registers (DDR, OR, DR). An active
edge on another pin can then be latched.
In edge-sensitive mode, a latch is set when a edge
occurs on the interrupt source line and is cleared
when the associated interrupt routine is started.
So, an interrupt request can be stored until com-
pletion of the currently executing interrupt routine,
before being processed. If several interrupt re-
quests occurs before completion of the current in-
terrupt routine, only the first request is stored.
I/O port Configuration Spurious Interrupt on
Vector #2
If a pin associated with interrupt vector #2 is in ‘in-
put with pull-up’ state, a ‘0’ level is present on the
pin and the ESB bit = 0, when the I/O pin is config-
ured as interrupt with pull-up by writing to the
DDRx, ORx and DRx register bits, an interrupt is
latched although a falling edge may not have oc-
curred on the associated pin.
Storing of interrupt requests is not possible in level
sensitive mode. To be taken into account, the low
level must be present on the interrupt pin when the
MCU samples the line after instruction execution.
5.9.1 Notes on using External Interrupts
ESB bit Spurious Interrupt on Vector #2
In the opposite case, if the pin is in interrupt with
pull-up state , a 0 level is present on the pin and
the ESB bit =1, when the I/O port is configured as
input with pull-up by writing to the DDRx, ORx and
DRx bits, an interrupt is latched although a rising
edge may not have occurred on the associated
pin.
If a pin associated with interrupt vector #2 is con-
figured as interrupt with pull-up, whenever vector
#2 is configured to be rising edge sensitive (by set-
ting the ESB bit in the IOR register), an interrupt is
latched although a rising edge may not have oc-
cured on the associated pin.
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5.10 INTERRUPT HANDLING PROCEDURE
The interrupt procedure is very similar to a call pro-
cedure, in fact the user can consider the interrupt
as an asynchronous call procedure. As this is an
asynchronous event, the user cannot know the
context and the time at which it occurred. As a re-
sult, the user should save all Data space registers
which may be used within the interrupt routines.
The following list summarizes the interrupt proce-
dure:
Figure 18. Interrupt Processing Flow Chart
INSTRUCTION
FETCH
INSTRUCTION
EXECUTE
INSTRUCTION
When an interrupt request occurs, the following
actions are performed by the MCU automatically:
LOAD PC FROM
INTERRUPT VECTOR
– The core switches from the normal flags to the
interrupt flags (or the NMI flags).
– The PC contents are stored in the top level of the
stack.
– The normal interrupt lines are inhibited (NMI still
active).
– The internal latch (if any) is cleared.
WAS
THE INSTRUCTION
NO
CLEAR
INTERNAL LATCH *)
?
A RETI
YES
IS THE CORE
ALREADY IN
NORMAL MODE?
YES
DISABLE
MASKABLE INTERRUPT
– TheassociatedinterruptvectorisloadedinthePC.
NO
When an interrupt request occurs, the following
actions must be performed by the user software:
ENABLE
MASKABLE INTERRUPTS
PUSH THE
PC INTO THE STACK
– User selected registers have to be saved within
the interrupt service routine (normally on a soft-
ware stack).
SELECT
NORMAL FLAGS
SELECT
– The source of the interrupt must be determined
by polling the interrupt flags (if more than one
source is associated with the same vector).
– The RETI (RETurn from Interrupt) instruction
must end the interrupt service routine.
INTERRUPT FLAGS
“POP”
THE STACKED PC
After the RETI instruction is executed, the MCU re-
turns to the main routine.
NO
IS THERE AN
AN INTERRUPT REQUEST
AND INTERRUPT MASK?
Caution: When a maskable interrupt occurs while
the ST6 core is in NORMAL mode and during the
execution of an “ldi IOR, 00h” instruction (disabling
all maskable interrupts): if the interrupt request oc-
curs during the first 3 cycles of the “ldi” instruction
(which is a 4-cycle instruction) the core will switch
to interrupt mode BUT the flags CN and ZN will
NOT switch to the interrupt pair CI and ZI.
YES
*) If a latch is present on the interrupt source line
Table 6. Interrupt Response Time
Minimum
Maximum
6 CPU cycles
11 CPU cycles
5.10.1 Interrupt Response Time
This is defined as the time between the moment
when the Program Counter is loaded with the in-
terrupt vector and when the program has jump to
the interrupt subroutine and is ready to execute
the code. It depends on when the interrupt occurs
while the core is processing an instruction.
One CPU cycle is 13 external clock cycles thus 11
CPU cycles = 11 x (13 /8M) = 17.875 µs with an 8
MHz external quartz.
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5.11 REGISTER DESCRIPTION
INTERRUPT OPTION REGISTER (IOR)
1: Low level sensitive mode is selected for inter-
rupt vector #1
Address: 0C8h
—
Write Only
Reset status: 00h
Bit 5 = ESB Edge Selection bit.
0: Falling edge mode on interrupt vector #2
1: Rising edge mode on interrupt vector #2
7
-
0
-
LES ESB GEN
-
-
-
Bit 4 = GEN Global Enable Interrupt.
0: Disable all maskable interrupts
1: Enable all maskable interrupts
Caution: This register is write-only and cannot be
accessed by single-bit operations (SET, RES,
DEC,...).
Note: When the GEN bit is cleared, the NMI inter-
rupt is active but cannot be used to exit from STOP
or WAIT modes.
Bit 7 =Reserved, must be cleared.
Bits 3:0 = Reserved, must be cleared.
Bit 6 = LES Level/Edge Selection bit.
0: Falling edge sensitive mode is selected for inter-
rupt vector #1
Table 7. Interrupt Mapping
Exit
from
STOP
Vector
Source
Block
Register
Label
Vector
Address
Priority
Order
Description
Flag
number
RESET
NMI
Reset
N/A
N/A
N/A
N/A
yes
yes
FFEh-FFFh
FFCh-FFDh
FFAh-FFBh
FF8h-FF9h
FF6h-FF7h
FF4h-FF5h
FF2h-FF3h
FF0h-FF1h
Highest
Priority
Vector #0
Non Maskable Interrupt
NOT USED
Vector #1 Port A
Vector #2 Port B
Vector #3 TIMER
Ext. Interrupt Port A
Ext. Interrupt Port B
Timer underflow
N/A
N/A
N/A
N/A
yes
yes
yes
no
Lowest
Priority
TSCR
ADCR
TMZ
EOC
Vector #4
ADC *
End Of Conversion
* Depending on device. See device summary on page 1.
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6 POWER SAVING MODES
6.1 INTRODUCTION
To give a large measure of flexibility to the applica-
tion in terms of power consumption, two main pow-
er saving modes are implemented in the ST6 (see
Figure 19).
Figure 19. Power Saving Mode Transitions
High
RUN
In addition, the Low Frequency Auxiliary Oscillator
(LFAO) can be used instead of the main oscillator
to reduce power consumption in RUN and WAIT
modes.
LFAO
WAIT
After a RESET the normal operating mode is se-
lected by default (RUN mode). This mode drives
the device (CPU and embedded peripherals) by
means of a master clock which is based on the
main oscillator frequency.
STOP
From Run mode, the different power saving
modes may be selected by calling the specific ST6
software instruction or for the LFAO by setting the
relevant register bit. For more information on the
LFAO, please refer to the Clock chapter.
Low
POWER CONSUMPTION
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6.2 WAIT MODE
The MCU goes into WAIT mode as soon as the
WAIT instruction is executed. This has the follow-
ing effects:
Figure 20. WAIT Mode Flowchart
OSCILLATOR
On
– Program execution is stopped, the microcontrol-
ler software can be considered as being in a “fro-
zen” state.
Clock to PERIPHERALS Yes
WAIT INSTRUCTION
Clock to CPU
No
– RAM contents and peripheral registers are pre-
served as long as the power supply voltage is
higher than the RAM retention voltage.
N
– The oscillator is kept running to provide a clock
to the peripherals; they are still active.
RESET
WAIT mode can be used when the user wants to
reduce the MCU power consumption during idle
periods, while not losing track of time or the ability
to monitor external events. WAIT mode places the
MCU in a low power consumption mode by stop-
ping the CPU. The active oscillator (main oscillator
or LFAO) is kept running in order to provide a clock
signal to the peripherals.
N
Y
INTERRUPT
Y
OSCILLATOR
Restart
If the power consumption has to be further re-
duced, the Low Frequency Auxiliary Oscillator
(LFAO) can be used in place of the main oscillator,
if its operating frequency is lower. If required, the
LFAO must be switched on before entering WAIT
mode.
Clock to PERIPHERALS Yes
Clock to CPU Yes
2048 OR 32768
CLOCK CYCLE
DELAY
Exit from Wait mode
The MCU remains in WAIT mode until one of the
following events occurs:
– RESET (Watchdog, LVD or RESET pin)
– A peripheral interrupt (timer, ADC,...),
OSCILLATOR
On
Clock to PERIPHERALS Yes
– An external interrupt (I/O port, NMI)
The Program Counter then branches to the start-
ing address of the interrupt or RESET service rou-
tine. Refer to Figure 20.
Clock to CPU
Yes
See also Section 6.4.1.
FETCH RESET VECTOR
OR SERVICE INTERRUPT
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6.3 STOP MODE
STOP mode is the lowest power consumption
mode of the MCU (see Figure 22).
The Program Counter then points to the starting
address of the interrupt or RESET service routine
(see Figure 21).
The MCU goes into STOP mode as soon as the
STOP instruction is executed. This has the follow-
ing effects:
STOP Mode and Watchdog
When the Watchdog is active (hardware or soft-
ware activation), the STOP instruction is disabled
and a WAIT instruction will be executed in its place
unless the EXCTNL option bit is set to 1 in the op-
tion bytes and a a high level is present on the NMI
pin. In this case, the STOP instruction will be exe-
cuted and the Watchdog will be frozen.
– Program execution is stopped, the microcontrol-
ler can be considered as being “frozen”.
– The contents of RAM and the peripheral regis-
ters are kept safely as long as the power supply
voltage is higher than the RAM retention voltage.
– The oscillator is stopped, so peripherals cannot
work except the those that can be driven by an
external clock.
Figure 21. STOP Mode Timing Overview
2048 or 32768
CLOCKCYCLE
Exit from STOP Mode
RUN
STOP
RUN
DELAY
The MCU remains in STOP mode until one of the
following events occurs:
– RESET (Watchdog, LVD or RESET pin)
STOP
INSTRUCTION
– A peripheral interrupt (assuming this peripheral
can be driven by an external clock)
– An external interrupt (I/O port, NMI)
In all cases a delay of 2048 or 32768 clock cycles
(fINT) is generated to make sure the oscillator has
started properly.
RESET
OR
INTERRUPT
FETCH
VECTOR
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STOP MODE (Cont’d)
Figure 22. STOP Mode Flowchart
STOP INSTRUCTION
ENABLE
WATCHDOG
DISABLE
1
EXCTNL
1)
VALUE
0
LEVEL
ON
OSCILLATOR
Off
1
2)
Clock to PERIPHERALS No
0
NMI PIN
Clock to CPU
No
N
RESET
OSCILLATOR
On
Clock to PERIPHERALS Yes
Clock to CPU No
N
3)
Y
INTERRUPT
Y
OSCILLATOR
Restart
Clock to PERIPHERALS Yes
Clock to CPU Yes
Y
N
RESET
2048 or 32768
N
DELAY
CLOCK CYCLE
INTERRUPT
OSCILLATOR
On
Y
Clock to PERIPHERALS Yes
Clock to CPU Yes
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Notes:
1. EXCTNL is an option bit. See option byte section for more details.
2. Peripheral clocked with an external clock source can still be active.
3. Only some specific interrupts can exit the MCU from STOP mode (such as external interrupt). Refer to
the Interrupt Mapping table for more details.
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6.4 NOTES RELATED TO WAIT AND STOP MODES
6.4.1 Exit from Wait and Stop Modes
6.4.1.1 NMI Interrupt
as soon as an interrupt occurs. Nevertheless, two
cases must be considered:
– If the interrupt is a normal one, the interrupt rou-
tine in which the WAIT or STOP mode was en-
tered will be completed, starting with the
execution of the instruction which follows the
STOP or the WAIT instruction, and the MCU is
still in interrupt mode. At the end of this routine
pending interrupts will be serviced according to
their priority.
It should be noted that when the GEN bit in the
IOR register is low (interrupts disabled), the NMI
interrupt is active but cannot cause a wake up from
STOP/WAIT modes.
6.4.1.2 Restart Sequence
When the MCU exits from WAIT or STOP mode, it
should be noted that the restart sequence de-
pends on the original state of the MCU (normal, in-
terrupt or non-maskable interrupt mode) prior to
entering WAIT or STOP mode, as well as on the
interrupt type.
– In the event of a non-maskable interrupt, the
non-maskable interrupt service routine is proc-
essed first, then the routine in which the WAIT or
STOP mode was entered will be completed by
executing the instruction following the STOP or
WAIT instruction. The MCU remains in normal in-
terrupt mode.
Normal Mode. If the MCU was in the main routine
when the WAIT or STOP instruction was execut-
ed, exit from Stop or Wait mode will occur as soon
as an interrupt occurs; the related interrupt routine
is executed and, on completion, the instruction
which follows the STOP or WAIT instruction is
then executed, providing no other interrupts are
pending.
6.4.2 Recommended MCU Configuration
For lowest power consumption during RUN or
WAIT modes, the user software must configure
the MCU as follows:
– Configure unused I/Os as output push-pull low
mode
Non Maskable Interrupt Mode. If the STOP or
WAIT instruction has been executed during execu-
tion of the non-maskable interrupt routine, the
MCU exits from Stop or Wait mode as soon as an
interrupt occurs: the instruction which follows the
STOP or WAIT instruction is executed, and the
MCU remains in non-maskable interrupt mode,
even if another interrupt has been generated.
– Place all peripherals in their power down modes
before entering STOP mode
– Select the Low Frequency Auxiliary Oscillator
(provided this runs at a lower frequency than the
main oscillator).
The WAIT and STOP instructions are not execut-
ed if an enabled interrupt request is pending.
Normal Interrupt Mode. If the MCU was in inter-
rupt mode before the STOP or WAIT instruction
was executed, it exits from STOP or WAIT mode
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7 I/O PORTS
7.1 INTRODUCTION
Each I/O port contains up to 8 pins. Each pin can
be programmed independently as digital input
(with or without pull-up and interrupt generation),
digital output (open drain, push-pull) or analog in-
put (when available).
All input lines can be individually connected by
software to the interrupt system by programming
the OR and DR registers accordingly. The inter-
rupt trigger modes (falling edge, rising edge and
low level) can be configured by software for each
port as described in the Interrupt section.
The I/O pins can be used in either standard or al-
ternate function mode.
7.2.2 Analog Inputs
Standard I/O mode is used for:
Some pins can be configured as analog inputs by
programming the OR and DR registers according-
ly, see Table 8. These analog inputs are connect-
ed to the on-chip 8-bit Analog to Digital Converter.
– Transfer of data through digital inputs and out-
puts (on specific pins):
– External interrupt generation
Caution: ONLY ONE pin should be programmed
as an analog input at any time, since by selecting
more than one input simultaneously their pins will
be effectively shorted.
Alternate function mode is used for:
– Alternate signal input/output for the on-chip
peripherals
7.2.3 Output Modes
The generic I/O block diagram is shown in Figure
23.
The output configuration is selected by setting the
corresponding DDR register bit. In this case, writ-
ing to the DR register applies this digital value to
the I/O pin through the latch. Then, reading the DR
register returns the previously stored value.
7.2 FUNCTIONAL DESCRIPTION
Each port is associated with 3 registers located in
Data space:
Two different output modes can be selected by
software through the OR register: push-pull and
open-drain.
– Data Register (DR)
– Data Direction Register (DDR)
– Option Register (OR)
DR register value and output pin status:
Each I/O pin may be programmed using the corre-
sponding register bits in the DDR, DR and OR reg-
isters: bit x corresponding to pin x of the port. Table
8 illustrates the various port configurations which
can be selected by user software.
DR
0
Push-pull
Open-drain
V
V
V
SS
SS
DD
1
Floating
Note: The open drain setting is not a true open
drain. This means it has the same structure as the
push-pull setting but the P-buffer is deactivated.
To avoid damaging the device, please respect the
During MCU initialization, all I/O registers are
cleared and the input mode with pull-up and no in-
terrupt generation is selected for all the pins, thus
avoiding pin conflicts.
V
absolute maximum rating described in the
Electrical Characteristics section.
OUT
7.2.1 Digital Input Modes
7.2.4 Alternate Functions
The input configuration is selected by clearing the
corresponding DDR register bit.
When an on-chip peripheral is configured to use a
pin, the alternate function (timer input/output...) is
not systematically selected but has to be config-
ured through the DDR, OR and DR registers. Re-
fer to the chapter describing the peripheral for
more details.
In this case, reading the DR register returns the
digital value applied to the external I/O pin.
Different input modes can be selected by software
through the DR and OR registers, see Table 8.
External Interrupt Function
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ST6200C/ST6201C/ST6203C
I/O PORTS (Cont’d)
Figure 23. I/O Port Block Diagram
PULL-UP
RESET
V
DD
V
DD
DATA
DIRECTION
REGISTER
V
DD
Pxx I/O Pin
DATA
REGISTER
ST6
INTERNAL
BUS
N-BUFFER
OPTION
REGISTER
P-BUFFER
CLAMPING
DIODES
CMOS
SCHMITT
TRIGGER
TO INTERRUPT
*
TO ADC
* Depending on device. See device summary on page 1.
Table 8. I/O Port Configurations
DDR
OR
0
DR
0
Mode
Input
Option
0
0
0
0
1
1
With pull-up, no interrupt
No pull-up, no interrupt
0
1
Input
1
0
Input
With pull-up and with interrupt
Analog input (when available)
1
1
Input
0
x
Output
Output
Open-drain output (20mA sink when available)
Push-pull output (20mA sink when available)
1
x
Note: x = Don’t care
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I/O PORTS (Cont’d)
7.2.5 Instructions NOT to be used to access
Port Data registers (SET, RES, INC and DEC)
2. Handling Unused Port Bits
On ports that have less than 8 external pins con-
nected:
DO NOT USE READ-MODIFY-WRITE INSTRUC-
TIONS (SET, RES, INC and DEC) ON PORT
DATA REGISTERS IF ANY PIN OF THE PORT IS
CONFIGURED IN INPUT MODE.
– Leave the unbonded pins in reset state and do
not change their configuration.
– Do not use instructions that act on a whole port
register (INC, DEC, or read operations). Unavail-
able bits must be masked by software (AND in-
struction). Thus, when a read operation
performed on an incomplete port is followed by a
comparison, use a mask.
These instructions make an implicit read and write
back of the entire register. In port input mode,
however, the data register reads from the input
pins directly, and not from the data register latch-
es. Since data register information in input mode is
used to set the characteristics of the input pin (in-
terrupt, pull-up, analog input), these may be unin-
tentionally reprogrammed depending on the state
of the input pins.
3. High Impedance Input
On any CMOS device, it is not recommended to
connect high impedance on input pins. The choice
of these impedance has to be done with respect to
the maximum leakage current defined in the da-
tasheet. The risk is to be close or out of specifica-
tion on the input levels applied to the device.
As a general rule, it is better to only use single bit
instructions on data registers when the whole (8-
bit) port is in output mode. In the case of inputs or
of mixed inputs and outputs, it is advisable to keep
a copy of the data register in RAM. Single bit in-
structions may then be used on the RAM copy, af-
ter which the whole copy register can be written to
the port data register:
7.3 LOW POWER MODES
The WAIT and STOP instructions allow the
ST62xx to be used in situations where low power
consumption is needed. The lowest power con-
sumption is achieved by configuring I/Os in output
push-pull low mode.
SET bit, datacopy
LD a, datacopy
LD DRA, a
7.2.6 Recommendations
Mode
WAIT
STOP
Description
1. Safe I/O State Switching Sequence
No effect on I/O ports. External interrupts
cause the device to exit from WAIT mode.
Switching the I/O ports from one state to another
should be done in a sequence which ensures that
no unwanted side effects can occur. The recom-
mended safe transitions are illustrated in Figure 24
The Interrupt Pull-up to Input Analog transition
(and vice-vesra) is potentially risky and should be
avoided when changing the I/O operating mode.
No effect on I/O ports. External interrupts
cause the device to exit from STOP mode.
7.4 INTERRUPTS
The external interrupt event generates an interrupt
if the corresponding configuration is selected with
DDR, DR and OR registers (see Table 8) and the
GEN-bit in the IOR register is set.
Figure 24. Diagram showing Safe I/O State Transitions
Interrupt
pull-up
Input
Analog
010*
011
001
Input
pull-up (Reset
000
Input
state)
Output
Open Drain
Output
Open Drain
100
101
111
Output
110
Output
Push-pull
Push-pull
Note *. xxx = DDR, OR, DR Bits respectively
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ST6200C/ST6201C/ST6203C
I/O PORTS (Cont’d)
Table 9. I/O Port Option Selections
MODE
AVAILABLE ON(1)
SCHEMATIC
V
V
V
DD
V
DD
Input
PA1-PA3
PB0, PB1, PB3,
PB5-PB7
Data in
DDRx
0
ORx
0
DRx
1
Interrupt
Reset state
Input
DD
V
DD
PA1-PA3
with pull up
PB0, PB1, PB3,
PB5-PB7
Data in
DDRx
0
ORx
0
DRx
0
Interrupt
Input
DD
V
DD
with pull up
with interrupt
PA1-PA3
PB0, PB1, PB3,
PB5-PB7
Data in
DDRx
0
ORx
1
DRx
0
Interrupt
V
DD
Analog Input
PB3, PB5-PB7
(Except on
ADC
ST6203C)
DDRx
0
ORx
1
DRx
1
Open drain output (5mA) PB0, PB1, PB3,
PB5-PB7
V
DD
P-buffer disconnected
Data out
Open drain output (20 mA) PA1-PA3
DDRx
1
ORx
0
DRx
0/1
Push-pull output (5mA)
PB0, PB1, PB3,
PB5-PB7
V
DD
Data out
Push-pull output (20 mA)
PA1-PA3
DDRx
1
ORx
1
DRx
0/1
Note 1. Provided the correct configuration has been selected (see Table 8).
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ST6200C/ST6201C/ST6203C
I/O PORTS (Cont’d)
7.5 REGISTER DESCRIPTION
DATA REGISTER (DR)
Bit 7:0 = DD[7:0] Data direction register bits.
The DDR register gives the input/output direction
configuration of the pins. Each bit is set and
cleared by software.
Port x Data Register
DRx with x = A or B.
0: Input mode
1: Output mode
Address DRA: 0C0h - Read/Write
Address DRB: 0C1h - Read/Write
OPTION REGISTER (OR)
Reset Value: 0000 0000 (00h)
Port x Option Register
ORx with x = A or B.
7
0
Address ORA: 0CCh - Read/Write
Address ORB: 0CDh - Read/Write
D7
D6
D5
D4
D3
D2
D1
D0
Reset Value: 0000 0000 (00h)
Bit 7:0 = D[7:0] Data register bits.
7
0
Reading the DR register returns either the DR reg-
ister latch content (pin configured as output) or the
digital value applied to the I/O pin (pin configured
as input).
O7
O6
O5
O4
O3
O2
O1
O0
Bit 7:0 = O[7:0] Option register bits.
Caution: In input mode, modifying this register will
modify the I/O port configuration (see Table 8).
The OR register allows to distinguish in output
mode if the push-pull or open drain configuration is
selected.
Do not use the Single bit instructions on I/O port
data registers. See (Section 7.2.5).
Output mode:
0: Open drain output(with P-Buffer deactivated)
1: Push-pull Output
DATA DIRECTION REGISTER (DDR)
Port x Data Direction Register
DDRx with x = A or B.
Input mode: See Table 8.
Each bit is set and cleared by software.
Address DDRA: 0C4h - Read/Write
Address DDRB: 0C5h - Read/Write
Caution: Modifying this register, will also modify
the I/O port configuration in input mode. (see Ta-
ble 8).
Reset Value: 0000 0000 (00h)
7
0
DD7
DD6
DD5
DD4
DD3
DD2
DD1
DD0
Table 10. I/O Port Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
Reset Value
of all I/O port registers
0
0
0
0
0
0
0
0
0C0h
0C1h
0C4h
0C5h
0CCh
0CDh
DRA
MSB
MSB
MSB
LSB
DRB
DDRA
DDRB
ORA
ORB
LSB
LSB
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8 ON-CHIP PERIPHERALS
8.1 WATCHDOG TIMER (WDG)
8.1.1 Introduction
8.1.2 Main Features
■ Programmable timer (64 steps of 3072 clock
The Watchdog timer is used to detect the occur-
rence of a software fault, usually generated by ex-
ternal interference or by unforeseen logical condi-
tions, which causes the application program to
abandon its normal sequence. The Watchdog cir-
cuit generates an MCU reset on expiry of a pro-
grammed time period, unless the program refresh-
es the counter’s contents before the SR bit be-
comes cleared.
cycles)
■ Software reset
■ Reset (if watchdog activated) when the SR bit
reaches zero
■ Hardware or software watchdog activation
selectable by option bit (Refer to the option
bytes section)
Figure 25. Watchdog Block Diagram
RESET
WATCHDOG REGISTER (WDGR)
T0
T5
T1
SR
C
T4
T2
T3
bit 7
bit 0
7-BIT DOWNCOUNTER
CLOCK DIVIDER
f
int /12
÷ 256
41/100
1
ST6200C/ST6201C/ST6203C
WATCHDOG TIMER (Cont’d)
8.1.3 Functional Description
mode availability (refer to the description of the
WDACT and EXTCNTL bits on the Option Bytes).
The watchdog activation is selected through an
option in the option bytes:
When STOP mode is not required, hardware acti-
vation without EXTERNAL STOP MODE CON-
TROL should be preferred, as it provides maxi-
mum security, especially during power-on.
– HARDWARE Watchdog option
After reset, the watchdog is permanently active,
the C bit in the WDGR is forced high and the user
can not change it. However, this bit can be read
equally as 0 or 1.
When STOP mode is required, hardware activa-
tion and EXTERNAL STOP MODE CONTROL
should be chosen. NMI should be high by default,
to allow STOP mode to be entered when the MCU
is idle.
– SOFTWARE Watchdog option
After reset, the watchdog is deactivated. The func-
tion is activated by setting C bit in the WDGR reg-
ister. Once activated, it cannot be deactivated.
The counter value stored in the WDGR register
(bits SR:T0), is decremented every 3072 clock cy-
cles. The length of the timeout period can be pro-
grammed by the user in 64 steps of 3072 clock cy-
cles.
The NMI pin can be connected to an I/O line (see
Figure 26) to allow its state to be controlled by soft-
ware. The I/O line can then be used to keep NMI
low while Watchdog protection is required, or to
avoid noise or key bounce. When no more
processing is required, the I/O line is released and
the device placed in STOP mode for lowest power
consumption.
If the watchdog is activated (by setting the C bit)
and when the SR bit is cleared, the watchdog initi-
ates a reset cycle pulling the reset pin low for typi-
cally 500ns.
Figure 26. A typical circuit making use of the
EXERNAL STOP MODE CONTROL feature
The application program must write in the WDGR
register at regular intervals during normal opera-
tion to prevent an MCU reset. The value to be
stored in the WDGR register must be between
FEh and 02h (see Table 11). To run the watchdog
function the following conditions must be true:
SWITCH
NMI
– The C bit is set (watchdog activated)
I/O
– The SR bit is set to prevent generating an imme-
diate reset
– The T[5:0] bits contain the number of decre-
ments which represent the time delay before the
watchdog produces a reset.
VR02002
Table 11. Watchdog Timing (f
= 8 MHz)
OSC
2. When software activation is selected (WDACT
bit in Option byte) and the Watchdog is not activat-
ed, the downcounter may be used as a simple 7-
bit timer (remember that the bits are in reverse or-
der).
WDGR Register
initial value
WDG timeout period
(ms)
Max.
Min.
FEh
02h
24.576
0.384
8.1.3.1 Software Reset
The software activation option should be chosen
only when the Watchdog counter is to be used as
a timer. To ensure the Watchdog has not been un-
expectedly activated, the following instructions
should be executed:
The SR bit can be used to generate a software re-
set by clearing the SR bit while the C bit is set.
8.1.4 Recommendations
jrr 0, WDGR, #+3; If C=0,jump to next
1. The Watchdog plays an important supporting
role in the high noise immunity of ST62xx devices,
and should be used wherever possible. Watchdog
related options should be selected on the basis of
a trade-off between application security and STOP
ldi WDGR, 0FDH
; SR=0 -> reset
next :
42/100
1
ST6200C/ST6201C/ST6203C
WATCHDOG TIMER (Cont’d)
These instructions test the C bit and reset the
MCU (i.e. disable the Watchdog) if the bit is set
(i.e. if the Watchdog is active), thus disabling the
Watchdog.
Note: This note applies only when the watchdog is
used as a standard timer. It is recommended to
read the counter twice, as it may sometimes return
an invalid value if the read is performed while the
counter is decremented (counter bits in transient
state). To validate the return value, both values
read must be equal. The counter decrements eve-
For more information on the use of the watchdog,
please read application note AN1015.
ry 384 µs at 8 MHz fOSC
.
8.1.5 Low Power Modes
Mode Description
WAIT No effect on Watchdog.
Behaviour depends on the EXTCNTL option in the Option bytes:
STOP
1. Watchdog disabled:
The MCU will enter Stop mode if a STOP instruction is executed.
2. Watchdog enabled and EXTCNTL option disabled:
If a STOP instruction is encountered, it is interpreted as a WAIT.
3. Watchdog and EXTCNTL option enabled:
If a STOP instruction is encountered when the NMI pin is low, it is interpreted as a WAIT. If, however, the
STOP instruction is encountered when the NMI pin is high, the Watchdog counter is frozen and the CPU en-
ters STOP mode.
When the MCU exits STOP mode (i.e. when an interrupt is generated), the Watchdog resumes its activity.
8.1.6 Interrupts
None.
43/100
1
ST6200C/ST6201C/ST6203C
WATCHDOG TIMER (Cont’d)
8.1.7 Register Description
WATCHDOG REGISTER (WDGR)
Address: 0D8h - Read/Write
Reset Value: 1111 1110 (FEh)
Bit 0 = C Watchdog Control bit.
If the hardware option is selected (WDACT bit in
Option byte), this bit is forced high and cannot be
changed by the user (the Watchdog is always ac-
tive). When the software option is selected
(WDACT bit in Option byte), the Watchdog func-
tion is activated by setting the C bit, and cannot
then be deactivated (except by resetting the
MCU).
7
0
T0
T1
T2
T3
T4
T5
SR
C
When C is kept cleared the counter can be used
as a 7-bit timer.
0: Watchdog deactivated
Bits 7:2 = T[5:0] Downcounter bits
Caution: These bits are reversed and shifted with
respect to the physical counter: bit-7 (T0) is the
LSB of the Watchdog downcounter and bit-2 (T5)
is the MSB.
1: Watchdog activated
Bit 1 = SR: Software Reset bit
Software can generate a reset by clearing this bit
while the C bit is set. When C = 0 (Watchdog de-
activated) the SR bit is the MSB of the 7-bit timer.
0: Generate (write)
1: No software reset generated, MSB of 7-bit timer
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1
ST6200C/ST6201C/ST6203C
8.2 8-BIT TIMER
8.2.1 Introduction
8.2.2 Main Features
■ Time-out downcounting mode with up to 15-bit
The 8-Bit Timer on-chip peripheral is a free run-
ning downcounter based on an 8-bit downcounter
with a 7-bit programmable prescaler, giving a max-
accuracy
■ Interrupt capability on counter underflow
15
imum count of 2 .
The timer can be used in WAIT mode to wake up
the MCU.
Figure 27. Timer Block Diagram
7
0
8-BIT DOWN COUNTER
f
COUNTER
TCR
REGISTER
TCR7 TCR6 TCR5 TCR4 TCR3 TCR2 TCR1 TCR0
7
0
TSCR
REGISTER
TMZ
ETI TSCR5 TSCR4 PSI
PS2
PS1
PS0
f
INT/12
INTERRUPT
f
PRESCALER
PSCR REGISTER
PSCR7 PSCR6 PSCR5 PSCR4 PSCR3 PSCR2 PSCR1 PSCR0
/128 /64 /32 /16 /8 /4 /2
7
0
/1
PROGRAMMABLE PRESCALER
45/100
1
ST6200C/ST6201C/ST6203C
8-BIT TIMER (Cont’d)
8.2.3 Counter/Prescaler Description
prescaler is also possible when PSI =1. Then, any
value between 0 and 7Fh can be loaded into it.
Prescaler
The 8-bit counter can be initialized separately by
writing to the TCR register.
The prescaler input is the internal frequency f
INT
divided by 12. The prescaler decrements on the
rising edge, depending on the division factor pro-
grammed by the PS[2:0] bits in the TSCR register.
8.2.3.1 8-bit Counting and Interrupt Capability
on Counter Underflow
Whatever the division factor defined for the pres-
caler, the Timer Counter works as an 8-bit down-
counter. The input clock frequency is user selecta-
ble using the PS[2:0] bits.
The state of the 7-bit prescaler can be read in the
PSCR register.
When the prescaler reaches 0, it is automatically
reloaded with 7Fh.
When the downcounter decrements to zero, the
TMZ (Timer Zero) bit in the TSCR is set. If the ETI
(Enable Timer Interrupt) bit in the TSCR is also
set, an interrupt request is generated.
Counter
The free running 8-bit downcounter is fed by the
output of the programmable prescaler, and is dec-
The Timer interrupt can be used to exit the MCU
from WAIT or STOP mode.
remented on every rising edge of the f
clock signal coming from the prescaler.
COUNTER
The TCR can be written at any time by software to
define a time period ending with an underflow
event, and therefore manage delay or timer func-
tions.
It is possible to read or write the contents of the
counter on the fly, by reading or writing the timer
counter register (TCR).
When the downcounter reaches 0, it is automati-
cally reloaded with the value 0FFh.
TMZ is set when the downcounter reaches zero;
however, it may also be set by writing 00h in the
TCRregisterorbysetting bit7oftheTSCR register.
Counter Clock and Prescaler
The counter clock frequency is given by:
The TMZ bit must be cleared by user software
when servicing the timer interrupt to avoid unde-
sired interrupts when leaving the interrupt service
routine.
PS[2:0]
f
= f / 2
PRESCALER
COUNTER
where f
is:
PRESCALER
– f /12
INT
Note: A write to the TCR register will predominate
over the 8-bit counter decrement to 00h function,
i.e. if a write and a TCR register decrement to 00h
occur simultaneously, the write will take prece-
dence, and the TMZ bit is not set until the 8-bit
counter underflows again.
The timer input clock feeds the 7-bit programma-
ble prescaler. The prescaler output can be pro-
grammed by selecting one of the 8 available pres-
caler taps using the PS[2:0] bits in the Status/Con-
trol Register (TSCR). Thus the division factor of
n
the prescaler can be set to 2 (where n equals 0, to
8.2.4 Low Power Modes
7). See Figure 27.
Mode
WAIT
STOP
Description
No effect on timer.
Timer interrupt events cause the device to
The clock input is enabled by the PSI (Prescaler
Initialize) bit in the TSCR register. When PSI is re-
set, the counter is frozen and the prescaler is load-
ed with the value 7Fh. When PSI is set, the pres-
caler and the counter run at the rate of the select-
ed clock source.
exit from WAIT mode.
Timer registers are frozen.
8.2.5 Interrupts
Interrupt Event
Counter and Prescaler Initialization
After RESET, the counter and the prescaler are in-
itialized to 0FFh and 7Fh respectively.
Exit
from
Wait
Exit
from
Stop
Event Enable
Flag
Bit
The 7-bit prescaler can be initialized to 7Fh by
clearing the PSI bit. Direct write access to the
Timer Zero
Event
TMZ
ETI
Yes
No
46/100
1
ST6200C/ST6201C/ST6203C
8-BIT TIMER (Cont’d)
8.2.6 Register Description
Bit 6 = ETI Enable Timer Interrupt.
PRESCALER COUNTER REGISTER (PSCR)
Address: 0D2h - Read/Write
Reset Value: 0111 1111 (7Fh)
When set, enables the timer interrupt request. If
ETI=0 the timer interrupt is disabled. If ETI=1 and
TMZ=1 an interrupt request is generated.
0: Interrupt disabled (reset state)
7
0
1: Interrupt enabled
PSCR PSCR PSCR PSCR PSCR PSCR PSCR PSCR
0
7
6
5
4
3
2
1
Bit 5 = TSCR5 Reserved, must be set.
Bit 7 = PSCR7: Not used, always read as “0”.
Bits 6:0 = PSCR[6:0] Prescaler LSB.
Bit 4 = TSCR4 Reserved, must be cleared.
Bit 3 = PSI: Prescaler Initialize bit.
Used to initialize the prescaler and inhibit its count-
ing. When PSI=“0” the prescaler is set to 7Fh and
the counter is inhibited. When PSI=“1” the prescal-
er is enabled to count downwards. As long as
PSE=“1” both counter and prescaler are not run-
ning
TIMER COUNTER REGISTER (TCR)
Address: 0D3h - Read / Write
Reset Value: 1111 1111 (FFh)
7
0
TCR7 TCR6 TCR5 TCR4 TCR3 TCR2 TCR1 TCR0
0: Counting disabled
1: Counting enabled
Bits 7:0 = TCR[7:0] Timer counter bits.
Bits 1:0 = PS[2:0] Prescaler Mux. Select.
These bits select the division ratio of the prescaler
register.
TIMER STATUS CONTROL REGISTER (TSCR)
Address: 0D4h - Read/Write
Reset Value: 0000 0000 (00h)
Table 12. Prescaler Division Factors
7
0
PS2
0
0
PS1
0
0
PS0
0
1
Divided by
1
2
TMZ
ETI TSCR5 TSCR4 PSI
PS2
PS1
PS0
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
4
8
16
32
64
128
Bit 7 = TMZ Timer Zero bit.
A low-to-high transition indicates that the timer
count register has underflowed. It means that the
TCR value has changed from 00h to FFh.
This bit must be cleared by user software.
0: Counter has not underflowed
1: Counter underflow occurred
Table 13. 8-Bit Timer Register Map and Reset Values
Address
Register Label
7
6
5
4
3
2
1
0
(Hex.)
PSCR
Reset Value
PSCR7 PSCR6 PSCR5 PSCR4 PSCR3 PSCR2 PSCR1 PSCR0
0D2h
0
1
1
1
1
1
1
1
TCR
Reset Value
TSCR
Reset Value
TCR7
1
TMZ
0
TCR6
1
ETI
0
TCR5
1
TSCR5 TSCR4
TCR4
1
TCR3
1
PSI
0
TCR2
1
PS2
0
TCR1
1
PS1
0
TCR0
1
PS0
0
0D3h
0D4h
0
0
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ST6200C/ST6201C/ST6203C
8.3 A/D CONVERTER (ADC)
8.3.1 Introduction
8.3.2 Main Features
■ 8-bit conversion
The on-chip Analog to Digital Converter (ADC) pe-
ripheral is a 8-bit, successive approximation con-
verter. This peripheral has multiplexed analog in-
put channels (refer to device pin out description)
that allow the peripheral to convert the analog volt-
age levels from different sources.
■ Multiplexed analog input channels
■ Linear successive approximation
■ Data register (DR) which contains the results
■ End of Conversion flag
■ On/Off bit (to reduce consumption)
The result of the conversion is stored in a 8-bit
Data Register. The A/D converter is controlled
through a Control Register.
■ Typical conversion time 70 µs (with an 8 MHz
crystal)
The block diagram is shown in Figure 28.
Figure 28. ADC Block Diagram
f
f
ADC
INT
DIV 12
AD
CR0
AD
CR3
AD
CR1
OSC
OFF
EAI EOC STA PDS
ADCR
I/O PORT
AIN0
AIN1
ANALOG TO DIGITAL
CONVERTER
PORT
MUX
AINx
DDRx
ORx
ADR
ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0
DRx
Note: ADC not present on some devices. See device summary on page 1.
48/100
1
ST6200C/ST6201C/ST6203C
A/D CONVERTER (Cont’d)
8.3.3 Functional Description
8.3.3.4 Software Procedure
8.3.3.1 Analog Power Supply
Refer to the Control register (ADCR) and Data reg-
ister (ADR) in Section 8.3.7 for the bit definitions.
The high and low level reference voltage pins are
internally connected to the V
and V pins.
Analog Input Configuration
DD
SS
Conversion accuracy may therefore be impacted
by voltage drops and noise in the event of heavily
loaded or badly decoupled power supply lines.
The analog input must be configured through the
Port Control registers (DDRx, ORx and DRx). Re-
fer to the I/O port chapter.
8.3.3.2 Digital A/D Conversion Result
ADC Configuration
The conversion is monotonic, meaning that the re-
sult never decreases if the analog input does not
and never increases if the analog input does not.
In the ADCR register:
– Reset the PDS bit to power on the ADC. This bit
must be set at least one instruction before the
beginning of the conversion to allow stabilisation
of the A/D converter.
If the input voltage (V ) is greater than or equal
AIN
to V
(high-level voltage reference) then the
DDA
conversion result in the DR register is FFh (full
– Set the EAI bit to enable the ADC interrupt if
needed.
scale) without overflow indication.
If input voltage (V ) is lower than or equal to
AIN
ADC Conversion
V
(low-level voltage reference) then the con-
version result in the DR register is 00h.
SSA
In the ADCR register:
– Set the STA bit to start a conversion. This auto-
matically clears (resets to “0”) the End Of Con-
version Bit (EOC).
The A/D converter is linear and the digital result of
the conversion is stored in the ADR register. The
accuracy of the conversion is described in the par-
ametric section.
When a conversion is complete
R
is the maximum recommended impedance
– The EOC bit is set by hardware to flag that con-
version is complete and that the data in the ADC
data conversion register is valid.
AIN
for an analog input signal. If the impedance is too
high, this will result in a loss of accuracy due to
leakage and sampling not being completed in the
allocated time. Refer to the electrical characteris-
tics chapter for more details.
– An interrupt is generated if the EAI bit was set
Setting the STA bit will start a new count and will
clear the EOC bit (thus clearing the interrupt con-
dition)
With an oscillator clock frequency less than
1.2MHz, conversion accuracy is decreased.
Note:
8.3.3.3 Analog Input Selection
Setting the STA bit must be done by a different in-
struction from the instruction that powers-on the
ADC (setting the PDS bit) in order to make sure
the voltage to be converted is present on the pin.
Selection of the input pin is done by configuring
the related I/O line as an analog input via the Data
Direction, Option and Data registers (refer to I/O
ports description for additional information).
Each conversion has to be separately initiated by
writing to the STA bit.
Caution: Only one I/O line must be configured as
an analog input at any time. The user must avoid
any situation in which more than one I/O pin is se-
lected as an analog input simultaneously, because
they will be shorted internally.
The STA bit is continuously scanned so that, if the
user sets it to “1” while a previous conversion is in
progress, a new conversion is started before com-
pleting the previous one. The start bit (STA) is a
write only bit, any attempt to read it will show a log-
ical “0”.
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ST6200C/ST6201C/ST6203C
A/D CONVERTER (Cont’d)
8.3.4 Recommendations
bances and power supply variations due to output
switching. Nevertheless, the WAIT instruction
should be executed as soon as possible after the
beginning of the conversion, because execution of
the WAIT instruction may cause a small variation
The following six notes provide additional informa-
tion on using the A/D converter.
1.The A/D converter does not feature a sample
and hold circuit. The analog voltage to be meas-
ured should therefore be stable during the entire
conversion cycle. Voltage variation should not ex-
ceed ±1/2 LSB for optimum conversion accuracy.
A low pass filter may be used at the analog input
pins to reduce input voltage variation during con-
version.
of the V voltage. The negative effect of this var-
DD
iation is minimized at the beginning of the conver-
sion when the converter is less sensitive, rather
than at the end of conversion, when the least sig-
nificant bits are determined.
The best configuration, from an accuracy stand-
point, is WAIT mode with the Timer stopped. In
this case only the ADC peripheral and the oscilla-
tor are then still working. The MCU must be woken
up from WAIT mode by the ADC interrupt at the
end of the conversion. The microcontroller can
also be woken up by the Timer interrupt, but this
means the Timer must be running and the result-
ing noise could affect conversion accuracy.
2. When selected as an analog channel, the input
pin is internally connected to a capacitor C of
ad
typically 9pF. For maximum accuracy, this capaci-
tor must be fully charged at the beginning of con-
version. In the worst case, conversion starts one
instruction (6.5 µs) after the channel has been se-
lected. The impedance of the analog voltage
source (ASI) in worst case conditions, is calculat-
ed using the following formula:
Caution: When an I/O pin is used as an analog in-
put, A/D conversion accuracy will be impaired if
6.5µs = 9 x C x ASI
ad
(capacitor charged to over 99.9%), i.e. 30 kΩ in-
negative current injections (V < V ) occur from
INJ
SS
cluding a 50% guardband.
The ASI can be higher if C has been charged for
a longer period by adding instructions before the
start of conversion (adding more than 26 CPU cy-
cles is pointless).
adjacent I/O pins with analog input capability. Re-
fer to Figure 29. To avoid this:
ad
– Use another I/O port located further away from
the analog pin, preferably not multiplexed on the
A/D converter
3. Since the ADC is on the same chip as the micro-
processor, the user should not switch heavily load-
ed output signals during conversion, if high preci-
sion is required. Such switching will affect the sup-
ply voltages used as analog references.
– Increase the input resistance R
current injections) and reduce R
conversion accuracy).
(to reduce the
IN J
(to preserve
ADC
Figure 29. Leakage from Digital Inputs
4. Conversion accuracy depends on the quality of
the power supplies (V
and V ). The user must
DD
SS
take special care to ensure a well regulated refer-
ence voltage is present on the V and V pins
DD
SS
(power supply voltage variations must be less than
0.1V/ms). This implies, in particular, that a suitable
Digital
Input
decoupling capacitor is used at the V
pin.
DD
The converter resolution is given by:
PBy/AINy
R
I/O Port
INJ
(Digital I/O)
V
– V
DD
-------------------------------
256
SS
V
INJ
Leakage Current
if V < V
INJ
SS
The Input voltage (Ain) which is to be converted
must be constant for 1µs before conversion and
remain constant during conversion.
Analog
Input
PBx/AINx
R
5. Conversion resolution can be improved if the
ADC
A/D
Converter
power supply voltage (V ) to the microcontroller
DD
is lowered.
V
AIN
6. In order to optimize the conversion resolution,
the user can configure the microcontroller in WAIT
mode, because this mode minimises noise distur-
50/100
1
ST6200C/ST6201C/ST6203C
A/D CONVERTER (Cont’d)
8.3.5 Low Power Modes
cally cleared when the STA bit is set. Data in the
data conversion register are valid only when this
bit is set to “1”.
Mode
Description
0: Conversion is not complete
1: Conversion can be read from the ADR register
No effect on A/D Converter. ADC interrupts
cause the device to exit from Wait mode.
WAIT
STOP
A/D Converter disabled.
Bit 5 = STA: Start of Conversion. Write Only.
0: No effect
1: Start conversion
Note: The A/D converter may be disabled by clear-
ing the PDS bit. This feature allows reduced power
consumption when no conversion is needed.
Note: Setting this bit automatically clears the EOC
bit. If the bit is set again when a conversion is in
progress, the present conversion is stopped and a
new one will take place. This bit is write only, any
attempt to read it will show a logical zero.
8.3.6 Interrupts
Exit
from
Wait
Exit
from
Stop
Event Enable
Interrupt Event
Flag
Bit
Bit 4 = PDS Power Down Selection.
End of Conver-
sion
EOC
EAI
Yes
No
0: A/D converter is switched off
1: A/D converter is switched on
Note: The EOC bit is cleared only when a new
conversion is started (it cannot be cleared by writ-
ing 0). To avoid generating further EOC interrupt,
the EAI bit has to be cleared within the ADC inter-
rupt subroutine.
Bit 3 = ADCR3 Reserved, must be cleared.
Bit 2 = OSCOFF Main Oscillator off.
8.3.7 Register Description
0: Main Oscillator enabled
1: Main Oscillator disabled
A/D CONVERTER CONTROL REGISTER (AD-
CR)
Note: This bit does not apply to the ADC peripher-
al but to the main clock system. Refer to the Clock
System section.
Address: 0D1h - Read/Write (Bit 6 Read Only, Bit
5 Write Only)
Reset value: 0100 0000 (40h)
7
0
Bits 1:0 = ADCR[1:0] Reserved, must be cleared.
ADCR OSC ADCR ADCR
EAI
EOC
STA
PDS
3
OFF
1
0
A/D CONVERTER DATA REGISTER (ADR)
Address: 0D0h - Read only
Bit 7 = EAI Enable A/D Interrupt.
0: ADC interrupt disabled
1: ADC interrupt enabled
Reset value: xxxx xxxx (xxh)
7
0
Bit 6 = EOC End of conversion. Read Only
ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0
When a conversion has been completed, this bit is
set by hardware and an interrupt request is gener-
ated if the EAI bit is set. The EOC bit is automati-
Bits 7:0 = ADR[7:0]: 8 Bit A/D Conversion Result.
Table 14. ADC Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
ADR
Reset Value
ADR7
0
ADR6
0
ADR5
0
ADR4
0
ADR3
0
ADR2
0
ADR1
0
ADR0
0
0D0h
0D1h
ADCR
Reset Value
EAI
0
EOC
1
STA
0
PDS
0
ADCR3 OSCOFF ADCR1
ADCR0
0
0
0
0
51/100
1
ST6200C/ST6201C/ST6203C
9 INSTRUCTION SET
9.1 ST6 ARCHITECTURE
The ST6 architecture has been designed for max-
imum efficiency while keeping byte usage to a
minimum; in short, to provide byte-efficient pro-
gramming. The ST6 core has the ability to set or
clear any register or RAM location bit in Data
space using a single instruction. Furthermore, pro-
grams can branch to a selected address depend-
ing on the status of any bit in Data space.
tended addressing mode are able to branch to any
address in the 4 Kbyte Program space.
Extended addressing mode instructions are two
bytes long.
Program Counter Relative. Relative addressing
mode is only used in conditional branch instruc-
tions. The instruction is used to perform a test and,
if the condition is true, a branch with a span of -15
to +16 locations next to the address of the relative
instruction. If the condition is not true, the instruc-
tion which follows the relative instruction is execut-
ed. Relative addressing mode instructions are one
byte long. The opcode is obtained by adding the
three most significant bits which characterize the
test condition, one bit which determines whether it
is a forward branch (when it is 0) or backward
branch (when it is 1) and the four least significant
bits which give the span of the branch (0h to Fh)
which must be added or subtracted from the ad-
dress of the relative instruction to obtain the
branch destination address.
9.2 ADDRESSING MODES
The ST6 has nine addressing modes, which are
described in the following paragraphs. Three dif-
ferent address spaces are available: Program
space, Data space, and Stack space. Program
space contains the instructions which are to be ex-
ecuted, plus the data for immediate mode instruc-
tions. Data space contains the Accumulator, the X,
Y, V and W registers, peripheral and Input/Output
registers, the RAM locations and Data ROM loca-
tions (for storage of tables and constants). Stack
space contains six 12-bit RAM cells used to stack
the return addresses for subroutines and inter-
rupts.
Bit Direct. In bit direct addressing mode, the bit to
be set or cleared is part of the opcode, and the
byte following the opcode points to the address of
the byte in which the specified bit must be set or
cleared. Thus, any bit in the 256 locations of Data
space memory can be set or cleared.
Immediate. In immediate addressing mode, the
operand of the instruction follows the opcode loca-
tion. As the operand is a ROM byte, the immediate
addressing mode is used to access constants
which do not change during program execution
(e.g., a constant used to initialize a loop counter).
Bit Test & Branch. Bit test and branch addressing
mode is a combination of direct addressing and
relative addressing. Bit test and branch instruc-
tions are three bytes long. The bit identification
and the test condition are included in the opcode
byte. The address of the byte to be tested is given
in the next byte. The third byte is the jump dis-
placement, which is in the range of -127 to +128.
This displacement can be determined using a la-
bel, which is converted by the assembler.
Direct. In direct addressing mode, the address of
the byte which is processed by the instruction is
stored in the location which follows the opcode. Di-
rect addressing allows the user to directly address
the 256 bytes in Data Space memory with a single
two-byte instruction.
Short Direct. The core can address the four RAM
registers X, Y, V, W (locations 80h, 81h, 82h, 83h)
in short-direct addressing mode. In this case, the
instruction is only one byte and the selection of the
location to be processed is contained in the op-
code. Short direct addressing is a subset of direct
addressing mode. (Note that 80h and 81h are also
indirect registers).
Indirect. In indirect addressing mode, the byte
processed by the register-indirect instruction is at
the address pointed to by the content of one of the
indirect registers, X or Y (80h, 81h). The indirect
register is selected by bit 4 of the opcode. Register
indirect instructions are one byte long.
Extended. In extended addressing mode, the 12-
bit address needed to define the instruction is ob-
tained by concatenating the four least significant
bits of the opcode with the byte following the op-
code. The instructions (JP, CALL) which use ex-
Inherent. In inherent addressing mode, all the in-
formation necessary for executing the instruction
is contained in the opcode. These instructions are
one byte long.
52/100
1
ST6200C/ST6201C/ST6203C
9.3 INSTRUCTION SET
The ST6 offers a set of 40 basic instructions
which, when combined with nine addressing
modes, yield 244 usable opcodes. They can be di-
vided into six different types: load/store, arithme-
tic/logic, conditional branch, control instructions,
jump/call, and bit manipulation. The following par-
agraphs describe the different types.
Load & Store. These instructions use one, two or
three bytes depending on the addressing mode.
For LOAD, one operand is the Accumulator and
the other operand is obtained from data memory
using one of the addressing modes.
For Load Immediate, one operand can be any of
the 256 data space bytes while the other is always
immediate data.
All the instructions belonging to a given type are
presented in individual tables.
Table 15. Load & Store Instructions
Flags
Instruction
LD A, X
Addressing Mode
Short Direct
Bytes
Cycles
Z
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
*
C
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
1
1
1
1
1
1
1
1
2
2
1
1
1
1
2
3
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
LD A, Y
LD A, V
LD A, W
LD X, A
LD Y, A
Short Direct
Short Direct
Short Direct
Short Direct
Short Direct
Short Direct
Short Direct
Direct
LD V, A
LD W, A
LD A, rr
LD rr, A
Direct
LD A, (X)
LD A, (Y)
LD (X), A
LD (Y), A
LDI A, #N
LDI rr, #N
Indirect
Indirect
Indirect
Indirect
Immediate
Immediate
Legend:
X, Y Index Registers,
V, W Short Direct Registers
#
rr
∆
*
Immediate data (stored in ROM memory)
Data space register
Affected
Not Affected
53/100
1
ST6200C/ST6201C/ST6203C
INSTRUCTION SET (Cont’d)
Arithmetic and Logic. These instructions are
used to perform arithmetic calculations and logic
operations. In AND, ADD, CP, SUB instructions
one operand is always the accumulator while, de-
pending on the addressing mode, the other can be
either a data space memory location or an imme-
diate value. In CLR, DEC, INC instructions the op-
erand can be any of the 256 data space address-
es. In COM, RLC, SLA the operand is always the
accumulator.
Table 16. Arithmetic & Logic Instructions
Flags
Instruction
ADD A, (X)
Addressing Mode
Indirect
Bytes
Cycles
Z
∆
∆
∆
∆
∆
∆
∆
∆
∆
*
C
∆
∆
∆
∆
∆
∆
∆
∆
∆
*
1
1
2
2
1
1
2
2
2
3
1
1
1
2
2
1
1
1
1
2
2
1
1
1
1
1
1
2
2
1
1
1
2
1
1
2
2
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
ADD A, (Y)
ADD A, rr
ADDI A, #N
AND A, (X)
AND A, (Y)
AND A, rr
ANDI A, #N
CLR A
Indirect
Direct
Immediate
Indirect
Indirect
Direct
Immediate
Short Direct
Direct
CLR r
COM A
Inherent
Indirect
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
*
CP A, (X)
CP A, (Y)
CP A, rr
CPI A, #N
DEC X
Indirect
Direct
Immediate
Short Direct
Short Direct
Short Direct
Short Direct
Direct
DEC Y
*
DEC V
*
DEC W
*
DEC A
*
DEC rr
Direct
*
DEC (X)
DEC (Y)
INC X
Indirect
*
Indirect
*
Short Direct
Short Direct
Short Direct
Short Direct
Direct
*
INC Y
*
INC V
*
INC W
*
INC A
*
INC rr
Direct
*
INC (X)
Indirect
*
INC (Y)
Indirect
*
RLC A
Inherent
Inherent
Indirect
∆
∆
∆
∆
∆
∆
SLA A
SUB A, (X)
SUB A, (Y)
SUB A, rr
SUBI A, #N
Indirect
Direct
Immediate
Notes:
X,Y Index Registers
V, W Short Direct Registers
#
*
Immediate data (stored in ROM memory)
Not Affected
∆
Affected
rr Data space register
54/100
1
ST6200C/ST6201C/ST6203C
INSTRUCTION SET (Cont’d)
Conditional Branch. Branch instructions perform
a branch in the program when the selected condi-
tion is met.
Control Instructions. Control instructions control
microcontroller operations during program execu-
tion.
Bit Manipulation Instructions. These instruc-
tions can handle any bit in Data space memory.
One group either sets or clears. The other group
(see Conditional Branch) performs the bit test
branch operations.
Jump and Call. These two instructions are used
to perform long (12-bit) jumps or subroutine calls
to any location in the whole program space.
Table 17. Conditional Branch Instructions
Flags
Instruction
Branch If
Bytes
Cycles
Z
*
*
*
*
*
*
C
*
JRC e
C = 1
1
1
1
1
3
3
2
2
2
2
5
5
JRNC e
C = 0
Z = 1
*
JRZ e
*
JRNZ e
Z = 0
*
JRR b, rr, ee
JRS b, rr, ee
Bit = 0
Bit = 1
∆
∆
Notes:
b
e
3-bit address
rr
∆
*
Data space register
Affected. The tested bit is shifted into carry.
Not Affected
5 bit signed displacement in the range -15 to +16
ee 8 bit signed displacement in the range -126 to +129
Table 18. Bit Manipulation Instructions
Flags
Instruction
Addressing Mode
Bytes
Cycles
Z
C
*
SET b,rr
Bit Direct
Bit Direct
2
2
4
4
*
*
RES b,rr
*
Notes:
b
3-bit address
Data space register
*
Not Affected
rr
Bit Manipulation Instructions should not be used on Port Data Registers and any registers with read only and/or write only bits (see I/O port
chapter)
Table 19. Control Instructions
Flags
Instruction
Addressing Mode
Bytes
Cycles
Z
*
C
*
NOP
Inherent
Inherent
Inherent
Inherent
Inherent
1
1
1
1
1
2
2
2
2
2
RET
*
*
RETI
STOP
WAIT
∆
*
∆
*
(1)
*
*
Notes:
1.
This instruction is deactivated and a WAIT is automatically executed instead of a STOP if the watchdog function is selected.
∆
Affected
*Not Affected
Table 20. Jump & Call Instructions
Flags
Instruction
Addressing Mode
Bytes
Cycles
Z
*
C
*
CALL abc
Extended
Extended
2
2
4
4
JP abc
*
*
Notes:
abc 12-bit address
*
Not Affected
55/100
1
ST6200C/ST6201C/ST6203C
Opcode Map Summary. The following table contains an opcode map for the instructions used by the ST6
LOW
LOW
0
1
2
3
4
5
6
7
0000
0001
0010
0011
0100
0101
0110
0111
HI
HI
2
JRNZ 4
CALL 2
abc
ext 1
CALL 2
abc
ext 1
CALL 2
abc
ext 1
CALL 2
abc
ext 1
CALL 2
abc
ext 1
CALL 2
abc
ext 1
CALL 2
abc
ext 1
CALL 2
abc
ext 1
CALL 2
abc
ext 1
CALL 2
abc
ext 1
CALL 2
abc
ext 1
CALL 2
abc
ext 1
CALL 2
abc
ext 1
CALL 2
abc
ext 1
CALL 2
abc
ext 1
CALL 2
abc
JRNC
5
JRR 2
b0,rr,ee
bt 1
JRS 2
b0,rr,ee
bt 1
JRR 2
b4,rr,ee
JRZ
e NOP
pcr
2
JRC 4
LD
0
0
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
#
x
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
a,(x)
a,nn
0000
0000
1
2
pcr 2
JRNZ 4
pcr 3
JRNC
1
prc 1
JRC 4
ind
LDI
5
JRZ 4
INC 2
1
1
e
e
0001
0001
1
2
pcr 2
JRNZ 4
pcr 3
JRNC
pcr 1
JRZ
sd
1
2
prc 2
JRC 4
imm
CP
5
2
2
#
a,(x)
0010
0010
1
2
pcr 2
JRNZ 4
pcr 3
JRNC
bt 1
JRS 2
pcr
JRZ 4
1
2
prc 1
JRC 4
ind
CPI
5
LD
sd
3
3
b4,rr,ee
e
bt 1
a,x
#
a,nn
0011
0011
1
2
pcr 2
JRNZ 4
pcr 3
JRNC
pcr 1
JRZ
1
2
prc 2
JRC 4
imm
ADD
a,(x)
5
JRR 2
b2,rr,ee
bt 1
JRS 2
b2,rr,ee
bt 1
JRR 2
b6,rr,ee
bt 1
JRS 2
b6,rr,ee
bt 1
JRR 2
b1,rr,ee
bt 1
JRS 2
b1,rr,ee
bt 1
JRR 2
b5,rr,ee
bt 1
JRS 2
b5,rr,ee
bt 1
JRR 2
b3,rr,ee
bt 1
JRS 2
b3,rr,ee
bt 1
JRR 2
b7,rr,ee
bt 1
JRS 2
b7,rr,ee
4
4
e
e
e
e
e
e
e
e
e
e
e
e
0100
0100
1
2
pcr 2
JRNZ 4
pcr 3
JRNC
pcr
JRZ 4
1
prc 1
JRC 4
ind
ADDI
5
INC 2
5
5
y
a,nn
0101
0101
1
2
pcr 2
JRNZ 4
pcr 3
JRNC
pcr 1
JRZ
sd
1
2
prc 2
JRC 4
imm
INC
5
6
6
#
(x)
#
0110
0110
1
2
pcr 2
JRNZ 4
pcr 3
JRNC
pcr
JRZ 4
1
2
prc 1
JRC
ind
5
LD
sd
7
7
a,y
#
0111
0111
1
2
pcr 2
JRNZ 4
pcr 3
JRNC
pcr 1
JRZ
1
2
prc
JRC 4
5
LD
ind
8
8
(x),a
#
1000
1000
1
2
pcr 2
JRNZ 4
pcr 3
JRNC
pcr
JRZ 4
1
prc 1
JRC
5
INC 2
9
9
v
1001
1001
1
2
pcr 2
JRNZ 4
pcr 3
JRNC
pcr 1
JRZ
sd
1
2
prc
JRC 4
5
AND
a,(x)
A
1010
A
1010
#
1
2
pcr 2
JRNZ 4
pcr 3
JRNC
pcr
JRZ 4
1
2
prc 1
JRC 4
ind
ANDI
5
LD
sd
B
1011
B
1011
a,v
#
a,nn
1
2
pcr 2
JRNZ 4
pcr 3
JRNC
pcr 1
JRZ
1
2
prc 2
JRC 4
imm
SUB
5
C
1100
C
1100
a,(x)
1
2
pcr 2
JRNZ 4
pcr 3
JRNC
pcr
JRZ 4
1
prc 1
JRC 4
ind
SUBI
5
INC 2
D
1101
D
1101
w
a,nn
1
2
pcr 2
JRNZ 4
pcr 3
JRNC
pcr 1
JRZ
sd
1
2
prc 2
JRC 4
imm
DEC
5
E
1110
E
1110
#
(x)
#
1
2
pcr 2
JRNZ 4
pcr 3
JRNC
pcr
JRZ 4
1
2
prc 1
JRC
ind
5
LD
sd
F
1111
F
1111
a,w
1
pcr 2
ext 1
pcr 3
bt 1
pcr 1
1
prc
Abbreviations for Addressing Modes: Legend:
dir
sd
Direct
Short Direct
#
e
b
rr
nn
Indicates Illegal Instructions
5-bit Displacement
3-bit Address
1-byte Data space address
1-byte immediate data
Mnemonic
2
e
1
Cycles
JRC
prc
imm Immediate
Operands
Bytes
inh
ext
b.d
bt
Inherent
Extended
Bit Direct
Bit Test
abc 12-bit address
ee 8-bit displacement
Addressing Mode
pcr
ind
Program Counter Relative
Indirect
56/100
1
ST6200C/ST6201C/ST6203C
Opcode Map Summary (Continued)
LOW
LOW
8
9
A
1010
B
1011
C
1100
D
1101
E
1110
F
1111
1000
1001
HI
HI
2
JRNZ 4
JP 2
JRNC
4
RES 2
b0,rr
JRZ 4
LDI 2
JRC 4
LD
0
0
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
abc
abc
abc
abc
abc
abc
abc
abc
abc
abc
abc
abc
abc
abc
abc
abc
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
rr,nn
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
a,(y)
a,rr
0000
0000
1
2
pcr 2
JRNZ 4
ext 1
JP 2
pcr 2
JRNC
b.d
SET 2
b0,rr
1
pcr 3
JRZ 4
imm 1
prc 1
JRC 4
ind
LD
4
DEC
2
1
1
x
a
0001
0001
1
2
pcr 2
JRNZ 4
ext 1
JP 2
pcr 2
JRNC
b.d
RES 2
b4,rr
1
pcr 1
JRZ 4
sd
1
prc 2
JRC 4
dir
CP
4
COM 2
1
2
2
a,(y)
a,rr
0010
0010
1
2
pcr 2
JRNZ 4
ext 1
JP 2
pcr 2
JRNC
b.d
1
pcr
JRZ 4
prc 1
JRC 4
ind
CP
4
SET 2
LD
2
3
3
b4,rr
e
1
x,a
0011
0011
1
2
pcr 2
JRNZ 4
ext 1
JP 2
pcr 2
JRNC
b.d
pcr 1
JRZ 2
sd
1
prc 2
JRC 4
dir
ADD
a,(y)
4
RES 2
b2,rr
RETI 2
inh 1
4
4
e
e
e
e
e
e
e
e
e
e
e
e
0100
0100
1
2
pcr 2
JRNZ 4
ext 1
JP 2
pcr 2
JRNC
b.d
SET 2
b2,rr
1
pcr 1
JRZ 4
prc 1
JRC 4
ind
ADD
4
DEC
2
5
5
y
a,rr
(y)
rr
0101
0101
1
2
pcr 2
JRNZ 4
ext 1
JP 2
pcr 2
JRNC
b.d
RES 2
b6,rr
1
pcr 1
JRZ 2
sd
1
prc 2
JRC 4
dir
INC
4
STOP 2
inh 1
6
6
0110
0110
1
2
pcr 2
JRNZ 4
ext 1
JP 2
pcr 2
JRNC
b.d
SET 2
b6,rr
1
pcr 1
JRZ 4
prc 1
JRC 4
ind
INC
4
LD
2
7
7
y,a
#
0111
0111
1
2
pcr 2
JRNZ 4
ext 1
JP 2
pcr 2
JRNC
b.d
RES 2
b1,rr
1
pcr 1
JRZ
sd
1
2
prc 2
JRC 4
dir
LD
4
8
8
(y),a
rr,a
1000
1000
1
2
pcr 2
JRNZ 4
ext 1
JP 2
pcr 2
JRNC
b.d
SET 2
b1,rr
1
pcr
JRZ 4
1
2
prc 1
JRC 4
ind
LD
4
DEC
sd
9
9
v
1001
1001
1
2
pcr 2
JRNZ 4
ext 1
JP 2
pcr 2
JRNC
b.d
RES 2
b5,rr
1
pcr 1
JRZ 4
1
prc 2
JRC 4
dir
AND
a,(y)
4
RCL 2
A
1010
A
1010
a
1
2
pcr 2
JRNZ 4
ext 1
JP 2
pcr 2
JRNC
b.d
SET 2
b5,rr
1
pcr 1
JRZ 4
inh 1
prc 1
JRC 4
ind
AND
4
LD
sd
2
1
B
1011
B
1011
v,a
a,rr
1
2
pcr 2
JRNZ 4
ext 1
JP 2
pcr 2
JRNC
b.d
RES 2
b3,rr
1
pcr 1
JRZ 2
prc 2
JRC 4
dir
SUB
4
RET 2
C
1100
C
1100
a,(y)
1
2
pcr 2
JRNZ 4
ext 1
JP 2
pcr 2
JRNC
b.d
SET 2
b3,rr
1
pcr 1
JRZ 4
inh 1
prc 1
JRC 4
ind
SUB
4
DEC
sd
2
1
D
1101
D
1101
w
a,rr
(y)
rr
1
2
pcr 2
JRNZ 4
ext 1
JP 2
pcr 2
JRNC
b.d
RES 2
b7,rr
1
pcr 1
JRZ 2
prc 2
JRC 4
dir
DEC
4
WAIT 2
E
1110
E
1110
1
2
pcr 2
JRNZ 4
ext 1
JP 2
pcr 2
JRNC
b.d
SET 2
b7,rr
1
pcr 1
JRZ 4
inh 1
prc 1
JRC 4
ind
DEC
4
LD
sd
2
1
F
1111
F
1111
w,a
1
pcr 2
ext 1
pcr 2
b.d
1
pcr 1
prc 2
dir
Abbreviations for Addressing Modes: Legend:
dir
sd
Direct
Short Direct
#
e
b
rr
nn
Indicates Illegal Instructions
5-bit Displacement
3-bit Address
1-byte Data space address
1-byte immediate data
2
e
1
Mnemonic
Cycles
JRC
prc
imm Immediate
Operands
Bytes
inh
ext
b.d
bt
Inherent
Extended
Bit Direct
Bit Test
abc 12-bit address
ee 8-bit Displacement
Addressing Mode
pcr
ind
Program Counter Relative
Indirect
57/100
1
ST6200C/ST6201C/ST6203C
10 ELECTRICAL CHARACTERISTICS
10.1 PARAMETER CONDITIONS
Unless otherwise specified, all voltages are re-
Figure 30. Pin Loading Conditions
ferred to V
.
SS
10.1.1 Minimum and Maximum Values
Unless otherwise specified the minimum and max-
imum values are guaranteed in the worst condi-
tions of ambient temperature, supply voltage and
frequencies by tests in production on 100% of the
ST6 PIN
C
L
devices with an ambient temperature at T =25°C
A
and T =T max (given by the selected temperature
A
A
range).
Data based on characterization results, design
simulation and/or technology characteristics are
indicated in the table footnotes and are not tested
in production. Based on characterization, the min-
imum and maximum values refer to sample tests
and represent the mean value plus or minus three
times the standard deviation (mean±3Σ).
10.1.5 Pin Input Voltage
The input voltage measurement on a pin of the de-
vice is described in Figure 31.
Figure 31. Pin Input Voltage
10.1.2 Typical Values
Unless otherwise specified, typical data are based
ST6 PIN
on T =25°C, V =5V (for the 4.5V≤V ≤6.0V
A
DD
DD
voltage range) and
V
=3.3V (for the
DD
3V≤V ≤3.6V voltage range). They are given only
DD
V
IN
as design guidelines and are not tested.
10.1.3 Typical Curves
Unless otherwise specified, all typical curves are
given only as design guidelines and are not tested.
10.1.4 Loading Capacitor
The loading conditions used for pin parameter
measurement is shown in Figure 30.
58/100
1
ST6200C/ST6201C/ST6203C
10.2 ABSOLUTE MAXIMUM RATINGS
Stresses above those listed as “absolute maxi-
mum ratings” may cause permanent damage to
the device. This is a stress rating only and func-
tional operation of the device under these condi-
tions is not implied. Exposure to maximum rating
conditions for extended periods may affect device
reliability.
10.2.1 Voltage Characteristics
Symbol
Ratings
Maximum value
7
Unit
V
- V
Supply voltage
DD
SS
1) & 2)
V
Input voltage on any pin
Output voltage on any pin
VSS-0.3 to VDD+0.3
VSS-0.3 to VDD+0.3
3500
IN
V
1) & 2)
V
OUT
V
Electro-static discharge voltage (Human Body Model)
ESD(HBM)
10.2.2 Current Characteristics
Symbol
Ratings
Maximum value
Unit
3)
3)
I
Total current into V power lines (source)
80
100
20
40
15
±5
VDD
DD
I
Total current out of V ground lines (sink)
SS
VSS
Output current sunk by any standard I/O and control pin
Output current sunk by any high sink I/O pin
Output current source by any I/Os and control pin
Injected current on RESET pin
I
mA
IO
2) & 4)
I
INJ(PIN)
Injected current on any other pin
±5
10.2.3 Thermal Characteristics
Symbol
Ratings
Value
Unit
T
Storage temperature range
-60 to +150
°C
STG
Maximum junction temperature
(see THERMAL CHARACTERISTICS section)
T
J
Notes:
1. Directly connecting the RESET and I/O pins to V or V could damage the device if an unintentional internal reset
DD
SS
is generated or an unexpected change of the I/O configuration occurs (for example, due to a corrupted program coun-
ter). To guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7kΩ
for RESET, 10kΩ for I/Os). Unused I/O pins must be tied in the same way to V or V according to their reset con-
DD
SS
figuration.
2. When the current limitation is not possible, the V absolute maximum rating must be respected, otherwise refer to
IN
I
specification. A positive injection is induced by V >V while a negative injection is induced by V <V
.
INJ(PIN)
IN
DD
IN
SS
3. Power (V ) and ground (V ) lines must always be connected to the external supply.
DD
SS
4. Negative injection disturbs the analog performance of the device. In particular, it induces leakage currents throughout
the device including the analog inputs. To avoid undesirable effects on the analog functions, care must be taken:
- Analog input pins must have a negative injection less than 1mA (assuming that the impedance of the analog voltage
is lower than the specified limits).
- Pure digital pins must have a negative injection less than 1mA. In addition, it is recommended to inject the current as
far as possible from the analog input pins.
59/100
1
ST6200C/ST6201C/ST6203C
10.3 OPERATING CONDITIONS
10.3.1 General Operating Conditions
Symbol
Parameter
Supply voltage
Conditions
see Figure 32
Min
Max
6
Unit
3.0
V
V
DD
1)
V
V
V
V
=3.0V, 1 & 6 Suffix
=3.0V, 3 Suffix
0
4
DD
DD
1)
0
4
f
Oscillator frequency
MHz
OSC
1)
=3.6V, 1 & 6Suffix
=3.6V, 3 Suffix
0
8
DD
1)
0
4
DD
f
f
f
f
=4MHz, 1 & 6 Suffix
=4MHz, 3 Suffix
3.0
3.0
3.6
4.5
0
6.0
6.0
6.0
6.0
70
85
125
OSC
OSC
OSC
OSC
V
Operating Supply Voltage
Ambient temperature range
V
DD
=8MHz, 1 & 6 Suffix
=8MHz, 3 Suffix
1 Suffix Version
6 Suffix Version
3 Suffix Version
-40
-40
T
°C
A
Notes:
1. An oscillator frequency above 1.2MHz is recommended for reliable A/D results.
2. Operating conditions with T =-40 to +125°C.
A
Figure 32. f
Maximum Operating Frequency Versus V Supply Voltage for OTP & ROM devices
DD
OSC
[MHz]
f
OSC
1 & 6 suffix version
8
7
6
5
4
3
2
1
3 suffix version
3
f
OSG
2
f
Min
OSG
1
SUPPLY
2.5
VOLTAGE (V
)
DD
3
3.6
4
4.5
5
5.5
6
1. In this area, operation is guaranteed at the quartz crystal frequency.
2. When the OSG is disabled, operation in this area is guaranteed at the crystal frequency. When the
OSG is enabled, operation in this area is guaranteed at a frequency of at least f Min.
OSG
3. When the OSG is disabled, operation in this area is guaranteed at the quartz crystal frequency. When
the OSG is enabled, access to this area is prevented. The internal frequency is kept at f
.
OSG
60/100
1
ST6200C/ST6201C/ST6203C
OPERATING CONDITIONS (Cont’d)
10.3.2 Operating Conditions with Low Voltage Detector (LVD)
Subject to general operating conditions for V , f
, and T .
A
DD OSC
Conditions
1)
Symbol
Parameter
Min
Typ
Max
Unit
Reset release threshold
3.9
4.1
4.3
V
IT+
(V rise)
DD
V
Reset generation threshold
3.6
50
3.8
4
V
V
IT-
(V fall)
DD
LVD voltage threshold hysteresis
V
-V
300
700
mV
mV/s
ns
hys
IT+ IT-
2)
Vt
V
rise time rate
POR
DD
3)
t
Filtered glitch delay on V
Not detected by the LVD
30
g(VDD)
DD
Notes:
1. LVD typical data are based on T =25°C. They are given only as design guidelines and are not tested.
A
2. The minimum V rise time rate is needed to insure a correct device power-on and LVD reset. Not tested in production.
DD
3. Data based on characterization results, not tested in production.
3)
Figure 33. LVD Threshold Versus V and f
DD
OSC
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
f
[MHz]
OSC
8
4
DEVICE UNDER
RESET
IN THIS AREA
FUNCTIONAL AREA
SUPPLY
VOLTAGE [V]
0
V
≥3.6
IT-
2.5
3
3.5
4
4.5
5
5.5
6
Figure 34. Typical LVD Thresholds Versus
Temperature for OTP devices
Figure 35. Typical LVD thresholds vs.
Temperature for ROM devices
Thresholds [V]
4.2
Thresholds [V]
4.2
4
4
V
IT+
V
Vdd up
IT+
V
IT-
V
3.8
3.6
3.8
3.6
IT-
-40°C
25°C
95°C
125°C
-40°C
25°C
95°C
125°C
T [°C]
T [°C]
61/100
1
ST6200C/ST6201C/ST6203C
10.4 SUPPLY CURRENT CHARACTERISTICS
The following current consumption specified for
the ST6 functional operating modes over tempera-
ture range does not take into account the clock
source current consumption. To get the total de-
vice consumption, the two current values must be
added (except for STOP mode for which the clock
is stopped).
10.4.1 RUN Modes
1)
2)
Symbol
Parameter
Conditions
Typ
Max
Unit
0.5
1.3
1.6
2.2
3.3
0.7
1.7
2.4
3.3
4.8
f
f
f
f
f
=32kHz
=1MHz
=2MHz
=4MHz
=8MHz
OSC
OSC
OSC
OSC
OSC
3)
3)
Supply current in RUN mode
(see Figure 36 & Figure 37)
I
mA
DD
0.3
0.6
0.9
1.0
1.8
0.4
0.8
1.2
1.5
2.3
f
f
f
f
f
=32kHz
=1MHz
=2MHz
=4MHz
=8MHz
OSC
OSC
OSC
OSC
OSC
Supply current in RUN mode
(see Figure 36 & Figure 37)
Notes:
1. Typical data are based on T =25°C, V =5V (4.5V≤V ≤6.0V range) and V =3.3V (3V≤V ≤3.6V range).
A
DD
DD
DD
DD
2. Data based on characterization results, tested in production at V max. and f
max.
DD
OSC
3. CPU running with memory access, all I/O pins in input with pull-up mode (no load), all peripherals in reset state; clock
input (OSC ) driven by external square wave, OSG and LVD disabled, option bytes not programmed.
IN
Figure 36. Typical I in RUN vs. f
Figure 37. Typical I
DD
in RUN vs. Temperature
DD
DD
CPU
(V = 5V)
IDD [mA]
5
IDD [mA]
3.5
8MHz
4MHz
2MHz
1MHz
32KHz
3
2.5
2
4
3
2
1
0
8MHz
4MHz
2MHz
1MHz
32KHz
1.5
1
0.5
0
3
4
5
6
-40
25
95
125
VDD [V]
T[°C]
62/100
1
ST6200C/ST6201C/ST6203C
SUPPLY CURRENT CHARACTERISTICS (Cont’d)
10.4.2 WAIT Modes
1)
2)
Symbol
Parameter
Conditions
Typ
Max
Unit
330
550
600
650
700
800
f
f
f
f
f
=32kHz
=1MHz
=2MHz
=4MHz
=8MHz
OSC
OSC
OSC
OSC
OSC
3)
Supply current in WAIT mode
Option bytes not programmed
(see Figure 38)
350
370
410
480
18
26
41
57
70
60
80
120
180
200
f
f
f
f
f
=32kHz
=1MHz
=2MHz
=4MHz
=8MHz
OSC
OSC
OSC
OSC
OSC
3)
Supply current in WAIT mode
Option bytes programmed to 00H
(see Figure 39)
190
210
240
280
350
300
350
400
500
600
f
f
f
f
f
=32kHz
=1MHz
=2MHz
=4MHz
=8MHz
OSC
OSC
OSC
OSC
OSC
3)
Supply current in WAIT mode
(see Figure 40)
I
µA
DD
80
90
100
120
150
120
140
150
200
250
f
f
f
f
f
=32kHz
=1MHz
=2MHz
=4MHz
=8MHz
OSC
OSC
OSC
OSC
OSC
3)
Supply current in WAIT mode
Option bytes not programmed
(see Figure 38)
5
8
16
18
20
30
40
50
60
100
f
f
f
f
f
=32kHz
=1MHz
=2MHz
=4MHz
=8MHz
OSC
OSC
OSC
OSC
OSC
3)
Supply current in WAIT mode
Option bytes programmed to 00H
(see Figure 39)
60
65
80
100
130
100
110
120
150
210
f
f
f
f
f
=32kHz
=1MHz
=2MHz
=4MHz
=8MHz
OSC
OSC
OSC
OSC
OSC
3)
Supply current in WAIT mode
Option bytes not programmed
(see Figure 40)
Notes:
1. Typical data are based on T =25°C, V =5V (4.5V≤V ≤6.0V range) and V =3.3V (3V≤V ≤3.6V range).
A
DD
DD
DD
DD
2. Data based on characterization results, tested in production at V max. and f
max.
DD
OSC
3. All I/O pins in input with pull-up mode (no load), all peripherals in reset state; clock input (OSC ) driven by external
IN
square wave, OSG and LVD disabled.
63/100
1
ST6200C/ST6201C/ST6203C
SUPPLY CURRENT CHARACTERISTICS (Cont’d)
Figure 38. Typical I
programmed
in WAIT vs f
and Temperature for OTP devices with option bytes not
CPU
DD
IDD [µA]
IDD [µA]
700
800
8MHz
1M
8MHz
4MHz
2MHz
1MHz
700
600
500
400
300
200
100
0
4MHz
2MHz
32KHz
32KHz
600
500
400
300
200
3
4
5
6
-40
25
95
125
VDD [V]
T[°C]
Figure 39. Typical I
programmed to 00H
in WAIT vs f
and Temperature for OTP devices with option bytes
CPU
DD
IDD [µA]
IDD [µA]
90
120
8MHz
1M
8MHz
4MHz
2MHz
1MHz
4MHz
32KHz
80
70
60
50
40
30
20
10
32KHz
100
2MHz
80
60
40
20
0
3
4
5
6
-20
25
95
VDD [V]
T[°C]
64/100
1
ST6200C/ST6201C/ST6203C
SUPPLY CURRENT CHARACTERISTICS (Cont’d)
Figure 40. Typical I in WAIT vs f
and Temperature for ROM devices
CPU
DD
IDD [µA]
IDD [µA]
600
450
8MHz
4MHz
2MHz
1M
8MHz
4MHz
2MHz
1MHz
32KHz
32KHz
400
350
300
250
200
150
100
500
400
300
200
100
0
3
4
5
6
-20
25
95
125
VDD [V]
T[°C]
65/100
1
ST6200C/ST6201C/ST6203C
SUPPLY CURRENT CHARACTERISTICS (Cont’d)
10.4.3 STOP Mode
1)
Symbol
Parameter
Conditions
Typ
Max
Unit
3)
10
20
OTP devices
ROM devices
0.3
4)
2)
Supply current in STOP mode
(see Figure 41 & Figure 42)
I
µA
DD
3)
2
20
0.1
4)
Notes:
1. Typical data are based on V =5.0V at T =25°C.
DD
A
2. All I/O pins in input with pull-up mode (no load), all peripherals in reset state, OSG and LVD disabled, option bytes
programmed to 00H. Data based on characterization results, tested in production at V max. and f
max.
DD
CPU
3. Maximum STOP consumption for -40°C<Ta<90°C
4. Maximum STOP consumption for -40°C<Ta<125°C
Figure 41. Typical I in STOP vs Temperature
Figure 42. Typical I in STOP vs Temperature
DD
DD
for OTP devices
for ROM devices
IDD [nA]
IDD [nA]
1200
Ta=-40°C
Ta=25°C
Ta=95°C
Ta=-40°C
Ta=25°C
Ta=95°C
Ta=125°C
Ta=125°C
1500
1000
500
0
1000
800
600
400
200
0
3
4
5
6
3
4
5
6
VDD [V]
VDD [V]
66/100
1
ST6200C/ST6201C/ST6203C
SUPPLY CURRENT CHARACTERISTICS (Cont’d)
10.4.4 Supply and Clock System
The previous current consumption specified for
the ST6 functional operating modes over tempera-
ture range does not take into account the clock
source current consumption. To get the total de-
vice consumption, the two current values must be
added (except for STOP mode).
1)
2)
Symbol
Parameter
Conditions
=32 kHz,
Typ
Max
Unit
f
f
f
f
f
OSC
OSC
OSC
OSC
OSC
=1 MHz
=2 MHz
=4 MHz
=8 MHz
230
V
V
V
V
=5.0 V
=3.3 V
=5.0 V
=3.3 V
260
340
480
DD
DD
DD
DD
Supply current of RC oscillator
f
f
f
f
f
=32 kHz,
=1 MHz
=2 MHz
=4 MHz
=8 MHz
OSC
OSC
OSC
OSC
OSC
80
110
180
320
I
DD(CK)
f
f
f
f
f
=32 kHz,
=1 MHz
=2 MHz
=4 MHz
=8MHz
900
280
240
140
40
OSC
OSC
OSC
OSC
OSC
µA
Supply current of resonator oscillator
f
f
f
f
f
=32 kHz,
=1 MHz
=2 MHz
=4 MHz
=8 MHz
120
70
50
20
10
OSC
OSC
OSC
OSC
OSC
3)
I
LFAO supply current
V
V
V
=5.0 V
=5.0 V
=5.0 V
102
40
DD(LFAO)
DD
DD
DD
4)
I
OSG supply current
DD(OSG)
5)
I
LVD supply current
170
DD(LVD)
10.4.5 On-Chip Peripherals
Symbol
1)
Parameter
Conditions
Typ
Unit
V
V
V
V
=5.0 V
170
100
80
DD
DD
DD
DD
6)
I
8-bit Timer supply current
f
f
=8 MHz
=8 MHz
DD(TIM)
OSC
=3.3 V
=5.0 V
=3.3 V
µA
7)
I
ADC supply current when converting
DD(ADC)
OSC
50
Notes:
1. Typical data are based on T =25°C.
A
2. Data based on characterization results, not tested in production.
3. Data based on a differential I measurement between reset configuration (OSG and LFAO disabled) and LFAO run-
DD
ning (also includes the OSG stand alone consumption).
4. Data based on a differential I measurement between reset configuration with OSG disabled and OSG enabled.
DD
5. Data based on a differential I measurement between reset configuration with LVD disabled and LVD enabled.
DD
6. Data based on a differential I measurement between reset configuration (timer disabled) and timer running.
DD
7. Data based on a differential I measurement between reset configuration and continuous A/D conversions.
DD
67/100
1
ST6200C/ST6201C/ST6203C
10.5 CLOCK AND TIMING CHARACTERISTICS
Subject to general operating conditions for V , f
, and T .
DD OSC
A
10.5.1 General Timings
1)
Symbol
Parameter
Conditions
Min
2
Typ
Max
5
Unit
tCPU
µs
4
t
Instruction cycle time
c(INST)
f
f
=8 MHz
3.25
6
6.5
8.125
11
CPU
2)
tCPU
µs
Interrupt reaction time
t
v(IT)
t
= ∆t
+ 6
=8 MHz
9.75
17.875
v(IT)
c(INST)
CPU
10.5.2 External Clock Source
Symbol
Parameter
OSC input pin high level voltage
Conditions
See Figure 43
≤V ≤V
Min
Typ
Max
Unit
V
V
0.7xV
V
DD
OSCINH
IN
DD
V
OSC input pin low level voltage
V
0.3xV
DD
OSCINL
IN
SS
I
OSCx Input leakage current
V
± 2
µA
L
SS
IN
DD
Notes:
1. Data based on typical application software.
2. Time measured between interrupt event and interrupt vector fetch. ∆tc(INST) is the number of tCPU cycles needed to finish
the current instruction execution.
Figure 43. Typical Application with an External Clock Source
90%
V
V
OSCINH
OSCINL
10%
OSC
OUT
Not connected
f
OSC
EXTERNAL
CLOCK SOURCE
I
L
OSC
IN
ST62XX
68/100
1
ST6200C/ST6201C/ST6203C
CLOCK AND TIMING CHARACTERISTICS (Cont’d)
10.5.3 Crystal and Ceramic Resonator Oscillators
The ST6 internal clock can be supplied with sever-
al different Crystal/Ceramic resonator oscillators.
Only parallel resonant crystals can be used. All the
information given in this paragraph are based on
characterization results with specified typical ex-
ternal components. Refer to the crystal/ceramic
resonator manufacturer for more details (frequen-
cy, package, accuracy...).
Symbol
Parameter
Conditions
Typ
Unit
R
Feedback resistor
3
MΩ
F
120
47
33
33
22
f
f
f
f
f
=32 kHz,
OSC
OSC
OSC
OSC
OSC
=1 MHz
=2 MHz
=4 MHz
=8 MHz
C
C
Recommended load capacitances versus equiva-
lent crystal or ceramic resonator frequency
L1
L2
pF
Typical Crystal or Ceramic Resonators
C
C
L2
t
L1
SU(osc)
1)
Oscillator
1)
[ms]
[pF] [pF]
220 220
100 100
47 47
47 47
15 15
Reference
CSB455E
Freq.
455KHz
1MHz
2MHz
4MHz
8MHz
Characteristic
∆f
∆f
∆f
∆f
∆f
=[±0.5KHz
=[±0.5KHz
,±0.3% ,±0.5%
]
]
OSC
OSC
OSC
OSC
OSC
tolerance
tolerance
∆Ta
aging
CSB1000J
,±0.3% ,±0.5%
∆Ta
aging
CSTCC2.00MG0H6
CSTCC4.00MG0H6
CSTCC8.00MG
=[±0.5%
=[±0.5%
=[±0.5%
,±0.5% ,±0.3%
]
]
]
tolerance
tolerance
tolerance
∆Ta
aging
aging
aging
,±0.3% ,±0.3%
∆Ta
,±0.3% ,±0.3%
∆Ta
Notes:
1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
2. t is the typical oscillator start-up time measured between V =2.8V and the fetch of the first instruction (with a
SU(OSC)
DD
quick V ramp-up from 0 to 5V (<50µs).
DD
3. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small R value.
S
Refer to crystal/ceramic resonator manufacturer for more details.
Figure 44. Typical Application with a Crystal or Ceramic Resonator
V
DD
C
L1
OSC
IN
RESONATOR
R
F
F
OSC
OSC
OUT
C
L2
ST62XX
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ST6200C/ST6201C/ST6203C
CLOCK AND TIMING CHARACTERISTICS (Cont’d)
10.5.4 RC Oscillator
The ST6 internal clock can be supplied with an external RC oscillator. Depending on the RNET value, the
accuracy of the frequency is about 20%, so it may not be suitable for some applications.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
MHz
kΩ
R
R
R
R
R
=22 kΩ
=47 kΩ
=100 kΩ
=220 kΩ
=470 kΩ
7.2
5.1
3.2
1.8
0.9
8.6
5.7
3.4
1.9
0.95
10
6.5
3.8
2
NET
NET
NET
NET
NET
1.1
1)
f
RC oscillator frequency
OSC
R
R
R
R
R
=22 kΩ
=47 kΩ
=100 kΩ
=220 kΩ
=470 kΩ
3.7
2.8
1.8
1
4.3
3
1.9
1.1
0.55
4.9
3.3
2
1.2
0.6
NET
NET
NET
NET
NET
0.5
2)
R
RC Oscillator external resistor
see Figure 46 & Figure 47
22
870
NET
Notes:
1. Data based on characterization results, not tested in production. These measurements were done with the OSCin pin
unconnected (only soldered on the PCB).
2. R
must have a positive temperature coefficient (ppm/°C), carbon resistors should therefore not be used.
NET
Figure 45. Typical Application with RC Oscillator
V
V
DD
DD
EXTERNAL RC
OSC
OUT
MIRROR
CURRENT
R
NET
V
DD
f
OSC
OSC
NC
IN
C ~9pF DISCHARGE
EX
ST62XX
70/100
1
ST6200C/ST6201C/ST6203C
CLOCK AND TIMING CHARACTERISTICS (Cont’d)
Figure 46. Typical RC Oscillator frequency vs.
DD
Figure 47. Typical RC Oscillator frequency vs.
V
Temperature (V = 5V)
DD
Rnet=22KOhm
Rnet=47KOhm
Rnet=100KOhm
Rnet=220KOhm
Rnet=470KOhm
fosc [MHz]
Rnet=22KOhm
fosc [MHz]
Rnet=47KOhm
Rnet=100KOhm
Rnet=220KOhm
Rnet=470KOhm
12
10
8
10
8
6
6
4
4
2
2
0
0
3
4
5
6
-40
25
95
125
VDD [V]
Ta [°C]
10.5.5 Oscillator Safeguard (OSG) and Low Frequency Auxiliary Oscillator (LFAO)
Symbol
Parameter
Conditions
Min
200
86
4
Typ
350
150
Max
800
340
Unit
T =25° C, V =5.0 V
Low Frequency Auxiliary Oscillator
A
DD
f
kHz
1)
LFAO
Frequency
T =25° C, V =3.3 V
A
DD
T =25° C, V =4.5 V
Internal Frequency with OSG ena-
bled
A
DD
f
MHz
OSG
T =25° C, V =3.3 V
2
A
DD
Figure 48. Typical LFAO Frequencies
fosc [kHz]
600
Ta=-40°C
Ta=25°C
Ta=125°C
500
400
300
200
100
0
3
4
5
6
VDD [V]
Note:
1. Data based on characterization results.
71/100
1
ST6200C/ST6201C/ST6203C
10.6 MEMORY CHARACTERISTICS
Subject to general operating conditions for V , f
, and T unless otherwise specified.
A
DD OSC
10.6.1 RAM and Hardware Registers
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
1)
V
Data retention
0.7
V
RM
10.6.2 EPROM Program Memory
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
2)
3)
t
Data retention
T =+55°C
10
years
ret
A
Figure 49. EPROM Retention Time vs. Temperature
Retention time [Years]
100000
10000
1000
100
10
1
0.1
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90 100 110 120
Temperature [°C]
Notes:
1. Minimum V supply voltage without losing data stored in RAM (in STOP mode or under RESET) or in hardware reg-
DD
isters (only in STOP mode). Guaranteed by construction, not tested in production.
2. Data based on reliability test results and monitored in production.
3. The data retention time increases when the T decreases, see Figure 49.
A
72/100
1
ST6200C/ST6201C/ST6203C
10.7 EMC CHARACTERISTICS
Susceptibility tests are performed on a sample ba-
sis during product characterization.
■ ESD: Electro-Static Discharge (positive and
negative) is applied on all pins of the device until
a functional disturbance occurs. This test
conforms with the IEC 1000-4-2 standard.
10.7.1 Functional EMS
(Electro Magnetic Susceptibility)
■ FTB: A Burst of Fast Transient voltage (positive
Based on a simple running application on the
product (toggling 2 LEDs through I/O ports), the
product is stressed by two electro magnetic events
until a failure occurs (indicated by the LEDs).
and negative) is applied to V and V through
DD
SS
a 100pF capacitor, until a functional disturbance
occurs. This test conforms with the IEC 1000-4-
4 standard.
A device reset allows normal operations to be re-
sumed.
1)
1)
Symbol
Parameter
Conditions
=5V, T =+25°C, f
conforms to IEC 1000-4-2
Neg
Pos
Unit
Voltage limits to be applied on any I/O pin
to induce a functional disturbance
V
=8MHz
OSC
DD
A
V
-2
2
FESD
kV
Fast transient voltage burst limits to be ap-
V
=5V, T =+25°C, f
=8MHz
OSC
DD
A
V
plied through 100pF on V and V pins
-2.5
3
FFTB
DD
DD
conforms to IEC 1000-4-4
to induce a functional disturbance
Notes:
1. Data based on characterization results, not tested in production.
2. The suggested 10 µF and 0.1 µF decoupling capacitors on the power supply lines are proposed as a good price vs.
EMC performance tradeoff. They have to be put as close as possible to the device power supply pins. Other EMC rec-
ommendations are given in other sections (I/Os, RESET, OSCx pin characteristics).
2)
Figure 50. EMC Recommended Star Network Power Supply Connection
ST62XX
V
DD
10 µF 0.1 µF
V
V
DD
SS
ST6
POWER
SUPPLY
SOURCE
DIGITAL NOISE
FILTERING
(close to the MCU)
73/100
1
ST6200C/ST6201C/ST6203C
EMC CHARACTERISTICS (Cont’d)
10.7.2 Absolute Electrical Sensitivity
– S1 switches position from generator to R.
Based on three different tests (ESD, LU and DLU)
using specific measurement methods, the product
is stressed in order to determine its performance in
terms of electrical sensitivity. For more details, re-
fer to the AN1181 application note.
– A discharge from C through R (body resistance)
to the ST6 occurs.
L
– S2 must be closed 10 to 100ms after the pulse
delivery period to ensure the ST6 is not left in
charge state. S2 must be opened at least 10ms
prior to the delivery of the next pulse.
10.7.2.1 Electro-Static Discharge (ESD)
Electro-Static Discharges (3 positive then 3 nega-
tive pulses separated by 1 second) are applied to
the pins of each sample according to each pin
combination. The sample size depends of the
number of supply pins of the device (3 parts*(n+1)
supply pin). Two models are usually simulated:
Human Body Model and Machine Model. This test
conforms to the JESD22-A114A/A115A standard.
See Figure 51 and the following test sequences.
Machine Model Test Sequence
– C is loaded through S1 by the HV pulse gener-
L
ator.
– S1 switches position from generator to ST6.
– A discharge from C to the ST6 occurs.
L
– S2 must be closed 10 to 100ms after the pulse
delivery period to ensure the ST6 is not left in
charge state. S2 must be opened at least 10ms
prior to the delivery of the next pulse.
Human Body Model Test Sequence
– C is loaded through S1 by the HV pulse gener-
ator.
– R (machine resistance), in series with S2, en-
sures a slow discharge of the ST6.
L
Absolute Maximum Ratings
1)
Symbol
Ratings
Conditions
Maximum value
Unit
Electro-static discharge voltage
(Human Body Model)
T =+25°C
V
2000
A
ESD(HBM)
V
Electro-static discharge voltage
(Machine Model)
T =+25°C
V
200
A
ESD(MM)
Notes:
1. Data based on characterization results, not tested in production.
Figure 51. Typical Equivalent ESD Circuits
S1
R=1500Ω
S1
HIGH VOLTAGE
PULSE
GENERATOR
HIGH VOLTAGE
PULSE
GENERATOR
ST6
ST6
C =100pF
S2
L
S2
C =200pF
L
HUMAN BODY MODEL
MACHINE MODEL
74/100
1
ST6200C/ST6201C/ST6203C
EMC CHARACTERISTICS (Cont’d)
10.7.2.2 Static and Dynamic Latch-Up
■ DLU: Electro-Static Discharges (one positive
then one negative test) are applied to each pin
of 3 samples when the micro is running to
assess the latch-up performance in dynamic
mode. Power supplies are set to the typical
values, the oscillator is connected as near as
possible to the pins of the micro and the
component is put in reset mode. This test
conforms to the IEC1000-4-2 and SAEJ1752/3
standards and is described in Figure 52. For
more details, refer to the AN1181 application
note.
■ LU: 3 complementary static tests are required
on 10 parts to assess the latch-up performance.
A supply overvoltage (applied to each power
supply pin), a current injection (applied to each
input, output and configurable I/O pin) and a
power supply switch sequence are performed
on each sample. This test conforms to the EIA/
JESD 78 IC latch-up standard. For more details,
refer to the AN1181 application note.
Electrical Sensitivities
1)
Symbol
LU
Parameter
Static latch-up class
Dynamic latch-up class
Conditions
Class
T =+25°C
A
A
A
T =+85°C
A
V
=5V, f
=4MHz, T =+25°C
DLU
A
DD
OSC A
Notes:
1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC spec-
ifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the
JEDEC criteria (international standard).
2. Schaffner NSG435 with a pointed test finger.
Figure 52. Simplified Diagram of the ESD Generator for DLU
R
=50MΩ
R =330Ω
D
CH
DISCHARGE TIP
V
V
DD
SS
HV RELAY
C =150pF
S
ST6
ESD
2)
DISCHARGE
RETURN CONNECTION
GENERATOR
75/100
1
ST6200C/ST6201C/ST6203C
EMC CHARACTERISTICS (Cont’d)
10.7.3 ESD Pin Protection Strategy
Standard Pin Protection
To protect an integrated circuit against Electro-
Static Discharge the stress must be controlled to
prevent degradation or destruction of the circuit el-
ements. The stress generally affects the circuit el-
ements which are connected to the pads but can
also affect the internal devices when the supply
pads receive the stress. The elements to be pro-
tected must not receive excessive current, voltage
or heating within their structure.
To protect the output structure the following ele-
ments are added:
– A diode to V (3a) and a diode from V (3b)
DD
SS
– A protection device between V
and V (4)
SS
DD
To protect the input structure the following ele-
ments are added:
– A resistor in series with the pad (1)
– A diode to V (2a) and a diode from V (2b)
DD
SS
An ESD network combines the different input and
output ESD protections. This network works, by al-
lowing safe discharge paths for the pins subjected
to ESD stress. Two critical ESD stress cases are
presented in Figure 53 and Figure 54 for standard
pins.
– A protection device between V
and V (4)
DD
SS
Figure 53. Positive Stress on a Standard Pad vs. V
SS
V
V
DD
DD
(3a)
(3b)
(2a)
(1)
(4)
OUT
IN
Main path
(2b)
Path to avoid
V
V
V
SS
SS
Figure 54. Negative Stress on a Standard Pad vs. V
DD
V
DD
DD
(3a)
(3b)
(2a)
(1)
(4)
OUT
IN
Main path
(2b)
V
V
SS
SS
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1
ST6200C/ST6201C/ST6203C
10.8 I/O PORT PIN CHARACTERISTICS
10.8.1 General Characteristics
Subject to general operating conditions for V , f
, and T unless otherwise specified.
A
DD OSC
1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
2)
V
Input low level voltage
0.3xVDD
IL
V
2)
V
Input high level voltage
0.7xVDD
200
IH
V
V
V
=5V
400
400
DD
DD
3)
V
Schmitt trigger voltage hysteresis
Input leakage current
mV
µA
kΩ
hys
=3.3V
200
SS≤V ≤V
IN
DD
I
0.1
1
L
(no pull-up configured)
V
V
=5V
40
80
110
230
5
350
700
10
DD
DD
4)
R
Weak pull-up equivalent resistor
V =V
IN SS
PU
=3.3V
C
I/O input pin capacitance
pF
pF
IN
C
I/O output pin capacitance
5
10
OUT
5)
t
Output high to low level fall time
Output low to high level rise time
30
35
C =50pF
Between 10% and 90%
f(IO)out
r(IO)out
L
ns
5)
t
6)
t
External interrupt pulse time
1
t
CPU
w(IT)in
Figure 55. Typical R vs. V with V = V
SS
PU
DD
IN
Rpu [Khom]
350
Ta=-40°C
Ta=25°C
Ta=95°C
Ta=125°C
300
250
200
150
100
50
3
4
5
6
VDD [V]
Notes:
1. Unless otherwise specified, typical data are based on T =25°C and V =5V.
A
DD
2. Data based on characterization results, not tested in production.
3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
4. The R pull-up equivalent resistor is based on a resistive transistor. This data is based on characterization results,
PU
not tested in production.
5. Data based on characterization results, not tested in production.
6. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external
interrupt source.
Figure 56. Two typical Applications with unused I/O Pin
V
ST62XX
DD
UNUSED I/O PORT
10kΩ
10kΩ
UNUSED I/O PORT
ST62XX
77/100
1
ST6200C/ST6201C/ST6203C
I/O PORT PIN CHARACTERISTICS (Cont’d)
10.8.2 Output Driving Current
Subject to general operating conditions for V , f
, and T unless otherwise specified.
A
DD OSC
Symbol
Parameter
Conditions
=+10µA, T ≤125°C
Min
Max
0.1
0.8
0.8
1.2
0.1
0.8
0.8
1.3
1.3
2
Unit
I
I
I
I
I
I
I
I
I
I
I
I
I
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
A
=+3mA, T ≤125°C
Output low level voltage for a standard I/O pin
(see Figure 57 and Figure 60)
A
=+5mA, T ≤85°C
A
=+10mA, T ≤85°C
A
=+10µA, T ≤125°C
A
1)
V
OL
=+7mA, T ≤125°C
A
V
=+10mA, T ≤85°C
Output low level voltage for a high sink I/O pin
(see Figure 58 and Figure 61)
A
=+15mA, T ≤125°C
A
=+20mA, T ≤85°C
A
=+30mA, T ≤85°C
A
=-10µA, T ≤125°C
V
V
V
-0.1
A
DD
DD
DD
Output high level voltage for an I/O pin
(see Figure 59 and Figure 62)
2)
V
=-3mA, T ≤125°C
-1.5
-1.5
OH
A
=-5mA, T ≤85°C
A
Notes:
1. The I current sunk must always respect the absolute maximum rating specified in Section 10.2.2 and the sum of I
IO
IO
(I/O ports and control pins) must not exceed I
.
VSS
2. The I current source must always respect the absolute maximum rating specified in Section 10.2.2 and the sum of
IO
I
(I/O ports and control pins) must not exceed I
. True open drain I/O pins does not have V
.
IO
VDD
OH
Figure 57. Typical V at V = 5V (standard)
Figure 58. Typical V at V = 5V (high-sink)
OL DD
OL
DD
Vol [V] at Vdd=5V
1
Vol [mV] at Vdd=5V
Ta=-40°C Ta=95°C
Ta=-40°C Ta=95°C
1000
800
600
400
200
0
0.8
0.6
0.4
0.2
0
Ta=25°C
Ta=125°C
Ta=25°C
Ta=125°C
0
4
8
12
16
20
0
2
4
6
8
10
Iio [mA]
Iio [mA]
78/100
1
ST6200C/ST6201C/ST6203C
I/O PORT PIN CHARACTERISTICS (Cont’d)
Figure 59. Typical V at V = 5V
OH
DD
Voh [V] at Vdd=5V
5
4.5
4
Ta=-40°C Ta=95°C
Ta=25°C Ta=125°C
3.5
-8
-6
-4
Iio [mA]
-2
0
Figure 60. Typical V vs V (standard I/Os)
OL
DD
Vol [mV] at Iio=2mA
350
Ta=-40°C Ta=95°C
Vol [mV] at Iio=5mA
700
Ta=-40°C Ta=95°C
Ta=25°C
Ta=125°C
Ta=25°C
Ta=125°C
300
250
200
600
500
400
150
3
300
3
4
5
6
4
5
6
VDD [V]
VDD [V]
Figure 61. Typical V vs V (high-sink I/Os)
OL
DD
Vol [V] at Iio=8mA
Vol [V] at Iio=20mA
Ta=-40°C Ta=95°C
0.55
0.5
1.8
1.6
1.4
1.2
1
Ta=-40°C Ta=95°C
Ta=25°C
Ta=125°C
0.45
0.4
Ta=25°C
Ta=125°C
0.35
0.3
0.8
0.6
0.25
0.2
3
0.4
3
4
5
6
4
5
6
VDD [V]
VDD [V]
79/100
1
ST6200C/ST6201C/ST6203C
I/O PORT PIN CHARACTERISTICS (Cont’d)
Figure 62. Typical V vs V
OH
DD
Voh [V] at Iio=-2mA
6
Voh [V] at Iio=-5mA
6
5
4
3
2
5
4
3
2
Ta=-40°C Ta=95°C
Ta=-40°C Ta=95°C
Ta=25°C
Ta=125°C
Ta=25°C
Ta=125°C
1
3
3
4
5
6
4
5
6
VDD [V]
VDD [V]
80/100
1
ST6200C/ST6201C/ST6203C
10.9 CONTROL PIN CHARACTERISTICS
10.9.1 Asynchronous RESET Pin
Subject to general operating conditions for V , f
, and T unless otherwise specified.
A
DD OSC
1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
V
2)
V
Input low level voltage
0.3xVDD
IL
2)
V
Input high level voltage
0.7xVDD
200
IH
3)
V
Schmitt trigger voltage hysteresis
400
mV
kΩ
hys
V
V
V
V
=5V
150
350
730
2.8
900
DD
DD
DD
DD
4)
R
Weak pull-up equivalent resistor
V =V
ON
IN
SS
=3.3V
=5V
300
1900
R
ESD resistor protection
V =V
kΩ
ESD
IN
SS
=3.3V
External pin or
internal reset sources
t
CPU
µs
t
Generated reset pulse duration
w(RSTL)out
5)
t
t
External reset pulse hold time
µs
h(RSTL)in
6)
Filtered glitch duration
ns
g(RSTL)in
Notes:
1. Unless otherwise specified, typical data are based on T =25°C and V =5V.
A
DD
2. Data based on characterization results, not tested in production.
3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
4. The R
pull-up equivalent resistor is based on a resistive transistor. This data is based on characterization results,
ON
not tested in production.
5. All short pulse applied on RESET pin with a duration below t
can be ignored.
h(RSTL)in
6. The reset network protects the device against parasitic resets, especially in a noisy environment.
7. The output of the external reset circuit must have an open-drain output to drive the ST6 reset pad. Otherwise the device
can be damaged when the ST6 generates an internal reset (LVD or watchdog).
Figure 63. Typical R
vs V with V =V
DD IN SS
ON
Ron [Kohm]
1000
900
800
700
600
500
400
300
Ta=-40°C
Ta=25°C
Ta=95°C
Ta=125°C
200
100
3
4
5
6
VDD [V]
81/100
1
ST6200C/ST6201C/ST6203C
CONTROL PIN CHARACTERISTICS (Cont’d)
8)
Figure 64. Typical Application with RESET pin
V
V
DD
INTERNAL
RESET
DD
f
INT
VDD
RPU
STOP MODE
0.1µF
0.1µF
4.7kΩ
RESET
EXTERNAL
RESET
7)
1)
RESD
CIRCUIT
WATCHDOG RESET
LVD RESET
10.9.2 NMI Pin
Subject to general operating conditions for V , f
, and T unless otherwise specified.
DD OSC
A
1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
V
2)
V
Input low level voltage
0.3xVDD
IL
2)
V
Input high level voltage
0.7xVDD
200
IH
3)
V
Schmitt trigger voltage hysteresis
400
mV
kΩ
hys
V
V
=5V
40
100
200
350
700
DD
4)
R
Weak pull-up equivalent resistor
V =V
IN SS
pull-up
=3.3V
80
DD
Notes:
1. Unless otherwise specified, typical data are based on T =25°C and V =5V.
A
DD
2. Data based on characterization results, not tested in production.
3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
4. The R
equivalent resistor is based on a resistive transistor. This data is based on characterization results, not
pull-up
tested in production.
Figure 65. Typical R
vs. V with V =V
DD IN SS
pull-up
Rpull-up [Kohm]
300
Ta=-40°C
Ta=25°C
Ta=95°C
250
200
150
100
Ta=125°C
50
3
4
5
6
VDD [V]
82/100
1
ST6200C/ST6201C/ST6203C
CONTROL PIN CHARACTERISTICS (Cont’d)
10.10 TIMER PERIPHERAL CHARACTERISTICS
Subject to general operating conditions for V
,
Refer to I/O port characteristics for more details on
the input/output alternate function characteristics
(TIMER).
DD
f
, and T unless otherwise specified.
OSC
A
10.10.1 Watchdog Timer
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tINT
ms
3,072
0.768
0.384
196,608
49.152
24.576
t
Watchdog time-out duration
fCPU=4MHz
CPU=8MHz
w(WDG)
f
ms
10.10.2 8-Bit Timer
Symbol
Parameter
Conditions
Min
0
Typ
Max
Unit
MHz
ns
f
Timer external clock frequency
f
/4
EXT
INT
VDD>4.5V
VDD=3V
125
1
t
Pulse width at TIMER pin
w
µs
83/100
1
ST6200C/ST6201C/ST6203C
10.11 8-BIT ADC CHARACTERISTICS
Subject to general operating conditions for V , f
, and T unless otherwise specified.
DD OSC
A
1)
Symbol
Parameter
Clock frequency
Conditions
Min
Typ
Max
Unit
MHz
V
f
1.2
f
OSC
OSC
2)
V
R
Conversion range voltage
External input resistor
V
V
AIN
AIN
SS
DD
3)
10
kΩ
f
f
=8MHz
=4MHz
70
140
OSC
OSC
t
Total convertion time
µs
ADC
2
4
t
CPU
4)
t
Stabilization time
STAB
f
=8MHz
3.25
6.5
1.0
5
µs
OSC
Analog input current during conver-
sion
AD
µA
pF
I
AC
Analog input capacitance
2
IN
Notes:
1. Unless otherwise specified, typical data are based on T =25°C and V =5V.
A
DD
2. The ADC refers to V and V
.
DD
SS
3. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10kΩ). Data
based on characterization results, not tested in production.
4. As a stabilization time for the AD converter is required, the first conversion after the enable can be wrong.
Figure 66. Typical Application with ADC
R
AIN
r≈150Ω
AINx
V
AIN
ADC
10pF
10MΩ
ST62XX
Note: ADC not present on some devices. See device summary on page 1.
84/100
1
ST6200C/ST6201C/ST6203C
8-BIT ADC CHARACTERISTICS (Cont’d)
ADC Accuracy
Symbol
Parameter
Conditions
Min
Typ.
Max
Unit
±2, fosc>1.2MHz
±4, fosc>32KHz
1)
1.2
|E |
Total unadjusted error
T
1)
0.72
-0.31
0.54
E
Offset error
2)
O
V
=5V
DD
LSB
1)
E
Gain Error
f
=8MHz
G
OSC
1)
|E |
Differential linearity error
D
1)
|E |
Integral linearity error
L
Notes:
1. Negative injection disturbs the analog performance of the device. In particular, it induces leakage currents throughout
the device including the analog inputs. To avoid undesirable effects on the analog functions, care must be taken:
- Analog input pins must have a negative injection less than 1mA (assuming that the impedance of the analog voltage
is lower than the specified limits).
- Pure digital pins must have a negative injection less than 1mA. In addition, it is recommended to inject the current as
far as possible from the analog input pins.
2. Data based on characterization results over the whole temperature range, monitored in production.
Figure 67. ADC Accuracy Characteristics
Digital Result ADCDR
E
G
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line
255
254
253
V
– V
DDA
SSA
1LSB
= ----------------------------------------
IDEAL
256
(2)
E =Total Unadjusted Error: maximum deviation
T
E
between the actual and the ideal transfer curves.
T
(3)
7
6
5
4
3
2
1
E =Offset Error: deviation between the first actual
O
transition and the first ideal one.
(1)
E =Gain Error: deviation between the last ideal
G
transition and the last actual one.
E
O
E
L
E =Differential Linearity Error: maximum deviation
D
between actual steps and the ideal one.
E =Integral Linearity Error: maximum deviation
L
E
between any actual transition and the end point
correlation line.
D
1 LSB
IDEAL
V
(LSB
)
IDEAL
in
0
1
2
3
4
5
6
7
253 254 255 256
V
V
DDA
SSA
Note: ADC not present on some devices. See device summary on page 1.
85/100
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ST6200C/ST6201C/ST6203C
11 GENERAL INFORMATION
11.1 PACKAGE MECHANICAL DATA
Figure 68. 16-Pin Plastic Dual In-Line Package, 300-mil Width
mm
Min Typ Max Min Typ Max
5.33 0.210
inches
Dim.
E
A
A1 0.38
0.015
A2
A
A1
A2 2.92 3.30 4.95 0.115 0.130 0.195
0.36 0.46 0.56 0.014 0.018 0.022
b
L
c
E1
b2 1.14 1.52 1.78 0.045 0.060 0.070
b3 0.76 0.99 1.14 0.030 0.039 0.045
b2
b
eB
e
D1
b3
c
0.20 0.25 0.36 0.008 0.010 0.014
18.67 19.18 19.69 0.735 0.755 0.775
D
D
D1 0.13
0.005
e
2.54
7.62 7.87 8.26 0.300 0.310 0.325
E1 6.10 6.35 7.11 0.240 0.250 0.280
0.100
E
L
2.92 3.30 3.81 0.115 0.130 0.150
eB
10.92
0.430
Number of Pins
N
16
Figure 69. 16-Pin Plastic Small Outline Package, 300-mil Width
D
mm
inches
h x 45×
Dim.
A
L
Min Typ Max Min Typ Max
A
2.35
2.65 0.093
0.30 0.004
0.51 0.013
0.32 0.009
10.50 0.398
7.60 0.291
10.65 0.394
0.104
0.012
0.020
0.013
0.413
0.299
0.419
C
A1
A1 0.10
a
B
C
D
E
H
e
0.33
0.23
e
B
10.10
7.40
10.00
1.27
0.050
h
α
0.25
0°
0.75 0.010
0.030
8°
H
E
8°
0°
L
0.40
1.27 0.016
0.050
Number of Pins
N
16
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ST6200C/ST6201C/ST6203C
PACKAGE MECHANICAL DATA (Cont’d)
Figure 70. 16-Pin Ceramic Side-Brazed Dual In-Line Package
mm
Min Typ Max Min Typ Max
3.78 0.149
inches
Dim.
A
A1 0.38
0.015
B
0.36 0.46 0.56 0.014 0.018 0.022
B1 1.14 1.37 1.78 0.045 0.054 0.070
C
D
0.20 0.25 0.36 0.008 0.010 0.014
19.86 20.32 20.78 0.782 0.800 0.818
D1
17.78
0.700
E1 7.04 7.49 7.95 0.277 0.295 0.313
e
2.54
0.100
G
6.35 6.60 6.86 0.250 0.260 0.270
G1 9.47 9.73 9.98 0.373 0.383 0.393
G2
L
1.02
0.040
2.92 3.30 3.81 0.115 0.130 0.150
S
1.27
4.22
0.050
0.166
CDIP16W
Ø
Number of Pins
16
N
Figure 71. 16-Pin Plastic Shrink Small Outline Package
mm
Min Typ Max Min Typ Max
2.00 0.079
inches
D
Dim.
L
A
A2
A
c
A1
A1 0.05
0.002
A2 1.65 1.75 1.85 0.065 0.069 0.073
b
h
e
b
c
0.22
0.09
0.38 0.009
0.25 0.004
0.015
0.010
D
E
5.90 6.20 6.50 0.232 0.244 0.256
7.40 7.80 8.20 0.291 0.307 0.323
E1 5.00 5.30 5.60 0.197 0.209 0.220
e
θ
0.65
0.026
E
E1
0°
4°
8°
0°
4°
8°
L
0.55 0.75 0.95 0.022 0.030 0.037
Number of Pins
N
16
87/100
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ST6200C/ST6201C/ST6203C
11.2 THERMAL CHARACTERISTICS
Symbol
Ratings
Value
Unit
Package thermal resistance (junction to ambient)
DIP16
SO16
90
90
R
°C/W
thJA
SSOP16
125
1)
P
Power dissipation
500
150
mW
°C
D
2)
T
Maximum junction temperature
Jmax
Notes:
1. The power dissipation is obtained from the formula P = P
+ P
where P
is the chip internal power (I xV
)
D
INT
PORT
INT
DD DD
and P
is the port power dissipation determined by the user.
PORT
2. The average chip-junction temperature can be obtained from the formula T = T + P x RthJA.
J
A
D
88/100
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ST6200C/ST6201C/ST6203C
11.3 SOLDERING AND GLUEABILITY INFORMATION
Recommended soldering information given only
as design guidelines in Figure 72 and Figure 73.
Recommended glue for SMD plastic packages:
■ Heraeus: PD945, PD955
■ Loctite: 3615, 3298
Figure 72. Recommended Wave Soldering Profile (with 37% Sn and 63% Pb)
250
COOLING PHASE
(ROOM TEMPERATURE)
5 sec
200
150
100
50
SOLDERING
PHASE
80°C
Temp. [°C]
PREHEATING
PHASE
Time [sec]
0
20
60
40
80
100
140
120
160
Figure 73. Recommended Reflow Soldering Oven Profile (MID JEDEC)
250
Tmax=220+/-5°C
for 25 sec
200
150
100
50
150 sec above 183°C
90 sec at 125°C
Temp. [°C]
ramp down natural
2°C/sec max
ramp up
2°C/sec for 50sec
Time [sec]
0
100
200
300
400
89/100
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ST6200C/ST6201C/ST6203C
11.4 PACKAGE/SOCKET FOOTPRINT PROPOSAL
Table 21. Suggested List of DIP16 Socket Types
Same
Footprint
Package / Probe
Adaptor / Socket Reference
216-33-40
Socket Type
Textool
DIP16
TEXTOOL
X
Table 22. Suggested List of SO16 Socket Types
Same
Footprint
Package / Probe
SO16
Adaptor / Socket Reference
Socket Type
ENPLAS
OTS-16-1.27-04
Open Top
Clamshell
YAMAICHI
IC51-347.KS-7704
Adapter from SO16 to DIP16 footprint
(delivered with emulator)
EMU PROBE
X
X
SMD to DIP
Open Top
Programming
Adapter
Logical Systems
PA16SO1-08H-6
Table 23. Suggested List of SSOP16 Socket Types
Same
Footprint
Package / Probe
SSOP16
Adaptor / Socket Reference
OTS-16-0.65-01
Socket Type
Open Top
ENPLAS
Adapter from SSOP16 to DIP16 footprint
(sales type: ST626X-P/SSOP16)
EMU PROBE
X
X
SMD to DIP
Programming
Adapter
Logical Systems
PA16SS-OT-6
Open Top
90/100
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ST6200C/ST6201C/ST6203C
11.5 ORDERING INFORMATION
The following section deals with the procedure for
transfer of customer codes to STMicroelectronics
and also details the ST6 factory coded device
type.
Figure 74. ST6 Factory Coded Device Types
ST62T03CB6/CCC
ROM code
Temperature code:
1: Standard 0 to +70 °C
3: Automotive -40 to +125 °C
6: Industrial -40 to +85 °C
Package type:
B: Plastic DIP
D: Ceramic DIP
M: Plastic SOP
N: Plastic SSOP
T: Plastic TQFP
Revision index:
B,C: Product Definition change
L: Low Voltage Device
ST6 Sub family
Version Code:
No char: ROM
E: EPROM
P: FASTROM
T: OTP
Family
91/100
1
ST6200C/ST6201C/ST6203C
11.6 TRANSFER OF CUSTOMER CODE
Customer code is made up of the ROM contents
and the list of the selected FASTROM options.
The ROM contents are to be sent on diskette, or
by electronic means, with the hexadecimal file
generated by the development tool. All unused
bytes must be set to FFh.
11.6.1 FASTROM version
The ST62P00C, P01C and P03C are the Factory
Advanced Service Technique ROM (FASTROM)
versions of ST62T00C, T01 and T03C OTP devic-
es.
They offer the same functionality as OTP devices,
but they do not have to be programmed by the
customer. The customer code must be sent to
STMicroelectronics in the same way as for ROM
devices. The FASTROM option list has the same
options as defined in the programmable option
byte of the OTP version. It also offers an identifier
option. If this option is enabled, each FASTROM
device is programmed with a unique 5-byte
number which is mapped at addresses 0F9Bh-
0F9Fh. The user must therefore leave these bytes
blanked.
The selected options are communicated to
STMicroelectronics using the correctly filled OP-
TION LIST appended. See page 94.
The STMicroelectronics Sales Organization will be
pleased to provide detailed information on con-
tractual points.
Listing Generation and Verification. When
STMicroelectronics receives the user’s ROM con-
tents, a computer listing is generated from it. This
listing refers exactly to the ROM contents and op-
tions which will be used to produce the specified
MCU. The listing is then returned to the customer
who must thoroughly check, complete, sign and
return it to STMicroelectronics. The signed listing
forms a part of the contractual agreement for the
production of the specific customer MCU.
The identification number is structured as follows:
0F9Bh
0F9Ch
0F9Dh
0F9Eh
0F9Fh
T0
T1
T2
T3
Test ID
with T0, T1, T2, T3 = time in seconds since 01/01/
1970 and Test ID = Tester Identifier.
92/100
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ST6200C/ST6201C/ST6203C
TRANSFER OF CUSTOMER CODE (Cont’d)
11.6.2 ROM VERSION
ROM Readout Protection. If the ROM READOUT
PROTECTION option is selected, a protection
fuse can be blown to prevent any access to the
program memory content.
The ST6200C, 01C and 03C are mask pro-
grammed ROM version of ST62T00C, T01 and
T03C OTP devices.
In case the user wants to blow this fuse, high volt-
They offer the same functionality as OTP devices,
selecting as ROM options the options defined in
the programmable option byte of the OTP version.
age must be applied on the V pin.
PP
Figure 76. Programming wave form
Figure 75. Programming Circuit
0.5s min
V
PP
100 µs max
5V
4.7µF
15
14V typ
10
100nF
5
V
V
DD
SS
V
PP
150 µs typ
PROTECT
14V
V
400mA
max
PP
100nF
ZPD15
15V
4mA typ
t
VR02001
VR02003
Note: ZPD15 is used for overvoltage protection
93/100
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ST6200C/ST6201C/ST6203C
TRANSFER OF CUSTOMER CODE (Cont’d)
ST6200C/01C/03C/P00C/P01C/P03C MICROCONTROLLER OPTION LIST
Customer:
Address:
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact:
Phone:
Reference:
STMicroelectronics references:
Device:
[ ] ST6200C (1 KB)
[ ] ST6201C (2 KB)
[ ] ST6203C (1 KB)
[ ] ST62P00C (1 KB)
[ ] ST62P01C (2 KB)
[ ] ST62P03C (1 KB)
Package:
[ ] Dual in Line Plastic
[ ] Small Outline Plastic with conditioning
[ ] Shrink Small Outline Plastic with conditioning
Conditioning option:
Temperature Range:
[ ] Standard (Tube)
[ ] Tape & Reel
[ ] 0°C to + 70°C
[ ] - 40°C to + 125°C
[ ] - 40°C to + 85°C
Marking:
[ ] Standard marking
[ ] Special marking (ROM only):
PDIP16 (9 char. max): _ _ _ _ _ _ _ _ _
SO16 (6 char. max): _ _ _ _ _ _
SSOP16 (10 char. max): _ _ _ _ _ _ _ _ _ _
Authorized characters are letters, digits, '.', '-', '/' and spaces only.
Oscillator Safeguard:
Watchdog Selection:
[ ] Enabled
[ ] Software Activation
[ ] Hardware Activation
[ ] Disabled
[ ] Disabled
NMI pull-up:
[ ] Enabled
Oscillator Selection:
[ ] Quartz crystal / Ceramic resonator
[ ] RC network
Readout Protection:
FASTROM:
[ ] Enabled
[ ] Disabled
ROM:
[ ] Enabled:
[ ] Fuse is blown by STMicroelectronics
[ ] Fuse can be blown by the customer
[ ] Disabled
Low Voltage Detector:
External STOP Mode Control:
Identifier (FASTROM only):
[ ] Enabled
[ ] Enabled
[ ] Enabled
[ ] Disabled
[ ] Disabled
[ ] Disabled
Comments:
Oscillator Frequency in the application:
Supply Operating Range in the application:
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Notes:
Date:
Signature:
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
94/100
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ST6200C/ST6201C/ST6203C
12 DEVELOPMENT TOOLS
STMicroelectronics offers a range of hardware
and software development tools for the ST6 micro-
controller family. Full details of tools available for
the ST6 from third party manufacturers can be ob-
tain from the STMicroelectronics Internet site:
➟ http://mcu.st.com.
Table 24. Dedicated Third Parties Development Tools
1)
Third Party
Designation
ST Sales Type
Web site address
ST-REALIZER II: Graphical Schematic
based Development available from
STMicroelectronics.
ACTUM
STREALIZER-II
http://www.actum.com/
Low cost emulator available from CEI-
BO.
http://www.ceibo.com/
CEIBO
This tool includes in the same environ-
ment: an assembler, linker, C compiler,
debugger and simulator. The assembler
package (plus limited C compiler) is free ST6RAIS-SWC/
http://www.raisonance.com/
RAISONANCE
and can be downloaded from raisonance
web site. The full version is available
both from STMicroelectronics and Raiso-
nance.
PC
High end emulator available from
SOFTEC.
SOFTEC
http://www.softecmicro.com/
Gang programmer available from
SOFTEC.
ADVANCED EQUIPMENT
ADVANCED TRANSDATA
BP MICROSYSTEMS
DATA I/O
http://www.aec.com.tw/
http://www.adv-transdata.com/
http://www.bpmicro.com/
http://www.data-io.com/
DATAMAN
http://www.dataman.com/
http://www.eetools.com/
http://www.elnec.com/
EE TOOLS
ELNEC
HI-LO SYSTEMS
ICE TECHNOLOGY
LEAP
http://www.hilosystems.com.tw/
http://www.icetech.com/
http://www.leap.com.tw/
http://www.lloyd-research.com/
Single and gang programmers
LLOYD RESEARCH
http://www.chipprogram-
mers.com/
LOGICAL DEVICES
MQP ELECTRONICS
http://www.mqp.com/
NEEDHAMS
ELECTRONICS
http://www.needhams.com/
http://www.stag.co.uk/
http://www.sg.com.tw
STAG PROGRAMMERS
SYSTEM GENERAL CORP
TRIBAL MICROSYSTEMS
XELTEK
http://www.tribalmicro.com/
http://www.xeltek.com/
Note 1: For latest information on third party tools, please visit our Internet site: ➟ http://mcu.st.com.
95/100
1
ST6200C/ST6201C/ST6203C
DEVELOPMENT TOOLS (Cont’d)
STMicroelectronics Tools
Four types of development tool are offered by ST, all of them connect to a PC via a parallel or serial port:
see Table 25 and Table 26 for more details.
Table 25. STMicroelectronics Tool Features
Emulation Type
Programming Capability
Software Included
MCU CD ROM with:
Device simulation (limited
ST6 Starter Kit
emulation as interrupts are Yes (DIP packages only)
not supported)
– Rkit-ST6 from Raisonance
– ST6 Assembly toolchain
In-circuit powerful emula-
tion features including
trace/ logic analyzer
– WGDB6 powerful Source Level
Debugger for Win 3.1, Win 95
and NT
– Various software demo ver-
sions.
ST6 HDS2 Emulator
No
ST6 EPROM
Programmer Board
Yes (All packages except
SSOP)
No
– Windows Programming Tools
for Win 3.1, Win 95 and NT
Table 26. Dedicated STMicroelectronics Development Tools
Supported Products
ST6 Starter Kit
ST6 HDS2 Emulator
ST6 Programming Board
Complete:
ST62GP-EMU2
ST6200C, 001C and 003C
ST622XC-KIT
ST62E2XC-EPB
Dedication board:
ST62GP-DBE
96/100
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ST6200C/ST6201C/ST6203C
13 ST6 APPLICATION NOTES
IDENTIFICATION
DESCRIPTION
MOTOR CONTROL
AN392
AN414
AN416
AN422
AN863
MICROCONTROLLER AND TRIACS ON THE 110/240V MAINS
CONTROLLING A BRUSH DC MOTOR WITH AN ST6265 MCU
SENSORLESS MOTOR DRIVE WITH THE ST62 MCU + TRIAC
IMPROVES UNIVERSAL MOTOR DRIVE
IMPROVED SENSORLESS CONTROL WITH THE ST62 MCU FOR UNIVERSAL MOTOR
BATTERY MANAGEMENT
AN417
FROM NICD TO NIMH FAST BATTERY CHARGING
AN433
ULTRA FAST BATTERY CHARGER USING ST6210 MICROCONTROLLER
AN859
AN INTELLIGENT ONE HOUR MULTICHARGER FOR Li-Ion, NiMH and NiCd BATTERIES
HOME APPLIANCE
AN674
MICROCONTROLLERS IN HOME APPLIANCES: A SOFT REVOLUTION
AN885
ST62 MICROCONTROLLERS DRIVE HOME APPLIANCE MOTOR TECHNOLOGY
GRAPHICAL DESIGN
AN676
BATTERY CHARGER USING THE ST6-REALIZER
AN677
PAINLESS MICROCONTROLLER CODE BY GRAPHICAL APPLICATION DESCRIPTION
ANALOG MULTIPLE KEY DECODING USING THE ST6-REALIZER
CODED LOCK USING THE ST6-REALIZER
AN839
AN840
AN841
A CLOCK DESIGN USING THE ST6-REALIZER
AN842
7 SEGMENT DISPLAY DRIVE USING THE ST6-REALIZER
COST REDUCTION
AN431
USING ST6 ANALOG INPUTS FOR MULTIPLE KEY DECODING
DIRECT SOFTWARE LCD DRIVE WITH ST621X AND ST626X
OPTIMIZING THE ST6 A/D CONVERTER ACCURACY
AN594
AN672
AN673
REDUCING CURRENT CONSUMPTION AT 32KHZ WITH ST62
DESIGN IMPROVEMENTS
AN420
AN432
AN434
AN435
AN669
AN670
AN671
AN911
AN975
AN1015
EXPANDING A/D RESOLUTION OF THE ST6 A/D CONVERTER
USING ST62XX I/O PORTS SAFELY
MOVEMENT DETECTOR CONCEPTS FOR NOISY ENVIRONMENTS
DESIGNING WITH MICROCONTROLLERS IN NOISY ENVIRONMENTS
SIMPLE RESET CIRCUITS FOR THE ST6
OSCILLATOR SELECTION FOR ST62
PREVENTION OF DATA CORRUPTION IN ST6 ON-CHIP EEPROM
ST6 MICRO IS EMC CHAMPION
UPGRADING FROM ST625X/6XB TO ST625X/6XC
SOFTWARE TECHNIQUES FOR IMPROVING ST6 EMC PERFORMANCE
PERIPHERAL OPERATIONS
AN590
AN591
AN592
AN593
AN678
PWM GENERATION WITH ST62 AUTO-RELOAD TIMER
INPUT CAPTURE WITH ST62 AUTO-RELOAD TIMER
PLL GENERATION USING THE ST62 AUTO-RELOAD TIMER
ST62 IN-CIRCUIT PROGRAMMING
LCD DRIVING WITH ST6240
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IDENTIFICATION
DESCRIPTION
AN913
PWM GENERATION WITH ST62 16-BIT AUTO-RELOAD TIMER
USING ST626X SPI AS UART
AN914
AN1016
AN1050
AN1127
GENERAL
ST6 USING THE ST623XB/ST628XB UART
ST6 INPUT CAPTURE WITH ST62 16-BIT AUTO-RELOAD TIMER
USING THE ST62T6XC/5XC SPI IN MASTER MODE
MCUS - 8/16-BIT MICROCONTROLLERS (MCUS) APPLICATION NOTES ABSTRACTS BY
TOPICS
AN683
AN886
AN887
AN898
AN899
AN900
AN901
AN902
AN912
AN1181
SELECTING BETWEEN ROM AND OTP FOR A MICROCONTROLLER
MAKING IT EASY WITH MICROCONTROLLERS
EMC GENERAL INFORMATION
SOLDERING RECOMMENDATIONS AND PACKAGING INFORMATION
INTRODUCTION TO SEMICONDUCTOR TECHNOLOGY
EMC GUIDE-LINES FOR MICROCONTROLLER - BASED APPLICATIONS
QUALITY AND RELIABILITY INFORMATION
A SIMPLE GUIDE TO DEVELOPMENT TOOLS
ELECTROSTATIC DISHARGE SENSITIVITY MEASUREMENT
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14 SUMMARY OF CHANGES
Description of the changes between the current release of the specification and the previous one.
Revision
Main Changes
Date
Pinout: Pin 10, TEST function is changed to non-user info. See Figure 2.
Modification of Caution in Section 3.1.6.1.
Addition of power consumption information in Section 3.3.
Addition of Note in Section 7.2.4.
3.1
15 Jan 2001
Modification of text (READ-MODIFY-WRITE instructions) in Section 7.2.5.
Modification of Section 8.2: 8-Bit Timer. Ext. Timer pin is not available.
Modification of bit names in ADCR and ADR registers in Section 8.3.
Modification of Electrical Characteristics in Section 10.2.1 (Add. of V
10.5.2 (Del. of tw and tr).
) and in Section
OUT
Removed “TEST” in Figure 1.
Updated Table 2 on page 11: CPU added for 0C8h and ROM added for 0C9h.
Changed bits 5:0 to bits 7:2 for T[5:0] bits (WDGR register on Section 8.1.7 on page 44)
Changed 4.5V≤V ≤5.5V to 4.5V≤V ≤6.0V (Section 10 on page 58).
DD
DD
Added one note on RC oscillator (Section 10.5.4 on page 70).
3.2
July 2001
Changed Figure 46 title on page 71 (vs V instead of vs R
).
DD
NET
Updated Electrical Sensitivities table on page 75.
Changed Section 11.6.1 on page 92.
Changed option list (page 94).
Updated Section 12 on page 95 and Section 13 on page 97.
15 TO GET MORE INFORMATION
To get the latest information on this product please use the STMicroelectronics web server.
➟ http://mcu.st.com/
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NOTES:
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
2001 STMicroelectronics - All Rights Reserved.
Purchase of I2C Components by STMicroelectronics conveys a license under the Philips I2C Patent. Rights to use these components in an
I2C system is granted provided that the system conforms to the I2C Standard Specification as defined by Philips.
STMicroelectronics Group of Companies
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http://www.st.com
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相关型号：
ST62T03CB6
8-bit MCUs with A/D converter two timers, oscillator safeguard & safe reset
STMICROELECTR
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