ST62T08B [STMICROELECTRONICS]
8-BIT OTP/EPROM MCU WITH LCD DRIVER, EEPROM AND A/D CONVERTER; 8位OTP / EPROM微控制器与LCD驱动器, EEPROM和A / D转换器型号: | ST62T08B |
厂家: | ST |
描述: | 8-BIT OTP/EPROM MCU WITH LCD DRIVER, EEPROM AND A/D CONVERTER |
文件: | 总78页 (文件大小:485K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ST62T80B/E80B
8-BIT OTP/EPROM MCU WITH LCD DRIVER,
EEPROM AND A/D CONVERTER
■ 3.0 to 6.0V Supply Operating Range
■ 8 MHz Maximum Clock Frequency
■ -40 to +85°C Operating Temperature Range
■ Run, Wait and Stop Modes
■ 5 Interrupt Vectors
■ Look-up Table capability in Program Memory
■ Data Storage in Program Memory:
User selectable size
■ Data RAM: 192 bytes
■ Data EEPROM: 128 bytes
■ User Programmable Options
■ 22 I/O pins, fully programmable as:
– Input with pull-up resistor
– Input without pull-up resistor
– Input with interrupt generation
– Open-drain or push-pull output
– Analog Input
PQFP100
■ 10 I/O lines can sink up to 20mA to drive LEDs
or TRIACs directly
■ One
8-bit
Timer/Counter
with
7-bit
programmable prescaler
■ One 8-bit Auto-Reload Timer with 7-bit
programmable prescaler (ARTimer)
■ Digital Watchdog
■ 8-bit A/D Converter with 12 analog inputs
■ 8-bit Synchronous Peripheral Interface (SPI)
■ 8-bit AsynchronousPeripheral Interface (UART)
■ LCD driver with 48 segment outputs, 8
CQFP100W
backplane outputs,
segment/backplane outputs and selectable
multiplexing ratio.
8 software selectable
(See end of Datasheet for Ordering Information)
■ 32kHz oscillator for stand-by LCD operation
■ On-chip Clockoscillator canbe driven by Quartz
Crystal or Ceramic resonator
DEVICE SUMMARY
■ One external Non-Maskable Interrupt
OTP
(Bytes)
EPROM
(Bytes)
DEVICE
LCD display
■ ST6280-EMU2 Emulation and Development
System (connects to an MS-DOS PC via a
parallel port).
ST62T80B
ST62E80B
7948
-
4 x 56 or 16 x 48
4 x 56 or 16 x 48
7948
Rev. 2.5
August 1999
1/78
1
Table of Contents
Document
Page
ST62T80B/E80B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2 PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.3 MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.3.2 Program Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.3.3 Data Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.3.4 Stack Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.3.5 Data Window Register (DWR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.3.6 Data RAM/EEPROM and LCD RAM Bank Register (DRBR) . . . . . . . . . . . . . . . . . . 12
1.3.7 EEPROM Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.4 PROGRAMMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.4.1 Option Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.4.2 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.4.3 EEPROM Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.4.4 EPROM Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . 18
3.1 CLOCK SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.1.1 Main Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.1.2 32 KHz STAND-BY OSCILLATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2 RESETS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.2.1 RESET Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.2.2 Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.2.3 Watchdog Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.2.4 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.2.5 MCU Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.3 DIGITAL WATCHDOG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.3.1 Digital Watchdog Register (DWDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.3.2 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.4 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.4.1 Interrupt request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.4.2 Interrupt Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.4.3 Interrupt Option Register (IOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.4.4 Interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.5 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.5.1 WAIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.5.2 STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.5.3 Exit from WAIT and STOP Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
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4 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.1 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.1.1 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.1.2 Safe I/O State Switching Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.1.3 ARTimer alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.1.4 SPI alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.1.5 UART alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.1.6 I/O Port Option Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.1.7 I/O Port Data Direction Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.1.8 I/O Port Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.2 TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.2.1 Timer Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.2.2 Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.2.3 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.3 AUTO-RELOAD TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.3.1 AR Timer Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.3.2 Timer Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.3.3 AR Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.4 U. A. R. T. (UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER) . . . . . . . . . . . 49
4.4.1 PORTS INTERFACING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.4.2 CLOCK GENERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.4.3 DATA TRANSMISSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.4.4 DATA RECEPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.4.5 INTERRUPT CAPABILITIES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.4.6 REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.5 A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.5.1 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.6 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.7 LCD CONTROLLER-DRIVER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.7.1 Multiplexing ratio and frame frequency setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
4.7.2 Segment and common plates driving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
4.7.3 Stand by or STOP operation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4.7.4 LCD Mode Control Register (LCDCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
5 SOFTWARE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
5.1 ST6 ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
5.2 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
5.3 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
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6 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6.1 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6.2 RECOMMENDED OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.3 DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
6.4 AC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
6.5 A/D CONVERTER CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
6.6 TIMER CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6.7 SPI CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6.8 LCD ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
7 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
7.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
7.2 PACKAGE THERMAL CHARACTERISTIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
7.3 .ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
ST6280B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
1.2 ROM READOUT PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
1.3 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
1.3.1 Transfer of Customer Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
1.3.2 Listing Generation and Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
78
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ST62T80B/E80B
1 GENERAL DESCRIPTION
1.1 INTRODUCTION
The ST62T80B and ST62E80B devices are low
cost members of the ST62xx 8-bit HCMOS family
of microcontrollers, which is targeted at low to me-
dium complexity applications. All ST62xx devices
are based on a building block approach: a com-
mon core is surrounded by a number of on-chip
peripherals.
The ST62E80B is the erasable EPROM version of
the ST62T80B device, which may be used to em-
ulate the ST62T80B device, as well as the respec-
tive ST6280B ROM devices.
Figure 1. Block Diagram
PA2..PA3 / 20mA Sink
PA4 / TIMER / 20mA Sink
PORT A
PORT B
PA5 / Scl / 20mA Sink
PA6 / Sin / 20mA Sink
PA7 / Sout / 20mA Sink
8-BIT
A/D CONVERTER
TEST/V
NMI
PP
TEST
PB0 / RXD / Ain
PB1 / TXD / Ain
PB2..PB5 / Ain
PB6 / ARTIMin/ Ain
PB7 / ARTIMout / Ain
INTERRUPT
ARTIMER
UART
DATA ROM
USER
SELECTABLE
PROGRAM
Memory
PC0..PC3 / 20mA Sink
PC4..PC7 / Ain
PORT C
DATA RAM
192 Bytes
7948 bytes
COM1..COM8
S9..S56
LCD DRIVER
COM9..COM16 / S1..S8
DATA EEPROM
128 Bytes
VLCD
VLCD1/5
VLCD2/5
VLCD3/5
VLCD4/5
PC
STACK LEVEL 1
STACK LEVEL 2
STACK LEVEL 3
STACK LEVEL 4
STACK LEVEL 5
STACK LEVEL 6
OSC32in
OSC32out
OSC 32kHz
TIMER
8 BIT CORE
DIGITAL
WATCHDOG
SPI (SERIAL
PERIPHERAL
INTERFACE)
POWER
SUPPLY
RESET
RESET
OSCILLATOR
V
V
OSCin OSCout
DD SS
VA0479
(V on EPROM/OTP versions only)
PP
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ST62T80B/E80B
INTRODUCTION (Cont’d)
OTP and EPROM devices are functionally identi-
cal. The ROM based versions offer the same func-
tionality selecting as ROM options the options de-
fined in the programmable option byte of the
OTP/EPROM versions.OTP devices offer all the
advantages of user programmability at low cost,
which make them the ideal choice in a wide range
of applications where frequent code changes, mul-
tiple code versions or last minute programmability
are required.
These compact low-cost devices feature one Tim-
er comprising an 8-bit counter and a 7-bit pro-
grammable prescaler, one 8-bit autoreload timer
with 7-bit programmable prescaler (ARTimer),
EEPROM data capability, a serial synchronous
port interface (SPI), an 8-bit A/D Converter with 12
analog inputs, a Digital Watchdog timer, and a
complete LCD controller driver, making them well
suited for a wide range of automotive, appliance
and industrial applications.
Figure 2. ST6280B Pin Description
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
S39
S40
S41
S42
S43
S44
S45
S46
S47
S48
S49
S50
S51
S52
S53
S54
S55
1
2
3
4
5
6
7
8
S18
S17
S16
S15
S14
S13
S12
S11
9
S10
S9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
COM16/S8
COM15/S7
COM14/S6
COM13/S5
COM12/S4
COM11/S3
COM10/S2
COM9/S1
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
OSC32in
OSC32out
PA2*
S56
PB7/ARTIMout/Ain
PB6/ARTIMin/Ain
PB5/Ain
PB4/Ain
PB3/Ain
PB2/Ain
PB1/Ain
PB0/Ain
TEST
OSCout
OSCin
RESET
PA3*
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
*Note: 20mA Sink
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ST62T80B/E80B
1.2 PIN DESCRIPTIONS
and V . Power is supplied to the MCU via
V
and PB7/ARTIMout are either Port B I/O bits or the
input and output of the ARTimer. PB0 (resp. PB1)
can also be used as reception (resp. transmission)
line for the embedded UART.
DD
SS
these two pins. V is the power connection and
DD
V
is the ground connection.
SS
OSCin and OSCout. These pins are internally
connected to the on-chip oscillator circuit. A quartz
crystal, a ceramic resonator or an external clock
signal can be connected between these two pins.
The OSCin pin is the input pin, the OSCout pin is
the output pin.
PC0-PC7. These 8 lines are organised as one I/O
port (C). Each line may be configured under soft-
ware control as input with or without internal pull-
up resistor, interrupt generating input with pull-up
resistor, open-drain or push-pull output, or analog
imputs for the A/D Converter. PC0-PC3 can sink
20mA for direct LED or TRIAC drive, while PC4-
PC7 can be used as analog inputs for the A/D
Converter.
RESET. The active-low RESET pin is used to re-
start the microcontroller.
TEST/VPP. The TEST must be held at VSS for nor-
mal operation. If TEST pin is connected to a
+12.5V level during the reset phase, the
EPROM/OTP programming Mode is entered.
COM1-COM8. These eight pins are the LCD pe-
ripheral common outputs. They are the outputs of
the on-chip backplane voltage generator which is
used for multiplexing the LCD lines.
NMI. The NMI pin provides the capability for asyn-
chronous interruption, by applying an external non
maskable interrupt to the MCU. The NMI input is
falling edge sensitive with Schmitt trigger charac-
teristics. The user can select as option the availa-
bility of an on-chip pull-up at this pin.
COM9/S1-COM16/S8. These pins are the 8 multi-
plexed common/segment lines. Under software
selected control, they can act as LCD common
outputs allowing a 48 x 16 dot matrix operation, or
they can act as segment outputs alowwing 56 x 8
dot matrix operation.
PA2-PA7. These 6 lines are organised as one I/O
port (A). Each line may be configured under soft-
ware control as inputs with or without internal pull-
up resistors, interrupt generating inputs with pull-
up resistors, open-drain or push-pull outputs,
PA5/SCL, PA6/Sin and PA7/Sout can be used re-
spectively as data clock, data in and clock pins for
the on-chip SPI, while PA4/TIMER can be used as
Timer I/O. In addition, PA2-PA7 can sink 20mA for
direct LED or TRIAC drive.
S9-S56. These pins are the 48 LCD peripheral
segment outputs.
VLCD1/5, VLCD5/5. Display supply voltage inputs
for determining the display voltage levels on
common and segment pins during multiplex oper-
ation.
OSC32in and OSC32out. These pins are inter-
nally connected with the on-chip 32kHz oscillator
circuit. A 32.768kHz quartz crystal can be con-
nected between these two pins if it is necessary to
provide the LCD stand-by clock and real time inter-
rupt. OSC32in is the input pin, OSC32out is the
output pin.
PB0...PB7. These 8 lines are organised as one I/O
port (B). Each line may be configured under soft-
ware control as inputs with or without internal pull-
up resistors, interrupt generating inputs with pull-
up resistors, open-drain or push-pull outputs, an-
alog inputs for the A/D converter. PB6/ARTIMin
7/78
7
ST62T80B/E80B
1.3 MEMORY MAP
1.3.1 Introduction
common (STATIC) 2K page is available all the
time for interrupt vectors and common subrou-
tines, independently of the PRPR register content.
This “STATIC” page is directly addressed in the
0800h-0FFFh by the MSB of the Program Counter
register PC 11. Note this page can also be ad-
dressed in the 000-7FFh range. It is two different
ways of addressing the same physical memory.
The MCU operates in three separate memory
spaces: Program space, Data space, and Stack
space. Operation in these three memory spaces is
described in the following paragraphs.
Briefly, Program space contains user program
code in Program memory and user vectors; Data
space contains user data in RAM and in Program
memory, and Stack space accommodates six lev-
els of stack for subroutine and interrupt service
routine nesting.
Jump from a dynamic page to another dynamic
page is achieved by jumping back to the static
page, changing contents of PRPR and then jump-
ing to the new dynamic page.
1.3.2 Program Space
Figure 3. 8Kbytes Program Space Addressing
Program Space comprises the instructions to be
executed, the data required for immediate ad-
dressing mode instructions, the reserved factory
test area and the user vectors. Program Space is
addressed via the 12-bit Program Counter register
(PC register).
ROM SPACE
PC
1FFFh
Page 3
SPACE
000h
0000h
Page 1
Static
Page
Page 0
Page 2
7FFh
800h
Program Space is organised in four 2K pages.
Three of them are addressed in the 000h-7FFh lo-
cations of the Program Space by the Program
Counter and by writing the appropriate code in the
Program ROM Page Register (PRPR register). A
Page 1
Static
Page
FFFh
Figure 4. Memory Addressing Diagram
PROGRAM SPACE
DATA SPACE
0000h
000h
RAM / EEPROM
BANKING AREA
0-63
03Fh
040h
DATA READ-ONLY
WINDOW
MEMORY
PROGRAM
MEMORY
07Fh
080h
081h
082h
083h
084h
X REGISTER
Y REGISTER
V REGISTER
W REGISTER
RAM
DATA READ-ONLY
MEMORY
WINDOW SELECT
0C0h
0FF0h
DATA RAM
INTERRUPT &
RESET VECTORS
0FFFh
BANK SELECT
ACCUMULATOR
0FFh
VR01568
8/78
8
ST62T80B/E80B
MEMORY MAP (Cont’d)
Table 1. ST62E80B/T80B Program MemoryMap
to the image register. The image register must be
written before PRPR, so if an interrpt occurs be-
tween the two instructions the PRPR is not af-
fected.
ROM Page Device Address
Description
0000h-007Fh
Page 0
Reserved
User ROM
0080h-07FFh
Program ROM Page Register (PRPR)
0800h-0F9Fh
0FA0h-0FEFh
0FF0h-0FF7h
0FF8h-0FFBh
0FFCh-0FFDh
0FFEh-0FFFh
User ROM
Reserved
Interrupt Vectors
Reserved
NMI Vector
Reset Vector
Address: CAh
7
— Write Only
Page 1
“STATIC”
0
-
-
-
-
-
-
PRPR1 PRPR0
0000h-000Fh
0010h-07FFh
Reserved
User ROM
Page 2
Page 3
Bits 2-7= Not used.
0000h-000Fh
0010h-07FFh
Reserved
User ROM
Bit 5-0 = PRPR1-PRPR0: Program ROM Select.
These two bits select the corresponding page to
be addressed in the lower part of the 4K program
address space as specified in Table 2.
Note: OTP/EPROM devices can be programmed
with thedevelopment toolsavailable fromSTMicro-
electronics (ST62E8X-EPB).
This register is undefined on Reset. Neither read
nor single bit instructions may be used to address
this register.
1.3.2.1 Program ROM Page Register (PRPR)
Table 2. 8Kbytes Program ROM Page Register
Coding
The PRPR register can be addressed like a RAM
location in the Data Space at the address CAh ;
nevertheless it is a write only register that cannot
be accessed with single-bit operations. This regis-
ter is used to select the 2-Kbyte ROM bank of the
Program Space that will be addressed. The
number of the page has to be loaded in the PRPR
register. Refer to the Program Space description
for additional information concerning the use of
this register. The PRPR register is not modified
when an interrupt or a subroutine occurs.
PRPR1
PRPR0 PC bit 11
Memory Page
Static Page (Page 1)
Page 0
X
0
0
1
1
X
0
1
0
1
1
0
0
0
0
Page 1 (Static Page
Page 2
Page 3
1.3.2.2 Program Memory Protection
The Program Memory in OTP or EPROM devices
can be protected against external readout of mem-
ory by selecting the READOUT PROTECTION op-
tion in the option byte.
Care is required when handling the PRPR register
as it is write only. For this reason, it is not allowed
to change the PRPR contents while executing in-
terrupt service routine, as the service routine
cannot save and then restore its previous content.
This operation may be necessary if common rou-
tines and interrupt service routines take more than
2K bytes ; in this case it could be necessary to di-
vide the interrupt service routine into a (minor) part
in the static page (start and end) and to a second
(major) part in one of the dynamic pages. If it is im-
possible to avoid the writing of this register in inter-
rupt service routines, an image of this register
must be saved in a RAM location, and each time
the program writes to the PRPR it must write also
In the EPROM parts, READOUT PROTECTION
option can be disactivated only by U.V. erasure
that also results into the whole EPROM context
erasure.
Note: Once the Readout Protection is activated, it
is no longer possible, even for STMicroelectronics,
to gain access to the Program memory contents.
Returned parts with a protection set can therefore
not be accepted.
9/78
9
ST62T80B/E80B
MEMORY MAP (Cont’d)
1.3.3 Data Space
Table 4. ST62T80B/E80B Data Memory Space
000h
DATA RAM/EEPROM, LCD RAM
03Fh
Data Space accommodates all the data necessary
for processing the user program. This space com-
prises the RAM resource, the processor core and
peripheral registers, as well as read-only data
such as constants and look-up tables in Program
memory.
040h
DATA ROM WINDOW AREA
07Fh
X REGISTER
Y REGISTER
V REGISTER
W REGISTER
080h
081h
082h
083h
084h
0BFh
0C0h
0C1h
0C2h
0C3h
0C4h
0C5h
0C6h
0C7h
0C8h*
0C9h*
0CAh*
1.3.3.1 Data ROM
DATA RAM
All read-only data is physically stored in program
memory, which also accommodates the Program
Space. The program memory consequently con-
tains the program code to be executed, as well as
the constants and look-up tables required by the
application.
PORT A DATAREGISTER
PORT B DATAREGISTER
SPI INTERRUPT DISABLE REGISTER
PORT C DATAREGISTER
PORT A DIRECTION REGISTER
PORT B DIRECTION REGISTER
PORT C DIRECTION REGISTER
RESERVED
INTERRUPT OPTION REGISTER
DATAROM WINDOW REGISTER
ROM BANK SELECT REGISTER
The Data Space locations in which the different
constants and look-up tables are addressed by the
processor core may be thought of as a 64-byte
window through which it is possible to access the
read-only data stored in Program memory.
DATARAM/EEPROM, LCD BANK SELECT REGISTER 0CBh*
1.3.3.2 Data RAM/EEPROM
PORT A OPTION REGISTER
RESERVED
PORT B OPTION REGISTER
PORT C OPTION REGISTER
A/D DATA REGISTER
0CCh
0CDh
0CEh
0CFh
0D0h
0D1h
0D2h
0D3h
0D4h
0D5h
0D6h
0D7h
0D8h
0D9h
0DAh
0DBh
0DCh
0DDh
0DEh
0DFh
0E0h
In ST62T80B and ST62E80B devices, the data
space includes 60 bytes of RAM, the accumulator
(A), the indirect registers (X), (Y), the short direct
registers (V), (W), the I/O port registers, the pe-
ripheral data and control registers, the interrupt
option register and the Data ROM Window register
(DRW register).
A/D CONTROL REGISTER
TIMER 1 PRESCALER REGISTER
TIMER 1 COUNTER REGISTER
TIMER 1 STATUS/CONTROL REGISTER
RESERVED
Additional RAM and EEPROM pages can also be
addressed using banks of 64 bytes located be-
tween addresses 00h and 3Fh.
UART DATA REGISTER
UART CONTROL REGISTER
WATCHDOG REGISTER
1.3.4 Stack Space
RESERVED
Stack space consists of six 12-bit registers which
are used to stack subroutine and interrupt return
addresses, as well as the current program counter
contents.
32kHz OSCILLATOR CONTROL REGISTER
LCD MODE CONTROL REGISTER
SPI DATAREGISTER
RESERVED
EEPROM CONTROL REGISTER
Table 3. Additional RAM/EEPROM Banks.
RESERVED
Device
RAM
EEPROM LCD RAM
0E4h
0E5h
0E6h
0E7h
ST62T80B/E80B 2 x 64 bytes 2 x 64 bytes 2 x 64 bytes
ARTIMER MODE/CONTROL REGISTER
ARTIMER STATUS/CONTROL REGISTER 0
ARTIMER STATUS/CONTROL REGISTER 1
RESERVED
ARTIMER RELOAD/CAPTURE REGISTER
ARTIMER COMPARE REGISTER
ARTIMER LOAD REGISTER
0E9h
0EAh
0EBh
0ECh
RESERVED
0FEh
OFFh
ACCUMULATOR
* WRITE ONLY REGISTER
10/78
10
ST62T80B/E80B
MEMORY MAP (Cont’d)
1.3.5 Data Window Register (DWR)
Data Window Register (DWR)
Address: 0C9h
— Write Only
The Data read-only memory windowislocatedfrom
address 0040h to address 007Fh in Data space. It
allows direct reading of 64 consecutive bytes locat-
ed anywhere in program memory, between ad-
dress 0000h and 1FFFh (top memory address de-
pends on the specific device). All the program
memory can therefore be used to store either in-
structions or read-only data. Indeed, the window
can be moved in steps of 64 bytes along the pro-
gram memoryby writing theappropriate code in the
Data Window Register (DWR).
7
0
-
DWR6 DWR5 DWR4 DWR3 DWR2 DWR1 DWR0
Bits 7 = Not used.
Bit 6-0 = DWR6-DWR0: Data read-only memory
Window Register Bits. These are the Data read-
only memory Window bits that correspond to the
upper bits of the data read-only memory space.
The DWR can beaddressed like any RAM location
in the Data Space, it is however a write-only regis-
ter and therefore cannot be accessed using single-
bit operations. This register is used to position the
64-byte read-only data window (from address 40h
to address 7Fh of the Data space) in program
memory in 64-byte steps. The effective address of
the byte to be read as data in program memory is
obtained by concatenating the 6 least significant
bits of the register address given in the instruction
(as least significant bits) and the content of the
DWR register (as most significant bits), as illustrat-
ed in Figure 5 below. For instance, when address-
ing location 0040h of the Data Space, with 0 load-
ed in the DWR register, the physical location ad-
dressed inprogram memory is 00h. The DWR reg-
ister is not cleared on reset, therefore it must be
written to prior to the first access to the Data read-
only memory window area.
Caution: This register is undefined on reset. Nei-
ther read nor single bit instructions may be used to
address this register.
Note: Care is required when handling the DWR
register as it is write only. For this reason, the
DWR contents should not be changed while exe-
cuting an interrupt service routine, as the service
routine cannot save and then restore the register’s
previous contents. If it is impossible to avoid writ-
ing to the DWR during the interrupt service routine,
an image of the register must be saved in a RAM
location, and each time the program writes to the
DWR, it must also write to the image register. The
image register must be written first so that, if an in-
terrupt occurs between the two instructions, the
DWR is not affected.
Figure 5. Data read-only memory Window Memory Addressing
13 12 11 10
9
3
8
2
7
1
6
0
5
4
3
2
1
1
0 PROGRAM SPACE ADDRESS
READ
DATA ROM
WINDOW REGISTER
CONTENTS
7
6
5
4
5
4
3
2
0
DATA SPACE ADDRESS
40h-7Fh
(DWR)
0
1
IN INSTRUCTION
Example:
DWR=28h
0
0
1
0
0
1
0
0
0
0
0
1
DATA SPACE ADDRESS
59h
0
0
1
1
1
0
0
0
0
1
ROM
ADDRESS:A19h
0
0
1
1
1
1
VR0A1573
11/78
11
ST62T80B/E80B
MEMORY MAP (Cont’d)
1.3.6 Data RAM/EEPROM and LCD RAM Bank
Register (DRBR)
point to the selected location as if it was in bank 0
(from 00h address to 3Fh address).
This register is not cleared during the MCU initiali-
zation, therefore it must be written before the first
access to the Data Space bank region. Refer to
the Data Space description for additional informa-
tion. The DRBR register is not modified when an
interrupt or a subroutine occurs.
Address: CBh — Write only
7
-
0
DRBR6
DRBR5
DRBR4
DRBR3
-
DRBR1 DRBR0
Notes :
Bit 7 = This bit is not used
Care is required when handling the DRBR register
as it is write only. For this reason, it is not allowed
to change the DRBR contents while executing in-
terrupt service routine, as the service routine can-
not save and then restore its previous content. If it
is impossible to avoid the writing of this register in
interrupt service routine, an image of this register
must be saved in a RAM location, and each time
the program writes to DRBR it must write also to
the image register. The image register must be
written first, so if an interrupt occurs between the
two instructions the DRBR is not affected.
Bit 6 - DRBR6. This bit, when set, selects LCD
RAM Page 2.
Bit 5 - DRBR5. This bit, when set, selects LCD
RAM Page 1.
Bit 4 - DRBR4. This bit, when set, selects RAM
Page 2.
Bit 3 - DRBR3. This bit, when set, selects RAM
Page 1.
Bit2. These bits are not used.
Bit 1 - DRBR1. This bit, when set, selects
EEPROM Page 1.
In DRBR Register, only 1 bit must be set. Other-
wise two or more pages are enabled in parallel,
producing errors.
Bit 0 - DRBR0. This bit, when set, selects
EEPROM Page 0.
Table 5. Data RAM Bank Register Set-up
The selection of the bank is made by programming
the Data RAM Bank Switch register (DRBR regis-
ter) located at address CBh of the Data Space ac-
cording to Table 1. No more than one bank should
be set at a time.
DRBR
00
ST62T80B/E80B
None
01
EEPROM Page 0
EEPROM Page 1
RAM Page 1
The DRBR register can be addressed like a RAM
Data Space at the address CBh; nevertheless it is
a write only register that cannot be accessed with
single-bit operations. This register is used to select
the desired 64-byte RAM/EEPROM bank of the
Data Space. The number of banks has to be load-
ed in the DRBR register and the instruction has to
02
08
10h
20h
40h
other
RAM Page 2
LCD RAM Page 1
LCD RAM Page 2
Reserved
12/78
12
ST62T80B/E80B
MEMORY MAP (Cont’d)
1.3.7 EEPROM Description
(PMODE). In BMODE, one byte is accessed at a
time, while in PMODE up to 8 bytes in the same
row are programmed simultaneously (with conse-
quent speed and power consumption advantages,
the latter being particularly important in battery
powered circuits).
EEPROM memory is located in 64-byte pages in
data space. This memory may be used by the user
program for non-volatile data storage.
Data space from 00h to 3Fh is paged as described
in Table 6. EEPROM locations are accessed di-
rectly by addressing these paged sections of data
space.
General Notes:
Data should be written directly to the intended ad-
dress in EEPROM space. There is no buffer mem-
ory between data RAM and the EEPROM space.
The EEPROM does not require dedicated instruc-
tions forreadorwrite access. Onceselectedvia the
Data RAM Bank Register, the active EEPROM
page is controlled by the EEPROM Control Regis-
ter (EECTL), which is described below.
When the EEPROM is busy (E2BUSY = “1”)
EECTL cannot be accessed in write mode, it is
only possible to read the status of E2BUSY. This
implies that as long as the EEPROM is busy, it is
not possible to change the status of the EEPROM
Control Register. EECTL bits 4 and 5 are reserved
and must never be set.
Bit E20FFof the EECTL registermust beresetprior
to any write or read access to the EEPROM. If no
bank hasbeen selected, orif E2OFF is set, any ac-
cess is meaningless.
Care is required when dealing withthe EECTL reg-
ister, as some bits are write only. For this reason,
the EECTL contents must not be altered while ex-
ecuting an interrupt service routine.
Programming must be enabled by setting the
E2ENA bit of the EECTL register.
The E2BUSY bit of the EECTL register is set when
the EEPROM is performing a programming cycle.
Any access to the EEPROM when E2BUSY is set
is meaningless.
If it is impossible to avoid writing to this register
within an interrupt service routine, an image of the
register must be saved in a RAM location, and
each time the program writes to EECTL it must
also write to the image register. The image register
must be written to first so that, if an interrupt oc-
curs between the two instructions, the EECTL will
not be affected.
Provided E2OFF and E2BUSY are reset, an EEP-
ROM location is read just like any other data loca-
tion, also in terms of access time.
Writing to the EEPROM may be carried out in two
modes: Byte Mode (BMODE) and Parallel Mode
Table 6. Row Arrangement for Parallel Writing of EEPROM Locations
Dataspace
addresses.
Banks 0 and 1.
Byte
0
1
2
3
4
5
6
7
ROW7
ROW6
ROW5
ROW4
ROW3
ROW2
ROW1
ROW0
38h-3Fh
30h-37h
28h-2Fh
20h-27h
18h-1Fh
10h-17h
08h-0Fh
00h-07h
Up to 8 bytes in each row may be programmed simultaneously in Parallel Write mode.
The number of available 64-byte banks (1 or 2) is device dependent.
13/78
13
ST62T80B/E80B
MEMORY MAP (Cont’d)
Additional Notes on Parallel Mode:
EEPROM Control Register (EECTL)
Address: DFh Read/Write
If the user wishes to perform parallel program-
ming, the first step should be to set the E2PAR2
bit. From this time on, the EEPROM will be ad-
dressed in write mode, the ROW address will be
latched and it will be possible to change it only at
the end of the programming cycle, or by resetting
E2PAR2 without programming the EEPROM. Af-
ter the ROW address is latched, the MCU can only
“see” the selected EEPROM row and any attempt
to write or read other rows will produce errors.
—
Reset status: 00h
7
0
D7 E2OFF D5
D4 E2PAR1 E2PAR2 E2BUSY E2ENA
Bit 7 = D7: Unused.
Bit 6= E2OFF: Stand-by EnableBit. WRITE ONLY.
If thisbit is settheEEPROM isdisabled(anyaccess
will bemeaningless) and the power consumption of
the EEPROM is reduced to its lowest value.
The EEPROM should not be read while E2PAR2
is set.
As soon as the E2PAR2 bit is set, the 8 volatile
ROW latches are cleared. From this moment on,
the user can load data in all or in part of the ROW.
Setting E2PAR1 will modify the EEPROM regis-
ters corresponding to the ROW latches accessed
after E2PAR2. For example, if the software sets
E2PAR2 and accesses the EEPROM by writing to
addresses 18h, 1Ah and 1Bh, and then sets
E2PAR1, these three registers will be modified si-
multaneously; the remaining bytes in the row will
be unaffected.
Bit 5-4 = D5-D4: Reserved. MUST be kept reset.
Bit 3 = E2PAR1: Parallel Start Bit. WRITE ONLY.
Once inParallelMode,as soonas theuser software
sets the E2PAR1 bit, parallel writing of the 8 adja-
cent registers will start. This bit is internally reset at
the end of the programming procedure. Note that
less than 8 bytes can be written if required, the un-
defined bytes being unaffected by the parallel pro-
gramming cycle;this is explained in greater detail in
the Additional Notes on Parallel Mode overleaf.
Note that E2PAR2 is internally reset at the end of
the programming cycle. This implies that the user
must set the E2PAR2 bit between two parallel pro-
gramming cycles. Note that if the user tries to set
E2PAR1 while E2PAR2 is not set, there will be no
programming cycle and the E2PAR1 bit will be un-
affected. Consequently, the E2PAR1 bit cannot be
set if E2ENA is low. The E2PAR1 bit can be set by
the user, only if the E2ENA and E2PAR2 bits are
also set.
Bit 2 = E2PAR2: Parallel Mode En. Bit. WRITE
ONLY. This bit must be set by the user program in
order to perform parallel programming. If E2PAR2
is set and the parallel start bit (E2PAR1) is reset,
up to 8 adjacent bytes can be written simultane-
ously. These 8 adjacent bytes are considered as a
row, whose address lines A7, A6, A5, A4, A3 are
fixed while A2, A1 and A0 are the changing bits, as
illustrated in Table 6. E2PAR2 is automatically re-
set at the end of any parallel programming proce-
dure. It can be reset by the user software before
starting the programming procedure, thus leaving
the EEPROM registers unchanged.
Bit 1 = E2BUSY: EEPROM Busy Bit. READ ON-
LY. This bit is automatically set by the EEPROM
control logic when the EEPROM is in program-
ming mode. The user program should test it before
any EEPROM read or write operation; any attempt
to access the EEPROM while the busy bit is set
will be aborted and the writing procedure in
progress will be completed.
Bit 0 = E2ENA: EEPROM Enable Bit. WRITE ON-
LY. This bit enables programming of the EEPROM
cells. It must be set before any write to the EEP-
ROM register. Any attempt to write to the EEP-
ROM when E2ENA is low is meaningless and will
not trigger a write cycle.
14/78
14
ST62T80B/E80B
1.4 PROGRAMMING MODES
1.4.1 Option Byte
1.4.2 Program Memory
The Option Byte allows configuration capability to
the MCUs. Option byte’s content is automatically
read, and the selected options enabled, when the
chip reset is activated.
EPROM/OTP programming mode is set by a
+12.5V voltage applied to the TEST/V pin. The
PP
programming flow of the ST62T80B/E80B is de-
scribed in the User Manual of the EPROM Pro-
gramming Board.
It can only be accessed during the programming
mode. This access is made either automatically
(copy from a master device) or by selecting the
OPTION BYTE PROGRAMMING modeof the pro-
grammer.
The MCUs can be programmed with the
ST62E8xB EPROM programming tools available
from STMicroelectronics.
1.4.3 EEPROM Data Memory
The option byte is located in a non-user map. No
address has to be specified.
EEPROM data pages are supplied in the virgin
state FFh. Partial or total programming of EEP-
ROM data memory can be performed either
through the application software, or through an ex-
ternal programmer. Any STMicroelectronics tool
used for the program memory (OTP/EPROM) can
also be used to program the EEPROM data mem-
ory.
EPROM Code Option Byte
7
-
0
-
PRO-
TECT
NMI
PULL
-
-
-
WDACT
1.4.4 EPROM Erasing
Bit 7-5. Reserved.
The EPROM of the windowed package of the
MCUs may be erased by exposure to Ultra Violet
light. The erasure characteristic of the MCUs is
such that erasure begins when the memory is ex-
posed to light with a wave lengths shorter than ap-
proximately 4000Å. It should be noted that sun-
lights and some types of fluorescent lamps have
wavelengths in the range 3000-4000Å.
Bit 5= PROTECT. This bit allows the protection of
the software contents against piracy. When the bit
PROTECT is set high, readout of the OTP con-
tents is prevented by hardware. No programming
equipment is able to gain access to the user pro-
gram. When this bit is low, the user program can
be read.
Bit 4. Reserved.
It is thus recommended that the window of the
MCUs packages be covered by an opaque label to
prevent unintentional erasure problems when test-
ing the application in such an environment.
Bit 3 = NMI PULL. . This bit must be set high to en-
able the internal pull-up resistor. When low, no
pull-up is provided.
The recommended erasure procedure of the
MCUs EPROM is the exposure to short wave ul-
traviolet light which have a wave-length 2537A.
The integrated dose (i.e. U.V. intensity x exposure
time) for erasure should be a minimum of 15W-
Bit 2. Reserved.
Bit 1 = WDACT. This bit controls the watchdog ac-
tivation. When it is high, hardware activation is se-
lected. The software activation is selected when
WDACT is low.
2
sec/cm . The erasure time with this dosage is ap-
proximately 15 to 20 minutes using an ultraviolet
2
Bit 0 = Reserved.
lamp with 12000µW/cm power rating. The
ST62E80B should be placed within 2.5cm (1Inch)
of the lamp tubes during erasure.
The Option byte is written during programming ei-
ther by using the PC menu (PC driven Mode) or
automatically (stand-alone mode)
15/78
15
ST62T80B/E80B
2 CENTRAL PROCESSING UNIT
2.1 INTRODUCTION
The CPUCoreof ST6 devicesis independent of the
I/O or Memory configuration. As such, it may be
thought of as an independent central processor
communicating with on-chip I/O, Memory and Pe-
ripherals via internal address, data, and control
buses. In-core communication is arranged as
shown in Figure 6; the controller being externally
linked to both the Reset and Oscillator circuits,
while thecore is linked to the dedicated on-chip pe-
ripherals via the serial data bus and indirectly, for
interrupt purposes, through the control registers.
Indirect Registers (X, Y). These two indirect reg-
isters are used as pointers to memory locations in
Data space. They are used in the register-indirect
addressing mode. These registers can be ad-
dressed in the data space as RAM locations at ad-
dresses 80h (X) and 81h (Y). They can also be ac-
cessed with the direct, short direct, or bit direct ad-
dressing modes. Accordingly, the ST6 instruction
set can use the indirect registers as any other reg-
ister of the data space.
Short Direct Registers (V, W). These two regis-
ters are used to save a byte in short direct ad-
dressing mode. They can be addressed in Data
space as RAM locations at addresses 82h (V) and
83h (W). They can also be accessed using the di-
rect and bit direct addressing modes. Thus, the
ST6 instruction set can use the short direct regis-
ters as any other register of the data space.
2.2 CPU REGISTERS
The ST6Family CPUcorefeatures sixregistersand
three pairs of flags available to the programmer.
These are described in the following paragraphs.
Accumulator (A). The accumulator is an 8-bit
general purpose register used in all arithmetic cal-
culations, logical operations, and data manipula-
tions. The accumulator can be addressed in Data
space as a RAM location at address FFh. Thus the
ST6 can manipulate the accumulator just like any
other register in Data space.
Program Counter (PC). The program counter is a
12-bit register which contains the address of the
next ROM location to be processed by the core.
This ROM location may be an opcode, an oper-
and, or the address of an operand. The 12-bit
length allows the direct addressing of 4096 bytes
in Program space.
Figure 6. ST6 Core Block Diagram
0,01 TO 8MHz
RESET
OSCin
OSCout
INTERRUPTS
CONTROLLER
DATA SPACE
DATA
CONTROL
SIGNALS
FLAG
VALUES
OPCODE
ADDRESS/READ LINE
ADDRESS
2
RAM/EEPROM
PROGRAM
DATA
ROM/EPROM
256
ROM/EPROM
DECODER
B-DATA
A-DATA
DEDICATIONS
ACCUMULATOR
Program Counter
and
12
FLAGS
6 LAYER STACK
ALU
RESULTS TO DATA SPACE (WRITE LINE)
VR01811
16/78
16
ST62T80B/E80B
CPU REGISTERS (Cont’d)
However, if the program space contains more than
4096 bytes, the additional memory in program
space can be addressed by using the Program
Bank Switch register.
automatically selected after the reset of the MCU,
the ST6 core uses at first the NMI flags.
Stack. The ST6 CPU includes a true LIFO hard-
ware stack which eliminates the need for a stack
pointer. The stack consists of six separate 12-bit
RAM locations that do not belong to the data
space RAM area. When a subroutine call (or inter-
rupt request) occurs, the contents of each level are
shifted into the next higher level, while the content
of the PC is shifted into the first level (the original
contents of the sixth stack level are lost). When a
subroutine or interrupt return occurs (RET or RETI
instructions), the first level register is shifted back
into the PC and the value of each level is popped
back into the previous level. Since the accumula-
tor, in common with all other data space registers,
is not stored in this stack, management of these
registers should be performed within the subrou-
tine. The stack will remain in its “deepest” position
if more than 6 nested calls orinterrupts are execut-
ed, and consequently the last return address will
be lost. It will also remain in its highest position if
the stack is empty and a RET or RETI is executed.
In this case the next instruction will be executed.
The PC value is incremented after reading the ad-
dress of the current instruction. To execute relative
jumps, the PC and the offset are shifted through
the ALU, where they are added; the result is then
shifted back into the PC. The program counter can
be changed in the following ways:
- JP (Jump) instructionPC=Jump address
- CALL instructionPC= Call address
- Relative Branch Instruction.PC= PC +/- offset
- Interrupt
- Reset
PC=Interrupt vector
PC= Reset vector
- RET & RETI instructionsPC= Pop (stack)
- Normal instructionPC= PC + 1
Flags (C, Z). The ST6 CPU includes three pairs of
flags (Carry and Zero), each pair being associated
with one of the three normal modes of operation:
Normal mode, Interrupt mode and Non Maskable
Interrupt mode. Each pair consists of a CARRY
flag and a ZERO flag. One pair (CN, ZN) is used
during Normal operation, another pair is used dur-
ing Interrupt mode (CI, ZI), and a third pair is used
in the Non Maskable Interrupt mode (CNMI, ZN-
MI).
Figure 7. ST6 CPU Programming Mode
l
b7 X REG. POINTER b0
INDEX
REGISTER
SHORT
DIRECT
ADDRESSING
b7 Y REG. POINTER b0
The ST6 CPU uses the pair of flags associated
with the current mode: as soon as an interrupt (or
a Non Maskable Interrupt) is generated, the ST6
CPU uses the Interrupt flags (resp. the NMI flags)
instead of the Normal flags. When the RETI in-
struction is executed, the previously used set of
flags is restored. It should be noted that each flag
set can only be addressed in its own context (Non
Maskable Interrupt, Normal Interrupt or Main rou-
tine). The flags are not cleared during context
switching and thus retain their status.
MODE
V REGISTER
W REGISTER
b7
b7
b0
b0
b7 ACCUMULATOR
PROGRAMCOUNTER
b0
b0
b11
SIX LEVELS
STACKREGISTER
The Carry flag is set when a carry or a borrow oc-
curs during arithmetic operations; otherwise it is
cleared. The Carry flag is also set to the value of
the bit tested in a bit test instruction; it also partici-
pates in the rotate left instruction.
NORMAL FLAGS
INTERRUPT FLAGS
NMI FLAGS
C
C
C
Z
Z
Z
The Zero flag is set if the result of the last arithme-
tic or logical operation was equal to zero; other-
wise it is cleared.
Switching between the three sets of flags is per-
formed automatically when an NMI, an interrupt or
a RETI instructions occurs. As the NMI mode is
VA000423
17/78
17
ST62T80B/E80B
3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES
3.1 CLOCK SYSTEM
3.1.1 Main Oscillator
Figure 8. Oscillator Configurations
The MCU features a Main Oscillator which can be
driven by an external clock, or used in conjunction
with an AT-cut parallel resonant crystal or a suita-
ble ceramic resonator.
CRYSTAL/RESONATOR CLOCK
ST6xxx
Figure 8 illustrates various possible oscillator con-
figurations using anexternal crystal or ceramic res-
OSC
OSC
out
in
onator, an external clock input. C an C should
L1
L2
have a capacitance in the range 12 to 22 pF for an
oscillator frequency in the 4-8 MHz range.
The internal MCU clock Frequency (F ) is divid-
INT
C
ed by 13 to drive the CPU core and by 12 to drive
the A/D converter and the watchdog timer, while
clock used to drive on-chip peripherals depends
on the peripheral as shown in the clock circuit
block diagram.
C
L1n
L2
VA0016
EXTERNAL CLOCK
ST6xxx
With an 8MHz oscillator frequency, the fastest ma-
chine cycle is therefore 1.625µs.
A machine cycle is the smallest unit of time needed
to execute anyoperation (for instance, to increment
the Program Counter). An instruction may require
two, four, or five machine cycles for execution.
OSC
OSC
NC
out
in
VA0015A
Figure 9. Clock Circuit Block Diagram
POR
f
OSC
OSCin
Core
: 13
: 12
f
INT
Timer 1 & 2
f
MAIN
OSCILLATOR
INT
Watchdog
ADC
OSCout
LCD
MUX
CONTROLLER
DRIVER
OSC32in
EOCR bit 5
(START/STOP )
32kHz
OSCILLATOR
OSC32out
18/78
18
ST62T80B/E80B
CLOCK SYSTEM (Cont’d)
3.1.2 32 KHz STAND-BY OSCILLATOR
32KHz Oscillator Register (32OCR)
An additional32KHz stand-by on chip oscillator al-
lows to generate real time interrupts and to supply
the clock to the LCD driver with the main oscillator
stopped. This enables the MCU to perform real
time functions with the LCD display running while
keeping advantages of low power consumption.
Figure 10 shows the 32KHz oscillator block dia-
gram.
Address: DBh - Read/Write
7
0
EOSCI OSCEOC S/S
D4
D3
D2
D1
D0
Bit 7= EOSCI. Enable Oscillator Interrupt. This bit,
when set, enables the 32KHz oscillator interrupt
request.
A 32.768KHz quartz crystal must be connected to
the OSC32in and OSC32out pins to perform the
real time clock operation. Two external capacitors
of 15-22pF each must be connected between the
oscillator pins and ground. The 32KHz oscillator is
managed by the dedicated status/control register
32OCR.
Bit 6 = OSCEOC. Oscillator Interrupt Flag. This bit
indicates when the 32KHz oscillator has measured
a
500ms
elapsed
time
(providing
a
32.768KHzquartz crystal is connected to the
32KHz oscillator dedicated pins). An interrupt re-
quest can be generated in relation to the state of
EOSCI bit. This bit must be cleared by the user
program before leaving the interrupt service rou-
tine.
As long as the 32KHz stand-by oscillator is ena-
bled, 32KHz internal clock is available to drive
14
LCD controller driver. This clock is divide by 2 to
Bit 5 = START/STOP. Oscillator Start/Stop bit.
This bit, when set, enables the 32KHz stand-by
oscillator and the free running divider chain is sup-
plied by the 32KHz oscillator signal. When this bit
is cleared to zero the divider chain is supplied with
generate interrupt request every 500ms . The peri-
odic interrupt request serves as reference time-
base for real time functions.
Note: When the 32KHz stand-by oscillator is
stopped (bit 5 of the Status/Control register
cleared) the divider chain is supplied with a clock
f
/13.
INT
This register is cleared during reset.
signal synchronous with machine cycle (f /13),
INT
14
this produces an interrupt request every 13x2
Note:
clock cycle (i.e. 26.624ms) with an 8MHz quartz
crystal.
To achieve minimum power consumption in STOP
mode (no system clock), the stand-by oscillator
must be switched off (real time function not availa-
ble) by clearing the Start/Stop bit in the oscillator
status/control register.
Figure 10. 32KHz Oscillator Block Diagram
OSC32KHz
2x15...22pF
OSC32IN
1
14
OSC32KHz
MUX
DIV 2
0
32.768KHz
Crystal
OSC32OUT
f
/13
INT
START
STOP
EOSCI OSCEOC
X
X
X
X
X
INT
19/78
19
ST62T80B/E80B
3.2 RESETS
The MCU can be reset in three ways:
– by the external Reset input being pulled low;
– by Power-on Reset;
The internaldelay is generated by an on-chipcoun-
ter. The internal reset line is released 2048 internal
clock cycles after release of the external reset.
Notes:
– by the digital Watchdog peripheral timing out.
3.2.1 RESET Input
To ensure correct start-up, the user should take
care that the reset signal is not released before the
The RESET pin may be connected to a device of
the application board in order to reset the MCU if
required. The RESET pin may be pulled low in
RUN, WAIT or STOP mode. This input can be
used to reset the MCU internal state and ensure a
correct start-up procedure. The pin is active low
and features a Schmitt trigger input. The internal
Reset signal is generated by adding a delay to the
external signal. Therefore even short pulses on
V
level is sufficient to allow MCU operation at
DD
the chosen frequency (see Recommended Oper-
ating Conditions).
A proper reset signal for a slow rising V supply
can generally be provided by an external RC net-
work connected to the RESET pin.
DD
Figure 11. Reset and Interrupt Processing
the RESET pin are acceptable, provided V has
DD
RESET
completed its rising phase and that the oscillator is
running correctly (normal RUN or WAIT modes).
The MCU is kept in the Reset state as long as the
RESET pin is held low.
NMI MASK SET
INT LATCH CLEARED
( IF PRESENT )
If RESET activation occurs in the RUN or WAIT
modes, processing of the user program is stopped
(RUN mode only), the Inputs and Outputs are con-
figured as inputs with pull-up resistors and the
main Oscillator is restarted. When the level on the
RESET pin then goes high, the initialization se-
quence is executed following expiry of the internal
delay period.
SELECT
NMI MODE FLAGS
PUT FFEH
If RESET pin activation occurs in the STOP mode,
the oscillator starts up and all Inputs and Outputs
are configured as inputs with pull-up resistors.
When the level of the RESET pin then goes high,
the initialization sequence is executed following
expiry of the internal delay period.
ON ADDRESS BUS
YES
IS RESET STILL
PRESENT?
3.2.2 Power-on Reset
The function of the POR circuit consists in waking
up the MCU at an appropriate stage during the
power-on sequence. At the beginning of this se-
quence, the MCU is configured in the Reset state:
all I/O ports are configured as inputs with pull-up
resistors and no instruction is executed. When the
power supply voltage rises to a sufficient level, the
oscillator starts to operate, whereupon an internal
delay is initiated, in order to allow the oscillator to
fully stabilize before executing the first instruction.
The initialization sequence is executed immediate-
ly following the internal delay.
NO
LOAD PC
FROM RESET LOCATIONS
FFE/FFF
FETCH INSTRUCTION
VA000427
20/78
20
ST62T80B/E80B
RESETS (Cont’d)
3.2.3 Watchdog Reset
initialisation routine from being interrupted. The in-
itialisation routine should therefore be terminated
by a RETI instruction, in order to revert to normal
mode and enable interrupts. If no pending interrupt
is presentat the end of the initialisation routine, the
MCU will continue by processing the instruction
immediately following the RETI instruction. If, how-
ever, a pending interrupt is present, it will be serv-
iced.
The MCU provides a Watchdog timer function in
order to ensure graceful recovery from software
upsets. If the Watchdog register is not refreshed
before an end-of-count condition is reached, the
internal reset will be activated. This, amongst oth-
er things, resets the watchdog counter.
The MCU restarts just as though the Reset had
been generated by the RESET pin, including the
built-in stabilisation delay period.
Figure 12. Reset and Interrupt Processing
3.2.4 Application Notes
RESET
No external resistor is required between V and
DD
the Reset pin, thanks to the built-in pull-up device.
The POR circuit operates dynamically, in that it
triggers MCU initialization on detecting the rising
JP:2 BYTES/4 CYCLES
JP
RESET
VECTOR
edge of V . The typical threshold is in the region
DD
of 2 volts, but the actual value of the detected
threshold depends on the way in which V rises.
DD
The POR circuit is NOT designed to supervise
static, or slowly rising or falling V
.
DD
INITIALIZATION
ROUTINE
3.2.5 MCU Initialization Sequence
RETI: 1 BYTE/2 CYCLES
When a reset occurs the stack is reset, the PC is
loaded with the address of the Reset Vector (locat-
ed in program ROM starting at address 0FFEh). A
jump to the beginning of the user program must be
coded at this address. Following a Reset, the In-
terrupt flag is automatically set, so that the CPU is
in Non Maskable Interrupt mode; this prevents the
RETI
VA00181
Figure 13. Reset Block Diagram
V
DD
ST6
INTERNAL
RESET
f
CK
OSC
300kΩ
COUNTER
RESET
RESET
RESET
2.8kΩ
ON RESET
POWER
WATCHDOG RESET
VA0200B
21/78
21
ST62T80B/E80B
RESETS (Cont’d)
Table 7. Register Reset Status
Register
Address(es)
0DFh
Status
Comment
EEPROM enabled
EEPROM Control Register
Port Data Registers
0C0h, 0C1h, 0C3h
0C4h to 0C6h
0CCh, 0CEh, OCFh
0C8h
Port A,B Direction Register
Port A,B Option Register
Interrupt Option Register
I/O are Input with pull-up
Interrupt disabled
00h
SPI Registers
0C2h, 0DDh
0DCh
SPI disabled
LCD Mode Control Register
32kHz Oscillator Register
LCD display off
Interrupt disabled
0DBh
UART Control
00h
UART disabled
UART Data Register
X, Y,V, W, Register
Accumulator
080H TO 083H
0FFh
Data RAM
084h to 0BFh
Data RAM/EEPROM/LCDRAM Page Register 0CBh
Undefined
As written if programmed
Data ROM Window Register
EEPROM
0C9h
00h to 03Fh
0D0h
A/D Result Register
TIMER 1 Status/Control
TIMER 1 Counter Register
TIMER 1 Prescaler Register
0D4h
0D3h
0D2h
00h
FFh
7Fh
TIMER 1 disabled/Max count
loaded
Watchdog Counter Register
A/D Control Register
0D8h
0D1h
FEh
40h
A/D in Standby
AR TIMER Mode Control Register
AR TIMER Status/Control 1 Register
AR TIMER Status/Control 2Register
AR TIMER Compare Register
0E5h
0E6h
0E7h
0EAh
AR TIMER stopped
00h
Undefined
As written if programmed
AR TIMER Load Register
0EBh
0E9h
AR TIMER Reload/Capture Register
22/78
22
ST62T80B/E80B
3.3 DIGITAL WATCHDOG
The digital Watchdog consists of a reloadable
downcounter timer which can be used to provide
controlled recovery from software upsets.
Watchdog behaviour is governed by one option,
known as “WATCHDOG ACTIVATION” (i.e.
HARDWARE or SOFTWARE) (See Table 8).
The Watchdog circuit generates a Reset when the
downcounter reaches zero. User software can
prevent this reset by reloading the counter, and
should therefore be written so that the counter is
regularly reloaded while the user program runs
correctly. In the event of a software mishap (usual-
ly caused by externally generated interference),
the user program will no longer behave in its usual
fashion and the timer register will thus not be re-
loaded periodically. Consequently the timer will
decrement down to 00h and reset the MCU. In or-
der to maximise the effectiveness of the Watchdog
function, user software must be written with this
concept in mind.
In the SOFTWARE option, the Watchdog is disa-
bled until bit C of the DWDR register has been set.
When the Watchdog is disabled, low power Stop
mode is available. Once activated, the Watchdog
cannot be disabled, except by resetting the MCU.
In the HARDWARE option, the Watchdog is per-
manently enabled. Since the oscillator will run con-
tinuously, low power mode is not available. The
STOP instruction is interpreted as a WAIT instruc-
tion, and the Watchdog continues to countdown.
When the MCU exits STOP mode (i.e. when an in-
terrupt is generated), the Watchdog resumes its
activity.
Table 8. Recommended Option Choices
Functions Required
Stop Mode
Recommended Options
“SOFTWARE WATCHDOG”
“HARDWARE WATCHDOG”
Watchdog
23/78
23
ST62T80B/E80B
DIGITAL WATCHDOG (Cont’d)
The Watchdog is associated with a Data space
register (Digital WatchDog Register, DWDR, loca-
tion 0D8h) which is described in greater detail in
Section 3.3.1 . This register is set to 0FEh on Re-
set: bit C is cleared to “0”, which disables the
Watchdog; the timer downcounter bits, T0 to T5,
and the SR bit are all set to “1”, thus selecting the
longest Watchdog timer period. This time period
can be set to the user’s requirements by setting
the appropriate value for bits T0 to T5 in the
DWDR register. The SR bit must be set to “1”,
since it is this bit which generates the Reset signal
when it changes to “0”; clearing this bit would gen-
erate an immediate Reset.
Figure 14. Watchdog Counter Control
D0
C
D1
SR
RESET
D2
D3
D4
D5
D6
D7
T5
T4
T3
T2
T1
T0
It should be noted that the order of the bits in the
DWDR register is inverted with respect to the as-
sociated bits in the down counter: bit 7 of the
DWDR register corresponds, in fact, to T0 and bit
2 to T5. The user should bear in mind the fact that
these bits are inverted and shifted with respect to
the physical counter bits when writing to this regis-
ter. The relationship between the DWDR register
bits and the physical implementation of the Watch-
dog timer downcounter is illustrated in Figure 14.
Only the 6 most significant bits may be used to de-
fine the time period, since it is bit 6 which triggers
the Reset when it changes to “0”. This offers the
user a choice of 64 timed periods ranging from
3,072 to 196,608 clock cycles (with an oscillator
frequency of 8MHz, this is equivalent to timer peri-
ods ranging from 384µs to 24.576ms).
8
÷2
OSC ÷12
VR02068A
24/78
24
ST62T80B/E80B
DIGITAL WATCHDOG (Cont’d)
3.3.1 Digital Watchdog Register (DWDR)
It should be noted that the register bits are re-
versed and shifted with respect to the physical
counter: bit-7 (T0) is the LSB of the Watchdog
downcounter and bit-2 (T5) is the MSB.
Address: 0D8h
— Read/Write
Reset status: 1111 1110b
These bits are set to “1” on Reset.
7
0
3.3.2 Application Notes
T0
T1
T2
T3
T4
T5
SR
C
The Watchdog plays an important supporting role
in the high noise immunity of ST62xx devices, and
should be used wherever possible. Watchdog re-
lated options should be selected on the basis of a
trade-off between application security and STOP
mode availability.
Bit 0 = C: Watchdog Control bit
If the hardware option is selected, this bit is forced
high and the user cannot change it (the Watchdog
is always active). When the software option is se-
lected, the Watchdog function is activated by set-
ting bit C to 1, and cannot then be disabled (save
by resetting the MCU).
When STOP mode is not required, hardware acti-
vation should be preferred, as it provides maxi-
mum security, especially during power-on.
When C is kept low the counter can be used as a
7-bit timer.
When software activation is selected and the
Watchdog is not activated, the downcounter may
be used as a simple 7-bit timer (remember that the
bits are in reverse order).
This bit is cleared to “0” on Reset.
Bit 1 = SR: Software Reset bit
This bit triggers a Reset when cleared.
The software activation option should be chosen
only when the Watchdog counter is to be used as
a timer. To ensure the Watchdog has not been un-
expectedly activated, the following instructions
should be executed within the first 27 instructions:
When C = “0” (Watchdog disabled) it is the MSB of
the 7-bit timer.
This bit is set to “1” on Reset.
Bits 2-7 = T5-T0: Downcounter bits
jrr 0, WD, #+3
25/78
25
ST62T80B/E80B
DIGITAL WATCHDOG (Cont’d)
These instructions test the C bit and Reset the
MCU (i.e. disable the Watchdog) if the bit is set
(i.e. if the Watchdog is active), thus disabling the
Watchdog.
should load the watchdog counter within the first
27 instructions following Watchdog activation
(software mode), or within the first 27 instructions
executed following a Reset (hardware activation).
In all modes, a minimum of 28 instructions are ex-
ecuted after activation, before the Watchdog can
generate a Reset. Consequently, user software
It should be noted that when the GEN bit is low (in-
terrupts disabled), the NMI interrupt is active but
cannot cause a wake up from STOP/WAIT modes.
Figure 15. Digital Watchdog Block Diagram
RESET
Q
RSFF
7
8
-2
-2
-12
R
DB1.7 LOAD SET
SET
S
OSCILLATOR
CLOCK
8
DB0
WRITE
RESET
DATA BUS
VA00010
26/78
26
ST62T80B/E80B
3.4 INTERRUPTS
The CPU can manage four Maskable Interrupt
sources, in addition to a Non Maskable Interrupt
source (top priority interrupt). Each source is asso-
ciated with a specific Interrupt Vector which con-
tains a Jump instruction to the associated interrupt
service routine. These vectors are located in Pro-
gram space (see Table 9).
ically reset by the core at the beginning of the non-
maskable interrupt service routine.
Interrupt request from source #1 can be config-
ured either as edge or level sensitive by setting ac-
cordingly the LES bit of the Interrupt Option Regis-
ter (IOR).
Interrupt request from source #2 are always edge
sensitive. The edge polarity can be configured by
setting accordingly the ESB bit of the Interrupt Op-
tion Register (IOR).
When an interrupt source generates an interrupt
request, and interrupt processing is enabled, the
PC register is loaded with the address of the inter-
rupt vector (i.e. of the Jump instruction), which
then causes a Jump to the relevant interrupt serv-
ice routine, thus servicing the interrupt.
Interrupt request from sources #3 & #4 are level
sensitive.
In edge sensitive mode, a latch is set when a edge
occurs on the interrupt source line and is cleared
when the associated interrupt routine is started.
So, the occurrence of an interrupt can be stored,
until completion of the running interrupt routine be-
fore being processed. If several interrupt requests
occurs before completion of the running interrupt
routine, only the first request is stored.
Interrupt sources are linked to events either on ex-
ternal pins, or on chip peripherals. Several events
can be ORed on the same interrupt source, and
relevant flags are available to determine which
event triggered the interrupt.
The Non Maskable Interrupt request has the high-
est priority and can interrupt any interrupt routine
at any time; the other four interrupts cannot inter-
rupt each other. If more than one interrupt request
is pending, these are processed by the processor
core according to their priority level: source #1 has
the higher priority while source #4 the lower. The
priority of each interrupt source is fixed.
Storage of interrupt requests is not available in lev-
el sensitive mode. To be taken into account, the
low level must be present on the interrupt pin when
the MCU samples the line after instruction execu-
tion.
At the end of every instruction, the MCU tests the
interrupt lines: if there is an interrupt request the
next instruction is not executed and the appropri-
ate interrupt service routine is executed instead.
Table 9. Interrupt Vector Map
Interrupt Source
Interrupt source #0
Interrupt source #1
Interrupt source #2
Interrupt source #3
Interrupt source #4
Priority
Vector Address
(FFCh-FFDh)
(FF6h-FF7h)
(FF4h-FF5h)
(FF2h-FF3h)
(FF0h-FF1h)
1
2
3
4
5
Table 10. Interrupt Option Register Description
SET
Enable all interrupts
Disable all interrupts
GEN
CLEARED
Rising edge mode on inter-
rupt source #2
SET
ESB
3.4.1 Interrupt request
Falling edge mode on inter-
rupt source #2
CLEARED
SET
All interrupt sources but the Non Maskable Inter-
rupt source can be disabled by setting accordingly
the GEN bit of the Interrupt Option Register (IOR).
This GEN bit also defines if an interrupt source, in-
cluding the Non Maskable Interrupt source, can re-
start the MCU from STOP/WAIT modes.
Level-sensitive mode on in-
terrupt source #1
LES
Falling edge mode on inter-
rupt source #1
CLEARED
OTHERS
NOT USED
Interrupt request from the Non Maskable Interrupt
source #0 is latched by a flip flop which is automat-
27/78
27
ST62T80B/E80B
INTERRUPTS (Cont’d)
3.4.2 Interrupt Procedure
MCU
– Automatically the MCU switches back to the nor-
mal flag set (or the interrupt flag set) and pops
the previous PC value from the stack.
The interrupt procedure is very similar to a call pro-
cedure, indeed the user can consider the interrupt
as an asynchronous call procedure. As this is an
asynchronous event, the user cannot know the
context and the time at which it occurred. As a re-
sult, the user should save all Data space registers
which may be used within the interrupt routines.
There are separate sets of processor flags for nor-
mal, interrupt and non-maskable interrupt modes,
which are automatically switched and so do not
need to be saved.
The interrupt routine usually begins by the identify-
ing the device which generated the interrupt re-
quest (by polling). The user should save the regis-
ters which are used within the interrupt routine in a
software stack. After the RETI instruction is exe-
cuted, the MCU returns to the main routine.
Figure 16. Interrupt Processing Flow Chart
The following list summarizes the interrupt proce-
dure:
INSTRUCTION
MCU
FETCH
– The interrupt is detected.
INSTRUCTION
– The C and Z flags are replaced by the interrupt
flags (or by the NMI flags).
EXECUTE
– The PC contents are stored in the first level of
the stack.
INSTRUCTION
– The normal interrupt lines are inhibited (NMI still
active).
– The first internal latch is cleared.
LOAD PC FROM
INTERRUPT VECTOR
NO
WAS
(FFC/FFD)
THE INSTRUCTION
?
A RETI
– Theassociatedinterruptvectorisloaded inthePC.
YES
IS THE CORE
ALREADY IN
NORMAL MODE?
SET
WARNING: In some circumstances, when a
maskable interrupt occurs while the ST6 core is in
NORMAL mode and especially during the execu-
tion of an ”ldi IOR, 00h” instruction (disabling all
maskable interrupts): if the interrupt arrives during
the first 3 cycles of the ”ldi” instruction (which is a
4-cycle instruction) the core will switch to interrupt
mode BUT the flags CN and ZN will NOT switch to
the interrupt pair CI and ZI.
YES
INTERRUPT MASK
?
NO
CLEAR
INTERRUPT MASK
PUSH THE
PC INTO THE STACK
SELECT
PROGRAM FLAGS
SELECT
INTERNAL MODE FLAG
User
”POP”
– User selected registers are saved within the in-
terrupt service routine (normally on a software
stack).
THE STACKED PC
CHECK IF THERE IS
AN INTERRUPT REQUEST
AND INTERRUPTMASK
NO
– Thesource of the interrupt is found by polling the
interrupt flags (if more than one source is associ-
ated with the same vector).
?
YES
VA000014
– The interrupt is serviced.
– Return from interrupt (RETI)
28/78
28
ST62T80B/E80B
INTERRUPTS (Cont’d)
3.4.3 Interrupt Option Register (IOR)
Bit 5 = ESB: Edge Selection bit.
The Interrupt Option Register (IOR) is used to en-
able/disable the individual interrupt sources and to
select the operating mode of the external interrupt
inputs. This register is write-only and cannot be
accessed by single-bit operations.
The bit ESB selects the polarity of the interrupt
source #2.
Bit 4= GEN: Global Enable Interrupt. When this bit
is set to one, all interrupts are enabled. When this
bit is cleared to zero all the interrupts (excluding
NMI) are disabled.
Address: 0C8h
—
Write Only
Reset status: 00h
When the GEN bit is low, the NMI interrupt is ac-
tive but cannot cause a wake up from STOP/WAIT
modes.
7
-
0
-
This register is cleared on reset.
LES ESB GEN
-
-
-
3.4.4 Interrupt sources
Interrupt
sources
available
on
the
Bit 7, Bits 3-0 = Unused.
ST62E80B/T80B are summarized in the Table 11
with associated mask bit to enable/disable the in-
terrupt request.
Bit 6 = LES: Level/Edge Selection bit.
When this bit is set to one, the interrupt source #1
is level sensitive. When cleared to zero the edge
sensitive mode for interrupt request is selected.
Table 11. Interrupt Requests and Mask Bits
Address
Interrupt
source
Peripheral
Register
IOR
TSCR1
A/D CONVERTER ADCR
Mask bit
Masked Interrupt Source
Register
GENERAL
TIMER 1
C8h
GEN
ETI
All Interrupts, excluding NMI All
D4h
TMZ: TIMER Overflow
EOC: End of Conversion
End of Transmission
source 3
D1h
EAI
source 4
source 1
source 2
source 2
source 2
source 3
SPI
SPI
C2h
ALL
Port PAn
Port PBn
Port PCn
32kHz OSC
ORPA-DRPA
ORPB-DRPB
C0h-C4h
C1h-C5h
ORPAn-DRPAn PAn pin
ORPBn-DRPBn PBn pin
ORPCn-DRPCn PCn pin
ORPC-DRPC C6h-CFh
32OCR
DBh
EOSCI
OSCEOC
OVIE
CPIE
EIE
OVF: ARTIMER Overflow
CPF: Successful Compare
EF: Active edge on ARTIMin
ARTIMER
UART
ARMC
E5h
source 3
source 4
RXIEN
TXIEN
RXRDY: byte received
TXMT: byte sent
UARTCR
D7h
29/78
29
ST62T80B/E80B
INTERRUPTS (Cont’d)
Figure 17. Interrupt Block Diagram
FF
CLK
CLR
INT #0 NMI (FFC,D))
NMI
Q
I
Start
0
FF
CLK
CLR
0
Q
SPI
INT #1 (FF6,7)
MUX
FROM REGISTER PORT A,B,C
SINGLE BIT ENABLE
I
Start
1
1
PBE
IOR bit 6 (LES)
V
DD
RESTART
FROM
STOP/WAIT
PORT A
FF
CLK
CLR
PBE
PBE
PORT B
PORT C
INT #2 (FF4,5)
Q
Bits
I
Start
2
IOR bit 5 (ESB)
TMZ
ETI
TIMER1
OVF
OVIE
CPF
CPIE
INT #3 (FF2,3)
ARTIMER
EF
EIE
OSCEOC
EOSCI
OSC32kHz
EAI
EOC
INT #4 (FF0,1)
A/D CONVERTER
RXRDY
RXIEN
TXMT
TXIEN
IOR bit 4(GEN)
30/78
30
ST62T80B/E80B
3.5 POWER SAVING MODES
The WAIT and STOP modes have been imple-
mented in the ST62xx family of MCUs in order to
reduce the product’s electrical consumption during
idle periods. These two power saving modes are
described in the following paragraphs.
of the processor core prior to the WAIT instruction,
but also on the kind of interrupt request which is
generated. This is described in the following para-
graphs. The processor core does not generate a
delay following the occurrence of the interrupt, be-
cause the oscillator clock is still available and no
stabilisation period is necessary.
3.5.1 WAIT Mode
The MCU goes into WAIT mode as soon as the
WAIT instruction is executed. The microcontroller
can be considered as being in a “software frozen”
state where the core stops processing the pro-
gram instructions, the RAM contents and peripher-
al registers are preserved as long as the power
supply voltage is higher than the RAM retention
voltage. In this mode the peripherals are still ac-
tive.
3.5.2 STOP Mode
If the Watchdog is disabled, STOP mode is availa-
ble. When in STOP mode, the MCU is placed in
the lowest power consumption mode. In this oper-
ating mode, the microcontroller can be considered
as being “frozen”, no instruction is executed, the
oscillator is stopped, the RAM contents and pe-
ripheral registers are preserved as long as the
power supply voltage is higher than the RAM re-
tention voltage, and the ST62xx core waits for the
occurrence of an external interrupt request or a
Reset to exit the STOP state.
WAIT mode can be used when the user wants to
reduce the MCU power consumption during idle
periods, while not losing track of time or the capa-
bility of monitoring external events. The active os-
cillator is not stopped in order to provide a clock
signal to the peripherals. Timer counting may be
enabled as well as the Timer interrupt, before en-
tering the WAIT mode: this allows the WAIT mode
to be exited when a Timer interrupt occurs. The
same applies to other peripherals which use the
clock signal.
If the STOP state is exited due to a Reset (by acti-
vating the external pin) the MCU will enter a nor-
mal reset procedure. Behaviour in response to in-
terrupts depends on the state of the processor
core prior to issuing the STOP instruction, and
also on the kind of interrupt request that is gener-
ated.
If the WAIT mode is exited due to a Reset (either
by activating the external pin or generated by the
Watchdog), the MCU enters a normal reset proce-
dure. If an interrupt is generated during WAIT
mode, the MCU’s behaviour depends on the state
This case will be described in the following para-
graphs. The processor core generates a delay af-
ter occurrence of the interrupt request, in order to
wait for complete stabilisation of the oscillator, be-
fore executing the first instruction.
31/78
31
ST62T80B/E80B
POWER SAVING MODE (Cont’d)
3.5.3 Exit from WAIT and STOP Modes
tered will be completed, starting with the
execution of the instruction which follows the
STOP or the WAIT instruction, and the MCU is
still in the interrupt mode. At the end of this rou-
tine pendinginterrupts will be serviced in accord-
ance with their priority.
The following paragraphs describe how the MCU
exits from WAIT and STOP modes, when an inter-
rupt occurs (not a Reset). It should be noted that
the restart sequence depends on the original state
of the MCU (normal, interrupt or non-maskable in-
terrupt mode) prior to entering WAIT or STOP
mode, as well as on the interrupt type.
– In the event of a non-maskable interrupt, the
non-maskable interrupt service routine is proc-
essed first, then the routine in which the WAIT or
STOP mode was entered will be completed by
executing the instruction following the STOP or
WAIT instruction. The MCU remains in normal
interrupt mode.
Interrupts do not affect the oscillator selection.
3.5.3.1 Normal Mode
If the MCU was in the main routine when the WAIT
or STOP instruction was executed, exit from Stop
or Wait mode will occur as soon as an interrupt oc-
curs; the related interrupt routine is executed and,
on completion, the instruction which follows the
STOP or WAIT instruction is then executed, pro-
viding no other interrupts are pending.
Notes:
To achieve the lowest power consumption during
RUN or WAIT modes, the user program must take
care of:
– configuring unused I/Os as inputs without pull-up
(these should be externally tied to well defined
logic levels);
3.5.3.2 Non Maskable Interrupt Mode
If the STOP or WAIT instruction has been execut-
ed during execution of the non-maskable interrupt
routine, the MCU exits from the Stop or Wait mode
as soon as an interrupt occurs: the instruction
which follows the STOP or WAIT instruction is ex-
ecuted, and the MCU remains in non-maskable in-
terrupt mode, even if another interrupt has been
generated.
– placing all peripherals in their power down
modes before entering STOP mode;
When the hardware activated Watchdog is select-
ed, or when the software Watchdog is enabled, the
STOP instruction is disabled and a WAIT instruc-
tion will be executed in its place.
3.5.3.3 Normal Interrupt Mode
If all interrupt sources are disabled (GEN low), the
MCU can only be restarted by a Reset. Although
setting GEN low does not mask the NMI as an in-
terrupt, it will stop it generating a wake-up signal.
If the MCU was in interrupt mode before the STOP
or WAIT instruction was executed, it exits from
STOP or WAIT mode as soon as an interrupt oc-
curs. Nevertheless, two cases must be consid-
ered:
The WAIT and STOP instructions are not execut-
ed if an enabled interrupt request is pending.
– If the interrupt is a normal one, the interrupt rou-
tine in which the WAIT or STOP mode was en-
32/78
32
ST62T80B/E80B
4 ON-CHIP PERIPHERALS
4.1 I/O PORTS
The MCU features Input/Output lines which may
be individually programmed as any of the following
input or output configurations:
be also written by user software, in conjunction
with the related option registers, to select the dif-
ferent input mode options.
– Input without pull-up or interrupt
– Input with pull-up and interrupt
– Input with pull-up, but without interrupt
– Analog input
Single-bit operations on I/O registers are possible
but care is necessary because reading in input
mode is done from I/O pins while writing will direct-
ly affect the Port data register causing an unde-
sired change of the input configuration.
The Data Direction registers (DDRx) allow the
data direction (input or output) of each pin to be
set.
– Push-pull output
– Open drain output
The lines are organised as bytewise Ports.
The Option registers (ORx) are used to select the
different port options available both in input and in
output mode.
Each port is associated with 3 registers in Data
space. Each bit of these registers is associated
with a particular line (for instance, bits 0 of Port A
Data, Direction and Option registers are associat-
ed with the PA0 line of Port A).
All I/O registers can be read or written to just as
any other RAM location in Data space, so no extra
RAM cells are needed for port data storage and
manipulation. During MCU initialization, all I/O reg-
isters are cleared and the input mode with pull-ups
and no interrupt generation is selected for all the
pins, thus avoiding pin conflicts.
The DATA registers (DRx), are used to read the
voltage level values of the lines which have been
configured as inputs, or to write the logic value of
the signal to be output on the lines configured as
outputs. The port data registers can be read to get
the effective logic levels of the pins, but they can
Figure 18. I/O Port Block Diagram
RESET
V
DD
S
CONTROLS
IN
DATA
DIRECTION
REGISTER
V
DD
INPUT/OUTPUT
DATA
REGISTER
SHIFT
REGISTER
OPTION
REGISTER
S
OUT
TO INTERRUPT
TO ADC
VA00413
33/78
33
ST62T80B/E80B
I/O PORTS (Cont’d)
4.1.1 Operating Modes
4.1.1.2 Interrupt Options
Each pin may be individually programmed as input
or output with various configurations.
All input lines can be individually connected by
software to the interrupt system by programming
the OR and DR registers accordingly. The inter-
rupt trigger modes (falling edge, rising edge and
low level) can be configured by software as de-
scribed in the Interrupt Chapter for each port.
This is achieved by writing the relevant bit in the
Data (DR), Data Direction (DDR) and Option reg-
isters (OR). Table 12 illustrates the various port
configurations which can be selected by user soft-
ware.
4.1.1.3 Analog Input Options
4.1.1.1 Input Options
Some pins can be configured as analog inputs by
programming the OR and DR registers according-
ly. These analog inputs are connected to the on-
chip 8-bit Analog to Digital Converter. ONLY ONE
pin should be programmed as an analog input at
any time, since by selecting more than one input
simultaneously their pins will be effectively short-
ed.
Pull-up, High Impedance Option. All input lines
can be individually programmed with or without an
internal pull-up by programming the OR and DR
registers accordingly. If the pull-up option is not
selected, the input pin will be in the high-imped-
ance state.
Table 12. I/O Port Option Selection
DDR
OR
0
DR
0
Mode
Input
Option
0
0
0
0
1
1
With pull-up, no interrupt
0
1
Input
No pull-up, no interrupt
1
0
Input
With pull-up and with interrupt
1
1
Input
Analog input (when available)
0
X
X
Output
Output
Open-drain output (20mA sink when available)
Push-pull output (20mA sink when available)
1
Note: X = Don’t care
34/78
34
ST62T80B/E80B
I/O PORTS (Cont’d)
4.1.2 Safe I/O State Switching Sequence
outputs, it is advisable to keep a copy of the data
register in RAM. Single bit instructions may then
be used on the RAM copy, after which the whole
copy register can be written to the port data regis-
ter:
Switching the I/O ports from one state to another
should be done in a sequence which ensures that
no unwanted side effects can occur. The recom-
mended safe transitions are illustrated in Figure
19. All other transitions are potentially risky and
should be avoided when changing the I/O operat-
ing mode, as it is most likely that undesirable side-
effects will be experienced, such as spurious inter-
rupt generation or two pins shorted together by the
analog multiplexer.
SET bit, datacopy
LD a, datacopy
LD DRA, a
Warning: Care must also be taken to not use in-
structions that act on a whole port register (INC,
DEC, or read operations) when all 8 bits are not
available on the device. Unavailable bits must be
masked by software (AND instruction).
Single bit instructions (SET, RES, INC and DEC)
should be used with great caution on Ports Data
registers, since these instructions make an implicit
read and write back of the entire register. In port
input mode, however, the data register reads from
the input pins directly, and not from the data regis-
ter latches. Since data register information in input
mode is used to set the characteristics of the input
pin (interrupt, pull-up, analog input), these may be
unintentionally reprogrammed depending on the
state of the input pins. As a general rule, it is better
to limit the use of single bit instructions on data
registers to when the whole (8-bit) port is in output
mode. In the case of inputs or of mixed inputs and
The WAIT and STOP instructions allow the
ST62xx to be used in situations where low power
consumption is needed. The lowest power con-
sumption is achieved by configuring I/Os in input
mode with well-defined logic levels.
The user must take care not to switch outputs with
heavy loads during the conversion of one of the
analog inputs in order to avoid any disturbance to
the conversion.
Figure 19. Diagram showing Safe I/O State Transitions
Interrupt
Input
010*
011
001
pull-up
Analog
Input
pull-up (Reset
state)
000
100
Input
Output
Open Drain
Output
Open Drain
101
111
Output
Push-pull
Output
Push-pull
110
Note *. xxx = DDR, OR, DR Bits respectively
35/78
35
ST62T80B/E80B
I/O PORTS (Cont’d)
Table 13. I/O Port configuration for the ST62T80B/E80B
MODE
AVAILABLE ON(1)
SCHEMATIC
PA2-PA7
Input
PB0-PB7
PC0-PC7
Data in
Interrupt
Input
PA2-PA7
PB0-PB7
PC0-PC7
with pull up
(Reset state)
Data in
Interrupt
Input
PA2-PA7
PB0-PB7
PC0-PC7
with pull up
with interrupt
Data in
Interrupt
PB0-PB7
PC4-PC7
Analog Input
ADC
Open drain output
5mA
PA2-PA7
PB0-PB7
PC0-PC7
Data out
Open drain output
20mA
PA2-PA7
PC0-PC3
Push-pull output
5mA
PA2-PA7
PB0-PB7
PC0-PC7
Data out
Push-pull output
20mA Sink
PA2-PA7
PC0-PC3
Note 1. Provided the correct configuration has been selected.
36/78
36
ST62T80B/E80B
I/O PORTS (Cont’d)
4.1.3 ARTimer alternate functions
PA7/Sout must be configured in open drain output
mode to be used as data out for the SPI. In output
mode, the value present on the pin is the port data
register content only if PA7 is defined as push pull
output, while serial transmission is possible only in
open drain mode.
When bit PWMOE of register ARMC is low, pin
ARTIMout/PB7 is configured as any standard pin
of port B through the port registers. When PW-
MOE is high, ARTIMout/PB7 is the PWM output,
independently of the port registers configuration.
4.1.5 UART alternate functions
ARTIMin/PB6 is connected to the AR Timer input.
It is configured through the port registers as any
standard pin of port B. To use ARTIMin/PB6 as AR
Timer input, it must be configured as input through
DDRB.
PB1/RXD1 pin must be configured as input
through the DDR and OR registers to be used as
reception line for the UART. All input modes are
available and PB1 can be read independently of
the UART at any time.
4.1.4 SPI alternate functions
PB0/TXD1 pin must be configured as output
through the DDR and OR registers to be used as
transmission line for the UART. Value present on
the pin in output mode is the Data register content
as long as no transmission is active.
PA6/Sin and PA5/Scl pins must be configured as
input through the DDR and OR registers to be
used as data in and data clock (Slave mode) for
the SPI. All input modes are available and I/O’s
can be read independently of the SPI at any time.
37/78
37
ST62T80B/E80B
Figure 20. Peripheral Interface Configuration of Serial I/O TImer 1, ARTimer
V
DD
PID
RXD
PB0/RXD1
PB1/TXD1
DR
UART
IARTOE
PID
DR
0
1
MUX
TXD
V
DD
PP/OD
OPR
DR
OUT
IN
0
1
PA7/Sout
MUX
SPI
PA6/Sin
DR
DR
CLOCK
PA5/SCL
PP/OD
OPR
DR
IN
TIMER1
0
1
OUT
PA4/TIM1
MUX
DR
TIMIN
PB6/ARTIMin
PWMOE
ARTimer
OPR
TIMOUT
PP/OD
1
0
PB7/ARTIMout
MUX
DR
VR01661
38/78
38
ST62T80B/E80B
I/O PORTS (Cont’d)
4.1.6 I/O Port Option Registers
4.1.8 I/O Port Data Registers
ORA/B/C (CCh PA, CEh PB, CFh PC)
Read/Write
DRA/B/C (C0h PA, C1h PB, C3h PC)
Read/Write
7
0
7
0
Px7 Px6 Px5 Px4 Px3 Px2 Px1 Px0
Px7 Px6 Px5 Px4 Px3 Px2 Px1 Px0
Bit 7-0 = Px7 - Px0: Port A, B, C Option Register
bits.
Bit 7-0 = Px7 - Px0: Port A, B, C Data Registers
bits.
4.1.7 I/O Port Data Direction Registers
DDRA/B/C (C4h PA, C5h PB, C6h PC)
Read/Write
7
0
Px7 Px6 Px5 Px4 Px3 Px2 Px1 Px0
Bit 7-0 = Px7 - Px0: Port A, B, C Data Direction
Registers bits.
39/78
39
ST62T80B/E80B
4.2 TIMER
The MCU features an on-chip Timer peripheral,
consisting of an 8-bit counter with a 7-bit program-
The prescaler input can be the internal frequency
divided by 12 or an external clock applied to
f
INT
15
mable prescaler, giving a maximum count of 2 .
the TIMER pin. The prescaler decrements on the
rising edge. Depending on the division factor pro-
grammed by PS2, PS1 and PS0 bits in the TSCR.
The clock input of the timer/counter register is mul-
tiplexed to different sources. For division factor 1,
the clock input of the prescaler is also that of tim-
er/counter; for factor 2, bit 0 of the prescaler regis-
ter is connected to the clock input of TCR. This bit
changes its state at half the frequency of the pres-
caler input clock. For factor 4, bit 1 of the PSC is
connected to the clock input of TCR, and so forth.
The prescaler initialize bit, PSI, in the TSCR regis-
ter must be set to “1” to allow the prescaler (and
hence the counter) to start. If it is cleared to “0”, all
the prescaler bits are set to “1” and the counter is
inhibited from counting. The prescaler can be
loaded with any value between 0 and 7Fh, if bit
PSI is set to “1”. The prescaler tap is selected by
means of the PS2/PS1/PS0 bits in the control reg-
ister.
The peripheral may be configured in three different
operating modes.
Figure 21 shows the Timer Block Diagram. The
external TIMER pin is available to the user. The
content of the 8-bit counter can be read/written in
the Timer/Counter register, TCR, while the state of
the 7-bit prescaler can be read in the PSC register.
The control logic device is managed in the TSCR
register as described in the following paragraphs.
The 8-bit counter is decremented by the output
(rising edge) coming from the 7-bit prescaler and
can be loaded and read under program control.
When it decrements to zero then the TMZ (Timer
Zero) bit in the TSCR is set to “1”. If the ETI (Ena-
ble Timer Interrupt) bit in the TSCR is also set to
“1”, an interrupt request is generated as described
in the Interrupt Chapter. The Timer interrupt can
be used to exit the MCU from WAIT mode.
Figure 22 illustrates the Timer’s working principle.
Figure 21. Timer Block Diagram
DATABUS 8
8
8
8
6
5
4
3
2
b5
b1
b0
b7
b6
b4
b3
b2
8-BIT
COUNTER
STATUS/CONTROL
REGISTER
SELECT
PSC
1
OF 7
ETI TOUT
TMZ
DOUT
PSI
PS2
PS1
PS0
1
0
3
TIMER
INTERRUPT
LINE
LATCH
SYNCHRONIZATION
LOGIC
:12
fOSC
VA00009
40/78
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ST62T80B/E80B
TIMER (Cont’d)
4.2.1 Timer Operating Modes
The user can select the desired prescaler division
ratio through the PS2, PS1, PS0 bits. When the
TCR count reaches 0, it sets the TMZ bit in the
TSCR. The TMZ bit can be tested under program
control to perform a timer function whenever it
goes high. The low-to-high TMZ bit transition is
used to latch the DOUT bit of the TSCR and trans-
fer it to the TIMER pin. This operating mode allows
external signal generation on the TIMER pin.
There are three operating modes, which are se-
lected by the TOUT and DOUT bits (see TSCR
register). These three modes correspond to the
two clocks which can be connected to the 7-bit
prescaler (f
the output mode.
÷ 12 or TIMER pin signal), and to
INT
4.2.1.1 Gated Mode
(TOUT = “0”, DOUT = “1”)
Table 14. Timer Operating Modes
In this mode the prescaler is decremented by the
TOUT
DOUT
Timer Pin
Input
Timer Function
Event Counter
Gated Input
Output “0”
Timer clock input (f
÷ 12), but ONLY when the
INT
signal on the TIMER pin is held high (allowing
pulse width measurement). This mode is selected
by clearing the TOUT bit in the TSCR register to
“0” (i.e. as input) and setting the DOUT bit to “1”.
0
0
1
1
0
1
0
1
Input
Output
Output
Output “1”
4.2.1.2 Event Counter Mode
(TOUT = “0”, DOUT = “0”)
4.2.2 Timer Interrupt
In this mode, the TIMER pin is the input clock of
the prescaler which is decremented on the rising
edge.
When the counter register decrements to zero with
the ETI (Enable Timer Interrupt) bit set to one, an
interrupt request is generated as described in the
Interrupt Chapter. When the counter decrements
to zero, the TMZ bit in the TSCR register is set to
one.
4.2.1.3 Output Mode
(TOUT = “1”, DOUT = data out)
The TIMER pin is connected to the DOUT latch,
hence the Timer prescaler is clocked by the pres-
caler clock input (f
÷ 12).
INT
Figure 22. Timer Working Principle
7-BIT PRESCALER
BIT0
BIT1
BIT2
BIT6
BIT3
BIT4
BIT5
CLOCK
PS0
PS1
PS2
0
1
2
3
4
6
7
5
8-1 MULTIPLEXER
BIT7
BIT2
BIT0
BIT1
BIT3
BIT4
BIT5
BIT6
8-BIT COUNTER
VA00186
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ST62T80B/E80B
TIMER (Cont’d)
4.2.3 Application Notes
If the Timer is programmed in output mode, the
DOUT bit is transferred to the TIMER pin when
TMZ is set to one (by software or due to counter
decrement). When TMZ is high, the latch is trans-
parent and DOUT is copied to the timer pin. When
TMZ goes low, DOUT is latched.
The user can select the presence of an on-chip
pull-up on the TIMER pin as option.
TMZ is set when the counter reaches zero; howev-
er, it may also be set by writing 00h in the TCR
register or by setting bit 7 of the TSCR register.
The TMZ bit must be cleared by user software
when servicing the timer interrupt to avoid unde-
sired interrupts when leaving the interrupt service
routine. After reset, the 8-bit counter register is
loaded with 0FFh, while the 7-bit prescaler is load-
ed with 07Fh, and the TSCR register is cleared.
This means that the Timer is stopped (PSI=“0”)
and the timer interrupt is disabled.
A write to the TCR register will predominate over
the 8-bit counter decrement to 00h function, i.e. if a
write and a TCR register decrement to 00h occur
simultaneously, the write will take precedence,
and the TMZ bit is not set until the 8-bit counter
reaches 00h again. The values of the TCR and the
PSC registers can be read accurately at any time.
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ST62T80B/E80B
4.3 AUTO-RELOAD TIMER
The Auto-Reload Timer (AR Timer) on-chip pe-
ripheral consists of an 8-bit timer/counter with
compare and capture/reload capabilities and of a
7-bit prescaler with a clock multiplexer, enabling
the prescaler and counter contents are frozen.
When TEN is set, the AR counter runs at the rate
of the selected clock source. The counter is
cleared on system reset.
the clock input to be selected as f , f
or an
INT INT/3
The AR counter may also be initialized by writing
to the ARLR load register, which also causes an
immediate copy of the value to be placed in the AR
counter, regardless of whether the counter is run-
ning or not. Initialization of the counter, by either
method, will also clear the ARPSC register, where-
upon counting will start from a known value.
external clock source. A Mode Control Register,
ARMC, two Status Control Registers, ARSC0 and
ARSC1, an output pin, ARTIMout, and an input
pin, ARTIMin, allow the Auto-Reload Timer to be
used in 4 modes:
– Auto-reload (PWM generation),
– Output compare and reload on external event
(PLL),
4.3.2 Timer Operating Modes
Four different operating modes are available for
the AR Timer:
– Input capture and output compare fortime meas-
urement.
Auto-reload Mode with PWM Generation. This
mode allows a Pulse Width Modulated signal to be
generated on the ARTIMout pin with minimum
Core processing overhead.
– Input capture and output compare for period
measurement.
The AR Timer can be used to wake the MCU from
WAIT mode either with an internal or with an exter-
nal clock. It also can be used to wake the MCU
from STOP mode, if used with an external clock
signal connected to the ARTIMin pin. A Load reg-
ister allows the program to read and write the
counter on the fly.
The free running 8-bit counter is fed by the pres-
caler’s output, and is incremented on every rising
edge of the clock signal.
When a counter overflow occurs, the counter is
automatically reloaded with thecontents of the Re-
load/Capture Register, ARCC, and ARTIMout is
set. When the counter reaches the value con-
tained in the compare register (ARCP), ARTIMout
is reset.
4.3.1 AR Timer Description
The AR COUNTER is an 8-bit up-counter incre-
mented on the input clock’s rising edge. The coun-
ter is loaded from the ReLoad/Capture Register,
ARRC, for auto-reload or capture operations, as
well as for initialization. Direct access to the AR
counter is not possible; however, by reading or
writing the ARLR load register, it is possible to
read or write the counter’s contents on the fly.
On overflow, the OVF flag of the ARSC0 register is
set and an overflow interrupt request is generated
if the overflow interrupt enable bit, OVIE, in the
Mode Control Register (ARMC), is set. The OVF
flag must be reset by the user software.
When the counter reaches the compare value, the
CPF flag of the ARSC0 register is set and a com-
pare interrupt request is generated, if the Compare
Interrupt enable bit, CPIE, in the Mode Control
Register (ARMC), is set. The interrupt service rou-
tine may then adjust the PWM period by loading a
new value into ARCP. The CPF flag must be reset
by user software.
The AR Timer’s input clock can be either the inter-
nal clock (from the Oscillator Divider), the internal
clock divided by 3, or the clock signal connected to
the ARTIMin pin. Selection between these clock
sources is effected by suitably programming bits
CC0-CC1 of the ARSC1 register. The output of the
AR Multiplexer feeds the 7-bit programmable AR
Prescaler, ARPSC, which selects one of the 8
available taps of the prescaler, as defined by
PSC0-PSC2 in the AR Mode Control Register.
Thus the division factor of the prescaler can be set
to 2n (where n = 0, 1,..7).
The PWM signal is generated on the ARTIMout
pin (refer to the Block Diagram). The frequency of
this signal is controlled by the prescaler setting
and by the auto-reload value present in the Re-
load/Capture register, ARRC. The duty cycle of
the PWM signal is controlled by the Compare Reg-
ister, ARCP.
The clock input to the AR counter is enabled by the
TEN (Timer Enable) bit in the ARMC register.
When TEN is reset, the AR counter is stopped and
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ST62T80B/E80B
AUTO-RELOAD TIMER (Cont’d)
Figure 23. AR Timer Block Diagram
DATA BUS
8
DDRB7
DRB7
AR COMPARE
REGISTER
8
PB7/
ARTIMout
CPF
COMPARE
8
R
S
PWMOE
OVF
OVF
f
INT
M
OVIE
8-Bit
7-Bit
f
/3
INT
U
X
AR PRESCALER
LOAD
AR COUNTER
TCLD
PS0-PS2
CC0-CC1
EIE
EF
AR TIMER
INTERRUPT
8
CPF
CPIE
8
8
PB6/
ARTIMin
SL0-SL1
AR
AR
EF
RELOAD/CAPTURE
REGISTER
LOAD
SYNCHRO
REGISTER
8
8
DATA BUS
VR01660A
44/78
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ST62T80B/E80B
AUTO-RELOAD TIMER (Cont’d)
It should be noted that the reload values will also
affect the value and the resolution of the duty cycle
of PWM output signal. To obtain a signal on ARTI-
Mout, the contents of the ARCP register must be
greater than the contents of the ARRC register.
The ARTC counter is initialized by writing to the
ARRC register and by then setting the TCLD (Tim-
er Load) and the TEN (Timer Clock Enable) bits in
the Mode Control register, ARMC.
Enabling and selection of the clock source is con-
trolled by the CC0, CC1, SL0 and SL1 bits in the
Status Control Register, ARSC1. The prescaler di-
vision ratio is selected by the PS0, PS1 and PS2
bits in the ARSC1 register.
The maximum available resolution for the ARTI-
Mout duty cycle is:
Resolution = 1/[255-(ARRC)]
Where ARRC is the content of the Reload/Capture
register. The compare value loaded in the Com-
pare Register, ARCP, must be in the range from
(ARRC) to 255.
In Auto-reload Mode, any of the three available
clock sources can be selected: Internal Clock, In-
ternal Clock divided by 3 or the clock signal
present on the ARTIMin pin.
Figure 24. Auto-reload Timer PWM Function
COUNTER
255
COMPARE
VALUE
RELOAD
REGISTER
000
t
PWM OUTPUT
t
VR001852
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ST62T80B/E80B
AUTO-RELOAD TIMER (Cont’d)
Capture Mode with PWM Generation. In this
mode, the AR counter operates as a free running
8-bit counter fed by the prescaler output. The
counter is incremented on every clock rising edge.
the count is incremented on every clock rising
edge.
Each counter overflow sets the ARTIMout pin. A
match between the counter and ARCP (Compare
Register) resets the ARTIMout pin and sets the
compare flag, CPF. A compare interrupt request is
generated if the related compare interrupt enable
bit, CPIE, is set. A PWM signal is generated on
ARTIMout. The CPF flag must be reset by user
software.
An 8-bit capture operation from the counter to the
ARRC register is performed on every active edge
on the ARTIMin pin, when enabled by Edge Con-
trol bits SL0, SL1 in the ARSC1 register. At the
same time, the External Flag, EF, in the ARSC0
register is set and an external interrupt request is
generated if the External Interrupt Enable bit, EIE,
in the ARMC register, is set. The EF flag must be
reset by user software.
Initialization of the counter is as described in the
previous paragraph. In addition, if the external AR-
TIMin input is enabled, an active edge on the input
pin will copy the contents of the ARRC register into
the counter, whether the counter is running or not.
Each ARTC overflow sets ARTIMout, while a
match between the counter and ARCP (Compare
Register) resets ARTIMout and sets the compare
flag, CPF. A compare interrupt request is generat-
ed if the related compare interrupt enable bit,
CPIE, is set. A PWM signal is generated on ARTI-
Mout. The CPF flag must be reset by user soft-
ware.
Notes:
The allowed AR Timer clock sources are the fol-
lowing:
AR Timer Mode
Auto-reload mode
Capture mode
Clock Sources
, f , ARTIMin
f
f
f
f
INT INT/3
The frequency of the generated signal is deter-
mined by the prescaler setting. The duty cycle is
determined by the ARCP register.
, f
INT INT/3
Capture/Reset mode
External Load mode
, f
INT INT/3
, f
INT INT/3
Initialization and reading of the counter are identi-
cal to the auto-reload mode (see previous descrip-
tion).
The clock frequency should not be modified while
the counter is counting, since the counter may be
set to an unpredictable value. For instance, the
multiplexer setting should not be modified while
the counter is counting.
Enabling and selection of clock sources is control-
led by the CC0 and CC1 bits in the AR Status Con-
trol Register, ARSC1.
Loading of the counter by any means (by auto-re-
load, through ARLR, ARRC or by the Core) resets
the prescaler at the same time.
The prescaler division ratio is selected by pro-
gramming the PS0, PS1 and PS2 bits in the
ARSC1 Register.
Care should be taken when both the Capture inter-
rupt and the Overflow interrupt are used. Capture
and overflow are asynchronous. If the capture oc-
curs when the Overflow Interrupt Flag, OVF, is
high (between counter overflow and the flag being
reset by software, in the interrupt routine), the Ex-
ternal Interrupt Flag, EF, may be cleared simul-
taneusly without the interrupt being taken into ac-
count.
In Capture mode, the allowed clock sources are
the internal clock and the internal clock divided by
3; the external ARTIMin input pin should not be
used as a clock source.
Capture Mode with Reset of counter and pres-
caler, and PWM Generation. This mode is identi-
cal to the previous one, with the difference that a
capture condition also resets the counter and the
prescaler, thus allowing easy measurement of the
time between two captures (for input period meas-
urement on the ARTIMin pin).
The solution consists in resetting the OVF flag by
writing 06h in the ARSC0 register. The value of EF
is not affected by this operation. If an interrupt has
occured, it will be processed when the MCU exits
from the interrupt routine (the second interrupt is
latched).
Load on External Input. The counter operates as
a free running 8-bit counter fed by the prescaler.
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ST62T80B/E80B
AUTO-RELOAD TIMER (Cont’d)
4.3.3 AR Timer Registers
AR Mode Control Register (ARMC)
Address: E5h — Read/Write
Reset status: 00h
ARSC0 register is also set, an interrupt request is
generated.
Bit 1-0 = ARMC1-ARMC0: Mode Control Bits 1-0.
These are the operating mode control bits. The fol-
lowing bit combinations will select the various op-
erating modes:
7
0
ARMC1
ARMC0
Operating Mode
Auto-reload Mode
Capture Mode
TCLD
TEN PWMOE
EIE
CPIE OVIE ARMC1 ARMC0
0
0
0
1
The AR Mode Control Register ARMC is used to
program the different operating modes of the AR
Timer, to enable the clock and to initialize the
counter. It can be read and written to by the Core
and it is cleared on system reset (the AR Timer is
disabled).
Capture Mode with Reset
of ARTC and ARPSC
1
1
0
1
Load on External Edge
Mode
AR Timer Status/Control Registers ARSC0 &
ARSC1. These registers contain the AR Timer sta-
tus information bits and also allow the program-
ming of clock sources, active edge and prescaler
multiplexer setting.
Bit 7 = TLCD: Timer Load Bit. This bit, when set,
will cause the contents of ARRC register to be
loaded into the counter and the contents of the
prescaler register, ARPSC, are cleared in order to
initialize the timer before starting to count. This bit
is write-only and any attempt to read it will yield a
logical zero.
ARSC0 register bits 0,1 and 2 contain the interrupt
flags of the AR Timer. These bits are read normal-
ly. Each one may be reset by software. Writing a
one does not affect the bit value.
Bit 6 = TEN: Timer Clock Enable. This bit, when
set, allows the timer to count. When cleared, it will
stop the timer and freeze ARPSC and ARTSC.
AR Status Control Register 0 (ARSC0)
Address: E6h
—
Read/Clear
Bit 5 = PWMOE: PWM Output Enable. This bit,
when set, enables the PWM output on the ARTI-
Mout pin. When reset, the PWM output is disabled.
7
0
D7
D6
D5
D4
D3
EF
CPF
OVF
Bit 4 = EIE: External Interrupt Enable. This bit,
when set, enables the external interrupt request.
When reset, the external interrupt request is
masked. If EIE is set and the related flag, EF, in
the ARSC0 register is also set, an interrupt re-
quest is generated.
Bits 7-3 = D7-D3: Unused
Bit 2= EF: External Interrupt Flag. This bit is set by
any active edge on the external ARTIMin input pin.
The flag is cleared by writing a zero to the EF bit.
Bit 3 = CPIE: Compare Interrupt Enable. This bit,
when set, enables the compare interrupt request.
If CPIE is reset, the compare interrupt request is
masked. IfCPIE is set and the related flag, CPF, in
the ARSC0 register is also set, an interrupt re-
quest is generated.
Bit 1 = CPF: Compare Interrupt Flag. This bit is set
if the contents of the counter and the ARCP regis-
ter are equal. The flag is cleared by writing a zero
to the CPF bit.
Bit 0 = OVF: Overflow Interrupt Flag. This bit is set
by a transition of the counter from FFh to 00h
(overflow). The flag is cleared by writing a zero to
the OVF bit.
Bit 2 = OVIE: Overflow Interrupt. This bit, when
set, enables the overflow interrupt request. If OVIE
is reset, the compare interrupt request is masked.
If OVIE is set and the related flag, OVF in the
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ST62T80B/E80B
AUTO-RELOAD TIMER (Cont’d)
AR Status Control Register 1(ARSC1)
Address: E7h — Read/Write
AR Load Register ARLR. The ARLR load register
is used to read or write the ARTC counter register
“on the fly” (while it is counting). The ARLR regis-
ter is not affected by system reset.
7
0
AR Load Register (ARLR)
PS2
PS1
PS0
D4
SL1
SL0
CC1
CC0
Address: EBh
— Read/Write
Bist 7-5 = PS2-PS0: Prescaler Division Selection
Bits 2-0. These bits determine the Prescaler divi-
sion ratio. The prescaler itself is not affected by
these bits.Theprescaler division ratioislisted inthe
following table:
7
0
D7
D6
D5
D4
D3
D2
D1
D0
Bit 7-0 = D7-D0: Load Register Data Bits. These
are the load register data bits.
Table 15. Prescaler Division Ratio Selection
PS2
0
PS1
0
PS0
0
ARPSC Division Ratio
AR Reload/Capture Register. The ARRC re-
load/capture register is used to hold the auto-re-
load value which is automatically loaded into the
counter when overflow occurs.
1
2
0
0
1
0
1
0
4
0
1
1
8
AR Reload/Capture (ARRC)
1
0
0
16
32
64
128
Address: E9h
—
Read/Write
1
0
1
7
0
1
1
0
D7
D6
D5
D4
D3
D2
D1
D0
1
1
1
Bit 4 = D4: Reserved. Must be kept reset.
Bit 7-0 = D7-D0: Reload/Capture Data Bits. These
Bit 3-2= SL1-SL0: Timer InputEdgeControl Bits 1-
0. These bits control the edge function of the Timer
input pinforexternalsynchronization. IfbitSL0isre-
set, edgedetectionis disabled; ifset edge detection
is enabled.If bit SL1 is reset, the AR Timer input pin
is rising edge sensitive; if set, it is falling edge sen-
sitive.
are the Reload/Capture register data bits.
AR Compare Register. The CP compare register
is used to hold the compare value for the compare
function.
AR Compare Register (ARCP)
SL1
X
SL0
0
Edge Detection
Disabled
Address: EAh
— Read/Write
7
0
0
1
Rising Edge
Falling Edge
1
1
D7
D6
D5
D4
D3
D2
D1
D0
Bit 1-0 = CC1-CC0: Clock Source Select Bit 1-0.
These bits select the clock source for the AR Timer
through the AR Multiplexer. The programming of
the clocksources isexplainedin the following Table
16:
Bit 7-0 = D7-D0: Compare Data Bits. These are
the Compare register data bits.
Table 16. Clock Source Selection.
CC1
CC0
Clock Source
0
0
1
1
0
1
0
1
Fint
Fint Divided by 3
ARTIMin Input Clock
Reserved
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ST62T80B/E80B
4.4 U. A. R. T. (Universal Asynchronous Receiver/Transmitter)
The UART provides the basic hardware for asyn-
chronous serial communication which, combined
with an appropriate software routine, gives a serial
interface providing communication with common
baud rates (up to 38,400 Baud with an 8MHz ex-
ternal oscillator) and flexible character formats.
4.4.1 PORTS INTERFACING
RXD reception line and TXD emission line are
sharing the same external pins as two I/O lines.
Therefore, UART configuration requires to set
these two I/O lines through the relevant ports reg-
isters. The I/O line common with RXD line must be
defined as input mode (with or without pull-up)
while the I/O line common with TXD line must be
defined as output mode (Push-pull or open drain).
The transmitted data is inverted and can therefore
use a single transistor buffering stage. Defined as
input, the RXD line can be read at any time as an
I/O line during the UART operation. The TXD pin
follows I/O port registers value when UARTOE bit
is cleared, which means when no serial transmis-
sion is in progress. As a consequence, a perma-
nent high level has to be written onto the I/O port in
order to achieve a proper stop condition on the
TXD line when no transmission is active.
Operating in Half-Duplex mode only, the UART
uses 11-bitcharacters comprising 1 start bit, 9 data
bits and 1 Stop bit. Parity is supported by software
only for transmit and for checking the received par-
ity bit (bit 9). Transmitted data is sent directly, while
received data is buffered allowing further data
characters to be received while the data is being
read out of the receive buffer register. Data trans-
mit has priority over data being received.
The UART is supplied with an MCU internal clock
that isalso available inWAITmodeof theprocessor.
Figure 25. UART Block Diagram
START
DETECTOR
RXD1
UARTOE
TXD
1
DIN
DOUT
DATA SHIFT
REGISTER
MUX
TXD1
DR
0
D8 D7 D6 D5 D4 D3 D2 D1 D0
WRITE
READ
RECEIVE BUFFER
REGISTER
D9
CONTROL REGISTER
BAUD RATE
RX and TX
INTERRUPTS
PROGRAMMABLE
DIVIDER
f
OSC
BAUD RATE x 8
VR02009
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ST62T80B/E80B
4.4.2 CLOCK GENERATION
The character options are summarised in the fol-
lowing table.
The UART contains a built-in divider of the MCU
internal clock for most common Baud Rates as
shown in Table 18. Other baud rate values can be
calculated from the chosen oscillator frequency di-
vided by the Divisor value shown.
Table 17. Character Options
Start Bit
Start Bit
Start Bit
Start Bit
8 Data
9 Data
8 Data
7 Data
1 Software Parity
No Parity
1 Stop
1 Stop
2 Stop
2 Stop
The divided clock provides a frequency that is 8
times the desired baud rate. This allows the Data
reception mechanism to provide a 2 to 1 majority
voting system to determine the logic state of the
asynchronous incoming serial logic bit by taking 3
timed samples within the 8 time states.
No Parity
1 Software Parity
Bit 9 remains in the state programmed for consec-
utive transmissions until changed by the user or
until a character is received when the state of this
bit is changed to that of the incoming bit 9. The
recommended procedure is thus to set the value of
this bit before transmission is started.
The bits not sampled provide a buffer to compen-
sate for frequency offsets between sender and re-
ceiver.
Transmission is started by writing to the Data Reg-
ister (the Baud Rate and Bit 9 should be set before
this action). The UARTOE signal switches the out-
put multiplexer to the UART output and a start bit
is sent (a 0 for one bit time) followed by the 8 data
values (lsb first) and the value of the Bit9 bit. The
output is then set to 1 for a period of one bit time to
generate a Stop bit, and then the UARTOE signal
returns the TXD1 line to its alternate I/O function.
The end of transmission is flagged by setting
TXMT to 1 and an interrupt is generated if ena-
bled. The TXMT flag is reset by writing a 0 to the
bit position, it is also cleared automatically when a
new character is written to the Data Register.
TXMT can be set to 1 by software to generate a
software interrupt so care must be taken in manip-
ulating the Control Register.
4.4.3 DATA TRANSMISSION
Transmission is fixed to a format of one start bit,
nine data bits and one stop bit. The start and stop
bits are automatically generated by the UART. The
nine databits are under control of the user and are
flexible in use. Bits 0..7 are typically used as data
bits while bit 9 is typically used as parity, but can
also be a 9th data bit or an additional Stop bit. As
parity is not generated by the UART, it should be
calculated by program and inserted in the appro-
priate position of the data (i.e as bit 7 for 7-bit data,
with Bit 9 set to 1 giving two effective stop bits or
as the independent bit 9).
Figure 26. Data Sampling Points
Figure 27. Character Format
START
BIT
STOP
BIT
1 BIT
D0 D1
D7 D8
BIT
POSITION
2
8
9
1
10
POSSIBLE
NEXT
0
1
2
3
4
5
6
7
8
CHARACTER
START
START OF DATA
SAMPLES
VR02010
VR02012
50/78
50
ST62T80B/E80B
4.4.4 DATA RECEPTION
4.4.5 INTERRUPT CAPABILITIES
The UART continuously looks for a falling edge on
the input pin whenever a transmission is not ac-
tive. Once an edge is detected it waits 1 bit time (8
states) to accommodate the Start bit, and then as-
sembles the following serial data stream into the
data register. The data in the ninth bit position is
copied into Bit 9, replacing any previous value set
for transmission. After all 9 bits have been re-
ceived, the Receiver waits for the duration of one
bit (for the Stop bit) and then transfers the received
data into the buffer register, allowing a following
character to be received. The interrupt flag
RXRDY is set to 1 as the data is transferred to the
buffer register and, if enabled, will generate an in-
terrupt.
Both reception and transmission processes can in-
duce interrupt to the core as defined in the inter-
rupt section. These interrupts are enabled by set-
ting TXIEN and RXIEN bit in the UARTCR register,
and TXMT and RXRDY flags are set accordingly
to the interrupt source.
4.4.6 REGISTERS
UART Data Register (UARTDR)
Address: D6h, Read/Write
7
0
D7
D6
D5
D4
D3
D2
D1
D0
Bit7-Bit0. UART data bits. A write to this register
loads the data into the transmit shift register and
triggers the start of transmission. In addition this
resets the transmit interrupt flag TXMT. A read of
this register returns the data from the Receive
buffer.
If a transmission is started during the course of a
reception, the transmission takes priority and the
reception is stopped to free the resources for the
transmission. This implies that a handshaking sys-
tem must be implemented, as polling of the UART
to detect reception is not available.
Warning. No Read/Write Instructions may be
used with this register as both transmit and receive
share the same address
Figure 28. UART Data Output
UARTOE
TXD
1
MUX
TXD1
PORT DATA
OUTPUT
0
VR02011
Table 18. Baud Rate Selection
Baud Rate
BR2
BR2
BR0
f
Division
INT
f
= 8MHz
1200
f
= 4MHz
600
INT
INT
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
6.656
3.328
1.664
832
2400
1200
2400
4800
9600
4800
9600
416
19200
31200
256
15600
19200
208
38400
Reserved
51/78
51
ST62T80B/E80B
REGISTERS (Cont’d)
UART Control Register (UARTCR)
Address: D7h, Read/Write
7
Writing to RXIEN does not affect the status of the
interrupt flag RXRDY.
Bit 4 = TXIEN. Transmit Interrupt Enable. When
this bit is set to 1, the transmit interrupt is enabled.
Writing to TXIEN does not affect the status of the
interrupt flag TXRDY.
0
RXRDY TXMT RXIEN TXIEN BR2
BR1
BR0 DAT9
Bit 7 = RXRDY. Receiver Ready. This flag be-
comes active as soon as a complete byte has
been received and copied into the receive buffer. It
may be cleared by writing a zero to it. Writing a
one is possible. If the interrupt enable bit RXIEN is
set to one, a software interrupt will be generated.
Bit 3-1= BR2..BR0. Baudrate select. These bits
select the operating baud rate of the UART, de-
pending on the frequency of fOSC. Care should be
taken not to change these bits during communica-
tion as writing to these bits has an immediate ef-
fect.
Bit 6 = TXMT. Transmitter Empty. This flag be-
comes active as soon as a complete byte has
been sent. It may be cleared by writing a zero to it.
It is automatically cleared by the action of writing a
data value into the UART data register.
Bit 0 = DAT9. Parity/Data Bit 9. This bit represents
the 9th bit of the data character that is received or
transmitted. A write to this bit sets the level for the
bit 9 to be transmitted, so it must always be set to
the correct level before transmission. If used as
parity, the value has first to be calculated by soft-
ware. Reading this bit will return the 9th bit of the
received character.
Bit 5 = RXIEN. Receive Interrupt Enable. When
this bit is set to 1, the receive interrupt is enabled.
52/78
52
ST62T80B/E80B
4.5 A/D CONVERTER (ADC)
The A/D converter peripheral is an 8-bit analog to
digital converter with analog inputs as alternate I/O
functions (the number of which is device depend-
ent), offering 8-bit resolution with a typical conver-
sion time of 70us (at an oscillator clock frequency
of 8MHz).
sion to allow stabilisation of the A/D converter.
This action is also needed before entering WAIT
mode, since the A/D comparator is not automati-
cally disabled in WAIT mode.
During Reset, any conversion in progress is
stopped, thecontrol register is reset to 40h and the
ADC interrupt is masked (EAI=0).
The ADC converts the input voltage by a process
of successive approximations, using a clock fre-
quency derived from the oscillator with a division
factor of twelve. With an oscillator clock frequency
less than 1.2MHz, conversion accuracy is de-
creased.
Figure 29. ADC Block Diagram
INTERRUPT
CLOCK
Selection of the input pin is done by configuring
the related I/O line as an analog input via the Op-
tion and Data registers (refer to I/O ports descrip-
tion for additional information). Only one I/O line
must be configured as an analog input at any time.
The user must avoid any situation in which more
than one I/O pin is selected as an analog input si-
multaneously, to avoid device malfunction.
Ain
CONVERTER
RESET
AV
AV
SS
DD
CONTROL REGISTER
8
RESULT REGISTER
8
The ADC uses two registers in the data space: the
ADC data conversion register, ADR, which stores
the conversion result, and the ADC control regis-
ter, ADCR, used to program the ADC functions.
CORE
CORE
CONTROL SIGNALS
VA00418
A conversion is started by writing a “1” to the Start
bit (STA) in the ADC control register. This auto-
matically clears (resets to “0”) the End Of Conver-
sion Bit (EOC). When a conversion is complete,
the EOC bit is automatically set to “1”, in order to
flag that conversion is complete and that the data
in the ADC data conversion register is valid. Each
conversion has to be separately initiated by writing
to the STA bit.
4.5.1 Application Notes
The A/D converter does not feature a sample and
hold circuit. The analog voltage to be measured
should therefore be stable during the entire con-
version cycle. Voltage variation should not exceed
±1/2 LSB for the optimum conversion accuracy. A
low pass filter may be used at the analog input
pins to reduce input voltage variation during con-
version.
The STA bit is continuously scanned so that, if the
user sets it to “1” while a previous conversion is in
progress, a new conversion is started before com-
pleting the previous one. The start bit (STA) is a
write only bit, any attempt to read it will show a log-
ical “0”.
When selected as an analog channel, the input pin
is internally connected to a capacitor C of typi-
ad
cally 12pF. For maximum accuracy, this capacitor
must be fully charged at the beginning of conver-
sion. In the worst case, conversion starts one in-
struction (6.5 µs) after the channel has been se-
lected. In worst case conditions, the impedance,
ASI, of the analog voltage source is calculated us-
ing the following formula:
The A/D converter features a maskable interrupt
associated with the end of conversion. This inter-
rupt is associated with interrupt vector #4 and oc-
curs when the EOC bit is set (i.e. when a conver-
sion is completed). The interrupt is masked using
the EAI (interrupt mask) bit in the control register.
6.5µs = 9 x C x ASI
ad
(capacitor charged to over 99.9%), i.e. 30 kΩ in-
cluding a 50% guardband. ASI can be higher if C
has been charged for a longer period by adding in-
structions before the start of conversion (adding
more than 26 CPU cycles is pointless).
The power consumption of the device can be re-
duced by turning off the ADC peripheral. This is
done by setting the PDS bit in the ADC control reg-
ister to “0”. If PDS=“1”, the A/D is powered and en-
abled for conversion. This bit must be set at least
one instruction before the beginning of the conver-
ad
53/78
53
ST62T80B/E80B
A/D CONVERTER (Cont’d)
Since the ADC is on the same chip as the micro-
processor, the user should not switch heavily load-
ed output signals during conversion, if high preci-
sion is required. Such switching will affect the sup-
ply voltages used as analog references.
up the microcontroller could also be done using
the Timer interrupt, but in this case the Timer will
be working and the resulting noise could affect
conversion accuracy.
A/D Converter Control Register (ADCR)
The accuracy of the conversion depends on the
Address: 0D1h
— Read/Write
quality of the power supplies (V
and V ). The
DD
SS
user must take special care to ensure a well regu-
lated reference voltage is present on the V and
7
0
DD
EAI
EOC
STA
PDS
D3
D2
D1
D0
V
pins (power supply voltage variations must be
SS
less than 5V/ms). This implies, in particular, that a
suitable decoupling capacitor is used at the V
pin.
DD
Bit 7 = EAI: Enable A/D Interrupt. If this bit is set to
“1” the A/D interrupt is enabled, when EAI=0 the
interrupt is disabled.
The converter resolution is given by::
Bit 6 = EOC: End of conversion. Read Only. This
read only bit indicates when a conversion has
been completed. This bit is automatically reset to
“0” when the STA bit is written. If the user is using
the interrupt option then this bit can be used as an
interrupt pending bit. Data in the data conversion
register are valid only when this bit is set to “1”.
V
DD – VSS
----------------------------
256
The Input voltage (Ain) which is to be converted
must be constant for 1µs before conversion and
remain constant during conversion.
Bit 5 = STA: Start of Conversion. Write Only. Writ-
ing a “1” to this bit will start a conversion on the se-
lected channel and automatically reset to “0” the
EOC bit. If the bit is set again when a conversion is
in progress, the present conversion is stopped and
a new one will take place. This bit is write only, any
attempt to read it will show a logical zero.
Conversion resolution can be improved if the pow-
er supply voltage (V ) to the microcontroller is
DD
lowered.
In orderto optimise conversion resolution, the user
can configure the microcontroller in WAIT mode,
because this mode minimises noise disturbances
and power supply variations due to output switch-
ing. Nevertheless, the WAIT instruction should be
executed as soon as possible after the beginning
of the conversion, because execution of the WAIT
Bit 4 = PDS: Power Down Selection. This bit acti-
vates the A/D converter if set to “1”. Writing a “0” to
this bit will put the ADC in power down mode (idle
mode).
Bit 3-0 = D3-D0. Not used
instruction may cause a small variation of the V
DD
voltage. The negative effect of this variation is min-
imized at the beginning of the conversion when the
converter is less sensitive, rather than at the end
of conversion, when the less significant bits are
determined.
A/D Converter Data Register (ADR)
Address: 0D0h
— Read only
7
0
The best configuration, from an accuracy stand-
point, is WAIT mode with the Timer stopped. In-
deed, only the ADC peripheral and the oscillator
are then still working. The MCU must be woken up
from WAIT mode by the ADC interrupt at the end
of the conversion. It should be noted that waking
D7
D6
D5
D4
D3
D2
D1
D0
Bit 7-0 = D7-D0: 8 Bit A/D Conversion Result.
54/78
54
ST62T80B/E80B
4.6 SERIAL PERIPHERAL INTERFACE (SPI)
The on-chip SPI is an optimized serial synchro-
nous interface that supports a wide range of indus-
try standard SPI specifications. The on-chip SPI is
controlled by small and simple user software to
perform serial data exchange. The serial shift
clock can be implemented either by software (us-
ing the bit-set and bit-reset instructions), with the
on-chip Timer 1 by externally connecting the SPI
clock pin to the timer pin or by directly applying an
external clock to the Scl line.
operation Sout has to be programmed as open-
drain output.
The SCL, Sin and Sout SPI clock and data signals
are connected to 3 I/O lines on the same external
pins. With these 3 lines, the SPI can operate in the
following operating modes: Software SPI, S-BUS,
I C-bus and as a standard serial I/O (clock, data,
enable). An interrupt request can be generated af-
ter eight clock pulses. Figure 30 shows the SPI
block diagram.
The peripheral is composed by an 8-bit Data/shift
Register and a 4-bit binary counter while the Sin
pin is the serial shift input and Sout is the serial
shift output. These two lines can be tied together
to implement two wires protocols (I C-bus, etc).
When data is serialized, the MSB is thefirst bit. Sin
has to be programmed as input. For serial output
The SCL line clocks, on the falling edge, the shift
register and the counter. To allow SPI operation in
slave mode, the SCL pin must be programmed as
input and an external clock must be supplied to
this pin to drive the SPI peripheral.
In master mode, SCL is programmed as output, a
clock signal must be generated by software to set
and reset the port line.
Figure 30. SPI Block Diagram
SPI Interrupt Disable Register
Write
SPI Data Register
Read
CLK
RESET
SCL
I/O Port
Data Reg
Direction
Set Res
DIN
Q4
Q4
RESET
4-Bit Counter
CP
(Q4=High after Clock8)
Sin
I/O Port
Data Reg
Direction
Interrupt
Reset
Load
8-Bit Data
Shift Register
CP
DIN
DOUT
Output
Enable
8-Bit Tristate Data I/O
OPR Reg.
Sout
I/O Port
0
1
DOUT
D0.............. ......... .....D7
to Processor Data Bus
Data Reg
Direction
VR01504
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ST62T80B/E80B
SERIAL PERIPHERAL INTERFACE (Cont’d)
After 8 clock pulses (D7..D0) the output Q4 of the
4-bit binary counter becomes low, disabling the
clock from the counter and the data/shift register.
Q4 enables the clock to generate an interrupt on
the 8th clock falling edge as long as no reset of the
counter (processor write into the 8-bit data/shift
register) takes place. After a processor reset the
interrupt is disabled. The interrupt is active when
writing data in the shift register and desactivated
when writing any data in the SPI Interrupt Disable
register.
As it is possible to directly read the Sin pin directly
through the port register, the software can detect a
difference between internal data and external data
(master mode). Similar condition can be applied to
the clock.
Three (Four) Wire Serial Bus
It is possible to use a single general purpose I/O
pin (with the corresponding interrupt enabled) as a
chip enable pin. SCL acts as active or passive
clock pin, Sin as data in and Sout as data out (four
wire bus). Sin and Sout can be connected together
externally to implement three wire bus.
The generation of an interrupt to the Core provides
information that new data is available (input mode)
or that transmission is completed (output mode),
allowing the Core to generate an acknowledge on
the 9th clock pulse (I C-bus).
Note:
When the SPI is not used, the three I/O lines (Sin,
SCL, Sout) can be used as normal I/O, with the fol-
lowing limitation: bit Sout cannot be used in open
drain mode as this enables the shift register output
to the port.
The interrupt is initiated by a high to low transition,
and therefore interrupt options must be set accord-
ingly as defined in the interrupt section.
It is recommended, in order to avoid spurious in-
terrupts from the SPI, to disable the SPI interrupt
(the default state after reset) i.e. no write must be
made to the 8-bit shift register. An explicit interrupt
disable may be made in software by a dummy
write to the SPI interrupt disable register.
After power on reset, or after writing the data/shift
register, the counter is reset to zero and the clock
is enabled. In this condition the data shift register
is ready for reception. No start condition has to be
detected. Through the user software the Core may
pull down the Sin line (Acknowledge) and slow
down the SCL, as long as it is needed to carry out
data from the shift register.
SPI Data/Shift Register
Address: DDh - Read/Write (SDSR)
I C-bus Master-Slave, Receiver-Transmitter
7
0
When pins Sin and Sout are externally connected
together it is possible to use the SPI as a receiver
as well as a transmitter. Through software routine
(by using bit-set and bit-reset on I/O line) a clock
can be generated allowing I C-bus to work in mas-
ter mode.
D7
D6
D5
D4
D3
D2
D1
D0
A write into this register enables SPI Interrupt after
8 clock pulses.
When implementing an I C-bus protocol, the start
condition can be detected by setting the processor
into a wait for start condition by enabling the inter-
rupt of the I/O port used for the Sin line. This frees
the processor from polling the Sin and SCL lines.
After the transmission/reception the processor has
to poll for the STOP condition.
SPI Interrupt Disable Register
Address: C2h - Read/Write (SIDR)
7
0
D7
D6
D5
D4
D3
D2
D1
D0
In slave mode the user software can slow down
the SCL clock frequency by simply putting the SCL
I/O line in output open-drain mode and writing a
zero into the corresponding data register bit.
A dummy write to this register disables SPI Inter-
rupt.
56/78
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ST62T80B/E80B
4.7 LCD CONTROLLER-DRIVER
On-chip LCD driver includes all features required
for LCD driving, including multiplexing of the com-
mon plates. Multiplexing allows to increase display
capability without increasing the number of seg-
ment outputs. In that case, the display capability is
equal to the product of the number of common
plates with the number of segment outputs.
quartz values. In case of oscillator failure, all seg-
ment and common lines are switched to ground to
avoid any DC biasing of the LCD elements.
Table 19. Oscillator Selection Bits
MCU
Oscillator HF2 HF1 HF0
fOSC
Division Factor
A dedicated LCD RAM is used to store the pattern
to be displayed while control logic generates ac-
cordingly all the waveforms sent onto the segment
or common outputs. Segments voltage supply is
MCU supply independant, and included driving
stages allow direct connection to the LCD panel.
0
0
1
1
1
0
1
0
0
1
0
1
0
1
0
Clock disabled: Display off
1.048MHz
2.097MHz
4.194MHz
8.388MHz
32
64
128
256
The multiplexing ratio (Number of common plates)
and the base LCD frame frequency is software
configurable to achieve the best trade-off con-
trast/display capability for each display panel.
Notes:
1. The usage fOSC values different from those
defined in this table cause the LCD to operate at a
reference frequency different from 32.768KHz, ac-
cording to division factor of Table 19.
The 32Khz clock used for the LCD controller is
derivated from the MCU’s internal clock and there-
fore does not require a dedicated oscillator. The
division factor is set by the three bits HF0..HF2 of
the LCD Mode Control Register LCDCR as sum-
marized in Table 19 for recommanded oscillator
2. It is not recommended to select an internal
frequency lower than 32.768KHz as the clock su-
pervisor circuit may switch off the LCD peripheral
if lower frequency is detected.
Figure 31. LCD Block Diagram
3/5
VLCD
1/5
2/5
4/5
VLCD
SEGMENTS
BACKPLANES
VLCD VLCD VLCD
VOLTAGE
DIVIDER
COMMON
DRIVER
SEGMENT
DRIVER
LCD
RAM
CONTROLLER
32KHz
CONTROL
REGISTER
f
int
CLOCK
SELECTION
OSC 32KHz
(When available)
DATA BUS
VR02099A
57/78
57
ST62T80B/E80B
LCD CONTROLLER-DRIVER (Cont”d)
4.7.1 Multiplexing ratio and frame frequency
setting
Figure 32. Bias Config for 1/2 Duty
VS
Up to 16 common plates COM1..COM16 can be
used for multiplexing ratio of 1/8, 1/11 and 1/16.
The selection is made by the bits MUX11 and
MUX16 of the LCDCR as shown in the Table 20.
Contrast
C5
VS
VLCD
Table 20. Multiplexing ratio
Contrast
VLCD
MUX11 MUX16 Display Mode Active backplanes
R5
C4
0
1
0
1
0
0
1
1
1/8 mux.ratio
1/11 mux.ratio
1/16 mux.ratio
-
COM1-8
C4
COM1-16
COM1-16
Reserved
VLCD 4/5
VLCD 3/5
VLCD 2/5
VLCD 1/5
R4
C3
R4
C3
If the 1/1 multiplexing ratio is chosen, LCD seg-
ments are refreshed with a frame frequency Flcd
derived from 32Khz clock with a division ratio de-
fined by the bits LF0..LF2 of the LCDCR.
VLCD 4/5
R3
C2
R3
C2
VLCD 3/5
VLCD 2/5
When ahigher multiplexing ratiois set,refreshment
frequency is decreased accordingly (Table 21).
R2
C1
R2
C1
Table 21. LCD Frame Frequency Selection
VLCD 1/5
Base
Frame Frequency f (Hz)
F
f
LF1 LF0
LCD
1/8
1/11
1/16
R1
R1
mux.ratio mux.ratio mux.ratio
(Hz)
128
170
256
512
0
1
0
1
1
1
0
0
1
1
128
170
256
512
93
64
85
GND
GND
124
186
372
128
256
1/5 bias
(1/16 MUX)
1/4 bias
(1/11, 1/8 MUX)
Reserved
R2 to R5 should be 1KΩ to 200KΩ
C1 to C5 should be 0µF to 0.3 µF
4.7.2 Segment and common plates driving
VR001662
LCD panels physical structure requires precise
timings and stepped voltage values on common
and segment outputs. Timings are managed by
the LCD controller, while voltages are generated
through an external resistive bridge. In 1/11 and
1/8 multiplexing mode, VLCD 2/5 and VLDCD 3/5
are shorted as seen on Figure 32.
Note: For display voltages V
< 4.5V the resis-
LCD
tivity of the divider may be too high for some appli-
cations (especially using 1/3 or 1/4 duty display
mode). In that case an external resistive divider
must be used to achieve the desired resistivity.
58/78
58
ST62T80B/E80B
LCD CONTROLLER-DRIVER (Cont”d)
Address Mapping of the Display Segments
If 1/16 duty cycle mode is selected (48 x 16 dot
matrix), RAM page 1 and 2 are used for display
data storage. In this case addresses 00 to 07 in
both pages are free for common data storage.
The LCD RAM is located in the ST6280B data
space in two pages of 64 bytes from addresses
00h to 3Fh. The LCD forms a matrix of 56 segment
lines (columns) and 8 backplane lines (rows) or 48
segment lines and 11 or 16 backplane lines ac-
cording to the chosen operating mode. Each bit of
the LCD RAM is mapped to one dot of the LCD
matrix, as described in Figure 33. If a bit is set, the
corresponding LCD dot is switched on; if it is reset,
the dos is switched off.
If 1/11 duty cycle mode is selected (48 x 11 dot
matrix), RAM pages 1 and 2 are used for display
data storage. In this case addresses 00 to 07 in
both pages and bits 3 to 7 in RAM page 2 are free
for common data storage.
In all display modes 16 bytes from address 38h to
3Fh in RAM pages 1 and 2 are free common data
storage.
If 1/8 duty cycle mode is selected (56 x 8 dot ma-
trix), only RAM page 1 is used for display data
storage. In this case page 2 is completely free for
common data storage.
After reset, the LCD RAM is not initialized and con-
tains arbitrary information. As the LCD control reg-
ister is reset, the LCD is completely switched off.
Figure 33. Addressing Mapping of the LCD RAM
1/11 MUX (48 x 11 = 528 dots
LCD-RAM Address
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
00
01
-
07
08
-
37
38
-
3E
3F Page 1
COM9
bit0
bit1
bit2
00
00
01
01
-
-
07
07
08
08
-
-
37
37
38
38
-
-
3E
3E
3F
COM10
COM11
Page 2
COM12
COM13
COM14
COM15
COM16
bit3
bit4
bit5
bit6
bit7
3F
5bitx48
free data
storage
S
E
G
S
E
G
S
E
G
S
E
G
S
E
G
1
2
-
8
9
-
56
16 bytes free for
data storage
16 bytes free for
data storage
59/78
59
ST62T80B/E80B
LCD CONTROLLER-DRIVER (Cont”d)
Addressing Mapping of the LCD RAM (Cont’d)
1/8 MUX (56 x 8 = 448 dots
LCD-RAM Address
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
00
01
-
07
08
-
37
38
-
3E
3F Page 1
S
E
G
S
E
G
S
E
G
S
E
G
S
E
G
1
2
-
8
9
-
56
16 bytes free for
data storage
LCD RAM Page 2: 64 bytes free for data storage
Addressing Mapping of the LCD RAM (Cont’d)
1/16 MUX (48 x 16 = 768 dots
LCD-RAM Address
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
00
01
-
07
08
-
37
38
-
3E
3F Page 1
COM9
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
00
00
01
01
-
-
07
07
08
08
-
-
37
37
38
38
-
-
3E
3E
3F
COM10
COM11
COM12
COM13
COM14
COM15
COM16
3F
Page 2
S
E
G
S
E
G
S
E
G
S
E
G
S
E
G
1
2
-
8
9
-
56
16 bytes free for
data storage
16 bytes free for
data storage
60/78
60
ST62T80B/E80B
LCD CONTROLLER-DRIVER (Cont”d)
4.7.3 Stand by or STOP operation mode
4.7.4 LCD Mode Control Register (LCDCR)
No clock from the main oscillator is available in
STOP mode for the LCD controller, and the con-
troller is switched off when the STOP instruction is
executed. All segment and common lines are then
switched to ground to avoid any DC biasing of the
LCD elements.
Address: DCh - Read/Write
7
0
MUX16 MUX11
HF2
HF1
HF0
-
LF1
LF0
Bits 7-6 = MUX16, MUX11. Multiplexing ratio se-
lect bits. These bits select the number of common
backplanes used by the LCD control.
Operation in STOP mode remain possible by
switching to the OSC32Khz, by setting the
HF0..HF2 bit of LCDCR accordingly (Table 22).
Care must be taken for the oscillator switching that
LCD function change is only effective at the end of
a frame. Therefore it must be guaranteed that
enough clock pulses are delivered before entering
into STOP mode. Otherwise the LCD function is
switched off at STOP instruction execution.
Bits 5-3 = HF0, HF1, HF2. Oscillator select bits.
These bits allow the LCD controller to be supplied
with the correct frequency when different high
main oscillator frequencies are selected as system
clock. Table 19 shows the set-up for different clock
crystals.
Bits 2 = Reserved.
Table 22. Oscillator Source Selection
Bits 1-0 = LF0, LF1. Base frame frequency select
bits. These bits control the LCD base operational
frequency of the LCD common lines.
HF2 HF1 HF0
Division Factor
Clock disabled: Display off
Auxiliary 32KHz oscillator
Reserved
0
0
0
1
0
0
1
0
1
0
LF0, LF1 define the 32KHz division factor as
shown in Table 23.
1
1
Reserved
Table 23. 32KHz Division Factor for Base
Frequency Selection
Others
Division from MCU f
INT
LF1 LF0
32KHz Division Factor
0
0
1
1
0
0
1
0
1
0
512
386
256
192
128
61/78
61
ST62T80B/E80B
5 SOFTWARE
5.1 ST6 ARCHITECTURE
The ST6 software has been designed to fully use
the hardware in the most efficient way possible
while keeping byte usage to a minimum; in short,
to provide byte efficient programming capability.
The ST6 core has the ability to set or clear any
register or RAM location bit of the Data space with
a single instruction. Furthermore, the program
may branch to a selected address depending on
the status of any bit of the Data space. The carry
bit is stored with the value of the bit when the SET
or RES instruction is processed.
bits of the opcode with the byte following the op-
code. The instructions (JP, CALL) which use the
extended addressing mode are able to branch to
any address of the 4K bytes Program space.
An extended addressing mode instruction is two-
byte long.
Program Counter Relative. The relative address-
ing mode is only used in conditional branch in-
structions. The instruction is used to perform a test
and, if the condition is true, a branch with a span of
-15 to +16 locations around the address of the rel-
ative instruction. If the condition is not true, the in-
struction which follows the relative instruction is
executed. The relative addressing mode instruc-
tion is one-byte long. The opcode is obtained in
adding the three most significant bits which char-
acterize the kind of the test, one bit which deter-
mines whether the branch is a forward (when it is
0) or backward (when it is 1) branch and the four
less significant bits which give the span of the
branch (0h to Fh) which must be added or sub-
tracted to the address of the relative instruction to
obtain the address of the branch.
5.2 ADDRESSING MODES
The ST6 core offers nine addressing modes,
which are described in the following paragraphs.
Three different address spaces are available: Pro-
gram space, Data space, and Stack space. Pro-
gram space contains the instructions which are to
be executed, plus the data for immediate mode in-
structions. Data space contains the Accumulator,
the X,Y,V and W registers, peripheral and In-
put/Output registers, the RAM locations and Data
ROM locations (for storage of tables and con-
stants). Stack space contains six 12-bit RAM cells
used to stack the return addresses for subroutines
and interrupts.
Bit Direct. In the bit direct addressing mode, the
bit to be set or cleared is part of the opcode, and
the byte following the opcode points to the ad-
dress of the byte in which the specified bit must be
set or cleared. Thus, any bit in the 256 locations of
Data space memory can be set or cleared.
Immediate. In the immediate addressing mode,
the operand of the instruction follows the opcode
location. Asthe operand is a ROM byte, the imme-
diate addressing mode is used to access con-
stants which do not change during program execu-
tion (e.g., a constant used to initialize a loop coun-
ter).
Bit Test & Branch. The bit test and branch ad-
dressing mode is a combination of direct address-
ing and relative addressing. The bit test and
branch instruction is three-byte long. The bit iden-
tification and the tested condition are included in
the opcode byte. The address of the byte to be
tested follows immediately the opcode in the Pro-
gram space. The third byte is the jump displace-
ment, which is in the range of -127 to +128. This
displacement can be determined using a label,
which is converted by the assembler.
Direct. In the direct addressing mode, the address
of the byte which is processed by the instruction is
stored in the location which follows the opcode. Di-
rect addressing allows the user to directly address
the 256 bytes in Data Space memory with a single
two-byte instruction.
Short Direct. The core can address the four RAM
registers X,Y,V,W (locations 80h, 81h, 82h, 83h) in
the short-direct addressing mode. In this case, the
instruction is only one byte and the selection of the
location to be processed is contained in the op-
code. Short direct addressing is a subset of the di-
rect addressing mode. (Note that 80h and 81h are
also indirect registers).
Indirect. In the indirect addressing mode, the byte
processed by the register-indirect instruction is at
the address pointed by the content of one of the in-
direct registers, X or Y (80h,81h). The indirect reg-
ister is selected by the bit 4 of the opcode. A regis-
ter indirect instruction is one byte long.
Inherent. In the inherent addressing mode, all the
information necessary to execute the instruction is
contained in the opcode. These instructions are
one byte long.
Extended. In the extended addressing mode, the
12-bit address needed to define the instruction is
obtained by concatenating the four less significant
62/78
62
ST62T80B/E80B
5.3 INSTRUCTION SET
The ST6 core offers a set of 40 basic instructions
which, when combined with nine addressing
modes, yield 244 usable opcodes. They can be di-
vided into six different types: load/store, arithme-
tic/logic, conditional branch, control instructions,
jump/call, and bit manipulation. The following par-
agraphs describe the different types.
Load & Store. These instructions use one, two or
three bytes in relation with the addressing mode.
One operand is the Accumulator for LOAD and the
other operand is obtained from data memory using
one of the addressing modes.
For Load Immediate one operand can be any of
the 256 data space bytes while the other is always
immediate data.
All the instructions belonging to a given type are
presented in individual tables.
Table 24. Load & Store Instructions
Flags
Instruction
LD A, X
Addressing Mode
Short Direct
Bytes
Cycles
Z
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
*
C
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
1
1
1
1
1
1
1
1
2
2
1
1
1
1
2
3
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
LD A, Y
LD A, V
LD A, W
LD X, A
LD Y, A
Short Direct
Short Direct
Short Direct
Short Direct
Short Direct
Short Direct
Short Direct
Direct
LD V, A
LD W, A
LD A, rr
LD rr, A
Direct
LD A, (X)
LD A, (Y)
LD (X), A
LD (Y), A
LDI A, #N
LDI rr, #N
Indirect
Indirect
Indirect
Indirect
Immediate
Immediate
Notes:
X,Y. Indirect Register Pointers, V & W Short Direct Registers
# . Immediate data (stored in ROM memory)
rr. Data space register
∆. Affected
* . Not Affected
63/78
63
ST62T80B/E80B
INSTRUCTION SET (Cont’d)
Arithmetic and Logic. These instructions are
used to perform the arithmetic calculations and
logic operations. In AND, ADD, CP, SUB instruc-
tions one operand is always the accumulator while
the other can be either a data space memory con-
tent or an immediate value in relation with the ad-
dressing mode. In CLR, DEC, INC instructions the
operand can be any of the 256 data space ad-
dresses. In COM, RLC, SLA the operand is always
the accumulator.
Table 25. Arithmetic & Logic Instructions
Flags
Instruction
ADD A, (X)
Addressing Mode
Indirect
Bytes
Cycles
Z
∆
∆
∆
∆
∆
∆
∆
∆
∆
*
C
∆
∆
∆
∆
∆
∆
∆
∆
∆
*
1
1
2
2
1
1
2
2
2
3
1
1
1
2
2
1
1
1
1
2
2
1
1
1
1
1
1
2
2
1
1
1
2
1
1
2
2
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
ADD A, (Y)
ADD A, rr
ADDI A, #N
AND A, (X)
AND A, (Y)
AND A, rr
ANDI A, #N
CLR A
Indirect
Direct
Immediate
Indirect
Indirect
Direct
Immediate
Short Direct
Direct
CLR r
COM A
Inherent
Indirect
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
*
CP A, (X)
CP A, (Y)
CP A, rr
CPI A, #N
DEC X
Indirect
Direct
Immediate
Short Direct
Short Direct
Short Direct
Short Direct
Direct
DEC Y
*
DEC V
*
DEC W
*
DEC A
*
DEC rr
Direct
*
DEC (X)
DEC (Y)
INC X
Indirect
*
Indirect
*
Short Direct
Short Direct
Short Direct
Short Direct
Direct
*
INC Y
*
INC V
*
INC W
*
INC A
*
INC rr
Direct
*
INC (X)
Indirect
*
INC (Y)
Indirect
*
RLC A
Inherent
Inherent
Indirect
∆
∆
∆
∆
∆
∆
SLA A
SUB A, (X)
SUB A, (Y)
SUB A, rr
SUBI A, #N
Indirect
Direct
Immediate
Notes:
X,Y.Indirect Register Pointers, V & W Short Direct RegistersD. Affected
# . Immediate data (stored in ROM memory)* . Not Affected
rr. Data space register
64/78
64
ST62T80B/E80B
INSTRUCTION SET (Cont’d)
Conditional Branch. The branch instructions
achieve a branch in the program when the select-
ed condition is met.
Control Instructions. The control instructions
control the MCU operations during program exe-
cution.
Bit Manipulation Instructions. These instruc-
tions can handle any bit in data space memory.
One group either sets or clears. The other group
(see Conditional Branch) performs the bit test
branch operations.
Jump and Call. These two instructions are used
to perform long (12-bit) jumps or subroutines call
inside the whole program space.
Table 26. Conditional Branch Instructions
Flags
Instruction
Branch If
Bytes
Cycles
Z
*
*
*
*
*
*
C
*
JRC e
C = 1
1
1
1
1
3
3
2
2
2
2
5
5
JRNC e
C = 0
Z = 1
*
JRZ e
*
JRNZ e
Z = 0
*
JRR b, rr, ee
JRS b, rr, ee
Bit = 0
Bit = 1
∆
∆
Notes:
b.
e.
3-bit address
rr. Data space register
∆ . Affected. The tested bit is shifted into carry.
5 bit signed displacement in the range -15 to +16<F128M>
ee. 8 bit signed displacement in the range -126 to +129
* . Not Affected
Table 27. Bit Manipulation Instructions
Flags
Instruction
Addressing Mode
Bytes
Cycles
Z
C
*
SET b,rr
Bit Direct
Bit Direct
2
2
4
4
*
*
RES b,rr
*
Notes:
b.
3-bit address;
* . Not<M> Affected
rr. Data space register;
Table 28. Control Instructions
Flags
Instruction
Addressing Mode
Bytes
Cycles
Z
*
C
*
NOP
Inherent
Inherent
Inherent
Inherent
Inherent
1
1
1
1
1
2
2
2
2
2
RET
*
*
RETI
∆
*
∆
*
STOP (1)
WAIT
*
*
Notes:
1.
This instruction is deactivated<N>and a WAIT is automatically executed instead of a STOP if the watchdog function is selected.
∆ . Affected
*.
Not Affected
Table 29. Jump & Call Instructions
Instruction
Flags
Addressing Mode
Bytes
Cycles
Z
*
C
*
CALL abc
JP abc
Extended
Extended
2
2
4
4
*
*
Notes:
abc. 12-bit address;
* . Not Affected
65/78
65
ST62T80B/E80B
Opcode Map Summary. The following table contains an opcode map for the instructions used by the ST6
LOW
LOW
0
0000
1
0001
2
0010
3
0011
4
0100
5
0101
6
0110
7
0111
HI
HI
2
JRNZ
4
CALL
abc
ext
CALL
abc
ext
CALL
abc
ext
CALL
abc
ext
CALL
abc
ext
CALL
abc
ext
CALL
abc
ext
CALL
abc
ext
CALL
abc
ext
CALL
abc
ext
CALL
abc
ext
CALL
abc
ext
CALL
abc
ext
CALL
abc
ext
CALL
abc
ext
CALL
abc
2
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
5
JRR
b0,rr,ee
bt
JRS
b0,rr,ee
bt
JRR
b4,rr,ee
bt
JRS
b4,rr,ee
bt
JRR
b2,rr,ee
bt
JRS
b2,rr,ee
bt
JRR
b6,rr,ee
bt
JRS
b6,rr,ee
bt
JRR
b1,rr,ee
bt
JRS
b1,rr,ee
bt
JRR
b5,rr,ee
bt
JRS
b5,rr,ee
bt
JRR
b3,rr,ee
bt
JRS
b3,rr,ee
bt
JRR
b7,rr,ee
bt
JRS
b7,rr,ee
2
JRZ
2
JRC
4
LD
0
0
e
e
e
e
e
e
e
e
e
e
e
#
x
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
a,(x)
a,nn
0000
0000
1
2
pcr
JRNZ
2
4
1
2
3
5
1
2
pcr
JRZ
1
2
prc
JRC
1
4
ind
LDI
4
1
INC
sd
1
0001
1
0001
1
2
pcr
JRNZ
2
4
1
2
3
5
1
2
pcr
JRZ
1
2
prc
JRC
2
4
imm
CP
2
0010
2
0010
#
a,(x)
1
2
pcr
JRNZ
2
4
1
2
3
5
1
2
e
1
2
pcr
JRZ
1
2
prc
JRC
1
4
ind
CPI
4
1
LD
sd
3
0011
3
0011
a,x
#
a,nn
1
2
pcr
JRNZ
2
4
1
2
3
5
pcr
JRZ
1
2
prc
JRC
2
4
imm
ADD
a,(x)
4
0100
4
0100
e
e
e
e
e
e
1
2
pcr
JRNZ
2
4
1
2
3
5
1
2
pcr
JRZ
1
2
prc
JRC
1
4
ind
ADDI
4
1
INC
sd
5
0101
5
0101
y
a,nn
1
2
pcr
JRNZ
2
4
1
2
3
5
1
2
pcr
JRZ
1
2
prc
JRC
2
4
imm
INC
6
0110
6
0110
#
(x)
#
1
2
pcr
JRNZ
2
4
1
2
3
5
1
2
pcr
JRZ
1
2
prc
JRC
1
ind
4
1
LD
sd
7
0111
7
0111
a,y
#
1
2
pcr
JRNZ
e
pcr
RNZ
e
pcr
JRNZ
2
4
1
2
3
5
1
2
pcr
JRZ
1
2
prc
JRC
4
1
LD
ind
8
1000
8
1000
(x),a
#
1
2
2
4
1
2
3
5
1
2
pcr
JRZ
1
2
prc
JRC
4
1
INC
sd
9
1001
9
1001
v
1
2
2
4
1
2
3
5
1
2
pcr
JRZ
1
2
prc
JRC
4
AND
a,(x)
A
1010
A
1010
e
e
e
e
e
e
e
e
e
e
e
e
#
1
2
pcr
JRNZ
2
4
1
2
3
5
1
2
pcr
JRZ
1
2
prc
JRC
1
4
ind
ANDI
4
1
LD
sd
B
1011
B
1011
a,v
#
a,nn
1
2
pcr
JRNZ
2
4
1
2
3
5
1
2
pcr
JRZ
1
2
prc
JRC
2
4
imm
SUB
C
1100
C
1100
a,(x)
1
2
pcr
JRNZ
2
4
1
2
3
5
1
2
pcr
JRZ
1
2
prc
JRC
1
4
ind
SUBI
4
1
INC
sd
D
1101
D
1101
w
a,nn
1
2
pcr
JRNZ
2
4
1
2
3
5
1
2
pcr
JRZ
1
2
prc
JRC
2
4
imm
DEC
E
1110
E
1110
#
(x)
#
1
2
pcr
JRNZ
2
4
1
2
3
5
1
2
pcr
JRZ
1
2
prc
JRC
1
ind
4
1
LD
sd
F
1111
F
1111
a,w
1
pcr
2
ext
1
pcr
3
bt
1
pcr
1
prc
Abbreviations for Addressing Modes: Legend:
dir
sd
Direct
Short Direct
#
e
b
rr
nn
abc
ee
Indicates Illegal Instructions
5 Bit Displacement
3 Bit Address
1byte dataspace address
1 byte immediate data
12 bit address
Cycle
Mnemonic
2
1
JRC
prc
Operand
Bytes
imm Immediate
e
inh
ext
b.d
bt
Inherent
Extended
Bit Direct
Bit Test
Addressing Mode
8 bit Displacement
pcr
ind
Program Counter Relative
Indirect
66/78
66
ST62T80B/E80B
Opcode Map Summary (Continued)
LOW
LOW
8
1000
9
1001
A
1010
B
1011
C
1100
D
1101
E
1110
F
1111
HI
HI
2
JRNZ
4
JP
2
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
pcr
JRNC
e
4
RES
b0,rr
b.d
SET 2
b0,rr
b.d
RES
b4,rr
b.d
SET 2
b4,rr
b.d
RES
b2,rr
b.d
SET 2
b2,rr
b.d
RES
b6,rr
b.d
SET 2
b6,rr
b.d
RES
b1,rr
b.d
SET 2
b1,rr
b.d
RES
b5,rr
b.d
SET 2
b5,rr
b.d
RES
b3,rr
2
1
JRZ
4
LDI
2
JRC
4
LD
0
0
e
e
e
e
e
e
e
e
abc
abc
abc
abc
abc
abc
abc
abc
abc
abc
abc
abc
abc
abc
abc
abc
e
e
e
rr,nn
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
a,(y)
a,rr
0000
0000
1
2
pcr
JRNZ
2
4
ext
JP
1
2
2
4
pcr
JRZ
3
4
imm
DEC
1
2
prc
JRC
1
4
ind
LD
1
0001
1
0001
x
1
2
pcr
JRNZ
2
4
ext
JP
1
2
2
4
1
2
pcr
JRZ
1
4
sd
COM
1
2
prc
JRC
2
4
dir
CP
2
0010
2
0010
a
a,(y)
a,rr
1
2
pcr
JRNZ
2
4
ext
JP
1
2
2
4
1
pcr
JRZ
1
2
prc
JRC
1
4
ind
CP
4
LD
3
0011
3
0011
e
1
2
x,a
1
2
pcr
JRNZ
2
4
ext
JP
1
2
2
4
pcr
JRZ
1
2
sd
RETI
1
2
prc
JRC
2
4
dir
ADD
a,(y)
4
0100
4
0100
e
e
e
e
e
e
1
2
pcr
JRNZ
2
4
ext
JP
1
2
2
4
1
pcr
JRZ
1
4
inh
DEC
1
2
prc
JRC
1
4
ind
ADD
5
0101
5
0101
y
a,rr
(y)
rr
1
2
pcr
JRNZ
2
4
ext
JP
1
2
2
4
1
2
pcr
JRZ
1
2
sd
STOP 2
1
prc
JRC
2
4
dir
INC
6
0110
6
0110
1
2
pcr
JRNZ
2
4
ext
JP
1
2
2
4
1
pcr
JRZ
1
4
inh
LD
1
2
prc
JRC
1
4
ind
INC
7
0111
7
0111
y,a
#
1
2
pcr
JRNZ
e
pcr
RNZ
e
pcr
JRNZ
2
4
ext
JP
1
2
2
4
1
2
pcr
JRZ
1
sd
1
2
prc
JRC
2
4
dir
LD
8
1000
8
1000
(y),a
rr,a
1
2
2
4
ext
JP
1
2
2
4
1
pcr
JRZ
1
2
prc
JRC
1
4
ind
LD
4
DEC
9
1001
9
1001
v
1
2
2
4
ext
JP
1
2
2
4
1
2
pcr
JRZ
1
4
sd
RCL
1
2
prc
JRC
2
4
dir
AND
a,(y)
A
1010
A
1010
e
e
e
e
e
e
e
e
e
e
e
e
a
1
2
pcr
JRNZ
2
4
ext
JP
1
2
2
4
1
pcr
JRZ
1
4
inh
LD
1
2
prc
JRC
1
4
ind
AND
B
1011
B
1011
v,a
a,rr
1
2
pcr
JRNZ
2
4
ext
JP
1
2
2
4
1
2
pcr
JRZ
1
2
sd
RET
1
2
prc
JRC
2
4
dir
SUB
C
1100
C
1100
a,(y)
1
2
pcr
JRNZ
2
4
ext
JP
1
2
2
4
b.d
SET 2
b3,rr
b.d
RES
b7,rr
b.d
SET 2
b7,rr
1
pcr
JRZ
1
4
inh
DEC
1
2
prc
JRC
1
4
ind
SUB
D
1101
D
1101
w
a,rr
(y)
rr
1
2
pcr
JRNZ
2
4
ext
JP
1
2
2
4
1
2
pcr
JRZ
1
2
sd
WAIT
1
2
prc
JRC
2
4
dir
DEC
E
1110
E
1110
1
2
pcr
JRNZ
2
4
ext
JP
1
2
2
4
1
pcr
JRZ
1
4
inh
LD
1
2
prc
JRC
1
4
ind
DEC
F
1111
F
1111
w,a
1
pcr
2
ext
1
pcr
2
b.d
1
pcr
1
sd
1
prc
2
dir
Abbreviations for Addressing Modes: Legend:
dir
sd
Direct
Short Direct
#
e
b
rr
nn
abc
ee
Indicates Illegal Instructions
5 Bit Displacement
3 Bit Address
1byte dataspace address
1 byte immediate data
12 bit address
Cycle
Mnemonic
2
1
JRC
prc
Operand
Bytes
imm Immediate
e
inh
ext
b.d
bt
Inherent
Extended
Bit Direct
Bit Test
Addressing Mode
8 bit Displacement
pcr
ind
Program Counter Relative
Indirect
67/78
67
ST62T80B/E80B
6 ELECTRICAL CHARACTERISTICS
6.1 ABSOLUTE MAXIMUM RATINGS
This product contains devices to protect the inputs
against damage due to high static voltages, how-
ever it is advisable to take normal precaution to
avoid application of any voltage higher than the
specified maximum rated voltages.
Power Considerations.The average chip-junc-
tion temperature, Tj, in Celsius can be obtained
from:
Tj=
TA + PD x RthJA
Where:TA =
Ambient Temperature.
For proper operation it is recommended that V
I
RthJA = Pµackage thermal resistance
and V be higher than V and lower than V .
O
SS
DD
(junction-to ambient).
Reliability is enhanced if unused inputs are con-
PD =
Pint + Pport.
I x V (chip internal power).
DD
nected to an appropriate logic voltage level (V
DD
or V ).
Pint =
SS
DD
Pport = Port power dissipation (deter-
mined by the user).
Symbol
Parameter
Value
Unit
V
V
Supply Voltage
Input Voltage
Output Voltage
-0.3 to 7.0
DD
(1)
(1)
V
V
V
- 0.3 to V
+ 0.3
+ 0.3
V
I
SS
SS
DD
DD
V
- 0.3 to V
V
O
I
IV
IV
Current Drain per Pin Excluding V , V
±10
50
mA
mA
mA
°C
°C
O
DD SS
Total Current into V (source)
DD
SS
DD
Total Current out of V (sink)
50
SS
Tj
Junction Temperature
Storage Temperature
150
T
-60 to 150
STG
Notes:
-
Stresses above those listed as ”absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
- (1) Within these limits, clamping diodes are guarantee to be not conductive. Voltages outside these limits are authorised as long as injection
current is kept within the specification.
68/78
68
ST62T80B/E80B
6.2 RECOMMENDED OPERATING CONDITIONS
Value
Typ.
Symbol
Parameter
Test Conditions
Unit
Min.
Max.
6 Suffix Version
1 Suffix Version
-40
0
85
°C
70
TA
Operating Temperature
Operating Supply Voltage
f
= 2MHz
3.0
4.5
6.0
V
OSC
VDD
fosc= 8MHz
6.0
V
V
= 3V
= 4.5V
0
0
2.0
2)
DD
DD
f
Oscillator Frequency
MHz
8.0
OSC
IINJ+
IINJ-
Pin Injection Current (positive) VDD = 4.5 to 5.5V
Pin Injection Current (negative) VDD = 4.5 to 5.5V
+5
-5
mA
mA
Notes:
1. Care must be taken in case of negative current injection, where adapted impedance must be respected on analog sources to not affect the
A/D conversion. For a -1mA injection, a maximum 10 KΩ is recommanded.
2. An oscillator frequency above 1MHz is recommended for reliable A/D results.
Figure 34. Maximum Operating FREQUENCY (Fmax) Versus SUPPLY VOLTAGE (VDD)
Maximum FREQUENCY (MHz)
8
7
6
5
4
3
2
1
FUNCTIONALITYIS NOT
GUARANTEEDIN
THIS AREA
2.5
3
3.5
4
4.5
5
5.5
6
SUPPLY VOLTAGE (VDD)
The shaded area is outside the recommended operating range; device functionality is not guaranteed under these conditions.
69/78
69
ST62T80B/E80B
6.3 DC ELECTRICAL CHARACTERISTICS
(T = -40 to +85°C unless otherwise specified)
A
Value
Typ.
Symbol
Parameter
Test Conditions
Unit
V
Min.
Max.
x 0.3
V
Input Low Level Voltage
All Input pins
IL
V
DD
V
Input High Level Voltage
All Input pins
IH
V
x 0.7
V
DD
(1)
Hysteresis Voltage
All Input pins
V
V
= 5V
= 3V
0.2
0.2
DD
DD
V
V
Hys
Low Level Output Voltage
All Output pins
V
V
= 5.0V; I = +10µA
0.1
0.8
DD
DD
OL
= 5.0V; I = + 5mA
OL
V
V
V
V
V
= 5.0V; I = +10µA
0.1
0.8
1.3
OL
DD
DD
DD
OL
Low Level Output Voltage
20 mA Sink I/O pins
= 5.0V; I = +10mA
OL
= 5.0V; I = +20mA
OL
V
High Level Output Voltage
All Output pins
V
V
= 5.0V; I = -10µA
4.9
3.5
OH
DD
DD
OH
V
= 5.0V; I = -5.0mA
OH
All Input pins
RESET pin
40
100
350
200
900
R
Pull-up Resistance
ΚΩ
PU
150
Input Leakage Current
All Input pins but RESET
V
V
= V (No Pull-Up configured)
IN
IN
SS
0.1
-16
1.0
= V
I
I
DD
IL
µA
Input Leakage Current
RESET pin
V
V
= V
-8
-30
10
IH
IN
IN
SS
= V
DD
Supply Current in RESET
Mode
V
=V
RESET SS
7
7
mA
mA
mA
µA
f
=8MHz
OSC
Supply Current in
V
V
=5.0V
f
=8MHz
=8MHz
(2)
DD
INT
RUN Mode
I
DD
Supply Current in WAIT
=5.0V
f
2
(3)
DD
INT
Mode
Supply Current in STOP
I
V
=0mA
=5.0V
LOAD
10
(3)
Mode
DD
Notes:
(1) Hysteresis voltage between switching levels
(2) All peripherals running
(3) All peripherals in stand-by
70/78
70
ST62T80B/E80B
6.4 AC ELECTRICAL CHARACTERISTICS
(T = -40 to +85°C unless otherwise specified)
A
Value
Symbol
Parameter
Test Conditions
Unit
Min.
Typ.
Max.
(1)
t
Supply Recovery Time
100
ms
REC
Minimum Pulse Width (V = 5V)
DD
T
RESET pin
NMI pin
100
100
ns
WR
TA = 25°C
TA = 85°C
5
10
10
20
T
EEPROM Write Time
ms
WEE
Endurance EEPROM WRITE/ERASE Cycle
Retention EEPROM Data Retention
300,000 1 million
10
cycles
years
pF
TA = 55°C
C
Input Capacitance
Output Capacitance
All Inputs Pins
All Outputs Pins
10
10
IN
C
pF
OUT
Notes:
1. Period for which V has to be connected at 0V to allow internal Reset function at next power-up.
DD
6.5 A/D CONVERTER CHARACTERISTICS
(T = -40 to +85°C unless otherwise specified)
A
Value
Typ.
8
Symbol
Parameter
Test Conditions
Unit
Min.
Max.
Res
Resolution
Total Accuracy
Bit
LSB
µs
f
f
> 1.2MHz
> 32kHz
±2
±4
(1) (2)
OSC
OSC
A
TOT
t
Conversion Time
f
= 8MHz
70
C
OSC
Conversion result when
= V
ZIR
Zero Input Reading
00
Hex
V
IN
SS
Conversion result when
FSR
Full Scale Reading
FF
Hex
V
= V
IN
DD
Analog Input Current During
Conversion
AD
V
= 4.5V
1.0
5
µA
I
DD
AC
Analog Input Capacitance
2
pF
IN
Notes:
1. Noise at AV , AV <10mV
DD
SS
2. With oscillator frequencies less than 1MHz, the A/D Converter accuracy is decreased. .
71/78
71
ST62T80B/E80B
6.6 TIMER CHARACTERISTICS
(T = -40 to +85°C unless otherwise specified)
A
Value
Typ.
Symbol
Parameter
Test Conditions
Unit
Min.
Max.
fINT
8
f
Input Frequency on TIMER Pin*
Pulse Width at TIMER Pin*
MHz
---------
IN
V
V
= 3.0V
>4.5V
1
125
µs
ns
DD
DD
t
W
Note*: When available.
6.7 SPI CHARACTERISTICS
(T = -40 to +85°C unless otherwise specified)
A
Value
Symbol
Parameter
Test Conditions
Unit
Min.
Typ.
Max.
F
Clock Frequency
Set-up Time
Hold Time
Applied on Scl
Applied on Sin
Applied onSin
1
MHz
ns
CL
t
50
SU
t
100
ns
h
6.8 LCD ELECTRICAL CHARACTERISTICS
(T = -40 to +85°C unless otherwise specified)
A
Value
Typ.
Symbol
Parameter
Test Conditions
Unit
Min.
Max.
V
DC Offset Voltage
V
= Vdd, no load
LCD
50
mV
os
COM High Level, Output Voltage
SEG High Level, Output Voltage
I=100µA, V
=5V
=5V
=5V
LCD
V
4.5
OH
I=50µA, V
LCD
COM Low Level, Output Voltage
SEG Low Level, Output Voltage
I=100µA, V
V
LCD
V
0.5
10
OL
I=50µA, V
=5V
LCD
V
Display Voltage
See Note 2
V
-0.2
LCD
DD
Notes:
1. The DC offset refers to all segment and common outputs. It is the difference between the measured voltage value and nominal value for
every voltage level.
2. An external resistor network is required when VLCD is lower then 4.5V.
72/78
72
ST62T80B/E80B
7 GENERAL INFORMATION
7.1 PACKAGE MECHANICAL DATA
Figure 35. 100-Pin Plastic Quad Flat Package Short Footprint
mm
inches
Dim
Min Typ Max Min Typ Max
3.40 0.134
A
A1 0.25
0.010
A2 2.55 2.80 3.05 0.100 0.110 0.120
B
C
D
0.22
0.13
0.38 0.009
0.23 0.005
0.015
0.009
22.95 23.20 23.45 0.904 0.913 0.923
D1 19.90 20.00 20.10 0.783 0.787 0.791
D3
E
18.85
0.742
16.95 17.20 17.45 0.667 0.677 0.687
E1 13.90 14.00 14.10 0.547 0.551 0.555
E3
e
12.35
0.65
0.486
0.026
K
0°
7°
L
0.65 0.80 0.95 0.026 0.031 0.037
L1
1.60
0.063
Number of Pins
PQFP100
N
100
ND
30
NE
20
Figure 36. 100-Pin Ceramic Quad Flat Package Long Footprint
mm
inches
Dim
Min Typ Max Min Typ Max
3.24 0.128
A
A1
B
0.20
0.008
0.22 0.35 0.38 0.009 0.014 0.015
0.13 0.15 0.23 0.005 0.006 0.009
23.35 23.90 24.45 0.919 0.941 0.963
C
D
D1 19.57 20.00 20.43 0.770 0.787 0.804
D3
E
18.85
0.742
17.35 17.90 18.45 0.683 0.705 0.726
E1 13.61 14.00 14.39 0.536 0.551 0.567
E3
e
12.35
0.65
0.486
0.026
G
13.75 14.00 14.25 0.541 0.551 0.561
G1 19.75 20.00 20.25 0.778 0.787 0.797
G2
L
1.17
0.35 0.80
8.89
0.046
0.014 0.031
CQFP100W
Ø
Number of Pins
100
N
73/78
73
ST62T80B/E80B
GENERAL INFORMATION (Cont’d)
7.2 PACKAGE THERMAL CHARACTERISTIC
Value
Typ.
Symbol
Parameter
Test Conditions
Unit
Min.
Max.
70
PQFP100
RthJA
Thermal Resistance
°C/W
CQFP100W
70
7.3 .ORDERING INFORMATION
Table 30. OTP/EPROM VERSION ORDERING INFORMATION
Program
Sales Type
I/O
Temperature Range
Package
Memory (Bytes)
7948 (EPROM)
7948 (OTP)
ST62E80BG1
0 to 70°C
CQFP100W
PQFP100
22
ST62T80BQ6
-40 to 85°C
74/78
74
ST6280B
8-BIT OTP/EPROM MCU WITH LCD DRIVER,
EEPROM AND A/D CONVERTER
■ 3.0 to 6.0V Supply Operating Range
■ 8 MHz Maximum Clock Frequency
■ -40 to +85°C Operating Temperature Range
■ Run, Wait and Stop Modes
■ 5 Interrupt Vectors
■ Look-up Table capability in Program Memory
■ Data Storage in Program Memory:
User selectable size
■ Data RAM: 192 bytes
■ Data EEPROM: 128 bytes
■ 22 I/O pins, fully programmable as:
– Input with pull-up resistor
– Input without pull-up resistor
– Input with interrupt generation
– Open-drain or push-pull output
– Analog Input
PQFP100
– LCD segments (8 combiport lines)
(See end of Datasheet for Ordering Information)
■ 4 I/O lines can sink up to 20mA to drive LEDs or
TRIACs directly
■ Two
8-bit
Timer/Counter
with
7-bit
programmable prescaler
■ Digital Watchdog
■ 8-bit A/D Converter with 12 analog inputs
■ 8-bit Synchronous Peripheral Interface (SPI)
■ 8-bit AsynchronousPeripheral Interface (UART)
■ LCD driver with 45 segment outputs, 4
backplane outputs and selectable multiplexing
ratio.
■ 32kHz oscillator for stand-by LCD operation
■ Power Supply Supervisor (PSS)
■ On-chip Clockoscillator canbe driven by Quartz
Crystal or Ceramic resonator
■ One external Non-Maskable Interrupt
■ ST6240-EMU2 Emulation and Development
System (connects to an MS-DOS PC via a
parallel port).
DEVICE SUMMARY
ROM
DEVICE
I/O Pins
(Bytes)
ST62T80B
7948
22
Rev. 2.5
August 1999
75/78
75
ST6280B
1 GENERAL DESCRIPTION
1.1 INTRODUCTION
1.2 ROM READOUT PROTECTION
The ST6280B is mask programmed ROM version
of ST62T80B OTP devices.
If the ROM READOUT PROTECTION option is
selected, a protection fuse can be blown to pre-
vent any access to the program memory content.
They offer the same functionality as OTP devices,
selecting as ROM options the options defined in
the programmable option byte of the OTP version.
In case the user wants to blow this fuse, high volt-
age must be applied on the TEST pin.
Figure 2. Programming Circuit
Figure 1. Programming wave form
0.5s min
TEST
5V
47mF
15
14V typ
10
100nF
5
V
SS
V
DD
TEST
150 µs typ
PROTECT
14V
TEST
100mA
max
100nF
ZPD15
15V
VR02003
4mA typ
t
VR02001
Note: ZPD15 is used for overvoltage protection
76/78
76
ST6280B
ST6280B MICROCONTROLLER OPTION LIST
Customer
Address
Contact
Phone No
Reference
STMicroelectronics references
Device:
[ ] ST6280B
Package:
[ ] Plastic Quad Flat Package (Tape & Reel)
Temperature Range:
Special Marking:
[ ] 0°C to + 70°C[ ] - 40°C to + 85°C
[ ] No
[ ] Yes ”_ _ _ _ _ _ _ _ _ _ _ ”
Authorized characters are letters, digits, ’.’, ’-’, ’/’ and spaces only.
Maximum character count: PQFP100: 10
Watchdog Selection:
[ ] Software Activation
[ ] Hardware Activation
NMI Pull-Up Selection: [ ] Yes [ ] No
ROM Readout Protection:[ ] Standard (Fuse cannot be blown)
[ ] Enabled (Fuse can be blown by the customer)
Note: No part is delivered with protected ROM.
The fuse must be blown for protection to be effective.
Comments :
Number of segments and backplanes used:
Supply Operating Range in the application:
Oscillator Fequency in the application:
Notes
. . . . . . . . . . . . . . . . . .
Signature
Date
77/78
77
ST6280B
1.3 ORDERING INFORMATION
The following section deals with the procedure for
transfer of customer codes to STMicroelectronics.
part of the contractual agreement for the creation
of the specific customer mask.
1.3.1 Transfer of Customer Code
The STMicroelectronics Sales Organization will be
pleased to provide detailed information on con-
tractual points.
Customer code is made up of the ROM contents
and the list of the selected mask options. The
ROM contents are to be sent on diskette, or by
electronic means, with the hexadecimal file gener-
ated by the development tool. All unused bytes
must be set to FFh.
Table 1. ROM Memory Map for ST6280B
ROM Page Device Address
Description
The selected mask options are communicated to
STMicroelectronics using the correctly filled OP-
TION LIST appended.
0000h-007Fh
Page 0
Reserved
User ROM
0080h-07FFh
0800h-0F9Fh
0FA0h-0FEFh
User ROM
Reserved
1.3.2 Listing Generation and Verification
Page 1
“STATIC”
0FF0h-0FF7h
0FF8h-0FFBh
0FFCh-0FFDh
0FFEh-0FFFh
Interrupt Vectors
Reserved
NMI Vector
Reset Vector
When STMicroelectronics receives the user’s
ROM contents, a computer listing is generated
from it. This listing refers exactly to the mask which
will be used to produce the specified MCU. The
listing is then returned to the customer who must
thoroughly check, complete, sign and return it to
STMicroelectronics. The signed listing forms a
0000h-000Fh
0010h-07FFh
Reserved
User ROM
Page 2
Page 3
0000h-000Fh
0010h-07FFh
Reserved
User ROM
Table 2. ROM version Ordering Information
Sales Type
ROM
I/O
Temperature Range
Package
ST6280BQ1/XXX
ST6280BQ6/XXX
0 to +70°C
-40 to 85°C
7948
22
PQFP100
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of useof such information nor for any infringement of patents or other rights of third parties which may result from its use. No license isgranted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
1999 STMicroelectronics - All Rights Reserved.
Purchase of I2C Components by STMicroelectronics conveys a license under the Philips I2C Patent. Rights to use these components in an
I2C system is granted provided that the system conforms to the I2C Standard Specification as defined by Philips.
STMicroelectronics Group of Companies
Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain
Sweden - Switzerland - United Kingdom - U.S.A.
http://www.st.com
78/78
78
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8-BIT MCUs WITH A/D CONVERTER, TWO TIMERS, OSCILLATOR SAFEGUARD & SAFE RESET
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ST62T08BM1/OTP
8-BIT MCUs WITH A/D CONVERTER, TWO TIMERS, OSCILLATOR SAFEGUARD & SAFE RESET
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8-BIT MCUs WITH A/D CONVERTER, TWO TIMERS, OSCILLATOR SAFEGUARD & SAFE RESET
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8-BIT MCUs WITH A/D CONVERTER, TWO TIMERS, OSCILLATOR SAFEGUARD & SAFE RESET
STMICROELECTR
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8-BIT MCUs WITH A/D CONVERTER, TWO TIMERS, OSCILLATOR SAFEGUARD & SAFE RESET
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