ST6373J5B1 [STMICROELECTRONICS]
8-BIT ROM/OTP/EPROM MCUs FOR DIGITALLY CONTROLLED MULTISYNC/MULTISTANDARD MONITORS; 8位ROM / OTP / EPROM微控制器用于数字控制多频/多标准监听音箱
| 型号： | ST6373J5B1 |
| 厂家： | 
ST |
| 描述： | 8-BIT ROM/OTP/EPROM MCUs FOR DIGITALLY CONTROLLED MULTISYNC/MULTISTANDARD MONITORS |
| 文件： | 总64页 (文件大小：457K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
R
ST6373
8-BIT ROM/OTP/EPROM MCUs FOR DIGITALLY
CONTROLLED MULTISYNC/MULTISTANDARD MONITORS
■ 4.5V to 6V Operating Supply Voltage Range
■ Low Current Consumption
■
0 to +70°C Operating Temperature Range
■
8 MHz clock Oscillator
■ 16K bytes ROM/OTP/EPROM
(8K and 12K ROM versions also available)
■
192 bytes RAM
■ 384 bytes general purpose EEPROM
■ 128 bytes dedicated EEPROM for DDC SPI
■ 22 fully programmable I/O pins, offering direct
LED drive capability, as well as interrupt
generation for keyboard inputs
■ Digital WATCHDOG timer
PSDIP42
■ Three Timers, each comprising an 8-bit counter
and a 7- bit Prescaler
■ SYNC Processor:
– 12-bits HSYNC Event Counter
– 12-bits VSYNC Period Counter
– HSYNC and VSYNC Polarity Detection
– HSYNC and VSYNC Outputs
– HFLYBACK and VFLYBACK Inputs
– CLAMP and BLANK Outputs
■ 14-bit (PWM + BRM) D/A Converter
■ Nine 7-bit PWM D/A Converter Outputs
CSDIP42
■
8-bit A/D Converter with 8 multiplexed inputs
■ DDC SPI with interrupt and 4 operating modes
(Refer to end of Document for Ordering Information)
■ A further SPI with interrupt and 2 operating
modes
■
Remote Control Signal Input (Non Maskable
Interrupt)
■ VSYNC Interrupt Input
■ Five Interrupt Vectors
■
XOR Register (Instruction Set expansion)
■ MIRROR Register (Instruction Set expansion)
February 1998
1/64
1
Thisisadvance informationfromSGS-THOMSON.Detailsaresubjecttochange withoutnotice.
Table of Contents
ST6373 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
1.3 MEMORY SPACES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
1.3.1 Stack Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
1.3.2 Program Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
1.3.3 Data Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
1.3.4 Data RAM/EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.3.5 EEPROM Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
1.4 MEMORY PROGRAMMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
1.4.1 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
1.4.2 Option Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
1.4.3 Eprom Erasure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
2 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
2.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
2.2 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . 18
3.1 ON-CHIP CLOCK OSCILLATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.2 RESETS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
3.2.1 RESET Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
3.2.2 Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
3.2.3 Watchdog Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
3.2.4 Application Note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
3.2.5 MCU Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.3 HARDWARE ACTIVATED DIGITAL WATCHDOG FUNCTION . . . . . . . . . . . . . . . . . . . . 21
3.4 INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
3.4.1 Interrupt Vectors/Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.4.2 Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
3.4.3 Interrupt Option Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.4.4 Interrupt Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
3.4.5 ST6373 Interrupt Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.5 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
3.5.1 WAIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
3.5.2 STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
3.5.3 Exit from WAIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
4 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
4.1 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
4.1.1 Details of I/O Ports A and B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.1.2 Details of I/O Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
4.1.3 I/O Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
4.2 TIMERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
4.2.1 Timer Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
64
4.2.2 Timer Status Control Registers (TSCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.2.3 Timer Counter Registers (TCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
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Table of Contents
4.2.4 Timer Prescaler Registers (PSC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.3 A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
4.3.1 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
4.4 SYNC PROCESSOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
4.4.1 Event Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
4.4.2 Period Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
4.4.3 Polarity Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
4.4.4 Output Polarity Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.4.5 Video Blanking Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.5 14-BIT PWM D/A CONVERTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.5.1 Output Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
4.5.2 HDA Tuning Cell Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.6 7-BIT PWM D/A CONVERTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.6.1 Digital Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
4.7 SERIAL PERIPHERAL INTERFACES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.7.1 SPI Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
4.8 MIRROR REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
4.9 XOR REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
5 SOFTWARE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
5.1 ST6 ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
5.2 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
5.3 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
6 ELECTRICAL CHARACTERISTICS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6.1 ABSOLUTE MAXIMUM RATINGS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6.2 RECOMMENDED OPERATING CONDITIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6.3 DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6.4 AC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
7 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
7.1 PACKAGE MECHANICAL DATA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
7.2 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
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1
ST6373
1 GENERAL DESCRIPTION
1.1 INTRODUCTION
ST6373 Microcontrollers are members of the 8-bit
HCMOS ST637x family, a series of devices spe-
cially intended for Digitally Controlled Multi Fre-
quency Monitor applications. All ST637x devices
are based on a building block approach: a com-
mon core is surrounded by a combination of on-
chip peripherals (macrocells) available from a
standard library.
– A Period Counter especially designed to calcu-
late the VSYNC Period.
– A Polarity Detector for HSYNC (or HDRIV) and
VSYNC.
– HSYNC and VSYNC outputs with controlled po-
larity.
– Video Blanking and Clamping Outputs.
ST6373 devices are available in functionally iden-
tical ROM, OTP (ST63T73) and EPROM
(ST63E73) versions, all with the same pinout.
ROM devices are available with 8, 12 or 16K Pro-
gram memory, whereas OTP and EPROM ver-
sions are both available in 16K versions only. For
details relating to sales types, refer to Section 7.2.
– Two I/O ports A & B usable for a keyboard wake-
up feature since an interrupt input ored on each
of their pins.
– An Analog to Digital converter connected to port
B which can be used to decode an analog key-
board or for AFC.
Since ROM, OTP and EPROM versions are
functionally identical, the present Datasheet
will refer to the generic ST6373 device, except
where specific versions differ in detail.
– A VSYNC input pin connected to an interrupt
vector and to the DDC SPI for DDC1 protocol.
– An NMI input which can be used, for example, as
a Remote Control input for a TV application.
The ST6373 devices feature:
– A hardware DDC SPI able to manage DDC1
– Nine PWM outputs, which can be used as Digital
to Analog converter outputs (with external RC fil-
ters). These are suitable for tuning and other
functions.
2
(VSYNC as clock), DDC2B and DDC2AB (I C
BUS Multimaster and Slave). A 128-byte
dedicated EEPROM memory is available for
DDC1 and DDC2B.
– A PWM output with Bit Rate Multiplier, to which
the above comments apply.
2
– Hardware I C SPI for internal monitor bus and to
manage, for example, an OSD.
– An Event Counter especially designed to calcu-
late the HSYNC (or HDRIV) Frequency, using
one of the on-chip timers.
– A Mirror Register and a XOR Register are includ-
ed to complement the basic ST6 instruction set.
Table 1. ST6373 Device Summary
Program
14-bit
D/ (PWM) D/A (PWM)
Output
7-bit
DEVICE
RAM
EEPROM
(Bytes)
A/D
Inputs
EMULATING
DEVICES
Memory
(Bytes)
CONFIGURATION
(Bytes)
Output
8K ROM
12K ROM
16K ROM
ST6373
192
512
8
1
9
ST63E73,ST63T73
ST63T73
ST63E73
16K OTP
192
192
512
512
8
8
1
1
9
9
-
-
16K EPROM
Note: See
Ordering Information in Table 23 at the end of the Datasheet.
4/64
ST6373
Figure 1. ST6373 Block Diagram
PA0 -> PA7*
PORT A
PORT B
PORT C
TIMER 1
TIMER 2
(
)
TEST/V
**
TEST
PP
PB0 -> PB7*
PC0 -> PC7*
INTERRUPT
Inputs
DIGITAL
WATCHDOG/TIMER
NMI
VSYNC
PWRIN
DATA ROM
USER
SELECTABLE
SCLD, SDAD
VSYNC, EXTCLK
DDC SPI (1)
USER PROGRAM
MEMORY
DATA RAM
192 Bytes
16 KBytes
EEPROM
128 Bytes (1)
DATA EEPROM
384 Bytes
TIMER 3
HSYNCO, VSYNCO
HSYNCI, VSYNCI
HDRIV
SYNC
PROCESSOR
PC
HFLY, VFLY
CLMPO, BLKO
STACK LEVEL 1
STACK LEVEL 2
STACK LEVEL 3
STACK LEVEL 4
STACK LEVEL 5
STACK LEVEL 6
I C SPI
SCLI, SDAI
8 BIT CORE
D/A Outputs
A/D Inputs
HDA, DA0 -> DA8
AD0 -> AD7
POWER
RESET
RESET
OSCILLATOR
SUPPLY
V
V
OSCin OSCout
DD SS
(*)Refer to Pin Description for Additional Information
) V input for OTP/EPROM device programming
(
**
PP
5/64
ST6373
1.2 PIN DESCRIPTION
V
and V
SS.
Power is supplied to the MCU using
to PC7 are configured as open-drain 12V; the in-
put pull-up option does not exist for these four
pins. Pins PC0, PC1 and PC3 can be configured
as the DDC SPI pins SCLD, SDAD and EXTCLK.
The input pull-up option does not exist for PC0
and PC1. Pins PC6 and PC7 can be configured
as HSYNC and HDRIV inputs. After reset: PC3 is
configured as input with pull-up. PC0, PC1 &
PC4 to PC7 are configured in input without pull-
up. PC2 is in output mode with the value 1 (high
impedance).
DD
these two pins. V
is power and V
is the
DD
SS
ground connection.
OSCin, OSCout.
These pins are internally con-
nected to the on-chip oscillator circuit. A quartz
crystal or a ceramic resonator can be connected
between these two pins in order to allow the cor-
rect operation of the MCU with various stabili-
ty/cost trade-offs. The OSCin pin is the input pin,
the OSCout pin is the output pin.
RESET. The active lowRESET pin is used to start
the microcontroller to the beginning of its program.
Additionally the quartz crystal oscillator will be dis-
abled when theRESET pin is low to reduce power
consumption during reset phase.
DA0-DA8. These pins are the nine PWM D/A out-
puts of the on-chip D/A converters. These lines
have push-pull outputs with 5V drive. The output
repetition rate is 31.25KHz (with 8MHz clock).
TEST
mal operation.
. The TEST pin must be held at VSS for nor-
VSYNC. This is the Vertical Synchronization pin.
This pin is connected to an internal interrupt and is
configured as input with pull-up and Schmitt trig-
ger.
PA0, PA1, PA2/HSYNCO, PA3/VSYNCO,
PA4/CLMPO, PA5/BLKO, PA6/SCLI, PA7/SDAI
HDA. This is the output pin of the on-chip 14-bit
PWM D/A Converter. This line is a push-pull out-
put with standard drive.
Port A.
–
Software configurable as push-pull out-
put, open-drain output, Schmitt trigger input with
or without pull-up. Port A inputs can be also
ORed into the INT1 interrupt. Port A outputs
have a LED drive capability (10 mA). Pins PA2
and PA3 can be configured respectively as
HSYNC and VSYNC outputs.Pins PA4 and PA5
can be configured respectively as CLAMP and
BLANK Outputs.Pins PA6 and PA7 can be con-
NMI
. This pin is the Non-Maskable interrupt input
and is configured as input with pull-up and Schmitt
trigger.
Figure 2. ST6373 Pin configuration
2
figurated as the I C SPI pins SCLI and SDAI.The
VDD
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
O0/DA0
O1/DA1
O2/DA2
1
2
3
4
5
6
7
8
push-pull output and the input pull-up options do
not exist for these two pins. After reset the PA0
to PA5 pins are configured as inputs with pull-up.
PC0/SCLD
PC1/SDAD
PC2
PC3/EXTCLK
PC4/PWRIN
PC5
PC6/HSYNC
PC7/HDRIV
HDA
O3/DA3
PB0/AD0, PB1/AD1, PB2/AD2, PB3/AD3,
PB4/AD4, PB5/AD5/HFLY, PB6/AD6/VFLY,
PB7/AD7
AD0/PB0
AD1/PB1
AD2/PB2
AD3/PB3
AD4/PB4
HFLY/AD5/PB5
VFLY/AD6/PB6
AD7/PB7
PA0
Port B
. Each pin can be software configured as
–
push-pull output, open-drain output, Schmitt trig-
ger input with or without pull-up.Port B inputs can
be also ored into the INT1 interrupt. Pins PB5
and PB6 can be configured as HFLY and VFLY
inputs. In addition, any pin of port B can be soft-
ware selected as the Analog-to-Digital converter
input. Only one pin should be selected at a time,
otherwise a conflict would result. After reset the
port B pins are configured as inputs with pull-up.
9
10
11
12
13
14
15
16
17
18
19
20
21
RESET
OSCout
OSCin
(1)
TEST/VPP
PA1
VSYNC
NMI
HSYNCO/PA2
VSYNCO/PA3
CLMPO/PA4
BLKO/PA5
SCLI/PA6
SDAI/PA7
VSS
DA4/O4
DAR/O5
DA6/O6
DA7/O7
DA8/O8
PC0/SCLD, PC1/SDAD, PC2, PC3/EXTCLK,
PC4/PWRIN, PC5, PC6/HSYNC, PC7/HDRIV
– Port C. Software configurable as open-drain out-
puts or Schmitt trigger inputs with or without pull-
ups. When configured as outputs, pins PC0 to
PC3 are configured as 5V open-drain. Pins PC4
(1) This pin is also the VPP input for OTP/EPROM devices
6/64
ST6373
Table 2. Pin Summary
Pin Function
DA0 to DA8
HDA
Description
Output, Push-Pull
Output, Push-Pull
NMI
Input, Pull-up, Schmitt Trigger Input
Input, Pull-up, Schmitt Trigger
Input, Pull-Down
VSYNC
TEST
OSCin
Input, Resistive Bias, Schmitt Trigger to Reset Logic Only
Output, Push-Pull
OSCout
RESET
Input, Pull-up, Schmitt Trigger Input
PA0-PA5
PA6-PA7
PB0-PB7
PC0-PC1
PC2-PC3
PC4-PC7
I/O, Push-Pull/Open Drain, Software Input Pull-up, Schmitt Trigger Input
I/O, Open-Drain, No Input Pull-up, Schmitt Trigger Input
I/O, Push-Pull/Open Drain, Software Input Pull-up, Schmitt Trigger Input, Analog Input
I/O, Open-Drain, No Input Pull-up, Schmitt Trigger Input
I/O, Open-Drain, 5V, Software Input Pull-up, Schmitt Trigger Input
I/O, Open-Drain, 12V, No Input Pull-up, Schmitt Trigger Input
Power Supply Pins
V
, V
SS
DD
7/64
ST6373
1.3 MEMORY SPACES
The MCU operates in three different memory
spaces: Stack Space, Program Space and Data
Space.
lower 2K byte of the 4K program space are bank
switched while the upper 2K byte can be seen as
static space. Table 3 gives the different codes that
allows the selection of the corresponding banks.
Note that, from the memory point of view, the Page
1 and the Static Page represent the same physical
memory: it is only a different way of addressing the
same location.
1.3.1 Stack Space
The stack space consists of six 12 bit registers that
are used for stacking subroutine and interrupt re-
turn addresses plus the current program counter
register.
Figure 3. 16K-Byte Program Space Addressing
1.3.2 Program Space
Program
counter
space
The program space is physically implemented in
the ROM and includes all the instructions that are
to be executed, as well as the data required for the
immediate addressing mode instructions, the re-
served test area and user vectors. It is addressed
thanks to the 12-bit Program Counter register (PC
register) and the ST6 Core can directly address up
to 4K bytes of Program Space. Nevertheless, the
Program Space can be extended by the addition
of 2-Kbyte memory banks as it is shown inFigure
2, in which the 16K bytes memory is described.
These banks are addressed by pointing to the
000h-7FFh locations of the Program Space thanks
to the Program Counter, and by writing the appro-
priate code in the Program ROM Page Register
(PRPR) located at address CAh in the Data
Space. Because interrupts and common subrour-
outines should be available all the time only the
1FFFh
0000h
0FFFh
Static
Page
Page 1
0800h
07FFh
Page1
Page Page Page Page Page Page
Page 0
Static
Page
2
3
4
5
6
7
0000h
Figure 4. Memory Addressing Diagram
PROGRAM SPACE
DATA SPACE
0000h
000h
PROGRAM COUNTER
RAM / EEPROM
BANKING AREA
0-63
STACK LEVEL 1
STACK LEVEL 2
03Fh
040h
DATA ROM
WINDOW
STACK LEVEL 3
ROM
07Fh
080h
081h
082h
083h
084h
STACK LEVEL 4
STACK LEVEL 5
STACK LEVEL 6
X REGISTER
Y REGISTER
V REGISTER
W REGISTER
RAM
0C0h
DATA ROM
WINDOW SELECT
0FF0h
DATA RAM
INTERRUPT &
RESET VECTORS
0FFFh
BANK SELECT
0FFh
ACCUMULATOR
8/64
ST6373
MEMORY SPACES (Cont’d)
Program ROM Page Register (PRPR)
Address: CAh - Write only
Reset Value: XXh
Care is required when handling the PRPR as it is
write only. For this reason, it is not allowed to
change the PRPR contents while executing inter-
rupts drivers, asthe driver cannot save and than re-
store its previous content. Anyway, this operation
may be necessary if the sum of common routines
and interrupt drivers will take more than 2K bytes;
in this case could be necessary to divide the inter-
rupt driver in a (minor) part in the static page (start
and end), and in the second (major) part in one dy-
namic page. If it is impossible to avoid the writing of
this register in interrupts drivers, an image of this
register must be saved ina RAM location, and each
time the program writes the PRPR bit writes also
the image register. The image register must be
written first, so if an interrupt occurs between the
two instructions the PRPR is not affected.
7
0
-
-
-
-
-
PRPR2 PRPR1 PRPR0
D7-D3. These bits are not used but have to be
written to “0”.
PRPR2-PRPR0.
These are the program ROM
banking bits and the value loaded selects the cor-
responding page to be addressed in the lower part
of 4K program address space as specified inTable
3.This register is undefined on reset.
Note:
Table 3. Program MemoryPageRegisterCoding
Only the lower part of address space has been
bankswitched because interrupt vectors and com-
mon subroutines should be available all the time.
The reason of this structure is due to the fact that it
is not possible to jump from a dynamic page to an-
other, unless jumping back to the static page,
changing contents of PRPR, and, then, jumping to
a different dynamic page.
PRPR2 PRPR1 PRPR0 PC11
Memory Page
Static Page (Page 1)
Page 0
X
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
1
0
0
0
0
0
0
0
0
Page 1 (Static Page)
Page 2
Page 3
Page 4
Page 5
Page 6
Page 7
Table 4. ST6373 Program Memory Map
*)
Program Memory Page
Device Address
Description
0000h-007Fh
0080h-07FFh
Reserved
User ROM
PAGE 0
0800h-0F9Fh
0FA0h-0FEFh
0FF0h-0FF7h
0FF8h-0FFBh
0FFCh-0FFDh
0FFEh-0FFFh
User ROM
Reserved
Interrupt Vectors
Reserved
NMI Vector
Reset Vector
PAGE 1
“STATIC”
0000h-000Fh
0010h-07FFh
Reserved
User ROM
PAGE 2
PAGE 3
PAGE 4
PAGE 5
PAGE 6
PAGE 7
0000h-000Fh
0010h-07FFh
Reserved
User ROM (End of 8K)
0000h-000Fh
0010h-07FFh
Reserved
User ROM
0000h-000Fh
0010h-07FFh
Reserved
User ROM (End of 12K)
0000h-000Fh
0010h-07FFh
Reserved
User ROM
0000h-000Fh
0010h-07FFh
Reserved
User ROM (End of 16K)
*)
Note : all reserved areas must be set to FFh in the ROM code.
9/64
ST6373
MEMORY SPACES (Cont’d)
1.3.3 Data Space
The Data Space allows the addressing of RAM
(192 bytes), EEPROM (384 bytes plus 128 bytes
for the DDC SPI), ST6 Core and peripheral regis-
ters, as well as read-only data such as constants
and look-up tables.
The ST6 Core instruction set operates on a specif-
ic space, referred to as the Data Space, which
contains all the data necessary for the program.
Figure 5. Data Space
MIRROR REGISTER
TIMER 3 PRESCALER REGISTER
TIMER 3 COUNTER REGISTER
TIMER 3 STATUS/CONTROL REGISTER
EVENT COUNTER DATA REGISTER 1
EVENT COUNTER DATA REGISTER 2
SYNC PROCESSOR CONTROL REGISTER
D/A 0/4 DATA CONTROL REGISTER
D/A 1/5 DATA CONTROL REGISTER
D/A 2/6 DATA CONTROL REGISTER
D/A 3/7 DATA CONTROL REGISTER
D/A 8 DATA CONTROL REGISTER
I C SPI CONTROL REGISTER1
I C SPI CONTROL REGISTER2
D/A BANK REGISTER
0D9h
0DAh
0DBh
0DCh
0DDh
000h
DATA RAM/EEPROM
BANK AREA
03Fh
040h
DATA ROM
*)
WINDOW AREA
07Fh
0DEh
*)
0DFh
X REGISTER
Y REGISTER
V REGISTER
W REGISTER
080h
081h
082h
083h
084h
0BFh
0C0h
0C1h
0C2h
0C3h
0C4h
0C5h
0C6h
0C7h
0C8h
0C9h
*)
*)
*)
*)
*)
*)
*)
0E0h
0E1h
0E2h
0E3h
0E4h
0E5h
0E6h
DATA RAM
PORT A DATA REGISTER
PORT B DATA REGISTER
PORT C DATA REGISTER
RESERVED
0E7h
0E8h
0E9h
0EAh
0EBh
0ECh
0EDh
DATA RAM BANK REGISTER
DDC EEPROM CONTROL REGISTER
EEPROM CONTROL REGISTER
DDC SPI CONTROL REGISTER 1
DDC SPI CONTROL REGISTER 2
NMI/PWRIN/VSYNC INTERRUPT REGISTER
HDA DATA REGISTER 1
PORT A DIRECTION REGISTER
PORT B DIRECTION REGISTER
PORT C DIRECTION REGISTER
RESERVED
INTERRUPT OPTIONREGISTER
DATA ROM WINDOW REGISTER
PROGRAM ROM PAGE REGISTER
I C SPI DATA REGISTER
*)
0EEh
0EFh
*)
HDA DATA REGISTER 2
*)
0CAh
0CBh
0CCh
0CDh
0CEh
0CFh
0D0h
PERIOD COUNTER DATA REGISTER
PERIOD COUNTER 1 AND BLANK CTRL REG.
AUTO-COUNTER REGISTER
0F0h
*)
0F1h
0F2h
DDC SPI DATA REGISTER
PORT A OPTION REGISTER
PORT B OPTION REGISTER
RESERVED
*)
SCL LATCHAND DDC2B ADDRESSCTRL REG.
XOR REGISTER
0F3h
0F4h
0F5h
ADC RESULT REGISTER
RESERVED
*)
ADC CONTROL REGISTER
TIMER 1 PRESCALER REGISTER
TIMER 1 COUNTER REGISTER
TIMER 1 STATUS/CONTROL REGISTER
TIMER 2 PRESCALER REGISTER
TIMER 2 COUNTER REGISTER
WATCHDOG REGISTER
0D1h
0D2h
0D3h
0D4h
0D5h
0D7h
0D8h
0FEh
0FFh
ACCUMULATOR
*) These registers contain write only bits, in which
case the bit operation instructions are not possi-
ble.
10/64
ST6373
MEMORY SPACES (Cont’d)
Data ROM Addressing. All the read-only data are
physically implemented in the ROM in which the
Program Space is also implemented. The ROM
therefore contains the program to be executed and
also the constants and the look-up tables needed
for the program. The locations of Data Space in
which the different constants and look-up tables
are addressed by the ST6 Core can be considered
as being a 64-byte window through which it is pos-
sible to access to the read-only data stored in the
ROM. This window is located from the 40h ad-
dress to the 7Fh address in the Data space and al-
lows the direct reading of the bytes from the 000h
address to the 03Fh address in the ROM. All the
bytes of the ROM can be used to store either in-
structions or read-only data. Indeed, the window
can be moved by step of 64 bytes along the ROM
in writing the appropriate code in the Write-only
Data ROM Window register (DRWR, location
C9h). The effective address of the byte to be read
as a data in the ROM is obtained by the concate-
nation of the 6 less significant bits of the address in
the Data Space (as less significant bits) and the
content of the DRWR (as most significant bits). So
when addressing location 40h of data space, and
0 is loaded in the DRWR, the physical addressed
location in ROM is 00h.
Data ROM Window Register (DWR)
Address: C9h - Write only
Reset Value: XXh
7
0
DWR7 DWR6 DWR5 DWR4 DWR3 DWR2 DWR1 DWR0
DWR7-DWR0. These are the Data Rom Window
bits that correspond to the upper bits of data ROM
program space. This register is undefined after re-
set.
Note:
Care is required when handling the DRWR as it is
write only. For this reason, it is not allowed to
change the DRWR contents while executing inter-
rupts drivers, as the driver cannot save and than
restore its previous content. If it is impossible to
avoid the writing of this register in interrupts driv-
ers, an image of this register must be saved in a
RAM location, and each time the program writes
the DRWR it writes also the image register. The
image register must be written first, so if an inter-
rupt occurs between the two instructions the
DRWR register is not affected.
Figure 6. Data ROM Window Memory Addressing
13 12 11 10
9
3
8
2
7
1
6
0
5
5
4
4
3
3
2
2
1
1
0
0
PROGRAM SPACE ADDRESS
READ
DATA ROM
WINDOW REGISTER
CONTENTS
7
6
5
4
DATA SPACE ADDRESS
40h-7Fh
(DWR)
0
1
IN INSTRUCTION
Example:
DWR=28h
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
DATA SPACE ADDRESS
59h
1
1
1
1
1
0
0
0
0
0
0
ROM
ADDRESS:A19h
0
0
1
1
VR01573B
11/64
ST6373
MEMORY SPACES (Cont’d)
1.3.4 Data RAM/EEPROM
DRBR7, DRBR1, DRBR0. These bits select the
EEPROM pages.
In the ST6373, 64 bytes of data RAM are directly
addressable in the data space from 80h to BFh ad-
dresses. The additional 128 bytes of RAM, and the
384 + 128 bytes of EEPROM can be addressed
using the 64-byte banks located between address-
es 00H and 3Fh. Bank selection is carried out by
programming the Data RAM Bank Register (DR-
BR) located at address E8h of the Data Space. In
this way each bank of RAM or EEPROM can se-
lect 64 bytes at a time. No more than one bank
should be set at a time.
This register is undefined after reset.
Table 5 summarizes how to set the Data RAM
Bank Register in order to select the various banks
or pages.
Note:
Care is required when handling the DRBR as it is
write only. For this reason, it is not allowed to
change the DRBR contents while executing inter-
rupts drivers, as the driver cannot save and than
restore its previous content. If it is impossible to
avoid the writing of this register in interrupts driv-
ers, an image of this register must be saved in a
RAM location, and each time the program writes
the DRBR it writes also the image register. The im-
age register must be written first, so if an interrupt
occurs between the two instructions the DRBR is
not affected.
Data RAM Bank Register (DRBR)
Address: E8h - Write only
Reset Value: XXh
7
0
DRBR DRBR DRBR DRBR DRBR DRBR DRBR DRBR
7
6
5
4
3
2
1
0
1.3.5 EEPROM Description
DRBR6
. This bit is reserved and must be held at
The data space of ST6373 devices, from 00h to
3Fh, is paged as described in Table 5. The 512
bytes of EEPROM are located in eight pages of 64
bytes (see Table 3 below).
“0”.
DRBR5, DRBR4
select one page of the EEPROM dedicated to the
DDC SPI.
. Each of these bits, when set, will
DRBR3, DRBR2
. Each of these bits, when set, will
select oneRAM page.
Table 5. Data RAM Bank Register Set-up
DRBR Value
Selection
Hex.
01h
02h
03h
04h
08h
10h
20h
81h
82h
83h
Binary
0000 0001
0000 0010
0000 0011
0000 0100
0000 1000
0001 0000
0010 0000
1000 0001
1000 0010
1000 0011
EEPROM Page 0
EEPROM Page 1
EEPROM Page 2
RAM Page 2
RAM Page 3
DDC EEPROM Page 0
DDC EEPROM Page 1
EEPROM Page 3
EEPROM Page 4
EEPROM Page 5
12/64
ST6373
MEMORY SPACES (Cont’d)
By programming the Data RAM Bank Register,
DRBR, the user can select the bank or page leav-
ing unaffected the means of addressing the static
registers. The way to address the “dynamic” page
is to set the DRBR as described in Table 5 (e.g. to
select EEPROM page 0, the DRBR has to be load-
ed with content 01h, see Data RAM/EEPROM ad-
dressing for additional information). Bits 0,1 and
4,5,7 of the DRBR are dedicated to the standard
EEPROM and DDC EEPROM respectively.
SB. WRITE ONLY. If this bit is set the EEPROM is
disabled (any access will be meaningless) and the
power consumption of the EEPROM is reduced to
the leakage values.
D5, D4. Reserved for testing purposes, they must
be set to zero.
PS
. SET ONLY. Once in Parallel Mode, as soon
as the user software sets the PS bit the parallel
writing of the 8 adjacent registers will start. PS is
internally reset at the end of the programming pro-
cedure. Note that less than 8 bytes can be written;
after parallel programming the remaining unde-
fined bytes will have no particular content.
The EEPROM pages do not require dedicated in-
structions to be accessed in reading or writing.
The standard EEPROM is controlled by the EEP-
ROM Control Register, EECR, the DDC EEPROM
is controlled by the DDC EPROM Control Register
DEECR, in the same way. Any EEPROM location
can be read just like any other data location, also
in terms of access time.
PE. WRITE ONLY. This bit must be set by the user
program in order to perform parallel programming
(more bytes per time). If PE is set and the “parallel
start bit” (PS) is low, up to 8 adjacent bytes can be
written at the maximum speed, the content being
stored in volatile registers. These 8 adjacent bytes
can be considered as row, whose A7, A6, A5, A4,
A3 are fixed while A2, A1 and A0 are the changing
bytes. PE is automatically reset at the end of any
parallel programming procedure. PE can be reset
by the user software before starting the program-
ming procedure, leaving unchanged the EEPROM
registers.
To write an EEPROM location takes an average
time of 5ms and during this time the EEPROM is
not accessible by the Core. A busy flag can be
read by the Core to know the EEPROM status be-
fore trying any access. In writing the EEPROM can
work in two modes: Byte Mode (BMODE) and Par-
allel Mode (PMODE). TheBMODE is the normal
way to use the EEPROM and consists in access-
ing one byte at a time. The PMODE consists in ac-
cessing 8 bytes per time.
BS. READ ONLY. This bit will be automatically set
by the CORE when the user program modifies an
EEPROM register. The user program has to test it
before any read or write EEPROM operation; any
attempt to access the EEPROM while “busy bit” is
set will be aborted and the writing procedure in
progress completed.
EEPROM Control Register (EECR)
Address: EAh - Read/Write
Reset Value: 00h
7
0
EN
. WRITE ONLY. This bit MUST be set to one in
order to write any EEPROM register. If the user
program will attempt to write the EEPROM when
EN= “0” the involved registers will be unaffected
and the “busy bit” will not be set.
Re-
Re-
-
SB
PS
PE
BS
EN
served served
DDC EEPROM Control Register (DDCEECR)
Address: E9h - Read/Write
Notes
:
When the EEPROM is busy (BS = “1”) the EECR
cannot be accessed in write mode, it is only possi-
ble to read BS status. This implies that, as long as
the EEPROM is busy, it is not possible to change
the status of the EEPROM control register. EECR
bits 4 and 5 are reserved for test purposes, and
must never be set.
Reset Value: 00h
7
0
Re-
Re-
-
SB
PS
PE
BS
EN
served served
D7
. Not used
13/64
ST6373
MEMORY SPACES (Cont’d)
Additional Notes on Parallel Mode. If the user
wants to perform a parallel programming the first
action should be the setting of the PE bit; from this
moment, the first time the EEPROM will be ad-
dressed in writing, the ROW address will be
latched and it will be possible to change it only at
the end of the programming procedure or by reset-
setting PE without programming the EEPROM.
For example, if the software sets PE and accesses
EEPROM in writing at addresses 18h,1Ah,1Bh
and then sets PS, these three registers will be
modified at the same time; the remaining bytes will
have no particular content. Note that PE is inter-
nally reset at the end of the programming proce-
dure. This implies that the user must set PE bit be-
tween two parallel programming procedures. Any-
way the user can set and then reset PE without
performing any EEPROM programming. PS is a
set only bit and is internally reset at the end of the
programming procedure. Note that if the user tries
to set PS while PE is not set there will not be any
programming procedure and the PS bit will be un-
affected. Consequently PS bit can not be set if EN
is low. PS can be affected by the user set if, and
only if, EN and PE bits are also set to one.
After the ROW address latching the Core can
“see” just one EEPROM row (the selected one)
and any attempt to write or read other rows will
produce errors. Do not read the EEPROM while
PE is set.
As soon as PE bit is set, the 8 volatile ROW latch-
es are cleared. From this moment the user can
load data in the whole ROW or just in a subset. PS
setting will modify the EEPROM registers corre-
sponding to the ROW latches accessed after PE.
14/64
ST6373
1.4 MEMORY PROGRAMMING
1.4.1 Program Memory
0 = 100KHz (default)
1 = 400KHz
The ST6373 OTP and EPROM MCUs can be pro-
grammed with a range of EPROM programming
tools available from SGS-THOMSON.
All other bits must be programmed as shown in the
register table above.
EPROM/OTP programming mode is set by a
The Option byte is written during programming ei-
ther by using the PC menu (PC driven Mode) or
automatically (stand-alone mode).
+12.5V voltage applied to the TEST/V pin. The
PP
programming flow is described in the User Manual
of the EPROM Programming Tool.
1.4.3 Eprom Erasure
1.4.2 Option Byte
Thanks to the transparent window present in the
EPROM package, its memory contents may be
erased by exposure to UV light.
The Option Byte allows OTP and EPROM ver-
sions to be configured to offer the same features
available as mask options in ROM devices. The
Option Byte’s content is automatically read, and
the selected options enabled on Reset.
Erasure begins when the device is exposed to light
with a wavelength shorter than 4000Å. It should be
noted that sunlight, as well as some types of artifi-
cial light, includes wavelengths in the 3000-4000Å
range which, on prolonged exposure, can cause
erasure of memory contents. It is thus recom-
mended that EPROM devices be fitted with an
opaque label over the window area in order to pre-
vent unintentional erasure.
The Option Byte can only be accessed during pro-
gramming mode. Access is either automatic (copy
from a master device) or by selecting the OPTION
BYTE PROGRAMMING mode of the programmer.
The option byte is located in a non-user map. No
address needs to be specified.
The recommended erasure procedure for EPROM
devices consists of exposure to short wave UV
light having a wavelength of 2537Å. The minimum
recommended integrated dose (intensity x expo-
Option Byte
7
0
0
0
2
sure time) for complete erasure is 15Wsec/cm .
0
0
0
X
0
1
This is equivalent to an erasure time of 15-20 min-
utes using a UV source having an intensity of
2
12mW/cm at a distance of 25mm (1 inch) from
the device window.
bit 3 = I2C Clock Speed:
15/64
ST6373
2 CENTRAL PROCESSING UNIT
2.1 INTRODUCTION
Indirect Registers (X, Y).
The CPU Core of ST6 devices is independent of the
I/O or Memory configuration. As such, it may be
thought of as an independent central processor
communicating with on-chip I/O, Memory and Pe-
ripherals via internal address, data, and control
buses. In-core communication is arranged as
shown in Figure 1; the controller being externally
linked to both the Reset and Oscillator circuits,
while the core is linked to the dedicated on-chip pe-
ripherals via the serial data bus and indirectly, for
interrupt purposes, through the control registers.
These two indirect reg-
isters are used as pointers to memory locations in
Data space. They are used in the register-indirect
addressing mode. These registers can be ad-
dressed in the data space as RAM locations at ad-
dresses 80h (X) and 81h (Y). They can also be ac-
cessed with the direct, short direct, or bit direct ad-
dressing modes. Accordingly, the ST6 instruction
set can use the indirect registers as any other reg-
ister of the data space.
Short Direct Registers (V, W).
These two regis-
ters are used to save a byte in short direct ad-
dressing mode. They can be addressed in Data
space as RAM locations at addresses 82h (V) and
83h (W). They can also be accessed using the di-
rect and bit direct addressing modes. Thus, the
ST6 instruction set can use the short direct regis-
ters as any other register of the data space.
2.2 CPU REGISTERS
The ST6 Family CPU core features six registers
and three pairs of flags available to the program-
mer. These are described in the following para-
graphs.
Accumulator (A)
. The accumulator is an 8-bit
Program Counter (PC). The program counter is a
12-bit register which contains the address of the
next ROM location to be processed by the core.
This ROM location may be an opcode, an oper-
and, or the address of an operand. The 12-bit
length allows the direct addressing of 4096 bytes
in Program space.
general purpose register used in all arithmetic cal-
culations, logical operations, and data manipula-
tions. The accumulator can be addressed in Data
space as a RAM location at address FFh. Thus the
ST6 can manipulate the accumulator just like any
other register in Data space.
Figure 7. ST6 Core Block Diagram
0,01 TO 8MHz
RESET
OSCin
OSCout
INTERRUPTS
DATA SPACE
CONTROLLER
CONTROL
SIGNALS
FLAG
VALUES
DATA
OPCODE
ADDRESS/READ LINE
2
RAM/EEPROM
PROGRAM
DATA
ADDRESS
ROM/EPROM
256
ROM/EPROM
DECODER
B-DATA
A-DATA
DEDICATIONS
ACCUMULATOR
Program Counter
and
12
FLAGS
6 LAYER STACK
ALU
RESULTS TO DATA SPACE(WRITE LINE)
VR01811
16/64
ST6373
CPU REGISTERS (Cont’d)
However, if the program space contains more than
4096 bytes, the additional memory in program
space can be addressed by using the Program
Bank Switch register.
automatically selected after the reset of the MCU,
the ST6 core uses at first the NMI flags.
Stack.
The ST6 CPU includes a true LIFO hard-
ware stack which eliminates the need for a stack
pointer. The stack consists of six separate 12-bit
RAM locations that do not belong to the data
space RAM area. When a subroutine call (or inter-
rupt request) occurs, the contents of each level are
shifted into the next higher level, while the content
of the PC is shifted into the first level (the original
contents of the sixth stack level are lost). When a
subroutine or interrupt return occurs (RET or RETI
instructions), the first level register is shifted back
into the PC and the value of each level is popped
back into the previous level. Since the accumula-
tor, in common with all other data space registers,
is not stored in this stack, management of these
registers should be performed within the subrou-
tine. The stack will remain in its “deepest” position
if more than 6 nested calls or interrupts are execut-
ed, and consequently the last return address will
be lost. It will also remain in its highest position if
the stack is empty and a RET or RETI is executed.
In this case the next instruction will be executed.
The PC value is incremented after reading the ad-
dress of the current instruction. To execute relative
jumps, the PC and the offset are shifted through
the ALU, where they are added; the result is then
shifted back into the PC. The program counter can
be changed in the following ways:
- JP (Jump) instruction. . . . . PC=Jump address
- CALL instruction . . . . . . . . . PC= Call address
- Relative Branch Instruction . PC= PC +/- offset
- Interrupt . . . . . . . . . . . . . .PC=Interrupt vector
- Reset . . . . . . . . . . . . . . . . . PC= Reset vector
- RET & RETI instructions . . . . PC= Pop (stack)
- Normal instruction . . . . . . . . . . . . .PC= PC + 1
Flags (C, Z). The ST6 CPU includes three pairs of
flags (Carry and Zero), each pair being associated
with one of the three normal modes of operation:
Normal mode, Interrupt mode and Non Maskable
Interrupt mode. Each pair consists of a CARRY
flag and a ZERO flag. One pair (CN, ZN) is used
during Normal operation, another pair is used dur-
ing Interrupt mode (CI, ZI), and a third pair is used
in the Non Maskable Interrupt mode (CNMI, ZN-
MI).
Figure 8. ST6 CPU Programming Mode
l
b7 X REG. POINTER b0
INDEX
REGISTER
SHORT
DIRECT
ADDRESSING
b7 Y REG. POINTER b0
MODE
The ST6 CPU uses the pair of flags associated
with the current mode: as soon as an interrupt (or
a Non Maskable Interrupt) is generated, the ST6
CPU uses the Interrupt flags (resp. the NMI flags)
instead of the Normal flags. When the RETI in-
struction is executed, the previously used set of
flags is restored. It should be noted that each flag
set can only be addressed in its own context (Non
Maskable Interrupt, Normal Interrupt or Main rou-
tine). The flags are not cleared during context
switching and thus retain their status.
b7
b7
V REGISTER
W REGISTER
b0
b0
b7 ACCUMULATOR
PROGRAM COUNTER
b0
b0
b11
SIX LEVELS
STACK REGISTER
The Carry flag is set when a carry or a borrow oc-
curs during arithmetic operations; otherwise it is
cleared. The Carry flag is also set to the value of
the bit tested in a bit test instruction; it also partici-
pates in the rotate left instruction.
NORMAL FLAGS
INTERRUPT FLAGS
NMI FLAGS
C
C
C
Z
Z
Z
The Zero flag is set if the result of the last arithme-
tic or logical operation was equal to zero; other-
wise it is cleared.
Switching between the three sets of flags is per-
formed automatically when an NMI, an interrupt or
a RETI instructions occurs. As the NMI mode is
VA000423
17/64
ST6373
3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES
3.1 ON-CHIP CLOCK OSCILLATOR
Figure 9. Clock Generator Option 1
The internal oscillator circuit is designed to require
a minimum of external components. A crystal
quartz, a ceramic resonator, or an external signal
(provided to the OSCin pin) may be used to gener-
ate a system clock with various stability/cost trade-
offs. The typical clock frequency is 8MHz. Please
note that different frequencies will affect the oper-
ation of those peripherals (D/As, SPI) whose refer-
ence frequencies are derived from the system
clock.
CRYSTAL/RESONATOR CLOCK
ST6xxx
OSC
OSC
out
in
The different clock generator connection schemes
are shown in Figure 1 and 2. One machine cycle
takes 13 oscillator pulses; 12 clock pulses are
needed to increment the PC while and additional
13th pulse is needed to stabilize the internal latch-
es during memory addressing. This means that
with a clock frequency of 8MHz the machine cycle
is 1.625µSec.
C
C
L1
L2
VA0016B
Figure 10. Clock Generator Option 2
The crystal oscillator start-up time is a function of
many variables: crystal parameters (especially
RS), oscillator load capacitance (CL), IC parame-
ters, ambient temperature, and supply voltage.It
must be observed that the crystal or ceramic leads
and circuit connections must be as short as possi-
ble. Typical values for CL1 and CL2 are in the
range of 15pF to 22pF but these should be chosen
based on the crystal manufacturers specification.
Typical input capacitance for OSCin and OSCout
pins is 5pF.
EXTERNAL CLOCK
ST6xxx
OSC
NC
OSC
in
out
The oscillator output frequency is internally divided
by 13 to produce the machine cycle and by 12 to
produce the Timers and the Watchdog clock. A
byte cycle is the smallest unit needed to execute
any operation (i.e., increment the program coun-
ter). An instruction may need two, four, or five byte
cycles to be executed (SeeTable 1).
VA0015C
Figure 11. OSCin, OSCout Diagram
OSCin, OSCout (QUARTZ PINS)
V
DD
Table 6. Instruction Timing with 8MHz Clock
Execution
OSCin
Instruction Type
Cycles
Time
Branch if set/reset
5 Cycles
4 Cycles
4 Cycles
4 Cycles
4 Cycles
2 Cycles
2 Cycles
8.125µs
1M
Branch & Subroutine Branch
Bit Manipulation
6.50 s
V
DD
µ
6.50µs
6.50µs
Load Instruction
In
OSCout
VA00462
Arithmetic & Logic
Conditional Branch
Program Control
6.50 s
µ
3.25µs
3.25µs
18/64
ST6373
3.2 RESETS
The MCU can be reset in three ways:
– by the external Reset input being pulled low;
– by Power-on Reset;
exit or enter the reset state correctly, without spu-
rious effects, ensuring, for example, that EEPROM
contents are not corrupted.
Note
: This feature is not available on OTP/EPROM
– by the digital Watchdog peripheral timing out.
3.2.1 RESET Input
Devices.
Figure 12. Power ON/OFF Reset operation
The RESET pin may be connected to a device of
the application board in order to reset the MCU if
required. The RESET pin may be pulled low in
RUN, WAIT or STOP mode. This input can be
used to reset the MCU internal state and ensure a
correct start-up procedure. The pin is active low
and features a Schmitt trigger input. The internal
Reset signal is generated by adding a delay to the
external signal. Therefore even short pulses on
V
DD
4.2
Threshold
3.4
the RESET pin are acceptable, provided V has
t
DD
completed its rising phase and that the oscillator is
running correctly (normal RUN or WAIT modes).
The MCU is kept in the Reset state as long as the
RESET pin is held low.
V
DD
If RESET activation occurs in RUN or WAIT
modes, processing of the user program is stopped
(RUN mode only), the Inputs and Outputs are con-
figured as inputs with pull-up resistors if available.
When the level on the RESET pin then goes high,
the initialization sequence is executed following
expiry of the internal delay period.
POWER
ON/OFF
RESET
t
VR02037
If RESET pin activation occurs in the STOP mode,
the oscillator starts up and all Inputs and Outputs
are configured as inputs with pull-up resistors if
available. When the level of theRESET pin then
goes high, the initialization sequence is executed
following expiry of the internal delay period.
Figure 13. Reset and Interrupt Processing
RESET
NMI MASK SET
INT LATCH CLEARED
( IF PRESENT )
3.2.2 Power-on Reset
The function of the POR circuit consists in waking
up the MCU at an appropriate stage during the
power-on sequence. At the beginning of this se-
quence, the MCU is configured in the Reset state:
all I/O ports are configured as inputs with pull-up
resistors and no instruction is executed. When the
power supply voltage rises to a sufficient level, the
oscillator starts to operate, whereupon an internal
delay is initiated, in order to allow the oscillator to
fully stabilize before executing the first instruction.
The initialization sequence is executed immediate-
ly following the internal delay.
SELECT
NMI MODE FLAGS
PUT FFEH
ON ADDRESSBUS
YES
IS RESET STILL
PRESENT?
The internal delay is generated by an on-chip
counter. The internal reset line is released 2048 in-
ternal clock cycles after release of the external re-
set.
NO
LOAD PC
FROM RESET LOCATIONS
FFE/FFF
The internal POR device is a static mechanism
which forces the reset state when V is below a
threshold voltage in the range 3.4 to 4.2 Volts (see
Figure 1). The circuit guarantees that the MCU will
DD
FETCH INSTRUCTION
VA000427
19/64
ST6373
RESETS (Cont’d)
3.2.3 Watchdog Reset
mode and enable interrupts. If no pending interrupt
is present at the end of the initialisation routine, the
MCU will continue by processing the instruction
immediately following the RETI instruction. If, how-
ever, a pending interrupt is present, it will be serv-
iced.
The MCU provides a Watchdog timer function in
order to ensure graceful recovery from software
upsets. If the Watchdog register is not refreshed
before an end-of-count condition is reached, the
internal reset will be activated. This, amongst oth-
er things, resets the watchdog counter.
Figure 14. Reset and Interrupt Processing
The MCU restarts just as though the Reset had
been generated by the RESET pin, including the
built-in stabilisation delay period.
RESET
3.2.4 Application Note
No external resistor is required between V and
DD
JP:2 BYTES/4 CYCLES
JP
the Reset pin, thanks to the built-in pull-up device.
RESET
VECTOR
3.2.5 MCU Initialization Sequence
When a reset occurs the stack is reset, the PC is
loaded with the address of the Reset Vector (locat-
ed in program ROM starting at address 0FFEh). A
jump to the beginning of the user program must be
coded at this address. Following a Reset, the In-
terrupt flag is automatically set, so that the CPU is
in Non Maskable Interrupt mode; this prevents the
initialisation routine from being interrupted. The in-
itialisation routine should therefore be terminated
by a RETI instruction, in order to revert to normal
INITIALIZATION
ROUTINE
RETI: 1 BYTE/2 CYCLES
RETI
VA00181
Figure 15. Reset Circuit
ST6
OSCILLATOR
SIGNAL
INTERNAL
RESET
COUNTER
TO ST6
1k
RESET
RESET
(ACTIVE LOW)
V
DD
300k
WATCHDOG RESET
POWER ON/OFF RESET
VA0200E
20/64
ST6373
3.3 HARDWARE ACTIVATED DIGITAL WATCHDOG FUNCTION
The hardware activated digital watchdog function
consists of a down counter that is automatically in-
itialized after reset so that this function does not
need to be activated by the user program. As the
watchdog function is always activated this down
counter can not be used as a timer. The watchdog
is using one data space register (HWDR location
D8h). The watchdog register is set to FEh on reset
and immediately starts to count down, requiring no
software start. Similarly the hardware activated
watchdog can not be stopped or delayed by soft-
ware.
possibility to generate a reset in a time between
3072 to 196608 oscillator cycles in 64 possible
steps. (With a clock frequency of 8MHz this means
from 384ms to 24.576ms). The reset is prevented
if the register is reloaded with the desired value
before bits 2-7 decrement from all zeros to all
ones.
The presence of the hardware watchdog deacti-
vates the STOP instruction and a WAIT instruction
is automatically executed instead of a STOP. Bit 1
of the watchdog register (set to one at reset) can
be used to generate a software reset if cleared to
zero). Figure 1shows the watchdog block diagram
while Figure 2 shows its working principle.
The watchdog time can be programmed using the
6 MSBs in the watchdog register, this gives the
Figure 16. Hardware Activated Watchdog Block Diagram
RESET
Q
RSFF
7
8
-2
-2
SET
-12
R
DB1.7 LOAD SET
S
OSCILLATOR
CLOCK
8
DB0
WRITE
RESET
DATA BUS
VA00010
21/64
ST6373
HARDWARE ACTIVATED DIGITAL WATCHDOG FUNCTION (Cont’d)
Hardware Activated Watchdog Register
(HWDR)
Figure 17. Hardware Activated Watchdog
Working Principle
Address: D8h - Read/Write
Reset Value: 0FEh
D0
D1
D2
D3
D4
D5
D6
D7
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
7
0
T1
T2
T3
T4
T5
T6
SR
C
T1-T6. These are the watchdog counter bits. It
should be noted that D7 (T1) is the LSB of the
counter and D2 (T6) is the MSB of the counter,
these bits are in the opposite order to normal.
RESET
SR. This bit is set to one during the reset phase
and will generate a software reset if cleared to ze-
ro.
C. This is the watchdog activation bit that is hard-
ware set. The watchdog function is always activat-
ed independently of changes of value of this bit.
The register reset value is FEh (Bit 1-7 set to one,
Bit 0 cleared).
8-BIT
DOWN COUNTER
OSC-12
VA00190
22/64
ST6373
3.4 INTERRUPT
The MCU Core can manage 4 different maskable
interrupt sources, plus one non-maskable interrupt
source (top priority level interrupt). Each source is
associated with a particular interrupt vector that
contains a Jump instruction to the related interrupt
service routine. Each vector is located in the Pro-
gram Space at a particular address (see Table 7).
When a source provides an interrupt request, and
the request processing is also enabled by the
MCU Core, then the PC register is loaded with the
address of the interrupt vector (i.e. of the Jump in-
struction). Finally, the PC executes the Jump in-
struction and the interrupt routine is processed.
struction (RETI included). Level sensitive inter-
rupts have to be valid during this period.
Table 7 details the different interrupt vec-
tors/sources relationships.
3.4.1 Interrupt Vectors/Sources
The MCU Core includes 5 different interrupt vec-
tors in order to branch to 5 different interrupt rou-
tines. The interrupt vectors are located in the fixed
(or static) page of the Program Space.
Table 7. Interrupt Vectors/Sources
Relationships
The relationship between vector and source and
the associated priority is hardware fixed for
ST6373 devices. For some interrupt sources it is
also possible to select by software the kind of
event that will generate the interrupt.
Associated
Vector
Vector
Address
Interrupt Source
Interrupt
Vector # 0 (NMI)
NMI pin
0FFCh-0FFDh
0FF6h-0FF7h
0FF4h-0FF5h
0FF2h-0FF3h
0FF0h-0FF1h
All interrupts can be disabled by writing to the GEN
bit (global interrupt enable) of the interrupt option
register (address C8h). Following a reset, the
ST6373 is in non maskable interrupt mode, so no
interrupts will be accepted and NMI flags will be
used, until a RETI instruction is executed. If an in-
terrupt is executed, one special cycle is made by
the core, during that the PC is set to the related in-
terrupt vector address. A jump instruction at this
address has to redirect program execution to the
beginning of the related interrupt routine. The in-
terrupt detecting cycle, also resets the related in-
terrupt flag (not available to the user), so that an-
other interrupt can be stored for this current vector,
while its driver is under execution.
Timer 3
I/O Port A, I/O Port B
Interrupt
Vector # 1
Timer 2
2
Interrupt
Vector #2
VSYNC,
SPI
I C
Timer 1
DDC SPI
Interrupt
Vector #3
ADC
PWRIN
Interrupt
Vector #4
The interrupt vector associated with the non-
maskable interrupt source is named interrupt vec-
tor #0. It is located at the (FFCh, FFDh) addresses
in the Program Space. This vector is associated
with the NMI pin.
If additional interrupts arrive from the same
source, they will be lost. NMI can interrupt other in-
terrupt routines at any time, while other interrupts
cannot interrupt each other. If more than one inter-
rupt is waiting for service, they are executed ac-
cording to their priority. The lower the number, the
higher the priority. Priority is, therefore, fixed. In-
terrupts are checked during the last cycle of an in-
The interrupt vectors located at addresses
(FF6h,FF7h),
(FF4h,FF5h),
(FF2h,FF3h),
(FF0h,FF1h) are named interrupt vectors #1, #2,
#3 and #4 respectively. These vectors are associ-
ated with TIMER 3, Port A and Port B interrupts
2
(#1), Timer 2, VSYNC and I C SPI (#2), TIMER 1
and the DDC SPI (#3) and the ADC and PC4
(PWRIN) (#4).
23/64
ST6373
INTERRUPTS (Cont’d)
3.4.2 Interrupt Priority
NMI/PWR/VSync Interrupt Register (NPVIR)
The non-maskable interrupt request has the high-
est priority and can interrupt any other interrupt
routines at any time, nevertheless the other inter-
rupts cannot interrupt each other. If more than one
interrupt request is pending, they are processed
by the MCU Core according to their priority level:
vector #1 has the higher priority while vector #4
the lower. The priority of each interrupt source is
hardware fixed.
7
0
D7
D6
D5
D4
D3
D2
D1
D0
b7: VSYNCST: (Read & Write, 0 written on Reset)
VSYNCEN
b6:
: (Read & Write, 0 written on Reset)
b5:PWRFLAG:(Read&Write,Undefined onReset)
b4: PWINTEN: (Write Only, 0 written on Reset)
3.4.3 Interrupt Option Register
PWREDGE
: (Write Only, 0 written on Reset)
b3:
The Interrupt Option Register (IOR register, loca-
tion C8h) is used to enable/disable the individual
interrupt sources and to select the operating mode
of the external interrupt inputs. This register is ad-
dressed in the Data Space as a RAM location at
address C8h, nevertheless it is write-only register
that can not be accessed with single-bit opera-
tions. The operating modes of the external inter-
rupt inputs associated to interrupt vectors #1 and
#2 are selected through bits 4 and 5 of the IOR
register.
b2:NMIFLAG:(Read &Write, Undefined on Reset)
b1: NMINTEN: (Write Only, 0 written on Reset)
b0: NMIEDGE: (Write Only, 0 written on Reset)
Note that NObit operation instructions are possible.
The input latch is activated on either the positive or
negative edge of the NMI (respectively PWRIN)
signal: if NMIEDGE (resp. PWREDGE) is high the
latch will be triggered on the rising edge of the sig-
nal at NMI (resp. PWRIN); if this bit is low the latch
will be triggered on the falling edge.
Interrupt Option Register (IOR)
Address: (C8h) - Write only
Reset Value: XX00XXXXb
An interrupt can be generated if it is enabled: if
NMINTEN (resp. PWINTEN) is high, then the out-
put of the latch may generate an interrupt on vec-
tor #0 (resp. vector #4); if this bit is low the inter-
rupt is disabled.
7
0
-
-
EL1 ES2 GEN
-
-
-
The status of the latch is read with NMIFLAG (re-
sp. PWRFLAG): if NMIFLAG (resp. PWRFLAG) is
high, a signal has been latched. The latch can be
reset by setting NMIFLAG (resp. PWRFLAG).
D7
. Not used.
EL1. This is the Edge/Level selection bit of inter-
rupt #1. When set to one, the interrupt is generat-
ed on low level of the related signal; when cleared
to zero, the interrupt is generated on falling edge.
The bit is cleared to zero after reset.
The VSYNC input is linked to the interrupt vector #
2 through a latch.
If 1 is written in VSYNCST the latch will be trig-
gered on the rising edge of the signal at VSYNC, if
VSYNCST is low the latch will be triggered on the
falling edge (0 written on Reset).
ES2
. This is the edge selection bit on interrupt #2.
This bit is used in ST6373 devices for VSYNC de-
2
tection, the interrupt for Timer 2 and the IC SPI. It
is cleared to zero on reset (falling edge), and must
2
be maintained at 0 if the Timer 2 and IC interrupts
An interrupt can be generated only if VSYNCEN is
at 1. Writing a 1 in VSYNCEN will also reset the
latch (0 written on Reset).
are to be used. The VSYNC interrupt may be con-
figured to act on the falling edge (ES2=0) or rising
edge (ES2=1) according to the system design.
The status of the latch is read through the bit
VSYNCEN; reading a 1 means that a signal has
been latched.
GEN
. This is the global enable bit. When set to
one all interrupts are globally enabled; when this
bit is cleared to zero all interrupts are disabled (ex-
cluding NMI) independently to the individual inter-
rupt enable bit of each peripheral.
The status of the VSYNC pin is read with the
VSYNCST bit.
D3 - D0
. These bits are not used.
24/64
ST6373
INTERRUPTS (Cont’d)
3.4.4 Interrupt Procedure
Figure 18. Interrupt Processing Flow-Chart
The interrupt procedure is very similar to a call pro-
cedure; the user can consider the interrupt as an
asynchronous call procedure. As this is an asyn-
chronous event the user does not know about the
context and the time at which it occurred. As a re-
sult the user should save all the data space regis-
ters which will be used inside the interrupt rou-
tines. There are separate sets of processor flags
for normal, interrupt and non-maskable interrupt
modes which are automatically switched and so
these do not need to be saved.
INSTRUCTION
FETCH
INSTRUCTION
EXECUTE
INSTRUCTION
The following list summarizes the interrupt proce-
dure (refer also to Figure 20. Interrupt Processing
Flow Chart):
WAS
THE INSTRUCTION
A RETI
NO
LOAD PC FROM
INTERRUPT VECTOR
( FFC / FFD )
YES
– Interrupt detection
IS THE CORE
ALREADY IN
NORMAL MODE ?
YES
– The flags C and Z of the main routine are ex-
changed with the flags C and Z of the interrupt
routine (resp. the NMI flags)
SET
?
INTERRUPT MASK
NO
CLEAR
PUSH THE
PC INTO THE STACK
– The value of the PC is stored in the first level of
the stack - The normal interrupt lines are inhibit-
ed (NMI still active)
INTERRUPT MASK
SELECT
SELECT
INTERNAL MODE FLAG
– The edge flip-flop is reset
PROGRAM FLAGS
– The related interrupt vector is loaded in the PC.
” POP ”
THE STACKED PC
– User selected registers are saved inside the in-
terrupt service routine (normally on a software
stack)
CHECK IF THERE IS
AN INTERRUPT REQUEST
AND INTERRUPT MASK
NO
?
– The source of the interrupt is found by polling (if
more than one source is associated to the same
vector)
YES
– Interrupt servicing
VA000014
– Return from interrupt (RETI)
– Automatically the MCU Core switches back to
the normal flags (resp. the interrupt flags) and
pops the previous PC value from the stack
3.4.5 ST6373 Interrupt Details
Interrupt #0. The NMI Interrupt is connected to the
first interrupt #0 (NMI, Pin 27). If the NMI interrupt
is disabled at the latch circuitry, then it will be high.
The #0 interrupt input detects a high to low level.
Note that once #0 has been latched, then the only
way to remove the latched #0 signal is to service
the interrupt. #0 can interrupt the other interrupts.
The interrupt routine begins usually by the identifi-
cation of the device that has generated the inter-
rupt request. The user should save the registers
which are used inside the interrupt routine (that
holds relevant data) into a software stack.
After the RETI instruction execution, the Core car-
ries out the previous actions and the main routine
can continue.
25/64
ST6373
INTERRUPTS (Cont’d)
Interrupt #1. The TIMER 3 Interrupt and the Port
A and B interrupts are connected by a logical AND
function to interrupt #1 (0FF6h). The TIMER 3 in-
terrupt generates a low level (which is latched in
the timer) requiring that the Interrupt 1 Edge/Level
bit is set to 1. The I/O Port A and B interrupts may
be set to generate an interrupt on the falling edge
or low level state of the input (EL1 = 1 or EL1 = 0
respectively) according to the external connec-
tions.Note that if a low level is maintained on an
I/O bit configured as acting on a Low Level after
the interrupt is generated, the MCU will return to
the interrupt state after exiting the RETI instruction
from the first interrupt service.
VIR) will cause a spurious interrupt.(see Interrupt
Circuit Diagram)
Interrupt #3
. The TIMER 1 and DDC SPI Interrupt
are connected by a logical AND function to inter-
rupt #3. This interrupt is triggered on detection of a
low level latched in the timer and DDC SPI.
Interrupt #4
. The PWRIN and Analog to Digital
Converter Interrupts are connected by a Logical
AND to interrupt #4 (0FF0h). The PWRIN interrupt
is controlled through the NPVIR Register at ad-
dress EDh, and the Phase Unlock interrupt is con-
trolled through SPCR at address DFh. The #4 in-
terrupt input detects a low level. A simple latch is
provided from the PC4 (PWRIN) pin in order to
generate the PWRINT signal. This latch can be
triggered by either the positive or negative edge of
the PWRIN signal (bit 3, PWREDGE, of register
NPVIR EDh). The latch is reset by software.
2
Interrupt #2.The VSYNC, Timer 2 and I C SPI In-
terrupt are connected by a logical AND function to
interrupt #2. Bit 5 of the interrupt option register
C8h is used to select the negative edge (ES2=0)
or the positive edge (ES2=1) to trigger the inter-
rupt #2.For the correct operation of the Timer 2
Notes
:
2
and I C SPI interrupts, the falling edge should be
Global disable does not reset edge sensitive inter-
rupt flags. These edge sensitive interrupts become
pending again when global disabling is released.
Moreover, edge sensitive interrupts are stored in
the related flags also when interrupts are globally
disabled, unless each edge sensitive interrupt is
also individually disabled before the interrupting
event happens. Global disable is done by clearing
the GEN bit of Interrupt option register, while any
individual disable is done in the control register of
the peripheral. The on-chip Timer peripherals
have an interrupt request flag bit (TMZ), this bit is
set to one when the device wants to generate an
interrupt request and a mask bit (ETI) that must be
set to one to allow the transfer of the flag bit to the
Core.
selected (ES2 = 0).For the VSYNC interrupt, either
edge can be selected, depending on the operation
required. For example if the rising edge on VSYNC
is the trigger, and after receiving the interrupt
edge, the VSYNC trigger level is switched to the
falling edge, the time between the rising and falling
edge (e.g. the display time) to be determined. The
VSYNC interrupt is controlled in Register NPVIR
at address EDh.
Note that once an edge has been latched, then the
only way to remove the latched signal is to service
the interrupt. Care must be taken not to generate
spurious interrupts. For example, changing the
edge selection bit from falling edge to rising edge
when the VSYNC input is high (or disabled in NP-
26/64
ST6373
INTERRUPTS (Cont’d)
Figure 19. Interrupt Circuit Diagram
27/64
ST6373
3.5 POWER SAVING MODES
STOP and WAIT modes have been implemented
in the ST638x in order to reduce the current con-
sumption of the device during idle periods. These
two modes are described in the following para-
graphs. Since the hardware activated digital
watchdog function is present, the STOP instruc-
tion is de-activated and any attempt to execute it
will cause the automatic execution of a WAIT in-
struction.
mode) before the start of the WAIT sequence, but
also of the type of the interrupt request that is gen-
erated. In all cases the GEN bit of IOR has to be
set to 1 in order to restart from WAIT mode. Con-
trary to the operation of NMI in the run mode, the
NMI is masked in WAIT mode if GEN=0.
Normal Mode. If the MCU Core was in the main
routine when the WAIT instruction has been exe-
cuted, the Core exits from WAIT mode as soon as
an interrupt occurs; the corresponding interrupt
routine is executed, and at the end of the interrupt
service routine, the instruction that follows the
WAIT instruction is executed if no other interrupts
are pending.
3.5.1 WAIT Mode
The configuration of the MCU in the WAIT mode
occurs as soon as the WAIT instruction is execut-
ed. The microcontroller can also be considered as
being in a “software frozen” state where the Core
stops processing the instructions of the routine,
the contents of the RAM locations and peripheral
registers are saved as long as the power supply
voltage is higher than the RAM retention voltage
but where the peripherals are still working. The
WAIT mode is used when the user wants to re-
duce the consumption of the MCU when it is in
idle, while not losing count of time or monitoring of
external events. The oscillator is not stopped in or-
der to provide clock signal to the peripherals. The
timers counting may be enabled (writing the PSI
bit in TSCR1 register) and the timer interrupt may
be also enabled before entering the WAIT mode;
this allows the WAIT mode to be left when timer in-
terrupt occurs. If the exit from the WAIT mode is
performed with a general RESET (either from the
activation of the external pin or by watchdog reset)
the MCU will enter a normal reset procedure as
described in the RESET chapter. If an interrupt is
generated during WAIT mode the MCU behaviour
depends on the state of the MCU Core before the
initialization of the WAIT sequence, but also of the
kind of the interrupt request that is generated. This
case will be described in the following paragraphs.
In any case, the MCU Core does not generate any
delay after the occurrence of the interrupt because
the oscillator clock is still available.
Non-maskable Interrupt Mode
. If the WAIT in-
struction has been executed during the execution
of the non-maskable interrupt routine, the MCU
Core outputs from WAIT mode as soon as any in-
terrupt occurs: the instruction that follows the
WAIT instruction is executed and the MCU Core is
still in the non-maskable interrupt mode even if an-
other interrupt has been generated.
Normal Interrupt Mode. If the MCU Core was in
the interrupt mode before the initialization of the
WAIT sequence, it outputs from the wait mode as
soon as any interrupt occurs. Nevertheless, two
cases have to be considered:
– If the interrupt is a normal interrupt, the interrupt
routine in which the WAIT was entered will be
completed with the execution of the instruction
that follows the WAIT and the MCU Core is still in
the interrupt mode. At the end of this routine
pending interrupts will be serviced in accordance
to their priority.
– If the interrupt is a non-maskable interrupt, the
non-maskable routine is processed at first. Then,
the routine in which the WAIT was entered will be
completed with the execution of the instruction
that follows the WAIT and the MCU Core is still in
the normal interrupt mode.
3.5.2 STOP Mode
Notes
:
Since the hardware activated watchdog is present
on the ST638x, the STOP instruction has been de-
activated. Any attempt to execute a STOP instruc-
tion will cause a WAIT instruction to be executed
instead.
If all the interrupt sources are disabled, the restart
of the MCU can only be done by a Reset activa-
tion. The Wait instruction is not executed if an en-
abled interrupt request is pending. In ST638x de-
vices, the hardware activated digital watchdog
function is present. As the watchdog is always ac-
tivated, the STOP instruction is de-activated and
any attempt to execute the STOP instruction will
cause an execution of a WAIT instruction.
3.5.3 Exit from WAIT Mode
The following paragraphs describe the output pro-
cedure of the MCU Core from WAIT mode when
an interrupt occurs. It must be noted that the re-
start sequence depends on the original state of the
MCU (normal, interrupt or non-maskable interrupt
28/64
ST6373
4 ON-CHIP PERIPHERALS
4.1 I/O PORTS
The ST6373 microcontroller uses three I/O ports
(A,B,C) with up to eight pins on each port. Each
line can be individually programmed either in the
input mode or the output mode with the following
software selectable options:
The three Data registers (DRA, DRB, DRC) are
used to read the voltage level values of the lines
programmed in the input mode, or to write the logic
value of the signal to be output on the lines config-
ured in the output mode. The port Data Registers
can be read to get the effective logic levels of the
pins, but they can be also written by the user soft-
ware, in conjunction with the related Data Direc-
tion Register and Option Register (Ports A and B
only), to select the different input mode options.
– Input without interrupt and without pull-up (Ports
A, B and C)
– Input withpull-up and withinterrupt (PA0-PA5 and
Port B)
Single-bit operations on I/O registers (bit set/reset
instructions) are possible but care is necessary
because reading in input mode is made from I/O
pins and therefore might be influenced by the ex-
ternal load, while writing will directly affect the Port
data register causing an undesired changes of the
input configuration.
– Input with pull-up without interrupt (PA0-PA5 and
Port B, PC2-PC7)
– Analog Inputs (PB0-PB7)
– Open-drain output 12V, no pull-up (PC4-PC7)
– Open-drain output 5V (PA0-PA7, PB0-PB7,
PC0-PC3)
The three Data Direction registers (DDRA, DDRB,
DDRC) allow the selection of the direction of each
pin (input or output).
– Push-pull output (PA0-PA5, PB0-PB7)
2
– SPI control signals (PA6,PA7 for I C SPI,
PC0,PC1,PC3 for DDC SPI)
The two Option registers (ORA and ORB) are used
to select the different port options available both in
input and in output mode for Ports A and B only.
–
Horizontal Timing inputs (PC6/HSYNC,
PC7/HDRIV
All the I/O registers can be read or written as any
other RAM location of the data space, so no extra
RAM cell is needed for port data storing and ma-
nipulation. During the initialization of the MCU, all
theI/Oregisters areclearedand theinput modewith
pull-up is selected on all the pins thus avoiding pin
conflicts (with the exception of PC2 which is set to
output mode with the value 1 (high impedance).
– External Power In Interrupt (PC4)
The lines are organized in three ports (Ports A, B,
C). The ports occupy 8 registers in the data space.
Each bit of these registers is associated with a par-
ticular line (for instance, the bits 0 of the Port A Da-
ta, Direction and Option registers are associated
with the PA0 line of Port A).
Figure 20. I/O Port Block Diagram (PA0-PA5 and Port B)
RESET
V
DD
S
CONTROLS
IN
V
DD
DATA
DIRECTION
REGISTER
INPUT/OUTPUT
DATA
REGISTER
SHIFT
REGISTER
OPTION
REGISTER
S
OUT
TO INTERRUPT
TO ADC
VA000413
29/64
ST6373
I/O PORTS (Cont’d)
4.1.1 Details of I/O Ports A and B
is not selected, the input pin is in the high imped-
ance state.
Each pin of Ports A and B can be individually pro-
grammed as input or output with different input
and output configurations.
Interrupt Option
. All the input lines can be individ-
ually connected by software to the interrupt lines of
the MCU core according to the codes programmed
in the OR and DR registers. The pins of Port A and
B are “ORed” and are connected to the interrupt
associated to the vector #1.
This is achieved by writing the relevant bit in the
data register (DR), data direction register (DDR)
and option register (OR). Table 8 shows all the
port configurations that can be selected by user
software.
Analog Input Option. The PB0-PB7 pins can be
configured to be analog inputs according to the
codes programmed in the OR and DR registers.
These analog inputs are connected to the on-chip
8-bit Analog to Digital Converter. ONLY ONE pin
should be programmed as analog input at a time,
otherwise the selected inputs will be shorted.
4.1.1.1 Input Option Description
Pull-up, High Impedance Option
. All the input
lines can be individually programmed with or with-
out an internal pull-up according to the codes pro-
grammed in the OR and DR registers. If the pull-up
Table 8. I/O Port Options Selection (Ports A and B only)
DDR
OR
0
DR
0
Mode
Input
Option
0
0
0
With pull-up, no interrupt (Reset state)
No pull-up, no interrupt
0
1
Input
1
0
Input
With pull-up, with interrupt
Input
No pull-up, no interrupt (Port A pins)
Analog input (Port B pins)
0
1
1
Input
1
1
0
1
X
X
Output
Output
Open-drain output (10mA sink current for Port A pins)
Push-pull output (10mA sink current for Port A pins)
Note X: Means don’t care.
30/64
ST6373
I/O PORTS (Cont’d)
4.1.1.2 Output Option Description
Output Option
therefore these characteristics may be uninten-
tionally reprogrammed, depending on the state of
input pins. As general rule is better to use single bit
instructions on data register only when the whole
port is in output mode. If input or mixed configura-
tion is needed it is recommended to keep a copy of
the data register in RAM. On this copy it is possible
to use single bit instructions, then the copy register
could be written into the port data register.
Port A and B pins in output modes can be set to
Open Drain or Push-Pull modes (not for PA6 and
PA7). Port A bits set to output have a maximum
10mA current sink LED drive capability.
2
4.1.1.3 I C SPI Input/Output
2
If the user uses the I C serial peripheral interface,
SET
LD
LD
bit, datacopy
a, datacopy
DRA, a
the I/O lines PA6 and PA7 should be set in output
mode with the open-drain configuration; the corre-
sponding data bit must set to one.
Note
. Switching the I/O ports with interrupt (Ports
4.1.2 Details of I/O Port C
A and B) from one state to another should be done
in a way that no unwanted side effects can hap-
pen. The recommended safe transitions are
shown below. All other transitions are risky and
should be avoided during change of operation
mode as it is most likely that there will be an un-
wanted side-effect such as interrupt generation or
two pins shorted together by the analog input
lines.
Port C
. When programmed as an input an internal
pull-up can be switched active under program con-
trol. When programmed as an output the Port C
I/O pins will operate in the open-drain mode. PC0-
PC3 are available as open-drain capable of with-
standing a maximum VDD+0.3V. PC4-PC7 are
available as open-drain capable of withstanding
12V and have no resistive pull-up in input mode.
If the user uses the DDC serial peripheral inter-
face, the I/O lines PC0 and PC1 should be set in
output mode while the open-drain configuration is
hardware fixed; the corresponding data bit must
set to one.If the latched interrupt functions are
used (HSYNC,(HSYNC, HDRIVE, PWRIN) then
the corresponding pins should be set to input
mode.
Single bit instructions (SET, RES, JRR and JRS)
should be used very carefully with Port A and B
data registers because these instructions make an
implicit read and write back of the whole ad-
dressed register byte. In port input mode however
data register address reads from input pins, not
from data register latches and data register infor-
mation in input mode is used to set characteristics
of the input pin (interrupt, pull-up, analog input),
Figure 21. State Transition Diagram for Safe Transitions (Ports A and B)
Interrupt
pull-up
Input
Analog
010*
000
011
001
Input
pull-up (Reset
state)
Input
Output
Open Drain
Output
Open Drain
100
110
101
111
Output
Push-pull
Output
Push-pull
Note
*.xxx = DDR, OR, DR bits respectively
31/64
ST6373
I/O PORTS (Cont’d)
Table 9. I/O Port Option Selections
MODE
AVAILABLE ON(1)
SCHEMATIC
PA0-PA7
PB0-PB7
PC0-PC7
Input
Data in
Interrupt
PA0-PA5
PB0-PB7
PC2, PC3
Input
Data in
with pull up
Interrupt
Input
PA0-PA5
PB0-PB7
with pull up
with interrupt
Data in
Interrupt
Analog Input
PB0-PB7
ADC
Open drain output
PB0-PB7
PC0-PC7
PA0-PA7
5mA / V +0.3V
DD
Open drain output
Data out
10mA / V +0.3V
DD
PC4-PC7
Open drain output
5mA / 12V
Push-pull output
5mA
PB0-PB7
Data out
PA0-PA5
Push-pull output
10mA
Note 1
. Provided the correct configuration has been selected.
32/64
ST6373
I/O PORTS (Cont’d)
4.1.2.1 Port C I/O Pin Programming
Table 10. I/O Port Options Selection (Port C)
Each Port C pin can be individually programmed
as input or output. This is achieved by writing to
the relevant bit in the data (DRC) and data direc-
tion register (DDRC). Table 9 shows all the port
configurations that can be selected by the user
software.
DDR
DR
0
Mode
Option
0
0
1
Input
With on-chip pull-up resistor
1
Input Without on-chip pull-up resistor
Output Open-drain
X
Note
4.1.2.2 Port C Input/Output Configurations
: X. Means don’t care.
The following schematics show the I/O lines hard-
ware configuration for the different options. Figure
31 shows the I/O configuration for an I/O pin with
open-drain 12V capability (standard drive and high
drive). Figure 32 shows the I/O configuration for an
I/O pin with open-drain 5V capability.
Figure 22. I/O Configuration Diagram
(Open Drain 12V)
I/O HIGH DRIVE, OPEN DRAIN 12V
In
(5mA, 1V)
I/O
Note:
All the Port A, B and C I/O lines have Schmitt-trig-
ger input configuration with a typical hysteresis of
1V.
Out
N
VA00342
Figure 23. I/O Configuration Diagram (Open Drain 5V)
OPEN-DRAIN OUTPUT
V
DD
*
In
I/O (OPEN-DRAIN, 5V)
Out
N
*
In Input mode only, SW programmable (~ 200k
)
VA00345A
33/64
ST6373
4.1.3 I/O Port Registers
4.1.3.1 Data Registers
line is in input mode, if bit is set to one the related
I/O line is in output mode. Reset at power-on.
Ports A, B, C Data Register
PC7-PC0
. These are the I/O Port C data direction
:
-
Address C0h (PA), C1h (PB), C2h (PC)
bits. When a bit is cleared to zero the related I/O
line is in input mode, if bit is set to one the related
I/O line is in output mode. Set to 04H at power-on.
Bit 2 (PC2 pin) is set to one (output mode select-
ed).
Read/Write
Reset Value: 00h
7
0
PA/PB PA/PB PA/PB PA/PB PA/PB PA/PB PA/PB PA/PB
/PC7 /PC6 /PC5 /PC4 /PC3 /PC2 /PC1 /PC0
4.1.3.3 Option Registers
Port A, B, C Option Register
Address: CCh (PA), CDh (PB) - Read/Write
Reset value:00h
PA7-PA0. These are the I/O Port A data bits. Re-
set at power-on.
PB7-PB0
. These are the I/O Port B data bits. Re-
set at power-on.
7
0
PC7-PC0
. These are the I/O Port C data bits. Set
PA/PB7 PA/PB6PA/PB5 PA/PB4PA/PB3 PA/PB2 PA/PB1 PA/PB0
to 04H at power-on. Bit 2 (PC2 pin) is set to one
(open-drain therefore high impedance).
PA7-PA0.
These are the I/O Port A option bits.
4.1.3.2 Data Direction Registers
These are set in conjunction with the correspond-
ing data and data direction bits to set the individual
Port A bit I/O mode.
Ports A, B, C Data Direction Register
Address: C4h (PA), C5h (PB), C6h (PC) -
Read/Write
PB7-PB0
. These are the I/O Port B option bits.
These are set in conjunction with the correspond-
ing data and data direction bits to set the individual
Port B bit I/O mode.
Reset Value: 00h
7
0
PA/PB PA/PB PA/PB PA/PB PA/PB PA/PB PA/PB PA/PB
Notes
: The WAIT instruction allows the MCU to be
/PC7
/PC6 /PC5 /PC4 /PC3
/PC2 /PC1 /PC0
used in situations where low power consumption is
required. This can only be achieved, however, if
the I/O pins are programmed as inputs with well
defined logic levels or have no power consuming
resistive loads in output mode.
PA7-PA0
. These are the I/O Port A data direction
bits. When a bit is cleared to zero the related I/O
line is in input mode, if bit is set to one the related
I/O line is in output mode. Reset at power-on.
Single-bit operations on I/O registers are possible
but care is necessary because reading in input
mode is from I/O pins while writing will directly af-
fect the Port data register.
PB7-PB0
. These are the I/O Port B data direction
bits. When a bit is cleared to zero the related I/O
34/64
ST6373
4.2 TIMERS
The ST638x devices offer two on-chip Timer pe-
ripherals consisting of an 8-bit counter with a 7-bit
programmable prescaler, thus giving a maximum
The prescaler decrements on rising edge. The
prescaler input is the oscillator frequency divided
by 12. Depending on the division factor pro-
grammed by PS2/PS1/PS0 (seeTable 1 ) bits in
the TSCR, the clock input of the timer/counter reg-
ister is multiplexed to different sources. On divi-
sion factor 1, the clock input of the prescaler is
also that of timer/counter; on factor 2, bit 0 of pres-
caler register is connected to the clock input of
TCR.
15
count of 2 , and a control logic that allows config-
uration the peripheral operating mode. Figure 1
shows the Timer block diagram. The content of the
8-bit counters can be read/written in the Tim-
er/Counter registers TCR that are addressed in
the data space as RAM locations at addresses
D3h (Timer 1), DBh (Timer 2). The state of the 7-
bit prescaler can be read in the PSC register at ad-
dresses D2h (Timer 1) and DAh (Timer 2). The
control logic is managed by TSCR registers at D4h
(Timer 1) and DCh (Timer 2) addresses as de-
scribed in the following paragraphs.
This bit changes its state with the half frequency of
prescaler clock input. On factor 4, bit 1 of PSC is
connected to clock input of TCR, and so on. On di-
vision factor 128, the MSB bit 6 of PSC is connect-
ed to clock input of TCR. The prescaler initialize bit
(PSI) in the TSCR register must be set to one to al-
low the prescaler (and hence the counter) to start.
If it is cleared to zero then all of the prescaler bits
are set to one and the counter is inhibited from
counting.The prescaler can be given any value be-
tween 0 and 7Fh by writing to the related register
address, if bit PSI in the TSCR register is set to
one. The tap of the prescaler is selected using the
PS2/PS1/PS0 bits in the control register.Figure 2
illustrates the Timer working principle.
The following description applies to all Timers. The
8-bit counter is decrement by the output (rising
edge) coming from the 7-bit prescaler and can be
loaded and read under program control. When it
decrements to zero then the TMZ (timer zero) bit in
the TSCR is set to one. If the ETI (enable timer in-
terrupt) bit in the TSCR is also set to one an inter-
rupt request, associated to interrupt vector #3 for
Timer 1 and #1 for Timer 2, is generated. The in-
terrupt of the timer can be used to exit the MCU
from the WAIT mode.
Figure 24. Timer Peripheral Block Diagram
DATABUS
8
8
8
8
6
5
4
3
2
b5
b1
b0
b7
b6
b4
b3
b2
8-BIT
COUNTER
STATUS/CONTROL
REGISTER
SELECT
1 OF 8
PSC
TMZ ETI TOUT
PSI
PS1
PS0
DOUT
PS2
1
0
3
TIMER
INTERRUPT
LINE
LATCH
SYNCHRONIZATION
LOGIC
:12
fOSC
VA00009
35/64
ST6373
TIMERS (Cont’d)
4.2.1 Timer Operating Modes
Since in the ST638x devices the external TIMER
pin is not connected, the only allowed operating
mode is the output mode, which is selected by set-
ting bit 4 and by clearing bit 5 in the TSCR1 regis-
ter. This procedure will enable Timer 1 and
Timer 2.
vector #1 (for Timer 2) is generated. When the
counter decrements to zero also the TMZ bit in the
TSCR register is set to one.
Notes:
TMZ is set when the counter reaches 00h; howev-
er, it may be set by writing 00h in the TCR register
or setting the bit 7 of the TSCR register. TMZ bit
must be cleared by user software when servicing
the timer interrupt to avoid undesired interrupts
when leaving the interrupt service routine. After re-
set, the 8-bit counter register is loaded to FFh
while the 7-bit prescaler is loaded to 7Fh, and the
TSCR register is cleared which means that timer is
stopped (PSI=0) and timer interrupt disabled.
Output Mode (TSCR1 D4 = 1, TSCR1 D5 = 0). On
this mode the timer prescaler is clocked by the
prescaler clock input (OSC/12). The user can se-
lect the desired prescaler division ratio through the
PS2/PS1/PS0 bits. When TCR count reaches 0, it
sets the TMZ bit in the TSCR.
The TMZ bit can be tested under program control
to perform timer functions whenever it goes high.
Bits D4 and D5 on TSCR2 (Timer 2) register are
not implemented.
A write to the TCR register will predominate over
the 8-bit counter decrement to 00h function, i.e. if a
write and a TCR register decrement to 00h occur
simultaneously, the write will take precedence,
and the TMZ bit is not set until the 8-bit counter
reaches 00h again. The values of the TCR and the
PSC registers can be read accurately at any time.
Timer Interrupt
When the counter register decrements to zero and
the software controlled ETI (enable timer interrupt)
bit is set to one then an interrupt request associat-
ed to interrupt vector #3 (for Timer 1), to interrupt
Figure 25. Timer Working Principle
7-BIT PRESCALER
BIT0
BIT1
BIT2
BIT6
BIT3
BIT4
BIT5
CLOCK
PS0
PS1
PS2
0
1
2
3
4
6
7
5
8-1 MULTIPLEXER
BIT2
BIT7
BIT0
BIT1
BIT3
BIT4
BIT5
BIT6
8-BIT COUNTER
VA00186
36/64
ST6373
TIMERS (Cont’d)
4.2.2 Timer Status Control Registers (TSCR)
Timers 1 and 2
written in TSCR1 by user’s software to enable the
operation of Timer 1 and 2.
Address: D4h (Timer 1), DCh (Timer 2) -
Read/Write
Table 11. Prescaler Division Factors
PS2
0
PS1
0
PS0
0
Divided By
Reset Value: 00h
1
2
7
0
0
0
1
0
1
0
4
TMZ
ETI
D5
D4
PSI
PS2
PS1
PS0
0
1
1
8
1
0
0
16
32
64
128
TMZ. Low-to-high transition indicates that the tim-
er count register has decremented to zero. This bit
must be cleared by user software before to start
with a new count.
1
0
1
1
1
0
1
1
1
ETI. This bit, when set, enables the timer interrupt
(vector #3 for Timer 1, vector #2 for Timer 2 re-
quest). If ETI=0 the timer interrupt is disabled. If
ETI= 1 and TMZ= 1 an interrupt request is gener-
ated.
4.2.3 Timer Counter Registers (TCR)
Timer Counter 1 and 2
Address: D3h (Timer Counter 1), DBh (Timer
Counter 2) - Read/Write
D5. This is the timers enable bit D5. It must be
cleared to 0 together with a set to 1 of bit D4 to en-
able Timer 1 and Timer 2 functions. It is not imple-
mented on registers TSCR2.
Reset Value: FFh
7
0
D4. This is the timers enable bit D4. This bit must
be set to 1 together with a clear to 0 of bit D5 to en-
able all Timers (Timer 1 and 2) functions. It is not
implemented on registers TSCR2.
D7
D6
D5
D4
D3
D2
D1
D0
Bit 7-0 = D7-D0: Counter Bits.
D5
0
D4
0
Timers
Disabled
Enabled
Reserved
4.2.4 Timer Prescaler Registers (PSCR)
Timer Prescalers 1 and 2
0
1
1
X
Address: D2h (Timer Prescaler 1), DAh (Timer
Prescaler 2) - Read/Write
PSI
Reset Value: 7Fh
. Used to initialize the prescaler and inhibit its
counting while PSI = 0 the prescaler is set to 7Fh
and the counter is inhibited. When PSI = 1 the
prescaler is enabled to count downwards. As long
as PSI= 0 both counter and prescaler are not run-
ning.
7
0
D7
D6
D5
D4
D3
D2
D1
D0
D7
: Always read as ”0”.
Bit 7 =
PS2-PS0
. These bits select the division ratio of the
prescaler register. (see Table 11)
Bit 6-0 = D6-D0: Prescaler Bits.
The TSCR1 and TSCR2 registers are cleared on
reset. The correct D4-D5 combination must be
37/64
ST6373
4.3 A/D CONVERTER (ADC)
The A/D converter peripheral is an 8-bit analog to
digital converter with analog inputs as alternate I/O
functions (the number of which is device depend-
ent), offering 8-bit resolution with a typical conver-
sion time of 70us (at an oscillator clock frequency
of 8MHz).
This action is also needed before entering WAIT
mode, since the A/D comparator is not automati-
cally disabled in WAIT mode.
During Reset, any conversion in progress is
stopped, the control register is reset to 40h and the
ADC interrupt is masked (EAI=0).
The ADC converts the input voltage by a process
of successive approximations, using a clock fre-
quency derived from the oscillator with a division
factor of twelve. With an oscillator clock frequency
less than 1.2MHz, conversion accuracy is de-
creased.
Figure 26. ADC Block Diagram
INTERRUPT
CLOCK
RESET
Selection of the input pin is done by configuring
the related I/O line as an analog input via the Op-
tion and Data registers (refer to I/O ports descrip-
tion for additional information). Only one I/O line
must be configured as an analog input at any time.
The user must avoid any situation in which more
than one I/O pin is selected as an analog input si-
multaneously, to avoid device malfunction.
Ain
CONVERTER
AV
AV
SS
DD
RESULT REGISTER
8
CONTROL REGISTER
8
The ADC uses two registers in the data space: the
ADC data conversion register, ADR, which stores
the conversion result, and the ADC control regis-
ter, ADCR, used to program the ADC functions.
CORE
CORE
CONTROL SIGNALS
VA00418
A conversion is started by writing a “1” to the Start
bit (STA) in the ADC control register. This auto-
matically clears (resets to “0”) the End Of Conver-
sion Bit (EOC). When a conversion is complete,
the EOC bit is automatically set to “1”, in order to
flag that conversion is complete and that the data
in the ADC data conversion register is valid. Each
conversion has to be separately initiated by writing
to the STA bit.
4.3.1 Application Notes
The A/D converter does not feature a sample and
hold circuit. The analog voltage to be measured
should therefore be stable during the entire con-
version cycle. Voltage variation should not exceed
±1/2 LSB for the optimum conversion accuracy. A
low pass filter may be used at the analog input
pins to reduce input voltage variation during con-
version.
The STA bit is continuously scanned so that, if the
user sets it to “1” while a previous conversion is in
progress, a new conversion is started before com-
pleting the previous one. The start bit (STA) is a
write only bit, any attempt to read it will show a log-
ical “0”.
When selected as an analog channel, the input pin
is internally connected to a capacitor C of typi-
ad
cally 12pF. For maximum accuracy, this capacitor
must be fully charged at the beginning of conver-
sion. In the worst case, conversion starts one in-
struction (6.5 µs) after the channel has been se-
lected. In worst case conditions, the impedance,
ASI, of the analog voltage source is calculated us-
ing the following formula:
The A/D converter features a maskable interrupt
associated with the end of conversion. This inter-
rupt is associated with interrupt vector #4 and oc-
curs when the EOC bit is set (i.e. when a conver-
sion is completed). The interrupt is masked using
the EAI (interrupt mask) bit in the control register.
The power consumption of the device can be re-
duced by turning off the ADC peripheral. This is
done by setting the PDS bit in the ADC control reg-
ister to “0”. If PDS=“1”, the A/D is powered and en-
abled for conversion. This bit must be set at least
one instruction before the beginning of the conver-
sion to allow stabilisation of the A/D converter.
6.5µs = 9 x C x ASI
ad
Ω
(capacitor charged to over 99.9%), i.e. 30 k in-
cluding a 50% guardband. ASI can be higher if C
ad
has been charged for a longer period by adding in-
structions before the start of conversion (adding
more than 26 CPU cycles is pointless).
38/64
ST6373
A/D CONVERTER (Cont’d)
Since the ADC is on the same chip as the micro-
processor, the user should not switch heavily load-
ed output signals during conversion, if high preci-
sion is required. Such switching will affect the sup-
ply voltages used as analog references.
the Timer interrupt, but in this case the Timer will
be working and the resulting noise could affect
conversion accuracy.
A/D Converter Control Register (ADCR)
Address: 0D1h
—
Read/Write
The accuracy of the conversion depends on the
Reset value: 40h
quality of the power supplies (V and V ). The
DD
SS
user must take special care to ensure a well regu-
lated reference voltage is present on the V and
7
0
DD
V
pins (power supply voltage variations must be
SS
EAI
EOC
STA
PDS
D3
D2
D1
D0
less than 5V/ms). This implies, in particular, that a
suitable decoupling capacitor is used at the V
DD
EAI
Bit 7 =
: Enable A/D Interrupt.If this bit is set to
pin.
“1” the A/D interrupt (vector #4) is enabled, when
EAI=0 the interrupt is disabled.
The converter resolution is given by:
EOC
Bit 6 =
: End of conversion. Read Only. This
V
DD – VSS
read only bit indicates when a conversion has
been completed. This bit is automatically reset to
“0” when the STA bit is written. If the user is using
the interrupt option then this bit can be used as an
interrupt pending bit. Data in the data conversion
register are valid only when this bit is set to “1”.
----------------------------
256
The Input voltage (Ain) which is to be converted
must be constant for 1µs before conversion and
remain constant during conversion.
Bit 5 = STA: Start of Conversion. Write Only. Writ-
ing a “1” to this bit will start a conversion on the se-
lected channel and automatically reset to “0” the
EOC bit. If the bit is set again when a conversion is
in progress, the present conversion is stopped and
a new one will take place. This bit is write only, any
attempt to read it will show a logical zero.
Conversion resolution can be improved if the pow-
er supply voltage (V ) to the microcontroller is
DD
lowered.
In order to optimise conversion resolution, the user
can configure the microcontroller in WAIT mode,
because this mode minimises noise disturbances
and power supply variations due to output switch-
ing. Nevertheless, the WAIT instruction should be
executed as soon as possible after the beginning
of the conversion, because execution of the WAIT
PDS: Power Down Selection. This bit acti-
Bit 4 =
vates the A/D converter if set to “1”. Writing a “0” to
this bit will put the ADC in power down mode (idle
mode).
D3-D0.
Not used
instruction may cause a small variation of the V
Bit 3-0 =
DD
voltage. The negative effect of this variation is min-
imized at the beginning of the conversion when the
converter is less sensitive, rather than at the end
of conversion, when the less significant bits are
determined.
A/D Converter Data Register (ADR)
Address: 0D0h Read only
—
Reset value: XXh
The best configuration, from an accuracy stand-
point, is WAIT mode with the Timer stopped. In-
deed, only the ADC peripheral and the oscillator
are then still working. The MCU must be woken up
from WAIT mode by the ADC interrupt at the end
of the conversion. It should be noted that waking
up the microcontroller could also be done using
7
0
D7
D6
D5
D4
D3
D2
D1
D0
Bit 7-0 = D7-D0: 8 Bit A/D Conversion Result.
39/64
ST6373
4.4 SYNC PROCESSOR
This Sync Processor is composed of five parts:
ment start by setting the VACQuisition bit (write 1).
As this bit is inverted in reading, it is read at 1 after
Reset. As soon as the operation starts it is read at
0. At the end of the measurement,after the second
VSYNC Falling edge, the VACQuisition bit is read
again at 1.
– The first one is a 12 bits Event Counter with
HSYNC (or HDRIV) as input especially design to
calculate the HSYNC (respectively HDRIV) Fre-
quency.
– The second one is a 12-bits Period Counter es-
pecially designed to calculate the VSYNC period
and therefore his Frequency.
Note: If FV < 31 Hz, VCOUNT = XFFFh = Max
If No V Sync, ACQ bit is not cleared
4.4.3 Polarity Detector
– The third one is a Polarity Detector for HSYNC
(or HDRIV) and VSYNC.
The VSYNC polarity detection is always active af-
ter reset so the software has only to read the Flag
(Bit 3 of SPCR) to determine the polarity. If the po-
larity of VSYNC changes, the Flag will switch after
a typical delay of 1.5 ms. The VSYNC polarity can
be read continuously.
– The fourth part is a HSYNC,VSYNC and CLAMP
outputs generator.
– The last part is a Video Blanking generator.
4.4.1 Event Counter
The Counting is directly controlled by the Timer 3.
The HSYNC/HDRIV polarity is returned in the Flag
(Bit 2 of SPCR). It is always running typically tog-
gles after one period of HSYNC/HDRIV when the
polarity changes.
When PSI bit of Timer 3 Status Control Register is
low the Event Counter is in Reset Mode. At this
time the Timer 3 counter can be loaded by the
count period (for example 10 ms).
The same delay has to be considered when
switching from HSYNC to HDRIV (Bit 0 of SPCR).
When PSI is set the Event Counter start simulta-
neously with the Timer.
Refer to the VSYNC an HSYNC input Timings.
When the timer count register has decremented to
zero the TMZ bit is set, an interrupt can be gener-
ated (if ETI bit is set) and the Event Counter stops.
4.4.4 Output Polarity Control
The selection of HSYNCO instead of PA2 (respec-
tively VSYNCO instead of PA3) is made with the
bit 7 (HVOS) of SPCR.
The result number read inside the EVENT COUN-
TER REGISTERS corresponds to the rising edge
number of the Event Counter Clock occurred be-
tween the start and the stop. This Counter Clock is
set to one when the Counter is in reset (PSI=0) or
just stopped (after stop). It is equal to HSYNC
(HDRIV) between start and stop.
HSYNCO and VSYNCO can take two different val-
ues according to the bit 6 (HVGEN) of SPCR:
- HSYNCI (respectively VSYNCI)
- HGEN: 62.5 KHz / Pulse width = 2us
(respectively VGEN: 61 Hz / Pulse width: 64 us).
[If there is no HSYNC (HDRIV) the result inside the
counter will be: XFFFh]
The control of the HSYNCO and VSYNCO polarity
is made with respectively the bit 4 (HOPC) and bit
5 (VOPC) of SPCR.
Example:
If the result is 5 the number of rising
edges is 6, the number of periods is: 4 < NP < 6).
The CLAMP output signal can be programmed af-
ter HSYNCO rising edge or HSYNCO falling edge
according to the bit 6 (CMCT) of ECCCR.
Calculation: If the timer count is 10 ms the calcula-
tion of the HSYNC Frequency could be simple:
Freq. = N/10 KHz where N is the Event Counter re-
sult, the error is + or - one LSB max, it means 100
Hz. Of course the accuracy can be increased with
a higher timing count; 20 ms will give + or - 50 Hz.
The CLAMP output polarity can be selected with
bit7 (COPC) of ECCCR.
The pulse width of CLMPO can have the values
250 ns, 500 ns or 1 ns according to the bits 5 and
4 (CMW1 and CMW0) of ECCCR.
4.4.2 Period Counter
The Vertical Period Counter is a 12-bits counter
with 8 us internal clock which measure by H/W the
duration between 2 VSYNC falling edges. Accura-
cy is 120+/-0.1 Hz. FVmin = 31 Hz. One measure-
Remark: when CMW1 = CMW0 = 0 PA4 is select-
ed.
40/64
ST6373
SYNC PROCESSOR (Cont’d)
4.4.5 Video Blanking Generator
Event Counter Register 1 (ECR1)
Address: DDh - Read-Only
Reset Value: FFh
This block involves HFLY, VFLY inputs and
VSYNCO as input. The falling edges of HFLY (re-
spectively VFLY) are detected on the flag bit 4
(HFLYF) of PCBCR (respectively bit 5 (VFLYF)).
HFLY flag (respectively VFLY flag) is reset by soft-
ware writing zero.
7
0
H7
H6
H5
H4
H3
H2
H1
H0
The selection between PA5 and BLANK output is
done with bit 6 (BOS) of PCBCR;
b7-b0: 8 LSB bits of counting result, Read Only,
FFh after Reset.
Event Counter2 And Clamp Control Register
(ECCCR)
SYNC Processor Control Register (SPCR)
Address: DFh - Read/Write
Reset Value: 00h
Address: DEh - Read/Write
Reset Value: 0Fh
7
0
7
0
HVOS HVGEN VOPC HOPC VPF HPF VACQ SHH
COPC CMCT CMW1 CMW0 H11 H10
H9
H8
b7:
HVOS: H/Vsync
Outputs
Selection
b7: COPC: Clamp Output Polarity Control
0=positive - 1=negative
0=PA2/PA3 as normal port A configuration,
1=HsyncO instead of PA2, VsyncO instead of
PA3, Write Only, 0 at Reset.
Write Only, 0 after Reset
CMCT:
Clamp Control
Remark
puts
b6:
: H/VSyncO are forced to push-pull out-
0=CLMPO after HsyncO rising edge,
1=CLMPO after HsyncO falling edge,
Write Only, 0 after Reset.
: HVGEN:
b6
H/Vsync GENeration.
0= H/VsyncO <- H/VsyncI or H/VsyncIN (accord-
ing to H/VOPC)
CMW1, CMW0:
b5-b4:
Clamp Pulse Width
1 = HsyncO <- HGEN: 62.5KHz, Pulse: 2µs (posi-
tive polarity); VsyncO <- VGEN: 61Hz, Pulse: 64µs
(positive polarity), Write Only, 0 at Reset.
Remark
: CLMPO is forced to push-pull outputs.
Write Only, 0 after Reset
b5: VOPC: Vsync Output Polarity Control
0=Vsynco <- VsyncI, 1= Vsynco <- VsyncIN, Write
Only, 0 after Reset.
Clamp Pulse
Width
CMW1
CMW0
0
0
1
1
0
1
0
1
Normal PA4
250 ns
HOPC:
b4:
Hsync Output Polarity Control
0=Hsynco <- HsyncI, 1=Hsynco<- HsyncIN, Write
Only, 0 after Reset.
500 ns
1000 ns
VPF: Vertical Polarity Flag
b3:
0=Positive, 1=Negative, Read Only, 0 after Reset.
HPF: Horizontal Polarity Flag
b3-b0: 4 MSB bits of Event Counting Result, Read
Only, XFh after Reset
b2:
0=Positive, 1=Negative, Read Only, 0 after Reset.
VACQ: Start Vsync Period Acquisition,
Period Counter Register 1 (PCR1)
Address: DFh - Read-Only
Reset Value: FFh
b1:
Read/Write, 0 after Reset (inverted in reading)
SHH: Selection of Hsync or Hdrive as input
b0:
7
0
0=Hsync, 1=Hdrive, Write Only, 0 after Reset.
V7
V6
V5
V4
V3
V2
V1
V0
b7-b0: 8 LSB bits of counting result, Read Only,
FFh after Reset.
41/64
ST6373
SYNC PROCESSOR (Cont’d)
Period Counter 2 And Blank Control Register
(PCBCR)
0=PA5, 1=BLANK, Write Only, 0 after Reset
VFLYF:
b5:
Vertical FLY-back Flag
Address: F1h - Read/Write
Reset Value: XFh
Set on falling edge of VFLY/PB6 input, Read and
Write, cleared by S/W (write of zero), undefined af-
ter Reset
7
0
HFLYF: Horizontal FLY-back Flag
b4:
NU
BOS
VFLY HFLY V11
V10
V9
V8
Set on falling edge of HFLY/PB5 Input, Read and
Write, cleared by S/W (write of zero), undefined af-
ter Reset
Not Used
b7:
b6:
b3 to b0: 4 MSB bits of period counting result,
Read Only, Fh After Reset
BOS:
Blank Output Selection
Figure 27. SYNC Processor Block Diagram
VSYNCEN
Latch
Polarity
Detector
VPF
V 12 bit TIMER
HVGEN
Pulse
(VACQ)
Detect
VSYNCI
VSYNCO
POLARITY
VOPC
0
1
VSYNCI
VSYNCO
HVOS
To
Blk
H Polarity Detector
HPF
VSYNC+
Generator
Sync Generator
H/W Block
61 Hz,64 µs
HSYNC+
H 12 bit Event Counter
(timer 3)
Generator
62.5 kHz, 2 µs
HOPC
SHH
1
0
HVOS
0
1
HSYNCI
HDRIVE
HSYNCO
HSYNCI
HSYNCO
POLARITY
CMW0:1
CLMPO
BACK PORCH
CLAMP
POLARITY
HVGEN
CLAMP
GENERATOR
COPC
CMCT
Blank Out Generation
To Edge detector (HFLYF)
PB5/HFLY
To Edge detector (VFLYF)
R
PA5/BLK0
PB6/VFLY
S
BLKEN
VR02089A
HFLY, VFLY, VSYNCO signals should have positive polarity
PA3/VSYNCO
42/64
ST6373
SYNC PROCESSOR (Cont’d)
Figure 28. Synch Processor Timing
HSYNCO:
Maximum delay is 250ns
CLMPO:
Programmable clamping width (250ns ; 500ns ; 1 µs)
8.25 µs Min
HSYNC
Input Timing
8.125 µs Max
1.0 µs Min
10 µs
(100kHz)
33.33 µs
(30kHz)
1536 µs Min
VSYNC
Input Timing
1024 µs Max
32 µs Min
8.33ms
(120Hz)
25ms
(40Hz)
VR02090A
43/64
ST6373
4.5 14-BIT PWM D/A CONVERTER
Table 12. Fine Tuning Pulse Addition
The PWM D/A CONVERTER (HDA) is composed
of a 14-bit counter that allows the conversion of
the digital content in an analog voltage, available
at the HDA output pin, by using Pulse Width Mod-
ification (PWM), and Bit Rate Multiplier (BRM)
techniques.
N° of pulses added at the
Fine Tuning
(7 LSB)
following cycles
(0... 127)
0000001
0000010
0000100
0001000
0010000
0100000
1000000
64
The tuning word consists of a 14-bit word con-
tained in the registers HDADATA1 (location EEh)
and HDADATA2 (location EFh). Coarse tuning
(PWM) is performed using the seven MSBs, while
fine tuning (BRM) is performed using the data in
the seven LSBits. With all zeros loaded the output
is zero; as the tuning voltage increases from all ze-
ros, the number of pulses in one period increase to
128 with all pulses being the same width. For val-
ues larger than 128, the PWM takes over and the
number of pulses in one period remains constant
at 128, but the width changes. At the other end of
the scale, when almost all ones are loaded, the
pulses will start to link together and the number of
pulses will decrease. When all ones are loaded,
the output will be almost 100% high but will have a
low pulse (1/16384 of the high pulse).
32, 96
16, 48, 80, 112
8, 24, ....104, 120
4, 12, ....116, 124
2, 6, .....122, 126
1, 3, .....125, 127
4.5.2 HDA Tuning Cell Registers
HDA Data Register 1 (HDAR1)
Address: EEh - Write only
Reset Value: XXh
7
0
4.5.1 Output Details
HDA7 HDA6 HDA5 HDA4 HDA3 HDA2 HDA1 HDA0
Inside the on-chip D/A CONVERTER are included
the register latches, a reference counter, PWM
and BRM control circuitry. In the ST6373 the clock
for the 14-bit reference counter is 2MHz derived
from the 8MHz system clock. From the circuit point
of view, the seven most significant bits control the
coarse tuning, while the seven least significant bits
control the fine tuning. From the application and
software point of view, the 14 bits can be consid-
ered as one binary number.
D7-D0
. These are the 8 least significant HDA data
bits. Bit 0 is the LSB. This register is undefined on
reset.
HDA Data Register 2 (HDAR2)
Address: EFh - Write only
Reset Value: XXh
As already mentioned the coarse tuning consists
of a PWM signal with 128 steps; we can consider
the fine tuning to cover 128 coarse tuning cycles.
The addition of pulses is described in the following
Table.
7
0
-
-
HDA13 HDA12 HDA11 HDA10 HDA9 HDA8
D7-D6
D5-D0
. These bits are not used.
The HDA output pin has a standard drive push-pull
output configuration.
. These are the 6 most significant HDA data
bits. Bit 5 is the MSB. This register is undefined on
reset.
44/64
ST6373
4.6 7-BIT PWM D/A CONVERTERS
D7-D1
DABS
The D/A peripheral features nine PWM D/A out-
puts (31.25kHz repetition, DA0-DA8) with seven
bit resolution.
= Not Used.
. D/A BANK Selection, This bit is used to se-
lect one of the two banks of 4 bytes located at ad-
dresses E0h to E3h. Read/Write, 0 after Reset.
Each D/A converter is composed by the following
main blocks:
0 = Select Bank 0
1 = Select Bank 1
- pre-divider
- 7-bit counter
Bank 0 is used for the DA0 to DA3 Outputs. Bank
1 is used for the DA4 to DA7 Outputs.
- data latches and compare circuits
The pre-divider uses the clock input frequency
(8MHz typical) and its output clocks the 7-bit free-
running up-counter. The data latched in the DTOA
Data/Control Registers control the nine D/A out-
puts (DA0,1,2,3,4,6,7 and 8). When the values in
the counter and data latch are equal, the relevant
output is set. The output is reset on the counter
overflow. When a DTOA output is disabled (bit 7 of
corresponding Control Register is low) the output
is forced to zero whatever the value of bits 0 to 6.
When enabled (bit 7 = 1) the output depends on
bits 0 to 6. If all these bits are equal to zero the rel-
evant output is an high logic level. All 1’s corre-
spond to a pulse with a 1/128 duty cycle and al-
most 100% zero level.
Table 13. Channel Address Selection
Channel
Bank Select
Address
Selected
0
0
0
0
1
1
1
1
X
E0h
E1h
E2h
E3h
EOh
E1h
E2h
E3h
E4h
DA0
DA1
DA2
DA3
DA4
DA5
DA6
DA7
DA8
The frequency of the PWM DTOA outputs is 31.25
KHz. The duty cycle of the DTOA outputs change
in steps of 250ns.
D/A Data Control Registers (DDCR)
Address: E0h to E3h, E4h - Write only
Reset Value: 0XXXXXXXXb
The repetition frequency is related to the 8MHz
clock frequency. Use of a different oscillator fre-
quency will result in a different repetition frequen-
cy. All D/A outputs are Push-pull with standard
current drive capability.
7
0
EN DAxC6 DAxC5 DAxC4 DAxC3 DAxC2 DAxC1 DAxC0
DTOA channels 0 to 7 are held in a bank of two
blocks of four registers selected according to the
status of DABS, bit 0 of the D/A Bank Register at
address E7h. DTOA channel 8 is directly ad-
dressed at address E4h without the need of the
D/A BANK REGISTER.
ENx
.Enable bit, Write Only, 0 after Reset.
0 = Disable Channel x
1 = Enable Channel x
DAxC6 to DAxC0: Data Control bits Channel x,
Write Only, Undefined after Reset.
D/A BANK Register (DABR)
Address: E7h - Read/Write
Reset Value: 00h
4.6.1 Digital Outputs
The nine 7 bits PWM outputs can also be used as
simple outputs.
7
0
DDC Bit 7
DDCR bits 0 to 6
don’t care
Output State
0
1
0
1
D7
D6
D5
D4
D3
D2
D1
DABS
all zero
45/64
ST6373
4.7 SERIAL PERIPHERAL INTERFACES
The ST6373 features two on-chip Serial Peripher-
al Interfaces (SPIs) for synchronous communica-
tion with other local control/interface devices. The
two SPIs are similar in basic function, however the
first contains additional logic and EEPROM mem-
ory to manage the VESA DDC data protocol
(DDC1, DDC2B and DDC2AB) transmission and
reception. Both SPIs can manage Standard shift
The maximum external clock and VSYNC clock
speed is 25kHz.
2
The I C Data Hold Time is 250ns minimum.
2
As the I C SPI is derived from the DDC SPI, the
DDC SPI is shown, with the functional differences
shown.
For the DDC1 and DDC2B an additional 128 bytes
of dedicated EEPROM can be used to load the
SPI with predefined data automatically without any
CPU time consumption (see Block Diagram).
2
modes (in addition to I C mode), and Master/Slave
2
I C Modes.
The serial modes of the SPI are summarised in the
following table:
The Address Generator contains a 7-bits Auto-
Counter Register which allows the CPU to set a
EEPROM Start Address from 00h to 7Fh.
Table 14. SPI Modes
Slave Standard shift mode, with external
DDC SPI only
In DDC2B the Hardware Slave Address A0/A1h
can be enabled in parallel with the Programmed
clock on EXTCLK
2
I C Slave Address.
Master Standard shift mode with internal
Both SPIs
clock
DDC1 mode with VSYNC as clock
2
DDC SPI only
Both SPIs
Multimaster/Slave
mode
I C
Figure 29. DDC SPI Block Diagram
ADDRESS
GENERATOR
1
0
VSYNC
AUTO
DDC CONTROL
SCLD
ADDRESS
DDC EEPROM
DATA
SHIFT
REGISTER
SDAD
1
0
1
0
VR02034
46/64
ST6373
SERIAL PERIPHERAL INTERFACE (Cont’d)
4.7.1 SPI Modes
2
the Read/Write (R/W) bit for I C-bus) is shifted out
when triggered with a preceding Start Condition.
DDC1 Mode
. In this mode, the eight bits of the
An Interrupt can be generated at the end of trans-
mission or this can be detected by polling. Arbitra-
tion is managed by comparing the data on the
SDAD line with the corresponding data bit of the
shift register and an error is flagged if they are dif-
ferent. If the addressed Slave stretches the low
period of the SCLD line, the Master is forced into a
wait state.In Slave Mode, the data register is load-
ed with its own slave address, and the DDC SPI
waits for detection of a START Condition. The ad-
dress received is compared to that set for the
slave, and if the address is correct, an acknowl-
edge is sent and an interrupt can be generated,
the SCLD line is held low to allow the software to
prepare for the incoming data. If the request in the
R/W bit is set (0) the external master wants to write
to the Slave, if reset, a data value is to be sent.
This is managed by the user software.
data register are shifted out of the register, most
significant bit first, clocked on the rising edge of
the VSYNC input. During the ninth period, the SDA
line remains high or low depending on the ACKC
bit. In Auto mode (AUTO=1), the 128 bytes of the
DDC EEPROM are sent in sequence until the
SCLD input goes low to indicate a DDC Acknowl-
edgment, an interrupt is generated and the trans-
fer is stopped. The data direction is from the MCU,
typically as data from the Monitor to the Host.
Slave Standard Shift Mode
. The operation of this
mode is the same as the DDC1 Mode except that
the clock used is taken from the external clock in-
put (EXTCLK on PC3).
Master Standard Shift Mode
. This mode corre-
sponds to the Standard Shift Protocol. Data in the
shift register is shifted out of the SDAD line at the
internal SPI clock speed after the transmission is
triggered. The synchronous clock for the data
transmission is output on the SCLD pin. An inter-
rupt can be generated at the end of transmission.
DDC2B Mode
. The DDC2B mode follows the
DDC2 mode until a read command is received.
The SPI can then be programmed in AUTO mode
to send automatically the 128 bytes of the EEP-
ROM until the end of the communication.
2
DDC2 or I C Mode. This mode is used in conjunc-
2
tion with software to implement the I C transmis-
2
I C SPI
sion protocol. In Master Mode, data written into the
data register (typically Address of the Slave and
2
The I C SPI manages only the Standard Shift
2
Register Mode and the I C-bus Mode of the DDC
SPI.
Figure 30. DDC1 Mode AUTO Not Set
1
2
3
4
5
6
7
8
9
10
VSYNC
SDA
D7
D6
D5
D4
D3
D2
D1
D0
ACK
START
VR02035
47/64
ST6373
SERIAL PERIPHERAL INTERFACE (Cont’d)
Figure 31. I CMaster Transmit to SlaveReceiver
(Write Mode)
ACKNOWLEDGE
FROM SLAVE
ACKNOWLEDGE
FROM SLAVE
ACKNOWLEDGE
FROM SLAVE
MSB
S
SLAVE ADDRESS
O
A
WORD ADDRESS
A
DATA
A
P
START
R/W
STOP
Figure 32. I C Master Reads Slave Immediately After First Byte (Read Mode)
ACKNOWLEDGE
FROM SLAVE
ACKNOWLEDGE
FROM MASTER
NO ACKNOWLEDGE
FROM MASTER
MSB
A
MSB
S
SLAVE ADDRESS
1
A
DATA
1
P
DATA
START
R/W
n BYTES
STOP
Figure 33. I C Master Reads After Setting Slave Register Address (Write Address, Read Data)
ACKNOWLEDGE
FROM SLAVE
ACKNOWLEDGE
FROM SLAVE
S
SLAVE ADDRESS
0
A
X
WORD ADDRESS
A
P
START
R/W
STOP
ACKNOWLEDGE
FROM SLAVE
ACKNOWLEDGE
FROM MASTER
NO ACKNOWLEDGE
FROM MASTER
MSB
MSB
S
SLAVE ADDRESS
1
A
A
DATA
1
P
DATA
START
R/W
STOP
48/64
ST6373
SERIAL PERIPHERAL INTERFACE (Cont’d)
SPI Control Register 1 (SCR1)
DDC
MS1,MS0. Mode Selection (MS1:MS0).
DDC1 mode with VSYNC as clock [DDC SPI
Only]
00
Address: EBh - Read/Write
Reset Value: 00h
01
10
11
Slave Standard Shift [DDC SPI Only]
Master Standard Shift
2
I C
Multimaster/Slave
BUS for DDC2
I C
Address: E5h - Read/Write
Reset Value: 00h
2
MS1 is not used forI C SPI
7
0
Note that NO bit operation instructions are possi-
ble on this register. (SET and RES)
ENA
MSS ENIT ACKC STAG STOG MS1
MS0
SPI Control Register 2 (SCR2)
DDC
ENA
. SPI Enable bit.0 - Disable SPI1 - Enable SPI
Write Only, 0 after Reset.Remark: When the SPI is
disabled, the pins PC0, PC1 and PC3 can be used
as normal I/O pins.
Address: ECh - Read/Write
Reset Value: 00h
I C
MSS
. MASTER/SLAVE Selection (MSS).0 - Se-
lect SLAVE operation1 - Select MASTER opera-
tion
Address: E6h - Read/Write
Reset Value: 00h
ENIT
. Enable SPI Interrupt. The interrupt occurs
on a falling edge of SBOR. In DDC1 Automatic
and in DDC2B Automatic there is an interrupt only
if AUTO has been reset (refer to bit AUTO).
7
0
AUTO INTF SCDF BBF
TRS VSDAF NADF SBOR
2
In I C Slave mode the interrupt occurs at the end
of the address reception only if this address is
matched.
AUTO. Automatic Operation mode (AUTO). This
bit is automatically reset
0 = Disable SPI Interrupt
1 = Enable SPI Interrupt
:- in DDC1 when SCL goes low
- in DDC2B when no acknowledge is received or
when the data on the SDA line is different from
the one being sent (For example parasitical
STOP or START).
ACKC
. Acknowledge Control bit (ACKC). This bit
2
is used in I C reception to control whether not to
send the acknowledge before a RESTART in
MASTER mode, or not to answer if too busy in
SLAVE mode.0 = Enable1 = Disable
Write Only.
2
Not used for I C SPI
Write Only.
INTF. Interrupt Flag (INTF). This flag is set when
an interrupt occurs if enabled. It must be reset be-
fore leaving the interrupt routine.
This bit is also used in DDC1 mode to change the
polarity of the Acknowledge bit
.0 = Set Acknowledge to high
1 = Set Acknowledge to low
Read and reset
SCDF
. START Condition Detection Flag. This flag
STAG
. START Condition Generation for MASTER
is set on a Start condition detection. It is also set in
DDC1 mode on a high to low transition of SCL. It
must be reset before leaving the interrupt routine.
2
2
I C. [I C BUS ONLY]0 = No Generation1 = Gener-
ation Start condition
Write Only.
Read and reset.
2
STOG. STOP Condition Generation for MASTER
BBF
. BUSY BUS Flag. (I C BUS ONLY) Set on a
2
2
I C. [I C BUS ONLY]0 = No Generation1 = Gener-
ation Stop condition
first START Condition and Reset on the STOP
Condition.
Write Only.
Read and reset.
49/64
ST6373
SERIAL PERIPHERAL INTERFACE (Cont’d)
TRS. Transmission/Reception Selection.
0 = Select Reception operation
1 = Select Transmission operation
Write Only.
SD7-SD0. Data bits, R/W, Undefined after Reset.
This Serial Data Register is composed of one Buff-
er Register and one Data Shift Register. When
AUTO = 1, the Shift Register is linked to the 128
byte DDC EEPROM dedicated to DDC1 and
DDC2B. The data will then automatically be sent
without CPU operation. The 128 bytes DDC EEP-
ROM can be addressed (programmed or read) by
the software only when bit AUTO = 0. Software
can address the buffer and not the Shift Register.
This bit is also used in reading as a STOP Condi-
tion Detection Flag.
Read Only.
VSDAF
. Verification of SDA line Flag. This bit is
set as soon as the data on SDA line is different to
the data inside SSDR, mainly in transmission but
also during the slave address reception when the
- The data transfer from the Shift Register to the
Buffer is always done at the end of a normal recep-
tion (TRS = 0) before the reset of SBOR. The buff-
er should not be read by the software during the
data transfer.
2
SLAVE mode is selected. [I C BUS ONLY]
0 = no difference detected
1 = Difference found on SDA
- With the DDC SPI, the loading of the Shift Regis-
ter is done in two different ways depending on the
AUTO bit:
Read Only.
2
NADF
. No Acknowledge Detection Flag. [IC BUS
When AUTO = 0 the transfer is done from the Buff-
er to the Shift Register on the setting of SBOR (or
ONLY]
2
0 = Detection Acknowledge
1 = No Detection of Acknowledge
Read Only.
also in I C SLAVE mode, on a Start Condition De-
tection).
When AUTO = 1, the transfer is done from the
DDC EEPROM to the Shift Register at the end of
each byte transmission. (The first byte is loaded
when SBOR is set simultaneously with AUTO)
SBOR
. SPI Byte Operation (Transmission or Re-
2
ception). This bit is set to start an operation; in IC
SLAVE mode it is automatically set when a Start
Condition is detected.
Note:
When SBOR = 1, the loading of the Buffer does
not affect the Shift Register.
0 = No Operation
1 = Operation Start
Read and Set.
Auto-counter Register (ACR)
Address: F2h - Read/Write
Reset Value: 00h
Note that NO bit operation instructions are possi-
ble on this register.
SPI Serial Data Register (SSDR)
DDC
7
0
-
D6
D5
D4
D3
D2
D1
D0
Address: CCh - Read/Write
Reset Value: XXh
I C
b7: Not used
b6 to b0: 7 bits Auto-Counter, Read/Write, 00h af-
ter Reset.
Address: CBh - Read/Write
Reset Value: XXh
Through these 7 bits the DDC1/DDC2B Address
Generator can be set at any EEPROM Start Ad-
dress from 00h to 7Fh. The content of the counter
can be read at any time during the DDC1 or
DDC2B Automatic Mode.
7
0
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
50/64
ST6373
SERIAL PERIPHERAL INTERFACE (Cont’d)
SCL Latch And Ddc2b Address Control Regis-
ter (SLACR)
b0: SCLEDGE: SCL EDGE selection bit.The SCL
input latch is activated on either the positive or
negative edge of SCL line: if SCLEDGE is high the
latch will be triggered on the rising edge of SCL; if
this bit is low the latch will be triggered on the fall-
ing edge (Write Only, 0 after Reset).
Address: F3h - Read/Write
Reset Value: 40h
7
0
Remark: In DDC1, it is not necessary to use the
SCL latch interrupt because the DDC1 SCL Falling
edge interrupt can be activated (see DDC1 mode).
SCL
SCL
SCL
-
-
-
-
HSAE
FLAG ITEN EDGE
b7 to b4: Not used
b3: HSAE: Hardware Slave Address Enable. This
bit allows the Slave I2C to check, after a Start Con-
dition Detection, both the Address A0/A1h for
DDC2B and the Programmed Address for the
switch to DDC2AB.
4.8 MIRROR REGISTER
This is an 8-bits Register at address D9h. It is
cleared on Reset. After writing, the read value is
the reversed byte:
Bit0 -> Bit7, Bit1 -> Bit6, Bit2 -> Bit5, Bit3 -> Bit4,
Bit4 -> Bit3, Bit5 -> Bit2, Bit6 -> Bit1, Bit7 -> Bit0
Note
always valid.
that software address contained in SSDR is
0=Disable, 1=Enable, Write only, 1 after Reset
4.9 XOR REGISTER
SCLFLAG:
b2:
SCL FLAG bit. This bit is set on
SCL rising or falling edge according to the polarity
bit SCLEDGE. This flag can be reset by writing a 1
in SCLFLAG bit (Read and Reset, undefined after
reset).
This is a 8-bit Register at address F4h. It is cleared
on Reset. After writing, the new content value is
the previous content ”XORed” with the written val-
ue.
b1: SCLITEN: SCL INterrupt ENable bit.If this bit
is set an interrupt on vector # 3 is generated when
the SCL flag is set (Write Only, 0 after Reset).
To reset this register the user must read its con-
tents and rewrite it (A XOR A = 0).
51/64
ST6373
5 SOFTWARE
5.1 ST6 ARCHITECTURE
The ST6 software has been designed to fully use
the hardware in the most efficient way possible
while keeping byte usage to a minimum; in short,
to provide byte efficient programming capability.
The ST6 core has the ability to set or clear any
register or RAM location bit of the Data space with
a single instruction. Furthermore, the program
may branch to a selected address depending on
the status of any bit of the Data space. The carry
bit is stored with the value of the bit when the SET
or RES instruction is processed.
bits of the opcode with the byte following the op-
code. The instructions (JP, CALL) which use the
extended addressing mode are able to branch to
any address of the 4K bytes Program space.
An extended addressing mode instruction is two-
byte long.
Program Counter Relative
. The relative address-
ing mode is only used in conditional branch in-
structions. The instruction is used to perform a test
and, if the condition is true, a branch with a span of
-15 to +16 locations around the address of the rel-
ative instruction. If the condition is not true, the in-
struction which follows the relative instruction is
executed. The relative addressing mode instruc-
tion is one-byte long. The opcode is obtained in
adding the three most significant bits which char-
acterize the kind of the test, one bit which deter-
mines whether the branch is a forward (when it is
0) or backward (when it is 1) branch and the four
less significant bits which give the span of the
branch (0h to 0Fh) which must be added or sub-
tracted to the address of the relative instruction to
obtain the address of the branch.
5.2 ADDRESSING MODES
The ST6 core offers nine addressing modes,
which are described in the following paragraphs.
Three different address spaces are available: Pro-
gram space, Data space, and Stack space. Pro-
gram space contains the instructions which are to
be executed, plus the data for immediate mode in-
structions. Data space contains the Accumulator,
the X,Y,V and W registers, peripheral and In-
put/Output registers, the RAM locations and Data
ROM locations (for storage of tables and con-
stants). Stack space contains six 12-bit RAM cells
used to stack the return addresses for subroutines
and interrupts.
Bit Direct. In the bit direct addressing mode, the
bit to be set or cleared is part of the opcode, and
the byte following the opcode points to the ad-
dress of the byte in which the specified bit must be
set or cleared. Thus, any bit in the 256 locations of
Data space memory can be set or cleared.
Immediate
. In the immediate addressing mode,
the operand of the instruction follows the opcode
location. As the operand is a ROM byte, the imme-
diate addressing mode is used to access con-
stants which do not change during program execu-
tion (e.g., a constant used to initialize a loop coun-
ter).
Bit Test & Branch. The bit test and branch ad-
dressing mode is a combination of direct address-
ing and relative addressing. The bit test and
branch instruction is three-byte long. The bit iden-
tification and the tested condition are included in
the opcode byte. The address of the byte to be
tested follows immediately the opcode in the Pro-
gram space. The third byte is the jump displace-
ment, which is in the range of -126 to +129. This
displacement can be determined using a label,
which is converted by the assembler.
Direct. In the direct addressing mode, the address
of the byte which is processed by the instruction is
stored in the location which follows the opcode. Di-
rect addressing allows the user to directly address
the 256 bytes in Data Space memory with a single
two-byte instruction.
Short Direct
. The core can address the four RAM
Indirect. In the indirect addressing mode, the byte
processed by the register-indirect instruction is at
the address pointed by the content of one of the in-
direct registers, X or Y (80h,81h). The indirect reg-
ister is selected by the bit 4 of the opcode. A regis-
ter indirect instruction is one byte long.
registers X,Y,V,W (locations 80h, 81h, 82h, 83h) in
the short-direct addressing mode. In this case, the
instruction is only one byte and the selection of the
location to be processed is contained in the op-
code. Short direct addressing is a subset of the di-
rect addressing mode. (Note that 80h and 81h are
also indirect registers).
Inherent
. In the inherent addressing mode, all the
information necessary to execute the instruction is
contained in the opcode. These instructions are
one byte long.
Extended
. In the extended addressing mode, the
12-bit address needed to define the instruction is
obtained by concatenating the four less significant
52/64
ST6373
5.3 INSTRUCTION SET
Load & Store
The ST6 core offers a set of 40 basic instructions
which, when combined with nine addressing
modes, yield 244 usable opcodes. They can be di-
vided into six different types: load/store, arithme-
tic/logic, conditional branch, control instructions,
jump/call, and bit manipulation. The following par-
agraphs describe the different types.
. These instructions use one, two or
three bytes in relation with the addressing mode.
One operand is the Accumulator for LOAD and the
other operand is obtained from data memory using
one of the addressing modes.
For Load Immediate one operand can be any of
the 256 data space bytes while the other is always
immediate data.
All the instructions belonging to a given type are
presented in individual tables.
Table 15. Load & Store Instructions
Flags
Instruction
LD A, X
Addressing Mode
Short Direct
Bytes
Cycles
Z
C
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
1
1
1
1
1
1
1
1
2
2
1
1
1
1
2
3
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
∆
LD A, Y
LD A, V
LD A, W
LD X, A
LD Y, A
LD V, A
LD W, A
LD A, rr
LD rr, A
LD A, (X)
LD A, (Y)
LD (X), A
LD (Y), A
LDI A, #N
LDI rr, #N
Short Direct
Short Direct
Short Direct
Short Direct
Short Direct
Short Direct
Short Direct
Direct
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
Direct
Indirect
Indirect
Indirect
Indirect
∆
Immediate
Immediate
∆
*
Notes:
X,Y. Indirect Register Pointers, V & W Short Direct Registers
#. Immediate data (stored in ROM memory)
rr. Data space register
∆. Affected
*.
Not Affected
53/64
ST6373
INSTRUCTION SET(Cont’d)
Arithmetic and Logic. These instructions are
used to perform the arithmetic calculations and
logic operations. In AND, ADD, CP, SUB instruc-
tions one operand is always the accumulator while
the other can be either a data space memory con-
tent or an immediate value in relation with the ad-
dressing mode. In CLR, DEC, INC instructions the
operand can be any of the 256 data space ad-
dresses. In COM, RLC, SLA the operand is always
the accumulator.
Table 16. Arithmetic & Logic Instructions
Flags
Instruction
ADD A, (X)
Addressing Mode
Indirect
Bytes
Cycles
Z
∆
∆
∆
∆
∆
∆
∆
∆
∆
*
C
∆
∆
∆
∆
∆
∆
∆
∆
∆
*
1
1
2
2
1
1
2
2
2
3
1
1
1
2
2
1
1
1
1
2
2
1
1
1
1
1
1
2
2
1
1
1
2
1
1
2
2
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
ADD A, (Y)
ADD A, rr
ADDI A, #N
AND A, (X)
AND A, (Y)
AND A, rr
ANDI A, #N
CLR A
Indirect
Direct
Immediate
Indirect
Indirect
Direct
Immediate
Short Direct
Direct
CLR r
COM A
Inherent
Indirect
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
*
CP A, (X)
CP A, (Y)
CP A, rr
CPI A, #N
DEC X
Indirect
Direct
Immediate
Short Direct
Short Direct
Short Direct
Short Direct
Direct
DEC Y
*
DEC V
*
DEC W
*
DEC A
*
DEC rr
Direct
*
DEC (X)
DEC (Y)
INC X
Indirect
*
Indirect
*
Short Direct
Short Direct
Short Direct
Short Direct
Direct
*
INC Y
*
INC V
*
INC W
*
INC A
*
INC rr
Direct
*
INC (X)
Indirect
*
INC (Y)
Indirect
*
RLC A
Inherent
Inherent
Indirect
∆
∆
∆
∆
∆
∆
SLA A
SUB A, (X)
SUB A, (Y)
SUB A, rr
SUBI A, #N
Indirect
Direct
Immediate
Notes:
X,Y.Indirect Register Pointers, V & W Short Direct RegistersD. Affected
#. Immediate data (stored in ROM memory)*. Not Affected
rr. Data space register
54/64
ST6373
INSTRUCTION SET(Cont’d)
Conditional Branch. The branch instructions
achieve a branch in the program when the select-
ed condition is met.
Control Instructions. The control instructions
control the MCU operations during program exe-
cution.
Bit Manipulation Instructions. These instruc-
tions can handle any bit in data space memory.
One group either sets or clears. The other group
(see Conditional Branch) performs the bit test
branch operations.
Jump and Call. These two instructions are used
to perform long (12-bit) jumps or subroutines call
inside the whole program space.
Table 17. Conditional Branch Instructions
Flags
Instruction
Branch If
Bytes
Cycles
Z
*
*
*
*
*
*
C
*
JRC e
C = 1
1
1
1
1
3
3
2
2
2
2
5
5
JRNC e
C = 0
Z = 1
*
JRZ e
*
JRNZ e
Z = 0
*
JRR b, rr, ee
JRS b, rr, ee
Bit = 0
Bit = 1
D
D
Notes
:
b.
e.
3-bit address
rr. Data space register
∆. Affected
5 bit signed displacement in the range -15 to +16<F128M>
ee. 8 bit signed displacement in the range -126 to +129
*. Not Affected
Table 18. Bit Manipulation Instructions
Flags
Instruction
Addressing Mode
Bytes
Cycles
Z
*
C
*
SET b,rr
Bit Direct
Bit Direct
2
2
4
4
RES b,rr
*
*
Notes:
b.
3-bit address;
*. Not<M> Affected
rr. Data space register;
Table 19. Control Instructions
Flags
Instruction
Addressing Mode
Bytes
Cycles
Z
*
C
*
NOP
Inherent
Inherent
Inherent
Inherent
Inherent
1
1
1
1
1
2
2
2
2
2
RET
*
*
RETI
∆
*
∆
*
STOP (1)
WAIT
*
*
Notes:
1.
This instruction is deactivated and a WAIT is automatically executed instead of a STOP if the watchdog function is selected.
∆. Affected
*.
Not Affected
Table 20. Jump & Call Instructions
Instruction
Flags
Addressing Mode
Bytes
Cycles
Z
*
C
*
CALL abc
JP abc
Extended
Extended
2
2
4
4
*
*
Notes:
abc. 12-bit address;
*.
Not Affected
55/64
ST6373
Opcode Map Summary.The following table contains an opcode map for the instructions used by the ST6
LOW
LOW
0
0000
1
0001
2
0010
3
0011
4
0100
5
6
7
0101
0110
0111
HI
HI
2
JRNZ 4
CALL 2
abc
ext 1
CALL 2
abc
ext 1
CALL 2
abc
ext 1
CALL 2
abc
ext 1
CALL 2
abc
ext 1
CALL 2
abc
ext 1
CALL 2
abc
ext 1
CALL 2
abc
ext 1
CALL 2
abc
ext 1
CALL 2
abc
ext 1
CALL 2
abc
ext 1
CALL 2
abc
ext 1
CALL 2
abc
ext 1
CALL 2
abc
ext 1
CALL 2
abc
ext 1
CALL 2
abc
JRNC 5
e
pcr 3
JRNC 5
e
pcr 3
JRNC 5
e
pcr 3
JRNC 5
e
pcr 3
JRNC 5
e
pcr 3
JRNC 5
e
pcr 3
JRNC 5
e
pcr 3
JRNC 5
e
pcr 3
JRNC 5
e
pcr 3
JRNC 5
e
pcr 3
JRNC 5
e
pcr 3
JRNC 5
e
pcr 3
JRNC 5
e
pcr 3
JRNC 5
e
pcr 3
JRNC 5
e
pcr 3
JRNC 5
e
JRR 2
b0,rr,ee
bt 1
JRS 2
b0,rr,ee
bt 1
JRR 2
b4,rr,ee
JRZ
2
JRC 4
LD
0
0
e
e
e
e
e
e
e
e
e
e
e
e
#
x
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
a,(x)
a,nn
0000
0000
1
2
pcr 2
JRNZ 4
pcr
JRZ 4
1
prc 1
JRC 4
ind
LDI
INC 2
1
0001
1
0001
1
2
pcr 2
JRNZ 4
pcr 1
JRZ
sd 1
2
prc 2
JRC 4
imm
CP
2
0010
2
#
a,(x)
0010
1
2
pcr 2
JRNZ 4
bt 1
JRS 2
pcr
JRZ 4
1
prc 1
JRC 4
ind
CPI
LD 2
3
0011
3
b4,rr,ee
e
bt 1
a,x
#
a,nn
0011
1
2
pcr 2
JRNZ 4
pcr 1
JRZ
sd 1
2
prc 2
JRC 4
imm
ADD
a,(x)
JRR 2
b2,rr,ee
bt 1
JRS 2
b2,rr,ee
bt 1
JRR 2
b6,rr,ee
bt 1
JRS 2
b6,rr,ee
bt 1
JRR 2
b1,rr,ee
bt 1
JRS 2
b1,rr,ee
bt 1
JRR 2
b5,rr,ee
bt 1
JRS 2
b5,rr,ee
bt 1
JRR 2
b3,rr,ee
bt 1
JRS 2
b3,rr,ee
bt 1
JRR 2
b7,rr,ee
bt 1
JRS 2
b7,rr,ee
4
0100
4
e
e
e
e
e
e
e
e
e
e
e
e
0100
1
2
pcr 2
JRNZ 4
pcr
JRZ 4
1
prc 1
JRC 4
ind
ADDI
INC 2
5
0101
5
y
a,nn
0101
1
2
pcr 2
JRNZ 4
pcr 1
JRZ
sd 1
2
prc 2
JRC 4
imm
INC
6
0110
6
#
(x)
#
0110
1
2
pcr 2
JRNZ 4
pcr
JRZ 4
1
prc 1
JRC
ind
LD 2
7
0111
7
a,y
#
0111
1
2
pcr 2
JRNZ 4
pcr 1
JRZ
sd 1
2
prc
JRC 4
LD
ind
8
1000
8
(x),a
#
1000
1
2
pcr 2
pcr
JRZ 4
1
prc 1
JRC
RNZ
e
4
INC 2
9
1001
9
v
1001
1
2
pcr 2
JRNZ 4
pcr 1
JRZ
sd 1
2
prc
JRC 4
AND
a,(x)
A
1010
A
1010
e
e
e
e
e
e
#
1
2
pcr 2
JRNZ 4
pcr
JRZ 4
1
prc 1
JRC 4
ind
ANDI
LD 2
B
1011
B
1011
a,v
#
a,nn
1
2
pcr 2
JRNZ 4
pcr 1
JRZ
sd 1
2
prc 2
JRC 4
imm
SUB
C
1100
C
1100
a,(x)
1
2
pcr 2
JRNZ 4
pcr
JRZ 4
1
prc 1
JRC 4
ind
SUBI
INC 2
D
1101
D
1101
w
a,nn
1
2
pcr 2
JRNZ 4
pcr 1
JRZ
sd 1
2
prc 2
JRC 4
imm
DEC
E
1110
E
1110
#
(x)
#
1
2
pcr 2
JRNZ 4
pcr
JRZ 4
1
prc 1
JRC
ind
LD 2
F
1111
F
1111
a,w
1
pcr 2
ext 1
pcr 3
bt 1
pcr 1
sd 1
prc
Abbreviations for Addressing Modes:
Legend:
dir
sd
Direct
Short Direct
#
e
b
Indicates Illegal Instructions
5 Bit Displacement
3 Bit Address
imm Immediate
inh
ext
b.d
bt
Inherent
Extended
Bit Direct
Bit Test
rr
1byte dataspace address
1 byte immediate data
12 bit address
nn
abc
ee
8 bit Displacement
pcr
ind
Program Counter Relative
Indirect
56/64
ST6373
Opcode Map Summary.(Continued)
LOW
LOW
8
1000
9
1001
A
1010
B
1011
C
1100
D
1101
E
1110
F
1111
HI
HI
2
JRNZ 4
JP 2
JRNC 4
e
pcr 2
JRNC 4
e
pcr 2
JRNC 4
e
pcr 2
JRNC 4
e
pcr 2
JRNC 4
e
pcr 2
JRNC 4
e
pcr 2
JRNC 4
e
pcr 2
JRNC 4
e
pcr 2
JRNC 4
e
pcr 2
JRNC 4
e
pcr 2
JRNC 4
e
pcr 2
JRNC 4
e
pcr 2
JRNC 4
e
pcr 2
JRNC 4
e
pcr 2
JRNC 4
e
pcr 2
JRNC 4
e
RES 2
b0,rr
b.d 1
SET 2
b0,rr
b.d 1
RES 2
b4,rr
JRZ 4
LDI 2
JRC 4
LD
0
0
e
e
e
e
e
e
e
e
e
abc
abc
abc
abc
abc
abc
abc
abc
abc
abc
abc
abc
abc
abc
abc
abc
e
e
e
rr,nn
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
a,(y)
a,rr
0000
0000
1
2
pcr 2
JRNZ 4
ext 1
JP 2
pcr 3
JRZ 4
imm 1
DEC 2
prc 1
JRC 4
ind
LD
1
0001
1
x
0001
1
2
pcr 2
JRNZ 4
ext 1
JP 2
pcr 1
JRZ 4
sd 1
COM 2
prc 2
JRC 4
dir
CP
2
0010
2
a
a,(y)
a,rr
0010
1
2
pcr 2
JRNZ 4
ext 1
JP 2
b.d 1
SET 2
pcr
JRZ 4
1
prc 1
JRC 4
ind
CP
LD 2
3
0011
3
b4,rr
e
b.d 1
x,a
0011
1
2
pcr 2
JRNZ 4
ext 1
JP 2
pcr 1
JRZ 2
sd 1
RETI 2
prc 2
JRC 4
dir
ADD
a,(y)
RES 2
b2,rr
b.d 1
SET 2
b2,rr
b.d 1
RES 2
b6,rr
b.d 1
SET 2
b6,rr
b.d 1
RES 2
b1,rr
b.d 1
SET 2
b1,rr
b.d 1
RES 2
b5,rr
b.d 1
SET 2
b5,rr
b.d 1
RES 2
b3,rr
b.d 1
SET 2
b3,rr
b.d 1
RES 2
b7,rr
b.d 1
SET 2
b7,rr
4
0100
4
e
e
e
e
e
e
e
e
e
e
e
e
0100
1
2
pcr 2
JRNZ 4
ext 1
JP 2
pcr 1
JRZ 4
inh 1
DEC 2
prc 1
JRC 4
ind
ADD
5
0101
5
y
a,rr
(y)
rr
0101
1
2
pcr 2
JRNZ 4
ext 1
JP 2
pcr 1
JRZ 2
sd 1
STOP 2
prc 2
JRC 4
dir
INC
6
0110
6
0110
1
2
pcr 2
JRNZ 4
ext 1
JP 2
pcr 1
JRZ 4
inh 1
LD 2
prc 1
JRC 4
ind
INC
7
0111
7
y,a
0111
1
2
pcr 2
JRNZ 4
ext 1
JP 2
pcr 1
JRZ
sd 1
2
prc 2
JRC 4
dir
LD
8
1000
8
#
v
(y),a
rr,a
1000
1
2
pcr 2
ext 1
JP 2
pcr
JRZ 4
1
prc 1
JRC 4
ind
LD
RNZ
e
4
DEC 2
9
1001
9
1001
1
2
pcr 2
JRNZ 4
ext 1
JP 2
pcr 1
JRZ 4
sd 1
prc 2
JRC 4
dir
AND
a,(y)
RCL
2
A
1010
A
1010
e
e
e
e
e
e
a
1
2
pcr 2
JRNZ 4
ext 1
JP 2
pcr 1
JRZ 4
inh 1
LD 2
prc 1
JRC 4
ind
AND
B
1011
B
1011
v,a
a,rr
1
2
pcr 2
JRNZ 4
ext 1
JP 2
pcr 1
JRZ 2
sd 1
RET 2
prc 2
JRC 4
dir
SUB
C
1100
C
1100
a,(y)
1
2
pcr 2
JRNZ 4
ext 1
JP 2
pcr 1
JRZ 4
inh 1
DEC 2
prc 1
JRC 4
ind
SUB
D
1101
D
1101
w
a,rr
(y)
rr
1
2
pcr 2
JRNZ 4
ext 1
JP 2
pcr 1
JRZ 2
sd 1
WAIT 2
prc 2
JRC 4
dir
DEC
E
1110
E
1110
1
2
pcr 2
JRNZ 4
ext 1
JP 2
pcr 1
JRZ 4
inh 1
LD 2
prc 1
JRC 4
ind
DEC
F
1111
F
1111
w,a
1
pcr 2
ext 1
pcr 2
b.d 1
pcr 1
sd 1
prc 2
dir
Abbreviations for Addressing Modes:
Legend:
dir
sd
Direct
Short Direct
#
e
b
Indicates Illegal Instructions
5 Bit Displacement
3 Bit Address
imm Immediate
inh
ext
b.d
bt
Inherent
Extended
Bit Direct
Bit Test
rr
1byte dataspace address
1 byte immediate data
12 bit address
nn
abc
ee
8 bit Displacement
pcr
ind
Program Counter Relative
Indirect
57/64
ST6373
6 ELECTRICAL CHARACTERISTICS
6.1 ABSOLUTE MAXIMUM RATINGS
This product contains devices to protect the inputs
against damage due to high static voltages, how-
ever it is advised to take normal precaution to
avoid application of any voltage higher than maxi-
mum rated voltages.
Tj=TA + PD x RthJA
Where :TA = Ambient Temperature.
RthJA =Package thermal resistance(junc-
tion-to ambient).
For proper operation it is recommended that VI
and VO must be higher than VSS and smaller than
VDD. Reliability is enhanced if unused inputs are
connected to an appropriated logic voltage level
(VDD or VSS).
PD = Pint + Pport.
Pint =IDD x VDD (chip internal power).
Pport =Port power dissipation(determined
by the user).
Power Considerations.The average chip-junc-
tion temperature, Tj, in Celsius can be obtained
from:
Symbol
VDD
VI
Parameter
Value
Unit
V
Supply Voltage
-0.3 to 7.0
VSS - 0.3 to +13
Input Voltage (AD IN)
V
VI
Input Voltage (Other inputs)
VSS - 0.3 to +13
V
VO
Output Voltage (PA4-PA7, PC4-PC7)
Output Voltage (Other outputs)
Current Drain per Pin Excluding VDD, VSS, PA0-PA7
Current Drain per Pin (PA0-PA7)
Total Current into VDD (source)
Total Current out of VSS (sink)
Junction Temperature
VSS - 0.3 to VDD + 0.3)
VSS - 0.3 to VDD + 0.3(1)
V
VO
V
IO
+ 10
+ 20
mA
mA
mA
mA
°C
°C
IO
IVDD
IVSS
Tj
50
150
150
TSTG
Storage Temperature
-60 to 150
Note
: Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
THERMAL CHARACTERISTICS
Value
Symbol
Parameter
Test Conditions
Unit
°C/W
Min.
Typ.
Max.
PSDIP42
CSDIP42
67
RthJA
Thermal Resistance
Not Specified
6.2 RECOMMENDED OPERATING CONDITIONS
Value
Typ.
Symbol
Parameter
Test Conditions
1 Suffix Versions
Unit
Min.
0
Max.
70
TA
Operating Temperature
Operating Supply Voltage
°C
VDD
4.5
5.0
5.5
V
Oscillator Frequency
Cycle
0.01
Mnemonic
MHz
fOSC
8.1
2
1
JRC
RUN & WAIT Modes
Operand
e
prc
Bytes
Addressing Mode
58/64
ST6373
6.3 DC ELECTRICAL CHARACTERISTICS
(TA = 0 to +70°C, V = 4.5V unless otherwise specified).
DD
Table 21: DC ELECTRICAL CHARACTERISTICS
Value
Typ.
Symbol
Parameter
Test Conditions
All I/O Pins
Unit
Min.
Max.
V
V
Input Low Level Voltage
Input High Level Voltage
Hysteresis Voltage(1)
0.3xV
V
V
V
IL
DD
All I/O Pins
0.7xV
IH
DD
V
All I/O Pins
1.0
HYS
V
= 5V
DD
V
Low Level Output Voltage
PB0-PB7, PC0-PC7
DA0/O0-DA8/O8
OL
OL
I
I
= 1.6mA
= 5mA
0.4
1.0
V
V
OL
OL
V
Low Level Output Voltage
PA0-PA7
I
I
= 1.6mA
= 10mA
0.4
1.0
OL
OL
V
V
Low Level Output Voltage
Low Level Output Voltage
OSCout
0.4
V
OL
OL
I
= 0.4mA
OL
HDA Output
I
I
= 0.5mA
= 1.6mA
0.4
1.0
V
V
V
V
OL
OL
V
High Level Output Voltage
High Level Output Voltage
High Level Output Voltage
PA0-PA7, PB0-PB7
= – 1.6mA
OH
I
4.1
4.1
4.1
OH
V
OSCout,
I
OH
= – 0.4mA
OH
V
HDA
OH
PU
I
= - 0.5mA
OH
I
I
Input Pull Up Current
Input Mode with Pull-up
PA0-PA7, PB0-PB7,
PC0-PC7, NMI, VSYNC
V
= V
– 100
– 50
– 25
– 25
– 10
µA
µA
IN
SS
Input Pull Up Current
RESET
V
PU
Input Mode with Pull-up
= V
– 50
100
IN
SS
I
Input Pull-down
OSCin
A
µ
IL
current in RESET Mode
I
Input Leakage Current
OSCin
IL
I
V
V
= V
= V
– 10
0.1
– 1
1
– 0.1
10
µA
µA
IH
IN
IN
SS
DD
I
Input Leakage Current
All I/O Input Mode
no Pull-up
IL
I
IH
V
V
= V
= V
– 10
– 10
10
10
A
µ
µA
IN
IN
SS
DD
V
RAM
RAM Retention Voltage in
RESET Mode
1.5
V
DD
I
Input Leakage Current
Reset Pin with Pull-up
V = V
IN
– 50
– 30
– 5
A
µ
µ
IL
I
IH
SS
I
Output Leakage Current
PC0-PC7
= V
10
A
OH
OH
Cycle
Mnemonic
2
1
JRC
V
OH
DD
Operand
e
I
Output Leakage Current High
Voltage
PC4-PC7
40
prc
A
A
µ
µ
Bytes
V
= 12V
OH
DD
Addressing Mode
A
ADC Input Current
V
= 4.5V
1.0
DI
During Conversation
59/64
ST6373
Table 21: DC ELECTRICAL CHARACTERISTICS
Value
Typ.
6
Symbol
Parameter
Test Conditions
Unit
Min.
Max.
I
Supply Current RUN Mode
f
= 8MHz, ILoad= 0mA
OSC
16
mA
DD
V
= 6.0V
DD
I
Supply Current WAIT Mode
f
V
= 8MHz, ILoad= 0mA
= 6V
3
10
1
mA
mA
DD
OSC
DD
I
Supply Current
f
= Not App,
0.1
DD
OSC
RESET, Oscillator Stopped
ILoad= 0mA
= 6V
V
DD
V
Reset Trigger Level ON
Reset Trigger Level OFF
ADC Conversion Range
RESET Pin
0.3xV
V
V
V
ON
DD
V
RESET Pin
0.8xV
DD
OFF
V
V
V
DD
AN
SS
Note 1. Not 100% Tested
6.4 AC ELECTRICAL CHARACTERISTICS
(TA = 0 to +70°C, f =8MHz, V =4.5 to 5.5V unless otherwise specified)
OSC
Parameter
DD
Value
Symbol
Test Conditions
Unit
Min.
Typ.
Max.
t
Minimum Pulse Width
RESET Pin
All Outputs Pins
= 5V, CL = 100pF
125
ns
ns
WRES
t
High to Low Transition Time
40
40
OHL
(2)
V
DD
t
Low to High Transition Time
All Outputs Pins
= 5V, CL = 100pF
ns
OLH
V
DD
t
SPI Data HOLD Time
SPI Baud Rate
250
ns
HD
f
100
kHz
kHz
SPI
f
D/A Converter Repetition
31.25
DAC
(1)
Frequency
t
EEPROM Write Time
T = 25°C One Byte
5
ms
WEE
A
c
EEPROM WRITE/ERASE
Cycles
Q
L
OT
300,000
10
> 1
million
cycles
YEE
A
Acceptance Criteria
(4)
r
EEPROM Data Retention
T = 25°C
years
pF
TEE
A
(3)
C
Input Capacitance
All Inputs Pins
10
10
IN
(3)
C
C
Output Capacitance
All Outputs Pins
pF
OUT
OSC
Oscillator Pins Internal
5
pF
(3)
Capacitance
Notes:
1. A clock other than 8MHz will affect the frequency response of those peripherals (D/A, and SPIs) whose clock is derived from the system
clock.
2. The rise and fall times of PORT A have been increased in order to avoid current spikes while maintaining a high drive capability
3. Not 100% Tested
4. Based on extrapolated data
60/64
ST6373
7 GENERAL INFORMATION
7.1 PACKAGE MECHANICAL DATA
Figure 34. ST6373 and ST63T73 42-Pin Plastic Shrink Dual-In-Line Package
mm
inches
Dim.
Min Typ Max Min Typ Max
A
5.08 0.000 0.000 0.200
G
See Lead Detail
K
2
A1
0.51
0.000 0.020 0.000
A2 3.05 3.81 4.57 0.150 0.120 0.180
B
B1
C
0.38 0.46 0.56 0.018 0.015 0.022
0.89 1.02 1.14 0.040 0.035 0.045
0.23 0.25 0.38 0.010 0.009 0.015
36.58 36.83 37.08 1.450 1.440 1.460
e
A
B
B
1
e
B
D
e
3
e3
E1
e
-
-
-
-
-
-
D
15.24
16.00 0.000 0.600 0.630
0.070 0.000 0.000
N
1
A
2
1.78
eA
eB
G
15.24
0.600 0.000 0.000
K
A
L
1
18.54 0.000 0.000 0.730
A
1
E
1
12.70 13.72 14.48 0.540 0.500 0.570
e
K1
K2
L
-
-
-
-
-
-
-
-
-
-
-
-
VR01725F
N/2
2.54 3.30 3.56 0.130 0.100 0.140
Number of Pins
N
42
Figure 35. ST63E73 42-Pin Ceramic Shrink Dual-In-Line Package
mm
inches
Dim.
Min Typ Max Min Typ Max
A
A1
B
4.5
1.27
0.45
0.89
0.25
37.3
15.49
14.98
-
0.177
0.050
0.018
0.035
0.010
1.470
0.610
0.590
-
B1
C
D
E
E1
K
L
3.2
0.125
0.070
e1
1.78
Number of Pins
42
N
61/64
ST6373
7.2 ORDERING INFORMATION
Customer EEPROM Initial Contents Format
The following chapter deals with the procedure for
transfer the Program/Data ROM codes to SGS-
THOMSON.
a The content should be written as an INTEL IN-
TELLEC format file.
Communication of the ROM Codes
nicate the contents of Program/Data ROM memo-
ries to SGS-THOMSON, the customer must send:
. To commu-
b In the case of 512 bytesof EEPROM, the starting
address is 000h and the end address is 1FFh.
The order of the pages (64 bytes each) is as
shown in the specification.
– one file in INTEL INTELLEC 8/MDS FORMAT
(either as an EPROM or as a MS-DOS diskette)
for the PROGRAM Memory;
c Undefined or don’t care bytes should have the
content FFh.
– one file in INTEL INTELLEC 8/MDS FORMAT
(either as an EPROM or as a MS-DOS diskette)
for the EEPROM initial content (this file is option-
al).
Listing Generation & Verification. When SGS-
THOMSON receives the Codes, a computer listing
is generated from them. This listing refers exactly
to the mask that will be used to produce the micro-
controller. The listing is then returned to the cus-
tomer, and it must be thoroughly check, complete,
sign and return it to SGS-THOMSON. The signed
list constitutes a part of the contractual agreement
for the creation of the customer mask. The SGS-
THOMSON sales organization will be pleased to
provide detailed information regarding contractual
matters.
The program ROM should respect the ROM Mem-
ory Map as in Table 22.
The ROM code must be generated with an ST6
assembler. Before programming the EPROM, the
EPROM programmer buffer must be filled with
FFh.
For shipment to SGS-THOMSON, the master
EPROMs should be placed in a conductive IC car-
rier and packed carefully.
Table 22. ROM Memory Map
ROM Page
Device Address
0000h-007Fh
0080h-07FFh
Description
Reserved
User ROM
PAGE 0
0800h-0F9Fh
0FA0h-0FEFh
0FF0h-0FF7h
0FF8h-0FFBh
0FFCh-0FFDh
0FFEh-0FFFh
User ROM
Reserved
Interrupt Vectors
Reserved
NMI Vector
Reset Vector
PAGE 1
“STATIC”
0000h-000Fh
0010h-07FFh
Reserved
User ROM
PAGE 2
PAGE 3
PAGE 4
PAGE 5
PAGE 6
PAGE 7
0000h-000Fh
0010h-07FFh
Reserved
User ROM
0000h-000Fh
0010h-07FFh
Reserved
User ROM
0000h-000Fh
0010h-07FFh
Reserved
User ROM
0000h-000Fh
0010h-07FFh
Reserved
User ROM
0000h-000Fh
0010h-07FFh
Reserved
User ROM
62/64
1
ST6373
ST6373 ROM MICROCONTROLLER OPTION LIST
Customer
Address
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Phone No
Reference
Device
[ ] ST6373J2
8K ROM
[ ] ST6373J3
12K ROM
[ ] ST6373J5
16K ROM
192 RAM
192 RAM
192 RAM
512 EEPROM
512 EEPROM
512 EEPROM
Special Marking
[ ] No
[ ] Yes
“________________”
(Authorized characters are letters, digits, ’ . ’, ’ - ’, ’ / ’ and spaces only)
Maximum character count is 16 characters
Default marking is sales type (part number)
MASK OPTION:
I2C Clock Speed
[ ] 100KHz (default)
[ ] 400KHz
All options MUST be defined before acceptance
Signature
Date
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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ST6373
Table 23. ORDERING INFORMATION TABLE
Program
DAC
Temp.
Range
Emulating
Devices
Sales Type
EEPROM DDC
Package
Memory
8K ROM
12K ROM
14 Bit
7 Bit
ST6373J2B1/XXX
ST6373J3B1/XXX
ST6373J5B1/XXX
ST63T73J5B1
ST63E73J5D1,
ST63T73J5B1
0 to +70 ° C PSDIP42
16K ROM 512 Bytes Yes
16K OTP
1
9
-
ST63E73J5D1
16K EPROM
25°C
CSDIP42
Note: XXX Is the ROM code identifier that is allocated by SGS-THOMSONafter receipt of all required options and the related ROM file.
“
”
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from itsuse. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously
supplied.SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems
without the express written approval of SGS-THOMSON Microelectronics.
1998 SGS-THOMSON Microelectronics - All rights reserved.
Purchase of I2C Components by SGS-THOMSON Microelectronics conveys a license under the Philips I2C Patent. Rights to use these
components in an I2C system is granted provided that the system conforms to the I2C Standard Specification as defined by Philips.
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