ST6388_技术文档

ST6380,ST6381,ST6382,

ST6383,ST6388,ST6389

8-BIT MCUs WITH

ON-SCREEN-DISPLAY FOR TV TUNING

■ 4.5 to 6V supply operating range

■ 8MHz Maximum Clock Frequency

■ User Program ROM: up to 20140 bytes

■ Reserved Test ROM: up to 340 bytes

■ Data ROM: user selectable size

■ Data RAM: 256 bytes

■ Data EEPROM: 384 bytes

■ 42-Pin Shrink Dual in Line Plastic Package

■ Up to 22 software programmable general

purpose Inputs/Outputs, including 2 direct LED

driving Outputs

■ Two Timers each including an 8-bit counter with

a 7-bit programmable prescaler

■ Digital Watchdog Function

■ Serial Peripheral Interface (SPI) supporting S-

PSDIP42

BUS/ I 2 C BUS and standard serial protocols

■ SPI for external frequency synthesis tuning

■ 14-bit counter for voltage synthesis tuning

■ Up to Six 6-Bit PWM D/A Converters

(Refer to end of Document for Ordering Information)

■ One 8 bits D/A Converter with 7 analog inputs

■ Five interrupt vectors (IRIN/NMI, Timer 1 & 2,

VSYNC, PWR /ADC)

DEVICE SUMMARY

ROM

■ On-chip clock oscillator

■ 8 Lines by 20 Characters On-Screen Display

Generator with 192 Characters in one bank.

14X18 OSD characters with rounding function.

■ All ROM types are supported by pin-to-pin

EPROM and OTP versions with programmable

OSD fonts.

■ The development tool of the ST6380, 81, 82,

83, 88 and ST6389 microcontrollers consists of

the ST638X-EMU2 emulation and development

system to be connected via a standard parallel

line to an MS-DOS Personal Computer.

DEVICE

D/A Converter

(Bytes)

ST6380

ST6381

ST6382

ST6383

ST6388

ST6389

8K

6

4

6

4

6

4

8K

16K

20K

October 2003

1/82

1

Table of Contents

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389 . . . . . . . . 1

1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.3 MEMORY SPACES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.3.1 Stack Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.3.2 Program Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.3.3 Data Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1.3.4 Data RAM/EEPROM/OSD RAM Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.2 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . 18

3.1 ON-CHIP CLOCK OSCILLATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.2 RESETS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.2.1 RESET Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.2.2 Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.2.3 Watchdog Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.2.4 Application Note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.2.5 MCU Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.3 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.3.1 WAIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.3.2 STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.3.3 Exit from WAIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.4 HARDWARE ACTIVATED DIGITAL WATCHDOG FUNCTION . . . . . . . . . . . . . . . . . . . . 22

3.5 INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.5.1 Interrupt Vectors/Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.5.2 Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.5.3 Interrupt Option Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.5.4 Interrupt Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.5.5 ST638x Interrupt Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.1 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.1.1 Details of I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4.1.2 I/O Pin Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4.1.3 Input/Output Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4.1.4 I/O Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4.2 TIMERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

4.2.1 Timer Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

4.2.2 Timer Status Control Registers (TSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4.2.3 Timer Counter Registers (TCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4.2.4 Timer Prescaler Registers (PSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

82

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Table of Contents

4.3 SERIAL PERIPHERAL INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

2

4.3.1 S-BUS/I C BUS Protocol Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

2

4.3.2 S-BUS/I C BUS Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

2

4.3.3 Compatibility S-BUS/I C BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

4.3.4 STD SPI Protocol (Shift Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

4.3.5 SPI Data/Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

4.4 14-BIT VOLTAGE SYNTHESIS TUNING PERIPHERAL . . . . . . . . . . . . . . . . . . . . . . . . . . 44

4.4.1 Output Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

4.4.2 VS Tuning Cell Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

4.5 6-BIT PWM D/A CONVERTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

4.6 A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

4.6.1 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

4.7 DEDICATED LATCHES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

4.8 ON-SCREEN DISPLAY (OSD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

4.8.1 Format Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

4.8.2 Format Character Register (FT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

4.8.3 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

4.9 MIRROR REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

4.10 XOR REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

5 SOFTWARE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

5.1 ST6 ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

5.2 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

5.3 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

6 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

6.1 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

6.2 RECOMMENDED OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

6.3 DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

6.4 AC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

7 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

7.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

7.2 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

7.3 CUSTOMER EEPROM INITIAL CONTENTS: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

7.4 OSD TEST CHARACTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

7.5 ORDERING INFORMATION TABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

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1

Table of Contents

ST63E88,ST63T88, ST63E89,ST63T89 . . . . . . . . . . . . . . . . . . 73

1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

1.1 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

1.2 EPROM/OTP DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

1.3 EPROM ERASING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

2 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

2.1 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

2.2 RECOMMENDED OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

2.3 DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

2.4 AC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

2.5 OSD TEST CHARACTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

82

4/82

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389

1 GENERAL DESCRIPTION

1.1 INTRODUCTION

The ST6380, ST6381, ST6382, ST6383, ST6388,

ST6389 microcontrollers are members of the 8-bit

HCMOS ST638x family, a series of devices spe-

cially oriented to TV applications. Different ROM

size and peripheral configurations are available to

give the maximum application and cost flexibility.

All ST638x members are based on a building

block approach: a common core is surrounded by

a combination of on-chip peripherals (macrocells)

available from a standard library. These peripher-

als are designed with the same Core technology

providing full compatibility and short design time.

Many of these macrocells are specially dedicated

to TV applications. The macrocells of the ST638x

family are: two Timer peripherals each including

an 8-bit counter with a 7-bit software programma-

ble prescaler (Timer), a digital hardware activated

watchdog function (DHWD), a 14-bit voltage syn-

thesis tuning peripheral, a Serial Peripheral Inter-

face (SPI), up to six 6-bit PWM D/A converters, up

to 7 8-bit A/D Converter, an on-screen display

(OSD) with 20 characters per line and 192 charac-

ters (in one bank). In addition the following memo-

ry resources are available: program ROM (up to

20K), data RAM (256 bytes), EEPROM (384

bytes). Refer to pin configurations figures and to

ST638x device summary (Table 1) for the defini-

tion of ST638x family members and a summary of

differences among the different types.

Table 1. Device Summary

ROM

(Bytes)

RAM

(Bytes)

EEPROM

(Bytes)

Colour

Pins

Device

ST6380

ADC

VS

D/A

Emulating Devices

8K

256

384

Yes

6

4

6

4

6

4

3

ST63T88, ST63E88

ST63T89, ST63E89

ST63T88, ST63E88

ST63T89, ST63E89

ST63T88, ST63E88

ST63T89, ST63E89

ST6381

ST6382

ST6383

ST6388

ST6389

16K

20K

5/82

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389

Figure 1. Block Diagram

PA0 - PA7*

PB0 - PB6*

PORT A

TEST

PORT B &

A/D inputs

INTERRUPT

Inputs

IRIN/PC6

PC2, PC4 - PC7*

PC0/SCL

PORT C

PC1/SDA

PC3/SEN

DATA ROM

USER

SELECTABLE

Serial Peripheral

Interface

USER PROGRAM

MEMORY

DATA RAM

256 Bytes

UP TO 20KBytes

TIMER 1

TIMER 2

DATA EEPROM

384 Bytes

Digital

PC

Watchdog Timer

STACK LEVEL 1

STACK LEVEL 2

STACK LEVEL 3

STACK LEVEL 4

STACK LEVEL 5

STACK LEVEL 6

DA0 - DA5*

VS*

D/A Outputs

VS Output

8 BIT CORE

On-Screen

Display

R, G, B, BLANK

HSYNC, VSYNC

POWER

RESET

OSCILLATOR

SUPPLY

OSDOSCout

OSDOSCin

V

OSCin OSCout

DD SS

*Refer to Pin Description for Additional Information

VR01753

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ST6380, ST6381, ST6382, ST6383, ST6388, ST6389

1.2 PIN DESCRIPTION

V

and V . Power is supplied to the MCU using

open-drain (5V drive) in output mode while PC4 to

PC7 are open-drain with 12V drive and the input

pull-up options does not exist on these four pins.

PC0, PC1 and PC3 lines when in output mode are

“ANDed” with the SPI control signals and are all

open-drain. PC0 is connected to the SPI clock sig-

nal (SCL), PC1 with the SPI data signal (SDA)

while PC3 is connected with SPI enable signal

(SEN, used in S-BUS protocol). Pin PC4 and PC6

can also be inputs to software programmable edge

sensitive latches which can generate interrupts;

PC4 can be connected to Power Interrupt while

PC6 can be connected to the IRIN/NMI interrupt

line.

DD

SS

these two pins. V

ground connection.

is power and V

is the

DD

SS

OSCin, OSCout. These pins are internally con-

nected to the on-chip oscillator circuit. A quartz

crystal or a ceramic resonator can be connected

between these two pins in order to allow the cor-

rect operation of the MCU with various stability/

cost trade-offs. The OSCin pin is the input pin, the

OSCout pin is the output pin.

RESET. The active low RESET pin is used to start

the microcontroller to the beginning of its program.

Additionally the quartz crystal oscillator will be dis-

abled when the RESET pin is low to reduce power

consumption during reset phase.

DA0-DA5. These pins are the six PWM D/A out-

puts of the 6-bit on-chip D/A converters. These

lines have open-drain outputs with 12V drive. The

output repetition rate is 31.25KHz (with 8MHz

clock).

TEST. The TEST pin must be held at V for nor-

mal operation.

SS

PA0-PA7. These 8 lines are organized as one I/O

port (A). Each line may be configured as either an

input with or without pull-up resistor or as an out-

put under software control of the data direction

register. Pins PA4 to PA7 are configured as open-

drain outputs (12V drive). On PA4-PA7 pins the in-

put pull-up option is not available while PA6 and

PA7 have additional current driving capability

OSDOSCin, OSDOSCout. These are the On

Screen Display oscillator terminals. An oscillation

capacitor and coil network have to be connected to

provide the right signal to the OSD.

HSYNC, VSYNC. These are the horizontal and

vertical synchronization pins. The active polarity of

these pins to the OSD macrocell can be selected

by the user as ROM mask option. If the device is

specified to have negative logic inputs, then these

signals are low the OSD oscillator stops. If the de-

vice is specified to have positive logic inputs, then

when these signals are high the OSD oscillator

stops. VSYNC is also connected to the VSYNC in-

terrupt.

(25mA, V :1V). PA0 to PA3 pins are configured

as push-pull.

OL

PB0-PB6. These 7 lines are organized as one I/O

port (B). Each line may be configured as either an

input with or without internal pull-up resistor or as

an output under software control of the data direc-

tion register. In addition any pin can be configured

by software as the input to the Analog to Digital

converter. In this case only one pin should be con-

figured at any time to avoid conflicts.

R, G, B, BLANK. Outputs from the OSD. R, G and

B are the color outputs while BLANK is the blank-

ing output. All outputs are push-pull.

PC0-PC7. These 8 lines are organized as one I/O

port (C). Each line may be configured as either an

input with or without internal pull-up resistor or as

an output under software control of the data direc-

tion register. Pins PC0 to PC3 are configured as

VS. This is the output pin of the on-chip 14-bit volt-

age synthesis tuning cell (VS). The tuning signal

present at this pin gives an approximate resolution

of 40KHz per step over the UHF band. This line is

a push-pull output with standard drive.

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ST6380, ST6381, ST6382, ST6383, ST6388, ST6389

Figure 2. ST6380, 82, 88 Pin Configuration

Figure 3. ST6381, 83, 89 Pin Configuration

VDD

42

41

40

39

38

37

36

35

34

42

41

40

39

38

37

36

35

34

DA0

DA1

DA2

DA3

DA4

1

2

3

4

5

6

7

8

VS

DA1

DA2

DA3

DA4

1

2

3

4

5

6

7

8

PC0/SCL

PC1/SDA

PC2

PC3/SEN

PC4/PWRIN

PC5

PC0/SCL

PC1/SDA

PC2

PC3/SEN

PC4/PWRIN

PC5

DA5

AD0/PB0

AD1/PB1

AD2/PB2

AD3/PB3

AD4/PB4

AD5/PB5

AD6/PB6

PA0

AD1/PB1

AD2/PB2

AD3/PB3

AD4/PB4

AD5/PB5

AD6/PB6

PA0

PC6/IRIN

VS

PC6/IRIN

PC7

9

33 RESET

32

33 RESET

32

10

11

12

13

14

15

16

17

18

19

20

21

10

11

12

13

14

15

16

17

18

19

20

21

OSCout

31 OSCin

30 TEST/V_PP

31 OSCin

30 TEST/V_PP

(1)

OSDOSCout

OSDOSCin

VSYNC

HSYNC

BLANK

B

OSDOSCout

OSDOSCin

VSYNC

HSYNC

BLANK

B

29

28

27

26

25

24

23

22

29

28

27

26

25

24

23

22

PA1

PA2

PA3

PA4

PA1

PA2

PA3

PA4

PA5

PA6 (HD0)

PA7 (HD1)

V^SS

PA6 (HD0)

PA7 (HD1)

V^SS

G

R

G

R

(1) This pin is also the V_PPinput for OTP/EPROM devices

VR01375

(1) This pin is also the V_PPinput for OTP/EPROM devices

VR01375E

Table 2. Pin Summary

Pin Function

Description

DA0 to DA5

VS

Output, Open- Drain, 12V

Output, Push- Pull

R, G, B, BLANK

HSYNC, VSYNC

OSDOSCin

OSDOSCout

TEST

Output, Push- Pull

Input, Pull- up, Schmitt Trigger

Input, High Impedance

Output, Push- Pull

Input, Pull- Down

OSCin

OSCout

Input, Resistive Bias, Schmitt Trigger to Reset Logic Only

Output, Push- Pull

RESET

Input, Pull- up, Schmitt Trigger Input

PA0- PA3

PA4- PA5

PA6- PA7

PB0- PB6

PC0- PC3

PC4- PC7

I/ O, Push- Pull, Software Input Pull- up, Schmitt Trigger Input 5mA

I/ O, Open- Drain, 12V, No Input Pull- up, Schmitt Trigger Input

I/ O, Open- Drain, 12V, No Input Pull- up, Schmitt Trigger Input, High Drive 25mA

I/ O, Push- Pull/Open Drain, Software Input Pull- up, Schmitt Trigger Input, Analog input

I/ O, Open- Drain, 5V, Software Input Pull- up, Schmitt Trigger Input 5mA

I/ O, Open- Drain, 12V, No Input Pull- up, Schmitt Trigger Input 5mA

Power Supply Pins

V

, V

DD SS

8/82

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389

1.3 MEMORY SPACES

The MCU operates in three different memory

spaces: Stack Space, Program Space and Data

Space.

seen as static space. Table 3 gives the different

codes that allows the selection of the correspond-

ing banks. Note that, from the memory point of

view, the Page 1 and the Static Page represent

the same physical memory: it is only a different

way of addressing the same location. On the

ST6388 and ST6389, a total of 20480 bytes of

ROM have been implemented; 20140 bytes are

available as User ROM while 340 bytes are re-

served for testing.

1.3.1 Stack Space

The stack space consists of six 12 bit registers that

are used for stacking subroutine and interrupt re-

turn addresses plus the current program counter

register.

1.3.2 Program Space

Figure 4. 20K-Byte Program Space Addressing

The program space is physically implemented in

the ROM and includes all the instructions that are

to be executed, as well as the data required for the

immediate addressing mode instructions, the re-

served test area and the user vectors. It is ad-

dressed thanks to the 12-bit Program Counter reg-

ister (PC register) and the ST6 Core can directly

address up to 4K bytes of Program Space. Never-

theless, the Program Space can be extended by

the addition of 2Kbyte memory banks as it is

shown in Figure 5, in which the 20K bytes memory

is described. These banks are addressed by point-

ing to the 000h-7FFh locations of the Program

Space thanks to the Program Counter, and by writ-

ing the appropriate code in the Program ROM

Page Register (PRPR) located at address CAh in

the Data Space. Because interrupts and common

subroutines should be available all the time only

the lower 2K byte of the 4K program space are

bank switched while the upper 2K byte can be

Program

counter

space

4FFFh

0000h

0FFFh

Page 1

Static

Page

0800h

07FFh

Page 1

...

Page 0

Page 9

Static Page

0000h

Figure 5. Memory Addressing Diagram

STACK SPACE

PROGRAM SPACE

DATA SPACE

0000h

000h

PROGRAM COUNTER

RAM / EEPROM

BANKING AREA

ROM

0-63

STACK LEVEL 1

STACK LEVEL 2

STACK LEVEL 3

STACK LEVEL 4

STACK LEVEL 5

STACK LEVEL 6

03Fh

040h

DATA ROM

WINDOW

07FFh

0800h

07Fh

080h

081h

082h

083h

084h

X REGISTER

Y REGISTER

V REGISTER

W REGISTER

ROM

RAM

0C0h

DATA ROM

0FF0h

0FFFh

WINDOW SELECT

DATA RAM

BANK SELECT

INTERRUPT &

RESET VECTORS

ACCUMULATOR

0FFh

vr01568

9/82

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389

MEMORY SPACES (Cont’d)

Program ROM Page Register (PRPR)

Address: CAh - Write only

Reset Value: XXh

restore its previous content. Anyway, this opera-

tion may be necessary if the sum of common rou-

tines and interrupt drivers will take more than 2K

bytes; in this case it could be necessary to divide

the interrupt driver in a (minor) part in the static

page (start and end), and in the second (major)

part in one dynamic page. If it is impossible to

avoid the writing of this register in interrupts driv-

ers, an image of this register must be saved in a

RAM location. Each time the program writes the

PRPR register, the image register should also be

written. The image register must be written first, so

if an interrupt occurs between the two instructions

the PRPR is not affected.

7

0

-

PRPR3 PRPR2 PRPR1 PRPR0

D7-D4. These bits are not used but have to be

written to “0”.

PRPR3-PRPR0. These are the program ROM

banking bits and the value loaded selects the cor-

responding page to be addressed in the lower part

of 4K program address space as specified in Table

4. This register is undefined on reset.

Table 3. Program Memory Page Register coding

PRPR3 PRPR2 PRPR1 PRPR0 PC11 Memory Page

Caution: This register contains at least one write

only bit. Single bit instructions (SET, RES, INC

and DEC) should not be used.

Static Page

X

0

X

0

X

0

X

0

1

0

(Page 1)

Page 0

Page 1 (Static

Page)

Note. Only the lower part of address space has

been bankswitched because interrupt vectors and

common subroutines should be available all the

time. The reason of this structure is due to the fact

that it is not possible to jump from a dynamic page

to another, unless jumping back to the static page,

changing contents of PRPR and then jumping to a

different dynamic page.

Care is required when handling the PRPR as it is

write only. For this reason, it is not allowed to

change the PRPR contents while executing inter-

rupts drivers, as the driver cannot save and than

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Page 2

Page 3

Page 4

Page 5

Page 6

Page 7

Page 8

Page 9

Table 4. Program Memory Map

Program Memory Page

Device Address

0000h-007Fh

0080h-07FFh

0800h-0F9Fh

0FA0h-0FEFh

0FF0h-0FF7h

0FF8h-0FFBh

0FFCh-0FFDh

0FFEh-0FFFh

0000h-000Fh

0010h-07FFh

0000h-000Fh

0010h-07FFh

0000h-000Fh

0010h-07FFh

0000h-000Fh

0010h-07FFh

0000h-000Fh

0010h-07FFh

0000h-000Fh

0010h-07FFh

0000h-000Fh

0010h-07FFh

0000h-000Fh

0010h-07FFh

Description

Reserved

User ROM

Reserved

Interrupt Vectors

Reserved

NMI Vector

Reset Vector

Reserved

PAGE 0

PAGE 1

“STATIC”

PAGE 2

PAGE 3

PAGE 4

PAGE 5

PAGE 6

PAGE 7

PAGE 8

PAGE 9

User ROM

Reserved

User ROM (End of 8K ST6380, 81)

Reserved

User ROM

Reserved

User ROM

Reserved

User ROM

Reserved

User ROM (End of 16K ST6382, 83)

Reserved

User ROM

Reserved

User ROM (End of 20K ST6388, 89)

10/82

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389

1.3.3 Data Space

The Data Space allows the addressing of RAM

(256 bytes), EEPROM (384 bytes), ST6 Core and

peripheral registers, as well as read-only data

such as constants and look-up tables.

The ST6 Core instruction set operates on a specif-

ic space, referred to as the Data Space, which

contains all the data necessary for the program.

RESERVED

TIMER 2 PRESCALER REGISTER

TIMER 2 COUNTER REGISTER

TIMER 2 STATUS/CONTROL REGISTER

RESERVED

0D9h

0DAh

0DBh

0DCh

0DDh

0DEh

0DFh

0E0h

0E1h

0E2h

0E3h

0E4h

0E5h

0E6h

0E7h

0E8h

0E9h

0EAh

0EBh

0ECh

0EDh

0EEh

0EFh

0F0h

0F5h

Figure 6. Data Space

000h

DATA RAM/EEPROM/OSD

BANK AREA

03Fh

MIRROR REGISTER

040h

DATA ROM

XOR REGISTER

WINDOW AREA

07Fh

DA 0 DATA/CONTROL REGISTER

DA 1 DATA/CONTROL REGISTER

DA 2 DATA/CONTROL REGISTER

DA 3 DATA/CONTROL REGISTER

IR & VSYNC STATUS REGISTER

RESERVED

X REGISTER

Y REGISTER

V REGISTER

W REGISTER

080h

081h

082h

083h

084h

0BFh

0C0h

0C1h

0C2h

0C3h

0C4h

0C5h

0C6h

0C7h

0C8h

0C9h

0CAh

0CBh

0CCh

0CDh

0CEh

0CFh

0D0h

0D1h

0D2h

0D3h

0D4h

0D5h

0D7h

0D8h

DATA RAM

DA 4 DATA/CONTROL REGISTER

DA 5 DATA/CONTROL REGISTER

DATA RAM BANK REGISTER

DEDICATED LATCHES CONTROL REGISTER

EEPROM CONTROL REGISTER

SPI CONTROL REGISTER 1

SPI CONTROL REGISTER 2

OSD POLARITY SELECT REGISTER

VS DATA REGISTER 1

PORT A DATA REGISTER

PORT B DATA REGISTER

PORT C DATA REGISTER

RESERVED

PORT A DIRECTION REGISTER

PORT B DIRECTION REGISTER

PORT C DIRECTION REGISTER

RESERVED

VS DATA REGISTER 2

INTERRUPT OPTION REGISTER

DATA ROM WINDOW REGISTER

PROGRAM ROM PAGE REGISTER

RESERVED

0FEh

0FFh

ACCUMULATOR

SPI DATA REGISTER

PORT B OPTION REGISTER

OSD CONTROL REGISTERS LOCATED IN

PAGE 5 OF BANKED DATA RAM

RESERVED

ADC DATA REGISTER

ADC CONTROL REGISTER

VERTICAL START ADDRESS REGISTER

HORIZONTAL START ADDRESS REGISTER

VERTICAL SPACE REGISTER 0

038h

039h

03Ah

03Bh

03Ch

03Dh

03Fh

TIMER 1 PRESCALER REGISTER

TIMER 1 COUNTER REGISTER

TIMER 1 STATUS/CONTROL REGISTER

HORIZONTAL SPACE REGISTER

BACKGROUND COLOUR REGISTER

VERTICAL SPACE REGISTER 1

RESERVED

OSD GLOBAL ENABLE REGISTER

WATCHDOG REGISTER

11/82

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389

MEMORY SPACES (Cont’d)

Data ROM Addressing. All the read-only data are

physically implemented in the ROM in which the

Program Space is also implemented. The ROM

therefore contains the program to be executed and

also the constants and the look-up tables needed

for the program. The locations of Data Space in

which the different constants and look-up tables

are addressed by the ST6 Core can be considered

as being a 64-byte window through which it is pos-

sible to access to the read-only data stored in the

ROM. This window is located from the 40h ad-

dress to the 7Fh address in the Data space and al-

lows the direct reading of the bytes from the 000h

address to the 03Fh address in the ROM. All the

bytes of the ROM can be used to store either in-

structions or read-only data. Indeed, the window

can be moved by step of 64 bytes along the ROM

in writing the appropriate code in the Write-only

Data ROM Window register (DRWR, location

C9h). The effective address of the byte to be read

as a data in the ROM is obtained by the concate-

nation of the 6 less significant bits of the address in

the Data Space (as less significant bits) and the

content of the DRWR (as most significant bits). So

when addressing location 40h of data space, and

0 is loaded in the DRWR, the physical addressed

location in ROM is 00h.

Data ROM Window Register (DRWR)

Address: C9h - Write only

Reset Value: XXh

7

0

DRWR DRWR DRWR DRWR DRWR DRWR DRWR DRWR

7

6

5

4

3

2

1

0

DRWR7-DRWR0. These are the Data Rom Win-

dow bits that correspond to the upper bits of data

ROM program space. This register is undefined af-

ter reset.

Caution: This register contains at least one write

only bit. Single bit instructions (SET, RES, INC

and DEC) should not be used.

Note: Care is required when handling the DRWR

as it is write only. For this reason, it is not allowed

to change the DRWR contents while executing in-

terrupts drivers, as the driver cannot save and

than restore its previous content. If it is impossible

to avoid the writing of this register in interrupts

drivers, an image of this register must be saved in

a RAM location, and each time the program writes

the DRWR it writes also the image register. The

image register must be written first, so if an inter-

rupt occurs between the two instructions the

DRWR register is not affected.

Note: The data ROM Window can not address

window above the 16K byte range.

Figure 7. Data ROM Window Memory Addressing

11 10

9

3

8

2

7

1

6

0

5

4

3

2

1

0

13 12

PROGRAM SPACE ADDRESS

READ

DATA ROM

WINDOW REGISTER

CONTENTS

7

6

5

4

DATA SPACE ADDRESS

40h-7Fh

(DWR)

0

1

IN INSTRUCTION

Example:

DWR=28h

0

1

0

1

0

1

DATA SPACE ADDRESS

59h

1

0

ROM

ADDRESS:A19h

0

1

VR01573B

12/82

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389

MEMORY SPACES (Cont’d)

1.3.4 Data RAM/EEPROM/OSD

Addressing

RAM

Caution: This register contains at least one write

only bit. Single bit instructions (SET, RES, INC

and DEC) should not be used.

In all members of the ST638x family 64 bytes of

data RAM are directly addressable in the data

space from 80h to BFh addresses. The additional

192 bytes of RAM, the 384 bytes of EEPROM, and

the OSD RAM can be addressed using the banks

of 64 bytes located between addresses 00h and

3Fh. The selection of the bank is done by pro-

gramming the Data RAM Bank Register (DRBR)

located at the E8h address of the Data Space. In

this way each bank of RAM, EEPROM or OSD

RAM can select 64 bytes at a time. No more than

one bank should be set at a time.

Note: Care is required when handling the DRBR

as it is write only. For this reason, it is not allowed

to change the DRBR contents while executing in-

terrupts drivers, as the driver cannot save and

than restore its previous content. If it is impossible

to avoid the writing of this register in interrupts

drivers, an image of this register must be saved in

a RAM location, and each time the program writes

the DRBR it writes also the image register. The im-

age register must be written first, so if an interrupt

occurs between the two instructions the DRBR is

not affected.

Data RAM Bank Register (DRBR)

Address: E8h - Write only

Reset Value: XXh

Table 5. Data RAM Bank Register Set-up

DRBR Value

Selection

7

0

Hex.

01h

02h

03h

81h

82h

83h

04h

08h

10h

20h

Binary

0000 0001

0000 0010

0000 0011

1000 0001

1000 0010

1000 0011

0000 0100

0000 1000

0001 0000

0010 0000

EEPROM Page 0

EEPROM Page 1

EEPROM Page 2

EEPROM Page 3

EEPROM Page 4

EEPROM Page 5

RAM Page 2

DRBR DRBR DRBR DRBR DRBR DRBR DRBR DRBR

7

6

5

4

3

2

1

0

DRBR7,DRBR1,DRBR0. These bits select the

EEPROM pages.

DRBR6, DRBR5. Each of these bits, when set, will

select one OSD RAM register page.

DRBR4,DRBR3,DRBR2. Each of these bits, when

set, will select one RAM page.

RAM Page 3

RAM Page 4

This register is undefined after reset.

OSD Page 5

Table 5 summarizes how to set the Data RAM

Bank Register in order to select the various banks

or pages.

13/82

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389

MEMORY SPACES (Cont’d)

EEPROM Description

power consumption of the EEPROM is reduced to

the leakage values.

The data space of ST638x family from 00h to 3Fh

is paged as described in Table 5. 384 bytes of

EEPROM located in six pages of 64 bytes (pages

0,1,2,3,4 and 5, see Table 5).

D5, D4. Reserved for testing purposes, they must

be set to zero.

PS. WRITE ONLY. Once in Parallel Mode, as

soon as the user software sets the PS bit the par-

allel writing of the 8 adjacent registers will start. PS

is internally reset at the end of the programming

procedure. Note that less than 8 bytes can be writ-

ten; after parallel programming the remaining un-

defined bytes will have no particular content.

Through the programming of the Data RAM Bank

Register (DRBR=E8h) the user can select the

bank or page leaving unaffected the way to ad-

dress the static registers. The way to address the

“dynamic” page is to set the DRBR as described in

Table 5 (e.g. to select EEPROM page 0, the

DRBR has to be loaded with content 01h, see

Data RAM/EEPROM/OSD RAM addressing for

additional information). Bits 0, 1 and 7 of the

DRBR are dedicated to the EEPROM.

PE. WRITE ONLY. This bit must be set by the user

program in order to perform parallel programming

(more bytes per time). If PE is set and the “parallel

start bit” (PS) is low, up to 8 adjacent bytes can be

written at the maximum speed, the content being

stored in volatile registers. These 8 adjacent bytes

can be considered as row, whose A7, A6, A5, A4,

A3 are fixed while A2, A1 and A0 are the changing

bytes. PE is automatically reset at the end of any

parallel programming procedure. PE can be reset

by the user software before starting the program-

ming procedure, leaving unchanged the EEPROM

registers.

The EEPROM pages do not require dedicated in-

structions to be accessed in reading or writing.

The EEPROM is controlled by the EEPROM Con-

trol Register (EECR=EAh). Any EEPROM location

can be read just like any other data location, also

in terms of access time.

To write an EEPROM location takes an average

time of 5 ms (10ms max) and during this time the

EEPROM is not accessible by the Core. A busy

flag can be read by the Core to know the EEPROM

status before trying any access. In writing the

EEPROM can work in two modes: Byte Mode

(BMODE) and Parallel Mode (PMODE). The

BMODE is the normal way to use the EEPROM

and consists in accessing one byte at a time. The

PMODE consists in accessing 8 bytes per time.

BS. READ ONLY. This bit will be automatically set

by the CORE when the user program modifies an

EEPROM register. The user program has to test it

before any read or write EEPROM operation; any

attempt to access the EEPROM while “busy bit” is

set will be aborted and the writing procedure in

progress completed.

EEPROM Control Register (EECR)

Address: EAh - Read only/Write only

Reset Value:

EN. WRITE ONLY. This bit MUST be set to one in

order to write any EEPROM register. If the user

program will attempt to write the EEPROM when

EN= “0” the involved registers will be unaffected

and the “busy bit” will not be set.

7

0

After RESET the content of EECR register will be

00h.

-

SB

-

PS

PE

BS

EN

Notes: When the EEPROM is busy (BS=”1”) the

EECR can not be accessed in write mode, it is only

possible to read BS status. This implies that as

long as the EEPROM is busy it is not possible to

change the status of the EEPROM control register.

EECR bits 4 and 5 are reserved for test purposes,

and must never be set to “1”.

D7. Not used

Caution: This register contains at least one write

only bit. Single bit instructions (SET, RES, INC

and DEC) should not be used.

SB. WRITE ONLY. If this bit is set the EEPROM is

disabled (any access will be meaningless) and the

14/82

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389

MEMORY SPACES (Cont’d)

Additional Notes on Parallel Mode. If the user

wants to perform a parallel programming the first

action should be the setting of the PE bit; from this

moment, the first time the EEPROM will be ad-

dressed in writing, the ROW address will be

latched and it will be possible to change it only at

the end of the programming procedure or by reset-

ting PE without programming the EEPROM.

For example, if the software sets PE and accesses

EEPROM in writing at addresses 18h,1Ah,1Bh

and then sets PS, these three registers will be

modified at the same time; the remaining bytes will

have no particular content. Note that PE is inter-

nally reset at the end of the programming proce-

dure. This implies that the user must set PE bit be-

tween two parallel programming procedures. Any-

way the user can set and then reset PE without

performing any EEPROM programming. PS is a

set only bit and is internally reset at the end of the

programming procedure. Note that if the user tries

to set PS while PE is not set there will not be any

programming procedure and the PS bit will be un-

affected. Consequently PS bit can not be set if EN

is low. PS can be affected by the user set if, and

only if, EN and PE bits are also set to one.

After the ROW address latching the Core can

“see” just one EEPROM row (the selected one)

and any attempt to write or read other rows will

produce errors. Do not read the EEPROM while

PE is set.

As soon as PE bit is set, the 8 volatile ROW latch-

es are cleared. From this moment the user can

load data in the whole ROW or just in a subset. PS

setting will modify the EEPROM registers corre-

sponding to the ROW latches accessed after PE.

15/82

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389

2 CENTRAL PROCESSING UNIT

2.1 INTRODUCTION

The CPU Core of ST6 devices is independent of the

I/O or Memory configuration. As such, it may be

thought of as an independent central processor

communicating with on-chip I/O, Memory and Pe-

ripherals via internal address, data, and control

buses. In-core communication is arranged as

shown in Figure 8; the controller being externally

linked to both the Reset and Oscillator circuits,

while the core is linked to the dedicated on-chip pe-

ripherals via the serial data bus and indirectly, for

interrupt purposes, through the control registers.

Indirect Registers (X, Y). These two indirect reg-

isters are used as pointers to memory locations in

Data space. They are used in the register-indirect

addressing mode. These registers can be ad-

dressed in the data space as RAM locations at ad-

dresses 80h (X) and 81h (Y). They can also be ac-

cessed with the direct, short direct, or bit direct ad-

dressing modes. Accordingly, the ST6 instruction

set can use the indirect registers as any other reg-

ister of the data space.

Short Direct Registers (V, W). These two regis-

ters are used to save a byte in short direct ad-

dressing mode. They can be addressed in Data

space as RAM locations at addresses 82h (V) and

83h (W). They can also be accessed using the di-

rect and bit direct addressing modes. Thus, the

ST6 instruction set can use the short direct regis-

ters as any other register of the data space.

2.2 CPU REGISTERS

The ST6 Family CPU core features six registers

and three pairs of flags available to the program-

mer. These are described in the following para-

graphs.

Accumulator (A). The accumulator is an 8-bit

general purpose register used in all arithmetic cal-

culations, logical operations, and data manipula-

tions. The accumulator can be addressed in Data

space as a RAM location at address FFh. Thus the

ST6 can manipulate the accumulator just like any

other register in Data space.

Program Counter (PC). The program counter is a

12-bit register which contains the address of the

next ROM location to be processed by the core.

This ROM location may be an opcode, an oper-

and, or the address of an operand. The 12-bit

length allows the direct addressing of 4096 bytes

in Program space.

Figure 8. ST6 Core Block Diagram

0,01 TO 8MHz

RESET

OSCin

OSCout

INTERRUPTS

DATA SPACE

CONTROLLER

CONTROL

SIGNALS

FLAG

VALUES

DATA

OPCODE

ADDRESS/READ LINE

2

RAM/EEPROM

PROGRAM

DATA

ADDRESS

ROM/EPROM

256

ROM/EPROM

DECODER

B-DATA

A-DATA

DEDICATIONS

ACCUMULATOR

Program Counter

and

12

FLAGS

6 LAYER STACK

ALU

RESULTS TO DATA SPACE (WRITE LINE)

VR01811

16/82

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389

CPU REGISTERS (Cont’d)

However, if the program space contains more than

4096 bytes, the additional memory in program

space can be addressed by using the Program

Bank Switch register.

automatically selected after the reset of the MCU,

the ST6 core uses at first the NMI flags.

Stack. The ST6 CPU includes a true LIFO hard-

ware stack which eliminates the need for a stack

pointer. The stack consists of six separate 12-bit

RAM locations that do not belong to the data

space RAM area. When a subroutine call (or inter-

rupt request) occurs, the contents of each level are

shifted into the next higher level, while the content

of the PC is shifted into the first level (the original

contents of the sixth stack level are lost). When a

subroutine or interrupt return occurs (RET or RETI

instructions), the first level register is shifted back

into the PC and the value of each level is popped

back into the previous level. Since the accumula-

tor, in common with all other data space registers,

is not stored in this stack, management of these

registers should be performed within the subrou-

tine. The stack will remain in its “deepest” position

if more than 6 nested calls or interrupts are execut-

ed, and consequently the last return address will

be lost. It will also remain in its highest position if

the stack is empty and a RET or RETI is executed.

In this case the next instruction will be executed.

The PC value is incremented after reading the ad-

dress of the current instruction. To execute relative

jumps, the PC and the offset are shifted through

the ALU, where they are added; the result is then

shifted back into the PC. The program counter can

be changed in the following ways:

- JP (Jump) instruction . . . . . PC=Jump address

- CALL instruction . . . . . . . . . PC= Call address

- Relative Branch Instruction . PC= PC +/- offset

- Interrupt . . . . . . . . . . . . . .PC=Interrupt vector

- Reset . . . . . . . . . . . . . . . . . PC= Reset vector

- RET & RETI instructions . . . . PC= Pop (stack)

- Normal instruction . . . . . . . . . . . . .PC= PC + 1

Flags (C, Z). The ST6 CPU includes three pairs of

flags (Carry and Zero), each pair being associated

with one of the three normal modes of operation:

Normal mode, Interrupt mode and Non Maskable

Interrupt mode. Each pair consists of a CARRY

flag and a ZERO flag. One pair (CN, ZN) is used

during Normal operation, another pair is used dur-

ing Interrupt mode (CI, ZI), and a third pair is used

in the Non Maskable Interrupt mode (CNMI, ZN-

MI).

Figure 9. ST6 CPU Programming Mode

l

b7 X REG. POINTER b0

INDEX

REGISTER

SHORT

DIRECT

ADDRESSING

MODE

b7 Y REG. POINTER b0

The ST6 CPU uses the pair of flags associated

with the current mode: as soon as an interrupt (or

a Non Maskable Interrupt) is generated, the ST6

CPU uses the Interrupt flags (resp. the NMI flags)

instead of the Normal flags. When the RETI in-

struction is executed, the previously used set of

flags is restored. It should be noted that each flag

set can only be addressed in its own context (Non

Maskable Interrupt, Normal Interrupt or Main rou-

tine). The flags are not cleared during context

switching and thus retain their status.

V REGISTER

W REGISTER

b7

b0

b7 ACCUMULATOR

PROGRAM COUNTER

b11

SIX LEVELS

STACK REGISTER

The Carry flag is set when a carry or a borrow oc-

curs during arithmetic operations; otherwise it is

cleared. The Carry flag is also set to the value of

the bit tested in a bit test instruction; it also partici-

pates in the rotate left instruction.

NORMAL FLAGS

INTERRUPT FLAGS

NMI FLAGS

C

Z

The Zero flag is set if the result of the last arithme-

tic or logical operation was equal to zero; other-

wise it is cleared.

Switching between the three sets of flags is per-

formed automatically when an NMI, an interrupt or

a RETI instructions occurs. As the NMI mode is

VA000423

17/82

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389

3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES

3.1 ON-CHIP CLOCK OSCILLATOR

The internal oscillator circuit is designed to require

a minimum of external components. A crystal

quartz, a ceramic resonator, or an external signal

(provided to the OSCin pin) may be used to gener-

ate a system clock with various stability/cost trade-

offs. The typical clock frequency is 8MHz. Please

note that different frequencies will affect the oper-

ation of those peripherals (D/As, SPI) whose refer-

ence frequencies are derived from the system

clock.

Figure 10. Clock Generator Option 1

CRYSTAL/RESONATOR CLOCK

ST6xxx

OSC

out

in

The different clock generator connection schemes

are shown in Figure 10 and 11. One machine cycle

takes 13 oscillator pulses; 12 clock pulses are

needed to increment the PC while and additional

13th pulse is needed to stabilize the internal latch-

es during memory addressing. This means that

with a clock frequency of 8MHz the machine cycle

is 1.625µSec.

C

L1

L2

VA0016B

Figure 11. Clock Generator Option 2

The crystal oscillator start-up time is a function of

many variables: crystal parameters (especially

RS), oscillator load capacitance (CL), IC parame-

ters, ambient temperature, and supply voltage.It

must be observed that the crystal or ceramic leads

and circuit connections must be as short as possi-

ble. Typical values for CL1 and CL2 are in the

range of 15pF to 22pF but these should be chosen

based on the crystal manufacturers specification.

Typical input capacitance for OSCin and OSCout

pins is 5pF.

EXTERNAL CLOCK

ST6xxx

OSC

NC

in

out

The oscillator output frequency is internally divided

by 13 to produce the machine cycle and by 12 to

produce the Timers and the Watchdog clock. A

byte cycle is the smallest unit needed to execute

any operation (i.e., increment the program coun-

ter). An instruction may need two, four, or five byte

cycles to be executed (See Table 6).

VA0015C

Figure 12. OSCin, OSCout Diagram

OSCin, OSCout (QUARTZ PINS)

V

DD

Table 6. Instruction Timing with 8MHz Clock

Execution

OSCin

Instruction Type

Cycles

Time

8.125µs

6.50µs

3.25µs

Branch if set/reset

5 Cycles

4 Cycles

2 Cycles

1M

Branch & Subroutine Branch

Bit Manipulation

V

DD

Load Instruction

In

OSCout

VA00462

Arithmetic & Logic

Conditional Branch

Program Control

18/82

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389

3.2 RESETS

The MCU can be reset in three ways:

Figure 13). The circuit guarantees that the MCU

will exit or enter the reset state correctly, without

spurious effects, ensuring, for example, that EEP-

ROM contents are not corrupted.

– by the external Reset input being pulled low;

– by Power-on Reset;

– by the digital Watchdog peripheral timing out.

3.2.1 RESET Input

Figure 13. Power ON/OFF Reset operation

The RESET pin may be connected to a device of

the application board in order to reset the MCU if

required. The RESET pin may be pulled low in

RUN, WAIT or STOP mode. This input can be

used to reset the MCU internal state and ensure a

correct start-up procedure. The pin is active low

and features a Schmitt trigger input. The internal

Reset signal is generated by adding a delay to the

external signal. Therefore even short pulses on

V

DD

4.2

Threshold

3.4

t

the RESET pin are acceptable, provided V has

DD

completed its rising phase and that the oscillator is

running correctly (normal RUN or WAIT modes).

The MCU is kept in the Reset state as long as the

RESET pin is held low.

V

DD

POWER

ON/OFF

If RESET activation occurs in RUN or WAIT

modes, processing of the user program is stopped

(RUN mode only), the Inputs and Outputs are con-

figured as inputs with pull-up resistors if available.

When the level on the RESET pin then goes high,

the initialization sequence is executed following

expiry of the internal delay period.

RESET

t

VR02037

Figure 14. Reset and Interrupt Processing

If RESET pin activation occurs in the STOP mode,

the oscillator starts up and all Inputs and Outputs

are configured as inputs with pull-up resistors if

available. When the level of the RESET pin then

goes high, the initialization sequence is executed

following expiry of the internal delay period.

RESET

NMI MASK SET

INT LATCH CLEARED

( IF PRESENT )

3.2.2 Power-on Reset

The function of the POR circuit consists in waking

up the MCU at an appropriate stage during the

power-on sequence. At the beginning of this se-

quence, the MCU is configured in the Reset state:

all I/O ports are configured as inputs with pull-up

resistors and no instruction is executed. When the

power supply voltage rises to a sufficient level, the

oscillator starts to operate, whereupon an internal

delay is initiated, in order to allow the oscillator to

fully stabilize before executing the first instruction.

The initialization sequence is executed immediate-

ly following the internal delay.

SELECT

NMI MODE FLAGS

PUT FFEH

ON ADDRESS BUS

YES

IS RESET STILL

PRESENT?

NO

The internal delay is generated by an on-chip

counter. The internal reset line is released 2048 in-

ternal clock cycles after release of the external re-

set.

LOAD PC

FROM RESET LOCATIONS

FFE/FFF

The internal POR device is a static mechanism

FETCH INSTRUCTION

which forces the reset state when V

is below a

DD

VA000427

threshold voltage in the range 3.4 to 4.2 Volts (see

19/82

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389

RESETS (Cont’d)

3.2.3 Watchdog Reset

mode and enable interrupts. If no pending interrupt

is present at the end of the initialisation routine, the

MCU will continue by processing the instruction

immediately following the RETI instruction. If, how-

ever, a pending interrupt is present, it will be serv-

iced.

The MCU provides a Watchdog timer function in

order to ensure graceful recovery from software

upsets. If the Watchdog register is not refreshed

before an end-of-count condition is reached, the

internal reset will be activated. This, amongst oth-

er things, resets the watchdog counter.

Figure 15. Reset and Interrupt Processing

The MCU restarts just as though the Reset had

been generated by the RESET pin, including the

built-in stabilisation delay period.

RESET

3.2.4 Application Note

No external resistor is required between V

and

DD

JP:2 BYTES/4 CYCLES

JP

the Reset pin, thanks to the built-in pull-up device.

RESET

VECTOR

3.2.5 MCU Initialization Sequence

When a reset occurs the stack is reset, the PC is

loaded with the address of the Reset Vector (locat-

ed in program ROM starting at address 0FFEh). A

jump to the beginning of the user program must be

coded at this address. Following a Reset, the In-

terrupt flag is automatically set, so that the CPU is

in Non Maskable Interrupt mode; this prevents the

initialisation routine from being interrupted. The in-

itialisation routine should therefore be terminated

by a RETI instruction, in order to revert to normal

INITIALIZATION

ROUTINE

RETI: 1 BYTE/2 CYCLES

RETI

VA00181

Figure 16. Reset Circuit

ST6

OSCILLATOR

SIGNAL

INTERNAL

RESET

COUNTER

TO ST6

1k

V

RESET

(ACTIVE LOW)

DD

300k

WATCHDOG RESET

POWER ON/OFF RESET

VA0200E

20/82

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389

3.3 POWER SAVING MODES

STOP and WAIT modes have been implemented

in the ST638x in order to reduce the current con-

sumption of the device during idle periods. These

two modes are described in the following para-

graphs. Since the hardware activated digital

watchdog function is present, the STOP instruc-

tion is de-activated and any attempt to execute it

will cause the automatic execution of a WAIT in-

struction.

mode) before the start of the WAIT sequence, but

also of the type of the interrupt request that is gen-

erated. In all cases the GEN bit of IOR has to be

set to 1 in order to restart from WAIT mode. Con-

trary to the operation of NMI in the run mode, the

NMI is masked in WAIT mode if GEN=0.

Normal Mode. If the MCU Core was in the main

routine when the WAIT instruction has been exe-

cuted, the Core exits from WAIT mode as soon as

an interrupt occurs; the corresponding interrupt

routine is executed, and at the end of the interrupt

service routine, the instruction that follows the

WAIT instruction is executed if no other interrupts

are pending.

3.3.1 WAIT Mode

The configuration of the MCU in the WAIT mode

occurs as soon as the WAIT instruction is execut-

ed. The microcontroller can also be considered as

being in a “software frozen” state where the Core

stops processing the instructions of the routine,

the contents of the RAM locations and peripheral

registers are saved as long as the power supply

voltage is higher than the RAM retention voltage

but where the peripherals are still working. The

WAIT mode is used when the user wants to re-

duce the consumption of the MCU when it is in

idle, while not losing count of time or monitoring of

external events. The oscillator is not stopped in or-

der to provide clock signal to the peripherals. The

timers counting may be enabled (writing the PSI

bit in TSCR1 register) and the timer interrupt may

be also enabled before entering the WAIT mode;

this allows the WAIT mode to be left when timer in-

terrupt occurs. If the exit from the WAIT mode is

performed with a general RESET (either from the

activation of the external pin or by watchdog reset)

the MCU will enter a normal reset procedure as

described in the RESET chapter. If an interrupt is

generated during WAIT mode the MCU behaviour

depends on the state of the MCU Core before the

initialization of the WAIT sequence, but also of the

kind of the interrupt request that is generated. This

case will be described in the following paragraphs.

In any case, the MCU Core does not generate any

delay after the occurrence of the interrupt because

the oscillator clock is still available.

Non-maskable Interrupt Mode. If the WAIT in-

struction has been executed during the execution

of the non-maskable interrupt routine, the MCU

Core outputs from WAIT mode as soon as any in-

terrupt occurs: the instruction that follows the

WAIT instruction is executed and the MCU Core is

still in the non-maskable interrupt mode even if an-

other interrupt has been generated.

Normal Interrupt Mode. If the MCU Core was in

the interrupt mode before the initialization of the

WAIT sequence, it outputs from the wait mode as

soon as any interrupt occurs. Nevertheless, two

cases have to be considered:

– If the interrupt is a normal interrupt, the interrupt

routine in which the WAIT was entered will be

completed with the execution of the instruction

that follows the WAIT and the MCU Core is still in

the interrupt mode. At the end of this routine

pending interrupts will be serviced in accordance

to their priority.

– If the interrupt is a non-maskable interrupt, the

non-maskable routine is processed at first. Then,

the routine in which the WAIT was entered will be

completed with the execution of the instruction

that follows the WAIT and the MCU Core is still in

the normal interrupt mode.

3.3.2 STOP Mode

Notes:

Since the hardware activated watchdog is present

on the ST638x, the STOP instruction has been de-

activated. Any attempt to execute a STOP instruc-

tion will cause a WAIT instruction to be executed

instead.

If all the interrupt sources are disabled, the restart

of the MCU can only be done by a Reset activa-

tion. The Wait instruction is not executed if an en-

abled interrupt request is pending. In ST638x de-

vices, the hardware activated digital watchdog

function is present. As the watchdog is always ac-

tivated, the STOP instruction is de-activated and

any attempt to execute the STOP instruction will

cause an execution of a WAIT instruction.

3.3.3 Exit from WAIT Mode

The following paragraphs describe the output pro-

cedure of the MCU Core from WAIT mode when

an interrupt occurs. It must be noted that the re-

start sequence depends on the original state of the

MCU (normal, interrupt or non-maskable interrupt

21/82

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389

3.4 HARDWARE ACTIVATED DIGITAL WATCHDOG FUNCTION

The hardware activated digital watchdog function

consists of a down counter that is automatically in-

itialized after reset so that this function does not

need to be activated by the user program. As the

watchdog function is always activated this down

counter can not be used as a timer. The watchdog

is using one data space register (HWDR location

D8h). The watchdog register is set to FEh on reset

and immediately starts to count down, requiring no

software start. Similarly the hardware activated

watchdog can not be stopped or delayed by soft-

ware.

possibility to generate a reset in a time between

3072 to 196608 oscillator cycles in 64 possible

steps. (With a clock frequency of 8MHz this means

from 384ms to 24.576ms). The reset is prevented

if the register is reloaded with the desired value

before bits 2-7 decrement from all zeros to all

ones.

The presence of the hardware watchdog deacti-

vates the STOP instruction and a WAIT instruction

is automatically executed instead of a STOP. Bit 1

of the watchdog register (set to one at reset) can

be used to generate a software reset if cleared to

zero). Figure 17 shows the watchdog block dia-

gram while Figure 18 shows its working principle.

The watchdog time can be programmed using the

6 MSBs in the watchdog register, this gives the

Figure 17. Hardware Activated Watchdog Block Diagram

RESET

Q

RSFF

7

8

-2

SET

-12

R

DB1.7 LOAD SET

S

OSCILLATOR

CLOCK

8

DB0

WRITE

RESET

DATA BUS

VA00010

22/82

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389

HARDWARE ACTIVATED DIGITAL WATCHDOG FUNCTION (Cont’d)

Hardware Activated Watchdog Register

(HWDR)

Figure 18. Hardware Activated Watchdog

Working Principle

Address: D8h - Read/Write

Reset Value: 0FEh

D0

D1

D2

D3

D4

D5

D6

D7

BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

7

0

T1

T2

T3

T4

T5

T6

SR

C

T1-T6. These are the watchdog counter bits. It

should be noted that D7 (T1) is the LSB of the

counter and D2 (T6) is the MSB of the counter,

these bits are in the opposite order to normal.

RESET

SR. This bit is set to one during the reset phase

and will generate a software reset if cleared to ze-

ro.

C. This is the watchdog activation bit that is hard-

ware set. The watchdog function is always activat-

ed independently of changes of value of this bit.

The register reset value is FEh (Bit 1-7 set to one,

Bit 0 cleared).

8-BIT

DOWN COUNTER

OSC-12

VA00190

23/82

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389

3.5 INTERRUPT

The ST638x Core can manage 4 different maska-

ble interrupt sources, plus one non-maskable in-

terrupt source (top priority level interrupt). Each

source is associated with a particular interrupt vec-

tor that contains a Jump instruction to the related

interrupt service routine. Each vector is located in

the Program Space at a particular address (see

Table 7). When a source provides an interrupt re-

quest, and the request processing is also enabled

by the ST638x Core, then the PC register is load-

ed with the address of the interrupt vector (i.e. of

the Jump instruction). Finally, the PC is loaded

with the address of the Jump instruction and the

interrupt routine is processed.

3.5.1 Interrupt Vectors/Sources

The ST638x Core includes 5 different interrupt

vectors in order to branch to 5 different interrupt

routines. The interrupt vectors are located in the

fixed (or static) page of the Program Space.

The interrupt vector associated with the non-

maskable interrupt source is named interrupt vec-

tor #0. It is located at the (FFCh,FFDh) addresses

in the Program Space. This vector is associated

with the PC6/IRIN pin.

The interrupt vectors located at addresses (FF6h,

FF7h), (FF4h, FF5h), (FF2h, FF3h), (FF0h, FF1h)

are named interrupt vectors #1, #2, #3 and #4 re-

spectively. These vectors are associated with TIM-

The relationship between vector and source and

the associated priority is hardware fixed for the dif-

ferent ST638x devices. For some interrupt sourc-

es it is also possible to select by software the kind

of event that will generate the interrupt.

ER

2

(#1), VSYNC (#2), TIMER

1 (#3),

PC4(PWRIN) (#4) and ADC (#4).

Table 7. Interrupt Vectors/Sources

Relationships

All interrupts can be disabled by writing to the GEN

bit (global interrupt enable) of the interrupt option

register (address C8h). After a reset, ST638x is in

non maskable interrupt mode, so no interrupts will

be accepted and NMI flags will be used, until a

RETI instruction is executed. If an interrupt is exe-

cuted, one special cycle is made by the core, dur-

ing that the PC is set to the related interrupt vector

address. A jump instruction at this address has to

redirect program execution to the beginning of the

related interrupt routine. The interrupt detecting

cycle, also resets the related interrupt flag (not

available to the user), so that another interrupt can

be stored for this current vector, while its driver is

under execution.

Associated

Interrupt Source

Vector

Address

Vector

Interrupt

Vector # 0 (NMI)

1

PC6/IRIN Pin

Timer 2

0FFCh-0FFDh

0FF6h-0FF7h

0FF4h-0FF5h

0FF2h-0FF3h

0FF0h-0FF1h

Interrupt

Vector # 1

Interrupt

Vector #2

Vsync

Interrupt

Vector #3

Timer 1

Interrupt

Vector #4

PC4/PWRIN, ADC

Note 1. This pin is associated with the NMI Inter-

rupt Vector

If additional interrupts arrive from the same

source, they will be lost. NMI can interrupt other in-

terrupt routines at any time, while other interrupts

cannot interrupt each other. If more than one inter-

rupt is waiting for service, they are executed ac-

cording to their priority. The lower the number, the

higher the priority. Priority is, therefore, fixed. In-

terrupts are checked during the last cycle of an in-

struction (RETI included). Level sensitive inter-

rupts have to be valid during this period.

3.5.2 Interrupt Priority

The non-maskable interrupt request has the high-

est priority and can interrupt any other interrupt

routines at any time, nevertheless the other inter-

rupts cannot interrupt each other. If more than one

interrupt request is pending, they are processed

by the ST638x Core according to their priority lev-

el: vector #1 has the higher priority while vector #4

the lower. The priority of each interrupt source is

hardware fixed.

24/82

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389

INTERRUPTS (Cont’d)

3.5.3 Interrupt Option Register

Interrupt Option Register (IOR)

Address: (C8h) - Write only

Reset Value: X000XXXXb

The following list summarizes the interrupt proce-

dure (refer also to Figure 19*)

– Interrupt detection

– The flags C and Z of the main routine are ex-

changed with the flags C and Z of the interrupt

routine (resp. the NMI flags)

7

0

– The value of the PC is stored in the first level of

the stack - The normal interrupt lines are inhibit-

ed (NMI still active)

-

EL1 ES2 GEN

The Interrupt Option Register (IOR register, loca-

tion C8h) is used to enable/disable the individual in-

terrupt sources and to select the operating mode of

theexternalinterruptinputs.Thisregistercanbead-

dressed in the Data Space as RAM location at the

C8h address, nevertheless it is a write-only register

that can not be accessed with single-bit operations.

The operating modesoftheexternal interruptinputs

associated to interrupt vectors #1 and #2 are se-

lected through bits 5 and 6 of the IOR register.

– The edge flip-flop is reset

– The related interrupt vector is loaded in the PC.

– User selected registers are saved inside the in-

terrupt service routine (normally on a software

stack)

– The source of the interrupt is found by polling (if

more than one source is associated to the same

vector)

Caution: This register contains at least one write

only bit. Single bit instructions (SET, RES, INC

and DEC) should not be used.

– Interrupt servicing

– Return from interrupt (RETI)

– Automatically the ST638x core switches back to

the normal flags (resp the interrupt flags) and

pops the previous PC value from the stack

D7. Not used.

EL1. This is the Edge/Level selection bit of inter-

rupt #1. When set to one, the interrupt is generat-

ed on low level of the related signal; when cleared

to zero, the interrupt is generated on falling edge.

The bit is cleared to zero after reset.

Figure 19. Interrupt Processing Flow-Chart

INSTRUCTION

ES2. This is the edge selection bit on interrupt #2.

This bit is used on the ST638x devices with on-

chip OSD generator for VSYNC detection. When

this bit is se to one, the interrupt #2 is positive

edge sensitive, when cleared to zero the negative

edge sensitive interrupt is selected.

FETCH

INSTRUCTION

EXECUTE

INSTRUCTION

GEN. This is the global enable bit. When set to

one all interrupts are globally enabled; when this

bit is cleared to zero all interrupts are disabled (ex-

cluding NMI).

LOAD PC FROM

INTERRUPT VECTOR

NO

WAS

(FFC/FFD)

THE INSTRUCTION

A RETI ?

YES

IS THE CORE

ALREADY IN

NORMAL MODE?

SET

YES

D3 - D0. These bits are not used.

INTERRUPT MASK

?

3.5.4 Interrupt Procedure

NO

The interrupt procedure is very similar to a call pro-

cedure; the user can consider the interrupt as an

asynchronous call procedure. As this is an asyn-

chronous event the user does not know about the

context and the time atwhich it occurred. As a result

the user should save all the data space registers

which will be used inside the interrupt routines.

There are separate sets of processor flags for nor-

mal, interrupt and non-maskable interrupt modes

which are automatically switched and so these do

not need to be saved.

CLEAR

INTERRUPT MASK

PUSH THE

PC INTO THE STACK

SELECT

PROGRAM FLAGS

SELECT

INTERNAL MODE FLAG

“POP”

THE STACKED PC

CHECK IF THERE IS

AN INTERRUPT REQUEST

AND INTERRUPT MASK

NO

?

YES

VA000014

25/82

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389

INTERRUPTS (Cont’d)

The interrupt routine begins usually by the identifi-

cation of the device that has generated the inter-

rupt request. The user should save the registers

which are used inside the interrupt routine (that

holds relevant data) into a software stack. After the

RETI instruction execution, the Core carries out

the previous actions and the main routine can con-

tinue.

latched signal is to service the interrupt. Care must

be taken not to generate spurious interrupts. This

interrupt may be used to synchronize the VSYNC

signal in order to change characters in the OSD

only when the screen is on vertical blanking (if de-

sired). This method may also be used to blink

characters.

TIMER 1 Interrupt (#3). The TIMER 1 Interrupt is

connected to the fourth interrupt #3 (0FF2h) which

detects a low level (latched in the timer).

3.5.5 ST638x Interrupt Details

IR Interrupt (#0). The IRIN/PC6 Interrupt is con-

nected to the first interrupt #0 (NMI, 0FFCh). If the

IRINT interrupt is disabled at the Latch circuitry,

then it will be high. The #0 interrupt input detects a

high to low level. Note that once #0 has been

latched, then the only way to remove the latched

#0 signal is to service the interrupt. #0 can inter-

rupt the other interrupts. A simple latch is provided

from the PC6(IRIN) pin in order to generate the IR-

INT signal. This latch can be triggered by either

the positive or negative edge of IRINT signal. IR-

INT is inverted with respect to the latch. The latch

can be read by software and reset by software.

PWR and ADC Interrupt (#4). The PWR and An-

alog to Digital Converter Interrupts are connected

by a logical AND to the fifth interrupt #4 (0FF0h). If

the PWRINT is disabled at the PWR circuitry, then

it will be high. The #4 interrupt input detects a low

level. A simple latch is provided from the PC4

(PWRIN) pin in order to generate the PWRINT sig-

nal. This latch can be triggered by either the posi-

tive or negative edge of the PWRIN signal.

PWRINT is inverted with respect to the latch. The

latch can be reset by software.

Notes: Global disable does not reset edge sensi-

tive interrupt flags. These edge sensitive interrupts

become pending again when global disabling is re-

leased. Moreover, edge sensitive interrupts are

stored in the related flags also when interrupts are

globally disabled, unless each edge sensitive in-

terrupt is also individually disabled before the in-

terrupting event happens. Global disable is done

by clearing the GEN bit of Interrupt option register,

while any individual disable is done in the control

register of the peripheral. The on-chip Timer pe-

ripherals have an interrupt request flag bit (TMZ),

this bit is set to one when the device wants to gen-

erate an interrupt request and a mask bit (ETI) that

must be set to one to allow the transfer of the flag

bit to the Core.

TIMER 2 Interrupt (#1). The TIMER 2 Interrupt is

connected to the interrupt #1 (0FF6h). The TIMER

2 interrupt generates a low level (which is latched

in the timer). Only the low level selection for #1 can

be used. Bit 6 of the interrupt option register C8h

has to be set.

VSYNC Interrupt (#2). The VSYNC Interrupt is

connected to the interrupt #2. When disabled the

VSYNC INT signal is low. The VSYNC INT signal

is inverted with respect to the signal applied to the

VSYNC pin. Bit 5 of the interrupt option register

C8h is used to select the negative edge (ES2=0)

or the positive edge (ES2=1); the edge will depend

on the application. Note that once an edge has

been latched, then the only way to remove the

26/82

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389

Figure 20. Interrupt circuit diagram

VDD

DLCR Bit 2

FF

CLK

CLR

FF

CLK

CLR

P

INT #0 - NMI (FFC,D)

C6

/IRIN

Q

DLCR Bit 1

I Start

DLCR Bit 3

0

FF

TIM

TSCR2 B it 6

E R 2

0

CLK

Q

CLR

INT #

1 (FF6,7)

MUX

1

I

Start

1

RESTART

FROM

Bit 6

IOR

STOP/WAIT

V

DD

NPVIR Bit

6

FF

CLK

CLR

INT #2 (FF4,5)

Q

VSYNC

OR

I

Bit 5

I

Start

2

V

DD

TIMER 1

TSCR1 Bit 6

INT #3 (FF2,3)

INT #4 (FF0,1)

ADC

ADCR Bit 7

FF

CLK

CLR

Q

DLCR Bit 5

PC4/PWRIN

DLCR Bit 4

DLCR Bit 6

IOR B

it

4 : GEN

27/82

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389

4 ON-CHIP PERIPHERALS

4.1 I/O PORTS

The ST638x microcontrollers use three standard I/

O ports (A,B,C) with up to eight pins on each port;

refer to the device pin configurations to see which

pins are available.

and Direction registers are associated with the PA0

line of Port A).

There are three Data registers (DRA, DRB, DRC),

that are used to read the voltage level values of the

lines programmed in the input mode, or to write the

logicvalueofthesignaltobeoutputonthe linescon-

figured in the output mode. The port Data Registers

can be read to get the effective logic levels of the

pins, but they can be also written by the user soft-

ware, in conjunction with the related Data Direction

Register and the Option Register (Port B only), to

select the different input mode options. Single-bit

operations on I/O registers (bit set/reset instruc-

tions) are possible but care is necessary because

reading in input mode is made from I/O pins and

therefore might be influenced by the external load,

while writing will directly affect the Port data register

causing an undesired changes of the input config-

uration. The three Data Direction registers (DDRA,

DDRB, DDRC) allow the selection of the direction

of each pin (input or output).

Each line can be individually programmed either in

the input mode or the output mode as follows by

software.

– Output

– Input with on-chip pull-up resistor (selected by

software)

– Input without on-chip pull-up resistor (selected

by software)

– Analog inputs (PB0-PB6)

Note: pins with 12V open-drain capability do not

have pull-up resistors.

In output mode the following hardware configura-

tions are available:

– Open-drain output 12V (PA4-PA7, PC4-PC7)

– Open-drain output 5V (PC0-PC3, PB0-PB6)

– Push-pull output (PA0-PA3, PB0-PB6)

All the I/O registers can be read or written as any

other RAM location of the data space, so no extra

RAM cell is needed for port data storing and ma-

nipulation. During the initialization of the MCU, all

theI/Oregistersareclearedandtheinputmodewith

pull-up is selected on all the pins thus avoiding pin

conflicts(with the exception of PC2 thatisset in out-

put mode and is set high i.e. high impedance).

The lines are organized in three ports (port A,B,C).

The ports occupy 7 registers in the data space.

Each bit of these registers is associated with a par-

ticular line (for instance, the bits 0 of the Port A Data

28/82

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389

I/O PORTS (Cont’d)

4.1.1 Details of I/O Ports

In this case the final signal on the output pin is

equivalent to a wired AND with the programmed

When programmed as an input a pull-up resistor (if

available) can be switched active under program

control. When programmed as an output the I/O

port will operate either in the push-pull mode or the

open-drain mode according to the hardware fixed

configuration as specified below.

data output.

If the user needs to use the serial peripheral, the I/

O line should be set in output mode while the

open-drain configuration is hardware fixed; the

corresponding data bit must set to one. If the

latched interrupt functions are used (IRIN,

PWRIN) then the corresponding pins should be

set to input mode.

Port A. PA0-PA3 are available as push-pull when

outputs. PA4-PA7 are available as open-drain (no

push-pull programmability) capable of withstand-

ing 12V (no resistive pull-up in input mode). PA6-

PA7 has been specially designed for higher driving

capability and are able to sink 25mA with a maxi-

mum VOL of 1V.

On ST638x the I/O pins with double or special

functions are:

– PC0/SCL (connected to the SPI clock signal)

– PC1/SDA (connected to the SPI data signal)

– PC3/SEN (connected to the SPI enable signal)

Port B. All lines are available as open drain, push-

pull when outputs or analog input.

– PC4/PWRIN (connected to the PWRIN interrupt

latch)

Port C. PC0-PC3 are available as open-drain ca-

pable of withstanding a maximum VDD+0.3V.

PC4-PC7 are avail-able as open-drain capable of

withstanding 12V (no resistive pull-up in input

mode). Some lines are also used as I/O buffers for

signals coming from the on-chip SPI.

– PC6/IRIN (connected to the IRIN interrupt latch)

All the Port A,B and C I/O lines have Schmitt-trig-

ger input configuration with a typical hysteresis of

1V.

Table 8. I/O Port Options Selection (Port A)

DDR

DR

0

Mode

Input

Option

With on-chip pull-up resistor

0

1

Input

Without on-chip pull-up resistor

Output open-drain or push-pull

X

Output

Note X: Means don’t care.

Table 9. I/O Port Options Selection (Port B)

DDR

OR

0

DR

0

Mode

Input

Option

With on-chip pull-up resistor

Without on-chip pull-up resistor

Analog input

0

1

0

1

Input

1

Input

0

x

Output

Open-drain output

1

X

Push-pull output

Note X: Means don’t care.

29/82

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389

I/O PORTS (Cont’d)

Table 10. I/O Port Option

MODE

AVAILABLE ON⁽¹⁾

SCHEMATIC

VDD

PA0-PA3

Input

PB0-PB6

PC0-PC3

Data in

VDD

PA0-PA3

PB0-PB6

PC0-PC3

Input

with pull up

Data in

VDD

Analog input

PB0-PB6

ADC

Open drain output

5mA/5V

PC0-PC3

PA4-PA5

PB0-PB6

PC4-PC7

PA6-PA7

Open drain output

5mA / 12V

Data out

Open drain output

25mA/12V

VDD

Push-pull output

5mA

PB0-PB6

PA0-PA3

Data out

Push-pull output

10mA

Note 1. Provided the correct configuration has been selected.

30/82

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389

I/O PORTS (Cont’d)

4.1.2 I/O Pin Programming

PA7-PA0. These are the I/O port A data bits. Re-

set at power-on.

Each pin can be individually programmed as input

or output with different input and output configura-

tions. This is achieved by writing to the relevant bit

in the data (DR) and data direction register (DDR).

Table 11 shows all the port configurations that can

be selected by the user software.

PB6-PB0. These are the I/O port B data bits. Re-

set at power-on.

PC7-PC0. Set to 04h at power-on. Bit 2 (PC2 pin)

is set to one (open drain therefore high imped-

ance).

4.1.3 Input/Output Configurations

4.1.4.2 Data Direction Registers

The Table 9 shows the I/O lines hardware configu-

ration for the different options.

Port A, B, C Data Direction Register

Address: C4h (PA), C5h (PB), C6h (PC) - Read/

Write

Notes: The WAIT instruction allows the ST638x to

be used in situations where low power consump-

tion is needed. This can only be achieved however

if the I/O pins either are programmed as inputs

with well defined logic levels or have no power

consuming resistive loads in output mode. As the

same die is used for the different ST638x versions

the unavailable I/O lines of ST638x should be pro-

grammed in output mode.

Reset value:00h

7

0

PA/

PB/

PC6

PA/

PB/

PC5

PA/

PB/

PC4

PA/

PB/

PC3

PA/

PB/

PC2

PA/

PB/

PC1

PA/

PB/

PC0

PA/

PC7

PA7-PA0. These are the I/O port A data direction

bits. When a bit is cleared to zero the related I/O

line is in input mode, if bit is set to one the related

I/O line is in output mode. Reset at power-on.

Single-bit operations on I/O registers are possible

but care is necessary because reading in input

mode is made from I/O pins while writing will di-

rectly affect the Port data register causing an un-

desired changes of the input configuration.

PB6-PB0. These are the I/O port B data direction

bits. When a bit is cleared to zero the related I/O

line is in input mode, if bit is set to one the related

I/O line is in output mode. Reset at power-on.

Table 11. I/O Port Options Selection (Port C)

DDR

DR

0

Mode

Option

PC7-PC0. These are the I/O port C data direction

bits. When a bit is cleared to zero the related I/O

line is in input mode, if bit is set to one the related

I/O line is in output mode. Set to 04h at power-on.

Bit 2 (PC2 pin) is set to one (output mode select-

ed).

0

1

Input

With on-chip pull-up resistor

1

Input Without on-chip pull-up resistor

X

Output Open-drain

Note: X. Means don’t care.

4.1.4 I/O Port Registers

4.1.4.1 Data Registers

4.1.4.3 Data Direction Registers

Port B Option Register

Address: CDh - Read/Write

Reset value:00h

Ports A, B, C Data Register

Address: C0h (PA), C1h (PB), C2h (PC) - Read/

Write

Reset Value: 00h

7

0

7

0

PB6

PB5

PB4

PB3

PB2

PB1

PB0

PA/

PB/

PC6

PA/

PB/

PC5

PA/

PB/

PC4

PA/

PB/

PC3

PA/

PB/

PC2

PA/

PB/

PC1

PA/

PB/

PC0

PA/

PC7

PB6-PB0. These are the I/O port B data direction

bits. If bit is set to one the related I/O line is in an-

alog input mode. Reset at power-on.

31/82

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389

4.2 TIMERS

The ST638x devices offer two on-chip Timer pe-

ripherals consisting of an 8-bit counter with a 7-bit

programmable prescaler, thus giving a maximum

The prescaler decrements on rising edge. The

prescaler input is the oscillator frequency divided

by 12. Depending on the division factor pro-

grammed by PS2/PS1/PS0 (see Table 12) bits in

the TSCR, the clock input of the timer/counter reg-

ister is multiplexed to different sources. On divi-

sion factor 1, the clock input of the prescaler is

also that of timer/counter; on factor 2, bit 0 of pres-

caler register is connected to the clock input of

TCR.

15

count of 2 , and a control logic that allows config-

uration the peripheral operating mode. Figure 21

shows the Timer block diagram. The content of the

8-bit counters can be read/written in the Timer/

Counter registers TCR that are addressed in the

data space as RAM locations at addresses D3h

(Timer 1), DBh (Timer 2). The state of the 7-bit

prescaler can be read in the PSC register at ad-

dresses D2h (Timer 1) and DAh (Timer 2). The

control logic is managed by TSCR registers at D4h

(Timer 1) and DCh (Timer 2) addresses as de-

scribed in the following paragraphs.

This bit changes its state with the half frequency of

prescaler clock input. On factor 4, bit 1 of PSC is

connected to clock input of TCR, and so on. On di-

vision factor 128, the MSB bit 6 of PSC is connect-

ed to clock input of TCR. The prescaler initialize bit

(PSI) in the TSCR register must be set to one to al-

low the prescaler (and hence the counter) to start.

If it is cleared to zero then all of the prescaler bits

are set to one and the counter is inhibited from

counting.The prescaler can be given any value be-

tween 0 and 7Fh by writing to the related register

address, if bit PSI in the TSCR register is set to

one. The tap of the prescaler is selected using the

PS2/PS1/PS0 bits in the control register. Figure 22

illustrates the Timer working principle.

The following description applies to all Timers. The

8-bit counter is decrement by the output (rising

edge) coming from the 7-bit prescaler and can be

loaded and read under program control. When it

decrements to zero then the TMZ (timer zero) bit in

the TSCR is set to one. If the ETI (enable timer in-

terrupt) bit in the TSCR is also set to one an inter-

rupt request, associated to interrupt vector #3 for

Timer 1 and #1 for Timer 2, is generated. The in-

terrupt of the timer can be used to exit the MCU

from the WAIT mode.

Figure 21. Timer Peripheral Block Diagram

DATABUS 8

8

6

5

4

3

2

b7

b5

b1

b0

b6

b4

b3

b2

8-BIT

COUNTER

STATUS/CONTROL

REGISTER

SELECT

1 OF 8

PSC

ETI TOUT

TMZ

PSI

PS1

PS0

DOUT

PS2

1

0

3

TIMER

INTERRUPT

LINE

LATCH

SYNCHRONIZATION

LOGIC

:12

f_OSC

VA00009

32/82

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389

TIMERS (Cont’d)

4.2.1 Timer Operating Modes

Since in the ST638x devices the external TIMER

pin is not connected, the only allowed operating

mode is the output mode, which is selected by set-

ting bit 4 and by clearing bit 5 in the TSCR1 regis-

ter. This procedure will enable Timer 1 and

Timer 2.

vector #1 (for Timer 2) is generated. When the

counter decrements to zero also the TMZ bit in the

TSCR register is set to one.

Notes:

TMZ is set when the counter reaches 00h; howev-

er, it may be set by writing 00h in the TCR register

or setting the bit 7 of the TSCR register. TMZ bit

must be cleared by user software when servicing

the timer interrupt to avoid undesired interrupts

when leaving the interrupt service routine. After re-

set, the 8-bit counter register is loaded to FFh

while the 7-bit prescaler is loaded to 7Fh, and the

TSCR register is cleared which means that timer is

stopped (PSI=0) and timer interrupt disabled.

Output Mode (TSCR1 D4 = 1, TSCR1 D5 = 0). On

this mode the timer prescaler is clocked by the

prescaler clock input (OSC/12). The user can se-

lect the desired prescaler division ratio through the

PS2/PS1/PS0 bits. When TCR count reaches 0, it

sets the TMZ bit in the TSCR.

The TMZ bit can be tested under program control

to perform timer functions whenever it goes high.

Bits D4 and D5 on TSCR2 (Timer 2) register are

not implemented.

A write to the TCR register will predominate over

the 8-bit counter decrement to 00h function, i.e. if a

write and a TCR register decrement to 00h occur

simultaneously, the write will take precedence,

and the TMZ bit is not set until the 8-bit counter

reaches 00h again. The values of the TCR and the

PSC registers can be read accurately at any time.

Timer Interrupt

When the counter register decrements to zero and

the software controlled ETI (enable timer interrupt)

bit is set to one then an interrupt request associat-

ed to interrupt vector #3 (for Timer 1), to interrupt

Figure 22. Timer Working Principle

7-BIT PRESCALER

BIT3

BIT0

BIT1

BIT2

BIT4

BIT5

BIT6

CLOCK

PS0

PS1

PS2

0

1

2

4

7

3

5

6

8-1 MULTIPLEXER

BIT7

BIT2

BIT0

BIT1

BIT3

BIT4

BIT5

BIT6

8-BIT COUNTER

VA00186

33/82

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389

TIMERS (Cont’d)

4.2.2 Timer Status Control Registers (TSCR)

Timers 1 and 2

The TSCR1 and TSCR2 registers are cleared on

reset. The correct D4-D5 combination must be

written in TSCR1 by user's software to enable the

operation of Timer 1 and 2.

Address: D4h (Timer 1), DCh (Timer 2) - Read/

Write

Table 12. Prescaler Division Factors

Reset Value: 00h

PS2

0

PS1

0

PS0

0

Divided By

7

0

1

2

TMZ

ETI

D5

D4

PSI

PS2

PS1

PS0

0

1

0

1

0

4

TMZ. Low-to-high transition indicates that the tim-

er count register has decremented to zero. This bit

must be cleared by user software before to start

with a new count.

0

1

8

1

0

16

32

64

128

1

0

1

0

ETI. This bit, when set, enables the timer interrupt

(vector #3 for Timer 1, vector #2 for Timer 2 re-

quest). If ETI=0 the timer interrupt is disabled. If

ETI= 1 and TMZ= 1 an interrupt request is gener-

ated.

1

4.2.3 Timer Counter Registers (TCR)

Timer Counter 1 and 2

D5. This is the timers enable bit D5. It must be

cleared to 0 together with a set to 1 of bit D4 to en-

able Timer 1 and Timer 2 functions. It is not imple-

mented on registers TSCR2.

Address: D3h (Timer Counter 1), DBh (Timer

Counter 2) - Read/Write

Reset Value: FFh

D4. This is the timers enable bit D4. This bit must

be set to 1 together with a clear to 0 of bit D5 to en-

able all Timers (Timer 1 and 2) functions. It is not

implemented on registers TSCR2.

7

0

D7

D6

D5

D4

D3

D2

D1

D0

D5

0

D4

0

Timers

Disabled

Enabled

Reserved

Bit 7-0 = D7-D0: Counter Bits.

0

1

4.2.4 Timer Prescaler Registers (PSCR)

Timer Prescalers 1 and 2

1

X

Address: D2h (Timer Prescaler 1), DAh (Timer

Prescaler 2) - Read/Write

PSI. Used to initialize the prescaler and inhibit its

counting while PSI = 0 the prescaler is set to 7Fh

and the counter is inhibited. When PSI = 1 the

prescaler is enabled to count downwards. As long

as PSI= 0 both counter and prescaler are not run-

ning.

Reset Value: 7Fh

7

0

D7

D6

D5

D4

D3

D2

D1

D0

PS2-PS0. These bits select the division ratio of the

prescaler register. (see Table 12)

Bit 7 = D7: Always read as "0".

Bit 6-0 = D6-D0: Prescaler Bits.

34/82

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389

4.3 SERIAL PERIPHERAL INTERFACE

The ST638x Serial Peripheral Interface (SPI) has

been designed to be cost effective and flexible in

interfacing the various peripherals in TV applica-

tions.

– On S-BUS by a transition of the SEN line (1 to 0

Start, 0 to 1 Stop) while the SCL line is at high

level.

2

– On I C BUS by a transition of the SDA line (10

It maintains the software flexibility but adds hard-

ware configurations suitable to drive devices

which require a fast exchange of data. The three

pins dedicated for serial data transfer (single mas-

ter only) can operate in the following ways:

Start, 01Stop) while the SCL line is at high level.

Start and Stop condition are always generated by

the master (ST638x SPI can only work as single

master). The bus is busy after the start condition

and can be considered again free only when a cer-

tain time delay is left after the stop condition. In the

S-BUS configuration the SDA line is only allowed

to change during the time SCL line is low. After the

start information the SEN line returns to high level

and remains unchanged for all the data transmis-

sion time. When the transmission is completed the

SDA line is set to high level and, at the same time,

the SEN line returns to the low level in order to

supply the stop information with a low to high tran-

sition, while the SCL line is at high level. On the S-

– as standard I/O lines (software configuration)

2

– as S-BUS or as I C BUS (two pins)

– as standard (shift register) SPI

When using the hardware SPI, a fixed clock rate of

62.5kHz is provided. It has to be noted that the first

bit that is output on the data line by the 8-bit shift

register is the MSB.

2

4.3.1 S-BUS/I C BUS Protocol Information

2

The S-BUS is a three-wire bidirectional data-bus

BUS, as on the I C BUS, each eight bit information

2

with functional features similar to the I C BUS. In

(byte) is followed by one acknowledged bit which

is a high level put on the SDA line by the transmit-

ter. A peripheral that acknowledges has to pull

down the SDA line during the acknowledge clock

pulse. An addressed receiver has to generate an

acknowledge after the reception of each byte; oth-

erwise the SDA line remains at the high level dur-

ing the ninth clock pulse time. In this case the mas-

ter transmitter can generate the Stop condition, via

fact the S-BUS includes decoding of Start/Stop

conditions and the arbitration procedure in case of

multimaster system configuration (the ST638x SPI

allows a single-master only operation). The SDA

2

line, in the I C BUS represents the AND combina-

tion of SDA and SEN lines in the S-BUS. If the

SDA and the SEN lines are short-circuit connect-

2

ed, they appear as the SDA line of the I C BUS.

2

The Start/Stop conditions are detected (by the ex-

the SEN (or SDA in I C BUS) line, in order to abort

2

ternal peripherals suited to work with S-BUS/I C

the transfer.

BUS) in the following way:

35/82

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389

SERIAL PERIPHERAL INTERFACE (Cont’d)

Start/Stop Acknowledge. The timing specs of the

a. an optional data byte to address (if needed) the

S-BUS protocol require that data on the SDA (only

slave location to be written (it can be a word

address in a memory or a register address,

etc.).

2

on this line for I C BUS) and SEN lines be stable

during the “high” time of SCL. Two exceptions to

this rule are foreseen and they are used to signal

the start and stop condition of data transfer.

b. a “data” byte which will be written at the

address given in the previous byte.

– On S-BUS by a transition of the SEN line (10

Start, 01 Stop) while the SCL line is at high level.

c. further data bytes.

d. a STOP condition

2

– On I C BUS by a transition of the SDA line (10

A data transfer is always terminated by a stop con-

dition generated from the master. The ST638x pe-

ripheral must finish with a stop condition before

another start is given. Figure 23 shows an exam-

ple of write operation.

Start, 01 Stop) while the SCL line is at high level.

Data are transmitted in 8-bit groups; after each

group, a ninth bit is interposed, with the purpose of

acknowledging the transmitting sequence (the

transmit device place a “1” on the bus, the ac-

knowledging receiver a “0”).

2. R/W = “1” (Read)

In this case the slave acts as transmitter and,

therefore, the transmission direction is changed. In

read mode two different conditions can be consid-

ered:

Interface Protocol. This paragraph deals with the

description of data protocol structure. The inter-

face protocol includes:

– A start condition

a. The master reads slave immediately after first

byte. In this case after the slave address sent

from the master with read condition enabled the

master transmitter becomes master receiver

and the slave receiver becomes slave transmit-

ter.

– A “slave chip address” byte, transmitted by the

master, containing two different information:

a. the code identifying the device the master

wants to address (this information is present in

the first seven bits)

b. the direction of transmission on the bus (this

information is given in the 8th bit of the byte);

“0” means “Write”, that is from the master to the

slave, while “1” means “Read”. The addressed

slave must always acknowledge.

b. The master reads a specified register or loca-

tion of the slave. In this case the first sent byte

will contain the slave address with write condi-

tion enabled, then the second byte will specify

the address of the register to be read. At this

moment a new start is given together with the

slave address in read mode and the procedure

will proceed as described in previous point “a”.

The sequence from, now on, is different according

to the value of R/W bit.

1. R/W = “0” (Write)

In all the following bytes the master acts as trans-

mitter; the sequence follows with:

36/82

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389

SERIAL PERIPHERAL INTERFACE (Cont’d)

Figure 23. I²C Master Transmit to Slave Receiver (Write Mode)

ACKNOWLEDGE

FROM SLAVE

ACKNOWLEDGE

FROM SLAVE

ACKNOWLEDGE

FROM SLAVE

MSB

S

SLAVE ADDRESS

O

A

WORD ADDRESS

A

DATA

A

P

START

R/W

STOP

Figure 24. I²C Master Reads Slave Immediately After First Byte (Read Mode)

ACKNOWLEDGE

FROM SLAVE

ACKNOWLEDGE

FROM MASTER

NO ACKNOWLEDGE

FROM MASTER

MSB

A

MSB

S

SLAVE ADDRESS

1

A

DATA

1

P

DATA

START

R/W

n BYTES

STOP

Figure 25. I²C Master Reads After Setting Slave Register Address (Write Address, Read Data)

ACKNOWLEDGE

FROM SLAVE

ACKNOWLEDGE

FROM SLAVE

S

SLAVE ADDRESS

0

A

X

WORD ADDRESS

A

P

START

R/W

STOP

ACKNOWLEDGE

FROM SLAVE

ACKNOWLEDGE

FROM MASTER

NO ACKNOWLEDGE

FROM MASTER

MSB

S

SLAVE ADDRESS

1

A

DATA

1

P

DATA

START

R/W

STOP

37/82

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389

SERIAL PERIPHERAL INTERFACE (Cont’d)

2

4.3.2 S-BUS/I C BUS Timing Diagrams

quencies up to 62.5KHz, either by being able to

2

transmit or receive at that speed or by applying the

clock synchronization procedure which will force

the master into a wait state and stretch low peri-

ods.

The clock of the S-BUS/I C BUS of the ST638x

SPI (single master only) has a fixed bus clock fre-

quency of 62.5KHz. All the devices connected to

the bus must be able to follow transfers with fre-

Figure 26. S-BUS Timing Diagram

SCL

1

2

5

6

7

A

0

3

4

SEN (TRANSMIT)

SDA (TRANSMIT)

^ ^ ^

SDA pulled low by receiver

if acknowledged.

SEN (RECEIVE)

SDA (RECEIVE)

^ ^ ^

SDA pulled low by SPI Peripheral.

SCL

1

2

5

6

7

A

0

3

4

SEN (START)

SDA (START)

^ ^ ^

SDA pulled low by receiver

if acknowledged.

SCL

1

2

5

6

7

A

0

3

4

SEN (STOP)

SDA (STOP)

^ ^ ^

SDA pulled low by receiver if acknowledge. If in receive then there

will be no ACK. by the SPI.

VA00454

2

Note: The third pin, SEN, should be high; it is not used in the I C BUS. Logically SDA is the AND of the

S-BUS SDA and SEN.)

38/82

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389

SERIAL PERIPHERAL INTERFACE (Cont’d)

2

Figure 27. I C BUS Timing Diagram

SCL

0

1

2

3

4

5

6

7

A

SDA (TRANSMIT)

SDA pulled low by receiver

if acknowledged.

SDA (RECEIVE)

SDA pulled low by SPI Peripheral.

SCL

0

1

2

3

5

6

7

A

SDA (START)

SDA pulled low by receiver

if acknowledged.

SCL

0

1

2

3

4

5

6

7

A

SDA (STOP)

SDA pulled low by receiver if acknowledge. If in receive then there

will be no ACK. by the SPI.

VA00455

2

Note: The third pin, SEN, should be high; it is not used in the I C BUS. Logically SDA is the AND of the

S-BUS SDA and SEN.)

39/82

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389

SERIAL PERIPHERAL INTERFACE (Cont’d)

2

4.3.3 Compatibility S-BUS/I C BUS

Figure 28 (a and b). It is also possible to use mixed

S-BUS/I C BUS protocols as showed in Figure 28

2

Using the S-BUS protocol it is possible to imple-

ment mixed system including S-BUS/I C BUS bus

peripherals. In order to have the compatibility with

the I C BUS peripherals, the devices including the

S-BUS interface must have their SDA and SEN

pins connected together as shown in the following

2

(c). S-BUS peripherals will only react to S-BUS

2

protocol signals, while I C BUS peripherals will

2

only react to I C BUS signals. Multimaster config-

uration is not possible with the ST63xx SPI (single

master only).

2

Figure 28. S-BUS/ I C BUS Mixed Configurations

SCL

SDA

SEN

SCL

SDA

SEN

SCL

SDA

SEN

SCL

SDA

SEN

2

ST6 I C-BUS

PROTOCOL

ST6 S-BUS

PROTOCOL

SCL

SDA

SCL

SDA

2

I C-BUS

SLAVE

I C-BUS

SLAVE

VA00457

VA00456

a

b

SCL

SDA

SEN

SCL

SDA

SEN

ST6

2

S-BUS/I C-BUS

PROTOCOL

SCL

SDA

2

I C-BUS

SLAVE

VA00452

c

40/82

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389

SERIAL PERIPHERAL INTERFACE (Cont’d)

4.3.4 STD SPI Protocol (Shift Register)

ter 1 (SCR1 Add. EBh). Bit 0 named I2C must be

set at one and bit 1 named STD must be reset.

When the standard bus protocol is selected bit 2 of

2

This protocol is similar to the I C BUS with the ex-

ception that there is no acknowledge pulse and

there are no stop or start bits. The clock cannot be

slowed down by the external peripherals.

the SCR1 is meaningless.

2

This bit named STOP bit is used only in I C BUS

or SBUS. However take care that THE STOP BIT

MUST BE RESET WHEN THE STANDARD PRO-

TOCOL IS USED. This bit is set to ZERO after RE-

SET.

In this case all three outputs should be high in or-

der not to lock the software I/Os from functioning.

SPI Standard Bus Protocol: The standard bus pro-

tocol is selected by loading the SPI Control Regis-

Figure 29. Software Bus (Hardware Bus Disabled) Timing Diagram

CLOCK

(was SCL)

0

1

2

3

4

5

6

7

IDENT (was SEN, this is optionally controlled by software; output

as far as hardware is concerned is high).

DATA

(was SDA, TRANSMIT)

DATA

(was SDA, RECEIVE)

VA00453

4.3.5 SPI Data/Control Register

SPI Serial Data Register (SSDR)

Address: CCh - Read/Write

Reset Value: XXh

For I/O details on SCL (Serial Clock), SDA (Serial

Data) and SEN (Serial Enable) please refer to I/O

Ports description with reference to the following

registers:

7

0

Port C data register, Address C2h (Read/Write).

- BIT D0 “SCL”

SSDR SSDR SSDR SSDR SSDR SSDR SSDR SSDR

7

6

5

4

3

2

1

0

- BIT D1 “SDA”

SSDR7-0. These are the SPI data bits. They can

be neither read nor written when SPI is operating

(BUSY bit set). They are undefined after reset.

- BIT D3 “SEN”

Port C data direction register, Address C6h (Read/

Write).

41/82

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389

SERIAL PERIPHERAL INTERFACE (Cont’d)

SPI Control Register 1 (SCR1)

Address: EBh - Write only

Reset Value: 00h

SPI Control Register 2 (SCR2)

Address: ECh - Read/Write

Reset Value: 00h

7

0

7

0

STD/

SPI

S-BUS/

2

-

TX/RX VRY/S ACN

BSY

-

STR

STP

I CBUS

Caution: This register contains at least one write

only bit. Single bit instructions (SET, RES, INC

and DEC) should not be used.

Caution: This register contains at least one write

only bit. Single bit instructions (SET, RES, INC

and DEC) should not be used.

b7-b4. These bits are not used.

2

TX/RX. Write Only. When this bit is set, current

byte operation is a transmission. When it is reset,

current operation is a reception. Set to zero after

reset.

STR. This is Start bit for I C BUS/S-BUS. This bit

is meaningless when STD/SPI enable bit is

cleared to zero. If this bit is set to one and STD/SPI

bit is also set to “1” then SPI Start generation, be-

fore beginning of transmission, is enabled. Set to

zero after reset.

VRY/S. Read Only/Write Only. This bit has two dif-

ferent functions in relation to read or write opera-

tion. Reading Operation: when STD and/or TRX

bits is cleared to 0, this bit is meaningless. When

bits STD and TX are set to 1, this bit is set each

time BSY bit is set. This bit is reset during byte op-

eration if real data on SDA line are different from

the output from the shift register. Set to zero after

reset. Writing Operation: it enables (if set to one)

or disables (if cleared to zero) the interrupt coming

from VSYNC pin. Undefined after reset. Refer to

OSD description for additional information.

2

STP. This is Stop bit for I C BUS/S-BUS. This bit

is meaningless when STD/SPI enable bit is

cleared to zero. If this bit is set to one and STD/SPI

bit is also set to “1” then SPI Stop condition gener-

ation is enabled. STP bit must be reset when

standard protocol is used (this is also the default

reset conditions). Set to zero after reset.

STD, SPI Enable. This bit, in conjunction with S-

2

BUS/I C BUS bit, allows the SPI disable and will

2

select between I C BUS/S-BUS and Standard

shift register protocols. If this bit is set to one, it se-

2

ACN. Read Only. If STD bit (D1 of SCR1 register)

is cleared to zero this bit is meaningless. When

STD is set to one, this bit is set to one if no Ac-

knowledge has been received. In this case it is au-

tomatically reset when BSY is set again. Set to

zero after reset.

lects both I C BUS and S-BUS protocols; final se-

2

lection between them is made by S-BUS/I C BUS

2

bit. If this bit is cleared to zero when S-BUS/I C

BUS is set to “1” the Standard shift register proto-

col is selected. If this bit is cleared to “0” when S-

2

BUS/I C BUS is cleared to 0 the SPI is disabled.

Set to zero after reset.

BSY. Read/Set Only. This is the busy bit. When a

one is loaded into this bit the SPI interface start the

transmission of the data byte loaded into SSDR

data register or receiving and building the receive

data into the SSDR data register. This is done in

accordance with the protocol, direction and start/

stop condition(s). This bit is automatically cleared

at the end of the current byte operation. Cleared to

zero after reset.

2

S-BUS/I C BUS Selection. This bit, in conjunction

with STD/SPI bit, allows the SPI disable and will

2

select between I C BUS and S-BUS protocols. If

this bit is cleared to “0” when STD bit is also “0”,

the SPI interface is disabled. If this bit is cleared to

2

zero when STD bit is set to “1”, the I C BUS proto-

col will be selected. If this bit is set to “1” when

STD bit is set to “1”, the S-BUS protocol will be se-

lected. Cleared to zero after reset.

Note: The SPI shift register is also the data trans-

mission register and the data received register;

this feature is made possible by using the serial

structure of the ST638x and thus reducing size

and complexity.

Table 13. SPI Mode Selection

D1

STD/SP

D0

SPI Function

2

S-BUS/I C BUS

0

1

0

1

0

1

Disabled

STD Shift Reg.

2

I C BUS

S-BUS

42/82

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389

SERIAL PERIPHERAL INTERFACE (Cont’d)

During transmission or reception of data, all ac-

cess to serial data register is therefore disabled.

The reception or transmission of data is started by

setting the BUSY bit to “1”; this will be automatical-

ly reset at the end of the operation. After reset, the

busy bit is cleared to “0”, and the hardware SPI

disabled by clearing bit 0 and bit 1 of SPI control

register 1 to “0”. The outputs from the hardware

SPI are “ANDed” to the standard I/O software con-

trolled outputs. If the hardware SPI is in operation

the Port C pins related to the SPI should be config-

ured as outputs using the Data Direction Register

and should be set high. When the SPI is config-

ured as the S-BUS, the three pins PC0, PC1 and

PC3 become the pins SCL, SDA and SEN respec-

general purpose I/O pin. The VERIFY bit is availa-

ble when the SPI is configured as either S-BUS or

I C BUS. At the start of a byte transmission, the

2

verify bit is set to one. If at any time during the

transmission of the following eight bits, the data on

the SDA line does not match the data forced by the

SPI (while SCL is high), then the VERIFY bit is re-

set. The verify is available only during transmis-

2

sion for the S-BUS and I C BUS; for other protocol

it is not defined. The SDA and SCL signal entering

the SPI are buffered in order to remove any minor

2

glitches. When STD bit is set to one (S-BUS or I C

BUS selected), and TRX bit is reset (receiving da-

ta), and STOP bit is set (last byte of current com-

munication), the SPI interface does not generate

2

tively. When configured as the I C BUS the pins

the Acknowledge, according to S-BUS/I C BUS

PC0 and PC1 are configured as the pins SCL and

SDA; PC3 is not driven and can be used as a gen-

eral purpose I/O pin. In the case of the STD SPI

the pins PC0 and PC1 become the signals CLOCK

and DATA, PC3 is not driven and can be used as

specifications. PCO-SCL, PC1-SDA and PC3-

SEN lines are standard drive I/O port pins with

open-drain output configuration (maximum voltage

that can be applied to these pins is V + 0.3V).

DD

43/82

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389

4.4 14-BIT VOLTAGE SYNTHESIS TUNING PERIPHERAL

The ST638x on-chip voltage synthesis tuning pe-

ripheral has been integrated to allow the genera-

tion of tuning reference voltage in low/mid end TV

set applications. The peripheral is composed of a

14-bit counter that allows the conversion of the

digital content in a tuning voltage, available at the

VS output pin, by using Pulse Width Modification

(PWM), and Bit Rate Multiplier (BRM) techniques.

The 14-bit counter gives 16384 steps which allows

a resolution of approximately 2mV over a tuning

voltage of 32V; this corresponds to a tuning reso-

lution of about 40KHz per step in the UHF band

(the actual value will depend on the characteristics

of the tuner).

Table 14. . Fine Tuning Pulse Addition

N° of pulses added at the

following cycles

(0... 127)

Fine Tuning

(7 LSB)

0000001

0000010

0000100

0001000

0010000

0100000

1000000

64

32, 96

16, 48, 80, 112

8, 24,....104, 120

4, 12,....116, 124

2, 6,.....122, 126

1, 3,.....125, 127

The VS output pin has a standard drive push-pull

output configuration.

The tuning word consists of a 14-bit word con-

tained in the registers VSDATA1 (location 0EEh)

and VSDATA2 (location 0EFh). Coarse tuning

(PWM) is performed using the seven MSBits,

while fine tuning (BRM) is performed using the

data in the seven LSBits. With all zeros loaded the

output is zero; as the tuning voltage increases

from all zeros, the number of pulses in one period

increase to 128 with all pulses being the same

width. For values larger than 128, the PWM takes

over and the number of pulses in one period re-

mains constant at 128, but the width changes. At

the other end of the scale, when almost all ones

are loaded, the pulses will start to link together and

the number of pulses will decrease. When all ones

are loaded, the output will be almost 100% high

but will have a low pulse (1/16384 of the high

pulse).

4.4.2 VS Tuning Cell Registers

Voltage Synthesis Data Register 1 (VSDR1)

Address: EEh - Write only

Reset Value: XXh

7

0

VSDR1 VSDR1 VSDR1 VSDR1 VSDR1 VSDR1 VSDR1 VSDR1

7

6

5

4

3

2

1

0

Caution: This register contains at least one write

only bit. Single bit instructions (SET, RES, INC

and DEC) should not be used.

D7-D0. These are the 8 least significant VS data

bits. Bit 0 is the LSB. This register is undefined on

reset.

4.4.1 Output Details

Inside the on-chip Voltage Synthesis are included

the register latches, a reference counter, PWM

and BRM control circuitry. In the ST638x the clock

for the 14-bit reference counter is 4MHz derived

from the 8MHz system clock. From the circuit point

of view, the seven most significant bits control the

coarse tuning, while the seven least significant bits

control the fine tuning. From the application and

software point of view, the 14 bits can be consid-

ered as one binary number.

Voltage Synthesis Data Register 2 (VSDR2)

Address: EFh - Write only

Reset Value: XXh

7

-

0

VSDR2 VSDR2 VSDR2 VSDR2 VSDR2 VSDR2

-

5

4

3

2

1

0

Caution: This register contains at least one write

only bit. Single bit instructions (SET, RES, INC

and DEC) should not be used.

As already mentioned the coarse tuning consists

of a PWM signal with 128 steps; we can consider

the fine tuning to cover 128 coarse tuning cycles.

The addition of pulses is described in the following

Table.

D7-D6. These bits are not used.

D5-D0. These are the 6 most significant VS data

bits. Bit 5 is the MSB. This register is undefined on

reset.

44/82

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389

4.5 6-BIT PWM D/A CONVERTERS

The D/A macrocell contains up to six PWM D/A

outputs (31.25kHz repetition, DA0-DA5) with six

bit resolution.

DA0-DA5 Data/Control Register (DADCR)

Address: E0h, E1h, E2h, E3h, E6h, E7h, - Write

only

Each D/A converter of ST638x is composed by the

following main blocks:

Reset Value: XXh

7

-

0

– pre-divider

DADCR DADCR DADCR DADCR DADCR DADCR

– 6-bit counter

-

5

4

3

2

1

0

– data latches and compare circuits

Caution: This register contains at least one write

only bit. Single bit instructions (SET, RES, INC

and DEC) should not be used.

The pre-divider uses the clock input frequency

(8MHz typical) and its output clocks the 6-bit free-

running counter. The data latched in the six regis-

ters (E0h, E1h, E2h, E3h, E6h and E7h) control

the six D/A outputs (DA0,1,2, 3, 4 and 5). When all

zeros are loaded the relevant output is an high log-

ic level; all 1's correspond to a pulse with a 1/64

duty cycle and almost 100% zero level.

DADCR0-DADCR5. These are the 6 bits of the

PWM digital to analog converter. Undefined after

reset.

Figure 30. 6-bit PWM D/A Output Configuration

The repetition frequency is 31.25kHz and is relat-

ed to the 8MHz clock frequency. Use of a different

oscillator frequency will result in a different repeti-

tion frequency. All D/A outputs are open-drain with

standard current drive capability and able to with-

stand up to 12V.

DA0-DA5

OUT

(OPEN-DRAIN, 12V)

Out

N

VA00343

45/82

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389

4.6 A/D CONVERTER (ADC)

The A/D converter peripheral is an 8-bit analog to

digital converter with analog inputs as alternate I/O

functions (the number of which is device depend-

ent), offering 8-bit resolution with a typical conver-

sion time of 70us (at an oscillator clock frequency

of 8MHz).

This action is also needed before entering WAIT

mode, since the A/D comparator is not automati-

cally disabled in WAIT mode.

During Reset, any conversion in progress is

stopped, the control register is reset to 40h and the

ADC interrupt is masked (EAI=0).

The ADC converts the input voltage by a process

of successive approximations, using a clock fre-

quency derived from the oscillator with a division

factor of twelve. With an oscillator clock frequency

less than 1.2MHz, conversion accuracy is de-

creased.

Figure 31. ADC Block Diagram

INTERRUPT

CLOCK

RESET

Ain

CONVERTER

Selection of the input pin is done by configuring

the related I/O line as an analog input via the Op-

tion and Data registers (refer to I/O ports descrip-

tion for additional information). Only one I/O line

must be configured as an analog input at any time.

The user must avoid any situation in which more

than one I/O pin is selected as an analog input si-

multaneously, to avoid device malfunction.

AV

DD

SS

CONTROL REGISTER

8

RESULT REGISTER

8

The ADC uses two registers in the data space: the

ADC data conversion register, ADR, which stores

the conversion result, and the ADC control regis-

ter, ADCR, used to program the ADC functions.

CORE

CONTROL SIGNALS

CORE

VA00418

A conversion is started by writing a “1” to the Start

bit (STA) in the ADC control register. This auto-

matically clears (resets to “0”) the End Of Conver-

sion Bit (EOC). When a conversion is complete,

the EOC bit is automatically set to “1”, in order to

flag that conversion is complete and that the data

in the ADC data conversion register is valid. Each

conversion has to be separately initiated by writing

to the STA bit.

4.6.1 Application Notes

The A/D converter does not feature a sample and

hold circuit. The analog voltage to be measured

should therefore be stable during the entire con-

version cycle. Voltage variation should not exceed

±1/2 LSB for the optimum conversion accuracy. A

low pass filter may be used at the analog input

pins to reduce input voltage variation during con-

version.

The STA bit is continuously scanned so that, if the

user sets it to “1” while a previous conversion is in

progress, a new conversion is started before com-

pleting the previous one. The start bit (STA) is a

write only bit, any attempt to read it will show a log-

ical “0”.

When selected as an analog channel, the input pin

is internally connected to a capacitor C of typi-

ad

cally 12pF. For maximum accuracy, this capacitor

must be fully charged at the beginning of conver-

sion. In the worst case, conversion starts one in-

struction (6.5 µs) after the channel has been se-

lected. In worst case conditions, the impedance,

ASI, of the analog voltage source is calculated us-

ing the following formula:

The A/D converter features a maskable interrupt

associated with the end of conversion. This inter-

rupt is associated with interrupt vector #4 and oc-

curs when the EOC bit is set (i.e. when a conver-

sion is completed). The interrupt is masked using

the EAI (interrupt mask) bit in the control register.

6.5µs = 9 x C x ASI

ad

The power consumption of the device can be re-

duced by turning off the ADC peripheral. This is

done by setting the PDS bit in the ADC control reg-

ister to “0”. If PDS=“1”, the A/D is powered and en-

abled for conversion. This bit must be set at least

one instruction before the beginning of the conver-

sion to allow stabilisation of the A/D converter.

(capacitor charged to over 99.9%), i.e. 30 kΩ in-

cluding a 50% guardband. ASI can be higher if C

ad

has been charged for a longer period by adding in-

structions before the start of conversion (adding

more than 26 CPU cycles is pointless).

46/82

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389

A/D CONVERTER (Cont’d)

Since the ADC is on the same chip as the micro-

processor, the user should not switch heavily load-

ed output signals during conversion, if high preci-

sion is required. Such switching will affect the sup-

ply voltages used as analog references.

be working and the resulting noise could affect

conversion accuracy.

A/D Converter Control Register (ADCR)

Address: 0D1h

—

Read/Write, Write only

Reset value: 40h

The accuracy of the conversion depends on the

quality of the power supplies (V

and V ). The

DD

SS

7

0

-

user must take special care to ensure a well regu-

lated reference voltage is present on the V and

DD

EAI

EOC

STA

PDS

-

V

pins (power supply voltage variations must be

SS

less than 5V/ms). This implies, in particular, that a

Bit 7 = EAI: Enable A/D Interrupt. If this bit is set to

“1” the A/D interrupt (vector #4) is enabled, when

EAI=0 the interrupt is disabled.

suitable decoupling capacitor is used at the V

pin.

DD

The converter resolution is given by:

Bit 6 = EOC: End of conversion. Read Only. This

read only bit indicates when a conversion has

been completed. This bit is automatically reset to

“0” when the STA bit is written. If the user is using

the interrupt option then this bit can be used as an

interrupt pending bit. Data in the data conversion

register are valid only when this bit is set to “1”.

V

_DD– V_SS

---------------------------

256

The Input voltage (Ain) which is to be converted

must be constant for 1µs before conversion and

remain constant during conversion.

Bit 5 = STA: Start of Conversion. Write Only. Writ-

ing a “1” to this bit will start a conversion on the se-

lected channel and automatically reset to “0” the

EOC bit. If the bit is set again when a conversion is

in progress, the present conversion is stopped and

a new one will take place. This bit is write only, any

attempt to read it will show a logical zero.

Conversion resolution can be improved if the pow-

er supply voltage (V ) to the microcontroller is

DD

lowered.

In order to optimise conversion resolution, the user

can configure the microcontroller in WAIT mode,

because this mode minimises noise disturbances

and power supply variations due to output switch-

ing. Nevertheless, the WAIT instruction should be

executed as soon as possible after the beginning

of the conversion, because execution of the WAIT

Bit 4 = PDS: Power Down Selection. This bit acti-

vates the A/D converter if set to “1”. Writing a “0” to

this bit will put the ADC in power down mode (idle

mode).

Bit 3-0 = Not used

instruction may cause a small variation of the V

DD

Caution: This register contains at least one write

only bit. Single bit instructions (SET, RES, INC

and DEC) should not be used.

voltage. The negative effect of this variation is min-

imized at the beginning of the conversion when the

converter is less sensitive, rather than at the end

of conversion, when the less significant bits are

determined.

A/D Converter Data Register (ADR)

Address: 0D0h

—

Read only

The best configuration, from an accuracy stand-

point, is WAIT mode with the Timer stopped. In-

deed, only the ADC peripheral and the oscillator

are then still working. The MCU must be woken up

from WAIT mode by the ADC interrupt at the end

of the conversion. It should be noted that waking

up the microcontroller could also be done using

the Timer interrupt, but in this case the Timer will

Reset value: XXh

7

0

D7

D6

D5

D4

D3

D2

D1

D0

Bit 7-0 = D7-D0: 8 Bit A/D Conversion Result.

47/82

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389

4.7 DEDICATED LATCHES

Two latches are available which may generate in-

terrupts to the ST638x core. The IR latch is set ei-

ther by the falling or rising edge of the signal on pin

PC6(IRIN). If bit 1 (IRPOSEDGE) of the latches

register (E9h) is high, then the latch will be trig-

gered on the rising edge of the signal at

PC6(IRIN). If bit 1 (IRPOSEDGE) is low, then the

latch will be triggered on the falling edge of the sig-

nal at PC6(IRIN). The IR latch can be reset by set-

ting bit 3 (RESIRLAT) of the latches register; the

bit is write only and a high should be written every

time the IR latch needs to be reset. If bit 2 (IRINT-

EN) of the latches register (E9h) is high, then the

output of the IR latch, IRINTN, may generate an in-

terrupt (#0). IRINTN is inverted with respect to the

state of the IR latch. If bit 2 (IRINTEN) is low, then

the output of the IR latch, IRINTN, is forced

high.The state of the IR latch may be read from bit

3 (IRLATCH) of register E4h; if the IR latch is set,

then bit 3 will be high. The PWR latch is set either

by the falling or rising edge of the signal on pin

PC4(PWRIN). If bit 4 (PWREDGE) of the latches

register (E9h) is high, then the latch will be trig-

gered on the rising edge of the signal at

PC4(PWRIN). If bit 4 (PWREDGE) is low, then the

latch will be triggered on the falling edge of the sig-

nal at PC4(PWRIN). The PWR latch can be reset

by setting bit 6 (RESPWRLAT) of the latches reg-

ister; the bit is set only and a high should be written

every time the PWR latch needs to be reset. If bit 5

(PWRINTEN) of the latches register (E9h) is high,

then the output of the PWR latch, PWRINTN, may

generate an interrupt (#4). PWRINTN is inverted

with respect to the state of the PWR latch. If bit 5

(PWRINTEN) is low, then the output of the PWR

latch, PWRINTN, is forced high.

Dedicated Latches Control Register (DLCR)

Address: E9h - Write only

Reset Value: XXh

7

0

-

IR-

POSED

GE

RESP- PWRINT- PWRED RESIR- IRINT-

-

WRLAT

EN

GE

LAT

EN

Caution: This register contains at least one write

only bit. Single bit instructions (SET, RES, INC

and DEC) should not be used.

Bit 7. This bit is not used

RESPWRLAT. Resets the PWR latch; this bit is

write only.

PWRINTEN. This bit enables the PWRINT signal

(#4) from the latch to the ST638x core. Undefined

after reset.

PWREDGE. The bit determines the edge which

will cause the PWRIN latch to be set. If this bit is

high, than the PWRIN latch will be set on the rising

edge of the PWRIN signal. Undefined after reset.

RESIRLAT. Resets the IR latch; this bit is write on-

ly. Undefined after Reset.

IRINTEN. This bit enables the IRINTN signal (#0)

from the latch to the ST638x core. Undefined after

reset.

IRPOSEDGE. The bit determines the edge which

will cause the IR latch to be set. If this bit is high,

than the IR latch will be set on the rising edge of

the IR signal. Undefined after reset.

Bit 0. This bit is not used

48/82

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389

4.8 ON-SCREEN DISPLAY (OSD)

The OSD macrocell is a CMOS LSI character gen-

erator which enables display of characters and

symbols on the TV screen. The character rounding

function enhances the readability of the charac-

ters. The OSD macrocell receives horizontal and

vertical synchronization signal and outputs screen

information via R, G, B and blanking pins.

4.8.1 Format Specification

The entire display can be turned on or off through

the use of the global enable bit or the display may

be selectively turned on or off by word. To turn off

the entire display, the global enable bit (GE)

should be zero. If the global enable bit and the

OSD ram enable bit are one, the display is control-

led by the word enable bit (WE). The global enable

bit and the OSD ram enable bit are located in the

global enable register and the word enable bit is

located in the space character preceding the word.

The main characteristics of the macrocell are list-

ed below

– Number of display characters: 8 lines by 20 col-

umns.

Each line must begin with a format character

which describes the format of that line and of the

first word. This character is not displayed.

– Number of character types: 192 characters in

one bank.

– Character size: Four character heights (18H,

36H, 54H, 72H), programmable by line.

A space character defines the format of the subse-

quent word. A space character is denoted by a pair

of one in bits 7 (MSB) and 6 of the character regis-

ter in the display RAM. If bit 7 and 6 of a character

register are different from “11”, the 8 bits of the

character register are used as an index which se-

lects the desired character font from the 192 char-

acters ROM.

– Character format: 14x18 dots with character

rounding function.

– Character colour: Eight colours available pro-

grammable by word.

– Display position: 63 horizontal positions pro-

grammable by 2/f

and 63 vertical positions

OSC

The character colour and background can be pro-

grammed by word. This information is encoded in

the space character between words or in the for-

mat character at the beginning of each line. Four

bits define the colour and background of the fol-

lowing word.

programmable by 4H

– Word spacing: 64 positions programmable from

2/f to 128/f

OSC

– Line spacing: 63 positions programmable from 4

to 252 H with two line spacing values per screen.

– Background: No background, square back-

ground or fringe background. The presence of

background is programmable by word, the mode

(fringe or square) being the same for the entire

screen.

Characters are defined in a 14 x 18 dots format.

One dot is defined vertically as 1H (horizontal line)

per field (2H per frame) and horizontally as 1/f

OSC

if the smallest character size is enabled. The

rounding function is not available for the smallest

character size. For the other sizes, the rounding

function could be disabled by the rounding disable

bit (RDIS). There is no space between characters

or lines if the vertical space enable (VSE) and hor-

izontal space enable (HSE) bits are both zero.

This allows the use of special graphic characters

(combination of two or more characters).

– Background colour: Two types selected by word

from a palette of eight colours. The palette is pro-

grammable by screen.

– Display output: Three video signal output termi-

nals (R,G,B) and a blank output terminal.

– Display on/off: Display data may be programmed

on or off by word or entire screen. The entire

screen may be blanked.

The normal alphanumeric character set is format-

ted to be 13 x 16 with one empty row at the top and

one at the bottom and one empty column at the

right. If VSE and HSE are both zero, then the

spacing between alphanumeric characters is 1 dot

and the spacing between lines of alphanumeric

characters is 4H per frame.

– Full screen background: Background on the en-

tire TV screen, one of eight colours available,

with normal text display possible.

49/82

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389

ON-SCREEN DISPLAY (Cont’d)

The character size is programmed by line through

the use of the size bits (S1 and S2) in the format

character. The vertical spacing enable bit (VSE)

located in the format character controls the spac-

ing between lines. If this bit is set to one, the spac-

ing between lines is defined by one of the vertical

spacing register, otherwise the spacing between

lines is 0. As there are two vertical space registers

available, the actual spacing between two succes-

sive lines will be selected by the vertical space se-

lect bit (VSS) in the format character.

Table 16. Format Character Register Colour

Setting.

R

0

1

G

0

1

0

1

B

0

1

0

1

0

1

0

1

Colour

Black

Blue

Green

Cyan

Red

Magenta

Yellow

White

The spacing between words is controlled by the

horizontal space enable bit (HSE) located in the

space character. If this bit is set to one, the spac-

ing between words is defined by the horizontal

spacing register, otherwise the space character

width of 14 dots is the spacing between words.

BGS. Background Select. The background select

bit selects the desired background for the following

word. There are two possible backgrounds defined

by the bits in the Background Control Register.

The formats for the format character, display char-

acter and space character are described hereaf-

ter.

“0” The background on the following word is ena-

bled by BG0 and the colour is set by R0, G0,

and B0.

4.8.2 Format Character Register (FT)

See Data RAM Table Description for Specific Ad-

dress — Read/Write

“1” The background on the following word is ena-

bled by BG1 and the colour is set by R1, G1,

and B1.

7

0

VSE. Vertical Space Enable. The vertical space

enable bit determines the spacing between lines.

S2

S1

R

G

B

BGS

VSS

VSE

“0” The space between lines is equal to 0H. The

alphanumeric character set is implemented in

a 13 x 16 format with one empty column to the

left and one empty row above and one below

and stored in a 14 x 18 format.

S1-S2. Character Size. The character size bits

specify the character size for each line as defined

in Table 15.

Table 15. Format Character Register Size

Setting

“1” The space between lines is defined by the val-

ues in the vertical space register and the value

of the VSS bit.

Vertical

Height

Horizontal

length

S2

S1

VSS. Vertical Space Select. If the VSE bit is set,

the value of this bit selects one of the two ver-

tical spaces contained in the vertical space

registers (VSR0 and VSR1). A “0” in this bit

selects the VSR0 value, a “1” selects the

VSR1 value, respectively.

1

0

1

0

1

0

18H

36H

54H

72H

14 TDOT

28 TDOT

42 TDOT

56 TDOT

Note. The first word of each line is always ena-

bled. If we desire the line to begin further to the

right we have two solutions: to increase the

HSAR register or to introduce a Space Char-

acter just after the Format Character. A Space

Character should also be used if we don’t want

the current line to be displayed.

TDOT= 1/f

osc

R, G, B. Colour. The 3 colour control bits define

the foreground colour of the following word as

shown in Table 16.

50/82

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389

ON-SCREEN DISPLAY (Cont’d)

Display Character Register (Ch)

“1” The background on the following word is ena-

bled by BG1 and the colour is set by R1, G1,

See Data RAM Table Description for Specific Ad-

dress — Read/Write

and B1.

WE. Word Enable. The word enable bit defines

whether or not the following word is displayed.

7

0

“0” The word is not displayed.

C7

C6

C5

C4

C3

C2

C1

C0

“1” If the global enable bit and the OSD ram ena-

ble bit are set, then the word is displayed.

C7-C6. This bits must be different from “11”.

HSE. Horizontal Space Enable. The horizontal

space enable bit determines the spacing between

words.

C7-C0. Character code. The 8 bits character code

(range: 00h to 0BFh) selects the character from a

set of 192 characters available.

“0” The space between words is equal to the width

of the space character, which is 14 dots.

Space Character Format Register (Ch)

“1” The space between words is defined by the

value in the horizontal space register plus the

width of the space character.

See Data RAM Table Description for Specific Ad-

dress — Read/Write

Character Set

7

0

The character set is user defined as ROM mask

option.

D7

D6

R

G

B

BGS

WE

HSE

Register and RAM Addressing

The OSD contains eight registers and 168 RAM lo-

cations. The eight registers are the Vertical Start

Address register, Horizontal Start Address regis-

ter, Vertical Space registers (VSR0 and VSR1),

Horizontal Space register, Background Control

register, Global Enable register and Polarity Select

register (PSR). The Global Enable register and

Polarity Select register can be written at any time

by the ST6 Core. The access to the next five reg-

isters and the RAM is controlled through the state

of the Global Enable register.

D7-D6. This bits must be “11”.

R, G, B. Colour. The 3 colour control bits define

the foreground colour of the following word as

shown in table below.

Table 17. Space Character Register Colour

Setting.

R

0

1

G

0

1

0

1

B

0

1

0

1

0

1

0

1

Colour

Black

Blue

The first six registers and the RAM are located in

page 5 of the paged memory of the ST6388 MCU.

This page contains 64 memory locations. This

paged memory is mapped into the memory loca-

tions 00h to 3Fh of the ST6388 memory map. A

page of memory is enabled by setting the desired

page bit, located in the Data Ram Bank Register,

to a one. The page register is at location E8h. The

hexadecimal value 20h selects page 5 - the OSD

RAM and registers (except PSR). As the OSD

RAM consists of 168 words, this RAM is further

paged using two bits (LS1/LS0) in the Global Ena-

ble register, in order to fit onto the 64 locations of

the page 5 of the MCU RAM space. Table 18

shows the addresses of the OSD registers and

RAM.

Green

Cyan

Red

Magenta

Yellow

White

BGS. Background Select. The background select

bit selects the desired background for the following

word. There are two possible backgrounds defined

by the bits in the Background Control Register.

“0” The background on the following word is ena-

bled by BG0 and the colour is set by R0, G0,

and B0.

51/82

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389

ON-SCREEN DISPLAY (Cont’d)

Table 18. OSD Control Registers and Data RAM

Addressing

“0” The OSD RAM can be accessed by the Core.

“1” The OSD RAM content is displayed on screen

and cannot be accessed by Core.

Page

Address

00h - 14h

20h - 34h

38h

Register or RAM

RAM Locations 00h - 14h

RAM Locations 20h - 34h

Vertical Start Register

Note: The display of characters on screen is only

Page 5

possible after the setting of these two bits

LS1-LS0. This bits selects one pair of OSD RAM

lines that is to be mapped into the 0h-35h address

area. There are four possible values of this pair of

bits:

39h

Horizontal Start Register

Vertical Space Register 0

Horizontal Space Register

Background Control Register

Vertical Space Register 1

Global Enable Register

3Ah

“00” - selects line 0 and line 1;

“01” - selects line 2 and line 3;

“10” - selects line 4 and line 5;

“11” - selects line 6 and line 7.

3Bh

3Ch

3Dh

3Fh

Note: The global registers in page 5 are accessi-

ble at RAM locations 38h-3Fh, page 5 selected,

regardless of the value of the LS0/LS1 bits.

Static

page

EDh

OSD Polarity Select Register

OSD Polarity Select Register (OPSR)

OSD Global Enable Register

Address: EDh - Static Page — Write Only

This register contains the global enable bit (GE),

OSD Ram Enable bit (ORE) and the line select bits

(LS1/LS0). This register can be written at any time.

It is a write only register.

7

0

D7

D6

D5

D4

VSP

HSP BLKP RGBP

OSD Global Enable Bit Register (OGER)

Address: 3Fh - Page 5

—

Write Only

D7-D4. These bits are reserved and must always

be written with 0.

7

0

VSP. Vertical sync polarity input select bit. This bit

selects the polarity of the VSync input signal (“0”

for positive, “1” for negative polarity, respectively).

D7

D6

D5

D4

LS1

LS0

ORE

GE

HSP. Horizontal sync input polarity select bit. This

bit selects the polarity of the HSync input signal

(“0” for positive, “1” for negative polarity, respec-

tively).

D7-D4. These bits are not used

GE. Global Enable. This bit allows the entire dis-

play to be turned off.

“0” The entire display is disabled. The other regis-

ters of the OSD can be accessed by the Core.

BLKP. Blanking output polarity select bit. This bit

selects the polarity of the BLK output (“0” for posi-

tive, “1” for negative polarity, respectively).

“1” Display of words is controlled by the word en-

able bits (WE) located in the format or space

character. The other registers cannot be ac-

cessed by the Core.

RGBP. RGB output polarity select bit. This bit se-

lects the polarity of the RGB outputs (“0” for posi-

tive, “1” for negative polarity, respectively).

Note: Reset value is 00h, all polarities being posi-

tive.

ORE. OSD Ram Enable. This bit controls the ac-

cess to the OSD RAM.

52/82

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389

ON-SCREEN DISPLAY (Cont’d)

Vertical Start Address Register (VSAR)

a menu, then the background should be displayed

when on space characters.

Address: 38h - Page 5

—

Read/Write

“0” The background during spaces is controlled

7

0

by the background enable bits (BG0 and BG1)

located in the Background Control register.

D7

FR

VSA5 VSA4 VSA3 VSA2 VSA1 VSA0

“1” The background is not displayed when spaces

are displayed.

D7. This bit is not used

HSA5, HSA0 - Horizontal Start Address bits.

These bits determine the start position of the first

character in the horizontal direction. The 6 bits can

FR. FRinge background.This bit changes the

background from a box background to a fringe

background. The background is enabled by word

as defined by either BG0 or BG1.

specify 64 display start positions of interval 2/f

OSC

or 400ns. The first start position will be at 7.2µs

because of the time needed to access RAM and

ROM before the first character can be displayed.

The horizontal start address is defined by the fol-

lowing formula.

“0” The background is defined to be a box which

is 15 x 18 dots (the 14x18 dots frame of the

character + one dot column placed left of the

character frame).

5

Horizontal Start Address = 2/f_OSC(18 + 2 (HSA5)

4

3

2

1

“1” The background is defined to be a fringe. The

fringe background is complete around the dis-

played character provided that it is inside the

15x18 dots frame.

+2 (HSA4) + 2 (HSA3) + 2 (HSA2) + 2 (HSA1)

0

+ 2 (HSA0))

Note: The case of all Horizontal Start Address bits

being zero is illegal.

Note: For the smallest character size (14TDOT,

18H) the fringe function may be either a full

fringe or a shadow background (see also

FF_SH bit of the VSR1 register).

Vertical Space Register 0 (VSR0)

Address: 3Ah - Page 5

—

Read/Write

7

0

VSA5-VSA0. Vertical Start Address. These bits

determine the start position of the first line in

the vertical direction. The 6 bits can specify 63

display start positions of interval 4H. The first

start position will be the fourth line of the dis-

play. The vertical start address is defined

VSA0 by the following formula.

D7

SCB

VS5

VS4

VS3

VS2

VS1

VS0

D7. This bit is not used

SCB. Screen Blanking. This bit allows the entire

screen to be blanked.

5

4

“0” The blanking output signal BLANK is active

only when displaying characters.

Vertical Start Address = 4H(2 (VSA5) + 2

(VSA4) +2 (VSA3) + 2 (VSA2) + 2 (VSA1) + 2

(VSA0))

3

2

1

0

“1” The blanking output signal BLANK is always

active. Characters in the display RAM are still

displayed.

Note: The case of all Vertical Start Address bits

being zero is illegal.

Horizontal Start Address Register (HSAR)

When this bit is set to one, the screen is blanked

also without setting the Global Enable bit to one

(OSD disabled).

Address: 39h - Page 5

—

Read/Write

7

0

VS5, VS0. Vertical Space. These bits determine

the spacing between lines if the Vertical Space En-

able bit (VSE) in the format character is set and

the Vertical Space Select bit (VSS) is reset. If VSE

is zero there will be no spaces between lines. The

Vertical Space bits can specify one of 63 spacing

values from 4H to 252H. The space between lines

is defined by the following formula.

D7

SBD HSA5 HSA4 HSA3 HSA2 HSA1 HSA0

D7. This bit is not used.

SBD. Space Background Disable. This bit controls

whether or not the background is displayed on

space characters. If two background colours are

used on adjacent words, then the background

should not be displayed on spaces in order to

make a nice break between colours. If an even

background around an area of text is desired, as in

5

4

Space between lines = 4H(2 (VS5) + 2 (VS4) +

3

2

1

0

2 (VS3) + 2 (VS2) + 2 (VS1) + 2 (VS0))

Note: The case of all Vertical Space bits being

zero is not legal.

53/82

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389

ON-SCREEN DISPLAY (Cont’d)

Horizontal Space Register (HSR)

Note: This size does not include the width of the

space character.

Address: 3Bh - Page 5

—

Read/Write

The case of all Vertical Start Address bits being

zero is illegal.

7

0

Background Control Register (BCR)

RDIS

FSB

HS5

HS4

HS3

HS2

HS1

HS0

This register sets up two possible backgrounds.

The background select bit (BGS) in the format or

space character will determine which background

is selected for the current word.

RDIS. Rounding DISable. This bit disable the

rounding function for the following screen. It allows

the display of some special characters which could

be modified by the rounding function.

Background Control Register

Address: 3Ch - Page 5

—

Read/Write

“0”Rounding function enable

“1”Rounding function disable

7

0

FSB. Full Screen Background. This bit allows the

entire screen to be filled with a one colour back-

ground. The background is controlled by the back-

ground select bit (BGS). During this mode the dis-

play of characters is possible.

R1

R0

G1

G0

B1

B0

BK1

BK0

R1,R0,G1,G0,B1,B0. Background Colour.

These bits define the colour of the specified back-

ground, either background 1 or background 0 as

defined in table below.

“0”No Full Screen Background

“1”Full Screen Background is active

Note: The full screen background bit has priority

over the background enable bits (BK0 and BK1)

and on the screen blanking bit. This means that if

the two backgrounds are disabled and the screen

blanking is active, the full screen background will

still be displayed.

Table 19. Background Register Colour Setting.

RX

0

GX

0

BX

0

Colour

Black

0

1

Blue

HS5, HS0. Horizontal Space. These bits deter-

mine the spacing between words if the Horizontal

Space Enable bit (HSE) located in the space char-

acter is a one. The space between words is then

equal to the width of the space character plus the

number of dots specified by the Horizontal Space

bits. The 6 bits can specify one of 64 spacing val-

0

1

0

Green

Cyan

0

1

0

Red

1

0

1

Magenta

Yellow

White

1

0

1

ues ranging from 1/f

to 64/f . The formula is

osc

shown below for the smallest size character(18H).

If larger size characters are being displayed the

spacing between words will increase proportion-

ately. Multiply the value below by 2, 3 or 4 for char-

acter sizes of 36H, 54H and 72H respectively.

BK1,BK0. Background Enable.These bits deter-

mine if the specified background is enabled or not.

“0” The word having this background specified

has not a background.

5

4

Space between words =2/f (1+2 (HS5)+2

3

2

1^OSC

0

(HS4)+2 (HS3) +2 (HS2)+ 2 (HS1)+2 (HS0))

“1” The word having this background specified

has a background of the colour selected by the

corresponding RGB bits.

54/82

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389

ON-SCREEN DISPLAY (Cont’d)

Vertical Space Register 1 (VSR1)

“0” The 18H characters have a shadow back-

ground. (provided also that FR bit is set and

the selected background is active). This con-

Address: 3Dh - Page 5

—

Read/Write

sists of a one dot wide line on the right and

lower sides of the character.

7

0

D7 FF_SH VS5

VS4

VS3

VS2

VS1

VS0

VS5, VS0. Vertical Space. These bits determine

the spacing between lines if the Vertical Space En-

able bit (VSE) in the format character is set and

the Vertical Space Select bit (VSS) is set. If VSE is

zero there will be no spaces between lines. The

Vertical Space bits can specify one of 63 spacing

values from 4H to 252H. The space between lines

is defined by the following formula.

D7. This bit is not used

FF_SH. Full fringe / shadow background select.

This bit selects between the fringe and shadow

backgrounds for the smallest size (18H) charac-

ters, provided that the FR bit is also set.

5

4

“1” The 18H characters are surrounded by a

fringe background. (Provided that FR bit is set

and the selected background is active). This

consists of a one dot wide contour in the back-

ground colour

Space between lines = 4H(2 (VS5) + 2 (VS4) +

3

2

1

0

2 (VS3) + 2 (VS2) + 2 (VS1) + 2 (VS0))

Note: The case of all Vertical Space bits being

zero is not legal.

55/82

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389

ON-SCREEN DISPLAY (Cont’d)

OSD Data RAM

The contents of the data RAM can be accessed by

the ST6388 MCU only when the Global Enable bit

(GE) in the Global Enable register is a zero.

ters are either spaces or one of the 192 available

character types.

The space character defines the colour, back-

ground, display enable and horizontal space ena-

ble for the following word. Since there are 8 dis-

play lines of 20 characters each, the display RAM

must contain 8 lines x (20 characters + 1 format

character) or 168 locations. The RAM size is 168

locations x 8bits. The data RAM map is shown in

Table 20.

The first character in every line is the format char-

acter. This character is not displayed. It defines

the size of the characters in the line and contains

the vertical space enable bit. This character also

defines the colour, background and display enable

for the first word in the line. Subsequent charac-

Table 20. OSD RAM Map

Column

0

1

0

2

0

1

0

3

1

0

4

0

1

0

...

14 15 16 17 18 19 20

A0

A1

A2

A3

A4

LS1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

LS0

0

A5

0

LINE

1

2

3

4

5

6

7

8

FT Ch Ch Ch Ch

...

Ch Ch Ch Ch Ch Ch Ch

0

1

0

1

0

1

0

1

0

1

0

1

AVAILABLE SCREEN SPACE

Notes: FT. The format character required for each line. Characters in columns1 through 20 are displayed.

Ch. (Byte) Character (Index into OSD character generator) or space character

Emulator Remarks

There are few differences between emulator and

silicon. For noise reasons, the OSD oscillator pins

are not available: the internal oscillator can not be

disabled and replaced by an external coil.

56/82

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389

ON-SCREEN DISPLAY (Cont’d)

4.8.3 Application Notes

4 - The timing of the on/off switching of the OSD

oscillator is the following:

1- The OSD character generator is composed of a

dual port video ram and some circuitry. It needs

two input signals VSYNC and HSYNC to synchro-

nize its dedicated oscillator to the TV picture. It

generates 4 output signals, that can be used from

the TV set to generate the characters on the

screen. For instance, they can be used to feed the

SCART plug, providing an adequate buffer to drive

the low impedance (75 ohm) of the SCART inputs.

a. GE bit is set. The OSD oscillator will start on

the next VSYNC signal.

b. GE bit is reset. The OSD oscillator will be im-

mediately switched off.

To avoid a bad visual impression, it is important

that the GE bit is set before the end of the flyback

time when changing characters. This can be done

inside the VSYNC interrupt routine. The following

diagram can explain better: OSD Oscillator ON/

OFF Timing

2 - The Core sees the OSD as a number of RAM

locations (168) plus a certain number of control

registers (8). 175 of these locations are mapped in

one page of the dynamic data ram address range

(0h...3Fh).

Figure 32. OSD Oscillator ON/OFF Timing

VSYNC

The page 5 (20h value loaded into the register

0E8h) is further subdivided in 4 pages (using bits

LS1 and LS0) in order to allow access to all 168

bytes of the OSD RAM within the allowed address

range. According to the value of these two bits we

shall a first line (selected among lines 0, 2, 4 or 6)

mapped onto the 0h-14h address range, and a

second line (selected among lines 1, 3, 5 or 7)

mapped onto the 20h-34h address range.

B

V

C

V

E

V

time

The global registers in page 5 are accessible at

RAM locations 38h-3Fh, page 5 selected via DR-

BR, regardless of the value of the LS0/LS1 bits.

A

D

VA00344

3 - The video RAM is a dual port ram. That means

that it can be addressed either from the Core or

from the OSD circuitry itself. To reduce the com-

plexity of the circuitry, and thus its cost, some re-

strictions have been introduced in the use of the

OSD.

Notes:A - Picture time: 20 mS in PAL/SECAM.

B - VSYNC interrupt, if enabled.

C - Starting of OSD oscillator, if GE = 1.

D - Flyback time.

When modifying the picture display (i.e.: a bar

graph for an analog control), it is important that the

switching on of the GE bit is done before the end

of the flyback time (D in Figure 32). If the GE bit is

set after the end of the flyback time then the OSD

will not start until the beginning of the next frame.

This results in one frame being lost and will result

in a flicker on the screen. One method to be sure

to avoid the flicker is to wait for the VSYNC inter-

rupt at the start of the flyback; once the VSYNC in-

terrupt is detected, then the GE and ORE bits can

be set to zero, the global control registers

changed, if necessary, and the GE set to one. All

this should occur before the end of the flyback time

in order not to lose a frame. The correct edge of

the interrupt must be chosen. The characters in

RAM can be changed until the last line before the

active screen area and then the ORE bit must be

set.

a. The Core can access 6 of the global registers

(addresses 38h - 3Dh in page 5) only when the

OSD oscillator is OFF (GE bit not set). Only

the last location (control register 3Fh in page

5) can be addressed at any time. This is the

Global Enable Register, which contains the

GE and ORE bits. If the GE bit is set, the OSD

is on, if it is reset the OSD is off.

c. The Core can write to the 168 locations of

OSD RAM only when the ORE bit is not set.

This bit must be set before the first active line

of OSD display (which displays characters).

This line follows the VSYNC active period and

is delayed by a time equal to the Vertical Start

register value multiplied by the duration of one

display line (64 µs for the usual TV standard).

57/82

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389

ON-SCREEN DISPLAY (Cont’d)

The VSYNC pin may alternatively be sampled by

software in order to know the status; this can be

done by reading bit 4 of register E4h; this bit is in-

verted with respect to the VSYNC pin.

4.10 XOR REGISTER

This an 8-bits Register at address DFh. It is unde-

fined on Reset. To compute the XOR of two 8-bits

values, the user has to write the first value in the

MIRROR register (DEh) and then the second val-

ue in the XOR register (DFh). After that the XOR

result can be read from the XOR register.

6- The OSD oscillator external network should

consist of a capacitor on each of the OSD oscilla-

tor pins to ground together with an inductance be-

tween pins. The user should select the two capac-

itors to be the same value (15pF to 25pF each is

recommended). The inductance is chosen to give

the desired OSD oscillator frequency for the appli-

cation (typically 56µH).

To compute a new XOR with the result of the pre-

vious operation, the user can directly write the sec-

ond value in the XOR register and read the XOR

result in this same register.

Note: writing the XOR register affects the value of

the MIRROR register also.

4.9 MIRROR REGISTER

This an 8-bits Register at address DEh. It is unde-

fined on Reset. After writing, the read value is the

reversed byte:

Bit0->Bit7, Bit1->Bit6, Bit2->Bit5, Bit3->Bit4,

Bit4->Bit3, Bit5->Bit2, Bit6->Bit1, Bit7->Bit0

Note: Writing the XOR register affects the value of

this register.

58/82

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389

5 SOFTWARE

5.1 ST6 ARCHITECTURE

The ST6 software has been designed to fully use

the hardware in the most efficient way possible

while keeping byte usage to a minimum; in short,

to provide byte efficient programming capability.

The ST6 core has the ability to set or clear any

register or RAM location bit of the Data space with

a single instruction. Furthermore, the program

may branch to a selected address depending on

the status of any bit of the Data space. The carry

bit is stored with the value of the bit when the SET

or RES instruction is processed.

bits of the opcode with the byte following the op-

code. The instructions (JP, CALL) which use the

extended addressing mode are able to branch to

any address of the 4K bytes Program space.

An extended addressing mode instruction is two-

byte long.

Program Counter Relative. The relative address-

ing mode is only used in conditional branch in-

structions. The instruction is used to perform a test

and, if the condition is true, a branch with a span of

-15 to +16 locations around the address of the rel-

ative instruction. If the condition is not true, the in-

struction which follows the relative instruction is

executed. The relative addressing mode instruc-

tion is one-byte long. The opcode is obtained in

adding the three most significant bits which char-

acterize the kind of the test, one bit which deter-

mines whether the branch is a forward (when it is

0) or backward (when it is 1) branch and the four

less significant bits which give the span of the

branch (0h to Fh) which must be added or sub-

tracted to the address of the relative instruction to

obtain the address of the branch.

5.2 ADDRESSING MODES

The ST6 core offers nine addressing modes,

which are described in the following paragraphs.

Three different address spaces are available: Pro-

gram space, Data space, and Stack space. Pro-

gram space contains the instructions which are to

be executed, plus the data for immediate mode in-

structions. Data space contains the Accumulator,

the X,Y,V and W registers, peripheral and Input/

Output registers, the RAM locations and Data

ROM locations (for storage of tables and con-

stants). Stack space contains six 12-bit RAM cells

used to stack the return addresses for subroutines

and interrupts.

Bit Direct. In the bit direct addressing mode, the

bit to be set or cleared is part of the opcode, and

the byte following the opcode points to the ad-

dress of the byte in which the specified bit must be

set or cleared. Thus, any bit in the 256 locations of

Data space memory can be set or cleared.

Immediate. In the immediate addressing mode,

the operand of the instruction follows the opcode

location. As the operand is a ROM byte, the imme-

diate addressing mode is used to access con-

stants which do not change during program execu-

tion (e.g., a constant used to initialize a loop coun-

ter).

Bit Test & Branch. The bit test and branch ad-

dressing mode is a combination of direct address-

ing and relative addressing. The bit test and

branch instruction is three-byte long. The bit iden-

tification and the tested condition are included in

the opcode byte. The address of the byte to be

tested follows immediately the opcode in the Pro-

gram space. The third byte is the jump displace-

ment, which is in the range of -127 to +128. This

displacement can be determined using a label,

which is converted by the assembler.

Direct. In the direct addressing mode, the address

of the byte which is processed by the instruction is

stored in the location which follows the opcode. Di-

rect addressing allows the user to directly address

the 256 bytes in Data Space memory with a single

two-byte instruction.

Short Direct. The core can address the four RAM

registers X,Y,V,W (locations 80h, 81h, 82h, 83h) in

the short-direct addressing mode. In this case, the

instruction is only one byte and the selection of the

location to be processed is contained in the op-

code. Short direct addressing is a subset of the di-

rect addressing mode. (Note that 80h and 81h are

also indirect registers).

Indirect. In the indirect addressing mode, the byte

processed by the register-indirect instruction is at

the address pointed by the content of one of the in-

direct registers, X or Y (80h,81h). The indirect reg-

ister is selected by the bit 4 of the opcode. A regis-

ter indirect instruction is one byte long.

Inherent. In the inherent addressing mode, all the

information necessary to execute the instruction is

contained in the opcode. These instructions are

one byte long.

Extended. In the extended addressing mode, the

12-bit address needed to define the instruction is

obtained by concatenating the four less significant

59/82

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389

5.3 INSTRUCTION SET

The ST6 core offers a set of 40 basic instructions

which, when combined with nine addressing

modes, yield 244 usable opcodes. They can be di-

vided into six different types: load/store, arithme-

tic/logic, conditional branch, control instructions,

jump/call, and bit manipulation. The following par-

agraphs describe the different types.

Load & Store. These instructions use one, two or

three bytes in relation with the addressing mode.

One operand is the Accumulator for LOAD and the

other operand is obtained from data memory using

one of the addressing modes.

For Load Immediate one operand can be any of

the 256 data space bytes while the other is always

immediate data.

All the instructions belonging to a given type are

presented in individual tables.

Table 21. Load & Store Instructions

Flags

Instruction

LD A, X

Addressing Mode

Short Direct

Bytes

Cycles

Z

∆

*

C

*

1

2

1

2

3

4

LD A, Y

LD A, V

LD A, W

LD X, A

LD Y, A

Short Direct

Direct

LD V, A

LD W, A

LD A, rr

LD rr, A

Direct

LD A, (X)

LD A, (Y)

LD (X), A

LD (Y), A

LDI A, #N

LDI rr, #N

Indirect

Immediate

Notes:

X,Y. Indirect Register Pointers, V & W Short Direct Registers

# . Immediate data (stored in ROM memory)

rr. Data space register

∆. Affected

* . Not Affected

60/82

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389

INSTRUCTION SET (Cont’d)

Arithmetic and Logic. These instructions are

used to perform the arithmetic calculations and

logic operations. In AND, ADD, CP, SUB instruc-

tions one operand is always the accumulator while

the other can be either a data space memory con-

tent or an immediate value in relation with the ad-

dressing mode. In CLR, DEC, INC instructions the

operand can be any of the 256 data space ad-

dresses. In COM, RLC, SLA the operand is always

the accumulator.

Table 22. Arithmetic & Logic Instructions

Flags

Instruction

ADD A, (X)

Addressing Mode

Indirect

Bytes

Cycles

Z

∆

*

C

∆

*

1

2

1

2

3

1

2

1

2

1

2

1

2

1

2

4

ADD A, (Y)

ADD A, rr

ADDI A, #N

AND A, (X)

AND A, (Y)

AND A, rr

ANDI A, #N

CLR A

Indirect

Direct

Immediate

Indirect

Direct

Immediate

Short Direct

Direct

CLR r

COM A

Inherent

Indirect

∆

*

CP A, (X)

CP A, (Y)

CP A, rr

CPI A, #N

DEC X

Indirect

Direct

Immediate

Short Direct

Direct

DEC Y

*

DEC V

*

DEC W

*

DEC A

*

DEC rr

Direct

*

DEC (X)

DEC (Y)

INC X

Indirect

*

Indirect

*

Short Direct

Direct

*

INC Y

*

INC V

*

INC W

*

INC A

*

INC rr

Direct

*

INC (X)

Indirect

*

INC (Y)

Indirect

*

RLC A

Inherent

Indirect

∆

SLA A

SUB A, (X)

SUB A, (Y)

SUB A, rr

SUBI A, #N

Indirect

Direct

Immediate

Notes:

X,Y.Indirect Register Pointers, V & W Short Direct RegistersD. Affected

# . Immediate data (stored in ROM memory)* . Not Affected

rr. Data space register

61/82

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389

INSTRUCTION SET (Cont’d)

Conditional Branch. The branch instructions

achieve a branch in the program when the select-

ed condition is met.

Control Instructions. The control instructions

control the MCU operations during program exe-

cution.

Bit Manipulation Instructions. These instruc-

tions can handle any bit in data space memory.

One group either sets or clears. The other group

(see Conditional Branch) performs the bit test

branch operations.

Jump and Call. These two instructions are used

to perform long (12-bit) jumps or subroutines call

inside the whole program space.

Table 23. Conditional Branch Instructions

Flags

Instruction

Branch If

Bytes

Cycles

Z

*

C

*

JRC e

C = 1

1

3

2

5

JRNC e

C = 0

Z = 1

*

JRZ e

*

JRNZ e

Z = 0

*

JRR b, rr, ee

JRS b, rr, ee

Bit = 0

Bit = 1

∆

Notes:

b.

e.

3-bit address

rr. Data space register

∆ . Affected. The tested bit is shifted into carry.

5 bit signed displacement in the range -15 to +16<F128M>

ee. 8 bit signed displacement in the range -126 to +129

* . Not Affected

Table 24. Bit Manipulation Instructions

Flags

Instruction

Addressing Mode

Bytes

Cycles

Z

C

*

SET b,rr

Bit Direct

2

4

*

RES b,rr

*

Notes:

b.

3-bit address;

* . Not<M> Affected

rr. Data space register;

Table 25. Control Instructions

Flags

Instruction

Addressing Mode

Bytes

Cycles

Z

*

C

*

NOP

Inherent

1

2

RET

*

RETI

∆

*

∆

*

STOP (1)

WAIT

*

Notes:

1.

This instruction is deactivated<N>and a WAIT is automatically executed instead of a STOP if the watchdog function is selected.

∆ . Affected

*.

Not Affected

Table 26. Jump & Call Instructions

Instruction

Flags

Addressing Mode

Bytes

Cycles

Z

*

C

*

CALL abc

JP abc

Extended

2

4

*

Notes:

abc. 12-bit address;

* . Not Affected

62/82

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389

Opcode Map Summary. The following table contains an opcode map for the instructions used by the ST6

LOW

0

1

2

3

0011

4

5

6

0110

7

0111

0000

0001

0010

0100

0101

HI

2

JRNZ 4

CALL 2

abc

ext 1

CALL 2

abc

ext 1

CALL 2

abc

ext 1

CALL 2

abc

ext 1

CALL 2

abc

ext 1

CALL 2

abc

ext 1

CALL 2

abc

ext 1

CALL 2

abc

ext 1

CALL 2

abc

ext 1

CALL 2

abc

ext 1

CALL 2

abc

ext 1

CALL 2

abc

ext 1

CALL 2

abc

ext 1

CALL 2

abc

ext 1

CALL 2

abc

ext 1

CALL 2

abc

JRNC

5

JRR 2

b0,rr,ee

bt 1

JRS 2

b0,rr,ee

bt 1

JRR 2

b4,rr,ee

JRZ

2

JRC 4

LD

0

e

#

x

e

a,(x)

a,nn

0000

1

2

pcr 2

JRNZ 4

pcr 3

JRNC

pcr

JRZ 4

1

prc 1

JRC 4

ind

LDI

5

INC 2

1

0001

1

2

pcr 2

JRNZ 4

pcr 3

JRNC

pcr 1

JRZ

sd

1

2

prc 2

JRC 4

imm

CP

5

2

#

a,(x)

0010

1

2

pcr 2

JRNZ 4

pcr 3

JRNC

bt 1

JRS 2

pcr

JRZ 4

1

2

prc 1

JRC 4

ind

CPI

5

LD

sd

3

0011

3

0011

b4,rr,ee

e

bt 1

a,x

#

a,nn

1

2

pcr 2

JRNZ 4

pcr 3

JRNC

pcr 1

JRZ

1

2

prc 2

JRC 4

imm

ADD

a,(x)

5

JRR 2

b2,rr,ee

bt 1

JRS 2

b2,rr,ee

bt 1

JRR 2

b6,rr,ee

bt 1

JRS 2

b6,rr,ee

bt 1

JRR 2

b1,rr,ee

bt 1

JRS 2

b1,rr,ee

bt 1

JRR 2

b5,rr,ee

bt 1

JRS 2

b5,rr,ee

bt 1

JRR 2

b3,rr,ee

bt 1

JRS 2

b3,rr,ee

bt 1

JRR 2

b7,rr,ee

bt 1

JRS 2

b7,rr,ee

4

e

0100

1

2

pcr 2

JRNZ 4

pcr 3

JRNC

pcr

JRZ 4

1

prc 1

JRC 4

ind

ADDI

5

INC 2

5

y

a,nn

0101

1

2

pcr 2

JRNZ 4

pcr 3

JRNC

pcr 1

JRZ

sd

1

2

prc 2

JRC 4

imm

INC

5

6

0110

6

0110

#

(x)

#

1

2

pcr 2

JRNZ 4

pcr 3

JRNC

pcr

JRZ 4

1

2

prc 1

JRC

ind

5

LD

sd

7

0111

7

0111

a,y

#

1

2

pcr 2

JRNZ 4

pcr 3

JRNC

pcr 1

JRZ

1

2

prc

JRC 4

5

LD

ind

8

(x),a

#

1000

1

2

pcr 2

pcr 3

JRNC

pcr

JRZ 4

1

prc 1

JRC

RNZ

e

4

5

INC 2

9

v

1001

1

2

pcr 2

JRNZ 4

pcr 3

JRNC

pcr 1

JRZ

sd

1

2

prc

JRC 4

5

AND

a,(x)

A

1010

A

1010

e

#

1

2

pcr 2

JRNZ 4

pcr 3

JRNC

pcr

JRZ 4

1

2

prc 1

JRC 4

ind

ANDI

5

LD

sd

B

1011

B

1011

a,v

#

a,nn

1

2

pcr 2

JRNZ 4

pcr 3

JRNC

pcr 1

JRZ

1

2

prc 2

JRC 4

imm

SUB

5

C

1100

C

1100

a,(x)

1

2

pcr 2

JRNZ 4

pcr 3

JRNC

pcr

JRZ 4

1

prc 1

JRC 4

ind

SUBI

5

INC 2

D

1101

D

1101

w

a,nn

1

2

pcr 2

JRNZ 4

pcr 3

JRNC

pcr 1

JRZ

sd

1

2

prc 2

JRC 4

imm

DEC

5

E

1110

E

1110

#

(x)

#

1

2

pcr 2

JRNZ 4

pcr 3

JRNC

pcr

JRZ 4

1

2

prc 1

JRC

ind

5

LD

sd

F

1111

F

1111

a,w

1

pcr 2

ext 1

pcr 3

bt 1

pcr 1

1

prc

Abbreviations for Addressing Modes: Legend:

dir

sd

Direct

Short Direct

#

e

b

rr

nn

Indicates Illegal Instructions

5 Bit Displacement

3 Bit Address

1byte dataspace address

1 byte immediate data

Cycle

Mnemonic

2

e

1

JRC

prc

Operand

imm Immediate

inh

ext

b.d

bt

Inherent

Extended

Bit Direct

Bit Test

Bytes

abc 12 bit address

ee 8 bit Displacement

Addressing Mode

pcr

ind

Program Counter Relative

Indirect

63/82

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389

Opcode Map Summary (Continued)

LOW

8

9

A

1010

B

1011

C

1100

D

1101

E

1110

F

1111

1000

1001

HI

2

JRNZ 4

JP 2

JRNC

4

RES 2

b0,rr

b.d 1

SET 2

b0,rr

b.d 1

RES 2

b4,rr

JRZ 4

LDI 2

JRC 4

LD

0

e

abc

e

rr,nn

e

a,(y)

a,rr

0000

1

2

pcr 2

JRNZ 4

ext 1

JP 2

pcr 2

JRNC

pcr 3

JRZ 4

imm 1

prc 1

JRC 4

ind

LD

4

DEC

2

1

x

a

0001

1

2

pcr 2

JRNZ 4

ext 1

JP 2

pcr 2

JRNC

pcr 1

JRZ 4

sd

1

prc 2

JRC 4

dir

CP

4

COM 2

1

2

a,(y)

a,rr

0010

1

2

pcr 2

JRNZ 4

ext 1

JP 2

pcr 2

JRNC

b.d 1

SET 2

pcr

JRZ 4

prc 1

JRC 4

ind

CP

4

LD

2

3

0011

3

0011

b4,rr

e

b.d 1

x,a

1

2

pcr 2

JRNZ 4

ext 1

JP 2

pcr 2

JRNC

pcr 1

JRZ 2

sd

1

prc 2

JRC 4

dir

ADD

a,(y)

4

RES 2

b2,rr

b.d 1

SET 2

b2,rr

b.d 1

RES 2

b6,rr

b.d 1

SET 2

b6,rr

b.d 1

RES 2

b1,rr

b.d 1

SET 2

b1,rr

b.d 1

RES 2

b5,rr

b.d 1

SET 2

b5,rr

b.d 1

RES 2

b3,rr

b.d 1

SET 2

b3,rr

b.d 1

RES 2

b7,rr

b.d 1

SET 2

b7,rr

RETI 2

inh 1

4

e

0100

1

2

pcr 2

JRNZ 4

ext 1

JP 2

pcr 2

JRNC

pcr 1

JRZ 4

prc 1

JRC 4

ind

ADD

4

DEC

2

5

y

a,rr

(y)

rr

0101

1

2

pcr 2

JRNZ 4

ext 1

JP 2

pcr 2

JRNC

pcr 1

JRZ 2

sd

1

prc 2

JRC 4

dir

INC

4

STOP 2

inh 1

6

0110

6

0110

1

2

pcr 2

JRNZ 4

ext 1

JP 2

pcr 2

JRNC

pcr 1

JRZ 4

prc 1

JRC 4

ind

INC

4

LD

2

7

0111

7

0111

y,a

#

1

2

pcr 2

JRNZ 4

ext 1

JP 2

pcr 2

JRNC

pcr 1

JRZ

sd

1

2

prc 2

JRC 4

dir

LD

4

8

(y),a

rr,a

1000

1

2

pcr 2

ext 1

JP 2

pcr 2

JRNC

pcr

JRZ 4

1

2

prc 1

JRC 4

ind

LD

RNZ

e

4

DEC

sd

9

v

1001

1

2

pcr 2

JRNZ 4

ext 1

JP 2

pcr 2

JRNC

pcr 1

JRZ 4

1

prc 2

JRC 4

dir

AND

a,(y)

4

RCL 2

A

1010

A

1010

e

a

1

2

pcr 2

JRNZ 4

ext 1

JP 2

pcr 2

JRNC

pcr 1

JRZ 4

inh 1

prc 1

JRC 4

ind

AND

4

LD

sd

2

1

B

1011

B

1011

v,a

a,rr

1

2

pcr 2

JRNZ 4

ext 1

JP 2

pcr 2

JRNC

pcr 1

JRZ 2

prc 2

JRC 4

dir

SUB

4

RET 2

C

1100

C

1100

a,(y)

1

2

pcr 2

JRNZ 4

ext 1

JP 2

pcr 2

JRNC

pcr 1

JRZ 4

inh 1

prc 1

JRC 4

ind

SUB

4

DEC

sd

2

1

D

1101

D

1101

w

a,rr

(y)

rr

1

2

pcr 2

JRNZ 4

ext 1

JP 2

pcr 2

JRNC

pcr 1

JRZ 2

prc 2

JRC 4

dir

DEC

4

WAIT 2

E

1110

E

1110

1

2

pcr 2

JRNZ 4

ext 1

JP 2

pcr 2

JRNC

pcr 1

JRZ 4

inh 1

prc 1

JRC 4

ind

DEC

4

LD

sd

2

1

F

1111

F

1111

w,a

1

pcr 2

ext 1

pcr 2

b.d 1

pcr 1

prc 2

dir

Abbreviations for Addressing Modes: Legend:

dir

sd

Direct

Short Direct

#

e

b

rr

nn

Indicates Illegal Instructions

5 Bit Displacement

3 Bit Address

1byte dataspace address

1 byte immediate data

Cycle

Mnemonic

2

e

1

JRC

prc

Operand

imm Immediate

inh

ext

b.d

bt

Inherent

Extended

Bit Direct

Bit Test

Bytes

abc 12 bit address

ee 8 bit Displacement

Addressing Mode

pcr

ind

Program Counter Relative

Indirect

64/82

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389

6 ELECTRICAL CHARACTERISTICS

6.1 ABSOLUTE MAXIMUM RATINGS

This product contains devices to protect the inputs

against damage due to high static voltages, how-

ever it is advised to take normal precaution to

avoid application of any voltage higher than maxi-

mum rated voltages.

Power Considerations.The average chip-junc-

tion temperature, Tj, in Celsius can be obtained

from:

Tj=

TA + PD x RthJA

Where: TA =

Ambient Temperature.

For proper operation it is recommended that VI

RthJA =Package thermal resistance

(junction-to ambient).

PD = Pint + Pport.

and VO must be higher than V and smaller than

SS

V

. Reliability is enhanced if unused inputs are

DD

connected to an appropriated logic voltage level

(V or V ).

Pint = IDD x V (chip internal pow-

DD

SS

er).

Pport = Port power dissipation

(determined by the user).

Symbol

Parameter

Value

Unit

V

V_DD

V_I

Supply Voltage

-0.3 to 7.0

Input Voltage (ADC IN)

V_SS- 0.3 to +13

V

V_I

Input Voltage (Other inputs)

V_SS- 0.3 to V + 0.3

V

DD

V_O

I_O

Output Voltage (PA4-PA7, PC4-PC7, DA0-DA5)

Output Voltage (Other outputs)

V_SS- 0.3 to +13

V

V_SS- 0.3 to V + 0.3

V

DD

Current Drain per Pin Excluding V , V_SS, PA6, PA7

+ 10

+ 50

mA

°C

DD

I_O

Current Drain per Pin (PA6-PA7)

IV

Total Current into V (source)

50

DD

IV_SS

T_j

Total Current out of V_SS(sink)

Junction Temperature

150

T_STG

Storage Temperature

-60 to 150

Note: Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only

and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may

affect device reliability.

THERMAL CHARACTERISTICS

Value

Typ.

Symbol

RthJA

Parameter

Test Conditions

Unit

°C/W

Min.

Max.

Thermal Resistance

PSDIP42

67

6.2 RECOMMENDED OPERATING CONDITIONS

Value

Symbol

Parameter

Operating Temperature

Test Conditions

Unit

Min.

Typ.

Max.

70

T_A

1 Suffix Versions

0

°C

V

Operating Supply Voltage

4.5

5.0

8

6.0

DD

Oscillator Frequency

RUN & WAIT Modes

f_OSC

8.1

8.0

MHz

f_OSDOSCOn-screen Display Oscillator Frequency

EEPROM INFORMATION

The ST63xx EEPROM single poly process has been specially developed to achieve 300.000 Write/Erase

cycles and a 10 years data retention.

65/82

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389

6.3 DC ELECTRICAL CHARACTERISTICS

(TA = 0 to +70°C unless otherwise specified).

Table 27: DC ELECTRICAL CHARACTERISTICS

Value

Typ.

Symbol

Parameter

Test Conditions

All I/O Pins

Unit

Min.

Max.

V

Input Low Level Voltage

Input High Level Voltage

0.2xV

V

IL

DD

V

0.8xV

IH

DD

(1)

V

Hysteresis Voltage

1.0

V

HYS

V

= 5V

DD

DA0-DA5, PB0-PB6, OSD

Outputs, PC0-PC7,

O0, O1, PA0-PA5

V

Low Level Output Voltage

OL

V

_DD= 4.5V

I

_OL= 1.6mA

_OL= 5.0mA

0.4

1.0

V

PA6-PA7

= 4.5V

V

DD

V

Low Level Output Voltage

High Level Output Voltage

OL

OH

I

= 1.6mA

= 25mA

0.4

1.0

V

OL

OSDOSCout

OSCout

V

0.4

V

= 4.5V

DD

I

= 0.4mA

OL

VS Output

= 4.5V

V

DD

I

= 0.5mA

= 1.6mA

0.4

1.0

V

OL

PB0-PB6, PA0-PA3, OSD

Outputs

V

4.1

V

= 4.5V

DD

I

= – 1.6mA

OH

OSDOSCout, OSCout,

= 4.5V

V

High Level Output Voltage

V

4.1

V

OH

DD

I

= – 0.4mA

OH

VS Output

= 4.5V

V

OH

DD

I

= - 0.5mA

OH

PB0-PB6, PA0-PA3,

PC0-PC3,

Input Pull Up Current

Input Mode with Pull-up

I

– 100

– 50

– 25

– 10

µA

PU

V

= V

IN

SS

OSCin

Input Pull Up Current

Input Leakage Current

µA

PU

V

= V

IN

SS

OSCin

I

IL

V

= V

– 10

0.1

– 1

1

– 0.1

10

IN

SS

DD

IH

Input Pull-down

current in RESET

I

OSCin

100

IL

All I/O Input Mode

no pull-up

OSDOSCin

I

IL

Input Leakage Current

-10

10

µA

I

IH

V

= V or V

IN

DD SS

RAM Retention Voltage in

RESET Mode

V

RAM

1.5

V

DD

I

Reset Pin with Pull-up

V = V

IN

IL

Input Leakage Current

– 50

– 30

– 10

µA

I

IH

SS

66/82

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389

Table 27: DC ELECTRICAL CHARACTERISTICS

Value

Typ.

Symbol

Parameter

Test Conditions

Unit

Min.

Max.

DA0-DA5, PA4-PA5,

PC0-PC7, O0, O1

I

Output Leakage Current

10

µA

OH

V

= V

OH

DD

DA0-DA5, PA4-PA7,

PC4-PC7, O0, O1

Output Leakage Current High Volt-

age

I

40

µA

V

= 12V

OH

f

V

= 8MHz, ILoad= 0mA

= 6.0V

= 8MHz, ILoad= 0mA

= 6V

OSC

I

Supply Current RUN Mode

Supply Current WAIT Mode

6

3

16

10

mA

DD

f

OSC

DD

V

DD

f

= Not App,

OSC

Supply Current at transition to

RESET

I

ILoad= 0mA

= 6V

0.1

1

mA

DD

V

DD

V

Reset Trigger Level ON

Reset Trigger Level OFF

RESET Pin

0.3xV

V

ON

DD

V

0.8xV

DD

OFF

A/D AFC Pin

Relative to other levels

(1)

V

Input Level Relatice Tolerance

± 100

mV

TR

V

= 5V

DD

Note 1. Not 100% Tested

67/82

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389

6.4 AC ELECTRICAL CHARACTERISTICS

(TA = 0 to +70°C, f

=8MHz, V =4.5 to 6.0V unless otherwise specified)

DD

OSC

Value

Typ.

Symbol

Parameter

Test Conditions

Unit

ns

Min.

Max.

t

Minimum Pulse Width

RESET Pin

PA6, PA7

= 5V, CL = 100pF

125

WRES

t

High to Low Transition Time

100

20

ns

(2)

OHL

V

DD

DA0-DA5, PB0-PB6, OSD

Outputs, PC0-PC7

t

High to Low Transition Time

ns

OHL

V

= 5V, CL = 100pF

DD

PB0-PB6, PA0-PA3, OSD

Outputs, PC0-PC3

t

Low to High Transition Time

D/A Converter Repetition Fre-

20

ns

OLH

V

= 5V, CL = 100pF

DD

f_DA

31.25

kHz

(1)

quency

(1)

f_SIO

SIO Baudrate

62.50

kHz

t

EEPROM Write Time

T

= 25°C One Byte

A

5

10

ms

WEE

EEPROM WRITE/ERASE Cy-

cles

Q

L

> 1

million

A

OT

Endurance

Retention

300,000

10

cycles

Acceptance Criteria

(4)

EEPROM Data Retention

T

= 25°C

years

pF

A

(3)

C

Input Capacitance

All Inputs Pins

10

IN

(3)

C

Output Capacitance

All Outputs Pins

pF

OUT

COSCin,

COSCout

COSDin,

COSDout

Oscillator Pins Internal

Capacitance

5

pF

(3)

Oscillator Pins External

Recommended

15

25

(3)

Capacitance

Notes:

1. A clock other than 8MHz will affect the frequency response of those peripherals (D/A, and SPIs) whose clock is derived from the system

clock.

2. The rise and fall times of PORT A have been increased in order to avoid current spikes while maintaining a high drive capability

3. Not 100% Tested

4. Based on extrapolated data

68/82

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389

7 GENERAL INFORMATION

7.1 PACKAGE MECHANICAL DATA

Figure 33. 42-Pin Plastic Shrink Dual-In-Line Package

mm

Min Typ Max Min Typ Max

5.08 0.200

inches

Dim.

A

A1 0.51

0.020

E

A2 3.05 3.81 4.57 0.120 0.150 0.180

A2

A

L

A1

b

b2

C

0.46 0.56

1.02 1.14

0.018 0.022

0.040 0.045

C

E1

eA

eB

e

0.23 0.25 0.38 0.009 0.010 0.015

36.58 36.83 37.08 1.440 1.450 1.460

b

b2

D

E

15.24

16.00 0.600

0.630

.015

E1 12.70 13.72 14.48 0.500 0.540 0.570

GAGE PLANE

e

1.78

0.070

0.600

eA

eB

eC

L

15.24

LEAD DETAIL

eB

VR01725G

eC

18.54

0.730

0.060

1.52 0.000

2.54 3.30 3.56 0.100 0.130 0.140

Number of Pins

N

42

7.2 ORDERING INFORMATION

The following chapter deals with the procedure for

transfer the Program/Data ROM codes to STMi-

croelectronics.

the EEPROM initial content (this file is optional).

– two files in INTEL...FORMAT for the OSD font

memory

Communication of the ROM Codes. To commu-

nicate the contents of Program/Data ROM memo-

ries to STMicroelectronics, the customer must

send:

– the option list described below.

The program ROM should respect the ROM Mem-

ory Map as in Table 4 on page 10.

– one file in INTEL INTELLEC 8/MDS FORMAT for

the PROGRAM Memory;

The ROM code must be generated with an ST6

assembler. Before programming the EPROM, the

EPROM programmer buffer must be filled with

FFh.

– one file in INTEL INTELLEC 8/MDS FORMAT for

69/82

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389

GENERAL INFORMATION (Cont’d)

7.3 CUSTOMER EEPROM INITIAL CONTENTS:

a. The content should be written into an INTEL

INTELLEC format file.

Figure 34. OSD Test Character

b In the case of 384 bytes of EEPROM, the start-

ing address is 000h and the end address is

17Fh. The order of the pages (64 bytes each) is

an in the specification (i.e. b7, b1 b0: 001, 010,

011, 101, 110. 111).

1

2

3

4

5

6

7

8

9 10 11 12 13 14

1

2

3

4

c. Undefined or don't care bytes should have the

content FFh.

5

6

7

7.4 OSD Test Character

8

IN ORDER TO ALLOW THE TESTING OF THE

ON-CHIP OSD MACROCELL THE FOLLOWING

CHARACTER MUST BE PROVIDED AT THE

FIXED BFh (191) POSITION.

9

10

11

12

13

14

15

16

17

18

Listing Generation & Verification. When STMi-

croelectronics receives the files, a computer listing

is generated from them. This listing refers extractly

to the mask that will be used to produce the micro-

controller. Then the listing is returned to the cus-

tomer that must thoroughly check, complete, sign

and return it to STMicroelectronics. The signed list

constitutes a part of the contractual agreement for

the creation of the customer mask. STMicroelec-

tronics sales organization will provide detailed in-

formation on contractual points.

7.5 ORDERING INFORMATION TABLE

D/ A

Converter

Sales Type

ROM/ EEPROM Size

Temperature Range

Package

ST6380B1/ XXX

ST6380B4/ XXX

ST6381B1/ XXX

ST6381B4/ XXX

ST6382B1/ XXX

ST6382B4/ XXX

ST6383B1/ XXX

ST6383B4/ XXX

ST6388B1/ XXX

ST6388B4/ XXX

ST6389B1/ XXX

ST6389B4/ XXX

8K/ 384 Bytes

14K/ 384 Bytes

20K/ 384 Bytes

6

4

6

4

6

4

0 to + 70 °C

-10 to + 70 °C

0 to + 70 °C

-10 to + 70 °C

0 to + 70 °C

-10 to + 70 C

0 to + 70 °C

-10 to + 70 °C

0 to + 70 °C

-10 to + 70 °C

0 to + 70 °C

-10 to + 70 °C

PSDIP42

Note: “XXX” Is the ROM code identifier that is allocated by STMicroelectronics after receipt of all required

options and the related ROM file.

70/82

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389

ST63 ROM MICROCONTROLLER FAMILY

OPTION LIST

Customer ................................................................

Address ................................................................

Contact ................................................................

Phone No ................................................................

Reference ...............................................................

ST638X SERIES

Device (Put a cross on selected item) :

ST6365 [ ]

ST6367 [ ]

ST6375 [ ]

ST6377 [ ]

ST6381 [ ]

ST6380 [ ]

ST6368 [ ]

ST6383 [ ]

ST6382 [ ]

ST6389 [ ]

ST6388 [ ]

ST6378 [ ]

[ ] (p)

ST6385 [ ]

ST6387 [ ]

Package

Temperature Range [ ] (t)

Special Marking [ ] (y/n)

Line 1 ".............." (N)

Line 2 ".............." (N)

Line 3 ".............." (N)

Traceability marking (mandatory)

(p) B = Dual in Line Plastic

T = Thin Quad Flat (not available on all products)

(t) 1 =

0 to +70 C

4 = -10 to +70 C

(only for ST6368/78/80/81/82/83/88/89)

(N) Letters, digits, ’.’, ’-’, ’/’ and spaces only

ST638X OPTION LIST

OSD Polarity Options (Put a cross on selected item) :

(No option list for ST6380/81/82/83/88/89)

POSITIVE

[ ]

NEGATIVE

[ ]

VSYNC, HSYNC

R,G,B

[ ]

BLANK

[ ]

ST638X CHECK LIST

YES

[ ]

NO

[ ]

ROM CODE

OSD Code: ODD & EVEN

OSD Code:

[ ] For ST6365/67/75/77/85/87

[ ]

[ ] For ST6368/78/80/81/82/83/88/89

[ ] Only for ST6365/67/75/77/85/87

EEPROM Code (If Desired)

Notes

..................................................................

Signature ...................

Date ..........

71/82

ST6380, ST6381, ST6382, ST6383, ST6388, ST6389

Notes:

72/82

ST63E88,ST63T88,

ST63E89,ST63T89

8-BIT MCUs WITH

ON-SCREEN-DISPLAY FOR TV TUNING

■ 4.5 to 6V supply operating range

■ 8MHz Maximum Clock Frequency

■ User Program EPROM: up to 20140 bytes

■ Reserved Test EPROM: up to 340 bytes

■ Data ROM: user selectable size

■ Data RAM: 256 bytes

■ Data EEPROM: 384 bytes

■ 42-Pin Shrink Dual in Line Plastic Package

■ Up to 22 software programmable general

purpose Inputs/Outputs, including 2 direct LED

driving Outputs

■ Two Timers each including an 8-bit counter with

a 7-bit programmable prescaler

PSDIP42

■ Digital Watchdog Function

■ Serial Peripheral Interface (SPI) supporting S-

BUS/ I 2 C BUS and standard serial protocols

■ SPI for external frequency synthesis tuning

■ 14 bit counter for voltage synthesis tuning

■ Up to Six 6-Bit PWM D/A Converters

■ One 8 bits D/A Converter with 7 analog inputs

■ Five interrupt vectors (IRIN/NMI, Timer 1 & 2,

VSYNC, PWR/ADC)

■ On-chip clock oscillator

■ 8 Lines by 20 Characters On-Screen Display

Generator with 192 Characters in one bank

■ All ROM types are supported by pin-to-pin

EPROM and OTP versions with programmable

OSD fonts.

CSDIP42

■ The development tool of the ST63T88 and

ST63T89 microcontrollers consists of the

ST638X-EMU2 emulation and development

system to be connected via a standard parallel

line to an MS-DOS Personal Computer.

(Refer to end of Document for Ordering Information)

October 2003

73/82

ST63E88,ST63T88, ST63E89,ST63T89

1 GENERAL DESCRIPTION

Table 28. Device Summary

EPROM

(Bytes)

OTP

(Bytes)

RAM

(Bytes)

EEPROM

(Bytes)

Colour

Pins

Target R0M

Devices

Device

ADC

VS

D/A

ST63E88

ST63T88

ST63T89

20K

256

384

Yes

6

4

3

ST6380, 82, 88

ST6381, 83, 89

20K

Figure 35. . Block Diagram

PA0 - PA7*

PORT A

TEST

PORT B &

A/D inputs

PB0 - PB6*

INTERRUPT

Inputs

IRIN/PC6

PC2, PC4 - PC7*

PC0/SCL

PORT C

PC1/SDA

PC3/SEN

DATA ROM

USER

SELECTABLE

Serial Peripheral

Interface

USER PROGRAM

MEMORY

DATA RAM

256 Bytes

UP TO 20KBytes

TIMER 1

TIMER 2

DATA EEPROM

384 Bytes

Digital

PC

Watchdog Timer

STACK LEVEL 1

STACK LEVEL 2

STACK LEVEL 3

STACK LEVEL 4

STACK LEVEL 5

STACK LEVEL 6

DA0 - DA5

VS*

D/A Outputs

VS Output

8 BIT CORE

On-Screen

Display

R, G, B, BLANK

HSYNC, VSYNC

POWER

RESET

OSCILLATOR

SUPPLY

OSDOSCout

OSDOSCin

V

OSCin OSCout

DD SS

*Refer to Pin Description for Additional Information

VR01753

74/82

ST63E88,ST63T88, ST63E89,ST63T89

1.1 PIN DESCRIPTION

and V . Power is supplied to the MCU using

V

open-drain (5V drive) in output mode while PC4 to

PC7 are open-drain with 12V drive and the input

pull-up options does not exist on these four pins.

PC0, PC1 and PC3 lines when in output mode are

“ANDed” with the SPI control signals and are all

open-drain. PC0 is connected to the SPI clock sig-

nal (SCL), PC1 with the SPI data signal (SDA)

while PC3 is connected with SPI enable signal

(SEN, used in S-BUS protocol). Pin PC4 and PC6

can also be inputs to software programmable edge

sensitive latches which can generate interrupts;

PC4 can be connected to Power Interrupt while

PC6 can be connected to the IRIN/NMI interrupt

line.

DD

SS

these two pins. V

ground connection.

is power and V

is the

DD

SS

OSCin, OSCout. These pins are internally con-

nected to the on-chip oscillator circuit. A quartz

crystal or a ceramic resonator can be connected

between these two pins in order to allow the cor-

rect operation of the MCU with various stability/

cost trade-offs. The OSCin pin is the input pin, the

OSCout pin is the output pin.

RESET. The active low RESET pin is used to start

the microcontroller to the beginning of its program.

Additionally the quartz crystal oscillator will be dis-

abled when the RESET pin is low to reduce power

consumption during reset phase.

DA0-DA5. These pins are the six PWM D/A out-

puts of the 6-bit on-chip D/A converters. These

lines have open-drain outputs with 12V drive. The

output repetition rate is 31.25KHz (with 8MHz

clock).

TEST/V . The TEST pin must be held at V for

PP

SS

normal operation.

If this pin is connected to a +12.5V level during the

reset phase, the EPROM programming mode is

entered.

OSDOSCin, OSDOSCout. These are the On

Screen Display oscillator terminals. An oscillation

capacitor and coil network have to be connected to

provide the right signal to the OSD.

PA0-PA7. These 8 lines are organized as one I/O

port (A). Each line may be configured as either an

input with or without pull-up resistor or as an out-

put under software control of the data direction

register. Pins PA4 to PA7 are configured as open-

drain outputs (12V drive). On PA4-PA7 pins the in-

put pull-up option is not available while PA6 and

PA7 have additional current driving capability

(25mA, VOL:1V). PA0 to PA3 pins are configured

as push-pull.

HSYNC, VSYNC. These are the horizontal and

vertical synchronization pins. The active polarity of

these pins to the OSD macrocell can be selected

by the user as ROM mask option. If the device is

specified to have negative logic inputs, then these

signals are low the OSD oscillator stops. If the de-

vice is specified to have positive logic inputs, then

when these signals are high the OSD oscillator

stops. VSYNC is also con-nected to the VSYNC

interrupt.

PB0-PB6. These 7 lines are organized as one I/O

port (B). Each line may be configured as either an

input with or without internal pull-up resistor or as

an output under software control of the data direc-

tion register. In addition any pin can be configured

by software as the input to the Analog to Digital

converter. In this case only one pin should be con-

figured at any time to avoid conflicts.

R, G, B, BLANK. Outputs from the OSD. R, G and

B are the color outputs while BLANK is the blank-

ing output. All outputs are push-pull. The active

polarity of these pins can be selected by the user

as ROM mask option.

VS. This is the output pin of the on-chip 14-bit volt-

age synthesis tuning cell (VS). The tuning signal

present at this pin gives an approximate resolution

of 40KHz per step over the UHF band. This line is

a push-pull output with standard drive.

PC0-PC7. These 8 lines are organized as one I/O

port (C). Each line may be configured as either an

input with or without internal pull-up resistor or as

an output under software control of the data direc-

tion register. Pins PC0 to PC3 are configured as

75/82

ST63E88,ST63T88, ST63E89,ST63T89

Figure 36. ST63E88, T88 Pin configuration

Figure 37. ST63E89, T89 Pin configuration

VDD

42

41

40

39

38

37

36

35

34

42

41

40

39

38

37

36

35

34

DA0

DA1

DA2

DA3

DA4

1

2

3

4

5

6

7

8

VS

DA1

DA2

DA3

DA4

1

2

3

4

5

6

7

8

PC0/SCL

PC1/SDA

PC2

PC3/SEN

PC4/PWRIN

PC5

PC0/SCL

PC1/SDA

PC2

PC3/SEN

PC4/PWRIN

PC5

DA5

AD0/PB0

AD1/PB1

AD2/PB2

AD3/PB3

AD4/PB4

AD5/PB5

AD6/PB6

PA0

AD1/PB1

AD2/PB2

AD3/PB3

AD4/PB4

AD5/PB5

AD6/PB6

PA0

PC6/IRIN

VS

PC6/IRIN

PC7

9

33 RESET

32

33 RESET

32

10

11

12

13

14

15

16

17

18

19

20

21

10

11

12

13

14

15

16

17

18

19

20

21

OSCout

31 OSCin

30 TEST/V_PP

31 OSCin

30 TEST/V_PP

(1)

OSDOSCout

OSDOSCin

VSYNC

HSYNC

BLANK

B

OSDOSCout

OSDOSCin

VSYNC

HSYNC

BLANK

B

29

28

27

26

25

24

23

22

29

28

27

26

25

24

23

22

PA1

PA2

PA3

PA4

PA1

PA2

PA3

PA4

PA5

PA6 (HD0)

PA7 (HD1)

V^SS

PA6 (HD0)

PA7 (HD1)

V^SS

G

R

G

R

(1) This pin is also the V_PPinput for OTP/EPROM devices

VR01375

(1) This pin is also the V_PPinput for OTP/EPROM devices

VR01375E

Table 29. Pin Summary

Pin Function

Description

DA0 to DA5

VS

Output, Open- Drain, 12V

Output, Push- Pull

R, G, B, BLANK

HSYNC, VSYNC

OSDOSCin

OSDOSCout

TEST

Output, Push- Pull

Input, Pull- up, Schmitt Trigger

Input, High Impedance

Output, Push- Pull

Input, Pull- Down

OSCin

OSCout

Input, Resistive Bias, Schmitt Trigger to Reset Logic Only

Output, Push- Pull

RESET

Input, Pull- up, Schmitt Trigger Input

PA0- PA3

PA4- PA5

PA6- PA7

PB0- PB6

PC0- PC3

PC4- PC7

I/ O, Push- Pull, Software Input Pull- up, Schmitt Trigger Input

I/ O, Open- Drain, 12V, No Input Pull- up, Schmitt Trigger Input

I/ O, Open- Drain, 12V, No Input Pull- up, Schmitt Trigger Input, High Drive

I/ O, Push- Pull, Software Input Pull- up, Schmitt Trigger Input, Analog input

I/ O, Open- Drain, 5V, Software Input Pull- up, Schmitt Trigger Input

I/ O, Open- Drain, 12V, No Input Pull- up, Schmitt Trigger Input

Power Supply Pins

V

, V

DD SS

76/82

ST63E88,ST63T88, ST63E89,ST63T89

1.2 EPROM/OTP DESCRIPTION

ST63E8x,T8x is described in the User Manual of

the EPROM Programming board.

The ST63E88 and ST63E89 are the EPROM ver-

sion of the ST6380, 82, 88 and ST6381, 83, 89

ROM products. They are intended for use during

the development of an application, and for pre-pro-

duction and small volume production. The

ST63T88 and ST63T89 OTPs have the same

characteristics. They both include EPROM memo-

ry instead of the ROM memory of the ST6388, 89,

and so the program and constants of the program

can be easily modified by the user with the

ST63E8x EPROM programming board from STMi-

croelectronics.

On the ST63E88, 89, all the 20140 bytes of PRO-

GRAM memory are available for the user, as all

the EPROM memory can be erased by exposure

to UV light. On the ST63T88, 89 (OTP device) a

reserved area for test purposes exists, as for the

ST6388, 89 ROM device. In order to avoid any dis-

crepancy between program functionality when us-

ing the EPROM, OTP and ROM it is recommend-

ed NOT TO USE THESE RESERVED AREAS,

even when using the ST63E88, 89. The Table 4

on page 10 is a summary of the EPROM/ROM

Map and its reserved area.

The EPROM OPTION BYTE is programmed by

the EPROM programming board and its associat-

ed software.

THE READER IS ASKED TO REFER TO THE

DATASHEET OF THE ST638x ROM-BASED DE-

VICE FOR FURTHER DETAILS.

The EPROM Option Byte content will define the

OSD options as follows:

7

-

0

1.3 EPROM ERASING

-

Opt 1 Opt 0

The EPROM of the windowed package of the

ST63E8, 89 may be erased by exposure to Ultra

Violet light.

b7-2: Not used.

The erasure characteristic of the ST63E88, 89

EPROM is such that erasure begins when the

memory is exposed to light with wave lengths

shorter than approximately 4000Å. It should be

noted that sunlight and some types of fluorescent

lamps have wavelengths in the range 3000-

4000Å. It is thus recommended that the window of

the ST63E88, 89 package be covered by an

opaque label to prevent unintentional erasure

problems when testing the application in such an

environment.The recommended erasure proce-

dure of the ST63E88, 89 EPROM is exposure to

short wave ultraviolet light which has wavelength

2537Å. The integrated dose (i.e. UV intensity x ex-

posure time) for erasure should be a minimum of

15 W-sec/cm2. The erasure time with this dosage

is approximately 15 to 20 minutes using an ultravi-

olet lamp with 12000mW/cm2 power rating. The

ST63E88, 89 should be placed within 2.5cm (1

inch) of the lamp tubes during erasure.

Opt 1: This option bit disconnect the Schmitt trig-

ger of PC7 and PB0 to prevent some electro-mag-

netic problems when these pads are not bonded.

-”0”: Schmitt triggers are connected to I/O’s inputs.

-”1”: Schmitt triggers are disconnected from I/O’s

inputs.

Opt 0: This option bit enables or disables the Pow-

er On/Off Reset.

-”0”: The Power On/Off Reset is enabled.

-”1”: The Power On/Off Reset is disabled.

From a user point of view (with the following ex-

ceptions) the ST63E8x,T8x products have exactly

the same software and hardware features of the

ROM version. An additional mode is used to con-

figure the part for programming of the EPROM,

this is set by a +12.5V voltage applied to the

TEST/VPP pin. The programming of the

77/82

ST63E88,ST63T88, ST63E89,ST63T89

2 ELECTRICAL CHARACTERISTICS

2.1 ABSOLUTE MAXIMUM RATINGS

This product contains devices to protect the inputs

against damage due to high static voltages, how-

ever it is advised to take normal precaution to

avoid application of any voltage higher than maxi-

mum rated voltages.

Power Considerations.The average chip-junc-

tion temperature, Tj, in Celsius can be obtained

from:

Tj=

TA + PD x RthJA

Where:TA =

Ambient Temperature.

For proper operation it is recommended that VI

RthJA = Package thermal resistance

(junction-to ambient).

and VO must be higher than V and smaller than

SS

V

. Reliability is enhanced if unused inputs are

DD

PD =

Pint + Pport.

connected to an appropriated logic voltage level

(V or V ).

Pint = IDD x V

er).

(chip internal pow-

DD

SS

Pport = Port power dissipation

(determined by the user).

Symbol

V_DD

V_I

Parameter

Value

Unit

V

Supply Voltage

-0.3 to 7.0

Input Voltage (AFC IN)

V_SS- 0.3 to +13

V

V_I

Input Voltage (Other inputs)

V_SS- 0.3 to V + 0.3

V

DD

V_O

Output Voltage (PA4-PA7, PC4-PC7, DA0-DA5)

Output Voltage (Other outputs)

V_SS- 0.3 to +13

V

V_O

V_SS- 0.3 to V + 0.3

V

DD

V_PP

I_O

EPROM Programming Voltage

- 0.3 to 13.0

+ 10

V

Current Drain per Pin Excluding V_DD, V_SS, PA6, PA7

Current Drain per Pin (PA6, PA7)

mA

°C

I_O

+ 50

IV

Total Current into V (source)

50

DD

IV_SS

T_j

Total Current out of V_SS(sink)

Junction Temperature

150

THERMAL CHARACTERISTICS

Value

Symbol

Parameter

Test Conditions

Unit

Min.

Typ.

Max.

RthJA

Thermal Resistance

PSDIP42

67

°C/W

2.2 RECOMMENDED OPERATING CONDITIONS

Value

Symbol

Parameter

Operating Temperature

Test Conditions

Unit

Min.

Typ.

Max.

70

T_A

0

°C

V

Operating Supply Voltage

4.5

12.0

5.0

6.0

DD

V_PP

EPROM Programming Voltage

12.5

13.0

V

Oscillator Frequency

RUN & WAIT Modes

f

8.0

8.1

8.0

MHz

OSC

f_OSDOSCOn-screen Display Oscillator Frequency

EEPROM INFORMATION

The ST63xx EEPROM single poly process has been specially developed to achieve 300.000 Write/Erase

cycles and a 10 years data retention.

78/82

ST63E88,ST63T88, ST63E89,ST63T89

2.3 DC ELECTRICAL CHARACTERISTICS

(TA = 0 to +70°C unless otherwise specified).

Table 30: DC ELECTRICAL CHARACTERISTICS

Value

Symbol

Parameter

Test Conditions

Unit

Min.

Typ.

Max.

V

Input Low Level Voltage

Input High Level Voltage

All I/O Pins

0.2xV

V

IL

DD

V

0.8xV

IH

DD

V

(1)

HYS

Hysteresis Voltage

1.0

V

= 5V

DD

DA0-DA5, PB0-PB6, OSD

Outputs, PC0-PC7,

O0, O1, PA0-PA5

V

Low Level Output Voltage

OL

V

= 4.5V

DD

I

= 1.6mA

= 5.0mA

0.4

1.0

V

OL

PA6-PA7

= 4.5V

V

I

DD

V

Low Level Output Voltage

High Level Output Voltage

OL

OH

= 1.6mA

= 25mA

0.4

1.0

V

OL

OSDOSCout

OSCout

V

0.4

V

= 4.5V

DD

I

= 0.4mA

OL

VS Output

= 4.5V

V

DD

I

= 0.5mA

= 1.6mA

0.4

1.0

V

OL

PB0-PB6 PA0-PA3, OSD

Outputs

V

4.1

V

= 4.5V

DD

I

= – 1.6mA

OH

OSDOSCout, OSCout,

= 4.5V

V

High Level Output Voltage

V

4.1

V

OH

PU

DD

I

= – 0.4mA

OH

VS Output

= 4.5V

V

DD

I

= - 0.5mA

OH

PB0-PB6, PA0-PA3,

PC0-PC3,

Input Pull Up Current

Input Mode with Pull-up

I

– 100

– 50

– 25

mA

V

= V

IN

SS

OSCin

I

IL

Input Leakage Current

V

= V

– 10

0.1

– 1

1

– 0.1

10

µA

IN

SS

DD

I

IH

Input Pull-down

current in RESET

I

OSCin

100

µA

IL

All I/O Input Mode

no pull-up

OSDOSCin

I

IL

Input Leakage Current

-10

10

µA

I

IH

V

= V or V

IN

DD SS

RAM Retention Voltage in

RESET

V

RAM

1.5

V

DD

I

Reset Pin with Pull-up

V = V

IN

IL

Input Leakage Current

– 50

– 30

– 10

µA

I

IH

SS

79/82

ST63E88,ST63T88, ST63E89,ST63T89

Table 30: DC ELECTRICAL CHARACTERISTICS

Value

Typ.

Symbol

Parameter

Test Conditions

AFC Pin

Unit

Min.

Max.

I

V = V

1

IL

IH

DD

Input Leakage Current

µA

I

V = V

-1

IH

IL

SS

V

= 12.0V

40

IH

DA0-DA5, PA4-PA5,

PC0-PC7, O0, O1

I

Output Leakage Current

10

40

OH

µA

V

= V

OH

DD

DA0-DA5, PA4-PA7,

PC4-PC7, O0, O1

Output Leakage Current High Volt-

age

V

= 12V

OH

f

V

= 8MHz, ILoad= 0mA

= 6.0V

OSC

I

Supply Current RUN Mode

Supply Current WAIT Mode

6

3

16

10

mA

DD

f

= 8MHz, ILoad= 0mA

= 6V

OSC

DD

V

DD

f

= Not App,

OSC

Supply Current at transition to RE-

SET

I

ILoad= 0mA

= 6V

0.1

1

mA

DD

V

DD

V

Reset Trigger Level ON

RESET Pin

0.3xV

V

ON

DD

V

Reset Trigger Level OFF

Input Level Absolute Tolerance

RESET Pin

0.8xV

DD

OFF

A/D AFC Pin

V

± 200

± 100

mV

TA

V

= 5V

DD

A/D AFC Pin

Relative to other levels

V

Input Level Relatice Tolerance⁽¹⁾

mV

TR

V

= 5V

DD

Note 1. Not 100% Tested

80/82

ST63E88,ST63T88, ST63E89,ST63T89

2.4 AC ELECTRICAL CHARACTERISTICS

(TA = 0 to +70°C, f_OSC=8MHz, V =4.5 to 6.0V unless otherwise specified)

DD

Value

Typ.

Symbol

Parameter

Test Conditions

Unit

ns

Min.

Max.

t

Minimum Pulse Width

High to Low Transition Time

RESET Pin

PA6, PA7

= 5V, CL = 1000pF

125

WRES

t

100

20

ns

(2)

OHL

V

DD

DA0-DA5, PB0-PB6, OSD

Outputs, PC0-PC7

t

High to Low Transition Time

ns

OHL

OLH

(2)

V

= 5V, CL = 100pF

DD

PB0-PB6, PA0-PA3, OSD

Outputs, PC0-PC3

t

Low to High Transition Time

Data HOLD Time SPI after

20

V

= 5V, CL = 100pF

DD

PB0-PB6, PA0-PA3, OSD

t

clock goes low I²CBUS/S-BUS Outputs, PC0-PC3

175

ns

OH

only

V

= 5V, CL = 100pF

DD

D/A Converter Repetition Fre-

f

31.25

kHz

(1)

DA

quency

(1)

f

SIO Baudrate

62.50

5

kHz

ms

SIO

t

EEPROM Write Time

T

= 25°C One Byte

A

10

WEE

EEPROM WRITE/ERASE Cy-

cles

Q

L

> 1

million

A

OT

Endurance

Retention

300,000

10

cycles

Acceptance Criteria

(4)

EEPROM Data Retention

T

= 25°C

years

pF

A

(3)

C

Input Capacitance

All Inputs Pins

10

IN

(3)

C

Output Capacitance

All Outputs Pins

pF

OUT

COSCin,

COSCout

COSDin,

COSDout

Oscillator Pins Internal

Capacitance

5

pF

(3)

Oscillator Pins External

Capacitance

15

25

Notes:

1. A clock other than 8MHz will affect the frequency response of those peripherals (D/A, and SPIs) whose clock is derived from the system

clock.

2. The rise and fall times of PORT A have been increased in order to avoid current spikes while maintaining a high drive capability

3. Not 100% Tested

4. Based on extrapolated data

81/82

ST63E88,ST63T88, ST63E89,ST63T89

2.5 OSD TEST CHARACTER

Figure 38. OSD Test Character

IN ORDER TO ALLOW THE TESTING OF THE

ON-CHIP OSD MACROCELL THE FOLLOWING

CHARACTER MUST BE PROVIDED AT THE

FIXED 3Fh (63) POSITION OF THE SECOND

OSD BANK.

1

2

3

4

5

6

7

8

9 10 11 12 13 14

1

2

3

Listing Generation & Verification. When STMi-

croelectronics receives the files, a computer listing

is generated from them. This listing refers extractly

to the mask that will be used to produce the micro-

controller. Then the listing is returned to the cus-

tomer that must thoroughly check, complete, sign

and return it to STMicroelectronics. The signed list

constitutes a part of the contractual agreement for

the creation of the customer mask. STMicroelec-

tronics sales organization will provide detailed in-

formation on contractual points.

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics

Purchase of I²C Components by STMicroelectronics conveys a license under the Philips I²C Patent. Rights to use these components in an

I²C system is granted provided that the system conforms to the I²C Standard Specification as defined by Philips.

STMicroelectronics Group of Companies

Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain

Sweden - Switzerland - United Kingdom - U.S.A.

http://www.st.com

82/82


型号：	ST6388
厂家：	ST
描述：	8-BIT MCUs WITH ON-SCREEN-DISPLAY FOR TV TUNING 与屏幕上，显示屏上的电视调谐8位MCU 电视
文件：	总82页 (文件大小：717K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ST6388 [STMICROELECTRONICS]

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