ST63E156D1 [STMICROELECTRONICS]
8-BIT HCMOS MCUs FOR TV FREQUENCY & VOLTAGE SYNTHESIS WITH OSD; 8 - BIT MCU的HCMOS用于电视频率与电压合成OSD
| 型号： | ST63E156D1 |
| 厂家： | 
ST |
| 描述： | 8-BIT HCMOS MCUs FOR TV FREQUENCY & VOLTAGE SYNTHESIS WITH OSD |
| 文件： | 总86页 (文件大小：710K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ST63140, ST63146
ST63126, ST63156
DATA SHEET
st
1 Edition
OCTOBER 1993
USE IN LIFE SUPPORT DEVICES OR SYSTEMS MUST BE EXPRESSLY AUTHORIZED.
SGS-THOMSON PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYS-
TEMS WITHOUT THE EXPRESSWRITTEN APPROVAL OF SGS-THOMSON Microelectronics.
As used herein :
1. Life support devices or systems are those which (a) are
intended for surgical implant into the body, or (b) support
or sustain life, and whose failure to perform, when prop-
erly used in accordance with instructions for use pro-
vided with the product, can be reasonably expected to
result in significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can reason-
ably be expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
ST631xx DATASHEET INDEX
Pages
1
ST63140, ST63142
ST63126, ST63156 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ST631xx CORE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MEMORY SPACES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
STACK SPACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
WAIT & STOP MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ON-CHIP CLOCK OSCILLATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
INPUT/OUTPUT PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TIMERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HARDWARE ACTIVATED DIGITAL WATCHDOG FUNCTION . . . . . . . . . . . . . . . . . . .
SERIAL PERIPHERAL INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
5
7
10
16
16
20
22
23
24
27
30
31
14-BIT VOLTAGE SYNTHESIS TUNING
PERIPHERAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
40
41
6-BIT PWM D/A CONVERTER AND 62.5 kHz OUTPUT FUNCTION . . . . . . . . . . . . . . . .
AFC A/D INPUT, KEYBOARD INPUTS
AND BANDSWITH OUTPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
43
44
45
54
59
60
63
65
INFRARED INPUT (IRIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ON-SCREEN DISPLAY (OSD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SOFTWARE DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EEPROM INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ORDERING INFORMATION TABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ST63E140/T140, E142/T142
ST63E126/T126, E156/T156 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
67
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EPROM/OTP DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EEPROM INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ORDERING INFORMATION TABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
69
71
74
75
76
79
82
ST63140, ST63142
ST63126, ST63156
8-BIT HCMOS MCUs FOR
TV FREQUENCY & VOLTAGE SYNTHESIS WITH OSD
PRELIMINARY DATA
4.5 to 6V operating Range
8MHz Maximum Clock Frequency
User Program ROM: 7948 bytes
Reserved Test ROM: 244 bytes
Data ROM:
Data RAM:
user selectable size
256 bytes
Data EEPROM:
128 bytes
40-Pin Dual in Line Plastic Package for the
ST63126, 156
28-Pin Dual in Line Plastic Package for the
ST63140, 142
1
PDIP40
Up to 18 software programmable general pur-
pose Inputs/Outputs, including 8 direct LED
driving Outputs
3 Inputs for keyboard scan (KBY0-2)
Up to 4 high voltage outputs (BSW0-3)
Two Timers each including an 8-bit counter with
a 7-bit programmable prescaler
Digital Watchdog Function
Serial Peripheral Interface (SPI) supporting
S-BUS/ I2C BUS and standard serial protocols
1
Up to Four 6-bit PWM D/A Converters
62.5kHz Output pin
14 bit counter for voltage synthesis tuning
(ST63156, ST63140)
PDIP28
(Ordering Information at the end of the datasheet)
DEVICE SUMMARY
ROM
AFC A/D converter with 0.5V resolution
Four interrupt vectors (IRIN/NMI, Timer 1 & 2,
VSYNC.)
DEVICE
TUN. I/O Pins Package
(Bytes)
On-chip clock oscillator
5 Lines by 15 Characters On-Screen Display
Generator with 128 Characters (2 banks)
ST63126
ST63156
ST63140
ST63142
8K
FS
VS
VS
FS
12
11
6
PDIP40
PDIP40
PDIP28
PDIP28
All ROM types are supported by pin-to-pin
EPROM and OTP versions.
8K
The development tool of the ST631xx microcon-
trollers consists of the ST63TVS-EMUemulation
and development system to be connected via a
standard RS232 serial line to an MS-DOS Per-
sonal Computer.
8K
8K
6
October 1993
1/82
This is Preliminary information from SGS-THOMSON. Details are subject tochange withoutnotice.
ST63140,142,126,156
Figure 1. ST63126, 156 Pin Configuration
VDD
VDD
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
1
2
BSW0
BSW
BSW2
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
1
2
BSW0
BSW1
BSW2
DA3
DA2
DA1
DA0
OUT1
IRIN
VS
DA3
DA2
3
3
4
BSW3
4
BSW3
DA1
5
6
KBY0
5
6
KBY0
DA0
KBY 1
KBY2
OUT1
IRIN
KBY 1
KBY2
7
7
8
9
OSDOSCout
OSDOSCin
(SEN) PB7
(SDA) PB6
(SCL) PB5
(HSYNC) PB3
(VSYNC) PB2
AFC
8
9
OSDOSCout
OSDOSCin
(SEN) PB7
(SDA) PB6
(SCL) PB5
(HSYNC) PB3
(VSYNC) PB2
AFC
PC7 (B)
PC6 (G)
PC5 (R)
PC3 (BLANK)
PC2 (ON/OFF)
PC1
PC7 (B)
PC6 (G)
PC5 (R)
PC3 (BLANK)
PC2 (ON/OFF)
PC1
10
11
12
10
11
12
13
14
15
13
14
15
PC0
OSCout
OSCin
OSCout
OSCin
RESET
PA1
TEST (1)
PA6
TEST (1)
PA6
16
17
18
19
20
16
17
18
19
20
RESET
PA1
PA5
PA5
PA2
PA4
VSS
PA2
PA4
VSS
PA3
PA3
VA00288
VA00282
ST63156
ST63126
Note 1. This pin is also the V
input for EPROM based devices
PP
Figure 2. ST63140, 142 Pin Configuration
BSW0
BSW1
1
2
3
4
5
6
7
8
9
28
VDD
BSW0
BSW1
1
28
27
26
25
24
23
22
VDD
27
26
25
24
23
22
DA0
2
DA0
BSW2
OUT1
IRIN
BSW2
3
OUT1
VS
KBY0
KBY0
4
KBY1
PC6 (G)
PC5 (R)
PC4
KBY1
5
PC6 (G)
PC4
KBY2
KBY2
6
OSDOSCout
OSDOSCin
PB3 (HSYNC)
PB2 (VSYNC)
AFC
OSDOSCout
OSDOSCin
PB3 (HSYNC)
PB2 (VSYNC)
7
PC3 (BLANK)
21 PC2
8
21 PC2
20
19
18
17
16
15
OSCout
9
20
19
18
17
16
15
OSCout
10
OSCin
RESET
PA0
10
11
12
13
14
OSCin
RESET
PA0
11
12
13
14
AFC
TEST (1)
PA4
TEST (1)
PA4
PA1
PA1
VSS
VSS
PA2
PA2
VR001390
VR001389
ST63142
ST63140
Note 1. This pin is also the V
input for EPROM based devices
PP
2/82
ST63140,142,126,156
GENERAL DESCRIPTION
The ST63140, 142, 126, 156 microcontrollers are
members of the 8-bit HCMOS ST631xx family, a
series of devices specially oriented to TV applica-
tions. DifferentROM sizeand peripheral configura-
tions areavailableto give themaximum application
and cost flexibility. All ST631xx members are
based on a building block approach: a common
core is surrounded by acombination of on-chip pe-
ripherals (macrocells) available from a standard li-
brary. These peripherals are designed with the
same Core technology providing full compatibility
and short design time. Many of these macrocells
are specially dedicated to TV applications. The
macrocells of the ST631xx family are: two Timer
peripherals each including an 8-bit counter with a
7-bit software programmable prescaler (Timer), a
digital hardware activated watchdog function
(DHWD), a 14-bit voltage synthesis tuning periph-
eral, a Serial Peripheral Interface (SPI), up to four
6-bit PWM D/A converters, an AFC A/D converter
with 0.5V resolution, an on-screen display (OSD)
with 15 characters per line and 128 characters (in
two banks each of 64 characters). In addition the
following memory resources are available: pro-
gram ROM (7K), data RAM (256 bytes), EEPROM
(128 bytes).
Refer to pin configuration figures and to ST631xx
device summary (Table 1) for the definition of
ST631xx family members and a summary of differ-
ences among the different types.
3/82
ST63140,142,126,156
Figure 3. ST631xx Block Diagram
* Refer To Pin Configuration For Additional Information
*
TEST
TEST
PORT A
PORT B
PORT C
PA0 - PA7
PB2 - PB7
PC0 - PC7
IR INTERRUPT
Input
*
IRIN/NMI
*
DATA ROM
USER SELECTABLE
SERIAL PERIPHERAL
INTERFACE
USER PROGRAM
ROM
DATA RAM
256 Bytes
8 KBytes
TIMER 1
TIMER 2
DATA EEPROM
128 Bytes
DIGITAL
WATCHDOG/TIMER
PC
STACK LEVEL 1
STACK LEVEL 2
STACK LEVEL 3
STACK LEVEL 4
STACK LEVEL 5
STACK LEVEL 6
D / A Outputs
DA0 - DA3
8-BIT CORE
VS output
AFC Input
&
*
AFC & VS
ON-SCREEN
DISPLAY
R, G, B, BLANK
HSYNC (PB3)
VSYNC (PB2)
POWER SUPPLY OSCILLATOR
RESET
VR01753E
V
V
OSCin OSCout
RESET
OSDOSCin
OSDOSCout
DD
SS
Table 1. Device Summary
ROM RAM EEPROM
KBY
I/O
BSW
OUT
EMUL.
DEVICES
DEVICE
I/O
AFC
VS
D/A
PACK.
(Bytes) (Bytes)
(Bytes)
ST63126
ST63156
ST63140
ST63142
8K
8K
8K
8K
256
256
256
256
128
12
11
6
3
4
4
3
3
YES
YES
YES
YES
NO
YES
YES
NO
4
4
1
1
PDIP40 ST63E126
PDIP40 ST63E156
128
3
128
3
PDIP28
ST6E140
128
6
3
PDIP28 ST63E142
4/82
ST63140,142,126,156
PIN DESCRIPTION
DD and VSS. Power is supplied to the MCU using
these two pins. VDD is power and VSS is theground
connection.
V
PC0-PC7. These 8 lines are organized as one I/O
port (C). Each line may be configured as either an
input with or without internal pull-up resistor or as
an output under software control of the data direc-
tion register. PC0-PC2, PC4 have apush-pull con-
figuration in output mode while PC3, PC5-PC7
(OSD signals) are open-drain(5V drive). PC3, PC5 ,
PC6 and PC7 lines when in output mode are
“ANDed” with the character and blank signals of
the OSD cell. PC3 is connected with the OSD
BLANK signal, PC5, PC6 and PC7 withthe OSDR,
G and B signals. The active polarity of these sig-
nals canbe selected by the user as ROM mask op-
tion. PC2 is also used as TV set ON-OFF switch
(5V drive).
OSCin, OSCout. These pins are internally con-
nected to the on-chip oscillator circuit. A quartz
crystal or a ceramic resonator can be connected
between these two pins in order to allow the cor-
rect operation of the MCU with various stabil-
ity/cost trade-offs. The OSCin pin is the input pin,
the OSCout pin is the output pin.
RESET. The active low RESET pin is used to start
the microcontroller to the beginningof its program.
TEST. The TEST pin must be held at VSS for nor-
mal operation.
DA0-DA3. These pins are the four PWM D/A out-
puts (with 32kHz repetition) of the6-bit on-chip D/A
converters. The PWM function can be disabled by
software and these lines can be used as general
purpose open-drain outputs (12V drive).
PA0-PA7. These 8 lines are organized as one I/O
port (A). Each line may be configured as either an
input or as an output under software control of the
data direction register. Port A has an open-drain
(12V drive) output configuration with direct LED
driving capability (30mA, 1V).
IRIN. This pin is the external NMI of the MCU.
PB2-PB3, PB5-PB7. These lines are organizedas
one I/O port (B). Each line may be configured as
either aninput with or without internal pull-up resis-
tor or as an output under software control of the
data direction register. PB2-PB3 have a push-pull
configuration in output mode while PB5-PB7 are
open-drain (5V drive).
OUT1. This pin is the 62.5kHz output specially
suited to drive multi-standard chroma processors.
This function can be disabled by software and the
pin can be used as general purpose open-drain
output (12V drive).
BSW0-BSW3. These output pins can be used to
select up to 4 tuning bands. These lines are config-
ured as open-drain outputs (12V drive).
PB2 and PB3 lines are connected to the VSYNC
and HSYNCcontrol signals of the OSD cell; to pro-
vide the right signals to the OSD these I/O lines
should beprogrammed in input mode and the user
can read “on the fly” the state of VSYNC and
HSYNC signals. PB2 is also connected with the
VSYNC Interrupt. The active polarity of VSYNC In-
terrupt signal is software controlled. The active po-
larity of these synchronization input pins to the
OSD macrocell can be selected by the user as
ROM mask option. If the device is specified to have
negative logic inputs, then when these signals are
low the OSD oscillator stops. If the device is speci-
fied to have positive logic inputs, then when these
signals are high the OSD oscillator stops.
KBY0-KBY2. These pins are input only and can be
used for keyboard scan. They have CMOS thresh-
old levels with Schmitt Trigger and on-chip 100kΩ
pull-up resistors.
AFC. This is the input of the on-chip 10 level com-
parator that can be used to implement the AFC
function. This pin is an high impedance input able
to withstand signals with a peak amplitude up to
12V.
OSDOSCin, OSDOSCout. These are the On
Screen Display oscillator terminals. An oscillation
capacitor and coil network have to be connected to
provide the right signal to the OSD.
PB5, PB6 and PB7 lines, when in output modes,
are “ANDed” with the SPI control signals. PB5 is
connected with the SPI clock signal (SCL), PB6
with the SPI data signal (SDA) while PB7 is con-
nected with SPI enable signal (SEN).
VS. This is the output pin of the on-chip 14-bit volt-
age synthesis tuning cell (VS). The tuning signal
present at this pin gives an approximate resolution
of 40kHz per step over the UHF band. This line is a
push-pull output with standard drive (ST63140,
ST63156 only).
5/82
ST63140,142,126,156
Table 2. Pin Summary
Pin Function
DA0 to DA3
BSW0 to BSW3
IRIN
Description
Output, Open-Drain, 12V
Output, Open-Drain, 12V
Input, Resistive Bias, Schmitt Trigger
Input, High Impedance, 12V
AFC
OUT1
Output, Open-Drain, 12V
KBY0 to KBY2
R,G,B, BLANK
HSYNC, VSYNC
OSDOSCin
OSDOSCout
TEST
Input, Pull-up, Schmitt Trigger
Output, Open-Drain, 5V
Input, Pull-up, Schmitt Trigger
Input, High Impedance
Output, Push-Pull
Input, Pull-Down
OSCin
Input, Resistive Bias, Schmitt Trigger to Reset Logic Only
Output, Push-Pull
OSCout
RESET
Input, Pull-up, Schmitt Trigger Input
Output, Push-Pull
VS
PA0-PA6
I/O, Open-Drain, 12V, No Input Pull-up, Schmitt Trigger, High Drive
I/O, Push-Pull, 5V, Input Pull-up, Schmitt Trigger
I/O, Open-Drain, 5V, Input Pull-up, Schmitt Trigger
I/O, Push-Pull, 5V, Input Pull-up, Schmitt Trigger
I/O, Open-Drain, 5V, Input Pull-up, Schmitt Trigger
Power Supply Pins
PB2-PB3, PB5-PB7
PB5-PB7
PC0-PC2, PC4
PC3, PC5-PC7
V
DD, VSS
6/82
ST63140,142,126,156
ST631xx CORE
Figure 5. ST631xx Core Programming Model
The Core of the ST631xx Family is implemented
independently from the I/O or memory configura-
tion. Consequently, it can be treated as an inde-
pendent central processor communicating with I/O
and memoryvia internal addresses, data, and con-
trol busses. The in-core communication is ar-
ranged as shown in the following block diagram
figure; the controller being externally linked to both
the reset and the oscillator, while the core is linked
to thededicated on-chip macrocells peripherals via
the serial data bus and indirectly for interrupt pur-
poses through the control registers.
b7 X REG. POINTER b0
INDEX
REGISTER
SHORT
DIRECT
ADDRESSING
MODE
b7 Y REG. POINTER b0
b7
b7
V REGISTER
W REGISTER
b0
b0
b7 ACCUMULATOR
PROGRAMCOUNTER
b0
b0
b11
Registers
The ST631xx Family Core has six registers and
three pairs of flags available to the programmer.
They are shown in Figure 5 and are explained in
the following paragraphs together with the pro-
gram and data memory page registers.
SIX LEVELS
STACK REGISTER
Accumulator (A). The accumulator is an 8-bit
general purpose register used in all arithmetic cal-
culations, logical operations, and data manipula-
tions. The accumulator is addressed in the data
space as RAM location at address FFh .
Accordingly, the ST631xx instruction set can use
the accumulator as any other register of the data
space.
NORMAL FLAGS
INTERRUPTFLAGS
NMI FLAGS
C
C
C
Z
Z
Z
VA000423
Figure 4. ST631xx Core Block Diagram
0,0 1 TO 8MHz
OSCin OSCout
RESET
CONTROLLER
INTERRUPTS
DATA SPACE
FLAG
CONTROL
SIGNALS
OPCODE
VALUES
2
ADDRESS / READ LINE
DATA
RAM / EEPROM
PROGRAM
ROM/EPROM
DATA
ADDRESS
DECODER
256
ROM / EPROM
B-DATA
A-DATA
DEDICATIONS
ACCUMULATOR
Program Counter
and
12
FLAGS
6 LAYER STACK
ALU
RESULTS TO DATA SPACE ( WRITE LINE )
VR001811
7/82
ST63140,142,126,156
ST631xx CORE (Continued)
Flags (C, Z)
Indirect Registers (X, Y). These two indirect reg-
isters are used as pointers tothe memorylocations
in the data space. They are used in the register-in-
direct addressing mode.These registers can be
addressed in the data space as RAM locations at
the 80h (X) and 81h (Y) addresses. They can also
be accessed with the direct, short direct, or bit di-
rect addressing modes. Accordingly, the ST631xx
instruction set can use the indirect registers as any
other register of the data space.
The ST631xx Core includes three pairs of flags
that correspond to 3 different modes: normal
mode, interrupt mode and Non-Maskable-Inter-
rupt-Mode. Each pair consists of a CARRY flag
and a ZERO flag. One pair (CN, ZN) is used during
normal operation, one pair is used during the inter-
rupt mode (CI,ZI) and one is used during the not-
maskable interrupt mode (CNMI, ZNMI).
The ST631xx Core uses the pair of flags that corre-
sponds to the actualmode: as soon as an interrupt
(resp. a Non-Maskable-Interrupt)is generated, the
ST631xx Core uses the interrupt flags (resp. the
NMI flags) instead of the normal flags. When the
RETI instruction is executed, the normal flags
(resp. the interrupt flags) are restored if the MCU
was in the normal mode (resp. in the interrupt
mode) before the interrupt. Should be observed
that each flag set can only be addressed in its own
routine (Not-maskable interrupt, normal interrupt
or main routine). The interrupt flags are not cleared
during the context switching and so, they remain in
the state they were at the exit of the last routine
switching.
Short Direct Registers (V, W). These two regis-
ters are used to save one byte in short direct ad-
dressing mode. These registers can be addressed
in the data space as RAM locations at the 82h (V)
and 83H (W) addresses. They can also be ac-
cessed with the direct and bit direct addressing
modes. Accordingly, the ST631xx instruction set
can use the short direct registers as any other reg-
ister of the data space.
Program Counter (PC)
The program counter is a 12-bit register that con-
tains the address of the next ROM location to be
processed by the core. This ROM location may be
an opcode, an operand, or an address of operand.
The 12-bit length allows the direct addressing of
4096 bytes in the program space. Nevertheless, if
the program space contains more than 4096 loca-
tions, the further program space can be addressed
by using theProgram ROM Page Register. The PC
value isincremented, after it is read for the address
of thecurrent instruction, by sending it through the
ALU, so giving the address of the next byte in the
program. To execute relative jumpsthe PCand the
offset values are shifted through the ALU, where
they will be added, and the result is shifted back
into the PC. The program counter can be changed
in the following ways:
The Carry flag is set when a carry or a borrow oc-
curs during arithmetic operations, otherwise it is
cleared. The Carry flag is also set to the value of
the bit tested in a bit test instruction, and partici-
pates in the rotate left instruction.
The Zero flag is setif theresult of the last arithmetic
or logical operation was equal to zero, otherwise it
is cleared.
The switching between these three sets is auto-
matically performedwhen an NMI, an interrupt and
a RETI instructions occur. As the NMI mode is
automatically selected after the reset of the MCU,
the ST631xxCore uses at first the NMI flags.
JP (Jump) instruction.... PC= Jump address
CALL instruction...........PC= Call address
Relative Branch
instructions................... PC= PC+offset
Interrupt........................ PC= Interrupt vector
Reset............................PC= Reset vector
RET & RETI instructions............PC=Pop (stack)
Normal instruction........ PC = PC+1
8/82
ST63140,142,126,156
ST631xxx CORE(Continued)
Stack
Figure 6. Stack Operation
The ST631xx Core includes true LIFO hardware
stack that eliminates the need for a stack pointer.
The stackconsists of six separate12-bit RAM loca-
tions that do not belong to the data space RAM
area. When a subroutine call (or interrupt request)
occurs, the contents of each level is shifted into the
next level while the content of the PC is shifted into
the first level (the value of the sixth level will be
lost). When subroutine or interrupt return occurs
(RET or RETI instructions), the first level register is
shifted back into the PCand thevalue of each level
is shifted back into the previous level. These two
operating modes are described in Figure 6. Since
the accumulator, as all other data space registers,
is not stored in this stack the handling of this regis-
ters shall be performed inside the subroutine. The
stack pointer will remain in its deepest position, if
more than 6 calls or interrupts are executed, so
that the last return address will be lost. It will also
remain in its highest position if the stack is empty
and a RET or RETI is executed. In this case the
next instruction will be executed.
PROGRAM COUNTER
STACK LEVEL 1
STACK LEVEL 1
STACK LEVEL 1
STACK LEVEL 1
STACK LEVEL 1
STACK LEVEL 1
WHEN CALL
OR
INTERRUPT REQUEST
OCCURS
RET OR RETI
WHEN
OCCURS
VA000424
9/82
ST63140,142,126,156
MEMORY SPACES
static space. Table 3 gives the codes that allow the
selection of the correspondingbanks.
The MCUs operate in three different memory
spaces: Program Space, Data Space, and Stack
Space. A description of these spaces is shown in
the following Figures.
Note that,from the memory point of view, the Page
1 and the Static Page represent the same physical
memory: it is only a different way of addressing the
same location. On the ST631xx a total of 8192
bytes of ROM have been implemented; 7948 are
available as user ROM while 244 are reserved for
testing.
Program Space
The program space is physically implemented in
the ROM and includes all the instructions that are
to be executed, as well as the data required for the
immediate addressing mode instructions, the re-
served test area and user vectors. It is addressed
thanks to the 12-bit Program Counter register (PC
register) and so, the ST631xxCore can directly ad-
dress up to 4K bytes of Program Space. Neverthe-
less, the Program Space can be extended by the
addition of 2-Kbyte ROM banks as it is shown in
Figure 8 in which the 8K bytes memory is de-
scribed.
Figure 8. ST631xx 8K Bytes Program Space
Addressing Description
Program
counter
space
0000h
1FFFh
0FFFh
Static Page
Page 1
These banks are addressed by pointing to the
000h-7FFh locations of the Program Space thanks
to the Program Counter, and by writing the appro-
priate code in the Program ROM Page Register
(PRPR) located at address CAh of the Data
Space. Because interrupts and common subrou-
tines should be available all the time only the lower
2K bytes of the 4K program space are bank
switched while the upper 2K bytes can be seen as
0800h
07FFh
Page 1
Static Page
Page 0
Page 2
Page 3
0000h
Figure 7. ST631xx Memory Addressing Description Diagram
STACK SPACE
PROGRAM SPACE
DATA SPACE
0000h
000h
RAM
/
EEPROM
PROGRAM COUNTER
BANKING AREA
0-63
STACK LEVEL 1
STACK LEVEL 2
STACK LEVEL 3
STACK LEVEL 4
STACK LEVEL 5
STACK LEVEL 6
03Fh
040h
ROM
DATA ROM
WINDOW
070h
080h
081h
X
Y
REGISTER
REGISTER
REGISTER
REGISTER
07FFh
0800h
V
082h
083h
084h
W
RAM
ROM
0C0h
DATA ROM
WINDOW SELECT
DATA RAM
BANK SELECT
0FF0h
0FFFh
INTERRUPT
&
ACCUMUL ATOR
RESET VECTORS
0FFh
VR001568
10/82
ST63140,142,126,156
MEMORY SPACES (Continued)
Care is required when handling the PRPR as it is
write only. For this reason, it is not allowed to
change the PRPR contents while executing inter-
rupts drivers, as the driver cannot save and than
restore its previous content. Anyway, this opera-
tion may be necessary if the sum of common rou-
tines and interrupt drivers will take more than 2K
bytes; in this case could be necessary to divide the
interrupt driver in a (minor) part in the static page
(start and end), and in the second (major) part in
one dynamic page. If it is impossible to avoid the
writing of this register in interrupts drivers, an im-
age of this register must be saved in a RAM loca-
tion, and each time the program writes the PRPR it
writes also the image register. The image register
must be written first, so if an interrupt occurs be-
tween the two instructions the PRPR is not af-
fected.
Figure 11. Program ROM Page Register
PRPR
Program ROM Page Register
(CAh, Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
PRPR0 = PROG.ROMSelect0
PRPR1 = PROG.ROMSelect1
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
D7-D2. These bits are not used.
Table 3. Program ROM Page Register Coding
PRPR1-PRPR0. These are the program ROM
banking bits and the value loaded selects the cor-
responding page to be addressed in the lower part
of 4K programaddress space as specified in Table 3.
This register is undefinedon reset.
PRPR1
PRPR0
PC11
Memory Page
Static Page (Page1)
Page 0
X
0
0
1
1
X
0
1
0
1
1
0
0
0
0
Note:
Page 1 (Static Page)
Page 2
Only the lower part of address space has been
bankswitched because interrupt vectors and com-
mon subroutines should be available all the time.
The reason of this structure is due to the fact that it
is notpossible to jump from a dynamic page to an-
other, unless jumping back to the static page,
changing contents of PRPR, and, then, jumping to
a differentdynamic page.
Page 3
This register is undefined on reset. Neither
read nor single bit instructions may be used to
address this register.
Table 4. ST631xx Program ROM Map
ROM Page
PAGE 0
Device Address
Device Address (1)
Description
Reserved
0000h-007Fh
0080h-07FFh
0000h-007Fh
0080h-07FFh
User ROM
0800h-0F9Fh
0FA0h-0FEFh
0FF0h-0FF7h
0FF8h-0FFBh
0FFCh-0FFDh
0FFEh-0FFFh
0800h-0F9Fh
0FA0h-0FEFh
0FF0h-0FF7h
0FF8h-0FFBh
0FFCh-0FFDh
0FFEh-0FFFh
User ROM
Reserved
Interrupt Vectors
Reserved
NMI Vector
Reset Vector
PAGE 1
“STATIC”
0000h-000Fh
0010h-07FFh
1000h-100Fh
1010h-17FFh
Reserved
User ROM
PAGE 2
PAGE 3
0000h-000Fh
0010h-07FFh
1800h-180Fh
1810h-1FFFh
Reserved
User ROM
Note 1. EPROM addresses relate to the use of ST63E1xx EPROM Emulation device.
11/82
ST63140,142,126,156
MEMORY SPACES (Continued)
Data Space
The instruction set of the ST631xx Core operates
on a specific space, named Data Space that con-
tains all the data necessary for the processing of
the program. The Data Space allows the address-
ing of RAM (256 bytes for the ST631xx family),
EEPROM (128 bytes), ST631xx Core/peripheral
registers, and read-only data such as constants
and the look-up tables.
Figure 13. ST631xx Data Space (Continued)
Figure 12. ST631xx Data Space
b7
b0
b7
b0
RESERVED
0D9h
0DAh
0DBh
000h
TIMER 2 PRESCALER REGISTER
TIMER 2 COUNTER REGISTER
DATA RAM/EEPROM/OSD
BANK AREA
TIMER 2 STATUS CONTROL REG. 0DCh
03Fh
040h
0DDh
DATA ROM
RESERVED
0DFh
WINDOW AREA
07Fh
080h
081h
082h
083h
084h
DA0 DATA/CONTROL REGISTER
DA1 DATA/CONTROL REGISTER
DA2 DATA/CONTROL REGISTER
DA3 DATA/CONTROL REGISTER
AFC RESULT REGISTER
KEYBOARD INPUT REGISTER
RESERVED
0E0h
0E1h
0E2h
0E3h
0E4h
0E5h
0E6h
0E7h
0E8h
0E9h
0EAh
0EBh
0ECh
0EDh
0EEh
X REGISTER
Y REGISTER
V REGISTER
W REGISTER
DATA RAM
0BFh
0C0h
0C1h
0C2h
0C3h
0C4h
0C5h
0C6h
0C7h
0C8h
0C9h
RESERVED
PORT A DATA REGISTER
PORT B DATA REGISTER
PORT C DATA REGISTER
RESERVED
DATA RAM BANK REGISTER
BSW CONTROL REGISTER
EEPROM CONTROL REGISTER
SPI CONTROL REGISTER 1
SPI CONTROL REGISTER 2
VS DATA REGISTER 1
PORT ADIRECTION REGISTER
PORT BDIRECTION REGISTER
PORT C DIRECTION REGISTER
RESERVED
VS DATA REGISTER 2
OSD CHARAC. BANK SELECT REG. 0EFh
INTERRUPT OPTION REGISTER
DATA ROM WINDOW REGISTER
0F0h
RESERVED
0FEh
PROGRAM ROM PAGE REGISTER 0CAh
RESERVED
0CBh
0CCh
0CDh
ACCUMULATOR
0FFh
SPI DATA REGISTER
RESERVED
0D1h
0D2h
0D3h
OSD CONTROL REGISTERSLOCATED
IN PAGE6 OF BANKED DATA RAM
TIMER 1 PRESCALER REGISTER
TIMER 1 COUNTER REGISTER
TIMER 1 STATUS/CONTROL REG. 0D4h
VERTICAL START ADDRESS REG. 010h
HORIZONTALSTART ADDRESS REG. 011h
0D5h
RESERVED
0D7h
VERTICAL SPACE REGISTER
012h
013h
HORIZONTAL SPACEREGISTER
WATCHDOG REGISTER
0D8h
BACKGROUND COLOUR REGISTER 014h
GLOBAL ENABLEREGISTER 017h
12/82
ST63140,142,126,156
MEMORY SPACES (Continued)
Figure 14. Data ROM Window Register
Data ROM Addressing. All the read-only data are
physically implemented in the ROM in which the
Program Space is also implemented. The ROM
therefore contains theprogram to be executed and
also the constants and the look-up tables needed
for the program. The locations of Data Space in
which the different constants and look-up tables
are addressed by the ST631xx Core can be con-
sidered as being a 64-byte window throughwhich
it is possible to access to the read-only data stored
in the ROM. This window is located from address
40H to address 7Fh in the Data space and allows
the direct reading of the bytes from the address
000h to address 03Fh in the ROM. All the bytes of
the ROMcan be usedto store either instructions or
read-only data. Indeed, the window can be moved
by step of 64 bytes along the ROM in writing the
appropriate code in the Write-only Data ROM Win-
dow register (DRWR, location C9h). The effective
address of thebyteto beread as adata in theROM
is obtained by the concatenation of the 6 less sig-
nificant bits of the address in the Data Space (as
less significant bits) and the content of the DRWR
(as most significant bits). So when addressing lo-
cation 40h of data space, and 0 is loaded in the
DRWR, the physical addressed location in ROM is
00h.
DWR
Data ROM Window Register
(C9h, Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
DWR0 = Data ROMWindow 0
DWR1 = Data ROMWindow 1
DWR2 = Data ROMWindow 2
DWR3 = Data ROMWindow 3
DWR4 = Data ROMWindow 4
DWR5 = Data ROMWindow 5
DWR6 = Data ROMWindow 6
UNUSED
D7. This bit is not used.
DWR6-DWR0. Theseare the Data Rom Window bits
thatcorrespondtotheupperbitsofdataROMprogram
space. This register is undefinedafterreset.
This register is undefined on reset. Neither
read nor single bit instructions may be used to
address this register.
Note. Care is required when handling the DRWR
as it is write only. For this reason, it is not allowed
to change the DRWR contents while executing in-
terrupts drivers, as the drivercannot save and than
restore its previous content. If it is impossible to
avoid the writing of this register in interrupts driv-
ers, an image of this register must be saved in a
RAM location, and each time the program writes
the DRWR it writes alsothe image register.The im-
age register must be written first, so if an interrupt
occurs between the two instructions the DRWR
register is not affected.
Figure 15. Data ROM Window Memory Addressing
13 12 11 10
9
3
8
2
7
1
6
0
5
4
4
3
3
2
2
1
1
0
0
PROGRAM SPACE ADDRESS
READ
DATA ROM
WINDOW REGISTER
CONTENTS
7
6
5
4
5
DATA SPACE ADDRESS
40h-7Fh
(DWR)
0
1
IN INSTRUCTION
Example:
DWR=28h
0
0
0
0
1
0
0
1
1
0
0
0
0
0
1
DATA SPACE ADDRESS
59h
1
1
1
1
1
0
0
0
0
0
0
ROM
ADDRESS:A19h
1
0
0
1
VR01573B
13/82
ST63140,142,126,156
MEMORY SPACES (Continued)
Data RAM/EEPROM/OSD RAM Addressing
In all members of the ST631xx family 64 bytes of
data RAM are directly addressable in the data
space from 80h to BFh addresses. The additional
192 bytesof RAM, the 128 bytes of EEPROM, and
the OSD RAM can be addressed using the banks
of 64 bytes located between addresses 00h and
3Fh. The selection of the bank is done by program-
ming theData RAM Bank Register (DRBR) located
at the E8h address of the Data Space. In this way
each bankof RAM, EEPROM orOSD RAM can se-
lect 64 bytes at a time. No more than one bank
should be set at a time.
D7. This bit is not used.
DRBR6, DRBR5.Each of these bits, when set, will
select one OSD RAM register page.
DRBR4,DRBR3,DRBR2.Each of these bits, when
set, will select one RAM page.
DRBR1,DRBR0. These bits select the EEPROM
pages.
This register is undefined after reset. Neither
read nor single bit instructions may be used to
address this register.
Table 5 summarizes how to set the Data RAM
Bank Register in order to select the various banks
or pages.
Figure 16. Data RAM Bank Register
Note :
DRBR
Care is required when handling the DRBR as it is
write only. For this reason, it is not allowed to
change the DRBR contents while executing inter-
rupts drivers, as the driver cannot save and than
restore its previous content. If it is impossible to
avoid the writing of this register in interrupts driv-
ers, an image of this register must be saved in a
RAM location, and each time the program writes
the DRBR it writes also the image register.
The image register must be written first, so if an in-
terrupt occurs between the two instructions the
DRBR is not affected.
Data RAM
Bank Register
(E8h, Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
DRBR0 = Data RAM Bank0
DRBR1= Data RAM Bank 0
DRBR2= Data RAM Bank 0
DRBR3= Data RAM Bank 0
DRBR4= Data RAM Bank 0
DRBR5= Data RAM Bank 0
DRBR6= Data RAM Bank 0
UNUSED
Table 5. Data RAM Bank Register Set-up
DRBR Value
Selection
Hex.
01h
02h
04h
08h
10h
20h
40h
Binary
0000 0001
0000 0010
0000 0100
000 1000
0001 0000
0010 0000
0100 0000
EEPROM Page 0
EEPROM Page 1
RAM Page 2
RAM Page 3
RAM Page 4
OSD Page 5
OSD Page 6
14/82
ST63140,142,126,156
MEMORY SPACES (Continued)
EEPROM Description
The data space of ST631xx family from 00h to 3Fh
is paged as described in Table 5. 128 bytes of
EEPROM located in 2 pages of 64 bytes (pages 0,
and 1, see Table 5).
D7. Not used
SB. WRITE ONLY. If this bit is set the EEPROM is
disabled (any access will be meaningless)and the
power consumption of the EEPROM is reduced to
the leakage values.
Through the programming of the Data RAM Bank
Register (DRBR=E8h) the user can select the
bank or page leaving unaffected the way to ad-
dress the static registers. The way to address the
“dynamic” page is to set the DRBR as described in
Table 5 (e.g. to select EEPROM page 0, the DRBR
has to be loaded with content 01h, see Data
RAM/EEPROM/OSD RAM addressing for addi-
tional information). Bits 0 and 1 of the DRBR are
dedicated to the EEPROM.
D5, D4. Reserved, they must be set to zero.
PS. SET ONLY. Once in Parallel Mode, as soon as
the user software sets the PSbit the parallel writing
of the 8 adjacent registers will start. PS is internally
reset at the end of the programming procedure.
Note that less than 8 bytes can be written; after
parallel programming the remaining undefined
bytes will have no particular content.
PE. WRITE ONLY. This bit must be set by the user
program in order to perform parallel programming
(more bytes per time). If PE is set and the “parallel
start bit” (PS) is low, up to 8 adjacent bytes can be
written at the maximum speed, the content being
stored in volatile registers. These 8 adjacent bytes
can be considered as row, whose A7, A6, A5, A4,
A3 are fixed while A2, A1 and A0 are thechanging
bytes. PE is automatically reset at the end of any
parallel programming procedure. PE can be reset
by the user software before starting the program-
ming procedure, leavingunchanged the EEPROM
registers.
The EEPROM pages do not require dedicated in-
structions to be accessed in reading or writing. The
EEPROM is controlled by the EEPROM Control
Register (EECR=EAh). Any EEPROM location can
be read just like any other data location, also in
terms of access time.
To write an EEPROM location takes an average
time of 5 ms (10ms max) and during this time the
EEPROM is not accessible by the Core. A busy
flag canbe read by the Core to know the EEPROM
status before trying any access. In writing the
EEPROM can work in two modes: Byte Mode
(BMODE) and Parallel Mode (PMODE). The
BMODE is the normal way to use the EEPROM
and consists in accessing one byte at a time. The
PMODE consists in accessing 8 bytes per time.
BS. READ ONLY. This bit will be automaticallyset
by the CORE when the user program modifies an
EEPROM register. The user program has to test it
before any read or write EEPROM operation; any
attempt to access the EEPROM while “busy bit” is
set will be aborted and the writing procedure in pro-
gress completed.
Figure 17. EEPROM Control Register
EN. WRITE ONLY. This bit MUST be set to one in
order to write any EEPROM register. If the user
program will attempt to write the EEPROM when
EN= “0” the involved registers will be unaffected
and the “busy bit” will not be set.
EECR
EEPROM Control Register
(EAh, Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
AfterRESET the contentof EECR registerwill be 00h.
EN = EEPROMEnable Bit
BS = EEPROM Busy Bit
PE = Parallel Mode Enable Bit
PS = Parallel Start Bit
Notes :
When the EEPROM is busy (BS=“1”) the EECR
can not be accessed in write mode, it is only possi-
ble to read BS status. This implies that as long as
the EEPROM is busy it is not possible to change
the status of the EEPROM control register. EECR
bits 4 and 5 are reserved for test purposes, and
must never be set to “1”.
Reserved (Must be set Low)
Reserved (Must be set Low)
SB =Stand-by Enable Bit
Unused
15/82
ST63140,142,126,156
MEMORY SPACES (Continued)
INTERRUPT
The ST631xxCore can manage 4 different mask-
able interrupt sources, plus one non-maskable in-
terrupt source (top priority level interrupt). Each
source is associated with a particular interrupt vec-
tor that contains a Jump instruction to the related
interrupt service routine. Each vector is located in
the Program Space at a particular address (see
Table 6). When a source provides an interrupt re-
quest, and the request processing is also enabled
by the ST631xx Core, then the PC register is
loaded with the address of the interrupt vector (i.e.
of the Jump instruction). Finally, the PC is loaded
with the address of the Jump instruction and the in-
terrupt routine is processed.
Additional Notes on Parallel Mode. If the user
wants to perform a parallel programming the first
action should be the set to one the PE bit; from this
moment the first time the EEPROM will be ad-
dressed in writing, the ROW address will be
latched and it will be possible to change it only at
the end ofthe programming procedure or by reset-
ting PE without programming the EEPROM. After
the ROW address latching the Core can “see” just
one EEPROM row (the selected one) and any at-
tempt to write or read other rows will produce er-
rors. Do not read the EEPROM while PE is set.
As soon as PE bit is set,the 8 volatile ROW latches
are cleared. From this moment the user can load
data in the whole ROW or just in a subset. PS set-
ting will modify the EEPROM registers correspond-
ing to the ROW latches accessed after PE. For
example, if the software sets PE and accesses
EEPROM in writing at addresses 18h,1Ah,1Bh
and then sets PS, these three registers will be
modified at the same time; the remaining bytes will
have no particular content. Note that PE is inter-
nally reset at the end of the programming proce-
dure. This implies that the user must set PE bit
between two parallel programming procedures.
Anyway the user can set andthen reset PE without
performing any EEPROM programming. PS is a
set only bit and is internally reset at the end of the
programming procedure. Note that if the user tries
to set PS while PE is not set there will not be any
programming procedure and the PS bit will be un-
affected. Consequently PS bit can not be set if EN
is low. PS can be affected by the user set if, and
only if, EN and PE bits are also set to one.
The relationship between vector and source and
the associated priority is hardware fixed for the dif-
ferent ST631xx devices. For some interrupt
sources it is also possible to select by software the
kind of event that will generate the interrupt.
All interruptscan be disabled by writing to the GEN
bit (global interrupt enable) of the interrupt option
register (address C8h). After a reset, ST631xx is in
non maskable interrupt mode, so no interrupts will
be accepted and NMI flags will be used, until a
RETI instruction is executed. If an interrupt is exe-
cuted, one special cycle is made by the core, dur-
ing that the PC is set to the related interrupt vector
address. A jump instruction at this address has to
redirect program execution to the beginningof the
related interruptroutine. The interrupt detectingcy-
cle, also resets the related interrupt flag (not avail-
able to the user), so that another interrupt can be
stored for this current vector, while its driver is un-
der execution.
STACK SPACE
If additionalinterruptsarrive from the same source,
they will be lost. NMI can interrupt other interrupt
routines at any time, while other interrupts cannot
interrupt each other. If more than one interrupt is
waiting for service, they are executed according to
their priority. The lower the number, the higher the
priority. Priority is, therefore, fixed. Interrupts are
checked during the last cycle of an instruction
(RETI included). Level sensitive interrupts have to
be valid during this period.
The stack space consists of six 12 bit registers that
are used for stacking subroutine and interrupt re-
turn addresses plus the current program counter
register.
16/82
ST63140,142,126,156
INTERRUPT (Continued)
Interrupt Option Register
Table 6. Interrupt Vectors/SourcesRelationships
The Interrupt Option Register (IOR register, loca-
tion C8h) is used to enable/disable the individual
interrupt sources and to select the operating mode
of theexternal interrupt inputs. This register can be
addressed in the Data Space as RAM location at
the C8h address, nevertheless it is write-only reg-
ister that can not be accessed with single-bit op-
erations. The operating modes of the external
interrupt inputs associated to interrupt vectors #1
and #2are selected through bits 5 and 6 of theIOR
register.
Interrupt
Source
Associated
Vector
Vector Address
0FFCh-0FFDh
0FF6h-0FF7h
0FF4h-0FF5h
0FF2h-0FF3h
0FF0h-0FF1h
IRIN/NMI
Pin (1)
Interrupt
Vector # 0 (NMI)
Interrupt
Vector # 1
(2)
None
Interrupt
Vector # 2
Vsync
Timer 1
Timer 2
Interrupt
Vector # 3
Figure 18. Interrupt Option Register
Interrupt
Vector # 4
IOR
Notes:
1. This pin is associated with the NMI Interrupt Vector
2. This vector is not used in ST631xx.
Interrupt Option Register
(C8h, Write Only)
Interrupt Vectors/Sources
D7 D6 D5 D4 D3 D2 D1 D0
The ST631xx Core includes 5 different interrupt
vectors in order to branch to 5 different interrupt
routines. The interrupt vectors are located in the
fixed (or static) page of the Program Space.
Unused
GEN =Global Enable Bit
ES2 = Edge Selection Bit
EL1 = Edge Level Selection Bit
Unused
The interrupt vector associatedwith the non-mask-
able interrupt source is named interrupt vector #0.
It is located at addresses FFCh,FFDh in the Pro-
gram Space. This vector is associated with the
PC6/IRIN pin.
D7. Not used.
EL1. This is the Edge/Level selection bit of inter-
rupt #1. When set to one, the interruptis generated
on low level of the related signal; when cleared to
zero, the interrupt is generated on falling edge.The
bit is cleared to zero after reset and as no interrupt
source is associated to vector #1 on ST631xx, the
user must keep this bit at zero to avoid ghost inter-
rupts from this source.
The interrupt vectors located at addresses
(FF6h,FF7h),
(FF4h,FF5h),
(FF2h,FF3h),
(FF0h,FF1h) are named interrupt vectors #1, #2,
#3 and #4 respectively. These vectors are associ-
ated with TIMER 2 (#4), VSYNC (#2), and TIMER
1 (#3). Interrupt vector (#1) is not used on
ST631xx.
Interrupt Priority
ES2. This is the edge selection bit on interrupt#2.
This bit is used on the ST631xx devices with on-
chip OSD generator for VSYNC detection.
The non-maskable interrupt request has the high-
est priority and can interrupt any other interrupt
routines at any time, nevertheless the other inter-
rupts cannot interrupt each other. If more than one
interrupt request is pending, they are processedby
the ST631xx Core according to their priority level:
vector #1 has the higher priority while vector #4 the
lower. The priority of each interrupt source is hard-
ware fixed.
GEN. This is the global enable bit. When set to one
all interrupts are globally enabled; when this bit is
cleared to zero all interrupts are disabled (EXclud-
ing NMI).
D3 - D0. These bits are not used.
17/82
ST63140,142,126,156
INTERRUPT (Continued)
Interrupt Procedure. The interrupt procedure is
very similar to a call procedure, indeed the user
can consider the interrupt as an asynchronouscall
procedure. As this is an asynchronous event the
user does not know about the context and the time
at which it occurred. As a result the user should
save all the data space registers which will be used
inside the interrupt routines. There are separate
sets of processor flags for normal, interrupt and
non-maskable interrupt modes which are automat-
ically switched and so these do not need to be
saved.
Figure 19. Interrupt Processing Flow-Chart
INSTRUCTION
FETCH
INSTRUCTION
EXECUTE
INSTRUCTION
The following list summarizes the interrupt proce-
dure:
WA S
THE INSTRUCTION
A RETI
NO
LOAD PC FROM
INTERRUPT VECTOR
( FFC / FFD )
ST631xx actions
YES
Interrupt detection
The flags C and Z of the main routine are ex-
changed with the flags C and Z of the interrupt
routine (or the NMI flags)
-
IS THE CORE
ALREADY IN
NORMAL MODE ?
YES
SET
?
-
INTERRUPT MASK
NO
CLEAR
PUSH THE
PC INTO THE STACK
The value of the PC is stored in the first level of
the stack
INTERRUPT MASK
-
The normal interrupt lines are inhibited (NMI
still active)
SELECT
PROGRAM FLAGS
SELECT
INTERNAL MODE FLAG
-
First internal latch is cleared
The related interrupt vector is loaded in the PC.
-
” POP ”
THE STACKED PC
-
User actions
CHECK IF THERE IS
AN INTERRUPT REQUEST
AND INTERRUPT MASK
NO
User selected registers are saved inside the in-
terrupt service routine (normally on a software
stack)
-
?
YES
The source of the interrupt is found by polling
(if more than one source is associated to the
same vector) the interrupt flag of the source.
-
VA000014
Interrupt servicing
Return from interrupt (RETI)
-
ST631xx Interrupt Details
-
ST631xx actions
IR Interrupt (#0). The IRIN Interrupt is connected
to the first interrupt #0 (NMI, 0FFCh). If enabled,
then an interruptwill be generated on a rising edge
at the pin.
Automatically the ST631xx core switches back
to the normal flags (or the interrupt flags) and
pops the previous PC value from the stack
-
Interrupt (#1). On ST631xx no sources are associ-
ated to vector (#1). To avoid any ghost interrupt
due to interrupt (#1) the user must keep the EL1
bit of IOR register to zero.
The interrupt routine begins usually by the identifi-
cation of the device that has generated the inter-
rupt request (by polling). The user should save the
registers which are used inside the interrupt rou-
tine (that holds relevant data) into a softwarestack.
After the RETI instruction execution, the core car-
ries out the previous actions and the main routine
can continue.
18/82
ST63140,142,126,156
INTERRUPT (Continued)
Notes: Global disable does not reset edge sensi-
tive interrupt flags. These edge sensitive interrupts
become pending again when global disabling is re-
leased. Moreover, edge sensitive interrupts are
stored in the related flags also when interrupts are
globally disabled, unlesseach edge sensitive inter-
rupt is also individually disabled before the inter-
rupting event happens. Global disable is done by
clearing the GEN bit of Interrupt option register,
while any individual disable is done in the control
register of the peripheral. The on-chip Timer pe-
ripherals have an interrupt request flag bit (TMZ),
this bit is set to one when the device wants to gen-
erate an interrupt request and a mask bit (ETI) that
must be set to one to allow the transfer of the flag
bit to the Core.
VSYNC Interrupt (#2). The VSYNC Interrupt is
connected to the interrupt #2. When disabled the
VSYNC INT signal is low. Bit 5 of the interrupt op-
tion register C8h is used to select the negative
edge (ES2=0) or the positive edge (ES2=1); the
edge willdepend ontheapplication. Notethat once
an edge has been latched, then the only way to re-
move the latched signal is to service the interrupt.
Care must be taken not to generate spurious inter-
rupts. This interrupt may be used for synchronize
to the VSYNC signal in order to change characters
in the OSD only when the screen is on vertical
blanking (if desired). This method may also be
used to blink characters.
TIMER 1 Interrupt (#3). The TIMER 1 Interrupt is
connected to the fourth interrupt #3 (0FF2h) which
detects a low level (latched in the timer).
TIMER 2 Interrupt (#4). The TIMER 2 Interrupt is
connected to the fifth interrupt #4 (0FF0h) which
detects a high to low level (latched in the timer).
19/82
ST63140,142,126,156
RESET
Watchdog Reset
The ST631xx device can be reset in two ways: by
the external reset input (RESET ) tied low, by
power-on reset and by the digital Watchdog pe-
ripheral.
The ST631xx devices are provided with an on-
chip hardware activated digital watchdog function
in order to provide a graceful recovery from a soft-
ware upset. If the watchdog register is not re-
freshed and the end-of-count is reached, then the
reset state will be latched into the MCU and an in-
ternal circuit pulls down the RESET pin. This also
resets the watchdog which subsequentlyturns off
the pull-down and activates the pull-up device at
the RESET pin. This causes the positive transition
at the RESET pin. The MCU will then exit the reset
state after 2048 clocks on the oscillator pin.
RESET Input
The external active low RESET pin is used to reset
the ST631xx devices and provide an orderly soft-
ware startup procedure. The activation of the RE-
SET pin may occur in the RUN or WAIT mode.
Even short pulses at the reset pin will be accepted
since the reset signal is latched internally and is
only cleared after 2048 clocks at the oscillator pin.
The clocks from the oscillator pin to the reset cir-
cuitry are buffered by a Schmitt Trigger so that an
oscillator in start-up conditions will not give spuri-
ous clocks. The MCU is configured in the Reset
mode aslong asthe signal of theRESET pin is low.
The processing of the program is stopped and the
standard Input/Outputports (port A, port B and port
C) are in the input state (except PC2). As soon as
the level on the RESET pin becomes high, the in-
itialization sequence is executed.
Application Notes
An external resistor between VDD and reset pin is
not required because an internal pull-up device is
provided. The user may prefer to add an external
pull-up resistor.
An internal Power-on device does not guarantee
that the MCU will exit the reset state when VDD is
above 4.5V and therefore the RESET pin should
be externally controlled.
Figure 20. Internal Reset Circuit
20/82
ST63140,142,126,156
RESET (Continued)
Figure 21. Reset & Interrupt Processing
Flow-Chart
Figure 22. Restart Initialization Program
Flow-Chart
RESET
JP
RESET
JP: 2 BYTES/4 CYCLES
RESET VECTOR
NMI MASK SET
INT LATCH CLEARED
( IF PRESENT )
INITIALIZATION
ROUTINE
RETI
RETI: 1BYTES/2 CYCLES
SELECT
NMI MODE FLAGS
PUT FFEh
ON ADDRESS BUS
VA000181
MCU InitializationSequence
When a reset occurs the stack is reset to the pro-
gram counter, the PC is loaded with the address of
the reset vector (located in the program ROM at
addresses FFEh & FFFh). A jump instruction to the
beginning of the program has to be written into
these locations. After a reset a NMI is automat-
ically activated so that the core is in non-maskable
interrupt mode to prevent false or ghost interrupts
during the restart phase. Therefore the restart rou-
tine should be terminated by a RETI instruction to
switch to normal mode and enable interrupts. If no
pending interrupt is present at the end of the reset
routine the ST631xx will continue with the instruc-
tion after the RETI; otherwise the pending interrupt
will be serviced.
YES
IS RESET
STILL PRESENT ?
NO
LOAD PC
FROM RESET LOCATIONS
FFE / FFF
FETCH INSTRUCTION
VA000427
21/82
ST63140,142,126,156
WAIT & STOP MODES
the MCU (normal, interrupt or non-maskable inter-
rupt mode) before the start of the WAIT sequence,
but also of the type of the interrupt request that is
generated. In all cases the GEN bit of IOR has to
be set to 1 in order to restart from WAIT Mode.
Contrary to the operation of NMI in the RUN Mode,
the NMI is masked in WAIT Mode if GEN=0.
The STOP and WAIT modes have been imple-
mented in the ST631xx Core in order to reduce the
consumption of the device when the latter has no
instruction to execute. These two modes are de-
scribed in the following paragraphs. On ST631xx
as the hardware activated digital watchdog func-
tion ispresent the STOP instruction is de-activated
and any attempt to execute it will cause the auto-
matic execution of a WAIT instruction.
Normal Mode. If the ST631xx Core was in the
main routine when the WAIT instruction has been
executed, the ST631xx Core outputs from the wait
mode as soon as any interrupt occurs; the related
interrupt routine is executed and at the end of the
interrupt service routine the instruction that follows
the WAIT instruction is executed if no other inter-
rupts are pending.
WAIT Mode
The configuration of the MCU in the WAIT mode
occurs as soon as the WAIT instruction is exe-
cuted. The microcontroller can also be considered
as being in a “software frozen” state where the
Core stops processing the instructions of the rou-
tine, the contents of the RAM locations and periph-
eral registers are saved as long as the power
supply voltage is higher than the RAM retention
voltage but where the peripherals are still working.
The WAIT modeis used when the user wants to re-
duce theconsumptionof the MCU when it is in idle,
while not losing count of time or monitoring of ex-
ternal events.The oscillator is not stopped in order
to provide clock signal to the peripherals. The tim-
ers counting may be enabled (writing the PSI bit in
TSCR register) and the timer interrupt may be also
enabled before entering the WAIT mode; this al-
lows the WAIT mode to be left when timer interrupt
occurs. If the exit from the WAIT mode is per-
formed with a general RESET (either from the acti-
vation of the external pin or by watchdog reset) the
MCU will enter a normal reset procedure as de-
scribed in the RESET chapter. If an interrupt is
generated during WAIT mode the MCU behaviour
depends on the state of the ST631xx Core before
the initialization of the WAIT sequence, but also of
the kind of the interrupt request that is generated.
This case will be described in the following para-
graphs. In any case, the ST631xx Core does not
generate any delay after the occurrence of the in-
terrupt because the oscillator clock is still available.
Non-maskable Interrupt Mode. If the WAIT in-
struction has been executed during the execution
of the non-maskable interruptroutine, the ST631xx
Core outputs from the wait mode as soon as any
interrupt occurs: the instruction that follows the
WAIT instruction is executed and the ST631xx
Core is still in the non-maskable interrupt mode
even if another interrupt has been generated.
Normal Interrupt Mode. If the ST631xx Core was
in the interrupt mode before the initialization of the
WAIT sequence, it outputs from the wait mode as
soon as any interrupt occurs. Nevertheless, two
cases have to be considered:
If the interrupt is a normal interrupt, the inter-
-
rupt routine in which the WAIT was entered will
be completed with the execution of the instruc-
tion that follows the WAIT and the ST631xx
Core is still in the interrupt mode. At the end of
this routine pending interrupts will be serviced
in accordance to their priority.
If the interrupt is a non-maskable interrupt, the
-
non-maskable routine is processed at first.
Then, the routine in which the WAIT was en-
tered will be completed with the execution of
the instruction that follows the WAIT and the
ST631xx Core is still in the normal interrupt
mode.
STOP Mode
On ST631xx the hardware watchdog is present
and the STOP instruction has been de-activated.
Any attempt to execute a STOP will cause the
automatic execution of a WAIT instruction.
Notes :
If all the interrupt sources are disabled, the restart
of the MCU can only be done bya Resetactivation.
The Wait instruction is not executed if an enabled
interrupt request is pending. In the ST631xx the
hardware activated digital watchdog function is
present. As the watchdog is always activated the
STOP instruction is de-activated and any attempt
to execute the STOP instruction will cause an exe-
cution of a WAIT instruction.
Exit from WAIT Mode
The following paragraphs describe the output pro-
cedure of the ST631xx Core from WAIT mode
when an interrupt occurs. It must be noted that the
restart sequence depends on the original state of
22/82
ST63140,142,126,156
ON-CHIP CLOCK OSCILLATOR
Figure 23. Clock Generator Option (1)
The internal oscillator circuit is designed to require
a minimum of external components. A crystal
quartz, a ceramic resonator, or an external signal
(provided to the OSCin pin) may be used to gener-
ate a system clock with various stability/cost trade-
offs. The typical clock frequency is 8MHz. Please
note that different frequencieswill affect the opera-
tion of those peripherals (D/As, SPI, 62.5 kHz
OUT) whose reference frequencies are derived
from the system clock.
The different clock generator options connection
methods are shown in Figures 24 and 25. One ma-
chine cycle takes 13 oscillator pulses; 12 clock
pulses are needed to increment the PC while and
additional 13th pulse is needed to stabilize the in-
ternal latches during memory addressing. This
means that with a clock frequency of 8MHz the ma-
chine cycleis 1.625µSec.
Figure 24. Clock Generator Option (2)
The crystal oscillator start-up time is a function of
many variables: crystal parameters (especially
RS), oscillator load capacitance (CL), IC parame-
ters, ambient temperature, and supply voltage.It
must be observed that the crystal or ceramic leads
and circuit connections must be as short as possi-
ble. Typical values for CL1 and CL2 are in the
range of 15pF to 22pF but these should be chosen
based on the crystal manufacturers specification.
Typical input capacitance for OSCin and OSCout
pins is 5pF.
The oscillator outputfrequency is internallydivided
by 13 to produce the machine cycle and by 12 to
produce the Timer and the Watchdog clock. A byte
cycle is the smallest unit needed to execute any
operation (i.e.,increment the program counter).An
instruction may need two, four, or five byte cycles
to be executed (See Table 7).
Figure 25. OSCin, OSCout Diagram
Table 7. Intructions Timing with 8MHz Clock
Execution
Instruction Type
Branch if set/reset
Cycles
Time
8.125µs
6.50µs
6.50µs
6.50µs
6.50µs
3.25µs
3.25µs
5 Cycles
4 Cycles
4 Cycles
4 Cycles
4 Cycles
2 Cycles
2 Cycles
Branch & Subroutine Branch
Bit Manipulation
Load Instruction
Arithmetic & Logic
Conditional Branch
Program Control
23/82
ST63140,142,126,156
INPUT/OUTPUT PORTS
Details of I/O Ports
The ST631xx microcontrollers use three standard
I/O ports (A,B,C) with up to eight pins on each port;
refer to the device pin configurations to see which
pins areavailable.
When programmed as an input a pull-up resistor (if
available) can be switched active under program
control. When programmed as an output the I/O
port will operate either in thepush-pull mode orthe
open-drain mode according to the hardware fixed
configuration as specified below.
Each line can be individuallyprogrammed either in
the input mode or the output mode as follows by
software.
Output
Port A. PA0-PA7 are available as an open-drain
only (no push-pull programmability and no resis-
tive pull-up in input mode) capable of withstanding
12V while the normal open drain has standard rat-
ings of VDD + 0.3V. ThisI/O port has been specially
designed for direct LED driving and is able to sink
up to 30mA with a maximum VOL of 1V.
-
Input with on-chip pull-up resistor (selected by
software)
Input without on-chip pull-up resistor (selected
by software)
-
-
Note: pins with 12V open-drain capability do not
have pull-up resistors.
Some Port B and C lines are also used as I/O buff-
ers for signals coming from the on-chip SPI and
OSD.
In output mode the following hardware configura-
tions are available:
Open-drain output 12V (PA0-PA7)
Open-drain output 5V (PB5-PB7, PC3, PC5-
PC7)
-
-
In this case the final signal on the output pin is
equivalent to a wired AND with the programmed
data output.
Push-pull output (PB0-PB4, PC0-PC2, PC4)
If the user needs to use the SPI or the OSD, then
the I/O line should be set in output mode while the
open-drain configuration is fixed in hardware ; the
correspondingdata bit must be set to one.
-
The lines are organized in three ports (port A,B,C).
The ports occupy 6 registers in the data space.
Each bit of these registers is associated with a par-
ticular line (for instance, the bits 0 of the Port A
Data and Direction registers are associated with
the PA0 line of Port A).
PB2 and PB3 must be programmed in input mode
to provide the HSYNC and VSYNC input signals to
the OSD.
There are three Data registers (DRA, DRB, DRC),
that are used to read the voltage level values of the
lines programmedin the input mode, or to write the
logic value of the signal to be output on the lines
configured in the output mode. The port Data Reg-
isters can be read to get the effectivelogic levels of
the pins, but they can be also written by the user
software, in conjunction with the related Data Di-
rection Register, to select the different input mode
options. Single-bit operations on I/O registers (bit
set/reset instructions) are possible but care is nec-
essary because reading in input mode is made
from I/O pins and therefore might be influenced by
the external load, while writing will directly affect
the Port data register causing an undesired
changes of the input configuration. The three Data
Direction registers (DDRA, DDRB, DDRC) allow
the selection of the direction of each pin (input or
output).
On ST631xx the I/O pins with double or special
functions are:
PB2/VSYNC (connected to the OSD VSYNC
signal)
-
PB3/HSYNC (connected to the OSD HSYNC
signal)
-
PB5/SCL (connected to the SPI clock signal)
PB6/SDA (connected to the SPI data signal)
PB7/SEN (connected to the SPI enable signal)
PC2-ON-OFF, this I/O is specially suited to TV
SET ON-OFF and for this reason at reset the
related Data Direction bit will be automatically
set to one (I/O line is in output mode), while the
rest of the port is in input mode
-
-
-
-
PC3/BLANK (connected to the OSD Blank sig-
nal)
-
PC5/R, PC6/G, PC7/B (connected to the OSD
R-G-B signals)
-
All the I/O registers can be read or written as any
other RAM location of the data space. During the
initialization of the MCU, all the I/O registers are
cleared and the input mode with pull-up is selected
on all the pins thus avoiding pin conflicts (with the
exception of PC2 which is set in output mode and
is set low).
All the Port A,B and C I/O lines have Schmitt-trig-
ger input configuration with a typical hysteresis of
1V.
24/82
ST63140,142,126,156
INPUT/OUTPUT PORTS (Continued)
I/O Pin Programming
Figure 25. Port A, B, C Data Direction Register
Each pin can be individually programmedas inputor
output with differentinput and output configurations.
This is achieved by writing to the relevant bit in the
data (DR) and data direction register (DDR). Table
8 shows all the port configurations that can be se-
lected by the user software.
DDRPA, DDRPB,DDRPC
Port A, B, C Data Direction Register
( C4h PA, C5h PB, C6h PCRead/ Write )
D7 D6 D5 D4 D3 D2 D1 D0
PA0 - PA7 = Data Direction Bits
PB0 - PB7 = Data Direction Bits
PC0 -PC7 = Data DirectionBits
“0” Defines bitas Input
Figure 24. Port A, B, C Data Register
DRA, DRB, DRC
”1” Defines bitas Output
Port A, B, C Data Register
( C0h PA, C1h PB, C2h PC Read/ Write )
PA7-PA0. These are the I/O port A data direction
bits. When a bit is cleared to zero the related I/O
line is in input mode, if bit is set to one the related
I/O line is in output mode. Reset at power-on.
D7 D6 D5 D4 D3 D2 D1 D0
PA0 -PA7 =Data Bits
PB0 -PB7 =Data Bits
PC0 - PC7 = Data Bits
PB7-PB0. These are the I/O port B data direction
bits. When a bit is cleared to zero the related I/O
line is in input mode, if bit is set to one the related
I/O line is in output mode. Reset at power-on.
PA7-PA0.These are the I/Oport A data bits. Reset
at power-on.
PC7-PC0. These are the I/O port C data direction
bits. When a bit is cleared to zero the related I/O
line is in input mode, if bit is set to one the related
I/O line is in output mode. Set to 04h at power-on.
Bit 2 (PC2 pin) is set to one (output mode selected)
as this line is intended for TV ON-OFF switching.
PB7-PB0.These are the I/Oport B data bits. Reset
at power-on.
PC7-PC0. These are the I/O port C data bits. Reset
at power-on.
Table 8. I/O Port Options Selection
DDR DR
Mode
Option
With on-chip pull-up
resistor
0
0
Input
Without on-chip pull-up
resistor
0
1
1
Input
X
Output
Open-drain or Push-Pull
Note: X: Means don’t care.
25/82
ST63140,142,126,156
INPUT/OUTPUT PORTS (Continued)
Input/Output Configurations
Notes :
The following schematics show the I/O lines hard-
ware configuration for the different options. Figure
30 shows the I/O configuration for an I/O pin with
open-drain 12Vcapability (standard drive and high
drive). Figure 31 shows the I/O configuration for an
I/O pin with push-pull and with open drain 5V capa-
bility.
The WAIT instruction allows the ST631xx to be
used in situations where low power consumptionis
needed. This can only be achievedhowever if the
I/O pins either are programmed as inputs with well
defined logic levels or have no power consuming
resistive loads in output mode. As the same die is
used for the different ST631xx versions the un-
available I/O lines of ST631xx should be pro-
grammed in output mode.
Figure 26. I/O Configuration Diagram
(Open Drain 12V)
Single-bit operations on I/O registers are possible
but care is necessary because reading in input
mode is made from I/O pins while writing will di-
rectly affectthe Port data register causing an unde-
sired changes of the input configuration.
Figure 27. I/O Configuration Diagram (Open Drain 5V, Push-pull)
26/82
ST63140,142,126,156
TIMERS
The prescaler decrements on rising edge. The
prescaler input is the oscillator frequency divided
by 12 or an external clock at TIMER pin (this is not
available in ST631xx).
Depending on the division factor programmed by
PS2/PS1/PS0 (see table 9) bits in the TSCR, the
clock input of the timer/counter register is multi-
plexed to different sources.
The ST631xx devices offer two on-chip Timer pe-
ripherals consisting of an 8-bit counter with a 7-bit
programmable prescaler, thus giving a maximum
count of 215, and a control logic that allows config-
uring the peripheral operating mode. Figure 30
shows the timer block diagram. The content of the
8-bit counters can be read/written in the
Timer/Counter registers TCR that can be ad-
dressed in the data space as RAM location at ad-
dresses D3h (Timer 1) and DBh (Timer 2). The
state of the 7-bit prescaler can be read in the PSC
register at addresses D2h (Timer 1) and DAh
(Timer 2). The control logic is managed by TSCR
registers at D4h (Timer 1) and DCh (Timer 2) ad-
dresses as described in thefollowing paragraphs.
On division factor 1, the clock input of the prescaleris
alsothat of timer/counter;on factor2,bit 0 ofprescaler
registeris connectedto the clock inputof TCR.
This bit changes its state with the half frequency of
prescaler clock input. On factor 4, bit 1 of PSC is
connected to clock input of TCR, and so on. On di-
vision factor 128, the MSB bit 6 of PSC is con-
nected to clock input of TCR. The prescaler
initialize bit (PSI) in the TSCR register must be set
to one to allow the prescaler (and hence the
counter) to start. If it is cleared to zero then all of
the prescaler bits are set to one and the counter is
inhibited fromcounting.
The prescaler can be given any value between 0
and 7Fh by writing to the related register address,
if bit PSI in the TSCR register is set to one. The tap
of the prescaler is selected using the
PS2/PS1/PS0bits in the control register. Figure 33
shows the timer working principle.
The following description applies to both Timer 1
and Timer2. The 8-bit counter is decrement by the
output (rising edge) coming from the 7-bit pres-
caler and can be loaded and read under program
control. When it decrements to zero then the TMZ
(timer zero) bit in the TSCR is set to one. If the ETI
(enable timer interrupt) bit in the TSCR is also set
to one an interrupt request, associated to interrupt
vector #3 (forTimer 1) and #1 for Timer 2, is gener-
ated. The interrupt of the timer can be used to exit
the MCU from the WAIT mode.
Figure 28. Timer Peripheral Block Diagram
27/82
ST63140,142,126,156
TIMERS (Continued)
Figure 29. Timer Working Principle
Timer Operating Modes
As the external TIMER pin is not available on
ST631xx devices, the only allowed operating mode
is the output mode that have to be selected by set-
ting to 1 bit 4 and by clearing to 0 bit 5 in the TSCR1
register. This procedurewill enableboth Timer 1 and
Timer 2.
Notes :
TMZ is set when the counter reaches 00h ; how-
ever, it may be set by writing 00h in the TCR regis-
ter or setting the bit 7 of the TSCR register. TMZ
bit must be cleared by user software when servic-
ing the timer interrupt to avoid undesired interrupts
when leaving the interrupt service routine. After re-
set, the 8-bit counter register is loaded to FFh while
the 7-bit prescaler is loaded to 7Fh , and the TSCR
register is cleared which means that timer is
stopped (PSI=0) and timer interrupt disabled.
Output Mode (TSCR1 D4 = 1, TSCR1 D5 = 0). On
this mode the timer prescaler is clocked by the
prescaler clock input (OSC/12). The user can se-
lect the desired prescaler division ratio through the
PS2/PS1/PS0 bits. When TCR count reaches 0, it
sets the TMZ bit in the TSCR.
A write to the TCR register will predominate over
the 8-bit counter decrement to 00h function, i.e. if a
write and a TCR register decrement to 00h occur
simultaneously,the write will take precedence, and
the TMZ bit is not set until the 8-bit counter reaches
00h again. The values of the TCR and the PSC
registers can be read accurately at any time.
The TMZ bit can be tested under program control
to perform timer functions whenever it goes high.
Bit D4 and D5 on TSCR2 (Timer 2) register are not
implemented.
Timer Interrupt
When the counter register decrementsto zero and
the software controlled ETI (enable timer interrupt)
bit is set to one then an interrupt request associ-
ated tointerrupt vector #3 (forTimer 1)and to inter-
rupt vector #4 (for Timer 2) is generated. When the
counter decrements to zero also the TMZ bit in the
TSCR register is set to one.
28/82
ST63140,142,126,156
TIMERS (Continued)
The TSCR1 and TSCR2 registers are cleared on
reset. The correct D4-D5 combination must be
written in TSCR1 by user’s software to enable the
operation of Timer 1 and Timer 2.
Figure 30. Timer Status Control Registers
TSCR
Timer 1&2 Status Control
Registers
D4h Timer 1, DCh Timer 2,
Table 9. Prescaler Division Factors
Read/ Write
PS2
0
PS1
0
PS0
0
Divided By
D7 D6 D5 D4 D3 D2 D1 D0
1
2
PS0 = Prescaler Mux. Select
PS1 = Prescaler Mux. Select
PS2 = Prescaler Mux. Select
PSI = Prescaler Initialize Bit
0
0
1
0
1
0
4
*
D4 = TimersEnable Bit
*
D5 = TimersEnable Bit
0
1
1
8
ETI = Enable TimerInterrupt
TMZ = Timer Zero Bit
1
0
0
16
32
64
128
*
Only Available in TSCR1
1
0
1
TMZ. Low-to-high transition indicates that thetimer
count register has decrement to zero. This bit must
be cleared by user software before to start with a
new count.
1
1
0
1
1
1
ETI. This bit, when set, enables the timer interrupt
(vector#3 forTimer 1,vector#4forTimer 2)request.
If ETI=0 the timer interrupt is disabled. If ETI= 1 and
TMZ= 1 an interrupt request is generated.
Figure 31. Timer Counter Registers
TCR
D5. This is the timers enable bit D5. It must be
cleared to 0 togetherwith a set to 1 of bit D4 to en-
able both Timer 1 and Timer 2 functions. It is not
implemented on TSCR2 register.
Timer Counter 1&2 Register
D3h Timer 1, DBh Timer 2, Read/ Write
D7 D6 D5 D4 D3 D2 D1 D0
D4. This is the timers enable bit D4. This bit must
be set to 1 togetherwith a clear to 0 of bit D5 to en-
able both Timer 1 and Timer 2 functions. It is not
implemented on TSCR2 register.
D7 - D0 = Counter bits
D5
0
D4
0
Timers
Disabled
Enabled
Reserved
Figure 32. Timer Counter Registers
0
1
PSC
1
X
TimerPrescaler 1&2 Register
D2h Timer 1, DAh Timer 2, Read/ Write
PSI. Used to initialize the prescaler and inhibit its
countingwhile PSI = 0 the prescalerissetto7Fh and
the counter is inhibited. When PSI = 1 the prescaler
is enabled to count downwards. As long as PSI= 0
both counterand prescaler are not running.
D7 D6 D5 D4 D3 D2 D1 D0
D6 - D0 = Prescaler bits
Always read as “0”
PS2-PS0. These bits select the division ratio of the
prescaler register (see Table 9)
29/82
ST63140,142,126,156
HARDWARE ACTIVATED DIGITAL WATCHDOG
FUNCTION
Figure 34. Hardware Activated Watchdog
Working Principle
The hardware activated digital watchdog function
consists of a down counter that is automatically ini-
tialized after reset so that this function does not
need to be activated by the user program. As the
watchdog function is always activated this down
counter can not be used as a timer. The watchdog
is using one data space register (HWDR location
D8h). The watchdog register is set to FEh on reset
and immediately starts to count down, requiring no
software start. Similarly the hardware activated
watchdog can not be stopped or delayed by soft-
ware.
The watchdog time can be programmed using the 6
MSbitsin the watchdog register,this givesthe possi-
bility to generate a reset in a time between3072 to
196608oscillator cycles in 64 possiblesteps (With a
clock frequency of 8MHz this means from 384µs to
24.576ms). The reset is prevented if the register is
reloaded with the desired value before bits 2-7
decrement from all zeros to all ones.
Thepresenceofthehardwarewatchdog deactivates
the STOP instruction and a WAITinstruction is auto-
matically executed instead of a STOP. Bit 1 of the
watchdog register(set to one at reset) can be used
to generate a software reset if cleared to zero).
Figure 33. Hardware Activated Watchdog Block Diagram
30/82
ST63140,142,126,156
HARDWARE ACTIVATED DIGITAL WATCHDOG
SERIAL PERIPHERAL INTERFACE
FUNCTION (Continued)
The ST631xx Serial Peripheral Interface (SPI) has
been designed to be cost effective and flexible in
interfacing the various peripherals in TV applica-
tions.
Figure 35. Watchdog Register
HWDR
It maintains the software flexibility but adds hard-
ware configurationssuitable to drive devices which
require a fast exchange of data. The three pins
dedicated for serial data transfer (single master
only) can operate in the following ways:
Hardware Activated Watchdog Register
(D8h, Read/ Write)
D7 D6 D5 D4 D3 D2 D1 D0
- as standard I/O lines (software configuration)
- as S-BUS or as I2CBUS (two pins)
- as standard (shift register) SPI
C = Watchdog Activation Bit
SR = Software Reset Bit
T1-T6 = Counter Bits
When using the hardware SPI, a fixed clock rate of
62.5kHz is provided.
T1-T6. These are the watchdog counter bits. It
should be noted that D7 (T1) is the LSB of the
counter and D2 (T6) is the MSB of the counter,
these bits are in the opposite order to normal.
It has to be noted that the first bit that is output on
the data line by the 8-bit shift register is the MSB.
SPI Data/Control Registers
SR. This bit is set to one during the reset phase
and will generate a software reset if cleared to
zero.
For I/O details on SCL (Serial Clock), SDA (Serial
Data) and SEN (Serial Enable) please refer to I/O
Ports description with reference to the following
registers:
C. This is the watchdog activation bit that is hard-
ware set to one; the user can not change the value
of this bit. The watchdog function is always acti-
vated independentlyof changes of value of this bit.
Port B data register, Address C1h (Read/Write).
- BIT D5 “SCL”
- BIT D6 “SDA”
The register reset value is FEh (Bit 1-7 set to one,
Bit 0 cleared).
- BIT D7 “SEN”
Port B data direction register, Address C5h
(Read/Write).
Figure 36. SPI Serial Data Register
SSDR
SPI Serial Data Register
(CCh, Read/ Write)
D7 D6 D5 D4 D3 D2 D1 D0
D0-D7 = Data Bits
D7-D0. These are the SPI data bits. They can be
neither read nor written when SPI is operating
(BUSY bit set). They are undefinedafter reset.
31/82
ST63140,142,126,156
SERIAL PERIPHERAL INTERFACE (Continued)
Figure 38. SPI Control Register 2
Figure 37. SPI Control Register 1
SCR2
SCR1
SPIControl Register2
(ECh, Read/ Write)
SPI Control Register 1
(EBh, Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
2
BSY = Busy Bit 0
S-BUS/I C BUS Selection
ACN =Acknowledge Bit
VRY/S = Verify/Sync.Enable
TX/RX = Enable Bit
Unused
STD/SPIEnable
STP = Stop Bit 2
STR = Start Bit 3
Unused
D7-D4. These bits are not used.
D7-D4. These bits are not used.
STR. This is Start bit for I2CBUS/S-BUS. This bit is
meaninglesswhen STD/SPI enable bit is cleared to
zero. If this bit is set to one STD/SPI bit is also set to
“1” and SPI Start generation, before beginning of
transmission, is enabled.Set to zero after reset.
TX/RX.Write Only. Whenthis bit is set, current byte
operation is a transmission. When it is reset, cur-
rent operation is a reception. Set to zero after re-
set.
VRY/S.Read Only/Write Only. This bit has two dif-
ferent functions in relation to read or write opera-
tion. Reading Operation: when STD and/or TRX
bits is cleared to 0, this bit is meaningless. When
bits STD and TX are set to 1, this bit is set each
time BSY bit is set. This bit is reset during byte op-
eration if real data on SDA line are different from
the output from the shift register. Set to zero after
reset. Writing Operation : it enables (if set to one)
or disables (if cleared to zero) the interrupt coming
from VSYNC pin. Undefined after reset. Refer to
OSD description for additional information.
STP. This is Stop bit for I2CBUS/S-BUS. This bit is
meaningless when STD/SPI enable bit is cleared
to zero. If this bit is set to one STD/SPI bit is also
set to “1” and SPI Stop condition generation is en-
abled. STP bit must be reset when standard proto-
col is used (this is also the default reset
conditions). Set to zero after reset.
STD, SPI Enable. This bit, in conjunction with S-
BUS/I2CBUS bit, allows the SPI disable and will
select between I2CBUS/S-BUS and Standard
shift register protocols. If this bit is set to one, it
selects both I2CBUS and S-BUS protocols; final
ACN.Read Only.If STD bit (D1 ofSCR1 register) is
cleared to zero this bit is meaningless. When STD
is setto one, this bit is set to one if noAcknowledge
has been received. In this case it is automatically
reset when BSY is set again. Set to zero after re-
set.
2
selection between them is made by S-BUS/I CBUS
2
bit. If this bit is cleared to zero when S-BUS/I CBUS
is set to “1” the Standard shift register protocol is
selected. If this bit is cleared to “0” when S-
BUS/I2CBUS is cleared to 0 the SPI is disabled.
Set to zero after reset.
S-BUS/I2CBUS Selection. This bit, in conjunction
with STD/SPI bit, allows the SPI disable and will
select between I2CBUS and S-BUS protocols. If
this bit is cleared to “0” when STDbit is also“0”, the
SPI interface is disabled. If this bit is cleared to zero
when STD bit is set to “1”, the I2CBUS protocol will
be selected. If this bit is set to “1” when STD bit is
set to “1”, the S-BUS protocol will be selected.
Cleared to zero after reset.
BSY.Read/Set Only. This is the busy bit. When a
one is loaded into this bit the SPI interface start the
transmission of the data byte loaded into SSDR
data register or receiving and building the receive
data into the SSDR data register. This is done in
accordance with the protocol, direction and
start/stop condition(s). This bit is automatically
cleared at the end of the current byte operation.
Cleared to zero after reset.
Note :
The SPI shift register is also the data transmission
register and the data received register; this feature
is madepossible by using the serialstructure of the
ST631xx and thus reducing size and complexity.
Table 10. SPI Modes Selection
D1
D0
SPI Function
STD/SP
S-BUS/I2C BUS
0
0
1
1
0
1
0
1
Disabled
STD Shift Reg.
I2C BUS
S-BUS
32/82
ST63140,142,126,156
SERIAL PERIPHERAL INTERFACE (Continued)
S-BUS/I2CBUS Protocol Information
During transmission or reception of data, all ac-
cess to serial data register is therefore disabled.
The reception or transmission of data is started by
setting the BUSY bit to “1”; this will be automat-
ically reset at the end of the operation. After reset,
the busy bit is cleared to “0”, and the hardware SPI
disabled by clearing bit 0 and bit 1 of SPI control
register 1 to “0”. The outputs from the hardware
SPI are “ANDed” to the standard I/O software con-
trolled outputs. If the hardware SPI is in operation
the Port C pins related to the SPI should be config-
ured as outputs using the Data Direction Register
and shouldbe set high. When the SPI is configured
as the S-BUS, the three pins PC0, PC1 and PC3
become the pins SCL, SDA and SEN respectively.
When configured as the I2CBUS the pins PC0 and
PC1 are configured as the pins SCL and SDA; PC3
is not driven and can be used as a general purpose
I/O pin. In the case of the STD SPI the pins PC0
and PC1 become the signals CLOCK and DATA,
PC3 is not driven and can be usedas general pur-
pose I/Opin. The VERIFY bit is available when the
SPI is configured as either S-BUS or I2CBUS. At
the start of a byte transmission, the verify bit is set
to one. If at any time during the transmission of the
following eight bits, the data on the SDA line does
not match the data forced by the SPI (while SCL is
high), then the VERIFY bit is reset. The verify is
available only during transmission for the S-BUS
and I2CBUS; for other protocol it is not defined.
The SDA and SCL signal entering the SPI are buff-
ered in order to remove any minor glitches. When
STD bit is set to one (S-BUS or I2CBUS selected),
and TRXbit is reset (receiving data), and STOP bit
is set(last byte of current communication), the SPI
interface does not generate the Acknowledge, ac-
cording to S-BUS/I2CBUS specifications. PCO-
SCL, PC1-SDA and PC3-SEN lines are standard
drive I/O port pins with open-drain output configura-
tion (maximum voltage that can be applied to these
pins is VDD+ 0.3V).
The S-BUS is a three-wire bidirectional data-bus
with functional features similar to the I CBUS. In
2
fact the S-BUS includes decoding of Start/Stop
conditions and the arbitration procedure in case of
multimaster system configuration (the ST631xx
SPI allows a single-master only operation). The
SDA line, in the I2CBUS represents the AND com-
bination of SDA and SEN lines in the S-BUS. If the
SDA and the SEN lines are short-circuit con-
nected, they appear as the SDA line of the
I2CBUS. The Start/Stopconditions are detected (by
the external peripherals suited to work with S-
BUS/I2CBUS) in the following way:
On S-BUS by a transition of the SEN line (1 to 0
-
Start, 0 to 1 Stop) while the SCL line is at high
level.
On I2CBUS by a transition of the SDA line (10
-
Start, 01Stop) while the SCL line is at high
level.
Start and Stop condition are always generated by
the master (ST631xx SPI can only work as single
master). The bus is busyafterthe start conditionand
can be considered again free only when a certain
time delay is left after the stop condition. In the S-
BUS configuration the SDA line is only allowed to
changeduringthe time SCL line is low. Afterthe start
informationthe SEN line returnsto high level and re-
mains unchangedfor all the data transmission time.
When the transmission is completed the SDA line is
set to high level and, at the same time, the SEN line
returnsto the low level in order to supplythe stop in-
formation with a low to high transition, while2the SCL
line is athigh level. On theS-BUS, ason theI CBUS,
each eight bit information (byte) is followed by one
acknowledged bit which is a high level put on the
SDA line by the transmitter. A peripheral that ac-
knowledgeshas to pulldownthe SDA line during the
acknowledge clock pulse. An addressed receiver
has to generatean acknowledge after the reception
of eachbyte;otherwise the SDA line remains at the
high level during the ninth clock pulse time. In this
case the master transmitter can generate the Stop
condition, via the SEN (or SDA in I2CBUS) line, in
order to abort the transfer.
33/82
ST63140,142,126,156
SERIAL PERIPHERAL INTERFACE (Continued)
Start/Stop Acknowledge. The timing specs of the
S-BUS protocol require that data on the SDA (only
on this line for I2CBUS) and SEN lines be stable
during the “high” time of SCL. Two exceptions to
this rule are foreseen and they are used to signal
the start and stop condition of data transfer.
The sequence from, now on, is different according
to the value of R/W bit.
1. R/W = “0” (Write)
In all the following bytes the master acts as trans-
mitter; the sequence follows with:
a. an optionaldata byte to address (if needed)the
slave location to be written (it can be a word ad-
dress in a memory or a register address, etc.).
On S-BUS by a transition of the SEN line (10
-
Start, 01 Stop) while the SCL line is at high
level.
On I2CBUS by a transition of the SDA line (10
b. a “data” byte which will be written at the ad-
dress given in the previous byte.
-
Start, 01 Stop) while the SCL line is at high
level.
c. further data bytes.
d. a STOP condition
Data are transmitted in 8-bit groups; after each
group, a ninth bit is interposed, with the purpose of
acknowledging the transmitting sequence (the
transmit device place a “1” on the bus, the acknow-
ledging receiver a “0”).
A data transfer is always terminated by a stop con-
dition generated from the master. The ST631xx
peripheral must finish with a stop condition before
another start is given. Figure 44 shows an example
of write operation.
Interface Protocol. This paragraph deals with the
description of data protocol structure. The inter-
face protocol includes:
2. R/W = “1” (Read)
In this case the slave acts as transmitter and,
therefore, the transmissiondirection is changed. In
read mode two different conditions can be consid-
ered:
- A start condition
- A “slave chip address” byte, transmitted by the
master, containingtwo different information:
a. the code identifying the device the master
wants to address (this information is present in
the first seven bits)
a. The master reads slave immediately after first
byte. In this case after the slave address sent
from the master with read condition enabled
the master transmitter becomes master re-
ceiver and the slave receiver becomes slave
transmitter.
b. the direction of transmission on the bus (this
information is given in the 8th bit of the byte);
“0” means “Write”, that is from the master to
the slave, while “1” means “Read”. The ad-
dressed slave must always acknowledge.
b. The master reads a specified register or loca-
tion of the slave. In this case the first sent byte
will contain the slave address with write condi-
tion enabled, then the second byte will specify
the address of the register to be read. At this
moment a new start is given together with the
slave address in read mode and the procedure
will proceed as described in previous point “a”.
34/82
ST63140,142,126,156
SERIAL PERIPHERAL INTERFACE (Continued)
Figure 39.Master Transmit to Slave Receiver (Write Mode)
ACKNOWLEDGE
FROM SLAVE
ACKNOWLEDGE
FROM SLAVE
ACKNOWLEDGE
FROM SLAVE
MSB
S
SLAVE ADDRESS
0
A
WORD ADDRESS
A
DATA
A
P
STOP
R/W
START
Figure 40.Master Reads Slave Immediately After First Byte (read Mode)
ACKNOWLEDGE
FROM SLAVE
ACKNOWLEDGE
FROM MASTER
NO ACKNOWLEDGE
FROM MASTER
MSB
A
MSB
S
SLAVE ADDRESS
1
A
DATA
DATA
1
P
R/W
n BYTES
STOP
START
Figure 41.Master Reads After Setting Slave Register Address (Write Address, Read Data)
ACKNOWLEDGE
FROM SLAVE
ACKNOWLEDGE
FROM SLAVE
S
SLAVE ADDRESS
0
A
X
WORD ADDRESS
A
P
STOP
R/W
START
ACKNOWLEDGE
FROM SLAVE
ACKNOWLEDGE
FROM MASTER
NO ACKNOWLEDGE
FROM MASTER
MSB
A
MSB
S
SLAVE ADDRESS
1
A
DATA
DATA
1
P
START
R/W
STOP
35/82
ST63140,142,126,156
SERIAL PERIPHERAL INTERFACE (Continued)
S-BUS/I2CBUS Timing Diagrams
frequencies up to 62.5kHz, either by being able to
transmit or receive at that speed or by applying the
clock synchronization procedure which will force
the master into a wait state and stretch low peri-
ods.
The clock of the S-BUS/I2CBUS of the ST631xx
SPI (single master only) has a fixed bus clock fre-
quency of 62.5kHz. All the devices connected to
the bus must be able to follow transfers with
Figure 42. S-BUS Timing Diagram
36/82
ST63140,142,126,156
SERIAL PERIPHERAL INTERFACE (Continued)
Figure 43. I2C BUS Timing Diagram
2
Note: The thirdpin, SEN, should be high; it is not used in the I CBUS. Logically SDA is the AND of the S-BUS SDA and SEN.
37/82
ST63140,142,126,156
SERIAL PERIPHERAL INTERFACE (Continued)
Compatibility S-BUS/I2CBUS
Figure 44 (a and b). It is also possible to use mixed
S-BUS/I2CBUS protocols as showed in Figure 48
(c). S-BUS peripherals will only react to S-BUS
Using the S-BUS protocol it is possible to imple-
ment mixed system including S-BUS/I2CBUS bus
peripherals. In order to have the compatibility with
the I2CBUS peripherals, the devices including the
S-BUS interface must have their SDA and SEN
pins connected together as shown in the following
2
protocol signals, while I CBUS peripherals will
only reactto I2CBUS signals. Multimaster configu-
ration isnot possible with the ST631xx SPI (single
master only).
Figure 44.S-BUS/I2C BUS Mixed Configurations
(b)
(a)
(c)
38/82
ST63140,142,126,156
SERIAL PERIPHERAL INTERFACE (Continued)
Figure 45.STD Bus (Hardware Bus Disabled)Timing Diagram
STD SPI Protocol (Shift Register)
This protocol is similar to the I2CBUS with the ex-
ception that there is no acknowledge pulse and
there are no stop or start bits. The clock cannot be
slowed down by the externalperipherals.
that the SCL line is indeed high beforeproceeding
with the START of another I2C or SBUS transmis-
sion. In all other cases the SCL clock slowdown
feature is operational.
SPI Standard Bus Protocol: The standard bus
protocol is selected by loading the SPI Control
Register 1 (SCR1 Add. EBh). Bit 0 named I2C must
be set at one and bit 1 named STD mut be reset.
When the standard bus protocol is selected bit 2 of
the SCR1 is meaningless.
The I/O ports associated with the SPI should be
programmed as outputs with data high in order not
to inhibit the functionality of the hardware SPI.
SPI APPLICATION NOTES
Stop Clock Slowdown: In the ST631xx family of
devices when operating in theI2C orSBUS modes,
there is no internal clock slowdown for the final
STOP clock. Slowdown means that if an external
peripheral requires extra time it will hold the
ST631xx SCL clock low. To be fully I2C and SBUS
compatible in this respect, the SW should check
2
This bit named STOP bit is used only in I CBUS or
SBUS. However take care thet THE STOP BIT
MUST BE RESET WHEN THE STANDARD PRO-
TOCOL IS USED. This bit is set to ZERO after RE-
SET.
39/82
ST63140,142,126,156
14-BIT VOLTAGE SYNTHESIS TUNING
PERIPHERAL
Table 11. Fine Tuning Pulse Addition
The ST631xx on-chip voltage synthesis tuning pe-
ripheral has been integrated to allow the genera-
tion of tuning reference voltage in low/mid end TV
set applications. The peripheral is composed of a
14-bit counter that allows the conversion of the
digital content in a tuning voltage, available at the
VS output pin, by using Pulse Width Modification
(PWM), and Bit Rate Multiplier (BRM) techniques.
The 14-bit counter gives 16384 steps which allows
a resolution of approximately 2mV over a tuning
voltage of 32V; this corresponds to a tuning resolu-
tion of about 40kHz per step in the UHF band (the
actual value will depend on the characteristics of
the tuner).
N° of Pulses added at
the following cycles
(0...127)
Fine Tuning
(7 LSB)
0000001
0000010
0000100
0001000
0010000
0100000
1000000
64
32, 96
16, 48, 80, 112
8, 24, ....104, 120
4, 12, ....116, 124
2, 6, .....122, 126
1, 3, .....125, 127
The tuning word consists of a 14-bit word con-
tained in the registers VSDATA1 (location 0EDh)
and VSDATA2 (location 0EEh). Coarse tuning
(PWM) is performed using theseven MSBits,while
fine tuning (BRM) is performed using the data in
the seven LSBits. With all zeros loaded the output
is zero; as the tuning voltage increases from all ze-
ros, the number of pulses in one period increas to
128 with all pulses being the same width. For val-
ues larger than 128, the PWM takes over and the
number of pulses in one period remains constant
at 128, but the width changes. At the other end of
the scale, when almost all ones are loaded, the
pulses will start to link together and the number of
pulses will decrease. When all ones are loaded,
the output will be almost 100% high but will have a
low pulse (1/16384 of the high pulse).
The VS output pin has a standard drive push-pull
output configuration.
VS Tuning Cell Registers
Figure 46. Voltage Synthesis Data Register 1
VSDR1
Voltage Synthesis Data Register 1
(EDh, Write only)
D7 D6 D5 D4 D3 D2 D1 D0
Output Details
VS Data Bits (LSB)
Inside the on-chip Voltage Synthesis are included
the registerlatches, a referencecounter, PWMand
BRM control circuitry. In the ST631xx the clock for
the 14-bit reference counter is 2MHz derived from
the 8MHz system clock. From the circuit point of
view, the seven most significant bits control the
coarse tuning, while the seven least significant bits
control the fine tuning. From the application and
software point of view, the 14 bits can be consid-
ered as one binary number.
D7-D0. These are the 8 least significant VS data
bits. Bit 0 is the LSB. This register is undefined on
reset.
Figure 47. Voltage Synthesis Data Register 2
VSDR2
As already mentionedthe coarse tuning consistsof
a PWM signal with 128 steps; we can consider the
fine tuning to cover 128 coarse tuning cycles. The
additionof pulsesis described inthe following Table.
Voltage Synthesis Data Register 2
(EEh, Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
VS Data Bits (LSB)
Unused
D7-D6. These bits are not used.
D5-D0. These are the 6 most significant VS data
bits. Bit 5 is the MSB. This register is undefined on
reset.
40/82
ST63140,142,126,156
6-BIT PWM D/A CONVERTER AND 62.5 kHz
OUTPUT FUNCTION
62.5 kHz Output
The D/A macrocell contains four PWM D/A outputs
(31.25kHz repetition, DA0-DA3) with six bit resolu-
tion plus a 62.5kHz open-drain output pin (OUT1)
specially suited for multistandard chroma proces-
sors driving. Both the D/A and OUT1 functions can
be disabled bysoftwareallowing the DA0-DA3 and
OUT1 pins to be used as general purpose open-
drain output pins able to withstand signals with up
to 12Vamplitude.
This pin providesa 62.5 kHz signalwith a 50%duty
cycle; the output is enabled by a dedicated enable
bit (E0h register bit 7). When the 62.5kHz fre-
quency is disabled then the output is controlled by
the OUT1 bit and the line can be used as general
purpose open-drain output (E1h bit 7). The OUT1
output isopen-drain with standard current drive ca-
pability and able to withstand signals with up to
12V amplitude.
6-Bit D/A Converters
D/A and OUT1 Data/Control Registers
Each D/A converter of ST631xx is composed by
the following main blocks:
This paragraph deals with the description of D/A
and OUT1data/controlregisters. Somebits ofDA2
and DA3 data/controlregisters are used for exter-
nal interrupt enable and A/D reference voltage
shift, please referto A/D and IR descriptionsfor ad-
ditional information.
- pre-divider
- 6-bit counter
- data latches and compare circuits
The pre-divider uses the clock input frequency
(8MHz) and its output clocks the 6-bit free-running
counter. The data latched in the four registers
(E0h, E1h, E2h and E3h) control the four D/A out-
puts (DA0,1,2 and 3). When all zeros are loaded
the relevant output is an high logic level; all 1’s cor-
respond to a pulse with a 1/64 duty cycle and al-
most 100% zero level. A 7th bit (bit D6) is used to
enable therelevant D/A output;when zero, the D/A
is no longer enabled and it forces the output to
zero. If the other six bits are all zero then the output
is controlledonly by the enable bit.
Figure 49. DA0 Data/Enable Register
DA0
DA0 Data/Control Registers
(E0h, Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
Data Bit 0
Data Bit 1
The repetition frequency is 32.5kHz and is related
to the 8MHz clock frequency. All D/A outputs are
open-drain with standard current drive capability
and able to withstand up to 12V.
Data Bit 2
Data Bit 3
Data Bit 4
Data Bit 5
DAE D/A Enable Bit
FO1 62.5kHzSelection Bit
Figure 48. 6-bit PWM D/A & 62.5kHz Output
Configuration
DA0-DA5. These are the 6 bits of the PWM digital
to analog converter . Undefined after reset.
DAE. This is theD/A 0 enablebit. If zero, theoutputof
the D/A is forced to zero; if one, the outputof the D/A
dependson bits DA0..DA5.Undefinedafterreset.
FO1. This is the 62.5kHz frequency output/ OUT1
selection bit. If one, the OUT1 pin will give a
62.5kHz frequency; if zero the OUT1 pin can be
used as general purpose open-drain output and
the value present on the pin depends on the value
of OUT1 bit programmed in the DA1 data/control
register. Undefined after reset.
41/82
ST63140,142,126,156
6-BIT PWM D/A CONVERTERS AND 62.5 kHz
OUTPUT FUNCTION (Continued)
DA0-DA5. These are the 6 bits of the PWM digital
Figure 50. DA1 Data/Enable Register
to analog converter bits. Undefined after reset.
DA1
DAE. This is the D/A 2 enable bit. If zero, the out-
put of the D/A is forced to zero; if one, the output of
the D/A depends on bits DA0..DA5. Undefined af-
ter reset.
DA1 Data/Control Registers
(E1h, Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
IEN. This is the external interrupt enable. If set to
one, the interrupt coming from the external inter-
rupt pin is enabled, if this bit is cleared the interrupt
is disabled. Undefined after reset. This interrupt is
associated to the NMI interrupt vector. Refer to IR
and interrupt descriptions for additional informa-
tion.
Data Bit0
Data Bit1
Data Bit2
Data Bit3
Data Bit4
Data Bit5
DAE D/A Enable Bit
OUT1 Data Bit
Figure 52. DA3 Data/Enable Register
DA0-DA5. These are the 6 bits of the PWM digital
to analog converter. Undefined after reset.
DA3
DAE. This is the D/A 1 enable bit. If zero, the out-
put of the D/A is forced to zero; if one, the output of
the D/A depends on bits DA0..DA5. Undefined af-
ter reset.
DA3 Data/Control Registers
(E3h, Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
OUT1. This is the OUT1 data bit. The content of
this bit is output onthe OUT1 pin when the 62.5kHz
frequency function is disabled (FO1 bit in DA0 reg-
ister is cleared to zero). Undefined after reset.
Data Bit 0
Data Bit 1
Data Bit 2
Data Bit 3
Data Bit 4
Figure 51. DA2 Data/Enable Register
Data Bit 5
DAE D/A Enable Bit
ADSH A/D ReferenceShift
DA2
DA2 Data/Control Registers
(E2h Write Only)
DA0-DA5. These are the 6 bits of the PWM digital
to analog converter. Undefinedafter reset.
D7 D6 D5 D4 D3 D2 D1 D0
DAE. This is the D/A 3 enable bit. If zero, the out-
put of the D/A is forced to zero; if one, the output of
the D/A depends on bits DA0..DA5. Undefined af-
ter reset.
Data Bit0
Data Bit1
Data Bit2
ADSH. This is the analog to digital converter refer-
ence voltage shift bit. If set to one, the AFC block
has reference voltages on 1V border. If set to zero,
on 0.5V border. Undefined after reset. Refer to
AFC for additional information.
Data Bit3
Data Bit4
Data Bit5
DAE D/A Enable Bit
IEN IR Interrupt Enable
42/82
ST63140,142,126,156
AFC A/D INPUT, KEYBOARD INPUTS
AND BANDSWITH OUTPUTS
The AFC macrocell contains an A/D comparator
with five levels at intervals of 1V from 1V to 5V. The
levels can all be lowered by 0.5V to effectivelydou-
ble the resolution. This A/D can be used to perform
the AFC function. In addition this cell offers also a
keyboard input register of three bits used to per-
form a keyboard scan and 4 open-drain outputs
(able to withstand signals up to 12V) that can be
used to perform band switch function.
Figure 54. BSW, DA, OUT1 Output Configu-
ration Diagram
Figure 53. AFC, KBY Inputs Configuration Dia-
grams
A/D Comparator
The A/D used to perform the AFC function (when
high threshold is selected) has the following volt-
age levels: 1,2,3,4 and 5V. Bits 0-2 of AFC result
register (E4h address) will provide the result in bi-
nary form (less than 1V is 000, greater than 5V is
101).
If the application requires a greater resolution, the
sensitivitycan be doubledby clearing to zero bit 7 of
DA3 Data/Control register, address E3h (refer to
D/A description for additional information). In this
case all levels are shifted lower by 0.5V. If the two
results are now added within a software routine
then the A/D S-curve can be located within a resolu-
tion of 0.5V.The A/D inputhas high impedanceable
to withstand up to 13V signals (input level toler-
ances ± 200mv absolute and ± 100mv relative to
5V).
AFC, Keyboard Inputs and Bandswitch Out-
puts Data/Control Registers
Figure 55. AFC Result Register
AFCR
AFC Result Register
(E4h, Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
AD2-AD0 A/D= Conversion
Result
Unused
D7-D3. These bits are not used.
AD0-AD2. These bits store the real time conver-
sion of the value present on the AFC input pin. No
reset value.
43/82
ST63140,142,126,156
AFC A/D INPUT, KEYBOARD INPUTS
INFRARED INPUT (IRIN)
AND BANDSWITH OUTPUTS(Continued)
The IRIN pin is directly connected to the NMI inter-
rupt and acts as external interrupt pin (refer to in-
terrupt description for additional information).
Figure 56. Keyboard Input Register
KBYREG
The enable/disable of this interrupt can be man-
aged with the write only IEN bit available in the
DA2 Data/Control Register (Address E2h, bit D7).
When this bit is set to one the interrupt is enabled
otherwise it is disabled.
Keyboard Input Register
(E5h, Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
The IRIN pin is RISING EDGE sensitive.
KBY0 Input Data Bit
KBY1 Input Data Bit
KBY2 Input Data Bit
Unused
Application Note
When the IR interrupt is enabled, then a rising
edge on the IR pin will generate an interrupt; if the
IR interrupt is disabled, no IR interrupts can occur.
Care should be taken because if the IR pin is high
when the IR interrupt is enabled, an interrupt will
also be generated; the following method to elimi-
nate noise can also be used if the SW engineer
wishes to enable/disable the IR interrupt.
D7-D3. These bits are not used.
KBY0-KBY2. These bits store the logic level pre-
sent at KBY0, KBY1 and KBY2 input pins. No reset
value. This input pins have CMOS levels with on-
chip pull-up resistor (100kΩ typical).
If a Low-cost infra-red receiver is used, the cus-
stomer may wish to test the IR signal by software
after an interrupt in order to verify that there is a
good pulse and not just noise. The IRIN pin cannot
be read, so in this case it should be connected in
parallel with another pin so the signal can be read.
Furthermore the IRIN pin is sensitive to a rising
edge interrupt; this means that the input to the pin
should be low in the presence of no infra-red sig-
nal, but since most infra-red receiver modules give
a high signal, the signal will need to be inverted
with a transistor.
Figure 57. Bandswitch Output Register
BSWREG
Bandswitch Output Register
(E9h, Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
BSW0 Output Bit
BSW1 Output Bit
BSW2 Output Bit
Unused
BSW3 Output Bit
D6-D3. These bits are not used.
BSW0-BSW2,BSW3. The writing into these bits
will cause the correspondingBSW open-drain out-
put line to switch to the programmed level. Unde-
fined after reset.
44/82
ST63140,142,126,156
ON-SCREEN DISPLAY (OSD)
Each line must begin witha formatcharacterwhich
describes the format of that line and of the first
word. This character is not displayed.
The ST631xx OSD macrocell is a CMOS LSI char-
acter generator which enable display of characters
and symbols on the TV screen. The character
rounding function enhances the readability of the
characters. The ST631xx OSD receives horizontal
and vertical synchronization signal and outputs
screen information via R, G, B and blanking pins.
The main characteristicsof the macrocell are listed
below:
A space character defines the format of sub-
sequent words. A space character is denoted by a
one inbit 6 in the display RAM. If bit 6 of the display
RAM is a zero, the other six bits define one of the
64 display characters.
The colour, background and enable can be pro-
grammed by word. This information is encoded in
the space character between words or in the for-
mat character at the beginning of each line. Five
bits define the colour and background of thefollow-
ing word, and determine whether it will be dis-
played or not.
Number of display characters: 5 lines by 15
columns.
-
Number of character types: 128 characters in
two banks of 64 characters. Only one bank
-
per screen can be used.
Character size: Four character heights (18h,
36h 54h, 72h), two heights are available per
screen, programmable by line.
-
Characters are storedin a 6 x9 dotformat. Onedot
is defined vertically as 2h (horizontal lines) and
horizontally as 2/fosc if the smallest character size
is enabled. There is no space between characters
or lines if the vertical spaceenable (VSE) and hori-
zontal space enable (HSE) bits are both zero. This
allows the use of special graphics characters.
Character format: 6x9 dots with character
rounding function.
-
Character colour: Eight colours available pro-
grammable by word.
-
Display position: 64 horizontal positions by
2/fosc and 63 vertical positions by 4 h
-
The normal alphanumeric character set is format-
ted to be 5 x 7 with one empty row at the top and
one at the bottom and one empty column at the
right. If VSE and HSE are both zero, then the spac-
ing between alphanumeric characters is 1 dot and
the spacing between lines ofalphanumericcharac-
ters is 2h.
Word spacing: 64 positions programmable
-
from 2/fosc to 128/fosc
.
Line spacing: 63 positions programmable from
4 to 252 h.
Background: No background, square back-
ground or fringe background programmable by
word.
-
-
The character size is programmed by line through
the use of the size bit (S) in the format character
and the global size bits (GS1 and GS2). The verti-
cal spacing enable bit (VSE) located in the format
character controls the spacing between lines. If
this bit is set to one, the spacing between lines is
defined by the vertical spacing register, otherwise
the spacing between lines is 0.
Background colour: Two of eight colours avail-
able programmable by word.
Display output: Three character data output
terminals (R,G,B) and a blank output terminal.
Display on/off: Display data may be pro-
grammed on or off by word or entire screen.
The entire screen may be blanked.
-
-
-
The spacing between words is controlled by the
horizontal space enable bit (HSE) located in the
space character.If this bit is set to one, the spacing
between wordsis defined bythe horizontal spacing
register, otherwise the space character width of 6
dots is the spacing between words.
Format Specification
The entire display can be turned on or off through
the use of the global enable bit or the display may
be selectively turned on or off by word. To turn off
the entiredisplay, the global enable bit (GE) should
be zero. If the global enable is one, the display is
controlled by the word enablebits (WE). Theglobal
enable bit is located in the global enable register
and the word enable bit is located in the space
character preceding the word.
The formats for the display character, space
character and format character are described
hereafter.
45/82
ST63140,142,126,156
ON-SCREEN DISPLAY(Continued)
Figure 58. Space Character Register
Explanation
WE. Word Enable. The word enable bit defines
whether or not the following word isdisplayed.
“0” -The word is not displayed.
“1” -If the global enable bit is one, then the word is
displayed.
Space Character Format
See Data RAM Table Description
for Specific Address
( Write Only)
HSE. Horizontal Space Enable. The horizontal
space enable bit determines the spacing between
words. The space between characters is always 0.
The alphanumeric character set is implemented in
a 5 x 7 format with one empty column to the right
and one empty row above and below so that the
space between alphanumeric characters will be
one dot.
D7 D6 D5 D4 D3 D2 D1 D0
HSE = Horizontal SpaceEnable
WE = Word Enable Bit
BGS = Backround Select
B = B Colour Bit
G = G Colour Bit
R = R Colour Bit
Fixed to “1”
“0” -The space between words is equal to the width
of the space character, which is 6 dots.
Unused
“1” -The space between words is defined by the
value in the horizontal space register plus the
width of the space character.
D7. Not used.
Figure 59. Format Character Register
Explanation
D6. This pin is fixed to “1”.
R, G, B. Colour. The 3 colour control bits define the
colour of the following word as shown in table be-
low.
Format Character
See Data RAM Table Description
for Specific Address
Space Character RegisterColour Setting.
( Write Only)
R
0
0
0
0
1
1
1
1
G
0
0
1
1
0
0
1
1
B
0
1
0
1
0
1
0
1
Colour
Black
D7 D6 D5 D4 D3 D2 D1 D0
VSE = Vertical Space Enable
WE = Word Enable Bit
BGS = Backround Select
B = B Colour Bit
Blue
Green
Cyan
G = G Colour Bit
R =R ColourBit
Red
S = Character Size Control Bit
Unused
Magenta
Yellow
White
D7. This bit is not used
BGS. Background Select. The background select
bit selectsthe desired background for thefollowing
word. There are two possible backgrounds defined
by the bits in the Background Control Register.
S. Character Size. The character size bit, along
with the global size bits (GS2 and GS1) located in
the horizontalspace register, specify the character
size for each line as defined in Table 14.
“0” -The background on the following word is en-
abled by BG0 and the colour is set by R0, G0,
and B0.
R, G, B. Colour. The 3 colour control bits define the
colour of the following word as shown in Table 13.
BGS. Background Select. The background select
bit selects the desired background for thefollowing
word. There are two possible backgrounds defined
by the bits in the Background Control Register.
“1” -The background on the following word is en-
abled by BG1 and the colour is set by R1, G1,
and B1.
“0” -The background on the following word is en-
abled by BG0 and the colour is set by R0, G0,
and B0.
46/82
ST63140,142,126,156
ON-SCREEN DISPLAY(Continued)
Figure 60. Display Character Register
Explanation
“1” -The background on the following word is en-
abled by BG1 and the colour is set by R1, G1,
and B1.
Display Character
See Data RAM Table Description
WE. Word Enable. The word enable bit defines
whether or not the following word is displayed.
for specific Addresses
“0” -The word is not displayed.
( Write Only)
“1” -If the global enablebit is one, then the word is
displayed.
D7 D6 D5 D4 D3 D2 D1 D0
VSE. Vertical Space Enable. The vertical space
enable bit determines the spacing between lines.
C5-C0 = CharacterTypes
controlBit
“0” -The space between lines is equal to 0h. The al-
phanumeric character set is implemented in a
5 x7 format with one empty column to the right
and one empty row above and onebelow and
stored in a 6 x 9 format.
Fixed to “0”
Unused
D7. This bit is not used.
D6. This bit is fixed to “0”.
“1” -The space between lines is defined by the
value in the vertical space register.
C5-C0. Character type. The 6 character type bits
define one of the 64 available character types.
These character types are shown on the following
pages.
Table 13. Format Character Register Colour
Setting.
Character Types
R
0
0
0
0
1
1
1
1
G
0
0
1
1
0
0
1
1
B
0
1
0
1
0
1
0
1
Colour
Black
The character set is user defined as ROM mask
option.
Blue
Register and RAM Addressing
Green
Cyan
The OSD contains seven registers and 80 RAM lo-
cations. The seven registers are the Vertical Start
Address register, Horizontal Start Address regis-
ter, Vertical Space register, Horizontal Space reg-
ister, Background Control register, Global Enable
register and Character Bank Select register. The
Global Enable register can be written at any time
by the ST631xx Core. The other six registers and
the RAM can only be read or written to if the global
enable is zero.
Red
Magenta
Yellow
White
Table 14. Format Character Register Size
Setting
The six registers and the RAM are located on two
pages of the paged memory of the ST631xx
MCUs; the Character Bank Select register is lo-
cated outside the paged memory at address EDh.
Each page contains 64 memory locations. This
paged memory is at memory locations 00h to 3Fh
in the ST631xx memory map. A page of memory is
enabled by setting the desired page bit, located in
the Data Ram Bank Register, to a one. The page
register is location E8h. A one in bit five selects
page 5, located on the OSD and a one in bit 6 se-
lects page 6 on the OSD. Table 15 shows the ad-
dresses of the OSD registers and RAM.
GS2 GS1
S
0
1
0
1
0
1
0
1
Vertical Height Horizontal length
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
18h
36h
18h
54h
36h
54h
36h
72h
6 TDOT
12 TDOT
6 TDOT
18 TDOT
12 TDOT
18 TDOT
12 TDOT
24 TDOT
TDOT= 2/f
osc
47/82
ST63140,142,126,156
ON-SCREEN DISPLAY(Continued)
Table 15. OSD Control Registers and Data
RAM Addressing
Figure 62. Vertical Start Address Register
VSAR
Page
Address
00h - 3Fh
00h - 0Fh
10h
Register or RAM
RAM Locations 00h - 3Fh
RAM Locations 00h - 0Fh
Vertical Start Register
Vertical Start Address Register
(10h - Page 6, Write Only)
5
6
6
6
6
6
6
6
D7 D6 D5 D4 D3 D2 D1 D0
11h
Horizontal Start Register
Vertical Space Register
Horizontal Space Register
Background Control Register
Global Enable Register
VSA5-VSA0 = Vertical Start
Addressbits
12h
FR = Fringe Backround
Controlbit
13h
Unused
14h
17h
D7. This bit is not used
No
Page
EDh
Character Bank Select Register
FR. Fringe Background.This bit changes the back-
ground from a box background to a fringe back-
ground. The background is enabled by word as
defined by either BG0 or BG1.
OSD Global Enable Register
“0” - The background is defined to be a box which
is 7 x 9 dots.
This register contains the global enable bit (GE). It
is the only register that can be written at any time
regardless of the state of the GE bit. It is a write
only register.
“1” - The background is defined to be a fringe.
VSA5-VSA0. Vertical Start Address. These bits
determine the start position of the first line in the
vertical direction. The 6 bits can specify 63 display
start positions of interval 4h. The first start position
will be the fourth line of the display. The vertical
start address is defined VSA0 by the following for-
mula.
Figure 61. Global Enable Bit
Global Enable
Register
17h - Page 6
( Write Only)
Vertical Start Address= 4h(25(VSA5) + 24(VSA4) +
D7 D6 D5 D4 D3 D2 D1 D0
23(VSA3) + 22(VSA2) + 21(VSA1) + 20(VSA0))
The case of all Vertical Start Address bits being
zero is illegal.
GE = Global Enable Bit
Unused
D7-D1. These bits are not used
GE. Global Enable. This bit allows the entire dis-
play to be turned off.
“0” - The entire display is disabled. The RAM and
other registersof the OSD can be accessed by
the Core.
“1” - Display of words is controlled by the word en-
able bits (WE) located in the format or space char-
acter. The other registers and RAM cannot be
accessed by the Core.
48/82
ST63140,142,126,156
ON-SCREEN DISPLAY(Continued)
Figure 64. Vertical Space Register
Figure 63. Horizontal Start Address Register
VSR
HSAR
Vertical Space Register
(12h - Page 6, Write Only)
Horizontal Start Address Register
(11h - Page 6, Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
VS5-VS0 =VerticalSpace
SCB = Screen Blanking bit
Unused
HSA5-HSA0 = Horizontal Start
Address bits
SBD = Space Blanking
Disabled bit
Unused
D7. This bit is not used
D7. This bit is not used.
SCB. Screen Blanking. This bit allows the entire
screen to be blanked.
SBD. Space Blanking Disable. This bit controls
whether or not the background is displayed when
outputting spaces. If two background colours are
used on adjacent words, then the background
should not be displayed on spaces in order to
make a nice break between colours. If an even
background around an area of text is desired, as in
a menu, then the background should be displayed
when outputtingspaces.
“0” -The blanking output signal (VBLK) is active
only when displaying characters.
“1” -The blanking output signal (VBLK) is always
active. Characters in the display RAM are still
displayed.
When this bit is set to one, the screen is blanked
also without setting the Global Enable bit to one
(OSD disabled).
“0” -The background during spaces is controlled by
the backgroundenable bits (BG0 and BG1) lo-
cated in the Background Control register.
VS5 , VS0. Vertical Space. These bits determine
the spacing between lines if theVertical Space En-
able bit (VSE) in the format character is one. If VSE
is zero there will be no spaces between lines. The
Vertical Space bits can specify one of 63 spacing
values from 4h to 252h. The space between lines
is defined by the following formula.
“1” -The background is notdisplayed when output-
ting spaces.
HSA5, HSA0 - Horizontal Start Address bits.
These bits determine the start position of the first
character in the horizontal direction. The 6 bits can
specify 64 display start positions ofinterval 2/fosc or
400ns. The first start position will be at 4.0µs be-
cause of the time needed to access RAM and
ROM before the first character can be displayed.
The horizontal start address is defined by the fol-
lowing formula.
Space between lines = 4h(25(VS5) + 24(VS4) +
23(VS3) + 22(VS2) + 21(VS1) + 20(VS0))
The case of all Vertical Start Address bits being
zero is illegal.
Horizontal Start Address = 2/fosc(10.0 + 25(HSA5)
+ 24(HSA4) + 23(HSA3) + 22(HSA2) + 21(HSA1) +
20(HSA0))
49/82
ST63140,142,126,156
ON-SCREEN DISPLAY(Continued)
Figure 65. Horizontal Space Register
Background Control Register
This register sets up two possible backgrounds.
The background select bit (BGS) in the format or
space character will determine which background
is selected for the current word.
HSR
Horizontal Space Register
(13h - Page 6, Write Only)
Figure 66. Background Control Register
D7 D6 D5 D4 D3 D2 D1 D0
BCR
HS5-HS0 = Horizontal Space
Backround Control Register
(14h - Page 6, Write Only)
GS1 =Global Size Bit 1
GS2 =Global Size Bit 2
D7 D6 D5 D4 D3 D2 D1 D0
BK0 = Backround Enable Bit 0
BK1 = Backround Enable Bit 1
B0 =B Colour Backround Bit 0
B1 =B Colour Backround Bit 1
G0 = G Colour Backround Bit 0
G1 = G Colour Backround Bit 1
R0 = RColour Backround Bit 0
R1 = RColour Backround Bit 1
GS2,GS1. Global Size. These bits along with the
size bit (S) located in the Character format word
specify the character size for each line as defined
in Table 16.
Table 16. Horizontal Space Register Size
Setting.
Horizontal
Length
R1,R0,G1,G0,B1,B0. Background Colour.
These bits define the colour of the specified back-
ground, either background 1 or background 0 as
defined in Table 17.
GS2 GS1
S
Vertical Height
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
18h
36h
18h
54h
36h
54h
36h
72h
6 TDOT
12 TDOT
6 TDOT
Table 17. Background Register Colour
Setting.
18 TDOT
12 TDOT
18 TDOT
12 TDOT
24 TDOT
RX
0
GX
0
BX
0
Colour
Black
0
0
1
Blue
0
1
0
Green
Cyan
Note: TDOT= 2/f
OSC
0
1
1
HS5, HS0 . Horizontal Space . These bits deter-
mine the spacing between words if the Horizontal
SpaceEnable bit(HSE) locatedin the spacecharac-
ter is a one. The space betweenwords is thenequal
to the width of the space character plus the number
of tdotsspecifiedby the HorizontalSpace bits. The 6
bits can specify one of 64 spacing values ranging
from 2/fosc to 128/fosc. The formula is shown below
for the smallest size character(18h). If larger size
charactersare being displayed the spacingbetween
words will increase proportionately. Multiply the
value below by 2, 3 or 4 for character sizes of 36h,
54h and 72h respectively.
1
0
0
Red
1
0
1
Magenta
Yellow
White
1
1
0
1
1
1
Space between words (not including the space
character)=2/fosc(1+25(HS5)+24(HS4)+23(HS3)
+22(HS2)+ 21(HS1)+20(HS0))
50/82
ST63140,142,126,156
ON-SCREEN DISPLAY(Continued)
Figure 67. Character Bank Select Register
OSD Data RAM
The contentsof the data RAM can be accessed by
the ST631xxMCUs only whenthe global enable bit
(GE) in the Global Enable register is a zero.
CBSR
Character Bank Select Register
(EFh - No Page , Write Only)
The first character in every line is the format char-
acter. This character is not displayed. It defines the
size of the characters in the line and contains the
vertical space enable bit. This character also de-
fines thecolour, background anddisplay enable for
the first word in the line. Subsequent characters
are eitherspaces or one of the64 availablecharac-
ter types.
D7 D6 D5 D4 D3 D2 D1 D0
BS =Bank Select Bit
Unused
BK1,BK0. Background Enable.These bits deter-
The space character defines the colour, back-
ground, display enable and horizontal space en-
able for the following word. Since there are 5
display lines of 15 characters each, the display
RAM must contain 5 lines x (15 characters + 1 for-
mat character) or 80 locations. The RAM size is 80
locations x 7 bits. The data RAM map is shown
inTable 12.
mine if the specified background isenabled or not.
“0” -The following worddoesnot havea background.
“1” -There is a background around the following
word.
D7-D1. These bits are not used
BS. Bank Select. This bit select the character bank
to be used. The lower bank is selected with 0. The
value can be modified only when the OSD is OFF
(GE=0). No reset value.
51/82
ST63140,142,126,156
ON-SCREEN DISPLAY(Continued)
Table 12. OSD RAM Map
Column
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
A0
A1
A2
A3
Page
5
0
0
0
0
1
0
0
0
0
1
0
0
1
1
0
0
0
0
1
0
1
0
1
0
0
1
1
0
1
1
1
0
0
0
0
1
1
0
0
1
0
1
0
1
1
1
0
1
0
0
1
1
1
0
1
1
0
1
1
1
1
1
1
1
A5 A4
LINE
0
0
1
1
0
0
1
0
1
0
1
2
3
4
5
FT Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch
FT Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch
FT Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch
FT Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch
FT Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch
5
5
5
6
AVAILABLE SCREEN SPACE
Notes: FT. The format character required for each line. Characters in columns 1 thru 15 are displayed.
Ch. (Byte) Character (Index into OSD character generator) or space character
Emulator Remarks
plus anhidden leading formatcharacter). In page 6
(load 40h in register 0E8h), the 16 bytes of the fifth
There are a few differences between emulatorand
silicon. For noise reasons, the OSD oscillator pins
are not available: the internal oscillator cannot be
disabled and replaced by an external coil. In the
emulator, the Character Bank Select register can
be writtenalso with Global Enable bit set, while this
is notallowed in the device.
row (0..0Fh), and the
(10h..14h,17h).
6
control registers
3 - The video RAM is a dual port ram. That means
that it can be addressed either from the Core or
from the OSD circuitry itself. To reduce the com-
plexity of the circuitry, and thus its cost, some re-
strictions have been introduced in the use of the
OSD.
Application Notes
1 - The OSD character generator is composed of a
dual port video ram and some circuitry. It needs
two input signals VSYNC and HSYNC to syncron-
ize its dedicated oscillator to the TV picture. It gen-
erates 4 output signals, that can be used from the
TV set to generate the characters on the screen.
For instance, they can be used to feed the SCART
plug, providing an adequate buffer to drive the low
impedance (75 Ω) of the SCART inputs.
a. The Core can Only write to any of the 86 loca-
tions (either video RAM or control registers).
b. The Core can Only write to any of the leading
85 locations when the OSD oscillator is OFF.
Only the last location (control register 17h in
page 6) can be addressed at any time. This is
the Global Enable Register, which contains
only the GE bit. If it is set, the OSD is on, if it is
reset the OSD is off.
2 - The Core sees the OSD as a number of RAM
locations (80) plus a certain number of control reg-
isters (6). These 86 locations are mapped in two
pages of the dynamic data ram address range
(0h..3Fh).
In page 5 (load 20h in the register 0E8h), there are
64 bytes of RAM, the ones of the first 4 rows (16
bytes each row, 15 characters per row maximum,
4 - The timing of the on/off switching of the OSD
oscillator is the following:
a. GE bit is set. The OSD oscillator will start on
the next VSYNC signal.
b. GE bit is reset. The OSD oscillator will be im-
mediately switched off.
52/82
ST63140,142,126,156
ON-SCREEN DISPLAY(Continued)
To avoid a bad visual impression, it is important
that the GE bit is set before the end of the flyback
time when changingcharacters. This can be done
inside the VSYNC interrupt routine. The following
diagram can explain better:
The VSYNC pin may alternatively be sampled by
software in order to know the status; this can be
done by reading bit 4 of register E4h; this bit is in-
verted with respect to the VSYNC pin.
6 - An OSD end of line Bar is present in the
ST63P1xx piggyback and ST631xxROM, EPROM
and OTP devices when using the background
mode. If this bar is present with software running in
the piggybacksthen it is also present on the ROM
mask version. If the end of line bar is seen to be
eliminated by software in the piggyback, then it is
also be eliminated in the ROM mask version.
Figure 68. OSD Oscillator ON/OFF Timing
The bar appears at the end of the line in the back-
ground mode when the last character is a space
character, the first format character is defined with
S=0 (size 0)and the backround is not displayed
during the space. The bar is the colour of the back-
ground defined by the space character. To elimi-
nate the bar:
a. If two backgrounds are used then the bar
should be moved off the screen by using large
word spaces instead of character spaces. If
there are not enoughspaces before the end of
the line, then the location of the valid charac-
ters should be moved so they appear at the
end of the line (and hence no bar); positioning
can be compensated using the horizontal start
register.
Notes: A - Picture time:20 mS in PAL/SECAM.
B - VSYNC interrupt, if enabled.
C - Starting of OSD oscillator, if GE = 1.
D - Flyback time.
When modifying the picture display (i.e.: a bar
graph for an analog control), it is important that the
switching on of the GE bit is done before the the
end of the flyback time (D in Figure 68). If the GE
bit is set after the end of the flyback time then the
OSD will not start until the begining of the next
frame. This results in one frame being lost and will
result in a Flicker on the screen. One method to be
sure to avoid the flicker is to wait for the VSYNC in-
terrupt at the start of the flyback; once the VSYNC
interrupt is detected, then the GE bit can be set to
zero, the characters changed, and the GE set to
one. All this should occur before the end of the fly-
back time in order not to lose a frame. The correct
edge of the interrupt must be chosen.
b. If only one background is used, then the other
background should be transparent in order to
eliminate the bar.
7 - The OSD oscillator external network should
consist ofa capacitoron each of the OSDoscillator
pins to ground together with an inductance be-
tween pins. The user should select the two capaci-
tors to be the same value (15pF to 25pF each is
recommended). The inductance is chosen to give
the desired OSD oscillator frequency for the appli-
cation (typically 56µH).
53/82
ST63140,142,126,156
SOFTWARE DESCRIPTION
Program Counter Relative. The relative address-
ing modeis only usedinconditional branch instruc-
tions. The instruction is used to perform a test and,
if the condition is true, a branch with a span of -15
to +16 locations around the address of the relative
instruction. If the condition is not true, the instruc-
tion that follows the relative instruction is executed.
The relative addressing mode instruction is one-
byte long. The opcode is obtained in adding the
three most significant bitsthat characterizethekind
of the test, one bit that determines whether the
branch isa forward (when itis0)or backward(when
it is 1) branch and the four less significant bits that
give the span of the branch (0h to Fh) that must be
added or subtracted to the address of the relative
instruction to obtain the address of the branch.
The ST631xx software has been designed to fully
use the hardware in the most efficient way possible
while keeping byte usage to a minimum; in short to
provide byte efficient programming capability. The
ST631xx Core has the ability to set or clear any
register or RAM location bit of the Data space with
a single instruction. Furthermore, the program may
branch to a selected address depending on the
status of any bit of the Data space. The carry bit is
stored with the value of the bit when the SET or
RES instruction is processed.
Addressing Modes
The ST631xx Core has nine addressing modes
which are described in the following paragraphs.
The ST631xx Core uses three different address
spaces : Program space, Data space, and Stack
space. Program space contains the instructions
which are to be executed, plus the data for imme-
diate mode instructions. Data space contains the
Accumulator,the X,Y,V and W registers, peripheral
and Input/Outputregisters, the RAM locations and
Data ROM locations (for storage of tables and
constants). Stack space contains six 12-bit RAM
cells usedto stack thereturn addresses for subrou-
tines and interrupts.
Bit Direct. In the bit direct addressing mode, the
bit to be set or cleared is part of the opcode, and
the byte following the opcodepoints to the address
of the byte in which the specified bit must be set or
cleared. Thus, any bit in the 256 locations of Data
space memory can be set or cleared.
Bit Test & Branch. The bit test and branch ad-
dressing mode is a combination of direct address-
ing and relative addressing. The bit testand branch
instruction is three-byte long. The bit identification
and the testedcondition areincluded in theopcode
byte. The address of the byte to be tested follows
immediately the opcode inthe Program space. The
third byte is the jump displacement, which is in the
range of -126 to +129. This displacement can be
determined using a label, which isconverted by the
assembler.
Immediate. In the immediate addressing mode,
the operand of the instruction follows the opcode
location. As the operand is a ROM byte, the imme-
diate addressingmode is used to access constants
which do not change during program execution
(e.g., a constant used to initialize a loop counter).
Direct. In the direct addressing mode, the address
of the byte that is processed by the instruction is
stored inthe location thatfollows theopcode. Direct
addressing allows the user to directly address the
256 bytes in Data Space memory with a single
two-byte instruction.
Indirect. In the indirect addressing mode, the byte
processed by the register-indirect instruction is at
the address pointed by the content of one of the
indirect registers, X or Y (80h,81h). The indirect
register is selected by the bit 4 of the opcode. A
register indirect instruction is one byte long.
Short Direct. The Core can address the four RAM
registers X,Y,V,W (locations 80h, 81h, 82h, 83h) in
the short-direct addressing mode. In this case, the
instruction is only one byte and the selection of the
location to be processed is contained in the op-
code. Short direct addressing is a subset of the
direct addressing mode. (Note that 80h and 81h
are also indirect registers).
Inherent. In the inherent addressing mode, all the
information necessary to execute the instruction is
contained in the opcode. These instructions are
one byte long.
Extended. In the extended addressing mode, the
12-bit address needed to define the instruction is
obtained by concatenating the four less significant
bits of the opcode with the byte following the op-
code. The instructions (JP, CALL) that use the
extended addressing mode are able to branch to
any address of the 4K bytes Program space.
An extended addressing mode instruction is two-
byte long.
54/82
ST63140,142,126,156
SOFTWARE DESCRIPTION (Continued)
Instruction Set
Load & Store. These instructions use one,two or
three bytes in relation with the addressing mode.
One operand is the Accumulator for LOAD and the
other operand is obtained fromdata memory using
one of the addressing modes.
The ST631xx Core has a set of 40 basic instruc-
tions. When these instructions are combined with
nine addressing modes, 244 usable opcodes can
be obtained. They can be divided into six different
types:load/store, arithmetic/logic, conditional
branch, control instructions, jump/call, bit manipu-
lation. The following paragraphs describe the dif-
ferent types.
For Load Immediate oneoperand can be any of the
256 data space bytes while the other is always
immediate data. See Table 13.
All the instructions within a given type are pre-
sented in individual tables.
Table 13. Load & Store Instructions
Flags
Instruction
Addressing Mode
Bytes
Cycles
Z
C
LD A, X
LD A, Y
LD A, V
LD A, W
LD X, A
LD Y, A
Short Direct
Short Direct
Short Direct
Short Direct
Short Direct
Short Direct
Short Direct
Short Direct
Direct
1
1
1
1
1
1
1
1
4
4
4
4
4
4
4
4
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
*
*
*
*
*
*
*
*
*
*
*
*
*
*
LD V, A
LD W, A
LD A, rr
LD rr, A
LD A, (X)
LD A, (Y)
LD (X), A
LD (Y), A
2
2
4
4
4
4
4
4
Direct
Indirect
1
1
1
1
Indirect
Indirect
Indirect
LDI A, #N
LDI rr, #N
Immediate
Immediate
2
3
4
∆
*
4
*
*
Notes:
X,Y.Indirect Register Pointers, V & W Short Direct Registers
# . Immediate data (stored in ROM memory)
rr. Data space register
∆ . Affected
* . Not Affected
55/82
ST63140,142,126,156
SOFTWARE DESCRIPTION (Continued)
content or an immediate value in relation with the
addressing mode. In CLR, DEC, INC instructions
the operand can be any of the 256 data space
addresses. In COM, RLC, SLA the operand is
always the accumulator. See Table 14.
Arithmetic and Logic. These instructions are
used to perform the arithmetic calculations and
logic operations. In AND, ADD, CP, SUB instruc-
tions one operandis always the accumulatorwhile
the other can be either a data space memory
Table 14. Arithmetic & Logic Instructions
Flags
Instruction
Addressing Mode
Bytes
Cycles
Z
C
ADD A, (X)
ADD A, (Y)
ADD A, rr
Indirect
Indirect
Direct
1
1
4
4
∆
∆
∆
∆
∆
∆
2
4
ADDI A, #N
Immediate
2
4
∆
∆
AND A, (X)
AND A, (Y)
AND A, rr
Indirect
Indirect
Direct
1
1
4
4
∆
∆
∆
*
*
*
2
3
4
4
ANDI A, #N
Immediate
2
2
4
4
∆
∆
*
CLR A
CLR rr
Short Direct
Direct
∆
*
*
COM A
Inherent
1
4
∆
∆
CP A, (X)
CP A, (Y)
CP A, rr
Indirect
Indirect
Direct
1
1
4
4
∆
∆
∆
∆
∆
∆
2
4
CPI A, #N
Immediate
2
4
∆
∆
DEC X
DEC Y
DEC V
DEC W
DEC A
DEC rr
DEC (X)
DEC (Y)
Short Direct
Short Direct
Short Direct
Short Direct
Direct
Direct
Indirect
Indirect
1
1
1
1
4
4
4
4
∆
∆
∆
∆
∆
∆
∆
∆
*
*
*
*
*
*
*
*
2
2
4
4
1
1
4
4
INC X
INC Y
INC V
INC W
INC A
INC rr
INC (X)
INC (Y)
Short Direct
Short Direct
Short Direct
Short Direct
Direct
Direct
Indirect
Indirect
1
1
1
1
4
4
4
4
∆
∆
∆
∆
∆
∆
∆
∆
*
*
*
*
*
*
*
*
2
2
4
4
1
1
4
4
RLC A
SLA A
Inherent
Inherent
1
4
∆
∆
∆
∆
2
4
SUB A, (X)
SUB A, (Y)
SUB A, rr
Indirect
Indirect
Direct
1
1
4
4
∆
∆
∆
∆
∆
∆
2
4
SUBI A, #N
Immediate
2
4
∆
∆
Notes:
X,Y.Indirect Register Pointers, V & W Short Direct Registers
# . Immediate data (stored in ROM memory)
rr. Data space register
∆. Affected
* . Not Affected
56/82
ST63140,142,126,156
SOFTWARE DESCRIPTION (Continued)
Conditional Branch. The branch instructions
achieve a branch inthe program whenthe selected
condition is met. See Table 15.
Control Instructions. The control instructions
control the MCUoperations during programexecu-
tion. See Table 17.
Bit Manipulation Instructions. These instruc-
tions can handle any bitin data spacememory. One
group either sets or clears. The other group (see
Conditional Branch) performs the bit test branch
operations. See Table 16.
Jump and Call. These two instructions are used to
perform long (12-bit) jumps or subroutines call
inside thewhole program space. Refer to Table 18.
Table 15. Conditional Branch Instructions
Flags
Instruction
Branch If
Bytes
Cycles
Z
C
JRC e
JRNC e
JRZ e
JRNZ e
JRR b, rr, ee
JRS b, rr, ee
C = 1
C = 0
Z = 1
Z = 0
Bit = 0
Bit = 1
1
1
1
1
3
3
2
2
2
2
5
5
*
*
*
*
*
*
*
*
*
∆
∆
*
Notes:
b. 3-bit address
e. 5 bit signed displacementin the range -15 to +16
ee. 8 bit signed displacement in the range -126 to +129
rr. Data space register
∆
.
Affected
* . Not Affected
Table 16. Bit Manipulation Instructions
Flags
Addressing
Instruction
Mode
Bytes
Cycles
Z
C
SET b,rr
RES b,rr
Bit Direct
Bit Direct
2
2
4
4
*
*
*
*
Notes:
b. 3-bit address;
* . Not Affected
rr. Data space register;
Table 17. Control Instructions
Flags
Addressing
Instruction
Mode
Bytes
Cycles
Z
C
NOP
RET
RETI
STOP (1)
WAIT
Inherent
Inherent
Inherent
Inherent
Inherent
1
1
1
1
1
2
2
2
2
2
*
*
∆
*
*
*
∆
*
*
*
Notes:
1. This instruction is deactivated and a WAITis automatically executed instead of a STOP if the hardware activated
watchdog function is selected.
∆ . Affected
* . Not Affected
Table 18. Jump & Call Instructions
Flags
Addressing
Mode
Instruction
Bytes
Cycles
Z
C
CALL abc
JP abc
Extended
Extended
2
2
4
4
*
*
*
*
Notes:
abc.12-bit address;
* . Not Affected
57/82
ST63140,142,126,156
SOFTWARE DESCRIPTION (Continued)
Opcode Map Summary.Thefollowingtable containsan opcode map forthe instructionsused on the MCU.
Low
Low
0
0000
1
0001
2
3
0011
4
5
6
0110
7
8
9
1001
A
1010
B
1011
C
1100
D
1101
E
1110
F
1111
0010
0100
0101
0111 1000
Hi
Hi
2 JRNZ 4 CALL 2 JRNC 5 JRR
abc b0,rr,ee
ext pcr 3 bt
2 JRNZ 4 CALL 2 JRNC 5 JRS
abc b0,rr,ee
ext pcr 3 bt
2 JRNZ 4 CALL 2 JRNC 5 JRR
abc b4,rr,ee
ext pcr 3 bt
2 JRNZ 4 CALL 2 JRNC 5 JRS
abc b4,rr,ee
ext pcr 3 bt
2 JRNZ 4 CALL 2 JRNC 5 JRR
abc b2,rr,ee
ext pcr 3 bt
2 JRNZ 4 CALL 2 JRNC 5 JRS
abc b2,rr,ee
ext pcr 3 bt
2 JRNZ 4 CALL 2 JRNC 5 JRR
abc b6,rr,ee
ext pcr 3 bt
2 JRNZ 4 CALL 2 JRNC 5 JRS
abc b6,rr,ee
ext pcr 3 bt
2 JRNZ 4 CALL 2 JRNC 5 JRR
abc b1,rr,ee
ext pcr 3 bt
2 JRNZ 4 CALL 2 JRNC 5 JRS
abc b1,rr,ee
ext pcr 3 bt
2 JRNZ 4 CALL 2 JRNC 5 JRR
abc b5,rr,ee
ext pcr 3 bt
2 JRNZ 4 CALL 2 JRNC 5 JRS
abc b5,rr,ee
ext pcr 3 bt
2 JRNZ 4 CALL 2 JRNC 5 JRR
abc b3,rr,ee
ext pcr 3 bt
2 JRNZ 4 CALL 2 JRNC 5 JRS
abc b3,rr,ee
ext pcr 3 bt
2 JRNZ 4 CALL 2 JRNC 5 JRR
abc b7,rr,ee
ext pcr 3 bt
2 JRNZ 4 CALL 2 JRNC 5 JRS
abc b7,rr,ee
ext pcr 3 bt
2
JRZ
e
2
JRC
4
LD 2 JRNZ 4
JP 2 JRNC
abc
ext
4
RES
b0,rr
b.d
2
JRZ
e
4
LDI
rr,nn
imm
2
JRC
4
LD
a,(y)
ind
0
0
e
e
#
e
a,(x)
ind 1
LDI 2 JRNZ 4
a,nn
e
e
e
0000
0000
1
pcr 2
1
1
2
pcr
JRZ
e
1
2
prc 1
pcr
2
1
pcr 2
1
2
pcr
JRZ
e
3
4
1
2
pcr 1
4
INC
x
JRC
4
JP 2 JRNC
abc
ext
4
SET
b0,rr
b.d
DEC
x
JRC
4
LD
1
1
0001
e
e
e
e
e
e
a,rr
dir
0001
1
pcr 2
1
1
2
pcr 1
JRZ
sd
1
2
prc 2 imm
1
pcr
2
1
pcr 2
1
2
pcr
JRZ
e
1
4
sd
1
2
pcr 2
JRC
4
CP 2 JRNZ 4
a,(x)
ind 1
CPI 2 JRNZ 4
a,nn
JP 2 JRNC
abc
ext
4
RES
b4,rr
b.d
COM
a
JRC
4
CP
2
2
0010
e
e
e
#
e
e
e
e
a,(y)
pcr 1 ind
0010
1
pcr 2
1
1
2
pcr
1
prc 1
pcr
2
1
pcr 2
1
2
pcr
JRZ
e
1
4
inh
LD
x,a
sd
1
2
JRZ
4
LD 2 JRC
a,x
sd
4
JP 2 JRNC
abc
ext
JP 2 JRNC
abc
ext
4
SET
b4,rr
JRC
4
CP
3
0011
3
0011
e
e
e
e
e
e
e
a,rr
dir
1
pcr 2
1
1
2
pcr 1
JRZ
1
2
prc 2 imm
1
pcr
2
1
pcr 2 b.d. 1
pcr
JRZ
e
1
2
1
2
pcr 2
JRC
4
ADD 2 JRNZ 4
a,(x)
ind 1
JRC 4 ADDI 2 JRNZ 4
4
RES
b2,rr
2
RETI
JRC
4
ADD
a,(y)
ind
4
4
0100
e
e
e
#
e
e
e
e
0100
1
pcr 2
1
1
2
pcr
1
2
prc 1
pcr
2
1
pcr 2
b.d
1
2
pcr
JRZ
e
1
4
inh
DEC
y
1
2
pcr 1
JRZ
4
INC
JP 2 JRNC
abc
ext
4
SET
JRC
4
ADD
a,rr
dir
5
0101
5
0101
e
e
e
y
e
a,nn
e
e
b2,rr
e
1
pcr 2
1
1
2
pcr 1
JRZ
sd
1
2
prc 2 imm
1
pcr
2
1
pcr 2
b.d
1
2
pcr
1
sd
1
2
pcr 2
JRC
4
INC 2 JRNZ 4
(x)
ind 1
JP 2 JRNC
abc
ext
4
RES
JRZ 2 STOP
JRC
4
INC
(y)
6
0110
6
0110
e
e
e
#
e
e
e
b6,rr
e
e
1
pcr 2
1
1
2
pcr
1
2
prc 1
JRC
pcr
2
1
pcr 2
b.d
1
2
pcr
JRZ
e
1
4
inh
1
2
pcr 1
ind
JRZ
4
LD
2 JRNZ 4
JP 2 JRNC
abc
ext
4
SET
LD
JRC
4
INC
rr
7
7
e
e
e
a,y
e
#
e
e
b6,rr
y,a
e
0111
0111
1
pcr 2
1
1
2
pcr 1
JRZ
sd
1
2
prc
1
pcr
2
1
pcr 2
b.d
1
2
pcr
JRZ
e
1
sd
1
2
pcr 2
dir
JRC
4
LD 2 JRNZ 4
JP 2 JRNC
abc
ext
4
RES
JRC
e
4
LD
8
1000
8
1000
e
e
e
#
e
(x),a
#
e
e
b1,rr
#
(y),a
ind
1
pcr 2
1
1
2
pcr
1
2
prc 1
JRC
ind 1
pcr
2
1
pcr 2
b.d
1
2
pcr
JRZ
e
1
2
pcr
JRC
e
1
4
JRZ
4
INC
2 JRNZ 4
JP 2 JRNC
abc
ext
4
SET
4
DEC
v
LD
9
1001
9
1001
e
e
e
v
e
e
e
b1,rr
rr,a
dir
1
pcr 2
1
1
2
pcr 1
JRZ
sd
1
2
prc
1
pcr
AND 2 JRNZ 4
a,(x)
ind 1
JRC 4 ANDI 2 JRNZ 4
2
1
pcr 2
b.d
1
2
pcr
JRZ
e
1
4
sd
1
2
pcr 2
JRC
4
JP 2 JRNC
abc
ext
4
RES
RLC
a
JRC
4
AND
a,(y)
ind
A
1010
A
1010
e
e
e
#
e
e
e
b5,rr
e
1
pcr 2
1
1
2
pcr
1
2
prc 1
pcr
2
1
pcr 2
b.d
1
2
pcr
JRZ
e
1
4
inh
LD
1
2
pcr 1
JRZ
4
LD
JP 2 JRNC
abc
ext
4
SET
JRC
4
AND
a,rr
dir
B
1011
B
1011
e
e
e
a,v
e
a,nn
e
e
b5,rr
v,a
e
1
pcr 2
1
1
2
pcr 1
JRZ
sd
1
2
prc 2 imm 1
pcr
2
1
pcr 2
b.d
1
2
pcr
JRZ
e
1
2
sd
1
2
pcr 2
JRC
4
SUB 2 JRNZ 4
a,(x)
ind 1
SUBI 2 JRNZ 4
a,nn
prc 2 imm 1
JP 2 JRNC
abc
ext
4
RES
RET
JRC
4
SUB
a,(y)
ind
C
1100
C
1100
e
e
e
#
e
e
e
b3,rr
b.d
e
1
pcr 2
1
1
2
pcr
1
2
prc 1
JRC
pcr
2
1
pcr 2
1
2
pcr
JRZ
e
1
4
inh
DEC
w
1
2
pcr 1
JRZ
4
INC
4
JP 2 JRNC 4 SET
abc b3,rr
ext b.d
JP 2 JRNC 4 RES
abc b7,rr
ext b.d
JP 2 JRNC 4 SET
abc b7,rr
ext b.d
JRC
4
SUB
a,rr
dir
D
1101
D
1101
e
e
e
w
e
e
e
e
1
pcr 2
1
1
2
pcr 1
JRZ
sd
1
2
pcr
2
1
pcr 2
1
2
pcr
JRZ
e
1
2
sd
1
pcr 2
JRC
4
DEC 2 JRNZ 4
WAIT 2 JRC
4
DEC
(y)
E
1110
E
1110
e
e
e
#
e
(x)
e
e
e
1
pcr 2
1
1
2
pcr
1
2
prc 1
JRC
ind 1
pcr
2
1
pcr 2
1
2
pcr
JRZ
e
1
4
inh
1
2
pcr 1
ind
JRZ
4
LD
2 JRNZ 4
LD
JRC
4
DEC
rr
F
1111
F
1111
e
e
e
a,w
sd
e
#
e
e
w,a
sd
e
1
pcr 2
1
1
pcr 1
1
prc
1
pcr
2
1
pcr 2
1
pcr
1
1
pcr 2
dir
Abbreviations for Addressing Modes:
Legend:
2
JRC
e
Mnemonic
Cycles
dir
sd
Direct
Short Direct
# Indicates Illegal Instructions
e 5 BitDisplacement
b 3 BitAddress
rr1byte dataspace address
nn 1 byte immediate data
abc 12 bit address
Operand
Bytes
1
pcr
imm Immediate
Addressing Mode
inh
ext
b.d
bt
Inherent
Extended
Bit Direct
Bit Test
ee 8 bit Displacement
pcr
Program Counter Relative
ind
Indirect
58/82
ST63140,142,126,156
ABSOLUTE MAXIMUM RATINGS
Power Considerations. The average chip-junc-
tion temperature, Tj, in Celsius can be obtained
from :
This product contains devices to protect the inputs
against damage due to high static voltages, how-
ever itis advisedto take normal precaution to avoid
application of any voltage higher than maximum
rated voltages.
Tj =
TA + PD x RthJA
Where :TA =
Ambient Temperature.
RthJA = Package thermal resistance
(junction-to ambient).
For properoperation it is recommended that V and
I
VO must be higher than VSS and smaller than VDD
.
PD =
Pint + Pport.
Reliability is enhanced if unused inputs are con-
nected to an appropriatedlogic voltage level (VDD
or VSS).
Pint = IDD x VDD (chip internal power).
Pport = Port power dissipation
(determinated by the user).
Symbol
VDD
VI
Parameter
Value
Unit
Supply Voltage
-0.3 to 7.0
V
V
Input Voltage (AFC IN)
- 0.3 to +13
V
V
SS
VI
Input Voltage (Other Inputs)
V
SS - 0.3 to VDD +0.3
VO
Output Voltage (PA4-PA7, PC4-PC7, DA0-DA5)
Output Voltage (Other Outputs)
VSS - 0.3 to +13
V
VO
V
SS - 0.3 to VDD +0.3
V
IO
Current Drain per Pin Excluding VDD, VSS, PA6, PA7
Current Drain per Pin (PA6, PA7)
± 10
± 50
mA
mA
mA
IO
IVDD
IVSS
Tj
Total Current into VDD (source)
50
Total Current out of VSS (sink)
150
mA
Junction Temperature
Storage Temperature
150
-60 to 150
°C
TSTG
°C
Note : Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device . This is a stress rating only
and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
THERMAL CHARACTERISTIC
Value
Symbol
Parameter
Test Conditions
Unit
Min.
Typ.
Max.
PDIP40
PDIP28
38
55
RthJA
Thermal Resistance
°C/W
RECOMMENDED OPERATING CONDITIONS
Value
Typ.
°C
Symbol
Parameter
Test Conditions
Unit
Min.
Max.
TA
Operating Temperature
Operating Supply Voltage
0
70
VDD
4.5
5.0
6.0
V
Oscillator Frequency
RUN & WAIT Modes
fOSC
8
8.1
8.0
MHz
MHz
On-screen Display Oscillator
Frequency
fOSDOSC
59/82
ST63140,142,126,156
EEPROM INFORMATION
The ST631xx EEPROM single poly process has been specially developed to achieve 300.000
Write/Erase cycles and a 10 years data retention.
DC ELECTRICAL CHARACTERISTICS
(TA = 0 to +70°C unless otherwise specified)
Value
Symbol
Parameter
Test Conditions
Unit
Min.
Typ.
Max.
VIL
VIH
Input Low Level Voltage
Input High Level Voltage
All I/O Pins, KBY0-2
All I/O Pins, KBY0-2
0.3xV
V
V
DD
0.75xVDD
VHYS
All I/O Pins, KBY0-2
VDD = 5V
Hysteresis Voltage(1)
1.0
V
Port B/C, DA0-3,
BSW0-3, OUT1,
VS, OSD Outputs,
VDD = 4.5V
VOL
Low Level Output Voltage
IOL = 1.6mA
IOL = 5.0mA
0.4
1.0
V
V
Port A
VDD = 4.5V
IOL= 3.2mA
IOL= 30mA
VOL
Low Level Output Voltage
0.4
1.0
V
V
OSDOSCout, OSCout
VDD = 4.5V
IOL= 0.1mA
Port B/C(2), VS
VDD = 4.5V
VOL
Low Level Output Voltage
High Level Output Voltage
High Level Output Voltage
V
V
0.4
4.1
VOH
IOH = – 1.6mA
OSDOSCout, OSCout,
VDD = 4.5V
VOH
V
IOL= – 0.1mA
4.1
Input Pull Up Current
Input Mode with Pull-up
Port B/C, KBY0-2
VIN= VSS
IPU
– 100
– 50
– 25
mA
µA
(2)
OSCin
VIN= VSS
VIN= VDD
IIL
IIH
– 10
0.1
– 1
1
– 0.1
10
Input Leakage Current
All I/O Input Mode
no Pull-up
OSDOSCin
IIL
IIH
Input Leakage Current
Input Leakage Current
Input Leakage Current
– 10
– 50
10
µA
µA
µA
VIN= VDD or VSS
IIL
IIH
Reset Pin with Pull-up
VIN= VSS
– 30
– 10
AFC Pin
VIH= VDD
VIL= VSS
VIH= 12.0V
IIL
IIH
1
– 1
40
Port A, DA0-3, BSW0-3
OUT1, OSDout
VOH = VDD
IOH
Output Leakage Current
10
40
µA
µA
Port A, DA0-3, BSW0-3
OUT1
VOH = 12V
Output Leakage Current High
Voltage
IOH
60/82
ST63140,142,126,156
DC ELECTRICAL CHARACTERISTICS (Continued)
Value
Unit
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
fOSC= 8MHz, ILoad= 0mA
VDD= 6.0V
IDD
IDD
Supply Current RUN Mode
Supply Current WAIT Mode
Reset Trigger Level ON
Reset Trigger Level OFF
6
16
mA
mA
V
f
OSC= 8MHz, ILoad= 0mA
3
10
VDD= 6V
VON
VOFF
VTA
RESET Pin
0.3xV
0.8xVDD
DD
RESET Pin
V
Input Level Absolute
Tolerance
A/D AFC Pin
VDD = 5V
±200
±100
mV
A/D AFC Pin
Relative to other levels
VDD = 5V
VTR
Input Level Relatice Tolerance
mV
Notes:
1. Not 100% Tested
2. Input pull-up option only
61/82
ST63140,142,126,156
AC ELECTRICAL CHARACTERISTICS
(TA = 0 to +70°C, fOSC=8MHz, VDD=4.5 to 6.0V unless otherwise specified )
Value
Typ.
Symbol
Parameter
Test Conditions
Unit
Min.
Max.
tWRES
tOHL
Minimum Pulse Width
RESET Pin
125
ns
PA6, PA7
VDD = 5V, CL = 1000pF (2)
High to Low Transition Time
100
20
ns
ns
DA0-DA5, PB0-PB6, OSD
Outputs, PC0-PC7,
VDD = 5V, CL = 100pF
tOHL
High to Low Transition Time
Low to High Transition Time
PB0-PB6, PA0-PA3, OSD
Outputs, PC0-PC3
20
tOLH
VDD = 5V, CL = 100pF
ns
Data HOLD Time
175
ns
tOH
SPI after clock goes low
I2CBUS/S-BUS Only
D/A Converter Repetition
Frequency(1)
f DA
f SIO
tWEE
31.25
kHz
kHz
SIO Baud Rate(1)
62.50
5
EEPROM Write Time
TA = 25°C One Byte
10
ms
cycles
years
EEPROM WRITE/ERASE
Cycles
Q
A LOT
> 1
million
Endurance
300.000
Acceptance Criteria
Retention
CIN
EEPROM Data Retention (4)
Input Capacitance (3)
TA = 25°C
10
10
All Inputs Pins
All outputs Pins
pF
COUT
Output Capacitance (3)
10
pF
COSCin,
COSCout
Oscillator Pins Internal
Capacitance(3)
5
pF
pF
COSDin,
COSDout
OSD Oscillator External
Capacitance
Recommended
15
25
Notes:
1. A clock other than 8 MHz will affect the frequency response of those peripherals (D/A, 62.5kHz and SPI) whose clock is
derived from the system clock.
2. The rise and fall times of PORT A have been reduced in order to avoid current spikes while maintaining a high drive capability
3. Not 100% Tested
4. Based on extrapolated data
62/82
ST63140,142,126,156
PACKAGE MECHANICAL DATA
Figure 69. ST631xx 40 Pin Plastic Dual-In-line Package
Dim.
mm
inches
Typ Max
0.189
Min
2.2
Typ Max
Min
A
A1
B
4.8 0.086
1.77 0.010
0.58 0.015
1.52 0.055
0.30 0.008
52.22 1.980
0.51
0.38
0.97
0.20
50.30
–
0.069
0.023
B1
C
0.065
0.009
D
20.560
D1
E
–
15.2
12.9
–
–
–
–
0.600
0.508
–
–
E1
K1
K2
L
–
–
–
–
–
–
–
–
–
–
3.18
4.44 1.25
0.174
e1
2.54
0.10
Number of Pins
N
40
Figure 70. ST631xx 28-Pin Dual-In-line Package
Dim.
mm
inches
Min
2.2
Typ Max
Min
Typ Max
0.189
A
A1
B
4.8 0.086
1.77 0.010
0.58 0.015
1.52 0.055
0.30 0.008
36.22 1.400
0.51
0.38
0.97
0.20
35.06
–
0.069
0.023
B1
C
0.065
0.009
D
1.425
D1
E
–
15.2
12.9
–
–
–
–
0.600
0.508
–
–
E1
K1
K2
L
–
–
–
–
–
–
–
–
–
–
3.18
4.44 1.25
0.174
e1
2.54
0.10
Number of Pins
N
28
63/82
ST63140,142,126,156
ORDERING INFORMATION
The following chapter deals with the procedure for
transfer the Program/Data ROM codes to SGS-
THOMSON.
– one fileinINTELINTELLEC8/MDS FORMAT
for the EEPROM initial content
(this file is optional)
Communication of the ROM Codes. To commu-
nicate the contents of Program /Data ROM memo-
ries to SGS-THOMSON, the customer has to send
a 5” Diskette with:
– a filled Option List form as described in the
OPTION LIST paragraph.
The program ROM should respect the ROM Mem-
ory Map as in Table 19.
– one filein INTELINTELLEC 8/MDS FORMAT
for the PROGRAM Memory
The ROM code must be generated with ST6 as-
sembler. Before programming the EPROM, the
buffer of the EPROM programmer must be filled
with FFh.
– one filein INTELINTELLEC 8/MDS FORMAT
for the ODD and EVEN ODD OSD Characters
Table 19. ROM Memory Map
Device
ROM Page
EPROM
Address
Description
(1)
Address
0000h-007Fh
0080h-07FFh
0000h-007Fh
0080h-07FFh
Reserved
User ROM
Page 0
0800h-0F9Fh
0FA0h-0FEFh
0FF0h-0FF7h
0FF8h-0FFBh
0FFCh-0FFDh
0FFEh-0FFFh
0800h-0F9Fh
0FA0h-0FEFh
0FF0h-0FF7h
0FF8h-0FFBh
0FFCh-0FFDh
0FFEh-0FFFh
User ROM
Reserved
Interrupt Vectors
Reserved
NMI Vector
Reset Vector
Page 1
“STATIC”
0000h-000Fh
0010h-07FFh
1000h-100Fh
1010h-17FFh
Reserved
User ROM
Page 2
Page 3
0000h-000Fh
0010h-07FFh
1800h-180Fh
1810h-1FFFh
Reserved
user ROM
Note 1. EPROM addresses are related to the use of ST63E1xx EPROM emulation devices.
64/82
ST63140,142,126,156
ORDERING INFORMATION (Continued)
Figure 71. OSD Test Character
Customer EEPROM Initial Contents:
Format
a. The content should be written into an INTEL
INTELLEC format file.
b. Undefined or don’t care bytes should have the
content FFh.
OSD Test Character. IN ORDER TO ALLOWTHE
TESTING OF THE ON-CHIP OSD MACROCELL
THE FOLLOWINGCHARACTER MUST BE PRO-
VIDED AT THE FIXED 3Fh (63) POSITION OF
THE SECOND OSD BANK.
Listing Generation & Verification. When SGS-
THOMSON receives the files, a computer listing is
generated from them. This listing refers extractly to
the mask that will beused to produce the microcon-
troller. Then the listing is returned to the customer
that must thoroughly check, complete, sign and
return itto SGS-THOMSON. The signed list consti-
tutes a part of the contractual agreement for the
creation of the customer mask. SGS-THOMSON
sales organization will provide detailed information
on contractual points.
ORDERING INFORMATION TABLE
Sales Type
ROM/EEPROM
Temperature Range
0 to + 70 ° C
PDIP28
Package
ST63140B1/XX
ST63142B1/XX
ST63126B1/XX
ST63156B1/XX
PDIP28
8K (EPROM)
0 to + 70 ° C
/
128 Bytes
0 to + 70 ° C
PDIP40
0 to + 70 ° C
PDIP40
Note. /XX Is the ROM Code idebtifier that is allocated by SGS-THOMSONafter receipt of all required options and the related ROM file
65/82
ST63140,142,126,156
ST631xx MICROCONTROLLER OPTION LIST
Customer:
Address:
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact:
Phone No:
Reference:
Device
[ ] ST63140
[ ] ST63142
[ ] ST63126
[ ] ST63156
Temperature Range
0 to 70°C
For marking one line with 12 charactersmaximum is possible
Special Marking
[ ] No
[ ] Yes Line1 “ _ _ _ _ _ _ _ _ _ _ _ _ ”
Letters, digits, ’ . ’, ’ - ’, ’ / ’ and spaces only
the default marking is equivalent to the sales type only (part number).
OSD POLARITY OPTIONS (Put a cross on selected item) :
POSITIVE
NEGATIVE
VSYNC,HSYNC
R,G,B
[ ]
[ ]
[ ]
[ ]
[ ]
[ ]
BLANK
CHECK LIST:
YES
[ ]
NO
[ ]
ROM CODE
OSD Code: ODD & EVEN
EEPROM Code (if Desired)
[ ]
[ ]
[ ]
[ ]
Signature ...................................
Date ...........................................
66/82
ST63E140/T140, E142/T142
ST63E126/T126, E156/T156
8-BIT EPROM HCMOS MCUs FOR
TV FREQUENCY & VOLTAGE SYNTHESIS WITH OSD
PRELIMINARY DATA
4.5 to 6V operating Range
8MHz Maximum Clock Frequency
User Program EPROM: 7948 bytes
Reserved Test EPROM:
244 bytes
Data EPROM:
Data RAM:
user selectable size
256 bytes
Data EEPROM:
40-Pin Dual in Line Package for the
ST63x126, x156
128 bytes
1
28-Pin Dual in Line Package for the
ST63x140, x142
Up to 18 software programmable general
purpose Inputs/Outputs, including 8 direct LED
driving Outputs
28
3 Inputs for keyboard scan (KBY0-2)
Up to 4 high voltage outputs (BSW0-3)
1
Two Timers each including an 8-bit counter with
a 7-bit programmable prescaler
Digital Watchdog Function
Serial Peripheral Interface (SPI) supporting
S-BUS/ I2C BUS and standard serial protocols
Up to Four 6-bit PWM D/A Converters
62.5kHz Output pin
14 bit counter for voltage synthesis tuning
(ST63156, ST63140)
AFC A/D converter with 0.5V resolution
Four interrupt vectors (IRIN/NMI, Timer 1 & 2,
VSYNC.)
1
On-chip clock oscillator
5 Lines by 15 Characters On-Screen Display
Generator with 128 Characters (2 banks)
These EPROM and OTP versions are fully pin to
pin compatible with their respective ROM versions
The development tool of the ST631xx
microcontrollers consists of the ST63TVS-EMU
emulation and development system to be
connected via a standard RS232 serial line to an
MS-DOS Personal Computer.
1
EPROM programming board ST63E1XX-EPB
(Ordering Information at the end of the datasheet)
October 1993
67/82
This is Preliminary information from SGS-THOMSON. Details are subject tochange withoutnotice.
ST63E140,E142,E126,E156, T140,T142,T126,T156
Figure 1. ST63E126/T126, E156/T156 Pin Configuration
VDD
VDD
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
BSW0
BSW
BSW2
BSW3
KBY0
1
2
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
1
2
BSW0
BSW1
BSW2
BSW3
KBY0
DA3
DA2
DA1
DA0
OUT1
IRIN
VS
DA3
DA2
3
4
3
4
DA1
5
5
6
DA0
6
KBY
1
OUT1
IRIN
KBY 1
KBY2
7
KBY2
OSDOSCout
OSDOSCin
(SEN) PB7
7
8
8
9
PC7 (B)
PC6 (G)
PC5 (R)
PC3 (BLANK)
PC2 (ON/OFF)
PC1
OSDOSCout
OSDOSCin
(SEN) PB7
(SDA) PB6
(SCL) PB5
(HSYNC) PB3
(VSYNC) PB2
AFC
9
PC7 (B)
PC6 (G)
PC5 (R)
PC3 (BLANK)
PC2 (ON/OFF)
PC1
10
11
12
10
11
12
13
14
15
(SDA) PB6
(SCL) PB5
(HSYNC) PB3
(VSYNC) PB2
AFC
13
14
15
PC0
OSCout
OSCin
OSCout
OSCin
RESET
PA1
TEST (1)
PA6
TEST (1)
PA6
16
17
18
19
20
16
17
18
19
20
RESET
PA1
PA2
PA5
PA5
PA4
VSS
PA2
PA4
VSS
PA3
PA3
VA00288
VA00282
ST63E126/T126
ST63E156/T156
Note 1. This pin is also the V
input for EPROM based devices
PP
Figure 2. ST63E140/T140, E142/T142 Pin Configuration
BSW0
BSW1
1
28
VDD
BSW0
BSW1
1
28
27
26
25
24
23
22
VDD
2
DA0
2
27
26
25
24
23
22
DA0
BSW2
3
OUT1
IRIN
BSW2
3
OUT1
VS
KBY0
4
KBY0
4
KBY1
5
PC6 (G)
PC4
KBY1
5
PC6 (G)
PC5 (R)
PC4
KBY2
6
KBY2
6
OSDOSCout
OSDOSCin
PB3 (HSYNC)
PB2 (VSYNC)
AFC
7
OSDOSCout
OSDOSCin
PB3 (HSYNC)
PB2 (VSYNC)
AFC
7
PC3 (BLANK)
8
21 PC2
8
21 PC2
9
20
19
18
17
16
15
OSCout
9
20
19
18
17
16
15
OSCout
10
11
12
13
14
OSCin
RESET
PA0
10
11
12
13
14
OSCin
RESET
PA0
TEST (1)
PA4
TEST (1)
PA1
PA4
VSS
PA1
PA2
VSS
PA2
VR001390
VR001389
ST63E142/T142
ST63E140/T140
Note 1. This pin is also the V
input for EPROM based devices
PP
68/82
ST63E140,E142,E126,E156, T140,T142,T126,T156
GENERAL DESCRIPTION
The ST63E140/T140, E142/T142, E126/T126,
E156/T156 microcontrollers are members of the 8-
bit HCMOS ST631xx family, a series of devices
specially oriented to TV applications. Different pe-
ripheral configurations are available to give the
maximum application and cost flexibility. All
ST631xx members are based on a building block
approach: a common coreis surrounded by a com-
bination of on-chip peripherals (macrocells) avail-
able froma standard library. Theseperipheralsare
designed with the same Coretechnology providing
full compatibility and short design time. Many of
these macrocells are specially dedicated to TV ap-
plications.
with a 7-bit software programmable prescaler
(Timer), a digital hardware activated watchdog
function (DHWD), a 14-bit voltage synthesis tuning
peripheral, a Serial Peripheral Interface (SPI), up
to four6-bit PWM D/A converters,an AFC A/D con-
verter with 0.5V resolution, an on-screen display
(OSD) with 15 characters per line and 128 charac-
ters (in two banks each of 64 characters). In addi-
tion the following Memory resources are available:
program EPROM (8K), data RAM (256 bytes),
EEPROM (128 bytes).
Refer to pin configuration figures and to ST631xx
device summary (Table 1) for the definition of
ST631xx family members and a summary of differ-
ences among the different types.
The macrocells of the ST631xx family are: two
Timer peripherals each including an 8-bit counter
69/82
ST63E140,E142,E126,E156, T140,T142,T126,T156
Figure 3. ST631xx family Block Diagram
* Refer To Pin Configuration For Additional Information
*
TEST
TEST/VP P
IRIN/NMI
PORT A
PORT B
PORT C
PA0 - PA7
PB2 - PB7
PC0 - PC7
IR INTERRUPT
Input
*
*
DATA ROM
USER SELECTABLE
SERIAL PERIPHERAL
INTERFACE
USER PROGRAM
EPROM
DATA RAM
256 Bytes
8 KBytes
TIMER 1
TIMER 2
DATA EEPROM
128 Bytes
DIGITAL
WATCHDOG/TIMER
PC
STACK LEVEL 1
STACK LEVEL 2
STACK LEVEL 3
STACK LEVEL 4
STACK LEVEL 5
STACK LEVEL 6
D / A Outputs
DA0 - DA3
8-BIT CORE
VS output
AFC input
&
*
AFC & VS
ON-SCREEN
DISPLAY
R, G, B, BLANK
HSYNC (PB3)
VSYNC (PB2)
POWER SUPPLY OSCILLATOR
RESET
VR01753F
V
V
OSCin OSCout
RESET
OSDOSCin
OSDOSCout
DD
SS
Table 1. Device Summary
EPROM OTP RAM
ROM
(Bytes) (Bytes) (Bytes) (Bytes)
EEPROM
TARGET
ROM
DEVICES
KBY BSW
DEVICE
I/O
AFC
VS
D/A
PACK.
I/O
OUT
ST63E140
ST63T140
ST63E142
ST631T42
ST63E126
ST63T126
ST63E156
ST63T156
8K
8K
8K
8K
256
256
256
256
256
256
256
256
128
128
128
128
128
128
128
128
6
6
3
3
3
3
3
3
3
3
3
3
3
3
4
4
4
4
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
NO
1
1
1
1
4
4
4
4
PDIP28 ST63140
PDIP28 ST63140
PDIP28 ST63142
PDIP28 ST63142
PDIP40 ST63126
PDIP40 ST63126
PDIP40 ST63156
PDIP40 ST63156
8K
8K
8K
8K
6
6
NO
12
12
11
11
NO
NO
YES
YES
70/82
ST63E140,E142,E126,E156, T140,T142,T126,T156
PIN DESCRIPTION
V
DD and VSS. Power is supplied to the MCU using
PC0-PC7. These 8 lines are organized as one I/O
port (C). Each line may be configured as either an
input with or without internal pull-up resistor or as
an output under software control of the data direc-
tion register. PC0-PC2, PC4 have apush-pull con-
figuration in output mode while PC3, PC5-PC7
(OSD signals) are open-drain(5V drive). PC3, PC5 ,
PC6 and PC7 lines when in output mode are
“ANDed” with the character and blank signals of
the OSD cell. PC3 is connected with the OSD
BLANK signal, PC5, PC6 and PC7 withthe OSDR,
G and B signals. The active polarity of these sig-
nals canbe selected by the user as ROM mask op-
tion. PC2 is also used as TV set ON-OFF switch
(5V drive).
these two pins. VDD is power and VSS is theground
connection.
OSCin, OSCout. These pins are internally con-
nected to the on-chip oscillator circuit. A quartz
crystal or a ceramic resonator can be connected
between these two pins in order to allow the cor-
rect operation of the MCU with various stabil-
ity/cost trade-offs. The OSCin pin is the input pin,
the OSCout pin is the output pin.
RESET. The active low RESET pin is used to start
the microcontroller to the beginningof its program.
TEST/VPP. The TEST pin must be held at VSS for
normal operation. If this pin is connected to a
12.5V level during the reset phase, the EPROM
programming mode is entered.
DA0-DA3. These pins are the four PWM D/A out-
puts (with 32kHz repetition) ofthe 6-bit on-chip D/A
converters. The PWM function can be disabled by
software and these lines can be used as general
purpose open-drain outputs (12V drive).
Caution. Exceeding 13V on TEST/VPP pin will per-
manently damaged the device.
PA0-PA7. These 8 lines are organized as one I/O
port (A). Each line may be configured as either an
input or as an output under software control of the
data direction register. Port A has an open-drain
(12V drive) output configuration with direct LED
driving capability (30mA, 1V).
IRIN. This pin is the external NMI of the MCU.
OUT1. This pin is the 62.5kHz output specially
suited to drive multi-standard chroma processors.
This function can be disabled by software and the
pin can be used as general purpose open-drain
output (12V drive).
PB2-PB3, PB5-PB7. These lines are organizedas
one I/O port (B). Each line may be configured as
either aninput with or without internal pull-up resis-
tor or as an output under software control of the
data direction register. PB2-PB3 have a push-pull
configuration in output mode while PB5-PB7 are
open-drain (5V drive).
BSW0-BSW3. These output pins can be used to
select up to 4 tuning bands. These lines are config-
ured as open-drain outputs (12V drive).
KBY0-KBY2. These pins are input only and can be
used for keyboard scan. They have CMOS thresh-
old levels with Schmitt Trigger and on-chip 100kΩ
pull-up resistors.
PB2 and PB3 lines are connected to the VSYNC
and HSYNCcontrol signals of the OSD cell; to pro-
vide the right signals to the OSD these I/O lines
should beprogrammed in input mode and the user
can read “on the fly” the state of VSYNC and
HSYNC signals. PB2 is also connected with the
VSYNC Interrupt. The active polarity of VSYNC In-
terrupt signal is software controlled. The active po-
larity of these synchronization input pins to the
OSD macrocell can be selected by the user as
ROM mask option. If the device is specified to have
negative logic inputs, then when these signals are
low the OSD oscillator stops. If the device is speci-
fied to have positive logic inputs, then when these
signals are high the OSD oscillator stops.
AFC. This is the input of the on-chip 10 level com-
parator that can be used to implement the AFC
function. This pin is an high impedance input able
to withstand signals with a peak amplitude up to
12V.
OSDOSCin, OSDOSCout. These are the On
Screen Display oscillator terminals. An oscillation
capacitor and coil network have to be connected to
provide the right signal to the OSD.
VS. This is the output pin of the on-chip 14-bit volt-
age synthesis tuning cell (VS). The tuning signal
present at this pin gives an approximate resolution
of 40kHz per step over the UHF band. This line is a
push-pull output with standard drive (ST63140,
ST63156 only).
PB5, PB6 and PB7 lines, when in output modes,
are “ANDed” with the SPI control signals. PB5 is
connected with the SPI clock signal (SCL), PB6
with the SPI data signal (SDA) while PB7 is con-
nected with SPI enable signal (SEN).
71/82
ST63E140,E142,E126,E156, T140,T142,T126,T156
PIN DESCRIPTION (Continued)
Table 2. Pin Summary
Pin Function
DA0 to DA3
Description
Output, Open-Drain, 12V
BSW0 to BSW3
IRIN
Output, Open-Drain, 12V
Input, Resistive Bias, Schmitt Trigger
Input, High Impedance, 12V
AFC
OUT1
Output, Open-Drain, 12V
KBY0 to KBY2
R,G,B, BLANK
HSYNC, VSYNC
OSDOSCin
OSDOSCout
TEST/VPP
OSCin
Input, Pull-up, Schmitt Trigger
Output, Open-Drain, 5V
Input, Pull-up, Schmitt Trigger
Input, High Impedance
Output, Push-Pull
Input, Pull-Down
Input, Resistive Bias, Schmitt Trigger to Reset Logic Only
Output, Push-Pull
OSCout
RESET
Input, Pull-up, Schmitt Trigger Input
Output, Push-Pull
VS
PA0-PA6
I/O, Open-Drain, 12V, No Input Pull-up, Schmitt Trigger, High Drive
I/O, Push-Pull, 5V, Input Pull-up, Schmitt Trigger
I/O, Open-Drain, 5V, Input Pull-up, Schmitt Trigger
I/O, Push-Pull, 5V, Input Pull-up, Schmitt Trigger
I/O, Open-Drain, 5V, Input Pull-up, Schmitt Trigger
Power Supply Pins
PB2-PB3, PB5-PB7
PB5-PB7
PC0-PC2, PC4
PC3, PC5-PC7
V
DD, VSS
72/82
ST63E140,E142,E126,E156, T140,T142,T126,T156
MEMORY SPACE
Table 3. EPROM Memory Map
EPROM Page
Device Address
EPROM Address
Description
0000h-007Fh
0080h-07FFh
0000h-007Fh
0080h-07FFh
Reserved
User ROM
Page 0
0800h-0F9Fh
0FA0h-0FEFh
0FF0h-0FF7h
0FF8h-0FFBh
0FFCh-0FFDh
0FFEh-0FFFh
0800h-0F9Fh
0FA0h-0FEFh
0FF0h-0FF7h
0FF8h-0FFBh
0FFCh-0FFDh
0FFEh-0FFFh
User ROM
Reserved
Interrupt Vectors
Reserved
NMI Vector
Reset Vector
Page 1
“STATIC”
0000h-000Fh
0010h-07FFh
1000h-100Fh
1010h-17FFh
Reserved
User ROM
Page 2
Page 3
0000h-000Fh
0010h-07FFh
1800h-180Fh
1810h-1FFFh
Reserved
user ROM
73/82
ST63E140,E142,E126,E156, T140,T142,T126,T156
EPROM/OTP DESCRIPTION.
The ST63E1xx representsthe genericpart number
From a user pointof view (with the following excep-
for the EPROM versions of the ST63140, 42, 26,
56 ROM products. They are intended for use dur-
ing the development of an application, and for pre-
production and small volume production.
The ST63T1xx OTP have the same charac-
teristics.
They both include EPROM memory instead of the
ROM memory of the ST631xx, and so the program
and constantsof the program can be easily modi-
fied by the user with the ST63E1XX EPROM Pro-
grammingBoard from SGS-THOMSON.
tions) the ST63E1xx,T1xx products have exactly
the same software and hardware features of the
ROM version. An additional mode is used to con-
figure the part for programming of the EPROM, this
is set by a +12.5V voltage applied to the TEST/VPP
pin. The programming of theST63E1xx,T1xxis de-
scribed in the User Manual of the EPROM Pro-
gramming board.
On the ST63E1xx, all the 7948 bytes of PRO-
GRAMmemory are available for the user, as all the
EPROM memory can be erased by exposure to UV
light. On the ST63T1xx (OTP device) a reserved
area for test purposes exists, as for the ST631xx
ROM device. In order to avoid any discrepancy be-
tween program functionality when using the
EPROM, OTP and ROM it is recommended NOT
TO USE THESE RESERVED AREAS, even when
using the ST63E1xx. The Table 3 is a summary of
the EPROM/ROM Map and its reserved area.
The ROM mask options of the ST631xx for OSD
polarities (HSYNC, VSYNC, R, G, B, BLANK) are
emulated with an EPROM OPTION BYTE. This is
programmed by the SGS-THOMSON EPROM
programming board and its associated software.
The EPROM Option Byte content will define the
OSD options as follows :
7
0
THE READER IS ASKED TO REFER TO THE
DATASHEET OF THE ST631xx ROM-BASED
DEVICE FOR FURTHER DETAILS.
Opt7
Opt6
Opt5
Opt4
Opt3
Opt 2 Opt 1 Opt 0
Opt7-Opt6. Device specific bits (1)
EPROM ERASING
Opt5 : This bit define the BLANK polarity,
if 0 the polarity will be negative
if 1 the polarity will be positive..
The EPROM of the windowed package of the
ST63E1xx may be erased by exposure to Ultra
Violet light.
Opt 4 : This bit define the RGB polarity,
if 0 the polarity will be negative
if 1 the polarity will be positive..
The erasure characteristic of the ST63E1xx
EPROM is such that erasure begins when the
memory is exposed to light with wave lengths
shorter than approximately 4000Å. It should be
noted that sunlight and some types of fluorescent
lamps have wavelengths inthe range3000-4000Å.
It is thus recommended that the window of the
ST63E1xxpackage be covered by anopaquelabel
to prevent unintentional erasure problems when
testing the application in such an environment.
The recommended erasure procedure of the
ST63E1xx EPROM is exposure to short wave ul-
traviolet light which haswavelength 2537Å. The in-
Opt 3 : This bit define the OSD H/Vsync polarity,
if 0 the polarity will be negative
if 1 the polarity will be positive.
Opt2-Opt0. Device specific bits (1)
Note 1. Device specific bits. These reserved bits
must beprogrammed according to thefollowing ta-
ble for their relevant device.
tegrated dose (i.e. UV intensity x exposure time)
Sales Type
Opt7-Opt6
0 0
Opt2-Opt0
1 0 0
2
for erasure should be a minimum of 15 W-sec/cm .
ST63E140/T140
ST63E142/T142
ST63E126/T126
ST63E156/T156
The erasure time with this dosage is approximately
15 to 20 minutes using an ultraviolet lamp with
12000µW/cm2 power rating. The ST63E1xx
should be placed within 2.5 cm (1 inch)of the lamp
tubes during erasure.
0 0
1 0 1
0 0
1 0 1
0 0
1 0 1
74/82
ST63E140,E142,E126,E156, T140,T142,T126,T156
ABSOLUTE MAXIMUM RATINGS
Power Considerations. The average chip-junc-
tion temperature, Tj, in Celsius can be obtained
This product contains devices to protect the inputs
against damage due to high static voltages, how-
ever itis advisedto take normal precaution to avoid
application of any voltage higher than maximum
rated voltages.
from :
Tj =
Where :TA =
TA + PD x RthJA
Ambient Temperature.
RthJA = Package thermal resistance
(junction-to ambient).
For properoperation it is recommended that V and
I
VO must be higher than VSS and smaller than VDD
.
PD =
Pint + Pport.
Reliability is enhanced if unused inputs are con-
nected to an appropriatedlogic voltage level (VDD
or VSS).
Pint =
IDD x VDD (chip internal power).
Pport = Port power dissipation
(determinated by the user).
Symbol
VDD
VI
Parameter
Value
Unit
Supply Voltage
-0.3 to 7.0
V
V
Input Voltage (AFC IN)
SS - 0.3 to +13
V
V
V
V
VI
Input Voltage (Other Inputs)
V
SS - 0.3 to VDD +0.3
VO
Output Voltage (PA4-PA7, PC4-PC7, DA0-DA5)
Output Voltage (Other Outputs)
VSS - 0.3 to +13
VO
V
SS - 0.3 to VDD +0.3
VPP
IO
EPROM programming Voltage
-0.3 to 13.0
V
± 10
± 50
mA
Current Drain per Pin Excluding VDD, VSS, PA6, PA7
Current Drain per Pin (PA6, PA7)
Total Current into VDD (source)
mA
mA
IO
IVDD
IVSS
Tj
50
Total Current out of VSS (sink)
150
mA
Junction Temperature
Storage Temperature
150
-60 to 150
°C
TSTG
°C
Note : Stresses abovethose listedas “absolute maximum ratings” may cause permanent damageto the device . This is a stress rating only and
functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect
device reliability.
RECOMMENDED OPERATING CONDITIONS
Value
Symbol
Parameter
Test Conditions
Unit
Min.
Typ.
Max.
TA
Operating Temperature
Operating Supply Voltage
0
70
°C
VDD
4.5
5.0
6.0
V
Oscillator Frequency
RUN & WAIT Modes
fOSC
8
8.1
8.0
MHz
MHz
On-screen Display Oscillator
Frequency
fOSDOSC
75/82
ST63E140,E142,E126,E156, T140,T142,T126,T156
EEPROM INFORMATION
The ST631xx EEPROM single poly process has been speciallydevelopedto achieve 300.000
Write/Erase cycles and a 10 years data retention.
DC ELECTRICAL CHARACTERISTICS
(TA = 0 to +70°C unless otherwise specified)
Value
Symbol
Parameter
Test Conditions
Unit
Min.
Typ.
Max.
VIL
VIH
Input Low Level Voltage
Input High Level Voltage
All I/O Pins, KBY0-2
All I/O Pins, KBY0-2
0.3xV
V
V
DD
0.75xVDD
VHYS
All I/O Pins, KBY0-2
VDD = 5V
Hysteresis Voltage(1)
1.0
V
Port B/C, DA0-3,
BSW0-3, OUT1,
VS, OSD Outputs,
VOL
Low Level Output Voltage
V
DD = 4.5V
IOL = 1.6mA
IOL = 5.0mA
0.4
1.0
V
V
Port A
VDD = 4.5V
IOL= 3.2mA
VOL
Low Level Output Voltage
0.4
1.0
V
V
IOL= 30mA
OSDOSCout, OSCout
VDD = 4.5V
IOL= 0.1mA
Port B/C(2), VS
VDD = 4.5V
VOL
Low Level Output Voltage
High Level Output Voltage
High Level Output Voltage
V
V
0.4
4.1
VOH
IOH = – 1.6mA
OSDOSCout, OSCout,
VDD = 4.5V
VOH
V
IOL= – 0.1mA
4.1
Input Pull Up Current
Input Mode with Pull-up
Port B/C, KBY0-2
VIN= VSS
IPU
– 100
– 50
– 25
mA
µA
(2)
OSCin
VIN= VSS
VIN= VDD
IIL
IIH
– 10
0.1
– 1
1
– 0.1
10
Input Leakage Current
All I/O Input Mode
no Pull-up
OSDOSCin
IIL
IIH
Input Leakage Current
Input Leakage Current
Input Leakage Current
– 10
– 50
10
µA
µA
µA
VIN= VDD or VSS
IIL
IIH
Reset Pin with Pull-up
VIN= VSS
– 30
– 10
AFC Pin
VIH= VDD
VIL= VSS
VIH= 12.0V
IIL
IIH
1
– 1
40
Port A, DA0-3, BSW0-3
OUT1, OSDout
VOH = VDD
IOH
Output Leakage Current
10
40
µA
µA
Port A, DA0-3, BSW0-3
OUT1
VOH = 12V
Output Leakage Current High
Voltage
IOH
76/82
ST63E140,E142,E126,E156, T140,T142,T126,T156
DC ELECTRICAL CHARACTERISTICS (Continued)
Value
Typ.
Symbol
Parameter
Test Conditions
Unit
Min.
Max.
f
OSC= 8MHz, ILoad= 0mA
IDD
IDD
Supply Current RUN Mode
Supply Current WAIT Mode
Reset Trigger Level ON
6
3
16
mA
mA
V
VDD= 6.0V
fOSC= 8MHz, ILoad= 0mA
VDD= 6V
10
VON
VOFF
VTA
RESET Pin
RESET Pin
0.3xV
DD
Reset Trigger Level OFF
Input Level Absolute Tolerance
0.8xVDD
V
A/D AFC Pin
VDD = 5V
±200
±100
mV
A/D AFC Pin
Relative to other levels
VDD = 5V
VTR
Input Level Relatice Tolerance
mV
77/82
ST63E140,E142,E126,E156, T140,T142,T126,T156
AC ELECTRICAL CHARACTERISTICS
(TA = 0 to +70°C, fOSC=8MHz, VDD=4.5 to 6.0V unless otherwise specified )
Value
Typ.
Symbol
Parameter
Test Conditions
Unit
Min.
Max.
tWRES
tOHL
Minimum Pulse Width
RESET Pin
125
ns
PA6, PA7
VDD = 5V, CL = 1000pF (2)
High to Low Transition Time
100
20
ns
ns
DA0-DA5, PB0-PB6, OSD
Outputs, PC0-PC7,
VDD = 5V, CL = 100pF
tOHL
High to Low Transition Time
Low to High Transition Time
PB0-PB6, PA0-PA3, OSD
Outputs, PC0-PC3
20
tOLH
VDD = 5V, CL = 100pF
ns
Data HOLD Time
175
ns
tOH
SPI after clock goes low
I2CBUS/S-BUS Only
D/A Converter Repetition
Frequency(1)
f DA
f SIO
tWEE
31.25
62.50
kHz
kHz
SIO Baud Rate(1)
EEPROM Write Time
TA = 25°C One Byte
5
10
ms
cycles
years
Q
A LOT
> 1
million
Endurance EEPROM WRITE/ERASE Cycles
Retention EEPROM Data Retention (4)
300.000
Acceptance Criteria
T
A = 25°C
10
10
10
CIN
Input Capacitance (3)
Output Capacitance (3)
All Inputs Pins
All outputs Pins
pF
COUT
pF
COSCin, Oscillator Pins Internal
COSCout Capacitance(3)
5
pF
pF
COSDin, OSD Oscillator External
COSDout Capacitance
Recommended
15
25
Notes:
1.A clock other than 8 MHz will affect the frequency response of those peripherals (D/A, 62.5kHz and SPI) whose clock is
derived from the system clock.
2. The rise and fall times of PORT A have been reduced in order to avoid current spikes while maintaining a high drive capability
3. Not 100% Tested
4. Based on extrapolated data
78/82
ST63E140,E142,E126,E156, T140,T142,T126,T156
PACKAGE MECHANICAL DATA
Figure 69. 40 PinCeramic Dual-In-line Package
Dim.
mm
inches
Min
Typ Max Min
Typ Max
A
A1
B
0.45
50.8
.018
B1
C
D
2.00
0.600 BSD
.52
D1
E
15.2 BSD
E1
K
13.2
L
e1
Ø
Number of Pins
40
N
Figure 70. 28-Pin Ceramic Dual-In-line Package
Dim.
mm
inches
Typ Max
.225
Min
Typ Max
Min
A
A1
B
5.71
0.50
0.40
1.17
0.22
1.78 .020
0.55 .016
1.42 .046
0.31 .009
38.10
.070
.022
B1
C
.056
.012
D
1.500
.098
D1
E
15.2
24.9 .060
15.2 BSD
0.600 BSD
.526
E1 13.05
13.36 .514
.118
L
e1
Ø
3.00
2.29
6.86
2.79 .090
7.36 .270
.110
.290
Number of Pins
N
28
79/82
ST63E140,E142,E126,E156, T140,T142,T126,T156
ORDERING INFORMATION
OSD Test Character.IN ORDER TO ALLOWTHE
To ensure compatibility between the EPROM/OTP
parts and the corresponding ROM families, the fol-
lowing information is provided. the user should
take this information into account when program-
ming the memory and OSD characters of the
EPROM parts.
TESTING OF THE ON-CHIP OSD MACROCELL
THE FOLLOWING CHARACTER MUST BE PRO-
VIDED AT THE FIXED 3Fh (63) POSITION OF
THE SECOND OSD BANK.
Listing Generation & Verification. When SGS-
THOMSON receives the files, a computer listing is
generated fromthem. This listing refers extractly to
the mask that will be used to produce the micro-
controller. Then the listing is returned to the cus-
tomer that must thoroughly check, complete, sign
and return it to SGS-THOMSON. The signed list
constitutes a part of the contractual agreement for
the creation of the customer mask. SGS-THOM-
SON sales organization will provide detailed infor-
mation on contractual points.
Communication of the ROM Codes. To commu-
nicate the contents of memories to SGS-THOM-
SON, the customer has to send:
– one file in INTEL INTELLEC 8/MDS FOR-
MAT (either as an EPROM or in a MS-DOS 5”
diskette)for the ODD and EVEN OSD Character
OSD ROM/EEPROM
– one file in INTEL INTELLEC 8/MDS FOR-
MAT (either as an EPROM or in a MS-DOS 5”
diskette) for the EEPROM initial content (this
file is optional)
Figure 71. OSD Test Character
– a filled Option List form as described in the
OPTION LIST paragraph.
The ROM code must be generated with ST6 as-
sembler. Before programming the EPROM, the
buffer of the EPROM programmer must be filled
with FFh.
For shipment to SGS-THOMSON the EPROMs
should be placed in a conductive IC carrier and
packaging carefully.
Customer EEPROM Initial Contents:
Format
a. The content should be written into an INTEL IN-
TELLEC format file.
b. Undefined or don’t care bytes should have the
content FFh.
80/82
ST63E140,E142,E126,E156, T140,T142,T126,T156
ST63E1xx/T1xx MICROCONTROLLER OPTION LIST
Customer:
Address:
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact:
Phone No:
Reference:
Device
[ ] ST63E140 [ ] ST63E142 [ ] ST63E126 [ ] ST63E156
[ ] ST63T140 [ ] ST63T142 [ ] ST63T126 [ ] ST63T156
Temperature Range
0 to 70°C
For marking one line with 10 characters maximum is possible
Special Marking
[ ] No
[ ] Yes Line1 “ _ _ _ _ _ _ _ _ _ _ ”
Letters, digits, ’ .’, ’ - ’, ’ / ’ and spaces only
the default marking is equivalent to the sales type only (part number).
CHECK LIST:
YES
[ ]
NO
[ ]
OSD Code: ODD & EVEN
EEPROM Code (if Desired)
[ ]
[ ]
Signature ...................................
Date ...........................................
81/82
ST63E140,E142,E126,E156, T140,T142,T126,T156
ORDERING INFORMATION TABLE
Sales Type
ST63E140D1
ST63E142D1
ST63E126D1
ST63E156D1
ST63T140B1
ST63T142B1
ST63T126B1
ST63T156B1
ROM/EEPROM
Temperature Range
0 to + 70 ° C
CDIP28
Package
CDIP28
8K (EPROM)
0 to + 70 ° C
/
128 Bytes
0 to + 70 ° C
CDIP40
0 to + 70 ° C
CDIP40
0 to + 70 ° C
PDIP28
PDIP28
8K (OTPROM)
0 to + 70 ° C
/
128 Bytes
0 to + 70 ° C
0 to + 70 ° C
PDIP40
PDIP40
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the
consequences of use ofsuch information nor for any infringement of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights ofSGS-THOMSON Microelectronics. Specifications mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without the
express written approval of SGS-THOMSON Microelectronics.
1994 SGS-THOMSON Microelectronics - All rights reserved.
2
2
Purchase of I C Components by SGS-THOMSON Microelectronics conveys a license under the Philips I C Patent.
2
2
Rights to use these components in an I C system is granted provided that the system conforms to the I C Standard
Specification as defined by Philips.
SGS-THOMSON Microelectronics Group of Companies
Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands
Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
82/82
相关型号：
ST63E73J5D1
8-BIT ROM/OTP/EPROM MCUs FOR DIGITALLY CONTROLLED MULTISYNC/MULTISTANDARD MONITORS
STMICROELECTR
ST63E85
8-BIT, UVPROM, 8MHz, MICROCONTROLLER, CDIP42, WINDOWED, SHRINK, CERAMIC, DIP-42
STMICROELECTR
ST63E87
8-BIT, UVPROM, 8MHz, MICROCONTROLLER, CDIP42, WINDOWED, SHRINK, CERAMIC, DIP-42
STMICROELECTR
©2020 ICPDF网 联系我们和版权申明