ST72101G1B1_技术文档

ST72101/ST72212/ST72213

8-BIT MCU WITH 4 TO 8K ROM/OTP/EPROM,

256 BYTES RAM, ADC, WDG, SPI AND 1 OR 2 TIMERS

DATASHEET

■ User Program Memory (ROM/OTP/EPROM):

4 to 8K bytes

■ Data RAM: 256 bytes, including 64 bytes of

stack

■ Master Reset and Power-On Reset

■ Run, Wait, Slow, Halt and RAM Retention

modes

■ 22 multifunctional bidirectional I/O lines:

PSDIP32

– 22 programmable interrupt inputs

– 8 high sink outputs

– 6 analog alternate inputs

– 10 to 14 alternate functions

– EMI filtering

■ Programmable watchdog (WDG)

■ One or two 16-bit Timers, each featuring:

– 2 Input Captures

– 2 Output Compares

CSDIP32W

– External Clock input (on Timer A only)

– PWM and Pulse Generator modes

■ Synchronous Serial Peripheral Interface (SPI)

■ 8-bit Analog-to-Digital converter (6 channels)

(ST72212 and ST72213 only)

■ 8-bit Data Manipulation

■ 63 Basic Instructions

SO28

■ 17 main Addressing Modes

■ 8 x 8 Unsigned Multiply Instruction

■

True Bit Manipulation

(See ordering information at the end of datasheet)

■ Complete Development Support on PC/DOS-

TM

WINDOWS Real-Time Emulator

■ Full Software Package on DOS/WINDOWS^TM

(C-Compiler, Cross-Assembler, Debugger)

Device Summary

Features

ST72101G1

ST72101G2

ST72213G1

ST72212G2

Program Memory- bytes

RAM (stack) - bytes

16-bit Timers

4K

8K

4K

8K

256 (64)

one

no

one

no

one

yes

two

yes

ADC

Other Peripherals

Operating Supply

CPU Frequency

Temperature Range

Package

Watchdog, SPI

3 to 5.5 V

8MHz max (16MHz oscillator) - 4MHz max over 85°C

- 40°C to + 125°C

SO28 - SDIP32

Rev. 1.7

September 1999

1/84

1

Table of Contents

1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.3 EXTERNAL CONNECTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.4 MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3 CLOCKS, RESET, INTERRUPTS & POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . 16

3.1 CLOCK SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.1.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.2 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.2.2 External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.2.3 Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.2.4 Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.3 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.4 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.4.2 Slow Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.4.3 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.4.4 Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.5 MISCELLANEOUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.1 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.1.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.1.3 I/O Port Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.1.4 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.2 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

4.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

4.2.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

4.2.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4.2.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4.2.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4.2.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4.3 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

4.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

4.3.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

4.3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

4.3.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

4.3.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

95

4.3.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

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Table of Contents

4.4 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

4.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

4.4.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

4.4.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

4.4.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

4.4.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

4.4.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

4.4.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

4.5 8-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

4.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

4.5.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

4.5.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

4.5.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

4.5.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

4.5.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

5 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

5.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

5.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

5.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

5.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

5.1.4 Indexed (No Offset, Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

5.1.5 Indirect (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

5.1.6 Indirect Indexed (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

5.1.7 Relative mode (Direct, Indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

5.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

6 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

6.1 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

6.2 RECOMMENDED OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

6.3 DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

6.4 RESET CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

6.5 OSCILLATOR CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

6.6 A/D CONVERTER CHARACTERISTICS (ST72212 AND ST72213 ONLY) . . . . . . . . . . . 75

6.7 SPI CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

7 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

7.1 EPROM ERASURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

7.2 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

7.3 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

7.3.1 Transfer Of Customer Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

8 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

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3

ST72101/ST72212/ST72213

1 GENERAL DESCRIPTION

1.1 INTRODUCTION

The ST72101, ST72213 and ST72212 HCMOS

Microcontroller Units are members of the ST7

family. These devices are based on an industry-

standard 8-bit core and feature an enhanced

instruction set. They normally operate at a 16MHz

oscillator frequency. Under software control, the

ST72101, ST72213 and ST72212 may be placed

in either WAIT, SLOW or HALT modes, thus

reducing power consumption. The enhanced

instruction set and addressing modes afford real

programming potential. In addition to standard

8-bit data management, the ST72101, ST72213

and ST72212 feature true bit manipulation, 8x8

unsigned multiplication and indirect addressing

modes on the whole memory. The devices include

an on-chip oscillator, CPU, program memory

(ROM/OTP/EPROM versions), RAM, 22 I/O lines

and the following on-chip peripherals: Analog-to-

Digital Converter (ADC) with 6 multiplexed analog

inputs (ST72212 and ST72213 only), industry

standard synchronous SPI serial interface, digital

Watchdog, one or two independent 16-bit Timers,

one featuring an External Clock Input, and both

featuring Pulse Generator capabilities, 2 Input

Captures and 2 Output Compares.

Figure 1. ST72101, ST72213 and ST72212 Block Diagram

Internal

CLOCK

OSCIN

PA0 -> PA7

(8 bits)

PORT A

SPI

OSC

OSCOUT

RESET

CONTROL

PORT B

PB0 -> PB7

(8 bits)

8-BIT CORE

ALU

TIMER A

PORT C

PC0 -> PC5

(6 bits)

PROGRAM

MEMORY

(4 - 8K Bytes)

1)

8-BIT ADC

TIMER B

2)

RAM

(256 Bytes)

V

DD

WATCHDOG

POWER

SUPPLY

V

SS

1) ST72213 and ST72212 only

2) ST72212 only

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ST72101/ST72212/ST72213

1.2 PIN DESCRIPTION

Figure 2. ST72212 Pinout (SO28)

Figure 5. ST72212 Pinout (SDIP32)

32

V_DD

RESET

OSCIN

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

V_SS

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

V_DD

V_SS

1

2

3

4

5

6

7

8

RESET

OSCIN

28

27

26

25

24

23

22

21

20

19

18

17

16

15

1)

TEST/V_PP

PA0

OSCOUT

SS/PB7

1)

TEST/V_PP

OSCOUT

PA1

SCK/PB6

SS/PB7

PA0

MISO/PB5

PA2

SCK/PB6

PA1

PA3

MOSI/PB4

MISO/PB5

PA2

NC

MOSI/PB4

PA3

NC

OCMP2_A/PB3

ICAP2_A/PB2

OCMP1_A/PB1

ICAP1_A/PB0

AIN5/EXTCLK_A/PC5

AIN4/OCMP2_B/PC4

AIN3/ICAP2_B/PC3

PA4

OCMP2_A/PB3

ICAP2_A/PB2

OCMP1_A/PB1

ICAP1_A/PB0

AIN5/EXTCLK_A/PC5

AIN4/OCMP2_B/PC4

AIN3/ICAP2_B/PC3

PA4

PA5

PA6

PA7

PA5

9

PA6

10

11

12

13

14

PA7

PC0/ICAP1_B/AIN0

PC1/OCMP1_B/AIN1

PC2/CLKOUT/AIN2

PC0/ICAP1_B/AIN0

PC1/OCMP1_B/AIN1

PC2/CLKOUT/AIN2

1) V on EPROM/OTP only

PP

1) V

PP

on EPROM/OTP only

Figure 6. ST72213 Pinout (SDIP32)

Figure 3. ST72213 Pinout (SO28)

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

V_DD

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

RESET

OSCIN

V_SS

RESET

OSCIN

1

2

3

4

5

6

7

8

28

27

26

25

24

23

22

21

20

19

18

17

16

15

V_DD

V_SS

1)

TEST/V_PP

PA0

PA1

PA2

PA3

NC

OSCOUT

SS/PB7

1)

OSCOUT

TEST/V_PP

SCK/PB6

MISO/PB5

MOSI/PB4

SS/PB7

PA0

SCK/PB6

PA1

MISO/PB5

PA2

NC

MOSI/PB4

PA3

NC

OCMP2_A/PB3

ICAP2_A/PB2

OCMP1_A/PB1

ICAP1_A/PB0

AIN5/EXTCLK_A/PC5

AIN4/PC4

PA4

OCMP2_A/PB3

ICAP2_A/PB2

OCMP1_A/PB1

ICAP1_A/PB0

AIN5/EXTCLK_A/PC5

AIN4/PC4

9

PA5

10

11

12

13

14

PA6

PA7

PC0/AIN0

PC1/AIN1

PC2/CLKOUT/AIN2

PC0/AIN0

PC1/AIN1

AIN3/PC3

PC2/CLKOUT/AIN2

AIN3/PC3

1) V

PP

onEPROM/OTP only

1) V

PP

on EPROM/OTP only

Figure 7. ST72101 Pinout (SDIP32)

Figure 4. ST72101 Pinout (SO28)

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

V_DD

RESET

OSCIN

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

V_SS

1

2

3

4

5

6

7

8

V_DD

V_SS

RESET

OSCIN

28

27

26

25

24

23

22

21

20

19

18

17

16

15

1)

TEST/V_PP

PA0

OSCOUT

SS/PB7

1)

OSCOUT

TEST/V_PP

PA1

SCK/PB6

MISO/PB5

MOSI/PB4

SS/PB7

PA0

PA2

SCK/PB6

PA1

PA3

MISO/PB5

MOSI/PB4

OCMP2_A/PB3

ICAP2_A/PB2

OCMP1_A/PB1

ICAP1_A/PB0

EXTCLK_A/PC5

PC4

PA2

NC

PA3

NC

PA4

PA5

PA6

PA7

PC0

PC1

OCMP2_A/PB3

ICAP2_A/PB2

OCMP1_A/PB1

ICAP1_A/PB0

EXTCLK_A/PC5

PC4

9

PA5

10

11

12

13

14

PA6

PA7

PC0

PC1

PC3

PC2/CLKOUT

PC3

1) V on EPROM/OTP only

PP

1) V

PP

on EPROM/OTPonly

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ST72101/ST72212/ST72213

Table 1. ST72212 Pin Configuration

Pin n° Pin n °

Pin Name

RESET

Type

Description

Remarks

SDIP32 SO28

1

2

1

2

3

4

5

6

7

I/O Bidirectional. Active low. Top priority non maskable interrupt.

OSCIN

I

Input/Output Oscillator pin. These pins connect a parallel-resonant

crystal, or an external source to the on-chip oscillator.

3

OSCOUT

PB7/SS

O

4

I/O Port B7 or SPI Slave Select (active low)

I/O Port B6 or SPI Serial Clock

External Interrupt: EI1

5

PB6/SCK

PB5/MISO

PB4/MOSI

NC

External Interrupt: EI1

6

I/O Port B5 or SPI Master In/ Slave Out Data

I/O Port B4 or SPI Master Out / Slave In Data

Not Connected

7

8

9

NC

Not Connected

10

11

12

13

14

8

PB3/OCMP2_A

PB2/ICAP2_A

PB1/OCMP1_A

PB0/ICAP1_A

I/O Port B3 or TimerA Output Compare 2

I/O Port B2 or TimerA Input Capture 2

I/O Port B1 or TimerA Output Compare 1

I/O Port B0 or TimerA Input Capture 1

External Interrupt: EI1

9

10

11

12

PC5/EXTCLK_A/AIN5 I/O PortC5orTimerA InputClockorADCAnalog Input5 External Interrupt: EI1

PortC4orTimerB OutputCompare 2or ADCAnalog

15

16

13

14

PC4/OCMP2_B/AIN4 I/O

External Interrupt: EI1

Input 4

Port C3 or TimerB Input Capture 2 or ADC Analog

Input 3

PC3/ICAP2_B/AIN3

PC2/CLKOUT/AIN2

I/O

External Interrupt: EI1

Port C2or Internal Clock Frequency Outputor ADC

I/O Analog Input 2. Clockout is driven by Bit 5 of the External Interrupt: EI1

miscellaneous register.

17

15

PortC1orTimerB OutputCompare 1or ADCAnalog

18

19

16

17

PC1/OCMP1_B/AIN1 I/O

External Interrupt: EI1

Input 1

Port C0 or TimerB Input Capture 1 or ADC Analog

Input 0

PC0/ICAP1_B/AIN0

I/O

20

21

22

23

24

25

26

27

28

29

18

19

20

21

PA7

PA6

PA5

PA4

NC

I/O Port A7, High Sink

I/O Port A6, High Sink

I/O Port A5, High Sink

I/O Port A4, High Sink

Not Connected

External Interrupt: EI0

NC

Not Connected

22

23

24

25

PA3

PA2

PA1

I/O Port A3, High Sink

I/O Port A2, High Sink

I/O Port A1, High Sink

I/O Port A0, High Sink

External Interrupt: EI0

PA0

Test mode pin (should be tied low in user mode). In the EPROM program-

(1)

30

26

TEST/V

I/S

PP

ming mode, this pin acts as the programming voltage input V

PP.

31

32

27

28

V

S

Ground

SS

DD

Main power supply

Note 1: V on EPROM/OTP only

PP

6/84

6

ST72101/ST72212/ST72213

Table 2. ST72213 Pin Configuration

Pin n° Pin n°

SDIP32 SO28

Pin Name

RESET

Type

Description

Remarks

Bidirectional. Active low. Top priority non maskable interrupt.

1

2

1

2

3

4

5

6

7

I/O

I

OSCIN

Input/Output Oscillator pin. These pins connect a parallel-resonant

crystal, or an external source to the on-chip oscillator.

3

OSCOUT

PB7/SS

O

4

I/O Port B7 or SPI Slave Select (active low)

External Interrupt: EI1

5

PB6/SCK

PB5/MISO

PB4/MOSI

NC

I/O Port B6 or SPI Serial Clock

I/O Port B5 or SPI Master In/ Slave Out Data

I/O Port B4 or SPI Master Out / Slave In Data

Not Connected

6

7

8

9

NC

Not Connected

10

11

12

13

8

9

PB3/OCMP2_A

PB2/ICAP2_A

PB1/OCMP1_A

PB0/ICAP1_A

I/O Port B3 or TimerA Output Compare 2

I/O Port B2 or TimerA Input Capture 2

I/O Port B1 or TimerA Output Compare 1

External Interrupt: EI1

10

11

I/O Port B0 or TimerA Input Capture 1

Port C5 or TimerA Input Clock or ADC Analog

Input 5

14

12

PC5/EXTCLK_A/AIN5 I/O

External Interrupt: EI1

15

16

13

14

PC4/AIN4

PC3/AIN3

I/O Port C4 or ADC Analog Input 4

External Interrupt: EI1

I/O Port C3 or ADC Analog Input 3

Port C2 or Internal Clock Frequency Output or

17

15

PC2/CLKOUT/AIN2

I/O ADC Analog Input 2. Clockout is driven by Bit 5 External Interrupt: EI1

of the miscellaneous register.

18

19

20

21

22

23

24

25

26

27

28

29

16

17

18

19

20

21

PC1/AIN1

PC0/AIN0

PA7

I/O Port C1 or ADC Analog Input 1

I/O Port C0 or ADC Analog Input 0

I/O Port A7, High Sink

I/O Port A6, High Sink

I/O Port A5, High Sink

I/O Port A4, High Sink

Not Connected

External Interrupt: EI1

External Interrupt: EI0

PA6

PA5

PA4

NC

Not Connected

22

23

24

25

PA3

I/O Port A3, High Sink

I/O Port A2, High Sink

I/O Port A1, High Sink

I/O Port A0, High Sink

External Interrupt: EI0

PA2

PA1

PA0

Test mode pin (should be tied low in user mode). In the EPROM pro-

(1)

30

26

TEST/V

I/S

PP

gramming mode, this pin acts as the programming voltage input V

PP.

31

32

27

28

V

S

Ground

SS

DD

Main power supply

Note 1: V on EPROM/OTP only

PP

7/84

7

ST72101/ST72212/ST72213

Table 3. ST72101 Pin Configuration

Pin n° Pin n°

SDIP32 SO28

Pin Name

RESET

Type

Description

Remarks

1

2

1

2

3

4

5

6

7

I/O Bidirectional. Active low. Top priority non maskable interrupt.

I

OSCIN

OSCOUT

PB7/SS

PB6/SCK

PB5/MISO

PB4/MOSI

NC

Input/Output Oscillator pin. These pins connect a parallel-resonant crystal, or

an external source to the on-chip oscillator.

3

O

4

I/O Port B7 or SPI Slave Select (active low)

External Interrupt: EI1

5

I/O Port B6 or SPI Serial Clock

I/O Port B5 or SPI Master In/ Slave Out Data

I/O Port B4 or SPI Master Out / Slave In Data

Not Connected

6

7

8

9

NC

Not Connected

10

11

12

13

14

15

16

8

PB3/OCMP2_A I/O Port B3 or TimerA Output Compare 2

PB2/ICAP2_A I/O Port B2 or TimerA Input Capture 2

PB1/OCMP1_A I/O Port B1 or TimerA Output Compare 1

PB0/ICAP1_A I/O Port B0 or TimerA Input Capture 1

PC5/EXTCLK_A I/O Port C5 or TimerA Input Clock

External Interrupt: EI1

9

10

11

12

13

14

PC4

PC3

I/O Port C4

I/O Port C3

Port C2 or Internal Clock Frequency Output. Clockout

is driven by MCO bit of the miscellaneous register.

17

15

PC2/CLKOUT

I/O

External Interrupt: EI1

18

19

20

21

22

23

24

25

26

27

28

29

16

17

18

19

20

21

PC1

PC0

PA7

PA6

PA5

PA4

NC

I/O Port C1

External Interrupt: EI1

External Interrupt: EI0

I/O Port C0

I/O Port A7, High Sink

I/O Port A6, High Sink

I/O Port A5, High Sink

I/O Port A4, High Sink

Not Connected

NC

Not Connected

22

23

24

25

PA3

PA2

PA1

PA0

(1)

I/O Port A3, High Sink

I/O Port A2, High Sink

I/O Port A1, High Sink

I/O Port A0, High Sink

External Interrupt: EI0

Test mode pin (should be tied low in user mode). In the EPROM programming

mode, this pin acts as the programming voltage input V

30

26

TEST/V

I/S

PP

PP.

31

32

27

28

V

S

Ground

SS

DD

Main power supply

Note 1: V on EPROM/OTP only.

PP

8/84

8

ST72101/ST72212/ST72213

1.3 EXTERNAL CONNECTIONS

The following figure shows the recommended ex-

ternal connections for the device.

The external reset network is intended to protect

the device against parasitic resets, especially in

noisy environments.

The V pin is only used for programming OTP

PP

and EPROM devices and must be tied to ground in

user mode.

Unused I/Os should be tied high to avoid any un-

necessary power consumption on floating lines.

An alternative solution is to program the unused

ports as inputs with pull-up.

The 10 nF and 0.1 µF decoupling capacitors on

the power supply lines are a suggested EMC per-

formance/cost tradeoff.

Figure 8. Recommended External Connections

V

PP

V

DD

SS

+

0.1µF

10nF

V

DD

4.7K

0.1µF

RESET

EXTERNAL RESET CIRCUIT

See

Clocks

OSCIN

Section

OSCOUT

Or configure unused I/O ports

by software as input with pull-up

10K

V

DD

Unused I/O

9/84

9

ST72101/ST72212/ST72213

1.4 MEMORY MAP

Figure 9. Memory Map

0000h

0080h

HW Registers

Short Addressing

RAM (zero page)

(see Table 5)

007Fh

0080h

00FFh

0100h

16-bit Addressing

RAM

256 Bytes RAM

013Fh

0140h

017Fh

0180h

64 Bytes Stack or

16-bit Addressing RAM

017Fh

Reserved

DFFFh

E000h

8K Bytes

Program Memory

F000h

4K Bytes

Program

Memory

FFDFh

FFE0h

Interrupt & Reset Vectors

(see Table 4)

FFFFh

Table 4. Interrupt Vector Map

Vector Address

Description

Remarks

FFE0-FFE1h

FFE2-FFE3h

FFE4-FFE5h

FFE6-FFE7h

FFE8-FFE9h

FFEA-FFEBh

FFEC-FFEDh

FFEE-FFEFh

FFF0-FFF1h

FFF2-FFF3h

FFF4-FFF5h

FFF6-FFF7h

FFF8-FFF9h

FFFA-FFFBh

FFFC-FFFDh

FFFE-FFFFh

Not Used

TIMER B Interrupt Vector (ST72212 only)

Not Used

Internal Interrupt

TIMER A Interrupt Vector

SPI Interrupt Vector

Internal Interrupt

Not Used

External Interrupt Vector EI1

External Interrupt Vector EI0

TRAP (software) Interrupt Vector

RESET Vector

External Interrupt

CPU Interrupt

10/84

10

ST72101/ST72212/ST72213

Table 5. Hardware Register Memory Map

Block

Name

Register

Label

Address

Register name

Reset Status

Remarks

0000h

PCDR

Data Register

00h

R/W

0001h

0002h

Port C

PCDDR

PCOR

Data Direction Register

Option Register

0003h

Reserved Area (1 Byte)

0004h

0005h

0006h

PBDR

PBDDR

PBOR

Data Register

00h

R/W

Port B

Port A

Data Direction Register

Option Register

0007h

Reserved Area (1 Byte)

0008h

0009h

000Ah

PADR

PADDR

PAOR

Data Register

00h

R/W

Data Direction Register

Option Register

000Bh to

001Fh

Reserved Area (21 Bytes)

0020h

MISCR

Miscellaneous Register

00h

R/W

0021h

0022h

0023h

SPIDR

SPICR

SPISR

Data I/O Register

Control Register

Status Register

xxh

0xh

00h

R/W

SPI

Read Only

0024h

WDG

WDGCR

Watchdog Control register

7Fh

R/W

0025h to

0030h

Reserved Area (12 Bytes)

Control Register2

00h

xxh

80h

00h

FFh

FCh

FFh

FCh

xxh

80h

00h

R/W

0031h

TACR2

Control Register1

R/W

0032h

TACR1

Status Register

Read Only

R/W

0033h

TASR

0034h-0035h

TAIC1HR

TAIC1LR

TAOC1HR

TAOC1LR

TACHR

Input Capture1 High Register

Input Capture1 Low Register

Output Compare1 High Register

Output Compare1 Low Register

Counter High Register

0036h-0037h

0038h-0039h

003Ah-003Bh

003Ch-003Dh

003Eh-003Fh

R/W

Read Only

R/W

Timer A

TACLR

Counter Low Register

TAACHR

TAACLR

TAIC2HR

TAIC2LR

TAOC2HR

TAOC2LR

Alternate Counter High Register

Alternate Counter Low Register

Input Capture2 High Register

Input Capture2 Low Register

Output Compare2 High Register

Output Compare2 Low Register

R/W

0040h

Reserved Area (1 Byte)

11/84

11

ST72101/ST72212/ST72213

Block

Name

Register

Label

Address

0041h

Register name

Control Register2

Reset Status

Remarks

00h

xxh

80h

00h

FFh

FCh

FFh

FCh

xxh

80h

00h

R/W

TBCR2

Control Register1

R/W

0042h

TBCR1

Status Register

Read Only

R/W

0043h

TBSR

0044h-0045h

TBIC1HR

TBIC1LR

TBOC1HR

TBOC1LR

TBCHR

Input Capture1 High Register

Input Capture1 Low Register

Output Compare1 High Register

Output Compare1 Low Register

Counter High Register

0046h-0047h

0048h-0049h

004Ah-004Bh

004Ch-004Dh

004Eh-004Fh

R/W

1)

Read Only

R/W

Timer B

TBCLR

Counter Low Register

TBACHR

TBACLR

TBIC2HR

TBIC2LR

TBOC2HR

TBOC2LR

Alternate Counter High Register

Alternate Counter Low Register

Input Capture2 High Register

Input Capture2 Low Register

Output Compare2 High Register

Output Compare2 Low Register

R/W

0050h to

006Fh

Reserved Area (32 Bytes)

0070h

0071h

ADCDR

Data Register

00h

Read Only

R/W

2)

ADC

ADCCSR

Control/Status Register

0072h to

007Fh

Reserved Area (14 Bytes)

Notes:

1. ST72212 only, reserved area for other devices.

2. ST72212 and ST72213 only, reserved otherwise.

12/84

12

ST72101/ST72212/ST72213

2 CENTRAL PROCESSING UNIT

2.1 INTRODUCTION

Accumulator (A)

The Accumulator is an 8-bit general purpose reg-

ister used to hold operands and the results of the

arithmetic and logic calculations and to manipulate

data.

This CPU has a full 8-bit architecture and contains

six internal registers allowing efficient 8-bit data

manipulation.

Index Registers (X and Y)

2.2 MAIN FEATURES

In indexed addressing modes, these 8-bit registers

are used to create either effective addresses or

temporary storage areas for data manipulation.

(The Cross-Assembler generates a precede in-

struction (PRE) to indicate that the following in-

struction refers to the Y register.)

■ 63 basic instructions

■ Fast 8-bit by 8-bit multiply

■ 17 main addressing modes (with indirect

addressing mode)

■ Two 8-bit index registers

■ 16-bit stack pointer

The Y register is not affected by the interrupt auto-

matic procedures (not pushed to and popped from

the stack).

■ 8 MHz CPU internal frequency

■ Low power modes

■ Maskable hardware interrupts

■ Non-maskable software interrupt

Program Counter (PC)

The program counter is a 16-bit register containing

the address of the next instruction to be executed

by the CPU. It is made of two 8-bit registers PCL

(Program Counter Low which is the LSB) and PCH

(Program Counter High which is the MSB).

2.3 CPU REGISTERS

The 6 CPU registers shown in Figure 10 are not

present in the memory mapping and are accessed

by specific instructions.

Figure 10. CPU Registers

7

0

ACCUMULATOR

RESET VALUE = XXh

7

X INDEX REGISTER

Y INDEX REGISTER

RESET VALUE = XXh

7

0

RESET VALUE = XXh

PCL

PCH

7

8

15

0

PROGRAM COUNTER

RESET VALUE = RESET VECTOR @ FFFEh-FFFFh

7

1

0

1

H I N Z

C

X

CONDITION CODE REGISTER

RESET VALUE =

8

1

X 1 X X

15

7

0

STACK POINTER

RESET VALUE = STACK HIGHER ADDRESS

X = Undefined Value

13/84

13

ST72101/ST72212/ST72213

CENTRAL PROCESSING UNIT (Cont’d)

CONDITION CODE REGISTER (CC)

Read/Write

ter it and reset by the IRET instruction at the end of

the interrupt routine. If the I bit is cleared by soft-

ware in the interrupt routine, pending interrupts are

serviced regardless of the priority level of the cur-

rent interrupt routine.

Reset Value: 111x1xxx

7

0

1

H

I

N

Z

C

Bit 2 = N Negative.

This bit is set and cleared by hardware. It is repre-

sentative of the result sign of the last arithmetic,

logical or data manipulation. It is a copy of the 7

The 8-bit Condition Code register contains the in-

terrupt mask and four flags representative of the

result of the instruction just executed. This register

can also be handled by the PUSH and POP in-

structions.

th

bit of the result.

0: The result of the last operation is positive or null.

1: The result of the last operation is negative

(i.e. the most significant bit is a logic 1).

These bits can be individually tested and/or con-

trolled by specific instructions.

This bit is accessed by the JRMI and JRPL instruc-

tions.

Bit 4 = H Half carry.

This bit is set by hardware when a carry occurs be-

tween bits 3 and 4 of the ALU during an ADD or

ADC instruction. It is reset by hardware during the

same instructions.

0: No half carry has occurred.

1: A half carry has occurred.

Bit 1 = Z Zero.

This bit is set and cleared by hardware. This bit in-

dicates that the result of the last arithmetic, logical

or data manipulation is zero.

0: The result of the last operation is different from

zero.

This bit is tested using the JRH or JRNH instruc-

tion. The H bit is useful in BCD arithmetic subrou-

tines.

1: The result of the last operation is zero.

This bit is accessed by the JREQ and JRNE test

instructions.

Bit 3 = I Interrupt mask.

Bit 0 = C Carry/borrow.

This bit is set by hardware when entering in inter-

rupt or by software to disable all interrupts except

the TRAP software interrupt. This bit is cleared by

software.

0: Interrupts are enabled.

1: Interrupts are disabled.

This bit is set and cleared by hardware and soft-

ware. It indicates an overflow or an underflow has

occurred during the last arithmetic operation.

0: No overflow or underflow has occurred.

1: An overflow or underflow has occurred.

This bit is driven by the SCF and RCF instructions

and tested by the JRC and JRNC instructions. It is

also affected by the “bit test and branch”, shift and

rotate instructions.

This bit is controlled by the RIM, SIM and IRET in-

structions and is tested by the JRM and JRNM in-

structions.

Note: Interrupts requested while I is set are

latched and can be processed when I is cleared.

By default an interrupt routine is not interruptable

because the I bit is set by hardware when you en-

14/84

14

ST72101/ST72212/ST72213

CENTRAL PROCESSING UNIT (Cont’d)

Stack Pointer (SP)

The least significant byte of the Stack Pointer

(called S) can be directly accessed by a LD in-

struction.

Read/Write

Reset Value: 01 7Fh

Note: When the lower limit is exceeded, the Stack

Pointer wraps around to the stack upper limit, with-

out indicating the stack overflow. The previously

stored information is then overwritten and there-

fore lost. The stack also wraps in case of an under-

flow.

15

8

1

0

7

0

The stack is used to save the return address dur-

ing a subroutine call and the CPU context during

an interrupt. The user may also directly manipulate

the stack by means of the PUSH and POP instruc-

tions. In the case of an interrupt, the PCL is stored

at the first location pointed to by the SP. Then the

other registers are stored in the next locations as

shown in Figure 11.

1

SP5 SP4 SP3 SP2 SP1 SP0

The Stack Pointer is a 16-bit register which is al-

ways pointing to the next free location in the stack.

It is then decremented after data has been pushed

onto the stack and incremented before data is

popped from the stack (see Figure 11).

– When an interrupt is received, the SP is decre-

mented and the context is pushed on the stack.

Since the stack is 64 bytes deep, the 10 most sig-

nificant bits are forced by hardware. Following an

MCU Reset, or after a Reset Stack Pointer instruc-

tion (RSP), the Stack Pointer contains its reset val-

ue (the SP5 to SP0 bits are set) which is the stack

higher address.

– On return from interrupt, the SP is incremented

and the context is popped from the stack.

A subroutine call occupies two locations and an in-

terrupt five locations in the stack area.

Figure 11. Stack Manipulation Example

CALL

Subroutine

RET

or RSP

PUSH Y

POP Y

IRET

Interrupt

Event

@ 0140h

SP

Y

CC

A

CC

A

CC

A

X

PCH

PCL

PCH

PCL

PCH

PCL

PCH

PCL

PCH

PCL

PCH

PCL

SP

PCH

PCL

PCH

PCL

SP

@ 017Fh

Stack Lower Address = 0140h

017Fh

Stack Higher Address =

15/84

15

ST72101/ST72212/ST72213

3 CLOCKS, RESET, INTERRUPTS & POWER SAVING MODES

3.1 CLOCK SYSTEM

3.1.1 General Description

Figure 12. External Clock Source Connections

The MCU accepts either a Crystal or Ceramic res-

onator, or an external clock signal to drive the in-

ternal oscillator. The internal clock (f

) is de-

CPU

rived from the external oscillator frequency (f

)

OSC .

The external Oscillator clock is first divided by 2,

and division factor of 32 can be applied if Slow

Mode is selected by setting the SMS bit in the Mis-

cellaneous Register. This reduces the frequency

OSCIN

OSCOUT

NC

of the f

on-chip peripherals.

; the clock signal is also routed to the

CPU

EXTERNAL

CLOCK

The internal oscillator is designed to operate with

an AT-cut parallel resonant quartz crystal resona-

tor in the frequency range specified for f . The

osc

circuit shown in Figure 13 is recommended when

using a crystal, and Table 6 lists the recommend-

ed capacitance and feedback resistance values.

The crystal and associated components should be

mounted as close as possible to the input pins in

order to minimize output distortion and start-up

stabilisation time.

Figure 13. Crystal/Ceramic Resonator

Use of an external CMOS oscillator is recom-

mended when crystals outside the specified fre-

quency ranges are to be used.

OSCIN

OSCOUT

Table 6. Recommended Values for 16 MHz

Crystal Resonator (C <7pF)

0

C

OSCIN

OSCOUT

R

40 Ω

56pF

60 Ω

47pF

150 Ω

22pF

SMAX

C

OSCIN

C

OSCOUT

Figure 14. Clock Prescaler Block Diagram

C : parasitic shunt capacitance of the quartz crys-

0

tal.

R

: equivalent serial resistor of the crystal (up-

SMAX

er limit, see crystal specification).

%2

% 16

f

C

, C : maximum total capacitance on

CPU

OSCOUT

OSCIN

to CPU and

Peripherals

OSCIN and OSCOUT, including the external ca-

pacitance plus the parasitic capacitance of the

board and the device.

OSCIN

OSCOUT

C

OSCIN

OSCOUT

16/84

16

ST72101/ST72212/ST72213

3.2 RESET

3.2.1 Introduction

lowing a Reset event, or after exiting Halt mode, a

4096 CPU Clock cycle delay period is initiated in

order to allow the oscillator to stabilise and to en-

sure that recovery has taken place from the Reset

state.

There are three sources of Reset:

– RESET pin (external source)

– Power-On Reset (Internal source)

– WATCHDOG (Internal Source)

In the high state, the RESET pin is connected in-

ternally to a pull-up resistor (R ). This resistor

ON

The Reset Service Routine vector is located at ad-

dress FFFEh-FFFFh.

can be pulled low by external circuitry to reset the

device.

3.2.2 External Reset

The RESET pin is an asynchronous signal which

plays a major role in EMS performance. In a noisy

environment, it is recommended to use the exter-

nal connections shown in Figure 8.

The RESET pin is both an input and an open-drain

output with integrated pull-up resistor. When one

of the internal Reset sources is active, the Reset

pin is driven low , for a duration of t

the whole application.

to reset

RESET,

3.2.4 Power-on Reset

This circuit detects the ramping up of V , and

DD

3.2.3 Reset Operation

generates a pulse that is used to reset the applica-

The duration of the Reset state is a minimum of

4096 internal CPU Clock cycles. During the Reset

state, all I/Os take their reset value.

tion (at approximately V = 2V).

DD

Power-On Reset is designed exclusively to cope

with power-up conditions, and should not be used

in order to attempt to detect a drop in the power

supply voltage.

A Reset signal originating from an external source

must have a duration of at least t

be recognised. This detection is asynchronous

and therefore the MCU can enter Reset state even

in Halt mode.

in order to

PULSE

Caution: to re-initialize the Power-On Reset, the

power supply must fall below approximately 0.8V

(Vtn), prior to rising above 2V. If this condition is

not respected, on subsequent power-up the Reset

pulse may not be generated. An external Reset

pulse may be required to correctly reactivate the

circuit.

At the end of the Reset cycle, the MCU may be

held in the Reset state by an External Reset sig-

nal. The RESET pin may thus be used to ensure

V

has risen to a point where the MCU can oper-

DD

ate correctly before the user program is run. Fol-

Figure 15. Reset Block Diagram

INTERNAL

RESET

OSCILLATOR

SIGNAL

TO ST7

RESET

V

DD

R

ON

POWER-ON RESET

WATCHDOG RESET

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ST72101/ST72212/ST72213

3.3 INTERRUPTS

The ST7 core may be interrupted by one of two dif-

ferent methods: maskable hardware interrupts as

listed in the Interrupt Mapping Table and a non-

maskable software interrupt (TRAP). The Interrupt

processing flowchart is shown in Figure 16.

The maskable interrupts must be enabled clearing

the I bit in order to be serviced. However, disabled

interrupts may be latched and processed when

they are enabled (see external interrupts subsec-

tion).

Halt low power mode (refer to the “Exit from HALT“

column in the Interrupt Mapping Table).

External Interrupts

External interrupt vectors can be loaded in the PC

register if the corresponding external interrupt oc-

curred and if the I bit is cleared. These interrupts

allow the processor to leave the Halt low power

mode.

When an interrupt has to be serviced:

The external interrupt polarity is selected through

the miscellaneous register or interrupt register (if

available).

– Normal processing is suspended at the end of

the current instruction execution.

External interrupt triggered on edge will be latched

and the interrupt request automatically cleared

upon entering the interrupt service routine.

– The PC, X, A and CC registers are saved onto

the stack.

– The I bit of the CC register is set to prevent addi-

tional interrupts.

If several input pins, connected to the same inter-

rupt vector, are configured as interrupts, their sig-

nals are logically ANDed before entering the edge/

level detection block.

– ThePC is then loaded with the interrupt vector of

the interrupt to service and the first instruction of

the interrupt service routine is fetched (refer to

the Interrupt Mapping Table for vector address-

es).

Warning: The type of sensitivity defined in the

Miscellaneous or Interrupt register (if available)

applies to the EI source. In case of an ANDed

source (as described on the I/O ports section), a

low level on an I/O pin configured as input with in-

terrupt, masks the interrupt request even in case

of rising-edge sensitivity.

The interrupt service routine should finish with the

IRET instruction which causes the contents of the

saved registers to be recovered from the stack.

Note: As a consequence of the IRET instruction,

the I bit will be cleared and the main program will

resume.

Peripheral Interrupts

Different peripheral interrupt flags in the status

register are able to cause an interrupt when they

are active if both:

Priority management

By default, a servicing interrupt can not be inter-

rupted because the I bit is set by hardware enter-

ing in interrupt routine.

– The I bit of the CC register is cleared.

– The corresponding enable bit is set in the control

register.

In the case several interrupts are simultaneously

pending, an hardware priority defines which one

will be serviced first (see the Interrupt Mapping Ta-

ble).

If any of these two conditions is false, the interrupt

is latched and thus remains pending.

Clearing an interrupt request is done by:

Non Maskable Software Interrupts

– writing “0” to the corresponding bit in the status

register or

This interrupt is entered when the TRAP instruc-

tion is executed regardless of the state of the I bit.

It will be serviced according to the flowchart on

Figure 16.

– an access to the status register while the flag is

set followed by a read or write of an associated

register.

Note: the clearing sequence resets the internal

latch. A pending interrupt (i.e. waiting for being en-

abled) will therefore be lost if the clear sequence is

executed.

Interrupts and Low power mode

All interrupts allow the processor to leave the Wait

low power mode. Only external and specific men-

tioned interrupts allow the processor to leave the

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ST72101/ST72212/ST72213

INTERRUPTS (Cont’d)

Figure 16. Interrupt Processing Flowchart

FROM RESET

N

BIT I SET

Y

N

BIT I SET

Y

FETCH NEXT INSTRUCTION

N

IRET

STACK PC, X, A, CC

SET I BIT

Y

LOAD PC FROM INTERRUPT VECTOR

EXECUTE INSTRUCTION

RESTORE PC, X, A, CC FROM STACK

THIS CLEARS I BIT BY DEFAULT

19/84

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ST72101/ST72212/ST72213

Table 7. Interrupt Mapping

Source

Exit

from

HALT

Register

Label

Vector

Address

Priority

Order

Description

Flag

Block

RESET

TRAP

EI0

Reset

Software

N/A

yes

no

FFFEh-FFFFh

FFFCh-FFFDh

FFFAh-FFFBh

FFF8h-FFF9h

FFF6h-FFF7h

Highest

Priority

External Interrupt PA0:PA7

External Interrupt PB0:PB7, PC0:PC5

Not Used

yes

EI1

Transfer Complete

Mode Fault

SPIF

MODF

SPI

SPISR

TASR

no

FFF4h-FFF5h

Input Capture 1

ICF1_A

OCF1_A

ICF2_A

OCF2_A

TOF_A

Output Compare 1

Input Capture 2

TIMER A

FFF2h-FFF3h

FFF0h-FFF1h

FFEEh-FFEFh

Output Compare 2

Timer Overflow

Not Used

Input Capture 1

ICF1_B

OCF1_B

ICF2_B

OCF2_B

TOF_B

Output Compare 1

Input Capture 2

1)

TIMER B

TBSR

no

Output Compare 2

Timer Overflow

FFECh-FFEDh

FFEAh-FFEBh

FFE8h-FFE9h

FFE6h-FFE7h

FFE4h-FFE5h

FFE2h-FFE3h

Not Used

Lowest

Priority

FFE0h-FFE1h

Note 1: Timer B is available on ST72212 only.

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ST72101/ST72212/ST72213

3.4 POWER SAVING MODES

3.4.1 Introduction

Figure 17. WAIT Flow Chart

There are three Power Saving modes. Slow Mode

is selected by setting the relevant bits in the Mis-

cellaneous register. Wait and Halt modes may be

entered using the WFI and HALT instructions.

WFI INSTRUCTION

3.4.2 Slow Mode

OSCILLATOR

ON

In Slow mode, the oscillator frequency can be di-

vided by a value defined in the Miscellaneous

Register. The CPU and peripherals are clocked at

this lower frequency. Slow mode is used to reduce

power consumption, and enables the user to adapt

clock frequency to available supply voltage.

PERIPH. CLOCK

CPU CLOCK

I-BIT

ON

OFF

CLEARED

3.4.3 Wait Mode

N

Wait mode places the MCU in a low power con-

sumption mode by stopping the CPU. All peripher-

als remain active. During Wait mode, the I bit (CC

Register) is cleared, so as to enable all interrupts.

All otherregisters and memory remain unchanged.

The MCU will remain in Wait mode until an Inter-

rupt or Reset occurs, whereupon the Program

Counter branches to the starting address of the In-

terrupt or Reset Service Routine.

RESET

N

Y

INTERRUPT

Y

OSCILLATOR

ON

PERIPH. CLOCK

CPU CLOCK

I-BIT

The MCU will remain in Wait mode until a Reset or

an Interrupt occurs, causing it to wake up.

ON

SET

Refer to Figure 17 below.

4096 CPU CLOCK

CYCLES DELAY

OSCILLATOR

ON

PERIPH. CLOCK

CPU CLOCK

I-BIT

ON

SET

FETCH RESET VECTOR

OR SERVICE INTERRUPT

Note: Before servicing an interrupt, the CC register is

pushed on the stack. The I-Bit is set during the inter-

rupt routine and cleared when the CC register is

popped.

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ST72101/ST72212/ST72213

POWER SAVING MODES (Cont’d)

3.4.4 Halt Mode

Figure 18. HALT Flow Chart

The Halt mode is the MCU lowest power con-

sumption mode. The Halt mode is entered by exe-

cuting the HALT instruction. The internal oscillator

is then turned off, causing all internal processing to

be stopped, including the operation of the on-chip

peripherals. The Halt mode cannot be used when

the watchdog is enabled, if the HALT instruction is

executed while the watchdog system is enabled, a

watchdog reset is generated thus resetting the en-

tire MCU.

When entering Halt mode, the I bit in the CC Reg-

ister is cleared so as to enable External Interrupts.

If an interrupt occurs, the CPU becomes active.

The MCU can exit the Halt mode upon reception of

an interrupt or a reset. Refer to the Interrupt Map-

ping Table. The oscillator is then turned on and a

stabilization time is provided before releasing CPU

operation. Thestabilization time is 4096 CPU clock

cycles.

HALT INSTRUCTION

Y

WDG

WATCHDOG

RESET

ENABLED?

N

OSCILLATOR

OFF

PERIPH. CLOCK

CPU CLOCK

I-BIT

OFF

CLEARED

N

After the start up delay, the CPU continues oper-

ation by servicing the interrupt which wakes it up or

by fetching the reset vector if a reset wakes it up.

RESET

N

EXTERNAL

INTERRUPT

Y

1)

Y

OSCILLATOR

ON

2)

PERIPH. CLOCK

CPU CLOCK

I-BIT

OFF

ON

SET

4096 CPU CLOCK

CYCLES DELAY

OSCILLATOR

ON

PERIPH. CLOCK

CPU CLOCK

I-BIT

ON

SET

FETCH RESET VECTOR

OR SERVICE INTERRUPT

1) or some specific interrupts

2) if reset PERIPH. CLOCK = ON ; if interrupt

PERIPH. CLOCK = OFF

Note: Before servicing an interrupt, the CC register is

pushed on the stack. The I-Bit is set during the inter-

rupt routine and cleared when the CC register is

popped.

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ST72101/ST72212/ST72213

3.5 MISCELLANEOUS REGISTER

The Miscellaneous register allows to select the

SLOW operating mode, the polarity of external in-

terrupt requests and to output the internal clock.

Bit 4:3 = PEI[1:0] External Interrupt EI0 Polarity

Option.

These bits are set and cleared by software. They

determine which event on EI0 causes the exter-

nal interrupt according to Table 9.

Register Address: 0020h

— Read/Write

Reset Value: 0000 0000 (00h)

Table 9. EI0 External Interrupt Polarity Options

7

0

MODE

PEI1

PEI0

PEI3 PEI2 MCO PEI1 PEI0

-

SMS

Falling edge and low level

(Reset state)

0

Bit 7:6 = PEI[3:2] External Interrupt EI1 Polarity

Falling edge only

Rising edge only

1

0

1

0

1

Option.

These bits are set and cleared by software. They

determine which event on EI1 causes the exter-

nal interrupt according to Table 8.

Rising and falling edge

Note: Any modification of one of these two bits re-

sets the interrupt request related to this interrupt

vector.

Table 8. EI1 External Interrupt Polarity Options

MODE

PEI3

PEI2

Falling edge and low level

(Reset state)

0

Bit 1:2 = Unused, always read at 0.

Warning: Software must write 1 to these bits for

compatibility with future products.

Falling edge only

Rising edge only

1

0

1

0

1

Rising and falling edge

Bit 0 = SMS Slow Mode Select

This bit is set and cleared by software.

Note: Any modification of one of these two bits re-

sets the interrupt request related to this interrupt

vector.

0- Normal mode - f

(Reset state)

= Oscillator frequency / 2

CPU

1- Slow mode - f

= Oscillator frequency /32

CPU

Bit 5 = MCO Main Clock Out

This bit is set and cleared by software. When set, it

enables the output of the Internal Clock on the

PC2 I/O port.

0 - PC2 is a general purpose I/O port.

1 - MCO alternate function (f

pin).

is output on PC2

CPU

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ST72101/ST72212/ST72213

4 ON-CHIP PERIPHERALS

4.1 I/O PORTS

4.1.1 Introduction

Interrupt function

The I/O ports offer different functional modes:

– transfer of data through digital inputs and outputs

and for specific pins:

When an I/O is configured in Input with Interrupt,

an event on this I/O can generate an external In-

terrupt request to the CPU. The interrupt polarity is

given independently according to the description

mentioned in the Miscellaneous register or in the

interrupt register (where available).

– analog signal input (ADC)

– alternate signal input/output for the on-chip pe-

ripherals.

Each pin can independently generate an Interrupt

request.

– external interrupt generation

Each external interrupt vector is linked to a dedi-

cated group of I/O port pins (see Interrupts sec-

tion). If several input pins are configured as inputs

to the same interrupt vector, their signals are logi-

cally ANDed before entering the edge/level detec-

tion block. For this reason if one of the interrupt

pins is tied low, it masks the other ones.

An I/O port is composed of up to 8 pins. Each pin

can be programmed independently as digital input

(with or without interrupt generation) or digital out-

put.

4.1.2 Functional Description

Each port is associated to 2 main registers:

– Data Register (DR)

4.1.2.2 Output Mode

The pin is configured in output mode by setting the

corresponding DDR register bit.

– Data Direction Register (DDR)

and some of them to an optional register:

– Option Register (OR)

In this mode, writing “0” or “1” to the DR register

applies this digital value to the I/O pin through the

latch. Then reading the DR register returns the

previously stored value.

Each I/O pin may be programmed using the corre-

sponding register bits in DDR and OR registers: bit

X corresponding to pin X of the port. The same cor-

respondence is used for the DR register.

Note: In this mode, the interrupt function is disa-

bled.

The following description takes into account the

OR register, for specific ports which do not provide

this register refer to the I/O Port Implementation

Section 4.1.3. The generic I/O block diagram is

shown on Figure 20.

4.1.2.3 Digital Alternate Function

When an on-chip peripheral is configured to use a

pin, the alternate function is automatically select-

ed. This alternate function takes priority over

standard I/O programming. When the signal is

coming from an on-chip peripheral, the I/O pin is

automatically configured in output mode (push-pull

or open drain according to the peripheral).

4.1.2.1 Input Modes

The input configuration is selected by clearing the

corresponding DDR register bit.

In this case, reading the DR register returns the

digital value applied to the external I/O pin.

When the signal is going to an on-chip peripheral,

the I/O pin has to be configured in input mode. In

this case, the pin’s state is also digitally readable

by addressing the DR register.

Different input modes can be selected by software

through the OR register.

Notes:

1. Input pull-up configuration can cause an unex-

pected value at the input of the alternate peripher-

al input.

2. When the on-chip peripheral uses a pin as input

and output, this pin must be configured as an input

(DDR = 0).

1. All the inputs are triggered by a Schmitt trigger.

2. When switching from input mode to output

mode, the DR register should be written first to

output the correct value as soon as the port is con-

figured as an output.

Warning: The alternate function must not be acti-

vated as long as the pin is configured as input with

interrupt, in order to avoid generating spurious in-

terrupts.

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ST72101/ST72212/ST72213

I/O PORTS (Cont’d)

4.1.2.4 Analog Alternate Function

4.1.3 I/O Port Implementation

When the pin is used as an ADC input the I/O must

be configured as input, floating. The analog multi-

plexer (controlled by the ADC registers) switches

the analog voltage present on the selected pin to

the common analog rail which is connected to the

ADC input.

The hardware implementation on each I/O port de-

pends on the settings in the DDR and OR registers

and specific feature of the I/O port such as ADC In-

put (see Figure 20) or true open drain. Switching

these I/O ports from one state to another should

be done in a sequence that prevents unwanted

side effects. Recommended safe transitions are il-

lustrated in Figure 19. Other transitions are poten-

tially risky and should be avoided, since they are

likely to present unwanted side-effects such as

spurious interrupt generation.

It is recommended not to change the voltage level

or loading on any port pin while conversion is in

progress. Furthermore it is recommended not to

have clocking pins located close to a selected an-

alog pin.

Warning: The analog input voltage level must be

within the limits stated in the Absolute Maximum

Ratings.

Figure 19. Recommended I/O State Transition Diagram

OUTPUT

push-pull

INPUT

no interrupt

OUTPUT

INPUT

with interrupt

open-drain

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ST72101/ST72212/ST72213

I/O PORTS (Cont’d)

Figure 20. I/O Block Diagram

ALTERNATE ENABLE

1

V

ALTERNATE

OUTPUT

DD

M

U

X

P-BUFFER

(SEE TABLE BELOW)

0

DR

LATCH

ALTERNATE

ENABLE

PULL-UP

V

DD

PULL-UP

CONDITION

DIODE

(SEE TABLE BELOW)

DDR

LATCH

PAD

OR

ANALOG ENABLE

(ADC)

LATCH

(SEE TABLE BELOW)

GND

ANALOG

SWITCH

OR SEL

(SEE NOTE BELOW)

DDR SEL

N-BUFFER

ALTERNATE

ENABLE

1

0

DR SEL

M

U

X

GND

ALTERNATE INPUT

CMOS

SCHMITT TRIGGER

POLARITY

SEL

FROM

OTHER

BITS

EXTERNAL

INTERRUPT

SOURCE (EIx)

Table 10. Port Mode Configuration

Configuration Mode

Pull-up

P-buffer

V

Diode

DD

Floating

Pull-up

0

1

0

1

Push-pull

not present in OTP

and EPROM devices

True Open Drain

not present

0

Open Drain (logic level)

0

1

Legend:

Notes:

– No OR Register on some ports (see register map).

– ADC Switch on ports with analog alternate functions.

0 -

1 -

present, not activated

present and activated

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ST72101/ST72212/ST72213

Table 11. Port Configuration

Input (DDR = 0)

OR = 1

Output (DDR = 1)

Port

Pin Name

OR = 0

OR = 1

True Open Drain,

High Sink Capability

Port A

PA0:PA7

Floating*

Floating with Interrupt

Reserved

Port B

Port C

PB0:PB7

PC0:PC5

Floating*

Pull-up with Interrupt

Open Drain (Logic level)

Push-pull

*Reset State

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ST72101/ST72212/ST72213

I/O PORTS (Cont’d)

4.1.4 Register Description

4.1.4.1 Data registers

4.1.4.3 Option registers

Port A Data Register (PADR)

Port B Data Register (PBDR)

Port C Data Register (PCDR)

Port A Option Register (PAOR)

Port B Option Register (PBOR)

Port C Option Register (PCOR)

Read/Write

Reset Value: 0000 0000 (00h)

Read/Write

Reset Value: 0000 0000 (00h) (no interrupt)

7

0

7

0

O7

O6

O5

O4

O3

O2

O1

O0

D7

D6

D5

D4

D3

D2

D1

D0

Bit 7:0 = O7-O0 Option Register 8 bits.

Bit 7:0 = D7-D0 Data Register 8 bits.

For specific I/O pins, this register is not implement-

ed. In this case the DDR register is enough to se-

lect the I/O pin configuration.

The DR register has a specific behaviour accord-

ing to the selected input/output configuration. Writ-

ing the DR register is always taken in account

even if the pin is configured as an input. Reading

the DR register returns either the DR register latch

content (pin configured as output) or the digital val-

ue applied to the I/O pin (pin configured as input).

The OR register allow to distinguish: in input mode

if the interrupt capability or the floating configura-

tion is selected, in output mode if the push-pull or

open drain configuration is selected.

Each bit is set and cleared by software.

Input mode:

4.1.4.2 Data direction registers

Port A Data Direction Register (PADDR)

Port B Data Direction Register (PBDDR)

Port C Data Direction Register (PCDDR)

0: floating input

1: input interrupt with or without pull-up

Output mode (only for PB0:PB7, PC0:PC5):

Read/Write

Reset Value: 0000 0000 (00h) (input mode)

0: output open drain (with P-Buffer inactivated)

1: output push-pull

7

0

Output mode (only for PA0:PA7):

0: output open drain

1: reserved

DD7

DD6

DD5

DD4

DD3 DD2

DD1

DD0

Bit 7:0 = DD7-DD0 Data Direction Register 8 bits.

The DDR register gives the input/output direction

configuration of the pins. Each bit is set and

cleared by software.

0: Input mode

1: Output mode

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ST72101/ST72212/ST72213

I/O PORTS (Cont’d)

Table 12. I/O Port Register Map and Reset Values

Address

(Hex.)

Register

Label

7

6

5

4

3

2

1

0

PCDR

D7

0

D6

0

D5

0

D4

0

D37

0

D2

0

D1

0

D0

0

0000h

0001h

0002h

0004h

0005h

0006h

0008h

0009h

000Ah

Reset Value

PCDDR

DD7

0

DD6

0

DD5

0

DD4

0

DD3

0

DD2

0

DD1

0

DD0

0

Reset Value

PCOR

O7

0

O6

0

O5

0

O4

0

O3

0

O2

0

O1

0

O0

0

Reset Value

PBDR

D7

0

D6

0

D5

0

D4

0

D37

0

D2

0

D1

0

D0

0

Reset Value

PBDDR

DD7

0

DD6

0

DD5

0

DD4

0

DD3

0

DD2

0

DD1

0

DD0

0

Reset Value

PBOR

O7

0

O6

0

O5

0

O4

0

O3

0

O2

0

O1

0

O0

0

Reset Value

PADR

D7

0

D6

0

D5

0

D4

0

D37

0

D2

0

D1

0

D0

0

Reset Value

PADDR

DD7

0

DD6

0

DD5

0

DD4

0

DD3

0

DD2

0

DD1

0

DD0

0

Reset Value

PAOR

O7

0

O6

0

O5

0

O4

0

O3

0

O2

0

O1

0

O0

0

Reset Value

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ST72101/ST72212/ST72213

4.2 WATCHDOG TIMER (WDG)

4.2.1 Introduction

4.2.2 Main Features

■ Programmable timer (64 increments of 12288

CPU cycles)

■ Programmable reset

The Watchdog timer is used to detect the occur-

rence of a software fault, usually generated by ex-

ternal interference or by unforeseen logical condi-

tions, which causes the application program to

abandon its normal sequence. The Watchdog cir-

cuit generates an MCU reset on expiry of a pro-

grammed time period, unless the program refresh-

es the counter’s contents before the T6 bit be-

comes cleared.

■ Reset (if watchdog activated) after a HALT

instruction or when the T6 bit reaches zero

Figure 21. Watchdog Block Diagram

RESET

WATCHDOG CONTROL REGISTER (CR)

T5 T0

T6

WDGA

T1

T4

T2

T3

7-BIT DOWNCOUNTER

CLOCK DIVIDER

f

CPU

÷12288

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ST72101/ST72212/ST72213

WATCHDOG TIMER (Cont’d)

4.2.3 Functional Description

4.2.4 Low Power Modes

The counter value stored in the CR register (bits

T6:T0), is decremented every 12,288 machine cy-

cles, and the length of the timeout period can be

programmed by the user in 64 increments.

Mode

Description

WAIT

No effect on Watchdog.

Immediate reset generation as soon as

the HALT instruction is executed if the

Watchdog is activated (WDGA bit is

set).

If the watchdog is activated (the WDGA bit is set)

and when the 7-bit timer (bits T6:T0) rolls over

from 40h to 3Fh (T6 becomes cleared), it initiates

a reset cycle pulling low the reset pin for typically

500ns.

HALT

The application program must write in the CR reg-

ister at regular intervals during normal operation to

prevent an MCU reset. The value to be stored in

the CR register must be between FFh and C0h

(see Table 13):

4.2.5 Interrupts

None.

4.2.6 Register Description

CONTROL REGISTER (CR)

Read/Write

– The WDGA bit is set (watchdog enabled)

– The T6 bit is set to prevent generating an imme-

diate reset

Reset Value: 0111 1111 (7Fh)

– TheT5:T0 bits contain the number of increments

which represents the time delay before the

watchdog produces a reset.

7

0

WDGA T6

T5

T4

T3

T2

T1

T0

Table 13. Watchdog Timing (f

= 8 MHz)

CPU

CR Register

initial value

WDG timeout period

(ms)

Bit 7 = WDGA Activation bit.

This bit is set by software and only cleared by

hardware after a reset. When WDGA = 1, the

watchdog can generate a reset.

Max

Min

FFh

C0h

98.304

1.536

0: Watchdog disabled

1: Watchdog enabled

Notes: Following a reset, the watchdog is disa-

bled. Once activated it cannot be disabled, except

by a reset.

Bit 6:0 = T[6:0] 7-bit timer (MSB to LSB).

These bits contain the decremented value. A reset

is produced when it rolls over from 40h to 3Fh (T6

becomes cleared).

The T6 bit can be used to generate a software re-

set (the WDGA bit is set and the T6 bit is cleared).

If the watchdog is activated, the HALT instruction

will generate a Reset.

Table 14. Watchdog Timer Register Map and Reset Values

Address

(Hex.)

Register

Label

7

6

5

4

3

2

1

0

WDGCR

Reset Value

WDGA

0

T6

1

T5

1

T4

1

T3

1

T2

1

T1

1

T0

1

0024h

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ST72101/ST72212/ST72213

4.3 16-BIT TIMER

4.3.1 Introduction

The timer consists of a 16-bit free-running counter

driven by a programmable prescaler.

4.3.3 Functional Description

4.3.3.1 Counter

It may be used for a variety of purposes, including

pulse length measurement of up to two input sig-

nals (input capture) or generation of up to two out-

put waveforms (output compare and PWM).

The principal block of the Programmable Timer is

a 16-bit free running increasing counter and its as-

sociated 16-bit registers:

Counter Registers

Pulse lengths and waveform periods can be mod-

ulated from a few microseconds to several milli-

seconds using the timer prescaler and the CPU

clock prescaler.

– Counter High Register (CHR) is the most sig-

nificant byte (MSB).

– Counter Low Register (CLR) is the least sig-

nificant byte (LSB).

Alternate Counter Registers

4.3.2 Main Features

– Alternate Counter High Register (ACHR) is the

most significant byte (MSB).

■ Programmable prescaler:f_CPUdividedby2, 4or 8.

■ Overflow status flag and maskable interrupt

■ External clock input (must be at least 4 times

slower thanthe CPUclock speed)with the choice

of active edge

– Alternate Counter Low Register (ACLR) is the

least significant byte (LSB).

These two read-only 16-bit registers contain the

same value but with the difference that reading the

ACLR register does not clear the TOF bit (overflow

flag), (see note at the end of paragraph titled 16-bit

read sequence).

■ Output compare functions with

– 2 dedicated 16-bit registers

– 2 dedicated programmable signals

– 2 dedicated status flags

Writing in the CLR register or ACLR register resets

the free running counter to the FFFCh value.

– 1 dedicated maskable interrupt

■ Input capture functions with

The timer clock depends on the clock control bits

of the CR2 register, as illustrated in Table 15. The

value in the counter register repeats every

131.072, 262.144 or 524.288 internal processor-

clock cycles depending on the CC1 and CC0 bits.

– 2 dedicated 16-bit registers

– 2 dedicated active edge selection signals

– 2 dedicated status flags

– 1 dedicated maskable interrupt

■ Pulse width modulation mode (PWM)

■ One pulse mode

■ 5 alternate functionson I/O ports (ICAP1,ICAP2,

OCMP1, OCMP2, EXTCLK)*

The Block Diagram is shown in Figure 22.

*Note: Some external pins are not available on all

devices. Refer to the device pin out description.

When reading an input signal which is not availa-

ble on an external pin, the value will always be ‘1’.

32/84

32

ST72101/ST72212/ST72213

16-BIT TIMER (Cont’d)

Figure 22. Timer Block Diagram

ST7 INTERNAL BUS

f

CPU

MCU-PERIPHERAL INTERFACE

8 low

8-bit

8 high

8

buffer

EXEDG

h

w

h

w

h

w

h

low

16

INPUT

CAPTURE

REGISTER

INPUT

CAPTURE

REGISTER

OUTPUT

COMPARE

REGISTER

OUTPUT

COMPARE

REGISTER

16 BIT

FREE RUNNING

1/2

1/4

1/8

COUNTER

1

2

COUNTER

ALTERNATE

REGISTER

16

CC1 CC0

TIMER INTERNAL BUS

16

OVERFLOW

DETECT

EXTCLK

EDGE DETECT

CIRCUIT1

OUTPUT COMPARE

CIRCUIT

ICAP1

ICAP2

CIRCUIT

6

EDGE DETECT

CIRCUIT2

OCMP1

OCMP2

LATCH1

LATCH2

ICF1 OCF1 TOF ICF2 OCF2

0

SR

ICIE OCIE TOIE FOLV2 FOLV1OLVL2 IEDG1 OLVL1

OC1E

OPM PWM CC1 CC0 IEDG2 EXEDG

OC2E

CR1

CR2

TIMER INTERRUPT

33/84

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ST72101/ST72212/ST72213

16-BIT TIMER (Cont’d)

16-bit read sequence: (from either the Counter

Register or the Alternate Counter Register).

Clearing the overflow interrupt request is done in

two steps:

1. Reading the SR register while the TOF bit is set.

2. An access (read or write) to the CLR register.

Beginning of the sequence

Notes: The TOF bit is not cleared by accesses to

ACLR register. This feature allows simultaneous

use of the overflow function and reads of the free

running counter at random times (for example, to

measure elapsed time) without the risk of clearing

the TOF bit erroneously.

Read MSB

At t0

LSB is buffered

Other

instructions

Returns the buffered

LSB value at t0

The timer is not affected by WAIT mode.

Read LSB

At t0 +∆t

In HALT mode, the counter stops counting until the

mode is exited. Counting then resumes from the

previous count (MCU awakened by an interrupt) or

from the reset count (MCU awakened by a Reset).

Sequence completed

The user must read the MSB first, then the LSB

value is buffered automatically.

This buffered value remains unchanged until the

16-bit read sequence is completed, even if the

user reads the MSB several times.

4.3.3.2 External Clock

The external clock (where available) is selected if

CC0=1 and CC1=1 in CR2 register.

After a complete reading sequence, if only the

CLR register or ACLR register are read, they re-

turn the LSB of the count value at the time of the

read.

The status of the EXEDG bit determines the type

of level transition on the external clock pin EXT-

CLK that will trigger the free running counter.

The counter is synchronised with the falling edge

of the internal CPU clock.

Whatever the timer mode used (input capture, out-

put compare, one pulse mode or PWM mode) an

overflow occurs when the counter rolls over from

FFFFh to 0000h then:

At least four falling edges of the CPU clock must

occur between two consecutive active edges of

the external clock; thus the external clock frequen-

cy must be less than a quarter of the CPU clock

frequency.

– The TOF bit of the SR register is set.

– A timer interrupt is generated if:

– TOIE bit of the CR1 register is set and

– I bit of the CC register is cleared.

If one of these conditions is false, the interrupt re-

mains pending to be issued as soon as they are

both true.

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ST72101/ST72212/ST72213

16-BIT TIMER (Cont’d)

Figure 23. Counter Timing Diagram, internal clock divided by 2

CPU CLOCK

INTERNAL RESET

TIMER CLOCK

FFFD FFFE FFFF 0000 0001 0002 0003

COUNTER REGISTER

OVERFLOW FLAG TOF

Figure 24. Counter Timing Diagram, internal clock divided by 4

CPU CLOCK

INTERNAL RESET

TIMER CLOCK

FFFC

FFFD

0000

0001

COUNTER REGISTER

OVERFLOW FLAG TOF

Figure 25. Counter Timing Diagram, internal clock divided by 8

CPU CLOCK

INTERNAL RESET

TIMER CLOCK

0000

FFFC

FFFD

COUNTER REGISTER

OVERFLOW FLAG TOF

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ST72101/ST72212/ST72213

16-BIT TIMER (Cont’d)

4.3.3.3 Input Capture

When an input capture occurs:

– ICFi bit is set.

In this section, the index, i, may be 1 or 2.

The two input capture 16-bit registers (IC1R and

IC2R) are used to latch the value of the free run-

ning counter after a transition detected by the

ICAPi pin (see figure 5).

– The ICiR register contains the value of the free

running counter on the active transition on the

ICAPi pin (see Figure 27).

– A timer interrupt is generated if the ICIE bit is set

and the I bit is cleared in the CC register. Other-

wise, the interrupt remains pending until both

conditions become true.

MS Byte

ICiHR

LS Byte

ICiLR

ICiR

Clearing the Input Capture interrupt request is

done in two steps:

ICi register is a read-only register.

The active transition is software programmable

through the IEDGi bit of the Control Register (CRi).

1. Reading the SR register while the ICFi bit is set.

2. An access (read or write) to the ICiLR register.

Timing resolution is one count of the free running

counter: (f

/(CC1.CC0)).

CPU

Notes:

Procedure:

1. After reading the ICiHR register, transfer of

input capture data is inhibited until the ICiLR

register is also read.

To use the input capture function select the follow-

ing in the CR2 register:

2. The ICiR register always contains the free run-

ning counter value which corresponds to the

most recent input capture.

– Select the timer clock (CC1-CC0) (see Table

15).

– Select the edge of the active transition on the

ICAP2 pin with the IEDG2 bit (the ICAP2 pin

must be configured as floating input).

3. The 2 input capture functions can be used

together even if the timer also uses the output

compare mode.

And select the following in the CR1 register:

4. In One pulse Mode and PWM mode only the

input capture 2 can be used.

– Set the ICIE bit to generate an interrupt after an

input capture coming from both the ICAP1 pin or

the ICAP2 pin

5. The alternate inputs (ICAP1 & ICAP2) are

always directly connected to the timer. So any

transitions on these pins activate the input cap-

ture process.

– Select the edge of the active transition on the

ICAP1 pin with the IEDG1 bit (the ICAP1pin must

be configured as floating input).

6. Moreover if one of the ICAPi pin is configured

as an input and the second one as an output,

an interrupt can be generated if the user toggle

the output pin and if the ICIE bit is set.

7. The TOF bit can be used with interrupt in order

to measure event that go beyond the timer

range (FFFFh).

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ST72101/ST72212/ST72213

16-BIT TIMER (Cont’d)

Figure 26. Input Capture Block Diagram

ICAP1

(Control Register 1) CR1

IEDG1

EDGE DETECT

CIRCUIT2

EDGE DETECT

CIRCUIT1

ICIE

ICAP2

(Status Register) SR

ICF1

ICF2

0

IC2R Register

IC1R Register

(Control Register 2) CR2

16-BIT

16-BIT FREE RUNNING

COUNTER

IEDG2

CC0

CC1

Figure 27. Input Capture Timing Diagram

TIMER CLOCK

FF01

FF02

FF03

COUNTER REGISTER

ICAPi PIN

ICAPi FLAG

FF03

ICAPi REGISTER

Note: Active edge is rising edge.

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ST72101/ST72212/ST72213

16-BIT TIMER (Cont’d)

4.3.3.4 Output Compare

∆t f

In this section, the index, i, may be 1 or 2.

* CPU

PRESC

∆ OCiR =

This function can be used to control an output

waveform or indicating when a period of time has

elapsed.

Where:

∆t

= Desired output compare period (in sec-

onds)

When a match is found between the Output Com-

pare register and the free running counter, the out-

put compare function:

f

= Internal clock frequency

CPU

= Timer prescaler factor (2, 4 or 8 de-

pending on CC1-CC0 bits, see Table

15)

PRESC

– Assigns pins with a programmable value if the

OCIE bit is set

– Sets a flag in the status register

– Generates an interrupt if enabled

Clearing the output compare interrupt request is

done by:

Two 16-bit registers Output Compare Register 1

(OC1R) and Output Compare Register 2 (OC2R)

contain the value to be compared to the free run-

ning counter each timer clock cycle.

1. Reading the SR register while the OCFi bit is

set.

2. An access (read or write) to the OCiLR register.

The following procedure is recommended to pre-

vent the OCFi bit from being set between the time

it is read and the write to the OCiR register:

MS Byte

OCiHR

LS Byte

OCiLR

OCiR

– Write to the OCiHR register (further compares

are inhibited).

These registers are readable and writable and are

not affected by the timer hardware. A reset event

changes the OCiR value to 8000h.

– Read the SR register (first step of the clearance

of the OCFi bit, which may be already set).

Timing resolution is one count of the free running

counter: (f

).

– Write to the OCiLR register (enables the output

compare function and clears the OCFi bit).

CPU/(CC1.CC0)

Procedure:

Notes:

To use the output compare function, select the fol-

lowing in the CR2 register:

1. After a processor write cycle to the OCiHR reg-

ister, the output compare function is inhibited

until the OCiLR register is also written.

– Set the OCiE bit if an output is needed then the

OCMPi pin is dedicated to the output compare i

function.

2. If the OCiE bit is not set, the OCMPi pin is a

general I/O port and the OLVLi bit will not

appear when a match is found but an interrupt

could be generated if the OCIE bit is set.

– Select the timer clock (CC1-CC0) (see Table

15).

And select the following in the CR1 register:

3. When the clock is divided by 2, OCFi and

OCMPi are set while the counter value equals

the OCiR register value (see Figure 29, on

page 39). This behaviour is the same in OPM

or PWM mode.

– Select the OLVLi bit to applied to the OCMPi pins

after the match occurs.

– Set the OCIE bit to generate an interrupt if it is

needed.

When the clock is divided by 4, 8 or in external

clock mode, OCFi and OCMPi are set while the

counter value equals the OCiR register value

plus 1 (see Figure 30, on page 39).

When a match is found:

– OCFi bit is set.

– The OCMPi pin takes OLVLi bit value (OCMPi

pin latch is forced low during reset and stays low

until valid compares change it to a high level).

4. The output compare functions can be used both

for generating external events on the OCMPi

pins even if the input capture mode is also

used.

– A timer interrupt is generated if the OCIE bit is

set in the CR2 register and the I bit is cleared in

the CC register (CC).

5. The value in the 16-bit OCiR register and the

OLVi bit should be changed after each suc-

cessful comparison in order to control an output

waveform or establish a new elapsed timeout.

The OCiR register value required for a specific tim-

ing application can be calculated using the follow-

ing formula:

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ST72101/ST72212/ST72213

16-BIT TIMER (Cont’d)

Figure 28. Output Compare Block Diagram

16 BIT FREE RUNNING

OC1E

CC1 CC0

OC2E

COUNTER

(Control Register 2) CR2

(Control Register 1) CR1

16-bit

OUTPUT COMPARE

CIRCUIT

Latch

1

OCIE

OLVL2

OLVL1

OCMP1

16-bit

Latch

2

OCMP2

OC1R Register

OCF1

OCF2

0

OC2R Register

(Status Register) SR

Figure 29. Output Compare Timing Diagram, Internal Clock Divided by 2

INTERNAL CPU CLOCK

TIMER CLOCK

2ECF 2ED0 2ED1 2ED2

2ED3

2ED4

2ED3

COUNTER

OUTPUT COMPARE REGISTER

OUTPUT COMPARE FLAG (OCFi)

OCMPi PIN (OLVLi=1)

Figure 30. Output Compare Timing Diagram, Internal Clock Divided by 4

INTERNAL CPU CLOCK

TIMER CLOCK

2ECF 2ED0 2ED1 2ED2

2ED3

2ED4

2ED3

COUNTER

OUTPUT COMPARE REGISTER

COMPARE REGISTER LATCH

OCFi AND OCMPi PIN (OLVLi=1)

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ST72101/ST72212/ST72213

16-BIT TIMER (Cont’d)

4.3.3.5 Forced Compare

In this section i may represent 1 or 2.

The following bits of the CR1 register are used:

One pulse mode cycle

OCMP1 = OLVL2

When

event occurs

on ICAP1

FOLV2 FOLV1 OLVL2

OLVL1

Counter is reset

to FFFCh

When the FOLVi bit is set by software, the OLVLi

bit is copied to the OCMPi pin. The OLVi bit has to

be toggled in order to toggle the OCMPi pin when

it is enabled (OCiE bit=1). The OCFi bit is then not

set by hardware, and thus no interrupt request is

generated.

ICF1 bit is set

When

Counter

= OC1R

OCMP1 = OLVL1

FOLVLi bits have no effect in both one pulse mode

and PWM mode.

Then, on a valid event on the ICAP1 pin, the coun-

ter is initialized to FFFCh and OLVL2 bit is loaded

on the OCMP1 pin, the ICF1 bit is set and the val-

ue FFFDh is loaded in the IC1R register.

4.3.3.6 One Pulse Mode

One Pulse mode enables the generation of a

pulse when an external event occurs. This mode is

selected via the OPM bit in the CR2 register.

When the value of the counter is equal to the value

of the contents of the OC1R register, the OLVL1

bit is output on the OCMP1 pin, (See Figure 31).

The one pulse mode uses the Input Capture1

function and the Output Compare1 function.

Procedure:

Notes:

To use one pulse mode:

1. The OCF1 bit cannot be set by hardware in one

pulse mode but the OCF2 bit can generate an

Output Compare interrupt.

1. Load the OC1R register with the value corre-

sponding to the length of the pulse (see the for-

mula in Section 4.3.3.7).

2. The ICF1 bit is set when an active edge occurs

and can generate an interrupt if the ICIE bit is

set.

2. Select the following in the CR1 register:

– Using the OLVL1 bit, select the level to be ap-

plied to the OCMP1 pin after the pulse.

3. When the Pulse Width Modulation (PWM) and

One Pulse Mode (OPM) bits are both set, the

PWM mode is the only active one.

– Using the OLVL2 bit, select the level to be ap-

plied to the OCMP1 pin during the pulse.

4. If OLVL1=OLVL2 a continuous signal will be

seen on the OCMP1 pin.

– Select the edge of the active transition on the

ICAP1 pin with the IEDG1 bit (the ICAP1 pin

must be configured as floating input).

5. The ICAP1 pin can not be used to perform input

capture. The ICAP2 pin can be used to perform

input capture (ICF2 can be set and IC2R can be

loaded) but the user must take care that the

counter is reset each time a valid edge occurs

on the ICAP1 pin and ICF1 can also generates

interrupt if ICIE is set.

3. Select the following in the CR2 register:

– Set the OC1E bit, the OCMP1 pin is then ded-

icated to the Output Compare 1 function.

– Set the OPM bit.

– Select the timer clock CC1-CC0 (see Table

15).

6. When the one pulse mode is used OC1R is

dedicated to this mode. Nevertheless OC2R

and OCF2 can be used to indicate a period of

time has been elapsed but cannot generate an

output waveform because the level OLVL2 is

dedicated to the one pulse mode.

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ST72101/ST72212/ST72213

Figure 31. One Pulse Mode Timing Example

....

FFFC FFFD FFFE

2ED0 2ED1 2ED2

2ED3

FFFC FFFD

COUNTER

ICAP1

OLVL2

OLVL1

OLVL2

OCMP1

compare1

Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1

Figure 32. Pulse Width Modulation Mode Timing Example

34E2 FFFC FFFD FFFE

2ED0 2ED1 2ED2

34E2 FFFC

COUNTER

OCMP1

OLVL2

OLVL1

OLVL2

compare2

compare1

compare2

Note: OC1R=2ED0h, OC2R=34E2, OLVL1=0, OLVL2= 1

41/84

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ST72101/ST72212/ST72213

16-BIT TIMER (Cont’d)

4.3.3.7 Pulse Width Modulation Mode

The Output Compare 2 event causes the counter

to be initialized to FFFCh (See Figure 32).

Pulse Width Modulation (PWM) mode enables the

generation of a signal with a frequency and pulse

length determined by the value of the OC1R and

OC2R registers.

Pulse Width Modulation cycle

When

The pulse width modulation mode uses the com-

plete Output Compare 1 function plus the OC2R

register, and so these functionality can not be

used when the PWM mode is activated.

Counter

= OC1R

OCMP1 = OLVL1

Procedure

OCMP1 = OLVL2

To use pulse width modulation mode:

When

Counter

= OC2R

Counter is reset

to FFFCh

1. Load the OC2R register with the value corre-

sponding to the period of the signal.

2. Load the OC1R register with the value corre-

sponding to the length of the pulse if (OLVL1=0

and OLVL2=1).

ICF1 bit is set

Notes:

3. Select the following in the CR1 register:

1. After a write instruction to the OCiHR register,

the output compare function is inhibited until the

OCiLR register is also written.

– Using the OLVL1 bit, select the level to be ap-

plied to the OCMP1 pin after a successful

comparison with OC1R register.

Therefore the Input Capture 1 function is inhib-

ited but the Input Capture 2 is available.

– Using the OLVL2 bit, select the level to be ap-

plied to the OCMP1 pin after a successful

comparison with OC2R register.

2. The OCF1 and OCF2 bits cannot be set by

hardware in PWM mode therefore the Output

Compare interrupt is inhibited.

4. Select the following in the CR2 register:

– Set OC1E bit: the OCMP1 pin is then dedicat-

ed to the output compare 1 function.

3. The ICF1 bit is set by hardware when the coun-

ter reaches the OC2R value and can produce a

timer interrupt if the ICIE bit is set and the I bit is

cleared.

– Set the PWM bit.

– Select the timer clock (CC1-CC0) (see Table

15).

4. In PWM mode the ICAP1 pin can not be used

to perform input capture because it is discon-

nected to the timer. The ICAP2 pin can be used

to perform input capture (ICF2 can be set and

IC2R can be loaded) but the user must take

care that the counter is reset each period and

ICF1 can also generates interrupt if ICIE is set.

If OLVL1=1 and OLVL2=0 the length of the posi-

tive pulse is the difference between the OC2R and

OC1R registers.

If OLVL1=OLVL2 a continuous signal will be seen

on the OCMP1 pin.

The OCiR register value required for a specific tim-

ing application can be calculated using the follow-

ing formula:

5. When the Pulse Width Modulation (PWM) and

One Pulse Mode (OPM) bits are both set, the

PWM mode is the only active one.

t _*f

CPU

PRESC

- 5

OCiR Value =

Where:

t

= Desired output compare period (in sec-

onds)

f

= Internal clock frequency

CPU

= Timer prescaler factor (2, 4 or 8 de-

pending on CC1-CC0 bits, see Table

15)

PRESC

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ST72101/ST72212/ST72213

16-BIT TIMER (Cont’d)

4.3.4 Low Power Modes

Mode

Description

No effect on 16-bit Timer.

Timer interrupts cause the device to exit from WAIT mode.

WAIT

HALT

16-bit Timer registers are frozen.

In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous

count when the MCU is woken up by an interrupt with “exit from HALT mode” capability or from the counter

reset value when the MCU is woken up by a RESET.

If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is armed. Consequent-

ly, when the MCU is woken up by an interrupt with “exit from HALT mode” capability, the ICFi bit is set, and

the counter value present when exiting from HALT mode is captured into the ICiR register.

4.3.5 Interrupts

Enable

Control from

Bit

Exit

from

Halt

Event

Flag

Interrupt Event

Wait

Yes

Input Capture 1 event/Counter reset in PWM mode

Input Capture 2 event

ICF1

ICF2

No

ICIE

Output Compare 1 event (not available in PWM mode)

Output Compare 2 event (not available in PWM mode)

Timer Overflow event

OCF1

OCF2

TOF

OCIE

TOIE

Note: The 16-bit Timer interrupt events are con-

nected to the same interrupt vector (see Interrupts

chapter).

These events generate an interrupt if the corre-

sponding Enable Control Bit is set and the I-bit in

the CC register is reset (RIM instruction).

43/84

43

ST72101/ST72212/ST72213

16-BIT TIMER (Cont’d)

4.3.6 Register Description

Bit 4 = FOLV2 Forced Output Compare 2.

This bit is set and cleared by software.

0: No effect on the OCMP2 pin.

1:Forces the OLVL2 bit to be copied to the

OCMP2 pin, if the OC2E bit is set and even if

there is no successful comparison.

Each Timer is associated with three control and

status registers, and with six pairs of data registers

(16-bit values) relating to the two input captures,

the two output compares, the counter and the al-

ternate counter.

Bit 3 = FOLV1 Forced Output Compare 1.

This bit is set and cleared by software.

0: No effect on the OCMP1 pin.

CONTROL REGISTER 1 (CR1)

Read/Write

1: Forces OLVL1 to becopied to the OCMP1 pin, if

the OC1E bit is set and even if there is no suc-

cessful comparison.

Reset Value: 0000 0000 (00h)

7

0

ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1

Bit 2 = OLVL2 Output Level 2.

This bit is copied to the OCMP2 pin whenever a

successful comparison occurs with the OC2R reg-

ister and OCxE is set in the CR2 register. This val-

ue is copied to the OCMP1 pin in One Pulse Mode

and Pulse Width Modulation mode.

Bit 7 = ICIE Input Capture Interrupt Enable.

0: Interrupt is inhibited.

1: A timer interrupt is generated whenever the

ICF1 or ICF2 bit of the SR register is set.

Bit 6 = OCIE Output Compare Interrupt Enable.

0: Interrupt is inhibited.

1: A timer interrupt is generated whenever the

OCF1 or OCF2 bit of the SR register is set.

Bit 1 = IEDG1 Input Edge 1.

This bit determines which type of level transition

on the ICAP1 pin will trigger the capture.

0: A falling edge triggers the capture.

1: A rising edge triggers the capture.

Bit 5 = TOIE Timer Overflow Interrupt Enable.

0: Interrupt is inhibited.

1: A timer interrupt is enabled whenever the TOF

bit of the SR register is set.

Bit 0 = OLVL1 Output Level 1.

The OLVL1 bit is copied to the OCMP1 pin when-

ever a successful comparison occurs with the

OC1R register and the OC1E bit is set in the CR2

register.

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ST72101/ST72212/ST72213

16-BIT TIMER (Cont’d)

CONTROL REGISTER 2 (CR2)

Read/Write

Bit 4 = PWM Pulse Width Modulation.

0: PWM mode is not active.

1: PWM mode is active, the OCMP1 pin outputs a

programmable cyclic signal; the length of the

pulse depends on the value of OC1R register;

the period depends on the value of OC2R regis-

ter.

Reset Value: 0000 0000 (00h)

7

0

OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG

Bit 3, 2 = CC1-CC0 Clock Control.

Bit 7 = OC1E Output Compare 1 Pin Enable.

This bit is used only to output the signal from the

timer on the OCMP1 pin (OLV1 in Output Com-

pare mode, both OLV1 and OLV2 in PWM and

one-pulse mode). Whatever the value of the OC1E

bit, the Output Compare 1 function of the timer re-

mains active.

0: OCMP1 pin alternate function disabled (I/O pin

free for general-purpose I/O).

1: OCMP1 pin alternate function enabled.

The value of the timer clock depends on these bits:

Table 15. Clock Control Bits

Timer Clock

f_CPU/ 4

CC1

CC0

0

1

0

1

0

f_CPU/ 2

f_CPU/ 8

External Clock (where

available)

1

Bit 6 = OC2E Output Compare 2 Enable.

This bit is used only to output the signal from the

timer on the OCMP2 pin (OLV2 in Output Com-

pare mode). Whatever the value of the OC2E bit,

the Output Compare 2 function of the timer re-

mains active.

Bit 1 = IEDG2 Input Edge 2.

This bit determines which type of level transition

on the ICAP2 pin will trigger the capture.

0: A falling edge triggers the capture.

1: A rising edge triggers the capture.

0: OCMP2 pin alternate function disabled (I/O pin

free for general-purpose I/O).

Bit 0 = EXEDG External Clock Edge.

1: OCMP2 pin alternate function enabled.

This bit determines which type of level transition

on the external clock pin EXTCLK will trigger the

free running counter.

0: A falling edge triggers the free running counter.

1: A rising edge triggers the free running counter.

Bit 5 = OPM One Pulse Mode.

0: One Pulse Mode is not active.

1: One Pulse Mode is active, the ICAP1 pin can be

used to trigger one pulse on the OCMP1 pin; the

active transition is given by the IEDG1 bit. The

length of the generated pulse depends on the

contents of the OC1R register.

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ST72101/ST72212/ST72213

16-BIT TIMER (Cont’d)

STATUS REGISTER (SR)

Read Only

Bit 2-0 = Reserved, forced by hardware to 0.

INPUT CAPTURE 1 HIGH REGISTER (IC1HR)

Reset Value: 0000 0000 (00h)

The three least significant bits are not used.

7

Read Only

Reset Value: Undefined

This is an 8-bit read only register that contains the

high part of the counter value (transferred by the

input capture 1 event).

0

ICF1 OCF1 TOF ICF2 OCF2

0

7

0

Bit 7 = ICF1 Input Capture Flag 1.

0: No input capture (reset value).

MSB

LSB

1: An input capture has occurred or the counter

has reached the OC2R value in PWM mode. To

clear this bit, first read the SR register, then read

or write the low byte of the IC1R (IC1LR) regis-

ter.

INPUT CAPTURE 1 LOW REGISTER (IC1LR)

Read Only

Reset Value: Undefined

Bit 6 = OCF1 Output Compare Flag 1.

0: No match (reset value).

1: The content of the free running counter has

matched the content of the OC1R register. To

clear this bit, first read the SR register, then read

or write the low byte of the OC1R (OC1LR) reg-

ister.

This is an 8-bit read only register that contains the

low part of the counter value (transferred by the in-

put capture 1 event).

7

0

MSB

LSB

Bit 5 = TOF Timer Overflow.

OUTPUT COMPARE

(OC1HR)

1

HIGH REGISTER

0: No timer overflow (reset value).

1: The free running counter rolled over from FFFFh

to 0000h. To clear this bit, first read the SR reg-

ister, then read or write the low byte of the CR

(CLR) register.

Read/Write

Reset Value: 1000 0000 (80h)

This is an 8-bit register that contains the high part

of the value to be compared to the CHR register.

Note: Reading or writing the ACLR register does

not clear TOF.

7

0

Bit 4 = ICF2 Input Capture Flag 2.

MSB

LSB

0: No input capture (reset value).

1: An input capture has occurred.To clear this bit,

first read the SR register, then read or write the

low byte of the IC2R (IC2LR) register.

OUTPUT COMPARE

(OC1LR)

1

LOW REGISTER

Bit 3 = OCF2 Output Compare Flag 2.

0: No match (reset value).

1: The content of the free running counter has

matched the content of the OC2R register. To

clear this bit, first read the SR register, then read

or write the low byte of the OC2R (OC2LR) reg-

ister.

Read/Write

Reset Value: 0000 0000 (00h)

This is an 8-bit register that contains the low part of

the value to be compared to the CLR register.

7

0

MSB

LSB

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16-BIT TIMER (Cont’d)

OUTPUT COMPARE

(OC2HR)

2

HIGH REGISTER

ALTERNATE COUNTER HIGH REGISTER

(ACHR)

Read/Write

Reset Value: 1000 0000 (80h)

Read Only

Reset Value: 1111 1111 (FFh)

This is an 8-bit register that contains the high part

of the value to be compared to the CHR register.

This is an 8-bit register that contains the high part

of the counter value.

7

0

7

0

MSB

LSB

MSB

LSB

OUTPUT COMPARE

(OC2LR)

2

LOW REGISTER

ALTERNATE COUNTER LOW REGISTER

(ACLR)

Read/Write

Reset Value: 0000 0000 (00h)

Read Only

Reset Value: 1111 1100 (FCh)

This is an 8-bit register that contains the low part of

the value to be compared to the CLR register.

This is an 8-bit register that contains the low part of

the counter value. A write to this register resets the

counter. An access to this register after an access

to SR register does not clear the TOF bit in SR

register.

7

0

MSB

LSB

7

0

COUNTER HIGH REGISTER (CHR)

MSB

LSB

Read Only

Reset Value: 1111 1111 (FFh)

INPUT CAPTURE 2 HIGH REGISTER (IC2HR)

This is an 8-bit register that contains the high part

of the counter value.

Read Only

Reset Value: Undefined

7

0

This is an 8-bit read only register that contains the

high part of the counter value (transferred by the

Input Capture 2 event).

MSB

LSB

7

0

MSB

LSB

COUNTER LOW REGISTER (CLR)

Read Only

Reset Value: 1111 1100 (FCh)

This is an 8-bit register that contains the low part of

the counter value. A write to this register resets the

counter. An access to this register after accessing

the SR register clears the TOF bit.

INPUT CAPTURE 2 LOW REGISTER (IC2LR)

Read Only

Reset Value: Undefined

This is an 8-bit read only register that contains the

low part of the counter value (transferred by the In-

put Capture 2 event).

7

0

MSB

LSB

7

0

MSB

LSB

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16-BIT TIMER (Cont’d)

Table 16. 16-Bit Timer Register Map and Reset Values

Address

(Hex.)

Register

Name

7

6

5

4

3

2

1

0

TimerA: 32 CR1

ICIE

0

OCIE

TOIE

0

FOLV2

FOLV1

OLVL2

IEDG1

OLVL1

TimerB: 42 Reset Value

TimerA: 31 CR2

0

OC2E

0

PWM

0

CC1

0

OC1E

0

OPM

0

CC0

IEDG2

EXEDG

TimerB: 41 Reset Value

TimerA: 33 SR

0

-

0

-

0

-

ICF1

0

OCF1

0

TOF

0

ICF2

0

OCF2

0

TimerB: 43 Reset Value

TimerA: 34 IC1HR

TimerB: 44 Reset Value

TimerA: 35 IC1LR

0

MSB

-

LSB

-

MSB

-

LSB

-

TimerB: 45 Reset Value

TimerA: 36 OC1HR

TimerB: 46 Reset Value

TimerA: 37 OC1LR

TimerB: 47 Reset Value

TimerA: 3E OC2HR

TimerB: 4E Reset Value

TimerA: 3F OC2LR

TimerB: 4F Reset Value

TimerA: 38 CHR

MSB

1

-

0

-

0

-

0

-

0

-

0

-

0

LSB

0

MSB

0

-

0

-

0

-

0

-

0

-

0

-

0

LSB

0

MSB

1

-

0

-

0

-

0

-

0

-

0

-

0

LSB

0

MSB

0

-

0

-

0

-

0

-

0

-

0

-

0

LSB

0

MSB

1

LSB

1

0

1

TimerB: 48 Reset Value

TimerA: 39 CLR

MSB

1

LSB

0

TimerB: 49 Reset Value

TimerA: 3A ACHR

MSB

1

LSB

1

TimerB: 4A Reset Value

TimerA: 3B ACLR

MSB

1

LSB

0

1

-

1

-

1

-

1

-

1

-

0

-

TimerB: 4B Reset Value

TimerA: 3C IC2HR

MSB

-

LSB

-

TimerB: 4C Reset Value

TimerA: 3D IC2LR

MSB

-

LSB

-

TimerB: 4D Reset Value

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ST72101/ST72212/ST72213

4.4 SERIAL PERIPHERAL INTERFACE (SPI)

4.4.1 Introduction

4.4.3 General description

The Serial Peripheral Interface (SPI) allows full-

duplex, synchronous, serial communication with

external devices. An SPI system may consist of a

master and one or more slaves or a system in

which devices may be either masters or slaves.

The SPI is connected to external devices through

4 alternate pins:

– MISO: Master In Slave Out pin

– MOSI: Master Out Slave In pin

– SCK: Serial Clock pin

The SPI is normally used for communication be-

tween the microcontroller and external peripherals

or another microcontroller.

– SS: Slave select pin

Refer to the Pin Description chapter for the device-

specific pin-out.

A basic example of interconnections between a

single master and a single slave is illustrated on

Figure 33.

4.4.2 Main Features

The MOSI pins are connected together as are

MISO pins. In this way data is transferred serially

between master and slave (most significant bit

first).

■ Full duplex, three-wire synchronous transfers

■ Master or slave operation

■ Four master mode frequencies

■ Maximum slave mode frequency = fCPU/2.

■ Four programmable master bit rates

■ Programmable clock polarity and phase

■ End of transfer interrupt flag

When the master device transmits data to a slave

device via MOSI pin, the slave device responds by

sending data to the master device via the MISO

pin. This implies full duplex transmission with both

data out and data in synchronized with the same

clock signal (which is provided by the master de-

vice via the SCK pin).

■ Write collision flag protection

■ Master mode fault protection capability.

Thus, the byte transmitted is replaced by the byte

received and eliminates the need for separate

transmit-empty and receiver-full bits. A status flag

is used to indicate that the I/O operation is com-

plete.

Four possible data/clock timing relationships may

be chosen (see Figure 36) but master and slave

must be programmed with the same timing mode.

Figure 33. Serial Peripheral Interface Master/Slave

MASTER

SLAVE

MSBit

LSBit

MSBit

LSBit

MISO

MOSI

MISO

MOSI

8-BIT SHIFT REGISTER

SPI

CLOCK

GENERATOR

SCK

SS

SCK

SS

+5V

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SERIAL PERIPHERAL INTERFACE (Cont’d)

Figure 34. Serial Peripheral Interface Block Diagram

Internal Bus

Read

DR

IT

Read Buffer

request

MOSI

SR

MISO

8-Bit Shift Register

Write

MODF

WCOL

SPIF

-

SPI

STATE

CONTROL

SCK

SS

CR

SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0

MASTER

CONTROL

SERIAL

CLOCK

GENERATOR

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SERIAL PERIPHERAL INTERFACE (Cont’d)

4.4.4 Functional Description

Figure 33 shows the serial peripheral interface

(SPI) block diagram.

In this configuration the MOSI pin is a data output

and to the MISO pin is a data input.

This interface contains 3 dedicated registers:

– A Control Register (CR)

Transmit sequence

– A Status Register (SR)

The transmit sequence begins when a byte is writ-

ten the DR register.

– A Data Register (DR)

The data byte is parallel loaded into the 8-bit shift

register (from the internal bus) during a write cycle

and then shifted out serially to the MOSI pin most

significant bit first.

Refer to the CR, SR and DR registers in Section

4.4.7for the bit definitions.

4.4.4.1 Master Configuration

In a master configuration, the serial clock is gener-

ated on the SCK pin.

When data transfer is complete:

– The SPIF bit is set by hardware

Procedure

– An interrupt is generated if the SPIE bit is set

and the I bit in the CCR register is cleared.

– Select the SPR0 & SPR1 bits to define the se-

rial clock baud rate (see CR register).

During the last clock cycle the SPIF bit is set, a

copy of the data byte received in the shift register

is moved to a buffer. When the DR register is read,

the SPI peripheral returns this buffered value.

– Select the CPOL and CPHA bits to define one

of the four relationships between the data

transfer and the serial clock (see Figure 36).

– The SS pin must be connected to a high level

signal during the complete byte transmit se-

quence.

Clearing the SPIF bit is performed by the following

software sequence:

1. An access to the SR register while the SPIF bit

is set

– The MSTR and SPE bits must be set (they re-

main set only if the SS pin is connected to a

high level signal).

2. A write or a read of the DR register.

Note: While the SPIF bit is set, all writes to the DR

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SERIAL PERIPHERAL INTERFACE (Cont’d)

4.4.4.2 Slave Configuration

When data transfer is complete:

– The SPIF bit is set by hardware

In slave configuration, the serial clock is received

on the SCK pin from the master device.

– An interrupt is generated if SPIE bit is set and

I bit in CCR register is cleared.

The value of the SPR0 & SPR1 bits is not used for

the data transfer.

During the last clock cycle the SPIF bit is set, a

copy of the data byte received in the shift register

is moved to a buffer. When the DR register is read,

the SPI peripheral returns this buffered value.

Procedure

– For correct data transfer, the slave device

must be in the same timing mode as the mas-

ter device (CPOL and CPHA bits). See Figure

36.

Clearing the SPIF bit is performed by the following

software sequence:

1. An access to the SR register while the SPIF bit

is set.

– The SS pin must be connected to a low level

signal during the complete byte transmit se-

quence.

2. A write or a read of the DR register.

– Clear the MSTR bit and set the SPE bit to as-

sign the pins to alternate function.

Notes: While the SPIF bit is set, all writes to the

DR register are inhibited until the SR register is

read.

In this configuration the MOSI pin is a data input

and the MISO pin is a data output.

The SPIF bit can be cleared during a second

transmission; however, it must be cleared before

the second SPIF bit in order to prevent an overrun

condition (see Section 4.4.4.6).

Transmit Sequence

The data byte is parallel loaded into the 8-bit shift

register (from the internal bus) during a write cycle

and then shifted out serially to the MISO pin most

significant bit first.

Depending on the CPHA bit, the SS pin has to be

set to write to the DR register between each data

byte transfer to avoid a write collision (see Section

4.4.4.4).

The transmit sequence begins when the slave de-

vice receives the clock signal and the most signifi-

cant bit of the data on its MOSI pin.

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SERIAL PERIPHERAL INTERFACE (Cont’d)

4.4.4.3 Data Transfer Format

The master device applies data to its MOSI pin-

clock edge before the capture clock edge.

During an SPI transfer, data is simultaneously

transmitted (shifted out serially) and received

(shifted in serially). The serial clock is used to syn-

chronize the data transfer during a sequence of

eight clock pulses.

CPHA bit is set

The second edge on the SCK pin (falling edge if

the CPOL bit is reset, rising edge if the CPOL bit is

set) is the MSBit capture strobe. Data is latched on

the occurrence of the first clock transition.

The SS pin allows individual selection of a slave

device; the other slave devices that are not select-

ed do not interfere with the SPI transfer.

No write collision should occur even if the SS pin

stays low during a transfer of several bytes (see

Figure 35).

Clock Phase and Clock Polarity

Four possible timing relationships may be chosen

by software, using the CPOL and CPHA bits.

CPHA bit is reset

The CPOL (clock polarity) bit controls the steady

state value of the clock when no data is being

transferred. This bit affects both master and slave

modes.

The first edge on the SCK pin (falling edge if CPOL

bit is set, rising edge if CPOL bit is reset) is the

MSBit capture strobe. Data is latched on the oc-

currence of the second clock transition.

The combination between the CPOL and CPHA

(clock phase) bits selects the data capture clock

edge.

This pin must be toggled high and low between

each byte transmitted (see Figure 35).

To protect the transmission from a write collision a

low value on the SS pin of a slave device freezes

the data in its DR register and does not allow it to

be altered. Therefore the SS pin must be high to

write a new data byte in the DR without producing

a write collision.

Figure 36, shows an SPI transfer with the four

combinations of the CPHA and CPOL bits. The di-

agram may be interpreted as a master or slave

timing diagram where the SCK pin, the MISO pin,

the MOSI pin are directly connected between the

master and the slave device.

The SS pin is the slave device select input and can

be driven by the master device.

Figure 35. CPHA / SS Timing Diagram

Byte 3

Byte 2

MOSI/MISO

Master SS

Byte 1

Slave SS

(CPHA=0)

Slave SS

(CPHA=1)

VR02131A

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SERIAL PERIPHERAL INTERFACE (Cont’d)

Figure 36. Data Clock Timing Diagram

CPHA =1

CPOL = 1

CPOL = 0

Bit 4

Bit3

Bit 2

Bit 1

LSBit

MSBit

Bit 6

Bit 5

MISO

(from master)

Bit3

MOSI

(from slave)

SS

(to slave)

CAPTURE STROBE

CPHA =0

CPOL = 1

CPOL = 0

Bit 4

Bit3

Bit 2

Bit 1

LSBit

MSBit

Bit 6

Bit 5

MISO

(from master)

MSBit

Bit3

MOSI

(from slave)

SS

(to slave)

CAPTURE STROBE

Note: This figure should not be used as a replacement for parametric information.

Refer to the Electrical Characteristics chapter.

VR02131B

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SERIAL PERIPHERAL INTERFACE (Cont’d)

4.4.4.4 Write Collision Error

When the CPHA bit is reset:

A write collision occurs when the software tries to

write to the DR register while a data transfer is tak-

ing place with an external device. When this hap-

pens, the transfer continues uninterrupted; and

the software write will be unsuccessful.

Data is latched on the occurrence of the first clock

transition. The slave device does not have any

way of knowing when that transition will occur;

therefore, the slave device collision occurs when

software attempts to write the DR register after its

SS pin has been pulled low.

Write collisions can occur both in master and slave

mode.

For this reason, the SS pin must be high, between

each data byte transfer, to allow the CPU to write

in the DR register without generating a write colli-

sion.

Note: a ”read collision” will never occur since the

received data byte is placed in a buffer in which

access is always synchronous with the MCU oper-

ation.

In Slave mode

In Master mode

When the CPHA bit is set:

Collision in the master device is defined as a write

of the DR register while the internal serial clock

(SCK) is in the process of transfer.

The slave device will receive a clock (SCK) edge

prior to the latch of the first data transfer. This first

clock edge will freeze the data in the slave device

DR register and output the MSBit on to the exter-

nal MISO pin of the slave device.

The SS pin signal must be always high on the

master device.

The SS pin low state enables the slave device but

the output of the MSBit onto the MISO pin does

not take place until the first data transfer clock

edge.

WCOL bit

The WCOL bit in the SR register is set if a write

collision occurs.

No SPI interrupt is generated when the WCOL bit

is set (the WCOL bit is a status flag only).

Clearing the WCOL bit is done through a software

sequence (see Figure 37).

Figure 37. Clearing the WCOL bit (Write Collision Flag) Software Sequence

Clearing sequence after SPIF = 1 (end of a data byte transfer)

Read SR

1st Step

2nd Step

OR

THEN

SPIF =0

WCOL=0

SPIF =0

WCOL=0 if no transfer has started

WCOL=1 if a transfer has started

before the 2nd step

Read DR

Write DR

Clearing sequence before SPIF = 1 (during a data byte transfer)

Read SR

1st Step

THEN

Note: Writing in DR register in-

2nd Step

Read DR

stead of reading in it do not reset

WCOL bit

WCOL=0

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SERIAL PERIPHERAL INTERFACE (Cont’d)

4.4.4.5 Master Mode Fault

may be restored to their original state during or af-

ter this clearing sequence.

Master mode fault occurs when the master device

has its SS pin pulled low, then the MODF bit is set.

Hardware does not allow the user to set the SPE

and MSTR bits while the MODF bit is set except in

the MODF bit clearing sequence.

Master mode fault affects the SPI peripheral in the

following ways:

In a slave device the MODF bit can not be set, but

in a multi master configuration the device can be in

slave mode with this MODF bit set.

– The MODF bit is set and an SPI interrupt is

generated if the SPIE bit is set.

– The SPE bit is reset. This blocks all output

from the device and disables the SPI periph-

eral.

The MODF bit indicates that there might have

been a multi-master conflict for system control and

allows a proper exit from system operation to a re-

set or default system state using an interrupt rou-

tine.

– The MSTR bit is reset, thus forcing the device

into slave mode.

Clearing the MODF bit is done through a software

sequence:

4.4.4.6 Overrun Condition

An overrun condition occurs, when the master de-

vice has sent several data bytes and the slave de-

vice has not cleared the SPIF bit issuing from the

previous data byte transmitted.

1. A read or write access to the SR register while

the MODF bit is set.

2. A write to the CR register.

In this case, the receiver buffer contains the byte

sent after the SPIF bit was last cleared. A read to

the DR register returns this byte. All other bytes

are lost.

Notes: To avoid any multiple slave conflicts in the

case of a system comprising several MCUs, the

SS pin must be pulled high during the clearing se-

quence of the MODF bit. The SPE and MSTR bits

This condition is not detected by the SPI peripher-

al.

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SERIAL PERIPHERAL INTERFACE (Cont’d)

4.4.4.7 Single Master and Multimaster Configurations

There are two types of SPI systems:

– Single Master System

For more security, the slave device may respond

to the master with the received data byte. Then the

master will receive the previous byte back from the

slave device if all MISO and MOSI pins are con-

nected and the slave has not written its DR regis-

ter.

– Multimaster System

Single Master System

Other transmission security methods can use

ports for handshake lines or data bytes with com-

mand fields.

A typical single master system may be configured,

using an MCU as the master and four MCUs as

slaves (see Figure 38).

Multi-master System

The master device selects the individual slave de-

vices by using four pins of a parallel port to control

the four SS pins of the slave devices.

A multi-master system may also be configured by

the user. Transfer of master control could be im-

plemented using a handshake method through the

I/O ports or by an exchange of code messages

through the serial peripheral interface system.

The SS pins are pulled high during reset since the

master device ports will be forced to be inputs at

that time, thus disabling the slave devices.

The multi-master system is principally handled by

the MSTR bit in the CR register and the MODF bit

in the SR register.

Note: To prevent a bus conflict on the MISO line

the master allows only one slave device during a

transmission.

Figure 38. Single Master Configuration

SS

SCK

Slave

SCK

Slave

SCK

Slave

MCU

Slave

MCU

MOSI MISO

SCK

Master

MCU

5V

SS

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SERIAL PERIPHERAL INTERFACE (Cont’d)

4.4.5 Low Power Modes

Mode

Description

No effect on SPI.

WAIT

SPI interrupt events cause the device to exit from WAIT mode.

SPI registers are frozen.

HALT

In HALT mode, the SPI is inactive. SPI operation resumes when the MCU is woken up by an interrupt with

“exit from HALT mode” capability.

4.4.6 Interrupts

Enable

Control from

Bit

Exit

from

Halt

Event

Flag

Interrupt Event

Wait

Yes

SPI End of Transfer Event

Master Mode Fault Event

SPIF

No

SPIE

MODF

Note: The SPI interrupt events are connected to

the same interrupt vector (see Interrupts chapter).

They generate an interrupt if the corresponding

Enable Control Bit is set and the I-bit in the CC reg-

ister is reset (RIM instruction).

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SERIAL PERIPHERAL INTERFACE (Cont’d)

4.4.7 Register Description

CONTROL REGISTER (CR)

Read/Write

Bit 3 = CPOL Clock polarity.

This bit is set and cleared by software. This bit de-

termines the steady state of the serial Clock. The

CPOL bit affects both the master and slave

modes.

0: The steady state is a low value at the SCK pin.

1: The steady state is a high value at the SCK pin.

Reset Value: 0000xxxx (0xh)

7

0

SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0

Bit 7 = SPIE Serial peripheral interrupt enable.

This bit is set and cleared by software.

0: Interrupt is inhibited

1: An SPI interrupt is generated whenever SPIF=1

or MODF=1 in the SR register

Bit 2 = CPHA Clock phase.

This bit is set and cleared by software.

0: The first clock transition is the first data capture

edge.

1: The second clock transition is the first capture

edge.

Bit 6 = SPE Serial peripheral output enable.

This bit is set and cleared by software. It is also

cleared by hardware when, in master mode, SS=0

(see Section 4.4.4.5 Master Mode Fault).

0: I/O port connected to pins

Bit 1:0 = SPR[1:0] Serial peripheral rate.

These bits are set and cleared by software.Used

with the SPR2 bit, they select one of six baud rates

to be used as the serial clock when the device is a

master.

1: SPI alternate functions connected to pins

The SPE bit is cleared by reset, so the SPI periph-

eral is not initially connected to the external pins.

These 2 bits have no effect in slave mode.

Table 17. Serial Peripheral Baud Rate

Bit 5 = SPR2 Divider Enable.

Serial Clock

SPR2 SPR1 SPR0

this bit is set and cleared by software and it is

cleared by reset. It is used with the SPR[1:0] bits to

set the baud rate. Refer to Table 17.

0: Divider by 2 enabled

f

/2

/8

1

0

1

0

1

0

1

0

1

CPU

f

/16

/32

/64

CPU

1: Divider by 2 disabled

Bit 4 = MSTR Master.

f

/128

CPU

This bit is set and cleared by software. It is also

cleared by hardware when, in master mode, SS=0

(see Section 4.4.4.5 Master Mode Fault).

0: Slave mode is selected

1: Master mode is selected, the function of the

SCK pin changes from an input to an output and

the functions of the MISO and MOSI pins are re-

versed.

59/84

59

ST72101/ST72212/ST72213

SERIAL PERIPHERAL INTERFACE (Cont’d)

STATUS REGISTER (SR)

Read Only

DATA I/O REGISTER (DR)

Read/Write

Reset Value: 0000 0000 (00h)

Reset Value: Undefined

7

0

-

7

0

SPIF

WCOL

-

MODF

-

D7

D6

D5

D4

D3

D2

D1

D0

Bit 7 = SPIF Serial Peripheral data transfer flag.

This bit is set by hardware when a transfer has

been completed. An interrupt is generated if

SPIE=1 in the CR register. It is cleared by a soft-

ware sequence (an access to the SR register fol-

lowed by a read or write to the DR register).

0: Data transfer is in progress or has been ap-

proved by a clearing sequence.

The DR register is used to transmit and receive

data on the serial bus. In the master device only a

write to this register will initiate transmission/re-

ception of another byte.

Notes: During the last clock cycle the SPIF bit is

set, a copy of the received data byte in the shift

register is moved to a buffer. When the user reads

the serial peripheral data I/O register, the buffer is

actually being read.

1: Data transfer between the device and an exter-

nal device has been completed.

Warning:

Note: While the SPIF bit is set, all writes to the DR

register are inhibited.

A write to the DR register places data directly into

the shift register for transmission.

A write to the the DR register returns the value lo-

cated in the buffer and not the contents of the shift

register (See Figure 34 ).

Bit 6 = WCOL Write Collision status.

This bit is set by hardware when a write to the DR

register is done during a transmit sequence. It is

cleared by a software sequence (see Figure 37).

0: No write collision occurred

1: A write collision has been detected

Bit 5 = Unused.

Bit 4 = MODF Mode Fault flag.

This bit is set by hardware when the SS pin is

pulled low in master mode (see Section 4.4.4.5

Master Mode Fault). An SPI interrupt can be gen-

erated if SPIE=1 in the CR register. This bit is

cleared by a software sequence (An access to the

SR register while MODF=1 followed by a write to

the CR register).

0: No master mode fault detected

1: A fault in master mode has been detected

Bits 3-0 = Unused.

60/84

60

ST72101/ST72212/ST72213

SERIAL PERIPHERAL INTERFACE (Cont’d)

Table 18. SPI Register Map and Reset Values

Address

(Hex.)

Register

Name

7

6

5

4

3

2

1

0

DR

D7

x

D6

D5

D4

D3

D2

D1

D0

21

22

23

Reset Value

CR

x

SPE

0

x

MSTR

0

x

SPIE

0

SPR2

CPOL

CPHA

SPR1

SPR0

Reset Value

SR

0

-

x

-

x

-

x

-

x

-

SPIF

0

WCOL

0

MODF

0

Reset Value

0

61/84

61

ST72101/ST72212/ST72213

4.5 8-BIT A/D CONVERTER (ADC)

4.5.1 Introduction

4.5.2 Main Features

■ 8-bit conversion

The on-chip Analog to Digital Converter (ADC) pe-

ripheral is a 8-bit, successive approximation con-

verter with internal sample and hold circuitry. This

peripheral has up to 8 multiplexed analog input

channels (refer to device pin out description) that

allow the peripheral to convert the analog voltage

levels from up to 8 different sources.

■ Up to 8 channels with multiplexed input

■ Linear successive approximation

■ Data register (DR) which contains the results

■ Conversion complete status flag

■ On/off bit (to reduce consumption)

The result of the conversion is stored in a 8-bit

Data Register. The A/D converter is controlled

through a Control/Status Register.

The block diagram is shown in Figure 39.

Figure 39. ADC block diagram

-

ADON

0

-

CH2 CH1 CH0

COCO

(Control Status Register) CSR

AIN0

AIN1

AIN2

AIN3

AIN4

AIN5

AIN6

AIN7

SAMPLE

&

HOLD

ANALOG TO

DIGITAL

CONVERTER

ANALOG

MUX

f

CPU

AD6 AD5 AD4 AD3 AD2 AD1 AD0

(Data Register) DR

AD7

62/84

62

ST72101/ST72212/ST72213

8-BIT A/D CONVERTER (ADC) (Cont’d)

4.5.3 Functional Description

The accuracy of the conversion is described in the

Electrical Characteristics Section.

The high level reference voltage V

must be

DDA

connected externally to the V pin. The low level

Procedure:

DD

reference voltage V

must be connected exter-

SSA

Refer to the CSR and DR register description sec-

tion for the bit definitions.

nally to the V pin. In some devices (refer to de-

vice pin out description) high and low level refer-

SS

Each analog input pin must be configured as input,

no pull-up, no interrupt. Refer to the «I/O ports»

chapter. Using these pins as analog inputs does

not affect the ability of the port to be read as a logic

input.

ence voltages are internally connected to the V

DD

and V pins.

SS

Conversion accuracy may therefore be degraded

by voltage drops and noise in the event of heavily

loaded or badly decoupled power supply lines.

In the CSR register:

Figure 40. Recommended Ext. Connections

– Select the CH2 to CH0 bits to assign the ana-

log channel to convert. Refer to Table 19.

1K

– Set the ADON bit. Then the A/D converter is

enabled after a stabilization time (typically 30

µs). It then performs a continuous conversion

of the selected channel.

V

DD

DDA

SSA

0.1µF

ST7

When a conversion is complete

– The COCO bit is set by hardware.

– No interrupt is generated.

R

AIN

V

Px.x/AINx

AIN

– The result is in the DR register.

A write to the CSR register aborts the current con-

version, resets the COCO bit and starts a new

conversion.

Characteristics:

The conversion is monotonic, meaning the result

never decreases if the analog input does not and

never increases if the analog input does not.

4.5.4 Low Power Modes

Note: The A/D converter may be disabled by re-

setting the ADON bit. This feature allows reduced

power consumption when no conversion is need-

ed.

If input voltage is greater than or equal to V

(voltage reference high) then results = FFh (full

scale) without overflow indication.

DD

If input voltage ≤ V (voltage reference low) then

SS

the results = 00h.

Mode

Description

WAIT

No effect on A/D Converter

A/D Converter disabled.

The conversion time is 64 CPU clock cycles in-

cluding a sampling time of 31.5 CPU clock cycles.

R

is the maximum recommended impedance

AIN

After wakeup from Halt mode, the A/D

Converter requires a stabilisation time

before accurate conversions can be

performed.

for an analog input signal. If the impedance is too

high, this will result in a loss of accuracy due to

leakage and sampling not being completed in the

alloted time.

HALT

The A/D converter is linear and the digital result of

the conversion is given by the formula:

4.5.5 Interrupts

None

255 x Input Voltage

Digital result =

Reference Voltage

Where Reference Voltage is V - V

.

DD

SS

63/84

63

ST72101/ST72212/ST72213

8-BIT A/D CONVERTER (ADC) (Cont’d)

4.5.6 Register Description

CONTROL/STATUS REGISTER (CSR)

Read/Write

These bits are set and cleared by software. They

select the analog input to convert.

Table 19. Channel Selection

Reset Value: 0000 0000 (00h)

Pin*

AIN0

AIN1

AIN2

AIN3

AIN4

AIN5

AIN6

AIN7

CH2

0

CH1

0

CH0

0

7

0

1

COCO

-

ADON

0

-

CH2

CH1

CH0

0

1

0

1

Bit 7 = COCO Conversion Complete

1

0

This bit is set by hardware. It is cleared by soft-

ware reading the result in the DR register or writing

to the CSR register.

0: Conversion is not complete.

1: Conversion can be read from the DR register.

1

0

1

0

1

*IMPORTANT NOTE: The number of pins AND

the channel selection vary according to the device.

REFER TO THE DEVICE PINOUT).

Bit 6 = Reserved. Must always be cleared.

Bit 5 = ADON A/D converter On

DATA REGISTER (DR)

Read Only

This bit is set and cleared by software.

0: A/D converter is switched off.

1: A/D converter is switched on.

Reset Value: 0000 0000 (00h)

Note: a typically 30µs delay time is necessary for

the ADC to stabilize when the ADON bit is set.

7

0

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

Bit 4 = Reserved. Forced by hardware to 0.

Bit 3 = Reserved. Must always be cleared.

Bits 2-0: CH[2:0] Channel Selection

Bit 7:0 = AD[7:0] Analog Converted Value

This register contains the converted analog value

in the range 00h to FFh.

Reading this register reset the COCO flag.

Table 20. ADC Register Map

Address

(Hex.)

Register

Name

7

6

5

4

3

2

1

0

70

AD7

0

AD6

0

AD5

0

AD4

0

AD3

0

AD2

0

AD1

0

AD0

0

DR

Reset Value

71

COCO

0

-

0

ADON

0

-

0

CH2

0

CH1

0

CH0

0

CSR

Reset Value

64/84

64

ST72101/ST72212/ST72213

5 INSTRUCTION SET

5.1 ST7 ADDRESSING MODES

so, most of the addressing modes may be subdi-

vided in two sub-modes called long and short:

The ST7 Core features 17 different addressing

modes which can be classified in 7 main groups:

– Long addressing mode is more powerful be-

cause itcan use the full 64 Kbyte address space,

however it uses more bytes and more CPU cy-

cles.

Addressing Mode

Inherent

Example

nop

– Short addressing mode is less powerful because

it can generally only access page zero (0000h -

00FFh range), but the instruction size is more

compact, and faster. All memory to memory in-

structions use short addressing modes only

(CLR, CPL, NEG, BSET, BRES, BTJT, BTJF,

INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP)

Immediate

Direct

ld A,#$55

ld A,$55

ld A,($55,X)

ld A,([$55],X)

jrne loop

Indexed

Indirect

Relative

Bit operation

bset byte,#5

The ST7 Assembler optimizes the use of long and

short addressing modes.

The ST7 Instruction set is designed to minimize

the number of bytes required per instruction: To do

Table 21. ST7 Addressing Mode Overview

Pointer Pointer

Destination/

Source

Length

(Bytes)

Mode

Syntax

Address

(Hex.)

Size

(Hex.)

Inherent

Immediate

Short

nop

+ 0

+ 1

+ 2

ld A,#$55

ld A,$10

Direct

00..FF

Long

ld A,$1000

0000..FFFF

+ 0 (with X register)

+ 1 (with Y register)

No Offset

Direct

Indexed

ld A,(X)

00..FF

Short

Long

Short

Long

Short

Long

Relative

Bit

Direct

Indexed

ld A,($10,X)

ld A,($1000,X)

ld A,[$10]

00..1FE

+ 1

+ 2

+ 1

+ 2

+ 1

+ 2

+ 3

Direct

0000..FFFF

00..FF

Indirect

Direct

00..FF

byte

word

byte

word

ld A,[$10.w]

ld A,([$10],X)

0000..FFFF

00..1FE

Indexed

ld A,([$10.w],X) 0000..FFFF

1)

jrne loop

PC-128/PC+127

Indirect

Direct

jrne [$10]

PC-128/PC+127

00..FF

byte

bset $10,#7

bset [$10],#7

Bit

Indirect

Direct

00..FF

Bit

Relative

btjt $10,#7,skip 00..FF

btjt [$10],#7,skip 00..FF

Bit

Indirect

Note 1. At the time the instruction is executed, the Program Counter (PC) points to the instruction follow-

ing JRxx.

65/84

65

ST72101/ST72212/ST72213

ST7 ADDRESSING MODES (Cont’d)

5.1.1 Inherent

5.1.3 Direct

All Inherent instructions consist of a single byte.

The opcode fully specifies all the required informa-

tion for the CPU to process the operation.

In Direct instructions, the operands are referenced

by their memory address.

The direct addressing mode consists of two sub-

modes:

Inherent Instruction

Function

No operation

Direct (short)

NOP

The address is a byte, thus requires only one byte

after the opcode, but only allows 00 - FF address-

ing space.

TRAP

S/W Interrupt

Wait For Interrupt (Low Power

Mode)

WFI

Direct (long)

Halt Oscillator (Lowest Power

Mode)

HALT

The address is a word, thus allowing 64 Kbyte ad-

dressing space, but requires 2 bytes after the op-

code.

RET

Sub-routine Return

Interrupt Sub-routine Return

Set Interrupt Mask

Reset Interrupt Mask

Set Carry Flag

IRET

SIM

5.1.4 Indexed (No Offset, Short, Long)

RIM

In this mode, the operand is referenced by its

memory address, which is defined by the unsigned

addition of an index register (X or Y) with an offset.

SCF

RCF

Reset Carry Flag

Reset Stack Pointer

Load

The indirect addressing mode consists of three

sub-modes:

RSP

LD

Indexed (No Offset)

CLR

Clear

There is no offset, (no extra byte after the opcode),

and allows 00 - FF addressing space.

PUSH/POP

INC/DEC

TNZ

Push/Pop to/from the stack

Increment/Decrement

Test Negative or Zero

1 or 2 Complement

Byte Multiplication

Indexed (Short)

The offset is a byte, thus requires only one byte af-

ter the opcode and allows 00 - 1FE addressing

space.

CPL, NEG

MUL

Indexed (long)

SLL, SRL, SRA, RLC,

RRC

Shift and Rotate Operations

Swap Nibbles

The offset is a word, thus allowing 64 Kbyte ad-

dressing space and requires 2 bytes after the op-

code.

SWAP

5.1.2 Immediate

Immediate instructions have two bytes, the first

byte contains the opcode, the second byte con-

tains the the operand value. .

5.1.5 Indirect (Short, Long)

The required data byte to do the operation is found

by its memory address, located in memory (point-

er).

Immediate Instruction

Function

The pointer address follows the opcode. The indi-

rect addressing mode consists of two sub-modes:

LD

Load

CP

Compare

Indirect (short)

BCP

Bit Compare

The pointer address is a byte, the pointer size is a

byte, thus allowing 00 - FF addressing space, and

requires 1 byte after the opcode.

AND, OR, XOR

ADC, ADD, SUB, SBC

Logical Operations

Arithmetic Operations

Indirect (long)

The pointer address is a byte, the pointer size is a

word, thus allowing 64 Kbyte addressing space,

and requires 1 byte after the opcode.

66/84

66

ST72101/ST72212/ST72213

ST7 ADDRESSING MODES (Cont’d)

5.1.6 Indirect Indexed (Short, Long)

5.1.7 Relative mode (Direct, Indirect)

This is a combination of indirect and short indexed

addressing modes. The operand is referenced by

its memory address, which is defined by the un-

signed addition of an index register value (X or Y)

with a pointer value located in memory. The point-

er address follows the opcode.

This addressing mode is used to modify the PC

register value, by adding an 8-bit signed offset to

it.

Available Relative Direct/

Function

Indirect Instructions

JRxx

Conditional Jump

Call Relative

The indirect indexed addressing mode consists of

two sub-modes:

CALLR

Indirect Indexed (Short)

The pointer address is a byte, the pointer size is a

byte, thus allowing 00 - 1FE addressing space,

and requires 1 byte after the opcode.

The relative addressing mode consists of two sub-

modes:

Relative (Direct)

The offset is following the opcode.

Relative (Indirect)

Indirect Indexed (Long)

The pointer address is a byte, the pointer size is a

word, thus allowing 64 Kbyte addressing space,

and requires 1 byte after the opcode.

The offset is defined in memory, which address

follows the opcode.

Table 22. Instructions Supporting Direct,

Indexed, Indirect and Indirect Indexed

Addressing Modes

Long and Short

Function

Instructions

LD

Load

CP

Compare

AND, OR, XOR

Logical Operations

Arithmetic Addition/subtrac-

tion operations

ADC, ADD, SUB, SBC

BCP

Bit Compare

Short Instructions Only

CLR

Function

Clear

INC, DEC

Increment/Decrement

Test Negative or Zero

1 or 2 Complement

Bit Operations

TNZ

CPL, NEG

BSET, BRES

Bit Test and Jump Opera-

tions

BTJT, BTJF

SLL, SRL, SRA, RLC,

RRC

Shift and Rotate Operations

SWAP

Swap Nibbles

CALL, JP

Call or Jump subroutine

67/84

67

ST72101/ST72212/ST72213

5.2 INSTRUCTION GROUPS

The ST7 family devices use an Instruction Set

consisting of 63 instructions. The instructions may

be subdivided into 13 main groups as illustrated in

the following table:

Load and Transfer

LD

CLR

POP

DEC

TNZ

OR

Stack operation

PUSH

INC

RSP

BCP

Increment/Decrement

Compare and Tests

Logical operations

CP

AND

BSET

BTJT

ADC

SLL

XOR

CPL

NEG

Bit Operation

BRES

BTJF

ADD

SRL

JRT

Conditional Bit Test and Branch

Arithmetic operations

Shift and Rotates

SUB

SRA

JRF

SBC

RLC

JP

MUL

RRC

CALL

SWAP

CALLR

SLA

Unconditional Jump or Call

Conditional Branch

JRA

JRxx

TRAP

SIM

NOP

RET

Interruption management

Code Condition Flag modification

WFI

RIM

HALT

SCF

IRET

RCF

Using a pre-byte

The instructions are described with one to four

bytes.

These prebytes enable instruction in Y as well as

indirect addressing modes to be implemented.

They precede the opcode of the instruction in X or

the instruction using direct addressing mode. The

prebytes are:

In order to extend the number of available op-

codes for an 8-bit CPU (256 opcodes), three differ-

ent prebyte opcodes are defined. These prebytes

modify the meaning of the instruction they pre-

cede.

PDY 90

Replace an X based instruction

using immediate, direct, indexed, or inherent ad-

dressing mode by a Y one.

The whole instruction becomes:

PIX 92

Replace an instruction using di-

PC-2

PC-1

PC

End of previous instruction

Prebyte

rect, direct bit, or direct relative addressing mode

to an instruction using the corresponding indirect

addressing mode.

It also changes an instruction using X indexed ad-

dressing mode to an instruction using indirect X in-

dexed addressing mode.

opcode

PC+1

Additional word (0 to 2) according

to the number of bytes required to compute the ef-

fective address

PIY 91

Replace an instruction using X in-

direct indexed addressing mode by a Y one.

68/84

68

ST72101/ST72212/ST72213

INSTRUCTION GROUPS (Cont’d)

Mnemo

ADC

ADD

AND

BCP

Description

Add with Carry

Function/Example

A = A + M + C

A = A + M

Dst

Src

H

I

N

Z

C

A

M

Addition

A

Logical And

A = A . M

A

Bit compare A, Memory

Bit Reset

tst (A . M)

A

BRES

BSET

BTJF

BTJT

CALL

CALLR

CLR

bres Byte, #3

bset Byte, #3

btjf Byte, #3, Jmp1

btjt Byte, #3, Jmp1

M

Bit Set

Jump if bit is false (0)

Jump if bit is true (1)

Call subroutine

Call subroutine relative

Clear

C

reg, M

reg

0

N

1

Z

CP

Arithmetic Compare

One Complement

Decrement

tst(Reg - M)

A = FFH-A

dec Y

M

C

1

CPL

reg, M

DEC

HALT

IRET

INC

Halt

0

I

Interrupt routine return

Increment

Pop CC, A, X, PC

inc X

H

N

Z

C

reg, M

JP

Absolute Jump

Jump relative always

Jump relative

jp [TBL.w]

JRA

JRT

JRF

Never jump

jrf *

JRIH

JRIL

Jump if ext. interrupt = 1

Jump if ext. interrupt = 0

Jump if H = 1

JRH

H = 1 ?

JRNH

JRM

Jump if H = 0

H = 0 ?

Jump if I = 1

I = 1 ?

JRNM

JRMI

JRPL

JREQ

JRNE

JRC

Jump if I = 0

I = 0 ?

Jump if N = 1 (minus)

Jump if N = 0 (plus)

Jump if Z = 1 (equal)

Jump if Z = 0 (not equal)

Jump if C = 1

N = 1 ?

N = 0 ?

Z = 1 ?

Z = 0 ?

C = 1 ?

JRNC

JRULT

Jump if C = 0

C = 0 ?

Jump if C = 1

Unsigned <

Jmp if unsigned >=

Unsigned >

JRUGE Jump if C = 0

JRUGT Jump if (C + Z = 0)

69/84

69

ST72101/ST72212/ST72213

INSTRUCTION GROUPS (Cont’d)

Mnemo

JRULE

LD

Description

Jump if (C + Z = 1)

Load

Function/Example

Unsigned <=

dst <= src

Dst

Src

H

I

N

Z

C

reg, M

A, X, Y

reg, M

M, reg

MUL

NEG

NOP

OR

Multiply

X,A = X * A

X, Y, A

0

Negate (2’s compl)

No Operation

OR operation

Pop from the Stack

neg $10

C

A = A + M

pop reg

pop CC

push Y

C = 0

A

M

POP

reg

CC

M

H

I

C

0

PUSH

RCF

RET

RIM

Push onto the Stack

Reset carry flag

Subroutine Return

Enable Interrupts

Rotate left true C

Rotate right true C

Reset Stack Pointer

Subtract with Carry

Set carry flag

reg, CC

I = 0

0

RLC

RRC

RSP

SBC

SCF

SIM

C <= Dst <= C

C => Dst => C

S = Max allowed

A = A - M - C

C = 1

reg, M

N

Z

C

A

M

N

Z

C

1

Disable Interrupts

Shift left Arithmetic

Shift left Logic

I = 1

1

SLA

C <= Dst <= 0

0 => Dst => C

Dst7 => Dst => C

A = A - M

reg, M

A

N

0

Z

C

SLL

SRL

SRA

SUB

SWAP

TNZ

TRAP

WFI

Shift right Logic

Shift right Arithmetic

Subtraction

N

M

SWAP nibbles

Dst[7..4] <=> Dst[3..0] reg, M

tnz lbl1

Test for Neg & Zero

S/W trap

S/W interrupt

1

0

Wait for Interrupt

Exclusive OR

XOR

A = A XOR M

A

M

N

Z

70/84

70

ST72101/ST72212/ST72213

6 ELECTRICAL CHARACTERISTICS

6.1 ABSOLUTE MAXIMUM RATINGS

This product contains devices to protect the inputs

against damage due to high static voltages, how-

ever it is advisable to take normal precaution to

avoid application of any voltage higher than the

specified maximum rated voltages.

Power Considerations.The average chip-junc-

tion temperature, T , in Celsius can be obtained

J

from:

T =

J

TA + PD x RthJA

Where: T =

Ambient Temperature.

A

For proper operation it is recommended that V

I

RthJA = Package thermal resistance

(junction-to ambient).

and V be higher than V and lower than V .

O

SS

DD

Reliability is enhanced if unused inputs are con-

nected to an appropriate logic voltage level (V

P

=

P

+ P

.

PORT

DD

D

INT

or V ).

SS

= I x V (chip internal power).

INT

DD

P

=Port power dissipation

determined by the user)

PORT

Symbol

Parameter

Value

Unit

V

Supply Voltage

Input Voltage

-0.3 to 6.0

V

DD

V

- 0.3 to V + 0.3

I

SS

DD

V

Analog Input Voltage (A/D Converter)

Output Voltage

- 0.3 to V + 0.3

V

AI

DD

V

- 0.3 to V + 0.3

V

O

DD

IV

Total Current into V (source)

80

mA

°C

DD

SS

DD

Total Current out of V (sink)

SS

T

Junction Temperature

Storage Temperature

150

J

T

-60 to 150

STG

Note: Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is

a stress rating only and functional operation of the device at these conditions is not implied. Exposure to maximum

rating conditions for extended periods may affect device reliability.

71/84

71

ST72101/ST72212/ST72213

6.2 RECOMMENDED OPERATING CONDITIONS

Value

Typ.

Symbol

Parameter

Test Conditions

Unit

Min.

Max.

1 Suffix Version

0

70

85

°C

T

Operating Temperature

6 Suffix Version

3 Suffix Version

-40

A

125

f

= 16 MHz (1 & 6 Suffix)

= 8 MHz

3.5

3.0

5.5

OSC

V

Operating Supply Voltage

Oscillator Frequency

V

DD

1)

V

= 3.0V

= 3.5V (1 & 6 Suffix)

0

8

16

DD

f

MHz

1)

OSC

0

Note 1: A/D operation and Oscillator start-up are not guaranteed below 1MHz.

Figure 41. Maximum Operating Frequency (f

) Versus Supply Voltage (V_DD)

OSC

FUNCTIONALITY NOT GUARANTEED IN THIS AREA

FUNCTIONALITY GUARANTEED IN THIS AREA

FUNCTIONALITY NOT GUARANTEED IN THIS AREA

FOR TEMPERATURE HIGHER THAN 85°C

f

OSC

[MHz]

16

8

4

Supplly Voltage

[V]

1

0

2.5

3

3.5

4

4.5

5

5.5

FUNCTIONALITY NOT GUARANTEED IN THIS AREA WITH RESONATOR

72/84

72

ST72101/ST72212/ST72213

6.3 DC ELECTRICAL CHARACTERISTICS

(T = -40°C to +125°C and V = 5V unless otherwise specified)

A

DD

Value

Unit

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

V x 0.3

DD

Input Low Level Voltage

All Input pins

V

3V < V < 5.5V

V

IL

DD

Input High Level Voltage

All Input pins

V

3V < V < 5.5V

V

x 0.7

DD

IH

DD

1)

Hysteresis Voltage

V

400

mV

HYS

All Input pins

Low Level Output Voltage

All Output pins

I

= +10µA

= + 2mA

0.1

0.4

OL

I

OL

I

= +10µA

= +10mA

= + 15mA

0.1

1.5

3.0

OL

V

OL

Low Level Output Voltage

High Sink I/O pins

I

OL

I

OL

I

= + 20mA, T = 85°C max

OL

A

High Level Output Voltage

All Output pins

I

= - 10µA

= - 2mA

4.9

4.2

OH

V

OH

I

OH

I

Input Leakage Current

All Input pins but RESET

V

= V (No Pull-up configured)

SS

IL

IN

0.1

1.0

4)

I

= V

IH

DD

µA

Input Leakage Current

RESET pin

I

V

= V

IH

IN

DD

V

> V

< V

20

60

40

120

80

240

IN

IH

IL

R

Reset Weak Pull-up R_ON

I/O Weak Pull-up R_PU

Supply Current in

kΩ

ON

R

V

< V

100

PU

IN

IL

f

= 4 MHz, f

= 8 MHz, f

= 16 MHz, f

= 4 MHz, f

= 8 MHz, f

= 2 MHz

= 4 MHz

3

5.5

10

1.5

2.5

4

6

11

20

3

5

8

OSC

CPU

f

mA

2)

OSC

RUN Mode

f

= 8 MHz

OSC

CPU

f

= 125 kHz

= 250 kHz

OSC

CPU

2)

Supply Current in SLOW Mode

f

OSC CPU

f

= 16 MHz, f

= 500 kHz

OSC

CPU

f

= 4MHz, f

= 8MHz, f

= 16MHz, f

= 2MHz

= 4 MHz

2

3.5

6

4

7

12

OSC

CPU

I

3)

DD

Supply Current in WAIT Mode

Supply Current in WAIT-MINI-

f

OSC

f

= 8 MHz

OSC

CPU

f

= 4 MHz, f

= 8 MHz, f

= 16 MHz, f

= 125 kHz

= 250 kHz

0.8

1

1.6

1.5

2

3.5

OSC

CPU

f

mA

5)

OSC

MUM Mode

f

= 500 kHz

OSC

CPU

I

= 0mA, T = 85°C max

= 0mA

1

5

10

20

LOAD

A

Supply Current in HALT Mode

µA

I

LOAD

Notes:

1. Hysteresis voltage between switching levels. Based on characterisation results, not tested.

2. CPU running with memory access, no DC load or activity on I/O’s; clock input (OSCIN) driven by external square wave.

3. No DC load or activity on I/O’s; clock input (OSCIN) driven by external square wave.

4. Except OSCIN and OSCOUT

5. WAIT Mode with SLOW Mode selected. Based on characterisation results, not tested.

73/84

73

ST72101/ST72212/ST72213

6.4 RESET CHARACTERISTICS

o

(T =-40...+125 C and V =5V±10% unless otherwise specified.

A

DD

1)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V

> V

20

60

40

120

80

240

IN

IH

R

Reset Weak Pull-up R_ON

kΩ

ON

< V

IL

Pulse duration generated by watch-

dog and POR reset

t

1

µs

RESET

PULSE

Minimum pulse duration to be ap-

plied on external RESET pin

1)

10

ns

Note:

1) These values given only as design guidelines and are not tested.

6.5 OSCILLATOR CHARACTERISTICS

(T = -40°C to +125°C unless otherwise specified)

A

Value

Typ.

Symbol

Parameter

Test Conditions

Unit

Min.

Max.

g

Oscillator transconductance

Crystal frequency

2

1

9

mA/V

MHz

ms

m

f

16

50

OSC

t

Osc. start up time

V

= 5V±10%

DD

START

74/84

74

ST72101/ST72212/ST72213

6.6 A/D CONVERTER CHARACTERISTICS (ST72212 and ST72213 only)

(T = -40°C to +125°C and V = 5V±10% unless otherwise specified )

A

DD

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

1/f

T

Sample Duration

31.5

SAMPLE

CPU

f

V

_CPU=8MHz

Res

ADC Resolution

8

bit

=V

=5V

DDA

DD

DLE

ILE

Differential Linearity Error*

Integral Linearity Error*

Analog Input Voltage

±0.6

±1

±2

V

DDA

V

AIN

SSA

Supply current rise

during A/D conversion

I

t

1

mA

ADC

f_CPU=8MHz

=V =5V

Stabilization time after ADC enable

Conversion Time

30

µs

STAB

CONV

V

DD

DDA

8

64

µs

1/f

CPU

Resistance of analog sources

R

C

R

15

22

2

ΚΩ

pF

AIN

(V

AIN)

f_CPU=8MHz, T=25°C,

=V =5V

Hold Capacitance

HOLD

SS

V

DD

DDA

Resistance of sampling switch and

internal trace

ΚΩ

*Note: ADC Accuracy vs. Negative Injection Current:

For I =0.8mA, the typical leakage induced inside the die is 1.6µA and the effect on the ADC accuracy is

inj-

a loss of 1 LSB by 10KΩ increase of the external analog source impedance.

These measurement results and recommendations take worst case injection conditions into account:

- negative injection

- injection to an Input with analog capability, adjacent to the enabled Analog Input

- at 5V V supply, and worst case temperature.

DD

V

Sampling

Switch

DD

V

= 0.6V

R

T

AIN

V

AIN

R

SS

Px.x/AINx

SS

2ΚΩ

C

hold

5pF

C

= input capacitance

= threshold voltage

22 pF

V

T

leakage max.

±1µA

V

= 0.6V

T

SS

C

= sampling switch

V

= sample/hold

capacitance

SS

hold

leakage = leakage current

at the pin due

to various junctions

75/84

75

ST72101/ST72212/ST72213

A/D CONVERTER CHARACTERISTICS (Cont’d)

Figure 42. ADC conversion characteristics

Offset Error OSE

Gain Error GE

255

254

253

252

251

250

( 2)

V

– V

refP

refM

code

out

1LSB

= ---------------------------------------

ideal

256

7

(1)

6

5

(5)

(1) Example of an actual transfer curve

(2) The ideal transfer curve

(3) Differential non-linearity error (DLE)

(4) Integral non-linearity error (ILE)

(5) Center of a step of the actual transfer curve

4

3

(4)

(3)

1 LSB (ideal)

2

1

0

1

2

3

4

5

6

7

250 251 252 253 254 255 256

(LSB

V

)

ideal

in(A)

Offset Error OSE

VR02133A

76/84

76

ST72101/ST72212/ST72213

6.7 SPI CHARACTERISTICS

Serial Peripheral Interface

Value

Unit

Ref.

Symbol

Parameter

Condition

Min.

Max.

Master

Slave

1/128

dc

1/4

1/2

f

t

SPI frequency

f

t

SPI

CPU

Master

Slave

4

2

1

SPI clock period

2

3

t

Enable lead time

Enable lag time

Slave

120

ns

Lead

t

Lag

Master

Slave

100

90

4

5

t

Clock (SCK) high time

Clock (SCK) low time

Data set-up time

ns

SPI_H

Master

Slave

100

90

t

SPI_L

Master

Slave

100

6

t

SU

Master

Slave

100

7

t

Data hold time (inputs)

H

Access time (time to data active

from high impedance state)

8

t

0

120

240

A

Slave

Disable time (hold time to high im-

pedance state)

9

t

Dis

Master (before capture edge)

Slave (after enable edge)

0.25

t

CPU

ns

10

11

12

13

t

Data valid

V

120

Master (before capture edge)

Slave (after enable edge)

0.25

0

CPU

ns

t

Data hold time (outputs)

Rise time

Hold

Outputs: SCK,MOSI,MISO

(20% V to 70% V , C = 200pF) Inputs: SCK,MOSI,MISO,SS

100

ns

µs

t

Rise

DD

L

Fall time

Outputs: SCK,MOSI,MISO

(70% V to 20% V , C = 200pF) Inputs: SCK,MOSI,MISO,SS

100

ns

µs

t

Fall

DD

L

Measurement points are V , V , V and V in the SPI Timing Diagram

OL

OH

IL

IH

Figure 43. SPI Master Timing Diagram CPHA=0, CPOL=0

SS

(INPUT)

1

13

12

SCK

(OUTPUT)

5

4

MISO

(INPUT)

D7-IN

7

D6-IN

D0-IN

6

MOSI

(OUTPUT)

D7-OUT

11

D6-OUT

D0-OUT

10

VR000109

77/84

77

ST72101/ST72212/ST72213

SPI CHARACTERISTICS (Cont’d)

Measurement points are V , V , V and V in the SPI Timing Diagram

OL

OH

IL

IH

Figure 44. SPI Master Timing Diagram CPHA=0, CPOL=1

SS

(INPUT)

1

13

12

13

SCK

(OUTPUT)

5

4

MISO

(INPUT)

D7-IN

7

D6-IN

D0-IN

6

MOSI

(OUTPUT)

D7-OUT

11

D6-OUT

D0-OUT

10

VR000110

VR000107

VR000108

Figure 45. SPI Master Timing Diagram CPHA=1, CPOL=0

SS

(INPUT)

1

13

SCK

(OUTPUT)

4

5

MISO

(INPUT)

D7-OUT

D6-OUT

D0-OUT

6

7

MOSI

(OUTPUT)

D6-IN

D0-IN

D7-IN

11

10

Figure 46. SPI Master Timing Diagram CPHA=1, CPOL=1

SS

(INPUT)

1

12

SCK

(OUTPUT)

4

5

MISO

(INPUT)

D7-IN

7

D6-IN

D0-IN

6

MOSI

(OUTPUT)

D7-OUT

11

D6-OUT

D0-OUT

10

78/84

ST72101/ST72212/ST72213

SPI CHARACTERISTICS (Cont’d)

Measurement points are V , V , V and V in the SPI Timing Diagram

OL

OH

IL

IH

Figure 47. SPI Slave Timing Diagram CPHA=0, CPOL=0

SS

(INPUT)

2

1

12

3

13

11

SCK

(INPUT)

4

5

MISO HIGH-Z

D7-OUT

D6-OUT

D6-IN

D0-OUT

D0-IN

(OUTPUT)

8

10

9

MOSI

(INPUT)

D7-IN

7

6

VR000113

Figure 48. SPI Slave Timing Diagram CPHA=0, CPOL=1

SS

(INPUT)

2

1

13

12

11

3

SCK

(INPUT)

5

4

MISO

HIGH-Z

8

D7-OUT

D6-OUT

D6-IN

D0-OUT

D0-IN

(OUTPUT)

10

9

MOSI

(INPUT)

D7-IN

7

6

VR000114

Figure 49. SPI Slave Timing Diagram CPHA=1, CPOL=0

SS

(INPUT)

2

1

13

12

3

SCK

(INPUT)

4

5

HIGH-Z

8

MISO

D7-OUT

D6-OUT

D6-IN

D0-OUT

(OUTPUT)

11

9

10

MOSI

(INPUT)

D7-IN

D0-IN

7

6

VR000111

Figure 50. SPI Slave Timing Diagram CPHA=1, CPOL=1

SS

(INPUT)

2

1

12

13

3

SCK

(INPUT)

5

4

HIGH-Z

8

MISO

D7-OUT

D6-OUT

D6-IN

D0-OUT

(OUTPUT)

11

10

9

MOSI

(INPUT)

D7-IN

D0-IN

6

7

VR000112

79/84

ST72101/ST72212/ST72213

7 GENERAL INFORMATION

7.1 EPROM ERASURE

EPROM version devices are erased by exposure

to high intensity UV light admitted through the

transparent window. This exposure discharges the

floating gate to its initial state through induced

photo current.

An opaque coating (paint, tape, label, etc...)

should be placed over the package window if the

product is to be operated under these lighting con-

ditions. Covering the window also reduces I

in

DD

power-saving modes due to photo-diode leakage

currents.

It is recommended that the EPROM devices be

kept out of direct sunlight, since the UV content of

sunlight can be sufficient to cause functional fail-

ure. Extended exposure to room level fluorescent

lighting may also cause erasure.

An Ultraviolet source of wave length 2537 Å yield-

2

ing a total integrated dosage of 15 Watt-sec/cm is

required to erase the device. It will be erased in 15

2

to 20 minutes if such a UV lamp with a 12mW/cm

power rating is placed 1 inch from the device win-

dow without any interposed filters.

7.2 PACKAGE MECHANICAL DATA

Figure 51. 28-Pin Small Outline Package, 300-mil Width

mm

inches

Typ

Dim.

A

Min Typ Max Min

Max

2.35

2.65 0.0926

0.30 0.0040

0.51 0.013

0.32 0.0091

18.10 0.6969

7.60 0.2914

0.1043

0.0118

0.020

A1 0.10

B

C

D

E

e

0.33

0.23

0.0125

0.7125

0.2992

17.70

7.40

1.27

0.0500

H

h

10.01

0.25

10.64 0.394

0.74 0.010

0°

0.419

0.029

8°

K

L

0.41

1.27 0.016

0.10

0.050

0.004

G

SO28

Number of Pins

N

28

80/84

ST72101/ST72212/ST72213

Figure 52. 32-Pin Shrink Plastic Dual In Line Package

mm

inches

Dim.

A

E

Min Typ Max Min Typ Max

3.56 3.76 5.08 0.140 0.148 0.200

See Lead Detail

A1 0.51

A2 3.05 3.56 4.57 0.120 0.140 0.180

0.36 0.46 0.58 0.014 0.018 0.023

b1 0.76 1.02 1.40 0.030 0.040 0.055

0.020

C

b

e_A

b1

b

e

C

D

E

0.20 0.25 0.36 0.008 0.010 0.014

27.43 27.94 28.45 1.080 1.100 1.120

9.91 10.41 11.05 0.390 0.410 0.435

B

e

3

D

E1 7.62 8.89 9.40 0.300 0.350 0.370

A

2

N

e

eA

eB

L

1.78

0.070

0.400

A

L

10.16

E

1

A

12.70

0.500

1

2.54 3.05 3.81 0.100 0.120 0.150

e

Number of Pins

VR01725J

1

N/2

N

32

Figure 53. 32-Pin Shrink Ceramic Dual In-Line Package

mm

Min Typ Max Min Typ Max

3.63 0.143

inches

Dim.

A

A1 0.38

0.015

B

0.36 0.46 0.58 0.014 0.018 0.023

B1 0.64 0.89 1.14 0.025 0.035 0.045

C

D

0.20 0.25 0.36 0.008 0.010 0.014

29.41 29.97 30.53 1.158 1.180 1.202

D1

E

26.67

10.16

1.050

0.400

E1 9.45 9.91 10.36 0.372 0.390 0.408

e

G

1.78

9.40

14.73

1.12

3.30

7.37

0.070

0.370

0.580

0.044

0.130

0.290

G1

G2

L

Ø

Number of Pins

32

CDIP32SW

N

81/84

ST72101/ST72212/ST72213

7.3 ORDERING INFORMATION

Each device is available for production in user pro-

grammable version (OTP) as well as in factory

coded version (ROM). OTP devices are shipped to

customer with a default blank content FFh, while

ROM factory coded parts contain the code sent by

customer. There is one common EPROM version

for debugging and prototyping which features the

maximum memory size and peripherals of the

family. Care must be taken to only use resources

available on the target device.

ROM contents are to be sent on diskette, or by

electronic means, with the hexadecimal file in .S19

format generated by the development tool. All un-

used bytes must be set to FFh.

The selected options are communicated to STMi-

croelectronics using the correctly completed OP-

TION LIST appended.

The STMicroelectronics Sales Organization will be

pleased to provide detailed information on con-

tractual points.

7.3.1 Transfer Of Customer Code

Customer code is made up of the ROM contents

and the list of the selected options (if any). The

Figure 54. ROM Factory Coded Device Types

TEMP.

PACKAGE RANGE

/ XXX

DEVICE

Code name (defined by STMicroelectronics)

1 = standard 0 to +70°C

3 = automotive -40 to +125°C

6 = industrial -40 to +85°C

B = Plastic DIP

M = Plastic SOIC

ST72101G1

ST72101G2

ST72212G2

ST72213G1

Figure 55. OTP User Programmable Device Types

TEMP.

PACKAGE RANGE

DEVICE

XXX

Option (if any)

3 = automotive -40 to +125°C

6 = industrial -40 to +85°C

B = Plastic DIP

M = Plastic SOIC

ST72T101G1

ST72T101G2

ST72T212G2

ST72T213G1

Note: The ST72E251G2D0 (CERDIP 25 °C) is used as the EPROM version for the above devices.

82/84

ST72101/ST72212/ST72213

ST72101, ST72213 and ST72212 MICROCONTROLLER OPTION LIST

Customer . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Address

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contact

Phone No . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

STMicroelectronics references

Device:

[ ] ST72101

[ ] ST72212

[ ] ST72213

Package:

[ ] Dual in Line Plastic [ ] Small Outline Plastic with conditioning:

[ ] Standard (Stick)

[ ] Tape & Reel

Temperature Range:

Special Marking:

[ ] 0°C to + 70°C

[ ] - 40°C to + 85°C

[ ] - 40°C to + 125°C

[ ] No

[ ] Yes ”_ _ _ _ _ _ _ _ _ _ _ ”

Authorized characters are letters, digits, ’.’, ’-’, ’/’ and spaces only.

Maximum character count: SDIP32:

SO28:

10

8

Comments:

Supply Operating Range in the application:

Oscillator Frequency in the application:

Notes

Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Date . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

83/84

ST72101/ST72212/ST72213

8 SUMMARY OF CHANGES

Change Description (Rev. 1.5 to 1.6)

Page

Added new External Connections section

Removed RP external resistor

9

16

Changed ORed to ANDed in External interrupts paragraph, to read “If several input pins, con-

nected to the same interrupt vector, are configured as interrupts, their signals are logically AN-

Ded before entering the edge/level detection block”.

18 and 24

23

Added note ”Any modification of one of these two bits resets the interrupt request related to

this interrupt vector.”

Added clamping diodes to I/O pin figure and table

Added sections on low power modes and interrupts to peripheral descriptions

Changed 16-bit Timer Chapter

26

31,43,58,63

32 to 48

44

Added details to description of FOLV1 and FOLV2 bits

Added ADC recommended external connections

Added Reset characteristics section

63

74

Added figure to ADC electrical characteristics section

75

Change Description (Rev. 1.6 to 1.7)

SPR2 bit reinstated in SPI chapter

49 to 61

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of useof such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics

Purchase of I²C Components by STMicroelectronics conveys a license under the Philips I²C Patent. Rights to use these components in an

I²C system is granted provided that the system conforms to the I²C Standard Specification as defined by Philips.

STMicroelectronics Group of Companies

Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain

Sweden - Switzerland - United Kingdom - U.S.A.

http:// www.st.com

84/84


型号：	ST72101G1B1
厂家：	ST
描述：	8-BIT MCU WITH 4 TO 8K ROM/OTP/EPROM, 256 BYTES RAM, ADC, WDG, SPI AND 1 OR 2 TIMERS 8位MCU 4〜 8K ROM / OTP / EPROM ， 256字节RAM ， ADC ， WDG ， SPI和1或2个定时器可编程只读存储器电动程控只读存储器
文件：	总84页 (文件大小：527K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ST72101G1B1 [STMICROELECTRONICS]

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