ST72121J2B3/XXX [STMICROELECTRONICS]
8-BIT, MROM, 8MHz, MICROCONTROLLER, PDIP42, 0.600 INCH, SHRINK, PLASTIC, DIP-42;
| 型号： | ST72121J2B3/XXX |
| 厂家： | 
ST |
| 描述： | 8-BIT, MROM, 8MHz, MICROCONTROLLER, PDIP42, 0.600 INCH, SHRINK, PLASTIC, DIP-42 光电二极管 |
| 文件： | 总87页 (文件大小：1365K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ST72121
8-BIT MCU WITH 8 TO 16K ROM/OTP/EPROM,
384 TO 512 BYTES RAM, WDG, SCI, SPI AND 2 TIMERS
PRELIMINARY DATA
User Program Memory (ROM/OTP/EPROM):
8 to 16K bytes
Data RAM: 384 to 512 bytes including 256 bytes
of stack
Master Reset and Power-On Reset
Low Voltage Detector (LVD) Reset option
Run and Power Saving modes
32 multifunctional bidirectional I/O lines:
– 9 programmable interrupt inputs
– 4 high sink outputs
PSDIP42
– 13 alternate functions
– EMI filtering
Software or Hardware Watchdog (WDG)
Two 16-bit Timers, each featuring:
– 2 Input Captures 1)
– 2 Output Compares 1)
– External Clock input (on Timer A)
– PWM and Pulse Generator modes
Synchronous Serial Peripheral Interface (SPI)
CSDIP42W
Asynchronous Serial Communications Interface
(SCI)
8-bit Data Manipulation
63 basic Instructions and 17 main Addressing
Modes
8 x 8 Unsigned Multiply Instruction
True Bit Manipulation
TQFP44
Complete Development Support on DOS/
WINDOWSTM Real-Time Emulator
Full Software Package on DOS/WINDOWSTM
(C-Compiler, Cross-Assembler, Debugger)
(See ordering information at the end of datasheet)
Note: 1. One only on Timer A.
Device Summary
Features
ST72121J2
ST72121J4
Program Memory - bytes
RAM (stack) - bytes
Peripherals
8K
384 (256)
16K
512 (256)
Watchdog, Timers, SPI, SCI and optional Low Voltage Detector Reset
Operating Supply
CPU Frequency
Temperature Range
Package
3 to 5.5 V
8MHz max (16MHz oscillator) - 4MHz max over 85°C
- 40°C to + 125°C
TQFP44 - SDIP42
OTP/EPROM Devices
ST72T121J4/ST72E121J4
Rev. 1.5
January 1999
1/87
This is preliminary information on a new product in development or undergoing evaluation. Details are subject to change without notice.
1
Table of Contents
1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.3 MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.4 OPTION BYTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3 CLOCKS, RESET, INTERRUPTS & POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1 CLOCK SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1.2 External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2.2 External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2.3 Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2.4 Low Voltage Detector Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.4 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.4.2 Slow Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.4.3 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.4.4 Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.5 MISCELLANEOUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.1 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.1.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.1.3 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.2 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.2.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.2.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.2.4 Hardware Watchdog Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.2.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.3 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.3.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.3.4 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.4 SERIAL COMMUNICATIONS INTERFACE (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.4.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.4.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
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Table of Contents
4.4.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.4.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.5 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.5.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.5.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.5.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.5.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
5 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
5.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
5.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
5.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
5.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
5.1.4 Indexed (No Offset, Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
5.1.5 Indirect (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
5.1.6 Indirect Indexed (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
5.1.7 Relative mode (Direct, Indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
5.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.1 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.2 RECOMMENDED OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.3 DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
6.4 OSCILLATOR CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
6.5 PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
7 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
7.1 EPROM ERASURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
7.2 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
7.3 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
7.3.1 Transfer Of Customer Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
3/87
3
ST72121
1 GENERAL DESCRIPTION
1.1 INTRODUCTION
The ST72121 HCMOS Microcontroller Unit (MCU)
is a member of the ST7 family. The device is
based on an industry-standard 8-bit core and fea-
tures an enhanced instruction set. The device is
normally operated at a 16 MHz oscillator frequen-
cy. Under software control, the ST72121 may be
placed in either Wait, Slow or Halt modes, thus re-
ducing power consumption. The enhanced in-
struction set and addressing modes afford real
programming potential. In addition to standard
8-bit data management, the ST72121 features
true bit manipulation, 8x8 unsigned multiplication
and indirect addressing modes on the whole mem-
ory. The device includes a low consumption and
fast start on-chip oscillator, CPU, program memo-
ry (ROM/OTP/EPROM versions), RAM, 32 I/O
lines, a Low Voltage Detector (LVD) and the fol-
lowing on-chip peripherals: industry standard syn-
chronous SPI and asynchronous SCI serial inter-
faces, digital Watchdog, two independent 16-bit
Timers, one featuring an External Clock Input, and
both featuring Pulse Generator capabilities, 2 In-
put Captures and 2 Output Compares (only 1 Input
Capture and 1 Output Compare on Timer A).
Figure 1. ST72121 Block Diagram
Internal
CLOCK
OSCIN
PA3 -> PA7
(5 bits)
PORT A
PORT B
OSC
OSCOUT
RESET
CONTROL
AND LVD
PB0 -> PB4
(5 bits)
8-BIT CORE
ALU
TIMER B
PORT C
SPI
PC0 -> PC7
(8 bits)
PROGRAM
MEMORY
(8 - 16K Bytes)
PORT D
PD0 -> PD5
(6 bits)
RAM
(384 - 512 Bytes)
PORT E
SCI
PE0 -> PE1
(2 bits)
PORT F
PF0 -> PF2,4,6,7
(6 bits)
TIMER A
V
DD
WATCHDOG
POWER
SUPPLY
V
SS
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4
ST72121
1.2 PIN DESCRIPTION
Figure 2. 44-Pin Thin QFP Package Pinout
44 43 42 41 40 39 38 37 36 35 34
VSS_1
VDD_1
PE1/RDI
PB0
33
32
1
2
3
4
5
6
7
8
9
(EI2)
(EI2)
(EI2)
(EI2)
(EI3)
PB1
(EI0) 31
30
PA3
PB2
PC7/SS
PB3
29
PC6/SCK
PB4
28
PC5/MOSI
PC4/MISO
PC3/ICAP1_B
PC2/ICAP2_B
PC1/OCMP1_B
PC0/OCMP2_B
PD0
PD1
PD2
PD3
PD4
27
26
25
10
11
24
23
12 13 14 15 16 17 18 19 20 21 22
1. V
on EPROM/OTP only
PP
Figure 3. 42-Pin Shrink DIP Package Pinout
PB4
PD0
PD1
PD2
PD3
PD4
PD5
VDD_3
VSS_3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
PB3
PB2
PB1
PB0
PE1/RDI
PE0/TD0
VDD_2
(EI3)
42
41
(EI2) 40
(EI2)
(EI2)
(EI2)
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
OSCIN
OSCOUT
VSS_2
CLKOUT/PF0
PF1
PF2
OCMP1_A/PF4
ICAP1_A/PF6
(EI1)
(EI1)
(EI1)
RESET
TEST/VPP
PA7
PA6
PA5
PA4
VSS_1
VDD_1
1)
EXTCLK_A/PF7
PC0/OCMP2_B
PC1/OCMP1_B
PC2/ICAP2_B
PC3/ICAP1_B
PC4/MISO
(EI0)
24
23
22
PA3
PC7/SS
PC6/SCK
PC5/MOSI
1. V
on EPROM/OTP only
PP
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5
ST72121
Table 1. ST72121Jx Pin Description
Pin n° Pin n°
Pin Name
Type
Description
Remarks
QFP44 SDIP42
1
38
39
40
41
42
1
PE1/RDI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
S
Port E1 or SCI Receive Data In
2
PB0
PB1
PB2
PB3
PB4
PD0
PD1
PD2
PD3
PD4
PD5
Port B0
External Interrupt: EI2
External Interrupt: EI2
External Interrupt: EI2
External Interrupt: EI2
External Interrupt: EI3
3
Port B1
4
Port B2
5
Port B3
6
Port B4
7
2
Port D0
8
3
Port D1
9
4
Port D2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
5
Port D3
6
Port D4
7
Port D5
8
V
V
Main Power Supply
Ground
DD_3
SS_3
9
S
10
11
12
13
14
15
PF0/CLKOUT
PF1
I/O
I/O
I/O
I/O
I/O
I/O
S
Port F0 or CPU Clock Output
Port F1
External Interrupt: EI1
External Interrupt: EI1
External Interrupt: EI1
PF2
Port F2
PF4/OCMP1_A
PF6/ICAP1_A
PF7/EXTCLK_A
Port F4 or Timer A Output Compare 1
Port F6 or Timer A Input Capture 1
Port F7 or External Clock on Timer A
Main power supply
V
V
DD_0
SS_0
S
Ground
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
PC0/OCMP2_B
PC1/OCMP1_B
PC2/ICAP2_B
PC3/ICAP1_B
PC4/MISO
PC5/MOSI
PC6/SCK
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
S
Port C0 or Timer B Output Compare 2
Port C1 or Timer B Output Compare 1
Port C2 or Timer B Input Capture 2
Port C3 or Timer B Input Capture 1
Port C4 or SPI Master In / Slave Out Data
Port C5 or SPI Master Out / Slave In Data
Port C6 or SPI Serial Clock
Port C7 or SPI Slave Select
Port A3
PC7/SS
PA3
External Interrupt: EI0
V
V
Main power supply
DD_1
SS_1
S
Ground
PA4
PA5
PA6
PA7
I/O
I/O
I/O
I/O
Port A4
High Sink
High Sink
High Sink
High Sink
Port A5
Port A6
Port A7
Test mode pin. In the EPROM programming
mode, this pin acts as the programming voltage
This pin must be tied low
in user mode
1)
PP
38
31
TEST/V
RESET
S
input V
PP.
39
40
41
42
43
44
32
33
34
35
36
37
I/O
S
Bidirectional. Active low. Top priority non maskable interrupt.
Ground
V
SS_2
OSCOUT
OSCIN
O
I
Input/Output Oscillator pin. These pins connect a parallel-resonant crystal, or
an external source to the on-chip oscillator.
V
S
Main power supply
DD_2
PE0/TDO
I/O
Port E0 or SCI Transmit Data Out
Note 1: V on EPROM/OTP only.
PP
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ST72121
1.3 MEMORY MAP
Figure 4. Program Memory Map
0080h
Short Addressing
RAM (zero page)
0000h
HW Registers
(see Table 3)
00FFh
0100h
007Fh
0080h
256 Bytes Stack/
16-bit Addressing RAM
01FFh
384 Bytes RAM
01FFh
512 Bytes RAM
027Fh
0200h / 0280h
0080h
Short Addressing
RAM (zero page)
00FFh
0100h
Reserved
256 Bytes Stack/
BFFFh
C000h
16-bit Addressing RAM
01FFh
0200h
16K Bytes
Program
Memory
16-bit Addressing
RAM
E000h
027Fh
8K Bytes
Program
Memory
FFDFh
FFE0h
Interrupt & Reset Vectors
(see Table 2)
FFFFh
Table 2. Interrupt Vector Map
Vector Address
Description
Remarks
FFE0-FFE1h
FFE2-FFE3h
FFE4-FFE5h
FFE6-FFE7h
FFE8-FFE9h
FFEA-FFEBh
FFEC-FFEDh
FFEE-FFEFh
FFF0-FFF1h
FFF2-FFF3h
FFF4-FFF5h
FFF6-FFF7h
FFF8-FFF9h
FFFA-FFFBh
FFFC-FFFDh
FFFE-FFFFh
Not Used
Not Used
Not Used
Internal Interrupt
Internal Interrupt
Internal Interrupt
Internal Interrupt
Internal Interrupt
SCI Interrupt Vector
TIMER B Interrupt Vector
TIMER A Interrupt Vector
SPI interrupt vector
Not Used
External Interrupt Vector EI3 (PB4)
External Interrupt Vector EI2 (PB0:PB3)
External Interrupt Vector EI1 (PF0:PF2)
External Interrupt Vector EI0 (PA3)
Not Used
External Interrupt
External Interrupt
External Interrupt
External Interrupt
Not Used
TRAP (software) Interrupt Vector
RESET Vector
CPU Interrupt
7/87
7
ST72121
Table 3. Hardware Register Memory Map
Register
Reset
Status
Address
Block
Register Name
Remarks
R/W
Label
0000h
PADR
Data Register
00h
00h
00h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h to
001Fh
0020h
0021h
0022h
0023h
0024h to
0029h
002Ah
Port A
PADDR
PAOR
Data Direction Register
Option Register
R/W
R/W
1)
Reserved Area (1 byte)
PCDR
PCDDR
PCOR
Data Register
00h
00h
00h
R/W
R/W
R/W
Port C
Port B
Port E
Port D
Port F
Data Direction Register
Option Register
Reserved Area (1 byte)
PBDR
PBDDR
PBOR
Data Register
00h
00h
00h
R/W
R/W
R/W
Data Direction Register
Option Register
1)
1)
1)
1)
Reserved Area (1 byte)
PEDR
PEDDR
PEOR
Data Register
00h
00h
0Ch
R/W
R/W
R/W
Data Direction Register
Option Register
Reserved Area (1 byte)
PDDR
PDDDR
PDOR
Data Register
00h
00h
00h
R/W
R/W
R/W
Data Direction Register
Option Register
Reserved Area (1 byte)
PFDR
PFDDR
PFOR
Data Register
00h
00h
28h
R/W
R/W
R/W
Data Direction Register
Option Register
Reserved Area (9 bytes)
MISCR
SPIDR
SPICR
SPISR
Miscellaneous Register
SPI Data I/O Register
SPI Control Register
SPI Status Register
00h
xxh
xxh
00h
R/W
R/W
SPI
Read Only
Reserved Area (6 bytes)
WDGCR
WDGSR
Watchdog Control Register
Watchdog Status Register
7Fh
00h
R/W
WDG
3)
002Bh
R/W
002Ch to
0030h
Reserved Area (5 bytes)
8/87
8
ST72121
Register
Label
Reset
Status
Address
0031h
Block
Register Name
Control Register2
Remarks
TACR2
TACR1
TASR
00h
00h
xxh
xxh
xxh
80h
00h
FFh
FCh
FFh
FCh
xxh
xxh
80h
00h
R/W
0032h
Control Register1
R/W
0033h
Status Register
Read Only
Read Only
Read Only
R/W
0034h-0035h
TAIC1HR
TAIC1LR
Input Capture1 High Register
Input Capture1 Low Register
0036h-0037h
0038h-0039h
003Ah-003Bh
003Ch-003Dh
003Eh-003Fh
TAOC1HR Output Compare1 High Register
TAOC1LR Output Compare1 Low Register
R/W
Timer A
TACHR
Counter High Register
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
TACLR
Counter Low Register
TAACHR
TAACLR
TAIC2HR
TAIC2LR
Alternate Counter High Register
Alternate Counter Low Register
Input Capture2 High Register
Input Capture2 Low Register
2)
2)
2)
TAOC2HR Output Compare2 High Register
TAOC2LR Output Compare2 Low Register
Reserved Area (1 byte)
R/W
2)
R/W
0040h
0041h
TBCR2
TBCR1
TBSR
Control Register2
00h
00h
xxh
xxh
xxh
80h
00h
FFh
FCh
FFh
FCh
xxh
xxh
80h
00h
C0h
xxh
R/W
0042h
Control Register1
R/W
0043h
Status Register
Read Only
Read Only
Read Only
R/W
0044h-0045h
TBIC1HR
TBIC1LR
Input Capture1 High Register
Input Capture1 Low Register
0046h-0047h
0048h-0049h
004Ah-004Bh
004Ch-004Dh
004Eh-004Fh
TBOC1HR Output Compare1 High Register
TBOC1LR Output Compare1 Low Register
R/W
Timer B
TBCHR
Counter High Register
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
R/W
TBCLR
Counter Low Register
TBACHR
TBACLR
TBIC2HR
TBIC2LR
Alternate Counter High Register
Alternate Counter Low Register
Input Capture2 High Register
Input Capture2 Low Register
TBOC2HR Output Compare2 High Register
TBOC2LR Output Compare2 Low Register
R/W
0050h
0051h
0052h
0053h
0054h
0055h
0056h
0057h
0058h to
007Fh
SCISR
SCI Status Register
Read Only
R/W
SCIDR
SCI Data Register
SCIBRR
SCICR1
SCICR2
SCIERPR
SCI Baud Rate Register
SCI Control Register 1
00x----xb R/W
xxh
00h
00h
---
R/W
SCI
SCI Control Register 2
R/W
SCI Extended Receive Prescaler Register
Reserved
R/W
Reserved
R/W
SCIETPR
SCI Extended Transmit Prescaler Register
00h
Reserved Area (40 bytes)
Notes:
1. The bits corresponding to unavailable pins are forced to 1 by hardware, this affects the reset status value.
2. External pin not available.
3. Not used in versions without Low Voltage Detector Reset.
9/87
9
ST72121
1.4 OPTION BYTE
The user has the option to select software watch-
dog or hardware watchdog (see description in the
Watchdog chapter). When programming EPROM
or OTP devices, this option is selected in a menu
by the user of the EPROM programmer before
burning the EPROM/OTP. The Option Byte is lo-
cated in a non-user map. No address has to be
specified. The Option Byte is at FFh after UV eras-
ure and must be properly programmed to set de-
sired options.
OPTBYTE
7
0
-
-
-
-
b3
b2
-
WDG
Bit 7:4 = Not used
Bit 3 = Reserved, must be cleared.
For ROM devices, the option (software or hard-
ware watchdog) must be specified in the option list
provided to STMicroelectronics with the ROM
code (see ordering information). The Option Byte
is hardware programmed as the ROM content.
Bit 2 = Reserved, must be set on ST72121N devic-
es and must be cleared on ST72121J devices.
Bit 1 = Not used
Bit 0 = WDG Watchdog disable
0: The Watchdog is enabled after reset (Hardware
Watchdog).
1: The Watchdog is not enabled after reset (Soft-
ware Watchdog).
10/87
10
ST72121
2 CENTRAL PROCESSING UNIT
2.1 INTRODUCTION
Accumulator (A)
The Accumulator is an 8-bit general purpose reg-
ister used to hold operands and the results of the
arithmetic and logic calculations and to manipulate
data.
This CPU has a full 8-bit architecture and contains
six internal registers allowing efficient 8-bit data
manipulation.
Index Registers (X and Y)
2.2 MAIN FEATURES
In indexed addressing modes, these 8-bit registers
are used to create either effective addresses or
temporary storage areas for data manipulation.
(The Cross-Assembler generates a precede in-
struction (PRE) to indicate that the following in-
struction refers to the Y register.)
63 basic instructions
Fast 8-bit by 8-bit multiply
17 main addressing modes (with indirect
addressing mode)
Two 8-bit index registers
16-bit stack pointer
8 MHz CPU internal frequency
Low power modes
Maskable hardware interrupts
Non-maskable software interrupt
The Y register is not affected by the interrupt auto-
matic procedures (not pushed to and popped from
the stack).
Program Counter (PC)
The program counter is a 16-bit register containing
the address of the next instruction to be executed
by the CPU. It is made of two 8-bit registers PCL
(Program Counter Low which is the LSB) and PCH
(Program Counter High which is the MSB).
2.3 CPU REGISTERS
The 6 CPU registers shown in Figure 5 are not
present in the memory mapping and are accessed
by specific instructions.
Figure 5. CPU Registers
7
0
ACCUMULATOR
RESET VALUE = XXh
7
0
0
X INDEX REGISTER
Y INDEX REGISTER
RESET VALUE = XXh
7
RESET VALUE = XXh
PCL
PCH
7
8
15
0
PROGRAM COUNTER
RESET VALUE = RESET VECTOR @ FFFEh-FFFFh
7
1
0
1
1
1
1
H I N Z
C
X
CONDITION CODE REGISTER
RESET VALUE =
8
1
X 1 X X
15
7
0
STACK POINTER
RESET VALUE = STACK HIGHER ADDRESS
X = Undefined Value
11/87
11
ST72121
CENTRAL PROCESSING UNIT (Cont’d)
CONDITION CODE REGISTER (CC)
Read/Write
ter it and reset by the IRET instruction at the end of
the interrupt routine. If the I bit is cleared by soft-
ware in the interrupt routine, pending interrupts are
serviced regardless of the priority level of the cur-
rent interrupt routine.
Reset Value: 111x1xxx
7
0
1
1
1
H
I
N
Z
C
Bit 2 = N Negative.
This bit is set and cleared by hardware. It is repre-
sentative of the result sign of the last arithmetic,
logical or data manipulation. It is a copy of the 7th
bit of the result.
0: The result of the last operation is positive or null.
1: The result of the last operation is negative
(i.e. the most significant bit is a logic 1).
The 8-bit Condition Code register contains the in-
terrupt mask and four flags representative of the
result of the instruction just executed. This register
can also be handled by the PUSH and POP in-
structions.
These bits can be individually tested and/or con-
trolled by specific instructions.
This bit is accessed by the JRMI and JRPL instruc-
tions.
Bit 4 = H Half carry.
This bit is set by hardware when a carry occurs be-
tween bits 3 and 4 of the ALU during an ADD or
ADC instruction. It is reset by hardware during the
same instructions.
0: No half carry has occurred.
1: A half carry has occurred.
Bit 1 = Z Zero.
This bit is set and cleared by hardware. This bit in-
dicates that the result of the last arithmetic, logical
or data manipulation is zero.
0: The result of the last operation is different from
zero.
This bit is tested using the JRH or JRNH instruc-
tion. The H bit is useful in BCD arithmetic subrou-
tines.
1: The result of the last operation is zero.
This bit is accessed by the JREQ and JRNE test
instructions.
Bit 3 = I Interrupt mask.
Bit 0 = C Carry/borrow.
This bit is set by hardware when entering in inter-
rupt or by software to disable all interrupts except
the TRAP software interrupt. This bit is cleared by
software.
0: Interrupts are enabled.
1: Interrupts are disabled.
This bit is set and cleared by hardware and soft-
ware. It indicates an overflow or an underflow has
occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.
This bit is driven by the SCF and RCF instructions
and tested by the JRC and JRNC instructions. It is
also affected by the “bit test and branch”, shift and
rotate instructions.
This bit is controlled by the RIM, SIM and IRET in-
structions and is tested by the JRM and JRNM in-
structions.
Note: Interrupts requested while I is set are
latched and can be processed when I is cleared.
By default an interrupt routine is not interruptable
because the I bit is set by hardware when you en-
12/87
12
ST72121
CENTRAL PROCESSING UNIT (Cont’d)
Stack Pointer (SP)
The least significant byte of the Stack Pointer
(called S) can be directly accessed by a LD in-
struction.
Read/Write
Reset Value: 01FFh
Note: When the lower limit is exceeded, the Stack
Pointer wraps around to the stack upper limit, with-
out indicating the stack overflow. The previously
stored information is then overwritten and there-
fore lost. The stack also wraps in case of an under-
flow.
15
8
1
0
7
0
0
0
0
0
0
0
The stack is used to save the return address dur-
ing a subroutine call and the CPU context during
an interrupt. The user may also directly manipulate
the stack by means of the PUSH and POP instruc-
tions. In the case of an interrupt, the PCL is stored
at the first location pointed to by the SP. Then the
other registers are stored in the next locations as
shown in Figure 6.
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
The Stack Pointer is a 16-bit register which is al-
ways pointing to the next free location in the stack.
It is then decremented after data has been pushed
onto the stack and incremented before data is
popped from the stack (see Figure 6).
– When an interrupt is received, the SP is decre-
mented and the context is pushed on the stack.
Since the stack is 256 bytes deep, the 8th most
significant bits are forced by hardware. Following
an MCU Reset, or after a Reset Stack Pointer in-
struction (RSP), the Stack Pointer contains its re-
set value (the SP7 to SP0 bits are set) which is the
stack higher address.
– On return from interrupt, the SP is incremented
and the context is popped from the stack.
A subroutine call occupies two locations and an in-
terrupt five locations in the stack area.
Figure 6. Stack Manipulation Example
CALL
Subroutine
RET
or RSP
PUSH Y
POP Y
IRET
Interrupt
Event
@ 0100h
SP
SP
SP
Y
CC
A
CC
A
CC
A
X
X
X
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
SP
SP
PCH
PCL
PCH
PCL
SP
@ 01FFh
Stack Higher Address = 01FFh
0100h
Stack Lower Address =
13/87
13
ST72121
3 CLOCKS, RESET, INTERRUPTS & POWER SAVING MODES
3.1 CLOCK SYSTEM
3.1.1 General Description
The MCU accepts either a crystal or ceramic reso-
nator, or an external clock signal to drive the inter-
nal oscillator. The internal clock (fCPU) is derived
Figure 7. External Clock Source Connections
from the external oscillator frequency (fOSC). The
external Oscillator clock is first divided by 2, and
an additional division factor of 2, 4, 8, or 16 can be
applied, in Slow Mode, to reduce the frequency of
the fCPU; this clock signal is also routed to the on-
chip peripherals. The CPU clock signal consists of
a square wave with a duty cycle of 50%.
OSCIN
OSCOUT
NC
EXTERNAL
CLOCK
The internal oscillator is designed to operate with
an AT-cut parallel resonant quartz crystal resona-
tor in the frequency range specified for fosc. The
circuit shown in Figure 8 is recommended when
using a crystal, and Table 4 lists the recommend-
ed capacitance and feedback resistance values.
The crystal and associated components should be
mounted as close as possible to the input pins in
order to minimize output distortion and start-up
stabilisation time.
Figure 8. Crystal/Ceramic Resonator
OSCIN
OSCOUT
Use of an external CMOS oscillator is recom-
mended when crystals outside the specified fre-
quency ranges are to be used.
R
P
3.1.2 External Clock
An external clock may be applied to the OSCIN in-
put with the OSCOUT pin not connected, as
shown on Figure 7.
C
C
OSCIN
OSCOUT
Table 4 Recommended Values for 16 MHz
Crystal Resonator (C0 < 7pF)
Figure 9. Clock Prescaler Block Diagram
R
40 Ω
56pF
60 Ω
47pF
150 Ω
22pF
SMAX
C
OSCIN
%2
%2,4,8,16
f
C
CPU
56pF
47pF
22pF
OSCOUT
to CPU and
Peripherals
OSCIN
R
OSCOUT
1-10 MΩ
1-10 MΩ
1-10 MΩ
P
R
P
RSMAX: Parasitic series resistance of the quartz
crystal (upper limit).
C0: Parasitic shunt capacitance of the quartz crys-
tal (upper limit 7pF).
C
C
OSCIN
OSCOUT
COSCOUT, COSCIN: Maximum total capacitance on
pins OSCIN and OSCOUT (the value includes the
external capacitance tied to the pin plus the para-
sitic capacitance of the board and of the device).
Rp: External shunt resistance. Recommended val-
ue for oscillator stability is 1MΩ.
14/87
14
ST72121
3.2 RESET
3.2.1 Introduction
nised. At the end of the Power-On Reset cycle, the
MCU may be held in the Reset condition by an Ex-
ternal Reset signal. The RESET pin may thus be
used to ensure VDD has risen to a point where the
MCU can operate correctly before the user pro-
gram is run. Following a Power-On Reset event, or
after exiting Halt mode, a 4096 CPU Clock cycle
delay period is initiated in order to allow the oscil-
lator to stabilise and to ensure that recovery has
taken place from the Reset state.
There are four sources of Reset:
– RESET pin (external source)
– Power-On Reset (Internal source)
– WATCHDOG (Internal Source)
– Low Voltage Detection Reset (internal source)
The Reset Service Routine vector is located at ad-
dress FFFEh-FFFFh.
During the Reset cycle, the device Reset pin acts
as an output that is pulsed low. In its high state, an
internal pull-up resistor is connected to the Reset
pin. This resistor can be pulled low by external cir-
cuitry to reset the device.
3.2.2 External Reset
The RESET pin is both an input and an open-drain
output with integrated pull-up resistor. When one
of the internal Reset sources is active, the Reset
pin is driven low to reset the whole application.
The Reset pin is an asynchronous signal which
plays a major role in EMS performance. In a noisy
environment, the best external network is a double
capacitive decoupling consisting of 0.1 µF to VSS
3.2.3 Reset Operation
The duration of the Reset condition, which is also
reflected on the output pin, is fixed at 4096 internal
CPU Clock cycles. A Reset signal originating from
an external source must have a duration of at least
1.5 internal CPU Clock cycles in order to be recog-
and 0.1 µF to VDD
.
Figure 10. Reset Block Diagram
INTERNAL
RESET
OSCILLATOR
SIGNAL
TO ST7
RESET
RESET
V
DD
POWER-ON RESET
WATCHDOG RESET
LOW VOLTAGE DETECTOR RESET
15/87
15
ST72121
RESET (Cont’d)
3.2.4 Low Voltage Detector Reset
cases, it is recommended to use devices without
the LVD Reset option and to rely on the watchdog
function to detect application runaway conditions.
The on-chip Low Voltage Detector (LVD) gener-
ates a static reset when the supply voltage is be-
low a reference value. The LVD functions both
during power-on as well as when the power supply
drops (brown-out). The reference value for a volt-
age drop is lower than the reference value for pow-
er-on in order to avoid a parasitic reset when the
MCU starts running and sinks current on the sup-
ply (hysteresis).
Figure 11. Low Voltage Detector Reset Function
LOW VOLTAGE
V
DD
DETECTOR RESET
The LVD Reset circuitry generates a reset when
VDD is below:
RESET
FROM
WATCHDOG
RESET
VLVDUP when VDD is rising
VLVDDOWN when VDD is falling
Provided the minimun VDD value (guaranteed for
the oscillator frequency) is above VLVDDOWN , the
MCU can only be in two modes:
Figure 12. Low Voltage Detector Reset Signal
V
LVDUP
- under full software control or
- in static safe reset
V
LVDDOWN
In this condition, secure operation is always en-
sured for the application without the need for ex-
ternal reset hardware.
V
DD
RESET
During a Low Voltage Detector Reset, the RESET
pin is held low, thus permitting the MCU to reset
other devices.
Note: See electrical characteristics for values of
VLVDUP and VLVDDOWN
In noisy environments, the power supply may drop
for short periods and cause the Low Voltage De-
tector to generate a Reset too frequently. In such
Figure 13. Temporization timing diagram after an internal Reset
V
LVDUP
V
DD
Temporization (4096 CPU clock cycles)
$FFFE
Addresses
16/87
16
ST72121
3.3 INTERRUPTS
The ST7 core may be interrupted by one of two dif-
ferent methods: maskable hardware interrupts as
listed in the Interrupt Mapping Table and a non-
maskable software interrupt (TRAP). The Interrupt
processing flowchart is shown in Figure 14.
The maskable interrupts must be enabled clearing
the I bit in order to be serviced. However, disabled
interrupts may be latched and processed when
they are enabled (see external interrupts subsec-
tion).
Halt low power mode (refer to the “Exit from HALT“
column in the Interrupt Mapping Table).
External Interrupts
External interrupt vectors can be loaded in the PC
register if the corresponding external interrupt oc-
curred and if the I bit is cleared. These interrupts
allow the processor to leave the Halt low power
mode.
When an interrupt has to be serviced:
The external interrupt polarity is selected through
the miscellaneous register or interrupt register (if
available).
– Normal processing is suspended at the end of
the current instruction execution.
External interrupt triggered on edge will be latched
and the interrupt request automatically cleared
upon entering the interrupt service routine.
– The PC, X, A and CC registers are saved onto
the stack.
– The I bit of the CC register is set to prevent addi-
tional interrupts.
If more than one input pin of a group connected to
the same interrupt line is selected simultaneously,
this will be logically ORed.
– The PC is then loaded with the interrupt vector of
the interrupt to service and the first instruction of
the interrupt service routine is fetched (refer to
the Interrupt Mapping Table for vector address-
es).
Warning: The type of sensitivity defined in the
Miscellaneous or Interrupt register (if available)
applies to the EI source. In case of an ORed
source (as described on the I/O ports section). A
low level on an I/O pin configured as input with in-
terrupt, masks the interrupt request even in case
of rising-edge sensitivity.
The interrupt service routine should finish with the
IRET instruction which causes the contents of the
saved registers to be recovered from the stack.
Note: As a consequence of the IRET instruction,
the I bit will be cleared and the main program will
resume.
Peripheral Interrupts
Different peripheral interrupt flags in the status
register are able to cause an interrupt when they
are active if both:
Priority management
By default, a servicing interrupt can not be inter-
rupted because the I bit is set by hardware enter-
ing in interrupt routine.
– The I bit of the CC register is cleared.
– The corresponding enable bit is set in the control
register.
In the case several interrupts are simultaneously
pending, an hardware priority defines which one
will be serviced first (see the Interrupt Mapping Ta-
ble).
If any of these two conditions is false, the interrupt
is latched and thus remains pending.
Clearing an interrupt request is done by:
Non Maskable Software Interrupts
– writing “0” to the corresponding bit in the status
register or
This interrupt is entered when the TRAP instruc-
tion is executed regardless of the state of the I bit.
It will be serviced according to the flowchart on
Figure 14.
– an access to the status register while the flag is
set followed by a read or write of an associated
register.
Note: the clearing sequence resets the internal
latch. A pending interrupt (i.e. waiting for being en-
abled) will therefore be lost if the clear sequence is
executed.
Interrupts and Low power mode
All interrupts allow the processor to leave the Wait
low power mode. Only external and specific men-
tioned interrupts allow the processor to leave the
17/87
17
ST72121
INTERRUPTS (Cont’d)
Figure 14. Interrupt Processing Flowchart
FROM RESET
N
BIT I SET
Y
N
INTERRUPT
FETCH NEXT INSTRUCTION
Y
N
STACK PC, X, A, CC
SET I BIT
EXECUTE INSTRUCTION
IRET
Y
LOAD PC FROM INTERRUPT VECTOR
RESTORE PC, X, A, CC FROM STACK
THIS CLEARS I BIT BY DEFAULT
VR01172D
18/87
18
ST72121
Table 5. Interrupt Mapping
Source
Exit
from
HALT
Register
Label
Vector
Address
Priority
Order
Description
Flag
Block
RESET
TRAP
Reset
N/A
N/A
N/A
N/A
yes
no
FFFEh-FFFFh
FFFCh-FFFDh
FFFAh-FFFBh
FFF8h-FFF9h
FFF6h-FFF7h
FFF4h-FFF5h
FFF2h-FFF3h
FFF0h-FFF1h
FFEEh-FFEFh
Highest
Priority
Software
NOT USED
NOT USED
EI0
EI1
EI2
EI3
Ext. Interrupt (Ports PA0:PA3)
Ext. Interrupt (Ports PF0:PF2)
Ext. Interrupt (Ports PB0:PB3)
Ext. Interrupt (Ports PB4:PB7)
NOT USED
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
yes
Transfer Complete
Mode Fault
SPIF
MODF
ICF1_A
OCF1_A
ICF2_A
OCF2_A
TOF_A
ICF1_B
OCF1_B
ICF2_B
OCF2_B
TOF_B
TDRE
SPI
SPISR
TASR
FFECh-FFEDh
Input Capture 1
Output Compare 1
Input Capture 2
TIMER A
FFEAh-FFEBh
Output Compare 2
Timer Overflow
Input Capture 1
Output Compare 1
Input Capture 2
no
TIMER B
TBSR
FFE8h-FFE9h
FFE6h-FFE7h
Output Compare 2
Timer Overflow
Transmit Buffer Empty
Transmit Complete
Receive Buffer Full
Idle Line Detect
TC
SCI
SCISR
RDRF
IDLE
Lowest
Priority
Overrun
OR
NOT USED
FFE4h-FFE5h
FFE2h-FFE3h
FFE0h-FFE1h
NOT USED
NOT USED
19/87
19
ST72121
3.4 POWER SAVING MODES
3.4.1 Introduction
Figure 15. WAIT Flow Chart
There are three Power Saving modes. Slow Mode
is selected by setting the relevant bits in the Mis-
cellaneous register. Wait and Halt modes may be
entered using the WFI and HALT instructions.
WFI INSTRUCTION
3.4.2 Slow Mode
OSCILLATOR
PERIPH. CLOCK
CPU CLOCK
I-BIT
ON
In Slow mode, the oscillator frequency can be di-
vided by a value defined in the Miscellaneous
Register. The CPU and peripherals are clocked at
this lower frequency. Slow mode is used to reduce
power consumption, and enables the user to adapt
clock frequency to available supply voltage.
ON
OFF
CLEARED
3.4.3 Wait Mode
N
Wait mode places the MCU in a low power con-
sumption mode by stopping the CPU. All peripher-
als remain active. During Wait mode, the I bit (CC
Register) is cleared, so as to enable all interrupts.
All other registers and memory remain unchanged.
The MCU will remain in Wait mode until an Inter-
rupt or Reset occurs, whereupon the Program
Counter branches to the starting address of the In-
terrupt or Reset Service Routine.
RESET
N
Y
INTERRUPT
Y
OSCILLATOR
ON
ON
PERIPH. CLOCK
CPU CLOCK
I-BIT
The MCU will remain in Wait mode until a Reset or
an Interrupt occurs, causing it to wake up.
ON
SET
Refer to Figure 15 below.
4096 CPU CLOCK
CYCLES DELAY
OSCILLATOR
ON
ON
PERIPH. CLOCK
CPU CLOCK
I-BIT
ON
SET
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Note: Before servicing an interrupt, the CC register is
pushed on the stack. The I-Bit is set during the inter-
rupt routine and cleared when the CC register is
popped.
20/87
20
ST72121
POWER SAVING MODES (Cont’d)
3.4.4 Halt Mode
Figure 16. HALT Flow Chart
The Halt mode is the MCU lowest power con-
sumption mode. The Halt mode is entered by exe-
cuting the HALT instruction. The internal oscillator
is then turned off, causing all internal processing to
be stopped, including the operation of the on-chip
peripherals. The Halt mode cannot be used when
the watchdog is enabled, if the HALT instruction is
executed while the watchdog system is enabled, a
watchdog reset is generated thus resetting the en-
tire MCU.
When entering Halt mode, the I bit in the CC Reg-
ister is cleared so as to enable External Interrupts.
If an interrupt occurs, the CPU becomes active.
The MCU can exit the Halt mode upon reception of
an interrupt or a reset. Refer to the Interrupt Map-
ping Table. The oscillator is then turned on and a
stabilization time is provided before releasing CPU
operation. The stabilization time is 4096 CPU clock
cycles.
HALT INSTRUCTION
WDG
Y
WATCHDOG
RESET
ENABLED?
N
OSCILLATOR
OFF
PERIPH. CLOCK
CPU CLOCK
I-BIT
OFF
OFF
CLEARED
N
After the start up delay, the CPU continues oper-
ation by servicing the interrupt which wakes it up or
by fetching the reset vector if a reset wakes it up.
RESET
N
EXTERNAL
INTERRUPT
Y
1)
Y
OSCILLATOR
ON
2)
PERIPH. CLOCK
CPU CLOCK
I-BIT
OFF
ON
SET
4096 CPU CLOCK
CYCLES DELAY
OSCILLATOR
ON
ON
PERIPH. CLOCK
CPU CLOCK
I-BIT
ON
SET
FETCH RESET VECTOR
OR SERVICE INTERRUPT
1) or some specific interrupts
2) if reset PERIPH. CLOCK = ON ; if interrupt
PERIPH. CLOCK = OFF
Note: Before servicing an interrupt, the CC register is
pushed on the stack. The I-Bit is set during the inter-
rupt routine and cleared when the CC register is
popped.
21/87
21
ST72121
3.5 MISCELLANEOUS REGISTER
The Miscellaneous register allows to select the
SLOW operating mode, the polarity of external in-
terrupt requests and to output the internal clock.
Bit 4:3 = PEI1-PEI0 External Interrupt EI1 and EI0
Polarity Options.
These bits are set and cleared by software. They
determine which event on EI0 and EI1 causes the
external interrupt according to Table 7.
Register Address: 0020h
—
Read/Write
Reset Value: 0000 0000 (00h)
Table 7. EI0 and EI1 External Interrupt Polarity
Options
7
0
MODE
PEI1
PEI0
PEI3 PEI2 MCO PEI1 PEI0 PSM1 PSM0 SMS
Falling edge and low level
(Reset state)
0
0
Bit 7:6 = PEI[3:2] External Interrupt EI3 and EI2
Polarity Options.
Falling edge only
Rising edge only
1
0
1
0
1
1
These bits are set and cleared by software. They
determine which event on EI2 and EI3 causes the
external interrupt according to Table 6.
Rising and falling edge
Table 6. EI2 and EI3 External Interrupt Polarity
Options
Bit 2:1 = PSM[1:0] Prescaler for Slow Mode
MODE
PEI3
PEI2
These bits are set and cleared by software. They
determine the CPU clock when the SMS bit is set
according to the following table.
Falling edge and low level
(Reset state)
0
0
Falling edge only
Rising edge only
1
0
1
0
1
1
Table 8. fCPU Value in Slow Mode
PSM1 PSM0
fCPU Value
fOSC / 4
Rising and falling edge
0
0
1
1
0
1
0
1
fOSC / 16
fOSC / 8
Bit 5 = MCO Main Clock Out
fOSC / 32
This bit is set and cleared by software. When set it
allows to output the Internal Clock on PF0 I/O.
0 - PF0 is a normal I/O port.
Bit 0 = SMS Slow Mode Select
1 - fCPU outputs on PF0 pin.
This bit is set and cleared by software.
0: Normal Mode - fCPU = fOSC/ 2
(Reset state)
1: Slow Mode - the fCPU value is determined by the
PSM1 and PSM0 bits.
22/87
22
ST72121
4 ON-CHIP PERIPHERALS
4.1 I/O PORTS
4.1.1 Introduction
Interrupt function
The I/O ports offer different functional modes:
– transfer of data through digital inputs and outputs
and for specific pins:
When an I/O is configured in Input with Interrupt,
an event on this I/O can generate an external In-
terrupt request to the CPU. The interrupt polarity is
given independently according to the description
mentioned in the Miscellaneous register or in the
interrupt register (where available).
– analog signal input (ADC)
– alternate signal input/output for the on-chip pe-
ripherals.
Each pin can independently generate an Interrupt
request.
– external interrupt generation
Each external interrupt vector is linked to a dedi-
cated group of I/O port pins (see Interrupts sec-
tion). If more than one input pin is selected simul-
taneously as interrupt source, this is logically
ORed. For this reason if one of the interrupt pins is
tied low, it masks the other ones.
An I/O port is composed of up to 8 pins. Each pin
can be programmed independently as digital input
(with or without interrupt generation) or digital out-
put.
4.1.2 Functional Description
Each port is associated to 2 main registers:
– Data Register (DR)
4.1.2.2 Output Mode
The pin is configured in output mode by setting the
corresponding DDR register bit.
– Data Direction Register (DDR)
and some of them to an optional register:
– Option Register (OR)
In this mode, writing “0” or “1” to the DR register
applies this digital value to the I/O pin through the
latch. Then reading the DR register returns the
previously stored value.
Each I/O pin may be programmed using the corre-
sponding register bits in DDR and OR registers: bit
X corresponding to pin X of the port. The same cor-
respondence is used for the DR register.
Note: In this mode, the interrupt function is disa-
bled.
4.1.2.3 Digital Alternate Function
The following description takes into account the
OR register, for specific ports which do not provide
this register refer to the I/O Port Implementation
Section 4.1.2.5. The generic I/O block diagram is
shown on Figure 18.
When an on-chip peripheral is configured to use a
pin, the alternate function is automatically select-
ed. This alternate function takes priority over
standard I/O programming. When the signal is
coming from an on-chip peripheral, the I/O pin is
automatically configured in output mode (push-pull
or open drain according to the peripheral).
4.1.2.1 Input Modes
The input configuration is selected by clearing the
corresponding DDR register bit.
When the signal is going to an on-chip peripheral,
the I/O pin has to be configured in input mode. In
this case, the pin’s state is also digitally readable
by addressing the DR register.
In this case, reading the DR register returns the
digital value applied to the external I/O pin.
Different input modes can be selected by software
through the OR register.
Notes:
1. Input pull-up configuration can cause an unex-
pected value at the input of the alternate peripher-
al input.
2. When the on-chip peripheral uses a pin as input
and output, this pin must be configured as an input
(DDR = 0).
Notes:
1. All the inputs are triggered by a Schmitt trigger.
2. When switching from input mode to output
mode, the DR register should be written first to
output the correct value as soon as the port is con-
figured as an output.
Warning: The alternate function must not be acti-
vated as long as the pin is configured as input with
interrupt, in order to avoid generating spurious in-
terrupts.
23/87
23
ST72121
I/O PORTS (Cont’d)
4.1.2.4 Analog Alternate Function
4.1.2.5 I/O Port Implementation
When the pin is used as an ADC input the I/O must
be configured as input, floating. The analog multi-
plexer (controlled by the ADC registers) switches
the analog voltage present on the selected pin to
the common analog rail which is connected to the
ADC input.
The hardware implementation on each I/O port de-
pends on the settings in the DDR and OR registers
and specific feature of the I/O port such as ADC In-
put (see Figure 18) or true open drain. Switching
these I/O ports from one state to another should
be done in a sequence that prevents unwanted
side effects. Recommended safe transitions are il-
lustrated in Figure 17. Other transitions are poten-
tially risky and should be avoided, since they are
likely to present unwanted side-effects such as
spurious interrupt generation.
It is recommended not to change the voltage level
or loading on any port pin while conversion is in
progress. Furthermore it is recommended not to
have clocking pins located close to a selected an-
alog pin.
Warning: The analog input voltage level must be
within the limits stated in the Absolute Maximum
Ratings.
Figure 17. Recommended I/O State Transition Diagram
OUTPUT
push-pull
INPUT
no interrupt
OUTPUT
INPUT
with interrupt
open-drain
24/87
24
ST72121
I/O PORTS (Cont’d)
Figure 18. I/O Block Diagram
ALTERNATE ENABLE
1
V
ALTERNATE
OUTPUT
DD
M
U
X
P-BUFFER
(SEE TABLE BELOW)
0
DR
LATCH
ALTERNATE
ENABLE
PULL-UP (SEE TABLE BELOW)
PULL-UP
CONDITION
DDR
LATCH
PAD
OR
ANALOG ENABLE
(ADC)
LATCH
(SEE TABLE BELOW)
ANALOG
SWITCH
OR SEL
(SEE NOTE BELOW)
DDR SEL
N-BUFFER
ALTERNATE
ENABLE
1
0
DR SEL
M
U
X
GND
ALTERNATE INPUT
CMOS
SCHMITT TRIGGER
POLARITY
SEL
FROM
OTHER
BITS
EXTERNAL
INTERRUPT
SOURCE (EIx)
Table 9. Port Mode Configuration
Configuration Mode
Floating
Pull-up
P-buffer
0
0
Pull-up
1
0
Push-pull
0
1
True Open Drain
Open Drain (logic level)
not present
0
not present
0
Legend:
Notes:
– No OR Register on some ports (see register map).
– ADC Switch on ports with analog alternate functions.
0 -
1 -
present, not activated
present and activated
25/87
25
ST72121
I/O PORTS (Cont’d)
Table 10. Port Configuration
Input (DDR = 0)
OR = 0
Output (DDR = 1)
Port
Pin name
OR = 1
OR = 0
open-drain
OR =1
PA3
PA4:PA7
PB0:PB4
PC0:PC7
PD0:PD5
PE0:PE1
PF0:PF2
floating*
pull-up with interrupt
push-pull
Port A
floating*
true open drain, high sink capability
Port B
Port C
Port D
Port E
floating*
floating*
floating*
floating*
floating*
floating*
pull-up with interrupt
pull-up
open-drain
open-drain
open-drain
open-drain
open-drain
open-drain
push-pull
push-pull
push-pull
push-pull
push-pull
push-pull
pull-up
pull-up
pull-up with interrupt
pull-up
Port F
PF4, PF6, PF7
* Reset state (The bits corresponding to unavailable pins are forced to 1 by hardware, this affects the reset status value).
Warning: All bits of the DDR register which correspond to unconnected I/Os must be left at their reset value. They must
not be modified by the user otherwise a spurious interrupt may be generated.
26/87
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ST72121
I/O PORTS (Cont’d)
4.1.3 Register Description
4.1.3.1 Data registers
4.1.3.3 Option registers
Port A Data Register (PADR)
Port B Data Register (PBDR)
Port C Data Register (PCDR)
Port D Data Register (PDDR)
Port E Data Register (PEDR)
Port F Data Register (PFDR)
Port A Option Register (PAOR)
Port B Option Register (PBOR)
Port C Option Register (PBOR)
Port D Option Register (PBOR)
Port E Option Register (PBOR)
Port F Option Register (PFOR)
Read/Write
Read/Write
Reset Value: 0000 0000 (00h)
Reset Value: see Register Memory Map Table 3
7
0
7
0
D7
D6
D5
D4
D3
D2
D1
D0
O7
O6
O5
O4
O3
O2
O1
O0
Bit 7:0 = D7-D0 Data Register 8 bits.
Bit 7:0 = O7-O0 Option Register 8 bits.
The DR register has a specific behaviour accord-
ing to the selected input/output configuration. Writ-
ing the DR register is always taken in account
even if the pin is configured as an input. Reading
the DR register returns either the DR register latch
content (pin configured as output) or the digital val-
ue applied to the I/O pin (pin configured as input).
The OR register allow to distinguish in input mode
if the interrupt capability or the floating configura-
tion is selected.
In output mode it select push-pull or open-drain
capability.
Each bit is set and cleared by software.
Input mode:
0: floating input
1: input pull-up with interrupt
4.1.3.2 Data direction registers
Port A Data Direction Register (PADDR)
Port B Data Direction Register (PBDDR)
Port C Data Direction Register (PCDDR)
Port D Data Direction Register (PDDDR)
Port E Data Direction Register (PEDDR)
Port F Data Direction Register (PFDDR)
Output mode:
0: open-drain configuration
1: push-pull configuration
Read/Write
Reset Value: 0000 0000 (00h) (input mode)
7
0
DD7
DD6
DD5
DD4
DD3
DD2
DD1
DD0
Bit 7:0 = DD7-DD0 Data Direction Register 8 bits.
The DDR register gives the input/output direction
configuration of the pins. Each bits is set and
cleared by software.
0: Input mode
1: Output mode
27/87
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ST72121
I/O PORTS (Cont’d)
Table 11. I/O Port Register Map
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
0000h
0001h
0002h
0004h
0005h
0006h
0008h
0009h
000Ah
000Ch
000Dh
000Eh
0010h
0011h
0012h
0014h
0015h
0016h
PADR
D7
DD7
O7
D6
DD6
O6
D5
DD5
O5
D4
DD4
O4
D3
DD3
O3
D2
DD2
O2
D1
DD1
O1
D0
DD0
O0
PADDR
PAOR
PCDR
PCDDR
PCOR
PBDR
PBDDR
PBOR
PEDR
D7
D6
D5
D4
D3
D2
D1
D0
DD7
O7
DD6
O6
DD5
O5
DD4
O4
DD3
O3
DD2
O2
DD1
O1
DD0
O0
D7
D6
D5
D4
D3
D2
D1
D0
DD7
O7
DD6
O6
DD5
O5
DD4
O4
DD3
O3
DD2
O2
DD1
O1
DD0
O0
D7
D6
D5
D4
D3
D2
D1
D0
PEDDR
PEOR
PDDR
PDDDR
PDOR
PFDR
DD7
O7
DD6
O6
DD5
O5
DD4
O4
DD3
O3
DD2
O2
DD1
O1
DD0
O0
D7
D6
D5
D4
D3
D2
D1
D0
DD7
O7
DD6
O6
DD5
O5
DD4
O4
DD3
O3
DD2
O2
DD1
O1
DD0
O0
D7
D6
D5
D4
D3
D2
D1
D0
PFDDR
PFOR
DD7
O7
DD6
O6
DD5
O5
DD4
O4
DD3
O3
DD2
O2
DD1
O1
DD0
O0
28/87
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ST72121
4.2 WATCHDOG TIMER (WDG)
4.2.1 Introduction
4.2.2 Main Features
Programmable timer (64 increments of 12288
CPU cycles)
Programmable reset
Reset (if watchdog activated) after a HALT
instruction or when the T6 bit reaches zero
Hardware Watchdog selectable by option byte.
The Watchdog timer is used to detect the occur-
rence of a software fault, usually generated by ex-
ternal interference or by unforeseen logical condi-
tions, which causes the application program to
abandon its normal sequence. The Watchdog cir-
cuit generates an MCU reset on expiry of a pro-
grammed time period, unless the program refresh-
es the counter’s contents before the T6 bit be-
comes cleared.
Watchdog Reset indicated by status flag (in
versions with Safe Reset option only)
Figure 19. Watchdog Block Diagram
RESET
WATCHDOG CONTROL REGISTER (CR)
T5 T0
WDGA T6
T1
T4
T2
T3
7-BIT DOWNCOUNTER
CLOCK DIVIDER
fCPU
÷12288
29/87
29
ST72121
WATCHDOG TIMER (Cont’d)
4.2.3 Functional Description
4.2.5 Register Description
CONTROL REGISTER (CR)
Read/Write
The counter value stored in the CR register (bits
T6:T0), is decremented every 12,288 machine cy-
cles, and the length of the timeout period can be
programmed by the user in 64 increments.
Reset Value: 0111 1111 (7Fh)
If the watchdog is activated (the WDGA bit is set)
and when the 7-bit timer (bits T6:T0) rolls over
from 40h to 3Fh (T6 becomes cleared), it initiates
a reset cycle pulling low the reset pin for typically
500ns.
7
0
WDGA T6
T5
T4
T3
T2
T1
T0
Bit 7 = WDGA Activation bit.
The application program must write in the CR reg-
ister at regular intervals during normal operation to
prevent an MCU reset. The value to be stored in
the CR register must be between FFh and C0h
(see Table 12):
This bit is set by software and only cleared by
hardware after a reset. When WDGA = 1, the
watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled
– The WDGA bit is set (watchdog enabled)
Note: This bit is not used if the hardware watch-
dog otion is enabled by option byte.
– The T6 bit is set to prevent generating an imme-
diate reset
Bit 6-0 = T[6:0] 7-bit timer (MSB to LSB).
These bits contain the decremented value. A reset
is produced when it rolls over from 40h to 3Fh (T6
become cleared).
– The T5:T0 bits contain the number of increments
which represents the time delay before the
watchdog produces a reset.
Table 12. Watchdog Timing (fCPU = 8 MHz)
STATUS REGISTER (SR)
Read/Write
CR Register
initial value
WDG timeout period
(ms)
Reset Value*: 0000 0000 (00h)
Max
Min
FFh
C0h
98.304
1.536
7
-
0
-
-
-
-
-
-
WDOGF
Notes: Following a reset, the watchdog is disa-
bled. Once activated it cannot be disabled, except
by a reset.
Bit 0 = WDOGF Watchdog flag.
This bit is set by a watchdog reset and cleared by
software or a power on/off reset. This bit is useful
for distinguishing power/on off or external reset
and watchdog reset.
The T6 bit can be used to generate a software re-
set (the WDGA bit is set and the T6 bit is cleared).
If the watchdog is activated, the HALT instruction
will generate a Reset.
0: No Watchdog reset occurred
4.2.4 Hardware Watchdog Option
1: Watchdog reset occurred
If Hardware Watchdog Is selected by option byte,
the watchdog is always active and the WDGA bit in
the CR is not used.
* Only by software and power on/off reset
Note: This register is not used in versions without
LVD Reset.
Refer to the device-specific Option Byte descrip-
tion.
Table 13. WDG Register Map
Address (Hex.) Register Name
7
6
5
4
3
T6.. T0
-
2
1
0
2A
2B
CR
SR
WDGA
-
-
-
-
-
-
WDOGF
30/87
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ST72121
4.3 16-BIT TIMER
4.3.1 Introduction
The timer consists of a 16-bit free-running counter
driven by a programmable prescaler.
4.3.3 Functional Description
4.3.3.1 Counter
It may be used for a variety of purposes, including
pulse length measurement of up to two input sig-
nals (input capture) or generation of up to two out-
put waveforms (output compare and PWM).
The principal block of the Programmable Timer is
a 16-bit free running increasing counter and its as-
sociated 16-bit registers:
Counter Registers
Pulse lengths and waveform periods can be mod-
ulated from a few microseconds to several milli-
seconds using the timer prescaler and the CPU
clock prescaler.
– Counter High Register (CHR) is the most sig-
nificant byte (MSB).
– Counter Low Register (CLR) is the least sig-
nificant byte (LSB).
Alternate Counter Registers
4.3.2 Main Features
– Alternate Counter High Register (ACHR) is the
most significant byte (MSB).
Programmableprescaler:fCPU dividedby 2, 4or8.
Overflow status flag and maskable interrupt
External clock input (must be at least 4 times
slower than the CPUclock speed) with the choice
of active edge
Output compare functions with
– 2 dedicated 16-bit registers
– 2 dedicated programmable signals
– 2 dedicated status flags
– Alternate Counter Low Register (ACLR) is the
least significant byte (LSB).
These two read-only 16-bit registers contain the
same value but with the difference that reading the
ACLR register does not clear the TOF bit (overflow
flag), (see note at the end of paragraph titled 16-bit
read sequence).
Writing in the CLR register or ACLR register resets
the free running counter to the FFFCh value.
– 1 dedicated maskable interrupt
Input capture functions with
The timer clock depends on the clock control bits
of the CR2 register, as illustrated in Table 14. The
value in the counter register repeats every
131.072, 262.144 or 524.288 internal processor-
clock cycles depending on the CC1 and CC0 bits.
– 2 dedicated 16-bit registers
– 2 dedicated active edge selection signals
– 2 dedicated status flags
– 1 dedicated maskable interrupt
Pulse width modulation mode (PWM)
One pulse mode
5 alternate functions on I/O ports (ICAP1, ICAP2,
OCMP1, OCMP2, EXTCLK)*
The Block Diagram is shown in Figure 20.
*Note: Some external pins are not available on all
devices. Refer to the device pin out description.
When reading an input signal which is not availa-
ble on an external pin, the value will always be ‘1’.
31/87
31
ST72121
16-BIT TIMER (Cont’d)
Figure 20. Timer Block Diagram
ST7 INTERNAL BUS
f
CPU
MCU-PERIPHERAL INTERFACE
8 low
8-bit
8 high
8
8
8
8
8
8
8
8
buffer
h
h
h
igh
EXEDG
h
w
h
w
h
w
h
low
16
INPUT
CAPTURE
REGISTER
INPUT
CAPTURE
REGISTER
OUTPUT
COMPARE
REGISTER
OUTPUT
COMPARE
REGISTER
16 BIT
FREE RUNNING
1/2
1/4
1/8
COUNTER
1
1
2
2
COUNTER
ALTERNATE
REGISTER
16
16
16
CC1 CC0
TIMER INTERNAL BUS
16
16
OVERFLOW
DETECT
EXTCLK
EDGE DETECT
CIRCUIT1
OUTPUT COMPARE
CIRCUIT
ICAP1
ICAP2
CIRCUIT
6
EDGE DETECT
CIRCUIT2
OCMP1
OCMP2
LATCH1
LATCH2
ICF1OCF1TOF ICF2OCF2 0
0
0
SR
EXEDG
ICIE OCIE TOIE FOLV2 FOLV1OLVL2 IEDG1 OLVL1
OC1E
OPM PWM CC1 CC0 IEDG2
OC2E
CR1
CR2
TIMER INTERRUPT
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ST72121
16-BIT TIMER (Cont’d)
16-bit read sequence: (from either the Counter
Register or the Alternate Counter Register).
Clearing the overflow interrupt request is done in
two steps:
1. Reading the SR register while the TOF bit is set.
2. An access (read or write) to the CLR register.
Beginning of the sequence
Notes: The TOF bit is not cleared by accesses to
ACLR register. This feature allows simultaneous
use of the overflow function and reads of the free
running counter at random times (for example, to
measure elapsed time) without the risk of clearing
the TOF bit erroneously.
Read MSB
At t0
LSB is buffered
Other
instructions
Returns the buffered
LSB value at t0
The timer is not affected by WAIT mode.
Read LSB
At t0 +∆t
In HALT mode, the counter stops counting until the
mode is exited. Counting then resumes from the
previous count (MCU awakened by an interrupt) or
from the reset count (MCU awakened by a Reset).
Sequence completed
The user must read the MSB first, then the LSB
value is buffered automatically.
This buffered value remains unchanged until the
16-bit read sequence is completed, even if the
user reads the MSB several times.
4.3.3.2 External Clock
The external clock (where available) is selected if
CC0=1 and CC1=1 in CR2 register.
After a complete reading sequence, if only the
CLR register or ACLR register are read, they re-
turn the LSB of the count value at the time of the
read.
The status of the EXEDG bit determines the type
of level transition on the external clock pin EXT-
CLK that will trigger the free running counter.
The counter is synchronised with the falling edge
of the internal CPU clock.
An overflow occurs when the counter rolls over
from FFFFh to 0000h then:
At least four falling edges of the CPU clock must
occur between two consecutive active edges of
the external clock; thus the external clock frequen-
cy must be less than a quarter of the CPU clock
frequency.
– The TOF bit of the SR register is set.
– A timer interrupt is generated if:
– TOIE bit of the CR1 register is set and
– I bit of the CC register is cleared.
If one of these conditions is false, the interrupt re-
mains pending to be issued as soon as they are
both true.
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ST72121
16-BIT TIMER (Cont’d)
Figure 21. Counter Timing Diagram, internal clock divided by 2
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
FFFD FFFE FFFF 0000 0001 0002 0003
COUNTER REGISTER
OVERFLOW FLAG TOF
Figure 22. Counter Timing Diagram, internal clock divided by 4
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
FFFC
FFFD
0000
0001
COUNTER REGISTER
OVERFLOW FLAG TOF
Figure 23. Counter Timing Diagram, internal clock divided by 8
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
0000
FFFC
FFFD
COUNTER REGISTER
OVERFLOW FLAG TOF
34/87
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ST72121
16-BIT TIMER (Cont’d)
4.3.3.3 Input Capture
When an input capture occurs:
– ICFi bit is set.
In this section, the index, i, may be 1 or 2.
The two input capture 16-bit registers (IC1R and
IC2R) are used to latch the value of the free run-
ning counter after a transition detected by the
ICAPi pin (see figure 5).
– The ICiR register contains the value of the free
running counter on the active transition on the
ICAPi pin (see Figure 25).
– A timer interrupt is generated if the ICIE bit is set
and the I bit is cleared in the CC register. Other-
wise, the interrupt remains pending until both
conditions become true.
MS Byte
ICiHR
LS Byte
ICiLR
ICiR
Clearing the Input Capture interrupt request is
done in two steps:
ICi Rregister is a read-only register.
The active transition is software programmable
through the IEDGi bit of the Control Register (CRi).
1. Reading the SR register while the ICFi bit is set.
2. An access (read or write) to the ICiLR register.
Timing resolution is one count of the free running
counter: (f
/(CC1.CC0)).
CPU
Procedure
Note: After reading the ICiHR register, transfer of
input capture data is inhibited until the ICiLR regis-
ter is also read.
To use the input capture function select the follow-
ing in the CR2 register:
The ICiR register always contains the free running
counter value which corresponds to the most re-
cent input capture.
– Select the timer clock (CC1-CC0) (see Table
14).
During HALT mode, if at least one valid input cap-
ture edge occurs on the ICAPi pin, the input cap-
ture detection circuitry is armed. This does not set
any timer flags, and does not “wake-up” the MCU.
If the MCU is awoken by an interrupt, the input
capture flag will become active, and data corre-
sponding to the first valid edge during HALT mode
will be present.
– Select the edge of the active transition on the
ICAP2 pin with the IEDG2 bit.
And select the following in the CR1 register:
– Set the ICIE bit to generate an interrupt after an
input capture.
– Select the edge of the active transition on the
ICAP1 pin with the IEDG1 bit.
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ST72121
16-BIT TIMER (Cont’d)
Figure 24. Input Capture Block Diagram
ICAP1
(Control Register 1) CR1
IEDG1
EDGE DETECT
CIRCUIT2
EDGE DETECT
CIRCUIT1
ICIE
ICAP2
(Status Register) SR
ICF1
ICF2
0
0
0
IC1R
IC2R
(Control Register 2) CR2
16-BIT
16-BIT FREE RUNNING
COUNTER
IEDG2
CC0
CC1
Figure 25. Input Capture Timing Diagram
TIMER CLOCK
FF01
FF02
FF03
COUNTER REGISTER
ICAPi PIN
ICAPi FLAG
FF03
ICAPi REGISTER
Note: Active edge is rising edge.
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ST72121
16-BIT TIMER (Cont’d)
4.3.3.4 Output Compare
Clearing the output compare interrupt request is
done by:
In this section, the index, i, may be 1 or 2.
1. Reading the SR register while the OCFi bit is
set.
This function can be used to control an output
waveform or indicating when a period of time has
elapsed.
2. An access (read or write) to the OCiLR register.
When a match is found between the Output Com-
pare register and the free running counter, the out-
put compare function:
Note: After a processor write cycle to the OCiHR
register, the output compare function is inhibited
until the OCiLR register is also written.
– Assigns pins with a programmable value if the
OCIE bit is set
If the OCiE bit is not set, the OCMPi pin is a gen-
eral I/O port and the OLVLi bit will not appear
when a match is found but an interrupt could be
generated if the OCIE bit is set.
– Sets a flag in the status register
– Generates an interrupt if enabled
Two 16-bit registers Output Compare Register 1
(OC1R) and Output Compare Register 2 (OC2R)
contain the value to be compared to the free run-
ning counter each timer clock cycle.
The value in the 16-bit OCiR register and the OLVi
bit should be changed after each successful com-
parison in order to control an output waveform or
establish a new elapsed timeout.
MS Byte
OCiHR
LS Byte
OCiLR
When the clock is divided by 2, OCFi and OCMPi
are set while the counter value equals the OCiR
register value (see Figure 27, on page 38). This
behaviour is the same in OPM or PWM mode.
OCiR
These registers are readable and writable and are
not affected by the timer hardware. A reset event
changes the OCiR value to 8000h.
When the clock is divided by 4, 8 or in external
clock mode , OCFi and OCMPi are set while the
counter value equals the OCiR register value plus
1 (see Figure 28, on page 38).
Timing resolution is one count of the free running
counter: (f
).
CPU/(CC1.CC0)
Procedure
The OCiR register value required for a specific tim-
ing application can be calculated using the follow-
ing formula:
To use the output compare function, select the fol-
lowing in the CR2 register:
– Set the OCiE bit if an output is needed then the
OCMPi pin is dedicated to the output compare i
function.
∆t f
* CPU
∆ OCiR =
t
PRESC
Where:
– Select the timer clock (CC1-CC0) (see Table
14).
∆t
= Desired output compare period (in
seconds)
And select the following in the CR1 register:
f
= Internal clock frequency
CPU
– Select the OLVLi bit to applied to the OCMPi pins
after the match occurs.
t
= Timer clock prescaler (CC1-CC0 bits,
see Table 14)
PRESC
– Set the OCIE bit to generate an interrupt if it is
needed.
The following procedure is recommended to pre-
vent the OCFi bit from being set between the time
it is read and the write to the OCiR register:
When a match is found:
– OCFi bit is set.
– Write to the OCiHR register (further compares
are inhibited).
– The OCMPi pin takes OLVLi bit value (OCMPi
pin latch is forced low during reset and stays low
until valid compares change it to a high level).
– Read the SR register (first step of the clearance
of the OCFi bit, which may be already set).
– A timer interrupt is generated if the OCIE bit is
set in the CR2 register and the I bit is cleared in
the CC register (CC).
– Write to the OCiLR register (enables the output
compare function and clears the OCFi bit).
37/87
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ST72121
16-BIT TIMER (Cont’d)
Figure 26. Output Compare Block Diagram
16 BIT FREE RUNNING
OC1E
CC1 CC0
OC2E
COUNTER
(Control Register 2) CR2
16-bit
(Control Register 1) CR1
OUTPUT COMPARE
CIRCUIT
Latch
1
OCIE
OLVL2
OLVL1
OCMP1
OCMP2
Latch
2
16-bit
OC1R
16-bit
OC2R
OCF1
OCF2
0
0
0
(Status Register) SR
Figure 27. Output Compare Timing Diagram, Internal Clock Divided by 2
INTERNAL CPU CLOCK
TIMER CLOCK
2ECF 2ED0 2ED1 2ED2
2ED3
2ED4
2ED3
COUNTER
OUTPUT COMPARE REGISTER
OUTPUT COMPARE FLAG (OCFi)
OCMPi PIN (OLVLi=1)
Figure 28. Output Compare Timing Diagram, Internal Clock Divided by 4
INTERNAL CPU CLOCK
TIMER CLOCK
2ECF 2ED0 2ED1 2ED2
2ED3
2ED4
2ED3
COUNTER
OUTPUT COMPARE REGISTER
COMPARE REGISTER LATCH
OCFi AND OCMPi PIN (OLVLi=1)
38/87
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ST72121
16-BIT TIMER (Cont’d)
4.3.3.5 Forced Compare Mode
In this section i may represent 1 or 2.
The following bits of the CR1 register are used:
– Select the timer clock CC1-CC0 (see Table
14).
One pulse mode cycle
Counter is
FOLV2 FOLV1 OLVL2
OLVL1
When
initialized
to FFFCh
event occurs
on ICAP1
When the FOLVi bit is set, the OLVLi bit is copied
to the OCMPi pin. The OLVi bit has to be toggled
in order to toggle the OCMPi pin when it is enabled
(OCiE bit=1).
OCMP1 = OLVL2
OCMP1 = OLVL1
The OCFi bit is not set, and thus no interrupt re-
quest is generated.
When
Counter
= OC1R
4.3.3.6 One Pulse Mode
One Pulse mode enables the generation of a
pulse when an external event occurs. This mode is
selected via the OPM bit in the CR2 register.
The one pulse mode uses the Input Capture1
function and the Output Compare1 function.
Then, on a valid event on the ICAP1 pin, the coun-
ter is initialized to FFFCh and OLVL2 bit is loaded
on the OCMP1 pin. When the value of the counter
is equal to the value of the contents of the OC1R
register, the OLVL1 bit is output on the OCMP1
pin, (See Figure 29).
Procedure
To use one pulse mode:
1. Load the OC1R register with the value corre-
sponding to the length of the pulse (see the for-
mula in Section 4.3.3.7).
2. Select the following in the the CR1 register:
Note: The OCF1 bit cannot be set by hardware in
one pulse mode but the OCF2 bit can generate an
Output Compare interrupt.
– Using the OLVL1 bit, select the level to be ap-
plied to the OCMP1 pin after the pulse.
– Using the OLVL2 bit, select the level to be ap-
plied to the OCMP1 pin during the pulse.
The ICF1 bit is set when an active edge occurs
and can generate an interrupt if the ICIE bit is set.
– Select the edge of the active transition on the
ICAP1 pin with the IEDG1 bit.
When the Pulse Width Modulation (PWM) and
One Pulse Mode (OPM) bits are both set, the
PWM mode is the only active one.
3. Select the following in the CR2 register:
– Set the OC1E bit, the OCMP1 pin is then ded-
icated to the Output Compare 1 function.
– Set the OPM bit.
Figure 29. One Pulse Mode Timing
....
FFFC FFFD FFFE
2ED0 2ED1 2ED2
2ED3
FFFC FFFD
COUNTER
ICAP1
OLVL2
OLVL1
OLVL2
OCMP1
compare1
Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1
39/87
39
ST72121
16-BIT TIMER (Cont’d)
4.3.3.7 Pulse Width Modulation Mode
Where:
– t = Desired output compare period (seconds)
– f = Internal clock frequency (see Miscella-
Pulse Width Modulation mode enables the gener-
ation of a signal with a frequency and pulse length
determined by the value of the OC1R and OC2R
registers.
CPU
neous register)
– t
= Timer clock prescaler (CC1-CC0
bits , see Table 14)
PRESC
The pulse width modulation mode uses the com-
plete Output Compare 1 function plus the OC2R
register.
The Output Compare 2 event causes the counter
to be initialized to FFFCh (See Figure 30).
Procedure
To use pulse width modulation mode:
Pulse Width Modulation cycle
When
1. Load the OC2R register with the value corre-
sponding to the period of the signal.
2. Load the OC1R register with the value corre-
sponding to the length of the pulse if (OLVL1=0
and OLVL2=1).
Counter
= OC1R
OCMP1 = OLVL1
3. Select the following in the CR1 register:
OCMP1 = OLVL2
– Using the OLVL1 bit, select the level to be ap-
plied to the OCMP1 pin after a successful
comparison with OC1R register.
When
Counter
= OC2R
Counter is reset
to FFFCh
– Using the OLVL2 bit, select the level to be ap-
plied to the OCMP1 pin after a successful
comparison with OC2R register.
ICF1 bit is set
4. Select the following in the CR2 register:
Note: After a write instruction to the OCiHR regis-
ter, the output compare function is inhibited until
the OCiLR register is also written.
– Set OC1E bit: the OCMP1 pin is then dedicat-
ed to the output compare 1 function.
– Set the PWM bit.
The ICF1 bit is set by hardware when the counter
reaches the OC2R value and can produce a timer
interrupt if the ICIE bit is set and the I bit is cleared.
– Select the timer clock (CC1-CC0) (see Table
14).
If OLVL1=1 and OLVL2=0 the length of the pulse
is the difference between the OC2R and OC1R
registers.
Therefore the Input Capture 1 function is inhibited
but the Input Capture 2 is available.
The OCF1 and OCF2 bits cannot be set by hard-
ware in PWM mode therefore the Output Compare
interrupt is inhibited.
The OCiR register value required for a specific tim-
ing application can be calculated using the follow-
ing formula:
When the Pulse Width Modulation (PWM) and
One Pulse Mode (OPM) bits are both set, the
PWM mode is the only active one.
t * f
t
CPU
- 5
OCiR Value =
PRESC
Figure 30. Pulse Width Modulation Mode Timing
34E2 FFFC FFFD FFFE
COUNTER
2ED0 2ED1 2ED2
34E2 FFFC
OLVL2
OLVL1
OLVL2
OCMP1
compare2
compare1
compare2
Note: OC1R=2ED0h, OC2R=34E2, OLVL1=0, OLVL2= 1
40/87
40
ST72121
16-BIT TIMER (Cont’d)
4.3.4 Register Description
Each Timer is associated with three control and
status registers, and with six pairs of data registers
(16-bit values) relating to the two input captures,
the two output compares, the counter and the al-
ternate counter.
Bit 4 = FOLV2 Forced Output Compare 2.
This bit is set and cleared by software.
0: No effect on the OCMP2 pin.
1: Forces the OLVL2 bit to be copied to the
OCMP2 pin.
CONTROL REGISTER 1 (CR1)
Read/Write
Bit 3 = FOLV1 Forced Output Compare 1.
This bit is set and cleared by software.
0: No effect on the OCMP1 pin.
Reset Value: 0000 0000 (00h)
1: Forces OLVL1 to be copied to the OCMP1 pin.
7
0
Bit 2 = OLVL2 Output Level 2.
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
This bit is copied to the OCMP2 pin whenever a
successful comparison occurs with the OC2R reg-
ister and OCxE is set in the CR2 register. This val-
ue is copied to the OCMP1 pin in One Pulse Mode
and Pulse Width Modulation mode.
Bit 7 = ICIE Input Capture Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the
ICF1 or ICF2 bit of the SR register is set.
Bit 1 = IEDG1 Input Edge 1.
This bit determines which type of level transition
on the ICAP1 pin will trigger the capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
Bit 6 = OCIE Output Compare Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the
OCF1 or OCF2 bit of the SR register is set.
Bit 0 = OLVL1 Output Level 1.
Bit 5 = TOIE Timer Overflow Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is enabled whenever the TOF
bit of the SR register is set.
The OLVL1 bit is copied to the OCMP1 pin when-
ever a successful comparison occurs with the
OC1R register and the OC1E bit is set in the CR2
register.
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ST72121
16-BIT TIMER (Cont’d)
CONTROL REGISTER 2 (CR2)
Read/Write
Bit 3, 2 = CC1-CC0 Clock Control.
Reset Value: 0000 0000 (00h)
The value of the timer clock depends on these bits:
7
0
Table 14. Clock Control Bits
Timer Clock
fCPU / 4
fCPU / 2
fCPU / 8
External Clock (where
available)
CC1
CC0
OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG
0
0
1
0
1
0
Bit 7 = OC1E Output Compare 1 Enable.
0: Output Compare 1 function is enabled, but the
OCMP1 pin is a general I/O.
1: Output Compare 1 function is enabled, the
OCMP1 pin is dedicated to the Output Compare
1 capability of the timer.
1
1
Bit 1 = IEDG2 Input Edge 2.
This bit determines which type of level transition
on the ICAP2 pin will trigger the capture.
0: A falling edge triggers the capture.
Bit 6 = OC2E Output Compare 2 Enable.
0: Output Compare 2 function is enabled, but the
OCMP2 pin is a general I/O.
1: A rising edge triggers the capture.
1: Output Compare 2 function is enabled, the
OCMP2 pin is dedicated to the Output Compare
2 capability of the timer.
Bit 0 = EXEDG External Clock Edge.
This bit determines which type of level transition
on the external clock pin EXTCLK will trigger the
free running counter.
0: A falling edge triggers the free running counter.
1: A rising edge triggers the free running counter.
Bit 5 = OPM One Pulse Mode.
0: One Pulse Mode is not active.
1: One Pulse Mode is active, the ICAP1 pin can be
used to trigger one pulse on the OCMP1 pin; the
active transition is given by the IEDG1 bit. The
length of the generated pulse depends on the
contents of the OC1R register.
Bit 4 = PWM Pulse Width Modulation.
0: PWM mode is not active.
1: PWM mode is active, the OCMP1 pin outputs a
programmable cyclic signal; the length of the
pulse depends on the value of OC1R register;
the period depends on the value of OC2R regis-
ter.
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ST72121
16-BIT TIMER (Cont’d)
STATUS REGISTER (SR)
Read Only
Bit 2-0 = Reserved, forced by hardware to 0.
INPUT CAPTURE 1 HIGH REGISTER (IC1HR)
Reset Value: 0000 0000 (00h)
The three least significant bits are not used.
7
Read Only
Reset Value: Undefined
This is an 8-bit read only register that contains the
high part of the counter value (transferred by the
input capture 1 event).
0
0
ICF1 OCF1 TOF ICF2 OCF2
0
0
7
0
Bit 7 = ICF1 Input Capture Flag 1.
0: No input capture (reset value).
MSB
LSB
1: An input capture has occurred or the counter
has reached the OC2R value in PWM mode. To
clear this bit, first read the SR register, then read
or write the low byte of the IC1R (IC1LR) regis-
ter.
INPUT CAPTURE 1 LOW REGISTER (IC1LR)
Read Only
Reset Value: Undefined
Bit 6 = OCF1 Output Compare Flag 1.
0: No match (reset value).
1: The content of the free running counter has
matched the content of the OC1R register. To
clear this bit, first read the SR register, then read
or write the low byte of the OC1R (OC1LR) reg-
ister.
This is an 8-bit read only register that contains the
low part of the counter value (transferred by the in-
put capture 1 event).
7
0
MSB
LSB
Bit 5 = TOF Timer Overflow.
OUTPUT COMPARE
(OC1HR)
1
HIGH REGISTER
0: No timer overflow (reset value).
1: The free running counter rolled over from FFFFh
to 0000h. To clear this bit, first read the SR reg-
ister, then read or write the low byte of the CR
(CLR) register.
Read/Write
Reset Value: 1000 0000 (80h)
This is an 8-bit register that contains the high part
of the value to be compared to the CHR register.
Note: Reading or writing the ACLR register does
not clear TOF.
7
0
Bit 4 = ICF2 Input Capture Flag 2.
MSB
LSB
0: No input capture (reset value).
1: An input capture has occurred.To clear this bit,
first read the SR register, then read or write the
low byte of the IC2R (IC2LR) register.
OUTPUT COMPARE
(OC1LR)
1
LOW REGISTER
Bit 3 = OCF2 Output Compare Flag 2.
0: No match (reset value).
Read/Write
Reset Value: 0000 0000 (00h)
1: The content of the free running counter has
matched the content of the OC2R register. To
clear this bit, first read the SR register, then read
or write the low byte of the OC2R (OC2LR) reg-
ister.
This is an 8-bit register that contains the low part of
the value to be compared to the CLR register.
7
0
MSB
LSB
43/87
43
ST72121
16-BIT TIMER (Cont’d)
OUTPUT COMPARE
(OC2HR)
2
HIGH REGISTER
ALTERNATE COUNTER HIGH REGISTER
(ACHR)
Read/Write
Reset Value: 1000 0000 (80h)
Read Only
Reset Value: 1111 1111 (FFh)
This is an 8-bit register that contains the high part
of the value to be compared to the CHR register.
This is an 8-bit register that contains the high part
of the counter value.
7
0
7
0
MSB
LSB
MSB
LSB
OUTPUT COMPARE
(OC2LR)
2
LOW REGISTER
ALTERNATE COUNTER LOW REGISTER
(ACLR)
Read/Write
Reset Value: 0000 0000 (00h)
Read Only
Reset Value: 1111 1100 (FCh)
This is an 8-bit register that contains the low part of
the value to be compared to the CLR register.
This is an 8-bit register that contains the low part of
the counter value. A write to this register resets the
counter. An access to this register after an access
to SR register does not clear the TOF bit in SR
register.
7
0
MSB
LSB
7
0
COUNTER HIGH REGISTER (CHR)
MSB
LSB
Read Only
Reset Value: 1111 1111 (FFh)
INPUT CAPTURE 2 HIGH REGISTER (IC2HR)
This is an 8-bit register that contains the high part
of the counter value.
Read Only
Reset Value: Undefined
7
0
This is an 8-bit read only register that contains the
high part of the counter value (transferred by the
Input Capture 2 event).
MSB
LSB
7
0
MSB
LSB
COUNTER LOW REGISTER (CLR)
Read Only
Reset Value: 1111 1100 (FCh)
This is an 8-bit register that contains the low part of
the counter value. A write to this register resets the
counter. An access to this register after accessing
the SR register clears the TOF bit.
INPUT CAPTURE 2 LOW REGISTER (IC2LR)
Read Only
Reset Value: Undefined
This is an 8-bit read only register that contains the
low part of the counter value (transferred by the In-
put Capture 2 event).
7
0
MSB
LSB
7
0
MSB
LSB
44/87
44
ST72121
16-BIT TIMER (Cont’d)
Table 15. 16-Bit Timer Register Map and Reset Values
Address
(Hex.)
Register
Name
7
6
5
4
3
2
1
0
TimerA: 32 CR1
ICIE
0
OCIE
0
TOIE
0
FOLV2
0
FOLV1
0
OLVL2
0
IEDG1
0
OLVL1
0
TimerB: 42 Reset Value
TimerA: 31 CR2
OC1E
0
OC2E
0
OPM
0
PWM
0
CC1
0
CC0
0
IEDG2
0
EXEDG
0
TimerB: 41 Reset Value
TimerA: 33 SR
ICF1
0
OCF1
0
TOF
0
ICF2
0
OCF2
0
-
-
-
TimerB: 43 Reset Value
0
0
0
TimerA: 34 IC1HR
MSB
-
LSB
-
-
-
-
-
-
-
-
-
-
-
-
-
TimerB: 44 Reset Value
TimerA: 35 IC1LR
MSB
-
LSB
-
TimerB: 45 Reset Value
TimerA: 36 OC1HR
MSB
1
-
0
-
0
-
0
-
0
-
0
-
0
LSB
0
TimerB: 46 Reset Value
TimerA: 37 OC1LR
MSB
0
-
0
-
0
-
0
-
0
-
0
-
0
LSB
0
TimerB: 47 Reset Value
TimerA: 3E OC2HR
MSB
1
-
0
-
0
-
0
-
0
-
0
-
0
LSB
0
TimerB: 4E Reset Value
TimerA: 3F OC2LR
MSB
0
-
0
-
0
-
0
-
0
-
0
-
0
LSB
0
TimerB: 4F Reset Value
TimerA: 38 CHR
MSB
1
LSB
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
TimerB: 48 Reset Value
TimerA: 39 CLR
MSB
1
LSB
0
TimerB: 49 Reset Value
TimerA: 3A ACHR
MSB
1
LSB
1
TimerB: 4A Reset Value
TimerA: 3B ACLR
MSB
1
LSB
0
1
-
1
-
1
-
1
-
1
-
0
-
TimerB: 4B Reset Value
TimerA: 3C IC2HR
MSB
-
LSB
-
TimerB: 4C Reset Value
TimerA: 3D IC2LR
MSB
-
LSB
-
-
-
-
-
-
-
TimerB: 4D Reset Value
45/87
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ST72121
4.4 SERIAL COMMUNICATIONS INTERFACE (SCI)
4.4.1 Introduction
4.4.3 General Description
The Serial Communications Interface (SCI) offers
a flexible means of full-duplex data exchange with
external equipment requiring an industry standard
NRZ asynchronous serial data format. The SCI of-
fers a very wide range of baud rates using two
baud rate generator systems.
The interface is externally connected to another
device by two pins (see Figure 32):
– TDO: Transmit Data Output. When the transmit-
ter is disabled, the output pin returns to its I/O
port configuration. When the transmitter is ena-
bled and nothing is to be transmitted, the TDO
pin is at high level.
4.4.2 Main Features
Full duplex, asynchronous communications
NRZ standard format (Mark/Space)
Dual baud rate generator systems
Independently programmable transmit and
receive baud rates up to 250K baud.
Programmable data word length (8 or 9 bits)
Receive buffer full, Transmit buffer empty and
End of Transmission flags
– RDI: Receive Data Input is the serial data input.
Oversampling techniques are used for data re-
covery by discriminating between valid incoming
data and noise.
Through this pins, serial data is transmitted and re-
ceived as frames comprising:
– An Idle Line prior to transmission or reception
– A start bit
– A data word (8 or 9 bits) least significant bit first
– A Stop bit indicating that the frame is complete.
Thisinterfaceusestwotypesofbaudrategenerator:
Two receiver wake-up modes:
– Address bit (MSB)
– Idle line
Muting function for multiprocessor configurations
Separate enable bits for Transmitter and
Receiver
Three error detection flags:
– Overrun error
– A conventional type for commonly-used baud
rates,
– An extended type with a prescaler offering a very
wide range of baud rates even with non-standard
oscillator frequencies.
– Noise error
– Frame error
Five interrupt sources with flags:
– Transmit data register empty
– Transmission complete
– Receive data register full
– Idle line received
– Overrun error detected
46/87
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ST72121
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
Figure 31. SCI Block Diagram
Write
Read
(DATA REGISTER) DR
Received Data Register (RDR)
Received Shift Register
Transmit Data Register (TDR)
TDO
Transmit Shift Register
RDI
CR1
R8
-
-
T8
M
WAKE
-
-
WAKE
UP
TRANSMIT
RECEIVER
CLOCK
RECEIVER
CONTROL
CONTROL
UNIT
CR2
SR
SBK RWU RE
TDRE TC RDRF
IDLE OR NF FE
TE ILIE RIE TCIE TIE
-
SCI
INTERRUPT
CONTROL
TRANSMITTER
CLOCK
TRANSMITTER RATE
CONTROL
f
CPU
/2
/PR
/16
BRR
SCP1SCP0 SCT2
SCT1 SCT0 SCR2 SCR1SCR0
RECEIVER RATE
CONTROL
CONVENTIONAL BAUD RATE GENERATOR
47/87
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ST72121
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
4.4.4 Functional Description
4.4.4.1 Serial Data Format
The block diagram of the Serial Control Interface,
is shown in Figure 31. It contains 6 dedicated reg-
isters:
Word length may be selected as being either 8 or 9
bits by programming the M bit in the CR1 register
(see Figure 31).
– Two control registers (CR1 & CR2)
– A status register (SR)
The TDO pin is in low state during the start bit.
The TDO pin is in high state during the stop bit.
– A baud rate register (BRR)
An Idle character is interpreted as an entire frame
of “1”s followed by the start bit of the next frame
which contains data.
– An extended prescaler receiver register (ERPR)
– Anextendedprescalertransmitterregister(ETPR)
A Break character is interpreted on receiving “0”s
for some multiple of the frame period. At the end of
the last break frame the transmitter inserts an ex-
tra “1” bit to acknowledge the start bit.
Refer to the register descriptions in Section
4.4.5for the definitions of each bit.
Transmission and reception are driven by their
own baud rate generator.
Figure 32. Word length programming
9-bit Word length (M bit is set)
Possible
Next Data Frame
Parity
Data Frame
Start
Bit
Next
Start
Bit
Stop
Bit
Bit2
Bit6
Bit1
Bit3
Bit4
Bit5
Bit7
Bit8
Bit0
Bit
Start
Bit
Idle Frame
Start
Bit
Extra
’1’
Break Frame
8-bit Word length (M bit is reset)
Possible
Parity
Next Data Frame
Data Frame
Start
Bit
Next
Start
Bit
Stop
Bit
Bit2
Bit5
Bit6
Bit0
Bit1
Bit3
Bit4
Bit7
Bit
Start
Bit
Idle Frame
Start
Bit
Extra
’1’
Break Frame
48/87
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ST72121
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
4.4.4.2 Transmitter
When a frame transmission is complete (after the
stop bit or after the break frame) the TC bit is set
and an interrupt is generated if the TCIE is set and
the I bit is cleared in the CCR register.
The transmitter can send data words of either 8 or
9 bits depending on the M bit status. When the M
bit is set, word length is 9 bits and the 9th bit (the
MSB) has to be stored in the T8 bit in the CR1 reg-
ister.
Clearing the TC bit is performed by the following
software sequence:
1. An access to the SR register
2. A write to the DR register
Character Transmission
During an SCI transmission, data shifts out least
significant bit first on the TDO pin. In this mode,
the DR register consists of a buffer (TDR) between
the internal bus and the transmit shift register (see
Figure 31).
Note: The TDRE and TC bits are cleared by the
same software sequence.
Break Characters
Setting the SBK bit loads the shift register with a
break character. The break frame length depends
on the M bit (see Figure 32).
Procedure
– Select the M bit to define the word length.
As long as the SBK bit is set, the SCI send break
frames to the TDO pin. After clearing this bit by
software the SCI insert a logic 1 bit at the end of
the last break frame to guarantee the recognition
of the start bit of the next frame.
– Select the desired baud rate using the BRR and
the ETPR registers.
– Set the TE bit to assign the TDO pin to the alter-
nate function and to send a idle frame as first
transmission.
Idle Characters
– Access the SR register and write the data to
send in the DR register (this sequence clears the
TDRE bit). Repeat this sequence for each data to
be transmitted.
Setting the TE bit drives the SCI to send an idle
frame before the first data frame.
Clearing and then setting the TE bit during a trans-
mission sends an idle frame after the current word.
Clearing the TDRE bit is always performed by the
following software sequence:
1. An access to the SR register
Note: Resetting and setting the TE bit causes the
data in the TDR register to be lost. Therefore the
best time to toggle the TE bit is when the TDRE bit
is set i.e. before writing the next byte in the DR.
2. A write to the DR register
The TDRE bit is set by hardware and it indicates:
– The TDR register is empty.
– The data transfer is beginning.
– The next data can be written in the DR register
without overwriting the previous data.
This flag generates an interrupt if the TIE bit is set
and the I bit is cleared in the CCR register.
When a transmission is taking place, a write in-
struction to the DR register stores the data in the
TDR register and which is copied in the shift regis-
ter at the end of the current transmission.
When no transmission is taking place, a write in-
struction to the DR register places the data directly
in the shift register, the data transmission starts,
and the TDRE bit is immediately set.
49/87
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ST72121
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
4.4.4.3 Receiver
Overrun Error
The SCI can receive data words of either 8 or 9
bits. When the M bit is set, word length is 9 bits
and the MSB is stored in the R8 bit in the CR1 reg-
ister.
An overrun error occurs when a character is re-
ceived when RDRF has not been reset. Data can
not be transferred from the shift register to the
TDR register as long as the RDRF bit is not
cleared.
Character reception
When a overrun error occurs:
– The OR bit is set.
During a SCI reception, data shifts in least signifi-
cant bit first through the RDI pin. In this mode, DR
register consists in a buffer (RDR) between the in-
ternal bus and the received shift register (see Fig-
ure 31).
– The RDR content will not be lost.
– The shift register will be overwritten.
– An interrupt is generated if the RIE bit is set and
the I bit is cleared in the CCR register.
Procedure
– Select the M bit to define the word length.
The OR bit is reset by an access to the SR register
followed by a DR register read operation.
– Select the desired baud rate using the BRR and
the ERPR registers.
Noise Error
– Set the RE bit, this enables the receiver which
begins searching for a start bit.
Oversampling techniques are used for data recov-
ery by discriminating between valid incoming data
and noise.
When a character is received:
– The RDRF bit is set. It indicates that the content
of the shift register is transferred to the RDR.
When noise is detected in a frame:
– The NF is set at the rising edge of the RDRF bit.
– An interrupt is generated if the RIE bit is set and
the I bit is cleared in the CCR register.
– Data is transferred from the Shift register to the
DR register.
– The error flags can be set if a frame error, noise
or an overrun error has been detected during re-
ception.
– No interrupt is generated. However this bit rises
at the same time as the RDRF bit which itself
generates an interrupt.
Clearing the RDRF bit is performed by the following
software sequence done by:
The NF bit is reset by a SR register read operation
followed by a DR register read operation.
1. An access to the SR register
2. A read to the DR register.
Framing Error
A framing error is detected when:
The RDRF bit must be cleared before the end of the
reception of the next character to avoid an overrun
error.
– The stop bit is not recognized on reception at the
expected time, following either a de-synchroni-
zation or excessive noise.
Break Character
– A break is received.
When a break character is received, the SPI han-
dles it as a framing error.
When the framing error is detected:
– the FE bit is set by hardware
Idle Character
– Data is transferred from the Shift register to the
DR register.
When a idle frame is detected, there is the same
procedure as a data received character plus an in-
terrupt if the ILIE bit is set and the I bit is cleared in
the CCR register.
– No interrupt is generated. However this bit rises
at the same time as the RDRF bit which itself
generates an interrupt.
The FE bit is reset by a SR register read operation
followed by a DR register read operation.
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ST72121
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
Figure 33. SCI Baud Rate and Extended Prescaler Block Diagram
EXTENDED PRESCALER TRANSMITTER RATE CONTROL
ETPR
EXTENDED TRANSMITTER PRESCALER REGISTER
ERPR
EXTENDED RECEIVER PRESCALER REGISTER
EXTENDED PRESCALER RECEIVER RATE CONTROL
EXTENDED PRESCALER
f
TRANSMITTER
CLOCK
CPU
TRANSMITTER RATE
CONTROL
/2
/PR
/16
BRR
SCP1
SCT2
SCT1 SCT0 SCR2 SCR1SCR0
SCP0
RECEIVER
CLOCK
RECEIVER RATE
CONTROL
CONVENTIONAL BAUD RATE GENERATOR
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ST72121
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
4.4.4.4 Conventional Baud Rate Generation
than zero. The baud rates are calculated as fol-
lows:
The baud rate for the receiver and transmitter (Rx
and Tx) are set independently and calculated as
follows:
f
f
CPU
CPU
Rx =
Tx =
f
f
16 ERPR
16 ETPR
CPU
CPU
*
*
Rx =
Tx =
(32 PR) RR
(32 PR) TR
*
*
*
*
with:
with:
ETPR = 1,..,255 (see ETPR register)
PR = 1, 3, 4 or 13 (see SCP0 & SCP1 bits)
TR = 1, 2, 4, 8, 16, 32, 64,128
ERPR = 1,.. 255 (see ERPR register)
4.4.4.6 Receiver Muting and Wake-up Feature
(see SCT0, SCT1 & SCT2 bits)
RR = 1, 2, 4, 8, 16, 32, 64,128
In multiprocessor configurations it is often desira-
ble that only the intended message recipient
should actively receive the full message contents,
thus reducing redundant SCI service overhead for
all non addressed receivers.
(see SCR0,SCR1 & SCR2 bits)
All this bits are in the BRR register.
Example: If f
PR=13 and TR=RR=1, the transmit and receive
baud rates are 19200 baud.
is 8 MHz (normal mode) and if
CPU
The non addressed devices may be placed in
sleep mode by means of the muting function.
Setting the RWU bit by software puts the SCI in
sleep mode:
Note: the baud rate registers MUST NOT be
changed while the transmitter or the receiver is en-
abled.
All the reception status bits can not be set.
All the receive interrupt are inhibited.
4.4.4.5 Extended Baud Rate Generation
A muted receiver may be awakened by one of the
following two ways:
The extended prescaler option gives a very fine
tuning on the baud rate, using a 255 value prescal-
er, whereas the conventional Baud Rate Genera-
tor retains industry standard software compatibili-
ty.
– by Idle Line detection if the WAKE bit is reset,
– by Address Mark detection if the WAKE bit is set.
Receiver wakes-up by Idle Line detection when
the Receive line has recognised an Idle Frame.
Then the RWU bit is reset by hardware but the
IDLE bit is not set.
The extended baud rate generator block diagram
is described in the Figure 33.
The output clock rate sent to the transmitter or to
the receiver will be the output from the 16 divider
divided by a factor ranging from 1 to 255 set in the
ERPR or the ETPR register.
Receiver wakes-up by Address Mark detection
when it received a “1” as the most significant bit of
a word, thus indicating that the message is an ad-
dress. The reception of this particular word wakes
up the receiver, sets the RWU bit and sets the
RDRF bit, which allows the receiver to receive this
word normally and to use it as an address word.
Note: the extended prescaler is activated by set-
ting the ETPR or ERPR register to a value other
52/87
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ST72121
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
4.4.5 Register Description
STATUS REGISTER (SR)
Note: The IDLE bit will not be set again until the
RDRF bit has been set itself (i.e. a new idle line oc-
curs). This bit is not set by an idle line when the re-
ceiver wakes up from wake-up mode.
Read Only
Reset Value: 1100 0000 (C0h)
Bit 3 = OR Overrun error.
7
0
-
This bit is set by hardware when the word currently
being received in the shift register is ready to be
transferred into the RDR register while RDRF=1.
An interrupt is generated if RIE=1 in the CR2 reg-
ister. It is cleared by hardware when RE=0 by a
software sequence (an access to the SR register
followed by a read to the DR register).
0: No Overrun error
TDRE
TC
RDRF IDLE
OR
NF
FE
Bit 7 = TDRE Transmit data register empty.
This bit is set by hardware when the content of the
TDR register has been transferred into the shift
register. An interrupt is generated if the TIE =1 in
the CR2 register. It is cleared by a software se-
quence (an access to the SR register followed by a
write to the DR register).
1: Overrun error is detected
Note: When this bit is set RDR register content will
not be lost but the shift register will be overwritten.
0: Data is not transferred to the shift register
1: Data is transferred to the shift register
Bit 2 = NF Noise flag.
Note: data will not be transferred to the shift regis-
This bit is set by hardware when noise is detected
on a received frame. It is cleared by hardware
when RE=0 by a software sequence (an access to
the SR register followed by a read to the DR regis-
ter).
0: No noise is detected
1: Noise is detected
ter as long as the TDRE bit is not reset.
Bit 6 = TC Transmission complete.
This bit is set by hardware when transmission of a
frame containing Data, a Preamble or a Break is
complete. An interrupt is generated if TCIE=1 in
the CR2 register. It is cleared by a software se-
quence (an access to the SR register followed by a
write to the DR register).
Note: This bit does not generate interrupt as it ap-
pears at the same time as the RDRF bit which it-
self generates an interrupt.
0: Transmission is not complete
1: Transmission is complete
Bit 1 = FE Framing error.
This bit is set by hardware when a de-synchroniza-
tion, excessive noise or a break character is de-
tected. It is cleared by hardware when RE=0 by a
software sequence (an access to the SR register
followed by a read to the DR register).
0: No Framing error is detected
1: Framing error or break character is detected
Bit 5 = RDRF Received data ready flag.
This bit is set by hardware when the content of the
RDR register has been transferred into the DR
register. An interrupt is generated if RIE=1 in the
CR2 register. It is cleared by hardware when
RE=0 or by a software sequence (an access to the
SR register followed by a read to the DR register).
0: Data is not received
Note: This bit does not generate interrupt as it ap-
pears at the same time as the RDRF bit which it-
self generates an interrupt. If the word currently
being transferred causes both frame error and
overrun error, it will be transferred and only the OR
bit will be set.
1: Received data is ready to be read
Bit 4 = IDLE Idle line detect.
This bit is set by hardware when a Idle Line is de-
tected. An interrupt is generated if the ILIE=1 in
the CR2 register. It is cleared by hardware when
RE=0 by a software sequence (an access to the
SR register followed by a read to the DR register).
0: No Idle Line is detected
Bit 0 = Unused.
1: Idle Line is detected
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ST72121
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
CONTROL REGISTER 1 (CR1)
Read/Write
1: An SCI interrupt is generated whenever TC=1 in
the SR register
Reset Value: Undefined
Bit 5 = RIE Receiver interrupt enable.
This bit is set and cleared by software.
0: interrupt is inhibited
1: An SCI interrupt is generated whenever OR=1
or RDRF=1 in the SR register
7
0
-
R8
T8
-
M
WAKE
-
-
Bit 7 = R8 Receive data bit 8.
This bit is used to store the 9th bit of the received
word when M=1.
Bit 4 = ILIE Idle line interrupt enable.
This bit is set and cleared by software.
0: interrupt is inhibited
1: An SCI interrupt is generated whenever IDLE=1
in the SR register.
Bit 6 = T8 Transmit data bit 8.
This bit is used to store the 9th bit of the transmit-
ted word when M=1.
Bit 3 = TE Transmitter enable.
This bit enables the transmitter and assigns the
TDO pin to the alternate function. It is set and
cleared by software.
0: Transmitter is disabled, the TDO pin is back to
the I/O port configuration.
Bit 4 = M Word length.
This bit determines the word length. It is set or
cleared by software.
0: 1 Start bit, 8 Data bits, 1 Stop bit
1: 1 Start bit, 9 Data bits, 1 Stop bit
1: Transmitter is enabled
Note: during transmission, a “0” pulse on the TE
bit (“0” followed by “1”) sends a preamble after the
current word.
Bit 3 = WAKE Wake-Up method.
This bit determines the SCI Wake-Up method, it is
set or cleared by software.
0: Idle Line
Bit 2 = RE Receiver enable.
This bit enables the receiver. It is set and cleared
by software.
1: Address Mark
0: Receiver is disabled, it resets the RDRF, IDLE,
OR, NF and FE bits of the SR register.
1: Receiver is enabled and begins searching for a
start bit.
CONTROL REGISTER 2 (CR2)
Read/Write
Reset Value: 0000 0000 (00h)
7
0
Bit 1 = RWU Receiver wake-up.
This bit determines if the SCI is in mute mode or
not. It is set and cleared by software and can be
cleared by hardware when a wake-up sequence is
recognized.
0: Receiver in active mode
1: Receiver in mute mode
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
Bit 7 = TIE Transmitter interrupt enable.
This bit is set and cleared by software.
0: interrupt is inhibited
1: An SCI interrupt is generated whenever
TDRE=1 in the SR register.
Bit 0 = SBK Send break.
This bit set is used to send break characters. It is
set and cleared by software.
0: No break character is transmitted
1: Break characters are transmitted
Bit 6 = TCIE Transmission complete interrupt ena-
ble
This bit is set and cleared by software.
0: interrupt is inhibited
Note: If the SBK bit is set to “1” and then to “0”, the
transmitter will send a BREAK word at the end of
the current word.
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ST72121
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
DATA REGISTER (DR)
Bit 5:3 = SCT[2:0] SCI Transmitter rate divisor
Read/Write
These 3 bits, in conjunction with the SCP1 & SCP0
bits define the total division applied to the bus
clock to yield the transmit rate clock in convention-
al Baud Rate Generator mode.
Reset Value: Undefined
Contains the Received or Transmitted data char-
acter, depending on whether it is read from or writ-
ten to.
TR dividing factor
SCT2
SCT1
SCT0
1
2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
7
0
4
DR7
DR6
DR5
DR4
DR3
DR2
DR1
DR0
8
The Data register performs a double function (read
and write) since it is composed of two registers,
one for transmission (TDR) and one for reception
(RDR).
The TDR register provides the parallel interface
between the internal bus and the output shift reg-
ister (see Figure 31).
The RDR register provides the parallel interface
between the input shift register and the internal
bus (see Figure 31).
16
32
64
128
Note: this TR factor is used only when the ETPR
fine tuning factor is equal to 00h; otherwise, TR is
replaced by the ETPR dividing factor.
Bit 2:0 = SCR[2:0] SCI Receiver rate divisor.
BAUD RATE REGISTER (BRR)
Read/Write
These 3 bits, in conjunction with the SCP1 & SCP0
bits define the total division applied to the bus
clock to yield the receive rate clock in conventional
Baud Rate Generator mode.
Reset Value: 00xx xxxx (XXh)
7
0
RR dividing factor
SCR2
SCR1
SCR0
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0
1
2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Bit 7:6= SCP[1:0] First SCI Prescaler
These 2 prescaling bits allow several standard
clock division ranges:
4
8
16
32
64
128
PR Prescaling factor
SCP1
SCP0
1
3
0
0
1
1
0
1
0
1
4
13
Note: this RR factor is used only when the ERPR
fine tuning factor is equal to 00h; otherwise, RR is
replaced by the ERPR dividing factor.
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ST72121
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
EXTENDED RECEIVE PRESCALER DIVISION
REGISTER (ERPR)
EXTENDED TRANSMIT PRESCALER DIVISION
REGISTER (ETPR)
Read/Write
Read/Write
Reset Value: 0000 0000 (00h)
Reset Value:0000 0000 (00h)
Allows setting of the Extended Prescaler rate divi-
sion factor for the receive circuit.
Allows setting of the External Prescaler rate divi-
sion factor for the transmit circuit.
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
ERPR ERPR ERPR ERPR ERPR ERPR ERPR ERPR
ETPR ETPR ETPR ETPR ETPR ETPR ETPR ETPR
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Bit 7:1 = ERPR[7:0] 8-bit Extended Receive Pres-
caler Register.
Bit 7:1 = ETPR[7:0] 8-bit Extended Transmit Pres-
caler Register.
The extended Baud Rate Generator is activated
when a value different from 00h is stored in this
register. Therefore the clock frequency issued
from the 16 divider (see Figure 33) is divided by
the binary factor set in the ERPR register (in the
range 1 to 255).
The extended Baud Rate Generator is activated
when a value different from 00h is stored in this
register. Therefore the clock frequency issued
from the 16 divider (see Figure 33) is divided by
the binary factor set in the ETPR register (in the
range 1 to 255).
The extended baud rate generator is not used af-
ter a reset.
The extended baud rate generator is not used af-
ter a reset.
Table 16. SCI Register Map and Reset Values
Address
(Hex.)
50
Register
Name
7
6
5
4
3
2
1
0
SR
TDRE
1
TC
1
RDRF
0
IDLE
0
OR
0
NF
0
FE
0
-
Reset Value
0
51
52
53
54
55
57
DR
DR7
DR6
DR5
DR4
DR3
DR2
DR1
DR0
Reset Value
BRR
-
SCP1
0
-
-
SCT2
x
-
-
-
SCR2
x
-
SCR1
x
-
SCR0
x
SCP0
SCT1
SCT0
Reset Value
CR1
0
T8
-
x
M
-
x
WAKE
-
R8
-
Reset Value
-
-
-
-
CR2
TIE
0
TCIE
0
RIE
0
ILIE
0
TE
0
RE
0
RWU
0
SBK
0
Reset Value
ERPR
ERPR7
0
ERPR6
0
ERPR5
0
ERPR4
0
ERPR3
0
ERPR2
0
ERPR1
0
ERPR0
0
Reset Value
ETPR
ETPR7
0
ETPR6
0
ETPR5
0
ETPR4
0
ETPR3
0
ETPR2
0
ETPR1
0
ETPR0
0
Reset Value
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ST72121
4.5 SERIAL PERIPHERAL INTERFACE (SPI)
4.5.1 Introduction
4.5.3 General description
The Serial Peripheral Interface (SPI) allows full-
duplex, synchronous, serial communication with
external devices. An SPI system may consist of a
master and one or more slaves or a system in
which devices may be either masters or slaves.
The SPI is connected to external devices through
4 alternate pins:
– MISO: Master In Slave Out pin
– MOSI: Master Out Slave In pin
– SCK: Serial Clock pin
The SPI is normally used for communication be-
tween the microcontroller and external peripherals
or another microcontroller.
– SS: Slave select pin
Refer to the Pin Description chapter for the device-
specific pin-out.
A basic example of interconnections between a
single master and a single slave is illustrated on
Figure 34.
4.5.2 Main Features
The MOSI pins are connected together as are
MISO pins. In this way data is transferred serially
between master and slave (most significant bit
first).
Full duplex, three-wire synchronous transfers
Master or slave operation
Four master mode frequencies
Maximum slave mode frequency = fCPU/2.
Four programmable master bit rates
Programmable clock polarity and phase
End of transfer interrupt flag
When the master device transmits data to a slave
device via MOSI pin, the slave device responds by
sending data to the master device via the MISO
pin. This implies full duplex transmission with both
data out and data in synchronized with the same
clock signal (which is provided by the master de-
vice via the SCK pin).
Write collision flag protection
Master mode fault protection capability.
Thus, the byte transmitted is replaced by the byte
received and eliminates the need for separate
transmit-empty and receiver-full bits. A status flag
is used to indicate that the I/O operation is com-
plete.
Four possible data/clock timing relationships may
be chosen (see Figure 37) but master and slave
must be programmed with the same timing mode.
Figure 34. Serial Peripheral Interface Master/Slave
MASTER
SLAVE
MSBit
LSBit
MSBit
LSBit
MISO
MOSI
MISO
MOSI
8-BIT SHIFT REGISTER
8-BIT SHIFT REGISTER
SPI
CLOCK
GENERATOR
SCK
SS
SCK
SS
+5V
VR02131A
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ST72121
SERIAL PERIPHERAL INTERFACE (Cont’d)
Figure 35. Serial Peripheral Interface Block Diagram
Internal Bus
Read
DR
Read Buffer
IT
request
MOSI
SR
MISO
8-Bit Shift Register
Write
MODF
WCOL
SPIF
-
-
-
-
-
SPI
STATE
CONTROL
SCK
SS
CR
MSTR
SPR0
CPOL CPHA SPR1
SPIE SPE SPR2
MASTER
CONTROL
SERIAL
CLOCK
GENERATOR
VR02131B
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ST72121
SERIAL PERIPHERAL INTERFACE (Cont’d)
4.5.4 Functional Description
Figure 34 shows the serial peripheral interface
(SPI) block diagram.
In this configuration the MOSI pin is a data output
and to the MISO pin is a data input.
This interface contains 3 dedicated registers:
– A Control Register (CR)
Transmit sequence
– A Status Register (SR)
The transmit sequence begins when a byte is writ-
ten in the DR register.
– A Data Register (DR)
The data byte is parallel loaded into the 8-bit shift
register (from the internal bus) during a write cycle
and then shifted out serially to the MOSI pin most
significant bit first.
Refer to the CR, SR and DR registers in Section
4.5.5for the bit definitions.
4.5.4.1 Master Configuration
In a master configuration, the serial clock is gener-
ated on the SCK pin.
When data transfer is complete:
– The SPIF bit is set by hardware
Procedure
– An interrupt is generated if the SPIE bit is set
and the I bit in the CCR register is cleared.
– Select the SPR0 & SPR1 bits to define the se-
rial clock baud rate (see CR register).
During the last clock cycle the SPIF bit is set, a
copy of the data byte received in the shift register
is moved to a buffer. When the DR register is read,
the SPI peripheral returns this buffered value.
– Select the CPOL and CPHA bits to define one
of the four relationships between the data
transfer and the serial clock (see Figure 37).
– The SS pin must be connected to a high level
signal during the complete byte transmit se-
quence.
Clearing the SPIF bit is performed by the following
software sequence:
1. An access to the SR register while the SPIF bit
is set
– The MSTR and SPE bits must be set (they re-
main set only if the SS pin is connected to a
high level signal).
2. A write or a read of the DR register.
Note: While the SPIF bit is set, all writes to the DR
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ST72121
SERIAL PERIPHERAL INTERFACE (Cont’d)
4.5.4.2 Slave Configuration
When data transfer is complete:
– The SPIF bit is set by hardware
In slave configuration, the serial clock is received
on the SCK pin from the master device.
– An interrupt is generated if SPIE bit is set and
I bit in CCR register is cleared.
The value of the SPR0 & SPR1 bits is not used for
the data transfer.
During the last clock cycle the SPIF bit is set, a
copy of the data byte received in the shift register
is moved to a buffer. When the DR register is read,
the SPI peripheral returns this buffered value.
Procedure
– For correct data transfer, the slave device
must be in the same timing mode as the mas-
ter device (CPOL and CPHA bits). See Figure
37.
Clearing the SPIF bit is performed by the following
software sequence:
1. An access to the SR register while the SPIF bit
is set.
– The SS pin must be connected to a low level
signal during the complete byte transmit se-
quence.
2. A write or a read of the DR register.
– Clear the MSTR bit and set the SPE bit to as-
sign the pins to alternate function.
Notes: While the SPIF bit is set, all writes to the
DR register are inhibited until the SR register is
read.
In this configuration the MOSI pin is a data input
and the MISO pin is a data output.
The SPIF bit can be cleared during a second
transmission; however, it must be cleared before
the second SPIF bit in order to prevent an overrun
condition (see Section 4.5.4.6).
Transmit Sequence
The data byte is parallel loaded into the 8-bit shift
register (from the internal bus) during a write cycle
and then shifted out serially to the MISO pin most
significant bit first.
Depending on the CPHA bit, the SS pin has to be
set to write to the DR register between each data
byte transfer to avoid a write collision (see Section
4.5.4.4).
The transmit sequence begins when the slave de-
vice receives the clock signal and the most signifi-
cant bit of the data on its MOSI pin.
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ST72121
SERIAL PERIPHERAL INTERFACE (Cont’d)
4.5.4.3 Data Transfer Format
The master device applies data to its MOSI pin-
clock edge before the capture clock edge.
During an SPI transfer, data is simultaneously
transmitted (shifted out serially) and received
(shifted in serially). The serial clock is used to syn-
chronize the data transfer during a sequence of
eight clock pulses.
CPHA bit is set
The second edge on the SCK pin (falling edge if
the CPOL bit is reset, rising edge if the CPOL bit is
set) is the MSBit capture strobe. Data is latched on
the occurrence of the first clock transition.
The SS pin allows individual selection of a slave
device; the other slave devices that are not select-
ed do not interfere with the SPI transfer.
No write collision should occur even if the SS pin
stays low during a transfer of several bytes (see
Figure 36).
Clock Phase and Clock Polarity
Four possible timing relationships may be chosen
by software, using the CPOL and CPHA bits.
CPHA bit is reset
The CPOL (clock polarity) bit controls the steady
state value of the clock when no data is being
transferred. This bit affects both master and slave
modes.
The first edge on the SCK pin (falling edge if CPOL
bit is set, rising edge if CPOL bit is reset) is the
MSBit capture strobe. Data is latched on the oc-
currence of the second clock transition.
The combination between the CPOL and CPHA
(clock phase) bits selects the data capture clock
edge.
This pin must be toggled high and low between
each byte transmitted (see Figure 36).
To protect the transmission from a write collision a
low value on the SS pin of a slave device freezes
the data in its DR register and does not allow it to
be altered. Therefore the SS pin must be high to
write a new data byte in the DR without producing
a write collision.
Figure 37, shows an SPI transfer with the four
combinations of the CPHA and CPOL bits. The di-
agram may be interpreted as a master or slave
timing diagram where the SCK pin, the MISO pin,
the MOSI pin are directly connected between the
master and the slave device.
The SS pin is the slave device select input and can
be driven by the master device.
Figure 36. CPHA / SS Timing Diagram
Byte 3
Byte 2
MOSI/MISO
Master SS
Byte 1
Slave SS
(CPHA=0)
Slave SS
(CPHA=1)
VR02131C
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ST72121
SERIAL PERIPHERAL INTERFACE (Cont’d)
Figure 37. Data Clock Timing Diagram
CPHA =1
CPOL = 1
CPOL = 0
Bit 4
Bit 4
Bit3
Bit 2
Bit 2
Bit 1
Bit 1
LSBit
LSBit
MSBit
MSBit
Bit 6
Bit 6
Bit 5
Bit 5
MISO
(from master)
Bit3
MOSI
(from slave)
SS
(to slave)
CAPTURE STROBE
CPHA =0
CPOL = 1
CPOL = 0
Bit 4
Bit 4
Bit3
Bit 2
Bit 2
Bit 1
Bit 1
LSBit
LSBit
MISO
(from master)
MSBit
Bit 6
Bit 6
Bit 5
Bit 5
Bit3
MOSI
(from slave)
MSBit
SS
(to slave)
CAPTURE STROBE
Note: This figure should not be used as a replacement for parametric information.
Refer to the Electrical Characteristics chapter.
VR02131D
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ST72121
SERIAL PERIPHERAL INTERFACE (Cont’d)
4.5.4.4 Write Collision Error
When the CPHA bit is reset:
A write collision occurs when the software tries to
write to the DR register while a data transfer is tak-
ing place with an external device. When this hap-
pens, the transfer continues uninterrupted; and
the software write will be unsuccessful.
Data is latched on the occurrence of the first clock
transition. The slave device does not have any
way of knowing when that transition will occur;
therefore, the slave device collision occurs when
software attempts to write the DR register after its
SS pin has been pulled low.
Write collisions can occur both in master and slave
mode.
For this reason, the SS pin must be high, between
each data byte transfer, to allow the CPU to write
in the DR register without generating a write colli-
sion.
Note: a "read collision" will never occur since the
received data byte is placed in a buffer in which
access is always synchronous with the MCU oper-
ation.
In Slave mode
In Master mode
When the CPHA bit is set:
Collision in the master device is defined as a write
of the DR register while the internal serial clock
(SCK) is in the process of transfer.
The slave device will receive a clock (SCK) edge
prior to the latch of the first data transfer. This first
clock edge will freeze the data in the slave device
DR register and output the MSBit on to the exter-
nal MISO pin of the slave device.
The SS pin signal must be always high on the
master device.
The SS pin low state enables the slave device but
the output of the MSBit onto the MISO pin does
not take place until the first data transfer clock
edge.
WCOL bit
The WCOL bit in the SR register is set if a write
collision occurs.
No SPI interrupt is generated when the WCOL bit
is set (the WCOL bit is a status flag only).
Clearing the WCOL bit is done through a software
sequence (see Figure 38).
Figure 38. Clearing the WCOL bit (Write Collision Flag) Software Sequence
Clearing sequence after SPIF = 1 (end of a data byte transfer)
Read SR
Read SR
1st Step
2nd Step
OR
THEN
THEN
SPIF =0
WCOL=0
SPIF =0
WCOL=0 if no transfer has started
WCOL=1 if a transfer has started
before the 2nd step
Read DR
Write DR
Clearing sequence before SPIF = 1 (during a data byte transfer)
Read SR
1st Step
THEN
Note: Writing in DR register in-
2nd Step
Read DR
stead of reading in it do not reset
WCOL bit
WCOL=0
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ST72121
SERIAL PERIPHERAL INTERFACE (Cont’d)
4.5.4.5 Master Mode Fault
may be restored to their original state during or af-
ter this clearing sequence.
Master mode fault occurs when the master device
has its SS pin pulled low, then the MODF bit is set.
Hardware does not allow the user to set the SPE
and MSTR bits while the MODF bit is set except in
the MODF bit clearing sequence.
Master mode fault affects the SPI peripheral in the
following ways:
In a slave device the MODF bit can not be set, but
in a multi master configuration the device can be in
slave mode with this MODF bit set.
– The MODF bit is set and an SPI interrupt is
generated if the SPIE bit is set.
– The SPE bit is reset. This blocks all output
from the device and disables the SPI periph-
eral.
The MODF bit indicates that there might have
been a multi-master conflict for system control and
allows a proper exit from system operation to a re-
set or default system state using an interrupt rou-
tine.
– The MSTR bit is reset, thus forcing the device
into slave mode.
Clearing the MODF bit is done through a software
sequence:
4.5.4.6 Overrun Condition
An overrun condition occurs, when the master de-
vice has sent several data bytes and the slave de-
vice has not cleared the SPIF bit issuing from the
previous data byte transmitted.
1. A read or write access to the SR register while
the MODF bit is set.
2. A write to the CR register.
In this case, the receiver buffer contains the byte
sent after the SPIF bit was last cleared. A read to
the DR register returns this byte. All other bytes
are lost.
Notes: To avoid any multiple slave conflicts in the
case of a system comprising several MCUs, the
SS pin must be pulled high during the clearing se-
quence of the MODF bit. The SPE and MSTR bits
This condition is not detected by the SPI peripher-
al.
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ST72121
SERIAL PERIPHERAL INTERFACE (Cont’d)
4.5.4.7 Single Master and Multimaster Configurations
There are two types of SPI systems:
– Single Master System
For more security, the slave device may respond
to the master with the received data byte. Then the
master will receive the previous byte back from the
slave device if all MISO and MOSI pins are con-
nected and the slave has not written its DR regis-
ter.
– Multimaster System
Single Master System
Other transmission security methods can use
ports for handshake lines or data bytes with com-
mand fields.
A typical single master system may be configured,
using an MCU as the master and four MCUs as
slaves (see Figure 39).
Multi-master System
The master device selects the individual slave de-
vices by using four pins of a parallel port to control
the four SS pins of the slave devices.
A multi-master system may also be configured by
the user. Transfer of master control could be im-
plemented using a handshake method through the
I/O ports or by an exchange of code messages
through the serial peripheral interface system.
The SS pins are pulled high during reset since the
master device ports will be forced to be inputs at
that time, thus disabling the slave devices.
The multi-master system is principally handled by
the MSTR bit in the CR register and the MODF bit
in the SR register.
Note: To prevent a bus conflict on the MISO line
the master allows only one slave device during a
transmission.
Figure 39. Single Master Configuration
SS
SS
SS
SS
SCK
SCK
Slave
SCK
Slave
SCK
Slave
MCU
Slave
MCU
MCU
MCU
MOSI MISO
MOSI MISO
MOSI MISO
MOSI MISO
MOSI MISO
SCK
Master
MCU
5V
SS
VR02131E
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ST72121
SERIAL PERIPHERAL INTERFACE (Cont’d)
4.5.5 Register Description
CONTROL REGISTER (CR)
Read/Write
Bit 3 = CPOL Clock polarity.
This bit is set and cleared by software. This bit de-
termines the steady state of the serial Clock. The
CPOL bit affects both the master and slave
modes.
Reset Value: 0000xxxx (0xh)
7
0
SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0
0: The steady state is a low value at the SCK pin.
1: The steady state is a high value at the SCK pin.
Bit 2 = CPHA Clock phase.
This bit is set and cleared by software.
0: The first clock transition is the first data capture
edge.
1: The second clock transition is the first capture
edge.
Bit 7 = SPIE Serial peripheral interrupt enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SPI interrupt is generated whenever SPIF=1
or MODF=1 in the SR register
Bit 6 = SPE Serial peripheral output enable.
This bit is set and cleared by software. It is also
cleared by hardware when, in master mode, SS=0
(see Section 4.5.4.5 Master Mode Fault).
0: I/O port connected to pins
Bit 1,0 = SPR1-SPR0 Serial peripheral rate.
These bits are set and cleared by software. Used
with the SPR2 bit, they select one of six baud rates
to be used as the serial clock when the device is a
master.
1: SPI alternate functions connected to pins
These 2 bits have no effect in slave mode.
The SPE bit is cleared by reset, so the SPI periph-
eral is not initially connected to the external pins.
Table 17. Serial Peripheral Baud Rate
Serial Clock
SPR2 SPR1 SPR0
Bit 5 = SPR2 Divider Enable.
This bit is set and cleared by software and it is
cleared by reset. It is used with the SPR[1:0] bits to
set the baud rate. Refer to Table 17.
0: Divider by 2 enabled
f
f
/4
/8
1
0
0
1
0
0
0
0
0
1
1
1
0
0
1
0
0
1
CPU
CPU
f
f
f
/16
/32
/64
CPU
CPU
CPU
1: Divider by 2 disabled
Bit 4 = MSTR Master.
f
/128
CPU
This bit is set and cleared by software. It is also
cleared by hardware when, in master mode, SS=0
(see Section 4.5.4.5 Master Mode Fault).
0: Slave mode is selected
1: Master mode is selected, the function of the
SCK pin changes from an input to an output and
the functions of the MISO and MOSI pins are re-
versed.
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ST72121
SERIAL PERIPHERAL INTERFACE (Cont’d)
STATUS REGISTER (SR)
Read Only
erated if SPIE=1 in the CR register. This bit is
cleared by a software sequence (An access to the
SR register while MODF=1 followed by a write to
the CR register).
Reset Value: 0000 0000 (00h)
0: No master mode fault detected
1: A fault in master mode has been detected
7
0
-
SPIF
WCOL
-
MODF
-
-
-
Bits 3-0 = Unused.
Bit 7 = SPIF Serial Peripheral data transfer flag.
This bit is set by hardware when a transfer has
been completed. An interrupt is generated if
SPIE=1 in the CR register. It is cleared by a soft-
ware sequence (an access to the SR register fol-
lowed by a read or write to the DR register).
0: Data transfer is in progress or has been ap-
proved by a clearing sequence.
DATA I/O REGISTER (DR)
Read/Write
Reset Value: Undefined
1: Data transfer between the device and an exter-
nal device has been completed.
7
0
Note: While the SPIF bit is set, all writes to the DR
register are inhibited.
D7
D6
D5
D4
D3
D2
D1
D0
The DR register is used to transmit and receive
data on the serial bus. In the master device only a
write to this register will initiate transmission/re-
ception of another byte.
Bit 6 = WCOL Write Collision status.
This bit is set by hardware when a write to the DR
register is done during a transmit sequence. It is
cleared by a software sequence (see Figure 38).
0: No write collision occurred
Notes: During the last clock cycle the SPIF bit is
set, a copy of the received data byte in the shift
register is moved to a buffer. When the user reads
the serial peripheral data I/O register, the buffer is
actually being read.
1: A write collision has been detected
Bit 5 = Unused.
Warning: A write to the DR register places data di-
rectly into the shift register for transmission.
Bit 4 = MODF Mode Fault flag.
A read to the DR register returns the value located
in the buffer and not the contents of the shift regis-
ter (see Figure 35).
This bit is set by hardware when the SS pin is
pulled low in master mode (see Section 4.5.4.5
Master Mode Fault). An SPI interrupt can be gen-
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ST72121
SERIAL PERIPHERAL INTERFACE (Cont’d)
Table 18. SPI Register Map and Reset Values
Address
(Hex.)
Register
Name
7
6
5
4
3
2
1
0
DR
Reset Value
CR
Reset Value
SR
Reset Value
D7
x
D6
D5
x
D4
D3
x
D2
x
D1
x
D0
x
21
22
23
x
SPE
0
x
MSTR
0
SPIE
0
SPR2
0
-
CPOL
x
-
CPHA
x
-
SPR1
x
-
SPR0
x
-
SPIF
0
WCOL
0
MODF
0
0
0
0
0
0
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ST72121
5 INSTRUCTION SET
5.1 ST7 ADDRESSING MODES
so, most of the addressing modes may be subdi-
vided in two sub-modes called long and short:
The ST7 Core features 17 different addressing
modes which can be classified in 7 main groups:
– Long addressing mode is more powerful be-
cause it can use the full 64 Kbyte address space,
however it uses more bytes and more CPU cy-
cles.
Addressing Mode
Inherent
Example
nop
– Short addressing mode is less powerful because
it can generally only access page zero (0000h -
00FFh range), but the instruction size is more
compact, and faster. All memory to memory in-
structions use short addressing modes only
(CLR, CPL, NEG, BSET, BRES, BTJT, BTJF,
INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP)
Immediate
Direct
ld A,#$55
ld A,$55
ld A,($55,X)
ld A,([$55],X)
jrne loop
Indexed
Indirect
Relative
Bit operation
bset byte,#5
The ST7 Assembler optimizes the use of long and
short addressing modes.
The ST7 Instruction set is designed to minimize
the number of bytes required per instruction: To do
Table 19. ST7 Addressing Mode Overview
Pointer
Address
(Hex.)
Pointer
Size
(Hex.)
Destination/
Source
Length
(Bytes)
Mode
Syntax
Inherent
Immediate
Short
nop
+ 0
+ 1
+ 1
+ 2
ld A,#$55
ld A,$10
Direct
Direct
00..FF
Long
ld A,$1000
0000..FFFF
+ 0 (with X register)
+ 1 (with Y register)
No Offset
Direct
Indexed
ld A,(X)
00..FF
Short
Long
Short
Long
Short
Long
Relative
Relative
Bit
Direct
Indexed
Indexed
ld A,($10,X)
ld A,($1000,X)
ld A,[$10]
00..1FE
+ 1
+ 2
+ 2
+ 2
+ 2
+ 2
+ 1
+ 2
+ 1
+ 2
+ 2
+ 3
Direct
0000..FFFF
00..FF
Indirect
Indirect
Indirect
Indirect
Direct
00..FF
00..FF
00..FF
00..FF
byte
word
byte
word
ld A,[$10.w]
ld A,([$10],X)
0000..FFFF
00..1FE
Indexed
Indexed
ld A,([$10.w],X) 0000..FFFF
jrne loop
PC-128/PC+1271)
PC-128/PC+1271) 00..FF
Indirect
Direct
jrne [$10]
byte
byte
byte
bset $10,#7
bset [$10],#7
00..FF
00..FF
Bit
Indirect
Direct
00..FF
00..FF
Bit
Relative btjt $10,#7,skip 00..FF
Relative btjt [$10],#7,skip 00..FF
Bit
Indirect
Note 1. At the time the instruction is executed, the Program Counter (PC) points to the instruction follow-
ing JRxx.
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ST72121
ST7 ADDRESSING MODES (Cont’d)
5.1.1 Inherent
5.1.3 Direct
All Inherent instructions consist of a single byte.
The opcode fully specifies all the required informa-
tion for the CPU to process the operation.
In Direct instructions, the operands are referenced
by their memory address.
The direct addressing mode consists of two sub-
modes:
Inherent Instruction
Function
No operation
Direct (short)
NOP
The address is a byte, thus requires only one byte
after the opcode, but only allows 00 - FF address-
ing space.
TRAP
S/W Interrupt
Wait For Interrupt (Low Power
Mode)
WFI
Direct (long)
Halt Oscillator (Lowest Power
Mode)
HALT
The address is a word, thus allowing 64 Kbyte ad-
dressing space, but requires 2 bytes after the op-
code.
RET
Sub-routine Return
Interrupt Sub-routine Return
Set Interrupt Mask
Reset Interrupt Mask
Set Carry Flag
IRET
SIM
5.1.4 Indexed (No Offset, Short, Long)
RIM
In this mode, the operand is referenced by its
memory address, which is defined by the unsigned
addition of an index register (X or Y) with an offset.
SCF
RCF
Reset Carry Flag
Reset Stack Pointer
Load
The indirect addressing mode consists of three
sub-modes:
RSP
LD
Indexed (No Offset)
CLR
Clear
There is no offset, (no extra byte after the opcode),
and allows 00 - FF addressing space.
PUSH/POP
INC/DEC
TNZ
Push/Pop to/from the stack
Increment/Decrement
Test Negative or Zero
1 or 2 Complement
Byte Multiplication
Indexed (Short)
The offset is a byte, thus requires only one byte af-
ter the opcode and allows 00 - 1FE addressing
space.
CPL, NEG
MUL
Indexed (long)
SLL, SRL, SRA, RLC,
RRC
Shift and Rotate Operations
Swap Nibbles
The offset is a word, thus allowing 64 Kbyte ad-
dressing space and requires 2 bytes after the op-
code.
SWAP
5.1.2 Immediate
Immediate instructions have two bytes, the first
byte contains the opcode, the second byte con-
tains the the operand value. .
5.1.5 Indirect (Short, Long)
The required data byte to do the operation is found
by its memory address, located in memory (point-
er).
Immediate Instruction
Function
The pointer address follows the opcode. The indi-
rect addressing mode consists of two sub-modes:
LD
Load
CP
Compare
Indirect (short)
BCP
Bit Compare
The pointer address is a byte, the pointer size is a
byte, thus allowing 00 - FF addressing space, and
requires 1 byte after the opcode.
AND, OR, XOR
ADC, ADD, SUB, SBC
Logical Operations
Arithmetic Operations
Indirect (long)
The pointer address is a byte, the pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.
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ST72121
ST7 ADDRESSING MODES (Cont’d)
5.1.6 Indirect Indexed (Short, Long)
5.1.7 Relative mode (Direct, Indirect)
This is a combination of indirect and short indexed
addressing modes. The operand is referenced by
its memory address, which is defined by the un-
signed addition of an index register value (X or Y)
with a pointer value located in memory. The point-
er address follows the opcode.
This addressing mode is used to modify the PC
register value, by adding an 8-bit signed offset to
it.
Available Relative Direct/
Function
Indirect Instructions
JRxx
Conditional Jump
Call Relative
The indirect indexed addressing mode consists of
two sub-modes:
CALLR
Indirect Indexed (Short)
The pointer address is a byte, the pointer size is a
byte, thus allowing 00 - 1FE addressing space,
and requires 1 byte after the opcode.
The relative addressing mode consists of two sub-
modes:
Relative (Direct)
The offset is following the opcode.
Relative (Indirect)
Indirect Indexed (Long)
The pointer address is a byte, the pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.
The offset is defined in memory, which address
follows the opcode.
Table 20. Instructions Supporting Direct,
Indexed, Indirect and Indirect Indexed
Addressing Modes
Long and Short
Function
Instructions
LD
Load
CP
Compare
AND, OR, XOR
Logical Operations
Arithmetic Addition/subtrac-
tion operations
ADC, ADD, SUB, SBC
BCP
Bit Compare
Short Instructions Only
CLR
Function
Clear
INC, DEC
Increment/Decrement
Test Negative or Zero
1 or 2 Complement
Bit Operations
TNZ
CPL, NEG
BSET, BRES
Bit Test and Jump Opera-
tions
BTJT, BTJF
SLL, SRL, SRA, RLC,
RRC
Shift and Rotate Operations
SWAP
Swap Nibbles
CALL, JP
Call or Jump subroutine
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ST72121
5.2 INSTRUCTION GROUPS
The ST7 family devices use an Instruction Set
consisting of 63 instructions. The instructions may
be subdivided into 13 main groups as illustrated in
the following table:
Load and Transfer
LD
CLR
POP
DEC
TNZ
OR
Stack operation
PUSH
INC
RSP
BCP
Increment/Decrement
Compare and Tests
Logical operations
CP
AND
BSET
BTJT
ADC
SLL
XOR
CPL
NEG
Bit Operation
BRES
BTJF
ADD
SRL
JRT
Conditional Bit Test and Branch
Arithmetic operations
Shift and Rotates
SUB
SRA
JRF
SBC
RLC
JP
MUL
RRC
CALL
SWAP
CALLR
SLA
Unconditional Jump or Call
Conditional Branch
JRA
JRxx
TRAP
SIM
NOP
RET
Interruption management
Code Condition Flag modification
WFI
RIM
HALT
SCF
IRET
RCF
Using a pre-byte
The instructions are described with one to four
bytes.
These prebytes enable instruction in Y as well as
indirect addressing modes to be implemented.
They precede the opcode of the instruction in X or
the instruction using direct addressing mode. The
prebytes are:
In order to extend the number of available op-
codes for an 8-bit CPU (256 opcodes), three differ-
ent prebyte opcodes are defined. These prebytes
modify the meaning of the instruction they pre-
cede.
PDY 90
Replace an X based instruction
using immediate, direct, indexed, or inherent ad-
dressing mode by a Y one.
The whole instruction becomes:
PIX 92
Replace an instruction using di-
PC-2
PC-1
PC
End of previous instruction
Prebyte
rect, direct bit, or direct relative addressing mode
to an instruction using the corresponding indirect
addressing mode.
opcode
It also changes an instruction using X indexed ad-
dressing mode to an instruction using indirect X in-
dexed addressing mode.
PC+1
Additional word (0 to 2) according
to the number of bytes required to compute the ef-
fective address
PIY 91
Replace an instruction using X in-
direct indexed addressing mode by a Y one.
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ST72121
INSTRUCTION GROUPS (Cont’d)
Mnemo
ADC
ADD
AND
BCP
Description
Add with Carry
Function/Example
A = A + M + C
A = A + M
Dst
Src
H
H
H
I
N
N
N
N
N
Z
Z
Z
Z
Z
C
C
C
A
M
M
M
M
Addition
A
Logical And
A = A . M
A
Bit compare A, Memory
Bit Reset
tst (A . M)
A
BRES
BSET
BTJF
BTJT
CALL
CALLR
CLR
bres Byte, #3
bset Byte, #3
btjf Byte, #3, Jmp1
btjt Byte, #3, Jmp1
M
M
M
M
Bit Set
Jump if bit is false (0)
Jump if bit is true (1)
Call subroutine
Call subroutine relative
Clear
C
C
reg, M
reg
0
N
N
N
1
Z
Z
Z
CP
Arithmetic Compare
One Complement
Decrement
tst(Reg - M)
A = FFH-A
dec Y
M
C
1
CPL
reg, M
reg, M
DEC
HALT
IRET
INC
Halt
0
I
Interrupt routine return
Increment
Pop CC, A, X, PC
inc X
H
N
N
Z
Z
C
reg, M
JP
Absolute Jump
Jump relative always
Jump relative
jp [TBL.w]
JRA
JRT
JRF
Never jump
jrf *
JRIH
JRIL
Jump if ext. interrupt = 1
Jump if ext. interrupt = 0
Jump if H = 1
JRH
H = 1 ?
JRNH
JRM
Jump if H = 0
H = 0 ?
Jump if I = 1
I = 1 ?
JRNM
JRMI
JRPL
JREQ
JRNE
JRC
Jump if I = 0
I = 0 ?
Jump if N = 1 (minus)
Jump if N = 0 (plus)
Jump if Z = 1 (equal)
Jump if Z = 0 (not equal)
Jump if C = 1
N = 1 ?
N = 0 ?
Z = 1 ?
Z = 0 ?
C = 1 ?
JRNC
JRULT
Jump if C = 0
C = 0 ?
Jump if C = 1
Unsigned <
Jmp if unsigned >=
Unsigned >
JRUGE Jump if C = 0
JRUGT Jump if (C + Z = 0)
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ST72121
INSTRUCTION GROUPS (Cont’d)
Mnemo
JRULE
LD
Description
Jump if (C + Z = 1)
Load
Function/Example
Unsigned <=
dst <= src
Dst
Src
H
I
N
N
N
N
N
Z
Z
Z
Z
Z
C
reg, M
A, X, Y
reg, M
M, reg
X, Y, A
MUL
NEG
NOP
OR
Multiply
X,A = X * A
0
0
Negate (2's compl)
No Operation
OR operation
Pop from the Stack
neg $10
C
A = A + M
pop reg
pop CC
push Y
C = 0
A
M
POP
reg
CC
M
M
M
H
I
C
0
PUSH
RCF
RET
RIM
Push onto the Stack
Reset carry flag
Subroutine Return
Enable Interrupts
Rotate left true C
Rotate right true C
Reset Stack Pointer
Subtract with Carry
Set carry flag
reg, CC
I = 0
0
RLC
RRC
RSP
SBC
SCF
SIM
C <= Dst <= C
C => Dst => C
S = Max allowed
A = A - M - C
C = 1
reg, M
reg, M
N
N
Z
Z
C
C
A
M
N
Z
C
1
Disable Interrupts
Shift left Arithmetic
Shift left Logic
I = 1
1
SLA
C <= Dst <= 0
C <= Dst <= 0
0 => Dst => C
Dst7 => Dst => C
A = A - M
reg, M
reg, M
reg, M
reg, M
A
N
N
0
Z
Z
Z
Z
Z
Z
Z
C
C
C
C
C
SLL
SRL
SRA
SUB
SWAP
TNZ
TRAP
WFI
Shift right Logic
Shift right Arithmetic
Subtraction
N
N
N
N
M
SWAP nibbles
Dst[7..4] <=> Dst[3..0] reg, M
tnz lbl1
Test for Neg & Zero
S/W trap
S/W interrupt
1
0
Wait for Interrupt
Exclusive OR
XOR
A = A XOR M
A
M
N
Z
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ST72121
6 ELECTRICAL CHARACTERISTICS
6.1 ABSOLUTE MAXIMUM RATINGS
This product contains devices to protect the inputs
against damage due to high static voltages, how-
ever it is advisable to take normal precaution to
avoid application of any voltage higher than the
specified maximum rated voltages.
Power Considerations.The average chip-junc-
tion temperature, T , in Celsius can be obtained
J
from:
T =
TA + PD x RthJA
J
Where: T =
Ambient Temperature.
A
For proper operation it is recommended that V
I
RthJA = Package thermal resistance
(junction-to ambient).
and V be higher than V and lower than V .
O
SS
DD
Reliability is enhanced if unused inputs are con-
nected to an appropriate logic voltage level (V
P
P
=
P
+ P
.
PORT
DD
D
INT
or V ).
SS
=
I
x V (chip internal power).
DD DD
INT
P
=Port power dissipation
determined by the user)
PORT
Symbol
Parameter
Digital Supply Voltage
Value
Unit
V
VDD
VDDA
VI
-0.3 to 6.0
Analog Supply and Reference Voltage
Input Voltage
VDD - 0.3 to VDD + 0.3
VSS - 0.3 to VDD + 0.3
V
V
V
SS - 0.3 to VDD + 0.3
VAI
Analog Input Voltage (A/D Converter)
V
VSSA-0.3 to VDDA+0.3
VO
IVDD
IVSS
TJ
Output Voltage
VSS - 0.3 to VDD + 0.3
V
Total Current into VDD (source)
Total Current out of VSS (sink)
Junction Temperature
Storage Temperature
100
100
mA
mA
°C
150
TSTG
-60 to 150
°C
Note: Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at these conditions is not implied. Exposure to maximum
rating conditions for extended periods may affect device reliability.
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ST72121
6.2 RECOMMENDED OPERATING CONDITIONS
Value
Typ.
Symbol
Parameter
Test Conditions
1 Suffix Version
Unit
Min.
0
Max.
70
°C
°C
°C
TA
Operating Temperature
6 Suffix Version
3 Suffix Version
-40
85
-40
125
f
OSC = 16 MHz (1 & 6 Suffix)
3.51)
3.0
5.5
5.5
VDD
Operating Supply Voltage
Oscillator Frequency
V
fOSC = 8 MHz
V
DD = 3.0V
02)
8
16
fOSC
MHz
VDD = 3.5V (1 & 6 Suffix)
02)
Note
1) A safe reset (with Low Voltage Detector option) is not guaranteed at 16 MHz.
2) A/D operation and Oscillator start-up are not guaranteed below 1MHz.
Figure 40. Maximum Operating Frequency (fOSC) Versus Supply Voltage (VDD)
FUNCTIONALITY NOT GUARANTEED IN THIS AREA
FUNCTIONALITY NOT GUARANTEED IN THIS AREA
f
OSC
[MHz]
FUNCTIONALITY GUARANTEED IN THIS AREA
FOR TEMPERATURE HIGHER THAN 85°C
16
8
4
1
0
Supplly Voltage
[V]
2.5
3
3.5
4
4.5
5
5.5
6
FUNCTIONALITY NOT GUARANTEED IN THIS AREA WITH RESONATOR
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ST72121
6.3 DC ELECTRICAL CHARACTERISTICS
(T = -40°C to +125°C and V = 5V unless otherwise specified)
A
DD
Value
Typ.
Symbol
VIL
Parameter
Test Conditions
3V < VDD < 5.5V
3V < VDD < 5.5V
Unit
Min.
Max.
Input Low Level Voltage
All Input pins
Input High Level Voltage
All Input pins
Hysteresis Voltage 1)
All Input pins
VDD x 0.3
V
V
VIH
VDD x 0.7
VHYS
400
mV
Low Level Output Voltage IOL = +10µA
0.1
0.4
All Output pins
IOL = + 2mA
IOL = +10µA
Low Level Output Voltage IOL = +10mA
0.1
1.5
3.0
3.0
VOL
V
High Sink I/O pins
IOL = + 15mA
IOL = + 20mA, TA = 85°C max
High Level Output Voltage IOH = - 10µA
4.9
4.2
VOH
V
All Output pins
IOH= - 2mA
IIL
IIH
Input Leakage Current
VIN = VSS (No Pull-up configured)
0.1
0.1
1.0
1.0
All Input pins but RESET 4) VIN = VDD
µA
Input Leakage Current
RESET pin
IIH
VIN = VDD
VIN > VIH
VIN < VIL
VIN < VIL
20
60
40
120
100
80
240
RON Reset Weak Pull-up RON
RPU I/O Weak Pull-up RPU
kΩ
kΩ
fOSC = 4 MHz, fCPU = 2 MHz
fOSC = 8 MHz, fCPU = 4 MHz
fOSC = 16 MHz, fCPU = 8 MHz
fOSC = 4 MHz, fCPU= 125 kHz
fOSC = 8 MHz, fCPU= 250 kHz
fOSC = 16 MHz, fCPU= 500 kHz
fOSC = 4MHz, fCPU = 2MHz
fOSC = 8MHz, fCPU = 4 MHz
fOSC = 16MHz, fCPU = 8 MHz
fOSC = 4 MHz, fCPU= 125 kHz
fOSC = 8 MHz, fCPU= 250 kHz
fOSC = 16 MHz, fCPU= 500 kHz
3.5
6
11
1.5
2.5
4.5
2
4
6.5
0.8
1
1.6
1
5
7
12
20
3
5
9
4
8
12
1.5
2
3.5
10
20
Supply Current in
RUN Mode 2)
mA
mA
mA
mA
µA
Supply Current in SLOW
Mode 2)
Supply Current in WAIT
IDD
Mode 3)
Supply Current in WAIT-
MINIMUM Mode5)
ILOAD = 0mA without LVD, TA = 85°C max
ILOAD = 0mA without LVD
ILOAD = 0mA with LVD
Supply Current in HALT
Mode
70
100
Notes:
1. Hysteresis voltage between switching levels. Based on characterisation results, not tested.
2. CPU running with memory access, no DC load or activity on I/O’s; clock input (OSCIN) driven by external square wave.
3. No DC load or activity on I/O’s; clock input (OSCIN) driven by external square wave.
4. Except OSCIN and OSCOUT
5. WAIT Mode with SLOW Mode selected. Based on characterisation results, not tested.
6.4 OSCILLATOR CHARACTERISTICS
(T = -40°C to +125°C unless otherwise specified)
A
Value
Typ.
Symbol
Parameter
Test Conditions
Unit
Min.
Max.
9
gm
Oscillator transconductance
Crystal frequency
2
1
mA/V
MHz
ms
fOSC
tstart
16
Osc. start up time
VDD = 5V±10%
50
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ST72121
6.5 PERIPHERAL CHARACTERISTICS
Low Voltage Detection Reset Electrical Specifications (Option)
Symbol
VLVDUP
Parameter
Conditions
Min.
Typ.
3.85
3.6
Max.
4.1
Unit
V
LVD Reset Trigger, VDD rising edge
LVD Reset Trigger, VDD falling edge
LVD Reset Trigger, hysteresis2)
fOSC = 8 MHz max1).
VLVDDOWN
VLVDHYS
3.35
3.85
V
250
mV
Notes:
1. The safe reset cannot be guaranted by the LVD when fosc is greater than 8MHz.
2. Based on characterisation results, not tested.
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ST72121
PERIPHERAL CHARACTERISTICS (Cont’d)
Serial Peripheral Interface
Value
Ref.
Symbol
Parameter
Condition
Unit
Min.
Max.
Master
Slave
1/128
dc
1/4
1/2
fSPI
tSPI
SPI frequency
fCPU
tCPU
Master
Slave
4
2
1
SPI clock periode
2
3
tLead
tLag
Enable lead time
Enable lag time
Slave
Slave
120
120
ns
ns
Master
Slave
100
90
4
5
tSPI_H
tSPI_L
tSU
Clock (SCK) high time
Clock (SCK) low time
Data set-up time
ns
ns
ns
ns
ns
ns
Master
Slave
100
90
Master
Slave
100
100
6
Master
Slave
100
100
7
tH
Data hold time (inputs)
Access time (time to data active
from high impedance state)
8
tA
0
120
240
Slave
Disable time (hold time to high im-
pedance state)
9
tDis
tV
Master (before capture edge)
Slave (after enable edge)
0.25
tCPU
ns
10
11
12
13
Data valid
120
Master (before capture edge)
Slave (after enable edge)
0.25
0
tCPU
ns
tHold
tRise
tFall
Data hold time (outputs)
Rise time
Outputs: SCK,MOSI,MISO
100
100
ns
µs
(20% VDD to 70% VDD, CL = 200pF) Inputs: SCK,MOSI,MISO,SS
Fall time Outputs: SCK,MOSI,MISO
(70% VDD to 20% VDD, CL = 200pF) Inputs: SCK,MOSI,MISO,SS
100
100
ns
µs
Measurement points are V , V , V and V in the SPI Timing Diagram
OL
OH
IL
IH
Figure 41. SPI Master Timing Diagram CPHA=0, CPOL=0
SS
(INPUT)
1
13
12
SCK
(OUTPUT)
5
4
MISO
(INPUT)
D7-IN
7
D6-IN
D0-IN
6
MOSI
(OUTPUT)
D7-OUT
11
D6-OUT
D0-OUT
10
VR000109
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ST72121
PERIPHERAL CHARACTERISTICS (Cont’d)
Measurement points are V , V , V and V in the SPI Timing Diagram
OL
OH
IL
IH
Figure 42. SPI Master Timing Diagram CPHA=0, CPOL=1
SS
(INPUT)
1
13
12
12
13
SCK
(OUTPUT)
5
4
MISO
(INPUT)
D7-IN
7
D6-IN
D0-IN
6
MOSI
(OUTPUT)
D7-OUT
11
D6-OUT
D0-OUT
10
VR000110
VR000107
VR000108
Figure 43. SPI Master Timing Diagram CPHA=1, CPOL=0
SS
(INPUT)
1
13
SCK
(OUTPUT)
4
5
MISO
(INPUT)
D7-OUT
D6-OUT
D0-OUT
6
7
MOSI
(OUTPUT)
D7-IN
11
D6-IN
D0-IN
10
Figure 44. SPI Master Timing Diagram CPHA=1, CPOL=1
SS
(INPUT)
1
12
SCK
(OUTPUT)
5
4
MISO
(INPUT)
D7-IN
7
D6-IN
D0-IN
6
MOSI
(OUTPUT)
D7-OUT
11
D6-OUT
D0-OUT
10
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ST72121
PERIPHERAL CHARACTERISTICS (Cont’d)
Measurement points are V , V , V and V in the SPI Timing Diagram
OL
OH
IL
IH
Figure 45. SPI Slave Timing Diagram CPHA=0, CPOL=0
SS
(INPUT)
2
1
12
3
13
11
SCK
(INPUT)
4
5
MISO HIGH-Z
D7-OUT
D6-OUT
D6-IN
D0-OUT
D0-IN
(OUTPUT)
8
10
9
MOSI
(INPUT)
D7-IN
7
6
VR000113
Figure 46. SPI Slave Timing Diagram CPHA=0, CPOL=1
SS
(INPUT)
2
1
13
12
11
3
SCK
(INPUT)
4
5
MISO
HIGH-Z
8
D7-OUT
D6-OUT
D6-IN
D0-OUT
D0-IN
(OUTPUT)
10
9
MOSI
(INPUT)
D7-IN
7
6
VR000114
Figure 47. SPI Slave Timing Diagram CPHA=1, CPOL=0
SS
(INPUT)
2
1
13
12
3
SCK
(INPUT)
4
5
HIGH-Z
8
MISO
D7-OUT
D6-OUT
D6-IN
D0-OUT
(OUTPUT)
11
9
10
MOSI
(INPUT)
D7-IN
D0-IN
7
6
VR000111
Figure 48. SPI Slave Timing Diagram CPHA=1, CPOL=1
SS
(INPUT)
2
1
12
13
3
SCK
(INPUT)
5
4
HIGH-Z
8
MISO
D7-OUT
D6-OUT
D6-IN
D0-OUT
(OUTPUT)
11
10
9
MOSI
(INPUT)
D7-IN
D0-IN
7
6
VR000112
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ST72121
7 GENERAL INFORMATION
7.1 EPROM ERASURE
EPROM version devices are erased by exposure
to high intensity UV light admitted through the
transparent window. This exposure discharges the
floating gate to its initial state through induced
photo current.
An opaque coating (paint, tape, label, etc...)
should be placed over the package window if the
product is to be operated under these lighting con-
ditions. Covering the window also reduces I
in
DD
power-saving modes due to photo-diode leakage
currents.
It is recommended that the EPROM devices be
kept out of direct sunlight, since the UV content of
sunlight can be sufficient to cause functional fail-
ure. Extended exposure to room level fluorescent
lighting may also cause erasure.
An Ultraviolet source of wave length 2537 Å yield-
2
ing a total integrated dosage of 15 Watt-sec/cm is
required to erase the device. It will be erased in 15
2
to 20 minutes if such a UV lamp with a 12mW/cm
power rating is placed 1 inch from the device win-
dow without any interposed filters.
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ST72121
7.2 PACKAGE MECHANICAL DATA
Figure 49. 42-Pin Shrink Plastic Dual In-Line Package, 600-mil Width
mm
inches
Dim.
A
Min Typ Max Min Typ Max
5.08 0.200
A1 0.51
0.020
A2 3.05 3.81 4.57 0.120 0.150 0.180
b
b2
C
0.46 0.56
1.02 1.14
0.018 0.022
0.040 0.045
0.23 0.25 0.38 0.009 0.010 0.015
36.58 36.83 37.08 1.440 1.450 1.460
D
E
15.24
16.00 0.600
0.630
E1 12.70 13.72 14.48 0.500 0.540 0.570
e
1.78
0.070
0.600
eA
eB
eC
L
15.24
18.54
0.730
0.060
1.52 0.000
PDIP42S
2.54 3.30 3.56 0.100 0.130 0.140
Number of Pins
N
42
Figure 50. 42-Pin Shrink Ceramic Dual In-Line Package, 600-mil Width
mm
Min Typ Max Min Typ Max
4.01 0.158
inches
Dim.
A
A1 0.76
0.38 0.46 0.56 0.015 0.018 0.022
B1 0.76 0.89 1.02 0.030 0.035 0.040
0.030
B
C
D
0.23 0.25 0.38 0.009 0.010 0.015
36.68 37.34 38.00 1.444 1.470 1.496
D1
35.56
1.400
E1 14.48 14.99 15.49 0.570 0.590 0.610
e
1.78
0.070
G
14.12 14.38 14.63 0.556 0.566 0.576
G1 18.69 18.95 19.20 0.736 0.746 0.756
G2 1.14 0.045
G3 11.05 11.30 11.56 0.435 0.445 0.455
G4 15.11 15.37 15.62 0.595 0.605 0.615
L
S
2.92
5.08 0.115
0.200
CDIP42SW
0.89
0.035
Number of Pins
N
42
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ST72121
Figure 51. 44-Pin Thin Quad Flat Package
mm
inches
Dim
Min Typ Max Min Typ Max
A
1.60
0.063
0.006
A1 0.05
0.15 0.002
A2 1.35 1.40 1.45 0.053 0.055 0.057
b
c
0.30 0.37 0.45 0.012 0.015 0.018
0.09 0.20 0.004 0.008
b
D
12.00
10.00
8.00
0.472
0.394
0.315
0.472
0.394
0.315
0.031
D1
D3
E
12.00
10.00
8.00
E1
E3
e
c
0.80
K
0° 3.5°
0.45 0.60 0.75 0.018 0.024 0.030
1.00 0.039
Number of Pins
44
7°
L
L1
L1
L
N
K
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ST72121
7.3 ORDERING INFORMATION
Each device is available for production in user pro-
grammable version (OTP) as well as in factory
coded version (ROM). OTP devices are shipped to
customer with a default blank content FFh, while
ROM factory coded parts contain the code sent by
customer. There is one common EPROM version
for debugging and prototyping which features the
maximum memory size and peripherals of the
family. Care must be taken to only use resources
available on the target device.
7.3.1 Transfer Of Customer Code
Customer code is made up of the ROM contents
and the list of the selected options (if any). The
ROM contents are to be sent on diskette, or by
electronic means, with the hexadecimal file gener-
ated by the development tool. All unused bytes
must be set to FFh.
The selected options are communicated to STMi-
croelectronics using the correctly completed OP-
TION LIST appended.
The STMicroelectronics Sales Organization will be
pleased to provide detailed information on con-
tractual points.
Figure 52. ROM Factory Coded Device Types
TEMP.
PACKAGE RANGE
/
XXX
DEVICE
Code name (defined by STMicroelectronics)
1 = standard 0 to +70°C
3 = automotive -40 to +125°C
6 = industrial -40 to +85°C
B= Plastic DIP
T= Plastic TQFP
ST72121J2
ST72121J4
Figure 53. OTP User Programmable Device Types
TEMP.
PACKAGE RANGE
DEVICE
X
S= LVD Reset option
3 = automotive -40 to +125°C
6= industrial -40 to +85 °C
B= Plastic DIP
T= Plastic TQFP
ST72T121J2
ST72T121J4
Note: The ST72E121J4D0 (CERDIP 25 °C) is used as the EPROM versions for the above devices.
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ST72121
ST72121 MICROCONTROLLER OPTION LIST
Customer . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact
Phone No . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
STMicroelectronics references
Device:
Option:
[ ] ST72121J2
[ ] ST72121J4
[ ] Software Watchdog [ ] Hardware Watchdog
[ ] Low Voltage Detector Reset
Package:
[ ] Dual In-Line Plastic [ ] Thin Quad Flat Pack:
[ ] Standard (Stick)
[ ] Tape & Reel
Temperature Range:
Special Marking:
[ ] 0°C to + 70°C
[ ] No
[ ] - 40°C to + 85°C
[ ] - 40°C to + 125°C
[ ] Yes "_ _ _ _ _ _ _ _ _ _ _ "
Authorized characters are letters, digits, '.', '-', '/' and spaces only.
Maximum character count: SDIP42:
TQFP44:
16
10
Comments :
Supply Operating Range in the application:
Oscillator Frequency in the application:
Notes
Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Date . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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ST72121
Notes:
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
1999 STMicroelectronics - All Rights Reserved.
Purchase of I2C Components by STMicroelectronics conveys a license under the Philips I2C Patent. Rights to use these components in an
I2C system is granted provided that the system conforms to the I2C Standard Specification as defined by Philips.
STMicroelectronics Group of Companies
Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands -
Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
http://www.st.com
87/87
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