ST72215G [STMICROELECTRONICS]
8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, I2C INTERFACES; 8位MCU单电压闪存， ADC ， 16位定时器， SPI ， I2C INTERFACES
| 型号： | ST72215G |
| 厂家： | 
ST |
| 描述： | 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, I2C INTERFACES |
| 文件： | 总135页 (文件大小：902K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ST72104G, ST72215G,
ST72216G, ST72254G
8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY,
2
ADC, 16-BIT TIMERS, SPI, I C INTERFACES
PRELIMINARY DATA
■ Memories
– 4K or 8K bytes Program memory (ROM and
single voltage FLASH) with read-out protec-
tion and in-situ programming (remote ISP)
– 256 bytes RAM
■ Clock, Reset and Supply Management
– Enhanced reset system
SDIP32
SO28
– Enhanced low voltage supply supervisor with
3 programmable levels
– Clock sources: crystal/ceramic resonator os-
cillators or RC oscillators, external clock,
backup Clock Security System
– Clock-out capability
– 3 Power Saving Modes: Halt, Wait and Slow
■ Interrupt Management
– 7 interrupt vectors plus TRAP and RESET
– 22 external interrupt lines (on 2 vectors)
■ 22 I/O Ports
■ Instruction Set
– 8-bit data manipulation
– 63 basic instructions
– 17 main addressing modes
– 8 x 8 unsigned multiply instruction
– True bit manipulation
– 22 multifunctional bidirectional I/O lines
– 14 alternate function lines
– 8 high sink outputs
■ 3 Timers
– Configurable watchdog timer
– Two 16-bittimers with: 2 input captures, 2 out-
put compares, external clock input on one tim-
er, PWM and Pulse generator modes
■ Development Tools
– Full hardware/softwaredevelopment package
(one only on ST72104Gx and ST72216G1)
■ 2 Communications Interfaces
– SPI synchronous serial interface
– I2C multimaster interface
(only on ST72254Gx)
■ 1 Analog peripheral
– 8-bit ADC with 6 input channels
(except on ST72104Gx)
Device Summary
Features
ST72104G1
ST72104G2
ST72216G1
ST72215G2
ST72254G1
ST72254G2
Program memory -bytes
RAM (stack) - bytes
4K
8K
4K
8K
4K
8K
256 (128)
Watchdog timer,
One 16-bit timer,
SPI
Watchdog timer, Watchdog timer,
One 16-bit timer, Two 16-bit timers,
Watchdog timer,
Two 16-bit timers,
SPI, I C, ADC
Peripherals
SPI, ADC
SPI, ADC
Operating Supply
CPU Frequency
Operating Temperature
Packages
3.0V to 5.5V
Up to 8 MHz (with oscillator up to 16 MHz)
-40°C to +85°C (-40°C to +105/125°C optional)
SO28 / SDIP32
Rev. 2.2
February 2000
1/135
This ispreliminary information on a new product in development or undergoing evaluation. Details aresubject to change without notice.
1
Table of Contents
1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.3 STRUCTURAL ORGANISATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.4 IN-SITU PROGRAMMING (ISP) MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.5 MEMORY READ-OUT PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.1 LOW VOLTAGE DETECTOR (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.2 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.2.2 Asynchronous External RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.2.3 Internal Low Voltage Detection RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.2.4 Internal Watchdog RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.3 MULTI-OSCILLATOR (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.4 CLOCK SECURITY SYSTEM (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.4.1 Clock Filter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.4.2 Safe Oscillator Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.4.3 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.4.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.5 CLOCK RESET AND SUPPLY REGISTER DESCRIPTION (CRSR) . . . . . . . . . . . . . . . 23
6.6 MAIN CLOCK CONTROLLER (MCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.1 NON MASKABLE SOFTWARE INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.2 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.3 PERIPHERAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
8 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8.2 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8.3 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.4 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
9 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9.2.1 Input Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
135
9.2.2 Output Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9.2.3 Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
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Table of Contents
9.4 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9.5 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9.6 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10 MISCELLANEOUS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
10.1 I/O PORT INTERRUPT SENSITIVITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
10.2 I/O PORT ALTERNATE FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
10.3 MISCELLANEOUS REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
11 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
11.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
11.1.1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
11.1.2Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
11.1.3Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
11.1.4Hardware Watchdog Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
11.1.5Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
11.1.6Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
11.1.7Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
11.2 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
11.2.1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
11.2.2Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
11.2.3Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
11.2.4Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
11.2.5Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
11.2.6Summary of Timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
11.2.7Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
11.3 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
11.3.1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
11.3.2Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
11.3.3General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
11.3.4Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
11.3.5Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
11.3.6Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
11.3.7Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
11.4 I2C BUS INTERFACE (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
11.4.1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
11.4.2Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
11.4.3General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
11.4.4Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
11.4.5Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
11.4.6Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
11.4.7Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
11.5 8-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
11.5.1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
11.5.2Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
11.5.3Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
11.5.4Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
11.5.5Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
11.5.6Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
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ST72104G, ST72215G, ST72216G, ST72254G
12 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
12.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
12.1.1Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
12.1.2Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
12.1.3Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
12.1.4Indexed (No Offset, Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
12.1.5Indirect (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
12.1.6Indirect Indexed (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
12.1.7Relative mode (Direct, Indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
12.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
13 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
13.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
13.1.1Minimum and Maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
13.1.2Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
13.1.3Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
13.1.4Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
13.1.5Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
13.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
13.2.1Voltage Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
13.2.2Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
13.2.3Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
13.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
13.3.1General Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
13.3.2Operating Conditions with Low Voltage Detector (LVD) . . . . . . . . . . . . . . . . . . . . . 99
13.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
13.4.1RUN and SLOW Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
13.4.2WAIT and SLOW WAIT Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
13.4.3HALT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
13.4.4Supply and Clock Managers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
13.4.5On-Chip Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
13.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
13.5.1General Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
13.5.2External Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
13.5.3Crystal and Ceramic Resonator Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
13.5.4RC Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
13.5.5Clock Security System (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
13.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
13.6.1RAM and Hardware Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
13.6.2FLASH Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
13.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
13.7.1Functional EMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
13.7.2Absolute Electrical Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
13.7.3ESD Pin Protection Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
13.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
13.8.1General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
13.8.2Output Driving Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
13.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
4/135
ST72104G, ST72215G, ST72216G, ST72254G
13.9.1Asynchronous RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
13.9.2ISPSEL Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
13.10 TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
13.10.1Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
13.10.216-Bit Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
13.11 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 121
13.11.1SPI - Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
13.11.2I2C - Inter IC Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
13.12 8-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
14 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
14.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
14.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
14.3 SOLDERING AND GLUEABILITY INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
14.4 PACKAGE/SOCKET FOOTPRINT PROPOSAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
15 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . 129
15.1 OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
15.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . 130
15.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
15.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
15.5 TO GET MORE INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
16 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
5/135
ST72104G, ST72215G, ST72216G, ST72254G
1 INTRODUCTION
The ST72104G, ST72215G, ST72216G and
ST72254G devices are members of the ST7 mi-
crocontroller family. They can be grouped as fol-
lows:
Under software control, all devices can be placed
in WAIT, SLOW, or HALT mode, reducing power
consumption when the application is in idle or
standby state.
– ST72254G devices are designed for mid-range
applications with ADC and I C interface capabili-
ties.
The enhanced instruction set and addressing
modes of the ST7 offer both power and flexibility to
software developers, enabling the design of highly
efficient and compact application code. In addition
to standard 8-bit data management, all ST7 micro-
controllers feature true bit manipulation, 8x8 un-
signed multiplication and indirect addressing
modes.
– ST72215/6G devices target the same range of
applications but without I C interface.
– ST72104G devices are for applications that do
not need ADC and I C peripherals.
All devices are based on a common industry-
standard 8-bit core, featuring an enhanced instruc-
tion set.
For easy reference, all parametric data are located
in Section 13 on page 96.
The ST72C104G, ST72C215G, ST72C216G and
ST72C254G versions feature single-voltage
FLASH memory with byte-by-byte In-Situ Pro-
gramming (ISP) capability.
Figure 1. General Block Diagram
Internal
CLOCK
OSC1
OSC2
MULTI OSC
+
2
I C
CLOCK FILTER
PA7:0
(8 bits)
PORT A
LVD
V
SPI
DD
POWER
SUPPLY
PB7:0
V
SS
PORT B
16-BIT TIMER A
PORT C
(8 bits)
RESET
CONTROL
8-BIT CORE
ALU
PC5:0
(6 bits)
PROGRAM
MEMORY
8-BIT ADC
(4 or 8K Bytes)
16-BIT TIMER B
RAM
(256 Bytes)
WATCHDOG
6/135
4
ST72104G, ST72215G, ST72216G, ST72254G
2 PIN DESCRIPTION
Figure 2. 28-Pin SO Package Pinout
RESET
V
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
DD
OSC1
OSC2
V
2
SS
ISPSEL
3
SS/PB7
ISPCLK/SCK/PB6
ISPDATA/MISO/PB5
MOSI/PB4
PA0 (HS)
PA1 (HS)
PA2 (HS)
PA3 (HS)
PA4 (HS)/SCLI
PA5 (HS)
4
5
6
7
ei1
ei0
OCMP2_A/PB3
8
ICAP2_A/PB2
OCMP1_A/PB1
9
10
11
12
PA6 (HS)/SDAI
PA7 (HS)
ICAP1_A/PB0
AIN5/EXTCLK_A/PC5
AIN4/OCMP2_B/PC4
PC0/ICAP1_B/AIN0
PC1/OCMP1_B/AIN1
PC2/MCO/AIN2
13
14
ei0 or ei1
AIN3/ICAP2_B/PC3
(HS) 20mA high sink capability
eiX associated external interrupt vector
Figure 3. 32-Pin SDIP Package Pinout
V
RESET
1
2
3
4
5
6
7
8
9
DD
32
V
OSC1
OSC2
SS
31
30
29
ISPSEL
SS/PB7
PA0 (HS)
PA1 (HS)
PA2 (HS)
PA3 (HS)
ISPCLK/SCK/PB6
ISPDATA/MISO/PB5
MOSI/PB4
28
27
26
25
24
23
22
21
20
19
18
17
ei1
ei0
NC
NC
NC
OCMP2_A/PB3
NC
PA4 (HS)/SCLI
10
ICAP2_A/PB2
11
12
13
14
15
16
PA5 (HS)
ei1 ei0
ei0or ei1
OCMP1_A/PB1
PA6 (HS)/SDAI
PA7 (HS)
ICAP1_A/PB0
AIN5/EXTCLK_A/PC5
AIN4/OCMP2_B/PC4
AIN3/ICAP2_B/PC3
PC0/ICAP1_B/AIN0
PC1/OCMP1_B/AIN1
PC2/MCO/AIN2
(HS) 20mA high sink capability
eiX associated external interrupt vector
7/135
5
ST72104G, ST72215G, ST72216G, ST72254G
PIN DESCRIPTION (Cont’d)
For external pin connection guidelines, refer to Section 13 ”ELECTRICAL CHARACTERISTICS” on page
96.
Legend / Abbreviations for Table 1:
Type:
I = input, O = output, S = supply
A = Dedicated analog input
Input level:
In/Output level: C = CMOS 0.3V /0.7V
,
DD
DD
C = CMOS 0.3V /0.7V with input trigger
T
DD
DD
Output level:
HS = 20mA high sink (on N-buffer only)
Port and control configuration:
1)
– Input:
float = floating, wpu = weak pull-up, int = interrupt , ana = analog
2)
– Output:
OD = open drain , PP = push-pull
Refer to Section 9 ”I/O PORTS” on page 30 for more details on the software configuration of the I/O ports.
The RESET configuration of each pin is shown in bold. This configuration is valid as long as the device is
in reset state.
Table 1. Device Pin Description
Pin n°
Level
Port / Control
Main
Function
(after reset)
Input
Output
Pin Name
Alternate Function
1
2
1
2
RESET
I/O
I
C
X
X
Top priority non maskable interrupt (active low)
T
External clock input or Resonator oscillator in-
verter input or resistor input for RC oscillator
3)
OSC1
OSC2
Resonator oscillator inverter output or capaci-
tor input for RC oscillator
3)
3
3
O
4
5
4
5
PB7/SS
I/O
I/O
C
X
X
ei1
ei1
X
X
X
X
Port B7
Port B6
SPI Slave Select (active low)
SPI Serial Clock or ISP Clock
T
PB6/SCK/ISPCLK
C
C
C
T
SPI Master In/ Slave Out Data
or ISP Data
6
6
7
PB5/MISO/ISPDATA I/O
X
X
ei1
ei1
X
X
X
X
Port B5
Port B4
T
T
7
8
PB4/MOSI
NC
I/O
SPI Master Out / Slave In Data
Not Connected
9
NC
10
11
8
9
PB3/OCMP2_A
PB2/ICAP2_A
I/O
I/O
I/O
I/O
C
C
C
C
X
X
X
X
ei1
ei1
ei1
ei1
X
X
X
X
X
X
X
X
Port B3
Port B2
Port B1
Port B0
Timer A Output Compare 2
Timer A Input Capture 2
Timer A Output Compare 1
Timer A Input Capture 1
T
T
T
T
12 10 PB1 /OCMP1_A
13 11 PB0 /ICAP1_A
Timer A Input Clock or ADC
Analog Input 5
14 12 PC5/EXTCLK_A/AIN5 I/O
15 13 PC4/OCMP2_B/AIN4 I/O
16 14 PC3/ ICAP2_B/AIN3 I/O
C
C
C
C
X
X
X
X
ei0/ei1
ei0/ei1
ei0/ei1
ei0/ei1
X
X
X
X
X
X
X
X
Port C5
Port C4
Port C3
Port C2
T
T
T
T
Timer B Output Compare 2 or
ADC Analog Input 4
Timer B Input Capture 2 or
ADC Analog Input 3
X
X
Main clock output (f
) or
CPU
17 15 PC2/MCO/AIN2
I/O
ADC Analog Input 2
8/135
6
ST72104G, ST72215G, ST72216G, ST72254G
Pin n°
Level
Port / Control
Main
Function
(after reset)
Input
Output
Pin Name
Alternate Function
Timer B Output Compare 1 or
ADC Analog Input 1
18 16 PC1/OCMP1_B/AIN1 I/O
C
C
X
X
ei0/ei1
ei0/ei1
X
X
X
X
X
Port C1
Port C0
T
Timer B Input Capture 1 or
ADC Analog Input 0
19 17 PC0/ICAP1_B/AIN0
I/O
X
X
T
20 18 PA7
I/O
I/O
I/O
I/O
C
C
C
C
HS
X
X
X
X
ei0
ei0
ei0
ei0
X
T
X
T
Port A7
Port A6
Port A5
Port A4
T
2
21 19 PA6 /SDAI
22 20 PA5
HS
HS
HS
I C Data
T
T
T
X
2
23 21 PA4 /SCLI
I C Clock
24
25
NC
NC
Not Connected
26 22 PA3
27 23 PA2
28 24 PA1
29 25 PA0
I/O
I/O
I/O
I/O
C
C
C
C
HS
HS
HS
HS
X
X
X
X
ei0
ei0
ei0
ei0
X
X
X
X
X
X
X
X
Port A3
Port A2
Port A1
Port A0
T
T
T
T
In situ programming selection (Should be tied
low in standard user mode).
30 26 ISPSEL
I
C
X
31 27 V
32 28 V
S
S
Ground
SS
DD
Main power supply
Notes:
1. In the interrupt input column, “eiX” defines the associated external interrupt vector. If the weak pull-up
column (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input,
else the configuration is floating interrupt input.
2. In the open drain output column, “T” defines a true open drain I/O (P-Buffer and protection diode to V
DD
are not implemented). See Section 9 ”I/O PORTS” on page 30 and Section 13.8 ”I/O PORT PIN CHAR-
ACTERISTICS” on page 114 for more details.
3. OSC1 and OSC2 pins connect a crystal or ceramic resonator, an external RC, or an external source to
the on-chip oscillator see Section 2 ”PIN DESCRIPTION” on page 7 and Section 13.5 ”CLOCK AND TIM-
ING CHARACTERISTICS” on page 104 for more details.
9/135
ST72104G, ST72215G, ST72216G, ST72254G
3 REGISTER & MEMORY MAP
As shown in the Figure 4, the MCU is capable of
addressing 64K bytes of memories and I/O regis-
ters.
IMPORTANT: Memory locations marked as “Re-
served” must never be accessed. Accessing a re-
seved area can have unpredicable effects on the
device.
The available memory locations consist of 128
bytes of register location, 256 bytes of RAM and
up to 8Kbytes of user program memory. The RAM
space includes up to 128 bytes for the stack from
0100h to 017Fh.
The highest address bytes contain the user reset
and interrupt vectors.
Figure 4. Memory Map
0000h
HW Registers
(see Table 2)
0080h
Short Addressing RAM
007Fh
0080h
Zero page
(128 Bytes)
00FFh
256 Bytes RAM
0100h
Stack or
16-bit Addressing RAM
017Fh
0180h
(128 Bytes)
017Fh
Reserved
DFFFh
E000h
Program Memory
E000h
(4K, 8 KBytes)
FFDFh
8 KBytes
F000h
FFE0h
Interrupt & Reset Vectors
4 KBytes
FFFFh
(see Table 5 on page 26)
FFFFh
10/135
ST72104G, ST72215G, ST72216G, ST72254G
Table 2. Hardware Register Map
Register
Reset
Status
Address
Block
Register Name
Port C Data Register
Port C Data Direction Register
Port C Option Register
Remarks
Label
1)
2)
0000h
0001h
0002h
PCDR
PCDDR
PCOR
00h
R/W
2)
2)
Port C
00h
00h
R/W
R/W
0003h
Reserved (1 Byte)
1)
0004h
0005h
0006h
PBDR
PBDDR
PBOR
Port B Data Register
Port B Data Direction Register
Port B Option Register
00h
R/W
R/W
R/W.
Port B
Port A
00h
00h
0007h
Reserved (1 Byte)
1)
R/W
R/W
0008h
0009h
000Ah
PADR
PADDR
PAOR
Port A Data Register
Port A Data Direction Register
Port A Option Register
00h
00h
00h
R/W
000Bh
to
Reserved (21 Bytes)
001Fh
0020h
MISCR1
Miscellaneous Register 1
00h
R/W
0021h
0022h
0023h
SPIDR
SPICR
SPISR
SPI Data I/O Register
SPI Control Register
SPI Status Register
xxh
0xh
00h
R/W
R/W
Read Only
SPI
0024h
0025h
WATCHDOG WDGCR
CRSR
Watchdog Control Register
7Fh
R/W
Clock, Reset, Supply Control / Status Register 000x 000x R/W
Reserved (2 bytes)
0026h
0027h
0028h
0029h
002Ah
002Bh
002Ch
002Dh
002Eh
I2CCR
I2CSR1
I2CSR2
I2CCCR
I2COAR1
I2COAR2
I2CDR
Control Register
Status Register 1
Status Register 2
Clock Control Register
Own Address Register 1
Own Address Register 2
Data Register
00h
00h
00h
00h
00h
00h
00h
R/W
Read Only
Read Only
R/W
R/W
R/W
2
I C
R/W
002Fh
to
Reserved (4 Bytes)
0030h
11/135
ST72104G, ST72215G, ST72216G, ST72254G
Register
Label
Reset
Status
Address
Block
Register Name
Remarks
R/W
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
TACR2
TACR1
TASR
TAIC1HR
TAIC1LR
TAOC1HR
TAOC1LR
TACHR
Timer A Control Register 2
Timer A Control Register 1
Timer A Status Register
Timer A Input Capture 1 High Register
Timer A Input Capture 1 Low Register
Timer A Output Compare 1 High Register
Timer A Output Compare 1 Low Register
Timer A Counter High Register
00h
00h
xxh
xxh
xxh
80h
00h
FFh
FCh
FFh
FCh
xxh
xxh
80h
00h
R/W
Read Only
Read Only
Read Only
R/W
R/W
TIMER A
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
R/W
TACLR
Timer A Counter Low Register
TAACHR
TAACLR
TAIC2HR
TAIC2LR
TAOC2HR
TAOC2LR
Timer A Alternate Counter High Register
Timer A Alternate Counter Low Register
Timer A Input Capture 2 High Register
Timer A Input Capture 2 Low Register
Timer A Output Compare 2 High Register
Timer A Output Compare 2 Low Register
R/W
0040h
MISCR2
Miscellaneous Register 2
00h
R/W
0041h
0042h
0043h
0044h
0045h
0046h
0047h
0048h
0049h
004Ah
004Bh
004Ch
004Dh
004Eh
004Fh
TBCR2
TBCR1
TBSR
TBIC1HR
TBIC1LR
TBOC1HR
TBOC1LR
TBCHR
Timer B Control Register 2
Timer B Control Register 1
Timer B Status Register
Timer B Input Capture 1 High Register
Timer B Input Capture 1 Low Register
Timer B Output Compare 1 High Register
Timer B Output Compare 1 Low Register
Timer B Counter High Register
00h
00h
xxh
xxh
xxh
80h
00h
FFh
FCh
FFh
FCh
xxh
xxh
80h
00h
R/W
R/W
Read Only
Read Only
Read Only
R/W
R/W
TIMER B
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
R/W
TBCLR
Timer B Counter Low Register
TBACHR
TBACLR
TBIC2HR
TBIC2LR
TBOC2HR
TBOC2LR
Timer B Alternate Counter High Register
Timer B Alternate Counter Low Register
Timer B Input Capture 2 High Register
Timer B Input Capture 2 Low Register
Timer B Output Compare 2 High Register
Timer B Output Compare 2 Low Register
R/W
0050h
to
Reserved (32 Bytes)
006Fh
0070h
0071h
ADCDR
ADCCSR
Data Register
Control/Status Register
00h
00h
Read Only
R/W
ADC
0072h
to
Reserved (14 Bytes)
007Fh
Legend: x=undefined, R/W=read/write
Notes:
1. The contents of the I/O port DR registers are readable only in output configuration. In input configura-
tion, the values of the I/O pins are returned instead of the DR register contents.
2. The bits associated with unavailable pins must always keep their reset value.
12/135
ST72104G, ST72215G, ST72216G, ST72254G
4 FLASH PROGRAM MEMORY
4.1 INTRODUCTION
This mode needs five signals (plus the V signal
if necessary) to be connected to the programming
tool. This signals are:
DD
FLASH devices have a single voltage non-volatile
FLASH memory that may be programmed in-situ
(or plugged in a programming tool) on a byte-by-
byte basis.
– RESET: device reset
– V : device ground power supply
SS
– ISPCLK: ISP output serial clock pin
– ISPDATA: ISP input serial data pin
4.2 MAIN FEATURES
– ISPSEL: Remote ISP mode selection. This pin
must be connected to V on the application
■ Remote In-Situ Programming (ISP) mode
■ Up to 16 bytes programmed in the same cycle
■ MTP memory (Multiple Time Programmable)
■ Read-out memory protection against piracy
SS
board through a pull-down resistor.
If any of these pins are used for other purposes on
the application, a serial resistor has to be imple-
mented to avoid a conflict if the other device forces
the signal level.
4.3 STRUCTURAL ORGANISATION
Figure 5 shows a typical hardware interface to a
standard ST7 programming tool. For more details
on the pin locations, refer to the device pinout de-
scription.
The FLASH program memory is organised in a
single 8-bit wide memory block which can be used
for storing both code and data constants.
Figure 5. Typical Remote ISP Interface
The FLASH program memory is mapped in the up-
per part of the ST7 addressing space and includes
the reset and interrupt user vector area .
HE10 CONNECTOR TYPE
TO PROGRAMMING TOOL
XTAL
4.4 IN-SITU PROGRAMMING (ISP) MODE
1
C
C
L0
L1
The FLASH program memory can be programmed
using Remote ISP mode. This ISP mode allows
the contents of the ST7 program memory to be up-
dated using a standard ST7 programming tools af-
ter the device is mounted on the application board.
This feature can be implemented with a minimum
number of added components and board area im-
pact.
ISPSEL
10KΩ
V
SS
RESET
ISPCLK
An exampleRemote ISP hardware interface to the
standard ST7 programming tool is described be-
low. For more details on ISP programming, refer to
the ST7 Programming Specification.
ST7
ISPDATA
47KΩ
Remote ISP Overview
The Remote ISP mode is initiated by a specific se-
quence on the dedicated ISPSEL pin.
APPLICATION
The Remote ISP is performed in three steps:
– Selection of the RAM execution mode
– Download of Remote ISP code in RAM
4.5 MEMORY READ-OUT PROTECTION
The read-out protection is enabled through an op-
tion bit.
– Execution of Remote ISP code in RAM to pro-
gram the user program into the FLASH
For FLASH devices, when this option is selected,
the program and data stored in the FLASH memo-
ry are protected against read-out piracy (including
a re-write protection). When this protection option
is removed the entire FLASH program memory is
Remote ISP hardware configuration
In Remote ISP mode, the ST7 has to be supplied
2
with power (V and V ) and a clock signal (os-
DD
SS
first automatically erased. However, the E PROM
cillator and application crystal circuit for example).
data memory (when available) can be protected
only with ROM devices.
13/135
ST72104G, ST72215G, ST72216G, ST72254G
5 CENTRAL PROCESSING UNIT
5.1 INTRODUCTION
Accumulator (A)
The Accumulator is an 8-bit general purpose reg-
ister used to hold operands and the results of the
arithmetic and logic calculations and to manipulate
data.
This CPU has a full 8-bit architecture and contains
six internal registers allowing efficient 8-bit data
manipulation.
Index Registers (X and Y)
5.2 MAIN FEATURES
In indexed addressing modes, these 8-bit registers
are used to create either effective addresses or
temporary storage areas for data manipulation.
(The Cross-Assembler generates a precede in-
struction (PRE) to indicate that the following in-
struction refers to the Y register.)
■ 63 basic instructions
■ Fast 8-bit by 8-bit multiply
■ 17 main addressing modes
■ Two 8-bit index registers
■ 16-bit stack pointer
The Y register is not affected by the interrupt auto-
matic procedures (not pushed to and popped from
the stack).
■ Low power modes
■ Maskable hardware interrupts
■ Non-maskable software interrupt
Program Counter (PC)
The program counter is a 16-bit register containing
the address of the next instruction to be executed
by the CPU. It is made of two 8-bit registers PCL
(Program Counter Low which is the LSB) and PCH
(Program Counter High which is the MSB).
5.3 CPU REGISTERS
The 6 CPU registers shown in Figure 6 are not
present in the memory mapping and are accessed
by specific instructions.
Figure 6. CPU Registers
7
0
ACCUMULATOR
RESET VALUE = XXh
7
0
0
X INDEX REGISTER
Y INDEX REGISTER
RESET VALUE = XXh
7
RESET VALUE = XXh
PCL
PCH
7
8
15
0
PROGRAM COUNTER
RESET VALUE = RESET VECTOR @ FFFEh-FFFFh
7
1
0
1
1
1
1
H I N Z
C
CONDITION CODE REGISTER
RESET VALUE =
8
1
X 1 X X X
0
15
7
STACK POINTER
RESET VALUE = STACK HIGHER ADDRESS
X = Undefined Value
14/135
ST72104G, ST72215G, ST72216G, ST72254G
CPU REGISTERS (Cont’d)
CONDITION CODE REGISTER (CC)
Read/Write
the interrupt routine. If the I bit is cleared by soft-
ware in the interrupt routine, pending interrupts are
serviced regardless of the priority level of the cur-
rent interrupt routine.
Reset Value: 111x1xxx
7
0
Bit 2 = N Negative.
1
1
1
H
I
N
Z
C
This bit is set and cleared by hardware. It is repre-
sentative of the result sign of the last arithmetic,
The 8-bit Condition Code register contains the in-
terrupt mask and four flags representative of the
result of the instruction just executed. This register
can also be handled by the PUSH and POP in-
structions.
th
logical or data manipulation. It is a copy of the 7
bit of the result.
0: The result of the last operation is positive or null.
1: The result of the last operation is negative
(i.e. the most significant bit is a logic 1).
These bits can be individually tested and/or con-
trolled by specific instructions.
This bit is accessed by the JRMI and JRPL instruc-
tions.
Bit 4 = H Half carry.
Bit 1 = Z Zero.
This bit is set by hardware when a carry occurs be-
tween bits 3 and 4 of the ALU during an ADD or
ADC instruction. It is reset by hardware during the
same instructions.
0: No half carry has occurred.
1: A half carry has occurred.
This bit is set and cleared by hardware. This bit in-
dicates that the result of the last arithmetic, logical
or data manipulation is zero.
0: The result of the last operation is different from
zero.
1: The result of the last operation is zero.
This bit is tested using the JRH or JRNH instruc-
tion. The H bit is useful in BCD arithmetic subrou-
tines.
This bit is accessed by the JREQ and JRNE test
instructions.
Bit 3 = I Interrupt mask.
Bit 0 = C Carry/borrow.
This bit is set and cleared by hardware and soft-
ware. It indicates an overflow or an underflow has
occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.
This bit is set by hardware when entering in inter-
rupt or by software to disable all interrupts except
the TRAP software interrupt. This bit is cleared by
software.
0: Interrupts are enabled.
1: Interrupts are disabled.
This bit is driven by the SCF and RCF instructions
and tested by the JRC and JRNC instructions. It is
also affected by the “bit test and branch”, shift and
rotate instructions.
This bit is controlled by the RIM, SIM and IRET in-
structions and is tested by the JRM and JRNM in-
structions.
Note: Interrupts requested while I is set are
latched and can be processed when I is cleared.
By default an interrupt routine is not interruptable
because the I bit is set by hardware when you en-
ter it and reset by the IRET instruction at the end of
15/135
ST72104G, ST72215G, ST72216G, ST72254G
CENTRAL PROCESSING UNIT (Cont’d)
Stack Pointer (SP)
The least significant byte of the Stack Pointer
(called S) can be directly accessed by a LD in-
struction.
Read/Write
Reset Value: 01 7Fh
Note: When the lower limit is exceeded, the Stack
Pointer wraps around to the stack upper limit, with-
out indicating the stack overflow. The previously
stored information is then overwritten and there-
fore lost. The stack also wraps in case of an under-
flow.
15
8
1
0
0
0
0
0
0
0
7
0
The stack is used to save the return address dur-
ing a subroutine call and the CPU context during
an interrupt. The user may also directly manipulate
the stack by means of the PUSH and POP instruc-
tions. In the case of an interrupt, the PCL is stored
at the first location pointed to by the SP. Then the
other registers are stored in the next locations as
shown in Figure 7.
0
SP6
SP5
SP4
SP3
SP2
SP1
SP0
The Stack Pointer is a 16-bit register which is al-
ways pointing to the next free location in the stack.
It is then decremented after data has been pushed
onto the stack and incremented before data is
popped from the stack (see Figure 7).
– When an interrupt is received, the SP is decre-
mented and the context is pushed on the stack.
Since the stack is 128 bytes deep, the 9th most
significant bits are forced by hardware. Following
an MCU Reset, or after a Reset Stack Pointer in-
struction (RSP), the Stack Pointer contains its re-
set value (the SP6 to SP0 bits are set) which is the
stack higher address.
– On return from interrupt, the SP is incremented
and the context is popped from the stack.
A subroutine call occupies two locations and an in-
terrupt five locations in the stack area.
Figure 7. Stack Manipulation Example
CALL
Subroutine
RET
or RSP
PUSH Y
POP Y
IRET
Interrupt
Event
@ 0100h
SP
SP
SP
Y
CC
A
CC
CC
A
A
X
X
X
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
SP
SP
PCH
PCH
PCL
SP
@ 017Fh PCL
Stack Higher Address = 017Fh
0100h
Stack Lower Address =
16/135
ST72104G, ST72215G, ST72216G, ST72254G
6 SUPPLY, RESET AND CLOCK MANAGEMENT
The ST72104G, ST72215G, ST72216G and
ST72254G microcontrollers include a range of util-
ity features for securing the application in critical
situations (for example in case of a power brown-
out), and reducing the number of external compo-
nents. An overview is shown in Figure 8.
See Section 13 ”ELECTRICAL CHARACTERIS-
TICS” on page 96 for more details.
Main Features
■ Supply Manager with main supply low voltage
detection (LVD)
■ Reset Sequence Manager (RSM)
■ Multi-Oscillator (MO)
– 4 Crystal/Ceramic resonator oscillators
– 1 External RC oscillator
– 1 Internal RC oscillator
■ Clock Security System (CSS)
– Clock Filter
– Backup Safe Oscillator
Figure 8. Clock, Reset and Supply Block Diagram
MCO
CLOCK SECURITY SYSTEM
(CSS)
MAIN CLOCK
CONTROLLER
(MCC)
MULTI-
OSCILLATOR
(MO)
f
f
CPU
OSC2
OSC1
OSC
CLOCK
FILTER
SAFE
OSC
RESET SEQUENCE
MANAGER
FROM
RESET
WATCHDOG
PERIPHERAL
(RSM)
VDD
VSS
LOW VOLTAGE
DETECTOR
(LVD)
LVD
CSS
WDG
RF
CRSR
0
0
0
RF
0
IE
D
CSS INTERRUPT
17/135
ST72104G, ST72215G, ST72216G, ST72254G
6.1 LOW VOLTAGE DETECTOR (LVD)
To allow the integration of power management
features in the application, the Low Voltage Detec-
tor function (LVD) generates a static reset when
In these conditions, secure operation is always en-
sured for the application without the need for ex-
ternal reset hardware.
the V
supply voltage is below a V reference
DD
IT-
During a Low Voltage Detector Reset, the RESET
pin is held low, thus permitting the MCU to reset
other devices.
value. This means that it secures the power-up as
well as the power-down keeping the ST7 in reset.
The V reference value for a voltage drop is lower
IT-
Notes:
than the V reference value for power-on in order
1. The LVD allows the device to be used without
any external RESET circuitry.
IT+
to avoida parasitic reset when the MCU starts run-
ning and sinks current on the supply (hysteresis).
2. Three different reference levels are selectable
through the option byte according to the applica-
tion requirement.
The LVD Reset circuitry generates a reset when
V
is below:
DD
LVD application note
– V when V is rising
IT+
DD
– V when V is falling
The LVD function is illustrated in the Figure 9.
Application software can detect a reset caused by
the LVD by reading the LVDRF bit in the CRSR
register.
IT-
DD
Provided the minimum V
value (guaranteed for
DD
This bit is set by hardware when a LVD reset is
generated and cleared by software (writing zero).
the oscillator frequency) is below V , the MCU
IT-
can only be in two modes:
– under full software control
– in static safe reset
Figure 9. Low Voltage Detector vs Reset
V
DD
V
hyst
V
V
IT+
IT-
RESET
18/135
ST72104G, ST72215G, ST72216G, ST72254G
6.2 RESET SEQUENCE MANAGER (RSM)
6.2.1 Introduction
The 4096 CPU clock cycle delay allows the oscil-
lator to stabilise and ensures that recovery has
taken place from the Reset state.
The reset sequence manager includes three RE-
SET sources as shown in Figure 11:
The RESET vector fetch phase duration is 2 clock
cycles.
■ External RESET source pulse
■ Internal LVD RESET (Low Voltage Detection)
■ Internal WATCHDOG RESET
Figure 10. RESET Sequence Phases
These sources act on the RESET pin and it is al-
ways kept low during the delay phase.
RESET
The RESET service routine vector is fixed at ad-
dresses FFFEh-FFFFh in the ST7 memory map.
INTERNAL RESET
FETCH
DELAY
4096 CLOCK CYCLES
VECTOR
The basic RESET sequence consists of 3 phases
as shown in Figure 10:
■ Delay depending on the RESET source
■ 4096 CPU clock cycle delay
■ RESET vector fetch
Figure 11. Reset Block Diagram
INTERNAL
RESET
V
DD
f
CPU
R
ON
RESET
WATCHDOG RESET
LVD RESET
19/135
ST72104G, ST72215G, ST72216G, ST72254G
RESET SEQUENCE MANAGER (Cont’d)
6.2.2 Asynchronous External RESET pin
6.2.3 Internal Low Voltage Detection RESET
The RESET pin is both an input and an open-drain
Two different RESET sequences caused by the in-
ternal LVD circuitry can be distinguished:
output with integrated R
weak pull-up resistor.
ON
This pull-up has no fixed value but varies in ac-
cordance with the input voltage. It can be pulled
low by external circuitry to reset the device. See
electrical characteristics section for more details.
■ Power-On RESET
■ Voltage Drop RESET
The device RESET pin acts as an output that is
pulled low when V <V
(rising edge) or
DD
IT+
A RESET signal originating from an external
V
<V (falling edge) as shown in Figure 12.
DD
IT-
source must have a duration of at least t
in
h(RSTL)in
The LVD filters spikes on V larger than t
avoid parasitic resets.
to
order to be recognized. This detection is asynchro-
nous and therefore the MCU can enter reset state
even in HALT mode.
DD
g(VDD)
6.2.4 Internal Watchdog RESET
The RESET pin is an asynchronous signal which
plays a major role in EMS performance. In a noisy
environment, it is recommended to follow the
guidelines mentioned in the electrical characteris-
tics section.
The RESET sequence generated by a internal
Watchdog counter overflow is shown in Figure 12.
Starting from the Watchdog counter underflow, the
device RESET pin acts as an output that is pulled
low during at least t
.
w(RSTL)out
Two RESET sequences can be associated with
this RESET source: short or long external reset
pulse (see Figure 12).
Starting from the external RESET pulse recogni-
tion, the device RESET pin acts as an output that
is pulled low during at least t
.
w(RSTL)out
Figure 12. RESET Sequences
V
DD
V
V
IT+
IT-
LVD
RESET
SHORT EXT.
RESET
LONG EXT.
RESET
WATCHDOG
RESET
RUN
RUN
RUN
RUN
RUN
DELAY
DELAY
DELAY
DELAY
t
t
w(RSTL)out
h(RSTL)in
t
w(RSTL)out
t
h(RSTL)in
EXTERNAL
RESET
SOURCE
RESET PIN
WATCHDOG
RESET
WATCHDOG UNDERFLOW
INTERNAL RESET (4096 TCPU
)
FETCH VECTOR
20/135
ST72104G, ST72215G, ST72216G, ST72254G
6.3 MULTI-OSCILLATOR (MO)
The main clock of the ST7 can be generated by
four different source types coming from the multi-
oscillator block:
Table 3. ST7 Clock Sources
Hardware Configuration
■ an external source
■ 4 crystal or ceramic resonator oscillators
■ an external RC oscillator
ST7
OSC1
OSC2
■ an internal high frequency RC oscillator
Each oscillator is optimized for a given frequency
range in terms of consumption and is selectable
through the option byte. The associated hardware
configuration are shown in Table 3. Refer to the
electrical characteristics section for more details.
EXTERNAL
SOURCE
External Clock Source
ST7
OSC1
OSC2
In this external clock mode, a clock signal (square,
sinus or triangle) with ~50% duty cycle has to drive
the OSC1 pin while the OSC2 pin is tied to ground.
Crystal/Ceramic Oscillators
This family of oscillators has the advantage of pro-
ducing a very accurate rate on the main clock of
the ST7. The selection within a list of 4 oscillators
with different frequency ranges has to be done by
option byte in order to reduce consumption. In this
mode of the multi-oscillator, the resonator and the
load capacitors have to be placed as close as pos-
sible to the oscillator pins in order to minimize out-
put distortion and start-up stabilization time. The
loading capacitance values must be adjusted ac-
cording to the selected oscillator.
C
C
L2
L1
LOAD
CAPACITORS
ST7
OSC1
OSC2
R
C
EX
EX
These oscillators are not stopped during the
RESET phase to avoid losing time in the oscillator
start-up phase.
External RC Oscillator
ST7
This oscillator allows a low cost solution for the
main clock of the ST7 using only an external resis-
tor and an external capacitor. The frequency of the
external RC oscillator (in the range of some MHz.)
is fixed by the resistor and the capacitor values.
Consequently in this MO mode, the accuracy of
the clock is directly linked to the accuracy of the
discrete components.
OSC1
OSC2
Internal RC Oscillator
The internal RC oscillator mode is based on the
same principle as the external RC oscillator includ-
ing the resistance and the capacitance of the de-
vice. This mode is the most cost effective one with
the drawback of a lower frequency accuracy. Its
frequency is in the range of several MHz.
In this mode, the two oscillator pins have to be tied
to ground.
21/135
ST72104G, ST72215G, ST72216G, ST72254G
6.4 CLOCK SECURITY SYSTEM (CSS)
The Clock Security System (CSS) protects the
ST7 against main clock problems. To allow the in-
tegration of the security features in the applica-
tions, it is based on a clock filter control and an In-
ternal safe oscillator. The CSS can be enabled or
disabled by option byte.
Limitation detection
The automatic safe oscillator selection is notified
by hardware setting the CSSD bit of the CRSR
register. An interrupt can be generated if the CS-
SIE bit has been previously set.
These two bits are described in the CRSR register
description.
6.4.1 Clock Filter Control
6.4.3 Low Power Modes
The clock filter is based on a clock frequency limi-
tation function.
Mode
WAIT
Description
This filter function is able to detect and filter high
frequency spikes on the ST7 main clock.
No effect on CSS. CSS interrupt cause the
device to exit from Wait mode.
If the oscillator is not working properly (e.g. work-
ing at a harmonic frequency of the resonator), the
current active oscillator clock can be totally fil-
tered, and then no clock signal is available for the
ST7 from this oscillator anymore. If the original
clock source recovers, the filtering is stopped au-
tomatically and the oscillator supplies the ST7
clock.
The CRSR register is frozen. The CSS (in-
cluding the safe oscillator) is disabled until
HALT mode is exited. The previous CSS
configuration resumes when the MCU is
woken up by an interrupt with “exit from
HALT mode” capability or from the counter
reset value when the MCU is woken up by a
RESET.
HALT
6.4.2 Safe Oscillator Control
6.4.4 Interrupts
The safe oscillator of the CSS block is a low fre-
quency back-up clock source (see Figure 13).
The CSS interrupt event generates an interrupt if
the corresponding Enable Control Bit (CSSIE) is
set and the interrupt mask in the CC register is re-
set (RIM instruction).
If the clock signal disappears (due to a broken or
disconnected resonator...) during a safe oscillator
period, the safe oscillator delivers a low frequency
clock signalwhich allows the ST7 to perform some
rescue operations.
Enable Exit
Control from
Exit
from
Halt
Event
Flag
Interrupt Event
Bit
Wait
Automatically, the ST7 clock source switches back
from the safe oscillator if the original clock source
recovers.
CSS event detection
(safe oscillator acti- CSSD CSSIE
vated as main clock)
Yes
No
Figure 13. Clock Filter Function and Safe Oscillator Function
f
/2
OSC
f
CPU
f
/2
OSC
f
SFOSC
f
CPU
22/135
ST72104G, ST72215G, ST72216G, ST72254G
6.5 CLOCK RESET AND SUPPLY REGISTER DESCRIPTION (CRSR)
Read/Write
Bit 1 = CSSD Clock security system detection
This bit indicates that the safe oscillator of the
clock security system block has been selected by
hardware due to a disturbance on the main clock
Reset Value: 000x 000x (XXh)
7
0
signal (f
). It is set by hardware and cleared by
OSC
reading the CRSR registerwhen the original oscil-
lator recovers.
LVD
RF
CSS CSS WDG
0
0
0
0
IE
D
RF
0: Safe oscillator is not active
1: Safe oscillator has been activated
When the CSS is disabled by option byte, the
CSSD bit value is forced to 0.
Bit 7:5 = Reserved, always read as 0.
Bit 4 = LVDRF LVD reset flag
This bit indicates that the last RESET was gener-
ated by the LVD block. It is set by hardware (LVD
reset) and cleared by software (writing zero). See
WDGRF flag description for more details. When
the LVD is disabled by option byte, the LVDRF bit
value is undefined.
Bit 0 = WDGRF Watchdog reset flag
This bit indicates that the last RESET was gener-
ated by the watchdog peripheral. It is set by hard-
ware (Watchdog RESET) and cleared by software
(writing zero) or an LVD RESET (to ensure a sta-
ble cleared state of the WDGRF flag when the
CPU starts).
Combined with the LVDRF flag information, the
flag description is given by the following table.
Bit 3 = Reserved, always read as 0.
RESET Sources
LVDRF WDGRF
Bit 2 = CSSIE Clock security syst interrupt enable
.
External RESET pin
Watchdog
0
0
1
0
1
This bit enables the interrupt when a disturbance
is detected by the clock security system (CSSD bit
set). It is set and cleared by software.
LVD
X
0: Clock security system interrupt disabled
1: Clock security system interrupt enabled
Refer to Table 5, “Interrupt Mapping,” on page 26
for more details on the CSS interrupt vector. When
the CSS is disabled by option byte, the CSSIE bit
has no effect.
Application notes
The LVDRF flag is not cleared when another RE-
SET type occurs (external or watchdog), the
LVDRF flag remains set to keep trace of the origi-
nal failure.
In this case, a watchdog reset can be detected by
software while an external reset can not.
Table 4. Clock, Reset and Supply Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
CRSR
Reset Value
LVDRF
x
CSSIE
0
CSSD
0
WDGRF
x
0025h
0
0
0
0
23/135
ST72104G, ST72215G, ST72216G, ST72254G
6.6 MAIN CLOCK CONTROLLER (MCC)
The Main Clock Controller (MCC) supplies the
clock for the ST7 CPU and its internal peripherals.
It allows SLOW power saving mode to be man-
aged by the application.
The prescaler allows the selection of the main
clock frequency and is controlled by three bits of
the MISCR1: CP1, CP0 and SMS.
The clock-out capability consists of a dedicated
All functions are managed by the Miscellaneous
register 1 (MISCR1).
I/O port pin configurable as an f
clock output to
CPU
drive external devices. It is controlled by the MCO
bit in the MISCR1 register.
The MCC block consists of:
■ A programmable CPU clock prescaler
■ A clock-out signal to supply external devices
See Section 10 ”MISCELLANEOUS REGIS-
TERS” on page 36 for more details.
Figure 14. Main Clock Controller (MCC) Block Diagram
CLOCK TO CAN
PERIPHERAL
PORT
ALTERNATE
FUNCTION
MCO
f
/2
OSC
MISCR1
-
-
MCO
-
-
CP1 CP0 SMS
f
OSC
DIV 2
DIV2, 4, 8, 16
CPU CLOCK
TO CPU AND
PERIPHERALS
f
CPU
24/135
ST72104G, ST72215G, ST72216G, ST72254G
7 INTERRUPTS
The ST7 core may be interrupted by one of two dif-
ferent methods: maskable hardware interrupts as
listed in the Interrupt Mapping Table and a non-
maskable software interrupt (TRAP). The Interrupt
processing flowchart is shown in Figure 15.
The maskable interrupts must be enabled clearing
the I bit in order to be serviced. However, disabled
interrupts may be latched and processed when
they are enabled (see external interrupts subsec-
tion).
It will be serviced according to the flowchart on
Figure 15.
7.2 EXTERNAL INTERRUPTS
External interrupt vectors can be loaded into the
PC register if the corresponding external interrupt
occurred and if the I bit is cleared. These interrupts
allow the processor to leave the Halt low power
mode.
When an interrupt has to be serviced:
The external interrupt polarity is selected through
the miscellaneous register or interrupt register (if
available).
– Normal processing is suspended at the end of
the current instruction execution.
An external interrupt triggered on edge will be
latched and the interrupt request automatically
cleared upon entering the interrupt service routine.
– The PC, X, A and CC registers are saved onto
the stack.
– The I bit of the CC register is set to prevent addi-
tional interrupts.
If several input pins, connected to the same inter-
rupt vector, are configured as interrupts, their sig-
nals are logically ANDed before entering the edge/
level detection block.
– ThePC is then loaded with the interrupt vector of
the interrupt to service and the first instruction of
the interrupt service routine is fetched (refer to
the Interrupt Mapping Table for vector address-
es).
Caution: The type of sensitivity defined in the Mis-
cellaneous or Interrupt register (if available) ap-
plies to the ei source. In case of an ANDed source
(as described on the I/O ports section), a low level
on an I/O pin configured as input with interrupt,
masks the interrupt request even in case of rising-
edge sensitivity.
The interrupt service routine should finish with the
IRET instruction which causes the contents of the
saved registers to be recovered from the stack.
Note: As a consequence of the IRET instruction,
the I bit will be cleared and the main program will
resume.
7.3 PERIPHERAL INTERRUPTS
Priority management
Different peripheral interrupt flags in the status
register are able to cause an interrupt when they
are active if both:
By default, a servicing interrupt cannot be inter-
rupted because the I bit is set by hardware enter-
ing in interrupt routine.
– The I bit of the CC register is cleared.
In the case when severalinterrupts are simultane-
ously pending, an hardware priority defines which
one will be serviced first (see the Interrupt Map-
ping Table).
– The corresponding enable bit is set in the control
register.
If any of these two conditions is false, the interrupt
is latched and thus remains pending.
Interrupts and Low power mode
Clearing an interrupt request is done by:
All interrupts allow the processor to leave the
WAIT low power mode. Only external and specifi-
cally mentioned interrupts allow the processor to
leave the HALT low power mode (refer to the “Exit
from HALT“ column in the Interrupt Mapping Ta-
ble).
– Writing “0” to the corresponding bit in the status
register or
– Access to the status register while the flag is set
followed by a read or write of an associated reg-
ister.
Note: the clearing sequence resets the internal
latch. A pending interrupt (i.e. waiting for being en-
abled) will therefore be lost if the clear sequence is
executed.
7.1 NON MASKABLE SOFTWARE INTERRUPT
This interrupt is entered when the TRAP instruc-
tion is executed regardless of the state of the I bit.
25/135
ST72104G, ST72215G, ST72216G, ST72254G
INTERRUPTS (Cont’d)
Figure 15. Interrupt Processing Flowchart
FROM RESET
N
I BIT SET?
N
Y
INTERRUPT
PENDING?
Y
FETCH NEXT INSTRUCTION
N
IRET?
STACK PC, X, A, CC
SET I BIT
Y
LOAD PC FROM INTERRUPT VECTOR
EXECUTE INSTRUCTION
RESTORE PC, X, A, CC FROM STACK
THIS CLEARS I BIT BY DEFAULT
Table 5. Interrupt Mapping
Exit
from
HALT
Source
Block
Register Priority
Address
Vector
N°
Description
Label
Order
RESET
TRAP
ei0
Reset
yes
no
FFFEh-FFFFh
FFFCh-FFFDh
FFFAh-FFFBh
FFF8h-FFF9h
FFF6h-FFF7h
FFF4h-FFF5h
FFF2h-FFF3h
FFF0h-FFF1h
FFEEh-FFEFh
FFECh-FFEDh
FFEAh-FFEBh
FFE8h-FFE9h
FFE6h-FFE7h
FFE4h-FFE5h
FFE2h-FFE3h
FFE0h-FFE1h
Highest
Priority
Software Interrupt
N/A
1
0
1
External Interrupt Port A7..0 (C5..0 )
yes
1
ei1
External Interrupt Port B7..0 (C5..0 )
2
CSS
Clock Filter Interrupt
SPI Peripheral Interrupts
TIMER A Peripheral Interrupts
Not used
CRSR
SPISR
TASR
3
SPI
no
4
TIMER A
5
6
TIMER B
TIMER B Peripheral Interrupts
Not used
TBSR
no
no
7
8
Not used
9
Not used
10
11
12
13
Not used
I C
I C Peripheral Interrupt
Not Used
I2CSRx
Lowest
Priority
Not Used
Note
1. Configurable by option byte.
26/135
ST72104G, ST72215G, ST72216G, ST72254G
8 POWER SAVING MODES
8.1 INTRODUCTION
8.2 SLOW MODE
To give a large measure of flexibility to the applica-
tion in terms of power consumption, three main
power saving modes are implemented in the ST7
(see Figure 16).
This mode has two targets:
– Toreduce powerconsumption by decreasingthe
internal clock in the device,
– To adapt the internal clock frequency (f
the available supply voltage.
) to
CPU
After a RESET the normal operating mode is se-
lected by default (RUN mode). This mode drives
the device (CPU and embedded peripherals) by
means of a master clock which is based on the
SLOW mode is controlled by three bits in the
MISCR1 register: the SMS bit which enables or
disables Slow mode and two CPx bits which select
main oscillator frequency divided by 2 (f
).
CPU
the internal slow frequency (f
).
CPU
From Run mode, the different power saving
modes may be selected by setting the relevant
register bits or by calling the specific ST7 software
instruction whose action depends on the the oscil-
lator status.
In this mode, the oscillator frequency can be divid-
ed by 4, 8, 16 or 32 instead of 2 in normal operat-
ing mode. The CPU and peripherals are clocked at
this lower frequency.
Note: SLOW-WAIT mode is activated when enter-
ring the WAIT mode while the device is already in
SLOW mode.
Figure 16. Power Saving Mode Transitions
High
RUN
Figure 17. SLOW Mode Clock Transitions
f
/4
f
/8
f
/2
OSC
OSC
OSC
f
f
CPU
SLOW
WAIT
/2
OSC
00
01
CP1:0
SMS
SLOW WAIT
HALT
NORMAL RUN MODE
REQUEST
NEW SLOW
FREQUENCY
REQUEST
Low
POWER CONSUMPTION
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ST72104G, ST72215G, ST72216G, ST72254G
POWER SAVING MODES (Cont’d)
8.3 WAIT MODE
Figure 18. WAIT Mode Flow-chart
WAIT mode places the MCU in a low power con-
sumption mode by stopping the CPU.
This power saving mode is selected by calling the
“WFI” ST7 software instruction.
OSCILLATOR
PERIPHERALS
CPU
I BIT
ON
ON
OFF
0
WFI INSTRUCTION
All peripherals remain active. During WAIT mode,
the I bit of the CC register is forced to 0, to enable
all interrupts. All other registers and memory re-
main unchanged. The MCU remains in WAIT
mode until an interrupt or Reset occurs, whereup-
on the Program Counter branches to the starting
address of the interrupt or Reset service routine.
The MCU will remain in WAIT mode until a Reset
or an Interrupt occurs, causing it to wake up.
N
RESET
Y
N
INTERRUPT
Y
OSCILLATOR
PERIPHERALS
CPU
ON
OFF
ON
1
Refer to Figure 18.
I BIT
4096 CPU CLOCK CYCLE
DELAY
OSCILLATOR
PERIPHERALS
CPU
ON
ON
ON
1)
I BIT
X
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Note:
1. Before servicing an interrupt, the CC register is
pushed on the stack. The I bit of the CC register is
set during the interrupt routine and cleared when
the CC register is popped.
28/135
ST72104G, ST72215G, ST72216G, ST72254G
POWER SAVING MODES (Cont’d)
8.4 HALT MODE
Figure 20. HALT Mode Flow-chart
The HALT mode is the lowest power consumption
mode of the MCU. It is entered by executing the
ST7 HALT instruction (see Figure 20).
HALT INSTRUCTION
ENABLE
The MCU can exit HALT mode on reception of ei-
ther a specific interrupt (see Table 5, “Interrupt
Mapping,” on page 26) or a RESET. When exiting
HALT mode by means of a RESET or an interrupt,
the oscillator is immediately turned on and the
4096 CPU cycle delay is used to stabilize the os-
cillator. After the start up delay, the CPU resumes
operation by servicing the interrupt or by fetching
the reset vector which woke it up (see Figure 19).
When entering HALT mode, the I bit in the CC reg-
ister is forced to 0 to enable interrupts. Therefore,
if an interrupt is pending, the MCU wakes immedi-
ately.
WATCHDOG
0
DISABLE
WDGHALT 1)
1
WATCHDOG
RESET
OSCILLATOR
OFF
PERIPHERALS 2)
OFF
OFF
0
CPU
I BIT
N
RESET
In the HALT mode the main oscillator is turned off
causing all internal processing to be stopped, in-
cluding the operation of the on-chip peripherals.
All peripherals are not clocked except the ones
which get their clock supply from another clock
generator (such as an external or auxiliary oscilla-
tor).
Y
N
INTERRUPT 3)
OSCILLATOR
PERIPHERALS
CPU
Y
ON
OFF
ON
1
The compatibility of Watchdog operation with
HALT mode is configured by the “WDGHALT” op-
tion bit of the option byte. The HALT instruction
when executed while the Watchdog system is en-
abled, can generate a Watchdog RESET (see
Section 15.1 ”OPTION BYTES” on page 129 for
more details).
I BIT
4096 CPU CLOCK CYCLE
DELAY
OSCILLATOR
PERIPHERALS
CPU
ON
ON
ON
X 4)
Figure 19. HALT Mode Timing Overview
I BIT
4096 CPU CYCLE
RUN
HALT
RUN
DELAY
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Notes:
HALT
INSTRUCTION
1. WDGHALT is an option bit. See option byte sec-
tion for more details.
2. Peripheral clocked with an external clock source
can still be active.
RESET
OR
INTERRUPT
FETCH
VECTOR
3. Only some specific interrupts can exit the MCU
from HALT mode (such as external interrupt). Re-
fer to Table 5, “Interrupt Mapping,” on page 26 for
more details.
4. Before servicing an interrupt, the CC register is
pushed on the stack. The I bit of the CC register is
set during the interrupt routine and cleared when
the CC register is popped.
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ST72104G, ST72215G, ST72216G, ST72254G
9 I/O PORTS
9.1 INTRODUCTION
programmable using the sensitivity bits in the Mis-
cellaneous register.
The I/O ports offer different functional modes:
– transfer of data through digitalinputs and outputs
Each external interrupt vector is linked to a dedi-
cated group of I/O port pins (see pinout description
and interrupt section). If several input pins are se-
lected simultaneously as interrupt source, these
are logically ANDed. For this reason if one of the
interrupt pins is tied low, it masks the other ones.
and for specific pins:
– external interrupt generation
– alternate signal input/output for the on-chip pe-
ripherals.
An I/O port contains up to 8 pins. Each pin can be
programmed independently as digital input (with or
without interrupt generation) or digital output.
In case of a floating input with interrupt configura-
tion, special care must be taken when changing
the configuration (see Figure 22).
The external interrupts are hardware interrupts,
which means that the request latch (not accessible
directly by the application) is automatically cleared
when the corresponding interrupt vector is
fetched. To clear an unwanted pending interrupt
by software, the sensitivity bits in the Miscellane-
ous register must be modified.
9.2 FUNCTIONAL DESCRIPTION
Each port has 2 main registers:
– Data Register (DR)
– Data Direction Register (DDR)
and one optional register:
– Option Register (OR)
9.2.2 Output Modes
The output configuration is selected by setting the
corresponding DDR register bit. In this case, writ-
ing the DR register applies this digital value to the
I/O pin through the latch. Then reading the DR reg-
ister returns the previously stored value.
Each I/O pin may be programmed using the corre-
sponding register bits in the DDR and OR regis-
ters: bit X corresponding to pin X of the port. The
same correspondence is used for the DR register.
The following description takes into account the
OR register, (for specific ports which do not pro-
vide this register refer to the I/O Port Implementa-
tion section). The generic I/O block diagram is
shown in Figure 21
Two different output modes can be selected by
software through the OR register: Output push-pull
and open-drain.
DR register value and output pin status:
9.2.1 Input Modes
DR
0
Push-pull
Open-drain
Vss
V
The input configuration is selected by clearing the
corresponding DDR register bit.
SS
1
V
Floating
DD
In this case, reading the DR register returns the
digital value applied to the external I/O pin.
9.2.3 Alternate Functions
When an on-chip peripheral is configured to use a
pin, the alternate function is automatically select-
ed. This alternate function takes priority over the
standard I/O programming.
Different input modes can be selected by software
through the OR register.
Notes:
1. Writing the DR register modifies the latch value
but does not affect the pin status.
When the signal is coming from an on-chip periph-
eral, the I/O pin is automatically configured in out-
put mode (push-pull or open drain according to the
peripheral).
2. When switching from input to output mode, the
DR register has to be written first to drive the cor-
rect level on the pin as soon as the port is config-
ured as an output.
When the signal is going to an on-chip peripheral,
the I/O pin must be configured in input mode. In
this case, the pin state is also digitally readable by
addressing the DR register.
External interrupt function
When an I/O is configured as Input with Interrupt,
an event on this I/O can generate anexternal inter-
rupt request to the CPU.
Note: Input pull-up configuration can cause unex-
pected value at the input of the alternate peripheral
input. When an on-chip peripheral use a pin as in-
put and output, this pin has to be configured in in-
put floating mode.
Each pin can independently generate an interrupt
request. The interrupt sensitivity is independently
30/135
ST72104G, ST72215G, ST72216G, ST72254G
I/O PORTS (Cont’d)
Figure 21. I/O Port General Block Diagram
ALTERNATE
OUTPUT
1
0
REGISTER
ACCESS
P-BUFFER
(see table below)
V
DD
ALTERNATE
ENABLE
PULL-UP
(see table below)
DR
V
DD
DDR
PULL-UP
CONDITION
PAD
OR
If implemented
OR SEL
DDR SEL
DR SEL
N-BUFFER
DIODES
(see table below)
ANALOG
INPUT
CMOS
SCHMITT
TRIGGER
1
0
ALTERNATE
INPUT
EXTERNAL
INTERRUPT
SOURCE (ei )
FROM
OTHER
BITS
x
POLARITY
SELECTION
Table 6. I/O Port Mode Options
Configuration Mode
Diodes
Pull-Up
P-Buffer
to V
to V
SS
DD
Floating with/without Interrupt
Pull-up with/without Interrupt
Push-pull
Off
On
Input
Off
On
On
Off
NI
On
Off
NI
Output
Open Drain (logic level)
True Open Drain
NI (see note)
Legend: NI - not implemented
Off - implemented not activated
On - implemented and activated
Note: The diode to V
is not implemented in the
DD
true open drain pads. A local protection between
the pad and V is implemented to protect the de-
SS
vice against positive stress.
31/135
ST72104G, ST72215G, ST72216G, ST72254G
I/O PORTS (Cont’d)
Table 7. I/O Port Configurations
Hardware Configuration
DR REGISTER ACCESS
NOT IMPLEMENTED IN
TRUE OPEN DRAIN
I/O PORTS
V
DD
PULL-UP
CONDITION
R
PU
DR
REGISTER
W
R
DATABUS
PAD
ALTERNATE INPUT
FROM
OTHER
PINS
EXTERNAL INTERRUPT
SOURCE (ei )
x
INTERRUPT
CONDITION
POLARITY
SELECTION
ANALOG INPUT
NOT IMPLEMENTED IN
TRUE OPEN DRAIN
I/O PORTS
DR REGISTER ACCESS
V
DD
R
PU
R/W
DR
REGISTER
DATA BUS
PAD
ALTERNATE
ENABLE
ALTERNATE
OUTPUT
NOT IMPLEMENTED IN
TRUE OPEN DRAIN
I/O PORTS
DR REGISTER ACCESS
V
DD
R
PU
R/W
DR
REGISTER
DATA BUS
PAD
ALTERNATE
ENABLE
ALTERNATE
OUTPUT
Notes:
1. When the I/O port is in input configuration and the associated alternate function is enabled as an output,
reading the DR register will read the alternate function output status.
2. When the I/O port is in output configuration and the associated alternate function is enabled as an input,
the alternate function reads the pin status given by the DR register content.
32/135
ST72104G, ST72215G, ST72216G, ST72254G
Figure 22. Interrupt I/O Port State Transitions
I/O PORTS (Cont’d)
CAUTION: The alternate function must not be ac-
tivated as long as the pin is configured as input
with interrupt, in order to avoid generating spurious
interrupts.
01
00
10
11
Analog alternate function
INPUT
floating/pull-up
interrupt
INPUT
floating
(reset state)
OUTPUT
open-drain
OUTPUT
push-pull
When the pin is used as an ADC input, the I/O
must be configured as floating input. The analog
multiplexer (controlled by the ADC registers)
switches the analog voltage present on the select-
ed pin to the common analog rail which is connect-
ed to the ADC input.
= DDR, OR
XX
The I/O port register configurations are summa-
rized as follows.
It is recommended not to change the voltage level
or loading on any port pin while conversion is in
progress. Furthermore it is recommended not to
have clocking pins located close to a selected an-
alog pin.
Interrupt Ports
PA7, PA5, PA3:0, PB7:0, PC5:0 (with pull-up)
MODE
DDR
OR
WARNING: The analog input voltage level must
be within the limits stated in the absolute maxi-
mum ratings.
floating input
0
0
1
1
0
1
0
1
pull-up interrupt input
open drain output
push-pull output
9.3 I/O PORT IMPLEMENTATION
The hardware implementation on each I/O port de-
pends onthe settings in the DDR and OR registers
and specificfeature of the I/O port such as ADC In-
put or true open drain.
True Open Drain Interrupt Ports
PA6, PA4 (without pull-up)
MODE
DDR
OR
Switching these I/O ports from one state to anoth-
er should be done in a sequence that prevents un-
wanted side effects. Recommended safe transi-
tions are illustrated in Figure 22 Other transitions
are potentially risky and should be avoided, since
they are likely to present unwanted side-effects
such as spurious interrupt generation.
floating input
0
0
1
0
1
floating interrupt input
open drain (high sink ports)
X
Table 8. Port Configuration
Input (DDR = 0)
Output (DDR = 1)
Port
Pin name
OR = 0
OR = 1
OR = 0
OR = 1
High-Sink
PA7
floating
floating
floating
floating
floating
floating
floating
pull-up interrupt
floating interrupt
pull-up interrupt
floating interrupt
pull-up interrupt
pull-up interrupt
pull-up interrupt
open drain
push-pull
PA6
true open-drain
Port A
PA5
open drain
push-pull
Yes
PA4
true open-drain
PA3:0
PB7:0
PC7:0
open drain
open drain
open drain
push-pull
push-pull
push-pull
Port B
Port C
No
33/135
ST72104G, ST72215G, ST72216G, ST72254G
I/O PORTS (Cont’d)
9.4 LOW POWER MODES
DATA DIRECTION REGISTER (DDR)
Port x Data Direction Register
PxDDR with x = A, B or C.
Mode
WAIT
HALT
Description
No effect on I/O ports. External interrupts
cause the device to exit from WAIT mode.
Read/Write
Reset Value: 0000 0000 (00h)
No effect on I/O ports. External interrupts
cause the device to exit from HALT mode.
7
0
9.5 INTERRUPTS
DD7
DD6
DD5
DD4
DD3
DD2
DD1
DD0
The external interrupt event generates an interrupt
if the corresponding configuration is selected with
DDR and OR registers and the I-bit in the CC reg-
ister is reset (RIM instruction).
Bit 7:0 = DD[7:0] Data direction register 8 bits.
The DDR register gives the input/output direction
configuration of the pins. Each bit is set and
cleared by software.
Enable Exit
Control from
Exit
from
Halt
Event
Flag
Interrupt Event
0: Input mode
1: Output mode
Bit
Wait
External interrupt on
selected external
event
DDRx
ORx
OPTION REGISTER (OR)
-
Yes
Yes
Port x Option Register
PxOR with x = A, B or C.
9.6 REGISTER DESCRIPTION
DATA REGISTER (DR)
Read/Write
Reset Value: 0000 0000 (00h)
Port x Data Register
PxDR with x = A, B or C.
7
0
Read/Write
O7
O6
O5
O4
O3
O2
O1
O0
Reset Value: 0000 0000 (00h)
Bit 7:0 = O[7:0] Option register 8 bits.
7
0
For specific I/O pins, this register is not implement-
ed. In this case the DDR register is enough to se-
lect the I/O pin configuration.
D7
D6
D5
D4
D3
D2
D1
D0
The OR register allows to distinguish: in input
mode if the pull-up with interrupt capability or the
basic pull-up configuration is selected, in output
mode if the push-pull or open drain configuration is
selected.
Bit 7:0 = D[7:0] Data register 8 bits.
The DR register has a specific behaviour accord-
ing to the selected input/output configuration. Writ-
ing the DR register is always taken into account
even if the pin is configured as an input; this allows
always having the expected level on the pin when
toggling to output mode. Reading the DR register
returns either the DR register latch content (pin
configured as output) or the digital value applied to
the I/O pin (pin configured as input).
Each bit is set and cleared by software.
Input mode:
0: Floating input
1: Pull-up input with or without interrupt
Output mode:
0: Output open drain (with P-Buffer unactivated)
1: Output push-pull (when available)
34/135
ST72104G, ST72215G, ST72216G, ST72254G
I/O PORTS (Cont’d)
Table 9. I/O Port Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
Reset Value
of all I/O port registers
0
0
0
0
0
0
0
0
0000h
0001h
0002h
0004h
0005h
0006h
0008h
0009h
000Ah
PCDR
PCDDR
PCOR
PBDR
PBDDR
PBOR
PADR
PADDR
PAOR
MSB
MSB
MSB
LSB
LSB
LSB
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ST72104G, ST72215G, ST72216G, ST72254G
10 MISCELLANEOUS REGISTERS
The miscellaneous registers allow control over
several different features such as the external in-
terrupts or the I/O alternate functions.
Figure 23. Ext. Interrupt Sensitivity (EXTIT=0)
MISCR1
IS00 IS01
PA7
ei0
10.1 I/O PORT INTERRUPT SENSITIVITY
INTERRUPT
SOURCE
The external interrupt sensitivity is controlled by
the ISxx bits of the Miscellaneous register and the
OPTION BYTE. This control allows having two ful-
ly independent external interrupt source sensitivi-
ties with configurable sources (using EXTIT option
bit) as shown in Figure 23 and Figure 24.
SENSITIVITY
CONTROL
PA0
PC5
PC0
MISCR1
Each external interrupt source can be generated
on four different events on the pin:
IS10
IS11
ei1
PB7
PB0
INTERRUPT
SOURCE
■ Falling edge
■ Rising edge
■ Falling and rising edge
■ Falling edge and low level
SENSITIVITY
CONTROL
To guarantee correct functionality, the sensitivity
bits in the MISCR1 register must be modified only
when the I bit of the CC register is set to 1 (inter-
rupt masked). See I/O port register and Miscella-
neous register descriptions for more details on the
programming.
Figure 24. Ext. Interrupt Sensitivity (EXTIT=1)
MISCR1
IS00
IS01
ei0
PA7
INTERRUPT
SOURCE
SENSITIVITY
CONTROL
10.2 I/O PORT ALTERNATE FUNCTIONS
PA0
PB7
The MISCR registers manage four I/O port miscel-
laneous alternate functions:
MISCR1
■ Main clock signal (f
) output on PC2
CPU
IS10
IS11
ei1
■ SPI pin configuration:
INTERRUPT
SOURCE
– SS pin internal control to use the PB7 I/O port
function while the SPI is active.
SENSITIVITY
CONTROL
PB0
PC5
– Master output capability on MOSI pin (PB4)
deactivated while the SPI is active.
– Slave output capability on MISO pin (PB5) de-
activated while the SPI is active.
PC0
These functions are described in detail in the Sec-
tion 10.3 ”MISCELLANEOUS REGISTER DE-
SCRIPTION” on page 37.
36/135
ST72104G, ST72215G, ST72216G, ST72254G
MISCELLANEOUS REGISTERS (Cont’d)
10.3 MISCELLANEOUS REGISTER DESCRIPTION
MISCELLANEOUS REGISTER 1 (MISCR1)
Read/Write
Bit 2:1 = CP[1:0] CPU clock prescaler
These bits select the CPU clock prescaler which is
applied in the different slow modes. Their action is
conditioned by the setting of the SMS bit. These
two bits are set and cleared by software
Reset Value: 0000 0000 (00h)
7
0
f
in SLOW mode
CP1
CP0
CPU
IS11 IS10 MCO IS01 IS00 CP1 CP0 SMS
f
f
/ 4
/ 8
0
1
0
1
0
0
1
1
OSC
OSC
f
/ 16
/ 32
OSC
Bit 7:6 = IS1[1:0] ei1 sensitivity
f
OSC
The interrupt sensitivity, defined using the IS1[1:0]
bits, is applied to the ei1 external interrupts. These
two bits can be written only when the I bit of the CC
register is set to 1 (interrupt masked).
Bit 0 = SMS Slow mode select
This bit is set and cleared by software.
0: Normal mode. f = fOSC / 2
ei1: Port B (C optional)
CPU
1: Slow mode. f
is given by CP1, CP0
CPU
External Interrupt Sensitivity
IS11 IS10
See low power consumption mode and MCC
chapters for more details.
Falling edge & low level
Rising edge only
0
0
1
1
0
1
0
1
Falling edge only
Rising and falling edge
Bit 5 = MCO Main clock out selection
This bit enables the MCO alternate function on the
PC2 I/O port. It is set and cleared by software.
0: MCO alternate function disabled (I/O pin free for
general-purpose I/O)
1: MCO alternate function enabled (f
port)
on I/O
CPU
Bit 4:3 = IS0[1:0] ei0 sensitivity
The interrupt sensitivity, defined using the IS0[1:0]
bits, is applied to the ei0 external interrupts. These
two bits can be written only when the I bit of the CC
register is set to 1 (interrupt masked).
ei0: Port A (C optional)
External Interrupt Sensitivity
IS01 IS00
Falling edge & low level
Rising edge only
0
0
1
1
0
1
0
1
Falling edge only
Rising and falling edge
37/135
ST72104G, ST72215G, ST72216G, ST72254G
MISCELLANEOUS REGISTERS (Cont’d)
MISCELLANEOUS REGISTER 2 (MISCR2)
Read/Write
Reset Value: 0000 0000 (00h)
7
0
0
0
0
0
MOD SOD SSM SSI
Bit 7:4 = Reserved always read as 0
Bit 5 = MOD SPI Master Output Disable
This bit is set and cleared by software. When set, it
disables the SPI Master (MOSI) output signal.
0: SPI Master Output enabled.
1: SPI Master Output disabled.
Bit 4 = SOD SPI Slave Output Disable
This bit is set and cleared by software. When set it
disable the SPI Slave (MISO) output signal.
0: SPI Slave Output enabled.
1: SPI Slave Output disabled.
Bit 1 = SSM SS mode selection
This bit is set and cleared by software.
0: Normal mode - the level of the SPI SS signal is
input from the external SS pin.
1: I/O mode, the level of the SPI SS signal is read
from the SSI bit.
Bit 0 = SSI SS internal mode
This bit replaces the SS pin of the SPI when the
SSM bit is set to 1. (see SPI description). It is set
and cleared by software.
Table 10. Miscellaneous Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
MISCR1
Reset Value
IS11
0
IS10
0
MCO
0
IS01
0
IS00
0
CP1
0
CP0
0
SMS
0
0020h
0040h
MISCR2
Reset Value
MOD
0
SOD
0
SSM
0
SSI
0
0
0
0
0
38/135
ST72104G, ST72215G, ST72216G, ST72254G
11 ON-CHIP PERIPHERALS
11.1 WATCHDOG TIMER (WDG)
11.1.1 Introduction
cles, and the length of the timeout period can be
programmed by the user in 64 increments.
The Watchdog timer is used to detect the occur-
rence of a software fault, usually generated by ex-
ternal interference or by unforeseen logical condi-
tions, which causes the application program to
abandon its normal sequence. The Watchdog cir-
cuit generates an MCU reset on expiry of a pro-
grammed time period, unless the program refresh-
es the counter’s contents before the T6 bit be-
comes cleared.
If the watchdog is activated (the WDGA bit is set)
and when the 7-bit timer (bits T6:T0) rolls over
from 40h to 3Fh (T6 becomes cleared), it initiates
a reset cycle pulling low the reset pin for typically
500ns.
The application program must write in the CR reg-
ister at regular intervals during normal operation to
prevent an MCU reset. The value to be stored in
the CR register must be between FFh and C0h
(see Table 11 . Watchdog Timing (fCPU = 8
MHz)):
11.1.2 Main Features
■ Programmable timer (64 increments of 12288
CPU cycles)
– The WDGA bit is set (watchdog enabled)
■ Programmable reset
– The T6 bit is set to prevent generating an imme-
diate reset
■ Reset (if watchdog activated) when the T6 bit
reaches zero
■ Optional
reset
on
HALT
instruction
– The T5:T0 bits contain the number of increments
which represents the time delay before the
watchdog produces a reset.
(configurable by option byte)
■ Hardware Watchdog selectable by option byte.
11.1.3 Functional Description
The counter value stored in the CR register (bits
T6:T0), is decremented every 12,288 machine cy-
Figure 25. Watchdog Block Diagram
RESET
WATCHDOG CONTROL REGISTER (CR)
T5 T0
WDGA T6
T4
T1
T2
T3
7-BIT DOWNCOUNTER
CLOCK DIVIDER
f
CPU
÷12288
39/135
ST72104G, ST72215G, ST72216G, ST72254G
WATCHDOG TIMER (Cont’d)
Table 11. Watchdog Timing (f
= 8 MHz)
reset immediately after waking up the microcon-
troller.
CPU
CR Register
initial value
WDG timeout period
(ms)
– When using an external interrupt to wake up the
microcontroller, reinitialize the corresponding I/O
as “Input Pull-up with Interrupt” before executing
the HALT instruction. The main reason for this is
that the I/O may be wrongly configured due to ex-
ternal interference or by an unforeseen logical
condition.
Max
Min
FFh
C0h
98.304
1.536
Notes: Following a reset, the watchdog is disa-
bled. Once activated it cannot be disabled, except
by a reset.
– For the same reason, reinitialize the level sensi-
tiveness of each external interrupt as a precau-
tionary measure.
The T6 bit can be used to generate a software re-
set (the WDGA bit is set and the T6 bit is cleared).
– The opcode for the HALT instruction is 0x8E. To
avoid an unexpected HALT instruction due to a
program counter failure, it is advised to clear all
occurrences of the data value 0x8E from memo-
ry. For example, avoid defining a constant in
ROM with the value 0x8E.
11.1.4 Hardware Watchdog Option
If Hardware Watchdog is selected by option byte,
the watchdog is always active and the WDGA bit in
the CR is not used.
– As the HALT instruction clears the I bit in the CC
register to allow interrupts, the user may choose
to clear all pending interrupt bits before execut-
ing the HALT instruction. This avoids entering
other peripheral interrupt routines afterexecuting
the external interrupt routine corresponding to
the wake-up event (reset or external interrupt).
Refer to the device-specific Option Byte descrip-
tion.
11.1.5 Low Power Modes
WAIT Instruction
No effect on Watchdog.
HALT Instruction
11.1.6 Interrupts
If the Watchdog reset on HALT option is selected
by option byte, a HALT instruction causes an im-
mediate reset generation if the Watchdog is acti-
vated (WDGA bit is set).
None.
11.1.7 Register Description
CONTROL REGISTER (CR)
Read/Write
11.1.5.1 Using Halt Modewith the WDG (option)
If the Watchdog reset on HALT option is not se-
lected by option byte, the Halt mode can be used
when the watchdog is enabled.
Reset Value: 0111 1111 (7Fh)
7
0
In this case, the HALT instruction stops the oscilla-
tor. When the oscillator is stopped, the WDG stops
counting and is no longer able to generate a reset
until the microcontroller receives an external inter-
rupt or a reset.
WDGA T6
T5
T4
T3
T2
T1
T0
Bit 7 = WDGA Activation bit.
This bit is set by software and only cleared by
hardware after a reset. When WDGA = 1, the
watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled
If an external interrupt is received, the WDG re-
starts counting after 4096 CPU clocks. If a reset is
generated, the WDG is disabled (reset state).
Recommendations
– Make sure that an external event is available to
wake up the microcontroller from Halt mode.
Bit 6:0 = T[6:0] 7-bit timer (MSB to LSB).
These bits contain the decremented value. A reset
is produced when it rolls over from 40h to 3Fh (T6
becomes cleared).
– Before executing the HALT instruction, refresh
the WDG counter, to avoidan unexpected WDG
40/135
ST72104G, ST72215G, ST72216G, ST72254G
WATCHDOG TIMER (Cond’t)
Table 12. Watchdog Timer Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
WDGCR
Reset Value
WDGA
0
T6
1
T5
1
T4
1
T3
1
T2
1
T1
1
T0
1
0024h
41/135
ST72104G, ST72215G, ST72216G, ST72254G
11.2 16-BIT TIMER
11.2.1 Introduction
11.2.3 Functional Description
11.2.3.1 Counter
The timer consists of a 16-bit free-running counter
driven by a programmable prescaler.
The main block of the Programmable Timer is a
16-bit free running upcounter and its associated
16-bit registers. The 16-bit registers are made up
of two 8-bit registers called high & low.
It may be used for a variety of purposes, including
pulse length measurement of up to two input sig-
nals (input capture) or generation of up to two out-
put waveforms (output compare and PWM).
Counter Register (CR):
Pulse lengths and waveform periods can be mod-
ulated from a few microseconds to several milli-
seconds using the timer prescaler and the CPU
clock prescaler.
– Counter High Register (CHR) is the most sig-
nificant byte (MS Byte).
– Counter Low Register (CLR) is the least sig-
nificant byte (LS Byte).
Some ST7 devices have two on-chip 16-bit timers.
They are completely independent, and do not
share any resources. They are synchronized after
a MCU reset as long as the timer clock frequen-
cies are not modified.
Alternate Counter Register (ACR)
– Alternate Counter High Register (ACHR) is the
most significant byte (MS Byte).
– Alternate Counter Low Register (ACLR) is the
least significant byte (LS Byte).
This description covers one or two 16-bit timers. In
ST7 devices with two timers, register names are
prefixed with TA (Timer A) or TB (Timer B).
These two read-only 16-bit registers contain the
same value but with the difference that reading the
ACLR register does not clear the TOF bit (Timer
overflow flag), located in the Status register, (SR),
(see note at the end of paragraph titled 16-bit read
sequence).
11.2.2 Main Features
■ Programmable prescaler:fCPU dividedby2, 4or8.
■ Overflow status flag and maskable interrupt
■ External clock input (must be at least 4 times
slower thantheCPUclock speed)withthechoice
of active edge
■ Output compare functions with
– 2 dedicated 16-bit registers
– 2 dedicated programmable signals
– 2 dedicated status flags
Writing in the CLR register or ACLR register resets
the free running counter to the FFFCh value.
Both counters have a reset value of FFFCh (this is
the only value which is reloaded in the 16-bit tim-
er). The reset value of both counters is also
FFFCh in One Pulse mode and PWM mode.
The timer clock depends on the clock control bits
of the CR2 register, as illustrated in Table 13 Clock
Control Bits. The value in the counter register re-
peats every 131.072, 262.144 or 524.288 CPU
clock cycles depending on the CC[1:0] bits.
– 1 dedicated maskable interrupt
■ Input capture functions with
– 2 dedicated 16-bit registers
– 2 dedicated active edge selection signals
– 2 dedicated status flags
The timer frequency can be f
or an external frequency.
/2, f
/4, f
/8
CPU
CPU
CPU
– 1 dedicated maskable interrupt
■ Pulse width modulation mode (PWM)
■ One pulse mode
■ 5 alternatefunctionson I/O ports (ICAP1,ICAP2,
OCMP1, OCMP2, EXTCLK)*
The Block Diagram is shown in Figure 26.
*Note: Some timer pins may not available (not
bonded) in some ST7 devices. Refer to the device
pin out description.
When reading an input signal on a non-bonded
pin, the value will always be ‘1’.
42/135
ST72104G, ST72215G, ST72216G, ST72254G
16-BIT TIMER (Cont’d)
Figure 26. Timer Block Diagram
ST7 INTERNAL BUS
f
CPU
MCU-PERIPHERAL INTERFACE
8 low
8-bit
8 high
8
8
8
8
8
8
8
8
buffer
EXEDG
h
w
h
w
h
w
h
low
16
INPUT
CAPTURE
REGISTER
INPUT
CAPTURE
REGISTER
OUTPUT
COMPARE
REGISTER
OUTPUT
COMPARE
REGISTER
1
1/2
1/4
1/8
COUNTER
REGISTER
1
2
2
ALTERNATE
COUNTER
REGISTER
EXTCLK
pin
16
16
16
CC[1:0]
TIMER INTERNAL BUS
16 16
OVERFLOW
DETECT
EDGE DETECT
CIRCUIT1
OUTPUT COMPARE
CIRCUIT
ICAP1
pin
CIRCUIT
6
EDGE DETECT
CIRCUIT2
ICAP2
pin
OCMP1
pin
LATCH1
LATCH2
ICF1 OCF1 TOF ICF2 OCF2
0
0
0
OCMP2
pin
(Status Register) SR
ICIE OCIE TOIE FOLV2 FOLV1OLVL2 IEDG1 OLVL1
OC1E
OPM PWM CC1 CC0 IEDG2 EXEDG
OC2E
(Control Register 1) CR1
(Control Register 2) CR2
(See note)
Note: If IC, OC and TO interrupt requests have separate vectors
then the last OR is not present (See device Interrupt Vector Table)
TIMER INTERRUPT
43/135
ST72104G, ST72215G, ST72216G, ST72254G
16-BIT TIMER (Cont’d)
16-bit read sequence: (from either the Counter
Register or the Alternate Counter Register).
Clearing the overflow interrupt request is done in
two steps:
1.Reading the SR register while the TOF bit is set.
2.An access (read or write) to the CLR register.
Beginning of the sequence
Read
LS Byte
Notes: The TOF bit is not cleared by accesses to
ACLR register. The advantage of accessing the
ACLR register rather than the CLR register is that
it allows simultaneous use of the overflow function
and reading the free running counter at random
times (for example, to measure elapsed time) with-
out the risk of clearing the TOF bit erroneously.
MS Byte
At t0
is buffered
Other
instructions
Returns the buffered
LS Byte value at t0
Read
LS Byte
At t0 +∆t
The timer is not affected by WAIT mode.
In HALT mode, the counter stops counting until the
mode is exited. Counting then resumes from the
previous count (MCU awakened by an interrupt) or
from the reset count (MCU awakened by a Reset).
Sequence completed
The user must read the MS Byte first, then the LS
Byte value is buffered automatically.
This buffered value remains unchanged until the
16-bit read sequence is completed, even if the
user reads the MS Byte several times.
11.2.3.2 External Clock
The external clock (where available) is selected if
CC0=1 and CC1=1 in CR2 register.
After a complete reading sequence, if only the
CLR register or ACLR register are read, they re-
turn the LS Byte of the count value at the time of
the read.
The status of the EXEDG bit in the CR2 register
determines the type of level transition on the exter-
nal clock pin EXTCLK that will trigger the free run-
ning counter.
Whatever the timer mode used (input capture, out-
put compare, one pulse mode or PWM mode) an
overflow occurs when the counter rolls over from
FFFFh to 0000h then:
The counter is synchronised with the falling edge
of the internal CPU clock.
A minimum of four falling edges of the CPU clock
must occur between two consecutive active edges
of the external clock; thus the external clock fre-
quency must be less than a quarter of the CPU
clock frequency.
– The TOF bit of the SR register is set.
– A timer interrupt is generated if:
– TOIE bit of the CR1 register is set and
– I bit of the CC register is cleared.
If one of these conditions is false, the interrupt re-
mains pending to be issued as soon as they are
both true.
44/135
ST72104G, ST72215G, ST72216G, ST72254G
16-BIT TIMER (Cont’d)
Figure 27. Counter Timing Diagram, internal clock divided by 2
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
FFFD FFFE FFFF 0000 0001 0002 0003
COUNTER REGISTER
TIMER OVERFLOW FLAG (TOF)
Figure 28. Counter Timing Diagram, internal clock divided by 4
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
FFFC
FFFD
0000
0001
COUNTER REGISTER
TIMER OVERFLOW FLAG (TOF)
Figure 29. Counter Timing Diagram, internal clock divided by 8
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
0000
FFFC
FFFD
COUNTER REGISTER
TIMER OVERFLOW FLAG (TOF)
Note: The MCU is in reset state when the internal reset signal is high, when it is low the MCU is running.
45/135
ST72104G, ST72215G, ST72216G, ST72254G
16-BIT TIMER (Cont’d)
11.2.3.3 Input Capture
When an input capture occurs:
– ICFi bit is set.
In this section, the index, i, may be 1 or 2 because
there are 2 input capture functions in the 16-bit
timer.
– The ICiR register contains the value of the free
running counter on the active transition on the
ICAPi pin (see Figure 31).
The two input capture 16-bit registers (IC1R and
IC2R) are used to latch the value of the free run-
ning counter after a transition detected by the
ICAPi pin (see figure 5).
– A timer interrupt is generated if the ICIE bit is set
and the I bit is cleared in the CC register. Other-
wise, the interrupt remains pending until both
conditions become true.
MS Byte
ICiHR
LS Byte
ICiLR
ICiR
Clearing the Input Capture interrupt request (i.e.
clearing the ICFi bit) is done in two steps:
ICiR register is a read-only register.
1. Reading the SR register while the ICFi bit is set.
2. An access (read or write) to the ICiLR register.
The active transition is software programmable
through the IEDGi bit of Control Registers (CRi).
Timing resolution is one count of the free running
Notes:
counter: (f
/CC[1:0]).
CPU
1. After reading the ICiHR register, transfer of
input capture data is inhibited and ICFi will
never be set until the ICiLR register is also
read.
Procedure:
To use the input capture function select the follow-
ing in the CR2 register:
2. The ICiR register contains the free running
counter value which corresponds to the most
recent input capture.
– Select the timer clock (CC[1:0]) (see Table 13
Clock Control Bits).
3. The 2 input capture functions can be used
together even if the timer also uses the 2 output
compare functions.
– Select the edge of the active transition on the
ICAP2 pin with the IEDG2 bit (the ICAP2 pin
must be configured as floating input).
4. In One pulse Mode and PWM mode only the
input capture 2 can be used.
And select the following in the CR1 register:
– Set the ICIE bit to generate an interrupt after an
input capture coming from either the ICAP1 pin
or the ICAP2 pin
5. The alternate inputs (ICAP1 & ICAP2) are
always directly connected to the timer. So any
transitions on these pins activate the input cap-
ture function.
– Select the edge of the active transition on the
ICAP1 pin with theIEDG1 bit (the ICAP1pin must
be configured as floating input).
Moreover if one of the ICAPi pin is configured
as an input and the second one as an output,
an interrupt can be generated if the user toggle
the output pin and if the ICIE bit is set.
This can be avoided if the input capture func-
tion i is disabled by reading the ICiHR (see note
1).
6. The TOF bit can be used with interrupt in order
to measure event that go beyond the timer
range (FFFFh).
46/135
ST72104G, ST72215G, ST72216G, ST72254G
16-BIT TIMER (Cont’d)
Figure 30. Input Capture Block Diagram
ICAP1
pin
(Control Register 1) CR1
EDGE DETECT
CIRCUIT2
EDGE DETECT
CIRCUIT1
ICIE
IEDG1
ICAP2
pin
(Status Register) SR
ICF1
ICF2
0
0
0
IC2R Register
IC1R Register
(Control Register 2) CR2
16-BIT
16-BIT FREE RUNNING
COUNTER
IEDG2
CC0
CC1
Figure 31. Input Capture Timing Diagram
TIMER CLOCK
FF01
FF02
FF03
COUNTER REGISTER
ICAPi PIN
ICAPi FLAG
FF03
ICAPi REGISTER
Note: Active edge is rising edge.
47/135
ST72104G, ST72215G, ST72216G, ST72254G
16-BIT TIMER (Cont’d)
11.2.3.4 Output Compare
– The OCMPi pin takes OLVLi bit value (OCMPi
pin latch is forced low during reset).
In this section, the index, i, may be 1 or 2 because
there are 2 output compare functions in the 16-bit
timer.
– A timer interrupt is generated if the OCIE bit is
set in the CR2 register and the I bit is cleared in
the CC register (CC).
This function can be used to control an output
waveform or indicate when a period of time has
elapsed.
The OCiR register value required for aspecific tim-
ing application can be calculated using the follow-
ing formula:
When a match is found between the Output Com-
pare register and the free running counter, the out-
put compare function:
– Assigns pins with a programmable value if the
OCIE bit is set
∆t f
* CPU
PRESC
∆ OCiR =
– Sets a flag in the status register
– Generates an interrupt if enabled
Where:
∆t
= Output compare period (in seconds)
= CPU clock frequency (in hertz)
Two 16-bit registers Output Compare Register 1
(OC1R) and Output Compare Register 2 (OC2R)
contain the value to be compared to the counter
register each timer clock cycle.
f
CPU
= Timer prescaler factor (2, 4 or 8 de-
pending on CC[1:0] bits, see Table 13
Clock Control Bits)
PRESC
MS Byte
OCiHR
LS Byte
OCiLR
OCiR
If the timer clock is an external clock, the formula
is:
These registers are readable and writable and are
not affected by the timer hardware. A reset event
changes the OCiR value to 8000h.
∆ OCiR = ∆t f
* EXT
Timing resolution is one count of the free running
Where:
counter: (f
).
CC[1:0]
CPU/
∆t
= Output compare period (in seconds)
= External timer clock frequency (in hertz)
f
EXT
Procedure:
To use the output compare function, select the fol-
lowing in the CR2 register:
Clearing the output compare interrupt request (i.e.
clearing the OCFi bit) is done by:
– Set the OCiE bit if an output is needed then the
OCMPi pin is dedicated to the output compare i
signal.
1. Reading the SR register while the OCFi bit is
set.
2. An access (read or write) to the OCiLR register.
– Select the timer clock (CC[1:0]) (see Table 13
Clock Control Bits).
The following procedure is recommended to pre-
vent the OCFi bit from being set between the time
it is read and the write to the OCiR register:
And select the following in the CR1 register:
– Select theOLVLi bit to applied to theOCMPi pins
after the match occurs.
– Write to the OCiHR register (further compares
are inhibited).
– Set the OCIE bit to generate an interrupt if it is
needed.
– Read the SR register (first step of the clearance
of the OCFi bit, which may be already set).
When a match is found between OCRi register
and CR register:
– Write to the OCiLR register (enables the output
compare function and clears the OCFi bit).
– OCFi bit is set.
48/135
ST72104G, ST72215G, ST72216G, ST72254G
Forced Compare Output capability
16-BIT TIMER (Cont’d)
Notes:
1. After a processor write cycle to the OCiHR reg-
ister, the output compare function is inhibited
until the OCiLR register is also written.
When the FOLVi bit is set by software, the OLVLi
bit is copied to the OCMPi pin. The OLVi bit has to
be toggled in order to toggle the OCMPi pin when
it is enabled (OCiE bit=1). The OCFi bit is then not
set by hardware, and thus no interrupt request is
generated.
2. If the OCiE bit is not set, the OCMPi pin is a
general I/O port and the OLVLi bit will not
appear when a match is found but an interrupt
could be generated if the OCIE bit is set.
3. When the timer clock is f
/2, OCFi and
FOLVLi bits have no effect in both one pulse mode
and PWM mode.
CPU
OCMPi are set while the counter value equals
the OCiR register value (see Figure 33 on page
49). This behaviour is the same in OPM or
PWM mode.
When the timer clock is f
/4, f
/8 or in
CPU
CPU
external clock mode, OCFi and OCMPi are set
while the counter value equals the OCiR regis-
ter value plus 1 (see Figure 34 on page 49).
4. The output compare functions can be used both
for generating external events on the OCMPi
pins even if the input capture mode is also
used.
5. The value in the 16-bit OCiR register and the
OLVi bit should be changed after each suc-
cessful comparison in order to control an output
waveform or establish a new elapsed timeout.
Figure 32. Output Compare Block Diagram
16 BIT FREE RUNNING
OC1E
CC1 CC0
OC2E
COUNTER
(Control Register 2) CR2
16-bit
(Control Register 1) CR1
OUTPUT COMPARE
CIRCUIT
Latch
1
OCIE
FOLV2 FOLV1 OLVL2
OLVL1
OCMP1
Pin
16-bit
16-bit
Latch
2
OCMP2
Pin
OC1R Register
OCF1
OCF2
0
0
0
OC2R Register
(Status Register) SR
49/135
ST72104G, ST72215G, ST72216G, ST72254G
16-BIT TIMER (Cont’d)
Figure 33. Output Compare Timing Diagram, f
=f
/2
TIMER
CPU
INTERNAL CPU CLOCK
TIMER CLOCK
COUNTER REGISTER
2ECF 2ED0 2ED1 2ED2 2ED3 2ED4
2ED3
OUTPUT COMPARE REGISTER i (OCRi)
OUTPUT COMPARE FLAG i (OCFi)
OCMPi PIN (OLVLi=1)
Figure 34. Output Compare Timing Diagram, f
=f
/4
TIMER
CPU
INTERNAL CPU CLOCK
TIMER CLOCK
2ECF 2ED0 2ED1 2ED2
2ED3
2ED4
2ED3
COUNTER REGISTER
OUTPUT COMPARE REGISTER i (OCRi)
COMPARE REGISTER i LATCH
OUTPUT COMPARE FLAG i (OCFi)
OCMPi PIN (OLVLi=1)
50/135
ST72104G, ST72215G, ST72216G, ST72254G
16-BIT TIMER (Cont’d)
11.2.3.5 One Pulse Mode
Clearing the Input Capture interrupt request (i.e.
clearing the ICFi bit) is done in two steps:
One Pulse mode enables the generation of a
pulse when an external event occurs. This mode is
selected via the OPM bit in the CR2 register.
1. Reading the SR register while the ICFi bit is set.
2. An access (read or write) to the ICiLR register.
The one pulse mode uses the Input Capture1
function and the Output Compare1 function.
The OC1R register value required for a specific
timing application can be calculated using the fol-
lowing formula:
Procedure:
t * f
To use one pulse mode:
CPU - 5
OCiR Value =
PRESC
1. Load the OC1R register with the value corre-
sponding to the length of the pulse (see the for-
mula in the opposite column).
Where:
t
= Pulse period (in seconds)
2. Select the following in the CR1 register:
f
= CPU clock frequency (in hertz)
CPU
– Using the OLVL1 bit, select the level to be ap-
plied to the OCMP1 pin after the pulse.
= Timer prescaler factor (2, 4 or 8 depend-
ing on the CC[1:0] bits, see Table 13
Clock Control Bits)
PRESC
– Using the OLVL2 bit, select the level to be ap-
plied to the OCMP1 pin during the pulse.
If the timer clock is an external clock the formula is:
– Select the edge of the active transition on the
ICAP1 pin with the IEDG1 bit (the ICAP1 pin
must be configured as floating input).
OCiR = t f
-5
* EXT
Where:
t
3. Select the following in the CR2 register:
= Pulse period (in seconds)
– Set the OC1E bit, the OCMP1 pin is then ded-
icated to the Output Compare 1 function.
f
= External timer clock frequency (in hertz)
EXT
– Set the OPM bit.
When the value of the counter is equal to the value
of the contents of the OC1R register, the OLVL1
bit is output on the OCMP1 pin, (See Figure 35).
– Select the timer clock CC[1:0] (see Table 13
Clock Control Bits).
One pulse mode cycle
When
Notes:
1. The OCF1 bit cannot be set by hardware in one
pulse mode but the OCF2 bit can generate an
Output Compare interrupt.
OCMP1 = OLVL2
event occurs
on ICAP1
Counter is reset
2. When the Pulse Width Modulation (PWM) and
One Pulse Mode (OPM) bits are both set, the
PWM mode is the only active one.
to FFFCh
ICF1 bit is set
3. If OLVL1=OLVL2 a continuous signal will be
seen on the OCMP1 pin.
When
Counter
OCMP1 = OLVL1
= OC1R
4. The ICAP1 pin can not be used to perform input
capture. The ICAP2 pin can be used to perform
input capture (ICF2 can be set and IC2R can be
loaded) but the user must take care that the
counter is reset each time a valid edge occurs
on the ICAP1 pin and ICF1 can also generates
interrupt if ICIE is set.
Then, on a valid event on the ICAP1 pin, the coun-
ter is initialized to FFFCh and OLVL2 bit is loaded
on the OCMP1 pin, the ICF1 bit is set and the val-
ue FFFDh is loaded in the IC1R register.
Because the ICF1 bit is set when an active edge
occurs, an interrupt can be generated if the ICIE
bit is set.
5. When one pulse mode is used OC1R is dedi-
cated to this mode. Nevertheless OC2R and
OCF2 can be used to indicate a period of time
has been elapsed but cannot generate an out-
put waveform because the level OLVL2 is dedi-
cated to the one pulse mode.
51/135
ST72104G, ST72215G, ST72216G, ST72254G
16-BIT TIMER (Cont’d)
Figure 35. One Pulse Mode Timing Example
FFFC FFFD FFFE
COUNTER
2ED0 2ED1 2ED2
2ED3
FFFC FFFD
ICAP1
OLVL2
OLVL1
OLVL2
OCMP1
compare1
Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1
Figure 36. Pulse Width Modulation Mode Timing Example
2ED0 2ED1 2ED2
34E2 FFFC
FFFC FFFD FFFE
34E2
COUNTER
OCMP1
OLVL2
OLVL1
OLVL2
compare2
compare1
compare2
Note: OC1R=2ED0h, OC2R=34E2, OLVL1=0, OLVL2= 1
52/135
ST72104G, ST72215G, ST72216G, ST72254G
16-BIT TIMER (Cont’d)
11.2.3.6 Pulse Width Modulation Mode
Pulse Width Modulation (PWM) mode enables the
generation of a signal with a frequency and pulse
length determined by the value of the OC1R and
OC2R registers.
The OCiR register value required for aspecific tim-
ing application can be calculated using the follow-
ing formula:
t * f
CPU
PRESC
- 5
OCiR Value =
The pulse width modulation mode uses the com-
plete Output Compare 1 function plus the OC2R
register, and so these functionality can not be
used when the PWM mode is activated.
Where:
t
= Signal or pulse period (in seconds)
= CPU clock frequency (in hertz)
f
Procedure
CPU
= Timer prescaler factor (2, 4 or 8 depend-
ing on CC[1:0] bits, see Table 13 Clock
Control Bits)
To use pulse width modulation mode:
PRESC
1. Load the OC2R register with the value corre-
sponding to the period of the signal using the
formula in the opposite column.
If the timer clock is an external clock the formula is:
2. Load the OC1R register with the value corre-
sponding to the period of the pulse if (OLVL1=0
and OLVL2=1) using the formula in the oppo-
site column.
OCiR = t f
-5
* EXT
Where:
t
= Signal or pulse period (in seconds)
3. Select the following in the CR1 register:
f
= External timer clock frequency (in hertz)
EXT
– Using the OLVL1 bit, select the level to be ap-
plied to the OCMP1 pin after a successful
comparison with OC1R register.
The Output Compare 2 event causes the counter
to be initialized to FFFCh (See Figure 36)
– Using the OLVL2 bit, select the level to be ap-
plied to the OCMP1 pin after a successful
comparison with OC2R register.
Notes:
1. After a write instruction to the OCiHR register,
the output compare function is inhibited until the
OCiLR register is also written.
4. Select the following in the CR2 register:
– Set OC1E bit: the OCMP1 pin is then dedicat-
ed to the output compare 1 function.
2. The OCF1 and OCF2 bits cannot be set by
hardware in PWM mode therefore the Output
Compare interrupt is inhibited.
– Set the PWM bit.
– Select the timer clock (CC[1:0]) (see Table 13
Clock Control Bits).
3. The ICF1 bit is set by hardware when the coun-
ter reaches the OC2R value and can produce a
timer interrupt if the ICIE bit is set and the I bit is
cleared.
If OLVL1=1 and OLVL2=0 the length of the posi-
tive pulse is the difference between the OC2R and
OC1R registers.
4. In PWM mode the ICAP1 pin can not be used
to perform input capture because it is discon-
nected to the timer. The ICAP2 pin can be used
to perform input capture (ICF2 can be set and
IC2R can be loaded) but the user must take
care that the counter is reset each period and
ICF1 can also generates interrupt if ICIE is set.
If OLVL1=OLVL2 a continuous signal will be seen
on the OCMP1 pin.
Pulse Width Modulation cycle
When
5. When the Pulse Width Modulation (PWM) and
One Pulse Mode (OPM) bits are both set, the
PWM mode is the only active one.
Counter
= OC1R
OCMP1 = OLVL1
OCMP1 = OLVL2
When
Counter
= OC2R
Counter is reset
to FFFCh
ICF1 bit is set
53/135
ST72104G, ST72215G, ST72216G, ST72254G
16-BIT TIMER (Cont’d)
11.2.4 Low Power Modes
Mode
WAIT
Description
No effect on 16-bit Timer.
Timer interrupts cause the device to exit from WAIT mode.
16-bit Timer registers are frozen.
In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous
count when the MCU is woken up by an interrupt with “exit from HALT mode” capability or from the counter
reset value when the MCU is woken up by a RESET.
HALT
If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is armed. Consequent-
ly, when the MCU is woken up by an interrupt with “exit from HALT mode” capability, the ICFi bit is set, and
the counter value present when exiting from HALT mode is captured into the ICiR register.
11.2.5 Interrupts
Enable
Control from
Bit
Exit
Exit
from
Halt
Event
Flag
Interrupt Event
Wait
Yes
Yes
Yes
Yes
Yes
Input Capture 1 event/Counter reset in PWM mode
Input Capture 2 event
ICF1
ICF2
No
No
No
No
No
ICIE
Output Compare 1 event (not available in PWM mode)
Output Compare 2 event (not available in PWM mode)
Timer Overflow event
OCF1
OCF2
TOF
OCIE
TOIE
Note: The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts chap-
ter). These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt
mask in the CC register is reset (RIM instruction).
11.2.6 Summary of Timer modes
AVAILABLE RESOURCES
MODES
Input Capture 1
Input Capture 2
Yes
Output Compare 1 Output Compare 2
Input Capture (1 and/or 2)
Output Compare (1 and/or 2)
One Pulse Mode
Yes
Yes
No
Yes
Yes
No
Yes
Yes
Yes
1)
3)
2)
Not Recommended
Not Recommended
Partially
No
PWM Mode
No
No
1)
2)
3)
See note 4 in Section 11.2.3.5 ”One Pulse Mode” on page 50
See note 5 in Section 11.2.3.5 ”One Pulse Mode” on page 50
See note 4 in Section 11.2.3.6 ”Pulse Width Modulation Mode” on page 52
54/135
ST72104G, ST72215G, ST72216G, ST72254G
16-BIT TIMER (Cont’d)
11.2.7 Register Description
Bit 4 = FOLV2 Forced Output Compare 2.
This bit is set and cleared by software.
0: No effect on the OCMP2 pin.
1:Forces the OLVL2 bit to be copied to the
OCMP2 pin, if the OC2E bit is set and even if
there is no successful comparison.
Each Timer is associated with three control and
status registers, and with six pairs of data registers
(16-bit values) relating to the two input captures,
the two output compares, the counter and the al-
ternate counter.
Bit 3 = FOLV1 Forced Output Compare 1.
This bit is set and cleared by software.
0: No effect on the OCMP1 pin.
CONTROL REGISTER 1 (CR1)
Read/Write
1: Forces OLVL1 to becopied to theOCMP1 pin, if
the OC1E bit is set and even if there is no suc-
cessful comparison.
Reset Value: 0000 0000 (00h)
7
0
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
Bit 2 = OLVL2 Output Level 2.
This bit is copied to the OCMP2 pin whenever a
successful comparison occurs with the OC2R reg-
ister and OCxE is set in the CR2 register. This val-
ue is copied to the OCMP1 pin in One Pulse Mode
and Pulse Width Modulation mode.
Bit 7 = ICIE Input Capture Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the
ICF1 or ICF2 bit of the SR register is set.
Bit 1 = IEDG1 Input Edge 1.
Bit 6 = OCIE Output Compare Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the
OCF1 or OCF2 bit of the SR register is set.
This bit determines which type of level transition
on the ICAP1 pin will trigger the capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
Bit 5 = TOIE Timer Overflow Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is enabled whenever the TOF
bit of the SR register is set.
Bit 0 = OLVL1 Output Level 1.
The OLVL1 bit is copied to the OCMP1 pin when-
ever a successful comparison occurs with the
OC1R register and the OC1E bit is set in the CR2
register.
55/135
ST72104G, ST72215G, ST72216G, ST72254G
16-BIT TIMER (Cont’d)
CONTROL REGISTER 2 (CR2)
Read/Write
Bit 4 = PWM Pulse Width Modulation.
0: PWM mode is not active.
1: PWM mode is active, the OCMP1 pin outputs a
programmable cyclic signal; the length of the
pulse depends on the value of OC1R register;
the period depends on the value of OC2R regis-
ter.
Reset Value: 0000 0000 (00h)
7
0
OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG
Bit 3, 2 = CC[1:0] Clock Control.
Bit 7 = OC1E Output Compare 1 Pin Enable.
This bit is used only to output the signal from the
timer on the OCMP1 pin (OLV1 in Output Com-
pare mode, both OLV1 and OLV2 in PWM and
one-pulse mode). Whatever the value of the OC1E
bit, the Output Compare 1 function of the timer re-
mains active.
0: OCMP1 pin alternate function disabled (I/O pin
free for general-purpose I/O).
1: OCMP1 pin alternate function enabled.
The timer clock mode depends on these bits:
Table 13. Clock Control Bits
Timer Clock
fCPU / 4
CC1
CC0
0
0
1
0
1
0
fCPU / 2
fCPU / 8
External Clock (where
available)
1
1
Bit 6 = OC2E Output Compare 2 Pin Enable.
This bit is used only to output the signal from the
timer on the OCMP2 pin (OLV2 in Output Com-
pare mode). Whatever the value of the OC2E bit,
the Output Compare 2 function of the timer re-
mains active.
0: OCMP2 pin alternate function disabled (I/O pin
free for general-purpose I/O).
1: OCMP2 pin alternate function enabled.
Note: If the external clock pin is not available, pro-
gramming the external clock configuration stops
the counter.
Bit 1 = IEDG2 Input Edge 2.
This bit determines which type of level transition
on the ICAP2 pin will trigger the capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
Bit 5 = OPM One Pulse Mode.
0: One Pulse Mode is not active.
Bit 0 = EXEDG External Clock Edge.
This bit determines which type of level transition
on the external clock pin EXTCLK will trigger the
counter register.
0: A falling edge triggers the counter register.
1: A rising edge triggers the counter register.
1: One Pulse Mode is active, the ICAP1 pin can be
used to trigger one pulse on the OCMP1 pin; the
active transition is given by the IEDG1 bit. The
length of the generated pulse depends on the
contents of the OC1R register.
56/135
ST72104G, ST72215G, ST72216G, ST72254G
INPUT CAPTURE 1 HIGH REGISTER (IC1HR)
16-BIT TIMER (Cont’d)
STATUS REGISTER (SR)
Read Only
Read Only
Reset Value: Undefined
Reset Value: 0000 0000 (00h)
The three least significant bits are not used.
7
This is an 8-bit read only register that contains the
high part of the counter value (transferred by the
input capture 1 event).
0
0
ICF1 OCF1 TOF ICF2 OCF2
0
0
7
0
MSB
LSB
Bit 7 = ICF1 Input Capture Flag 1.
0: No input capture (reset value).
1: An input capture has occurred on the ICAP1 pin
or the counter has reached the OC2R value in
PWM mode. To clear this bit, first read the SR
register, then read or write the low byte of the
IC1R (IC1LR) register.
INPUT CAPTURE 1 LOW REGISTER (IC1LR)
Read Only
Reset Value: Undefined
This is an 8-bit read only register that contains the
low part of the counter value (transferred by the in-
put capture 1 event).
Bit 6 = OCF1 Output Compare Flag 1.
0: No match (reset value).
1: The content of the free running counter has
matched the content of the OC1R register. To
clear this bit, first read the SR register, then read
or write the low byte of the OC1R (OC1LR) reg-
ister.
7
0
MSB
LSB
OUTPUT COMPARE
(OC1HR)
1
HIGH REGISTER
Bit 5 = TOF Timer Overflow Flag.
0: No timer overflow (reset value).
Read/Write
Reset Value: 1000 0000 (80h)
1: The free running counter rolled over from FFFFh
to 0000h. To clear this bit, first read the SR reg-
ister, then read or write the low byte of the CR
(CLR) register.
This is an 8-bit register that contains the high part
of the value to be compared to the CHR register.
Note: Reading or writing the ACLR register does
not clear TOF.
7
0
MSB
LSB
Bit 4 = ICF2 Input Capture Flag 2.
0: No input capture (reset value).
1: An input capture has occurred on the ICAP2
pin. To clear this bit, first read the SR register,
then read or write the low byte of the IC2R
(IC2LR) register.
OUTPUT COMPARE
(OC1LR)
1
LOW REGISTER
Read/Write
Reset Value: 0000 0000 (00h)
Bit 3 = OCF2 Output Compare Flag 2.
0: No match (reset value).
1: The content of the free running counter has
matched the content of the OC2R register. To
clear this bit, first read the SR register, then read
or write the low byte of the OC2R (OC2LR) reg-
ister.
This is an 8-bit register that contains the low part of
the value to be compared to the CLR register.
7
0
MSB
LSB
Bit 2-0 = Reserved, forced by hardware to 0.
57/135
ST72104G, ST72215G, ST72216G, ST72254G
16-BIT TIMER (Cont’d)
OUTPUT COMPARE
(OC2HR)
2
HIGH REGISTER
ALTERNATE COUNTER HIGH REGISTER
(ACHR)
Read/Write
Reset Value: 1000 0000 (80h)
Read Only
Reset Value: 1111 1111 (FFh)
This is an 8-bit register that contains the high part
of the value to be compared to the CHR register.
This is an 8-bit register that contains the high part
of the counter value.
7
0
7
0
MSB
LSB
MSB
LSB
OUTPUT COMPARE
(OC2LR)
2
LOW REGISTER
ALTERNATE COUNTER LOW REGISTER
(ACLR)
Read/Write
Reset Value: 0000 0000 (00h)
Read Only
Reset Value: 1111 1100 (FCh)
This is an 8-bit register that contains the low part of
the value to be compared to the CLR register.
This is an 8-bit register that contains the low part of
the counter value. A write to this register resets the
counter. An access to this register after an access
to SR register does not clear the TOF bit in SR
register.
7
0
MSB
LSB
7
0
COUNTER HIGH REGISTER (CHR)
MSB
LSB
Read Only
Reset Value: 1111 1111 (FFh)
INPUT CAPTURE 2 HIGH REGISTER (IC2HR)
This is an 8-bit register that contains the high part
of the counter value.
Read Only
Reset Value: Undefined
7
0
This is an 8-bit read only register that contains the
high part of the counter value (transferred by the
Input Capture 2 event).
MSB
LSB
7
0
MSB
LSB
COUNTER LOW REGISTER (CLR)
Read Only
Reset Value: 1111 1100 (FCh)
This is an 8-bit register that contains the low part of
the countervalue. A write to this register resets the
counter. An access to this register after accessing
the SR register clears the TOF bit.
INPUT CAPTURE 2 LOW REGISTER (IC2LR)
Read Only
Reset Value: Undefined
This is an 8-bit read only register that contains the
low part of the counter value (transferred by the In-
put Capture 2 event).
7
0
MSB
LSB
7
0
MSB
LSB
58/135
ST72104G, ST72215G, ST72216G, ST72254G
16-BIT TIMER (Cont’d)
Table 14. 16-Bit Timer Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
Timer A: 32 CR1
ICIE
0
OCIE
0
TOIE
0
FOLV2
0
FOLV1
0
OLVL2
0
IEDG1
0
OLVL1
0
Timer B: 42 Reset Value
Timer A: 31 CR2
OC1E
0
OC2E
0
OPM
0
PWM
0
CC1
0
CC0
0
IEDG2
0
EXEDG
0
Timer B: 41 Reset Value
Timer A: 33 SR
ICF1
0
OCF1
0
TOF
0
ICF2
0
OCF2
0
-
-
-
Timer B: 43 Reset Value
0
0
0
Timer A: 34 ICHR1
MSB
-
LSB
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Timer B: 44 Reset Value
Timer A: 35 ICLR1
MSB
-
LSB
-
Timer B: 45 Reset Value
Timer A: 36 OCHR1
MSB
-
LSB
-
Timer B: 46 Reset Value
Timer A: 37 OCLR1
MSB
-
LSB
-
Timer B: 47 Reset Value
Timer A: 3E OCHR2
MSB
-
LSB
-
Timer B: 4E Reset Value
Timer A: 3F OCLR2
MSB
-
LSB
-
Timer B: 4F Reset Value
Timer A: 38 CHR
MSB
1
LSB
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
Timer B: 48 Reset Value
Timer A: 39 CLR
MSB
1
LSB
0
Timer B: 49 Reset Value
Timer A: 3A ACHR
MSB
1
LSB
1
Timer B: 4A Reset Value
Timer A: 3B ACLR
MSB
1
LSB
0
1
-
1
-
1
-
1
-
1
-
0
-
Timer B: 4B Reset Value
Timer A: 3C ICHR2
MSB
-
LSB
-
Timer B: 4C Reset Value
Timer A: 3D ICLR2
MSB
-
LSB
-
-
-
-
-
-
-
Timer B: 4D Reset Value
59/135
ST72104G, ST72215G, ST72216G, ST72254G
11.3 SERIAL PERIPHERAL INTERFACE (SPI)
11.3.1 Introduction
11.3.3 General description
The Serial Peripheral Interface (SPI) allows full-
duplex, synchronous, serial communication with
external devices. An SPI system may consist of a
master and one or more slaves or a system in
which devices may be either masters or slaves.
The SPI is connected to external devices through
4 alternate pins:
– MISO: Master In Slave Out pin
– MOSI: Master Out Slave In pin
– SCK: Serial Clock pin
The SPI is normally used for communication be-
tween the microcontroller and external peripherals
or another microcontroller.
– SS: Slave select pin
Refer to the Pin Description chapter for the device-
specific pin-out.
A basic example of interconnections between a
single master and a single slave is illustrated on
Figure 37.
11.3.2 Main Features
The MOSI pins are connected together as are
MISO pins. In this way data is transferred serially
between master and slave (most significant bit
first).
■ Full duplex, three-wire synchronous transfers
■ Master or slave operation
■ Four master mode frequencies
■ Maximum slave mode frequency = fCPU/2.
■ Four programmable master bit rates
■ Programmable clock polarity and phase
■ End of transfer interrupt flag
When the master device transmits data to a slave
device via MOSI pin, the slave device responds by
sending data to the master device via the MISO
pin. This implies full duplex transmission with both
data out and data in synchronized with the same
clock signal (which is provided by the master de-
vice via the SCK pin).
■ Write collision flag protection
■ Master mode fault protection capability.
Thus, the byte transmitted is replaced by the byte
received and eliminates the need for separate
transmit-empty and receiver-full bits. A status flag
is used to indicate that the I/O operation is com-
plete.
Four possible data/clock timing relationships may
be chosen (see Figure 40) but master and slave
must be programmed with the same timing mode.
Figure 37. Serial Peripheral Interface Master/Slave
MASTER
SLAVE
MSBit
LSBit
MSBit
LSBit
MISO
MOSI
MISO
MOSI
8-BIT SHIFT REGISTER
8-BIT SHIFT REGISTER
SPI
CLOCK
GENERATOR
SCK
SS
SCK
SS
+5V
60/135
ST72104G, ST72215G, ST72216G, ST72254G
SERIAL PERIPHERAL INTERFACE (Cont’d)
Figure 38. Serial Peripheral Interface Block Diagram
Internal Bus
Read
DR
IT
Read Buffer
request
MOSI
SR
MISO
8-Bit Shift Register
Write
MODF
WCOL
SPIF
-
-
-
-
-
SPI
STATE
CONTROL
SCK
SS
CR
SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0
MASTER
CONTROL
SERIAL
CLOCK
GENERATOR
61/135
ST72104G, ST72215G, ST72216G, ST72254G
SERIAL PERIPHERAL INTERFACE (Cont’d)
11.3.4 Functional Description
In this configuration the MOSI pin is a data output
and to the MISO pin is a data input.
Figure 37 shows the serial peripheral interface
(SPI) block diagram.
This interface contains 3 dedicated registers:
– A Control Register (CR)
Transmit sequence
The transmit sequence begins when a byte is writ-
ten the DR register.
– A Status Register (SR)
The data byte is parallel loaded into the 8-bit shift
register (from the internal bus) during a write cycle
and then shifted out serially to the MOSI pin most
significant bit first.
– A Data Register (DR)
Refer to the CR, SR and DR registers in Section
11.3.7for the bit definitions.
11.3.4.1 Master Configuration
When data transfer is complete:
– The SPIF bit is set by hardware
In a master configuration, the serial clock is gener-
ated on the SCK pin.
– An interrupt is generated if the SPIE bit is set
and the I bit in the CCR register is cleared.
Procedure
– Select the SPR0 & SPR1 bits to define the se-
rial clock baud rate (see CR register).
During the last clock cycle the SPIF bit is set, a
copy of the data byte received in the shift register
is moved to a buffer. When the DR register is read,
the SPI peripheral returns this buffered value.
– Select the CPOL and CPHA bits to define one
of the four relationships between the data
transfer and the serial clock (see Figure 40).
Clearing the SPIF bit is performed by the following
software sequence:
– The SS pin must be connected to a high level
signal during the complete byte transmit se-
quence.
1. An access to the SR register while the SPIF bit
is set
– The MSTR and SPE bits must be set (they re-
main set only if the SS pin is connected to a
high level signal).
2. A write or a read of the DR register.
Note: While the SPIF bit is set, all writes to the DR
register are inhibited until the SR register is read.
62/135
ST72104G, ST72215G, ST72216G, ST72254G
SERIAL PERIPHERAL INTERFACE (Cont’d)
11.3.4.2 Slave Configuration
When data transfer is complete:
– The SPIF bit is set by hardware
In slave configuration, the serial clock is received
on the SCK pin from the master device.
– An interrupt is generated if SPIE bit is set and
I bit in CCR register is cleared.
The value of the SPR0 & SPR1 bits is not used for
the data transfer.
During the last clock cycle the SPIF bit is set, a
copy of the data byte received in the shift register
is moved to a buffer. When the DR register is read,
the SPI peripheral returns this buffered value.
Procedure
– For correct data transfer, the slave device
must be in the same timing mode as the mas-
ter device (CPOL and CPHA bits). See Figure
40.
Clearing the SPIF bit is performed by the following
software sequence:
1. An access to the SR register while the SPIF bit
is set.
– The SS pin must be connected to a low level
signal during the complete byte transmit se-
quence.
2. A write or a read of the DR register.
– Clear the MSTR bit and set the SPE bit to as-
sign the pins to alternate function.
Notes: While the SPIF bit is set, all writes to the
DR register are inhibited until the SR register is
read.
In this configuration the MOSI pin is a data input
and the MISO pin is a data output.
The SPIF bit can be cleared during a second
transmission; however, it must be cleared before
the second SPIF bit in order to prevent an overrun
condition (see Section 11.3.4.6).
Transmit Sequence
The data byte is parallel loaded into the 8-bit shift
register (from the internal bus) during a write cycle
and then shifted out serially to the MISO pin most
significant bit first.
Depending on the CPHA bit, the SS pin has to be
set to write to the DR register between each data
byte transfer to avoid a write collision (see Section
11.3.4.4).
The transmit sequence begins when the slave de-
vice receives the clock signal and the most signifi-
cant bit of the data on its MOSI pin.
63/135
ST72104G, ST72215G, ST72216G, ST72254G
SERIAL PERIPHERAL INTERFACE (Cont’d)
11.3.4.3 Data Transfer Format
The master device applies data to its MOSI pin-
clock edge before the capture clock edge.
During an SPI transfer, data is simultaneously
transmitted (shifted out serially) and received
(shifted in serially). The serial clock is used to syn-
chronize the data transfer during a sequence of
eight clock pulses.
CPHA bit is set
The second edge on the SCK pin (falling edge if
the CPOL bit is reset, rising edge if the CPOL bit is
set) is the MSBit capture strobe. Data is latched on
the occurrence of the second clock transition.
The SS pin allows individual selection of a slave
device; the other slave devices that are not select-
ed do not interfere with the SPI transfer.
No write collision should occur even if the SS pin
stays low during a transfer of several bytes (see
Figure 39).
Clock Phase and Clock Polarity
Four possible timing relationships may be chosen
by software, using the CPOL and CPHA bits.
CPHA bit is reset
The CPOL (clock polarity) bit controls the steady
state value of the clock when no data is being
transferred. This bit affects both master and slave
modes.
The firstedge on the SCK pin (falling edge if CPOL
bit is set, rising edge if CPOL bit is reset) is the
MSBit capture strobe. Data is latched on the oc-
currence of the first clock transition.
The combination between the CPOL and CPHA
(clock phase) bits selects the data capture clock
edge.
The SS pin must be toggled high and low between
each byte transmitted (see Figure 39).
To protect the transmission from a write collision a
low value on the SS pin of a slave device freezes
the data in its DR register and does not allow it to
be altered. Therefore the SS pin must be high to
write a new data byte in the DR without producing
a write collision.
Figure 40, shows an SPI transfer with the four
combinations of the CPHA and CPOL bits. The di-
agram may be interpreted as a master or slave
timing diagram where the SCK pin, the MISO pin,
the MOSI pin are directly connected between the
master and the slave device.
The SS pin is the slave device select input and can
be driven by the master device.
Figure 39. CPHA / SS Timing Diagram
Byte 3
Byte 2
MOSI/MISO
Master SS
Byte 1
Slave SS
(CPHA=0)
Slave SS
(CPHA=1)
VR02131A
64/135
ST72104G, ST72215G, ST72216G, ST72254G
SERIAL PERIPHERAL INTERFACE (Cont’d)
Figure 40. Data Clock Timing Diagram
CPHA =1
SCLK (with
CPOL = 1)
SCLK (with
CPOL = 0)
Bit 4
Bit 4
Bit3
Bit3
Bit 2
Bit 2
Bit 1
Bit 1
LSBit
LSBit
MSBit
MSBit
Bit 6
Bit 6
Bit 5
Bit 5
MISO
(from master)
MOSI
(from slave)
SS
(to slave)
CAPTURE STROBE
CPHA =0
CPOL = 1
CPOL = 0
Bit 4
Bit 4
Bit3
Bit 2
Bit 2
Bit 1
Bit 1
LSBit
LSBit
MSBit
Bit 6
Bit 6
Bit 5
Bit 5
MISO
(from master)
MSBit
Bit3
MOSI
(from slave)
SS
(to slave)
CAPTURE STROBE
Note: This figure should not be used as a replacement for parametric information.
Refer to the Electrical Characteristics chapter.
VR02131B
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ST72104G, ST72215G, ST72216G, ST72254G
SERIAL PERIPHERAL INTERFACE (Cont’d)
11.3.4.4 Write Collision Error
When the CPHA bit is reset:
A write collision occurs when the software tries to
write to the DR register while a data transfer is tak-
ing place with an external device. When this hap-
pens, the transfer continues uninterrupted; and
the software write will be unsuccessful.
Data is latched on the occurrence of the first clock
transition. The slave device does not have any
way of knowing when that transition will occur;
therefore, the slave device collision occurs when
software attempts to write the DR register after its
SS pin has been pulled low.
Write collisions can occur both in master and slave
mode.
For this reason, the SS pin must be high, between
each data byte transfer, to allow the CPU to write
in the DR register without generating a write colli-
sion.
Note: a ”read collision” will never occur since the
received data byte is placed in a buffer in which
access is always synchronous with the MCU oper-
ation.
In Slave mode
In Master mode
When the CPHA bit is set:
Collision in the master device is defined as a write
of the DR register while the internal serial clock
(SCK) is in the process of transfer.
The slave device will receive a clock (SCK) edge
prior to the latch of the first data transfer. This first
clock edge will freeze the data in the slave device
DR register and output the MSBit on to the exter-
nal MISO pin of the slave device.
The SS pin signal must be always high on the
master device.
The SS pin low state enables the slave device but
the output of the MSBit onto the MISO pin does
not take place until the first data transfer clock
edge.
WCOL bit
The WCOL bit in the SR register is set if a write
collision occurs.
No SPI interrupt is generated when the WCOL bit
is set (the WCOL bit is a status flag only).
Clearing the WCOL bit is done through a software
sequence (see Figure 41).
Figure 41. Clearing the WCOL bit (Write Collision Flag) Software Sequence
Clearing sequence after SPIF = 1 (end of a data byte transfer)
Read SR
Read SR
1st Step
2nd Step
OR
THEN
THEN
SPIF =0
WCOL=0
SPIF =0
WCOL=0 if no transfer has started
WCOL=1 if a transfer has started
before the 2nd step
Read DR
Write DR
Clearing sequence before SPIF = 1 (during a data byte transfer)
Read SR
1st Step
THEN
Note: Writing in DR register in-
2nd Step
Read DR
stead of reading in it do not reset
WCOL bit
WCOL=0
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ST72104G, ST72215G, ST72216G, ST72254G
SERIAL PERIPHERAL INTERFACE (Cont’d)
11.3.4.5 Master Mode Fault
may be restored to their original state during or af-
ter this clearing sequence.
Master mode fault occurs when the master device
has its SS pin pulled low, then the MODF bit is set.
Hardware does not allow the user to set the SPE
and MSTR bits while the MODF bit is set except in
the MODF bit clearing sequence.
Master mode fault affects the SPI peripheral in the
following ways:
In a slave device the MODF bit can not be set, but
in a multi master configuration the device can be in
slave mode with this MODF bit set.
– The MODF bit is set and an SPI interrupt is
generated if the SPIE bit is set.
– The SPE bit is reset. This blocks all output
from the device and disables the SPI periph-
eral.
The MODF bit indicates that there might have
been amulti-master conflict for system control and
allows a proper exit from system operation to a re-
set or default system state using an interrupt rou-
tine.
– The MSTR bit is reset, thus forcing the device
into slave mode.
Clearing the MODF bit is done through a software
sequence:
11.3.4.6 Overrun Condition
An overrun condition occurs when the master de-
vice has sent several data bytes and the slave de-
vice has not cleared the SPIF bit issuing from the
previous data byte transmitted.
1. A read or write access to the SR register while
the MODF bit is set.
2. A write to the CR register.
In this case, the receiver buffer contains the byte
sent after the SPIF bit was last cleared. A read to
the DR register returns this byte. All other bytes
are lost.
Notes: To avoid any multiple slave conflicts in the
case of a system comprising several MCUs, the
SS pin must be pulled high during the clearing se-
quence of the MODF bit. The SPE and MSTR bits
This condition is not detected by the SPI peripher-
al.
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ST72104G, ST72215G, ST72216G, ST72254G
SERIAL PERIPHERAL INTERFACE (Cont’d)
11.3.4.7 Single Master and Multimaster Configurations
There are two types of SPI systems:
– Single Master System
For more security, the slave device may respond
to the master with the received data byte. Then the
master will receive the previous byte back from the
slave device if all MISO and MOSI pins are con-
nected and the slave has not written its DR regis-
ter.
– Multimaster System
Single Master System
Other transmission security methods can use
ports for handshake lines or data bytes with com-
mand fields.
A typical single master system may be configured,
using an MCU as the master and four MCUs as
slaves (see Figure 42).
Multi-master System
The master device selects the individual slave de-
vices by using four pins of a parallel port to control
the four SS pins of the slave devices.
A multi-master system may also be configured by
the user. Transfer of master control could be im-
plemented using a handshake method through the
I/O ports or by an exchange of code messages
through the serial peripheral interface system.
The SS pins are pulled high during reset since the
master device ports will be forced to be inputs at
that time, thus disabling the slave devices.
The multi-master system is principally handled by
the MSTR bit in the CR register and the MODF bit
in the SR register.
Note: To prevent a bus conflict on the MISO line
the master allows only one active slave device
during a transmission.
Figure 42. Single Master Configuration
SS
SS
SS
SS
SCK
SCK
Slave
SCK
Slave
SCK
Slave
MCU
Slave
MCU
MCU
MCU
MOSI MISO
MOSI MISO
MOSI MISO
MOSI MISO
MOSI MISO
SCK
Master
MCU
5V
SS
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ST72104G, ST72215G, ST72216G, ST72254G
SERIAL PERIPHERAL INTERFACE (Cont’d)
11.3.5 Low Power Modes
Mode
Description
No effect on SPI.
WAIT
SPI interrupt events cause the device to exit from WAIT mode.
SPI registers are frozen.
HALT
In HALT mode, the SPI is inactive. SPI operation resumes when the MCU is woken up by an interrupt with
“exit from HALT mode” capability.
11.3.6 Interrupts
Enable
Control from
Bit
Exit
Exit
from
Halt
Event
Flag
Interrupt Event
Wait
Yes
Yes
SPI End of Transfer Event
Master Mode Fault Event
SPIF
No
No
SPIE
MODF
Note: The SPI interrupt events are connected to
the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding
Enable Control Bit is set and the interrupt mask in
the CC register is reset (RIM instruction).
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ST72104G, ST72215G, ST72216G, ST72254G
SERIAL PERIPHERAL INTERFACE (Cont’d)
11.3.7 Register Description
CONTROL REGISTER (CR)
Read/Write
Bit 3 = CPOL Clock polarity.
This bit is set and cleared by software. This bit de-
termines the steady state of the serial Clock. The
CPOL bit affects both the master and slave
modes.
0: The steady state is a low value at the SCK pin.
1: The steady state is a high value at the SCK pin.
Reset Value: 0000xxxx (0xh)
7
0
SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0
Bit 7 = SPIE Serial peripheral interrupt enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SPI interrupt is generated whenever SPIF=1
or MODF=1 in the SR register
Bit 2 = CPHA Clock phase.
This bit is set and cleared by software.
0: The first clock transition is the first data capture
edge.
1: The second clock transition is the first capture
edge.
Bit 6 = SPE Serial peripheral output enable.
This bit is set and cleared by software. It is also
cleared by hardware when, in master mode, SS=0
(see Section 11.3.4.5 ”Master Mode Fault” on
page 66).
Bit 1:0 = SPR[1:0] Serial peripheral rate.
These bits are set and cleared by software.Used
with the SPR2 bit, they select one of six baud rates
to be used as the serial clock when the device is a
master.
0: I/O port connected to pins
1: SPI alternate functions connected to pins
The SPE bit is cleared by reset, so the SPI periph-
eral is not initially connected to the external pins.
These 2 bits have no effect in slave mode.
Table 15. Serial Peripheral Baud Rate
Bit 5 = SPR2 Divider Enable.
Serial Clock
SPR2 SPR1 SPR0
this bit is set and cleared by software and it is
cleared by reset. It is used with the SPR[1:0] bits to
set the baud rate. Refer to Table 15.
0: Divider by 2 enabled
f
f
/2
/8
1
0
0
1
0
0
0
0
0
1
1
1
0
0
1
0
0
1
CPU
CPU
f
f
f
/16
/32
/64
CPU
CPU
CPU
1: Divider by 2 disabled
f
/128
CPU
Bit 4 = MSTR Master.
This bit is set and cleared by software. It is also
cleared by hardware when, in master mode, SS=0
(see Section 11.3.4.5 ”Master Mode Fault” on
page 66).
0: Slave mode is selected
1: Master mode is selected, the function of the
SCK pin changes from an input to an output and
the functions of the MISO and MOSI pins are re-
versed.
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ST72104G, ST72215G, ST72216G, ST72254G
SERIAL PERIPHERAL INTERFACE (Cont’d)
STATUS REGISTER (SR)
Read Only
DATA I/O REGISTER (DR)
Read/Write
Reset Value: 0000 0000 (00h)
Reset Value: Undefined
7
0
-
7
0
SPIF
WCOL
-
MODF
-
-
-
D7
D6
D5
D4
D3
D2
D1
D0
Bit 7 = SPIF Serial Peripheral data transfer flag.
This bit is set by hardware when a transfer has
been completed. An interrupt is generated if
SPIE=1 in the CR register. It is cleared by a soft-
ware sequence (an access to the SR register fol-
lowed by a read or write to the DR register).
0: Data transfer is in progress or has been ap-
proved by a clearing sequence.
The DR register is used to transmit and receive
data on the serial bus. In the master device only a
write to this register will initiate transmission/re-
ception of another byte.
Notes: During the last clock cycle the SPIF bit is
set, a copy of the received data byte in the shift
register is moved to a buffer. When the user reads
the serial peripheral data I/O register, the buffer is
actually being read.
1: Data transfer between the device and an exter-
nal device has been completed.
Warning:
Note: While the SPIF bit is set, all writes to the DR
register are inhibited.
A write to the DR register places data directly into
the shift register for transmission.
A write to the the DR register returns the value lo-
cated in the buffer and not the contents of the shift
register (See Figure 38 ).
Bit 6 = WCOL Write Collision status.
This bit is set by hardware when a write to the DR
register is done during a transmit sequence. It is
cleared by a software sequence (see Figure 41).
0: No write collision occurred
1: A write collision has been detected
Bit 5 = Unused.
Bit 4 = MODF Mode Fault flag.
This bit is set by hardware when the SS pin is
pulled low in master mode (see Section 11.3.4.5
”Master Mode Fault” on page 66). An SPI interrupt
can be generated if SPIE=1 in the CR register.
This bit is cleared by a software sequence (An ac-
cess to the SR register while MODF=1 followed by
a write to the CR register).
0: No master mode fault detected
1: A fault in master mode has been detected
Bits 3-0 = Unused.
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ST72104G, ST72215G, ST72216G, ST72254G
SERIAL PERIPHERAL INTERFACE (Cont’d)
Table 16. SPI Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
SPIDR
Reset Value
MSB
x
LSB
x
0021h
0022h
0023h
x
x
x
x
x
x
SPICR
Reset Value
SPIE
0
SPE
0
SPR2
0
MSTR
0
CPOL
x
CPHA
x
SPR1
x
SPR0
x
SPISR
Reset Value
SPIF
0
WCOL
0
MODF
0
0
0
0
0
0
72/135
ST72104G, ST72215G, ST72216G, ST72254G
2
11.4 I C BUS INTERFACE (I2C)
11.4.1 Introduction
handshake. The interrupts are enabled or disabled
2
2
by software. The interface is connected to the I C
The I C Bus Interface serves as an interface be-
tween the microcontroller and the serial I C bus. It
2
bus by a data pin (SDAI) and by a clock pin (SCLI).
2
It can be connected both with a standard I C bus
provides both multimaster and slave functions,
2
2
and a Fast I C bus. This selection is made by soft-
and controls all I C bus-specific sequencing, pro-
2
ware.
tocol, arbitration and timing. It supports fast I C
mode (400kHz).
Mode Selection
11.4.2 Main Features
The interface can operate in the four following
modes:
2
■ Parallel-bus/I C protocol converter
– Slave transmitter/receiver
■ Multi-master capability
– Master transmitter/receiver
By default, it operates in slave mode.
■ 7-bit/10-bit Addressing
■ Transmitter/Receiver flag
■ End-of-byte transmission flag
■ Transfer problem detection
The interface automatically switches from slave to
master after it generates a START condition and
from master to slave in case of arbitration loss or a
STOP generation, allowing then Multi-Master ca-
pability.
2
I C Master Features:
■ Clock generation
2
■ I C bus busy flag
Communication Flow
■ Arbitration Lost Flag
In Master mode, it initiates a data transfer and
generates the clock signal. A serial data transfer
always begins with a start condition and ends with
a stop condition. Both start and stop conditions are
generated in master mode by software.
■ End of byte transmission flag
■ Transmitter/Receiver Flag
■ Start bit detection flag
■ Start and Stop generation
In Slave mode, the interface is capable of recog-
nising its own address (7 or 10-bit), and the Gen-
eral Call address. The General Call address de-
tection may be enabled or disabled by software.
2
I C Slave Features:
■ Stop bit detection
2
■ I C bus busy flag
Data and addresses are transferred as 8-bit bytes,
MSB first. The first byte(s) following the start con-
dition contain the address (one in 7-bit mode, two
in 10-bit mode). The address is always transmitted
in Master mode.
■ Detection of misplaced start or stop condition
2
■ Programmable I C Address detection
■ Transfer problem detection
■ End-of-byte transmission flag
■ Transmitter/Receiver flag
11.4.3 General Description
A 9th clock pulse follows the 8 clock cycles of a
byte transfer, during which the receiver must send
an acknowledge bit to the transmitter. Refer to Fig-
ure 43.
In addition to receiving and transmitting data, this
interface converts it from serial to parallel format
and vice versa, using either an interrupt or polled
2
Figure 43. I C BUS Protocol
SDA
MSB
ACK
SCL
1
2
8
9
START
STOP
CONDITION
CONDITION
VR02119B
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ST72104G, ST72215G, ST72216G, ST72254G
2
I C BUS INTERFACE (Cont’d)
Acknowledge may be enabled and disabled by
software.
The SCL frequency (F ) is controlled by a pro-
scl
grammable clock divider which depends on the
2
2
I C bus mode.
The I C interface address and/or general call ad-
2
dress can be selected by software.
When the I C cell is enabled, the SDA and SCL
2
ports must be configured as floating inputs. In this
case, the value of the external pull-up resistor
used depends on the application.
The speed of the I C interface may be selected
2
between Standard (0-100KHz) and Fast I C (100-
400KHz).
2
When the I C cell is disabled, the SDA and SCL
ports revert to being standard I/O port pins.
SDA/SCL Line Control
Transmitter mode: the interface holds the clock
line low before transmission to wait for the micro-
controller to write the byte in the Data Register.
Receiver mode: the interface holds the clock line
low after reception to wait for the microcontroller to
read the byte in the Data Register.
2
Figure 44. I C Interface Block Diagram
DATA REGISTER (DR)
DATA CONTROL
SDA or SDAI
DATA SHIFT REGISTER
COMPARATOR
OWN ADDRESS REGISTER1 (OAR1)
OWN ADDRESS REGISTER 2 (OAR2)
CLOCK CONTROL
SCL or SCLI
CLOCK CONTROL REGISTER (CCR)
CONTROL REGISTER (CR)
STATUS REGISTER 1 (SR1)
STATUS REGISTER 2 (SR2)
CONTROL LOGIC
INTERRUPT
74/135
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2
I C BUS INTERFACE (Cont’d)
11.4.4 Functional Description
– EVF and BTF bits are set with an interrupt if the
ITE bit is set.
Refer to the CR, SR1 and SR2 registers in Section
11.4.7. for the bit definitions.
Then the interface waits for a read of the SR1 reg-
ister followed by a read of the DR register, holding
the SCL line low (see Figure 45 Transfer se-
quencing EV2).
2
By default the I C interface operates in Slave
mode (M/SL bit is cleared) except when it initiates
a transmit or receive sequence.
First the interface frequency must be configured
using the FRi bits in the OAR2 register.
Slave Transmitter
Following the address reception and after SR1
register has been read, the slave sends bytes from
the DR register to the SDA line via the internal shift
register.
11.4.4.1 Slave Mode
As soon as a start condition is detected, the
address is received from the SDA line and sent to
the shift register; then it is compared with the
address of the interface or the General Call
address (if selected by software).
The slave waits for a read of the SR1 register fol-
lowed by a write in the DR register, holding the
SCL line low (see Figure 45 Transfer sequencing
EV3).
Note: In 10-bit addressing mode, the comparision
includes the header sequence (11110xx0) and the
two most significant bits of the address.
When the acknowledge pulse is received:
Header matched (10-bit mode only): the interface
generates an acknowledge pulse if the ACK bit is
set.
– The EVF and BTF bits are set by hardware with
an interrupt if the ITE bit is set.
Address not matched: the interface ignores it
Closing slave communication
and waits for another Start condition.
After the last data byte is transferred a Stop Con-
dition is generated by the master. The interface
detects this condition and sets:
Address matched: the interface generates in se-
quence:
– Acknowledge pulse if the ACK bit is set.
– EVF and STOPF bits with an interrupt if the ITE
bit is set.
– EVFand ADSL bits are set with an interrupt if the
ITE bit is set.
Then the interface waits for a read of the SR2 reg-
ister (see Figure 45 Transfer sequencing EV4).
Then the interface waits for a read of the SR1 reg-
ister, holding the SCL line low (see Figure 45
Transfer sequencing EV1).
Next, in 7-bit mode read the DR register to deter-
mine from the least significant bit (Data Direction
Bit) if the slave must enter Receiver or Transmitter
mode.
Error Cases
– BERR: Detection of a Stop or a Start condition
during a byte transfer. In this case, the EVF and
the BERR bits are set with an interrupt if the ITE
bit is set.
If it is a Stop then the interface discards thedata,
released the lines and waits for another Start
condition.
In 10-bit mode, after receiving the address se-
quence the slave is always in receive mode. It will
enter transmit mode on receiving a repeated Start
condition followed by the header sequence with
matching address bits and the least significant bit
set (11110xx1) .
If it is a Start then the interface discards the data
and waits for the next slave address on the bus.
– AF: Detection of a non-acknowledge bit. In this
case, the EVF and AF bits are set with an inter-
rupt if the ITE bit is set.
Slave Receiver
Following the address reception and after SR1
register has been read, the slave receives bytes
from the SDA line into the DR register via the inter-
nal shift register. After each byte the interface gen-
erates in sequence:
Note: In both cases, SCL line is not held low; how-
ever, SDA line can remain low due to possible «0»
bits transmitted last. It is then necessary to release
both lines by software.
– Acknowledge pulse if the ACK bit is set
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2
I C BUS INTERFACE (Cont’d)
How to release the SDA / SCL lines
After completion of this transfer (and acknowledge
from the slave if the ACK bit is set):
Set and subsequently clear the STOP bit while
BTF is set. The SDA/SCL lines are released after
the transfer of the current byte.
– The EVF bit is set by hardware with interrupt
generation if the ITE bit is set.
11.4.4.2 Master Mode
Then the master waits for a read of the SR1 regis-
ter followed by a write in the CR register (for exam-
ple set PE bit), holding the SCL line low (see Fig-
ure 45 Transfer sequencing EV6).
To switch from default Slave mode to Master
mode a Start condition generation is needed.
Start condition
Next the master must enter Receiver or Transmit-
ter mode.
Setting the START bit while the BUSY bit is
cleared causes the interface to switch to Master
mode (M/SL bit set) and generates a Start condi-
tion.
Note: In 10-bit addressing mode, to switch the
master to Receiver mode, software must generate
a repeated Start condition and resend the header
sequence with the least significant bit set
(11110xx1).
Once the Start condition is sent:
– The EVF and SB bits are set by hardware with
an interrupt if the ITE bit is set.
Then the master waits for a read of the SR1 regis-
ter followed by a write in the DR register with the
Slave address, holding the SCL line low (see
Figure 45 Transfer sequencing EV5).
Master Receiver
Following the address transmission and after SR1
and CR registers have been accessed, the master
receives bytes from the SDA line into the DR reg-
ister via the internal shift register. After each byte
the interface generates in sequence:
Slave address transmission
– Acknowledge pulse if if the ACK bit is set
Then the slave address is sent to the SDA line via
the internal shift register.
– EVFand BTF bits are set by hardware withan in-
terrupt if the ITE bit is set.
In 7-bit addressing mode, one address byte is
sent.
Then the interface waits for a read of the SR1 reg-
ister followed by a read of the DR register, holding
the SCL line low (see Figure 45 Transfer se-
quencing EV7).
In 10-bit addressing mode, sending the first byte
including the header sequence causes the follow-
ing event:
– The EVF bit is set by hardware with interrupt
generation if the ITE bit is set.
Then the master waits for a read of the SR1 regis-
ter followed by a write in the DR register, holding
the SCL line low (see Figure 45 Transfer se-
quencing EV9).
To close the communication: before reading the
last byte from the DR register, set the STOP bit to
generate the Stop condition. The interface goes
automatically back to slave mode (M/SL bit
cleared).
Note: In order to generate the non-acknowledge
pulse after the last received data byte, the ACK bit
must be cleared just before reading the second
last data byte.
Then the second address byte is sent by the inter-
face.
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2
I C BUS INTERFACE (Cont’d)
Master Transmitter
BERR bits are set by hardware with an interrupt
if ITE is set.
Following the address transmission and after SR1
register has been read, the master sends bytes
from the DR register to the SDA line via the inter-
nal shift register.
– AF: Detection of a non-acknowledge bit. In this
case, the EVF and AF bits are set by hardware
with an interrupt if the ITE bit is set. To resume,
set the START or STOP bit.
The master waits for a read of the SR1 register fol-
lowed by a write in the DR register, holding the
SCL line low (see Figure 45 Transfer sequencing
EV8).
– ARLO: Detection of an arbitration lost condition.
In this case theARLO bit is set by hardware (with
an interrupt if the ITE bit is set and the interface
goes automatically backto slave mode (the M/SL
bit is cleared).
When the acknowledge bit is received, the
interface sets:
Note: In all these cases, the SCL line is not held
low; however, the SDA line can remain low due to
possible «0» bits transmitted last. It is then neces-
sary to release both lines by software.
– EVF and BTF bits with an interrupt if the ITE bit
is set.
To close the communication: after writing the last
byte to the DR register, set the STOP bit to gener-
ate the Stop condition. The interface goes auto-
matically back to slave mode (M/SL bit cleared).
Error Cases
– BERR: Detection of a Stop or a Start condition
during a bytetransfer. In this case, the EVF and
77/135
ST72104G, ST72215G, ST72216G, ST72254G
2
I C BUS INTERFACE (Cont’d)
Figure 45. Transfer Sequencing
7-bit Slave receiver:
S
Address
A
Data1
A
Data1
Data1
Data2
EV3
A
DataN
A
P
.....
EV1
EV2
A
EV2
A
EV2
NA
EV4
7-bit Slave transmitter:
S
Address
A
Data2
DataN
P
.....
.....
EV1 EV3
EV3
EV3-1
EV4
7-bit Master receiver:
S
Address
A
A
Data2
A
DataN NA
P
EV5
EV6
EV7
A
EV7
A
EV7
A
7-bit Master transmitter:
S
Address
A
Data1
Data2
DataN
P
.....
EV5
EV6 EV8
EV8
EV8
EV8
10-bit Slave receiver:
S
Header
A
Address
A
Data1
A
DataN
A
P
.....
EV1
EV2
EV2
EV4
10-bit Slave transmitter:
S
Header
A
Data1
A
A
DataN
....
.
A
P
r
EV1 EV3
EV6 EV8
EV3
EV3-1
EV4
10-bit Master transmitter
S
Header
A
Address
A
Data1
DataN
A
P
.....
EV5
EV9
EV8
A
EV8
A
10-bit Master receiver:
S
Header
A
Data1
DataN
P
r
.....
EV5
EV6
EV7
EV7
Legend: S=Start, S = Repeated Start, P=Stop, A=Acknowledge, NA=Non-acknowledge,
r
EVx=Event (with interrupt if ITE=1)
EV1: EVF=1, ADSL=1, cleared by reading SR1 register.
EV2: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register.
EV3: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register.
EV3-1: EVF=1, AF=1, BTF=1; AF is cleared by reading SR1 register. BTF is cleared by releasing the
lines (STOP=1, STOP=0) or by writing DR register (DR=FFh). Note: If lines are released by
STOP=1, STOP=0, the subsequent EV4 is not seen.
EV4: EVF=1, STOPF=1, cleared by reading SR2 register.
EV5: EVF=1, SB=1, cleared by reading SR1 register followed by writing DR register.
EV6: EVF=1, cleared by reading SR1 register followed by writing CR register (for example PE=1).
EV7: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register.
EV8: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register.
EV9: EVF=1, ADD10=1, cleared by reading SR1 register followed by writing DR register.
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2
I C BUS INTERFACE (Cont’d)
11.4.5 Low Power Modes
Mode
Description
2
No effect on I C interface.
WAIT
HALT
2
I C interrupts cause the device to exit from WAIT mode.
2
I C registers are frozen.
2
2
In HALT mode, the I C interface is inactive and does not acknowledge data on the bus. The I C interface
resumes operation when the MCU is woken up by an interrupt with “exit from HALT mode” capability.
11.4.6 Interrupts
Figure 46. Event Flags and Interrupt Generation
ADD10
ITE
BTF
ADSL
SB
INTERRUPT
EVF
AF
STOPF
ARLO
BERR
*
* EVF can also be set by EV6 or an error from the SR2 register.
Enable
Control from
Bit
Exit
Exit
from
Halt
Event
Flag
Interrupt Event
Wait
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
10-bit Address Sent Event (Master mode)
End of Byte Transfer Event
ADD10
BTF
No
No
No
No
No
No
No
No
Address Matched Event (Slave mode)
Start Bit Generation Event (Master mode)
Acknowledge Failure Event
ADSEL
SB
ITE
AF
Stop Detection Event (Slave mode)
Arbitration Lost Event (Multimaster configuration)
Bus Error Event
STOPF
ARLO
BERR
2
Note: The I C interrupt events are connected to
the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding
Enable Control Bitis set and the I-bit in the CC reg-
ister is reset (RIM instruction).
79/135
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2
I C BUS INTERFACE (Cont’d)
11.4.7 Register Description
2
Bit 2 = ACK Acknowledge enable.
This bit is set and cleared by software. It is also
cleared by hardware when the interface is disa-
bled (PE=0).
0: No acknowledge returned
1: Acknowledge returned after an address byte or
a data byte is received
I C CONTROL REGISTER (CR)
Read / Write
Reset Value: 0000 0000 (00h)
7
0
0
0
PE
ENGC START ACK STOP
ITE
Bit 1 = STOP Generation of a Stop condition.
This bit is set and cleared by software. It is also
cleared by hardware in master mode. Note: This
bit is not cleared when the interface is disabled
(PE=0).
Bit 7:6 = Reserved. Forced to 0 by hardware.
Bit 5 = PE Peripheral enable.
This bit is set and cleared by software.
0: Peripheral disabled
1: Master/Slave capability
Notes:
– When PE=0, all the bits of the CR register and
the SR register except the Stop bit are reset. All
outputs are released while PE=0
– In master mode:
0: No stop generation
1: Stop generation after the current byte transfer
or after the current Start condition is sent. The
STOP bit is cleared by hardware when the Stop
condition is sent.
– When PE=1, the corresponding I/O pins are se-
lected by hardware as alternate functions.
– In slave mode:
0: No stop generation
1: Release the SCL and SDA lines after the cur-
rent byte transfer (BTF=1). In this mode the
STOP bit has to be cleared by software.
2
– Toenable the I C interface, write the CR register
TWICE with PE=1 as the first write only activates
the interface (only PE is set).
Bit 4 = ENGC Enable General Call.
This bit is set and cleared by software. It is also
cleared by hardware when the interface is disa-
bled (PE=0). The 00h General Call address is ac-
knowledged (01h ignored).
Bit 0 = ITE Interrupt enable.
This bit is set and cleared by software and cleared
by hardware when the interface is disabled
(PE=0).
0: Interrupts disabled
1: Interrupts enabled
Refer to Figure 46 for the relationship between the
events and the interrupt.
SCL is held low when the ADD10, SB, BTF or
ADSL flags or an EV6 event (See Figure 45) is de-
tected.
0: General Call disabled
1: General Call enabled
Bit 3 = START Generation of a Start condition.
This bit is set and cleared by software. It is also
cleared by hardware when the interface is disa-
bled (PE=0) or when the Start condition is sent
(with interrupt generation if ITE=1).
– In master mode:
0: No start generation
1: Repeated start generation
– In slave mode:
0: No start generation
1: Start generation when the bus is free
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2
I C BUS INTERFACE (Cont’d)
2
I C STATUS REGISTER 1 (SR1)
arbitration (ARLO=1) or when the interface is disa-
bled (PE=0).
0: Data byte received (if BTF=1)
1: Data byte transmitted
Read Only
Reset Value: 0000 0000 (00h)
7
0
Bit 4 = BUSY Bus busy.
EVF ADD10 TRA BUSY BTF ADSL M/SL
SB
This bit is set by hardware on detection of a Start
condition and cleared by hardware on detection of
a Stop condition. It indicates a communication in
progress on the bus. This information is still updat-
ed when the interface is disabled (PE=0).
0: No communication on the bus
Bit 7 = EVF Event flag.
This bit is set by hardware as soon as an event oc-
curs. It is cleared by software reading SR2 register
in case of error event or as described in Figure 45.
It is also cleared by hardware when the interface is
disabled (PE=0).
1: Communication ongoing on the bus
Bit 3 = BTF Byte transfer finished.
0: No event
1: One of the following events has occurred:
This bit is set by hardware as soon as a byte is cor-
rectly received or transmitted with interrupt gener-
ation if ITE=1. It is cleared by software reading
SR1 register followed by a read or write of DR reg-
ister. It is also cleared by hardware when the inter-
face is disabled (PE=0).
– BTF=1 (Byte received or transmitted)
– ADSL=1 (Address matched in Slave mode
while ACK=1)
– SB=1 (Start condition generated in Master
mode)
– Following a byte transmission, this bit is set after
reception of the acknowledge clock pulse. In
case an address byte is sent, this bit is set only
after the EV6 event (See Figure 45). BTF is
cleared by reading SR1 register followed by writ-
ing the next byte in DR register.
– AF=1 (No acknowledge received after byte
transmission)
– STOPF=1 (Stop condition detected in Slave
mode)
– Following a byte reception, this bit is set after
transmission of the acknowledge clock pulse if
ACK=1. BTF is cleared by reading SR1 register
followed by reading the byte from DR register.
– ARLO=1 (Arbitration lost in Master mode)
– BERR=1 (Bus error, misplaced Start or Stop
condition detected)
– ADD10=1 (Master has sent header byte)
The SCL line is held low while BTF=1.
– Address byte successfully transmitted in Mas-
ter mode.
0: Byte transfer not done
1: Byte transfer succeeded
Bit 6 = ADD10 10-bit addressing in Master mode.
This bit is set by hardware when the master has
sent the first byte in 10-bit address mode. It is
cleared by software reading SR2 register followed
by a write in the DR register of the second address
byte. It is also cleared by hardware when the pe-
ripheral is disabled (PE=0).
Bit 2 = ADSL Address matched (Slave mode).
This bit is set by hardware as soon as the received
slave address matched with the OAR register con-
tent or a general call is recognized. An interrupt is
generated if ITE=1. It is cleared by software read-
ing SR1 register or by hardware when the inter-
face is disabled (PE=0).
0: No ADD10 event occurred.
1: Master has sent first address byte (header)
The SCL line is held low while ADSL=1.
0: Address mismatched or not received
1: Received address matched
Bit 5 = TRA Transmitter/Receiver.
When BTF is set, TRA=1 if a data byte has been
transmitted. It is cleared automatically when BTF
is cleared. It is also cleared by hardware after de-
tection of Stop condition (STOPF=1), loss of bus
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2
I C BUS INTERFACE (Cont’d)
Bit 1 = M/SL Master/Slave.
Bit 2 = ARLO Arbitration lost.
This bit is set by hardware as soon as the interface
is in Master mode (writing START=1). It is cleared
by hardware after detecting a Stop condition on
the bus or a loss of arbitration (ARLO=1). It is also
cleared when the interface is disabled (PE=0).
0: Slave mode
This bit is set by hardware when the interface los-
es the arbitration of the bus to another master. An
interrupt is generated if ITE=1. It is cleared by soft-
ware reading SR2 register or by hardware when
the interface is disabled (PE=0).
After an ARLO event the interface switches back
automatically to Slave mode (M/SL=0).
1: Master mode
The SCL line is not held low while ARLO=1.
Bit 0 = SB Start bit (Master mode).
This bit is set by hardware as soon as the Start
condition is generated (following
0: No arbitration lost detected
1: Arbitration lost detected
a
write
START=1). An interrupt is generated if ITE=1. It is
cleared by software reading SR1 register followed
by writing the address byte in DRregister. It is also
cleared by hardware when the interface is disa-
bled (PE=0).
0: No Start condition
1: Start condition generated
Bit 1 = BERR Bus error.
This bit is set by hardware when the interface de-
tects a misplaced Start or Stop condition. An inter-
rupt is generated if ITE=1. It is cleared by software
reading SR2 register or by hardware when the in-
terface is disabled (PE=0).
The SCL line is not held low while BERR=1.
2
I C STATUS REGISTER 2 (SR2)
0: No misplaced Start or Stop condition
1: Misplaced Start or Stop condition
Read Only
Reset Value: 0000 0000 (00h)
7
0
0
Bit 0 = GCAL General Call (Slave mode).
This bit is set by hardware when a general call ad-
dress is detected on the bus while ENGC=1. It is
cleared by hardware detecting a Stop condition
(STOPF=1) or when the interface is disabled
(PE=0).
0
0
AF STOPF ARLO BERR GCAL
Bit 7:5 = Reserved. Forced to 0 by hardware.
0: No general call address detected on bus
1: general call address detected on bus
Bit 4 = AF Acknowledge failure.
This bit is set by hardware when no acknowledge
is returned. An interrupt is generated if ITE=1. It is
cleared by software reading SR2 register or by
hardware when the interface is disabled (PE=0).
The SCL line is not held low while AF=1.
0: No acknowledge failure
1: Acknowledge failure
Bit 3 = STOPF Stop detection (Slave mode).
This bit is set by hardware when a Stop condition
is detected on the bus after an acknowledge (if
ACK=1). An interrupt is generated if ITE=1. It is
cleared by software reading SR2 register or by
hardware when the interface is disabled (PE=0).
The SCL line is not held low while STOPF=1.
0: No Stop condition detected
1: Stop condition detected
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ST72104G, ST72215G, ST72216G, ST72254G
2
I C BUS INTERFACE (Cont’d)
2
I C CLOCK CONTROL REGISTER (CCR)
2
Read / Write
I C DATA REGISTER (DR)
Reset Value: 0000 0000 (00h)
Read / Write
Reset Value: 0000 0000 (00h)
7
0
7
0
FM/SM CC6
CC5
CC4
CC3
CC2
CC1
CC0
D7
D6
D5
D4
D3
D2
D1
D0
2
Bit 7 = FM/SM Fast/Standard I C mode.
This bit is set and cleared by software. It is not
cleared when the interface is disabled (PE=0).
2
Bit 7:0 = D7-D0 8-bit Data Register.
These bits contain the byte to be received or trans-
mitted on the bus.
0: Standard I C mode
2
1: Fast I C mode
– Transmitter mode: Byte transmission start auto-
matically when the software writes in the DR reg-
ister.
Bit 6:0 = CC6-CC0 7-bit clock divider.
These bits select the speed of the bus (F
) de-
SCL
2
pending on the I C mode. They are not cleared
when the interface is disabled (PE=0).
– Receiver mode: the first data byte is received au-
tomatically in the DR register using the least sig-
nificant bit of the address.
Then, the following data bytes are received one
by one after reading the DR register.
– Standard mode (FM/SM=0): F
<= 100kHz
SCL
F
= F
/(2x([CC6..CC0]+2))
SCL
CPU
– Fast mode (FM/SM=1): F
> 100kHz
SCL
F
= F
/(3x([CC6..CC0]+2))
SCL
CPU
Note: The programmed F
SCL and SDA lines.
assumes no load on
SCL
83/135
ST72104G, ST72215G, ST72216G, ST72254G
2
I C BUS INTERFACE (Cont’d)
2
2
I C OWN ADDRESS REGISTER (OAR1)
I C OWN ADDRESS REGISTER (OAR2)
Read / Write
Reset Value: 0000 0000 (00h)
Read / Write
Reset Value: 0100 0000 (40h)
7
0
7
0
0
ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0
FR1
FR0
0
0
0
ADD9 ADD8
7-bit Addressing Mode
Bit 7:6 = FR1-FR0 Frequency bits.
Bit 7:1 = ADD7-ADD1 Interface address.
These bits define the I C bus address of the inter-
face. They are not cleared when the interface is
disabled (PE=0).
These bits are set by software only when the inter-
face is disabled(PE=0). To configure the interface
2
2
to I C specifed delays select the value corre-
sponding to the microcontroller frequency F
.
CPU
F
Range (MHz)
2.5 - 6
FR1
0
FR0
CPU
Bit 0 = ADD0 Address direction bit.
This bit is don’t care, the interface acknowledges
either 0 or 1. It is not cleared when the interface is
disabled (PE=0).
0
1
0
1
6 -10
0
10 - 14
1
14 - 24
1
Note: Address 01h is always ignored.
Bit 5:3 = Reserved
Bit 2:1 = ADD9-ADD8 Interface address.
These are the most significant bits of the I C bus
address of the interface (10-bit mode only). They
are not cleared when the interface is disabled
(PE=0).
10-bit Addressing Mode
Bit 7:0 = ADD7-ADD0 Interface address.
These are the least significant bits of the I C bus
address of the interface. They are not cleared
when the interface is disabled (PE=0).
2
2
Bit 0 = Reserved.
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ST72104G, ST72215G, ST72216G, ST72254G
I C BUS INTERFACE (Cont’d)
2
Table 17. I C Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
I2CCR
Reset Value
PE
0
ENGC
0
START
0
ACK
0
STOP
0
ITE
0
0028h
0029h
002Ah
02Bh
0
0
I2CSR1
Reset Value
EVF
0
ADD10
0
TRA
0
BUSY
0
BTF
0
ADSL
0
M/SL
0
SB
0
I2CSR2
Reset Value
AF
0
STOPF
0
ARLO
0
BERR
0
GCAL
0
0
0
0
I2CCCR
Reset Value
FM/SM
0
CC6
0
CC5
0
CC4
0
CC3
0
CC2
0
CC1
0
CC0
0
I2COAR1
Reset Value
ADD7
0
ADD6
0
ADD5
0
ADD4
0
ADD3
0
ADD2
0
ADD1
0
ADD0
0
02Ch
I2COAR2
Reset Value
FR1
0
FR0
1
ADD9
0
ADD8
0
002Dh
002Eh
0
0
0
0
0
0
0
I2CDR
Reset Value
MSB
0
LSB
0
0
0
0
85/135
ST72104G, ST72215G, ST72216G, ST72254G
11.5 8-BIT A/D CONVERTER (ADC)
11.5.1 Introduction
11.5.3 Functional Description
11.5.3.1 Analog Power Supply
The on-chip Analog to Digital Converter (ADC) pe-
ripheral is a 8-bit, successive approximation con-
verter with internal sample and hold circuitry. This
peripheral has up to 16 multiplexed analog input
channels (refer to device pin out description) that
allow the peripheral to convert the analog voltage
levels from up to 16 different sources.
V
and V
are the high and low level refer-
SSA
DDA
ence voltage pins. In some devices (refer to device
pin out description) they are internally connected
to the V and V pins.
DD
SS
Conversion accuracy may therefore be impacted
by voltage drops and noise in the event of heavily
loaded or badly decoupled power supply lines.
The result of the conversion is stored in a 8-bit
Data Register. The A/D converter is controlled
through a Control/Status Register.
See electrical characteristics section for more de-
tails.
11.5.2 Main Features
■ 8-bit conversion
■ Up to 16 channels with multiplexed input
■ Linear successive approximation
■ Data register (DR) which contains the results
■ Conversion complete status flag
■ On/off bit (to reduce consumption)
The block diagram is shown in Figure 47.
Figure 47. ADC Block Diagram
f
f
ADC
CPU
DIV 2
COCO
0
ADON
4
0
CH3 CH2 CH1 CH0
ADCCSR
AIN0
AIN1
HOLD CONTROL
R
ADC
ANALOG TO DIGITAL
CONVERTER
ANALOG
MUX
AINx
C
ADC
ADCDR
D7
D6
D5
D4 D3
D2
D1
D0
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ST72104G, ST72215G, ST72216G, ST72254G
8-BIT A/D CONVERTER (ADC) (Cont’d)
11.5.3.2 Digital A/D Conversion Result
The analog input ports must be configured as in-
put, no pull-up, no interrupt. Refer to the «I/O
ports» chapter. Using these pins as analog inputs
does not affect the ability of the port to be read as
a logic input.
The conversion is monotonic, meaning that the re-
sult never decreases if the analog input does not
and never increases if the analog input does not.
If the input voltage (V ) is greater than or equal
AIN
In the CSR register:
to V
(high-level voltage reference) then the
DDA
conversion result in the DR register is FFh (full
scale) without overflow indication.
– Select the CH[3:0] bits to assign the analog
channel to be converted.
ADC Conversion
If input voltage (V ) is lower than or equal to
AIN
V
(low-level voltage reference) then the con-
SSA
In the CSR register:
version result in the DR register is 00h.
– Set the ADON bit to enable the A/D converter
and to start the first conversion. From this time
on, the ADC performs a continuous conver-
sion of the selected channel.
The A/D converter is linear and the digital result of
the conversion is stored in the ADCDR register.
The accuracy of the conversion is described in the
parametric section.
When a conversion is complete
– The COCO bit is set by hardware.
– No interrupt is generated.
– The result is in the DR register and remains
valid until the next conversion has ended.
A write to the CSR register (with ADON set) aborts
the current conversion, resets the COCO bit and
starts a new conversion.
R
is the maximum recommended impedance
AIN
for an analog input signal. If the impedance is too
high, this will result in a loss of accuracy due to
leakage and sampling not being completed in the
alloted time.
11.5.3.3 A/D Conversion Phases
The A/D conversion is based on two conversion
phases as shown in Figure 48:
Figure 48. ADC Conversion Timings
■ Sample capacitor loading [duration: t
]
LOAD
During this phase, the V
input voltage to be
AIN
ADON
measured is loaded into the C
capacitor.
sample
ADC
ADCCSR WRITE
OPERATION
t
CONV
■ A/D conversion [duration: t
]
CONV
During this phase, the A/D conversion is
computed (8 successive approximations cycles)
HOLD
CONTROL
and the C
sample capacitor is disconnected
ADC
from the analog input pin to get the optimum
analog to digital conversion accuracy.
t
LOAD
COCO BIT SET
While the ADC is on, these two phases are contin-
uously repeated.
11.5.4 Low Power Modes
At the end of each conversion, the sample capaci-
tor is kept loaded with the previous measurement
load. The advantage of this behaviour is that it
minimizes the current consumption on the analog
pin in case of single input channel measurement.
Mode
WAIT
Description
No effect on A/D Converter
A/D Converter disabled.
After wakeup from Halt mode, the A/D Con-
verter requires a stabilisation time before ac-
curate conversions can be performed.
HALT
11.5.3.4 Software Procedure
Refer to the control/status register (CSR) and data
register (DR) in Section 11.5.6 for the bit defini-
tions and to Figure 48 for the timings.
Note: The A/D converter may be disabled by reset-
ting the ADON bit. This feature allows reduced
power consumption when no conversion is needed
and between single shot conversions.
ADC Configuration
The total duration of the A/D conversion is 12 ADC
11.5.5 Interrupts
clock periods (1/f
=2/f
).
ADC
CPU
None
87/135
ST72104G, ST72215G, ST72216G, ST72254G
8-BIT A/D CONVERTER (ADC) (Cont’d)
11.5.6 Register Description
CONTROL/STATUSREGISTER (CSR)
Read/Write
DATA REGISTER (DR)
Read Only
Reset Value: 0000 0000 (00h)
Reset Value: 0000 0000 (00h)
7
0
7
0
COCO
0
ADON
0
CH3
CH2
CH1
CH0
D7
D6
D5
D4
D3
D2
D1
D0
Bit 7 = COCO Conversion Complete
This bit is set by hardware. It is cleared by soft-
ware readingthe result in the DR register or writing
to the CSR register.
0: Conversion is not complete
1: Conversion can be read from the DR register
Bit 7:0 = D[7:0] Analog Converted Value
This register contains the converted analog value
in the range 00h to FFh.
Note: Reading this register reset the COCO flag.
Bit 6 = Reserved. must always be cleared.
Bit 5 = ADON A/D Converter On
This bit is set and cleared by software.
0: A/D converter is switched off
1: A/D converter is switched on
Bit 4 = Reserved. must always be cleared.
Bit 3:0 = CH[3:0] Channel Selection
These bits are set and cleared by software. They
select the analog input to convert.
Channel Pin*
CH3 CH2 CH1 CH0
AIN0
AIN1
AIN2
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
AIN10
AIN11
AIN12
AIN13
AIN14
AIN15
*Note: The number of pins AND the channel selec-
tion varies accordingto the device. Refer to the de-
vice pinout.
88/135
ST72104G, ST72215G, ST72216G, ST72254G
8-BIT A/D CONVERTER (ADC) (Cont’d)
Table 18. ADC Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
ADCDR
Reset Value
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
0070h
0071h
ADCCSR
Reset Value
COCO
0
ADON
0
CH3
0
CH2
0
CH1
0
CH0
0
0
0
89/135
ST72104G, ST72215G, ST72216G, ST72254G
12 INSTRUCTION SET
12.1 ST7 ADDRESSING MODES
so, most of the addressing modes may be subdi-
vided in two sub-modes called long and short:
The ST7 Core features 17 different addressing
modes which can be classified in 7 main groups:
– Long addressing mode is more powerful be-
cause itcan use the full 64 Kbyte address space,
however it uses more bytes and more CPU cy-
cles.
Addressing Mode
Inherent
Example
nop
– Short addressing mode is less powerful because
it can generally only access page zero (0000h -
00FFh range), but the instruction size is more
compact, and faster. All memory to memory in-
structions use short addressing modes only
(CLR, CPL, NEG, BSET, BRES, BTJT, BTJF,
INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP)
Immediate
Direct
ld A,#$55
ld A,$55
ld A,($55,X)
ld A,([$55],X)
jrne loop
Indexed
Indirect
Relative
Bit operation
bset byte,#5
The ST7 Assembler optimizes the use of long and
short addressing modes.
The ST7 Instruction set is designed to minimize
the number of bytes required per instruction: To do
Table 19. ST7 Addressing Mode Overview
Pointer Pointer
Destination/
Source
Length
(Bytes)
Mode
Syntax
Address
(Hex.)
Size
(Hex.)
Inherent
Immediate
Short
nop
+ 0
+ 1
+ 1
+ 2
ld A,#$55
ld A,$10
Direct
Direct
00..FF
Long
ld A,$1000
0000..FFFF
+ 0 (with X register)
+ 1 (with Y register)
No Offset
Direct
Indexed
ld A,(X)
00..FF
Short
Long
Short
Long
Short
Long
Relative
Relative
Bit
Direct
Indexed
Indexed
ld A,($10,X)
ld A,($1000,X)
ld A,[$10]
00..1FE
+ 1
+ 2
+ 2
+ 2
+ 2
+ 2
+ 1
+ 2
+ 1
+ 2
+ 2
+ 3
Direct
0000..FFFF
00..FF
Indirect
Indirect
Indirect
Indirect
Direct
00..FF
00..FF
00..FF
00..FF
byte
word
byte
word
ld A,[$10.w]
ld A,([$10],X)
0000..FFFF
00..1FE
Indexed
Indexed
ld A,([$10.w],X) 0000..FFFF
1)
1)
jrne loop
PC-128/PC+127
Indirect
Direct
jrne [$10]
PC-128/PC+127
00..FF
00..FF
00..FF
00..FF
byte
byte
byte
bset $10,#7
bset [$10],#7
Bit
Indirect
Direct
00..FF
Bit
Relative
Relative
btjt $10,#7,skip 00..FF
btjt [$10],#7,skip 00..FF
Bit
Indirect
Note 1. At the time the instruction is executed, the Program Counter (PC) points to the instruction follow-
ing JRxx.
90/135
ST72104G, ST72215G, ST72216G, ST72254G
12.1.3 Direct
ST7 ADDRESSING MODES (Cont’d)
12.1.1 Inherent
All Inherent instructions consist of a single byte.
The opcode fully specifies all the required informa-
tion for the CPU to process the operation.
In Direct instructions, the operands are referenced
by their memory address.
The direct addressing mode consists of two sub-
modes:
Inherent Instruction
Function
No operation
Direct (short)
NOP
The address is a byte, thus requires only one byte
after the opcode, but only allows 00 - FF address-
ing space.
TRAP
S/W Interrupt
Wait For Interrupt (Low Power
Mode)
WFI
Direct (long)
Halt Oscillator (Lowest Power
Mode)
HALT
The address is a word, thus allowing 64 Kbyte ad-
dressing space, but requires 2 bytes after the op-
code.
RET
Sub-routine Return
Interrupt Sub-routine Return
Set Interrupt Mask
Reset Interrupt Mask
Set Carry Flag
IRET
SIM
12.1.4 Indexed (No Offset, Short, Long)
RIM
In this mode, the operand is referenced by its
memory address, which is defined by the unsigned
addition of an index register (X or Y) with an offset.
SCF
RCF
Reset Carry Flag
Reset Stack Pointer
Load
The indirect addressing mode consists of three
sub-modes:
RSP
LD
Indexed (No Offset)
CLR
Clear
There is no offset, (no extra byte after the opcode),
and allows 00 - FF addressing space.
PUSH/POP
INC/DEC
TNZ
Push/Pop to/from the stack
Increment/Decrement
Test Negative or Zero
1 or 2 Complement
Byte Multiplication
Indexed (Short)
The offset is a byte, thus requires only one byte af-
ter the opcode and allows 00 - 1FE addressing
space.
CPL, NEG
MUL
Indexed (long)
SLL, SRL, SRA, RLC,
RRC
Shift and Rotate Operations
Swap Nibbles
The offset is a word, thus allowing 64 Kbyte ad-
dressing space and requires 2 bytes after the op-
code.
SWAP
12.1.2 Immediate
Immediate instructions have two bytes, the first
byte contains the opcode, the second byte con-
tains the operand value.
12.1.5 Indirect (Short, Long)
The required data byte to do the operation is found
by its memory address, located in memory (point-
er).
Immediate Instruction
Function
The pointer address follows the opcode. The indi-
rect addressing mode consists of two sub-modes:
LD
Load
CP
Compare
Indirect (short)
BCP
Bit Compare
The pointer address is a byte, the pointer size is a
byte, thus allowing 00 - FF addressing space, and
requires 1 byte after the opcode.
AND, OR, XOR
ADC, ADD, SUB, SBC
Logical Operations
Arithmetic Operations
Indirect (long)
The pointer address is a byte, the pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.
91/135
ST72104G, ST72215G, ST72216G, ST72254G
ST7 ADDRESSING MODES (Cont’d)
12.1.6 Indirect Indexed (Short, Long)
12.1.7 Relative mode (Direct, Indirect)
This is a combination of indirect and short indexed
addressing modes. The operand is referenced by
its memory address, which is defined by the un-
signed addition of an index register value (X or Y)
with a pointer value located in memory. The point-
er address follows the opcode.
This addressing mode is used to modify the PC
register value, by adding an 8-bit signed offset to
it.
Available Relative Direct/
Function
Indirect Instructions
JRxx
Conditional Jump
Call Relative
The indirect indexed addressing mode consists of
two sub-modes:
CALLR
Indirect Indexed (Short)
The pointer address is a byte, the pointer size is a
byte, thus allowing 00 - 1FE addressing space,
and requires 1 byte after the opcode.
The relative addressing mode consists of two sub-
modes:
Relative (Direct)
The offset follows the opcode.
Relative (Indirect)
Indirect Indexed (Long)
The pointer address is a byte, the pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.
The offset is defined in memory, of which the ad-
dress follows the opcode.
Table 20. Instructions Supporting Direct,
Indexed, Indirect and Indirect Indexed
Addressing Modes
Long and Short
Function
Instructions
LD
Load
CP
Compare
AND, OR, XOR
Logical Operations
Arithmetic Addition/subtrac-
tion operations
ADC, ADD, SUB, SBC
BCP
Bit Compare
Short Instructions Only
CLR
Function
Clear
INC, DEC
Increment/Decrement
Test Negative or Zero
1 or 2 Complement
Bit Operations
TNZ
CPL, NEG
BSET, BRES
Bit Test and Jump Opera-
tions
BTJT, BTJF
SLL, SRL, SRA, RLC,
RRC
Shift and Rotate Operations
SWAP
Swap Nibbles
CALL, JP
Call or Jump subroutine
92/135
ST72104G, ST72215G, ST72216G, ST72254G
12.2 INSTRUCTION GROUPS
The ST7 family devices use an Instruction Set
consisting of 63 instructions. The instructions may
be subdivided into 13 main groups as illustrated in
the following table:
Load and Transfer
LD
CLR
Stack operation
PUSH
INC
POP
DEC
TNZ
OR
RSP
Increment/Decrement
Compare and Tests
Logical operations
CP
BCP
XOR
AND
BSET
BTJT
ADC
SLL
CPL
NEG
Bit Operation
BRES
BTJF
ADD
SRL
JRT
Conditional Bit Test and Branch
Arithmetic operations
Shift and Rotates
SUB
SRA
JRF
SBC
RLC
JP
MUL
RRC
CALL
SWAP
CALLR
SLA
Unconditional Jump or Call
Conditional Branch
JRA
JRxx
TRAP
SIM
NOP
RET
Interruption management
Code Condition Flag modification
WFI
RIM
HALT
SCF
IRET
RCF
Using a pre-byte
The instructions are described with one to four
bytes.
These prebytes enable instruction in Y as well as
indirect addressing modes to be implemented.
They precede the opcode of the instruction in X or
the instruction using direct addressing mode. The
prebytes are:
In order to extend the number of available op-
codes for an 8-bit CPU (256 opcodes), three differ-
ent prebyte opcodes are defined. These prebytes
modify the meaning of the instruction they pre-
cede.
PDY 90
Replace an X based instruction
using immediate, direct, indexed, or inherent ad-
dressing mode by a Y one.
The whole instruction becomes:
PIX 92
Replace an instruction using di-
PC-2
PC-1
PC
End of previous instruction
Prebyte
rect, direct bit, or direct relative addressing mode
to an instruction using the corresponding indirect
addressing mode.
It also changes an instruction using X indexed ad-
dressing mode to an instruction using indirect X in-
dexed addressing mode.
opcode
PC+1
Additional word (0 to 2) according
to the number of bytes required to compute the ef-
fective address
PIY 91
Replace an instruction using X in-
direct indexed addressing mode by a Y one.
93/135
ST72104G, ST72215G, ST72216G, ST72254G
INSTRUCTION GROUPS (Cont’d)
Mnemo
ADC
ADD
AND
BCP
Description
Add with Carry
Function/Example
A = A + M + C
A = A + M
Dst
Src
H
H
H
I
N
N
N
N
N
Z
Z
Z
Z
Z
C
C
C
A
M
M
M
M
Addition
A
Logical And
A = A . M
A
Bit compare A, Memory
Bit Reset
tst (A . M)
A
BRES
BSET
BTJF
BTJT
CALL
CALLR
CLR
bres Byte, #3
bset Byte, #3
btjf Byte, #3, Jmp1
btjt Byte, #3, Jmp1
M
M
M
M
Bit Set
Jump if bit is false (0)
Jump if bit is true (1)
Call subroutine
Call subroutine relative
Clear
C
C
reg, M
reg
0
N
N
N
1
Z
Z
Z
CP
Arithmetic Compare
One Complement
Decrement
tst(Reg - M)
A = FFH-A
dec Y
M
C
1
CPL
reg, M
reg, M
DEC
HALT
IRET
INC
Halt
0
I
Interrupt routine return
Increment
Pop CC, A, X, PC
inc X
H
N
N
Z
Z
C
reg, M
JP
Absolute Jump
Jump relative always
Jump relative
jp [TBL.w]
JRA
JRT
JRF
Never jump
jrf *
JRIH
JRIL
Jump if ext. interrupt = 1
Jump if ext. interrupt = 0
Jump if H = 1
JRH
H = 1 ?
JRNH
JRM
Jump if H = 0
H = 0 ?
Jump if I = 1
I = 1 ?
JRNM
JRMI
JRPL
JREQ
JRNE
JRC
Jump if I = 0
I = 0 ?
Jump if N = 1 (minus)
Jump if N = 0 (plus)
Jump if Z = 1 (equal)
Jump if Z = 0 (not equal)
Jump if C = 1
N = 1 ?
N = 0 ?
Z = 1 ?
Z = 0 ?
C = 1 ?
JRNC
JRULT
Jump if C = 0
C = 0 ?
Jump if C = 1
Unsigned <
Jmp if unsigned >=
Unsigned >
JRUGE Jump if C = 0
JRUGT Jump if (C + Z = 0)
94/135
ST72104G, ST72215G, ST72216G, ST72254G
INSTRUCTION GROUPS (Cont’d)
Mnemo
JRULE
LD
Description
Jump if (C + Z = 1)
Load
Function/Example
Unsigned <=
dst <= src
Dst
Src
H
I
N
N
N
N
N
Z
Z
Z
Z
Z
C
reg, M
A, X, Y
reg, M
M, reg
MUL
NEG
NOP
OR
Multiply
X,A = X * A
X, Y, A
0
0
Negate (2’s compl)
No Operation
OR operation
Pop from the Stack
neg $10
C
A = A + M
pop reg
pop CC
push Y
C = 0
A
M
POP
reg
CC
M
M
M
H
I
C
0
PUSH
RCF
RET
RIM
Push onto the Stack
Reset carry flag
Subroutine Return
Enable Interrupts
Rotate left true C
Rotate right true C
Reset Stack Pointer
Subtract with Carry
Set carry flag
reg, CC
I = 0
0
RLC
RRC
RSP
SBC
SCF
SIM
C <= Dst <= C
C => Dst => C
S = Max allowed
A = A - M - C
C = 1
reg, M
reg, M
N
N
Z
Z
C
C
A
M
N
Z
C
1
Disable Interrupts
Shift left Arithmetic
Shift left Logic
I = 1
1
SLA
C <= Dst <= 0
C <= Dst <= 0
0 => Dst => C
Dst7 => Dst => C
A = A - M
reg, M
reg, M
reg, M
reg, M
A
N
N
0
Z
Z
Z
Z
Z
Z
Z
C
C
C
C
C
SLL
SRL
SRA
SUB
SWAP
TNZ
TRAP
WFI
Shift right Logic
Shift right Arithmetic
Subtraction
N
N
N
N
M
SWAP nibbles
Dst[7..4] <=> Dst[3..0] reg, M
tnz lbl1
Test for Neg & Zero
S/W trap
S/W interrupt
1
0
Wait for Interrupt
Exclusive OR
XOR
A = A XOR M
A
M
N
Z
95/135
ST72104G, ST72215G, ST72216G, ST72254G
13 ELECTRICAL CHARACTERISTICS
13.1 PARAMETER CONDITIONS
Unless otherwise specified, all voltages are re-
13.1.5 Pin input voltage
ferred to V
.
SS
The input voltage measurement on a pin of the de-
vice is described in Figure 50.
13.1.1 Minimum and Maximum values
Unless otherwise specified the minimum and max-
imum values are guaranteed in the worst condi-
tions of ambient temperature, supply voltage and
frequencies by tests in production on 100% of the
Figure 50. Pin input voltage
devices with an ambient temperature at T =25°C
A
ST7 PIN
and T =T max (given by the selected temperature
A
A
range).
V
Data based on characterization results, design
simulation and/or technology characteristics are
indicated in the table footnotes and are not tested
in production. Based on characterization, the min-
imum and maximum values refer to sample tests
and represent the mean value plus or minus three
times the standard deviation (mean±3Σ).
IN
13.1.2 Typical values
Unless otherwise specified, typical data are based
on T =25°C, V =5V (for the 4.5V≤V ≤5.5V
A
DD
DD
voltage range) and V =3.3V (for the 3V≤V ≤4V
DD
DD
voltage range). They are given only as design
guidelines and are not tested.
13.1.3 Typical curves
Unless otherwise specified, all typical curves are
given only as design guidelines and are not tested.
13.1.4 Loading capacitor
The loading conditions used for pin parameter
measurement are shown in Figure 49.
Figure 49. Pin loading conditions
ST7 PIN
C
L
96/135
ST72104G, ST72215G, ST72216G, ST72254G
13.2 ABSOLUTE MAXIMUM RATINGS
Stresses above those listed as “absolute maxi-
mum ratings” may cause permanent damage to
the device. This is a stress rating only and func-
tional operation of the device under these condi-
tions is not implied. Exposure to maximum rating
conditions for extended periods may affect device
reliability.
13.2.1 Voltage Characteristics
Symbol
Ratings
Maximum value
6.5
Unit
V
- V
Supply voltage
DD
SS
V
1) & 2)
V
Input voltage on any pin
VSS-0.3 to VDD+0.3
IN
V
Electro-static discharge voltage (Human Body Model)
Electro-static discharge voltage (Machine Model)
see Section 13.7.2 ”Absolute Elec-
trical Sensitivity” on page 110
ESD(HBM)
V
ESD(MM)
13.2.2 Current Characteristics
Symbol
Ratings
Maximum value
Unit
3)
3)
I
Total current into V
power lines (source)
DD
80
80
VDD
I
Total current out of V ground lines (sink)
SS
VSS
Output current sunk by any standard I/O and control pin
Output current sunk by any high sink I/O pin
Output current source by any I/Os and control pin
Injected current on ISPSEL pin
25
I
50
IO
- 25
± 5
± 5
± 5
± 5
± 20
mA
Injected current on RESET pin
2) & 4)
I
INJ(PIN)
Injected current on OSC1 and OSC2 pins
5) & 6)
Injected current on any other pin
2)
5)
ΣI
Total injected current (sum of all I/O and control pins)
INJ(PIN)
13.2.3 Thermal Characteristics
Symbol
Ratings
Value
Unit
T
Storage temperature range
Maximum junction temperature
(see Section 14.2 ”THERMAL CHARACTERISTICS” on page 127 )
-65 to +150
°C
STG
T
J
Notes:
1. Directly connecting the RESET and I/O pins to V or V could damage the device if an unintentional internal reset
DD
SS
is generated or an unexpected change of the I/O configuration occurs (for example, due to a corrupted program counter).
To guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7kΩ for
RESET, 10kΩ for I/Os). Unused I/O pins must be tied in the same way to V orV according to their reset configuration.
DD
SS
2. When the current limitation is not possible, the V absolute maximum rating must be respected, otherwise refer to
IN
I
specification. A positive injection is induced by V >V while a negative injection is induced by V <V
.
INJ(PIN)
IN
DD
IN
SS
3. All power (V ) and ground (V ) lines must always be connected to the external supply.
DD
SS
4. Negative injection disturbs the analog performance of the device. In particular, it induces leakage currents throughout
the device including the analog inputs. To avoid undesirable effects on the analog functions, care must be taken:
- Analog input pins must have a negative injection less than 0.8 mA (assuming that the impedance of the analog voltage
is lower than the specified limits)
- Pure digital pins must have a negative injection less than 1.6mA. In addition, it is recommended to inject the current as
far as possible from the analog input pins.
5. When several inputs are submitted to a current injection, the maximum ΣI
is the absolute sum of the positive
INJ(PIN)
and negative injected currents (instantaneous values). These results are based on characterisation with ΣI
maxi-
INJ(PIN)
mum current injection on four I/O port pins of the device.
6. True open drain I/O port pins do not accept positive injection.
97/135
ST72104G, ST72215G, ST72216G, ST72254G
13.3 OPERATING CONDITIONS
13.3.1 General Operating Conditions
Symbol
Parameter
Supply voltage
Conditions
Min
Max
Unit
V
see Figure 51 and Figure 52
3.0
5.5
V
DD
V
V
≥3.5V for ROM devices
≥4.5V for FLASH devices
1)
DD
DD
0
16
f
External clock frequency
MHz
OSC
1)
V
≥3.0V
0
8
DD
1 Suffix Version
6 Suffix Version
7 Suffix Version
3 Suffix Version
0
70
-40
-40
-40
85
T
Ambient temperature range
°C
A
105
125
2)
Figure 51. f
Maximum Operating Frequency Versus VDD Supply Voltage for ROM devices
OSC
f
[MHz]
FUNCTIONALITY
GUARANTEED
IN THIS AREA
OSC
16
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
8
4
1)
WITH RESONATOR
1
0
SUPPLY VOLTAGE [V]
2)
2.5
3
3.5
4
4.5
5
5.5
Figure 52. f
Maximum Operating Frequency Versus VDD Supply Voltage for FLASH devices
OSC
FUNCTIONALITY NOT GUARANTEED IN THIS AREA
3)
FOR TEMPERATURE HIGHER THAN 85°C
f
[MHz]
OSC
FUNCTIONALITY
GUARANTEED
IN THIS AREA
3)
16
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
8
4
1)
WITH RESONATOR
1
0
SUPPLY VOLTAGE [V]
2.5
3
3.5
3.85
4
4.5
5
5.5
Notes:
1. Guaranteed by construction. A/D operation and resonator oscillator start-up are not guaranteed below 1MHz.
2. Operating conditions with T =-40 to +125°C.
A
3. FLASH programming tested in production at maximum T with two different conditions: V =5.5V, f =8MHz and
CPU
A
DD
V
=3V, f
=4MHz.
CPU
DD
98/135
ST72104G, ST72215G, ST72216G, ST72254G
OPERATING CONDITIONS (Cont’d)
13.3.2 Operating Conditions with Low Voltage Detector (LVD)
Subject to general operating conditions for V , f , and T .
DD OSC
Conditions
High Threshold
Med. Threshold
Low Threshold
A
1)
Symbol
Parameter
Min
Typ
Max
Unit
2)
4.10
3.75
3.25
4.30
3.90
3.35
4.50
4.05
3.45
Reset release threshold
2)
2)
V
IT+
(V rise)
DD
V
High Threshold
Med. Threshold
Low Threshold
3.85
3.50
3.00
4.05
3.65
3.10
4.25
3.80
3.20
Reset generation threshold
V
V
IT-
(V fall)
DD
LVD voltage threshold hysteresis
V
-V
IT+ IT-
200
0.2
250
300
50
mV
V/ms
ns
hyst
3)
Vt
V
rise time rate
DD
POR
2)
t
Filtered glitch delay on V
Not detected by the LVD
40
g(VDD)
DD
3)
Figure 53. High LVD Threshold Versus VDD and f
for FLASH devices
OSC
FUNCTIONALITY AND RESET NOT GUARANTEED IN THIS AREA
FOR TEMPERATURES HIGHER THAN 85°C
f
[MHz]
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
OSC
16
DEVICE UNDER
RESET
IN THIS AREA
FUNCTIONAL AREA
8
0
SUPPLY VOLTAGE [V]
V
≥3.85
IT-
2.5
3
3.5
4
4.5
5
5.5
3)
Figure 54. Medium LVD Threshold Versus VDD and f
for FLASH devices
OSC
FUNCTIONALITY AND RESET NOT GUARANTEED IN THIS AREA
FOR TEMPERATURES HIGHER THAN 85°C
f
[MHz]
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
OSC
16
DEVICE UNDER
RESET
IN THIS AREA
FUNCTIONAL AREA
8
0
SUPPLY VOLTAGE [V]
2.5
3
V
IT-≥3.5V
4
4.5
5
5.5
2)
Figure 55. Low LVD Threshold Versus VDD and f
for FLASH devices
OSC
FUNCTIONALITY NOT GUARANTEED IN THIS AREA
FOR TEMPERATURES HIGHER THAN 85°C
f
[MHz]
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
OSC
16
DEVICE UNDER
RESET
IN THIS AREA
FUNCTIONAL AREA
8
0
SUPPLY VOLTAGE [V]
2.5
V
IT-≥3V
3.5
4
4.5
5
5.5
Notes:
1. LVD typical data are based on T =25°C. They are given only as design guidelines and are not tested.
A
2. Data based on characterization results, not tested in production.
3. The V rise time rate condition isneeded to insure a correct device power-on and LVD reset. Not tested in production.
DD
99/135
ST72104G, ST72215G, ST72216G, ST72254G
FUNCTIONAL OPERATING CONDITIONS (Cont’d)
2)
Figure 56. High LVD Threshold Versus VDD and f
for ROM devices
OSC
f
[MHz]
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
OSC
16
DEVICE UNDER
RESET
IN THIS AREA
FUNCTIONAL AREA
8
0
SUPPLY VOLTAGE [V]
V
≥3.85
IT-
2.5
3
3.5
4
4.5
5
5.5
5.5
5.5
2)
Figure 57. Medium LVD Threshold Versus VDD and f
for ROM devices
OSC
f
[MHz]
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
OSC
16
DEVICE UNDER
RESET
IN THIS AREA
FUNCTIONAL AREA
8
0
SUPPLY VOLTAGE [V]
2.5
3
V
IT-≥3.5V
4
4.5
5
2)
Figure 58. Low LVD Threshold Versus VDD and f
for ROM devices
OSC
f
[MHz]
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
OSC
16
DEVICE UNDER
RESET
IN THIS AREA
FUNCTIONAL AREA
8
0
SUPPLY VOLTAGE [V]
2.5
V
IT-≥3.00V
3.5
4
4.5
5
Notes:
1. LVD typical data are based on T =25°C. They are given only as design guidelines and are not tested.
A
2. The minimum V rise time rate is needed to insure a correct device power-on and LVD reset. Not tested in production.
DD
100/135
ST72104G, ST72215G, ST72216G, ST72254G
13.4 SUPPLY CURRENT CHARACTERISTICS
The following current consumption specified for
the ST7 functional operating modes over tempera-
ture range does not take into account the clock
source current consumption. To get the total de-
vice consumption, the two current values must be
added (except for HALT mode for which the clock
is stopped).
Symbol
∆I
Parameter
Conditions
Max
Unit
Supply current variation vs. temperature
Constant V and f
10
%
DD(∆Ta)
DD
CPU
13.4.1 RUN and SLOW Modes
1)
2)
Symbol
Parameter
Conditions
Typ
Max
Unit
500
1500
5600
900
2500
9000
f
f
f
=1MHz, f
=500kHz
=2MHz
=8MHz
3)
OSC
OSC
OSC
CPU
Supply current in RUN mode
(see Figure 59)
=4MHz, f
CPU
=16MHz, f
CPU
150
250
670
450
550
1250
f
f
f
=1MHz, f
=31.25kHz
=125kHz
=500kHz
4)
4)
OSC
OSC
OSC
CPU
Supply current in SLOW mode
(see Figure 60)
=4MHz, f
=16MHz, f
CPU
CPU
I
µA
DD
300
970
3600
550
1350
4500
f
f
f
=1MHz, f
=500kHz
=2MHz
=8MHz
3)
OSC
OSC
OSC
CPU
Supply current in RUN mode
(see Figure 59)
=4MHz, f
CPU
=16MHz, f
CPU
100
170
420
250
300
700
f
f
f
=1MHz, f
=31.25kHz
=125kHz
=500kHz
OSC
OSC
OSC
CPU
Supply current in SLOW mode
(see Figure 60)
=4MHz, f
CPU
=16MHz, f
CPU
Figure 59. Typical I in RUN vs. f
Figure 60. Typical I in SLOW vs. f
CPU
DD
CPU
DD
IDD [mA]
IDD [mA]
7
500kHz
250kHz
125kHz
31.25kHz
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
8MHz
4MHz
2MHz
6
5
4
3
500kHz
2
1
0
3
3.5
4
4.5
5
5.5
3
3.5
4
4.5
5
5.5
VDD [V]
VDD [V]
Notes:
1. Typical data are based on T =25°C, V =5V (4.5V≤V ≤5.5V range) and V =3.3V (3V≤V ≤3.6V range).
A
DD
DD
DD
DD
2. Data based on characterization results, tested in production at V max. and f
max.
DD
CPU
3. CPU running with memory access, all I/O pins in input mode with a static value at V or V (no load), all peripherals
DD
SS
in reset state; clock input (OSC1) driven by external square wave, CSS and LVD disabled.
4. SLOW mode selected with f
SS
based on f
divided by 32. All I/O pins in input mode with a static value at V or
CPU
OSC DD
V
(no load), all peripherals in reset state; clock input (OSC1) driven by external square wave, CSS and LVD disabled.
101/135
ST72104G, ST72215G, ST72216G, ST72254G
SUPPLY CURRENT CHARACTERISTICS (Cont’d)
13.4.2 WAIT and SLOW WAIT Modes
1)
2)
Symbol
Parameter
Conditions
Typ
Max
Unit
150
560
2200
280
900
3000
f
f
f
=1MHz, f
=500kHz
=2MHz
=8MHz
3)
OSC
OSC
OSC
CPU
Supply current in WAIT mode
(see Figure 61)
=4MHz, f
CPU
=16MHz, f
CPU
20
90
340
70
190
850
f
f
f
=1MHz, f
=31.25kHz
=125kHz
=500kHz
4)
4)
OSC
OSC
OSC
CPU
Supply current in SLOW WAIT mode
(see Figure 62)
=4MHz, f
=16MHz, f
CPU
CPU
I
µA
DD
90
350
1370
200
550
1900
f
f
f
=1MHz, f
=500kHz
=2MHz
=8MHz
3)
OSC
OSC
OSC
CPU
Supply current in WAIT mode
=4MHz, f
CPU
(see Figure 61)
=16MHz, f
CPU
10
50
200
20
80
350
f
f
f
=1MHz, f
=31.25kHz
=125kHz
=500kHz
OSC
OSC
OSC
CPU
Supply current in SLOW WAIT mode
(see Figure 62)
=4MHz, f
CPU
=16MHz, f
CPU
Figure 61. Typical I in WAIT vs. f
Figure 62. Typical I in SLOW-WAIT vs. f
DD
CPU
DD
CPU
IDD [mA]
3
IDD [mA]
0.35
500kHz
250kHz
125kHz
8MHz
4MHz
2MHz
0.3
2.5
2
31.25kHz
500kHz
0.25
0.2
1.5
1
0.15
0.1
0.05
0
0.5
0
3
3.5
4
4.5
5
5.5
3
3.5
4
4.5
5
5.5
VDD [V]
VDD [V]
Notes:
1. Typical data are based on T =25°C, V =5V (4.5V≤V ≤5.5V range) and V =3.3V (3V≤V ≤3.6V range).
A
DD
DD
DD
DD
2. Data based on characterization results, tested in production at V max. and f
max.
CPU
DD
3. All I/O pins in input mode with a static value at V or V (no load), all peripherals in reset state; clock input (OSC1)
DD
SS
driven by external square wave, CSS and LVD disabled.
4. SLOW-WAIT mode selected with f
based on f
divided by 32. All I/O pins in input mode with a static value at
OSC
CPU
V
or V (no load), all peripherals in reset state; clock input (OSC1) driven by external square wave, CSS and LVD
DD
SS
disabled.
102/135
ST72104G, ST72215G, ST72216G, ST72254G
SUPPLY CURRENT CHARACTERISTICS (Cont’d)
13.4.3 HALT Mode
1)
Symbol
Parameter
Conditions
-40°C≤T ≤+85°C
Typ
Max
10
50
6
Unit
A
V
V
=5.5V
=3.6V
DD
-40°C≤T ≤+125°C
A
2)
I
Supply current in HALT mode
0
µA
DD
-40°C≤T ≤+85°C
A
DD
-40°C≤T ≤+125°C
50
A
13.4.4 Supply and Clock Managers
The previous current consumption specified for
the ST7 functional operating modes over tempera-
ture range does not take into account the clock
source current consumption. To get the total de-
vice consumption, the two current values must be
added (except for HALT mode).
1)
3)
Symbol
Parameter
Conditions
Typ
Max
Unit
Supply current of internal RC oscillator
Supply current of external RC oscillator
500
525
750
750
4)
200
300
450
700
400
550
750
LP: Low power oscillator
I
DD(CK)
MP: Medium power oscillator
MS: Medium speed oscillator
HS: High speed oscillator
4) & 5)
Supply current of resonator oscillator
µA
1000
Clock security system supply current
LVD supply current
150
100
350
150
I
HALT mode
DD(LVD)
13.4.5 On-Chip Peripherals
Symbol
Parameter
Conditions
Typ
50
Unit
V
V
V
V
V
V
V
V
=3.3V
=5.0V
=3.3V
=5.0V
=3.3V
=5.0V
=3.3V
=5.0V
DD
DD
DD
DD
DD
DD
DD
DD
6)
I
16-bit Timer supply current
f
f
f
f
=8MHz
=8MHz
=8MHz
=4MHz
DD(TIM)
CPU
CPU
CPU
ADC
150
250
350
250
350
800
1100
7)
8)
I
SPI supply current
DD(SPI)
µA
2
I
I C supply current
DD(I2C)
9)
I
ADC supply current when converting
DD(ADC)
Notes:
1. Typical data are based on T =25°C.
A
2. All I/O pins in input mode with a static value at V or V (no load), CSS and LVD disabled. Data based on charac-
DD
SS
CPU
terization results, tested in production at V
max. and f
max.
DD
3. Data based on characterization results, not tested in production.
4. Data based on characterization results done with the external components specified in Section 13.5.3 and Section
13.5.4, not tested in production.
5. As the oscillator is based on a current source, the consumption does not depend on the voltage.
6. Data based on a differential I measurement between reset configuration (timer counter running at f
/4) and timer
CPU
DD
counter stopped (selecting external clock capability). Data valid for one timer.
7. Data based on a differential I measurement between reset configuration and a permanent SPI master communica-
DD
tion (data sent equal to 55h).
8. Data based on a differential I measurement between reset configuration and I2C peripheral enabled (PE bit set).
DD
9. Data based on a differential I measurement between reset configuration and continuous A/D conversions.
DD
103/135
ST72104G, ST72215G, ST72216G, ST72254G
13.5 CLOCK AND TIMING CHARACTERISTICS
Subject to general operating conditions for V , f
, and T .
DD OSC
A
13.5.1 General Timings
1)
Symbol
Parameter
Conditions
Min
2
Typ
Max
12
Unit
tCPU
ns
3
t
Instruction cycle time
c(INST)
f
f
=8MHz
250
10
375
1500
22
CPU
2)
tCPU
µs
Interrupt reaction time
t
v(IT)
t
= ∆t
+ 10
=8MHz
1.25
2.75
v(IT)
c(INST)
CPU
13.5.2 External Clock Source
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
V
OSC1 input pin high level voltage
OSC1 input pin low level voltage
0.7xV
V
V
DD
OSC1H
DD
V
V
0.3xV
DD
OSC1L
SS
t
t
3)
w(OSC1H)
see Figure 63
OSC1 high or low time
15
w(OSC1L)
ns
t
t
3)
r(OSC1)
OSC1 rise or fall time
15
f(OSC1)
I
OSCx Input leakage current
V
≤V ≤V
DD
±1
µA
L
SS IN
Figure 63. Typical Application with an External Clock Source
90%
V
V
OSC1H
OSC1L
10%
t
t
w(OSC1H)
t
t
w(OSC1L)
f(OSC1)
r(OSC1)
OSC2
Not connected internally
f
OSC
EXTERNAL
CLOCK SOURCE
I
L
OSC1
ST72XXX
Notes:
1. Data based on typical application software.
2. Time measured between interrupt event and interrupt vector fetch. ∆tc(INST) is the number of tCPU cycles needed to finish
the current instruction execution.
3. Data based on design simulation and/or technology characteristics, not tested in production.
104/135
ST72104G, ST72215G, ST72216G, ST72254G
CLOCK AND TIMING CHARACTERISTICS (Cont’d)
13.5.3 Crystal and Ceramic Resonator Oscillators
The ST7 internal clock can be supplied with four
different Crystal/Ceramic resonator oscillators. All
the information given in this paragraph are based
on characterization results with specified typical
external componants. In the application, the reso-
nator and the load capacitors have to be placed as
close as possible to the oscillator pins in order to
minimize output distortion and start-up stabiliza-
tion time. Refer to the crystal/ceramic resonator
manufacturer for more details (frequency, pack-
age, accuracy...).
Symbol
Parameter
Conditions
Min
Max
Unit
MHz
kΩ
LP: Low power oscillator
1
2
4
8
MP: Medium power oscillator
MS: Medium speed oscillator
HS: High speed oscillator
>2
>4
>8
3)
f
Oscillator Frequency
OSC
16
R
Feedback resistor
20
40
F
R =200Ω
LP oscillator
MP oscillator
MS oscillator
HS oscillator
38
32
18
15
56
46
26
21
S
Recommanded load capacitances ver-
sus equivalent serial resistance of the
C
C
R =200Ω
L1
L2
S
pF
R =200Ω
S
crystal or ceramic resonator (R )
S
R =100Ω
S
V
=5V
LP oscillator
MP oscillator
MS oscillator
HS oscillator
40
100
190
360
700
DD
V =V
110
180
400
IN
SS
i
OSC2 driving current
µA
2
Typical Crystal or Ceramic Resonators
C
C
L1 L2
t
SU(osc)
Oscil.
2)
1)
[ms]
[pF] [pF]
Reference
Freq.
2MHz
4MHz
8MHz
16MHz
2MHz
4MHz
8MHz
16MHz
Characteristic
LP
MP
MS
HS
LP
S-200-30-30/50
SS3-400-30-30/30
SS3-800-30-30/30
SS3-1600-30-30/30
CSA2.00MG
∆f
∆f
∆f
∆f
∆f
∆f
∆f
∆f
=[±30ppm
=[±30ppm
=[±30ppm
=[±30ppm
,±30ppm ], Typ. R =200Ω
33 34 10~15
33 34 7~10
33 34 2.5~3
33 34 1~1.5
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
25°C
∆Ta
S
,±30ppm ], Typ. R =60Ω
25°C
∆Ta
S
,±30ppm ], Typ. R =25Ω
25°C
∆Ta
S
,±30ppm ], Typ. R =15Ω
25°C
∆Ta
S
=[±0.5%
=[±0.5%
=[±0.5%
=[±0.5%
,±0.3% ,±0.3%
,±x.x%
,±x.x%
,±x.x%
,±x.x%
]
]
]
]
33 30
33 30
33 30
33 30
4.2
2.1
1.1
0.7
tolerance
tolerance
tolerance
tolerance
∆Ta
aging
aging
aging
aging
correl
correl
correl
correl
MP
MS
HS
CSA4.00MG
,±0.3% ,±0.3%
∆Ta
CSA8.00MTZ
,±0.5% ,±0.3%
∆Ta
CSA16.00MXZ040
,±0.3% ,±0.3%
∆Ta
Figure 64. Typical Application with a Crystal or Ceramic Resonator
WHEN RESONATOR WITH
INTEGRATEDCAPACITORS
i
2
f
OSC
C
L1
OSC1
OSC2
RESONATOR
R
F
C
L2
ST72XXX
Notes:
1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
2. t
is the typical oscillator start-up time measured between V =2.8V and the fetch of the first instruction (with a
SU(OSC)
DD
quick V
ramp-up from 0 to 5V (<50µs).
DD
3. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small R value.
S
Refer to crystal/ceramic resonator manufacturer for more details.
105/135
ST72104G, ST72215G, ST72216G, ST72254G
CLOCK CHARACTERISTICS (Cont’d)
13.5.4 RC Oscillators
The ST7 internal clock can be supplied with an RC
oscillator. This oscillator can be used with internal
or external components (selectable by option
byte).
Symbol
Parameter
Conditions
see Figure 66
Min
3.60
1
Typ
Max
5.10
14
Unit
1)
Internal RC oscillator frequency
f
t
MHz
OSC
2)
External RC oscillator frequency
Internal RC Oscillator Start-up Time
3)
2.0
R
R
R
R
=47KΩ,
=47KΩ,
=10KΩ,
=10KΩ,
C
C
C
C
=”0”pF
=100pF
=6.8pF
=470pF
1.0
6.5
0.7
3.0
EX
EX
EX
EX
EX
EX
EX
EX
ms
SU(OSC)
3)
External RC Oscillator Start-up Time
4)
R
C
Oscillator external resistor
10
47
KΩ
EX
EX
see Figure 67
5)
Oscillator external capacitor
0
470
pF
Figure 65. Typical Application with RC oscillator
ST72XXX
V
DD
INTERNAL RC
Current copy
EXTERNAL RC
+
-
V
f
REF
OSC
R
EX
OSC2
C
EX
OSC1
Voltage generator
C
EX discharge
Figure 66. Typical Internal RC Oscillator
Figure 67. Typical External RC Oscillator
fosc [MHz]
fosc [MHz]
Rex=10KOhm
-40°C
+85°C
20
15
10
5
4.3
4.2
4.1
4
Rex=15KOhm
Rex=22KOhm
Rex=33KOhm
Rex=39KOhm
Rex=47KOhm
+25°C
+125°C
3.9
3.8
0
3
5.5
0
6.8
22
47
100
270
470
VDD [V]
Cex [pF]
Notes:
1. Data based on characterization results.
2. Guaranteed frequency range with the specified C and R ranges taking into account the device process variation.
EX
EX
Data based on design simulation.
3. Data based on characterization results done with V nominal at 5V, not tested in production.
DD
4. R must have a positive temperature coefficient (ppm/°C), carbon resistors should therefore not be used.
EX
5. Important: when no external C is applied, the capacitance to be considered is the global parasitic capacitance which
EX
is subject to high variation (package, application...). In this case, the RC oscillator frequency tuning has to be done by
trying out several resistor values.
106/135
ST72104G, ST72215G, ST72216G, ST72254G
CLOCK CHARACTERISTICS (Cont’d)
13.5.5 Clock Security System (CSS)
Symbol
Parameter
Conditions
T =25°C, V =5.0V
Min
250
190
Typ
340
260
30
Max
430
330
Unit
kHz
A
DD
1)
f
f
Safe Oscillator Frequency
SFOSC
GFOSC
T =25°C, V =3.3V
A
DD
2)
Glitch Filtered Frequency
MHz
Figure 68. Typical Safe Oscillator Frequencies
fosc [kHz]
-40°C
+85°C
400
350
300
250
200
+25°C
+125°C
3
5.5
VDD [V]
Note:
1. Data based on characterization results, tested in production between 90KHz and 500KHz.
2. Filtered glitch on the f signal. See functional description in Section 6.5 on page 23 for more details.
OSC
107/135
ST72104G, ST72215G, ST72216G, ST72254G
13.6 MEMORY CHARACTERISTICS
Subject to general operating conditions for V , f
, and T unless otherwise specified.
A
DD OSC
13.6.1 RAM and Hardware Registers
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
1)
V
Data retention mode
HALT mode (or RESET)
1.6
V
RM
13.6.2 FLASH Program Memory
Symbol
Parameter
Conditions
Min
Typ
25
8
Max
70
Unit
°C
2)
T
Programming temperature range
0
A(prog)
3)
T =+25°C
25
Programming time for 1~16 bytes
ms
A
t
prog
T =+25°C
2.1
6.4
Programming time for 4 or 8kBytes
sec
A
5)
4)
t
Data retention
T =+55°C
20
years
cycles
ret
A
5)
N
Write erase cycles
T =+25°C
100
RW
A
Notes:
1. Minimum V
supply voltage without losing data stored in RAM (in in HALT mode or under RESET) or in hardware
DD
registers (only in HALT mode). Guaranteed by construction, not tested in production.
2. Data based on characterization results, tested in production at T =25°C.
A
3. Up to 16 bytes can be programmed at a time for a 4kBytes FLASH block (then up to 32 bytes at a time for an 8k device)
4. The data retention time increases when the T decreases.
A
5. Data based on reliability test results and monitored in production.
108/135
ST72104G, ST72215G, ST72216G, ST72254G
13.7 EMC CHARACTERISTICS
Susceptibility tests are performed on a sample ba-
sis during product characterization.
■ ESD: Electro-Static Discharge (positive and
negative) is applied on all pins of the device until
a functional disturbance occurs. This test
conforms with the IEC 1000-4-2 standard.
13.7.1 Functional EMS
(Electro Magnetic Susceptibility)
■ FTB: A Burst of Fast Transient voltage (positive
Based on a simple running application on the
product (toggling 2 LEDs through I/O ports), the
product is stressed by two electro magnetic events
until a failure occurs (indicated by the LEDs).
and negative) is applied to V and V through
DD
SS
a 100pF capacitor, until a functional disturbance
occurs. This test conforms with the IEC 1000-4-
4 standard.
A device reset allows normal operations to be re-
sumed.
1)
1)
Symbol
Parameter
Conditions
=5V, T =+25°C, f
conforms to IEC 1000-4-2
Neg
Pos
Unit
Voltage limits to be applied on any I/O pin
to induce a functional disturbance
V
=8MHz
OSC
DD
A
V
-1
1
FESD
kV
Fast transient voltage burst limits to be ap-
V
=5V, T =+25°C, f
=8MHz
OSC
DD
A
V
plied through 100pF on V and V pins
-4
4
FFTB
DD
DD
conforms to IEC 1000-4-4
to induce a functional disturbance
2)
Figure 69. EMC Recommended star network power supply connection
ST72XXX
10nF 0.1µF
V
V
DD
SS
ST7
DIGITAL NOISE
FILTERING
V
DD
POWER
SUPPLY
SOURCE
V
V
SSA
DDA
EXTERNAL
NOISE
FILTERING
0.1µF
Notes:
1. Data based on characterization results, not tested in production.
2. The suggested 10nF and 0.1µF decoupling capacitors on the power supply lines are proposed as a good price vs. EMC
performance tradeoff. They have to be put as close as possible to the device power supply pins. Other EMC recommen-
dations are given in other sections (I/Os, RESET, OSCx pin characteristics).
109/135
ST72104G, ST72215G, ST72216G, ST72254G
EMC CHARACTERISTICS (Cont’d)
13.7.2 Absolute Electrical Sensitivity
Machine Model Test Sequence
Based on three different tests (ESD, LU and DLU)
using specific measurement methods, the product
is stressed in order to determine its performance in
terms of electrical sensitivity. For more details, re-
fer to the AN1181 ST7 application note.
– C is loaded through S1 by the HV pulse gener-
ator.
L
– S1 switches position from generator to ST7.
– A discharge from C to the ST7 occurs.
L
– S2 must be closed 10 to 100ms after the pulse
delivery period to ensure the ST7 is not left in
charge state. S2 must be opened at least 10ms
prior to the delivery of the next pulse.
13.7.2.1 Electro-Static Discharge (ESD)
Electro-Static Discharges (3 positive then 3 nega-
tive pulses separated by 1 second) are applied to
the pins of each sample according to each pin
combination. The sample size depends of the
number of supply pins of the device (3 parts*(n+1)
supply pin). Two models are usually simulated:
Human Body Model and Machine Model. This test
conforms to the JESD22-A114A/A115A standard.
See Figure 70 and the following test sequences.
– R (machine resistance), in series with S2, en-
sures a slow discharge of the ST7.
Human Body Model Test Sequence
– C is loaded through S1 by the HV pulse gener-
L
ator.
– S1 switches position from generator to R.
– Adischarge from C through R(body resistance)
L
to the ST7 occurs.
– S2 must be closed 10 to 100ms after the pulse
delivery period to ensure the ST7 is not left in
charge state. S2 must be opened at least 10ms
prior to the delivery of the next pulse.
Absolute Maximum Ratings
1)
Symbol
Ratings
Conditions
Maximum value
Unit
Electro-static discharge voltage
(Human Body Model)
T =+25°C
V
2000
A
ESD(HBM)
V
Electro-static discharge voltage
(Machine Model)
V
T =+25°C
200
ESD(MM)
A
Figure 70. Typical Equivalent ESD Circuits
S1
R=1500Ω
S1
HIGH VOLTAGE
PULSE
GENERATOR
HIGH VOLTAGE
PULSE
GENERATOR
ST7
ST7
C =100pF
S2
L
S2
C =200pF
L
HUMAN BODY MODEL
MACHINE MODEL
Notes:
1. Data based on characterization results, not tested in production.
110/135
ST72104G, ST72215G, ST72216G, ST72254G
EMC CHARACTERISTICS (Cont’d)
13.7.2.2 Static and Dynamic Latch-Up
■ DLU: Electro-Static Discharges (one positive
then one negative test) are applied to each pin
of 3 samples when the micro is running to
assess the latch-up performance in dynamic
mode. Power supplies are set to the typical
values, the oscillator is connected as near as
possible to the pins of the micro and the
component is put in reset mode. This test
conforms to the IEC1000-4-2 and SAEJ1752/3
standards and is described in Figure 71. For
more details, refer to the AN1181 ST7
application note.
■ LU: 3 complementary static tests are required
on 10parts to assess the latch-up performance.
A supply overvoltage (applied to each power
supply pin), a current injection (applied to each
input, output and configurable I/O pin) and a
power supply switch sequence are performed
on each sample. This test conforms to the EIA/
JESD 78 IC latch-up standard. For more details,
refer to the AN1181 ST7 application note.
Electrical Sensitivities
1)
Symbol
LU
Parameter
Static latch-up class
Dynamic latch-up class
Conditions
Class
T =+25°C
A
A
A
T =+85°C
A
V
=5.5V, f
=4MHz, T =+25°C
DLU
A
DD
OSC
A
Figure 71. Simplified Diagram of the ESD Generator for DLU
R
2)
=50MΩ
R =330Ω
D
CH
DISCHARGE TIP
V
V
DD
SS
HV RELAY
C =150pF
S
ST7
ESD
GENERATOR
DISCHARGE
RETURN CONNECTION
Notes:
1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC spec-
ifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the
JEDEC criteria (international standard).
2. Schaffner NSG435 with a pointed test finger.
111/135
ST72104G, ST72215G, ST72216G, ST72254G
EMC CHARACTERISTICS (Cont’d)
13.7.3 ESD Pin Protection Strategy
Standard Pin Protection
To protect an integrated circuit against Electro-
Static Discharge the stress must be controlled to
prevent degradation or destruction of the circuit el-
ements. The stress generally affects the circuit el-
ements which are connected to the pads but can
also affect the internal devices when the supply
pads receive the stress. The elements to be pro-
tected must not receive excessive current, voltage
or heating within their structure.
To protect the output structure the following ele-
ments are added:
– A diode to V (3a) and a diode from V (3b)
DD
SS
– A protection device between V and V (4)
DD
SS
To protect the input structure the following ele-
ments are added:
– A resistor in series with the pad (1)
– A diode to V (2a) and a diode from V (2b)
DD
SS
– A protection device between V and V (4)
DD
SS
An ESD network combines the different input and
output ESD protections. This network works, by al-
lowing safe discharge paths for the pins subjected
to ESD stress. Two critical ESD stress cases are
presented in Figure 72 and Figure 73 for standard
pins and in Figure 74 and Figure 75 for true open
drain pins.
Figure 72. Positive Stress on a Standard Pad vs. V
SS
V
V
DD
DD
(3a)
(2a)
(1)
(4)
OUT
IN
Main path
(3b)
(2b)
Path to avoid
V
V
V
SS
SS
DD
Figure 73. Negative Stress on a Standard Pad vs. V
DD
V
DD
(3a)
(2a)
(1)
(4)
OUT
IN
Main path
(3b)
(2b)
V
V
SS
SS
112/135
ST72104G, ST72215G, ST72216G, ST72254G
Multisupply Configuration
EMC CHARACTERISTICS (Cont’d)
True Open Drain Pin Protection
The centralized protection (4) is not involved in the
discharge of the ESD stresses applied to true
open drain pads due to the fact that a P-Buffer and
When several types of ground (V , V
, ...) and
SS
SSA
power supply (V , V
, ...) are available for any
DD
DDA
reason (better noise immunity...), the structure
shown in Figure 76 is implemented to protect the
device against ESD.
diode to V
are not implemented. An additional
DD
local protection between the pad and V (5a &
SS
5b) is implemented to completly absorb the posi-
tive ESD discharge.
Figure 74. Positive Stress on a True Open Drain Pad vs. V
SS
V
V
DD
DD
Main path
(1)
Path to avoid
OUT
(4)
IN
(5a)
(5b)
(3b)
(2b)
V
V
V
SS
SS
Figure 75. Negative Stress on a True Open Drain Pad vs. V
DD
V
DD
DD
Main path
(1)
OUT
(4)
IN
(3b)
(3b)
(3b)
(2b)
V
V
SS
SS
Figure 76. Multisupply Configuration
V
DD
V
DDA
V
DDA
V
SS
BACK TO BACK DIODE
BETWEEN GROUNDS
V
SSA
V
SSA
113/135
ST72104G, ST72215G, ST72216G, ST72254G
13.8 I/O PORT PIN CHARACTERISTICS
13.8.1 General Characteristics
Subject to general operating conditions for V , f
, and T unless otherwise specified.
DD OSC
A
1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
V
2)
V
Input low level voltage
0.3xVDD
IL
2)
V
Input high level voltage
0.7xVDD
IH
3)
V
Schmitt trigger voltage hysteresis
Input leakage current
400
mV
µA
hys
I
V
SS≤V ≤V
DD
±1
L
IN
4)
I
Static current consumption
Floating input mode
200
250
230
S
V
V
=5V
80
120
200
5
DD
DD
5)
R
Weak pull-up equivalent resistor
V =V
SS
kΩ
pF
ns
PU
IN
=3.3V
170
C
I/O pin capacitance
IO
6)
t
Output high to low level fall time
25
25
C =50pF
Between 10% and 90%
f(IO)out
r(IO)out
L
6)
t
Output low to high level rise time
7)
t
External interrupt pulse time
1
t
CPU
w(IT)in
Figure 77. Two typical Applications with unused I/O Pin
V
DD
ST72XXX
UNUSED I/O PORT
10kΩ
10kΩ
UNUSED I/O PORT
ST72XXX
Figure 78. Typical I vs. V with V =V
PU
DD
IN
SS
Ipu [µA]
70
Ta=-40°C
Ta=25°C
Ta=85°C
60
Ta=125°C
50
40
30
20
10
0
3
3.5
4
4.5
5
5.5
Vdd [V]
Notes:
1. Unless otherwise specified, typical data are based on T =25°C and V =5V.
A
DD
2. Data based on characterization results, not tested in production.
3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
4. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for
example or an external pull-up or pull-down resistor (see Figure 77). Data based on design simulation and/or technology
characteristics, not tested in production.
5. The R
pull-up equivalent resistor is based on a resistive transistor (corresponding I current characteristics de-
PU
PU
scribed in Figure 78). This data is based on characterization results, tested in production at V max.
DD
6. Data based on characterization results, not tested in production.
7. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external
interrupt source.
114/135
ST72104G, ST72215G, ST72216G, ST72254G
I/O PORT PIN CHARACTERISTICS (Cont’d)
13.8.2 Output Driving Current
Subject to general operating conditions for V , f
, and T unless otherwise specified.
A
DD OSC
Symbol
Parameter
Conditions
Min
Max
Unit
Output low level voltage for a standard I/O pin
when 8 pins are sunk at same time
(see Figure 79 and Figure 82)
I
I
I
=+5mA
1.2
IO
IO
IO
=+2mA
0.5
1)
V
OL
=+20mA,T ≤85°C
1.3
1.5
A
Output low level voltage for a high sink I/O pin
when 4 pins are sunk at same time
(see Figure 80 and Figure 83)
T ≥85°C
A
V
I
I
=+8mA
0.6
IO
=-5mA, T ≤85°C
V
V
-1.4
-1.6
IO
A
Output high level voltage for an I/O pin
when 4 pins are sourced at same time
(see Figure 81 and Figure 84)
DD
DD
2)
T ≥85°C
V
A
OH
I
=-2mA
V
-0.7
IO
DD
Figure 79. Typical V at V =5V (standard)
Figure 81. Typical V -V at V =5V
DD OH DD
OL
DD
Vol [V] at Vdd=5V
2.5
Vdd-Voh [V] at Vdd=5V
6
Ta=-40°C
Ta=85°C
2
5
4
3
2
1
Ta=25°C
Ta=125°C
1.5
Ta=-40°C
Ta=25°C
Ta=85°C
Ta=125°C
1
0.5
0
0
2
4
6
8
10
-8
-6
-4
Iio [mA]
-2
0
Iio [mA]
Figure 80. Typical V at V =5V (high-sink)
OL
DD
Vol [V] at Vdd=5V
2
Ta=-40°C
Ta=85°C
1.5
Ta=25°C
Ta=125°C
1
0.5
0
0
5
10
15
Iio [mA]
20
25
30
Notes:
1. The I current sunk must always respect the absolute maximum rating specified in Section 13.2.2 and the sum of I
IO
IO
(I/O ports and control pins) must not exceed I
.
VSS
2. The I current sourced must always respect the absolute maximum rating specified in Section 13.2.2 and the sum of
IO
I
(I/O ports and control pins) must not exceed I
. True open drain I/O pins does not have V
.
IO
VDD
OH
115/135
ST72104G, ST72215G, ST72216G, ST72254G
I/O PORT PIN CHARACTERISTICS (Cont’d)
Figure 82. Typical V vs. V (standard I/Os)
OL
DD
Ta=-40°C
Ta=85°C
Ta=-40°C
Ta=25°C
Ta=85°C
Vol [V] at Iio=2mA
0.5
Vol [V] at Iio=5mA
1.4
1.3
Ta=25°C
Ta=125°C
Ta=125°C
0.45
0.4
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
0.35
0.3
0.25
0.2
3
3.5
4
4.5
5
5.5
3
3.5
4
Vdd [V]
4.5
5
5.5
Vdd [V]
Figure 83. Typical V vs. V (high-sink I/Os)
OL
DD
Ta=-40°C
Ta=25°C
Ta=85°C
Ta=-40°C
Ta=25°C
Ta=85°C
Vol [V] at Iio=8mA
Vol [V] at Iio=20mA
1.5
0.55
0.5
Ta=125°C
Ta=125°C
1.3
1.1
0.9
0.7
0.5
0.45
0.4
0.35
0.3
0.25
0.2
3
3.5
4
4.5
5
5.5
3
3.5
4
Vdd [V]
4.5
5
5.5
Vdd [V]
Figure 84. Typical V -V vs. V
DD OH
DD
Vdd-Voh [V] at Iio=-2mA
Vdd-Voh [V] at Iio=-5mA
5
5.5
5
4
3
2
1
0
4.5
4
Ta=-40°C
Ta=25°C
Ta=85°C
3.5
Ta=-40°C
Ta=25°C
Ta=85°C
3
2.5
2
Ta=125°C
Ta=125°C
3
3.5
4
4.5
5
5.5
3.5
4
4.5
Vdd [V]
5
5.5
Vdd [V]
116/135
ST72104G, ST72215G, ST72216G, ST72254G
13.9 CONTROL PIN CHARACTERISTICS
13.9.1 Asynchronous RESET Pin
Subject to general operating conditions for V , f
, and T unless otherwise specified.
DD OSC
A
1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
V
2)
V
Input low level voltage
0.3xVDD
IL
2)
V
Input high level voltage
0.7xVDD
IH
3)
V
Schmitt trigger voltage hysteresis
400
mV
V
hys
4)
I
I
=+5mA
=+2mA
0.68
0.28
40
0.95
0.45
60
Output low level voltage
IO
V
V
=5V
DD
OL
(see Figure 87, Figure 88)
IO
V
V
=5V
20
80
DD
DD
5)
R
Weak pull-up equivalent resistor
Generated reset pulse duration
V =V
SS
kΩ
ON
IN
=3.3V
100
120
External pin or
internal reset sources
6
30
1/f
SFOSC
t
w(RSTL)out
µs
6)
t
External reset pulse hold time
20
µs
h(RSTL)in
7)
t
Filtered glitch duration
100
ns
g(RSTL)in
8)
Figure 85. Typical Application with RESET pin
ST72XXX
V
DD
V
V
DD
DD
INTERNAL
RESET CONTROL
R
ON
0.1µF
0.1µF
4.7kΩ
USER
EXTERNAL
RESET
RESET
8)
CIRCUIT
WATCHDOG RESET
LVD RESET
Notes:
1. Unless otherwise specified, typical data are based on T =25°C and V =5V.
A
DD
2. Data based on characterization results, not tested in production.
3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
4. The I current sunk must always respect the absolute maximum rating specified in Section 13.2.2 and the sum of I
IO
IO
(I/O ports and control pins) must not exceed I
.
VSS
5. The R
pull-up equivalent resistor is based on a resistive transistor (corresponding I current characteristics de-
ON
ON
scribed in Figure 86). This data is based on characterization results, not tested in production.
5. To guarantee the reset of the device, a minimum pulse has to be applied to RESET pin.
6. All short pulse applied on RESET pin with a duration below t
can be ignored.
h(RSTL)in
7. The reset network (the resistor and two capacitors) protects the device against parasitic resets, especially in a noisy
environment.
8. The output of the external reset circuit must have an open-drain output to drive theST7 reset pad. Otherwise the device
can be damaged when the ST7 generates an internal reset (LVD or watchdog).
117/135
ST72104G, ST72215G, ST72216G, ST72254G
CONTROL PIN CHARACTERISTICS (Cont’d)
Figure 86. Typical I vs. V with V =V
Figure 87. Typical V at V =5V (RESET)
OL DD
ON
DD
IN
SS
Ion [µA]
Vol [V] at Vdd=5V
2
Ta=-40°C
Ta=25°C
Ta=85°C
Ta=125°C
200
Ta=-40°C
Ta=25°C
Ta=85°C
Ta=125°C
150
100
50
1.5
1
0.5
0
0
0
1
2
3
4
5
6
7
8
3
3.5
4
4.5
5
5.5
Iio [mA]
Vdd [V]
Figure 88. Typical V vs. V (RESET)
OL
DD
Vol [V] at Iio=2mA
0.55
Vol [V] at Iio=5mA
Ta=-40°C
Ta=25°C
Ta=85°C
Ta=-40°C
Ta=85°C
Ta=125°C
Ta=25°C
Ta=125°C
1.2
1
0.5
0.45
0.4
0.35
0.3
0.8
0.6
0.4
0.25
0.2
0.15
3
3.5
4
4.5
5
5.5
3
3.5
4
Vdd [V]
4.5
5
5.5
Vdd [V]
118/135
ST72104G, ST72215G, ST72216G, ST72254G
CONTROL PIN CHARACTERISTICS (Cont’d)
13.9.2 ISPSEL Pin
Subject to general operating conditions for V , f
, and T unless otherwise specified.
A
DD OSC
Symbol
Parameter
Conditions
Min
Max
Unit
V
1)
V
Input low level voltage
V
0.2
IL
IH
L
SS
1)
V
I
Input high level voltage
Input leakage current
V
-0.1 12.6
DD
V
=V
±1
µA
IN
SS
2)
Figure 89. Two typical Applications with ISPSEL Pin
ISPSEL
ISPSEL
PROGRAMMING
TOOL
10kΩ
ST72XXX
ST72XXX
Notes:
1. Data based on design simulation and/or technology characteristics, not tested in production.
2. When the ISP Remote mode is not required by the application ISPSEL pin must be tied to V
.
SS
119/135
ST72104G, ST72215G, ST72216G, ST72254G
13.10 TIMER PERIPHERAL CHARACTERISTICS
Subject to general operating conditions for V
,
Refer to I/O port characteristics for more details on
the input/output alternate function characteristics
(output compare, input capture, external clock,
PWM output...).
DD
f
, and T unless otherwise specified.
OSC
A
13.10.1 Watchdog Timer
Symbol
Parameter
Conditions
Min
12,288
1.54
Typ
Max
786,432
98.3
Unit
tCPU
ms
t
Watchdog time-out duration
w(WDG)
fCPU=8MHz
13.10.2 16-Bit Timer
Symbol
Parameter
Conditions
Min
1
Typ
Max
Unit
t
Input capture pulse time
t
t
w(ICAP)in
CPU
2
CPU
t
PWM resolution time
res(PWM)
f
=8MHz
250
0
ns
CPU
f
Timer external clock frequency
PWM repetition rate
f
/4
MHz
MHz
bit
EXT
CPU
f
0
f
/4
PWM
CPU
Res
PWM resolution
16
PWM
120/135
ST72104G, ST72215G, ST72216G, ST72254G
13.11 COMMUNICATION INTERFACE CHARACTERISTICS
13.11.1 SPI - Serial Peripheral Interface
Refer to I/O port characteristics for more details on
the input/output alternate function characteristics
(SS, SCK, MOSI, MISO).
Subject to general operating conditions for V
,
DD
f
, and T unless otherwise specified.
OSC
A
Symbol
Parameter
Conditions
Min
/128
0.0625
Max
Unit
Master
Slave
f
f
f
/4
CPU
2
CPU
f
=8MHz
=8MHz
f
CPU
SCK
SPI clock frequency
MHz
1/t
/2
c(SCK)
CPU
0
f
4
CPU
t
t
r(SCK)
f(SCK)
SPI clock rise and fall time
see I/O port pin description
t
SS setup time
SS hold time
Slave
Slave
120
120
su(SS)
t
h(SS)
t
t
Master
Slave
100
90
w(SCKH)
SCK high and low time
Data input setup time
Data input hold time
w(SCKL)
t
Master
Slave
100
100
su(MI)
t
su(SI)
ns
t
Master
Slave
100
100
h(MI)
t
h(SI)
t
Data output access time
Data output disable time
Data output valid time
Data output hold time
Data output valid time
Data output hold time
Slave
Slave
0
120
240
120
a(SO)
t
dis(SO)
t
v(SO)
Slave (after enable edge)
t
0
h(SO)
v(MO)
h(MO)
t
0.25
0.25
Master (before capture edge)
t
CPU
t
Figure 90. SPI Slave Timing Diagram with CPHA=0 3)
SS
INPUT
t
t
su(SS)
c(SCK)
t
h(SS)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
t
t
w(SCKH)
w(SCKL)
t
t
t
t
dis(SO)
a(SO)
v(SO)
h(SO)
t
t
r(SCK)
f(SCK)
see
note 2
MISO
OUTPUT
INPUT
see note 2
MSB OUT
BIT6 OUT
LSB OUT
t
t
h(SI)
su(SI)
MSB IN
BIT1 IN
LSB IN
MOSI
Notes:
1. Data based on design simulation and/or characterisation results, not tested in production.
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has
its alternate function capability released. In this case, the pin status depends on the I/O port configuration.
3. Measurement points are done at CMOS levels: 0.3xV
and 0.7xV
.
DD
DD
121/135
ST72104G, ST72215G, ST72216G, ST72254G
COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d)
Figure 91. SPI Slave Timing Diagram with CPHA=11)
SS
INPUT
t
t
su(SS)
c(SCK)
t
h(SS)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
t
t
w(SCKH)
w(SCKL)
t
t
dis(SO)
a(SO)
t
t
h(SO)
v(SO)
t
t
r(SCK)
f(SCK)
see
note 2
see
note 2
MISO
OUTPUT
HZ
MSB OUT
t
BIT6 OUT
LSB OUT
t
su(SI)
h(SI)
MSB IN
LSB IN
BIT1 IN
MOSI
INPUT
Figure 92. SPI Master Timing Diagram 1)
SS
INPUT
t
c(SCK)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
CPHA=1
CPOL=0
CPHA=1
CPOL=1
t
w(SCKH)
t
r(SCK)
t
w(SCKL)
t
f(SCK)
t
t
h(MI)
su(MI)
MISO
MOSI
INPUT
MSB IN
h(MO)
BIT6 IN
LSB IN
t
t
v(MO)
MSB OUT
LSB OUT
see note 2
BIT6 OUT
see note 2
OUTPUT
Notes:
1. Measurement points are done at CMOS levels: 0.3xV and 0.7xV
.
DD
DD
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has
its alternate function capability released. In this case, the pin status depends of the I/O port configuration.
122/135
ST72104G, ST72215G, ST72216G, ST72254G
COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d)
2
13.11.2 I C - Inter IC Control Interface
Refer to I/O port characteristics for more details on
the input/output alternate function characteristics
Subject to general operating conditions for V
,
DD
2
(SDAI and SCLI). The ST7 I C interfacemeets the
f
, and T unless otherwise specified.
OSC
A
2
requirements of the Standard I C communication
protocol described in the following table.
2
2
Standard mode I C
Fast mode I C
Symbol
Parameter
Unit
1)
1)
1)
1)
Min
Max
Min
Max
t
SCL clock low time
SCL clock high time
SDA setup time
4.7
4.0
1.3
0.6
100
w(SCLL)
µs
t
w(SCLH)
t
250
su(SDA)
3)
2)
3)
t
SDA data hold time
0
0
900
h(SDA)
t
t
r(SDA)
ns
SDA and SCL rise time
SDA and SCL fall time
1000
300
20+0.1C
20+0.1C
300
300
b
b
r(SCL)
t
t
f(SDA)
f(SCL)
t
START condition hold time
4.0
4.7
4.0
4.7
0.6
0.6
0.6
1.3
h(STA)
µs
t
Repeated START condition setup time
STOP condition setup time
su(STA)
t
ns
ms
pF
su(STO)
t
STOP to START condition time (bus free)
Capacitive load for each bus line
w(STO:STA)
C
400
400
b
2
Figure 93. Typical Application with I C Bus and Timing Diagram 4)
V
V
DD
DD
4.7kΩ
4.7kΩ
100Ω
100Ω
SDAI
SCLI
2
I C BUS
ST72XXX
REPEATED START
START
t
t
su(STA)
w(STO:STA)
START
SDA
t
t
r(SDA)
f(SDA)
STOP
t
t
h(SDA)
su(SDA)
SCK
t
t
t
t
t
su(STO)
t
h(STA)
w(SCKH)
w(SCKL)
r(SCK)
f(SCK)
Notes:
2
1. Data based on standard I C protocol requirement, not tested in production.
2. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined
region of the falling edge of SCL.
3. The maximum hold time of the START condition has only to be met if the interface does not stretch the low period of
SCL signal.
4. Measurement points are done at CMOS levels: 0.3xV
and 0.7xV
.
DD
DD
123/135
ST72104G, ST72215G, ST72216G, ST72254G
13.12 8-BIT ADC CHARACTERISTICS
Subject to general operating conditions for V , f
, and T unless otherwise specified.
DD OSC
A
1)
Symbol
Parameter
ADC clock frequency
Conversion range voltage
External input resistor
Conditions
Min
Typ
Max
Unit
MHz
V
f
4
ADC
2)
V
V
V
AIN
SSA
DDA
3)
R
10
kΩ
AIN
C
t
Internal sample and hold capacitor
Stabilization time after ADC enable
Conversion time (Sample+Hold)
6
pF
ADC
4)
0
STAB
µs
3
f
=8MHz, f
=4MHz
ADC
CPU
t
- Sample capacitor loading time
- Hold conversion time
4
8
ADC
1/f
ADC
Figure 94. Typical Application with ADC
V
DD
V
T
0.6V
R
AIN
AINx
V
AIN
ADC
V
0.6V
T
C
~2pF
I
L
±1µA
IO
V
DD
V
V
DDA
SSA
0.1µF
ST72XXX
Notes:
1. Unless otherwise specified, typical data are based on T =25°C and V -V =5V. They are given only as design guide-
A
DD SS
lines and are not tested.
2. When V and V
pins are not available on the pinout, the ADC refer to V and V .
SS
DDA
SSA
DD
3. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10kΩ). Data
based on characterization results, not tested in production.
4. The stabilization time of the AD converter is masked by the first t
always valid.
. The first conversion after the enable is then
LOAD
124/135
ST72104G, ST72215G, ST72216G, ST72254G
8-BIT ADC CHARACTERISTICS (Cont’d)
ADC Accuracy
Symbol
|E |
Parameter
Conditions
Min
Max
1
Unit
1)
Total unadjusted error
T
1)
-0.5
-0.5
0.5
0.5
0.5
0.5
E
E
Offset error
O
G
3)
V
=5.0V,
1)
DD
LSB
Gain Error
f
=8MHz
CPU
1)
|E |
Differential linearity error
D
1)
|E |
Integral linearity error
L
Figure 95. ADC Accuracy Characteristics
Digital Result ADCDR
E
G
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line
255
V
– V
254
253
DDA
SSA
1LSB
= ----------------------------------------
IDEAL
256
(2)
E =Total Unadjusted Error: maximum deviation
T
E
between the actual and the ideal transfer curves.
T
(3)
7
6
5
4
3
2
1
E =Offset Error: deviation between the first actual
O
(1)
transition and the first ideal one.
E =Gain Error: deviation between the last ideal
G
transition and the last actual one.
E
O
E
L
E =Differential Linearity Error: maximum deviation
D
between actual steps and the ideal one.
E =Integral Linearity Error: maximum deviation
L
E
between any actual transition and the end point
correlation line.
D
1 LSB
IDEAL
7
V
(LSB
)
in
IDEAL
0
1
2
3
4
5
6
253 254 255 256
V
V
DDA
SSA
Notes:
1. ADC Accuracy vs. Negative Injection Current:
For I =0.8mA, the typical leakage induced inside the die is 1.6µA and the effect on the ADC accuracy is a loss of 1 LSB
INJ-
for each 10KΩ increase of the external analog source impedance. This effect on the ADC accuracy has been observed
under worst-case conditions for injection:
- negative injection
- injection to an Input with analog capability, adjacent to the enabled Analog Input
- at 5V V supply, and worst case temperature.
DD
3. Data based on characterization results over the whole temperature range, monitored in production.
125/135
ST72104G, ST72215G, ST72216G, ST72254G
14 PACKAGE CHARACTERISTICS
14.1 PACKAGE MECHANICAL DATA
Figure 96. 32-Pin Shrink Plastic Dual In Line Package
mm
inches
Dim.
E
Min Typ Max Min Typ Max
A
A1
A2
b
3.56 3.76 5.08 0.140 0.148 0.200
See Lead Detail
0.51
0.020
3.05 3.56 4.57 0.120 0.140 0.180
0.36 0.46 0.58 0.014 0.018 0.023
C
eA
b1
b
b1 0.76 1.02 1.40 0.030 0.040 0.055
e
B
C
D
0.20 0.25 0.36 0.008 0.010 0.014
27.43 27.94 28.45 1.080 1.100 1.120
9.91 10.41 11.05 0.390 0.410 0.435
7.62 8.89 9.40 0.300 0.350 0.370
e
3
D
E
E1
e
A
2
N
1.78
0.070
0.400
A
L
eA
eB
L
10.16
E
1
A
1
12.70
0.500
e
2.54 3.05 3.81 0.100 0.120 0.150
VR01725J
1
N/2
Number of Pins
N
32
Figure 97. 28-Pin Plastic Small Outline Package, 300-mil Width
mm
inches
Typ
Dim.
Min Typ Max Min
Max
A
2.35
2.65 0.0926
0.30 0.0040
0.51 0.013
0.32 0.0091
18.10 0.6969
7.60 0.2914
0.1043
0.0118
0.020
A1 0.10
B
C
D
E
e
0.33
0.23
0.0125
0.7125
0.2992
17.70
7.40
1.27
0.0500
H
h
10.01
0.25
10.64 0.394
0.74 0.010
0°
0.419
0.029
8°
K
L
0.41
1.27 0.016
0.10
0.050
0.004
G
SO28
Number of Pins
N
28
126/135
ST72104G, ST72215G, ST72216G, ST72254G
14.2 THERMAL CHARACTERISTICS
Symbol
Ratings
Value
Unit
Package thermal resistance (junction to ambient)
SDIP32
SO28
R
60
75
°C/W
thJA
1)
P
Power dissipation
Maximum junction temperature
500
150
mW
D
2)
T
°C
Jmax
Notes:
1. The power dissipation is obtained from the formula P =P +P
where P
is the chip internal power (I xV
)
D
INT
PORT
INT
DD DD
and P
is the port power dissipation determined by the user.
PORT
2. The average chip-junction temperature can be obtained from the formula T = T + P x RthJA.
J
A
D
127/135
ST72104G, ST72215G, ST72216G, ST72254G
14.3 SOLDERING AND GLUEABILITY INFORMATION
Recommended soldering information given only
as design guidelines in Figure 98 and Figure 99.
Recommended glue for SMD plastic packages
dedicated to molding compound with silicone:
■ Heraeus: PD945, PD955
■ Loctite: 3615, 3298
Figure 98. Recommended Wave Soldering Profile (with 37% Sn and 63% Pb)
250
COOLING PHASE
(ROOM TEMPERATURE)
5 sec
200
150
100
50
SOLDERING
PHASE
80°C
Temp. [°C]
PREHEATING
PHASE
Time [sec]
0
20
40
60
80
100
120
140
160
Figure 99. Recommended Reflow Soldering Oven Profile (MID JEDEC)
250
Tmax=220+/-5°C
for 25 sec
200
150
100
50
150 sec above 183°C
90 sec at 125°C
Temp. [°C]
ramp down natural
2°C/sec max
ramp up
2°C/sec for 50sec
Time [sec]
0
100
200
300
400
14.4 PACKAGE/SOCKET FOOTPRINT PROPOSAL
Table 21. Suggested List of SDIP32 Socket Types
Same
Footprint
Package / Probe
Adaptor / Socket Reference
Socket Type
Textool
SDIP32
EMU PROBE
TEXTOOL
232-1291-00
X
Table 22. Suggested List of SO28 Socket Types
Same
Footprint
Package / Probe
Adaptor / Socket Reference
Socket Type
ENPLAS
OTS-28-1.27-04
IC51-0282-334-1
Open Top
SO28
YAMAICHI
Clamshell
EMU PROBE
Adapter from SO28 to SDIP32 footprint (delivered with emulator)
X
SMD to SDIP
128/135
ST72104G, ST72215G, ST72216G, ST72254G
15 DEVICE CONFIGURATION AND ORDERING INFORMATION
Each device is available for production in user pro-
grammable versions (FLASH) as well as in factory
coded versions (ROM). FLASH devices are
shipped to customers with a default content (FFh),
while ROM factory coded parts contain the code
supplied by the customer. This implies that FLASH
devices have to be configured by the customer us-
ing the Option Bytes while the ROM devices are
factory-configured.
USER OPTION BYTE 1
Bit 7 = CFC Clock filter control on/off
This option bit enables or disables the clock filter
(CF) features.
0: Clock filter enabled
1: Clock filter disabled
Bit 6:4 = OSC[2:0] Oscillator selection
These three option bits can be used to select the
main oscillator as shown in Table 24.
Bit 3:2 = LVD[1:0] Low voltage detection selection
These option bits enable the LVD block with a se-
lected threshold as shown in Table 25.
15.1 OPTION BYTES
The two option bytes allow the hardware configu-
ration of the microcontroller to be selected.
The option bytes have no address in the memory
map and can be accessed only in programming
mode (for example using a standard ST7 program-
ming tool). The default content of the FLASH is
fixed to FFh.
In masked ROM devices, the option bytes are
fixed in hardware by the ROM code (see option
list).
Bit 1 = WDG HALT Watchdog and halt mode
This option bit determines if a RESET is generated
when entering HALT mode while the Watchdog is
active.
0: No Reset generation when entering Halt mode
1: Reset generation when entering Halt mode
Bit 0 = WDG SW Hardware or software watchdog
This option bit selects the watchdog type.
0: Hardware (watchdog always enabled)
USER OPTION BYTE 0
1: Software (watchdog to be enabled by software)
Table 24. Main Oscillator Configuration
Bit 7:2 = Reserved, must always be 1.
Bit 1 = EXTIT External Interrupt Configuration.
This option bit allows the external interrupt map-
ping to be configured as shown in Table 23.
Selected Oscillator
External Clock (Stand-by)
~4 MHz Internal RC
OSC2 OSC1 OSC0
1
1
1
0
0
0
0
1
1
0
1
1
0
0
1
0
X
1
0
1
0
Table 23. External Interrupt Configuration
1~14 MHz External RC
External IT0
External IT1
EXTIT
Low Power Resonator (LP)
Medium Power Resonator (MP)
Medium Speed Resonator (MS)
High Speed Resonator (HS)
Ports PB7-PB0
Ports PC5-PC0
Ports PA7-PA0
1
Ports PA7-PA0
Ports PC5-PC0
Ports PB7-PB0
0
Table 25. LVD Threshold Configuration
Bit 0 = FMP Full memory protection.
Configuration
LVD1 LVD0
This option bit enables or disables external access
to the internal program memory (read-out protec-
tion). Clearing this bit causes the erasing (to 00h)
of the whole memory (including the option byte).
0: Program memory not read-out protected
1: Program memory read-out protected
1
1
0
0
1
0
1
0
LVD Off
Highest Voltage Threshold ( 4.50V)
Medium Voltage Threshold ( 4.05V)
Lowest Voltage Threshold ( 3.45V)
USER OPTIONBYTE 0
USER OPTION BYTE 1
7
0
7
0
OSC OSC OSC
WDG WDG
HALT SW
Reserved
EXTIT FMP CFC
LVD1 LVD0
2
1
0
Default
Value
1
1
1
1
1
1
1
0
1
1
1
0
1
1
1
1
129/135
ST72104G, ST72215G, ST72216G, ST72254G
15.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE
Customer code is made up of the ROM contents
and the list of the selected options (if any). The
ROM contents are to be sent on diskette, or by
electronic means, with the S19 hexadecimal file
generated by the development tool. All unused
bytes must be set to FFh.
The selected options are communicated to
STMicroelectronics using the correctly completed
OPTION LIST appended.
The STMicroelectronics Sales Organization will be
pleased to provide detailed information on con-
tractual points.
Figure 100. ROM Factory Coded Device Types
TEMP.
PACKAGE RANGE
/
XXX
DEVICE
Code name (defined by STMicroelectronics)
1= standard 0 to +70 °C
6= industrial -40 to +85 °C
7= automotive -40 to +105°C
3 = automotive -40 to +125 °C
B= Plastic DIP
M= Plastic SOIC
ST72104G1, ST72104G2,
ST72215G2, ST72216G1,
ST72254G1, ST72254G2
Figure 101. FLASH User Programmable Device Types
TEMP.
DEVICE PACKAGE RANGE
1= standard 0 to +70 °C
6= industrial -40 to +85 °C
7= automotive -40 to +105°C
3 = automotive -40 to +125 °C
B= Plastic DIP
M= Plastic SOIC
ST72C104G1, ST72C104G2,
ST72C215G2, ST72C216G1,
ST72C254G1, ST72C254G2
130/135
ST72104G, ST72215G, ST72216G, ST72254G
TRANSFER OF CUSTOMER CODE (Cont’d)
MICROCONTROLLEROPTION LIST
Customer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact
Phone No . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
STMicroelectronics references
Device:
[ ] ST72104G1
[ ] ST72104G2
[ ] ST72215G2
[ ] ST72216G1
[ ] ST72254G1
[ ] ST72254G2
Package:
[ ] SDIP32
[ ] SO28 with Standard conditionning (tube)
[ ] SO28 with Tape & Reel conditionning
External Interrupt:
[ ] IT0 interrupt vector Port A, IT1 interrupt vector Port B & C
[ ] IT0 interrupt vector Port A & C, IT1 interrupt vector Port B
Temperature Range:
[ ] 0°C to + 70°C
[ ] - 40°C to + 85°C
[ ] - 40°C to + 105°C
[ ] - 40°C to + 125°C
Clock Source Selection:
[ ] Resonator:
[ ] LP: Low power resonator (1 to 2 MHz)
[ ] MP: Medium power resonator (2 to 4 MHz)
[ ] MS: Medium speed resonator (4 to 8 MHz)
[ ] HS: High speed resonator (8 to 16 MHz)
[ ] RC Network: [ ] Internal
[ ] External
[ ] External Clock
Clock Security System:
[ ] Disabled
[ ] Enabled
Watchdog Selection:
Halt when Watchdog on:
[ ] SoftwareActivation
[ ] Reset
[ ] Hardware Activation
[ ] No reset
Readout Protection:
LVD Reset
[ ] Disabled
[ ] Enabled
[ ] Disabled
[ ] Enabled: [ ] Highest threshold (4.05V/4.30V)
[ ] Medium threshold (3.65V/3.90V)
[ ] Lowest threshold (3.10V/3.35V)
Comments : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply Operating Range in the application: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Notes
Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Date . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
131/135
ST72104G, ST72215G, ST72216G, ST72254G
15.3 DEVELOPMENT TOOLS
STmicroelectronics offers a range of hardware
and software development tools for the ST7 micro-
controller family. Full details of tools available for
the ST7 from third party manufacturers can be ob-
tain from the STMicroelectronics Internet site:
➟ http//mcu.st.com.
STMicroelectronics Tools
Three types of development tool are offered by
ST, all of them connect to a PC via a parallel (LPT)
port: see Table 26 and Table 27 for more details.
Third Party Tools
■ ACTUM
■ BP
■ COSMIC
■ CMX
■ DATA I/O
■ HITEX
■ HIWARE
■ ISYSTEM
■ KANDA
■ LEAP
Tools from these manufacturers include C compli-
ers, emulators and gang programmers.
Table 26. STMicroelectronic Tool Features
1)
In-Circuit Emulation
Programming Capability
Software Included
ST7 CD ROM with:
Yes. (Same features as
ST7 Development Kit
ST7 HDS2 Emulator
HDS2 emulator but without Yes (DIP packages only)
logic analyzer)
– ST7 Assembly toolchain
– STVD7 and WGDB7 powerful
Source Level Debugger for Win
3.1, Win 95 and NT
– C compiler demo versions
– ST Realizer for Win 3.1 and Win
95.
Yes, powerful emulation
features including trace/
logic analyzer
No
ST7 Programming Board
No
Yes (All packages)
– Windows Programming Tools
for Win 3.1, Win 95 and NT
Table 27. Dedicated STMicroelectronics Development Tools
Supported Products
ST7 Development Kit
ST7 HDS2 Emulator
ST7 Programming Board
ST72254G1, ST72C254G1
ST72254G2, ST72C254G2
ST72215G2, ST72C215G2
ST72216G1, ST72C216G1
ST72104G1, ST72C104G1,
ST72104G2, ST72C104G2
ST7MDT1-EPB2/EU
ST7MDT1-EPB2/US
ST7MDT1-EPB2/UK
ST7MDT1-DVP2
ST7MDT1-EMU2B
Note:
1. In-Situ Programming (ISP) interface for FLASH devices.
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15.4 ST7 APPLICATION NOTES
Identification
Description
PROGRAMMING AND TOOLS
AN985
Executing code in ST7 RAM
Using the ST7 indirect addressing mode
AN986
AN987
ST7 in-circuit programming
AN988
Starting with ST7 assembly tool chain
Starting with ST7 Hiware C
AN989
AN1039
AN1064
AN1179
EXAMPLE DRIVERS
AN969
ST7 math utility routines
Writing optimized hiware C language for ST7
Programming ST7 Flash Microcontrollers in Remote ISP Mode (In-Situ Programming)
ST7 SCI communication between the ST7 and a PC
ST7 SPI communication between the ST7 and E PROM
ST7 I C communication between the ST7 and E PROM
ST7 software SPI master communication
AN970
AN971
AN972
AN973
SCI software communication with a PC using ST72251 16-bit timer
Real time clock with the ST7 timer output compare
Driving a buzzer using the ST7 PWM function
AN974
AN976
AN979
Driving an analog keyboard with the ST7 ADC
AN980
ST7 keypad decoding techniques, implementing wake-up on keystroke
Using the ST7 USB microcontroller
AN1017
AN1041
AN1042
AN1044
AN1045
AN1047
AN1048
AN1048
Using ST7 PWM signal to generate analog output (sinusoid)
ST7 routine for I C slave mode management
Multiple interrupt sources management for ST7 MCUs
ST7 software implementation of I C bus master
Managing reception errors with the ST7 SCI peripheral
ST7 software LCD driver
ST7 timer PWM duty cycle switch for true 0% or 100% duty cycle
PRODUCT OPTIMIZATION
AN982
Using ceramic resonators with the ST7
AN1014
AN1070
How to minimize the ST7 power consumption
ST7 checksum selfchecking capability
PRODUCT EVALUATION
AN910
AN990
AN1181
ST7 and ST9 performance benchmarking
ST7 benefits versus industry standard
Electrostatic discharge sensitivity measurement
APPLICATION EXAMPLES
AN1086
ST7 / ST10U435 CAN-Do solutions for car multiplexing
15.5 TO GET MORE INFORMATION
To get the latest information on this product please use the ST web server.➟ http://mcu.st.com/
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16 SUMMARY OF CHANGES
Description of the changes between the current release of the specification and the previous one.
Rev.
Main changes
Date
2.2 Power saving mode corrected in Figure 18 on page 28 and Figure 20 on page 29.
Feb-00
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Notes:
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of useof such information nor for any infringement of patents or other rights of third parties which may result from its use. No license isgranted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
2000 STMicroelectronics - All Rights Reserved.
Purchase of I2C Components by STMicroelectronics conveys a license under the Philips I2C Patent. Rights to use these components in an
I2C system is granted provided that the system conforms to the I2C Standard Specification as defined by Philips.
STMicroelectronics Group of Companies
Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain
Sweden - Switzerland - United Kingdom - U.S.A.
http://www.st.com
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