ST72321J9B5/XXX [STMICROELECTRONICS]
8-BIT, MROM, 8MHz, MICROCONTROLLER, PDIP42, 0.600 INCH, SHRINK, PLASTIC, DIP-42;
| 型号： | ST72321J9B5/XXX |
| 厂家： | 
ST |
| 描述： | 8-BIT, MROM, 8MHz, MICROCONTROLLER, PDIP42, 0.600 INCH, SHRINK, PLASTIC, DIP-42 光电二极管 |
| 文件： | 总176页 (文件大小：1083K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ST72321J, ST72324J/K
8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC,
2
FIVE TIMERS, SPI, SCI, I C INTERFACE
PRODUCT PREVIEW
■ Memories
– 8 to 60K dual voltage High Density Flash (HD-
Flash) or ROM with read-out protection capa-
bility. In-Application Programming and In-
Circuit Programming for HDFlash devices
– 384 to 2K bytes RAM
TQFP32
7 x 7
TQFP44
10 x 10
■ Clock, Reset And Supply Management
– Enhanced reset system
– Enhanced low voltage supervisor (LVD) for
main supply with 3 programmable reset
thresholds and auxiliary voltage detector
(AVD) with interrupt capability
– Clock sources: crystal/ceramic resonator os-
cillators or RC oscillator with PLL and by-pass
for external clock, clock security system.
SDIP32
200 mil
SDIP42
600 mil
– Four Power Saving Modes: Halt, Active-Halt,
Wait and Slow
■ Interrupt Management
■ 3 Communication Interfaces
– SPI synchronous serial interface
– SCI asynchronous serial interface
– I C multimaster interface
– Nested interrupt controller
– 10 interrupt vectors plus TRAP and RESET
– 9/6 external interrupt lines (on 4 vectors)
■ Up to 32 I/O Ports
2
■ 1 Analog Peripheral
– 10-bit ADC with 12 input pins
– 32/24 multifunctional bidirectional I/O lines
– 22/17 alternate function lines
– 12/10 high sink outputs
■ Instruction Set
■ 5 Timers
– 8-bit Data Manipulation
– 63 Basic Instructions
– 17 main Addressing Modes
– 8 x 8 Unsigned Multiply Instruction
– True Bit Manipulation
– Main Clock Controller with: Real time base,
Beep and Clock-out capabilities
– Configurable watchdog timer
– Two 16-bittimers with: 2 input captures, 2 out-
put compares, external clock input on one tim-
er, PWM and pulse generator modes
■ Development Tools
– 8-bit PWMAuto-reload timer with: 4 PWM out-
puts, output compare and time base interrupt,
external clock with event detector
– Full hardware/software development package
– In-Circuit Testing capability
Device Summary
Features
Program memory - bytes
RAM (stack) - bytes
ST72(F)321J9
60K
ST72(F)321J7
48K
ST72(F)324(J/K)6 ST72(F)324(J/K)4
ST72324(J/K)2
8K
32K
16K
2K (256)
1536 (256)
1024 (256)
512 (256)
384 (256)
Watchdog, 16-bit Timers, SPI, SCI, ADC
-
Peripherals
2
PWM ART, I C
-
-
Operating
FLASH: 2.7 to 5.5V with f
≤4MHz or 3.85V to 5.5V with f
≤8MHz
CPU
ROM: 2.7 to 5.5V
CPU
Supply vs. Frequency
ROM: 2.7 to 5.5V with f
≤8MHz
with f
≤8MHz
CPU
CPU
Temperature Range
0°C to 70°C / -10°C to +85 °C / -40°C to +85 °C / -40°C to +105°C / -40°C to +125°C
SDIP42 (JxB), TQFP44 10x10 (JxT),
TQFP44 10x10 (JxT)
Packages
SDIP32 (KxB), TQFP32 7x7 (KxT)
Rev. 1.3
1/176
February 2001
This ispreliminary information on a new product in development or undergoing evaluation. Details aresubject to change without notice.
1
Table of Contents
1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.3 STRUCTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.4 PROGRAM MEMORY READ-OUT PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.5 ICP (IN-CIRCUIT PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.6 IAP (IN-APPLICATION PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.6.1 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.1 PHASE LOCKED LOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.2 MULTI-OSCILLATOR (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.3 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.3.2 Asynchronous External RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.3.3 Internal Low Voltage Detection RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.3.4 Internal Watchdog RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.4 SYSTEM INTEGRITY MANAGEMENT (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.4.1 Low Voltage Detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.4.2 Auxiliary Voltage Detector (AVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.4.3 Clock Security System (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.4.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.4.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.2 MASKING AND PROCESSING FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.3 INTERRUPTS AND LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.4 CONCURRENT & NESTED MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.5 INTERRUPT REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.6 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.6.1 I/O PORT INTERRUPT SENSITIVITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.7 EXTERNAL INTERRUPT CONTROL REGISTER (EICR) . . . . . . . . . . . . . . . . . . . . . . . 37
8 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8.2 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8.3 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
176
8.4 ACTIVE-HALT AND HALT MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
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8.4.1 ACTIVE-HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8.4.2 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
9 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9.2.1 Input Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9.2.2 Output Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9.2.3 Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.4 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.5 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.5.1 I/O Port Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
10 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
10.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
10.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
10.1.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
10.1.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
10.1.4 Hardware Watchdog Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
10.1.5 Using Halt Mode with the WDG (WDGHALT option) . . . . . . . . . . . . . . . . . . . . . . . 50
10.1.6 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
10.1.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
10.1.8 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
10.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK AND BEEPER (MCC/RTC) . 52
10.2.1 Programmable CPU Clock Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
10.2.2 Clock-out Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
10.2.3 Real Time Clock Timer (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
10.2.4 Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
10.2.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
10.2.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
10.2.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
10.3 PWM AUTO-RELOAD TIMER (ART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
10.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
10.3.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
10.3.3 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
10.4 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
10.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
10.4.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
10.4.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
10.4.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
10.4.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
10.4.6 Summary of Timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
10.4.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
10.5 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
10.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
10.5.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
176
10.5.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
10.5.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
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10.5.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
10.5.6 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
10.5.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
10.6 SERIAL COMMUNICATIONS INTERFACE (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
10.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
10.6.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
10.6.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
10.6.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
10.6.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
10.6.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
10.6.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
10.7 I2C BUS INTERFACE (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
10.7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
10.7.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
10.7.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
10.7.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
10.7.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
10.7.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
10.7.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
10.8 10-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
10.8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
10.8.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
10.8.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
10.8.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
10.8.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
10.8.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
11 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
11.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
11.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
11.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
11.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
11.1.4 Indexed (No Offset, Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
11.1.5 Indirect (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
11.1.6 Indirect Indexed (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
11.1.7 Relative mode (Direct, Indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
11.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
12 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
12.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
12.1.1 Minimum and Maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
12.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
12.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
12.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
12.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
12.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
12.2.1 Voltage Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
176
12.2.2 Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
12.2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
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Table of Contents
12.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
12.3.1 General Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
12.3.2 Operating Conditions with Low Voltage Detector (LVD) . . . . . . . . . . . . . . . . . . . . 136
12.3.3 Internal Voltage Detector (IVD) Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
12.3.4 External Voltage Detector (EVD) Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
12.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
12.4.1 RUN and SLOW Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
12.4.2 WAIT and SLOW WAIT Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
12.4.3 HALT and ACTIVE-HALT Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
12.4.4 Supply and Clock Managers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
12.4.5 On-Chip Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
12.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
12.5.1 General Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
12.5.2 External Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
12.5.3 Crystal and Ceramic Resonator Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
12.5.4 RC Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
12.5.5 Clock Security System (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
12.5.6 PLL Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
12.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
12.6.1 RAM and Hardware Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
12.6.2 FLASH Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
12.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
12.7.1 Functional EMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
12.7.2 Electro Magnetic Interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
12.7.3 Absolute Electrical Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
12.7.4 ESD Pin Protection Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
12.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
12.8.1 General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
12.8.2 Output Driving Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
12.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
12.9.1 Asynchronous RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
12.9.2 VPP Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
12.10 TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
12.10.1Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
12.10.28-Bit PWM-ART Auto-Reload Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
12.10.316-Bit Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
12.11 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 159
12.11.1SPI - Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
12.11.2SCI - Serial Communications Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
12.11.3I2C - Inter IC Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
12.12 10-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
13 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
13.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
13.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
176
13.3 SOLDERING AND GLUEABILITY INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
14 ST72321J/K DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . 169
5/176
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Table of Contents
14.1 FLASH OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
14.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . 171
14.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
14.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
14.5 TO GET MORE INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
15 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
176
6/176
1
ST72321J, ST72324J/K
tion set and are available with FLASH or ROM pro-
gram memory.
1 INTRODUCTION
The ST72321J, ST72324K and ST72324J devices
are members of the ST7 microcontroller family.
They can be grouped as follows:
Under software control, all devices can be placed
in WAIT, SLOW, ACTIVE-HALT or HALT mode,
reducing power consumption when the application
is in idle or stand-by state.
– The 32-pin ST72324K devices are designed for
mid-range applications
The enhanced instruction set and addressing
modes of the ST7 offer both power and flexibility to
software developers, enabling the design of highly
efficient and compact application code. In addition
to standard 8-bit data management, all ST7 micro-
controllers feature true bit manipulation, 8x8 un-
signed multiplication and indirect addressing
modes.
– The 42/44-pin ST72321/4J devices target the
same range of applications requiring more than
24 I/O ports.
All devices are based on a common industry-
standard 8-bit core, featuring an enhanced instruc-
Figure 1. Device Block Diagram
8-BIT CORE
ALU
PROGRAM
MEMORY
(8K - 60K Bytes)
RESET
CONTROL
V
PP
RAM
(384 - 2048 Bytes)
V
V
SS
DD
LVD
WATCHDOG
OSC1
OSC2
OSC
MCC/RTC/BEEP
1
I2C
PA7:3
(5 bits on J devices)
(4 bits on K devices)
PORT A
PORT F
TIMER A
BEEP
PF7:6,4,2:0
(6 bits on J devices)
(5 bits on K devices)
1
PWM ART
PB4:0
(5 bits on J devices)
(3 bits on K devices)
PORT B
PORT E
PE1:0
PORT C
TIMER B
SPI
(2 bits)
SCI
PC7:0
(8 bits)
PORT D
PD5:0
(6 bits on J devices)
(2 bits on K devices)
10-BIT ADC
V
AREF
V
SSA
1
On some devices only, see Device Summary on page 1
7/176
3
ST72321J, ST72324J/K
2 PIN DESCRIPTION
Figure 2. 42-Pin SDIP and 44-Pin TQFP Package Pinouts
44 43 42 41 40 39 38 37 36 35 34
PE1 / RDI
V
V
1
33
32
31
30
29
28
27
26
25
24
23
SS_1
DD_1
PWM3 / PB0
PWM2 / PB1
PWM1 / PB2
PWM0 / PB3
ARTCLK / (HS) PB4
AIN0 / PD0
2
PA3 (HS)
3
ei0
ei2
ei3
PC7 / SS / AIN15
4
PC6 / SCK / ICCCLK
PC5 / MOSI / AIN14
PC4 / MISO / ICCDATA
PC3 (HS) / ICAP1_B
PC2 (HS) / ICAP2_B
PC1 / OCMP1_B / AIN13
PC0 / OCMP2_B / AIN12
5
6
7
AIN1 / PD1
8
AIN2 / PD2
9
AIN3 / PD3
ei1
10
AIN4 / PD4
11
12 13 14 15 16 17 18 19 20 21 22
ARTCLK / (HS) PB4
AIN0 / PD0
PB3 / PWM0
PB2 / PWM1
1
ei3
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
2
ei2
PB1 / PWM2
PB0 / PWM3
PE1 / RDI
AIN1 / PD1
AIN2 / PD2
AIN3 / PD3
AIN4 / PD4
AIN5 / PD5
3
4
5
6
PE0 / TDO
V
_2
7
DD
V
8
OSC1
OSC2
AREF
V
9
SSA
MCO / AIN8 / PF0
BEEP / (HS) PF1
10
11
12
13
14
15
16
17
18
19
20
21
V
_2
SS
RESET
ei1
(HS) PF2
V
PP
AIN10 / OCMP1_A / PF4
ICAP1_A / (HS) PF6
EXTCLK_A / (HS) PF7
AIN12 / OCMP2_B / PC0
AIN13 / OCMP1_B / PC1
PA7 (HS) / SCLI
PA6 (HS) / SDAI
PA5 (HS)
PA4 (HS)
V
SS_1
ICAP2_B/ (HS) PC2
ICAP1_B / (HS) PC3
ICCDATA / MISO / PC4
AIN14 / MOSI / PC5
V
DD_1
PA3 (HS)
ei0
PC7 / SS / AIN15
PC6 / SCK / ICCCLK
(HS) 20mA high sink capability
eix associated external interrupt vector
8/176
ST72321J, ST72324J/K
PIN DESCRIPTION (Cont’d)
Figure 3. 32-Pin SDIP Package Pinout
PB3
PB0
(HS) PB4
1
32
ei3
ei1
ei2
AIN0 / PD0
AIN1 / PD1
2
31
30
29
3
PE1 / RDI
PE0 / TDO
V
4
AREF
V
_2
DD
5
V
28
27
26
25
24
23
22
21
20
19
18
17
SSA
MCO / AIN8 / PF0
BEEP / (HS) PF1
OSC1
OSC2
6
7
OCMP1_A / AIN10 / PF4
8
V
_2
SS
ICAP1_A / (HS) PF6
RESET
9
V
EXTCLK_A / (HS) PF7
10
11
12
13
14
15
16
PP
AIN12 / OCMP2_B / PC0
PA7 (HS)
AIN13 / OCMP1_B / PC1
PA6 (HS)
PA4 (HS)
PA3 (HS)
ICAP2_B / (HS) PC2
ICAP1_B / (HS) PC3
ICCDATA/ MISO / PC4
AIN14 / MOSI / PC5
ei0
PC7 / SS / AIN15
PC6 / SCK / ICCCLK
(HS) 20mA high sink capability
eix associated external interrupt vector
Figure 4. 32-Pin TQFP 7x7 Package Pinout
32 31 30 29 28 27 26 25
V
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
OSC1
OSC2
_2
AREF
ei3 ei2
V
SSA
V
MCO / AIN8 / PF0
BEEP / (HS) PF1
SS
ei1
RESET
OCMP1_A / AIN10 / PF4
ICAP1_A / (HS) PF6
V
PP
PA7 (HS)
PA6 (HS)
PA4 (HS)
EXTCLK_A / (HS) PF7
AIN12 / OCMP2_B / PC0
ei0
9 10 11 12 13 14 15
16
(HS) 20mA high sink capability
eix associated external interrupt vector
9/176
ST72321J, ST72324J/K
PIN DESCRIPTION (Cont’d)
For external pin connection guidelines, refer to See “ELECTRICAL CHARACTERISTICS” on page 133.
Legend / Abbreviations for Table 1:
Type:
I = input, O = output, S = supply
A = Dedicated analog input
Input level:
In/Output level: C = CMOS 0.3V /0.7V
DD
DD
C = CMOS 0.3V /0.7V with input trigger
HS = 20mA high sink (on N-buffer only)
T
DD
DD
Output level:
Port and control configuration:
1)
– Input:
float = floating, wpu = weak pull-up, int = interrupt , ana = analog
2)
– Output:
OD = open drain , PP = push-pull
Refer to “I/O PORTS” on page 43 for more details on the software configuration of the I/O ports.
The RESET configuration of each pin is shown in bold. This configuration is valid as long as the device is
in reset state.
Table 1. Device Pin Description
Pin n°
Level
Port
Main
function
(after
Input
Output
Pin Name
Alternate Function
reset)
6
1
2
3
4
5
6
7
8
9
30
31
32
1
2
3
PB4 (HS)/ARTCLK
PD0/AIN0
I/O C
I/O C
I/O C
I/O C
I/O C
I/O C
I/O C
S
HS
X
X
X
X
X
X
X
ei3
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Port B4 PWM-ART External Clock
Port D0 ADC Analog Input 0
Port D1 ADC Analog Input 1
Port D2 ADC Analog Input 2
Port D3 ADC Analog Input 3
Port D4 ADC Analog Input 4
Port D5 ADC Analog Input 5
Analog Reference Voltage for ADC
Analog Ground Voltage
T
T
T
T
T
T
T
7
X
X
X
X
X
X
8
PD1/AIN1
X
9
PD2 / AIN2
PD3/AIN3
X
10
11
12
13
14
X
PD4/AIN4
X
PD5/AIN5
X
1
2
4
5
V
V
AREF
SSA
S
Main clock
ADC Analog
15 10
3
4
6
7
PF0/MCO/AIN8
I/O C
X
ei1
ei1
X
X
Port F0
T
out (f /2) Input 8
OSC
16 11
17 12
PF1 (HS)/BEEP
PF2 (HS)
I/O C
I/O C
HS
HS
X
X
X
X
X
X
Port F1 Beep signal output
Port F2
T
T
ei1
Timer A Out-
Port F4 put Com-
pare 1
PF4/OCMP1_A/
AIN10
ADC Analog
Input 10
18 13
5
8
I/O C
X
X
X
X
X
T
19 14
20 15
6
7
9
PF6 (HS)/ICAP1_A I/O C
HS
HS
X
X
X
X
X
X
X
X
Port F6 Timer A Input Capture 1
T
T
PF7 (HS)/
I/O C
Timer A External Clock
10
Port F7
Source
EXTCLK_A
21
22
V
V
S
S
Digital Main Supply Voltage
Digital Ground Voltage
DD_0
SS_0
Timer B Out-
ADC Analog
PC0/OCMP2_B/
AIN12
23 16
8
11
I/O C
X
X
X
X
X
Port C0 put Com-
Input 12
T
pare 2
10/176
ST72321J, ST72324J/K
Pin n°
Level
Port
Main
function
(after
Input
Output
Pin Name
Alternate Function
reset)
Timer B Out-
Port C1 put Com-
pare 1
PC1/OCMP1_B/
AIN13
ADC Analog
Input 13
24 17
9
12
I/O C
X
X
X
X
X
T
25 18 10 13 PC2 (HS)/ICAP2_B I/O C
26 19 11 14 PC3 (HS)/ICAP1_B I/O C
HS
HS
X
X
X
X
X
X
X
X
Port C2 Timer B Input Capture 2
Port C3 Timer B Input Capture 1
T
T
SPI Master
ICC Data In-
Port C4 In / Slave
put
PC4/MISO/ICCDA-
TA
27 20 12 15
I/O C
X
X
X
X
T
Out Data
SPI Master
ADC Analog
28 21 13 16 PC5/MOSI/AIN14
29 22 14 17 PC6/SCK/ICCCLK
I/O C
I/O C
I/O C
X
X
X
X
X
X
X
X
X
X
X
Port C5 Out / Slave
Input 14
T
T
In Data
SPI Serial
Clock
ICC Clock
Output
Port C6
SPI Slave
Port C7 Select (ac-
tive low)
ADC Analog
Input 15
30 23 15 18 PC7/SS/AIN15
31 24 16 19 PA3 (HS)
X
X
X
X
X
X
T
T
I/O C
S
HS
ei0
Port A3
32 25
33 26
V
V
Digital Main Supply Voltage
Digital Ground Voltage
Port A4
DD_1
SS_1
S
34 27 17 20 PA4 (HS)
35 28 PA5 (HS)
I/O C
I/O C
I/O C
I/O C
HS
HS
HS
HS
X
X
X
X
X
X
X
X
T
T
X
X
T
T
T
T
Port A5
2
2)
36 29 18 21 PA6 (HS)/SDAI
37 30 19 22 PA7 (HS)/SCLI
Port A6 I C Data
2
2)
Port A7 I C Clock
Must be tied low. In the programming
mode when available, this pin acts as
38 31 20 23 V
I
PP
the programming voltage input V
.
PP
See Section 12.9.2 for more details.
Top priority non maskable interrupt.
Digital Ground Voltage
39 32 21 24 RESET
40 33 22 25 V
I/O C
S
T
SS_2
Resonator oscillator inverter output or
capacitor input for RC oscillator
41 34 23 26 OSC2
O
External clock input or Resonator os-
cillator inverter input or resistor input
for RC oscillator
42 35 24 27 OSC1
I
43 36 25 28 V
S
Digital Main Supply Voltage
Port E0 SCI Transmit Data Out
Port E1 SCI Receive Data In
Port B0 PWM Output 3
Port B1 PWM Output 2
Port B2 PWM Output 1
Port B3 PWM Output 0
DD_2
44 37 26 29 PE0/TDO
I/O C
I/O C
I/O C
I/O C
I/O C
I/O C
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
T
T
T
T
T
T
1
2
3
4
5
38 27 30 PE1/RDI
39 28 31 PB0/PWM3
ei2
40
41
PB1/PWM2
PB2/PWM1
ei2
ei2
42 29 32 PB3/PWM0
ei2
Notes:
1. In the interrupt input column, “eiX” defines the associated external interrupt vector. If the weak pull-up
11/176
ST72321J, ST72324J/K
column (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input,
else the configuration is floating interrupt input.
2. In the open drain output column, “T” defines a true open drain I/O (P-Buffer and protection diode to V
DD
are not implemented). See See “I/O PORTS” on page 43. and Section 12.8 I/O PORT PIN CHARACTER-
ISTICS for more details.
3. OSC1 and OSC2 pins connect a crystal/ceramic resonator, an RC oscillator, or an external source to
the on-chip oscillator; see Section 1 INTRODUCTION and Section 12.5 CLOCK AND TIMING CHARAC-
TERISTICS for more details.
12/176
ST72321J, ST72324J/K
3 REGISTER & MEMORY MAP
As shown in Figure 5, the MCU is capable of ad-
dressing 64K bytes of memories and I/O registers.
ry. The RAM space includes up to 256 bytes for
the stack from 0100h to 01FFh.
The available memory locations consist of 128
bytes of register locations, up to 1024 bytes of
RAM and up to 32 Kbytes of user program memo-
The highest address bytes contain the user reset
and interrupt vectors.
Figure 5. Memory Map
0000h
0080h
HW Registers
(see Table 2)
Short Addressing
RAM (zero page)
007Fh
0080h
00FFh
0100h
RAM
(2048,1536,1024
512,384 Bytes)
256 Bytes Stack
1000h
01FFh
0200h
087Fh
0880h
60 KBytes
16-bit Addressing
RAM
4000h
Reserved
027Fh
or 047Fh
or 067Fh
or 087Fh
48 KBytes
0FFFh
1000h
8000h
C000h
Program Memory
(60K,48K,32K,16K,8K)
32 KBytes
16 KBytes
FFDFh
FFE0h
E000h
FFFFh
Interrupt & Reset Vectors
(see Table 6)
8 Kbytes
FFFFh
Table 2. Hardware Register Map
Register
Label
Reset
Status
Address
Block
Register Name
Remarks
1)
0000h
0001h
0002h
PADR
PADDR
PAOR
Port A Data Register
Port A Data Direction Register
Port A Option Register
00h
R/W
R/W
R/W
2)
Port A
Port B
00h
00h
1)
0003h
0004h
0005h
PBDR
PBDDR
PBOR
Port B Data Register
Port B Data Direction Register
Port B Option Register
00h
R/W
R/W
R/W
2)
00h
00h
1)
0006h
0007h
0008h
PCDR
PCDDR
PCOR
Port C Data Register
Port C Data Direction Register
Port C Option Register
00h
R/W
R/W
R/W
Port C
00h
00h
1)
0009h
000Ah
000Bh
PDADR
PDDDR
PDOR
Port D Data Register
Port D Data Direction Register
Port D Option Register
00h
R/W
R/W
R/W
2)
Port D
00h
00h
13/176
ST72321J, ST72324J/K
Register
Label
Reset
Status
Address
Block
Register Name
Remarks
1)
000Ch
000Dh
000Eh
PEDR
PEDDR
PEOR
Port E Data Register
Port E Data Direction Register
Port E Option Register
00h
R/W
R/W
R/W
2)
2)
2)
Port E
Port F
00h
00h
1)
000Fh
0010h
0011h
PFDR
PFDDR
PFOR
Port F Data Register
Port F Data Direction Register
Port F Option Register
00h
R/W
R/W
R/W
2)
00h
00h
0012h
to
Reserved Area (6 Bytes)
0017h
2
0018h
0019h
001Ah
001Bh
001Ch
001Dh
001Eh
I2CCR
I C Control Register
00h
00h
00h
00h
00h
00h
00h
R/W
2
I2CSR1
I2CSR2
I2CCCR
I2COAR1
I2COAR2
I2CDR
I C Status Register 1
Read Only
Read Only
R/W
R/W
R/W
2
I C Status Register 2
2
2
I C
I C Clock Control Register
2
I C Own Address Register 1
2
I C Own Address Register2
2
I C Data Register
R/W
001Fh
0020h
Reserved Area (2 Bytes)
0021h
0022h
0023h
SPIDR
SPICR
SPICSR
SPI Data I/O Register
SPI Control Register
SPI Control/Status Register
xxh
0xh
00h
R/W
R/W
R/W
SPI
ITC
0024h
0025h
0026h
0027h
ITSPR0
ITSPR1
ITSPR2
ITSPR3
Interrupt Software Priority Register 0
Interrupt Software Priority Register 1
Interrupt Software Priority Register 2
Interrupt Software Priority Register 3
FFh
FFh
FFh
FFh
R/W
R/W
R/W
R/W
0028h
0029h
002Ah
002Bh
EICR
External Interrupt Control Register
Flash Control/Status Register
00h
00h
7Fh
R/W
R/W
R/W
FLASH
FCSR
WATCHDOG
WDGCR
SICSR
Watchdog Control Register
System Integrity Control/Status Register
000x 000x b R/W
002Ch
002Dh
MCCSR
MCCBCR
Main Clock Control / Status Register
Main Clock Controller: Beep Control Register
00h
00h
R/W
R/W
MCC
002Eh
to
Reserved Area (3 Bytes)
0030h
14/176
ST72321J, ST72324J/K
Register
Label
Reset
Address
Block
Register Name
Remarks
Status
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
TACR2
TACR1
TACSR
TAIC1HR
TAIC1LR
TAOC1HR
TAOC1LR
TACHR
Timer A Control Register 2
Timer A Control Register 1
Timer A Control/Status Register
Timer A Input Capture 1 High Register
Timer A Input Capture 1 Low Register
Timer A Output Compare 1 High Register
Timer A Output Compare 1 Low Register
Timer A Counter High Register
00h
00h
xxh
xxh
xxh
80h
00h
FFh
FCh
FFh
FCh
xxh
xxh
80h
00h
R/W
R/W
R/W
Read Only
Read Only
R/W
R/W
TIMER A
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
R/W
TACLR
Timer A Counter Low Register
TAACHR
TAACLR
TAIC2HR
TAIC2LR
TAOC2HR
TAOC2LR
Timer A Alternate Counter High Register
Timer A Alternate Counter Low Register
Timer A Input Capture 2 High Register
Timer A Input Capture 2 Low Register
Timer A Output Compare 2 High Register
Timer A Output Compare 2 Low Register
R/W
0040h
Reserved Area (1 Byte)
0041h
0042h
0043h
0044h
0045h
0046h
0047h
0048h
0049h
004Ah
004Bh
004Ch
004Dh
004Eh
004Fh
TBCR2
TBCR1
TBCSR
TBIC1HR
TBIC1LR
TBOC1HR
TBOC1LR
TBCHR
Timer B Control Register 2
Timer B Control Register 1
Timer B Control/Status Register
Timer B Input Capture 1 High Register
Timer B Input Capture 1 Low Register
Timer B Output Compare 1 High Register
Timer B Output Compare 1 Low Register
Timer B Counter High Register
00h
00h
xxh
xxh
xxh
80h
00h
FFh
FCh
FFh
FCh
xxh
xxh
80h
00h
R/W
R/W
R/W
Read Only
Read Only
R/W
R/W
TIMER B
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
R/W
TBCLR
Timer B Counter Low Register
TBACHR
TBACLR
TBIC2HR
TBIC2LR
TBOC2HR
TBOC2LR
Timer B Alternate Counter High Register
Timer B Alternate Counter Low Register
Timer B Input Capture 2 High Register
Timer B Input Capture 2 Low Register
Timer B Output Compare 2 High Register
Timer B Output Compare 2 Low Register
R/W
0050h
0051h
0052h
0053h
0054h
0055h
0056h
0057h
SCISR
SCIDR
SCIBRR
SCICR1
SCICR2
SCIERPR
SCI Status Register
SCI Data Register
SCI Baud Rate Register
SCI Control Register 1
SCI Control Register 2
SCI Extended Receive Prescaler Register
Reserved area
SCI Extended Transmit Prescaler Register
C0h
xxh
Read Only
R/W
00xx xxxx b R/W
xxh
00h
00h
---
R/W
R/W
R/W
SCI
SCIETPR
00h
R/W
0058h
to
Reserved Area (24 Bytes)
006Fh
0070h
0071h
0072h
ADCCSR
ADCDRH
ADCDRL
Control/Status Register
Data High Register
Data Low Register
00h
xxh
R/W
Read Only
ADC
0000 00xx b Read Only
15/176
ST72321J, ST72324J/K
Register
Label
Reset
Status
Address
Block
Register Name
Remarks
0073h
0074h
0075h
0076h
0077h
PWMDCR3 PWM AR Timer Duty Cycle Register 3
PWMDCR2 PWM AR Timer Duty Cycle Register 2
PWMDCR1 PWM AR Timer Duty Cycle Register 1
PWMDCR0 PWM AR Timer Duty Cycle Register 0
00h
00h
00h
00h
00h
R/W
R/W
R/W
R/W
R/W
PWMCR
PWM AR Timer Control Register
0078h
0079h
007Ah
PWM ART
ARTCSR
ARTCAR
ARTARR
Auto-Reload Timer Control/Status Register
Auto-Reload Timer Counter Access Register
Auto-Reload Timer Auto-Reload Register
00h
00h
00h
R/W
R/W
R/W
007Bh
007Ch
007Dh
ARTICCSR AR Timer Input Capture Control/Status Reg.
00h
00h
00h
R/W
Read Only
Read Only
ARTICR1
ARTICR2
AR Timer Input Capture Register 1
AR Timer Input Capture Register 1
007Eh
007Fh
Reserved Area (2 Bytes)
Legend: x=undefined, R/W=read/write
Notes:
1. The contents of the I/O port DR registers are readable only in output configuration. In input configura-
tion, the values of the I/O pins are returned instead of the DR register contents.
2. The bits associated with unavailable pins must always keep their reset value.
16/176
ST72321J, ST72324J/K
4 FLASH PROGRAM MEMORY
4.1 Introduction
4.3 Structure
The ST7 dual voltage High Density Flash
The Flash memory is organised in sectors and can
be used for both code and data storage.
(HDFlash) is a non-volatile memory that can be
electrically erased as a single block or by individu-
al sectors and programmed on a Byte-by-Byte ba-
Depending on the overall Flash memory size in the
microcontroller device, there are up to three user
sectors (see Table 3). Each of these sectors can
be erased independently to avoid unnecessary
erasing of the whole Flash memory when only a
partial erasing is required.
sis using an external V supply.
PP
The HDFlash devices can be programmed and
erased off-board (plugged in a programming tool)
or on-board using ICP (In-Circuit Programming) or
IAP (In-Application Programming).
The first two sectors have a fixed size of 4 Kbytes
(see Figure 6). They are mapped in the upper part
of the ST7 addressing space so the reset and in-
terrupt vectors are located in Sector 0 (F000h-
FFFFh).
The array matrix organisation allows each sector
to be erased and reprogrammed without affecting
other sectors.
4.2 Main Features
Table 3. Sectors available in Flash devices
■ Three Flash programming modes:
Flash Memory Size
Available Sectors
(bytes)
– Insertion in a programming tool. In this mode,
all sectors including option bytes can be pro-
grammed or erased.
– ICP (In-Circuit Programming). In this mode, all
sectors including option bytes can be pro-
grammed or erased without removing the de-
vice from the application board.
4K
8K
Sector 0
Sectors 0,1
Sectors 0,1, 2
> 8K
– IAP (In-Application Programming) In this
mode, all sectors except Sector 0, can be pro-
grammed or erased without removing the de-
vice from the application board and while the
application is running.
4.4 Program Memory Read-out Protection
The read-out protection is enabled through an op-
tion bit.
■ ICT (In-Circuit Testing) for downloading and
executing user application test patterns in RAM
■ Read-out protection against piracy
When this option is selected, the programs and
data stored in the program memory (Flash or
ROM) are protected against read-out piracy (in-
cluding a re-write protection). In Flash devices,
when this protection is removed by reprogram-
ming the Option Byte, the entire program memory
is first automatically erased.
■ Register Access Security System (RASS) to
prevent accidental programming or erasing
Refer to the Option Byte description for more de-
tails.
Figure 6. Memory Map and Sector Address
4K
8K
10K
16K
24K
32K
48K
60K
DV FLASH
MEMORY SIZE
1000h
3FFFh
7FFFh
9FFFh
BFFFh
D7FFh
DFFFh
EFFFh
FFFFh
SECTOR 2
52 Kbytes
2 Kbytes 8 Kbytes 16 Kbytes 24 Kbytes 40 Kbytes
4 Kbytes
4 Kbytes
SECTOR 1
SECTOR 0
17/176
ST72321J, ST72324J/K
FLASH PROGRAM MEMORY (Cont’d)
4.5 ICP (In-Circuit Programming)
CAUTIONS:
1. If RESET, ICCCLK or ICCDATA pins are used
for other purposes in the application, a serial resis-
tor has to be implemented to avoid a conflict in
case one of the other devices forces the signal lev-
el.
To perform ICP the microcontroller must be
switched to ICC (In-Circuit Communication) mode
by an external controller or programming tool.
Depending on the ICP code downloaded in RAM,
Flash memory programming can be fully custom-
ized (number of bytes to program, program loca-
tions, or selection serial communication interface
for downloading).
2. As soon as the external controller is plugged to
the board, even if an ICC session is not in
progress, the ICCCLK and ICCDATA pins are not
available for the application.
When using an STMicroelectronics or third-party
programming tool that supports ICP and the spe-
cific microcontroller device, the user needs only to
implement the ICP hardware interface on the ap-
plication board (see Figure 7). For more details on
the pin locations, refer to the device pinout de-
scription.
Note: To develop a custom programming tool, re-
fer to the ST7 Flash Programming and ICC Refer-
ence Manual which gives full details on the ICC
protocol hardware and software.
4.6 IAP (In-Application Programming)
ICP needs five signals to be connected to the pro-
gramming tool. These signals are:
This mode uses a BootLoader program previously
stored in Sector 0 by the user (in ICP mode or by
plugging the device in a programming tool).
– RESET: device reset
– V : device power supply ground
– ICCCLK: ICC output serial clock pin
– ICCDATA: ICC input serial data pin
SS
This mode is fully controlled by user software. This
allows it to be adapted to the user application, (us-
er-defined strategy for entering programming
mode, choice of communications protocol used to
fetch the data to be stored, etc.). For example, it is
possible to download code from the SPI, SCI, USB
or CAN interface and program it in the Flash. IAP
mode can be used to program any of the Flash
sectors except Sector 0, which is write/erase pro-
tected to allow recovery in case errors occur dur-
ing the programming operation.
– V : programming voltage
PP
When the device is not yet configured to support
the application clock source (option byte not yet
programmed) or if the option bytes have to be pro-
grammed using ICP, one more pin has to be con-
nected:
– OSCIN: main clock input for external source
When the device is not supplied (V ) by the ap-
DD
plication, one more pin has to be connected:
– V : main power supply
DD
Figure 7. Typical ICP Interface
ICP PROGRAMMING TOOL CONNECTOR
HE10 CONNECTOR TYPE
1
APPLICATION
BOARD
10kΩ
4.7kΩ
C
C
L2
L1
ST7
18/176
ST72321J, ST72324J/K
FLASH PROGRAM MEMORY (Cont’d)
4.6.1 Register Description
FLASH CONTROL/STATUS REGISTER (FCSR)
Read/Write
Reset Value: 0000 0000 (00h)
7
0
0
0
0
0
0
0
0
0
This register is reserved for use by Programming
Tool software. It controls the Flash programming
and erasing operations. For details on customizing
Flash programming methods and In-Circuit Test-
ing, refer to the ST7 Flash Programming and ICC
Reference Manual.
19/176
ST72321J, ST72324J/K
5 CENTRAL PROCESSING UNIT
5.1 INTRODUCTION
5.3 CPU REGISTERS
This CPU has a full 8-bit architecture and contains
six internal registers allowing efficient 8-bit data
manipulation.
The 6 CPU registers shown in Figure 8 are not
present in the memory mapping and are accessed
by specific instructions.
Accumulator (A)
5.2 MAIN FEATURES
The Accumulator is an 8-bit general purpose reg-
ister used to hold operands and the results of the
arithmetic and logic calculations and to manipulate
data.
■ Enable executing 63 basic instructions
■ Fast 8-bit by 8-bit multiply
■ 17 main addressing modes (with indirect
Index Registers (X and Y)
addressing mode)
These 8-bit registers are used to create effective
addresses or as temporary storage areas for data
manipulation. (The Cross-Assembler generates a
precede instruction (PRE) to indicate that the fol-
lowing instruction refers to the Y register.)
■ Two 8-bit index registers
■ 16-bit stack pointer
■ Low power HALT and WAIT modes
■ Priority maskable hardware interrupts
■ Non-maskable software/hardware interrupts
The Y register is not affected by the interrupt auto-
matic procedures.
Program Counter (PC)
The program counter is a 16-bit register containing
the address of the next instruction to be executed
by the CPU. It is made of two 8-bit registers PCL
(Program Counter Low which is the LSB) and PCH
(Program Counter High which is the MSB).
Figure 8. CPU Registers
7
0
ACCUMULATOR
RESET VALUE = XXh
7
0
0
X INDEX REGISTER
Y INDEX REGISTER
RESET VALUE = XXh
7
RESET VALUE = XXh
PCL
8 7
PCH
15
0
PROGRAM COUNTER
RESET VALUE = RESET VECTOR @ FFFEh-FFFFh
7
1
0
1
1
I1 H I0 N Z
C
CONDITION CODE REGISTER
RESET VALUE =
8
1
7
1
X 1 X X X
0
15
STACK POINTER
RESET VALUE = STACK HIGHER ADDRESS
X = Undefined Value
20/176
ST72321J, ST72324J/K
CENTRAL PROCESSING UNIT (Cont’d)
Condition Code Register (CC)
Read/Write
Bit 1 = Z Zero.
This bit is set and cleared by hardware. This bit in-
dicates that the result of the last arithmetic, logical
or data manipulation is zero.
0: The result of the last operation is different from
zero.
Reset Value: 111x1xxx
7
0
1: The result of the last operation is zero.
1
1
I1
H
I0
N
Z
C
This bit is accessed by the JREQ and JRNE test
instructions.
The 8-bit Condition Code register contains the in-
terrupt masks and four flags representative of the
result of the instruction just executed. This register
can also be handled by the PUSH and POP in-
structions.
Bit 0 = C Carry/borrow.
This bit is set and cleared by hardware and soft-
ware. It indicates an overflow or an underflow has
occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.
These bits can be individually tested and/or con-
trolled by specific instructions.
Arithmetic Management Bits
This bit is driven by the SCF and RCF instructions
and tested by the JRC and JRNC instructions. It is
also affected by the “bit test and branch”, shift and
rotate instructions.
Bit 4 = H Half carry.
This bit is set by hardware when a carry occurs be-
tween bits 3 and 4 of the ALU during an ADD or
ADC instructions. It is reset by hardware during
the same instructions.
Interrupt Management Bits
Bit 5,3 = I1, I0 Interrupt
0: No half carry has occurred.
1: A half carry has occurred.
The combination of the I1 and I0 bits gives the cur-
rent interrupt software priority.
This bit is tested using the JRH or JRNH instruc-
tion. The H bit is useful in BCD arithmetic subrou-
tines.
Interrupt Software Priority
Level 0 (main)
I1
1
0
0
1
I0
0
1
0
1
Level 1
Bit 2 = N Negative.
Level 2
This bit is set and cleared by hardware. It is repre-
sentative of the result sign of the last arithmetic,
logical or data manipulation. It’s a copy of the re-
Level 3 (= interrupt disable)
These two bits are set/cleared by hardware when
entering in interrupt. The loaded value is given by
the corresponding bits in the interrupt software pri-
ority registers (IxSPR). They can be also set/
cleared by software with the RIM, SIM, IRET,
HALT, WFI and PUSH/POP instructions.
th
sult 7 bit.
0: The result of the last operation is positive or null.
1: The result of the last operation is negative
(i.e. the most significant bit is a logic 1).
This bit is accessed by the JRMI and JRPL instruc-
tions.
See the interrupt management chapter for more
details.
21/176
ST72321J, ST72324J/K
CENTRAL PROCESSING UNIT (Cont’d)
Stack Pointer (SP)
Read/Write
The least significant byte of the Stack Pointer
(called S) can be directly accessed by a LD in-
struction.
Reset Value: 01 FFh
Note: When the lower limit is exceeded, the Stack
Pointer wraps around to the stack upper limit, with-
out indicating the stack overflow. The previously
stored information is then overwritten and there-
fore lost. The stack also wraps in case of an under-
flow.
15
8
1
0
0
7
0
0
0
0
0
0
The stack is used to save the return address dur-
ing a subroutine call and the CPU context during
an interrupt. The user may also directly manipulate
the stack by means of the PUSH and POP instruc-
tions. In the case of an interrupt, the PCL is stored
at the first location pointed to by the SP. Then the
other registers are stored in the next locations as
shown in Figure 9
SP7
SP6
SP5
SP4
SP3
SP2
SP1 SP0
The Stack Pointer is a 16-bit register which is al-
ways pointing to the next free location in the stack.
It is then decremented after data has been pushed
onto the stack and incremented before data is
popped from the stack (see Figure 9).
– When an interrupt is received, the SP is decre-
mented and the context is pushed on the stack.
Since the stack is 256 bytes deep, the 8 most sig-
nificant bits are forced by hardware. Following an
MCU Reset, or after a Reset Stack Pointer instruc-
tion (RSP), the Stack Pointer contains its reset val-
ue (the SP7 to SP0 bits are set) which is the stack
higher address.
– On return from interrupt, the SP is incremented
and the context is popped from the stack.
A subroutine call occupies two locations and an in-
terrupt five locations in the stack area.
Figure 9. Stack Manipulation Example
CALL
Subroutine
RET
or RSP
PUSH Y
POP Y
IRET
Interrupt
Event
@ 0100h
SP
SP
SP
Y
CC
A
CC
A
CC
A
X
X
X
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
SP
SP
PCH
PCH
PCL
SP
@ 01FFh PCL
Stack Higher Address = 01FFh
0100h
Stack Lower Address =
22/176
ST72321J, ST72324J/K
6 SUPPLY, RESET AND CLOCK MANAGEMENT
The device includes a range of utility features for
securing the application in critical situations (for
example in case of a power brown-out), and re-
ducing the number of external components. An
overview is shown in Figure 11.
Security System (CSS) with Clock Filter and
Backup Safe Oscillator (enabled by option
byte)
6.1 PHASE LOCKED LOOP
For more details, refer to dedicated parametric
section.
If the clock frequency input to the PLL is in the
range 2 to 4 MHz, the PLL can be used to multiply
the frequency by two to obtain an f
of 4 to 8
OSC2
Main features
■ Optional PLL for multiplying the frequency by 2
(enabled by option byte)
■ Reset Sequence Manager (RSM)
MHz. The PLL is enabled by option byte. If the PLL
is disabled, then f /2.
f
OSC2 = OSC
Figure 10. PLL Block Diagram
■ Multi-Oscillator Clock Management (MO)
– 4 Crystal/Ceramic resonator oscillators
– 1 External RC oscillator
– 1 Internal RC oscillator
PLL x 2
/ 2
0
1
f
OSC
f
OSC2
■ System Integrity Management (SI)
PLL OPTION BIT
– Main supply Low voltage detection (LVD)
– Auxiliary Voltage detector (AVD) with interrupt
capability for monitoring the main supplyClock
Figure 11. Clock, Reset and Supply Block Diagram
SYSTEM INTEGRITY MANAGEMENT
CLOCK SECURITY SYSTEM
(CSS)
MAIN CLOCK
CONTROLLER
WITH REALTIME
CLOCK (MCC/RTC)
MULTI-
OSCILLATOR
(MO)
f
OSC2
OSC1
f
f
CPU
f
OSC2
CLOCK
FILTER
SAFE
OSC
OSC
OSC2
PLL
(option)
RESET SEQUENCE
MANAGER
WATCHDOG
TIMER (WDG)
AVD Interrupt Request
RESET
SICSR
AVD AVD
CSS CSS
LVD
RF
WDG
D
RF
(RSM)
0
0
IE
F
IE
CSS Interrupt Request
LOW VOLTAGE
DETECTOR
(LVD)
V
SS
V
DD
AUXILIARY VOLTAGE
DETECTOR
(AVD)
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ST72321J, ST72324J/K
6.2 MULTI-OSCILLATOR (MO)
The main clock of the ST7 can be generated by
four different source types coming from the multi-
oscillator block:
vice. This mode is the most cost effective one with
the drawback of a lower frequency accuracy. Its
frequency is in the range of several MHz.
■ an external source
In this mode, the two oscillator pins have to be tied
to ground.
■ 5 crystal or ceramic resonator oscillators
■ an external RC oscillator
Table 4. ST7 Clock Sources
Hardware Configuration
■ an internal high frequency RC oscillator
Each oscillator is optimized for a given frequency
range in terms of consumption and is selectable
through the option byte. The associated hardware
configuration are shown in Table 4. Refer to the
electrical characteristics section for more details.
ST7
OSC1
OSC2
External Clock Source
In this external clock mode, a clock signal (square,
sinus or triangle) with ~50% duty cycle has to drive
the OSC1 pin while the OSC2 pin is tied to ground.
EXTERNAL
SOURCE
Crystal/Ceramic Oscillators
This family of oscillators has the advantage of pro-
ducing a very accurate rate on the main clock of
the ST7. The selection within a list of 5 oscillators
with different frequency ranges has to be done by
option byte in order to reduce consumption (refer
to Section 14.1 on page 169 for more details on
the frequency ranges). In this mode of the multi-
oscillator, the resonator and the load capacitors
have to be placed as close as possible to the oscil-
lator pins in order to minimize output distortion and
start-up stabilization time. The loading capaci-
tance values must be adjusted according to the
selected oscillator.
ST7
OSC1
OSC2
C
C
L2
L1
LOAD
CAPACITORS
ST7
OSC1
OSC2
These oscillators are not stopped during the
RESET phase to avoid losing time in the oscillator
start-up phase.
R
EX
C
EX
External RC Oscillator
This oscillator allows a low cost solution for the
main clock of the ST7 using only an external resis-
tor and an external capacitor. The frequency of the
external RC oscillator (in the range of some MHz.)
is fixed by the resistor and the capacitor values.
Consequently in this MO mode, the accuracy of
the clock is directly linked to the accuracy of the
discrete components.
ST7
OSC1
OSC2
Internal RC Oscillator
The internal RC oscillator mode is based on the
same principle as the external RC oscillator includ-
ing the resistance and the capacitance of the de-
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6.3 RESET SEQUENCE MANAGER (RSM)
6.3.1 Introduction
The 256 or 4096 CPU clock cycle delay allows the
oscillator to stabilise and ensures that recovery
has taken place from the Reset state. The shorter
or longer clock cycle delay should be selected by
option byte to correspond to the stabilization time
of the external oscillator used in the application
(see Section 14.1 on page 169).
The reset sequence manager includes three RE-
SET sources as shown in Figure 13:
■ External RESET source pulse
■ Internal LVD RESET (Low Voltage Detection)
■ Internal WATCHDOG RESET
The RESET vector fetch phase duration is 2 clock
cycles.
These sources act on the RESET pin and it is al-
ways kept low during the delay phase.
The RESET service routine vector is fixed at ad-
dresses FFFEh-FFFFh in the ST7 memory map.
Figure 12. RESET Sequence Phases
The basic RESET sequence consists of 3 phases
as shown in Figure 12:
RESET
■ Delay depending on the RESET source
INTERNAL RESET
FETCH
DELAY
■ 256 or 4096 CPU clock cycle delay (selected by
256 or 4096 CLOCK CYCLES
VECTOR
option byte)
■ RESET vector fetch
Figure 13. Reset Block Diagram
V
DD
INTERNAL
RESET
f
CPU
R
ON
FILTER
DELAY
RESET
WATCHDOG RESET
LVD RESET
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RESET SEQUENCE MANAGER (Cont’d)
6.3.2 Asynchronous External RESET pin
6.3.3 Internal Low Voltage Detection RESET
The RESET pin is both an input and an open-drain
Two different RESET sequences caused by the in-
ternal LVD circuitry can be distinguished:
output with integrated R
weak pull-up resistor.
ON
This pull-up has no fixed value but varies in ac-
cordance with the input voltage. It can be pulled
low by external circuitry to reset the device. See
electrical characteristics section for more details.
■ Power-On RESET
■ Voltage Drop RESET
The device RESET pin acts as an output that is
pulled low when V <V
(rising edge) or
DD
IT+
A RESET signal originating from an external
V
<V (falling edge) as shown in Figure 14.
DD
IT-
source must have a duration of at least t
in
h(RSTL)in
The LVD filters spikes on V larger than t
avoid parasitic resets.
to
order to be recognized. This detection is asynchro-
nous and therefore the MCU can enter reset state
even in HALT mode.
DD
g(VDD)
6.3.4 Internal Watchdog RESET
The RESET pin is an asynchronous signal which
plays a major role in EMS performance. In a noisy
environment, it is recommended to follow the
guidelines mentioned in the electrical characteris-
tics section.
The RESET sequence generated by a internal
Watchdog counter overflow is shown in Figure 14.
Starting from the Watchdog counter underflow, the
device RESET pin acts as an output that is pulled
low during at least t
.
w(RSTL)out
Two RESET sequences can be associated with
this RESET source: short or long external reset
pulse (see Figure 14).
Starting from the external RESET pulse recogni-
tion, the device RESET pin acts as an output that
is pulled low during at least t
.
w(RSTL)out
Figure 14. RESET Sequences
V
DD
V
V
IT+
IT-
LVD
RESET
SHORT EXT.
RESET
LONG EXT.
RESET
WATCHDOG
RESET
RUN
RUN
RUN
RUN
RUN
DELAY
DELAY
DELAY
DELAY
t
t
w(RSTL)out
h(RSTL)in
t
w(RSTL)out
t
h(RSTL)in
EXTERNAL
RESET
SOURCE
RESET PIN
WATCHDOG
RESET
WATCHDOG UNDERFLOW
INTERNAL RESET (4096 TCPU
)
FETCH VECTOR
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6.4 SYSTEM INTEGRITY MANAGEMENT (SI)
The System Integrity Management block contains
the Low Voltage Detector (LVD), Auxiliary Voltage
Detector (AVD) and Clock Security System (CSS)
functions. It is managed by the SICSR register.
The voltage threshold can be configured by option
byte to be low, medium or high.
Provided the minimum V value (guaranteed for
DD
6.4.1 Low Voltage Detector (LVD)
the oscillator frequency) is above V , the MCU
IT-
The Low Voltage Detector function (LVD) gener-
can only be in two modes:
ates a static reset when the V supply voltage is
DD
– under full software control
– in static safe reset
In these conditions, secure operation is always en-
sured for the application without the need for ex-
ternal reset hardware.
below a V reference value. This means that it
IT-
secures the power-up as well as the power-down
keeping the ST7 in reset.
The V reference value for a voltage drop is lower
IT-
than the V reference value for power-on in order
IT+
During a Low Voltage Detector Reset, the RESET
pin is held low, thus permitting the MCU to reset
other devices.
to avoida parasitic reset when the MCU starts run-
ning and sinks current on the supply (hysteresis).
The LVD Reset circuitry generates a reset when
V
is below:
DD
Notes:
– V when V is rising
IT+
DD
The LVD allows the device to be used without any
external RESET circuitry.
– V when V is falling
The LVD function is illustrated in Figure 15.
IT-
DD
The LVD is an optional function which can be se-
lected by option byte.
Figure 15. Low Voltage Detector vs Reset
V
DD
V
hys
V
V
IT+
IT-
RESET
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SYSTEM INTEGRITY MANAGEMENT (Cont’d)
6.4.2 Auxiliary Voltage Detector (AVD)
6.4.2.1 Monitoring the V Main Supply
DD
The Voltage Detector function (AVD) is based on
an analog comparison between aV and V ref-
The AVD voltage threshold value is relative to the
selected LVD threshold configured by option byte
(see Section 14.1 on page 169).
IT-
IT+
erence value and the V
main supply. The V
DD
IT-
reference value for falling voltage is lower than the
reference value for rising voltage in order to
avoid parasitic detection (hysteresis).
If the VD interrupt is enabled, an interrupt is gener-
V
IT+
ated when the voltage crosses the V
threshold (VDF bit toggles).
or V
IT+
IT-
The output of the AVD comparator is directly read-
able by the application software through a real
time status bit (VDF) inthe SICSR register. This bit
is read only.
Caution: The AVD function is active only if the
LVD is enabled through the option byte.
In the case of a drop in voltage, the VD interrupt
acts as an early warning, allowing software to shut
down safely before the LVD resets the microcon-
troller. See Figure 16.
The interrupt on the rising edge is used to inform
the application that the V warning state is over
DD
Figure 16. Using the AVD to Monitor V (VDS bit=0)
DD
V
DD
Early Warning Interrupt
(Power has dropped, MCU not
not yet in reset)
V
hyst
V
IT+(AVD)
V
IT-(AVD)
V
V
IT+(LVD)
IT-(LVD)
VDF bit
0
1
0
VD INTERRUPT
REQUEST
IF VDIE bit = 1
INTERRUPT PROCESS
INTERRUPT PROCESS
LVD RESET
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SYSTEM INTEGRITY MANAGEMENT (Cont’d)
6.4.3 Clock Security System (CSS)
Limitation detection
The Clock Security System (CSS) protects the
ST7 against main clock problems. To allow the in-
tegration of the security features in the applica-
tions, it is based on a clock filter control and an In-
ternal safe oscillator. The CSS can be enabled or
disabled by option byte.
The automatic safe oscillator selection is notified
by hardware setting the CSSD bit of the SICSR
register. An interrupt can be generated if the CS-
SIE bit has been previously set.
These two bits are described in the SICSR register
description.
6.4.3.1 Clock Filter Control
6.4.4 Low Power Modes
The clock filter is based on a clock frequency limi-
tation function.
Mode
WAIT
Description
No effect on SI. CSS and AVD interrupts
cause the device to exit from Wait mode.
This filter function is able to detect and filter high
frequency spikes on the ST7 main clock.
The CRSR register is frozen.
If the oscillator is not working properly (e.g. work-
ing at a harmonic frequency of the resonator), the
current active oscillator clock can be totally fil-
tered, and then no clock signal is available for the
ST7 from this oscillator anymore. If the original
clock source recovers, the filtering is stopped au-
tomatically and the oscillator supplies the ST7
clock.
The CSS (including the safe oscillator) is
disabled until HALT mode is exited. The
previous CSS configuration resumes when
the MCU is woken up by an interrupt with
“exit from HALT mode” capability or from
the counter reset value when the MCU is
woken up by a RESET. The AVD remains
active, and an AVD interrupt can be used to
exit from Halt mode.
HALT
6.4.3.2 Safe Oscillator Control
The safe oscillator of the CSS block is a low fre-
quency back-up clock source (see Figure 17).
6.4.4.1 Interrupts
The CSS or AVD interrupt events generate an in-
terrupt if the corresponding Enable Control Bit
(CSSIE or AVDIE) is set and the interrupt mask in
the CC register is reset (RIM instruction).
If the clock signal disappears (due to a broken or
disconnected resonator...) during a safe oscillator
period, the safe oscillator delivers a low frequency
clock signalwhich allows the ST7 to perform some
rescue operations.
Enable Exit
Control from
Exit
from
Halt
Event
Flag
Interrupt Event
Automatically, the ST7 clock source switches back
from the safe oscillator if the original clock source
recovers.
Bit
Wait
CSS event detection
(safe oscillator acti- CSSD CSSIE
vated as main clock)
1)
Yes
Yes
No
AVD event
AVDF AVDIE
Yes
Note 1: This interrupt allows to exit from active-
halt mode.
Figure 17. Clock Filter Function and Safe Oscillator Function
f
/2
OSC
f
CPU
f
/2
OSC
f
SFOSC
f
CPU
29/176
ST72321J, ST72324J/K
SYSTEM INTEGRITY MANAGEMENT (Cont’d)
6.4.5 Register Description
SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR)
Read/Write
1: Clock security system interrupt enabled
When the CSS is disabled by OPTION BYTE, the
CSSIE bit has no effect.
Reset Value: 000x 000x (00h)
7
0
Bit 1 = CSSD Clock security system detection
This bit indicates that the safe oscillator of the
Clock Security System block has been selected by
hardware due to a disturbance on the main clock
AVD
IE
AVD LVD
RF
CSS CSS WDG
0
0
F
IE
D
RF
signal (f ). It is set by hardware and cleared by
OSC
Bit 7 = Reserved, must be kept cleared.
reading the SICSR register when the original oscil-
lator recovers.
Bit 6 = AVDIE Voltage Detector interrupt enable
This bit is set and cleared by software. It enables
an interrupt to be generated when the VDF flag
changes (toggles). The pending interrupt informa-
tion is automatically cleared when software enters
the VD interrupt routine.
0: Safe oscillator is not active
1: Safe oscillator has been activated
When the CSS is disabled by OPTION BYTE, the
CSSD bit value is forced to 0.
Bit 0 = WDGRF Watchdog reset flag
0: VD interrupt disabled
This bit indicates that the last Reset was generat-
ed by the Watchdog peripheral. It is set by hard-
ware (watchdog reset) and cleared by software
(writing zero) or an LVD Reset (to ensure a stable
cleared state of the WDGRF flag when CPU
starts).
1: VD interrupt enabled
Bit 5 = AVDF Voltage Detector flag
This read-only bit is set and cleared by hardware.
If the VDIE bit is set, an interrupt request is gener-
ated when the VDF bit changes value.
Combined with the LVDRF flag information, the
flag description is given by the following table.
0: V or V
over V threshold
DD
EVD
EVD
IT+
1: V or V
under V threshold
IT-
DD
RESET Sources
LVDRF WDGRF
External RESET pin
Watchdog
0
0
1
0
1
Bit 4 = LVDRF LVD reset flag
This bit indicates that the last Reset was generat-
ed by the LVD block. It is set by hardware (LVD re-
set) and cleared by software (writing zero). See
WDGRF flag description for more details. When
the LVD is disabled by OPTION BYTE, the LVDRF
bit value is undefined.
LVD
X
Application notes
The LVDRF flag is not cleared when another RE-
SET type occurs (external or watchdog), the
LVDRF flag remains set to keep trace of the origi-
nal failure.
Bit 3 = Reserved, must be kept cleared.
In this case, a watchdog reset can be detected by
software while an external reset can not.
Bit 2 = CSSIE Clock security syst interrupt enable
.
This bit enables the interrupt when a disturbance
is detected by the Clock Security System (CSSD
bit set). It is set and cleared by software.
CAUTION: When the LVD is not activated with the
associated option byte, the WDGRF flag can not
be used in the application.
0: Clock security system interrupt disabled
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7 INTERRUPTS
7.1 INTRODUCTION
When an interrupt request has to be serviced:
– Normal processing is suspended at the end of
the current instruction execution.
The ST7 enhanced interrupt management pro-
vides the following features:
■ Hardware interrupts
– The PC, X, A and CC registers are saved onto
the stack.
■ Software interrupt (TRAP)
– I1 and I0 bits of CC register are set according to
the corresponding values in the ISPRx registers
of the serviced interrupt vector.
■ Nested or concurrent interrupt management
with flexible interrupt priority and level
management:
– The PC isthen loaded with the interrupt vector of
the interrupt to service and the first instruction of
the interrupt service routine is fetched (refer to
“Interrupt Mapping” table for vector addresses).
– Up to 4 software programmable nesting levels
– Up to 16 interrupt vectors fixed by hardware
– 3 non maskable events: TLI, RESET, TRAP
This interrupt management is based on:
The interrupt service routine should end with the
IRET instruction which causes the contents of the
saved registers to be recovered from the stack.
– Bit 5 and bit 3 of the CPU CC register (I1:0),
– Interrupt software priority registers (ISPRx),
Note: As a consequence of the IRET instruction,
the I1 and I0 bits will be restored from the stack
and the program in the previous level will resume.
– Fixed interrupt vector addresses located at the
high addresses of the memory map (FFE0h to
FFFFh) sorted by hardware priority order.
This enhanced interrupt controller guarantees full
upward compatibility with the standard (not nest-
ed) ST7 interrupt controller.
Table 5. Interrupt Software Priority Levels
Interrupt software priority Level
I1
1
0
0
1
I0
0
1
0
1
Level 0 (main)
Level 1
Low
7.2 MASKING AND PROCESSING FLOW
Level 2
The interrupt masking is managed by the I1 and I0
bits of the CC register and the ISPRx registers
which give the interrupt software priority level of
each interrupt vector (see Table 5). The process-
ing flow is shown in Figure 18
High
Level 3 (= interrupt disable)
Figure 18. Interrupt Processing Flowchart
PENDING
INTERRUPT
Y
Y
RESET
TLI
N
Interrupt has the same or a
lower software priority
than current one
N
I1:0
FETCH NEXT
INSTRUCTION
THE INTERRUPT
STAYS PENDING
Y
“IRET”
N
RESTORE PC, X, A, CC
FROM STACK
EXECUTE
INSTRUCTION
STACK PC, X, A, CC
LOAD I1:0 FROM INTERRUPT SW REG.
LOAD PC FROM INTERRUPT VECTOR
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INTERRUPTS (Cont’d)
Servicing Pending Interrupts
3). These sources allow the processor to exit
HALT mode.
■ TLI (Top Level Hardware Interrupt)
As several interrupts can be pending at the same
time, theinterrupt to be taken into account is deter-
mined by the following two-step process:
This hardware interrupt occurs when a specific
edge is detected on the dedicated TLI pin. Its de-
tailed specification is given in the External Inter-
rupts chapter.
– the highest software priority interrupt is serviced,
– if several interrupts have the same software pri-
ority then the interrupt with the highest hardware
priority is serviced first.
■ TRAP (Non Maskable Software Interrupt)
This software interrupt is serviced when the TRAP
instruction is executed. It will be serviced accord-
ing to the flowchart on Figure 18 as a TLI.
Figure 19 describes this decision process.
Figure 19. Priority Decision Process
■ RESET
PENDING
INTERRUPTS
The RESET source has the highest priority in the
ST7. This means that the first current routine has
the highest software priority (level 3) and the high-
est hardware priority.
See the RESET chapter for more details.
Different
Same
SOFTWARE
PRIORITY
Maskable Sources
Maskable interrupt vector sources can be serviced
if the corresponding interrupt is enabled and if its
own interrupt software priority (in ISPRx registers)
is higher than the one currently being serviced (I1
and I0 in CC register). If any of these two condi-
tions is false, the interrupt is latched and thus re-
mains pending.
HIGHEST SOFTWARE
PRIORITY SERVICED
HIGHEST HARDWARE
PRIORITY SERVICED
■ External Interrupts
When an interrupt request is not serviced immedi-
ately, it is latched and then processed when its
software priority combined with the hardware pri-
ority becomes the highest one.
External interrupts allow the processor to exit from
HALT low power mode.
External interrupt sensitivity is software selectable
through the External Interrupt Control register
(EICR).
External interrupt triggered on edge will be latched
and the interrupt request automatically cleared
upon entering the interrupt service routine.
If several input pins of a group connected to the
same interrupt line are selected simultaneously,
these will be logically ORed.
Note 1: The hardware priority is exclusive while
the software one is not. This allows the previous
process to succeed with only one interrupt.
Note 2: RESET, TRAP and TLI are non maskable
and they can be considered as having the highest
software priority in the decision process.
■ Peripheral Interrupts
Different Interrupt Vector Sources
Usually the peripheral interrupts cause the MCU to
exit from HALT mode except those mentioned in
the “Interrupt Mapping” table.
A peripheral interrupt occurs when a specific flag
is set in the peripheral status registers and if the
corresponding enable bit is set in the peripheral
control register.
Two interrupt source types are managed by the
ST7 interrupt controller: the non-maskable type
(RESET, TLI, TRAP) and the maskable type (ex-
ternal or from internal peripherals).
Non-Maskable Sources
These sources are processed regardless of the
state of the I1 and I0 bits of the CC register (see
Figure 18). After stacking the PC, X, A and CC
registers (except for RESET), the corresponding
vector is loaded in the PC register and the I1 and
I0 bits of the CC are set to disable interrupts (level
The general sequence for clearing an interrupt is
based on an access to the status register followed
by a read or write to an associated register.
Note: The clearing sequence resets the internal
latch. A pending interrupt (i.e. waiting for being
serviced) will therefore be lost if the clear se-
quence is executed.
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INTERRUPTS (Cont’d)
7.3 INTERRUPTS AND LOW POWER MODES
7.4 CONCURRENT & NESTED MANAGEMENT
All interrupts allow the processor to exit the WAIT
low power mode. On the contrary, only external
and other specified interrupts allow the processor
to exit the HALT modes (see column “Exit from
HALT” in “Interrupt Mapping” table). When several
pending interrupts are present while exiting HALT
mode, the first one serviced can only be an inter-
rupt with exit from HALT mode capability and it is
selected through the same decision process
shown in Figure 19.
The following Figure 20 and Figure 21 show two
different interrupt management modes. The first is
called concurrent mode and does not allow an in-
terrupt to be interrupted, unlike the nested mode in
Figure 21. The interrupt hardware priority is given
in this order from the lowest to the highest: MAIN,
IT4, IT3, IT2, IT1, IT0, TLI. The software priority is
given for each interrupt.
Warning: A stack overflow may occur without no-
tifying the software of the failure.
Note: If an interrupt, that is not able to Exit from
HALT mode, is pending with the highest priority
when exiting HALT mode, this interrupt is serviced
after the first one serviced.
Figure 20. Concurrent Interrupt Management
SOFTWARE
PRIORITY
LEVEL
I1
I0
TLI
3
1 1
1 1
1 1
1 1
1 1
1 1
IT0
3
IT1
IT1
3
IT2
3
IT3
3
RIM
IT4
3
MAIN
MAIN
3/0
11 / 10
10
Figure 21. Nested Interrupt Management
SOFTWARE
PRIORITY
LEVEL
I1
I0
TLI
3
1 1
1 1
0 0
0 1
1 1
1 1
IT0
3
IT1
IT2
IT1
2
IT2
1
IT3
3
RIM
IT4
IT4
3
MAIN
MAIN
3/0
11 / 10
10
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INTERRUPTS (Cont’d)
7.5 INTERRUPT REGISTER DESCRIPTION
INTERRUPT SOFTWARE PRIORITY REGIS-
TERS (ISPRX)
CPU CC REGISTER INTERRUPT BITS
Read/Write
Read/Write (bit 7:4 of ISPR3 are read only)
Reset Value: 1111 1111 (FFh)
Reset Value: 111x 1010 (xAh)
7
0
7
0
ISPR0
ISPR1
I1_3 I0_3 I1_2 I0_2 I1_1 I0_1 I1_0 I0_0
I1_7 I0_7 I1_6 I0_6 I1_5 I0_5 I1_4 I0_4
1
1
I1
H
I0
N
Z
C
Bit 5, 3 = I1, I0 Software Interrupt Priority
ISPR2 I1_11 I0_11 I1_10 I0_10 I1_9 I0_9 I1_8 I0_8
These two bits indicate the current interrupt soft-
ware priority.
ISPR3
1
1
1
1
I1_13 I0_13 I1_12 I0_12
Interrupt Software Priority Level
I1
1
0
0
1
I0
0
1
0
1
Level 0 (main)
Level 1
Low
These four registers contain the interrupt software
priority of each interrupt vector.
Level 2
– Each interruptvector (except RESET and TRAP)
has corresponding bits in these registers where
its own software priority is stored. This corre-
spondance is shown in the following table.
High
Level 3 (= interrupt disable*)
These two bits are set/cleared by hardware when
entering in interrupt. The loaded value is given by
the corresponding bits in the interrupt software pri-
ority registers (ISPRx).
Vector address
ISPRx bits
FFFBh-FFFAh
FFF9h-FFF8h
...
I1_0 and I0_0 bits*
I1_1 and I0_1 bits
...
They can be also set/cleared by software with the
RIM, SIM, HALT, WFI, IRET and PUSH/POP in-
structions (see “Interrupt Dedicated Instruction
Set” table).
FFE1h-FFE0h
I1_13 and I0_13 bits
*Note: TLI, TRAP and RESET events are non
maskable sources and can interrupt a level 3 pro-
gram.
– Each I1_x and I0_x bit value in the ISPRx regis-
ters has the same meaning as the I1 and I0 bits
in the CC register.
– Level 0 can not be written (I1_x=1, I0_x=0). In
this case, the previously stored value is kept. (ex-
ample: previous=CFh, write=64h, result=44h)
The RESET, TRAP and TLI vectors have no soft-
ware priorities. When one is serviced, the I1 and I0
bits of the CC register are both set.
*Note: Bits in the ISPRx registers which corre-
spond to the TLI can be read and written but they
are not significant in the interrupt process man-
agement.
Caution: If the I1_x and I0_x bits are modified
while the interrupt x is executed the following be-
haviour has to be considered: If the interrupt x is
still pending (new interrupt or flag not cleared) and
the new software priority is higher than the previ-
ous one, the interrupt x is re-entered. Otherwise,
the software priority stays unchanged up to the
next interrupt request (after the IRET of the inter-
rupt x).
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INTERRUPTS (Cont’d)
Table 6. Interrupt Mapping
Exit
Source
Block
Register Priority
Address
Vector
N°
Description
from
Label
Order
1)
HALT
RESET
TRAP
Reset
Software interrupt
Not used
yes
no
FFFEh-FFFFh
FFFCh-FFFDh
FFFAh-FFFBh
N/A
0
1
MCC/RTC
CSS
Main clock controller time base interrupt
Safe oscillator activation interrupt
MCCSR
SICSR
yes
FFF8h-FFF9h
Highest
Priority
2
3
ei0
ei1
ei2
ei3
External interrupt port A3..0
External interrupt port F2..0
External interrupt port B3..0
External interrupt port B7..4
Not used
yes
yes
yes
yes
FFF6h-FFF7h
FFF4h-FFF5h
FFF2h-FFF3h
FFF0h-FFF1h
FFEEh-FFEFh
FFECh-FFEDh
FFEAh-FFEBh
FFE8h-FFE9h
FFE6h-FFE7h
FFE4h-FFE5h
FFE2h-FFE3h
FFE0h-FFE1h
N/A
4
5
6
7
SPI
TIMER A
TIMER B
SCI
SPI peripheral interrupts
TIMER A peripheral interrupts
TIMER B peripheral interrupts
SCI Peripheral interrupts
Auxiliary Voltage detector interrupt
I2C Peripheral interrupts
PWM ART overflow interrupt
SPICSR
TASR
yes
no
8
9
TBSR
no
10
11
12
13
SCISR
no
AVD
SICSR
yes
no
I2C
(see periph)
ARTCSR
Lowest
Priority
PWM ART
yes
Notes:
1. Valid for HALT and ACTIVE-HALT modes except for the MCC/RTC or CSS interrupt source which exits
from ACTIVE-HALT mode only.
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INTERRUPTS (Cont’d)
7.6 EXTERNAL INTERRUPTS
The pending interrupts are cleared writing a differ-
ent value in the ISx[1:0], IPA or IPB bits of the
EICR.
Each external interrupt source can be generated
on four (or five) different events on the pin:
■ Falling edge
Note: External interrupts are masked when an I/O
(configured as input interrupt) of the same inter-
■ Rising edge
■ Falling and rising edge
■ Falling edge and low level
■ Rising edge and high level (only for ei0 and ei2)
rupt vector is forced to V
.
SS
7.6.1 I/O PORT INTERRUPT SENSITIVITY
The external interrupt sensitivity is controlled by
the IPA, IPB and ISxx bits of the EICR register
(Figure 22). This control allows to have up to 4 fully
independent external interrupt source sensitivities.
To guarantee correct functionality, the sensitivity
bits in the EICR register can be modified only
when the I1 and I0 bits of the CC register are both
set to 1 (level 3).
Figure 22. External Interrupt Control bits
ei0
EICR
IS20 IS21
INTERRUPT
SOURCE
PA3
SENSITIVITY
CONTROL
IPA BIT
ei1
INTERRUPT
SOURCE
PF2
SOURCES
SOURCES
PF1
PF0
ei2
PB3
PB2
PB1
PB0
EICR
INTERRUPT
SOURCE
IS10
IS11
SENSITIVITY
CONTROL
IPB BIT
ei3
INTERRUPT
SOURCE
PB4
36/176
ST72321J, ST72324J/K
INTERRUPTS (Cont’d)
7.7 EXTERNAL INTERRUPT CONTROL REGISTER (EICR)
Read/Write
Bit 4:3 = IS2[1:0] ei0 and ei1 sensitivity
The interrupt sensitivity, defined using the IS2[1:0]
bits, is applied to the following external interrupts:
Reset Value: 0000 0000 (00h)
7
0
0
IS11 IS10 IPB IS21 IS20 IPA
0
- ei0 (port A3..0)
Bit 7:6 = IS1[1:0] ei2 and ei3 sensitivity
The interrupt sensitivity, defined using the IS1[1:0]
bits, is applied to the following external interrupts:
- ei2 (port B3..0)
External Interrupt Sensitivity
IS21 IS20
IPA bit =0
IPA bit =1
Falling edge &
low level
Rising edge
& high level
0
0
External Interrupt Sensitivity
IS11 IS10
0
1
1
1
0
1
Rising edge only
Falling edge only
Falling edge only
Rising edge only
IPB bit =0
IPB bit =1
Falling edge &
low level
Rising edge
& high level
0
0
Rising and falling edge
0
1
1
1
0
1
Rising edge only
Falling edge only
Falling edge only
Rising edge only
- ei1 (port F2..0)
Rising and falling edge
IS21 IS20
External Interrupt Sensitivity
- ei3 (port B4)
0
0
1
1
0
1
0
1
Falling edge & low level
Rising edge only
IS11 IS10
External Interrupt Sensitivity
0
0
1
1
0
1
0
1
Falling edge & low level
Rising edge only
Falling edge only
Rising and falling edge
Falling edge only
These 2 bits can be written only when I1 and I0 of
the CC register are both set to 1 (level 3).
Rising and falling edge
These 2 bits can be written only when I1 and I0 of
the CC register are both set to 1 (level 3).
Bit 2 = IPA Interrupt polarity for port A
This bit is used to invert the sensitivity of the port A
[3:0] external interrupts. It can be set and cleared
by software only when I1 and I0 of the CC register
are both set to 1 (level 3).
0: No sensitivity inversion
1: Sensitivity inversion
Bit 5 = IPB Interrupt polarity for port B
This bit is used to invert the sensitivity of the port B
[3:0] external interrupts. It can be set and cleared
by software only when I1 and I0 of the CC register
are both set to 1 (level 3).
0: No sensitivity inversion
1: Sensitivity inversion
Bits 1:0 = Reserved, must always be kept cleared.
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ST72321J, ST72324J/K
INTERRUPTS (Cont’d)
Table 7. Nested Interrupts Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
ei1
SPI
AVD
ei0
MCC + SI
0024h
0025h
0026h
ISPR0
Reset Value
I1_3
1
I0_3
1
I1_2
1
I0_2
1
I1_1
1
I0_1
1
1
1
ei3
ei2
I1_7
1
I0_7
1
I1_6
1
I0_6
1
I1_5
1
I0_5
1
I1_4
1
I0_4
1
ISPR1
Reset Value
SCI
TIMER B
TIMER A
I1_11
1
I0_11
1
I1_10
1
I0_10
1
I1_9
I0_9
1
I1_8
1
I0_8
1
ISPR2
Reset Value
1
PWMART
I2C
0027h
0028h
I1_13
1
I0_13
1
I1_12
1
I0_12
1
ISPR3
Reset Value
1
1
1
1
EICR
Reset Value
IS11
0
IS10
0
IPB
0
IS21
0
IS20
0
IPA
0
0
0
38/176
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8 POWER SAVING MODES
8.1 INTRODUCTION
8.2 SLOW MODE
To give a large measure of flexibility to the applica-
tion in terms of power consumption, four main
power saving modes are implemented in the ST7
(see Figure 23): SLOW, WAIT (SLOW WAIT), AC-
TIVE HALT and HALT.
This mode has two targets:
– Toreduce powerconsumption by decreasingthe
internal clock in the device,
– To adapt the internal clock frequency (f
the available supply voltage.
) to
CPU
After a RESET the normal operating mode is se-
lected by default (RUN mode). This mode drives
the device (CPU and embedded peripherals) by
means of a master clock which is based on the
main oscillator frequency divided or multiplied by 2
SLOW mode is controlled by three bits in the
MCCSR register: the SMS bit which enables or
disables Slow mode and two CPx bits which select
the internal slow frequency (f
).
CPU
(f
).
In this mode, the master clock frequency (f
)
OSC2
OSC2
can be divided by 2, 4, 8 or 16. The CPU and pe-
ripherals are clocked at this lower frequency
From RUN mode, the different power saving
modes may be selected by setting the relevant
register bits or by calling the specific ST7 software
instruction whose action depends on the oscillator
status.
(f
).
CPU
Note: SLOW-WAIT mode is activated when enter-
ing the WAIT mode while the device is already in
SLOW mode.
Figure 23. Power Saving Mode Transitions
Figure 24. SLOW Mode Clock Transitions
High
f
/2
f
/4
f
OSC2
OSC2
OSC2
f
CPU
RUN
f
OSC2
SLOW
WAIT
00
01
CP1:0
SMS
SLOW WAIT
ACTIVE HALT
HALT
NORMAL RUN MODE
REQUEST
NEW SLOW
FREQUENCY
REQUEST
Low
POWER CONSUMPTION
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POWER SAVING MODES (Cont’d)
8.3 WAIT MODE
Figure 25. WAIT Mode Flow-chart
WAIT mode places the MCU in a low power con-
sumption mode by stopping the CPU.
This power saving mode is selected by calling the
‘WFI’ instruction.
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
ON
ON
OFF
10
WFI INSTRUCTION
All peripherals remain active. During WAIT mode,
the I[1:0] bits of the CC register are forced to ‘10’,
to enable all interrupts. All other registers and
memory remain unchanged. The MCU remains in
WAIT mode until an interrupt or RESET occurs,
whereupon the Program Counter branches to the
starting address of the interrupt or Reset service
routine.
N
RESET
Y
N
INTERRUPT
The MCU will remain in WAIT mode until a Reset
or an Interrupt occurs, causing it to wake up.
Y
OSCILLATOR
PERIPHERALS
CPU
ON
OFF
ON
10
Refer to Figure 25.
I[1:0] BITS
256 OR 4096 CPU CLOCK
CYCLE DELAY
OSCILLATOR
PERIPHERALS
CPU
ON
ON
ON
I[1:0] BITS
XX 1)
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Note:
1. Before servicing an interrupt, the CC register is
pushed on the stack. The I[1:0] bits of the CC reg-
ister are set to the current software priority level of
the interrupt routine and recovered when the CC
register is popped.
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POWER SAVING MODES (Cont’d)
8.4 ACTIVE-HALT AND HALT MODES
pending on option byte). Otherwise, the ST7 en-
ters HALT mode for the remaining t
period.
DELAY
ACTIVE-HALT and HALT modes are the two low-
est power consumption modes of the MCU. They
are both entered by executing the ‘HALT’ instruc-
tion. The decision to enter either in ACTIVE-HALT
or HALT mode is given by the MCC/RTC interrupt
enable flag (OIE bit in MCCSR register).
Figure 26. ACTIVE-HALT Timing Overview
ACTIVE
HALT
256 OR 4096 CPU
CYCLE DELAY
RUN
RUN
1)
RESET
OR
INTERRUPT
MCCSR Power Saving Mode entered when HALT
HALT
INSTRUCTION
[MCCSR.OIE=1]
OIE bit
instruction is executed
HALT mode
ACTIVE-HALT mode
FETCH
VECTOR
0
1
Figure 27. ACTIVE-HALT Mode Flow-chart
8.4.1 ACTIVE-HALT MODE
OSCILLATOR
PERIPHERALS
CPU
ON
OFF
OFF
10
2)
HALT INSTRUCTION
ACTIVE-HALT mode is the lowest power con-
sumption mode of the MCU with a real time clock
available. It is entered by executing the ‘HALT’ in-
struction when the OIE bit of the Main Clock Con-
troller Status register (MCCSR) is set (see Section
10.2 on page 52 for more details on the MCCSR
register).
(MCCSR.OIE=1)
I[1:0] BITS
N
RESET
Y
N
3)
INTERRUPT
Y
The MCU can exit ACTIVE-HALT mode on recep-
tion of either an MCC/RTC interrupt, a specific in-
terrupt (see Table 6, “Interrupt Mapping,” on
page 35) or a RESET. When exiting ACTIVE-
HALT mode by means of an interrupt, no 256 or
4096 CPU cycle delay occurs. The CPU resumes
operation by servicing the interrupt or by fetching
the reset vector which woke it up (see Figure 27).
OSCILLATOR
PERIPHERALS
CPU
ON
OFF
ON
4)
I[1:0] BITS
XX
256 OR 4096 CPU CLOCK
CYCLE DELAY
When entering ACTIVE-HALT mode, the I[1:0] bits
in the CC register are forced to ‘10b’ to enable in-
terrupts. Therefore, if an interrupt is pending, the
MCU wakes up immediately.
OSCILLATOR
PERIPHERALS
CPU
ON
ON
ON
4)
I[1:0] BITS
XX
In ACTIVE-HALT mode, only the main oscillator
and its associated counter (MCC/RTC) are run-
ning to keep a wake-up time base. All other periph-
erals are not clocked except those which get their
clock supply from another clock generator (such
as external or auxiliary oscillator).
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Notes:
1. This delay occurs only if the MCU exits ACTIVE-
HALT mode by means of a RESET.
2. Peripheral clocked with an external clock source
can still be active.
3. Only the MCC/RTC interrupt and some specific
interrupts can exit the MCU from ACTIVE-HALT
mode (such as external interrupt). Refer to
Table 6, “Interrupt Mapping,” on page 35 for more
details.
4. Before servicing an interrupt, the CC register is
pushed on the stack. The I[1:0] bits of the CC reg-
ister are set to the current software priority level of
the interrupt routine and restored when the CC
register is popped.
The safeguard against staying locked in ACTIVE-
HALT mode is provided by the oscillator interrupt.
Note: As soon as the interrupt capability of one of
the oscillators is selected (MCCSR.OIE bit set),
entering ACTIVE-HALT mode while the Watchdog
is active does not generate a RESET.
This means that the device cannot spend more
than a defined delay in this power saving mode.
CAUTION: When exiting ACTIVE-HALT mode fol-
lowing an interrupt, OIE bit of MCCSR register
must not be cleared before t
after the inter-
CPU
DELAY
rupt occurs (t
= 256 or 4096 t
delay de-
DELAY
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ST72321J, ST72324J/K
POWER SAVING MODES (Cont’d)
8.4.2 HALT MODE
Figure 29. HALT Mode Flow-chart
The HALT mode is the lowest power consumption
mode of the MCU. It is entered by executing the
‘HALT’ instruction when the OIE bit of the Main
Clock Controller Status register (MCCSR) is
cleared (see Section 10.2 on page 52 for more de-
tails on the MCCSR register).
HALT INSTRUCTION
(MCCSR.OIE=0)
ENABLE
WATCHDOG
0
DISABLE
WDGHALT 1)
1
The MCU can exit HALT mode on reception of ei-
ther a specific interrupt (see Table 6, “Interrupt
Mapping,” on page 35) or a RESET. When exiting
HALT mode by means of a RESET or an interrupt,
the oscillator is immediately turned on and the 256
or 4096 CPU cycle delay is used to stabilize the
oscillator. After the start up delay, the CPU
resumes operation by servicing the interrupt or by
fetching the reset vector which woke it up (see Fig-
ure 29).
When entering HALT mode, the I[1:0] bits in the
CC register are forced to ‘10b’to enable interrupts.
Therefore, if an interrupt is pending, the MCU
wakes up immediately.
WATCHDOG
RESET
OSCILLATOR
OFF
PERIPHERALS 2)
CPU
OFF
OFF
10
I[1:0] BITS
N
RESET
Y
N
INTERRUPT 3)
In HALT mode, the main oscillator is turned off
causing all internal processing to be stopped, in-
cluding the operation of the on-chip peripherals.
All peripherals are not clocked except the ones
which get their clock supply from another clock
generator (such as an external or auxiliary oscilla-
tor).
Y
OSCILLATOR
PERIPHERALS
CPU
ON
OFF
ON
I[1:0] BITS
XX 4)
256 OR 4096 CPU CLOCK
CYCLE DELAY
The compatibility of Watchdog operation with
HALT mode is configured by the “WDGHALT” op-
tion bit of the option byte. The HALT instruction
when executed while the Watchdog system is en-
abled, can generate a Watchdog RESET (see
Section 14.1 on page 169 for more details).
OSCILLATOR
PERIPHERALS
CPU
ON
ON
ON
I[1:0] BITS
XX 4)
Figure 28. HALT Timing Overview
FETCH RESET VECTOR
OR SERVICE INTERRUPT
256 OR 4096 CPU
CYCLE DELAY
RUN
HALT
RUN
Notes:
RESET
OR
INTERRUPT
1. WDGHALT is an option bit. See option byte sec-
tion for more details.
HALT
INSTRUCTION
[MCCSR.OIE=0]
2. Peripheral clocked with an external clock source
can still be active.
FETCH
VECTOR
3. Only some specific interrupts can exit the MCU
from HALT mode (such as external interrupt). Re-
fer to Table 6, “Interrupt Mapping,” on page 35 for
more details.
4. Before servicing an interrupt, the CC register is
pushed on the stack. The I[1:0] bits of the CC reg-
ister are set to the current software priority level of
the interrupt routine and recovered when the CC
register is popped.
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9 I/O PORTS
9.1 INTRODUCTION
programmable using the sensitivity bits in the
EICR register.
The I/O ports offer different functional modes:
– transfer of data through digital inputs and outputs
Each external interrupt vector is linked to a dedi-
cated group of I/O port pins (see pinout description
and interrupt section). If several input pins are se-
lected simultaneously as interrupt source, these
are logically ANDed. For this reason if one of the
interrupt pins is tied low, it masks the other ones.
and for specific pins:
– external interrupt generation
– alternate signal input/output for the on-chip pe-
ripherals.
An I/O port contains up to 8 pins. Each pin can be
programmed independently as digital input (with or
without interrupt generation) or digital output.
The external interrupts are hardware interrupts,
which means that the request latch (not accessible
directly by the application) is automatically cleared
when the corresponding interrupt vector is
fetched. To clear an unwanted pending interrupt
by software, the sensitivity bits in the EICR register
must be modified.
9.2 FUNCTIONAL DESCRIPTION
Each port has 2 main registers:
– Data Register (DR)
9.2.2 Output Modes
– Data Direction Register (DDR)
and one optional register:
– Option Register (OR)
The output configuration is selected by setting the
corresponding DDR register bit. In this case, writ-
ing the DR register applies this digital value to the
I/O pin through the latch. Then reading the DR reg-
ister returns the previously stored value.
Each I/O pin may be programmed using the corre-
sponding register bits in the DDR and OR regis-
ters: bit X corresponding to pin X of the port. The
same correspondence is used for the DR register.
Two different output modes can be selected by
software through the OR register: Output push-pull
and open-drain.
The following description takes into account the
OR register, (for specific ports which do not pro-
vide this register refer to the I/O Port Implementa-
tion section). The generic I/O block diagram is
shown in Figure 30
DR register value and output pin status:
DR
0
Push-pull
Open-drain
Vss
V
SS
DD
1
V
Floating
9.2.1 Input Modes
9.2.3 Alternate Functions
The input configuration is selected by clearing the
corresponding DDR register bit.
When an on-chip peripheral is configured to use a
pin, the alternate function is automatically select-
ed. This alternate function takes priority over the
standard I/O programming.
In this case, reading the DR register returns the
digital value applied to the external I/O pin.
Different input modes can be selected by software
through the OR register.
When the signal is coming from an on-chip periph-
eral, the I/O pin is automatically configured in out-
put mode (push-pull or open drain according to the
peripheral).
Notes:
1. Writing the DR register modifies the latch value
but does not affect the pin status.
When the signal is going to an on-chip peripheral,
the I/O pin must be configured in input mode. In
this case, the pin state is also digitally readable by
addressing the DR register.
2. When switching from input to output mode, the
DR register has to be written first to drive the cor-
rect level on the pin as soon as the port is config-
ured as an output.
External interrupt function
Note: Input pull-up configuration can cause unex-
pected value at the input of the alternate peripheral
input. When an on-chip peripheral use a pin as in-
put and output, this pin has to be configured in in-
put floating mode.
When an I/O is configured as Input with Interrupt,
an event on this I/O can generate anexternal inter-
rupt request to the CPU.
Each pin can independently generate an interrupt
request. The interrupt sensitivity is independently
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I/O PORTS (Cont’d)
Figure 30. I/O Port General Block Diagram
ALTERNATE
OUTPUT
1
0
REGISTER
ACCESS
P-BUFFER
(see table below)
V
DD
ALTERNATE
ENABLE
PULL-UP
(see table below)
DR
V
DD
DDR
PULL-UP
CONDITION
PAD
OR
If implemented
OR SEL
DDR SEL
DR SEL
N-BUFFER
DIODES
(see table below)
ANALOG
INPUT
CMOS
SCHMITT
TRIGGER
1
0
ALTERNATE
INPUT
EXTERNAL
INTERRUPT
SOURCE (ei )
FROM
OTHER
BITS
x
POLARITY
SELECTION
Table 8. I/O Port Mode Options
Configuration Mode
Diodes
Pull-Up
P-Buffer
to V
to V
SS
DD
Floating with/without Interrupt
Pull-up with/without Interrupt
Push-pull
Off
On
Input
Off
On
On
Off
NI
On
Off
NI
Output
Open Drain (logic level)
True Open Drain
NI (see note)
Legend: NI - not implemented
Off - implemented not activated
On - implemented and activated
Note: The diode to V
is not implemented in the
DD
true open drain pads. A local protection between
the pad and V is implemented to protect the de-
SS
vice against positive stress.
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I/O PORTS (Cont’d)
Table 9. I/O Port Configurations
Hardware Configuration
DR REGISTER ACCESS
NOT IMPLEMENTED IN
TRUE OPEN DRAIN
I/O PORTS
V
DD
PULL-UP
CONDITION
R
PU
DR
REGISTER
W
R
DATABUS
PAD
ALTERNATEINPUT
FROM
OTHER
PINS
EXTERNAL INTERRUPT
SOURCE (ei )
x
INTERRUPT
CONDITION
POLARITY
SELECTION
ANALOG INPUT
NOT IMPLEMENTED IN
TRUE OPEN DRAIN
I/O PORTS
DR REGISTER ACCESS
V
DD
R
PU
R/W
DR
REGISTER
DATA BUS
PAD
ALTERNATE
ENABLE
ALTERNATE
OUTPUT
NOT IMPLEMENTED IN
TRUE OPEN DRAIN
I/O PORTS
DR REGISTER ACCESS
V
DD
R
PU
R/W
DR
REGISTER
DATA BUS
PAD
ALTERNATE
ENABLE
ALTERNATE
OUTPUT
Notes:
1. When the I/O port is in input configuration and the associated alternate function is enabled as an output,
reading the DR register will read the alternate function output status.
2. When the I/O port is in output configuration and the associated alternate function is enabled as an input,
the alternate function reads the pin status given by the DR register content.
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I/O PORTS (Cont’d)
CAUTION: The alternate function must not be ac-
tivated as long as the pin is configured as input
with interrupt, in order to avoid generating spurious
interrupts.
9.4 LOW POWER MODES
Mode
WAIT
HALT
Description
No effect on I/O ports. External interrupts
cause the device to exit from WAIT mode.
Analog alternate function
No effect on I/O ports. External interrupts
cause the device to exit from HALT mode.
When the pin is used as an ADC input, the I/O
must be configured as floating input. The analog
multiplexer (controlled by the ADC registers)
switches the analog voltage present on the select-
ed pin to the common analog rail which is connect-
ed to the ADC input.
9.5 INTERRUPTS
The external interrupt event generates an interrupt
if the corresponding configuration is selected with
DDR and OR registers and the interrupt mask in
the CC register is not active (RIM instruction).
It is recommended not to change the voltage level
or loading on any port pin while conversion is in
progress. Furthermore it is recommended not to
have clocking pins located close to a selected an-
alog pin.
Enable Exit
Control from
Exit
from
Halt
Event
Flag
Interrupt Event
WARNING: The analog input voltage level must
be within the limits stated in the absolute maxi-
mum ratings.
Bit
Wait
External interrupt on
selected external
event
DDRx
ORx
-
Yes
Yes
9.3 I/O PORT IMPLEMENTATION
The hardware implementation on each I/O port de-
pends onthe settings in the DDR and OR registers
and specificfeature of the I/O port such as ADC In-
put or true open drain.
Switching these I/O ports from one state to anoth-
er should be done in a sequence that prevents un-
wanted side effects. Recommended safe transi-
tions are illustrated in Figure 31 Other transitions
are potentially risky and should be avoided, since
they are likely to present unwanted side-effects
such as spurious interrupt generation.
Figure 31. Interrupt I/O Port State Transitions
01
00
10
11
INPUT
floating/pull-up
interrupt
INPUT
floating
(reset state)
OUTPUT
open-drain
OUTPUT
push-pull
= DDR, OR
XX
46/176
ST72321J, ST72324J/K
I/O PORTS (Cont’d)
9.5.1 I/O Port Implementation
The I/O port register configurations are summa-
rised as follows.
PA3, PB3, PF2 (without pull-up)
MODE
DDR
OR
0
Standard Ports
floating input
0
0
1
1
floating interrupt input
open drain output
push-pull output
1
PA5:4, PC7:0, PD5:0,
PE1:0, PF7:6, 4
0
1
MODE
DDR
OR
0
floating input
pull-up input
0
0
1
1
1
True Open Drain Ports
PA7:6
open drain output
push-pull output
0
1
MODE
floating input
DDR
0
1
Interrupt Ports
open drain (high sink ports)
PB4, PB2:0, PF1:0 (with pull-up)
MODE
floating input
DDR
OR
0
0
0
1
1
pull-up interrupt input
open drain output
push-pull output
1
0
1
Table 10. Port Configuration
Input
floating
Output
Port
Port A
Port B
Pin name
PA7:6
OR = 0
OR = 1
OR = 0
OR = 1
true open-drain
PA5:4
PA3
floating
floating
floating
floating
floating
floating
floating
floating
floating
floating
pull-up
open drain
open drain
open drain
open drain
open drain
open drain
open drain
open drain
open drain
open drain
push-pull
push-pull
push-pull
push-pull
push-pull
push-pull
push-pull
push-pull
push-pull
push-pull
floating interrupt
floating interrupt
pull-up interrupt
pull-up
PB3
PB4, PB2:0
PC7:0
PD5:0
PE1:0
PF7:6, 4
PF2
Port C
Port D
Port E
pull-up
pull-up
pull-up
Port F
floating interrupt
pull-up interrupt
PF1:0
47/176
ST72321J, ST72324J/K
I/O PORTS (Cont’d)
Table 11. I/O Port Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
Reset Value
of all I/O port registers
0
0
0
0
0
0
0
0
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
0010h
0011h
PADR
PADDR
PAOR
PBDR
PBDDR
PBOR
PCDR
PCDDR
PCOR
PDDR
PDDDR
PDOR
PEDR
MSB
MSB
MSB
MSB
MSB
MSB
LSB
LSB
LSB
LSB
LSB
LSB
PEDDR
PEOR
PFDR
PFDDR
PFOR
48/176
ST72321J, ST72324J/K
10 ON-CHIP PERIPHERALS
10.1 WATCHDOG TIMER (WDG)
10.1.1 Introduction
■ Optional
reset
on
HALT
instruction
(configurable by option byte)
■ Hardware Watchdog selectable by option byte
The Watchdog timer is used to detect the occur-
rence of a software fault, usually generated by ex-
ternal interference or by unforeseen logical condi-
tions, which causes the application program to
abandon its normal sequence. The Watchdog cir-
cuit generates an MCU reset on expiry of a pro-
grammed time period, unless the program refresh-
es the counter’s contents before the T6 bit be-
comes cleared.
10.1.3 Functional Description
The counter value stored in the CR register (bits
T[6:0]), is decremented every 12,288 machine cy-
cles, and the length of the timeout period can be
programmed by the user in 64 increments.
10.1.2 Main Features
If the watchdog is activated (the WDGA bit is set)
and when the 7-bit timer (bits T[6:0]) rolls over
from 40h to 3Fh (T6 becomes cleared), it initiates
a reset cycle pulling low the reset pin for typically
500ns.
■ Programmable timer (64 increments of 12288
CPU cycles)
■ Programmable reset
■ Reset (if watchdog activated) when the T6 bit
reaches zero
Figure 32. Watchdog Block Diagram
RESET
WATCHDOG CONTROL REGISTER (CR)
T5 T0
T6
WDGA
T1
T4
T2
T3
7-BIT DOWNCOUNTER
CLOCK DIVIDER
f
CPU
÷12288
49/176
ST72321J, ST72324J/K
WATCHDOG TIMER (Cont’d)
The application program must write in the CR reg-
ister at regular intervals during normal operation to
prevent an MCU reset. The value to be stored in
the CR register must be between FFh and C0h
(see Table 12 .Watchdog Timing):
10.1.5 Using Halt Mode with the WDG
(WDGHALT option)
The following recommendations apply if Halt mode
is used when the watchdog is enabled.
Recommendations
– The WDGA bit is set (watchdog enabled)
– Make sure that an external event is available to
wake up the microcontroller from Halt mode.
– The T6 bit is set to prevent generating an imme-
diate reset
– Before executing the HALT instruction, refresh
the WDG counter, to avoid an unexpected WDG
reset immediately after waking up the microcon-
troller.
– The T[5:0] bits contain the number of increments
which represents the time delay before the
watchdog produces a reset.
Following a reset, the watchdog is disabled. Once
activated it cannot be disabled, except by a reset.
– When using an external interrupt to wake up the
microcontroller, reinitialize the corresponding I/O
as “Input Pull-up with Interrupt” before executing
the HALT instruction. The main reason for this is
that the I/O may be wrongly configured due to ex-
ternal interference or by an unforeseen logical
condition.
The T6 bit can be used to generate a software re-
set (the WDGA bit is set and the T6 bit is cleared).
If the watchdog is activated, the HALT instruction
will generate a Reset.
Table 12.Watchdog Timing
– For the same reason, reinitialize the level sensi-
tiveness of each external interrupt as a precau-
tionary measure.
f
= 8MHz
CPU
WDG
Counter
Code
min
[ms]
max
[ms]
– The opcode for the HALT instruction is 0x8E. To
avoid an unexpected HALT instruction due to a
program counter failure, it is advised to clear all
occurrences of the data value 0x8E from memo-
ry. For example, avoid defining a constant in
ROM with the value 0x8E.
C0h
FFh
1.536
2.048
130.560
131.072
Notes: The timing variation shown in Table 12 is
due to the unknown status of the prescaler when
writing to the CR register.
– Asthe HALT instructionclears theinterrupt mask
in the CC register to allow interrupts, the user
may choose to clear all pending interrupt bits be-
fore executing the HALT instruction. This avoids
entering other peripheral interrupt routines after
executing the external interrupt routine corre-
sponding to the wake-up event (reset or external
interrupt).
10.1.4 Hardware Watchdog Option
If Hardware Watchdog is selected by option byte,
the watchdog is always active and the WDGA bit in
the CR is not used.
Refer to the Option Byte description.
50/176
ST72321J, ST72324J/K
WATCHDOG TIMER (Cont’d)
10.1.6 Low Power Modes
Mode Description
WAIT No effect on Watchdog.
OIE bit in
MCCSR
register
WDGHALT bit
in Option
Byte
No Watchdog reset is generated. The MCU enters Halt mode. The Watch-
dog counter is decremented once and then stops counting and is no longer
able to generate a watchdog reset until the MCU receives an external inter-
rupt or a reset.
0
0
If an external interrupt is received, the Watchdog restarts counting after
4096 CPU clocks. If a reset is generated, the Watchdog is disabled (reset
state) unless Hardware Watchdog is selected by option byte. For applica-
tion recommendations see Section 10.1.5 below.
HALT
0
1
1
x
A reset is generated.
No reset is generated. The MCU enters Active Halt mode. The Watchdog
counter is not decremented. It stop counting. When the MCU receives an
oscillator interrupt, external interrupt or a reset the Watchdog restarts
counting after 4096 CPU clocks.
10.1.7 Interrupts
Bit 6:0 = T[6:0] 7-bit timer (MSB to LSB).
These bits contain the decremented value. A reset
is produced when it rolls over from 40h to 3Fh (T6
becomes cleared).
None.
10.1.8 Register Description
CONTROL REGISTER (CR)
Read/Write
Reset Value: 0111 1111 (7Fh)
7
0
WDGA T6
T5
T4
T3
T2
T1
T0
Bit 7 = WDGA Activation bit.
This bit is set by software and only cleared by
hardware after a reset. When WDGA = 1, the
watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled
Note: This bit is not used if the hardware watch-
dog option is enabled by option byte.
Table 13. Watchdog Timer Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
WDGCR
Reset Value
WDGA
0
T6
1
T5
1
T4
1
T3
1
T2
1
T1
1
T0
1
002Ah
51/176
ST72321J, ST72324J/K
10.2
MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK AND BEEPER (MCC/RTC)
10.2.2
The Main Clock Controller consists of three differ-
ent functions:
Clock-out Capability
The clock-out capability is an alternate function of
an I/O port pin that outputs a f clock to drive
■
a programmable CPU clock prescaler
OSC2
external devices. It is controlled by the MCO bit in
the MCCSR register.
CAUTION: When selected, the clock out pin sus-
pends the clock during ACTIVE-HALT mode.
■
a clock-out signal to supply external devices
■
a real time clock timer with interrupt capability
Each function can be used independently and si-
multaneously.
10.2.3
Real Time Clock Timer (RTC)
10.2.1
Programmable CPU Clock Prescaler
The counter of the real time clock timer allows an
interrupt to be generated based on an accurate
real time clock. Four different time bases depend-
The programmable CPU clock prescaler supplies
the clock for the ST7 CPU and its internal periph-
erals. It manages SLOW power saving mode (See
Section 8.2 SLOW MODE for more details).
ing directly on f
are available. The whole
OSC2
functionality is controlled by four bits of the MCC-
SR register: TB[1:0], OIE and OIF.
The prescaler selects the f
main clock frequen-
CPU
cy and is controlled by three bits in the MCCSR
register: CP[1:0] and SMS.
When the RTC interrupt is enabled (OIE bit set),
the ST7 enters ACTIVE-HALT mode when the
HALT instruction is executed. See Section 8.4 AC-
TIVE-HALT AND HALT MODES for more details.
CAUTION: The prescaler does not act on the CAN
peripheral clock source. This peripheral is always
supplied by the f
clock source.
10.2.4
Beeper
OSC2
The beep function is controlled by the MCCBCR
register. It can output three selectable frequencies
on the BEEP pin (I/O port alternate function).
Figure 33.
Main Clock Controller (MCC/RTC) Block Diagram
BC1 BC0
MCCBCR
BEEP
MCO
BEEP SIGNAL
GENERATOR
f
OSC2
RTC
COUNTER
MCO CP1 CP0 SMS TB1 TB0 OIE OIF
MCCSR
MCC/RTC INTERRUPT
DIV 2, 4, 8, 16
CPU CLOCK
TO CPU AND
f
CPU
PERIPHERALS
CLOCK TO CAN
PERIPHERAL
52/176
ST72321J, ST72324J/K
MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont’d)
10.2.5
Low Power Modes
Bit 6:5 = CP[1:0] CPU clock prescaler
Mode
Description
These bits select the CPU clock prescaler which is
applied in the different slow modes. Their action is
conditioned by the setting of the SMS bit. These
two bits are set and cleared by software
No effect on MCC/RTC peripheral.
MCC/RTC interrupt cause the device to exit
from WAIT mode.
WAIT
No effect on MCC/RTC counter (OIE bit is
ACTIVE- set), the registers are frozen.
f
in SLOW mode
CP1
CP0
CPU
HALT
MCC/RTC interrupt cause the device to exit
from ACTIVE-HALT mode.
f
f
f
/ 2
/ 4
0
0
1
1
0
1
0
1
OSC2
OSC2
OSC2
MCC/RTC counter and registers are frozen.
MCC/RTC operation resumes when the
MCU is woken up by an interrupt with “exit
from HALT” capability.
/ 8
HALT
f
/ 16
OSC2
10.2.6
Bit 4 = SMS Slow mode select
This bit is set and cleared by software.
0: Normal mode. f = f
Interrupts
The MCC/RTC interrupt event generates an inter-
rupt if the OIE bit of the MCCSR register is set and
the interrupt mask in the CC register is not active
(RIM instruction).
OSC2
CPU
1: Slow mode. f
is given by CP1, CP0
CPU
See Section 8.2 SLOW MODE and Section 10.2
MAIN CLOCK CONTROLLER WITH REAL TIME
CLOCK AND BEEPER (MCC/RTC) for more de-
tails.
Enable Exit
Control from
Exit
from
Halt
Event
Flag
Interrupt Event
Bit
Wait
Time base overflow
event
1)
Bit 3:2 = TB[1:0] Time base control
OIF
OIE
Yes
No
These bits select the programmable divider time
base. They are set and cleared by software.
Note:
The MCC/RTC interrupt wakes up the MCU from
ACTIVE-HALT mode, not from HALT mode.
Time Base
Counter
TB1 TB0
Prescaler
f
=4MHz
f
=8MHz
OSC2
OSC2
32000
64000
4ms
2ms
4ms
0
0
1
1
0
1
0
1
8ms
20ms
50ms
10.2.7
Register Description
160000
400000
10ms
25ms
MCC CONTROL/STATUS REGISTER (MCCSR)
Read/Write
Reset Value: 0000 0000 (00h
)
A modification of the time base is taken into ac-
count at the end of the current period (previously
set) to avoid an unwanted time shift. This allows to
use this time base as a real time clock.
7
0
MCO CP1 CP0 SMS TB1 TB0 OIE
OIF
Bit 1 = OIE Oscillator interrupt enable
This bit set and cleared by software.
0: Oscillator interrupt disabled
1: Oscillator interrupt enabled
This interrupt can be used to exit from ACTIVE-
HALT mode.
Bit 7 = MCO Main clock out selection
This bit enables the MCO alternate function on the
PF0 I/O port. It is set and cleared by software.
0: MCO alternate function disabled (I/O pin free for
general-purpose I/O)
1: MCO alternate function enabled (f
port)
on I/O
OSC2
When this bit is set, calling the ST7 software HALT
instruction enters the ACTIVE-HALT power saving
Note: To reduce power consumption, the MCO
mode
.
function is not active in ACTIVE-HALT mode.
53/176
ST72321J, ST72324J/K
MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont’d)
MCC BEEP CONTROL REGISTER (MCCBCR)
Bit 0 = OIF Oscillator interrupt flag
This bit is set by hardware and cleared by software
reading the MCCSR register. It indicates when set
that the main oscillator has reached the selected
elapsed time (TB1:0).
Read/Write
Reset Value: 0000 0000 (00h)
7
0
0: Timeout not reached
1: Timeout reached
0
0
0
0
0
0
BC1 BC0
CAUTION: The BRES and BSET instructions
must not be used on the MCCSR register to avoid
unintentionally clearing the OIF bit.
Bit 7:2 = Reserved, must be kept cleared.
Bit 1:0 = BC[1:0] Beep control
These 2 bits select the PF1 pin beep capability.
BC1
BC0
Beep mode with f
=8MHz
OSC2
0
0
1
1
0
1
0
1
Off
~2-KHz
Output
Beep signal
~50% duty cycle
~1-KHz
~500-Hz
The beep output signal is available in ACTIVE-
HALT mode but has to be disabled to reduce the
consumption.
Table 14. Main Clock Controller Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
SICSR
Reset Value
VDS
0
VDIE
0
VDF
0
LVDRF
x
CFIE
0
CSSD
0
WDGRF
x
002Bh
002Ch
002Dh
0
MCCSR
Reset Value
MCO
0
CP1
0
CP0
0
SMS
0
TB1
0
TB0
0
OIE
0
OIF
0
MCCBCR
Reset Value
BC1
0
BC0
0
0
0
0
0
0
0
54/176
ST72321J, ST72324J/K
10.3 PWM AUTO-RELOAD TIMER (ART)
10.3.1 Introduction
The Pulse Width Modulated Auto-Reload Timer
on-chip peripheral consists of an 8-bit auto reload
counter with compare/capture capabilities and of a
7-bit prescaler clock source.
– Up to two input capture functions
– External event detector
– Up to two external interrupt sources
The three first modes can be used together with a
single counter frequency.
These resources allow five possible operating
modes:
The timer can be used to wake up the MCU from
WAIT and HALT modes.
– Generation of up to 4 independent PWM signals
– Output compare and Time base interrupt
Figure 34. PWM Auto-Reload Timer Block Diagram
OCRx
DCRx
OEx
OPx
PWMCR
REGISTER
REGISTER
LOAD
PORT
ALTERNATE
FUNCTION
POLARITY
CONTROL
PWMx
COMPARE
8-BIT COUNTER
(CAR REGISTER)
ARR
REGISTER
LOAD
INPUT CAPTURE
CONTROL
ICRx
LOAD
ARTICx
REGISTER
ICSx
ICIEx
ICFx
ICCSR
ICx INTERRUPT
f
EXT
ARTCLK
f
COUNTER
f
CPU
MUX
f
INPUT
PROGRAMMABLE
PRESCALER
ARTCSR
EXCL CC2
CC1
CC0
TCE FCRL OIE
OVF
OVF INTERRUPT
55/176
ST72321J, ST72324J/K
PWM AUTO-RELOAD TIMER (Cont’d)
10.3.2 Functional Description
Counter
When TCE is set, the counter runs at the rate of
the selected clock source.
The free running 8-bit counter is fed by the output
of the prescaler, and is incremented on every ris-
ing edge of the clock signal.
Counter and Prescaler Initialization
After RESET, the counter and the prescaler are
It is possible to read or write the contents of the
counter on the fly by reading or writing the Counter
Access register (CAR).
cleared and f
= f
.
INPUT
CPU
The counter can be initialized by:
– Writing to the ARR register and then setting the
FCRL (Force Counter Re-Load) and the TCE
(Timer Counter Enable) bits in the CSR register.
When a counter overflow occurs, the counter is
automatically reloaded with the contents of the
ARR register (the prescaler is not affected).
– Writing to the CAR counter access register,
Counter clock and prescaler
In both cases the 7-bit prescaler is also cleared,
whereupon counting will start from a known value.
The counter clock frequency is given by:
CC[2:0]
f
= f
/ 2
COUNTER
INPUT
Direct access to the prescaler is not possible.
The timer counter’s input clock (f
) feeds the
INPUT
Output compare control
7-bit programmable prescaler, which selects one
of the 8 available taps of the prescaler, as defined
by CC[2:0] bits in the Control/Status Register
(CSR). Thus the division factor of the prescaler
The timer compare function is based on four differ-
ent comparisons with the counter (one for each
PWMx output). Each comparison is made be-
tween the counter value and an output compare
register (OCRx) value. This OCRx register can not
be accessed directly, it is loaded from the duty cy-
cle register (DCRx) at each overflow of the coun-
ter.
n
can be set to 2 (where n = 0, 1,..7).
This f
frequency source is selected through
INPUT
the EXCL bit of the CSR register and can be either
the f or an external input frequency f
.
EXT
CPU
The clock input to the counter is enabled by the
TCE (Timer Counter Enable) bit in the CSR regis-
ter. When TCE is reset, the counter is stopped and
the prescaler and counter contents are frozen.
This double buffering method avoids glitch gener-
ation when changing the duty cycle on the fly.
Figure 35. Output compare control
fCOUNTER
ARR=FDh
FFh
COUNTER
OCRx
FDh
FEh
FDh
FEh
FFh
FDh
FEh
FFh
FEh
FDh
DCRx
FEh
FDh
PWMx
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ST72321J, ST72324J/K
PWM AUTO-RELOAD TIMER (Cont’d)
Independent PWM signal generation
OPx (output polarity) bit in the PWMCR register.
When the counter reaches the value contained in
one of the output compare register (OCRx) the
corresponding PWMx pin level is restored.
This mode allows up to four Pulse Width Modulat-
ed signals to be generated on the PWMx output
pins with minimum core processing overhead.
This function is stopped during HALT mode.
It should be noted that the reload values will also
affect the value and the resolution of the duty cycle
of the PWM output signal. To obtain a signal on a
PWMx pin, the contents of the OCRx register must
be greater than the contents of the ARR register.
Each PWMx output signal can be selected inde-
pendently using the corresponding OEx bit in the
PWM Control register (PWMCR). When this bit is
set, the corresponding I/O pin is configured as out-
put push-pull alternate function.
The maximum available resolution for the PWMx
duty cycle is:
The PWM signals all have the same frequency
which is controlled by the counter period and the
ARR register value.
Resolution = 1 / (256 - ARR)
Note: To get the maximum resolution (1/256), the
ARR register must be 0. With this maximum reso-
lution, 0% and 100% can be obtained by changing
the polarity.
f
= f
/ (256 - ARR)
PWM
COUNTER
When a counter overflow occurs, the PWMx pin
level is changed depending on the corresponding
Figure 36. PWM Auto-reload Timer Function
255
DUTY CYCLE
REGISTER
(DCRx)
AUTO-RELOAD
REGISTER
(ARR)
000
t
WITH OEx=1
AND OPx=0
WITH OEx=1
AND OPx=1
Figure 37. PWM Signal from 0% to 100% Duty Cycle
fCOUNTER
ARR=FDh
COUNTER
FDh
FEh
FFh
FDh
FEh
FFh
FDh
FEh
OCRx=FCh
OCRx=FDh
OCRx=FEh
OCRx=FFh
t
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ST72321J, ST72324J/K
PWM AUTO-RELOAD TIMER (Cont’d)
Output compare and Time base interrupt
External clock and event detector mode
Using the f external prescaler input clock, the
auto-reload timer can be used as an external clock
event detector. In this mode, the ARR register is
On overflow, the OVF flag of the CSR register is
set and an overflow interrupt request is generated
if the overflow interrupt enable bit, OIE, in the CSR
register, is set. The OVF flag must be reset by the
user software. This interrupt can be used as a time
base in the application.
EXT
used to select the n
number of events to be
EVENT
counted before setting the OVF flag.
n
= 256 - ARR
EVENT
When entering HALT mode while f
is selected,
EXT
all the timer control registers are frozen but the
counter continues to increment. If the OIE bit is
set, the next overflow of the counter will generate
an interrupt which wakes up the MCU.
Figure 38. External Event Detector Example (3 counts)
fEXT=fCOUNTER
ARR=FDh
COUNTER
FDh
FEh
FFh
FDh
FEh
FFh
FDh
OVF
CSR READ
CSR READ
INTERRUPT
IF OIE=1
INTERRUPT
IF OIE=1
t
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ST72321J, ST72324J/K
PWM AUTO-RELOAD TIMER (Cont’d)
Input capture function
This mode allows the measurement of external
signal pulse widths through ICRx registers.
External interrupt capability
This mode allows the Input capture capabilities to
be used as external interrupt sources. The inter-
rupts are generated on the edge of the ARTICx
signal.
Each input capture can generate an interrupt inde-
pendently on a selected input signal transition.
This event is flagged by a set of the corresponding
CFx bits of the Input Capture Control/Status regis-
ter (ICCSR).
The edge sensitivity of the external interrupts is
programmable (CSx bit of ICCSR register) and
they are independently enabled through CIEx bits
of the ICCSR register. After fetching the interrupt
vector, the CFx flags can be read to identify the in-
terrupt source.
These input capture interrupts are enabled
through the CIEx bits of the ICCSR register.
The active transition (falling or rising edge) is soft-
ware programmable through the CSx bits of the
ICCSR register.
During HALT mode, the external interrupts can be
used to wake up the micro (if the CIEx bit is set).
The read only input capture registers (ICRx) are
used to latch the auto-reload counter value when a
transition is detected on the ARTICx pin (CFx bit
set in ICCSR register). After fetching the interrupt
vector, the CFx flags can be read to identify the in-
terrupt source.
Note: After a capture detection, data transfer in
the ICRx register is inhibited until it is read (clear-
ing the CFx bit).
The timer interrupt remains pending while the CFx
flag is set when the interrupt is enabled (CIEx bit
set). This means, the ICRx register has to be read
at each capture event to clear the CFx flag.
The timing resolution is given by auto-reload coun-
ter cycle time (1/f
).
COUNTER
Note: During HALT mode, if both input capture
and external clock are enabled, the ICRx register
value is not guaranteed if the input capture pin and
the external clock change simultaneously.
Figure 39. Input Capture Timing Diagram
fCOUNTER
COUNTER
01h
02h
03h
04h
05h
06h
07h
INTERRUPT
04h
ARTICx PIN
CFx FLAG
xxh
ICRx REGISTER
t
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PWM AUTO-RELOAD TIMER (Cont’d)
10.3.3 Register Description
CONTROL / STATUS REGISTER (CSR)
Read/Write
COUNTER ACCESS REGISTER (CAR)
Read/Write
Reset Value: 0000 0000 (00h)
Reset Value: 0000 0000 (00h)
7
0
7
0
EXCL CC2
CC1
CC0
TCE FCRL
OIE
OVF
CA7
CA6
CA5
CA4
CA3
CA2
CA1
CA0
Bit 7 = EXCLExternal Clock
Bit 7:0 = CA[7:0] Counter Access Data
This bit is set and cleared by software. It selects the
input clock for the 7-bit prescaler.
0: CPU clock.
These bits can be set and cleared either by hard-
ware or by software. The CAR register is used to
read or write the auto-reload counter “on the fly”
(while it is counting).
1: External clock.
Bit 6:4 = CC[2:0] Counter Clock Control
These bits are set and cleared by software. They
determine the prescaler division ratio from f
.
INPUT
AUTO-RELOAD REGISTER (ARR)
Read/Write
f
With f
INPUT
=8 MHz CC2 CC1 CC0
COUNTER
f
8 MHz
4 MHz
2 MHz
1 MHz
500 KHz
250 KHz
125 KHz
62.5 KHz
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
INPUT
Reset Value: 0000 0000 (00h)
f
f
f
/ 2
/ 4
/ 8
INPUT
INPUT
INPUT
7
0
f
/ 16
/ 32
/ 64
/ 128
INPUT
AR7
AR6
AR5
AR4
AR3
AR2
AR1
AR0
f
INPUT
f
INPUT
INPUT
f
Bit 7:0 = AR[7:0]Counter Auto-Reload Data
These bits are set and cleared by software. They
are used to hold the auto-reload value which is au-
tomatically loaded in the counter when an overflow
occurs. At the same time, the PWM output levels
are changed according to the corresponding OPx
bit in the PWMCR register.
Bit 3 = TCE Timer Counter Enable
This bit is set and cleared by software. It puts the
timer in the lowest power consumption mode.
0: Counter stopped (prescaler and counter frozen).
1: Counter running.
Bit 2 = FCRLForce Counter Re-Load
This register has two PWM management func-
tions:
This bit is write-only and any attempt to read it will
yield alogicalzero. When set, itcausesthecontents
of ARR register to be loaded into the counter, and
the content of the prescaler register to be clearedin
order to initialize the timer before starting to count.
– Adjusting the PWM frequency
– Setting the PWM duty cycle resolution
PWM Frequency vs. Resolution:
Bit 1 = OIEOverflow Interrupt Enable
This bit is set and cleared by software. It allows to
enable/disable the interrupt which is generated
when the OVF bit is set.
f
PWM
ARR value Resolution
Min
Max
0: Overflow Interrupt disable.
0
8-bit
~0.244-KHz 31.25-KHz
1: Overflow Interrupt enable.
[ 0..127 ]
> 7-bit
> 6-bit
> 5-bit
> 4-bit
~0.244-KHz
~0.488-KHz
~0.977-KHz
~1.953-KHz
62.5-KHz
125-KHz
250-KHz
500-KHz
Bit 0 = OVFOverflow Flag
[ 128..191 ]
[ 192..223 ]
[ 224..239 ]
This bit is set by hardware and cleared by software
reading the CSR register. It indicates the transition
of the counter from FFh to the ARR value
.
0: New transition not yet reached
1: Transition reached
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ST72321J, ST72324J/K
PWM AUTO-RELOAD TIMER (Cont’d)
PWM CONTROL REGISTER (PWMCR)
Read/Write
DUTY CYCLE REGISTERS (DCRx)
Read/Write
Reset Value: 0000 0000 (00h)
Reset Value: 0000 0000 (00h)
7
0
7
0
OE3
OE2
OE1
OE0
OP3
OP2
OP1
OP0
DC7
DC6
DC5
DC4
DC3
DC2
DC1
DC0
Bit 7:4 = OE[3:0] PWM Output Enable
Bit 7:0 = DC[7:0] Duty Cycle Data
These bits are set and cleared by software.
These bits are set and cleared by software. They
enable or disable the PWM output channels inde-
pendently acting on the corresponding I/O pin.
0: PWM output disabled.
A DCRx register is associated with the OCRx reg-
ister of each PWM channel to determine the sec-
ond edge location of the PWM signal (the first
edge location is common to all channels and given
by the ARR register). These DCR registers allow
the duty cycle to be set independently for each
PWM channel.
1: PWM output enabled.
Bit 3:0 = OP[3:0] PWM Output Polarity
These bits are set and cleared by software. They
independently select the polarity of the four PWM
output signals.
PWMx output level
OPx
Counter <= OCRx
Counter > OCRx
1
0
0
1
0
1
Note: When an OPx bit is modified, the PWMx out-
put signal polarity is immediately reversed.
61/176
ST72321J, ST72324J/K
PWM AUTO-RELOAD TIMER (Cont’d)
INPUT CAPTURE
CONTROL / STATUS REGISTER (ICCSR)
INPUT CAPTURE REGISTERS (ICRx)
Read only
Read/Write
Reset Value: 0000 0000 (00h)
Reset Value: 0000 0000 (00h)
7
0
7
0
IC7
IC6
IC5
IC4
IC3
IC2
IC1
IC0
0
0
CS2
CS1
CIE2
CIE1
CF2
CF1
Bit 7:0 = IC[7:0] Input Capture Data
Bit 7:6 = Reserved, always read as 0.
These read only bits are set and cleared by hard-
ware. An ICRx register contains the 8-bit auto-re-
load counter value transferred by the input capture
channel x event.
Bit 5:4 = CS[2:1] Capture Sensitivity
These bits are set and cleared by software. They
determine the trigger event polarity on the corre-
sponding input capture channel.
0: Falling edge triggers capture on channel x.
1: Rising edge triggers capture on channel x.
Bit 3:2 = CIE[2:1] Capture Interrupt Enable
These bits are set and cleared by software. They
enable or disable the Input capture channel inter-
rupts independently.
0: Input capture channel x interrupt disabled.
1: Input capture channel x interrupt enabled.
Bit 1:0 = CF[2:1] Capture Flag
These bits are set by hardware and cleared by
software reading the corresponding ICRx register.
Each CFx bit indicates that an input capture x has
occurred.
0: No input capture on channel x.
1: An input capture has occured on channel x.
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ST72321J, ST72324J/K
PWM AUTO-RELOAD TIMER (Cont’d)
Table 15. PWM Auto-Reload Timer Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
PWMDCR3
DC7
0
DC6
0
DC5
0
DC4
0
DC3
0
DC2
0
DC1
0
DC0
0
0073h
0074h
0075h
0076h
0077h
0078h
0079h
007Ah
007Bh
007Ch
007Dh
Reset Value
PWMDCR2
DC7
0
DC6
0
DC5
0
DC4
0
DC3
0
DC2
0
DC1
0
DC0
0
Reset Value
PWMDCR1
DC7
0
DC6
0
DC5
0
DC4
0
DC3
0
DC2
0
DC1
0
DC0
0
Reset Value
PWMDCR0
DC7
0
DC6
0
DC5
0
DC4
0
DC3
0
DC2
0
DC1
0
DC0
0
Reset Value
PWMCR
OE3
0
OE2
0
OE1
0
OE0
0
OP3
0
OP2
0
OP1
0
OP0
0
Reset Value
ARTCSR
EXCL
0
CC2
0
CC1
0
CC0
0
TCE
0
FCRL
0
RIE
0
OVF
0
Reset Value
ARTCAR
CA7
0
CA6
0
CA5
0
CA4
0
CA3
0
CA2
0
CA1
0
CA0
0
Reset Value
ARTARR
AR7
0
AR6
0
AR5
0
AR4
0
AR3
0
AR2
0
AR1
0
AR0
0
Reset Value
ARTICCSR
CE2
0
CE1
0
CS2
0
CS1
0
CF2
0
CF1
0
0
0
Reset Value
ARTICR1
IC7
0
IC6
0
IC5
0
IC4
0
IC3
0
IC2
0
IC1
0
IC0
0
Reset Value
ARTICR2
IC7
0
IC6
0
IC5
0
IC4
0
IC3
0
IC2
0
IC1
0
IC0
0
Reset Value
63/176
ST72321J, ST72324J/K
10.4 16-BIT TIMER
10.4.1 Introduction
When reading an input signal on a non-bonded
pin, the value will always be ‘1’.
The timer consists of a 16-bit free-running counter
driven by a programmable prescaler.
10.4.3 Functional Description
10.4.3.1 Counter
It may be used for a variety of purposes, including
pulse length measurement of up to two input sig-
nals (input capture) or generation of up to two out-
put waveforms (output compare and PWM).
The main block of the Programmable Timer is a
16-bit free running upcounter and its associated
16-bit registers. The 16-bit registers are made up
of two 8-bit registers called high & low.
Pulse lengths and waveform periods can be mod-
ulated from a few microseconds to several milli-
seconds using the timer prescaler and the CPU
clock prescaler.
Counter Register (CR):
– Counter High Register (CHR) is the most sig-
nificant byte (MS Byte).
Some ST7 devices have two on-chip 16-bit timers.
They are completely independent, and do not
share any resources. They are synchronized after
a MCU reset as long as the timer clock frequen-
cies are not modified.
– Counter Low Register (CLR) is the least sig-
nificant byte (LS Byte).
Alternate Counter Register (ACR)
– Alternate Counter High Register (ACHR) is the
most significant byte (MS Byte).
This description covers one or two 16-bit timers. In
ST7 devices with two timers, register names are
prefixed with TA (Timer A) or TB (Timer B).
– Alternate Counter Low Register (ACLR) is the
least significant byte (LS Byte).
10.4.2 Main Features
These two read-only 16-bit registers contain the
same value but with the difference that reading the
ACLR register does not clear the TOF bit (Timer
overflow flag), located in the Status register, (SR),
(see note at the end of paragraph titled 16-bit read
sequence).
■ Programmable prescaler:fCPU dividedby2, 4or8.
■ Overflow status flag and maskable interrupt
■ External clock input (must be at least 4 times
slower thantheCPUclock speed)withthechoice
of active edge
■ Output compare functions with
– 2 dedicated 16-bit registers
– 2 dedicated programmable signals
– 2 dedicated status flags
Writing in the CLR register or ACLR register resets
the free running counter to the FFFCh value.
Both counters have a reset value of FFFCh (this is
the only value which is reloaded in the 16-bit tim-
er). The reset value of both counters is also
FFFCh in One Pulse mode and PWM mode.
– 1 dedicated maskable interrupt
■ Input capture functions with
– 2 dedicated 16-bit registers
– 2 dedicated active edge selection signals
– 2 dedicated status flags
The timer clock depends on the clock control bits
of the CR2 register, as illustrated in Table 16 Clock
Control Bits. The value in the counter register re-
peats every 131.072, 262.144 or 524.288 CPU
clock cycles depending on the CC[1:0] bits.
– 1 dedicated maskable interrupt
■ Pulse width modulation mode (PWM)
■ One pulse mode
The timer frequency can be f
or an external frequency.
/2, f
/4, f
/8
CPU
CPU
CPU
■ Reduced Power Mode
■ 5 alternatefunctionson I/O ports (ICAP1,ICAP2,
OCMP1, OCMP2, EXTCLK)*
The Block Diagram is shown in Figure 40.
*Note: Some timer pins may not available (not
bonded) in some ST7 devices. Refer to the device
pin out description.
64/176
ST72321J, ST72324J/K
16-BIT TIMER (Cont’d)
Figure 40. Timer Block Diagram
ST7 INTERNAL BUS
f
CPU
MCU-PERIPHERAL INTERFACE
8 low
8-bit
8 high
8
8
8
8
8
8
8
8
buffer
EXEDG
h
w
h
w
h
w
h
low
16
INPUT
CAPTURE
REGISTER
INPUT
CAPTURE
REGISTER
OUTPUT
COMPARE
REGISTER
OUTPUT
COMPARE
REGISTER
1
1/2
1/4
1/8
COUNTER
REGISTER
1
2
2
ALTERNATE
COUNTER
REGISTER
EXTCLK
pin
16
16
16
CC[1:0]
TIMER INTERNAL BUS
16 16
OVERFLOW
DETECT
EDGE DETECT
CIRCUIT1
OUTPUT COMPARE
CIRCUIT
ICAP1
pin
CIRCUIT
6
EDGE DETECT
CIRCUIT2
ICAP2
pin
OCMP1
pin
LATCH1
LATCH2
0
ICF1 OCF1 TOF ICF2 OCF2
0
TIMD
(Control/Status Register)
OCMP2
pin
CSR
ICIE OCIE TOIE FOLV2 FOLV1OLVL2 IEDG1 OLVL1
OC1E
OPM PWM CC1 CC0 IEDG2 EXEDG
OC2E
(Control Register 1) CR1
(Control Register 2) CR2
(See note)
Note: If IC, OC and TO interrupt requests have separate vectors
then the last OR is not present (See device Interrupt Vector Table)
TIMER INTERRUPT
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ST72321J, ST72324J/K
16-BIT TIMER (Cont’d)
16-bit read sequence: (from either the Counter
If one of these conditions is false, the interrupt re-
mains pending to be issued as soon as they are
both true.
Register or the Alternate Counter Register).
Beginning of the sequence
Clearing the overflow interrupt request is done in
two steps:
Read
MS Byte
LS Byte
is buffered
At t0
1.Reading the SR register while the TOF bit is set.
2.An access (read or write) to the CLR register.
Other
Notes: The TOF bit is not cleared by accesses to
ACLR register. The advantage of accessing the
ACLR register rather than the CLR register is that
it allows simultaneous use of the overflow function
and reading the free running counter at random
times (for example, to measure elapsed time) with-
out the risk of clearing the TOF bit erroneously.
instructions
Returns the buffered
LS Byte value at t0
Read
LS Byte
At t0 +∆t
Sequence completed
The timer is not affected by WAIT mode.
The user must read the MS Byte first, then the LS
Byte value is buffered automatically.
In HALT mode, the counter stops counting until the
mode is exited. Counting then resumes from the
previous count (MCU awakened by an interrupt) or
from the reset count (MCU awakened by a Reset).
This buffered value remains unchanged until the
16-bit read sequence is completed, even if the
user reads the MS Byte several times.
After a complete reading sequence, if only the
CLR register or ACLR register are read, they re-
turn the LS Byte of the count value at the time of
the read.
10.4.3.2 External Clock
The external clock (wthe CR2 register.
The status of the EXEDG bit in the CR2 register
determines the type of level transition on the exter-
nal clock pin EXTCLK that will trigger the free run-
ning counter.
Whatever the timer mode used (input capture, out-
put compare, one pulse mode or PWM mode) an
overflow occurs when the counter rolls over from
FFFFh to 0000h then:
The counter is synchronized with the falling edge
of the internal CPU clock.
– The TOF bit of the SR register is set.
– A timer interrupt is generated if:
– TOIE bit of the CR1 register is set and
– I bit of the CC register is cleared.
A minimum of four falling edges of the CPU clock
must occur between two consecutive active edges
of the external clock; thus the external clock fre-
quency must be less than a quarter of the CPU
clock frequency.
66/176
ST72321J, ST72324J/K
16-BIT TIMER (Cont’d)
Figure 41. Counter Timing Diagram, internal clock divided by 2
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
FFFD FFFE FFFF 0000 0001 0002 0003
COUNTER REGISTER
TIMER OVERFLOW FLAG (TOF)
Figure 42. Counter Timing Diagram, internal clock divided by 4
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
FFFC
FFFD
0000
0001
COUNTER REGISTER
TIMER OVERFLOW FLAG (TOF)
Figure 43. Counter Timing Diagram, internal clock divided by 8
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
0000
FFFC
FFFD
COUNTER REGISTER
TIMER OVERFLOW FLAG (TOF)
Note: The MCU is in reset state when the internal reset signal is high, when it is low the MCU is running.
67/176
ST72321J, ST72324J/K
16-BIT TIMER (Cont’d)
10.4.3.3 Input Capture
When an input capture occurs:
– ICFi bit is set.
In this section, the index, i, may be 1 or 2 because
there are 2 input capture functions in the 16-bit
timer.
– The ICiR register contains the value of the free
running counter on the active transition on the
ICAPi pin (see Figure 45).
The two 16-bit input capture registers (IC1R and
IC2R) are used to latch the value of the free run-
ning counter after a transition is detected on the
ICAPi pin (see figure 5).
– A timer interrupt is generated if the ICIE bit is set
and the I bit is cleared in the CC register. Other-
wise, the interrupt remains pending until both
conditions become true.
MS Byte
ICiHR
LS Byte
ICiLR
ICiR
Clearing the Input Capture interrupt request (i.e.
clearing the ICFi bit) is done in two steps:
ICiR register is a read-only register.
1. Reading the SR register while the ICFi bit is set.
2. An access (read or write) to the ICiLR register.
The active transition is software programmable
through the IEDGi bit of Control Registers (CRi).
Timing resolution is one count of the free running
Notes:
counter: (f
/CC[1:0]).
CPU
1. After reading the ICiHR register, transfer of
input capture data is inhibited and ICFi will
never be set until the ICiLR register is also
read.
Procedure:
To use the input capture function select the follow-
ing in the CR2 register:
2. The ICiR register contains the free running
counter value which corresponds to the most
recent input capture.
– Select the timer clock (CC[1:0]) (see Table 16
Clock Control Bits).
3. The 2 input capture functions can be used
together even if the timer also uses the 2 output
compare functions.
– Select the edge of the active transition on the
ICAP2 pin with the IEDG2 bit (the ICAP2 pin
must be configured as floating input).
4. In One pulse Mode and PWM mode only Input
Capture 2 can be used.
And select the following in the CR1 register:
– Set the ICIE bit to generate an interrupt after an
input capture coming from either the ICAP1 pin
or the ICAP2 pin
5. The alternate inputs (ICAP1 & ICAP2) are
always directly connected to the timer. So any
transitions on these pins activates the input
capture function.
– Select the edge of the active transition on the
ICAP1 pin with theIEDG1 bit (the ICAP1pin must
be configured as floating input).
Moreover if one of the ICAPi pins is configured
as an input and the second one as an output,
an interrupt can be generated if the user tog-
gles the output pin and if the ICIE bit is set.
This can be avoided if the input capture func-
tion i is disabled by reading the ICiHR (see note
1).
6. The TOF bit can be used with interrupt genera-
tion in order to measure events that go beyond
the timer range (FFFFh).
68/176
ST72321J, ST72324J/K
16-BIT TIMER (Cont’d)
Figure 44. Input Capture Block Diagram
ICAP1
pin
(Control Register 1) CR1
IEDG1
EDGE DETECT
CIRCUIT2
EDGE DETECT
CIRCUIT1
ICIE
ICAP2
pin
(Status Register) SR
ICF1
ICF2
0
0
0
IC2R Register
IC1R Register
(Control Register 2) CR2
16-BIT
16-BIT FREE RUNNING
COUNTER
IEDG2
CC0
CC1
Figure 45. Input Capture Timing Diagram
TIMER CLOCK
FF01
FF02
FF03
COUNTER REGISTER
ICAPi PIN
ICAPi FLAG
FF03
ICAPi REGISTER
Note: The rising edge is the active edge.
69/176
ST72321J, ST72324J/K
16-BIT TIMER (Cont’d)
10.4.3.4 Output Compare
– The OCMPi pin takes OLVLi bit value (OCMPi
pin latch is forced low during reset).
In this section, the index, i, may be 1 or 2 because
there are 2 output compare functions in the 16-bit
timer.
– A timer interrupt is generated if the OCIE bit is
set in the CR2 register and the I bit is cleared in
the CC register (CC).
This function can be used to control an output
waveform or indicate when a period of time has
elapsed.
The OCiR register value required for aspecific tim-
ing application can be calculated using the follow-
ing formula:
When a match is found between the Output Com-
pare register and the free running counter, the out-
put compare function:
– Assigns pins with a programmable value if the
OCIE bit is set
∆t f
* CPU
PRESC
∆ OCiR =
– Sets a flag in the status register
– Generates an interrupt if enabled
Where:
∆t
= Output compare period (in seconds)
= CPU clock frequency (in hertz)
Two 16-bit registers Output Compare Register 1
(OC1R) and Output Compare Register 2 (OC2R)
contain the value to be compared to the counter
register each timer clock cycle.
f
CPU
= Timer prescaler factor (2, 4 or 8 de-
pending on CC[1:0] bits, see Table 16
Clock Control Bits)
PRESC
MS Byte
OCiHR
LS Byte
OCiLR
OCiR
If the timer clock is an external clock, the formula
is:
These registers are readable and writable and are
not affected by the timer hardware. A reset event
changes the OCiR value to 8000h.
∆ OCiR = ∆t f
* EXT
Timing resolution is one count of the free running
Where:
counter: (f
).
CC[1:0]
CPU/
∆t
= Output compare period (in seconds)
= External timer clock frequency (in hertz)
f
EXT
Procedure:
To use the output compare function, select the fol-
lowing in the CR2 register:
Clearing the output compare interrupt request (i.e.
clearing the OCFi bit) is done by:
– Set the OCiE bit if an output is needed then the
OCMPi pin is dedicated to the output compare i
signal.
1. Reading the SR register while the OCFi bit is
set.
2. An access (read or write) to the OCiLR register.
– Select the timer clock (CC[1:0]) (see Table 16
Clock Control Bits).
The following procedure is recommended to pre-
vent the OCFi bit from being set between the time
it is read and the write to the OCiR register:
And select the following in the CR1 register:
– Select theOLVLi bit to applied to theOCMPi pins
after the match occurs.
– Write to the OCiHR register (further compares
are inhibited).
– Set the OCIE bit to generate an interrupt if it is
needed.
– Read the SR register (first step of the clearance
of the OCFi bit, which may be already set).
When a match is found between OCRi register
and CR register:
– Write to the OCiLR register (enables the output
compare function and clears the OCFi bit).
– OCFi bit is set.
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ST72321J, ST72324J/K
16-BIT TIMER (Cont’d)
Notes:
1. After a processor write cycle to the OCiHR reg-
ister, the output compare function is inhibited
until the OCiLR register is also written.
Forced Compare Output capability
When the FOLVi bit is set by software, the OLVLi
bit is copied to the OCMPi pin. The OLVi bit has to
be toggled in order to toggle the OCMPi pin when
it is enabled (OCiE bit=1). The OCFi bit is then not
set by hardware, and thus no interrupt request is
generated.
2. If the OCiE bit is not set, the OCMPi pin is a
general I/O port and the OLVLi bit will not
appear when a match is found but an interrupt
could be generated if the OCIE bit is set.
3. When the timer clock is f
/2, OCFi and
The FOLVLi bits have no effect in both one pulse
mode and PWM mode.
CPU
OCMPi are set while the counter value equals
the OCiR register value (see Figure 47 on page
72). This behaviour is the same in OPM or
PWM mode.
When the timer clock is f
/4, f
/8 or in
CPU
CPU
external clock mode, OCFi and OCMPi are set
while the counter value equals the OCiR regis-
ter value plus 1 (see Figure 48 on page 72).
4. The output compare functions can be used both
for generating external events on the OCMPi
pins even if the input capture mode is also
used.
5. The value in the 16-bit OCiR register and the
OLVi bit should be changed after each suc-
cessful comparison in order to control an output
waveform or establish a new elapsed timeout.
Figure 46. Output Compare Block Diagram
16 BIT FREE RUNNING
OC1E
CC1 CC0
OC2E
COUNTER
(Control Register 2) CR2
16-bit
(Control Register 1) CR1
OUTPUT COMPARE
CIRCUIT
Latch
1
OCIE
FOLV2 FOLV1 OLVL2
OLVL1
OCMP1
Pin
16-bit
16-bit
Latch
2
OCMP2
Pin
OC1R Register
OCF1
OCF2
0
0
0
OC2R Register
(Status Register) SR
71/176
ST72321J, ST72324J/K
16-BIT TIMER (Cont’d)
Figure 47. Output Compare Timing Diagram, f
=f
/2
TIMER
CPU
INTERNAL CPU CLOCK
TIMER CLOCK
COUNTER REGISTER
2ECF 2ED0 2ED1 2ED2 2ED3 2ED4
2ED3
OUTPUT COMPARE REGISTER i (OCRi)
OUTPUT COMPARE FLAG i (OCFi)
OCMPi PIN (OLVLi=1)
Figure 48. Output Compare Timing Diagram, f
=f
/4
TIMER
CPU
INTERNAL CPU CLOCK
TIMER CLOCK
2ECF 2ED0 2ED1 2ED2
2ED3
2ED4
2ED3
COUNTER REGISTER
OUTPUT COMPARE REGISTER i (OCRi)
COMPARE REGISTER i LATCH
OUTPUT COMPARE FLAG i (OCFi)
OCMPi PIN (OLVLi=1)
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ST72321J, ST72324J/K
16-BIT TIMER (Cont’d)
10.4.3.5 One Pulse Mode
Clearing the Input Capture interrupt request (i.e.
clearing the ICFi bit) is done in two steps:
One Pulse mode enables the generation of a
pulse when an external event occurs. This mode is
selected via the OPM bit in the CR2 register.
1. Reading the SR register while the ICFi bit is set.
2. An access (read or write) to the ICiLR register.
The one pulse mode uses the Input Capture1
function and the Output Compare1 function.
The OC1R register value required for a specific
timing application can be calculated using the fol-
lowing formula:
Procedure:
t * f
To use one pulse mode:
CPU - 5
OCiR Value =
PRESC
1. Load the OC1R register with the value corre-
sponding to the length of the pulse (see the for-
mula in the opposite column).
Where:
t
= Pulse period (in seconds)
2. Select the following in the CR1 register:
f
= CPU clock frequency (in hertz)
CPU
– Using the OLVL1 bit, select the level to be ap-
plied to the OCMP1 pin after the pulse.
= Timer prescaler factor (2, 4 or 8 depend-
ing on the CC[1:0] bits, see Table 16
Clock Control Bits)
PRESC
– Using the OLVL2 bit, select the level to be ap-
plied to the OCMP1 pin during the pulse.
If the timer clock is an external clock the formula is:
– Select the edge of the active transition on the
ICAP1 pin with the IEDG1 bit (the ICAP1 pin
must be configured as floating input).
OCiR = t f
-5
* EXT
Where:
t
3. Select the following in the CR2 register:
= Pulse period (in seconds)
– Set the OC1E bit, the OCMP1 pin is then ded-
icated to the Output Compare 1 function.
f
= External timer clock frequency (in hertz)
EXT
– Set the OPM bit.
When the value of the counter is equal to the value
of the contents of the OC1R register, the OLVL1
bit is output on the OCMP1 pin, (See Figure 49).
– Select the timer clock CC[1:0] (see Table 16
Clock Control Bits).
One pulse mode cycle
Notes:
ICR1 = Counter
When
1. The OCF1 bit cannot be set by hardware in one
pulse mode but the OCF2 bit can generate an
Output Compare interrupt.
OCMP1 = OLVL2
event occurs
on ICAP1
Counter is reset
2. When the Pulse Width Modulation (PWM) and
One Pulse Mode (OPM) bits are both set, the
PWM mode is the only active one.
to FFFCh
ICF1 bit is set
3. If OLVL1=OLVL2 a continuous signal will be
seen on the OCMP1 pin.
When
Counter
OCMP1 = OLVL1
= OC1R
4. The ICAP1 pin can not be used to perform input
capture. The ICAP2 pin can be used to perform
input capture (ICF2 can be set and IC2R can be
loaded) but the user must take care that the
counter is reset each time a valid edge occurs
on the ICAP1 pin and ICF1 can also generates
interrupt if ICIE is set.
Then, on a valid event on the ICAP1 pin, the coun-
ter is initialized to FFFCh and OLVL2 bit is loaded
on the OCMP1 pin, the ICF1 bit is set and the val-
ue FFFDh is loaded in the IC1R register.
Because the ICF1 bit is set when an active edge
occurs, an interrupt can be generated if the ICIE
bit is set.
5. When one pulse mode is used OC1R is dedi-
cated to this mode. Nevertheless OC2R and
OCF2 can be used to indicate a period of time
has been elapsed but cannot generate an out-
put waveform because the level OLVL2 is dedi-
cated to the one pulse mode.
73/176
ST72321J, ST72324J/K
16-BIT TIMER (Cont’d)
Figure 49. One Pulse Mode Timing Example
2ED3
01F8
IC1R
FFFC FFFD FFFE
2ED0 2ED1 2ED2
2ED3
FFFC FFFD
01F8
COUNTER
ICAP1
OLVL2
OLVL1
OLVL2
OCMP1
compare1
Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1
Figure 50. Pulse Width Modulation Mode Timing Example
2ED0 2ED1 2ED2
34E2 FFFC
FFFC FFFD FFFE
34E2
COUNTER
OCMP1
OLVL2
OLVL1
OLVL2
compare2
compare1
compare2
Note: OC1R=2ED0h, OC2R=34E2, OLVL1=0, OLVL2= 1
74/176
ST72321J, ST72324J/K
16-BIT TIMER (Cont’d)
10.4.3.6 Pulse Width Modulation Mode
If OLVL1=1 and OLVL2=0 the length of the posi-
tive pulse is the difference between the OC2R and
OC1R registers.
Pulse Width Modulation (PWM) mode enables the
generation of a signal with a frequency and pulse
length determined by the value of the OC1R and
OC2R registers.
If OLVL1=OLVL2 a continuous signal will be seen
on the OCMP1 pin.
Pulse Width Modulation mode uses the complete
Output Compare 1 function plus the OC2R regis-
ter, and so this functionality can not be used when
PWM mode is activated.
The OCiR register value required for aspecific tim-
ing application can be calculated using the follow-
ing formula:
t * f
CPU
PRESC
- 5
OCiR Value =
In PWM mode, double buffering is implemented on
the output compare registers. Any new values writ-
ten in the OC1R and OC2R registers are taken
into account only at the end of the PWM period
(OC2) to avoid spikes on the PWM output pin
(OCMP1).
Where:
t
= Signal or pulse period (in seconds)
= CPU clock frequency (in hertz)
f
CPU
= Timer prescaler factor (2, 4 or 8 depend-
ing on CC[1:0] bits, see Table 16 Clock
Control Bits)
PRESC
Procedure
To use pulse width modulation mode:
If the timer clock is an external clock the formula is:
1. Load the OC2R register with the value corre-
sponding to the period of the signal using the
formula in the opposite column.
OCiR = t f
-5
* EXT
2. Load the OC1R register with the value corre-
sponding to the period of the pulse if (OLVL1=0
and OLVL2=1) using the formula in the oppo-
site column.
Where:
t
= Signal or pulse period (in seconds)
f
= External timer clock frequency (in hertz)
EXT
3. Select the following in the CR1 register:
The Output Compare 2 event causes the counter
to be initialized to FFFCh (See Figure 50)
– Using the OLVL1 bit, select the level to be ap-
plied to the OCMP1 pin after a successful
comparison with the OC1R register.
Notes:
– Using the OLVL2 bit, select the level to be ap-
plied to the OCMP1 pin after a successful
comparison with the OC2R register.
1. After a write instruction to the OCiHR register,
the output compare function is inhibited until the
OCiLR register is also written.
4. Select the following in the CR2 register:
2. The OCF1 and OCF2 bits cannot be set by
hardware in PWM mode therefore the Output
Compare interrupt is inhibited.
– Set OC1E bit: the OCMP1 pin is then dedicat-
ed to the output compare 1 function.
3. The ICF1 bit is set by hardware when the coun-
ter reaches the OC2R value and can produce a
timer interrupt if the ICIE bit is set and the I bit is
cleared.
– Set the PWM bit.
– Select the timer clock (CC[1:0]) (see Table 16
Clock Control Bits).
Pulse Width Modulation cycle
4. In PWM mode the ICAP1 pin can not be used
to perform input capture because it is discon-
nected to the timer. The ICAP2 pin can be used
to perform input capture (ICF2 can be set and
IC2R can be loaded) but the user must take
care that the counter is reset each period and
ICF1 can also generates interrupt if ICIE is set.
When
Counter
= OC1R
OCMP1 = OLVL1
OCMP1 = OLVL2
5. When the Pulse Width Modulation (PWM) and
One Pulse Mode (OPM) bits are both set, the
PWM mode is the only active one.
When
Counter
= OC2R
Counter is reset
to FFFCh
ICF1 bit is set
75/176
ST72321J, ST72324J/K
16-BIT TIMER (Cont’d)
10.4.4 Low Power Modes
Mode
Description
No effect on 16-bit Timer.
Timer interrupts cause the device to exit from WAIT mode.
WAIT
HALT
16-bit Timer registers are frozen.
In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous
count when the MCU is woken up by an interrupt with “exit from HALT mode” capability or from the counter
reset value when the MCU is woken up by a RESET.
If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is armed. Consequent-
ly, when the MCU is woken up by an interrupt with “exit from HALT mode” capability, the ICFi bit is set, and
the counter value present when exiting from HALT mode is captured into the ICiR register.
10.4.5 Interrupts
Enable
Control from
Bit
Exit
Exit
from
Halt
Event
Flag
Interrupt Event
Wait
Yes
Yes
Yes
Yes
Yes
Input Capture 1 event/Counter reset in PWM mode
Input Capture 2 event
ICF1
ICF2
No
No
No
No
No
ICIE
Output Compare 1 event (not available in PWM mode)
Output Compare 2 event (not available in PWM mode)
Timer Overflow event
OCF1
OCF2
TOF
OCIE
TOIE
Note: The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts chap-
ter). These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt
mask in the CC register is reset (RIM instruction).
10.4.6 Summary of Timer modes
AVAILABLE RESOURCES
MODES
Input Capture 1
Input Capture 2
Yes
Output Compare 1 Output Compare 2
Input Capture (1 and/or 2)
Output Compare (1 and/or 2)
One Pulse Mode
Yes
Yes
No
Yes
Yes
No
Yes
Yes
Yes
1)
3)
2)
Not Recommended
Not Recommended
Partially
No
PWM Mode
No
No
1) See note 4 in Section 10.4.3.5 One Pulse Mode
1) See note 5 in Section 10.4.3.5 One Pulse Mode
1) See note 4 in Section 10.4.3.6 Pulse Width Modulation Mode
76/176
ST72321J, ST72324J/K
16-BIT TIMER (Cont’d)
10.4.7 Register Description
Bit 4 = FOLV2 Forced Output Compare 2.
This bit is set and cleared by software.
0: No effect on the OCMP2 pin.
1:Forces the OLVL2 bit to be copied to the
OCMP2 pin, if the OC2E bit is set and even if
there is no successful comparison.
Each Timer is associated with three control and
status registers, and with six pairs of data registers
(16-bit values) relating to the two input captures,
the two output compares, the counter and the al-
ternate counter.
Bit 3 = FOLV1 Forced Output Compare 1.
This bit is set and cleared by software.
0: No effect on the OCMP1 pin.
CONTROL REGISTER 1 (CR1)
Read/Write
1: Forces OLVL1 to becopied to theOCMP1 pin, if
the OC1E bit is set and even if there is no suc-
cessful comparison.
Reset Value: 0000 0000 (00h)
7
0
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
Bit 2 = OLVL2 Output Level 2.
This bit is copied to the OCMP2 pin whenever a
successful comparison occurs with the OC2R reg-
ister and OCxE is set in the CR2 register. This val-
ue is copied to the OCMP1 pin in One Pulse Mode
and Pulse Width Modulation mode.
Bit 7 = ICIE Input Capture Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the
ICF1 or ICF2 bit of the SR register is set.
Bit 6 = OCIE Output Compare Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the
OCF1 or OCF2 bit of the SR register is set.
Bit 1 = IEDG1 Input Edge 1.
This bit determines which type of level transition
on the ICAP1 pin will trigger the capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
Bit 5 = TOIE Timer Overflow Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is enabled whenever the TOF
bit of the SR register is set.
Bit 0 = OLVL1 Output Level 1.
The OLVL1 bit is copied to the OCMP1 pin when-
ever a successful comparison occurs with the
OC1R register and the OC1E bit is set in the CR2
register.
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ST72321J, ST72324J/K
16-BIT TIMER (Cont’d)
CONTROL REGISTER 2 (CR2)
Read/Write
Bit 4 = PWM Pulse Width Modulation.
0: PWM mode is not active.
1: PWM mode is active, the OCMP1 pin outputs a
programmable cyclic signal; the length of the
pulse depends on the value of OC1R register;
the period depends on the value of OC2R regis-
ter.
Reset Value: 0000 0000 (00h)
7
0
OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG
Bit 3, 2 = CC[1:0] Clock Control.
Bit 7 = OC1E Output Compare 1 Pin Enable.
This bit is used only to output the signal from the
timer on the OCMP1 pin (OLV1 in Output Com-
pare mode, both OLV1 and OLV2 in PWM and
one-pulse mode). Whatever the value of the OC1E
bit, the Output Compare 1 function of the timer re-
mains active.
0: OCMP1 pin alternate function disabled (I/O pin
free for general-purpose I/O).
1: OCMP1 pin alternate function enabled.
The timer clock mode depends on these bits:
Table 16. Clock Control Bits
Timer Clock
fCPU / 4
CC1
CC0
0
0
1
0
1
0
fCPU / 2
fCPU / 8
External Clock (where
available)
1
1
Bit 6 = OC2E Output Compare 2 Pin Enable.
This bit is used only to output the signal from the
timer on the OCMP2 pin (OLV2 in Output Com-
pare mode). Whatever the value of the OC2E bit,
the Output Compare 2 function of the timer re-
mains active.
0: OCMP2 pin alternate function disabled (I/O pin
free for general-purpose I/O).
1: OCMP2 pin alternate function enabled.
Note: If the external clock pin is not available, pro-
gramming the external clock configuration stops
the counter.
Bit 1 = IEDG2 Input Edge 2.
This bit determines which type of level transition
on the ICAP2 pin will trigger the capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
Bit 5 = OPM One Pulse Mode.
0: One Pulse Mode is not active.
Bit 0 = EXEDG External Clock Edge.
This bit determines which type of level transition
on the external clock pin EXTCLK will trigger the
counter register.
0: A falling edge triggers the counter register.
1: A rising edge triggers the counter register.
1: One Pulse Mode is active, the ICAP1 pin can be
used to trigger one pulse on the OCMP1 pin; the
active transition is given by the IEDG1 bit. The
length of the generated pulse depends on the
contents of the OC1R register.
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ST72321J, ST72324J/K
16-BIT TIMER (Cont’d)
CONTROL/STATUS REGISTER (CSR)
Note: Reading or writing the ACLR register does
not clear TOF.
Read Only
Reset Value: 0000 0000 (00h)
7
Bit 4 = ICF2 Input Capture Flag 2.
0: No input capture (reset value).
1: An input capture has occurred on the ICAP2
pin. To clear this bit, first read the SR register,
then read or write the low byte of the IC2R
(IC2LR) register.
0
0
ICF1 OCF1 TOF ICF2 OCF2 TIMD
0
Bit 7 = ICF1 Input Capture Flag 1.
0: No input capture (reset value).
1: An input capture has occurred on the ICAP1 pin
or the counter has reached the OC2R value in
PWM mode. To clear this bit, first read the SR
register, then read or write the low byte of the
IC1R (IC1LR) register.
Bit 3 = OCF2 Output Compare Flag 2.
0: No match (reset value).
1: The content of the free running counter has
matched the content of the OC2R register. To
clear this bit, first read the SR register, then read
or write the low byte of the OC2R (OC2LR) reg-
ister.
Bit 6 = OCF1 Output Compare Flag 1.
0: No match (reset value).
1: The content of the free running counter has
matched the content of the OC1R register. To
clear this bit, first read the SR register, then read
or write the low byte of the OC1R (OC1LR) reg-
ister.
Bit 2 = TIMD Timer disable.
This bit is set and cleared by software. When set, it
freezes the timer prescaler and counter and disa-
bled the output functions (OCMP1 and OCMP2
pins) to reduce power consumption. Access to the
timer registers is still available, allowing the timer
configuration to be changed while it is disabled.
0: Timer enabled
Bit 5 = TOF Timer Overflow Flag.
0: No timer overflow (reset value).
1: The free running counter rolled over from FFFFh
to 0000h. To clear this bit, first read the SR reg-
ister, then read or write the low byte of the CR
(CLR) register.
1: Timer prescaler, counter and outputs disabled
Bits 1:0 = Reserved, must be kept cleared.
79/176
ST72321J, ST72324J/K
16-BIT TIMER (Cont’d)
INPUT CAPTURE 1 HIGH REGISTER (IC1HR)
OUTPUT COMPARE
(OC1HR)
1
HIGH REGISTER
Read Only
Reset Value: Undefined
Read/Write
Reset Value: 1000 0000 (80h)
This is an 8-bit read only register that contains the
high part of the counter value (transferred by the
input capture 1 event).
This is an 8-bit register that contains the high part
of the value to be compared to the CHR register.
7
0
7
0
MSB
LSB
MSB
LSB
INPUT CAPTURE 1 LOW REGISTER (IC1LR)
OUTPUT COMPARE
(OC1LR)
1
LOW REGISTER
Read Only
Reset Value: Undefined
Read/Write
Reset Value: 0000 0000 (00h)
This is an 8-bit read only register that contains the
low part of the counter value (transferred by the in-
put capture 1 event).
This is an 8-bit register that contains the low part of
the value to be compared to the CLR register.
7
0
7
0
MSB
LSB
MSB
LSB
80/176
ST72321J, ST72324J/K
16-BIT TIMER (Cont’d)
OUTPUT COMPARE
(OC2HR)
2
HIGH REGISTER
ALTERNATE COUNTER HIGH REGISTER
(ACHR)
Read/Write
Reset Value: 1000 0000 (80h)
Read Only
Reset Value: 1111 1111 (FFh)
This is an 8-bit register that contains the high part
of the value to be compared to the CHR register.
This is an 8-bit register that contains the high part
of the counter value.
7
0
7
0
MSB
LSB
MSB
LSB
OUTPUT COMPARE
(OC2LR)
2
LOW REGISTER
ALTERNATE COUNTER LOW REGISTER
(ACLR)
Read/Write
Reset Value: 0000 0000 (00h)
Read Only
Reset Value: 1111 1100 (FCh)
This is an 8-bit register that contains the low part of
the value to be compared to the CLR register.
This is an 8-bit register that contains the low part of
the counter value. A write to this register resets the
counter. An access to this register after an access
to CSR register does not clear the TOF bit in the
CSR register.
7
0
MSB
LSB
7
0
COUNTER HIGH REGISTER (CHR)
MSB
LSB
Read Only
Reset Value: 1111 1111 (FFh)
INPUT CAPTURE 2 HIGH REGISTER (IC2HR)
This is an 8-bit register that contains the high part
of the counter value.
Read Only
Reset Value: Undefined
7
0
This is an 8-bit read only register that contains the
high part of the counter value (transferred by the
Input Capture 2 event).
MSB
LSB
7
0
MSB
LSB
COUNTER LOW REGISTER (CLR)
Read Only
Reset Value: 1111 1100 (FCh)
This is an 8-bit register that contains the low part of
the countervalue. A write to this register resets the
counter. An access to this register after accessing
the CSR register clears the TOF bit.
INPUT CAPTURE 2 LOW REGISTER (IC2LR)
Read Only
Reset Value: Undefined
This is an 8-bit read only register that contains the
low part of the counter value (transferred by the In-
put Capture 2 event).
7
0
MSB
LSB
7
0
MSB
LSB
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ST72321J, ST72324J/K
16-BIT TIMER (Cont’d)
Table 17. 16-Bit Timer Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
Timer A: 32 CR1
Timer B: 42 Reset Value
ICIE
0
OCIE
0
TOIE
0
FOLV2
0
FOLV1
0
OLVL2
0
IEDG1
0
OLVL1
0
Timer A: 31 CR2
Timer B: 41 Reset Value
OC1E
0
OC2E
0
OPM
0
PWM
0
CC1
0
CC0
0
IEDG2
0
EXEDG
0
OCF1
0
Timer A: 33 CSR
Timer B: 43 Reset Value
ICF1
0
TOF
0
ICF2
0
OCF2
0
TIMD
0
-
0
-
0
Timer A: 34 ICHR1
Timer B: 44 Reset Value
MSB
-
LSB
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Timer A: 35 ICLR1
Timer B: 45 Reset Value
MSB
-
LSB
-
Timer A: 36 OCHR1
Timer B: 46 Reset Value
MSB
-
LSB
-
Timer A: 37 OCLR1
Timer B: 47 Reset Value
MSB
-
LSB
-
Timer A: 3E OCHR2
Timer B: 4E Reset Value
MSB
-
LSB
-
Timer A: 3F OCLR2
Timer B: 4F Reset Value
MSB
-
LSB
-
Timer A: 38 CHR
Timer B: 48 Reset Value
MSB
1
LSB
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
Timer A: 39 CLR
Timer B: 49 Reset Value
MSB
1
LSB
0
Timer A: 3A ACHR
Timer B: 4A Reset Value
MSB
1
LSB
1
Timer A: 3B ACLR
Timer B: 4B Reset Value
MSB
1
LSB
0
1
-
1
-
1
-
1
-
1
-
0
-
Timer A: 3C ICHR2
Timer B: 4C Reset Value
MSB
-
LSB
-
Timer A: 3D ICLR2
Timer B: 4D Reset Value
MSB
-
LSB
-
-
-
-
-
-
-
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10.5 SERIAL PERIPHERAL INTERFACE (SPI)
10.5.1 Introduction
10.5.3 General Description
The Serial Peripheral Interface (SPI) allows full-
duplex, synchronous, serial communication with
external devices. An SPI system may consist of a
master and one or more slaves or a system in
which devices may be either masters or slaves.
The SPI is connected to external devices through
4(3) alternate pins:
– MISO: Master In / Slave Out pin
– MOSI: Master Out / Slave In pin
– SCK: Serial Clock pin
The SPI is normally used for communication be-
tween the microcontroller and external peripherals
or another microcontroller.
– SS: Slave select pin (if not done through soft-
ware)
Refer to the Pin Description chapter for the device-
specific pin-out.
A basic example of interconnections between a
single master and a single slave is illustrated on
Figure 51.
10.5.2 Main Features
The MOSI pins are connected together as are
MISO pins. In this way data is transferred serially
between master and slave (most significant bit
first).
■ Full duplex, three-wire synchronous transfers
■ Simplex, two wire synchronous transfers
■ Master or slave operation selectable either
through software or hardware
When the master device transmits data to a slave
device via MOSI pin, the slave device responds by
sending data to the master device via the MISO
pin. This implies full duplex transmission with both
data out and data in synchronized with the same
clock signal (which is provided by the master de-
vice via the SCK pin).
■ Six master mode frequencies
■ Maximum slave mode frequency = f
/2.
CPU
■ Programmable clock polarity and phase
■ End of transfer interrupt flag
■ Write collision flag protection
■ Master mode fault protection capability.
■ Overrun error detection flag.
Thus, the byte transmitted is replaced by the byte
received and eliminates the need for separate
transmit-empty and receiver-full bits. A status flag
is used to indicate that the I/O operation is com-
plete.
Four possible data/clock timing relationships may
be chosen (see Figure 54) but master and slave
must be programmed with the same timing mode.
Figure 51. Serial Peripheral Interface Master/Slave
MASTER
SLAVE
MSBit
LSBit
MSBit
LSBit
MISO
MOSI
MISO
MOSI
8-BIT SHIFT REGISTER
8-BIT SHIFT REGISTER
SPI
CLOCK
GENERATOR
SCK
SS
SCK
SS
+5V
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SERIAL PERIPHERAL INTERFACE (Cont’d)
Figure 52. Serial Peripheral Interface Block Diagram
Internal Bus
Read
DR
IT
Read Buffer
request
MOSI
SPICSR
MISO
8-Bit Shift Register
Write
SPIF WCOL OVR MODF
0
SOD SSM SSI
SPI
STATE
CONTROL
SCK
SS
SPICR
MSTR
SPR0
CPHA SPR1
CPOL
SPIE SPE SPR2
MASTER
CONTROL
SERIAL
CLOCK
GENERATOR
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SERIAL PERIPHERAL INTERFACE (Cont’d)
10.5.4 Functional Description
4. The MSTR and SPE bits must be set (they
remain set only if the SS pin is connected to
a high level signal).
Figure 51 shows the serial peripheral interface
(SPI) block diagram.
This interface contains 3 dedicated registers:
– A Control Register (SPICR)
In this configuration the MOSI pin is a data output
and to the MISO pin is a data input.
– A Control Status Register (SPICSR)
– A Data Register (SPIDR)
Transmit Sequence
Refer to the SPICR, SPICSR and SPIDR registers
in Section 10.5.5for the bit definitions.
The transmit sequence begins when a byte is writ-
ten in the DR register.
The data byte is parallel loaded into the 8-bit shift
register (from the internal bus) during a write cycle
and then shifted out serially to the MOSI pin most
significant bit first.
10.5.4.1 SS Signal in Hardware/Software Mode
The SS signal can obtained in two modes:
– Hardware mode (through the SS pin)
– Software mode (through the SSI bit in the SPIC-
SR register)
When data transfer is complete:
– The SPIF bit is set by hardware
The mode (hardware or software) is selected by
the SlaveSelection Mode (SSM) bit inthe SPICSR
register.
– An interrupt is generated if the SPIE bit is set
and the I bit in the CCR register is cleared.
Note: In this document, wherever SS signal selec-
tion is done using the SS pin (hardware mode),
this can also be done in software mode, using the
SSM and SSI bits.
During the last clock cycle the SPIF bit is set, a
copy of the data byte received in the shift register
is moved to a buffer. When the SPIDR register is
read, the SPI peripheral returns this buffered val-
ue.
Clearing the SPIF bit is performed by the following
software sequence:
10.5.4.2 Master Configuration
In a master configuration, the serial clock is gener-
ated on the SCK pin.
1. An access to the SPICSR register while the
SPIF bit is set
Procedure
2. A read to the SPIDR register.
1. Select the SPR[2:0] bits to define the serial
clock baud rate (see SPICR register).
Note: While the SPIF bit is set, all writes to the
SPIDR register are inhibited until the SPICSR reg-
ister is read.
2. Select the CPOL and CPHA bits to define
one of the four relationships between the
data transfer and the serial clock (see Figure
54).
3. Connect the SS pin to a high level signal dur-
ing the complete byte transmit sequence or,
in software mode, set the SSI bit in the
SPICSR register.
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SERIAL PERIPHERAL INTERFACE (Cont’d)
10.5.4.3 Slave Configuration
Clearing the SPIF bit is performed by the following
software sequence:
In slave configuration, the serial clock is received
on the SCK pin from the master device.
1. An access to the SPICSR register while the
SPIF bit is set.
The value of the SPR[2:0] bits is not used for the
data transfer.
2. A write or a read of the DR register.
Procedure
Notes: While the SPIF bit is set, all writes to the
SPIDR register are inhibited until the SPICSR reg-
ister is read.
1. For correct data transfer, the slave device
must be in the same timing mode as the
master device (CPOL and CPHA bits). See
Figure 54.
The SPIF bit can be cleared during a second
transmission; however, it must be cleared before
the second SPIF bit in order to prevent an overrun
condition (see Section 10.5.4.8).
2. The SS pin must be connected to a low level
signal during the complete byte transmit
sequence or, in software mode, clear the SSI
bit in the SPICSR register.
Depending on the CPHA bit, the SS pin has to be
set to write to the SPIDR register between each
data byte transfer to avoid a write collision (see
Section 10.5.4.6).
3. Clear the MSTR bit and set the SPE bit to
assign the pins to alternate function.
Slave in Halt mode
In this configuration the MOSI pin is a data input
and the MISO pin is a data output.
In slave configuration, the SPI is able to exit the
ST7 device from HALT mode through a SPIF inter-
rupt. The data received is subsequently read from
the SPIDR register when the software is running
(interrupt vector fetch). If multiple data transfers
have been performed before software clears the
SPIF bit, then the OVR bit is set by hardware.
Transmit Sequence
The data byte is parallel loaded into the 8-bit shift
register (from the internal bus) during a write cycle
and then shifted out serially to the MISO pin most
significant bit first.
Note: When waking up from Halt mode, if the SPI
remains in Slave mode, it is recommended to per-
form an extra communications cycle to bring the
SPI from Halt mode state to normal state. If the
SPI exits from Slave mode, it returns to normal
state immediately.
The transmit sequence begins when the slave de-
vice receives the clock signal and the most signifi-
cant bit of the data on its MOSI pin.
When data transfer is complete:
– The SPIF bit is set by hardware
Caution: The SPI can wake up the ST7 from Halt
mode only if the Slave Select signal (external SS
pin or the SSI bit in the SPICSR register) is low
when the ST7 enters Halt mode. So if Slave selec-
tion is configured as external (see Section
10.5.4.1), make sure the master drives a low level
on the SS pin when the slave enters Halt mode.
– An interrupt is generated if SPIE bit is set and
I bit in CCR register is cleared.
During the last clock cycle the SPIF bit is set, a
copy of the data byte received in the shift register
is moved to a buffer. When the SPIDR register is
read, the SPI peripheral returns this buffered val-
ue.
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SERIAL PERIPHERAL INTERFACE (Cont’d)
10.5.4.4 Data Transfer Format
The master device applies data to its MOSI pin-
clock edge before the capture clock edge.
During an SPI transfer, data is simultaneously
transmitted (shifted out serially) and received
(shifted in serially). The serial clock is used to syn-
chronize the data transfer during a sequence of
eight clock pulses.
CPHA bit is set
The second edge on the SCK pin (falling edge if
the CPOL bit is reset, rising edge if the CPOL bit is
set) is the MSBit capture strobe. Data is latched on
the occurrence of the first clock transition.
The SS pin allows individual selection of a slave
device; the other slave devices that are not select-
ed do not interfere with the SPI transfer.
No write collision should occur even if the SS pin
stays low during a transfer of several bytes (see
Figure 53).
Clock Phase and Clock Polarity
Four possible timing relationships may be chosen
by software, using the CPOL and CPHA bits.
CPHA bit is reset
The CPOL (clock polarity) bit controls the steady
state value of the clock when no data is being
transferred. This bit affects both master and slave
modes.
The firstedge on the SCK pin (falling edge if CPOL
bit is set, rising edge if CPOL bit is reset) is the
MSBit capture strobe. Data is latched on the oc-
currence of the second clock transition.
The combination between the CPOL and CPHA
(clock phase) bits selects the data capture clock
edge.
This pin must be toggled high and low between
each byte transmitted (see Figure 53).
To protect the transmission from a write collision a
low value on the SS pin of a slave device freezes
the data in its SPIDR register and does not allow it
to be altered. Therefore the SS pin must be high to
write a new data byte in the SPIDR without pro-
ducing a write collision.
Figure 54, shows an SPI transfer with the four
combinations of the CPHA and CPOL bits. The di-
agram may be interpreted as a master or slave
timing diagram where the SCK pin, the MISO pin,
the MOSI pin are directly connected between the
master and the slave device.
Note: The SPI must be disabled by resetting the
SPE bit if the CPOL bit is changed at the commu-
nication byte boundaries.
The SS pin is the slave device select input and can
be driven by the master device.
10.5.4.5 Output Disable
In order to free the I/O pin so it can be used for oth-
er purposes, it is possible to disable the SPI output
function by setting the SOD bit in the SPICSR reg-
ister.
Figure 53. CPHA / SS Timing Diagram
Byte 3
Byte 2
MOSI/MISO
Master SS
Byte 1
Slave SS
(CPHA=0)
Slave SS
(CPHA=1)
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SERIAL PERIPHERAL INTERFACE (Cont’d)
Figure 54. Data Clock Timing Diagram
CPHA =1
CPOL = 1
CPOL = 0
Bit 4
Bit 4
Bit3
Bit 2
Bit 2
Bit 1
Bit 1
LSBit
LSBit
MSBit
MSBit
Bit 6
Bit 6
Bit 5
Bit 5
MISO
(from master)
Bit3
MOSI
(from slave)
SS
(to slave)
CAPTURE STROBE
CPHA =0
CPOL = 1
CPOL = 0
Bit 4
Bit 4
Bit3
Bit 2
Bit 2
Bit 1
Bit 1
LSBit
LSBit
MISO
(from master)
MSBit
Bit 6
Bit 6
Bit 5
Bit 5
Bit3
MOSI
(from slave)
MSBit
SS
(to slave)
CAPTURE STROBE
Note: This figure should not be used as a replacement for parametric information.
Refer to the Electrical Characteristics chapter.
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SERIAL PERIPHERAL INTERFACE (Cont’d)
10.5.4.6 Write Collision Error
When the CPHA bit is reset:
A write collision occurs when the software tries to
write to the SPIDR register while a data transfer is
taking place with an external device. When this
happens, the transfer continues uninterrupted;
and the software write will be unsuccessful.
Data is latched on the occurrence of the first clock
transition. The slave device does not have any
way of knowing when that transition will occur;
therefore, the slave device collision occurs when
software attempts to write the SPIDR register after
its SS pin has been pulled low.
Write collisions can occur both in master and slave
mode.
For this reason, the SS pin must be high, between
each data byte transfer, to allow the CPU to write
in the DR register without generating a write colli-
sion.
Note: a ”read collision” will never occur since the
received data byte is placed in a buffer in which
access is always synchronous with the MCU oper-
ation.
In Slave mode
In Master mode
When the CPHA bit is set:
Collision in the master device is defined as a write
of the SPIDR register while the internal serial clock
(SCK) is in the process of transfer.
The slave device will receive a clock (SCK) edge
prior to the latch of the first data transfer. This first
clock edge will freeze the data in the slave device
SPIDR register and output the MSBit on to the ex-
ternal MISO pin of the slave device.
The SS pin signal must be always high on the
master device.
The SS pin low state enables the slave device but
the output of the MSBit onto the MISO pin does
not take place until the first data transfer clock
edge.
WCOL bit
The WCOL bit in the SPICSR register is set if a
write collision occurs.
No SPI interrupt is generated when the WCOL bit
is set (the WCOL bit is a status flag only).
Clearing the WCOL bit is done through a software
sequence (see Figure 55).
Figure 55. Clearing the WCOL bit (Write Collision Flag) Software Sequence
Clearing sequence after SPIF = 1 (end of a data byte transfer)
Read SPICSR
Read SPICSR
1st Step
2nd Step
OR
THEN
THEN
SPIF =0
WCOL=0
SPIF =0
WCOL=0 if no transfer has started
WCOL=1 if a transfer has started
before the 2nd step
Write SPIDR
Read SPIDR
Clearing sequence before SPIF = 1 (during a data byte transfer)
Read SPICSR
1st Step
THEN
Note: Writing in SPIDR register
2nd Step
Read SPIDR
instead of reading in it do not re-
set WCOL bit
WCOL=0
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SERIAL PERIPHERAL INTERFACE (Cont’d)
10.5.4.7 Master Mode Fault
may be restored to their original state during or af-
ter this clearing sequence.
Master mode fault occurs when the master device
has its SS pin pulled low, then the MODF bit is set.
Hardware does not allow the user to set the SPE
and MSTR bits while the MODF bit is set except in
the MODF bit clearing sequence.
Master mode fault affects the SPI peripheral in the
following ways:
In a slave device the MODF bit can not be set, but
in a multi master configuration the device can be in
slave mode with this MODF bit set.
– The MODF bit is set and an SPI interrupt is
generated if the SPIE bit is set.
– The SPE bit is reset. This blocks all output
from the device and disables the SPI periph-
eral.
The MODF bit indicates that there might have
been amulti-master conflict for system control and
allows a proper exit from system operation to a re-
set or default system state using an interrupt rou-
tine.
– The MSTR bit is reset, thus forcing the device
into slave mode.
Clearing the MODF bit is done through a software
sequence:
10.5.4.8 Overrun Condition
An overrun condition occurs, when the master de-
vice has sent a data byte and the slave device has
not cleared the SPIF bit issued from the previous
data byte transmitted, then the OVR bit is set and
an interrupt is generated if the SPIE bit is set.
1. A read or write access to the SR register while
the MODF bit is set.
2. A write to the CR register.
In this case, the receiver buffer contains the byte
sent after the SPIF bit was last cleared. A read to
the SPIDR register returns this byte. All other
bytes are lost.
Notes: To avoid any multiple slave conflicts in the
case of a system comprising several MCUs, the
SS pin must be pulled high during the clearing se-
quence of the MODF bit. The SPE and MSTR bits
The OVR bit is cleared just after it has been read.
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SERIAL PERIPHERAL INTERFACE (Cont’d)
10.5.4.9 Single Master and Multimaster Configurations
There are two types of SPI systems:
– Single Master System
For more security, the slave device may respond
to the master with the received data byte. Then the
master will receive the previous byte back from the
slave device if all MISO and MOSI pins are con-
nected and the slave has not written its DR regis-
ter.
– Multimaster System
Single Master System
Other transmission security methods can use
ports for handshake lines or data bytes with com-
mand fields.
A typical single master system may be configured,
using an MCU as the master and four MCUs as
slaves (see Figure 56).
Multi-Master System
The master device selects the individual slave de-
vices by using four pins of a parallel port to control
the four SS pins of the slave devices.
A multi-master system may also be configured by
the user. Transfer of master control could be im-
plemented using a handshake method through the
I/O ports or by an exchange of code messages
through the serial peripheral interface system.
The SS pins are pulled high during reset since the
master device ports will be forced to be inputs at
that time, thus disabling the slave devices.
The multi-master system is principally handled by
the MSTR bit in the SPICR register and the MODF
bit in the SPICSR register.
Note: To prevent a bus conflict on the MISO line
the master allows only one active slave device
during a transmission.
Figure 56. Single Master Configuration
SS
SS
SS
SS
SCK
Slave
MCU
SCK
Slave
SCK
Slave
SCK
Slave
MCU
MCU
MCU
MISO
MOSI MISO
MOSI MISO
MOSI MISO
MOSI
MOSI MISO
SCK
Master
MCU
5V
SS
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SERIAL PERIPHERAL INTERFACE (Cont’d)
10.5.5 Register Description
CONTROL REGISTER (SPICR)
Read/Write
Bit 3 = CPOL Clock Polarity.
This bit is set and cleared by software. This bit de-
termines the steady state of the serial Clock. The
CPOL bit affects both the master and slave
modes.
0: The steady state is a low value at the SCK pin.
1: The steady state is a high value at the SCK pin.
Reset Value: 0000 xxxx (0xh)
7
0
SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0
Note: The SPI must be disabled by resetting SPE
bit if CPOL is changed at the communication byte
boundaries.
Bit 7 = SPIE Serial Peripheral Interrupt Enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SPI interrupt is generated whenever SPIF=1
or MODF=1 in the SR register
Bit 2 = CPHA Clock Phase.
This bit is set and cleared by software.
0: The first clock transition is the first data capture
edge.
1: The second clock transition is the first capture
edge.
Bit 6 = SPE Serial Peripheral Output Enable.
This bit is set and cleared by software. It is also
cleared by hardware when, in master mode, SS=0
(see Section 10.5.4.7 Master Mode Fault).
0: I/O port connected to pins
Bits 1:0 = SPR[1:0] Serial Peripheral Rate.
These bits are set and cleared by software. Used
with the SPR2 bit, they select one of six baud rates
to be used as the serial clock when the device is a
master.
1: SPI alternate functions connected to pins
The SPE bit is cleared by reset, so the SPI periph-
eral is not initially connected to the external pins.
These 2 bits have no effect in slave mode.
Bit 5 = SPR2 Divider Enable.
This bit is set and cleared by software and it is
cleared by reset. It is used with the SPR[1:0] bits to
set the baud rate. Refer to Table 18 Serial Periph-
eral Baud Rate.
0: Divider by 2 enabled
1: Divider by 2 disabled
Table 18. Serial Peripheral Baud Rate
Serial Clock
SPR2 SPR1 SPR0
f
f
/4
/8
1
0
0
1
0
0
0
0
0
1
1
1
0
0
1
0
0
1
CPU
CPU
Note: This bit has no effect in slave mode.
f
f
f
/16
/32
/64
CPU
CPU
CPU
Bit 4 = MSTR Master.
This bit is set and cleared by software. It is also
cleared by hardware when, in master mode, SS=0
(see Section 10.5.4.7 Master Mode Fault).
0: Slave mode is selected
f
/128
CPU
1: Master mode is selected, the function of the
SCK pin changes from an input to an output and
the functions of the MISO and MOSI pins are re-
versed.
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SERIAL PERIPHERAL INTERFACE (Cont’d)
CONTROL/STATUS REGISTER (SPICSR)
Read/Write (some bits Read Only)
Bit 2 = SOD SPI Output Disable.
This bit is set and cleared by software. When set it
disables the alternate function of the SPI output
(MOSI in master mode / MISO in slave mode)
0: SPI output not disabled
Reset Value: 0000 0000 (00h)
7
0
1: SPI output disabled
SPIF
WCOL OVR MODF
-
SOD SSM SSI
Bit 1 = SSM SS Mode Selection.
Bit 7 = SPIF Serial Peripheral Data Transfer Flag
(Read only).
This bit is set and cleared by software. When set, it
disables the alternate function of the SPI Slave
Select pin and use the SSI bit value instead.
0: Hardware mode (SS pin is used for Master/
Slave Selection).
This bit is set by hardware when a transfer has
been completed. An interrupt is generated if
SPIE=1 in the CR register. It is cleared by a soft-
ware sequence (an access to the SR register fol-
lowed by a read or write to the DR register).
0: Data transfer is in progress or has been ap-
proved by a clearing sequence.
1: Software mode (SSI bit is used for Master/Slave
Selection). SS is free to be used as a standard
I/O pin
1: Data transfer between the device and an exter-
nal device has been completed.
Note: Master mode selection also depends on the
value of the MSTR bit in the SPICR register
Note: While the SPIF bit is set, all writes to the DR
register are inhibited.
Bit 0 = SSI SS Internal Mode.
This bit is set and cleared by software. It replaces
pin SS of the SPI when bit SSM is set to 1. SSI bit
is active low slave select signal when SSM is set to
1.
Bit 6 = WCOL Write Collision status (Read only).
This bit is set by hardware when a write to the DR
register is done during a transmit sequence. It is
cleared by a software sequence (see Figure 55).
0: No write collision occurred
0 : Slave selected
1 : Slave not selected
1: A write collision has been detected
DATA I/O REGISTER (SPIDR)
Read/Write
Bit 5 = OVR SPI Overrun error (Read only).
This bit is set by hardware when the byte currently
being received in the shift register is ready to be
transferred into the SPIDR register while SPIF = 1
(See Section 10.5.4.8). An interrupt is generated if
SPIE = 1 in SPICR register. The OVR bit is cleared
by software reading the SPICSR register.
0: No overrun error
Reset Value: Undefined
7
0
D7
D6
D5
D4
D3
D2
D1
D0
The SPIDR register is used to transmit and receive
data on the serial bus. In the master device only a
write to this register will initiate transmission/re-
ception of another byte.
1: Overrun error detected
Bit 4 = MODF Mode Fault flag (Read only).
This bit is set by hardware when the SS pin is
pulled low in master mode (see Section 10.5.4.7
Master Mode Fault). An SPI interrupt can be gen-
erated if SPIE=1 in the SPICR register. This bit is
cleared by a software sequence (An access to the
SPICSR register while MODF=1 followed by a
write to the SPICR register).
Notes: During the last clock cycle the SPIF bit is
set, a copy of the received data byte in the shift
register is moved to a buffer. When the user reads
the serial peripheral data I/O register, the buffer is
actually being read.
Warning: A write to the SPIDR register places
data directly into the shift register for transmission.
0: No master mode fault detected
1: A fault in master mode has been detected
A read to the SPIDR register returns the value lo-
cated in the buffer and not the contents of the shift
register (see Figure 52).
Bits 3 = Reserved, must be kept cleared.
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SERIAL PERIPHERAL INTERFACE (Cont’d)
10.5.6 Low Power Modes
Mode
Description
No effect on SPI.
WAIT
SPI interrupt events cause the device to exit from WAIT mode.
SPI registers are frozen.
In HALT mode, the SPI is inactive. SPI operation resumes when the MCU is woken up by an interrupt with
“exit from HALT mode” capability. The data received is subsequently read from the SPIDR register when the
software is running (interrupt vector fetching). If several data are received before the wake-up event, then an
overrun error is generated. This error can be detected after the fetch of the interrupt routine that woke up the
device.
HALT
10.5.7 Interrupts
Enable
Control from
Bit
Exit
Exit
from
Halt
Event
Flag
Interrupt Event
Wait
Yes
Yes
Yes
SPI End of Transfer Event
Master Mode Fault Event
Overrun Error
SPIF
MODF
OVR
Yes
No
SPIE
No
Note: The SPI interrupt events are connected to the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC
register is reset (RIM instruction).
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SERIAL PERIPHERAL INTERFACE (Cont’d)
Table 19. SPI Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
SPIDR
Reset Value
MSB
x
LSB
x
0021h
0022h
0023h
x
x
x
x
x
x
SPICR
Reset Value
SPIE
0
SPE
0
SPR2
0
MSTR
0
CPOL
x
CPHA
x
SPR1
x
SPR0
x
SPICSR
Reset Value
SPIF
0
WCOL
0
OR
0
MODF
0
SOD
0
SSM
0
SSI
0
0
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10.6 SERIAL COMMUNICATIONS INTERFACE (SCI)
10.6.1 Introduction
The Serial Communications Interface (SCI) offers
a flexible means of full-duplex data exchange with
external equipment requiring an industry standard
NRZ asynchronous serial data format. The SCI of-
fers a very wide range of baud rates using two
baud rate generator systems.
10.6.3 General Description
The interface is externally connected to another
device by two pins (see Figure 58):
– TDO: Transmit Data Output. When the transmit-
ter is disabled, the output pin returns to its I/O
port configuration. When the transmitter is ena-
bled and nothing is to be transmitted, the TDO
pin is at high level.
10.6.2 Main Features
■ Full duplex, asynchronous communications
■ NRZ standard format (Mark/Space)
■ Dual baud rate generator systems
– RDI: Receive Data Input is the serial data input.
Oversampling techniques are used for data re-
covery by discriminating between valid incoming
data and noise.
■ Independently programmable transmit and
receive baud rates up to 250K baud.
Through these pins, serial data is transmitted and
received as frames comprising:
■ Programmable data word length (8 or 9 bits)
■ Receive buffer full, Transmit buffer empty and
– An Idle Line prior to transmission or reception
– A start bit
End of Transmission flags
■ Two receiver wake-up modes:
– Address bit (MSB)
– A data word (8 or 9 bits) least significant bit first
– A Stop bit indicating that the frame is complete.
Thisinterfaceusestwo typesofbaudrategenerator:
– Idle line
■ Muting functionformultiprocessorconfigurations
■ Separate enable bits for Transmitter and
– A conventional type for commonly-used baud
rates,
Receiver
■ Four error detection flags:
– Overrun error
– An extended type with a prescaler offeringa very
wide range of baud rates even with non-standard
oscillator frequencies.
– Noise error
– Frame error
– Parity error
■ Five interrupt sources with flags:
– Transmit data register empty
– Transmission complete
– Receive data register full
– Idle line received
– Overrun error detected
■ Parity control:
– Transmits parity bit
– Checks parity of received data byte
■ Reduced power consumption mode
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SERIAL COMMUNICATIONS INTERFACE (Cont’d)
Figure 57. SCI Block Diagram
Write
Read
(DATA REGISTER) DR
Received Data Register (RDR)
Received Shift Register
Transmit Data Register (TDR)
TDO
Transmit Shift Register
RDI
CR1
R8 T8 SCID
M WAKE PCE PS PIE
WAKE
UP
TRANSMIT
CONTROL
RECEIVER
CLOCK
RECEIVER
CONTROL
UNIT
CR2
SR
TIE TCIE RIE ILIE TE RE RWU SBK
TDRE TC RDRF IDLE OR NF FE
PE
SCI
INTERRUPT
CONTROL
TRANSMITTER
CLOCK
TRANSMITTER RATE
CONTROL
f
CPU
/PR
/16
BRR
SCP1SCP0SCT2 SCT1 SCT0SCR2SCR1SCR0
RECEIVER RATE
CONTROL
CONVENTIONAL BAUD RATE GENERATOR
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SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.6.4 Functional Description
10.6.4.1 Serial Data Format
The block diagram of the Serial Control Interface,
is shown in Figure 57. It contains 6 dedicated reg-
isters:
Word length may be selected as being either 8 or 9
bits by programming the M bit in the SCICR1 reg-
ister (see Figure 57).
– Two control registers (SCICR1 & SCICR2)
– A status register (SCISR)
The TDO pin is in low state during the start bit.
The TDO pin is in high state during the stop bit.
– A baud rate register (SCIBRR)
An Idle character is interpreted as an entire frame
of “1”s followed by the start bit of the next frame
which contains data.
– Anextended prescaler receiver register (SCIER-
PR)
A Break character is interpreted on receiving “0”s
for some multiple of the frame period. At the end of
the last break frame the transmitter inserts an ex-
tra “1” bit to acknowledge the start bit.
– An extended prescaler transmitter register (SCI-
ETPR)
Refer to the register descriptions in Section
10.6.7for the definitions of each bit.
Transmission and reception are driven by their
own baud rate generator.
Figure 58. Word Length Programming
9-bit Word length (M bit is set)
Possible
Next Data Frame
Parity
Data Frame
Start
Bit
Next
Start
Bit
Stop
Bit
Bit1 Bit2 Bit3
Bit5
Bit6
Bit8
Bit0
Bit4
Bit7
Bit
Start
Bit
Idle Frame
Start
Bit
Extra
’1’
Break Frame
8-bit Word length (M bit is reset)
Possible
Parity
Next Data Frame
Data Frame
Start
Bit
Next
Start
Bit
Stop
Bit
Bit2
Bit0
Bit1
Bit3
Bit4 Bit5
Bit6
Bit7
Bit
Start
Bit
Idle Frame
Start
Bit
Extra
’1’
Break Frame
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SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.6.4.2 Transmitter
When a frame transmission is complete (after the
stop bit or after the break frame) the TC bit is set
and an interrupt is generated if the TCIE is set and
the I bit is cleared in the CCR register.
The transmitter can send data words of either 8 or
9 bits depending on the M bit status. When the M
bit is set, word length is 9 bits and the 9th bit (the
MSB) has to be stored in the T8 bit in the SCICR1
register.
Clearing the TC bit is performed by the following
software sequence:
1. An access to the SCISR register
2. A write to the SCIDR register
Character Transmission
During an SCI transmission, data shifts out least
significant bit first on the TDO pin. In this mode,
the SCIDR register consists of a buffer (TDR) be-
tween the internal bus and the transmit shift regis-
ter (see Figure 57).
Note: The TDRE and TC bits are cleared by the
same software sequence.
Break Characters
Setting the SBK bit loads the shift register with a
break character. The break frame length depends
on the M bit (see Figure 58).
Procedure
– Select the M bit to define the word length.
As long as the SBK bit is set, the SCI send break
frames to the TDO pin. After clearing this bit by
software the SCI insert a logic 1 bit at the end of
the last break frame to guarantee the recognition
of the start bit of the next frame.
– Select the desired baud rate using the SCIBRR
and the SCIETPR registers.
– Set the TE bit to assign the TDO pin to the alter-
nate function and to send a idle frame as first
transmission.
Idle Characters
– Access the SCISR register and write the data to
send in the SCIDR register (this sequence clears
the TDRE bit). Repeat this sequence for each
data to be transmitted.
Setting the TE bit drives the SCI to send an idle
frame before the first data frame.
Clearing and then setting the TE bit during a trans-
mission sends an idle frame after the current word.
Clearing the TDRE bit is always performed by the
following software sequence:
1. An access to the SCISR register
2. A write to the SCIDR register
Note: Resetting and setting the TE bit causes the
data in the TDR register to be lost. Therefore the
best time to toggle the TE bit is when the TDRE bit
is set i.e. before writing the next byte in the SCIDR.
The TDRE bit is set by hardware and it indicates:
– The TDR register is empty.
– The data transfer is beginning.
– The next data can be written in the SCIDR regis-
ter without overwriting the previous data.
This flag generates an interrupt if the TIE bit is set
and the I bit is cleared in the CCR register.
When a transmission is taking place, a write in-
struction to the SCIDR register stores the data in
the TDR register and which is copied in the shift
register at the end of the current transmission.
When no transmission is taking place, a write in-
struction to the SCIDR register places the data di-
rectly in the shift register, the data transmission
starts, and the TDRE bit is immediately set.
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SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.6.4.3 Receiver
Overrun Error
The SCI can receive data words of either 8 or 9
bits. When the M bit is set, word length is 9 bits
and the MSB is stored in the R8 bit in the SCICR1
register.
An overrun error occurs when a character is re-
ceived when RDRF has not been reset. Data can
not be transferred from the shift register to the
RDR register as long as the RDRF bit is not
cleared.
Character reception
When a overrun error occurs:
– The OR bit is set.
During a SCI reception, data shifts in least signifi-
cant bit first through the RDI pin. In this mode, the
SCIDR register consists or a buffer (RDR) be-
tween the internal bus and the received shift regis-
ter (see Figure 57).
– The RDR content will not be lost.
– The shift register will be overwritten.
– An interrupt is generated if the RIE bit is set and
the I bit is cleared in the CCR register.
Procedure
– Select the M bit to define the word length.
The OR bit is reset by an access to the SCISR reg-
ister followed by a SCIDR register read operation.
– Select the desired baud rate using the SCIBRR
and the SCIERPR registers.
Noise Error
– Set the RE bit, this enables the receiver which
begins searching for a start bit.
Oversampling techniques are used for data recov-
ery by discriminating between valid incoming data
and noise.
When a character is received:
– The RDRF bit is set. It indicates that the content
of the shift register is transferred to the RDR.
When noise is detected in a frame:
– The NF is set at the rising edge of the RDRF bit.
– An interrupt is generated if the RIE bit is set and
the I bit is cleared in the CCR register.
– Data is transferred from the Shift register to the
SCIDR register.
– The error flags can be set if a frame error, noise
or an overrun error has been detected during re-
ception.
– No interrupt is generated. However this bit rises
at the same time as the RDRF bit which itself
generates an interrupt.
Clearing theRDRF bit isperformedby thefollowing
software sequence done by:
The NF bit is reset by a SCISR register read oper-
ation followed by a SCIDR register read operation.
1. An access to the SCISR register
2. A read to the SCIDR register.
Framing Error
A framing error is detected when:
The RDRF bit must be cleared before the endof the
reception of the next character to avoid an overrun
error.
– The stop bit is not recognized on reception at the
expected time, following either a de-synchroni-
zation or excessive noise.
Break Character
– A break is received.
When a break character is received, the SPI han-
dles it as a framing error.
When the framing error is detected:
– the FE bit is set by hardware
Idle Character
– Data is transferred from the Shift register to the
SCIDR register.
When a idle frame is detected, there is the same
procedure as a data received character plus an in-
terrupt if the ILIE bit is set and the I bit is cleared in
the CCR register.
– No interrupt is generated. However this bit rises
at the same time as the RDRF bit which itself
generates an interrupt.
The FE bit is reset by a SCISR register read oper-
ation followed by a SCIDR register read operation.
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SERIAL COMMUNICATIONS INTERFACE (Cont’d)
Figure 59. SCI Baud Rate and Extended Prescaler Block Diagram
TRANSMITTE R
CLOCK
EXTENDED PRESCALER TRANSMITTERRATE CONTROL
SCIETPR
EXTENDED TRANSMITTER PRESCALER REGISTER
SCIERPR
EXTENDED RECEIVER PRESCALER REGISTER
RECEIVER
CLOCK
EXTENDED PRESCALER RECEIVER RATE CONTROL
EXTENDED PRESCALER
f
CPU
TRANSMITTERRATE
CONTROL
/PR
/16
SCIBRR
SCP1
SCT2
SCT1 SCT0 SCR2 SCR1SCR0
SCP0
RECEIVER RATE
CONTROL
CONVENTIONAL BAUD RATE GENERATOR
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SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.6.4.4 Conventional Baud Rate Generation
other than zero. The baud rates are calculated as
follows:
The baud rate for the receiver and transmitter (Rx
and Tx) are set independently and calculated as
follows:
f
f
CPU
CPU
Rx =
16 ERPR*(PR*RR)
Tx =
16 ETPR*(PR*TR)
f
f
CPU
CPU
*
*
Rx =
(16 PR) RR
Tx =
(16 PR) TR
*
*
*
*
with:
with:
ETPR = 1,..,255 (see SCIETPR register)
ERPR = 1,.. 255 (see SCIERPR register)
10.6.4.6 Receiver Muting and Wake-up Feature
PR = 1, 3, 4 or 13 (see SCP[1:0] bits)
TR = 1, 2, 4, 8, 16, 32, 64,128
(see SCT[2:0] bits)
In multiprocessor configurations it is often desira-
ble that only the intended message recipient
should actively receive the full message contents,
thus reducing redundant SCI service overhead for
all non addressed receivers.
RR = 1, 2, 4, 8, 16, 32, 64,128
(see SCR[2:0] bits)
All these bits are in the SCIBRR register.
Example: If f is 8 MHz (normal mode) and if
PR=13 and TR=RR=1, the transmit and receive
baud rates are 38400 baud.
The non addressed devices may be placed in
sleep mode by means of the muting function.
CPU
Setting the RWU bit by software puts the SCI in
sleep mode:
Note: the baud rate registers MUST NOT be
changed while the transmitter or the receiver is en-
abled.
All the reception status bits can not be set.
All the receive interrupts are inhibited.
10.6.4.5 Extended Baud Rate Generation
A muted receiver may be awakened by one of the
following two ways:
The extended prescaler option gives a very fine
tuning onthe baud rate, using a 255 value prescal-
er, whereas the conventional Baud Rate Genera-
tor retains industry standard software compatibili-
ty.
– by Idle Line detection if the WAKE bit is reset,
– by Address Mark detection if the WAKE bit is set.
Receiver wakes-up by Idle Line detection when
the Receive line has recognised an Idle Frame.
Then the RWU bit is reset by hardware but the
IDLE bit is not set.
The extended baud rate generator block diagram
is described in the Figure 59.
The output clock rate sent to the transmitter or to
the receiver will be the output from the 16 divider
divided by a factor ranging from 1 to 255 set in the
SCIERPR or the SCIETPR register.
Receiver wakes-up by Address Mark detection
when it received a “1” as the most significant bit of
a word, thus indicating that the message is an ad-
dress. The reception of this particular word wakes
up the receiver, resets the RWU bit and sets the
RDRF bit, which allows the receiver to receive this
word normally and to use it as an address word.
Note: the extended prescaler is activated by set-
ting the SCIETPR or SCIERPR register to a value
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SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.6.4.7 Parity Control
(PS=0) or an odd number of “1s” if odd parity is se-
lected (PS=1). If the parity check fails, the PE flag
is set in the SCISR register and an interrupt is gen-
erated if PIE is set in the SCICR1 register.
Parity control (generation of parity bit in trasmis-
sion and and parity chencking in reception) can be
enabled by setting the PCE bit in the SCICR1 reg-
ister. Depending on the frame length defined by
the M bit, the possible SCI frame formats are as
listed in Table 20.
10.6.5 Low Power Modes
Mode
Description
Table 20. Frame Formats
No effect on SCI.
M bit
PCE bit
SCI frame
WAIT
SCI interrupts cause thedevice to exit
from Wait mode.
0
0
1
1
0
1
0
1
| SB | 8 bit data | STB |
| SB | 7-bit data | PB | STB |
| SB | 9-bit data | STB |
| SB | 8-bit data PB | STB |
SCI registers are frozen.
In Halt mode, the SCI stops transmit-
ting/receiving until Halt mode is exit-
ed.
HALT
Legend: SB = Start Bit, STB = Stop Bit,
PB = Parity Bit
Note: In case of wake up by an address mark, the
MSB bit of the data is taken into account and not
the parity bit
10.6.6 Interrupts
Interrupt Event
Enable Exit
Control from from
Exit
Event
Flag
Even parity: the parity bit is calculated to obtain
an even number of “1s” inside the frame made of
the 7 or 8 LSB bits (depending on whether M is
equal to 0 or 1) and the parity bit.
Bit
Wait
Halt
Transmit Data Register
Empty
TDRE
TC
TIE
Yes
No
Transmission Com-
plete
TCIE
RIE
Yes
Yes
Yes
No
No
No
Ex: data=00110101; 4 bits set => parity bit will be
0 if even parity is selected (PS bit = 0).
Received Data Ready
to be Read
RDRF
OR
Odd parity: the parity bit is calculated to obtain an
odd number of “1s” inside the frame made of the 7
or 8 LSB bits (depending on whether M is equal to
0 or 1) and the parity bit.
Overrrun Error Detect-
ed
Idle Line Detected
Parity Error
IDLE
PE
ILIE
PIE
Yes
Yes
No
No
Ex: data=00110101; 4 bits set => parity bit will be
1 if odd parity is selected (PS bit = 1).
The SCI interrupt events are connected to the
same interrupt vector.
Transmission mode: If the PCE bit is set then the
MSB bit of the data written in the data register is
not transmitted but is changed by the parity bit.
These events generate an interrupt if the corre-
sponding Enable Control Bit is set and the inter-
rupt mask in the CC register is reset (RIM instruc-
tion).
Reception mode: If the PCE bit is set then the in-
terface checks if the received data byte has an
even number of “1s” if even parity is selected
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SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.6.7 Register Description
curs). This bit is not set by an idle line when the re-
ceiver wakes up from wake-up mode.
STATUS REGISTER (SCISR)
Read Only
Reset Value: 1100 0000 (C0h)
Bit 3 = OR Overrun error.
This bit is set by hardware when the word currently
being received in the shift register is ready to be
transferred into the RDR register while RDRF=1.
An interrupt is generated if RIE=1 in the SCICR2
register. It is cleared by hardware when RE=0 by a
software sequence (an access to the SCISR regis-
ter followed by a read to the SCIDR register).
0: No Overrun error
7
0
TDRE
TC
RDRF IDLE
OR
NF
FE
PE
Bit 7 = TDRE Transmit data register empty.
This bit is set by hardware when the content of the
TDR register has been transferred into the shift
register. An interrupt is generated if the TIE bit=1
in the SCICR2 register. It is cleared by a software
sequence (an access to the SCISR register fol-
lowed by a write to the SCIDR register).
1: Overrun error is detected
Note: When this bit is set RDR register content will
not be lost but the shift register will be overwritten.
0: Data is not transferred to the shift register
1: Data is transferred to the shift register
Bit 2 = NF Noise flag.
This bit is set by hardware when noise is detected
on a received frame. It is cleared by hardware
when RE=0 by a software sequence (an access to
the SCISR register followed by a read to the
SCIDR register).
0: No noise is detected
1: Noise is detected
Note: Data will not be transferred to the shift reg-
ister unless the TDRE bit is cleared.
Bit 6 = TC Transmission complete.
This bit is set by hardware when transmission of a
frame containing Data, a Preamble or a Break is
complete. An interrupt is generated if TCIE=1 in
the SCICR2 register. It is cleared by a software se-
quence (an access to the SCISR register followed
by a write to the SCIDR register).
Note: This bit does not generate interrupt as it ap-
pears at the same time as the RDRF bit which it-
self generates an interrupt.
0: Transmission is not complete
1: Transmission is complete
Bit 1 = FE Framing error.
This bit is set by hardware when a de-synchroniza-
tion, excessive noise or a break character is de-
tected. It is cleared by hardware when RE=0 by a
software sequence (an access to the SCISR regis-
ter followed by a read to the SCIDR register).
0: No Framing error is detected
Bit 5 = RDRF Received data ready flag.
This bit is set by hardware when the content of the
RDR register has been transferred to the SCIDR
register. An interrupt is generated if RIE=1 in the
SCICR2 register. It is cleared by hardware when
RE=0 or by a software sequence (an access to the
SCISR register followed by a read to the SCIDR
register).
1: Framing error or break character is detected
Note: This bit does not generate interrupt as it ap-
pears at the same time as the RDRF bit which it-
self generates an interrupt. If the word currently
being transferred causes both frame error and
overrun error, it will be transferred and only the OR
bit will be set.
0: Data is not received
1: Received data is ready to be read
Bit 4 = IDLE Idle line detect.
This bit is set by hardware when a Idle Line is de-
tected. An interrupt is generated if the ILIE=1 in
the SCICR2 register. It is cleared by hardware
when RE=0 by a software sequence (an access to
the SCISR register followed by a read to the
SCIDR register).
Bit 0 = PE Parity error.
This bit is set by hardware when a parity error oc-
curs in receiver mode. It is cleared by a software
sequence (a read to the status register followed by
an access to the SCIDR data register). An inter-
rupt is generated if PIE=1 in the SCICR1 register.
0: No parity error
0: No Idle Line is detected
1: Idle Line is detected
Note: The IDLE bit will not be set again until the
RDRF bit has been set itself (i.e. anew idle line oc-
1: Parity error
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SERIAL COMMUNICATIONS INTERFACE (Cont’d)
CONTROL REGISTER 1 (SCICR1)
Read/Write
Bit 3 = WAKE Wake-Up method.
This bit determines the SCI Wake-Up method, it is
set or cleared by software.
0: Idle Line
Reset Value: x000 0000 (x0h)
7
0
1: Address Mark
R8
T8
SCID
M
WAKE PCE
PS
PIE
Bit 2 = PCE Parity control enable.
This bit selects the hardware parity control (gener-
ation and detection). When the parity control is en-
abled, the computed parity is inserted at the MSB
position (9th bit if M=1; 8th bit if M=0) and parity is
checked on the received data. This bit is set and
cleared by software. Once it is set, PCE is active
after the current byte (in reception and in transmis-
sion).
Bit 7 = R8 Receive data bit 8.
This bit is used to store the 9th bit of the received
word when M=1.
Bit 6 = T8 Transmit data bit 8.
This bit is used to store the 9th bit of the transmit-
ted word when M=1.
0: Parity control disabled
1: Parity control enabled
Bit 5 = SCID Disabled for low power consumption
When this bit is set the SCI prescalers and outputs
are stopped and the end of the current byte trans-
fer in order to reduce power consumption.This bit
is set and cleared by software.
0: SCI enabled
1: SCI prescaler and outputs disabled
Bit 1 = PS Parity selection.
This bit selects the odd or even parity when the
parity generation/detection is enabled (PCE bit
set). It is set and cleared by software. The parity
will be selected after the current byte.
0: Even parity
1: Odd parity
Bit 4 = M Word length.
This bit determines the word length. It is set or
cleared by software.
0: 1 Start bit, 8 Data bits, 1 Stop bit
1: 1 Start bit, 9 Data bits, 1 Stop bit
Bit 0 = PIE Parity interrupt enable.
This bit enables the interrupt capability of the hard-
ware parity control when a parity error is detected
(PE bit set). It is set and cleared by software.
0: Parity error interrupt disabled
Note: The M bit must not be modified during a data
transfer (both transmission and reception).
1: Parity error interrupt enabled.
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SERIAL COMMUNICATIONS INTERFACE (Cont’d)
CONTROL REGISTER 2 (SCICR2)
Read/Write
TDO pin to the alternate function. It is set and
cleared by software.
0: Transmitter is disabled, the TDO pin is back to
the I/O port configuration
Reset Value: 0000 0000 (00h)
1: Transmitter is enabled
7
0
Note: During transmission, a “0” pulse on the TE
bit (“0” followed by “1”) sends a preamble after the
current word.
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
Bit 7 = TIE Transmitter interrupt enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever
TDRE=1 in the SCISR register
Bit 2 = RE Receiver enable.
This bit enables the receiver. It is set and cleared
by software.
0: Receiver is disabled, it resets the RDRF, IDLE,
OR, NF and FE bits of the SCISR register
1: Receiver is enabled and begins searching for a
start bit
Bit 6 = TCIE Transmission complete interrupt ena-
ble
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever TC=1 in
the SCISR register
Bit 1 = RWU Receiver wake-up.
This bit determines if the SCI is in mute mode or
not. It is set and cleared by software and can be
cleared by hardware when a wake-up sequence is
recognized.
0: Receiver in Active mode
1: Receiver in Mute mode
Bit 5 = RIE Receiver interrupt enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
Note: Before selecting Mute mode (setting the
RWU bit), the SCI must receive some data first,
otherwise it cannot function in Mute mode with
wakeup by idle line detection.
1: An SCI interrupt is generated whenever OR=1
or RDRF=1 in the SCISR register
Bit 4 = ILIE Idle line interrupt enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever IDLE=1
in the SCISR register.
Bit 0 = SBK Send break.
This bit set is used to send break characters. It is
set and cleared by software.
0: No break character is transmitted
1: Break characters are transmitted
Bit 3 = TE Transmitter enable.
This bit enables the transmitter and assigns the
Note: If the SBK bit is set to “1” and then to “0”, the
transmitter will send a BREAK word at the end of
the current word.
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SERIAL COMMUNICATIONS INTERFACE (Cont’d)
DATA REGISTER (SCIDR)
Read/Write
Bits 5:3 = SCT[2:0] SCI Transmitter rate divisor
These 3 bits, in conjunction with the SCP1 & SCP0
bits define the total division applied to the bus
clock to yield the transmit rate clock inconvention-
al Baud Rate Generator mode.
Reset Value: Undefined
Contains the Received or Transmitted data char-
acter, depending on whether it is read from or writ-
ten to.
TR dividing factor
SCT2
SCT1
SCT0
1
2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
7
0
4
DR7
DR6
DR5
DR4
DR3
DR2
DR1
DR0
8
16
32
64
128
The Data register performs a double function (read
and write) since it is composed of two registers,
one for transmission (TDR) and one for reception
(RDR).
The TDR register provides the parallel interface
between the internal bus and the output shift reg-
ister (see Figure 57).
The RDR register provides the parallel interface
between the input shift register and the internal
bus (see Figure 57).
Bits 2:0 = SCR[2:0] SCI Receiver rate divisor.
These 3 bits, in conjunction with the SCP[1:0] bits
define the total division applied to the bus clock to
yield the receive rate clock in conventional Baud
Rate Generator mode.
RR Dividing factor
SCR2
SCR1
SCR0
BAUD RATE REGISTER (SCIBRR)
Read/Write
1
2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reset Value: 0000 0000 (00h)
4
7
0
8
16
32
64
128
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0
Bits 7:6= SCP[1:0] First SCI Prescaler
These 2 prescaling bits allow several standard
clock division ranges:
PR Prescaling factor
SCP1
SCP0
1
3
0
0
1
1
0
1
0
1
4
13
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SERIAL COMMUNICATIONS INTERFACE (Cont’d)
EXTENDED RECEIVE PRESCALER DIVISION
REGISTER (SCIERPR)
EXTENDED TRANSMIT PRESCALER DIVISION
REGISTER (SCIETPR)
Read/Write
Read/Write
Reset Value: 0000 0000 (00h)
Reset Value:0000 0000 (00h)
Allows setting of the Extended Prescaler rate divi-
sion factor for the receive circuit.
Allows setting of the External Prescaler rate divi-
sion factor for the transmit circuit.
7
0
7
0
ERPR ERPR ERPR ERPR ERPR ERPR ERPR ERPR
ETPR ETPR ETPR ETPR ETPR ETPR ETPR ETPR
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Bits 7:0 = ERPR[7:0] 8-bit Extended Receive
Prescaler Register.
Bits 7:0 = ETPR[7:0] 8-bit Extended Transmit
Prescaler Register.
The extended Baud Rate Generator is activated
when a value different from 00h is stored in this
register. Therefore the clock frequency issued
from the 16 divider (see Figure 59) is divided by
the binary factor set in the SCIERPR register (in
the range 1 to 255).
The extended Baud Rate Generator is activated
when a value different from 00h is stored in this
register. Therefore the clock frequency issued
from the 16 divider (see Figure 59) is divided by
the binary factor set in the SCIETPR register (in
the range 1 to 255).
The extended baud rate generator is not used af-
ter a reset.
The extended baud rate generator is not used af-
ter a reset.
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SERIAL COMMUNICATION INTERFACE (Cont’d)
Table 21. SCI Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
SCISR
Reset Value
TDRE
1
TC
1
RDRF
0
IDLE
0
OR
0
NF
0
FE
0
PE
0
0050h
0051h
0052h
0053h
0054h
0055h
0057h
SCIDR
Reset Value
MSB
x
LSB
x
x
x
x
x
x
x
SCIBRR
Reset Value
SCP1
0
SCP0
0
SCT2
x
SCT1
x
SCT0
x
SCR2
x
SCR1
x
SCR0
x
SCICR1
Reset Value
R8
x
T8
x
SCID
0
M
x
WAKE
x
PCE
0
PS
0
PIE
0
SCICR2
Reset Value
TIE
0
TCIE
0
RIE
0
ILIE
0
TE
0
RE
0
RWU
0
SBK
0
SCIERPR
Reset Value
MSB
0
LSB
0
0
0
0
0
0
0
0
0
0
0
0
0
SCIPETPR
Reset Value
MSB
0
LSB
0
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10.7 I C BUS INTERFACE (I2C)
10.7.1 Introduction
handshake. The interrupts are enabled or disabled
2
2
by software. The interface is connected to the I C
The I C Bus Interface serves as an interface be-
tween the microcontroller and the serial I C bus. It
2
bus by a data pin (SDAI) and by a clock pin (SCLI).
2
It can be connected both with a standard I C bus
provides both multimaster and slave functions,
2
2
and a Fast I C bus. This selection is made by soft-
and controls all I C bus-specific sequencing, pro-
2
ware.
tocol, arbitration and timing. It supports fast I C
mode (400kHz).
Mode Selection
10.7.2 Main Features
The interface can operate in the four following
modes:
2
■ Parallel-bus/I C protocol converter
– Slave transmitter/receiver
■ Multi-master capability
– Master transmitter/receiver
By default, it operates in slave mode.
■ 7-bit/10-bit Addressing
■ Transmitter/Receiver flag
■ End-of-byte transmission flag
■ Transfer problem detection
The interface automatically switches from slave to
master after it generates a START condition and
from master to slave in case of arbitration loss or a
STOP generation, allowing then Multi-Master ca-
pability.
2
I C Master Features:
■ Clock generation
2
■ I C bus busy flag
Communication Flow
■ Arbitration Lost Flag
In Master mode, it initiates a data transfer and
generates the clock signal. A serial data transfer
always begins with a start condition and ends with
a stop condition. Both start and stop conditions are
generated in master mode by software.
■ End of byte transmission flag
■ Transmitter/Receiver Flag
■ Start bit detection flag
■ Start and Stop generation
In Slave mode, the interface is capable of recog-
nising its own address (7 or 10-bit), and the Gen-
eral Call address. The General Call address de-
tection may be enabled or disabled by software.
2
I C Slave Features:
■ Stop bit detection
2
■ I C bus busy flag
Data and addresses are transferred as 8-bit bytes,
MSB first. The first byte(s) following the start con-
dition contain the address (one in 7-bit mode, two
in 10-bit mode). The address is always transmitted
in Master mode.
■ Detection of misplaced start or stop condition
2
■ Programmable I C Address detection
■ Transfer problem detection
■ End-of-byte transmission flag
■ Transmitter/Receiver flag
10.7.3 General Description
A 9th clock pulse follows the 8 clock cycles of a
byte transfer, during which the receiver must send
an acknowledge bit to the transmitter. Refer to Fig-
ure 60.
In addition to receiving and transmitting data, this
interface converts it from serial to parallel format
and vice versa, using either an interrupt or polled
2
Figure 60. I C BUS Protocol
SDA
MSB
ACK
SCL
1
2
8
9
START
STOP
CONDITION
CONDITION
VR02119B
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2
I C BUS INTERFACE (Cont’d)
Acknowledge may be enabled and disabled by
software.
The SCL frequency (F ) is controlled by a pro-
scl
grammable clock divider which depends on the
2
2
I C bus mode.
The I C interface address and/or general call ad-
2
dress can be selected by software.
When the I C cell is enabled, the SDA and SCL
2
ports must be configured as floating inputs. In this
case, the value of the external pull-up resistor
used depends on the application.
The speed of the I C interface may be selected
2
between Standard (0-100KHz) and Fast I C (100-
400KHz).
2
When the I C cell is disabled, the SDA and SCL
ports revert to being standard I/O port pins.
SDA/SCL Line Control
Transmitter mode: the interface holds the clock
line low before transmission to wait for the micro-
controller to write the byte in the Data Register.
Receiver mode: the interface holds the clock line
low after reception to wait for the microcontroller to
read the byte in the Data Register.
2
Figure 61. I C Interface Block Diagram
DATA REGISTER (DR)
DATA CONTROL
SDA or SDAI
DATA SHIFT REGISTER
COMPARATOR
OWN ADDRESS REGISTER1 (OAR1)
OWN ADDRESS REGISTER 2 (OAR2)
CLOCK CONTROL
SCL or SCLI
CLOCK CONTROL REGISTER (CCR)
CONTROL REGISTER (CR)
STATUS REGISTER 1 (SR1)
STATUS REGISTER 2 (SR2)
CONTROL LOGIC
INTERRUPT
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I C BUS INTERFACE (Cont’d)
10.7.4 Functional Description
– EVF and BTF bits are set with an interrupt if the
ITE bit is set.
Refer to the CR, SR1 and SR2 registers in Section
10.7.7. for the bit definitions.
Then the interface waits for a read of the SR1 reg-
ister followed by a read of the DR register, holding
the SCL line low (see Figure 62 Transfer se-
quencing EV2).
2
By default the I C interface operates in Slave
mode (M/SL bit is cleared) except when it initiates
a transmit or receive sequence.
First the interface frequency must be configured
using the FRi bits in the OAR2 register.
Slave Transmitter
Following the address reception and after SR1
register has been read, the slave sends bytes from
the DR register to the SDA line via the internal shift
register.
10.7.4.1 Slave Mode
As soon as a start condition is detected, the
address is received from the SDA line and sent to
the shift register; then it is compared with the
address of the interface or the General Call
address (if selected by software).
The slave waits for a read of the SR1 register fol-
lowed by a write in the DR register, holding the
SCL line low (see Figure 62 Transfer sequencing
EV3).
Note: In 10-bit addressing mode, the comparision
includes the header sequence (11110xx0) and the
two most significant bits of the address.
When the acknowledge pulse is received:
Header matched (10-bit mode only): the interface
generates an acknowledge pulse if the ACK bit is
set.
– The EVF and BTF bits are set by hardware with
an interrupt if the ITE bit is set.
Address not matched: the interface ignores it
Closing slave communication
and waits for another Start condition.
After the last data byte is transferred a Stop Con-
dition is generated by the master. The interface
detects this condition and sets:
Address matched: the interface generates in se-
quence:
– Acknowledge pulse if the ACK bit is set.
– EVF and STOPF bits with an interrupt if the ITE
bit is set.
– EVFand ADSL bits are set with an interrupt if the
ITE bit is set.
Then the interface waits for a read of the SR2 reg-
ister (see Figure 62 Transfer sequencing EV4).
Then the interface waits for a read of the SR1 reg-
ister, holding the SCL line low (see Figure 62
Transfer sequencing EV1).
Next, in 7-bit mode read the DR register to deter-
mine from the least significant bit (Data Direction
Bit) if the slave must enter Receiver or Transmitter
mode.
Error Cases
– BERR: Detection of a Stop or a Start condition
during a byte transfer. In this case, the EVF and
the BERR bits are set with an interrupt if the ITE
bit is set.
If it is a Stop then the interface discards thedata,
released the lines and waits for another Start
condition.
In 10-bit mode, after receiving the address se-
quence the slave is always in receive mode. It will
enter transmit mode on receiving a repeated Start
condition followed by the header sequence with
matching address bits and the least significant bit
set (11110xx1) .
If it is a Start then the interface discards the data
and waits for the next slave address on the bus.
– AF: Detection of a non-acknowledge bit. In this
case, the EVF and AF bits are set with an inter-
rupt if the ITE bit is set.
Slave Receiver
Following the address reception and after SR1
register has been read, the slave receives bytes
from the SDA line into the DR register via the inter-
nal shift register. After each byte the interface gen-
erates in sequence:
Note: In both cases, SCL line is not held low; how-
ever, SDA line can remain low due to possible «0»
bits transmitted last. It is then necessary to release
both lines by software.
– Acknowledge pulse if the ACK bit is set
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2
I C BUS INTERFACE (Cont’d)
How to release the SDA / SCL lines
After completion of this transfer (and acknowledge
from the slave if the ACK bit is set):
Set and subsequently clear the STOP bit while
BTF is set. The SDA/SCL lines are released after
the transfer of the current byte.
– The EVF bit is set by hardware with interrupt
generation if the ITE bit is set.
10.7.4.2 Master Mode
Then the master waits for a read of the SR1 regis-
ter followed by a write in the CR register (for exam-
ple set PE bit), holding the SCL line low (see Fig-
ure 62 Transfer sequencing EV6).
To switch from default Slave mode to Master
mode a Start condition generation is needed.
Start condition
Next the master must enter Receiver or Transmit-
ter mode.
Setting the START bit while the BUSY bit is
cleared causes the interface to switch to Master
mode (M/SL bit set) and generates a Start condi-
tion.
Note: In 10-bit addressing mode, to switch the
master to Receiver mode, software must generate
a repeated Start condition and resend the header
sequence with the least significant bit set
(11110xx1).
Once the Start condition is sent:
– The EVF and SB bits are set by hardware with
an interrupt if the ITE bit is set.
Then the master waits for a read of the SR1 regis-
ter followed by a write in the DR register with the
Slave address, holding the SCL line low (see
Figure 62 Transfer sequencing EV5).
Master Receiver
Following the address transmission and after SR1
and CR registers have been accessed, the master
receives bytes from the SDA line into the DR reg-
ister via the internal shift register. After each byte
the interface generates in sequence:
Slave address transmission
– Acknowledge pulse if if the ACK bit is set
Then the slave address is sent to the SDA line via
the internal shift register.
– EVFand BTF bits are set by hardware withan in-
terrupt if the ITE bit is set.
In 7-bit addressing mode, one address byte is
sent.
Then the interface waits for a read of the SR1 reg-
ister followed by a read of the DR register, holding
the SCL line low (see Figure 62 Transfer se-
quencing EV7).
In 10-bit addressing mode, sending the first byte
including the header sequence causes the follow-
ing event:
– The EVF bit is set by hardware with interrupt
generation if the ITE bit is set.
Then the master waits for a read of the SR1 regis-
ter followed by a write in the DR register, holding
the SCL line low (see Figure 62 Transfer se-
quencing EV9).
To close the communication: before reading the
last byte from the DR register, set the STOP bit to
generate the Stop condition. The interface goes
automatically back to slave mode (M/SL bit
cleared).
Note: In order to generate the non-acknowledge
pulse after the last received data byte, the ACK bit
must be cleared just before reading the second
last data byte.
Then the second address byte is sent by the inter-
face.
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2
I C BUS INTERFACE (Cont’d)
Master Transmitter
BERR bits are set by hardware with an interrupt
if ITE is set.
Following the address transmission and after SR1
register has been read, the master sends bytes
from the DR register to the SDA line via the inter-
nal shift register.
– AF: Detection of a non-acknowledge bit. In this
case, the EVF and AF bits are set by hardware
with an interrupt if the ITE bit is set. To resume,
set the START or STOP bit.
The master waits for a read of the SR1 register fol-
lowed by a write in the DR register, holding the
SCL line low (see Figure 62 Transfer sequencing
EV8).
– ARLO: Detection of an arbitration lost condition.
In this case theARLO bit is set by hardware (with
an interrupt if the ITE bit is set and the interface
goes automatically backto slave mode (the M/SL
bit is cleared).
When the acknowledge bit is received, the
interface sets:
Note: In all these cases, the SCL line is not held
low; however, the SDA line can remain low due to
possible «0» bits transmitted last. It is then neces-
sary to release both lines by software.
– EVF and BTF bits with an interrupt if the ITE bit
is set.
To close the communication: after writing the last
byte to the DR register, set the STOP bit to gener-
ate the Stop condition. The interface goes auto-
matically back to slave mode (M/SL bit cleared).
Error Cases
– BERR: Detection of a Stop or a Start condition
during a bytetransfer. In this case, the EVF and
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2
I C BUS INTERFACE (Cont’d)
Figure 62. Transfer Sequencing
7-bit Slave receiver:
S
Address
A
Data1
A
Data1
Data1
Data2
EV3
A
DataN
A
P
.....
EV1
EV2
A
EV2
A
EV2
NA
EV4
7-bit Slave transmitter:
S
Address
A
Data2
DataN
P
.....
.....
EV1 EV3
EV3
EV3-1
EV4
7-bit Master receiver:
S
Address
A
A
Data2
A
DataN NA
P
EV5
EV6
EV7
A
EV7
A
EV7
A
7-bit Master transmitter:
S
Address
A
Data1
Data2
DataN
P
.....
EV5
EV6 EV8
EV8
EV8
EV8
10-bit Slave receiver:
S
Header
A
Address
A
Data1
A
DataN
A
P
.....
EV1
EV2
EV2
EV4
10-bit Slave transmitter:
S
Header
A
Data1
A
A
DataN
....
.
A
P
r
EV1 EV3
EV6 EV8
EV3
EV3-1
EV4
10-bit Master transmitter
S
Header
A
Address
A
Data1
DataN
A
P
.....
EV5
EV9
EV8
A
EV8
A
10-bit Master receiver:
S
Header
A
Data1
DataN
P
r
.....
EV5
EV6
EV7
EV7
Legend: S=Start, S = Repeated Start, P=Stop, A=Acknowledge, NA=Non-acknowledge,
r
EVx=Event (with interrupt if ITE=1)
EV1: EVF=1, ADSL=1, cleared by reading SR1 register.
EV2: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register.
EV3: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register.
EV3-1: EVF=1, AF=1, BTF=1; AF is cleared by reading SR1 register. BTF is cleared by releasing the
lines (STOP=1, STOP=0) or by writing DR register (DR=FFh). Note: If lines are released by
STOP=1, STOP=0, the subsequent EV4 is not seen.
EV4: EVF=1, STOPF=1, cleared by reading SR2 register.
EV5: EVF=1, SB=1, cleared by reading SR1 register followed by writing DR register.
EV6: EVF=1, cleared by reading SR1 register followed by writing CR register (for example PE=1).
EV7: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register.
EV8: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register.
EV9: EVF=1, ADD10=1, cleared by reading SR1 register followed by writing DR register.
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I C BUS INTERFACE (Cont’d)
10.7.5 Low Power Modes
Mode
Description
2
No effect on I C interface.
WAIT
HALT
2
I C interrupts cause the device to exit from WAIT mode.
2
I C registers are frozen.
2
2
In HALT mode, the I C interface is inactive and does not acknowledge data on the bus. The I C interface
resumes operation when the MCU is woken up by an interrupt with “exit from HALT mode” capability.
10.7.6 Interrupts
Figure 63. Event Flags and Interrupt Generation
ADD10
ITE
BTF
ADSL
SB
INTERRUPT
EVF
AF
STOPF
ARLO
BERR
*
* EVF can also be set by EV6 or an error from the SR2 register.
Enable
Control from
Bit
Exit
Exit
from
Halt
Event
Flag
Interrupt Event
Wait
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
10-bit Address Sent Event (Master mode)
End of Byte Transfer Event
ADD10
BTF
No
No
No
No
No
No
No
No
Address Matched Event (Slave mode)
Start Bit Generation Event (Master mode)
Acknowledge Failure Event
ADSEL
SB
ITE
AF
Stop Detection Event (Slave mode)
Arbitration Lost Event (Multimaster configuration)
Bus Error Event
STOPF
ARLO
BERR
2
Note: The I C interrupt events are connected to
the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding
Enable Control Bitis set and the I-bit in the CC reg-
ister is reset (RIM instruction).
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I C BUS INTERFACE (Cont’d)
10.7.7 Register Description
2
Bit 2 = ACK Acknowledge enable.
I C CONTROL REGISTER (CR)
Read / Write
Reset Value: 0000 0000 (00h)
This bit is set and cleared by software. It is also
cleared by hardware when the interface is disa-
bled (PE=0).
7
0
0: No acknowledge returned
1: Acknowledge returned after an address byte or
a data byte is received
0
0
PE
ENGC START ACK STOP
ITE
Bit 1 = STOP Generation of a Stop condition.
This bit is set and cleared by software. It is also
cleared by hardware in master mode. Note: This
bit is not cleared when the interface is disabled
(PE=0).
Bit 7:6 = Reserved. Forced to 0 by hardware.
Bit 5 = PE Peripheral enable.
This bit is set and cleared by software.
0: Peripheral disabled
1: Master/Slave capability
Notes:
– When PE=0, all the bits of the CR register and
the SR register except the Stop bit are reset. All
outputs are released while PE=0
– In master mode:
0: No stop generation
1: Stop generation after the current byte transfer
or after the current Start condition is sent. The
STOP bit is cleared by hardware when the Stop
condition is sent.
– When PE=1, the corresponding I/O pins are se-
lected by hardware as alternate functions.
– In slave mode:
0: No stop generation
1: Release the SCL and SDA lines after the cur-
rent byte transfer (BTF=1). In this mode the
STOP bit has to be cleared by software.
2
– Toenable the I C interface, write the CR register
TWICE with PE=1 as the first write only activates
the interface (only PE is set).
Bit 4 = ENGC Enable General Call.
This bit is set and cleared by software. It is also
cleared by hardware when the interface is disa-
bled (PE=0). The 00h General Call address is ac-
knowledged (01h ignored).
Bit 0 = ITE Interrupt enable.
This bit is set and cleared by software and cleared
by hardware when the interface is disabled
(PE=0).
0: Interrupts disabled
1: Interrupts enabled
Refer to Figure 63 for the relationship between the
events and the interrupt.
SCL is held low when the ADD10, SB, BTF or
ADSL flags or an EV6 event (See Figure 62) is de-
tected.
0: General Call disabled
1: General Call enabled
Bit 3 = START Generation of a Start condition.
This bit is set and cleared by software. It is also
cleared by hardware when the interface is disa-
bled (PE=0) or when the Start condition is sent
(with interrupt generation if ITE=1).
– In master mode:
0: No start generation
1: Repeated start generation
– In slave mode:
0: No start generation
1: Start generation when the bus is free
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I C BUS INTERFACE (Cont’d)
2
I C STATUS REGISTER 1 (SR1)
arbitration (ARLO=1) or when the interface is disa-
bled (PE=0).
0: Data byte received (if BTF=1)
1: Data byte transmitted
Read Only
Reset Value: 0000 0000 (00h)
7
0
Bit 4 = BUSY Bus busy.
EVF ADD10 TRA BUSY BTF ADSL M/SL
SB
This bit is set by hardware on detection of a Start
condition and cleared by hardware on detection of
a Stop condition. It indicates a communication in
progress on the bus. This information is still updat-
ed when the interface is disabled (PE=0).
0: No communication on the bus
Bit 7 = EVF Event flag.
This bit is set by hardware as soon as an event oc-
curs. It is cleared by software reading SR2 register
in case of error event or as described in Figure 62.
It is also cleared by hardware when the interface is
disabled (PE=0).
1: Communication ongoing on the bus
Bit 3 = BTF Byte transfer finished.
0: No event
1: One of the following events has occurred:
This bit is set by hardware as soon as a byte is cor-
rectly received or transmitted with interrupt gener-
ation if ITE=1. It is cleared by software reading
SR1 register followed by a read or write of DR reg-
ister. It is also cleared by hardware when the inter-
face is disabled (PE=0).
– BTF=1 (Byte received or transmitted)
– ADSL=1 (Address matched in Slave mode
while ACK=1)
– SB=1 (Start condition generated in Master
mode)
– Following a byte transmission, this bit is set after
reception of the acknowledge clock pulse. In
case an address byte is sent, this bit is set only
after the EV6 event (See Figure 62). BTF is
cleared by reading SR1 register followed by writ-
ing the next byte in DR register.
– AF=1 (No acknowledge received after byte
transmission)
– STOPF=1 (Stop condition detected in Slave
mode)
– Following a byte reception, this bit is set after
transmission of the acknowledge clock pulse if
ACK=1. BTF is cleared by reading SR1 register
followed by reading the byte from DR register.
– ARLO=1 (Arbitration lost in Master mode)
– BERR=1 (Bus error, misplaced Start or Stop
condition detected)
– ADD10=1 (Master has sent header byte)
The SCL line is held low while BTF=1.
– Address byte successfully transmitted in Mas-
ter mode.
0: Byte transfer not done
1: Byte transfer succeeded
Bit 6 = ADD10 10-bit addressing in Master mode.
This bit is set by hardware when the master has
sent the first byte in 10-bit address mode. It is
cleared by software reading SR2 register followed
by a write in the DR register of the second address
byte. It is also cleared by hardware when the pe-
ripheral is disabled (PE=0).
Bit 2 = ADSL Address matched (Slave mode).
This bit is set by hardware as soon as the received
slave address matched with the OAR register con-
tent or a general call is recognized. An interrupt is
generated if ITE=1. It is cleared by software read-
ing SR1 register or by hardware when the inter-
face is disabled (PE=0).
0: No ADD10 event occurred.
1: Master has sent first address byte (header)
The SCL line is held low while ADSL=1.
0: Address mismatched or not received
1: Received address matched
Bit 5 = TRA Transmitter/Receiver.
When BTF is set, TRA=1 if a data byte has been
transmitted. It is cleared automatically when BTF
is cleared. It is also cleared by hardware after de-
tection of Stop condition (STOPF=1), loss of bus
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I C BUS INTERFACE (Cont’d)
Bit 1 = M/SL Master/Slave.
Bit 2 = ARLO Arbitration lost.
This bit is set by hardware as soon as the interface
is in Master mode (writing START=1). It is cleared
by hardware after detecting a Stop condition on
the bus or a loss of arbitration (ARLO=1). It is also
cleared when the interface is disabled (PE=0).
0: Slave mode
This bit is set by hardware when the interface los-
es the arbitration of the bus to another master. An
interrupt is generated if ITE=1. It is cleared by soft-
ware reading SR2 register or by hardware when
the interface is disabled (PE=0).
After an ARLO event the interface switches back
automatically to Slave mode (M/SL=0).
1: Master mode
The SCL line is not held low while ARLO=1.
Bit 0 = SB Start bit (Master mode).
This bit is set by hardware as soon as the Start
condition is generated (following
0: No arbitration lost detected
1: Arbitration lost detected
a
write
START=1). An interrupt is generated if ITE=1. It is
cleared by software reading SR1 register followed
by writing the address byte in DRregister. It is also
cleared by hardware when the interface is disa-
bled (PE=0).
0: No Start condition
1: Start condition generated
Bit 1 = BERR Bus error.
This bit is set by hardware when the interface de-
tects a misplaced Start or Stop condition. An inter-
rupt is generated if ITE=1. It is cleared by software
reading SR2 register or by hardware when the in-
terface is disabled (PE=0).
The SCL line is not held low while BERR=1.
2
I C STATUS REGISTER 2 (SR2)
0: No misplaced Start or Stop condition
1: Misplaced Start or Stop condition
Read Only
Reset Value: 0000 0000 (00h)
7
0
0
Bit 0 = GCAL General Call (Slave mode).
This bit is set by hardware when a general call ad-
dress is detected on the bus while ENGC=1. It is
cleared by hardware detecting a Stop condition
(STOPF=1) or when the interface is disabled
(PE=0).
0
0
AF STOPF ARLO BERR GCAL
Bit 7:5 = Reserved. Forced to 0 by hardware.
0: No general call address detected on bus
1: general call address detected on bus
Bit 4 = AF Acknowledge failure.
This bit is set by hardware when no acknowledge
is returned. An interrupt is generated if ITE=1. It is
cleared by software reading SR2 register or by
hardware when the interface is disabled (PE=0).
The SCL line is not held low while AF=1.
0: No acknowledge failure
1: Acknowledge failure
Bit 3 = STOPF Stop detection (Slave mode).
This bit is set by hardware when a Stop condition
is detected on the bus after an acknowledge (if
ACK=1). An interrupt is generated if ITE=1. It is
cleared by software reading SR2 register or by
hardware when the interface is disabled (PE=0).
The SCL line is not held low while STOPF=1.
0: No Stop condition detected
1: Stop condition detected
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2
I C BUS INTERFACE (Cont’d)
2
I C CLOCK CONTROL REGISTER (CCR)
2
Read / Write
I C DATA REGISTER (DR)
Reset Value: 0000 0000 (00h)
Read / Write
Reset Value: 0000 0000 (00h)
7
0
7
0
FM/SM CC6
CC5
CC4
CC3
CC2
CC1
CC0
D7
D6
D5
D4
D3
D2
D1
D0
2
Bit 7 = FM/SM Fast/Standard I C mode.
This bit is set and cleared by software. It is not
cleared when the interface is disabled (PE=0).
2
Bit 7:0 = D7-D0 8-bit Data Register.
These bits contain the byte to be received or trans-
mitted on the bus.
0: Standard I C mode
2
1: Fast I C mode
– Transmitter mode: Byte transmission start auto-
matically when the software writes in the DR reg-
ister.
Bit 6:0 = CC6-CC0 7-bit clock divider.
These bits select the speed of the bus (F
) de-
SCL
2
pending on the I C mode. They are not cleared
when the interface is disabled (PE=0).
– Receiver mode: the first data byte is received au-
tomatically in the DR register using the least sig-
nificant bit of the address.
Then, the following data bytes are received one
by one after reading the DR register.
– Standard mode (FM/SM=0): F
<= 100kHz
SCL
F
= F
/(2x([CC6..CC0]+2))
SCL
CPU
– Fast mode (FM/SM=1): F
> 100kHz
SCL
F
= F
/(3x([CC6..CC0]+2))
SCL
CPU
Note: The programmed F
SCL and SDA lines.
assumes no load on
SCL
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2
I C BUS INTERFACE (Cont’d)
2
2
I C OWN ADDRESS REGISTER (OAR1)
I C OWN ADDRESS REGISTER (OAR2)
Read / Write
Reset Value: 0000 0000 (00h)
Read / Write
Reset Value: 0100 0000 (40h)
7
0
7
0
0
ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0
FR1
FR0
0
0
0
ADD9 ADD8
7-bit Addressing Mode
Bit 7:6 = FR1-FR0 Frequency bits.
Bit 7:1 = ADD7-ADD1 Interface address.
These bits define the I C bus address of the inter-
face. They are not cleared when the interface is
disabled (PE=0).
These bits are set by software only when the inter-
face is disabled(PE=0). To configure the interface
2
2
to I C specifed delays select the value corre-
sponding to the microcontroller frequency F
.
CPU
F
Range (MHz)
2.5 - 6
FR1
0
FR0
CPU
Bit 0 = ADD0 Address direction bit.
This bit is don’t care, the interface acknowledges
either 0 or 1. It is not cleared when the interface is
disabled (PE=0).
0
1
0
1
6 -10
0
10 - 14
1
14 - 24
1
Note: Address 01h is always ignored.
Bit 5:3 = Reserved
Bit 2:1 = ADD9-ADD8 Interface address.
These are the most significant bits of the I C bus
address of the interface (10-bit mode only). They
are not cleared when the interface is disabled
(PE=0).
10-bit Addressing Mode
Bit 7:0 = ADD7-ADD0 Interface address.
These are the least significant bits of the I C bus
address of the interface. They are not cleared
when the interface is disabled (PE=0).
2
2
Bit 0 = Reserved.
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I C BUS INTERFACE (Cont’d)
2
Table 22. I C Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
I2CCR
Reset Value
PE
0
ENGC
0
START
0
ACK
0
STOP
0
ITE
0
0018h
0019h
001Ah
001Bh
001Ch
001Dh
001Eh
0
0
I2CSR1
Reset Value
EVF
0
ADD10
0
TRA
0
BUSY
0
BTF
0
ADSL
0
M/SL
0
SB
0
I2CSR2
Reset Value
AF
0
STOPF
0
ARLO
0
BERR
0
GCAL
0
0
0
0
I2CCCR
Reset Value
FM/SM
0
CC6
0
CC5
0
CC4
0
CC3
0
CC2
0
CC1
0
CC0
0
I2COAR1
Reset Value
ADD7
0
ADD6
0
ADD5
0
ADD4
0
ADD3
0
ADD2
0
ADD1
0
ADD0
0
I2COAR2
Reset Value
FR1
0
FR0
1
ADD9
0
ADD8
0
0
0
0
0
0
0
0
I2CDR
Reset Value
MSB
0
LSB
0
0
0
0
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10.8 10-BIT A/D CONVERTER (ADC)
10.8.1 Introduction
■ Data register (DR) which contains the results
■ Conversion complete status flag
The on-chip Analog to Digital Converter (ADC) pe-
ripheral is a 10-bit, successive approximation con-
verter with internal sample and hold circuitry. This
peripheral has up to 16 multiplexed analog input
channels (refer to device pin out description) that
allow the peripheral to convert the analog voltage
levels from up to 16 different sources.
■ On/off bit (to reduce consumption)
The block diagram is shown in Figure 64.
10.8.3 Functional Description
10.8.3.1 Analog Power Supply
V
and V
are the high and low level refer-
SSA
DDA
The result of the conversion is stored in a 10-bit
Data Register. The A/D converter is controlled
through a Control/Status Register.
ence voltage pins. In some devices (refer to device
pin out description) they are internally connected
to the V and V pins.
DD
SS
10.8.2 Main Features
Conversion accuracy may therefore be impacted
by voltage drops and noise in the event of heavily
loaded or badly decoupled power supply lines.
■ 10-bit conversion
■ Up to 16 channels with multiplexed input
■ Linear successive approximation
Figure 64. ADC Block Diagram
f
CPU
DIV 2
0
1
f
ADC
CH3
EOC SPEEDADON
0
CH2 CH1 CH0
ADCCSR
4
AIN0
AIN1
ANALOG TO DIGITAL
CONVERTER
ANALOG
MUX
AINx
ADCDRH
D9
D8
D7
D6 D5
D4
D3
D2
ADCDRL
0
0
0
0
0
0
D1 D0
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10-BIT A/D CONVERTER (ADC) (Cont’d)
10.8.3.2 Digital A/D Conversion Result
When a conversion is complete:
The conversion is monotonic, meaning that the re-
sult never decreases if the analog input does not
and never increases if the analog input does not.
– The EOC bit is set by hardware.
– The result is in the ADCDR registers.
A read to the ADCDRH resets the EOC bit.
If the input voltage (V ) is greater than V
AIN
DDA
(high-level voltage reference) then the conversion
result is FFh in the ADCDRH register and 03h in
the ADCDRL register (without overflow indication).
To read the 10 bits, perform the following steps:
1. Poll EOC bit
If the input voltage (V ) is lower than V
level voltage reference) then the conversion result
in the ADCDRH and ADCDRL registers is 00 00h.
(low-
2. Read ADCDRL
AIN
SSA
3. Read ADCDRH. This clears EOC automati-
cally.
The A/D converter is linear and the digital result of
the conversion is stored in the ADCDRH and AD-
CDRL registers. The accuracy of the conversion is
described in the Electrical Characteristics Section.
To read only 8 bits, perform the following steps:
1. Poll EOC bit
R
is the maximum recommended impedance
2. Read ADCDRH. This clears EOC automati-
cally.
AIN
for an analog input signal. If the impedance is too
high, this will result in a loss of accuracy due to
leakage and sampling not being completed in the
alloted time.
10.8.4 Low Power Modes
10.8.3.3 A/D Conversion
Note: The A/D converter may be disabled by re-
setting the ADON bit. This feature allows reduced
power consumption when no conversion is need-
ed and between single shot conversions.
The analog input ports must be configured as in-
put, no pull-up, no interrupt. Refer to the «I/O
ports» chapter. Using these pins as analog inputs
does not affect the ability of the port to be read as
a logic input.
Mode
Description
WAIT
No effect on A/D Converter
A/D Converter disabled.
In the ADCCSR register:
– Select the CS[2:0] bits to assign the analog
channel to convert.
After wakeup from Halt mode, the A/D
Converter requires a stabilisation time
ADC Conversion mode
HALT
t
(see Electrical Characteristics)
STAB
In the ADCCSR register:
before accurate conversions can be
performed.
Set the ADON bit to enable the A/D converter and
to start the conversion. From this time on, the
ADC performs a continuous conversion of the
selected channel.
10.8.5 Interrupts
None.
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ST72321J, ST72324J/K
10-BIT A/D CONVERTER (ADC) (Cont’d)
10.8.6 Register Description
CONTROL/STATUSREGISTER (ADCCSR)
Read/Write (Except bit 7 read only)
Reset Value: 0000 0000 (00h)
Bit 3:0 = CH[3:0] Channel Selection
These bits are set and cleared by software. They
select the analog input to convert.
Channel Pin*
CH3
CH2 CH1 CH0
7
0
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
AIN10
AIN11
AIN12
AIN13
AIN14
AIN15
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
EOC SPEED ADON
0
CH3
CH2
CH1
CH0
Bit 7 = EOC End of Conversion
This bit is set by hardware. It is cleared by soft-
ware reading the ADCDRH register.
0: Conversion is not complete
1: Conversion complete
Bit 6 = SPEED ADC clock selection
This bit is set and cleared by software.
0: f
1: f
= f
= f
/2
CPU
CPU
ADC
ADC
Bit 5 = ADON A/D Converter on
*The number of channels is device dependent. Refer to
the device pinout description.
This bit is set and cleared by software.
0: Enable ADC and start conversion
1: Disable ADC and stop conversion
DATA REGISTER (ADCDRH)
Read Only
Bit 4 = Reserved. Must be kept cleared.
Reset Value: 0000 0000 (00h)
7
0
D9
D8
D7
D6
D5
D4
D3
D2
Bit 7:0 = D[9:2] MSB of Analog Converted Value
DATA REGISTER (ADCDRL)
Read Only
Reset Value: 0000 0000 (00h)
7
0
0
0
0
0
0
0
D1
D0
Bit 7:2 = Reserved. Forced by hardware to 0.
Bit 1:0 = D[1:0] LSB of Analog Converted Value
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ST72321J, ST72324J/K
10-BIT A/D CONVERTER (Cont’d)
Table 23. ADC Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
ADCCSR
Reset Value
EOC
0
SPEED
0
ADON
0
CH3
0
CH2
0
CH1
0
CH0
0
0070h
0071h
0072h
0
ADCDRH
Reset Value
D9
0
D8
0
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
ADCDRL
Reset Value
D1
0
D0
0
0
0
0
0
0
0
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11 INSTRUCTION SET
11.1 ST7 ADDRESSING MODES
so, most of the addressing modes may be subdi-
vided in two sub-modes called long and short:
The ST7 Core features 17 different addressing
modes which can be classified in 7 main groups:
– Long addressing mode is more powerful be-
cause itcan use the full 64 Kbyte address space,
however it uses more bytes and more CPU cy-
cles.
Addressing Mode
Inherent
Example
nop
– Short addressing mode is less powerful because
it can generally only access page zero (0000h -
00FFh range), but the instruction size is more
compact, and faster. All memory to memory in-
structions use short addressing modes only
(CLR, CPL, NEG, BSET, BRES, BTJT, BTJF,
INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP)
Immediate
Direct
ld A,#$55
ld A,$55
ld A,($55,X)
ld A,([$55],X)
jrne loop
Indexed
Indirect
Relative
Bit operation
bset byte,#5
The ST7 Assembler optimizes the use of long and
short addressing modes.
The ST7 Instruction set is designed to minimize
the number of bytes required per instruction: To do
Table 24. ST7 Addressing Mode Overview
Pointer
Address
(Hex.)
Pointer Size
(Hex.)
Length
(Bytes)
Mode
Syntax
Destination
Inherent
Immediate
Short
Long
nop
+ 0
ld A,#$55
+ 1
+ 1
+ 2
+ 0
+ 1
+ 2
+ 2
+ 2
+ 2
+ 2
+ 1
+ 2
+ 1
+ 2
+ 2
+ 3
Direct
ld A,$10
00..FF
Direct
ld A,$1000
ld A,(X)
0000..FFFF
00..FF
No Offset
Short
Long
Direct
Indexed
Indexed
Indexed
Direct
ld A,($10,X)
ld A,($1000,X)
ld A,[$10]
00..1FE
0000..FFFF
00..FF
Direct
Short
Long
Indirect
Indirect
Indirect
Indirect
Direct
00..FF
byte
word
byte
word
ld A,[$10.w]
ld A,([$10],X)
ld A,([$10.w],X)
jrne loop
0000..FFFF 00..FF
00..1FE 00..FF
Short
Long
Indexed
Indexed
0000..FFFF 00..FF
PC+/-127
Relative
Relative
Bit
Indirect
Direct
jrne [$10]
PC+/-127
00..FF
00..FF
00..FF
00..FF
00..FF
00..FF
00..FF
byte
byte
byte
bset $10,#7
bset [$10],#7
btjt $10,#7,skip
btjt [$10],#7,skip
Bit
Indirect
Direct
Bit
Relative
Relative
Bit
Indirect
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ST72321J, ST72324J/K
INSTRUCTION SET OVERVIEW (Cont’d)
11.1.1 Inherent
11.1.3 Direct
All Inherent instructions consist of a single byte.
The opcode fully specifies all the required informa-
tion for the CPU to process the operation.
In Direct instructions, the operands are referenced
by their memory address.
The direct addressing mode consists of two sub-
modes:
Inherent Instruction
Function
No operation
Direct (short)
NOP
The address is a byte, thus requires only one byte
after the opcode, but only allows 00 - FF address-
ing space.
TRAP
S/W Interrupt
Wait For Interrupt (Low Pow-
er Mode)
WFI
Direct (long)
Halt Oscillator (Lowest Power
Mode)
HALT
The address is a word, thus allowing 64 Kbyte ad-
dressing space, but requires 2 bytes after the op-
code.
RET
Sub-routine Return
Interrupt Sub-routine Return
Set Interrupt Mask (level 3)
Reset Interrupt Mask (level 0)
Set Carry Flag
IRET
SIM
11.1.4 Indexed (No Offset, Short, Long)
RIM
In this mode, the operand is referenced by its
memory address, which is defined by the unsigned
addition of an index register (X or Y) with an offset.
SCF
RCF
Reset Carry Flag
RSP
Reset Stack Pointer
Load
The indirect addressing mode consists of three
sub-modes:
LD
CLR
Clear
Indexed (No Offset)
PUSH/POP
INC/DEC
TNZ
Push/Pop to/from the stack
Increment/Decrement
Test Negative or Zero
1 or 2 Complement
Byte Multiplication
There is no offset, (no extra byte after the opcode),
and allows 00 - FF addressing space.
Indexed (Short)
CPL, NEG
MUL
The offset is a byte, thus requires only one byte af-
ter the opcode and allows 00 - 1FE addressing
space.
SLL, SRL, SRA, RLC,
RRC
Shift and Rotate Operations
Swap Nibbles
Indexed (long)
The offset is a word, thus allowing 64 Kbyte ad-
dressing space and requires 2 bytes after the op-
code.
SWAP
11.1.2 Immediate
Immediate instructions have two bytes, the first
byte contains the opcode, the second byte con-
tains the operand value.
11.1.5 Indirect (Short, Long)
The required data byte to do the operation is found
by its memory address, located in memory (point-
er).
Immediate Instruction
Function
LD
Load
The pointer address follows the opcode. The indi-
rect addressing mode consists of two sub-modes:
CP
Compare
BCP
Bit Compare
Indirect (short)
AND, OR, XOR
ADC, ADD, SUB, SBC
Logical Operations
Arithmetic Operations
The pointer address is a byte, the pointer size is a
byte, thus allowing 00 - FF addressing space, and
requires 1 byte after the opcode.
Indirect (long)
The pointer address is a byte, the pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.
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ST72321J, ST72324J/K
INSTRUCTION SET OVERVIEW (Cont’d)
11.1.6 Indirect Indexed (Short, Long)
11.1.7 Relative mode (Direct, Indirect)
This is a combination of indirect and short indexed
addressing modes. The operand is referenced by
its memory address, which is defined by the un-
signed addition of an index register value (X or Y)
with a pointer value located in memory. The point-
er address follows the opcode.
This addressing mode is used to modify the PC
register value, by adding an 8-bit signed offset to
it.
Available Relative
Direct/Indirect
Instructions
Function
The indirect indexed addressing mode consists of
two sub-modes:
JRxx
CALLR
Conditional Jump
Call Relative
Indirect Indexed (Short)
The pointer address is a byte, the pointer size is a
byte, thus allowing 00 - 1FE addressing space,
and requires 1 byte after the opcode.
The relative addressing mode consists of two sub-
modes:
Relative (Direct)
Indirect Indexed (Long)
The offset is following the opcode.
Relative (Indirect)
The pointer address is a byte, the pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.
The offset is defined in memory, which address
follows the opcode.
Table 25. Instructions Supporting Direct,
Indexed, Indirect and Indirect Indexed
Addressing Modes
Long and Short
Function
Instructions
LD
Load
CP
Compare
AND, OR, XOR
Logical Operations
Arithmetic Additions/Sub-
stractions operations
ADC, ADD, SUB, SBC
BCP
Bit Compare
Short Instructions
Only
Function
CLR
Clear
INC, DEC
TNZ
Increment/Decrement
Test Negative or Zero
1 or 2 Complement
Bit Operations
CPL, NEG
BSET, BRES
Bit Test and Jump Opera-
tions
BTJT, BTJF
SLL, SRL, SRA, RLC,
RRC
Shift and Rotate Opera-
tions
SWAP
Swap Nibbles
CALL, JP
Call or Jump subroutine
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ST72321J, ST72324J/K
INSTRUCTION SET OVERVIEW (Cont’d)
11.2 INSTRUCTION GROUPS
The ST7 family devices use an Instruction Set
consisting of 63 instructions. The instructions may
be subdivided into 13 main groups as illustrated in
the following table:
Load and Transfer
LD
CLR
POP
DEC
TNZ
OR
Stack operation
PUSH
INC
RSP
BCP
Increment/Decrement
Compare and Tests
Logical operations
CP
AND
BSET
BTJT
ADC
SLL
XOR
CPL
NEG
Bit Operation
BRES
BTJF
ADD
SRL
JRT
Conditional Bit Test and Branch
Arithmetic operations
Shift and Rotates
SUB
SRA
JRF
SBC
RLC
JP
MUL
RRC
CALL
SWAP
CALLR
SLA
Unconditional Jump or Call
Conditional Branch
JRA
JRxx
TRAP
SIM
NOP
RET
Interruption management
Code Condition Flag modification
WFI
RIM
HALT
SCF
IRET
RCF
Using a pre-byte
The instructions are described with one to four op-
codes.
These prebytes enable instruction in Y as well as
indirect addressing modes to be implemented.
They precede the opcode of the instruction in X or
the instruction using direct addressing mode. The
prebytes are:
In order to extend the number of available op-
codes for an 8-bit CPU (256 opcodes), three differ-
ent prebyte opcodes are defined. These prebytes
modify the meaning of the instruction they pre-
cede.
PDY 90
Replace an X based instruction
using immediate, direct, indexed, or inherent ad-
dressing mode by a Y one.
The whole instruction becomes:
PIX 92
Replace an instruction using di-
PC-2
PC-1
PC
End of previous instruction
Prebyte
rect, direct bit, or direct relative addressing mode
to an instruction using the corresponding indirect
addressing mode.
opcode
It also changes an instruction using X indexed ad-
dressing mode to an instruction using indirect X in-
dexed addressing mode.
PC+1
Additional word (0 to 2) according
to the number of bytes required to compute the ef-
fective address
PIY 91
Replace an instruction using X in-
direct indexed addressing mode by a Y one.
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INSTRUCTION SET OVERVIEW (Cont’d)
Mnemo
ADC
ADD
AND
BCP
Description
Add with Carry
Function/Example
A = A + M + C
A = A + M
Dst
Src
I1
H
H
H
I0
N
N
N
N
N
Z
Z
Z
Z
Z
C
C
C
A
M
Addition
A
M
M
M
Logical And
A = A . M
A
Bit compare A, Memory
Bit Reset
tst (A . M)
A
BRES
BSET
BTJF
BTJT
CALL
CALLR
CLR
bres Byte, #3
bset Byte, #3
btjf Byte, #3, Jmp1
btjt Byte, #3, Jmp1
M
M
M
M
Bit Set
Jump if bit is false (0)
Jump if bit is true (1)
Call subroutine
Call subroutine relative
Clear
C
C
reg, M
reg
0
N
N
N
1
Z
Z
Z
CP
Arithmetic Compare
One Complement
Decrement
tst(Reg - M)
A = FFH-A
dec Y
M
C
1
CPL
reg, M
reg, M
DEC
HALT
IRET
INC
Halt
1
0
Interrupt routine return
Increment
Pop CC, A, X, PC
inc X
I1
H
I0
N
N
Z
Z
C
reg, M
JP
Absolute Jump
Jump relative always
Jump relative
Never jump
jp [TBL.w]
JRA
JRT
JRF
jrf *
JRIH
JRIL
Jump if Port B INT pin = 1 (no Port B Interrupts)
Jump if Port B INT pin = 0 (Port B interrupt)
JRH
Jump if H = 1
H = 1 ?
JRNH
JRM
Jump if H = 0
H = 0 ?
Jump if I1:0 = 11
Jump if I1:0 <> 11
Jump if N = 1 (minus)
Jump if N = 0 (plus)
Jump if Z = 1 (equal)
I1:0 = 11 ?
I1:0 <> 11 ?
N = 1 ?
JRNM
JRMI
JRPL
JREQ
JRNE
JRC
N = 0 ?
Z = 1 ?
Jump if Z = 0 (not equal) Z = 0 ?
Jump if C = 1
Jump if C = 0
Jump if C = 1
C = 1 ?
JRNC
JRULT
C = 0 ?
Unsigned <
Jmp if unsigned >=
Unsigned >
JRUGE Jump if C = 0
JRUGT Jump if (C + Z = 0)
131/176
ST72321J, ST72324J/K
INSTRUCTION SET OVERVIEW (Cont’d)
Mnemo
JRULE
LD
Description
Jump if (C + Z = 1)
Load
Function/Example
Unsigned <=
dst <= src
Dst
Src
I1
H
I0
N
N
N
N
N
Z
Z
Z
Z
Z
C
reg, M
A, X, Y
reg, M
M, reg
X, Y, A
MUL
NEG
NOP
OR
Multiply
X,A = X * A
neg $10
0
0
Negate (2’s compl)
No Operation
OR operation
C
A = A + M
pop reg
pop CC
push Y
C = 0
A
M
reg
CC
M
M
POP
Pop from the Stack
M
I1
1
H
I0
0
C
0
PUSH
RCF
RET
RIM
Push onto the Stack
Reset carry flag
Subroutine Return
Enable Interrupts
Rotate left true C
Rotate right true C
Reset Stack Pointer
Substract with Carry
Set carry flag
reg, CC
I1:0 = 10 (level 0)
C <= A <= C
C => A => C
S = Max allowed
A = A - M - C
C = 1
RLC
RRC
RSP
SBC
SCF
SIM
reg, M
reg, M
N
N
Z
Z
C
C
A
M
N
Z
C
1
Disable Interrupts
Shift left Arithmetic
Shift left Logic
I1:0 = 11 (level 3)
C <= A <= 0
C <= A <= 0
0 => A => C
A7 => A => C
A = A - M
1
1
SLA
reg, M
reg, M
reg, M
reg, M
A
N
N
0
Z
Z
Z
Z
Z
Z
Z
C
C
C
C
C
SLL
SRL
SRA
SUB
SWAP
TNZ
TRAP
WFI
Shift right Logic
Shift right Arithmetic
Substraction
N
N
N
N
M
M
SWAP nibbles
A7-A4 <=> A3-A0
tnz lbl1
reg, M
Test for Neg & Zero
S/W trap
S/W interrupt
1
1
1
0
Wait for Interrupt
Exclusive OR
XOR
A = A XOR M
A
N
Z
132/176
ST72321J, ST72324J/K
12 ELECTRICAL CHARACTERISTICS
12.1 PARAMETER CONDITIONS
Unless otherwise specified, all voltages are re-
12.1.5 Pin input voltage
ferred to V
.
SS
The input voltage measurement on a pin of the de-
vice is described in Figure 66.
12.1.1 Minimum and Maximum values
Unless otherwise specified the minimum and max-
imum values are guaranteed in the worst condi-
tions of ambient temperature, supply voltage and
frequencies by tests in production on 100% of the
Figure 66. Pin input voltage
devices with an ambient temperature at T =25°C
A
ST7 PIN
and T =T max (given by the selected temperature
A
A
range).
V
Data based on characterization results, design
simulation and/or technology characteristics are
indicated in the table footnotes and are not tested
in production. Based on characterization, the min-
imum and maximum values refer to sample tests
and represent the mean value plus or minus three
times the standard deviation (mean±3Σ).
IN
12.1.2 Typical values
Unless otherwise specified, typical data are based
on T =25°C, V =5V (for the 4.5V≤V ≤5.5V
A
DD
DD
voltage range) and V =3.3V (for the 3V≤V ≤4V
DD
DD
voltage range). They are given only as design
guidelines and are not tested.
12.1.3 Typical curves
Unless otherwise specified, all typical curves are
given only as design guidelines and are not tested.
12.1.4 Loading capacitor
The loading conditions used for pin parameter
measurement are shown in Figure 65.
Figure 65. Pin loading conditions
ST7 PIN
C
L
133/176
ST72321J, ST72324J/K
12.2 ABSOLUTE MAXIMUM RATINGS
Stresses above those listed as “absolute maxi-
mum ratings” may cause permanent damage to
the device. This is a stress rating only and func-
tional operation of the device under these condi-
tions is not implied. Exposure to maximum rating
conditions for extended periods may affect device
reliability.
12.2.1 Voltage Characteristics
Symbol
Ratings
Maximum value
Unit
V
V
- V
Supply voltage
6.5
14
DD
PP
SS
SS
- V
Programming Voltage
V
Input Voltage on true open drain pin
VSS-0.3 to 6.5
1) & 2)
V
IN
Input voltage on any other pin
V
SS-0.3 to VDD+0.3
|∆V
| and |∆V
|
SSx
Variations between different digital power pins
Variations between digital and analog ground pins
Electro-static discharge voltage (Human Body Model)
Electro-static discharge voltage (Machine Model)
50
50
DDx
mV
|V
- V
|
SSA
SSx
ESD(HBM)
V
see Section 12.7.3 on page 148
V
ESD(MM)
12.2.2 Current Characteristics
Symbol
Ratings
Maximum value
Unit
3)
3)
I
Total current into V power lines (source)
150
150
25
VDD
DD
I
Total current out of V ground lines (sink)
SS
VSS
Output current sunk by any standard I/O and control pin
Output current sunk by any high sink I/O pin
I
50
IO
Output current source by any I/Os and control pin
- 25
± 5
± 5
± 5
± 5
± 25
mA
Injected current on V pin
PP
Injected current on RESET pin
2) & 4)
I
INJ(PIN)
Injected current on OSC1 and OSC2 pins
5) & 6)
Injected current on any other pin
2)
5)
ΣI
Total injected current (sum of all I/O and control pins)
INJ(PIN)
12.2.3 Thermal Characteristics
Symbol
Ratings
Value
Unit
T
Storage temperature range
-65 to +150
°C
STG
T
Maximum junction temperature (see Section 13.2 THERMAL CHARACTERISTICS)
J
Notes:
1. Directly connecting the RESET and I/O pins to V or V could damage the device if an unintentional internal reset
DD
SS
is generated or an unexpected change of the I/O configuration occurs (for example, due to a corrupted program counter).
To guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7kΩ for
RESET, 10kΩ for I/Os). For the same reason, unused I/O pins must not be directly tied to V or V
.
DD
SS
2. When the current limitation is not possible, the V absolute maximum rating must be respected, otherwise refer to
IN
I
specification. A positive injection is induced by V >V while a negative injection is induced by V <V
.
INJ(PIN)
IN
DD
IN
SS
3. All power (V ) and ground (V ) lines must always be connected to the external supply.
DD
SS
4. Negative injection disturbs the analog performance of the device. In particular, it induces leakage currents throughout
the device including the analog inputs. To avoid undesirable effects on the analog functions, care must be taken:
- Analog input pins must have a negative injection less than 0.8 mA (assuming that the impedance of the analog voltage
is lower than the specified limits)
- Pure digital pins must have a negative injection less than 1.6mA. In addition, it is recommended to inject the current as
far as possible from the analog input pins.
5. When several inputs are submitted to a current injection, the maximum ΣI
is the absolute sum of the positive
INJ(PIN)
and negative injected currents (instantaneous values). These results are based on characterisation with ΣI
mum current injection on four I/O port pins of the device.
maxi-
INJ(PIN)
6. True open drain I/O port pins do not accept positive injection.
134/176
ST72321J, ST72324J/K
12.3 OPERATING CONDITIONS
12.3.1 General Operating Conditions
Symbol
Parameter
Conditions
Min
Max
Unit
FLASH: 2.7V ≤ V ≤ 5.5V
4
DD
1)
2)
f
Internal clock frequency versus V
0
MHz
FLASH: 3.85V ≤ V ≤ 5.5V
CPU
DD
DD
8
ROM: 2.7V ≤ V ≤ 5.5V
DD
1 Suffix Version
5 Suffix Version
6 Suffix Version
7 Suffix Version
3 Suffix Version
0
70
85
-10
-40
-40
-40
T
Ambient temperature range
85
°C
A
105
125
Notes:
1. Guaranteed by construction. A/D operation and resonator oscillator start-up are not guaranteed below 1 MHz.
2. This value is the minimum LVD V value when the highest LVD threshold is selected.
IT-
135/176
ST72321J, ST72324J/K
OPERATING CONDITIONS (Cont’d)
12.3.2 Operating Conditions with Low Voltage Detector (LVD)
Subject to general operating conditions for V , f
, and T .
A
DD OSC
Conditions
High Threshold
1)
Symbol
Parameter
Min
Typ
Max
Unit
2)
4.10
3.75
3.25
4.30
3.90
3.35
4.50
4.05
3.45
Reset release threshold
2)
2)
V
Med. Threshold
Low Threshold
IT+
(V rise)
DD
V
High Threshold
Med. Threshold
Low Threshold
3.85
3.50
3.00
4.05
3.65
3.10
4.25
3.80
3.20
Reset generation threshold
V
V
IT-
(V fall)
DD
LVD voltage threshold hysteresis
V
-V
IT+ IT-
200
5
250
300
5000
40
mV
µs/V
ns
hys
3)
Vt
V
rise time rate
DD
POR
2)
t
Filtered glitch delay on V
Not detected by the LVD
g(VDD)
DD
Notes:
1. LVD typical data are based on T =25°C. They are given only as design guidelines and are not tested.
A
2. Data based on characterization results, not tested in production.
3. The V rise time rate condition isneeded to insure a correct device power-on and LVD reset. Not tested in production.
DD
12.3.3 Internal Voltage Detector (IVD) Thresholds
Subject to general operating condition for V , f
, and T .
DD OSC
A
1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
V
VD level = Low in option byte
VD level = Med. in option byte
VD level = High in option byte
3.60
4.00
4.95
1
0 VDF flag toggle threshold
V
IT+
(V rise)
DD
VD level = Low in option byte
VD level = Med. in option byte
VD level = High in option byte
3.35
3.75
4.70
0
1 VDF flag toggle threshold
V
V
IT-
(V fall)
DD
IVD voltage threshold hysteresis
V
-V
IT+ IT-
250
mV
hyst
12.3.4 External Voltage Detector (EVD) Thresholds
Subject to general operating condition for V , f
, and T .
DD OSC
A
1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
V
1
0 VDF flag toggle threshold
V
1.35
IT+
(V rise)
DD
0
1 VDF flag toggle threshold
V
V
1.10
250
IT-
(V fall)
DD
EVD voltage threshold hysteresis
V
-V
IT+ IT-
mV
hyst
136/176
ST72321J, ST72324J/K
12.4 SUPPLY CURRENT CHARACTERISTICS
The following current consumption specified for the ST7 functional operating modes over temperature
range does not take into account the clock source current consumption. To get the total device consump-
tion, the two current values must be added (except for HALT mode for which the clock is stopped).
Symbol
∆I
Parameter
Conditions
Max
Unit
Supply current variation vs. temperature
Constant V and f
10
%
DD(∆Ta)
DD
CPU
12.4.1 RUN and SLOW Modes
1)
2)
Symbol
Parameter
Conditions
Typ
Max
Unit
f
f
f
f
=2MHz, f
=4MHz, f
=8MHz, f
=1MHz
=2MHz
=4MHz
1.5
2.3
3.7
6.5
2.5
3.5
5.0
8.0
OSC
OSC
OSC
OSC
CPU
CPU
CPU
3)
Supply current in RUN mode
(see Figure 67)
=16MHz, f
=8MHz
CPU
f
f
f
f
=2MHz, f
=4MHz, f
=8MHz, f
=62.5kHz
=125kHz
=250kHz
=500kHz
0.9
1.0
1.2
1.4
2.0
2.2
2.4
2.6
OSC
OSC
OSC
OSC
CPU
CPU
CPU
4)
Supply current in SLOW mode
(see Figure 68)
=16MHz, f
CPU
I
mA
DD
f
f
f
f
=2MHz, f
=4MHz, f
=8MHz, f
=1MHz
=2MHz
=4MHz
0.8
1.2
2.0
3.7
1.0
1.5
3.0
5.0
OSC
OSC
OSC
OSC
CPU
CPU
CPU
3)
Supply current in RUN mode
(see Figure 67)
=16MHz, f
=8MHz
CPU
f
f
f
f
=2MHz, f
=4MHz, f
=8MHz, f
=62.5kHz
=125kHz
=250kHz
0.35
0.4
0.5
0.6
0.6
0.7
0.8
1.0
OSC
OSC
OSC
OSC
CPU
CPU
CPU
4)
Supply current in SLOW mode
(see Figure 68)
=16MHz, f
=500kHz
CPU
Figure 67. Typical I in RUN vs. f
Figure 68. Typical I in SLOW vs. f
CPU
DD
CPU
DD
0.008
0.0025
1M Hz
1MHz
0.007
0.006
0.005
0.004
0.003
0.002
0.001
0
2M HZ
4M HZ
8M Hz
2MHZ
0.002
4MHZ
8MHz
0.0015
0.001
0.0005
0
2.5
3
3.5
4
4.5
5
5.5
6
2.5
3
3.5
4
4.5
5
5.5
6
VDD(V)
VDD(V)
Notes:
1. Typical data are based on T =25°C, V =5V (4.5V≤V ≤5.5V range) and V =3.3V (3V≤V ≤3.6V range).
A
DD
DD
DD
DD
2. Data based on characterization results, tested in production at V max. and f
max.
CPU
DD
3. CPU running with memory access, all I/O pins in input mode with a static value at V or V (no load), all peripherals
DD
SS
in reset state; clock input (OSC1) driven by external square wave, CSS and LVD disabled.
4. SLOW mode selected with f
SS
based on f
divided by 32. All I/O pins in input mode with a static value at V or
CPU
OSC DD
V
(no load), all peripherals in reset state; clock input (OSC1) driven by external square wave, CSS and LVD disabled.
137/176
ST72321J, ST72324J/K
SUPPLY CURRENT CHARACTERISTICS (Cont’d)
12.4.2 WAIT and SLOW WAIT Modes
1)
2)
Symbol
Parameter
Conditions
Typ
Max
Unit
f
f
f
f
=2MHz, f
=4MHz, f
=8MHz, f
=1MHz
=2MHz
=4MHz
1.9
2.3
3.0
4.7
2.7
3.2
4.0
5.8
OSC
OSC
OSC
OSC
CPU
CPU
CPU
3)
Supply current in WAIT mode
(see Figure 69)
=16MHz, f
=8MHz
CPU
f
f
f
f
=2MHz, f
=4MHz, f
=8MHz, f
=62.5kHz
=125kHz
=250kHz
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
OSC
OSC
OSC
OSC
CPU
CPU
CPU
4)
Supply current in SLOW WAIT mode
(see Figure 70)
=16MHz, f
=500kHz
CPU
I
mA
DD
f
f
f
f
=2MHz, f
=4MHz, f
=8MHz, f
=1MHz
=2MHz
=4MHz
0.7
0.9
1.4
2.4
1.4
1.7
2.2
3.3
OSC
OSC
OSC
OSC
CPU
CPU
CPU
3)
Supply current in WAIT mode
(see Figure 69)
=16MHz, f
=8MHz
CPU
f
f
f
f
=2MHz, f
=4MHz, f
=8MHz, f
=62.5kHz
=125kHz
=250kHz
=500kHz
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
OSC
OSC
OSC
OSC
CPU
CPU
CPU
4)
Supply current in SLOW WAIT mode
(see Figure 70)
=16MHz, f
CPU
Figure 69. Typical I in WAIT vs. f
Figure 70. Typical I in SLOW-WAIT vs. f
DD CPU
DD
CPU
0.006
1MHz
0.005
0.004
0.003
0.002
0.001
0
2MHZ
4MHZ
8MHz
2 .5
3
3.5
4
4.5
5
5.5
6
VDD(V)
Notes:
1. Typical data are based on T =25°C, V =5V (4.5V≤V ≤5.5V range) and V =3.3V (3V≤V ≤3.6V range).
A
DD
DD
DD
DD
2. Data based on characterization results, tested in production at V max. and f
max.
CPU
DD
3. All I/O pins in input mode with a static value at V or V (no load), all peripherals in reset state; clock input (OSC1)
DD
SS
driven by external square wave, CSS and LVD disabled.
4. SLOW-WAIT mode selected with f
based on f
divided by 32. All I/O pins in input mode with a static value at
OSC
CPU
V
or V (no load), all peripherals in reset state; clock input (OSC1) driven by external square wave, CSS and LVD
DD
SS
disabled.
138/176
ST72321J, ST72324J/K
SUPPLY CURRENT CHARACTERISTICS (Cont’d)
12.4.3 HALT and ACTIVE-HALT Modes
1)
Symbol
Parameter
Conditions
-40°C≤T ≤+85°C
Typ
Max
10
Unit
A
V
V
=5.5V
=3.6V
0
DD
-40°C≤T ≤+125°C
50
A
2)
Supply current in HALT mode
I
-40°C≤T ≤+85°C
6
µA
DD
A
DD
-40°C≤T ≤+125°C
50
A
3)
Supply current in ACTIVE-HALT mode
50
150
12.4.4 Supply and Clock Managers
The previous current consumption specified for
the ST7 functional operating modes over tempera-
ture range does not take into account the clock
source current consumption. To get the total de-
vice consumption, the two current values must be
added (except for HALT mode).
1)
4)
Symbol
Parameter
Conditions
Typ
Max
Unit
Supply current of internal RC oscillator
see Section
12.5.4 on page
144
5)
Supply current of external RC oscillator
see Section
12.5.3 on page
142
I
DD(CK)
5) & 6)
µA
Supply current of resonator oscillator
Clock security system supply current
LVD supply current
150
100
350
150
I
HALT mode
DD(LVD)
Notes:
1. Typical data are based on T =25°C.
A
2. All I/O pins in input mode with a static value at V or V (no load), CSS and LVD disabled. Data based on charac-
DD
SS
CPU
terization results, tested in production at V
max. and f
max.
DD
3. Data based on design simulation and/or technology characteristics, not tested in production. All I/O pins in input mode
with a static value at V or V (no load); clock input (OSC1) driven by external square wave, LVD disabled.
DD
SS
4. Data based on characterization results, not tested in production.
5. Data based on characterization results done with the external components specified in Section 12.5.3 and Section
12.5.4, not tested in production.
6. As the oscillator is based on a current source, the consumption does not depend on the voltage.
139/176
ST72321J, ST72324J/K
SUPPLY CURRENT CHARACTERISTICS (Cont’d)
12.4.5 On-Chip Peripherals
Symbol
Parameter
Conditions
Typ
50
Unit
V
V
V
V
V
V
V
V
V
V
=3.3V
=5.0V
=5.0V
=5.0V
=3.3V
=5.0V
=3.3V
=5.0V
=3.3V
=5.0V
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
1)
I
16-bit Timer supply current
f
=8MHz
DD(TIM)
CPU
150
TBD
TBD
TBD
TBD
250
350
800
1100
I
I2C supply current
CAN supply current
f
f
=8MHz
=8MHz
DD(I2C)
CPU
I
I
DD(CAN)
CPU
I
ART PWM supply current
f
f
f
=8MHz
=8MHz
=4MHz
µA
DD(ART)
CPU
CPU
ADC
2)
I
SPI supply current
DD(SPI)
3)
ADC supply current when converting
DD(ADC)
Notes:
1. Data based on a differential I measurement between reset configuration (timer counter running at f
/4) and timer
CPU
DD
counter stopped (selecting external clock capability). Data valid for one timer.
2. Data based on a differential I measurement between reset configuration and a permanent SPI master communica-
DD
tion (data sent equal to 55h).
3. Data based on a differential I measurement between reset configuration and continuous A/D conversions.
DD
140/176
ST72321J, ST72324J/K
12.5 CLOCK AND TIMING CHARACTERISTICS
Subject to general operating conditions for V , f
, and T .
DD OSC
A
12.5.1 General Timings
1)
Symbol
Parameter
Conditions
Min
2
Typ
3
Max
12
Unit
tCPU
ns
t
Instruction cycle time
c(INST)
f
f
=8MHz
250
10
375
1500
22
CPU
2)
tCPU
µs
Interrupt reaction time
t
v(IT)
t
= ∆t
+ 10
=8MHz
1.25
2.75
v(IT)
c(INST)
CPU
12.5.2 External Clock Source
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
V
OSC1 input pin high level voltage
OSC1 input pin low level voltage
0.7xV
V
V
DD
OSC1H
DD
V
V
0.3xV
DD
OSC1L
SS
t
t
3)
w(OSC1H)
see Figure 71
OSC1 high or low time
15
w(OSC1L)
ns
t
t
3)
r(OSC1)
OSC1 rise or fall time
15
f(OSC1)
I
OSCx Input leakage current
V
≤V ≤V
DD
±1
µA
L
SS IN
Figure 71. Typical Application with an External Clock Source
90%
V
V
OSC1H
OSC1L
10%
t
t
w(OSC1H)
t
t
w(OSC1L)
f(OSC1)
r(OSC1)
OSC2
Not connected internally
f
OSC
EXTERNAL
CLOCK SOURCE
I
L
OSC1
ST72XXX
Notes:
1. Data based on typical application software.
2. Time measured between interrupt event and interrupt vector fetch. ∆tc(INST) is the number of tCPU cycles needed to finish
the current instruction execution.
3. Data based on design simulation and/or technology characteristics, not tested in production.
141/176
ST72321J, ST72324J/K
CLOCK AND TIMING CHARACTERISTICS (Cont’d)
12.5.3 Crystal and Ceramic Resonator Oscillators
The ST7 internal clock can be supplied with four
different Crystal/Ceramic resonator oscillators. All
the information given in this paragraph are based
on characterization results with specified typical
external components. In the application, the reso-
nator and the load capacitors have to be placed as
close as possible to the oscillator pins in order to
minimize output distortion and start-up stabiliza-
tion time. Refer to the crystal/ceramic resonator
manufacturer for more details (frequency, pack-
age, accuracy...).
Symbol
Parameter
Conditions
Min
Max
Unit
MHz
kΩ
LP: Low power oscillator
1
2
4
8
MP: Medium power oscillator
MS: Medium speed oscillator
HS: High speed oscillator
>2
>4
>8
1)
f
Oscillator Frequency
OSC
16
R
Feedback resistor
20
40
F
VLP oscillator TBD
TBD
56
46
26
21
Recommended load capacitance ver- R =200Ω
LP oscillator
MP oscillator
MS oscillator
HS oscillator
38
32
18
15
S
C
C
L1
L2
sus equivalent serial resistance of the R =200Ω
pF
S
crystal or ceramic resonator (R )
R =200Ω
S
S
R =100Ω
S
Symbol
Parameter
Conditions
Typ
Max
Unit
VLP oscillator
LP oscillator
MP oscillator
MS oscillator
HS oscillator
10
90
180
350
690
20
V
=5V
150
250
450
850
DD
i
OSC2 driving current
V =V
µA
2
IN
SS
Figure 72. Typical Application with a Crystal or Ceramic Resonator
WHEN RESONATOR WITH
INTEGRATEDCAPACITORS
i
2
f
OSC
C
L1
OSC1
OSC2
RESONATOR
R
F
C
L2
ST72XXX
Notes:
1. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small R value.
S
Refer to crystal/ceramic resonator manufacturer for more details.
142/176
ST72321J, ST72324J/K
CLOCK AND TIMING CHARACTERISTICS (Cont’d)
Typical Crystal or Ceramic Resonators
C
C
L2
t
L1
SU(osc)
2)
Oscil.
1)
[ms]
[pF] [pF]
22 22
22 22
Reference
Freq.
2MHz
4MHz
8MHz
16MHz
2MHz
4MHz
8MHz
16MHz
Characteristic
LP
MP
MS
HS
LP
S-200-30-30/50
SS3-400-30-30/30
SS3-800-30-30/30
SS3-1600-30-30/30
CSA2.00MG
∆f
∆f
∆f
∆f
∆f
∆f
∆f
∆f
=[±30ppm
=[±30ppm
=[±30ppm
=[±30ppm
,±30ppm ], Typ. R =200Ω
8
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
25°C
∆Ta
S
,±30ppm ], Typ. R =60Ω
6.5
25°C
∆Ta
S
,±30ppm ], Typ. R =25Ω
33 33 3.25
25°C
∆Ta
S
,±30ppm ], Typ. R =15Ω
33 33
22 22
22 22
33 33
33 33
1.3
4
25°C
∆Ta
S
=[±0.5%
=[±0.5%
=[±0.5%
=[±0.5%
,±0.3% ,±0.3%
,±x.x%
,±x.x%
,±x.x%
,±x.x%
]
]
]
]
tolerance
tolerance
tolerance
tolerance
∆Ta
aging
aging
aging
aging
correl
correl
correl
correl
MP
MS
HS
CSA4.00MG
,±0.3% ,±0.3%
2
∆Ta
CSA8.00MTZ
,±0.5% ,±0.3%
1
∆Ta
CSA16.00MXZ040
,±0.3% ,±0.3%
0.7
∆Ta
Notes:
1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
2. t
is the typical oscillator start-up time measured between V =2.8V and the fetch of the first instruction (with a
SU(OSC)
DD
quick V
ramp-up from 0 to 5V (<50µs).
DD
143/176
ST72321J, ST72324J/K
CLOCK CHARACTERISTICS (Cont’d)
12.5.4 RC Oscillators
The ST7 internal clock can be supplied with an RC
oscillator. This oscillator can be used with internal
or external components (selectable by option
byte).
Symbol
Parameter
Conditions
=50KΩ, C =20pF ±20%
Min
Typ
Max
Unit
1)
Internal RC oscillator frequency
R
4
IN
IN
R
R
R
=33KΩ,
=47KΩ,
=47KΩ,
C
C
C
=22pF ±5%
=22pF ±5%
=100pF ±5%
4.3
3.1
1.2
EX
EX
EX
EX
EX
EX
f
t
MHz
OSC
2)
External RC oscillator frequency
Internal RC Oscillator Start-up Time
3)
R
=50KΩ, C =20pF ±20%
60
IN
IN
R
R
R
=33KΩ,
=47KΩ,
=47KΩ,
C
C
C
=22pF ±5%
=22pF ±5%
=100pF ±5%
60
80
200
EX
EX
EX
EX
EX
EX
µs
SU(OSC)
3)
External RC Oscillator Start-up Time
4)
R
C
|i
Oscillator external resistor
10
100
470
320
KΩ
pF
EX
EX
5)
Oscillator external capacitor
15
6)
OSC1 = V or 1.5V
|
Capacitor load current
290
µA
SS
CEX
Figure 73. Typical Application with RC oscillator
ST72XXX
V
DD
INTERNAL RC
Current copy
C
IN
EXTERNAL RC
R
IN
+
-
V
f
REF
OSC
R
EX
OSC1
OSC2
C
i
EX
CEX
Voltage generator
C
EX discharge
Notes:
1. Data based on characterization results.
2. Guaranteed frequency range with the specified C and R ranges taking into account the device process variation.
EX
EX
Data based on design simulation.
3. Data based on characterization results done with V nominal at 5V, not tested in production.
DD
4. R must have a positive temperature coefficient (ppm/°C), carbon resistors should therefore not be used.
EX
5. Important: when no external C is applied, the capacitance to be considered is the global parasitic capacitance which
EX
is subject to high variation (package, application...). In this case, the RC oscillator frequency tuning has to be done by
trying out several resistor values.
6. i
is the current needed to load the C capacitor while OSC1 is forced to V or 1.5V (RC oscillation voltage range)
EX SS
CEX
144/176
ST72321J, ST72324J/K
CLOCK CHARACTERISTICS (Cont’d)
12.5.5 Clock Security System (CSS)
Symbol
Parameter
Conditions
32kHz~100kHz
Min
2
Typ
Max
4
Unit
MHz
kHz
1)
f
Safe Oscillator Frequency
3
SFOSC
13.5
0.44
845
1.65
115
3.3
7.4
1MHz~2MHz
Typical CSS
operating frequency range limits
(versus oscillator range option)
2MHz~4MHz with PLL off
4MHz~8MHz
∆f
CPU
MHz
2)
30
8MHz~16MHz or
2MHz~4MHz with PLL on
3.2
Note:
1. Data based on simulation results.
2. Data given only as information, to be characterized later on.
12.5.6 PLL Characteristics
Symbol
Parameter
Conditions
Typ
100
3
Max
150
5
Unit
µA
1)
I
f
t
PLL Consumption
PLL
1)
PLL input frequency range
MHz
kHz
%
OSC
w(JIT)
1)
PLL jitter period
60
1)
∆f
/f
PLL jitter
± 0.4
± 1
CPU CPU
Figure 74. PLL ∆f
/f
versus the time
CPU CPU
∆f
/f
CPU CPU
Max
0
t
Min
t
w(JIT)
Note:
1. Data based on characterization results, not tested in production.
145/176
ST72321J, ST72324J/K
12.6 MEMORY CHARACTERISTICS
12.6.1 RAM and Hardware Registers
Symbol
Parameter
Conditions
Min
Typ
Typ
Max
Unit
1)
V
Data retention mode
HALT mode (or RESET)
1.6
V
RM
12.6.2 FLASH Memory
DUAL VOLTAGE HDFLASH MEMORY
Symbol
Parameter
Conditions
read mode
Min
0
Max
8
Unit
MHz
V
f
Operating frequency
CPU
write / erase mode
1
8
2)
V
Programming voltage
Supply current
4.5V <= V <= 5.5V
11.4
12.6
3
PP
DD
RUN mode (f
Write / Erase
= 4MHz)
CPU
mA
I
0
1
DD
Power down mode / HALT
10
µA
Read
V
V
> V
<=V
200
±15
PP
DD
DD
I
VPP current
PP
PP
Write / Erase
= 8MHz
30
TBD
TBD
10
mA
t
Byte programming time
Sector erasing time
100
0.5
2
µs
PROG
f
CPU
t
sec
ERASE
Device erasing time
f
= 8MHz, T =25°C
3
CPU
A
t
t
Internal V stabilization time
10
µs
VPP
RET
PP
Data retention
T =55°C
20
years
cycles
A
N
Write erase cycles
T =25°C
100
RW
A
T
Programming or erasing tempera-
ture range
PROG
TBD
25
TBD
°C
T
ERASE
Notes:
1. Minimum V supply voltage without losing data stored in RAM (in HALT mode or under RESET) or in hardware reg-
DD
isters (only in HALT mode). Guaranted by construction, not tested in production.
2. V must be applied only during the programming or erasing operation and not permanently for reliability reasons.
PP
146/176
ST72321J, ST72324J/K
12.7 EMC CHARACTERISTICS
Susceptibility tests are performed on a sample ba-
sis during product characterization.
■ ESD: Electro-Static Discharge (positive and
negative) is applied on all pins of the device until
a functional disturbance occurs. This test
conforms with the IEC 1000-4-2 standard.
12.7.1 Functional EMS
(Electro Magnetic Susceptibility)
■ FTB: A Burst of Fast Transient voltage (positive
Based on a simple running application on the
product (toggling 2 LEDs through I/O ports), the
product is stressed by two electro magnetic events
until a failure occurs (indicated by the LEDs).
and negative) is applied to V and V through
DD
SS
a 100pF capacitor, until a functional disturbance
occurs. This test conforms with the IEC 1000-4-
4 standard.
A device reset allows normal operations to be re-
sumed.
1)
1)
Symbol
Parameter
Conditions
=5V, T =+25°C, f
conforms to IEC 1000-4-2
Neg
Pos
Unit
Voltage limits to be applied on any I/O pin
to induce a functional disturbance
V
=8MHz
OSC
DD
A
V
-1
1
FESD
kV
Fast transient voltage burst limits to be ap-
V
=5V, T =+25°C, f
=8MHz
OSC
DD
A
V
plied through 100pF on V and V pins
-1.5
1.5
FFTB
DD
DD
conforms to IEC 1000-4-4
to induce a functional disturbance
2)
Figure 75. EMC Recommended star network power supply connection
ST72XXX
10µF 0.1µF
V
V
DD
SS
ST7
DIGITAL NOISE
FILTERING
V
DD
POWER
SUPPLY
SOURCE
V
V
SSA
EXTERNAL
NOISE
FILTERING
AREF
0.1µF
12.7.2 Electro Magnetic Interference (EMI)
Based on a simple application running on the product (toggling 2 LEDs through the I/O ports), the product
is monitoredin terms of emission. This emission test is in line with the norm SAE J 1752/3 which specifies
the board and the loading of each pin.
Max vs. [f
/f
]
Unit
Monitored
Frequency Band
OSC CPU
Symbol
Parameter
Conditions
8/4MHz 16/8MHz
0.1MHz to 30MHz
30MHz to 130MHz
130MHz to 1GHz
SAE EMI Level
9
9
21
4
V
=5V, T =+25°C,
A
DD
15
-1
dBµV
S
Peak level
TQFP64 14x14 package
conform with SAE J 1752/3
EMI
1.5
2.0
-
Notes:
1. Data based on characterization results, not tested in production.
2. The suggested 10µF and 0.1µF decoupling capacitors on the power supply lines are proposed as a good price vs.EMC
performance trade-off. They have to be put as close as possible to the device power supply pins. Other EMC recommen-
dations are given in other sections (I/Os, RESET, OSCx pin characteristics).
147/176
ST72321J, ST72324J/K
EMC CHARACTERISTICS (Cont’d)
12.7.3 Absolute Electrical Sensitivity
Machine Model Test Sequence
Based on three different tests (ESD, LU and DLU)
using specific measurement methods, the product
is stressed in order to determine its performance in
terms of electrical sensitivity. For more details, re-
fer to the AN1181 ST7 application note.
– C is loaded through S1 by the HV pulse gener-
ator.
L
– S1 switches position from generator to ST7.
– A discharge from C to the ST7 occurs.
L
– S2 must be closed 10 to 100ms after the pulse
delivery period to ensure the ST7 is not left in
charge state. S2 must be opened at least 10ms
prior to the delivery of the next pulse.
12.7.3.1 Electro-Static Discharge (ESD)
Electro-Static Discharges (3 positive then 3 nega-
tive pulses separated by 1 second) are applied to
the pins of each sample according to each pin
combination. The sample size depends of the
number of supply pins of the device (3 parts*(n+1)
supply pin). Two models are usually simulated:
Human Body Model and Machine Model. This test
conforms to the JESD22-A114A/A115A standard.
See Figure 76 and the following test sequences.
– R (machine resistance), in series with S2, en-
sures a slow discharge of the ST7.
Human Body Model Test Sequence
– C is loaded through S1 by the HV pulse gener-
L
ator.
– S1 switches position from generator to R.
– Adischarge from C through R(body resistance)
L
to the ST7 occurs.
– S2 must be closed 10 to 100ms after the pulse
delivery period to ensure the ST7 is not left in
charge state. S2 must be opened at least 10ms
prior to the delivery of the next pulse.
Absolute Maximum Ratings
1)
Symbol
Ratings
Conditions
Maximum value
Unit
Electro-static discharge voltage
(Human Body Model)
T =+25°C
V
2000
A
ESD(HBM)
V
Electro-static discharge voltage
(Machine Model)
V
T =+25°C
TBD
ESD(MM)
A
Figure 76. Typical Equivalent ESD Circuits
S1
R=1500Ω
S1
HIGH VOLTAGE
PULSE
GENERATOR
HIGH VOLTAGE
PULSE
GENERATOR
ST7
ST7
C =100pF
S2
L
S2
C =200pF
L
HUMAN BODY MODEL
MACHINE MODEL
Notes:
1. Data based on characterization results, not tested in production.
148/176
ST72321J, ST72324J/K
EMC CHARACTERISTICS (Cont’d)
12.7.3.2 Static and Dynamic Latch-Up
■ DLU: Electro-Static Discharges (one positive
then one negative test) are applied to each pin
of 3 samples when the micro is running to
assess the latch-up performance in dynamic
mode. Power supplies are set to the typical
values, the oscillator is connected as near as
possible to the pins of the micro and the
component is put in reset mode. This test
conforms to the IEC1000-4-2 and SAEJ1752/3
standards and is described in Figure 77. For
more details, refer to the AN1181 ST7
application note.
■ LU: 3 complementary static tests are required
on 10parts to assess the latch-up performance.
A supply overvoltage (applied to each power
supply pin), a current injection (applied to each
input, output and configurable I/O pin) and a
power supply switch sequence are performed
on each sample. This test conforms to the EIA/
JESD 78 IC latch-up standard. For more details,
refer to the AN1181 ST7 application note.
Electrical Sensitivities
1)
Symbol
Parameter
Static latch-up class
Dynamic latch-up class
Conditions
Class
T =+25°C
A
A
A
A
LU
T =+85°C
A
T =+125°C
A
V
=5.5V, f
=4MHz, T =+25°C
DLU
A
DD
OSC
A
Figure 77. Simplified Diagram of the ESD Generator for DLU
R
2)
=50MΩ
R =330Ω
D
CH
DISCHARGE TIP
V
V
DD
SS
HV RELAY
C =150pF
S
ST7
ESD
DISCHARGE
RETURN CONNECTION
GENERATOR
Notes:
1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC spec-
ifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the
JEDEC criteria (international standard).
2. Schaffner NSG435 with a pointed test finger.
149/176
ST72321J, ST72324J/K
EMC CHARACTERISTICS (Cont’d)
12.7.4 ESD Pin Protection Strategy
Standard Pin Protection
To protect an integrated circuit against Electro-
Static Discharge the stress must be controlled to
prevent degradation or destruction of the circuit el-
ements. The stress generally affects the circuit el-
ements which are connected to the pads but can
also affect the internal devices when the supply
pads receive the stress. The elements to be pro-
tected must not receive excessive current, voltage
or heating within their structure.
To protect the output structure the following ele-
ments are added:
– A diode to V (3a) and a diode from V (3b)
DD
SS
– A protection device between V and V (4)
DD
SS
To protect the input structure the following ele-
ments are added:
– A resistor in series with the pad (1)
– A diode to V (2a) and a diode from V (2b)
DD
SS
– A protection device between V and V (4)
DD
SS
An ESD network combines the different input and
output ESD protections. This network works, by al-
lowing safe discharge paths for the pins subjected
to ESD stress. Two critical ESD stress cases are
presented in Figure 78 and Figure 79 for standard
pins and in Figure 80 and Figure 81 for true open
drain pins.
Figure 78. Positive Stress on a Standard Pad vs. V
SS
V
V
DD
DD
(3a)
(2a)
(1)
(4)
OUT
IN
Main path
(3b)
(2b)
Path to avoid
V
V
V
SS
SS
DD
Figure 79. Negative Stress on a Standard Pad vs. V
DD
V
DD
(3a)
(2a)
(1)
(4)
OUT
IN
Main path
(3b)
(2b)
V
V
SS
SS
150/176
ST72321J, ST72324J/K
EMC CHARACTERISTICS (Cont’d)
True Open Drain Pin Protection
Multisupply Configuration
When several types of ground (V , V
The centralized protection (4) is not involved in the
discharge of the ESD stresses applied to true
open drain pads due to the fact that a P-Buffer and
, ...) and
SSA
SS
power supply (V , V
, ...) are available for
AREF
DD
any reason (better noise immunity...), the structure
shown in Figure 82 is implemented to protect the
device against ESD.
diode to V
are not implemented. An additional
DD
local protection between the pad and V (5a &
SS
5b) is implemented to completely absorb the posi-
tive ESD discharge.
Figure 80. Positive Stress on a True Open Drain Pad vs. V
SS
V
V
DD
DD
Main path
(1)
Path to avoid
OUT
(4)
IN
(5a)
(5b)
(3b)
(2b)
V
V
V
SS
SS
Figure 81. Negative Stress on a True Open Drain Pad vs. V
DD
V
DD
DD
Main path
(1)
OUT
(4)
IN
(3b)
(3b)
(3b)
(2b)
V
V
SS
SS
Figure 82. Multisupply Configuration
V
DD
V
AREF
V
AREF
V
SS
BACK TO BACK DIODE
BETWEEN GROUNDS
V
SSA
V
SSA
151/176
ST72321J, ST72324J/K
12.8 I/O PORT PIN CHARACTERISTICS
12.8.1 General Characteristics
Subject to general operating conditions for V , f
, and T unless otherwise specified.
DD OSC
A
1)
Symbol
Parameter
Conditions
Min
Typ
400
400
Max
Unit
V
2)
V
Input low level voltage
0.3xVDD
IL
2)
V
Input high level voltage
CMOS ports
TTL ports
0.7xVDD
IH
3)
3)
V
Schmitt trigger voltage hysteresis
mV
V
hys
2)
0.8
V
Input low level voltage
IL
2)
2
V
Input high level voltage
IH
V
Schmitt trigger voltage hysteresis
Injected Curent on an IO pin
mV
hys
4)
I
± 4
INJ(PIN)
V
V
=5V
mA
Total injected current (sum of all I/O
and control pins)
DD
4)
ΣI
± 25
6)
INJ(PIN)
I
Input leakage current
SS≤V ≤V
DD
±1
L
IN
µA
5)
I
Static current consumption
Floating input mode
200
250
230
S
V
V
=5V
80
120
200
5
DD
6)
R
Weak pull-up equivalent resistor
V =V
SS
kΩ
pF
ns
PU
IN
=3.3V
170
DD
C
I/O pin capacitance
IO
7)
t
Output high to low level fall time
25
25
C =50pF
Between 10% and 90%
f(IO)out
r(IO)out
L
7)
t
Output low to high level rise time
8)
t
External interrupt pulse time
1
t
CPU
w(IT)in
Figure 83. Unused I/O Pin Applications
V
DD
ST72XXX
10kΩ
UNUSED I/O PORT
UNUSED I/O PORT
10kΩ
ST72XXX
Notes:
1. Unless otherwise specified, typical data are based on T =25°C and V =5V.
A
DD
2. Data based on characterization results, not tested in production.
3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
4. When the current limitation is not possible, the V maximum must be respected, otherwise refer to I
specifica-
IN
INJ(PIN)
tion. A positive injection is induced by V >V
while a negative injection is induced by V <V . Refer to Section 12.2.2
IN SS
IN
DD
on page 134 for more details.
5. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for
example or an external pull-up or pull-down resistor (see Figure 83). Data based on design simulation and/or technology
characteristics, not tested in production.
6. The R
pull-up equivalent resistor is based on a resistive transistor (corresponding I current characteristics de-
PU
PU
scribed in Figure 84). This data is based on characterization results, tested in production at V max.
DD
7. Data based on characterization results, not tested in production.
8. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external
interrupt source.
152/176
ST72321J, ST72324J/K
I/O PORT PIN CHARACTERISTICS (Cont’d)
Figure 84. Typical I vs. V with V =V
SS
PU
DD
IN
90
80
70
60
50
40
30
20
10
0
Ta=140°C
Ta=95°C
Ta=25°C
Ta=-45°C
2
2.5
3
3.5
4
4.5
5
5.5
6
Vdd(V)
153/176
ST72321J, ST72324J/K
I/O PORT PIN CHARACTERISTICS (Cont’d)
12.8.2 Output Driving Current
Subject to general operating conditions for V , f
, and T unless otherwise specified.
A
DD OSC
Symbol
Parameter
Conditions
Min
Max
Unit
Output low level voltage for a standard I/O pin
when 8 pins are sunk at same time
(see Figure 85 )
I
I
I
=+5mA
1.2
IO
IO
IO
=+2mA
0.5
1)
V
OL
=+20mA,T ≤85°C
1.3
1.5
A
Output low level voltage for a high sink I/O pin
when 4 pins are sunk at same time
(see Figure 86 and Figure 88)
T ≥85°C
A
V
I
I
=+8mA
0.6
IO
=-5mA, T ≤85°C
V
V
-1.4
-1.6
IO
A
Output high level voltage for an I/O pin
when 4 pins are sourced at same time
(see Figure 87 and Figure 90)
DD
DD
2)
T ≥85°C
V
A
OH
I
=-2mA
V
-0.7
IO
DD
Figure 85. Typical V at V =5V (standard)
Figure 87. Typical V -V at V =5V
DD OH DD
OL
DD
5.5
1.4
1.2
1
5
4.5
4
0.8
0.6
0.4
0.2
0
3.5
3
Vdd=5V 140°C min
Vdd=5v 95°C min
Vdd=5v 25°C min
Vdd=5v -45°C min
Ta=140°C ”
Ta=95°C
Ta=25°C
2.5
2
Ta=-45°C
-0.01 -0.008 -0.006 -0.004 -0.002
Iio (A)
0
0
0.005
0.01
0.015
Iio(A)
Figure 86. Typical V at V =5V (high-sink)
OL
DD
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
Ta= 140°C
Ta= 95°C
Ta= 25°C
Ta= -45°C
0
0.01
0.02
0.03
Iio(A)
Notes:
1. The I current sunk must always respect the absolute maximum rating specified in Section 12.2.2 and the sum of I
IO
IO
(I/O ports and control pins) must not exceed I
.
VSS
2. The I current sourced must always respect the absolute maximum rating specified in Section 12.2.2 and the sum of
IO
I
(I/O ports and control pins) must not exceed I
. True open drain I/O pins does not have V
.
IO
VDD
OH
154/176
ST72321J, ST72324J/K
I/O PORT PIN CHARACTERISTICS (Cont’d)
Figure 88. Typical V vs. V (standard)
OL
DD
1
0.45
0.4
Ta= -45°C
Ta= 25°C
Ta=-45°C
Ta=25°C
Ta=95°C
Ta=140°C
0.9
Ta= 95°C
0.8
0.7
0.35
Ta= 140°C
0.3
0.25
0.2
0.6
0.5
0.4
0.3
0.2
0.1
0
0.15
0.1
0.05
0
2
2.5
3
3.5
4
4.5
5
5.5
6
2
2.5
3
3.5
4
4.5
5
5.5
6
Vdd(V)
Vdd(V)
Figure 89. Typical V vs. V (high-sink)
OL
DD
1.6
1.4
1.2
1
0.6
Ta= 140°C
Ta=95°C
0.5
Ta=25°C
Ta=-45°C
0.4
0.3
0.2
0.8
0.6
Ta= 140°C
Ta=95°C
Ta=25°C
Ta=-45°C
0.4
0.2
0
0.1
0
2
2.5
3
3.5
4
4.5
5
5.5
6
2
2.5
3
3.5
4
4. 5
5
5.5
6
Vdd(V )
Vdd(V )
Figure 90. Typical V -V vs. V
DD OH
DD
5.5
6
5
4
3
2
1
0
Ta= -45°C
Ta= 25°C
Ta= 95°C
Ta= 140°C
5
4.5
4
3.5
3
Ta=-45°C
Ta=25°C
Ta=95°C
Ta=140°C
2.5
2
2
2.5
3
3.5
4
4.5
5
5.5
6
2
2.5
3
3.5
4
4.5
5
5.5
6
Vdd(V)
Vdd(V)
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ST72321J, ST72324J/K
12.9 CONTROL PIN CHARACTERISTICS
12.9.1 Asynchronous RESET Pin
Subject to general operating conditions for V , f
, and T unless otherwise specified.
DD OSC
A
1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
V
2)
V
Input low level voltage
0.3xVDD
IL
2)
V
Input high level voltage
0.7xVDD
IH
3)
V
Schmitt trigger voltage hysteresis
400
mV
V
hys
I
I
=+5mA
=+2mA
0.68
0.28
40
0.95
0.45
60
IO
4)
V
Output low level voltage
V
=5V
DD
OL
IO
V
V
=5V
20
80
DD
DD
5)
R
Weak pull-up equivalent resistor
Generated reset pulse duration
V =V
SS
kΩ
µs
ON
IN
=3.3V
100
120
External pin or
internal reset sources
t
30
w(RSTL)out
6)
t
External reset pulse hold time
20
µs
h(RSTL)in
7)
t
Filtered glitch duration
100
ns
g(RSTL)in
8)
Figure 91. Typical Application with RESET pin
ST72XXX
V
DD
V
V
DD
DD
INTERNAL
RESET CONTROL
R
ON
0.1µF
0.1µF
4.7kΩ
USER
EXTERNAL
RESET
RESET
8)
CIRCUIT
WATCHDOG RESET
LVD RESET
Notes:
1. Unless otherwise specified, typical data are based on T =25°C and V =5V.
A
DD
2. Data based on characterization results, not tested in production.
3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
4. The I current sunk must always respect the absolute maximum rating specified in Section 12.2.2 and the sum of I
IO
IO
(I/O ports and control pins) must not exceed I
.
VSS
5. The R
pull-up equivalent resistor is based on a resistive transistor.
ON
6. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on
RESET pin with a duration below t can be ignored.
h(RSTL)in
7. The reset network (the resistor and two capacitors) protects the device against parasitic resets, especially in a noisy
environments.
8. The output of the external reset circuit must have an open-drain output to drive theST7 reset pad. Otherwise the device
can be damaged when the ST7 generates an internal reset (LVD or watchdog).
156/176
ST72321J, ST72324J/K
CONTROL PIN CHARACTERISTICS (Cont’d)
12.9.2 V Pin
PP
Subject to general operating conditions for V , f
, and T unless otherwise specified.
DD OSC
A
Symbol
Parameter
Conditions
Min
Max
Unit
V
1)
V
Input low level voltage
V
0.2
IL
IH
L
SS
1)
V
I
Input high level voltage
Input leakage current
V
-0.1 12.6
DD
V
=V
2)
±1
µA
IN
SS
Figure 92. Two typical Applications with V Pin
PP
V
V
PP
PP
PROGRAMMING
TOOL
10kΩ
ST72XXX
ST72XXX
Notes:
1. Data based on design simulation and/or technology characteristics, not tested in production.
2. When the ICC mode is not required by the application V pin must be tied to V
.
SS
PP
157/176
ST72321J, ST72324J/K
12.10 TIMER PERIPHERAL CHARACTERISTICS
Subject to general operating conditions for V
,
Refer to I/O port characteristics for more details on
the input/output alternate function characteristics
(output compare, input capture, external clock,
PWM output...).
DD
f
, and T unless otherwise specified.
OSC
A
12.10.1 Watchdog Timer
Symbol
Parameter
Conditions
Min
12,288
1.54
Typ
Max
786,432
98.3
Unit
tCPU
ms
t
Watchdog time-out duration
w(WDG)
fCPU=8MHz
12.10.2 8-Bit PWM-ART Auto-Reload Timer
Symbol
Parameter
Conditions
Min
1
Typ
Max
Unit
t
CPU
t
PWM resolution time
res(PWM)
f
=8MHz
125
0
ns
CPU
f
ART external clock frequency
PWM repetition rate
f
/2
EXT
CPU
MHz
f
0
f
/2
PWM
CPU
Res
PWM resolution
8
bit
PWM
OS
V
PWM/DAC output step voltage
V
=5V, Res=8-bits
20
mV
DD
12.10.3 16-Bit Timer
Symbol
Parameter
Conditions
Min
1
Typ
Max
Unit
t
Input capture pulse time
t
t
w(ICAP)in
CPU
2
CPU
t
PWM resolution time
res(PWM)
f
=8MHz
250
0
ns
CPU
f
Timer external clock frequency
PWM repetition rate
f
/4
MHz
MHz
bit
EXT
CPU
f
0
f
/4
PWM
CPU
Res
PWM resolution
16
PWM
158/176
ST72321J, ST72324J/K
12.11 COMMUNICATION INTERFACE CHARACTERISTICS
12.11.1 SPI - Serial Peripheral Interface
Refer to I/O port characteristics for more details on
the input/output alternate function characteristics
(SS, SCK, MOSI, MISO).
Subject to general operating conditions for V
,
DD
f
, and T unless otherwise specified.
OSC
A
Symbol
Parameter
Conditions
Min
/128
0.0625
Max
Unit
Master
Slave
f
f
f
/4
CPU
2
CPU
f
=8MHz
=8MHz
f
CPU
SCK
SPI clock frequency
MHz
1/t
/2
c(SCK)
CPU
0
f
4
CPU
t
t
r(SCK)
f(SCK)
SPI clock rise and fall time
see I/O port pin description
t
SS setup time
SS hold time
Slave
Slave
120
120
su(SS)
t
h(SS)
t
t
Master
Slave
100
90
w(SCKH)
SCK high and low time
Data input setup time
Data input hold time
w(SCKL)
t
Master
Slave
100
100
su(MI)
t
su(SI)
ns
t
Master
Slave
100
100
h(MI)
t
h(SI)
t
Data output access time
Data output disable time
Data output valid time
Data output hold time
Data output valid time
Data output hold time
Slave
Slave
0
120
240
120
a(SO)
t
dis(SO)
t
v(SO)
Slave (after enable edge)
t
0
h(SO)
v(MO)
h(MO)
t
0.25
0.25
Master (before capture edge)
t
CPU
t
Figure 93. SPI Slave Timing Diagram with CPHA=0 3)
SS
INPUT
t
t
su(SS)
c(SCK)
t
h(SS)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
t
t
w(SCKH)
w(SCKL)
t
t
t
t
dis(SO)
a(SO)
v(SO)
h(SO)
t
t
r(SCK)
f(SCK)
see
note 2
MISO
OUTPUT
INPUT
see note 2
MSB OUT
BIT6 OUT
LSB OUT
t
t
h(SI)
su(SI)
MSB IN
BIT1 IN
LSB IN
MOSI
Notes:
1. Data based on design simulation and/or characterisation results, not tested in production.
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has
its alternate function capability released. In this case, the pin status depends on the I/O port configuration.
3. Measurement points are done at CMOS levels: 0.3xV
and 0.7xV
.
DD
DD
159/176
ST72321J, ST72324J/K
COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d)
Figure 94. SPI Slave Timing Diagram with CPHA=11)
SS
INPUT
t
t
su(SS)
c(SCK)
t
h(SS)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
t
t
w(SCKH)
w(SCKL)
t
t
dis(SO)
a(SO)
t
t
h(SO)
v(SO)
t
t
r(SCK)
f(SCK)
see
note 2
see
note 2
MISO
OUTPUT
HZ
MSB OUT
t
BIT6 OUT
LSB OUT
t
su(SI)
h(SI)
MSB IN
LSB IN
BIT1 IN
MOSI
INPUT
Figure 95. SPI Master Timing Diagram 1)
SS
INPUT
t
c(SCK)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
CPHA=1
CPOL=0
CPHA=1
CPOL=1
t
w(SCKH)
t
r(SCK)
t
w(SCKL)
t
f(SCK)
t
t
h(MI)
su(MI)
MISO
MOSI
INPUT
MSB IN
h(MO)
BIT6 IN
LSB IN
t
t
v(MO)
MSB OUT
LSB OUT
see note 2
BIT6 OUT
see note 2
OUTPUT
Notes:
1. Measurement points are done at CMOS levels: 0.3xV and 0.7xV
.
DD
DD
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has
its alternate function capability released. In this case, the pin status depends of the I/O port configuration.
160/176
ST72321J, ST72324J/K
COMMUNICATIONS INTERFACE CHARACTERISTICS (Cont’d)
12.11.2 SCI - Serial Communications Interface
Subject to general operating condition for V , f
DD O-
, and T unless otherwise specified.
SC
A
Refer to I/O port characteristics for more details on
the input/output alternate function characteristics
(RDI and TDO).
Conditions
Accuracy
Baud
Rate
Symbol
Parameter
Standard
Unit
Prescaler
f
CPU
vs. Standard
Conventional Mode
TR (or RR)=128, PR=13
TR (or RR)= 32, PR=13
TR (or RR)= 16, PR=13
TR (or RR)= 8, PR=13
TR (or RR)= 4, PR=13
TR (or RR)= 16, PR= 3
TR (or RR)= 2, PR=13
TR (or RR)= 1, PR=13
300
~300.48
1200 ~1201.92
2400 ~2403.84
4800 ~4807.69
9600 ~9615.38
10400 ~10416.67
19200 ~19230.77
38400 ~38461.54
~0.16%
f
f
Tx
Rx
Communication frequency 8MHz
Hz
Extended Mode
~0.79%
ETPR (or ERPR) = 35,
TR (or RR)= 1, PR=1
14400 ~14285.71
161/176
ST72321J, ST72324J/K
COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d)
2
12.11.3 I C - Inter IC Control Interface
Refer to I/O port characteristics for more details on
the input/output alternate function characteristics
Subject to general operating conditions for V
,
DD
2
(SDAI and SCLI). The ST7 I C interfacemeets the
f
, and T unless otherwise specified.
OSC
A
2
requirements of the Standard I C communication
protocol described in the following table.
2
2
Standard mode I C
Fast mode I C
Symbol
Parameter
Unit
1)
1)
1)
1)
Min
Max
Min
Max
t
SCL clock low time
SCL clock high time
SDA setup time
4.7
4.0
1.3
0.6
100
w(SCLL)
µs
t
w(SCLH)
t
250
su(SDA)
3)
2)
3)
t
SDA data hold time
0
0
900
h(SDA)
t
t
r(SDA)
ns
SDA and SCL rise time
SDA and SCL fall time
1000
300
20+0.1C
20+0.1C
300
300
b
b
r(SCL)
t
t
f(SDA)
f(SCL)
t
START condition hold time
4.0
4.7
4.0
4.7
0.6
0.6
0.6
1.3
h(STA)
µs
t
Repeated START condition setup time
STOP condition setup time
su(STA)
t
ns
ms
pF
su(STO)
t
STOP to START condition time (bus free)
Capacitive load for each bus line
w(STO:STA)
C
400
400
b
2
Figure 96. Typical Application with I C Bus and Timing Diagram 4)
V
V
DD
DD
4.7kΩ
4.7kΩ
100Ω
100Ω
SDAI
SCLI
2
I C BUS
ST72XXX
REPEATED START
START
t
t
su(STA)
w(STO:STA)
START
SDA
t
t
r(SDA)
f(SDA)
STOP
t
t
h(SDA)
su(SDA)
SCK
t
t
t
t
t
su(STO)
t
h(STA)
w(SCKH)
w(SCKL)
r(SCK)
f(SCK)
Notes:
2
1. Data based on standard I C protocol requirement, not tested in production.
2. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined
region of the falling edge of SCL.
3. The maximum hold time of the START condition has only to be met if the interface does not stretch the low period of
SCL signal.
4. Measurement points are done at CMOS levels: 0.3xV
and 0.7xV
.
DD
DD
162/176
ST72321J, ST72324J/K
12.12 10-BIT ADC CHARACTERISTICS
Subject to general operating conditions for V , f
, and T unless otherwise specified.
DD OSC
A
1)
Symbol
Parameter
ADC clock frequency
Conversion voltage range
External input resistor
Conditions
Min
Typ
Max
Unit
MHz
V
f
4
ADC
2)
V
V
V
AIN
SSA
AREF
3)
R
10
kΩ
AIN
C
t
Internal sample and hold capacitor
Stabilization time after ADC enable
Conversion time (Sample+Hold)
6
pF
ADC
4)
0
STAB
µs
7.25
f
=8MHz, f
=4MHz
ADC
CPU
t
- Sample capacitor loading time
- Hold conversion time
8
21
ADC
1/f
ADC
Figure 97. Typical Application with ADC
V
DD
V
T
0.6V
R
AIN
AINx
V
AIN
ADC
V
0.6V
T
C
~2pF
I
L
±1µA
IO
V
DD
V
AREF
0.1µF
V
SSA
ST72XXX
Notes:
1. Unless otherwise specified, typical data are based on T =25°C and V -V =5V. They are given only as design guide-
A
DD SS
lines and are not tested.
2. When V and V
pins are not available on the pinout, the ADC refer to V and V .
SS
AREF
SSA
DD
3. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10kΩ). Data
based on characterization results, not tested in production.
4. The stabilization time of the AD converter is masked by the first t
always valid.
. The first conversion after the enable is then
LOAD
163/176
ST72321J, ST72324J/K
10-BIT ADC CHARACTERISTICS (Cont’d)
ADC Accuracy
2)
3)
3)
V
f
=5.5V,
V
f
=5.0V,
V
f
=3.3V,
DD
DD
DD
Conditions
=1MHz
=8MHz
=8MHz
Symbol
Parameter
CPU
CPU
CPU
Min
Max
Min
Max
Min
Max
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
4
V
E
+0.5V≤V ≤V -0.5V
SS
IN
DD
1)
TBD
TBD
3.5
2
|E |
Total unadjusted error
software compensated
O
T
1)
TBD
TBD
2.5
0
TBD
TBD
E
E
Offset error
O
G
1)
Gain Error
1)
4.5
4.5
|E |
Differential linearity error
D
1)
|E |
Integral linearity error
L
Figure 98. ADC Accuracy Characteristics
Digital Result ADCDR
E
G
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line
1023
V
– V
1022
1021
DDA
SSA
1LSB
= ----------------------------------------
IDEAL
1024
(2)
E =Total Unadjusted Error: maximum deviation
T
E
between the actual and the ideal transfer curves.
T
(3)
7
6
5
4
3
2
1
E =Offset Error: deviation between the first actual
O
transition and the first ideal one.
(1)
E =Gain Error: deviation between the last ideal
G
transition and the last actual one.
E
O
E
L
E =Differential Linearity Error: maximum deviation
D
between actual steps and the ideal one.
E =Integral Linearity Error: maximum deviation
L
E
between any actual transition and the end point
correlation line.
D
1 LSB
IDEAL
V
(LSB
)
IDEAL
in
0
1
2
3
4
5
6
7
1021 1022 1023 1024
V
V
SSA
AREF
Notes:
1. ADC Accuracy vs. Negative Injection Current:
For I =0.8mA, the typical leakage induced inside the die is 1.6µA and the effect on the ADC accuracy is a loss of 4 LSB
INJ-
for each 10KΩ increase of the external analog source impedance. This effect on the ADC accuracy has been observed
under worst-case conditions for injection:
- negative injection
- injection to an Input with analog capability, adjacent to the enabled Analog Input
- at 5V V supply, and worst case temperature.
DD
2. Data based on characterization results with T =25°C.
A
3. Data based on characterization results over the whole temperature range, monitored in production.
164/176
ST72321J, ST72324J/K
13 PACKAGE CHARACTERISTICS
13.1 PACKAGE MECHANICAL DATA
Figure 99. 44-Pin Thin Quad Flat Package
0.10mm
.004
seating plane
mm
inches
Dim
Min Typ Max Min Typ Max
A
1.60
0.063
0.006
A1 0.05
0.15 0.002
A2 1.35 1.40 1.45 0.053 0.055 0.057
b
c
0.30 0.37 0.45 0.012 0.015 0.018
0.09
0.20 0.004
0.008
b
D
12.00
10.00
8.00
0.472
0.394
0.315
0.472
0.394
0.315
0.031
D1
D3
E
12.00
10.00
8.00
E1
E3
e
c
0.80
K
0° 3.5°
7°
L
0.45 0.60 0.75 0.018 0.024 0.030
1.00 0.039
Number of Pins
44
L1
L1
L
N
K
165/176
ST72321J, ST72324J/K
PACKAGE CHARACTERISTICS (Cont’d)
Figure 100. 42-Pin Shrink Plastic Dual In-Line Package, 600-mil Width
mm
Min Typ Max Min Typ Max
5.08 0.200
inches
Dim.
A
A1 0.51
A2 3.05 3.81 4.57 0.120 0.150 0.180
0.020
b
b2
C
0.46 0.56
1.02 1.14
0.018 0.022
0.040 0.045
0.23 0.25 0.38 0.009 0.010 0.015
36.58 36.83 37.08 1.440 1.450 1.460
D
E
15.24
16.00 0.600
0.630
E1 12.70 13.72 14.48 0.500 0.540 0.570
e
1.78
0.070
0.600
eA
15.24
eB
18.54
0.730
0.060
eC 0.00
1.52 0.000
PDIP42S
L
2.54 3.30 3.56 0.100 0.130 0.140
Number of Pins
N
42
Figure 101. 32-Pin Thin Quad Flat Package
0.10mm
.004
seating plane
mm
inches
Dim
Min Typ Max Min Typ Max
D
D1
D3
A
1.60
0.063
0.006
A
A2
A1 0.05
0.15 0.002
A1
A2 1.35 1.40 1.45 0.053 0.055 0.057
24
17
B
C
0.30 0.37 0.45 0.012 0.015 0.018
0.09 0.20 0.004 0.008
25
32
16
9
D
9.00
7.00
5.60
0.80
9.00
7.00
5.60
0.354
0.276
0.220
0.031
0.354
0.276
0.220
D1
D3
e
E
8
1
E1
E3
L
C
e
0.45 0.60 0.75 0.018 0.024 0.030
1.00 0.039
L1
K
K
0°
7°
Number of Pins
TQFP32
N
32
166/176
ST72321J, ST72324J/K
PACKAGE CHARACTERISTICS (Cont’d)
Figure 102. 32-Pin Shrink Plastic Dual In Line Package
mm
inches
Dim.
A
E
Min Typ Max Min Typ Max
3.56 3.76 5.08 0.140 0.148 0.200
See Lead Detail
A1 0.51
A2 3.05 3.56 4.57 0.120 0.140 0.180
0.36 0.46 0.58 0.014 0.018 0.023
b1 0.76 1.02 1.40 0.030 0.040 0.055
0.020
C
b
eA
b1
b
e
C
D
E
0.20 0.25 0.36 0.008 0.010 0.014
27.43 27.94 28.45 1.080 1.100 1.120
9.91 10.41 11.05 0.390 0.410 0.435
B
e
3
D
E1 7.62 8.89 9.40 0.300 0.350 0.370
A
2
N
e
eA
eB
L
1.78
0.070
0.400
A
L
10.16
E
1
A
12.70
0.500
1
2.54 3.05 3.81 0.100 0.120 0.150
e
Number of Pins
VR01725J
1
N/2
N
32
13.2 THERMAL CHARACTERISTICS
Symbol
Ratings
Value
Unit
Package thermal resistance (junction to ambient)
TQFP44 10x10
TBD
TBD
TBD
TBD
R
TQFP32 7x7
SDIP42 600mil
SDIP32 200mil
°C/W
thJA
1)
P
Power dissipation
Maximum junction temperature
500
150
mW
D
2)
T
°C
Jmax
Notes:
1. The power dissipation is obtained from the formula P =P +P
where P
is the chip internal power (I xV
)
D
INT
PORT
INT
DD DD
and P
is the port power dissipation determined by the user.
PORT
2. The average chip-junction temperature can be obtained from the formula T = T + P x RthJA.
J
A
D
167/176
ST72321J, ST72324J/K
13.3 SOLDERING AND GLUEABILITY INFORMATION
Recommended soldering information given only as design guidelines.
Figure 103. Recommended Wave Soldering Profile (with 37% Sn and 63% Pb)
250
COOLING PHASE
(ROOM TEMPERATURE)
5 sec
200
150
100
50
SOLDERING
PHASE
80°C
Temp. [°C]
PREHEATING
PHASE
Time [sec]
0
20
40
60
80
100
140
120
160
Figure 104. Recommended Reflow Soldering Oven Profile (MID JEDEC)
250
Tmax=220+/-5°C
for 25 sec
200
150
100
50
150 sec above 183°C
90 sec at 125°C
Temp. [°C]
ramp down natural
2°C/sec max
ramp up
2°C/sec for 50sec
Time [sec]
0
100
200
300
400
Recommended glue for SMD plastic packages dedicated to molding compound with silicone:
■ Heraeus: PD945, PD955
■ Loctite: 3615, 3298
168/176
ST72321J, ST72324J/K
14 ST72321J/K DEVICE CONFIGURATION AND ORDERING INFORMATION
Each device is available for production in user pro-
grammable versions (FLASH) as well as in factory
coded versions (ROM). FLASH devices are
shipped to customers with a default content (FFh),
while ROM factory coded parts contain the code
supplied by the customer. This implies that FLASH
devices have to be configured by the customer us-
ing the Option Bytes while the ROM devices are
factory-configured.
14.1 FLASH OPTION BYTES
STATIC OPTION BYTE 2
STATIC OPTION BYTE 1
15
8
7
0
OSCTYPE
OSCRANGE
WDG
VD
1
1
0
0
2
1
1
1
0
1
1
1
0
1
Default
1
1
1
1
1
1
1
1
1
The option bytes allows the hardware configura-
tion of the microcontroller to be selected. They
have no address in the memory map and can be
accessed only in programming mode (for example
using a standard ST7 programming tool). The de-
fault content of the FLASH is fixed to FFh. To pro-
gram directly the FLASH devices using ICP,
FLASH devices are shipped to customers with the
internal RC clock source. In masked ROM devic-
es, the option bytes are fixed in hardware by the
ROM code (see option list).
OPT13:12 = OSCTYPE[1:0] Oscillator Type
These option bits select the ST7 main clock
source type.
OSCTYPE
Clock Source
1
0
0
1
1
0
0
1
0
1
Resonator Oscillator
External RC Oscillator
Internal RC Oscillator
External Source
OPT15= PKG32P 32 Pin package selection
This option bit selects the 32 pin package.
OPT11:9 = OSCRANGE[2:0] Oscillator range
When the resonator oscillator type is selected,
these option bits select the resonator oscillator
current source. This selection corresponds to used
resonator frequency range. Otherwise, these bits
are used to select the normal operating frequency
range (see CSS option description).
Version
Selected Package
TQFP44 / SDIP42
TQFP32 / SDIP32
PKG
J
1
0
K
OPT14 = RSTC RESET clock cycle selection
This option bit selects the number of CPU cycles
applied during the RESET phase and when exiting
HALT mode. For resonator oscillators, it is advised
to select 4096 due to the long crystal stabilization
time.
0: Reset phase with 4096 CPU cycles
1: Reset phase with 256 CPU cycles
Note: when the CSS is enabled, the device starts
to count immediately thanks to the backup oscilla-
tor.
OSCRANGE
Typ. Freq. Range
2
1
0
0
0
0
1
x
0
0
1
1
0
x
0
1
0
1
VLP
LP
32~100kHz
1~2MHz
2~4MHz
4~8MHz
8~16MHz
MP
MS
HS
169/176
ST72321J, ST72324J/K
ST72321J/K DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d)
OPT13 = PLL OFF PLL activation
OSCRANGE Compared frequencies to
Typ. Freq.
Range
This option bit activates the PLL which allows mul-
tiplication by two of the main input clock frequency.
The PLL is guaranteed only with an input frequen-
cy between 2 and 4MHz.
decide to switch to the
backup oscillator
2
1
0
32~100kHz
1~2MHz
2~4MHz
4~8MHz
8~16MHz
1
0
0
0
0
x
0
0
1
1
x
0
1
0
1
f
f
/64
SFOSC
CPU
0: PLL x2 enabled
2 x f
f
CPU
1: PLL x2 disabled
CAUTION: the PLL can be enabled only if the
“OSC RANGE” (OPT11:9) bits are configured to
“MP - 2~4MHz”. Otherwise, the device functionali-
ty is not guaranteed.
CPU
f
SFOSC
f
/2
CPU
f
/4
CPU
Selected Low Voltage Detector
VD1
VD0
OPT7= WDG HALT Watchdog and HALT mode
This option bit determines if a RESET is generated
when entering HALT mode while the Watchdog is
active.
0: No Reset generation when entering Halt mode
1: Reset generation when entering Halt mode
LVD and AVD Off
1
1
0
0
1
0
1
0
Lowest Voltage Threshold (V ~3.5V)
DD
Medium Voltage Threshold (V ~4V)
DD
Highest Voltage Threshold (V ~5V)
DD
OPT0= FMP_R Flash memory read-out protection
This option indicates if the user flash memory is
protected against read-out piracy. This protection
is based on read and a write protection of the
memory in test modes and ICP mode. Erasing the
option bytes when the FMP_R option is selected
induce the whole user memory erasing first.
0: read-out protection disabled
OPT6= WDG SWHardware or software watchdog
This option bit selects the watchdog type.
0: Hardware (watchdog always enabled)
1: Software (watchdog to be enabled by software)
OPT5 = CSS Clock security system on/off
This option bit enables or disables the clock secu-
rity system function (CSS) which include the clock
filter and the backup safe oscillator.
1: read-out protection enabled
0: CSS enabled
1: CSS disabled
When enabled, the selected “OSC RANGE” is
used to determine which is the selected operating
frequency range to switch to the backup oscillator
when the frequency is out of range.
OPT4:3= VD[1:0] Voltage detection
These option bits enable the voltage detection
block (LVD, and AVD) with aselected threshold for
170/176
ST72321J, ST72324J/K
ST72321J/K DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d)
14.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE
Customer code is made up of the ROM contents
and the list of the selected options (if any). The
ROM contents are to be sent on diskette, or by
electronic means, with the S19 hexadecimal file
generated by the development tool. All unused
bytes must be set to FFh.
The selected options are communicated to
STMicroelectronics using the correctly completed
OPTION LIST appended.
The STMicroelectronics Sales Organization will be
pleased to provide detailed information on con-
tractual points.
Figure 105. ROM Factory Coded Device Types
TEMP.
PACKAGE RANGE
/ XXX
DEVICE
Code name (defined by STMicroelectronics)
1= standard 0 to +70 °C
5= industrial -10 to +85 °C
6= industrial -40 to +85 °C
7= automotive -40 to +105°C
3 = automotive -40 to +125 °C
T= Plastic Thin Quad Flat Pack
B= Plastic Dual in Line
M= Plastic Small Outline
ST72321J9, ST72321J7
ST72324J6, ST72324J4, ST72324J2
ST72324K6, ST72324K4, ST72324K2
Figure 106. FLASH User Programmable Device Types
TEMP.
PACKAGE RANGE
/
XXX
DEVICE
Code name (defined by STMicroelectronics)
1= standard 0 to +70 °C
5= industrial -10 to +85 °C
6= industrial -40 to +85 °C
7= automotive -40 to +105°C
3 = automotive -40 to +125 °C
T= Plastic Thin Quad Flat Pack
B= Plastic Dual in Line
M= Plastic Small Outline
ST72F321J9, ST72F321J7
ST72F324J6, ST72F324J4, ST72F324J2
ST72F324K6, ST72F324K4, ST72F324K2
171/176
ST72321J, ST72324J/K
ST72321J/K DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d)
MICROCONTROLLER OPTION LIST
Customer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact
Phone No . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
STMicroelectronics references
Device:
[ ] ST72321J9
[ ] ST72324J6
[ ] ST72324K6
[ ] ST72321J7
[ ] ST72324J4
[ ] ST72324K4
[ ] ST72324J2
[ ] ST72324K2
Package:
[ ] TQFP44 10x10
[ ] TQFP32 7x7
[ ] SDIP42 600mil
[ ] SDIP32 200mil
Conditioning:
[ ] Tube
[ ] Tape & Reel (not available for SDIP packages)
Temperature Range:
[ ] 0°C to + 70°C
[ ] - 10°C to + 85°C
[ ] - 40°C to + 85°C
[ ] - 40°C to + 105°C
[ ] - 40°C to + 125°C
Clock Source Selection:
[ ] Resonator:
[ ] VLP: V. Low power resonator (32 to 100KHz)
[ ] LP: Low power resonator (1 to 2 MHz)
[ ] MP: Medium power resonator (2 to 4 MHz)
[ ] MS: Medium speed resonator (4 to 8 MHz)
[ ] HS: High speed resonator (8 to 16 MHz)
[ ] Internal
[ ] RC Network:
[ ] External
[ ] External Clock
[ ] Disabled
PLL
[ ] Enabled
[ ] Enabled
Clock Security System:
[ ] Disabled
Watchdog Selection:
Halt when Watchdog on:
[ ] Software Activation
[ ] Reset
[ ] Hardware Activation
[ ] No reset
Readout Protection:
LVD Reset
[ ] Disabled
[ ] Enabled
[ ] Disabled
[ ]Enabled: [ ] Highest threshold
[ ] Medium threshold
[ ] Lowest threshold
Reset Delay
[ ] 256 Cycles
[ ] 4096 Cycles
Comments : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply Operating Range in the application: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Notes
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Date . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
172/176
ST72321J, ST72324J/K
DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d)
14.3 DEVELOPMENT TOOLS
STmicroelectronics offers a range of hardware
and software development tools for the ST7 micro-
controller family. Full details of tools available for
the ST7 from third party manufacturers can be ob-
tain from the STMicroelectronics Internet site:
➟ http//mcu.st.com.
Tools from these manufacturers include C compli-
ers, emulators and gang programmers.
STMicroelectronics Tools
Three types of development tool are offered by
ST, all of them connect to a PC via a parallel (LPT)
port: see Table 26 and Table 27 for more details.
Table 26. STMicroelectronics Tool Features
1)
In-Circuit Emulation
Programming Capability
Software Included
ST7 CD ROM with:
Yes. (Same features as
ST7 Development Kit
ST7 HDS2 Emulator
HDS2 emulator but without Yes (DIP packages only)
logic analyzer)
– ST7 Assembly toolchain
– STVD7 powerful Source Level
Debugger for Win 3.1, Win 9x
and NT
– C compiler demo versions
– ST Realizer for Win 3.1 and Win
95.
Yes, powerful emulation
features including trace/
logic analyzer
No
ST7 Programming Board No
Yes (All packages)
– Windows Programming Tools
for Win 3.1, Win 9x and NT
Table 27. Dedicated STMicroelectronics Development Tools
Supported Products
ST72321J, ST72F321J
ST72324J, ST72F324J
ST72324K, ST72F324K
ST7 Development Kit
ST7 HDS2 Emulator
ST7 Programming Board
ST7MDT20-EPB2/EU
ST7MDT20-EPB2/US
ST7MDT20-EPB2/UK
N/A
ST7MDT20-EMU2B
Note:
1. Flash Programming interface for FLASH devices.
173/176
ST72321J, ST72324J/K
14.4 ST7 APPLICATION NOTES
IDENTIFICATION
DESCRIPTION
PROGRAMMING AND TOOLS
AN985
AN986
EXECUTING CODE IN ST7 RAM
USING THE ST7 INDIRECT ADDRESSING MODE
AN987
ST7 IN-CIRCUIT PROGRAMMING
AN988
AN989
STARTING WITH ST7 ASSEMBLY TOOL CHAIN
STARTING WITH ST7 HIWARE C
AN1039
AN1064
AN1106
EXAMPLE DRIVERS
AN969
AN970
AN971
AN972
ST7 MATH UTILITY ROUTINES
WRITING OPTIMIZED HIWARE C LANGUAGE FOR ST7
TRANSLATING ASSEMBLY CODE FROM HC05 TO ST7
ST7 SCI COMMUNICATION BETWEEN THE ST7 AND A PC
ST7 SPI COMMUNICATION BETWEEN THE ST7 AND E PROM
ST7 I C COMMUNICATION BETWEEN THE ST7 AND E PROM
ST7 SOFTWARE SPI MASTER COMMUNICATION
AN973
AN974
AN976
AN979
SCI SOFTWARE COMMUNICATION WITH A PC USING ST72251 16-BIT TIMER
REAL TIME CLOCK WITH THE ST7 TIMER OUTPUT COMPARE
DRIVING A BUZZER USING THE ST7 PWM FUNCTION
DRIVING AN ANALOG KEYBOARD WITH THE ST7 ADC
ST7 KEYPAD DECODING TECHNIQUES, IMPLEMENTING WAKE-UP ON KEYSTROKE
USING THE ST7 USB MICROCONTROLLER
USING ST7 PWM SIGNAL TO GENERATE ANALOG OUTPUT (SINUSOID)
ST7 ROUTINE FOR I C SLAVE MODE MANAGEMENT
MULTIPLE INTERRUPT SOURCES MANAGEMENT FOR ST7 MCUS
ST7 SOFTWARE IMPLEMENTATION OF I C BUS MASTER
ST7 UART EMULATION SOFTWARE
MANAGING RECEPTION ERRORS WITH THE ST7 SCI PERIPHERAL
ST7 SOFTWARE LCD DRIVER
ST7 TIMER PWM DUTY CYCLE SWITCH FOR TRUE 0% or 100% DUTY CYCLE
DESCRIPTION OF THE ST72141 MOTOR CONTROL
ST72141 BLDC MOTOR CONTROL SOFTWARE AND FLOWCHART EXAMPLE
PWM MANAGEMENT FOR BLDC MOTOR DRIVES USING THE ST72141
BRUSHLESS DC MOTOR DRIVE WITH ST72141
AN980
AN1017
AN1041
AN1042
AN1044
AN1045
AN1046
AN1047
AN1048
AN1078
AN1082
AN1083
AN1129
AN1130
AN1148
AN1149
AN1180
AN1182
USING THE ST7263 FOR DESIGNING A USB MOUSE
HANDLING SUSPEND MODE ON A USB MOUSE
USING THE ST7263 KIT TO IMPLEMENT A USB GAME PAD
USING THE ST7 USB LOW-SPEED FIRMWARE
PRODUCT OPTIMIZATION
AN982
USING CERAMIC RESONATORS WITH THE ST7
AN1014
AN1070
AN1179
HOW TO MINIMIZE THE ST7 POWER CONSUMPTION
ST7 CHECKSUM SELFCHECKING CAPABILITY
PROGRAMMING ST7 FLASH MICROCONTROLLERS IN REMOTE ISP
PRODUCT EVALUATION
AN910
ST7 AND ST9 PERFORMANCE BENCHMARKING
AN990
ST7 BENEFITS VERSUS INDUSTRY STANDARD
ST7 / ST10U435 CAN-do SOLUTIONS FOR CAR MULTIPLEXING
BENCHMARK ST72 VS PC16
AN1086
AN1150
AN1151
PERFORMANCE COMPARISON BETWEEN ST72254 & PC16F8
14.5 TO GET MORE INFORMATION
To get the latest information on this product please use the ST web server: http://mcu.st.com/
174/176
ST72321J, ST72324J/K
15 SUMMARY OF CHANGES
Revision
Main Changes
Date
ST72F521/321/324 FLASH memory is now named HDFlash (High Density Flash).
Device summary updates: sale types and temperature ranges.
- 24K devices removed.
- SO34 Package removed.TQFP32 pinout modified (Figure 4 on page 9 and Table 1 on
page 10).
CAUTION added for WDGRF flag use when LVD is not activated (Section 6.4.5 on page 30).
CAUTION added when exiting Active-Halt mode and clearing OIE of MCCSR (Section 8.4.1
on page 41)
Electrical characteristics:
- V for open-drain IOs and V added in Absolute Maximum Rating (Section 12.2.1 on
IN
PP
page 134).
1.3
09-Feb-01
- Operating range updated for ROM and FLASH in Section 12.3.1 on page 135.
- Vt updated in Section 12.3.2 on page 136.
(POR)
- RAM and FLASH notes added in Section 12.6 on page 146.
- FLASH programming and erasing temperature range in Section 12.6.2 on page 146.
- EMC characteristics updated in Section 12.7 on page 147
- I functionnal data added for I/O port pins in Section 12.8 on page 152.
INJ
- IOs typical curves have been updated with preliminary caracterisation report in Section
12.8 on page 152.
- ADC convertion time and accuracy have been updated in Section 12.12 on page 163.
Default option byte value modified to Internal RC clock source (Section 14.1 on page 169).
New temperature range in device configuration (Section 14.2 on page 171).
175/176
ST72321J, ST72324J/K
Notes:
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of useof such information nor for any infringement of patents or other rights of third parties which may result from its use. No license isgranted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
2001 STMicroelectronics - All Rights Reserved.
Purchase of I2C Components by STMicroelectronics conveys a license under the Philips I2C Patent. Rights to use these components in an
I2C system is granted provided that the system conforms to the I2C Standard Specification as defined by Philips.
STMicroelectronics Group of Companies
Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain
Sweden - Switzerland - United Kingdom - U.S.A.
http://www.st.com
176/176
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STMICROELECTR
ST72321J9TC/XXX
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