ST7232AJ2BC_技术文档

ST7232A

8-BIT MICROCONTROLLER WITH 8K FLASH/ROM,

ADC, 4 TIMERS, SPI, SCI INTERFACE

■ Memories

– 8K dual voltage High Density Flash (HDFlash)

or ROM with read-out protection capability. In-

Application Programming and In-Circuit Pro-

gramming for HDFlash devices

– 384 bytes RAM

TQFP32

7 x 7

SDIP32

400mil

– HDFlash endurance: 100 cycles, data reten-

tion: 40 years at 85°C

■ Clock, Reset And Supply Management

– Clock sources: crystal/ceramic resonator os-

cillators and bypass for external clock

– PLL for 2x frequency multiplication

– Four Power Saving Modes: Halt, Active-Halt,

TQFP44

SDIP42

Wait and Slow

■ Interrupt Management

– Nested interrupt controller

– 14 interrupt vectors plus TRAP and RESET

– 6 external interrupt lines (on 4 vectors)

■ Up to 32 I/O Ports

■ 1 Analog peripheral (low current coupling)

– 10-bit ADC with up to 12 robust input ports

■ Instruction Set

– 8-bit Data Manipulation

– 63 Basic Instructions

– 17 main Addressing Modes

– 8 x 8 Unsigned Multiply Instruction

■ Development Tools

– 32/24 multifunctional bidirectional I/O lines

– 22/17 alternate function lines

– 12/10 high sink outputs

■ 4Timers

– Main Clock Controller with: Real time base,

Beep and Clock-out capabilities

– Full hardware/software development package

– In-Circuit Testing capability

– Configurable watchdog timer

– Two 16-bit Timers with: 2 input captures, 2

output compares, PWM and pulse generator

modes

■ 2 Communications Interfaces

– SPI synchronous serial interface

– SCI asynchronous serial interface

Device Summary

Features

ST72F32AK1 ST72F32AK2 ST72F32AJ1 ST72F32AJ2 ST7232AK1 ST7232AK2 ST7232AJ1 ST7232AJ2

Program memory

- bytes

FLASH 4K

FLASH 8K

FLASH 4K

FLASH 8K

ROM 4K

ROM 8K

ROM 4K

ROM 8K

RAM (stack) -

bytes

384 (256)

Operating Voltage

Temp. Range

3.8V to 5.5V

up to -40°C to +125°C

SDIP32 400mils /

TQFP32 7x7

SDIP42 600mils /

TQFP44 10x10

SDIP32 400mils /

TQFP32 7x7

SDIP42 600mils /

TQFP44 10x10

Package

Rev. 2

December 2005

1/157

1

Table of Contents

1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.3 STRUCTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.3.1 Read-out Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.4 ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.5 ICP (IN-CIRCUIT PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.6 IAP (IN-APPLICATION PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.7 RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.7.1 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

6.1 PHASE LOCKED LOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

6.2 MULTI-OSCILLATOR (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

6.3 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6.3.2 Asynchronous External RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6.3.3 External Power-On RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

6.3.4 Internal Watchdog RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

6.4 SYSTEM INTEGRITY MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.4.1 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

7.2 MASKING AND PROCESSING FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

7.3 INTERRUPTS AND LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.4 CONCURRENT & NESTED MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.5 INTERRUPT REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

7.6 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.6.1 I/O Port Interrupt Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.7 EXTERNAL INTERRUPT CONTROL REGISTER (EICR) . . . . . . . . . . . . . . . . . . . . . . . 35

8 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

8.2 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

8.3 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

8.4 ACTIVE-HALT AND HALT MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

157

8.4.1 ACTIVE-HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

8.4.2 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

2/157

2

Table of Contents

9 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

9.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

9.2.1 Input Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

9.2.2 Output Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

9.2.3 Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

9.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

9.4 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

9.5 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

9.5.1 I/O Port Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

10 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

10.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

10.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

10.1.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

10.1.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

10.1.4 How to Program the Watchdog Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

10.1.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

10.1.6 Hardware Watchdog Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

10.1.7 Using Halt Mode with the WDG (WDGHALT option) . . . . . . . . . . . . . . . . . . . . . . . 51

10.1.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

10.1.9 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

10.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK AND BEEPER (MCC/RTC) . 53

10.2.1 Programmable CPU Clock Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

10.2.2 Clock-out Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

10.2.3 Real Time Clock Timer (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

10.2.4 Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

10.2.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

10.2.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

10.2.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

10.3 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

10.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

10.3.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

10.3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

10.3.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

10.3.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

10.3.6 Summary of Timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

10.3.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

10.4 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

10.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

10.4.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

10.4.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

10.4.4 Clock Phase and Clock Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

10.4.5 Error Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

10.4.6 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

10.4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

157

10.4.8 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

10.5 SERIAL COMMUNICATIONS INTERFACE (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

3/157

1

Table of Contents

10.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

10.5.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

10.5.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

10.5.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

10.5.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

10.5.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

10.5.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

10.6 10-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

10.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

10.6.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

10.6.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

10.6.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

10.6.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

10.6.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

11 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

11.1 CPU ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

11.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

11.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

11.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

11.1.4 Indexed (No Offset, Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

11.1.5 Indirect (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

11.1.6 Indirect Indexed (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

11.1.7 Relative mode (Direct, Indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

11.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

12 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

12.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

12.1.1 Minimum and Maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

12.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

12.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

12.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

12.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

12.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

12.2.1 Voltage Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

12.2.2 Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

12.2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

12.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

12.3.1 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

12.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

12.4.1 CURRENT CONSUMPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

12.4.2 Supply and Clock Managers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

12.4.3 On-Chip Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

12.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

12.5.1 General Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

12.5.2 External Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

12.5.3 Crystal and Ceramic Resonator Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

157

12.5.4 PLL Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

12.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

4/157

1

Table of Contents

12.6.1 RAM and Hardware Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

12.6.2 FLASH Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

12.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

12.7.1 Functional EMS (Electro Magnetic Susceptibility) . . . . . . . . . . . . . . . . . . . . . . . . 125

12.7.2 Electro Magnetic Interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

12.7.3 Absolute Maximum Ratings (Electrical Sensitivity) . . . . . . . . . . . . . . . . . . . . . . . . 127

12.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

12.8.1 General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

12.8.2 Output Driving Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

12.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

12.9.1 Asynchronous RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

12.9.2 ICCSEL/VPP Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

12.10 TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

12.10.116-Bit Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

12.11 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 135

12.11.1SPI - Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

12.12 10-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

12.12.1Analog Power Supply and Reference Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

12.12.2General PCB Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

12.12.3ADC Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

13 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

13.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

13.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

13.3 SOLDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

14 ST7232A DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . 145

14.1 FLASH OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

14.2 ROM DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE 147

14.3 VERSION-SPECIFIC SALES CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

14.4 FLASH DEVICE ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

14.5 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

14.5.1 Socket and Emulator Adapter Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

14.6 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

15 KNOWN LIMITATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

15.1 ALL FLASH AND ROM DEVICES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

15.1.1 Safe Connection of OSC1/OSC2 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

15.1.2 Unexpected Reset Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

15.1.3 Clearing active interrupts outside interrupt routine . . . . . . . . . . . . . . . . . . . . . . . . 154

15.1.4 16-bit Timer PWM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

15.1.5 SCI Wrong Break duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

15.1.6 39-Pulse ICC Entry Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

15.2 ROM DEVICES ONLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

15.2.1 I/O Port A and F Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

15.2.2 External clock source with PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

157

16 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

5/157

1

Table of Contents

To obtain the most recent version of this datasheet,

please check at www.st.com>products>technical literature>datasheet.

Please also pay special attention to the Section “KNOWN LIMITATIONS” on page 154.

157

6/157

1

ST7232A

Under software control, all devices can be placed

in WAIT, SLOW, ACTIVE-HALT or HALT mode,

reducing power consumption when the application

is in idle or stand-by state.

1 INTRODUCTION

The ST72F32A and ST7232A devices are mem-

bers of the ST7 microcontroller family designed for

the 5V operating range.

The enhanced instruction set and addressing

modes of the ST7 offer both power and flexibility to

software developers, enabling the design of highly

efficient and compact application code. In addition

to standard 8-bit data management, all ST7 micro-

controllers feature true bit manipulation, 8x8 un-

signed multiplication and indirect addressing

modes.

The 32 and 44-pin devices are designed for mid-

range applications

All devices are based on a common industry-

standard 8-bit core, featuring an enhanced instruc-

tion set and are available with FLASH or ROM pro-

gram memory.

Figure 1. Device Block Diagram

8-BIT CORE

ALU

PROGRAM

MEMORY

(8K Bytes)

RESET

CONTROL

V

PP

RAM

(384 Bytes)

V

SS

DD

WATCHDOG

PORT A

OSC1

OSC2

OSC

MCC/RTC/BEEP

PORT F

TIMER A

BEEP

PORT B

PORT E

PORT C

TIMER B

SPI

SCI

PORT D

10-BIT ADC

V

AREF

V

SSA

7/157

3

ST7232A

2 PIN DESCRIPTION

Figure 2. 32-Pin SDIP Package Pinout

PB3

PB0

(HS) PB4

1

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

ei3

ei1

ei2

AIN0 / PD0

AIN1 / PD1

2

PE1 / RDI

PE0 / TDO

3

V

4

AREF

V

_2

V

5

DD

SSA

OSC1

OSC2

MCO / AIN8 / PF0

BEEP / (HS) PF1

6

7

OCMP1_A / AIN10 / PF4

V

_2

8

SS

ICAP1_A / (HS) PF6

EXTCLK_A / (HS) PF7

AIN12 / OCMP2_B / PC0

RESET

/ ICCSEL

9

V

10

11

12

13

14

15

16

PP

PA7 (HS)

AIN13 / OCMP1_B / PC1

ICAP2_B / (HS) PC2

ICAP1_B / (HS) PC3

ICCDATA/ MISO / PC4

AIN14 / MOSI / PC5

PA6 (HS)

PA4 (HS)

PA3 (HS)

ei0

PC7 / SS / AIN15

PC6 / SCK / ICCCLK

(HS) 20mA high sink capability

eix associated external interrupt vector

Figure 3. 32-Pin TQFP 7x7 Package Pinout

32 31 30 29 28 27 26 25

V

24

23

22

21

20

19

18

17

OSC1

OSC2

_2

1

2

3

4

5

6

7

8

AREF

ei3 ei2

V

SSA

MCO / AIN8 / PF0

BEEP / (HS) PF1

V

SS

ei1

RESET

/ ICCSEL

OCMP1_A / AIN10 / PF4

ICAP1_A / (HS) PF6

V

PP

PA7 (HS)

PA6 (HS)

PA4 (HS)

EXTCLK_A / (HS) PF7

AIN12 / OCMP2_B / PC0

ei0

9 10 11 12 13 14 15 16

(HS) 20mA high sink capability

eix associated external interrupt vector

8/157

ST7232A

PIN DESCRIPTION (Cont’d)

Figure 4. 42-Pin SDIP and 44-Pin TQFP Package Pinouts

44 43 42 41 40 39 38 37 36 35 34

RDI / PE1

V

1

33

32

31

30

29

28

27

26

25

24

23

SS_1

DD_1

PB0

PB1

2

PA3 (HS)

3

ei0

ei2

ei3

PB2

PC7 / SS / AIN15

4

PB3

PC6 / SCK / ICCCLK

PC5 / MOSI / AIN14

PC4 / MISO / ICCDATA

PC3 (HS) / ICAP1_B

PC2 (HS) / ICAP2_B

PC1 / OCMP1_B / AIN13

PC0 / OCMP2_B / AIN12

5

(HS) PB4

AIN0 / PD0

AIN1 / PD1

AIN2 / PD2

AIN3 / PD3

AIN4 / PD4

6

7

8

9

ei1

10

11

12 13 14 15 16 17 18 19 20 21 22

(HS) PB4

AIN0 / PD0

PB3

1

ei3

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

PB2

PB1

PB0

2

ei2

AIN1 / PD1

AIN2 / PD2

AIN3 / PD3

AIN4 / PD4

AIN5 / PD5

3

4

PE1 / RDI

PE0 / TDO

5

6

V

_2

7

DD

V

OSC1

OSC2

8

AREF

V

9

SSA

MCO / AIN8 / PF0

BEEP / (HS) PF1

V

_2

SS

10

11

12

13

14

15

16

17

18

19

20

21

RESET

V / ICCSEL

PP

ei1

(HS) PF2

AIN10 / OCMP1_A / PF4

ICAP1_A / (HS) PF6

EXTCLK_A / (HS) PF7

AIN12 / OCMP2_B / PC0

AIN13 / OCMP1_B / PC1

ICAP2_B/ (HS) PC2

ICAP1_B / (HS) PC3

ICCDATA / MISO / PC4

AIN14 / MOSI / PC5

PA7 (HS)

PA6 (HS)

PA5 (HS)

PA4 (HS)

V

SS_1

V

DD_1

PA3 (HS)

ei0

PC7 / SS / AIN15

PC6 / SCK / ICCCLK

(HS) 20mA high sink capability

eix associated external interrupt vector

9/157

1

ST7232A

PIN DESCRIPTION (Cont’d)

For external pin connection guidelines, refer to See “ELECTRICAL CHARACTERISTICS” on page 113.

Legend / Abbreviations for Table 1:

Type:

I = input, O = output, S = supply

A = Dedicated analog input

Input level:

In/Output level: C = CMOS 0.3V /0.7V

DD

C = CMOS 0.3V /0.7V with input trigger

T

DD

Output level:

HS = 20mA high sink (on N-buffer only)

Port and control configuration:

1)

– Input:

float = floating, wpu = weak pull-up, int = interrupt , ana = analog ports

2)

– Output:

OD = open drain , PP = push-pull

Refer to “I/O PORTS” on page 42 for more details on the software configuration of the I/O ports.

The RESET configuration of each pin is shown in bold. This configuration is valid as long as the device is

in reset state.

Table 1. Device Pin Description

Pin n°

Level

Port

Main

function

(after

Input

Output

Pin Name

Alternate Function

reset)

6

7

1

2

3

4

5

6

7

8

9

30

31

32

1

2

3

PB4 (HS)

I/O C

S

HS

X

ei3

X

Port B4

T

PD0/AIN0

PD1/AIN1

PD2/AIN2

PD3/AIN3

PD4/AIN4

PD5/AIN5

X

Port D0 ADC Analog Input 0

Port D1 ADC Analog Input 1

Port D2 ADC Analog Input 2

Port D3 ADC Analog Input 3

Port D4 ADC Analog Input 4

Port D5 ADC Analog Input 5

Analog Reference Voltage for ADC

Analog Ground Voltage

8

X

9

X

10

11

12

13

14

X

1

2

4

5

V

AREF

SSA

S

Main clock

out (f

ADC Analog

Input 8

15 10

3

4

6

7

PF0/MCO/AIN8

I/O C

X

ei1

X

Port F0

T

)

CPU

16 11

17 12

PF1 (HS)/BEEP

PF2 (HS)

I/O C

HS

X

Port F1 Beep signal output

Port F2

T

ei1

Timer A Out-

Port F4 put Com-

pare 1

PF4/OCMP1_A/

AIN10

ADC Analog

Input 10

18 13

5

8

I/O C

X

T

19 14

20 15

6

7

9

PF6 (HS)/ICAP1_A I/O C

HS

X

Port F6 Timer A Input Capture 1

T

PF7 (HS)/

I/O C

Timer A External Clock

10

Port F7

Source

EXTCLK_A

21

22

V

S

Digital Main Supply Voltage

Digital Ground Voltage

DD_0

SS_0

Timer B Out-

ADC Analog

PC0/OCMP2_B/

AIN12

23 16

8

11

I/O C

X

Port C0 put Com-

Input 12

T

pare 2

10/157

1

ST7232A

Pin n°

Level

Port

Main

function

(after

Input

Output

Pin Name

Alternate Function

reset)

Timer B Out-

Port C1 put Com-

pare 1

PC1/OCMP1_B/

AIN13

ADC Analog

Input 13

24 17

9

12

I/O C

X

T

25 18 10 13 PC2 (HS)/ICAP2_B I/O C

26 19 11 14 PC3 (HS)/ICAP1_B I/O C

HS

X

Port C2 Timer B Input Capture 2

Port C3 Timer B Input Capture 1

T

SPI Master

ICC Data In-

Port C4 In / Slave

put

PC4/MISO/ICCDA-

TA

27 20 12 15

I/O C

X

T

Out Data

SPI Master

ADC Analog

28 21 13 16 PC5/MOSI/AIN14

29 22 14 17 PC6/SCK/ICCCLK

I/O C

X

Port C5 Out / Slave

Input 14

T

In Data

SPI Serial

Clock

ICC Clock

Output

Port C6

SPI Slave

Port C7 Select (ac-

tive low)

ADC Analog

Input 15

30 23 15 18 PC7/SS/AIN15

31 24 16 19 PA3 (HS)

X

T

I/O C

S

HS

ei0

Port A3

32 25

33 26

V

Digital Main Supply Voltage

Digital Ground Voltage

Port A4

DD_1

SS_1

S

34 27 17 20 PA4 (HS)

35 28 PA5 (HS)

I/O C

HS

X

T

X

T

Port A5

1)

36 29 18 21 PA6 (HS)

37 30 19 22 PA7 (HS)

Port A6

1)

Port A7

Must be tied low. In the flash pro-

gramming mode, this pin acts as the

programming voltage input V . See

PP

38 31 20 23 V /ICCSEL

I

PP

Section 12.9.2 for more details. High

voltage must not be applied to ROM

devices.

39 32 21 24 RESET

I/O C

Top priority non maskable interrupt.

Digital Ground Voltage

T

40 33 22 25 V

S

SS_2

41 34 23 26 OSC2

O

Resonator oscillator inverter output

External clock input or Resonator os-

cillator inverter input

42 35 24 27 OSC1

I

43 36 25 28 V

S

Digital Main Supply Voltage

DD_2

44 37 26 29 PE0/TDO

I/O C

X

Port E0 SCI Transmit Data Out

Port E1 SCI Receive Data In

T

1

38 27 30 PE1/RDI

T

Caution: Negative cur-

2

39 28 31 PB0

I/O C

X

ei2

X

Port B0 rent injection not al-

T

5)

lowed on this pin

3

4

5

40

41

PB1

PB2

I/O C

X

ei2

X

Port B1

Port B2

Port B3

T

42 29 32 PB3

ei2

11/157

1

ST7232A

Notes:

1. In the interrupt input column, “eiX” defines the associated external interrupt vector. If the weak pull-up

column (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input,

else the configuration is floating interrupt input.

2. In the open drain output column, “T” defines a true open drain I/O (P-Buffer and protection diode to V

DD

are not implemented). See See “I/O PORTS” on page 42. and Section 12.8 I/O PORT PIN CHARACTER-

ISTICS for more details.

3. OSC1 and OSC2 pins connect a crystal/ceramic resonator, or an external source to the on-chip oscil-

lator; see Section 1 INTRODUCTION and Section 12.5 CLOCK AND TIMING CHARACTERISTICS for

more details.

4. On the chip, each I/O port has 8 pads. Pads that are not bonded to external pins are in input pull-up con-

figuration after reset. The configuration of these pads must be kept at reset state to avoid added current

consumption.

5. For details refer to Section 12.8.1 on page 128

12/157

1

ST7232A

3 REGISTER & MEMORY MAP

As shown in Figure 5, the MCU is capable of ad-

dressing 64K bytes of memories and I/O registers.

The highest address bytes contain the user reset

and interrupt vectors.

The available memory locations consist of 128

bytes of register locations, up to 384 bytes of RAM

and up to 8 Kbytes of user program memory. The

RAM space includes up to 256 bytes for the stack

from 0100h to 01FFh.

IMPORTANT: Memory locations marked as “Re-

served” must never be accessed. Accessing a re-

served area can have unpredictable effects on the

device.

Figure 5. Memory Map

0080h

Short Addressing

RAM (zero page)

0000h

HW Registers

(see Table 2)

00FFh

0100h

007Fh

0080h

256 Bytes Stack

Reserved

RAM

(384 Bytes)

01FFh

0200h

047Fh

0480h

027Fh

or 047Fh

Reserved

E000h

Program Memory

(4K or 8K)

8 KBytes

FFDFh

FFE0h

F000h

4 Kbytes

Interrupt & Reset Vectors

(see Table 8)

FFFFh

13/157

1

ST7232A

Table 2. Hardware Register Map

Register

Label

Reset

Status

Address

Block

Register Name

Remarks

1)

0000h

0001h

0002h

PADR

PADDR

PAOR

Port A Data Register

Port A Data Direction Register

Port A Option Register

00h

R/W

2)

Port A

Port B

00h

1)

0003h

0004h

0005h

PBDR

PBDDR

PBOR

Port B Data Register

Port B Data Direction Register

Port B Option Register

00h

R/W

2)

00h

1)

0006h

0007h

0008h

PCDR

PCDDR

PCOR

Port C Data Register

Port C Data Direction Register

Port C Option Register

00h

R/W

Port C

00h

1)

0009h

000Ah

000Bh

PDADR

PDDDR

PDOR

Port D Data Register

Port D Data Direction Register

Port D Option Register

00h

R/W

2)

Port D

Port E

Port F

00h

1)

000Ch

000Dh

000Eh

PEDR

PEDDR

PEOR

Port E Data Register

Port E Data Direction Register

Port E Option Register

00h

R/W

2)

00h

1)

000Fh

0010h

0011h

PFDR

PFDDR

PFOR

Port F Data Register

Port F Data Direction Register

Port F Option Register

00h

R/W

00h

0012h

to

Reserved Area (15 Bytes)

0020h

0021h

0022h

0023h

SPIDR

SPICR

SPICSR

SPI Data I/O Register

SPI Control Register

SPI Control/Status Register

xxh

0xh

00h

R/W

SPI

ITC

0024h

0025h

0026h

0027h

ISPR0

ISPR1

ISPR2

ISPR3

Interrupt Software Priority Register 0

Interrupt Software Priority Register 1

Interrupt Software Priority Register 2

Interrupt Software Priority Register 3

FFh

R/W

0028h

0029h

002Ah

002Bh

EICR

External Interrupt Control Register

Flash Control/Status Register

Watchdog Control Register

Reserved Area (1 Byte)

00h

7Fh

R/W

FLASH

FCSR

WATCHDOG

WDGCR

002Ch

002Dh

MCCSR

MCCBCR

Main Clock Control / Status Register

Main Clock Controller: Beep Control Register

00h

R/W

MCC

002Eh

to

Reserved Area (3 Bytes)

0030h

14/157

1

ST7232A

Register

Label

Reset

Status

Address

Block

Register Name

Remarks

0031h

0032h

0033h

0034h

0035h

0036h

0037h

0038h

0039h

003Ah

003Bh

003Ch

003Dh

003Eh

003Fh

TACR2

TACR1

TACSR

TAIC1HR

TAIC1LR

TAOC1HR

TAOC1LR

TACHR

Timer A Control Register 2

Timer A Control Register 1

Timer A Control/Status Register

Timer A Input Capture 1 High Register

Timer A Input Capture 1 Low Register

Timer A Output Compare 1 High Register

Timer A Output Compare 1 Low Register

Timer A Counter High Register

00h

R/W

xxxx x0xxb R/W

xxh

80h

00h

FFh

FCh

FFh

FCh

xxh

80h

00h

Read Only

R/W

TIMER A

Read Only

R/W

TACLR

Timer A Counter Low Register

TAACHR

TAACLR

TAIC2HR

TAIC2LR

TAOC2HR

TAOC2LR

Timer A Alternate Counter High Register

Timer A Alternate Counter Low Register

Timer A Input Capture 2 High Register

Timer A Input Capture 2 Low Register

Timer A Output Compare 2 High Register

Timer A Output Compare 2 Low Register

R/W

0040h

Reserved Area (1 Byte)

0041h

0042h

0043h

0044h

0045h

0046h

0047h

0048h

0049h

004Ah

004Bh

004Ch

004Dh

004Eh

004Fh

TBCR2

TBCR1

TBCSR

TBIC1HR

TBIC1LR

TBOC1HR

TBOC1LR

TBCHR

Timer B Control Register 2

Timer B Control Register 1

Timer B Control/Status Register

Timer B Input Capture 1 High Register

Timer B Input Capture 1 Low Register

Timer B Output Compare 1 High Register

Timer B Output Compare 1 Low Register

Timer B Counter High Register

00h

R/W

xxxx x0xxb R/W

xxh

80h

00h

FFh

FCh

FFh

FCh

xxh

80h

00h

Read Only

R/W

TIMER B

Read Only

R/W

TBCLR

Timer B Counter Low Register

TBACHR

TBACLR

TBIC2HR

TBIC2LR

TBOC2HR

TBOC2LR

Timer B Alternate Counter High Register

Timer B Alternate Counter Low Register

Timer B Input Capture 2 High Register

Timer B Input Capture 2 Low Register

Timer B Output Compare 2 High Register

Timer B Output Compare 2 Low Register

R/W

0050h

0051h

0052h

0053h

0054h

0055h

0056h

0057h

SCISR

SCIDR

SCIBRR

SCICR1

SCICR2

SCIERPR

SCI Status Register

SCI Data Register

SCI Baud Rate Register

SCI Control Register 1

SCI Control Register 2

SCI Extended Receive Prescaler Register

Reserved area

SCI Extended Transmit Prescaler Register

C0h

xxh

00h

Read Only

R/W

x000 0000h R/W

SCI

00h

---

R/W

SCIETPR

00h

R/W

0058h

to

Reserved Area (24 Bytes)

006Fh

0070h

0071h

0072h

ADCCSR

ADCDRH

ADCDRL

Control/Status Register

Data High Register

Data Low Register

00h

R/W

Read Only

ADC

0073h

007Fh

Reserved Area (13 Bytes)

Legend: x=undefined, R/W=read/write

15/157

1

ST7232A

Notes:

1. The contents of the I/O port DR registers are readable only in output configuration. In input configura-

tion, the values of the I/O pins are returned instead of the DR register contents.

2. The bits associated with unavailable pins must always keep their reset value.

16/157

1

ST7232A

4 FLASH PROGRAM MEMORY

4.1 Introduction

Depending on the overall Flash memory size in the

microcontroller device, there are up to three user

sectors (see Table 3). Each of these sectors can

be erased independently to avoid unnecessary

erasing of the whole Flash memory when only a

partial erasing is required.

The ST7 dual voltage High Density Flash

(HDFlash) is a non-volatile memory that can be

electrically erased as a single block or by individu-

al sectors and programmed on a Byte-by-Byte ba-

sis using an external V supply.

PP

The first two sectors have a fixed size of 4 Kbytes

(see Figure 6). They are mapped in the upper part

of the ST7 addressing space so the reset and in-

terrupt vectors are located in Sector 0 (F000h-

FFFFh).

The HDFlash devices can be programmed and

erased off-board (plugged in a programming tool)

or on-board using ICP (In-Circuit Programming) or

IAP (In-Application Programming).

The array matrix organisation allows each sector

to be erased and reprogrammed without affecting

other sectors.

Table 3. Sectors available in Flash devices

Flash Size (bytes)

Available Sectors

4K

8K

Sector 0

Sectors 0,1

Sectors 0,1, 2

4.2 Main Features

■ Three Flash programming modes:

> 8K

– Insertion in a programming tool. In this mode,

all sectors including option bytes can be pro-

grammed or erased.

4.3.1 Read-out Protection

– ICP (In-Circuit Programming). In this mode, all

sectors including option bytes can be pro-

grammed or erased without removing the de-

vice from the application board.

– IAP (In-Application Programming) In this

mode, all sectors except Sector 0, can be pro-

grammed or erased without removing the de-

vice from the application board and while the

application is running.

Read-out protection, when selected, provides a

protection against Program Memory content ex-

traction and against write access to Flash memo-

ry. Even if no protection can be considered as to-

tally unbreakable, the feature provides a very high

level of protection for a general purpose microcon-

troller.

In flash devices, this protection is removed by re-

programming the option. In this case, the entire

program memory is first automatically erased.

■ ICT (In-Circuit Testing) for downloading and

executing user application test patterns in RAM

■ Read-out protection

Read-out protection selection depends on the de-

vice type:

■ Register Access Security System (RASS) to

prevent accidental programming or erasing

– In Flash devices it is enabled and removed

through the FMP_R bit in the option byte.

4.3 Structure

– In ROM devices it is enabled by mask option

specified in the Option List.

The Flash memory is organised in sectors and can

be used for both code and data storage.

Figure 6. Memory Map and Sector Address

4K

8K

10K

16K

24K

32K

48K

60K

FLASH

MEMORY SIZE

1000h

3FFFh

7FFFh

9FFFh

BFFFh

D7FFh

DFFFh

EFFFh

FFFFh

SECTOR 2

52 Kbytes

2 Kbytes 8 Kbytes 16 Kbytes 24 Kbytes 40 Kbytes

4 Kbytes

SECTOR 1

SECTOR 0

17/157

1

ST7232A

FLASH PROGRAM MEMORY (Cont’d)

4.4 ICC Interface

– ICCCLK: ICC output serial clock pin

– ICCDATA: ICC input/output serial data pin

ICC needs a minimum of 4 and up to 6 pins to be

connected to the programming tool (see Figure 7).

These pins are:

– ICCSEL/V : programming voltage

PP

– OSC1(or OSCIN): main clock input for exter-

nal source (optional)

– RESET: device reset

– V : application board power supply (option-

DD

– V : device power supply ground

al, see Figure 7, Note 3)

SS

Figure 7. Typical ICC Interface

PROGRAMMING TOOL

ICC CONNECTOR

ICC Cable

APPLICATION BOARD

ICC CONNECTOR

(See Note 3)

(See caution)

HE10 CONNECTOR TYPE

9

7

5

6

3

1

2

10

8

4

APPLICATION

RESET SOURCE

See Note 2

10kΩ

APPLICATION

POWER SUPPLY

C

L2

L1

See Note 1

APPLICATION

I/O

ST7

Notes:

1. If the ICCCLK or ICCDATA pins are only used

classical RC network with R>1K or a reset man-

agement IC with open drain output and pull-up re-

sistor>1K, no additional components are needed.

In all cases the user must ensure that no external

reset is generated by the application during the

ICC session.

as outputs in the application, no signal isolation is

necessary. As soon as the Programming Tool is

plugged to the board, even if an ICC session is not

in progress, the ICCCLK and ICCDATA pins are

not available for the application. If they are used as

inputs by the application, isolation such as a serial

resistor has to implemented in case another de-

vice forces the signal. Refer to the Programming

Tool documentation for recommended resistor val-

ues.

3. The use of Pin 7 of the ICC connector depends

on the Programming Tool architecture. This pin

must be connected when using most ST Program-

ming Tools (it is used to monitor the application

power supply). Please refer to the Programming

Tool manual.

2. During the ICC session, the programming tool

must control the RESET pin. This can lead to con-

flicts between the programming tool and the appli-

cation reset circuit if it drives more than 5mA at

high level (push pull output or pull-up resistor<1K).

A schottky diode can be used to isolate the appli-

cation RESET circuit in this case. When using a

Caution: External clock ICC entry mode is man-

datory. Pin 9 must be connected to the OSC1 or

OSCIN pin of the ST7 and OSC2 must be ground-

ed.

18/157

1

ST7232A

FLASH PROGRAM MEMORY (Cont’d)

4.5 ICP (In-Circuit Programming)

possible to download code from the SPI, SCI, USB

or CAN interface and program it in the Flash. IAP

mode can be used to program any of the Flash

sectors except Sector 0, which is write/erase pro-

tected to allow recovery in case errors occur dur-

ing the programming operation.

To perform ICP the microcontroller must be

switched to ICC (In-Circuit Communication) mode

by an external controller or programming tool.

Depending on the ICP code downloaded in RAM,

Flash memory programming can be fully custom-

ized (number of bytes to program, program loca-

tions, or selection serial communication interface

for downloading).

4.7 Related Documentation

For details on Flash programming and ICC proto-

col, refer to the ST7 Flash Programming Refer-

ence Manual and to the ST7 ICC Protocol Refer-

ence Manual.

When using an STMicroelectronics or third-party

programming tool that supports ICP and the spe-

cific microcontroller device, the user needs only to

implement the ICP hardware interface on the ap-

plication board (see Figure 7). For more details on

the pin locations, refer to the device pinout de-

scription.

4.7.1 Register Description

FLASH CONTROL/STATUS REGISTER (FCSR)

Read/Write

Reset Value: 0000 0000 (00h)

4.6 IAP (In-Application Programming)

7

0

This mode uses a BootLoader program previously

stored in Sector 0 by the user (in ICP mode or by

plugging the device in a programming tool).

0

This mode is fully controlled by user software. This

allows it to be adapted to the user application, (us-

er-defined strategy for entering programming

mode, choice of communications protocol used to

fetch the data to be stored, etc.). For example, it is

This register is reserved for use by Programming

Tool software. It controls the Flash programming

and erasing operations.

Table 4. Flash Control/Status Register Address and Reset Value

Address

(Hex.)

Register

Label

7

6

5

4

3

2

1

0

FCSR

Reset Value

0029h

0

19/157

1

ST7232A

5 CENTRAL PROCESSING UNIT

5.1 INTRODUCTION

5.3 CPU REGISTERS

This CPU has a full 8-bit architecture and contains

six internal registers allowing efficient 8-bit data

manipulation.

The 6 CPU registers shown in Figure 8 are not

present in the memory mapping and are accessed

by specific instructions.

Accumulator (A)

5.2 MAIN FEATURES

The Accumulator is an 8-bit general purpose reg-

ister used to hold operands and the results of the

arithmetic and logic calculations and to manipulate

data.

■ Enable executing 63 basic instructions

■ Fast 8-bit by 8-bit multiply

■ 17 main addressing modes (with indirect

Index Registers (X and Y)

addressing mode)

These 8-bit registers are used to create effective

addresses or as temporary storage areas for data

manipulation. (The Cross-Assembler generates a

precede instruction (PRE) to indicate that the fol-

lowing instruction refers to the Y register.)

■ Two 8-bit index registers

■ 16-bit stack pointer

■ Low power HALT and WAIT modes

■ Priority maskable hardware interrupts

■ Non-maskable software/hardware interrupts

The Y register is not affected by the interrupt auto-

matic procedures.

Program Counter (PC)

The program counter is a 16-bit register containing

the address of the next instruction to be executed

by the CPU. It is made of two 8-bit registers PCL

(Program Counter Low which is the LSB) and PCH

(Program Counter High which is the MSB).

Figure 8. CPU Registers

7

0

ACCUMULATOR

RESET VALUE = XXh

7

0

X INDEX REGISTER

Y INDEX REGISTER

RESET VALUE = XXh

7

RESET VALUE = XXh

PCL

PCH

7

8

15

0

PROGRAM COUNTER

RESET VALUE = RESET VECTOR @ FFFEh-FFFFh

7

1

0

1

I1 H I0 N Z C

CONDITION CODE REGISTER

RESET VALUE =

8

1

X 1 X X X

0

15

7

STACK POINTER

RESET VALUE = STACK HIGHER ADDRESS

X = Undefined Value

20/157

1

ST7232A

CENTRAL PROCESSING UNIT (Cont’d)

Condition Code Register (CC)

Read/Write

Bit 1 = Z Zero.

This bit is set and cleared by hardware. This bit in-

dicates that the result of the last arithmetic, logical

or data manipulation is zero.

0: The result of the last operation is different from

zero.

1: The result of the last operation is zero.

Reset Value: 111x1xxx

7

0

1

I1

H

I0

N

Z

C

This bit is accessed by the JREQ and JRNE test

instructions.

The 8-bit Condition Code register contains the in-

terrupt masks and four flags representative of the

result of the instruction just executed. This register

can also be handled by the PUSH and POP in-

structions.

Bit 0 = C Carry/borrow.

This bit is set and cleared by hardware and soft-

ware. It indicates an overflow or an underflow has

occurred during the last arithmetic operation.

0: No overflow or underflow has occurred.

1: An overflow or underflow has occurred.

These bits can be individually tested and/or con-

trolled by specific instructions.

Arithmetic Management Bits

This bit is driven by the SCF and RCF instructions

and tested by the JRC and JRNC instructions. It is

also affected by the “bit test and branch”, shift and

rotate instructions.

Bit 4 = H Half carry.

This bit is set by hardware when a carry occurs be-

tween bits 3 and 4 of the ALU during an ADD or

ADC instructions. It is reset by hardware during

the same instructions.

Interrupt Management Bits

Bit 5,3 = I1, I0 Interrupt

0: No half carry has occurred.

1: A half carry has occurred.

The combination of the I1 and I0 bits gives the cur-

rent interrupt software priority.

This bit is tested using the JRH or JRNH instruc-

tion. The H bit is useful in BCD arithmetic subrou-

tines.

Interrupt Software Priority

Level 0 (main)

I1

1

0

1

I0

0

1

0

1

Level 1

Bit 2 = N Negative.

Level 2

This bit is set and cleared by hardware. It is repre-

sentative of the result sign of the last arithmetic,

logical or data manipulation. It’s a copy of the re-

Level 3 (= interrupt disable)

These two bits are set/cleared by hardware when

entering in interrupt. The loaded value is given by

the corresponding bits in the interrupt software pri-

ority registers (IxSPR). They can be also set/

cleared by software with the RIM, SIM, IRET,

HALT, WFI and PUSH/POP instructions.

th

sult 7 bit.

0: The result of the last operation is positive or null.

1: The result of the last operation is negative

(i.e. the most significant bit is a logic 1).

This bit is accessed by the JRMI and JRPL instruc-

tions.

See the interrupt management chapter for more

details.

21/157

1

ST7232A

CENTRAL PROCESSING UNIT (Cont’d)

Stack Pointer (SP)

Read/Write

The least significant byte of the Stack Pointer

(called S) can be directly accessed by a LD in-

struction.

Reset Value: 01 FFh

Note: When the lower limit is exceeded, the Stack

Pointer wraps around to the stack upper limit, with-

out indicating the stack overflow. The previously

stored information is then overwritten and there-

fore lost. The stack also wraps in case of an under-

flow.

15

8

1

0

7

0

The stack is used to save the return address dur-

ing a subroutine call and the CPU context during

an interrupt. The user may also directly manipulate

the stack by means of the PUSH and POP instruc-

tions. In the case of an interrupt, the PCL is stored

at the first location pointed to by the SP. Then the

other registers are stored in the next locations as

shown in Figure 9.

SP7

SP6

SP5

SP4

SP3

SP2

SP1

SP0

The Stack Pointer is a 16-bit register which is al-

ways pointing to the next free location in the stack.

It is then decremented after data has been pushed

onto the stack and incremented before data is

popped from the stack (see Figure 9).

– When an interrupt is received, the SP is decre-

mented and the context is pushed on the stack.

Since the stack is 256 bytes deep, the 8 most sig-

nificant bits are forced by hardware. Following an

MCU Reset, or after a Reset Stack Pointer instruc-

tion (RSP), the Stack Pointer contains its reset val-

ue (the SP7 to SP0 bits are set) which is the stack

higher address.

– On return from interrupt, the SP is incremented

and the context is popped from the stack.

A subroutine call occupies two locations and an in-

terrupt five locations in the stack area.

Figure 9. Stack Manipulation Example

CALL

Subroutine

RET

or RSP

PUSH Y

POP Y

IRET

Interrupt

Event

@ 0100h

SP

Y

CC

A

CC

A

CC

A

X

PCH

PCL

PCH

PCL

PCH

PCL

PCH

PCL

PCH

PCL

PCH

PCL

SP

PCH

PCL

PCH

PCL

SP

@ 01FFh

Stack Higher Address = 01FFh

0100h

Stack Lower Address =

22/157

1

ST7232A

6 SUPPLY, RESET AND CLOCK MANAGEMENT

The device includes a range of utility features for

securing the application in critical situations (for

example in case of a power brown-out), and re-

ducing the number of external components. An

overview is shown in Figure 11.

the frequency by two to obtain an f

of 4 to 8

OSC2

MHz. The PLL is enabled by option byte. If the PLL

is disabled, then f /2.

f

OSC2 = OSC

Caution: The PLL is not recommended for appli-

cations where timing accuracy is required.

For more details, refer to dedicated parametric

section.

Figure 10. PLL Block Diagram

Main features

■ Optional PLL for multiplying the frequency by 2

■ Reset Sequence Manager (RSM)

■ Multi-Oscillator Clock Management (MO)

– 5 Crystal/Ceramic resonator oscillators

PLL x 2

/ 2

0

1

f

OSC

f

OSC2

PLL OPTION BIT

6.1 PHASE LOCKED LOOP

If the clock frequency input to the PLL is in the

range 2 to 4 MHz, the PLL can be used to multiply

Figure 11. Clock, Reset and Supply Block Diagram

MAIN CLOCK

CONTROLLER

WITH REALTIME

MULTI-

f

OSC2

f

CPU

OSC2

OSC

PLL

(option)

OSCILLATOR

(MO)

OSC1

CLOCK (MCC/RTC)

SYSTEM INTEGRITY MANAGEMENT

RESET SEQUENCE

MANAGER

WATCHDOG

TIMER (WDG)

RESET

SICSR

WDG

RF

(RSM)

0

V

SS

DD

23/157

1

ST7232A

6.2 MULTI-OSCILLATOR (MO)

The main clock of the ST7 can be generated by

two different source types coming from the multi-

oscillator block:

■ an external source

■ 4 crystal or ceramic resonator oscillators

the frequency ranges). In this mode of the multi-

oscillator, the resonator and the load capacitors

have to be placed as close as possible to the oscil-

lator pins in order to minimize output distortion and

start-up stabilization time. The loading capaci-

tance values must be adjusted according to the

selected oscillator.

Each oscillator is optimized for a given frequency

range in terms of consumption and is selectable

through the option byte. The associated hardware

configurations are shown in Table 5. Refer to the

electrical characteristics section for more details.

These oscillators are not stopped during the

RESET phase to avoid losing time in the oscillator

start-up phase.

Table 5. ST7 Clock Sources

Hardware Configuration

Caution: The OSC1 and/or OSC2 pins must not

be left unconnected. For the purposes of Failure

Mode and Effect Analysis, it should be noted that if

the OSC1 and/or OSC2 pins are left unconnected,

the ST7 main oscillator may start and, in this con-

ST7

figuration, could generate an f

clock frequency

OSC

OSC1

OSC2

in excess of the allowed maximum (>16MHz.),

putting the ST7 in an unsafe/undefined state. The

product behaviour must therefore be considered

undefined when the OSC pins are left unconnect-

ed.

EXTERNAL

SOURCE

External Clock Source

In this external clock mode, a clock signal (square,

sinus or triangle) with ~50% duty cycle has to drive

the OSC1 pin while the OSC2 pin is tied to ground.

ST7

OSC1

OSC2

Crystal/Ceramic Oscillators

This family of oscillators has the advantage of pro-

ducing a very accurate rate on the main clock of

the ST7. The selection within a list of 4 oscillators

with different frequency ranges has to be done by

option byte in order to reduce consumption (refer

to Section 14.1 on page 145 for more details on

C

L2

L1

LOAD

CAPACITORS

24/157

1

ST7232A

6.3 RESET SEQUENCE MANAGER (RSM)

6.3.1 Introduction

The RESET vector fetch phase duration is 2 clock

cycles.

The reset sequence manager includes two RE-

SET sources as shown in Figure 13:

■ External RESET source pulse

■ Internal WATCHDOG RESET

Figure 12. RESET Sequence Phases

RESET

These sources act on the RESET pin and it is al-

ways kept low during the delay phase.

INTERNAL RESET

256 or 4096 CLOCK CYCLES

FETCH

VECTOR

Active Phase

The RESET service routine vector is fixed at ad-

dresses FFFEh-FFFFh in the ST7 memory map.

The basic RESET sequence consists of 3 phases

as shown in Figure 12:

■ Active Phase depending on the RESET source

■ 256 or 4096 CPU clock cycle delay (selected by

option byte)

■ RESET vector fetch

6.3.2 Asynchronous External RESET pin

The RESET pin is both an input and an open-drain

output with integrated R

weak pull-up resistor.

ON

This pull-up has no fixed value but varies in ac-

cordance with the input voltage. It can be pulled

low by external circuitry to reset the device. See

Electrical Characteristic section for more details.

The 256 or 4096 CPU clock cycle delay allows the

oscillator to stabilise and ensures that recovery

has taken place from the Reset state. The shorter

or longer clock cycle delay should be selected by

option byte to correspond to the stabilization time

of the external oscillator used in the application.

A RESET signal originating from an external

source must have a duration of at least t

in

h(RSTL)in

order to be recognized (see Figure 14). This de-

tection is asynchronous and therefore the MCU

can enter reset state even in HALT mode.

Figure 13. Reset Block Diagram

V

DD

R

ON

INTERNAL

RESET

Filter

RESET

PULSE

WATCHDOG RESET

GENERATOR

25/157

1

ST7232A

RESET SEQUENCE MANAGER (Cont’d)

The RESET pin is an asynchronous signal which

plays a major role in EMS performance. In a noisy

environment, it is recommended to follow the

guidelines mentioned in the electrical characteris-

tics section.

A proper reset signal for a slow rising V supply

can generally be provided by an external RC net-

work connected to the RESET pin.

DD

6.3.4 Internal Watchdog RESET

The RESET sequence generated by a internal

Watchdog counter overflow is shown in Figure 14.

6.3.3 External Power-On RESET

To start up the microcontroller correctly, the user

must ensure by means of an external reset circuit

Starting from the Watchdog counter underflow, the

device RESET pin acts as an output that is pulled

that the reset signal is held low until V

the minimum level specified for the selected f

frequency.

is over

DD

low during at least t

.

w(RSTL)out

OSC

Figure 14. RESET Sequences

EXTERNAL

RESET

WATCHDOG

RESET

RUN

ACTIVE

PHASE

t

w(RSTL)out

t

h(RSTL)in

EXTERNAL

RESET

SOURCE

RESET PIN

WATCHDOG

RESET

WATCHDOG UNDERFLOW

INTERNAL RESET (256 or 4096 T_CPU

VECTOR FETCH

)

26/157

1

ST7232A

6.4 SYSTEM INTEGRITY MANAGEMENT

6.4.1 Register Description

SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR)

Read/Write

Reset Value: 0000 000x (00h)

Bit 0 = WDGRF Watchdog reset flag

This bit indicates that the last Reset was generat-

ed by the Watchdog peripheral. It is set by hard-

ware (watchdog reset) and cleared by software

(writing zero).

7

0

WDG

RF

0

Bits 7:1 = Reserved, must be kept cleared.

27/157

1

ST7232A

7 INTERRUPTS

7.1 INTRODUCTION

When an interrupt request has to be serviced:

– Normal processing is suspended at the end of

the current instruction execution.

– The PC, X, A and CC registers are saved onto

the stack.

– I1 and I0 bits of CC register are set according to

the corresponding values in the ISPRx registers

of the serviced interrupt vector.

– The PC is then loaded with the interrupt vector of

the interrupt to service and the first instruction of

the interrupt service routine is fetched (refer to

“Interrupt Mapping” table for vector addresses).

The ST7 enhanced interrupt management pro-

vides the following features:

■ Hardware interrupts

■ Software interrupt (TRAP)

■ Nested or concurrent interrupt management

with flexible interrupt priority and level

management:

– Up to 4 software programmable nesting levels

– Up to 16 interrupt vectors fixed by hardware

– 2 non maskable events: RESET, TRAP

This interrupt management is based on:

The interrupt service routine should end with the

IRET instruction which causes the contents of the

saved registers to be recovered from the stack.

– Bit 5 and bit 3 of the CPU CC register (I1:0),

– Interrupt software priority registers (ISPRx),

– Fixed interrupt vector addresses located at the

high addresses of the memory map (FFE0h to

FFFFh) sorted by hardware priority order.

Note: As a consequence of the IRET instruction,

the I1 and I0 bits will be restored from the stack

and the program in the previous level will resume.

This enhanced interrupt controller guarantees full

upward compatibility with the standard (not nest-

ed) ST7 interrupt controller.

Table 6. Interrupt Software Priority Levels

Interrupt software priority Level

I1

1

I0

0

Level 0 (main)

Level 1

Low

7.2 MASKING AND PROCESSING FLOW

0

1

Level 2

0

The interrupt masking is managed by the I1 and I0

bits of the CC register and the ISPRx registers

which give the interrupt software priority level of

each interrupt vector (see Table 6). The process-

ing flow is shown in Figure 15

Level 3 (= interrupt disable)

High

1

Figure 15. Interrupt Processing Flowchart

PENDING

INTERRUPT

Y

RESET

TRAP

N

Interrupt has the same or a

lower software priority

than current one

N

I1:0

FETCH NEXT

INSTRUCTION

THE INTERRUPT

STAYS PENDING

Y

“IRET”

N

RESTORE PC, X, A, CC

FROM STACK

EXECUTE

INSTRUCTION

STACK PC, X, A, CC

LOAD I1:0 FROM INTERRUPT SW REG.

LOAD PC FROM INTERRUPT VECTOR

28/157

1

ST7232A

INTERRUPTS (Cont’d)

Servicing Pending Interrupts

vector is loaded in the PC register and the I1 and

I0 bits of the CC are set to disable interrupts (level

3). These sources allow the processor to exit

HALT mode.

As several interrupts can be pending at the same

time, the interrupt to be taken into account is deter-

mined by the following two-step process:

■ TRAP (Non Maskable Software Interrupt)

– the highest software priority interrupt is serviced,

This software interrupt is serviced when the TRAP

instruction is executed. It will be serviced accord-

ing to the flowchart in Figure 15.

– if several interrupts have the same software pri-

ority then the interrupt with the highest hardware

priority is serviced first.

■ RESET

Figure 16 describes this decision process.

The RESET source has the highest priority in the

ST7. This means that the first current routine has

the highest software priority (level 3) and the high-

est hardware priority.

Figure 16. Priority Decision Process

PENDING

INTERRUPTS

See the RESET chapter for more details.

Maskable Sources

Maskable interrupt vector sources can be serviced

if the corresponding interrupt is enabled and if its

own interrupt software priority (in ISPRx registers)

is higher than the one currently being serviced (I1

and I0 in CC register). If any of these two condi-

tions is false, the interrupt is latched and thus re-

mains pending.

Different

Same

SOFTWARE

PRIORITY

HIGHEST SOFTWARE

PRIORITY SERVICED

■ External Interrupts

HIGHEST HARDWARE

PRIORITY SERVICED

External interrupts allow the processor to exit from

HALT low power mode. External interrupt sensitiv-

ity is software selectable through the External In-

terrupt Control register (EICR).

External interrupt triggered on edge will be latched

and the interrupt request automatically cleared

upon entering the interrupt service routine.

If several input pins of a group connected to the

same interrupt line are selected simultaneously,

these will be logically ORed.

When an interrupt request is not serviced immedi-

ately, it is latched and then processed when its

software priority combined with the hardware pri-

ority becomes the highest one.

Note 1: The hardware priority is exclusive while

the software one is not. This allows the previous

process to succeed with only one interrupt.

Note 2: RESET and TRAP can be considered as

having the highest software priority in the decision

process.

■ Peripheral Interrupts

Usually the peripheral interrupts cause the MCU to

exit from HALT mode except those mentioned in

the “Interrupt Mapping” table. A peripheral inter-

rupt occurs when a specific flag is set in the pe-

ripheral status registers and if the corresponding

enable bit is set in the peripheral control register.

The general sequence for clearing an interrupt is

based on an access to the status register followed

by a read or write to an associated register.

Note: The clearing sequence resets the internal

latch. A pending interrupt (i.e. waiting for being

serviced) will therefore be lost if the clear se-

quence is executed.

Different Interrupt Vector Sources

Two interrupt source types are managed by the

ST7 interrupt controller: the non-maskable type

(RESET,TRAP) and the maskable type (external

or from internal peripherals).

Non-Maskable Sources

These sources are processed regardless of the

state of the I1 and I0 bits of the CC register (see

Figure 15). After stacking the PC, X, A and CC

registers (except for RESET), the corresponding

29/157

1

ST7232A

INTERRUPTS (Cont’d)

7.3 INTERRUPTS AND LOW POWER MODES

7.4 CONCURRENT & NESTED MANAGEMENT

All interrupts allow the processor to exit the WAIT

low power mode. On the contrary, only external

and other specified interrupts allow the processor

to exit from the HALT modes (see column “Exit

from HALT” in “Interrupt Mapping” table). When

several pending interrupts are present while exit-

ing HALT mode, the first one serviced can only be

an interrupt with exit from HALT mode capability

and it is selected through the same decision proc-

ess shown in Figure 16.

The following Figure 17 and Figure 18 show two

different interrupt management modes. The first is

called concurrent mode and does not allow an in-

terrupt to be interrupted, unlike the nested mode in

Figure 18. The interrupt hardware priority is given

in this order from the lowest to the highest: MAIN,

IT4, IT3, IT2, IT1, IT0. The software priority is giv-

en for each interrupt.

Warning: A stack overflow may occur without no-

tifying the software of the failure.

Note: If an interrupt, that is not able to Exit from

HALT mode, is pending with the highest priority

when exiting HALT mode, this interrupt is serviced

after the first one serviced.

Figure 17. Concurrent Interrupt Management

SOFTWARE

PRIORITY

I1

I0

LEVEL

TRAP

3

1 1

IT0

3

IT1

3

IT2

3

IT3

3

RIM

IT4

3

MAIN

3/0

11 / 10

10

Figure 18. Nested Interrupt Management

SOFTWARE

PRIORITY

LEVEL

I1

I0

TRAP

3

1 1

0 0

0 1

1 1

IT0

3

IT1

IT2

2

IT2

1

IT3

3

RIM

IT4

3

MAIN

3/0

11 / 10

10

30/157

1

ST7232A

INTERRUPTS (Cont’d)

7.5 INTERRUPT REGISTER DESCRIPTION

CPU CC REGISTER INTERRUPT BITS

Read/Write

INTERRUPT SOFTWARE PRIORITY REGIS-

TERS (ISPRX)

Reset Value: 111x 1010 (xAh)

Read/Write (bit 7:4 of ISPR3 are read only)

7

0

Reset Value: 1111 1111 (FFh)

7

0

1

I1

H

I0

N

Z

C

ISPR0

ISPR1

I1_3 I0_3 I1_2 I0_2 I1_1 I0_1 I1_0 I0_0

I1_7 I0_7 I1_6 I0_6 I1_5 I0_5 I1_4 I0_4

Bit 5, 3 = I1, I0 Software Interrupt Priority

These two bits indicate the current interrupt soft-

ware priority.

ISPR2 I1_11 I0_11 I1_10 I0_10 I1_9 I0_9 I1_8 I0_8

Interrupt Software Priority Level

I1

1

I0

0

Level 0 (main)

Level 1

Low

ISPR3

1

I1_13 I0_13 I1_12 I0_12

0

1

Level 2

0

These four registers contain the interrupt software

priority of each interrupt vector.

Level 3 (= interrupt disable*)

High

1

These two bits are set/cleared by hardware when

entering in interrupt. The loaded value is given by

the corresponding bits in the interrupt software pri-

ority registers (ISPRx).

– Each interrupt vector (except RESET and TRAP)

has corresponding bits in these registers where

its own software priority is stored. This corre-

spondance is shown in the following table.

They can be also set/cleared by software with the

RIM, SIM, HALT, WFI, IRET and PUSH/POP in-

structions (see “Interrupt Dedicated Instruction

Set” table).

Vector address

ISPRx bits

FFFBh-FFFAh

FFF9h-FFF8h

...

I1_0 and I0_0 bits*

I1_1 and I0_1 bits

...

*Note: TRAP and RESET events can interrupt a

level 3 program.

FFE1h-FFE0h

I1_13 and I0_13 bits

– Each I1_x and I0_x bit value in the ISPRx regis-

ters has the same meaning as the I1 and I0 bits

in the CC register.

– Level 0 can not be written (I1_x=1, I0_x=0). In

this case, the previously stored value is kept. (ex-

ample: previous=CFh, write=64h, result=44h)

The RESET, and TRAP vectors have no software

priorities. When one is serviced, the I1 and I0 bits

of the CC register are both set.

Caution: If the I1_x and I0_x bits are modified

while the interrupt x is executed the following be-

haviour has to be considered: If the interrupt x is

still pending (new interrupt or flag not cleared) and

the new software priority is higher than the previ-

ous one, the interrupt x is re-entered. Otherwise,

the software priority stays unchanged up to the

next interrupt request (after the IRET of the inter-

rupt x).

31/157

1

ST7232A

INTERRUPTS (Cont’d)

Table 7. Dedicated Interrupt Instruction Set

Instruction

New Description

Entering Halt mode

Function/Example

I1

H

I0

N

Z

C

HALT

IRET

JRM

1

0

Interrupt routine return

Jump if I1:0=11 (level 3)

Jump if I1:0<>11

Pop CC, A, X, PC

I1:0=11 ?

I1

H

I0

N

Z

C

JRNM

POP CC

RIM

I1:0<>11 ?

Pop CC from the Stack

Enable interrupt (level 0 set)

Disable interrupt (level 3 set)

Software trap

Mem => CC

I1

1

H

I0

0

1

0

N

Z

C

Load 10 in I1:0 of CC

Load 11 in I1:0 of CC

Software NMI

SIM

1

TRAP

WFI

1

Wait for interrupt

1

Note: During the execution of an interrupt routine, the HALT, POPCC, RIM, SIM and WFI instructions change the current

software priority up to the next IRET instruction or one of the previously mentioned instructions.

32/157

1

ST7232A

INTERRUPTS (Cont’d)

Table 8. Interrupt Mapping

Exit

from

ACTIVE

HALT

Exit

from

HALT

Source

Block

Register Priority

Address

Vector

N°

Description

Label

Order

RESET

TRAP

Reset

Software interrupt

Not used

yes

no

yes

no

FFFEh-FFFFh

FFFCh-FFFDh

FFFAh-FFFBh

N/A

0

1

Main clock controller time base inter-

rupt

MCC/RTC

MCCSR

N/A

yes

FFF8h-FFF9h

Higher

Priority

2

3

ei0

ei1

ei2

ei3

External interrupt port A3..0

External interrupt port F2..0

External interrupt port B3..0

External interrupt port B7..4

Not used

yes

no

FFF6h-FFF7h

FFF4h-FFF5h

FFF2h-FFF3h

FFF0h-FFF1h

FFEEh-FFEFh

FFECh-FFEDh

FFEAh-FFEBh

FFE8h-FFE9h

FFE6h-FFE7h

FFE4h-FFE5h

4

5

6

1)

7

SPI

SPI peripheral interrupts

TIMER A peripheral interrupts

TIMER B peripheral interrupts

SCI Peripheral interrupts

Not used

SPICSR

TASR

yes

no

8

TIMER A

TIMER B

SCI

no

9

TBSR

10

11

SCISR

Lower

Priority

Note 1: Unexpected exit from HALT may occur when SPI is in slave mode.

7.6 EXTERNAL INTERRUPTS

7.6.1 I/O Port Interrupt Sensitivity

■ Falling edge and low level

■ Rising edge and high level (only for ei0 and ei2)

The external interrupt sensitivity is controlled by

the IPA, IPB and ISxx bits of the EICR register

(Figure 19). This control allows to have up to 4 fully

independent external interrupt source sensitivities.

To guarantee correct functionality, the sensitivity

bits in the EICR register can be modified only

when the I1 and I0 bits of the CC register are both

set to 1 (level 3). This means that interrupts must

be disabled before changing sensitivity.

Each external interrupt source can be generated

on four (or five) different events on the pin:

■ Falling edge

■ Rising edge

■ Falling and rising edge

The pending interrupts are cleared by writing a dif-

ferent value in the ISx[1:0], IPA or IPB bits of the

EICR.

33/157

1

ST7232A

Figure 19. External Interrupt Control bits

EICR

IS20 IS21

PORT A3 INTERRUPT

PAOR.3

PADDR.3

ei0 INTERRUPT SOURCE

SENSITIVITY

CONTROL

PA3

IPA BIT

EICR

PORT F [2:0] INTERRUPTS

IS20

IS21

PFOR.2

PFDDR.2

SENSITIVITY

CONTROL

PF2

PF1

PF0

ei1 INTERRUPT SOURCE

PF2

EICR

PORT B [3:0] INTERRUPTS

IS10

IS11

PBOR.3

PBDDR.3

SENSITIVITY

CONTROL

PB3

PB2

PB1

PB0

PB3

ei2 INTERRUPT SOURCE

IPB BIT

EICR

PORT B [7:4] INTERRUPTS

IS10

IS11

PBOR.7

PBDDR.7

SENSITIVITY

CONTROL

PB7

PB6

PB5

PB4

ei3 INTERRUPT SOURCE

PB7

34/157

1

ST7232A

INTERRUPTS (Cont’d)

7.7 EXTERNAL INTERRUPT CONTROL REGISTER (EICR)

Read/Write

Bit 4:3 = IS2[1:0] ei0 and ei1 sensitivity

The interrupt sensitivity, defined using the IS2[1:0]

bits, is applied to the following external interrupts:

Reset Value: 0000 0000 (00h)

7

0

IS11 IS10 IPB IS21 IS20 IPA

0

- ei0 (port A3..0)

Bit 7:6 = IS1[1:0] ei2 and ei3 sensitivity

The interrupt sensitivity, defined using the IS1[1:0]

bits, is applied to the following external interrupts:

- ei2 (port B3..0)

External Interrupt Sensitivity

IS21 IS20

IPA bit =0

IPA bit =1

Falling edge &

low level

Rising edge

& high level

0

External Interrupt Sensitivity

IS11 IS10

0

1

0

1

Rising edge only

Falling edge only

Rising edge only

IPB bit =0

IPB bit =1

Falling edge &

low level

Rising edge

& high level

0

Rising and falling edge

0

1

0

1

Rising edge only

Falling edge only

Rising edge only

- ei1 (port F2..0)

Rising and falling edge

IS21 IS20

External Interrupt Sensitivity

- ei3 (port B4)

0

1

0

1

0

1

Falling edge & low level

Rising edge only

IS11 IS10

External Interrupt Sensitivity

0

1

0

1

0

1

Falling edge & low level

Rising edge only

Falling edge only

Rising and falling edge

Falling edge only

These 2 bits can be written only when I1 and I0 of

the CC register are both set to 1 (level 3).

Rising and falling edge

These 2 bits can be written only when I1 and I0 of

the CC register are both set to 1 (level 3).

Bit 2 = IPA Interrupt polarity for port A

This bit is used to invert the sensitivity of the port A

[3:0] external interrupts. It can be set and cleared

by software only when I1 and I0 of the CC register

are both set to 1 (level 3).

Bit 5 = IPB Interrupt polarity for port B

This bit is used to invert the sensitivity of the port B

[3:0] external interrupts. It can be set and cleared

by software only when I1 and I0 of the CC register

are both set to 1 (level 3).

0: No sensitivity inversion

1: Sensitivity inversion

0: No sensitivity inversion

1: Sensitivity inversion

Bits 1:0 = Reserved, must always be kept cleared.

35/157

1

ST7232A

INTERRUPTS (Cont’d)

Table 9. Nested Interrupts Register Map and Reset Values

Address

(Hex.)

Register

Label

7

6

5

4

3

2

1

0

ei1

SPI

ei0

MCC + SI

0024h

0025h

0026h

I1_3

1

I0_3

1

I1_2

1

I0_2

1

I1_1

1

I0_1

1

ISPR0

Reset Value

1

ei3

ei2

I1_7

1

I0_7

1

I1_6

1

I0_6

1

I1_5

1

I0_5

1

I1_4

1

I0_4

1

ISPR1

Reset Value

AVD

SCI

TIMER B

TIMER A

I1_11

1

I0_11

1

I1_10

1

I0_10

1

I1_9

I0_9

1

I1_8

1

I0_8

1

ISPR2

Reset Value

1

0027h

0028h

I1_13

1

I0_13

1

I1_12

1

I0_12

1

ISPR3

Reset Value

1

EICR

Reset Value

IS11

0

IS10

0

IPB

0

IS21

0

IS20

0

IPA

0

36/157

1

ST7232A

8 POWER SAVING MODES

8.1 INTRODUCTION

8.2 SLOW MODE

To give a large measure of flexibility to the applica-

tion in terms of power consumption, four main

power saving modes are implemented in the ST7

(see Figure 20): SLOW, WAIT (SLOW WAIT), AC-

TIVE HALT and HALT.

This mode has two targets:

– To reduce power consumption by decreasing the

internal clock in the device,

– To adapt the internal clock frequency (f

the available supply voltage.

) to

CPU

After a RESET the normal operating mode is se-

lected by default (RUN mode). This mode drives

the device (CPU and embedded peripherals) by

means of a master clock which is based on the

main oscillator frequency divided or multiplied by 2

SLOW mode is controlled by three bits in the

MCCSR register: the SMS bit which enables or

disables Slow mode and two CPx bits which select

the internal slow frequency (f

).

CPU

(f

).

In this mode, the master clock frequency (f

)

OSC2

can be divided by 2, 4, 8 or 16. The CPU and pe-

ripherals are clocked at this lower frequency

CPU

From RUN mode, the different power saving

modes may be selected by setting the relevant

register bits or by calling the specific ST7 software

instruction whose action depends on the oscillator

status.

(f

).

Note: SLOW-WAIT mode is activated when enter-

ing the WAIT mode while the device is already in

SLOW mode.

Figure 20. Power Saving Mode Transitions

Figure 21. SLOW Mode Clock Transitions

High

RUN

f

/2

f

/4

f

OSC2

f

CPU

f

OSC2

SLOW

WAIT

00

01

CP1:0

SMS

SLOW WAIT

ACTIVE HALT

HALT

NORMAL RUN MODE

REQUEST

NEW SLOW

FREQUENCY

REQUEST

Low

POWER CONSUMPTION

37/157

1

ST7232A

POWER SAVING MODES (Cont’d)

8.3 WAIT MODE

Figure 22. WAIT Mode Flow-chart

WAIT mode places the MCU in a low power con-

sumption mode by stopping the CPU.

This power saving mode is selected by calling the

‘WFI’ instruction.

OSCILLATOR

PERIPHERALS

CPU

I[1:0] BITS

ON

OFF

10

WFI INSTRUCTION

All peripherals remain active. During WAIT mode,

the I[1:0] bits of the CC register are forced to ‘10’,

to enable all interrupts. All other registers and

memory remain unchanged. The MCU remains in

WAIT mode until an interrupt or RESET occurs,

whereupon the Program Counter branches to the

starting address of the interrupt or Reset service

routine.

N

RESET

Y

N

INTERRUPT

The MCU will remain in WAIT mode until a Reset

or an Interrupt occurs, causing it to wake up.

Y

OSCILLATOR

PERIPHERALS

CPU

I[1:0] BITS

ON

OFF

ON

10

Refer to Figure 22.

256 OR 4096 CPU CLOCK

CYCLE DELAY

OSCILLATOR

PERIPHERALS

CPU

ON

I[1:0] BITS

XX ¹⁾

FETCH RESET VECTOR

OR SERVICE INTERRUPT

Note:

1. Before servicing an interrupt, the CC register is

pushed on the stack. The I[1:0] bits of the CC reg-

ister are set to the current software priority level of

the interrupt routine and recovered when the CC

register is popped.

38/157

1

ST7232A

POWER SAVING MODES (Cont’d)

8.4 ACTIVE-HALT AND HALT MODES

pending on option byte). Otherwise, the ST7 en-

ters HALT mode for the remaining t

period.

DELAY

ACTIVE-HALT and HALT modes are the two low-

est power consumption modes of the MCU. They

are both entered by executing the ‘HALT’ instruc-

tion. The decision to enter either in ACTIVE-HALT

or HALT mode is given by the MCC/RTC interrupt

enable flag (OIE bit in MCCSR register).

Figure 23. ACTIVE-HALT Timing Overview

ACTIVE

HALT

256 OR 4096 CPU

CYCLE DELAY

RUN

1)

RESET

OR

INTERRUPT

MCCSR Power Saving Mode entered when HALT

HALT

INSTRUCTION

[MCCSR.OIE=1]

OIE bit

instruction is executed

HALT mode

ACTIVE-HALT mode

FETCH

VECTOR

0

1

Figure 24. ACTIVE-HALT Mode Flow-chart

8.4.1 ACTIVE-HALT MODE

OSCILLATOR

PERIPHERALS

CPU

ON

OFF

10

2)

HALT INSTRUCTION

(MCCSR.OIE=1)

ACTIVE-HALT mode is the lowest power con-

sumption mode of the MCU with a real time clock

available. It is entered by executing the ‘HALT’ in-

struction when the OIE bit of the Main Clock Con-

troller Status register (MCCSR) is set (see Section

10.2 on page 53 for more details on the MCCSR

register).

I[1:0] BITS

N

RESET

Y

N

3)

INTERRUPT

Y

The MCU can exit ACTIVE-HALT mode on recep-

tion of either an MCC/RTC interrupt, a specific in-

terrupt (see Table 8, “Interrupt Mapping,” on

page 33) or a RESET. When exiting ACTIVE-

HALT mode by means of an interrupt, no 256 or

4096 CPU cycle delay occurs. The CPU resumes

operation by servicing the interrupt or by fetching

the reset vector which woke it up (see Figure 24).

OSCILLATOR

PERIPHERALS

CPU

ON

OFF

ON

4)

I[1:0] BITS

XX

256 OR 4096 CPU CLOCK

CYCLE DELAY

When entering ACTIVE-HALT mode, the I[1:0] bits

in the CC register are forced to ‘10b’ to enable in-

terrupts. Therefore, if an interrupt is pending, the

MCU wakes up immediately.

OSCILLATOR

PERIPHERALS

CPU

ON

4)

I[1:0] BITS

XX

In ACTIVE-HALT mode, only the main oscillator

and its associated counter (MCC/RTC) are run-

ning to keep a wake-up time base. All other periph-

erals are not clocked except those which get their

clock supply from another clock generator (such

as external or auxiliary oscillator).

FETCH RESET VECTOR

OR SERVICE INTERRUPT

Notes:

1. This delay occurs only if the MCU exits ACTIVE-

HALT mode by means of a RESET.

2. Peripheral clocked with an external clock source

can still be active.

3. Only the MCC/RTC interrupt and some specific

interrupts can exit the MCU from ACTIVE-HALT

mode (such as external interrupt). Refer to

Table 8, “Interrupt Mapping,” on page 33 for more

details.

4. Before servicing an interrupt, the CC register is

pushed on the stack. The I[1:0] bits of the CC reg-

ister are set to the current software priority level of

the interrupt routine and restored when the CC

register is popped.

The safeguard against staying locked in ACTIVE-

HALT mode is provided by the oscillator interrupt.

Note: As soon as the interrupt capability of one of

the oscillators is selected (MCCSR.OIE bit set),

entering ACTIVE-HALT mode while the Watchdog

is active does not generate a RESET.

This means that the device cannot spend more

than a defined delay in this power saving mode.

CAUTION: When exiting ACTIVE-HALT mode fol-

lowing an interrupt, OIE bit of MCCSR register

must not be cleared before t

after the inter-

CPU

DELAY

rupt occurs (t

= 256 or 4096 t

delay de-

DELAY

39/157

1

ST7232A

POWER SAVING MODES (Cont’d)

8.4.2 HALT MODE

Figure 26. HALT Mode Flow-chart

The HALT mode is the lowest power consumption

mode of the MCU. It is entered by executing the

‘HALT’ instruction when the OIE bit of the Main

Clock Controller Status register (MCCSR) is

cleared (see Section 10.2 on page 53 for more de-

tails on the MCCSR register).

HALT INSTRUCTION

(MCCSR.OIE=0)

ENABLE

WATCHDOG

0

DISABLE

WDGHALT ¹⁾

1

The MCU can exit HALT mode on reception of ei-

ther a specific interrupt (see Table 8, “Interrupt

Mapping,” on page 33) or a RESET. When exiting

HALT mode by means of a RESET or an interrupt,

the oscillator is immediately turned on and the 256

or 4096 CPU cycle delay is used to stabilize the

oscillator. After the start up delay, the CPU

resumes operation by servicing the interrupt or by

fetching the reset vector which woke it up (see Fig-

ure 26).

When entering HALT mode, the I[1:0] bits in the

CC register are forced to ‘10b’to enable interrupts.

Therefore, if an interrupt is pending, the MCU

wakes up immediately.

WATCHDOG

RESET

OSCILLATOR

OFF

PERIPHERALS ²⁾

CPU

OFF

10

I[1:0] BITS

N

RESET

Y

N

INTERRUPT ³⁾

In HALT mode, the main oscillator is turned off

causing all internal processing to be stopped, in-

cluding the operation of the on-chip peripherals.

All peripherals are not clocked except the ones

which get their clock supply from another clock

generator (such as an external or auxiliary oscilla-

tor).

Y

OSCILLATOR

PERIPHERALS

CPU

ON

OFF

ON

I[1:0] BITS

XX ⁴⁾

256 OR 4096 CPU CLOCK

CYCLE DELAY

The compatibility of Watchdog operation with

HALT mode is configured by the “WDGHALT” op-

tion bit of the option byte. The HALT instruction

when executed while the Watchdog system is en-

abled, can generate a Watchdog RESET (see

Section 14.1 on page 145) for more details.

OSCILLATOR

PERIPHERALS

CPU

ON

I[1:0] BITS

XX ⁴⁾

Figure 25. HALT Timing Overview

FETCH RESET VECTOR

OR SERVICE INTERRUPT

256 OR 4096 CPU

CYCLE DELAY

RUN

HALT

RUN

Notes:

RESET

OR

INTERRUPT

1. WDGHALT is an option bit. See option byte sec-

tion for more details.

HALT

INSTRUCTION

[MCCSR.OIE=0]

2. Peripheral clocked with an external clock source

can still be active.

FETCH

VECTOR

3. Only some specific interrupts can exit the MCU

from HALT mode (such as external interrupt). Re-

fer to Table 8, “Interrupt Mapping,” on page 33 for

more details.

4. Before servicing an interrupt, the CC register is

pushed on the stack. The I[1:0] bits of the CC reg-

ister are set to the current software priority level of

the interrupt routine and recovered when the CC

register is popped.

40/157

1

ST7232A

POWER SAVING MODES (Cont’d)

8.4.2.1 Halt Mode Recommendations

– The opcode for the HALT instruction is 0x8E. To

avoid an unexpected HALT instruction due to a

program counter failure, it is advised to clear all

occurrences of the data value 0x8E from memo-

ry. For example, avoid defining a constant in

ROM with the value 0x8E.

– Make sure that an external event is available to

wake up the microcontroller from Halt mode.

– When using an external interrupt to wake up the

microcontroller, reinitialize the corresponding I/O

as “Input Pull-up with Interrupt” before executing

the HALT instruction. The main reason for this is

that the I/O may be wrongly configured due to ex-

ternal interference or by an unforeseen logical

condition.

– As the HALT instruction clears the interrupt mask

in the CC register to allow interrupts, the user

may choose to clear all pending interrupt bits be-

fore executing the HALT instruction. This avoids

entering other peripheral interrupt routines after

executing the external interrupt routine corre-

sponding to the wake-up event (reset or external

interrupt).

– For the same reason, reinitialize the level sensi-

tiveness of each external interrupt as a precau-

tionary measure.

41/157

1

ST7232A

9 I/O PORTS

9.1 INTRODUCTION

Each pin can independently generate an interrupt

request. The interrupt sensitivity is independently

programmable using the sensitivity bits in the

EICR register.

The I/O ports offer different functional modes:

– transfer of data through digital inputs and outputs

and for specific pins:

Each external interrupt vector is linked to a dedi-

cated group of I/O port pins (see pinout description

and interrupt section). If several input pins are se-

lected simultaneously as interrupt sources, these

are first detected according to the sensitivity bits in

the EICR register and then logically ORed.

– external interrupt generation

– alternate signal input/output for the on-chip pe-

ripherals.

An I/O port contains up to 8 pins. Each pin can be

programmed independently as digital input (with or

without interrupt generation) or digital output.

The external interrupts are hardware interrupts,

which means that the request latch (not accessible

directly by the application) is automatically cleared

when the corresponding interrupt vector is

fetched. To clear an unwanted pending interrupt

by software, the sensitivity bits in the EICR register

must be modified.

9.2 FUNCTIONAL DESCRIPTION

Each port has 2 main registers:

– Data Register (DR)

– Data Direction Register (DDR)

and one optional register:

– Option Register (OR)

9.2.2 Output Modes

The output configuration is selected by setting the

corresponding DDR register bit. In this case, writ-

ing the DR register applies this digital value to the

I/O pin through the latch. Then reading the DR reg-

ister returns the previously stored value.

Each I/O pin may be programmed using the corre-

sponding register bits in the DDR and OR regis-

ters: bit X corresponding to pin X of the port. The

same correspondence is used for the DR register.

Two different output modes can be selected by

software through the OR register: Output push-pull

and open-drain.

The following description takes into account the

OR register, (for specific ports which do not pro-

vide this register refer to the I/O Port Implementa-

tion section). The generic I/O block diagram is

shown in Figure 27

DR register value and output pin status:

DR

0

Push-pull

Open-drain

Vss

V

9.2.1 Input Modes

SS

1

V

Floating

DD

The input configuration is selected by clearing the

corresponding DDR register bit.

9.2.3 Alternate Functions

In this case, reading the DR register returns the

digital value applied to the external I/O pin.

When an on-chip peripheral is configured to use a

pin, the alternate function is automatically select-

ed. This alternate function takes priority over the

standard I/O programming.

Different input modes can be selected by software

through the OR register.

Notes:

When the signal is coming from an on-chip periph-

eral, the I/O pin is automatically configured in out-

put mode (push-pull or open drain according to the

peripheral).

1. Writing the DR register modifies the latch value

but does not affect the pin status.

2. When switching from input to output mode, the

DR register has to be written first to drive the cor-

rect level on the pin as soon as the port is config-

ured as an output.

When the signal is going to an on-chip peripheral,

the I/O pin must be configured in input mode. In

this case, the pin state is also digitally readable by

addressing the DR register.

3. Do not use read/modify/write instructions (BSET

or BRES) to modify the DR register

External interrupt function

Note: Input pull-up configuration can cause unex-

pected value at the input of the alternate peripheral

input. When an on-chip peripheral use a pin as in-

put and output, this pin has to be configured in in-

put floating mode.

When an I/O is configured as Input with Interrupt,

an event on this I/O can generate an external inter-

rupt request to the CPU.

42/157

1

ST7232A

I/O PORTS (Cont’d)

Figure 27. I/O Port General Block Diagram

ALTERNATE

OUTPUT

1

0

REGISTER

ACCESS

P-BUFFER

(see table below)

V

DD

ALTERNATE

ENABLE

PULL-UP

(see table below)

DR

DDR

OR

V

DD

PULL-UP

CONDITION

PAD

If implemented

OR SEL

DDR SEL

DR SEL

N-BUFFER

DIODES

(see table below)

ANALOG

INPUT

CMOS

SCHMITT

TRIGGER

1

0

ALTERNATE

INPUT

EXTERNAL

INTERRUPT

SOURCE (ei )

x

Table 10. I/O Port Mode Options

Configuration Mode

Diodes

Pull-Up

P-Buffer

to V

SS

DD

Floating with/without Interrupt

Input

Off

On

Off

Pull-up with/without Interrupt

On

Push-pull

On

Off

NI

On

Off

NI

Output

Open Drain (logic level)

True Open Drain

NI (see note)

Legend: NI - not implemented

Off - implemented not activated

On - implemented and activated

Note: The diode to V is not implemented in the

DD

true open drain pads. A local protection between

the pad and V is implemented to protect the de-

SS

vice against positive stress.

43/157

1

ST7232A

I/O PORTS (Cont’d)

Table 11. I/O Port Configurations

Hardware Configuration

DR REGISTER ACCESS

NOT IMPLEMENTED IN

TRUE OPEN DRAIN

I/O PORTS

V

DD

PULL-UP

CONDITION

R

W

R

PU

DR

REGISTER

DATA BUS

PAD

ALTERNATE INPUT

EXTERNAL INTERRUPT

SOURCE (ei )

x

INTERRUPT

CONDITION

ANALOG INPUT

NOT IMPLEMENTED IN

TRUE OPEN DRAIN

I/O PORTS

DR REGISTER ACCESS

V

DD

R

PU

R/W

DR

REGISTER

DATA BUS

PAD

ALTERNATE

ENABLE

ALTERNATE

OUTPUT

NOT IMPLEMENTED IN

TRUE OPEN DRAIN

I/O PORTS

DR REGISTER ACCESS

V

DD

R

PU

R/W

DR

REGISTER

DATA BUS

PAD

ALTERNATE

ENABLE

ALTERNATE

OUTPUT

Notes:

1. When the I/O port is in input configuration and the associated alternate function is enabled as an output,

reading the DR register will read the alternate function output status.

2. When the I/O port is in output configuration and the associated alternate function is enabled as an input,

the alternate function reads the pin status given by the DR register content.

44/157

1

ST7232A

I/O PORTS (Cont’d)

CAUTION: The alternate function must not be ac-

tivated as long as the pin is configured as input

with interrupt, in order to avoid generating spurious

interrupts.

Figure 28. Interrupt I/O Port State Transitions

01

00

10

11

Analog alternate function

INPUT

floating/pull-up

interrupt

INPUT

floating

(reset state)

OUTPUT

open-drain

OUTPUT

push-pull

When the pin is used as an ADC input, the I/O

must be configured as floating input. The analog

multiplexer (controlled by the ADC registers)

switches the analog voltage present on the select-

ed pin to the common analog rail which is connect-

ed to the ADC input.

= DDR, OR

XX

9.4 LOW POWER MODES

It is recommended not to change the voltage level

or loading on any port pin while conversion is in

progress. Furthermore it is recommended not to

have clocking pins located close to a selected an-

alog pin.

Mode

WAIT

HALT

Description

No effect on I/O ports. External interrupts

cause the device to exit from WAIT mode.

No effect on I/O ports. External interrupts

cause the device to exit from HALT mode.

WARNING: The analog input voltage level must

be within the limits stated in the absolute maxi-

mum ratings.

9.5 INTERRUPTS

9.3 I/O PORT IMPLEMENTATION

The external interrupt event generates an interrupt

if the corresponding configuration is selected with

DDR and OR registers and the interrupt mask in

the CC register is not active (RIM instruction).

The hardware implementation on each I/O port de-

pends on the settings in the DDR and OR registers

and specific feature of the I/O port such as ADC In-

put or true open drain.

Enable Exit

Control from

Exit

from

Halt

Event

Flag

Interrupt Event

Switching these I/O ports from one state to anoth-

er should be done in a sequence that prevents un-

wanted side effects. Recommended safe transi-

tions are illustrated in Figure 28 Other transitions

are potentially risky and should be avoided, since

they are likely to present unwanted side-effects

such as spurious interrupt generation.

Bit

Wait

External interrupt on

selected external

event

DDRx

ORx

-

Yes

45/157

1

ST7232A

I/O PORTS (Cont’d)

9.5.1 I/O Port Implementation

The I/O port register configurations are summa-

rised as follows.

PA3, PB3, PF2 (without pull-up)

MODE

floating input

DDR

OR

0

Standard Ports

0

1

floating interrupt input

open drain output

push-pull output

1

PA5:4, PC7:0, PD5:0,

PE1:0, PF7:6, 4

0

1

MODE

DDR

OR

0

floating input

pull-up input

0

1

True Open Drain Ports

PA7:6

open drain output

push-pull output

0

1

MODE

floating input

DDR

0

1

Interrupt Ports

open drain (high sink ports)

PB4, PB2:0, PF1:0 (with pull-up)

MODE

floating input

DDR

OR

0

1

pull-up interrupt input

open drain output

push-pull output

1

0

1

Table 12. Port Configuration

Input

floating

Output

Port

Port A

Port B

Pin name

PA7:6

OR = 0

OR = 1

OR = 0

OR = 1

true open-drain

PA5:4

PA3

floating

pull-up

open drain

push-pull

floating interrupt

pull-up interrupt

pull-up

PB3

PB4, PB2:0

PC7:0

PD5:0

PE1:0

PF7:6, 4

PF2

Port C

Port D

Port E

pull-up

Port F

floating interrupt

pull-up interrupt

PF1:0

46/157

1

ST7232A

I/O PORTS (Cont’d)

Table 13. I/O Port Register Map and Reset Values

Address

(Hex.)

Register

Label

7

6

5

4

3

2

1

0

Reset Value

of all I/O port registers

0

0000h

0001h

0002h

0003h

0004h

0005h

0006h

0007h

0008h

0009h

000Ah

000Bh

000Ch

000Dh

000Eh

000Fh

0010h

0011h

PADR

PADDR

PAOR

PBDR

PBDDR

PBOR

PCDR

PCDDR

PCOR

PDDR

PDDDR

PDOR

PEDR

MSB

LSB

PEDDR

PEOR

PFDR

PFDDR

PFOR

47/157

1

ST7232A

10 ON-CHIP PERIPHERALS

10.1 WATCHDOG TIMER (WDG)

10.1.1 Introduction

If the watchdog is activated (the WDGA bit is set)

and when the 7-bit timer (bits T[6:0]) rolls over

from 40h to 3Fh (T6 becomes cleared), it initiates

a reset cycle pulling low the reset pin for typically

30µs.

The Watchdog timer is used to detect the occur-

rence of a software fault, usually generated by ex-

ternal interference or by unforeseen logical condi-

tions, which causes the application program to

abandon its normal sequence. The Watchdog cir-

cuit generates an MCU reset on expiry of a pro-

grammed time period, unless the program refresh-

es the counter’s contents before the T6 bit be-

comes cleared.

The application program must write in the

WDGCR register at regular intervals during normal

operation to prevent an MCU reset. This down-

counter is free-running: it counts down even if the

watchdog is disabled. The value to be stored in the

WDGCR register must be between FFh and C0h:

10.1.2 Main Features

■ Programmable free-running downcounter

■ Programmable reset

– The WDGA bit is set (watchdog enabled)

– The T6 bit is set to prevent generating an imme-

diate reset

■ Reset (if watchdog activated) when the T6 bit

– The T[5:0] bits contain the number of increments

which represents the time delay before the

watchdog produces a reset (see Figure 30. Ap-

proximate Timeout Duration). The timing varies

between a minimum and a maximum value due

to the unknown status of the prescaler when writ-

ing to the WDGCR register (see Figure 31).

reaches zero

■ Optional

reset

on

HALT

instruction

(configurable by option byte)

■ Hardware Watchdog selectable by option byte

10.1.3 Functional Description

Following a reset, the watchdog is disabled. Once

activated it cannot be disabled, except by a reset.

The counter value stored in the Watchdog Control

register (WDGCR bits T[6:0]), is decremented

every 16384 f

cycles (approx.), and the

The T6 bit can be used to generate a software re-

set (the WDGA bit is set and the T6 bit is cleared).

OSC2

length of the timeout period can be programmed

by the user in 64 increments.

If the watchdog is activated, the HALT instruction

will generate a Reset.

Figure 29. Watchdog Block Diagram

RESET

f

OSC2

MCC/RTC

WATCHDOG CONTROL REGISTER (WDGCR)

T5

DIV 64

WDGA T6

T1

T0

T4

T2

T3

6-BIT DOWNCOUNTER (CNT)

12-BIT MCC

RTC COUNTER

WDG PRESCALER

DIV 4

TB[1:0] bits

(MCCSR

Register)

MSB

LSB

0

6 5

11

48/157

1

ST7232A

WATCHDOG TIMER (Cont’d)

10.1.4 How to Program the Watchdog Timeout

more precision is needed, use the formulae in Fig-

ure 31.

Figure 30 shows the linear relationship between

the 6-bit value to be loaded in the Watchdog Coun-

ter (CNT) and the resulting timeout duration in mil-

liseconds. This can be used for a quick calculation

without taking the timing variations into account. If

Caution: When writing to the WDGCR register, al-

ways write 1 in the T6 bit to avoid generating an

immediate reset.

Figure 30. Approximate Timeout Duration

3F

38

30

28

20

18

10

08

00

1.5

18

34

50

65

82

98

114

128

Watchdog timeout (ms) @ 8 MHz. f

OSC2

49/157

1

ST7232A

WATCHDOG TIMER (Cont’d)

Figure 31. Exact Timeout Duration (t

and t

)

max

min

WHERE:

t

= (LSB + 128) x 64 x t

min0

OSC2

= 16384 x t

= 125ns if f

max0

OSC2

=8 MHz

OSC2

CNT = Value of T[5:0] bits in the WDGCR register (6 bits)

MSB and LSB are values from the table below depending on the timebase selected by the TB[1:0] bits

in the MCCSR register

TB1 Bit

TB0 Bit

Selected MCCSR

Timebase

MSB

LSB

(MCCSR Reg.) (MCCSR Reg.)

0

1

0

1

0

1

2ms

4ms

4

8

59

53

35

54

10ms

25ms

20

49

To calculate the minimum Watchdog Timeout (t ):

min

MSB

4

IF

THEN

ELSE

-------------

CNT <

t

= t

+ 16384 × CNT × t

min

min0

osc2

4CNT

----------------

4CNT

----------------

⎛

⎞

⎠

t

= t

+ 16384 × CNT –

+ (192 + LSB) × 64 ×

× t

min

min0

⎝

osc2

MSB

To calculate the maximum Watchdog Timeout (t

):

max

MSB

4

IF

-------------

THEN

ELSE

CNT ≤

t

= t

+ 16384 × CNT × t

max

max0

osc2

4CNT

----------------

4CNT

----------------

⎛

⎞

t

= t

+ 16384 × CNT –

+ (192 + LSB) × 64 ×

× t

max

max0

osc2

⎝

⎠

MSB

Note: In the above formulae, division results must be rounded down to the next integer value.

Example:

With 2ms timeout selected in MCCSR register

Min. Watchdog

Timeout (ms)

Max. Watchdog

Timeout (ms)

Value of T[5:0] Bits in

WDGCR Register (Hex.)

t

min

max

00

3F

1.496

128

2.048

128.552

50/157

1

ST7232A

WATCHDOG TIMER (Cont’d)

10.1.5 Low Power Modes

Mode Description

SLOW No effect on Watchdog.

WAIT No effect on Watchdog.

OIE bit in

MCCSR

register

WDGHALT bit

in Option

Byte

No Watchdog reset is generated. The MCU enters Halt mode. The Watch-

dog counter is decremented once and then stops counting and is no longer

able to generate a watchdog reset until the MCU receives an external inter-

rupt or a reset.

0

If an external interrupt is received, the Watchdog restarts counting after 256

or 4096 CPU clocks. If a reset is generated, the Watchdog is disabled (reset

state) unless Hardware Watchdog is selected by option byte. For applica-

tion recommendations see Section 10.1.7 below.

HALT

0

1

x

A reset is generated.

No reset is generated. The MCU enters Active Halt mode. The Watchdog

counter is not decremented. It stop counting. When the MCU receives an

oscillator interrupt or external interrupt, the Watchdog restarts counting im-

mediately. When the MCU receives a reset the Watchdog restarts counting

after 256 or 4096 CPU clocks.

10.1.6 Hardware Watchdog Option

10.1.9 Register Description

If Hardware Watchdog is selected by option byte,

the watchdog is always active and the WDGA bit in

the WDGCR is not used. Refer to the Option Byte

description.

CONTROL REGISTER (WDGCR)

Read/Write

Reset Value: 0111 1111 (7Fh)

10.1.7 Using Halt Mode with the WDG

(WDGHALT option)

7

0

WDGA T6

T5

T4

T3

T2

T1

T0

The following recommendation applies if Halt

mode is used when the watchdog is enabled.

– Before executing the HALT instruction, refresh

the WDG counter, to avoid an unexpected WDG

reset immediately after waking up the microcon-

troller.

Bit 7 = WDGA Activation bit.

This bit is set by software and only cleared by

hardware after a reset. When WDGA = 1, the

watchdog can generate a reset.

0: Watchdog disabled

1: Watchdog enabled

10.1.8 Interrupts

None.

Note: This bit is not used if the hardware watch-

dog option is enabled by option byte.

Bit 6:0 = T[6:0] 7-bit counter (MSB to LSB).

These bits contain the value of the watchdog

counter. It is decremented every 16384 f

cles (approx.). A reset is produced when it rolls

over from 40h to 3Fh (T6 becomes cleared).

cy-

OSC2

51/157

1

ST7232A

Table 14. Watchdog Timer Register Map and Reset Values

Address

(Hex.)

Register

Label

7

6

5

4

3

2

1

0

WDGCR

Reset Value

WDGA

0

T6

1

T5

1

T4

1

T3

1

T2

1

T1

1

T0

1

002Ah

52/157

1

ST7232A

10.2

MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK AND BEEPER (MCC/RTC)

The Main Clock Controller consists of three differ-

ent functions:

external devices. It is controlled by the MCO bit in

the MCCSR register.

CAUTION: When selected, the clock out pin sus-

pends the clock during ACTIVE-HALT mode.

■

a programmable CPU clock prescaler

■

a clock-out signal to supply external devices

10.2.3

Real Time Clock Timer (RTC)

■

a real time clock timer with interrupt capability

The counter of the real time clock timer allows an

interrupt to be generated based on an accurate

real time clock. Four different time bases depend-

Each function can be used independently and si-

multaneously.

10.2.1

Programmable CPU Clock Prescaler

ing directly on f

are available. The whole

OSC2

functionality is controlled by four bits of the MCC-

SR register: TB[1:0], OIE and OIF.

The programmable CPU clock prescaler supplies

the clock for the ST7 CPU and its internal periph-

erals. It manages SLOW power saving mode (See

Section 8.2 SLOW MODE for more details).

When the RTC interrupt is enabled (OIE bit set),

the ST7 enters ACTIVE-HALT mode when the

HALT instruction is executed. See Section 8.4 AC-

TIVE-HALT AND HALT MODES for more details.

The prescaler selects the f

main clock frequen-

CPU

cy and is controlled by three bits in the MCCSR

register: CP[1:0] and SMS.

10.2.4

Beeper

10.2.2

Clock-out Capability

The clock-out capability is an alternate function of

an I/O port pin that outputs a f clock to drive

The beep function is controlled by the MCCBCR

register. It can output three selectable frequencies

on the BEEP pin (I/O port alternate function).

OSC2

Figure 32.

Main Clock Controller (MCC/RTC) Block Diagram

BC1 BC0

MCCBCR

BEEP

MCO

BEEP SIGNAL

SELECTION

12-BIT MCC RTC

COUNTER

TO

DIV 64

WATCHDOG

TIMER

MCO CP1 CP0 SMS TB1 TB0 OIE OIF

MCCSR

MCC/RTC INTERRUPT

f_CPU

f_OSC2

DIV 2, 4, 8, 16

1

0

CPU CLOCK

TO CPU AND

PERIPHERALS

53/157

1

ST7232A

MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont’d)

10.2.5

Low Power Modes

Bit 6:5 = CP[1:0] CPU clock prescaler

Mode

Description

These bits select the CPU clock prescaler which is

applied in the different slow modes. Their action is

conditioned by the setting of the SMS bit. These

two bits are set and cleared by software

No effect on MCC/RTC peripheral.

MCC/RTC interrupt cause the device to exit

from WAIT mode.

WAIT

No effect on MCC/RTC counter (OIE bit is

f

in SLOW mode

CP1

CP0

ACTIVE- set), the registers are frozen.

CPU

HALT

MCC/RTC interrupt cause the device to exit

from ACTIVE-HALT mode.

f

/ 2

/ 4

0

1

0

1

0

1

OSC2

MCC/RTC counter and registers are frozen.

MCC/RTC operation resumes when the

MCU is woken up by an interrupt with “exit

from HALT” capability.

/ 8

HALT

f

/ 16

OSC2

10.2.6

Bit 4 = SMS Slow mode select

This bit is set and cleared by software.

0: Normal mode. f = f

Interrupts

The MCC/RTC interrupt event generates an inter-

rupt if the OIE bit of the MCCSR register is set and

the interrupt mask in the CC register is not active

(RIM instruction).

OSC2

CPU

1: Slow mode. f

is given by CP1, CP0

CPU

See Section 8.2 SLOW MODE and Section 10.2

MAIN CLOCK CONTROLLER WITH REAL TIME

CLOCK AND BEEPER (MCC/RTC) for more de-

tails.

Enable Exit

Control from

Exit

from

Halt

Event

Flag

Interrupt Event

Bit

Wait

Time base overflow

event

1)

Bit 3:2 = TB[1:0] Time base control

OIF

OIE

Yes

No

These bits select the programmable divider time

base. They are set and cleared by software.

Note:

The MCC/RTC interrupt wakes up the MCU from

ACTIVE-HALT mode, not from HALT mode.

Time Base

Counter

TB1 TB0

Prescaler

f

=4MHz

f

=8MHz

OSC2

16000

32000

80000

200000

4ms

2ms

4ms

0

1

0

1

0

1

8ms

20ms

50ms

10.2.7

Register Description

10ms

25ms

MCC CONTROL/STATUS REGISTER (MCCSR)

Read/Write

Reset Value: 0000 0000 (00h

)

A modification of the time base is taken into ac-

count at the end of the current period (previously

set) to avoid an unwanted time shift. This allows to

use this time base as a real time clock.

7

0

MCO CP1 CP0 SMS TB1 TB0 OIE OIF

Bit 1 = OIE Oscillator interrupt enable

This bit set and cleared by software.

0: Oscillator interrupt disabled

Bit 7 = MCO Main clock out selection

This bit enables the MCO alternate function on the

PF0 I/O port. It is set and cleared by software.

0: MCO alternate function disabled (I/O pin free for

general-purpose I/O)

1: Oscillator interrupt enabled

This interrupt can be used to exit from ACTIVE-

HALT mode.

1: MCO alternate function enabled (f

port)

on I/O

CPU

When this bit is set, calling the ST7 software HALT

instruction enters the ACTIVE-HALT power saving

mode

.

Note: To reduce power consumption, the MCO

function is not active in ACTIVE-HALT mode.

54/157

1

ST7232A

MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont’d)

MCC BEEP CONTROL REGISTER (MCCBCR)

Read/Write

Bit 0 = OIF Oscillator interrupt flag

This bit is set by hardware and cleared by software

reading the MCCSR register. It indicates when set

that the main oscillator has reached the selected

elapsed time (TB1:0).

Reset Value: 0000 0000 (00h)

7

0

0: Timeout not reached

1: Timeout reached

0

BC1 BC0

CAUTION: The BRES and BSET instructions

must not be used on the MCCSR register to avoid

unintentionally clearing the OIF bit.

Bit 7:2 = Reserved, must be kept cleared.

Bit 1:0 = BC[1:0] Beep control

These 2 bits select the PF1 pin beep capability.

BC1

BC0

Beep mode with f

=8MHz

OSC2

0

1

0

1

0

1

Off

~2-KHz

Output

Beep signal

~50% duty cycle

~1-KHz

~500-Hz

The beep output signal is available in ACTIVE-

HALT mode but has to be disabled to reduce the

consumption.

Table 15. Main Clock Controller Register Map and Reset Values

Address

(Hex.)

Register

Label

7

6

5

4

3

2

1

0

MCCSR

Reset Value

MCO

0

CP1

0

CP0

0

SMS

0

TB1

0

TB0

0

OIE

0

OIF

0

002Ch

002Dh

MCCBCR

Reset Value

BC1

0

BC0

0

55/157

1

ST7232A

10.3 16-BIT TIMER

10.3.1 Introduction

When reading an input signal on a non-bonded

pin, the value will always be ‘1’.

The timer consists of a 16-bit free-running counter

driven by a programmable prescaler.

10.3.3 Functional Description

10.3.3.1 Counter

It may be used for a variety of purposes, including

pulse length measurement of up to two input sig-

nals (input capture) or generation of up to two out-

put waveforms (output compare and PWM).

The main block of the Programmable Timer is a

16-bit free running upcounter and its associated

16-bit registers. The 16-bit registers are made up

of two 8-bit registers called high & low.

Pulse lengths and waveform periods can be mod-

ulated from a few microseconds to several milli-

seconds using the timer prescaler and the CPU

clock prescaler.

Counter Register (CR):

– Counter High Register (CHR) is the most sig-

nificant byte (MS Byte).

Some ST7 devices have two on-chip 16-bit timers.

They are completely independent, and do not

share any resources. They are synchronized after

a MCU reset as long as the timer clock frequen-

cies are not modified.

– Counter Low Register (CLR) is the least sig-

nificant byte (LS Byte).

Alternate Counter Register (ACR)

– Alternate Counter High Register (ACHR) is

the most significant byte (MS Byte).

This description covers one or two 16-bit timers. In

ST7 devices with two timers, register names are

prefixed with TA (Timer A) or TB (Timer B).

– Alternate Counter Low Register (ACLR) is the

least significant byte (LS Byte).

These two read-only 16-bit registers contain the

same value but with the difference that reading the

ACLR register does not clear the TOF bit (Timer

overflow flag), located in the Status register, (SR),

(see note at the end of paragraph titled 16-bit read

sequence).

10.3.2 Main Features

■ Programmableprescaler:f_CPUdividedby2,4or8.

■ Overflow status flag and maskable interrupt

■ External clock input (must be at least 4 times

slowerthantheCPUclockspeed)withthechoice

of active edge

■ 1 or 2 Output Compare functions each with:

– 2 dedicated 16-bit registers

Writing in the CLR register or ACLR register resets

the free running counter to the FFFCh value.

Both counters have a reset value of FFFCh (this is

the only value which is reloaded in the 16-bit tim-

er). The reset value of both counters is also

FFFCh in One Pulse mode and PWM mode.

– 2 dedicated programmable signals

– 2 dedicated status flags

– 1 dedicated maskable interrupt

■ 1 or 2 Input Capture functions each with:

– 2 dedicated 16-bit registers

The timer clock depends on the clock control bits

of the CR2 register, as illustrated in Table 16 Clock

Control Bits. The value in the counter register re-

peats every 131072, 262144 or 524288 CPU clock

cycles depending on the CC[1:0] bits.

– 2 dedicated active edge selection signals

– 2 dedicated status flags

The timer frequency can be f

or an external frequency.

/2, f

/4, f

/8

CPU

– 1 dedicated maskable interrupt

■ Pulse width modulation mode (PWM)

■ One pulse mode

Caution: In Flash devices, Timer A functionality

has the following restrictions:

■ Reduced Power Mode

■ 5 alternate functions on I/O ports (ICAP1, ICAP2,

– TAOC2HR and TAOC2LR registers are write

only

OCMP1, OCMP2, EXTCLK)*

– Input Capture 2 is not implemented

The Block Diagram is shown in Figure 33.

– The corresponding interrupts cannot be used

(ICF2, OCF2 forced by hardware to zero)

*Note: Some timer pins may not be available (not

bonded) in some ST7 devices. Refer to the device

pin out description.

56/157

1

ST7232A

16-BIT TIMER (Cont’d)

Figure 33. Timer Block Diagram

ST7 INTERNAL BUS

f

CPU

MCU-PERIPHERAL INTERFACE

8 low

8-bit

8 high

8

buffer

EXEDG

16

INPUT

CAPTURE

REGISTER

INPUT

CAPTURE

REGISTER

OUTPUT

COMPARE

REGISTER

OUTPUT

COMPARE

REGISTER

1/2

1/4

1/8

COUNTER

REGISTER

1

2

ALTERNATE

COUNTER

REGISTER

EXTCLK

16

CC[1:0]

TIMER INTERNAL BUS

16 16

OVERFLOW

DETECT

EDGE DETECT

CIRCUIT1

OUTPUT COMPARE

CIRCUIT

ICAP1

CIRCUIT

6

EDGE DETECT

CIRCUIT2

ICAP2

OCMP1

LATCH1

LATCH2

0

ICF1 OCF1 TOF ICF2 OCF2

0

TIMD

(Control/Status Register)

OCMP2

CSR

EXEDG

ICIE OCIE TOIE FOLV2 FOLV1OLVL2 IEDG1 OLVL1

OC1E

OPM PWM CC1 CC0 IEDG2

OC2E

(Control Register 1) CR1

(Control Register 2) CR2

(See note)

Note: If IC, OC and TO interrupt requests have separate vectors

then the last OR is not present (See device Interrupt Vector Table)

TIMER INTERRUPT

57/157

1

ST7232A

16-BIT TIMER (Cont’d)

16-bit read sequence: (from either the Counter

Register or the Alternate Counter Register).

Clearing the overflow interrupt request is done in

two steps:

1. Reading the SR register while the TOF bit is set.

2. An access (read or write) to the CLR register.

Beginning of the sequence

Read

LS Byte

Notes: The TOF bit is not cleared by accesses to

ACLR register. The advantage of accessing the

ACLR register rather than the CLR register is that

it allows simultaneous use of the overflow function

and reading the free running counter at random

times (for example, to measure elapsed time) with-

out the risk of clearing the TOF bit erroneously.

MS Byte

At t0

is buffered

Other

instructions

Returns the buffered

LS Byte value at t0

Read

LS Byte

At t0 +∆t

The timer is not affected by WAIT mode.

In HALT mode, the counter stops counting until the

mode is exited. Counting then resumes from the

previous count (MCU awakened by an interrupt) or

from the reset count (MCU awakened by a Reset).

Sequence completed

The user must read the MS Byte first, then the LS

Byte value is buffered automatically.

This buffered value remains unchanged until the

16-bit read sequence is completed, even if the

user reads the MS Byte several times.

10.3.3.2 External Clock

The external clock (where available) is selected if

CC0=1 and CC1=1 in the CR2 register.

After a complete reading sequence, if only the

CLR register or ACLR register are read, they re-

turn the LS Byte of the count value at the time of

the read.

The status of the EXEDG bit in the CR2 register

determines the type of level transition on the exter-

nal clock pin EXTCLK that will trigger the free run-

ning counter.

Whatever the timer mode used (input capture, out-

put compare, one pulse mode or PWM mode) an

overflow occurs when the counter rolls over from

FFFFh to 0000h then:

The counter is synchronized with the falling edge

of the internal CPU clock.

A minimum of four falling edges of the CPU clock

must occur between two consecutive active edges

of the external clock; thus the external clock fre-

quency must be less than a quarter of the CPU

clock frequency.

– The TOF bit of the SR register is set.

– A timer interrupt is generated if:

– TOIE bit of the CR1 register is set and

– I bit of the CC register is cleared.

If one of these conditions is false, the interrupt re-

mains pending to be issued as soon as they are

both true.

58/157

1

ST7232A

16-BIT TIMER (Cont’d)

Figure 34. Counter Timing Diagram, internal clock divided by 2

CPU CLOCK

INTERNAL RESET

TIMER CLOCK

FFFD FFFE FFFF 0000 0001 0002 0003

COUNTER REGISTER

TIMER OVERFLOW FLAG (TOF)

Figure 35. Counter Timing Diagram, internal clock divided by 4

CPU CLOCK

INTERNAL RESET

TIMER CLOCK

FFFC

FFFD

0000

0001

COUNTER REGISTER

TIMER OVERFLOW FLAG (TOF)

Figure 36. Counter Timing Diagram, internal clock divided by 8

CPU CLOCK

INTERNAL RESET

TIMER CLOCK

0000

FFFC

FFFD

COUNTER REGISTER

TIMER OVERFLOW FLAG (TOF)

Note: The MCU is in reset state when the internal reset signal is high, when it is low the MCU is running.

59/157

1

ST7232A

16-BIT TIMER (Cont’d)

10.3.3.3 Input Capture

When an input capture occurs:

In this section, the index, i, may be 1 or 2 because

there are 2 input capture functions in the 16-bit

timer.

– ICFi bit is set.

– The ICiR register contains the value of the free

running counter on the active transition on the

ICAPi pin (see Figure 38).

The two 16-bit input capture registers (IC1R and

IC2R) are used to latch the value of the free run-

ning counter after a transition is detected on the

ICAPi pin (see figure 5).

– A timer interrupt is generated if the ICIE bit is set

and the I bit is cleared in the CC register. Other-

wise, the interrupt remains pending until both

conditions become true.

MS Byte

LS Byte

ICiR

ICiHR

ICiLR

Clearing the Input Capture interrupt request (i.e.

clearing the ICFi bit) is done in two steps:

ICiR register is a read-only register.

1. Reading the SR register while the ICFi bit is set.

2. An access (read or write) to the ICiLR register.

The active transition is software programmable

through the IEDGi bit of Control Registers (CRi).

Timing resolution is one count of the free running

Notes:

counter: (f

/CC[1:0]).

CPU

1. After reading the ICiHR register, transfer of

input capture data is inhibited and ICFi will

never be set until the ICiLR register is also

read.

Procedure:

To use the input capture function select the follow-

ing in the CR2 register:

2. The ICiR register contains the free running

counter value which corresponds to the most

recent input capture.

– Select the timer clock (CC[1:0]) (see Table 16

Clock Control Bits).

3. The 2 input capture functions can be used

together even if the timer also uses the 2 output

compare functions.

– Select the edge of the active transition on the

ICAP2 pin with the IEDG2 bit (the ICAP2 pin

must be configured as floating input or input with

pull-up without interrupt if this configuration is

available).

4. In One pulse Mode and PWM mode only Input

Capture 2 can be used.

And select the following in the CR1 register:

5. The alternate inputs (ICAP1 & ICAP2) are

always directly connected to the timer. So any

transitions on these pins activates the input

capture function.

– Set the ICIE bit to generate an interrupt after an

input capture coming from either the ICAP1 pin

or the ICAP2 pin

Moreover if one of the ICAPi pins is configured

as an input and the second one as an output,

an interrupt can be generated if the user tog-

gles the output pin and if the ICIE bit is set.

This can be avoided if the input capture func-

tion i is disabled by reading the ICiHR (see note

1).

– Select the edge of the active transition on the

ICAP1 pin with the IEDG1 bit (the ICAP1pin must

be configured as floating input or input with pull-

up without interrupt if this configuration is availa-

ble).

6. The TOF bit can be used with interrupt genera-

tion in order to measure events that go beyond

the timer range (FFFFh).

7. In Flash devices, the ICAP2 registers

(TAIC2HR, TAIC2LR) are not available on

Timer A. The corresponding interrupts cannot

be used (ICF2 is forced by hardware to 0).

60/157

1

ST7232A

16-BIT TIMER (Cont’d)

Figure 37. Input Capture Block Diagram

ICAP1

(Control Register 1) CR1

EDGE DETECT

CIRCUIT2

EDGE DETECT

CIRCUIT1

ICIE

IEDG1

ICAP2

(Status Register) SR

ICF1

ICF2

0

IC2R Register

IC1R Register

(Control Register 2) CR2

16-BIT

16-BIT FREE RUNNING

COUNTER

IEDG2

CC0

CC1

Figure 38. Input Capture Timing Diagram

TIMER CLOCK

FF01

FF02

FF03

COUNTER REGISTER

ICAPi PIN

ICAPi FLAG

FF03

ICAPi REGISTER

Note: The rising edge is the active edge.

61/157

1

ST7232A

16-BIT TIMER (Cont’d)

10.3.3.4 Output Compare

– The OCMPi pin takes OLVLi bit value (OCMPi

pin latch is forced low during reset).

In this section, the index, i, may be 1 or 2 because

there are 2 output compare functions in the 16-bit

timer.

– A timer interrupt is generated if the OCIE bit is

set in the CR1 register and the I bit is cleared in

the CC register (CC).

This function can be used to control an output

waveform or indicate when a period of time has

elapsed.

The OCiR register value required for a specific tim-

ing application can be calculated using the follow-

ing formula:

When a match is found between the Output Com-

pare register and the free running counter, the out-

put compare function:

– Assigns pins with a programmable value if the

∆t f

* CPU

PRESC

∆ OCiR =

OCiE bit is set

– Sets a flag in the status register

– Generates an interrupt if enabled

Where:

∆t

= Output compare period (in seconds)

= CPU clock frequency (in hertz)

Two 16-bit registers Output Compare Register 1

(OC1R) and Output Compare Register 2 (OC2R)

contain the value to be compared to the counter

register each timer clock cycle.

f

CPU

= Timer prescaler factor (2, 4 or 8 de-

pending on CC[1:0] bits, see Table 16

Clock Control Bits)

PRESC

MS Byte

LS Byte

OCiR

OCiHR

OCiLR

If the timer clock is an external clock, the formula

is:

These registers are readable and writable and are

not affected by the timer hardware. A reset event

changes the OCiR value to 8000h.

∆ OCiR = ∆t f

* EXT

Timing resolution is one count of the free running

Where:

counter: (f

).

CC[1:0]

CPU/

∆t

= Output compare period (in seconds)

= External timer clock frequency (in hertz)

f

EXT

Procedure:

To use the output compare function, select the fol-

lowing in the CR2 register:

Clearing the output compare interrupt request (i.e.

clearing the OCFi bit) is done by:

– Set the OCiE bit if an output is needed then the

OCMPi pin is dedicated to the output compare i

signal.

1. Reading the SR register while the OCFi bit is

set.

2. An access (read or write) to the OCiLR register.

– Select the timer clock (CC[1:0]) (see Table 16

Clock Control Bits).

The following procedure is recommended to pre-

vent the OCFi bit from being set between the time

it is read and the write to the OCiR register:

And select the following in the CR1 register:

– Select the OLVLi bit to applied to the OCMPi pins

after the match occurs.

– Write to the OCiHR register (further compares

are inhibited).

– Set the OCIE bit to generate an interrupt if it is

needed.

– Read the SR register (first step of the clearance

of the OCFi bit, which may be already set).

When a match is found between OCRi register

and CR register:

– Write to the OCiLR register (enables the output

compare function and clears the OCFi bit).

– OCFi bit is set.

62/157

1

ST7232A

16-BIT TIMER (Cont’d)

Notes:

6. In Flash devices, the TAOC2HR, TAOC2LR

registers are "write only" in Timer A. The corre-

sponding event cannot be generated (OCF2 is

forced by hardware to 0).

1. After a processor write cycle to the OCiHR reg-

ister, the output compare function is inhibited

until the OCiLR register is also written.

Forced Compare Output capability

2. If the OCiE bit is not set, the OCMPi pin is a

general I/O port and the OLVLi bit will not

appear when a match is found but an interrupt

could be generated if the OCIE bit is set.

When the FOLVi bit is set by software, the OLVLi

bit is copied to the OCMPi pin. The OLVi bit has to

be toggled in order to toggle the OCMPi pin when

it is enabled (OCiE bit=1). The OCFi bit is then not

set by hardware, and thus no interrupt request is

generated.

3. When the timer clock is f

/2, OCFi and

CPU

OCMPi are set while the counter value equals

the OCiR register value (see Figure 40 on page

64). This behaviour is the same in OPM or

PWM mode.

The FOLVLi bits have no effect in both one pulse

mode and PWM mode.

When the timer clock is f

/4, f

/8 or in

CPU

external clock mode, OCFi and OCMPi are set

while the counter value equals the OCiR regis-

ter value plus 1 (see Figure 41 on page 64).

4. The output compare functions can be used both

for generating external events on the OCMPi

pins even if the input capture mode is also

used.

5. The value in the 16-bit OCiR register and the

OLVi bit should be changed after each suc-

cessful comparison in order to control an output

waveform or establish a new elapsed timeout.

Figure 39. Output Compare Block Diagram

16 BIT FREE RUNNING

OC1E

CC1 CC0

OC2E

COUNTER

(Control Register 2) CR2

16-bit

(Control Register 1) CR1

OUTPUT COMPARE

CIRCUIT

Latch

1

OCIE

FOLV2 FOLV1OLVL2

OLVL1

OCMP1

16-bit

Latch

2

OCMP2

OC1R Register

OCF1

OCF2

0

OC2R Register

(Status Register) SR

63/157

1

ST7232A

16-BIT TIMER (Cont’d)

Figure 40. Output Compare Timing Diagram, f

=f

/2

TIMER

CPU

INTERNAL CPU CLOCK

TIMER CLOCK

COUNTER REGISTER

2ECF 2ED0 2ED1 2ED2

2ED3

2ED4

2ED3

OUTPUT COMPARE REGISTER i (OCRi)

OUTPUT COMPARE FLAG i (OCFi)

OCMPi PIN (OLVLi=1)

Figure 41. Output Compare Timing Diagram, f

=f

/4

TIMER

CPU

INTERNAL CPU CLOCK

TIMER CLOCK

2ECF 2ED0 2ED1 2ED2

2ED3

2ED4

2ED3

COUNTER REGISTER

OUTPUT COMPARE REGISTER i (OCRi)

COMPARE REGISTER i LATCH

OUTPUT COMPARE FLAG i (OCFi)

OCMPi PIN (OLVLi=1)

64/157

1

ST7232A

16-BIT TIMER (Cont’d)

10.3.3.5 One Pulse Mode

Clearing the Input Capture interrupt request (i.e.

clearing the ICFi bit) is done in two steps:

One Pulse mode enables the generation of a

pulse when an external event occurs. This mode is

selected via the OPM bit in the CR2 register.

1. Reading the SR register while the ICFi bit is set.

2. An access (read or write) to the ICiLR register.

The one pulse mode uses the Input Capture1

function and the Output Compare1 function.

The OC1R register value required for a specific

timing application can be calculated using the fol-

lowing formula:

Procedure:

t f

To use one pulse mode:

* CPU

- 5

OCiR Value =

1. Load the OC1R register with the value corre-

sponding to the length of the pulse (see the for-

mula in the opposite column).

PRESC

Where:

t

= Pulse period (in seconds)

2. Select the following in the CR1 register:

f

= CPU clock frequency (in hertz)

CPU

– Using the OLVL1 bit, select the level to be ap-

plied to the OCMP1 pin after the pulse.

= Timer prescaler factor (2, 4 or 8 depend-

ing on the CC[1:0] bits, see Table 16

Clock Control Bits)

PRESC

– Using the OLVL2 bit, select the level to be ap-

plied to the OCMP1 pin during the pulse.

If the timer clock is an external clock the formula is:

– Select the edge of the active transition on the

ICAP1 pin with the IEDG1 bit (the ICAP1 pin

must be configured as floating input).

OCiR = t f_EXT-5

*

Where:

t

3. Select the following in the CR2 register:

= Pulse period (in seconds)

– Set the OC1E bit, the OCMP1 pin is then ded-

icated to the Output Compare 1 function.

f

= External timer clock frequency (in hertz)

EXT

– Set the OPM bit.

When the value of the counter is equal to the value

of the contents of the OC1R register, the OLVL1

bit is output on the OCMP1 pin, (See Figure 42).

– Select the timer clock CC[1:0] (see Table 16

Clock Control Bits).

Notes:

One pulse mode cycle

1. The OCF1 bit cannot be set by hardware in one

pulse mode but the OCF2 bit can generate an

Output Compare interrupt.

ICR1 = Counter

When

OCMP1 = OLVL2

event occurs

2. When the Pulse Width Modulation (PWM) and

One Pulse Mode (OPM) bits are both set, the

PWM mode is the only active one.

on ICAP1

Counter is reset

to FFFCh

3. If OLVL1=OLVL2 a continuous signal will be

seen on the OCMP1 pin.

ICF1 bit is set

When

4. The ICAP1 pin can not be used to perform input

capture. The ICAP2 pin can be used to perform

input capture (ICF2 can be set and IC2R can be

loaded) but the user must take care that the

counter is reset each time a valid edge occurs

on the ICAP1 pin and ICF1 can also generates

interrupt if ICIE is set.

Counter

OCMP1 = OLVL1

= OC1R

Then, on a valid event on the ICAP1 pin, the coun-

ter is initialized to FFFCh and OLVL2 bit is loaded

on the OCMP1 pin, the ICF1 bit is set and the val-

ue FFFDh is loaded in the IC1R register.

5. When one pulse mode is used OC1R is dedi-

cated to this mode. Nevertheless OC2R and

OCF2 can be used to indicate a period of time

has been elapsed but cannot generate an out-

put waveform because the level OLVL2 is dedi-

cated to the one pulse mode.

Because the ICF1 bit is set when an active edge

occurs, an interrupt can be generated if the ICIE

bit is set.

6. In Flash devices, Timer A OCF2 bit is forced by

hardware to 0.

65/157

1

ST7232A

16-BIT TIMER (Cont’d)

Figure 42. One Pulse Mode Timing Example

2ED3

01F8

IC1R

FFFC FFFD FFFE

2ED0 2ED1 2ED2

2ED3

FFFC FFFD

01F8

COUNTER

ICAP1

OLVL2

OLVL1

OLVL2

OCMP1

compare1

Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1

Figure 43. Pulse Width Modulation Mode Timing Example with 2 Output Compare Functions

2ED0 2ED1 2ED2

34E2 FFFC

FFFC FFFD FFFE

34E2

COUNTER

OCMP1

OLVL2

OLVL1

OLVL2

compare2

compare1

compare2

Note: OC1R=2ED0h, OC2R=34E2, OLVL1=0, OLVL2= 1

66/157

1

ST7232A

16-BIT TIMER (Cont’d)

10.3.3.6 Pulse Width Modulation Mode

If OLVL1=1 and OLVL2=0 the length of the posi-

tive pulse is the difference between the OC2R and

OC1R registers.

Pulse Width Modulation (PWM) mode enables the

generation of a signal with a frequency and pulse

length determined by the value of the OC1R and

OC2R registers.

If OLVL1=OLVL2 a continuous signal will be seen

on the OCMP1 pin.

Pulse Width Modulation mode uses the complete

Output Compare 1 function plus the OC2R regis-

ter, and so this functionality can not be used when

PWM mode is activated.

The OCiR register value required for a specific tim-

ing application can be calculated using the follow-

ing formula:

t _*f_CPU

- 5

OCiR Value =

In PWM mode, double buffering is implemented on

the output compare registers. Any new values writ-

ten in the OC1R and OC2R registers are taken

into account only at the end of the PWM period

(OC2) to avoid spikes on the PWM output pin

(OCMP1).

PRESC

Where:

t

= Signal or pulse period (in seconds)

= CPU clock frequency (in hertz)

f

CPU

= Timer prescaler factor (2, 4 or 8 depend-

ing on CC[1:0] bits, see Table 16)

PRESC

Procedure

If the timer clock is an external clock the formula is:

To use pulse width modulation mode:

OCiR = t f_EXT-5

1. Load the OC2R register with the value corre-

sponding to the period of the signal using the

formula in the opposite column.

*

Where:

t

f

= Signal or pulse period (in seconds)

2. Load the OC1R register with the value corre-

sponding to the period of the pulse if (OLVL1=0

and OLVL2=1) using the formula in the oppo-

site column.

= External timer clock frequency (in hertz)

EXT

The Output Compare 2 event causes the counter

to be initialized to FFFCh (See Figure 43)

3. Select the following in the CR1 register:

Notes:

– Using the OLVL1 bit, select the level to be ap-

plied to the OCMP1 pin after a successful

comparison with the OC1R register.

1. After a write instruction to the OCiHR register,

the output compare function is inhibited until the

OCiLR register is also written.

– Using the OLVL2 bit, select the level to be ap-

plied to the OCMP1 pin after a successful

comparison with the OC2R register.

2. The OCF1 and OCF2 bits cannot be set by

hardware in PWM mode therefore the Output

Compare interrupt is inhibited.

4. Select the following in the CR2 register:

3. The ICF1 bit is set by hardware when the coun-

ter reaches the OC2R value and can produce a

timer interrupt if the ICIE bit is set and the I bit is

cleared.

– Set OC1E bit: the OCMP1 pin is then dedicat-

ed to the output compare 1 function.

– Set the PWM bit.

4. In PWM mode the ICAP1 pin can not be used

to perform input capture because it is discon-

nected to the timer. The ICAP2 pin can be used

to perform input capture (ICF2 can be set and

IC2R can be loaded) but the user must take

care that the counter is reset each period and

ICF1 can also generates interrupt if ICIE is set.

– Select the timer clock (CC[1:0]) (see Table 16

Clock Control Bits).

Pulse Width Modulation cycle

When

Counter

= OC1R

OCMP1 = OLVL1

5. When the Pulse Width Modulation (PWM) and

One Pulse Mode (OPM) bits are both set, the

PWM mode is the only active one.

OCMP1 = OLVL2

When

Counter

= OC2R

Counter is reset

to FFFCh

ICF1 bit is set

67/157

1

ST7232A

16-BIT TIMER (Cont’d)

10.3.4 Low Power Modes

Mode

Description

No effect on 16-bit Timer.

Timer interrupts cause the device to exit from WAIT mode.

WAIT

16-bit Timer registers are frozen.

In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous

count when the MCU is woken up by an interrupt with “exit from HALT mode” capability or from the counter

reset value when the MCU is woken up by a RESET.

HALT

If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is armed. Consequent-

ly, when the MCU is woken up by an interrupt with “exit from HALT mode” capability, the ICFi bit is set, and

the counter value present when exiting from HALT mode is captured into the ICiR register.

10.3.5 Interrupts

Enable

Control from

Bit

Exit

from

Halt

Event

Flag

Interrupt Event

Wait

Yes

Input Capture 1 event/Counter reset in PWM mode

Input Capture 2 event

ICF1

ICF2

No

ICIE

Output Compare 1 event (not available in PWM mode)

Output Compare 2 event (not available in PWM mode)

Timer Overflow event

OCF1

OCF2

TOF

OCIE

TOIE

Note: The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts chap-

ter). These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt

mask in the CC register is reset (RIM instruction).

10.3.6 Summary of Timer modes

TIMER RESOURCES

MODES

Input Capture 1

Input Capture 2

Output Compare 1 Output Compare 2

2)

Input Capture (1 and/or 2)

Output Compare (1 and/or 2)

One Pulse Mode

Yes

No

Yes

No

Yes

1)

3)

2)

Not Recommended

Partially

No

PWM Mode

No

1) See note 4 in Section 10.3.3.5 One Pulse Mode

2) See note 5 and 6 in Section 10.3.3.5 One Pulse Mode

3) See note 4 in Section 10.3.3.6 Pulse Width Modulation Mode

68/157

1

ST7232A

16-BIT TIMER (Cont’d)

10.3.7 Register Description

Bit 4 = FOLV2 Forced Output Compare 2.

This bit is set and cleared by software.

0: No effect on the OCMP2 pin.

Each Timer is associated with three control and

status registers, and with six pairs of data registers

(16-bit values) relating to the two input captures,

the two output compares, the counter and the al-

ternate counter.

1:Forces the OLVL2 bit to be copied to the

OCMP2 pin, if the OC2E bit is set and even if

there is no successful comparison.

Bit 3 = FOLV1 Forced Output Compare 1.

This bit is set and cleared by software.

0: No effect on the OCMP1 pin.

CONTROL REGISTER 1 (CR1)

Read/Write

1: Forces OLVL1 to be copied to the OCMP1 pin, if

the OC1E bit is set and even if there is no suc-

cessful comparison.

Reset Value: 0000 0000 (00h)

7

0

ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1

Bit 2 = OLVL2 Output Level 2.

This bit is copied to the OCMP2 pin whenever a

successful comparison occurs with the OC2R reg-

ister and OCxE is set in the CR2 register. This val-

ue is copied to the OCMP1 pin in One Pulse Mode

and Pulse Width Modulation mode.

Bit 7 = ICIE Input Capture Interrupt Enable.

0: Interrupt is inhibited.

1: A timer interrupt is generated whenever the

ICF1 or ICF2 bit of the SR register is set.

Bit 6 = OCIE Output Compare Interrupt Enable.

0: Interrupt is inhibited.

1: A timer interrupt is generated whenever the

OCF1 or OCF2 bit of the SR register is set.

Bit 1 = IEDG1 Input Edge 1.

This bit determines which type of level transition

on the ICAP1 pin will trigger the capture.

0: A falling edge triggers the capture.

1: A rising edge triggers the capture.

Bit 5 = TOIE Timer Overflow Interrupt Enable.

0: Interrupt is inhibited.

1: A timer interrupt is enabled whenever the TOF

bit of the SR register is set.

Bit 0 = OLVL1 Output Level 1.

The OLVL1 bit is copied to the OCMP1 pin when-

ever a successful comparison occurs with the

OC1R register and the OC1E bit is set in the CR2

register.

69/157

1

ST7232A

16-BIT TIMER (Cont’d)

CONTROL REGISTER 2 (CR2)

Read/Write

Bit 4 = PWM Pulse Width Modulation.

0: PWM mode is not active.

1: PWM mode is active, the OCMP1 pin outputs a

programmable cyclic signal; the length of the

pulse depends on the value of OC1R register;

the period depends on the value of OC2R regis-

ter.

Reset Value: 0000 0000 (00h)

7

0

OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG

Bit 3, 2 = CC[1:0] Clock Control.

Bit 7 = OC1E Output Compare 1 Pin Enable.

This bit is used only to output the signal from the

timer on the OCMP1 pin (OLV1 in Output Com-

pare mode, both OLV1 and OLV2 in PWM and

one-pulse mode). Whatever the value of the OC1E

bit, the Output Compare 1 function of the timer re-

mains active.

0: OCMP1 pin alternate function disabled (I/O pin

free for general-purpose I/O).

1: OCMP1 pin alternate function enabled.

The timer clock mode depends on these bits:

Table 16. Clock Control Bits

Timer Clock

f_CPU/ 4

CC1

CC0

0

1

0

1

0

f_CPU/ 2

f_CPU/ 8

External Clock (where

available)

1

Bit 6 = OC2E Output Compare 2 Pin Enable.

This bit is used only to output the signal from the

timer on the OCMP2 pin (OLV2 in Output Com-

pare mode). Whatever the value of the OC2E bit,

the Output Compare 2 function of the timer re-

mains active.

0: OCMP2 pin alternate function disabled (I/O pin

free for general-purpose I/O).

1: OCMP2 pin alternate function enabled.

Note: If the external clock pin is not available, pro-

gramming the external clock configuration stops

the counter.

Bit 1 = IEDG2 Input Edge 2.

This bit determines which type of level transition

on the ICAP2 pin will trigger the capture.

0: A falling edge triggers the capture.

1: A rising edge triggers the capture.

Bit 5 = OPM One Pulse Mode.

0: One Pulse Mode is not active.

1: One Pulse Mode is active, the ICAP1 pin can be

used to trigger one pulse on the OCMP1 pin; the

active transition is given by the IEDG1 bit. The

length of the generated pulse depends on the

contents of the OC1R register.

Bit 0 = EXEDG External Clock Edge.

This bit determines which type of level transition

on the external clock pin EXTCLK will trigger the

counter register.

0: A falling edge triggers the counter register.

1: A rising edge triggers the counter register.

70/157

1

ST7232A

16-BIT TIMER (Cont’d)

CONTROL/STATUS REGISTER (CSR)

Read Only (except bit 2 R/W)

Reset Value: xxxx x0xx (xxh)

7

Note: Reading or writing the ACLR register does

not clear TOF.

Bit 4 = ICF2 Input Capture Flag 2.

0: No input capture (reset value).

1: An input capture has occurred on the ICAP2

pin. To clear this bit, first read the SR register,

then read or write the low byte of the IC2R

(IC2LR) register.

0

ICF1 OCF1 TOF ICF2 OCF2 TIMD

0

Bit 7 = ICF1 Input Capture Flag 1.

0: No input capture (reset value).

1: An input capture has occurred on the ICAP1 pin

or the counter has reached the OC2R value in

PWM mode. To clear this bit, first read the SR

register, then read or write the low byte of the

IC1R (IC1LR) register.

Bit 3 = OCF2 Output Compare Flag 2.

0: No match (reset value).

1: The content of the free running counter has

matched the content of the OC2R register. To

clear this bit, first read the SR register, then read

or write the low byte of the OC2R (OC2LR) reg-

ister.

Bit 6 = OCF1 Output Compare Flag 1.

0: No match (reset value).

1: The content of the free running counter has

matched the content of the OC1R register. To

clear this bit, first read the SR register, then read

or write the low byte of the OC1R (OC1LR) reg-

ister.

Bit 2 = TIMD Timer disable.

This bit is set and cleared by software. When set, it

freezes the timer prescaler and counter and disa-

bled the output functions (OCMP1 and OCMP2

pins) to reduce power consumption. Access to the

timer registers is still available, allowing the timer

configuration to be changed, or the counter reset,

while it is disabled.

Bit 5 = TOF Timer Overflow Flag.

0: No timer overflow (reset value).

1:The free running counter rolled over from FFFFh

to 0000h. To clear this bit, first read the SR reg-

ister, then read or write the low byte of the CR

(CLR) register.

0: Timer enabled

1: Timer prescaler, counter and outputs disabled

Bits 1:0 = Reserved, must be kept cleared.

71/157

1

ST7232A

16-BIT TIMER (Cont’d)

INPUT CAPTURE 1 HIGH REGISTER (IC1HR)

OUTPUT COMPARE

(OC1HR)

1

HIGH REGISTER

Read Only

Reset Value: Undefined

Read/Write

Reset Value: 1000 0000 (80h)

This is an 8-bit read only register that contains the

high part of the counter value (transferred by the

input capture 1 event).

This is an 8-bit register that contains the high part

of the value to be compared to the CHR register.

7

0

7

0

MSB

LSB

MSB

LSB

INPUT CAPTURE 1 LOW REGISTER (IC1LR)

OUTPUT COMPARE

(OC1LR)

1

LOW REGISTER

Read Only

Reset Value: Undefined

Read/Write

Reset Value: 0000 0000 (00h)

This is an 8-bit read only register that contains the

low part of the counter value (transferred by the in-

put capture 1 event).

This is an 8-bit register that contains the low part of

the value to be compared to the CLR register.

7

0

7

0

MSB

LSB

MSB

LSB

72/157

1

ST7232A

16-BIT TIMER (Cont’d)

OUTPUT COMPARE

(OC2HR)

2

HIGH REGISTER

COUNTER HIGH REGISTER (CHR)

Read Only

Reset Value: 1111 1111 (FFh)

Read/Write

Reset Value: 1000 0000 (80h)

This is an 8-bit register that contains the high part

of the counter value.

This is an 8-bit register that contains the high part

of the value to be compared to the CHR register.

7

0

7

0

MSB

LSB

MSB

LSB

COUNTER LOW REGISTER (CLR)

OUTPUT COMPARE

(OC2LR)

2

LOW REGISTER

Read Only

Reset Value: 1111 1100 (FCh)

Read/Write

Reset Value: 0000 0000 (00h)

This is an 8-bit register that contains the low part of

the counter value. A write to this register resets the

counter. An access to this register after accessing

the CSR register clears the TOF bit.

This is an 8-bit register that contains the low part of

the value to be compared to the CLR register.

7

0

7

0

MSB

LSB

MSB

LSB

73/157

1

ST7232A

16-BIT TIMER (Cont’d)

ALTERNATE COUNTER HIGH REGISTER

INPUT CAPTURE 2 HIGH REGISTER (IC2HR)

Read Only

(ACHR)

Read Only

Reset Value: 1111 1111 (FFh)

Reset Value: Undefined

This is an 8-bit read only register that contains the

high part of the counter value (transferred by the

Input Capture 2 event).

This is an 8-bit register that contains the high part

of the counter value.

7

0

7

0

MSB

LSB

MSB

LSB

ALTERNATE COUNTER LOW REGISTER

INPUT CAPTURE 2 LOW REGISTER (IC2LR)

Read Only

(ACLR)

Read Only

Reset Value: 1111 1100 (FCh)

Reset Value: Undefined

This is an 8-bit read only register that contains the

low part of the counter value (transferred by the In-

put Capture 2 event).

This is an 8-bit register that contains the low part of

the counter value. A write to this register resets the

counter. An access to this register after an access

to CSR register does not clear the TOF bit in the

CSR register.

7

0

MSB

LSB

7

0

MSB

LSB

74/157

1

ST7232A

16-BIT TIMER (Cont’d)

Table 17. 16-Bit Timer Register Map and Reset Values

Address

(Hex.)

Register

Label

7

6

5

4

3

2

1

0

Timer A: 32 CR1

Timer B: 42 Reset Value

ICIE

0

OCIE

0

TOIE

0

FOLV2

0

FOLV1

0

OLVL2

0

IEDG1

0

OLVL1

0

Timer A: 31 CR2

Timer B: 41 Reset Value

OC1E

0

OC2E

0

OPM

0

PWM

0

CC1

0

CC0

0

IEDG2

0

EXEDG

0

Timer A: 33 CSR

Timer B: 43 Reset Value

ICF1

x

OCF1

x

TOF

x

ICF2

x

OCF2

x

TIMD

0

-

x

-

x

Timer A: 34 IC1HR

Timer B: 44 Reset Value

MSB

x

LSB

x

0

1

x

0

1

x

0

1

x

0

1

x

0

1

x

0

1

0

1

0

x

Timer A: 35 IC1LR

Timer B: 45 Reset Value

MSB

x

LSB

x

Timer A: 36 OC1HR

Timer B: 46 Reset Value

MSB

1

LSB

0

Timer A: 37 OC1LR

Timer B: 47 Reset Value

MSB

0

LSB

0

Timer A: 3E OC2HR

Timer B: 4E Reset Value

MSB

1

LSB

0

Timer A: 3F OC2LR

Timer B: 4F Reset Value

MSB

0

LSB

0

Timer A: 38 CHR

Timer B: 48 Reset Value

MSB

1

LSB

1

Timer A: 39 CLR

Timer B: 49 Reset Value

MSB

1

LSB

0

Timer A: 3A ACHR

Timer B: 4A Reset Value

MSB

1

LSB

1

Timer A: 3B ACLR

Timer B: 4B Reset Value

MSB

1

LSB

0

Timer A: 3C IC2HR

Timer B: 4C Reset Value

MSB

x

LSB

x

Timer A: 3D IC2LR

Timer B: 4D Reset Value

MSB

x

LSB

x

75/157

1

ST7232A

10.4 SERIAL PERIPHERAL INTERFACE (SPI)

10.4.1 Introduction

Note: In slave mode, continuous transmission is

not possible at maximum frequency due to the

software overhead for clearing status flags and to

initiate the next transmission sequence.

The Serial Peripheral Interface (SPI) allows full-

duplex, synchronous, serial communication with

external devices. An SPI system may consist of a

master and one or more slaves however the SPI

interface can not be a master in a multi-master

system.

10.4.3 General Description

Figure 44 shows the serial peripheral interface

(SPI) block diagram. There are 3 registers:

10.4.2 Main Features

– SPI Control Register (SPICR)

– SPI Control/Status Register (SPICSR)

– SPI Data Register (SPIDR)

■ Full duplex synchronous transfers (on 3 lines)

■ Simplex synchronous transfers (on 2 lines)

■ Master or slave operation

The SPI is connected to external devices through

4 pins:

■ Six master mode frequencies (f

/4 max.)

CPU

■ f

/2 max. slave mode frequency (see note)

CPU

– MISO: Master In / Slave Out data

– MOSI: Master Out / Slave In data

■ SS Management by software or hardware

■ Programmable clock polarity and phase

■ End of transfer interrupt flag

– SCK: Serial Clock out by SPI masters and in-

put by SPI slaves

■ Write collision, Master Mode Fault and Overrun

flags

Figure 44. Serial Peripheral Interface Block Diagram

Data/Address Bus

Read

SPIDR

Interrupt

request

Read Buffer

MOSI

7

0

SPICSR

MISO

8-Bit Shift Register

SPIF WCOL OVR MODF

0

SOD SSM SSI

Write

SOD

bit

1

SS

SPI

STATE

0

SCK

CONTROL

7

0

SPICR

MSTR

SPR0

SPIE SPE SPR2

CPOL CPHA SPR1

MASTER

CONTROL

SERIAL CLOCK

GENERATOR

SS

76/157

1

ST7232A

SERIAL PERIPHERAL INTERFACE (Cont’d)

– SS: Slave select:

The communication is always initiated by the mas-

ter. When the master device transmits data to a

slave device via MOSI pin, the slave device re-

sponds by sending data to the master device via

the MISO pin. This implies full duplex communica-

tion with both data out and data in synchronized

with the same clock signal (which is provided by

the master device via the SCK pin).

This input signal acts as a ‘chip select’ to let

the SPI master communicate with slaves indi-

vidually and to avoid contention on the data

lines. Slave SS inputs can be driven by stand-

ard I/O ports on the master MCU.

10.4.3.1 Functional Description

A basic example of interconnections between a

single master and a single slave is illustrated in

Figure 45.

To use a single data line, the MISO and MOSI pins

must be connected at each node ( in this case only

simplex communication is possible).

The MOSI pins are connected together and the

MISO pins are connected together. In this way

data is transferred serially between master and

slave (most significant bit first).

Four possible data/clock timing relationships may

be chosen (see Figure 48) but master and slave

must be programmed with the same timing mode.

Figure 45. Single Master/ Single Slave Application

SLAVE

MASTER

MSBit

LSBit

MSBit

LSBit

MISO

MOSI

MISO

MOSI

8-BIT SHIFT REGISTER

SPI

CLOCK

GENERATOR

SCK

SS

SCK

SS

+5V

Not used if SS is managed

by software

77/157

1

ST7232A

SERIAL PERIPHERAL INTERFACE (Cont’d)

10.4.3.2 Slave Select Management

In Slave Mode:

As an alternative to using the SS pin to control the

Slave Select signal, the application can choose to

manage the Slave Select signal by software. This

is configured by the SSM bit in the SPICSR regis-

ter (see Figure 47)

There are two cases depending on the data/clock

timing relationship (see Figure 46):

If CPHA=1 (data latched on 2nd clock edge):

– SS internal must be held low during the entire

transmission. This implies that in single slave

applications the SS pin either can be tied to

In software management, the external SS pin is

free for other application uses and the internal SS

signal level is driven by writing to the SSI bit in the

SPICSR register.

V

, or made free for standard I/O by manag-

SS

ing the SS function by software (SSM= 1 and

SSI=0 in the in the SPICSR register)

If CPHA=0 (data latched on 1st clock edge):

In Master mode:

– SS internal must be held low during byte

transmission and pulled high between each

byte to allow the slave to write to the shift reg-

ister. If SS is not pulled high, a Write Collision

error will occur when the slave writes to the

shift register (see Section 10.4.5.3).

– SS internal must be held high continuously

Figure 46. Generic SS Timing Diagram

Byte 3

Byte 2

MOSI/MISO

Master SS

Byte 1

Slave SS

(if CPHA=0)

Slave SS

(if CPHA=1)

Figure 47. Hardware/Software Slave Select Management

SSM bit

SSI bit

1

0

SS internal

SS external pin

78/157

1

ST7232A

SERIAL PERIPHERAL INTERFACE (Cont’d)

10.4.3.3 Master Mode Operation

Note: While the SPIF bit is set, all writes to the

SPIDR register are inhibited until the SPICSR reg-

ister is read.

In master mode, the serial clock is output on the

SCK pin. The clock frequency, polarity and phase

are configured by software (refer to the description

of the SPICSR register).

10.4.3.5 Slave Mode Operation

In slave mode, the serial clock is received on the

SCK pin from the master device.

Note: The idle state of SCK must correspond to

the polarity selected in the SPICSR register (by

pulling up SCK if CPOL=1 or pulling down SCK if

CPOL=0).

To operate the SPI in slave mode:

1. Write to the SPICSR register to perform the fol-

lowing actions:

To operate the SPI in master mode, perform the

following steps in order (if the SPICSR register is

not written first, the SPICR register setting (MSTR

bit) may be not taken into account):

– Select the clock polarity and clock phase by

configuring the CPOL and CPHA bits (see

Figure 48).

Note: The slave must have the same CPOL

and CPHA settings as the master.

1. Write to the SPICR register:

– Manage the SS pin as described in Section

10.4.3.2 and Figure 46. If CPHA=1 SS must

be held low continuously. If CPHA=0 SS must

be held low during byte transmission and

pulled up between each byte to let the slave

write in the shift register.

– Select the clock frequency by configuring the

SPR[2:0] bits.

– Select the clock polarity and clock phase by

configuring the CPOL and CPHA bits. Figure

48 shows the four possible configurations.

Note: The slave must have the same CPOL

and CPHA settings as the master.

2. Write to the SPICR register to clear the MSTR

bit and set the SPE bit to enable the SPI I/O

functions.

2. Write to the SPICSR register:

– Either set the SSM bit and set the SSI bit or

clear the SSM bit and tie the SS pin high for

the complete byte transmit sequence.

10.4.3.6 Slave Mode Transmit Sequence

When software writes to the SPIDR register, the

data byte is loaded into the 8-bit shift register and

then shifted out serially to the MISO pin most sig-

nificant bit first.

3. Write to the SPICR register:

– Set the MSTR and SPE bits

Note: MSTR and SPE bits remain set only if

SS is high).

The transmit sequence begins when the slave de-

vice receives the clock signal and the most signifi-

cant bit of the data on its MOSI pin.

The transmit sequence begins when software

writes a byte in the SPIDR register.

10.4.3.4 Master Mode Transmit Sequence

When data transfer is complete:

– The SPIF bit is set by hardware

When software writes to the SPIDR register, the

data byte is loaded into the 8-bit shift register and

then shifted out serially to the MOSI pin most sig-

nificant bit first.

– An interrupt request is generated if SPIE bit is

set and interrupt mask in the CCR register is

cleared.

When data transfer is complete:

– The SPIF bit is set by hardware

Clearing the SPIF bit is performed by the following

software sequence:

– An interrupt request is generated if the SPIE

bit is set and the interrupt mask in the CCR

register is cleared.

1. An access to the SPICSR register while the

SPIF bit is set.

2. A write or a read to the SPIDR register.

Clearing the SPIF bit is performed by the following

software sequence:

Notes: While the SPIF bit is set, all writes to the

SPIDR register are inhibited until the SPICSR reg-

ister is read.

1. An access to the SPICSR register while the

SPIF bit is set

The SPIF bit can be cleared during a second

transmission; however, it must be cleared before

the second SPIF bit in order to prevent an Overrun

condition (see Section 10.4.5.2).

2. A read to the SPIDR register.

79/157

1

ST7232A

SERIAL PERIPHERAL INTERFACE (Cont’d)

10.4.4 Clock Phase and Clock Polarity

Figure 48, shows an SPI transfer with the four

combinations of the CPHA and CPOL bits. The di-

agram may be interpreted as a master or slave

timing diagram where the SCK pin, the MISO pin,

the MOSI pin are directly connected between the

master and the slave device.

Four possible timing relationships may be chosen

by software, using the CPOL and CPHA bits (See

Figure 48).

Note: The idle state of SCK must correspond to

the polarity selected in the SPICSR register (by

pulling up SCK if CPOL=1 or pulling down SCK if

CPOL=0).

Note: If CPOL is changed at the communication

byte boundaries, the SPI must be disabled by re-

setting the SPE bit.

The combination of the CPOL clock polarity and

CPHA (clock phase) bits selects the data capture

clock edge

Figure 48. Data Clock Timing Diagram

CPHA =1

SCK

(CPOL = 1)

SCK

(CPOL = 0)

Bit 4

Bit3

Bit 2

Bit 1

LSBit

MSBit Bit 6

Bit 5

MISO

(from master)

MOSI

(from slave)

SS

(to slave)

CAPTURE STROBE

CPHA =0

SCK

(CPOL = 1)

SCK

(CPOL = 0)

Bit 4

Bit3

Bit 2

Bit 1

LSBit

MISO

(from master)

MSBit Bit 6

Bit 5

Bit3

MOSI

(from slave)

SS

(to slave)

CAPTURE STROBE

Note: This figure should not be used as a replacement for parametric information.

Refer to the Electrical Characteristics chapter.

80/157

1

ST7232A

SERIAL PERIPHERAL INTERFACE (Cont’d)

10.4.5 Error Flags

not cleared the SPIF bit issued from the previously

transmitted byte.

10.4.5.1 Master Mode Fault (MODF)

When an Overrun occurs:

Master mode fault occurs when the master device

has its SS pin pulled low.

– The OVR bit is set and an interrupt request is

generated if the SPIE bit is set.

When a Master mode fault occurs:

In this case, the receiver buffer contains the byte

sent after the SPIF bit was last cleared. A read to

the SPIDR register returns this byte. All other

bytes are lost.

– The MODF bit is set and an SPI interrupt re-

quest is generated if the SPIE bit is set.

– The SPE bit is reset. This blocks all output

from the device and disables the SPI periph-

eral.

The OVR bit is cleared by reading the SPICSR

register.

– The MSTR bit is reset, thus forcing the device

into slave mode.

10.4.5.3 Write Collision Error (WCOL)

A write collision occurs when the software tries to

write to the SPIDR register while a data transfer is

taking place with an external device. When this

happens, the transfer continues uninterrupted;

and the software write will be unsuccessful.

Clearing the MODF bit is done through a software

sequence:

1. A read access to the SPICSR register while the

MODF bit is set.

2. A write to the SPICR register.

Write collisions can occur both in master and slave

mode. See also Section 10.4.3.2 Slave Select

Management.

Notes: To avoid any conflicts in an application

with multiple slaves, the SS pin must be pulled

high during the MODF bit clearing sequence. The

SPE and MSTR bits may be restored to their orig-

inal state during or after this clearing sequence.

Note: a "read collision" will never occur since the

received data byte is placed in a buffer in which

access is always synchronous with the MCU oper-

ation.

Hardware does not allow the user to set the SPE

and MSTR bits while the MODF bit is set except in

the MODF bit clearing sequence.

The WCOL bit in the SPICSR register is set if a

write collision occurs.

10.4.5.2 Overrun Condition (OVR)

No SPI interrupt is generated when the WCOL bit

is set (the WCOL bit is a status flag only).

An overrun condition occurs, when the master de-

vice has sent a data byte and the slave device has

Clearing the WCOL bit is done through a software

sequence (see Figure 49).

Figure 49. Clearing the WCOL bit (Write Collision Flag) Software Sequence

Clearing sequence after SPIF = 1 (end of a data byte transfer)

Read SPICSR

1st Step

RESULT

SPIF =0

WCOL=0

2nd Step

Read SPIDR

Clearing sequence before SPIF = 1 (during a data byte transfer)

Read SPICSR

1st Step

Note: Writing to the SPIDR regis-

ter instead of reading it does not

reset the WCOL bit

RESULT

2nd Step

Read SPIDR

WCOL=0

81/157

1

ST7232A

SERIAL PERIPHERAL INTERFACE (Cont’d)

10.4.5.4 Single Master Systems

Note: To prevent a bus conflict on the MISO line

the master allows only one active slave device

during a transmission.

A typical single master system may be configured,

using an MCU as the master and four MCUs as

slaves (see Figure 50).

For more security, the slave device may respond

to the master with the received data byte. Then the

master will receive the previous byte back from the

slave device if all MISO and MOSI pins are con-

nected and the slave has not written to its SPIDR

register.

The master device selects the individual slave de-

vices by using four pins of a parallel port to control

the four SS pins of the slave devices.

The SS pins are pulled high during reset since the

master device ports will be forced to be inputs at

that time, thus disabling the slave devices.

Other transmission security methods can use

ports for handshake lines or data bytes with com-

mand fields.

Figure 50. Single Master / Multiple Slave Configuration

SS

SCK

Slave

SCK

Slave

MCU

SCK

Slave

MCU

Slave

MCU

MOSI MISO

SCK

Master

MCU

5V

SS

82/157

1

ST7232A

SERIAL PERIPHERAL INTERFACE (Cont’d)

10.4.6 Low Power Modes

Note: When waking up from Halt mode, if the SPI

remains in Slave mode, it is recommended to per-

form an extra communications cycle to bring the

SPI from Halt mode state to normal state. If the

SPI exits from Slave mode, it returns to normal

state immediately.

Mode

Description

No effect on SPI.

WAIT

SPI interrupt events cause the device to exit

from WAIT mode.

SPI registers are frozen.

Caution: The SPI can wake up the ST7 from Halt

mode only if the Slave Select signal (external SS

pin or the SSI bit in the SPICSR register) is low

when the ST7 enters Halt mode. So if Slave selec-

tion is configured as external (see Section

10.4.3.2), make sure the master drives a low level

on the SS pin when the slave enters Halt mode.

In HALT mode, the SPI is inactive. SPI oper-

ation resumes when the MCU is woken up by

an interrupt with “exit from HALT mode” ca-

pability. The data received is subsequently

read from the SPIDR register when the soft-

ware is running (interrupt vector fetching). If

several data are received before the wake-

up event, then an overrun error is generated.

This error can be detected after the fetch of

the interrupt routine that woke up the device.

HALT

10.4.7 Interrupts

Enable

Control from

Bit

Exit

from

Halt

Event

Flag

Interrupt Event

Wait

10.4.6.1 Using the SPI to wakeup the MCU from

Halt mode

SPI End of Transfer

Event

SPIF

Yes

In slave configuration, the SPI is able to wakeup

the ST7 device from HALT mode through a SPIF

interrupt. The data received is subsequently read

from the SPIDR register when the software is run-

ning (interrupt vector fetch). If multiple data trans-

fers have been performed before software clears

the SPIF bit, then the OVR bit is set by hardware.

Master Mode Fault

Event

SPIE

MODF

OVR

Yes

No

Overrun Error

Note: The SPI interrupt events are connected to

the same interrupt vector (see Interrupts chapter).

They generate an interrupt if the corresponding

Enable Control Bit is set and the interrupt mask in

83/157

1

ST7232A

SERIAL PERIPHERAL INTERFACE (Cont’d)

10.4.8 Register Description

CONTROL REGISTER (SPICR)

Read/Write

Bit 3 = CPOL Clock Polarity.

This bit is set and cleared by software. This bit de-

termines the idle state of the serial Clock. The

CPOL bit affects both the master and slave

modes.

Reset Value: 0000 xxxx (0xh)

7

0

SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0

0: SCK pin has a low level idle state

1: SCK pin has a high level idle state

Note: If CPOL is changed at the communication

byte boundaries, the SPI must be disabled by re-

setting the SPE bit.

Bit 7 = SPIE Serial Peripheral Interrupt Enable.

This bit is set and cleared by software.

0: Interrupt is inhibited

1: An SPI interrupt is generated whenever

SPIF=1, MODF=1 or OVR=1 in the SPICSR

register

Bit 2 = CPHA Clock Phase.

This bit is set and cleared by software.

0: The first clock transition is the first data capture

edge.

1: The second clock transition is the first capture

edge.

Bit 6 = SPE Serial Peripheral Output Enable.

This bit is set and cleared by software. It is also

cleared by hardware when, in master mode, SS=0

(see Section 10.4.5.1 Master Mode Fault

(MODF)). The SPE bit is cleared by reset, so the

SPI peripheral is not initially connected to the ex-

ternal pins.

Note: The slave must have the same CPOL and

CPHA settings as the master.

Bits 1:0 = SPR[1:0] Serial Clock Frequency.

These bits are set and cleared by software. Used

with the SPR2 bit, they select the baud rate of the

SPI serial clock SCK output by the SPI in master

mode.

0: I/O pins free for general purpose I/O

1: SPI I/O pin alternate functions enabled

Bit 5 = SPR2 Divider Enable.

Note: These 2 bits have no effect in slave mode.

This bit is set and cleared by software and is

cleared by reset. It is used with the SPR[1:0] bits to

set the baud rate. Refer to Table 18 SPI Master

mode SCK Frequency.

Table 18. SPI Master mode SCK Frequency

Serial Clock

SPR2 SPR1 SPR0

0: Divider by 2 enabled

1: Divider by 2 disabled

f

/4

/8

1

0

1

0

1

0

1

0

1

CPU

Note: This bit has no effect in slave mode.

f

/16

/32

/64

CPU

Bit 4 = MSTR Master Mode.

This bit is set and cleared by software. It is also

cleared by hardware when, in master mode, SS=0

(see Section 10.4.5.1 Master Mode Fault

(MODF)).

f

/128

CPU

0: Slave mode

1: Master mode. The function of the SCK pin

changes from an input to an output and the func-

tions of the MISO and MOSI pins are reversed.

84/157

1

ST7232A

SERIAL PERIPHERAL INTERFACE (Cont’d)

CONTROL/STATUS REGISTER (SPICSR)

Read/Write (some bits Read Only)

Reset Value: 0000 0000 (00h)

Bit 3 = Reserved, must be kept cleared.

Bit 2 = SOD SPI Output Disable.

7

0

This bit is set and cleared by software. When set, it

disables the alternate function of the SPI output

(MOSI in master mode / MISO in slave mode)

0: SPI output enabled (if SPE=1)

SPIF

WCOL OVR MODF

-

SOD SSM SSI

1: SPI output disabled

Bit 7 = SPIF Serial Peripheral Data Transfer Flag

(Read only).

Bit 1 = SSM SS Management.

This bit is set by hardware when a transfer has

been completed. An interrupt is generated if

SPIE=1 in the SPICR register. It is cleared by a

software sequence (an access to the SPICSR

register followed by a write or a read to the

SPIDR register).

This bit is set and cleared by software. When set, it

disables the alternate function of the SPI SS pin

and uses the SSI bit value instead. See Section

10.4.3.2 Slave Select Management.

0: Hardware management (SS managed by exter-

nal pin)

0: Data transfer is in progress or the flag has been

cleared.

1: Data transfer between the device and an exter-

nal device has been completed.

1: Software management (internal SS signal con-

trolled by SSI bit. External SS pin free for gener-

al-purpose I/O)

Note: While the SPIF bit is set, all writes to the

SPIDR register are inhibited until the SPICSR reg-

ister is read.

Bit 0 = SSI SS Internal Mode.

This bit is set and cleared by software. It acts as a

‘chip select’ by controlling the level of the SS slave

select signal when the SSM bit is set.

0 : Slave selected

Bit 6 = WCOL Write Collision status (Read only).

This bit is set by hardware when a write to the

SPIDR register is done during a transmit se-

quence. It is cleared by a software sequence (see

Figure 49).

0: No write collision occurred

1: A write collision has been detected

1 : Slave deselected

DATA I/O REGISTER (SPIDR)

Read/Write

Reset Value: Undefined

7

0

Bit 5 = OVR SPI Overrun error (Read only).

This bit is set by hardware when the byte currently

being received in the shift register is ready to be

transferred into the SPIDR register while SPIF = 1

(See Section 10.4.5.2). An interrupt is generated if

SPIE = 1 in SPICR register. The OVR bit is cleared

by software reading the SPICSR register.

0: No overrun error

D7

D6

D5

D4

D3

D2

D1

D0

The SPIDR register is used to transmit and receive

data on the serial bus. In a master device, a write

to this register will initiate transmission/reception

of another byte.

1: Overrun error detected

Notes: During the last clock cycle the SPIF bit is

set, a copy of the received data byte in the shift

register is moved to a buffer. When the user reads

the serial peripheral data I/O register, the buffer is

actually being read.

Bit 4 = MODF Mode Fault flag (Read only).

This bit is set by hardware when the SS pin is

pulled low in master mode (see Section 10.4.5.1

Master Mode Fault (MODF)). An SPI interrupt can

be generated if SPIE=1 in the SPICSR register.

This bit is cleared by a software sequence (An ac-

cess to the SPICR register while MODF=1 fol-

lowed by a write to the SPICR register).

While the SPIF bit is set, all writes to the SPIDR

register are inhibited until the SPICSR register is

read.

Warning: A write to the SPIDR register places

data directly into the shift register for transmission.

0: No master mode fault detected

1: A fault in master mode has been detected

A read to the SPIDR register returns the value lo-

cated in the buffer and not the content of the shift

register (see Figure 44).

85/157

1

ST7232A

SERIAL PERIPHERAL INTERFACE (Cont’d)

Table 19. SPI Register Map and Reset Values

Address

(Hex.)

Register

Label

7

6

5

4

3

2

1

0

SPIDR

Reset Value

MSB

x

LSB

x

0021h

0022h

0023h

x

SPICR

Reset Value

SPIE

0

SPE

0

SPR2

0

MSTR

0

CPOL

x

CPHA

x

SPR1

x

SPR0

x

SPICSR

Reset Value

SPIF

0

WCOL

0

OR

0

MODF

0

SOD

0

SSM

0

SSI

0

86/157

1

ST7232A

10.5 SERIAL COMMUNICATIONS INTERFACE (SCI)

10.5.1 Introduction

10.5.3 General Description

The Serial Communications Interface (SCI) offers

a flexible means of full-duplex data exchange with

external equipment requiring an industry standard

NRZ asynchronous serial data format. The SCI of-

fers a very wide range of baud rates using two

baud rate generator systems.

The interface is externally connected to another

device by two pins (see Figure 52):

– TDO: Transmit Data Output. When the transmit-

ter and the receiver are disabled, the output pin

returns to its I/O port configuration. When the

transmitter and/or the receiver are enabled and

nothing is to be transmitted, the TDO pin is at

high level.

10.5.2 Main Features

■ Full duplex, asynchronous communications

■ NRZ standard format (Mark/Space)

■ Dual baud rate generator systems

– RDI: Receive Data Input is the serial data input.

Oversampling techniques are used for data re-

covery by discriminating between valid incoming

data and noise.

■ Independently programmable transmit and

receive baud rates up to 500K baud.

Through these pins, serial data is transmitted and

received as frames comprising:

■ Programmable data word length (8 or 9 bits)

■ Receive buffer full, Transmit buffer empty and

– An Idle Line prior to transmission or reception

– A start bit

End of Transmission flags

■ Two receiver wake-up modes:

– Address bit (MSB)

– A data word (8 or 9 bits) least significant bit first

– A Stop bit indicating that the frame is complete.

Thisinterfaceusestwotypesofbaudrategenerator:

– Idle line

■ Mutingfunctionformultiprocessorconfigurations

– A conventional type for commonly-used baud

rates,

■ Separate enable bits for Transmitter and

Receiver

– An extended type with a prescaler offering a very

wide range of baud rates even with non-standard

oscillator frequencies.

■ Four error detection flags:

– Overrun error

– Noise error

– Frame error

– Parity error

■ Five interrupt sources with flags:

– Transmit data register empty

– Transmission complete

– Receive data register full

– Idle line received

– Overrun error detected

■ Parity control:

– Transmits parity bit

– Checks parity of received data byte

■ Reduced power consumption mode

87/157

1

ST7232A

SERIAL COMMUNICATIONS INTERFACE (Cont’d)

Figure 51. SCI Block Diagram

Write

Read

(DATA REGISTER) DR

Received Data Register (RDR)

Received Shift Register

Transmit Data Register (TDR)

TDO

Transmit Shift Register

RDI

CR1

R8 T8 SCID

M WAKE PCE PS PIE

WAKE

UP

TRANSMIT

CONTROL

RECEIVER

CLOCK

RECEIVER

CONTROL

UNIT

CR2

SR

TIE TCIE RIE ILIE TE RE RWU SBK

TDRE TC RDRF IDLE OR NF FE

PE

SCI

INTERRUPT

CONTROL

TRANSMITTER

CLOCK

TRANSMITTER RATE

CONTROL

f

CPU

/PR

/16

BRR

SCP1

SCT2

SCT1SCT0SCR2 SCR1SCR0

SCP0

RECEIVER RATE

CONTROL

CONVENTIONAL BAUD RATE GENERATOR

88/157

1

ST7232A

SERIAL COMMUNICATIONS INTERFACE (Cont’d)

10.5.4 Functional Description

10.5.4.1 Serial Data Format

The block diagram of the Serial Control Interface,

is shown in Figure 51. It contains 6 dedicated reg-

isters:

Word length may be selected as being either 8 or 9

bits by programming the M bit in the SCICR1 reg-

ister (see Figure 51).

– Two control registers (SCICR1 & SCICR2)

– A status register (SCISR)

The TDO pin is in low state during the start bit.

The TDO pin is in high state during the stop bit.

– A baud rate register (SCIBRR)

An Idle character is interpreted as an entire frame

of “1”s followed by the start bit of the next frame

which contains data.

– An extended prescaler receiver register (SCIER-

PR)

A Break character is interpreted on receiving “0”s

for some multiple of the frame period. At the end of

the last break frame the transmitter inserts an ex-

tra “1” bit to acknowledge the start bit.

– An extended prescaler transmitter register (SCI-

ETPR)

Refer to the register descriptions in Section

10.5.7for the definitions of each bit.

Transmission and reception are driven by their

own baud rate generator.

Figure 52. Word Length Programming

9-bit Word length (M bit is set)

Possible

Next Data Frame

Parity

Data Frame

Start

Bit

Stop

Bit

Bit2

Bit6

Bit3

Bit4

Bit5

Bit7

Bit8

Bit0 Bit1

Bit

Start

Bit

Idle Frame

Start

Bit

Extra

’1’

Break Frame

8-bit Word length (M bit is reset)

Possible

Parity

Next Data Frame

Data Frame

Bit

Start

Bit

Stop

Bit

Bit2

Bit1

Bit3

Bit4

Bit5

Bit6

Bit0

Bit7

Start

Bit

Idle Frame

Start

Bit

Extra

’1’

Break Frame

89/157

1

ST7232A

SERIAL COMMUNICATIONS INTERFACE (Cont’d)

10.5.4.2 Transmitter

When a frame transmission is complete (after the

stop bit) the TC bit is set and an interrupt is gener-

ated if the TCIE is set and the I bit is cleared in the

CCR register.

The transmitter can send data words of either 8 or

9 bits depending on the M bit status. When the M

bit is set, word length is 9 bits and the 9th bit (the

MSB) has to be stored in the T8 bit in the SCICR1

register.

Clearing the TC bit is performed by the following

software sequence:

1. An access to the SCISR register

2. A write to the SCIDR register

Character Transmission

During an SCI transmission, data shifts out least

significant bit first on the TDO pin. In this mode,

the SCIDR register consists of a buffer (TDR) be-

tween the internal bus and the transmit shift regis-

ter (see Figure 51).

Note: The TDRE and TC bits are cleared by the

same software sequence.

Break Characters

Setting the SBK bit loads the shift register with a

break character. The break frame length depends

on the M bit (see Figure 52).

Procedure

– Select the M bit to define the word length.

As long as the SBK bit is set, the SCI send break

frames to the TDO pin. After clearing this bit by

software the SCI insert a logic 1 bit at the end of

the last break frame to guarantee the recognition

of the start bit of the next frame.

– Select the desired baud rate using the SCIBRR

and the SCIETPR registers.

– Set the TE bit to assign the TDO pin to the alter-

nate function and to send a idle frame as first

transmission.

Idle Characters

– Access the SCISR register and write the data to

send in the SCIDR register (this sequence clears

the TDRE bit). Repeat this sequence for each

data to be transmitted.

Setting the TE bit drives the SCI to send an idle

frame before the first data frame.

Clearing and then setting the TE bit during a trans-

mission sends an idle frame after the current word.

Clearing the TDRE bit is always performed by the

following software sequence:

1. An access to the SCISR register

2. A write to the SCIDR register

Note: Resetting and setting the TE bit causes the

data in the TDR register to be lost. Therefore the

best time to toggle the TE bit is when the TDRE bit

is set i.e. before writing the next byte in the SCIDR.

The TDRE bit is set by hardware and it indicates:

– The TDR register is empty.

– The data transfer is beginning.

– The next data can be written in the SCIDR regis-

ter without overwriting the previous data.

This flag generates an interrupt if the TIE bit is set

and the I bit is cleared in the CCR register.

When a transmission is taking place, a write in-

struction to the SCIDR register stores the data in

the TDR register and which is copied in the shift

register at the end of the current transmission.

When no transmission is taking place, a write in-

struction to the SCIDR register places the data di-

rectly in the shift register, the data transmission

starts, and the TDRE bit is immediately set.

90/157

1

ST7232A

SERIAL COMMUNICATIONS INTERFACE (Cont’d)

10.5.4.3 Receiver

RDR register as long as the RDRF bit is not

cleared.

The SCI can receive data words of either 8 or 9

bits. When the M bit is set, word length is 9 bits

and the MSB is stored in the R8 bit in the SCICR1

register.

When a overrun error occurs:

– The OR bit is set.

– The RDR content will not be lost.

– The shift register will be overwritten.

Character reception

During a SCI reception, data shifts in least signifi-

cant bit first through the RDI pin. In this mode, the

SCIDR register consists or a buffer (RDR) be-

tween the internal bus and the received shift regis-

ter (see Figure 51).

– An interrupt is generated if the RIE bit is set and

the I bit is cleared in the CCR register.

The OR bit is reset by an access to the SCISR reg-

ister followed by a SCIDR register read operation.

Procedure

Noise Error

– Select the M bit to define the word length.

Oversampling techniques are used for data recov-

ery by discriminating between valid incoming data

and noise. Normal data bits are considered valid if

three consecutive samples (8th, 9th, 10th) have

the same bit value, otherwise the NF flag is set. In

the case of start bit detection, the NF flag is set on

the basis of an algorithm combining both valid

edge detection and three samples (8th, 9th, 10th).

Therefore, to prevent the NF flag getting set during

start bit reception, there should be a valid edge de-

tection as well as three valid samples.

– Select the desired baud rate using the SCIBRR

and the SCIERPR registers.

– Set the RE bit, this enables the receiver which

begins searching for a start bit.

When a character is received:

– The RDRF bit is set. It indicates that the content

of the shift register is transferred to the RDR.

– An interrupt is generated if the RIE bit is set and

the I bit is cleared in the CCR register.

When noise is detected in a frame:

– The error flags can be set if a frame error, noise

or an overrun error has been detected during re-

ception.

– The NF flag is set at the rising edge of the RDRF

bit.

– Data is transferred from the Shift register to the

SCIDR register.

Clearing the RDRF bit is performed by the following

software sequence done by:

– No interrupt is generated. However this bit rises

at the same time as the RDRF bit which itself

generates an interrupt.

1. An access to the SCISR register

2. A read to the SCIDR register.

The RDRF bit must be cleared before the end of the

reception of the next character to avoid an overrun

error.

The NF flag is reset by a SCISR register read op-

eration followed by a SCIDR register read opera-

tion.

Break Character

During reception, if a false start bit is detected (e.g.

8th, 9th, 10th samples are 011,101,110), the

frame is discarded and the receiving sequence is

not started for this frame. There is no RDRF bit set

for this frame and the NF flag is set internally (not

accessible to the user). This NF flag is accessible

along with the RDRF bit when a next valid frame is

received.

When a break character is received, the SPI han-

dles it as a framing error.

Idle Character

When a idle frame is detected, there is the same

procedure as a data received character plus an in-

terrupt if the ILIE bit is set and the I bit is cleared in

the CCR register.

Note: If the application Start Bit is not long enough

to match the above requirements, then the NF

Flag may get set due to the short Start Bit. In this

case, the NF flag may be ignored by the applica-

tion software when the first valid byte is received.

Overrun Error

An overrun error occurs when a character is re-

ceived when RDRF has not been reset. Data can

not be transferred from the shift register to the


型号：	ST7232AJ2BC
厂家：	ST
描述：	8-BIT MICROCONTROLLER WITH 8K FLASH/ROM, ADC, 4 TIMERS, SPI, SCI INTERFACE 具有8K闪存/ ROM ， ADC ， 4个定时器， SPI ， SCI接口8位微控制器闪存微控制器
文件：	总157页 (文件大小：1415K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ST7232AJ2BC [STMICROELECTRONICS]

相关型号：

ST7232AJ2T1

ST7232AJ2T5

ST7232AJ2T6A

ST7232AJ2TA/XXX

ST7232AJ2TA/XXXRE

ST7232AJ2TB

ST7232AJ2TC

ST7232AK1

ST7232AK1B1

ST7232AK1B5

ST7232AK1B6

ST7232AK1B6A