ST72344XX [STMICROELECTRONICS]
SCI asynchronous serial interface;型号: | ST72344XX |
厂家: | ST |
描述: | SCI asynchronous serial interface |
文件: | 总247页 (文件大小:1998K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ST72344xx, ST72345xx
8-bit MCU with up to 16 Kbytes Flash memory, 10-bit ADC,
two 16-bit timers, two I2C, SPI, SCI
Datasheet −production data
Features
■ Memories
– up to 16 Kbytes Program memory: single
voltage extended Flash (XFlash) with read-
out and write protection, in-circuit and in-
application programming (ICP and IAP).
10,000 write/erase cycles guaranteed, data
retention: 20 years at 55 °C.
LQFP48
7 x 7 mm
LQFP32
7 × 7 mm
LQFP44
10 × 10 mm
– 16-bit timer B with: 2 input captures, 2
output compares, PWM and pulse
generator modes
– up to 1 Kbyte RAM
– 256 bytes data EEPROM with readout
protection. 300,000 write/erase cycles
guaranteed, data retention: 20 years at
55 °C.
■ 3 communication interfaces
2
– I C multimaster / slave
2
– I C slave 3 addresses, no stretch, with
DMA access and byte pair coherency on
I²C read
■ Clock, reset and supply management
– Power on / power off safe reset with
3 programmable threshold levels (LVD)
– SCI asynchronous serial interface (LIN
compatible)
– Auxiliary voltage detector (AVD)
– SPI synchronous serial interface
– Clock sources: crystal/ceramic resonator
oscillators, high-accuracy internal RC
oscillator or external clock
■ 1 analog peripheral
– 10-bit ADC with 12 input channels (8 on 32-
pin devices)
– PLL for 4x or 8x frequency multiplication
■ Instruction set
– 5 power-saving modes: Slow, Wait, Halt,
Auto-wakeup from Halt and Active-halt
– 8-bit data manipulation
– 63 basic instructions with illegal opcode
detection
– Clock output capability (f
)
CPU
■ Interrupt management
– 17 main addressing modes
– Nested interrupt controller
– 8 x 8 unsigned multiply instruction
– 10 interrupt vectors plus TRAP and RESET
– 9 external interrupt lines on 4 vectors
■ Development tools
– Full hardware/software development
package
■ Up to 34 I/O ports
– up to 34 multifunctional bidirectional I/O
lines
– On-chip debug module
– up to 12 high sink outputs (10 on 32-pin
devices)
Table 1.
Device summary
Part numbers
References
■ 4 timers
ST72344K2, ST72344K4,
ST72344S2, ST72344S4
– Configurable window watchdog timer
– Real-time base
ST72344xx
ST72345xx
ST72345C4
– 16-bit timer A with: 1 input capture, 1 output
compare, external clock input, PWM and
pulse generator modes
July 2012
Doc ID 12321 Rev 6
1/247
This is information on a product in full production.
www.st.com
1
Contents
ST72344xx, ST2345xx
Contents
1
2
3
4
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Register and memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.1
4.2
4.3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Programming modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.3.1
4.3.2
In-circuit programming (ICP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
In-application programming (IAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.4
4.5
ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.5.1
4.5.2
Readout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Flash write/erase protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.6
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.6.1
Flash control/status register (FCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5
Data EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.1
5.2
5.3
5.4
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Memory access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.4.1
5.4.2
5.4.3
Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Active-halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.5
5.6
5.7
Access error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Data EEPROM readout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.7.1
EEPROM control/status register (EECSR) . . . . . . . . . . . . . . . . . . . . . . 35
6
Central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
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Contents
6.1
6.2
6.3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.3.1
6.3.2
Condition code register (CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Stack pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7
Supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7.1
7.2
7.3
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Phase locked loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Multioscillator (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
7.3.1
7.3.2
7.3.3
External clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Crystal/ceramic oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Internal RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
7.4
7.5
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
7.4.1
7.4.2
RC control register (RCCRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
RC control register (RCCRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Reset sequence manager (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
7.5.1
7.5.2
7.5.3
7.5.4
7.5.5
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Asynchronous external RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
External power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Internal low-voltage detector (LVD) reset . . . . . . . . . . . . . . . . . . . . . . . . 48
Internal watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
7.6
System integrity management (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
7.6.1
7.6.2
7.6.3
7.6.4
7.6.5
Low-voltage detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Auxiliary-voltage detector (AVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
8
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
8.1
8.2
8.3
8.4
8.5
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Masking and processing flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Interrupts and low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Concurrent & nested management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Interrupt register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
8.5.1
CPU CC register interrupt bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
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8.5.2
Interrupt software priority registers (ISPRX) . . . . . . . . . . . . . . . . . . . . . 58
8.6
8.7
External interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
8.6.1
I/O port interrupt sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
External interrupt control register (EICR) . . . . . . . . . . . . . . . . . . . . . . . . . 61
9
Power-saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
9.1
9.2
9.3
9.4
9.5
9.6
9.7
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Active-halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Auto-wakeup from Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
9.7.1
9.7.2
AWUFH control/status register (AWUCSR) . . . . . . . . . . . . . . . . . . . . . . 72
AWUFH prescaler register (AWUPR) . . . . . . . . . . . . . . . . . . . . . . . . . . 73
10
I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
10.2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
10.2.1 Input modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
10.2.2 Output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
10.2.3 Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
10.3 I/O port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
10.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
10.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
10.5.1 I/O port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
11
On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
11.1 Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
11.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
11.1.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
11.1.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
11.1.4 Using Halt mode with the WDG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
11.1.5 How to program the watchdog timeout . . . . . . . . . . . . . . . . . . . . . . . . . 84
11.1.6 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
11.1.7 Hardware watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
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11.1.8 Using Halt mode with the WDG (WDGHALT option) . . . . . . . . . . . . . . . 87
11.1.9 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
11.1.10 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
11.2 Main clock controller with real-time clock and beeper (MCC/RTC) . . . . . 88
11.2.1 Programmable CPU clock prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
11.2.2 Clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
11.2.3 Real-time clock timer (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
11.2.4 Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
11.2.5 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
11.2.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
11.2.7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
11.3 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
11.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
11.3.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
11.3.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
11.3.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
11.3.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
11.3.6 Summary of timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
11.3.7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
11.4 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
11.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
11.4.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
11.4.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
11.4.4 Clock phase and clock polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
11.4.5 Error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
11.4.6 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
11.4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
11.4.8 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
11.5 SCI serial communication interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
11.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
11.5.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
11.5.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
11.5.4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
11.5.5 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
11.5.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
11.5.7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
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11.6 I2C bus interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
11.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
11.6.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
11.6.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
11.6.4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
11.6.5 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
11.6.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
11.6.7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
11.7 I2C triple slave interface with DMA (I2C3S) . . . . . . . . . . . . . . . . . . . . . . 167
11.7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
11.7.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
11.7.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
11.7.4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
11.7.5 Address handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
11.7.6 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
11.7.7 Interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
11.7.8 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
11.8 10-bit A/D converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
11.8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
11.8.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
11.8.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
11.8.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
11.8.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
11.8.6 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
12
Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
12.1 ST7 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
12.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
12.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
12.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
12.1.4 Indexed (No Offset, Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
12.1.5 Indirect (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
12.1.6 Indirect Indexed (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
12.1.7 Relative Mode (direct, indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
12.2 Instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
12.2.1 Illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
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Contents
13
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
13.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
13.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
13.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
13.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
13.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
13.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
13.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
13.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
13.4 Internal RC oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
13.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
13.6 Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
13.6.1 Crystal and ceramic resonator oscillators . . . . . . . . . . . . . . . . . . . . . . 210
13.7 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
13.8 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
13.8.1 Functional EMS (electromagnetic susceptibility) . . . . . . . . . . . . . . . . . 213
13.8.2 EMI (electromagnetic interference) . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
13.8.3 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 214
13.9 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
13.10 Control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
13.10.1 Asynchronous RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
13.11 Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . 224
13.11.1 I2C and I²C3SNS interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
13.12 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
14
15
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
14.1 ECOPACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
14.2 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Device configuration and ordering information . . . . . . . . . . . . . . . . . 232
15.1 Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
15.1.1 Option byte 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
15.1.2 Option byte 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
15.1.3 Option byte 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
15.1.4 Option byte 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
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15.2 Device ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
15.3 Development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
15.3.1 Starter kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
15.3.2 Development and debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
15.3.3 Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
15.3.4 Order codes for ST72F34x development tools . . . . . . . . . . . . . . . . . . 238
16
Known limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
16.1 External interrupt missed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
16.1.1 Workaround . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
16.1.2 Unexpected reset fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
16.2 Clearing active interrupts outside interrupt routine . . . . . . . . . . . . . . . . . 241
16.3 16-bit timer PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
16.4 TIMD set simultaneously with OC interrupt . . . . . . . . . . . . . . . . . . . . . . 242
16.4.1 Impact on the application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
16.4.2 Workaround . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
16.5 SCI wrong break duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
16.5.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
16.5.2 Occurrence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
16.5.3 Workaround . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
16.6 Random read operations not supported with the standard I²C . . . . . . . 243
16.6.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
16.6.2 Occurrence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
16.6.3 Workaround . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
16.7 Programming of EEPROM data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
16.7.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
16.7.2 Impact on application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
16.7.3 Workaround . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
17
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
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List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
ST72344xx and ST72345xx features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Device pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Data EEPROM register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Interrupt software priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
PLL configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
ST7 clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Low-power mode description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Interrupt event. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
LVDRF and WDGRF description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Interrupt software priority levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Interrupt software priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Interrupt vector addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Dedicated interrupt instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
External interrupt sensitivity (ei2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
External interrupt sensitivity (ei3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
External interrupt sensitivity (ei0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
External interrupt sensitivity (ei1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Nested interrupts register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Power saving mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
AWUPR dividing factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
AWU register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
I/O Port mode options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
I/O port configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Description of interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
I/O port register configurations (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
I/O port register configurations (interrupt ports with pull-up). . . . . . . . . . . . . . . . . . . . . . . . 79
I/O port register configurations (interrupt ports without pull-up) . . . . . . . . . . . . . . . . . . . . . 79
I/O port register configurations (true open drain ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
I/O port register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Watchdog timer register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Mode description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Interrupt event. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
CPU clock prescaler selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Time base control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Beep control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Main clock controller register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
ICiR register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
OCiR register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Low-power mode description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Interrupt events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
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List of tables
ST72344xx, ST2345xx
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
Table 82.
Table 83.
Table 84.
Table 85.
Table 86.
Table 87.
Table 88.
Table 89.
Table 90.
Table 91.
Table 92.
Table 93.
Table 94.
Table 95.
Table 96.
Table 97.
Table 98.
Table 99.
Timer modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Clock control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
16-bit timer register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Interrupt events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
SPI master mode SCK frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
SPI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Mode description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Interrupt events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
SCP[1:0] configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
SCT[2:0] configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
SCR[2:0] configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Baud rate selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
SCI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Mode description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
FR[1:0] configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
I2C register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Mode description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Interrupt events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
PL configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
I2C3S register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Mode description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
ADC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Addressing mode groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
ST7 addressing mode overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Inherent instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Immediate instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Instructions supporting direct, indexed, indirect and indirect indexed addressing modes 194
Short instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Relative direct/indirect instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Main instruction groups. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Illegal opcode detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
LVD thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
AVD thresholds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Internal RC oscillator and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Internal RC oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Supply current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
General timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
External clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Auto-wakeup from Halt oscillator (AWU) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 210
Crystal/ceramic resonator oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Recommended load capacitance vs. equivalent serial resistance of ceramic
resonator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
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Table 100. RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Table 101. Flash program memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Table 102. EEPROM data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Table 103. EMS test results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Table 104. EMI emissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Table 105. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Table 106. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Table 107. General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Table 108. Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Table 109. Asynchronous RESET pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Table 110. I2C and I²C3SNS interfaces characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
2
Table 111. SCL frequency table (multimaster I C interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Table 112. ADC accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Table 113. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Table 114. 32-pin low profile quad flat package (7 x 7 mm) mechanical data . . . . . . . . . . . . . . . . . . 228
Table 115. 40-lead very thin fine pitch quad flat no-lead package mechanical data . . . . . . . . . . . . . 229
Table 116. 44-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Table 117. 48-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Table 118. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Table 119. LVD threshold configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Table 120. Size of sector 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Table 121. Selection of the resonator oscillator range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Table 122. List of valid option combinations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Table 123. Package selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Table 124. Option byte default values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Table 125. Development tool order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Table 126. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
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List of figures
ST72344xx, ST2345xx
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
General block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
LQFP32 package pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
LQFP44 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
LQFP48 package pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Typical ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
EEPROM block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Data EEPROM programming flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Data EEPROM write operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 10. Data EEPROM programming cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 11. CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 12. Stack manipulation example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 13. Clock, reset and supply block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 14. PLL output frequency timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 15. reset sequence phases. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 16. Reset block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 17. Reset sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 18. Low voltage detector vs. reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 19. Using the AVD to monitor VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 20. Interrupt processing flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 21. Priority decision process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 22. Concurrent interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 23. Nested interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 24. External interrupt control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 25. Power saving mode transitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 26. Slow mode clock transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 27. Wait mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 28. Halt timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 29. Halt mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 30. Active-halt timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 31. Active-halt mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 32. AWUFH mode block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 33. AWUF Halt timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 34. AWUFH mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 35. I/O port general block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 36. Interrupt I/O port state transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 37. Watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 38. Approximate timeout duration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 39. Exact timeout duration (tmin and tmax) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 40. Window watchdog timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 41. Main clock controller (MCC/RTC) block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 42. Timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 43. 16-bit read sequence (from either the counter register or the alternate
counter register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 44. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 45. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 46. Counter timing diagram, internal clock divided by 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 47. Input capture block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
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Figure 48. Input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 49. Output compare block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 50. Output compare timing diagram, f
Figure 51. Output compare timing diagram, f
= f
= f
/2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
/4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
TIMER
CPU
TIMER
CPU
Figure 52. One-pulse mode cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 53. One-pulse mode timing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 54. Pulse width modulation mode timing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 55. Pulse width modulation cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 56. Serial peripheral interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Figure 57. Single master/ single slave application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 58. Generic SS timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Figure 59. Hardware/software slave select management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Figure 60. Data clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Figure 61. Clearing the WCOL bit (write collision flag) software sequence . . . . . . . . . . . . . . . . . . . . 123
Figure 62. Single master / multiple slave configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Figure 63. SCI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Figure 64. Word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Figure 65. SCI baud rate and extended prescaler block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Figure 66. Bit sampling in reception mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Figure 67. I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Figure 68. I2C interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Figure 69. Transfer sequencing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Figure 70. Event flags and interrupt generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Figure 71. I2C3S interface block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Figure 72. I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Figure 73. 16-bit word write operation flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Figure 74. 16-bit word read operation flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Figure 75. Transfer sequencing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Figure 76. Byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Figure 77. Page write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Figure 78. Current address read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Figure 79. Random read (dummy write + restart + current address read). . . . . . . . . . . . . . . . . . . . . 175
Figure 80. Random read (dummy write + stop + start + current address read). . . . . . . . . . . . . . . . . 176
Figure 81. Sequential read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Figure 82. Combined format for read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Figure 83. Event flags and interrupt generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Figure 84. ADC block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Figure 85. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Figure 86. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Figure 87.
Figure 88. Typical RC frequency vs. RCCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Figure 89. Typical I in Run vs. f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
f
maximum operating frequency versus V supply voltage . . . . . . . . . . . . . . . . . . . 202
CPU DD
DD
CPU
Figure 90. Typical I in Run at f
= 8 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
DD
CPU
Figure 91. Typical I in Slow vs. f
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
CPU
DD
Figure 92. Typical I in Wait vs. f
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
DD
CPU
Figure 93. Typical I in Wait at f
= 8 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
DD
CPU
Figure 94. Typical I in Slow-wait vs. f
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
DD
CPU
Figure 95. Typical I vs. temp. at V = 5 V and f = 8 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
DD
DD
CPU
Figure 96. Typical application with an external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Figure 97. Typical application with a crystal or ceramic resonator . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Figure 98. Two typical applications with unused I/O pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Figure 99. Typical V at V = 2.4 V (std I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
OL
DD
Doc ID 12321 Rev 6
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List of figures
ST72344xx, ST2345xx
Figure 100. Typical V at V = 3 V (std I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
OL
DD
Figure 101. Typical V at V = 5 V (std I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
OL
DD
Figure 102. Typical V at V = 2.4 V (high-sink I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
OL
DD
Figure 103. Typical V at V = 3 V (high-sink I/Os). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
OL
DD
Figure 104. Typical V at V = 5 V (high-sink I/Os). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
OL
DD
Figure 105. Typical V vs. V (std I/Os, 2 mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
OL
DD
Figure 106. Typical V vs. V (std I/Os, 6 mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
OL
DD
Figure 107. Typical V vs. V (HS I/Os, I = 8 mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
OL
DD
IO
Figure 108. Typical V vs. V (HS I/Os, I = 2 mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
OL
DD
IO
Figure 109. Typical V vs. V (HS I/Os, I = 12 mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
OL
DD
IO
Figure 110. Typical V – v at V = 2.4 V (std I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
DD
OH
DD
Figure 111. Typical V – V at V = 3 V (std I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
DD
OH
DD
Figure 112. Typical V – V at V = 4 V (std). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
DD
OH
DD
Figure 113. Typical V – V at V = 5 V (std) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
DD
OH
DD
Figure 114. Typical V – V vs. VDD (high sink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
DD
OH
Figure 115. RESET pin protection when LVD is enabled(1)(2)(3)(4). . . . . . . . . . . . . . . . . . . . . . . . . . 223
Figure 116. RESET pin protection when LVD is disabled (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Figure 117. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Figure 118. Typical A/D converter application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Figure 119. 32-pin low profile quad flat package (7 x 7 mm) outline . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Figure 120. 40-lead very thin fine pitch quad flat no-lead package outline . . . . . . . . . . . . . . . . . . . . . 228
Figure 121. 44-pin low profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Figure 122. 48-pin low profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Figure 123. ST7234x ordering information scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
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ST72344xx, ST2345xx
Description
1
Description
The ST7234x devices are members of the ST7 microcontroller family. Table 2 gives the
available part numbers and details on the devices. All devices are based on a common
industry-standard 8-bit core, featuring an enhanced instruction set.
They feature single-voltage Flash memory with byte-by-byte in-circuit programming (ICP)
and in-application programming (IAP) capabilities.
Under software control, all devices can be placed in Wait, Slow, Auto-wakeup from Halt,
Active-halt or Halt mode, reducing the power consumption when the application is in idle or
stand-by state.
The enhanced instruction set and addressing modes of the ST7 offer both power and
flexibility to software developers, enabling the design of highly efficient and compact
application code. In addition to standard 8-bit data management, all ST7 microcontrollers
feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes.
The devices feature an on-chip debug module (DM) to support in-circuit debugging (ICD).
For a description of the DM registers, refer to the ST7 ICC Protocol Reference Manual.
Figure 1.
General block diagram
8-BIT CORE
ALU
PROGRAM
MEMORY
(16 K - 32 KBytes)
RESET
CONTROL
RAM
(512- 1024 Bytes)
VSS
VDD
LVD
AVD
WATCHDOG
I2CMMS
OSC1
OSC2
CLOCK CONTROL
PA
(5-bits)
INTERNAL RC
PORT A
MCC/RTC/BEEP
PORT B
PB
(5-bits)
PORT F
TIMER A
BEEP
PWM ART
PF
(6-bits)
PORT C
TIMER B
SPI
PC
(8-bits)
I2C3SNS
PD
(6-bits)
PORT D
PORT E
SCI
10-BIT ADC
PE
(2-bits)
VAREF
VSSA
Doc ID 12321 Rev 6
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Description
ST72344xx, ST2345xx
ST72345C4
Table 2.
ST72344xx and ST72345xx features
ST72344K2, ST72344K4, ST72344S2,
Features
ST72344S4
Program memory - bytes
RAM (stack) - bytes
EEPROM data - bytes
Common peripherals
Other peripherals
CPU frequency
8,000
512 bytes (256 bytes) 1 Kbyte (256 bytes)
256 256
16,000
16,000
1 Kbyte (256 bytes)
256
Window watchdog, 2 16-bit timers, SCI, SPI, I2CMMS
10-bit ADC
I2C3SNS, 10-bit ADC
8 MHz @ 3.3 V to 5.5 V, 4 MHz @ 2.7 V to 5.5 V
-40 °C to +85 °C
Temperature range
Package
LQFP32 7x7, LQFP44 10x10
LQFP48 7x7
16/247
Doc ID 12321 Rev 6
ST72344xx, ST2345xx
Pin description
2
Pin description
Figure 2.
LQFP32 package pinout
32 31 30 29 28 27 26 25
ei3 ei2 ei0
VDDA
VSSA
AIN8 / PF0
1
2
3
24
23
22
OSC1
OSC2
V
SS_2
ei1
4
21
(HS) PF1
OCMP1_A / AIN10 / PF4
ICAP1_A / (HS) PF6
EXTCLK_A / (HS) PF7
AIN12 / OCMP2_B / PC0
RESET
ICCSEL
PA7 (HS) / SCL
PA6 (HS) / SDA
PA4 (HS)
5
6
7
8
20
19
18
17
ei0
10 11 12 13 14 15 16
9
(HS) 20mA high sink capability
eix associated external interrupt vector
Doc ID 12321 Rev 6
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Pin description
ST72344xx, ST2345xx
Figure 3.
LQFP44 package pinout
44 43 42 41 40 39 38 37 36 35 34
ei0
RDI / PE1
PB0
1
33 VSS_1
2
32
31
30
29
28
27
26
25
24
23
VDD_1
3
ei0
PB1
PA3 (HS)
ei2
ei3
4
PB2
PB3
PC7 / SS / AIN15
5
PC6 / SCK / ICCCLK
PC5 / MOSI / AIN14
PC4 / MISO / ICCDATA
PC3 (HS) / ICAP1_B
PC2 (HS) / ICAP2_B
PC1 / OCMP1_B / AIN13
PC0 / OCMP2_B / AIN12
6
(HS) PB4
AIN0 / PD0
AIN1 / PD1
AIN2 / PD2
AIN3 / PD3
AIN4 / PD4
7
8
9
10
11
ei1
12 13 14 15 16 17 18 19 20 21 22
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Doc ID 12321 Rev 6
ST72344xx, ST2345xx
Figure 4.
Pin description
LQFP48 package pinout
48 47 46 45 44 43 42 41 40 39 38 37
36
35
34
33
32
31
30
29
28
27
26
25
1
VSS_1
PE0/TD0
RDI / PE1
PB0
2
ei0
ei2
ei3
VDD_1
ei0
3
PA3 (HS)
PC7 / SS / AIN15
4
PB1
5
PB2
PB3
PC6 / SCK / ICCCLK
PC5 / MOSI / AIN14
PC4 / MISO / ICCDATA
PC3 (HS) / ICAP1_B
PC2 (HS) / ICAP2_B
PC1 / OCMP1_B / AIN13
NC
6
7
(HS) PB4
AIN0 / PD0
AIN1 / PD1
AIN2 / PD2
AIN3 / PD3
AIN4 / PD4
8
9
10
11
12
ei1
NC
24
13 14 15 16 17 18 19 20 21 22 23
Note:
For external pin connection guidelines, refer to Section 13: Electrical characteristics.
Doc ID 12321 Rev 6
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Pin description
ST72344xx, ST2345xx
Legend / Abbreviations for Table 3:
Type:
I = input, O = output, S = supply
A = Dedicated analog input
Input level:
In/Output level: C = CMOS 0.3V /0.7V with input trigger
T
DD
DD
Output level:
HS = 20 mA high sink (on N-buffer only)
Port and control configuration:
1)
■
■
Input:
float = floating, wpu = weak pull-up, int = interrupt , ana = analog
2)
Output:
OD = open drain , PP = push-pull
The reset configuration of each pin is shown in bold. This configuration is valid as long as
the device is in reset state.
On the chip, each I/O port may have up to 8 pads. Pads that are not bonded to external pins
are set in input pull-up configuration after reset through the option byte Package selection.
The configuration of these pads must be kept at reset state to avoid added current
consumption.
Table 3.
Pin n°
Device pin description
Level
Port
Input (1)
Main
function
(after
Output
Pin name
Alternate function
reset)
(2)
(2)
1
2
13 14 VDDA
14 15 VSSA
S
S
Analog supply voltage
Analog ground voltage
Main clock ADC
out analog
(fOSC/2) input 8
3
15 16 PF0/MCO/AIN8
I/O CT
X
ei1
ei1
X
X
X
X
Port F0
4
-
16 17 PF1 (HS)/BEEP
17 18 PF2 (HS) (3)
I/O CT HS
I/O CT HS
X
X
X
X
X
X
Port F1
Port F2
Beep signal output
ei1
Timer A
output
ADC
analog
5
18 19 PF4/OCMP1_A/AIN10
I/O CT
X
X
X
X
Port F4
compare 1 input 10
Timer A Input
Capture 1
6
7
19 20 PF6 (HS)/ICAP1_A
20 21 PF7 (HS)/EXTCLK_A
I/O CT HS
I/O CT HS
X
X
X
X
X
X
X
X
Port F6
Port F7
Timer A external
clock source
(2)
-
-
21 22 VDD_0
S
S
Digital main supply voltage
Digital ground voltage
(2)
22 23 VSS_0
Timer B
Port C0 output
ADC
analog
8
9
23 24 PC0/OCMP2_B/AIN12
24 27 PC1/OCMP1_B/AIN13
I/O CT
I/O CT
X
X
X
X
X
X
X
X
X
X
compare 2 input 12
Timer B
ADC
Port C1 output
analog
compare 1 input 13
20/247
Doc ID 12321 Rev 6
ST72344xx, ST2345xx
Pin description
Alternate function
Table 3.
Pin n°
Device pin description (continued)
Level
Port
Input (1)
Main
function
(after
Output
Pin name
reset)
Timer B input capture
2
10 25 28 PC2 (HS)/ICAP2_B
11 26 29 PC3 (HS)/ICAP1_B
I/O CT HS
I/O CT HS
X
X
X
X
X
X
X
X
Port C2
Port C3
Timer B input capture
1
SPIMaster
ICC data
12 27 30 PC4/MISO/ICCDATA
13 28 31 PC5/MOSI/AIN14
14 29 32 PC6/SCK/ICCCLK
I/O CT
I/O CT
I/O CT
X
X
X
X
X
X
X
X
X
X
X
X
Port C4 In / Slave
Out data
input
SPIMaster ADC
Port C5 Out / Slave analog
X
X
In data
input 14
ICC
clock
output
SPI serial
clock
Port C6
SPI slave
select
(active
low)
ADC
analog
input 15
15 30 33 PC7/SS/AIN15
I/O CT
X
X
X
X
X
X
X
Port C7
Port A3
16 31 34 PA3 (HS)
I/O CT HS
ei0
(2)
-
-
32 35 VDD_1
33 36 VSS_1
S
S
Digital main supply voltage
Digital ground voltage
(2)
T
-
-
-
-
37 PD7 (3)/ SCL3SNS
38 PD6 (3)/ SDA3SNS
I/O CT HS
X
Port D7 I2C3SNS serial clock
(4)
I/O CT HS
I/O CT HS
I/O CT HS
I/O CT HS
I/O CT HS
I
X
X
X
X
X
T
X
X
T
T
Port D6 I2C3SNS serial data
Port A4
17 34 39 PA4 (HS)
35 40 PA5 (HS) (3)
X
X
X
X
-
Port A5
18 36 41 PA6 (HS)/SDA
19 37 42 PA7 (HS)/SCL
20 38 43 ICCSEL (5)
Port A6 I2C serial data
Port A7 I2C serial clock
ICC mode selection
Top priority non maskable
interrupt.
21 39 44 RESET
I/O CT
(2)
22 40 45 VSS_2
S
Digital ground voltage
Resonator oscillator inverter
output
23 41 46 OSC2
24 42 47 OSC1
O
External clock input or resonator
oscillator inverter input
I
(2)
25 43 48 VDD_2
S
Digital main supply voltage
26 44
1
PE0/TDO
I/O CT
X
X
X
X
Port E0 SCI transmit data out
Doc ID 12321 Rev 6
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Pin description
ST72344xx, ST2345xx
Table 3.
Pin n°
Device pin description (continued)
Level
Port
Input (1)
Main
function
(after
Output
Pin name
Alternate function
reset)
27
28
-
1
2
3
4
5
6
7
8
9
2
3
4
5
6
7
8
9
PE1/RDI
I/O CT
X
X
X
X
X
X
X
X
X
X
X
X
ei0
ei2
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Port E1 SCI receive data in
Port B0
PB0
I/O CT
I/O CT
I/O CT
I/O CT
I/O CT HS
I/O CT
I/O CT
I/O CT
I/O CT
I/O CT
I/O CT
PB1 (3)
PB2 (3)
PB3
ei2
ei2
Port B1
-
Port B2
29
30
31
32
-
ei2
ei3
Port B3
PB4 (HS)
PD0/AIN0
PD1/AIN1
Port B4
X
X
X
X
X
X
X
X
X
X
X
X
Port D0 ADC analog input 0
Port D1 ADC analog input 1
Port D2 ADC analog input 2
Port D3 ADC analog input 3
Port D4 ADC analog input 4
Port D5 ADC analog input 5
10 PD2/AIN2
-
10 11 PD3/AIN3
11 12 PD4/AIN4
12 13 PD5/AIN5
-
-
1. In the interrupt input column, “eiX” defines the associated external interrupt vector. If the weak pull-up column (wpu) is
merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input, else the configuration is floating
interrupt input.
2. It is mandatory to connect all available VDD and VDDA pins to the supply voltage and all VSS and VSSA pins to ground.
3. Pulled-up by hardware when not present on the package.
4. In the open drain output column, “T” defines a true open drain I/O (P-Buffer and protection diode to VDD are not
implemented).
5. Internal weak pull-down.
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Doc ID 12321 Rev 6
ST72344xx, ST2345xx
Register and memory map
3
Register and memory map
As shown in Figure 5, the MCU is capable of addressing 64 Kbytes of memories and I/O
registers.
The available memory locations consist of 128 bytes of register locations, up to 1 Kbyte of
RAM, 256 bytes of Data EEPROM and up to 16 Kbytes of user program memory. The RAM
space includes up to 256 bytes for the stack from 0100h to 01FFh.
The highest address bytes contain the user reset and interrupt vectors.
Figure 5.
Memory map
0000h
0080h
HW registers
Short addressing
RAM (zero page)
See Table 4
007Fh
0080h
00FFh
0100h
RAM
(512 or 1K Bytes)
047Fh
0480h
256 Bytes stack
01FFh
0200h
Reserved
16-bit addressing
RAM
0BFFh
0C00h
Data EEPROM
(256 Bytes)
047Fh
C000h
0CFFh
0D00h
C000h
E000h
Reserved
SECTOR 2
SECTOR 1
SECTOR 0
BFFFh
C000h
16 Kbytes
8 Kbytes
Program memory
(8 or 16 KBytes)
E000h
FFFFh
FFDFh
FFE0h
F000h (4k)
or FB00h (2k)
or FC00h (1k)
or FE00h (0.5k)
Interrupt & Reset Vectors
See Table 17
FFFFh
FFFFh
Doc ID 12321 Rev 6
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Register and memory map
ST72344xx, ST2345xx
Reset status Remarks
Table 4.
Address
Hardware register map
Register
label
Block
Register name
(1)
(2)
0000h
0001h
0002h
PADR
Port A Data Register
Port A Data Direction Register
Port A Option Register
00h (4)
00h
00h
R/W
R/W
R/W
Port A (3) PADDR
PAOR
0003h
0004h
0005h
PBDR
Port B (3) PBDDR
PBOR
Port B Data Register
Port B Data Direction Register
Port B Option Register
00h (4)
00h
00h
R/W
R/W
R/W
0006h
0007h
0008h
PCDR
Port C (3) PCDDR
PCOR
Port C Data Register
Port C Data Direction Register
Port C Option Register
00h (4)
00h
00h
R/W
R/W
R/W
0009h
000Ah
000Bh
PDADR
Port D (3) PDDDR
PDOR
Port D Data Register
Port D Data Direction Register
Port D Option Register
00h (4)
00h
00h
R/W
R/W
R/W
000Ch
000Dh
000Eh
PEDR
Port E (3) PEDDR
PEOR
Port E Data Register
Port E Data Direction Register
Port E Option Register
00h (4)
00h
00h
R/W
R/W
R/W
000Fh
0010h
0011h
PFDR
Port F (3) PFDDR
PFOR
Port F Data Register
Port F Data Direction Register
Port F Option Register
00h (4)
00h
00h
R/W
R/W
R/W
0012h to
0016h
Reserved area (5 bytes)
0017h
0018h
RCCRH
RC
RC oscillator Control Register High
RC oscillator Control Register Low
FFh
03h
R/W
R/W
RCCRL
0019h
Reserved area (1 byte)
001Ah to
001Fh
DM (5)
Reserved area (6 bytes)
00020h
EEPROM EECSR
SPIDR
Data EEPROM Control/Status Register
00h
R/W
0021h
0022h
0023h
SPI Data I/O Register
SPI Control Register
SPI Control Status Register
xxh
0xh
00h
R/W
R/W
R/W
SPI
SPICR
SPICSR
0024h
0025h
0026h
0027h
ISPR0
ISPR1
ISPR2
ISPR3
Interrupt Software Priority Register 0
Interrupt Software Priority Register 1
Interrupt Software Priority Register 2
Interrupt Software Priority Register 3
FFh
FFh
FFh
FFh
R/W
R/W
R/W
R/W
ITC
0028h
00029h
002Ah
002Bh
EICR
External Interrupt Control Register
Flash Control/Status Register
00h
00h
7Fh
R/W
R/W
R/W
Flash
FCSR
WWDG WDGCR
Watchdog Control Register
SI
SICSR
System Integrity Control/Status Register
000x 000xb R/W
002Ch
002Dh
MCCSR
MCCBCR
Main Clock Control/Status Register
MCC Beep Control Register
00h
00h
R/W
R/W
MCC
002Eh
002Fh
AWUCSR
AWUPR
AWU Control/Status Register
AWU Prescaler Register
00h
FFh
R/W
R/W
AWU
0030h
WWDG WDGWR
Window Watchdog Control Register
7Fh
R/W
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Register and memory map
Reset status Remarks
Table 4.
Address
Hardware register map (continued)
Register
label
Block
Register name
(1)
(2)
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
TACR2
TACR1
TACSR
TAIC1HR
TAIC1LR
TAOC1HR
TAOC1LR
Timer A Control Register 2
Timer A Control Register 1
Timer A Control/Status Register
Timer A Input Capture 1 High Register
Timer A Input Capture 1 Low Register
Timer A Output Compare 1 High Register
Timer A Output Compare 1 Low Register
Timer A Counter High Register
00h
00h
xxh
xxh
xxh
80h
00h
FFh
FCh
FFh
FCh
xxh
xxh
80h
00h
R/W
R/W
R/W
Read Only
Read Only
R/W
R/W
TIMER A TACHR
TACLR
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
R/W
Timer A Counter Low Register
TAACHR
TAACLR
TAIC2HR
TAIC2LR
TAOC2HR
TAOC2LR
Timer A Alternate Counter High Register
Timer A Alternate Counter Low Register
Timer A Input Capture 2 High Register
Timer A Input Capture 2 Low Register
Timer A Output Compare 2 High Register
Timer A Output Compare 2 Low Register
R/W
0040h
Reserved area (1 Byte)
0041h
0042h
0043h
0044h
0045h
0046h
0047h
0048h
0049h
004Ah
004Bh
004Ch
004Dh
004Eh
004Fh
TBCR2
TBCR1
TBCSR
TBIC1HR
TBIC1LR
Timer B Control Register 2
Timer B Control Register 1
Timer B Control/Status Register
Timer B Input Capture 1 High Register
Timer B Input Capture 1 Low Register
Timer B Output Compare 1 High Register
Timer B Output Compare 1 Low Register
Timer B Counter High Register
00h
00h
xxh
xxh
xxh
80h
00h
FFh
FCh
FFh
FCh
xxh
xxh
80h
00h
R/W
R/W
R/W
Read Only
Read Only
R/W
TBOC1HR
TBOC1LR
TIMER B TBCHR
TBCLR
R/W
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
R/W
Timer B Counter Low Register
TBACHR
TBACLR
TBIC2HR
TBIC2LR
TBOC2HR
TBOC2LR
Timer B Alternate Counter High Register
Timer B Alternate Counter Low Register
Timer B Input Capture 2 High Register
Timer B Input Capture 2 Low Register
Timer B Output Compare 2 High Register
Timer B Output Compare 2 Low Register
R/W
0050h
0051h
0052h
0053h
0054h
0055h
0056h
0057h
SCISR
SCIDR
SCIBRR
SCICR1
SCICR2
SCI Status Register
SCI Data Register
SCI Baud Rate Register
SCI Control Register 1
SCI Control Register 2
Reserved area
SCI Extended Receive Prescaler Register
SCI Extended Transmit Prescaler Register
C0h
xxh
00h
Read Only
R/W
R/W
x000 0000b R/W
SCI
00h
--
00h
00h
R/W
SCIERPR
SCIETPR
R/W
R/W
0058h
0059h
005Ah
005Bh
005Ch
005Dh
005Eh
I2CCR
I2CSR1
I2CSR2
I2CCCR
I2COAR1
I2COAR2
I2CDR
I2C Control Register
00h
00h
00h
00h
00h
40h
00h
R/W
I2C Status Register 1
I2C Status Register 2
I2C Clock Control Register
I2C Own Address Register 1
I2C Own Address Register2
I2C Data Register
Read Only
Read Only
R/W
R/W
R/W
I2C
R/W
005Fh
Reserved area (1 byte)
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Register and memory map
ST72344xx, ST2345xx
Reset status Remarks
Table 4.
Address
Hardware register map (continued)
Register
label
Block
Register name
(1)
(2)
0060h
0061h
0062h
0063h
0064h
0065h
0066h
0067h
0068h
0069h
I2C3SCR1
I2C3SCR2
I2C3SSR
I2C3SNS Control Register 1
I2C3SNS Control Register 2
I2C3SNS Status Register
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
R/W
R/W
Read Only
Read Only
R/W
R/W
R/W
R/W
R/W
I2C3SBCR
I2C3SNS Byte Count Register
I2C3SSAR1 I2C3SNS Slave Address 1 Register
I2C3SCAR1 I2C3SNS Current Address 1 Register
I2C3SSAR2 I2C3SNS Slave Address 2 Register
I2C3SCAR2 I2C3SNS Current Address 2 Register
I2C3SSAR3 I2C3SNS Slave Address 3 Register
I2C3SCAR3 I2C3SNS Current Address 3 Register
I2C3SNS
R/W
0070h
0071h
0072h
ADCCSR
ADCDRH
ADCDRL
A/D Control Status Register
A/D Data Register High
A/D Data Low Register
00h
xxh
R/W
Read Only
ADC
0000 00xxb Read Only
0073h to
007Fh
Reserved area (13 bytes)
1. x = undefined.
2. R/W = read/write.
3. The bits associated with unavailable pins must always keep their reset value.
4. The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the
I/O pins are returned instead of the DR register contents.
5. For a description of the Debug Module registers, see ST7 ICC protocol reference manual.
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Flash program memory
4
Flash program memory
4.1
Introduction
The ST7 single voltage extended Flash (XFlash) is a non-volatile memory that can be
electrically erased and programmed either on a byte-by-byte basis or up to 32 bytes in
parallel.
The XFlash devices can be programmed off-board (plugged in a programming tool) or on-
board using In-Circuit Programming or In-Application Programming.
The array matrix organization allows each sector to be erased and reprogrammed without
affecting other sectors.
4.2
4.3
Main features
■
■
■
ICP (in-circuit programming)
IAP (in-application programming)
ICT (in-circuit testing) for downloading and executing user application test patterns in
RAM
■
■
Sector 0 size configurable by option byte
Read-out and write protection
Programming modes
The ST7 can be programmed in three different ways:
■
■
■
Insertion in a programming tool
In this mode, Flash sectors 0 and 1, option byte row and data EEPROM (if present) can
be programmed or erased.
In-circuit programming
In this mode, Flash sectors 0 and 1, option byte row and data EEPROM (if present) can
be programmed or erased without removing the device from the application board.
In-application programming
In this mode, sector 1 and data EEPROM (if present) can be programmed or erased
without removing the device from the application board and while the application is
running.
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Flash program memory
ST72344xx, ST2345xx
4.3.1
In-circuit programming (ICP)
ICP uses a protocol called ICC (in-circuit communication) which allows an ST7 plugged on a
printed circuit board (PCB) to communicate with an external programming device connected
via cable. ICP is performed in three steps:
Switch the ST7 to ICC mode (in-circuit communications). This is done by driving a specific
signal sequence on the ICCCLK/DATA pins while the RESET pin is pulled low. When the
ST7 enters ICC mode, it fetches a specific reset vector which points to the ST7 System
Memory containing the ICC protocol routine. This routine enables the ST7 to receive bytes
from the ICC interface.
■
■
Download ICP Driver code in RAM from the ICCDATA pin
Execute ICP Driver code in RAM to program the Flash memory
Depending on the ICP Driver code downloaded in RAM, Flash memory programming can
be fully customized (number of bytes to program, program locations, or selection of the
serial communication interface for downloading).
4.3.2
In-application programming (IAP)
This mode uses an IAP Driver program previously programmed in Sector 0 by the user (in
ICP mode).
This mode is fully controlled by user software. This allows it to be adapted to the user
application (user-defined strategy for entering programming mode, choice of
communications protocol used to fetch the data to be stored etc.)
IAP mode can be used to program any memory areas except Sector 0, which is write/erase
protected to allow recovery in case errors occur during the programming operation.
4.4
ICC interface
ICP needs a minimum of 4 and up to 7 pins to be connected to the programming tool. These
pins are:
■
■
■
■
■
■
RESET: device reset
: device power supply ground
V
SS
ICCCLK: ICC output serial clock pin
ICCDATA: ICC input serial data pin
ICCSEL: ICC selection
OSC1: main clock input for external source (not required on devices without
OSC1/OSC2 pins)
■
V
: application board power supply (optional, see Note 3)
DD
Note:
1
2
If the ICCCLK or ICCDATA pins are only used as outputs in the application, no signal
isolation is necessary. As soon as the Programming Tool is plugged to the board, even if an
ICC session is not in progress, the ICCCLK and ICCDATA pins are not available for the
application. If they are used as inputs by the application, isolation such as a serial resistor
has to be implemented in case another device forces the signal. Refer to the Programming
Tool documentation for recommended resistor values.
During the ICP session, the programming tool must control the RESET pin. This can lead to
conflicts between the programming tool and the application reset circuit if it drives more than
5 mA at high level (push pull output or pull-up resistor<1,000). A schottky diode can be used
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ST72344xx, ST2345xx
Flash program memory
to isolate the application reset circuit in this case. When using a classical RC network with
R>1,000 or a reset management IC with open drain output and pull-up resistor>1,000, no
additional components are needed. In all cases the user must ensure that no external reset
is generated by the application during the ICC session.
3
4
5
The use of Pin 7 of the ICC connector depends on the Programming Tool architecture. This
pin must be connected when using most ST Programming Tools (it is used to monitor the
application power supply). Please refer to the Programming Tool manual.
Pin 9 has to be connected to the OSC1 pin of the ST7 when the clock is not available in the
application or if the selected clock option is not programmed in the option byte. ST7 devices
with multi-oscillator capability need to have OSC2 grounded in this case.
In “enabled option byte” mode (38-pulse ICC mode), the internal RC oscillator is forced as a
clock source, regardless of the selection in the option byte.
Caution:
During normal operation, the ICCCLK pin must be internally or externally pulled- up
(external pull-up of 10 kΩ mandatory in noisy environment) to avoid entering ICC mode
unexpectedly during a reset. In the application, even if the pin is configured as an output,
any reset will put it back in input pull-up.
Figure 6.
Typical ICC interface
PROGRAMMING TOOL
ICC CONNECTOR
ICC Cable
ICC CONNECTOR
HE10 CONNECTOR TYPE
(See Note 3)
OPTIONAL
(See Note 4)
APPLICATION BOARD
9
7
5
6
3
1
2
10
8
4
APPLICATION
RESET SOURCE
See Note 2
10kΩ
APPLICATION
POWER SUPPLY
CL2
CL1
APPLICATION
I/O
See Note 1
ST7
4.5
Memory protection
There are two different types of memory protection: Read Out Protection and Write/Erase
Protection which can be applied individually.
4.5.1
Readout protection
Readout protection, when selected, provides a protection against program memory content
extraction and against write access to Flash memory. Even if no protection can be
considered as totally unbreakable, the feature provides a very high level of protection for a
2
general purpose microcontroller. Both program and data E memory are protected.
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Flash program memory
ST72344xx, ST2345xx
In Flash devices, this protection is removed by reprogramming the option. In this case, both
2
program and data E memory are automatically erased, and the device can be
reprogrammed.
Read-out protection selection depends on the device type:
■
■
In Flash devices, it is enabled and removed through the FMP_R bit in the option byte.
In ROM devices, it is enabled by mask option specified in the Option List.
4.5.2
Flash write/erase protection
Write/erase protection, when set, makes it impossible to both overwrite and erase program
2
memory. It does not apply to E data. Its purpose is to provide advanced security to
applications and prevent any change being made to the memory content.
Warning: Once set, Write/erase protection can never be removed. A
write-protected Flash device is no longer reprogrammable.
Write/erase protection is enabled through the FMP_W bit in the option byte.
4.6
Register description
4.6.1
Flash control/status register (FCSR)
Reset value: 0000 0000 (00h)
1st RASS Key: 0101 0110 (56h)
2nd RASS Key: 1010 1110 (AEh)
7
0
0
0
0
0
0
OPT
LAT
PGM
Read/Write
Note:
This register is reserved for programming using ICP, IAP or other programming methods. It
controls the XFlash programming and erasing operations. For details on XFlash
programming, refer to the ST7 Flash Programming Reference Manual.
When an EPB or another programming tool is used (in socket or ICP mode), the RASS keys
are sent automatically.
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Data EEPROM
5
Data EEPROM
5.1
Introduction
The electrically erasable programmable read only memory can be used as a non-volatile
backup for storing data. Using the EEPROM requires a basic access protocol described in
this chapter.
5.2
Main features
■
■
■
■
■
■
Up to 32 bytes programmed in the same cycle
EEPROM mono-voltage (charge pump)
Chained erase and programming cycles
Internal control of the global programming cycle duration
Wait mode management
Readout protection
Figure 7.
EEPROM block diagram
HIGH VOLTAGE
PUMP
EECSR
0
0
0
0
0
0
E2LAT E2PGM
EEPROM
ROW
ADDRESS
DECODER
4
MEMORY MATRIX
(1 ROW = 32 x 8 BITS)
DECODER
128
128
DATA
MULTIPLEXER
32 x 8 BITS
4
4
DATA LATCHES
ADDRESS BUS
DATA BUS
5.3
Memory access
The Data EEPROM memory read/write access modes are controlled by the E2LAT bit of the
EEPROM Control/Status register (EECSR). The flowchart in Figure 8 describes these
different memory access modes.
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Data EEPROM
ST72344xx, ST2345xx
Read operation (E2LAT = 0)
The EEPROM can be read as a normal ROM location when the E2LAT bit of the EECSR
register is cleared.
On this device, Data EEPROM can also be used to execute machine code. Take care not to
write to the Data EEPROM while executing from it. This would result in an unexpected code
being executed.
Write operation (E2LAT = 1)
To access the write mode, the E2LAT bit has to be set by software (the E2PGM bit remains
cleared). When a write access to the EEPROM area occurs, the value is latched inside the
32 data latches according to its address.
When E2PGM bit is set by the software, all the previous bytes written in the data latches (up
to 32) are programmed in the EEPROM cells. The effective high address (row) is
determined by the last EEPROM write sequence. To avoid wrong programming, the user
must take care that all the bytes written between two programming sequences have the
same high address: only the five Least Significant Bits of the address can change.
The programming cycle is fully completed when the E2PGM bit is cleared.
Note:
Care should be taken during the programming cycle. Writing to the same memory location
will over-program the memory (logical AND between the two write access data results)
because the data latches are only cleared at the end of the programming cycle and by the
falling edge of the E2LAT bit.
It is not possible to read the latched data.
This note is illustrated by the Figure 10.
Figure 8.
Data EEPROM programming flowchart
READ MODE
E2LAT = 0
WRITE MODE
E2LAT = 1
E2PGM = 0
E2PGM = 0
WRITE UP TO 32 BYTES
IN EEPROM AREA
(with the same 11 MSB of the address)
READ BYTES
IN EEPROM AREA
START PROGRAMMING CYCLE
E2LAT=1
E2PGM=1 (set by software)
0
1
E2PGM
CLEARED BY HARDWARE
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ST72344xx, ST2345xx
Figure 9.
Data EEPROM
Data EEPROM write operation
Row / Byte
0
1
2
3
... 30 31
Physical address
Row
0
1
00h...1Fh
20h...3Fh
definition
...
N
Nx20h...Nx20h+1Fh
Read operation impossible
Read operation possible
Programming cycle
PHASE 2
Waiting E2PGM and E2LAT to fall
Byte 1 Byte 2
PHASE 1
Byte 32
Writing data latches
E2LAT bit
Set by USER application
Cleared by hardware
E2PGM bit
Note:
If a programming cycle is interrupted (by reset action), the integrity of the data in memory
will not be guaranteed.
5.4
Power saving modes
5.4.1
Wait mode
The data EEPROM can enter Wait mode on execution of the WFI instruction of the
microcontroller or when the microcontroller enters Active Halt mode.The data EEPROM will
immediately enter this mode if there is no programming in progress, otherwise the data
EEPROM will finish the cycle and then enter Wait mode.
5.4.2
5.4.3
Active-halt mode
Refer to Wait mode.
Halt mode
The data EEPROM immediately enters Halt mode if the microcontroller executes the Halt
instruction. Therefore the EEPROM will stop the function in progress, and data may be
corrupted.
5.5
Access error handling
If a read access occurs while E2LAT = 1, then the data bus will not be driven.
If a write access occurs while E2LAT = 0, then the data on the bus will not be latched.
If a programming cycle is interrupted (by reset action), the integrity of the data in memory
will not be guaranteed.
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Data EEPROM
ST72344xx, ST2345xx
5.6
Data EEPROM readout protection
The readout protection is enabled through an option bit (see Section 15.1: Option bytes).
When this option is selected, the programs and data stored in the EEPROM memory are
protected against read-out (including a rewrite protection). In Flash devices, when this
protection is removed by reprogramming the option byte, the entire Program memory and
EEPROM is first automatically erased.
Note:
Both program memory and data EEPROM are protected using the same option bit.
Figure 10. Data EEPROM programming cycle
READ OPERATION NOT POSSIBLE
READ OPERATION POSSIBLE
INTERNAL
PROGRAMMING
VOLTAGE
ERASE CYCLE
WRITE CYCLE
WRITE OF
DATA
LATCHES
t
PROG
E2LAT
E2PGM
I bit in CC register
1)
All interrupts must be masked
Note 1: refer to Programming of EEPROM data
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Data EEPROM
5.7
Register description
5.7.1
EEPROM control/status register (EECSR)
Reset value: 0000 0000 (00h)
7
0
0
0
0
0
0
0
E2LAT
E2PGM
Read/Write
Bits 7:2 = Reserved, forced by hardware to 0.
Bit 1 = E2LAT Latch Access Transfer
This bit is set by software. It is cleared by hardware at the end of the programming
cycle. It can only be cleared by software if the E2PGM bit is cleared.
0: Read mode
1: Write mode
Bit 0 = E2PGM Programming control and status
This bit is set by software to begin the programming cycle. At the end of the
programming cycle, this bit is cleared by hardware.
0: Programming finished or not yet started
1: Programming cycle is in progress
Note:
If the E2PGM bit is cleared during the programming cycle, the memory data is not
guaranteed.
Table 5.
Data EEPROM register map and reset values
Address Register
7
6
5
4
3
2
1
0
(Hex.)
label
EECSR
Reset value
E2LAT E2PGM
0020h
0
0
0
0
0
0
0
0
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Central processing unit
ST72344xx, ST2345xx
6
Central processing unit
6.1
Introduction
This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-
bit data manipulation.
6.2
Main features
■
■
■
■
■
■
■
■
Enable executing 63 basic instructions
Fast 8-bit by 8-bit multiply
17 main addressing modes (with indirect addressing mode)
Two 8-bit index registers
16-bit stack pointer
Low power Halt and Wait modes
Priority maskable hardware interrupts
Non-maskable software/hardware interrupts
6.3
CPU registers
The six CPU registers shown in Figure 11 are not present in the memory mapping and are
accessed by specific instructions.
Accumulator (A)
The Accumulator is an 8-bit general purpose register used to hold operands and the results
of the arithmetic and logic calculations and to manipulate data.
Index Registers (X and Y)
These 8-bit registers are used to create effective addresses or as temporary storage areas
for data manipulation. (The Cross-Assembler generates a precede instruction (PRE) to
indicate that the following instruction refers to the Y register.)
The Y register is not affected by the interrupt automatic procedures.
Program Counter (PC)
The program counter is a 16-bit register containing the address of the next instruction to be
executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is
the LSB) and PCH (Program Counter High which is the MSB).
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Central processing unit
Figure 11. CPU registers
7
0
0
0
ACCUMULATOR
RESET VALUE = XXh
7
X INDEX REGISTER
Y INDEX REGISTER
RESET VALUE = XXh
7
RESET VALUE = XXh
PCL
PCH
7
8
15
0
PROGRAM COUNTER
RESET VALUE = RESET VECTOR @ FFFEh-FFFFh
7
1
0
1
1
I1 H I0 N Z
C
X
CONDITION CODE REGISTER
STACK POINTER
RESET VALUE =
8
1
1 X 1 X X
15
7
0
RESET VALUE = STACK HIGHER ADDRESS
X = Undefined Value
6.3.1
Condition code register (CC)
Reset value: 111x1xxx
7
0
1
1
I1
H
I0
N
Z
C
Read/Write
The 8-bit Condition Code register contains the interrupt masks and four flags representative
of the result of the instruction just executed. This register can also be handled by the PUSH
and POP instructions.
These bits can be individually tested and/or controlled by specific instructions.
Arithmetic management bits
Bit 4 = H Half carry.
This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during
an ADD or ADC instructions. It is reset by hardware during the same instructions.
0: No half carry has occurred.
1: A half carry has occurred.
This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD
arithmetic subroutines.
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Central processing unit
ST72344xx, ST2345xx
Bit 2 = N Negative.
This bit is set and cleared by hardware. It is representative of the result sign of the last
th
arithmetic, logical or data manipulation. It’s a copy of the result 7 bit.
0: The result of the last operation is positive or null.
1: The result of the last operation is negative
(that is, the most significant bit is a logic 1).
This bit is accessed by the JRMI and JRPL instructions.
Bit 1 = Z Zero.
This bit is set and cleared by hardware. This bit indicates that the result of the last
arithmetic, logical or data manipulation is zero.
0: The result of the last operation is different from zero.
1: The result of the last operation is zero.
This bit is accessed by the JREQ and JRNE test instructions.
Bit 0 = C Carry/borrow.
This bit is set and cleared by hardware and software. It indicates an overflow or an
underflow has occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.
This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC
instructions. It is also affected by the “bit test and branch”, shift and rotate instructions.
Interrupt management bits
Bits 5,3 = I1, I0 Interrupt
The combination of the I1 and I0 bits gives the current interrupt software priority.
Table 6.
Priority
Interrupt software priority
I1
I0
Level 0 (main)
Level 1
1
0
0
1
0
1
0
1
Level 2
Level 3 (= interrupt disable)
These two bits are set/cleared by hardware when entering in interrupt. The loaded value is
given by the corresponding bits in the interrupt software priority registers (IxSPR). They can
be also set/cleared by software with the RIM, SIM, IRET, HALT, WFI and PUSH/POP
instructions.
See the interrupt management chapter for more details.
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Central processing unit
6.3.2
Stack pointer (SP)
Reset value: 01 FFh
15
8
0
0
0
0
0
0
0
1
Read/Write
7
0
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
Read/Write
The Stack pointer is a 16-bit register which is always pointing to the next free location in the
stack. It is then decremented after data has been pushed onto the stack and incremented
before data is popped from the stack (see Figure 12).
Since the stack is 256 bytes deep, the 8 most significant bits are forced by hardware.
Following an MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack pointer
contains its reset value (the SP7 to SP0 bits are set) which is the stack higher address.
The least significant byte of the Stack pointer (called S) can be directly accessed by an LD
instruction.
Note:
When the lower limit is exceeded, the Stack pointer wraps around to the stack upper limit,
without indicating the stack overflow. The previously stored information is then overwritten
and therefore lost. The stack also wraps in case of an underflow.
The stack is used to save the return address during a subroutine call and the CPU context
during an interrupt. The user may also directly manipulate the stack by means of the PUSH
and POP instructions. In the case of an interrupt, the PCL is stored at the first location
pointed to by the SP. Then the other registers are stored in the next locations as shown in
Figure 12.
■
When an interrupt is received, the SP is decremented and the context is pushed on the
stack.
■
On return from interrupt, the SP is incremented and the context is popped from the
stack.
A subroutine call occupies two locations and an interrupt five locations in the stack area.
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Central processing unit
ST72344xx, ST2345xx
Figure 12. Stack manipulation example
CALL
Subroutine
RET
or RSP
PUSH Y
POP Y
IRET
Interrupt
Event
@ 0100h
SP
SP
SP
Y
CC
A
CC
A
CC
A
X
X
X
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
SP
SP
PCH
PCL
PCH
PCL
SP
@ 01FFh
Stack Higher Address = 01FFh
0100h
Stack Lower Address =
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Supply, reset and clock management
7
Supply, reset and clock management
The device includes a range of utility features for securing the application in critical
situations (for example in case of a power brown-out), and reducing the number of external
components.
7.1
Main features
■
Clock management
–
–
–
–
1 MHz high-accuracy internal RC oscillator (enabled by option byte)
1 to 16 MHz External crystal/ceramic resonator (enabled by option byte)
External Clock Input (enabled by option byte)
PLL for multiplying the frequency by 8 or 4 (enabled by option byte)
■
■
Reset sequence manager (RSM)
System integrity management (SI)
–
Main supply low voltage detection (LVD) with reset generation (enabled by option
byte)
–
Auxiliary voltage detector (AVD) with interrupt capability for monitoring the main
supply (enabled by option byte)
Figure 13. Clock, reset and supply block diagram
RCCRH/RCCRL Register
MAIN CLOCK
CONTROLLER
fCPU
CR9 CR8 CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0
WITH REAL-TIME
CLOCK(MCC/RTC)
Tunable
External Clock (0.5-8 MHz)
RC Oscillator
RC Clock (1 MHz)
1 MHz
fOSC2
8 MHz
PLL 1 MHz --> 8 MHz
/2
DIVIDER
/2
4 MHz
PLL 1 MHz --> 4 MHz
DIVIDER*
PLL Clock 8/4 MHz
OSC Option bit
PLLx4x8
Option bit
DIV2EN
OSC, PLLOFF
OSCRANGE[2:0]
Option bits
Option bit*
OSC
1-16 MHz
OSC1
OSC2
Crystal OSC (0.5-8 MHz)
/2
DIVIDER
*not available if PLLx4 is enabled
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7.2
Phase locked loop
The PLL can be used to multiply a 1 MHz frequency from the RC oscillator or the external
clock by 4 or 8 to obtain f of 4 or 8 MHz. The PLL is enabled and the multiplication factor
OSC
of 4 or 8 is selected by 3 option bits. Refer to Table 7 for the PLL configuration depending on
the required frequency and the application voltage. Refer to Section 15.1 for the option byte
description.
Table 7.
PLL configurations
Target ratio
VDD
PLL ratio
DIV2
x4(1)
x4
2.7 V - 3.65 V
x4
x8
x8
OFF
ON
3.3 V - 5.5 V
x8
OFF
1. For a target ratio of x4 between 3.3 V - 3.65 V, this is the recommended configuration.
Figure 14. PLL output frequency timing diagram
LOCKED bit set
4/8 x
input
freq.
tSTAB
tLOCK
tSTARTUP
t
When the PLL is started, after reset or wakeup from Halt mode or AWUFH mode, it outputs
the clock after a delay of t
.
STARTUP
When the PLL output signal reaches the operating frequency, the LOCKED bit in the
SICSCR register is set. Full PLL accuracy (ACC ) is reached after a stabilization time of
PLL
t
(see Figure 14).
STAB
Refer to Section 7.6.5: Register description for a description of the LOCKED bit in the
SICSR register.
Caution:
Caution:
The PLL is not recommended for applications where timing accuracy is required.
When the RC oscillator and the PLL are enabled, it is recommended to calibrate this clock
through the RCCRH and RCCRL registers.
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Supply, reset and clock management
7.3
Multioscillator (MO)
The main clock of the ST7 can be generated by three different source types coming from the
multioscillator block:
■
■
■
an external source
4 crystal or ceramic resonator oscillators
an internal high-accuracy RC oscillator
Each oscillator is optimized for a given frequency range in terms of consumption and is
selectable through the option byte. The associated hardware configurations are shown in
Table 8. Refer to Section 13: Electrical characteristics for more details.
Caution:
The OSC1 and/or OSC2 pins must not be left unconnected. For the purposes of Failure
Mode and Effect Analysis, it should be noted that if the OSC1 and/or OSC2 pins are left
unconnected, the ST7 main oscillator may start and, in this configuration, could generate an
f
clock frequency in excess of the allowed maximum (>16 MHz), putting the ST7 in an
OSC
unsafe/undefined state. The product behavior must therefore be considered undefined when
the OSC pins are left unconnected.
7.3.1
7.3.2
External clock source
In this external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle
has to drive the OSC1 pin while the OSC2 pin is tied to ground.
Crystal/ceramic oscillators
This family of oscillators has the advantage of producing a very accurate rate on the main
clock of the ST7. The selection within a list of 4 oscillators with different frequency ranges
has to be done by option byte in order to reduce consumption (refer to Section 15.1: Option
bytes for more details on the frequency ranges). In this mode of the multi-oscillator, the
resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. The loading
capacitance values must be adjusted according to the selected oscillator.
These oscillators are not stopped during the reset phase to avoid losing time in the oscillator
startup phase.
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Table 8.
ST7 clock sources
Hardware configuration
ST7
OSC1
OSC2
EXTERNAL
SOURCE
ST7
OSC1
OSC2
C
C
L2
L1
LOAD
CAPACITORS
ST7
OSC1
OSC2
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Supply, reset and clock management
7.3.3
Internal RC oscillator
The device contains a high-precision internal RC oscillator. It must be calibrated to obtain
the frequency required in the application. This is done by software writing a calibration value
in the RCCRH and RCCRL Registers.
Whenever the microcontroller is reset, the RCCR returns to its default value (FF 03h), i.e.
each time the device is reset, the calibration value must be loaded in the RCCRH and
RCCRL registers. Predefined calibration values are stored in XFlash for 3 and 5V V
supply voltages at 25 °C, as shown in the following table:
DD
Table 9.
Calibration values
Conditions
DD = 5 V
RCCR
Address
V
RCCR0
TA = 25 °C
BEE0, BEE1
fRC = 1 MHz
VDD = 3 V
RCCR1
TA = 25 °C
BEE4, BEE5
fRC = 1 MHz
Note:
To improve clock stability, it is recommended to place a decoupling capacitor between the
and V pins.
V
DD
SS
These two 10-bit values are systematically programmed by ST.
RCCR0 and RCCR1 calibration values will be erased if the read-out protection bit is reset
after it has been set. See Section 4.5: Memory protection.
Caution:
If the voltage or temperature conditions change in the application, the frequency may need
to be recalibrated.
Refer to application note AN1324 for information on how to calibrate the RC frequency using
an external reference signal.
7.4
Register description
7.4.1
RC control register (RCCRH)
Reset value: 1111 1111 (FFh)
7
0
CR9
CR8
CR7
CR6
CR5
CR4
CR3
CR2
Read/Write
Bits 7:0 = CR[9:2] RC oscillator frequency adjustment bits
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ST72344xx, ST2345xx
7.4.2
RC control register (RCCRL)
Reset value: 0000 0011 (03h)
7
0
0
0
0
0
0
0
CR1
CR0
Read/Write
Bits 7:2 = Reserved, must be kept cleared.
Bits 1:0 = CR[1:0] RC Oscillator Frequency Adjustment Bits
This 10-bit value must be written immediately after reset to adjust the RC oscillator
frequency in order to obtain the specified accuracy. The application can store the
correct value for each voltage range in EEPROM and write it to this register at startup.
0000h = maximum available frequency
03FFh = lowest available frequency
Note:
To tune the oscillator, write a series of different values in the register until the correct
frequency is reached. The fastest method is to use a dichotomy starting with 200h.
7.5
Reset sequence manager (RSM)
7.5.1
Introduction
The reset sequence manager includes three reset sources as shown in Figure 16:
■
■
■
External RESET source pulse
Internal LVD reset (low voltage detection)
Internal watchdog reset
Note:
A reset can also be triggered following the detection of an illegal opcode or prebyte code.
Refer to Section 12.2.1: Illegal opcode reset on page 196 for further details.
These sources act on the RESET pin and it is always kept low during the delay phase.
The reset service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory
map.
The basic reset sequence consists of 3 phases as shown in Figure 15:
■
■
■
Active phase depending on the reset source
256 or 4096 CPU clock cycle delay (selected by option byte)
reset vector fetch
Caution:
When the ST7 is unprogrammed or fully erased, the Flash is blank and the reset vector is
not programmed. For this reason, it is recommended to keep the RESET pin in low state
until programming mode is entered, in order to avoid unwanted behavior.
The 256 or 4096 CPU clock cycle delay allows the oscillator to stabilize and ensures that
recovery has taken place from the Reset state. The shorter or longer clock cycle delay
should be selected by option byte to correspond to the stabilization time of the external
oscillator used in the application (see Section 15.1: Option bytes).
The reset vector fetch phase duration is 2 clock cycles.
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Supply, reset and clock management
Figure 15. reset sequence phases
RESET
Internal Reset
256 or 4096 clock cycles
Fetch
vector
Active phase
7.5.2
Asynchronous external RESET pin
The RESET pin is both an input and an open-drain output with integrated R weak pull-up
ON
resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It
can be pulled low by external circuitry to reset the device. See Section 13: Electrical
characteristics for more details.
A reset signal originating from an external source must have a duration of at least t
h(RSTL)in
in order to be recognized (see Figure 17). This detection is asynchronous and therefore the
MCU can enter reset state even in Halt mode.
Figure 16. Reset block diagram
VDD
R
ON
INTERNAL
RESET
Filter
RESET
WATCHDOG RESET
ILLEGAL OPCODE RESET (1)
LVD RESET
PULSE
GENERATOR
1. See Section 12.2.1: Illegal opcode reset for more details on illegal opcode reset conditions.
The RESET pin is an asynchronous signal which plays a major role in EMS performance. In
a noisy environment, it is recommended to follow the guidelines mentioned in Section 13:
Electrical characteristics.
If the external RESET pulse is shorter than t
(see short ext. Reset in Figure 17),
w(RSTL)out
the signal on the RESET pin may be stretched. Otherwise the delay will not be applied (see
long ext. Reset in Figure 17). Starting from the external RESET pulse recognition, the
device RESET pin acts as an output that is pulled low during at least t
.
w(RSTL)out
7.5.3
External power-on reset
If the LVD is disabled by option byte, to start up the microcontroller correctly, the user must
ensure by means of an external reset circuit that the reset signal is held low until V is over
DD
the minimum level specified for the selected f
frequency (see Section 13.3: Operating
OSC
conditions).
A proper reset signal for a slow rising V supply can generally be provided by an external
DD
RC network connected to the RESET pin.
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7.5.4
Internal low-voltage detector (LVD) reset
Two different reset sequences caused by the internal LVD circuitry can be distinguished:
■
■
Power-on reset
Voltage-drop reset
The device RESET pin acts as an output that is pulled low when V <V (rising edge) or
DD
IT+
V
<V (falling edge) as shown in Figure 17.
DD
IT-
The LVD filters spikes on V larger than t
to avoid parasitic resets.
g(VDD)
DD
Note:
It is recommended to make sure that the V supply voltage rises monotonously when the
DD
device is exiting from Reset, to ensure the application functions properly.
7.5.5
Internal watchdog reset
The reset sequence generated by a internal Watchdog counter overflow is shown in
Figure 17.
Starting from the Watchdog counter underflow, the device RESET pin acts as an output that
is pulled low during at least t
.
w(RSTL)out
Figure 17. Reset sequences
VDD
VIT+(LVD)
VIT-(LVD)
LVD
RESET
SHORT EXT.
RESET
LONG EXT.
RESET
WATCHDOG
RESET
Run
Run
Run
Run
Run
ACTIVE
PHASE
ACTIVE
PHASE
ACTIVE
PHASE
ACTIVE PHASE
tw(RSTL)out
th(RSTL)in
tw(RSTL)out
tw(RSTL)out
th(RSTL)in
DELAY
EXTERNAL
RESET
SOURCE
RESET PIN
WATCHDOG
RESET
WATCHDOG UNDERFLOW
INTERNAL RESET (256 or 4096 TCPU
)
VECTOR FETCH
7.6
System integrity management (SI)
The system integrity management block contains the low-voltage detector (LVD) and
auxiliary-voltage detector (AVD) functions. It is managed by the SICSR register.
Note:
A reset can also be triggered following the detection of an illegal opcode or prebyte code.
Refer to Section 12.2.1: Illegal opcode reset for further details.
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Supply, reset and clock management
7.6.1
Low-voltage detector (LVD)
The low-voltage detector function (LVD) generates a static reset when the V supply
DD
voltage is below a V reference value. This means that it secures the power-up as well as
IT-
the power-down keeping the ST7 in reset.
The V reference value for a voltage drop is lower than the V reference value for power-
IT-
IT+
on, in order to avoid a parasitic reset when the MCU starts running and sinks current on the
supply (hysteresis).
The LVD Reset circuitry generates a reset when V is below:
DD
■
■
V
V
when V is rising
DD
IT+
IT-
when V is falling
DD
The LVD function is illustrated in Figure 18.
The LVD is an optional function which can be selected by option byte.
LVD threshold configuration: the voltage threshold can be configured by option byte to be
Note:
low, medium or high. The configuration should be chosen depending on the f
and V
OSC
DD
parameters in the application. When correctly configured, the LVD ensures safe power-on
and power-off conditions for the microcontroller without using any external components.
To determine which LVD thresholds to use:
■
■
Define the minimum operating voltage for the application V
.
APP(min)
Refer to Section 13: Electrical characteristics to get the minimum operating voltage for
the MCU at the application frequency V
.
DD(min)
■
Select the LVD threshold that ensures that the internal reset is released at V
APP(min)
and activated at V
.
DD(MCUmin)
During a low-voltage detector reset, the RESET pin is held low, thus permitting the MCU to
reset other devices.
Figure 18. Low voltage detector vs. reset
VDD
Vhys
VIT+(LVD)
VIT-((LVD)
RESET
7.6.2
Auxiliary-voltage detector (AVD)
The AVD is used to provide the application with an early warning of a drop in voltage. If
enabled, an interrupt can be generated allowing software to shut down safely before the LVD
resets the microcontroller. See Figure 19.
Note:
The AVD function is active only if the LVD is enabled through the option byte (see
Section 15.1: Option bytes). The activation level of the AVD is fixed at around 0.5 mV above
the selected LVD threshold.
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In the case of a drop in voltage below V
, the AVDF flag is set and an interrupt request
IT-(AVD)
is issued.
If V rises above the V
threshold voltage the AVDF bit is cleared automatically by
IT+(AVD)
DD
hardware. No interrupt is generated, and therefore software should poll the AVDF bit to
detect when the voltage has risen, and resume normal processing.
Figure 19. Using the AVD to monitor V
VDD
DD
Early warning interrupt
(Power has dropped, MCU not
not yet in reset)
Vhys
VIT+(AVD)
VIT-(AVD)
VIT-(LVD)
1
0
AVDF bit
0
RESET VALUE
1
AVD INTERRUPT
REQUEST
IF AVDIE bit = 1
INTERRUPT PROCESS
LVD RESET
7.6.3
7.6.4
Low-power modes
Table 10. Low-power mode description
Mode
Description
Wait
Halt
No effect on SI. AVD interrupts cause the device to exit from Wait mode.
The SICSR register is frozen.
Interrupts
The AVD interrupt event generates an interrupt if the corresponding AVDIE bit is set and the
interrupt mask in the CC register is reset (RIM instruction).
Table 11. Interrupt event
Enable
control bit
Exit from
Wait
Exit from
Halt
Interrupt event
Event flag
AVD event
AVDF
AVDIE
Yes
No
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Supply, reset and clock management
7.6.5
Register description
System integrity (SI) control/status register (SICSR)
Reset value: 000x 000x (xxh)
7
0
0
PDVDIE
AVDF
LVDRF
LOCKED
0
0
WDGRF
Read/Write
Bit 7 = Reserved, must be kept cleared.
Bit 6 = AVDIE Voltage detector interrupt enable
This bit is set and cleared by software. It enables an interrupt to be generated when the
AVDF flag goes from 0 to 1. The pending interrupt information is automatically cleared
when software enters the AVD interrupt routine.
0: PDVD interrupt disabled
1: PDVD interrupt enabled
Bit 5 = AVDF Voltage Detector flag
This read-only bit is set and cleared by hardware. If the AVDIE bit is set, an interrupt
request is generated when the AVDF bit goes from 0 to 1. Refer to Figure 19 and to
Section 7.6.2 for additional details.
0: V over V
threshold
threshold
IT-(AVD)
DD
IT+(AVD)
1: V under V
DD
Bit 4 = LVDRF LVD reset flag
This bit indicates that the last Reset was generated by the LVD block. It is set by
hardware (LVD reset) and cleared by software (writing zero). See WDGRF flag
description for more details. When the LVD is disabled by OPTION BYTE, the LVDRF
bit value is undefined.
Bit 3 = LOCKED PLL Locked Flag
This bit is set and cleared by hardware. It is set automatically when the PLL reaches its
operating frequency.
0: PLL not locked
1: PLL locked
Bits 2:1 = Reserved, must be kept cleared.
Bit 0 = WDGRF Watchdog reset flag
This bit indicates that the last Reset was generated by the Watchdog peripheral. It is
set by hardware (watchdog reset) and cleared by software (writing zero) or an LVD
Reset (to ensure a stable cleared state of the WDGRF flag when CPU starts).
Combined with the LVDRF flag information, the flag description is given by the following
table.
Table 12. LVDRF and WDGRF description
Reset sources
LVDRF
WDGRF
External RESET pin
Watchdog
0
0
1
0
1
LVD
X
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Application notes
ST72344xx, ST2345xx
The LVDRF flag is not cleared when another reset type occurs (external or watchdog), the
LVDRF flag remains set to keep trace of the original failure.
In this case, a watchdog reset can be detected by software while an external reset can not.
Caution:
When the LVD is not activated with the associated option byte, the WDGRF flag can not be
used in the application.
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Interrupts
8
Interrupts
8.1
Introduction
The ST7 enhanced interrupt management provides the following features:
■
■
■
Hardware interrupts
Software interrupt (TRAP)
Nested or concurrent interrupt management with flexible interrupt priority and level
management:
–
–
–
Up to 4 software programmable nesting levels
Up to 16 interrupt vectors fixed by hardware
2 non maskable events: reset, TRAP
This interrupt management is based on:
■
■
■
Bit 5 and bit 3 of the CPU CC register (I1:0),
Interrupt software priority registers (ISPRx),
Fixed interrupt vector addresses located at the high addresses of the memory map
(FFE0h to FFFFh) sorted by hardware priority order.
This enhanced interrupt controller guarantees full upward compatibility with the standard
(not nested) ST7 interrupt controller.
8.2
Masking and processing flow
The interrupt masking is managed by the I1 and I0 bits of the CC register and the ISPRx
registers which give the interrupt software priority level of each interrupt vector (see
Table 6). The processing flow is shown in Figure 20.
When an interrupt request has to be serviced:
■
■
■
Normal processing is suspended at the end of the current instruction execution.
The PC, X, A and CC registers are saved onto the stack.
I1 and I0 bits of CC register are set according to the corresponding values in the ISPRx
registers of the serviced interrupt vector.
■
The PC is then loaded with the interrupt vector of the interrupt to service and the first
instruction of the interrupt service routine is fetched (refer to “Interrupt Mapping” table
for vector addresses).
The interrupt service routine should end with the IRET instruction which causes the
contents of the saved registers to be recovered from the stack.
Note:
As a consequence of the IRET instruction, the I1 and I0 bits will be restored from the stack
and the program in the previous level will resume.
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Interrupts
ST72344xx, ST2345xx
Table 13. Interrupt software priority levels
Interrupt software priority
Level
I1
I0
1
0
0
1
0
1
0
1
Level 0 (main)
Level 1
Low
Level 2
High
Level 3 (= interrupt disable)
Figure 20. Interrupt processing flowchart
PENDING
INTERRUPT
Y
Y
RESET
TRAP
N
Interrupt has the same or a
lower software priority
than current one
N
I1:0
FETCH NEXT
INSTRUCTION
THE INTERRUPT
STAYS PENDING
Y
“IRET”
N
RESTORE PC, X, A, CC
FROM STACK
EXECUTE
INSTRUCTION
STACK PC, X, A, CC
LOAD I1:0 FROM INTERRUPT SW REG.
LOAD PC FROM INTERRUPT VECTOR
Servicing pending interrupts
As several interrupts can be pending at the same time, the interrupt to be taken into account
is determined by the following two-step process:
■
■
the highest software priority interrupt is serviced,
if several interrupts have the same software priority, then the interrupt with the highest
hardware priority is serviced first.
Figure 21 describes this decision process.
Figure 21. Priority decision process
PENDING
INTERRUPTS
Different
Same
SOFTWARE
PRIORITY
HIGHEST SOFTWARE
PRIORITY SERVICED
HIGHEST HARDWARE
PRIORITY SERVICED
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Interrupts
When an interrupt request is not serviced immediately, it is latched and then processed
when its software priority combined with the hardware priority becomes the highest one.
Note:
1
2
The hardware priority is exclusive while the software one is not. This allows the previous
process to succeed with only one interrupt.
TLI, reset and TRAP can be considered as having the highest software priority in the
decision process.
Different interrupt vector sources
Two interrupt source types are managed by the ST7 interrupt controller: the non-maskable
type (reset, TRAP) and the maskable type (external or from internal peripherals).
Non-maskable sources
These sources are processed regardless of the state of the I1 and I0 bits of the CC register
(see Figure 20). After stacking the PC, X, A and CC registers (except for reset), the
corresponding vector is loaded in the PC register and the I1 and I0 bits of the CC are set to
disable interrupts (level 3). These sources allow the processor to exit Halt mode.
■
TRAP (non-maskable software interrupt)
This software interrupt is serviced when the TRAP instruction is executed. It will be serviced
according to the flowchart in Figure 20.
■
reset
The reset source has the highest priority in the ST7. This means that the first current routine
has the highest software priority (level 3) and the highest hardware priority.
See the reset chapter for more details.
Maskable sources
Maskable interrupt vector sources can be serviced if the corresponding interrupt is enabled
and if its own interrupt software priority (in ISPRx registers) is higher than the one currently
being serviced (I1 and I0 in CC register). If any of these two conditions is false, the interrupt
is latched and thus remains pending.
■
External interrupts
External interrupts allow the processor to exit from Halt low-power mode. External
interrupt sensitivity is software selectable through the External Interrupt Control register
(EICR).
External interrupt triggered on edge will be latched and the interrupt request
automatically cleared upon entering the interrupt service routine.
If several input pins of a group connected to the same interrupt line are selected
simultaneously, these will be logically ORed.
■
Peripheral interrupts
Usually, the peripheral interrupts cause the MCU to exit from Halt mode except those
mentioned in the “Interrupt Mapping” table. A peripheral interrupt occurs when a
specific flag is set in the peripheral status registers and if the corresponding enable bit
is set in the peripheral control register.
The general sequence for clearing an interrupt is based on an access to the status
register followed by a read or write to an associated register.
Note:
The clearing sequence resets the internal latch. A pending interrupt (i.e. waiting for being
serviced) will therefore be lost if the clear sequence is executed.
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8.3
Interrupts and low-power modes
All interrupts allow the processor to exit the Wait low-power mode. On the contrary, only
external and other specified interrupts allow the processor to exit from the Halt modes (see
column “Exit from Halt” in Table 17: Interrupt mapping). When several pending interrupts are
present while exiting Halt mode, the first one serviced can only be an interrupt with exit from
Halt mode capability and it is selected through the same decision process shown in
Figure 21.
Note:
If an interrupt, that is not able to Exit from Halt mode, is pending with the highest priority
when exiting Halt mode, this interrupt is serviced after the first one serviced.
8.4
Concurrent & nested management
The following Figure 22 and Figure 23 show two different interrupt management modes. The
first is called concurrent mode and does not allow an interrupt to be interrupted, unlike the
nested mode in Figure 23. The interrupt hardware priority is given in this order from the
lowest to the highest: MAIN, IT4, IT3, IT2, IT1, IT0, TLI. The software priority is given for
each interrupt.
Warning: A stack overflow may occur without notifying the software of
the failure.
Figure 22. Concurrent interrupt management
SOFTWARE
PRIORITY
LEVEL
I1
I0
TRAP
3
1 1
1 1
1 1
1 1
1 1
1 1
IT0
3
IT1
IT1
3
IT2
3
IT3
3
RIM
IT4
3
MAIN
MAIN
3/0
11 / 10
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Interrupts
Figure 23. Nested interrupt management
SOFTWARE
PRIORITY
LEVEL
I1
I0
TRAP
3
1 1
IT0
3
1 1
0 0
0 1
1 1
1 1
IT1
IT1
2
IT2
IT2
1
IT3
3
RIM
IT4
IT4
3
MAIN
MAIN
3/0
11 / 10
10
8.5
Interrupt register description
8.5.1
CPU CC register interrupt bits
Reset value: 111x 1010 (xAh)
7
0
1
1
I1
H
I0
Read/Write
Bits 5, 3 = I1, I0 Software interrupt priority
N
Z
C
These two bits indicate the current interrupt software priority.
Table 14. Interrupt software priority
Priority
Level
I1
I0
Level 0 (main)
Level 1
1
0
0
1
0
1
0
1
Low
Level 2
High
Level 3 (= interrupt disable(1)
)
1. TRAP and reset events can interrupt a level 3 program.
These two bits are set/cleared by hardware when entering in interrupt. The loaded value is
given by the corresponding bits in the interrupt software priority registers (ISPRx).
They can be also set/cleared by software with the RIM, SIM, HALT, WFI, IRET and
PUSH/POP instructions (see Table 16: Dedicated interrupt instruction set).
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Interrupts
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8.5.2
Interrupt software priority registers (ISPRX)
Reset value: 1111 1111 (FFh)
7
0
ISPR0
ISPR1
ISPR2
ISPR3
I1_3
I1_7
I1_11
1
I0_3
I0_7
I0_11
1
I1_2
I1_6
I1_10
1
I0_2
I0_6
I0_10
1
I1_1
I1_5
I0_1
I0_5
I1_0
I1_4
I0_0
I0_4
I1_9
I0_9
I1_8
I0_8
I1_13
I0_13
I1_12
I0_12
Read/Write (bits 7:4 of ISPR3 are read only)
These four registers contain the interrupt software priority of each interrupt vector.
Each interrupt vector (except reset and TRAP) has corresponding bits in these
■
registers where its own software priority is stored. This correspondence is shown in the
following table.
Table 15. Interrupt vector addresses
Vector address
ISPRx bits
FFFBh-FFFAh
FFF9h-FFF8h
...
I1_0 and I0_0 bits*
I1_1 and I0_1 bits
...
FFE1h-FFE0h
I1_13 and I0_13 bits
■
■
Each I1_x and I0_x bit value in the ISPRx registers has the same meaning as the I1
and I0 bits in the CC register.
Level 0 can not be written (I1_x=1, I0_x=0). In this case, the previously stored value is
kept. (example: previous = CFh, write = 64h, result = 44h)
The reset, and TRAP vectors have no software priorities. When one is serviced, the I1 and
I0 bits of the CC register are both set.
Caution:
If the I1_x and I0_x bits are modified while the interrupt x is executed, the following behavior
has to be considered: If the interrupt x is still pending (new interrupt or flag not cleared) and
the new software priority is higher than the previous one, the interrupt x is re-entered.
Otherwise, the software priority stays unchanged up to the next interrupt request (after the
IRET of the interrupt x).
Table 16. Dedicated interrupt instruction set
Instruction
HALT
New description
Function/example
I1
H
I0
N
Z
C
Entering Halt mode
Interrupt routine return
Jump if I1:0=11 (level 3)
Jump if I1:0<>11
1
0
IRET
Pop CC, A, X, PC
I1:0=11 ?
I1
H
I0
N
Z
C
JRM
JRNM
POP CC
I1:0<>11 ?
Pop CC from the stack
Mem => CC
I1
H
I0
N
Z
C
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Table 16. Dedicated interrupt instruction set (continued)
Instruction New description Function/example
RIM
I1
H
I0
N
Z
C
Enable interrupt (level 0 set) Load 10 in I1:0 of CC
Disable interrupt (level 3 set) Load 11 in I1:0 of CC
1
0
SIM
1
1
1
1
1
0
TRAP
WFI
Software trap
Software NMI
Wait for interrupt
Note:
During the execution of an interrupt routine, the HALT, POPCC, RIM, SIM and WFI
instructions change the current software priority up to the next IRET instruction or one of the
previously mentioned instructions.
Table 17. Interrupt mapping
Source
block
Register Priority Exit from
Address
vector
No.
Description
label
order
Halt (1)
Reset
Reset
yes
no
FFFEh-FFFFh
FFFCh-FFFDh
FFFAh-FFFBh
FFF8h-FFF9h
FFF6h-FFF7h
FFF4h-FFF5h
FFF2h-FFF3h
FFF0h-FFF1h
FFEEh-FFEFh
N/A
TRAP/ICD Software or ICD interrupt
AWU Auto wakeup interrupt
MCC/RTC RTC time base interrupt
0
1
2
3
4
5
6
AWUCSR
MCCSR
N/A
yes
yes
yes
yes
yes
yes
no
Highest
priority
ei0
ei1
ei2
ei3
External interrupt Port PA3, PE1
External interrupt Port PF2:0
External interrupt Port PB3:0
External interrupt Port PB4
N/A
N/A
N/A
I2C3SNS I2C3SNS address 3 interrupt
I2C3SSR
I2C3SNS address 1 & 2
7
I2C3SNS
interrupt
no
FFECh-FFEDh
8
9
SPI
SPI peripheral interrupts
SPISR
TASR
yes(2)
no
FFEAh-FFEBh
FFE8h-FFE9h
FFE6h-FFE7h
FFE4h-FFE5h
TIMER A TIMER A peripheral interrupts
Lowest
priority
10 TIMER B TIMER B peripheral interrupts
TBSR
SCISR
no
11
12
13
SCI
AVD
I2C
SCI peripheral interrupt
no
Auxiliary-voltage-detector
interrupt
SICSR
no
no
FFE2h-FFE3h
FFE0h-FFE1h
I2C peripheral interrupt
I2CSRx
1. Valid for Halt and Active-halt modes except for the MCC/RTC interrupt source which exits from Active-halt
mode only and AWU interrupt which exits from AWUFH mode only.
2. Exit from Halt possible when SPI is in slave mode.
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8.6
External interrupts
8.6.1
I/O port interrupt sensitivity
The external interrupt sensitivity is controlled by the IPA, IPB and ISxx bits of the EICR
register (Figure 24). This control allows to have up to 4 fully independent external interrupt
source sensitivities.
Each external interrupt source can be generated on four (or five) different events on the pin:
■
■
■
■
■
Falling edge
Rising edge
Falling and rising edge
Falling edge and low level
Rising edge and high level (only for ei0 and ei2)
To guarantee correct functionality, the sensitivity bits in the EICR register can be modified
only when the I1 and I0 bits of the CC register are both set to 1 (level 3). This means that
interrupts must be disabled before changing sensitivity.
The pending interrupts are cleared by writing a different value in the ISx[1:0], IPA or IPB bits
of the EICR.
Figure 24. External interrupt control bits
PORT A3, E1 INTERRUPTS
EICR
IS20 IS21
PAOR.3
PADDR.3
PA3
PE1
ei0 INTERRUPT SOURCE
SENSITIVITY
CONTROL
PA3
IPA BIT
EICR
PORT F [2:0] INTERRUPTS
IS20
IS21
PFOR.2
PF2
PF1
PFDDR.2
ei1 INTERRUPT SOURCE
SENSITIVITY
CONTROL
PF2
PF0
EICR
PORT B [3:0] INTERRUPTS
IS10
IS11
PB3
PBOR.3
PBDDR.3
ei2 INTERRUPT SOURCE
PB2
PB1
PB0
SENSITIVITY
CONTROL
PB3
IPB BIT
EICR
PORT B4 INTERRUPT
IS10
IS11
PBOR.4
PBDDR.4
ei3 INTERRUPT SOURCE
SENSITIVITY
CONTROL
PB4
PB4
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8.7
External interrupt control register (EICR)
Reset value: 0000 0000 (00h)
7
0
0
IS11
IS10
IPB
IS21
IS20
IPA
0
Read/Write
Bits 7:6 = IS1[1:0] ei2 and ei3 sensitivity
The interrupt sensitivity, defined using the IS1[1:0] bits, is applied to the following
external interrupts:
■
ei2 (port B3..0)
Table 18. External interrupt sensitivity (ei2)
Sensitivity
IS11
IS10
IPB bit =0
IPB bit =1
0
0
1
1
0
1
0
1
Falling edge & low level
Rising edge only
Rising edge & high level
Falling edge only
Falling edge only
Rising edge only
Rising and falling edge
■
ei3 (port B4)
Table 19. External interrupt sensitivity (ei3)
IS11
IS10
Sensitivity
0
0
1
1
0
1
0
1
Falling edge & low level
Rising edge only
Falling edge only
Rising and falling edge
These 2 bits can be written only when I1 and I0 of the CC register are both set to 1 (level 3).
Bit 5 = IPB Interrupt polarity for port B
This bit is used to invert the sensitivity of the port B [3:0] external interrupts. It can be
set and cleared by software only when I1 and I0 of the CC register are both set to 1
(level 3).
0: No sensitivity inversion
1: Sensitivity inversion
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Bits 4:3 = IS2[1:0] ei0 and ei1 sensitivity
The interrupt sensitivity, defined using the IS2[1:0] bits, is applied to the following
external interrupts:
■
ei0 (port A3, port E1)
Table 20. External interrupt sensitivity (ei0)
Sensitivity
IS21
IS20
IPA bit =0
IPA bit =1
0
0
1
1
0
1
0
1
Falling edge & low level
Rising edge only
Rising edge & high level
Falling edge only
Falling edge only
Rising edge only
Rising and falling edge
■
ei1 (port F2..0)
Table 21. External interrupt sensitivity (ei1)
IS21
IS20
Sensitivity
0
0
1
1
0
1
0
1
Falling edge & low level
Rising edge only
Falling edge only
Rising and falling edge
These 2 bits can be written only when I1 and I0 of the CC register are both set to 1 (level 3).
Bit 2 = IPA Interrupt polarity for ports A3 and E1
This bit is used to invert the sensitivity of the port A3 and E1 external interrupts. It can
be set and cleared by software only when I1 and I0 of the CC register are both set to 1
(level 3).
0: No sensitivity inversion
1: Sensitivity inversion
Bits 1:0 = Reserved, must always be kept cleared.
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Table 22. Nested interrupts register map and reset values
Address Register
7
6
5
4
3
2
1
0
(Hex.)
label
ei1
ei0
MCC + SI
AWU
0024h
ISPR0
Reset value
I1_3
1
I0_3
1
I1_2
1
I0_2
1
I1_1
1
I0_1
1
I1_0
1
I0_0
1
I2C3SNS
I2C3SNS
ei3
ei2
SPI
AVD
0025h
0026h
ISPR1
Reset value
I1_7
1
I0_7
1
I1_6
1
I0_6
1
I1_5
1
I0_5
1
I1_4
1
I0_4
1
SCI
TIMER B
TIMER A
ISPR2
Reset value
I1_11
1
I0_11
1
I1_10
1
I0_10
1
I1_9
1
I0_9
1
I1_8
1
I0_8
1
I2C
0027h
0028h
ISPR3
Reset value
I1_13
1
I0_13
1
I1_12
1
I0_12
1
1
1
1
1
EICR
Reset value
IS11
0
IS10
0
IPB
0
IS21
0
IS20
0
IPA
0
0
0
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ST72344xx, ST2345xx
9
Power-saving modes
9.1
Introduction
To give a large measure of flexibility to the application in terms of power consumption, five
main power saving modes are implemented in the ST7 (see Figure 25):
■
■
■
■
■
Slow
Wait (and Slow-Wait)
Active-halt
Auto-wakeup from Halt (AWUFH)
Halt
After a reset the normal operating mode is selected by default (Run mode). This mode
drives the device (CPU and embedded peripherals) by means of a master clock which is
based on the main oscillator frequency divided or multiplied by 2 (f
).
OSC2
From Run mode, the different power saving modes may be selected by setting the relevant
register bits or by calling the specific ST7 software instruction whose action depends on the
oscillator status.
Figure 25. Power saving mode transitions
High
Run
Slow
Wait
Slow-wait
Active-halt
Auto-wakeup from Halt
Halt
Low
Power consumption
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9.2
Slow mode
This mode has two targets:
■
■
To reduce power consumption by decreasing the internal clock in the device,
To adapt the internal clock frequency (f ) to the available supply voltage.
CPU
Slow mode is controlled by three bits in the MCCSR register: the SMS bit which enables or
disables Slow mode and two CPx bits which select the internal slow frequency (f ).
CPU
In this mode, the master clock frequency (f
) can be divided by 2, 4, 8 or 16. The CPU
OSC2
and peripherals are clocked at this lower frequency (f
).
CPU
Note:
Slow-wait mode is activated by entering Wait mode while the device is in Slow mode.
Figure 26. Slow mode clock transitions
f
/2
f
/4
f
OSC2
OSC2
OSC2
f
CPU
f
OSC2
00
01
CP1:0
SMS
Normal Run mode
request
New slow
frequency
request
9.3
Wait mode
Wait mode places the MCU in a low-power consumption mode by stopping the CPU.
This power saving mode is selected by calling the ‘WFI’ instruction.
All peripherals remain active. During Wait mode, the I[1:0] bits of the CC register are forced
to ‘10’, to enable all interrupts. All other registers and memory remain unchanged. The MCU
remains in Wait mode until an interrupt or reset occurs, whereupon the Program Counter
branches to the starting address of the interrupt or Reset service routine.
The MCU will remain in Wait mode until a Reset or an Interrupt occurs, causing it to wake
up. Refer to Figure 27.
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Figure 27. Wait mode flowchart
OSCILLATOR
PERIPHERALS
CPU
ON
ON
OFF
10
WFI INSTRUCTION
I[1:0] BITS
N
RESET
Y
N
INTERRUPT
Y
OSCILLATOR
PERIPHERALS
CPU
ON
OFF
ON
10
I[1:0] BITS
256 OR 4096 CPU CLOCK
CYCLE DELAY
OSCILLATOR
PERIPHERALS
CPU
ON
ON
ON
I[1:0] BITS
XX (1)
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Note:
Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the
CC register are set to the current software priority level of the interrupt routine and
recovered when the CC register is popped.
9.4
Halt mode
The Halt mode is the lowest power consumption mode of the MCU. It is entered by
executing the ‘HALT’ instruction when the OIE bit of the Main Clock Controller Status
register (MCCSR) is cleared (see Section 11.2: Main clock controller with real-time clock
and beeper (MCC/RTC) for more details on the MCCSR register) and when the AWUEN bit
in the AWUCSR register is cleared.
The MCU can exit Halt mode on reception of either a specific interrupt (see Table 17:
Interrupt mapping) or a reset. When exiting Halt mode by means of a reset or an interrupt,
the oscillator is immediately turned on and the 256 or 4096 CPU cycle delay is used to
stabilize the oscillator. After the start up delay, the CPU resumes operation by servicing the
interrupt or by fetching the reset vector which woke it up (see Figure 29).
When entering Halt mode, the I[1:0] bits in the CC register are forced to ‘10b’to enable
interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately.
In Halt mode, the main oscillator is turned off causing all internal processing to be stopped,
including the operation of the on-chip peripherals. All peripherals are not clocked except the
ones which get their clock supply from another clock generator (such as an external or
auxiliary oscillator).
The compatibility of Watchdog operation with Halt mode is configured by the “WDGHALT”
option bit of the option byte. The HALT instruction when executed while the Watchdog
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system is enabled, can generate a Watchdog reset (see Section 11.1: Window watchdog
(WWDG) for more details).
Figure 28. Halt timing overview
256 OR 4096 CPU
Run
Halt
Run
cycle delay
Reset
or
interrupt
Halt
instruction
[MCCSR.OIE=0]
Fetch
vector
Figure 29. Halt mode flowchart
HALT INSTRUCTION
(MCCSR.OIE=0)
(AWUCSR.AWUEN=0)
WATCHDOG
DISABLE
ENABLE
0
WDGHALT 1)
1
WATCHDOG
RESET
OSCILLATOR
OFF
OFF
OFF
10
PERIPHERALS 2)
CPU
I[1:0] BITS
N
RESET
Y
N
INTERRUPT 3)
Y
OSCILLATOR
PERIPHERALS
CPU
ON
OFF
ON
I[1:0] BITS
XX 4)
256 OR 4096 CPU CLOCK
CYCLE DELAY
OSCILLATOR
PERIPHERALS
CPU
ON
ON
ON
I[1:0] BITS
XX 4)
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Note:
1
2
3
WDGHALT is an option bit. See Section 15.1: Option bytes for more details.
Peripheral clocked with an external clock source can still be active.
Only some specific interrupts can exit the MCU from Halt mode (such as external interrupt).
Refer to Table 17: Interrupt mapping for more details.
4
Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the
CC register are set to the current software priority level of the interrupt routine and
recovered when the CC register is popped.
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Halt mode recommendations
■
Make sure that an external event is available to wake up the microcontroller from Halt
mode.
■
When using an external interrupt to wake up the microcontroller, reinitialize the
corresponding I/O as “Input Pull-up with Interrupt” before executing the HALT
instruction. The main reason for this is that the I/O may be wrongly configured due to
external interference or by an unforeseen logical condition.
■
■
For the same reason, reinitialize the level sensitiveness of each external interrupt as a
precautionary measure.
The opcode for the HALT instruction is 0x8E. To avoid an unexpected HALT instruction
due to a program counter failure, it is advised to clear all occurrences of the data value
0x8E from memory. For example, avoid defining a constant in ROM with the value
0x8E.
■
As the HALT instruction clears the interrupt mask in the CC register to allow interrupts,
the user may choose to clear all pending interrupt bits before executing the HALT
instruction. This avoids entering other peripheral interrupt routines after executing the
external interrupt routine corresponding to the wake-up event (reset or external
interrupt).
9.5
Active-halt mode
Active-halt mode is the lowest power consumption mode of the MCU with a real-time clock
available. It is entered by executing the ‘HALT’ instruction when MCC/RTC interrupt enable
flag (OIE bit in MCCSR register) is set and when the AWUEN bit in the AWUCSR register is
cleared (see Section 9.7: Register description).
Table 23. Power saving mode
MCCSR OIE bit
Power saving mode entered when HALT instruction is executed
Halt mode
Active-halt mode
0
1
The MCU can exit Active-halt mode on reception of the RTC interrupt and some specific
interrupts (see Table 17: Interrupt mapping) or a reset. When exiting Active-halt mode by
means of a reset a 4096 or 256 CPU cycle delay occurs (depending on the option byte).
After the start up delay, the CPU resumes operation by servicing the interrupt or by fetching
the reset vector which woke it up (see Figure 31).
When entering Active-halt mode, the I[1:0] bits in the CC register are cleared to enable
interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately.
In Active-Halt mode, only the main oscillator and its associated counter (MCC/RTC) are
running to keep a wake-up time base. All other peripherals are not clocked except those
which get their clock supply from another clock generator (such as external or auxiliary
oscillator).
The safeguard against staying locked in Active-halt mode is provided by the oscillator
interrupt.
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Note:
As soon as active halt is enabled, executing a HALT instruction while the Watchdog is active
does not generate a reset. This means that the device cannot spend more than a defined
delay in this power saving mode.
Figure 30. Active-halt timing overview
Active-
halt
256 OR 4096 cycle
delay (after reset)
Run
Run
Reset
or
interrupt
HALT
instruction
Fetch
vector
(Active-halt enabled)
Figure 31. Active-halt mode flowchart
OSCILLATOR
ON
HALT INSTRUCTION
(MCCSR.OIE=1)
(AWUCSR.AWUEN=0)
PERIPHERALS 2)
CPU
OFF
OFF
10
I[1:0] BITS
N
RESET
N
Y
INTERRUPT 3)
OSCILLATOR
PERIPHERALS
CPU
ON
OFF
ON
Y
I[1:0] BITS
XX 4)
256 OR 4096 CPU CLOCK
CYCLE DELAY
OSCILLATOR
PERIPHERALS
CPU
ON
ON
ON
I[1:0] BITS
XX 4)
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Note:
1
2
3
This delay occurs only if the MCU exits Active-Halt mode by means of a reset.
Peripheral clocked with an external clock source can still be active.
Only the RTC interrupt and some specific interrupts can exit the MCU from Active-halt mode
(such as external interrupt). Refer to Table 17 for more details.
4
Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits in the
CC register are set to the current software priority level of the interrupt routine and restored
when the CC register is popped.
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ST72344xx, ST2345xx
9.6
Auto-wakeup from Halt mode
Auto-wakeup from Halt (AWUFH) mode is similar to Halt mode with the addition of an
internal RC oscillator for wake-up. Compared to Active-Halt mode, AWUFH has lower power
consumption because the main clock is not kept running, but there is no accurate real-time
clock available.
It is entered by executing the HALT instruction when the AWUEN bit in the AWUCSR
register has been set and the OIE bit in the MCCSR register is cleared (see Section 11.2:
Main clock controller with real-time clock and beeper (MCC/RTC) for more details).
Figure 32. AWUFH mode block diagram
AWU RC
oscillator
to Timer input capture
f
AWU_RC
AWUFH
interrupt
AWUFH
/64
divider
prescaler
/1 .. 255
As soon as Halt mode is entered, and if the AWUEN bit has been set in the AWUCSR
register, the AWU RC oscillator provides a clock signal (f ). Its frequency is divided by
AWU_RC
a fixed divider and a programmable prescaler controlled by the AWUPR register. The output
of this prescaler provides the delay time. When the delay has elapsed the AWUF flag is set
by hardware and an interrupt wakes-up the MCU from Halt mode. At the same time the main
oscillator is immediately turned on and a 256 or 4096 cycle delay is used to stabilize it. After
this startup delay, the CPU resumes operation by servicing the AWUFH interrupt. The AWU
flag and its associated interrupt are cleared by software reading the AWUCSR register.
To compensate for any frequency dispersion of the AWU RC oscillator, it can be calibrated
by measuring the clock frequency f
and then calculating the right prescaler value.
AWU_RC
Measurement mode is enabled by setting the AWUM bit in the AWUCSR register in Run
mode. This connects internally f to the ICAP2 input of the 16-bit timer A, allowing the
AWU_RC
f
to be measured using the main oscillator clock as a reference timebase.
AWU_RC
Similarities with Halt mode
The following AWUFH mode behavior is the same as normal Halt mode:
■
■
■
The MCU can exit AWUFH mode by means of any interrupt with exit from Halt
capability or a reset (see Section 9.4: Halt mode).
When entering AWUFH mode, the I[1:0] bits in the CC register are forced to 10b to
enable interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately.
In AWUFH mode, the main oscillator is turned off causing all internal processing to be
stopped, including the operation of the on-chip peripherals. None of the peripherals are
clocked except those which get their clock supply from another clock generator (such
as an external or auxiliary oscillator like the AWU oscillator).
■
The compatibility of the Watchdog operation with the AWUFH mode is configured by
the WDGHALT option bit in the option byte. Depending on this setting, the HALT
instruction, when executed while the Watchdog system is enabled, can generate a
Watchdog reset.
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Power-saving modes
Figure 33. AWUF Halt timing diagram
t
AWU
Run mode
Halt mode
256 or 4096 t
Run mode
Clear
CPU
fCPU
fAWU_RC
by software
AWUFH interrupt
Figure 34. AWUFH mode flowchart
HALT INSTRUCTION
(MCCSR.OIE=0)
(AWUCSR.AWUEN=1)
ENABLE
WATCHDOG
0
DISABLE
WDGHALT (1)
1
AWU RC OSC
MAIN OSC
ON
OFF
OFF
OFF
10
WATCHDOG
RESET
PERIPHERALS (2)
CPU
I[1:0] BITS
N
RESET
Y
N
INTERRUPT (3)
AWU RC OSC
MAIN OSC
OFF
ON
Y
PERIPHERALS
CPU
I[1:0] BITS
OFF
ON
XX (4)
256 OR 4096 CPU CLOCK
CYCLE DELAY
AWU RC OSC
MAIN OSC
PERIPHERALS
CPU
OFF
ON
ON
ON
I[1:0] BITS
XX (4)
FETCH RESET VECTOR
OR SERVICE INTERRUPT
1. WDGHALT is an option bit. See Section 15.1: Option bytes for more details.
2. Peripheral clocked with an external clock source can still be active.
3. Only an AWUFH interrupt and some specific interrupts can exit the MCU from Halt mode (such as external
interrupt). Refer to Table 17: Interrupt mapping for more details.
4. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are
set to the current software priority level of the interrupt routine and recovered when the CC register is
popped.
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Power-saving modes
ST72344xx, ST2345xx
9.7
Register description
9.7.1
AWUFH control/status register (AWUCSR)
Reset value: 0000 0000 (00h)
7
0
AWU
F
0
0
0
0
0
AWUM
AWUEN
Read/Write (except bit 2 read only)
Bits 7:3 = Reserved.
Bit 2= AWUF Auto-wakeup flag
This bit is set by hardware when the AWU module generates an interrupt and cleared
by software on reading AWUCSR.
0: No AWU interrupt occurred
1: AWU interrupt occurred
Bit 1= AWUM Auto-wakeup measurement
This bit enables the AWU RC oscillator and connects internally its output to the ICAP2
input of 16-bit timer A. This allows the timer to be used to measure the AWU RC
oscillator dispersion and then compensate this dispersion by providing the right value in
the AWUPR register.
0: Measurement disabled
1: Measurement enabled
Bit 0 = AWUEN Auto-wakeup from Halt Enabled
This bit enables the Auto-wakeup from Halt feature: once Halt mode is entered, the
AWUFH wakes up the microcontroller after a time delay defined by the AWU prescaler
value. It is set and cleared by software.
0: AWUFH (Auto-wakeup from Halt) mode disabled
1: AWUFH (Auto-wakeup from Halt) mode enabled
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Power-saving modes
9.7.2
AWUFH prescaler register (AWUPR)
Reset value: 1111 1111 (FFh)
7
0
AWUPR7 AWUPR6 AWUPR5 AWUPR4 AWUPR3 AWUPR2 AWUPR1 AWUPR0
Read/Write
Bits 7:0= AWUPR[7:0] Auto-wakeup Prescaler
These 8 bits define the AWUPR Dividing factor, as explained below:
Table 24. AWUPR dividing factor
AWUPR[7:0]
Dividing factor
00h
01h
...
Forbidden (1)
1
...
FEh
FFh
254
255
1. If 00h is written to AWUPR, depending on the product, an interrupt is generated immediately after a HALT
instruction, or the AWUPR remains unchanged.
In AWU mode, the period that the MCU stays in Halt mode (t
in Figure 33) is defined by
AWU
1
t
= 64 × AWUPR × ------------------------- + t
RCSTRT
AWU
f
AWURC
This prescaler register can be programmed to modify the time that the MCU stays in Halt
mode before waking up automatically.
Table 25. AWU register map and reset values
Address Register
7
6
5
4
3
2
1
0
(Hex.)
label
AWUCSR
Reset value
AWUF
0
AWUM
0
AWUEN
0
002Eh
0
0
0
0
0
AWUPR
Reset value
AWUPR7 AWUPR6 AWUPR5 AWUPR4 AWUPR3 AWUPR2 AWUPR1 AWUPR0
002Fh
1
1
1
1
1
1
1
1
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I/O ports
ST72344xx, ST2345xx
10
I/O ports
10.1
Introduction
The I/O ports offer different functional modes:
■
transfer of data through digital inputs and outputs
and for specific pins:
■
■
external interrupt generation
alternate signal input/output for the on-chip peripherals.
An I/O port contains up to 8 pins. Each pin can be programmed independently as digital
input (with or without interrupt generation) or digital output.
10.2
Functional description
Each port has two main registers:
■
■
Data Register (DR)
Data Direction Register (DDR)
and one optional register:
Option Register (OR)
■
Each I/O pin may be programmed using the corresponding register bits in the DDR and OR
registers: Bit X corresponding to pin X of the port. The same correspondence is used for the
DR register.
The following description takes into account the OR register. (For specific ports which do not
provide this register, refer to the I/O Port Implementation section). The generic I/O block
diagram is shown in Figure 35.
10.2.1
Input modes
The input configuration is selected by clearing the corresponding DDR register bit. In this
case, reading the DR register returns the digital value applied to the external I/O pin.
Different input modes can be selected by software through the OR register.
Note:
1
Writing the DR register modifies the latch value but does not affect the pin status.
2
When switching from input to output mode, the DR register has to be written first to drive the
correct level on the pin as soon as the port is configured as an output.
3
Do not use read/modify/write instructions (BSET or BRES) to modify the DR register as this
might corrupt the DR content for I/Os configured as input.
External interrupt function
When an I/O is configured as Input with Interrupt, an event on this I/O can generate an
external interrupt request to the CPU.
Each pin can independently generate an interrupt request. The interrupt sensitivity is
independently programmable using the sensitivity bits in the EICR register.
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I/O ports
Each external interrupt vector is linked to a dedicated group of I/O port pins (see Section 2:
Pin description and Section 8: Interrupts). If several input pins are selected simultaneously
as interrupt sources, these are first detected according to the sensitivity bits in the EICR
register and then logically ORed.
The external interrupts are hardware interrupts, which means that the request latch (not
accessible directly by the application) is automatically cleared when the corresponding
interrupt vector is fetched. To clear an unwanted pending interrupt by software, the
sensitivity bits in the EICR register must be modified.
10.2.2
Output modes
The output configuration is selected by setting the corresponding DDR register bit. In this
case, writing the DR register applies this digital value to the I/O pin through the latch. Then
reading the DR register returns the previously stored value.
Two different output modes can be selected by software through the OR register: Output
push-pull and open-drain. DR register value and output pin status are described below:
Table 26. Output modes
DR
Push-pull
Open-drain
0
1
VSS
VDD
VSS
Floating
10.2.3
Alternate functions
When an on-chip peripheral is configured to use a pin, the alternate function is automatically
selected. This alternate function takes priority over the standard I/O programming.
When the signal is coming from an on-chip peripheral, the I/O pin is automatically
configured in output mode (push-pull or open drain according to the peripheral).
When the signal is going to an on-chip peripheral, the I/O pin must be configured in input
mode. In this case, the pin state is also digitally readable by addressing the DR register.
Note:
Input pull-up configuration can cause unexpected value at the input of the alternate
peripheral input. When an on-chip peripheral uses a pin as input and output, this pin has to
be configured in input floating mode.
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I/O ports
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Figure 35. I/O port general block diagram
ALTERNATE
OUTPUT
1
0
REGISTER
ACCESS
P-BUFFER
(see table below)
VDD
ALTERNATE
ENABLE
PULL-UP
(see table below)
DR
DDR
OR
VDD
PULL-UP
CONDITION
PAD
If implemented
OR SEL
DDR SEL
DR SEL
N-BUFFER
DIODES
(see table below)
ANALOG
INPUT
CMOS
SCHMITT
TRIGGER
1
0
ALTERNATE
INPUT
EXTERNAL
INTERRUPT
SOURCE (eix)
(1)
Table 27. I/O Port mode options
Configuration mode
Diodes
Pull-up
P-Buffer
to VDD
to VSS
Floating with/without Interrupt
Pull-up with/without Interrupt
Push-pull
Off
On
Input
Off
On
On
Off
NI
On
Off
NI
Output
Open drain (logic level)
True open drain
NI(2)
1. NI = not implemented, Off = implemented not activated, On = implemented and activated.
2. The diode to VDD is not implemented in the true open drain pads. A local protection between the pad and
VSS is implemented to protect the device against positive stress.
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I/O ports
Table 28. I/O port configurations
Hardware configuration
DR REGISTER ACCESS
NOT IMPLEMENTED IN
TRUE OPEN DRAIN
I/O PORTS
VDD
PULL-UP
CONDITION
RPU
W
R
DR
REGISTER
DATA BUS
PAD
ALTERNATE INPUT
EXTERNAL INTERRUPT
SOURCE (eix)
INTERRUPT
CONDITION
ANALOG INPUT
NOT IMPLEMENTED IN
TRUE OPEN DRAIN
I/O PORTS
DR REGISTER ACCESS
VDD
RPU
R/W
DR
REGISTER
DATA BUS
PAD
ALTERNATE
ENABLE
ALTERNATE
OUTPUT
NOT IMPLEMENTED IN
TRUE OPEN DRAIN
I/O PORTS
DR REGISTER ACCESS
VDD
RPU
R/W
DR
REGISTER
DATA BUS
PAD
ALTERNATE
ENABLE
ALTERNATE
OUTPUT
1. When the I/O port is in input configuration and the associated alternate function is enabled as an output,
reading the DR register will read the alternate function output status.
2. When the I/O port is in output configuration and the associated alternate function is enabled as an input,
the alternate function reads the pin status given by the DR register content.
Caution:
The alternate function must not be activated as long as the pin is configured as input with
interrupt, in order to avoid generating spurious interrupts.
Analog alternate function
When the pin is used as an ADC input, the I/O must be configured as floating input. The
analog multiplexer (controlled by the ADC registers) switches the analog voltage present on
the selected pin to the common analog rail which is connected to the ADC input.
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I/O ports
ST72344xx, ST2345xx
It is recommended not to change the voltage level or loading on any port pin while
conversion is in progress. Furthermore, it is recommended not to have clocking pins located
close to a selected analog pin.
Warning: The analog input voltage level must be within the limits
stated in the absolute maximum ratings.
10.3
I/O port implementation
The hardware implementation on each I/O port depends on the settings in the DDR and OR
registers and specific feature of the I/O port such as ADC Input or true open drain.
Switching these I/O ports from one state to another should be done in a sequence that
prevents unwanted side effects. Recommended safe transitions are illustrated in Figure 36.
Other transitions are potentially risky and should be avoided, since they are likely to present
unwanted side-effects such as spurious interrupt generation.
Figure 36. Interrupt I/O port state transitions
01
00
10
11
INPUT
floating/pull-up
interrupt
INPUT
floating
(reset state)
OUTPUT
open-drain
OUTPUT
push-pull
= DDR, OR
XX
10.4
10.5
Low-power modes
Table 29. Description
Mode
Description
Wait
Halt
No effect on I/O ports. External interrupts cause the device to exit from Wait mode.
No effect on I/O ports. External interrupts cause the device to exit from Halt mode.
Interrupts
The external interrupt event generates an interrupt if the corresponding configuration is
selected with DDR and OR registers and the interrupt mask in the CC register is not active
(RIM instruction).
Table 30. Description of interrupt events
Enable
Control bit
Exit from
Wait
Exit from
Halt
Interrupt event
Event flag
External interrupt on selected
external event
DDRx
ORx
-
Yes
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I/O ports
10.5.1
I/O port implementation
The I/O port register configurations are summarized as follows.
Standard ports: PA[5:4], PC[7:0], PD[5:0], PE0, PF[7:6], PF4
Table 31. I/O port register configurations (standard ports)
Mode
DDR
OR
floating input
0
0
1
1
0
1
0
1
pull-up input
open drain output
push-pull output
Interrupt ports: PB4, PB[2:0], PF[1:0] (with pull-up)
Table 32. I/O port register configurations (interrupt ports with pull-up)
Mode
DDR
OR
floating input
0
0
1
1
0
1
0
1
pull-up interrupt input
open drain output
push-pull output
PA3, PE1, PB3, PF2 (without pull-up)
Table 33. I/O port register configurations (interrupt ports without pull-up)
Mode
DDR
OR
floating input
0
0
1
1
0
1
0
1
floating interrupt input
open drain output
push-pull output
True open-drain ports: PA[7:6], PD[7:6]
Table 34. I/O port register configurations (true open drain ports)
Mode
DDR
floating input
0
1
open drain (high sink ports)
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I/O ports
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Output
Table 35. Port configuration
Input
Port
Pin name
OR = 0
OR = 1
OR = 0
OR = 1
PA7:6
PA5:4
PA3
floating
true open-drain
Port A
floating
floating
floating
pull-up
open drain
open drain
open drain
push-pull
push-pull
push-pull
floating interrupt
floating interrupt
PB3
Port B
PB4,
PB2:0
floating
floating
pull-up interrupt
pull-up
open drain
open drain
push-pull
push-pull
Port C
Port D
PC7:0
PD7:6
PD5:0
PE1
floating
true open-drain
floating
floating
floating
floating
floating
floating
pull-up
floating interrupt
pull-up
open drain
open drain
open drain
open drain
open drain
open drain
push-pull
push-pull
push-pull
push-pull
push-pull
push-pull
Port E
Port F
PE0
PF7:6, 4
PF2
pull-up
floating interrupt
pull-up interrupt
PF1:0
Caution:
In small packages, an internal pull-up is applied permanently to the non-bonded I/O pins. So
they have to be kept in input floating configuration to avoid unwanted consumption.
Table 36. I/O port register map and reset values
Address Register
7
6
5
4
3
2
1
0
(Hex.)
label
Reset value
of all I/O port registers
0
0
0
0
0
0
0
0
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
000Ah
000Bh
PADR
PADDR
PAOR
MSB
MSB
MSB
MSB
LSB
LSB
LSB
LSB
PBDR
PBDDR
PBOR
PCDR
PCDDR
PCOR
PDDR
PDDDR
PDOR
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I/O ports
Table 36. I/O port register map and reset values (continued)
Address Register
7
6
5
4
3
2
1
0
(Hex.)
label
000Ch
000Dh
000Eh
000Fh
0010h
0011h
PEDR
PEDDR
PEOR
PFDR
MSB
LSB
PFDDR
PFOR
MSB
LSB
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On-chip peripherals
ST72344xx, ST2345xx
11
On-chip peripherals
11.1
Window watchdog (WWDG)
11.1.1
Introduction
The window watchdog is used to detect the occurrence of a software fault, usually
generated by external interference or by unforeseen logical conditions, which causes the
application program to abandon its normal sequence. The Watchdog circuit generates an
MCU reset on expiry of a programmed time period, unless the program refreshes the
contents of the downcounter before the T6 bit becomes cleared. An MCU reset is also
generated if the 7-bit downcounter value (in the control register) is refreshed before the
downcounter has reached the window register value. This implies that the counter must be
refreshed in a limited window.
11.1.2
Main features
■
■
Programmable free-running downcounter
Conditional reset
–
–
Reset (if watchdog activated) when the downcounter value becomes less than 40h
Reset (if watchdog activated) if the downcounter is reloaded outside the window
(see Figure 40)
■
■
Hardware/Software Watchdog activation (selectable by option byte)
Optional reset on HALT instruction (configurable by option byte)
11.1.3
Functional description
The counter value stored in the WDGCR register (bits T[6:0]), is decremented every 16384
f
cycles (approx.), and the length of the timeout period can be programmed by the user
OSC2
in 64 increments.
If the watchdog is activated (the WDGA bit is set) and when the 7-bit downcounter (T[6:0]
bits) rolls over from 40h to 3Fh (T6 becomes cleared), it initiates a reset cycle pulling low the
reset pin for typically 30 μs. If the software reloads the counter while the counter is greater
than the value stored in the window register, then a reset is generated.
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On-chip peripherals
Figure 37. Watchdog block diagram
WATCHDOG WINDOW REGISTER (WDGWR)
W5
W0
W1
RESET
-
W6
W4
W2
W3
comparator
= 1 when
T6:0 > W6:0
CMP
Write WDGCR
WATCHDOG CONTROL REGISTER (WDGCR)
T5
T0
WDGA T6
T1
T4
T2
T3
6-BIT DOWNCOUNTER (CNT)
MCC/RTC
f
OSC2
DIV 64
WDG PRESCALER
DIV 4
12-BIT MCC
RTC COUNTER
TB[1:0] bits
(MCCSR
Register)
MSB
LSB
0
6 5
11
The application program must write in the WDGCR register at regular intervals during
normal operation to prevent an MCU reset. This operation must occur only when the counter
value is lower than the window register value. The value to be stored in the WDGCR register
must be between FFh and C0h (see Figure 38: Approximate timeout duration):
■
Enabling the watchdog:
When Software Watchdog is selected (by option byte), the watchdog is disabled after a
reset. It is enabled by setting the WDGA bit in the WDGCR register, then it cannot be
disabled again except by a reset.
When Hardware Watchdog is selected (by option byte), the watchdog is always active
and the WDGA bit is not used.
■
Controlling the downcounter:
This downcounter is free-running: It counts down even if the watchdog is disabled.
When the watchdog is enabled, the T6 bit must be set to prevent generating an
immediate reset.
The T[5:0] bits contain the number of increments which represents the time delay
before the watchdog produces a reset (see Figure 38). The timing varies between a
minimum and a maximum value due to the unknown status of the prescaler when
writing to the WDGCR register (see Figure 39: Exact timeout duration (tmin and tmax)).
The window register (WDGWR) contains the high limit of the window: To prevent a
reset, the downcounter must be reloaded when its value is lower than the window
register value and greater than 3Fh. Figure 40: Window watchdog timing diagram
describes the window watchdog process.
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On-chip peripherals
ST72344xx, ST2345xx
Note:
The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is
cleared).
■
Watchdog reset on Halt option
If the watchdog is activated and the watchdog reset on halt option is selected, then the
HALT instruction will generate a Reset.
11.1.4
11.1.5
Using Halt mode with the WDG
If Halt mode with Watchdog is enabled by option byte (no watchdog reset on HALT
instruction), it is recommended before executing the HALT instruction to refresh the WDG
counter, to avoid an unexpected WDG reset immediately after waking up the microcontroller.
How to program the watchdog timeout
Figure 38 shows the linear relationship between the 6-bit value to be loaded in the watchdog
counter (CNT) and the resulting timeout duration in milliseconds. This can be used for a
quick calculation without taking the timing variations into account. If more precision is
needed, use the formulae in Figure 39.
Caution:
When writing to the WDGCR register, always write 1 in the T6 bit to avoid generating an
immediate reset.
Figure 38. Approximate timeout duration
3F
38
30
28
20
18
10
08
00
1.5
18
34
50
65
82
98
114
128
Watchdog timeout (ms) @ 8 MHz fOSC2
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On-chip peripherals
Figure 39. Exact timeout duration (t
and t
)
min
max
Where:
t
t
t
= (LSB + 128) x 64 x t
OSC2
min0
= 16384 x t
max0
OSC2
OSC2
= 125 ns if f
= 8 MHz
OSC2
CNT = Value of T[5:0] bits in the WDGCR register (6 bits)
MSB and LSB are values from the table below depending on the timebase selected by the TB[1:0]
bits in the MCCSR register
TB1 bit
(MCCSR Reg.)
TB0 bit
(MCCSR Reg.)
Selected MCCSR
time base
MSB
LSB
0
0
1
1
0
1
0
1
2 ms
4 ms
4
59
53
35
54
8
10 ms
25 ms
20
49
To calculate the minimum watchdog timeout (t ):
min
MSB
4
If CNT < -------------
then
else
t
= tmin0 + 16384 × CNT × t
min
= t
osc2
4CNT
4CNT
t
+ 16384 × CNT – ---------------- + (192 + LSB) × 64 × ---------------- × t
osc2
MSB MSB
min
min0
To calculate the maximum Watchdog Timeout (tmax):
If CNT ≤ M------S----B---
then
t
= tmax0 + 16384 × CNT × t
max
= t
osc2
4CNT
4
4CNT
elset
+ 16384 × CNT – ---------------- + (192 + LSB) × 64 × ---------------- × t
osc2
MSB MSB
max
max0
Note:
In the above formulae, division results must be rounded down to the next integer
value.
Example:
With 2 ms timeout selected in MCCSR register
Value of T[5:0] Bits in
WDGCR Register (Hex.)
Min. watchdog timeout (ms)
Max. watchdog timeout (ms)
tmax
tmin
00
3F
1.496
128
2.048
128.552
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On-chip peripherals
ST72344xx, ST2345xx
Figure 40. Window watchdog timing diagram
T[5:0] CNT downcounter
WDGWR
3Fh
time
(step = 16384/f
)
Refresh not allowed Refresh Window
OSC2
T6 bit
Reset
11.1.6
Low-power modes
Table 37. Descriptions
Mode
Description
Slow
Wait
No effect on Watchdog: the downcounter continues to decrement at normal speed.
No effect on Watchdog: the downcounter continues to decrement.
OIE bit in
MCCSR
register
WDGHALT
bit in
Option Byte
No Watchdog reset is generated. The MCU enters Halt
mode. The Watchdog counter is decremented once and
then stops counting and is no longer able to generate a
watchdog reset until the MCU receives an external
interrupt or a reset.
Halt
If an interrupt is received (refer to interrupt table mapping
to see interrupts which can occur in halt mode), the
Watchdog restarts counting after 256 or 4096 CPU clocks.
If a reset is generated, the Watchdog is disabled (reset
state) unless Hardware Watchdog is selected by option
byte. For application recommendations see Section 11.1.8
below.
0
0
0
1
1
x
A reset is generated instead of entering halt mode.
No reset is generated. The MCU enters Active Halt mode.
The Watchdog counter is not decremented. It stop
counting. When the MCU receives an oscillator interrupt or
external interrupt, the Watchdog restarts counting
immediately. When the MCU receives a reset, the
Watchdog restarts counting after 256 or 4096 CPU clocks.
Active-halt
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On-chip peripherals
11.1.7
11.1.8
Hardware watchdog option
If hardware watchdog is selected by option byte, the watchdog is always active and the
WDGA bit in the WDGCR is not used. Refer to the Option Byte description.
Using Halt mode with the WDG (WDGHALT option)
The following recommendation applies if Halt mode is used when the watchdog is enabled.
■
Before executing the HALT instruction, refresh the WDG counter, to avoid an
unexpected WDG reset immediately after waking up the microcontroller.
11.1.9
Interrupts
None.
11.1.10 Register description
Control register (WDGCR)
Reset value: 0111 1111 (7Fh)
7
0
WDGA
T6
T5
T4
T3
T2
T1
T0
Read/Write
Bit 7 = WDGA Activation bit.
This bit is set by software and only cleared by hardware after a reset. When WDGA = 1,
the watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled
Note:
This bit is not used if the hardware watchdog option is enabled by option byte.
Bits 6:0 = T[6:0] 7-bit counter (MSB to LSB).
These bits contain the value of the watchdog counter. It is decremented every
16384 f
cycles (approx.). A reset is produced when it rolls over from 40h to 3Fh
OSC2
(T6 becomes cleared).
Window register (WDGWR)
Reset value: 0111 1111 (7Fh)
7
0
-
W6
W5
W4
W3
W2
W1
W0
Read/Write
Bit 7 = Reserved
Bits 6:0 = W[6:0] 7-bit window value
These bits contain the window value to be compared to the downcounter.
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Table 38. Watchdog timer register map and reset values
Address
(Hex.)
Register
label
7
6
5
4
3
2
1
0
WDGCR
WDGA
0
T6
1
T5
1
T4
1
T3
1
T2
1
T1
1
T0
1
2A
30
Reset value
WDGWR
-
W6
1
W5
1
W4
1
W3
1
W2
1
W1
1
W0
1
Reset value
0
11.2
Main clock controller with real-time clock and beeper
(MCC/RTC)
The main clock controller consists of three different functions:
■
■
■
a programmable CPU clock prescaler
a clock-out signal to supply external devices
a real-time clock timer with interrupt capability
Each function can be used independently and simultaneously.
11.2.1
11.2.2
Programmable CPU clock prescaler
The programmable CPU clock prescaler supplies the clock for the ST7 CPU and its internal
peripherals. It manages Slow power-saving mode (See Section 9.2: Slow mode for more
details).
The prescaler selects the f
main clock frequency and is controlled by three bits in the
CPU
MCCSR register: CP[1:0] and SMS.
Clock-out capability
The clock-out capability is an alternate function of an I/O port pin that outputs a f
to drive external devices. It is controlled by the MCO bit in the MCCSR register.
clock
OSC2
Caution:
When selected, the clock out pin suspends the clock during Active-halt mode.
11.2.3
Real-time clock timer (RTC)
The counter of the real-time clock timer allows an interrupt to be generated based on an
accurate real-time clock. Four different time bases depending directly on f are available.
OSC2
The whole functionality is controlled by four bits of the MCCSR register: TB[1:0], OIE and
OIF.
When the RTC interrupt is enabled (OIE bit set), the ST7 enters Active-halt mode when the
HALT instruction is executed. See Section 9.5: Active-halt mode for more details.
11.2.4
Beeper
The beep function is controlled by the MCCBCR register. It can output three selectable
frequencies on the BEEP pin (I/O port alternate function).
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Figure 41.
On-chip peripherals
Main clock controller (MCC/RTC) block diagram
BC1 BC0
MCCBCR
BEEP
MCO
BEEP SIGNAL
SELECTION
12-BIT MCC RTC
COUNTER
TO
DIV 64
WATCHDOG
TIMER
MCO CP1 CP0 SMS TB1 TB0 OIE OIF
MCCSR
MCC/RTC INTERRUPT
fCPU
fOSC2
DIV 2, 4, 8, 16
1
0
CPU CLOCK
TO CPU AND
PERIPHERALS
11.2.5
Low-power modes
Table 39. Mode description
Mode
Description
No effect on MCC/RTC peripheral.
MCC/RTC interrupt cause the device to exit from Wait mode.
Wait
No effect on MCC/RTC counter (OIE bit is set), the registers are frozen.
MCC/RTC interrupt cause the device to exit from Active-halt mode.
Active-halt
MCC/RTC counter and registers are frozen.
Halt
MCC/RTC operation resumes when the MCU is woken up by an interrupt with “exit
from Halt” capability.
11.2.6
Interrupts
The MCC/RTC interrupt event generates an interrupt if the OIE bit of the MCCSR register is
set and the interrupt mask in the CC register is not active (RIM instruction).
Table 40. Interrupt event
Enable
Control bit
Exit from
Wait
Exit from
Halt
Interrupt event
Event flag
Time base overflow event
OIF
OIE
Yes
No (1)
1. The MCC/RTC interrupt wakes up the MCU from Active-halt mode, not from Halt mode.
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11.2.7
Register description
MCC control/status register (MCCSR)
Reset value: 0000 0000 (00h)
7
0
MCO
CP1
CP0
SMS
TB1
TB0
OIE
OIF
Read/Write
Bit 7 = MCO Main clock out selection
This bit enables the MCO alternate function on the PF0 I/O port. It is set and cleared by
software.
0: MCO alternate function disabled (I/O pin free for general-purpose I/O)
1: MCO alternate function enabled (f
on I/O port)
CPU
Note:
To reduce power consumption, the MCO function is not active in Active-halt mode.
Bits 6:5 = CP[1:0] CPU clock prescaler
These bits select the CPU clock prescaler which is applied in the different slow modes.
Their action is conditioned by the setting of the SMS bit. These two bits are set and
cleared by software.
Table 41. CPU clock prescaler selection
fCPU in Slow mode
OSC2 / 2
CP1
CP0
f
0
0
1
1
0
1
0
1
fOSC2 / 4
fOSC2 / 8
OSC2 / 16
f
Bit 4 = SMS Slow mode select
This bit is set and cleared by software.
0: Normal mode. f
= f
OSC2
CPU
1: Slow mode. f
is given by CP1, CP0
CPU
See Section 9.2: Slow mode and Section 11.1: Window watchdog (WWDG) for more
details.
Bits 3:2 = TB[1:0] Time base control
These bits select the programmable divider time base. They are set and cleared by
software.
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Table 42. Time base control
Time base
Counter
TB1
TB0
prescaler
fOSC2 = 4 MHz
fOSC2 = 8 MHz
16000
32000
80000
200000
4 ms
8 ms
2 ms
4 ms
0
0
1
1
0
1
0
1
20 ms
50 ms
10 ms
25 ms
A modification of the time base is taken into account at the end of the current period
(previously set) to avoid an unwanted time shift. This allows to use this time base as a real-
time clock.
Bit 1 = OIE Oscillator interrupt enable
This bit set and cleared by software.
0: Oscillator interrupt disabled
1: Oscillator interrupt enabled
This interrupt can be used to exit from Active-halt mode.
When this bit is set, calling the ST7 software HALT instruction enters the Active-halt
.
power-saving mode
Bit 0 = OIF Oscillator interrupt flag
This bit is set by hardware and cleared by software reading the MCCSR register. It
indicates when set that the main oscillator has reached the selected elapsed time
(TB1:0).
0: Timeout not reached
1: Timeout reached
Caution:
The BRES and BSET instructions must not be used on the MCCSR register to avoid
unintentionally clearing the OIF bit.
MCC beep control register (MCCBCR)
Reset value: 0000 0000 (00h)
7
0
0
0
0
0
0
0
BC1
BC0
Read/Write
Bits 7:2 = Reserved, must be kept cleared.
Bits 1:0 = BC[1:0] Beep control
These 2 bits select the PF1 pin beep capability.
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Table 43. Beep control
BC1
BC0
Beep mode with fOSC2 = 8 MHz
Off
0
0
1
1
0
1
0
1
~2-kHz
~1-kHz
Output
beep signal
~50% duty cycle
~500-Hz
The beep output signal is available in Active-halt mode but has to be disabled to reduce the
consumption.
Table 44. Main clock controller register map and reset values
Address Register
7
6
5
4
3
2
1
0
(Hex.)
label
SICSR
Reset value
AVDIE AVDF LVDRF LOCKED
WDGRF
x
002Bh
0
0
0
x
0
0
0
MCCSR
Reset value
MCO
0
CP1
0
CP0
0
SMS
0
TB1
0
TB0
0
OIE
0
OIF
0
002Ch
002Dh
MCCBCR
Reset value
BC1
0
BC0
0
0
0
0
0
0
0
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On-chip peripherals
11.3
16-bit timer
11.3.1
Introduction
The timer consists of a 16-bit free-running counter driven by a programmable prescaler.
It may be used for a variety of purposes, including pulse length measurement of up to two
input signals (input capture) or generation of up to two output waveforms (output compare
and PWM).
Pulse lengths and waveform periods can be modulated from a few microseconds to several
milliseconds using the timer prescaler and the CPU clock prescaler.
Some devices of the ST7 family have two on-chip 16-bit timers. They are completely
independent, and do not share any resources. They are synchronized after a Device reset
as long as the timer clock frequencies are not modified.
This description covers one or two 16-bit timers. In the devices with two timers, register
names are prefixed with TA (Timer A) or TB (Timer B).
11.3.2
Main features
■
■
■
Programmable prescaler: f
divided by 2, 4 or 8.
CPU
Overflow status flag and maskable interrupt
External clock input (must be at least 4 times slower than the CPU clock speed) with
the choice of active edge
■
■
Output compare functions with
–
–
–
–
2 dedicated 16-bit registers
2 dedicated programmable signals
2 dedicated status flags
1 dedicated maskable interrupt
Input capture functions with
–
–
–
–
2 dedicated 16-bit registers
2 dedicated active edge selection signals
2 dedicated status flags
1 dedicated maskable interrupt
■
■
■
■
Pulse width modulation mode (PWM)
One-pulse mode
Reduced-power mode
5 alternate functions on I/O ports (ICAP1, ICAP2, OCMP1, OCMP2, EXTCLK). See the
note below.
The block diagram is shown in Figure 42.
Note:
Some timer pins may not be available (not bonded) in some devices. Refer to the device pin
out description. When reading an input signal on a non-bonded pin, the value will always
be ‘1’.
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11.3.3
Functional description
Counter
The main block of the programmable timer is a 16-bit free running upcounter and its
associated 16-bit registers. The 16-bit registers are made up of two 8-bit registers called
high & low.
Counter Register (CR):
■
■
Counter High Register (CHR) is the most significant byte (MS Byte).
Counter Low Register (CLR) is the least significant byte (LS Byte).
Alternate Counter Register (ACR)
■
■
Alternate Counter High Register (ACHR) is the most significant byte (MS Byte).
Alternate Counter Low Register (ACLR) is the least significant byte (LS Byte).
These two read-only 16-bit registers contain the same value but with the difference that
reading the ACLR register does not clear the TOF bit (Timer overflow flag) located in the
Status register (SR). (See the following Note:).
Writing in the CLR register or ACLR register resets the free running counter to the FFFCh
value.
Both counters have a reset value of FFFCh (this is the only value which is reloaded in the
16-bit timer). The reset value of both counters is also FFFCh in One-pulse mode and PWM
mode.
The timer clock depends on the clock control bits of the CR2 register, as illustrated in
Table 50: Clock control bits. The value in the counter register repeats every 131 072, 262
144 or 524 288 CPU clock cycles, depending on the CC[1:0] bits.
The timer frequency can be f
/2, f
/4, f
/8 or an external frequency.
CPU
CPU
CPU
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On-chip peripherals
Figure 42. Timer block diagram
INTERNAL BUS
fCPU
16-BIT TIMER PERIPHERAL INTERFACE
8 low
8-bit
8 high
8
8
8
8
8
8
8
8
buffer
EXEDG
16
INPUT
CAPTURE
REGISTER
INPUT
CAPTURE
REGISTER
OUTPUT
COMPARE
REGISTER
OUTPUT
COMPARE
REGISTER
1/2
1/4
1/8
COUNTER
REGISTER
1
1
2
2
ALTERNATE
COUNTER
REGISTER
EXTCLK
pin
16
16
16
CC[1:0]
TIMER INTERNAL BUS
16 16
OVERFLOW
DETECT
EDGE DETECT
CIRCUIT1
OUTPUT COMPARE
CIRCUIT
ICAP1
pin
CIRCUIT
6
EDGE DETECT
CIRCUIT2
ICAP2
pin
OCMP1
pin
LATCH1
LATCH2
0
ICF1 OCF1 TOF ICF2 OCF2
0
TIMD
(Control/Status Register)
OCMP2
pin
CSR
EXEDG
ICIE OCIE TOIE FOLV2 FOLV1OLVL2 IEDG1 OLVL1
OC1E
OPM PWM CC1 CC0 IEDG2
OC2E
(Control Register 1) CR1
(Control Register 2) CR2
(See note 1)
TIMER INTERRUPT
1. If IC, OC and TO interrupt requests have separate vectors, then the last OR is not present (See Device
Interrupt Vector Table).
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Figure 43. 16-bit read sequence (from either the counter register or the alternate
counter register)
Beginning of the sequence
Read
MS Byte
LS Byte
is buffered
At t0
Other
instructions
Returns the buffered
LS Byte value at t0
Read
LS Byte
At t0 +Δt
Sequence completed
The user must read the MS Byte first, then the LS Byte value is buffered automatically.
This buffered value remains unchanged until the 16-bit read sequence is completed, even if
the user reads the MS Byte several times.
After a complete reading sequence, if only the CLR register or ACLR register are read, they
return the LS Byte of the count value at the time of the read.
Whatever the timer mode used (input capture, output compare, one-pulse mode or PWM
mode) an overflow occurs when the counter rolls over from FFFFh to 0000h then:
■
■
The TOF bit of the SR register is set.
A timer interrupt is generated if:
–
–
TOIE bit of the CR1 register is set and
I bit of the CC register is cleared.
If one of these conditions is false, the interrupt remains pending to be issued as soon as
they are both true.
Clearing the overflow interrupt request is done in two steps:
1. Reading the SR register while the TOF bit is set.
2. An access (read or write) to the CLR register.
Note:
The TOF bit is not cleared by accesses to ACLR register. The advantage of accessing the
ACLR register rather than the CLR register is that it allows simultaneous use of the overflow
function and reading the free running counter at random times (for example, to measure
elapsed time) without the risk of clearing the TOF bit erroneously.
The timer is not affected by Wait mode.
In Halt mode, the counter stops counting until the mode is exited. Counting then resumes
from the previous count (Device awakened by an interrupt) or from the reset count (Device
awakened by a Reset).
External clock
The external clock (where available) is selected if CC0=1 and CC1=1 in CR2 register.
The status of the EXEDG bit in the CR2 register determines the type of level transition on
the external clock pin EXTCLK that will trigger the free running counter.
The counter is synchronized with the falling edge of the internal CPU clock.
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A minimum of four falling edges of the CPU clock must occur between two consecutive
active edges of the external clock; thus, the external clock frequency must be less than a
quarter of the CPU clock frequency.
Figure 44. Counter timing diagram, internal clock divided by 2
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
FFFD FFFE FFFF 0000 0001 0002 0003
COUNTER REGISTER
TIMER OVERFLOW FLAG (TOF)
Figure 45. Counter timing diagram, internal clock divided by 4
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
FFFC
FFFD
0000
0001
COUNTER REGISTER
TIMER OVERFLOW FLAG (TOF)
Figure 46. Counter timing diagram, internal clock divided by 8
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
0000
FFFC
FFFD
COUNTER REGISTER
TIMER OVERFLOW FLAG (TOF)
Note:
The device is in reset state when the internal reset signal is high. When it is low, the Device
is running.
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Input capture
In this section, the index, i, may be 1 or 2 because there are 2 input capture functions in the
16-bit timer.
The two input-capture 16-bit registers (IC1R and IC2R) are used to latch the value of the
free-running counter after a transition detected by the ICAPi pin.
Table 45. ICiR register
MS Byte
LS Byte
ICiR
ICiHR
ICiLR
ICiR register is a read-only register. The active transition is software-programmable through
the IEDGi bit of Control Registers (CRi). The timing resolution is one count of the free-
running counter: (fCPU/CC[1:0]).
Procedure:
To use the input capture function, select the following in the CR2 register:
■
■
Select the timer clock (CC[1:0]) (see Table 50: Clock control bits).
Select the edge of the active transition on the ICAP2 pin with the IEDG2 bit (the ICAP2
pin must be configured as floating input).
And select the following in the CR1 register:
■
Set the ICIE bit to generate an interrupt after an input capture coming from either the
ICAP1 pin or the ICAP2 pin
■
Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the
ICAP1pin must be configured as floating input).
When an input capture occurs:
■
■
ICFi bit is set.
The ICiR register contains the value of the free running counter on the active transition
on the ICAPi pin (see Figure 48).
■
A timer interrupt is generated if the ICIE bit is set and the I bit is cleared in the CC
register. Otherwise, the interrupt remains pending until both conditions become true.
Clearing the Input Capture interrupt request (i.e. clearing the ICFi bit) is done in two steps:
1. Reading the SR register while the ICFi bit is set.
2. An access (read or write) to the ICiLR register.
Note:
1
2
3
After reading the ICiHR register, transfer of input capture data is inhibited and ICFi will never
be set until the ICiLR register is also read.
The ICiR register contains the free running counter value which corresponds to the most
recent input capture.
The 2 input capture functions can be used together even if the timer also uses the 2 output
compare functions.
4
5
In One-pulse Mode and PWM mode only the input capture 2 can be used.
The alternate inputs (ICAP1 & ICAP2) are always directly connected to the timer. So any
transitions on these pins activate the input capture function.
Moreover, if one of the ICAPi pins is configured as an input and the second one as an
output, an interrupt can be generated provided that the user toggles the output pin and that
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the ICIE bit is set. This can be avoided if the input capture function i is disabled by reading
the ICiHR (see note 1).
6
The TOF bit can be used with interrupt in order to measure events that go beyond the timer
range (FFFFh).
Figure 47. Input capture block diagram
ICAP1
pin
(Control Register 1) CR1
EDGE DETECT
CIRCUIT2
EDGE DETECT
CIRCUIT1
ICIE
IEDG1
ICAP2
pin
(Status Register) SR
ICF1
ICF2
0
0
0
IC2R Register
IC1R Register
(Control Register 2) CR2
16-BIT
16-BIT FREE RUNNING
COUNTER
IEDG2
CC0
CC1
Figure 48. Input capture timing diagram
TIMER CLOCK
FF01
FF02
FF03
COUNTER REGISTER
ICAPi PIN
ICAPi FLAG
FF03
ICAPi REGISTER
1. The active edge is the rising edge.
2. The time between an event on the ICAPi pin and the appearance of the corresponding flag is from 2 to 3
CPU clock cycles. This depends on the moment when the ICAP event happens relative to the timer clock.
Output compare
In this section, the index, i, may be 1 or 2 because there are 2 output compare functions in
the 16-bit timer.
This function can be used to control an output waveform or indicate when a period of time
has elapsed.
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When a match is found between the Output Compare register and the free running counter,
the output compare function:
■
■
■
Assigns pins with a programmable value if the OCIE bit is set
Sets a flag in the status register
Generates an interrupt if enabled
Two 16-bit registers, Output Compare Register 1 (OC1R) and Output Compare Register 2
(OC2R), contain the value to be compared to the counter register each timer clock cycle.
Table 46. OCiR register
MS Byte
LS Byte
OCiR
OCiHR
OCiLR
These registers are readable and writable and are not affected by the timer hardware. A
reset event changes the OCiR value to 8000h.
The timing resolution is one count of the free running counter: (fCPU/
).
CC[1:0]
Procedure:
To use the output compare function, select the following in the CR2 register:
■
Set the OCiE bit if an output is needed then the OCMPi pin is dedicated to the output
compare i signal.
■
Select the timer clock (CC[1:0]) (see Table 50: Clock control bits).
And select the following in the CR1 register:
■
■
Select the OLVLi bit to applied to the OCMPi pins after the match occurs.
Set the OCIE bit to generate an interrupt if it is needed.
When a match is found between OCRi register and CR register:
■
■
■
OCFi bit is set.
The OCMPi pin takes OLVLi bit value (OCMPi pin latch is forced low during reset).
A timer interrupt is generated if the OCIE bit is set in the CR2 register and the I bit is
cleared in the CC register (CC).
The OCiR register value required for a specific timing application can be calculated using
the following formula:
Δt * fCPU
Δ OCiR =
PRESC
Where:
■
■
■
Δt = Output compare period (in seconds)
= CPU clock frequency (in Hertz)
f
CPU
PRESC = Timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits, see Table 50)
If the timer clock is an external clock, the formula is:
Δ OCiR = Δt * fEXT
Where:
■
■
Δt = Output compare period (in seconds)
f
= External timer clock frequency (in Hertz)
EXT
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Clearing the output compare interrupt request (i.e. clearing the OCFi bit) is done by:
1. Reading the SR register while the OCFi bit is set.
2. An access (read or write) to the OCiLR register.
The following procedure is recommended to prevent the OCFi bit from being set between
the time it is read and the write to the OCiR register:
■
■
Write to the OCiHR register (further compares are inhibited).
Read the SR register (first step of the clearance of the OCFi bit, which may be already
set).
■
Write to the OCiLR register (enables the output compare function and clears the OCFi
bit).
Note:
1
2
3
After a processor write cycle to the OCiHR register, the output compare function is inhibited
until the OCiLR register is also written.
If the OCiE bit is not set, the OCMPi pin is a general I/O port and the OLVLi bit will not
appear when a match is found but an interrupt could be generated if the OCIE bit is set.
In both internal and external clock modes, OCFi and OCMPi are set while the counter value
equals the OCiR register value (see Figure 50 and Figure 51). This behavior is the same in
OPM or PWM mode.
4
5
The output compare functions can be used both for generating external events on the
OCMPi pins even if the input capture mode is also used.
The value in the 16-bit OCiR register and the OLVi bit should be changed after each
successful comparison in order to control an output waveform or establish a new elapsed
timeout.
Forced compare output capability
When the FOLVi bit is set by software, the OLVLi bit is copied to the OCMPi pin. The OLVi bit
has to be toggled in order to toggle the OCMPi pin when it is enabled (OCiE bit=1). The
OCFi bit is then not set by hardware, and thus no interrupt request is generated.
FOLVLi bits have no effect in both one-pulse mode and PWM mode.
Figure 49. Output compare block diagram
16 BIT FREE RUNNING
OC1E
CC1 CC0
OC2E
COUNTER
(Control Register 2) CR2
16-bit
(Control Register 1) CR1
OUTPUT COMPARE
CIRCUIT
Latch
1
OCIE
FOLV2 FOLV1 OLVL2
OLVL1
OCMP1
Pin
16-bit
16-bit
Latch
2
OCMP2
Pin
OC1R Register
OCF1
OCF2
0
0
0
OC2R Register
(Status Register) SR
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Figure 50. Output compare timing diagram, f
= f
/2
CPU
TIMER
INTERNAL CPU CLOCK
TIMER CLOCK
COUNTER REGISTER
2ECF 2ED0 2ED1 2ED2
2ED3
2ED4
2ED3
OUTPUT COMPARE REGISTER i (OCRi)
OUTPUT COMPARE FLAG i (OCFi)
OCMPi PIN (OLVLi=1)
Figure 51. Output compare timing diagram, f
= f
/4
CPU
TIMER
INTERNAL CPU CLOCK
TIMER CLOCK
2ECF 2ED0 2ED1 2ED2
2ED3
2ED4
2ED3
COUNTER REGISTER
OUTPUT COMPARE REGISTER i (OCRi)
COMPARE REGISTER i LATCH
OUTPUT COMPARE FLAG i (OCFi)
OCMPi PIN (OLVLi=1)
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On-chip peripherals
One-pulse mode
One-pulse mode enables the generation of a pulse when an external event occurs. This
mode is selected via the OPM bit in the CR2 register.
The one-pulse mode uses the Input Capture1 function and the Output Compare1 function.
Procedure:
To use one-pulse mode:
1. Load the OC1R register with the value corresponding to the length of the pulse (see the
formula in the opposite column).
2. Select the following in the CR1 register:
–
–
–
Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after the
pulse.
Using the OLVL2 bit, select the level to be applied to the OCMP1 pin during the
pulse.
Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the
ICAP1 pin must be configured as floating input).
3. Select the following in the CR2 register:
–
Set the OC1E bit, the OCMP1 pin is then dedicated to the Output Compare 1
function.
–
–
Set the OPM bit.
Select the timer clock CC[1:0] (see Table 50: Clock control bits).
Figure 52. One-pulse mode cycle
One-pulse mode cycle
ICR1 = Counter
OCMP1 = OLVL2
When
event occurs
on ICAP1
Counter is reset
to FFFCh
ICF1 bit is set
When
Counter
= OC1R
OCMP1 = OLVL1
When a valid event occurs on the ICAP1 pin, the counter value is loaded in the ICR1
register. The counter is then initialized to FFFCh, the OLVL2 bit is output on the OCMP1 pin
and the ICF1 bit is set.
Because the ICF1 bit is set when an active edge occurs, an interrupt can be generated if the
ICIE bit is set.
Clearing the Input Capture interrupt request (i.e. clearing the ICFi bit) is done in two steps:
1. Reading the SR register while the ICFi bit is set.
2. An access (read or write) to the ICiLR register.
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The OC1R register value required for a specific timing application can be calculated using
the following formula:
t * fCPU
- 5
OCiR Value =
PRESC
Where:
■
■
■
t = Pulse period (in seconds)
f
= CPU clock frequency (in Hertz)
CPU
PRESC = Timer prescaler factor (2, 4 or 8 depending on the CC[1:0] bits, see Table 50:
Clock control bits)
If the timer clock is an external clock the formula is:
OCiR = t * fEXT -5
Where:
■
■
t = Pulse period (in seconds)
= External timer clock frequency (in Hertz)
f
EXT
When the value of the counter is equal to the value of the contents of the OC1R register, the
OLVL1 bit is output on the OCMP1 pin (See Figure 53).
Note:
1
2
The OCF1 bit cannot be set by hardware in One-pulse mode but the OCF2 bit can generate
an Output Compare interrupt.
When the Pulse Width Modulation (PWM) and One-pulse mode (OPM) bits are both set, the
PWM mode is the only active one.
3
4
If OLVL1=OLVL2 a continuous signal will be seen on the OCMP1 pin.
The ICAP1 pin can not be used to perform input capture. The ICAP2 pin can be used to
perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take
care that the counter is reset each time a valid edge occurs on the ICAP1 pin and ICF1 can
also generates interrupt if ICIE is set.
5
When One-pulse mode is used, OC1R is dedicated to this mode. Nevertheless, OC2R and
OCF2 can be used to indicate that a period of time has been elapsed but cannot generate
an output waveform, because the OLVL2 level is dedicated to the One-pulse mode.
Figure 53. One-pulse mode timing example
2ED3
01F8
IC1R
FFFC FFFD FFFE
2ED0 2ED1 2ED2
2ED3
FFFC FFFD
01F8
COUNTER
ICAP1
OLVL2
OLVL1
OLVL2
OCMP1
compare1
1. IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1.
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On-chip peripherals
Figure 54. Pulse width modulation mode timing example
2ED0 2ED1 2ED2
34E2 FFFC
FFFC FFFD FFFE
34E2
COUNTER
OCMP1
OLVL2
OLVL1
OLVL2
compare2
compare1
compare2
1. OC1R = 2ED0h, OC2R = 34E2, OLVL1 = 0, OLVL2 = 1
Pulse-width modulation mode
Pulse-width modulation (PWM) mode enables the generation of a signal with a frequency
and pulse length determined by the value of the OC1R and OC2R registers.
Pulse-width modulation mode uses the complete Output Compare 1 function plus the OC2R
register, and so this functionality can not be used when PWM mode is activated.
In PWM mode, double buffering is implemented on the output compare registers. Any new
values written in the OC1R and OC2R registers are loaded in their respective shadow
registers (double buffer) only at the end of the PWM period (OC2) to avoid spikes on the
PWM output pin (OCMP1). The shadow registers contain the reference values for
comparison in PWM “double buffering” mode.
Note:
There is a locking mechanism for transferring the OCiR value to the buffer. After a write to
the OCiHR register, the transfer of the new compare value to the buffer is inhibited until
OCiLR is also written.
Unlike in Output Compare mode, the compare function is always enabled in PWM mode.
Procedure:
To use pulse-width modulation mode:
1. Load the OC2R register with the value corresponding to the period of the signal using
the formula in the opposite column.
2. Load the OC1R register with the value corresponding to the period of the pulse if
(OLVL1=0 and OLVL2=1) using the formula in the opposite column.
3. Select the following in the CR1 register:
–
Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after a
successful comparison with OC1R register.
–
Using the OLVL2 bit, select the level to be applied to the OCMP1 pin after a
successful comparison with OC2R register.
4. Select the following in the CR2 register:
–
–
–
Set OC1E bit: the OCMP1 pin is then dedicated to the output compare 1 function.
Set the PWM bit.
Select the timer clock (CC[1:0]) (see Table 50: Clock control bits).
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Figure 55. Pulse width modulation cycle
Pulse-width modulation cycle
When
Counter
= OC1R
OCMP1 = OLVL1
OCMP1 = OLVL2
When
Counter
= OC2R
Counter is reset
to FFFCh
ICF1 bit is set
If OLVL1=1 and OLVL2=0 the length of the positive pulse is the difference between the
OC2R and OC1R registers.
If OLVL1=OLVL2 a continuous signal will be seen on the OCMP1 pin.
The OCiR register value required for a specific timing application can be calculated using
the following formula:
t * fCPU
- 5
OCiR Value =
PRESC
Where:
■
■
■
t = Signal or pulse period (in seconds)
= CPU clock frequency (in Hertz)
f
CPU
PRESC = Timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits, see Table 50:
Clock control bits)
If the timer clock is an external clock the formula is:
OCiR = t * fEXT -5
Where:
■
■
t = Signal or pulse period (in seconds)
= External timer clock frequency (in Hertz)
f
EXT
The Output Compare 2 event causes the counter to be initialized to FFFCh (See Figure 54)
Note:
1
2
3
The OCF1 and OCF2 bits cannot be set by hardware in PWM mode; therefore, the Output
Compare interrupt is inhibited.
The ICF1 bit is set by hardware when the counter reaches the OC2R value; it can produce a
timer interrupt if the ICIE bit is set and the I bit is cleared.
In PWM mode, the ICAP1 pin cannot be used to perform an input capture because it is
disconnected to the timer. The ICAP2 pin can be used to perform an input capture (ICF2 can
be set and IC2R can be loaded) but the user must take care that the counter is reset each
period, and ICF1 can also generate an interrupt if ICIE is set.
4
When the pulse-width modulation (PWM) and One-pulse mode (OPM) bits are both set, the
PWM mode is the only active one.
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On-chip peripherals
11.3.4
Low-power modes
Table 47. Low-power mode description
Mode
Description
No effect on 16-bit timer.
Wait
Timer interrupts cause the Device to exit from Wait mode.
16-bit timer registers are frozen.
In Halt mode, the counter stops counting until Halt mode is exited. Counting resumes from
the previous count when the Device is woken up by an interrupt with “exit from Halt mode”
capability or from the counter reset value when the Device is woken up by a reset.
Halt
If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is
armed. Consequently, when the Device is woken up by an interrupt with “exit from Halt
mode” capability, the ICFi bit is set, and the counter value present when exiting from Halt
mode is captured into the ICiR register.
11.3.5
Interrupts
Table 48. Interrupt events
Interrupt event
Event
flag
Enable Exit from Exitfrom
control bit
Wait
Halt
Input Capture 1 event/Counter reset in PWM mode
Input Capture 2 event
ICF1
ICF2
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
ICIE
Output Compare 1 event (not available in PWM mode) OCF1
Output Compare 2 event (not available in PWM mode) OCF2
OCIE
TOIE
Timer overflow event
TOF
Note:
The 16-bit timer interrupt events are connected to the same interrupt vector (see Section 8:
Interrupts). These events generate an interrupt if the corresponding Enable Control Bit is set
and the interrupt mask in the CC register is reset (RIM instruction).
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11.3.6
Summary of timer modes
Table 49. Timer modes
Available resources
Modes
Input Capture 1
Input Capture 2
Output Compare 1 Output Compare 2
Input Capture (1 and/or 2)
Output Compare (1 and/or 2)
One-pulse mode
Yes
Yes
No
Yes
Yes
Yes
No
Yes
Yes
Yes
Not recommended (1)
Not recommended (3)
Partially (2)
PWM mode
No
No
No
1. See note 4 in One-pulse mode.
2. See note 5 in One-pulse mode.
3. See note 4 in Pulse-width modulation mode.
11.3.7
Register description
Each timer is associated with three control and status registers, and with six pairs of data
registers (16-bit values) related to the two input captures, the two output compares, the
counter and the alternate counter.
Control register 1 (CR1)
Read/Write
Reset value: 0000 0000 (00h)
7
0
ICIE
OCIE
TOIE
FOLV2
FOLV1
OLVL2
IEDG1
OLVL1
Read/Write
Bit 7 = ICIE Input Capture Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the ICF1 or ICF2 bit of the SR register is set.
Bit 6 = OCIE Output Compare Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the OCF1 or OCF2 bit of the SR register is
set.
Bit 5 = TOIE Timer Overflow Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is enabled whenever the TOF bit of the SR register is set.
Bit 4 = FOLV2 Forced Output Compare 2.
This bit is set and cleared by software.
0: No effect on the OCMP2 pin.
1: Forces the OLVL2 bit to be copied to the OCMP2 pin, if the OC2E bit is set and even
if there is no successful comparison.
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On-chip peripherals
Bit 3 = FOLV1 Forced Output Compare 1.
This bit is set and cleared by software.
0: No effect on the OCMP1 pin.
1: Forces OLVL1 to be copied to the OCMP1 pin, if the OC1E bit is set and even if there
is no successful comparison.
Bit 2 = OLVL2 Output Level 2.
This bit is copied to the OCMP2 pin whenever a successful comparison occurs with the
OC2R register and OCxE is set in the CR2 register. This value is copied to the OCMP1
pin in One-pulse mode and Pulse-width modulation mode.
Bit 1 = IEDG1 Input Edge 1.
This bit determines which type of level transition on the ICAP1 pin will trigger the
capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
Bit 0 = OLVL1 Output Level 1.
The OLVL1 bit is copied to the OCMP1 pin whenever a successful comparison occurs
with the OC1R register and the OC1E bit is set in the CR2 register.
Control register 2 (CR2)
Reset value: 0000 0000 (00h)
7
0
OC1E
OC2E
OPM
PWM
Read/Write
Bit 7 = OC1E Output Compare 1 Pin Enable.
CC1
CC0
IEDG2
EXEDG
This bit is used only to output the signal from the timer on the OCMP1 pin (OLV1 in
Output Compare mode, both OLV1 and OLV2 in PWM and one-pulse mode). Whatever
the value of the OC1E bit, the Output Compare 1 function of the timer remains active.
0: OCMP1 pin alternate function disabled (I/O pin free for general-purpose I/O).
1: OCMP1 pin alternate function enabled.
Bit 6 = OC2E Output Compare 2 Pin Enable.
This bit is used only to output the signal from the timer on the OCMP2 pin (OLV2 in
Output Compare mode). Whatever the value of the OC2E bit, the Output Compare 2
function of the timer remains active.
0: OCMP2 pin alternate function disabled (I/O pin free for general-purpose I/O).
1: OCMP2 pin alternate function enabled.
Bit 5 = OPM One-pulse Mode.
0: One-pulse Mode is not active.
1: One-pulse Mode is active, the ICAP1 pin can be used to trigger one pulse on the
OCMP1 pin; the active transition is given by the IEDG1 bit. The length of the generated
pulse depends on the contents of the OC1R register.
Bit 4 = PWM Pulse-Width Modulation.
0: PWM mode is not active.
1: PWM mode is active, the OCMP1 pin outputs a programmable cyclic signal; the
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On-chip peripherals
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length of the pulse depends on the value of OC1R register; the period depends on the
value of OC2R register.
Bits 3:2 = CC[1:0] Clock Control.
The timer clock mode depends on these bits:
Table 50. Clock control bits
Timer clock
CC1
CC0
f
f
f
CPU / 4
CPU / 2
CPU / 8
0
0
1
1
0
1
0
1
External clock (where available)
Note:
If the external clock pin is not available, programming the external clock configuration stops
the counter.
Bit 1 = IEDG2 Input Edge 2.
This bit determines which type of level transition on the ICAP2 pin will trigger the
capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
Bit 0 = EXEDG External Clock Edge.
This bit determines which type of level transition on the external clock pin EXTCLK will
trigger the counter register.
0: A falling edge triggers the counter register.
1: A rising edge triggers the counter register.
Control/status register (CSR)
Reset value: 0000 0000 (00h)
The three least significant bits are not used.
7
0
0
ICF1
OCF1
TOF
ICF2
OCF2
TIMD
0
Read-only
Bit 7 = ICF1 Input Capture Flag 1.
0: No input capture (reset value).
1: An input capture has occurred on the ICAP1 pin or the counter has reached the
OC2R value in PWM mode. To clear this bit, first read the SR register, then read or
write the low byte of the IC1R (IC1LR) register.
Bit 6 = OCF1 Output Compare Flag 1.
0: No match (reset value).
1: The content of the free running counter has matched the content of the OC1R
register. To clear this bit, first read the SR register, then read or write the low byte of the
OC1R (OC1LR) register.
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On-chip peripherals
Bit 5 = TOF Timer Overflow Flag.
0: No timer overflow (reset value).
1: The free running counter rolled over from FFFFh to 0000h. To clear this bit, first read
the SR register, then read or write the low byte of the CR (CLR) register.
Note:
Reading or writing the ACLR register does not clear TOF.
Bit 4 = ICF2 Input Capture Flag 2.
0: No input capture (reset value).
1: An input capture has occurred on the ICAP2 pin. To clear this bit, first read the SR
register, then read or write the low byte of the IC2R (IC2LR) register.
Bit 3 = OCF2 Output Compare Flag 2.
0: No match (reset value).
1: The content of the free running counter has matched the content of the OC2R
register. To clear this bit, first read the SR register, then read or write the low byte of the
OC2R (OC2LR) register.
Bit 2 = TIMD Timer disable.
This bit is set and cleared by software. When set, it freezes the timer prescaler and
counter and disabled the output functions (OCMP1 and OCMP2 pins) to reduce power
consumption. Access to the timer registers is still available, allowing the timer
configuration to be changed while it is disabled.
0: Timer enabled
1: Timer prescaler, counter and outputs disabled
Bits 1:0 = Reserved, must be kept cleared.
Input capture 1 high register (IC1HR)
Reset value: Undefined
This is an 8-bit read-only register that contains the high part of the counter value (transferred
by the input capture 1 event).
7
0
MSB
LSB
Read Only
Input capture 1 low register (IC1LR)
Reset value: Undefined
This is an 8-bit read only register that contains the low part of the counter value (transferred
by the input capture 1 event).
7
0
MSB
LSB
Read Only
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Output compare 1 high register (OC1HR)
Read/Write
Reset value: 1000 0000 (80h)
This is an 8-bit register that contains the high part of the value to be compared to the CHR
register.
7
0
MSB
LSB
Read/Write
Output compare 1 low register (OC1LR)
Reset value: 0000 0000 (00h)
This is an 8-bit register that contains the low part of the value to be compared to the CLR
register.
7
0
MSB
LSB
Read/Write
Output compare 2 high register (OC2HR)
Reset value: 1000 0000 (80h)
This is an 8-bit register that contains the high part of the value to be compared to the CHR
register.
7
0
MSB
LSB
Read/Write
Output compare 2 low register (OC2LR)
Reset value: 0000 0000 (00h)
This is an 8-bit register that contains the low part of the value to be compared to the CLR
register.
7
0
MSB
LSB
Read/Write
Counter high register (CHR)
Reset value: 1111 1111 (FFh)
This is an 8-bit register that contains the high part of the counter value.
7
0
MSB
LSB
Read-only
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On-chip peripherals
Counter low register (CLR)
Reset value: 1111 1100 (FCh)
This is an 8-bit register that contains the low part of the counter value. A write to this register
resets the counter. An access to this register, after accessing the CSR register, clears the
TOF bit.
7
0
MSB
LSB
Read-only
Alternate counter high register (ACHR)
Reset value: 1111 1111 (FFh)
This is an 8-bit register that contains the high part of the counter value.
7
0
MSB
LSB
Read-only
Alternate counter low register (ACLR)
Reset value: 1111 1100 (FCh)
This is an 8-bit register that contains the low part of the counter value. A write to this register
resets the counter. An access to this register after an access to CSR register does not clear
the TOF bit in the CSR register.
7
0
MSB
LSB
Read-only
Input capture 2 high register (IC2HR)
Reset value: Undefined
This is an 8-bit read only register that contains the high part of the counter value (transferred
by the Input Capture 2 event).
7
0
MSB
LSB
Read-only
Input capture 2 low register (IC2LR)
Reset value: Undefined
This is an 8-bit read only register that contains the low part of the counter value (transferred
by the Input Capture 2 event).
7
0
MSB
LSB
Read-only
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Table 51. 16-bit timer register map and reset values
Address
(Hex.)
Register
label
7
6
5
4
3
2
1
0
Timer A: 32 CR1
Timer B: 42 Reset value 0
ICIE
OCIE
0
TOIE
0
FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
0
0
0
0
0
Timer A: 31 CR2
OC1E OC2E OPM
Timer B: 41 Reset value 0
PWM
0
CC1
0
CC0
0
IEDG2 EXEDG
0
0
0
0
Timer A: 33 CSR
Timer B: 43 Reset value x
ICF1
OCF1 TOF
ICF2
x
OCF2 TIMD
-
x
-
x
x
x
x
0
0
0
0
1
1
1
1
x
x
x
x
x
0
0
0
0
1
1
1
1
x
x
x
x
x
0
0
0
0
1
1
0
x
x
0
0
0
0
1
1
Timer A: 34 IC1HR
Timer B: 44 Reset value x
MSB
LSB
x
x
x
0
0
0
0
1
1
x
x
0
0
0
0
1
0
Timer A: 35 IC1LR
Timer B: 45 Reset value x
MSB
LSB
x
Timer A: 36 OC1HR
Timer B: 46 Reset value 1
MSB
LSB
0
Timer A: 37 OC1LR
Timer B: 47 Reset value 0
MSB
LSB
0
Timer A: 3E OC2HR
Timer B: 4E Reset value 1
MSB
LSB
0
Timer A: 3F OC2LR
Timer B: 4F Reset value 0
MSB
LSB
0
Timer A: 38 CHR
Timer B: 48 Reset value 1
MSB
LSB
1
Timer A: 39 CLR
Timer B: 49 Reset value 1
MSB
LSB
0
Timer A: 3A ACHR
Timer B: 4A Reset value 1
MSB
LSB
1
1
1
1
1
1
1
Timer A: 3B ACLR
Timer B: 4B Reset value 1
MSB
LSB
0
1
0
x
x
Timer A: 3C IC2HR
Timer B: 4C Reset value x
MSB
LSB
x
x
x
x
x
x
x
Timer A: 3D IC2LR
Timer B: 4D Reset value x
MSB
LSB
x
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On-chip peripherals
11.4
Serial peripheral interface (SPI)
11.4.1
Introduction
The serial peripheral interface (SPI) allows full-duplex, synchronous, serial communication
with external devices. An SPI system may consist of a master and one or more slaves, or a
system in which devices may be either masters or slaves.
11.4.2
Main features
■
■
■
■
■
■
■
■
■
Full-duplex synchronous transfers (on three lines)
Simplex synchronous transfers (on two lines)
Master or slave operation
6 master mode frequencies (f
/4 max.)
CPU
f
/2 max. slave mode frequency (see the note)
CPU
SS Management by software or hardware
Programmable clock polarity and phase
End-of-transfer interrupt flag
Write collision, master mode fault and Overrun flags
Note:
In slave mode, continuous transmission is not possible at maximum frequency due to the
software overhead for clearing status flags and to initiate the next transmission sequence.
11.4.3
General description
Figure 56 on page 116 shows the serial peripheral interface (SPI) block diagram. There are
three registers:
■
■
■
SPI Control Register (SPICR)
SPI Control/Status Register (SPICSR)
SPI Data Register (SPIDR)
The SPI is connected to external devices through four pins:
■
■
■
■
MISO: Master In / Slave Out data
MOSI: Master Out / Slave In data
SCK: Serial Clock out by SPI masters and input by SPI slaves
SS: Slave select:
This input signal acts as a ‘chip select’ to let the SPI master communicate with slaves
individually and to avoid contention on the data lines. Slave SS inputs can be driven by
standard I/O ports on the master Device.
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Figure 56. Serial peripheral interface block diagram
Data/Address Bus
Read
SPIDR
Interrupt
request
Read Buffer
MOSI
MISO
7
0
SPICSR
8-bit Shift Register
SPIF WCOL OVR MODF
0
SOD SSM SSI
Write
SOD
bit
1
SS
SPI
STATE
0
SCK
CONTROL
7
0
SPICR
MSTR
SPR0
SPIE SPE SPR2
CPOL CPHA SPR1
MASTER
CONTROL
SERIAL CLOCK
GENERATOR
SS
Functional description
A basic example of interconnections between a single master and a single slave is
illustrated in Figure 57.
The MOSI pins are connected together and the MISO pins are connected together. In this
way data is transferred serially between master and slave (most significant bit first).
The communication is always initiated by the master. When the master device transmits
data to a slave device via MOSI pin, the slave device responds by sending data to the
master device via the MISO pin. This implies full duplex communication with both data out
and data in, synchronized with the same clock signal (which is provided by the master
device via the SCK pin).
To use a single data line, the MISO and MOSI pins must be connected at each node (in this
case only simplex communication is possible).
Four possible data/clock timing relationships may be chosen (see Figure 60) but master and
slave must be programmed with the same timing mode.
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Figure 57. Single master/ single slave application
SLAVE
MASTER
MSBit
LSBit
MSBit
LSBit
MISO
MOSI
MISO
MOSI
8-bit SHIFT REGISTER
8-bit SHIFT REGISTER
SPI
CLOCK
GENERATOR
SCK
SS
SCK
SS
+5V
Not used if SS is managed
by software
Slave select management
As an alternative to using the SS pin to control the Slave Select signal, the application can
choose to manage the Slave Select signal by software. This is configured by the SSM bit in
the SPICSR register (see Figure 59).
In software management, the external SS pin is free for other application uses and the
internal SS signal level is driven by writing to the SSI bit in the SPICSR register.
■
In Master mode:
–
SS internal must be held high continuously
■
In Slave Mode:
There are two cases depending on the data/clock timing relationship (see Figure 58):
If CPHA = 1 (data latched on second clock edge):
–
SS internal must be held low during the entire transmission. This implies that in
single slave applications the SS pin either can be tied to V , or made free for
SS
standard I/O by managing the SS function by software (SSM = 1 and SSI = 0 in
the in the SPICSR register)
If CPHA = 0 (data latched on first clock edge):
–
SS internal must be held low during byte transmission and pulled high between
each byte to allow the slave to write to the shift register. If SS is not pulled high, a
Write Collision error will occur when the slave writes to the shift register (see Write
collision error (WCOL)).
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Figure 58. Generic SS timing diagram
Byte 3
Byte 1
Byte 2
MOSI/MISO
Master SS
Slave SS
(if CPHA = 0)
Figure 59. Hardware/software slave select management
SSM bit
SSI bit
1
0
SS internal
SS external pin
Master mode operation
In master mode, the serial clock is output on the SCK pin. The clock frequency, polarity and
phase are configured by software (refer to the description of the SPICSR register).
Note:
The idle state of SCK must correspond to the polarity selected in the SPICSR register (by
pulling up SCK if CPOL = 1 or pulling down SCK if CPOL = 0).
How to operate the SPI in master mode
To operate the SPI in master mode, perform the following steps in order:
1. Write to the SPICR register:
–
–
Select the clock frequency by configuring the SPR[2:0] bits.
Select the clock polarity and clock phase by configuring the CPOL and CPHA bits.
Figure 60 shows the four possible configurations.
Note that the slave must have the same CPOL and CPHA settings as the master.
2. Write to the SPICSR register:
Either set the SSM bit and set the SSI bit or clear the SSM bit and tie the SS pin
high for the complete byte transmit sequence.
3. Write to the SPICR register:
–
–
Set the MSTR and SPE bits
Note that the MSTR and SPE bits remain set only if SS is high).
Note:
Important: if the SPICSR register is not written first, the SPICR register setting (MSTR bit)
may be not taken into account.
The transmit sequence begins when the software writes a byte in the SPIDR register.
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Master mode transmit sequence
When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift
register and then shifted out serially to the MOSI pin most significant bit first.
When data transfer is complete:
■
■
The SPIF bit is set by hardware.
An interrupt request is generated if the SPIE bit is set and the interrupt mask in the
CCR register is cleared.
Clearing the SPIF bit is performed by the following software sequence:
1. An access to the SPICSR register while the SPIF bit is set
2. A read to the SPIDR register
Note:
While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR
register is read.
Slave mode operation
In slave mode, the serial clock is received on the SCK pin from the master device.
To operate the SPI in slave mode:
1. Write to the SPICSR register to perform the following actions:
–
Select the clock polarity and clock phase by configuring the CPOL and CPHA bits
(see Figure 60).
Note that the slave must have the same CPOL and CPHA settings as the master.
–
Manage the SS pin as described in Slave select management and Figure 58.
If CPHA = 1, SS must be held low continuously.
If CPHA = 0, SS must be held low during byte transmission and pulled up between
each byte to let the slave write in the shift register.
2. Write to the SPICR register to clear the MSTR bit and set the SPE bit to enable the SPI
I/O functions.
Slave mode transmit sequence
When the software writes to the SPIDR register, the data byte is loaded into the 8-bit shift
register and then shifted out serially to the MISO pin most significant bit first.
The transmit sequence begins when the slave device receives the clock signal and the most
significant bit of the data on its MOSI pin.
When data transfer is complete:
■
■
The SPIF bit is set by hardware.
An interrupt request is generated if SPIE bit is set and interrupt mask in the CCR
register is cleared.
Clearing the SPIF bit is performed by the following software sequence:
1. An access to the SPICSR register while the SPIF bit is set
2. A write or a read to the SPIDR register
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Note:
While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR
register is read.
The SPIF bit can be cleared during a second transmission; however, it must be cleared
before the second SPIF bit in order to prevent an Overrun condition (see Overrun condition
(OVR)).
11.4.4
Clock phase and clock polarity
Four possible timing relationships may be chosen by software, using the CPOL and CPHA
bits (See Figure 60).
Note:
The idle state of SCK must correspond to the polarity selected in the SPICSR register (by
pulling up SCK if CPOL = 1 or pulling down SCK if CPOL = 0).
The combination of the CPOL clock polarity and CPHA (clock phase) bits selects the data
capture clock edge.
Figure 60 shows an SPI transfer with the four combinations of the CPHA and CPOL bits.
The diagram may be interpreted as a master or slave timing diagram where the SCK pin, the
MISO pin and the MOSI pin are directly connected between the master and the slave
device.
Note:
If CPOL is changed at the communication byte boundaries, the SPI must be disabled by
resetting the SPE bit.
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Figure 60. Data clock timing diagram
CPHA = 1
SCK
(CPOL = 1)
SCK
(CPOL = 0)
Bit 4
Bit 4
Bit3
Bit3
Bit 2
Bit 2
Bit 1
LSBit
LSBit
MSBit
MSBit
Bit 6
Bit 6
Bit 5
Bit 5
MISO
(from master)
Bit 1
MOSI
(from slave)
SS
(to slave)
CAPTURE STROBE
CPHA = 0
SCK
(CPOL = 1)
SCK
(CPOL = 0)
Bit 4
Bit 4
Bit3
Bit3
Bit 2
Bit 2
Bit 1
Bit 1
LSBit
LSBit
MISO
(from master)
MSBit
Bit 6
Bit 6
Bit 5
Bit 5
MOSI
(from slave)
MSBit
SS
(to slave)
CAPTURE STROBE
1. This figure should not be used as a replacement for parametric information. Refer to Section 13: Electrical
characteristics.
11.4.5
Error flags
Master mode fault (MODF)
Master mode fault occurs when the master device’s SS pin is pulled low.
When a Master mode fault occurs:
■
■
The MODF bit is set and an SPI interrupt request is generated if the SPIE bit is set.
The SPE bit is reset. This blocks all output from the device and disables the SPI
peripheral.
■
The MSTR bit is reset, thus forcing the device into slave mode.
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Clearing the MODF bit is done through a software sequence:
1. A read access to the SPICSR register while the MODF bit is set.
2. A write ac cess to the SPICR register.
Note:
To avoid any conflicts in an application with multiple slaves, the SS pin must be pulled high
during the MODF bit clearing sequence. The SPE and MSTR bits may be restored to their
original state during or after this clearing sequence.
The hardware does not allow the user to set the SPE and MSTR bits while the MODF bit is
set, except in the MODF bit clearing sequence.
In a slave device, the MODF bit can not be set, but in a multimaster configuration the device
can be in slave mode with the MODF bit set.
The MODF bit indicates that there might have been a multimaster conflict and allows
software to handle this using an interrupt routine and either perform a reset or return to an
application default state.
Overrun condition (OVR)
An overrun condition occurs when the master device has sent a data byte and the slave
device has not cleared the SPIF bit issued from the previously transmitted byte.
When an Overrun occurs:
■
The OVR bit is set, and an interrupt request is generated if the SPIE bit is set.
In this case, the receiver buffer contains the byte sent after the SPIF bit was last cleared. A
read to the SPIDR register returns this byte. All other bytes are lost.
The OVR bit is cleared by reading the SPICSR register.
Write collision error (WCOL)
A write collision occurs when the software tries to write to the SPIDR register while a data
transfer is taking place with an external device. When this happens, the transfer continues
uninterrupted and the software write will be unsuccessful.
Write collisions can occur both in master and slave mode. See also Slave select
management.
Note:
A “read collision” will never occur since the received data byte is placed in a buffer in which
access is always synchronous with the CPU operation.
The WCOL bit in the SPICSR register is set if a write collision occurs.
No SPI interrupt is generated when the WCOL bit is set (the WCOL bit is a status flag only).
Clearing the WCOL bit is done through a software sequence (see Figure 61).
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Figure 61. Clearing the WCOL bit (write collision flag) software sequence
Clearing sequence after SPIF = 1 (end of a data byte transfer)
Read SPICSR
1st Step
RESULT
SPIF = 0
WCOL = 0
2nd Step
Read SPIDR
Clearing sequence before SPIF = 1 (during a data byte transfer)
Read SPICSR
1st Step
RESULT
2nd Step
Read SPIDR
WCOL = 0
1. Writing to the SPIDR register instead of reading it does not reset the WCOL bit.
Single master and multimaster configurations
There are two types of SPI systems: Single master system and Multimaster system.
■
Single master system
A typical single master system may be configured using a device as the master and
four devices as slaves (see Figure 62).
The master device selects the individual slave devices by using four pins of a parallel
port to control the four SS pins of the slave devices.
The SS pins are pulled high during reset since the master device ports will be forced to
be inputs at that time, thus disabling the slave devices.
Note: To prevent a bus conflict on the MISO line, the master allows only one active
slave device during a transmission.
For more security, the slave device may respond to the master with the received data
byte. Then the master will receive the previous byte back from the slave device if all
MISO and MOSI pins are connected and the slave has not written to its SPIDR register.
Other transmission security methods can use ports for handshake lines or data bytes
with command fields.
■
Multimaster system
A multimaster system may also be configured by the user. Transfer of master control
could be implemented using a handshake method through the I/O ports or by an
exchange of code messages through the serial peripheral interface system.
The multimaster system is principally handled by the MSTR bit in the SPICR register,
and the MODF bit in the SPICSR register.
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Figure 62. Single master / multiple slave configuration
SS
SS
SS
SS
SCK
Slave
Device
SCK
Slave
SCK
Slave
Device
SCK
Slave
Device
Device
MOSI MISO
MOSI MISO
MOSI MISO
MOSI MISO
MOSI MISO
SCK
Master
Device
5V
SS
11.4.6
Low-power modes
Table 52. Description
Mode
Description
No effect on SPI.
Wait
SPI interrupt events cause the device to exit from Wait mode.
SPI registers are frozen.
In Halt mode, the SPI is inactive. SPI operation resumes when the device is woken up by
an interrupt with “exit from Halt mode” capability. The data received is subsequently read
from the SPIDR register when the software is running (interrupt vector fetching). If several
data are received before the wake-up event, then an overrun error is generated. This error
can be detected after the fetch of the interrupt routine that woke up the Device.
Halt
Using the SPI to wake up the device from Halt mode
In slave configuration, the SPI is able to wake up the device from Halt mode through a SPIF
interrupt. The data received is subsequently read from the SPIDR register when the
software is running (interrupt vector fetch). If multiple data transfers have been performed
before software clears the SPIF bit, then the OVR bit is set by hardware.
Note:
When waking up from Halt mode, if the SPI remains in Slave mode, it is recommended to
perform an extra communications cycle to bring the SPI from Halt mode state to normal
state. If the SPI exits from Slave mode, it returns to normal state immediately.
Caution:
The SPI can wake up the device from Halt mode only if the Slave Select signal (external SS
pin or the SSI bit in the SPICSR register) is low when the device enters Halt mode. So, if
Slave selection is configured as external (see Slave select management), make sure the
master drives a low level on the SS pin when the slave enters Halt mode.
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11.4.7
Interrupts
Table 53. Interrupt events
Interrupt event
Enable control
bit
Event flag
Exit from Wait Exit from Halt
SPI end of transfer event
Master mode fault event
Overrun error
SPIF
MODF
OVR
Yes
SPIE
Yes
No
Note:
The SPI interrupt events are connected to the same interrupt vector (see Section 8:
Interrupts).
They generate an interrupt if the corresponding Enable Control Bit is set and the interrupt
mask in the CC register is reset (RIM instruction).
11.4.8
Register description
SPI control register (SPICR)
Reset value: 0000 xxxx (0xh)
7
0
SPIE
SPE
SPR2
MSTR
CPOL
CPHA
SPR1
SPR0
Read/Write
Bit 7 = SPIE Serial Peripheral Interrupt Enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SPI interrupt is generated whenever an End of Transfer event, Master Mode Fault
or Overrun error occurs (SPIF = 1, MODF = 1 or OVR = 1 in the SPICSR register)
Bit 6 = SPE Serial Peripheral Output Enable
This bit is set and cleared by software. It is also cleared by hardware when, in master
mode, SS = 0 (see Master mode fault (MODF)). The SPE bit is cleared by reset, so the
SPI peripheral is not initially connected to the external pins.
0: I/O pins free for general purpose I/O
1: SPI I/O pin alternate functions enabled
Bit 5 = SPR2 Divider Enable
This bit is set and cleared by software and is cleared by reset. It is used with the
SPR[1:0] bits to set the baud rate. Refer to Table 54: SPI master mode SCK frequency.
0: Divider by 2 enabled
1: Divider by 2 disabled
Note:
This bit has no effect in slave mode.
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Bit 4 = MSTR Master Mode
This bit is set and cleared by software. It is also cleared by hardware when, in master
mode, SS = 0 (see Master mode fault (MODF)).
0: Slave mode
1: Master mode. The function of the SCK pin changes from an input to an output and
the functions of the MISO and MOSI pins are reversed.
Bit 3 = CPOL Clock Polarity
This bit is set and cleared by software. This bit determines the idle state of the serial
Clock. The CPOL bit affects both the master and slave modes.
0: SCK pin has a low level idle state
1: SCK pin has a high level idle state
Note:
If CPOL is changed at the communication byte boundaries, the SPI must be disabled by
resetting the SPE bit.
Bit 2 = CPHA Clock Phase
This bit is set and cleared by software.
0: The first clock transition is the first data capture edge.
1: The second clock transition is the first capture edge.
Note:
Note:
The slave must have the same CPOL and CPHA settings as the master.
Bits 1:0 = SPR[1:0] Serial clock frequency
These bits are set and cleared by software. Used with the SPR2 bit, they select the
baud rate of the SPI serial clock SCK output by the SPI in master mode.
These 2 bits have no effect in slave mode.
Table 54. SPI master mode SCK frequency
Serial clock
CPU/4
SPR2
SPR1
SPR0
f
1
0
1
0
1
fCPU/8
0
0
1
0
fCPU/16
f
CPU/32
fCPU/64
1
fCPU/128
SPI control/status register (SPICSR)
Reset value: 0000 0000 (00h)
7
0
SPIF
WCOL
OVR
MODF
-
SOD
SSM
SSI
Read-only
Reserved
Read/Write
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Bit 7 = SPIF Serial Peripheral Data Transfer Flag (Read-only)
This bit is set by hardware when a transfer has been completed. An interrupt is
generated if SPIE = 1 in the SPICR register. It is cleared by a software sequence (an
access to the SPICSR register followed by a write or a read to the SPIDR register).
0: Data transfer is in progress or the flag has been cleared.
1: Data transfer between the device and an external device has been completed.
Note:
While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR
register is read.
Bit 6 = WCOL Write collision status (Read-only)
This bit is set by hardware when a write to the SPIDR register is done during a transmit
sequence. It is cleared by a software sequence (see Figure 61).
0: No write collision occurred
1: A write collision has been detected
Bit 5 = OVR SPI overrun error (Read-only)
This bit is set by hardware when the byte currently being received in the shift register is
ready to be transferred into the SPIDR register while SPIF = 1 (See Overrun condition
(OVR)). An interrupt is generated if SPIE = 1 in the SPICR register. The OVR bit is
cleared by software reading the SPICSR register.
0: No overrun error
1: Overrun error detected
Bit 4 = MODF Mode fault flag (Read-only)
This bit is set by hardware when the SS pin is pulled low in master mode (see Master
mode fault (MODF)). An SPI interrupt can be generated if SPIE = 1 in the SPICR
register. This bit is cleared by a software sequence (An access to the SPICSR register
while MODF = 1 followed by a write to the SPICR register).
0: No master mode fault detected
1: A fault in master mode has been detected
Bit 3 = Reserved, must be kept cleared.
Bit 2 = SOD SPI Output disable
This bit is set and cleared by software. When set, it disables the alternate function of
the SPI output (MOSI in master mode / MISO in slave mode)
0: SPI output enabled (if SPE = 1)
1: SPI output disabled
Bit 1 = SSM SS management
This bit is set and cleared by software. When set, it disables the alternate function of
the SPI SS pin and uses the SSI bit value instead. See Slave select management.
0: Hardware management (SS managed by external pin)
1: Software management (internal SS signal controlled by SSI bit. External SS pin free
for general-purpose I/O)
Bit 0 = SSI SS internal mode
This bit is set and cleared by software. It acts as a ‘chip select’ by controlling the level of
the SS slave select signal when the SSM bit is set.
0: Slave selected
1: Slave deselected
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SPI data I/O register (SPIDR)
Reset value: Undefined
7
0
D7
D6
D5
D4
D3
D2
D1
D0
Read/Write
The SPIDR register is used to transmit and receive data on the serial bus. In a master
device, a write to this register will initiate transmission/reception of another byte.
Note:
During the last clock cycle the SPIF bit is set, a copy of the received data byte in the shift
register is moved to a buffer. When the user reads the serial peripheral data I/O register, the
buffer is actually being read.
While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR
register is read.
Warning: A write to the SPIDR register places data directly into the
shift register for transmission.
A read to the SPIDR register returns the value located in the buffer and not the content of
the shift register (see Figure 56).
Table 55. SPI register map and reset values
Address
(Hex.)
Register
label
7
6
5
4
3
2
1
0
SPIDR
Reset value
MSB
x
LSB
x
0021h
0022h
0023h
x
x
x
x
x
x
SPICR
Reset value
SPIE
0
SPE
0
SPR2
0
MSTR CPOL CPHA
SPR1
x
SPR0
x
0
x
x
SPICSR
Reset value
SPIF
0
WCOL OR
0
MODF
0
SOD
0
SSM
0
SSI
0
0
0
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11.5
SCI serial communication interface
11.5.1
Introduction
The serial communications interface (SCI) offers a flexible means of full-duplex data
exchange with external equipment requiring an industry standard NRZ asynchronous serial
data format. The SCI offers a very wide range of baud rates using two baud rate generator
systems.
11.5.2
Main features
■
■
■
■
■
■
■
Full-duplex, asynchronous communications
NRZ standard format (Mark/Space)
Dual baud rate generator systems
Independently programmable transmit and receive baud rates up to 500,000 baud
Programmable data word length (8 or 9 bits)
Receive buffer full, Transmit buffer empty and End of Transmission flags
2 receiver wake-up modes:
–
–
Address bit (MSB)
Idle line
■
■
■
Muting function for multiprocessor configurations
Separate enable bits for Transmitter and Receiver
4 error detection flags:
–
–
–
–
Overrun error
Noise error
Frame error
Parity error
■
5 interrupt sources with flags:
–
–
–
–
–
Transmit data register empty
Transmission complete
Receive data register full
Idle line received
Overrun error detected
■
■
Parity control:
–
–
Transmits parity bit
Checks parity of received data byte
Reduced power consumption mode
11.5.3
General description
The interface is externally connected to another device by three pins (see Figure 63). Any
SCI bidirectional communication requires a minimum of two pins: Receive Data In (RDI) and
Transmit Data Out (TDO):
■
SCLK: Transmitter clock output. This pin outputs the transmitter data clock for
synchronous transmission (no clock pulses on start bit and stop bit, and a software
option to send a clock pulse on the last data bit). This can be used to control
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peripherals that have shift registers (e.g. LCD drivers). The clock phase and polarity
are software programmable.
■
■
TDO: Transmit Data Output. When the transmitter is disabled, the output pin returns to
its I/O port configuration. When the transmitter is enabled and nothing is to be
transmitted, the TDO pin is at high level.
RDI: Receive Data Input is the serial data input. Oversampling techniques are used for
data recovery by discriminating between valid incoming data and noise.
Through these pins, serial data is transmitted and received as frames comprising:
■
■
■
■
An Idle Line prior to transmission or reception
A start bit
A data word (8 or 9 bits) least significant bit first
A Stop bit indicating that the frame is complete.
This interface uses two types of baud rate generator:
■
■
A conventional type for commonly-used baud rates,
An extended type with a prescaler offering a very wide range of baud rates, even with
non-standard oscillator frequencies.
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Figure 63. SCI block diagram
Write
Read
(DATA REGISTER) SCIDR
Receive Data Register (RDR)
Receive Shift Register
Transmit Data Register (TDR)
TDO
RDI
Transmit Shift Register
R8
T8 SCID
M
WAKE PCE PS PIE
SCICR1
WAKE
UP
TRANSMIT
CONTROL
RECEIVER
CLOCK
RECEIVER
CONTROL
UNIT
SCISR
SCICR2
TDRE TC RDRF IDLE OR NF FE
PE
TIE TCIE RIE ILIE TE RE RWU SBK
SCI
INTERRUPT
CONTROL
TRANSMITTER
CLOCK
TRANSMITTER RATE
CONTROL
f
CPU
/PR
/16
SCIBRR
SCP1
SCT2
SCT1SCT0SCR2 SCR1SCR0
SCP0
RECEIVER RATE
CONTROL
CONVENTIONAL BAUD RATE GENERATOR
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11.5.4
Functional description
The block diagram of the Serial Control Interface, is shown in Figure 63. It contains six
dedicated registers:
■
■
■
■
2 control registers (SCICR1 and SCICR2)
A status register (SCISR)
A baud rate register (SCIBRR)
An extended prescaler receiver register
(SCIERPR)
■
An extended prescaler transmitter register
(SCIETPR)
Refer to the register descriptions in Section 11.5.7 for the definitions of each bit.
Serial data format
Word length may be selected as being either 8 or 9 bits by programming the M bit in the
SCICR1 register (see Figure 64).
The TDO pin is in low state during the start bit.
The TDO pin is in high state during the stop bit.
An Idle character is interpreted as an entire frame of “1”s followed by the start bit of the next
frame which contains data.
A Break character is interpreted on receiving “0”s for some multiple of the frame period. At
the end of the last break frame the transmitter inserts an extra “1” bit to acknowledge the
start bit.
Transmission and reception are driven by their own baud rate generator.
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Figure 64. Word length programming
9-bit (M bit is set)
Data Frame
Possible
Parity
Next Data Frame
Bit
Next
Start
Bit
Start
Bit
Stop
Bit
Bit2
Bit6
Bit3
Bit4
Bit5
Bit7
Bit8
Bit0 Bit1
CLOCK
(1)
Start
Bit
Idle Frame
Start
Bit
Extra
’1’
Break Frame
8-bit (M bit is reset)
Data Frame
Possible
Parity
Next Data Frame
Bit
Next
Start
Bit
Start
Bit
Stop
Bit
Bit2
Bit6
Bit0
Bit1
Bit3
Bit4
Bit5
Bit7
CLOCK
(1)
Start
Bit
Idle Frame
Start
Bit
Extra
’1’
Break Frame
1. LBCL bit controls last data clock pulse.
Transmitter
The transmitter can send data words of either 8 or 9 bits depending on the M bit status.
When the M bit is set, word length is 9 bits and the 9th bit (the MSB) has to be stored in the
T8 bit in the SCICR1 register.
When the transmit enable bit (TE) is set, the data in the transmit shift register is output on
the TDO pin.
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Character transmission
During an SCI transmission, data shifts out least significant bit first on the TDO pin. In
this mode, the SCIDR register consists of a buffer (TDR) between the internal bus and
the transmit shift register (see Figure 64).
Procedure:
–
–
–
–
Select the M bit to define the word length.
Select the desired baud rate using the SCIBRR and the SCIETPR registers.
Set the TE bit to send an idle frame as first transmission.
Access the SCISR register and write the data to send in the SCIDR register (this
sequence clears the TDRE bit). Repeat this sequence for each data to be
transmitted.
Clearing the TDRE bit is always performed by the following software sequence:
a) An access to the SCISR register
b) A write to the SCIDR register
The TDRE bit is set by hardware and it indicates:
–
–
–
The TDR register is empty.
The data transfer is beginning.
The next data can be written in the SCIDR register without overwriting the
previous data.
This flag generates an interrupt if the TIE bit is set and the I bit is cleared in the CCR
register.
When a transmission is taking place, a write instruction to the SCIDR register stores
the data in the TDR register and which is copied in the shift register at the end of the
current transmission.
When no transmission is taking place, a write instruction to the SCIDR register places
the data directly in the shift register; the data transmission starts, and the TDRE bit is
immediately set.
When a frame transmission is complete (after the stop bit or after the break frame) the
TC bit is set and an interrupt is generated if the TCIE is set and the I bit is cleared in the
CCR register.
Clearing the TC bit is performed by the following software sequence:
a) An access to the SCISR register
b) A write to the SCIDR register
Note:
The TDRE and TC bits are cleared by the same software sequence.
Break characters
Setting the SBK bit loads the shift register with a break character. The break frame
length depends on the M bit (see Figure 64).
As long as the SBK bit is set, the SCI send break frames to the TDO pin. After clearing
this bit by software the SCI insert a logic 1 bit at the end of the last break frame to
guarantee the recognition of the start bit of the next frame.
Idle characters
Setting the TE bit drives the SCI to send an idle frame before the first data frame.
Clearing and then setting the TE bit during a transmission sends an idle frame after the
current word.
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Note:
Resetting and setting the TE bit causes the data in the TDR register to be lost. Therefore,
the best time to toggle the TE bit is when the TDRE bit is set, that is, before writing the next
byte in the SCIDR.
Receiver
The SCI can receive data words of either 8 or 9 bits. When the M bit is set, the word length
is 9 bits and the MSB is stored in the R8 bit in the SCICR1 register.
Character reception
During a SCI reception, data shifts in least significant bit first through the RDI pin. In
this mode, the SCIDR register consists or a buffer (RDR) between the internal bus and
the received shift register (see Figure 63).
Procedure:
–
–
–
Select the M bit to define the word length.
Select the desired baud rate using the SCIBRR and the SCIERPR registers.
Set the RE bit, this enables the receiver which begins searching for a start bit.
When a character is received:
–
–
–
The RDRF bit is set. It indicates that the content of the shift register is transferred
to the RDR.
An interrupt is generated if the RIE bit is set and the I bit is cleared in the CCR
register.
The error flags can be set if a frame error, noise or an overrun error has been
detected during reception.
Clearing the RDRF bit is performed by the following software sequence done by:
a) An access to the SCISR register
b) A read to the SCIDR register.
The RDRF bit must be cleared before the end of the reception of the next character to
avoid an overrun error.
Break character
When a break character is received, the SCI handles it as a framing error.
Idle character
When an idle frame is detected, there is the same procedure as a data received
character plus an interrupt if the ILIE bit is set and the I bit is cleared in the CCR
register.
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Overrun error
An overrun error occurs when a character is received and RDRF has not been reset.
Data cannot be transferred from the shift register to the RDR register until the RDRF bit
is cleared.
When a overrun error occurs:
–
–
–
–
The OR bit is set.
The RDR content is not lost.
The shift register is overwritten.
An interrupt is generated if the RIE bit is set and the I bit is cleared in the CCR
register.
The OR bit is reset by an access to the SCISR register followed by a SCIDR register
read operation.
Noise error
Oversampling techniques are used for data recovery by discriminating between valid
incoming data and noise.
Normal data bits are considered valid if three consecutive samples (8th, 9th, 10th) have
the same bit value, otherwise the NF flag is set. In the case of start bit detection, the NF
flag is set on the basis of an algorithm combining both valid edge detection and three
samples (8th, 9th, 10th). Therefore, to prevent the NF flag getting set during start bit
reception, there should be a valid edge detection as well as three valid samples.
When noise is detected in a frame:
–
–
–
The NF flag is set at the rising edge of the RDRF bit.
Data is transferred from the Shift register to the SCIDR register.
No interrupt is generated. However this bit rises at the same time as the RDRF bit
which itself generates an interrupt.
The NF flag is reset by a SCISR register read operation followed by a SCIDR register
read operation.
During reception, if a false start bit is detected (e.g. 8th, 9th, 10th samples are
011,101,110), the frame is discarded and the receiving sequence is not started for this
frame. There is no RDRF bit set for this frame and the NF flag is set internally (not
accessible to the user). This NF flag is accessible along with the RDRF bit when a next
valid frame is received.
Note:
If the application Start Bit is not long enough to match the above requirements, then the NF
flag may get set due to the short Start Bit. In this case, the NF flag may be ignored by the
application software when the first valid byte is received.
See also Noise error causes.
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Framing error
A framing error is detected when:
–
The stop bit is not recognized on reception at the expected time, following either a
de-synchronization or excessive noise.
–
A break is received.
When the framing error is detected:
–
–
–
the FE bit is set by hardware
Data is transferred from the Shift register to the SCIDR register.
No interrupt is generated. However this bit rises at the same time as the RDRF bit
which itself generates an interrupt.
The FE bit is reset by a SCISR register read operation followed by an SCIDR register
read operation.
Figure 65. SCI baud rate and extended prescaler block diagram
TRANSMITTER
CLOCK
EXTENDED PRESCALER TRANSMITTER RATE CONTROL
SCIETPR
EXTENDED TRANSMITTER PRESCALER REGISTER
SCIERPR
EXTENDED RECEIVER PRESCALER REGISTER
RECEIVER
CLOCK
EXTENDED PRESCALER RECEIVER RATE CONTROL
EXTENDED PRESCALER
f
CPU
TRANSMITTER RATE
CONTROL
/PR
/16
SCIBRR
SCP1SCP0SCT2
SCT1 SCT0 SCR2 SCR1SCR0
RECEIVER RATE
CONTROL
CONVENTIONAL BAUD RATE GENERATOR
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Conventional baud rate generation
The baud rates for the receiver and transmitter (Rx and Tx) are set independently and
calculated as follows:
:
fCPU
fCPU
Rx =
Tx =
(16*PR)*RR
(16*PR)*TR
with:
PR = 1, 3, 4 or 13 (see SCP[1:0] bits)
TR = 1, 2, 4, 8, 16, 32, 64,128
(see SCT[2:0] bits)
RR = 1, 2, 4, 8, 16, 32, 64,128
(see SCR[2:0] bits)
All these bits are in the SCIBRR register.
Example: If f
is 8 MHz (normal mode) and if PR = 13 and TR = RR = 1, the transmit and
CPU
receive baud rates are 38400 baud.
Note:
The baud rate registers MUST NOT be changed while the transmitter or the receiver is
enabled.
Extended baud rate generation
The extended prescaler option gives a very fine tuning on the baud rate, using a 255 value
prescaler, whereas the conventional Baud Rate Generator retains industry standard
software compatibility.
The extended baud rate generator block diagram is shown in Figure 65.
The output clock rate sent to the transmitter or to the receiver is the output from the 16
divider divided by a factor ranging from 1 to 255 set in the SCIERPR or the SCIETPR
register.
Note:
The extended prescaler is activated by setting the SCIETPR or SCIERPR register to a value
other than zero. The baud rates are calculated as follows:
fCPU
16*ERPR*(PR*RR)
fCPU
16*ETPR*(PR*TR)
Rx =
Tx =
with:
ETPR = 1, ..., 255 (see SCIETPR register)
ERPR = 1, ..., 255 (see SCIERPR register)
Receiver muting and wakeup feature
In multiprocessor configurations, it is often desirable that only the intended message
recipient should actively receive the full message contents, thus reducing redundant SCI
service overhead for all non addressed receivers.
The non-addressed devices may be placed in sleep mode by means of the muting function.
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Setting the RWU bit by software puts the SCI in sleep mode:
■
■
None of the reception status bits can be set.
All the receive interrupts are inhibited.
A muted receiver can be woken up in one of the following two ways:
■
■
by Idle Line detection if the WAKE bit is reset,
by Address Mark detection if the WAKE bit is set.
A receiver wakes-up by Idle Line detection when the Receive line has recognized an Idle
Frame. Then the RWU bit is reset by hardware but the IDLE bit is not set.
A receiver wakes up by Address Mark detection when it received a “1” as the most
significant bit of a word, thus indicating that the message is an address. The reception of
this particular word wakes up the receiver, resets the RWU bit and sets the RDRF bit, which
allows the receiver to receive this word normally and to use it as an address word.
Parity control
Parity control (generation of parity bit in transmission and parity checking in reception) can
be enabled by setting the PCE bit in the SCICR1 register. Depending on the frame length
defined by the M bit, the possible SCI frame formats are as listed in Table 56.
Table 56. Frame formats
M bit
PCE bit
SCI frame(1)
0
1
0
1
| SB | 8 bit data | STB |
0
1
| SB | 7-bit data | PB | STB |
| SB | 9-bit data | STB |
| SB | 8-bit data PB | STB |
1. SB: Start Bit, STB: Stop Bit, PB: Parity Bit.
Note:
In case of wakeup by an address mark, the MSB bit of the data is taken into account and not
the parity bit
Even parity: The parity bit is calculated to obtain an even number of “1s” inside the frame
made of the 7 or 8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit.
Example: data = 00110101; 4 bits set => parity bit is 0 if even parity is selected (PS bit = 0).
Odd parity: The parity bit is calculated to obtain an odd number of “1s” inside the frame
made of the 7 or 8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit.
Example: data = 00110101; 4 bits set => parity bit is 1 if odd parity is selected (PS bit = 1).
Transmission mode: If the PCE bit is set, then the MSB bit of the data written in the data
register is not transmitted but is changed by the parity bit.
Reception mode: If the PCE bit is set, then the interface checks if the received data byte
has an even number of “1s” if even parity is selected (PS = 0) or an odd number of “1s” if
odd parity is selected (PS = 1). If the parity check fails, the PE flag is set in the SCISR
register and an interrupt is generated if PIE is set in the SCICR1 register.
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SCI clock tolerance
During reception, each bit is sampled 16 times. The majority of the 8th, 9th and 10th
samples is considered as the bit value. For a valid bit detection, all the three samples should
have the same value otherwise the noise flag (NF) is set. For example: if the 8th, 9th and
10th samples are 0, 1 and 1 respectively, then the bit value is “1”, but the Noise Flag bit is
set because the three samples values are not the same.
Consequently, the bit length must be long enough so that the 8th, 9th and 10th samples
have the desired bit value. This means the clock frequency should not vary more than 6/16
(37.5%) within one bit. The sampling clock is resynchronized at each start bit, so that when
receiving 10 bits (one start bit, 1 data byte, 1 stop bit), the clock deviation must not exceed
3.75%.
Note:
The internal sampling clock of the microcontroller samples the pin value on every falling
edge. Therefore, the internal sampling clock and the time the application expects the
sampling to take place may be out of sync. For example: If the baud rate is 15.625 kbaud (bit
length is 64 µs), then the 8th, 9th and 10th samples will be at 28 µs, 32 µs and 36 µs
respectively (the first sample starting ideally at 0 µs). But if the falling edge of the internal
clock occurs just before the pin value changes, the samples would then be out of sync by
~4 µs. This means the entire bit length must be at least 40 µs (36 µs for the 10th sample
+ 4 µs for synchronization with the internal sampling clock).
Clock deviation causes
The causes which contribute to the total deviation are:
■
D
: Deviation due to transmitter error (Local oscillator error of the transmitter or the
TRA
transmitter is transmitting at a different baud rate).
■
■
D
D
: Error due to the baud rate quantization of the receiver.
QUANT
: Deviation of the local oscillator of the receiver: This deviation can occur during
REC
the reception of one complete SCI message assuming that the deviation has been
compensated at the beginning of the message.
■
D
: Deviation due to the transmission line (generally due to the transceivers)
TCL
All the deviations of the system should be added and compared to the SCI clock tolerance:
+ D + D + D < 3.75%
D
TRA
QUANT
REC
TCL
Noise error causes
See also description of noise error in Receiver.
■
Start bit: the noise flag (NF) is set during start bit reception if one of the following
conditions occurs:
–
A valid falling edge is not detected. A falling edge is considered to be valid if the
three consecutive samples before the falling edge occurs are detected as '1' and,
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after the falling edge occurs, during the sampling of the 16 samples, if one of the
samples numbered 3, 5 or 7 is detected as a “1”.
–
During sampling of the 16 samples, if one of the samples numbered 8, 9 or 10 is
detected as a “1”.
■
■
Therefore, a valid Start bit must satisfy both the above conditions to prevent the Noise
Flag getting set.
Data bits: the noise flag (NF) is set during normal data bit reception if the following
condition occurs:
–
During the sampling of 16 samples, if all three samples numbered 8, 9 and 10 are
not the same. The majority of the 8th, 9th and 10th samples is considered as the
bit value.
Therefore, a valid Data bit must have samples 8, 9 and 10 at the same value to prevent the
Noise Flag getting set.
Figure 66. Bit sampling in reception mode
RDI LINE
sampled values
Sample
clock
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
6/16
7/16
7/16
One bit time
11.5.5
Low-power modes
Table 57. Mode description
Mode
Description
No effect on SCI.
Wait
SCI interrupts cause the device to exit from Wait mode.
SCI registers are frozen.
Halt
In Halt mode, the SCI stops transmitting/receiving until Halt mode is exited.
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11.5.6
Interrupts
Table 58. Interrupt events
Interrupt event
Enable control
bit
Exit from
Wait
Exit from
Halt
Event flag
TDRE
Transmit data register empty
Transmission complete
Received data ready to be read
Overrun error detected
Idle line detected
TIE
TC
TCIE
RDRF
OR
RIE
Yes
No
IDLE
PE
ILIE
PIE
Parity error
The SCI interrupt events are connected to the same interrupt vector.
These events generate an interrupt if the corresponding Enable Control Bit is set and the
interrupt mask in the CC register is reset (RIM instruction).
11.5.7
Register description
Status register (SCISR)
Reset value: 1100 0000 (C0h)
7
0
TDRE
TC
RDRF
IDLE
Read-only
Bit 7 = TDRE Transmit data register empty.
OR
NF
FE
PE
This bit is set by hardware when the content of the TDR register has been transferred
into the shift register. An interrupt is generated if the TIE bit = 1 in the SCICR2 register.
It is cleared by a software sequence (an access to the SCISR register followed by a
write to the SCIDR register).
0: Data is not transferred to the shift register
1: Data is transferred to the shift register
Note:
Data is not transferred to the shift register until the TDRE bit is cleared.
Bit 6 = TC Transmission complete.
This bit is set by hardware when transmission of a frame containing Data is complete.
An interrupt is generated if TCIE = 1 in the SCICR2 register. It is cleared by a software
sequence (an access to the SCISR register followed by a write to the SCIDR register).
0: Transmission is not complete
1: Transmission is complete
Note:
TC is not set after the transmission of a Preamble or a Break.
Bit 5 = RDRF Received data ready flag.
This bit is set by hardware when the content of the RDR register has been transferred
to the SCIDR register. An interrupt is generated if RIE = 1 in the SCICR2 register. It is
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cleared by a software sequence (an access to the SCISR register followed by a read to
the SCIDR register).
0: Data is not received
1: Received data is ready to be read
Bit 4 = IDLE Idle line detect.
This bit is set by hardware when an Idle Line is detected. An interrupt is generated if
the ILIE = 1 in the SCICR2 register. It is cleared by a software sequence (an access to
the SCISR register followed by a read to the SCIDR register).
0: No Idle Line is detected
1: Idle Line is detected
Note:
The IDLE bit is not set again until the RDRF bit has been set itself (that is, a new idle line
occurs).
Bit 3 = OR Overrun error.
This bit is set by hardware when the word currently being received in the shift register is
ready to be transferred into the RDR register while RDRF = 1. An interrupt is generated
if RIE = 1 in the SCICR2 register. It is cleared by a software sequence (an access to
the SCISR register followed by a read to the SCIDR register).
0: No Overrun error
1: Overrun error is detected
Note:
When this bit is set, the RDR register content is not lost but the shift register is overwritten.
Bit 2 = NF Noise flag.
This bit is set by hardware when noise is detected on a received frame. It is cleared by
a software sequence (an access to the SCISR register followed by a read to the SCIDR
register).
0: No noise is detected
1: Noise is detected
Note:
This bit does not generate interrupt as it appears at the same time as the RDRF bit which
itself generates an interrupt.
Bit 1 = FE Framing error.
This bit is set by hardware when a desynchronization, excessive noise or a break
character is detected. It is cleared by a software sequence (an access to the SCISR
register followed by a read to the SCIDR register).
0: No Framing error is detected
1: Framing error or break character is detected
Note:
This bit does not generate an interrupt as it appears at the same time as the RDRF bit which
itself generates an interrupt. If the word currently being transferred causes both frame error
and overrun error, it is transferred and only the OR bit is set.
Bit 0 = PE Parity error.
This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by
a software sequence (a read to the status register followed by an access to the SCIDR
data register). An interrupt is generated if PIE = 1 in the SCICR1 register.
0: No parity error
1: Parity error
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Control register 1 (SCICR1)
Reset value: x000 0000 (x0h)
7
0
R8
T8
SCID
M
WAKE
PCE
PS
PIE
Read/Write
Bit 7 = R8 Receive data bit 8.
This bit is used to store the 9th bit of the received word when M = 1.
Bit 6 = T8 Transmit data bit 8.
This bit is used to store the 9th bit of the transmitted word when M = 1.
Bit 5 = SCID Disabled for low power consumption
When this bit is set the SCI prescalers and outputs are stopped and the end of the
current byte transfer in order to reduce power consumption.This bit is set and cleared
by software.
0: SCI enabled
1: SCI prescaler and outputs disabled
Bit 4 = M Word length.
This bit determines the word length. It is set or cleared by software.
0: 1 Start bit, 8 Data bits, 1 Stop bit
1: 1 Start bit, 9 Data bits, 1 Stop bit
Note:
The M bit must not be modified during a data transfer (both transmission and reception).
Bit 3 = WAKE Wakeup method.
This bit determines the SCI Wake-Up method, it is set or cleared by software.
0: Idle Line
1: Address Mark
Bit 2 = PCE Parity control enable.
This bit selects the hardware parity control (generation and detection). When the parity
control is enabled, the computed parity is inserted at the MSB position (9th bit if M = 1;
8th bit if M = 0) and parity is checked on the received data. This bit is set and cleared
by software. Once it is set, PCE is active after the current byte (in reception and in
transmission).
0: Parity control disabled
1: Parity control enabled
Bit 1 = PS Parity selection.
This bit selects the odd or even parity when the parity generation/detection is enabled
(PCE bit set). It is set and cleared by software. The parity is selected after the current
byte.
0: Even parity
1: Odd parity
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Bit 0 = PIE Parity interrupt enable.
This bit enables the interrupt capability of the hardware parity control when a parity
error is detected (PE bit set). It is set and cleared by software.
0: Parity error interrupt disabled
1: Parity error interrupt enabled
Control register 2 (SCICR2)
Reset value: 0000 0000 (00h)
7
0
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
Read/Write
Bit 7 = TIE Transmitter interrupt enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever TDRE = 1 in the SCISR register
Bit 6 = TCIE Transmission complete interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever TC = 1 in the SCISR register
Bit 5 = RIE Receiver interrupt enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever OR = 1 or RDRF = 1 in the SCISR register
Bit 4 = ILIE Idle line interrupt enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever IDLE = 1 in the SCISR register.
Bit 3 = TE Transmitter enable.
This bit enables the transmitter. It is set and cleared by software.
0: Transmitter is disabled
1: Transmitter is enabled
Note:
During transmission, a “0” pulse on the TE bit (“0” followed by “1”) sends a preamble (idle
line) after the current word.
When TE is set there is a 1 bit-time delay before the transmission starts.
Bit 2 = RE Receiver enable.
This bit enables the receiver. It is set and cleared by software.
0: Receiver is disabled
1: Receiver is enabled and begins searching for a start bit
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Bit 1 = RWU Receiver wake-up.
This bit determines if the SCI is in mute mode or not. It is set and cleared by software
and can be cleared by hardware when a wake-up sequence is recognized.
0: Receiver in active mode
1: Receiver in mute mode
Note:
Before selecting Mute mode (by setting the RWU bit), the SCI must first receive a data byte;
otherwise, it cannot function in Mute mode with wake-up by Idle line detection.
In Address Mark Detection Wake-Up configuration (WAKE bit = 1), the RWU bit cannot be
modified by software while the RDRF bit is set.
Bit 0 = SBK Send break.
This bit set is used to send break characters. It is set and cleared by software.
0: No break character is transmitted
1: Break characters are transmitted
Note:
If the SBK bit is set to “1” and then to “0”, the transmitter sends a BREAK word at the end of
the current word.
Data register (SCIDR)
Reset value: Undefined
Contains the Received or Transmitted data character, depending on whether it is read from
or written to.
7
0
DR7
DR6
DR5
DR4
DR3
DR2
DR1
DR0
Read/Write
The Data register performs a double function (read and write) since it is composed of two
registers, one for transmission (TDR) and one for reception (RDR).
The TDR register provides the parallel interface between the internal bus and the output
shift register (see Figure 63).
The RDR register provides the parallel interface between the input shift register and the
internal bus (see Figure 63).
Baud rate register (SCIBRR)
Reset value: 0000 0000 (00h)
7
0
SCP1
SCP0
SCT2
SCT1
SCT0
SCR2
SCR1
SCR0
Read/Write
Bits 7:6 = SCP[1:0] First SCI Prescaler
These 2 prescaling bits allow several standard clock division ranges as shown in Figure 59.
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SCP0
Table 59. SCP[1:0] configuration
PR prescaling factor
SCP1
1
3
0
1
0
1
0
4
1
13
Bits 5:3 = SCT[2:0] SCI Transmitter rate divisor
These 3 bits, in conjunction with the SCP1 and SCP0 bits, define the total division
applied to the bus clock to yield the transmit rate clock in conventional baud rate
Generator mode.
Table 60. SCT[2:0] configuration
TR dividing factor
SCT2
SCT1
SCT0
1
2
0
1
0
1
0
1
0
1
0
0
4
1
0
1
8
16
32
64
128
1
Note:
This TR factor is used only when the ETPR fine tuning factor is equal to 00h; otherwise, TR
is replaced by the (TR*ETPR) dividing factor.
Bits 2:0 = SCR[2:0] SCI Receiver rate divisor.
These 3 bits, in conjunction with the SCP1 and SCP0 bits, define the total division
applied to the bus clock to yield the receive rate clock in conventional Baud Rate
Generator mode.
Table 61. SCR[2:0] configuration
RR dividing factor
SCR2
SCR1
SCR0
1
2
0
1
0
1
0
1
0
1
0
0
4
1
0
1
8
16
32
64
128
1
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On-chip peripherals
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Note:
This RR factor is used only when the ERPR fine tuning factor is equal to 00h; otherwise, RR
is replaced by the (RR*ERPR) dividing factor.
Extended receive prescaler division register (SCIERPR)
Reset value: 0000 0000 (00h)
7
0
ERPR7
ERPR6
ERPR5
ERPR4
Read/Write
Bits 7:0 = ERPR[7:0] 8-bit Extended Receive Prescaler Register.
ERPR3
ERPR2
ERPR1
ERPR0
The extended Baud Rate Generator is activated when a value other than 00h is stored
in this register. The clock frequency from the 16 divider (see Figure 65) is divided by the
binary factor set in the SCIERPR register (in the range 1 to 255).
The extended baud rate generator is not active after a reset.
Extended transmit prescaler division register (SCIETPR)
Reset value:0000 0000 (00h)
7
0
ETPR7
ETPR6
ETPR5
ETPR4
Read/Write
Bits 7:0 = ETPR[7:0] 8-bit extended transmit prescaler register.
ETPR3
ETPR2
ETPR1
ETPR0
The extended Baud Rate Generator is activated when a value other than 00h is stored
in this register. The clock frequency from the 16 divider (see Figure 65) is divided by the
binary factor set in the SCIETPR register (in the range 1 to 255).
The extended baud rate generator is not active after a reset.
Table 62. Baud rate selection
Conditions
Accuracy
Baud
Rate
Symbol
Parameter
Standard
Unit
fCPU
vs.
Prescaler
Standard
Conventional Mode
TR (or RR) = 128,
300
1200
2400
4800
9600
10400
19200
38400
~300.48
~1201.92
~2403.84
~4807.69
~9615.38
~10416.67
~19230.77
~38461.54
PR = 13
TR (or RR) = 32, PR = 13
TR (or RR) = 16, PR =13
TR (or RR) = 8, PR = 13
TR (or RR) = 4, PR = 13
TR (or RR) = 16, PR = 3
TR (or RR) = 2, PR = 13
TR (or RR) = 1, PR = 13
~0.16%
~0.79%
fTx
fRx
Communication
frequency
8 MHz
Hz
Extended Mode
ETPR (or ERPR) = 35,
TR (or RR) = 1, PR = 1
14400
~14285.71
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On-chip peripherals
Table 63. SCI register map and reset values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
SCISR
Reset value
TDRE
1
TC
1
RDRF
0
IDLE
0
OR
0
NF
0
FE
0
PE
0
0050h
0051h
0052h
0053h
0054h
0056h
0057h
SCIDR
Reset value
MSB
x
LSB
x
x
x
x
x
x
x
SCIBRR
Reset value
SCP1
0
SCP0
0
SCT2
0
SCT1
0
SCT0
0
SCR2
0
SCR1
0
SCR0
0
SCICR1
Reset value
R8
x
T8
0
SCID
0
M
0
WAKE
0
PCE
0
PS
0
PIE
0
SCICR2
Reset value
TIE
0
TCIE
0
RIE
0
ILIE
0
TE
0
RE
0
RWU
0
SBK
0
SCIERPR
Reset value
MSB
0
LSB
0
0
0
0
0
0
0
0
0
0
0
0
0
SCIPETPR
Reset value
MSB
0
LSB
0
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11.6
I2C bus interface (I2C)
11.6.1
Introduction
2
2
The I C bus interface serves as an interface between the microcontroller and the serial I C
2
bus. It provides both multimaster and slave functions, and controls all I C bus-specific
sequencing, protocol, arbitration and timing. It supports fast I C mode (400 kHz).
2
11.6.2
Main features
2
■
■
■
■
■
■
Parallel-bus/I C protocol converter
Multi-master capability
7-bit/10-bit Addressing
Transmitter/Receiver flag
End-of-byte transmission flag
Transfer problem detection
I2C master features
■
■
■
■
■
■
■
Clock generation
2
I C bus busy flag
Arbitration lost flag
End of byte transmission flag
Transmitter/receiver flag
Start bit detection flag
Start and Stop generation
I2C slave features
■
■
■
■
■
■
■
Stop bit detection
2
I C bus busy flag
Detection of misplaced start or stop condition
2
Programmable I C address detection
Transfer problem detection
End-of-byte transmission flag
Transmitter/receiver flag
11.6.3
General description
In addition to receiving and transmitting data, this interface converts it from serial to parallel
format and vice versa, using either an interrupt or polled handshake. The interrupts are
2
enabled or disabled by software. The interface is connected to the I C bus by a data pin
2
(SDAI) and by a clock pin (SCLI). It can be connected both with a standard I C bus and a
2
Fast I C bus. This selection is made by software.
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Mode selection
The interface can operate in the four following modes:
■
■
Slave transmitter/receiver
Master transmitter/receiver
By default, it operates in slave mode.
The interface automatically switches from slave to master after it generates a START
condition, and from master to slave in case of an arbitration loss or a STOP generation,
allowing then Multi-Master capability.
Communication flow
In Master mode, it initiates a data transfer and generates the clock signal. A serial data
transfer always begins with a start condition and ends with a stop condition. Both start and
stop conditions are generated in master mode by software.
In Slave mode, the interface is capable of recognizing its own address (7 or 10-bit), and the
General Call address. The General Call address detection may be enabled or disabled by
software.
Data and addresses are transferred as 8-bit bytes, MSB first. The first byte(s) following the
start condition contain the address (one in 7-bit mode, two in 10-bit mode). The address is
always transmitted in Master mode.
A 9th clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver must
send an acknowledge bit to the transmitter. Refer to Figure 67.
2
Figure 67. I C bus protocol
SDA
ACK
9
MSB
1
SCL
2
8
Stop
Condition
Start
Condition
Acknowledge may be enabled and disabled by software.
2
The I C interface address and/or general call address can be selected by software.
2
The speed of the I C interface may be selected between Standard (up to 100 kHz) and Fast
2
I C (up to 400 kHz).
SDA/SCL line control
■
Transmitter mode: the interface holds the clock line low before transmission to wait for
the microcontroller to write the byte in the Data Register.
■
Receiver mode: the interface holds the clock line low after reception to wait for the
microcontroller to read the byte in the Data Register.
The SCL frequency (f
the I C bus mode.
) is controlled by a programmable clock divider which depends on
SCL
2
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2
When the I C cell is enabled, the SDA and SCL ports must be configured as floating inputs.
In this case, the value of the external pull-up resistor used depends on the application.
2
When the I C cell is disabled, the SDA and SCL ports revert to being standard I/O port pins.
2
Figure 68. I C interface block diagram
Data register (DR)
Data control
SDA or SDAI
Data shift register
Comparator
Own address register 1 (OAR1)
Own address register 2 (OAR2)
Clock control
SCL or SCLI
Clock control register (CCR)
Control register (CR)
Status register 1 (SR1)
Status register 2 (SR2)
Control logic
Interrupt
11.6.4
Functional description
Refer to the CR, SR1 and SR2 registers in Section 11.6.7. for the bit definitions.
2
By default the I C interface operates in Slave mode (M/SL bit is cleared) except when it
initiates a transmit or receive sequence.
First the interface frequency must be configured using the FRi bits in the OAR2 register.
Slave mode
As soon as a start condition is detected, the address is received from the SDA line and sent
to the shift register; then it is compared with the address of the interface or the General Call
address (if selected by software).
Note:
In 10-bit addressing mode, the comparison includes the header sequence (11110xx0) and
the two most significant bits of the address.
Header matched (10-bit mode only): the interface generates an acknowledge pulse if the
ACK bit is set.
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Address not matched: the interface ignores it and waits for another Start condition.
Address matched: the interface generates in sequence:
■
■
Acknowledge pulse if the ACK bit is set.
EVF and ADSL bits are set with an interrupt if the ITE bit is set.
Then the interface waits for a read of the SR1 register, holding the SCL line low (see
Figure 69 Transfer sequencing EV1).
Next, in 7-bit mode read the DR register to determine from the least significant bit (Data
Direction Bit) if the slave must enter Receiver or Transmitter mode.
In 10-bit mode, after receiving the address sequence the slave is always in receive mode. It
will enter transmit mode on receiving a repeated Start condition followed by the header
sequence with matching address bits and the least significant bit set (11110xx1).
Slave receiver
Following the address reception and after SR1 register has been read, the slave receives
bytes from the SDA line into the DR register via the internal shift register. After each byte the
interface generates in sequence:
■
■
Acknowledge pulse if the ACK bit is set
EVF and BTF bits are set with an interrupt if the ITE bit is set.
Then the interface waits for a read of the SR1 register followed by a read of the DR register,
holding the SCL line low (see Figure 69 Transfer sequencing EV2).
Slave transmitter
Following the address reception and after SR1 register has been read, the slave sends
bytes from the DR register to the SDA line via the internal shift register.
The slave waits for a read of the SR1 register followed by a write in the DR register, holding
the SCL line low (see Figure 69 Transfer sequencing EV3).
When the acknowledge pulse is received:
■
The EVF and BTF bits are set by hardware with an interrupt if the ITE bit is set.
Closing slave communication
After the last data byte is transferred a Stop Condition is generated by the master. The
interface detects this condition and sets:
■
EVF and STOPF bits with an interrupt if the ITE bit is set.
Then the interface waits for a read of the SR2 register (see Figure 69 Transfer sequencing
EV4).
Error cases
■
■
BERR: Detection of a Stop or a Start condition during a byte transfer. In this case, the
EVF and the BERR bits are set with an interrupt if the ITE bit is set.
If it is a Stop, then the interface discards the data, released the lines and waits for
another Start condition.
If it is a Start, then the interface discards the data and waits for the next slave address
on the bus.
AF: Detection of a non-acknowledge bit. In this case, the EVF and AF bits are set with
an interrupt if the ITE bit is set.
The AF bit is cleared by reading the I2CSR2 register. However, if read before the
completion of the transmission, the AF flag will be set again, thus possibly generating a
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new interrupt. Software must ensure either that the SCL line is back at 0 before reading
the SR2 register, or be able to correctly handle a second interrupt during the 9th pulse
of a transmitted byte.
Note:
In both cases, SCL line is not held low; however, the SDA line can remain low if the last bits
transmitted are all 0. It is then necessary to release both lines by software. The SCL line is
not held low while AF=1 but by other flags (SB or BTF) that are set at the same time.
How to release the SDA / SCL lines
Set and subsequently clear the STOP bit while BTF is set. The SDA/SCL lines are released
after the transfer of the current byte.
SMBus compatibility
2
ST7 I C is compatible with SMBus V1.1 protocol. It supports all SMBus addressing modes,
SMBus bus protocols and CRC-8 packet error checking. Refer to AN1713: SMBus Slave
2
Driver For ST7 I C Peripheral.
Master mode
To switch from default Slave mode to Master mode a Start condition generation is needed.
Start condition
Setting the START bit while the BUSY bit is cleared causes the interface to switch to Master
mode (M/SL bit set) and generates a Start condition.
Once the Start condition is sent:
■
The EVF and SB bits are set by hardware with an interrupt if the ITE bit is set.
Then the master waits for a read of the SR1 register followed by a write in the DR register
with the Slave address, holding the SCL line low (see Figure 69 Transfer sequencing
EV5).
Slave address transmission
Then the slave address is sent to the SDA line via the internal shift register.
In 7-bit addressing mode, one address byte is sent.
In 10-bit addressing mode, sending the first byte including the header sequence causes the
following event:
■
The EVF bit is set by hardware with interrupt generation if the ITE bit is set.
Then the master waits for a read of the SR1 register followed by a write in the DR register,
holding the SCL line low (see Figure 69 Transfer sequencing EV9).
Then the second address byte is sent by the interface.
After completion of this transfer (and acknowledge from the slave if the ACK bit is set):
■
The EVF bit is set by hardware with interrupt generation if the ITE bit is set.
Then the master waits for a read of the SR1 register followed by a write in the CR register
(for example set PE bit), holding the SCL line low (see Figure 69 Transfer sequencing
EV6).
Next the master must enter Receiver or Transmitter mode.
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Note:
In 10-bit addressing mode, to switch the master to Receiver mode, the software must
generate a repeated Start condition and resend the header sequence with the least
significant bit set (11110xx1).
Master receiver
Following the address transmission and after SR1 and CR registers have been accessed,
the master receives bytes from the SDA line into the DR register via the internal shift
register. After each byte the interface generates in sequence:
■
■
Acknowledge pulse if the ACK bit is set
EVF and BTF bits are set by hardware with an interrupt if the ITE bit is set.
Then the interface waits for a read of the SR1 register followed by a read of the DR register,
holding the SCL line low (see Figure 69 Transfer sequencing EV7).
To close the communication: before reading the last byte from the DR register, set the STOP
bit to generate the Stop condition. The interface goes automatically back to slave mode
(M/SL bit cleared).
Note:
In order to generate the non-acknowledge pulse after the last received data byte, the ACK
bit must be cleared just before reading the second last data byte.
Master transmitter
Following the address transmission and after SR1 register has been read, the master sends
bytes from the DR register to the SDA line via the internal shift register.
The master waits for a read of the SR1 register followed by a write in the DR register,
holding the SCL line low (see Figure 69 Transfer sequencing EV8).
When the acknowledge bit is received, the interface sets:
■
EVF and BTF bits with an interrupt if the ITE bit is set.
To close the communication: after writing the last byte to the DR register, set the STOP bit to
generate the Stop condition. The interface goes automatically back to slave mode (M/SL bit
cleared).
Error cases
■
BERR: Detection of a Stop or a Start condition during a byte transfer. In this case, the
EVF and BERR bits are set by hardware with an interrupt if ITE is set.
Note that BERR will not be set if an error is detected during the first pulse of each 9-bit
transaction:
Single Master Mode
If a Start or Stop is issued during the first pulse of a 9-bit transaction, the BERR flag will
not be set and transfer will continue however the BUSY flag will be reset. To work
around this, slave devices should issue a NACK when they receive a misplaced Start or
Stop. The reception of a NACK or BUSY by the master in the middle of communication
gives the possibility to re-initiate transmission.
Multimaster Mode
Normally the BERR bit would be set whenever unauthorized transmission takes place
while transfer is already in progress. However, an issue will arise if an external master
2
generates an unauthorized Start or Stop while the I C master is on the first pulse of a
2
9-bit transaction. It is possible to work around this by polling the BUSY bit during I C
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master mode transmission. The resetting of the BUSY bit can then be handled in a
similar manner as the BERR flag being set.
■
AF: Detection of a non-acknowledge bit. In this case, the EVF and AF bits are set by
hardware with an interrupt if the ITE bit is set. To resume, set the Start or Stop bit.
The AF bit is cleared by reading the I2CSR2 register. However, if read before the
completion of the transmission, the AF flag will be set again, thus possibly generating a
new interrupt. Software must ensure either that the SCL line is back at 0 before reading
the SR2 register, or be able to correctly handle a second interrupt during the 9th pulse
of a transmitted byte.
■
ARLO: Detection of an arbitration lost condition.
In this case the ARLO bit is set by hardware (with an interrupt if the ITE bit is set and
the interface goes automatically back to slave mode (the M/SL bit is cleared).
Note:
In all these cases, the SCL line is not held low; however, the SDA line can remain low if the
last bits transmitted are all 0. It is then necessary to release both lines by software. The SCL
line is not held low while AF=1 but by other flags (SB or BTF) that are set at the same time.
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Figure 69. Transfer sequencing
7-bit Slave receiver:
S Address A Data1 A
Data2 A
DataN A
P
.....
EV1
EV2
EV2
EV2
EV4
7-bit Slave transmitter:
S Address A
EV1 EV3
Data1 A
Data2 A
Data2 A
DataN NA
DataN NA
P
.....
.....
EV3
EV3
EV7
EV3-1
EV4
7-bit Master receiver:
S
Address A
Data1 A
P
EV5
EV6
EV7
EV7
7-bit Master transmitter:
Address A
S
Data1 A
Data2 A
DataN A
P
.....
EV5
EV6 EV8
EV8
EV2
EV8
EV8
10-bit Slave receiver:
S Header A Address A
Data1 A
DataN A
P
.....
EV1
EV2
EV4
10-bit Slave transmitter:
Sr Header A
Data1 A
DataN A
P
.....
EV1 EV3
EV3
EV3-1
P
EV4
10-bit Master transmitter
Header A Address A
S
Data1 A
DataN A
.....
EV5
EV9
EV6 EV8
EV8
EV8
10-bit Master receiver:
Sr
Header A
Data1
A
DataN
A
P
.....
EV5
EV6
EV7
EV7
Legend: S = Start, S = Repeated Start, P = Stop, A = Acknowledge, NA = Non-
r
acknowledge, EVx = Event (with interrupt if ITE=1)
EV1: EVF=1, ADSL=1, cleared by reading SR1 register.
EV2: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register.
EV3: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register.
EV3-1: EVF=1, AF=1, BTF=1; AF is cleared by reading SR1 register. BTF is cleared by
releasing the lines (STOP=1, STOP=0) or by writing DR register (DR=FFh).
Note:
If lines are released by STOP=1, STOP=0, the subsequent EV4 is not seen.
EV4: EVF=1, STOPF=1, cleared by reading SR2 register.
EV5: EVF=1, SB=1, cleared by reading SR1 register followed by writing DR register.
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EV6: EVF=1, cleared by reading SR1 register followed by writing CR register (for example
PE=1).
EV7: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register.
EV8: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register.
EV9: EVF=1, ADD10=1, cleared by reading SR1 register followed by writing DR register.
11.6.5
Low-power modes
Table 64. Mode description
Mode
Description
No effect on I2C interface.
Wait
I2C interrupts cause the device to exit from Wait mode.
I2C registers are frozen.
In HALT mode, the I2C interface is inactive and does not acknowledge data on the bus.
The I2C interface resumes operation when the MCU is woken up by an interrupt with “exit
from HALT mode” capability.
Halt
11.6.6
Interrupts
Figure 70. Event flags and interrupt generation
ADD10
ITE
BTF
ADSL
SB
Interrupt
EVF
AF
STOPF
ARLO
BERR
*
* EVF can also be set by EV6 or an error from the SR2 register.
(1)
Table 65. Interrupt events
Enable
control bit
Exit from Exit from
Interrupt event
Event flag
Wait
Halt
10-bit address sent event (Master mode)
End of byte transfer event
ADD10
BTF
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
No
Address matched event (Slave mode)
Start bit generation event (Master mode)
Acknowledge failure event
ADSL
SB
ITE
AF
Stop detection event (Slave mode)
Arbitration lost event (Multimaster configuration)
Bus error event
STOPF
ARLO
BERR
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1. The I2C interrupt events are connected to the same interrupt vector (see Section 8: Interrupts). They
generate an interrupt if the corresponding Enable Control Bit is set and the I-bit in the CC register is reset
(RIM instruction).
11.6.7
Register description
I2C control register (CR)
Reset value: 0000 0000 (00h)
7
0
0
0
PE
ENGC
START
ACK
STOP
ITE
Read / Write
Bits 7:6 = Reserved. Forced to 0 by hardware.
Bit 5 = PE Peripheral enable.
This bit is set and cleared by software.
0: Peripheral disabled
1: Master/Slave capability
Note:
When PE=0, all the bits of the CR register and the SR register except the Stop bit are reset.
All outputs are released while PE=0
When PE=1, the corresponding I/O pins are selected by hardware as alternate functions.
2
To enable the I C interface, write the CR register TWICE with PE=1 as the first write only
activates the interface (only PE is set).
Bit 4 = ENGC Enable General Call.
This bit is set and cleared by software. It is also cleared by hardware when the interface
is disabled (PE=0). The 00h General Call address is acknowledged (01h ignored).
0: General Call disabled
1: General Call enabled
Note:
In accordance with the I2C standard, when GCAL addressing is enabled, an I2C slave can
only receive data. It will not transmit data to the master.
Bit 3 = START Generation of a Start condition.
This bit is set and cleared by software. It is also cleared by hardware when the interface
is disabled (PE=0) or when the Start condition is sent (with interrupt generation if
ITE=1).
■
■
In master mode:
0: No start generation
1: Repeated start generation
In slave mode:
0: No start generation
1: Start generation when the bus is free
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Bit 2 = ACK Acknowledge enable.
This bit is set and cleared by software. It is also cleared by hardware when the interface
is disabled (PE=0).
0: No acknowledge returned
1: Acknowledge returned after an address byte or a data byte is received
Bit 1 = STOP Generation of a Stop condition.
This bit is set and cleared by software. It is also cleared by hardware in master mode.
Note:
This bit is not cleared when the interface is disabled (PE=0).
■
In master mode:
0: No stop generation
1: Stop generation after the current byte transfer or after the current Start condition is
sent. The STOP bit is cleared by hardware when the Stop condition is sent.
■
In slave mode:
0: No stop generation
1: Release the SCL and SDA lines after the current byte transfer (BTF=1). In this mode
the STOP bit has to be cleared by software.
Bit 0 = ITE Interrupt enable.
This bit is set and cleared by software and cleared by hardware when the interface is
disabled (PE=0).
0: Interrupts disabled
1: Interrupts enabled
Refer to Figure 70 for the relationship between the events and the interrupt.
SCL is held low when the ADD10, SB, BTF or ADSL flags or an EV6 event (See
Figure 69) is detected.
I2C status register 1 (SR1)
Reset value: 0000 0000 (00h)
7
0
EVF
ADD10
TRA
BUSY
BTF
ADSL
M/SL
SB
Read Only
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Bit 7 = EVF Event flag.
This bit is set by hardware as soon as an event occurs. It is cleared by software reading
SR2 register in case of error event or as described in Figure 69. It is also cleared by
hardware when the interface is disabled (PE=0).
0: No event
1: One of the following events has occurred:
BTF=1 (Byte received or transmitted)
■
■
■
■
■
■
■
■
■
ADSL=1 (Address matched in Slave mode while ACK=1)
SB=1 (Start condition generated in Master mode)
AF=1 (No acknowledge received after byte transmission)
STOPF=1 (Stop condition detected in Slave mode)
ARLO=1 (Arbitration lost in Master mode)
BERR=1 (Bus error, misplaced Start or Stop condition detected)
ADD10=1 (Master has sent header byte)
Address byte successfully transmitted in Master mode.
Bit 6 = ADD10 10-bit addressing in Master mode.
This bit is set by hardware when the master has sent the first byte in 10-bit address
mode. It is cleared by software reading SR2 register followed by a write in the DR
register of the second address byte. It is also cleared by hardware when the peripheral
is disabled (PE=0).
0: No ADD10 event occurred.
1: Master has sent first address byte (header)
Bit 5 = TRA Transmitter/Receiver.
When BTF is set, TRA=1 if a data byte has been transmitted. It is cleared automatically
when BTF is cleared. It is also cleared by hardware after detection of Stop condition
(STOPF=1), loss of bus arbitration (ARLO=1) or when the interface is disabled (PE=0).
0: Data byte received (if BTF=1)
1: Data byte transmitted
Bit 4 = BUSY Bus busy.
This bit is set by hardware on detection of a Start condition and cleared by hardware on
detection of a Stop condition. It indicates a communication in progress on the bus. The
BUSY flag of the I2CSR1 register is cleared if a Bus Error occurs.
0: No communication on the bus
1: Communication ongoing on the bus
Bit 3 = BTF Byte transfer finished.
This bit is set by hardware as soon as a byte is correctly received or transmitted with
interrupt generation if ITE=1. It is cleared by software reading SR1 register followed by
a read or write of DR register. It is also cleared by hardware when the interface is
disabled (PE=0).
■
Following a byte transmission, this bit is set after reception of the acknowledge clock
pulse. In case an address byte is sent, this bit is set only after the EV6 event (See
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On-chip peripherals
ST72344xx, ST2345xx
Figure 69). BTF is cleared by reading SR1 register followed by writing the next byte in
DR register.
■
Following a byte reception, this bit is set after transmission of the acknowledge clock
pulse if ACK=1. BTF is cleared by reading SR1 register followed by reading the byte
from DR register.
The SCL line is held low while BTF=1.
0: Byte transfer not done
1: Byte transfer succeeded
Bit 2 = ADSL Address matched (Slave mode).
This bit is set by hardware as soon as the received slave address matched with the
OAR register content or a general call is recognized. An interrupt is generated if ITE=1.
It is cleared by software reading SR1 register or by hardware when the interface is
disabled (PE=0).
The SCL line is held low while ADSL=1.
0: Address mismatched or not received
1: Received address matched
Bit 1 = M/SL Master/Slave.
This bit is set by hardware as soon as the interface is in Master mode (writing
START=1). It is cleared by hardware after detecting a Stop condition on the bus or a
loss of arbitration (ARLO=1). It is also cleared when the interface is disabled (PE=0).
0: Slave mode
1: Master mode
Bit 0 = SB Start bit (Master mode).
This bit is set by hardware as soon as the Start condition is generated (following a write
START=1). An interrupt is generated if ITE=1. It is cleared by software reading SR1
register followed by writing the address byte in DR register. It is also cleared by
hardware when the interface is disabled (PE=0).
0: No Start condition
1: Start condition generated
2
I C status register 2 (SR2)
Reset value: 0000 0000 (00h)
7
0
0
0
0
AF
STOPF
ARLO
BERR
GCAL
Read Only
Bit 7:5 = Reserved.
Forced to 0 by hardware.
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On-chip peripherals
Bit 4 = AF Acknowledge failure.
This bit is set by hardware when no acknowledge is returned. An interrupt is generated
if ITE=1. It is cleared by software reading SR2 register or by hardware when the
interface is disabled (PE=0).
The SCL line is not held low while AF=1 but by other flags (SB or BTF) that are set at
the same time.
0: No acknowledge failure
1: Acknowledge failure
Bit 3 = STOPF Stop detection (Slave mode).
This bit is set by hardware when a Stop condition is detected on the bus after an
acknowledge (if ACK=1). An interrupt is generated if ITE=1. It is cleared by software
reading SR2 register or by hardware when the interface is disabled (PE=0).
The SCL line is not held low while STOPF=1.
0: No Stop condition detected
1: Stop condition detected
Bit 2 = ARLO Arbitration lost.
This bit is set by hardware when the interface loses the arbitration of the bus to another
master. An interrupt is generated if ITE=1. It is cleared by software reading SR2
register or by hardware when the interface is disabled (PE=0).
After an ARLO event the interface switches back automatically to Slave mode
(M/SL=0).
The SCL line is not held low while ARLO=1.
0: No arbitration lost detected
1: Arbitration lost detected
Note:
In a Multimaster environment, when the interface is configured in Master Receive mode it
does not perform arbitration during the reception of the Acknowledge Bit. A mishandling of
the ARLO bit from the I2CSR2 register may occur when a second master simultaneously
2
requests the same data from the same slave, and the I C master does not acknowledge the
data. The ARLO bit is then left at 0 instead of being set.
Bit 1 = BERR Bus error.
This bit is set by hardware when the interface detects a misplaced Start or Stop
condition. An interrupt is generated if ITE=1. It is cleared by software reading SR2
register or by hardware when the interface is disabled (PE=0).
The SCL line is not held low while BERR=1.
0: No misplaced Start or Stop condition
1: Misplaced Start or Stop condition
Note:
If a Bus Error occurs, a Stop or a repeated Start condition should be generated by the
Master to re-synchronize communication, get the transmission acknowledged and the bus
released for further communication
Bit 0 = GCAL General Call (Slave mode).
This bit is set by hardware when a general call address is detected on the bus while
ENGC=1. It is cleared by hardware detecting a Stop condition (STOPF=1) or when the
interface is disabled (PE=0).
0: No general call address detected on the bus
1: General call address detected on the bus
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I2C clock control register (CCR)
Reset value: 0000 0000 (00h)
7
0
FM/SM
CC6
CC5
CC4
CC3
CC2
CC1
CC0
Read / Write
2
Bit 7 = FM/SM Fast/Standard I C mode.
This bit is set and cleared by software. It is not cleared when the interface is disabled
(PE=0).
2
0: Standard I C mode
2
1: Fast I C mode
Bit 6:0 = CC[6:0] 7-bit clock divider.
2
These bits select the speed of the bus (F
) depending on the I C mode. They are not
SCL
cleared when the interface is disabled (PE=0).
Refer to Section 13: Electrical characteristics for the table of values.
Note:
The programmed f
assumes no load on SCL and SDA lines.
SCL
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On-chip peripherals
I2C data register (DR)
Reset value: 0000 0000 (00h)
7
0
D7
D6
D5
D4
D3
D2
D1
D0
Read / Write
Bits 7:0 = D[7:0] 8-bit Data Register.
These bits contain the byte to be received or transmitted on the bus.
■
Transmitter mode: byte transmission start automatically when the software writes in the
DR register.
■
Receiver mode: the first data byte is received automatically in the DR register using the
least significant bit of the address.
Then, the following data bytes are received one by one after reading the DR register.
I2C own address register (OAR1)
Reset value: 0000 0000 (00h)
7
0
ADD7
ADD6
ADD5
ADD4
ADD3
ADD2
ADD1
ADD0
Read / Write
7-bit addressing mode
Bits 7:1 = ADD[7:1] Interface address.
2
These bits define the I C bus address of the interface. They are not cleared when the
interface is disabled (PE=0).
Bit 0 = ADD0 Address direction bit.
This bit is don’t care, the interface acknowledges either 0 or 1. It is not cleared when
the interface is disabled (PE=0).
Note:
Address 01h is always ignored.
10-bit addressing mode
Bit 7:0 = ADD[7:0] Interface address.
2
These are the least significant bits of the I C bus address of the interface. They are not
cleared when the interface is disabled (PE=0).
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I2C own address register (OAR2)
Reset value: 0100 0000 (40h)
7
0
FR1
FR0
0
0
0
ADD9
ADD8
0
Read / Write
Bit 7:6 = FR[1:0] Frequency bits.
These bits are set by software only when the interface is disabled (PE=0). To configure
2
the interface to I C specified delays select the value corresponding to the
microcontroller frequency f
.
CPU
Table 66. FR[1:0] configuration
fCPU
FR1
FR0
< 6 MHz
0
0
0
1
6 to 8 MHz
Bits 5:3 = Reserved
Bits 2:1 = ADD[9:8] Interface address.
2
These are the most significant bits of the I C bus address of the interface (10-bit mode
only). They are not cleared when the interface is disabled (PE=0).
Bit 0 = Reserved.
2
Table 67. I C register map and reset values
Address
(Hex.)
Register
label
7
6
5
4
3
2
1
0
I2CCR
Reset value
PE
0
ENGC
0
START
0
ACK
0
STOP
0
ITE
0
0058h
0059h
005Ah
005Bh
005Ch
005Dh
005Eh
0
0
I2CSR1
Reset value
EVF
0
ADD10
0
TRA
0
BUSY
0
BTF
0
ADSL
0
M/SL
0
SB
0
I2CSR2
Reset value
AF
0
STOPF
0
ARLO
0
BERR
0
GCAL
0
0
0
0
I2CCCR
Reset value
FM/SM
0
CC6
0
CC5
0
CC4
0
CC3
0
CC2
0
CC1
0
CC0
0
I2COAR1
Reset value
ADD7
0
ADD6
0
ADD5
0
ADD4
0
ADD3
0
ADD2
0
ADD1
0
ADD0
0
I2COAR2
Reset value
FR1
0
FR0
1
ADD9
0
ADD8
0
0
0
0
0
0
0
0
I2CDR
Reset value
MSB
0
LSB
0
0
0
0
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On-chip peripherals
11.7
I2C triple slave interface with DMA (I2C3S)
11.7.1
Introduction
2
The I C3S interface provides three I2C slave functions, supporting both standard (up to
2
100 kHz) and fast I C mode (100 to 400 kHz). Special features are provided for:
2
2
■
■
Full-speed emulation of standard I C E PROMs
Receiving commands to perform user-defined operations such as IAP
11.7.2
Main features
■
■
■
■
■
■
■
■
■
■
Three user configurable independent slave addresses can be individually enabled
2x 256 bytes and 1x 128 bytes buffers with fixed addresses in RAM
7-bit addressing
2
DMA transfer to/from I C bus and RAM
Standard (transfers 256 bytes at up to 100 kHz)
Fast mode (transfers 256 bytes at up to 400 kHz)
Transfer error detection and handling
3 interrupt flags per address for maximum flexibility
Two interrupt request lines (one for Slaves 1 and 2, the other for Slave 3)
2
Full emulation of standard I C EEPROMs:
–
–
–
–
Supports 5 read/write commands and combined format
2
No I C clock stretching
Programmable page size (8/16 bytes) or full buffer
Configurable write protection
2
■
Data integrity and byte-pair coherency when reading 16-bit words from I C bus
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2
Figure 71. I C3S interface block diagram
I2C SLAVE ADDRESS 1
I2C SLAVE ADDRESS 2
I2C SLAVE ADDRESS 3
2
DATA E PROM
256 BYTES
RAM
SLAVE 1 BUFFER
256 BYTES
COMPARATOR
8-BIT
SHIFT REGISTER
SDA or SDAI
SLAVE 2 BUFFER
256 BYTES
SCL or SCLI
SLAVE 3 BUFFER
128 BYTES
DMA
SHADOW
REGISTER
CONTROL LOGIC
Slave 1 or 2 Interrupt
Slave 3 Interrupt
CPU
11.7.3
General description
In addition to receiving and transmitting data, I2C3S converts it from serial to parallel format
and vice versa. The interrupts are enabled or disabled by software. The I2C3S is connected
2
to the I C bus by a data pin (SDA) and by a clock pin (SCL). It can be connected both with a
2
2
standard I C bus and a Fast I C bus. The interface operates only in Slave mode as
transmitter/receiver.
2
In order to fully emulate standard I C EEPROM devices with highest transfer speed, the
2
peripheral prevents I C clock signal stretching and performs data transfer between the shift
register and the RAM buffers using DMA.
Communication flow
A serial data transfer normally begins with a start condition and ends with a stop condition.
Both start and stop conditions are generated by an external master. Refer to Figure 67 for
the standard protocol. The I2C3S is not a master and is not capable of generating a
start/stop condition on the SDA line. The I2C3S is capable of recognizing 3 slave addresses
2
which are user programmable. The three I C slave addresses can be individually
enabled/disabled by software.
Since the I2C3S interface always acts as a slave, it does not generate a clock. Data and
addresses are transferred as 8-bit bytes, MSB first. The first byte following the start
condition contains the slave address. A 9th clock pulse follows the 8 clock cycles of a byte
transfer, during which the receiver must send an acknowledge bit to the transmitter.
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On-chip peripherals
SDA/SCL line control
■
When the I2C3S interface is enabled, the SDA and SCL ports must be configured as
floating inputs. In this case, the value of the external pull-up resistor used depends on
the application.
■
When the I2C3S interface is disabled, the SDA and SCL ports revert to being standard
I/O port pins.
2
Figure 72. I C bus protocol
SDA
ACK
9
MSB
1
SCL
2
8
Start
Stop
condition
condition
11.7.4
Functional description
2
The three slave addresses 1, 2 and 3 can be used as general purpose I C slaves. They also
2
support all features of standard I C EEPROMs like the ST M24Cxx family and are able to
fully emulate them.
Slaves 1 and 2 are mapped on the same interrupt vector. Slave 3 has a separate interrupt
vector with higher priority.
The three slave addresses are defined by writing the 7 MSBs of the address in the
I2C3SSAR1, I2C3SSAR2 and I2C3SSAR3 registers. The slaves are enabled by setting the
enable bits in the same registers.
Each slave has its own RAM buffer at a fixed location in the ST7 RAM area.
2
■
Slaves 1 and 2 have 256-byte buffers which can be individually protected from I C
master write accesses.
■
Slave 3 has a 128-byte RAM buffer without write protection feature.
All three slaves have individual read flags (RF) and write flags (WF) with maskable
2
interrupts. These flags are set when the I C master has completed a read or write operation.
Paged operation
2
To allow emulation of Standard I C EEPROM devices, pages can be defined in the RAM
buffer. The pages are configured using the PL[1:0] bits in the I2C3SCR1 register. 8/16-Byte
page length has to be selected depending on the EEPROM device to emulate. The Full
Page option is to be used when no paging of the RAM buffer is required. The configuration is
common to the 3 slave addresses. The Full Page configuration corresponds to 256 bytes for
address 1 and 2 and to 128 bytes for address 3.
Paging affects the handling of rollover when write operations are performed. In case the
bottom of the page is reached, the write continues from the first address of the same page.
Page length does not affect read operations: rollover is done on the whole RAM buffer
whatever the configured page length.
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The Byte count register is reset when it reaches 256 bytes, whatever the page length, for all
slave addresses, including slave 3.
DMA
2
The I C slaves use a DMA controller to write/read data to/from their RAM buffer.
A DMA request is issued to the DMA controller on reception of a byte or just before
transmission of a byte.
When a byte is written by DMA in RAM, the CPU is stalled for max. 2 cycles. When several
bytes are transferred from the I2C bus to RAM, the DMA releases between each byte and
the CPU resumes processing until the DMA writes the next byte.
RAM buffer write protection
By setting the WP1/WP2 bits in the I2C3SCR2 register, it is possible to protect the RAM
buffer of Slaves 1/2 respectively against write access from the master.
If a write operation is attempted, the slave address is acknowledged, the current address
register is overwritten, data is also acknowledged but it is not written to the RAM. Both the
current address and byte count registers are incremented as in normal operation.
In case of write access to a write protected address, no interrupt is generated and the
BusyW bit in the I2C3SCR2 register is not set.
Only write operations are disabled/enabled. Read operations are not affected.
Byte-pair coherency for I2C read operations
2
Byte-pair coherency allows the I C master to read a 16-bit word and ensures that it is not
corrupted by a simultaneous CPU update. Two mechanisms are implemented, covering the
two possible cases:
1. CPU updates a word in RAM after the first byte has been transferred to the I2C shift
register from RAM. In this case, the first byte read from RAM would be the MSB of the
old word and 2nd byte would be the LSB of the new word.
To prevent this corruption, the I2C3S uses DMA to systematically read a 2-byte word
2
when it receives a read command from the I C master. The MSB of the word should be
at address 2n. Using DMA, the MSB is moved from RAM address 2n to the I2C shift
register and the LSB from RAM address 2n+1 moved to a shadow register in the I2C3S
peripheral. The CPU is stalled for a maximum of 2 cycles during word transfer.
In case only one byte is read, the unused content of the shadow register will be
automatically overwritten when a new read operation is performed.
2
In case a second byte is read in the same I C message (no Stop or Restart condition),
the content of the shadow register is transferred to the shift register and transmitted to
the master.
This process continues until a Stop or Restart condition occurs.
2. I2C3S attempts to read a word while the CPU is updating the RAM buffer. To prevent
data corruption, the CPU must switch operation to Word mode prior to updating a word
in the RAM buffer. Word mode is enabled by software using the B/W bit in the
I2C3SCR2 register. In Word mode, when the CPU writes the MSB of a word to address
2n, it is stored in a shadow register rather than being actually written in RAM. When the
CPU writes the second byte (the LSB) at address 2n+1, it is directly written in RAM.
The next cycle after the write to address 2n+1, the MSB is automatically written from
the shadow register to RAM address 2n. DMA is disabled for a 1 cycle while the CPU is
writing a word.
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On-chip peripherals
Word mode is disabled by hardware after the word update is performed. It must be
enabled before each word update by CPU.
Use the following procedure when the ST7 writes a word in RAM:
1. Disable interrupts
2. Enable Word mode by setting the B/W and BusyW bits in the I2C3SCR2 register.
BusyW bit is set to 1 when modifying any bits in Control Register 2. Writing a 1 to this
bit does not actually modify BusyW but prevents accidental clearing of the bit.
3. Write Byte 1 in an even address in RAM. The byte is not actually written in RAM but in
a shadow register. This address must be within the I2C RAM buffer of slave addresses
1, 2 or 3.
4. Write Byte 2 in the next higher address in RAM. This byte is actually written in RAM.
During the next cycle, the shadow register content is written in the lower address. The
DMA request is disabled during this cycle.
5. Byte mode resumes automatically after writing byte 2 and DMA is re-enabled.
6. Enable interrupts
Note:
Word mode does not guarantee byte-pair coherency of words WRITTEN by the I2C master
in RAM and read by the ST7. In this case, byte pair coherency must be handled by software.
Figure 73. 16-bit word write operation flowchart
HOST
ST7 I2C3SNS
ST7 CPU
Sends address
and write bit
Decodes I2C3SNS address
decodes R/W bit
Normal execution
sets write flag
Updates current address-
register
Sends write address
Issues DMA request
Halts execution
N
Word mode?
1 Cycle
max
Y
Repeat
Delays while CPU
completes word write
Sends 1 byte of data
STOP condition
Writes one byte to RAM
Resumes execution
1 Cycle
max
Sets BUSYW in control -
register + I2C3S disabled
issues interrupt
Services I2C3SNS interrupt
Resets I2C3SNS write flag
Enables I2C3SNS
Reads I2C3SNS status register
Updates control register
Byte-Pair Coherency ensured by setting Word Mode
RAM start address depends on slave address
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Figure 74. 16-bit word read operation flowchart
Host
ST7 I2C3SNS
ST7 CPU
Sends address
and read bit
Decodes I2C3SNS address
Decodes R/W bit
Normal execution
Sets read flag
Updates current address-
register
Sends read address
Issues DMA request
Halts execution
N
Word mode?
Y
Delays while CPU
completes word write
3 cycles
max
Repeat
Reads 1 word from RAM
Byte 1 => Shift reg
Resumes execution
Receives byte 1
Byte 2 => Shadow reg
Releases DMA
Y
STOP?
N
Shadow reg => Shift reg
Receives byte 2
Stop condition
Services I2C3SNS interrupt
Updates status + DMA CNTL
Resets read flag
Reads I2C3SNS status register
Byte-Pair Coherency ensured by setting Word Mode + DMA on Words
RAM start address depends on slave address
Application note
Taking full advantage of its higher interrupt priority Slave 3 can be used to allow the
addressing master to send data bytes as commands to the ST7. These commands can be
decoded by the ST7 software to perform various operations such as programming the Data
E2PROM via IAP (In-Application Programming).
Slave 3 writes the command byte and other data in the RAM and generates an interrupt.
The ST7 then decodes the command and processes the data as decoded from the
command byte. The ST7 also writes a status byte in the RAM which the addressing master
can poll.
11.7.5
Address handling
As soon as a start condition is detected, the address is received from the SDA line and sent
to the shift register. Then it is compared with the three addresses of the interface to decode
which slave of the interface is being addressed.
Address not matched: the interface ignores it and waits for another Start condition.
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On-chip peripherals
Address matched: the interface generates in sequence the following:
■
■
An Acknowledge pulse
Depending on the LSB of the slave address sent by the master, slaves enter transmitter
or receiver mode.
■
Send an interrupt to the CPU after completion of the read/write operation after
detecting the Stop/ Restart condition on the SDA line.
Note:
The Status Register has to be read to clear the event flag associated with the interrupt.
An interrupt will be generated only if the interrupt enable bit is set in the Control Register.
Slaves 1 and 2 have a common interrupt and the Slave 3 has a separate interrupt.
At the end of write operation, I2C3S is temporarily disabled by hardware by setting BusyW
bit in CR2. The byte count register, status register and current address register should be
saved before resetting BusyW bit.
Slave reception (write operations)
Byte Write: The Slave address is followed by an 8-bit byte address. Upon receipt of this
address, an acknowledge is generated, the address is moved into the current address
register and the 8-bit data is clocked in. Once the data is shifted in, a DMA request is
generated and the data is written in the RAM. The addressing device will terminate the write
sequence with a stop condition. Refer to Figure 76.
Page Write: A page write is initiated in a similar way to a byte write, but the addressing
device does not send a stop condition after the first data byte. The page length is
programmed using bits 7:6 (PL[1:0]) in the Control Register1.
The current address register value is incremented by one every time a byte is written. When
this address reaches the page boundary, the next byte will be written at the beginning of the
same page. Refer to Figure 77.
Slave transmission (Read operations)
Current address read: The current address register maintains the last address accessed
during the last read or write operation incremented by one.
During this operation the I2C slave reads the data pointed by the current address register.
Refer to Figure 78.
Random read: Random read requires a dummy byte write sequence to load in the byte
address. The addressing device then generates restart condition and resends the device
address similar to current address read with the read/write bit high. Refer to Figure 79.
Some types of I2C masters perform a dummy write with a stop condition and then a current
address read.
In either case, the slave generates a DMA request, sends an acknowledge and serially
clocks out the data.
When the memory address limit is reached, the current address will roll over and the
random read will continue till the addressing master sends a stop condition.
Sequential read: Sequential reads are initiated by either a current address read or a
random address read. After the addressing master receives the data byte, it responds with
an acknowledge. As long as the slave receives an acknowledge, it continues to increment
the current address register and clock out sequential data bytes.
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When the memory address limit is reached the current address will roll over and the
sequential read will continue till the addressing master sends a stop condition. Refer to
Figure 81.
Combined format
If a master wants to continue communication either with another slave or by changing the
direction of transfer then the master would generate a restart and provide a different slave
address or the same slave address with the R/W bit reversed. Refer to Figure 82.
Rollover handling
The RAM buffer of each slave is divided into pages whose length is defined according to
PL1:0 bits in I2C3SCR1. Rollover takes place in these pages as described below.
In the case of Page Write, if the number of data bytes transmitted is more than the page
length, the current address will roll over to the first byte of the current page and the previous
data will be overwritten. This page size is configured using PL[1:0] bit in the I2C3SCR1
register.
In case of Sequential Read, if the current address register value reaches the memory
address limit the address will roll over to the first address of the reserved area for the
respective slave.
There is no status flag to indicate the roll over.
Note:
The reserved areas for slaves 1 and 2 have a limit of 256 bytes. The area for slave 3 is 128
bytes. The MSB of the address is hardwired, the addressing master therefore needs to send
only an 8 bit address.
The page boundaries are defined based on the page size configuration using PL[1:0] bit in
the I2C3SCR1 register. If an 8-byte page size is selected, the upper 5 bits of the RAM
address are fixed and the lower 3 bits are incremented. For example, if the page write starts
at register address 0x0C, the write will follow the sequence 0x0C, 0x0D, 0x0E, 0x0F, 0x08,
0x09, 0x0A, 0x0B. If a 16-byte page size is selected, the upper 4 bits of the RAM address
are fixed and the lower 4 bits are incremented. For example, if the page write starts at
register address 0x0C, the write will follow the sequence 0x0C, 0x0D, 0x0E, 0x0F, 0x00,
0x01, etc.
Error conditions
■
BERR: Detection of a Stop or a Start condition during a byte transfer. In this case, the
BERR bit is set by hardware with an interrupt if ITER is set. During a stop condition, the
interface discards the data, releases the lines and waits for another Start condition.
However, a BERR on a Start condition will result in the interface discarding the data
and waiting for the next slave address on the bus.
■
NACK: Detection of a non-acknowledge bit not followed by a Stop condition. In this
case, NACK bit is set by hardware with an interrupt if ITER is set.
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On-chip peripherals
Figure 75. Transfer sequencing
7-bit Slave receiver:
S Address A Data1
A
A
Data2
Data2
A
A
DataN A P
.....
.....
WF
BusyW
7-bit Slave transmitter:
S Address A Data1
DataN NA P
RF
Legend: S = Start, P = Stop, A = Acknowledge, NA = Non-acknowledge,
WF = WF event, WFx bit is set (with interrupt if ITWEx=1, after Stop or Restart conditions),
cleared by reading the I2C3SSR register while no communication is ongoing.
RF = RF event, RFx is set (with interrupt if ITREx=1, after Stop or Restart conditions),
cleared by reading the I2C3SSR register while no communication is ongoing.
BusyW = BusyW flag in the I2C3CR2 register set, cleared by software writing 0.
Note:
The I2C3S supports a repeated start (S ) in place of a stop condition (P).
r
Figure 76. Byte write
Start
SA
W
Ack
BA
Ack
Data
Ack Stop
Figure 77. Page write
Start
SA
W
Ack
BA
Ack
Data
Ack
Data
Ack
Stop
Figure 78. Current address read
Start
SA
R
Ack
Data
Nack
Stop
Figure 79. Random read (dummy write + restart + current address read)
Start
SA
W
Ack
BA
Ack Start
SA
Ack
R
Data Nack
Stop
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On-chip peripherals
ST72344xx, ST2345xx
Figure 80. Random read (dummy write + stop + start + current address read)
Start
SA
W
Ack
BA
Ack Stop Start
SA
R
Ack Data Nack
Stop
Figure 81. Sequential read
Start
SA
R
Ack
Data
Ack
Ack
Data Nack
Stop
Data
Figure 82. Combined format for read
Start
SA
Nack
SA
R
Ack Data
Nack
Stop
Restart
R
Ack Data
Legend: SA - Slave Address, BA - Byte Address, W: Write, R: Read
11.7.6
Low-power modes
Table 68. Mode description
Mode
Description
No effect on I2C interface.
I2C interrupts causes the device to exit from Wait mode.
Wait
I2C registers are frozen.
In Halt mode, the I2C interface is inactive and does not acknowledge data on the bus.
The I2C interface resumes operation when the MCU is woken up by an interrupt with
“exit from Halt mode” capability.
Halt
I2C registers are frozen.
In Active halt mode, the I2C interface is inactive and does not acknowledge data on the
bus. The I2C interface resumes operation when the MCU is woken up by an interrupt
with “exit from Active-halt mode” capability.
Active-halt
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On-chip peripherals
11.7.7
Interrupt generation
Figure 83. Event flags and interrupt generation
Restart:
Restart: Restart condition on SDA
Restart condition on SDA
Stop: Stop condition on SDA
Dummy Write: True if no data is written in RAM
Write Protect: True for Write operation and if slaves
are write protected (since this is applicable for
slaves 1 and 2. For slave 3 and for Read operation
write protect will always be 0)
Restart
Stop
Data Status Flag
Dummy Write
Write Protect
Data Status Flag: Actual Interrupt is produced when
this condition is true
Data Status Flag
RF1
RF2
ITRE1/2
NACK
INTERRUPT 1
(Slave address 1/2)
ITER
BERR
WF1
WF2
ITWE1/2
Data Status Flag
Data Status Flag
WF3
ITWE3
BERR
INTERRUPT 2
ITER
NACK
(Slave address 3)
RF3
ITRE3
Data Status Flag
Note:
Read/Write interrupts are generated only after stop or restart conditions. Figure 83 shows
the conditions for the generation of the two interrupts.
Table 69. Interrupt events
Interrupt event
Enable
control
bit
Exit
from
wait
Exit
from
halt
Flag
Interrupt on write to Slave 1
Interrupt on write to Slave 2
Interrupt on write to Slave 3
Interrupt on Read from Slave 1, Slave 2 or Slave 3.
Errors
WF1
WF2
ITWE1
ITWE1
ITWE2
ITREx
ITER
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
WF3
RF1- RF3
BERR, NACK
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On-chip peripherals
ST72344xx, ST2345xx
11.7.8
Register description
I2C 3S control register 1 (I2C3SCR1)
Reset value: 0000 0000 (00h)
7
0
ITWE
PL1
PL0
0
ITER
Read / Write
Bits 7:6 = PL1:0 Page length configuration
ITRE3
ITRE1/2
ITWE3
1/2
This bit is set and cleared by software. It is also cleared by hardware when the interface
is disabled (PE=0).
Table 70. PL configuration
PL1
PL0
Page length
0
0
1
1
0
1
0
1
8
16
Full Page (256 bytes for slave 1 & 2, 128 bytes for slave 3)
NA
Bit 5 = Reserved, must be kept at 0.
Bit 4 = ITER BERR / NACK Interrupt enable
This bit is set and cleared by software. It is also cleared by hardware when the interface
is disabled (PE=0).
0: BERR / NACK interrupt disabled
1: BERR / NACK interrupt enabled
Note:
In case of error, if ITER is enabled either interrupt 1 or 2 is generated depending on which
slave flags the error (see Figure 83).
Bit 3= ITRE3 Interrupt enable on read from Slave 3
This bit is set and cleared by software. It is also cleared by hardware when the interface
is disabled (PE =0).
0: Interrupt on Read from Slave 3 disabled
1: Interrupt on Read from Slave 3 enabled
Bit 2 = ITRE1/2 Interrupt enable on read from Slave 1 or 2
This bit is set and cleared by software. It is also cleared by hardware when the interface
is disabled.
(PE =0)
0: Interrupt on Read from Slave 1 or 2 disabled
1: Interrupt on Read from Slave 1 or 2 enabled
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On-chip peripherals
Bit 1= ITWE3 Interrupt enable on write to Slave 3
This bit is set and cleared by software. It is also cleared by hardware when the interface
is disabled.
0: Interrupt after write to Slave 3 disabled
1: Interrupt after write to Slave 3 enabled
Bit 0 = ITWE1/2 Interrupt enable on write to Slave 1 or 2
This bit is set and cleared by software. It is also cleared by hardware when the interface
is disabled software. It is also cleared by hardware when the interface is disabled.
0: Interrupt after write to Slave 1 or 2 disabled
1: Interrupt after write to Slave 1 or 2 enabled
I2C control register 2 (I2C3SCR2)
Reset value: 0000 0000 (00h)
7
0
0
0
0
WP2
WP1
PE
BusyW
B/W
Read / Write
Bits 7:5 = Reserved, must be kept at 0.
Bit 4 = WP2 Write Protect enable for Slave 2
This bit is set and cleared by software. It is also cleared by hardware when the interface
is disabled (PE=0)
0: Write access to Slave 2 RAM buffer enabled
1: Write access to Slave 2 RAM buffer disabled
Bit 3 = WP1 Write Protect enable for Slave 1
This bit is set and cleared by software. It is also cleared by hardware when the interface
is disabled (PE=0).
0: Write access to Slave 1 RAM buffer enabled
1: Write access to Slave 1 RAM buffer disabled
Note:
(Applicable for both WP2/ WP1)
Only write operations are disabled/enabled. Read operations are not affected.
If a write operation is attempted, the slave address is acknowledged, the current address
register is overwritten, data is also acknowledged but it is not written to the RAM.
Both the current address and byte count registers are incremented as in normal operation.
No interrupt generated if slave is write protected
BusyW will not be set if slave is write protected
Bit 2 = PE Peripheral enable
This bit is set and cleared by software.
0: Peripheral disabled
1: Slave capability enabled
2
Note:
To enable the I C interface, write the CR register TWICE with PE=1, as the first write only
activates the interface (only PE is set).
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On-chip peripherals
ST72344xx, ST2345xx
Bit 1 = BusyW Busy on Write to RAM Buffer
This bit is set by hardware when a Stop/ Restart is detected after a write operation. The
I2C3S peripheral is temporarily disabled till this bit is reset. This bit is cleared by
software. If this bit is not cleared before the next slave address reception, further
communication will be non-acknowledged. This bit is set to 1 when modifying any bits
in Control Register 2. Writing a 1 to this bit does not actually modify BusyW but
prevents accidentally clearing of the bit.
0: No BusyW event occurred
1: A Stop/ Restart is detected after a write operation
Bit 0 = B/W Byte / Word Mode
This control bit must be set by software before a word is updated in the RAM buffer and
cleared by hardware after completion of the word update. In Word mode the CPU
cannot be interrupted when it is modifying the LSB byte and MSB byte of the word. This
mode is to ensure the coherency of data stored as words.
0: Byte mode
1: Word mode
Note:
When the word mode is enabled, all interrupts should be masked while the word is being
written in RAM.
I2C3S status register (I2C3SSR)
Reset value: 0000 0000 (00h)
7
0
NACK
BERR
WF3
WF2
Read Only
Bit 7= NACK Non Acknowledge not followed by Stop
WF1
RF3
RF2
RF1
This bit is set by hardware when a non acknowledge returned by the master is not
followed by a Stop or Restart condition. It is cleared by software reading the SR register
or by hardware when the interface is disabled (PE=0).
0: No NACK error occurred
1: Non Acknowledge not followed by Stop
Bit 6 = BERR Bus error
This bit is set by hardware when the interface detects a misplaced Start or Stop
condition. It is cleared by software reading SR register or by hardware when the
interface is disabled (PE=0).
The SCL line is not held low while BERR=1.
0: No misplaced Start or Stop condition
1: Misplaced Start or Stop condition
Bit 5 = WF3 Write operation to Slave 3
2
This bit is set by hardware on reception of the direction bit in the I C address byte for
Slave 3. This bit is cleared when the status register is read and there is no
communication ongoing or when the peripheral is disabled (PE = 0)
0: No write operation to Slave 3
1: Write operation performed to Slave 3
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On-chip peripherals
Bit 4 = WF2 Write operation to Slave 2
2
This bit is set by hardware on reception of the direction bit in the I C address byte for
Slave 2. This bit is cleared when the status register is read and there is no
communication ongoing, or when the peripheral is disabled (PE = 0)
0: No write operation to Slave 2
1: Write operation performed to Slave 2
Bit 3 = WF1 Write operation to Slave 1
2
This bit is set by hardware on reception of the direction bit in the I C address byte for
Slave 1. This bit is cleared by software when the status register is read and there is no
communication ongoing, or by hardware when the peripheral is disabled (PE = 0).
0: No write operation to Slave 1
1: Write operation performed to Slave 1
Bit 2 = RF3 Read operation from Slave 3
2
This bit is set by hardware on reception of the direction bit in the I C address byte for
Slave 3. It is cleared by software reading the SR register when there is no
communication ongoing. It is also cleared by hardware when the interface is disabled
(PE=0).
0: No read operation from Slave 3
1: Read operation performed from Slave 3
Bit 1= RF2 Read operation from Slave 2
2
This bit is set by hardware on reception of the direction bit in the I C address byte for
Slave 2. It is cleared by software reading the SR register when there is no
communication ongoing. It is also cleared by hardware when the interface is disabled
(PE=0).
0: No read operation from Slave 2
1: Read operation performed from Slave 2
Bit 0= RF1 Read operation from Slave 1
2
This bit is set by hardware on reception of the direction bit in the I C address byte for
Slave 1. It is cleared by software reading SR register when there is no communication
ongoing. It is also cleared by hardware when the interface is disabled (PE=0).
0: No read operation from Slave 1
1: Read operation performed from Slave 1
I2C byte count register (I2C3SBCR)
Reset value: 0000 0000 (00h)
7
0
NB7
NB6
NB5
NB4
NB3
NB2
NB1
NB0
Read only
Bits 7:0 = NB [7:0] Byte Count Register
This register keeps a count of the number of bytes received or transmitted through any
of the three addresses. This byte count is reset after reception by a slave address of a
new transfer and is incremented after each byte is transferred. This register is not
limited by the full page length. It is also cleared by hardware when the interface is
disabled (PE =0).
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On-chip peripherals
ST72344xx, ST2345xx
I2C slave 1 address register (I2C3SSAR1)
Reset value: 0000 0000 (00h)
7
0
ADDR7
ADDR6
ADDR5
ADDR4
Read / Write
Bits 7:1 = ADDR[7:1] Address of Slave 1
ADDR3
ADDR2
ADDR1
EN1
This register contains the first 7 bits of Slave 1 address (excluding the LSB) and is user
programmable. It is also cleared by hardware when the interface is disabled (PE =0).
Bit 0= EN1 Enable bit for Slave Address 1
This bit is used to enable/disable Slave Address 1. It is also cleared by hardware when
the interface is disabled (PE =0).
0: Slave Address 1 disabled
1: Slave Address 1 enabled
I2C slave 2 address register (I2C3SSAR2)
Reset value: 0000 0000 (00h)
7
0
ADDR7
ADDR6
ADDR5
ADDR4
Read / Write
Bits 7:1 = ADDR[7:1] Address of Slave 2.
ADDR3
ADDR2
ADDR1
EN2
This register contains the first 7 bits of Slave 2 address (excluding the LSB) and is user
programmable. It is also cleared by hardware when the interface is disabled (PE =0).
Bit 0= EN2 Enable bit for Slave Address 2
This bit is used to enable/disable Slave Address 2. It is also cleared by hardware when
the interface is disabled (PE =0).
0: Slave Address 2 disabled
1: Slave Address 2 enabled
I2C slave 3 address register (I2C3SSAR3)
Reset value: 0000 0000 (00h)
7
0
ADDR7
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
EN3
Read / Write
Bit 7:1 = ADDR[7:1] Address of Slave 3
This register contains the first 7 bits of Slave 3 address (excluding the LSB) and is user
programmable. It is also cleared by hardware when the interface is disabled (PE =0).
Bit 0= EN3 Enable bit for Slave Address 3
This bit is used to enable/disable Slave Address 3. It is also cleared by hardware when
the interface is disabled (PE =0).
0: Slave Address 3 disabled
1: Slave Address 3 enabled
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On-chip peripherals
I2C slave 1 memory current address register (I2C3SCAR1)
Reset value: 0000 0000 (00h)
7
0
CA7
CA6
CA5
CA4
Read only
Bit 7:0 = CA[7:0] Current address of Slave 1 buffer
CA3
CA2
CA1
CA0
This register contains the 8 bit offset of Slave Address 1 reserved area in RAM. It is
also cleared by hardware when the interface is disabled (PE =0).
I2C slave 2 memory current address register (I2C3SCAR2)
Reset value: 0000 0000 (00h)
7
0
CA7
CA6
CA5
CA4
Read only
Bit 7:0 = CA[7:0] Current address of Slave 2 buffer
CA3
CA2
CA1
CA0
This register contains the 8-bit offset of Slave Address 2 reserved area in RAM. It is
also cleared by hardware when the interface is disabled (PE =0).
I2C slave 3 memory current address register (I2C3SCAR3)
Reset value: 0000 0000 (00h)
7
0
CA7
CA6
CA5
CA4
Read only
Bit 6:0 = CA[6:0] Current address of Slave 3 buffer
CA3
CA2
CA1
CA0
This register contains the 8-bit offset of slave address 3 reserved area in RAM. It is also
cleared by hardware when the interface is disabled (PE =0).
Note:
Slave address 3 can store only 128 bytes. For slave address 3, CA7 bit will remain 0. i.e. if
the Byte Address sent is 0x80, then the Current Address register will hold the 0x00 value
due to an overflow.
2
Table 71. I C3S register map
Address Register
7
6
5
4
3
2
1
0
(Hex.)
name
0060h
0061h
0062h
0063h
I2C3SCR1
I2C3SCR2
I2C3SSR
PL1
0
PL0
0
0
ITER
WP2
WF2
NB4
ITRE3 ITRE1/2 ITWE3 ITWE1/2
0
WP1
WF1
NB3
PE
BusyW
RF2
B/W
RF1
NB1
EN1
NACK BERR
NB7 NB6
WF3
NB5
RF3
NB2
I2C3SBCR
NB1
0064h I2C3SSAR1 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1
0065h I2C3SCAR1 CA 7 .. CA0
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On-chip peripherals
ST72344xx, ST2345xx
2
Table 71. I C3S register map (continued)
Address Register
7
6
5
4
3
2
1
0
(Hex.)
0066h I2C3SSAR2 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1
0067h I2C3SCAR2 CA 7 .. CA0
0068h I2C3SSAR3 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1
0069h I2C3SCAR3 CA 7 .. CA0
name
EN2
EN3
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On-chip peripherals
11.8
10-bit A/D converter (ADC)
11.8.1
Introduction
The on-chip Analog to Digital Converter (ADC) peripheral is a 10-bit, successive
approximation converter with internal sample and hold circuitry. This peripheral has up to 16
multiplexed analog input channels (refer to device pinout description) that allow the
peripheral to convert the analog voltage levels from up to 16 different sources.
The result of the conversion is stored in a 10-bit Data Register. The A/D converter is
controlled through a Control/Status Register.
Note:
Whenever you change the channel or write in the ADCCSR register, the ADC conversion
starts again.
11.8.2
Main features
■
■
■
■
■
■
10-bit conversion
Up to 16 channels with multiplexed input
Linear successive approximation
Data register (DR) which contains the results
Conversion complete status flag
ON/OFF bit (to reduce consumption)
The block diagram is shown in Figure 84.
Figure 84. ADC block diagram
fCPU
DIV 4
0
fADC
DIV 2
1
CH3
EOC SPEEDADON
0
CH2 CH1 CH0
ADCCSR
4
AIN0
AIN1
ANALOG TO DIGITAL
CONVERTER
ANALOG
MUX
AINx
ADCDRH
D9 D8 D7 D6 D5 D4 D3 D2
ADCDRL
0
0
0
0
0
0
D1 D0
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On-chip peripherals
ST72344xx, ST2345xx
11.8.3
Functional description
The conversion is monotonic, meaning that the result never decreases if the analog input
does not, and never increases if the analog input does not.
If the input voltage (V ) is greater than V
(high-level voltage reference), then the
AIN
AREF
conversion result is FFh in the ADCDRH register and 03h in the ADCDRL register (without
overflow indication).
If the input voltage (V ) is lower than V
(low-level voltage reference), then the
SSA
AIN
conversion result in the ADCDRH and ADCDRL registers is 00 00h.
The A/D converter is linear and the digital result of the conversion is stored in the ADCDRH
and ADCDRL registers. The accuracy of the conversion is described in Section 13:
Electrical characteristics.
R
is the maximum recommended impedance for an analog input signal. If the impedance
AIN
is too high, this will result in a loss of accuracy due to leakage and sampling not being
completed in the allotted time.
A/D converter configuration
The analog input ports must be configured as input, no pull-up, no interrupt. Refer to the
«I/O ports» chapter. Using these pins as analog inputs does not affect the ability of the port
to be read as a logic input.
In the ADCCSR register:
–
Select the CS[3:0] bits to assign the analog channel to convert.
Starting the conversion
In the ADCCSR register:
■
Set the ADON bit to enable the A/D converter and to start the conversion. From this
time on, the ADC performs a continuous conversion of the selected channel.
When a conversion is complete:
■
■
The EOC bit is set by hardware.
The result is in the ADCDR registers.
A read to the ADCDRH resets the EOC bit.
To read the 10 bits, perform the following steps:
1. Poll the EOC bit
2. Read the ADCDRL register
3. Read the ADCDRH register. This clears EOC automatically.
Note:
The data is not latched, so both the low and the high data register must be read before the
next conversion is complete, so it is recommended to disable interrupts while reading the
conversion result.
To read only 8 bits, perform the following steps:
1. Poll the EOC bit
2. Read the ADCDRH register. This clears EOC automatically.
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On-chip peripherals
Changing the conversion channel
The application can change channels during conversion. When software modifies the
CH[3:0] bits in the ADCCSR register, the current conversion is stopped, the EOC bit is
cleared, and the A/D converter starts converting the newly selected channel.
11.8.4
Low-power modes
Note:
The A/D converter may be disabled by resetting the ADON bit. This feature allows reduced
power consumption when no conversion is needed.
Table 72. Mode description
Mode
Description
Wait
Halt
No effect on A/D Converter
A/D Converter disabled.
After wakeup from Halt mode, the A/D Converter requires a stabilization time
STAB (see Electrical characteristics) before accurate conversions can be
performed.
t
11.8.5
11.8.6
Interrupts
None.
Register description
Control/status register (ADCCSR)
Reset value: 0000 0000 (00h)
7
0
EOC
SPEED
ADON
Read/Write (Except bit 7 read only)
Bit 7 = EOC End of Conversion
0
CH3
CH2
CH1
CH0
This bit is set by hardware. It is cleared by hardware when software reads the ADCDRH
register or writes to any bit of the ADCCSR register.
0: Conversion is not complete
1: Conversion complete
Bit 6 = SPEED ADC clock selection
This bit is set and cleared by software.
0: f
1: f
= f
= f
/4
/2
ADC
ADC
CPU
CPU
Bit 5 = ADON A/D Converter on
This bit is set and cleared by software.
0: Disable ADC and stop conversion
1: Enable ADC and start conversion
Bit 4 = Reserved. Must be kept cleared.
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On-chip peripherals
ST72344xx, ST2345xx
Bits 3:0 = CH[3:0] Channel Selection
These bits are set and cleared by software. They select the analog input to convert.
Table 73. Channel selection
Channel pin(1)
CH3
CH2
CH1
CH0
AIN0
AIN1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
AIN2
AIN3
AIN4
AIN5
Reserved
Reserved
AIN8
Reserved
AIN10
Reserved
AIN12
AIN13
AIN14
AIN15
1. The number of channels is device dependent. Refer to the device pinout description.
Data register (ADCDRH)
Reset value: 0000 0000 (00h)
7
0
D9
D8
D7
D6
D5
D4
D3
D2
Read Only
Bits 7:0 = D[9:2] MSB of Converted Analog Value
Data register (ADCDRL)
Reset value: 0000 0000 (00h)
7
0
0
0
0
0
0
0
D1
D0
Read Only
Bits7:2 = Reserved. Forced by hardware to 0.
Bits 1:0 = D[1:0] LSB of Converted Analog Value
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On-chip peripherals
Table 74. ADC register map and reset values
Address
(Hex.)
Register
label
7
6
5
4
3
2
1
0
ADCCSR
Reset value
EOC SPEED ADON
CH3
0
CH2
0
CH1
0
CH0
0
0070h
0071h
0072h
0
0
0
0
ADCDRH
Reset value
D9
0
D8
0
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
ADCDRL
Reset value
D1
0
D0
0
0
0
0
0
0
0
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Instruction set
ST72344xx, ST2345xx
12
Instruction set
12.1
ST7 addressing modes
The ST7 Core features 17 different addressing modes which can be classified in seven main
groups:
Table 75. Addressing mode groups
Addressing mode
Example
Inherent
Immediate
Direct
nop
ld A,#$55
ld A,$55
Indexed
ld A,($55,X)
ld A,([$55],X)
jrne loop
Indirect
Relative
Bit operation
bset byte,#5
The ST7 Instruction set is designed to minimize the number of bytes required per
instruction: To do so, most of the addressing modes may be subdivided in two submodes
called long and short:
■
Long addressing mode is more powerful because it can use the full 64-Kbyte address
space; however, it uses more bytes and more CPU cycles.
■
Short addressing mode is less powerful because it can generally only access page
zero (0000h - 00FFh range), but the instruction size is more compact, and faster. All
memory-to-memory instructions use short addressing modes only (CLR, CPL, NEG,
BSET, BRES, BTJT, BTJF, INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP)
The ST7 Assembler optimizes the use of long and short addressing modes.
Table 76. ST7 addressing mode overview
Destination/
source
Pointer
address size (hex.)
Pointer
Length
(bytes)
Mode
Syntax
Inherent
nop
+ 0
+ 1
Immedi
ate
ld A,#$55
Short
Long
Direct
Direct
ld A,$10
00..FF
+ 1
+ 2
ld A,$1000
0000..FFFF
00..FF
No
Offset
+ 0 (with X register)
+ 1 (with Y register)
Direct Indexed ld A,(X)
Short
Long
Short
Long
Direct Indexed ld A,($10,X)
Direct Indexed ld A,($1000,X)
00..1FE
+ 1
+ 2
+ 2
+ 2
0000..FFFF
00..FF
Indirect
Indirect
ld A,[$10]
00..FF
00..FF
byte
ld A,[$10.w]
0000..FFFF
word
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Instruction set
Table 76. ST7 addressing mode overview (continued)
Destination/
Pointer
address size (hex.)
Pointer
Length
(bytes)
Mode
Syntax
source
Short
Long
Indirect Indexed ld A,([$10],X)
Indirect Indexed ld A,([$10.w],X)
00..1FE
00..FF
00..FF
byte
+ 2
+ 2
+ 1
+ 2
+ 1
+ 2
+ 2
+ 3
0000..FFFF
PC-128/PC+127(1)
PC-128/PC+127(1)
00..FF
word
Relative Direct
Relative Indirect
jrne loop
jrne [$10]
00..FF
00..FF
00..FF
byte
byte
byte
Bit
Bit
Bit
Bit
Direct
bset $10,#7
bset [$10],#7
Indirect
00..FF
Direct Relative btjt $10,#7,skip
Indirect Relative btjt [$10],#7,skip
00..FF
00..FF
1. At the time the instruction is executed, the Program Counter (PC) points to the instruction following JRxx.
12.1.1
Inherent
All Inherent instructions consist of a single byte. The opcode fully specifies all the required
information for the CPU to process the operation.
Table 77. Inherent instructions
Inherent instruction
Function
NOP
No operation
S/W Interrupt
TRAP
WFI
Wait for interrupt (low-power mode)
Halt oscillator (lowest power mode)
Subroutine return
HALT
RET
IRET
SIM
Interrupt subroutine return
Set interrupt mask
Reset interrupt mask
Set carry flag
RIM
SCF
RCF
Reset carry flag
RSP
Reset stack pointer
Load
LD
CLR
Clear
PUSH/POP
INC/DEC
TNZ
Push/Pop to/from the stack
Increment/Decrement
Test negative or zero
1 or 2 complement
Byte Multiplication
CPL, NEG
MUL
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Instruction set
ST72344xx, ST2345xx
Table 77. Inherent instructions (continued)
Inherent instruction
Function
Shift and Rotate Operations
Swap Nibbles
SLL, SRL, SRA, RLC, RRC
SWAP
12.1.2
Immediate
Immediate instructions have 2 bytes; the first byte contains the opcode, the second byte
contains the operand value.
Table 78. Immediate instructions
Immediate instruction
Function
LD
Load
CP
Compare
BCP
Bit Compare
Logical Operations
Arithmetic Operations
AND, OR, XOR
ADC, ADD, SUB, SBC
12.1.3
Direct
In Direct instructions, the operands are referenced by their memory address.
The direct addressing mode consists of two submodes:
Direct (Short)
The address is a byte, thus requires only 1 byte after the opcode, but only allows 00 - FF
addressing space.
Direct (Long)
The address is a word, thus allowing 64-Kbyte addressing space, but requires 2 bytes after
the opcode.
12.1.4
Indexed (No Offset, Short, Long)
In this mode, the operand is referenced by its memory address, which is defined by the
unsigned addition of an index register (X or Y) with an offset.
The indirect addressing mode consists of three submodes:
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Instruction set
Indexed (No offset)
There is no offset (no extra byte after the opcode), and allows 00 - FF addressing space.
■
Indexed (Short)
The offset is a byte, thus requires only 1 byte after the opcode and allows 00 - 1FE
addressing space.
■
Indexed (Long)
The offset is a word, thus allowing 64-Kbyte addressing space and requires 2 bytes
after the opcode.
12.1.5
Indirect (Short, Long)
The required data byte to do the operation is found by its memory address, located in
memory (pointer).
The pointer address follows the opcode. The indirect addressing mode consists of two
submodes:
Indirect (Short)
The pointer address is a byte, the pointer size is a byte, thus allowing 00 - FF addressing
space, and requires 1 byte after the opcode.
Indirect (Long)
The pointer address is a byte, the pointer size is a word, thus allowing 64-Kbyte addressing
space, and requires 1 byte after the opcode.
12.1.6
Indirect Indexed (Short, Long)
This is a combination of indirect and short indexed addressing modes. The operand is
referenced by its memory address, which is defined by the unsigned addition of an index
register value (X or Y) with a pointer value located in memory. The pointer address follows
the opcode.
The indirect indexed addressing mode consists of two submodes:
Indirect Indexed (Short)
The pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1FE addressing
space, and requires 1 byte after the opcode.
Indirect Indexed (Long)
The pointer address is a byte, the pointer size is a word, thus allowing 64-Kbyte addressing
space, and requires 1 byte after the opcode.
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Instruction set
ST72344xx, ST2345xx
Table 79. Instructions supporting direct, indexed, indirect and indirect indexed
addressing modes
Long and short instructions
Function
LD
CP
Load
Compare
AND, OR, XOR
ADC, ADD, SUB, SBC
BCP
Logical Operations
Arithmetic Addition/subtraction operations
Bit Compare
Table 80. Short instructions
Short instructions only
Function
CLR
Clear
INC, DEC
Increment/Decrement
Test Negative or Zero
1 or 2 Complement
Bit Operations
TNZ
CPL, NEG
BSET, BRES
BTJT, BTJF
SLL, SRL, SRA, RLC, RRC
SWAP
Bit Test and Jump Operations
Shift and Rotate Operations
Swap Nibbles
CALL, JP
Call or Jump subroutine
12.1.7
Relative Mode (direct, indirect)
This addressing mode is used to modify the PC register value by adding an 8-bit signed
offset to it.
Table 81. Relative direct/indirect instructions
Available relative direct/indirect instructions
Function
JRxx
Conditional Jump
Call Relative
CALLR
The relative addressing mode consists of two submodes:
Relative (Direct)
The offset follows the opcode.
Relative (Indirect)
The offset is defined in memory, of which the address follows the opcode.
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Instruction set
12.2
Instruction groups
The ST7 family devices use an instruction set consisting of 63 instructions. The instructions
may be subdivided into 13 main groups as illustrated in the following table:
Table 82. Main instruction groups
Load and Transfer
LD
CLR
Stack operation
PUSH POP
RSP
Increment/Decrement
Compare and Tests
Logical operations
INC
CP
DEC
TNZ
OR
BCP
XOR
AND
CPL NEG
Bit Operation
BSET BRES
BTJT BTJF
Conditional Bit Test and Branch
Arithmetic operations
Shift and Rotates
ADC
SLL
ADD
SRL
JRT
SUB
SRA
JRF
SBC MUL
RLC RRC SWAP SLA
Unconditional Jump or Call
Conditional Branch
Interruption management
JRA
JRxx
JP
CALL CALLR NOP RET
TRAP WFI
HALT IRET
SCF RCF
Condition Code Flag modification SIM
RIM
Using a prebyte
The instructions are described with 1 to 4 bytes.
In order to extend the number of available opcodes for an 8-bit CPU (256 opcodes), three
different prebyte opcodes are defined. These prebytes modify the meaning of the instruction
they precede.
The whole instruction becomes:
■
■
■
■
PC-2
PC-1
PC
End of previous instruction
Prebyte
Opcode
PC+1
Additional word (0 to 2) according to the number of bytes required to
compute the effective address
These prebytes enable instruction in Y as well as indirect addressing modes to be
implemented. They precede the opcode of the instruction in X or the instruction using direct
addressing mode. The prebytes are:
PDY 90
Replace an X-based instruction using immediate, direct, indexed, or inherent
addressing mode by a Y one.
PIX 92
Replace an instruction using direct, direct bit or direct relative addressing mode
to an instruction using the corresponding indirect addressing mode.
It also changes an instruction using X indexed addressing mode to an
instruction using indirect X indexed addressing mode.
PIY 91
Replace an instruction using X indirect indexed addressing mode by a Y one.
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Instruction set
ST72344xx, ST2345xx
12.2.1
Illegal opcode reset
In order to provide enhanced robustness to the device against unexpected behavior, a
system of illegal opcode detection is implemented. If a code to be executed does not
correspond to any opcode or prebyte value, a reset is generated. This, combined with the
Watchdog, allows the detection and recovery from an unexpected fault or interference.
Note:
A valid prebyte associated with a valid opcode forming an unauthorized combination does
not generate a reset.
Table 83. Illegal opcode detection
Mnemo
Description
Function/Example
Dst
Src
H
I
N
Z
C
ADC
ADD
AND
Add with Carry
Addition
A = A + M + C
A = A + M
A
A
A
M
H
H
N
N
N
Z
Z
Z
C
C
M
M
Logical And
A = A . M
Bit compare A,
Memory
BCP
tst (A . M)
A
M
N
Z
BRES Bit Reset
bres Byte, #3
bset Byte, #3
M
M
M
M
BSET
BTJF
BTJT
CALL
Bit Set
Jump if bit is false (0) btjf Byte, #3, Jmp1
Jump if bit is true (1) btjt Byte, #3, Jmp1
Call subroutine
C
C
Call subroutine
relative
CALLR
CLR
CP
Clear
reg, M
reg
0
N
N
N
1
Z
Z
Z
Arithmetic Compare
One Complement
Decrement
tst(Reg - M)
A = FFH-A
dec Y
M
C
1
CPL
DEC
HALT
reg, M
reg, M
Halt
0
I
Interrupt routine
return
IRET
Pop CC, A, X, PC
H
N
N
Z
Z
C
INC
JP
Increment
inc X
reg, M
Absolute Jump
Jump relative always
Jump relative
Never jump
jp [TBL.w]
JRA
JRT
JRF
jrf *
Jump if ext. interrupt
= 1
JRIH
JRIL
Jump if ext. interrupt
= 0
JRH
Jump if H = 1
Jump if H = 0
H = 1 ?
H = 0 ?
JRNH
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Instruction set
Table 83. Illegal opcode detection (continued)
Mnemo
Description
Function/Example
I = 1 ?
I = 0 ?
Jump if N = 1 (minus) N = 1 ?
Jump if N = 0 (plus) N = 0 ?
Dst
Src
H
I
N
Z
C
JRM
Jump if I = 1
JRNM Jump if I = 0
JRMI
JRPL
JREQ
Jump if Z = 1 (equal) Z = 1 ?
Jump if Z = 0 (not
Z = 0 ?
JRNE
equal)
JRC
Jump if C = 1
Jump if C = 0
C = 1 ?
JRNC
C = 0 ?
JRULT Jump if C = 1
Unsigned <
Jmp if unsigned >=
Unsigned >
Unsigned <=
dst <= src
JRUGE Jump if C = 0
JRUGT Jump if (C + Z = 0)
JRULE Jump if (C + Z = 1)
LD
Load
reg, M M, reg
A, X, Y X, Y, A
reg, M
N
N
N
N
Z
Z
Z
Z
MUL
NEG
NOP
OR
Multiply
X,A = X * A
neg $10
0
0
Negate (2's compl)
No Operation
OR operation
Pop from the Stack
C
A = A + M
pop reg
A
M
M
M
POP
reg
CC
pop CC
H
I
C
0
reg,
CC
PUSH Push onto the Stack push Y
M
RCF
RET
RIM
RLC
RRC
RSP
SBC
SCF
SIM
Reset carry flag
Subroutine Return
Enable Interrupts
Rotate left true C
Rotate right true C
Reset Stack Pointer
Subtract with Carry
Set carry flag
C = 0
I = 0
0
C <= Dst <= C
C => Dst => C
S = Max allowed
A = A - M - C
C = 1
reg, M
reg, M
N
N
Z
Z
C
C
A
M
N
Z
C
1
Disable Interrupts
Shift left Arithmetic
Shift left Logic
I = 1
1
SLA
SLL
C <= Dst <= 0
C <= Dst <= 0
0 => Dst => C
reg, M
reg, M
reg, M
reg, M
N
N
0
Z
Z
Z
Z
C
C
C
C
SRL
SRA
Shift right Logic
Shift right Arithmetic Dst7 => Dst => C
N
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Instruction set
ST72344xx, ST2345xx
Table 83. Illegal opcode detection (continued)
Mnemo Description Function/Example
SUB Subtraction A = A - M
SWAP SWAP nibbles
Dst
Src
H
I
N
Z
C
A
M
N
N
N
Z
Z
Z
C
Dst[7..4] <=> Dst[3..0]
tnz lbl1
reg, M
TNZ
Test for Neg & Zero
TRAP
WFI
S/W trap
S/W interrupt
1
0
Wait for Interrupt
Exclusive OR
XOR
A = A XOR M
A
M
N
Z
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Electrical characteristics
13
Electrical characteristics
13.1
Parameter conditions
Unless otherwise specified, all voltages are referred to V
.
SS
13.1.1
Minimum and maximum values
Unless otherwise specified, the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at T =25°C and T =T max (given by the
A
A
A
selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean±3Σ).
13.1.2
Typical values
Unless otherwise specified, typical data are based on T = 25 °C, V = 5 V (for the
A
DD
4.5 V ≤ V ≤ 5.5 V voltage range) and V = 3.3 V (for the 3 V ≤ V ≤ 3.6 V voltage range).
DD
DD
DD
They are given only as design guidelines and are not tested.
13.1.3
13.1.4
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 85.
Figure 85. Pin loading conditions
ST7 PIN
C
L
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Electrical characteristics
ST72344xx, ST2345xx
13.1.5
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 86.
Figure 86. Pin input voltage
ST7 PIN
V
IN
13.2
Absolute maximum ratings
Stresses above those listed as “absolute maximum ratings” may cause permanent damage
to the device. This is a stress rating only and functional operation of the device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
Table 84. Voltage characteristics
Symbol
DD - VSS Supply voltage
Ratings
Maximum value
Unit
V
7.0
VIN
Input voltage on any pin (1)(2)
VSS-0.3 to VDD+0.3
V
|VDDx- VDD
|
Variations between different power pins
0.3
0.3
|VSSx - VSS
| Variations between all the different ground pins
see Section 13.8.3: Absolute
maximum ratings (electrical
sensitivity)
Electrostatic discharge voltage (human body
model)
VESD(HBM)
1. Directly connecting the RESET and I/O pins to VDD or VSS could damage the device if an unintentional
internal reset is generated or an unexpected change of the I/O configuration occurs (for example, due to a
corrupted program counter). To guarantee safe operation, this connection has to be done through a pull-up
or pull-down resistor (typical: 4.7 kΩ for RESET, 10 kΩ for I/Os). Unused I/O pins must be tied in the same
way to VDD or VSS according to their reset configuration.
2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. For true open-drain
pads, there is no positive injection current, and the corresponding VIN maximum must always be respected
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Electrical characteristics
Maximum value Unit
Table 85. Current characteristics
Symbol
Ratings
IVDD
IVSS
Total current into VDD power lines (source) (1)
Total current out of VSS ground lines (sink) (1)
Output current sunk by any standard I/O and control pin
Output current sunk by any high sink I/O pin
Output current source by any I/Os and control pin
Injected current on ISPSEL pin
75
150
20
IIO
40
- 25
± 5
± 5
± 5
+5
mA
Injected current on RESET pin
(2)(3)
IINJ(PIN)
Injected current on OSC1 and OSC2 pins
Injected current on PB0 pin (4)
Injected current on any other pin (5)
± 5
± 20
(2)
ΣIINJ(PIN)
Total injected current (sum of all I/O and control pins) (5)
1. All power (VDD) and ground (VSS) lines must always be connected to the external supply.
2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. For true open-drain
pads, there is no positive injection current, and the corresponding VIN maximum must always be respected
3. Negative injection disturbs the analog performance of the device. In particular, it induces leakage currents
throughout the device including the analog inputs. To avoid undesirable effects on the analog functions,
care must be taken:
- Analog input pins must have a negative injection less than 0.8 mA (assuming that the impedance of the
analog voltage is lower than the specified limits)
- Pure digital pins must have a negative injection less than 1.6 mA. In addition, it is recommended to inject
the current as far as possible from the analog input pins.
4. No negative current injection allowed on PB0 pin.
5. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values). These results are based on
characterisation with ΣIINJ(PIN) maximum current injection on four I/O port pins of the device.
Table 86. Thermal characteristics
Symbol
Ratings
Value
Unit
TSTG
TJ
Storage temperature range
–65 to +150
°C
Maximum junction temperature (see Table 118)
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Electrical characteristics
ST72344xx, ST2345xx
13.3
Operating conditions
(1)
Table 87. General operating conditions
Symbol
Parameter
Conditions
CPU = 8 MHz. max.
Min
Max
Unit
f
3.3
2.7
5.5
5.5
VDD
Supply voltage
V
fCPU = 4 MHz. max.
3.3 V ≤VDD≤ 5.5 V
2.7 V ≤ VDD < 3.3 V
Up to 16
Up to 8
fOSC
External clock frequency
MHz
1. TA = -40 to +85 °C unless otherwise specified.
Note:
When the power supply is between 2.7 and 2.95 V (V
max), the device is either in the
IT+(LVD)
guaranteed functional area or in reset state, thus allowing a deterministic application
behavior. However, the LVD may generate a reset below 2.95 V and the user should
therefore not use the device below this level when the LVD is enabled.
Figure 87. f
maximum operating frequency versus V supply voltage
DD
CPU
fCPU [MHz]
8
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
4
2
0
FUNCTIONALITY
GUARANTEED
IN THIS AREA
CAUTION: RESET MAY
BE ACTIVATED BY LVD
IN THIS AREA
SUPPLY VOLTAGE [V]
5.5
4.0
4.5
5.0
2.7 3.3
3.6
Table 88. LVD thresholds
Symbol
Parameter
Conditions (1)
Min
Typ
Max
Unit
High threshold
Med. threshold
Low threshold
3.85
3.24
2.60
4.20
3.56
2.88
4.61
3.90
3.14
Reset release threshold
(VDD rise)
VIT+(LVD)
V
High threshold
Med. threshold
Low threshold
3.66
3.04
2.45
3.98
3.36
2.71
4.36
3.66
2.95
Reset generation threshold
(VDD fall)
VIT-(LVD)
LVD voltage threshold
hysteresis
Vhys(LVD)
VIT+(LVD)-VIT-(LVD)
200
mV
VtPOR
VDD rise time rate
20 (2)
100 (2)
ms/V
ns
tg(VDD)
VDD glitches filtered by LVD
150
1. TA = -40 to +85 °C unless otherwise specified.
2. Not tested in production, guaranteed by design
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Electrical characteristics
Min (2) Typ Max (2) Unit
Table 89. AVD thresholds
Symbol
Parameter
Conditions (1)
High threshold
Med. threshold
Low threshold
4.15
3.64
3.00
4.50
3.96
3.28
4.91
4.30
3.54
1=>0 AVDF flag toggle threshold
(VDD rise)
VIT+(AVD)
V
High threshold
Med. threshold
Low threshold
3.96
3.44
2.85
4.28
3.76
3.11
4.66
4.06
3.35
0=>1 AVDF flag toggle threshold
(VDD fall)
VIT-(AVD)
Vhys(AVD) AVD voltage threshold hysteresis VIT+(AVD)-VIT-(AVD)
Voltage drop between ADV flag
200
mV
mV
ΔVIT-
V
IT-(AVD)-VIT-(LVD)
450
set and LVD reset activated
1. TA = -40 to +85°C unless otherwise specified.
2. Not tested in production, guaranteed by characterization.
Table 90. PLL characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDD = 2.7 to 3.65 V
PLL option x4 selected
0.95
1
1.05
fPLLIN
PLL Input frequency (1)
MHz
VDD = 3.3 to 5.5 V
PLL option x8 selected
0.90
1
1.10
PLL option x4 selected (2)
PLL option x8 selected
fRC = 1 MHz
2.7
3.3
3.65
5.5
VDD(PLL)
tw(JIT)
PLL operating range
PLL jitter period
V
kHz
%
8
VDD = 3.0 V
3.0
1.6
JITPLL
PLL jitter (ΔfCPU/fCPU)
VDD = 5.0 V
PLL current
consumption
IDD(PLL)
TA=25 °C
600
µA
1. Guaranteed by design.
2. To obtain a x4 multiplication ratio in the range 3.3 to 5.5V, the DIV2EN option bit must enabled.
The ST7 internal clock can be supplied by an internal RC oscillator and PLL (selectable by
option byte).
Table 91. Internal RC oscillator and PLL
Symbol
Parameter
Conditions
Min
Typ Max
Unit
Internal RC oscillator
operating voltage
VDD(RC)
2.7
5.5
Refer to operating range
of VDD with TA, Table 87
V
VDD(x4PLL) x4 PLL operating voltage
VDD(x8PLL) x8 PLL operating voltage
2.7
3.3
5.5
5.5
PLL input
tSTARTUP
PLL Startup time
60
clock(fPLL
)
cycles
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Electrical characteristics
ST72344xx, ST2345xx
13.4
Internal RC oscillator characteristics
Table 92. Internal RC oscillator characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
RCCR = FF (reset value), TA = 25 °C,
VDD = 5 V
625
1000
612
RCCR = RCCR0 (2), TA = 25 °C, VDD = 5 V
Internal RC oscillator
frequency (1)
fRC
kHz
RCCR = FF (reset value), TA = 25 °C,
VDD = 3 V
RCCR = RCCR1(2), TA = 25 °C, VDD = 3 V
1000
TA = 25 °C, VDD = 5 V
-1
-1
+1
+1
%
%
%
%
%
TA = 25 °C, VDD = 4.5 to 5.5 V (3)
TA = 25 to +85 °C, VDD = 5 V (3)
Accuracy of Internal RC
ACCRC oscillator with
-3
+3
RCCR=RCCR0 (2)
TA = 25 to +85 °C, VDD = 4.5 to 5.5 V (3)
TA = -40 to +25 °C, VDD = 4.5 to 5.5 V (3)
-3.5
-3
+3.5
+7
RC oscillator current
consumption
IDD(RC)
tsu(RC)
TA = 25 °C, VDD = 5 V
600 (3)
μA
μs
RC oscillator setup time TA = 25 °C, VDD = 5 V
10 (2)
1. If the RC oscillator clock is selected, to improve clock stability and frequency accuracy, it is recommended to place a
decoupling capacitor, typically 100 nF, between the VDD and VSS pins as close as possible to the ST7 device.
It is also recommended to perform the calibration on board.
2. See Internal RC oscillator.
3. Expected results. Data based on characterization, not tested in production.
Figure 88. Typical RC frequency vs. RCCR
Typical Rc freq (MHz) = f(RCCR) @ 25°C
1.7
1.6
Rc @ 5V
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
Rc @ 3V
0
50
100
150
200
250
RCCR (decimal)
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Electrical characteristics
13.5
Supply current characteristics
The following current consumption specified for the ST7 functional operating modes over
temperature range does not take into account the clock source current consumption. To get
the total device consumption, the two current values must be added (except for Halt mode
for which the clock is stopped).
Table 93. Supply current
Symbol
Parameter
Conditions(1)
Typ Max Unit
Supply current in Run mode
Supply current in Wait mode
Supply current in Slow mode
fCPU = 8 MHz (2)
fCPU = 8 MHz (3)
fCPU = 250 kHz (4)
8.5
3.7
4.1
13
6
mA
µA
7
Supply current in Slow-wait
mode
f
CPU = 250 kHz (5)
2.2
1
3.5
10
60
IDD
Supply current in Halt mode (6)
-40°C ≤TA ≤ +85 °C
TA= +25 °C
Supply current in AWUFH
mode (7)(8)
50
Supply current in Active-halt
mode (6)(7)
TA= +25 °C
500
700
1. TA = -40 to +85°C unless otherwise specified
2. CPU running with memory access, all I/O pins in input mode with a static value at VDD or VSS (no load), all
peripherals in reset state; clock input (OSC1) driven by external square wave, LVD disabled.
3. All I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals in reset state; clock
input (OSC1) driven by external square wave, LVD disabled.
4. Slow mode selected with fCPU based on fOSC divided by 32. All I/O pins in input mode with a static value at
V
DD or VSS (no load), all peripherals in reset state; clock input (OSC1) driven by external square wave,
LVD disabled.
5. Slow-wait mode selected with fCPU based on fOSC divided by 32. All I/O pins in input mode with a static
value at VDD or VSS (no load), all peripherals in reset state; clock input (OSC1) driven by external square
wave, LVD disabled.
6. All I/O pins in output mode with a static value at VSS (no load), LVD disabled. Data based on
characterization results, tested in production at VDD max and fCPU max.
7. All I/O pins in input mode with a static value at VDD or VSS (no load). Data tested in production at VDD max.
and fCPU max.
8. This consumption refers to the Halt period only and not the associated run period which is software
dependent.
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Electrical characteristics
ST72344xx, ST2345xx
Figure 89. Typical I in Run vs. f
DD
CPU
9
.5
1
2
4
6
8
8
7
6
5
4
3
2
1
0
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
Vdd (V)
1. Graph displays data beyond the normal operating range of 3 V - 5.5 V.
Figure 90. Typical I in Run at f
= 8 MHz
DD
CPU
9
8
7
6
5
4
3
2
1
0
140°C
90°C
25°C
-5°C
-45°C
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
Vdd (V)
1. Graph displays data beyond the normal operating range of 3 V - 5.5 V.
Figure 91. Typical I in Slow vs. f
DD
CPU
0.90
250KHz
125KHz
0.80
0.70
0.60
0.50
0.40
0.30
0.20
0.10
0.00
62KHz
2.7
3.3
4
5
6
VDD (V)
1. Graph displays data beyond the normal operating range of 3 V - 5.5 V.
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ST72344xx, ST2345xx
Electrical characteristics
Figure 92. Typical I in Wait vs. f
DD
CPU
4
3.5
3
0.5
1
2
4
2.5
2
6
8
1.5
1
0.5
0
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
Vdd (V)
1. Graph displays data beyond the normal operating range of 3 V - 5.5 V.
Figure 93. Typical I in Wait at f
= 8 MHz
CPU
DD
4
3.5
3
0.5
1
2
4
6
8
2.5
2
1.5
1
0.5
0
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
Vdd (V)
1. Graph displays data beyond the normal operating range of 3 V - 5.5 V.
Figure 94. Typical I in Slow-wait vs. f
DD
CPU
0.60
250KHz
0.50
125KHz
62KHz
0.40
0.30
0.20
0.10
0.00
2.7
3.3
4
5
6
VDD (V)
1. Graph displays data beyond the normal operating range of 3 V - 5.5 V.
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Electrical characteristics
ST72344xx, ST2345xx
Figure 95. Typical I vs. temp. at V = 5 V and f
= 8 MHz
DD
DD
CPU
6.00
5.00
4.00
3.00
2.00
1.00
0.00
RUN
WAIT
SLOW
SLOW-WAIT
-45
25
90
110
Temperature (°C)
Table 94. On-chip peripherals
Symbol Parameter
Conditions
Typ
Unit
fCPU = 4 MHz
CPU = 8 MHz
V
V
V
V
V
V
V
V
V
V
DD = 3.0 V
20
100
250
800
300
1000
100
500
250
800
IDD(16-bit timer) 16-bit Timer supply current (1)
f
DD = 5.0 V
DD = 3.0 V
DD = 5.0 V
DD = 3.0 V
DD = 5.0 V
DD = 3.0 V
DD = 5.0 V
DD = 3.0 V
DD = 5.0 V
fCPU = 4 MHz
fCPU = 8 MHz
fADC = 2 MHz
fADC = 4 MHz
fCPU = 4 MHz
IDD(SPI)
IDD(ADC)
IDD(I2C)
IDD(SCI)
SPI supply current (2)
ADC supply current when
converting (3)
μA
I2C supply current (4)
SCI supply current (5)
f
CPU = 8 MHz
fCPU = 4 MHz
fCPU = 8 MHz
1. Data based on a differential IDD measurement between reset configuration (timer stopped) and a timer
running in PWM mode at fcpu=8 MHz.
2. Data based on a differential IDD measurement between reset configuration and a permanent SPI master
communication (data sent equal to 55h).
3. Data based on a differential IDD measurement between reset configuration and continuous A/D
conversions.
4. Data based on a differential IDD measurement between reset configuration (I2C disabled) and a
permanent I2C master communication at 100 kHz (data sent equal to 55h). This measurement include the
pad toggling consumption
(4.7 kΩ external pull-up on clock and data lines).
5. Data based on a differential IDD measurement between SCI low power state (SCID=1) and a permanent
SCI data transmit sequence.
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ST72344xx, ST2345xx
Electrical characteristics
13.6
Clock and timing characteristics
Subject to general operating conditions for V , f
, and T .
DD OSC
A
Table 95. General timings
Symbol
Parameter (1)
Conditions
Min
Typ (2)
Max
Unit
2
3
12
1500
22
tCPU
ns
tc(INST) Instruction cycle time
fCPU=8 MHz
250
10
375
Interrupt reaction time (3)
tv(IT)
tCPU
µs
fCPU=8 MHz
tv(IT) = Δtc(INST) + 10
1.25
2.75
1. Guaranteed by Design. Not tested in production.
2. Data based on typical application software.
3. Time measured between interrupt event and interrupt vector fetch. Dtc(INST) is the number of tCPU cycles
needed to finish the current instruction execution.
Table 96. External clock source
Symbol
Parameter
Conditions
Min
Max
Unit
VOSC1H OSC1 input pin high level voltage
0.7xVDD VDD
V
VOSC1L
OSC1 input pin low level voltage
OSC1 high or low time (1)
VSS
15
0.3xVDD
tw(OSC1H)
tw(OSC1L)
see Figure 96
ns
tr(OSC1)
tf(OSC1)
OSC1 rise or fall time (1)
15
±1
IL
OSCx Input leakage current
VSS ≤ VIN ≤ VDD
µA
1. Data based on design simulation and/or technology characteristics, not tested in production.
Figure 96. Typical application with an external clock source
90%
V
OSC1H
OSC1L
10%
V
t
t
w(OSC1H)
t
t
w(OSC1L)
f(OSC1)
r(OSC1)
OSC2
Not connected internally
f
OSC
EXTERNAL
CLOCK SOURCE
I
L
OSC1
ST72XXX
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Electrical characteristics
ST72344xx, ST2345xx
Table 97. Auto-wakeup from Halt oscillator (AWU) characteristics
Symbol
fAWU
tRCSRT
Parameter
Conditions
Min
Typ
Max
Unit
AWU oscillator frequency
AWU oscillator startup time
50
125
250
50
kHz
µs
13.6.1
Crystal and ceramic resonator oscillators
The ST7 internal clock can be supplied with four different Crystal/Ceramic resonator
oscillators. All the information given in this paragraph is based on characterization results
with specified typical external components. In the application, the resonator and the load
capacitors have to be placed as close as possible to the oscillator pins in order to minimize
output distortion and startup stabilization time. Refer to the crystal/ceramic resonator
manufacturer for more details (frequency, package, accuracy, etc.).
Table 98. Crystal/ceramic resonator oscillator characteristics
Symbol
Parameter
Oscillator frequency (1)
Conditions
Min Max Unit
fOSC
RF
1
16
40
MHz
Feedback resistor (2)
20
kΩ
Recommended load capacitance versus
equivalent serial resistance of the
crystal or ceramic resonator (RS) (3)
CL1
CL2
See Table 99 below
pF
µA
fOSC= 2 MHz, C0 = 6 pF,
CL1 = CL2 = 68 pF
426
425
456
660
f
OSC= 4 MHz, C0 = 6 pF,
CL1 = CL2 = 68 pF
i2
OSC2 driving current
fOSC= 8 MHz, C0 = 6 pF,
CL1 = CL2 = 40 pF
fOSC= 16 MHz, C0 = 7 pF,
CL1 = CL2 = 20 pF
1. The oscillator selection can be optimized in terms of supply current using an high quality resonator with
small RS value. Refer to crystal/ceramic resonator manufacturer for more details.
2. Data based on characterisation results, not tested in production. The relatively low value of the RF
resistor, offers a good protection against issues resulting from use in a humid environment, due to the
induced leakage and the bias condition change. However, it is recommended to take this point into
account if the µC is used in tough humidity conditions.
3. For CL1 and CL2 it is recommended to use high-quality ceramic capacitors in the 5-pF to 25-pF range (typ.)
designed for high-frequency applications and selected to match the requirements of the crystal or
resonator. CL1 and CL2, are usually the same size. The crystal manufacturer typically specifies a load
capacitance which is the series combination of CL1 and CL2. PCB and MCU pin capacitance must be
included when sizing CL1 and CL2 (10 pF can be used as a rough estimate of the combined pin and board
capacitance).
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ST72344xx, ST2345xx
Electrical characteristics
Table 99. Recommended load capacitance vs. equivalent serial resistance of ceramic
resonator
Typical ceramic resonators (1)
Supply
voltage
range (V)
CL1 (2) CL2 (2)
RF
[Ω]
Rd
[Ω]
Temperature
range (°C)
fOSC
Supplier
[pF]
[pF]
Type(3)
Reference
[MHz]
2
4
SMD CSTCC2M00G56Z-R0
SMD CSTCR4M00G55Z-R0
LEAD CSTLS4M00G56Z-B0
SMD CSTCE8M00G52Z-R0
LEAD CSTLS8M00G53Z-B0
SMD CSTCE16M0V51Z-R0
LEAD CSTLS16M0X53Z-B0
(47)
(39)
(47)
(10)
(15)
(5)
(47)
(39)
(47)
(10)
(15)
(5)
Open
Open
Open
Open
Open
Open
6.8 k
0
0
0
0
0
0
0
2.7 to 5.5
Murata
–40 °C to 85 °C
8
3.3 to 5.5
3.4 to 5.5
16
(15)
(15)
1. Resonator characteristics given by the ceramic resonator manufacturer. For more information on these resonators, please
consult Murata’s web site.
2. () means load capacitor built in resonator.
3. SMD = [-R0: Plastic tape package (Ø =180mm), -B0: Bulk]
LEAD = [-B0: Bulk].
Figure 97. Typical application with a crystal or ceramic resonator
When resonator with
f
integrated capacitors
OSC
POWER DOWN
LOGIC
C
L1
OSC1
LINEAR
AMPLIFIER
FEEDBACK
LOOP
i
V
/2
2
DD
Ref
Resonator
R
F
C
L2
OSC2
ST72XXX
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Electrical characteristics
ST72344xx, ST2345xx
13.7
Memory characteristics
T = –40°C to 85°C, unless otherwise specified.
A
Table 100. RAM and hardware registers
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VRM
Data retention mode (1)
Halt mode (or reset)
1.6
V
1. Minimum VDD supply voltage without losing data stored in RAM (in Halt mode or under reset) or in
hardware registers (only in Halt mode). Guaranteed by construction, not tested in production.
Table 101. Flash program memory
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Operating voltage for Refer to operating range of
VDD
2.7
5.5
V
Flash write/erase
VDD with TA, Table 87
TA=−40 to +85°C
TA=+55°C(3)
Programming time for
1~32 bytes (1)
tprog
tRET
NRW
5
10
ms
Data retention (2)
20
years
cycles
10,000
Write erase cycles
TA=+25°C
(4)
Read / Write / Erase modes
fCPU = 8 MHz, VDD = 5.5V
2.6
mA
IDD
Supply current (5)
No Read/No Write Mode
Power down mode / Halt
100
0.1
µA
µA
0
1. Up to 32 bytes can be programmed at a time.
2. Data based on reliability test results and monitored in production.
3. The data retention time increases when the TA decreases.
4. Design target value pending full product characterization.
5. Guaranteed by Design. Not tested in production.
Table 102. EEPROM data memory
Symbol
Parameter
Conditions
Min
Typ Max Unit
Refer to operating range of
VDD with TA, Table 87:
General operating conditions
Operating voltage for
EEPROM write/erase
VDD
2.7
5.5
10
V
Programming time for
1~32 bytes
tprog
tret
TA=−40 to +85°C
TA=+55°C (2)
TA=+25°C
5
ms
Data retention(1)
20
years
cycles
300,000
NRW
Write erase cycles
(3)
1. Data based on reliability test results and monitored in production.
2. The data retention time increases when the TA decreases.
3. Design target value pending full product characterization.
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Electrical characteristics
13.8
EMC characteristics
Susceptibility tests are performed on a sample basis during product characterization.
13.8.1
Functional EMS (electromagnetic susceptibility)
Based on a simple running application on the product (toggling 2 LEDs through I/O ports),
the product is stressed by two electromagnetic events until a failure occurs (indicated by the
LEDs).
■
ESD: Electro-Static Discharge (positive and negative) is applied on all pins of the
device until a functional disturbance occurs. This test conforms with the IEC 1000-4-2
standard.
■
FTB: A Burst of Fast Transient voltage (positive and negative) is applied to V and
DD
V
through a 100 pF capacitor, until a functional disturbance occurs. This test
SS
conforms with the IEC 1000-4-4 standard.
A device reset allows normal operations to be resumed. The test results are given in the
table below based on the EMS levels and classes defined in application note AN1709.
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations:
The software flowchart must include the management of runaway conditions such as:
■
■
■
Corrupted program counter
Unexpected reset
Critical Data corruption (control registers...)
Prequalification trials:
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the RESET pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Table 103. EMS test results
Level/
Class
Symbol
Parameter
Conditions
VDD = 5 V, TA = +25 °C,
Voltage limits to be applied on any I/O pin to
induce a functional disturbance
VFESD
fOSC = 8 MHz
TBD
conforms to IEC 1000-4-2
Fast transient voltage burst limits to be
VDD = 5 V, TA = +25 °C,
VFFTB applied through 100 pF on VDD and VDD pins fOSC = 8 MHz
to induce a functional disturbance conforms to IEC 1000-4-4
TBD
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Electrical characteristics
ST72344xx, ST2345xx
13.8.2
EMI (electromagnetic interference)
Based on a simple application running on the product (toggling 2 LEDs through the I/O
ports), the product is monitored in terms of emission. This emission test is in line with the
norm SAE J 1752/3 which specifies the board and the loading of each pin.
(1)
Table 104. EMI emissions
Max vs. [fOSC/fCPU
]
Monitored
Symbol Parameter
Conditions
Unit
frequency band
8/4 MHz 16/8 MHz
0.1 MHz to 30 MHz
30 MHz to 130 MHz
130 MHz to 1 GHz
SAE EMI Level
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
V
DD=5V, TA=+25°C,
dBµV
-
SO20 package,
conforming to
SAE J 1752/3
SEMI
Peak level
1. Data based on characterization results, not tested in production.
13.8.3
Absolute maximum ratings (electrical sensitivity)
Based on two different tests (ESD and LU) using specific measurement methods, the
product is stressed in order to determine its performance in terms of electrical sensitivity.
For more details, refer to the application note AN1181.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts*(n+1) supply pin). Human body
model can be simulated. This test conforms to the JESD22-A114A/A115A standard.
Table 105. ESD absolute maximum ratings
Symbol
Ratings
Conditions
Maximum value(1) Unit
>2000
Electrostatic discharge voltage
(human body model)
VESD(HBM)
TA = +25 °C
V
1. Data based on characterization results, not tested in production.
Static latch-up (LU)
Two complementary static tests are required on 6 parts to assess the latch-up performance.
■
■
A supply overvoltage (applied to each power supply pin)
A current injection (applied to each input, output and configurable I/O pin) performed on
each sample.
This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the
application note AN1181.
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ST72344xx, ST2345xx
Electrical characteristics
Class
Table 106. Electrical sensitivities
Symbol
Parameter
Conditions
TA = +25°C
A
A
LU
Static latch-up class
TA = +85°C
13.9
I/O port pin characteristics
(1)
Table 107. General characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIL
VIH
Input low level voltage (4)
Input high level voltage (4)
VSS - 0.3
0.7xVDD
0.3xVDD
VDD + 0.3
V
Schmitt trigger voltage
hysteresis (4)
Vhys
IL
400
400
mV
µA
Input leakage current
VSS ≤ VIN ≤ VDD
±1
Static current consumption
induced by each floating
input pin (2)
IS
Floating input mode
VDD=5V
VIN=VSS
50
120
160
5
250
Weak pull-up equivalent
resistor (3)
RPU
kΩ
VDD=3V
CIO
I/O pin capacitance
pF
Output high to low level fall
time (4)
tf(IO)out
25
25
CL=50 pF
Between 10% and
90%
ns
Output low to high level rise
time (4)
tr(IO)out
tw(IT)in
External interrupt pulse
time (5)
1
tCPU
1. Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.
2. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of
the I/O for example or an external pull-up or pull-down resistor (see Figure 98). Static peak current value
taken at a fixed VIN value, based on design simulation and technology characteristics, not tested in
production. This value depends on VDD and temperature values.
3. The RPU pull-up equivalent resistor is based on a resistive transistor.
4. Data based on validation/design results.
5. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured
as an external interrupt source.
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Electrical characteristics
ST72344xx, ST2345xx
Figure 98. Two typical applications with unused I/O pin
V
ST7XXX
DD
UNUSED I/O PORT
10kΩ
10kΩ
UNUSED I/O PORT
ST7XXX
1. I/O can be left unconnected if it is configured as output (0 or 1) by the software. This has the advantage of
greater EMC robustness and lower cost.
Caution:
During normal operation the ICCCLK pin must be pulled-up, internally or externally (external
pull-up of 10k mandatory in noisy environment). This is to avoid entering ICC mode
unexpectedly during a reset.
(1)
Table 108. Output driving current
Symbol
Parameter
Conditions
IIO = +5 mA
IIO = +2 mA
IIO = +20 mA
Min
Max
1.0
Unit
Output low level voltage for a standard I/O
pin when 8 pins are sunk at same time
(see Figure 101)
0.4
(2)
VOL
Output low level voltage for a high sink I/O
pin when 4 pins are sunk at same time
(see Figure 104)
1.3
I
IO = +8 mA
0.75
Output high level voltage for an I/O pin
when 4 pins are sourced at same time
(see Figure 113)
IIO = -5 mA
IIO = -2 mA
VDD-1.5
VDD-0.8
(3)
VOH
Output low level voltage for a standard I/O
pin when 8 pins are sunk at same time
(see Figure 100)
IIO = +2 mA
IIO = +8 mA
IIO = -2 mA
0.7
0.5
VOL
(2)(4)
Output low level voltage for a high sink I/O
pin when 4 pins are sunk at same time
V
Output high level voltage for an I/O pin
when 4 pins are sourced at same time
(Figure 111)
VOH
VDD-0.8
(3)(4)
Output low level voltage for a standard I/O
pin when 8 pins are sunk at same time
(see Figure 102)
IIO = +2 mA
IIO = +8 mA
IIO = -2 mA
0.9
0.6
VOL
(2)(4)
Output low level voltage for a high sink I/O
pin when 4 pins are sunk at same time
Output high level voltage for an I/O pin
when 4 pins are sourced at same time
(see Figure 110)
VOH
VDD-0.9
(3)(4)
1. Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified.
2. The IIO current sunk must always respect the absolute maximum rating specified in Table 85: Current
characteristics and the sum of IIO (I/O ports and control pins) must not exceed IVSS
.
3. The IIO current sourced must always respect the absolute maximum rating specified in Table 85: Current
characteristics and the sum of IIO (I/O ports and control pins) must not exceed IVDD
.
4. Not tested in production, based on characterization results.
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Electrical characteristics
Figure 99. Typical V at V = 2.4 V (std I/Os)
OL
DD
1000
800
600
400
200
0
-45°C
25°C
90°C
130°C
0
2
4
6
ILOAD (mA)
Figure 100. Typical V at V = 3 V (std I/Os)
OL
DD
1000
800
600
400
200
0
-45°C
25°C
90°C
130°C
0
2
4
6
ILOAD (mA)
Figure 101. Typical V at V = 5 V (std I/Os)
OL
DD
1000
-45°C
25°C
800
600
400
200
0
90°C
130°C
0
2
4
6
ILOAD (mA)
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Electrical characteristics
ST72344xx, ST2345xx
Figure 102. Typical V at V = 2.4 V (high-sink I/Os)
OL
DD
1000
800
600
400
200
0
-45°C
25°C
90°C
130°C
0
2
4
6
8
10 12 14 16 18 20
ILOAD (mA)
Figure 103. Typical V at V = 3 V (high-sink I/Os)
OL
DD
1200
-45°C
25°C
1000
800
600
400
200
0
90°C
130°C
0
2
4
6
8
10 12 14 16 18 20
ILOAD (mA)
Figure 104. Typical V at V = 5 V (high-sink I/Os)
OL
DD
700
600
500
400
300
200
100
0
-45°C
25°C
90°C
130°C
0
2
4
6
8
10 12 14 16 18 20
ILOAD (mA)
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Electrical characteristics
Figure 105. Typical V vs. V (std I/Os, 2 mA)
OL
DD
1000
-45°C
25°C
800
600
400
200
0
90°C
130°C
2.4
2.6
2.8
Ilo (mA)
3
5
Figure 106. Typical V vs. V (std I/Os, 6 mA)
OL
DD
500
400
300
200
100
0
-45°C
25°C
90°C
130°C
2.5
3
3.5
Ilo (mA)
4
5
Figure 107. Typical V vs. V (HS I/Os, I = 8 mA)
OL
DD
IO
1000
-45°C
25°C
800
600
400
200
0
90°C
130°C
2.4
2.6
2.8
Ilo (mA)
3
5
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Electrical characteristics
ST72344xx, ST2345xx
Figure 108. Typical V vs. V (HS I/Os, I = 2 mA)
OL
DD
IO
200
160
120
80
-45°C
25°C
90°C
130°C
40
0
2.5
3
3.5
Ilo (mA)
4
5
Figure 109. Typical V vs. V (HS I/Os, I = 12 mA)
OL
DD
IO
1000
-45°C
25°C
800
600
400
200
0
90°C
130°C
2.4
2.6
2.8
Ilo (mA)
3
5
Figure 110. Typical V – v at V = 2.4 V (std I/Os)
DD
OH
DD
1400
1200
1000
800
600
400
200
0
-45°C
25°C
90°C
130°C
0
-2 -4 -6 -8 -10 -12 -14 -16 -18 -20
ILOAD (mA)
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ST72344xx, ST2345xx
Electrical characteristics
Figure 111. Typical V – V at V = 3 V (std I/Os)
DD
OH
DD
1800
-45°C
25°C
1500
1200
900
600
300
0
90°C
130°C
0
-2 -4 -6 -8 -10 -12 -14 -16 -18 -20
ILOAD (mA)
Figure 112. Typical V – V at V = 4 V (std)
DD
OH
DD
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
-45°C
25°C
90°C
130°C
0
-2 -4 -6 -8 -10 -12 -14 -16 -18 -20
ILOAD (mA)
Figure 113. Typical V – V at V = 5 V (std)
DD
OH
DD
1000
900
800
700
600
500
400
300
200
100
0
-45°C
25°C
90°C
130°C
0
-2 -4 -6 -8 -10 -12 -14 -16 -18 -20
ILOAD (mA)
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Electrical characteristics
ST72344xx, ST2345xx
Figure 114. Typical V – V vs. V (high sink)
DD
OH
DD
200
160
120
80
500
400
300
200
100
0
-45°C
25°C
90°C
130°C
-45°C
25°C
90°C
40
130°C
0
2.5
3
3.5
Ilo (mA)
4
5
2.5
3
3.5
Ilo (mA)
4
5
13.10
Control pin characteristics
13.10.1 Asynchronous RESET pin
T = -40 °C to 85 °C, unless otherwise specified.
A
Table 109. Asynchronous RESET pin characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
0.3VDD
Unit
VIL
VIH
Input low level voltage
Input high level voltage
Vss - 0.3
0.7VDD
V
VDD + 0.3
Schmitt trigger voltage
hysteresis (1)
Vhys
2
V
V
I
IO = +5 mA
0.5
0.2
40
1.0
0.4
80
VOL
Output low level voltage (2) VDD = 5 V
IIO = +2 mA
VDD = 5 V
VDD = 3 V
20
40
Pull-up equivalent resistor
RON
kΩ
(3)(1)
70
120
Generated reset pulse
duration
tw(RSTL)out
Internal reset sources
14 (1)
12 (1)
32
µs
External reset pulse hold
time (4)
th(RSTL)in
µs
ns
tg(RSTL)in Filtered glitch duration
200
1. Data based on characterization results, not tested in production.
2. The IIO current sunk must always respect the absolute maximum rating specified in Table 85: Current
characteristics and the sum of IIO (I/O ports and control pins) must not exceed IVSS
.
3. The RON pull-up equivalent resistor is based on a resistive transistor. Specified for voltages on RESET pin
between VILmax and VDD
4. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses
applied on RESET pin with a duration below th(RSTL)in can be ignored.
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Electrical characteristics
(1)(2)(3)(4)
Figure 115. RESET pin protection when LVD is enabled
VDD
ST72XXX
Optional
(note 3)
Required
R
ON
Filter
INTERNAL
RESET
EXTERNAL
RESET
0.01 µF
1 MΩ
WATCHDOG
ILLEGALOPCODE
LVD RESET
PULSE
GENERATOR
(5)
1. The reset network protects the device against parasitic resets.
- The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad.
Otherwise the device can be damaged when the ST7 generates an internal reset (LVD or watchdog).
- Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin
can go below the VIL max. level specified in Section 13.10.1. Otherwise the reset will not be taken into
account internally.
- Because the reset circuit is designed to allow the internal reset to be output in the RESET pin, the user
must ensure that the current sunk on the RESET pin is less than the absolute maximum value specified
for IINJ(RESET) in Table 85.
2. When the LVD is enabled, it is recommended not to connect a pull-up resistor or capacitor. A 10nF pull-
down capacitor is required to filter noise on the reset line.
3. In case a capacitive power supply is used, it is recommended to connect a 1MΩ pull-down resistor to the
RESET pin to discharge any residual voltage induced by the capacitive effect of the power supply (this will
add 5µA to the power consumption of the MCU).
4. Tips when using the LVD:
1. Check that all recommendations related to the reset circuit have been applied (see notes above)
2. Check that the power supply is properly decoupled (100nF + 10µF close to the MCU). Refer to AN1709
and AN2017. If this cannot be done, it is recommended to put a 100nF + 1MΩ pull-down on the RESET
pin.
3. The capacitors connected on the RESET pin and also the power supply are key to avoid any startup
marginality. In most cases, steps 1 and 2 above are sufficient for a robust solution. Otherwise: replace
10nF pull-down on the RESET pin with a 5µF to 20µF capacitor.”
5. Please refer to Section 12.2.1: Illegal opcode reset for more details on illegal opcode reset conditions.
(1)
Figure 116. RESET pin protection when LVD is disabled
VDD
ST72XXX
R
ON
Filter
INTERNAL
RESET
USER
EXTERNAL
RESET
CIRCUIT
0.01 µF
WATCHDOG
PULSE
GENERATOR
(2)
ILLEGALOPCODE
Required
1. The reset network protects the device against parasitic resets.
- The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad.
Otherwise the device can be damaged when the ST7 generates an internal reset (LVD or watchdog).
- Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin
can go below the VIL max. level specified in Section 13.10.1. Otherwise the reset will not be taken into
account internally.
- Because the reset circuit is designed to allow the internal reset to be output in the RESET pin, the user
must ensure that the current sunk on the RESET pin is less than the absolute maximum value specified
for IINJ(RESET) in Table 85.
2. Please refer to Section 12.2.1: Illegal opcode reset for more details on illegal opcode reset conditions.
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Electrical characteristics
ST72344xx, ST2345xx
13.11
Communication interface characteristics
2
13.11.1 I C and I²C3SNS interfaces
Subject to general operating conditions for V , f
, and T unless otherwise specified.
A
DD OSC
Refer to I/O port characteristics for more details on the input/output alternate function
2
characteristics (SDAI and SCLI). The ST7 I C and I2C3SNS interfaces meet the electrical
2
and timing requirements of the Standard I C communication protocol.
T = -40°C to 85°C, unless otherwise specified.
A
2
Table 110. I C and I²C3SNS interfaces characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
CPU=4 MHz to 8 MHz (1)
,
fSCL
I²C SCL frequency
400
400
kHz
kHz
f
fSCL3SNS I²C3SNS SCL frequency (2)
VDD= 2.7 V to 5.5 V
1. The I2C and I2C3SNS interfaces will not function below the minimum clock speed of 4 MHz.
2. Not tested in production within the whole operating range. Guaranteed by design/validation test results.
The following table gives the values to be written in the I2CCCR register to obtain the
2
required I C SCL line frequency.
2
(1)
Table 111. SCL frequency table (multimaster I C interface)
I2CCCR value
f
CPU = 4 MHz.
VDD = 5 V
fCPU = 8 MHz.
fSCL
V
DD = 3.3 V
VDD = 3.3 V
VDD = 5 V
RP=3.3kΩ RP=4.7kΩ RP=3.3kΩ RP=4.7kΩ RP=3.3kΩ RP=4.7kΩ RP=3.3kΩ RP=4.7kΩ
400
300
200
100
50
NA
NA
NA
NA
NA
NA
NA
NA
84h
86h
8Ah
25h
4Bh
FFh
84h
86h
8Ah
24h
4Ch
FFh
84h
85h
8Bh
28h
53h
FFh
84h
87h
8Ch
28h
54h
FFh
84h
11h
25h
60h
84h
10h
24h
5Fh
84h
11h
25h
60h
84h
11h
26h
62h
20
1.
R
P = External pull-up resistance, fSCL = I2C speed, NA = Not achievable.
Note:
For speeds around 200 kHz, achieved speed can have ±5% tolerance; for other speed
ranges, achieved speed can have ±2% tolerance.
The above variations depend on the accuracy of the external components used.
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Electrical characteristics
13.12
10-bit ADC characteristics
T = -40 °C to 85 °C, unless otherwise specified
A
Table 112. ADC accuracy
Symbol
Parameter
Conditions (1)(2)
fCPU = 8 MHz,
fADC = 4 MHz
RAIN < 10κΩ,
Typ
Max (3)
Unit
|ET|
|EO|
|EG|
|ED|
Total unadjusted error
Offset error
4
-1
-2
3
8
-2
-4
6
LSB
Gain Error
VDD = 2.7 V to 5.5 V
Differential linearity error
1. Data based on characterization results over the whole temperature range.
2. ADC accuracy vs. negative injection current: Injecting negative current on any of the analog input pins may
reduce the accuracy of the conversion being performed on another analog input.
The effect of negative injection current on robust pins is specified in Section 13.10
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 13.9 does not
affect the ADC accuracy.
3. Data based on characterization results, monitored in production to guarantee 99.73% within ± max value
from -40 °C to +125 °C (± 3σ distribution limits).
Figure 117. ADC accuracy characteristics
Digital Result ADCDR
E
G
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line
1023
1022
1021
V
– V
DD
SS
1LSB
= -------------------------------
IDEAL
1024
(2)
E =Total Unadjusted Error: maximum deviation
T
E
between the actual and the ideal transfer curves.
T
(3)
7
6
5
4
3
2
1
E =Offset Error: deviation between the first actual
O
transition and the first ideal one.
(1)
E =Gain Error: deviation between the last ideal
G
transition and the last actual one.
E
O
E
L
E =Differential Linearity Error: maximum deviation
D
between actual steps and the ideal one.
E =Integral Linearity Error: maximum deviation
L
E
between any actual transition and the end point
correlation line.
D
1 LSB
IDEAL
V
(LSB
)
in
IDEAL
0
1
2
3
4
5
6
7
1021 1022 1023 1024
V
V
DD
SS
ai15169
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Electrical characteristics
ST72344xx, ST2345xx
Subject to general operating condition for V , f
, and T unless otherwise specified.
A
DD OSC
Table 113. ADC characteristics
Symbol
Parameter
Conditions
Min
Typ (1)
Max
Unit
fADC
VAIN
ADC clock frequency
0.4
4
MHz
V
Conversion voltage range (2)
VSSA
VDDA
10 (3)
RAIN
CADC
External input resistor
kΩ
pF
Internal sample and hold capacitor
6
Stabilization time after ADC
enable
tSTAB
0 (4)
3.5
µs
fCPU = 8 MHz,
fADC = 4 MHz
Conversion time (Sample+Hold)
tADC
– Sample capacitor loading time
– Hold conversion time
4
10
1/fADC
mA
Analog Part
Digital Part
1
IADC
0.2
1. Unless otherwise specified, typical data are based on TA= 25 °C and VDD-VSS= 5 V. They are given only
as design guidelines and are not tested.
2. When VDDA and VSSA pins are not available on the pinout, the ADC refers to VDD and VSS.
3. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than
10 kΩ). Data based on characterization results, not tested in production.
4. The stabilization time of the AD converter is masked by the first tLOAD. The first conversion after the enable
is then always valid.
Figure 118. Typical A/D converter application
V
DD
ST72XXX
V
T
0.6 V
R
AIN
2 kΩ (max)
AINx
10-Bit A/D
V
AIN
Conversion
C
V
0.6 V
AIN
T
I
C
L
ADC
6 pF
±1 μA
Note:
1
2
C
represents the capacitance of the PCB (dependent on soldering and PCB layout
PARASITIC
quality) plus the pad capacitance (3 pF). A high C
accuracy. To remedy this, f
value will downgrade conversion
PARASITIC
should be reduced.
ADC
This graph shows that depending on the input signal variation (f ), C
can be increased
AIN
AIN
for stabilization time and decreased to allow the use of a larger serial resistor (R
.
AIN)
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Package characteristics
14
Package characteristics
14.1
ECOPACK
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
14.2
Package mechanical data
Figure 119. 32-pin low profile quad flat package (7 x 7 mm) outline
D
D1
A
A2
A1
e
b
E
E1
c
L1
L
h
1. Drawing is not to scale.
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Package characteristics
ST72344xx, ST2345xx
Table 114. 32-pin low profile quad flat package (7 x 7 mm) mechanical data
mm
Typ
inches (1)
Dim.
Min
Max
Min
Typ
Max
A
A1
A2
b
1.60
0.15
1.45
0.45
0.20
0.0630
0.0059
0.0571
0.0177
0.0079
0.05
1.35
0.30
0.09
0.0020
0.0531
0.0118
0.0035
1.40
0.37
0.0551
0.0146
C
D
9.00
7.00
9.00
7.00
0.80
3.5°
0.60
1.00
0.3543
0.2756
0.3543
0.2756
0.0315
3.5°
D1
E
E1
e
θ
0°
7°
0°
7°
L
0.45
0.75
0.0177
0.0236
0.0394
0.0295
L1
N (number of pins)
32
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 120. 40-lead very thin fine pitch quad flat no-lead package outline
A
SEATING
A3
PLANE
A1
D
D2
E2
E
PIN #1 ID TYPE C
RADIUS
2
1
L
e
b
1. Drawing is not to scale.
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Package characteristics
Table 115. 40-lead very thin fine pitch quad flat no-lead package mechanical data
mm
Typ
inches (1)
Dim.
Min
Max
Min
Typ
Max
A
A1
A2
A3
b
0.80
0.90
0.02
0.65
0.20
0.25
6.00
2.9
1.00
0.05
1.00
0.0315
0.0354
0.0008
0.0256
0.0079
0.0098
0.2362
0.1142
0.2362
0.1142
0.0197
0.0157
0.0394
0.0020
0.0394
0.18
5.85
2.75
5.85
2.75
0.30
6.15
3.05
6.15
3.05
0.0071
0.2303
0.1083
0.2303
0.1083
0.0118
0.2421
0.1201
0.2421
0.1201
D
D2
E
6
E2
e
2.9
0.50
0.40
L
0.30
0.50
0.0118
Number of pins
40
0.0197
N
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 121. 44-pin low profile quad flat package outline
A
D
D1
A2
A1
b
e
E1
E
c
L1
L
h
1. Drawing is not to scale.
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Package characteristics
ST72344xx, ST2345xx
Table 116. 44-pin low profile quad flat package mechanical data
mm
Typ
inches (1)
Dim.
Min
Max
Min
Typ
Max
A
A1
A2
b
1.60
0.15
1.45
0.45
0.20
0.0630
0.0059
0.0571
0.0177
0.0079
0.05
1.35
0.30
0.09
0.0020
0.0531
0.0118
0.0035
1.40
0.37
0.0551
0.0146
C
D
12.00
10.00
12.00
10.00
0.80
0.4724
0.3937
0.4724
0.3937
0.0315
3.5°
D1
E
E1
e
θ
0°
3.5°
7°
0°
7°
L
0.45
0.60
0.75
0.0177
0.0236
0.0394
0.0295
L1
1.00
Number of pins
44
N
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 122. 48-pin low profile quad flat package outline
D
A
D1
A2
A1
b
e
E1
E
c
L1
L
θ
1. Drawing is not to scale.
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ST72344xx, ST2345xx
Package characteristics
Table 117. 48-pin low profile quad flat package mechanical data
mm
Typ
inches (1)
Dim.
Min
Max
Min
Typ
Max
A
A1
A2
b
1.60
0.15
1.45
0.27
0.20
0.0630
0.0059
0.0571
0.0106
0.0079
0.05
1.35
0.17
0.09
0.0020
0.0531
0.0067
0.0035
1.40
0.22
0.0551
0.0087
C
D
9.00
7.00
9.00
7.00
0.50
3.5°
0.60
1.00
0.3543
0.2756
0.3543
0.2756
0.0197
3.5°
D1
E
E1
e
θ
0°
7°
0°
7°
L
0.45
0.75
0.0177
0.0236
0.0394
0.0295
L1
Number of pins
48
N
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Table 118. Thermal characteristics
Symbol
Ratings
Value (1)
Unit
LQFP32
60
54
RthJA
Package thermal resistance (junction to ambient) LQFP44
LQFP48
°C/W
°C
73
TJmax Maximum junction temperature (2)
PDmax Power dissipation (3)
150
415
460
340
LQFP32
LQFP44
LQFP48
mW
1. Values given for a 4-layer board. PDmax computed for TA = 125 °C.
2. The maximum chip-junction temperature is based on technology characteristics.
3. The maximum power dissipation is obtained from the formula PD = (TJ -TA) / RthJA
.
The power dissipation of an application can be defined by the user with the formula: PD=PINT+PPORT
where PINT is the chip internal power (IDD x VDD) and PPORT is the port power dissipation depending on the
ports used in the application.
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Device configuration and ordering information
ST72344xx, ST2345xx
15
Device configuration and ordering information
Each device is available for production in user programmable versions (Flash).
ST72F34x Flash devices are shipped to customers with a default content (FFh). This implies
that Flash devices have to be configured by the customer using the Option Bytes.
15.1
Option bytes
The four option bytes allow the hardware configuration of the microcontroller to be selected.
The option bytes can be accessed only in programming mode (for example using a standard
ST7 programming tool).
15.1.1
Option byte 0
OPT7 = WDG Halt Watchdog Reset on Halt
This option bit determines if a reset is generated when entering Halt mode while the
Watchdog is active.
0: No Reset generation when entering Halt mode
1: Reset generation when entering Halt mode
OPT6 = WDG SW Hardware or Software Watchdog
This option bit selects the watchdog type.
0: Hardware (watchdog always enabled)
1: Software (watchdog to be enabled by software)
OPT5:4 = LVD[1:0] Low voltage detection selection
These option bits enable the LVD block with a selected threshold as shown in
Table 119.
Table 119. LVD threshold configuration
Configuration
LVD1
LVD0
LVD Off
1
1
0
0
1
0
1
0
Highest voltage threshold ( 4.1V)
Medium voltage threshold ( 3.5V)
Lowest voltage threshold ( 2.8V)
OPT3:2 = SEC[1:0] Sector 0 size definition
These option bits indicate the size of sector 0 according to the following table.
Table 120. Size of sector 0
Sector 0 size
SEC1
SEC0
0.5k
1k
0
0
0
1
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Device configuration and ordering information
Table 120. Size of sector 0
Sector 0 size
SEC1
SEC0
2k
4k
1
1
0
1
OPT1 = FMP_R Read-out protection
Readout protection, when selected provides a protection against program memory
content extraction and against write access to Flash memory. Erasing the option bytes
when the FMP_R option is selected will cause the whole memory to be erased first and
the device can be reprogrammed. Refer to the ST7 Flash Programming Reference
Manual and Section 4.5 for more details.
0: Read-out protection off
1: Read-out protection on
OPT0 = FMP_W Flash write protection
This option indicates if the Flash program memory is write protected.
Warning: When this option is selected, the program memory (and the option bit itself)
can never be erased or programmed again.
0: Write protection off
1: Write protection on
Option byte 0
Option byte 1
7
1
6
1
5
1
4
1
3
2
1
1
0
0
0
7
1
6
1
5
1
4
3
2
1
1
1
0
1
Default
value
1
1
0
15.1.2
Option byte 1
OPT7 = RSTC reset clock cycle selection
This option bit selects the number of CPU cycles inserted during the reset phase and
when exiting Halt mode. For resonator oscillators, it is advised to select 4096 due to the
long crystal stabilization time.
0: Reset phase with 4096 CPU cycles
1: Reset phase with 256 CPU cycles
OPT6:4 = OSCRANGE[2:0] Oscillator range
When the internal RC oscillator is not selected (Option OSC=1), these option bits
select the range of the resonator oscillator current source or the external clock source.
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OSCRANGE
Table 121. Selection of the resonator oscillator range
2
1
0
LP
1~2 MHz
2~4 MHz
4~8 MHz
8~16 MHz
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
MP
MS
HS
Typical frequency range
with Resonator
Reserved
External clock
OPT3 = OSC RC Oscillator selection
0: RC oscillator on
1: RC oscillator off
OPT2 = DIV2EN PLL Divide by 2 enable
0: PLL division by 2 enabled
1: PLL division by 2 disabled
Note:
DIV2EN must be kept disabled when PLLx4 is enabled.
OPT1 = PLLx4x8 PLL Factor selection
0: PLLx4
1: PLLx8
OPT0 = PLLOFF PLL disable
0: PLL enabled
1: PLL disabled (by-passed)
These option bits must be configured as described in Table 122 depending on the voltage
range and the expected CPU frequency.
Table 122. List of valid option combinations
Option bits
Target ratio
VDD
DIV2 EN
PLL OFF
PLL x4x8
x4 (1)
2.7 V - 3.65 V
3.3 V - 5.5 V
x
0
1
0
0
0
0
1
1
x4
x8
1. For a target ratio of x4 between 3.3V - 3.65V, this is the recommended configuration.
15.1.3
Option byte 2
Note:
OPT7:0 = Reserved. Must be kept at 1.
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Device configuration and ordering information
15.1.4
Option byte 3
OPT7:6 = PKG1:0 Package selection
These option bits select the package.
Table 123. Package selection
Version
Selected package
PKG 1
PKG 0
K
S
C
LQFP32
LQFP44
LQFP48
0
0
1
0
1
x
OPT5 = I2C3S I2C3SNS selection
0: I2C3SNS selected
1: I2C3SNS not selected
OPT4:0 = Reserved. Must be kept at 1.
Table 124. Option byte default values
Option byte 2
Option byte 3
7
1
6
1
5
1
4
3
2
1
1
1
0
1
7
x
6
x
5
x
4
3
2
1
0
1
Reserved
Reserved
1 1
Default
value
1
1
1
1
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15.2
Device ordering information
Figure 123. ST7234x ordering information scheme
Example:
ST72
F
34x
K
2
T
6
TR
Product class
ST7 microcontroller
Version
Flash
Sub-family
344, 345
No. of pins
K = 32 pins
S = 44 pins
C = 48 pins
Memory size
2 = 8K
4 = 16K
Package
T = LQFP
Temperature range
6 = -40 ˚C to 85 ˚C
Shipping
TR = Tape and Reel
No character = Tray
ai15170
For a list of available options (e.g. memory size, package) and orderable part numbers or for
further information on any aspect of this device, please contact the nearest ST sales office.
15.3
Development tools
Development tools for the ST7 microcontrollers include a complete range of hardware
systems and software tools from STMicroelectronics and third-party tool suppliers. The
range of tools includes solutions to help you evaluate microcontroller peripherals, develop
and debug your application, and program your microcontrollers.
15.3.1
Starter kits
ST offers complete, affordable starter kits. Starter kits are complete, affordable
hardware/software tool packages that include features and samples to help you quickly start
developing your application.
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15.3.2
Development and debugging tools
Application development for ST7 is supported by fully optimizing C Compilers and the ST7
Assembler-Linker toolchain, which are all seamlessly integrated in the ST7 integrated
development environments in order to facilitate the debugging and fine-tuning of your
application. The Cosmic C Compiler is available in a free version that outputs up to
16 KBytes of code.
The range of hardware tools includes full-featured ST7-EMU3 series emulators and the
low-cost RLink in-circuit debugger/programmer. These tools are supported by the ST7
Toolset from STMicroelectronics, which includes the STVD7 integrated development
environment (IDE) with high-level language debugger, editor, project manager and
integrated programming interface.
15.3.3
Programming tools
During the development cycle, the ST7-EMU3 series emulators and the RLink provide in-
circuit programming capability for programming the Flash microcontroller on your application
board.
ST also provides a low-cost dedicated in-circuit programmer, the ST7-STICK, as well as
ST7 Socket Boards which provide all the sockets required for programming any of the
devices in a specific ST7 sub-family on a platform that can be used with any tool with in-
circuit programming capability for ST7.
For production programming of ST7 devices, ST’s third-party tool partners also provide a
complete range of gang and automated programming solutions, which are ready to integrate
into your production environment.
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Device configuration and ordering information
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15.3.4
Order codes for ST72F34x development tools
Table 125. Development tool order codes
Programming tool
MCU
Starter kit
Emulator
In-circuitdebugger/
programmer
Dedicated
programmer
ST7SB20J/xx (4)(6)
ST72F344
ST72F345
ST72F34x-
SK/RAIS (1)
ST7MDT40-EMU3
STX-RLINK (3)
ST7SB40-QP48/xx
(2)
ST7-STICK (4)(5)
(4)(7)
1. USB connection to PC
2. ST7MDT40-EMU3 order code is discontinued
3. RLink with ST7 tool set
4. Add suffix /EU, /UK or /US for the power supply for your region
5. Parallel port connection to PC
6. Only available for LQFP32 and LQFP44 packages
7. Only available for LQFP48 package
For additional ordering codes for spare parts and accessories, refer to the online product
selector at www.st.com/mcu.
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Known limitations
16
Known limitations
16.1
External interrupt missed
To avoid any risk if generating a parasitic interrupt, the edge detector is automatically
disabled for one clock cycle during an access to either DDR and OR. Any input signal edge
during this period will not be detected and will not generate an interrupt.
This case can typically occur if the application refreshes the port configuration registers at
intervals during runtime.
16.1.1
Workaround
The workaround is based on software checking the level on the interrupt pin before and after
writing to the PxOR or PxDDR registers. If there is a level change (depending on the
sensitivity programmed for this pin), the interrupt routine is invoked using the call instruction
with three extra PUSH instructions before executing the interrupt routine (this is to make the
call compatible with the IRET instruction at the end of the interrupt service routine).
But detection of the level change does not make sure that edge occurs during the critical 1
cycle duration and the interrupt has been missed. This may lead to occurrence of same
interrupt twice (one hardware and another with software call).
To avoid this, a semaphore is set to '1' before checking the level change. The semaphore is
changed to level '0' inside the interrupt routine. When a level change is detected, the
semaphore status is checked and if it is '1' this means that the last interrupt has been
missed. In this case, the interrupt routine is invoked with the call instruction.
There is another possible case i.e. if writing to PxOR or PxDDR is done with global
interrupts disabled (interrupt mask bit set). In this case, the semaphore is changed to '1'
when the level change is detected. Detecting a missed interrupt is done after the global
interrupts are enabled (interrupt mask bit reset) and by checking the status of the
semaphore. If it is '1' this means that the last interrupt was missed and the interrupt routine
is invoked with the call instruction.
To implement the workaround, the following software sequence is to be followed for writing
into the PxOR/PxDDR registers. The example is for Port PF1 with falling edge interrupt
sensitivity. The software sequence is given for both cases (global interrupt
disabled/enabled).
Case 1: Writing to PxOR or PxDDR with global interrupts enabled:
LD A,#01
LD sema,A; set the semaphore to '1'
LD A,PFDR
AND A,#02
LD X,A; store the level before writing to PxOR/PxDDR
LD A,#$90
LD PFDDR,A; Write to PFDDR
LD A,#$ff
LD PFOR,A; Write to PFOR
LD A,PFDR
AND A,#02
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LD Y,A; store the level after writing to PxOR/PxDDR
LD A,X; check for falling edge
cp A,#02
jrne OUT
TNZ Y
jrne OUT
LD A,sema; check the semaphore status if edge is detected
CP A,#01
jrne OUT
call call_routine; call the interrupt routine
OUT:LD A,#00
LD sema,A
.call_routine; entry to call_routine
PUSH A
PUSH X
PUSH CC
.ext1_rt; entry to interrupt routine
LD A,#00
LD sema,A
IRET
Case 2: Writing to PxOR or PxDDR with global interrupts disabled:
SIM; set the interrupt mask
LD A,PFDR
AND A,#$02
LD X,A; store the level before writing to PxOR/PxDDR
LD A,#$90
LD PFDDR,A; Write into PFDDR
LD A,#$ff
LD PFOR,A; Write to PFOR
LD A,PFDR
AND A,#$02
LD Y,A; store the level after writing to PxOR/PxDDR
LD A,X; check for falling edge
cp A,#$02
jrne OUT
TNZ Y
jrne OUT
LD A,#$01
LD sema,A; set the semaphore to '1' if edge is detected
RIM; reset the interrupt mask
LD A,sema; check the semaphore status
CP A,#$01
jrne OUT
call call_routine; call the interrupt routine
RIM
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Known limitations
OUT: RIM
JP while_loop
.call_routine; entry to call_routine
PUSH A
PUSH X
PUSH CC
.ext1_rt; entry to interrupt routine
LD A,#$00
LD sema,A
IRET
16.1.2
Unexpected reset fetch
If an interrupt request occurs while a “POP CC” instruction is executed, the interrupt
controller does not recognise the source of the interrupt and, by default, passes the reset
vector address to the CPU.
Workaround
To solve this issue, a “POP CC” instruction must always be preceded by a “SIM” instruction.
16.2
Clearing active interrupts outside interrupt routine
When an active interrupt request occurs at the same time as the related flag is being
cleared, an unwanted reset may occur.
Note:
Clearing the related interrupt mask will not generate an unwanted reset.
Concurrent interrupt context
The symptom does not occur when the interrupts are handled normally, i.e. when:
■
■
■
The interrupt flag is cleared within its own interrupt routine
The interrupt flag is cleared within any interrupt routine
The interrupt flag is cleared in any part of the code while this interrupt is disabled
If these conditions are not met, the symptom can be avoided by implementing the following
sequence:
Perform SIM and RIM operation before and after resetting an active interrupt request.
Example:
SIM
reset interrupt flag
RIM
Nested interrupt context:
The symptom does not occur when the interrupts are handled normally, i.e. when:
■
■
The interrupt flag is cleared within its own interrupt routine
The interrupt flag is cleared within any interrupt routine with higher or identical priority
level
■
The interrupt flag is cleared in any part of the code while this interrupt is disabled
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If these conditions are not met, the symptom can be avoided by implementing the following
sequence:
PUSH CC
SIM
reset interrupt flag
POP CC
16.3
16-bit timer PWM mode
In PWM mode, the first PWM pulse is missed after writing the value FFFCh in the OC1R
register (OC1HR, OC1LR). It leads to either full or no PWM during a period, depending on
the OLVL1 and OLVL2 settings.
16.4
TIMD set simultaneously with OC interrupt
If the 16-bit timer is disabled at the same time the output compare event occurs then output
compare flag gets locked and cannot be cleared before the timer is enabled again.
16.4.1
16.4.2
Impact on the application
If output compare interrupt is enabled, then the output compare flag cannot be cleared in the
timer interrupt routine. Consequently, the interrupt service routine is called repeatedly.
Workaround
Disable the timer interrupt before disabling the timer. Again while enabling, first enable the
timer then the timer interrupts.
Perform the following to disable the timer:
TACR1 = 0x00h; // Disable the compare interrupt
TACSR |= 0x40; // Disable the timer
Perform the following to enable the timer again:
TACSR &= ~0x40; // Enable the timer
TACR1 = 0x40; // Enable the compare interrupt
16.5
SCI wrong break duration
16.5.1
Description
A single break character is sent by setting and resetting the SBK bit in the SCICR2 register.
In some cases, the break character may have a longer duration than expected:
■
■
20 bits instead of 10 bits if M=0
22 bits instead of 11 bits if M=1
In the same way, as long as the SBK bit is set, break characters are sent to the TDO pin.
This may lead to generate one break more than expected.
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Known limitations
16.5.2
Occurrence
The occurrence of the problem is random and proportional to the baud rate. With a transmit
frequency of 19200 baud (f
occurrence is around 1%.
=8 MHz and SCIBRR=0xC9), the wrong break duration
CPU
16.5.3
Workaround
If this wrong duration is not compliant with the communication protocol in the application,
software can request that an Idle line be generated before the break character. In this case,
the break duration is always correct assuming the application is not doing anything between
the idle and the break. This can be ensured by temporarily disabling interrupts.
The exact sequence is:
■
■
■
■
Disable interrupts
Reset and Set TE (IDLE request)
Set and Reset SBK (Break request)
Re-enable interrupts
16.6
Random read operations not supported with the standard I²C
16.6.1
Description
The standard I²C peripheral is not fully compliant with random read capabilities (only the
I2C3SNS interface supports these capabilities). If the master sends a Restart condition, a
bus error is generated on the ST7 device in slave mode.
16.6.2
16.6.3
Occurrence
The occurrence of the problem is random.
Workaround
The Restart condition is not allowed. The master must not send a Restart condition. It must
send a Stop condition before a second Start (each Start has to be preceded by a Stop).
16.7
Programming of EEPROM data
16.7.1
Description
In user mode, when programming EEPROM data memory, the read access to the program
memory between E000h and FFFFh can be corrupted.
16.7.2
Impact on application
The EEPROM programming routine must be located outside this program memory area.
Any access to the interrupt vector table can result in an unexpected code being executed, so
the interrupts must be masked.
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Known limitations
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16.7.3
Workaround
The sequence to program the EEPROM data (refer to Section 5.3) must be executed within
C000h-DFFFh area or from the RAM. It is as follows:
set E2LAT bit
write up to 32 bytes in E2PROM area
SIM ; to disable the interrupts
set E2PGM bit
wait for E2PGM=0
RIM ; to enable the interrupts
return to the program memory
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Revision history
17
Revision history
Table 126. Document revision history
Date
Revision
Changes
29-April-2006
1
First release on internet
Removed references to BGA56 and QFN40 packages
TQFP package naming changed to LQFP (Low-profile Quad Flat)
Changed number of I/O ports on first page
PDVD (Power Down Voltage Detector) replaced by AVD (Auxiliary
Voltage Detector)
Modified note 3 to Table 4 on page 24
Added PF4 to Figure 3 on page 18 and Figure 4 on page 19
Modified Memory access on page 31
Modified Figure 8, Figure 9 on page 33 and Figure 10 on page 34
Changed RCCR table in Section 7.3 on page 43 (fRC=1 MHz)
References to PDVDF, PDVDIE corrected to AVDF, AVDIE:
Section 7.6.2 on page 49
Current characteristics Table 85 on page 201 updated
General operating conditions table updated, Table 87 on page 202
Data updated in Table 88 on page 202, note replaced
Table modified in Table 89 on page 203
Notes adjusted for table in Table 90 on page 203
Modified Section 13.4 on page 204 (for VDD=5V)
Table in Table 93 on page 205 modified
23-Oct-2006
2
Updated Table 94 on page 208
Added Table 96 on page 209 and Figure 96 on page 209
Table in Table 101 on page 212 modified
Absolute maximum ratings and electrical sensitivity table updated,
Section 13.8.3 on page 214
Added note 1 to VIL and VIH in Table 107 on page 215
Table in Table 108 on page 216 modified (for VDD= 3.3V and VDD=2.7V)
Modified graphs in Table 108 on page 216
tg(RSTL)in updated in Table 13.10 on page 222
Updated Table 111 on page 224
Updated Table 118 on page 231
Modified default values for option byte 2 and 3 on Option byte 2 on
page 234
Added option list on Option byte 2 on page 234
Added Section 15.3: Development tools on page 236
Added known limitations: Section 16.6: In-application programming on
page 242, Section 16.7: Programming of EEPROM data on page 243,
and Section 16.8: Flash write/erase protection on page 243
Modified Section 16.7 on page 243
Changed status of the document (datasheet instead of preliminary data)
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Table 126. Document revision history (continued)
Date
Revision
Changes
Document reformatted
Title modified
Removed references to ST72340 devices and FASTROM devices
Modified device summary on first page
Added note 1 and note 3 to Table 3 on page 20 and removed note on
ICCDATA and ICCCLK
Added note 5 and “caution” to Section 4.4 on page 28
Added one caution to Section 7.2 on page 42
Modified note in Section 7.3.3 on page 45,
Added caution to Section 7.5 on page 46
Added one caution to Section 7.6.2 on page 49
Modified Figure 24 on page 60
Modified note 3 in Output compare on page 99
Added note to Section 11.8.1 on page 185
Modified table in Table 84 on page 200
22-Sep-2008
3
Modified Section 13.4 on page 204: modified note 1 and added fRC
values for VDD = 3 V
Modified Table 94 on page 208
Modified Section 13.6.1 on page 210
Modified EMC characteristics on page 213 and removed references to
DLU in Absolute maximum ratings (electrical sensitivity) on page 214
Modified Section 13.10.1 on page 222
Added note 2 to Section 13.11.1 on page 224
Added Section 16.4 on page 242 Section 16.4 on page 242
Modified Section 14 on page 227 (values in inches rounded to 4 decimal
digits instead of 3 decimal digits)
Modified Section 15 on page 232, Device ordering information on
page 236
Removed option list.
"Flash write/erase protection” and “In-application programming”
removed in Section 16: Known limitations on page 239 (limitations
corrected in the silicon revision now in production).
11-Dec-2008
4
Updated Section 14.1: ECOPACK on page 227
Modified title of Table 2 on page 16
15-Jun-2009
28-Jun-2012
5
6
Added Section 16.6: Random read operations not supported with the
standard I²C on page 243
Note (2) added to Table 125: Development tool order codes.
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