ST72521BAR9TC/XXXX [STMICROELECTRONICS]
8-BIT, MROM, 8MHz, MICROCONTROLLER, PQFP64, 10 X 10 MM, ROHS COMPLIANT, LQFP-64;
| 型号： | ST72521BAR9TC/XXXX |
| 厂家： | 
ST |
| 描述： | 8-BIT, MROM, 8MHz, MICROCONTROLLER, PQFP64, 10 X 10 MM, ROHS COMPLIANT, LQFP-64 闪存 |
| 文件： | 总215页 (文件大小：4598K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ST72F521, ST72521B
80/64-PIN 8-BIT MCU WITH 32 TO 60K FLASH/ROM, ADC,
FIVE TIMERS, SPI, SCI, I2C, CAN INTERFACE
■ Memories
– 32K to 60K dual voltage High Density Flash
(HDFlash) or ROM with read-out protection
capability. In-Application Programming and
In-Circuit Programming for HDFlash devices
– 1K to 2K RAM
– HDFlash endurance: 100 cycles, data reten-
tion: 20 years at 55°C
■ Clock, Reset And Supply Management
TQFP64
14 x 14
– Enhanced low voltage supervisor (LVD) for
main supply and auxiliary voltage detector
(AVD) with interrupt capability
TQFP64
10 x 10
TQFP80
14 x 14
– Clock sources: crystal/ceramic resonator os-
cillators, internal RC oscillator and bypass for
external clock
– PLL for 2x frequency multiplication
– Four power saving modes: Halt, Active-Halt,
■ 4 Communications Interfaces
Wait and Slow
– SPI synchronous serial interface
– SCI asynchronous serial interface
■ Interrupt Management
– Nested interrupt controller
– 14 interrupt vectors plus TRAP and RESET
– Top Level Interrupt (TLI) pin
2
– I C multimaster interface
(SMbus V1.1 compliant)
– CAN interface (2.0B Passive)
■ Analog periperal (low current coupling)
– 15 external interrupt lines (on 4 vectors)
■ Up to 64 I/O Ports
– 10-bit ADC with 16 input robust input ports
– 48 multifunctional bidirectional I/O lines
– 34 alternate function lines
– 16 high sink outputs
■ Instruction Set
– 8-bit Data Manipulation
– 63 Basic Instructions
– 17 main Addressing Modes
– 8 x 8 Unsigned Multiply Instruction
■ Development Tools
■ 5 Timers
– Main Clock Controller with: Real time base,
Beep and Clock-out capabilities
– Configurable watchdog timer
– Two 16-bit timers with: 2 input captures, 2 out-
put compares, external clock input on one tim-
er, PWM and pulse generator modes
– 8-bit PWM Auto-Reload timer with: 2 input
captures, 4 PWM outputs, output compare
and time base interrupt, external clock with
event detector
– Full hardware/software development package
– In-Circuit Testing capability
Device Summary
Features
Program memory - bytes
RAM (stack) - bytes
Operating Voltage
Temp. Range
ST72F521(M/R/AR)9
Flash 60K
ST72F521(R/AR)6
Flash 32K
ST72521B(M/R/AR)9
ROM 60K
ST72521B(R/AR)6
ROM 32K
2048 (256)
1024 (256)
2048 (256)
1024 (256)
3.8V to 5.5V
up to -40°C to +125 °C
TQFP80 14x14 (M),
TQFP64 14x14 (R),
TQFP64 10x10 (AR)
TQFP80 14x14 (M),
TQFP64 14x14 (R),
TQFP64 10x10 (AR)
TQFP64 14x14 (R), TQFP64
10x10 (AR)
TQFP64 14x14 (R), TQFP64
10x10 (AR)
Package
Rev. 5
May 2005
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1
Table of Contents
1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.3 STRUCTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.3.1 Read-out Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.4 ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.5 ICP (IN-CIRCUIT PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.6 IAP (IN-APPLICATION PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.7 RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.7.1 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.1 PHASE LOCKED LOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.2 MULTI-OSCILLATOR (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.3 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.3.2 Asynchronous External RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.3.3 External Power-On RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.3.4 Internal Low Voltage Detector (LVD) RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.3.5 Internal Watchdog RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.4 SYSTEM INTEGRITY MANAGEMENT (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.4.1 Low Voltage Detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.4.2 Auxiliary Voltage Detector (AVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.4.3 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.4.4 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.2 MASKING AND PROCESSING FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.3 INTERRUPTS AND LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.4 CONCURRENT & NESTED MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.5 INTERRUPT REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.6 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.6.1 I/O Port Interrupt Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.7 EXTERNAL INTERRUPT CONTROL REGISTER (EICR) . . . . . . . . . . . . . . . . . . . . . . . . . 40
8 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.2 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.3 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
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8.4 ACTIVE-HALT AND HALT MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8.4.1 ACTIVE-HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8.4.2 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
9.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
9.2.1 Input Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
9.2.2 Output Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
9.2.3 Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
9.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
9.4 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
9.5 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
9.5.1 I/O Port Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
10 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
10.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
10.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
10.1.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
10.1.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
10.1.4 How to Program the Watchdog Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
10.1.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
10.1.6 Hardware Watchdog Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
10.1.7 Using Halt Mode with the WDG (WDGHALT option) . . . . . . . . . . . . . . . . . . . . . . . 56
10.1.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
10.1.9 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
10.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK AND BEEPER (MCC/RTC) . . 58
10.2.1 Programmable CPU Clock Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
10.2.2 Clock-out Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
10.2.3 Real Time Clock Timer (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
10.2.4 Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
10.2.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
10.2.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
10.2.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
10.3 PWM AUTO-RELOAD TIMER (ART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
10.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
10.3.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
10.3.3 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
10.4 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
10.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
10.4.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
10.4.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
10.4.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
10.4.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
10.4.6 Summary of Timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
10.4.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
10.5 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
10.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
10.5.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
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10.5.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
10.5.4 Clock Phase and Clock Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
10.5.5 Error Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
10.5.6 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
10.5.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
10.5.8 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
10.6 SERIAL COMMUNICATIONS INTERFACE (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
10.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
10.6.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
10.6.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
10.6.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
10.6.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
10.6.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
10.6.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
10.7 I2C BUS INTERFACE (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
10.7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
10.7.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
10.7.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
10.7.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
10.7.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
10.7.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
10.7.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
10.8 CONTROLLER AREA NETWORK (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
10.8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
10.8.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
10.8.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
10.8.4 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
10.8.5 List of CAN Cell Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
10.9 10-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
10.9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
10.9.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
10.9.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
10.9.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
10.9.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
10.9.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
11 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
11.1 CPU ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
11.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
11.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
11.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
11.1.4 Indexed (No Offset, Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
11.1.5 Indirect (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
11.1.6 Indirect Indexed (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
11.1.7 Relative mode (Direct, Indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
11.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
12 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
12.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
4/215
Table of Contents
12.1.1 Minimum and Maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
12.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
12.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
12.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
12.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
12.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
12.2.1 Voltage Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
12.2.2 Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
12.2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
12.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
12.3.1 General Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
12.3.2 Operating Conditions with Low Voltage Detector (LVD) . . . . . . . . . . . . . . . . . . . 168
12.3.3 Auxiliary Voltage Detector (AVD) Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
12.3.4 External Voltage Detector (EVD) Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
12.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
12.4.1 CURRENT CONSUMPTION
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
12.4.2 Supply and Clock Managers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
12.4.3 On-Chip Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
12.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
12.5.1 General Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
12.5.2 External Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
12.5.3 Crystal and Ceramic Resonator Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
12.5.4 RC Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
12.5.5 PLL Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
12.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
12.6.1 RAM and Hardware Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
12.6.2 FLASH Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
12.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
12.7.1 Functional EMS (Electro Magnetic Susceptibility) . . . . . . . . . . . . . . . . . . . . . . . . 179
12.7.2 Electro Magnetic Interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
12.7.3 Absolute Maximum Ratings (Electrical Sensitivity) . . . . . . . . . . . . . . . . . . . . . . . 181
12.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
12.8.1 General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
12.8.2 Output Driving Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
12.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
12.9.1 Asynchronous RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
12.9.2 ICCSEL/VPP Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
12.10TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
12.10.1 8-Bit PWM-ART Auto-Reload Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
12.10.2 16-Bit Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
12.11COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 189
12.11.1 SPI - Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
12.11.2 I2C - Inter IC Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
12.11.3 CAN - Controller Area Network Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
12.1210-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
12.12.1 Analog Power Supply and Reference Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
12.12.2 General PCB Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
5/215
Table of Contents
12.12.3 ADC Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
13 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
13.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
13.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
13.3 SOLDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
14 ST72521 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . 201
14.1 FLASH OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
14.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . . 203
14.2.1 Version-Specific Sales Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
14.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
14.3.1 Socket and Emulator Adapter Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
14.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
15 KNOWN LIMITATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
15.1 ALL FLASH AND ROM DEVICES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
15.1.1 External RC option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
15.1.2 Safe Connection of OSC1/OSC2 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
15.1.3 Reset pin protection with LVD Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
15.1.4 Unexpected Reset Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
15.1.5 Clearing active interrupts outside interrupt routine . . . . . . . . . . . . . . . . . . . . . . . 211
15.1.6 SCI Wrong Break duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
15.1.7 16-bit Timer PWM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
15.1.8 CAN Cell Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
15.1.9 I2C Multimaster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
15.2 ALL FLASH DEVICES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
15.2.1 Internal RC Oscillator with LVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
15.2.2 I/O behaviour during ICC mode entry sequence . . . . . . . . . . . . . . . . . . . . . . . . . 213
15.2.3 Read-out protection with LVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
16 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
6/215
ST72F521, ST72521B
reducing power consumption when the application
is in idle or stand-by state.
1 INTRODUCTION
The ST72F521 and ST72521B devices are mem-
bers of the ST7 microcontroller family designed for
mid-range applications with a CAN bus interface
(Controller Area Network).
The enhanced instruction set and addressing
modes of the ST7 offer both power and flexibility to
software developers, enabling the design of highly
efficient and compact application code. In addition
to standard 8-bit data management, all ST7 micro-
controllers feature true bit manipulation, 8x8 un-
signed multiplication and indirect addressing
modes.
All devices are based on a common industry-
standard 8-bit core, featuring an enhanced instruc-
tion set and are available with FLASH or ROM pro-
gram memory.
Under software control, all devices can be placed
in WAIT, SLOW, ACTIVE-HALT or HALT mode,
Related Documentation
AN1131: Migrating applications from ST72511/
311/314 to ST72521/321/324
Figure 1. Device Block Diagram
8-BIT CORE
ALU
PROGRAM
MEMORY
(32K - 60K Bytes)
RESET
CONTROL
V
PP
RAM
TLI
(1024-2048 Bytes)
V
SS
DD
LVD
AVD
OSC
V
EVD
WATCHDOG
OSC1
OSC2
I2C
PA7:0
(8-bits)
MCC/RTC/BEEP
PORT A
PORT B
PORT F
TIMER A
BEEP
PF7:0
(8-bits)
PB7:0
(8-bits)
PWM ART
PORT C
PORT E
CAN
PC7:0
TIMER B
(8-bits)
PE7:0
(8-bits)
SPI
SCI
PG7:0
(8-bits)
1
PORT G
PORT D
10-BIT ADC
PD7:0
(8-bits)
PH7:0
(8-bits)
1
PORT H
V
AREF
V
SSA
1
On some devices only, see Device Summary on page 1
7/215
ST72F521, ST72521B
2 PIN DESCRIPTION
Figure 2. 80-Pin TQFP 14x14 Package Pinout
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
1
(HS) PE4
(HS) PE5
V
V
SS_1
2
DD_1
(HS) PE6
3
PA3 (HS)
PA2
(HS) PE7
4
ei0
PWM3 / PB0
PWM2 / PB1
PWM1 / PB2
PWM0 / PB3
PG0
5
PA1
6
PA0
ei2
7
PC7 / SS / AIN15
PC6 / SCK /ICCCLK
8
9
PH3
PH2
PH1
PG1
10
11
12
13
14
15
16
17
18
19
20
PG2
PH0
PG3
PC5 / MOSI / AIN14
ARTCLK / (HS) PB4
ARTIC1 / PB5
ARTIC2 / PB6
PB7
PC4 / MISO / ICCDATA
ei3
PC3 (HS) /ICAP1_B
PC2(HS) / ICAP2_B
PC1 / OCMP1_B / AIN13
AIN0 / PD0
AIN1 / PD1
AIN2 / PD2
AIN3 / PD3
PC0 / OCMP2_B /AIN12
VSS_0
ei1
VDD_0
(HS) 20mA high sink capability
eix associated external interrupt vector
8/215
ST72F521, ST72521B
PIN DESCRIPTION (Cont’d)
Figure 3. 64-Pin TQFP 14x14 and 10x10 Package Pinout
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
V
(HS) PE4
(HS) PE5
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
SS_1
DD_1
V
2
PA3 (HS)
(HS) PE6
3
PA2
(HS) PE7
4
ei0
PA1
PWM3 / PB0
PWM2 / PB1
PWM1 / PB2
PWM0 / PB3
ARTCLK / (HS) PB4
ARTIC1 / PB5
ARTIC2 / PB6
PB7
5
PA0
6
ei2
ei3
PC7 / SS / AIN15
PC6 / SCK / ICCCLK
PC5 / MOSI / AIN14
PC4 / MISO / ICCDATA
PC3 (HS) / ICAP1_B
PC2 (HS) / ICAP2_B
PC1 / OCMP1_B / AIN13
PC0 / OCMP2_B / AIN12
7
8
9
10
11
12
13
14
15
16
AIN0 / PD0
AIN1 / PD1
AIN2 / PD2
AIN3 / PD3
ei1
V
SS_0
V
DD_0
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
(HS) 20mA high sink capability
eix associated external interrupt vector
9/215
ST72F521, ST72521B
PIN DESCRIPTION (Cont’d)
For external pin connection guidelines, refer to See “ELECTRICAL CHARACTERISTICS” on page 165.
Legend / Abbreviations for Table 1:
Type:
I = input, O = output, S = supply
A = Dedicated analog input
Input level:
In/Output level: C = CMOS 0.3V /0.7V
DD
DD
C = CMOS 0.3V /0.7V with input trigger
T
DD
DD
T = TTL 0.8V / 2V with Schmitt trigger
T
Output level:
HS = 20mA high sink (on N-buffer only)
Port and control configuration:
1)
– Input:
float = floating, wpu = weak pull-up, int = interrupt , ana = analog
2)
– Output:
OD = open drain , PP = push-pull
Refer to “I/O PORTS” on page 47 for more details on the software configuration of the I/O ports.
The RESET configuration of each pin is shown in bold. This configuration is valid as long as the device is
in reset state.
Table 1. Device Pin Description
Pin n°
Level
Port
Main
function
(after
Input
Output
Pin Name
Alternate function
reset)
1
2
1
2
3
4
5
6
7
8
-
PE4 (HS)
I/O C
I/O C
I/O C
I/O C
I/O C
I/O C
I/O C
I/O C
HS
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Port E4
Port E5
Port E6
Port E7
T
T
T
T
T
T
T
T
T
T
T
T
PE5 (HS)
PE6 (HS)
PE7 (HS)
PB0/PWM3
PB1/PWM2
PB2/PWM1
PB3/PWM0
PG0
HS
HS
HS
X
3
X
4
X
5
ei2
ei2
ei2
Port B0 PWM Output 3
Port B1 PWM Output 2
Port B2 PWM Output 1
Port B3 PWM Output 0
Port G0
6
7
8
ei2
9
I/O
I/O
I/O
I/O
T
T
T
T
X
X
X
X
10
11
12
13
-
PG1
Port G1
-
PG2
Port G2
-
PG3
Port G3
9
PB4 (HS)/ARTCLK
I/O C
I/O C
I/O C
I/O C
I/O C
I/O C
I/O C
I/O C
HS
ei3
ei3
ei3
Port B4 PWM-ART External Clock
Port B5 PWM-ART Input Capture 1
Port B6 PWM-ART Input Capture 2
Port B7
T
T
T
T
T
T
T
T
T
T
14 10 PB5/ARTIC1
15 11 PB6/ARTIC2
16 12 PB7
ei3
17 13 PD0 /AIN0
18 14 PD1/AIN1
19 15 PD2/AIN2
20 16 PD3/AIN3
X
X
X
X
X
X
X
X
X
X
X
Port D0 ADC Analog Input 0
Port D1 ADC Analog Input 1
Port D2 ADC Analog Input 2
Port D3 ADC Analog Input 3
Port G6
21
22
-
-
PG6
PG7
I/O
I/O
T
T
Port G7
23 17 PD4/AIN4
I/O C
X
Port D4 ADC Analog Input 4
T
10/215
ST72F521, ST72521B
Pin n°
Level
Port
Main
function
(after
Input
Output
Pin Name
Alternate function
reset)
24 18 PD5/AIN5
25 19 PD6/AIN6
26 20 PD7/AIN7
I/O C
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Port D5 ADC Analog Input 5
Port D6 ADC Analog Input 6
Port D7 ADC Analog Input 7
Analog Reference Voltage for ADC
Analog Ground Voltage
Digital Main Supply Voltage
Digital Ground Voltage
Port G4
T
T
T
I/O C
I/O C
27 21
28 22
29 23
30 24
V
V
V
V
I
AREF
SSA
S
S
S
DD_3
SS_3
31
32
-
-
PG4
PG5
I/O
I/O
T
T
X
X
X
X
X
X
X
X
T
T
Port G5
Main clock
out (f
ADC Analog
Input 8
33 25 PF0/MCO/AIN8
I/O C
X
ei1
ei1
X
X
X
Port F0
T
)
CPU
34 26 PF1 (HS)/BEEP
35 27 PF2 (HS)
I/O C
I/O C
HS
X
X
X
X
X
X
Port F1 Beep signal output
Port F2
T
T
HS
ei1
Timer A Out-
Port F3 put Compare
2
ADC Analog
Input 9
36 28 PF3/OCMP2_A/AIN9
37 29 PF4/OCMP1_A/AIN10
I/O C
I/O C
X
X
X
X
X
X
X
X
X
T
T
Timer A Out-
Port F4 put Compare
1
ADC Analog
Input 10
X
X
Timer A Input ADC Analog
Capture 2 Input 11
38 30 PF5/ICAP2_A/AIN11
39 31 PF6 (HS)/ICAP1_A
40 32 PF7 (HS)/EXTCLK_A
I/O C
I/O C
I/O C
X
X
X
X
X
X
X
X
X
X
X
X
Port F5
T
T
T
HS
HS
Port F6 Timer A Input Capture 1
Timer A External Clock
Port F7
Source
41 33
42 34
V
V
S
S
Digital Main Supply Voltage
Digital Ground Voltage
Timer B Out-
DD_0
SS_0
ADC Analog
43 35 PC0/OCMP2_B/AIN12
44 36 PC1/OCMP1_B/AIN13
I/O C
I/O C
X
X
X
X
X
X
X
X
X
X
Port C0 put Compare
2
T
T
Input 12
Timer B Out-
Port C1 put Compare
1
ADC Analog
Input 13
45 37 PC2 (HS)/ICAP2_B
46 38 PC3 (HS)/ICAP1_B
I/O C
I/O C
HS
HS
X
X
X
X
X
X
X
X
Port C2 Timer B Input Capture 2
Port C3 Timer B Input Capture 1
SPIMasterIn
T
T
ICC Data In-
47 39 PC4/MISO/ICCDATA
48 40 PC5/MOSI/AIN14
I/O C
I/O C
X
X
X
X
X
X
X
X
Port C4 / Slave Out
Data
T
T
put
SPI Master
Port C5 Out / Slave In
Data
ADC Analog
Input 14
X
49
50
51
-
-
-
PH0
PH1
PH2
I/O
I/O
I/O
T
T
T
X
X
X
X
X
X
X
X
X
X
X
X
Port H0
Port H1
Port H2
T
T
T
11/215
ST72F521, ST72521B
Pin n°
Level
Port
Main
function
(after
Input
Output
Pin Name
Alternate function
reset)
52
-
PH3
I/O
T
X
X
X
X
X
X
X
X
Port H3
Port C6
T
T
SPI Serial
Clock
ICC Clock
Output
53 41 PC6/SCK/ICCCLK
I/O C
Caution: Negative current
injection not allowed on this
5)
pin
SPI Slave
Port C7 Select(active
low)
ADC Analog
Input 15
54 42 PC7/SS/AIN15
I/O C
X
X
X
X
X
T
55 43 PA0
56 44 PA1
57 45 PA2
58 46 PA3 (HS)
I/O C
I/O C
I/O C
I/O C
S
X
X
X
X
ei0
ei0
ei0
X
X
X
X
X
X
X
X
Port A0
Port A1
Port A2
Port A3
T
T
T
HS
ei0
T
59 47
60 48
V
V
Digital Main Supply Voltage
Digital Ground Voltage
Port A4
DD_1
SS_1
S
61 49 PA4 (HS)
I/O C
I/O C
I/O C
I/O C
HS
HS
HS
HS
X
X
X
X
X
X
X
X
T
T
X
X
T
T
T
T
62 50 PA5 (HS)
Port A5
2
1)
63 51 PA6 (HS)/SDAI
64 52 PA7 (HS)/SCLI
Port A6
Port A7
I C Data
2
1)
I C Clock
Must be tied low. In flash programming
mode, this pin acts as the programming
65 53
V
/ ICCSEL
I
voltage input V . See Section 12.9.2
PP
PP
for more details. High voltage must not
be applied to ROM devices
66 54 RESET
67 55 EVD
68 56 TLI
I/O C
Top priority non maskable interrupt.
External voltage detector
Top level interrupt input pin
Port H4
T
I
C
X
X
X
X
X
X
T
T
T
T
T
69
70
71
72
-
-
-
-
PH4
PH5
PH6
PH7
I/O
I/O
I/O
I/O
S
T
T
T
T
X
X
X
X
X
X
X
X
X
X
X
X
Port H5
Port H6
Port H7
73 57
V
Digital Ground Voltage
Resonator oscillator inverter output
SS_2
3)
3)
74 58 OSC2
I/O
External clock input or Resonator oscil-
lator inverter input
75 59 OSC1
I
76 60
V
S
Digital Main Supply Voltage
DD_2
77 61 PE0/TDO
78 62 PE1/RDI
I/O C
I/O C
I/O C
I/O C
X
X
X
X
X
X
X
X
X
X
Port E0 SCI Transmit Data Out
Port E1 SCI Receive Data In
Port E2 CAN Transmit Data Output
Port E3 CAN Receive Data Input
T
T
T
T
79 63 PE2/CANTX
80 64 PE3/CANRX
X
X
X
Notes:
1. In the interrupt input column, “eiX” defines the associated external interrupt vector. If the weak pull-up
12/215
ST72F521, ST72521B
column (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input,
else the configuration is floating interrupt input.
2. In the open drain output column, “T” defines a true open drain I/O (P-Buffer and protection diode to V
DD
are not implemented). See See “I/O PORTS” on page 47. and Section 12.8 I/O PORT PIN CHARACTER-
ISTICS for more details.
3. OSC1 and OSC2 pins connect a crystal/ceramic resonator, or an external source to the on-chip oscil-
lator; see Section 1 INTRODUCTION and Section 12.5 CLOCK AND TIMING CHARACTERISTICS for
more details.
4. On the chip, each I/O port may have up to 8 pads. Pads that are not bonded to external pins are in input
pull-up configuration after reset. The configuration of these pads must be kept at reset state to avoid add-
ed current consumption.
13/215
ST72F521, ST72521B
3 REGISTER & MEMORY MAP
As shown in Figure 4, the MCU is capable of ad-
dressing 64K bytes of memories and I/O registers.
IMPORTANT: Memory locations marked as “Re-
served” must never be accessed. Accessing a re-
seved area can have unpredictable effects on the
device.
The available memory locations consist of 128
bytes of register locations, up to 2Kbytes of RAM
and up to 60Kbytes of user program memory. The
RAM space includes up to 256 bytes for the stack
from 0100h to 01FFh.
Related Documentation
AN 985: Executing Code in ST7 RAM
The highest address bytes contain the user reset
and interrupt vectors.
Figure 4. Memory Map
0000h
0080h
HW Registers
(see Table 2)
Short Addressing
RAM (zero page)
007Fh
0080h
00FFh
0100h
RAM
256 Bytes Stack
1000h
(2048 or 1024 Bytes)
01FFh
0200h
087Fh
0880h
60 KBytes
16-bit Addressing
RAM
Reserved
or 047Fh
or 067Fh
or 087Fh
0FFFh
1000h
8000h
Program Memory
(60K or 32K)
32 KBytes
FFDFh
FFE0h
Interrupt & Reset Vectors
(see Table 7)
FFFFh
FFFFh
14/215
ST72F521, ST72521B
Table 2. Hardware Register Map
Register
Label
Reset
Address
Block
Register Name
Remarks
Status
1)
0000h
0001h
0002h
PADR
PADDR
PAOR
Port A Data Register
Port A Data Direction Register
Port A Option Register
00h
00h
00h
R/W
R/W
R/W
Port A
1)
0003h
0004h
0005h
PBDR
PBDDR
PBOR
Port B Data Register
Port B Data Direction Register
Port B Option Register
00h
00h
00h
R/W
R/W
R/W
Port B
Port C
Port D
Port E
Port F
1)
0006h
0007h
0008h
PCDR
PCDDR
PCOR
Port C Data Register
Port C Data Direction Register
Port C Option Register
00h
00h
00h
R/W
R/W
R/W
1)
0009h
000Ah
000Bh
PDDR
PDDDR
PDOR
Port D Data Register
Port D Data Direction Register
Port D Option Register
00h
00h
00h
R/W
R/W
R/W
1)
000Ch
000Dh
000Eh
PEDR
PEDDR
PEOR
Port E Data Register
Port E Data Direction Register
Port E Option Register
00h
00h
00h
R/W
R/W
R/W
2)
2)
1)
000Fh
0010h
0011h
PFDR
PFDDR
PFOR
Port F Data Register
Port F Data Direction Register
Port F Option Register
00h
00h
00h
R/W
R/W
R/W
1)
0012h
0013h
0014h
PGDR
PGDDR
PGOR
Port G Data Register
Port G Data Direction Register
Port G Option Register
00h
00h
00h
R/W
R/W
R/W
2)
Port G
Port H
1)
0015h
0016h
0017h
PHDR
PHDDR
PHOR
Port H Data Register
Port H Data Direction Register
Port H Option Register
00h
00h
00h
R/W
R/W
R/W
2)
2
0018h
0019h
001Ah
001Bh
001Ch
001Dh
001Eh
I2CCR
I C Control Register
00h
00h
00h
00h
00h
00h
00h
R/W
2
I2CSR1
I2CSR2
I2CCCR
I2COAR1
I2COAR2
I2CDR
I C Status Register 1
Read Only
Read Only
R/W
R/W
R/W
2
I C Status Register 2
2
2
I C
I C Clock Control Register
2
I C Own Address Register 1
2
I C Own Address Register2
2
I C Data Register
R/W
001Fh
0020h
Reserved Area (2 Bytes)
0021h
0022h
0023h
SPIDR
SPICR
SPICSR
SPI Data I/O Register
SPI Control Register
SPI Control/Status Register
xxh
0xh
00h
R/W
R/W
R/W
SPI
15/215
ST72F521, ST72521B
Register
Label
Reset
Status
Address
Block
Register Name
Remarks
0024h
0025h
0026h
0027h
ISPR0
Interrupt Software Priority Register 0
Interrupt Software Priority Register 1
Interrupt Software Priority Register 2
Interrupt Software Priority Register 3
FFh
FFh
FFh
FFh
R/W
ISPR1
ISPR2
ISPR3
R/W
R/W
R/W
ITC
0028h
0029h
002Ah
002Bh
EICR
External Interrupt Control Register
Flash Control/Status Register
00h
00h
7Fh
R/W
R/W
R/W
FLASH
FCSR
WATCHDOG
WDGCR
SICSR
Watchdog Control Register
System Integrity Control/Status Register
000x 000x b R/W
002Ch
002Dh
MCCSR
MCCBCR
Main Clock Control / Status Register
Main Clock Controller: Beep Control Register
00h
00h
R/W
R/W
MCC
002Eh
to
Reserved Area (3 Bytes)
0030h
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
TACR2
TACR1
TACSR
TAIC1HR
TAIC1LR
TAOC1HR
TAOC1LR
TACHR
Timer A Control Register 2
Timer A Control Register 1
Timer A Control/Status Register
Timer A Input Capture 1 High Register
Timer A Input Capture 1 Low Register
Timer A Output Compare 1 High Register
Timer A Output Compare 1 Low Register
Timer A Counter High Register
00h
00h
R/W
R/W
xxxx x0xx b R/W
xxh
xxh
80h
00h
FFh
FCh
FFh
FCh
xxh
xxh
80h
00h
Read Only
Read Only
R/W
R/W
TIMER A
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
R/W
TACLR
Timer A Counter Low Register
TAACHR
TAACLR
TAIC2HR
TAIC2LR
TAOC2HR
TAOC2LR
Timer A Alternate Counter High Register
Timer A Alternate Counter Low Register
Timer A Input Capture 2 High Register
Timer A Input Capture 2 Low Register
Timer A Output Compare 2 High Register
Timer A Output Compare 2 Low Register
R/W
0040h
Reserved Area (1 Byte)
0041h
0042h
0043h
0044h
0045h
0046h
0047h
0048h
0049h
004Ah
004Bh
004Ch
004Dh
004Eh
004Fh
TBCR2
TBCR1
TBCSR
TBIC1HR
TBIC1LR
TBOC1HR
TBOC1LR
TBCHR
Timer B Control Register 2
Timer B Control Register 1
Timer B Control/Status Register
Timer B Input Capture 1 High Register
Timer B Input Capture 1 Low Register
Timer B Output Compare 1 High Register
Timer B Output Compare 1 Low Register
Timer B Counter High Register
00h
00h
R/W
R/W
xxxx x0xx b R/W
xxh
xxh
80h
00h
FFh
FCh
FFh
FCh
xxh
xxh
80h
00h
Read Only
Read Only
R/W
R/W
TIMER B
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
R/W
TBCLR
Timer B Counter Low Register
TBACHR
TBACLR
TBIC2HR
TBIC2LR
TBOC2HR
TBOC2LR
Timer B Alternate Counter High Register
Timer B Alternate Counter Low Register
Timer B Input Capture 2 High Register
Timer B Input Capture 2 Low Register
Timer B Output Compare 2 High Register
Timer B Output Compare 2 Low Register
R/W
16/215
ST72F521, ST72521B
Register
Label
Reset
Address
Block
Register Name
Remarks
Status
0050h
0051h
0052h
0053h
0054h
0055h
0056h
0057h
SCISR
SCIDR
SCIBRR
SCICR1
SCICR2
SCIERPR
SCI Status Register
SCI Data Register
SCI Baud Rate Register
SCI Control Register 1
SCI Control Register 2
SCI Extended Receive Prescaler Register
Reserved area
C0h
xxh
00h
Read Only
R/W
R/W
x000 0000b R/W
SCI
00h
00h
---
R/W
R/W
SCIETPR
SCI Extended Transmit Prescaler Register
00h
R/W
0058h
0059h
Reserved Area (2 Bytes)
005Ah
005Bh
005Ch
005Dh
005Eh
005Fh
0060h
to
CANISR
CAN Interrupt Status Register
CAN Interrupt Control Register
CAN Control / Status Register
CAN Baud Rate Prescaler Register
CAN Bit Timing Register
CAN Page Selection Register
First address
00h
00h
00h
00h
23h
00h
--
R/W
R/W
R/W
R/W
R/W
R/W
See CAN
Description
CANICR
CANCSR
CANBRPR
CANBTR
CANPSR
CAN
ADC
to
006Fh
Last address of CAN page x
0070h
0071h
0072h
ADCCSR
ADCDRH
ADCDRL
Control/Status Register
Data High Register
Data Low Register
00h
00h
00h
R/W
Read Only
Read Only
0073h
0074h
0075h
0076h
0077h
00h
00h
00h
00h
00h
00h
00h
00h
PWMDCR3 PWM AR Timer Duty Cycle Register 3
PWMDCR2 PWM AR Timer Duty Cycle Register 2
PWMDCR1 PWM AR Timer Duty Cycle Register 1
PWMDCR0 PWM AR Timer Duty Cycle Register 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PWMCR
ARTCSR
ARTCAR
ARTARR
PWM AR Timer Control Register
0078h
0079h
007Ah
PWM ART
Auto-Reload Timer Control/Status Register
Auto-Reload Timer Counter Access Register
Auto-Reload Timer Auto-Reload Register
ARTICCSR AR Timer Input Capture Control/Status Reg.
R/W
Read Only
Read Only
00h
00h
00h
007Bh
007Ch
007Dh
ARTICR1
ARTICR2
AR Timer Input Capture Register 1
AR Timer Input Capture Register 1
007Eh
007Fh
Reserved Area (2 Bytes)
Legend: x=undefined, R/W=read/write
Notes:
1. The contents of the I/O port DR registers are readable only in output configuration. In input configura-
tion, the values of the I/O pins are returned instead of the DR register contents.
2. The bits associated with unavailable pins must always keep their reset value.
17/215
ST72F521, ST72521B
4 FLASH PROGRAM MEMORY
4.1 Introduction
sectors (see Table 3). Each of these sectors can
be erased independently to avoid unnecessary
erasing of the whole Flash memory when only a
partial erasing is required.
The ST7 dual voltage High Density Flash
(HDFlash) is a non-volatile memory that can be
electrically erased as a single block or by individu-
al sectors and programmed on a Byte-by-Byte ba-
The first two sectors have a fixed size of 4 Kbytes
(see Figure 5). They are mapped in the upper part
of the ST7 addressing space so the reset and in-
terrupt vectors are located in Sector 0 (F000h-
FFFFh).
sis using an external V supply.
PP
The HDFlash devices can be programmed and
erased off-board (plugged in a programming tool)
or on-board using ICP (In-Circuit Programming) or
IAP (In-Application Programming).
Table 3. Sectors available in Flash devices
The array matrix organisation allows each sector
to be erased and reprogrammed without affecting
other sectors.
Flash Size (bytes)
Available Sectors
4K
8K
Sector 0
Sectors 0,1
Sectors 0,1, 2
4.2 Main Features
> 8K
■ Three Flash programming modes:
4.3.1 Read-out Protection
– Insertion in a programming tool. In this mode,
all sectors including option bytes can be pro-
grammed or erased.
– ICP (In-Circuit Programming). In this mode, all
sectors including option bytes can be pro-
grammed or erased without removing the de-
vice from the application board.
– IAP (In-Application Programming) In this
mode, all sectors except Sector 0, can be pro-
grammed or erased without removing the de-
vice from the application board and while the
application is running.
Read-out protection, when selected, provides a
protection against Program Memory content ex-
traction and against write access to Flash memo-
ry. Even if no protection can be considered as to-
tally unbreakable, the feature provides a very high
level of protection for a general purpose microcon-
troller.
In flash devices, this protection is removed by re-
programming the option. In this case, the entire
program memory is first automatically erased and
the device can be reprogrammed.
■ ICT (In-Circuit Testing) for downloading and
executing user application test patterns in RAM
Read-out protection selection depends on the de-
vice type:
■ Read-out protection
■ Register Access Security System (RASS) to
– In Flash devices it is enabled and removed
through the FMP_R bit in the option byte.
prevent accidental programming or erasing
– In ROM devices it is enabled by mask option
specified in the Option List.
4.3 Structure
The Flash memory is organised in sectors and can
be used for both code and data storage.
Note: In flash devices, the LVD is not supported if
read-out protection is enabled.
Depending on the overall Flash memory size in the
microcontroller device, there are up to three user
Figure 5. Memory Map and Sector Address
4K
8K
10K
16K
24K
32K
48K
60K
FLASH
MEMORY SIZE
1000h
3FFFh
7FFFh
9FFFh
BFFFh
D7FFh
DFFFh
EFFFh
FFFFh
SECTOR 2
52 Kbytes
2 Kbytes 8 Kbytes 16 Kbytes 24 Kbytes 40 Kbytes
4 Kbytes
4 Kbytes
SECTOR 1
SECTOR 0
18/215
ST72F521, ST72521B
FLASH PROGRAM MEMORY (Cont’d)
4.4 ICC Interface
– ICCCLK: ICC output serial clock pin
– ICCDATA: ICC input/output serial data pin
ICC needs a minimum of 4 and up to 6 pins to be
connected to the programming tool (see Figure 6).
These pins are:
– ICCSEL/V : programming voltage
PP
– OSC1(or OSCIN): main clock input for exter-
nal source (optional)
– RESET: device reset
– V : application board power supply (option-
DD
– V : device power supply ground
al, see Figure 6, Note 3)
SS
Figure 6. Typical ICC Interface
PROGRAMMING TOOL
ICC CONNECTOR
ICC Cable
APPLICATION BOARD
ICC CONNECTOR
(See Note 3)
OPTIONAL
HE10 CONNECTOR TYPE
9
7
5
6
3
1
2
(See Note 4)
10
8
4
APPLICATION
RESET SOURCE
See Note 2
10kΩ
APPLICATION
POWER SUPPLY
C
C
L2
L1
See Note 1
APPLICATION
I/O
ST7
Notes:
1. If the ICCCLK or ICCDATA pins are only used
agement IC with open drain output and pull-up re-
sistor>1K, no additional components are needed.
In all cases the user must ensure that no external
reset is generated by the application during the
ICC session.
as outputs in the application, no signal isolation is
necessary. As soon as the Programming Tool is
plugged to the board, even if an ICC session is not
in progress, the ICCCLK and ICCDATA pins are
not available for the application. If they are used as
inputs by the application, isolation such as a serial
resistor has to implemented in case another de-
vice forces the signal. Refer to the Programming
Tool documentation for recommended resistor val-
ues.
3. The use of Pin 7 of the ICC connector depends
on the Programming Tool architecture. This pin
must be connected when using most ST Program-
ming Tools (it is used to monitor the application
power supply). Please refer to the Programming
Tool manual.
2. During the ICC session, the programming tool
must control the RESET pin. This can lead to con-
flicts between the programming tool and the appli-
cation reset circuit if it drives more than 5mA at
high level (push pull output or pull-up resistor<1K).
A schottky diode can be used to isolate the appli-
cation RESET circuit in this case. When using a
classical RC network with R>1K or a reset man-
4. Pin 9 has to be connected to the OSC1 or OS-
CIN pin of the ST7 when the clock is not available
in the application or if the selected clock option is
not programmed in the option byte. ST7 devices
with multi-oscillator capability need to have OSC2
grounded in this case.
19/215
ST72F521, ST72521B
FLASH PROGRAM MEMORY (Cont’d)
4.5 ICP (In-Circuit Programming)
possible to download code from the SPI, SCI, USB
or CAN interface and program it in the Flash. IAP
mode can be used to program any of the Flash
sectors except Sector 0, which is write/erase pro-
tected to allow recovery in case errors occur dur-
ing the programming operation.
To perform ICP the microcontroller must be
switched to ICC (In-Circuit Communication) mode
by an external controller or programming tool.
Depending on the ICP code downloaded in RAM,
Flash memory programming can be fully custom-
ized (number of bytes to program, program loca-
tions, or selection serial communication interface
for downloading).
4.7 Related Documentation
For details on Flash programming and ICC proto-
col, refer to the ST7 Flash Programming Refer-
ence Manual and to the ST7 ICC Protocol Refer-
ence Manual.
When using an STMicroelectronics or third-party
programming tool that supports ICP and the spe-
cific microcontroller device, the user needs only to
implement the ICP hardware interface on the ap-
plication board (see Figure 6). For more details on
the pin locations, refer to the device pinout de-
scription.
4.7.1 Register Description
FLASH CONTROL/STATUS REGISTER (FCSR)
Read/Write
Reset Value: 0000 0000 (00h)
4.6 IAP (In-Application Programming)
7
0
0
0
This mode uses a BootLoader program previously
stored in Sector 0 by the user (in ICP mode or by
plugging the device in a programming tool).
0
0
0
0
0
0
This mode is fully controlled by user software. This
allows it to be adapted to the user application, (us-
er-defined strategy for entering programming
mode, choice of communications protocol used to
fetch the data to be stored, etc.). For example, it is
This register is reserved for use by Programming
Tool software. It controls the Flash programming
and erasing operations.
Figure 7. Flash Control/Status Register Address and Reset Value
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
FCSR
Reset Value
0029h
0
0
0
0
0
0
0
0
20/215
ST72F521, ST72521B
5 CENTRAL PROCESSING UNIT
5.1 INTRODUCTION
5.3 CPU REGISTERS
This CPU has a full 8-bit architecture and contains
six internal registers allowing efficient 8-bit data
manipulation.
The 6 CPU registers shown in Figure 8 are not
present in the memory mapping and are accessed
by specific instructions.
Accumulator (A)
5.2 MAIN FEATURES
The Accumulator is an 8-bit general purpose reg-
ister used to hold operands and the results of the
arithmetic and logic calculations and to manipulate
data.
■ Enable executing 63 basic instructions
■ Fast 8-bit by 8-bit multiply
■ 17 main addressing modes (with indirect
Index Registers (X and Y)
addressing mode)
These 8-bit registers are used to create effective
addresses or as temporary storage areas for data
manipulation. (The Cross-Assembler generates a
precede instruction (PRE) to indicate that the fol-
lowing instruction refers to the Y register.)
■ Two 8-bit index registers
■ 16-bit stack pointer
■ Low power HALT and WAIT modes
■ Priority maskable hardware interrupts
■ Non-maskable software/hardware interrupts
The Y register is not affected by the interrupt auto-
matic procedures.
Program Counter (PC)
The program counter is a 16-bit register containing
the address of the next instruction to be executed
by the CPU. It is made of two 8-bit registers PCL
(Program Counter Low which is the LSB) and PCH
(Program Counter High which is the MSB).
Figure 8. CPU Registers
7
0
ACCUMULATOR
RESET VALUE = XXh
7
0
0
X INDEX REGISTER
Y INDEX REGISTER
RESET VALUE = XXh
7
RESET VALUE = XXh
PCL
PCH
7
8
15
0
PROGRAM COUNTER
RESET VALUE = RESET VECTOR @ FFFEh-FFFFh
7
1
0
1
1
I1 H I0 N Z C
CONDITION CODE REGISTER
RESET VALUE =
8
1
1
X 1 X X X
0
15
7
STACK POINTER
RESET VALUE = STACK HIGHER ADDRESS
X = Undefined Value
21/215
ST72F521, ST72521B
CENTRAL PROCESSING UNIT (Cont’d)
Condition Code Register (CC)
Read/Write
Bit 1 = Z Zero.
This bit is set and cleared by hardware. This bit in-
dicates that the result of the last arithmetic, logical
or data manipulation is zero.
0: The result of the last operation is different from
zero.
Reset Value: 111x1xxx
7
0
1: The result of the last operation is zero.
1
1
I1
H
I0
N
Z
C
This bit is accessed by the JREQ and JRNE test
instructions.
The 8-bit Condition Code register contains the in-
terrupt masks and four flags representative of the
result of the instruction just executed. This register
can also be handled by the PUSH and POP in-
structions.
Bit 0 = C Carry/borrow.
This bit is set and cleared by hardware and soft-
ware. It indicates an overflow or an underflow has
occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.
These bits can be individually tested and/or con-
trolled by specific instructions.
Arithmetic Management Bits
This bit is driven by the SCF and RCF instructions
and tested by the JRC and JRNC instructions. It is
also affected by the “bit test and branch”, shift and
rotate instructions.
Bit 4 = H Half carry.
This bit is set by hardware when a carry occurs be-
tween bits 3 and 4 of the ALU during an ADD or
ADC instructions. It is reset by hardware during
the same instructions.
Interrupt Management Bits
Bit 5,3 = I1, I0 Interrupt
0: No half carry has occurred.
1: A half carry has occurred.
The combination of the I1 and I0 bits gives the cur-
rent interrupt software priority.
This bit is tested using the JRH or JRNH instruc-
tion. The H bit is useful in BCD arithmetic subrou-
tines.
Interrupt Software Priority
Level 0 (main)
I1
1
0
0
1
I0
0
1
0
1
Level 1
Bit 2 = N Negative.
Level 2
This bit is set and cleared by hardware. It is repre-
sentative of the result sign of the last arithmetic,
logical or data manipulation. It’s a copy of the re-
Level 3 (= interrupt disable)
These two bits are set/cleared by hardware when
entering in interrupt. The loaded value is given by
the corresponding bits in the interrupt software pri-
ority registers (IxSPR). They can be also set/
cleared by software with the RIM, SIM, IRET,
HALT, WFI and PUSH/POP instructions.
th
sult 7 bit.
0: The result of the last operation is positive or null.
1: The result of the last operation is negative
(i.e. the most significant bit is a logic 1).
This bit is accessed by the JRMI and JRPL instruc-
tions.
See the interrupt management chapter for more
details.
22/215
ST72F521, ST72521B
CENTRAL PROCESSING UNIT (Cont’d)
Stack Pointer (SP)
Read/Write
The least significant byte of the Stack Pointer
(called S) can be directly accessed by a LD in-
struction.
Reset Value: 01 FFh
Note: When the lower limit is exceeded, the Stack
Pointer wraps around to the stack upper limit, with-
out indicating the stack overflow. The previously
stored information is then overwritten and there-
fore lost. The stack also wraps in case of an under-
flow.
15
8
1
0
7
0
0
0
0
0
0
0
The stack is used to save the return address dur-
ing a subroutine call and the CPU context during
an interrupt. The user may also directly manipulate
the stack by means of the PUSH and POP instruc-
tions. In the case of an interrupt, the PCL is stored
at the first location pointed to by the SP. Then the
other registers are stored in the next locations as
shown in Figure 9.
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
The Stack Pointer is a 16-bit register which is al-
ways pointing to the next free location in the stack.
It is then decremented after data has been pushed
onto the stack and incremented before data is
popped from the stack (see Figure 9).
– When an interrupt is received, the SP is decre-
mented and the context is pushed on the stack.
Since the stack is 256 bytes deep, the 8 most sig-
nificant bits are forced by hardware. Following an
MCU Reset, or after a Reset Stack Pointer instruc-
tion (RSP), the Stack Pointer contains its reset val-
ue (the SP7 to SP0 bits are set) which is the stack
higher address.
– On return from interrupt, the SP is incremented
and the context is popped from the stack.
A subroutine call occupies two locations and an in-
terrupt five locations in the stack area.
Figure 9. Stack Manipulation Example
CALL
Subroutine
RET
or RSP
PUSH Y
POP Y
IRET
Interrupt
Event
@ 0100h
SP
SP
SP
Y
CC
A
CC
A
CC
A
X
X
X
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
SP
SP
PCH
PCL
PCH
PCL
SP
@ 01FFh
Stack Higher Address = 01FFh
0100h
Stack Lower Address =
23/215
ST72F521, ST72521B
6 SUPPLY, RESET AND CLOCK MANAGEMENT
The device includes a range of utility features for
securing the application in critical situations (for
example in case of a power brown-out), and re-
ducing the number of external components. An
overview is shown in Figure 11.
6.1 PHASE LOCKED LOOP
If the clock frequency input to the PLL is in the
range 2 to 4 MHz, the PLL can be used to multiply
the frequency by two to obtain an f
of 4 to 8
OSC2
MHz. The PLL is enabled by option byte. If the PLL
is disabled, then f /2.
For more details, refer to dedicated parametric
section.
f
OSC2 = OSC
Caution: The PLL is not recommended for appli-
cations where timing accuracy is required. See
“PLL Characteristics” on page 177.
Main features
■ Optional PLL for multiplying the frequency by 2
(not to be used with internal RC oscillator)
■ Reset Sequence Manager (RSM)
Figure 10. PLL Block Diagram
■ Multi-Oscillator Clock Management (MO)
PLL x 2
/ 2
0
1
– 5 Crystal/Ceramic resonator oscillators
– 1 Internal RC oscillator
■ System Integrity Management (SI)
f
OSC
f
OSC2
– Main supply Low voltage detection (LVD)
PLL OPTION BIT
– Auxiliary Voltage detector (AVD) with interrupt
capability for monitoring the main supply or
the EVD pin
Figure 11. Clock, Reset and Supply Block Diagram
MAIN CLOCK
CONTROLLER
WITH REALTIME
CLOCK (MCC/RTC)
MULTI-
f
OSC2
f
f
CPU
OSC2
OSC
PLL
(option)
OSCILLATOR
(MO)
OSC1
SYSTEM INTEGRITY MANAGEMENT
AVD Interrupt Request
RESET SEQUENCE
MANAGER
WATCHDOG
TIMER (WDG)
RESET
SICSR
AVD
S
AVD AVD
LVD
RF
WDG
RF
(RSM)
0
0
0
IE
F
LOW VOLTAGE
DETECTOR
(LVD)
V
V
SS
DD
0
1
AUXILIARY VOLTAGE
DETECTOR
EVD
(AVD)
24/215
ST72F521, ST72521B
6.2 MULTI-OSCILLATOR (MO)
The main clock of the ST7 can be generated by
three different source types coming from the multi-
oscillator block:
■ an external source
■ 4 crystal or ceramic resonator oscillators
■ an internal high frequency RC oscillator
Internal RC Oscillator
This oscillator allows a low cost solution for the
main clock of the ST7 using only an internal resis-
tor and capacitor. Internal RC oscillator mode has
the drawback of a lower frequency accuracy and
should not be used in applications that require ac-
curate timing.
Each oscillator is optimized for a given frequency
range in terms of consumption and is selectable
through the option byte. The associated hardware
configurations are shown in Table 4. Refer to the
electrical characteristics section for more details.
In this mode, the two oscillator pins have to be tied
to ground.
Table 4. ST7 Clock Sources
Hardware Configuration
Caution: The OSC1 and/or OSC2 pins must not
be left unconnected. For the purposes of Failure
Mode and Effect Analysis, it should be noted that if
the OSC1 and/or OSC2 pins are left unconnected,
the ST7 main oscillator may start and, in this con-
ST7
OSC1
OSC2
figuration, could generate an f
clock frequency
OSC
in excess of the allowed maximum (>16MHz.),
putting the ST7 in an unsafe/undefined state. The
product behaviour must therefore be considered
undefined when the OSC pins are left unconnect-
ed.
EXTERNAL
SOURCE
External Clock Source
ST7
In this external clock mode, a clock signal (square,
sinus or triangle) with ~50% duty cycle has to drive
the OSC1 pin while the OSC2 pin is tied to ground.
OSC1
OSC2
Crystal/Ceramic Oscillators
This family of oscillators has the advantage of pro-
ducing a very accurate rate on the main clock of
the ST7. The selection within a list of 4 oscillators
with different frequency ranges has to be done by
option byte in order to reduce consumption (refer
to section 14.1 on page 201 for more details on the
frequency ranges). In this mode of the multi-oscil-
lator, the resonator and the load capacitors have
to be placed as close as possible to the oscillator
pins in order to minimize output distortion and
start-up stabilization time. The loading capaci-
tance values must be adjusted according to the
selected oscillator.
C
C
L2
L1
LOAD
CAPACITORS
ST7
OSC1
OSC2
These oscillators are not stopped during the
RESET phase to avoid losing time in the oscillator
start-up phase.
25/215
ST72F521, ST72521B
6.3 RESET SEQUENCE MANAGER (RSM)
6.3.1 Introduction
The RESET vector fetch phase duration is 2 clock
cycles.
The reset sequence manager includes three RE-
SET sources as shown in Figure 13:
■ External RESET source pulse
Figure 12. RESET Sequence Phases
■ Internal LVD RESET (Low Voltage Detection)
■ Internal WATCHDOG RESET
RESET
These sources act on the RESET pin and it is al-
ways kept low during the delay phase.
INTERNAL RESET
FETCH
Active Phase
256 or 4096 CLOCK CYCLES
VECTOR
The RESET service routine vector is fixed at ad-
dresses FFFEh-FFFFh in the ST7 memory map.
6.3.2 Asynchronous External RESET pin
The basic RESET sequence consists of 3 phases
as shown in Figure 12:
■ Active Phase depending on the RESET source
■ 256 or 4096 CPU clock cycle delay (selected by
option byte)
■ RESET vector fetch
The RESET pin is both an input and an open-drain
output with integrated R
weak pull-up resistor.
ON
This pull-up has no fixed value but varies in ac-
cordance with the input voltage. It can be pulled
low by external circuitry to reset the device. See
“CONTROL PIN CHARACTERISTICS” on
page 185 for more details.
The 256 or 4096 CPU clock cycle delay allows the
oscillator to stabilise and ensures that recovery
has taken place from the Reset state. The shorter
or longer clock cycle delay should be selected by
option byte to correspond to the stabilization time
of the external oscillator used in the application
(see section 14.1 on page 201).
A RESET signal originating from an external
source must have a duration of at least t
in
h(RSTL)in
order to be recognized (see Figure 14). This de-
tection is asynchronous and therefore the MCU
can enter reset state even in HALT mode.
Figure 13. Reset Block Diagram
V
DD
R
ON
INTERNAL
RESET
Filter
RESET
PULSE
WATCHDOG RESET
GENERATOR
LVD RESET
26/215
ST72F521, ST72521B
RESET SEQUENCE MANAGER (Cont’d)
The RESET pin is an asynchronous signal which
plays a major role in EMS performance. In a noisy
environment, it is recommended to follow the
guidelines mentioned in the electrical characteris-
tics section.
A proper reset signal for a slow rising V supply
can generally be provided by an external RC net-
work connected to the RESET pin.
DD
6.3.4 Internal Low Voltage Detector (LVD)
RESET
If the external RESET pulse is shorter than
Two different RESET sequences caused by the in-
ternal LVD circuitry can be distinguished:
■ Power-On RESET
t
(see short ext. Reset in Figure 14), the
w(RSTL)out
signal on the RESET pin may be stretched. Other-
wise the delay will not be applied (see long ext.
Reset in Figure 14). Starting from the external RE-
SET pulse recognition, the device RESET pin acts
as an output that is pulled low during at least
■ Voltage Drop RESET
The device RESET pin acts as an output that is
pulled low when V <V
(rising edge) or
DD
IT+
t
.
w(RSTL)out
V
<V (falling edge) as shown in Figure 14.
DD
IT-
6.3.3 External Power-On RESET
The LVD filters spikes on V larger than t
avoid parasitic resets.
to
DD
g(VDD)
If the LVD is disabled by option byte, to start up the
microcontroller correctly, the user must ensure by
means of an external reset circuit that the reset
6.3.5 Internal Watchdog RESET
signal is held low until V
level specified for the selected f
(see “OPERATING CONDITIONS” on page 167)
is over the minimum
DD
The RESET sequence generated by a internal
Watchdog counter overflow is shown in Figure 14.
frequency.
OSC
Starting from the Watchdog counter underflow, the
device RESET pin acts as an output that is pulled
low during at least t
.
w(RSTL)out
Figure 14. RESET Sequences
V
DD
V
V
IT+(LVD)
IT-(LVD)
LVD
RESET
SHORT EXT.
RESET
LONG EXT.
RESET
WATCHDOG
RESET
RUN
RUN
RUN
RUN
RUN
ACTIVE
PHASE
ACTIVE
PHASE
ACTIVE
PHASE
ACTIVE PHASE
t
t
t
w(RSTL)out
h(RSTL)in
w(RSTL)out
t
w(RSTL)out
t
h(RSTL)in
DELAY
EXTERNAL
RESET
SOURCE
RESET PIN
WATCHDOG
RESET
WATCHDOG UNDERFLOW
INTERNAL RESET (256 or 4096 TCPU
VECTOR FETCH
)
27/215
ST72F521, ST72521B
6.4 SYSTEM INTEGRITY MANAGEMENT (SI)
The System Integrity Management block contains
the Low Voltage Detector (LVD) and Auxiliary Volt-
age Detector (AVD) functions. It is managed by
the SICSR register.
– under full software control
– in static safe reset
In these conditions, secure operation is always en-
sured for the application without the need for ex-
ternal reset hardware.
6.4.1 Low Voltage Detector (LVD)
The Low Voltage Detector function (LVD) gener-
During a Low Voltage Detector Reset, the RESET
pin is held low, thus permitting the MCU to reset
other devices.
ates a static reset when the V supply voltage is
DD
below a V reference value. This means that it
IT-
secures the power-up as well as the power-down
keeping the ST7 in reset.
Notes:
The V reference value for a voltage drop is lower
IT-
The LVD allows the device to be used without any
external RESET circuitry.
than the V reference value for power-on in order
IT+
to avoid a parasitic reset when the MCU starts run-
ning and sinks current on the supply (hysteresis).
If the medium or low thresholds are selected, the
detection may occur outside the specified operat-
ing voltage range. Below 3.8V, device operation is
not guaranteed.
The LVD Reset circuitry generates a reset when
V
is below:
DD
– V when V is rising
IT+
DD
The LVD is an optional function which can be se-
lected by option byte.
– V when V is falling
IT-
DD
The LVD function is illustrated in Figure 15.
It is recommended to make sure that the V sup-
DD
The voltage threshold can be configured by option
byte to be low, medium or high.
ply voltage rises monotonously when the device is
exiting from Reset, to ensure the application func-
tions properly.
Provided the minimum V value (guaranteed for
DD
the oscillator frequency) is above V , the MCU
IT-
can only be in two modes:
Figure 15. Low Voltage Detector vs Reset
V
DD
V
hys
V
V
IT+
IT-
RESET
28/215
ST72F521, ST72521B
SYSTEM INTEGRITY MANAGEMENT (Cont’d)
6.4.2 Auxiliary Voltage Detector (AVD)
In the case of a drop in voltage, the AVD interrupt
acts as an early warning, allowing software to shut
down safely before the LVD resets the microcon-
troller. See Figure 16.
The Voltage Detector function (AVD) is based on
an analog comparison between a V
and
main sup-
IT-(AVD)
V
reference value and the V
IT+(AVD)
DD
ply or the external EVD pin voltage level (V
).
The interrupt on the rising edge is used to inform
EVD
The V reference value for falling voltage is lower
the application that the V warning state is over.
IT-
DD
than the V
reference value for rising voltage in
IT+
If the voltage rise time t is less than 256 or 4096
rv
order to avoid parasitic detection (hysteresis).
CPU cycles (depending on the reset delay select-
ed by option byte), no AVD interrupt will be gener-
The output of the AVD comparator is directly read-
able by the application software through a real
time status bit (AVDF) in the SICSR register. This
bit is read only.
Caution: The AVD function is active only if the
LVD is enabled through the option byte.
ated when V
is reached.
IT+(AVD)
If t is greater than 256 or 4096 cycles then:
rv
– If the AVD interrupt is enabled before the
V
threshold is reached, then 2 AVD inter-
IT+(AVD)
rupts will be received: the first when the AVDIE
bit is set, and the second when the threshold is
reached.
6.4.2.1 Monitoring the V Main Supply
DD
This mode is selected by clearing the AVDS bit in
the SICSR register.
– If the AVD interrupt is enabled after the V
IT+(AVD)
threshold is reached then only one AVD interrupt
will occur.
The AVD voltage threshold value is relative to the
selected LVD threshold configured by option byte
(see section 14.1 on page 201).
If the AVD interrupt is enabled, an interrupt is gen-
erated when the voltage crosses the V
or
IT+(AVD)
V
threshold (AVDF bit toggles).
IT-(AVD)
Figure 16. Using the AVD to Monitor V (AVDS bit=0)
DD
V
DD
Early Warning Interrupt
(Power has dropped, MCU not
not yet in reset)
V
hyst
V
IT+(AVD)
V
IT-(AVD)
V
V
IT+(LVD)
t
VOLTAGE RISE TIME
rv
IT-(LVD)
1
1
AVDF bit
0
RESET VALUE
0
AVD INTERRUPT
REQUEST
IF AVDIE bit = 1
INTERRUPT PROCESS
INTERRUPT PROCESS
LVD RESET
29/215
ST72F521, ST72521B
SYSTEM INTEGRITY MANAGEMENT (Cont’d)
6.4.2.2 Monitoring a Voltage on the EVD pin
of the comparator output. This means it is generat-
ed when either one of these two events occur:
This mode is selected by setting the AVDS bit in
the SICSR register.
– V
– V
rises up to V
IT+(EVD)
EVD
EVD
falls down to V
The AVD circuitry can generate an interrupt when
the AVDIE bit of the SICSR register is set. This in-
terrupt is generated on the rising and falling edges
IT-(EVD)
The EVD function is illustrated in Figure 17.
For more details, refer to the Electrical Character-
istics section.
Figure 17. Using the Voltage Detector to Monitor the EVD pin (AVDS bit=1)
V
EVD
V
hyst
V
V
IT+(EVD)
IT-(EVD)
AVDF
0
1
0
AVD INTERRUPT
REQUEST
IF AVDIE = 1
INTERRUPT PROCESS
INTERRUPT PROCESS
30/215
ST72F521, ST72521B
SYSTEM INTEGRITY MANAGEMENT (Cont’d)
6.4.3 Low Power Modes
set and the interrupt mask in the CC register is re-
set (RIM instruction).
Mode
Description
Enable Exit
Control from
Exit
from
Halt
No effect on SI. AVD interrupts cause the
device to exit from Wait mode.
Event
Flag
WAIT
HALT
Interrupt Event
Bit
Wait
The CRSR register is frozen.
AVD event
AVDF AVDIE
Yes
No
6.4.3.1 Interrupts
The AVD interrupt event generates an interrupt if
the corresponding Enable Control Bit (AVDIE) is
31/215
ST72F521, ST72521B
SYSTEM INTEGRITY MANAGEMENT (Cont’d)
6.4.4 Register Description
SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR)
Read/Write
ed by the LVD block. It is set by hardware (LVD re-
set) and cleared by software (writing zero). See
WDGRF flag description for more details. When
the LVD is disabled by OPTION BYTE, the LVDRF
bit value is undefined.
Reset Value: 000x 000x (00h)
7
0
AVD
IE
AVD
S
AVD LVD
RF
WDG
RF
0
0
0
F
Bits 3:1 = Reserved, must be kept cleared.
Bit 7 = AVDS Voltage Detection selection
Bit 0 = WDGRF Watchdog reset flag
This bit is set and cleared by software. Voltage De-
tection is available only if the LVD is enabled by
option byte.
This bit indicates that the last Reset was generat-
ed by the Watchdog peripheral. It is set by hard-
ware (watchdog reset) and cleared by software
(writing zero) or an LVD Reset (to ensure a stable
cleared state of the WDGRF flag when CPU
starts).
0: Voltage detection on V supply
DD
1: Voltage detection on EVD pin
Combined with the LVDRF flag information, the
flag description is given by the following table.
Bit 6 = AVDIE Voltage Detector interrupt enable
This bit is set and cleared by software. It enables
an interrupt to be generated when the AVDF flag
changes (toggles). The pending interrupt informa-
tion is automatically cleared when software enters
the AVD interrupt routine.
RESET Sources
LVDRF WDGRF
External RESET pin
Watchdog
0
0
1
0
1
0: AVD interrupt disabled
1: AVD interrupt enabled
LVD
X
Application notes
Bit 5 = AVDF Voltage Detector flag
This read-only bit is set and cleared by hardware.
If the AVDIE bit is set, an interrupt request is gen-
erated when the AVDF bit changes value. Refer to
Figure 16 and to Section 6.4.2.1 for additional de-
tails.
The LVDRF flag is not cleared when another RE-
SET type occurs (external or watchdog), the
LVDRF flag remains set to keep trace of the origi-
nal failure.
In this case, a watchdog reset can be detected by
software while an external reset can not.
0: V or V
over V
under V
IT-(AVD)
threshold
threshold
DD
EVD
EVD
IT+(AVD)
1: V or V
DD
CAUTION: When the LVD is not activated with the
associated option byte, the WDGRF flag can not
be used in the application.
Bit 4 = LVDRF LVD reset flag
This bit indicates that the last Reset was generat-
32/215
ST72F521, ST72521B
7 INTERRUPTS
7.1 INTRODUCTION
each interrupt vector (see Table 5). The process-
ing flow is shown in Figure 18
The ST7 enhanced interrupt management pro-
vides the following features:
When an interrupt request has to be serviced:
– Normal processing is suspended at the end of
the current instruction execution.
■ Hardware interrupts
■ Software interrupt (TRAP)
■ Nested or concurrent interrupt management
with flexible interrupt priority and level
management:
– The PC, X, A and CC registers are saved onto
the stack.
– I1 and I0 bits of CC register are set according to
the corresponding values in the ISPRx registers
of the serviced interrupt vector.
– Up to 4 software programmable nesting levels
– Up to 16 interrupt vectors fixed by hardware
– 2 non maskable events: RESET, TRAP
– 1 maskable Top Level event: TLI
– The PC is then loaded with the interrupt vector of
the interrupt to service and the first instruction of
the interrupt service routine is fetched (refer to
“Interrupt Mapping” table for vector addresses).
This interrupt management is based on:
The interrupt service routine should end with the
IRET instruction which causes the contents of the
saved registers to be recovered from the stack.
– Bit 5 and bit 3 of the CPU CC register (I1:0),
– Interrupt software priority registers (ISPRx),
– Fixed interrupt vector addresses located at the
high addresses of the memory map (FFE0h to
FFFFh) sorted by hardware priority order.
Note: As a consequence of the IRET instruction,
the I1 and I0 bits will be restored from the stack
and the program in the previous level will resume.
This enhanced interrupt controller guarantees full
upward compatibility with the standard (not nest-
ed) ST7 interrupt controller.
Table 5. Interrupt Software Priority Levels
Interrupt software priority Level
I1
1
I0
0
7.2 MASKING AND PROCESSING FLOW
Level 0 (main)
Level 1
Low
0
1
The interrupt masking is managed by the I1 and I0
bits of the CC register and the ISPRx registers
which give the interrupt software priority level of
Level 2
0
0
Level 3 (= interrupt disable)
High
1
1
Figure 18. Interrupt Processing Flowchart
PENDING
INTERRUPT
Y
Y
RESET
TRAP
N
Interrupt has the same or a
lower software priority
than current one
N
I1:0
FETCH NEXT
INSTRUCTION
THE INTERRUPT
STAYS PENDING
Y
“IRET”
N
RESTORE PC, X, A, CC
FROM STACK
EXECUTE
INSTRUCTION
STACK PC, X, A, CC
LOAD I1:0 FROM INTERRUPT SW REG.
LOAD PC FROM INTERRUPT VECTOR
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ST72F521, ST72521B
INTERRUPTS (Cont’d)
Servicing Pending Interrupts
■ TRAP (Non Maskable Software Interrupt)
As several interrupts can be pending at the same
time, the interrupt to be taken into account is deter-
mined by the following two-step process:
This software interrupt is serviced when the TRAP
instruction is executed. It will be serviced accord-
ing to the flowchart in Figure 18.
– the highest software priority interrupt is serviced,
Caution: TRAP can be interrupted by a TLI.
■ RESET
– if several interrupts have the same software pri-
ority then the interrupt with the highest hardware
priority is serviced first.
The RESET source has the highest priority in the
ST7. This means that the first current routine has
the highest software priority (level 3) and the high-
est hardware priority.
Figure 19 describes this decision process.
Figure 19. Priority Decision Process
See the RESET chapter for more details.
PENDING
INTERRUPTS
Maskable Sources
Maskable interrupt vector sources can be serviced
if the corresponding interrupt is enabled and if its
own interrupt software priority (in ISPRx registers)
is higher than the one currently being serviced (I1
and I0 in CC register). If any of these two condi-
tions is false, the interrupt is latched and thus re-
mains pending.
Different
Same
SOFTWARE
PRIORITY
■ TLI (Top Level Hardware Interrupt)
HIGHEST SOFTWARE
PRIORITY SERVICED
This hardware interrupt occurs when a specific
edge is detected on the dedicated TLI pin. It will be
serviced according to the flowchart in Figure 18 as
a trap.
HIGHEST HARDWARE
PRIORITY SERVICED
Caution: A TRAP instruction must not be used in a
TLI service routine.
When an interrupt request is not serviced immedi-
ately, it is latched and then processed when its
software priority combined with the hardware pri-
ority becomes the highest one.
■ External Interrupts
External interrupts allow the processor to exit from
HALT low power mode. External interrupt sensitiv-
ity is software selectable through the External In-
terrupt Control register (EICR).
External interrupt triggered on edge will be latched
and the interrupt request automatically cleared
upon entering the interrupt service routine.
If several input pins of a group connected to the
same interrupt line are selected simultaneously,
these will be logically ORed.
Note 1: The hardware priority is exclusive while
the software one is not. This allows the previous
process to succeed with only one interrupt.
Note 2: TLI, RESET and TRAP can be considered
as having the highest software priority in the deci-
sion process.
Different Interrupt Vector Sources
■ Peripheral Interrupts
Two interrupt source types are managed by the
ST7 interrupt controller: the non-maskable type
(RESET, TRAP) and the maskable type (external
or from internal peripherals).
Usually the peripheral interrupts cause the MCU to
exit from HALT mode except those mentioned in
the “Interrupt Mapping” table. A peripheral inter-
rupt occurs when a specific flag is set in the pe-
ripheral status registers and if the corresponding
enable bit is set in the peripheral control register.
The general sequence for clearing an interrupt is
based on an access to the status register followed
by a read or write to an associated register.
Note: The clearing sequence resets the internal
latch. A pending interrupt (i.e. waiting for being
serviced) will therefore be lost if the clear se-
quence is executed.
Non-Maskable Sources
These sources are processed regardless of the
state of the I1 and I0 bits of the CC register (see
Figure 18). After stacking the PC, X, A and CC
registers (except for RESET), the corresponding
vector is loaded in the PC register and the I1 and
I0 bits of the CC are set to disable interrupts (level
3). These sources allow the processor to exit
HALT mode.
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ST72F521, ST72521B
INTERRUPTS (Cont’d)
7.3 INTERRUPTS AND LOW POWER MODES
7.4 CONCURRENT & NESTED MANAGEMENT
All interrupts allow the processor to exit the WAIT
low power mode. On the contrary, only external
and other specified interrupts allow the processor
to exit from the HALT modes (see column “Exit
from HALT” in “Interrupt Mapping” table). When
several pending interrupts are present while exit-
ing HALT mode, the first one serviced can only be
an interrupt with exit from HALT mode capability
and it is selected through the same decision proc-
ess shown in Figure 19.
The following Figure 20 and Figure 21 show two
different interrupt management modes. The first is
called concurrent mode and does not allow an in-
terrupt to be interrupted, unlike the nested mode in
Figure 21. The interrupt hardware priority is given
in this order from the lowest to the highest: MAIN,
IT4, IT3, IT2, IT1, IT0, TLI. The software priority is
given for each interrupt.
Warning: A stack overflow may occur without no-
tifying the software of the failure.
Note: If an interrupt, that is not able to Exit from
HALT mode, is pending with the highest priority
when exiting HALT mode, this interrupt is serviced
after the first one serviced.
Figure 20. Concurrent Interrupt Management
SOFTWARE
PRIORITY
LEVEL
I1
I0
TRAP
3
1 1
1 1
1 1
1 1
1 1
1 1
IT0
3
IT1
IT1
3
IT2
3
IT3
3
RIM
IT4
3
MAIN
MAIN
3/0
11 / 10
10
Figure 21. Nested Interrupt Management
SOFTWARE
PRIORITY
LEVEL
I1
I0
TRAP
3
1 1
1 1
0 0
0 1
1 1
1 1
IT0
3
IT1
IT1
IT2
2
IT2
1
IT3
3
RIM
IT4
IT4
3
MAIN
MAIN
3/0
11 / 10
10
35/215
ST72F521, ST72521B
INTERRUPTS (Cont’d)
7.5 INTERRUPT REGISTER DESCRIPTION
INTERRUPT SOFTWARE PRIORITY REGIS-
TERS (ISPRX)
CPU CC REGISTER INTERRUPT BITS
Read/Write
Read/Write (bit 7:4 of ISPR3 are read only)
Reset Value: 1111 1111 (FFh)
Reset Value: 111x 1010 (xAh)
7
0
7
0
ISPR0
ISPR1
I1_3 I0_3 I1_2 I0_2 I1_1 I0_1 I1_0 I0_0
I1_7 I0_7 I1_6 I0_6 I1_5 I0_5 I1_4 I0_4
1
1
I1
H
I0
N
Z
C
Bit 5, 3 = I1, I0 Software Interrupt Priority
ISPR2 I1_11 I0_11 I1_10 I0_10 I1_9 I0_9 I1_8 I0_8
These two bits indicate the current interrupt soft-
ware priority.
ISPR3
1
1
1
1
I1_13 I0_13 I1_12 I0_12
Interrupt Software Priority Level
I1
1
I0
0
Level 0 (main)
Level 1
Low
These four registers contain the interrupt software
priority of each interrupt vector.
0
1
Level 2
0
0
– Each interrupt vector (except RESET and TRAP)
has corresponding bits in these registers where
its own software priority is stored. This corre-
spondance is shown in the following table.
Level 3 (= interrupt disable*)
High
1
1
These two bits are set/cleared by hardware when
entering in interrupt. The loaded value is given by
the corresponding bits in the interrupt software pri-
ority registers (ISPRx).
Vector address
ISPRx bits
FFFBh-FFFAh
FFF9h-FFF8h
...
I1_0 and I0_0 bits*
I1_1 and I0_1 bits
...
They can be also set/cleared by software with the
RIM, SIM, HALT, WFI, IRET and PUSH/POP in-
structions (see “Interrupt Dedicated Instruction
Set” table).
FFE1h-FFE0h
I1_13 and I0_13 bits
*Note: TLI, TRAP and RESET events can interrupt
a level 3 program.
– Each I1_x and I0_x bit value in the ISPRx regis-
ters has the same meaning as the I1 and I0 bits
in the CC register.
– Level 0 can not be written (I1_x=1, I0_x=0). In
this case, the previously stored value is kept. (ex-
ample: previous=CFh, write=64h, result=44h)
The TLI, RESET, and TRAP vectors have no soft-
ware priorities. When one is serviced, the I1 and I0
bits of the CC register are both set.
*Note: Bits in the ISPRx registers which corre-
spond to the TLI can be read and written but they
are not significant in the interrupt process man-
agement.
Caution: If the I1_x and I0_x bits are modified
while the interrupt x is executed the following be-
haviour has to be considered: If the interrupt x is
still pending (new interrupt or flag not cleared) and
the new software priority is higher than the previ-
ous one, the interrupt x is re-entered. Otherwise,
the software priority stays unchanged up to the
next interrupt request (after the IRET of the inter-
rupt x).
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ST72F521, ST72521B
INTERRUPTS (Cont’d)
Table 6. Dedicated Interrupt Instruction Set
Instruction
New Description
Entering Halt mode
Function/Example
I1
H
I0
N
Z
C
HALT
IRET
JRM
1
0
Interrupt routine return
Jump if I1:0=11 (level 3)
Jump if I1:0<>11
Pop CC, A, X, PC
I1:0=11 ?
I1
H
I0
N
Z
C
JRNM
POP CC
RIM
I1:0<>11 ?
Pop CC from the Stack
Enable interrupt (level 0 set)
Disable interrupt (level 3 set)
Software trap
Mem => CC
I1
1
H
I0
0
1
1
0
N
Z
C
Load 10 in I1:0 of CC
Load 11 in I1:0 of CC
Software NMI
SIM
1
TRAP
WFI
1
Wait for interrupt
1
Note: During the execution of an interrupt routine, the HALT, POPCC, RIM, SIM and WFI instructions change the current
software priority up to the next IRET instruction or one of the previously mentioned instructions.
37/215
ST72F521, ST72521B
INTERRUPTS (Cont’d)
Table 7. Interrupt Mapping
Exit
from
Source
Block
Register Priority
Address
Vector
N°
Description
HALT/
ACTIVE
Label
Order
3)
HALT
RESET
TRAP
TLI
Reset
yes
no
FFFEh-FFFFh
FFFCh-FFFDh
FFFAh-FFFBh
FFF8h-FFF9h
FFF6h-FFF7h
FFF4h-FFF5h
FFF2h-FFF3h
FFF0h-FFF1h
FFEEh-FFEFh
FFECh-FFEDh
FFEAh-FFEBh
FFE8h-FFE9h
FFE6h-FFE7h
FFE4h-FFE5h
FFE2h-FFE3h
FFE0h-FFE1h
N/A
Software interrupt
0
1
External top level interrupt
Main clock controller time base interrupt
External interrupt port A3..0
External interrupt port F2..0
External interrupt port B3..0
External interrupt port B7..4
CAN peripheral interrupts
SPI peripheral interrupts
EICR
yes
yes
yes
yes
yes
yes
yes
MCC/RTC
ei0
MCCSR
Higher
Priority
2
3
ei1
N/A
4
ei2
5
ei3
6
CAN
CANISR
SPICSR
TASR
1
7
SPI
yes
8
TIMER A
TIMER B
SCI
TIMER A peripheral interrupts
TIMER B peripheral interrupts
SCI Peripheral interrupts
Auxiliary Voltage detector interrupt
I2C Peripheral interrupts
no
no
no
no
no
9
TBSR
10
11
12
13
SCISR
Lower
Priority
AVD
SICSR
I2C
(see periph)
ARTCSR
2
PWM ART
PWM ART interrupt
yes
Notes:
1. Exit from HALT possible when SPI is in slave mode.
2. Exit from HALT possible when PWM ART is in external clock mode.
3. In Flash devices only a RESET or MCC/RTC interrupt can be used to wake-up from Active Halt mode.
7.6 EXTERNAL INTERRUPTS
7.6.1 I/O Port Interrupt Sensitivity
■ Falling edge and low level
■ Rising edge and high level (only for ei0 and ei2)
The external interrupt sensitivity is controlled by
the IPA, IPB and ISxx bits of the EICR register
(Figure 22). This control allows to have up to 4 fully
independent external interrupt source sensitivities.
To guarantee correct functionality, the sensitivity
bits in the EICR register can be modified only
when the I1 and I0 bits of the CC register are both
set to 1 (level 3). This means that interrupts must
be disabled before changing sensitivity.
Each external interrupt source can be generated
on four (or five) different events on the pin:
■ Falling edge
■ Rising edge
■ Falling and rising edge
The pending interrupts are cleared by writing a dif-
ferent value in the ISx[1:0], IPA or IPB bits of the
EICR.
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ST72F521, ST72521B
INTERRUPTS (Cont’d)
Figure 22. External Interrupt Control bits
EICR
IS20 IS21
PORT A [3:0] INTERRUPTS
PAOR.3
PADDR.3
SENSITIVITY
CONTROL
PA3
PA2
PA1
PA0
PA3
ei0 INTERRUPT SOURCE
IPA BIT
EICR
PORT F [2:0] INTERRUPTS
IS20
IS21
PFOR.2
PFDDR.2
SENSITIVITY
CONTROL
PF2
PF1
PF0
ei1 INTERRUPT SOURCE
PF2
EICR
PORT B [3:0] INTERRUPTS
IS10
IS11
PBOR.3
PBDDR.3
SENSITIVITY
CONTROL
PB3
PB2
PB1
PB0
PB3
ei2 INTERRUPT SOURCE
IPB BIT
EICR
PORT B [7:4] INTERRUPTS
IS10
IS11
PBOR.7
PBDDR.7
SENSITIVITY
CONTROL
PB7
PB6
PB5
PB4
ei3 INTERRUPT SOURCE
PB7
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ST72F521, ST72521B
7.7 EXTERNAL INTERRUPT CONTROL REGISTER (EICR)
Read/Write
- ei0 (port A3..0)
Reset Value: 0000 0000 (00h)
External Interrupt Sensitivity
IS21 IS20
7
0
IPA bit =0
IPA bit =1
Falling edge &
low level
Rising edge
& high level
0
0
IS11 IS10 IPB IS21 IS20 IPA TLIS TLIE
0
1
1
1
0
1
Rising edge only
Falling edge only
Falling edge only
Rising edge only
Bit 7:6 = IS1[1:0] ei2 and ei3 sensitivity
The interrupt sensitivity, defined using the IS1[1:0]
bits, is applied to the following external interrupts:
- ei2 (port B3..0)
Rising and falling edge
External Interrupt Sensitivity
IS11 IS10
- ei1 (port F2..0)
IPB bit =0
IPB bit =1
IS21 IS20
External Interrupt Sensitivity
Falling edge &
low level
Rising edge
& high level
0
0
1
1
0
1
0
1
Falling edge & low level
Rising edge only
0
0
0
1
1
1
0
1
Rising edge only
Falling edge only
Falling edge only
Rising edge only
Falling edge only
Rising and falling edge
Rising and falling edge
These 2 bits can be written only when I1 and I0 of
the CC register are both set to 1 (level 3).
- ei3 (port B7..4)
IS11 IS10
External Interrupt Sensitivity
Bit 2 = IPA Interrupt polarity for port A
This bit is used to invert the sensitivity of the port A
[3:0] external interrupts. It can be set and cleared
by software only when I1 and I0 of the CC register
are both set to 1 (level 3).
0
0
1
1
0
1
0
1
Falling edge & low level
Rising edge only
Falling edge only
Rising and falling edge
0: No sensitivity inversion
1: Sensitivity inversion
These 2 bits can be written only when I1 and I0 of
the CC register are both set to 1 (level 3).
Bit 1 = TLIS TLI sensitivity
Bit 5 = IPB Interrupt polarity for port B
This bit is used to invert the sensitivity of the port B
[3:0] external interrupts. It can be set and cleared
by software only when I1 and I0 of the CC register
are both set to 1 (level 3).
This bit allows to toggle the TLI edge sensitivity. It
can be set and cleared by software only when
TLIE bit is cleared.
0: Falling edge
1: Rising edge
0: No sensitivity inversion
1: Sensitivity inversion
Bit 0 = TLIE TLI enable
This bit allows to enable or disable the TLI capabil-
ity on the dedicated pin. It is set and cleared by
software.
Bit 4:3 = IS2[1:0] ei0 and ei1 sensitivity
The interrupt sensitivity, defined using the IS2[1:0]
bits, is applied to the following external interrupts:
0: TLI disabled
1: TLI enabled
Note: a parasitic interrupt can be generated when
clearing the TLIE bit.
40/215
ST72F521, ST72521B
INTERRUPTS (Cont’d)
Table 8. Nested Interrupts Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
ei1
SPI
ei0
CAN
SCI
MCC
ei3
TLI
ei2
0024h
0025h
0026h
I1_3
1
I0_3
1
I1_2
1
I0_2
1
I1_1
1
I0_1
1
ISPR0
Reset Value
1
1
I1_7
1
I0_7
1
I1_6
1
I0_6
1
I1_5
1
I0_5
1
I1_4
1
I0_4
1
ISPR1
Reset Value
AVD
TIMER B
TIMER A
I1_11
1
I0_11
1
I1_10
1
I0_10
1
I1_9
1
I0_9
1
I1_8
1
I0_8
1
ISPR2
Reset Value
PWMART
I2C
0027h
0028h
I1_13
1
I0_13
1
I1_12
1
I0_12
1
ISPR3
Reset Value
1
1
1
1
EICR
Reset Value
IS11
0
IS10
0
IPB
0
IS21
0
IS20
0
IPA
0
TLIS
0
TLIE
0
41/215
ST72F521, ST72521B
8 POWER SAVING MODES
8.1 INTRODUCTION
8.2 SLOW MODE
To give a large measure of flexibility to the applica-
tion in terms of power consumption, four main
power saving modes are implemented in the ST7
(see Figure 23): SLOW, WAIT (SLOW WAIT), AC-
TIVE HALT and HALT.
This mode has two targets:
– To reduce power consumption by decreasing the
internal clock in the device,
– To adapt the internal clock frequency (f
the available supply voltage.
) to
CPU
After a RESET the normal operating mode is se-
lected by default (RUN mode). This mode drives
the device (CPU and embedded peripherals) by
means of a master clock which is based on the
main oscillator frequency divided or multiplied by 2
SLOW mode is controlled by three bits in the
MCCSR register: the SMS bit which enables or
disables Slow mode and two CPx bits which select
the internal slow frequency (f
).
CPU
(f
).
In this mode, the master clock frequency (f
)
OSC2
OSC2
can be divided by 2, 4, 8 or 16. The CPU and pe-
ripherals are clocked at this lower frequency
From RUN mode, the different power saving
modes may be selected by setting the relevant
register bits or by calling the specific ST7 software
instruction whose action depends on the oscillator
status.
(f
).
CPU
Note: SLOW-WAIT mode is activated when enter-
ing the WAIT mode while the device is already in
SLOW mode.
Figure 23. Power Saving Mode Transitions
Figure 24. SLOW Mode Clock Transitions
High
RUN
f
/2
f
/4
f
OSC2
OSC2
OSC2
f
CPU
f
OSC2
SLOW
WAIT
00
01
CP1:0
SMS
SLOW WAIT
ACTIVE HALT
HALT
NORMAL RUN MODE
REQUEST
NEW SLOW
FREQUENCY
REQUEST
Low
POWER CONSUMPTION
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ST72F521, ST72521B
POWER SAVING MODES (Cont’d)
8.3 WAIT MODE
Figure 25. WAIT Mode Flow-chart
WAIT mode places the MCU in a low power con-
sumption mode by stopping the CPU.
This power saving mode is selected by calling the
‘WFI’ instruction.
OSCILLATOR
PERIPHERALS
CPU
ON
ON
OFF
10
WFI INSTRUCTION
I[1:0] BITS
All peripherals remain active. During WAIT mode,
the I[1:0] bits of the CC register are forced to ‘10’,
to enable all interrupts. All other registers and
memory remain unchanged. The MCU remains in
WAIT mode until an interrupt or RESET occurs,
whereupon the Program Counter branches to the
starting address of the interrupt or Reset service
routine.
N
RESET
Y
N
INTERRUPT
The MCU will remain in WAIT mode until a Reset
or an Interrupt occurs, causing it to wake up.
Y
OSCILLATOR
PERIPHERALS
CPU
ON
OFF
ON
10
Refer to Figure 25.
I[1:0] BITS
256 OR 4096 CPU CLOCK
CYCLE DELAY
OSCILLATOR
PERIPHERALS
CPU
ON
ON
ON
I[1:0] BITS
XX 1)
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Note:
1. Before servicing an interrupt, the CC register is
pushed on the stack. The I[1:0] bits of the CC reg-
ister are set to the current software priority level of
the interrupt routine and recovered when the CC
register is popped.
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ST72F521, ST72521B
POWER SAVING MODES (Cont’d)
8.4 ACTIVE-HALT AND HALT MODES
lay depending on option byte). Otherwise, the ST7
enters HALT mode for the remaining t
od.
peri-
DELAY
ACTIVE-HALT and HALT modes are the two low-
est power consumption modes of the MCU. They
are both entered by executing the ‘HALT’ instruc-
tion. The decision to enter either in ACTIVE-HALT
or HALT mode is given by the MCC/RTC interrupt
enable flag (OIE bit in MCCSR register).
Figure 26. ACTIVE-HALT Timing Overview
ACTIVE
HALT
256 OR 4096 CPU
CYCLE DELAY
RUN
RUN
1)
MCCSR Power Saving Mode entered when HALT
RESET
OR
INTERRUPT
OIE bit
instruction is executed
HALT mode
ACTIVE-HALT mode
HALT
INSTRUCTION
[MCCSR.OIE=1]
FETCH
VECTOR
0
1
Figure 27. ACTIVE-HALT Mode Flow-chart
8.4.1 ACTIVE-HALT MODE
OSCILLATOR
PERIPHERALS
CPU
ON
OFF
OFF
10
ACTIVE-HALT mode is the lowest power con-
sumption mode of the MCU with a real time clock
available. It is entered by executing the ‘HALT’ in-
struction when the OIE bit of the Main Clock Con-
troller Status register (MCCSR) is set (see section
10.2 on page 58 for more details on the MCCSR
register).
2)
HALT INSTRUCTION
(MCCSR.OIE=1)
I[1:0] BITS
N
RESET
Y
N
The MCU can exit ACTIVE-HALT mode on recep-
tion of an MCC/RTC interrupt or a RESET. In ROM
devices, external interrupts can be used to wake-
up the MCU. When exiting ACTIVE-HALT mode
by means of an interrupt, no 256 or 4096 CPU cy-
cle delay occurs. The CPU resumes operation by
servicing the interrupt or by fetching the reset vec-
tor which woke it up (see Figure 27).
4)
INTERRUPT
Y
OSCILLATOR
PERIPHERALS
CPU
ON
OFF
ON
3)
I[1:0] BITS
XX
256 OR 4096 CPU CLOCK
CYCLE DELAY
When entering ACTIVE-HALT mode, the I[1:0] bits
in the CC register are forced to ‘10b’ to enable in-
terrupts. Therefore, if an interrupt is pending, the
MCU wakes up immediately.
OSCILLATOR
PERIPHERALS
CPU
ON
ON
ON
3)
In ACTIVE-HALT mode, only the main oscillator
and its associated counter (MCC/RTC) are run-
ning to keep a wake-up time base. All other periph-
erals are not clocked except those which get their
clock supply from another clock generator (such
as external or auxiliary oscillator).
I[1:0] BITS
XX
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Notes:
The safeguard against staying locked in ACTIVE-
HALT mode is provided by the oscillator interrupt.
1. This delay occurs only if the MCU exits ACTIVE-
HALT mode by means of a RESET.
2. Peripheral clocked with an external clock source
can still be active.
Note: As soon as the interrupt capability of one of
the oscillators is selected (MCCSR.OIE bit set),
entering ACTIVE-HALT mode while the Watchdog
is active does not generate a RESET.
This means that the device cannot spend more
than a defined delay in this power saving mode.
3. Before servicing an interrupt, the CC register is
pushed on the stack. The I[1:0] bits of the CC reg-
ister are set to the current software priority level of
the interrupt routine and restored when the CC
register is popped.
CAUTION: When exiting ACTIVE-HALT mode fol-
lowing an MCC/RTC interrupt, OIE bit of MCCSR
4. In flash devices only the MCC/RTC interrupt can
exit the MCU from ACTIVE-HALT mode.
register must not be cleared before t
after
DELAY
the interrupt occurs (t
= 256 or 4096 t
de-
DELAY
CPU
44/215
ST72F521, ST72521B
POWER SAVING MODES (Cont’d)
8.4.2 HALT MODE
Figure 29. HALT Mode Flow-chart
The HALT mode is the lowest power consumption
mode of the MCU. It is entered by executing the
‘HALT’ instruction when the OIE bit of the Main
Clock Controller Status register (MCCSR) is
cleared (see section 10.2 on page 58 for more de-
tails on the MCCSR register).
HALT INSTRUCTION
(MCCSR.OIE=0)
ENABLE
WATCHDOG
DISABLE
0
WDGHALT 1)
1
The MCU can exit HALT mode on reception of ei-
ther a specific interrupt (see Table 7, “Interrupt
Mapping,” on page 38) or a RESET. When exiting
HALT mode by means of a RESET or an interrupt,
the oscillator is immediately turned on and the 256
or 4096 CPU cycle delay is used to stabilize the
oscillator. After the start up delay, the CPU
resumes operation by servicing the interrupt or by
fetching the reset vector which woke it up (see Fig-
ure 29).
When entering HALT mode, the I[1:0] bits in the
CC register are forced to ‘10b’to enable interrupts.
Therefore, if an interrupt is pending, the MCU
wakes up immediately.
WATCHDOG
RESET
OSCILLATOR
OFF
OFF
OFF
10
PERIPHERALS 2)
CPU
I[1:0] BITS
N
RESET
Y
N
INTERRUPT 3)
In HALT mode, the main oscillator is turned off
causing all internal processing to be stopped, in-
cluding the operation of the on-chip peripherals.
All peripherals are not clocked except the ones
which get their clock supply from another clock
generator (such as an external or auxiliary oscilla-
tor).
Y
OSCILLATOR
PERIPHERALS
CPU
ON
OFF
ON
I[1:0] BITS
XX 4)
256 OR 4096 CPU CLOCK
CYCLE DELAY
The compatibility of Watchdog operation with
HALT mode is configured by the “WDGHALT” op-
tion bit of the option byte. The HALT instruction
when executed while the Watchdog system is en-
abled, can generate a Watchdog RESET (see sec-
tion 14.1 on page 201 for more details).
OSCILLATOR
PERIPHERALS
CPU
ON
ON
ON
I[1:0] BITS
XX 4)
Figure 28. HALT Timing Overview
FETCH RESET VECTOR
OR SERVICE INTERRUPT
256 OR 4096 CPU
CYCLE DELAY
RUN
HALT
RUN
Notes:
RESET
OR
INTERRUPT
1. WDGHALT is an option bit. See option byte sec-
tion for more details.
HALT
INSTRUCTION
[MCCSR.OIE=0]
2. Peripheral clocked with an external clock source
can still be active.
FETCH
VECTOR
3. Only some specific interrupts can exit the MCU
from HALT mode (such as external interrupt). Re-
fer to Table 7, “Interrupt Mapping,” on page 38 for
more details.
4. Before servicing an interrupt, the CC register is
pushed on the stack. The I[1:0] bits of the CC reg-
ister are set to the current software priority level of
the interrupt routine and recovered when the CC
register is popped.
45/215
ST72F521, ST72521B
POWER SAVING MODES (Cont’d)
8.4.2.1 Halt Mode Recommendations
ry. For example, avoid defining a constant in
ROM with the value 0x8E.
– Make sure that an external event is available to
wake up the microcontroller from Halt mode.
– As the HALT instruction clears the interrupt mask
in the CC register to allow interrupts, the user
may choose to clear all pending interrupt bits be-
fore executing the HALT instruction. This avoids
entering other peripheral interrupt routines after
executing the external interrupt routine corre-
sponding to the wake-up event (reset or external
interrupt).
– When using an external interrupt to wake up the
microcontroller, reinitialize the corresponding I/O
as “Input Pull-up with Interrupt” before executing
the HALT instruction. The main reason for this is
that the I/O may be wrongly configured due to ex-
ternal interference or by an unforeseen logical
condition.
Related Documentation
– For the same reason, reinitialize the level sensi-
tiveness of each external interrupt as a precau-
tionary measure.
AN 980: ST7 Keypad Decoding Techniques, Im-
plementing Wake-Up on Keystroke
– The opcode for the HALT instruction is 0x8E. To
avoid an unexpected HALT instruction due to a
program counter failure, it is advised to clear all
occurrences of the data value 0x8E from memo-
AN1014: How to Minimize the ST7 Power Con-
sumption
AN1605: Using an active RC to wakeup the
ST7LITE0 from power saving mode
46/215
ST72F521, ST72521B
9 I/O PORTS
9.1 INTRODUCTION
Each pin can independently generate an interrupt
request. The interrupt sensitivity is independently
programmable using the sensitivity bits in the
EICR register.
The I/O ports offer different functional modes:
– transfer of data through digital inputs and outputs
and for specific pins:
Each external interrupt vector is linked to a dedi-
cated group of I/O port pins (see pinout description
and interrupt section). If several input pins are se-
lected simultaneously as interrupt sources, these
are first detected according to the sensitivity bits in
the EICR register and then logically ORed.
– external interrupt generation
– alternate signal input/output for the on-chip pe-
ripherals.
An I/O port contains up to 8 pins. Each pin can be
programmed independently as digital input (with or
without interrupt generation) or digital output.
The external interrupts are hardware interrupts,
which means that the request latch (not accessible
directly by the application) is automatically cleared
when the corresponding interrupt vector is
fetched. To clear an unwanted pending interrupt
by software, the sensitivity bits in the EICR register
must be modified.
9.2 FUNCTIONAL DESCRIPTION
Each port has 2 main registers:
– Data Register (DR)
– Data Direction Register (DDR)
and one optional register:
– Option Register (OR)
9.2.2 Output Modes
The output configuration is selected by setting the
corresponding DDR register bit. In this case, writ-
ing the DR register applies this digital value to the
I/O pin through the latch. Then reading the DR reg-
ister returns the previously stored value.
Each I/O pin may be programmed using the corre-
sponding register bits in the DDR and OR regis-
ters: bit X corresponding to pin X of the port. The
same correspondence is used for the DR register.
Two different output modes can be selected by
software through the OR register: Output push-pull
and open-drain.
The following description takes into account the
OR register, (for specific ports which do not pro-
vide this register refer to the I/O Port Implementa-
tion section). The generic I/O block diagram is
shown in Figure 30
DR register value and output pin status:
DR
0
Push-pull
Open-drain
Vss
V
9.2.1 Input Modes
SS
1
V
Floating
DD
The input configuration is selected by clearing the
corresponding DDR register bit.
9.2.3 Alternate Functions
In this case, reading the DR register returns the
digital value applied to the external I/O pin.
When an on-chip peripheral is configured to use a
pin, the alternate function is automatically select-
ed. This alternate function takes priority over the
standard I/O programming.
Different input modes can be selected by software
through the OR register.
Notes:
When the signal is coming from an on-chip periph-
eral, the I/O pin is automatically configured in out-
put mode (push-pull or open drain according to the
peripheral).
1. Writing the DR register modifies the latch value
but does not affect the pin status.
2. When switching from input to output mode, the
DR register has to be written first to drive the cor-
rect level on the pin as soon as the port is config-
ured as an output.
When the signal is going to an on-chip peripheral,
the I/O pin must be configured in input mode. In
this case, the pin state is also digitally readable by
addressing the DR register.
3. Do not use read/modify/write instructions (BSET
or BRES) to modify the DR register
External interrupt function
Note: Input pull-up configuration can cause unex-
pected value at the input of the alternate peripheral
input. When an on-chip peripheral use a pin as in-
put and output, this pin has to be configured in in-
put floating mode.
When an I/O is configured as Input with Interrupt,
an event on this I/O can generate an external inter-
rupt request to the CPU.
47/215
ST72F521, ST72521B
I/O PORTS (Cont’d)
Figure 30. I/O Port General Block Diagram
ALTERNATE
OUTPUT
1
0
REGISTER
ACCESS
P-BUFFER
(see table below)
V
DD
ALTERNATE
ENABLE
PULL-UP
(see table below)
DR
DDR
OR
V
DD
PULL-UP
CONDITION
PAD
If implemented
OR SEL
DDR SEL
DR SEL
N-BUFFER
DIODES
(see table below)
ANALOG
INPUT
CMOS
SCHMITT
TRIGGER
1
0
ALTERNATE
INPUT
EXTERNAL
INTERRUPT
SOURCE (ei )
x
Table 9. I/O Port Mode Options
Configuration Mode
Diodes
Pull-Up
P-Buffer
to V
to V
SS
DD
Floating with/without Interrupt
Input
Off
On
Off
Pull-up with/without Interrupt
On
Push-pull
On
Off
NI
On
Off
NI
Output
Open Drain (logic level)
True Open Drain
NI (see note)
Legend: NI - not implemented
Off - implemented not activated
On - implemented and activated
Note: The diode to V is not implemented in the
DD
true open drain pads. A local protection between
the pad and V is implemented to protect the de-
SS
vice against positive stress.
48/215
ST72F521, ST72521B
I/O PORTS (Cont’d)
Table 10. I/O Port Configurations
Hardware Configuration
DR REGISTER ACCESS
NOT IMPLEMENTED IN
TRUE OPEN DRAIN
I/O PORTS
V
DD
PULL-UP
CONDITION
R
W
R
PU
DR
REGISTER
DATA BUS
PAD
ALTERNATE INPUT
EXTERNAL INTERRUPT
SOURCE (ei )
x
INTERRUPT
CONDITION
ANALOG INPUT
NOT IMPLEMENTED IN
TRUE OPEN DRAIN
I/O PORTS
DR REGISTER ACCESS
V
DD
R
PU
R/W
DR
REGISTER
DATA BUS
PAD
ALTERNATE
ENABLE
ALTERNATE
OUTPUT
NOT IMPLEMENTED IN
TRUE OPEN DRAIN
I/O PORTS
DR REGISTER ACCESS
V
DD
R
PU
R/W
DR
REGISTER
DATA BUS
PAD
ALTERNATE
ENABLE
ALTERNATE
OUTPUT
Notes:
1. When the I/O port is in input configuration and the associated alternate function is enabled as an output,
reading the DR register will read the alternate function output status.
2. When the I/O port is in output configuration and the associated alternate function is enabled as an input,
the alternate function reads the pin status given by the DR register content.
49/215
ST72F521, ST72521B
I/O PORTS (Cont’d)
CAUTION: The alternate function must not be ac-
tivated as long as the pin is configured as input
with interrupt, in order to avoid generating spurious
interrupts.
Figure 31. Interrupt I/O Port State Transitions
01
00
10
11
Analog alternate function
INPUT
floating/pull-up
interrupt
INPUT
floating
(reset state)
OUTPUT
open-drain
OUTPUT
push-pull
When the pin is used as an ADC input, the I/O
must be configured as floating input. The analog
multiplexer (controlled by the ADC registers)
switches the analog voltage present on the select-
ed pin to the common analog rail which is connect-
ed to the ADC input.
= DDR, OR
XX
9.4 LOW POWER MODES
It is recommended not to change the voltage level
or loading on any port pin while conversion is in
progress. Furthermore it is recommended not to
have clocking pins located close to a selected an-
alog pin.
Mode
WAIT
HALT
Description
No effect on I/O ports. External interrupts
cause the device to exit from WAIT mode.
No effect on I/O ports. External interrupts
cause the device to exit from HALT mode.
WARNING: The analog input voltage level must
be within the limits stated in the absolute maxi-
mum ratings.
9.5 INTERRUPTS
9.3 I/O PORT IMPLEMENTATION
The external interrupt event generates an interrupt
if the corresponding configuration is selected with
DDR and OR registers and the interrupt mask in
the CC register is not active (RIM instruction).
The hardware implementation on each I/O port de-
pends on the settings in the DDR and OR registers
and specific feature of the I/O port such as ADC In-
put or true open drain.
Enable Exit
Control from
Exit
from
Halt
Event
Flag
Interrupt Event
Switching these I/O ports from one state to anoth-
er should be done in a sequence that prevents un-
wanted side effects. Recommended safe transi-
tions are illustrated in Figure 31 Other transitions
are potentially risky and should be avoided, since
they are likely to present unwanted side-effects
such as spurious interrupt generation.
Bit
Wait
External interrupt on
selected external
event
DDRx
ORx
-
Yes
Yes
50/215
ST72F521, ST72521B
I/O PORTS (Cont’d)
9.5.1 I/O Port Implementation
The I/O port register configurations are summa-
rised as follows.
PA3, PB7, PB3, PF2 (without pull-up)
MODE
DDR
OR
0
Standard Ports
floating input
0
0
1
1
floating interrupt input
open drain output
push-pull output
1
PA5:4, PC7:0, PD7:0, PE7:34,
PE1:0, PF7:3, PG7:0, PH7:0
0
1
MODE
DDR
OR
0
floating input
pull-up input
0
0
1
1
1
True Open Drain Ports
PA7:6
open drain output
push-pull output
0
1
MODE
floating input
DDR
0
1
Interrupt Ports
open drain (high sink ports)
PA2:0, PB6:5, PB4, PB2:0, PF1:0 (with pull-up)
MODE
DDR
OR
0
Pull-up Input Port (CANTX requirement)
PE2
floating input
0
0
1
1
pull-up interrupt input
open drain output
push-pull output
1
MODE
0
pull-up input
1
Table 11. Port Configuration
Input
floating
Output
Port
Pin name
PA7:6
OR = 0
OR = 1
OR = 0
OR = 1
true open-drain
PA5:4
PA3
floating
floating
floating
floating
pull-up
open drain
open drain
open drain
open drain
push-pull
push-pull
push-pull
push-pull
Port A
floating interrupt
pull-up interrupt
floating interrupt
PA2:0
PB7, PB3
Port B
PB6:5, PB4,
PB2:0
floating
pull-up interrupt
open drain
push-pull
Port C
Port D
PC7:0
PD7:0
PE7:3, PE1:0
PE2
floating
floating
floating
pull-up
pull-up
pull-up
open drain
open drain
open drain
push-pull
push-pull
push-pull
Port E
pull-up input only *
PF7:3
PF2
floating
floating
floating
floating
floating
pull-up
floating interrupt
pull-up interrupt
pull-up
open drain
open drain
open drain
open drain
open drain
push-pull
push-pull
push-pull
push-pull
push-pull
Port F
PF1:0
PG7:0
PH7:0
Port G
Port H
pull-up
* Note: when the CANTX alternate function is selected the I/O port operates in output push-pull mode.
51/215
ST72F521, ST72521B
I/O PORTS (Cont’d)
Table 12. I/O Port Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
Reset Value
of all I/O port registers
0
0
0
0
0
0
0
0
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
PADR
PADDR
PAOR
PBDR
PBDDR
PBOR
PCDR
PCDDR
PCOR
PDDR
PDDDR
PDOR
PEDR
MSB
MSB
MSB
MSB
MSB
MSB
MSB
MSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
PEDDR
PEOR
PFDR
PFDDR
PFOR
PGDR
PGDDR
PGOR
PHDR
PHDDR
PHOR
Related Documentation
AN1045: S/W implementation of I2C bus master
AN1048: Software LCD driver
AN 970: SPI Communication between ST7 and
EEPROM
52/215
ST72F521, ST72521B
10 ON-CHIP PERIPHERALS
10.1 WATCHDOG TIMER (WDG)
10.1.1 Introduction
If the watchdog is activated (the WDGA bit is set)
and when the 7-bit timer (bits T[6:0]) rolls over
from 40h to 3Fh (T6 becomes cleared), it initiates
a reset cycle pulling low the reset pin for typically
500ns.
The Watchdog timer is used to detect the occur-
rence of a software fault, usually generated by ex-
ternal interference or by unforeseen logical condi-
tions, which causes the application program to
abandon its normal sequence. The Watchdog cir-
cuit generates an MCU reset on expiry of a pro-
grammed time period, unless the program refresh-
es the counter’s contents before the T6 bit be-
comes cleared.
The application program must write in the
WDGCR register at regular intervals during normal
operation to prevent an MCU reset. This down-
counter is free-running: it counts down even if the
watchdog is disabled. The value to be stored in the
WDGCR register must be between FFh and C0h:
10.1.2 Main Features
– The WDGA bit is set (watchdog enabled)
■ Programmable free-running downcounter
■ Programmable reset
■ Reset (if watchdog activated) when the T6 bit
– The T6 bit is set to prevent generating an imme-
diate reset
– The T[5:0] bits contain the number of increments
which represents the time delay before the
watchdog produces a reset (see Figure 33. Ap-
proximate Timeout Duration). The timing varies
between a minimum and a maximum value due
to the unknown status of the prescaler when writ-
ing to the WDGCR register (see Figure 34).
reaches zero
■ Optional
reset
on
HALT
instruction
(configurable by option byte)
■ Hardware Watchdog selectable by option byte
10.1.3 Functional Description
Following a reset, the watchdog is disabled. Once
activated it cannot be disabled, except by a reset.
The counter value stored in the Watchdog Control
register (WDGCR bits T[6:0]), is decremented
every 16384 f
length of the timeout period can be programmed
by the user in 64 increments.
cycles (approx.), and the
The T6 bit can be used to generate a software re-
set (the WDGA bit is set and the T6 bit is cleared).
OSC2
If the watchdog is activated, the HALT instruction
will generate a Reset.
Figure 32. Watchdog Block Diagram
RESET
f
OSC2
MCC/RTC
WATCHDOG CONTROL REGISTER (WDGCR)
T5
DIV 64
WDGA T6
T1
T0
T4
T2
T3
6-BIT DOWNCOUNTER (CNT)
12-BIT MCC
RTC COUNTER
WDG PRESCALER
DIV 4
TB[1:0] bits
(MCCSR
Register)
MSB
LSB
0
6 5
11
53/215
ST72F521, ST72521B
WATCHDOG TIMER (Cont’d)
10.1.4 How to Program the Watchdog Timeout
more precision is needed, use the formulae in Fig-
ure 34.
Figure 33 shows the linear relationship between
the 6-bit value to be loaded in the Watchdog Coun-
ter (CNT) and the resulting timeout duration in mil-
liseconds. This can be used for a quick calculation
without taking the timing variations into account. If
Caution: When writing to the WDGCR register, al-
ways write 1 in the T6 bit to avoid generating an
immediate reset.
Figure 33. Approximate Timeout Duration
3F
38
30
28
20
18
10
08
00
1.5
18
34
50
65
82
98
114
128
Watchdog timeout (ms) @ 8 MHz. f
OSC2
54/215
ST72F521, ST72521B
WATCHDOG TIMER (Cont’d)
Figure 34. Exact Timeout Duration (t
and t
)
max
min
WHERE:
t
t
t
= (LSB + 128) x 64 x t
min0
OSC2
= 16384 x t
= 125ns if f
max0
OSC2
OSC2
=8 MHz
OSC2
CNT = Value of T[5:0] bits in the WDGCR register (6 bits)
MSB and LSB are values from the table below depending on the timebase selected by the TB[1:0] bits
in the MCCSR register
TB1 Bit
TB0 Bit
Selected MCCSR
Timebase
MSB
LSB
(MCCSR Reg.) (MCCSR Reg.)
0
0
1
1
0
1
0
1
2ms
4ms
4
8
59
53
35
54
10ms
25ms
20
49
To calculate the minimum Watchdog Timeout (t ):
min
MSB
4
IF
THEN
ELSE
-------------
CNT <
t
= tmin0 + 16384 × CNT × t
min
osc2
4CNT
----------------
4CNT
----------------
⎛
⎞
⎠
t
= t
+ 16384 × CNT –
+ (192 + LSB) × 64 ×
× t
osc2
min
min0
⎝
MSB
MSB
To calculate the maximum Watchdog Timeout (t
):
max
MSB
4
IF
-------------
THEN
ELSE
CNT ≤
t
= tmax0 + 16384 × CNT × t
osc2
max
4CNT
----------------
4CNT
----------------
⎛
⎞
t
= t
+ 16384 × CNT –
+ (192 + LSB) × 64 ×
× t
osc2
max
max0
⎝
⎠
MSB
MSB
Note: In the above formulae, division results must be rounded down to the next integer value.
Example:
With 2ms timeout selected in MCCSR register
Min. Watchdog
Timeout (ms)
Max. Watchdog
Timeout (ms)
Value of T[5:0] Bits in
WDGCR Register (Hex.)
t
t
min
max
00
3F
1.496
128
2.048
128.552
55/215
ST72F521, ST72521B
WATCHDOG TIMER (Cont’d)
10.1.5 Low Power Modes
Mode Description
SLOW No effect on Watchdog.
WAIT No effect on Watchdog.
OIE bit in
MCCSR
register
WDGHALT bit
in Option
Byte
No Watchdog reset is generated. The MCU enters Halt mode. The Watch-
dog counter is decremented once and then stops counting and is no longer
able to generate a watchdog reset until the MCU receives an external inter-
rupt or a reset.
0
0
If an external interrupt is received, the Watchdog restarts counting after 256
or 4096 CPU clocks. If a reset is generated, the Watchdog is disabled (reset
state) unless Hardware Watchdog is selected by option byte. For applica-
tion recommendations see Section 10.1.7 below.
HALT
0
1
1
x
A reset is generated.
No reset is generated. The MCU enters Active Halt mode. The Watchdog
counter is not decremented. It stop counting. When the MCU receives an
oscillator interrupt or external interrupt, the Watchdog restarts counting im-
mediately. When the MCU receives a reset the Watchdog restarts counting
after 256 or 4096 CPU clocks.
10.1.6 Hardware Watchdog Option
10.1.9 Register Description
If Hardware Watchdog is selected by option byte,
the watchdog is always active and the WDGA bit in
the WDGCR is not used. Refer to the Option Byte
description.
CONTROL REGISTER (WDGCR)
Read/Write
Reset Value: 0111 1111 (7Fh)
10.1.7 Using Halt Mode with the WDG
(WDGHALT option)
7
0
WDGA T6
T5
T4
T3
T2
T1
T0
The following recommendation applies if Halt
mode is used when the watchdog is enabled.
– Before executing the HALT instruction, refresh
the WDG counter, to avoid an unexpected WDG
reset immediately after waking up the microcon-
troller.
Bit 7 = WDGA Activation bit.
This bit is set by software and only cleared by
hardware after a reset. When WDGA = 1, the
watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled
10.1.8 Interrupts
None.
Note: This bit is not used if the hardware watch-
dog option is enabled by option byte.
Bit 6:0 = T[6:0] 7-bit counter (MSB to LSB).
These bits contain the value of the watchdog
counter. It is decremented every 16384 f
cy-
OSC2
cles (approx.). A reset is produced when it rolls
over from 40h to 3Fh (T6 becomes cleared).
56/215
ST72F521, ST72521B
Table 13. Watchdog Timer Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
WDGCR
Reset Value
WDGA
0
T6
1
T5
1
T4
1
T3
1
T2
1
T1
1
T0
1
002Ah
57/215
ST72F521, ST72521B
10.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK AND BEEPER (MCC/RTC)
The Main Clock Controller consists of three differ-
ent functions:
external devices. It is controlled by the MCO bit in
the MCCSR register.
CAUTION: When selected, the clock out pin sus-
pends the clock during ACTIVE-HALT mode.
■
a programmable CPU clock prescaler
■
a clock-out signal to supply external devices
10.2.3
Real Time Clock Timer (RTC)
■
a real time clock timer with interrupt capability
The counter of the real time clock timer allows an
interrupt to be generated based on an accurate
real time clock. Four different time bases depend-
Each function can be used independently and si-
multaneously.
10.2.1
Programmable CPU Clock Prescaler
ing directly on f
are available. The whole
OSC2
functionality is controlled by four bits of the MCC-
SR register: TB[1:0], OIE and OIF.
The programmable CPU clock prescaler supplies
the clock for the ST7 CPU and its internal periph-
erals. It manages SLOW power saving mode (See
Section 8.2 SLOW MODE for more details).
When the RTC interrupt is enabled (OIE bit set),
the ST7 enters ACTIVE-HALT mode when the
HALT instruction is executed. See Section 8.4 AC-
TIVE-HALT AND HALT MODES for more details.
The prescaler selects the f
main clock frequen-
CPU
cy and is controlled by three bits in the MCCSR
register: CP[1:0] and SMS.
10.2.4
Beeper
10.2.2
Clock-out Capability
The clock-out capability is an alternate function of
an I/O port pin that outputs a f clock to drive
The beep function is controlled by the MCCBCR
register. It can output three selectable frequencies
on the BEEP pin (I/O port alternate function).
CPU
Figure 35.
Main Clock Controller (MCC/RTC) Block Diagram
BC1 BC0
MCCBCR
BEEP
MCO
BEEP SIGNAL
SELECTION
12-BIT MCC RTC
COUNTER
TO
DIV 64
WATCHDOG
TIMER
MCO CP1 CP0 SMS TB1 TB0 OIE OIF
MCCSR
MCC/RTC INTERRUPT
fCPU
fOSC2
DIV 2, 4, 8, 16
1
0
CPU CLOCK
TO CPU AND
PERIPHERALS
58/215
ST72F521, ST72521B
MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont’d)
10.2.5
Low Power Modes
Bit 6:5 = CP[1:0] CPU clock prescaler
Mode
Description
These bits select the CPU clock prescaler which is
applied in the different slow modes. Their action is
conditioned by the setting of the SMS bit. These
two bits are set and cleared by software
No effect on MCC/RTC peripheral.
MCC/RTC interrupt cause the device to exit
from WAIT mode.
WAIT
No effect on MCC/RTC counter (OIE bit is
ACTIVE- set), the registers are frozen.
f
in SLOW mode
CP1
CP0
CPU
HALT
MCC/RTC interrupt cause the device to exit
from ACTIVE-HALT mode.
f
f
f
/ 2
/ 4
0
0
1
1
0
1
0
1
OSC2
OSC2
OSC2
MCC/RTC counter and registers are frozen.
MCC/RTC operation resumes when the
MCU is woken up by an interrupt with “exit
from HALT” capability.
/ 8
HALT
f
/ 16
OSC2
10.2.6
Bit 4 = SMS Slow mode select
This bit is set and cleared by software.
0: Normal mode. f = f
Interrupts
The MCC/RTC interrupt event generates an inter-
rupt if the OIE bit of the MCCSR register is set and
the interrupt mask in the CC register is not active
(RIM instruction).
OSC2
CPU
1: Slow mode. f
is given by CP1, CP0
CPU
See Section 8.2 SLOW MODE and Section 10.2
MAIN CLOCK CONTROLLER WITH REAL TIME
CLOCK AND BEEPER (MCC/RTC) for more de-
tails.
Enable Exit
Control from
Exit
from
Halt
Event
Flag
Interrupt Event
Bit
Wait
Time base overflow
event
1)
Bit 3:2 = TB[1:0] Time base control
OIF
OIE
Yes
No
These bits select the programmable divider time
base. They are set and cleared by software.
Note:
The MCC/RTC interrupt wakes up the MCU from
ACTIVE-HALT mode, not from HALT mode.
Time Base
Counter
TB1 TB0
Prescaler
f
=4MHz
f
=8MHz
OSC2
OSC2
16000
32000
80000
200000
4ms
2ms
4ms
0
0
1
1
0
1
0
1
8ms
20ms
50ms
10.2.7
Register Description
10ms
25ms
MCC CONTROL/STATUS REGISTER (MCCSR)
Read/Write
Reset Value: 0000 0000 (00h
)
A modification of the time base is taken into ac-
count at the end of the current period (previously
set) to avoid an unwanted time shift. This allows to
use this time base as a real time clock.
7
0
MCO CP1 CP0 SMS TB1 TB0 OIE OIF
Bit 1 = OIE Oscillator interrupt enable
This bit set and cleared by software.
0: Oscillator interrupt disabled
1: Oscillator interrupt enabled
This interrupt can be used to exit from ACTIVE-
HALT mode.
Bit 7 = MCO Main clock out selection
This bit enables the MCO alternate function on the
PF0 I/O port. It is set and cleared by software.
0: MCO alternate function disabled (I/O pin free for
general-purpose I/O)
1: MCO alternate function enabled (f
port)
on I/O
CPU
When this bit is set, calling the ST7 software HALT
instruction enters the ACTIVE-HALT power saving
mode
.
Note: To reduce power consumption, the MCO
function is not active in ACTIVE-HALT mode.
59/215
ST72F521, ST72521B
MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont’d)
MCC BEEP CONTROL REGISTER (MCCBCR)
Bit 0 = OIF Oscillator interrupt flag
This bit is set by hardware and cleared by software
reading the MCCSR register. It indicates when set
that the main oscillator has reached the selected
elapsed time (TB1:0).
Read/Write
Reset Value: 0000 0000 (00h)
7
0
0: Timeout not reached
1: Timeout reached
0
0
0
0
0
0
BC1 BC0
CAUTION: The BRES and BSET instructions
must not be used on the MCCSR register to avoid
unintentionally clearing the OIF bit.
Bit 7:2 = Reserved, must be kept cleared.
Bit 1:0 = BC[1:0] Beep control
These 2 bits select the PF1 pin beep capability.
BC1
BC0
Beep mode with f
=8MHz
OSC2
0
0
1
1
0
1
0
1
Off
~2-KHz
Output
Beep signal
~50% duty cycle
~1-KHz
~500-Hz
The beep output signal is available in ACTIVE-
HALT mode but has to be disabled to reduce the
consumption.
Table 14. Main Clock Controller Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
SICSR
Reset Value
AVDS
0
AVDIE
0
AVDF
0
LVDRF
x
WDGRF
x
002Bh
002Ch
002Dh
0
0
0
MCCSR
Reset Value
MCO
0
CP1
0
CP0
0
SMS
0
TB1
0
TB0
0
OIE
0
OIF
0
MCCBCR
Reset Value
BC1
0
BC0
0
0
0
0
0
0
0
60/215
ST72F521, ST72521B
10.3 PWM AUTO-RELOAD TIMER (ART)
10.3.1 Introduction
The Pulse Width Modulated Auto-Reload Timer
on-chip peripheral consists of an 8-bit auto reload
counter with compare/capture capabilities and of a
7-bit prescaler clock source.
– Up to two input capture functions
– External event detector
– Up to two external interrupt sources
The three first modes can be used together with a
single counter frequency.
These resources allow five possible operating
modes:
The timer can be used to wake up the MCU from
WAIT and HALT modes.
– Generation of up to 4 independent PWM signals
– Output compare and Time base interrupt
Figure 36. PWM Auto-Reload Timer Block Diagram
OCRx
DCRx
OEx
OPx
PWMCR
REGISTER
REGISTER
LOAD
PORT
ALTERNATE
FUNCTION
POLARITY
CONTROL
PWMx
COMPARE
8-BIT COUNTER
(CAR REGISTER)
ARR
REGISTER
LOAD
INPUT CAPTURE
CONTROL
ICRx
LOAD
ARTICx
REGISTER
ICSx
ICIEx
ICFx
ICCSR
ICx INTERRUPT
f
EXT
ARTCLK
f
COUNTER
f
CPU
MUX
f
INPUT
PROGRAMMABLE
PRESCALER
ARTCSR
EXCL CC2
CC1
CC0
TCE FCRL OIE
OVF
OVF INTERRUPT
61/215
ST72F521, ST72521B
PWM AUTO-RELOAD TIMER (Cont’d)
10.3.2 Functional Description
Counter
Counter and Prescaler Initialization
The free running 8-bit counter is fed by the output
of the prescaler, and is incremented on every ris-
ing edge of the clock signal.
After RESET, the counter and the prescaler are
cleared and f
= f
.
INPUT
CPU
The counter can be initialized by:
It is possible to read or write the contents of the
counter on the fly by reading or writing the Counter
Access register (ARTCAR).
– Writing to the ARTARR register and then setting
the FCRL (Force Counter Re-Load) and the TCE
(Timer Counter Enable) bits in the ARTCSR reg-
ister.
When a counter overflow occurs, the counter is
automatically reloaded with the contents of the
ARTARR register (the prescaler is not affected).
– Writing to the ARTCAR counter access register,
In both cases the 7-bit prescaler is also cleared,
whereupon counting will start from a known value.
Counter clock and prescaler
The counter clock frequency is given by:
Direct access to the prescaler is not possible.
CC[2:0]
f
= f
/ 2
COUNTER
INPUT
Output compare control
The timer counter’s input clock (f
) feeds the
INPUT
The timer compare function is based on four differ-
ent comparisons with the counter (one for each
PWMx output). Each comparison is made be-
tween the counter value and an output compare
register (OCRx) value. This OCRx register can not
be accessed directly, it is loaded from the duty cy-
cle register (PWMDCRx) at each overflow of the
counter.
7-bit programmable prescaler, which selects one
of the 8 available taps of the prescaler, as defined
by CC[2:0] bits in the Control/Status Register
(ARTCSR). Thus the division factor of the prescal-
n
er can be set to 2 (where n = 0, 1,..7).
This f
frequency source is selected through
INPUT
the EXCL bit of the ARTCSR register and can be
either the f or an external input frequency f
.
EXT
CPU
This double buffering method avoids glitch gener-
ation when changing the duty cycle on the fly.
The clock input to the counter is enabled by the
TCE (Timer Counter Enable) bit in the ARTCSR
register. When TCE is reset, the counter is
stopped and the prescaler and counter contents
are frozen. When TCE is set, the counter runs at
the rate of the selected clock source.
Figure 37. Output compare control
f
COUNTER
ARTARR=FDh
FFh
COUNTER
OCRx
FDh
FEh
FDh
FEh
FFh
FDh
FEh
FFh
FEh
FDh
PWMDCRx
FEh
FDh
PWMx
62/215
ST72F521, ST72521B
PWM AUTO-RELOAD TIMER (Cont’d)
Independent PWM signal generation
When the counter reaches the value contained in
one of the output compare register (OCRx) the
corresponding PWMx pin level is restored.
This mode allows up to four Pulse Width Modulat-
ed signals to be generated on the PWMx output
pins with minimum core processing overhead.
This function is stopped during HALT mode.
It should be noted that the reload values will also
affect the value and the resolution of the duty cycle
of the PWM output signal. To obtain a signal on a
PWMx pin, the contents of the OCRx register must
be greater than the contents of the ARTARR reg-
ister.
Each PWMx output signal can be selected inde-
pendently using the corresponding OEx bit in the
PWM Control register (PWMCR). When this bit is
set, the corresponding I/O pin is configured as out-
put push-pull alternate function.
The maximum available resolution for the PWMx
duty cycle is:
The PWM signals all have the same frequency
which is controlled by the counter period and the
ARTARR register value.
Resolution = 1 / (256 - ARTARR)
Note: To get the maximum resolution (1/256), the
ARTARR register must be 0. With this maximum
resolution, 0% and 100% can be obtained by
changing the polarity.
f
= f
/ (256 - ARTARR)
PWM
COUNTER
When a counter overflow occurs, the PWMx pin
level is changed depending on the corresponding
OPx (output polarity) bit in the PWMCR register.
Figure 38. PWM Auto-reload Timer Function
255
DUTY CYCLE
REGISTER
(PWMDCRx)
AUTO-RELOAD
REGISTER
(ARTARR)
000
t
WITH OEx=1
AND OPx=0
WITH OEx=1
AND OPx=1
Figure 39. PWM Signal from 0% to 100% Duty Cycle
f
COUNTER
ARTARR=FDh
FFh
COUNTER
FDh
FEh
FDh
FEh
FFh
FDh
FEh
OCRx=FCh
OCRx=FDh
OCRx=FEh
OCRx=FFh
t
63/215
ST72F521, ST72521B
PWM AUTO-RELOAD TIMER (Cont’d)
Output compare and Time base interrupt
External clock and event detector mode
Using the f external prescaler input clock, the
auto-reload timer can be used as an external clock
event detector. In this mode, the ARTARR register
On overflow, the OVF flag of the ARTCSR register
is set and an overflow interrupt request is generat-
ed if the overflow interrupt enable bit, OIE, in the
ARTCSR register, is set. The OVF flag must be re-
set by the user software. This interrupt can be
used as a time base in the application.
EXT
is used to select the n
be counted before setting the OVF flag.
number of events to
EVENT
n
= 256 - ARTARR
EVENT
Caution: The external clock function is not availa-
ble in HALT mode. If HALT mode is used in the ap-
plication, prior to executing the HALT instruction,
the counter must be disabled by clearing the TCE
bit in the ARTCSR register to avoid spurious coun-
ter increments.
Figure 40. External Event Detector Example (3 counts)
f
=f
EXT COUNTER
ARTARR=FDh
FFh
COUNTER
OVF
FDh
FEh
FDh
FEh
FFh
FDh
ARTCSR READ
ARTCSR READ
INTERRUPT
IF OIE=1
INTERRUPT
IF OIE=1
t
64/215
ST72F521, ST72521B
PWM AUTO-RELOAD TIMER (Cont’d)
Input capture function
This mode allows the measurement of external
signal pulse widths through ARTICRx registers.
External interrupt capability
This mode allows the Input capture capabilities to
be used as external interrupt sources. The inter-
rupts are generated on the edge of the ARTICx
signal.
Each input capture can generate an interrupt inde-
pendently on a selected input signal transition.
This event is flagged by a set of the corresponding
CFx bits of the Input Capture Control/Status regis-
ter (ARTICCSR).
The edge sensitivity of the external interrupts is
programmable (CSx bit of ARTICCSR register)
and they are independently enabled through CIEx
bits of the ARTICCSR register. After fetching the
interrupt vector, the CFx flags can be read to iden-
tify the interrupt source.
These input capture interrupts are enabled
through the CIEx bits of the ARTICCSR register.
The active transition (falling or rising edge) is soft-
ware programmable through the CSx bits of the
ARTICCSR register.
During HALT mode, the external interrupts can be
used to wake up the micro (if the CIEx bit is set).
The read only input capture registers (ARTICRx)
are used to latch the auto-reload counter value
when a transition is detected on the ARTICx pin
(CFx bit set in ARTICCSR register). After fetching
the interrupt vector, the CFx flags can be read to
identify the interrupt source.
Note: After a capture detection, data transfer in
the ARTICRx register is inhibited until it is read
(clearing the CFx bit).
The timer interrupt remains pending while the CFx
flag is set when the interrupt is enabled (CIEx bit
set). This means, the ARTICRx register has to be
read at each capture event to clear the CFx flag.
The timing resolution is given by auto-reload coun-
ter cycle time (1/f
).
COUNTER
Note: During HALT mode, if both input capture
and external clock are enabled, the ARTICRx reg-
ister value is not guaranteed if the input capture
pin and the external clock change simultaneously.
Figure 41. Input Capture Timing Diagram
f
COUNTER
COUNTER
01h
02h
03h
04h
05h
06h
07h
INTERRUPT
04h
ARTICx PIN
CFx FLAG
xxh
ICRx REGISTER
t
65/215
ST72F521, ST72521B
PWM AUTO-RELOAD TIMER (Cont’d)
10.3.3 Register Description
CONTROL / STATUS REGISTER (ARTCSR)
Read/Write
0: New transition not yet reached
1: Transition reached
COUNTER ACCESS REGISTER (ARTCAR)
Read/Write
Reset Value: 0000 0000 (00h)
7
0
Reset Value: 0000 0000 (00h)
EXCL CC2
CC1
CC0
TCE FCRL
OIE
OVF
7
0
Bit 7 = EXCLExternal Clock
CA7
CA6
CA5
CA4
CA3
CA2
CA1
CA0
This bit is set and cleared by software. It selects the
input clock for the 7-bit prescaler.
0: CPU clock.
Bit 7:0 = CA[7:0] Counter Access Data
1: External clock.
These bits can be set and cleared either by hard-
ware or by software. The ARTCAR register is used
to read or write the auto-reload counter “on the fly”
(while it is counting).
Bit 6:4 = CC[2:0] Counter Clock Control
These bits are set and cleared by software. They
determine the prescaler division ratio from f
.
INPUT
f
With f
INPUT
=8 MHz CC2 CC1 CC0
COUNTER
f
8 MHz
4 MHz
2 MHz
1 MHz
500 KHz
250 KHz
125 KHz
62.5 KHz
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
INPUT
AUTO-RELOAD REGISTER (ARTARR)
Read/Write
f
f
f
f
f
f
/ 2
/ 4
/ 8
/ 16
/ 32
/ 64
/ 128
INPUT
INPUT
INPUT
Reset Value: 0000 0000 (00h)
INPUT
INPUT
INPUT
7
0
f
INPUT
AR7
AR6
AR5
AR4
AR3
AR2
AR1
AR0
Bit 3 = TCE Timer Counter Enable
Bit 7:0 = AR[7:0]Counter Auto-Reload Data
This bit is set and cleared by software. It puts the
timer in the lowest power consumption mode.
0: Counter stopped (prescaler and counter frozen).
1: Counter running.
These bits are set and cleared by software. They
are used to hold the auto-reload value which is au-
tomatically loaded in the counter when an overflow
occurs. At the same time, the PWM output levels
are changed according to the corresponding OPx
bit in the PWMCR register.
Bit 2 = FCRLForce Counter Re-Load
This bit is write-only and any attempt to read it will
yieldalogicalzero.Whenset,itcausesthecontents
of ARTARR register to be loaded into the counter,
and the content of the prescaler register to be
cleared in order to initialize the timer before starting
to count.
This register has two PWM management func-
tions:
– Adjusting the PWM frequency
– Setting the PWM duty cycle resolution
Bit 1 = OIEOverflow Interrupt Enable
This bit is set and cleared by software. It allows to
enable/disable the interrupt which is generated
when the OVF bit is set.
0: Overflow Interrupt disable.
1: Overflow Interrupt enable.
PWM Frequency vs. Resolution:
f
PWM
ARTARR
value
Resolution
Min
Max
0
8-bit
~0.244-KHz 31.25-KHz
Bit 0 = OVFOverflow Flag
This bit is set by hardware and cleared by software
reading the ARTCSR register. It indicates the tran-
sition of the counter from FFh to the ARTARR val-
[ 0..127 ]
> 7-bit
> 6-bit
> 5-bit
> 4-bit
~0.244-KHz
~0.488-KHz
~0.977-KHz
~1.953-KHz
62.5-KHz
125-KHz
250-KHz
500-KHz
[ 128..191 ]
[ 192..223 ]
[ 224..239 ]
ue
.
66/215
ST72F521, ST72521B
PWM AUTO-RELOAD TIMER (Cont’d)
PWM CONTROL REGISTER (PWMCR)
Read/Write
DUTY CYCLE REGISTERS (PWMDCRx)
Read/Write
Reset Value: 0000 0000 (00h)
Reset Value: 0000 0000 (00h)
7
0
7
0
OE3
OE2
OE1
OE0
OP3
OP2
OP1
OP0
DC7
DC6
DC5
DC4
DC3
DC2
DC1
DC0
Bit 7:4 = OE[3:0] PWM Output Enable
Bit 7:0 = DC[7:0] Duty Cycle Data
These bits are set and cleared by software.
These bits are set and cleared by software. They
enable or disable the PWM output channels inde-
pendently acting on the corresponding I/O pin.
0: PWM output disabled.
A PWMDCRx register is associated with the OCRx
register of each PWM channel to determine the
second edge location of the PWM signal (the first
edge location is common to all channels and given
by the ARTARR register). These PWMDCR regis-
ters allow the duty cycle to be set independently
for each PWM channel.
1: PWM output enabled.
Bit 3:0 = OP[3:0] PWM Output Polarity
These bits are set and cleared by software. They
independently select the polarity of the four PWM
output signals.
PWMx output level
OPx
Counter <= OCRx
Counter > OCRx
1
0
0
1
0
1
Note: When an OPx bit is modified, the PWMx out-
put signal polarity is immediately reversed.
67/215
ST72F521, ST72521B
PWM AUTO-RELOAD TIMER (Cont’d)
INPUT CAPTURE
CONTROL / STATUS REGISTER (ARTICCSR)
INPUT CAPTURE REGISTERS (ARTICRx)
Read only
Read/Write
Reset Value: 0000 0000 (00h)
Reset Value: 0000 0000 (00h)
7
0
7
0
0
IC7
IC6
IC5
IC4
IC3
IC2
IC1
IC0
0
CS2
CS1
CIE2 CIE1
CF2
CF1
Bit 7:0 = IC[7:0] Input Capture Data
Bit 7:6 = Reserved, always read as 0.
These read only bits are set and cleared by hard-
ware. An ARTICRx register contains the 8-bit
auto-reload counter value transferred by the input
capture channel x event.
Bit 5:4 = CS[2:1] Capture Sensitivity
These bits are set and cleared by software. They
determine the trigger event polarity on the corre-
sponding input capture channel.
0: Falling edge triggers capture on channel x.
1: Rising edge triggers capture on channel x.
Bit 3:2 = CIE[2:1] Capture Interrupt Enable
These bits are set and cleared by software. They
enable or disable the Input capture channel inter-
rupts independently.
0: Input capture channel x interrupt disabled.
1: Input capture channel x interrupt enabled.
Bit 1:0 = CF[2:1] Capture Flag
These bits are set by hardware and cleared by
software reading the corresponding ARTICRx reg-
ister. Each CFx bit indicates that an input capture x
has occurred.
0: No input capture on channel x.
1: An input capture has occured on channel x.
68/215
ST72F521, ST72521B
PWM AUTO-RELOAD TIMER (Cont’d)
Table 15. PWM Auto-Reload Timer Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
PWMDCR3
DC7
0
DC6
0
DC5
0
DC4
0
DC3
0
DC2
0
DC1
0
DC0
0
0073h
0074h
0075h
0076h
0077h
0078h
0079h
007Ah
007Bh
007Ch
007Dh
Reset Value
PWMDCR2
DC7
0
DC6
0
DC5
0
DC4
0
DC3
0
DC2
0
DC1
0
DC0
0
Reset Value
PWMDCR1
DC7
0
DC6
0
DC5
0
DC4
0
DC3
0
DC2
0
DC1
0
DC0
0
Reset Value
PWMDCR0
DC7
0
DC6
0
DC5
0
DC4
0
DC3
0
DC2
0
DC1
0
DC0
0
Reset Value
PWMCR
OE3
0
OE2
0
OE1
0
OE0
0
OP3
0
OP2
0
OP1
0
OP0
0
Reset Value
ARTCSR
EXCL
0
CC2
0
CC1
0
CC0
0
TCE
0
FCRL
0
RIE
0
OVF
0
Reset Value
ARTCAR
CA7
0
CA6
0
CA5
0
CA4
0
CA3
0
CA2
0
CA1
0
CA0
0
Reset Value
ARTARR
AR7
0
AR6
0
AR5
0
AR4
0
AR3
0
AR2
0
AR1
0
AR0
0
Reset Value
ARTICCSR
CS2
0
CS1
0
CIE2
0
CIE1
0
CF2
0
CF1
0
0
0
Reset Value
ARTICR1
IC7
0
IC6
0
IC5
0
IC4
0
IC3
0
IC2
0
IC1
0
IC0
0
Reset Value
ARTICR2
IC7
0
IC6
0
IC5
0
IC4
0
IC3
0
IC2
0
IC1
0
IC0
0
Reset Value
69/215
ST72F521, ST72521B
10.4 16-BIT TIMER
10.4.1 Introduction
When reading an input signal on a non-bonded
pin, the value will always be ‘1’.
The timer consists of a 16-bit free-running counter
driven by a programmable prescaler.
10.4.3 Functional Description
10.4.3.1 Counter
It may be used for a variety of purposes, including
pulse length measurement of up to two input sig-
nals (input capture) or generation of up to two out-
put waveforms (output compare and PWM).
The main block of the Programmable Timer is a
16-bit free running upcounter and its associated
16-bit registers. The 16-bit registers are made up
of two 8-bit registers called high & low.
Pulse lengths and waveform periods can be mod-
ulated from a few microseconds to several milli-
seconds using the timer prescaler and the CPU
clock prescaler.
Counter Register (CR):
– Counter High Register (CHR) is the most sig-
nificant byte (MS Byte).
Some ST7 devices have two on-chip 16-bit timers.
They are completely independent, and do not
share any resources. They are synchronized after
a MCU reset as long as the timer clock frequen-
cies are not modified.
– Counter Low Register (CLR) is the least sig-
nificant byte (LS Byte).
Alternate Counter Register (ACR)
– Alternate Counter High Register (ACHR) is the
most significant byte (MS Byte).
This description covers one or two 16-bit timers. In
ST7 devices with two timers, register names are
prefixed with TA (Timer A) or TB (Timer B).
– Alternate Counter Low Register (ACLR) is the
least significant byte (LS Byte).
10.4.2 Main Features
■ Programmableprescaler:fCPU dividedby2,4or8.
■ Overflow status flag and maskable interrupt
■ External clock input (must be at least 4 times
slowerthantheCPUclockspeed)withthechoice
of active edge
■ 1 or 2 Output Compare functions each with:
– 2 dedicated 16-bit registers
These two read-only 16-bit registers contain the
same value but with the difference that reading the
ACLR register does not clear the TOF bit (Timer
overflow flag), located in the Status register, (SR),
(see note at the end of paragraph titled 16-bit read
sequence).
Writing in the CLR register or ACLR register resets
the free running counter to the FFFCh value.
Both counters have a reset value of FFFCh (this is
the only value which is reloaded in the 16-bit tim-
er). The reset value of both counters is also
FFFCh in One Pulse mode and PWM mode.
– 2 dedicated programmable signals
– 2 dedicated status flags
– 1 dedicated maskable interrupt
■ 1 or 2 Input Capture functions each with:
– 2 dedicated 16-bit registers
The timer clock depends on the clock control bits
of the CR2 register, as illustrated in Table 16 Clock
Control Bits. The value in the counter register re-
peats every 131072, 262144 or 524288 CPU clock
cycles depending on the CC[1:0] bits.
– 2 dedicated active edge selection signals
– 2 dedicated status flags
– 1 dedicated maskable interrupt
■ Pulse width modulation mode (PWM)
■ One pulse mode
The timer frequency can be f
or an external frequency.
/2, f
/4, f
/8
CPU
CPU
CPU
■ Reduced Power Mode
■ 5 alternate functions on I/O ports (ICAP1, ICAP2,
OCMP1, OCMP2, EXTCLK)*
The Block Diagram is shown in Figure 42.
*Note: Some timer pins may not be available (not
bonded) in some ST7 devices. Refer to the device
pin out description.
70/215
ST72F521, ST72521B
16-BIT TIMER (Cont’d)
Figure 42. Timer Block Diagram
ST7 INTERNAL BUS
f
CPU
MCU-PERIPHERAL INTERFACE
8 low
8-bit
8 high
8
8
8
8
8
8
8
8
buffer
EXEDG
16
INPUT
CAPTURE
REGISTER
INPUT
CAPTURE
REGISTER
OUTPUT
COMPARE
REGISTER
OUTPUT
COMPARE
REGISTER
1/2
1/4
1/8
COUNTER
REGISTER
1
1
2
2
ALTERNATE
COUNTER
REGISTER
EXTCLK
pin
16
16
16
CC[1:0]
TIMER INTERNAL BUS
16 16
OVERFLOW
DETECT
EDGE DETECT
CIRCUIT1
OUTPUT COMPARE
CIRCUIT
ICAP1
pin
CIRCUIT
6
EDGE DETECT
CIRCUIT2
ICAP2
pin
OCMP1
pin
LATCH1
LATCH2
0
ICF1 OCF1 TOF ICF2 OCF2
0
TIMD
(Control/Status Register)
OCMP2
pin
CSR
EXEDG
ICIE OCIE TOIE FOLV2 FOLV1OLVL2 IEDG1 OLVL1
OC1E
OPM PWM CC1 CC0 IEDG2
OC2E
(Control Register 1) CR1
(Control Register 2) CR2
(See note)
Note: If IC, OC and TO interrupt requests have separate vectors
then the last OR is not present (See device Interrupt Vector Table)
TIMER INTERRUPT
71/215
ST72F521, ST72521B
16-BIT TIMER (Cont’d)
16-bit read sequence: (from either the Counter
Register or the Alternate Counter Register).
Clearing the overflow interrupt request is done in
two steps:
1. Reading the SR register while the TOF bit is set.
2. An access (read or write) to the CLR register.
Beginning of the sequence
Read
LS Byte
Notes: The TOF bit is not cleared by accesses to
ACLR register. The advantage of accessing the
ACLR register rather than the CLR register is that
it allows simultaneous use of the overflow function
and reading the free running counter at random
times (for example, to measure elapsed time) with-
out the risk of clearing the TOF bit erroneously.
MS Byte
At t0
is buffered
Other
instructions
Returns the buffered
LS Byte value at t0
Read
LS Byte
At t0 +∆t
The timer is not affected by WAIT mode.
In HALT mode, the counter stops counting until the
mode is exited. Counting then resumes from the
previous count (MCU awakened by an interrupt) or
from the reset count (MCU awakened by a Reset).
Sequence completed
The user must read the MS Byte first, then the LS
Byte value is buffered automatically.
This buffered value remains unchanged until the
16-bit read sequence is completed, even if the
user reads the MS Byte several times.
10.4.3.2 External Clock
The external clock (where available) is selected if
CC0=1 and CC1=1 in the CR2 register.
After a complete reading sequence, if only the
CLR register or ACLR register are read, they re-
turn the LS Byte of the count value at the time of
the read.
The status of the EXEDG bit in the CR2 register
determines the type of level transition on the exter-
nal clock pin EXTCLK that will trigger the free run-
ning counter.
Whatever the timer mode used (input capture, out-
put compare, one pulse mode or PWM mode) an
overflow occurs when the counter rolls over from
FFFFh to 0000h then:
The counter is synchronized with the falling edge
of the internal CPU clock.
A minimum of four falling edges of the CPU clock
must occur between two consecutive active edges
of the external clock; thus the external clock fre-
quency must be less than a quarter of the CPU
clock frequency.
– The TOF bit of the SR register is set.
– A timer interrupt is generated if:
– TOIE bit of the CR1 register is set and
– I bit of the CC register is cleared.
If one of these conditions is false, the interrupt re-
mains pending to be issued as soon as they are
both true.
72/215
ST72F521, ST72521B
16-BIT TIMER (Cont’d)
Figure 43. Counter Timing Diagram, internal clock divided by 2
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
FFFD FFFE FFFF 0000 0001 0002 0003
COUNTER REGISTER
TIMER OVERFLOW FLAG (TOF)
Figure 44. Counter Timing Diagram, internal clock divided by 4
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
FFFC
FFFD
0000
0001
COUNTER REGISTER
TIMER OVERFLOW FLAG (TOF)
Figure 45. Counter Timing Diagram, internal clock divided by 8
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
0000
FFFC
FFFD
COUNTER REGISTER
TIMER OVERFLOW FLAG (TOF)
Note: The MCU is in reset state when the internal reset signal is high, when it is low the MCU is running.
73/215
ST72F521, ST72521B
16-BIT TIMER (Cont’d)
10.4.3.3 Input Capture
When an input capture occurs:
In this section, the index, i, may be 1 or 2 because
there are 2 input capture functions in the 16-bit
timer.
– ICFi bit is set.
– The ICiR register contains the value of the free
running counter on the active transition on the
ICAPi pin (see Figure 47).
The two 16-bit input capture registers (IC1R and
IC2R) are used to latch the value of the free run-
ning counter after a transition is detected on the
ICAPi pin (see figure 5).
– A timer interrupt is generated if the ICIE bit is set
and the I bit is cleared in the CC register. Other-
wise, the interrupt remains pending until both
conditions become true.
MS Byte
LS Byte
ICiR
ICiHR
ICiLR
Clearing the Input Capture interrupt request (i.e.
clearing the ICFi bit) is done in two steps:
ICiR register is a read-only register.
1. Reading the SR register while the ICFi bit is set.
2. An access (read or write) to the ICiLR register.
The active transition is software programmable
through the IEDGi bit of Control Registers (CRi).
Timing resolution is one count of the free running
Notes:
counter: (f
/CC[1:0]).
CPU
1. After reading the ICiHR register, transfer of
input capture data is inhibited and ICFi will
never be set until the ICiLR register is also
read.
Procedure:
To use the input capture function select the follow-
ing in the CR2 register:
2. The ICiR register contains the free running
counter value which corresponds to the most
recent input capture.
– Select the timer clock (CC[1:0]) (see Table 16
Clock Control Bits).
3. The 2 input capture functions can be used
together even if the timer also uses the 2 output
compare functions.
– Select the edge of the active transition on the
ICAP2 pin with the IEDG2 bit (the ICAP2 pin
must be configured as floating input or input with
pull-up without interrupt if this configuration is
available).
4. In One pulse Mode and PWM mode only Input
Capture 2 can be used.
And select the following in the CR1 register:
5. The alternate inputs (ICAP1 & ICAP2) are
always directly connected to the timer. So any
transitions on these pins activates the input
capture function.
– Set the ICIE bit to generate an interrupt after an
input capture coming from either the ICAP1 pin
or the ICAP2 pin
Moreover if one of the ICAPi pins is configured
as an input and the second one as an output,
an interrupt can be generated if the user tog-
gles the output pin and if the ICIE bit is set.
This can be avoided if the input capture func-
tion i is disabled by reading the ICiHR (see note
1).
– Select the edge of the active transition on the
ICAP1 pin with the IEDG1 bit (the ICAP1pin must
be configured as floating input or input with pull-
up without interrupt if this configuration is availa-
ble).
6. The TOF bit can be used with interrupt genera-
tion in order to measure events that go beyond
the timer range (FFFFh).
74/215
ST72F521, ST72521B
16-BIT TIMER (Cont’d)
Figure 46. Input Capture Block Diagram
ICAP1
pin
(Control Register 1) CR1
EDGE DETECT
CIRCUIT2
EDGE DETECT
CIRCUIT1
ICIE
IEDG1
ICAP2
pin
(Status Register) SR
ICF1
ICF2
0
0
0
IC2R Register
IC1R Register
(Control Register 2) CR2
16-BIT
16-BIT FREE RUNNING
COUNTER
IEDG2
CC0
CC1
Figure 47. Input Capture Timing Diagram
TIMER CLOCK
FF01
FF02
FF03
COUNTER REGISTER
ICAPi PIN
ICAPi FLAG
FF03
ICAPi REGISTER
Note: The rising edge is the active edge.
75/215
ST72F521, ST72521B
16-BIT TIMER (Cont’d)
10.4.3.4 Output Compare
– The OCMPi pin takes OLVLi bit value (OCMPi
pin latch is forced low during reset).
In this section, the index, i, may be 1 or 2 because
there are 2 output compare functions in the 16-bit
timer.
– A timer interrupt is generated if the OCIE bit is
set in the CR1 register and the I bit is cleared in
the CC register (CC).
This function can be used to control an output
waveform or indicate when a period of time has
elapsed.
The OCiR register value required for a specific tim-
ing application can be calculated using the follow-
ing formula:
When a match is found between the Output Com-
pare register and the free running counter, the out-
put compare function:
– Assigns pins with a programmable value if the
∆t f
PRESC
* CPU
∆ OCiR =
OCiE bit is set
– Sets a flag in the status register
– Generates an interrupt if enabled
Where:
∆t
= Output compare period (in seconds)
= CPU clock frequency (in hertz)
Two 16-bit registers Output Compare Register 1
(OC1R) and Output Compare Register 2 (OC2R)
contain the value to be compared to the counter
register each timer clock cycle.
f
CPU
= Timer prescaler factor (2, 4 or 8 de-
pending on CC[1:0] bits, see Table 16
Clock Control Bits)
PRESC
MS Byte
LS Byte
OCiR
OCiHR
OCiLR
If the timer clock is an external clock, the formula
is:
These registers are readable and writable and are
not affected by the timer hardware. A reset event
changes the OCiR value to 8000h.
∆ OCiR = ∆t f
* EXT
Timing resolution is one count of the free running
Where:
counter: (f
).
CC[1:0]
CPU/
∆t
= Output compare period (in seconds)
= External timer clock frequency (in hertz)
f
EXT
Procedure:
To use the output compare function, select the fol-
lowing in the CR2 register:
Clearing the output compare interrupt request (i.e.
clearing the OCFi bit) is done by:
– Set the OCiE bit if an output is needed then the
OCMPi pin is dedicated to the output compare i
signal.
1. Reading the SR register while the OCFi bit is
set.
2. An access (read or write) to the OCiLR register.
– Select the timer clock (CC[1:0]) (see Table 16
Clock Control Bits).
The following procedure is recommended to pre-
vent the OCFi bit from being set between the time
it is read and the write to the OCiR register:
And select the following in the CR1 register:
– Select the OLVLi bit to applied to the OCMPi pins
after the match occurs.
– Write to the OCiHR register (further compares
are inhibited).
– Set the OCIE bit to generate an interrupt if it is
needed.
– Read the SR register (first step of the clearance
of the OCFi bit, which may be already set).
When a match is found between OCRi register
and CR register:
– Write to the OCiLR register (enables the output
compare function and clears the OCFi bit).
– OCFi bit is set.
76/215
ST72F521, ST72521B
16-BIT TIMER (Cont’d)
Notes:
1. After a processor write cycle to the OCiHR reg-
ister, the output compare function is inhibited
until the OCiLR register is also written.
Forced Compare Output capability
When the FOLVi bit is set by software, the OLVLi
bit is copied to the OCMPi pin. The OLVi bit has to
be toggled in order to toggle the OCMPi pin when
it is enabled (OCiE bit=1). The OCFi bit is then not
set by hardware, and thus no interrupt request is
generated.
2. If the OCiE bit is not set, the OCMPi pin is a
general I/O port and the OLVLi bit will not
appear when a match is found but an interrupt
could be generated if the OCIE bit is set.
3. When the timer clock is f
/2, OCFi and
The FOLVLi bits have no effect in both one pulse
CPU
OCMPi are set while the counter value equals
the OCiR register value (see Figure 49 on page
78). This behaviour is the same in OPM or
PWM mode.
mode and PWM mode.
When the timer clock is f
/4, f
/8 or in
CPU
CPU
external clock mode, OCFi and OCMPi are set
while the counter value equals the OCiR regis-
ter value plus 1 (see Figure 50 on page 78).
4. The output compare functions can be used both
for generating external events on the OCMPi
pins even if the input capture mode is also
used.
5. The value in the 16-bit OCiR register and the
OLVi bit should be changed after each suc-
cessful comparison in order to control an output
waveform or establish a new elapsed timeout.
Figure 48. Output Compare Block Diagram
16 BIT FREE RUNNING
OC1E
CC1 CC0
OC2E
COUNTER
(Control Register 2) CR2
16-bit
(Control Register 1) CR1
OUTPUT COMPARE
CIRCUIT
Latch
1
OCIE
FOLV2 FOLV1OLVL2
OLVL1
OCMP1
Pin
16-bit
16-bit
Latch
2
OCMP2
Pin
OC1R Register
OCF1
OCF2
0
0
0
OC2R Register
(Status Register) SR
77/215
ST72F521, ST72521B
16-BIT TIMER (Cont’d)
Figure 49. Output Compare Timing Diagram, f
=f
/2
TIMER
CPU
INTERNAL CPU CLOCK
TIMER CLOCK
COUNTER REGISTER
2ECF 2ED0 2ED1 2ED2
2ED3
2ED4
2ED3
OUTPUT COMPARE REGISTER i (OCRi)
OUTPUT COMPARE FLAG i (OCFi)
OCMPi PIN (OLVLi=1)
Figure 50. Output Compare Timing Diagram, f
=f
/4
TIMER
CPU
INTERNAL CPU CLOCK
TIMER CLOCK
2ECF 2ED0 2ED1 2ED2
2ED3
2ED4
2ED3
COUNTER REGISTER
OUTPUT COMPARE REGISTER i (OCRi)
COMPARE REGISTER i LATCH
OUTPUT COMPARE FLAG i (OCFi)
OCMPi PIN (OLVLi=1)
78/215
ST72F521, ST72521B
16-BIT TIMER (Cont’d)
10.4.3.5 One Pulse Mode
Clearing the Input Capture interrupt request (i.e.
clearing the ICFi bit) is done in two steps:
One Pulse mode enables the generation of a
pulse when an external event occurs. This mode is
selected via the OPM bit in the CR2 register.
1. Reading the SR register while the ICFi bit is set.
2. An access (read or write) to the ICiLR register.
The one pulse mode uses the Input Capture1
function and the Output Compare1 function.
The OC1R register value required for a specific
timing application can be calculated using the fol-
lowing formula:
Procedure:
t * f
To use one pulse mode:
CPU
- 5
OCiR Value =
1. Load the OC1R register with the value corre-
sponding to the length of the pulse (see the for-
mula in the opposite column).
PRESC
Where:
t
= Pulse period (in seconds)
2. Select the following in the CR1 register:
f
= CPU clock frequency (in hertz)
CPU
– Using the OLVL1 bit, select the level to be ap-
plied to the OCMP1 pin after the pulse.
= Timer prescaler factor (2, 4 or 8 depend-
ing on the CC[1:0] bits, see Table 16
Clock Control Bits)
PRESC
– Using the OLVL2 bit, select the level to be ap-
plied to the OCMP1 pin during the pulse.
If the timer clock is an external clock the formula is:
– Select the edge of the active transition on the
ICAP1 pin with the IEDG1 bit (the ICAP1 pin
must be configured as floating input).
OCiR = t f
-5
* EXT
Where:
t
3. Select the following in the CR2 register:
= Pulse period (in seconds)
– Set the OC1E bit, the OCMP1 pin is then ded-
icated to the Output Compare 1 function.
f
= External timer clock frequency (in hertz)
EXT
– Set the OPM bit.
When the value of the counter is equal to the value
of the contents of the OC1R register, the OLVL1
bit is output on the OCMP1 pin, (See Figure 51).
– Select the timer clock CC[1:0] (see Table 16
Clock Control Bits).
One pulse mode cycle
Notes:
ICR1 = Counter
When
1. The OCF1 bit cannot be set by hardware in one
pulse mode but the OCF2 bit can generate an
Output Compare interrupt.
OCMP1 = OLVL2
event occurs
on ICAP1
Counter is reset
2. When the Pulse Width Modulation (PWM) and
One Pulse Mode (OPM) bits are both set, the
PWM mode is the only active one.
to FFFCh
ICF1 bit is set
3. If OLVL1=OLVL2 a continuous signal will be
seen on the OCMP1 pin.
When
Counter
OCMP1 = OLVL1
= OC1R
4. The ICAP1 pin can not be used to perform input
capture. The ICAP2 pin can be used to perform
input capture (ICF2 can be set and IC2R can be
loaded) but the user must take care that the
counter is reset each time a valid edge occurs
on the ICAP1 pin and ICF1 can also generates
interrupt if ICIE is set.
Then, on a valid event on the ICAP1 pin, the coun-
ter is initialized to FFFCh and OLVL2 bit is loaded
on the OCMP1 pin, the ICF1 bit is set and the val-
ue FFFDh is loaded in the IC1R register.
Because the ICF1 bit is set when an active edge
occurs, an interrupt can be generated if the ICIE
bit is set.
5. When one pulse mode is used OC1R is dedi-
cated to this mode. Nevertheless OC2R and
OCF2 can be used to indicate a period of time
has been elapsed but cannot generate an out-
put waveform because the level OLVL2 is dedi-
cated to the one pulse mode.
79/215
ST72F521, ST72521B
16-BIT TIMER (Cont’d)
Figure 51. One Pulse Mode Timing Example
2ED3
01F8
IC1R
FFFC FFFD FFFE
2ED0 2ED1 2ED2
2ED3
FFFC FFFD
01F8
COUNTER
ICAP1
OLVL2
OLVL1
OLVL2
OCMP1
compare1
Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1
Figure 52. Pulse Width Modulation Mode Timing Example with 2 Output Compare Functions
2ED0 2ED1 2ED2
34E2 FFFC
FFFC FFFD FFFE
34E2
COUNTER
OCMP1
OLVL2
OLVL1
OLVL2
compare2
compare1
compare2
Note: OC1R=2ED0h, OC2R=34E2, OLVL1=0, OLVL2= 1
Note: On timers with only 1 Output Compare register, a fixed frequency PWM signal can be generated us-
ing the output compare and the counter overflow to define the pulse length.
80/215
ST72F521, ST72521B
16-BIT TIMER (Cont’d)
10.4.3.6 Pulse Width Modulation Mode
If OLVL1=1 and OLVL2=0 the length of the posi-
tive pulse is the difference between the OC2R and
OC1R registers.
Pulse Width Modulation (PWM) mode enables the
generation of a signal with a frequency and pulse
length determined by the value of the OC1R and
OC2R registers.
If OLVL1=OLVL2 a continuous signal will be seen
on the OCMP1 pin.
Pulse Width Modulation mode uses the complete
Output Compare 1 function plus the OC2R regis-
ter, and so this functionality can not be used when
PWM mode is activated.
The OCiR register value required for a specific tim-
ing application can be calculated using the follow-
ing formula:
t * f
CPU
PRESC
- 5
OCiR Value =
In PWM mode, double buffering is implemented on
the output compare registers. Any new values writ-
ten in the OC1R and OC2R registers are taken
into account only at the end of the PWM period
(OC2) to avoid spikes on the PWM output pin
(OCMP1).
Where:
t
= Signal or pulse period (in seconds)
= CPU clock frequency (in hertz)
f
CPU
= Timer prescaler factor (2, 4 or 8 depend-
ing on CC[1:0] bits, see Table 16 Clock
Control Bits)
PRESC
Procedure
To use pulse width modulation mode:
If the timer clock is an external clock the formula is:
1. Load the OC2R register with the value corre-
sponding to the period of the signal using the
formula in the opposite column.
OCiR = t f
-5
* EXT
2. Load the OC1R register with the value corre-
sponding to the period of the pulse if (OLVL1=0
and OLVL2=1) using the formula in the oppo-
site column.
Where:
t
= Signal or pulse period (in seconds)
f
= External timer clock frequency (in hertz)
EXT
3. Select the following in the CR1 register:
The Output Compare 2 event causes the counter
to be initialized to FFFCh (See Figure 52)
– Using the OLVL1 bit, select the level to be ap-
plied to the OCMP1 pin after a successful
comparison with the OC1R register.
Notes:
– Using the OLVL2 bit, select the level to be ap-
plied to the OCMP1 pin after a successful
comparison with the OC2R register.
1. After a write instruction to the OCiHR register,
the output compare function is inhibited until the
OCiLR register is also written.
4. Select the following in the CR2 register:
2. The OCF1 and OCF2 bits cannot be set by
hardware in PWM mode therefore the Output
Compare interrupt is inhibited.
– Set OC1E bit: the OCMP1 pin is then dedicat-
ed to the output compare 1 function.
3. The ICF1 bit is set by hardware when the coun-
ter reaches the OC2R value and can produce a
timer interrupt if the ICIE bit is set and the I bit is
cleared.
– Set the PWM bit.
– Select the timer clock (CC[1:0]) (see Table 16
Clock Control Bits).
Pulse Width Modulation cycle
4. In PWM mode the ICAP1 pin can not be used
to perform input capture because it is discon-
nected to the timer. The ICAP2 pin can be used
to perform input capture (ICF2 can be set and
IC2R can be loaded) but the user must take
care that the counter is reset each period and
ICF1 can also generates interrupt if ICIE is set.
When
Counter
= OC1R
OCMP1 = OLVL1
OCMP1 = OLVL2
5. When the Pulse Width Modulation (PWM) and
One Pulse Mode (OPM) bits are both set, the
PWM mode is the only active one.
When
Counter
= OC2R
Counter is reset
to FFFCh
ICF1 bit is set
81/215
ST72F521, ST72521B
16-BIT TIMER (Cont’d)
10.4.4 Low Power Modes
Mode
Description
No effect on 16-bit Timer.
Timer interrupts cause the device to exit from WAIT mode.
WAIT
HALT
16-bit Timer registers are frozen.
In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous
count when the MCU is woken up by an interrupt with “exit from HALT mode” capability or from the counter
reset value when the MCU is woken up by a RESET.
If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is armed. Consequent-
ly, when the MCU is woken up by an interrupt with “exit from HALT mode” capability, the ICFi bit is set, and
the counter value present when exiting from HALT mode is captured into the ICiR register.
10.4.5 Interrupts
Enable
Control from
Bit
Exit
Exit
from
Halt
Event
Flag
Interrupt Event
Wait
Yes
Yes
Yes
Yes
Yes
Input Capture 1 event/Counter reset in PWM mode
Input Capture 2 event
ICF1
ICF2
No
No
No
No
No
ICIE
Output Compare 1 event (not available in PWM mode)
Output Compare 2 event (not available in PWM mode)
Timer Overflow event
OCF1
OCF2
TOF
OCIE
TOIE
Note: The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts chap-
ter). These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt
mask in the CC register is reset (RIM instruction).
10.4.6 Summary of Timer modes
TIMER RESOURCES
MODES
Input Capture 1
Input Capture 2
Yes
Output Compare 1 Output Compare 2
Input Capture (1 and/or 2)
Output Compare (1 and/or 2)
One Pulse Mode
Yes
Yes
No
Yes
Yes
No
Yes
Yes
Yes
1)
3)
2)
Not Recommended
Not Recommended
Partially
No
PWM Mode
No
No
1) See note 4 in Section 10.4.3.5 One Pulse Mode
2) See note 5 in Section 10.4.3.5 One Pulse Mode
3) See note 4 in Section 10.4.3.6 Pulse Width Modulation Mode
82/215
ST72F521, ST72521B
16-BIT TIMER (Cont’d)
10.4.7 Register Description
Bit 4 = FOLV2 Forced Output Compare 2.
This bit is set and cleared by software.
0: No effect on the OCMP2 pin.
1:Forces the OLVL2 bit to be copied to the
OCMP2 pin, if the OC2E bit is set and even if
there is no successful comparison.
Each Timer is associated with three control and
status registers, and with six pairs of data registers
(16-bit values) relating to the two input captures,
the two output compares, the counter and the al-
ternate counter.
Bit 3 = FOLV1 Forced Output Compare 1.
This bit is set and cleared by software.
0: No effect on the OCMP1 pin.
CONTROL REGISTER 1 (CR1)
Read/Write
1: Forces OLVL1 to be copied to the OCMP1 pin, if
the OC1E bit is set and even if there is no suc-
cessful comparison.
Reset Value: 0000 0000 (00h)
7
0
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
Bit 2 = OLVL2 Output Level 2.
This bit is copied to the OCMP2 pin whenever a
successful comparison occurs with the OC2R reg-
ister and OCxE is set in the CR2 register. This val-
ue is copied to the OCMP1 pin in One Pulse Mode
and Pulse Width Modulation mode.
Bit 7 = ICIE Input Capture Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the
ICF1 or ICF2 bit of the SR register is set.
Bit 6 = OCIE Output Compare Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the
OCF1 or OCF2 bit of the SR register is set.
Bit 1 = IEDG1 Input Edge 1.
This bit determines which type of level transition
on the ICAP1 pin will trigger the capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
Bit 5 = TOIE Timer Overflow Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is enabled whenever the TOF
bit of the SR register is set.
Bit 0 = OLVL1 Output Level 1.
The OLVL1 bit is copied to the OCMP1 pin when-
ever a successful comparison occurs with the
OC1R register and the OC1E bit is set in the CR2
register.
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ST72F521, ST72521B
16-BIT TIMER (Cont’d)
CONTROL REGISTER 2 (CR2)
Read/Write
Bit 4 = PWM Pulse Width Modulation.
0: PWM mode is not active.
1: PWM mode is active, the OCMP1 pin outputs a
programmable cyclic signal; the length of the
pulse depends on the value of OC1R register;
the period depends on the value of OC2R regis-
ter.
Reset Value: 0000 0000 (00h)
7
0
OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG
Bit 3, 2 = CC[1:0] Clock Control.
Bit 7 = OC1E Output Compare 1 Pin Enable.
This bit is used only to output the signal from the
timer on the OCMP1 pin (OLV1 in Output Com-
pare mode, both OLV1 and OLV2 in PWM and
one-pulse mode). Whatever the value of the OC1E
bit, the Output Compare 1 function of the timer re-
mains active.
0: OCMP1 pin alternate function disabled (I/O pin
free for general-purpose I/O).
1: OCMP1 pin alternate function enabled.
The timer clock mode depends on these bits:
Table 16. Clock Control Bits
Timer Clock
fCPU / 4
CC1
CC0
0
0
1
0
1
0
fCPU / 2
fCPU / 8
External Clock (where
available)
1
1
Bit 6 = OC2E Output Compare 2 Pin Enable.
This bit is used only to output the signal from the
timer on the OCMP2 pin (OLV2 in Output Com-
pare mode). Whatever the value of the OC2E bit,
the Output Compare 2 function of the timer re-
mains active.
0: OCMP2 pin alternate function disabled (I/O pin
free for general-purpose I/O).
1: OCMP2 pin alternate function enabled.
Note: If the external clock pin is not available, pro-
gramming the external clock configuration stops
the counter.
Bit 1 = IEDG2 Input Edge 2.
This bit determines which type of level transition
on the ICAP2 pin will trigger the capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
Bit 5 = OPM One Pulse Mode.
0: One Pulse Mode is not active.
Bit 0 = EXEDG External Clock Edge.
1: One Pulse Mode is active, the ICAP1 pin can be
used to trigger one pulse on the OCMP1 pin; the
active transition is given by the IEDG1 bit. The
length of the generated pulse depends on the
contents of the OC1R register.
This bit determines which type of level transition
on the external clock pin EXTCLK will trigger the
counter register.
0: A falling edge triggers the counter register.
1: A rising edge triggers the counter register.
84/215
ST72F521, ST72521B
16-BIT TIMER (Cont’d)
CONTROL/STATUS REGISTER (CSR)
Read/Write (bits 7:3 read only)
Reset Value: xxxx x0xx (xxh)
7
Note: Reading or writing the ACLR register does
not clear TOF.
Bit 4 = ICF2 Input Capture Flag 2.
0: No input capture (reset value).
1: An input capture has occurred on the ICAP2
pin. To clear this bit, first read the SR register,
then read or write the low byte of the IC2R
(IC2LR) register.
0
0
ICF1 OCF1 TOF ICF2 OCF2 TIMD
0
Bit 7 = ICF1 Input Capture Flag 1.
0: No input capture (reset value).
1: An input capture has occurred on the ICAP1 pin
or the counter has reached the OC2R value in
PWM mode. To clear this bit, first read the SR
register, then read or write the low byte of the
IC1R (IC1LR) register.
Bit 3 = OCF2 Output Compare Flag 2.
0: No match (reset value).
1: The content of the free running counter has
matched the content of the OC2R register. To
clear this bit, first read the SR register, then read
or write the low byte of the OC2R (OC2LR) reg-
ister.
Bit 6 = OCF1 Output Compare Flag 1.
0: No match (reset value).
1: The content of the free running counter has
matched the content of the OC1R register. To
clear this bit, first read the SR register, then read
or write the low byte of the OC1R (OC1LR) reg-
ister.
Bit 2 = TIMD Timer disable.
This bit is set and cleared by software. When set, it
freezes the timer prescaler and counter and disa-
bled the output functions (OCMP1 and OCMP2
pins) to reduce power consumption. Access to the
timer registers is still available, allowing the timer
configuration to be changed, or the counter reset,
while it is disabled.
Bit 5 = TOF Timer Overflow Flag.
0: No timer overflow (reset value).
1:The free running counter rolled over from FFFFh
to 0000h. To clear this bit, first read the SR reg-
ister, then read or write the low byte of the CR
(CLR) register.
0: Timer enabled
1: Timer prescaler, counter and outputs disabled
Bits 1:0 = Reserved, must be kept cleared.
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ST72F521, ST72521B
16-BIT TIMER (Cont’d)
INPUT CAPTURE 1 HIGH REGISTER (IC1HR)
OUTPUT COMPARE
(OC1HR)
1
HIGH REGISTER
Read Only
Reset Value: Undefined
Read/Write
Reset Value: 1000 0000 (80h)
This is an 8-bit read only register that contains the
high part of the counter value (transferred by the
input capture 1 event).
This is an 8-bit register that contains the high part
of the value to be compared to the CHR register.
7
0
7
0
MSB
LSB
MSB
LSB
INPUT CAPTURE 1 LOW REGISTER (IC1LR)
OUTPUT COMPARE
(OC1LR)
1
LOW REGISTER
Read Only
Reset Value: Undefined
Read/Write
Reset Value: 0000 0000 (00h)
This is an 8-bit read only register that contains the
low part of the counter value (transferred by the in-
put capture 1 event).
This is an 8-bit register that contains the low part of
the value to be compared to the CLR register.
7
0
7
0
MSB
LSB
MSB
LSB
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ST72F521, ST72521B
16-BIT TIMER (Cont’d)
OUTPUT COMPARE
(OC2HR)
2
HIGH REGISTER
ALTERNATE COUNTER HIGH REGISTER
(ACHR)
Read/Write
Reset Value: 1000 0000 (80h)
Read Only
Reset Value: 1111 1111 (FFh)
This is an 8-bit register that contains the high part
of the value to be compared to the CHR register.
This is an 8-bit register that contains the high part
of the counter value.
7
0
7
0
MSB
LSB
MSB
LSB
OUTPUT COMPARE
(OC2LR)
2
LOW REGISTER
ALTERNATE COUNTER LOW REGISTER
(ACLR)
Read/Write
Reset Value: 0000 0000 (00h)
Read Only
Reset Value: 1111 1100 (FCh)
This is an 8-bit register that contains the low part of
the value to be compared to the CLR register.
This is an 8-bit register that contains the low part of
the counter value. A write to this register resets the
counter. An access to this register after an access
to CSR register does not clear the TOF bit in the
CSR register.
7
0
MSB
LSB
7
0
COUNTER HIGH REGISTER (CHR)
MSB
LSB
Read Only
Reset Value: 1111 1111 (FFh)
INPUT CAPTURE 2 HIGH REGISTER (IC2HR)
This is an 8-bit register that contains the high part
of the counter value.
Read Only
Reset Value: Undefined
7
0
This is an 8-bit read only register that contains the
high part of the counter value (transferred by the
Input Capture 2 event).
MSB
LSB
7
0
MSB
LSB
COUNTER LOW REGISTER (CLR)
Read Only
Reset Value: 1111 1100 (FCh)
This is an 8-bit register that contains the low part of
the counter value. A write to this register resets the
counter. An access to this register after accessing
the CSR register clears the TOF bit.
INPUT CAPTURE 2 LOW REGISTER (IC2LR)
Read Only
Reset Value: Undefined
This is an 8-bit read only register that contains the
low part of the counter value (transferred by the In-
put Capture 2 event).
7
0
MSB
LSB
7
0
MSB
LSB
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ST72F521, ST72521B
16-BIT TIMER (Cont’d)
Table 17. 16-Bit Timer Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
Timer A: 32 CR1
Timer B: 42 Reset Value
ICIE
0
OCIE
0
TOIE
0
FOLV2
0
FOLV1
0
OLVL2
0
IEDG1
0
OLVL1
0
Timer A: 31 CR2
Timer B: 41 Reset Value
OC1E
0
OC2E
0
OPM
0
PWM
0
CC1
0
CC0
0
IEDG2
0
EXEDG
0
Timer A: 33 CSR
Timer B: 43 Reset Value
ICF1
x
OCF1
x
TOF
x
ICF2
x
OCF2
x
TIMD
0
-
x
-
x
Timer A: 34 IC1HR
Timer B: 44 Reset Value
MSB
x
LSB
x
x
x
0
0
0
0
1
1
1
1
x
x
x
x
0
0
0
0
1
1
1
1
x
x
x
x
0
0
0
0
1
1
1
1
x
x
x
x
0
0
0
0
1
1
1
1
x
x
x
x
0
0
0
0
1
1
1
1
x
x
x
x
0
0
0
0
1
0
1
0
x
x
Timer A: 35 IC1LR
Timer B: 45 Reset Value
MSB
x
LSB
x
Timer A: 36 OC1HR
Timer B: 46 Reset Value
MSB
1
LSB
0
Timer A: 37 OC1LR
Timer B: 47 Reset Value
MSB
0
LSB
0
Timer A: 3E OC2HR
Timer B: 4E Reset Value
MSB
1
LSB
0
Timer A: 3F OC2LR
Timer B: 4F Reset Value
MSB
0
LSB
0
Timer A: 38 CHR
Timer B: 48 Reset Value
MSB
1
LSB
1
Timer A: 39 CLR
Timer B: 49 Reset Value
MSB
1
LSB
0
Timer A: 3A ACHR
Timer B: 4A Reset Value
MSB
1
LSB
1
Timer A: 3B ACLR
Timer B: 4B Reset Value
MSB
1
LSB
0
Timer A: 3C IC2HR
Timer B: 4C Reset Value
MSB
x
LSB
x
Timer A: 3D IC2LR
Timer B: 4D Reset Value
MSB
x
LSB
x
Related Documentation
AN1041: Using ST7 PWM signal to generate ana-
log input (sinusoid)
AN 973: SCI software communications using 16-
bit timer
AN1046: UART emulation software
AN 974: Real Time Clock with ST7 Timer Output
Compare
AN1078: PWM duty cycle switch implementing
true 0 or 100 per cent duty cycle
AN 976: Driving a buzzer through the ST7 Timer
PWM function
AN1504: Starting a PWM signal directly at high
level using the ST7 16-Bit timer
88/215
ST72F521, ST72521B
10.5 SERIAL PERIPHERAL INTERFACE (SPI)
10.5.1 Introduction
Note: In slave mode, continuous transmission is
not possible at maximum frequency due to the
software overhead for clearing status flags and to
initiate the next transmission sequence.
The Serial Peripheral Interface (SPI) allows full-
duplex, synchronous, serial communication with
external devices. An SPI system may consist of a
master and one or more slaves however the SPI
interface can not be a master in a multi-master
system.
10.5.3 General Description
Figure 53 shows the serial peripheral interface
(SPI) block diagram. There are 3 registers:
10.5.2 Main Features
– SPI Control Register (SPICR)
– SPI Control/Status Register (SPICSR)
– SPI Data Register (SPIDR)
■ Full duplex synchronous transfers (on 3 lines)
■ Simplex synchronous transfers (on 2 lines)
■ Master or slave operation
The SPI is connected to external devices through
4 pins:
■ Six master mode frequencies (f
/4 max.)
CPU
■ f
/2 max. slave mode frequency (see note)
CPU
– MISO: Master In / Slave Out data
– MOSI: Master Out / Slave In data
■ SS Management by software or hardware
■ Programmable clock polarity and phase
■ End of transfer interrupt flag
– SCK: Serial Clock out by SPI masters and in-
put by SPI slaves
■ Write collision, Master Mode Fault and Overrun
flags
Figure 53. Serial Peripheral Interface Block Diagram
Data/Address Bus
Read
SPIDR
Interrupt
request
Read Buffer
MOSI
7
0
SPICSR
MISO
8-Bit Shift Register
SPIF WCOL OVR MODF
0
SOD SSM SSI
Write
SOD
bit
1
SS
SPI
STATE
0
SCK
CONTROL
7
0
SPICR
MSTR
SPR0
SPIE SPE SPR2
CPOL CPHA SPR1
MASTER
CONTROL
SERIAL CLOCK
GENERATOR
SS
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ST72F521, ST72521B
SERIAL PERIPHERAL INTERFACE (Cont’d)
– SS: Slave select:
The communication is always initiated by the mas-
ter. When the master device transmits data to a
slave device via MOSI pin, the slave device re-
sponds by sending data to the master device via
the MISO pin. This implies full duplex communica-
tion with both data out and data in synchronized
with the same clock signal (which is provided by
the master device via the SCK pin).
This input signal acts as a ‘chip select’ to let
the SPI master communicate with slaves indi-
vidually and to avoid contention on the data
lines. Slave SS inputs can be driven by stand-
ard I/O ports on the master MCU.
10.5.3.1 Functional Description
A basic example of interconnections between a
single master and a single slave is illustrated in
Figure 54.
To use a single data line, the MISO and MOSI pins
must be connected at each node ( in this case only
simplex communication is possible).
The MOSI pins are connected together and the
MISO pins are connected together. In this way
data is transferred serially between master and
slave (most significant bit first).
Four possible data/clock timing relationships may
be chosen (see Figure 57) but master and slave
must be programmed with the same timing mode.
Figure 54. Single Master/ Single Slave Application
SLAVE
MASTER
MSBit
LSBit
MSBit
LSBit
MISO
MOSI
MISO
MOSI
8-BIT SHIFT REGISTER
8-BIT SHIFT REGISTER
SPI
CLOCK
GENERATOR
SCK
SS
SCK
SS
+5V
Not used if SS is managed
by software
90/215
ST72F521, ST72521B
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.5.3.2 Slave Select Management
In Slave Mode:
As an alternative to using the SS pin to control the
Slave Select signal, the application can choose to
manage the Slave Select signal by software. This
is configured by the SSM bit in the SPICSR regis-
ter (see Figure 56)
There are two cases depending on the data/clock
timing relationship (see Figure 55):
If CPHA=1 (data latched on 2nd clock edge):
– SS internal must be held low during the entire
transmission. This implies that in single slave
applications the SS pin either can be tied to
In software management, the external SS pin is
free for other application uses and the internal SS
signal level is driven by writing to the SSI bit in the
SPICSR register.
V
, or made free for standard I/O by manag-
SS
ing the SS function by software (SSM= 1 and
SSI=0 in the in the SPICSR register)
If CPHA=0 (data latched on 1st clock edge):
In Master mode:
– SS internal must be held low during byte
transmission and pulled high between each
byte to allow the slave to write to the shift reg-
ister. If SS is not pulled high, a Write Collision
error will occur when the slave writes to the
shift register (see Section 10.5.5.3).
– SS internal must be held high continuously
Figure 55. Generic SS Timing Diagram
Byte 3
Byte 2
MOSI/MISO
Master SS
Byte 1
Slave SS
(if CPHA=0)
Slave SS
(if CPHA=1)
Figure 56. Hardware/Software Slave Select Management
SSM bit
SSI bit
1
0
SS internal
SS external pin
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ST72F521, ST72521B
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.5.3.3 Master Mode Operation
Note: While the SPIF bit is set, all writes to the
SPIDR register are inhibited until the SPICSR reg-
ister is read.
In master mode, the serial clock is output on the
SCK pin. The clock frequency, polarity and phase
are configured by software (refer to the description
of the SPICSR register).
10.5.3.5 Slave Mode Operation
In slave mode, the serial clock is received on the
SCK pin from the master device.
Note: The idle state of SCK must correspond to
the polarity selected in the SPICSR register (by
pulling up SCK if CPOL=1 or pulling down SCK if
CPOL=0).
To operate the SPI in slave mode:
1. Write to the SPICSR register to perform the fol-
lowing actions:
To operate the SPI in master mode, perform the
following steps in order (if the SPICSR register is
not written first, the SPICR register setting (MSTR
bit) may be not taken into account):
– Select the clock polarity and clock phase by
configuring the CPOL and CPHA bits (see
Figure 57).
Note: The slave must have the same CPOL
and CPHA settings as the master.
– Manage the SS pin as described in Section
10.5.3.2 and Figure 55. If CPHA=1 SS must
be held low continuously. If CPHA=0 SS must
be held low during byte transmission and
pulled up between each byte to let the slave
write in the shift register.
1. Write to the SPICR register:
– Select the clock frequency by configuring the
SPR[2:0] bits.
– Select the clock polarity and clock phase by
configuring the CPOL and CPHA bits. Figure
57 shows the four possible configurations.
Note: The slave must have the same CPOL
and CPHA settings as the master.
2. Write to the SPICR register to clear the MSTR
bit and set the SPE bit to enable the SPI I/O
functions.
2. Write to the SPICSR register:
– Either set the SSM bit and set the SSI bit or
clear the SSM bit and tie the SS pin high for
the complete byte transmit sequence.
10.5.3.6 Slave Mode Transmit Sequence
When software writes to the SPIDR register, the
data byte is loaded into the 8-bit shift register and
then shifted out serially to the MISO pin most sig-
nificant bit first.
3. Write to the SPICR register:
– Set the MSTR and SPE bits
Note: MSTR and SPE bits remain set only if
SS is high).
The transmit sequence begins when the slave de-
vice receives the clock signal and the most signifi-
cant bit of the data on its MOSI pin.
The transmit sequence begins when software
writes a byte in the SPIDR register.
10.5.3.4 Master Mode Transmit Sequence
When data transfer is complete:
– The SPIF bit is set by hardware
When software writes to the SPIDR register, the
data byte is loaded into the 8-bit shift register and
then shifted out serially to the MOSI pin most sig-
nificant bit first.
– An interrupt request is generated if SPIE bit is
set and interrupt mask in the CCR register is
cleared.
When data transfer is complete:
– The SPIF bit is set by hardware
Clearing the SPIF bit is performed by the following
software sequence:
– An interrupt request is generated if the SPIE
bit is set and the interrupt mask in the CCR
register is cleared.
1. An access to the SPICSR register while the
SPIF bit is set.
2. A write or a read to the SPIDR register.
Clearing the SPIF bit is performed by the following
software sequence:
Notes: While the SPIF bit is set, all writes to the
SPIDR register are inhibited until the SPICSR reg-
ister is read.
1. An access to the SPICSR register while the
SPIF bit is set
The SPIF bit can be cleared during a second
transmission; however, it must be cleared before
the second SPIF bit in order to prevent an Overrun
condition (see Section 10.5.5.2).
2. A read to the SPIDR register.
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ST72F521, ST72521B
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.5.4 Clock Phase and Clock Polarity
Figure 57, shows an SPI transfer with the four
combinations of the CPHA and CPOL bits. The di-
agram may be interpreted as a master or slave
timing diagram where the SCK pin, the MISO pin,
the MOSI pin are directly connected between the
master and the slave device.
Four possible timing relationships may be chosen
by software, using the CPOL and CPHA bits (See
Figure 57).
Note: The idle state of SCK must correspond to
the polarity selected in the SPICSR register (by
pulling up SCK if CPOL=1 or pulling down SCK if
CPOL=0).
Note: If CPOL is changed at the communication
byte boundaries, the SPI must be disabled by re-
setting the SPE bit.
The combination of the CPOL clock polarity and
CPHA (clock phase) bits selects the data capture
clock edge
Figure 57. Data Clock Timing Diagram
CPHA =1
SCK
(CPOL = 1)
SCK
(CPOL = 0)
Bit 4
Bit 4
Bit3
Bit3
Bit 2
Bit 2
Bit 1
Bit 1
LSBit
LSBit
MSBit
MSBit
Bit 6
Bit 6
Bit 5
Bit 5
MISO
(from master)
MOSI
(from slave)
SS
(to slave)
CAPTURE STROBE
CPHA =0
SCK
(CPOL = 1)
SCK
(CPOL = 0)
Bit 4
Bit 4
Bit3
Bit 2
Bit 2
Bit 1
Bit 1
LSBit
LSBit
MISO
(from master)
MSBit
Bit 6
Bit 6
Bit 5
Bit 5
Bit3
MOSI
(from slave)
MSBit
SS
(to slave)
CAPTURE STROBE
Note: This figure should not be used as a replacement for parametric information.
Refer to the Electrical Characteristics chapter.
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ST72F521, ST72521B
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.5.5 Error Flags
not cleared the SPIF bit issued from the previously
transmitted byte.
10.5.5.1 Master Mode Fault (MODF)
When an Overrun occurs:
Master mode fault occurs when the master device
has its SS pin pulled low.
– The OVR bit is set and an interrupt request is
generated if the SPIE bit is set.
When a Master mode fault occurs:
In this case, the receiver buffer contains the byte
sent after the SPIF bit was last cleared. A read to
the SPIDR register returns this byte. All other
bytes are lost.
– The MODF bit is set and an SPI interrupt re-
quest is generated if the SPIE bit is set.
– The SPE bit is reset. This blocks all output
from the device and disables the SPI periph-
eral.
The OVR bit is cleared by reading the SPICSR
register.
– The MSTR bit is reset, thus forcing the device
into slave mode.
10.5.5.3 Write Collision Error (WCOL)
A write collision occurs when the software tries to
write to the SPIDR register while a data transfer is
taking place with an external device. When this
happens, the transfer continues uninterrupted;
and the software write will be unsuccessful.
Clearing the MODF bit is done through a software
sequence:
1. A read access to the SPICSR register while the
MODF bit is set.
2. A write to the SPICR register.
Write collisions can occur both in master and slave
mode. See also Section 10.5.3.2 Slave Select
Management.
Notes: To avoid any conflicts in an application
with multiple slaves, the SS pin must be pulled
high during the MODF bit clearing sequence. The
SPE and MSTR bits may be restored to their orig-
inal state during or after this clearing sequence.
Note: a "read collision" will never occur since the
received data byte is placed in a buffer in which
access is always synchronous with the MCU oper-
ation.
Hardware does not allow the user to set the SPE
and MSTR bits while the MODF bit is set except in
the MODF bit clearing sequence.
The WCOL bit in the SPICSR register is set if a
write collision occurs.
10.5.5.2 Overrun Condition (OVR)
No SPI interrupt is generated when the WCOL bit
is set (the WCOL bit is a status flag only).
An overrun condition occurs, when the master de-
vice has sent a data byte and the slave device has
Clearing the WCOL bit is done through a software
sequence (see Figure 58).
Figure 58. Clearing the WCOL bit (Write Collision Flag) Software Sequence
Clearing sequence after SPIF = 1 (end of a data byte transfer)
Read SPICSR
1st Step
RESULT
SPIF =0
WCOL=0
2nd Step
Read SPIDR
Clearing sequence before SPIF = 1 (during a data byte transfer)
Read SPICSR
1st Step
Note: Writing to the SPIDR regis-
ter instead of reading it does not
reset the WCOL bit
RESULT
2nd Step
Read SPIDR
WCOL=0
94/215
ST72F521, ST72521B
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.5.5.4 Single Master Systems
Note: To prevent a bus conflict on the MISO line
the master allows only one active slave device
during a transmission.
A typical single master system may be configured,
using an MCU as the master and four MCUs as
slaves (see Figure 59).
For more security, the slave device may respond
to the master with the received data byte. Then the
master will receive the previous byte back from the
slave device if all MISO and MOSI pins are con-
nected and the slave has not written to its SPIDR
register.
The master device selects the individual slave de-
vices by using four pins of a parallel port to control
the four SS pins of the slave devices.
The SS pins are pulled high during reset since the
master device ports will be forced to be inputs at
that time, thus disabling the slave devices.
Other transmission security methods can use
ports for handshake lines or data bytes with com-
mand fields.
Figure 59. Single Master / Multiple Slave Configuration
SS
SS
SS
SS
SCK
SCK
Slave
SCK
Slave
MCU
SCK
Slave
MCU
Slave
MCU
MCU
MOSI MISO
MOSI MISO
MOSI MISO
MOSI MISO
MOSI MISO
SCK
Master
MCU
5V
SS
95/215
ST72F521, ST72521B
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.5.6 Low Power Modes
Note: When waking up from Halt mode, if the SPI
remains in Slave mode, it is recommended to per-
form an extra communications cycle to bring the
SPI from Halt mode state to normal state. If the
SPI exits from Slave mode, it returns to normal
state immediately.
Mode
Description
No effect on SPI.
WAIT
SPI interrupt events cause the device to exit
from WAIT mode.
SPI registers are frozen.
Caution: The SPI can wake up the ST7 from Halt
mode only if the Slave Select signal (external SS
pin or the SSI bit in the SPICSR register) is low
when the ST7 enters Halt mode. So if Slave selec-
tion is configured as external (see Section
10.5.3.2), make sure the master drives a low level
on the SS pin when the slave enters Halt mode.
In HALT mode, the SPI is inactive. SPI oper-
ation resumes when the MCU is woken up by
an interrupt with “exit from HALT mode” ca-
pability. The data received is subsequently
read from the SPIDR register when the soft-
ware is running (interrupt vector fetching). If
several data are received before the wake-
up event, then an overrun error is generated.
This error can be detected after the fetch of
the interrupt routine that woke up the device.
HALT
10.5.7 Interrupts
Enable
Control from
Bit
Exit
Exit
from
Halt
Event
Flag
Interrupt Event
Wait
10.5.6.1 Using the SPI to wakeup the MCU from
Halt mode
SPI End of Transfer
Event
SPIF
Yes
Yes
In slave configuration, the SPI is able to wakeup
the ST7 device from HALT mode through a SPIF
interrupt. The data received is subsequently read
from the SPIDR register when the software is run-
ning (interrupt vector fetch). If multiple data trans-
fers have been performed before software clears
the SPIF bit, then the OVR bit is set by hardware.
Master Mode Fault
Event
SPIE
MODF
OVR
Yes
Yes
No
No
Overrun Error
Note: The SPI interrupt events are connected to
the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding
Enable Control Bit is set and the interrupt mask in
96/215
ST72F521, ST72521B
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.5.8 Register Description
CONTROL REGISTER (SPICR)
Read/Write
Bit 3 = CPOL Clock Polarity.
This bit is set and cleared by software. This bit de-
termines the idle state of the serial Clock. The
CPOL bit affects both the master and slave
modes.
0: SCK pin has a low level idle state
1: SCK pin has a high level idle state
Reset Value: 0000 xxxx (0xh)
7
0
SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0
Note: If CPOL is changed at the communication
byte boundaries, the SPI must be disabled by re-
setting the SPE bit.
Bit 7 = SPIE Serial Peripheral Interrupt Enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SPI interrupt is generated whenever
SPIF=1, MODF=1 or OVR=1 in the SPICSR
register
Bit 2 = CPHA Clock Phase.
This bit is set and cleared by software.
0: The first clock transition is the first data capture
edge.
1: The second clock transition is the first capture
edge.
Bit 6 = SPE Serial Peripheral Output Enable.
This bit is set and cleared by software. It is also
cleared by hardware when, in master mode, SS=0
(see Section 10.5.5.1 Master Mode Fault
(MODF)). The SPE bit is cleared by reset, so the
SPI peripheral is not initially connected to the ex-
ternal pins.
Note: The slave must have the same CPOL and
CPHA settings as the master.
Bits 1:0 = SPR[1:0] Serial Clock Frequency.
These bits are set and cleared by software. Used
with the SPR2 bit, they select the baud rate of the
SPI serial clock SCK output by the SPI in master
mode.
0: I/O pins free for general purpose I/O
1: SPI I/O pin alternate functions enabled
Bit 5 = SPR2 Divider Enable.
Note: These 2 bits have no effect in slave mode.
This bit is set and cleared by software and is
cleared by reset. It is used with the SPR[1:0] bits to
set the baud rate. Refer to Table 18 SPI Master
mode SCK Frequency.
Table 18. SPI Master mode SCK Frequency
Serial Clock
SPR2 SPR1 SPR0
0: Divider by 2 enabled
1: Divider by 2 disabled
f
f
/4
/8
1
0
0
1
0
0
0
0
0
1
1
1
0
0
1
0
0
1
CPU
CPU
Note: This bit has no effect in slave mode.
f
f
f
/16
/32
/64
CPU
CPU
CPU
Bit 4 = MSTR Master Mode.
This bit is set and cleared by software. It is also
cleared by hardware when, in master mode, SS=0
(see Section 10.5.5.1 Master Mode Fault
(MODF)).
f
/128
CPU
0: Slave mode
1: Master mode. The function of the SCK pin
changes from an input to an output and the func-
tions of the MISO and MOSI pins are reversed.
97/215
ST72F521, ST72521B
SERIAL PERIPHERAL INTERFACE (Cont’d)
CONTROL/STATUS REGISTER (SPICSR)
Read/Write (some bits Read Only)
Reset Value: 0000 0000 (00h)
Bit 3 = Reserved, must be kept cleared.
Bit 2 = SOD SPI Output Disable.
7
0
This bit is set and cleared by software. When set, it
disables the alternate function of the SPI output
(MOSI in master mode / MISO in slave mode)
0: SPI output enabled (if SPE=1)
SPIF
WCOL OVR MODF
-
SOD SSM SSI
1: SPI output disabled
Bit 7 = SPIF Serial Peripheral Data Transfer Flag
(Read only).
Bit 1 = SSM SS Management.
This bit is set by hardware when a transfer has
been completed. An interrupt is generated if
SPIE=1 in the SPICR register. It is cleared by a
software sequence (an access to the SPICSR
register followed by a write or a read to the
SPIDR register).
This bit is set and cleared by software. When set, it
disables the alternate function of the SPI SS pin
and uses the SSI bit value instead. See Section
10.5.3.2 Slave Select Management.
0: Hardware management (SS managed by exter-
nal pin)
1: Software management (internal SS signal con-
trolled by SSI bit. External SS pin free for gener-
al-purpose I/O)
0: Data transfer is in progress or the flag has been
cleared.
1: Data transfer between the device and an exter-
nal device has been completed.
Note: While the SPIF bit is set, all writes to the
SPIDR register are inhibited until the SPICSR reg-
ister is read.
Bit 0 = SSI SS Internal Mode.
This bit is set and cleared by software. It acts as a
‘chip select’ by controlling the level of the SS slave
select signal when the SSM bit is set.
0 : Slave selected
Bit 6 = WCOL Write Collision status (Read only).
This bit is set by hardware when a write to the
SPIDR register is done during a transmit se-
quence. It is cleared by a software sequence (see
Figure 58).
0: No write collision occurred
1: A write collision has been detected
1 : Slave deselected
DATA I/O REGISTER (SPIDR)
Read/Write
Reset Value: Undefined
7
0
Bit 5 = OVR SPI Overrun error (Read only).
This bit is set by hardware when the byte currently
being received in the shift register is ready to be
transferred into the SPIDR register while SPIF = 1
(See Section 10.5.5.2). An interrupt is generated if
SPIE = 1 in SPICR register. The OVR bit is cleared
by software reading the SPICSR register.
0: No overrun error
D7
D6
D5
D4
D3
D2
D1
D0
The SPIDR register is used to transmit and receive
data on the serial bus. In a master device, a write
to this register will initiate transmission/reception
of another byte.
1: Overrun error detected
Notes: During the last clock cycle the SPIF bit is
set, a copy of the received data byte in the shift
register is moved to a buffer. When the user reads
the serial peripheral data I/O register, the buffer is
actually being read.
Bit 4 = MODF Mode Fault flag (Read only).
This bit is set by hardware when the SS pin is
pulled low in master mode (see Section 10.5.5.1
Master Mode Fault (MODF)). An SPI interrupt can
be generated if SPIE=1 in the SPICSR register.
This bit is cleared by a software sequence (An ac-
cess to the SPICR register while MODF=1 fol-
lowed by a write to the SPICR register).
While the SPIF bit is set, all writes to the SPIDR
register are inhibited until the SPICSR register is
read.
Warning: A write to the SPIDR register places
data directly into the shift register for transmission.
0: No master mode fault detected
1: A fault in master mode has been detected
A read to the SPIDR register returns the value lo-
cated in the buffer and not the content of the shift
register (see Figure 53).
98/215
ST72F521, ST72521B
SERIAL PERIPHERAL INTERFACE (Cont’d)
Table 19. SPI Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
SPIDR
Reset Value
MSB
x
LSB
x
0021h
0022h
0023h
x
x
x
x
x
x
SPICR
Reset Value
SPIE
0
SPE
0
SPR2
0
MSTR
0
CPOL
x
CPHA
x
SPR1
x
SPR0
x
SPICSR
Reset Value
SPIF
0
WCOL
0
OR
0
MODF
0
SOD
0
SSM
0
SSI
0
0
99/215
ST72F521, ST72521B
10.6 SERIAL COMMUNICATIONS INTERFACE (SCI)
10.6.1 Introduction
10.6.3 General Description
The Serial Communications Interface (SCI) offers
a flexible means of full-duplex data exchange with
external equipment requiring an industry standard
NRZ asynchronous serial data format. The SCI of-
fers a very wide range of baud rates using two
baud rate generator systems.
The interface is externally connected to another
device by two pins (see Figure 61):
– TDO: Transmit Data Output. When the transmit-
ter and the receiver are disabled, the output pin
returns to its I/O port configuration. When the
transmitter and/or the receiver are enabled and
nothing is to be transmitted, the TDO pin is at
high level.
10.6.2 Main Features
■ Full duplex, asynchronous communications
■ NRZ standard format (Mark/Space)
■ Dual baud rate generator systems
■ Independently programmable transmit and
receive baud rates up to 500K baud.
■ Programmable data word length (8 or 9 bits)
– RDI: Receive Data Input is the serial data input.
Oversampling techniques are used for data re-
covery by discriminating between valid incoming
data and noise.
Through these pins, serial data is transmitted and
received as frames comprising:
■ Receive buffer full, Transmit buffer empty and
– An Idle Line prior to transmission or reception
– A start bit
End of Transmission flags
■ Two receiver wake-up modes:
– Address bit (MSB)
– A data word (8 or 9 bits) least significant bit first
– A Stop bit indicating that the frame is complete.
Thisinterfaceusestwotypesofbaudrategenerator:
– Idle line
■ Mutingfunctionformultiprocessorconfigurations
– A conventional type for commonly-used baud
rates,
■ Separate enable bits for Transmitter and
Receiver
– An extended type with a prescaler offering a very
wide range of baud rates even with non-standard
oscillator frequencies.
■ Four error detection flags:
– Overrun error
– Noise error
– Frame error
– Parity error
■ Five interrupt sources with flags:
– Transmit data register empty
– Transmission complete
– Receive data register full
– Idle line received
– Overrun error detected
■ Parity control:
– Transmits parity bit
– Checks parity of received data byte
■ Reduced power consumption mode
100/215
ST72F521, ST72521B
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
Figure 60. SCI Block Diagram
Write
Read
(DATA REGISTER) DR
Received Data Register (RDR)
Received Shift Register
Transmit Data Register (TDR)
TDO
Transmit Shift Register
RDI
CR1
R8 T8 SCID
M WAKE PCE PS PIE
WAKE
UP
TRANSMIT
CONTROL
RECEIVER
CLOCK
RECEIVER
CONTROL
UNIT
CR2
SR
TIE TCIE RIE ILIE TE RE RWU SBK
TDRE TC RDRF IDLE OR NF FE
PE
SCI
INTERRUPT
CONTROL
TRANSMITTER
CLOCK
TRANSMITTER RATE
CONTROL
f
CPU
/PR
/16
BRR
SCP1
SCT2
SCT1SCT0SCR2 SCR1SCR0
SCP0
RECEIVER RATE
CONTROL
CONVENTIONAL BAUD RATE GENERATOR
101/215
ST72F521, ST72521B
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.6.4 Functional Description
10.6.4.1 Serial Data Format
The block diagram of the Serial Control Interface,
is shown in Figure 60. It contains 6 dedicated reg-
isters:
Word length may be selected as being either 8 or 9
bits by programming the M bit in the SCICR1 reg-
ister (see Figure 60).
– Two control registers (SCICR1 & SCICR2)
– A status register (SCISR)
The TDO pin is in low state during the start bit.
The TDO pin is in high state during the stop bit.
– A baud rate register (SCIBRR)
An Idle character is interpreted as an entire frame
of “1”s followed by the start bit of the next frame
which contains data.
– An extended prescaler receiver register (SCIER-
PR)
A Break character is interpreted on receiving “0”s
for some multiple of the frame period. At the end of
the last break frame the transmitter inserts an ex-
tra “1” bit to acknowledge the start bit.
– An extended prescaler transmitter register (SCI-
ETPR)
Refer to the register descriptions in Section
10.6.7for the definitions of each bit.
Transmission and reception are driven by their
own baud rate generator.
Figure 61. Word Length Programming
9-bit Word length (M bit is set)
Possible
Next Data Frame
Parity
Data Frame
Start
Bit
Next
Start
Bit
Stop
Bit
Bit2
Bit6
Bit3
Bit4
Bit5
Bit7
Bit8
Bit0 Bit1
Bit
Start
Bit
Idle Frame
Start
Bit
Extra
’1’
Break Frame
8-bit Word length (M bit is reset)
Possible
Parity
Next Data Frame
Data Frame
Bit
Next
Start
Bit
Start
Bit
Stop
Bit
Bit2
Bit1
Bit3
Bit4
Bit5
Bit6
Bit0
Bit7
Start
Bit
Idle Frame
Start
Bit
Extra
’1’
Break Frame
102/215
ST72F521, ST72521B
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.6.4.2 Transmitter
When a frame transmission is complete (after the
stop bit or after the break frame) the TC bit is set
and an interrupt is generated if the TCIE is set and
the I bit is cleared in the CCR register.
The transmitter can send data words of either 8 or
9 bits depending on the M bit status. When the M
bit is set, word length is 9 bits and the 9th bit (the
MSB) has to be stored in the T8 bit in the SCICR1
register.
Clearing the TC bit is performed by the following
software sequence:
1. An access to the SCISR register
2. A write to the SCIDR register
Character Transmission
During an SCI transmission, data shifts out least
significant bit first on the TDO pin. In this mode,
the SCIDR register consists of a buffer (TDR) be-
tween the internal bus and the transmit shift regis-
ter (see Figure 60).
Note: The TDRE and TC bits are cleared by the
same software sequence.
Break Characters
Setting the SBK bit loads the shift register with a
break character. The break frame length depends
on the M bit (see Figure 61).
Procedure
– Select the M bit to define the word length.
As long as the SBK bit is set, the SCI send break
frames to the TDO pin. After clearing this bit by
software the SCI insert a logic 1 bit at the end of
the last break frame to guarantee the recognition
of the start bit of the next frame.
– Select the desired baud rate using the SCIBRR
and the SCIETPR registers.
– Set the TE bit to assign the TDO pin to the alter-
nate function and to send a idle frame as first
transmission.
Idle Characters
– Access the SCISR register and write the data to
send in the SCIDR register (this sequence clears
the TDRE bit). Repeat this sequence for each
data to be transmitted.
Setting the TE bit drives the SCI to send an idle
frame before the first data frame.
Clearing and then setting the TE bit during a trans-
mission sends an idle frame after the current word.
Clearing the TDRE bit is always performed by the
following software sequence:
1. An access to the SCISR register
2. A write to the SCIDR register
Note: Resetting and setting the TE bit causes the
data in the TDR register to be lost. Therefore the
best time to toggle the TE bit is when the TDRE bit
is set i.e. before writing the next byte in the SCIDR.
The TDRE bit is set by hardware and it indicates:
– The TDR register is empty.
– The data transfer is beginning.
– The next data can be written in the SCIDR regis-
ter without overwriting the previous data.
This flag generates an interrupt if the TIE bit is set
and the I bit is cleared in the CCR register.
When a transmission is taking place, a write in-
struction to the SCIDR register stores the data in
the TDR register and which is copied in the shift
register at the end of the current transmission.
When no transmission is taking place, a write in-
struction to the SCIDR register places the data di-
rectly in the shift register, the data transmission
starts, and the TDRE bit is immediately set.
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ST72F521, ST72521B
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.6.4.3 Receiver
RDR register as long as the RDRF bit is not
cleared.
The SCI can receive data words of either 8 or 9
bits. When the M bit is set, word length is 9 bits
and the MSB is stored in the R8 bit in the SCICR1
register.
When a overrun error occurs:
– The OR bit is set.
– The RDR content will not be lost.
– The shift register will be overwritten.
Character reception
During a SCI reception, data shifts in least signifi-
cant bit first through the RDI pin. In this mode, the
SCIDR register consists or a buffer (RDR) be-
tween the internal bus and the received shift regis-
ter (see Figure 60).
– An interrupt is generated if the RIE bit is set and
the I bit is cleared in the CCR register.
The OR bit is reset by an access to the SCISR reg-
ister followed by a SCIDR register read operation.
Procedure
Noise Error
– Select the M bit to define the word length.
Oversampling techniques are used for data recov-
ery by discriminating between valid incoming data
and noise. Normal data bits are considered valid if
three consecutive samples (8th, 9th, 10th) have
the same bit value, otherwise the NF flag is set. In
the case of start bit detection, the NF flag is set on
the basis of an algorithm combining both valid
edge detection and three samples (8th, 9th, 10th).
Therefore, to prevent the NF flag getting set during
start bit reception, there should be a valid edge de-
tection as well as three valid samples.
– Select the desired baud rate using the SCIBRR
and the SCIERPR registers.
– Set the RE bit, this enables the receiver which
begins searching for a start bit.
When a character is received:
– The RDRF bit is set. It indicates that the content
of the shift register is transferred to the RDR.
– An interrupt is generated if the RIE bit is set and
the I bit is cleared in the CCR register.
When noise is detected in a frame:
– The error flags can be set if a frame error, noise
or an overrun error has been detected during re-
ception.
– The NF flag is set at the rising edge of the RDRF
bit.
– Data is transferred from the Shift register to the
SCIDR register.
Clearing the RDRF bit is performed by the following
software sequence done by:
– No interrupt is generated. However this bit rises
at the same time as the RDRF bit which itself
generates an interrupt.
1. An access to the SCISR register
2. A read to the SCIDR register.
The RDRF bit must be cleared before the end of the
reception of the next character to avoid an overrun
error.
The NF flag is reset by a SCISR register read op-
eration followed by a SCIDR register read opera-
tion.
Break Character
During reception, if a false start bit is detected (e.g.
8th, 9th, 10th samples are 011,101,110), the
frame is discarded and the receiving sequence is
not started for this frame. There is no RDRF bit set
for this frame and the NF flag is set internally (not
accessible to the user). This NF flag is accessible
along with the RDRF bit when a next valid frame is
received.
When a break character is received, the SPI han-
dles it as a framing error.
Idle Character
When a idle frame is detected, there is the same
procedure as a data received character plus an in-
terrupt if the ILIE bit is set and the I bit is cleared in
the CCR register.
Note: If the application Start Bit is not long enough
to match the above requirements, then the NF
Flag may get set due to the short Start Bit. In this
case, the NF flag may be ignored by the applica-
tion software when the first valid byte is received.
Overrun Error
An overrun error occurs when a character is re-
ceived when RDRF has not been reset. Data can
not be transferred from the shift register to the
See also Section 10.6.4.10.
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ST72F521, ST72521B
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
Figure 62. SCI Baud Rate and Extended Prescaler Block Diagram
TRANSMITTER
CLOCK
EXTENDED PRESCALER TRANSMITTER RATE CONTROL
SCIETPR
EXTENDED TRANSMITTER PRESCALER REGISTER
SCIERPR
EXTENDED RECEIVER PRESCALER REGISTER
RECEIVER
CLOCK
EXTENDED PRESCALER RECEIVER RATE CONTROL
EXTENDED PRESCALER
f
CPU
TRANSMITTER RATE
CONTROL
/PR
/16
SCIBRR
SCP1
SCT2
SCT1SCT0SCR2 SCR1SCR0
SCP0
RECEIVER RATE
CONTROL
CONVENTIONAL BAUD RATE GENERATOR
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ST72F521, ST72521B
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
Framing Error
Note: the extended prescaler is activated by set-
ting the SCIETPR or SCIERPR register to a value
other than zero. The baud rates are calculated as
follows:
A framing error is detected when:
– The stop bit is not recognized on reception at the
expected time, following either a de-synchroni-
zation or excessive noise.
f
f
CPU
CPU
Rx =
16 ERPR*(PR*RR)
Tx =
16 ETPR*(PR*TR)
– A break is received.
*
*
When the framing error is detected:
– the FE bit is set by hardware
with:
– Data is transferred from the Shift register to the
SCIDR register.
ETPR = 1,..,255 (see SCIETPR register)
ERPR = 1,.. 255 (see SCIERPR register)
10.6.4.6 Receiver Muting and Wake-up Feature
– No interrupt is generated. However this bit rises
at the same time as the RDRF bit which itself
generates an interrupt.
In multiprocessor configurations it is often desira-
ble that only the intended message recipient
should actively receive the full message contents,
thus reducing redundant SCI service overhead for
all non addressed receivers.
The FE bit is reset by a SCISR register read oper-
ation followed by a SCIDR register read operation.
10.6.4.4 Conventional Baud Rate Generation
The baud rate for the receiver and transmitter (Rx
and Tx) are set independently and calculated as
follows:
The non addressed devices may be placed in
sleep mode by means of the muting function.
Setting the RWU bit by software puts the SCI in
sleep mode:
f
f
CPU
CPU
Rx =
Tx =
All the reception status bits can not be set.
All the receive interrupts are inhibited.
(16 PR) RR
(16 PR) TR
*
*
*
*
with:
A muted receiver may be awakened by one of the
following two ways:
PR = 1, 3, 4 or 13 (see SCP[1:0] bits)
TR = 1, 2, 4, 8, 16, 32, 64,128
(see SCT[2:0] bits)
– by Idle Line detection if the WAKE bit is reset,
– by Address Mark detection if the WAKE bit is set.
RR = 1, 2, 4, 8, 16, 32, 64,128
(see SCR[2:0] bits)
Receiver wakes-up by Idle Line detection when
the Receive line has recognised an Idle Frame.
Then the RWU bit is reset by hardware but the
IDLE bit is not set.
All these bits are in the SCIBRR register.
Example: If f is 8 MHz (normal mode) and if
CPU
Receiver wakes-up by Address Mark detection
when it received a “1” as the most significant bit of
a word, thus indicating that the message is an ad-
dress. The reception of this particular word wakes
up the receiver, resets the RWU bit and sets the
RDRF bit, which allows the receiver to receive this
word normally and to use it as an address word.
PR=13 and TR=RR=1, the transmit and receive
baud rates are 38400 baud.
Note: the baud rate registers MUST NOT be
changed while the transmitter or the receiver is en-
abled.
10.6.4.5 Extended Baud Rate Generation
The extended prescaler option gives a very fine
tuning on the baud rate, using a 255 value prescal-
er, whereas the conventional Baud Rate Genera-
tor retains industry standard software compatibili-
ty.
Caution: In Mute mode, do not write to the
SCICR2 register. If the SCI is in Mute mode during
the read operation (RWU=1) and a address mark
wake up event occurs (RWU is reset) before the
write operation, the RWU bit will be set again by
this write operation. Consequently the address
byte is lost and the SCI is not woken up from Mute
mode.
The extended baud rate generator block diagram
is described in the Figure 62.
The output clock rate sent to the transmitter or to
the receiver will be the output from the 16 divider
divided by a factor ranging from 1 to 255 set in the
SCIERPR or the SCIETPR register.
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SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.6.4.7 Parity Control
even number of “1s” if even parity is selected
(PS=0) or an odd number of “1s” if odd parity is se-
lected (PS=1). If the parity check fails, the PE flag
is set in the SCISR register and an interrupt is gen-
erated if PIE is set in the SCICR1 register.
Parity control (generation of parity bit in transmis-
sion and parity checking in reception) can be ena-
bled by setting the PCE bit in the SCICR1 register.
Depending on the frame length defined by the M
bit, the possible SCI frame formats are as listed in
Table 20.
10.6.4.8 SCI Clock Tolerance
During reception, each bit is sampled 16 times.
The majority of the 8th, 9th and 10th samples is
considered as the bit value. For a valid bit detec-
tion, all the three samples should have the same
value otherwise the noise flag (NF) is set. For ex-
ample: if the 8th, 9th and 10th samples are 0, 1
and 1 respectively, then the bit value will be “1”,
but the Noise Flag bit is be set because the three
samples values are not the same.
Table 20. Frame Formats
M bit
PCE bit
SCI frame
0
0
1
1
0
1
0
1
| SB | 8 bit data | STB |
| SB | 7-bit data | PB | STB |
| SB | 9-bit data | STB |
| SB | 8-bit data PB | STB |
Legend: SB = Start Bit, STB = Stop Bit,
PB = Parity Bit
Consequently, the bit length must be long enough
so that the 8th, 9th and 10th samples have the de-
sired bit value. This means the clock frequency
should not vary more than 6/16 (37.5%) within one
bit. The sampling clock is resynchronized at each
start bit, so that when receiving 10 bits (one start
bit, 1 data byte, 1 stop bit), the clock deviation
must not exceed 3.75%.
Note: In case of wake up by an address mark, the
MSB bit of the data is taken into account and not
the parity bit
Even parity: the parity bit is calculated to obtain
an even number of “1s” inside the frame made of
the 7 or 8 LSB bits (depending on whether M is
equal to 0 or 1) and the parity bit.
Note: The internal sampling clock of the microcon-
troller samples the pin value on every falling edge.
Therefore, the internal sampling clock and the time
the application expects the sampling to take place
may be out of sync. For example: If the baud rate
is 15.625 kbaud (bit length is 64µs), then the 8th,
9th and 10th samples will be at 28µs, 32µs & 36µs
respectively (the first sample starting ideally at
0µs). But if the falling edge of the internal clock oc-
curs just before the pin value changes, the sam-
ples would then be out of sync by ~4us. This
means the entire bit length must be at least 40µs
(36µs for the 10th sample + 4µs for synchroniza-
tion with the internal sampling clock).
Ex: data=00110101; 4 bits set => parity bit will be
0 if even parity is selected (PS bit = 0).
Odd parity: the parity bit is calculated to obtain an
odd number of “1s” inside the frame made of the 7
or 8 LSB bits (depending on whether M is equal to
0 or 1) and the parity bit.
Ex: data=00110101; 4 bits set => parity bit will be
1 if odd parity is selected (PS bit = 1).
Transmission mode: If the PCE bit is set then the
MSB bit of the data written in the data register is
not transmitted but is changed by the parity bit.
Reception mode: If the PCE bit is set then the in-
terface checks if the received data byte has an
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SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.6.4.9 Clock Deviation Causes
10.6.4.10 Noise Error Causes
The causes which contribute to the total deviation
are:
See also description of Noise error in Section
10.6.4.3.
– D
: Deviation due to transmitter error (Local
Start bit
TRA
oscillator error of the transmitter or the trans-
mitter is transmitting at a different baud rate).
The noise flag (NF) is set during start bit reception
if one of the following conditions occurs:
– D
: Error due to the baud rate quantisa-
QUANT
1. A valid falling edge is not detected. A falling
edge is considered to be valid if the 3 consecu-
tive samples before the falling edge occurs are
detected as '1' and, after the falling edge
occurs, during the sampling of the 16 samples,
if one of the samples numbered 3, 5 or 7 is
detected as a “1”.
tion of the receiver.
– D
: Deviation of the local oscillator of the
REC
receiver: This deviation can occur during the
reception of one complete SCI message as-
suming that the deviation has been compen-
sated at the beginning of the message.
– D
: Deviation due to the transmission line
2. During sampling of the 16 samples, if one of the
samples numbered 8, 9 or 10 is detected as a
“1”.
TCL
(generally due to the transceivers)
All the deviations of the system should be added
and compared to the SCI clock tolerance:
Therefore, a valid Start Bit must satisfy both the
above conditions to prevent the Noise Flag getting
set.
D
+ D
+ D
+ D
< 3.75%
TCL
TRA
QUANT
REC
Data Bits
The noise flag (NF) is set during normal data bit re-
ception if the following condition occurs:
– During the sampling of 16 samples, if all three
samples numbered 8, 9 and10 are not the same.
The majority of the 8th, 9th and 10th samples is
considered as the bit value.
Therefore, a valid Data Bit must have samples 8, 9
and 10 at the same value to prevent the Noise
Flag getting set.
Figure 63. Bit Sampling in Reception Mode
RDI LINE
sampled values
Sample
clock
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
6/16
7/16
7/16
One bit time
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ST72F521, ST72521B
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.6.5 Low Power Modes
Enable Exit
Control from from
Exit
Event
Flag
Interrupt Event
Mode
Description
Bit
Wait
Halt
No effect on SCI.
Transmit Data Register
Empty
TDRE
TC
TIE
Yes
No
WAIT
SCI interrupts cause the device to exit
from Wait mode.
Transmission Com-
plete
TCIE
RIE
Yes
Yes
No
No
SCI registers are frozen.
Received Data Ready
to be Read
RDRF
In Halt mode, the SCI stops transmit-
ting/receiving until Halt mode is exit-
ed.
HALT
Overrun Error Detected OR
Yes
Yes
Yes
No
No
No
Idle Line Detected
Parity Error
IDLE
PE
ILIE
PIE
10.6.6 Interrupts
The SCI interrupt events are connected to the
same interrupt vector.
rupt mask in the CC register is reset (RIM instruc-
tion).
These events generate an interrupt if the corre-
sponding Enable Control Bit is set and the inter-
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SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.6.7 Register Description
Note: The IDLE bit will not be set again until the
RDRF bit has been set itself (i.e. a new idle line oc-
curs).
STATUS REGISTER (SCISR)
Read Only
Reset Value: 1100 0000 (C0h)
Bit 3 = OR Overrun error.
7
0
This bit is set by hardware when the word currently
being received in the shift register is ready to be
transferred into the RDR register while RDRF=1.
An interrupt is generated if RIE=1 in the SCICR2
register. It is cleared by a software sequence (an
access to the SCISR register followed by a read to
the SCIDR register).
TDRE
TC
RDRF IDLE
OR
NF
FE
PE
Bit 7 = TDRE Transmit data register empty.
This bit is set by hardware when the content of the
TDR register has been transferred into the shift
register. An interrupt is generated if the TIE bit=1
in the SCICR2 register. It is cleared by a software
sequence (an access to the SCISR register fol-
lowed by a write to the SCIDR register).
0: No Overrun error
1: Overrun error is detected
Note: When this bit is set RDR register content will
not be lost but the shift register will be overwritten.
0: Data is not transferred to the shift register
1: Data is transferred to the shift register
Bit 2 = NF Noise flag.
Note: Data will not be transferred to the shift reg-
This bit is set by hardware when noise is detected
on a received frame. It is cleared by a software se-
quence (an access to the SCISR register followed
by a read to the SCIDR register).
0: No noise is detected
ister unless the TDRE bit is cleared.
Bit 6 = TC Transmission complete.
This bit is set by hardware when transmission of a
frame containing Data is complete. An interrupt is
generated if TCIE=1 in the SCICR2 register. It is
cleared by a software sequence (an access to the
SCISR register followed by a write to the SCIDR
register).
1: Noise is detected
Note: This bit does not generate interrupt as it ap-
pears at the same time as the RDRF bit which it-
self generates an interrupt.
0: Transmission is not complete
1: Transmission is complete
Bit 1 = FE Framing error.
This bit is set by hardware when a de-synchroniza-
tion, excessive noise or a break character is de-
tected. It is cleared by a software sequence (an
access to the SCISR register followed by a read to
the SCIDR register).
0: No Framing error is detected
1: Framing error or break character is detected
Note: TC is not set after the transmission of a Pre-
amble or a Break.
Bit 5 = RDRF Received data ready flag.
This bit is set by hardware when the content of the
RDR register has been transferred to the SCIDR
register. An interrupt is generated if RIE=1 in the
SCICR2 register. It is cleared by a software se-
quence (an access to the SCISR register followed
by a read to the SCIDR register).
Note: This bit does not generate interrupt as it ap-
pears at the same time as the RDRF bit which it-
self generates an interrupt. If the word currently
being transferred causes both frame error and
overrun error, it will be transferred and only the OR
bit will be set.
0: Data is not received
1: Received data is ready to be read
Bit 4 = IDLE Idle line detect.
This bit is set by hardware when a Idle Line is de-
tected. An interrupt is generated if the ILIE=1 in
the SCICR2 register. It is cleared by a software se-
quence (an access to the SCISR register followed
by a read to the SCIDR register).
0: No Idle Line is detected
1: Idle Line is detected
Bit 0 = PE Parity error.
This bit is set by hardware when a parity error oc-
curs in receiver mode. It is cleared by a software
sequence (a read to the status register followed by
an access to the SCIDR data register). An inter-
rupt is generated if PIE=1 in the SCICR1 register.
0: No parity error
1: Parity error
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SERIAL COMMUNICATIONS INTERFACE (Cont’d)
CONTROL REGISTER 1 (SCICR1)
Read/Write
Bit 3 = WAKE Wake-Up method.
This bit determines the SCI Wake-Up method, it is
set or cleared by software.
0: Idle Line
Reset Value: x000 0000 (x0h)
7
0
1: Address Mark
R8
T8
SCID
M
WAKE PCE
PS
PIE
Bit 2 = PCE Parity control enable.
This bit selects the hardware parity control (gener-
ation and detection). When the parity control is en-
abled, the computed parity is inserted at the MSB
position (9th bit if M=1; 8th bit if M=0) and parity is
checked on the received data. This bit is set and
cleared by software. Once it is set, PCE is active
after the current byte (in reception and in transmis-
sion).
Bit 7 = R8 Receive data bit 8.
This bit is used to store the 9th bit of the received
word when M=1.
Bit 6 = T8 Transmit data bit 8.
This bit is used to store the 9th bit of the transmit-
ted word when M=1.
0: Parity control disabled
1: Parity control enabled
Bit 5 = SCID Disabled for low power consumption
When this bit is set the SCI prescalers and outputs
are stopped and the end of the current byte trans-
fer in order to reduce power consumption.This bit
is set and cleared by software.
0: SCI enabled
1: SCI prescaler and outputs disabled
Bit 1 = PS Parity selection.
This bit selects the odd or even parity when the
parity generation/detection is enabled (PCE bit
set). It is set and cleared by software. The parity
will be selected after the current byte.
0: Even parity
1: Odd parity
Bit 4 = M Word length.
This bit determines the word length. It is set or
cleared by software.
0: 1 Start bit, 8 Data bits, 1 Stop bit
1: 1 Start bit, 9 Data bits, 1 Stop bit
Bit 0 = PIE Parity interrupt enable.
This bit enables the interrupt capability of the hard-
ware parity control when a parity error is detected
(PE bit set). It is set and cleared by software.
0: Parity error interrupt disabled
Note: The M bit must not be modified during a data
transfer (both transmission and reception).
1: Parity error interrupt enabled.
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ST72F521, ST72521B
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
CONTROL REGISTER 2 (SCICR2)
Read/Write
Notes:
– During transmission, a “0” pulse on the TE bit
(“0” followed by “1”) sends a preamble (idle line)
after the current word.
Reset Value: 0000 0000 (00h)
7
0
– When TE is set there is a 1 bit-time delay before
the transmission starts.
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
Caution: The TDO pin is free for general purpose
I/O only when the TE and RE bits are both cleared
(or if TE is never set).
Bit 7 = TIE Transmitter interrupt enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever
TDRE=1 in the SCISR register
Bit 2 = RE Receiver enable.
This bit enables the receiver. It is set and cleared
by software.
0: Receiver is disabled
1: Receiver is enabled and begins searching for a
start bit
Bit 6 = TCIE Transmission complete interrupt ena-
ble
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever TC=1 in
the SCISR register
Bit 1 = RWU Receiver wake-up.
This bit determines if the SCI is in mute mode or
not. It is set and cleared by software and can be
cleared by hardware when a wake-up sequence is
recognized.
0: Receiver in Active mode
1: Receiver in Mute mode
Bit 5 = RIE Receiver interrupt enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever OR=1
or RDRF=1 in the SCISR register
Note: Before selecting Mute mode (setting the
RWU bit), the SCI must receive some data first,
otherwise it cannot function in Mute mode with
wakeup by idle line detection.
Bit 4 = ILIE Idle line interrupt enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever IDLE=1
in the SCISR register.
Bit 0 = SBK Send break.
This bit set is used to send break characters. It is
set and cleared by software.
0: No break character is transmitted
1: Break characters are transmitted
Bit 3 = TE Transmitter enable.
This bit enables the transmitter. It is set and
cleared by software.
0: Transmitter is disabled
1: Transmitter is enabled
Note: If the SBK bit is set to “1” and then to “0”, the
transmitter will send a BREAK word at the end of
the current word.
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ST72F521, ST72521B
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
DATA REGISTER (SCIDR)
Read/Write
Bits 5:3 = SCT[2:0] SCI Transmitter rate divisor
These 3 bits, in conjunction with the SCP1 & SCP0
bits define the total division applied to the bus
clock to yield the transmit rate clock in convention-
al Baud Rate Generator mode.
Reset Value: Undefined
Contains the Received or Transmitted data char-
acter, depending on whether it is read from or writ-
ten to.
TR dividing factor
SCT2
SCT1
SCT0
1
2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
7
0
4
DR7
DR6
DR5
DR4
DR3
DR2
DR1
DR0
8
16
32
64
128
The Data register performs a double function (read
and write) since it is composed of two registers,
one for transmission (TDR) and one for reception
(RDR).
The TDR register provides the parallel interface
between the internal bus and the output shift reg-
ister (see Figure 60).
The RDR register provides the parallel interface
between the input shift register and the internal
bus (see Figure 60).
Bits 2:0 = SCR[2:0] SCI Receiver rate divisor.
These 3 bits, in conjunction with the SCP[1:0] bits
define the total division applied to the bus clock to
yield the receive rate clock in conventional Baud
Rate Generator mode.
RR Dividing factor
SCR2
SCR1
SCR0
BAUD RATE REGISTER (SCIBRR)
Read/Write
1
2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reset Value: 0000 0000 (00h)
4
7
0
8
16
32
64
128
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0
Bits 7:6= SCP[1:0] First SCI Prescaler
These 2 prescaling bits allow several standard
clock division ranges:
PR Prescaling factor
SCP1
SCP0
1
3
0
0
1
1
0
1
0
1
4
13
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SERIAL COMMUNICATIONS INTERFACE (Cont’d)
EXTENDED RECEIVE PRESCALER DIVISION
REGISTER (SCIERPR)
EXTENDED TRANSMIT PRESCALER DIVISION
REGISTER (SCIETPR)
Read/Write
Read/Write
Reset Value: 0000 0000 (00h)
Reset Value:0000 0000 (00h)
Allows setting of the Extended Prescaler rate divi-
sion factor for the receive circuit.
Allows setting of the External Prescaler rate divi-
sion factor for the transmit circuit.
7
0
7
0
ERPR ERPR ERPR ERPR ERPR ERPR ERPR ERPR
ETPR ETPR ETPR ETPR ETPR ETPR ETPR ETPR
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Bits 7:0 = ERPR[7:0] 8-bit Extended Receive
Prescaler Register.
Bits 7:0 = ETPR[7:0] 8-bit Extended Transmit
Prescaler Register.
The extended Baud Rate Generator is activated
when a value different from 00h is stored in this
register. Therefore the clock frequency issued
from the 16 divider (see Figure 62) is divided by
the binary factor set in the SCIERPR register (in
the range 1 to 255).
The extended Baud Rate Generator is activated
when a value different from 00h is stored in this
register. Therefore the clock frequency issued
from the 16 divider (see Figure 62) is divided by
the binary factor set in the SCIETPR register (in
the range 1 to 255).
The extended baud rate generator is not used af-
ter a reset.
The extended baud rate generator is not used af-
ter a reset.
Table 21. Baudrate Selection
Conditions
Baud
Rate
Symbol
Parameter
Standard
Unit
Accuracy
vs. Standard
Prescaler
f
CPU
Conventional Mode
TR (or RR)=128, PR=13
TR (or RR)= 32, PR=13
TR (or RR)= 16, PR=13
TR (or RR)= 8, PR=13
TR (or RR)= 4, PR=13
TR (or RR)= 16, PR= 3
TR (or RR)= 2, PR=13
TR (or RR)= 1, PR=13
300
~300.48
1200 ~1201.92
2400 ~2403.84
4800 ~4807.69
9600 ~9615.38
10400 ~10416.67
19200 ~19230.77
38400 ~38461.54
~0.16%
~0.79%
f
f
Tx
Communication frequency 8MHz
Hz
Rx
Extended Mode
ETPR (or ERPR) = 35,
TR (or RR)= 1, PR=1
14400 ~14285.71
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SERIAL COMMUNICATION INTERFACE (Cont’d)
Table 22. SCI Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
SCISR
Reset Value
TDRE
1
TC
1
RDRF
0
IDLE
0
OR
0
NF
0
FE
0
PE
0
0050h
0051h
0052h
0053h
0054h
0055h
0057h
SCIDR
Reset Value
MSB
x
LSB
x
x
x
x
x
x
x
SCIBRR
Reset Value
SCP1
0
SCP0
0
SCT2
0
SCT1
0
SCT0
0
SCR2
0
SCR1
0
SCR0
0
SCICR1
Reset Value
R8
x
T8
0
SCID
0
M
0
WAKE
0
PCE
0
PS
0
PIE
0
SCICR2
Reset Value
TIE
0
TCIE
0
RIE
0
ILIE
0
TE
0
RE
0
RWU
0
SBK
0
SCIERPR
Reset Value
MSB
0
LSB
0
0
0
0
0
0
0
0
0
0
0
0
0
SCIPETPR
Reset Value
MSB
0
LSB
0
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2
10.7 I C BUS INTERFACE (I2C)
10.7.1 Introduction
and vice versa, using either an interrupt or polled
handshake. The interrupts are enabled or disabled
by software. The interface is connected to the I C
2
The I C Bus Interface serves as an interface be-
tween the microcontroller and the serial I C bus. It
2
2
bus by a data pin (SDAI) and by a clock pin (SCLI).
provides both multimaster and slave functions,
2
2
It can be connected both with a standard I C bus
and controls all I C bus-specific sequencing, pro-
2
2
and a Fast I C bus. This selection is made by soft-
tocol, arbitration and timing. It supports fast I C
mode (400kHz).
ware.
Mode Selection
10.7.2 Main Features
■ Parallel-bus/I C protocol converter
■ Multi-master capability
2
The interface can operate in the four following
modes:
– Slave transmitter/receiver
■ 7-bit/10-bit Addressing
■ SMBus V1.1 Compliant
■ Transmitter/Receiver flag
■ End-of-byte transmission flag
■ Transfer problem detection
– Master transmitter/receiver
By default, it operates in slave mode.
The interface automatically switches from slave to
master after it generates a START condition and
from master to slave in case of arbitration loss or a
STOP generation, allowing then Multi-Master ca-
pability.
2
I C Master Features:
■ Clock generation
2
■ I C bus busy flag
Communication Flow
■ Arbitration Lost Flag
In Master mode, it initiates a data transfer and
generates the clock signal. A serial data transfer
always begins with a start condition and ends with
a stop condition. Both start and stop conditions are
generated in master mode by software.
■ End of byte transmission flag
■ Transmitter/Receiver Flag
■ Start bit detection flag
■ Start and Stop generation
In Slave mode, the interface is capable of recog-
nising its own address (7 or 10-bit), and the Gen-
eral Call address. The General Call address de-
tection may be enabled or disabled by software.
2
I C Slave Features:
■ Stop bit detection
2
■ I C bus busy flag
Data and addresses are transferred as 8-bit bytes,
MSB first. The first byte(s) following the start con-
dition contain the address (one in 7-bit mode, two
in 10-bit mode). The address is always transmitted
in Master mode.
■ Detection of misplaced start or stop condition
■ Programmable I C Address detection
■ Transfer problem detection
■ End-of-byte transmission flag
■ Transmitter/Receiver flag
10.7.3 General Description
2
A 9th clock pulse follows the 8 clock cycles of a
byte transfer, during which the receiver must send
an acknowledge bit to the transmitter. Refer to Fig-
ure 64.
In addition to receiving and transmitting data, this
interface converts it from serial to parallel format
2
Figure 64. I C BUS Protocol
SDA
MSB
ACK
SCL
1
2
8
9
START
STOP
CONDITION
CONDITION
VR02119B
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2
I C BUS INTERFACE (Cont’d)
Acknowledge may be enabled and disabled by
software.
The SCL frequency (F ) is controlled by a pro-
scl
grammable clock divider which depends on the
2
2
I C bus mode.
The I C interface address and/or general call ad-
2
dress can be selected by software.
When the I C cell is enabled, the SDA and SCL
2
ports must be configured as floating inputs. In this
case, the value of the external pull-up resistor
used depends on the application.
The speed of the I C interface may be selected
2
between Standard (up to 100KHz) and Fast I C
(up to 400KHz).
2
When the I C cell is disabled, the SDA and SCL
ports revert to being standard I/O port pins.
SDA/SCL Line Control
Transmitter mode: the interface holds the clock
line low before transmission to wait for the micro-
controller to write the byte in the Data Register.
Receiver mode: the interface holds the clock line
low after reception to wait for the microcontroller to
read the byte in the Data Register.
2
Figure 65. I C Interface Block Diagram
DATA REGISTER (DR)
DATA CONTROL
SDA or SDAI
DATA SHIFT REGISTER
COMPARATOR
OWN ADDRESS REGISTER 1 (OAR1)
OWN ADDRESS REGISTER 2 (OAR2)
CLOCK CONTROL
SCL or SCLI
CLOCK CONTROL REGISTER (CCR)
CONTROL REGISTER (CR)
STATUS REGISTER 1 (SR1)
STATUS REGISTER 2 (SR2)
CONTROL LOGIC
INTERRUPT
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2
I C BUS INTERFACE (Cont’d)
10.7.4 Functional Description
Then the interface waits for a read of the SR1 reg-
ister followed by a read of the DR register, holding
the SCL line low (see Figure 66 Transfer se-
quencing EV2).
Refer to the CR, SR1 and SR2 registers in Section
10.7.7. for the bit definitions.
2
By default the I C interface operates in Slave
Slave Transmitter
mode (M/SL bit is cleared) except when it initiates
a transmit or receive sequence.
Following the address reception and after SR1
register has been read, the slave sends bytes from
the DR register to the SDA line via the internal shift
register.
First the interface frequency must be configured
using the FRi bits in the OAR2 register.
10.7.4.1 Slave Mode
The slave waits for a read of the SR1 register fol-
lowed by a write in the DR register, holding the
SCL line low (see Figure 66 Transfer sequencing
EV3).
As soon as a start condition is detected, the
address is received from the SDA line and sent to
the shift register; then it is compared with the
address of the interface or the General Call
address (if selected by software).
When the acknowledge pulse is received:
– The EVF and BTF bits are set by hardware with
an interrupt if the ITE bit is set.
Note: In 10-bit addressing mode, the comparison
includes the header sequence (11110xx0) and the
two most significant bits of the address.
Closing slave communication
Header matched (10-bit mode only): the interface
generates an acknowledge pulse if the ACK bit is
set.
After the last data byte is transferred a Stop Con-
dition is generated by the master. The interface
detects this condition and sets:
Address not matched: the interface ignores it
and waits for another Start condition.
– EVF and STOPF bits with an interrupt if the ITE
bit is set.
Address matched: the interface generates in se-
quence:
Then the interface waits for a read of the SR2 reg-
ister (see Figure 66 Transfer sequencing EV4).
Error Cases
– Acknowledge pulse if the ACK bit is set.
– BERR: Detection of a Stop or a Start condition
during a byte transfer. In this case, the EVF and
the BERR bits are set with an interrupt if the ITE
bit is set.
If it is a Stop then the interface discards the data,
released the lines and waits for another Start
condition.
– EVF and ADSL bits are set with an interrupt if the
ITE bit is set.
Then the interface waits for a read of the SR1 reg-
ister, holding the SCL line low (see Figure 66
Transfer sequencing EV1).
Next, in 7-bit mode read the DR register to deter-
mine from the least significant bit (Data Direction
Bit) if the slave must enter Receiver or Transmitter
mode.
If it is a Start then the interface discards the data
and waits for the next slave address on the bus.
– AF: Detection of a non-acknowledge bit. In this
case, the EVF and AF bits are set with an inter-
rupt if the ITE bit is set.
In 10-bit mode, after receiving the address se-
quence the slave is always in receive mode. It will
enter transmit mode on receiving a repeated Start
condition followed by the header sequence with
matching address bits and the least significant bit
set (11110xx1).
The AF bit is cleared by reading the I2CSR2 reg-
ister. However, if read before the completion of
the transmission, the AF flag will be set again,
thus possibly generating a new interrupt. Soft-
ware must ensure either that the SCL line is back
at 0 before reading the SR2 register, or be able
to correctly handle a second interrupt during the
9th pulse of a transmitted byte.
Slave Receiver
Following the address reception and after SR1
register has been read, the slave receives bytes
from the SDA line into the DR register via the inter-
nal shift register. After each byte the interface gen-
erates in sequence:
Note: In case of errors, SCL line is not held low;
however, the SDA line can remain low if the last
bits transmitted are all 0. While AF=1, the SCL line
may be held low due to SB or BTF flags that are
set at the same time. It is then necessary to re-
lease both lines by software.
– Acknowledge pulse if the ACK bit is set
– EVF and BTF bits are set with an interrupt if the
ITE bit is set.
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2
I C INTERFACE (Cont’d)
How to release the SDA / SCL lines
Then the second address byte is sent by the inter-
face.
Set and subsequently clear the STOP bit while
BTF is set. The SDA/SCL lines are released after
the transfer of the current byte.
After completion of this transfer (and acknowledge
from the slave if the ACK bit is set):
SMBus Compatibility
– The EVF bit is set by hardware with interrupt
generation if the ITE bit is set.
2
ST7 I C is compatible with SMBus V1.1 protocol. It
supports all SMBus adressing modes, SMBus bus
protocols and CRC-8 packet error checking. Refer
to AN1713: SMBus Slave Driver For ST7 I C Pe-
Then the master waits for a read of the SR1 regis-
ter followed by a write in the CR register (for exam-
ple set PE bit), holding the SCL line low (see Fig-
ure 66 Transfer sequencing EV6).
2
ripheral.
10.7.4.2 Master Mode
Next the master must enter Receiver or Transmit-
ter mode.
To switch from default Slave mode to Master
mode a Start condition generation is needed.
Note: In 10-bit addressing mode, to switch the
master to Receiver mode, software must generate
a repeated Start condition and resend the header
sequence with the least significant bit set
(11110xx1).
Start condition
Setting the START bit while the BUSY bit is
cleared causes the interface to switch to Master
mode (M/SL bit set) and generates a Start condi-
tion.
Master Receiver
Following the address transmission and after SR1
and CR registers have been accessed, the master
receives bytes from the SDA line into the DR reg-
ister via the internal shift register. After each byte
the interface generates in sequence:
Once the Start condition is sent:
– The EVF and SB bits are set by hardware with
an interrupt if the ITE bit is set.
Then the master waits for a read of the SR1 regis-
ter followed by a write in the DR register with the
Slave address, holding the SCL line low (see
Figure 66 Transfer sequencing EV5).
– Acknowledge pulse if the ACK bit is set
– EVF and BTF bits are set by hardware with an in-
terrupt if the ITE bit is set.
Then the interface waits for a read of the SR1 reg-
ister followed by a read of the DR register, holding
the SCL line low (see Figure 66 Transfer se-
quencing EV7).
Slave address transmission
Then the slave address is sent to the SDA line via
the internal shift register.
To close the communication: before reading the
last byte from the DR register, set the STOP bit to
generate the Stop condition. The interface goes
automatically back to slave mode (M/SL bit
cleared).
In 7-bit addressing mode, one address byte is
sent.
In 10-bit addressing mode, sending the first byte
including the header sequence causes the follow-
ing event:
Note: In order to generate the non-acknowledge
pulse after the last received data byte, the ACK bit
must be cleared just before reading the second
last data byte.
– The EVF bit is set by hardware with interrupt
generation if the ITE bit is set.
Then the master waits for a read of the SR1 regis-
ter followed by a write in the DR register, holding
the SCL line low (see Figure 66 Transfer se-
quencing EV9).
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2
I C BUS INTERFACE (Cont’d)
Master Transmitter
of communication gives the possibility to reiniti-
ate transmission.
Multimaster Mode
Following the address transmission and after SR1
register has been read, the master sends bytes
from the DR register to the SDA line via the inter-
nal shift register.
Normally the BERR bit would be set whenever
unauthorized transmission takes place while
transfer is already in progress. However, an is-
sue will arise if an external master generates an
The master waits for a read of the SR1 register fol-
lowed by a write in the DR register, holding the
SCL line low (see Figure 66 Transfer sequencing
EV8).
2
unauthorized Start or Stop while the I C master
is on the first or second pulse of a 9-bit transac-
tion. It is possible to work around this by polling
2
the BUSY bit during I C master mode transmis-
When the acknowledge bit is received, the
interface sets:
sion. The resetting of the BUSY bit can then be
handled in a similar manner as the BERR flag
being set.
– EVF and BTF bits with an interrupt if the ITE bit
is set.
– AF: Detection of a non-acknowledge bit. In this
case, the EVF and AF bits are set by hardware
with an interrupt if the ITE bit is set. To resume,
set the Start or Stop bit.
The AF bit is cleared by reading the I2CSR2 reg-
ister. However, if read before the completion of
the transmission, the AF flag will be set again,
thus possibly generating a new interrupt. Soft-
ware must ensure either that the SCL line is back
at 0 before reading the SR2 register, or be able
to correctly handle a second interrupt during the
9th pulse of a transmitted byte.
To close the communication: after writing the last
byte to the DR register, set the STOP bit to gener-
ate the Stop condition. The interface goes auto-
matically back to slave mode (M/SL bit cleared).
Error Cases
– BERR: Detection of a Stop or a Start condition
during a byte transfer. In this case, the EVF and
BERR bits are set by hardware with an interrupt
if ITE is set.
Note that BERR will not be set if an error is de-
tected during the first or second pulse of each 9-
bit transaction:
– ARLO: Detection of an arbitration lost condition.
In this case the ARLO bit is set by hardware (with
an interrupt if the ITE bit is set and the interface
goes automatically back to slave mode (the M/SL
bit is cleared).
Single Master Mode
If a Start or Stop is issued during the first or sec-
ond pulse of a 9-bit transaction, the BERR flag
will not be set and transfer will continue however
the BUSY flag will be reset. To work around this,
slave devices should issue a NACK when they
receive a misplaced Start or Stop. The reception
of a NACK or BUSY by the master in the middle
Note: In all these cases, the SCL line is not held
low; however, the SDA line can remain low due to
possible «0» bits transmitted last. It is then neces-
sary to release both lines by software.
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2
I C BUS INTERFACE (Cont’d)
Figure 66. Transfer Sequencing
7-bit Slave receiver:
S
Address
A
Data1
A
Data1
Data1
Data2
EV3
A
Data2
Data2
DataN
A
P
.....
EV1
EV2
A
EV2
A
EV2
NA
EV4
7-bit Slave transmitter:
S
Address
A
DataN
P
.....
.....
EV1 EV3
EV3
EV3-1
EV4
7-bit Master receiver:
S
Address
A
A
A
DataN NA
P
EV5
EV6
EV7
A
EV7
A
EV7
A
7-bit Master transmitter:
S
Address
A
Data1
Data2
DataN
P
.....
EV5
EV6 EV8
EV8
EV8
EV8
10-bit Slave receiver:
S
Header
A
Address
A
Data1
A
DataN
A
P
.....
EV1
EV2
EV2
EV4
10-bit Slave transmitter:
S
Header
A
Data1
A
A
DataN
....
.
A
P
r
EV1 EV3
EV6 EV8
EV3
EV3-1
EV4
10-bit Master transmitter
S
Header
A
Address
A
Data1
DataN
A
P
.....
EV5
EV9
EV8
A
EV8
A
10-bit Master receiver:
S
Header
A
Data1
DataN
P
r
.....
EV5
EV6
EV7
EV7
Legend: S=Start, Sr = Repeated Start, P=Stop, A=Acknowledge, NA=Non-acknowledge,
EVx=Event (with interrupt if ITE=1)
EV1: EVF=1, ADSL=1, cleared by reading SR1 register.
EV2: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register.
EV3: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register.
EV3-1: EVF=1, AF=1, BTF=1; AF is cleared by reading SR1 register. BTF is cleared by releasing the
lines (STOP=1, STOP=0) or by writing DR register (DR=FFh). Note: If lines are released by
STOP=1, STOP=0, the subsequent EV4 is not seen.
EV4: EVF=1, STOPF=1, cleared by reading SR2 register.
EV5: EVF=1, SB=1, cleared by reading SR1 register followed by writing DR register.
EV6: EVF=1, cleared by reading SR1 register followed by writing CR register (for example PE=1).
EV7: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register.
EV8: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register.
EV9: EVF=1, ADD10=1, cleared by reading SR1 register followed by writing DR register.
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2
I C BUS INTERFACE (Cont’d)
10.7.5 Low Power Modes
Mode
Description
2
No effect on I C interface.
WAIT
HALT
2
I C interrupts cause the device to exit from WAIT mode.
2
I C registers are frozen.
2
2
In HALT mode, the I C interface is inactive and does not acknowledge data on the bus. The I C interface
resumes operation when the MCU is woken up by an interrupt with “exit from HALT mode” capability.
10.7.6 Interrupts
Figure 67. Event Flags and Interrupt Generation
ADD10
ITE
BTF
ADSL
SB
INTERRUPT
EVF
AF
STOPF
ARLO
BERR
*
* EVF can also be set by EV6 or an error from the SR2 register.
Enable
Control from
Bit
Exit
Exit
from
Halt
Event
Flag
Interrupt Event
Wait
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
10-bit Address Sent Event (Master mode)
End of Byte Transfer Event
ADD10
BTF
No
No
No
No
No
No
No
No
Address Matched Event (Slave mode)
Start Bit Generation Event (Master mode)
Acknowledge Failure Event
ADSEL
SB
ITE
AF
Stop Detection Event (Slave mode)
Arbitration Lost Event (Multimaster configuration)
Bus Error Event
STOPF
ARLO
BERR
2
Note: The I C interrupt events are connected to
the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding
Enable Control Bit is set and the I-bit in the CC reg-
ister is reset (RIM instruction).
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2
I C BUS INTERFACE (Cont’d)
10.7.7 Register Description
– In slave mode:
0: No start generation
1: Start generation when the bus is free
2
I C CONTROL REGISTER (CR)
Read / Write
Reset Value: 0000 0000 (00h)
Bit 2 = ACK Acknowledge enable.
This bit is set and cleared by software. It is also
cleared by hardware when the interface is disa-
bled (PE=0).
7
0
0
0
PE
ENGC START ACK STOP
ITE
0: No acknowledge returned
1: Acknowledge returned after an address byte or
a data byte is received
Bit 7:6 = Reserved. Forced to 0 by hardware.
Bit 1 = STOP Generation of a Stop condition.
This bit is set and cleared by software. It is also
cleared by hardware in master mode. Note: This
bit is not cleared when the interface is disabled
(PE=0).
Bit 5 = PE Peripheral enable.
This bit is set and cleared by software.
0: Peripheral disabled
1: Master/Slave capability
Notes:
– When PE=0, all the bits of the CR register and
the SR register except the Stop bit are reset. All
outputs are released while PE=0
– In master mode:
0: No stop generation
1: Stop generation after the current byte transfer
or after the current Start condition is sent. The
STOP bit is cleared by hardware when the Stop
condition is sent.
– When PE=1, the corresponding I/O pins are se-
lected by hardware as alternate functions.
2
– To enable the I C interface, write the CR register
TWICE with PE=1 as the first write only activates
the interface (only PE is set).
– In slave mode:
0: No stop generation
1: Release the SCL and SDA lines after the cur-
rent byte transfer (BTF=1). In this mode the
STOP bit has to be cleared by software.
Bit 4 = ENGC Enable General Call.
This bit is set and cleared by software. It is also
cleared by hardware when the interface is disa-
bled (PE=0). The 00h General Call address is ac-
knowledged (01h ignored).
0: General Call disabled
1: General Call enabled
Bit 0 = ITE Interrupt enable.
This bit is set and cleared by software and cleared
by hardware when the interface is disabled
(PE=0).
0: Interrupts disabled
1: Interrupts enabled
Refer to Figure 67 for the relationship between the
events and the interrupt.
SCL is held low when the ADD10, SB, BTF or
ADSL flags or an EV6 event (See Figure 66) is de-
tected.
Note: In accordance with the I2C standard, when
GCAL addressing is enabled, an I2C slave can
only receive data. It will not transmit data to the
master.
Bit 3 = START Generation of a Start condition.
This bit is set and cleared by software. It is also
cleared by hardware when the interface is disa-
bled (PE=0) or when the Start condition is sent
(with interrupt generation if ITE=1).
– In master mode:
0: No start generation
1: Repeated start generation
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2
I C BUS INTERFACE (Cont’d)
2
I C STATUS REGISTER 1 (SR1)
1: Data byte transmitted
Read Only
Reset Value: 0000 0000 (00h)
Bit 4 = BUSY Bus busy.
This bit is set by hardware on detection of a Start
condition and cleared by hardware on detection of
a Stop condition. It indicates a communication in
progress on the bus. The BUSY flag of the I2CSR1
register is cleared if a Bus Error occurs.
0: No communication on the bus
7
0
EVF ADD10 TRA BUSY BTF ADSL M/SL
SB
Bit 7 = EVF Event flag.
1: Communication ongoing on the bus
Note:
This bit is set by hardware as soon as an event oc-
curs. It is cleared by software reading SR2 register
in case of error event or as described in Figure 66.
It is also cleared by hardware when the interface is
disabled (PE=0).
0: No event
1: One of the following events has occurred:
– The BUSY flag is NOT updated when the inter-
face is disabled (PE=0). This can have conse-
quences when operating in Multimaster mode;
2
i.e. a second active I C master commencing a
transfer with an unset BUSY bit can cause a con-
flict resulting in lost data. A software workaround
– BTF=1 (Byte received or transmitted)
2
consists of checking that the I C is not busy be-
2
– ADSL=1 (Address matched in Slave mode
while ACK=1)
fore enabling the I C Multimaster cell.
– SB=1 (Start condition generated in Master
mode)
Bit 3 = BTF Byte transfer finished.
This bit is set by hardware as soon as a byte is cor-
rectly received or transmitted with interrupt gener-
ation if ITE=1. It is cleared by software reading
SR1 register followed by a read or write of DR reg-
ister. It is also cleared by hardware when the inter-
face is disabled (PE=0).
– AF=1 (No acknowledge received after byte
transmission)
– STOPF=1 (Stop condition detected in Slave
mode)
– ARLO=1 (Arbitration lost in Master mode)
– Following a byte transmission, this bit is set after
reception of the acknowledge clock pulse. In
case an address byte is sent, this bit is set only
after the EV6 event (See Figure 66). BTF is
cleared by reading SR1 register followed by writ-
ing the next byte in DR register.
– BERR=1 (Bus error, misplaced Start or Stop
condition detected)
– ADD10=1 (Master has sent header byte)
– Address byte successfully transmitted in Mas-
ter mode.
– Following a byte reception, this bit is set after
transmission of the acknowledge clock pulse if
ACK=1. BTF is cleared by reading SR1 register
followed by reading the byte from DR register.
Bit 6 = ADD10 10-bit addressing in Master mode.
This bit is set by hardware when the master has
sent the first byte in 10-bit address mode. It is
cleared by software reading SR2 register followed
by a write in the DR register of the second address
byte. It is also cleared by hardware when the pe-
ripheral is disabled (PE=0).
The SCL line is held low while BTF=1.
0: Byte transfer not done
1: Byte transfer succeeded
0: No ADD10 event occurred.
1: Master has sent first address byte (header)
Bit 2 = ADSL Address matched (Slave mode).
This bit is set by hardware as soon as the received
slave address matched with the OAR register con-
tent or a general call is recognized. An interrupt is
generated if ITE=1. It is cleared by software read-
ing SR1 register or by hardware when the inter-
face is disabled (PE=0).
Bit 5 = TRA Transmitter/Receiver.
When BTF is set, TRA=1 if a data byte has been
transmitted. It is cleared automatically when BTF
is cleared. It is also cleared by hardware after de-
tection of Stop condition (STOPF=1), loss of bus
arbitration (ARLO=1) or when the interface is disa-
bled (PE=0).
The SCL line is held low while ADSL=1.
0: Address mismatched or not received
1: Received address matched
0: Data byte received (if BTF=1)
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2
I C BUS INTERFACE (Cont’d)
Bit 1 = M/SL Master/Slave.
The SCL line is not held low while STOPF=1.
This bit is set by hardware as soon as the interface
is in Master mode (writing START=1). It is cleared
by hardware after detecting a Stop condition on
the bus or a loss of arbitration (ARLO=1). It is also
cleared when the interface is disabled (PE=0).
0: Slave mode
0: No Stop condition detected
1: Stop condition detected
Bit 2 = ARLO Arbitration lost.
This bit is set by hardware when the interface los-
es the arbitration of the bus to another master. An
interrupt is generated if ITE=1. It is cleared by soft-
ware reading SR2 register or by hardware when
the interface is disabled (PE=0).
1: Master mode
Bit 0 = SB Start bit (Master mode).
This bit is set by hardware as soon as the Start
After an ARLO event the interface switches back
automatically to Slave mode (M/SL=0).
condition is generated (following
a
write
START=1). An interrupt is generated if ITE=1. It is
cleared by software reading SR1 register followed
by writing the address byte in DR register. It is also
cleared by hardware when the interface is disa-
bled (PE=0).
0: No Start condition
1: Start condition generated
The SCL line is not held low while ARLO=1.
0: No arbitration lost detected
1: Arbitration lost detected
Note:
– In a Multimaster environment, when the interface
is configured in Master Receive mode it does not
perform arbitration during the reception of the
Acknowledge Bit. Mishandling of the ARLO bit
from the I2CSR2 register may occur when a sec-
ond master simultaneously requests the same
data from the same slave and the I C master
does not acknowledge the data. The ARLO bit is
then left at 0 instead of being set.
2
I C STATUS REGISTER 2 (SR2)
Read Only
Reset Value: 0000 0000 (00h)
2
7
0
0
0
0
AF STOPF ARLO BERR GCAL
Bit 1 = BERR Bus error.
This bit is set by hardware when the interface de-
tects a misplaced Start or Stop condition. An inter-
rupt is generated if ITE=1. It is cleared by software
reading SR2 register or by hardware when the in-
terface is disabled (PE=0).
Bit 7:5 = Reserved. Forced to 0 by hardware.
Bit 4 = AF Acknowledge failure.
This bit is set by hardware when no acknowledge
is returned. An interrupt is generated if ITE=1. It is
cleared by software reading SR2 register or by
hardware when the interface is disabled (PE=0).
The SCL line is not held low while BERR=1.
0: No misplaced Start or Stop condition
1: Misplaced Start or Stop condition
Note:
– If a Bus Error occurs, a Stop or a repeated Start
condition should be generated by the Master to
re-synchronize communication, get the transmis-
sion acknowledged and the bus released for fur-
ther communication
The SCL line is not held low while AF=1 but by oth-
er flags (SB or BTF) that are set at the same time.
0: No acknowledge failure
1: Acknowledge failure
Note:
– When an AF event occurs, the SCL line is not
held low; however, the SDA line can remain low
if the last bits transmitted are all 0. It is then nec-
essary to release both lines by software.
Bit 0 = GCAL General Call (Slave mode).
This bit is set by hardware when a general call ad-
dress is detected on the bus while ENGC=1. It is
cleared by hardware detecting a Stop condition
(STOPF=1) or when the interface is disabled
(PE=0).
Bit 3 = STOPF Stop detection (Slave mode).
This bit is set by hardware when a Stop condition
is detected on the bus after an acknowledge (if
ACK=1). An interrupt is generated if ITE=1. It is
cleared by software reading SR2 register or by
hardware when the interface is disabled (PE=0).
0: No general call address detected on bus
1: general call address detected on bus
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2
I C BUS INTERFACE (Cont’d)
2
2
I C CLOCK CONTROL REGISTER (CCR)
I C DATA REGISTER (DR)
Read / Write
Reset Value: 0000 0000 (00h)
Read / Write
Reset Value: 0000 0000 (00h)
7
0
7
0
FM/SM CC6
CC5
CC4
CC3
CC2
CC1
CC0
D7
D6
D5
D4
D3
D2
D1
D0
2
Bit 7 = FM/SM Fast/Standard I C mode.
This bit is set and cleared by software. It is not
cleared when the interface is disabled (PE=0).
Bit 7:0 = D[7:0] 8-bit Data Register.
These bits contain the byte to be received or trans-
mitted on the bus.
2
0: Standard I C mode
2
1: Fast I C mode
– Transmitter mode: Byte transmission start auto-
matically when the software writes in the DR reg-
ister.
Bit 6:0 = CC[6:0] 7-bit clock divider.
These bits select the speed of the bus (F
pending on the I C mode. They are not cleared
when the interface is disabled (PE=0).
) de-
SCL
– Receiver mode: the first data byte is received au-
tomatically in the DR register using the least sig-
nificant bit of the address.
2
Refer to the Electrical Characteristics section for
the table of values.
Then, the following data bytes are received one
by one after reading the DR register.
Note: The programmed F
SCL and SDA lines.
assumes no load on
SCL
126/215
ST72F521, ST72521B
2
I C BUS INTERFACE (Cont’d)
2
2
I C OWN ADDRESS REGISTER (OAR1)
I C OWN ADDRESS REGISTER (OAR2)
Read / Write
Reset Value: 0000 0000 (00h)
Read / Write
Reset Value: 0100 0000 (40h)
7
0
7
0
0
ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0
FR1
FR0
0
0
0
ADD9 ADD8
7-bit Addressing Mode
Bit 7:6 = FR[1:0] Frequency bits.
Bit 7:1 = ADD[7:1] Interface address.
These bits define the I C bus address of the inter-
face. They are not cleared when the interface is
disabled (PE=0).
These bits are set by software only when the inter-
face is disabled (PE=0). To configure the interface
to I C specified delays select the value corre-
2
2
sponding to the microcontroller frequency F
.
CPU
f
FR1
0
FR0
CPU
Bit 0 = ADD0 Address direction bit.
This bit is don’t care, the interface acknowledges
either 0 or 1. It is not cleared when the interface is
disabled (PE=0).
< 6 MHz
0
1
6 to 8 MHz
0
Note: Address 01h is always ignored.
Bit 5:3 = Reserved
10-bit Addressing Mode
Bit 2:1 = ADD[9:8] Interface address.
2
These are the most significant bits of the I C bus
address of the interface (10-bit mode only). They
are not cleared when the interface is disabled
(PE=0).
Bit 7:0 = ADD[7:0] Interface address.
These are the least significant bits of the I C bus
address of the interface. They are not cleared
when the interface is disabled (PE=0).
2
Bit 0 = Reserved.
127/215
ST72F521, ST72521B
I²C BUS INTERFACE (Cont’d)
2
Table 23. I C Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
I2CCR
Reset Value
PE
0
ENGC
0
START
0
ACK
0
STOP
0
ITE
0
0018h
0019h
001Ah
001Bh
001Ch
001Dh
001Eh
0
0
I2CSR1
Reset Value
EVF
0
ADD10
0
TRA
0
BUSY
0
BTF
0
ADSL
0
M/SL
0
SB
0
I2CSR2
Reset Value
AF
0
STOPF
0
ARLO
0
BERR
0
GCAL
0
0
0
0
I2CCCR
Reset Value
FM/SM
0
CC6
0
CC5
0
CC4
0
CC3
0
CC2
0
CC1
0
CC0
0
I2COAR1
Reset Value
ADD7
0
ADD6
0
ADD5
0
ADD4
0
ADD3
0
ADD2
0
ADD1
0
ADD0
0
I2COAR2
Reset Value
FR1
0
FR0
1
ADD9
0
ADD8
0
0
0
0
0
0
0
0
I2CDR
Reset Value
MSB
0
LSB
0
0
0
0
128/215
ST72F521, ST72521B
10.8 CONTROLLER AREA NETWORK (CAN)
10.8.1 Introduction
are checked for correctness and acknowledged
accordingly although such frames cannot be trans-
mitted nor received. The same applies to overload
frames which are recognized but never initiated.
This peripheral is designed to support serial data
exchanges using a multi-master contention based
priority scheme as described in CAN specification
Rev. 2.0 part A. It can also be connected to a 2.0 B
network without problems, since extended frames
Figure 68. CAN Block Diagram
ST7 Internal Bus
ST7 Interface
PSR
BRPR
BTR
TX/RX
Buffer 1
TX/RX
Buffer 2
TX/RX
Buffer 3
ID
Filter 0
ID
Filter 1
10 Bytes
10 Bytes
10 Bytes
4 Bytes
4 Bytes
ICR
ISR
RX
TX
SHREG
BTL
BCDL
EML
CRC
CSR
TECR
RECR
CAN 2.0B passive Core
129/215
ST72F521, ST72521B
CONTROLLER AREA NETWORK (Cont’d)
10.8.2 Main Features
The acknowledgement (ACK) field comprises the
ACK slot and the ACK delimiter. The bit in the ACK
slot is placed on the bus by the transmitter as a re-
cessive bit (logical 1). It is overwritten as a domi-
nant bit (logical 0) by those receivers which have
at this time received the data correctly. In this way,
the transmitting node can be assured that at least
one receiver has correctly received its message.
Note that messages are acknowledged by the re-
ceivers regardless of the outcome of the accept-
ance test.
– Support of CAN specification 2.0A and 2.0B pas-
sive
– Three prioritized 10-byte Transmit/Receive mes-
sage buffers
– Two programmable global 12-bit message ac-
ceptance filters
– Programmable baud rates up to 1 MBit/s
– Buffer flip-flopping capability in transmission
– Maskable interrupts for transmit, receive (one
per buffer), error and wake-up
The end of the message is indicated by the End Of
Frame (EOF). The intermission field defines the
minimum number of bit periods separating con-
secutive messages. If there is no subsequent bus
access by any station, the bus remains idle.
– Automatic low-power mode after 20 recessive
bits or on demand (standby mode)
– Interrupt-driven wake-up from standby mode
upon reception of dominant pulse
10.8.3.2 Hardware Blocks
The CAN controller contains the following func-
tional blocks (refer to Figure 68):
– Optional dominant pulse transmission on leaving
standby mode
– ST7 Interface: buffering of the ST7 internal bus
and address decoding of the CAN registers.
– Automatic message queuing for transmission
upon writing of data byte 7
– TX/RX Buffers: three 10-byte buffers for trans-
mission and reception of maximum length mes-
sages.
– Programmable loop-back mode for self-test op-
eration
– Advanced error detection and diagnosis func-
tions
– ID Filters: two 12-bit compare and don’t care
masks for message acceptance filtering.
– Software-efficient buffer mapping at a unique ad-
dress space
– PSR: page selection register (see memory map).
– BRPR: clock divider for different data rates.
– BTR: bit timing register.
– Scalable architecture.
10.8.3 Functional Description
10.8.3.1 Frame Formats
– ICR: interrupt control register.
– ISR: interrupt status register.
A summary of all the CAN frame formats is given
in Figure 69 for reference. It covers only the stand-
ard frame format since the extended one is only
acknowledged.
– CSR: general purpose control/status register.
– TECR: transmit error counter register.
– RECR: receive error counter register.
A message begins with a start bit called Start Of
Frame (SOF). This bit is followed by the arbitration
field which contains the 11-bit identifier (ID) and
the Remote Transmission Request bit (RTR). The
RTR bit indicates whether it is a data frame or a re-
mote request frame. A remote request frame does
not have any data byte.
– BTL: bit timing logic providing programmable bit
sampling and bit clock generation for synchroni-
zation of the controller.
– BCDL: bit coding logic generating a NRZ-coded
datastream with stuff bits.
– SHREG: 8-bit shift register for serialization of
data to be transmitted and parallelisation of re-
ceived data.
The control field contains the Identifier Extension
bit (IDE), which indicates standard or extended
format, a reserved bit (ro) and, in the last four bits,
a count of the data bytes (DLC). The data field
ranges from zero to eight bytes and is followed by
the Cyclic Redundancy Check (CRC) used as a
frame integrity check for detecting bit errors.
– CRC: 15-bit CRC calculator and checker.
– EML: error detection and management logic.
– CAN Core: CAN 2.0B passive protocol control-
ler.
130/215
ST72F521, ST72521B
CONTROLLER AREA NETWORK (Cont’d)
Figure 69. CAN Frames
Inter-Frame Space
or Overload Frame
Inter-Frame Space
Data Frame
44 + 8 * N
Ack Field
Control Field Data Field
CRC Field
16
Arbitration Field
12
2
6
8 * N
7
ID
CRC
EOF
DLC
Inter-Frame Space
or Overload Frame
Inter-Frame Space
Remote Frame
44
Ack Field End Of Frame
Control Field
6
CRC Field
16
Arbitration Field
12
2
7
ID
CRC
DLC
Data Frame or
Remote Frame
Inter-Frame Space
or Overload Frame
Error Frame
Flag Echo Error Delimiter
Error Flag
≤ 6
8
6
Notes:
Data Frame or
Remote Frame
Any Frame
Inter-Frame Space
Suspend
Transmission
8
• 0
<= N
<= 8
• SOF = Start Of Frame
• ID = Identifier
Intermission
Bus Idle
3
• RTR = Remote Transmission Request
• IDE = Identifier Extension Bit
• r0 = Reserved Bit
• DLC = Data Length Code
End Of Frame or
Error Delimiter or
Overload Delimiter
Inter-Frame Space
or Error Frame
• CRC = Cyclic Redundancy Code
• Error flag: 6 dominant bits if node is error
active else 6 recessive bits.
• Suspend transmission: applies to error
passive nodes only.
Overload Frame
Overload Flag Overload Delimiter
6
8
• EOF = End of Frame
• ACK = Acknowledge bit
131/215
ST72F521, ST72521B
CONTROLLER AREA NETWORK (Cont’d)
10.8.3.3 Modes of Operation
bit. If the WKPS bit is set in the CSR register,
then the controller passes through WAKE-UP
otherwise it enters RESYNC directly.
It is important to note that the wake-up mecha-
nism is software-driven and therefore carries a
significant time overhead. All messages received
after the wake-up bit and before the controller is
set to run and has completed synchronization
are ignored.
The CAN Core unit assumes one of the seven
states described below:
– STANDBY. Standby mode is entered either on a
chip reset or on resetting the RUN bit in the Con-
trol/Status Register (CSR). Any on-going trans-
mission or reception operation is not interrupted
and completes normally before the Bit Time Log-
ic and the clock prescaler are turned off for mini-
mum power consumption. This state is signalled
by the RUN bit being read-back as 0.
Once in standby, the only event monitored is the
reception of a dominant bit which causes a wake-
up interrupt if the SCIE bit of the Interrupt Control
Register (ICR) is set.
Note: Standby mode is not entered on resetting
the RUN bit in the Control/Status register (CSR) if
the CANRX pin is shorted to GND.
– WAKE-UP. The CAN bus line is forced to domi-
nant for one bit time signalling the wake-up con-
dition to all other bus members.
The STANDBY mode is left by setting the RUN
Figure 70. CAN Controller State Diagram
ARESET
RUN & WKPS
STANDBY
RESYNC
RUN
RUN & WKPS
WAKE-UP
FSYN & BOFF & 11 Recessive bits |
(FSYN | BOFF) & 128 * 11 Recessive bits
RUN
IDLE
Write to DATA7 |
Start Of Frame
RX OK
TX Error & NRTX
TX OK
Arbitration lost
TRANSMISSION
TX Error
RECEPTION
RX Error
BOFF
ERROR
BOFF
n
132/215
ST72F521, ST72521B
CONTROLLER AREA NETWORK (Cont’d)
– RESYNC. The resynchronization mode is used
to find the correct entry point for starting trans-
mission or reception after the node has gone
asynchronous either by going into the STANDBY
or bus-off states.
Resynchronization is achieved when 128 se-
quences of 11 recessive bits have been moni-
tored unless the node is not bus-off and the
FSYN bit in the CSR register is set in which case
a single sequence of 11 recessive bits needs to
be monitored.
allows transmitted messages to be simultane-
ously received when they pass the acceptance
filtering. This is particularly useful for checking
the integrity of the communication path.
RECEPTION. Once the CAN controller has syn-
chronized itself onto the bus activity, it is ready
for reception of new messages. Every incoming
message gets its identifier compared to the ac-
ceptance filters. If the bitwise comparison of the
selected bits ends up with a match for at least
one of the filters then that message is elected for
reception and a target buffer is searched for. This
buffer will be the first one - order is 1 to 3 - that
has the LOCK and RDY bits of its BCSRx regis-
ter reset.
– IDLE. The CAN controller looks for one of the fol-
lowing events: the RUN bit is reset, a Start Of
Frame appears on the CAN bus or the DATA7
register of the currently active page is written to.
– When no such buffer exists then an overrun
interrupt is generated if the ORIE bit of the ICR
register has been set. In this case the identifi-
er of the last message is made available in the
Last Identifier Register (LIDHR and LIDLR) at
least until it gets overwritten by a new identifi-
er picked-up from the bus.
– When a buffer does exist, the accepted mes-
sage gets written into it, the ACC bit in the
BCSRx register gets the number of the match-
ing filter, the RDY and RXIF bits get set and an
interrupt is generated if the RXIE bit in the ISR
register is set.
Up to three messages can be automatically
received without intervention from the CPU
because each buffer has its own set of status
bits, greatly reducing the reactiveness require-
ments in the processing of the receive inter-
rupts.
– TRANSMISSION. Once the LOCK bit of a Buffer
Control/Status Register (BCSRx) has been set
and read back as such, a transmit job can be
submitted by writing to the DATA7 register. The
message with the highest priority will be transmit-
ted as soon as the CAN bus becomes idle.
Among those messages with a pending trans-
mission request, the highest priority is given to
Buffer 3 then 2 and 1. If the transmission fails due
to a lost arbitration or to an error while the NRTX
bit of the CSR register is reset, then a new trans-
mission attempt is performed. This goes on until
the transmission ends successfully or until the
job is cancelled by unlocking the buffer, by set-
ting the NRTX bit or if the node ever enters bus-
off or if a higher priority message becomes pend-
ing. The RDY bit in the BCSRx register, which
was set since the job was submitted, gets reset.
When a transmission is in progress, the BUSY bit
in the BCSRx register is set. If it ends successful-
ly then the TXIF bit in the Interrupt Status Regis-
ter (ISR) is set, else the TEIF bit is set. An
interrupt is generated in either case provided the
TXIE and TEIE bits of the ICR register are set.
Note 1: Setting the SRTE bit of the CSR register
133/215
ST72F521, ST72521B
CONTROLLER AREA NETWORK (Cont’d)
– ERROR. The error management as described in
the CAN protocol is completely handled by hard-
ware using 2 error counters which get increment-
ed or decremented according to the error
cation to determine the stability of the network.
Moreover, as one of the node status bits (EPSV
or BOFF of the CSR register) changes, an inter-
rupt is generated if the SCIE bit is set in the ICR
Register. Refer to Figure 71.
condition. Both of them may be read by the appli-
Figure 71. CAN Error State Diagram
When TECR or RECR > 127, the EPSV bit gets set
ERROR ACTIVE
ERROR PASSIVE
When TECR and RECR < 128,
the EPSV bit gets cleared
When 128 * 11 recessive bits occur:
- the BOFF bit gets cleared
When TECR > 255 the BOFF bit gets set
and the EPSV bit gets cleared
- the TECR register gets cleared
- the RECR register gets cleared
BUS OFF
134/215
ST72F521, ST72521B
CONTROLLER AREA NETWORK (Cont’d)
10.8.3.4 Bit Timing Logic
– Resynchronization Jump Width (RJW): de-
fines an upper bound to the amount of lengthen-
ing or shortening of the bit segments. It is
The bit timing logic monitors the serial bus-line and
performs sampling and adjustment of the sample
point by synchronizing on the start-bit edge and re-
synchronizing on following edges.
programmable between 1 and 4 time quanta.
To guarantee the correct behaviour of the CAN
controller, SYNC_SEG + BS1 + BS2 must be
greater than or equal to 5 time quanta.
Its operation may be explained simply when the
nominal bit time is divided into three segments as
follows:
The CAN controller resynchronizes on recessive
to dominant edges only.
– Synchronisation segment (SYNC_SEG): a bit
change is expected to lie within this time seg-
ment. It has a fixed length of one time quanta (1
For a detailed description of the CAN resynchroni-
zation mechanism and other bit timing configura-
tion constraints, please refer to the Bosch CAN
standard 2.0.
x t
).
CAN
– Bit segment 1 (BS1): defines the location of the
sample point. It includes the PROP_SEG and
PHASE_SEG1 of the CAN standard. Its duration
is programmable between 1 and 16 time quanta
but may be automatically lengthened to compen-
sate for positive phase drifts due to differences in
the frequency of the various nodes of the net-
work.
As a safeguard against programming errors, the
configuration of the Bit Timing Register (BTR) is
only possible while the device is in STANDBY
mode.
– Bit segment 2 (BS2): defines the location of the
transmit point. It represents the PHASE_SEG2
of the CAN standard. Its duration is programma-
ble between 1 and 8 time quanta but may also be
automatically shortened to compensate for neg-
ative phase drifts.
Figure 72. Bit Timing
NOMINAL BIT TIME
BIT SEGMENT 1 (BS1)
SYNC_SEG
BIT SEGMENT 2 (BS2)
1 x t
t
t
BS2
CAN
BS1
SAMPLE POINT
TRANSMIT POINT
135/215
ST72F521, ST72521B
CONTROLLER AREA NETWORK (Cont’d)
Bit 4 = TXIF Transmit Interrupt Flag
− Read/Clear
10.8.4 Register Description
The CAN registers are organized as 6 general pur-
pose registers plus 5 pages of 16 registers span-
ning the same address space and primarily used
for message and filter storage. The page actually
selected is defined by the content of the Page Se-
lection Register.
Set by hardware to signal that the highest priority
message queued for transmission has been suc-
cessfully transmitted.
Cleared by software.
Bit 3 = SCIF Status Change Interrupt Flag
− Read/Clear
10.8.4.1 General Purpose Registers
INTERRUPT STATUS REGISTER (ISR)
Read/Write
Set by hardware to signal the reception of a domi-
nant bit while in standby mode. In Run mode this bit
is set when EPVS is set or reset (refer to Figure 71.
CAN Error State Diagram). This bit also signals any
receive error when ESCI=1.
Reset Value: 00h
Cleared by software.
7
0
Bit 2 = ORIF Overrun Interrupt Flag
− Read/Clear
RXIF3 RXIF2 RXIF1 TXIF SCIF ORIF TEIF EPND
Set by hardware to signal that a message could not
be stored because no receive buffer was available.
Cleared by software.
Bit 7 = RXIF3 Receive Interrupt Flag for Buffer 3
− Read/Clear
Bit 1 = TEIF Transmit Error Interrupt Flag
− Read/Clear
Setby hardwaretosignal thatanew error-freemes-
sage is available in buffer 3.
Setbyhardwaretosignalthatanerroroccurreddur-
ing the transmission of the highest priority message
queued for transmission.
Cleared by software to release buffer 3.
Also cleared by resetting bit RDY of BCSR3.
Cleared by software.
Bit 6 = RXIF2 Receive Interrupt Flag for Buffer 2
− Read/Clear
Bit 0 = EPND Error Interrupt Pending
− Read Only
Set by hardware to signal that a new error-free
message is available in buffer 2.
Set by hardware when at least one of the three error
interrupt flags SCIF, ORIF or TEIF is set.
Reset by hardware when all error interrupt flags
have been cleared.
Cleared by software to release buffer 2.
Also cleared by resetting bit RDY of BCSR2.
Bit 5 = RXIF1 Receive Interrupt Flag for Buffer 1
− Read/Clear
Caution:
Setby hardwaretosignal thatanew error-freemes-
sage is available in buffer 1.
Interrupt flags are reset by writing a “0” to the cor-
responding bit position. The appropriate way con-
sistsinwritinganimmediatemaskortheone’scom-
plement of the register content initially read by the
interrupt handler. Bit manipulation instruction
BRES should never be used due to its read-modify-
write nature.
Cleared by software to release buffer 1.
Also cleared by resetting bit RDY of BCSR1.
136/215
ST72F521, ST72521B
CONTROLLER AREA NETWORK (Cont’d)
whenever a message has been successfully trans-
mitted.
Cleared by software to disable transmit interrupt
requests.
INTERRUPT CONTROL REGISTER (ICR)
Read/Write
Reset Value: 00h
Bit 3 = SCIE Status Change Interrupt Enable
− Read/Set/Clear
7
0
0
Set by software to enable an interrupt request
whenever the node’s status changes in run mode or
whenever a dominant pulse is received in standby
mode.
0
ESCI RXIE TXIE SCIE ORIE TEIE
Bit 7 = Reserved.
Cleared by software to disable status change inter-
rupt requests.
Bit 6 = ESCI Extended Status Change Interrupt
− Read/Set/Clear
Bit 2 = ORIE Overrun Interrupt Enable
− Read/Set/Clear
Set by software to specify that SCIF is to be set on
receive errors also.
Set by software to enable an interrupt request
whenever a message should be stored and no re-
ceive buffer is avalaible.
Cleared by software to set SCIF only on status
changes and wake-up but not on all receive errors.
Bit 5 = RXIE Receive Interrupt Enable
− Read/Set/Clear
Cleared by software to disable overrun interrupt re-
quests.
Set by software to enable an interrupt request
whenever a message has been received free of er-
rors.
Bit 1 = TEIE Transmit Error Interrupt Enable
− Read/Set/Clear
Set by software to enable an interrupt whenever an
error has been detected during transmission of a
message.
Cleared by software to disable receive interrupt re-
quests.
Bit 4 = TXIE Transmit Interrupt Enable
− Read/Set/Clear
Cleared by software to disable transmit error inter-
rupts.
Set by software to enable an interrupt request
Bit 0 = Reserved.
137/215
ST72F521, ST72521B
CONTROLLER AREA NETWORK (Cont’d)
Bit 3 = NRTX No Retransmission
CONTROL/STATUS REGISTER (CSR)
Read/Write
− Read/Set/Clear
Set by software to disable the retransmission of un-
successfulmessages. Itdoesnotstoptransmission
in case of Arbitration Lost.
Reset Value: 00h
Cleared by software to enable retransmission of
messages until success is met.
7
0
0
BOFF EPSV SRTE NRTX FSYN WKPS RUN
Bit 2 = FSYN Fast Synchronization
− Read/Set/Clear
Set by software to enable a fast resynchronization
when leaving standby mode, i.e. wait for only 11 re-
cessive bits in a row.
Bit 6 = BOFF Bus-Off State
− Read Only
Set by hardware to indicate that the node is in bus-
off state, i.e. the Transmit Error Counter exceeds
255.
Cleared by software to enable the standard resyn-
chronization when leaving standby mode, i.e. wait
for 128 sequences of 11 recessive bits.
Reset by hardware to indicate that the node is in-
volved in bus activities.
Bit 1 = WKPS Wake-up Pulse
− Read/Set/Clear
Bit 5 = EPSV Error Passive State
− Read Only
Set by software to generate a dominant pulse when
leaving standby mode.
Set by hardware to indicate that the node is error
passive.
Cleared by software for no dominant wake-up
pulse.
Resetby hardwaretoindicatethatthenodeis either
error active (BOFF = 0) or bus-off.
Bit 0 = RUN CAN Enable
− Read/Set/Clear
Bit 4 = SRTE Simultaneous Receive/Transmit En-
able − Read/Set/Clear
Setbysoftwaretoleavestandbymodeafter128se-
quences of 11 recessive bits or just 11 recessive
bits if FSYN is set.
Set by software to enable simultaneous transmis-
sion and reception of a message passing the ac-
ceptance filtering. Allows to check the integrity of
the communication path.
Cleared by software to request a switch to the
standby or low-power mode as soon as any on-go-
ing transfer is complete. Read-back as 1 in the
meantimetoenablepropersignallingofthestandby
state. The CPU clock may therefore be safely
switched OFF whenever RUN is read as 0.
Reset by software to discard all messages trans-
mitted by the node. Allows remote and data frames
to share the same identifier.
138/215
ST72F521, ST72521B
CONTROLLER AREA NETWORK (Cont’d)
BAUD RATE PRESCALER REGISTER (BRPR)
Read/Write in Standby mode
Reset Value: 00h
BIT TIMING REGISTER (BTR)
Read/Write in Standby mode
Reset Value: 23h
7
0
7
0
RJW1 RJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0
0
BS22 BS21 BS20 BS13 BS12 BS11 BS10
RJW[1:0] determine the maximum number of time
quanta by which a bit period may be shortened or
lengthened to achieve resynchronization.
BS2[2:0] determine the length of Bit Segment 2.
= t * (BS2 + 1)
t
BS2
CAN
BS1[3:0] determine the length of Bit Segment 1.
= t * (BS1 + 1)
t
= t
* (RJW + 1)
RJW
CAN
t
BS1
CAN
BRP[5:0] determine the CAN system clock cycle
time or time quanta which is used to build up the in-
dividual bit timing.
Note: Writing to this register is allowed only in
Standby mode to prevent any accidental CAN pro-
tocol violation through programming errors.
t
= t
* (BRP + 1)
CAN
CPU
Where t
= time period of the CPU clock.
CPU
The resulting baud rate can be computed by the for-
mula:
PAGE SELECTION REGISTER (PSR)
Read/Write
Reset Value: 00h
7
0
0
1
BR = ---------------------------------------------------------------------------------------------------
PAGE PAGE PAGE
0
0
0
0
tCPU × (BRP + 1) × (BS1 + BS2 + 3)
2
1
0
PAGE[2:0] determine which buffer or filter page is
mapped at addresses 0010h to 001Fh.
Note: Writing to this register is allowed only in
Standby mode to prevent any accidental CAN pro-
tocol violation through programming errors.
PAGE2
PAGE1
PAGE0
Page Title
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Diagnosis
Buffer 1
Buffer 2
Buffer 3
Filters
Reserved
Reserved
Reserved
139/215
ST72F521, ST72521B
CONTROLLER AREA NETWORK (Cont’d)
10.8.4.2 Paged Registers
TRANSMIT ERROR COUNTER REG. (TECR)
Read Only
LAST IDENTIFIER HIGH REGISTER (LIDHR)
Read/Write
Reset Value: 00h
Reset Value: Undefined
7
0
7
0
TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0
LID10 LID9
LID8
LID7
LID6
LID5
LID4
LID3
TEC[7:0] is the least significant byte of the 9-bit
Transmit Error Counter implementing part of the
fault confinement mechanism of the CAN protocol.
In case of an error during transmission, this counter
is incremented by 8. It is decremented by 1 after
every successful transmission. When the counter
value exceeds 127, the CAN controller enters the
errorpassivestate. Whenavalueof256isreached,
the CAN controller is disconnected from the bus.
LID[10:3] are the most significant 8 bits of the last
Identifier read on the CAN bus.
LAST IDENTIFIER LOW REGISTER (LIDLR)
Read/Write
Reset Value: Undefined
7
0
RECEIVE ERROR COUNTER REG. (RECR)
Page: 00h — Read Only
LDLC LDLC LDLC LDLC
LID2
LID1
LID0 LRTR
Reset Value: 00h
3
2
1
0
7
0
LID[2:0] are the least significant 3 bits of the last
Identifier read on the CAN bus.
REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0
LRTR is the last Remote Transmission Request bit
read on the CAN bus.
REC[7:0] is the Receive Error Counter implement-
ing part of the fault confinement mechanism of the
CAN protocol. In case of an error during reception,
this counter is incremented by 1 or by 8 depending
on the error condition as defined by the CAN stand-
ard. After every successful reception the counter is
decremented by 1 or reset to 120 if its value was
higher than 128. When the counter value exceeds
127, the CAN controller enters the error passive
state.
LDLC[3:0] is the last Data Length Code read on the
CAN bus.
IDENTIFIER HIGH REGISTERS (IDHRx)
Read/Write
Reset Value: Undefined
7
0
ID10
ID9
ID8
ID7
ID6
ID5
ID4
ID3
ID[10:3] are the most significant 8 bits of the 11-bit
message identifier.The identifier acts as the mes-
sage’s name, used for bus access arbitration and
acceptance filtering.
140/215
ST72F521, ST72521B
CONTROLLER AREA NETWORK (Cont’d)
IDENTIFIER LOW REGISTERS (IDLRx)
Read/Write
BUFFER CONTROL/STATUS REGs. (BCSRx)
Read/Write
Reset Value: Undefined
Reset Value: 00h
7
0
7
0
0
ID2
ID1
ID0
RTR DLC3 DLC2 DLC1 DLC0
0
0
0
ACC
RDY BUSY LOCK
Bit 3 = ACC Acceptance Code
− Read Only
ID[2:0] are the least significant 3 bits of the 11-bit
message identifier.
Set by hardware with the id of the highest priority
filter which accepted the message stored in the
buffer.
RTR is the Remote Transmission Request bit. It is
set to indicate a remote frame and reset to indicate
a data frame.
ACC = 0: Match for Filter/Mask0. Possible match
for Filter/Mask1.
ACC = 1: No match for Filter/Mask0 and match for
Filter/Mask1.
DLC[3:0] is the Data Length Code. It gives the
number of bytes in the data field of the mes-
sage.The valid range is 0 to 8.
Reset by hardware when either RDY or RXIF gets
reset.
Bit 2 = RDY Message Ready
DATA REGISTERS (DATA0-7x)
Read/Write
− Read/Clear
Set by hardware to signal that a new error-free
message is available (LOCK = 0) or that a trans-
mission request is pending (LOCK = 1).
Cleared by software when LOCK = 0 to release
the buffer and to clear the corresponding RXIF bit
in the Interrupt Status Register.
Reset Value: Undefined
7
0
DATA DATA DATA DATA DATA DATA DATA DATA
7
6
5
4
3
2
1
0
Cleared by hardware when LOCK = 1 to indicate
that the transmission request has been serviced or
cancelled.
DATA[7:0]isamessagedatabyte.Uptoeightsuch
bytes may be part of a message. Writing to byte
DATA7 initiates a transmit request and should al-
ways be done even when DATA7 is not part of the
message.
Bit 1 = BUSY Busy Buffer
− Read Only
Set by hardware when the buffer is being filled
(LOCK = 0) or emptied (LOCK = 1) and reset after
the 2nd intermission bit.
Reset by hardware when the buffer is not ac-
cessed by the CAN core for transmission nor re-
ception purposes.
Bit 0 = LOCK Lock Buffer
− Read/Set/Clear
Set by software to lock a buffer. No more message
can be received into the buffer thus preserving its
content and making it available for transmission.
Cleared by software to make the buffer available
for reception. Cancels any pending transmission
request.
Cleared by hardware once a message has been
successfully transmitted provided the early trans-
mit interrupt mode is on. Left untouched otherwise.
Note that in order to prevent any message corrup-
tion or loss of context, LOCK cannot be set nor re-
set while BUSY is set. Trying to do so will result in
LOCK not changing state.
141/215
ST72F521, ST72521B
CONTROLLER AREA NETWORK (Cont’d)
FILTER HIGH REGISTERS (FHRx)
Read/Write
MASK HIGH REGISTERS (MHRx)
Read/Write
Reset Value: Undefined
Reset Value: Undefined
7
0
7
0
FIL11 FIL10 FIL9
FIL8
FIL7
FIL6
FIL5
FlL4
MSK1 MSK1
MSK9 MSK8 MSK7 MSK6 MSK5 MSK4
1
0
FIL[11:3] are the most significant 8 bits of a 12-bit
message filter. The acceptance filter is compared
bit by bit with the identifier and the RTR bit of the
incoming message. If there is a match for the set
of bits specified by the acceptance mask then the
message is stored in a receive buffer.
MSK[11:3] are the most significant 8 bits of a 12-
bit message mask. The acceptance mask defines
which bits of the acceptance filter should match
the identifier and the RTR bit of the incoming mes-
sage.
MSK = 0: don’t care.
i
MSK = 1: match required.
i
FILTER LOW REGISTERS (FLRx)
Read/Write
MASK LOW REGISTERS (MLRx)
Read/Write
Reset Value: Undefined
Reset Value: Undefined
7
0
0
7
0
0
FIL3
FIL2
FIL1
FIL0
0
0
0
MSK3 MSK2 MSK1 MSK0
0
0
0
FIL[3:0] are the least significant 4 bits of a 12-bit
message filter.
MSK[3:0] are the least significant 4 bits of a 12-bit
message mask.
142/215
ST72F521, ST72521B
CONTROLLER AREA NETWORK (Cont’d)
Figure 73. CAN Register Map
Interrupt Status
Interrupt Control
Control/Status
5Ah
5Bh
5Ch
5Dh
5Eh
5Fh
60h
Baud Rate Prescaler
Bit Timing
Page Selection
Paged Reg0
Paged Reg1
Paged Reg2
Paged Reg3
Paged Reg4
Paged Reg5
Paged Reg6
Paged Reg7
Paged Reg8
Paged Reg9
Paged Reg10
Paged Reg11
Paged Reg12
Paged Reg13
6Fh
Paged Reg14
Paged Reg15
143/215
ST72F521, ST72521B
CONTROLLER AREA NETWORK (Cont’d)
Figure 74. Page Maps
PAGE 0
PAGE 1
PAGE 2
PAGE 3
PAGE 4
60h
61h
62h
63h
64h
65h
66h
67h
68h
69h
6Ah
6Bh
6Ch
6Dh
6Eh
6Fh
LIDHR
LIDLR
IDHR1
IDLR1
IDHR2
IDLR2
IDHR3
IDLR3
FHR0
FLR0
MHR0
MLR0
FHR1
FLR1
MHR1
MLR1
DATA01
DATA11
DATA21
DATA31
DATA41
DATA51
DATA61
DATA71
DATA02
DATA12
DATA22
DATA32
DATA42
DATA52
DATA62
DATA72
DATA03
DATA13
DATA23
DATA33
DATA43
DATA53
DATA63
DATA73
Reserved
Reserved
Reserved
Reserved
Reserved
TECR
RECR
BCSR1
Buffer 1
BCSR2
Buffer 2
BCSR3
Buffer 3
Diagnosis
Acceptance Filters
144/215
ST72F521, ST72521B
CONTROLLER AREA NETWORK (Cont’d)
Table 24. CAN Register Map and Reset Values
Address
(Hex.)
Register
Label
Page
7
6
5
4
3
2
1
0
CANISR
Reset Value
RXIF3
0
RXIF2
0
RXIF1
0
TXIF
0
SCIF
0
ORIF
0
TEIF
0
EPND
0
5A
5B
5C
5D
5E
5F
CANICR
Reset Value
ESCI
0
RXIE
0
TXIE
0
SCIE
0
ORIE
0
TEIE
0
ETX
0
0
0
CANCSR
Reset Value
BOFF
0
EPSV
0
SRTE
0
NRTX
0
FSYN
0
WKPS
0
RUN
0
CANBRPR
Reset Value
RJW1
0
RJW0
0
BRP5
0
BRP4
0
BRP3
0
BRP2
0
BRP1
0
BRP0
0
CANBTR
Reset Value
BS22
0
BS21
1
BS20
0
BS13
0
BS12
0
BS11
1
BS10
1
0
0
CANPSR
Reset Value
PAGE2 PAGE1 PAGE0
0
0
0
0
0
0
0
CANLIDHR
Reset Value
LID10
x
LID9
x
LID8
x
LID7
x
LID6
x
LID5
x
LID4
x
LID3
x
0
1 to 3
4
60
CANIDHRx
Reset Value
ID10
x
ID9
x
ID8
x
ID7
x
ID6
x
ID5
x
ID4
x
ID3
x
CANFHRx
Reset Value
FIL11
x
FIL10
x
FIL9
x
FIL8
x
FIL7
x
FIL6
x
FIL5
x
FIL4
x
60, 64
61
CANLIDLR
Reset Value
LID2
x
LID1
x
LID0
x
LRTR LDLC3 LDLC2 LDLC1 LDLC0
0
x
x
x
x
x
CANIDLRx
Reset Value
ID2
x
ID1
x
ID0
x
RTR
x
DLC3
x
DLC2
x
DLC1
x
DLC0
x
1 to 3
4
CANFLRx
Reset Value
FIL3
x
FIL2
x
FIL1
x
FIL0
x
61, 65
0
0
0
0
CANDRx
Reset Value
MSB
x
LSB
x
62 to 69 1 to 3
x
x
x
x
x
x
CANMHRx
Reset Value
MSK11 MSK10
MSK9
x
MSK8
x
MSK7
x
MSK6
x
MSK5
x
MSK4
x
62, 66
63, 67
6E
4
4
0
x
x
CANMLRx
Reset Value
MSK3
x
MSK2
x
MSK1
x
MSK0
x
0
0
0
0
0
0
0
0
0
0
CANTECR
Reset Value
MSB
0
LSB
0
0
0
0
0
0
0
0
0
0
CANRECR
Reset Value
MSB
0
LSB
0
6F
CANBCSRx
Reset Value
ACC
0
RDY
0
BUSY
0
LOCK
0
1 to 3
0
145/215
ST72F521, ST72521B
CONTROLLER AREA NETWORK (Cont’d)
10.8.5 List of CAN Cell Limitations
10.8.5.1 Omitted SOF bit
For CAN transmitted messages the 2nd data byte
can be corrupted.
Details:
Symptom:
The CAN transmit and receive buffers are imple-
mented as dual ported RAM. During the reception
of a CAN frame the CAN core writes the received
identifier and the data byte-by-byte in the corre-
sponding buffer.
Start of Frame (SOF) bit is omitted if transmission
is requested in the last Intermission bit.
Test Case:
5.3.1 10-Kbit Stress Test
Details:
IF the CAN bit timing configuration is t
quanta
< 5 time
BS2
The IUT is requested to start transmission immedi-
ately after the completion of the previous transmis-
sion. The LT also starts its transmission and as-
AND
IF concurrently with the pCAN, the CPU executes
a write access to the dual ported RAM using an in-
struction with more than one cycle access, e.g.
CLR, BSET, BRES
THEN the access conflict can lead to the corrup-
tion described in the symptoms paragraph above.
rd
serts the SOF bit just after the 3 Intermission bit.
The IUT also starts transmission but omits the
SOF bit. The IUT wins the arbitration and contin-
ues the transmission. The frame is sent correctly.
Impact On The Application:
Impact On The Application:
As this effect only occurs when the IUT detects a
SOF bit on the CAN bus, the fact that it omits its
own SOF bit has no impact on the communication.
Several CAN frames with erroneous data or iden-
tifier will be received/transmitted.
Software Workaround:
10.8.5.2 CAN: CPU Write Access (More Than
One Cycle) Corrupts CAN Frame
Program t
> 4 time quanta or, when accessing
BS2
the receive or transmit buffers, do not use the crit-
ical instructions which are:
Symptoms:
For CAN received messages the identifier high
byte or last data byte can be corrupted.
BSET, BRES, CLR, CPL, DEC, INC, NEG, RLC,
SLL, SRL, RRC, SRA, SWAP.
146/215
ST72F521, ST72521B
CONTROLLER AREA NETWORK (Cont’d)
10.8.5.3 Unexpected message transmission
Symptom:
cation might need to abort this transmission re-
quest. To do so, the application can reset the
LOCK bit in the BCSR register.
The previous message received by pCAN, even if
this message did not pass the receive filter, will be
retransmitted by pCAN with a correct identifier and
DLC but with corrupted data. The data bytes will
be a copy of the identifier bytes IDHR and IDLR in
the following repetitive pattern:
DATA_0 = IDHR
DATA_1 = IDLR
DATA_2 = IDHR
DATA_3 = IDLR
etc.
If the message is pending (RDY bit set) but not
currently being transmitted, then clearing the
LOCK bit will abort it immediately.
If the message is pending (RDY bit set) and cur-
rently being transmitted then the message will not
be interrupted but the CAN core will wait until the
end of this transmission attempt. Then software
must clear the LOCK bit again to abort the trans-
mission.
An unexpected transmission can occur:
IF the application resets the LOCK bit
DATA_7 = IDLR
If no message has been received before the prob-
lem occurs then identifier byte values are random
but the data bytes are in the same repetitive pat-
tern.
WHILE the CAN core is preparing the
transmission AND there is no other transmission
pending in another buffer
1)
THEN the LOCK bit is reset but the transmission is
not stopped. Instead the content of the page 0
buffer will be transmitted.
Details:
The buffers of the pCAN cell are configurable as
receive or transmit buffers. By default, all buffers
are configured in reception. To use a buffer to
transmit a CAN message the application has to re-
serve this buffer for transmission by setting the
LOCK bit in the BCSR register. So the buffer is
then locked for any further reception and reserved
for transmission.
Impact On The Application:
pCAN will echo some messages sent by other
nodes. Identifier and DLC will be correct but data
are corrupted as described previously.
Note 1: The preparation lasts two bit times just be-
fore SOF, this is the critical window during which
the LOCK bit must not be reset by the application.
Once a transmission has been requested by a
write access to data byte 7 of the buffer the appli-
147/215
ST72F521, ST72521B
CONTROLLER AREA NETWORK (Cont’d)
Software Work-around - Devices with Hard-
ware Fix (ST72F521 rev “R”):
To abort the transmission, first the application sets
the WKPS bit and polls it until it is set. The maxi-
mum time needed to set this bit is two CAN bit
times. Once the application has read the WKPS bit
as one, it can reset the LOCK bit to stop the cur-
rent transmission.
To implement a transmission abort under safe
conditions, the LOCK bit must not be reset during
the critical window (2 bit times). A new function
has been implemented in the MCU allowing the
application to synchronize the reset of the LOCK
bit (abort request) with the reset of the TXRQST bit
(internal signal) in the pCAN core.
The abort is completed when the LOCK bit is read
back as zero by the application. Once the abort
has been completed, the application must reset
the WKPS bit to be able to transmit again. Of
course the transmit buffer must be in LOCK state
as usual before any transmission attempt.
The synchronization is done using the WKPS bit in
the CANCSR register, the function of this bit has
been modified and no more Wake-up Pulse (dom-
inant bit) is sent on the CAN_TX signal when the
WKPS bit is set. This means the functionality de-
scribed in the datasheet is no longer applicable
(see Section 10.8.5.4).
The “C” code sequence below shows the software
work-around using the WKPS bit.
CANCSR |= WKPS;
// Set WKPS bit
while(!(CANCSR & WKPS) );// Wait until WKPS bit is set
while( CANBCSR & LOCK )// Wait until abort has been confirmed
{
CANBCSR &= ~LOCK;
}
CANCSR &= ~WKPS;
CANBCSR |= LOCK;
// Allow transmission again
//Alloc buffer for next transmission
148/215
ST72F521, ST72521B
CONTROLLER AREA NETWORK (Cont’d)
Software Work-around - Devices without Hard-
ware Fix:
Abort while staying in RUN mode (RUN=1)
Contrary to the STANDBY case described previ-
ously, in the RUN case the application has to han-
dle the error or arbitration lost conditions. In case
of transmission errors, causing the frame to be
transmitted again and again, the application must
set the NRTX bit in the CSR register. This will
cause pCAN to abort the transmission at the end
of the current attempt.
To implement a transmission abort under safe
conditions, any reset of the LOCK bit during the
critical window (2 bit times) must be avoided. Two
different cases have to be considered, either the
pCAN enters standby mode after the abort, or the
abort is performed and pCAN keeps running.
In case of arbitration lost, setting the NRTX bit
does not abort the transmission, therefore the ap-
plication must reset the LOCK bit to abort the
transmission. To avoid resetting the LOCK bit dur-
ing the critical time window, leading to the problem
described at the start of this section, the applica-
tion must monitor the BUSY bit in the BCSR regis-
ter and reset the LOCK bit just after the falling
edge of the BUSY bit. The time between the falling
edge of the BUSY bit and the SOF of the next
transmission attempt is in any case long enough to
guarantee that the LOCK bit is reset before the
critical time window.
Abort followed by STANDBY mode (RUN=0)
In this case, aborting the pending transmissions
can safely be done by first entering STANDBY
mode and then releasing the transmit buffers.
STANDBY mode is entered by resetting the RUN
bit in the CSR register and once the current trans-
mission attempt, even if it fails due to error or lost
arbitration, has been performed, pCAN enters
STANDBY mode (RUN=0). Once in STANDBY
mode the application can abort all pending trans-
missions by resetting the corresponding LOCK bit.
The “C” code sequence below shows the software
work-around for both the error and arbitration lost
cases.
_asm("SIM\n");
CANCSR |= NRTX;
// Mask interrupts
// Set non automatic retransmission bit
while(!(CANBCSR & BUSY) &&// Wait till BUSY bit is set
(CANBCSR & RDY) ); // or transmission done
while( CANBCSR & BUSY ); // Wait till BUSY bit is reset (falling edge)
if( CANBCSR & RDY )
{ // transmission still pending -> must be aborted
CANBCSR &= ~LOCK; //Arbitration lost => cancel transmission safel
while( CANBCSR & RDY );// Wait for unlock confirmed
CANCSR &= ~NRTX;// Reset NRTX bit once abort sequence done
_asm("RIM\n");
}
else
{ // No more abort required as RDY bit already reset
CANCSR &= ~NRTX;// Reset NRTX bit once abort sequence done
_asm("RIM\n"); // Enable interrupts
}
149/215
ST72F521, ST72521B
Figure 75. Work-around Flowchart
Application Requests
an Abort
YES
NO
READY == 1
MASK INT
SET NRTX
BUSY == 0
AND
YES
NO
READY == 1
YES
NO
BUSY == 0
NO
YES
READY == 1
RESET LOCK
NO
YES
READY == 1
RESET NRTX
ENABLE INT
Abort Done
SET LOCK
150/215
ST72F521, ST72521B
CONTROLLER AREA NETWORK (Cont’d)
The figures below show the abort behaviour in the
four possible cases.
the error (the first attempt). The abort has been
successful and the transmit buffer is empty.
Figure 76. Abort and successful transmission
Figure 79. Abort and arbitration lost
TX RQST
TX RQST
ABORT RQST
ABORT RQST
CAN TX
CAN RX
LOCK
CAN TX
CAN RX
LOCK
READY
BUSY
READY
BUSY
NRTX
NRTX
In this case the NRTX bit is set but has no effect,
as the previous transmission attempt failed due to
an arbitration lost. The application waits for the
falling edge of BUSY bit and checks that READY is
still set. This is the case, this means pCAN has lost
the arbitration and LOCK bit can be safely reset.
Abort is immediate and pCAN resets the READY
and BUSY bits.
In this case the abort request performed during the
transmission has no effect, as the first transmis-
sion is successful.
Figure 77. Abort and transmission delayed by
busy CAN bus
TX RQST
ABORT RQST
Timing Considerations
As no interrupt signals that an abort has been suc-
cessful, the application has to wait until the trans-
mit buffer is empty (transmission has been aborted
or transmitted successfully). This time can vary
depending on the case in which the abort is per-
formed (arbitration lost, error or successful trans-
mission). To show the impact of the software work-
around on this timing behaviour Figure 80 and Fig-
ure 81 compare the reference behaviour (worst
case when abort is done by LOCK only) with the
behaviour when NRTX, BUSY and LOCK bits are
used.
CAN TX
CAN RX
LOCK
READY
BUSY
NRTX
In this case the NRTX bit is set to abort the trans-
mission after the first attempt. As the first attempt
is successful the READY and BUSY bits are reset
by pCAN and the transmit buffer becomes empty.
An abort is no longer required.
Figure 78. Abort and error during transmission
Figure 80. Abort by LOCK only - Reference
behaviour
Error
TX RQST
ABORT RQST
TX RQST
CAN TX
CAN RX
LOCK
ABORT RQST
CAN TX
CAN RX
LOCK
READY
BUSY
READY
BUSY
NRTX
NRTX
In this case NRTX (abort request) is set before the
error, thus pCAN resets READY and BUSY after
151/215
ST72F521, ST72521B
CONTROLLER AREA NETWORK (Cont’d)
The worst case is when the abort request is done
when the transmission has just started. In this
case the LOCK bit cannot be reset as long as the
BUSY bit is set, this means until the end of the
frame. So the application will wait for READY to be
reset during the whole frame and in this case the
worst case will be the longest frame the applica-
tion is expected to transmit.
reset. If the next arbitration is won by pCAN then
the BUSY bit will be reset by the end of the suc-
cessful transmission. The longest time the applica-
tion has to wait in this case is the time of the long-
est message expected on the bus (minus identifi-
er) plus the longest message expected to be trans-
mitted by the application. This roughly double the
time the application may have to wait before the
abort sequence is performed.
Figure 81. Abort with the software work-around
- by NRTX, BUSY and LOCK
10.8.5.4 WKPS Functionality
Due to a fix implemented to solve the “Unexpected
Message Transmission” issue (see Section
10.8.5.3) the WKPS functionality has been modi-
fied as follows in Flash ST72F521 devices:
TX RQST
ABORT RQST
CAN TX
CAN RX
LOCK
Device
Modification
READY
BUSY
WKPS bit does not generate a wakeup
pulse. It is used to synchronize the re-
set of the LOCK bit (see “Software
Work-around - Devices with Hardware
Fix (ST72F521 rev “R”):” on page 148)
Flash
ST72F521
Rev R
NRTX
Using the software work-around the worst case
occurs in the arbitration lost case. If the abort is re-
quested just after pCAN has lost the arbitration
then the application has to wait for the next falling
edge of the BUSY bit before the LOCK bit can be
ROM
ST72521 All
revisions
WKPS bit functions according to the
datasheet description.
152/215
ST72F521, ST72521B
CONTROLLER AREA NETWORK (Cont’d)
10.8.5.5 Bus-off state not entered
Symptom:
ue lower than 128, this is the case with any correct
reception even if the message is filtered out.
As bus-off state is not entered and pCAN still at-
tempts to transmit its message, after the overflow
the TEC register continues to increment as long as
transmission errors occur.
pCAN does not enter bus-off state under certain
conditions. This is fixed in FLASH version of
ST72F521 starting from silicon Rev R and in ROM
version ST72521B starting from silicon Rev Y.
Impact on the application:
Details:
The application will not stop attempting to transmit
CAN messages, even when the bus-off conditions
have been reached, until the transmission has
been successful or the value of REC becomes
lower than 128. However the application will not
disturb the communication of the other nodes on
the CAN network as pCAN is in Error Passive
State.
According to the CAN standard, pCAN is expected
to enter bus-off state when TEC (Transmit Error
Counter) is greater than 255.
But if REC (Receive Error Counter) is greater than
127 (Error Passive State) pCAN does not enter
bus-off and the BOFF bit of the CSR register is not
set. To enter bus-off, REC must decrease to a val-
Figure 82. CAN Error State Diagram showing “BUSOFF not entered” limitation
When TECR or RECR > 127, the EPSV bit gets set
ERROR ACTIVE
ERROR PASSIVE
When TECR and RECR < 128,
the EPSV bit gets cleared
When 128 * 11 recessive bits occur:
- the BOFF bit gets cleared
When TECR > 255 and RECR < 128 the BOFF bit
gets set and the EPSV bit gets cleared
- the TECR register gets cleared
- the RECR register gets cleared
BUS OFF
153/215
ST72F521, ST72521B
CONTROLLER AREA NETWORK (Cont’d)
Workaround Description
to reach 256 the sequence must be executed 32
times. Under these conditions the shortest se-
quence leading to a TEC overflow lasts 832 bit
times.
The bus-off entry works correctly in almost all cas-
es, only when REC is greater than 127 a bus-off
will not be recognized by pCAN. Therefore the
pCAN bus-off signalling (BOFF) is still used but it
needs to be complemented by monitoring TEC by
software.
Depending on the baudrate the application will
have to adapt the monitoring period, for example
at 500kbps the period must be less than 1600us.
To detect the bus-off condition by software the ap-
plication has to monitor the value of the TEC reg-
ister periodically. An overflow signals a bus-off
condition. When a bus-off condition has been de-
tected the application must execute the following
sequence to recover from bus-off properly: the ap-
plication stops pCAN by clearing the RUN bit in the
CANCSR register resets all pending transmission
by clearing the LOCK bit in the BCSR register and
starts it again by setting the RUN bit.
The ‘C’ code below shows an implementation ex-
ample of the monitoring sequence. This code is
called periodically as described above.
To detect the overflow, the test condition must
take into account that TEC might also have been
decremented due to a successful transmission. So
an overflow condition is detected:
IF the current TEC value is lower than the previous
TEC value
AND the difference is greater than the number of
possible successful transmissions during the mon-
itoring period.
To detect the bus-off condition properly, the TEC
monitoring period must be lower than the time be-
tween two overflows. As the problem only occurs
when pCAN is in Error Passive State (REC > 127)
pCAN will continuously try to send a SOF followed
by an Error Passive Flag and a Suspend Trans-
mission. This leads to 26 (1 + 6 + 8 + 3 + 8) bit
times. Each time TEC is incremented by 8, hence
In the example above, one message can be sent,
therefore one is added to CANTECR.
************************************************/
/* INITIALISATION
/************************************************/
unsigned char TECReg=0; //Previous value of TEC
unsigned char BusOffFlag=0; //Set to one if bus-off
/************************************************/
/* BUS-OFF MONITORING SEQUENCE
/************************************************/
if( (CANCSR & BOFF) || ( CANTECR+1 < TECReg) )
{
BusOffFlag = 1;
}
else
{
TECReg = CANTECR;
}
154/215
ST72F521, ST72521B
10.9 10-BIT A/D CONVERTER (ADC)
10.9.1 Introduction
10.9.2 Main Features
■ 10-bit conversion
■ Up to 16 channels with multiplexed input
■ Linear successive approximation
■ Data register (DR) which contains the results
■ Conversion complete status flag
■ On/off bit (to reduce consumption)
The block diagram is shown in Figure 83.
The on-chip Analog to Digital Converter (ADC) pe-
ripheral is a 10-bit, successive approximation con-
verter with internal sample and hold circuitry. This
peripheral has up to 16 multiplexed analog input
channels (refer to device pin out description) that
allow the peripheral to convert the analog voltage
levels from up to 16 different sources.
The result of the conversion is stored in a 10-bit
Data Register. The A/D converter is controlled
through a Control/Status Register.
Figure 83. ADC Block Diagram
f
CPU
DIV 4
DIV 2
0
1
f
ADC
CH3
EOC SPEEDADON
0
CH2 CH1 CH0
ADCCSR
4
AIN0
AIN1
ANALOG TO DIGITAL
CONVERTER
ANALOG
MUX
AINx
ADCDRH
D9 D8 D7 D6 D5 D4
D3
D2
ADCDRL
0
0
0
0
0
0
D1
D0
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ST72F521, ST72521B
10-BIT A/D CONVERTER (ADC) (Cont’d)
10.9.3 Functional Description
The conversion is monotonic, meaning that the re-
sult never decreases if the analog input does not
and never increases if the analog input does not.
To read the 10 bits, perform the following steps:
1. Poll the EOC bit
2. Read the ADCDRL register
If the input voltage (V ) is greater than V
AIN
AREF
3. Read the ADCDRH register. This clears EOC
automatically.
(high-level voltage reference) then the conversion
result is FFh in the ADCDRH register and 03h in
the ADCDRL register (without overflow indication).
Note: The data is not latched, so both the low and
the high data register must be read before the next
conversion is complete, so it is recommended to
disable interrupts while reading the conversion re-
sult.
If the input voltage (V ) is lower than V
(low-
SSA
AIN
level voltage reference) then the conversion result
in the ADCDRH and ADCDRL registers is 00 00h.
The A/D converter is linear and the digital result of
the conversion is stored in the ADCDRH and AD-
CDRL registers. The accuracy of the conversion is
described in the Electrical Characteristics Section.
To read only 8 bits, perform the following steps:
1. Poll the EOC bit
2. Read the ADCDRH register. This clears EOC
automatically.
R
is the maximum recommended impedance
AIN
for an analog input signal. If the impedance is too
high, this will result in a loss of accuracy due to
leakage and sampling not being completed in the
alloted time.
10.9.3.3 Changing the conversion channel
The application can change channels during con-
version. When software modifies the CH[3:0] bits
in the ADCCSR register, the current conversion is
stopped, the EOC bit is cleared, and the A/D con-
verter starts converting the newly selected chan-
nel.
10.9.3.1 A/D Converter Configuration
The analog input ports must be configured as in-
put, no pull-up, no interrupt. Refer to the «I/O
ports» chapter. Using these pins as analog inputs
does not affect the ability of the port to be read as
a logic input.
10.9.4 Low Power Modes
Note: The A/D converter may be disabled by re-
setting the ADON bit. This feature allows reduced
power consumption when no conversion is need-
ed and between single shot conversions.
In the ADCCSR register:
– Select the CS[3:0] bits to assign the analog
channel to convert.
10.9.3.2 Starting the Conversion
Mode
Description
WAIT
No effect on A/D Converter
A/D Converter disabled.
In the ADCCSR register:
– Set the ADON bit to enable the A/D converter
and to start the conversion. From this time on,
the ADC performs a continuous conversion of
the selected channel.
After wakeup from Halt mode, the A/D
Converter requires a stabilization time
HALT
t
(see Electrical Characteristics)
STAB
before accurate conversions can be
performed.
When a conversion is complete:
– The EOC bit is set by hardware.
– The result is in the ADCDR registers.
A read to the ADCDRH resets the EOC bit.
10.9.5 Interrupts
None.
156/215
ST72F521, ST72521B
10-BIT A/D CONVERTER (ADC) (Cont’d)
10.9.6 Register Description
CONTROL/STATUS REGISTER (ADCCSR)
Read/Write (Except bit 7 read only)
Reset Value: 0000 0000 (00h)
Bit 3:0 = CH[3:0] Channel Selection
These bits are set and cleared by software. They
select the analog input to convert.
Channel Pin*
CH3 CH2 CH1 CH0
7
0
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
EOC SPEED ADON
0
CH3
CH2
CH1
CH0
Bit 7 = EOC End of Conversion
This bit is set by hardware. It is cleared by hard-
ware when software reads the ADCDRH register
or writes to any bit of the ADCCSR register.
0: Conversion is not complete
1: Conversion complete
AIN9
AIN10
AIN11
AIN12
AIN13
AIN14
AIN15
Bit 6 = SPEED ADC clock selection
This bit is set and cleared by software.
0: f
1: f
= f
= f
/4
/2
ADC
ADC
CPU
CPU
*The number of channels is device dependent. Refer to
the device pinout description.
Bit 5 = ADON A/D Converter on
This bit is set and cleared by software.
0: Disable ADC and stop conversion
1: Enable ADC and start conversion
DATA REGISTER (ADCDRH)
Read Only
Bit 4 = Reserved. Must be kept cleared.
Reset Value: 0000 0000 (00h)
7
0
D9
D8
D7
D6
D5
D4
D3
D2
Bit 7:0 = D[9:2] MSB of Converted Analog Value
DATA REGISTER (ADCDRL)
Read Only
Reset Value: 0000 0000 (00h)
7
0
0
0
0
0
0
0
D1
D0
Bit 7:2 = Reserved. Forced by hardware to 0.
Bit 1:0 = D[1:0] LSB of Converted Analog Value
157/215
ST72F521, ST72521B
10-BIT A/D CONVERTER (Cont’d)
Table 25. ADC Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
ADCCSR
Reset Value
EOC
0
SPEED
0
ADON
0
CH3
0
CH2
0
CH1
0
CH0
0
0070h
0071h
0072h
0
ADCDRH
Reset Value
D9
0
D8
0
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
ADCDRL
Reset Value
D1
0
D0
0
0
0
0
0
0
0
158/215
ST72F521, ST72521B
11 INSTRUCTION SET
11.1 CPU ADDRESSING MODES
so, most of the addressing modes may be subdi-
vided in two sub-modes called long and short:
The CPU features 17 different addressing modes
which can be classified in 7 main groups:
– Long addressing mode is more powerful be-
cause it can use the full 64 Kbyte address space,
however it uses more bytes and more CPU cy-
cles.
Addressing Mode
Inherent
Example
nop
– Short addressing mode is less powerful because
it can generally only access page zero (0000h -
00FFh range), but the instruction size is more
compact, and faster. All memory to memory in-
structions use short addressing modes only
(CLR, CPL, NEG, BSET, BRES, BTJT, BTJF,
INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP)
Immediate
Direct
ld A,#$55
ld A,$55
ld A,($55,X)
ld A,([$55],X)
jrne loop
Indexed
Indirect
Relative
Bit operation
bset byte,#5
The ST7 Assembler optimizes the use of long and
short addressing modes.
The CPU Instruction set is designed to minimize
the number of bytes required per instruction: To do
Table 26. CPU Addressing Mode Overview
Pointer
Address
(Hex.)
Pointer Size
(Hex.)
Length
(Bytes)
Mode
Syntax
Destination
Inherent
Immediate
Short
Long
nop
+ 0
ld A,#$55
+ 1
+ 1
+ 2
+ 0
+ 1
+ 2
+ 2
+ 2
+ 2
+ 2
+ 1
+ 2
+ 1
+ 2
+ 2
+ 3
Direct
Direct
Direct
Direct
Direct
Indirect
Indirect
ld A,$10
00..FF
ld A,$1000
ld A,(X)
0000..FFFF
00..FF
No Offset
Short
Long
Indexed
Indexed
Indexed
ld A,($10,X)
ld A,($1000,X)
ld A,[$10]
00..1FE
0000..FFFF
00..FF
Short
Long
00..FF
byte
word
byte
word
ld A,[$10.w]
ld A,([$10],X)
ld A,([$10.w],X)
jrne loop
0000..FFFF 00..FF
00..1FE 00..FF
Short
Long
Indirect Indexed
Indirect Indexed
Direct
0000..FFFF 00..FF
PC+/-127
Relative
Relative
Bit
Indirect
jrne [$10]
PC+/-127
00..FF
00..FF
00..FF
00..FF
00..FF
00..FF
00..FF
byte
byte
byte
Direct
bset $10,#7
bset [$10],#7
Bit
Indirect
Bit
Direct
Relative btjt $10,#7,skip
Bit
Indirect Relative btjt [$10],#7,skip
159/215
ST72F521, ST72521B
INSTRUCTION SET OVERVIEW (Cont’d)
11.1.1 Inherent
11.1.3 Direct
All Inherent instructions consist of a single byte.
The opcode fully specifies all the required informa-
tion for the CPU to process the operation.
In Direct instructions, the operands are referenced
by their memory address.
The direct addressing mode consists of two sub-
modes:
Inherent Instruction
Function
No operation
Direct (short)
NOP
The address is a byte, thus requires only one byte
after the opcode, but only allows 00 - FF address-
ing space.
TRAP
S/W Interrupt
Wait For Interrupt (Low Pow-
er Mode)
WFI
Direct (long)
Halt Oscillator (Lowest Power
Mode)
HALT
The address is a word, thus allowing 64 Kbyte ad-
dressing space, but requires 2 bytes after the op-
code.
RET
Sub-routine Return
Interrupt Sub-routine Return
Set Interrupt Mask (level 3)
Reset Interrupt Mask (level 0)
Set Carry Flag
IRET
SIM
11.1.4 Indexed (No Offset, Short, Long)
RIM
In this mode, the operand is referenced by its
memory address, which is defined by the unsigned
addition of an index register (X or Y) with an offset.
SCF
RCF
Reset Carry Flag
RSP
Reset Stack Pointer
Load
The indirect addressing mode consists of three
sub-modes:
LD
CLR
Clear
Indexed (No Offset)
PUSH/POP
INC/DEC
TNZ
Push/Pop to/from the stack
Increment/Decrement
Test Negative or Zero
1 or 2 Complement
Byte Multiplication
There is no offset, (no extra byte after the opcode),
and allows 00 - FF addressing space.
Indexed (Short)
CPL, NEG
MUL
The offset is a byte, thus requires only one byte af-
ter the opcode and allows 00 - 1FE addressing
space.
SLL, SRL, SRA, RLC,
RRC
Shift and Rotate Operations
Swap Nibbles
Indexed (long)
SWAP
The offset is a word, thus allowing 64 Kbyte ad-
dressing space and requires 2 bytes after the op-
code.
11.1.2 Immediate
Immediate instructions have two bytes, the first
byte contains the opcode, the second byte con-
tains the operand value.
11.1.5 Indirect (Short, Long)
The required data byte to do the operation is found
by its memory address, located in memory (point-
er).
Immediate Instruction
Function
LD
Load
The pointer address follows the opcode. The indi-
rect addressing mode consists of two sub-modes:
CP
Compare
BCP
Bit Compare
Indirect (short)
AND, OR, XOR
ADC, ADD, SUB, SBC
Logical Operations
Arithmetic Operations
The pointer address is a byte, the pointer size is a
byte, thus allowing 00 - FF addressing space, and
requires 1 byte after the opcode.
Indirect (long)
The pointer address is a byte, the pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.
160/215
ST72F521, ST72521B
INSTRUCTION SET OVERVIEW (Cont’d)
11.1.6 Indirect Indexed (Short, Long)
11.1.7 Relative mode (Direct, Indirect)
This is a combination of indirect and short indexed
addressing modes. The operand is referenced by
its memory address, which is defined by the un-
signed addition of an index register value (X or Y)
with a pointer value located in memory. The point-
er address follows the opcode.
This addressing mode is used to modify the PC
register value, by adding an 8-bit signed offset to
it.
Available Relative
Direct/Indirect
Instructions
Function
The indirect indexed addressing mode consists of
two sub-modes:
JRxx
CALLR
Conditional Jump
Call Relative
Indirect Indexed (Short)
The pointer address is a byte, the pointer size is a
byte, thus allowing 00 - 1FE addressing space,
and requires 1 byte after the opcode.
The relative addressing mode consists of two sub-
modes:
Relative (Direct)
Indirect Indexed (Long)
The offset is following the opcode.
Relative (Indirect)
The pointer address is a byte, the pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.
The offset is defined in memory, which address
follows the opcode.
Table 27. Instructions Supporting Direct,
Indexed, Indirect and Indirect Indexed
Addressing Modes
Long and Short
Function
Instructions
LD
Load
CP
Compare
AND, OR, XOR
Logical Operations
Arithmetic Additions/Sub-
stractions operations
ADC, ADD, SUB, SBC
BCP
Bit Compare
Short Instructions
Only
Function
CLR
Clear
INC, DEC
TNZ
Increment/Decrement
Test Negative or Zero
1 or 2 Complement
Bit Operations
CPL, NEG
BSET, BRES
Bit Test and Jump Opera-
tions
BTJT, BTJF
SLL, SRL, SRA, RLC,
RRC
Shift and Rotate Opera-
tions
SWAP
Swap Nibbles
CALL, JP
Call or Jump subroutine
161/215
ST72F521, ST72521B
INSTRUCTION SET OVERVIEW (Cont’d)
11.2 INSTRUCTION GROUPS
The ST7 family devices use an Instruction Set
consisting of 63 instructions. The instructions may
be subdivided into 13 main groups as illustrated in
the following table:
Load and Transfer
LD
CLR
POP
DEC
TNZ
OR
Stack operation
PUSH
INC
RSP
BCP
Increment/Decrement
Compare and Tests
Logical operations
CP
AND
BSET
BTJT
ADC
SLL
XOR
CPL
NEG
Bit Operation
BRES
BTJF
ADD
SRL
JRT
Conditional Bit Test and Branch
Arithmetic operations
Shift and Rotates
SUB
SRA
JRF
SBC
RLC
JP
MUL
RRC
CALL
SWAP
CALLR
SLA
Unconditional Jump or Call
Conditional Branch
JRA
JRxx
TRAP
SIM
NOP
RET
Interruption management
Condition Code Flag modification
WFI
RIM
HALT
SCF
IRET
RCF
Using a pre-byte
The instructions are described with one to four op-
codes.
These prebytes enable instruction in Y as well as
indirect addressing modes to be implemented.
They precede the opcode of the instruction in X or
the instruction using direct addressing mode. The
prebytes are:
In order to extend the number of available op-
codes for an 8-bit CPU (256 opcodes), three differ-
ent prebyte opcodes are defined. These prebytes
modify the meaning of the instruction they pre-
cede.
PDY 90
Replace an X based instruction
using immediate, direct, indexed, or inherent ad-
dressing mode by a Y one.
The whole instruction becomes:
PIX 92
Replace an instruction using di-
PC-2
PC-1
PC
End of previous instruction
Prebyte
rect, direct bit, or direct relative addressing mode
to an instruction using the corresponding indirect
addressing mode.
opcode
It also changes an instruction using X indexed ad-
dressing mode to an instruction using indirect X in-
dexed addressing mode.
PC+1
Additional word (0 to 2) according
to the number of bytes required to compute the ef-
fective address
PIY 91
Replace an instruction using X in-
direct indexed addressing mode by a Y one.
162/215
ST72F521, ST72521B
INSTRUCTION SET OVERVIEW (Cont’d)
Mnemo
ADC
ADD
AND
BCP
Description
Add with Carry
Function/Example
A = A + M + C
A = A + M
Dst
Src
I1
H
H
H
I0
N
N
N
N
N
Z
Z
Z
Z
Z
C
C
C
A
M
Addition
A
M
M
M
Logical And
A = A . M
A
Bit compare A, Memory
Bit Reset
tst (A . M)
A
BRES
BSET
BTJF
BTJT
CALL
CALLR
CLR
bres Byte, #3
bset Byte, #3
btjf Byte, #3, Jmp1
btjt Byte, #3, Jmp1
M
M
M
M
Bit Set
Jump if bit is false (0)
Jump if bit is true (1)
Call subroutine
Call subroutine relative
Clear
C
C
reg, M
reg
0
N
N
N
1
Z
Z
Z
CP
Arithmetic Compare
One Complement
Decrement
tst(Reg - M)
A = FFH-A
dec Y
M
C
1
CPL
reg, M
reg, M
DEC
HALT
IRET
INC
Halt
1
0
Interrupt routine return
Increment
Pop CC, A, X, PC
inc X
I1
H
I0
N
N
Z
Z
C
reg, M
JP
Absolute Jump
Jump relative always
Jump relative
jp [TBL.w]
JRA
JRT
JRF
Never jump
jrf *
JRIH
JRIL
Jump if ext. INT pin = 1
Jump if ext. INT pin = 0
Jump if H = 1
(ext. INT pin high)
(ext. INT pin low)
H = 1 ?
JRH
JRNH
JRM
Jump if H = 0
H = 0 ?
Jump if I1:0 = 11
Jump if I1:0 <> 11
Jump if N = 1 (minus)
Jump if N = 0 (plus)
Jump if Z = 1 (equal)
I1:0 = 11 ?
I1:0 <> 11 ?
N = 1 ?
JRNM
JRMI
JRPL
JREQ
JRNE
JRC
N = 0 ?
Z = 1 ?
Jump if Z = 0 (not equal) Z = 0 ?
Jump if C = 1
Jump if C = 0
Jump if C = 1
C = 1 ?
JRNC
JRULT
C = 0 ?
Unsigned <
Jmp if unsigned >=
Unsigned >
JRUGE Jump if C = 0
JRUGT Jump if (C + Z = 0)
163/215
ST72F521, ST72521B
INSTRUCTION SET OVERVIEW (Cont’d)
Mnemo
JRULE
LD
Description
Jump if (C + Z = 1)
Load
Function/Example
Unsigned <=
dst <= src
Dst
Src
I1
H
I0
N
N
N
N
N
Z
Z
Z
Z
Z
C
reg, M
A, X, Y
reg, M
M, reg
X, Y, A
MUL
NEG
NOP
OR
Multiply
X,A = X * A
neg $10
0
0
Negate (2's compl)
No Operation
OR operation
C
A = A + M
pop reg
pop CC
push Y
C = 0
A
M
reg
CC
M
M
POP
Pop from the Stack
M
I1
1
H
I0
0
C
0
PUSH
RCF
RET
RIM
Push onto the Stack
Reset carry flag
Subroutine Return
Enable Interrupts
Rotate left true C
Rotate right true C
Reset Stack Pointer
Substract with Carry
Set carry flag
reg, CC
I1:0 = 10 (level 0)
C <= A <= C
C => A => C
S = Max allowed
A = A - M - C
C = 1
RLC
RRC
RSP
SBC
SCF
SIM
reg, M
reg, M
N
N
Z
Z
C
C
A
M
N
Z
C
1
Disable Interrupts
Shift left Arithmetic
Shift left Logic
I1:0 = 11 (level 3)
C <= A <= 0
C <= A <= 0
0 => A => C
A7 => A => C
A = A - M
1
1
SLA
reg, M
reg, M
reg, M
reg, M
A
N
N
0
Z
Z
Z
Z
Z
Z
Z
C
C
C
C
C
SLL
SRL
SRA
SUB
SWAP
TNZ
TRAP
WFI
Shift right Logic
Shift right Arithmetic
Substraction
N
N
N
N
M
M
SWAP nibbles
A7-A4 <=> A3-A0
tnz lbl1
reg, M
Test for Neg & Zero
S/W trap
S/W interrupt
1
1
1
0
Wait for Interrupt
Exclusive OR
XOR
A = A XOR M
A
N
Z
164/215
ST72F521, ST72521B
12 ELECTRICAL CHARACTERISTICS
12.1 PARAMETER CONDITIONS
Unless otherwise specified, all voltages are re-
Figure 85. Pin input voltage
ferred to V
.
SS
12.1.1 Minimum and Maximum values
Unless otherwise specified the minimum and max-
imum values are guaranteed in the worst condi-
tions of ambient temperature, supply voltage and
frequencies by tests in production on 100% of the
ST7 PIN
V
IN
devices with an ambient temperature at T =25°C
A
and T =T max (given by the selected temperature
A
A
range).
Data based on characterization results, design
simulation and/or technology characteristics are
indicated in the table footnotes and are not tested
in production. Based on characterization, the min-
imum and maximum values refer to sample tests
and represent the mean value plus or minus three
times the standard deviation (mean±3Σ).
12.1.2 Typical values
Unless otherwise specified, typical data are based
on T =25°C, V =5V.They are given only as de-
A
DD
sign guidelines and are not tested.
12.1.3 Typical curves
Unless otherwise specified, all typical curves are
given only as design guidelines and are not tested.
12.1.4 Loading capacitor
The loading conditions used for pin parameter
measurement are shown in Figure 84.
Figure 84. Pin loading conditions
ST7 PIN
C
L
12.1.5 Pin input voltage
The input voltage measurement on a pin of the de-
vice is described in Figure 85.
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ST72F521, ST72521B
12.2 ABSOLUTE MAXIMUM RATINGS
Stresses above those listed as “absolute maxi-
mum ratings” may cause permanent damage to
the device. This is a stress rating only and func-
tional operation of the device under these condi-
tions is not implied. Exposure to maximum rating
conditions for extended periods may affect device
reliability.
12.2.1 Voltage Characteristics
Symbol
Ratings
Maximum value
Unit
V
- V
- V
Supply voltage
6.5
DD
SS
V
Programming Voltage
13
PP
SS
V
Input Voltage on true open drain pin
VSS-0.3 to 6.5
1) & 2)
V
IN
Input voltage on any other pin
VSS-0.3 to VDD+0.3
|∆V
| and |∆V
|
SSx
Variations between different digital power pins
Variations between digital and analog ground pins
Electro-static discharge voltage (Human Body Model)
Electro-static discharge voltage (Machine Model)
50
50
DDx
mV
|V
- V
|
SSA
SSx
V
ESD(HBM)
see section 12.7.3 on page 181
V
ESD(MM)
12.2.2 Current Characteristics
Symbol
Ratings
Maximum value
Unit
3)
3)
I
Total current into V power lines (source)
150
150
25
VDD
DD
mA
I
Total current out of V ground lines (sink)
SS
VSS
Output current sunk by any standard I/O and control pin
Output current sunk by any high sink I/O pin
I
50
IO
Output current source by any I/Os and control pin
- 25
± 5
± 5
± 5
+ 5
± 5
± 25
Injected current on V pin
PP
Injected current on RESET pin
mA
2) & 4)
I
Injected current on OSC1 and OSC2 pins
INJ(PIN)
Injected current on PC6 (Flash devices only)
5) & 6)
Injected current on any other pin
2)
5)
ΣI
Total injected current (sum of all I/O and control pins)
INJ(PIN)
Notes:
1. Directly connecting the RESET and I/O pins to V or V could damage the device if an unintentional internal reset
DD
SS
is generated or an unexpected change of the I/O configuration occurs (for example, due to a corrupted program counter).
To guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7kΩ for
RESET, 10kΩ for I/Os). For the same reason, unused I/O pins must not be directly tied to V or V
.
DD
SS
2. I
must never be exceeded. This is implicitly insured if V maximum is respected. If V maximum cannot be
INJ(PIN)
IN
INJ(PIN)
IN
respected, the injection current must be limited externally to the I
value. A positive injection is induced by V >V
IN DD
while a negative injection is induced by V <V . For true open-drain pads, there is no positive injection current, and the
corresponding V maximum must always be respected
IN
SS
IN
3. All power (V ) and ground (V ) lines must always be connected to the external supply.
DD
SS
4. Negative injection disturbs the analog performance of the device. See note in “ADC Accuracy” on page 196.
For best reliability, it is recommended to avoid negative injection of more than 1.6mA.
5. When several inputs are submitted to a current injection, the maximum ΣI
is the absolute sum of the positive
INJ(PIN)
and negative injected currents (instantaneous values). These results are based on characterisation with ΣI
maxi-
INJ(PIN)
mum current injection on four I/O port pins of the device.
6. True open drain I/O port pins do not accept positive injection.
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ST72F521, ST72521B
12.2.3 Thermal Characteristics
Symbol
Ratings
Value
Unit
T
Storage temperature range
-65 to +150
°C
STG
T
Maximum junction temperature (see Section 13.2 THERMAL CHARACTERISTICS)
J
12.3 OPERATING CONDITIONS
12.3.1 General Operating Conditions
Symbol
Parameter
Conditions
Min
Max
Unit
f
Internal clock frequency
0
8
MHz
CPU
Standard voltage range (except Flash
Write/Erase)
3.8
5.5
V
V
DD
Operating Voltage for Flash Write/Erase
Ambient temperature range
V
= 11.4 to 12.6V
4.5
0
5.5
70
PP
1 Suffix Version
5 Suffix Version
-10
-40
-40
-40
85
T
6 or A Suffix Versions
7 or B Suffix Versions
C Suffix Version
85
°C
A
105
125
Figure 86. f
Max Versus VDD
CPU
f
[MHz]
CPU
FUNCTIONALITY
GUARANTEED
IN THIS AREA
(UNLESS
8
6
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
OTHERWISE
SPECIFIED
4
2
IN THE TABLES
OF PARAMETRIC
DATA)
1
0
3.5
3.8 4.0
4.5
5.5
SUPPLY VOLTAGE [V]
Note: Some temperature ranges are only available with a specific package and memory size. Refer to Or-
dering Information.
167/215
ST72F521, ST72521B
OPERATING CONDITIONS (Cont’d)
12.3.2 Operating Conditions with Low Voltage Detector (LVD)
Subject to general operating conditions for V , f
, and T .
A
DD CPU
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
1)
VD level = High in option byte
4.0
4.2
4.5
Reset release threshold
3)
1)
1)
1)
V
VD level = Med. in option byte 3.55
3.75
3.15
4.0
IT+(LVD)
(V rise)
DD
3)
1)
1)
VD level = Low in option byte
VD level = High in option byte
VD level = Med. in option byte
2.95
3.35
V
3.8
4.0
4.25
Reset generation threshold
3)
1)
1)
1)
V
V
3.35
3.55
3.0
3.75
3.15
IT-(LVD)
hys(LVD)
(V fall)
DD
3)
1)
VD level = Low in option byte
2.8
LVD voltage threshold hysteresis
V
-V
150
200
250
mV
ns
1)
IT+(LVD) IT-(LVD)
Flash device, LVD enabled
ROM device, LVD enabled
6µs/V
6µs/V
20ms/V
1)2)
Vt
t
V
V
rise time
POR
DD
DD
100ms/V
glitches filtered (not detect-
40
1)
g(VDD)
ed) by LVD
Notes:
1. Data based on characterization results, tested in production for ROM devices only.
2. When Vt is faster than 100 µs/V, the Reset signal is released after a delay of max. 42µs after V crosses the
POR
threshold.
DD
V
IT+(LVD)
3. If the medium or low thresholds are selected, the detection may occur outside the specified operating voltage range.
Below 3.8V, device operation is not guaranteed.
12.3.3 Auxiliary Voltage Detector (AVD) Thresholds
Subject to general operating conditions for V , f
, and T .
DD CPU
A
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
1)
VD level = High in option byte
4.4
4.6
4.9
1⇒0 AVDF flag toggle threshold
1)
1)
V
VD level = Med. in option byte
VD level = Low in option byte
3.95
3.4
4.15
3.6
4.4
3.8
IT+(AVD)
(V rise)
DD
1)
1)
1)
V
VD level = High in option byte
4.2
4.4
4.65
0⇒1 AVDF flag toggle threshold
1)
1)
V
V
VD level = Med. in option byte
VD level = Low in option byte
3.75
3.2
4.0
3.4
4.2
3.6
IT-(AVD)
hys(AVD)
(V fall)
DD
1)
1)
AVD voltage threshold hysteresis
V
-V
200
mV
mV
IT+(AVD) IT-(AVD)
Voltage drop between AVD flag set
and LVD reset activated
∆V
V
-V
450
IT-
IT-(AVD) IT-(LVD)
1. Data based on characterization results, tested in production for ROM devices only.
12.3.4 External Voltage Detector (EVD) Thresholds
Subject to general operating conditions for V , f
, and T .
A
DD CPU
Conditions
Symbol
Parameter
Min
Typ
Max
Unit
V
1⇒0 AVDF flag toggle threshold
V
1.15
1.26
1.35
1)
IT+(EVD)
(V rise)
DD
0⇒1 AVDF flag toggle threshold
V
V
1.1
1.2
1.3
1)
IT-(EVD)
hys(EVD)
(V fall)
DD
EVD voltage threshold hysteresis
V
-V
200
mV
IT+(EVD) IT-(EVD)
1. Data based on characterization results, not tested in production.
168/215
ST72F521, ST72521B
12.4 SUPPLY CURRENT CHARACTERISTICS
The following current consumption specified for the ST7 functional operating modes over temperature
range does not take into account the clock source current consumption. To get the total device consump-
tion, the two current values must be added (except for HALT mode for which the clock is stopped).
12.4.1 CURRENT CONSUMPTION
Flash Devices ROM Devices
Symbol
Parameter
Conditions
Unit
1)
1)
Typ
Max
Typ Max
f
f
f
f
=2MHz, f
=4MHz, f
=8MHz, f
=1MHz
=2MHz
=4MHz
1.3
2.0
3.6
7.1
3.0
5.0
8.0
1.3
2.0
3.6
7.1
2.0
3.0
5.0
OSC
OSC
OSC
OSC
CPU
CPU
CPU
2)
Supply current in RUN mode
mA
=16MHz, f
=8MHz
15.0
10.0
CPU
f
f
f
f
=2MHz, f
=4MHz, f
=8MHz, f
=62.5kHz
=125kHz
=250kHz
600
700
800
2700
3000
3600
4000
600
700
800
1800
2100
2400
OSC
OSC
OSC
OSC
CPU
CPU
CPU
2)
Supply current in SLOW mode
µA
=16MHz, f
=500kHz
1100
1100 3000
CPU
f
f
f
f
=2MHz, f
=4MHz, f
=8MHz, f
=1MHz
=2MHz
=4MHz
1.0
1.5
2.5
4.5
3.0
4.0
5.0
7.0
1.0
1.5
2.5
4.5
1.3
2.0
3.3
6.0
OSC
OSC
OSC
OSC
CPU
CPU
CPU
I
DD
2)
Supply current in WAIT mode
mA
=16MHz, f
=8MHz
CPU
f
f
f
f
=2MHz, f
=4MHz, f
=8MHz, f
=62.5kHz
=125kHz
=250kHz
580
650
770
1200
1300
1800
2000
70
200
300
600
OSC
OSC
OSC
OSC
CPU
CPU
CPU
100
200
350
2)
Supply current in SLOW WAIT mode
µA
µA
=16MHz, f
=500kHz
1050
1200
CPU
-40°C≤T ≤+85°C
-40°C≤T ≤+125°C
<1
<1
10
50
<1
<1
10
50
A
3)
Supply current in HALT mode
A
f
f
f
f
=2MHz
=4MHz
=8MHz
=16MHz
80
160
No
max.
15
30
25
50
100
200
OSC
OSC
OSC
OSC
Supply current in ACTIVE-HALT mode
I
µA
4)
DD
325 guaran- 60
650 teed 120
Notes:
1. Data based on characterization results, tested in production at V max. and f
max.
CPU
DD
2. Measurements are done in the following conditions:
- Program executed from RAM, CPU running with RAM access. The increase in consumption when executing from Flash
is 50%.
- All I/O pins in input mode with a static value at V or V (no load)
DD
SS
- All peripherals in reset state.
- LVD disabled.
- Clock input (OSC1) driven by external square wave.
- In SLOW and SLOW WAIT mode, f is based on f
divided by 32.
OSC
CPU
To obtain the total current consumption of the device, add the clock source (Section 12.4.2) and the peripheral power
consumption (Section 12.4.3).
3. All I/O pins in push-pull 0 mode (when applicable) with a static value at V or VSS (no load), LVD disabled. Data
DD
CPU
based on characterization results, tested in production at V max. and f
max.
DD
4. Data based on characterisation results, not tested in production. All I/O pins in push-pull 0 mode (when applicable) with
a static value at V or V (no load); clock input (OSC1) driven by external square wave, LVD disabled. To obtain the
DD
SS
total current consumption of the device, add the clock source consumption (Section 12.4.2).
169/215
ST72F521, ST72521B
SUPPLY CURRENT CHARACTERISTICS (Cont’d)
12.4.1.1 Power Consumption vs f
: Flash Devices
CPU
Figure 87. Typical I in RUN mode
Figure 89. Typical I in WAIT mode
DD
DD
8MHz
4MHz
2MHz
1MHz
6
5
4
3
2
1
0
8MHz
4MHz
2MHz
1MHz
9
8
7
6
5
4
3
2
1
0
3.2
3.6
4
4.4
4.8
5.2
5.5
3.2
3.6
4
4.4
4.8
5.2
5.5
Vdd (V)
Vdd (V)
Figure 90. Typ. I in SLOW-WAIT mode
DD
Figure 88. Typical I in SLOW mode
DD
500kHz
1.20
500kHz
1.20
250kHz
250kHz
1.00
0.80
0.60
0.40
0.20
0.00
125kHz
62.5kHz
1.00
125kHz
62.5kHz
0.80
0.60
0.40
0.20
0.00
3.2
3.6
4
4.4
4.8
5.2
5.5
3.2
3.6
4
4.4
4.8
5.2
5.5
Vdd (V)
Vdd (V)
170/215
ST72F521, ST72521B
SUPPLY CURRENT CHARACTERISTICS (Cont’d)
12.4.2 Supply and Clock Managers
The previous current consumption specified for the ST7 functional operating modes over temperature
range does not take into account the clock source current consumption. To get the total device consump-
tion, the two current values must be added (except for HALT mode).
Symbol
Parameter
Conditions
Typ
Max
Unit
I
Supply current of internal RC oscillator
625
DD(RCINT)
see section
12.5.3 on page
174
1) & 2)
I
I
Supply current of resonator oscillator
DD(RES)
µA
I
PLL supply current
LVD supply current
V
V
= 5V
= 5V
360
DD(PLL)
DD
DD
150
300
DD(LVD)
Notes:
1.. Data based on characterization results done with the external components specified in Section 12.5.3, not tested in
production.
2. As the oscillator is based on a current source, the consumption does not depend on the voltage.
171/215
ST72F521, ST72521B
SUPPLY CURRENT CHARACTERISTICS (Cont’d)
12.4.3 On-Chip Peripherals
Measured on S72F521R9T3 on TQFP64 generic board T = 25°C f
=4MHz.
A
CPU
Symbol
Parameter
Conditions
Typ
50
Unit
µA
µA
µA
µA
µA
µA
µA
1)
I
16-bit Timer supply current
V
V
V
V
V
V
V
=5.0V
DD(TIM)
DD
DD
DD
DD
DD
DD
DD
2)
I
ART PWM supply current
=5.0V
=5.0V
=5.0V
=5.0V
=5.0V
=5.0V
75
DD(ART)
3)
I
SPI supply current
400
400
175
400
400
DD(SPI)
4)
I
SCI supply current
DD(SCI)
5)
I
I2C supply current
DD(I2C)
6)
I
ADC supply current when converting
DD(ADC)
5)
I
CAN supply current
DD(CAN)
Notes:
1. Data based on a differential I measurement between reset configuration (timer counter running at f
/4) and timer
DD
CPU
counter stopped (only TIMD bit set). Data valid for one timer.
2. Data based on a differential I measurement between reset configuration (timer stopped) and timer counter enabled
DD
(only TCE bit set).
3. Data based on a differential I measurement between reset configuration (SPI disabled) and a permanent SPI master
DD
communication at maximum speed (data sent equal to 55h).This measurement includes the pad toggling consumption.
4. Data based on a differential I measurement between SCI low power state (SCID=1) and a permanent SCI data trans-
DD
mit sequence.
5. Data based on a differential I measurement between reset configuration (I2C disabled) and a permanent I2C master
DD
communication at 100kHz (data sent equal to 55h). This measurement include the pad toggling consumption (27kOhm
external pull-up on clock and data lines).
6. Data based on a differential I measurement between reset configuration and continuous A/D conversions.
DD
7. Data based on a differential IDD measurement between reset configuration (CAN disabled) and a permanent CAN data
transmit sequence with RX and TX connected together. This measurement include the pad toggling consumption.
172/215
ST72F521, ST72521B
12.5 CLOCK AND TIMING CHARACTERISTICS
Subject to general operating conditions for V , f
, and T .
DD CPU
A
12.5.1 General Timings
1)
Symbol
Parameter
Conditions
Min
2
Typ
3
Max
12
Unit
tCPU
ns
t
Instruction cycle time
c(INST)
f
f
=8MHz
250
10
375
1500
22
CPU
CPU
2)
tCPU
µs
Interrupt reaction time
t
v(IT)
t
= ∆t
+ 10
c(INST)
=8MHz
1.25
2.75
v(IT)
12.5.2 External Clock Source
Symbol
Parameter
Conditions
Min
-1
Typ
Max
Unit
V
OSC1 input pin high level voltage
OSC1 input pin low level voltage
V
V
DD
OSC1H
DD
V
V
V
V
+1
SS
OSC1L
SS
t
t
3)
w(OSC1H)
see Figure 91
OSC1 high or low time
5
w(OSC1L)
ns
t
t
3)
r(OSC1)
OSC1 rise or fall time
15
±1
f(OSC1)
I
OSC1 Input leakage current
V
≤V ≤V
DD
µA
L
SS
IN
Figure 91. Typical Application with an External Clock Source
90%
V
V
OSC1H
10%
OSC1L
t
t
w(OSC1H)
t
t
w(OSC1L)
f(OSC1)
r(OSC1)
OSC2
Not connected internally
f
OSC
EXTERNAL
CLOCK SOURCE
I
L
OSC1
ST72XXX
Notes:
1. Data based on typical application software.
2. Time measured between interrupt event and interrupt vector fetch. ∆tc(INST) is the number of tCPU cycles needed to finish
the current instruction execution.
3. Data based on design simulation and/or technology characteristics, not tested in production.
173/215
ST72F521, ST72521B
CLOCK AND TIMING CHARACTERISTICS (Cont’d)
12.5.3 Crystal and Ceramic Resonator Oscillators
The ST7 internal clock can be supplied with four
different Crystal/Ceramic resonator oscillators. All
the information given in this paragraph are based
on characterization results with specified typical
external components. In the application, the reso-
nator and the load capacitors have to be placed as
close as possible to the oscillator pins in order to
minimize output distortion and start-up stabiliza-
tion time. Refer to the crystal/ceramic resonator
manufacturer for more details (frequency, pack-
age, accuracy...).
Symbol
Parameter
Conditions
Min
Max
Unit
MHz
kΩ
LP: Low power oscillator
1
2
4
8
MP: Medium power oscillator
MS: Medium speed oscillator
HS: High speed oscillator
>2
>4
>8
1)
f
Oscillator Frequency
OSC
16
2)
R
Feedback resistor
20
40
F
R =200Ω
S
LP oscillator
MP oscillator
MS oscillator
HS oscillator
22
22
18
15
56
46
33
33
S
Recommended load capacitance ver-
sus equivalent serial resistance of the
C
C
R =200Ω
L1
L2
pF
R =200Ω
S
crystal or ceramic resonator (R )
S
R =100Ω
S
Symbol
Parameter
Conditions
Typ
Max
Unit
V
=5V
LP oscillator
MP oscillator
MS oscillator
HS oscillator
80
150
250
460
910
DD
V =V
160
310
610
IN
SS
i
OSC2 driving current
µA
2
Figure 92. Typical Application with a Crystal or Ceramic Resonator
WHEN RESONATOR WITH
INTEGRATED CAPACITORS
i
2
f
OSC
C
L1
OSC1
OSC2
RESONATOR
R
F
C
L2
ST72XXX
Notes:
1. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small R value.
S
Refer to crystal/ceramic resonator manufacturer for more details.
2. Data based on characterisation results, not tested in production.
174/215
ST72F521, ST72521B
CLOCK AND TIMING CHARACTERISTICS (Cont’d)
Typical Ceramic Resonators
f
OSC
Supplier
Recommended OSCRANGE
Option bit configuration
2)
(MHz)
Reference
3)
2
4
CSTCC2M00G56A-R0
CSTCR4M00G55B-R0
CSTCE8M00G55A-R0
CSTCE16M0G53A-R0
MP Mode
MS Mode
HS Mode
HS Mode
8
16
Notes:
1. Resonator characteristics given by the ceramic resonator manufacturer.
2. SMD = [-R0: Plastic tape package (∅ =180mm), -B0: Bulk]
LEAD = [-A0: Flat pack package (Radial taping Ho= 18mm), -B0: Bulk]
3. LP mode is not recommended for 2 MHz resonator because the peak to peak amplitude is too small (>0.8V)
For more information on these resonators, please consult www.murata.com
175/215
ST72F521, ST72521B
CLOCK CHARACTERISTICS (Cont’d)
12.5.4 RC Oscillators
Symbol
Parameter
Internal RC oscillator frequency
See Figure 93
Conditions
Min
Typ
Max
Unit
T =25°C, V =5V
f
2
3.5
5.6
MHz
A
DD
OSC (RCINT)
Figure 93. Typical f
vs T
Note: To reduce disturbance to the RC oscillator,
OSC(RCINT)
A
it is recommended to place decoupling capacitors
between V and V as shown in Figure 113
DD
SS
4
3.8
3.6
3.4
3.2
3
Vdd = 5V
Vdd = 5.5V
-45
0
25
70
130
TA(°C)
176/215
ST72F521, ST72521B
CLOCK CHARACTERISTICS (Cont’d)
12.5.5 PLL Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
f
PLL input frequency range
2
4
MHz
OSC
ROM device,
= 4 MHz.
0.7
1.0
2.5
2
f
OSC
Flash device,
= 4 MHz.
1)
∆ f
/ f
Instantaneous PLL jitter
2.5
4.0
%
CPU CPU
f
OSC
Flash device,
= 2 MHz.
f
OSC
Note:
1. Data characterized but not tested.
The user must take the PLL jitter into account in the application (for example in serial communication or
sampling of high frequency signals). The PLL jitter is a periodic effect, which is integrated over several
CPU cycles. Therefore the longer the period of the application signal, the less it will be impacted by the
PLL jitter.
Figure 94 shows the PLL jitter integrated on application signals in the range 125kHz to 4MHz. At frequen-
cies of less than 125KHz, the jitter is negligible.
1
Figure 94. Integrated PLL Jitter vs signal frequency
+/-Jitter (%)
1.2
FLASH typ
1
ROM max
ROM typ
0.8
0.6
0.4
0.2
0
4 MHz 2 MHz 1 MHz 500 kHz 250 kHz 125 kHz
Application Frequency
Note 1: Measurement conditions: f
= 8MHz.
CPU
177/215
ST72F521, ST72521B
12.6 MEMORY CHARACTERISTICS
12.6.1 RAM and Hardware Registers
Symbol
Parameter
Conditions
Min
Typ
Typ
Max
Unit
1)
V
Data retention mode
HALT mode (or RESET)
1.6
V
RM
12.6.2 FLASH Memory
DUAL VOLTAGE HDFLASH MEMORY
2)
2)
Symbol
Parameter
Conditions
Read mode
Min
Max
Unit
MHz
V
0
1
8
8
f
Operating frequency
CPU
Write / Erase mode
4.5V ≤ VDD ≤ 5.5V
3)
V
Programming voltage
11.4
12.6
3
PP
RUN mode (f
= 4MHz)
CPU
mA
4)
I
Supply current
Write / Erase
0
1
DD
Power down mode / HALT
10
200
30
µA
Read (V =12V)
PP
4)
I
V
current
PP
PP
Write / Erase
mA
µs
t
Internal V stabilization time
10
25
VPP
PP
t
Data retention
T =55°C
20
years
cycles
RET
A
N
Write erase cycles
T =25°C
100
RW
A
T
Programming or erasing tempera-
ture range
PROG
-40
85
°C
T
ERASE
Notes:
1. Minimum V supply voltage without losing data stored in RAM (in HALT mode or under RESET) or in hardware reg-
DD
isters (only in HALT mode). Not tested in production.
2. Data based on characterization results, not tested in production.
3. V must be applied only during the programming or erasing operation and not permanently for reliability reasons.
PP
4. Data based on simulation results, not tested in production.
Warning: Do not connect 12V to V before V is powered on, as this may damage the device.
PP
DD
178/215
ST72F521, ST72521B
12.7 EMC CHARACTERISTICS
should be noted that good EMC performance is
highly dependent on the user application and the
software in particular.
Susceptibility tests are performed on a sample ba-
sis during product characterization.
Therefore it is recommended that the user applies
EMC software optimization and prequalification
tests in relation with the EMC level requested for
his application.
12.7.1 Functional EMS (Electro Magnetic
Susceptibility)
Based on a simple running application on the
product (toggling 2 LEDs through I/O ports), the
product is stressed by two electro magnetic events
until a failure occurs (indicated by the LEDs).
■ ESD: Electro-Static Discharge (positive and
negative) is applied on all pins of the device until
a functional disturbance occurs. This test
conforms with the IEC 1000-4-2 standard.
Software recommendations:
The software flowchart must include the manage-
ment of runaway conditions such as:
– Corrupted program counter
– Unexpected reset
– Critical Data corruption (control registers...)
Prequalification trials:
■ FTB: A Burst of Fast Transient voltage (positive
and negative) is applied to V and V through
DD
SS
a 100pF capacitor, until a functional disturbance
occurs. This test conforms with the IEC 1000-4-
4 standard.
Most of the common failures (unexpected reset
and program counter corruption) can be repro-
duced by manually forcing a low state on the RE-
SET pin or the Oscillator pins for 1 second.
A device reset allows normal operations to be re-
sumed. The test results are given in the table be-
low based on the EMS levels and classes defined
in application note AN1709.
To complete these trials, ESD stress can be ap-
plied directly on the device, over the range of
specification values. When unexpected behaviour
is detected, the software can be hardened to pre-
vent unrecoverable errors occurring (see applica-
tion note AN1015)
12.7.1.1 Designing hardened software to avoid
noise problems
EMC characterization and optimization are per-
formed at component level with a typical applica-
tion environment and simplified MCU software. It
.
Level/
Symbol
Parameter
Conditions
Class
Flash device: V =5V, T =+25°C,
OSC
DD
A
4B
3B
f
=8MHz, conforms to IEC 1000-4-2
Voltage limits to be applied on any I/O pin to induce a
functional disturbance
V
FESD
ROM device: V =5V, T =+25°C, f
O-
DD
A
=8MHz,conforms to IEC 1000-4-2
SC
Fast transient voltage burst limits to be applied
Flash device: V =5V, T =+25°C, f
=8
=8
DD
A
OSC
OSC
V
V
through 100pF on V and V pins to induce a func-
3B
3B
FFTB
FFTB
DD
DD
MHz, conforms to IEC 1000-4-4
tional disturbance
Fast transient voltage burst limits to be applied
through 100pF on V and V pins to induce a func-
Flash device: V =5V, T =+25°C, f
DD
A
DD
DD
MHz, conforms to IEC 1000-4-4
tional disturbance
179/215
ST72F521, ST72521B
EMC CHARACTERISTICS (Cont’d)
12.7.2 Electro Magnetic Interference (EMI)
Based on a simple application running on the
product (toggling 2 LEDs through the I/O ports),
the product is monitored in terms of emission. This
emission test is in line with the norm SAE J 1752/
3 which specifies the board and the loading of
each pin.
Max vs. [f
/f
]
Unit
Monitored
Frequency Band
OSC CPU
Symbol
Parameter
Conditions
8/4MHz 16/8MHz
0.1MHz to 30MHz
30MHz to 130MHz
130MHz to 1GHz
SAE EMI Level
15
20
0
15
27
5
V
=5V, T =+25°C,
DD
A
dBµV
S
Peak level
TQFP64 14x14 package
conforming to SAE J 1752/3
EMI
2.5
3.0
-
Notes:
1. Data based on characterization results, not tested in production.
2. Refer to Application Note AN1709 for data on other package types.
180/215
ST72F521, ST72521B
EMC CHARACTERISTICS (Cont’d)
12.7.3 Absolute Maximum Ratings (Electrical
Sensitivity)
12.7.3.1 Electro-Static Discharge (ESD)
Electro-Static Discharges (a positive then a nega-
tive pulse separated by 1 second) are applied to
the pins of each sample according to each pin
combination. The sample size depends on the
number of supply pins in the device (3 parts*(n+1)
supply pin). Two models can be simulated: Human
Body Model and Machine Model. This test con-
forms to the JESD22-A114A/A115A standard.
Based on three different tests (ESD, LU and DLU)
using specific measurement methods, the product
is stressed in order to determine its performance in
terms of electrical sensitivity. For more details, re-
fer to the application note AN1181.
Absolute Maximum Ratings
1)
Symbol
Ratings
Conditions
Maximum value
Unit
Electro-static discharge voltage
(Human Body Model)
T =+25°C
V
2000
A
ESD(HBM)
V
Electro-static discharge voltage
(Machine Model)
T =+25°C
V
200
A
ESD(MM)
Notes:
1. Data based on characterization results, not tested in production.
12.7.3.2 Static and Dynamic Latch-Up
■ DLU: Electro-Static Discharges (one positive
then one negative test) are applied to each pin
of 3 samples when the micro is running to
assess the latch-up performance in dynamic
mode. Power supplies are set to the typical
values, the oscillator is connected as near as
possible to the pins of the micro and the
component is put in reset mode. This test
conforms to the IEC1000-4-2 and SAEJ1752/3
standards. For more details, refer to the
application note AN1181.
■ LU: 3 complementary static tests are required
on 10 parts to assess the latch-up performance.
A supply overvoltage (applied to each power
supply pin) and a current injection (applied to
each input, output and configurable I/O pin) are
performed on each sample. This test conforms
to the EIA/JESD 78 IC latch-up standard. For
more details, refer to the application note
AN1181.
Electrical Sensitivities
1)
Symbol
Parameter
Static latch-up class
Dynamic latch-up class
Conditions
Class
T =+25°C
A
A
A
A
A
LU
T =+85°C
T =+125°C
A
V
=5.5V, f
=4MHz, T =+25°C
OSC A
DLU
A
DD
Notes:
1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC spec-
ifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the
JEDEC criteria (international standard).
181/215
ST72F521, ST72521B
12.8 I/O PORT PIN CHARACTERISTICS
12.8.1 General Characteristics
Subject to general operating conditions for V , f
, and T unless otherwise specified.
A
DD OSC
Symbol
Parameter
Conditions
Min
Typ
0.7
1
Max
Unit
1)
V
Input low level voltage
Input high level voltage
0.3xVDD
IL
1)
V
CMOS ports
TTL ports
0.7xVDD
IH
2)
2)
V
Schmitt trigger voltage hysteresis
hys
V
1)
V
Input low level voltage
0.8
IL
IH
1)
V
Input high level voltage
2
0
V
Schmitt trigger voltage hysteresis
hys
Injected Current on PC6 (Flash de-
vices only)
+4
± 4
± 25
±1
3)
I
INJ(PIN)
Injected Current on an I/O pin
V
V
=5V
mA
DD
Total injected current (sum of all I/O
and control pins)
3)
ΣI
INJ(PIN)
I
Input leakage current
SS≤V ≤V
L
IN
DD
µA
4)
I
Static current consumption
Floating input mode
V =V =5V
400
120
5
S
5)
R
Weak pull-up equivalent resistor
V
DD
50
1
250
kΩ
PU
IN
SS
C
I/O pin capacitance
pF
IO
1)
t
Output high to low level fall time
25
C =50pF
Between 10% and 90%
f(IO)out
r(IO)out
L
ns
1)
t
Output low to high level rise time
25
6)
t
External interrupt pulse time
t
CPU
w(IT)in
Figure 95. Unused I/O Pins configured as input
Figure 96. Typical I vs. V with V =V
PU DD IN SS
90
80
70
60
50
40
30
20
10
0
V
DD
Ta=140°C
Ta=95°C
Ta=25°C
Ta=-45°C
ST7XXX
10kΩ
10kΩ
UNUSED I/O PORT
UNUSED I/O PORT
ST7XXX
Note: I/O can be left unconnected if it is configured as output
(0 or 1) by the software. This has the advantage of
greater EMC robustness and lower cost.
2
2.5
3
3.5
4
4.5
5
5.5
6
Vdd(V)
Notes:
1. Data based on characterization results, not tested in production.
2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
3. When the current limitation is not possible, the V maximum must be respected, otherwise refer to I
specifica-
INJ(PIN)
IN
tion. A positive injection is induced by V >V while a negative injection is induced by V <V . Refer to section 12.2.2
IN
DD
IN
SS
on page 166 for more details.
4. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for
example and leaving the I/O unconnected on the board or an external pull-up or pull-down resistor (see Figure 95). Data
based on design simulation and/or technology characteristics, not tested in production.
5. The R pull-up equivalent resistor is based on a resistive transistor (corresponding I current characteristics de-
PU
PU
scribed in Figure 96).
6. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external
interrupt source.
182/215
ST72F521, ST72521B
I/O PORT PIN CHARACTERISTICS (Cont’d)
12.8.2 Output Driving Current
Subject to general operating conditions for V , f
, and T unless otherwise specified.
A
DD CPU
Symbol
Parameter
Conditions
Min
Max
Unit
Output low level voltage for a standard I/O pin
when 8 pins are sunk at same time
(see Figure 97)
I
I
I
=+5mA
=+2mA
1.2
IO
IO
IO
0.5
1)
V
OL
=+20mA,T ≤85°C
1.3
1.5
A
Output low level voltage for a high sink I/O pin
when 4 pins are sunk at same time
(see Figure 98 and Figure 100)
T ≥85°C
A
V
I
I
=+8mA
0.6
IO
=-5mA, T ≤85°C
V
V
-1.4
-1.6
IO
A
Output high level voltage for an I/O pin
when 4 pins are sourced at same time
(see Figure 99 and Figure 102)
DD
DD
2)
T ≥85°C
V
A
OH
I
=-2mA
V
-0.7
IO
DD
Figure 97. Typical V at V =5V (standard)
Figure 99. Typical V at V =5V
OH DD
OL
DD
1.4
1.2
1
5.5
5
4.5
4
0.8
0.6
0.4
0.2
0
3.5
3
Ta=140°C "
Ta=95°C
Ta=25°C
Ta=-45°C
Vdd=5V 140°C min
Vdd=5v 95°C min
Vdd=5v 25°C min
Vdd=5v -45°C min
2.5
2
0
0.005
0.01
0.015
-0.01 -0.008 -0.006 -0.004 -0.002
0
Iio(A)
Figure 98. Typical V at V =5V (high-sink)
OL
DD
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
Ta= 140°C
Ta= 95°C
Ta= 25°C
Ta=-45°C
0
0.01
0.02
0.03
Iio(A)
Notes:
1. The I current sunk must always respect the absolute maximum rating specified in Section 12.2.2 and the sum of I
IO
IO
(I/O ports and control pins) must not exceed I
.
VSS
2. The I current sourced must always respect the absolute maximum rating specified in Section 12.2.2 and the sum of
IO
I
(I/O ports and control pins) must not exceed I
. True open drain I/O pins do not have V
.
IO
VDD
OH
183/215
ST72F521, ST72521B
I/O PORT PIN CHARACTERISTICS (Cont’d)
Figure 100. Typical V vs. V (standard)
OL
DD
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.45
0.4
Ta= -45°C
Ta= 25°C
Ta=-45°C
Ta=25°C
Ta=95°C
Ta=140°C
Ta= 95°C
0.35
0.3
Ta= 140°C
0.25
0.2
0.15
0.1
0.05
0
2
2.5
3
3.5
4
4.5
5
5.5
6
2
2.5
3
3.5
4
4.5
5
5.5
6
Vdd(V)
Vdd(V)
Figure 101. Typical V vs. V (high-sink)
OL
DD
1.6
1.4
1.2
1
0.6
Ta= 140°C
Ta=95°C
Ta=25°C
Ta=-45°C
0.5
0.4
0.3
0.2
0.8
0.6
0.4
0.2
0
Ta= 140°C
Ta=95°C
Ta=25°C
Ta=-45°C
0.1
0
2
2.5
3
3.5
4
4.5
5
5.5
6
2
2.5
3
3.5
4
4.5
5
5.5
6
V dd(V )
Vdd(V )
Figure 102. Typical V -V vs. V
DD OH
DD
5.5
6
5
4
3
2
1
0
Ta=-45°C
Ta=25°C
Ta=95°C
Ta=140°C
5
4.5
4
3.5
3
Ta=-45°C
Ta=25°C
Ta=95°C
Ta=140°C
2.5
2
2
2.5
3
3.5
4
4.5
5
5.5
6
2
2.5
3
3.5
4
4.5
5
5.5
6
Vdd(V)
Vdd(V)
184/215
ST72F521, ST72521B
12.9 CONTROL PIN CHARACTERISTICS
12.9.1 Asynchronous RESET Pin
Subject to general operating conditions for V , f
, and T unless otherwise specified.
A
DD CPU
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
1)
V
Input low level voltage
0.16xVDD
IL
V
1)
V
Input high level voltage
0.85xVDD
IH
2)
V
Schmitt trigger voltage hysteresis
2.5
0.2
2
hys
V
3)
V
Output low level voltage
V
=5V
I =+2mA
IO
0.5
OL
IO
DD
I
Input current on RESET pin
mA
R
Weak pull-up equivalent resistor
20
0
30
120
kΩ
ON
Stretch applied on
external pulse
6)
42
µs
t
Generated reset pulse duration
w(RSTL)out
6)
Internal reset sources
20
30
42
µs
µs
ns
4)
t
External reset pulse hold time
2.5
h(RSTL)in
5)
t
Filtered glitch duration
200
g(RSTL)in
Notes:
1. Data based on characterization results, not tested in production.
2. Hysteresis voltage between Schmitt trigger switching levels.
3. The I current sunk must always respect the absolute maximum rating specified in Section 12.2.2 and the sum of I
IO
IO
(I/O ports and control pins) must not exceed I
.
VSS
4. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on
the RESET pin with a duration below t can be ignored.
h(RSTL)in
5. The reset network (the resistor and two capacitors) protects the device against parasitic resets, especially in noisy en-
vironments.
6. Data guaranteed by design, not tested in production.
185/215
ST72F521, ST72521B
CONTROL PIN CHARACTERISTICS (Cont’d)
1)2)3)4)
Figure 103. RESET pin protection when LVD is enabled.
V
ST72XXX
DD
Optional
(note 3)
Required
R
ON
Filter
INTERNAL
RESET
EXTERNAL
RESET
0.01µF
1MΩ
WATCHDOG
PULSE
GENERATOR
LVD RESET
1)
Figure 104. RESET pin protection when LVD is disabled.
Recommended for EMC
V
ST72XXX
DD
V
V
DD
DD
R
ON
Filter
0.01µF
0.01µF
4.7kΩ
INTERNAL
RESET
USER
EXTERNAL
RESET
CIRCUIT
PULSE
GENERATOR
WATCHDOG
Required
Note 1:
– The reset network protects the device against parasitic resets.
– The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the
device can be damaged when the ST7 generates an internal reset (LVD or watchdog).
– Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin can go
below the V max. level specified in section 12.9.1 on page 185. Otherwise the reset will not be taken into account
IL
internally.
– Because the reset circuit is designed to allow the internal RESET to be output in the RESET pin, the user must en-
sure that the current sunk on the RESET pin is less than the absolute maximum value specified for I
section 12.2.2 on page 166.
in
INJ(RESET)
Note 2: When the LVD is enabled, it is recommended not to connect a pull-up resistor or capacitor. A 10nF pull-down
capacitor is required to filter noise on the reset line.
Note 3: In case a capacitive power supply is used, it is recommended to connect a 1MΩ pull-down resistor to the RESET
pin to discharge any residual voltage induced by the capacitive effect of the power supply (this will add 5µA to the power
consumption of the MCU).
Note 4: Tips when using the LVD:
– 1. Check that all recommendations related to reset circuit have been applied (see notes above).
– 2. Check that the power supply is properly decoupled (100nF + 10µF close to the MCU). Refer to AN1709 and
AN2017. If this cannot be done, it is recommended to put a 100nF + 1MΩ pull-down on the RESET pin.
– 3. The capacitors connected on the RESET pin and also the power supply are key to avoid any start-up marginality.
In most cases, steps 1 and 2 above are sufficient for a robust solution. Otherwise: replace 10nF pull-down on the
RESET pin with a 5µF to 20µF capacitor.
186/215
ST72F521, ST72521B
CONTROL PIN CHARACTERISTICS (Cont’d)
12.9.2 ICCSEL/V Pin
PP
Subject to general operating conditions for V , f
, and T unless otherwise specified.
DD CPU
A
Symbol
Parameter
Conditions
Min
Max
Unit
V
FLASH versions
V
V
0.2
SS
SS
1)
V
Input low level voltage
IL
ROM versions
FLASH versions
ROM versions
V =V
0.3xV
DD
V
-0.1 12.6
DD
1)
V
I
Input high level voltage
Input leakage current
IH
0.7xV
V
DD
DD
±1
µA
L
IN
SS
2)
Figure 105. Two typical Applications with ICCSEL/V Pin
PP
ICCSEL/V
V
PP
PP
PROGRAMMING
TOOL
10kΩ
ST72XXX
ST72XXX
Notes:
1. Data based on design simulation and/or technology characteristics, not tested in production.
2. When ICC mode is not required by the application ICCSEL/V pin must be tied to V
.
SS
PP
187/215
ST72F521, ST72521B
12.10 TIMER PERIPHERAL CHARACTERISTICS
Subject to general operating conditions for V , f
, and T unless otherwise specified.
A
DD OSC
Refer to I/O port characteristics for more details on the input/output alternate function characteristics (out-
put compare, input capture, external clock, PWM output...).
12.10.1 8-Bit PWM-ART Auto-Reload Timer
Symbol
Parameter
Conditions
Min
1
Typ
Max
Unit
t
CPU
t
PWM resolution time
res(PWM)
f
=8MHz
125
0
ns
CPU
f
ART external clock frequency
PWM repetition rate
f
/2
CPU
EXT
MHz
f
0
f
/2
CPU
PWM
Res
PWM resolution
8
bit
PWM
OS
V
PWM/DAC output step voltage
V
=5V, Res=8-bits
20
mV
DD
12.10.2 16-Bit Timer
Symbol
Parameter
Conditions
Min
1
Typ
Max
Unit
t
Input capture pulse time
t
t
w(ICAP)in
CPU
2
CPU
t
PWM resolution time
res(PWM)
f
=8MHz
250
0
ns
CPU
f
Timer external clock frequency
PWM repetition rate
f
f
/4
MHz
MHz
bit
EXT
CPU
f
0
/4
CPU
PWM
Res
PWM resolution
16
PWM
188/215
ST72F521, ST72521B
12.11 COMMUNICATION INTERFACE CHARACTERISTICS
12.11.1 SPI - Serial Peripheral Interface
Refer to I/O port characteristics for more details on
the input/output alternate function characteristics
(SS, SCK, MOSI, MISO).
Subject to general operating conditions for V
,
DD
f
, and T unless otherwise specified.
CPU
A
Symbol
Parameter
Conditions
Min
/128
0.0625
Max
Unit
Master
Slave
f
f
f
/4
CPU
2
CPU
f
=8MHz
=8MHz
f
CPU
SCK
MHz
SPI clock frequency
1/t
/2
c(SCK)
CPU
0
f
4
CPU
t
t
r(SCK)
SPI clock rise and fall time
see I/O port pin description
f(SCK)
t
SS setup time
SS hold time
Slave
Slave
120
120
su(SS)
t
h(SS)
t
t
Master
Slave
100
90
w(SCKH)
SCK high and low time
Data input setup time
Data input hold time
w(SCKL)
t
Master
Slave
100
100
su(MI)
t
su(SI)
ns
t
Master
Slave
100
100
h(MI)
t
h(SI)
t
Data output access time
Data output disable time
Data output valid time
Data output hold time
Data output valid time
Data output hold time
Slave
Slave
0
120
240
90
a(SO)
t
dis(SO)
t
v(SO)
h(SO)
v(MO)
h(MO)
Slave (after enable edge)
t
0
t
0.25
0.25
Master (before capture edge)
t
CPU
t
Figure 106. SPI Slave Timing Diagram with CPHA=0 3)
SS
INPUT
t
t
su(SS)
c(SCK)
t
h(SS)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
t
t
w(SCKH)
w(SCKL)
t
t
t
t
dis(SO)
a(SO)
v(SO)
h(SO)
t
t
r(SCK)
f(SCK)
see
note 2
MISO
OUTPUT
INPUT
MSB OUT
see note 2
BIT6 OUT
LSB OUT
t
t
h(SI)
su(SI)
LSB IN
MSB IN
BIT1 IN
MOSI
Notes:
1. Data based on design simulation and/or characterisation results, not tested in production.
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has
its alternate function capability released. In this case, the pin status depends on the I/O port configuration.
3. Measurement points are done at CMOS levels: 0.3xV and 0.7xV
.
DD
DD
189/215
ST72F521, ST72521B
COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d)
Figure 107. SPI Slave Timing Diagram with CPHA=11)
SS
INPUT
t
t
su(SS)
c(SCK)
t
h(SS)
CPHA=1
CPOL=0
CPHA=1
CPOL=1
t
t
w(SCKH)
w(SCKL)
t
t
dis(SO)
a(SO)
t
t
h(SO)
v(SO)
t
t
r(SCK)
f(SCK)
see
note 2
see
note 2
MISO
OUTPUT
MSB OUT
BIT6 OUT
HZ
LSB OUT
t
t
h(SI)
su(SI)
MSB IN
LSB IN
BIT1 IN
MOSI
INPUT
Figure 108. SPI Master Timing Diagram 1)
SS
INPUT
t
c(SCK)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
CPHA=1
CPOL=0
CPHA=1
CPOL=1
t
t
w(SCKH)
w(SCKL)
t
t
r(SCK)
f(SCK)
t
t
h(MI)
su(MI)
MISO
MOSI
INPUT
MSB IN
h(MO)
BIT6 IN
LSB IN
t
t
v(MO)
MSB OUT
LSB OUT
see note 2
BIT6 OUT
see note 2
OUTPUT
Notes:
1. Measurement points are done at CMOS levels: 0.3xV and 0.7xV
.
DD
DD
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has
its alternate function capability released. In this case, the pin status depends of the I/O port configuration.
190/215
ST72F521, ST72521B
COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d)
2
I C - Inter IC Control Interface
Refer to I/O port characteristics for more details on
the input/output alternate function characteristics
12.11.2
Subject to general operating conditions for V
,
DD
2
(SDAI and SCLI). The ST7 I C interface meets the
, and T unless otherwise specified.
f
A
2
CPU
requirements of the Standard I C communication
protocol described in the following table.
2
2
5)
Standard mode I C
Fast mode I C
Symbol
Parameter
Unit
1)
1)
1)
1)
Min
Max
Min
1.3
Max
t
SCL clock low time
SCL clock high time
SDA setup time
4.7
4.0
250
w(SCLL)
µs
t
0.6
w(SCLH)
t
100
su(SDA)
3)
2)
3)
t
SDA data hold time
0
0
900
h(SDA)
t
t
r(SDA)
ns
SDA and SCL rise time
SDA and SCL fall time
1000
300
20+0.1C
20+0.1C
300
300
b
b
r(SCL)
t
t
f(SDA)
f(SCL)
t
START condition hold time
4.0
4.7
4.0
4.7
0.6
0.6
0.6
1.3
h(STA)
µs
t
Repeated START condition setup time
STOP condition setup time
su(STA)
su(STO)
t
µs
µs
pF
t
STOP to START condition time (bus free)
Capacitive load for each bus line
w(STO:STA)
C
400
400
b
2
Typical Application with I C Bus and Timing Diagram 4)
Figure 109.
V
V
DD
DD
4.7kΩ
4.7kΩ
100Ω
100Ω
SDAI
SCLI
2
I C BUS
ST72XXX
REPEATED START
START
t
t
su(STA)
w(STO:STA)
START
SDA
t
t
r(SDA)
f(SDA)
STOP
t
t
h(SDA)
su(SDA)
SCK
t
t
t
t
t
t
h(STA)
w(SCKH)
w(SCKL)
r(SCK)
su(STO)
f(SCK)
Notes:
1. Data based on standard I C protocol requirement, not tested in production.
2
2. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined
region of the falling edge of SCL.
3. The maximum hold time of the START condition has only to be met if the interface does not stretch the low period of
SCL signal.
4. Measurement points are done at CMOS levels: 0.3xV and 0.7xV
.
DD
DD
2
2
5. At 4MHz f
, max.I C speed (400kHz) is not achievable. In this case, max. I C speed will be approximately 260KHz.
CPU
191/215
ST72F521, ST72521B
COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d)
The following table gives the values to be written in
2
the I2CCCR register to obtain the required I C
SCL line frequency.
Table 28. SCL Frequency Table
I2CCCR Value
f
f
=4 MHz.
f
=8 MHz.
SCL
CPU
CPU
V
= 4.1 V
V
= 5 V
V
= 4.1 V
V
= 5 V
DD
(kHz)
DD
DD
DD
R =3.3kΩ R =4.7kΩ R =3.3kΩ R =4.7kΩ R =3.3kΩ R =4.7kΩ R =3.3kΩ R =4.7kΩ
P
P
P
P
P
P
P
P
400
300
200
100
50
NA
NA
NA
NA
83h
85h
8Ah
24h
4Ch
FFh
83
83h
85h
8Ah
24h
4Ch
FFh
83h
85h
8Ah
23h
4Ch
FFh
NA
NA
NA
NA
85h
89h
23h
4Ch
FFh
83h
10h
24h
5Fh
83h
10h
24h
5Fh
83h
10h
24h
5Fh
83h
10h
24h
5Fh
20
Legend:
R = External pull-up resistance
P
2
f
= I C speed
SCL
NA = Not achievable
Note:
– For speeds around 200 kHz, achieved speed can have 5% tolerance
– For other speed ranges, achieved speed can have 2% tolerance
The above variations depend on the accuracy of the external components used.
12.11.3 CAN - Controller Area Network Interface
Subject to general operating condition for V , f
, and T unless otherwise specified.
A
DD OSC
Refer to I/O port characteristics for more details on the input/output alternate function characteristics
(CANTX and CANRX).
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
1)
t
CAN controller propagation time
60
ns
p(RX:TX)
Notes:
1. Data based on simulation results, not tested in production
192/215
ST72F521, ST72521B
12.12 10-BIT ADC CHARACTERISTICS
Subject to general operating conditions for V , f
, and T unless otherwise specified.
DD CPU
A
Symbol
Parameter
ADC clock frequency
Conditions
Min
0.4
3.8
Typ
Max
Unit
f
2
MHz
ADC
V
Analog reference voltage
Conversion voltage range
0.7*V ≤V
≤V
V
AREF
DD
AREF
DD
DD
V
1)
V
V
V
AREF
AIN
SSA
-40°C≤T ≤85°C range
±250
nA
Positive input leakage current for analog
input
A
Other T ranges
±1
µA
A
I
lkg
V <V | I |< 400µA
IN
SS, IN
Negative input leakage current on ro-
bust analog pins (ROM devices only)
on adjacent robust ana-
log pin
5
5
6
µA
2
-40°C≤T ≤85°C range
±250
±1
nA
Positive input leakage current for analog
input
A
Other T ranges
µA
A
I
lkg
V <V | I |< 400µA
IN
SS, IN
Negative input leakage current on ro-
on adjacent robust ana-
log pin
6
µA
2
bust analog pins (ROM devices only)
R
C
External input impedance
see
kΩ
AIN
AIN
Figure
110 and
Figure
External capacitor on analog input
pF
f
Variation freq. of analog input signal
Hz
AIN
2)3)4)
111
C
t
Internal sample and hold capacitor
Conversion time (Sample+Hold)
12
pF
ADC
7.5
µs
ADC
ADC
f
=8MHz, SPEED=0 f
=2MHz
CPU
ADC
- No of sample capacitor loading cycles
- No. of Hold conversion cycles
4
11
t
1/f
ADC
Notes:
1. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10kΩ). Data
based on characterization results, not tested in production.
2. For Flash devices: injecting negative current on any of the analog input pins significantly reduces the accuracy of any
conversion being performed on any analog input. Analog pins of flash devices can be protected against negative injection
by adding a Schottky diode (pin to ground). Injecting negative current on digital input pins degrades ADC accuracy espe-
cially if performed on a pin close to the analog input pins. Any positive injection current within the limits specified for
I
and ΣI
in Section 12.8 does not affect the ADC accuracy.
INJ(PIN)
INJ(PIN)
193/215
ST72F521, ST72521B
ADC CHARACTERISTICS (Cont’d)
1)
2)
Figure 110. R
max. vs f
with C =0pF
Figure 111. Recommended C
& R
AIN
ADC
AIN
AIN AIN values.
45
40
35
30
25
20
15
10
5
1000
Cain 10 nF
Cain 22 nF
Cain 47 nF
2 MHz
1 MHz
100
10
1
0
0.1
0
10
30
70
0.01
0.1
1
10
CPARASITIC (pF)
fAIN(KHz)
Figure 112. Typical A/D Converter Application
V
DD
ST72XXX
V
T
0.6V
R
2kΩ(max)
AIN
AINx
10-Bit A/D
V
AIN
Conversion
C
V
0.6V
AIN
T
I
C
ADC
12pF
L
±1µA
Notes:
1. C
represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad ca-
PARASITIC
pacitance (3pF). A high C
value will downgrade conversion accuracy. To remedy this, f
should be reduced.
PARASITIC
ADC
2. This graph shows that depending on the input signal variation (f ), C
can be increased for stabilization time and
AIN
AIN
decreased to allow the use of a larger serial resistor (R
.
AIN)
194/215
ST72F521, ST72521B
ADC CHARACTERISTICS (Cont’d)
12.12.1 Analog Power Supply and Reference
Pins
– Filter power to the analog power planes. It is rec-
ommended to connect capacitors, with good high
frequency characteristics, between the power
and ground lines, placing 0.1µF and optionally, if
needed 10pF capacitors as close as possible to
the ST7 power supply pins and a 1 to 10µF ca-
pacitor close to the power source (see Figure
113).
Depending on the MCU pin count, the package
may feature separate V
and V
analog
AREF
SSA
power supply pins. These pins supply power to the
A/D converter cell and function as the high and low
reference voltages for the conversion.
Separation of the digital and analog power pins al-
low board designers to improve A/D performance.
Conversion accuracy can be impacted by voltage
drops and noise in the event of heavily loaded or
badly decoupled power supply lines (see Section
12.12.2 General PCB Design Guidelines).
– The analog and digital power supplies should be
connected in a star network. Do not use a resis-
tor, as V
is used as a reference voltage by
AREF
the A/D converter and any resistance would
cause a voltage drop and a loss of accuracy.
– Properly place components and route the signal
traces on the PCB to shield the analog inputs.
Analog signals paths should run over the analog
ground plane and be as short as possible. Isolate
analog signals from digital signals that may
switch while the analog inputs are being sampled
by the A/D converter. Do not toggle digital out-
puts on the same I/O port as the A/D input being
converted.
12.12.2 General PCB Design Guidelines
To obtain best results, some general design and
layout rules should be followed when designing
the application PCB to shield the noise-sensitive,
analog physical interface from noise-generating
CMOS logic signals.
– Use separate digital and analog planes. The an-
alog ground plane should be connected to the
digital ground plane via a single point on the
PCB.
Figure 113. Power Supply Filtering
ST72XXX
1 to 10µF
0.1µF
V
V
SS
DD
ST7
DIGITAL NOISE
FILTERING
V
DD
POWER
SUPPLY
SOURCE
0.1µF
V
V
AREF
SSA
EXTERNAL
NOISE
FILTERING
195/215
ST72F521, ST72521B
10-BIT ADC CHARACTERISTICS (Cont’d)
12.12.3 ADC Accuracy
Conditions: V =5V 1)
DD
2)
Max
Symbol
|E |
Parameter
Conditions
Typ
3
Unit
1)
4
3
3
2
2
Total unadjusted error
T
1)
2
|E |
Offset error
O
1)
0.5
1
LSB
|E |
Gain Error
G
1)
|E |
Differential linearity error
CPU in run mode @ f
2 MHz.
2 MHz.
D
ADC
1)
1
|E |
Integral linearity error
CPU in run mode @ f
L
ADC
Notes:
1. ADC Accuracy vs. Negative Injection Current: Injecting negative current may reduce the accuracy of the conversion
being performed on another analog input. The effect of negative injection current on robust pins is specified in Section
12.12.
Any positive injection current within the limits specified for I
accuracy.
and ΣI
in Section 12.8 does not affect the ADC
INJ(PIN)
INJ(PIN)
2. Data based on characterization results, monitored in production to guarantee 99.73% within ± max value from -40°C
to 125°C (± 3σ distribution limits).
Figure 114. ADC Accuracy Characteristics
Digital Result ADCDR
E
G
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line
1023
1022
1021
V
– V
AREF
SSA
1LSB
= --------------------------------------------
IDEAL
1024
(2)
E =Total Unadjusted Error: maximum deviation
T
E
between the actual and the ideal transfer curves.
T
(3)
7
6
5
4
3
2
1
E =Offset Error: deviation between the first actual
O
transition and the first ideal one.
(1)
E =Gain Error: deviation between the last ideal
G
transition and the last actual one.
E
E
O
L
E =Differential Linearity Error: maximum deviation
D
between actual steps and the ideal one.
E =Integral Linearity Error: maximum deviation
L
E
between any actual transition and the end point
correlation line.
D
1 LSB
IDEAL
V
(LSB
)
in
IDEAL
0
1
2
3
4
5
6
7
1021 1022 1023 1024
V
V
SSA
AREF
196/215
ST72F521, ST72521B
13 PACKAGE CHARACTERISTICS
13.1 PACKAGE MECHANICAL DATA
Figure 115. 80-Pin Thin Quad Flat Package
mm
inches
Dim.
Min Typ Max Min Typ Max
D
A
A
1.60
0.063
0.006
D1
A2
A1 0.05
0.15 0.002
A1
b
A2 1.35 1.40 1.45 0.053 0.055 0.057
b
C
0.22 0.32 0.38 0.009 0.013 0.015
0.09 0.20 0.004 0.008
D
16.00
14.00
16.00
14.00
0.65
0.630
0.551
0.630
0.551
0.026
3.5°
e
D1
E
E1
E
E1
e
θ
0°
3.5°
7°
0°
7°
L
0.45 0.60 0.75 0.018 0.024 0.030
1.00 0.039
Number of Pins
80
c
L1
L1
L
h
N
Figure 116. 64-Pin Thin Quad Flat Package
A
mm
inches
D
Dim.
A2
Min Typ Max Min Typ Max
D1
A
1.60
0.063
0.006
A1
b
A1 0.05
0.15 0.002
A2 1.35 1.40 1.45 0.053 0.055 0.057
b
c
0.30 0.37 0.45 0.012 0.015 0.018
0.09 0.20 0.004 0.008
D
16.00
14.00
16.00
14.00
0.80
0.630
0.551
0.630
0.551
0.031
3.5°
e
D1
E
E
E1
E1
e
θ
0°
3.5°
7°
0°
7°
L
0.45 0.60 0.75 0.018 0.024 0.030
1.00 0.039
Number of Pins
64
L
L1
L1
c
N
h
197/215
ST72F521, ST72521B
PACKAGE MECHANICAL DATA (Cont’d)
Figure 117. 64-Pin Thin Quad Flat Package
mm
inches
Dim.
Min Typ Max Min Typ Max
D
A
A
1.60
0.063
0.006
D1
A2
A1 0.05
0.15 0.002
A1
A2 1.35 1.40 1.45 0.053 0.055 0.057
b
c
0.17 0.22 0.27 0.007 0.009 0.011
0.09 0.20 0.004 0.008
b
e
D
12.00
10.00
12.00
10.00
0.50
0.472
0.394
0.472
0.394
0.020
3.5°
E1
D1
E
E
E1
e
θ
0°
3.5°
7°
0°
7°
c
L1
L
0.45 0.60 0.75 0.018 0.024 0.030
1.00 0.039
Number of Pins
64
h
L1
L
N
198/215
ST72F521, ST72521B
13.2 THERMAL CHARACTERISTICS
Symbol
Ratings
Value
Unit
Package thermal resistance (junction to ambient)
TQFP80 14x14
55
47
50
R
TQFP64 14x14
TQFP64 10x10
°C/W
thJA
1)
P
Power dissipation
Maximum junction temperature
500
150
mW
°C
D
2)
T
Jmax
Notes:
1. The power dissipation is obtained from the formula P =P +P
where P
is the chip internal power (I xV
)
D
INT
PORT
INT
DD DD
and P
is the port power dissipation determined by the user.
PORT
2. The average chip-junction temperature can be obtained from the formula T = T + P x RthJA.
J
A
D
199/215
ST72F521, ST72521B
13.3 SOLDERING INFORMATION
In accordance with the RoHS European directive,
all STMicroelectronics packages will be converted
Backward and forward compatibility:
The main difference between Pb and Pb-free sol-
dering process is the temperature range.
in 2005 to lead-free technology, named ECO-
TM
PACK
(for a detailed roadmap, please refer to
TM
– ECOPACK TQFP packages are fully compat-
PCN CRP/04/744 "Lead-free Conversion Program
- Compliance with RoHS", issued November 18th,
2004).
ible with Lead (Pb) containing soldering process
(see application note AN2034)
TM
– TQFP Pb-packages are compatible with Lead-
free soldering process, nevertheless it's the cus-
tomer's duty to verify that the Pb-packages max-
imum temperature (mentioned on the Inner box
label) is compatible with their Lead-free soldering
temperature.
■ ECOPACK packages are qualified according
to the JEDEC STD-020B compliant soldering
profile.
■ Detailed information on the STMicroelectronic
TM
ECOPACK transition program is available on
www.st.com/stonline/leadfree/, with specific
technical Application notes covering the main
technical aspects related to lead-free
conversion (AN2033, AN2034, AN2035,
AN2036).
Table 29. Soldering Compatibility (wave and reflow soldering process)
Package
TQFP
Plating material devices
Pb solder paste
Pb-free solder paste
NiPdAu (Nickel-palladium-Gold)
Yes
Yes *
* Assemblers must verify that the Pb-package maximum temperature (mentioned on the Inner box label)
is compatible with their Lead-free soldering process.
200/215
ST72F521, ST72521B
14 ST72521 DEVICE CONFIGURATION AND ORDERING INFORMATION
Each device is available for production in user pro-
grammable versions (FLASH) as well as in factory
coded versions (ROM/FASTROM).
shipped to customers with a default content, while
ROM/FASTROM factory coded parts contain the
code supplied by the customer. This implies that
FLASH devices have to be configured by the cus-
tomer using the Option Bytes while the ROM/FAS-
TROM devices are factory-configured.
ST72521B devices are ROM versions. ST72P521
devices are Factory Advanced Service Technique
ROM (FASTROM) versions: they are factory-pro-
grammed HDFlash devices. FLASH devices are
14.1 FLASH OPTION BYTES
STATIC OPTION BYTE 0
STATIC OPTION BYTE 1
7
0
7
0
WDG
VD
OSCTYPE
OSCRANGE
1
0
0
0
1
1
0
0
1
1
0
1
2
1
Default
1
1
1
1
1
1
1
1
1
The option bytes allow the hardware configuration
of the microcontroller to be selected. They have no
address in the memory map and can be accessed
only in programming mode (for example using a
standard ST7 programming tool). The default con-
tent of the FLASH is fixed to FFh. To program the
FLASH devices directly using ICP, FLASH devices
are shipped to customers with the internal RC
clock source. In masked ROM devices, the option
bytes are fixed in hardware by the ROM code (see
option list).
1: Software (watchdog to be enabled by software)
OPT5 = Reserved, must be kept at default value.
OPT4:3= VD[1:0] Voltage detection
These option bits enable the voltage detection
block (LVD, and AVD) with a selected threshold for
the LVD and AVD (EVD+AVD).
Selected Low Voltage Detector
VD1
VD0
LVD and AVD Off
1
1
0
0
1
0
1
0
OPTION BYTE 0
Lowest Threshold: (V ~3V)
DD
OPT7= WDG HALT Watchdog and HALT mode
This option bit determines if a RESET is generated
when entering HALT mode while the Watchdog is
active.
0: No Reset generation when entering Halt mode
1: Reset generation when entering Halt mode
Med. Threshold (V ~3.5V)
DD
Highest Threshold (V ~4V)
DD
Caution: If the medium or low thresholds are se-
lected, the detection may occur outside the speci-
fied operating voltage range. Below 3.8V, device
operation is not guaranteed. For details on the
AVD and LVD threshold levels refer to section
12.3.2 on page 168
OPT6= WDG SW Hardware or software watchdog
This option bit selects the watchdog type.
0: Hardware (watchdog always enabled)
201/215
ST72F521, ST72521B
ST72521 DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d)
OPT2 = Reserved, must be kept at default value.
OPT5:4 = OSCTYPE[1:0] Oscillator Type
These option bits select the ST7 main clock
source type.
OPT1= PKG0 Package selection bit 0
This option bit is used to select the package (see
table in PKG1 option bit description).
OSCTYPE
Clock Source
1
0
0
1
1
0
0
1
0
1
Resonator Oscillator
Reserved
OPT0= FMP_R Flash memory read-out protection
Read-out protection, when selected, provides a
protection against Program Memory content ex-
traction and against write access to Flash memo-
ry.
Internal RC Oscillator
External Source
Erasing the option bytes when the FMP_R option
is selected causes the whole user memory to be
erased first, and the device can be reprogrammed.
Refer to Section 4.3.1 and the ST7 Flash Pro-
gramming Reference Manual for more details.
Note: Readout protection is not supported if LVD
is enabled.
OPT3:1 = OSCRANGE[2:0] Oscillator range
When the resonator oscillator type is selected,
these option bits select the resonator oscillator
current source corresponding to the frequency
range of the used resonator. Otherwise, these bits
are used to select the normal operating frequency
range.
0: Read-out protection enabled
1: Read-out protection disabled
OSCRANGE
Typ. Freq. Range
OPTION BYTE 1
2
0
0
0
0
1
0
0
1
1
0
0
1
0
1
OPT7= PKG1 Package selection bit 1
This option bit, with the PKG0 bit, selects the pack-
age.
LP
1~2MHz
2~4MHz
4~8MHz
8~16MHz
MP
MS
HS
Version
M
Selected Package
TQFP80
PKG 1 PKG 0
1
1
1
0
OPT0 = PLLOFF PLL activation
(A)R
TQFP64
This option bit activates the PLL which allows mul-
tiplication by two of the main input clock frequency.
The PLL must not be used with the internal RC os-
cillator or with external clock source. The PLL is
guaranteed only with an input frequency between
2 and 4MHz.
Note: On the chip, each I/O port has 8 pads. Pads
that are not bonded to external pins are in input
pull-up configuration after reset. The configuration
of these pads must be kept at reset state to avoid
added current consumption.
0: PLL x2 enabled
1: PLL x2 disabled
OPT6 = RSTC RESET clock cycle selection
This option bit selects the number of CPU cycles
applied during the RESET phase and when exiting
HALT mode. For resonator oscillators, it is advised
to select 4096 due to the long crystal stabilization
time.
CAUTION: the PLL can be enabled only if the
“OSC RANGE” (OPT3:1) bits are configured to
“MP - 2~4MHz”. Otherwise, the device functionali-
ty is not guaranteed.
0: Reset phase with 4096 CPU cycles
1: Reset phase with 256 CPU cycles
202/215
ST72F521, ST72521B
ST72521 DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d)
14.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE
Customer code is made up of the ROM/FAS-
TROM contents and the list of the selected options
(if any). The ROM/FASTROM contents are to be
sent on diskette, or by electronic means, with the
S19 hexadecimal file generated by the develop-
ment tool. All unused bytes must be set to FFh.
The STMicroelectronics Sales Organization will be
pleased to provide detailed information on con-
tractual points.
14.2.1 Version-Specific Sales Conditions
To satisfy the different customer requirements and
to ensure that ST Standard Microcontrollers will
consistently meet or exceed the expectations of
each Market Segment, the Codification System for
Standard Microcontrollers clearly distinguishes
products intended for use in automotive environ-
ments, from products intended for use in non-auto-
motive environments.
The selected options are communicated to
STMicroelectronics using the correctly completed
OPTION LIST appended.
Refer to application note AN1635 for information
on the counter listing returned by ST after code
has been transferred.
It is the responsibility of the Customer to select the
appropriate product for his application.
Figure 118. ROM Factory Coded Device Types
/
XXX
PACKAGE VERSION
DEVICE
Code name (defined by STMicroelectronics)
1 = Standard 0 to +70 °C
3 = Standard -40 to +125 °C
5 = Standard -10 to +85 °C
6 = Standard -40 to +85 °C
A = Automotive -40 to +85 °C
B = Automotive -40 to +105 °C
C = Automotive -40 to +125 °C
T= Plastic Thin Quad Flat Pack
ST72521BR9, ST72521BR6
ST72521BAR9, ST72521BAR6
ST72521BM9
203/215
ST72F521, ST72521B
ST72521 DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d)
ST72521B MICROCONTROLLER OPTION LIST
(Last update: December 2004)
Customer:
Address:
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact:
Phone No:
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference/ROM Code* : . . . . . . . . . . . . . . . . . . . . . . .
*The ROM code name is assigned by STMicroelectronics.
ROM code must be sent in .S19 format. .Hex extension cannot be processed.
Device Type/Memory Size/Package (check only one option):
--------------------------------- -------------------------------------
-------------------------------------
|
|
|
ROM DEVICE:
60K
32K
|
-------------------------------------
--------------------------------- -------------------------------------
TQFP80:
TQFP64 14x14: |
TQFP64 10x10: |
|
[ ] ST72521BM9
[ ] ST72521BR9
[ ] ST72521BAR9
|
|
|
[ ] ST72521BR6
[ ] ST72521BAR6
--------------------------------- -------------------------------------- -------------------------------------
|
|
|
|
DIE FORM:
60K
32K
--------------------------------- -------------------------------------- --------------------------------------
80-pin:
64-pin:
|
|
[ ]
[ ]
|
|
[ ]
Conditioning (check only one option):
------------------------------------------------------------------------ -----------------------------------------------------
|
Packaged Product
Die Product (dice tested at 25°C only)
|
------------------------------------------------------------------------ -----------------------------------------------------
[ ] Tape & Reel
[ ] Tray
|
|
|
[ ] Tape & Reel
[ ] Inked wafer
[ ] Sawn wafer on sticky foil
Version/ Temp. Range (do not check for die product). Please refer to datasheet for specific sales conditions:
-------------------------------------------
-------------------------------------------
|
|
|
|
|
|
|
|
|
----------------------------- -------------------------------------------
Automotive
----------------------------- -------------------------------------------
Temp. Range
Standard
[ ]
[ ]
[ ]
|
|
|
|
|
[ ] 0°C to +70°C
[ ] -10°C to +85°C
[ ] -40°C to +85°C
[ ] -40°C to +105°C
[ ] -40°C to +125°C
[ ]
[ ]
[ ]
Special Marking:
[ ] No
[ ] Yes "_ _ _ _ _ _ _ _ _ _ " (10 char. max)
Authorized characters are letters, digits, '.', '-', '/' and spaces only.
Clock Source Selection:
[ ] Resonator:
[ ] LP: Low power resonator (1 to 2 MHz)
[ ] MP: Medium power resonator (2 to 4 MHz)
[ ] MS: Medium speed resonator (4 to 8 MHz)
[ ] HS: High speed resonator (8 to 16 MHz)
[ ] Internal RC:
[ ] External Clock
PLL
[ ] Disabled
[ ] Enabled
LVD Reset [ ] Disabled
[ ] High threshold [ ] Med. threshold [ ] Low threshold
Reset Delay
[ ] 256 Cycles
[ ] 4096 Cycles
Watchdog Selection:
Watchdog Reset on Halt:
Readout Protection:
[ ] Software Activation
[ ] Reset
[ ] Hardware Activation
[ ] No Reset
[ ] Enabled
[ ] Disabled
Date
Signature
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Please download the latest version of this option list from:
http://www.st.com/mcu > downloads > ST7 microcontrollers > Option list
204/215
ST72F521, ST72521B
DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d)
Table 30. Orderable Flash Device Types
Flash
Part Number
Version
Package
Memory
(Kbytes)
Temp. Range
ST72F521AR6TC
ST72F521AR9TC
ST72F521R6TC
ST72F521R9TC
ST72F521M9TC
ST72F521AR6T3
ST72F521AR9T3
ST72F521R6T3
ST72F521R9T3
ST72F521M9T3
ST72F521AR6T6
ST72F521AR9T6
ST72F521R6T6
ST72F521R9T6
ST72F521M9T6
32
60
32
60
60
32
60
32
60
60
32
60
32
60
60
TQFP64 10 x 10
Automotive
-40°C +125°C
TQFP64 14 x 14
TQFP80
TQFP64 10 x 10
Standard
Standard
-40°C +125°C
-40°C +85°C
TQFP64 14 x 14
TQFP80
TQFP64 10 x 10
TQFP64 14 x 14
TQFP80
205/215
ST72F521, ST72521B
DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d)
14.3 DEVELOPMENT TOOLS
STMicroelectronics offers a range of hardware
and software development tools for the ST7 micro-
controller family. Full details of tools available for
the ST7 from third party manufacturers can be ob-
tained from the STMicroelectronics Internet site:
http//www.st.com.
and a specific demo board for ST72521
(TQFP64)
■ STxF-INDART
Flash Programming tools
■ ST7-STICK ST7 In-circuit Communication Kit, a
complete software/hardware package for
programming ST7 Flash devices. It connects to
a host PC parallel port and to the target board or
socket board via ST7 ICC connector.
Tools from these manufacturers include C compli-
ers, evaluation tools, emulators and programmers.
Emulators
Two types of emulators are available from ST for
the ST725 family:
■ ST7 DVP3 entry-level emulator offers a flexible
and modular debugging and programming
solution. SDIP42 & SDIP32 probes/adapters
are included, other packages need a specific
connection kit (refer to Table 31)
■ ICC Socket Boards provide an easy to use and
flexible means of programming ST7 Flash
devices. They can be connected to any tool that
supports the ST7 ICC interface, such as ST7
EMU3, ST7-DVP3, inDART, ST7-STICK, or
many third-party development tools.
Evaluation boards
■ ST7 EMU3 high-end emulator is delivered with
everything (probes, TEB, adapters etc.) needed
to start emulating the ST725. To configure it to
emulate other ST7 subfamily devices, the active
probe for the ST7EMU3 can be changed and
the ST7EMU3 probe is designed for easy
interchange of TEBs (Target Emulation Board).
See Table 31.
Three different Evaluation boards are available:
■ ST7232x-EVAL ST72F321/325/521 evaluation
board, with ICC connector for programming
capability. Provides direct connection to ST7-
DVP3 emulator. Supplied with daughter boards
(core module) for ST72F321, ST72F324,
ST72325 & ST72F521 (the ST72F32x chips are
not included)
In-circuit Debugging Kit
1
■ ST7MDT20-EVC/xx with CAB TQFP64 14x14
Two configurations are available from ST:
socket
1
■ STXF521-IND/USB:
Low-cost
In-Circuit
■ ST7MDT20-EVY/xx with Yamaichi TQFP64
Debugging kit from Softec Microsystems.
Includes STX-InDART/USB board (USB port)
10x10 socket
Table 31. STMicroelectronics Development Tools
Emulation
Programming
Supported
Products
ST7 DVP3 Series
ST7 EMU3 series
ICC Socket Board
Active Probe &
T.E.B.
Emulator
Connection kit
Emulator
ST7MDT20-T80/
DVP
ST72521M,
ST72F521M
ST7MDT20-T6A/
DVP
ST7MDT20M-
EMU3
ST72521AR,
ST72F521AR
1
ST7MDT20-DVP3
ST7MDT20M-TEB ST7SB20M/xx
ST7MDT20-T64/
DVP
ST72521R,
ST72F521R
Note 1: Add suffix /EU, /UK, /US for the power supply of your region.
206/215
ST72F521, ST72521B
DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d)
Table 32. Suggested List of Socket Types
Socket (supplied with ST7MDT20M-
Emulator Adapter (supplied with
ST7MDT20M-EMU3)
Device
EMU3)
TQFP64 14 x14
TQFP64 10 x10
TQFP80 14 X 14
CAB 3303262
CAB 3303351
YAMAICHI IC149-064-*75-*5
YAMAICHI IC149-080-*51-*5
YAMAICHI ICP-064-6
YAMAICHI ICP-080-7
14.3.1
Information
Socket
and
Emulator
Adapter
TQFP64 10 x 10 and TQFP80 14 x 14 and
www.cabgmbh.com for TQFP64 14 x 14)
For information on the type of socket that is sup-
plied with the emulator, refer to the suggested list
of sockets in Table 32.
Related Documentation
AN 978: ST7 Visual Develop Software Key Debug-
ging Features
Note: Before designing the board layout, it is rec-
ommended to check the overall dimensions of the
socket as they may be greater than the dimen-
sions of the device.
AN 1938: ST7 Visual Develop for ST7 Cosmic C
toolset users
AN 1939: ST7 Visual Develop for ST7 Metroworks
C toolset users
For footprint and other mechanical information
about these sockets and adapters, refer to the
manufacturer’s datasheet (www.yamaichi.de for
AN 1940: ST7 Visual Develop for ST7 Assembler
Linker toolset users
207/215
ST72F521, ST72521B
14.4 ST7 APPLICATION NOTES
Table 33. ST7 Application Notes
IDENTIFICATION DESCRIPTION
APPLICATION EXAMPLES
AN1658
AN1720
AN1755
AN1756
SERIAL NUMBERING IMPLEMENTATION
MANAGING THE READ-OUT PROTECTION IN FLASH MICROCONTROLLERS
A HIGH RESOLUTION/PRECISION THERMOMETER USING ST7 AND NE555
CHOOSING A DALI IMPLEMENTATION STRATEGY WITH ST7DALI
EXAMPLE DRIVERS
SCI COMMUNICATION BETWEEN ST7 AND PC
AN 969
AN 970
AN 971
AN 972
AN 973
AN 974
AN 976
AN 979
AN 980
AN1017
AN1041
AN1042
AN1044
AN1045
AN1046
AN1047
AN1048
AN1078
AN1082
AN1083
AN1105
AN1129
SPI COMMUNICATION BETWEEN ST7 AND EEPROM
I²C COMMUNICATION BETWEEN ST7 AND M24CXX EEPROM
ST7 SOFTWARE SPI MASTER COMMUNICATION
SCI SOFTWARE COMMUNICATION WITH A PC USING ST72251 16-BIT TIMER
REAL TIME CLOCK WITH ST7 TIMER OUTPUT COMPARE
DRIVING A BUZZER THROUGH ST7 TIMER PWM FUNCTION
DRIVING AN ANALOG KEYBOARD WITH THE ST7 ADC
ST7 KEYPAD DECODING TECHNIQUES, IMPLEMENTING WAKE-UP ON KEYSTROKE
USING THE ST7 UNIVERSAL SERIAL BUS MICROCONTROLLER
USING ST7 PWM SIGNAL TO GENERATE ANALOG OUTPUT (SINUSOÏD)
ST7 ROUTINE FOR I²C SLAVE MODE MANAGEMENT
MULTIPLE INTERRUPT SOURCES MANAGEMENT FOR ST7 MCUS
ST7 S/W IMPLEMENTATION OF I²C BUS MASTER
UART EMULATION SOFTWARE
MANAGING RECEPTION ERRORS WITH THE ST7 SCI PERIPHERALS
ST7 SOFTWARE LCD DRIVER
PWM DUTY CYCLE SWITCH IMPLEMENTING TRUE 0% & 100% DUTY CYCLE
DESCRIPTION OF THE ST72141 MOTOR CONTROL PERIPHERALS REGISTERS
ST72141 BLDC MOTOR CONTROL SOFTWARE AND FLOWCHART EXAMPLE
ST7 PCAN PERIPHERAL DRIVER
PWM MANAGEMENT FOR BLDC MOTOR DRIVES USING THE ST72141
AN INTRODUCTION TO SENSORLESS BRUSHLESS DC MOTOR DRIVE APPLICATIONS
WITH THE ST72141
AN1130
AN1148
AN1149
AN1180
AN1276
AN1321
AN1325
AN1445
AN1475
AN1504
AN1602
AN1633
AN1712
AN1713
AN1753
AN1947
USING THE ST7263 FOR DESIGNING A USB MOUSE
HANDLING SUSPEND MODE ON A USB MOUSE
USING THE ST7263 KIT TO IMPLEMENT A USB GAME PAD
BLDC MOTOR START ROUTINE FOR THE ST72141 MICROCONTROLLER
USING THE ST72141 MOTOR CONTROL MCU IN SENSOR MODE
USING THE ST7 USB LOW-SPEED FIRMWARE V4.X
EMULATED 16 BIT SLAVE SPI
DEVELOPING AN ST7265X MASS STORAGE APPLICATION
STARTING A PWM SIGNAL DIRECTLY AT HIGH LEVEL USING THE ST7 16-BIT TIMER
16-BIT TIMING OPERATIONS USING ST7262 OR ST7263B ST7 USB MCUS
DEVICE FIRMWARE UPGRADE (DFU) IMPLEMENTATION IN ST7 NON-USB APPLICATIONS
GENERATING A HIGH RESOLUTION SINEWAVE USING ST7 PWMART
SMBUS SLAVE DRIVER FOR ST7 I2C PERIPHERALS
SOFTWARE UART USING 12-BIT ART
ST7MC PMAC SINE WAVE MOTOR CONTROL SOFTWARE LIBRARY
208/215
ST72F521, ST72521B
Table 33. ST7 Application Notes
IDENTIFICATION DESCRIPTION
GENERAL PURPOSE
AN1476
AN1526
AN1709
AN1752
LOW COST POWER SUPPLY FOR HOME APPLIANCES
ST7FLITE0 QUICK REFERENCE NOTE
EMC DESIGN FOR ST MICROCONTROLLERS
ST72324 QUICK REFERENCE NOTE
PRODUCT EVALUATION
AN 910
AN 990
AN1077
AN1086
AN1103
AN1150
AN1151
AN1278
PERFORMANCE BENCHMARKING
ST7 BENEFITS VERSUS INDUSTRY STANDARD
OVERVIEW OF ENHANCED CAN CONTROLLERS FOR ST7 AND ST9 MCUS
U435 CAN-DO SOLUTIONS FOR CAR MULTIPLEXING
IMPROVED B-EMF DETECTION FOR LOW SPEED, LOW VOLTAGE WITH ST72141
BENCHMARK ST72 VS PC16
PERFORMANCE COMPARISON BETWEEN ST72254 & PC16F876
LIN (LOCAL INTERCONNECT NETWORK) SOLUTIONS
PRODUCT MIGRATION
AN1131
AN1322
AN1365
AN1604
MIGRATING APPLICATIONS FROM ST72511/311/214/124 TO ST72521/321/324
MIGRATING AN APPLICATION FROM ST7263 REV.B TO ST7263B
GUIDELINES FOR MIGRATING ST72C254 APPLICATIONS TO ST72F264
HOW TO USE ST7MDT1-TRAIN WITH ST72F264
PRODUCT OPTIMIZATION
AN 982
AN1014
AN1015
AN1040
AN1070
AN1181
AN1324
AN1502
AN1529
USING ST7 WITH CERAMIC RESONATOR
HOW TO MINIMIZE THE ST7 POWER CONSUMPTION
SOFTWARE TECHNIQUES FOR IMPROVING MICROCONTROLLER EMC PERFORMANCE
MONITORING THE VBUS SIGNAL FOR USB SELF-POWERED DEVICES
ST7 CHECKSUM SELF-CHECKING CAPABILITY
ELECTROSTATIC DISCHARGE SENSITIVE MEASUREMENT
CALIBRATING THE RC OSCILLATOR OF THE ST7FLITE0 MCU USING THE MAINS
EMULATED DATA EEPROM WITH ST7 HDFLASH MEMORY
EXTENDING THE CURRENT & VOLTAGE CAPABILITY ON THE ST7265 VDDF SUPPLY
ACCURATE TIMEBASE FOR LOW-COST ST7 APPLICATIONS WITH INTERNAL RC OSCILLA-
TOR
AN1530
AN1605
AN1636
AN1828
AN1946
AN1971
USING AN ACTIVE RC TO WAKEUP THE ST7LITE0 FROM POWER SAVING MODE
UNDERSTANDING AND MINIMIZING ADC CONVERSION ERRORS
PIR (PASSIVE INFRARED) DETECTOR USING THE ST7FLITE05/09/SUPERLITE
SENSORLESS BLDC MOTOR CONTROL AND BEMF SAMPLING METHODS WITH ST7MC
ST7LITE0 MICROCONTROLLED BALLAST
PROGRAMMING AND TOOLS
AN 978
AN 983
AN 985
AN 986
AN 987
AN 988
AN 989
AN1039
AN1064
AN1071
ST7 VISUAL DEVELOP SOFTWARE KEY DEBUGGING FEATURES
KEY FEATURES OF THE COSMIC ST7 C-COMPILER PACKAGE
EXECUTING CODE IN ST7 RAM
USING THE INDIRECT ADDRESSING MODE WITH ST7
ST7 SERIAL TEST CONTROLLER PROGRAMMING
STARTING WITH ST7 ASSEMBLY TOOL CHAIN
GETTING STARTED WITH THE ST7 HIWARE C TOOLCHAIN
ST7 MATH UTILITY ROUTINES
WRITING OPTIMIZED HIWARE C LANGUAGE FOR ST7
HALF DUPLEX USB-TO-SERIAL BRIDGE USING THE ST72611 USB MICROCONTROLLER
209/215
ST72F521, ST72521B
Table 33. ST7 Application Notes
IDENTIFICATION DESCRIPTION
AN1106
TRANSLATING ASSEMBLY CODE FROM HC05 TO ST7
PROGRAMMING ST7 FLASH MICROCONTROLLERS IN REMOTE ISP MODE (IN-SITU PRO-
GRAMMING)
AN1179
AN1446
AN1477
AN1478
AN1527
AN1575
AN1576
AN1577
AN1601
AN1603
AN1635
AN1754
AN1796
AN1900
AN1904
AN1905
USING THE ST72521 EMULATOR TO DEBUG A ST72324 TARGET APPLICATION
EMULATED DATA EEPROM WITH XFLASH MEMORY
PORTING AN ST7 PANTA PROJECT TO CODEWARRIOR IDE
DEVELOPING A USB SMARTCARD READER WITH ST7SCR
ON-BOARD PROGRAMMING METHODS FOR XFLASH AND HDFLASH ST7 MCUS
IN-APPLICATION PROGRAMMING (IAP) DRIVERS FOR ST7 HDFLASH OR XFLASH MCUS
DEVICE FIRMWARE UPGRADE (DFU) IMPLEMENTATION FOR ST7 USB APPLICATIONS
SOFTWARE IMPLEMENTATION FOR ST7DALI-EVAL
USING THE ST7 USB DEVICE FIRMWARE UPGRADE DEVELOPMENT KIT (DFU-DK)
ST7 CUSTOMER ROM CODE RELEASE INFORMATION
DATA LOGGING PROGRAM FOR TESTING ST7 APPLICATIONS VIA ICC
FIELD UPDATES FOR FLASH BASED ST7 APPLICATIONS USING A PC COMM PORT
HARDWARE IMPLEMENTATION FOR ST7DALI-EVAL
ST7MC THREE-PHASE AC INDUCTION MOTOR CONTROL SOFTWARE LIBRARY
ST7MC THREE-PHASE BLDC MOTOR CONTROL SOFTWARE LIBRARY
SYSTEM OPTIMIZATION
AN1711
AN1827
AN2009
AN2030
SOFTWARE TECHNIQUES FOR COMPENSATING ST7 ADC ERRORS
IMPLEMENTATION OF SIGMA-DELTA ADC WITH ST7FLITE05/09
PWM MANAGEMENT FOR 3-PHASE BLDC MOTOR DRIVES USING THE ST7FMC
BACK EMF DETECTION DURING PWM ON TIME BY ST7MC
210/215
ST72F521, ST72521B
15 KNOWN LIMITATIONS
15.1 ALL FLASH AND ROM DEVICES
15.1.1 External RC option
The symptom does not occur when the interrupts
are handled normally, i.e.
when:
The External RC clock source option described in
previous datasheet revisions is no longer support-
ed and has been removed from this specification.
– The interrupt flag is cleared within its own inter-
rupt routine
– The interrupt flag is cleared within any interrupt
routine
15.1.2 Safe Connection of OSC1/OSC2 Pins
The OSC1 and/or OSC2 pins must not be left un-
connected otherwise the ST7 main oscillator may
start and, in this configuration, could generate an
– The interrupt flag is cleared in any part of the
code while this interrupt is disabled
f
clock frequency in excess of the allowed
If these conditions are not met, the symptom can
be avoided by implementing the following se-
quence:
OSC
maximum (>16MHz.), putting the ST7 in an un-
safe/undefined state. Refer to section 6.2 on page
25.
Perform SIM and RIM operation before and after
resetting an active interrupt request.
15.1.3 Reset pin protection with LVD Enabled
As mentioned in note 2 below Figure 103 on page
186, when the LVD is enabled, it is recommended
not to connect a pull-up resistor or capacitor. A
10nF pull-down capacitor is required to filter noise
on the reset line.
Example:
SIM
reset interrupt flag
RIM
15.1.4 Unexpected Reset Fetch
Nested interrupt context:
If an interrupt request occurs while a “POP CC” in-
struction is executed, the interrupt controller does
not recognise the source of the interrupt and, by
default, passes the RESET vector address to the
CPU.
The symptom does not occur when the interrupts
are handled normally, i.e.
when:
– The interrupt flag is cleared within its own inter-
rupt routine
Workaround
– The interrupt flag is cleared within any interrupt
routine with higher or identical priority level
To solve this issue, a “POP CC” instruction must
always be preceded by a “SIM” instruction.
– The interrupt flag is cleared in any part of the
code while this interrupt is disabled
15.1.5 Clearing active interrupts outside
interrupt routine
If these conditions are not met, the symptom can
be avoided by implementing the following se-
quence:
When an active interrupt request occurs at the
same time as the related flag is being cleared, an
unwanted reset may occur.
PUSH CC
SIM
Note: clearing the related interrupt mask will not
generate an unwanted reset
reset interrupt flag
POP CC
Concurrent interrupt context
211/215
ST72F521, ST72521B
KNOWN LIMITATIONS (Cont’d)
15.1.6 SCI Wrong Break duration
Description
15.1.7 16-bit Timer PWM Mode
In PWM mode, the first PWM pulse is missed after
writing the value FFFCh in the OC1R register
(OC1HR, OC1LR). It leads to either full or no PWM
during a period, depending on the OLVL1 and
OLVL2 settings.
A single break character is sent by setting and re-
setting the SBK bit in the SCICR2 register. In
some cases, the break character may have a long-
er duration than expected:
15.1.8 CAN Cell Limitations
- 20 bits instead of 10 bits if M=0
- 22 bits instead of 11 bits if M=1.
1
Limitation
Flash
ROM
Omitted SOF bit
x
x
In the same way, as long as the SBK bit is set,
break characters are sent to the TDO pin. This
may lead to generate one break more than expect-
ed.
CPU write access
(morethan onecycle)
corrupts CAN frame
x
x
Unexpected Mes-
sage transmission
2
x
Occurrence
The occurrence of the problem is random and pro-
portional to the baudrate. With a transmit frequen-
cy of 19200 baud (f
BRR=0xC9), the wrong break duration occurrence
is around 1%.
Bus Off State Not En-
tered
4
x
=8MHz and SCI-
CPU
3
WKPS Functionality
x
x=limitation present
Workaround
1
For details see section 10.8.5 on page 146
If this wrong duration is not compliant with the
communication protocol in the application, soft-
ware can request that an Idle line be generated
before the break character. In this case, the break
duration is always correct assuming the applica-
tion is not doing anything between the idle and the
break. This can be ensured by temporarily disa-
bling interrupts.
2
Software workaround possible using modified
WKPS bit.
3
Functionality modified for Unexpected Message
Transmission workaround in Flash.
4
Limitation present on ROM Rev W and Rev Z.
Not present in Flash and ROM Rev Y.
15.1.9 I2C Multimaster
The exact sequence is:
In multimaster configurations, if the ST7 I2C re-
ceives a START condition from another I2C mas-
ter after the START bit is set in the I2CCR register
and before the START condition is generated by
the ST7 I2C, it may ignore the START condition
from the other I2C master. In this case, the ST7
master will receive a NACK from the other device.
On reception of the NACK, ST7 can send a re-start
and Slave address to re-initiate communication
- Disable interrupts
- Reset and Set TE (IDLE request)
- Set and Reset SBK (Break Request)
- Re-enable interrupts
212/215
ST72F521, ST72521B
KNOWN LIMITATIONS (Cont’d)
15.2 ALL FLASH DEVICES
modes are critical because the I/Os PG[7:0] and
PH[7:0] are forced to output push-pull.
15.2.1 Internal RC Oscillator with LVD
Impact on the Application
The internal RC can only be used if LVD is ena-
bled.
The PG and PH I/O ports are forced to output
push-pull during three pulses on ICCDATA. In cer-
tain circumstances, this behaviour can lead to a
15.2.2 I/O behaviour during ICC mode entry
sequence
short-circuit between the I/O signals and V , V
DD
SS
Symptom
or an output signal of another application compo-
nent.
In 80-pin devices (Flash), both Port G and H are
forced to output push-pull during ICC mode entry
sequence. 80-pin ROM devices are not impacted
by this issue.
In addition, switching these I/Os to output mode
can cause the application to leave reset state, dis-
turbing the ICC communication and preventing the
user from programming the flash.
Details
To enable programming of all flash sectors, the
device must leave USER mode and be configured
in ICC mode. Once in ICC mode, the ICC protocol
enables an ST7 microcontroller to communicate
with an external controller (such as a PC). ICC
mode is entered by applying 39 pulses on the IC-
CDATA signal during reset. To enter ICC mode,
the device goes through other modes, some
15.2.3 Read-out protection with LVD
The LVD is not supported if Readout protection is
enabled.
213/215
ST72F521, ST72521B
16 REVISION HISTORY
Table 34. Revision History
Date
Revision
Description of Changes
Added Figure 82 on page 153
Reinstated “I/O behaviour during ICC mode entry sequence” on page 213
Reinstated “BUSOFF not entered” in “CAN Cell Limitations” on page 212
Added “flash only” to PC6 Iinj spec in Section 12.2 and Section 12.8
Added Note on SMbus to Section 10.7
7-Dec-2004
3
Static current consumption modified in section 12.8 on page 182
Updated footnote and Figure 103 and Figure 104 on page 186
Modified VtPOR in section 12.3.2 on page 168
4-Mar-2005
4
5
Added note 4 below Table of “CAN Cell Limitations” on page 212
Corrected MCO description in Table 1 and Section 10.2
Updated footnotes and Figure 103 and Figure 104 on page 186.
Updated soldering information in section 13.3 on page 200
Added Suffix 3 to Figure 118 on page 203
18-May-2005
Updated partnumbers in Table 30 on page 205
Added “Reset pin protection with LVD Enabled” on page 211
214/215
ST72F521, ST72521B
Notes:
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
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215/215
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