ST72532R4T1S [STMICROELECTRONICS]
8-BIT MCU WITH NESTED INTERRUPTS, EEPROM, ADC, 16-BIT TIMERS, 8-BIT PWM ART, SPI, SCI, CAN INTERFACES; 8位MCU嵌套中断， EEPROM ， ADC ， 16位定时器， 8位PWM技术， SPI ， SCI ， CAN接口
| 型号： | ST72532R4T1S |
| 厂家： | 
ST |
| 描述： | 8-BIT MCU WITH NESTED INTERRUPTS, EEPROM, ADC, 16-BIT TIMERS, 8-BIT PWM ART, SPI, SCI, CAN INTERFACES |
| 文件： | 总164页 (文件大小：1033K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ST72311R, ST72511R,
ST72512R, ST72532R
8-BIT MCU WITH NESTED INTERRUPTS, EEPROM, ADC,
16-BIT TIMERS, 8-BIT PWM ART, SPI, SCI, CAN INTERFACES
DATASHEET
■ Memories
– 16K to 60K bytes Program memory
(ROM,OTP and EPROM)
with read-out protection
2
– 256 bytes E PROM Data memory
(only on ST72532R4)
– 1024 to 2048 bytes RAM
■ Clock, Reset and Supply Management
– Enhanced reset system
– Low voltage supply supervisor
– Clock sources: crystal/ceramic resonator os-
cillator or external clock
– Beep and Clock-out capability
TQFP64
14 x 14
– 4 Power Saving Modes: Halt, Active-Halt,
Wait and Slow
■ Interrupt Management
■ 3 Communications Interfaces
– Nested interrupt controller
– SPI synchronous serial interface
– 13 interrupt vectors plus TRAP and RESET
– SCI asynchronous serial interface
– 15 external interrupt lines (on 4 vectors)
– CAN interface (except on ST72311Rx)
■ 1 Analog peripheral
– TLI dedicated top level interrupt pin
■ 48 I/O Ports
– 8-bit ADC with 8 input channels
■ Instruction Set
– 48 multifunctional bidirectional I/O lines
– 32 alternate function lines
– 8-bit data manipulation
– 12 high sink outputs
– 63 basic instructions
■ 5 Timers
– 17 main addressing modes
– 8 x 8 unsigned multiply instruction
– Configurable watchdog timer
– Real time clock timer
– True bit manipulation
– One 8-bit auto-reload timer with 4 independ-
■ Development Tools
ent PWM output channels, 2 input captures,
output compares and external clock with
event detector (except on ST725x2R4)
– Full hardware/software development package
– Two 16-bittimers with: 2 input captures, 2 out-
put compares, external clock input on one tim-
er, PWM and Pulse generator modes
Device Summary
Features
ST72511R9 ST72511R7 ST72511R6 ST72311R9 ST72311R7 ST72311R6 ST72512R4 ST72532R4
Program memory -bytes
RAM (stack) - bytes
EEPROM - bytes
60K
48K
32K
60K
48K
32K
16K
16K
1024 (256)
256
2048 (256) 1536 (256) 1024 (256) 2048 (256) 1536 (256) 1024 (256) 1024 (256)
-
-
-
-
-
-
-
watchdog, two 16-bit timers, 8-bit PWM watchdog, two 16-bit timers, 8-bit PWM watchdog, two16-bit timers,
Peripherals
ART, SPI, SCI, CAN, ADC
ART, SPI, SCI, ADC
SPI, SCI, CAN, ADC
1)
1)
Operating Supply
CPU Frequency
Operating Temperature
Packages
3.0V to 5.5V
3.0 to 5.5V
2 to 8 MHz (with 4 to 16 MHz oscillator)
-40°C to +85°C (-40°C to +105/125°C optional)
TQFP64
2 to 4 MHz
Note 1. See Section 12.3.1 on page 133 for more information on V versus f
.
DD
OSC
Rev. 2.1
February 2000
1/164
1
Table of Contents
1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2 EPROM PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3 DATA EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3 MEMORY ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.4 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.5 ACCESS ERROR HANDLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.6 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1 LOW VOLTAGE DETECTOR (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.2 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.2.2 Asynchronous External RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.2.3 Internal Low Voltage Detection RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.2.4 Internal Watchdog RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.3 LOW CONSUMPTION OSCILLATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.2 MASKING AND PROCESSING FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.3 INTERRUPTS AND LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.4 CONCURRENT & NESTED MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.5 INTERRUPT REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.2 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.3 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.4 ACTIVE-HALT AND HALT MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.4.1 ACTIVE-HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.4.2 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
8 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
8.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
8.2.1 Input Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
164
8.2.2 Output Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
8.2.3 Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
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Table of Contents
8.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8.4 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.5 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.5.1 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9 MISCELLANEOUS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9.1 I/O PORT INTERRUPT SENSITIVITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9.2 I/O PORT ALTERNATE FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9.3 MISCELLANEOUS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
10 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
10.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
10.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
10.1.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
10.1.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
10.1.4 Hardware Watchdog Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
10.1.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
10.1.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
10.1.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
10.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK TIMER (MCC/RTC) . . . . . . . 52
10.2.1 Programmable CPU Clock Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
10.2.2 Clock-out Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
10.2.3 Real Time Clock Timer (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
10.2.4 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
10.2.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
10.2.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
10.3 PWM AUTO-RELOAD TIMER (ART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
10.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
10.3.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
10.3.3 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
10.4 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
10.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
10.4.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
10.4.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
10.4.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
10.4.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
10.4.6 Summary of Timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
10.4.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
10.5 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
10.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
10.5.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
10.5.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
10.5.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
10.5.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
10.5.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
10.5.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
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ST72311R, ST72511R, ST72512R, ST72532R
10.6 SERIAL COMMUNICATIONS INTERFACE (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
10.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
10.6.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
10.6.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
10.6.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
10.6.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
10.6.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
10.6.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
10.7 CONTROLLER AREA NETWORK (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
10.7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
10.7.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
10.7.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
10.7.4 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
10.8 8-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
10.8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
10.8.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
10.8.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
10.8.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
10.8.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
10.8.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
11 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
11.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
11.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
11.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
11.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
11.1.4 Indexed (No Offset, Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
11.1.5 Indirect (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
11.1.6 Indirect Indexed (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
11.1.7 Relative mode (Direct, Indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
11.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
12 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
12.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
12.1.1 Minimum and Maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
12.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
12.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
12.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
12.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
12.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
12.2.1 Voltage Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
12.2.2 Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
12.2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
12.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
12.3.1 General Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
12.3.2 Operating Conditions with Low Voltage Detector (LVD) . . . . . . . . . . . . . . . . . . . . 134
12.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
12.4.1 RUN and SLOW Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
12.4.2 WAIT and SLOW WAIT Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
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ST72311R, ST72511R, ST72512R, ST72532R
12.4.3 HALT and ACTIVE-HALT Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
12.4.4 Supply and Clock Managers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
12.4.5 On-Chip Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
12.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
12.5.1 General Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
12.5.2 External Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
12.5.3 Crystal and Ceramic Resonator Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
12.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
12.6.1 RAM and Hardware Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
12.6.2 EEPROM Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
12.6.3 EPROM Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
12.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
12.7.1 Functional EMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
12.7.2 Absolute Electrical Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
12.7.3 ESD Pin Protection Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
12.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
12.8.1 General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
12.8.2 Output Driving Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
12.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
12.9.1 Asynchronous RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
12.9.2 VPP Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
12.10 TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
12.10.1Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
12.10.28-Bit PWM-ART Auto-Reload Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
12.10.316-Bit Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
12.11 COMMUNICATIONS INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . 149
12.11.1SPI - Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
12.11.2SCI - Serial Communications Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
12.11.3CAN - Controller Area Network Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
12.12 8-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
13 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
13.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
13.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
13.3 SOLDERING AND GLUEABILITY INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
13.4 PACKAGE/SOCKET FOOTPRINT PROPOSAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
14 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . 158
14.1 OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
14.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . 159
14.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
15 ST7 GENERIC APPLICATION NOTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
16 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
5/164
ST72311R, ST72511R, ST72512R, ST72532R
1 GENERAL DESCRIPTION
1.1 INTRODUCTION
The ST72311R, ST72511R, ST72512R and
ST72532R devices are members of the ST7 mi-
crocontroller family. They can be grouped as fol-
lows:
Under software control, all devices can be placed
in WAIT, SLOW, ACTIVE-HALT or HALT mode,
reducing power consumption when the application
is in idle or standby state.
– ST725xxR devices are designed for mid-range
applications witha CAN bus interface (Controller
Area Network)
The enhanced instruction set and addressing
modes of the ST7 offer both power and flexibility to
software developers, enabling the design of highly
efficient and compact application code. In addition
to standard 8-bit data management, all ST7 micro-
controllers feature true bit manipulation, 8x8 un-
signed multiplication and indirect addressing
modes.
– ST72311R devices target the same range of ap-
plications but without CAN interface.
All devices are based on a common industry-
standard 8-bit core, featuring an enhanced instruc-
tion set.
Figure 1. Device Block Diagram
8-BIT CORE
ALU
PROGRAM
MEMORY
(16K - 60K Bytes)
RESET
CONTROL
V
PP
RAM
TLI
(1024, 2048 Bytes)
V
V
DD
LVD
SS
EEPROM
(256 Bytes)
OSC1
OSC2
OSC
WATCHDOG
MCC/RTC
PA7:0
PORT A
(8-BIT)
PORT F
TIMER A
BEEP
PF7:0
(8-BIT)
PORT B
PB7:0
(8-BIT)
PWM ART
PORT C
PORT E
CAN
PE7:0
(8-BIT)
PC7:0
TIMER B
(8-BIT)
SPI
SCI
PORT D
8-BIT ADC
PD7:0
(8-BIT)
V
DDA
V
SSA
6/164
4
ST72311R, ST72511R, ST72512R, ST72532R
1.2 PIN DESCRIPTION
Figure 2. 64-Pin TQFP Package Pinout
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
V
V
(HS) PE4
1
(HS) PE5
2
(HS) PE6
3
(HS) PE7
4
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SS_1
DD_1
PA3
PA2
ei0
PA1
PWM3 / PB0
5
PA0
PWM2 / PB1
PWM1 / PB2
PWM0 / PB3
ARTCLK / PB4
PB5
6
ei2
ei3
PC7 / SS
7
PC6 / SCK
PC5 / MOSI
PC4 / MISO
PC3 (HS) / ICAP1_B
PC2 (HS) / ICAP2_B
PC1 / OCMP1_B
PC0 / OCMP2_B
8
9
10
11
12
13
14
15
16
PB6
PB7
AIN0 / PD0
AIN1 / PD1
ei1
V
AIN2 / PD2
AIN3 / PD3
SS_0
V
DD_0
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
(HS) 20mA high sink capability
eix associated external interrupt vector
7/164
5
ST72311R, ST72511R, ST72512R, ST72532R
PIN DESCRIPTION (Cont’d)
For external pin connection guidelines, refer to Section 12 ”ELECTRICAL CHARACTERISTICS” on page
131.
Legend / Abbreviations for Table 1:
Type:
I = input, O = output, S = supply
A = Dedicated analog input
Input level:
In/Output level: C = CMOS 0.3V /0.7V
,
DD
DD
C = CMOS 0.3V /0.7V with input trigger
T
DD
DD
Output level:
HS = 20mA high sink (on N-buffer only)
Port and control configuration:
1)
– Input:
float = floating, wpu = weak pull-up, int = interrupt , ana = analog
2)
– Output:
OD = open drain , PP = push-pull
Refer to Section 8 ”I/O PORTS” on page 38 for more details on the software configuration of the I/O ports.
The RESET configuration of each pin is shown in bold. This configuration is valid as long as the device is
in reset state.
Table 1. Device Pin Description
Pin n°
Level
Port
Input
Main
function
(after
Output
Pin Name
Alternate function
reset)
1
2
PE4 (HS)
I/O C HS
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Port E4
Port E5
Port E6
Port E7
Port B0
Port B1
Port B2
Port B3
Port B4
Port B5
Port B6
Port B7
Port D0
Port D1
Port D2
Port D3
Port D4
Port D5
Port D6
Port D7
T
PE5 (HS)
PE6 (HS)
PE7 (HS)
PB0/PWM3
PB1/PWM2
PB2/PWM1
PB3/PWM0
PB4/ARTCLK
PB5
I/O C HS
T
3
I/O C HS
T
4
I/O C HS
T
5
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
S
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
ei2
PWM Output 3
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
6
ei2
ei2
PWM Output 2
7
PWM Output 1
8
ei2
ei3
ei3
PWM Output 0
9
PWM-ART External Clock
10
11
12
13
14
15
16
17
18
19
20
21
22
23
PB6
ei3
ei3
PB7
PD0/AIN0
PD1/AIN1
PD2/AIN2
PD3/AIN3
PD4/AIN4
PD5/AIN5
PD6/AIN6
PD7/AIN7
X
X
X
X
X
X
X
X
X
ADC Analog Input 0
ADC Analog Input 1
ADC Analog Input 2
ADC Analog Input 3
ADC Analog Input 4
ADC Analog Input 5
ADC Analog Input 6
ADC Analog Input 7
X
X
X
X
X
X
X
V
V
V
Analog Power Supply Voltage
Analog Ground Voltage
DDA
SSA
S
S
Digital Main Supply Voltage
DD_3
8/164
6
ST72311R, ST72511R, ST72512R, ST72532R
Pin n°
Level
Port
Main
function
(after
Input
Output
Pin Name
Alternate function
reset)
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
V
S
Digital Ground Voltage
SS_3
PF0/MCO
I/O
I/O
I/O
I/O
I/O
I/O
C
C
C
C
C
C
X
X
X
X
X
X
X
X
ei1
ei1
ei1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Port F0
Port F1
Port F2
Port F3
Port F4
Port F5
Port F6
Port F7
Main clock output (f
/2)
T
T
T
T
T
T
OSC
PF1/BEEP
Beep signal output
PF2
PF3/OCMP2_A
PF4/OCMP1_A
PF5/ICAP2_A
PF6 (HS)/ICAP1_A
Timer A Output Compare 2
Timer A Output Compare 1
Timer A Input Capture 2
X
X
I/O C HS
X
Timer A Input Capture 1
T
PF7 (HS)/EXTCLK_A I/O C HS
X
Timer A External Clock Source
T
V
V
S
S
Digital Main Supply Voltage
Digital Ground Voltage
DD_0
SS_0
PC0/OCMP2_B
PC1/OCMP1_B
I/O
I/O
C
C
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Port C0
Port C1
Port C2
Port C3
Port C4
Port C5
Port C6
Port C7
Port A0
Port A1
Port A2
Port A3
Timer B Output Compare 2
T
X
Timer B Output Compare 1
Timer B Input Capture 2
Timer B Input Capture 1
SPI Master In / Slave Out Data
SPI Master Out / Slave In Data
SPI Serial Clock
T
PC2 (HS)/ICAP2_B I/O C HS
X
T
PC3 (HS)/ICAP1_B I/O C HS
X
T
PC4/MISO
PC5/MOSI
PC6/SCK
PC7/SS
PA0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
S
C
C
C
C
C
C
C
C
X
T
T
T
T
T
T
T
T
X
X
X
SPI Slave Select (active low)
ei0
ei0
ei0
ei0
PA1
PA2
PA3
V
V
Digital Main Supply Voltage
Digital Ground Voltage
Port A4
DD_1
SS_1
S
PA4 (HS)
PA5 (HS)
PA6 (HS)
PA7 (HS)
I/O C HS
X
X
X
X
X
X
X
X
T
T
X
X
T
I/O C HS
Port A5
T
I/O C HS
Port A6
T
I/O C HS
Port A7
T
Must be tied low in user mode. In programming
mode when available, this pin acts as the pro-
53
V
I
PP
gramming voltage input V
.
PP
54
55
56
57
RESET
NC
I/O
C
X
X
Top priority non maskable interrupt (active low)
Not Connected
NMI
I
C
X
Non maskable interrupt input pin
Digital Ground Voltage
T
V
S
SS_3
External clock mode input pull-up orcrystal/ce-
ramic resonator oscillator inverter output
3)
3)
58
OSC2
OSC1
I/O
External clock input or crystal/ceramic resona-
tor oscillator inverter input
59
60
I
V
S
Digital Main Supply Voltage
DD_3
9/164
ST72311R, ST72511R, ST72512R, ST72532R
Pin n°
Level
Port
Input
Main
function
(after
Output
Pin Name
Alternate function
reset)
61
62
63
64
PE0/TDO
I/O
I/O
I/O
I/O
C
C
C
C
X
X
X
X
X
X
X
X
X
X
Port E0
Port E1
Port E2
Port E3
SCI Transmit Data Out
SCI Receive Data In
T
T
T
T
PE1/RDI
PE2/CANTX
PE3/CANRX
CAN Transmit Data Output
CAN Receive Data Input
X
X
X
Notes:
1. In the interrupt input column, “eiX” defines the associated external interrupt vector. If the weak pull-up
column (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input,
else the configuration is floating interrupt input.
2. In the open drain output column, “T” defines a true open drain I/O (P-Buffer and protection diode to V
DD
are not implemented). See Section 8 ”I/O PORTS” on page 38 and Section 12.8 ”I/O PORT PIN CHAR-
ACTERISTICS” on page 145 for more details.
3. OSC1 and OSC2 pins connect a crystal/ceramic resonator or an external source to the on-chip oscillator
see Section 1.2 ”PIN DESCRIPTION” on page 7 and Section 12.5 ”CLOCK AND TIMING CHARACTER-
ISTICS” on page 138 for more details.
10/164
ST72311R, ST72511R, ST72512R, ST72532R
1.3 REGISTER & MEMORY MAP
As shown in the Figure 3, the MCU is capable of
addressing 64K bytes of memories and I/O regis-
ters.
60Kbytes of user program memory. The RAM
space includes up to 256 bytes for the stack from
0100h to 01FFh.
The available memory locations consist of 128
bytes of register location, up to 2Kbytes of RAM,
up to 256 bytes of data EEPROM and up to
The highest address bytes contain the user reset
and interrupt vectors.
Figure 3. Memory Map
0000h
HW Registers
0080h
(see Table 2)
007Fh
0080h
Short Addressing
RAM (zero page)
00FFh
1024 Bytes RAM
0100h
Stack
1536 Bytes RAM
(256 Bytes)
2048 Bytes RAM
087Fh
01FFh
0200h
0880h
16-bit Addressing
Reserved
0BFFh
RAM
047Fh
0C00h
Optional EEPROM
or 067Fh
or 087Fh
(256 Bytes)
0CFFh
0D00h
1000h
60 KBytes
Reserved
4000h
0FFFh
1000h
48 KBytes
8000h
Program Memory
32 KBytes
(60K, 48K, 32K, 16K Bytes)
FFDFh
C000h
16 KBytes
FFE0h
Interrupt & Reset Vectors
FFFFh
(see Table 7 on page 32)
FFFFh
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ST72311R, ST72511R, ST72512R, ST72532R
Table 2. Hardware Register Map
Register
Reset
Status
Address
Block
Register Name
Remarks
Label
1)
0000h
0001h
0002h
PADR
PADDR
PAOR
Port A Data Register
Port A Data Direction Register
Port A Option Register
00h
R/W
R/W
R/W
Port A
00h
00h
2)
0003h
Reserved Area (1 Byte)
1)
0004h
0005h
0006h
PCDR
PCDDR
PCOR
Port C Data Register
Port C Data Direction Register
Port C Option Register
00h
R/W
R/W
R/W
Port C
Port B
Port E
Port D
Port F
00h
00h
0007h
Reserved Area (1 Byte)
1)
0008h
0009h
000Ah
PBDR
PBDDR
PBOR
Port B Data Register
Port B Data Direction Register
Port B Option Register
00h
R/W
R/W
R/W
00h
00h
000Bh
Reserved Area (1 Byte)
1)
000Ch
000Dh
000Eh
PEDR
PEDDR
PEOR
Port E Data Register
Port E Data Direction Register
Port E Option Register
00h
R/W
R/W
R/W
2)
2)
00h
00h
000Fh
Reserved Area (1 Byte)
1)
0010h
0011h
0012h
PDDR
PDDDR
PDOR
Port D Data Register
Port D Data Direction Register
Port D Option Register
00h
R/W
R/W
R/W
00h
00h
0013h
Reserved Area (1 Byte)
1)
0014h
0015h
0016h
PFDR
PFDDR
PFOR
Port F Data Register
Port F Data Direction Register
Port F Option Register
00h
R/W
R/W
R/W
00h
00h
0017h
to
001Fh
Reserved Area (9 Bytes)
Miscellaneous Register 1
0020h
MISCR1
00h
R/W
0021h
0022h
0023h
SPIDR
SPICR
SPISR
SPI Data I/O Register
SPI Control Register
SPI Status Register
xxh
0xh
00h
R/W
R/W
Read Only
SPI
ITC
0024h
0025h
0026h
0027h
ISPR0
ISPR1
ISPR2
ISPR3
Interrupt Software Priority Register 0
Interrupt Software Priority Register 1
Interrupt Software Priority Register 2
Interrupt Software Priority Register 3
FFh
FFh
FFh
FFh
R/W
R/W
R/W
R/W
0028h
0029h
Reserved Area (1 Byte)
MCC
MCCSR
Main Clock Control / Status Register
01h
R/W
12/164
ST72311R, ST72511R, ST72512R, ST72532R
Register
Label
Reset
Status
Address
Block
Register Name
Remarks
002Ah
002Bh
WDGCR
WDGSR
Watchdog Control Register
Watchdog Status Register
7Fh
R/W
WATCHDOG
EEPROM
000x 000x R/W
002Ch
EECSR
Data EEPROM Control/Status Register
Reserved Area (4 Bytes)
00h
R/W
002Dh
to
0030h
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
TACR2
TACR1
TASR
TAIC1HR
TAIC1LR
TAOC1HR
TAOC1LR
TACHR
Timer A Control Register 2
Timer A Control Register 1
Timer A Status Register
Timer A Input Capture 1 High Register
Timer A Input Capture 1 Low Register
Timer A Output Compare 1 High Register
Timer A Output Compare 1 Low Register
Timer A Counter High Register
00h
00h
xxh
xxh
xxh
80h
00h
FFh
FCh
FFh
FCh
xxh
xxh
80h
00h
R/W
R/W
Read Only
Read Only
Read Only
R/W
R/W
TIMER A
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
R/W
TACLR
Timer A Counter Low Register
TAACHR
TAACLR
TAIC2HR
TAIC2LR
TAOC2HR
TAOC2LR
Timer A Alternate Counter High Register
Timer A Alternate Counter Low Register
Timer A Input Capture 2 High Register
Timer A Input Capture 2 Low Register
Timer A Output Compare 2 High Register
Timer A Output Compare 2 Low Register
R/W
0040h
MISCR2
Miscellaneous Register 2
00h
R/W
0041h
0042h
0043h
0044h
0045h
0046h
0047h
0048h
0049h
004Ah
004Bh
004Ch
004Dh
004Eh
004Fh
TBCR2
TBCR1
TBSR
TBIC1HR
TBIC1LR
TBOC1HR
TBOC1LR
TBCHR
Timer B Control Register 2
Timer B Control Register 1
Timer B Status Register
Timer B Input Capture 1 High Register
Timer B Input Capture 1 Low Register
Timer B Output Compare 1 High Register
Timer B Output Compare 1 Low Register
Timer B Counter High Register
00h
00h
xxh
xxh
xxh
80h
00h
FFh
FCh
FFh
FCh
xxh
xxh
80h
00h
R/W
R/W
Read Only
Read Only
Read Only
R/W
R/W
TIMER B
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
R/W
TBCLR
Timer B Counter Low Register
TBACHR
TBACLR
TBIC2HR
TBIC2LR
TBOC2HR
TBOC2LR
Timer B Alternate Counter High Register
Timer B Alternate Counter Low Register
Timer B Input Capture 2 High Register
Timer B Input Capture 2 Low Register
Timer B Output Compare 2 High Register
Timer B Output Compare 2 Low Register
R/W
0050h
0051h
0052h
0053h
0054h
0055h
0056h
0057h
SCISR
SCIDR
SCIBRR
SCICR1
SCICR2
SCIERPR
SCI Status Register
SCI Data Register
SCI Baud Rate Register
SCI Control Register 1
SCI Control Register 2
SCI Extended Receive Prescaler Register
Reserved area
SCI Extended Transmit Prescaler Register
C0h
xxh
Read Only
R/W
00xx xxxx R/W
xxh
00h
00h
R/W
R/W
R/W
SCI
SCIETPR
00h
R/W
13/164
ST72311R, ST72511R, ST72512R, ST72532R
Register
Label
Reset
Status
Address
Block
Register Name
Remarks
0058h
0059h
Reserved Area (2 Bytes)
005Ah
005Bh
005Ch
005Dh
005Eh
005Fh
0060h
to
CANISR
CANICR
CANCSR
CANBRPR
CANBTR
CANPSR
CAN Interrupt Status Register
CAN Interrupt Control Register
CAN Control / Status Register
CAN Baud Rate Prescaler Register
CAN Bit Timing Register
CAN Page Selection Register
First address
00h
00h
00h
00h
23h
00h
R/W
R/W
R/W
R/W
R/W
R/W
See CAN
Description
CAN
to
006Fh
Last address of CAN page X
0070h
0071h
ADCDR
ADCCSR
Data Register
Control/Status Register
xxh
00h
Read Only
R/W
ADC
0072h
0073h
0074h
0075h
0076h
PWMDCR3 PWM AR Timer Duty Cycle Register 3
PWMDCR2 PWM AR Timer Duty Cycle Register 2
PWMDCR1 PWM AR Timer Duty Cycle Register 1
PWMDCR0 PWM AR Timer Duty Cycle Register 0
00h
00h
00h
00h
00h
R/W
R/W
R/W
R/W
R/W
PWM ART
PWMCR
PWM AR Timer Control Register
0077h
0078h
0079h
ARTCSR
ARTCAR
ARTARR
Auto-Reload Timer Control/Status Register
Auto-Reload Timer Counter Access Register
Auto-Reload Timer Auto-Reload Register
00h
00h
00h
R/W
R/W
R/W
007Ah
to
Reserved Area (6 Bytes)
007Fh
Legend: x=undefined, R/W=read/write
Notes:
1. The contents of the I/O port DR registers are readable only in output configuration. In input configura-
tion, the values of the I/O pins are returned instead of the DR register contents.
2. The bits associated with unavailable pins must always keep their reset value.
14/164
ST72311R, ST72511R, ST72512R, ST72532R
2 EPROM PROGRAM MEMORY
The program memory of the OTP and EPROM de-
vices can be programmed with EPROM program-
ming tools available from STMicroelectronics
sunlight can be sufficient to cause functional fail-
ure. Extended exposure to room level fluorescent
lighting may also cause erasure.
An opaque coating (paint, tape, label, etc...)
should be placed over the package window if the
product is to be operated under these lighting con-
EPROM Erasure
EPROM devices are erased by exposure to high
intensity UV light admitted through the transparent
window. This exposure discharges the floating
gate to its initial state through induced photo cur-
rent.
ditions. Covering the window also reduces I
in
DD
power-saving modes due to photo-diode leakage
currents.
It is recommended that the EPROM devices be
kept out of direct sunlight, since the UV content of
15/164
ST72311R, ST72511R, ST72512R, ST72532R
3 DATA EEPROM
3.1 INTRODUCTION
3.2 MAIN FEATURES
The Electrically Erasable Programmable Read
Only Memory can be used as a non volatile back-
up for storing data. Using the EEPROM requires a
basic access protocol described in this chapter.
■ Up to 16 Bytes programmed in the same cycle
■ EEPROM mono-voltage (charge pump)
■ Chained erase and programming cycles
■ Internal control of the global programming cycle
duration
■ End of programming cycle interrupt flag
■ WAIT mode management
Figure 4. EEPROM Block Diagram
FALLING
EDGE
DETECTOR
EEPROM INTERRUPT
HIGH VOLTAGE
PUMP
RESERVED
EEPROM
EECSR
0
0
0
0
0
IE LAT PGM
EEPROM
ADDRESS
DECODER
ROW
4
MEMORY MATRIX
(1 ROW = 16 x 8 BITS)
DECODER
128
128
DATA
MULTIPLEXER
16 x 8 BITS
4
4
DATA LATCHES
ADDRESS BUS
DATA BUS
16/164
ST72311R, ST72511R, ST72512R, ST72532R
DATA EEPROM (Cont’d)
3.3 MEMORY ACCESS
When PGM bit is set by the software, all the previ-
ous bytes written in the data latches (up to 16) are
programmed in the EEPROM cells. The effective
high address (row) is determined by the last EEP-
ROM write sequence. To avoid wrong program-
ming, the user must take care that all the bytes
written between two programming sequences
have the same high address: only the four Least
Significant Bits of the address can change.
The Data EEPROM memory read/write access
modes are controlled by the LAT bit of the EEP-
ROM Control/Status register (EECSR). The flow-
chart in Figure 5 describes these different memory
access modes.
Read Operation (LAT=0)
The EEPROM can be read as a normal ROM loca-
tion when the LAT bit of the EECSR register is
cleared. In a read cycle, the byte to be accessed is
put on the data bus in less than 1 CPU clock cycle.
This means that reading data from EEPROM
takes the same time as reading data from
EPROM, but this memory cannot be used to exe-
cute machine code.
At the end of the programming cycle, the PGM and
LAT bits are cleared simultaneously, and an inter-
rupt is generated if the IE bit is set. The Data EEP-
ROM interrupt request is cleared by hardware
when the Data EEPROM interrupt vector is
fetched.
Note: Care should be taken during the program-
ming cycle. Writing to the same memory location
will over-program the memory (logical AND be-
tween the two write access data result) because
the data latches are only cleared at the end of the
programming cycle and by the falling edge of LAT
bit.
Write Operation (LAT=1)
To access the write mode, the LAT bit has to be
set by software (the PGM bit remains cleared).
When a write access to the EEPROM area occurs,
the value is latched inside the 16 data latches ac-
cording to its address.
It is not possible to read the latched data.
This note is ilustrated by the Figure 6.
Figure 5. Data EEPROM Programming Flowchart
READ MODE
LAT=0
WRITE MODE
LAT=1
PGM=0
PGM=0
WRITE UP TO 16 BYTES
IN EEPROM AREA
(with the same 12 MSB of the address)
READ BYTES
IN EEPROM AREA
START PROGRAMMING CYCLE
LAT=1
PGM=1 (set by software)
INTERRUPT GENERATION
IF IE=1
0
1
LAT
CLEARED BY HARDWARE
17/164
ST72311R, ST72511R, ST72512R, ST72532R
DATA EEPROM (Cont’d)
3.4 POWER SAVING MODES
Wait mode
3.5 ACCESS ERROR HANDLING
If a read access occurs while LAT=1, then the data
bus will not be driven.
The DATA EEPROM can enter WAIT mode on ex-
ecution of the WFI instruction of the microcontrol-
ler. The DATA EEPROM will immediately enter
this mode if there is no programming in progress,
otherwise the DATA EEPROM will finish the cycle
and then enter WAIT mode.
If a write access occurs while LAT=0, then the
data on the bus will not be latched.
If a programming cycle is interrupted (by software/
RESET action), the memory data will not be guar-
anteed.
Halt mode
The DATA EEPROM immediatly enters HALT
mode if the microcontroller executes the HALT in-
struction. Therefore the EEPROM will stop the
function in progress, and data may be corrupted.
Figure 6. Data EEPROM Programming Cycle
READ OPERATION NOT POSSIBLE
READ OPERATION POSSIBLE
INTERNAL
PROGRAMMING
VOLTAGE
ERASE CYCLE
WRITE CYCLE
WRITE OF
DATA LATCHES
tPROG
LAT
PGM
EEPROM INTERRUPT
18/164
ST72311R, ST72511R, ST72512R, ST72532R
DATA EEPROM (Cont’d)
3.6 REGISTER DESCRIPTION
Bit 1 = LAT Latch Access Transfer
This bit is set by software. It is cleared by hard-
ware at the end of the programming cycle. It can
only be cleared by software if PGM bit is cleared.
0: Read mode
CONTROL/STATUS REGISTER (CSR)
Read/Write
Reset Value: 0000 0000 (00h)
1: Write mode
7
0
Bit 0 = PGM Programming control and status
This bit is set by software to begin theprogramming
cycle. At the end of the programming cycle, this bit
is clearedby hardwareand aninterrupt isgenerated
if the ITE bit is set.
0
0
0
0
0
IE
LAT
PGM
Bit 7:3 = Reserved, forced by hardware to 0.
0: Programming finished or not yet started
1: Programming cycle is in progress
Bit 2 = IE Interrupt enable
This bitisset andclearedby software. Itenables the
Data EEPROM interrupt capability when the PGM
bit is cleared by hardware. The interrupt request is
automatically cleared when thesoftware enters the
interrupt routine.
Note: if the PGM bit is cleared during the program-
ming cycle, the memory data is not guaranteed
0: Interrupt disabled
1: Interrupt enabled
Table 3. DATA EEPROM Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
EECSR
IE
0
RWM
0
PGM
0
002Ch
0
0
0
0
0
Reset Value
19/164
ST72311R, ST72511R, ST72512R, ST72532R
4 CENTRAL PROCESSING UNIT
4.1 INTRODUCTION
4.3 CPU REGISTERS
This CPU has a full 8-bit architecture and contains
six internal registers allowing efficient 8-bit data
manipulation.
The 6 CPU registers shown in Figure 7 are not
present in the memory mapping and are accessed
by specific instructions.
Accumulator (A)
4.2 MAIN FEATURES
The Accumulator is an 8-bit general purpose reg-
ister used to hold operands and the results of the
arithmetic and logic calculations and to manipulate
data.
■ Enable executing 63 basic instructions
■ Fast 8-bit by 8-bit multiply
■ 17 main addressing modes (with indirect
Index Registers (X and Y)
addressing mode)
These 8-bit registers are used to create effective
addresses or as temporary storage areas for data
manipulation. (The Cross-Assembler generates a
precede instruction (PRE) to indicate that the fol-
lowing instruction refers to the Y register.)
■ Two 8-bit index registers
■ 16-bit stack pointer
■ Low power HALT and WAIT modes
■ Priority maskable hardware interrupts
■ Non-maskable software/hardware interrupts
The Y register is not affected by the interrupt auto-
matic procedures.
Program Counter (PC)
The program counter is a 16-bit register containing
the address of the next instruction to be executed
by the CPU. It is made of two 8-bit registers PCL
(Program Counter Low which is the LSB) and PCH
(Program Counter High which is the MSB).
Figure 7. CPU Registers
7
0
ACCUMULATOR
RESET VALUE = XXh
7
0
0
X INDEX REGISTER
Y INDEX REGISTER
RESET VALUE = XXh
7
RESET VALUE = XXh
PCL
8 7
PCH
15
0
PROGRAM COUNTER
RESET VALUE = RESET VECTOR @ FFFEh-FFFFh
7
1
0
1
1
I1 H I0 N Z
C
CONDITION CODE REGISTER
RESET VALUE =
8
1
7
1
X 1 X X X
0
15
STACK POINTER
RESET VALUE = STACK HIGHER ADDRESS
X = Undefined Value
20/164
ST72311R, ST72511R, ST72512R, ST72532R
CENTRAL PROCESSING UNIT (Cont’d)
Condition Code Register (CC)
Read/Write
Bit 1 = Z Zero.
This bit is set and cleared by hardware. This bit in-
dicates that the result of the last arithmetic, logical
or data manipulation is zero.
0: The result of the last operation is different from
zero.
Reset Value: 111x1xxx
7
0
1: The result of the last operation is zero.
1
1
I1
H
I0
N
Z
C
This bit is accessed by the JREQ and JRNE test
instructions.
The 8-bit Condition Code register contains the in-
terrupt masks and four flags representative of the
result of the instruction just executed. This register
can also be handled by the PUSH and POP in-
structions.
Bit 0 = C Carry/borrow.
This bit is set and cleared by hardware and soft-
ware. It indicates an overflow or an underflow has
occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.
These bits can be individually tested and/or con-
trolled by specific instructions.
Arithmetic management bits
This bit is driven by the SCF and RCF instructions
and tested by the JRC and JRNC instructions. It is
also affected by the “bit test and branch”, shift and
rotate instructions.
Bit 4 = H Half carry.
This bit is set by hardware when a carry occurs be-
tween bits 3 and 4 of the ALU during an ADD or
ADC instructions. It is reset by hardware during
the same instructions.
Interrupt management bits
Bit 5,3 = I1, I0 Interrupt.
0: No half carry has occurred.
1: An half carry has occurred.
The combination of the Iand I0 bits gives the cur-
rent interrupt software priority.
This bit is tested using the JRH or JRNH instruc-
tion. The H bit is useful in BCD arithmetic subrou-
tines.
Interrupt Software Priority
Level 0 (main)
I1
1
0
0
1
I0
0
1
0
1
Level 1
Bit 2 = N Negative.
Level 2
This bit is set and cleared by hardware. It is repre-
sentative of the result sign of the last arithmetic,
logical or data manipulation. It’s a copy of the re-
Level 3 (= interrupt disable)
These two bits are set/cleared by hardware when
entering in interrupt. The loaded value is given by
the corresponding bits in the interrupt software pri-
ority registers (IxSPR). They can be also set/
cleared by software with the RIM, SIM, IRET,
HALT, WFI and PUSH/POP instructions.
th
sult 7 bit.
0: The result of the last operation is positive or null.
1: The result of the last operation is negative
(i.e. the most significant bit is a logic 1).
This bit is accessed by the JRMI and JRPL instruc-
tions.
See the interrupt management chapter for more
details.
21/164
ST72311R, ST72511R, ST72512R, ST72532R
CENTRAL PROCESSING UNIT (Cont’d)
Stack Pointer (SP)
Read/Write
The least significant byte of the Stack Pointer
(called S) can be directly accessed by a LD in-
struction.
Reset Value: 01 FFh
Note: When the lower limit is exceeded, the Stack
Pointer wraps around to the stack upper limit, with-
out indicating the stack overflow. The previously
stored information is then overwritten and there-
fore lost. The stack also wraps in case of an under-
flow.
15
0
8
1
0
0
0
0
0
0
0
7
The stack is used to save the return address dur-
ing a subroutine call and the CPU context during
an interrupt. The user may also directly manipulate
the stack by means of the PUSH and POP instruc-
tions. In the case of an interrupt, the PCL is stored
at the first location pointed to by the SP. Then the
other registers are stored in the next locations as
shown in Figure 8
SP7
SP6
SP5
SP4
SP3
SP2
SP1 SP0
The Stack Pointer is a 16-bit register which is al-
ways pointing to the next free location in the stack.
It is then decremented after data has been pushed
onto the stack and incremented before data is
popped from the stack (see Figure 8).
– When an interrupt is received, the SP is decre-
mented and the context is pushed on the stack.
Since the stack is 256 bytes deep, the 8 most sig-
nificant bits are forced by hardware. Following an
MCU Reset, or after a Reset Stack Pointer instruc-
tion (RSP), the Stack Pointer contains its reset val-
ue (the SP7 to SP0 bits are set) which is the stack
higher address.
– On return from interrupt, the SP is incremented
and the context is popped from the stack.
A subroutine call occupies two locations and an in-
terrupt five locations in the stack area.
Figure 8. Stack Manipulation Example
CALL
Subroutine
RET
or RSP
PUSH Y
POP Y
IRET
Interrupt
Event
@ 0100h
SP
SP
SP
Y
CC
A
CC
A
CC
A
X
X
X
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
SP
SP
PCH
PCH
PCL
SP
@ 01FFh PCL
Stack Higher Address = 01FFh
0100h
Stack Lower Address =
22/164
ST72311R, ST72511R, ST72512R, ST72532R
5 SUPPLY, RESET AND CLOCK MANAGEMENT
The ST72311R, ST72511R, ST72512R and
ST72532R microcontrollers include a range of util-
ity features for securing the application in critical
situations (for example in case of a power brown-
out), and reducing the number of external compo-
nents. An overview is shown in Figure 9.
Main features
■ Main supply low voltage detection (LVD)
■ RESET Manager (RSM)
■ Low consumption resonator oscillator
Figure 9. Clock, RESET, Option and Supply Management Overview
TO
OSC2
f
OSC
MAIN CLOCK
CONTROLLER
OSCILLATOR
RESET
OSC1
FROM
WATCHDOG
PERIPHERAL
RESET
LOW VOLTAGE
DETECTOR
(LVD)
V
DD
V
SS
23/164
ST72311R, ST72511R, ST72512R, ST72532R
5.1 LOW VOLTAGE DETECTOR (LVD)
To allow the integration of power management
features in the application, the Low Voltage Detec-
tor function (LVD) generates a static reset when
– under full software control
– in static safe reset
In these conditions, secure operation is always en-
sured for the application without the need for ex-
ternal reset hardware.
the V
supply voltage is below a V reference
DD
IT-
value. This means that it secures the power-up as
well as the power-down keeping the ST7 in reset.
During a Low Voltage Detector Reset, the RESET
pin is held low, thus permitting the MCU to reset
other devices.
The V reference value for a voltage drop is lower
IT-
than the V reference value for power-on in order
IT+
to avoida parasitic reset when the MCU starts run-
ning and sinks current on the supply (hysteresis).
Notes:
The LVD Reset circuitry generates a reset when
DD
V
is below:
The LVD allows the device to be used without any
external RESET circuitry.
– V when V is rising
IT+
DD
The LVD is an optional function which can be se-
lected when ordering the device (ordering informa-
tion).
– V when V is falling
The LVD function is illustrated in Figure 10.
IT-
DD
Provided the minimum V
value (guaranteed for
DD
the oscillator frequency) is below V , the MCU
IT-
can only be in two modes:
Figure 10. Low Voltage Detector vs Reset
V
DD
V
hys
V
V
IT+
IT-
RESET
24/164
ST72311R, ST72511R, ST72512R, ST72532R
5.2 RESET SEQUENCE MANAGER (RSM)
5.2.1 Introduction
The 4096 CPU clock cycle delay allows the oscil-
lator to stabilise and ensures that recovery has
taken place from the Reset state.
The reset sequence manager includes three RE-
SET sources as shown in Figure 12:
The RESET vector fetch phase duration is 2 clock
cycles.
■ External RESET source pulse
■ Internal LVD RESET (Low Voltage Detection)
■ Internal WATCHDOG RESET
Figure 11. RESET Sequence Phases
These sources act on the RESET pin and it is al-
ways kept low during the delay phase.
RESET
The RESET service routine vector is fixed at ad-
dresses FFFEh-FFFFh in the ST7 memory map.
INTERNAL RESET
FETCH
DELAY
4096 CLOCK CYCLES
VECTOR
The basic RESET sequence consists of 3 phases
as shown in Figure 11:
■ Delay depending on the RESET source
■ 4096 CPU clock cycle delay
■ RESET vector fetch
Figure 12. Reset Block Diagram
INTERNAL
RESET
V
DD
f
CPU
R
ON
RESET
WATCHDOG RESET
LVD RESET
25/164
ST72311R, ST72511R, ST72512R, ST72532R
RESET SEQUENCE MANAGER (Cont’d)
5.2.2 Asynchronous External RESET pin
5.2.3 Internal Low Voltage Detection RESET
The RESET pin is both an input and an open-drain
Two different RESET sequences caused by the in-
ternal LVD circuitry can be distinguished:
output with integrated R
weak pull-up resistor.
ON
This pull-up has no fixed value but varies in ac-
cordance with the input voltage. It can be pulled
low by external circuitry to reset the device. See
electrical characteristics section for more details.
■ Power-On RESET
■ Voltage Drop RESET
The device RESET pin acts as an output that is
pulled low when V <V
(rising edge) or
DD
IT+
A RESET signal originating from an external
V
<V (falling edge) as shown in Figure 13.
DD
IT-
source must have a duration of at least t
in
h(RSTL)in
The LVD filters spikes on V larger than t
avoid parasitic resets.
to
order to be recognized as shown in Figure 13. This
detection is asynchronous and therefore the MCU
can enter reset state even in HALT mode.
DD
g(VDD)
5.2.4 Internal Watchdog RESET
The RESET pin is an asynchronous signal which
plays a major role in EMS performance. In a noisy
environment, it is recommended to follow the
guidelines mentioned in the electrical characteris-
tics section.
The RESET sequence generated by a internal
Watchdog counter overflow is shown in Figure 13.
Starting from the Watchdog counter underflow, the
device RESET pin acts as an output that is pulled
low during t
.
w(RSTL)out
CAUTION: this output signal as not enought ener-
gy to be used to drive external devices.
Figure 13. RESET Sequences
V
DD
V
V
IT+
IT-
WATCHDOG
RESET
LVD
RESET
SHORT EXT.
RESET
RUN
RUN
RUN
RUN
DELAY
DELAY
DELAY
t
w(RSTL)out
t
h(RSTL)in
EXTERNAL
RESET
SOURCE
RESET PIN
WATCHDOG
RESET
WATCHDOG UNDERFLOW
INTERNAL RESET (4096 TCPU
)
FETCH VECTOR
26/164
ST72311R, ST72511R, ST72512R, ST72532R
5.3 LOW CONSUMPTION OSCILLATOR
The f main clock of the ST7 can be generated
by two different source types:
■ an external source
Table 4. ST7 Clock Sources
Hardware Configuration
OSC
■ a crystal or ceramic resonator oscillators
ST7
V
The associated hardware configuration are shown
in Table 4. Refer to the electrical characteristics
section for more details.
DD
OSC1
OSC2
External Clock Source
R
OBP
In this external clock mode, a clock signal (square,
sinus or triangle) with ~50% duty cycle has to drive
the OSC1 pin while the OSC2 pin is tied to ground.
EXTERNAL
SOURCE
Crystal/Ceramic Oscillator
ST7
This oscillator (based on constant current source)
is optimized in terms of consumption and has the
advantage of producing a very accurate rate on
the main clock of the ST7.
OSC1
OSC2
When using this oscillator, the resonator and the
load capacitances have to be connected as shown
in Table 4 and have to be mounted as close as
possible to the oscillator pins in order to minimize
output distortion and start-up stabilization time.
C
C
L2
L1
LOAD
CAPACITORS
This oscillator is not stopped during the RESET
phase to avoid losing time in the oscillator start-up
phase.
These oscillators are not stopped during the
RESET phase to avoid losing time in the oscillator
start-up phase.
27/164
ST72311R, ST72511R, ST72512R, ST72532R
6 INTERRUPTS
6.1 INTRODUCTION
When an interrupt request has to be serviced:
– Normal processing is suspended at the end of
the current instruction execution.
The ST7 enhanced interrupt management pro-
vides the following features:
■ Hardware interrupts
– The PC, X, A and CC registers are saved onto
the stack.
■ Software interrupt (TRAP)
– I1 and I0 bits of CC register are set according to
the corresponding values in the ISPRx registers
of the serviced interrupt vector.
■ Nested or concurrent interrupt management
with flexible interrupt priority and level
management:
– The PC isthen loaded with the interrupt vector of
the interrupt to service and the first instruction of
the interrupt service routine is fetched (refer to
“Interrupt Mapping” table for vector addresses).
– Up to 4 software programmable nesting levels
– Up to 16 interrupt vectors fixed by hardware
– 3 non maskable events: TLI, RESET, TRAP
This interrupt management is based on:
The interrupt service routine should end with the
IRET instruction which causes the contents of the
saved registers to be recovered from the stack.
– Bit 5 and bit 3 of the CPU CC register (I1:0),
– Interrupt software priority registers (ISPRx),
Note: As a consequence of the IRET instruction,
the I1 and I0 bits will be restored from the stack
and the program in the previous level will resume.
– Fixed interrupt vector addresses located at the
high addresses of the memory map (FFE0h to
FFFFh) sorted by hardware priority order.
This enhanced interrupt controller guarantees full
upward compatibility with the standard (not nest-
ed) ST7 interrupt controller.
Table 5. Interrupt Software Priority Levels
Interrupt software priority Level
I1
1
0
0
1
I0
0
1
0
1
Level 0 (main)
Level 1
Low
6.2 MASKING AND PROCESSING FLOW
Level 2
The interrupt masking is managed by the I1 and I0
bits of the CC register and the ISPRx registers
which give the interrupt software priority level of
each interrupt vector (see Table 5). The process-
ing flow is shown in Figure 14
High
Level 3 (= interrupt disable)
Figure 14. Interrupt Processing Flowchart
PENDING
INTERRUPT
Y
Y
RESET
TLI
N
Interrupt has the same or a
lower software priority
than current one
N
I1:0
FETCH NEXT
INSTRUCTION
THE INTERRUPT
STAYS PENDING
Y
“IRET”
N
RESTORE PC, X, A, CC
FROM STACK
EXECUTE
INSTRUCTION
STACK PC, X, A, CC
LOAD I1:0 FROM INTERRUPT SW REG.
LOAD PC FROM INTERRUPT VECTOR
28/164
ST72311R, ST72511R, ST72512R, ST72532R
INTERRUPTS (Cont’d)
Servicing Pending Interrupts
I0 bits of the CC are set to disable interrupts (level
3). These sources allow the processor to exit
HALT mode.
As several interrupts can be pending at the same
time, theinterrupt to be taken into account is deter-
mined by the following two-step process:
■ TLI (Top Level Hardware Interrupt)
This hardware interrupt occurs when a specific
edge is detected on the dedicated TLI pin. Its de-
tailed specification is given in the Miscellaneous
register chapter.
– the highest software priority interrupt is serviced,
– if several interrupts have the same software pri-
ority then the interrupt with the highest hardware
priority is serviced first.
■ TRAP (Non Maskable Software Interrupt)
Figure 15 describes this decision process.
This software interrupt is serviced when the TRAP
instruction is executed. It will be serviced accord-
ing to the flowchart on Figure 14 as a TLI.
Figure 15. Priority Decision Process
PENDING
INTERRUPTS
■ RESET
The RESET source has the highest priority in the
ST7. This means that the first current routine has
the highest software priority (level 3) and the high-
est hardware priority.
Different
Same
SOFTWARE
PRIORITY
See the RESET chapter for more details.
Maskable Sources
Maskable interrupt vector sources can be serviced
if the corresponding interrupt is enabled and if its
own interrupt software priority (in ISPRx registers)
is higher than the one currently being serviced (I1
and I0 in CC register). If any of these two condi-
tions is false, the interrupt is latched and thus re-
mains pending.
HIGHEST SOFTWARE
PRIORITY SERVICED
HIGHEST HARDWARE
PRIORITY SERVICED
■ External Interrupts
When an interrupt request is not serviced immedi-
ately, it is latched and then processed when its
software priority combined with the hardware pri-
ority becomes the highest one.
External interrupts allow the processor to exit from
HALT low power mode.
External interrupt sensitivity is software selectable
through the Miscellaneous registers (MISCRx).
External interrupt triggered on edge will be latched
and the interrupt request automatically cleared
upon entering the interrupt service routine.
If several input pins of a group connected to the
same interrupt line are selected simultaneously,
these will be logically ORed.
Note 1: The hardware priority is exclusive while
the software one is not. This allows the previous
process to succeed with only one interrupt.
Note 2: RESET, TRAP and TLI are non maskable
and they can be considered as having the highest
software priority in the decision process.
■ Peripheral Interrupts
Usually the peripheral interrupts cause the MCU to
exit from HALT mode except those mentioned in
the “Interrupt Mapping” table.
A peripheral interrupt occurs when a specific flag
is set in the peripheral status registers and if the
corresponding enable bit is set in the peripheral
control register.
The general sequence for clearing an interrupt is
based on an access to the status register followed
by a read or write to an associated register.
Note: The clearing sequence resets the internal
latch. A pending interrupt (i.e. waiting for being
serviced) will therefore be lost if the clear se-
quence is executed.
Different Interrupt Vector Sources
Two interrupt source types are managed by the
ST7 interrupt controller: the non-maskable type
(RESET, TLI, TRAP) and the maskable type (ex-
ternal or from internal peripherals).
Non-Maskable Sources
These sources are processed regardless of the
state of the I1 and I0 bits of the CC register (see
Figure 14). After stacking the PC, X, A and CC
registers (except for RESET), the corresponding
vector is loaded in the PC register and the I1 and
29/164
ST72311R, ST72511R, ST72512R, ST72532R
INTERRUPTS (Cont’d)
6.3 INTERRUPTS AND LOW POWER MODES
6.4 CONCURRENT & NESTED MANAGEMENT
All interrupts allow the processor to exit the WAIT
low power mode. On the contrary, only external
and other specified interrupts allow the processor
to exit the HALT modes (see column “Exit from
HALT” in “Interrupt Mapping” table). When several
pending interrupts are present while exiting HALT
mode, the first one serviced can only be an inter-
rupt with exit from HALT mode capability and it is
selected through the same decision process
shown in Figure 15
The following Figure 16 and Figure 17 show two
different interrupt management modes. The first is
called concurrent mode and does not allow an in-
terrupt to be interrupted, unlike the nested mode in
Figure 17 The interrupt hardware priority is given
in this order from the lowest to the highest: MAIN,
IT4, IT3, IT2, IT1, IT0, TLI. The software priority is
given for each interrupt.
Warning: A stack overflow may occur without no-
tifying the software of the failure.
Note: If an interrupt, that is not able to Exit from
HALT mode, is pending with the highest priority
when exiting HALT mode, this interrupt is serviced
after the first one serviced.
Figure 16. Concurrent interrupt management
SOFTWARE
PRIORITY
LEVEL
I1
I0
TLI
3
1 1
1 1
1 1
1 1
1 1
1 1
IT0
3
IT1
IT1
3
IT2
3
IT3
3
RIM
IT4
3
MAIN
MAIN
3/0
11 / 10
10
Figure 17. Nested interrupt management
SOFTWARE
PRIORITY
LEVEL
I1
I0
TLI
3
1 1
1 1
0 0
0 1
1 1
1 1
IT0
3
IT1
IT2
IT1
2
IT2
1
IT3
3
RIM
IT4
IT4
3
MAIN
MAIN
3/0
11 / 10
10
30/164
ST72311R, ST72511R, ST72512R, ST72532R
INTERRUPTS (Cont’d)
6.5 INTERRUPT REGISTER DESCRIPTION
INTERRUPT SOFTWARE PRIORITY REGIS-
TERS (ISPRX)
CPU CC REGISTER INTERRUPT BITS
Read/Write
Read/Write (bit 7:4 of ISPR3 are read only)
Reset Values: 1111 1111 (FFh)
Reset Value: 111x 1010 (xAh)
7
0
7
0
ISPR0
ISPR1
I1_3 I0_3 I1_2 I0_2 I1_1 I0_1 I1_0 I0_0
I1_7 I0_7 I1_6 I0_6 I1_5 I0_5 I1_4 I0_4
1
1
I1
H
I0
N
Z
C
Bit 5, 3 = I1, I0 Software Interrupt Priority
ISPR2 I1_11 I0_11 I1_10 I0_10 I1_9 I0_9 I1_8 I0_8
These two bits indicate the current interrupt soft-
ware priority.
ISPR3
1
1
1
1
I1_13 I0_13 I1_12 I0_12
Interrupt Software Priority Level
I1
1
0
0
1
I0
0
1
0
1
Level 0 (main)
Level 1
Low
These four registers contain the interrupt software
priority of each interrupt vector.
Level 2
– Each interruptvector (except RESET and TRAP)
has corresponding bits in these registers where
its own software priority is stored. This corre-
spondance is shown in the following table.
High
Level 3 (= interrupt disable*)
These two bits are set/cleared by hardware when
entering in interrupt. The loaded value is given by
the corresponding bits in the interrupt software pri-
ority registers (ISPRx).
Vector address
ISPRx bits
FFFBh-FFFAh
FFF9h-FFF8h
...
I1_0 and I0_0 bits*
I1_1 and I0_1 bits
...
They can be also set/cleared by software with the
RIM, SIM, HALT, WFI, IRET and PUSH/POP in-
structions (see “Interrupt Dedicated Instruction
Set” table).
FFE1h-FFE0h
I1_13 and I0_13 bits
*Note: TLI, TRAP and RESET events are non
maskable sources and can interrupt a level 3 pro-
gram.
– Each I1_x and I0_x bit value in the ISPRx regis-
ters has the same meaning as the I1 and I0 bits
in the CC register.
– Level 0 can not be written (I1_x=1, I0_x=0). In
this case, the previously stored value is kept. (ex-
ample: previous=CFh, write=64h, result=44h)
The RESET, TRAP and TLI vectors have no soft-
ware priorities. When one is serviced, the I1 and I0
bits of the CC register are both set.
*Note: Bits in the ISPRx registers which corre-
spond to the TLI can be read and written but they
are not significant in the interrupt process man-
agement.
Caution: If the I1_x and I0_x bits are modified
while the interrupt x is executed the following be-
haviour has to be considered: If the interrupt x is
still pending (new interrupt or flag not cleared) and
the new software priority is higher than the previ-
ous one, the interrupt x is re-entered. Otherwise,
the software priority stays unchanged up to the
next interrupt request (after the IRET of the inter-
rupt x).
31/164
ST72311R, ST72511R, ST72512R, ST72532R
INTERRUPTS (Cont’d)
Table 6. Dedicated Interrupt Instruction Set
Instruction
New Description
Entering Halt mode
Function/Example
I1
H
I0
N
Z
C
HALT
IRET
JRM
1
0
Interrupt routine return
Jump if I1:0=11
Pop CC, A, X, PC
I1:0=11 ?
I1
H
I0
N
Z
C
JRNM
POP CC
RIM
Jump if I1:0<>11
I1:0<>11 ?
Pop CC from the Stack
Enable interrupt (level 0 set)
Disable interrupt (level 3 set)
Software trap
Mem => CC
I1
1
1
1
1
H
I0
0
1
1
0
N
Z
C
Load 10 in I1:0 of CC
Load 11 in I1:0 of CC
Software NMI
SIM
TRAP
WFI
Wait for interrupt
Note: During the execution of an interrupt routine, the HALT, POPCC, RIM, SIM and WFI instructions change the current
software priority up to the next IRET instruction or one of the previously mentioned instructions.
In order not to lose the current software priority level, the RIM, SIM, HALT, WFI and POP CC instructions should never
be used in an interrupt routine.
Table 7. Interrupt Mapping
Exit
from
HALT
Source
Block
Register Priority
Address
Vector
N°
Description
Label
Order
RESET
TRAP
TLI
Reset
yes
no
FFFEh-FFFFh
FFFCh-FFFDh
FFFAh-FFFBh
FFF8h-FFF9h
FFF6h-FFF7h
FFF4h-FFF5h
FFF2h-FFF3h
FFF0h-FFF1h
Highest
Priority
N/A
Software Interrupt
0
1
2
3
4
5
External Top Level Interrupt
Main Clock Controller Time Base Interrupt
External Interrupt Port A3..0
External Interrupt Port F2..0
External Interrupt Port B3..0
External Interrupt Port B7..4
MISCR2
MCCSR
yes
MCC/RTC
ei0
ei1
N/A
ei2
ei3
6
CAN
CAN Peripheral Interrupts
CANISR
FFEEh-FFEFh
7
8
SPI
SPI Peripheral Interrupts
TIMER A Peripheral Interrupts
TIMER B Peripheral Interrupts
SCI Peripheral Interrupts
EEPROM Interrupt
SPISR
TASR
FFECh-FFEDh
FFEAh-FFEBh
FFE8h-FFE9h
FFE6h-FFE7h
FFE4h-FFE5h
FFE2h-FFE3h
FFE0h-FFE1h
no
TIMER A
TIMER B
SCI
9
TBSR
10
11
12
13
SCISR
EECSR
EEPROM
Not Used
Lowest
Priority
PWM ART
PWM ART Overflow Interrupt
ARTCSR
Yes
32/164
ST72311R, ST72511R, ST72512R, ST72532R
INTERRUPTS (Cont’d)
Table 8. Nested Interrupts Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
ei1
ei0
CAN
SCI
MCC/RTC
TLI
ei2
0024h
0025h
0026h
0027h
ISPR0
Reset Value
I1_3
1
I0_3
1
I1_2
1
I0_2
1
I1_1
1
I0_1
1
1
1
SPI
ei3
ISPR1
Reset Value
I1_7
1
I0_7
1
I1_6
1
I0_6
1
I1_5
1
I0_5
1
I1_4
1
I0_4
1
EEPROM
TIMER B
TIMER A
ISPR2
Reset Value
I1_11
1
I0_11
1
I1_10
1
I0_10
1
I1_9
1
I0_9
1
I1_8
1
I0_8
1
PWMART
Not Used
ISPR3
Reset Value
I1_13
1
I0_13
1
I1_12
1
I0_12
1
1
1
1
1
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ST72311R, ST72511R, ST72512R, ST72532R
7 POWER SAVING MODES
7.1 INTRODUCTION
7.2 SLOW MODE
To give a large measure of flexibility to the applica-
tion in terms of power consumption, four main
power saving modes are implemented in the ST7
(see Figure 18): SLOW, WAIT (SLOW WAIT), AC-
TIVE HALT and HALT.
This mode has two targets:
– Toreduce powerconsumption by decreasingthe
internal clock in the device,
– To adapt the internal clock frequency (f
the available supply voltage.
) to
CPU
After a RESET the normal operating mode is se-
lected by default (RUN mode). This mode drives
the device (CPU and embedded peripherals) by
means of a master clock which is based on the
SLOW mode is controlled by three bits in the
MISCR1 register: the SMS bit which enables or
disables Slow mode and two CPx bits which select
the internal slow frequency (f
).
CPU
main oscillator frequency divided by 2 (f
).
CPU
In this mode, the oscillator frequency can be divid-
ed by 4, 8, 16 or 32 instead of 2 in normal operat-
ing mode. The CPU and peripherals are clocked at
this lower frequency.
From RUN mode, the different power saving
modes may be selected by setting the relevant
register bits or by calling the specific ST7 software
instruction whose action depends on the the oscil-
lator status.
Note: SLOW-WAIT mode is activated when enter-
ring the WAIT mode while the device is already in
SLOW mode.
Figure 18. Power Saving Mode Transitions
Figure 19. SLOW Mode Clock Transitions
High
RUN
f
/4
f
/8
f
/2
OSC
OSC
OSC
f
f
CPU
SLOW
WAIT
/2
OSC
00
01
CP1:0
SMS
SLOW WAIT
ACTIVE HALT
HALT
NORMAL RUN MODE
REQUEST
NEW SLOW
FREQUENCY
REQUEST
Low
POWER CONSUMPTION
34/164
ST72311R, ST72511R, ST72512R, ST72532R
Figure 20. WAIT Mode Flow-chart
POWER SAVING MODES (Cont’d)
7.3 WAIT MODE
WAIT mode places the MCU in a low power con-
sumption mode by stopping the CPU.
This power saving mode is selected by calling the
‘WFI’ instruction.
OSCILLATOR
PERIPHERALS
CPU
ON
ON
OFF
10
WFI INSTRUCTION
I[1:0] BITS
All peripherals remain active. During WAIT mode,
the I[1:0] bits of the CC register are forced to ‘10’,
to enable all interrupts. All other registers and
memory remain unchanged. The MCU remains in
WAIT mode until an interrupt or RESET occurs,
whereupon the Program Counter branches to the
starting address of the interrupt or Reset service
routine.
N
RESET
Y
N
INTERRUPT
The MCU will remain in WAIT mode until a Reset
or an Interrupt occurs, causing it to wake up.
Y
OSCILLATOR
PERIPHERALS
CPU
ON
OFF
ON
10
Refer to Figure 20.
I[1:0] BITS
4096 CPU CLOCK CYCLE
DELAY
OSCILLATOR
PERIPHERALS
CPU
ON
ON
ON
I[1:0] BITS
XX 1)
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Note:
1. Before servicing an interrupt, the CC register is
pushed on the stack. The I[1:0] bits of the CC reg-
ister are set to the current software priority level of
the interrupt routine and recovered when the CC
register is popped.
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ST72311R, ST72511R, ST72512R, ST72532R
POWER SAVING MODES (Cont’d)
7.4 ACTIVE-HALT AND HALT MODES
Figure 21. ACTIVE-HALT Timing Overview
ACTIVE-HALT and HALT modes are the two low-
est power consumption modes of the MCU. They
are both entered by executing the ‘HALT’ instruc-
tion. The decision to enter either in ACTIVE-HALT
or HALT mode is given by the MCC/RTC interrupt
enable flag (OIE bit in MCCSR register).
ACTIVE
HALT
4096 CPU CYCLE
RUN
RUN
DELAY
RESET
OR
HALT
INSTRUCTION
[MCCSR.OIE=1]
INTERRUPT
FETCH
VECTOR
MCCSR Power Saving Mode entered when HALT
OIE bit
instruction is executed
HALT mode
ACTIVE-HALT mode
Figure 22. ACTIVE-HALT Mode Flow-chart
0
1
OSCILLATOR
PERIPHERALS 1)
CPU
ON
OFF
OFF
10
HALT INSTRUCTION
(MCCSR.OIE=1)
7.4.1 ACTIVE-HALT MODE
I[1:0] BITS
ACTIVE-HALT mode is the lowest power con-
sumption mode of the MCU with a real time clock
available. It is entered by executing the ‘HALT’ in-
struction when the OIE bit of the Main Clock Con-
troller Status register (MCCSR) is set (see Section
10.2 on page 52 for more details on the MCCSR
register).
N
RESET
Y
N
INTERRUPT 2)
The MCU can exit ACTIVE-HALT mode on recep-
tion of either an MCC/RTC interrupt, a specific in-
terrupt (see Table 7, “Interrupt Mapping,” on
page 32) or a RESET. When exiting ACTIVE-
HALT mode by means of a RESET or an interrupt,
a 4096 CPU cycle delay occurs. After the start up
delay, the CPU resumes operation by servicing
the interrupt or by fetching the reset vector which
woke it up (see Figure 22).
Y
OSCILLATOR
PERIPHERALS
CPU
ON
OFF
ON
I[1:0] BITS
XX 3)
4096 CPU CLOCK CYCLE
DELAY
When entering ACTIVE-HALT mode, the I[1:0] bits
in the CC register are forced to ‘10’ to enable inter-
rupts. Therefore, if an interrupt is pending, the
MCU wakes up immediately.
OSCILLATOR
PERIPHERALS
CPU
ON
ON
ON
I[1:0] BITS
XX 3)
In ACTIVE-HALT mode, only the main oscillator
and its associated counter (MCC/RTC) are run-
ning to keep a wake-up time base. All other periph-
erals are not clocked except those which get their
clock supply from another clock generator (such
as external or auxiliary oscillator).
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Notes:
1. Peripheral clocked with an external clock source
The safeguard against staying locked in ACTIVE-
HALT mode is provided by the oscillator interrupt.
can still be active.
2. Only the MCC/RTC interrupt and some specific
interrupts can exit the MCU from ACTIVE-HALT
mode (such as external interrupt). Refer to
Table 7, “Interrupt Mapping,” on page 32 for more
details.
Note: As soon as the interrupt capability of one of
the oscillators is selected (MCCSR.OIE bit set),
entering ACTIVE-HALT mode while the Watchdog
is active does not generate a RESET.
This means that the device cannot spend more
than a defined delay in this power saving mode.
3. Before servicing an interrupt, the CC register is
pushed on the stack. The I[1:0] bits of the CC reg-
ister are set to the current software priority level of
the interrupt routine and restored when the CC
register is popped.
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ST72311R, ST72511R, ST72512R, ST72532R
Figure 24. HALT Mode Flow-chart
POWER SAVING MODES (Cont’d)
7.4.2 HALT MODE
The HALT mode is the lowest power consumption
mode of the MCU. It is entered by executing the
‘HALT’ instruction when the OIE bit of the Main
Clock Controller Status register (MCCSR) is
cleared (see Section 10.2 on page 52 for more de-
tails on the MCCSR register).
HALT INSTRUCTION
(MCCSR.OIE=0)
ENABLE
WATCHDOG
0
DISABLE
WDGHALT 1)
1
The MCU can exit HALT mode on reception of ei-
ther a specific interrupt (see Table 7, “Interrupt
Mapping,” on page 32) or a RESET. When exiting
HALT mode by means of a RESET or an interrupt,
the oscillator is immediately turned on and the
4096 CPU cycle delay is used to stabilize the os-
cillator. After the start up delay, the CPU resumes
operation by servicing the interrupt or by fetching
the reset vector which woke it up (see Figure 24).
WATCHDOG
RESET
OSCILLATOR
OFF
PERIPHERALS 2)
CPU
OFF
OFF
10
I[1:0] BITS
When entering HALT mode, the I bit in the CC reg-
ister is forced to 0 to enable interrupts. Therefore,
if an interrupt is pending, the MCU wakes immedi-
ately.
N
RESET
Y
N
INTERRUPT 3)
In HALT mode, the main oscillator is turned off
causing all internal processing to be stopped, in-
cluding the operation of the on-chip peripherals.
All peripherals are not clocked except the ones
which get their clock supply from another clock
generator (such as an external or auxiliary oscilla-
tor).
Y
OSCILLATOR
PERIPHERALS
CPU
ON
OFF
ON
I[1:0] BITS
XX 4)
4096 CPU CLOCK CYCLE
DELAY
The compatibility of Watchdog operation with
HALT mode is configured by the “WDGHALT” op-
tion bit of the option byte. The HALT instruction
when executed while the Watchdog system is en-
abled, can generate a Watchdog RESET (see
Section 14.1 on page 158 for more details).
OSCILLATOR
PERIPHERALS
CPU
ON
ON
ON
I[1:0] BITS
XX 4)
Figure 23. HALT Timing Overview
FETCH RESET VECTOR
OR SERVICE INTERRUPT
4096 CPU CYCLE
RUN
HALT
RUN
DELAY
Notes:
RESET
OR
INTERRUPT
1. WDGHALT is an option bit. See option byte sec-
tion for more details.
HALT
INSTRUCTION
[MCCSR.OIE=0]
FETCH
VECTOR
2. Peripheral clocked with an external clock source
can still be active.
3. Only some specific interrupts can exit the MCU
from HALT mode (such as external interrupt). Re-
fer to Table 7, “Interrupt Mapping,” on page 32 for
more details.
4. Before servicing an interrupt, the CC register is
pushed on the stack. The I[1:0] bits of the CC reg-
ister are set to the current software priority level of
the interrupt routine and recovered when the CC
register is popped.
37/164
ST72311R, ST72511R, ST72512R, ST72532R
8 I/O PORTS
8.1 INTRODUCTION
programmable using the sensitivity bits in the Mis-
cellaneous register.
The I/O ports offer different functional modes:
– transfer of data through digitalinputs and outputs
Each external interrupt vector is linked to a dedi-
cated group of I/O port pins (see pinout description
and interrupt section). If several input pins are se-
lected simultaneously as interrupt source, these
are logically ANDed. For this reason if one of the
interrupt pins is tied low, it masks the other ones.
and for specific pins:
– external interrupt generation
– alternate signal input/output for the on-chip pe-
ripherals.
An I/O port contains up to 8 pins. Each pin can be
programmed independently as digital input (with or
without interrupt generation) or digital output.
In case of a floating input with interrupt configura-
tion, special care must be taken when changing
the configuration (see Figure 26).
The external interrupts are hardware interrupts,
which means that the request latch (not accessible
directly by the application) is automatically cleared
when the corresponding interrupt vector is
fetched. To clear an unwanted pending interrupt
by software, the sensitivity bits in the Miscellane-
ous register must be modified.
8.2 FUNCTIONAL DESCRIPTION
Each port has 2 main registers:
– Data Register (DR)
– Data Direction Register (DDR)
and one optional register:
– Option Register (OR)
8.2.2 Output Modes
The output configuration is selected by setting the
corresponding DDR register bit. In this case, writ-
ing the DR register applies this digital value to the
I/O pin through the latch. Then reading the DR reg-
ister returns the previously stored value.
Each I/O pin may be programmed using the corre-
sponding register bits in the DDR and OR regis-
ters: bit X corresponding to pin X of the port. The
same correspondence is used for the DR register.
The following description takes into account the
OR register, (for specific ports which do not pro-
vide this register refer to the I/O Port Implementa-
tion section). The generic I/O block diagram is
shown in Figure 25
Two different output modes can be selected by
software through the OR register: Output push-pull
and open-drain.
DR register value and output pin status:
8.2.1 Input Modes
DR
0
Push-pull
Open-drain
Vss
V
The input configuration is selected by clearing the
corresponding DDR register bit.
SS
1
V
Floating
DD
In this case, reading the DR register returns the
digital value applied to the external I/O pin.
8.2.3 Alternate Functions
When an on-chip peripheral is configured to use a
pin, the alternate function is automatically select-
ed. This alternate function takes priority over the
standard I/O programming.
Different input modes can be selected by software
through the OR register.
Notes:
1. Writing the DR register modifies the latch value
but does not affect the pin status.
When the signal is coming from an on-chip periph-
eral, the I/O pin is automatically configured in out-
put mode (push-pull or open drain according to the
peripheral).
2. When switching from input to output mode, the
DR register has to be written first to drive the cor-
rect level on the pin as soon as the port is config-
ured as an output.
When the signal is going to an on-chip peripheral,
the I/O pin must be configured in input mode. In
this case, the pin state is also digitally readable by
addressing the DR register.
External interrupt function
When an I/O is configured as Input with Interrupt,
an event on this I/O can generate anexternal inter-
rupt request to the CPU.
Note: Input pull-up configuration can cause unex-
pected value at the input of the alternate peripheral
input. When an on-chip peripheral use a pin as in-
put and output, this pin has to be configured in in-
put floating mode.
Each pin can independently generate an interrupt
request. The interrupt sensitivity is independently
38/164
ST72311R, ST72511R, ST72512R, ST72532R
I/O PORTS (Cont’d)
Figure 25. I/O Port General Block Diagram
ALTERNATE
OUTPUT
1
0
REGISTER
ACCESS
P-BUFFER
(see table below)
V
DD
ALTERNATE
ENABLE
PULL-UP
(see table below)
DR
V
DD
DDR
PULL-UP
CONDITION
PAD
OR
If implemented
OR SEL
DDR SEL
DR SEL
N-BUFFER
DIODES
(see table below)
ANALOG
INPUT
CMOS
SCHMITT
TRIGGER
1
0
ALTERNATE
INPUT
EXTERNAL
INTERRUPT
SOURCE (ei )
FROM
OTHER
BITS
x
POLARITY
SELECTION
Table 9. I/O Port Mode Options
Configuration Mode
Diodes
Pull-Up
P-Buffer
to V
to V
SS
DD
Floating with/without Interrupt
Pull-up with/without Interrupt
Push-pull
Off
On
Input
Off
On
On
Off
NI
On
Off
NI
Output
Open Drain (logic level)
True Open Drain
NI (see note)
Legend: NI - not implemented
Off - implemented not activated
On - implemented and activated
Note: The diode to V
is not implemented in the
DD
true open drain pads. A local protection between
the pad and V is implemented to protect the de-
SS
vice against positive stress.
39/164
ST72311R, ST72511R, ST72512R, ST72532R
I/O PORTS (Cont’d)
Table 10. I/O Port Configurations
Hardware Configuration
DR REGISTER ACCESS
NOT IMPLEMENTED IN
TRUE OPEN DRAIN
I/O PORTS
V
DD
PULL-UP
CONDITION
R
PU
DR
REGISTER
W
R
DATABUS
PAD
ALTERNATE INPUT
FROM
OTHER
PINS
EXTERNAL INTERRUPT
SOURCE (ei )
x
INTERRUPT
CONDITION
POLARITY
SELECTION
ANALOG INPUT
NOT IMPLEMENTED IN
TRUE OPEN DRAIN
I/O PORTS
DR REGISTER ACCESS
V
DD
R
PU
R/W
DR
REGISTER
DATA BUS
PAD
ALTERNATE
ENABLE
ALTERNATE
OUTPUT
NOT IMPLEMENTED IN
TRUE OPEN DRAIN
I/O PORTS
DR REGISTER ACCESS
V
DD
R
PU
R/W
DR
REGISTER
DATA BUS
PAD
ALTERNATE
ENABLE
ALTERNATE
OUTPUT
Notes:
1. When the I/O port is in input configuration and the associated alternate function is enabled as an output,
reading the DR register will read the alternate function output status.
2. When the I/O port is in output configuration and the associated alternate function is enabled as an input,
the alternate function reads the pin status given by the DR register content.
40/164
ST72311R, ST72511R, ST72512R, ST72532R
I/O PORTS (Cont’d)
CAUTION: The alternate function must not be ac-
tivated as long as the pin is configured as input
with interrupt, in order to avoid generating spurious
interrupts.
Standard Ports
PA5:4, PC7:0, PD7:0, PE7:3, PE1:0, PF7:3
MODE
DDR
OR
Analog alternate function
floating input
pull-up input
0
0
1
1
0
1
0
1
When the pin is used as an ADC input, the I/O
must be configured as floating input. The analog
multiplexer (controlled by the ADC registers)
switches the analog voltage present on the select-
ed pin to the common analog rail which is connect-
ed to the ADC input.
open drain output
push-pull output
Interrupt Ports
PA2:0, PB7:5, PB2:0, PF1:0 (with pull-up)
It is recommended not to change the voltage level
or loading on any port pin while conversion is in
progress. Furthermore it is recommended not to
have clocking pins located close to a selected an-
alog pin.
MODE
DDR
OR
floating input
0
0
1
1
0
1
0
1
pull-up interrupt input
open drain output
push-pull output
WARNING: The analog input voltage level must
be within the limits stated in the absolute maxi-
mum ratings.
PA3, PB4, PB3, PF2 (without pull-up)
8.3 I/O PORT IMPLEMENTATION
MODE
DDR
OR
The hardware implementation on each I/O port de-
pends onthe settings in the DDR and OR registers
and specificfeature of the I/O port such as ADC In-
put or true open drain.
floating input
0
0
1
1
0
1
0
1
floating interrupt input
open drain output
push-pull output
Switching these I/O ports from one state to anoth-
er should be done in a sequence that prevents un-
wanted side effects. Recommended safe transi-
tions are illustrated in Figure 26 Other transitions
are potentially risky and should be avoided, since
they are likely to present unwanted side-effects
such as spurious interrupt generation.
True Open Drain Ports
PA7:6
MODE
DDR
floating input
0
1
Figure 26. Interrupt I/O Port State Transitions
open drain (high sink ports)
01
00
10
11
Pull-up Input Port (CANTX requirement)
PE2
INPUT
floating/pull-up
interrupt
INPUT
floating
(reset state)
OUTPUT
open-drain
OUTPUT
push-pull
MODE
= DDR, OR
XX
pull-up input
The I/O port register configurations are summa-
rized as follows.
41/164
ST72311R, ST72511R, ST72512R, ST72532R
I/O PORTS (Cont’d)
8.4 LOW POWER MODES
8.5 INTERRUPTS
The external interrupt event generates an interrupt
if the corresponding configuration is selected with
DDR and OR registers and the interrupt mask in
the CC register is not active (RIM instruction).
Mode
WAIT
HALT
Description
No effect on I/O ports. External interrupts
cause the device to exit from WAIT mode.
No effect on I/O ports. External interrupts
cause the device to exit from HALT mode.
Enable Exit
Control from
Exit
from
Halt
Event
Flag
Interrupt Event
Bit
Wait
External interrupt on
selected external
event
DDRx
ORx
-
Yes
Yes
Table 11. Port Configuration
Input
Output
Port
Pin name
OR = 0
OR = 1
OR = 0
OR = 1
High-Sink
PA7:6
floating
true open-drain
Yes
PA5:4
floating
floating
floating
floating
floating
floating
floating
floating
pull-up
open drain
open drain
open drain
open drain
open drain
open drain
open drain
open drain
push-pull
push-pull
push-pull
push-pull
push-pull
push-pull
push-pull
push-pull
Port A
Port B
PA3
floating interrupt
pull-up interrupt
floating interrupt
pull-up interrupt
pull-up
PA2:0
No
PB4, PB3
PB7:5, PB2:0
PC7:0
Port C
Port D
PC3:2 only
No
PD7:0
pull-up
PE7:3, PE1:0
PE2
pull-up
PE7:4 only
No
Port E
pull-up input only *
PF7:3
floating
floating
floating
pull-up
open drain
open drain
open drain
push-pull
push-pull
push-pull
PF7:6 only
Port F
PF2
floating interrupt
pull-up interrupt
No
PF1:0
* Note: when the CANTX alternate function is selected the IO port operates in output push-pull mode.
42/164
ST72311R, ST72511R, ST72512R, ST72532R
I/O PORTS (Cont’d)
8.5.1 Register Description
DATA REGISTER (DR)
OPTION REGISTER (OR)
Port x Data Register
PxDR with x = A, B, C, D, E or F.
Port x Option Register
PxOR with x = A, B, C, D, E or F.
Read/Write
Read/Write
Reset Value: 0000 0000 (00h)
Reset Value: 0000 0000 (00h)
7
0
7
0
D7
D6
D5
D4
D3
D2
D1
D0
O7
O6
O5
O4
O3
O2
O1
O0
Bit 7:0 = D[7:0] Data register 8 bits.
Bit 7:0 = O[7:0] Option register 8 bits.
The DR register has a specific behaviour accord-
ing to the selected input/output configuration. Writ-
ing the DR register is always taken into account
even if the pin is configured as an input; this allows
to always have the expected level on the pin when
toggling to output mode. Reading the DR register
returns either the DR register latch content (pin
configured as output) or the digital value applied to
the I/O pin (pin configured as input).
For specific I/O pins, this register is not implement-
ed. In this case the DDR register is enough to se-
lect the I/O pin configuration.
The OR register allows to distinguish: in input
mode if the pull-up with interrupt capability or the
basic pull-up configuration is selected, in output
mode if the push-pull or open drain configuration is
selected.
Each bit is set and cleared by software.
Input mode:
DATA DIRECTION REGISTER (DDR)
0: floating input
Port x Data Direction Register
PxDDR with x = A, B, C, D, E or F.
1: pull-up input with or without interrupt
Output mode:
0: output open drain (with P-Buffer unactivated)
1: output push-pull
Read/Write
Reset Value: 0000 0000 (00h)
7
0
DD7
DD6
DD5
DD4
DD3
DD2
DD1
DD0
Bit 7:0 = DD[7:0] Data direction register 8 bits.
The DDR register gives the input/output direction
configuration of the pins. Each bits is set and
cleared by software.
0: Input mode
1: Output mode
43/164
ST72311R, ST72511R, ST72512R, ST72532R
I/O PORTS (Cont’d)
Table 12. I/O Port Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
Reset Value
of all IO port registers
0
0
0
0
0
0
0
0
0000h
0001h
0002h
0004h
0005h
0006h
0008h
0009h
000Ah
000Ch
000Dh
000Eh
0010h
0011h
0012h
0014h
0015h
0016h
PADR
PADDR
PAOR
PCDR
PCDDR
PCOR
PBDR
PBDDR
PBOR
PEDR
MSB
MSB
MSB
MSB
MSB
MSB
LSB
LSB
LSB
LSB
LSB
LSB
PEDDR
PEOR
PDDR
PDDDR
PDOR
PFDR
PFDDR
PFOR
44/164
ST72311R, ST72511R, ST72512R, ST72532R
9.2 I/O PORT ALTERNATE FUNCTIONS
9 MISCELLANEOUS REGISTERS
The miscellaneous registers allow control over
several features such as the external interrupts or
the I/Oalternate functions.
The MISCR registers allow to manage four I/O port
miscellaneous alternate functions:
■ Main clock signal (f
■ A Beep signal output on PF1 (with three
/2) output on PF0
OSC
9.1 I/O PORT INTERRUPT SENSITIVITY
The external interrupt sensitivity is controlled by
the IPA, IPB and ISxx bits of the Miscellaneous
registers (Figure 27). This control allows to have
up to 4 fully independent external interrupt source
sensitivities.
selectable audio frequencies)
■ A TLI management on a dedicated pin
■ A SPI SS pin internal control to use the PC7 I/O
port function while the SPI is active.
These functions are described in details in the
Section 9.3 ”MISCELLANEOUS REGISTERS” on
page 46.
Each external interrupt source can be generated
on four (or five) different events on the pin:
■ Falling edge
■ Rising edge
■ Falling and rising edge
■ Falling edge and low level
■ Rising edge and high level (only for ei0 and ei2)
To guarantee correct functionality, the sensitivity
bits in the MISCR registers must be modified only
when the I1 and I0 bits of the CC register are both
set to 1 (level 3). See I/O port register and Miscel-
laneous register descriptions for more details on
the programming.
Figure 27. External Interrupt Sources vs MISCR
ei0
PA3
MISCR1
IS20 IS21
INTERRUPT
SOURCE
PA2
SOURCES
PA1
PA0
SENSITIVITY
CONTROL
MISCR2.IPA
ei1
INTERRUPT
SOURCE
PF2
SOURCES
SOURCES
SOURCES
PF1
PF0
ei2
PB3
PB2
PB1
PB0
MISCR1
INTERRUPT
SOURCE
IS10
IS11
SENSITIVITY
CONTROL
MISCR2.IPB
ei3
PB7
PB6
PB5
PB4
INTERRUPT
SOURCE
45/164
ST72311R, ST72511R, ST72512R, ST72532R
MISCELLANEOUS REGISTERS (Cont’d)
9.3 MISCELLANEOUS REGISTERS
Bit 4:3 = IS2[1:0] ei0 and ei1 sensitivity
The interrupt sensitivity, defined using the IS2[1:0]
bits, is applied to the following external interrupts:
MISCELLANEOUS REGISTER 1 (MISCR1)
Read/Write
- ei0 (port A3..0)
Reset Value: 0000 0000 (00h)
External Interrupt Sensitivity
IS21 IS20
7
0
MISCR2.IPA=0
MISCR2.IPA=1
Falling edge &
low level
Rising edge
& high level
IS11 IS10 MCO IS21 IS20 CP1 CP0 SMS
0
0
0
1
1
1
0
1
Rising edge only
Falling edge only
Falling edge only
Rising edge only
Bit 7:6 = IS1[1:0] ei2 and ei3 sensitivity
The interrupt sensitivity, defined using the IS1[1:0]
bits, is applied to the following external interrupts:
- ei2 (port B3..0)
Rising and falling edge
- ei1 (port F2..0)
IS21 IS20
External Interrupt Sensitivity
External Interrupt Sensitivity
IS11 IS10
0
0
1
1
0
1
0
1
Falling edge & low level
Rising edge only
MISCR2.IPB=0
MISCR2.IPB=1
Falling edge &
low level
Rising edge
& high level
Falling edge only
0
0
Rising and falling edge
0
1
1
1
0
1
Rising edge only
Falling edge only
Falling edge only
Rising edge only
These 2 bits can be written only when I1 and I0 of
the CC register are both set to 1 (level 3).
Rising and falling edge
Bit 2:1 = CP[1:0] CPU clock prescaler
- ei3 (port B7..4)
These bits select the CPU clock prescaler which is
applied in the different slow modes. Their action is
conditioned by the setting of the SMS bit. These
two bits are set and cleared by software
IS11 IS10
External Interrupt Sensitivity
0
0
1
1
0
1
0
1
Falling edge & low level
Rising edge only
f
in SLOW mode
CP1
CP0
CPU
Falling edge only
f
f
/ 4
/ 8
0
1
0
1
0
0
1
1
OSC
OSC
Rising and falling edge
These 2 bits can be written only when I1 and I0 of
the CC register are both set to 1 (level 3).
f
/ 16
/ 32
OSC
f
OSC
Bit 5 = MCO Main clock out selection
This bit enables the MCO alternate function on the
PF0 I/O port. It is set and cleared by software.
0: MCO alternate function disabled (I/O pin free for
general-purpose I/O)
Bit 0 = SMS Slow mode select
This bit is set and cleared by software.
0: Normal mode. f = fOSC / 2
CPU
1: Slow mode. f
is given by CP1, CP0
CPU
1: MCO alternate function enabled (f
port)
/2on I/O
OSC
See Section 7.2 ”SLOW MODE” on page 34 and
Section 10.2 ”MAIN CLOCK CONTROLLER
WITH REAL TIME CLOCK TIMER (MCC/RTC)”
on page 52 for more details.
Note: To reduce power consumption, the MCO
function is not active in ACTIVE-HALT mode.
46/164
ST72311R, ST72511R, ST72512R, ST72532R
MISCELLANEOUS REGISTERS (Cont’d)
MISCELLANEOUS REGISTER 2 (MISCR2)
Read/Write
Bit 3 = TLIS TLI sensitivity
This bit allows to toggle the TLI edge sensitivity. It
can be set and cleared by software only when
TLIE bit is cleared.
Reset Value: 0000 0000 (00h)
0: Falling edge
1: Rising edge
7
0
IPA
IPB BC1 BC0 TLIS TLIE SSM SSI
Bit 2 = TLIE TLI enable
This bit allows to enable or disable the TLI capabil-
ity on the dedicated pin. It is set and cleared by
software.
Bit 7 = IPA Interrupt polarity for port A
This bit is used to invert the sensitivity of the port A
[3:0] external interrupts. It is set and cleared by
software.
0: TLI disabled
1: TLI enabled
Note: a parasitic interrupt can be generated when
clearing the TLIE bit.
0: No sensitivity inversion
1: Sensitivity inversion
See Section 9.1 ”I/O PORT INTERRUPT SENSI-
TIVITY” on page 45 and the description of the IS2x
bits of the MISCR1 register for more details.
Bit 1 = SSM SS mode selection
This bit is set and cleared by software.
0: Normal mode - the level of the SPI SS signal is
input from the external SS pin.
1: I/O mode (PC7), the level of the SPI SS signal is
read from the SSI bit.
Bit 6 = IPB Interrupt polarity for port B
This bit is used to invert the sensitivity of the port B
[3:0] external interrupts. It is set and cleared by
software.
Bit 0 = SSI SS internal mode
0: No sensitivity inversion
This bit replaces pin SS of the SPI when bit SSM is
set to 1. (see SPI description). It is set and cleared
by software.
1: Sensitivity inversion
See Section 9.1 ”I/O PORT INTERRUPT SENSI-
TIVITY” on page 45 and the description of the IS1x
bits of the MISCR1 register for more details.
Bit 5:4 = BC[1:0] Beep control
These 2 bits select the PF1 pin beep capability.
BC1
BC0
Beep mode with f
=16MHz
OSC
0
0
1
1
0
1
0
1
Off
~2-KHz
Output
Beep signal
~1-KHz
~50% duty cycle
~500-Hz
The beep output signal is available in ACTIVE-
HALT mode but has to be disabled to reduce the
consumption.
47/164
ST72311R, ST72511R, ST72512R, ST72532R
MISCELLANEOUS REGISTERS (Cont’d)
Table 13. Miscellaneous Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
MISCR1
Reset Value
IS11
0
IS10
0
MCO
0
IS21
0
IS20
0
CP1
0
CP0
0
SMS
0
0020h
0040h
MISCR2
Reset Value
IPA
0
IPB
0
BC1
0
BC0
0
TLIS
0
TLIE
0
SSM
0
SSI
0
48/164
ST72311R, ST72511R, ST72512R, ST72532R
10 ON-CHIP PERIPHERALS
10.1 WATCHDOG TIMER (WDG)
10.1.1 Introduction
■ Hardware Watchdog selectable by option byte
■ Watchdog Reset indicated by status flag (in
The Watchdog timer is used to detect the occur-
rence of a software fault, usually generated by ex-
ternal interference or by unforeseen logical condi-
tions, which causes the application program to
abandon its normal sequence. The Watchdog cir-
cuit generates an MCU reset on expiry of a pro-
grammed time period, unless the program refresh-
es the counter’s contents before the T6 bit be-
comes cleared.
versions with Safe Reset option only)
10.1.3 Functional Description
The counter value stored in the CR register (bits
T[6:0]), is decremented every 12,288 machine cy-
cles, and the length of the timeout period can be
programmed by the user in 64 increments.
10.1.2 Main Features
If the watchdog is activated (the WDGA bit is set)
and when the 7-bit timer (bits T[6:0]) rolls over
from 40h to 3Fh (T6 becomes cleared), it initiates
a reset cycle pulling low the reset pin for typically
500ns.
■ Programmable timer (64 increments of 12288
CPU cycles)
■ Programmable reset
■ Reset (if watchdog activated) after a HALT
instruction or when the T6 bit reaches zero
Figure 28. Watchdog Block Diagram
RESET
WATCHDOG CONTROL REGISTER (CR)
T5 T0
T6
WDGA
T1
T4
T2
T3
7-BIT DOWNCOUNTER
CLOCK DIVIDER
f
CPU
÷12288
49/164
ST72311R, ST72511R, ST72512R, ST72532R
WATCHDOG TIMER (Cont’d)
The application program must write in the CR reg-
ister at regular intervals during normal operation to
prevent an MCU reset. The value to be stored in
the CR register must be between FFh and C0h
(see Table 14 .Watchdog Timing (fCPU = 8 MHz)):
10.1.7 Register Description
CONTROL REGISTER (CR)
Read/Write
Reset Value: 0111 1111 (7Fh)
– The WDGA bit is set (watchdog enabled)
7
0
– The T6 bit is set to prevent generating an imme-
diate reset
WDGA T6
T5
T4
T3
T2
T1
T0
– The T[5:0] bits contain the number of increments
which represents the time delay before the
watchdog produces a reset.
Bit 7 = WDGA Activation bit.
This bit is set by software and only cleared by
hardware after a reset. When WDGA = 1, the
watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled
Table 14.Watchdog Timing (f
= 8 MHz)
CPU
CR Register
initial value
WDG timeout period
(ms)
Max
Min
FFh
C0h
98.304
1.536
Note: This bit is not used if the hardware watch-
dog option is enabled by option byte.
Bit 6:0 = T[6:0] 7-bit timer (MSB to LSB).
These bits contain the decremented value. A reset
is produced when it rolls over from 40h to 3Fh (T6
becomes cleared).
Notes: Following a reset, the watchdog is disa-
bled. Once activated it cannot be disabled, except
by a reset.
The T6 bit can be used to generate a software re-
set (the WDGA bit is set and the T6 bit is cleared).
STATUS REGISTER (SR)
Read/Write
If the watchdog is activated, the HALT instruction
will generate a Reset.
Reset Value*: 0000 0000 (00h)
10.1.4 Hardware Watchdog Option
7
-
0
If Hardware Watchdog is selected by option byte,
the watchdog is always active and the WDGA bit in
the CR is not used.
-
-
-
-
-
-
WDOGF
Refer to the device-specific Option Byte descrip-
tion.
Bit 0 = WDOGF Watchdog flag.
This bit is set by a watchdog reset and cleared by
software or a power on/off reset. This bit is useful
for distinguishing power/on off or external reset
and watchdog reset.
10.1.5 Low Power Modes
Mode
Description
0: No Watchdog reset occurred
1: Watchdog reset occurred
WAIT
No effect on Watchdog.
Immediate reset generation as soon as
the HALT instruction is executed if the
Watchdog is activated (WDGA bit is
set).
* Only by software and power on/off reset
HALT
Note: This register is not used in versions without
LVD Reset.
10.1.6 Interrupts
None.
50/164
ST72311R, ST72511R, ST72512R, ST72532R
WATCHDOG TIMER (Cond’t)
Table 15. Watchdog Timer Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
WDGCR
Reset Value
WDGA
0
T6
1
T5
1
T4
1
T3
1
T2
1
T1
1
T0
1
002Ah
002Bh
WDGSR
Reset Value
-
0
-
0
-
0
-
0
-
0
-
0
-
0
WDOGF
0
51/164
ST72311R, ST72511R, ST72512R, ST72532R
10.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK TIMER (MCC/RTC)
The Main Clock Controller consists of three differ-
ent functions:
■ a programmable CPU clock prescaler
10.2.2 Clock-out Capability
The clock-out capability is an alternate function of
an I/O port pin that outputs a f
/2 clock to drive
OSC
external devices. It is controlled by the MCO bit in
the MISCR1 register.
CAUTION: When selected, the clock out pin sus-
pends the clock during ACTIVE-HALT mode.
■ a clock-out signal to supply external devices
■ a real time clock timer with interrupt capability
Each function can be used independently and si-
multaneously.
10.2.3 Real Time Clock Timer (RTC)
10.2.1 Programmable CPU Clock Prescaler
The counter of the real time clock timer allows an
interrupt to be generated based on an accurate
real time clock. Four different time bases depend-
The programmable CPU clock prescaler supplies
the clock for the ST7 CPU and its internal periph-
erals. It manages SLOW power saving mode (See
Section 7.2 ”SLOW MODE” on page 34 for more
details).
ing directly on f
are available. The whole func-
OSC
tionality is controlled by four bits of the MCCSR
register: TB[1:0], OIE and OIF.
The prescaler selects the f
cy and is controlled by three bits in the MISCR1
register: CP[1:0] and SMS.
main clock frequen-
When the RTC interrupt is enabled (OIE bit set),
the ST7 enters ACTIVE-HALT mode when the
HALT instruction is executed. See Section 7.4
”ACTIVE-HALT AND HALT MODES” on page 36
for more details.
CPU
CAUTION: The prescaler does not act on the CAN
peripheral clock source. This peripheral is always
supplied by the f
/2 clock source.
OSC
Figure 29. Main Clock Controller (MCC/RTC) Block Diagram
CLOCK TO CAN
PERIPHERAL
PORT
ALTERNATE
FUNCTION
MCO
f
/2
OSC
MISCR1
-
-
MCO
-
-
CP1 CP0 SMS
f
OSC
DIV2, 4, 8, 16
DIV 2
CPU CLOCK
TO CPU AND
PERIPHERALS
f
CPU
RTC
COUNTER
MCCSR
0
0
0
0
TB1 TB0 OIE OIF
MCC/RTC INTERRUPT
52/164
ST72311R, ST72511R, ST72512R, ST72532R
MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK TIMER (Cont’d)
10.2.4 Register Description
Bit 0 = OIF Oscillator interrupt flag
This bit is set by hardware and cleared by software
reading the CSR register. It indicates when set
that the main oscillator has reached the selected
elapsed time (TB1:0).
MISCELLANEOUS REGISTER 1 (MISCR1)
See “MISCELLANEOUS REGISTERS” Section.
MAIN CLOCK CONTROL/STATUS REGISTER
(MCCSR)
0: Timeout not reached
1: Timeout reached
Read/Write
CAUTION: The BRES and BSET instructions
must not be used on the MCCSR register to avoid
unintentionally clearing the OIF bit.
Reset Value: 0000 0001 (01h)
7
0
0
10.2.5 Low Power Modes
0
0
0
TB1
TB0
OIE
OIF
Mode
Description
No effect on MCC/RTC peripheral.
MCC/RTC interrupt cause the device to exit
from WAIT mode.
WAIT
Bit 7:4 = Reserved, always read as 0.
No effect on MCC/RTC counter (OIE bit is
Bit 3:2 = TB[1:0] Time base control
ACTIVE- set), the registers are frozen.
HALT
MCC/RTC interrupt cause the device to exit
These bits select the programmable divider time
base. They are set and cleared by software.
from ACTIVE-HALT mode.
MCC/RTC counter and registers are frozen.
MCC/RTC operation resumes when the
MCU is woken up by an interrupt with “exit
from HALT” capability.
Time Base
Counter
HALT
TB1 TB0
Prescaler
f
=8MHz
f
=16MHz
OSC
OSC
32000
64000
4ms
8ms
2ms
4ms
0
0
1
1
0
1
0
1
10.2.6 Interrupts
The MCC/RTC interrupt event generates an inter-
rupt if the OIE bit of the MCCSR register is set and
the interrupt mask in the CC register is not active
(RIM instruction).
160000
400000
20ms
50ms
10ms
25ms
A modification of the time base is taken into ac-
count at the end of the current period (previously
set) to avoid an unwanted time shift. This allows to
use this time base as a real time clock.
Enable Exit
Control from
Exit
from
Halt
Event
Flag
Interrupt Event
Bit
Wait
Time base overflow
event
1)
OIF
OIE
Yes
No
Bit 1 = OIE Oscillator interrupt enable
This bit set and cleared by software.
0: Oscillator interrupt disabled
1: Oscillator interrupt enabled
This interrupt can be used to exit from ACTIVE-
HALT mode.
Note:
1. The MCC/RTC interrupt allows to exit from AC-
TIVE-HALT mode, not from HALT mode.
When this bit is set, calling the ST7 software HALT
instruction enters the ACTIVE-HALT power saving
mode
.
Table 16. MCC/RTC Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
MCCSR
Reset Value
TB1
0
TB0
0
OIE
0
OIF
1
0029h
0
0
0
0
53/164
ST72311R, ST72511R, ST72512R, ST72532R
10.3 PWM AUTO-RELOAD TIMER (ART)
10.3.1 Introduction
The Pulse Width Modulated Auto-Reload Timer
on-chip peripheral consists of an 8-bit auto reload
counter with compare capabilities and of a 7-bit
prescaler clock source.
The two first modes can be used together with a
single counter frequency.
The timer can be used to wake up the MCU from
WAIT and HALT modes.
These resources allow three possible operating
modes:
– Generation of up to 4 independent PWM signals
– Output compare and Time base interrupt
– External event detector
Figure 30. PWM Auto-Reload Timer Block Diagram
OCRx
DCRx
OEx
OPx
PWMCR
REGISTER
REGISTER
LOAD
PORT
ALTERNATE
FUNCTION
POLARITY
CONTROL
PWMx
COMPARE
8-BIT COUNTER
(CAR REGISTER)
ARR
REGISTER
LOAD
f
EXT
ARTCLK
f
CPU
f
COUNTER
MUX
f
INPUT
PROGRAMMABLE
PRESCALER
ARTCSR
EXCL CC2
CC1
CC0
TCE FCRL OIE
OVF
OVF INTERRUPT
54/164
ST72311R, ST72511R, ST72512R, ST72532R
PWM AUTO-RELOAD TIMER (Cont’d)
10.3.2 Functional Description
Counter
When TCE is set, the counter runs at the rate of
the selected clock source.
The free running 8-bit counter is fed by the output
of the prescaler, and is incremented on every ris-
ing edge of the clock signal.
Counter and Prescaler Initialization
After RESET, the counter and the prescaler are
It is possible to read or write the contents of the
counter on the fly by reading or writing the Counter
Access register (CAR).
cleared and f
= f
.
INPUT
CPU
The counter can be initialized by:
– Writing to the ARR register and then setting the
FCRL (Force Counter Re-Load) and the TCE
(Timer Counter Enable) bits in the CSR register.
When a counter overflow occurs, the counter is
automatically reloaded with the contents of the
ARR register (the prescaler is not affected).
– Writing to the CAR counter access register,
Counter clock and prescaler
In both cases the 7-bit prescaler is also cleared,
whereupon counting will start from a known value.
The counter clock frequency is given by:
CC[2:0]
f
= f
/ 2
COUNTER
INPUT
Direct access to the prescaler is not possible.
The timer counter’s input clock (f
) feeds the
INPUT
Output compare control
7-bit programmable prescaler, which selects one
of the 8 available taps of the prescaler, as defined
by CC[2:0] bits in the Control/Status Register
(CSR). Thus the division factor of the prescaler
The timer compare function is based on four differ-
ent comparisons with the counter (one for each
PWMx output). Each comparison is made be-
tween the counter value and an output compare
register (OCRx) value. This OCRx register can not
be accessed directly, it is loaded from the duty cy-
cle register (DCRx) at each overflow of the coun-
ter.
n
can be set to 2 (where n = 0, 1,..7).
This f
frequency source is selected through
INPUT
the EXCL bit of the CSR register and can be either
the f or an external input frequency f
.
EXT
CPU
The clock input to the counter is enabled by the
TCE (Timer Counter Enable) bit in the CSR regis-
ter. When TCE is reset, the counter is stopped and
the prescaler and counter contents are frozen.
This double buffering method avoids glitch gener-
ation when changing the duty cycle on the fly.
Figure 31. Output compare control
fCOUNTER
ARR=FDh
FFh
COUNTER
OCRx
FDh
FEh
FDh
FEh
FFh
FDh
FEh
FFh
FEh
FDh
DCRx
FEh
FDh
PWMx
55/164
ST72311R, ST72511R, ST72512R, ST72532R
PWM AUTO-RELOAD TIMER (Cont’d)
Independent PWM signal generation
OPx (output polarity) bit in the PWMCR register.
When the counter reaches the value contained in
one of the output compare register (OCRx) the
corresponding PWMx pin level is restored.
This mode allows up to four Pulse Width Modulat-
ed signals to be generated on the PWMx output
pins with minimum core processing overhead.
This function is stopped during HALT mode.
It should be noted that the reload values will also
affect the value and the resolution of the duty cycle
of the PWM output signal. To obtain a signal on a
PWMx pin, the contents of the OCRx register must
be greater than the contents of the ARR register.
Each PWMx output signal can be selected inde-
pendently using the corresponding OEx bit in the
PWM Control register (PWMCR). When this bit is
set, the corresponding I/O pin is configured as out-
put push-pull alternate function.
The maximum available resolution for the PWMx
duty cycle is:
The PWM signals all have the same frequency
which is controlled by the counter period and the
ARR register value.
Resolution = 1 / (256 - ARR)
Note: To get the maximum resolution (1/256), the
ARR register must be 0. With this maximum reso-
lution, 0% and 100% can be obtained by changing
the polarity.
f
= f
/ (256 - ARR)
PWM
COUNTER
When a counter overflow occurs, the PWMx pin
level is changed depending on the corresponding
Figure 32. PWM Auto-reload Timer Function
255
DUTY CYCLE
REGISTER
(DCRx)
AUTO-RELOAD
REGISTER
(ARR)
000
t
WITH OEx=1
AND OPx=0
WITH OEx=1
AND OPx=1
Figure 33. PWM Signal from 0% to 100% Duty Cycle
fCOUNTER
ARR=FDh
COUNTER
FDh
FEh
FFh
FDh
FEh
FFh
FDh
FEh
OCRx=FCh
OCRx=FDh
OCRx=FEh
OCRx=FFh
t
56/164
ST72311R, ST72511R, ST72512R, ST72532R
External clock and event detector mode
PWM AUTO-RELOAD TIMER (Cont’d)
Output compare and Time base interrupt
On overflow, the OVF flag of the CSR register is
set and an overflow interrupt request is generated
if the overflow interrupt enable bit, OIE, in the CSR
register, is set. The OVF flag must be reset by the
user software. This interrupt can be used as a time
base in the application.
Using the f
external prescaler input clock, the
EXT
auto-reload timer can be used as an external clock
event detector. In this mode, the ARR register is
used to select the n
counted before setting the OVF flag.
number of events to be
EVENT
n
= 256 - ARR
EVENT
When entering HALT mode while f
is selected,
EXT
all the timer control registers are frozen but the
counter continues to increment. If the OIE bit is
set, the next overflow of the counter will generate
an interrupt which wakes up the MCU.
Figure 34. External Event Detector Example (3 counts)
fEXT=fCOUNTER
ARR=FDh
COUNTER
FDh
FEh
FFh
FDh
FEh
FFh
FDh
OVF
CSR READ
CSR READ
INTERRUPT
IF OIE=1
INTERRUPT
IF OIE=1
t
57/164
ST72311R, ST72511R, ST72512R, ST72532R
PWM AUTO-RELOAD TIMER (Cont’d)
10.3.3 Register Description
CONTROL / STATUS REGISTER (CSR)
Read/Write
COUNTER ACCESS REGISTER (CAR)
Read/Write
Reset Value: 0000 0000 (00h)
Reset Value: 0000 0000 (00h)
7
0
7
0
EXCL CC2
CC1
CC0
TCE FCRL
OIE
OVF
CA7
CA6
CA5
CA4
CA3
CA2
CA1
CA0
Bit 7 = EXCLExternal Clock
Bit 7:0 = CA[7:0] Counter Access Data
This bit is set and cleared by software. It selects the
input clock for the 7-bit prescaler.
0: CPU clock.
These bits can be set and cleared either by hard-
ware or by software. The CAR register is used to
read or write the auto-reload counter “on the fly”
(while it is counting).
1: External clock.
Bit 6:4 = CC[2:0] Counter Clock Control
These bits are set and cleared by software. They
determine the prescaler division ratio from f
.
INPUT
AUTO-RELOAD REGISTER (ARR)
Read/Write
f
With f
INPUT
=8 MHz CC2 CC1 CC0
COUNTER
f
8 MHz
4 MHz
2 MHz
1 MHz
500 KHz
250 KHz
125 KHz
62.5 KHz
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
INPUT
Reset Value: 0000 0000 (00h)
f
f
f
/ 2
/ 4
/ 8
INPUT
INPUT
INPUT
7
0
f
/ 16
/ 32
/ 64
/ 128
INPUT
AR7
AR6
AR5
AR4
AR3
AR2
AR1
AR0
f
INPUT
f
INPUT
INPUT
f
Bit 7:0 = AR[7:0]Counter Auto-Reload Data
These bits are set and cleared by software. They
are used to hold the auto-reload value which is au-
tomatically loaded in the counter when an overflow
occurs. At the same time, the PWM output levels
are changed according to the corresponding OPx
bit in the PWMCR register.
Bit 3 = TCE Timer Counter Enable
This bit is set and cleared by software. It puts the
timer in the lowest power consumption mode.
0: Counter stopped (prescaler and counter frozen).
1: Counter running.
Bit 2 = FCRLForce Counter Re-Load
This register has two PWM management func-
tions:
This bit is write-only and any attempt to read it will
yield alogicalzero. When set, itcausesthecontents
of ARR register to be loaded into the counter, and
the content of the prescaler register to be clearedin
order to initialize the timer before starting to count.
– Adjusting the PWM frequency
– Setting the PWM duty cycle resolution
PWM Frequency vs. Resolution:
Bit 1 = OIEOverflow Interrupt Enable
This bit is set and cleared by software. It allows to
enable/disable the interrupt which is generated
when the OVF bit is set.
f
PWM
ARR value Resolution
Min
Max
0: Overflow Interrupt disable.
0
8-bit
~0.244-KHz 31.25-KHz
1: Overflow Interrupt enable.
[ 0..127 ]
> 7-bit
> 6-bit
> 5-bit
> 4-bit
~0.244-KHz
~0.488-KHz
~0.977-KHz
~1.953-KHz
62.5-KHz
125-KHz
250-KHz
500-KHz
Bit 0 = OVFOverflow Flag
[ 128..191 ]
[ 192..223 ]
[ 224..239 ]
This bit is set by hardware and cleared by software
reading the CSR register. It indicates the transition
of the counter from FFh to the ARR value
.
0: New transition not yet reached
1: Transition reached
58/164
ST72311R, ST72511R, ST72512R, ST72532R
PWM AUTO-RELOAD TIMER (Cont’d)
PWM CONTROL REGISTER (PWMCR)
Read/Write
DUTY CYCLE REGISTERS (DCRx)
Read/Write
Reset Value: 0000 0000 (00h)
Reset Value: 0000 0000 (00h)
7
0
7
0
OE3
OE2
OE1
OE0
OP3
OP2
OP1
OP0
DC7
DC6
DC5
DC4
DC3
DC2
DC1
DC0
Bit 7:4 = OE[3:0] PWM Output Enable
Bit 7:0 = DC[7:0] Duty Cycle Data
These bits are set and cleared by software.
These bits are set and cleared by software. They
enable or disable the PWM output channels inde-
pendently acting on the corresponding I/O pin.
0: PWM output disabled.
A DCRx register is associated with the OCRx reg-
ister of each PWM channel to determine the sec-
ond edge location of the PWM signal (the first
edge location is common to all channels and given
by the ARR register). These DCR registers allow
the duty cycle to be set independently for each
PWM channel.
1: PWM output enabled.
Bit 3:0 = OP[3:0] PWM Output Polarity
These bits are set and cleared by software. They
independently select the polarity of the four PWM
output signals.
PWMx output level
OPx
Counter <= OCRx
Counter > OCRx
1
0
0
1
0
1
Note: When an OPx bit is modified, the PWMx out-
put signal polarity is immediately reversed.
59/164
ST72311R, ST72511R, ST72512R, ST72532R
PWM AUTO-RELOAD TIMER (Cont’d)
Table 17. PWM Auto-Reload Timer Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
PWMDCR3
DC7
0
DC6
0
DC5
0
DC4
0
DC3
0
DC2
0
DC1
0
DC0
0
0072h
0073h
0074h
0075h
0076h
0077h
0078h
0079h
Reset Value
PWMDCR2
DC7
0
DC6
0
DC5
0
DC4
0
DC3
0
DC2
0
DC1
0
DC0
0
Reset Value
PWMDCR1
DC7
0
DC6
0
DC5
0
DC4
0
DC3
0
DC2
0
DC1
0
DC0
0
Reset Value
PWMDCR0
DC7
0
DC6
0
DC5
0
DC4
0
DC3
0
DC2
0
DC1
0
DC0
0
Reset Value
PWMCR
OE3
0
OE2
0
OE1
0
OE0
0
OP3
0
OP2
0
OP1
0
OP0
0
Reset Value
ARTCSR
EXCL
0
CC2
0
CC1
0
CC0
0
TCE
0
FCRL
0
OIE
0
OVF
0
Reset Value
ARTCAR
CA7
0
CA6
0
CA5
0
CA4
0
CA3
0
CA2
0
CA1
0
CA0
0
Reset Value
ARTARR
AR7
0
AR6
0
AR5
0
AR4
0
AR3
0
AR2
0
AR1
0
AR0
0
Reset Value
60/164
ST72311R, ST72511R, ST72512R, ST72532R
10.4 16-BIT TIMER
10.4.1 Introduction
10.4.3 Functional Description
10.4.3.1 Counter
The timer consists of a 16-bit free-running counter
driven by a programmable prescaler.
The main block of the Programmable Timer is a
16-bit free running upcounter and its associated
16-bit registers. The 16-bit registers are made up
of two 8-bit registers called high & low.
It may be used for a variety of purposes, including
pulse length measurement of up to two input sig-
nals (input capture) or generation of up to two out-
put waveforms (output compare and PWM).
Counter Register (CR):
Pulse lengths and waveform periods can be mod-
ulated from a few microseconds to several milli-
seconds using the timer prescaler and the CPU
clock prescaler.
– Counter High Register (CHR) is the most sig-
nificant byte (MS Byte).
– Counter Low Register (CLR) is the least sig-
nificant byte (LS Byte).
Some ST7 devices have two on-chip 16-bit timers.
They are completely independent, and do not
share any resources. They are synchronized after
a MCU reset as long as the timer clock frequen-
cies are not modified.
Alternate Counter Register (ACR)
– Alternate Counter High Register (ACHR) is the
most significant byte (MS Byte).
– Alternate Counter Low Register (ACLR) is the
least significant byte (LS Byte).
This description covers one or two 16-bit timers. In
ST7 devices with two timers, register names are
prefixed with TA (Timer A) or TB (Timer B).
These two read-only 16-bit registers contain the
same value but with the difference that reading the
ACLR register does not clear the TOF bit (Timer
overflow flag), located in the Status register, (SR),
(see note at the end of paragraph titled 16-bit read
sequence).
10.4.2 Main Features
■ Programmable prescaler:fCPU dividedby2, 4or8.
■ Overflow status flag and maskable interrupt
■ External clock input (must be at least 4 times
slower thantheCPUclock speed)withthechoice
of active edge
■ Output compare functions with
– 2 dedicated 16-bit registers
– 2 dedicated programmable signals
– 2 dedicated status flags
Writing in the CLR register or ACLR register resets
the free running counter to the FFFCh value.
Both counters have a reset value of FFFCh (this is
the only value which is reloaded in the 16-bit tim-
er). The reset value of both counters is also
FFFCh in One Pulse mode and PWM mode.
The timer clock depends on the clock control bits
of the CR2 register, as illustrated in Table 18 Clock
Control Bits. The value in the counter register re-
peats every 131.072, 262.144 or 524.288 CPU
clock cycles depending on the CC[1:0] bits.
– 1 dedicated maskable interrupt
■ Input capture functions with
– 2 dedicated 16-bit registers
– 2 dedicated active edge selection signals
– 2 dedicated status flags
The timer frequency can be f
or an external frequency.
/2, f
/4, f
/8
CPU
CPU
CPU
– 1 dedicated maskable interrupt
■ Pulse width modulation mode (PWM)
■ One pulse mode
■ 5 alternatefunctionson I/O ports (ICAP1,ICAP2,
OCMP1, OCMP2, EXTCLK)*
The Block Diagram is shown in Figure 35.
*Note: Some timer pins may not available (not
bonded) in some ST7 devices. Refer to the device
pin out description.
When reading an input signal on a non-bonded
pin, the value will always be ‘1’.
61/164
ST72311R, ST72511R, ST72512R, ST72532R
16-BIT TIMER (Cont’d)
Figure 35. Timer Block Diagram
ST7 INTERNAL BUS
f
CPU
MCU-PERIPHERAL INTERFACE
8 low
8-bit
8 high
8
8
8
8
8
8
8
8
buffer
EXEDG
h
w
h
w
h
w
h
low
16
INPUT
CAPTURE
REGISTER
INPUT
CAPTURE
REGISTER
OUTPUT
COMPARE
REGISTER
OUTPUT
COMPARE
REGISTER
1
1/2
1/4
1/8
COUNTER
REGISTER
1
2
2
ALTERNATE
COUNTER
REGISTER
EXTCLK
pin
16
16
16
CC[1:0]
TIMER INTERNAL BUS
16 16
OVERFLOW
DETECT
EDGE DETECT
CIRCUIT1
OUTPUT COMPARE
CIRCUIT
ICAP1
pin
CIRCUIT
6
EDGE DETECT
CIRCUIT2
ICAP2
pin
OCMP1
pin
LATCH1
LATCH2
ICF1 OCF1 TOF ICF2 OCF2
0
0
0
OCMP2
pin
(Status Register) SR
ICIE OCIE TOIE FOLV2 FOLV1OLVL2 IEDG1 OLVL1
OC1E
OPM PWM CC1 CC0 IEDG2 EXEDG
OC2E
(Control Register 1) CR1
(Control Register 2) CR2
(See note)
Note: If IC, OC and TO interrupt requests have separate vectors
then the last OR is not present (See device Interrupt Vector Table)
TIMER INTERRUPT
62/164
ST72311R, ST72511R, ST72512R, ST72532R
16-BIT TIMER (Cont’d)
16-bit read sequence: (from either the Counter
Register or the Alternate Counter Register).
Clearing the overflow interrupt request is done in
two steps:
1.Reading the SR register while the TOF bit is set.
2.An access (read or write) to the CLR register.
Beginning of the sequence
Read
LS Byte
Notes: The TOF bit is not cleared by accesses to
ACLR register. The advantage of accessing the
ACLR register rather than the CLR register is that
it allows simultaneous use of the overflow function
and reading the free running counter at random
times (for example, to measure elapsed time) with-
out the risk of clearing the TOF bit erroneously.
MS Byte
At t0
is buffered
Other
instructions
Returns the buffered
LS Byte value at t0
Read
LS Byte
At t0 +∆t
The timer is not affected by WAIT mode.
In HALT mode, the counter stops counting until the
mode is exited. Counting then resumes from the
previous count (MCU awakened by an interrupt) or
from the reset count (MCU awakened by a Reset).
Sequence completed
The user must read the MS Byte first, then the LS
Byte value is buffered automatically.
This buffered value remains unchanged until the
16-bit read sequence is completed, even if the
user reads the MS Byte several times.
10.4.3.2 External Clock
The external clock (where available) is selected if
CC0=1 and CC1=1 in CR2 register.
After a complete reading sequence, if only the
CLR register or ACLR register are read, they re-
turn the LS Byte of the count value at the time of
the read.
The status of the EXEDG bit in the CR2 register
determines the type of level transition on the exter-
nal clock pin EXTCLK that will trigger the free run-
ning counter.
Whatever the timer mode used (input capture, out-
put compare, one pulse mode or PWM mode) an
overflow occurs when the counter rolls over from
FFFFh to 0000h then:
The counter is synchronised with the falling edge
of the internal CPU clock.
A minimum of four falling edges of the CPU clock
must occur between two consecutive active edges
of the external clock; thus the external clock fre-
quency must be less than a quarter of the CPU
clock frequency.
– The TOF bit of the SR register is set.
– A timer interrupt is generated if:
– TOIE bit of the CR1 register is set and
– I bit of the CC register is cleared.
If one of these conditions is false, the interrupt re-
mains pending to be issued as soon as they are
both true.
63/164
ST72311R, ST72511R, ST72512R, ST72532R
16-BIT TIMER (Cont’d)
Figure 36. Counter Timing Diagram, internal clock divided by 2
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
FFFD FFFE FFFF 0000 0001 0002 0003
COUNTER REGISTER
TIMER OVERFLOW FLAG (TOF)
Figure 37. Counter Timing Diagram, internal clock divided by 4
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
FFFC
FFFD
0000
0001
COUNTER REGISTER
TIMER OVERFLOW FLAG (TOF)
Figure 38. Counter Timing Diagram, internal clock divided by 8
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
0000
FFFC
FFFD
COUNTER REGISTER
TIMER OVERFLOW FLAG (TOF)
Note: The MCU is in reset state when the internal reset signal is high, when it is low the MCU is running.
64/164
ST72311R, ST72511R, ST72512R, ST72532R
16-BIT TIMER (Cont’d)
10.4.3.3 Input Capture
When an input capture occurs:
– ICFi bit is set.
In this section, the index, i, may be 1 or 2 because
there are 2 input capture functions in the 16-bit
timer.
– The ICiR register contains the value of the free
running counter on the active transition on the
ICAPi pin (see Figure 40).
The two input capture 16-bit registers (IC1R and
IC2R) are used to latch the value of the free run-
ning counter after a transition detected by the
ICAPi pin (see figure 5).
– A timer interrupt is generated if the ICIE bit is set
and the I bit is cleared in the CC register. Other-
wise, the interrupt remains pending until both
conditions become true.
MS Byte
ICiHR
LS Byte
ICiLR
ICiR
Clearing the Input Capture interrupt request (i.e.
clearing the ICFi bit) is done in two steps:
ICiR register is a read-only register.
1. Reading the SR register while the ICFi bit is set.
2. An access (read or write) to the ICiLR register.
The active transition is software programmable
through the IEDGi bit of Control Registers (CRi).
Timing resolution is one count of the free running
Notes:
counter: (f
/CC[1:0]).
CPU
1. After reading the ICiHR register, transfer of
input capture data is inhibited and ICFi will
never be set until the ICiLR register is also
read.
Procedure:
To use the input capture function select the follow-
ing in the CR2 register:
2. The ICiR register contains the free running
counter value which corresponds to the most
recent input capture.
– Select the timer clock (CC[1:0]) (see Table 18
Clock Control Bits).
3. The 2 input capture functions can be used
together even if the timer also uses the 2 output
compare functions.
– Select the edge of the active transition on the
ICAP2 pin with the IEDG2 bit (the ICAP2 pin
must be configured as floating input).
4. In One pulse Mode and PWM mode only the
input capture 2 can be used.
And select the following in the CR1 register:
– Set the ICIE bit to generate an interrupt after an
input capture coming from either the ICAP1 pin
or the ICAP2 pin
5. The alternate inputs (ICAP1 & ICAP2) are
always directly connected to the timer. So any
transitions on these pins activate the input cap-
ture function.
– Select the edge of the active transition on the
ICAP1 pin with theIEDG1 bit (the ICAP1pin must
be configured as floating input).
Moreover if one of the ICAPi pin is configured
as an input and the second one as an output,
an interrupt can be generated if the user toggle
the output pin and if the ICIE bit is set.
This can be avoided if the input capture func-
tion i is disabled by reading the ICiHR (see note
1).
6. The TOF bit can be used with interrupt in order
to measure event that go beyond the timer
range (FFFFh).
65/164
ST72311R, ST72511R, ST72512R, ST72532R
16-BIT TIMER (Cont’d)
Figure 39. Input Capture Block Diagram
ICAP1
pin
(Control Register 1) CR1
IEDG1
EDGE DETECT
CIRCUIT2
EDGE DETECT
CIRCUIT1
ICIE
ICAP2
pin
(Status Register) SR
ICF1
ICF2
0
0
0
IC2R Register
IC1R Register
(Control Register 2) CR2
16-BIT
16-BIT FREE RUNNING
COUNTER
IEDG2
CC0
CC1
Figure 40. Input Capture Timing Diagram
TIMER CLOCK
FF01
FF02
FF03
COUNTER REGISTER
ICAPi PIN
ICAPi FLAG
FF03
ICAPi REGISTER
Note: Active edge is rising edge.
66/164
ST72311R, ST72511R, ST72512R, ST72532R
16-BIT TIMER (Cont’d)
10.4.3.4 Output Compare
– The OCMPi pin takes OLVLi bit value (OCMPi
pin latch is forced low during reset).
In this section, the index, i, may be 1 or 2 because
there are 2 output compare functions in the 16-bit
timer.
– A timer interrupt is generated if the OCIE bit is
set in the CR2 register and the I bit is cleared in
the CC register (CC).
This function can be used to control an output
waveform or indicate when a period of time has
elapsed.
The OCiR register value required for aspecific tim-
ing application can be calculated using the follow-
ing formula:
When a match is found between the Output Com-
pare register and the free running counter, the out-
put compare function:
– Assigns pins with a programmable value if the
OCIE bit is set
∆t f
* CPU
PRESC
∆ OCiR =
– Sets a flag in the status register
– Generates an interrupt if enabled
Where:
∆t
= Output compare period (in seconds)
= CPU clock frequency (in hertz)
Two 16-bit registers Output Compare Register 1
(OC1R) and Output Compare Register 2 (OC2R)
contain the value to be compared to the counter
register each timer clock cycle.
f
CPU
= Timer prescaler factor (2, 4 or 8 de-
pending on CC[1:0] bits, see Table 18
Clock Control Bits)
PRESC
MS Byte
OCiHR
LS Byte
OCiLR
OCiR
If the timer clock is an external clock, the formula
is:
These registers are readable and writable and are
not affected by the timer hardware. A reset event
changes the OCiR value to 8000h.
∆ OCiR = ∆t f
* EXT
Timing resolution is one count of the free running
Where:
counter: (f
).
CC[1:0]
CPU/
∆t
= Output compare period (in seconds)
= External timer clock frequency (in hertz)
f
EXT
Procedure:
To use the output compare function, select the fol-
lowing in the CR2 register:
Clearing the output compare interrupt request (i.e.
clearing the OCFi bit) is done by:
– Set the OCiE bit if an output is needed then the
OCMPi pin is dedicated to the output compare i
signal.
1. Reading the SR register while the OCFi bit is
set.
2. An access (read or write) to the OCiLR register.
– Select the timer clock (CC[1:0]) (see Table 18
Clock Control Bits).
The following procedure is recommended to pre-
vent the OCFi bit from being set between the time
it is read and the write to the OCiR register:
And select the following in the CR1 register:
– Select theOLVLi bit to applied to theOCMPi pins
after the match occurs.
– Write to the OCiHR register (further compares
are inhibited).
– Set the OCIE bit to generate an interrupt if it is
needed.
– Read the SR register (first step of the clearance
of the OCFi bit, which may be already set).
When a match is found between OCRi register
and CR register:
– Write to the OCiLR register (enables the output
compare function and clears the OCFi bit).
– OCFi bit is set.
67/164
ST72311R, ST72511R, ST72512R, ST72532R
16-BIT TIMER (Cont’d)
Notes:
1. After a processor write cycle to the OCiHR reg-
ister, the output compare function is inhibited
until the OCiLR register is also written.
Forced Compare Output capability
When the FOLVi bit is set by software, the OLVLi
bit is copied to the OCMPi pin. The OLVi bit has to
be toggled in order to toggle the OCMPi pin when
it is enabled (OCiE bit=1). The OCFi bit is then not
set by hardware, and thus no interrupt request is
generated.
2. If the OCiE bit is not set, the OCMPi pin is a
general I/O port and the OLVLi bit will not
appear when a match is found but an interrupt
could be generated if the OCIE bit is set.
3. When the timer clock is f
/2, OCFi and
FOLVLi bits have no effect in both one pulse mode
and PWM mode.
CPU
OCMPi are set while the counter value equals
the OCiR register value (see Figure 42 on page
68). This behaviour is the same in OPM or
PWM mode.
When the timer clock is f
/4, f
/8 or in
CPU
CPU
external clock mode, OCFi and OCMPi are set
while the counter value equals the OCiR regis-
ter value plus 1 (see Figure 43 on page 68).
4. The output compare functions can be used both
for generating external events on the OCMPi
pins even if the input capture mode is also
used.
5. The value in the 16-bit OCiR register and the
OLVi bit should be changed after each suc-
cessful comparison in order to control an output
waveform or establish a new elapsed timeout.
Figure 41. Output Compare Block Diagram
16 BIT FREE RUNNING
OC1E
CC1 CC0
OC2E
COUNTER
(Control Register 2) CR2
16-bit
(Control Register 1) CR1
OUTPUT COMPARE
CIRCUIT
Latch
1
OCIE
FOLV2 FOLV1 OLVL2
OLVL1
OCMP1
Pin
16-bit
16-bit
Latch
2
OCMP2
Pin
OC1R Register
OCF1
OCF2
0
0
0
OC2R Register
(Status Register) SR
68/164
ST72311R, ST72511R, ST72512R, ST72532R
16-BIT TIMER (Cont’d)
Figure 42. Output Compare Timing Diagram, f
=f
/2
TIMER
CPU
INTERNAL CPU CLOCK
TIMER CLOCK
COUNTER REGISTER
2ECF 2ED0 2ED1 2ED2 2ED3 2ED4
2ED3
OUTPUT COMPARE REGISTER i (OCRi)
OUTPUT COMPARE FLAG i (OCFi)
OCMPi PIN (OLVLi=1)
Figure 43. Output Compare Timing Diagram, f
=f
/4
TIMER
CPU
INTERNAL CPU CLOCK
TIMER CLOCK
2ECF 2ED0 2ED1 2ED2
2ED3
2ED4
2ED3
COUNTER REGISTER
OUTPUT COMPARE REGISTER i (OCRi)
COMPARE REGISTER i LATCH
OUTPUT COMPARE FLAG i (OCFi)
OCMPi PIN (OLVLi=1)
69/164
ST72311R, ST72511R, ST72512R, ST72532R
16-BIT TIMER (Cont’d)
10.4.3.5 One Pulse Mode
Clearing the Input Capture interrupt request (i.e.
clearing the ICFi bit) is done in two steps:
One Pulse mode enables the generation of a
pulse when an external event occurs. This mode is
selected via the OPM bit in the CR2 register.
1. Reading the SR register while the ICFi bit is set.
2. An access (read or write) to the ICiLR register.
The one pulse mode uses the Input Capture1
function and the Output Compare1 function.
The OC1R register value required for a specific
timing application can be calculated using the fol-
lowing formula:
Procedure:
t * f
To use one pulse mode:
CPU - 5
OCiR Value =
PRESC
1. Load the OC1R register with the value corre-
sponding to the length of the pulse (see the for-
mula in the opposite column).
Where:
t
= Pulse period (in seconds)
2. Select the following in the CR1 register:
f
= CPU clock frequency (in hertz)
CPU
– Using the OLVL1 bit, select the level to be ap-
plied to the OCMP1 pin after the pulse.
= Timer prescaler factor (2, 4 or 8 depend-
ing on the CC[1:0] bits, see Table 18
Clock Control Bits)
PRESC
– Using the OLVL2 bit, select the level to be ap-
plied to the OCMP1 pin during the pulse.
If the timer clock is an external clock the formula is:
– Select the edge of the active transition on the
ICAP1 pin with the IEDG1 bit (the ICAP1 pin
must be configured as floating input).
OCiR = t f
-5
* EXT
Where:
t
3. Select the following in the CR2 register:
= Pulse period (in seconds)
– Set the OC1E bit, the OCMP1 pin is then ded-
icated to the Output Compare 1 function.
f
= External timer clock frequency (in hertz)
EXT
– Set the OPM bit.
When the value of the counter is equal to the value
of the contents of the OC1R register, the OLVL1
bit is output on the OCMP1 pin, (See Figure 44).
– Select the timer clock CC[1:0] (see Table 18
Clock Control Bits).
One pulse mode cycle
When
Notes:
1. The OCF1 bit cannot be set by hardware in one
pulse mode but the OCF2 bit can generate an
Output Compare interrupt.
OCMP1 = OLVL2
event occurs
on ICAP1
Counter is reset
2. When the Pulse Width Modulation (PWM) and
One Pulse Mode (OPM) bits are both set, the
PWM mode is the only active one.
to FFFCh
ICF1 bit is set
3. If OLVL1=OLVL2 a continuous signal will be
seen on the OCMP1 pin.
When
Counter
OCMP1 = OLVL1
= OC1R
4. The ICAP1 pin can not be used to perform input
capture. The ICAP2 pin can be used to perform
input capture (ICF2 can be set and IC2R can be
loaded) but the user must take care that the
counter is reset each time a valid edge occurs
on the ICAP1 pin and ICF1 can also generates
interrupt if ICIE is set.
Then, on a valid event on the ICAP1 pin, the coun-
ter is initialized to FFFCh and OLVL2 bit is loaded
on the OCMP1 pin, the ICF1 bit is set and the val-
ue FFFDh is loaded in the IC1R register.
Because the ICF1 bit is set when an active edge
occurs, an interrupt can be generated if the ICIE
bit is set.
5. When one pulse mode is used OC1R is dedi-
cated to this mode. Nevertheless OC2R and
OCF2 can be used to indicate a period of time
has been elapsed but cannot generate an out-
put waveform because the level OLVL2 is dedi-
cated to the one pulse mode.
70/164
ST72311R, ST72511R, ST72512R, ST72532R
16-BIT TIMER (Cont’d)
Figure 44. One Pulse Mode Timing Example
FFFC FFFD FFFE
COUNTER
2ED0 2ED1 2ED2
2ED3
FFFC FFFD
ICAP1
OLVL2
OLVL1
OLVL2
OCMP1
compare1
Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1
Figure 45. Pulse Width Modulation Mode Timing Example
2ED0 2ED1 2ED2
34E2 FFFC
FFFC FFFD FFFE
34E2
COUNTER
OCMP1
OLVL2
OLVL1
OLVL2
compare2
compare1
compare2
Note: OC1R=2ED0h, OC2R=34E2, OLVL1=0, OLVL2= 1
71/164
ST72311R, ST72511R, ST72512R, ST72532R
16-BIT TIMER (Cont’d)
10.4.3.6 Pulse Width Modulation Mode
Pulse Width Modulation (PWM) mode enables the
generation of a signal with a frequency and pulse
length determined by the value of the OC1R and
OC2R registers.
The OCiR register value required for aspecific tim-
ing application can be calculated using the follow-
ing formula:
t * f
CPU
PRESC
- 5
OCiR Value =
The pulse width modulation mode uses the com-
plete Output Compare 1 function plus the OC2R
register, and so these functionality can not be
used when the PWM mode is activated.
Where:
t
= Signal or pulse period (in seconds)
= CPU clock frequency (in hertz)
f
Procedure
CPU
= Timer prescaler factor (2, 4 or 8 depend-
ing on CC[1:0] bits, see Table 18 Clock
Control Bits)
To use pulse width modulation mode:
PRESC
1. Load the OC2R register with the value corre-
sponding to the period of the signal using the
formula in the opposite column.
If the timer clock is an external clock the formula is:
2. Load the OC1R register with the value corre-
sponding to the period of the pulse if (OLVL1=0
and OLVL2=1) using the formula in the oppo-
site column.
OCiR = t f
-5
* EXT
Where:
t
= Signal or pulse period (in seconds)
3. Select the following in the CR1 register:
f
= External timer clock frequency (in hertz)
EXT
– Using the OLVL1 bit, select the level to be ap-
plied to the OCMP1 pin after a successful
comparison with OC1R register.
The Output Compare 2 event causes the counter
to be initialized to FFFCh (See Figure 45)
– Using the OLVL2 bit, select the level to be ap-
plied to the OCMP1 pin after a successful
comparison with OC2R register.
Notes:
1. After a write instruction to the OCiHR register,
the output compare function is inhibited until the
OCiLR register is also written.
4. Select the following in the CR2 register:
– Set OC1E bit: the OCMP1 pin is then dedicat-
ed to the output compare 1 function.
2. The OCF1 and OCF2 bits cannot be set by
hardware in PWM mode therefore the Output
Compare interrupt is inhibited.
– Set the PWM bit.
– Select the timer clock (CC[1:0]) (see Table 18
Clock Control Bits).
3. The ICF1 bit is set by hardware when the coun-
ter reaches the OC2R value and can produce a
timer interrupt if the ICIE bit is set and the I bit is
cleared.
If OLVL1=1 and OLVL2=0 the length of the posi-
tive pulse is the difference between the OC2R and
OC1R registers.
4. In PWM mode the ICAP1 pin can not be used
to perform input capture because it is discon-
nected to the timer. The ICAP2 pin can be used
to perform input capture (ICF2 can be set and
IC2R can be loaded) but the user must take
care that the counter is reset each period and
ICF1 can also generates interrupt if ICIE is set.
If OLVL1=OLVL2 a continuous signal will be seen
on the OCMP1 pin.
Pulse Width Modulation cycle
When
5. When the Pulse Width Modulation (PWM) and
One Pulse Mode (OPM) bits are both set, the
PWM mode is the only active one.
Counter
= OC1R
OCMP1 = OLVL1
OCMP1 = OLVL2
When
Counter
= OC2R
Counter is reset
to FFFCh
ICF1 bit is set
72/164
ST72311R, ST72511R, ST72512R, ST72532R
16-BIT TIMER (Cont’d)
10.4.4 Low Power Modes
Mode
Description
No effect on 16-bit Timer.
Timer interrupts cause the device to exit from WAIT mode.
WAIT
HALT
16-bit Timer registers are frozen.
In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous
count when the MCU is woken up by an interrupt with “exit from HALT mode” capability or from the counter
reset value when the MCU is woken up by a RESET.
If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is armed. Consequent-
ly, when the MCU is woken up by an interrupt with “exit from HALT mode” capability, the ICFi bit is set, and
the counter value present when exiting from HALT mode is captured into the ICiR register.
10.4.5 Interrupts
Enable
Control from
Bit
Exit
Exit
from
Halt
Event
Flag
Interrupt Event
Wait
Yes
Yes
Yes
Yes
Yes
Input Capture 1 event/Counter reset in PWM mode
Input Capture 2 event
ICF1
ICF2
No
No
No
No
No
ICIE
Output Compare 1 event (not available in PWM mode)
Output Compare 2 event (not available in PWM mode)
Timer Overflow event
OCF1
OCF2
TOF
OCIE
TOIE
Note: The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts chap-
ter). These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt
mask in the CC register is reset (RIM instruction).
10.4.6 Summary of Timer modes
AVAILABLE RESOURCES
MODES
Input Capture 1
Input Capture 2
Yes
Output Compare 1 Output Compare 2
Input Capture (1 and/or 2)
Output Compare (1 and/or 2)
One Pulse Mode
Yes
Yes
No
Yes
Yes
No
Yes
Yes
Yes
1)
3)
2)
Not Recommended
Not Recommended
Partially
No
PWM Mode
No
No
1)
2)
3)
See note 4 in Section 10.4.3.5 ”One Pulse Mode” on page 69
See note 5 in Section 10.4.3.5 ”One Pulse Mode” on page 69
See note 4 in Section 10.4.3.6 ”Pulse Width Modulation Mode” on page 71
73/164
ST72311R, ST72511R, ST72512R, ST72532R
16-BIT TIMER (Cont’d)
10.4.7 Register Description
Bit 4 = FOLV2 Forced Output Compare 2.
This bit is set and cleared by software.
0: No effect on the OCMP2 pin.
1:Forces the OLVL2 bit to be copied to the
OCMP2 pin, if the OC2E bit is set and even if
there is no successful comparison.
Each Timer is associated with three control and
status registers, and with six pairs of data registers
(16-bit values) relating to the two input captures,
the two output compares, the counter and the al-
ternate counter.
Bit 3 = FOLV1 Forced Output Compare 1.
This bit is set and cleared by software.
0: No effect on the OCMP1 pin.
CONTROL REGISTER 1 (CR1)
Read/Write
1: Forces OLVL1 to becopied to theOCMP1 pin, if
the OC1E bit is set and even if there is no suc-
cessful comparison.
Reset Value: 0000 0000 (00h)
7
0
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
Bit 2 = OLVL2 Output Level 2.
This bit is copied to the OCMP2 pin whenever a
successful comparison occurs with the OC2R reg-
ister and OCxE is set in the CR2 register. This val-
ue is copied to the OCMP1 pin in One Pulse Mode
and Pulse Width Modulation mode.
Bit 7 = ICIE Input Capture Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the
ICF1 or ICF2 bit of the SR register is set.
Bit 1 = IEDG1 Input Edge 1.
Bit 6 = OCIE Output Compare Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the
OCF1 or OCF2 bit of the SR register is set.
This bit determines which type of level transition
on the ICAP1 pin will trigger the capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
Bit 5 = TOIE Timer Overflow Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is enabled whenever the TOF
bit of the SR register is set.
Bit 0 = OLVL1 Output Level 1.
The OLVL1 bit is copied to the OCMP1 pin when-
ever a successful comparison occurs with the
OC1R register and the OC1E bit is set in the CR2
register.
74/164
ST72311R, ST72511R, ST72512R, ST72532R
16-BIT TIMER (Cont’d)
CONTROL REGISTER 2 (CR2)
Read/Write
Bit 4 = PWM Pulse Width Modulation.
0: PWM mode is not active.
1: PWM mode is active, the OCMP1 pin outputs a
programmable cyclic signal; the length of the
pulse depends on the value of OC1R register;
the period depends on the value of OC2R regis-
ter.
Reset Value: 0000 0000 (00h)
7
0
OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG
Bit 3, 2 = CC[1:0] Clock Control.
Bit 7 = OC1E Output Compare 1 Pin Enable.
This bit is used only to output the signal from the
timer on the OCMP1 pin (OLV1 in Output Com-
pare mode, both OLV1 and OLV2 in PWM and
one-pulse mode). Whatever the value of the OC1E
bit, the Output Compare 1 function of the timer re-
mains active.
0: OCMP1 pin alternate function disabled (I/O pin
free for general-purpose I/O).
1: OCMP1 pin alternate function enabled.
The timer clock mode depends on these bits:
Table 18. Clock Control Bits
Timer Clock
fCPU / 4
CC1
CC0
0
0
1
0
1
0
fCPU / 2
fCPU / 8
External Clock (where
available)
1
1
Bit 6 = OC2E Output Compare 2 Pin Enable.
This bit is used only to output the signal from the
timer on the OCMP2 pin (OLV2 in Output Com-
pare mode). Whatever the value of the OC2E bit,
the Output Compare 2 function of the timer re-
mains active.
0: OCMP2 pin alternate function disabled (I/O pin
free for general-purpose I/O).
1: OCMP2 pin alternate function enabled.
Note: If the external clock pin is not available, pro-
gramming the external clock configuration stops
the counter.
Bit 1 = IEDG2 Input Edge 2.
This bit determines which type of level transition
on the ICAP2 pin will trigger the capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
Bit 5 = OPM One Pulse Mode.
0: One Pulse Mode is not active.
Bit 0 = EXEDG External Clock Edge.
This bit determines which type of level transition
on the external clock pin EXTCLK will trigger the
counter register.
0: A falling edge triggers the counter register.
1: A rising edge triggers the counter register.
1: One Pulse Mode is active, the ICAP1 pin can be
used to trigger one pulse on the OCMP1 pin; the
active transition is given by the IEDG1 bit. The
length of the generated pulse depends on the
contents of the OC1R register.
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ST72311R, ST72511R, ST72512R, ST72532R
16-BIT TIMER (Cont’d)
STATUS REGISTER (SR)
Read Only
INPUT CAPTURE 1 HIGH REGISTER (IC1HR)
Read Only
Reset Value: Undefined
Reset Value: 0000 0000 (00h)
The three least significant bits are not used.
This is an 8-bit read only register that contains the
high part of the counter value (transferred by the
input capture 1 event).
7
0
0
ICF1 OCF1 TOF ICF2 OCF2
0
0
7
0
MSB
LSB
Bit 7 = ICF1 Input Capture Flag 1.
0: No input capture (reset value).
1: An input capture has occurred on the ICAP1 pin
or the counter has reached the OC2R value in
PWM mode. To clear this bit, first read the SR
register, then read or write the low byte of the
IC1R (IC1LR) register.
INPUT CAPTURE 1 LOW REGISTER (IC1LR)
Read Only
Reset Value: Undefined
This is an 8-bit read only register that contains the
low part of the counter value (transferred by the in-
put capture 1 event).
Bit 6 = OCF1 Output Compare Flag 1.
0: No match (reset value).
1: The content of the free running counter has
matched the content of the OC1R register. To
clear this bit, first read the SR register, then read
or write the low byte of the OC1R (OC1LR) reg-
ister.
7
0
MSB
LSB
OUTPUT COMPARE
(OC1HR)
1
HIGH REGISTER
Bit 5 = TOF Timer Overflow Flag.
0: No timer overflow (reset value).
Read/Write
Reset Value: 1000 0000 (80h)
1: The free running counter rolled over from FFFFh
to 0000h. To clear this bit, first read the SR reg-
ister, then read or write the low byte of the CR
(CLR) register.
This is an 8-bit register that contains the high part
of the value to be compared to the CHR register.
Note: Reading or writing the ACLR register does
not clear TOF.
7
0
MSB
LSB
Bit 4 = ICF2 Input Capture Flag 2.
0: No input capture (reset value).
1: An input capture has occurred on the ICAP2
pin. To clear this bit, first read the SR register,
then read or write the low byte of the IC2R
(IC2LR) register.
OUTPUT COMPARE
(OC1LR)
1
LOW REGISTER
Read/Write
Reset Value: 0000 0000 (00h)
Bit 3 = OCF2 Output Compare Flag 2.
0: No match (reset value).
1: The content of the free running counter has
matched the content of the OC2R register. To
clear this bit, first read the SR register, then read
or write the low byte of the OC2R (OC2LR) reg-
ister.
This is an 8-bit register that contains the low part of
the value to be compared to the CLR register.
7
0
MSB
LSB
Bit 2-0 = Reserved, forced by hardware to 0.
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ST72311R, ST72511R, ST72512R, ST72532R
16-BIT TIMER (Cont’d)
OUTPUT COMPARE
(OC2HR)
2
HIGH REGISTER
ALTERNATE COUNTER HIGH REGISTER
(ACHR)
Read/Write
Reset Value: 1000 0000 (80h)
Read Only
Reset Value: 1111 1111 (FFh)
This is an 8-bit register that contains the high part
of the value to be compared to the CHR register.
This is an 8-bit register that contains the high part
of the counter value.
7
0
7
0
MSB
LSB
MSB
LSB
OUTPUT COMPARE
(OC2LR)
2
LOW REGISTER
ALTERNATE COUNTER LOW REGISTER
(ACLR)
Read/Write
Reset Value: 0000 0000 (00h)
Read Only
Reset Value: 1111 1100 (FCh)
This is an 8-bit register that contains the low part of
the value to be compared to the CLR register.
This is an 8-bit register that contains the low part of
the counter value. A write to this register resets the
counter. An access to this register after an access
to SR register does not clear the TOF bit in SR
register.
7
0
MSB
LSB
7
0
COUNTER HIGH REGISTER (CHR)
MSB
LSB
Read Only
Reset Value: 1111 1111 (FFh)
INPUT CAPTURE 2 HIGH REGISTER (IC2HR)
This is an 8-bit register that contains the high part
of the counter value.
Read Only
Reset Value: Undefined
7
0
This is an 8-bit read only register that contains the
high part of the counter value (transferred by the
Input Capture 2 event).
MSB
LSB
7
0
MSB
LSB
COUNTER LOW REGISTER (CLR)
Read Only
Reset Value: 1111 1100 (FCh)
This is an 8-bit register that contains the low part of
the countervalue. A write to this register resets the
counter. An access to this register after accessing
the SR register clears the TOF bit.
INPUT CAPTURE 2 LOW REGISTER (IC2LR)
Read Only
Reset Value: Undefined
This is an 8-bit read only register that contains the
low part of the counter value (transferred by the In-
put Capture 2 event).
7
0
MSB
LSB
7
0
MSB
LSB
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ST72311R, ST72511R, ST72512R, ST72532R
16-BIT TIMER (Cont’d)
Table 19. 16-Bit Timer Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
Timer A: 32 CR1
ICIE
0
OCIE
0
TOIE
0
FOLV2
0
FOLV1
0
OLVL2
0
IEDG1
0
OLVL1
0
Timer B: 42 Reset Value
Timer A: 31 CR2
OC1E
0
OC2E
0
OPM
0
PWM
0
CC1
0
CC0
0
IEDG2
0
EXEDG
0
Timer B: 41 Reset Value
Timer A: 33 SR
ICF1
0
OCF1
0
TOF
0
ICF2
0
OCF2
0
-
-
-
Timer B: 43 Reset Value
0
0
0
Timer A: 34 ICHR1
MSB
-
LSB
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Timer B: 44 Reset Value
Timer A: 35 ICLR1
MSB
-
LSB
-
Timer B: 45 Reset Value
Timer A: 36 OCHR1
MSB
-
LSB
-
Timer B: 46 Reset Value
Timer A: 37 OCLR1
MSB
-
LSB
-
Timer B: 47 Reset Value
Timer A: 3E OCHR2
MSB
-
LSB
-
Timer B: 4E Reset Value
Timer A: 3F OCLR2
MSB
-
LSB
-
Timer B: 4F Reset Value
Timer A: 38 CHR
MSB
1
LSB
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
Timer B: 48 Reset Value
Timer A: 39 CLR
MSB
1
LSB
0
Timer B: 49 Reset Value
Timer A: 3A ACHR
MSB
1
LSB
1
Timer B: 4A Reset Value
Timer A: 3B ACLR
MSB
1
LSB
0
1
-
1
-
1
-
1
-
1
-
0
-
Timer B: 4B Reset Value
Timer A: 3C ICHR2
MSB
-
LSB
-
Timer B: 4C Reset Value
Timer A: 3D ICLR2
MSB
-
LSB
-
-
-
-
-
-
-
Timer B: 4D Reset Value
78/164
ST72311R, ST72511R, ST72512R, ST72532R
10.5.3 General description
10.5 SERIAL PERIPHERAL INTERFACE (SPI)
10.5.1 Introduction
The Serial Peripheral Interface (SPI) allows full-
duplex, synchronous, serial communication with
external devices. An SPI system may consist of a
master and one or more slaves or a system in
which devices may be either masters or slaves.
The SPI is connected to external devices through
4 alternate pins:
– MISO: Master In Slave Out pin
– MOSI: Master Out Slave In pin
– SCK: Serial Clock pin
The SPI is normally used for communication be-
tween the microcontroller and external peripherals
or another microcontroller.
– SS: Slave select pin
Refer to the Pin Description chapter for the device-
specific pin-out.
A basic example of interconnections between a
single master and a single slave is illustrated on
Figure 46.
10.5.2 Main Features
The MOSI pins are connected together as are
MISO pins. In this way data is transferred serially
between master and slave (most significant bit
first).
■ Full duplex, three-wire synchronous transfers
■ Master or slave operation
■ Four master mode frequencies
■ Maximum slave mode frequency = fCPU/2.
■ Four programmable master bit rates
■ Programmable clock polarity and phase
■ End of transfer interrupt flag
When the master device transmits data to a slave
device via MOSI pin, the slave device responds by
sending data to the master device via the MISO
pin. This implies full duplex transmission with both
data out and data in synchronized with the same
clock signal (which is provided by the master de-
vice via the SCK pin).
■ Write collision flag protection
■ Master mode fault protection capability.
Thus, the byte transmitted is replaced by the byte
received and eliminates the need for separate
transmit-empty and receiver-full bits. A status flag
is used to indicate that the I/O operation is com-
plete.
Four possible data/clock timing relationships may
be chosen (see Figure 49) but master and slave
must be programmed with the same timing mode.
Figure 46. Serial Peripheral Interface Master/Slave
MASTER
SLAVE
MSBit
LSBit
MSBit
LSBit
MISO
MOSI
MISO
MOSI
8-BIT SHIFT REGISTER
8-BIT SHIFT REGISTER
SPI
CLOCK
GENERATOR
SCK
SS
SCK
SS
+5V
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ST72311R, ST72511R, ST72512R, ST72532R
SERIAL PERIPHERAL INTERFACE (Cont’d)
Figure 47. Serial Peripheral Interface Block Diagram
Internal Bus
Read
DR
IT
Read Buffer
request
MOSI
SR
MISO
8-Bit Shift Register
Write
MODF
WCOL
SPIF
-
-
-
-
-
SPI
STATE
CONTROL
SCK
SS
CR
SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0
MASTER
CONTROL
SERIAL
CLOCK
GENERATOR
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ST72311R, ST72511R, ST72512R, ST72532R
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.5.4 Functional Description
In this configuration the MOSI pin is a data output
and to the MISO pin is a data input.
Figure 46 shows the serial peripheral interface
(SPI) block diagram.
This interface contains 3 dedicated registers:
– A Control Register (CR)
Transmit sequence
The transmit sequence begins when a byte is writ-
ten the DR register.
– A Status Register (SR)
The data byte is parallel loaded into the 8-bit shift
register (from the internal bus) during a write cycle
and then shifted out serially to the MOSI pin most
significant bit first.
– A Data Register (DR)
Refer to the CR, SR and DR registers in Section
10.5.7for the bit definitions.
10.5.4.1 Master Configuration
When data transfer is complete:
– The SPIF bit is set by hardware
In a master configuration, the serial clock is gener-
ated on the SCK pin.
– An interrupt is generated if the SPIE bit is set
and the I bit in the CCR register is cleared.
Procedure
– Select the SPR0 & SPR1 bits to define the se-
rial clock baud rate (see CR register).
During the last clock cycle the SPIF bit is set, a
copy of the data byte received in the shift register
is moved to a buffer. When the DR register is read,
the SPI peripheral returns this buffered value.
– Select the CPOL and CPHA bits to define one
of the four relationships between the data
transfer and the serial clock (see Figure 49).
Clearing the SPIF bit is performed by the following
software sequence:
– The SS pin must be connected to a high level
signal during the complete byte transmit se-
quence.
1. An access to the SR register while the SPIF bit
is set
– The MSTR and SPE bits must be set (they re-
main set only if the SS pin is connected to a
high level signal).
2. A write or a read of the DR register.
Note: While the SPIF bit is set, all writes to the DR
register are inhibited until the SR register is read.
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ST72311R, ST72511R, ST72512R, ST72532R
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.5.4.2 Slave Configuration
When data transfer is complete:
– The SPIF bit is set by hardware
In slave configuration, the serial clock is received
on the SCK pin from the master device.
– An interrupt is generated if SPIE bit is set and
I bit in CCR register is cleared.
The value of the SPR0 & SPR1 bits is not used for
the data transfer.
During the last clock cycle the SPIF bit is set, a
copy of the data byte received in the shift register
is moved to a buffer. When the DR register is read,
the SPI peripheral returns this buffered value.
Procedure
– For correct data transfer, the slave device
must be in the same timing mode as the mas-
ter device (CPOL and CPHA bits). See Figure
49.
Clearing the SPIF bit is performed by the following
software sequence:
1. An access to the SR register while the SPIF bit
is set.
– The SS pin must be connected to a low level
signal during the complete byte transmit se-
quence.
2. A write or a read of the DR register.
– Clear the MSTR bit and set the SPE bit to as-
sign the pins to alternate function.
Notes: While the SPIF bit is set, all writes to the
DR register are inhibited until the SR register is
read.
In this configuration the MOSI pin is a data input
and the MISO pin is a data output.
The SPIF bit can be cleared during a second
transmission; however, it must be cleared before
the second SPIF bit in order to prevent an overrun
condition (see Section 10.5.4.6).
Transmit Sequence
The data byte is parallel loaded into the 8-bit shift
register (from the internal bus) during a write cycle
and then shifted out serially to the MISO pin most
significant bit first.
Depending on the CPHA bit, the SS pin has to be
set to write to the DR register between each data
byte transfer to avoid a write collision (see Section
10.5.4.4).
The transmit sequence begins when the slave de-
vice receives the clock signal and the most signifi-
cant bit of the data on its MOSI pin.
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ST72311R, ST72511R, ST72512R, ST72532R
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.5.4.3 Data Transfer Format
The master device applies data to its MOSI pin-
clock edge before the capture clock edge.
During an SPI transfer, data is simultaneously
transmitted (shifted out serially) and received
(shifted in serially). The serial clock is used to syn-
chronize the data transfer during a sequence of
eight clock pulses.
CPHA bit is set
The second edge on the SCK pin (falling edge if
the CPOL bit is reset, rising edge if the CPOL bit is
set) is the MSBit capture strobe. Data is latched on
the occurrence of the second clock transition.
The SS pin allows individual selection of a slave
device; the other slave devices that are not select-
ed do not interfere with the SPI transfer.
No write collision should occur even if the SS pin
stays low during a transfer of several bytes (see
Figure 48).
Clock Phase and Clock Polarity
Four possible timing relationships may be chosen
by software, using the CPOL and CPHA bits.
CPHA bit is reset
The CPOL (clock polarity) bit controls the steady
state value of the clock when no data is being
transferred. This bit affects both master and slave
modes.
The firstedge on the SCK pin (falling edge if CPOL
bit is set, rising edge if CPOL bit is reset) is the
MSBit capture strobe. Data is latched on the oc-
currence of the first clock transition.
The combination between the CPOL and CPHA
(clock phase) bits selects the data capture clock
edge.
The SS pin must be toggled high and low between
each byte transmitted (see Figure 48).
To protect the transmission from a write collision a
low value on the SS pin of a slave device freezes
the data in its DR register and does not allow it to
be altered. Therefore the SS pin must be high to
write a new data byte in the DR without producing
a write collision.
Figure 49, shows an SPI transfer with the four
combinations of the CPHA and CPOL bits. The di-
agram may be interpreted as a master or slave
timing diagram where the SCK pin, the MISO pin,
the MOSI pin are directly connected between the
master and the slave device.
The SS pin is the slave device select input and can
be driven by the master device.
Figure 48. CPHA / SS Timing Diagram
Byte 3
Byte 2
MOSI/MISO
Master SS
Byte 1
Slave SS
(CPHA=0)
Slave SS
(CPHA=1)
VR02131A
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ST72311R, ST72511R, ST72512R, ST72532R
SERIAL PERIPHERAL INTERFACE (Cont’d)
Figure 49. Data Clock Timing Diagram
CPHA =1
SCLK (with
CPOL = 1)
SCLK (with
CPOL = 0)
Bit 4
Bit 4
Bit3
Bit3
Bit 2
Bit 2
Bit 1
Bit 1
LSBit
LSBit
MSBit
MSBit
Bit 6
Bit 6
Bit 5
Bit 5
MISO
(from master)
MOSI
(from slave)
SS
(to slave)
CAPTURE STROBE
CPHA =0
CPOL = 1
CPOL = 0
Bit 4
Bit 4
Bit3
Bit 2
Bit 2
Bit 1
Bit 1
LSBit
LSBit
MSBit
Bit 6
Bit 6
Bit 5
Bit 5
MISO
(from master)
MSBit
Bit3
MOSI
(from slave)
SS
(to slave)
CAPTURE STROBE
Note: This figure should not be used as a replacement for parametric information.
Refer to the Electrical Characteristics chapter.
VR02131B
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ST72311R, ST72511R, ST72512R, ST72532R
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.5.4.4 Write Collision Error
When the CPHA bit is reset:
A write collision occurs when the software tries to
write to the DR register while a data transfer is tak-
ing place with an external device. When this hap-
pens, the transfer continues uninterrupted; and
the software write will be unsuccessful.
Data is latched on the occurrence of the first clock
transition. The slave device does not have any
way of knowing when that transition will occur;
therefore, the slave device collision occurs when
software attempts to write the DR register after its
SS pin has been pulled low.
Write collisions can occur both in master and slave
mode.
For this reason, the SS pin must be high, between
each data byte transfer, to allow the CPU to write
in the DR register without generating a write colli-
sion.
Note: a ”read collision” will never occur since the
received data byte is placed in a buffer in which
access is always synchronous with the MCU oper-
ation.
In Slave mode
In Master mode
When the CPHA bit is set:
Collision in the master device is defined as a write
of the DR register while the internal serial clock
(SCK) is in the process of transfer.
The slave device will receive a clock (SCK) edge
prior to the latch of the first data transfer. This first
clock edge will freeze the data in the slave device
DR register and output the MSBit on to the exter-
nal MISO pin of the slave device.
The SS pin signal must be always high on the
master device.
The SS pin low state enables the slave device but
the output of the MSBit onto the MISO pin does
not take place until the first data transfer clock
edge.
WCOL bit
The WCOL bit in the SR register is set if a write
collision occurs.
No SPI interrupt is generated when the WCOL bit
is set (the WCOL bit is a status flag only).
Clearing the WCOL bit is done through a software
sequence (see Figure 50).
Figure 50. Clearing the WCOL bit (Write Collision Flag) Software Sequence
Clearing sequence after SPIF = 1 (end of a data byte transfer)
Read SR
Read SR
1st Step
2nd Step
OR
THEN
THEN
SPIF =0
WCOL=0
SPIF =0
WCOL=0 if no transfer has started
WCOL=1 if a transfer has started
before the 2nd step
Read DR
Write DR
Clearing sequence before SPIF = 1 (during a data byte transfer)
Read SR
1st Step
THEN
Note: Writing in DR register in-
2nd Step
Read DR
stead of reading in it do not reset
WCOL bit
WCOL=0
85/164
ST72311R, ST72511R, ST72512R, ST72532R
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.5.4.5 Master Mode Fault
may be restored to their original state during or af-
ter this clearing sequence.
Master mode fault occurs when the master device
has its SS pin pulled low, then the MODF bit is set.
Hardware does not allow the user to set the SPE
and MSTR bits while the MODF bit is set except in
the MODF bit clearing sequence.
Master mode fault affects the SPI peripheral in the
following ways:
In a slave device the MODF bit can not be set, but
in a multi master configuration the device can be in
slave mode with this MODF bit set.
– The MODF bit is set and an SPI interrupt is
generated if the SPIE bit is set.
– The SPE bit is reset. This blocks all output
from the device and disables the SPI periph-
eral.
The MODF bit indicates that there might have
been amulti-master conflict for system control and
allows a proper exit from system operation to a re-
set or default system state using an interrupt rou-
tine.
– The MSTR bit is reset, thus forcing the device
into slave mode.
Clearing the MODF bit is done through a software
sequence:
10.5.4.6 Overrun Condition
An overrun condition occurs when the master de-
vice has sent several data bytes and the slave de-
vice has not cleared the SPIF bit issuing from the
previous data byte transmitted.
1. A read or write access to the SR register while
the MODF bit is set.
2. A write to the CR register.
In this case, the receiver buffer contains the byte
sent after the SPIF bit was last cleared. A read to
the DR register returns this byte. All other bytes
are lost.
Notes: To avoid any multiple slave conflicts in the
case of a system comprising several MCUs, the
SS pin must be pulled high during the clearing se-
quence of the MODF bit. The SPE and MSTR bits
This condition is not detected by the SPI peripher-
al.
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ST72311R, ST72511R, ST72512R, ST72532R
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.5.4.7 Single Master and Multimaster Configurations
There are two types of SPI systems:
– Single Master System
For more security, the slave device may respond
to the master with the received data byte. Then the
master will receive the previous byte back from the
slave device if all MISO and MOSI pins are con-
nected and the slave has not written its DR regis-
ter.
– Multimaster System
Single Master System
Other transmission security methods can use
ports for handshake lines or data bytes with com-
mand fields.
A typical single master system may be configured,
using an MCU as the master and four MCUs as
slaves (see Figure 51).
Multi-master System
The master device selects the individual slave de-
vices by using four pins of a parallel port to control
the four SS pins of the slave devices.
A multi-master system may also be configured by
the user. Transfer of master control could be im-
plemented using a handshake method through the
I/O ports or by an exchange of code messages
through the serial peripheral interface system.
The SS pins are pulled high during reset since the
master device ports will be forced to be inputs at
that time, thus disabling the slave devices.
The multi-master system is principally handled by
the MSTR bit in the CR register and the MODF bit
in the SR register.
Note: To prevent a bus conflict on the MISO line
the master allows only one active slave device
during a transmission.
Figure 51. Single Master Configuration
SS
SS
SS
SS
SCK
SCK
Slave
SCK
Slave
SCK
Slave
MCU
Slave
MCU
MCU
MCU
MOSI MISO
MOSI MISO
MOSI MISO
MOSI MISO
MOSI MISO
SCK
Master
MCU
5V
SS
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ST72311R, ST72511R, ST72512R, ST72532R
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.5.5 Low Power Modes
Mode
WAIT
Description
No effect on SPI.
SPI interrupt events cause the device to exit from WAIT mode.
SPI registers are frozen.
HALT
In HALT mode, the SPI is inactive. SPI operation resumes when the MCU is woken up by an interrupt with
“exit from HALT mode” capability.
10.5.6 Interrupts
Enable
Control from
Bit
Exit
Exit
from
Halt
Event
Flag
Interrupt Event
Wait
Yes
Yes
SPI End of Transfer Event
Master Mode Fault Event
SPIF
No
No
SPIE
MODF
Note: The SPI interrupt events are connected to
the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding
Enable Control Bit is set and the interrupt mask in
the CC register is reset (RIM instruction).
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ST72311R, ST72511R, ST72512R, ST72532R
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.5.7 Register Description
CONTROL REGISTER (CR)
Read/Write
Bit 3 = CPOL Clock polarity.
This bit is set and cleared by software. This bit de-
termines the steady state of the serial Clock. The
CPOL bit affects both the master and slave
modes.
0: The steady state is a low value at the SCK pin.
1: The steady state is a high value at the SCK pin.
Reset Value: 0000xxxx (0xh)
7
0
SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0
Bit 7 = SPIE Serial peripheral interrupt enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SPI interrupt is generated whenever SPIF=1
or MODF=1 in the SR register
Bit 2 = CPHA Clock phase.
This bit is set and cleared by software.
0: The first clock transition is the first data capture
edge.
1: The second clock transition is the first capture
edge.
Bit 6 = SPE Serial peripheral output enable.
This bit is set and cleared by software. It is also
cleared by hardware when, in master mode, SS=0
(see Section 10.5.4.5 ”Master Mode Fault” on
page 85).
Bit 1:0 = SPR[1:0] Serial peripheral rate.
These bits are set and cleared by software.Used
with the SPR2 bit, they select one of six baud rates
to be used as the serial clock when the device is a
master.
0: I/O port connected to pins
1: SPI alternate functions connected to pins
The SPE bit is cleared by reset, so the SPI periph-
eral is not initially connected to the external pins.
These 2 bits have no effect in slave mode.
Table 20. Serial Peripheral Baud Rate
Bit 5 = SPR2 Divider Enable.
Serial Clock
SPR2 SPR1 SPR0
this bit is set and cleared by software and it is
cleared by reset. It is used with the SPR[1:0] bits to
set the baud rate. Refer to Table 20.
0: Divider by 2 enabled
f
f
/2
/8
1
0
0
1
0
0
0
0
0
1
1
1
0
0
1
0
0
1
CPU
CPU
f
f
f
/16
/32
/64
CPU
CPU
CPU
1: Divider by 2 disabled
f
/128
CPU
Bit 4 = MSTR Master.
This bit is set and cleared by software. It is also
cleared by hardware when, in master mode, SS=0
(see Section 10.5.4.5 ”Master Mode Fault” on
page 85).
0: Slave mode is selected
1: Master mode is selected, the function of the
SCK pin changes from an input to an output and
the functions of the MISO and MOSI pins are re-
versed.
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ST72311R, ST72511R, ST72512R, ST72532R
SERIAL PERIPHERAL INTERFACE (Cont’d)
STATUS REGISTER (SR)
Read Only
DATA I/O REGISTER (DR)
Read/Write
Reset Value: 0000 0000 (00h)
Reset Value: Undefined
7
0
-
7
0
SPIF
WCOL
-
MODF
-
-
-
D7
D6
D5
D4
D3
D2
D1
D0
Bit 7 = SPIF Serial Peripheral data transfer flag.
This bit is set by hardware when a transfer has
been completed. An interrupt is generated if
SPIE=1 in the CR register. It is cleared by a soft-
ware sequence (an access to the SR register fol-
lowed by a read or write to the DR register).
0: Data transfer is in progress or has been ap-
proved by a clearing sequence.
The DR register is used to transmit and receive
data on the serial bus. In the master device only a
write to this register will initiate transmission/re-
ception of another byte.
Notes: During the last clock cycle the SPIF bit is
set, a copy of the received data byte in the shift
register is moved to a buffer. When the user reads
the serial peripheral data I/O register, the buffer is
actually being read.
1: Data transfer between the device and an exter-
nal device has been completed.
Warning:
Note: While the SPIF bit is set, all writes to the DR
register are inhibited.
A write to the DR register places data directly into
the shift register for transmission.
A write to the the DR register returns the value lo-
cated in the buffer and not the contents of the shift
register (See Figure 47 ).
Bit 6 = WCOL Write Collision status.
This bit is set by hardware when a write to the DR
register is done during a transmit sequence. It is
cleared by a software sequence (see Figure 50).
0: No write collision occurred
1: A write collision has been detected
Bit 5 = Unused.
Bit 4 = MODF Mode Fault flag.
This bit is set by hardware when the SS pin is
pulled low in master mode (see Section 10.5.4.5
”Master Mode Fault” on page 85). An SPI interrupt
can be generated if SPIE=1 in the CR register.
This bit is cleared by a software sequence (An ac-
cess to the SR register while MODF=1 followed by
a write to the CR register).
0: No master mode fault detected
1: A fault in master mode has been detected
Bits 3-0 = Unused.
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SERIAL PERIPHERAL INTERFACE (Cont’d)
Table 21. SPI Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
SPIDR
Reset Value
MSB
x
LSB
x
0021h
0022h
0023h
x
x
x
x
x
x
SPICR
Reset Value
SPIE
0
SPE
0
SPR2
0
MSTR
0
CPOL
x
CPHA
x
SPR1
x
SPR0
x
SPISR
Reset Value
SPIF
0
WCOL
0
MODF
0
0
0
0
0
0
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ST72311R, ST72511R, ST72512R, ST72532R
10.6 SERIAL COMMUNICATIONS INTERFACE (SCI)
10.6.1 Introduction
10.6.3 General Description
The Serial Communications Interface (SCI) offers
a flexible means of full-duplex data exchange with
external equipment requiring an industry standard
NRZ asynchronous serial data format. The SCI of-
fers a very wide range of baud rates using two
baud rate generator systems.
The interface is externally connected to another
device by two pins (see Figure 53):
– TDO: Transmit Data Output. When the transmit-
ter is disabled, the output pin returns to its I/O
port configuration. When the transmitter is ena-
bled and nothing is to be transmitted, the TDO
pin is at high level.
10.6.2 Main Features
■ Full duplex, asynchronous communications
■ NRZ standard format (Mark/Space)
■ Dual baud rate generator systems
■ Independently programmable transmit and
receive baud rates up to 250K baud.
■ Programmable data word length (8 or 9 bits)
– RDI: Receive Data Input is the serial data input.
Oversampling techniques are used for data re-
covery by discriminating between valid incoming
data and noise.
Through this pins, serial data is transmitted and re-
ceived as frames comprising:
– An Idle Line prior to transmission or reception
– A start bit
■ Receive buffer full, Transmit buffer empty and
End of Transmission flags
– A data word (8 or 9 bits) least significant bit first
– A Stop bit indicating that the frame is complete.
Thisinterfaceusestwo typesofbaudrategenerator:
■ Two receiver wake-up modes:
– Address bit (MSB)
– Idle line
■ Muting functionformultiprocessorconfigurations
■ Separate enable bits for Transmitter and
– A conventional type for commonly-used baud
rates,
Receiver
– An extended type with a prescaler offeringa very
wide range of baud rates even with non-standard
oscillator frequencies.
■ Three error detection flags:
– Overrun error
– Noise error
– Frame error
■ Five interrupt sources with flags:
– Transmit data register empty
– Transmission complete
– Receive data register full
– Idle line received
– Overrun error detected
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ST72311R, ST72511R, ST72512R, ST72532R
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
Figure 52. SCI Block Diagram
Write
Read
(DATA REGISTER) DR
Received Data Register (RDR)
Received Shift Register
Transmit Data Register (TDR)
TDO
Transmit Shift Register
RDI
CR1
R8
-
-
T8
M
WAKE
-
-
WAKE
UP
TRANSMIT
RECEIVER
CLOCK
RECEIVER
CONTROL
CONTROL
UNIT
SR
CR2
TIE TCIE RIE ILIE TE RE RWU SBK
TDRE TC RDRF
IDLE OR NF FE
-
SCI
INTERRUPT
CONTROL
TRANSMITTER
CLOCK
TRANSMITTER RATE
CONTROL
f
CPU
/2
/PR
/16
BRR
SCP1SCP0SCT2 SCT1 SCT0SCR2SCR1SCR0
RECEIVER RATE
CONTROL
CONVENTIONAL BAUD RATE GENERATOR
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ST72311R, ST72511R, ST72512R, ST72532R
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.6.4 Functional Description
10.6.4.1 Serial Data Format
The block diagram of the Serial Control Interface,
is shown in Figure 52. It contains 6 dedicated reg-
isters:
Word length may be selected as being either 8 or 9
bits by programming the M bit in the CR1 register
(see Figure 52).
– Two control registers (CR1 & CR2)
– A status register (SR)
The TDO pin is in low state during the start bit.
The TDO pin is in high state during the stop bit.
– A baud rate register (BRR)
An Idle character is interpreted as an entire frame
of “1”s followed by the start bit of the next frame
which contains data.
– An extended prescaler receiver register (ERPR)
– Anextendedprescalertransmitter register(ETPR)
A Break character is interpreted on receiving “0”s
for some multiple of the frame period. At the end of
the last break frame the transmitter inserts an ex-
tra “1” bit to acknowledge the start bit.
Refer to the register descriptions in Section
10.6.7for the definitions of each bit.
Transmission and reception are driven by their
own baud rate generator.
Figure 53. Word length programming
9-bit Word length (M bit is set)
Possible
Next Data Frame
Parity
Data Frame
Start
Bit
Next
Start
Bit
Stop
Bit
Bit2
Bit0
Bit1
Bit3
Bit4 Bit5
Bit6
Bit7 Bit8
Bit
Start
Bit
Idle Frame
Start
Bit
Extra
’1’
Break Frame
8-bit Word length (M bit is reset)
Possible
Parity
Next Data Frame
Data Frame
Start
Bit
Next
Start
Bit
Stop
Bit
Bit2
Bit5
Bit6
Bit0
Bit1
Bit3
Bit4
Bit7
Bit
Start
Bit
Idle Frame
Start
Bit
Extra
’1’
Break Frame
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ST72311R, ST72511R, ST72512R, ST72532R
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.6.4.2 Transmitter
When a frame transmission is complete (after the
stop bit or after the break frame) the TC bit is set
and an interrupt is generated if the TCIE is set and
the I bit is cleared in the CCR register.
The transmitter can send data words of either 8 or
9 bits depending on the M bit status. When the M
bit is set, word length is 9 bits and the 9th bit (the
MSB) has to be stored in the T8 bit in the CR1 reg-
ister.
Clearing the TC bit is performed by the following
software sequence:
1. An access to the SR register
2. A write to the DR register
Character Transmission
During an SCI transmission, data shifts out least
significant bit first on the TDO pin. In this mode,
the DR register consists of a buffer (TDR) between
the internal bus and the transmit shift register (see
Figure 52).
Note: The TDRE and TC bits are cleared by the
same software sequence.
Break Characters
Setting the SBK bit loads the shift register with a
break character. The break frame length depends
on the M bit (see Figure 53).
Procedure
– Select the M bit to define the word length.
As long as the SBK bit is set, the SCI send break
frames to the TDO pin. After clearing this bit by
software the SCI insert a logic 1 bit at the end of
the last break frame to guarantee the recognition
of the start bit of the next frame.
– Select the desired baud rate using the BRR and
the ETPR registers.
– Set the TE bit to assign the TDO pin to the alter-
nate function and to send a idle frame as first
transmission.
Idle Characters
– Access the SR register and write the data to
send in the DR register (this sequence clears the
TDRE bit).Repeat this sequencefor each data to
be transmitted.
Setting the TE bit drives the SCI to send an idle
frame before the first data frame.
Clearing and then setting the TE bit during a trans-
mission sends an idle frame after the current word.
Clearing the TDRE bit is always performed by the
following software sequence:
1. An access to the SR register
Note: Resetting and setting the TE bit causes the
data in the TDR register to be lost. Therefore the
best time to toggle the TE bit is when the TDRE bit
is set i.e. before writing the next byte in the DR.
2. A write to the DR register
The TDRE bit is set by hardware and it indicates:
– The TDR register is empty.
– The data transfer is beginning.
– The next data can be written in the DR register
without overwriting the previous data.
This flag generates an interrupt if the TIE bit is set
and the I bit is cleared in the CCR register.
When a transmission is taking place, a write in-
struction to the DR register stores the data in the
TDR register and which is copied in the shift regis-
ter at the end of the current transmission.
When no transmission is taking place, a write in-
struction to the DR register places the data directly
in the shift register, the data transmission starts,
and the TDRE bit is immediately set.
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ST72311R, ST72511R, ST72512R, ST72532R
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.6.4.3 Receiver
Overrun Error
The SCI can receive data words of either 8 or 9
bits. When the M bit is set, word length is 9 bits
and the MSB is stored in the R8 bit in the CR1 reg-
ister.
An overrun error occurs when a character is re-
ceived when RDRF has not been reset. Data can
not be transferred from the shift register to the
TDR register as long as the RDRF bit is not
cleared.
Character reception
When a overrun error occurs:
– The OR bit is set.
During a SCI reception, data shifts in least signifi-
cant bit first through the RDI pin. In this mode, DR
register consists in a buffer (RDR) between the in-
ternal bus and the received shift register (see Fig-
ure 52).
– The RDR content will not be lost.
– The shift register will be overwritten.
– An interrupt is generated if the RIE bit is set and
the I bit is cleared in the CCR register.
Procedure
– Select the M bit to define the word length.
The OR bit is reset by an access to the SR register
followed by a DR register read operation.
– Select the desired baud rate using the BRR and
the ERPR registers.
Noise Error
– Set the RE bit, this enables the receiver which
begins searching for a start bit.
Oversampling techniques are used for data recov-
ery by discriminating between valid incoming data
and noise.
When a character is received:
– The RDRF bit is set. It indicates that the content
of the shift register is transferred to the RDR.
When noise is detected in a frame:
– The NF is set at the rising edge of the RDRF bit.
– An interrupt is generated if the RIE bit is set and
the I bit is cleared in the CCR register.
– Data is transferred from the Shift register to the
DR register.
– The error flags can be set if a frame error, noise
or an overrun error has been detected during re-
ception.
– No interrupt is generated. However this bit rises
at the same time as the RDRF bit which itself
generates an interrupt.
Clearing theRDRF bit isperformedby thefollowing
software sequence done by:
The NF bit is reset by a SR register read operation
followed by a DR register read operation.
1. An access to the SR register
2. A read to the DR register.
Framing Error
A framing error is detected when:
The RDRF bit must be cleared before the endof the
reception of the next character to avoid an overrun
error.
– The stop bit is not recognized on reception at the
expected time, following either a de-synchroni-
zation or excessive noise.
Break Character
– A break is received.
When a break character is received, the SPI han-
dles it as a framing error.
When the framing error is detected:
– the FE bit is set by hardware
Idle Character
– Data is transferred from the Shift register to the
DR register.
When a idle frame is detected, there is the same
procedure as a data received character plus an in-
terrupt if the ILIE bit is set and the I bit is cleared in
the CCR register.
– No interrupt is generated. However this bit rises
at the same time as the RDRF bit which itself
generates an interrupt.
The FE bit is reset by a SR register read operation
followed by a DR register read operation.
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SERIAL COMMUNICATIONS INTERFACE (Cont’d)
Figure 54. SCI Baud Rate and Extended Prescaler Block Diagram
EXTENDED PRESCALER TRANSMITTERRATE CONTROL
ETPR
EXTENDED TRANSMITTER PRESCALER REGISTER
ERPR
EXTENDED RECEIVER PRESCALER REGISTER
EXTENDED PRESCALER RECEIVER RATE CONTROL
EXTENDED PRESCALER
f
TRANSMITTER
CLOCK
CPU
TRANSMITTER RATE
CONTROL
/2
/PR
/16
BRR
SCP1SCP0SCT2 SCT1 SCT0SCR2SCR1SCR0
RECEIVER
CLOCK
RECEIVER RATE
CONTROL
CONVENTIONAL BAUD RATE GENERATOR
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ST72311R, ST72511R, ST72512R, ST72532R
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.6.4.4 Conventional Baud Rate Generation
than zero. The baud rates are calculated as fol-
lows:
The baud rate for the receiver and transmitter (Rx
and Tx) are set independently and calculated as
follows:
f
f
CPU
CPU
Rx =
Tx =
f
f
16 ERPR
16 ETPR
CPU
CPU
*
*
Rx =
(32 PR) RR
Tx =
(32 PR) TR
*
*
*
*
with:
with:
ETPR = 1,..,255 (see ETPR register)
PR = 1, 3, 4 or 13 (see SCP0 & SCP1 bits)
TR = 1, 2, 4, 8, 16, 32, 64,128
ERPR = 1,.. 255 (see ERPR register)
10.6.4.6 Receiver Muting and Wake-up Feature
(see SCT0, SCT1 & SCT2 bits)
RR = 1, 2, 4, 8, 16, 32, 64,128
In multiprocessor configurations it is often desira-
ble that only the intended message recipient
should actively receive the full message contents,
thus reducing redundant SCI service overhead for
all non addressed receivers.
(see SCR0,SCR1 & SCR2 bits)
All this bits are in the BRR register.
Example: If f
PR=13 and TR=RR=1, the transmit and receive
baud rates are 19200 baud.
is 8 MHz (normal mode) and if
The non addressed devices may be placed in
sleep mode by means of the muting function.
CPU
Setting the RWU bit by software puts the SCI in
sleep mode:
Note: the baud rate registers MUST NOT be
changed while the transmitter or the receiver is en-
abled.
All the reception status bits can not be set.
All the receive interrupt are inhibited.
10.6.4.5 Extended Baud Rate Generation
A muted receiver may be awakened by one of the
following two ways:
The extended prescaler option gives a very fine
tuning onthe baud rate, using a 255 value prescal-
er, whereas the conventional Baud Rate Genera-
tor retains industry standard software compatibili-
ty.
– by Idle Line detection if the WAKE bit is reset,
– by Address Mark detection if the WAKE bit is set.
Receiver wakes-up by Idle Line detection when
the Receive line has recognised an Idle Frame.
Then the RWU bit is reset by hardware but the
IDLE bit is not set.
The extended baud rate generator block diagram
is described in the Figure 54.
The output clock rate sent to the transmitter or to
the receiver will be the output from the 16 divider
divided by a factor ranging from 1 to 255 set in the
ERPR or the ETPR register.
Receiver wakes-up by Address Mark detection
when it received a “1” as the most significant bit of
a word, thus indicating that the message is an ad-
dress. The reception of this particular word wakes
up the receiver, resets the RWU bit and sets the
RDRF bit, which allows the receiver to receive this
word normally and to use it as an address word.
Note: the extended prescaler is activated by set-
ting the ETPR or ERPR register to a value other
98/164
ST72311R, ST72511R, ST72512R, ST72532R
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.6.5 Low Power Modes
Mode
Description
No effect on SCI.
WAIT
SCI interrupts cause the device to exit from Wait mode.
SCI registers are frozen.
HALT
In Halt mode, the SCI stops transmitting/receiving until Halt mode is exited.
10.6.6 Interrupts
Enable
Control from
Bit
Exit
Exit
from
Halt
Event
Flag
Interrupt Event
Wait
Yes
Yes
Yes
Yes
Yes
Transmit Data Register Empty
Transmission Complete
TDRE
TC
TIE
No
No
No
No
No
TCIE
Received Data Ready to be Read
Overrrun Error Detected
Idle Line Detected
RDRF
OR
RIE
IDLE
ILIE
The SCI interrupt events are connected to the
same interrupt vector (see Interrupts chapter).
These events generate an interrupt if the corre-
sponding Enable Control Bit is set and the inter-
rupt mask in the CC register is reset (RIM instruc-
tion).
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SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.6.7 Register Description
STATUS REGISTER (SR)
Note: The IDLE bit will not be set again until the
RDRF bit has been set itself (i.e. a new idle line oc-
curs). This bit is not set by an idle line when the re-
ceiver wakes up from wake-up mode.
Read Only
Reset Value: 1100 0000 (C0h)
Bit 3 = OR Overrun error.
7
0
-
This bit is set by hardware when the word currently
being received in the shift register is ready to be
transferred into the RDR register while RDRF=1.
An interrupt is generated if RIE=1 in the CR2 reg-
ister. It is cleared by hardware when RE=0 by a
software sequence (an access to the SR register
followed by a read to the DR register).
0: No Overrun error
TDRE
TC
RDRF IDLE
OR
NF
FE
Bit 7 = TDRE Transmit data register empty.
This bit is set by hardware when the content of the
TDR register has been transferred into the shift
register. An interrupt is generated if the TIE =1 in
the CR2 register. It is cleared by a software se-
quence (an access to the SR register followed by a
write to the DR register).
1: Overrun error is detected
Note: When this bit is set RDR register content will
not be lost but the shift register will be overwritten.
0: Data is not transferred to the shift register
1: Data is transferred to the shift register
Bit 2 = NF Noise flag.
Note: data will not be transferred to the shift regis-
ter as long as the TDRE bit is not reset.
This bit is set by hardware when noise is detected
on a received frame. It is cleared by hardware
when RE=0 by a software sequence (an access to
the SR register followed by a read to the DR regis-
ter).
Bit 6 = TC Transmission complete.
This bit is set by hardware when transmission of a
frame containing Data, a Preamble or a Break is
complete. An interrupt is generated if TCIE=1 in
the CR2 register. It is cleared by a software se-
quence (an access to the SR register followed by a
write to the DR register).
0: No noise is detected
1: Noise is detected
Note: This bit does not generate interrupt as it ap-
pears at the same time as the RDRF bit which it-
self generates an interrupt.
0: Transmission is not complete
1: Transmission is complete
Bit 1 = FE Framing error.
This bit is set by hardware when a de-synchroniza-
tion, excessive noise or a break character is de-
tected. It is cleared by hardware when RE=0 by a
software sequence (an access to the SR register
followed by a read to the DR register).
Bit 5 = RDRF Received data ready flag.
This bit is set by hardware when the content of the
RDR register has been transferred into the DR
register. An interrupt is generated if RIE=1 in the
CR2 register. It is cleared by hardware when
RE=0 or by a software sequence (an access to the
SR register followed by a read to the DR register).
0: Data is not received
0: No Framing error is detected
1: Framing error or break character is detected
Note: This bit does not generate interrupt as it ap-
pears at the same time as the RDRF bit which it-
self generates an interrupt. If the word currently
being transferred causes both frame error and
overrun error, it will be transferred and only the OR
bit will be set.
1: Received data is ready to be read
Bit 4 = IDLE Idle line detect.
This bit is set by hardware when a Idle Line is de-
tected. An interrupt is generated if the ILIE=1 in
the CR2 register. It is cleared by hardware when
RE=0 by a software sequence (an access to the
SR register followed by a read to the DR register).
0: No Idle Line is detected
Bit 0 = Unused.
1: Idle Line is detected
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ST72311R, ST72511R, ST72512R, ST72532R
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
CONTROL REGISTER 1 (CR1)
Read/Write
1: AnSCI interrupt is generated whenever TC=1 in
the SR register
Reset Value: Undefined
Bit 5 = RIE Receiver interrupt enable.
This bit is set and cleared by software.
0: interrupt is inhibited
1: An SCI interrupt is generated whenever OR=1
or RDRF=1 in the SR register
7
0
-
R8
T8
-
M
WAKE
-
-
Bit 7 = R8 Receive data bit 8.
This bit is used to store the 9th bit of the received
word when M=1.
Bit 4 = ILIE Idle line interrupt enable.
This bit is set and cleared by software.
0: interrupt is inhibited
1: An SCI interrupt is generated whenever IDLE=1
in the SR register.
Bit 6 = T8 Transmit data bit 8.
This bit is used to store the 9th bit of the transmit-
ted word when M=1.
Bit 3 = TE Transmitter enable.
This bit enables the transmitter and assigns the
TDO pin to the alternate function. It is set and
cleared by software.
0: Transmitter is disabled, the TDO pin is back to
the I/O port configuration.
Bit 4 = M Word length.
This bit determines the word length. It is set or
cleared by software.
0: 1 Start bit, 8 Data bits, 1 Stop bit
1: 1 Start bit, 9 Data bits, 1 Stop bit
1: Transmitter is enabled
Note: during transmission, a “0” pulse on the TE
bit (“0” followed by “1”) sends a preamble after the
current word.
Bit 3 = WAKE Wake-Up method.
This bit determines the SCI Wake-Up method, it is
set or cleared by software.
0: Idle Line
Bit 2 = RE Receiver enable.
This bit enables the receiver. It is set and cleared
by software.
1: Address Mark
0: Receiver is disabled, it resets the RDRF, IDLE,
OR, NF and FE bits of the SR register.
1: Receiver is enabled and begins searching for a
start bit.
CONTROL REGISTER 2 (CR2)
Read/Write
Reset Value: 0000 0000 (00h)
7
0
Bit 1 = RWU Receiver wake-up.
This bit determines if the SCI is in mute mode or
not. It is set and cleared by software and can be
cleared by hardware when a wake-up sequence is
recognized.
0: Receiver in active mode
1: Receiver in mute mode
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
Bit 7 = TIE Transmitter interrupt enable.
This bit is set and cleared by software.
0: interrupt is inhibited
1: An SCI interrupt is generated whenever
TDRE=1 in the SR register.
Bit 0 = SBK Send break.
This bit set is used to send break characters. It is
set and cleared by software.
0: No break character is transmitted
1: Break characters are transmitted
Bit 6 = TCIE Transmission complete interrupt ena-
ble
This bit is set and cleared by software.
0: interrupt is inhibited
Note: If the SBK bit is set to “1” and then to “0”, the
transmitter will send a BREAK word at the end of
the current word.
101/164
ST72311R, ST72511R, ST72512R, ST72532R
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
DATA REGISTER (DR)
Bit 5:3 = SCT[2:0] SCI Transmitter rate divisor
Read/Write
These 3 bits, in conjunction with the SCP1 & SCP0
bits define the total division applied to the bus
clock to yield the transmit rate clock inconvention-
al Baud Rate Generator mode.
Reset Value: Undefined
Contains the Received or Transmitted data char-
acter, depending on whether it is read from or writ-
ten to.
TR dividing factor
SCT2
SCT1
SCT0
1
2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
7
0
4
DR7
DR6
DR5
DR4
DR3
DR2
DR1
DR0
8
The Data register performs a double function (read
and write) since it is composed of two registers,
one for transmission (TDR) and one for reception
(RDR).
The TDR register provides the parallel interface
between the internal bus and the output shift reg-
ister (see Figure 52).
The RDR register provides the parallel interface
between the input shift register and the internal
bus (see Figure 52).
16
32
64
128
Note: this TR factor is used only when the ETPR
fine tuning factor is equal to 00h; otherwise, TR is
replaced by the ETPR dividing factor.
Bit 2:0 = SCR[2:0] SCI Receiver rate divisor.
BAUD RATE REGISTER (BRR)
Read/Write
These 3 bits, in conjunction with the SCP1 & SCP0
bits define the total division applied to the bus
clock to yield the receive rate clock in conventional
Baud Rate Generator mode.
Reset Value: 00xx xxxx (XXh)
7
0
RR dividing factor
SCR2
SCR1
SCR0
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0
1
2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Bit 7:6= SCP[1:0] First SCI Prescaler
These 2 prescaling bits allow several standard
clock division ranges:
4
8
16
32
64
128
PR Prescaling factor
SCP1
SCP0
1
3
0
0
1
1
0
1
0
1
4
13
Note: this RR factor is used only when the ERPR
fine tuning factor is equal to 00h; otherwise, RR is
replaced by the ERPR dividing factor.
102/164
ST72311R, ST72511R, ST72512R, ST72532R
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
EXTENDED RECEIVE PRESCALER DIVISION
REGISTER (ERPR)
EXTENDED TRANSMIT PRESCALER DIVISION
REGISTER (ETPR)
Read/Write
Read/Write
Reset Value: 0000 0000 (00h)
Reset Value:0000 0000 (00h)
Allows setting of the Extended Prescaler rate divi-
sion factor for the receive circuit.
Allows setting of the External Prescaler rate divi-
sion factor for the transmit circuit.
7
0
7
0
ERPR ERPR ERPR ERPR ERPR ERPR ERPR ERPR
ETPR ETPR ETPR ETPR ETPR ETPR ETPR ETPR
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Bit 7:1 = ERPR[7:0] 8-bit Extended Receive Pres-
caler Register.
Bit 7:1 = ETPR[7:0] 8-bit Extended Transmit Pres-
caler Register.
The extended Baud Rate Generator is activated
when a value different from 00h is stored in this
register. Therefore the clock frequency issued
from the 16 divider (see Figure 54) is divided by
the binary factor set in the ERPR register (in the
range 1 to 255).
The extended Baud Rate Generator is activated
when a value different from 00h is stored in this
register. Therefore the clock frequency issued
from the 16 divider (see Figure 54) is divided by
the binary factor set in the ETPR register (in the
range 1 to 255).
The extended baud rate generator is not used af-
ter a reset.
The extended baud rate generator is not used af-
ter a reset.
Table 22. SCI Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
SCISR
Reset Value
TDRE
1
TC
1
RDRF
0
IDLE
0
OR
0
NF
0
FE
0
0050h
0051h
0052h
0053h
0054h
0055h
0057h
0
SCIDR
Reset Value
MSB
x
LSB
x
x
x
x
x
x
x
SCIBRR
Reset Value
SCP1
0
SCP0
0
SCT2
0
SCT1
0
SCT0
0
SCR2
0
SCR1
0
SCR0
0
SCICR1
Reset Value
R8
x
T8
x
M
x
WAKE
x
0
0
0
0
SCICR2
Reset Value
TIE
0
TCIE
0
RIE
0
ILIE
0
TE
0
RE
0
RWU
0
SBK
0
SCIERPR
Reset Value
MSB
0
LSB
0
0
0
0
0
0
0
0
0
0
0
0
0
SCIETPR
Reset Value
MSB
0
LSB
0
103/164
ST72311R, ST72511R, ST72512R, ST72532R
10.7 CONTROLLER AREA NETWORK (CAN)
10.7.1 Introduction
are checked for correctness and acknowledged
accordingly although such frames cannot be trans-
mitted nor received. The same applies to overload
frames which are recognized but never initiated.
This peripheral is designed to support serial data
exchanges using a multi-master contention based
priority scheme as described in CAN specification
Rev. 2.0 part A. It can also be connected to a 2.0 B
network without problems, since extended frames
Figure 55. CAN Block Diagram
ST7 Internal Bus
ST7 Interface
PSR
BRPR
BTR
TX/RX
Buffer 1
TX/RX
Buffer 2
TX/RX
Buffer 3
ID
Filter 0
ID
Filter 1
10 Bytes
10 Bytes
10 Bytes
4 Bytes
4 Bytes
ICR
RX
TX
SHREG
BCDL
BTL
ISR
EML
CRC
CSR
TECR
RECR
CAN 2.0B passive Core
104/164
ST72311R, ST72511R, ST72512R, ST72532R
CONTROLLER AREA NETWORK (Cont’d)
10.7.2 Main Features
The acknowledgement (ACK) field comprises the
ACK slot and the ACK delimiter. The bit in the ACK
slot is placed on the bus by the transmitter as a re-
cessive bit (logical 1). It is overwritten as a domi-
nant bit (logical 0) by those receivers which have
at this timereceived the data correctly. In this way,
the transmitting node can be assured that at least
one receiver has correctly received its message.
Note that messages are acknowledged by the re-
ceivers regardless of the outcome of the accept-
ance test.
– Support of CAN specification 2.0A and 2.0B pas-
sive
– Three prioritized 10-byte Transmit/Receive mes-
sage buffers
– Two programmable global 12-bit message ac-
ceptance filters
– Programmable baud rates up to 1 MBit/s
– Buffer flip-flopping capability in transmission
– Maskable interrupts for transmit, receive (one
per buffer), error and wake-up
The end of the message is indicated by the End Of
Frame (EOF). The intermission field defines the
minimum number of bit periods separating con-
secutive messages. If there is no subsequent bus
access by any station, the bus remains idle.
– Automatic low-power mode after 20 recessive
bits or on demand (standby mode)
– Interrupt-driven wake-up from standby mode
upon reception of dominant pulse
10.7.3.2 Hardware Blocks
The CAN controller contains the following func-
tional blocks (refer to Figure 55):
– Optionaldominant pulse transmissionon leaving
standby mode
– ST7 Interface: buffering of the ST7 internal bus
and address decoding of the CAN registers.
– Automatic message queuing for transmission
upon writing of data byte 7
– TX/RX Buffers: three 10-byte buffers for trans-
mission and reception of maximum length mes-
sages.
– Programmable loop-back mode for self-test op-
eration
– Advanced error detection and diagnosis func-
tions
– ID Filters: two 12-bit compare and don’t care
masks for message acceptance filtering.
– Software-efficient buffer mapping at a unique ad-
dress space
– PSR:page selectionregister (see memory map).
– BRPR: clock divider for different data rates.
– BTR: bit timing register.
– Scalable architecture.
10.7.3 Functional Description
10.7.3.1 Frame Formats
– ICR: interrupt control register.
– ISR: interrupt status register.
A summary of all the CAN frame formats is given
in Figure 56 for reference. It covers only the stand-
ard frame format since the extended one is only
acknowledged.
– CSR: general purpose control/status register.
– TECR: transmit error counter register.
– RECR: receive error counter register.
A message begins with a start bit called Start Of
Frame (SOF). This bit is followed by the arbitration
field which contains the 11-bit identifier (ID) and
the Remote Transmission Request bit (RTR). The
RTR bit indicates whether it is adata frame or a re-
mote request frame. A remote request frame does
not have any data byte.
– BTL: bit timing logic providing programmable bit
sampling and bit clock generation for synchroni-
zation of the controller.
– BCDL: bit coding logic generating a NRZ-coded
datastream with stuff bits.
– SHREG: 8-bit shift register for serialization of
data to be transmitted and parallelisation of re-
ceived data.
The control field contains the Identifier Extension
bit (IDE), which indicates standard or extended
format, a reserved bit (ro) and, in the last four bits,
a count of the data bytes (DLC). The data field
ranges from zero to eight bytes and is followed by
the Cyclic Redundancy Check (CRC) used as a
frame integrity check for detecting bit errors.
– CRC: 15-bit CRC calculator and checker.
– EML: error detection and management logic.
– CAN Core: CAN 2.0B passive protocol control-
ler.
105/164
ST72311R, ST72511R, ST72512R, ST72532R
CONTROLLER AREA NETWORK (Cont’d)
Figure 56. CAN Frames
Inter-Frame Space
or Overload Frame
Inter-Frame Space
Data Frame
44 + 8 * N
Ack Field
Control Field Data Field
CRC Field
16
Arbitration Field
12
2
6
8 * N
7
ID
CRC
EOF
DLC
Inter-Frame Space
or Overload Frame
Inter-Frame Space
Remote Frame
44
Control Field
6
CRC Field
16
Ack Field End Of Frame
Arbitration Field
12
2
7
ID
CRC
DLC
Data Frame or
Remote Frame
Inter-Frame Space
or Overload Frame
Error Frame
Flag Echo Error Delimiter
Error Flag
≤ 6
8
6
Notes:
Data Frame or
Remote Frame
Any Frame
Inter-Frame Space
Suspend
Transmission
8
• 0
<=
N
<= 8
• SOF = Start Of Frame
• ID = Identifier
Intermission
Bus Idle
3
• RTR = Remote Transmission Request
• IDE = Identifier Extension Bit
• r0 = Reserved Bit
• DLC = Data Length Code
End Of Frame or
Error Delimiter or
Overload Delimiter
Inter-Frame Space
or Error Frame
• CRC = Cyclic Redundancy Code
• Error flag: 6dominant bitsif node is error
active else 6 recessive bits.
• Suspend transmission: applies to error
passive nodes only.
Overload Frame
Overload Flag Overload Delimiter
6
8
• EOF = End of Frame
• ACK = Acknowledge bit
106/164
ST72311R, ST72511R, ST72512R, ST72532R
CONTROLLER AREA NETWORK (Cont’d)
10.7.3.3 Modes of Operation
Register (ICR) is set.
The STANDBY mode is left by setting the RUN
bit. If the WKPS bit is set in the CSR register,
then the controller passes through WAKE-UP
otherwise it enters RESYNC directly.
It is important to note that the wake-up mecha-
nism is software-driven and therefore carries a
significant time overhead. All messages received
after the wake-up bit and before the controller is
set to run and has completed synchronization
are ignored.
The CAN Core unit assumes one of the seven
states described below:
– STANDBY. Standby mode is entered either on a
chip reset or on resetting the RUN bit in the Con-
trol/Status Register (CSR). Any on-going trans-
mission or reception operation is not interrupted
and completes normally before the Bit Time Log-
ic and the clock prescaler are turned off for mini-
mum power consumption. This state is signalled
by the RUN bit being read-back as 0.
– WAKE-UP. The CAN bus line is forced to domi-
nant for one bit time signalling the wake-up con-
dition to all other bus members.
Once in standby, the only event monitored is the
reception of a dominant bit which causes a wake-
up interrupt if the SCIE bit of theInterrupt Control
Figure 57. CAN Controller State Diagram
ARESET
RUN & WKPS
STANDBY
RUN
RUN & WKPS
WAKE-UP
RESYNC
FSYN & BOFF & 11 Recessive bits |
(FSYN | BOFF) & 128 * 11 Recessive bits
RUN
IDLE
Write to DATA7 |
TX Error & NRTX
Start Of Frame
RX OK
TX OK
Arbitration lost
TRANSMISSION
TX Error
RECEPTION
RX Error
BOFF
ERROR
BOFF
n
107/164
ST72311R, ST72511R, ST72512R, ST72532R
CONTROLLER AREA NETWORK (Cont’d)
– RESYNC. The resynchronization mode is used
to find the correct entry point for starting trans-
mission or reception after the node has gone
asynchronous eitherby going into the STANDBY
or bus-off states.
Resynchronization is achieved when 128 se-
quences of 11 recessive bits have been moni-
tored unless the node is not bus-off and the
FSYN bit inthe CSR register is set in which case
a single sequence of 11 recessive bits needs to
be monitored.
Note 1: Setting the SRTE bit of the CSR register
allows transmitted messages to be simultane-
ously received when they pass the acceptance
filtering. This is particularly useful for checking
the integrity of the communication path.
Note 2: When the ETX bit is reset, the buffer with
the highest priority and with a pending transmis-
sion request is always transmitted. When the
ETX bit is set, once a buffer participates in the ar-
bitration phase, it is sent until it wins the arbitra-
tion even if another transmission is requested
from a buffer with a higher priority.
– IDLE. The CAN controller looks for one of the fol-
lowing events: the RUN bit is reset, a Start Of
Frame appears on the CAN bus or the DATA7
register of the currently active page is written to.
– RECEPTION. Once the CAN controller has syn-
chronized itself onto the bus activity, it is ready
for reception of new messages. Every incoming
message gets its identifier compared to the ac-
ceptance filters. If the bitwise comparison of the
selected bits ends up with a match for at least
one of the filters then that message is elected for
reception and atarget buffer is searched for. This
buffer will be the first one - order is 1 to 3 - that
has the LOCK and RDY bits of its BCSRx regis-
ter reset.
– TRANSMISSION. Once the LOCK bit of a Buffer
Control/Status Register (BCSRx) has been set
and read back as such, a transmit job can be
submitted by writing to the DATA7 register. The
message with the highest priority will be transmit-
ted as soon as the CAN bus becomes idle.
Among those messages with a pending trans-
mission request, the highest priority is given to
Buffer 3then 2 and 1. If the transmission fails due
to a lost arbitration or to an error while the NRTX
bit of the CSR register is reset, then a new trans-
mission attempt is performed . This goes on until
the transmission ends successfully or until the
job is cancelled by unlocking the buffer, by set-
ting the NRTX bit or if the node ever enters bus-
off or if a higher priority message becomes pend-
ing. The RDY bit in the BCSRx register, which
was set since the job was submitted, gets reset.
When a transmission is in progress, the BUSY bit
in the BCSRx register is set. If it ends successful-
ly then the TXIF bit in the Interrupt Status Regis-
ter (ISR) is set, else the TEIF bit is set. An
interrupt is generated in either case provided the
TXIE and TEIE bits of the ICR register are set.
The ETX bit in the same register is used to get an
early transmit interrupt and to automatically un-
lock the transmitting buffer upon successful com-
pletion of its job. This enables the CPU to get a
new transmit job pending by the end of the cur-
rent transmission while always leaving two buff-
ers available for reception. An uninterrupted
stream of messages may be transmitted in this
way at no overrun risk.
– When no such buffer exists then an overrun
interrupt is generated if the ORIE bit of the ICR
register has been set. In this case the identifi-
er of the last message is made available in the
Last Identifier Register (LIDHR and LIDLR) at
least until it gets overwritten by a new identifi-
er picked-up from the bus.
– When a buffer does exist, the accepted mes-
sage gets written into it, the ACC bit in the
BCSRx register gets the number of the match-
ing filter, the RDY and RXIF bits get set and an
interrupt is generated if the RXIE bit in the ISR
register is set.
Up to three messages can be automatically
received without intervention from the CPU
because each buffer has its own set of status
bits, greatly reducing the reactiveness require-
ments in the processing of the receive inter-
rupts.
108/164
ST72311R, ST72511R, ST72512R, ST72532R
CONTROLLER AREA NETWORK (Cont’d)
– ERROR. The error management as described in
the CAN protocol is completely handled by hard-
ware using 2 error counters which get increment-
ed or decremented according to the error
cation to determine the stability of the network.
Moreover, as one of the node status bits (EPSV
or BOFF of the CSR register) changes, an inter-
rupt is generated if the SCIE bit is set in the ICR
Register. Refer to Figure 58.
condition. Both of them may be read by the appli-
Figure 58. CAN Error State Diagram
When TECR or RECR > 127, the EPSV bit gets set
ERROR ACTIVE
ERROR PASSIVE
When TECR and RECR < 128,
the EPSV bit gets cleared
When 128 * 11 recessive bits occur:
- the BOFF bit gets cleared
When TECR > 255 the BOFF bit gets set
and the EPSV bit gets cleared
- the TECR register gets cleared
- the RECR register gets cleared
BUS OFF
109/164
ST72311R, ST72511R, ST72512R, ST72532R
CONTROLLER AREA NETWORK (Cont’d)
10.7.3.4 Bit Timing Logic
The resynchronization jump width (RJW) defines
an upper bound to the amount of lengthening or
shortening of the bit segments. It is programmable
between 1 and 4 time quanta.
The bit timing logic monitors the serial bus-line and
performs sampling and adjustment of the sample
point by synchronizing on the start-bit edge and re-
synchronizing on following edges.
A valid edge is defined as the first transition in a bit
time from dominant to recessive bus level provid-
ed the controller itself does not send a recessive
bit.
Its operation may be explained simply when the
nominal bit time is divided into three segments as
follows:
If a valid edge is detected in BS1 instead of
SYNC_SEG, BS1 is extended by up to RJW so
that the sample point is delayed.
– Synchronisation segment (SYNC_SEG): a bit
change is expected to lie within this time seg-
ment. It has a fixed length of one time quanta (1
x t
).
Conversely, if a valid edge is detected in BS2 in-
stead of SYNC_SEG, BS2 is shortened by up to
RJW so that the transmit point is moved earlier.
CAN
– Bit segment 1 (BS1): defines the location of the
sample point. It includes the PROP_SEG and
PHASE_SEG1 of the CAN standard. Its duration
is programmable between 1 and 16 time quanta
but may be automatically lengthened to compen-
sate for positive phase drifts due to differences in
the frequency of the various nodes of the net-
work.
As a safeguard against programming errors, the
configuration of the Bit Timing Register (BTR) is
only possible while the device is in STANDBY
mode.
– Bit segment 2 (BS2): defines the location of the
transmit point. It represents the PHASE_SEG2
of the CAN standard. Its duration is programma-
ble between 1 and 8 timequanta but may also be
automatically shortened to compensate for neg-
ative phase drifts.
Figure 59. Bit Timing
NOMINAL BIT TIME
SYNC_SEG
BIT SEGMENT 1 (BS1)
BIT SEGMENT 2 (BS2)
1 x t
CAN
t
t
BS1
BS2
SAMPLE POINT
TRANSMIT POINT
110/164
ST72311R, ST72511R, ST72512R, ST72532R
CONTROLLER AREA NETWORK (Cont’d)
Bit 4 = TXIF Transmit Interrupt Flag
10.7.4 Register Description
−
Read/Clear
The CAN registers are organized as 6 general pur-
pose registers plus 5 pages of 16 registers span-
ning the same address space and primarily used
for message and filter storage. The page actually
selected is defined by the content of the Page Se-
lection Register. Refer to Figure 60.
Set by hardware to signal that the highest priority
message queued for transmission has been suc-
cessfully transmitted(ETX = 0) orthat it has passed
successfully the arbitration (ETX = 1).
Cleared by software.
Bit 3 = SCIF Status Change Interrupt Flag
10.7.4.1 General Purpose Registers
INTERRUPT STATUS REGISTER (ISR)
Read/Write
−
Read/Clear
Set by hardware to signal the reception of a domi-
nant bit while in standby or a change from error ac-
tive to error passive and bus-off while in run. Also
signals any receive error when ESCI = 1.
Cleared by software.
Reset Value: 00h
7
0
Bit 2 = ORIF Overrun Interrupt Flag
−
Read/Clear
RXIF3 RXIF2 RXIF1 TXIF SCIF ORIF TEIF EPND
Set by hardware to signal that a message could not
be stored because no receive buffer was available.
Cleared by software.
Bit 7 = RXIF3 Receive Interrupt Flag for Buffer 3
−
Read/Clear
Bit 1 = TEIF Transmit Error Interrupt Flag
Set byhardware tosignal that anew error-free mes-
sage is available in buffer 3.
−
Read/Clear
Set byhardware tosignal thatanerroroccurred dur-
ing thetransmission ofthe highest prioritymessage
queued for transmission.
Cleared by software to release buffer 3.
Also cleared by resetting bit RDY of BCSR3.
Cleared by software.
Bit 6 = RXIF2 Receive Interrupt Flag for Buffer 2
−
Read/Clear
Bit 0 = EPND Error Interrupt Pending
Set by hardware to signal that a new error-free
message is available in buffer 2.
−
Read Only
Set byhardware when at leastone of thethree error
interrupt flags SCIF, ORIF or TEIF is set.
Reset by hardware when all error interrupt flags
have been cleared.
Cleared by software to release buffer 2.
Also cleared by resetting bit RDY of BCSR2.
Bit 5 = RXIF1 Receive Interrupt Flag for Buffer 1
−
Read/Clear
Caution;
Set byhardware tosignal that anew error-free mes-
sage is available in buffer 1.
Interrupt flags are reset by writing a ”0” to the cor-
responding bit position. The appropriate way con-
sists inwritingan immediatemask orthe one’s com-
plement of the register content initially read by the
interrupt handler. Bit manipulation instruction
BRES should neverbe used due to its read-modify-
write nature.
Cleared by software to release buffer 1.
Also cleared by resetting bit RDY of BCSR1.
111/164
ST72311R, ST72511R, ST72512R, ST72532R
CONTROLLER AREA NETWORK (Cont’d)
Bit 3 = SCIE Status Change Interrupt Enable
Read/Set/Clear
Set by software to enable an interrupt request
whenever thenode’s statuschanges in run modeor
whenever a dominant pulse is received in standby
mode.
INTERRUPT CONTROL REGISTER (ICR)
Read/Write
−
Reset Value: 00h
7
0
0
Cleared by software to disable status change inter-
rupt requests.
ESCI RXIE TXIE SCIE ORIE TEIE
ETX
Bit 2 = ORIE Overrun Interrupt Enable
−
Read/Set/Clear
Bit 6 = ESCI Extended Status Change Interrupt
Read/Set/Clear
Set by software to specify that SCIF is to be set on
receive errors also.
Cleared by software to set SCIF only on status
changes and wake-up but not onall receive errors.
Set by software to enable an interrupt request
whenever a message should be stored and no re-
ceive buffer is avalaible.
−
Cleared by software to disable overrun interrupt re-
quests.
Bit 1 = TEIE Transmit Error Interrupt Enable
Bit 5 = RXIE Receive Interrupt Enable
−
Read/Set/Clear
−
Read/Set/Clear
Set by software to enablean interrupt whenever an
error has been detected during transmission of a
message.
Set by software to enable an interrupt request
whenever amessage has been received free of er-
rors.
Cleared by software to disable receive interrupt re-
quests.
Cleared by software to disable transmit error inter-
rupts.
Read/Set/Clear
112/164
ST72311R, ST72511R, ST72512R, ST72532R
CONTROLLER AREA NETWORK (Cont’d)
Bit 3 = NRTX No Retransmission
CONTROL/STATUS REGISTER (CSR)
Read/Write
−
Read/Set/Clear
Set by software to disable theretransmission of un-
successful messages.
Reset Value: 00h
Cleared by software to enable retransmission of
messages until success is met.
7
0
Bit 2 = FSYN Fast Synchronization
0
BOFF EPSV SRTE NRTX FSYN WKPS RUN
−
Read/Set/Clear
Set by software to enable a fast resynchronization
when leaving standby mode, i.e. wait foronly 11 re-
cessive bits in a row.
Bit 6 = BOFF Bus-Off State
Read Only
Set by hardware to indicate that the node is in bus-
off state, i.e. the Transmit Error Counter exceeds
255.
−
Cleared by software to enable the standard resyn-
chronization when leaving standby mode, i.e. wait
for 128 sequences of 11 recessive bits.
Reset by hardware to indicate that the node is in-
volved in bus activities.
Read/Set/Clear
Bit 5 = EPSV Error Passive State
−
Read Only
Set by hardware to indicate that the node is error
passive.
Reset by hardware toindicatethat thenode iseither
error active (BOFF = 0) or bus-off.
Bit 4 = SRTE Simultaneous Receive/Transmit En-
able
−
Read/Set/Clear
Set by software to enable simultaneous transmis-
sion and reception of a message passing the ac-
ceptance filtering. Allows to check the integrity of
the communication path.
Reset by software to discard all messages trans-
mitted by the node. Allows remote and data frames
to share the same identifier.
113/164
ST72311R, ST72511R, ST72512R, ST72532R
CONTROLLER AREA NETWORK (Cont’d)
BAUD RATE PRESCALER REGISTER (BRPR)
Read/Write in Standby mode
Reset Value: 00h
BIT TIMING REGISTER (BTR)
Read/Write in Standby mode
Reset Value: 23h
7
0
7
0
RJW1 RJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0
0
BS22 BS21 BS20 BS13 BS12 BS11 BS10
RJW[1:0] determine the maximum number of time
quanta by which a bit period may be shortened or
lengthened to achieve resynchronization.
BS2[2:0] determine the length of Bit Segment 2.
= t * (BS2 + 1)
t
BS2
CAN
BS1[3:0] determine the length of Bit Segment 1.
= t * (BS1 + 1)
t
= t
* (RJW + 1)
RJW
CAN
t
BS1
CAN
BRP[5:0] determine the CAN system clock cycle
time or time quanta which is used to build up the in-
dividual bit timing.
Note: Writing to this register is allowed only in
Standby mode to prevent any accidental CAN pro-
tocol violation through programming errors.
t
= t
* (BRP + 1)
CAN
CPU
Where t
= time period of the CPU clock.
CPU
The resultingbaudrate canbe computed bythe for-
mula:
PAGE SELECTION REGISTER (PSR)
Read/Write
Reset Value: 00h
7
0
1
BR = --------------------------------------------------------------------------------------------- -
PAGE PAGE PAGE
0
0
0
0
0
tCPU × (BRP + 1) × (BS1 + BS2 + 3)
2
1
0
PAGE[2:0] determine which buffer or filter page is
mapped at addresses 0010h to 001Fh.
Note: Writing to this register is allowed only in
Standby mode to prevent any accidental CAN pro-
tocol violation through programming errors.
PAGE2
PAGE1
PAGE0
Page Title
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Diagnosis
Buffer 1
Buffer 2
Buffer 3
Filters
Reserved
Reserved
Reserved
114/164
ST72311R, ST72511R, ST72512R, ST72532R
CONTROLLER AREA NETWORK (Cont’d)
10.7.4.2 Paged Registers
TRANSMIT ERROR COUNTER REG. (TECR)
Read Only
LAST IDENTIFIER HIGH REGISTER (LIDHR)
Read/Write
Reset Value: 00h
Reset Value: Undefined
7
0
7
0
TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0
LID10 LID9
LID8
LID7
LID6
LID5
LID4
LID3
TEC[7:0] is the least significant byte of the 9-bit
Transmit Error Counter implementing part of the
fault confinement mechanism of the CAN protocol.
In case of an error during transmission, this counter
is incremented by 8. It is decremented by 1 after
every successful transmission. When the counter
value exceeds 127, the CAN controller enters the
error passivestate. When avalueof256 isreached,
the CAN controller is disconnected from the bus.
LID[10:3] are the most significant 8 bits of the last
Identifier read on the CAN bus.
LAST IDENTIFIER LOW REGISTER (LIDLR)
Read/Write
Reset Value: Undefined
7
0
RECEIVE ERROR COUNTER REG. (RECR)
Page: 00h — Read Only
LDLC LDLC LDLC LDLC
LID2
LID1
LID0 LRTR
Reset Value: 00h
3
2
1
0
7
0
LID[2:0] are the least significant 3 bits of the last
Identifier read on the CAN bus.
REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0
LRTR is the last Remote Transmission Request bit
read on the CAN bus.
REC[7:0] is the Receive Error Counter implement-
ing part of the fault confinement mechanism of the
CAN protocol. In case of an error during reception,
this counter is incremented by 1 or by 8 depending
on theerror condition as defined by the CAN stand-
ard. After every successful reception the counter is
decremented by 1 or reset to 120 if its value was
higher than 128. When the counter value exceeds
127, the CAN controller enters the error passive
state.
LDLC[3:0] is the last DataLength Codereadon the
CAN bus.
IDENTIFIER HIGH REGISTERS (IDHRx)
Read/Write
Reset Value: Undefined
7
0
ID10
ID9
ID8
ID7
ID6
ID5
ID4
ID3
ID[10:3] are the most significant 8 bits of the 11-bit
message identifier.The identifier acts as the mes-
sage’s name, used for bus access arbitration and
acceptance filtering.
115/164
ST72311R, ST72511R, ST72512R, ST72532R
CONTROLLER AREA NETWORK (Cont’d)
IDENTIFIER LOW REGISTERS (IDLRx)
Read/Write
BUFFER CONTROL/STATUS REGs. (BCSRx)
Read/Write
Reset Value: Undefined
Reset Value: 00h
7
0
7
0
0
ID2
ID1
ID0
RTR DLC3 DLC2 DLC1 DLC0
0
0
0
ACC
RDY BUSY LOCK
Bit 3 = ACC Acceptance Code
Read Only
Set by hardware with the id of the highest priority
filter which accepted the message stored in the
buffer.
ACC = 0: Match for Filter/Mask0. Possible match
for Filter/Mask1.
ACC = 1: No match for Filter/Mask0 and match for
Filter/Mask1.
ID[2:0] are the least significant 3 bits of the 11-bit
message identifier.
−
RTR is the Remote Transmission Request bit. It is
set to indicate a remote frame and reset to indicate
a data frame.
DLC[3:0] is the Data Length Code. It gives the
number of bytes in the data field of the mes-
sage.The valid range is 0 to 8.
Reset by hardware when either RDY or RXIF gets
reset.
Bit 2 = RDY Message Ready
DATA REGISTERS (DATA0-7x)
Read/Write
−
Read/Clear
Set by hardware to signal that a new error-free
message is available (LOCK = 0) or that a trans-
mission request is pending (LOCK = 1).
Cleared by software when LOCK = 0 to release
the buffer and to clear the corresponding RXIF bit
in the Interrupt Status Register.
Reset Value: Undefined
7
0
DATA DATA DATA DATA DATA DATA DATA DATA
7
6
5
4
3
2
1
0
Cleared by hardware when LOCK = 1 to indicate
that the transmission request has been serviced or
cancelled.
DATA[7:0] is amessage databyte. Upto eight such
bytes may be part of a message. Writing to byte
DATA7 initiates a transmit request and should al-
ways be done even when DATA7 is not part of the
message.
Bit 1 = BUSY Busy Buffer
−
Read Only
Set by hardware when the buffer is being filled
(LOCK = 0) or emptied (LOCK = 1).
Reset by hardware when the buffer is not ac-
cessed by the CAN core for transmission nor re-
ception purposes.
Bit 0 = LOCK Lock Buffer
−
Read/Set/Clear
Set by software to lock a buffer. No more message
can be received into the buffer thus preserving its
content and making it available for transmission.
Cleared by software to make the buffer available
for reception. Cancels any pending transmission
request.
Cleared by hardware once a message has been
successfully transmitted provided the early trans-
mit interrupt modeis on. Left untouched otherwise.
Note that in order to prevent any message corrup-
tion or loss of context, LOCK cannot be set nor re-
set while BUSY is set. Trying to do so will result in
LOCK not changing state.
116/164
ST72311R, ST72511R, ST72512R, ST72532R
CONTROLLER AREA NETWORK (Cont’d)
FILTER HIGH REGISTERS (FHRx)
Read/Write
MASK HIGH REGISTERS (MHRx)
Read/Write
Reset Value: Undefined
Reset Value: Undefined
7
0
7
0
FIL11 FIL10 FIL9
FIL8
FIL7
FIL6
FIL5
FlL4
MSK1 MSK1
MSK9 MSK8 MSK7 MSK6 MSK5 MSK4
1
0
FIL[11:3] are the most significant 8 bits of a 12-bit
message filter. The acceptance filter is compared
bit by bit with the identifier and the RTR bit of the
incoming message. If there is a match for the set
of bits specified by the acceptance mask then the
message is stored in a receive buffer.
MSK[11:3] are the most significant 8 bits of a 12-
bit message mask. The acceptance mask defines
which bits of the acceptance filter should match
the identifier and the RTR bit of the incoming mes-
sage.
MSK = 0: don’t care.
i
MSK = 1: match required.
i
FILTER LOW REGISTERS (FLRx)
Read/Write
MASK LOW REGISTERS (MLRx)
Read/Write
Reset Value: Undefined
Reset Value: Undefined
7
0
0
7
0
0
FIL3
FIL2
FIL1
FIL0
0
0
0
MSK3 MSK2 MSK1 MSK0
0
0
0
FIL[3:0] are the least significant 4 bits of a 12-bit
message filter.
MSK[3:0] are the least significant 4 bits of a 12-bit
message mask.
117/164
ST72311R, ST72511R, ST72512R, ST72532R
CONTROLLER AREA NETWORK (Cont’d)
Figure 60. CAN Register Map
Interrupt Status
5Ah
5Bh
5Ch
5Dh
5Eh
5Fh
60h
Interrupt Control
Control/Status
Baud Rate Prescaler
Bit Timing
Page Selection
Paged Reg1
Paged Reg1
Paged Reg0
Paged Reg1
Paged Reg2
Paged Reg1
Paged R g2
Paged Reg1
Paged Reg2
Paged Reg3
Paged Reg2
Paged Reg3
Paged Reg2
Paged Reg3
Paged Reg4
Paged Reg3
Paged Reg4
Paged Reg3
Paged Reg4
Paged Reg5
Paged Reg4
Paged Reg5
Paged Reg4
Paged Reg5
Paged Reg6
Paged Reg5
Paged Reg6
Paged Reg5
Paged Reg6
Paged Reg7
Paged Reg6
Paged Reg7
Paged Reg6
Paged Reg7
Paged Reg8
Paged Reg7
Paged R g8
Paged Reg7
Paged Reg8
Paged Reg9
Paged Reg8
Paged R g9
Paged Reg8
Paged Reg9
Paged Reg10
Paged Reg9
Paged Reg10
Paged Reg9
Paged Reg10
Paged Reg11
Paged Reg10
Paged Reg11
Paged Reg10
Paged Reg11
Paged Reg12
Paged Reg11
Paged Reg12
Paged Reg11
Paged Reg12
Paged Reg13
Paged Reg12
Paged Reg13
Paged Reg12
Paged Reg13
Paged Reg14
Paged Reg13
Paged R g14
Paged Reg13
Paged Reg14
Paged R g15
Paged Reg14
Paged Reg15
Paged Reg14
Paged Reg15
6Fh
Paged Reg15
Paged Reg15
118/164
ST72311R, ST72511R, ST72512R, ST72532R
CONTROLLER AREA NETWORK (Cont’d)
Figure 61. Page Maps
PAGE 0
PAGE 1
PAGE 2
PAGE 3
PAGE 4
60h
61h
62h
63h
64h
65h
66h
67h
68h
69h
6Ah
6Bh
6Ch
6Dh
6Eh
6Fh
LIDHR
LIDLR
IDHR1
IDHR2
IDLR2
IDHR3
IDLR3
FHR0
FLR0
MHR0
MLR0
FHR1
FLR1
MHR1
MLR1
IDLR1
DATA01
DATA11
DATA21
DATA31
DATA41
DATA51
DATA61
DATA71
DATA02
DATA12
DATA22
DATA32
DATA42
DATA52
DATA62
DATA72
DATA03
DATA13
DATA23
DATA33
DATA43
DATA53
DATA63
DATA73
Reserved
Reserved
Reserved
Reserved
Reserved
TSTR
TECR
RECR
BCSR1
Buffer 1
BCSR2
Buffer 2
BCSR3
Buffer 3
Diagnosis
Acceptance Filters
119/164
ST72311R, ST72511R, ST72512R, ST72532R
CONTROLLER AREA NETWORK (Cont’d)
Table 23. CAN Register Map and Reset Values
Address
(Hex.)
Register
Label
Page
7
6
5
4
3
2
1
0
CANISR
Reset Value
RXIF3
0
RXIF2
0
RXIF1
0
TXIF
0
SCIF
0
ORIF
0
TEIF
0
EPND
0
5A
5B
5C
5D
5E
5F
CANICR
Reset Value
ESCI
0
RXIE
0
TXIE
0
SCIE
0
ORIE
0
TEIE
0
ETX
0
0
0
CANCSR
Reset Value
BOFF
0
EPSV
0
SRTE
0
NRTX
0
FSYN
0
WKPS
0
RUN
0
CANBRPR
Reset Value
RJW1
0
RJW0
0
BRP5
0
BRP4
0
BRP3
0
BRP2
0
BRP1
0
BRP0
0
CANBTR
Reset Value
BS22
0
BS21
1
BS20
0
BS13
0
BS12
0
BS11
1
BS10
1
0
CANPSR
Reset Value
PAGE2 PAGE1 PAGE0
0
0
0
0
0
0
0
0
CANLIDHR
Reset Value
LID10
x
LID9
x
LID8
x
LID7
x
LID6
x
LID5
x
LID4
x
LID3
x
0
1 to 3
4
60
CANIDHRx
Reset Value
ID10
x
ID9
x
ID8
x
ID7
x
ID6
x
ID5
x
ID4
x
ID3
x
CANFHRx
Reset Value
FIL11
x
FIL10
x
FIL9
x
FIL8
x
FIL7
x
FIL6
x
FIL5
x
FIL4
x
60, 64
61
CANLIDLR
Reset Value
LID2
x
LID1
x
LID0
x
LRTR LDLC3 LDLC2 LDLC1 LDLC0
0
x
x
x
x
x
CANIDLRx
Reset Value
ID2
x
ID1
x
ID0
x
RTR
x
DLC3
x
DLC2
x
DLC1
x
DLC0
x
1 to 3
4
CANFLRx
Reset Value
FIL3
x
FIL2
x
FIL1
x
FIL0
x
61, 65
0
0
0
0
CANDRx
Reset Value
MSB
x
LSB
x
62 to 69 1 to 3
x
x
x
x
x
x
CANMHRx
Reset Value
MSK11 MSK10
MSK9
x
MSK8 MSK7
MSK6
x
MSK5
x
MSK4
x
62, 66
63, 67
6E
4
4
0
x
x
x
x
CANMLRx
Reset Value
MSK3
x
MSK2
x
MSK1
x
MSK0
x
0
0
0
0
0
0
0
0
CANTECR
Reset Value
MSB
0
LSB
0
0
0
0
0
0
0
0
0
0
0
CANRECR
Reset Value
MSB
0
LSB
0
0
6F
CANBCSRx
Reset Value
ACC
0
RDY
0
BUSY
0
LOCK
0
1 to 3
0
120/164
ST72311R, ST72511R, ST72512R, ST72532R
10.8 8-BIT A/D CONVERTER (ADC)
10.8.1 Introduction
10.8.3 Functional Description
10.8.3.1 Analog Power Supply
The on-chip Analog to Digital Converter (ADC) pe-
ripheral is a 8-bit, successive approximation con-
verter with internal sample and hold circuitry. This
peripheral has up to 16 multiplexed analog input
channels (refer to device pin out description) that
allow the peripheral to convert the analog voltage
levels from up to 16 different sources.
V
and V
are the high and low level refer-
SSA
DDA
ence voltage pins. In some devices (refer to device
pin out description) they are internally connected
to the V and V pins.
DD
SS
Conversion accuracy may therefore be impacted
by voltage drops and noise in the event of heavily
loaded or badly decoupled power supply lines.
The result of the conversion is stored in a 8-bit
Data Register. The A/D converter is controlled
through a Control/Status Register.
See electrical characteristics section for more de-
tails.
10.8.2 Main Features
■ 8-bit conversion
■ Up to 16 channels with multiplexed input
■ Linear successive approximation
■ Data register (DR) which contains the results
■ Conversion complete status flag
■ On/off bit (to reduce consumption)
The block diagram is shown in Figure 62.
Figure 62. ADC Block Diagram
f
f
ADC
CPU
DIV 2
COCO
0
ADON
4
0
CH3 CH2 CH1 CH0
ADCCSR
AIN0
AIN1
HOLD CONTROL
R
ADC
ANALOG TO DIGITAL
CONVERTER
ANALOG
MUX
AINx
C
ADC
ADCDR
D7
D6
D5
D4 D3
D2
D1
D0
121/164
ST72311R, ST72511R, ST72512R, ST72532R
8-BIT A/D CONVERTER (ADC) (Cont’d)
10.8.3.2 Digital A/D Conversion Result
The analog input ports must be configured as in-
put, no pull-up, no interrupt. Refer to the «I/O
ports» chapter. Using these pins as analog inputs
does not affect the ability of the port to be read as
a logic input.
The conversion is monotonic, meaning that the re-
sult never decreases if the analog input does not
and never increases if the analog input does not.
If the input voltage (V ) is greater than or equal
AIN
In the CSR register:
to V
(high-level voltage reference) then the
DDA
conversion result in the DR register is FFh (full
scale) without overflow indication.
– Select the CH[3:0] bits to assign the analog
channel to be converted.
ADC Conversion
If input voltage (V ) is lower than or equal to
AIN
V
(low-level voltage reference) then the con-
SSA
In the CSR register:
version result in the DR register is 00h.
– Set the ADON bit to enable the A/D converter
and to start the first conversion. From this time
on, the ADC performs a continuous conver-
sion of the selected channel.
The A/D converter is linear and the digital result of
the conversion is stored in the ADCDR register.
The accuracy of the conversion is described in the
parametric section.
When a conversion is complete
– The COCO bit is set by hardware.
– No interrupt is generated.
– The result is in the DR register and remains
valid until the next conversion has ended.
A write to the CSR register (with ADON set) aborts
the current conversion, resets the COCO bit and
starts a new conversion.
R
is the maximum recommended impedance
AIN
for an analog input signal. If the impedance is too
high, this will result in a loss of accuracy due to
leakage and sampling not being completed in the
alloted time.
10.8.3.3 A/D Conversion Phases
The A/D conversion is based on two conversion
phases as shown in Figure 63:
Figure 63. ADC Conversion Timings
■ Sample capacitor loading [duration: t
]
LOAD
During this phase, the V
input voltage to be
AIN
ADON
measured is loaded into the C
capacitor.
sample
ADC
ADCCSR WRITE
OPERATION
t
CONV
■ A/D conversion [duration: t
]
CONV
During this phase, the A/D conversion is
computed (8 successive approximations cycles)
HOLD
CONTROL
and the C
sample capacitor is disconnected
ADC
from the analog input pin to get the optimum
analog to digital conversion accuracy.
t
LOAD
COCO BIT SET
While the ADC is on, these two phases are contin-
uously repeated.
10.8.4 Low Power Modes
At the end of each conversion, the sample capaci-
tor is kept loaded with the previous measurement
load. The advantage of this behaviour is that it
minimizes the current consumption on the analog
pin in case of single input channel measurement.
Mode
WAIT
Description
No effect on A/D Converter
A/D Converter disabled.
After wakeup from Halt mode, the A/D Con-
verter requires a stabilisation time before ac-
curate conversions can be performed.
HALT
10.8.3.4 Software Procedure
Refer to the control/status register (CSR) and data
register (DR) in Section 10.8.6 for the bit defini-
tions and to Figure 63 for the timings.
Note: The A/D converter may be disabled by reset-
ting the ADON bit. This feature allows reduced
power consumption when no conversion is needed
and between single shot conversions.
ADC Configuration
The total duration of the A/D conversion is 12 ADC
10.8.5 Interrupts
clock periods (1/f
=2/f
).
ADC
CPU
None
122/164
ST72311R, ST72511R, ST72512R, ST72532R
8-BIT A/D CONVERTER (ADC) (Cont’d)
10.8.6 Register Description
CONTROL/STATUS REGISTER (CSR)
Read/Write
DATA REGISTER (DR)
Read Only
Reset Value: 0000 0000 (00h)
Reset Value: 0000 0000 (00h)
7
0
7
0
COCO
0
ADON
0
CH3
CH2
CH1
CH0
D7
D6
D5
D4
D3
D2
D1
D0
Bit 7 = COCO Conversion Complete
This bit is set by hardware. It is cleared by soft-
ware readingthe result in the DR register or writing
to the CSR register.
0: Conversion is not complete
1: Conversion can be read from the DR register
Bit 7:0 = D[7:0] Analog Converted Value
This register contains the converted analog value
in the range 00h to FFh.
Note: Reading this register reset the COCO flag.
Bit 6 = Reserved. must always be cleared.
Bit 5 = ADON A/D Converter On
This bit is set and cleared by software.
0: A/D converter is switched off
1: A/D converter is switched on
Bit 4 = Reserved. must always be cleared.
Bit 3:0 = CH[3:0] Channel Selection
These bits are set and cleared by software. They
select the analog input to convert.
Channel Pin*
CH3 CH2 CH1 CH0
AIN0
AIN1
AIN2
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
AIN10
AIN11
AIN12
AIN13
AIN14
AIN15
*Note: The number of pins AND the channel selec-
tion varies accordingto the device. Refer to the de-
vice pinout.
123/164
ST72311R, ST72511R, ST72512R, ST72532R
8-BIT A/D CONVERTOR (ADC) (Cont’d)
Table 24. ADC Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
ADCDR
Reset Value
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
0070h
0071h
ADCCSR
Standard
Reset Value
COCO
0
ADON
0
CH2
0
CH1
0
CH0
0
0
0
0
124/164
ST72311R, ST72511R, ST72512R, ST72532R
11 INSTRUCTION SET
11.1 ST7 ADDRESSING MODES
so, most of the addressing modes may be subdi-
vided in two sub-modes called long and short:
The ST7 Core features 17 different addressing
modes which can be classified in 7 main groups:
– Long addressing mode is more powerful be-
cause itcan use the full 64 Kbyte address space,
however it uses more bytes and more CPU cy-
cles.
Addressing Mode
Inherent
Example
nop
– Short addressing mode is less powerful because
it can generally only access page zero (0000h -
00FFh range), but the instruction size is more
compact, and faster. All memory to memory in-
structions use short addressing modes only
(CLR, CPL, NEG, BSET, BRES, BTJT, BTJF,
INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP)
Immediate
Direct
ld A,#$55
ld A,$55
ld A,($55,X)
ld A,([$55],X)
jrne loop
Indexed
Indirect
Relative
Bit operation
bset byte,#5
The ST7 Assembler optimizes the use of long and
short addressing modes.
The ST7 Instruction set is designed to minimize
the number of bytes required per instruction: To do
Table 25. ST7 Addressing Mode Overview
Pointer
Address
(Hex.)
Pointer Size
(Hex.)
Length
(Bytes)
Mode
Syntax
Destination
Inherent
Immediate
Short
Long
nop
+ 0
ld A,#$55
+ 1
+ 1
+ 2
+ 0
+ 1
+ 2
+ 2
+ 2
+ 2
+ 2
+ 1
+ 2
+ 1
+ 2
+ 2
+ 3
Direct
ld A,$10
00..FF
Direct
ld A,$1000
ld A,(X)
0000..FFFF
00..FF
No Offset
Short
Long
Direct
Indexed
Indexed
Indexed
Direct
ld A,($10,X)
ld A,($1000,X)
ld A,[$10]
00..1FE
0000..FFFF
00..FF
Direct
Short
Long
Indirect
Indirect
Indirect
Indirect
Direct
00..FF
byte
word
byte
word
ld A,[$10.w]
ld A,([$10],X)
ld A,([$10.w],X)
jrne loop
0000..FFFF 00..FF
00..1FE 00..FF
Short
Long
Indexed
Indexed
0000..FFFF 00..FF
PC+/-127
Relative
Relative
Bit
Indirect
Direct
jrne [$10]
PC+/-127
00..FF
00..FF
00..FF
00..FF
00..FF
00..FF
00..FF
byte
byte
byte
bset $10,#7
bset [$10],#7
btjt $10,#7,skip
btjt [$10],#7,skip
Bit
Indirect
Direct
Bit
Relative
Relative
Bit
Indirect
125/164
ST72311R, ST72511R, ST72512R, ST72532R
INSTRUCTION SET OVERVIEW (Cont’d)
11.1.1 Inherent
11.1.3 Direct
All Inherent instructions consist of a single byte.
The opcode fully specifies all the required informa-
tion for the CPU to process the operation.
In Direct instructions, the operands are referenced
by their memory address.
The direct addressing mode consists of two sub-
modes:
Inherent Instruction
Function
No operation
Direct (short)
NOP
The address is a byte, thus requires only one byte
after the opcode, but only allows 00 - FF address-
ing space.
TRAP
S/W Interrupt
Wait For Interrupt (Low Pow-
er Mode)
WFI
Direct (long)
Halt Oscillator (Lowest Power
Mode)
HALT
The address is a word, thus allowing 64 Kbyte ad-
dressing space, but requires 2 bytes after the op-
code.
RET
Sub-routine Return
Interrupt Sub-routine Return
Set Interrupt Mask (level 3)
Reset Interrupt Mask (level 0)
Set Carry Flag
IRET
SIM
11.1.4 Indexed (No Offset, Short, Long)
RIM
In this mode, the operand is referenced by its
memory address, which is defined by the unsigned
addition of an index register (X or Y) with an offset.
SCF
RCF
Reset Carry Flag
RSP
Reset Stack Pointer
Load
The indirect addressing mode consists of three
sub-modes:
LD
CLR
Clear
Indexed (No Offset)
PUSH/POP
INC/DEC
TNZ
Push/Pop to/from the stack
Increment/Decrement
Test Negative or Zero
1 or 2 Complement
Byte Multiplication
There is no offset, (no extra byte after the opcode),
and allows 00 - FF addressing space.
Indexed (Short)
CPL, NEG
MUL
The offset is a byte, thus requires only one byte af-
ter the opcode and allows 00 - 1FE addressing
space.
SLL, SRL, SRA, RLC,
RRC
Shift and Rotate Operations
Swap Nibbles
Indexed (long)
The offset is a word, thus allowing 64 Kbyte ad-
dressing space and requires 2 bytes after the op-
code.
SWAP
11.1.2 Immediate
Immediate instructions have two bytes, the first
byte contains the opcode, the second byte con-
tains the operand value.
11.1.5 Indirect (Short, Long)
The required data byte to do the operation is found
by its memory address, located in memory (point-
er).
Immediate Instruction
Function
LD
Load
The pointer address follows the opcode. The indi-
rect addressing mode consists of two sub-modes:
CP
Compare
BCP
Bit Compare
Indirect (short)
AND, OR, XOR
ADC, ADD, SUB, SBC
Logical Operations
Arithmetic Operations
The pointer address is a byte, the pointer size is a
byte, thus allowing 00 - FF addressing space, and
requires 1 byte after the opcode.
Indirect (long)
The pointer address is a byte, the pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.
126/164
ST72311R, ST72511R, ST72512R, ST72532R
11.1.7 Relative mode (Direct, Indirect)
INSTRUCTION SET OVERVIEW (Cont’d)
11.1.6 Indirect Indexed (Short, Long)
This is a combination of indirect and short indexed
addressing modes. The operand is referenced by
its memory address, which is defined by the un-
signed addition of an index register value (X or Y)
with a pointer value located in memory. The point-
er address follows the opcode.
This addressing mode is used to modify the PC
register value, by adding an 8-bit signed offset to
it.
Available Relative
Direct/Indirect
Instructions
Function
The indirect indexed addressing mode consists of
two sub-modes:
JRxx
CALLR
Conditional Jump
Call Relative
Indirect Indexed (Short)
The pointer address is a byte, the pointer size is a
byte, thus allowing 00 - 1FE addressing space,
and requires 1 byte after the opcode.
The relative addressing mode consists of two sub-
modes:
Relative (Direct)
Indirect Indexed (Long)
The offset is following the opcode.
Relative (Indirect)
The pointer address is a byte, the pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.
The offset is defined in memory, which address
follows the opcode.
Table 26. Instructions Supporting Direct,
Indexed, Indirect and Indirect Indexed
Addressing Modes
Long and Short
Function
Instructions
LD
Load
CP
Compare
AND, OR, XOR
Logical Operations
Arithmetic Additions/Sub-
stractions operations
ADC, ADD, SUB, SBC
BCP
Bit Compare
Short Instructions
Only
Function
CLR
Clear
INC, DEC
TNZ
Increment/Decrement
Test Negative or Zero
1 or 2 Complement
Bit Operations
CPL, NEG
BSET, BRES
Bit Test and Jump Opera-
tions
BTJT, BTJF
SLL, SRL, SRA, RLC,
RRC
Shift and Rotate Opera-
tions
SWAP
Swap Nibbles
CALL, JP
Call or Jump subroutine
127/164
ST72311R, ST72511R, ST72512R, ST72532R
INSTRUCTION SET OVERVIEW (Cont’d)
11.2 INSTRUCTION GROUPS
The ST7 family devices use an Instruction Set
consisting of 63 instructions. The instructions may
be subdivided into 13 main groups as illustrated in
the following table:
Load and Transfer
LD
CLR
POP
DEC
TNZ
OR
Stack operation
PUSH
INC
RSP
BCP
Increment/Decrement
Compare and Tests
Logical operations
CP
AND
BSET
BTJT
ADC
SLL
XOR
CPL
NEG
Bit Operation
BRES
BTJF
ADD
SRL
JRT
Conditional Bit Test and Branch
Arithmetic operations
Shift and Rotates
SUB
SRA
JRF
SBC
RLC
JP
MUL
RRC
CALL
SWAP
CALLR
SLA
Unconditional Jump or Call
Conditional Branch
JRA
JRxx
TRAP
SIM
NOP
RET
Interruption management
Code Condition Flag modification
WFI
RIM
HALT
SCF
IRET
RCF
Using a pre-byte
The instructions are described with one to four op-
codes.
These prebytes enable instruction in Y as well as
indirect addressing modes to be implemented.
They precede the opcode of the instruction in X or
the instruction using direct addressing mode. The
prebytes are:
In order to extend the number of available op-
codes for an 8-bit CPU (256 opcodes), three differ-
ent prebyte opcodes are defined. These prebytes
modify the meaning of the instruction they pre-
cede.
PDY 90
Replace an X based instruction
using immediate, direct, indexed, or inherent ad-
dressing mode by a Y one.
The whole instruction becomes:
PIX 92
Replace an instruction using di-
PC-2
PC-1
PC
End of previous instruction
Prebyte
rect, direct bit, or direct relative addressing mode
to an instruction using the corresponding indirect
addressing mode.
opcode
It also changes an instruction using X indexed ad-
dressing mode to an instruction using indirect X in-
dexed addressing mode.
PC+1
Additional word (0 to 2) according
to the number of bytes required to compute the ef-
fective address
PIY 91
Replace an instruction using X in-
direct indexed addressing mode by a Y one.
128/164
ST72311R, ST72511R, ST72512R, ST72532R
INSTRUCTION SET OVERVIEW (Cont’d)
Mnemo
ADC
ADD
AND
BCP
Description
Add with Carry
Function/Example
A = A + M + C
A = A + M
Dst
Src
I1
H
H
H
I0
N
N
N
N
N
Z
Z
Z
Z
Z
C
C
C
A
M
Addition
A
M
M
M
Logical And
A = A . M
A
Bit compare A, Memory
Bit Reset
tst (A . M)
A
BRES
BSET
BTJF
BTJT
CALL
CALLR
CLR
bres Byte, #3
bset Byte, #3
btjf Byte, #3, Jmp1
btjt Byte, #3, Jmp1
M
M
M
M
Bit Set
Jump if bit is false (0)
Jump if bit is true (1)
Call subroutine
Call subroutine relative
Clear
C
C
reg, M
reg
0
N
N
N
1
Z
Z
Z
CP
Arithmetic Compare
One Complement
Decrement
tst(Reg - M)
A = FFH-A
dec Y
M
C
1
CPL
reg, M
reg, M
DEC
HALT
IRET
INC
Halt
1
0
Interrupt routine return
Increment
Pop CC, A, X, PC
inc X
I1
H
I0
N
N
Z
Z
C
reg, M
JP
Absolute Jump
Jump relative always
Jump relative
Never jump
jp [TBL.w]
JRA
JRT
JRF
jrf *
JRIH
JRIL
Jump if Port B INT pin = 1 (no Port B Interrupts)
Jump if Port B INT pin = 0 (Port B interrupt)
JRH
Jump if H = 1
H = 1 ?
JRNH
JRM
Jump if H = 0
H = 0 ?
Jump if I1:0 = 11
Jump if I1:0 <> 11
Jump if N = 1 (minus)
Jump if N = 0 (plus)
Jump if Z = 1 (equal)
I1:0 = 11 ?
I1:0 <> 11 ?
N = 1 ?
JRNM
JRMI
JRPL
JREQ
JRNE
JRC
N = 0 ?
Z = 1 ?
Jump if Z = 0 (not equal) Z = 0 ?
Jump if C = 1
Jump if C = 0
Jump if C = 1
C = 1 ?
JRNC
JRULT
C = 0 ?
Unsigned <
Jmp if unsigned >=
Unsigned >
JRUGE Jump if C = 0
JRUGT Jump if (C + Z = 0)
129/164
ST72311R, ST72511R, ST72512R, ST72532R
INSTRUCTION SET OVERVIEW (Cont’d)
Mnemo
JRULE
LD
Description
Jump if (C + Z = 1)
Load
Function/Example
Unsigned <=
dst <= src
Dst
Src
I1
H
I0
N
N
N
N
N
Z
Z
Z
Z
Z
C
reg, M
A, X, Y
reg, M
M, reg
X, Y, A
MUL
NEG
NOP
OR
Multiply
X,A = X * A
neg $10
0
0
Negate (2’s compl)
No Operation
OR operation
C
A = A + M
pop reg
pop CC
push Y
C = 0
A
M
reg
CC
M
M
POP
Pop from the Stack
M
I1
1
H
I0
0
C
0
PUSH
RCF
RET
RIM
Push onto the Stack
Reset carry flag
Subroutine Return
Enable Interrupts
Rotate left true C
Rotate right true C
Reset Stack Pointer
Substract with Carry
Set carry flag
reg, CC
I1:0 = 10 (level 0)
C <= A <= C
C => A => C
S = Max allowed
A = A - M - C
C = 1
RLC
RRC
RSP
SBC
SCF
SIM
reg, M
reg, M
N
N
Z
Z
C
C
A
M
N
Z
C
1
Disable Interrupts
Shift left Arithmetic
Shift left Logic
I1:0 = 11 (level 3)
C <= A <= 0
C <= A <= 0
0 => A => C
A7 => A => C
A = A - M
1
1
SLA
reg, M
reg, M
reg, M
reg, M
A
N
N
0
Z
Z
Z
Z
Z
Z
Z
C
C
C
C
C
SLL
SRL
SRA
SUB
SWAP
TNZ
TRAP
WFI
Shift right Logic
Shift right Arithmetic
Substraction
N
N
N
N
M
M
SWAP nibbles
A7-A4 <=> A3-A0
tnz lbl1
reg, M
Test for Neg & Zero
S/W trap
S/W interrupt
1
1
1
0
Wait for Interrupt
Exclusive OR
XOR
A = A XOR M
A
N
Z
130/164
ST72311R, ST72511R, ST72512R, ST72532R
12 ELECTRICAL CHARACTERISTICS
12.1 PARAMETER CONDITIONS
Unless otherwise specified, all voltages are re-
12.1.5 Pin input voltage
ferred to V
.
SS
The input voltage measurement on a pin of the de-
vice is described in Figure 65.
12.1.1 Minimum and Maximum values
Unless otherwise specified the minimum and max-
imum values are guaranteed in the worst condi-
tions of ambient temperature, supply voltage and
frequencies by tests in production on 100% of the
Figure 65. Pin input voltage
devices with an ambient temperature at T =25°C
A
ST7 PIN
and T =T max (given by the selected temperature
A
A
range).
V
Data based on characterization results, design
simulation and/or technology characteristics are
indicated in the table footnotes and are not tested
in production. Based on characterization, the min-
imum and maximum values refer to sample tests
and represent the mean value plus or minus three
times the standard deviation (mean±3Σ).
IN
12.1.2 Typical values
Unless otherwise specified, typical data are based
on T =25°C, V =5V (for the 4.5V≤V ≤5.5V
A
DD
DD
voltage range) and V =3.3V (for the 3V≤V ≤4V
DD
DD
voltage range). They are given only as design
guidelines and are not tested.
12.1.3 Typical curves
Unless otherwise specified, all typical curves are
given only as design guidelines and are not tested.
12.1.4 Loading capacitor
The loading conditions used for pin parameter
measurement are shown in Figure 64.
Figure 64. Pin loading conditions
ST7 PIN
C
L
131/164
ST72311R, ST72511R, ST72512R, ST72532R
12.2 ABSOLUTE MAXIMUM RATINGS
Stresses above those listed as “absolute maxi-
mum ratings” may cause permanent damage to
the device. This is a stress rating only and func-
tional operation of the device under these condi-
tions is not implied. Exposure to maximum rating
conditions for extended periods may affect device
reliability.
12.2.1 Voltage Characteristics
Symbol
Ratings
Maximum value
Unit
V
- V
- V
Supply voltage
Analog reference voltage (V ≥V )
DD DDA
6.5
DD
SS
V
V
6.5
DDA
SSA
|∆V
| and |∆V
| Variations between different digital power pins
Variations between digital and analog ground pins
50
50
DDx
SSx
mV
V
|V
- V
|
SSA
SSx
Input voltage on V pin
VSS-0.3 to 13
VSS-0.3 to VDD+0.3
PP
V
IN
1) & 2)
Input voltage on any other pin
V
Electro-static discharge voltage (Human Body Model)
Electro-static discharge voltage (Machine Model)
see Section 12.7.2 ”Absolute Electri-
cal Sensitivity” on page 141
ESD(HBM)
V
ESD(MM)
12.2.2 Current Characteristics
Symbol
Ratings
Maximum value
Unit
3)
3)
I
Total current into V power lines (source)
150
150
25
VDD
DD
I
Total current out of V ground lines (sink)
SS
VSS
Output current sunk by any standard I/O and control pin
Output current sunk by any high sink I/O pin
I
50
IO
Output current source by any I/Os and control pin
- 25
± 5
± 5
± 5
± 5
± 20
mA
Injected current on V pin
PP
Injected current on RESET pin
2) & 4)
2)
I
INJ(PIN)
Injected current on OSC1 and OSC2 pins
5) & 6)
Injected current on any other pin
5)
ΣI
Total injected current (sum of all I/O and control pins)
INJ(PIN)
12.2.3 Thermal Characteristics
Symbol
Ratings
Value
Unit
T
Storage temperature range
-65 to +150
°C
STG
T
Maximum junction temperature (see Section 13.2 ”THERMAL CHARACTERISTICS” on page 155 )
J
Notes:
1. Directly connecting the RESET and I/O pins to V or V could damage the device if an unintentional internal reset
DD
SS
is generated or an unexpected change of the I/O configuration occurs (for example, due to a corrupted program counter).
To guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7kΩ for
RESET, 10kΩ for I/Os). Unused I/O pins must be tied in the same way to V orV according to their reset configuration.
DD
SS
2. When the current limitation is not possible, the V absolute maximum rating must be respected, otherwise refer to
IN
I
specification. A positive injection is induced by V >V while a negative injection is induced by V <V
.
INJ(PIN)
IN
DD
IN
SS
3. All power (V ) and ground (V ) lines must always be connected to the external supply.
DD
SS
4. Negative injection disturbs the analog performance of the device. In particular, it induces leakage currents throughout
the device including the analog inputs. To avoid undesirable effect on analog part, care must be taken:
- Analog input pins must have a negative injection less than 0.8 mA (assuming that the impedance of the analog voltage
is lower than the specified limits)
- Pure digital pins must have a negative injection less than 1.6mA. In addition, it is recommended to inject the current as
far as possible from the analog input pins.
5. When several inputs are submitted to a current injection, the maximum ΣI
is the absolute sum of the positive
INJ(PIN)
and negative injected currents (instantaneous values). These results are based on characterisation with ΣI
mum current injection on four I/O port pins of the device.
maxi-
INJ(PIN)
6. True open drain I/O port pins do not accept positive injection.
132/164
ST72311R, ST72511R, ST72512R, ST72532R
12.3 OPERATING CONDITIONS
12.3.1 General Operating Conditions
Symbol
Parameter
Supply voltage
Conditions
Min
Max
Unit
V
see Figure 66 and Figure 67
3.0
5.5
V
DD
V
V
≥3.5V (without EEPROM)
≥4.5V (with EEPROM)
1)
DD
DD
0
16
f
External clock frequency
MHz
OSC
1)
V
≥3.0V
0
8
DD
1 Suffix Version
6 Suffix Version
7 Suffix Version
3 Suffix Version
0
70
-40
-40
-40
85
T
Ambient temperature range
°C
A
105
125
2)
Figure 66. f
Maximum Operating Frequency Versus VDD Supply for devices without EEPROM
OSC
f
[MHz]
FUNCTIONALITY
OSC
GUARANTEED
IN THIS AREA
16
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
8
4
1)
WITH RESONATOR
1
0
SUPPLY VOLTAGE [V]
2)
2.5
3
3.5
4
4.5
5
5.5
Figure 67. f
Maximum Operating Frequency Versus VDD Supply for device with EEPROM
OSC
FUNCTIONALITY NOT GUARANTEED IN THIS AREA
FOR TEMPERATURE HIGHER THAN 85°C
f
[MHz]
OSC
FUNCTIONALITY
GUARANTEED
IN THIS AREA
16
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
8
4
1)
WITH RESONATOR
1
0
SUPPLY VOLTAGE [V]
2.5
3
3.5
4
4.5
5
5.5
Notes:
1. Guaranteed by construction. A/D operation is not guaranteed below 1MHz.
2. Operating conditions with T =-40 to +125°C.
A
133/164
ST72311R, ST72511R, ST72512R, ST72532R
OPERATING CONDITIONS (Cont’d)
12.3.2 Operating Conditions with Low Voltage Detector (LVD)
Subject to general operating condition for V , f
, and T .
DD OSC
A
1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Reset release threshold
V
3.95
4.15
4.35
IT+
(V rise)
DD
V
Reset generation threshold
V
V
3.70
0.02
3.90
250
4.10
40
IT-
(V fall)
DD
LVD voltage threshold hysteresis
V
-V
IT+ IT-
mV
V/ms
ns
hyst
2)
Vt
V
rise time rate
DD
POR
t
Filtered glitch delay on V
Not detected by the LVD
g(VDD)
DD
2)
Figure 68. LVD Threshold Versus VDD and f
for ROM devices
OSC
f
[MHz]
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
OSC
16
DEVICE UNDER
RESET
IN THIS AREA
FUNCTIONAL AREA
8
0
SUPPLY VOLTAGE [V]
V
≥3.70
IT-
2.5
3
3.5
4
4.5
5
5.5
Notes:
1. LVD typical data are based on T =25°C. They are given only as design guidelines and are not tested.
A
2. The minimum V rise time rate is needed to insure a correct device power-on and LVD reset. Not tested in production.
DD
134/164
ST72311R, ST72511R, ST72512R, ST72532R
12.4 SUPPLY CURRENT CHARACTERISTICS
The following current consumption specified for
the ST7 functional operating modes over tempera-
ture range does not take into account the clock
source current consumption. To get the total de-
vice consumption, the two current values must be
added (except for HALT mode for which the clock
is stopped).
Symbol
∆I
Parameter
Conditions
Max
Unit
Supply current variation vs. temperature
Constant V and f
10
%
DD(∆Ta)
DD
CPU
12.4.1 RUN and SLOW Modes
1)
2)
Symbol
Parameter
Conditions
Typ
Max
Unit
2.5
6.5
14.5
4
9
20
f
f
f
=1MHz, f
=500kHz
=2MHz
=8MHz
3)
OSC
OSC
OSC
CPU
Supply current in RUN mode
(see Figure 69)
=4MHz, f
CPU
=16MHz, f
CPU
0.3
0.8
1.8
0.5
2.0
3.0
f
f
f
=1MHz, f
=31.25kHz
=125kHz
=500kHz
4)
4)
OSC
OSC
OSC
CPU
Supply current in SLOW mode
(see Figure 70)
=4MHz, f
=16MHz, f
CPU
CPU
I
mA
DD
1.6
3.6
8
2.4
5.4
12
f
f
f
=1MHz, f
=500kHz
=2MHz
=8MHz
3)
OSC
OSC
OSC
CPU
Supply current in RUN mode
(see Figure 69)
=4MHz, f
CPU
=16MHz, f
CPU
0.15
0.45
1
0.3
0.9
1.5
f
f
f
=1MHz, f
=31.25kHz
=125kHz
=500kHz
OSC
OSC
OSC
CPU
Supply current in SLOW mode
(see Figure 70)
=4MHz, f
CPU
=16MHz, f
CPU
Figure 69. Typical I in RUN vs. f
Figure 70. Typical I in SLOW vs. f
CPU
DD
CPU
DD
IDD [mA]
IDD [mA]
20
2.5
500kHz
8MHz
2MHz
125kHz
2
4MHz 500kHz
15
10
5
31.25kHz
1.5
1
0.5
0
0
3
3.5
4
4.5
5
5.5
3
3.5
4
4.5
5
5.5
VDD [V]
VDD [V]
Notes:
1. Typical data are based on T =25°C, V =5V (4.5V≤V ≤5.5V range) and V =3.3V (3V≤V ≤3.6V range).
A
DD
DD
DD
DD
2. Data based on characterization results, tested in production at V max. and f
max.
CPU
DD
3. CPU running with memory access, all I/O pins in input mode with a static value at V or V (no load), all peripherals
DD
SS
switched off; clock input (OSC1) driven by external square wave, LVD disabled.
4. SLOW mode selected with f based on f divided by 32. All I/O pins in input mode with a static value at V or
CPU
OSC
DD
V
(no load), all peripherals switched off; clock input (OSC1) driven by external square wave, LVD disabled.
SS
135/164
ST72311R, ST72511R, ST72512R, ST72532R
SUPPLY CURRENT CHARACTERISTICS (Cont’d)
12.4.2 WAIT and SLOW WAIT Modes
1)
2)
Symbol
Parameter
Conditions
Typ
Max
Unit
1.25
3.2
5.2
2
5
9
f
f
f
=1MHz, f
=500kHz
=2MHz
=8MHz
3)
OSC
OSC
OSC
CPU
Supply current in WAIT mode
(see Figure 71)
=4MHz, f
CPU
=16MHz, f
CPU
0.2
0.6
1.2
0.35
1
2
f
f
f
=1MHz, f
=31.25kHz
=125kHz
=500kHz
4)
4)
OSC
OSC
OSC
CPU
Supply current in SLOW WAIT mode
(see Figure 72)
=4MHz, f
=16MHz, f
CPU
CPU
I
mA
DD
0.7
1.6
2.7
1
2.6
4.5
f
f
f
=1MHz, f
=500kHz
=2MHz
=8MHz
3)
OSC
OSC
OSC
CPU
Supply current in WAIT mode
=4MHz, f
CPU
(see Figure 71)
=16MHz, f
CPU
0.1
0.3
0.6
0.15
0.5
1
f
f
f
=1MHz, f
=31.25kHz
=125kHz
=500kHz
OSC
OSC
OSC
CPU
Supply current in SLOW WAIT mode
(see Figure 72)
=4MHz, f
CPU
=16MHz, f
CPU
Figure 71. Typical I in WAIT vs. f
Figure 72. Typical I in SLOW-WAIT vs. f
CPU
DD
CPU
DD
IDD [mA]
7
IDD [mA]
1.5
8MHz 2MHz 500kHz
6
500kHz 125kHz 31.25kHz
5
4
3
2
1
0
1
0.5
0
3
3.5
4
4.5
5
5.5
3
3.5
4
4.5
5
5.5
VDD [V]
VDD [V]
Notes:
1. Typical data are based on T =25°C, V =5V (4.5V≤V ≤5.5V range) and V =3.3V (3V≤V ≤3.6V range).
A
DD
DD
DD
DD
2. Data based on characterization results, tested in production at V max. and f
max.
DD
CPU
3. All I/O pins in input mode with a static value at V
driven by external square wave, LVD disabled.
or V (no load), all peripherals switched off; clock input (OSC1)
SS
DD
4. SLOW-WAIT mode selected with f
DD
based on f
divided by 32. All I/O pins in input mode with a static value at
OSC
CPU
V
or V (no load), all peripherals switched off; clock input (OSC1) driven by external square wave, LVD disabled.
SS
136/164
ST72311R, ST72511R, ST72512R, ST72532R
SUPPLY CURRENT CHARACTERISTICS (Cont’d)
12.4.3 HALT and ACTIVE-HALT Modes
1)
Symbol
Parameter
Conditions
Typ
0
Max
10
Unit
-40°C≤T ≤+105°C
3.0V≤V
A
2)
DD
Supply current in HALT mode
V
≤5.5V
I
40°C≤T ≤+125°C
50
µA
DD
DD
A
3)
Supply current in ACTIVE-HALT mode
50
150
12.4.4 Supply and Clock Managers
The previous current consumption specified for
the ST7 functional operating modes over tempera-
ture range does not take into account the clock
source current consumption. To get the total de-
vice consumption, the two current values must be
added (except for HALT mode).
4)
5)
Symbol
Parameter
Supply current of resonator oscillator
LVD supply current
Conditions
Typ
Max
Unit
6) & 7)
I
600
100
850
150
DD(CK)
µA
I
HALT mode
DD(LVD)
12.4.5 On-Chip Peripheral
Symbol
Parameter
Conditions
Typ
50
Unit
V
V
V
V
V
V
=3.3V
=5.0V
=3.3V
=5.0V
=3.3V
=5.0V
DD
DD
DD
DD
DD
DD
8)
I
16-bit Timer supply current
f
f
f
=8MHz
=8MHz
=4MHz
DD(TIM)
CPU
CPU
ADC
150
250
350
800
1100
9)
I
SPI supply current
ADC supply current when converting
µA
DD(SPI)
10)
I
DD(ADC)
Notes:
1. Typical data are based on T =25°C.
A
2. All I/O pins in input mode with a static value at V or V (no load), LVD disabled.
DD
SS
3. Data based on design simulation and/or technology characteristics, not tested in production. All I/O pins in input mode
with a static value at V or V (no load); clock input (OSC1) driven by external square wave, LVD disabled.
DD
SS
4. Typical data are based on T =25°C, V =5V.
A
DD
5. Data based on characterization results, not tested in production.
6. Data based on characterization results done with the typical external components, not tested in production.
7. As the oscillator is based on a current source, the consumption does not depend on the voltage.
8. Data based on a differential I measurement between reset configuration (timer counter running at f
/4) and timer
CPU
DD
counter stopped (selecting external clock capability). Data valid for one timer.
9. Data based on a differential I measurement between reset configuration and a permanent SPI master communica-
DD
tion (data sent equal to 55h).
10. Data based on a differential I measurement between reset configuration and continuous A/D conversions.
DD
137/164
ST72311R, ST72511R, ST72512R, ST72532R
12.5 CLOCK AND TIMING CHARACTERISTICS
Subject to general operating condition for V , f
, and T .
DD OSC
A
12.5.1 General Timings
1)
Symbol
Parameter
Conditions
Min
2
Typ
Max
12
Unit
tCPU
ns
4
t
Instruction cycle time
c(INST)
f
f
=8MHz
250
10
500
1500
22
CPU
2)
tCPU
µs
Interrupt reaction time
t
v(IT)
t
= ∆t
+ 10
=8MHz
1.25
2.75
v(IT)
c(INST)
CPU
12.5.2 External Clock Source
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
V
OSC1 input pin high level voltage
OSC1 input pin low level voltage
0.7xV
V
V
DD
OSC1H
DD
V
V
0.3xV
OSC1L
SS
DD
t
t
3)
w(OSC1H)
see Figure 73
OSC1 high or low time
15
w(OSC1L)
ns
t
t
3)
r(OSC1)
OSC1 rise or fall time
15
f(OSC1)
R
Oscillator bypass exteranl resistor
1
kΩ
OBP
Figure 73. Typical Application with an External Clock Source
90%
V
V
OSC1H
OSC1L
10%
t
t
w(OSC1H)
t
t
w(OSC1L)
f(OSC1)
r(OSC1)
12.5.3 Crystal and Ceramic Resonator Oscillators
Symbol
Parameter
Oscillator Frequency
Conditions
Min
4
Max
16
Unit
MHz
pF
f
OSC
4)
5)
C
, C
Load capacitance
Oscillator start-up time
R =100Ω
12
21
L1
L2
S
t
Depends on resonator quality. A typical value is 10ms
START
Notes:
1. Data based on typical application software.
2. Time measured between interrupt event and interrupt vector fetch. ∆tc(INST) is the number of tCPU cycles needed to finish
the current instruction execution.
3. Data based on design simulation and/or technology characteristics, not tested in production.
4. C (resp.C ) is load capacitance on OSC1 (resp. OSC2) pin.
L1
L2
5. R is the equivalent serial resistance of the crystal or ceramic resonator.
S
138/164
ST72311R, ST72511R, ST72512R, ST72532R
12.6 MEMORY CHARACTERISTICS
Subject to general operating condition for V , f
, and T unless otherwise specified.
DD OSC
A
12.6.1 RAM and Hardware Registers
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
1)
V
Data retention mode
HALT mode (or RESET)
1.6
V
RM
12.6.2 EEPROM Data Memory
Symbol
Parameter
Conditions
Min
Typ
Max
10
Unit
-40°C≤T ≤+85°C
Programming time
(for 1 up to 16 bytes at a time)
A
t
ms
prog
-40°C≤T ≤+125°C
15
A
3)
2)
t
Data retention
T =+55°C
20
Years
ret
A
3)
N
Write erase cycles
T =+25°C
300 000
Cycles
RW
A
12.6.3 EPROM Program Memory
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Watt.sec
/cm
W
UV lamp
Lamp wavelength 2537Å
15
2
ERASE
UV lamp is placed 1 inch
from the device window
without any interposed
4)
t
Erase Time
15
20
20
min
erase
filters
3)
2)
t
Data retention
T =+55°C
years
ret
A
Notes:
1. Minimum V supply voltage without losing data stored into RAM (in in HALT mode or under RESET) or into hardware
DD
registers (only in HALT mode). Guaranteed by construction, not tested in production.
2. The data retention time increase when the T decreases.
A
3. Data based on reliability test results and monitored in production.
4. Data given only as guidelines.
139/164
ST72311R, ST72511R, ST72512R, ST72532R
12.7 EMC CHARACTERISTICS
Susceptibility tests are performed on a sample ba-
sis during product characterization.
■ ESD: Electro-Static Discharge (positive and
negative) is applied on all pins of the device until
a functional disturbance occurs. This test
conforms with the IEC 1000-4-2 standard.
12.7.1 Functional EMS
(Electro Magnetic Susceptibility)
■ FTB: A Burst of Fast Transient voltage (positive
Based on a simple running application on the
product (toggling 2 LEDs through I/O ports), the
product is stressed by two electro magnetic events
until a failure occurs (indicated by the LEDs).
and negative) is applied to V and V through
DD
SS
a 100pF capacitor, until a functional disturbance
occurs. This test conforms with the IEC 1000-4-
4 standard.
A device reset allows normal operations to be re-
sumed.
1)
1)
Symbol
Parameter
Conditions
=5V, T =+25°C, f
conforms to IEC 1000-4-2
Neg
Pos
Unit
Voltage limits to be applied on any I/O pin
to induce a functional disturbance
V
=8MHz
OSC
DD
A
V
-1
1
FESD
kV
Fast transient voltage burst limits to be ap-
V
=5V, T =+25°C, f
=8MHz
OSC
DD
A
V
plied through 100pF on V and V pins
-4
4
FFTB
DD
DD
conforms to IEC 1000-4-4
to induce a functional disturbance
2)
Figure 74. EMC Recommended star network power supply connection
ST72XXX
10nF 0.1µF
V
V
DD
SS
ST7
DIGITAL NOISE
FILTERING
V
DD
POWER
SUPPLY
SOURCE
V
V
SSA
DDA
EXTERNAL
NOISE
FILTERING
0.1µF
Notes:
1. Data based on characterization results, not tested in production.
2. The suggested 10nF and 0.1µF decoupling capacitors on the power supply lines are proposed as a good price vs. EMC
performance tradeoff. They have to be put as close as possible to the device power supply pins. Other EMC recommen-
dations are given in other sections (I/Os, RESET, OSCx pin characteristics).
140/164
ST72311R, ST72511R, ST72512R, ST72532R
Machine Model Test Sequence
EMC CHARACTERISTICS (Cont’d)
12.7.2 Absolute Electrical Sensitivity
Based on three different tests (ESD, LU and DLU)
using specific measurement methods, the product
is stressed in order to determine its performance in
terms of electrical sensitivity. For more details, re-
fer to the AN1181 ST7 application note.
– C is loaded through S1 by the HV pulse gener-
ator.
L
– S1 switches position from generator to ST7.
– A discharge from C to the ST7 occurs.
L
– S2 must be closed 10 to 100ms after the pulse
delivery period to ensure the ST7 is not left in
charge state. S2 must be opened at least 10ms
prior to the delivery of the next pulse.
12.7.2.1 Electro-Static Discharge (ESD)
Electro-Static Discharges (3 positive then 3 nega-
tive pulses separated by 1 second) are applied to
the pins of each sample according to each pin
combination. The sample size depends of the
number of supply pins of the device (3 parts*(n+1)
supply pin). Two models are usually simulated:
Human Body Model and Machine Model. This test
conforms to the JESD22-A114A/A115A standard.
See Figure 75 and the following test sequences.
– R (machine resistance), in series with S2, en-
sures a slow discharge of the ST7.
Human Body Model Test Sequence
– C is loaded through S1 by the HV pulse gener-
L
ator.
– S1 switches position from generator to R.
– Adischarge from C through R(body resistance)
L
to the ST7 occurs.
– S2 must be closed 10 to 100ms after the pulse
delivery period to ensure the ST7 is not left in
charge state. S2 must be opened at least 10ms
prior to the delivery of the next pulse.
Absolute Maximum Ratings
1)
Symbol
Ratings
Conditions
Maximum value
Unit
Electro-static discharge voltage
(Human Body Model)
T =+25°C
V
2500
A
ESD(HBM)
V
Electro-static discharge voltage
(Machine Model)
V
T =+25°C
TBD
ESD(MM)
A
Figure 75. Typical Equivalent ESD Circuits
S1
R=1500Ω
S1
HIGH VOLTAGE
PULSE
GENERATOR
HIGH VOLTAGE
PULSE
GENERATOR
ST7
ST7
C =100pF
S2
L
S2
C =200pF
L
HUMAN BODY MODEL
MACHINE MODEL
Notes:
1. Data based on characterization results, not tested in production.
141/164
ST72311R, ST72511R, ST72512R, ST72532R
EMC CHARACTERISTICS (Cont’d)
12.7.2.2 Static and Dynamic Latch-Up
■ DLU: Electro-Static Discharges (one positive
then one negative test) are applied to each pin
of 3 samples when the micro is running to
assess the latch-up performance in dynamic
mode. Power supplies are set to the typical
values, the oscillator is connected as near as
possible to the pins of the micro and the
component is put in reset mode. This test
conforms to the IEC1000-4-2 and SAEJ1752/3
standards and is described in Figure 76. For
more details, refer to the AN1181 ST7
application note.
■ LU: 3 complementary static tests are required
on 10parts to assess the latch-up performance.
A supply overvoltage (applied to each power
supply pin), a current injection (applied to each
input, output and configurable I/O pin) and a
power supply switch sequence are performed
on each sample. This test conforms to the EIA/
JESD 78 IC latch-up standard. For more details,
refer to the AN1181 ST7 application note.
Electrical Sensitivities
1)
Symbol
LU
Parameter
Static latch-up class
Dynamic latch-up class
Conditions
Class
T =+25°C
A
A
A
T =+85°C
A
V
=5.5V, f
=4MHz, T =+25°C
DLU
TBD
DD
OSC
A
Figure 76. Simplified Diagram of the ESD Generator for DLU
R
2)
=50MΩ
R =330Ω
D
CH
DISCHARGE TIP
V
V
DD
SS
HV RELAY
C =150pF
S
ST7
ESD
GENERATOR
DISCHARGE
RETURN CONNECTION
Notes:
1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC spec-
ifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the
JEDEC criteria (international standard).
2. Schaffner NSG435 with a pointed test finger.
142/164
ST72311R, ST72511R, ST72512R, ST72532R
Standard Pin Protection
EMC CHARACTERISTICS (Cont’d)
12.7.3 ESD Pin Protection Strategy
To protect an integrated circuit against Electro-
Static Discharge the stress must be controlled to
prevent degradation or destruction of the circuit el-
ements. The stress generally affects the circuit el-
ements which are connected to the pads but can
also affect the internal devices when the supply
pads receive the stress. The elements to be pro-
tected must not receive excessive current, voltage
or heating within their structure.
To protect the output structure the following ele-
ments are added:
– A diode to V (3a) and a diode from V (3b)
DD
SS
– A protection device between V and V (4)
DD
SS
To protect the input structure the following ele-
ments are added:
– A resistor in series with the pad (1)
– A diode to V (2a) and a diode from V (2b)
DD
SS
– A protection device between V and V (4)
DD
SS
An ESD network combines the different input and
output ESD protections. This network works, by al-
lowing safe discharge paths for the pins subjected
to ESD stress. Two critical ESD stress cases are
presented in Figure 77 and Figure 78 for standard
pins and in Figure 79 and Figure 80 for true open
drain pins.
Figure 77. Positive Stress on a Standard Pad vs. V
SS
V
V
DD
DD
(3a)
(2a)
(1)
(4)
OUT
IN
Main path
(3b)
(2b)
Path to avoid
V
V
V
SS
SS
DD
Figure 78. Negative Stress on a Standard Pad vs. V
DD
V
DD
(3a)
(2a)
(1)
(4)
OUT
IN
Main path
(3b)
(2b)
V
V
SS
SS
143/164
ST72311R, ST72511R, ST72512R, ST72532R
EMC CHARACTERISTICS (Cont’d)
True Open Drain Pin Protection
Multisupply Configuration
When several types of ground (V , V
The centralized protection (4) is not involved in the
discharge of the ESD stresses applied to true
open drain pads due to the fact that a P-Buffer and
, ...) and
SSA
SS
power supply (V , V
, ...) are available for any
DD
DDA
reason (better noise immunity...), the structure
shown in Figure 81 is implemented to protect the
device against ESD.
diode to V
are not implemented. An additional
DD
local protection between the pad and V (5a &
SS
5b) is implemented to completly absorb the posi-
tive ESD discharge.
Figure 79. Positive Stress on a True Open Drain Pad vs. V
SS
V
V
DD
DD
Main path
(1)
Path to avoid
OUT
(4)
IN
(5a)
(5b)
(3b)
(2b)
V
V
V
SS
SS
Figure 80. Negative Stress on a True Open Drain Pad vs. V
DD
V
DD
DD
Main path
(1)
OUT
(4)
IN
(3b)
(3b)
(3b)
(2b)
V
V
SS
SS
Figure 81. Multisupply Configuration
V
DD
V
DDA
V
DDA
V
SS
BACK TO BACK DIODE
BETWEEN GROUNDS
V
SSA
V
SSA
144/164
ST72311R, ST72511R, ST72512R, ST72532R
12.8 I/O PORT PIN CHARACTERISTICS
12.8.1 General Characteristics
Subject to general operating condition for V , f
, and T unless otherwise specified.
DD OSC
A
1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
V
2)
V
Input low level voltage
0.3xVDD
IL
2)
V
Input high level voltage
0.7xVDD
IH
3)
V
Schmitt trigger voltage hysteresis
Input leakage current
400
mV
µA
hys
I
V
SS≤V ≤V
DD
±1
L
IN
4)
I
Static current consumption
Floating input mode
V =V =5V
200
240
S
5)
R
Weak pull-up equivalent resistor
IO pin capacitance
V
DD
60
1
kΩ
PU
IN
SS
C
5
pF
IO
2)
t
Output high to low level fall time
25
25
C =50pF
Between 10% and 90%
f(IO)out
r(IO)out
L
ns
2)
t
Output low to high level rise time
6)
t
External interrupt pulse time
t
CPU
w(IT)in
Figure 82. Two typical Applications with unused I/O Pin
V
ST72XXX
DD
UNUSED I/O PORT
10kΩ
10kΩ
UNUSED I/O PORT
ST72XXX
Notes:
1. Unless otherwise specified, typical data are based on T =25°C and V =5V.
A
DD
2. Data based on characterization results, not tested in production.
3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
4. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for
example or an external pull-up or pull-down resistor (see Figure 82). Data based on design simulation and/or technology
characteristics, not tested in production.
5. The R pull-up equivalent resistor is based on a resistive transistor. This data is based on characterization results,
PU
not tested in production.
6. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external
interrupt source.
145/164
ST72311R, ST72511R, ST72512R, ST72532R
I/O PORT PIN CHARACTERISTICS (Cont’d)
12.8.2 Output Driving Current
Subject to general operating condition for V , f
, and T unless otherwise specified.
A
DD OSC
Symbol
Parameter
Conditions
Min
Max
Unit
Output low level voltage for a standard I/O pin
when 8 pins are sunk at same time
(see Figure 83)
I
=+5mA
=+2mA
=+20mA
=+8mA
=-5mA
=-2mA
1.3
IO
I
0.4
1.3
0.4
IO
1)
V
OL
Output low level voltage for a high sink I/O pin
when 4 pins are sunk at same time
(see Figure 84)
I
IO
V
I
IO
Output high level voltage for an I/O pin
when 8 pins are sourced at same time
(see Figure 85)
I
V
V
-2.0
IO
DD
2)
V
OH
I
-0.8
IO
DD
Figure 83. Typical V at V =5V (standard)
Figure 85. Typical V -V at V =5V
DD OH DD
OL
DD
Ta=-40°C
Ta=25°C
Ta=85°C
Ta=125°C
Vol [V]
Vdd-Voh [V]
(Vdd=5V)
Ta=-40°C
Ta=25°C
Ta=85°C
Ta=125°C
(Vdd=5V)
1.5
1.4
1.2
1
1
0.8
0.6
0.4
0.2
0.5
0
0
0
2
4
6
8
-8
-6
-4
-2
0
Iio [mA]
Iio [mA]
Figure 84. Typical V at V =5V (high-sink)
OL
DD
Ta=-40°C
Ta=25°C
Ta=85°C
Ta=125°C
Vol [V]
(Vdd=5V)
2
1.5
1
0.5
0
0
10
20
Iio [mA]
30
40
Notes:
1. The I current sunk must always respect the absolute maximum rating specified in Section 12.2.2 and the sum of I
IO
IO
(I/O ports and control pins) must not exceed I
.
VSS
2. The I current sourced must always respect the absolute maximum rating specified in Section 12.2.2 and the sum of
IO
I
(I/O ports and control pins) must not exceed I
. True open drain I/O pins does not have V
.
IO
VDD
OH
146/164
ST72311R, ST72511R, ST72512R, ST72532R
12.9 CONTROL PIN CHARACTERISTICS
12.9.1 Asynchronous RESET Pin
Subject to general operating condition for V , f
, and T unless otherwise specified.
DD OSC
A
1)
Symbol
Parameter
Conditions
Min
0.7xVDD
20
Typ
Max
Unit
2)
V
Input low level voltage
0.3xVDD
IL
V
2)
V
Input high level voltage
IH
3)
V
Schmitt trigger voltage hysteresis
400
mV
kΩ
µs
hys
4)
R
Weak pull-up equivalent resistor
Generated reset pulse duration
External reset pulse hold time
V =V
V =5V
DD
60
ON
IN
SS
t
Watchdog reset source
1
w(RSTL)out
t
20
µs
h(RSTL)in
5)
Figure 86. Typical Application with RESET pin
V
ST72XXX
DD
V
V
DD
DD
INTERNAL RESET CONTROL
R
ON
0.1µF
0.1µF
4.7kΩ
EXTERNAL
RESET
CIRCUIT
RESET
WATCHDOG RESET
LVD RESET
12.9.2 V Pin
PP
Subject to general operating condition for V , f
, and T unless otherwise specified.
A
DD OSC
Symbol
Parameter
Conditions
Min
Max
Unit
6)
V
Input low level voltage
V
0.2
IL
SS
V
6)
V
Input high level voltage
V
-0.1 12.6
IH
DD
7)
Figure 87. Two typical Applications with V Pin
PP
V
PP
PROGRAMMING
TOOL
V
PP
4.7kΩ
ST72XXX
ST72XXX
Notes:
1. Unless otherwise specified, typical data are based on T =25°C and V =5V.
A
DD
2. Data based on characterization results, not tested in production.
3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
4. The R
pull-up equivalent resistor is based on a resistive transistor. This data is based on characterization results,
ON
not tested in production.
5. The reset network protects the device against parasitic resets, especially in a noisy environment.
6. Data based on design simulation and/or technology characteristics, not tested in production.
7. When the in-circuit programming mode is not required by the application V pin must be tied to V
.
SS
PP
147/164
ST72311R, ST72511R, ST72512R, ST72532R
12.10 TIMER PERIPHERAL CHARACTERISTICS
Subject to general operating condition for V , f
Refer to I/O port characteristics for more details on
the input/output alternate function characteristics
(outpu compare, input capture, external clock,
PWM output...).
DD O-
, and T unless otherwise specified.
SC
A
12.10.1 Watchdog Timer
Symbol
Parameter
Conditions
Min
12,288
1.54
Typ
Max
786,432
98.3
Unit
tCPU
ms
t
Watchdog time-out duration
w(WDG)
fCPU=8MHz
12.10.2 8-Bit PWM-ART Auto-Reload Timer
Symbol
Parameter
Conditions
Min
1
Typ
Max
Unit
t
CPU
t
PWM resolution time
res(PWM)
f
=8MHz
125
0
ns
CPU
f
ART external clock frequency
PWM repetition rate
f
/2
EXT
CPU
MHz
f
0
f
/2
PWM
CPU
Res
PWM resolution
8
bit
PWM
OS
V
PWM/DAC output step voltage
V
=5V, Res=8-bits
20
mV
DD
12.10.3 16-Bit Timer
Symbol
Parameter
Conditions
Min
1
Typ
Max
Unit
t
Input capture pulse time
t
t
w(ICAP)in
CPU
2
CPU
t
PWM resolution time
res(PWM)
f
=8MHz
250
0
ns
CPU
f
Timer external clock frequency
PWM repetition rate
f
/4
MHz
MHz
bit
EXT
CPU
f
0
f
/4
PWM
CPU
Res
PWM resolution
16
PWM
148/164
ST72311R, ST72511R, ST72512R, ST72532R
12.11 COMMUNICATIONS INTERFACE CHARACTERISTICS
12.11.1 SPI - Serial Peripheral Interface
Subject to general operating condition for V , f
Refer to I/O port characteristics for more details on
the input/output alternate function characteristics
(SS, SCK, MOSI, MISO).
DD O-
, and T unless otherwise specified.
SC
A
Symbol
Parameter
Conditions
Min
/128
0.0625
Max
Unit
Master
Slave
f
f
f
/4
CPU
2
CPU
f
=8MHz
=8MHz
f
CPU
SCK
SPI clock frequency
MHz
1/t
/2
c(SCK)
CPU
0
f
4
CPU
t
t
r(SCK)
f(SCK)
SPI clock rise and fall time
see I/O port pin description
t
SS setup time
SS hold time
Slave
Slave
120
120
su(SS)
t
h(SS)
t
t
Master
Slave
100
90
w(SCKH)
SCK high and low time
Data input setup time
Data input hold time
w(SCKL)
t
Master
Slave
100
100
su(MI)
t
su(SI)
ns
t
Master
Slave
100
100
h(MI)
t
h(SI)
t
Data output access time
Data output disable time
Data output valid time
Data output hold time
Data output valid time
Data output hold time
Slave
Slave
0
120
240
120
a(SO)
t
dis(SO)
t
v(SO)
Slave (after enable edge)
t
0
h(SO)
v(MO)
h(MO)
t
0.25
0.25
Master (before capture edge)
t
CPU
t
Figure 88. SPI Slave Timing Diagram with CPHA=0 3)
SS
INPUT
t
t
su(SS)
c(SCK)
t
h(SS)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
t
t
w(SCKH)
w(SCKL)
t
t
t
t
dis(SO)
a(SO)
v(SO)
h(SO)
t
t
r(SCK)
f(SCK)
see
note 2
MISO
OUTPUT
INPUT
see note 2
MSB OUT
BIT6 OUT
LSB OUT
t
t
h(SI)
su(SI)
MSB IN
BIT1 IN
LSB IN
MOSI
Notes:
1. Data based on design simulation and/or characterisation results, not tested in production.
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has
its alternate function capability released. In this case, the pin status depends on the I/O port configuration.
3. Measurement points are done at CMOS levels: 0.3xV
and 0.7xV
.
DD
DD
149/164
ST72311R, ST72511R, ST72512R, ST72532R
COMMUNICATIONS INTERFACE CHARACTERISTICS (Cont’d)
Figure 89. SPI Slave Timing Diagram with CPHA=11)
SS
INPUT
t
t
su(SS)
c(SCK)
t
h(SS)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
t
t
w(SCKH)
w(SCKL)
t
t
dis(SO)
a(SO)
t
t
h(SO)
v(SO)
t
t
r(SCK)
f(SCK)
see
note 2
see
note 2
MISO
OUTPUT
HZ
MSB OUT
t
BIT6 OUT
LSB OUT
t
su(SI)
h(SI)
MSB IN
LSB IN
BIT1 IN
MOSI
INPUT
Figure 90. SPI Master Timing Diagram 1)
SS
INPUT
t
c(SCK)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
CPHA=1
CPOL=0
CPHA=1
CPOL=1
t
w(SCKH)
t
r(SCK)
t
w(SCKL)
t
f(SCK)
t
t
h(MI)
su(MI)
MISO
MOSI
INPUT
MSB IN
h(MO)
BIT6 IN
LSB IN
t
t
v(MO)
MSB OUT
LSB OUT
see note 2
BIT6 OUT
see note 2
OUTPUT
Notes:
1. Measurement points are done at CMOS levels: 0.3xV and 0.7xV
.
DD
DD
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has
its alternate function capability released. In this case, the pin status depends of the I/O port configuration.
150/164
ST72311R, ST72511R, ST72512R, ST72532R
COMMUNICATIONS INTERFACE CHARACTERISTICS (Cont’d)
12.11.2 SCI - Serial Communications Interface
Subject to general operating condition for V , f
Refer to I/O port characteristics for more details on
the input/output alternate function characteristics
(RDI and TDO).
DD O-
, and T unless otherwise specified.
SC
A
Conditions
Baud
Rate
Symbol
Parameter
Standard
Unit
Accuracy
vs. Standard
Prescaler
f
CPU
Conventional Mode
TR (or RR)=64, PR=13
TR (or RR)=16, PR=13
TR (or RR)= 8, PR=13
TR (or RR)= 4, PR=13
TR (or RR)= 2, PR=13
TR (or RR)= 8, PR= 3
TR (or RR)= 1, PR=13
300
~300.48
1200 ~1201.92
2400 ~2403.84
4800 ~4807.69
9600 ~9615.38
10400 ~10416.67
19200 ~19230.77
~0.16%
~0.79%
f
f
Tx
Rx
Communication frequency 8MHz
Hz
Extended Mode
ETPR (or ERPR) = 13
38400 ~38461.54
14400 ~14285.71
Extended Mode
ETPR (or ERPR) = 35
12.11.3 CAN - Controller Area Network Interface
Subject to general operating condition for V , f
the input/output alternate function characteristics
(CANTX and CANRX).
DD O-
, and T unless otherwise specified.
SC
A
Refer to I/O port characteristics for more details on
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
t
CAN controller propagation time
60
ns
p(RX:TX)
151/164
ST72311R, ST72511R, ST72512R, ST72532R
12.12 8-BIT ADC CHARACTERISTICS
Subject to general operating condition for V , f
, and T unless otherwise specified.
DD OSC
A
1)
Symbol
Parameter
ADC clock frequency
Conversion range voltage
External input resistor
Internal input resistor
Conditions
Min
Typ
Max
Unit
MHz
V
f
4
ADC
2)
V
V
V
AIN
SSA
DDA
3)
R
15
kΩ
kΩ
pF
AIN
R
C
1.5
ADC
ADC
Internal sample and hold capacitor
Stabilization time after ADC enable
6
4)
t
0
µs
STAB
1
4
µs
t
Sample capacitor loading time
Hold conversion time
LOAD
f
=8MHz, f
=4MHz
1/f
CPU
ADC
ADC
2.250
9
µs
t
CONV
1/f
ADC
Figure 91. Typical Application with ADC
V
DD
SAMPLING SWITCH
V
T
0.6V
R
AIN
AINx
V
AIN
V
T
0.6V
R
ADC
C
0.1µF
I
C
ADC
0.1µF
IO
L
±1µA
V
DD
1kΩ
V
DDA
0.1µF
V
SSA
ST72XXX
Notes:
1. Unless otherwise specified, typical data are based on T =25°C and V -V =5V. They are given only as design guide-
A
DD SS
lines and are not tested.
2. When V and V
pins are not available on the pinout, the ADC refer to V and V .
SS
DDA
SSA
DD
3. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10kΩ). Data
based on characterization results, not tested in production.
4. The stabilization time of the AD converter is masked by the first t
always valid.
. The first conversion after the enable is then
LOAD
152/164
ST72311R, ST72511R, ST72512R, ST72532R
ADC CHARACTERISTICS (Cont’d)
ADC Accuracy with V =5.0V
DD
Symbol
|E |
Parameter
Conditions
Min
Max
1.5
1
Unit
2)
Total unadjusted error
T
2)
E
E
Offset error
-1
O
G
2)
1)
Gain Error
f
=8MHz, f
=4MHz
-0.5
0.5
1
LSB
CPU
ADC
2)
|E |
Differential linearity error
D
2)
|E |
Integral linearity error
1
L
Figure 92. ADC Accuracy Characteristics
Digital Result ADCDR
E
G
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line
255
V
– V
254
253
DDA
SSA
1LSB
= ----------------------------------------
IDEAL
256
(2)
E =Total Unadjusted Error: maximum deviation
T
E
between the actual and the ideal transfer curves.
T
(3)
7
6
5
4
3
2
1
E =Offset Error: deviation between the first actual
O
(1)
transition and the first ideal one.
E =Gain Error: deviation between the last ideal
G
transition and the last actual one.
E
O
E
L
E =Differential Linearity Error: maximum deviation
D
between actual steps and the ideal one.
E =Integral Linearity Error: maximum deviation
L
E
between any actual transition and the end point
correlation line.
D
1 LSB
IDEAL
7
V
(LSB
)
in
IDEAL
0
1
2
3
4
5
6
253 254 255 256
V
V
DDA
SSA
Notes:
1. Data based on characterization results over the whole temperature range, monitored in production.
2. ADC Accuracy vs. Negative Injection Current:
For I =0.8mA, the typical leakage induced inside the die is 1.6µA and the effect on the ADC accuracy is a loss of 1 LSB
INJ-
for each 10KΩ increase of the external analog source impedance. This effect on the ADC accuracy has been observed
under worst-case conditions for injection:
- negative injection
- injection to an Input with analog capability, adjacent to the enabled Analog Input
- at 5V V supply, and worst case temperature.
DD
153/164
ST72311R, ST72511R, ST72512R, ST72532R
13 PACKAGE CHARACTERISTICS
13.1 PACKAGE MECHANICAL DATA
Figure 93. 64-Pin Thin Quad Flat Package
mm
inches
Dim
Min Typ Max Min Typ Max
A
1.60
0.063
0.006
A1 0.05
0.15 0.002
A2 1.35 1.40 1.45 0.053 0.055 0.057
B
C
0.30 0.37 0.45 0.012 0.015 0.018
0.09
0.20 0.004
0.008
D
16.00
14.00
12.00
16.00
14.00
12.00
0.80
0.630
0.551
0.472
0.630
0.551
0.472
0.031
D1
D3
E
E1
E3
e
K
0°
3.5°
7°
L
0.45 0.60 0.75 0.018 0.024 0.030
1.00 0.039
Number of Pins
L1
L1
L
N
64
ND
16
NE
16
K
Figure 94. 64-Pin Epoxy Thin Quad Flat Package
mm
inches
P
Dim
Min Typ Max Min Typ Max
A
A1
B
2.40
0.60
0.095
0.024
L1
L
0.25 0.38 0.50 0.010 0.015 0.020
15.80 16.00 16.20 0.622 0.630 0.638
E
n
e
E1 12.20 12.35 12.50 0.480 0.486 0.492
G
e
G
L
0.80
0.031
0.515
13.10
0.50
0.020
0.043
B
L1 1.10
n
P
0.35
1.10
0.013
0.043
A1
Number of Pins
A
N
64 (4x16)
ETQFP64
Note: “ QUALIFICATION OR VOLUME PRODUCTION OF DEVICES USING EPOXY PACKAGES
(ESO/EDIL/EQFP) IS NOT AUTHORIZED It is expressly specified that qualification and/or volume production of devices
using the package E.... in any applications is not authorized. Usage in any application is strictly restricted to development
purpose. Similar devices are available in plastic package mechanically compatible to the epoxy package for qualification
and volume production.”
154/164
ST72311R, ST72511R, ST72512R, ST72532R
13.2 THERMAL CHARACTERISTICS
Symbol
Ratings
Value
Unit
Package thermal resistance (junction to ambient)
TQFP64
R
°C/W
thJA
60
1)
P
Power dissipation
Maximum junction temperature
500
150
mW
D
2)
T
°C
Jmax
Notes:
1. The power dissipation is obtained from the formula P =P +P
where P
is the chip internal power (I xV
)
D
INT
PORT
INT
DD DD
and P
is the port power dissipation determined by the user.
PORT
2. The average chip-junction temperature can be obtained from the formula T = T + P x RthJA.
J
A
D
155/164
ST72311R, ST72511R, ST72512R, ST72532R
13.3 SOLDERING AND GLUEABILITY INFORMATION
Recommended soldering information given only as design guidelines.
Figure 95. Recommended Wave Soldering Profile (with 37% Sn and 63% Pb)
250
COOLING PHASE
(ROOM TEMPERATURE)
5 sec
200
150
100
50
SOLDERING
PHASE
80°C
Temp. [°C]
PREHEATING
PHASE
Time [sec]
0
20
40
60
80
100
140
120
160
Figure 96. Recommended Reflow Soldering Oven Profile (MID JEDEC)
250
Tmax=220+/-5°C
for 25 sec
200
150
100
50
150 sec above 183°C
90 sec at 125°C
Temp. [°C]
ramp down natural
2°C/sec max
ramp up
2°C/sec for 50sec
Time [sec]
0
100
200
300
400
Recommended glue for SMD plastic packages dedicated to molding compound with silicone:
■ Heraeus: PD945, PD955
■ Loctite: 3615, 3298
156/164
ST72311R, ST72511R, ST72512R, ST72532R
13.4 PACKAGE/SOCKET FOOTPRINT PROPOSAL
To solder the TQFP64 device directly on the appli-
cation board, or to solder a socket for connecting
the emulator probe, the application board should
provide the footprint described in Figure 97. This
footprint allows both configurations:
■ YAMAICHI IC149-064-008-S5 socket soldering
to plug either the emulator probe or an adaptor
board with an TQFP64 clamshell socket.
This socket is not compatible with TQFP64
package.
■ Direct TQFP64 soldering
Figure 97. TQFP64 Device And Emulator Probe Compatible Footprint
SK
E
mm
inches
Dim
Min Typ Max Min
Typ Max
E1
E3
B
E
0.35 0.45 0.50 0.014 0.018 0.020
20.80 0.819
E1
14.00
0.551
e
E3 11.90 12.00 12.10 0.468 0.472 0.476
e
0.75 0.80 0.85 0.029 0.031 0.033
26 1.023
Number of Pins
64 (4x16)
B
SOCKET
SK*
DETAIL
N
* SK: Plastic socket overall dimensions.
Table 27. Suggested List of TQFP64 Socket Types
Package / Probe
TQFP64
EMU PROBE
Adaptor / Socket Reference
Socket type
ENPLAS
OTQ-64-0.8-02
Open Top
YAMAICHI
YAMAICHI
IC51-0644-1240.KS-14584
Clamshell
SMC
IC149-064-008-S5
157/164
ST72311R, ST72511R, ST72512R, ST72532R
14 DEVICE CONFIGURATION AND ORDERING INFORMATION
Each device is available for production in user pro-
grammable versions (OTP) as well as in factory
coded versions (ROM). OTP devices are shipped
to customers with a default content (FFh), while
ROM factory coded parts contain the code sup-
plied by the customer. This implies that OTP de-
vices have to be configured by the customer using
the Option Bytes while the ROM devices are facto-
ry-configured.
14.1 OPTION BYTES
The option byte allows the hardware configuration
of the microcontroller to be selected.
The option byte has no address in the memory
map and can be accessed only in programming
mode (for example using a standard ST7 program-
ming tool). The default content of the OTP is fixed
to FFh. This means that all the options have “1” as
their default value.
In masked ROM devices, the option bytes are
fixed in hardware by the ROM code (see option
list).
USER OPTION BYTE
7
0
FMP
1
WDG HALT WDG SW
Default
Value
1
1
1
1
1
1
1
USER OPTION BYTE
Bit 7:6,4 = Reserved, must always be 1.
Bit 5 = Reserved, must always be 0.
Bit 3 = FMP Full memory protection
Bit 1 = WDG HALT Watchdog and HALT mode
This option bit determines if a RESET is generated
when entering HALT mode while the Watchdog is
active.
0: No Reset generation when entering Halt mode
1: Reset generation when entering Halt mode
This option bit allows the protection of the software
contents against piracy (program or data). When
the protection is activated, read-out of the EPROM
or data EEPROM contents is prevented by hard-
ware.
0: Read-out protection enabled
1: Read-out protection disabled
Bit 0 = WDG SW Hardware or software watchdog
This option bit selects the watchdog type.
0: Hardware (watchdog always enabled)
1: Software (watchdog to be enabled by software)
Bit 2 = Reserved, must always be 1
158/164
ST72311R, ST72511R, ST72512R, ST72532R
14.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE
Customer code is made up of the ROM contents
and the list of the selected options (if any). The
ROM contents are to be sent on diskette, or by
electronic means, with the S19 hexadecimal file
generated by the development tool. All unused
bytes must be set to FFh.
The selected options are communicated to
STMicroelectronics using the correctly completed
OPTION LIST appended.
The STMicroelectronics Sales Organization will be
pleased to provide detailed information on con-
tractual points.
Figure 98. ROM Factory Coded Device Types
TEMP.
PACKAGE RANGE X
/
XXX
DEVICE
Code name (defined by STMicroelectronics)
= LVD disabled
S= LVD enabled
1= standard 0 to +70 °C
6= industrial -40 to +85 °C
7= automotive -40 to +105 °C
3 = automotive -40 to +125 °C
T= TQFP
ST72311R6, ST72311R7, ST72311R9
ST72511R6, ST72511R7, ST72511R9
ST72512R4
ST72532R4
Figure 99. OTP User Programmable Device Types
TEMP.
DEVICE PACKAGE RANGE X
= LVD disabled
S= LVD enabled
1= standard 0 to +70 °C
6= industrial -40 to +85 °C
7= automotive -40 to +105 °C
3 = automotive -40 to +125 °C
T= TQFP
ST72T311R6, ST72T311R7, ST72T311R9
ST72T511R6, ST72T511R7, ST72T511R9
ST72T512R4,
ST72T532R4
159/164
ST72311R, ST72511R, ST72512R, ST72532R
TRANSFER OF CUSTOMER CODE (Cont’d)
MICROCONTROLLER OPTION LIST
Customer . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact
Phone N° . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
STMicroelectronics references
Device:
[ ] ST72311R9
[ ] ST72311R7
[ ] ST72311R6
[ ] ST72511R9
[ ] ST72511R7
[ ] ST72511R6
[ ] ST72512R4
[ ] ST72532R4
Package:
[ ] TQFP64
Temperature Range:
[ ]
0°C to + 70°C [ ] - 40°C to + 85°C
[ ] - 40°C to + 105°C [ ] - 40°C to + 125°C
Oscillator Source Selection: [ ] Quartz Crystal/Ceramic resonator
[ ] External Clock
Watchdog Selection:
[ ] Software Activation
[ ] Hardware Activation
Watchdog Reset on Halt
[ ] Disabled
[ ] Enabled
Readout Protection:
[ ] Disabled
[ ] Enabled
LVD Reset
[ ] Disabled
[ ] Enabled:
Comments :
Supply Operating Range in the application:
Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Date . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
160/164
ST72311R, ST72511R, ST72512R, ST72532R
14.3 DEVELOPMENT TOOLS
STMicroelectronics offers a range of hardware
and software development tools for the ST7 micro-
controller family. Full details of tools available for
the ST7 from third party manufacturers can be ob-
tain from the STMicroelectronics Internet site ➟
http//st7.st.com.
Third Party Tools
■ ACTUM
■ BP
■ HIWARE
■ ISYSTEM
■ KANDA
■ LEAP
■ COSMIC
■ CMX
■ DATA I/O
■ HITEX
Tools from these manufacturers include C compli-
ers, emulators and gang programmers.
STMicroelectronics Tools
Four types of development tool are offered by ST, all of which connect to a PC via a parallel (LPT) port:
1)
In-Circuit Emulation
Programming Capability
Software Included
ST7 CD ROM with:
Yes. (Same features as
ST7 Development Kit
ST7 HDS2 Emulator
HDS2 emulator but no trace/ Yes (DIP packages only)
logic analyzer)
– ST7 Assembly toolchain
– WGDB7 powerful Source Level
Debugger for Win 3.1, Win 95
and NT)
– C compiler demo versions
– ST Realizer for Win 3.1 and Win
95.
Yes, powerful emulation fea-
tures including trace/ logic an- No
alyzer
ST7 Programming
Board
No
Yes (All packages)
– Windows Programming Tools
for Win 3.1, Win 95 and NT
Note:
1. In Situ Programming (ISP) interface for FLASH devices.
Table 28. STMicroelectronics Development Tools
Supported Products
ST72311R6, ST72311R7, ST72311R9
ST72511R6, ST72511R7, ST72511R9
ST72512R4
Development Kit
HDS2 Emulator
Programming Board
ST7MDT2-EPB2/EU
ST7MDT2-EPB2/US
ST7MDT2-EPB2/UK
ST7MDT2-DVP2
ST7MDT2-EMU2B
ST72532R4
161/164
ST72311R, ST72511R, ST72512R, ST72532R
15 ST7 GENERIC APPLICATION NOTE
Identification
Description
PROGRAMMING AND TOOLS
AN912
A simple guide to development tools
Executing code in ST7 RAM
AN985
AN986
Using the ST7 indirect addressing mode
ST7 in-circuit programming
AN987
AN988
Starting with ST7 assembly tool chain
Starting with ST7 Hiware C
AN989
AN1039
AN1064
EXAMPLE DRIVERS
AN969
ST7 math utility routines
Writing optimized hiware C language for ST7
ST7 SCI communication between the ST7 and a PC
ST7 SPI communication between the ST7 and E PROM
ST7 I C communication between the ST7 and E PROM
ST7 software SPI master communication
AN970
AN971
AN972
AN973
SCI software communication with a PC using ST72251 16-bit timer
Real time clock with the ST7 timer output compare
Driving a buzzer using the ST7 PWM function
AN974
AN976
AN979
Driving an analog keyboard with the ST7 ADC
AN980
ST7 keypad decoding techniques, implementing wake-up on keystroke
Using the ST7 USB microcontroller
AN1017
AN1041
AN1042
AN1044
AN1045
AN1047
AN1048
AN1048
Using ST7 PWM signal to generate analog output (sinusoid)
ST7 routine for I C slave mode management
Multiple interrupt sources management for ST7 MCUs
ST7 software implementation of I C bus master
Managing reception errors with the ST7 SCI peripheral
ST7 software LCD driver
ST7 timer PWM duty cycle switch for true 0% or 100% duty cycle
PRODUCT OPTIMIZATION
AN982
Using ceramic resonators with the ST7
AN1014
AN1070
How to minimize the ST7 power consumption
ST7 checksum selfchecking capability
PRODUCT EVALUATION
AN910
AN990
ST7 and st9 performance benchmarking
ST7 benefits versus industry standard
APPLICATIONS EXAMPLES
AN1086
ST7 / ST10U435 CAN-Do solutions for car multiplexing
TO GET MORE INFORMATION
To get the updated information on that product please refer to STMicroelectronics web server.
➟ http://st7.st.com/
162/164
ST72311R, ST72511R, ST72512R, ST72532R
16 SUMMARY OF CHANGES
Description of the changes between the current release of the specification and the previous one.
Revision
Main changes
Date
- Section 8.4 ”LOW POWER MODES” on page 42 and Section 8.5 ”INTERRUPTS” on page
42 added in Section 8 ”I/O PORTS” on page 38.
- Section 10.2.5 ”Low Power Modes” on page 53and Section 10.2.6 ”Interrupts” on page 53
added in Section 10.2 ”MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK TIMER
(MCC/RTC)” on page 52.
2.1
Feb-00
- ESD absolute maximum rating modified in Section 12.2 on page 132.
- EMC characteristics corrected in Section 12.7 on page 140.
163/164
ST72311R, ST72511R, ST72512R, ST72532R
Notes:
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of useof such information nor for any infringement of patents or other rights of third parties which may result from its use. No license isgranted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
2000 STMicroelectronics - All Rights Reserved.
Purchase of I2C Components by STMicroelectronics conveys a license under the Philips I2C Patent. Rights to use these components in an
I2C system is granted provided that the system conforms to the I2C Standard Specification as defined by Philips.
STMicroelectronics Group of Companies
Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain
Sweden - Switzerland - United Kingdom - U.S.A.
http://www.st.com
164/164
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