ST72561AR9T3 [STMICROELECTRONICS]
IC,MICROCONTROLLER,8-BIT,ST72 CPU,CMOS,QFP,64PIN,PLASTIC;
| 型号： | ST72561AR9T3 |
| 厂家： | 
ST |
| 描述： | IC,MICROCONTROLLER,8-BIT,ST72 CPU,CMOS,QFP,64PIN,PLASTIC 微控制器 |
| 文件： | 总263页 (文件大小：5919K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ST72561
8-BIT MCU WITH FLASH OR ROM,
10-BIT ADC, 5 TIMERS, SPI, LINSCI™, ACTIVE CAN
■ Memories
– 16K to 60K High Density Flash (HDFlash) or
ROM with read-out protection capability. In-
Application Programming and In-Circuit Pro-
gramming for HDFlash devices
– 1 to 2K RAM
LQFP32
7x7mm
LQFP64
14x14mm
– HDFlash endurance: 100 cycles, data reten-
tion 40 years at 85°C
■ Clock, Reset and Supply Management
– Low power crystal/ceramic resonator oscilla-
tors and bypass for external clock
– PLL for 2x frequency multiplication
– 5 power saving modes: Halt, Auto Wake Up
LQFP44
10x10mm
LQFP64
10x10mm
From Halt, Active Halt, Wait and Slow
■ Interrupt Management
– Nested interrupt controller
– Main clock controller with real-time base and
clock output
– Window watchdog timer
– 14 interrupt vectors plus TRAP and RESET
– TLI top level interrupt (on 64-pin devices)
– Up to 21 external interrupt lines (on 4 vectors)
■ Up to 48 I/O Ports
■ Up to 4 Communications Interfaces
– SPI synchronous serial interface
– Up to 48 multifunctional bidirectional I/O lines
– Up to 36 alternate function lines
– Up to 6 high sink outputs
– Master/slave LINSCI™ asynchronous serial
interface
– Master-only LINSCI™ asynchronous serial in-
■ 5 Timers
terface
– CAN 2.0B active
■ Analog Peripheral (Low Current Coupling)
– 10-bit A/D converter with up to 16 inputs
– Up to 9 robust ports (low current coupling)
■ Instruction Set
– 16-bit timer with 2 input captures, 2 output
compares, external clock input, PWM and
pulse generator modes
– 8-bit timer with 1 or 2 input captures, 1 or 2
output compares, PWM and pulse generator
modes
– 8-bit PWM auto-reload timer with 1 or 2 input
captures, 2 or 4 independent PWM output
channels, output compare and time base in-
terrupt, external clock with event detector
– 8-bit data manipulation
– 63 basic instructions
– 17 main addressing modes
– 8 x 8 unsigned multiply instruction
■ Development Tools
– Full hardware/software development package
Device Summary
Features
ST72(F)561(AR/J/K)9
ST72561(AR/J/K)7
ST72(F)561(AR/J/K)6
Program memory - bytes
RAM (stack) - bytes
Operating Supply
CPU Frequency
60K
48K
2K (256)
32K
2K (256)
1K (256)
4.5V to 5.5V
External Resonator Osc. w/ PLLx2/8 MHz
-40°C to +125°C
Max. Temp. Range
Packages
LQFP64 10x10mm (AR), LQFP44 10x10mm (J), LQFP32 7x7mm (K)
Rev. 5
1/263
September 2006
1
Table of Contents
1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 REGISTER AND MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.3 STRUCTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.4 ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.5 ICP (IN-CIRCUIT PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.6 IAP (IN-APPLICATION PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.7 RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.8 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.1 PHASE LOCKED LOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.2 MULTI-OSCILLATOR (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.3 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.4 SYSTEM INTEGRITY MANAGEMENT (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.2 MASKING AND PROCESSING FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.3 INTERRUPTS AND LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.4 CONCURRENT & NESTED MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.5 INTERRUPT REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.6 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
8 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8.2 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8.3 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8.4 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8.5 ACTIVE HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.6 AUTO WAKE-UP FROM HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
9 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
9.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
9.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
9.4 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
9.5 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
9.6 I/O PORT REGISTER CONFIGURATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
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Table of Contents
10 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
10.1 WINDOW WATCHDOG (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
10.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK MCC/RTC . . . . . . . . . . . . . . . 60
10.3 PWM AUTO-RELOAD TIMER (ART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
10.4 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
10.5 8-BIT TIMER (TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
10.6 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
10.7 LINSCI SERIAL COMMUNICATION INTERFACE (LIN MASTER/SLAVE) . . . . . . . . . . . 123
10.8 LINSCI SERIAL COMMUNICATION INTERFACE (LIN MASTER ONLY) . . . . . . . . . . . . 154
10.9 BECAN CONTROLLER (BECAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
10.1010-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
11 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
11.1 CPU ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
11.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
12 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
12.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
12.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
12.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
12.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
12.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
12.6 AUTO WAKEUP FROM HALT OSCILLATOR (AWU) . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
12.7 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
12.8 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
12.9 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
12.10CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
12.11TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
12.12COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 243
12.1310-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
13 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
13.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
13.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
13.3 SOLDERING AND GLUEABILITY INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
14 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . 251
14.1 FLASH OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
14.2 TRANSFER OF CUSTOMER CODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
15 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
16 IMPORTANT NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
16.1 ALL DEVICES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
16.2 FLASH/FASTROM DEVICES ONLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
16.3 ROM DEVICES ONLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
17 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
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ST72561
To obtain the most recent version of this datasheet,
please check at www.st.com>products>technical literature>datasheet
Please also pay special attention to the Section “IMPORTANT NOTES” on page 257.
4/263
ST72561
1 INTRODUCTION
The ST72561 devices are members of the ST7 mi-
crocontroller family designed for mid-range appli-
cations with CAN (Controller Area Network) and
LIN (Local Interconnect Network) interface.
The enhanced instruction set and addressing
modes of the ST7 offer both power and flexibility to
software developers, enabling the design of highly
efficient and compact application code. In addition
to standard 8-bit data management, all ST7 micro-
controllers feature true bit manipulation, 8x8 un-
signed multiplication and indirect addressing
modes.
All devices are based on a common industry-
standard 8-bit core, featuring an enhanced instruc-
tion set and are available with FLASH or ROM pro-
gram memory.
Figure 1. Device Block Diagram
option
PWM
ART
OSC1
OSC2
PLL x 2
/2
OSC
8-Bit
TIMER
16-Bit
TIMER
PA7:0
(8 bits)
1
PORT A
V
POWER
SUPPLY
DD
PB7:0
V
SS
PORT B
PORT C
PORT D
1
(8 bits)
PC7:0
(8 bits)
1
RESET
PD7:0
CONTROL
1
1
(8 bits)
PE7:0
(8 bits)
TLI
PORT E
PORT F
1
8-BIT CORE
ALU
PF7:0
1
(8 bits)
PROGRAM
MEMORY
SPI
(16 - 60 Kbytes)
LINSCI2
(LIN master)
RAM
(1 - 2 Kbytes)
LINSCI1
(LIN master/slave)
WINDOW
WATCHDOG
MCC
(Clock Control)
CAN
(2.0B ACTIVE)
1
On some devices only (see Device Summary on page 1)
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3
ST72561
2 PIN DESCRIPTION
Figure 2. LQFP 64-Pin Package Pinout
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
PD2 / LINSCI1_TDO
PD1 / LINSCI1_RDI
PF2 / AIN8
OSC1
OSC2
48
ei3 47
46
1
ei3
ei3
2
ARTIC1 / PA0
PWM0 / PA1
PWM1 / (HS) PA2
PWM2 / PA3
PWM3 / PA4
3
PF1 / AIN7
45
4
PF0
44
ei0
5
PE7
43
6
PD0 / SPI_SS / AIN6
42
41
40
39
38
37
36
35
34
33
ei3
7
V _1
DD
V
8
SS_3
V _1
SS
V
9
DD_3
PC7 / SPI_SCK
PC6 / SPI_MOSI
PC5 / SPI_MISO
PE6 / AIN5
ARTCLK / (HS) PA5
ARTIC2 / (HS) PA6
T8_OCMP2 / PA7
T8_ICAP2 / PB0
T8_OCMP1 / PB1
T8_ICAP1 / PB2
MCO / PB3
10
11
12
13
14
15
16
ei0
ei1
PE5
PC4 / CAN_TX
PC3 / CAN_RX
ei1
ei2
ei1
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
(HS) 20mA high sink capability
eix associated external interrupt vector
(*) : by option bit:
T16_ICAP1 can be moved to PD4
T16_ICAP2 can be moved to PD1
T16_OCMP1 can be moved to PD3
T16_OCMP2 can be moved to PD5
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ST72561
PIN DESCRIPTION (Cont’d)
Figure 3. LQFP 44-Pin Package Pinout
44 43 42 41 40 39 38 37 36 35 34
OSC1
OSC2
PD2 / LINSCI1_TDO
PD1 / LINSCI1_RDI
PF2 / AIN8
1
33
32
31
30
ei3
ei3
2
ei3
PWM0 / PA1
3
PWM1 / (HS) PA2
PWM2 / PA3
PF1 / AIN7
4
PD0 / SPI_SS / AIN6
PC7 / SPI_SCK
PC6 / SPI_MOSI
PC5 / SPI_MISO
PE6 / AIN5
5
ei3 29
28
ei0
PWM3 / PA4
6
ARTCLK / (HS) PA5
ARTIC2 / (HS) PA6
T8_OCMP1 / PB1
T8_ICAP1 / PB2
MCO / PB3
7
27
8
26
9
25
ei1
PC4 / CAN_TX
PC3 / CAN_RX
10
11
24
ei2
ei1
23
12 13 14 15 16 17 18 19 20 21 22
(HS) 20mA high sink capability
eix associated external interrupt vector
(*) : by option bit:
T16_ICAP1 can be moved to PD4
T16_ICAP2 can be moved to PD1
T16_OCMP1 can be moved to PD3
T16_OCMP2 can be moved to PD5
7/263
ST72561
PIN DESCRIPTION (Cont’d)
Figure 4. LQFP 32-Pin Package Pinout
32 31 30 29 28 27 26 25
OSC1
OSC2
24
23
22
21
20
19
18
17
PD2 / LINSCI1_TDO
PD1 / LINSCI1_RDI
PD0 / SPI_SS / AIN6
PC7 / SPI_SCK
1
2
3
4
5
6
7
8
ei3
ei3
PWM0 / PA1
PWM1 / (HS) PA2
ARTCLK / (HS) PA5
T8_OCMP1 / PB1
T8_ICAP1 / PB2
MCO / PB3
ei0
PC6 / SPI_MOSI
PC5 / SPI_MISO
PC4 / CAN_TX
ei1
ei1
ei2
9 10 11 12 13 14 15 16
PC3 / CAN_RX
(HS) 20mA high sink capability
eix associated external interrupt vector
(*) : by option bit:
T16_ICAP1 can be moved to PD4
T16_ICAP2 can be moved to PD1
T16_OCMP1 can be moved to PD3
T16_OCMP2 can be moved to PD5
For external pin connection guidelines, refer to “ELECTRICAL CHARACTERISTICS” on page 220.
8/263
ST72561
PIN DESCRIPTION (Cont’d)
For external pin connection guidelines, refer to “ELECTRICAL CHARACTERISTICS” on page 220.
Legend / Abbreviations for Table 1:
Type:
I = input, O = output, S = supply
In/Output level: C = CMOS 0.3V /0.7V with Schmitt trigger
T
DD
DD
T = TTL 0.8V / 2V with Schmitt trigger
T
Output level:
HS = 20mA high sink (on N-buffer only)
Port and control configuration:
1)
– Input:
float = floating, wpu = weak pull-up, int = interrupt , ana = analog, RB = robust
OD = open drain, PP = push-pull
– Output:
Refer to “I/O PORTS” on page 47 for more details on the software configuration of the I/O ports.
The RESET configuration of each pin is shown in bold which is valid as long as the device is in reset state.
Table 1. Device Pin Description
Pin n°
Level
Port
Main
function
(after
Input
Output
Pin Name
Alternate function
reset)
External clock input or Resonator os-
cillator inverter input
3)
3)
1
1
1
OSC1
I
2
3
2
-
2
-
OSC2
I/O
Resonator oscillator inverter output
Port A0 ART Input Capture 1
Port A1 ART PWM Output 0
Port A2 ART PWM Output 1
Port A3 ART PWM Output 2
Port A4 ART PWM Output 3
Digital Ground Voltage
PA0 / ARTIC1
PA1 / PWM0
I/O C
I/O C
X
X
X
X
X
ei0
X
X
X
X
X
X
X
X
X
X
T
T
4
3
4
5
6
-
3
4
-
ei0
ei0
ei0
ei0
5
PA2 (HS) / PWM1
PA3 / PWM2
I/O C HS
T
6
I/O C
I/O C
S
T
T
7
-
PA4 / PWM3
8
-
V
V
SS_3
DD_3
9
-
-
S
Digital Main Supply Voltage
10
11
12
13
14
7
8
-
5
-
PA5 (HS) / ARTCLK
PA6 (HS) / ARTIC2
PA7 / T8_OCMP2
PB0 /T8_ICAP2
PB1 /T8_OCMP1
PB2 / T8_ICAP1
PB3 / MCO
I/O C HS
X
X
X
X
X
X
X
X
X
ei0
ei0
ei0
ei1
ei1
ei1
ei1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Port A5 ART External Clock
Port A6 ART Input Capture 2
Port A7 TIM8 Output Compare 2
Port B0 TIM8 Input Capture 2
Port B1 TIM8 Output Compare 1
Port B2 TIM8 Input Capture 1
T
I/O C HS
T
-
I/O C
I/O C
I/O C
I/O C
I/O C
T
T
T
T
T
T
T
-
-
9
6
7
8
-
15 10
16 11
Port B3 Main clock out (f
)
OSC2
17
18
-
-
PE0 / AIN12
I/O T
I/O T
X
RB
RB
Port E0 ADC Analog Input 12
Port E1 ADC Analog Input 13
-
PE1 / AIN13
X
ICC Clock
input
ADC Analog
Input 0
19 12
9
PB4 / AIN0 / ICCCLK
I/O C
X
ei1 RB
X
X
Port B4
T
20
21
-
-
-
-
PE2 / AIN14
PE3 / AIN15
I/O T
I/O T
X
X
X
RB
RB
X
X
X
X
Port E2 ADC Analog Input 14
Port E3 ADC Analog Input 15
T
T
X
ICC Data in- ADC Analog
Port B5
22 13 10 PB5 / AIN1 / ICCDATA I/O C
X
ei1 RB
X
X
T
put
Input 1
9/263
ST72561
Pin n°
Level
Port
Main
function
(after
Input
Output
Pin Name
Alternate function
reset)
TIM16 Out-
Port B6 put Com-
pare 1
PB6 / AIN2 /
T16_OCMP1
ADC Analog
Input 2
23 14 11
I/O C
X
X
X
RB
X
X
T
24 15
25 16
-
-
V
V
S
S
Digital Ground Voltage
SS_2
DD_2
Digital Main Supply Voltage
TIM16 Out-
Port B7 put Com-
pare 2
PB7 /AIN3 /
T16_OCMP2
ADC Analog
Input 3
26 17 12
I/O C
X
RB
RB
X
X
T
T
PC0 / AIN4 /
T16_ICAP1
TIM16 Input ADC Analog
Capture 1 Input 4
27 18 13
I/O C
X
X
X
X
X
X
X
X
X
X
X
X
X
Port C0
28 19 14 PC1 (HS) / T16_ICAP2 I/O C HS
ei2
Port C1 TIM16 Input Capture 2
Port C2 TIM16 External Clock input
Port E4
T
PC2 (HS) /
T16_EXTCLK
29 20 15
I/O C HS
ei2
T
30 21
31
-
-
PE4
NC
I/O T
X
T
-
Not Connected
Flash programming voltage. Must be
tied low in user mode.
32 22 16
V
I
PP
33 23 17 PC3 / CANRX
34 24 18 PC4 / CANTX
I/O C
I/O C
X
X
X
X
X
X
X
X
X
X
Port C3 CAN Receive Data Input
Port C4 CAN Transmit Data Output
Port E5
T
T
T
T
2)
X
35
-
-
-
PE5
I/O T
I/O T
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
36 25
PE6 / AIN5
X
X
Port E6 ADC Analog Input 5
Port C5 SPI Master In/Slave Out
Port C6 SPI Master Out/Slave In
Port C7 SPI Serial Clock
Digital Ground Voltage
37 26 19 PC5 /MISO
38 27 20 PC6 / MOSI
39 28 21 PC7 /SCK
I/O C
I/O C
I/O C
S
T
T
T
40
41
-
-
-
-
V
V
SS_1
DD_1
S
Digital Main Supply Voltage
SPI Slave
Select
ADC Analog
Input 6
42 29 22 PD0 / SS/ AIN6
I/O C
X
ei3
X
X
Port D0
T
43
44
-
-
-
-
-
-
PE7
I/O T
I/O T
I/O T
I/O T
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Port E7
Port F0
T
T
T
T
PF0
45 30
46 31
PF1 / AIN7
PF2 / AIN8
X
X
Port F1 ADC Analog Input 7
Port F2 ADC Analog Input 8
LINSCI1 Receive Data in-
47 32 23 PD1 / SCI1_RDI
48 33 24 PD2 / SCI1_TDO
I/O C
I/O C
X
X
ei3
X
X
X
X
Port D1
put
T
T
LINSCI1 Transmit Data
X
Port D2
output
49
50
51
-
-
-
-
-
-
-
PF3 / AIN9
PF4
I/O T
I/O T
X
X
X
X
X
X
X
X
X
X
X
Port F3 ADC Analog Input 9
Port F4
T
T
TLI
I
C
X
Top level interrupt input pin
Port F5
T
52 34
PF5
I/O T
X
X
X
X
X
X
T
LINSCI2 Serial Clock Out-
53 35 25 PD3 (HS) / SCI2_SCK I/O C HS
X
Port D3
put
T
10/263
ST72561
Pin n°
Level
Port
Main
function
(after
Input
Output
Pin Name
Alternate function
reset)
LINSCI2 Receive Data in-
put
54 36 26 PD4 / SCI2_RDI
I/O C
X
X
ei3
X
X
Port D4
T
55 37 27
56 38 28
57 39 29
58 40 30
V
V
V
V
S
S
I
Analog Ground Voltage
SSA
Digital Ground Voltage
SS_0
DDA
DD_0
Analog Reference Voltage for ADC
Digital Main Supply Voltage
S
LINSCI2 Transmit Data
59 41 31 PD5 / SCI2_TDO
I/O C
X
X
X
Port D5
output
T
60 42 32 RESET
I/O C
I/O C
I/O C
Top priority non maskable interrupt.
Port D6 ADC Analog Input 10
Port D7 ADC Analog Input 11
Port F6
T
T
T
T
T
61 43
62 44
-
-
-
-
PD6 / AIN10
PD7 / AIN11
PF6
X
X
X
X
ei3
ei3
X
X
X
X
X
X
X
X
X
X
63
64
-
-
I/O T
I/O T
X
X
PF7
Port F7
Notes:
1. In the interrupt input column, “eiX” defines the associated external interrupt vector. If the weak pull-up column (wpu) is
merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input, else the configuration is floating
interrupt input.
2. Input mode can be used for general purpose I/O, output mode only for CANTX.
3. OSC1 and OSC2 pins connect a crystal/ceramic resonator, or an external source to the on-chip oscillator; see Section
1 and Section 12.5 "CLOCK AND TIMING CHARACTERISTICS" for more details.
4. On the chip, each I/O port has eight pads. Pads that are not bonded to external pins are in input pull-up configuration
after reset. The configuration of these pads must be kept at reset state to avoid added current consumption.
11/263
ST72561
3 REGISTER AND MEMORY MAP
As shown in Figure 5, the MCU is capable of ad-
dressing 64 Kbytes of memories and I/O registers.
The RAM space includes up to 256 bytes for the
stack from 0100h to 01FFh.The highest address
bytes contain the user reset and interrupt vectors.
The available memory locations consist of 128
bytes of register locations, up to 2 Kbytes of RAM
and up to 60 Kbytes of user program memory.
IMPORTANT: Memory locations marked as “Re-
served” must never be accessed. Accessing a re-
seved area can have unpredictable effects on the
device.
Figure 5. Memory Map
0000h
0080h
HW Registers
(see Table 2)
Short Addressing
RAM (zero page)
007Fh
0080h
00FFh
0100h
RAM
1000h
256 bytes Stack
(2048/1024 bytes)
60 Kbytes
48 Kbytes
01FFh
0200h
087Fh
0880h
4000h
8000h
16-bit Addressing
RAM
Reserved
047Fh
0FFFh
1000h
or 087Fh
32 Kbytes
16 Kbytes
Program Memory
(60K, 48K, 32K, 16K)
C000h
FFDFh
FFDFh
FFE0h
Interrupt & Reset Vectors
(see Table 8)
FFFFh
Table 2. Hardware Register Map
Register
Reset
Status
Address
Block
Register Name
Remarks
Label
1)
2)
0000h
0001h
0002h
PADR
PADDR
PAOR
Port A Data Register
Port A Data Direction Register
Port A Option Register
00h
R/W
R/W
R/W
2)
2)
Port A
00h
00h
1)
2)
2)
2)
0003h
0004h
0005h
PBDR
PBDDR
PBOR
Port B Data Register
Port B Data Direction Register
Port B Option Register
00h
R/W
R/W
R/W
Port B
Port C
Port D
Port E
00h
00h
1)
2)
2)
2)
0006h
0007h
0008h
PCDR
PCDDR
PCOR
Port C Data Register
Port C Data Direction Register
Port C Option Register
00h
R/W
R/W
R/W
00h
00h
1)
2)
2)
2)
0009h
000Ah
000Bh
PDDR
PDDDR
PDOR
Port D Data Register
Port D Data Direction Register
Port D Option Register
00h
R/W
R/W
R/W
00h
00h
1)
2)
2)
2)
000Ch
000Dh
000Eh
PEDR
PEDDR
PEOR
Port E Data Register
Port E Data Direction Register
Port E Option Register
00h
R/W
R/W
R/W
00h
00h
12/263
ST72561
Register
Label
Reset
Status
Address
Block
Register Name
Port F Data Register
Port F Data Direction Register
Port F Option Register
Remarks
1)
2)
000Fh
0010h
0011h
PFDR
PFDDR
PFOR
00h
R/W
2)
2)
Port F
00h
00h
R/W
R/W
0012h
to
Reserved Area (15 bytes)
0020h
0021h
0022h
0023h
SPIDR
SPICR
SPICSR
SPI Data I/O Register
SPI Control Register
SPI Control/Status Register
xxh
0xh
00h
R/W
R/W
R/W
SPI
0024h
FLASH
FCSR
Flash Control/Status Register
00h
R/W
0025h
0026h
0027h
0028h
0029h
002Ah
ISPR0
ISPR1
ISPR2
ISPR3
EICR0
EICR1
Interrupt Software Priority Register 0
Interrupt Software Priority Register 1
Interrupt Software Priority Register 2
Interrupt Software Priority Register 3
External Interrupt Control Register 0
External Interrupt Control Register 1
FFh
FFh
FFh
FFh
00h
00h
R/W
R/W
R/W
R/W
R/W
R/W
ITC
002Bh
002Ch
AWUCSR
AWUPR
Auto Wake up f. Halt Control/Status Register
Auto Wake Up From Halt Prescaler
00h
FFh
R/W
R/W
AWU
002Dh
002Eh
SICSR
MCCSR
System Integrity Control / Status Register
Main Clock Control / Status Register
0xh
00h
R/W
R/W
CKCTRL
WWDG
002Fh
0030h
WDGCR
WDGWR
Watchdog Control Register
Watchdog Window Register
7Fh
7Fh
R/W
R/W
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
003Ah
003Bh
PWMDCR3 Pulse Width Modulator Duty Cycle Register 3
PWMDCR2 PWM Duty Cycle Register 2
PWMDCR1 PWM Duty Cycle Register 1
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PWMDCR0 PWM Duty Cycle Register 0
PWMCR
ARTCSR
ARTCAR
ARTARR
PWM Control register
PWM
ART
Auto-Reload Timer Control/Status Register
Auto-Reload Timer Counter Access Register
Auto-Reload Timer Auto-Reload Register
ARTICCSR ART Input Capture Control/Status Register
ARTICR1
ARTICR2
ART Input Capture Register 1
ART Input Capture register 2
Read Only
Read Only
003Ch
003Dh
003Eh
003Fh
0040h
0041h
0042h
0043h
0044h
T8CR2
T8CR1
Timer Control Register 2
Timer Control Register 1
00h
00h
00h
xxh
00h
FCh
FCh
xxh
00h
R/W
R/W
T8CSR
T8IC1R
T8OC1R
T8CTR
T8ACTR
T8IC2R
T8OC2R
Timer Control/Status Register
Timer Input Capture 1 Register
Timer Output Compare 1 Register
Timer Counter Register
Timer Alternate Counter Register
Timer Input Capture 2 Register
Timer Output Compare 2 Register
Read Only
Read Only
R/W
Read Only
Read Only
Read Only
R/W
8-BIT
TIMER
0045h
0046h
0047h
ADCCSR
ADCDRH
ADCDRL
Control/Status Register
Data High Register
Data Low Register
00h
00h
00h
R/W
Read Only
Read Only
ADC
13/263
ST72561
Register
Label
Reset
Status
Address
Block
Register Name
SCI1 Status Register
SCI1 Data Register
SCI1 Baud Rate Register
SCI1 Control Register 1
SCI1 Control Register 2
SCI1Control Register 3
SCI1 Extended Receive Prescaler Register
SCI1 Extended Transmit Prescaler Register
Remarks
0048h
0049h
004Ah
004Bh
004Ch
004Dh
004Eh
004Fh
SCI1ISR
SCI1DR
C0h
xxh
00h
xxh
00h
00h
00h
00h
Read Only
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SCI1BRR
SCI1CR1
SCI1CR2
SCI1CR3
SCI1ERPR
SCI1ETPR
LINSCI1
(LIN Master/
Slave)
0050h
Reserved Area (1 byte)
0051h
0052h
0053h
0054h
0055h
0056h
0057h
0058h
0059h
005Ah
005Bh
005Ch
005Dh
005Eh
005Fh
T16CR2
T16CR1
T16CSR
T16IC1HR
T16IC1LR
Timer Control Register 2
Timer Control Register 1
Timer Control/Status Register
Timer Input Capture 1 High Register
Timer Input Capture 1 Low Register
00h
00h
00h
xxh
xxh
80h
00h
FFh
FCh
FFh
FCh
xxh
xxh
80h
00h
R/W
R/W
R/W
Read Only
Read Only
R/W
T16OC1HR Timer Output Compare 1 High Register
T16OC1LR Timer Output Compare 1 Low Register
T16CHR
R/W
16-BIT
TIMER
Timer Counter High Register
Timer Counter Low Register
Timer Alternate Counter High Register
Timer Alternate Counter Low Register
Timer Input Capture 2 High Register
Timer Input Capture 2 Low Register
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
R/W
T16CLR
T16ACHR
T16ACLR
T16IC2HR
T16IC2LR
T16OC2HR Timer Output Compare 2 High Register
T16OC2LR Timer Output Compare 2 Low Register
R/W
0060h
0061h
0062h
0063h
0064h
0065h
0066h
0067h
SCI2SR
SCI2DR
SCI2 Status Register
SCI2 Data Register
SCI2 Baud Rate Register
SCI2 Control Register 1
SCI2 Control Register 2
SCI2 Control Register 3
SCI2 Extended Receive Prescaler Register
SCI2 Extended Transmit Prescaler Register
C0h
xxh
00h
xxh
00h
00h
00h
00h
Read Only
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SCI2BRR
SCI2CR1
SCI2CR2
SCI2CR3
SCI2ERPR
SCI2ETPR
LINSCI2
(LIN Master)
14/263
ST72561
Register
Label
Reset
Status
Address
Block
Register Name
Remarks
0068h
0069h
006Ah
006Bh
006Ch
006Dh
006Eh
006Fh
CMCR
CMSR
CTSR
CTPR
CRFR
CIER
CAN Master Control Register
CAN Master Status Register
CAN Transmit Status Register
CAN Transmit Priority Register
CAN Receive FIFO Register
CAN Interrupt Enable Register
CAN Diagnosis Register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CDGR
CPSR
CAN Page Selection Register
0070h
0071h
0072h
0073h
0074h
0075h
0076h
0077h
0078h
0079h
007Ah
007Bh
007Ch
007Dh
007Eh
007Fh
PAGE REGISTER 0
PAGE REGISTER 1
PAGE REGISTER 2
PAGE REGISTER 3
PAGE REGISTER 4
PAGE REGISTER 5
PAGE REGISTER 6
PAGE REGISTER 7
PAGE REGISTER 8
PAGE REGISTER 9
PAGE REGISTER 10
PAGE REGISTER 11
PAGE REGISTER 12
PAGE REGISTER 13
PAGE REGISTER 14
PAGE REGISTER 15
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Active CAN
PAGES
Legend: x = undefined, R/W = read/write
Notes:
1. The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values
of the I/O pins are returned instead of the DR register contents.
2. The bits associated with unavailable pins must always keep their reset value.
15/263
ST72561
4 FLASH PROGRAM MEMORY
4.1 INTRODUCTION
Depending on the overall Flash memory size in the
microcontroller device, there are up to three user
sectors (see Table 1). Each of these sectors can
be erased independently to avoid unnecessary
erasing of the whole Flash memory when only a
partial erasing is required.
The ST7 dual voltage High Density Flash
(HDFlash) is a non-volatile memory that can be
electrically erased as a single block or by individu-
al sectors and programmed on a Byte-by-Byte ba-
sis using an external V supply.
PP
The first two sectors have a fixed size of 4 Kbytes
(see Figure 1). They are mapped in the upper part
of the ST7 addressing space so the reset and in-
terrupt vectors are located in Sector 0 (F000h-
FFFFh).
The HDFlash devices can be programmed and
erased off-board (plugged in a programming tool)
or on-board using ICP (In-Circuit Programming) or
IAP (In-Application Programming).
The array matrix organisation allows each sector
to be erased and reprogrammed without affecting
other sectors.
Table 3. Sectors available in Flash devices
Flash Size (bytes)
Available Sectors
4K
8K
Sector 0
Sectors 0,1
Sectors 0,1, 2
4.2 MAIN FEATURES
■ 3 Flash programming modes:
> 8K
– Insertion in a programming tool. In this mode,
all sectors including option bytes can be pro-
grammed or erased.
4.3.1 Read-out Protection
– ICP (In-Circuit Programming). In this mode, all
sectors including option bytes can be pro-
grammed or erased without removing the de-
vice from the application board.
– IAP (In-Application Programming) In this
mode, all sectors except Sector 0, can be pro-
grammed or erased without removing the de-
vice from the application board and while the
application is running.
Read-out protection, when selected, provides a
protection against Program Memory content ex-
traction and against write access to Flash memo-
ry. Even if no protection can be considered as to-
tally unbreakable, the feature provides a very high
level of protection for a general purpose microcon-
troller.
In Flash devices, this protection is removed by re-
programming the option. In this case, the entire
program memory is first automatically erased and
the device can be reprogrammed.
■ ICT (In-Circuit Testing) for downloading and
executing user application test patterns in RAM
■ Read-out protection
■ Register Access Security System (RASS) to
Read-out protection selection depends on the de-
vice type:
prevent accidental programming or erasing
– In Flash devices it is enabled and removed
through the FMP_R bit in the option byte.
4.3 STRUCTURE
The Flash memory is organised in sectors and can
be used for both code and data storage.
– In ROM devices it is enabled by mask option
specified in the Option List.
Figure 6. Memory Map and Sector Address
4K
8K
10K
16K
24K
32K
48K
60K
FLASH
MEMORY SIZE
1000h
3FFFh
7FFFh
9FFFh
BFFFh
D7FFh
DFFFh
EFFFh
FFFFh
SECTOR 2
52 Kbytes
2 Kbytes 8 Kbytes 16 Kbytes 24 Kbytes 40 Kbytes
4 Kbytes
4 Kbytes
SECTOR 1
SECTOR 0
16/263
ST72561
FLASH PROGRAM MEMORY (Cont’d)
4.4 ICC INTERFACE
– ICCCLK: ICC output serial clock pin
– ICCDATA: ICC input/output serial data pin
ICC (In-Circuit Communication) needs a minimum
of four and up to six pins to be connected to the
programming tool (see Figure 2). These pins are:
– ICCSEL/V : programming voltage
PP
– OSC1(or OSCIN): main clock input for exter-
nal source (optional)
– RESET: device reset
– V : application board power supply (see Fig-
DD
– V : device power supply ground
ure 2, Note 3)
SS
Figure 7. Typical ICC Interface
PROGRAMMING TOOL
ICC CONNECTOR
ICC Cable
APPLICATION BOARD
ICC CONNECTOR
(See Note 3)
OPTIONAL
HE10 CONNECTOR TYPE
9
7
5
6
3
1
2
(See Note 4)
10
8
4
APPLICATION
RESET SOURCE
See Note 2
10kΩ
APPLICATION
POWER SUPPLY
C
C
L2
L1
See Note 1
APPLICATION
I/O
ST7
Notes:
1. If the ICCCLK or ICCDATA pins are only used
as outputs in the application, no signal isolation is
necessary. As soon as the Programming Tool is
plugged to the board, even if an ICC session is not
in progress, the ICCCLK and ICCDATA pins are
not available for the application. If they are used as
inputs by the application, isolation such as a serial
resistor has to implemented in case another de-
vice forces the signal. Refer to the Programming
Tool documentation for recommended resistor val-
ues.
agement IC with open drain output and pull-up
resistor > 1K, no additional components are need-
ed. In all cases the user must ensure that no exter-
nal reset is generated by the application during the
ICC session.
3. The use of Pin 7 of the ICC connector depends
on the Programming Tool architecture. This pin
must be connected when using most ST Program-
ming Tools (it is used to monitor the application
power supply). Please refer to the Programming
Tool manual.
2. During the ICC session, the programming tool
must control the RESET pin. This can lead to con-
flicts between the programming tool and the appli-
cation reset circuit if it drives more than 5mA at
high level (push pull output or pull-up resistor<1K).
A schottky diode can be used to isolate the appli-
cation RESET circuit in this case. When using a
classical RC network with R > 1K or a reset man-
4. Pin 9 has to be connected to the OSC1 or OS-
CIN pin of the ST7 when the clock is not available
in the application or if the selected clock option is
not programmed in the option byte. ST7 devices
with multi-oscillator capability need to have OSC2
grounded in this case.
17/263
ST72561
FLASH PROGRAM MEMORY (Cont’d)
4.5 ICP (IN-CIRCUIT PROGRAMMING)
4.7 RELATED DOCUMENTATION
To perform ICP the microcontroller must be
switched to ICC (In-Circuit Communication) mode
by an external controller or programming tool.
For details on Flash programming and ICC proto-
col, refer to the ST7 Flash Programming Refer-
ence Manual and to the ST7 ICC Protocol Refer-
ence Manual.
Depending on the ICP code downloaded in RAM,
Flash memory programming can be fully custom-
ized (number of bytes to program, program loca-
tions, or selection serial communication interface
for downloading).
4.8 REGISTER DESCRIPTION
FLASH CONTROL/STATUS REGISTER (FCSR)
When using an STMicroelectronics or third-party
programming tool that supports ICP and the spe-
cific microcontroller device, the user needs only to
implement the ICP hardware interface on the ap-
plication board (see Figure 2). For more details on
the pin locations, refer to the device pinout de-
scription.
Read/Write
Reset Value: 0000 0000 (00h)
7
0
0
0
0
0
0
0
0
0
4.6 IAP (IN-APPLICATION PROGRAMMING)
This register is reserved for use by Programming
Tool software. It controls the Flash programming
and erasing operations.
This mode uses a BootLoader program previously
stored in Sector 0 by the user (in ICP mode or by
plugging the device in a programming tool).
This mode is fully controlled by user software. This
allows it to be adapted to the user application, (us-
er-defined strategy for entering programming
mode, choice of communications protocol used to
fetch the data to be stored, etc.). For example, it is
possible to download code from the SPI, SCI or
other type of serial interface and program it in the
Flash. IAP mode can be used to program any of
the Flash sectors except Sector 0, which is write/
erase protected to allow recovery in case errors
occur during the programming operation.
Table 4. Flash Control/Status Register Address and Reset Value
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
FCSR
Reset Value
0024h
0
0
0
0
0
0
0
0
18/263
ST72561
5 CENTRAL PROCESSING UNIT
5.1 INTRODUCTION
5.3 CPU REGISTERS
This CPU has a full 8-bit architecture and contains
six internal registers allowing efficient 8-bit data
manipulation.
The six CPU registers shown in Figure 1 are not
present in the memory mapping and are accessed
by specific instructions.
Accumulator (A)
5.2 MAIN FEATURES
The Accumulator is an 8-bit general purpose reg-
ister used to hold operands and the results of the
arithmetic and logic calculations and to manipulate
data.
■ Enable executing 63 basic instructions
■ Fast 8-bit by 8-bit multiply
■ 17 main addressing modes (with indirect
Index Registers (X and Y)
addressing mode)
These 8-bit registers are used to create effective
addresses or as temporary storage areas for data
manipulation. (The Cross-Assembler generates a
precede instruction (PRE) to indicate that the fol-
lowing instruction refers to the Y register.)
■ Two 8-bit index registers
■ 16-bit stack pointer
■ Low power HALT and WAIT modes
■ Priority maskable hardware interrupts
■ Non-maskable software/hardware interrupts
The Y register is not affected by the interrupt auto-
matic procedures.
Program Counter (PC)
The program counter is a 16-bit register containing
the address of the next instruction to be executed
by the CPU. It is made of two 8-bit registers PCL
(Program Counter Low which is the LSB) and PCH
(Program Counter High which is the MSB).
Figure 8. CPU Registers
7
0
ACCUMULATOR
RESET VALUE = XXh
7
0
0
X INDEX REGISTER
Y INDEX REGISTER
RESET VALUE = XXh
7
RESET VALUE = XXh
PCL
PCH
7
8
15
0
PROGRAM COUNTER
RESET VALUE = RESET VECTOR @ FFFEh-FFFFh
7
1
0
1
1
I1 H I0 N Z C
CONDITION CODE REGISTER
RESET VALUE =
8
1
1
X 1 X X X
0
15
7
STACK POINTER
RESET VALUE = STACK HIGHER ADDRESS
X = Undefined Value
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ST72561
CENTRAL PROCESSING UNIT (Cont’d)
Condition Code Register (CC)
Read/Write
Bit 1 = Z Zero.
This bit is set and cleared by hardware. This bit in-
dicates that the result of the last arithmetic, logical
or data manipulation is zero.
0: The result of the last operation is different from
zero.
1: The result of the last operation is zero.
Reset Value: 111x1xxx
7
0
1
1
I1
H
I0
N
Z
C
This bit is accessed by the JREQ and JRNE test
instructions.
The 8-bit Condition Code register contains the in-
terrupt masks and four flags representative of the
result of the instruction just executed. This register
can also be handled by the PUSH and POP in-
structions.
Bit 0 = C Carry/borrow.
This bit is set and cleared by hardware and soft-
ware. It indicates an overflow or an underflow has
occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.
These bits can be individually tested and/or con-
trolled by specific instructions.
Arithmetic Management Bits
This bit is driven by the SCF and RCF instructions
and tested by the JRC and JRNC instructions. It is
also affected by the “bit test and branch”, shift and
rotate instructions.
Bit 4 = H Half carry.
This bit is set by hardware when a carry occurs be-
tween bits 3 and 4 of the ALU during an ADD or
ADC instructions. It is reset by hardware during
the same instructions.
Interrupt Management Bits
Bit 5,3 = I1, I0 Interrupt
0: No half carry has occurred.
1: A half carry has occurred.
The combination of the I1 and I0 bits gives the cur-
rent interrupt software priority.
This bit is tested using the JRH or JRNH instruc-
tion. The H bit is useful in BCD arithmetic subrou-
tines.
Interrupt Software Priority
Level 0 (main)
I1
1
0
0
1
I0
0
1
0
1
Level 1
Bit 2 = N Negative.
Level 2
This bit is set and cleared by hardware. It is repre-
sentative of the result sign of the last arithmetic,
logical or data manipulation. It’s a copy of the re-
Level 3 (= interrupt disable)
These two bits are set/cleared by hardware when
entering in interrupt. The loaded value is given by
the corresponding bits in the interrupt software pri-
ority registers (IxSPR). They can be also set/
cleared by software with the RIM, SIM, IRET,
HALT, WFI and PUSH/POP instructions.
th
sult 7 bit.
0: The result of the last operation is positive or null.
1: The result of the last operation is negative
(that is, the most significant bit is a logic 1).
This bit is accessed by the JRMI and JRPL instruc-
tions.
See the interrupt management chapter for more
details.
20/263
ST72561
CENTRAL PROCESSING UNIT (Cont’d)
Stack Pointer (SP)
Read/Write
The least significant byte of the Stack Pointer
(called S) can be directly accessed by a LD in-
struction.
Reset Value: 01 FFh
Note: When the lower limit is exceeded, the Stack
Pointer wraps around to the stack upper limit, with-
out indicating the stack overflow. The previously
stored information is then overwritten and there-
fore lost. The stack also wraps in case of an under-
flow.
15
8
1
0
7
0
0
0
0
0
0
0
The stack is used to save the return address dur-
ing a subroutine call and the CPU context during
an interrupt. The user may also directly manipulate
the stack by means of the PUSH and POP instruc-
tions. In the case of an interrupt, the PCL is stored
at the first location pointed to by the SP. Then the
other registers are stored in the next locations as
shown in Figure 2.
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
The Stack Pointer is a 16-bit register which is al-
ways pointing to the next free location in the stack.
It is then decremented after data has been pushed
onto the stack and incremented before data is
popped from the stack (see Figure 2).
– When an interrupt is received, the SP is decre-
mented and the context is pushed on the stack.
Since the stack is 256 bytes deep, the 8 most sig-
nificant bits are forced by hardware. Following an
MCU Reset, or after a Reset Stack Pointer instruc-
tion (RSP), the Stack Pointer contains its reset val-
ue (the SP7 to SP0 bits are set) which is the stack
higher address.
– On return from interrupt, the SP is incremented
and the context is popped from the stack.
A subroutine call occupies two locations and an in-
terrupt five locations in the stack area.
Figure 9. Stack Manipulation Example
CALL
Subroutine
RET
or RSP
PUSH Y
POP Y
IRET
Interrupt
Event
@ 0100h
SP
SP
SP
Y
CC
A
CC
A
CC
A
X
X
X
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
SP
SP
PCH
PCL
PCH
PCL
SP
@ 01FFh
Stack Higher Address = 01FFh
0100h
Stack Lower Address =
21/263
ST72561
6 SUPPLY, RESET AND CLOCK MANAGEMENT
The device includes a range of utility features for
securing the application in critical situations (for
example, in case of a power brown-out), and re-
ducing the number of external components. An
overview is shown in Figure 11.
6.1 PHASE LOCKED LOOP
If the clock frequency input to the PLL is in the
range 2 to 4 MHz, the PLL can be used to multiply
the frequency by two to obtain an f
of 4 to 8
OSC2
MHz. The PLL is enabled by option byte. If the PLL
is disabled, then f = f /2.
For more details, refer to dedicated parametric
section.
OSC2
OSC
Caution: The PLL is not recommended for appli-
cations where timing accuracy is required. See
“PLL Characteristics” on page 229.
Main features
■ Optional PLL for multiplying the frequency by 2
■ Reset Sequence Manager (RSM)
■ Multi-Oscillator Clock Management (MO)
Figure 10. PLL Block Diagram
PLL x 2
/ 2
0
1
– 4 Crystal/Ceramic resonator oscillators
■ System Integrity Management (SI)
f
OSC
f
OSC2
– Main supply Low voltage detection (LVD)
– Auxiliary Voltage detector (AVD) with interrupt
PLL OPTION BIT
8-BIT TIMER
capability for monitoring the main supply
Figure 11. Clock, Reset and Supply Block Diagram
/ 8000
MAIN CLOCK
CONTROLLER
WITH REALTIME
MULTI-
f
OSC2
OSC1
f
CPU
OSC
f
OSC2
PLL
(option)
OSCILLATOR
(MO)
CLOCK (MCC/RTC)
SYSTEM INTEGRITY MANAGEMENT
RESET SEQUENCE
MANAGER
WATCHDOG
TIMER (WDG)
AVD Interrupt Request
RESET
SICSR
AVD AVD
WDG
RF
LVD
RF
(RSM)
0
0
0
0
IE
F
LOW VOLTAGE
DETECTOR
(LVD)
V
V
SS
DD
AUXILIARY VOLTAGE
DETECTOR
(AVD)
22/263
ST72561
6.2 MULTI-OSCILLATOR (MO)
The main clock of the ST7 can be generated by
two different source types coming from the multi-
oscillator block:
■ an external source
■ a crystal or ceramic resonator oscillator
the frequency ranges). The resonator and the load
capacitors must be placed as close as possible to
the oscillator pins in order to minimize output dis-
tortion and start-up stabilization time. The loading
capacitance values must be adjusted according to
the selected oscillator.
Each oscillator is optimized for a given frequency
range in terms of consumption and is selectable
through the option byte. The associated hardware
configuration are shown in Table 5. Refer to the
electrical characteristics section for more details.
These oscillators are not stopped during the
RESET phase to avoid losing time in the oscillator
start-up phase.
Table 5. ST7 Clock Sources
Hardware Configuration
Caution: The OSC1 and/or OSC2 pins must not
be left unconnected. For the purposes of Failure
Mode and Effect Analysis, it should be noted that if
the OSC1 and/or OSC2 pins are left unconnected,
the ST7 main oscillator may start and, in this con-
ST7
OSC1
OSC2
figuration, could generate an f
clock frequency
OSC
in excess of the allowed maximum (> 16 MHz),
putting the ST7 in an unsafe/undefined state. The
product behavior must therefore be considered
undefined when the OSC pins are left unconnect-
ed.
EXTERNAL
SOURCE
External Clock Source
In external clock mode, a clock signal (square, si-
nus or triangle) with ~50% duty cycle has to drive
the OSC1 pin while the OSC2 pin is tied to ground.
ST7
OSC1
OSC2
Crystal/Ceramic Oscillators
This family of oscillators has the advantage of pro-
ducing a very accurate rate on the main clock of
the ST7. The selection within a list of five oscilla-
tors with different frequency ranges must be done
by option byte in order to reduce consumption (re-
fer to Section 14.1 on page 251 for more details on
C
C
L2
L1
LOAD
CAPACITORS
23/263
ST72561
6.3 RESET SEQUENCE MANAGER (RSM)
6.3.1 Introduction
The RESET vector fetch phase duration is two
clock cycles.
The reset sequence manager includes three RE-
SET sources as shown in Figure 2:
■ External RESET source pulse
Figure 12. RESET Sequence Phases
■ Internal LVD RESET (Low Voltage Detection)
■ Internal WATCHDOG RESET
RESET
These sources act on the RESET pin and it is al-
ways kept low during the delay phase.
INTERNAL RESET
256 or 4096 CLOCK CYCLES
FETCH
VECTOR
Active Phase
The RESET service routine vector is fixed at ad-
dresses FFFEh-FFFFh in the ST7 memory map.
6.3.2 Asynchronous External RESET pin
The basic RESET sequence consists of three
phases as shown in Figure 1:
■ Active Phase depending on the RESET source
■ 256 or 4096 CPU clock cycle delay (selected by
option byte)
■ RESET vector fetch
The RESET pin is both an input and an open-drain
output with integrated R
weak pull-up resistor.
ON
This pull-up has no fixed value but varies in ac-
cordance with the input voltage. It can be pulled
low by external circuitry to reset the device. See
Electrical Characteristic section for more details.
A RESET signal originating from an external
The 256 or 4096 CPU clock cycle delay allows the
oscillator to stabilize and ensures that recovery
has taken place from the Reset state. The shorter
or longer clock cycle delay should be selected by
option byte to correspond to the stabilization time
of the external oscillator used in the application.
source must have a duration of at least t
in
h(RSTL)in
order to be recognized (see Figure 3). This detec-
tion is asynchronous and therefore the MCU can
enter reset state even in HALT mode.
Figure 13. Reset Block Diagram
V
DD
R
ON
INTERNAL
RESET
Filter
RESET
PULSE
GENERATOR
WATCHDOG RESET
LVD RESET
24/263
ST72561
RESET SEQUENCE MANAGER (Cont’d)
The RESET pin is an asynchronous signal which
plays a major role in EMS performance. In a noisy
environment, it is recommended to follow the
guidelines mentioned in the electrical characteris-
tics section.
6.3.4 Internal Low Voltage Detector (LVD)
RESET
Two different RESET sequences caused by the in-
ternal LVD circuitry can be distinguished:
■ Power-On RESET
6.3.3 External Power-On RESET
■ Voltage Drop RESET
If the LVD is disabled by option byte, to start up the
microcontroller correctly, the user must ensure by
means of an external reset circuit that the reset
The device RESET pin acts as an output that is
pulled low when V < V
(rising edge) or
DD
IT+
V
< V (falling edge) as shown in Figure 3.
DD
IT-
signal is held low until V
is over the minimum
DD
The LVD filters spikes on V larger than t
to
level specified for the selected f
frequency.
DD
g(VDD)
OSC
avoid parasitic resets.
A proper reset signal for a slow rising V supply
DD
can generally be provided by an external RC net-
work connected to the RESET pin.
6.3.5 Internal Watchdog RESET
The RESET sequence generated by a internal
Watchdog counter overflow is shown in Figure 3.
Starting from the Watchdog counter underflow, the
device RESET pin acts as an output that is pulled
low during at least t
.
w(RSTL)out
Figure 14. RESET Sequences
V
DD
V
V
IT+(LVD)
IT-(LVD)
LVD
RESET
EXTERNAL
RESET
WATCHDOG
RESET
RUN
RUN
RUN
RUN
ACTIVE
PHASE
ACTIVE
PHASE
ACTIVE PHASE
t
w(RSTL)out
t
h(RSTL)in
EXTERNAL
RESET
SOURCE
RESET PIN
WATCHDOG
RESET
WATCHDOG UNDERFLOW
INTERNAL RESET (256 or 4096 TCPU
VECTOR FETCH
)
25/263
ST72561
6.4 SYSTEM INTEGRITY MANAGEMENT (SI)
The System Integrity Management block contains
the Low Voltage Detector (LVD) and Auxiliary Volt-
age Detector (AVD) functions. It is managed by
the SICSR register.
Provided the minimum V value (guaranteed for
DD
the oscillator frequency) is above V
MCU can only be in two modes:
, the
IT-(LVD)
– under full software control
– in static safe reset
6.4.1 Low Voltage Detector (LVD)
The Low Voltage Detector function (LVD) gener-
In these conditions, secure operation is always en-
sured for the application without the need for ex-
ternal reset hardware.
ates a static reset when the V supply voltage is
DD
below a V
reference value. This means that
IT-(LVD)
it secures the power-up as well as the power-down
keeping the ST7 in reset.
During a Low Voltage Detector Reset, the RESET
pin is held low, thus permitting the MCU to reset
other devices.
The V
reference value for a voltage drop is
IT-(LVD)
lower than the V
reference value for power-
IT+(LVD)
Notes:
on in order to avoid a parasitic reset when the
MCU starts running and sinks current on the sup-
ply (hysteresis).
The LVD allows the device to be used without any
external RESET circuitry.
The LVD is an optional function which can be se-
lected by option byte.
The LVD Reset circuitry generates a reset when
DD
V
is below:
It is recommended to make sure that the V sup-
DD
– V
– V
when V is rising
DD
IT+(LVD)
IT-(LVD)
ply voltage rises monotonously when the device is
exiting from Reset, to ensure the application func-
tions properly.
when V is falling
DD
The LVD function is illustrated in Figure 15.
Figure 15. Low Voltage Detector vs Reset
V
DD
V
hys
V
IT+
(LVD)
V
IT-
(LVD)
RESET
26/263
ST72561
SYSTEM INTEGRITY MANAGEMENT (Cont’d)
6.4.2 Auxiliary Voltage Detector (AVD)
down safely before the LVD resets the microcon-
troller. See Figure 16.
The Voltage Detector function (AVD) is based on
an analog comparison between a V
and
The interrupt on the rising edge is used to inform
IT-(AVD)
V
reference value and the V
main sup-
the application that the V warning state is over.
IT+(AVD)
DD
DD
ply. The V
reference value for falling volt-
IT-(AVD)
If the voltage rise time t is less than 256 or 4096
rv
age is lower than the V
reference value for
IT+(AVD)
CPU cycles (depending on the reset delay select-
ed by option byte), no AVD interrupt will be gener-
rising voltage in order to avoid parasitic detection
(hysteresis).
ated when V
is reached.
IT+(AVD)
The output of the AVD comparator is directly read-
able by the application software through a real
time status bit (AVDF) in the SICSR register. This
bit is read only.
Caution: The AVD function is active only if the
LVD is enabled through the option byte.
If t is greater than 256 or 4096 cycles then:
rv
– If the AVD interrupt is enabled before the
V
threshold is reached, then two AVD in-
IT+(AVD)
terrupts will be received: The first when the
AVDIE bit is set and the second when the thresh-
old is reached.
6.4.2.1 Monitoring the V Main Supply
DD
– If the AVD interrupt is enabled after the V
threshold is reached, then only one AVD inter-
rupt occurs.
IT+(AVD)
If the AVD interrupt is enabled, an interrupt is gen-
erated when the voltage crosses the V
IT-(AVD)
or
IT+(AVD)
V
threshold (AVDF bit toggles).
In the case of a drop in voltage, the AVD interrupt
acts as an early warning, allowing software to shut
Figure 16. Using the AVD to Monitor V
DD
V
DD
Early Warning Interrupt
(Power has dropped, MCU not
not yet in reset)
V
hyst
V
IT+(AVD)
V
IT-(AVD)
V
V
IT+(LVD)
t
VOLTAGE RISE TIME
rv
IT-(LVD)
1
1
AVDF bit
0
RESET VALUE
0
AVD INTERRUPT
REQUEST
IF AVDIE bit = 1
INTERRUPT PROCESS
INTERRUPT PROCESS
LVD RESET
27/263
ST72561
SYSTEM INTEGRITY MANAGEMENT (Cont’d)
6.4.3 Low Power Modes
Mode
Description
No effect on SI. AVD interrupts cause the
device to exit from Wait mode.
WAIT
HALT
The SICSR register is frozen.
6.4.3.1 Interrupts
The AVD interrupt event generates an interrupt if
the AVDIE bit is set and the interrupt mask in the
CC register is reset (RIM instruction).
Enable Exit
Control from
Exit
from
Halt
Event
Flag
Interrupt Event
Bit
Wait
AVD event
AVDF AVDIE
Yes
No
28/263
ST72561
SYSTEM INTEGRITY MANAGEMENT (Cont’d)
6.4.4 Register Description
SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR)
Read/Write
Reset Value: 000x 000x (00h)
Bits 3:1 = Reserved, must be kept cleared.
7
0
Bit 0 = WDGRF Watchdog reset flag
AVD
This bit indicates that the last Reset was generat-
ed by the Watchdog peripheral. It is set by hard-
ware (watchdog reset) and cleared by software
(writing zero) or an LVD Reset (to ensure a stable
cleared state of the WDGRF flag when CPU
starts).
AVD LVD
WDG
RF
0
0
0
0
F
RF
IE
Bit 7 = Reserved, must be kept cleared.
Combined with the LVDRF flag information, the
flag description is given by the following table.
Bit 6 = AVDIE Voltage Detector interrupt enable
This bit is set and cleared by software. It enables
an interrupt to be generated when the AVDF flag
changes (toggles). The pending interrupt informa-
tion is automatically cleared when software enters
the AVD interrupt routine.
RESET Sources
LVDRF WDGRF
External RESET pin
Watchdog
0
0
1
0
1
X
LVD
0: AVD interrupt disabled
1: AVD interrupt enabled
Application notes
Bit 5 = AVDF Voltage Detector flag
The LVDRF flag is not cleared when another RE-
SET type occurs (external or watchdog), the
LVDRF flag remains set to keep trace of the origi-
nal failure.
In this case, a watchdog reset can be detected by
software while an external reset can not.
This read-only bit is set and cleared by hardware.
If the AVDIE bit is set, an interrupt request is gen-
erated when the AVDF bit changes value. Refer to
Figure 16 and to Section 6.4.2.1 for additional de-
tails.
0: V over V
threshold
threshold
IT-(AVD)
DD
DD
IT+(AVD)
1: V under V
CAUTION: When the LVD is not activated with the
associated option byte, the WDGRF flag can not
be used in the application.
Bit 4 = LVDRF LVD reset flag
This bit indicates that the last Reset was generat-
ed by the LVD block. It is set by hardware (LVD re-
set) and cleared by software (writing zero). See
WDGRF flag description for more details. When
the LVD is disabled by OPTION BYTE, the LVDRF
bit value is undefined.
29/263
ST72561
7 INTERRUPTS
7.1 INTRODUCTION
each interrupt vector (see Table 1). The process-
ing flow is shown in Figure 1.
The ST7 enhanced interrupt management pro-
vides the following features:
When an interrupt request has to be serviced:
– Normal processing is suspended at the end of
the current instruction execution.
– The PC, X, A and CC registers are saved onto
the stack.
– I1 and I0 bits of CC register are set according to
the corresponding values in the ISPRx registers
of the serviced interrupt vector.
– The PC is then loaded with the interrupt vector of
the interrupt to service and the first instruction of
the interrupt service routine is fetched (refer to
“Interrupt Mapping” table for vector addresses).
■ Hardware interrupts
■ Software interrupt (TRAP)
■ Nested or concurrent interrupt management
with flexible interrupt priority and level
management:
– Up to 4 software programmable nesting levels
– Up to 16 interrupt vectors fixed by hardware
– 2 non maskable events: RESET, TRAP
– 1 maskable Top Level Event: TLI
This interrupt management is based on:
The interrupt service routine should end with the
IRET instruction which causes the contents of the
saved registers to be recovered from the stack.
– Bit 5 and bit 3 of the CPU CC register (I1:0),
– Interrupt software priority registers (ISPRx),
– Fixed interrupt vector addresses located at the
high addresses of the memory map (FFE0h to
FFFFh) sorted by hardware priority order.
This enhanced interrupt controller guarantees full
upward compatibility with the standard (not nest-
ed) ST7 interrupt controller.
Note: As a consequence of the IRET instruction,
the I1 and I0 bits will be restored from the stack
and the program in the previous level will resume.
Table 6. Interrupt Software Priority Levels
Interrupt software priority Level
I1
1
I0
0
7.2 MASKING AND PROCESSING FLOW
Level 0 (main)
Level 1
Low
1
The interrupt masking is managed by the I1 and I0
bits of the CC register and the ISPRx registers
which give the interrupt software priority level of
0
1
Level 2
0
Level 3 (= interrupt disable)
High
1
Figure 17. Interrupt Processing Flowchart
PENDING
INTERRUPT
Y
Y
RESET
TLI
N
Interrupt has the same or a
lower software priority
than current one
N
I1:0
FETCH NEXT
INSTRUCTION
THE INTERRUPT
STAYS PENDING
Y
“IRET”
N
RESTORE PC, X, A, CC
FROM STACK
EXECUTE
INSTRUCTION
STACK PC, X, A, CC
LOAD I1:0 FROM INTERRUPT SW REG.
LOAD PC FROM INTERRUPT VECTOR
30/263
ST72561
INTERRUPTS (Cont’d)
Servicing Pending Interrupts
■ TRAP (Non Maskable Software Interrupt)
As several interrupts can be pending at the same
time, the interrupt to be taken into account is deter-
mined by the following two-step process:
This software interrupt is serviced when the TRAP
instruction is executed. It will be serviced accord-
ing to the flowchart in Figure 1 as a TLI.
Caution: TRAP can be interrupted by a TLI.
– the highest software priority interrupt is serviced,
■ RESET
– if several interrupts have the same software pri-
ority then the interrupt with the highest hardware
priority is serviced first.
The RESET source has the highest priority in the
ST7. This means that the first current routine has
the highest software priority (level 3) and the high-
est hardware priority.
Figure 2 describes this decision process.
See the RESET chapter for more details.
Figure 18. Priority Decision Process
Maskable Sources
PENDING
INTERRUPTS
Maskable interrupt vector sources can be serviced
if the corresponding interrupt is enabled and if its
own interrupt software priority (in ISPRx registers)
is higher than the one currently being serviced (I1
and I0 in CC register). If any of these two condi-
tions is false, the interrupt is latched and thus re-
mains pending.
Different
Same
SOFTWARE
PRIORITY
■ TLI (Top Level Hardware Interrupt)
HIGHEST SOFTWARE
PRIORITY SERVICED
This hardware interrupt occurs when a specific
edge is detected on the dedicated TLI pin.
Caution: A TRAP instruction must not be used in a
TLI service routine.
HIGHEST HARDWARE
PRIORITY SERVICED
■ External Interrupts
External interrupts allow the processor to exit from
HALT low power mode.
External interrupt sensitivity is software selectable
through the External Interrupt Control register
(EICR).
When an interrupt request is not serviced immedi-
ately, it is latched and then processed when its
software priority combined with the hardware pri-
ority becomes the highest one.
External interrupt triggered on edge will be latched
and the interrupt request automatically cleared
upon entering the interrupt service routine.
If several input pins of a group connected to the
same interrupt line are selected simultaneously,
these will be logically ORed.
Note 1: The hardware priority is exclusive while
the software one is not. This allows the previous
process to succeed with only one interrupt.
Note 2: RESET, TRAP and TLI can be considered
as having the highest software priority in the deci-
sion process.
■ Peripheral Interrupts
Different Interrupt Vector Sources
Usually the peripheral interrupts cause the MCU to
exit from HALT mode except those mentioned in
the “Interrupt Mapping” table.
A peripheral interrupt occurs when a specific flag
is set in the peripheral status registers and if the
corresponding enable bit is set in the peripheral
control register.
Two interrupt source types are managed by the
ST7 interrupt controller: the non-maskable type
(RESET, TRAP) and the maskable type (external
or from internal peripherals).
Non-Maskable Sources
These sources are processed regardless of the
state of the I1 and I0 bits of the CC register (see
Figure 1). After stacking the PC, X, A and CC reg-
isters (except for RESET), the corresponding vec-
tor is loaded in the PC register and the I1 and I0
bits of the CC are set to disable interrupts (level 3).
These sources allow the processor to exit HALT
mode.
The general sequence for clearing an interrupt is
based on an access to the status register followed
by a read or write to an associated register.
Note: The clearing sequence resets the internal
latch. A pending interrupt (that is, waiting for being
serviced) will therefore be lost if the clear se-
quence is executed.
31/263
ST72561
INTERRUPTS (Cont’d)
7.3 INTERRUPTS AND LOW POWER MODES
7.4 CONCURRENT & NESTED MANAGEMENT
All interrupts allow the processor to exit the WAIT
low power mode. On the contrary, only external
and other specified interrupts allow the processor
to exit from the HALT modes (see column “Exit
from HALT” in “Interrupt Mapping” table). When
several pending interrupts are present while exit-
ing HALT mode, the first one serviced can only be
an interrupt with exit from HALT mode capability
and it is selected through the same decision proc-
ess shown in Figure 2.
The following Figure 3 and Figure 4 show two dif-
ferent interrupt management modes. The first is
called concurrent mode and does not allow an in-
terrupt to be interrupted, unlike the nested mode in
Figure 4. The interrupt hardware priority is given in
this order from the lowest to the highest: MAIN,
IT4, IT3, IT2, IT1, IT0, TLI. The software priority is
given for each interrupt.
Warning: A stack overflow may occur without no-
tifying the software of the failure.
Note: If an interrupt, that is not able to Exit from
HALT mode, is pending with the highest priority
when exiting HALT mode, this interrupt is serviced
after the first one serviced.
Figure 19. Concurrent Interrupt Management
SOFTWARE
PRIORITY
I1
I0
LEVEL
TLI
3
1 1
1 1
1 1
1 1
1 1
1 1
IT0
3
IT1
IT1
3
IT2
3
IT3
3
RIM
IT4
3
MAIN
MAIN
3/0
11 / 10
10
Figure 20. Nested Interrupt Management
SOFTWARE
PRIORITY
LEVEL
I1
I0
TLI
3
1 1
1 1
0 0
0 1
1 1
1 1
IT0
3
IT1
IT1
IT2
2
IT2
1
IT3
3
RIM
IT4
IT4
3
MAIN
MAIN
3/0
11 / 10
10
32/263
ST72561
INTERRUPTS (Cont’d)
7.5 INTERRUPT REGISTER DESCRIPTION
INTERRUPT SOFTWARE PRIORITY REGIS-
TERS (ISPRX)
CPU CC REGISTER INTERRUPT BITS
Read/Write
Read/Write (bit 7:4 of ISPR3 are read only)
Reset Value: 1111 1111 (FFh)
Reset Value: 111x 1010 (xAh)
7
0
7
0
ISPR0
ISPR1
I1_3 I0_3 I1_2 I0_2 I1_1 I0_1 I1_0 I0_0
I1_7 I0_7 I1_6 I0_6 I1_5 I0_5 I1_4 I0_4
1
1
I1
H
I0
N
Z
C
Bit 5, 3 = I1, I0 Software Interrupt Priority
ISPR2 I1_11 I0_11 I1_10 I0_10 I1_9 I0_9 I1_8 I0_8
These two bits indicate the current interrupt soft-
ware priority.
ISPR3
1
1
1
1
I1_13 I0_13 I1_12 I0_12
Interrupt Software Priority Level
I1
1
I0
0
1
0
1
Level 0 (main)
Level 1
Low
These four registers contain the interrupt software
priority of each interrupt vector.
0
1
Level 2
– Each interrupt vector (except RESET and TRAP)
has corresponding bits in these registers where
its own software priority is stored. This corre-
spondence is shown in the following table.
Level 3 (= interrupt disable*)
High
These two bits are set/cleared by hardware when
entering in interrupt. The loaded value is given by
the corresponding bits in the interrupt software pri-
ority registers (ISPRx).
Vector address
ISPRx bits
FFFBh-FFFAh
FFF9h-FFF8h
...
I1_0 and I0_0 bits*
I1_1 and I0_1 bits
...
They can be also set/cleared by software with the
RIM, SIM, HALT, WFI, IRET and PUSH/POP in-
structions (see “Interrupt Dedicated Instruction
Set” table).
FFE1h-FFE0h
I1_13 and I0_13 bits
*Note: TLI, TRAP and RESET events can interrupt
a level 3 program.
– Each I1_x and I0_x bit value in the ISPRx regis-
ters has the same meaning as the I1 and I0 bits
in the CC register.
– Level 0 cannot be written (I1_x = 1, I0_x = 0). In
this case, the previously stored value is kept (Ex-
ample: previous = CFh, write = 64h,
result = 44h)
The RESET, TRAP and TLI vectors have no soft-
ware priorities. When one is serviced, the I1 and I0
bits of the CC register are both set.
*Note: Bits in the ISPRx registers which corre-
spond to the TLI can be read and written but they
are not significant in the interrupt process man-
agement.
Caution: If the I1_x and I0_x bits are modified
while the interrupt x is executed the following be-
havior has to be considered: If the interrupt x is still
pending (new interrupt or flag not cleared) and the
new software priority is higher than the previous
one, the interrupt x is re-entered. Otherwise, the
software priority stays unchanged up to the next
interrupt request (after the IRET of the interrupt x).
33/263
ST72561
INTERRUPTS (Cont’d)
Table 7. Dedicated Interrupt Instruction Set
Instruction
New Description
Entering Halt mode
Function/Example
I1
H
I0
N
Z
C
HALT
IRET
JRM
1
0
Interrupt routine return
Jump if I1:0 = 11 (level 3)
Jump if I1:0 <> 11
Pop CC, A, X, PC
I1:0 = 11 ?
I1
H
I0
N
Z
C
JRNM
POP CC
RIM
I1:0 <> 11 ?
Pop CC from the Stack
Enable interrupt (level 0 set)
Disable interrupt (level 3 set)
Software trap
Mem => CC
I1
1
H
I0
0
1
1
0
N
Z
C
Load 10 in I1:0 of CC
Load 11 in I1:0 of CC
Software NMI
SIM
1
TRAP
WFI
1
Wait for interrupt
1
Note: During the execution of an interrupt routine, the HALT, POPCC, RIM, SIM and WFI instructions change the current
software priority up to the next IRET instruction or one of the previously mentioned instructions.
34/263
ST72561
INTERRUPTS (Cont’d)
Table 8. Interrupt Mapping
Exit
Source
Block
Register Priority
Address
Vector
N°
Description
from
Label
Order
1)
HALT
RESET
TRAP
Reset
yes
no
FFFEh-FFFFh
FFFCh-FFFDh
FFFAh-FFFBh
FFF8h-FFF9h
N/A
Software interrupt
0
1
TLI
External top level interrupt
Main clock controller time base interrupt
EICR
yes
yes
Highest
Priority
MCC/RTC
MCCSR
EICR/
AWUCSR
2
3
ei0/AWUFH External interrupt ei0/ Auto wake-up from Halt
FFF6h-FFF7h
FFF4h-FFF5h
EICR/
SICSR
2)
ei1/AVD
External interrupt ei1/Auxiliary Voltage Detector
yes
4
5
ei2
ei3
External interrupt ei2
EICR
EICR
FFF2h-FFF3h
FFF0h-FFF1h
FFEEh-FFEFh
FFECh-FFEDh
FFEAh-FFEBh
FFE8h-FFE9h
FFE6h-FFE7h
FFE4h-FFE5h
External interrupt ei3
6
CAN
CAN peripheral interrupt - RX
CAN peripheral interrupt - TX / ER / SC
SPI peripheral interrupts
CIER
no
3)
7
CAN
CIER
yes
8
SPI
SPICSR
T8_TCR1
TCR1
yes
no
9
TIMER8
TIMER16
LINSCI2
8-bit TIMER peripheral interrupts
16-bit TIMER peripheral interrupts
LINSCI2 Peripheral interrupts
10
11
no
SCI2CR1
no
LINSCI1 Peripheral interrupts (LIN Master/
Slave)
4)
12
LINSCI1
SCI1CR1
PWMCR
no
FFE2h-FFE3h
FFE0h-FFE1h
Lowest
Priority
13
PWM ART 8-bit PWM ART interrupts
yes
Notes:
1. Valid for HALT and ACTIVE HALT modes except for the MCC/RTC interrupt source which exits from ACTIVE HALT
mode only.
2. Except AVD interrupt
3. Exit from Halt only when a wake-up condition is detected, generating a Status Change interrupt. See Section 10.8.6
on page 161.
4. It is possible to exit from Halt using the external interrupt which is mapped on the RDI pin.
35/263
ST72561
INTERRUPTS (Cont’d)
7.6 EXTERNAL INTERRUPTS
■ Falling and rising edge
■ Falling edge and low level
7.6.1 I/O Port Interrupt Sensitivity
To guarantee correct functionality, the sensitivity
bits in the EICR register can be modified only
when the I1 and I0 bits of the CC register are both
set to 1 (level 3). This means that interrupts must
be disabled before changing sensitivity.
The external interrupt sensitivity is controlled by
the ISxx bits in the EICR register (Figure 21). This
control allows up to four fully independent external
interrupt source sensitivities.
Each external interrupt source can be generated
on four (or five) different events on the pin:
■ Falling edge
■ Rising edge
The pending interrupts are cleared by writing a dif-
ferent value in the ISx[1:0] of the EICR.
Figure 21. External Interrupt Control Bits
EICR
IS00 IS01
PORT A [7:0] INTERRUPTS
PAOR.0
PADDR.0
SENSITIVITY
CONTROL
PA0
PA1
PA2
PA0
ei0 INTERRUPT SOURCE
PA3
PA4
PA5
PA6
PA7
AWUFH
Oscillator
EICR
/ AWUPR
To Timer Input Capture 1
PORT B [5:0] INTERRUPTS
IS10
IS11
PBOR.0
PBDDR.0
SENSITIVITY
CONTROL
PB0
PB1
PB2
PB3
PB0
ei1 INTERRUPT SOURCE
PB4
PB5
EICR
PORT C [2:1] INTERRUPTS
IS20
IS21
PCOR.7
PCDDR.7
SENSITIVITY
CONTROL
PC1
PC2
ei2 INTERRUPT SOURCE
PC1
EICR
PORT D [7:6, 4, 1:0] INTERRUPTS
IS30
IS31
PDOR.0
PDDDR.0
SENSITIVITY
CONTROL
PD0
PD1
PD4
PD6
PD0
ei3 INTERRUPT SOURCE
PD7
36/263
ST72561
INTERRUPTS (Cont’d)
7.6.2 Register Description
These 2 bits can be written only when I1 and I0 of
the CC register are both set to 1 (level 3).
EXTERNAL INTERRUPT CONTROL
REGISTER 0 (EICR0)
Read/Write
Reset Value: 0000 0000 (00h)
Bits 1:0 = IS0[1:0] ei0 sensitivity
The interrupt sensitivity, defined using the IS0[1:0]
bits, is applied to the ei0 external interrupts:
7
0
IS01 IS00
External Interrupt Sensitivity
IS31 IS30 IS21 IS20 IS11 IS10 IS01 IS00
0
0
1
1
0
1
0
1
Falling edge & low level
Rising edge only
Bits 7:6 = IS3[1:0] ei3 sensitivity
The interrupt sensitivity, defined using the IS3[1:0]
bits, is applied to the ei3 external interrupts:
Falling edge only
Rising and falling edge
These 2 bits can be written only when I1 and I0 of
the CC register are both set to 1 (level 3).
IS31 IS30
External Interrupt Sensitivity
0
0
1
1
0
1
0
1
Falling edge & low level
Rising edge only
EXTERNAL INTERUPT CONTROL REGISTER 1
Falling edge only
(EICR1)
Read/Write
Rising and falling edge
Reset Value: 0000 0000 (00h)
These 2 bits can be written only when I1 and I0 of
the CC register are both set to 1 (level 3).
7
0
0
0
0
0
0
0
TLIS TLIE
Bits 5:4 = IS2[1:0] ei2 sensitivity
The interrupt sensitivity, defined using the IS2[1:0]
bits, is applied to the ei2 external interrupts:
BIts 7:2 = Reserved
IS21 IS20
External Interrupt Sensitivity
Bit 1 = TLIS Top Level Interrupt sensitivity
This bit configures the TLI edge sensitivity. It can
be set and cleared by software only when TLIE bit
is cleared.
0
0
1
1
0
1
0
1
Falling edge & low level
Rising edge only
Falling edge only
0: Falling edge
Rising and falling edge
1: Rising edge
These 2 bits can be written only when I1 and I0 of
the CC register are both set to 1 (level 3).
Bit 0 = TLIE Top Level Interrupt enable
This bit allows to enable or disable the TLI capabil-
ity on the dedicated pin. It is set and cleared by
software.
Bits 3:2 = IS1[1:0] ei1 sensitivity
The interrupt sensitivity, defined using the IS1[1:0]
bits, is applied to the ei1 external interrupts:
0: TLI disabled
IS11 IS10
External Interrupt Sensitivity
1: TLI enabled
0
0
1
1
0
1
0
1
Falling edge & low level
Rising edge only
Notes:
– A parasitic interrupt can be generated when
clearing the TLIE bit.
Falling edge only
– In some packages, the TLI pin is not available. In
this case, the TLIE bit must be kept low to avoid
parasitic TLI interrupts.
Rising and falling edge
37/263
ST72561
INTERRUPTS (Cont’d)
Table 9. Nested Interrupts Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
ei1
ei0
CLKM
ei3
TLI
ei2
0025h
0026h
0027h
0028h
I1_3
1
I0_3
1
I1_2
1
I0_2
1
I1_1
1
I0_1
1
ISPR0
Reset Value
1
1
CAN TX/ER/SC
CAN RX
I1_7
1
I0_7
1
I1_6
1
I0_6
1
I1_5
1
I0_5
1
I1_4
1
I0_4
1
ISPR1
Reset Value
LINSCI 2
TIMER 16
TIMER 8
SPI
I1_11
1
I0_11
1
I1_10
1
I0_10
1
I1_9
1
I0_9
1
I1_8
1
I0_8
1
ISPR2
Reset Value
ART
LINSCI 1
I1_13
1
I0_13
1
I1_12
1
I0_12
1
ISPR3
Reset Value
1
1
1
1
EICR0
Reset Value
IS31
0
IS30
0
IS21
0
IS20
0
IS11
0
IS10
0
IS01
0
IS00
0
0029h
002Ah
EICR1
Reset Value
TLIS
0
TLIE
0
0
0
0
0
0
0
38/263
ST72561
8 POWER SAVING MODES
8.1 INTRODUCTION
8.2 SLOW MODE
To give a large measure of flexibility to the applica-
tion in terms of power consumption, five main pow-
er saving modes are implemented in the ST7 (see
Figure 1.):
■ Slow
■ Wait (and Slow-Wait)
■ Active Halt
This mode has two targets:
– To reduce power consumption by decreasing the
internal clock in the device,
– To adapt the internal clock frequency (f
the available supply voltage.
) to
CPU
SLOW mode is controlled by three bits in the
MCCSR register: the SMS bit which enables or
disables Slow mode and two CPx bits which select
■ Auto Wake-up From Halt (AWUFH)
■ Halt
the internal slow frequency (f
).
CPU
In this mode, the master clock frequency (f
)
After a RESET the normal operating mode is se-
lected by default (RUN mode). This mode drives
the device (CPU and embedded peripherals) by
means of a master clock which is based on the
main oscillator frequency divided or multiplied by 2
OSC2
can be divided by 2, 4, 8 or 16. The CPU and pe-
ripherals are clocked at this lower frequency
(f
).
CPU
Note: SLOW-WAIT mode is activated by entering
WAIT mode while the device is in SLOW mode.
(f
).
OSC2
From RUN mode, the different power saving
modes may be selected by setting the relevant
register bits or by calling the specific ST7 software
instruction whose action depends on the oscillator
status.
Figure 23. SLOW Mode Clock Transitions
f
/2
f
/4
f
OSC2
OSC2
OSC2
f
CPU
Figure 22. Power Saving Mode Transitions
f
OSC2
00
01
CP1:0
SMS
High
RUN
NORMAL RUN MODE
REQUEST
NEW SLOW
FREQUENCY
REQUEST
SLOW
WAIT
SLOW WAIT
ACTIVE HALT
AUTO WAKE-UP FROM HALT
HALT
Low
POWER CONSUMPTION
39/263
ST72561
POWER SAVING MODES (Cont’d)
8.3 WAIT MODE
Figure 24. WAIT Mode Flow-chart
WAIT mode places the MCU in a low power con-
sumption mode by stopping the CPU.
This power saving mode is selected by calling the
‘WFI’ instruction.
All peripherals remain active. During WAIT mode,
the I[1:0] bits of the CC register are forced to ‘10’,
to enable all interrupts. All other registers and
memory remain unchanged. The MCU remains in
WAIT mode until an interrupt or RESET occurs,
whereupon the Program Counter branches to the
starting address of the interrupt or Reset service
routine.
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
ON
ON
OFF
10
WFI INSTRUCTION
N
RESET
Y
N
INTERRUPT
The MCU will remain in WAIT mode until a Reset
or an Interrupt occurs, causing it to wake up.
Y
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
ON
OFF
ON
10
Refer to Figure 3.
256 OR 4096 CPU CLOCK
CYCLE DELAY
OSCILLATOR
PERIPHERALS
CPU
ON
ON
ON
I[1:0] BITS
XX 1)
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Note:
1. Before servicing an interrupt, the CC register is
pushed on the stack. The I[1:0] bits of the CC reg-
ister are set to the current software priority level of
the interrupt routine and recovered when the CC
register is popped.
40/263
ST72561
POWER SAVING MODES (Cont’d)
8.4 HALT MODE
Figure 26. HALT Mode Flow-chart
The HALT mode is the lowest power consumption
mode of the MCU. It is entered by executing the
‘HALT’ instruction when the OIE bit of the Main
Clock Controller Status register (MCCSR) is
cleared (see section 10.2 on page 59 for more de-
tails on the MCCSR register) and when the
AWUEN bit in the AWUCSR register is cleared.
HALT INSTRUCTION
(MCCSR.OIE=0)
(AWUCSR.AWUEN=0)
WATCHDOG
ENABLE
0
DISABLE
WDGHALT 1)
1
The MCU can exit HALT mode on reception of ei-
ther a specific interrupt (see Table 8, “Interrupt
Mapping,” on page 34) or a RESET. When exiting
HALT mode by means of a RESET or an interrupt,
the oscillator is immediately turned on and the 256
or 4096 CPU cycle delay is used to stabilize the
oscillator. After the start up delay, the CPU
resumes operation by servicing the interrupt or by
fetching the reset vector which woke it up (see Fig-
ure 5.).
When entering HALT mode, the I[1:0] bits in the
CC register are forced to ‘10b’ to enable interrupts.
Therefore, if an interrupt is pending, the MCU
wakes up immediately.
WATCHDOG
RESET
OSCILLATOR
OFF
PERIPHERALS 2)
CPU
OFF
OFF
10
I[1:0] BITS
N
RESET
Y
N
INTERRUPT 3)
OSCILLATOR
PERIPHERALS
CPU
Y
ON
OFF
ON
In HALT mode, the main oscillator is turned off
causing all internal processing to be stopped, in-
cluding the operation of the on-chip peripherals.
All peripherals are not clocked except the ones
which get their clock supply from another clock
generator (such as an external or auxiliary oscilla-
tor).
I[1:0] BITS
XX 4)
256 OR 4096 CPU CLOCK
CYCLE DELAY
The compatibility of Watchdog operation with
HALT mode is configured by the “WDGHALT” op-
tion bit of the option byte. The HALT instruction
when executed while the Watchdog system is en-
abled, can generate a Watchdog RESET (see sec-
tion 14.1 on page 210 for more details).
OSCILLATOR
PERIPHERALS
CPU
ON
ON
ON
I[1:0] BITS
XX 4)
Figure 25. HALT Timing Overview
FETCH RESET VECTOR
OR SERVICE INTERRUPT
256 OR 4096 CPU
CYCLE DELAY
Notes:
RUN
HALT
RUN
1. WDGHALT is an option bit. See option byte sec-
tion for more details.
2. Peripheral clocked with an external clock source
can still be active.
3. Only some specific interrupts can exit the MCU
from HALT mode (such as external interrupt). Re-
fer to Table 8, “Interrupt Mapping,” on page 34 for
more details.
RESET
OR
INTERRUPT
HALT
INSTRUCTION
[MCCSR.OIE=0]
FETCH
VECTOR
4. Before servicing an interrupt, the CC register is
pushed on the stack. The I[1:0] bits of the CC reg-
ister are set to the current software priority level of
the interrupt routine and recovered when the CC
register is popped.
41/263
ST72561
POWER SAVING MODES (Cont’d)
Halt Mode Recommendations
8.5 ACTIVE HALT MODE
– Make sure that an external event is available to
wake up the microcontroller from Halt mode.
ACTIVE HALT mode is the lowest power con-
sumption mode of the MCU with a real time clock
available. It is entered by executing the ‘HALT’ in-
struction when MCC/RTC interrupt enable flag
(OIE bit in MCCSR register) is set and when the
AWUEN bit in the AWUCSR register is cleared
(See “Register Description” on page 9.)
– When using an external interrupt to wake up the
microcontroller, reinitialize the corresponding I/O
as “Input Pull-up with Interrupt” before executing
the HALT instruction. The main reason for this is
that the I/O may be wrongly configured due to ex-
ternal interference or by an unforeseen logical
condition.
MCCSR Power Saving Mode entered when HALT
OIE bit
instruction is executed
HALT mode
ACTIVE HALT mode
– For the same reason, reinitialize the level sensi-
tiveness of each external interrupt as a precau-
tionary measure.
0
1
– The opcode for the HALT instruction is 0x8E. To
avoid an unexpected HALT instruction due to a
program counter failure, it is advised to clear all
occurrences of the data value 0x8E from memo-
ry. For example, avoid defining a constant in
ROM with the value 0x8E.
The MCU can exit ACTIVE HALT mode on recep-
tion of the RTC interrupt and some specific inter-
rupts (see Table 8, “Interrupt Mapping,” on
page 34) or a RESET. When exiting ACTIVE
HALT mode by means of a RESET a 4096 or 256
CPU cycle delay occurs (depending on the option
byte). After the start up delay, the CPU resumes
operation by servicing the interrupt or by fetching
the reset vector which woke it up (see Figure 7.).
When entering ACTIVE HALT mode, the I[1:0] bits
in the CC register are are forced to ‘10b’ to enable
interrupts. Therefore, if an interrupt is pending, the
MCU wakes up immediately.
– As the HALT instruction clears the interrupt mask
in the CC register to allow interrupts, the user
may choose to clear all pending interrupt bits be-
fore executing the HALT instruction. This avoids
entering other peripheral interrupt routines after
executing the external interrupt routine corre-
sponding to the wake-up event (reset or external
interrupt).
In ACTIVE HALT mode, only the main oscillator
and its associated counter (MCC/RTC) are run-
ning to keep a wake-up time base. All other periph-
erals are not clocked except those which get their
clock supply from another clock generator (such
as external or auxiliary oscillator).
The safeguard against staying locked in ACTIVE
HALT mode is provided by the oscillator interrupt.
Note: As soon as active halt is enabled, executing
a HALT instruction while the Watchdog is active
does not generate a RESET.
This means that the device cannot spend more
than a defined delay in this power saving mode.
42/263
ST72561
POWER SAVING MODES (Cont’d)
Figure 27. ACTIVE HALT Timing Overview
Notes:
1. This delay occurs only if the MCU exits ACTIVE
HALT mode by means of a RESET.
ACTIVE
HALT
256 OR 4096 CYCLE
DELAY (AFTER RESET)
RUN
RUN
2. Peripheral clocked with an external clock
source can still be active.
RESET
OR
INTERRUPT
3. Only the RTC interrupt and some specific inter-
rupts can exit the MCU from ACTIVE HALT
mode (such as external interrupt). Refer to
Table 8, “Interrupt Mapping,” on page 34 for
more details.
HALT
INSTRUCTION
(Active Halt enabled)
FETCH
VECTOR
Figure 28. ACTIVE HALT Mode Flow-chart
4. Before servicing an interrupt, the CC register is
pushed on the stack. The I[1:0] bits in the CC
register are set to the current software priority
level of the interrupt routine and restored when
the CC register is popped.
OSCILLATOR
ON
PERIPHERALS
CPU
HALT INSTRUCTION
(MCCSR.OIE=1)
(AWUCSR.AWUEN=0)
2)
OFF
OFF
10
I[1:0] BITS
N
RESET
N
Y
INTERRUPT 3)
OSCILLATOR
PERIPHERALS
CPU
ON
OFF
ON
Y
I[1:0] BITS
XX 4)
256 OR 4096 CPU CLOCK
CYCLE DELAY
OSCILLATOR
PERIPHERALS
CPU
ON
ON
ON
I[1:0] BITS
XX 4)
FETCH RESET VECTOR
OR SERVICE INTERRUPT
43/263
ST72561
POWER SAVING MODES (Cont’d)
8.6 AUTO WAKE-UP FROM HALT MODE
and a 256 or 4096 cycle delay is used to stabilize
it. After this start-up delay, the CPU resumes oper-
ation by servicing the AWUFH interrupt. The AWU
flag and its associated interrupt are cleared by
software reading the AWUCSR register.
Auto Wake-Up From Halt (AWUFH) mode is simi-
lar to Halt mode with the addition of an internal RC
oscillator for wake-up. Compared to ACTIVE
HALT mode, AWUFH has lower power consump-
tion because the main clock is not kept running,
but there is no accurate realtime clock available.
To compensate for any frequency dispersion of
the AWU RC oscillator, it can be calibrated by
measuring the clock frequency f
and then
AWU_RC
It is entered by executing the HALT instruction
when the AWUEN bit in the AWUCSR register has
been set and the OIE bit in the MCCSR register is
cleared (see section 10.2 on page 59 for more de-
tails).
calculating the right prescaler value. Measurement
mode is enabled by setting the AWUM bit in the
AWUCSR register in Run mode. This connects
f
to the ICAP1 input of the 16-bit timer, al-
AWU_RC
AWU_RC
lowing the f
to be measured using the main
oscillator clock as a reference timebase.
Figure 29. AWUFH Mode Block Diagram
Similarities with Halt mode
The following AWUFH mode behavior is the same
as normal Halt mode:
AWU RC
oscillator
– The MCU can exit AWUFH mode by means of
any interrupt with exit from Halt capability or a re-
set (see Section 1.4 HALT MODE).
to Timer input capture
f
AWU_RC
– When entering AWUFH mode, the I[1:0] bits in
the CC register are forced to 10b to enable inter-
rupts. Therefore, if an interrupt is pending, the
MCU wakes up immediately.
AWUFH
interrupt
AWUFH
/64
prescaler
divider
(ei0 source)
/1 .. 255
– In AWUFH mode, the main oscillator is turned off
causing all internal processing to be stopped, in-
cluding the operation of the on-chip peripherals.
None of the peripherals are clocked except those
which get their clock supply from another clock
generator (such as an external or auxiliary oscil-
lator like the AWU oscillator).
As soon as HALT mode is entered, and if the
AWUEN bit has been set in the AWUCSR register,
the AWU RC oscillator provides a clock signal
(f
). Its frequency is divided by a fixed divid-
AWU_RC
– The compatibility of Watchdog operation with
AWUFH mode is configured by the WDGHALT
option bit in the option byte. Depending on this
setting, the HALT instruction when executed
while the Watchdog system is enabled, can gen-
erate a Watchdog RESET.
er and a programmable prescaler controlled by the
AWUPR register. The output of this prescaler pro-
vides the delay time. When the delay has elapsed
the AWUF flag is set by hardware and an interrupt
wakes up the MCU from Halt mode. At the same
time the main oscillator is immediately turned on
Figure 30. AWUF Halt Timing Diagram
t
AWU
RUN MODE
HALT MODE
256 or 4096 t
RUN MODE
Clear
CPU
f
CPU
f
AWU_RC
by software
AWUFH interrupt
44/263
ST72561
POWER SAVING MODES (Cont’d)
Figure 31. AWUFH Mode Flow-chart
Notes:
1. WDGHALT is an option bit. See option byte sec-
tion for more details.
2. Peripheral clocked with an external clock source
can still be active.
HALT INSTRUCTION
(MCCSR.OIE=0)
(AWUCSR.AWUEN=1)
3. Only an AWUFH interrupt and some specific in-
terrupts can exit the MCU from HALT mode (such
as external interrupt). Refer to Table 8, “Interrupt
Mapping,” on page 34 for more details.
4. Before servicing an interrupt, the CC register is
pushed on the stack. The I[1:0] bits of the CC reg-
ister are set to the current software priority level of
the interrupt routine and recovered when the CC
register is popped.
ENABLE
WATCHDOG
0
DISABLE
WDGHALT 1)
1
AWU RC OSC
MAIN OSC
ON
OFF
OFF
OFF
10
WATCHDOG
RESET
PERIPHERALS 2)
CPU
I[1:0] BITS
N
RESET
Y
N
INTERRUPT 3)
AWU RC OSC
MAIN OSC
OFF
ON
Y
PERIPHERALS
CPU
I[1:0] BITS
OFF
ON
XX 4)
256 OR 4096 CPU CLOCK
CYCLE DELAY
AWU RC OSC
MAIN OSC
PERIPHERALS
CPU
OFF
ON
ON
ON
I[1:0] BITS
XX 4)
FETCH RESET VECTOR
OR SERVICE INTERRUPT
45/263
ST72561
POWER SAVING MODES (Cont’d)
8.6.1 Register Description
0: AWUFH (Auto Wake-Up From Halt) mode disa-
bled
AWUFH CONTROL/STATUS REGISTER
(AWUCSR)
Read/Write (except bit 2 read only)
Reset Value: 0000 0000 (00h)
1: AWUFH (Auto Wake-Up From Halt) mode ena-
bled
AWUFH PRESCALER REGISTER (AWUPR)
Read/Write
Reset Value: 1111 1111 (FFh)
7
0
AWU AWU AWU
EN
7
0
0
0
0
0
0
F
M
AWU AWU AWU AWU AWU AWU AWU AWU
PR7 PR6 PR5 PR4 PR3 PR2 PR1 PR0
Bits 7:3 = Reserved.
Bits 7:0 = AWUPR[7:0] Auto Wake-Up Prescaler
These 8 bits define the AWUPR Dividing factor (as
explained below:
Bit 2 = AWUF Auto Wake-Up Flag
This bit is set by hardware when the AWU module
generates an interrupt and cleared by software on
reading AWUCSR.
AWUPR[7:0]
Dividing factor
0: No AWU interrupt occurred
1: AWU interrupt occurred
00h
01h
...
Forbidden (See note)
1
...
Bit 1 = AWUM Auto Wake-Up Measurement
This bit enables the AWU RC oscillator and con-
nects its output to the ICAP1 input of the 16-bit tim-
er. This allows the timer to be used to measure the
AWU RC oscillator dispersion and then compen-
sate this dispersion by providing the right value in
the AWUPR register.
FEh
FFh
254
255
In AWU mode, the period that the MCU stays in
Halt Mode (t
in Figure 9.) is defined by
AWU
1
t
= 64 × AWUPR × ------------------------- + t
RCSTRT
0: Measurement disabled
AWU
f
AWURC
1: Measurement enabled
This prescaler register can be programmed to
modify the time that the MCU stays in Halt mode
before waking up automatically.
Bit 0 = AWUEN Auto Wake-Up From Halt Enabled
This bit enables the Auto Wake-Up From Halt fea-
ture: once HALT mode is entered, the AWUFH
wakes up the microcontroller after a time delay de-
fined by the AWU prescaler value. It is set and
cleared by software.
Note: If 00h is written to AWUPR, depending on
the product, an interrupt is generated immediately
after a HALT instruction or the AWUPR remains
unchanged.
Table 10. AWU Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
AWUCSR
Reset Value
AWUF
0
AWUM
0
AWUEN
0
002Bh
002Ch
0
0
0
0
0
AWUPR
Reset Value
AWUPR7 AWUPR6 AWUPR5 AWUPR4 AWUPR3 AWUPR2 AWUPR1 AWUPR0
1
1
1
1
1
1
1
1
46/263
ST72561
9 I/O PORTS
9.1 INTRODUCTION
Each pin can independently generate an interrupt
request. The interrupt sensitivity is independently
programmable using the sensitivity bits in the
EICR register.
The I/O ports offer different functional modes:
– transfer of data through digital inputs and outputs
and for specific pins:
Each external interrupt vector is linked to a dedi-
cated group of I/O port pins (see pinout description
and interrupt section). If several input pins are se-
lected simultaneously as interrupt sources, these
are first detected according to the sensitivity bits in
the EICR register and then logically ORed.
– external interrupt generation
– alternate signal input/output for the on-chip pe-
ripherals.
An I/O port contains up to 8 pins. Each pin can be
programmed independently as digital input (with or
without interrupt generation) or digital output.
The external interrupts are hardware interrupts,
which means that the request latch (not accessible
directly by the application) is automatically cleared
when the corresponding interrupt vector is
fetched. To clear an unwanted pending interrupt
by software, the sensitivity bits in the EICR register
must be modified.
9.2 FUNCTIONAL DESCRIPTION
Each port has two main registers:
– Data Register (DR)
– Data Direction Register (DDR)
and one optional register:
– Option Register (OR)
9.2.2 Output Modes
The output configuration is selected by setting the
corresponding DDR register bit. In this case, writ-
ing the DR register applies this digital value to the
I/O pin through the latch. Then reading the DR reg-
ister returns the previously stored value.
Each I/O pin may be programmed using the corre-
sponding register bits in the DDR and OR regis-
ters: Bit X corresponding to pin X of the port. The
same correspondence is used for the DR register.
Two different output modes can be selected by
software through the OR register: Output push-pull
and open-drain.
The following description takes into account the
OR register, (for specific ports which do not pro-
vide this register refer to the I/O Port Implementa-
tion section). The generic I/O block diagram is
shown in Figure 1
DR register value and output pin status:
DR
0
Push-pull
Open-drain
Vss
V
9.2.1 Input Modes
SS
1
V
Floating
DD
The input configuration is selected by clearing the
corresponding DDR register bit.
9.2.3 Alternate Functions
In this case, reading the DR register returns the
digital value applied to the external I/O pin.
When an on-chip peripheral is configured to use a
pin, the alternate function is automatically select-
ed. This alternate function takes priority over the
standard I/O programming.
Different input modes can be selected by software
through the OR register.
Notes:
When the signal is coming from an on-chip periph-
eral, the I/O pin is automatically configured in out-
put mode (push-pull or open drain according to the
peripheral).
1. Writing the DR register modifies the latch value
but does not affect the pin status.
2. When switching from input to output mode, the
DR register has to be written first to drive the cor-
rect level on the pin as soon as the port is config-
ured as an output.
When the signal is going to an on-chip peripheral,
the I/O pin must be configured in input mode. In
this case, the pin state is also digitally readable by
addressing the DR register.
3. Do not use read/modify/write instructions (BSET
or BRES) to modify the DR register as this might
corrupt the DR content for I/Os configured as input.
Note: Input pull-up configuration can cause unex-
pected value at the input of the alternate peripheral
input. When an on-chip peripheral use a pin as in-
put and output, this pin has to be configured in in-
put floating mode.
External interrupt function
When an I/O is configured as Input with Interrupt,
an event on this I/O can generate an external inter-
rupt request to the CPU.
47/263
ST72561
I/O PORTS (Cont’d)
Figure 32. I/O Port General Block Diagram
ALTERNATE
OUTPUT
1
0
REGISTER
ACCESS
P-BUFFER
(see table below)
V
DD
ALTERNATE
ENABLE
PULL-UP
(see table below)
DR
DDR
OR
V
DD
PULL-UP
CONDITION
PAD
If implemented
OR SEL
DDR SEL
DR SEL
N-BUFFER
DIODES
(see table below)
ANALOG
INPUT
CMOS
SCHMITT
TRIGGER
1
0
ALTERNATE
INPUT
EXTERNAL
INTERRUPT
SOURCE (ei )
x
Table 11. I/O Port Mode Options
Configuration Mode
Diodes
Pull-Up
P-Buffer
to V
to V
SS
DD
Floating with/without Interrupt
Input
Off
On
Off
Pull-up with/without Interrupt
On
Push-pull
On
Off
NI
On
Off
NI
Output
Open Drain (logic level)
True Open Drain
NI (see note)
Legend: NI - not implemented
Note: The diode to V is not implemented in the
DD
Off - implemented not activated
On - implemented and activated
true open drain pads. A local protection between
the pad and V is implemented to protect the de-
SS
vice against positive stress.
48/263
ST72561
I/O PORTS (Cont’d)
Table 12. I/O Port Configurations
Hardware Configuration
DR REGISTER ACCESS
NOT IMPLEMENTED IN
TRUE OPEN DRAIN
I/O PORTS
V
DD
PULL-UP
CONDITION
R
W
R
PU
DR
REGISTER
DATA BUS
PAD
ALTERNATE INPUT
EXTERNAL INTERRUPT
SOURCE (ei )
x
INTERRUPT
CONDITION
ANALOG INPUT
NOT IMPLEMENTED IN
TRUE OPEN DRAIN
I/O PORTS
DR REGISTER ACCESS
V
DD
R
PU
R/W
DR
REGISTER
DATA BUS
PAD
ALTERNATE
ENABLE
ALTERNATE
OUTPUT
NOT IMPLEMENTED IN
TRUE OPEN DRAIN
I/O PORTS
DR REGISTER ACCESS
V
DD
R
PU
R/W
DR
REGISTER
DATA BUS
PAD
ALTERNATE
ENABLE
ALTERNATE
OUTPUT
Notes:
1. When the I/O port is in input configuration and the associated alternate function is enabled as an output,
reading the DR register will read the alternate function output status.
2. When the I/O port is in output configuration and the associated alternate function is enabled as an input,
the alternate function reads the pin status given by the DR register content.
49/263
ST72561
I/O PORTS (Cont’d)
CAUTION: The alternate function must not be ac-
tivated as long as the pin is configured as input
with interrupt, in order to avoid generating spurious
interrupts.
Figure 33. Interrupt I/O Port State Transitions
01
00
10
11
Analog alternate function
INPUT
floating/pull-up
interrupt
INPUT
floating
(reset state)
OUTPUT
open-drain
OUTPUT
push-pull
When the pin is used as an ADC input, the I/O
must be configured as floating input. The analog
multiplexer (controlled by the ADC registers)
switches the analog voltage present on the select-
ed pin to the common analog rail which is connect-
ed to the ADC input.
= DDR, OR
XX
9.4 LOW POWER MODES
It is recommended not to change the voltage level
or loading on any port pin while conversion is in
progress. Furthermore it is recommended not to
have clocking pins located close to a selected an-
alog pin.
Mode
WAIT
HALT
Description
No effect on I/O ports. External interrupts
cause the device to exit from WAIT mode.
No effect on I/O ports. External interrupts
cause the device to exit from HALT mode.
WARNING: The analog input voltage level must
be within the limits stated in the absolute maxi-
mum ratings.
9.5 INTERRUPTS
9.3 I/O PORT IMPLEMENTATION
The external interrupt event generates an interrupt
if the corresponding configuration is selected with
DDR and OR registers and the interrupt mask in
the CC register is not active (RIM instruction).
The hardware implementation on each I/O port de-
pends on the settings in the DDR and OR registers
and specific feature of the I/O port such as ADC In-
put or true open drain.
Enable Exit
Control from
Exit
from
Halt
Event
Flag
Interrupt Event
Switching these I/O ports from one state to anoth-
er should be done in a sequence that prevents un-
wanted side effects. Recommended safe transi-
tions are illustrated in Figure 2 on page 4. Other
transitions are potentially risky and should be
avoided, since they are likely to present unwanted
side-effects such as spurious interrupt generation.
Bit
Wait
External interrupt on
selected external
event
DDRx
ORx
-
Yes
50/263
ST72561
I/O PORTS (Cont’d)
9.6 I/O PORT REGISTER CONFIGURATIONS
PA1,3,5,7; PB1,3,5; PC2; PD1,4,7
The I/O port register configurations are summa-
rized as follows.
(without pull-up)
MODE
floating input
DDR
OR
0
0
0
1
1
9.6.1 Standard Ports
floating interrupt input
open drain output
push-pull output
1
PB7:6, PC0, PC3, PC7:5, PD3:2, PD5, PE7:0,
PF7:0
0
1
MODE
DDR
OR
0
floating input
pull-up input
0
0
1
1
1
open drain output
push-pull output
0
9.6.3 Pull-up Input Port (CANTX requirement)
PC4
1
MODE
pull-up input
9.6.2 Interrupt Ports
PA0,2,4,6; PB0,2,4; PC1; PD0,6
(with pull-up)
The PC4 port cannot operate as a general pur-
pose output. The CAN peripheral controls it direct-
ly when enabled. Otherwise, PC4 is a pull-up in-
put.
MODE
floating input
DDR
OR
0
0
0
1
1
If DDR = 1 it is still possible to read the port
through the DR register.
pull-up interrupt input
open drain output
push-pull output
1
0
1
51/263
ST72561
I/O PORTS (Cont’d)
Table 13. Port Configuration
Input
Output
Port
Pin name
PA0
OR = 0
OR = 1
OR = 0
OR = 1
pull-up interrupt (ei0)
floating interrupt (ei0)
pull-up interrupt (ei0)
floating interrupt (ei0)
pull-up interrupt (ei0)
floating interrupt (ei0)
pull-up interrupt (ei0)
floating interrupt (ei0)
pull-up interrupt (ei1)
floating interrupt (ei1)
pull-up interrupt (ei1)
floating interrupt (ei1)
pull-up interrupt (ei1)
floating interrupt (ei1)
pull-up
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB3
PB4
PB5
PC0
PC1
PC2
PC3
PC4
PC7:5
PD0
PD1
PD3:2
PD4
PD5
PD6
PD7
PE7:0
PF7:0
Port A
floating
open drain
push-pull
Port B
Port C
floating
open drain
open drain
push-pull
push-pull
pull-up interrupt (ei2)
floating interrupt (ei2)
pull-up
floating
floating
pull-up
controlled by CANTX *
pull-up
open drain
push-pull
pull-up interrupt (ei3)
floating interrupt (ei3)
pull-up
Port D
floating
floating interrupt (ei3)
pull-up
open drain
push-pull
pull-up interrupt (ei3)
floating interrupt (ei3)
pull-up (TTL)
Port E
Port F
floating (TTL)
floating (TTL)
open drain
open drain
push-pull
push-pull
pull-up (TTL)
* Note: When the CANTX alternate function is selected, the I/O port operates in output push-pull mode.
52/263
ST72561
I/O PORTS (Cont’d)
Table 14. I/O Port Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
Reset Value
of all IO port registers
0
0
0
0
0
0
0
0
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
0010h
0011h
PADR
PADDR
PAOR
PBDR
PBDDR
PBOR
PCDR
PCDDR
PCOR
PDDR
PDDDR
PDOR
PEDR
MSB
MSB
MSB
MSB
MSB
MSB
LSB
LSB
LSB
LSB
LSB
LSB
PEDDR
PEOR
PFDR
PFDDR
PFOR
53/263
ST72561
10 ON-CHIP PERIPHERALS
10.1 WINDOW WATCHDOG (WWDG)
10.1.1 Introduction
counter is reloaded outside the window (see
Figure 4)
The Window Watchdog is used to detect the oc-
currence of a software fault, usually generated by
external interference or by unforeseen logical con-
ditions, which causes the application program to
abandon its normal sequence. The Watchdog cir-
cuit generates an MCU reset on expiry of a pro-
grammed time period, unless the program refresh-
es the contents of the downcounter before the T6
bit becomes cleared. An MCU reset is also gener-
ated if the 7-bit downcounter value (in the control
register) is refreshed before the downcounter has
reached the window register value. This implies
that the counter must be refreshed in a limited win-
dow.
■ Hardware/Software
Watchdog
activation
(selectable by option byte)
■ Optional
reset
on
HALT
instruction
(configurable by option byte)
10.1.3 Functional Description
The counter value stored in the WDGCR register
(bits T[6:0]), is decremented every 16384 f
cycles (approx.), and the length of the timeout pe-
riod can be programmed by the user in 64 incre-
ments.
OSC2
If the watchdog is activated (the WDGA bit is set)
and when the 7-bit downcounter (T[6:0] bits) rolls
over from 40h to 3Fh (T6 becomes cleared), it ini-
tiates a reset cycle pulling low the reset pin for typ-
ically 30µs. If the software reloads the counter
while the counter is greater than the value stored
in the window register, then a reset is generated.
10.1.2 Main Features
■ Programmable free-running downcounter
■ Conditional reset
– Reset (if watchdog activated) when the down-
counter value becomes less than 40h
– Reset (if watchdog activated) if the down-
Figure 34. Watchdog Block Diagram
RESET
WATCHDOG WINDOW REGISTER (WDGWR)
-
W5
W0
W6
W1
W4
W2
W3
comparator
= 1 when
T6:0 > W6:0
CMP
Write WDGCR
WATCHDOG CONTROL REGISTER (WDGCR)
T5
T0
WDGA T6
T1
T4
T2
T3
6-BIT DOWNCOUNTER (CNT)
MCC/RTC
f
OSC2
DIV 64
WDG PRESCALER
DIV 4
12-BIT MCC
RTC COUNTER
TB[1:0] bits
(MCCSR
Register)
MSB
LSB
0
6 5
11
54/263
ST72561
WINDOW WATCHDOG (Cont’d)
The application program must write in the
WDGCR register at regular intervals during normal
operation to prevent an MCU reset. This operation
must occur only when the counter value is lower
than the window register value. The value to be
stored in the WDGCR register must be between
FFh and C0h (see Figure 2):
between a minimum and a maximum value due
to the unknown status of the prescaler when writ-
ing to the WDGCR register (see Figure 3).
The window register (WDGWR) contains the
high limit of the window: To prevent a reset, the
downcounter must be reloaded when its value is
lower than the window register value and greater
than 3Fh. Figure 4 describes the window watch-
dog process.
– Enabling the watchdog:
When Software Watchdog is selected (by option
byte), the watchdog is disabled after a reset. It is
enabled by setting the WDGA bit in the WDGCR
register, then it cannot be disabled again except
by a reset.
Note: The T6 bit can be used to generate a soft-
ware reset (the WDGA bit is set and the T6 bit is
cleared).
– Watchdog Reset on Halt option
When Hardware Watchdog is selected (by option
byte), the watchdog is always active and the
WDGA bit is not used.
If the watchdog is activated and the watchdog re-
set on halt option is selected, then the HALT in-
struction will generate a Reset.
– Controlling the downcounter:
10.1.4 Using Halt Mode with the WDG
This downcounter is free-running: It counts down
even if the watchdog is disabled. When the
watchdog is enabled, the T6 bit must be set to
prevent generating an immediate reset.
If Halt mode with Watchdog is enabled by option
byte (no watchdog reset on HALT instruction), it is
recommended before executing the HALT instruc-
tion to refresh the WDG counter, to avoid an unex-
pected WDG reset immediately after waking up
the microcontroller.
The T[5:0] bits contain the number of increments
which represents the time delay before the
watchdog produces a reset (see Figure 2. Ap-
proximate Timeout Duration). The timing varies
55/263
ST72561
WINDOW WATCHDOG (Cont’d)
10.1.5 How to Program the Watchdog Timeout
more precision is needed, use the formulae in Fig-
ure 3.
Figure 2 shows the linear relationship between the
6-bit value to be loaded in the Watchdog Counter
(CNT) and the resulting timeout duration in milli-
seconds. This can be used for a quick calculation
without taking the timing variations into account. If
Caution: When writing to the WDGCR register, al-
ways write 1 in the T6 bit to avoid generating an
immediate reset.
Figure 35. Approximate Timeout Duration
3F
38
30
28
20
18
10
08
00
1.5
18
34
50
65
82
98
114
128
Watchdog timeout (ms) @ 8 MHz f
OSC2
56/263
ST72561
WINDOW WATCHDOG (Cont’d)
Figure 36. Exact Timeout Duration (t
and t
)
max
min
WHERE:
t
t
t
= (LSB + 128) x 64 x t
min0
OSC2
= 16384 x t
= 125ns if f
max0
OSC2
OSC2
= 8 MHz
OSC2
CNT = Value of T[5:0] bits in the WDGCR register (6 bits)
MSB and LSB are values from the table below depending on the timebase selected by the TB[1:0] bits
in the MCCSR register
TB1 Bit
TB0 Bit
Selected MCCSR
Timebase
MSB
LSB
(MCCSR Reg.) (MCCSR Reg.)
0
0
1
1
0
1
0
1
2ms
4ms
4
8
59
53
35
54
10ms
25ms
20
49
To calculate the minimum Watchdog Timeout (t ):
min
MSB
4
IF
THEN
ELSE
-------------
CNT <
t
= tmin0 + 16384 × CNT × t
min
osc2
4CNT
----------------
4CNT
----------------
⎛
⎞
⎠
t
= t
+ 16384 × CNT –
+ (192 + LSB) × 64 ×
× t
osc2
min
min0
⎝
MSB
MSB
To calculate the maximum Watchdog Timeout (t
):
max
MSB
4
IF
-------------
THEN
ELSE
CNT ≤
t
= tmax0 + 16384 × CNT × t
osc2
max
4CNT
----------------
4CNT
----------------
⎛
⎞
t
= t
+ 16384 × CNT –
+ (192 + LSB) × 64 ×
× t
osc2
max
max0
⎝
⎠
MSB
MSB
Note: In the above formulae, division results must be rounded down to the next integer value.
Example:
With 2ms timeout selected in MCCSR register
Min. Watchdog
Timeout (ms)
Max. Watchdog
Timeout (ms)
Value of T[5:0] Bits in
WDGCR Register (Hex.)
t
t
min
max
00
3F
1.496
128
2.048
128.552
57/263
ST72561
WINDOW WATCHDOG (Cont’d)
Figure 37. Window Watchdog Timing Diagram
T[5:0] CNT downcounter
WDGWR
3Fh
time
(step = 16384/fOSC2
)
Refresh not allowed Refresh Window
T6 bit
Reset
10.1.6 Low Power Modes
Mode Description
SLOW No effect on Watchdog: The downcounter continues to decrement at normal speed.
WAIT No effect on Watchdog: The downcounter continues to decrement.
OIE bit in
MCCSR
register
WDGHALT bit
in Option
Byte
No Watchdog reset is generated. The MCU enters Halt mode. The Watch-
dog counter is decremented once and then stops counting and is no longer
able to generate a watchdog reset until the MCU receives an external inter-
rupt or a reset.
HALT
0
0
If an interrupt is received (refer to interrupt table mapping to see interrupts
which can occur in halt mode), the Watchdog restarts counting after 256 or
4096 CPU clocks. If a reset is generated, the Watchdog is disabled (reset
state) unless Hardware Watchdog is selected by option byte. For applica-
tion recommendations see Section 0.1.8 below.
0
1
1
x
A reset is generated instead of entering halt mode.
No reset is generated. The MCU enters Active Halt mode. The Watchdog
counter is not decremented. It stop counting. When the MCU receives an
oscillator interrupt or external interrupt, the Watchdog restarts counting im-
mediately. When the MCU receives a reset the Watchdog restarts counting
after 256 or 4096 CPU clocks.
ACTIVE
HALT
10.1.7 Hardware Watchdog Option
10.1.8 Using Halt Mode with the WDG
(WDGHALT option)
If Hardware Watchdog is selected by option byte,
the watchdog is always active and the WDGA bit in
the WDGCR is not used. Refer to the Option Byte
description.
The following recommendation applies if Halt
mode is used when the watchdog is enabled.
– Before executing the HALT instruction, refresh
the WDG counter, to avoid an unexpected WDG
reset immediately after waking up the microcon-
troller.
58/263
ST72561
WINDOW WATCHDOG (Cont’d)
10.1.9 Interrupts
None.
WINDOW REGISTER (WDGWR)
Read/Write
Reset Value: 0111 1111 (7Fh)
10.1.10 Register Description
CONTROL REGISTER (WDGCR)
Read/Write
7
0
-
W6
W5
W4
W3 W2 W1
W0
Reset Value: 0111 1111 (7Fh)
Bit 7 = Reserved
Bits 6:0 = W[6:0] 7-bit window value
7
0
These bits contain the window value to be com-
pared to the downcounter.
WDGA T6
T5
T4
T3
T2
T1
T0
Bit 7 = WDGA Activation bit.
This bit is set by software and only cleared by
hardware after a reset. When WDGA = 1, the
watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled
Note: This bit is not used if the hardware watch-
dog option is enabled by option byte.
Bits 6:0 = T[6:0] 7-bit counter (MSB to LSB).
These bits contain the value of the watchdog
counter. It is decremented every 16384 f
cy-
OSC2
cles (approx.). A reset is produced when it rolls
over from 40h to 3Fh (T6 becomes cleared).
Figure 38. Watchdog Timer Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
WDGCR
WDGA
0
T6
1
T5
1
T4
1
T3
1
T2
1
T1
1
T0
1
2F
30
Reset Value
WDGWR
-
W6
1
W5
1
W4
1
W3
1
W2
1
W1
1
W0
1
Reset Value
0
59/263
ST72561
ON-CHIP PERIPHERALS (Cont’d)
10.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK MCC/RTC
10.2.2
The Main Clock Controller consists of three differ-
ent functions:
Clock-out Capability
The clock-out capability is an alternate function of
an I/O port pin that outputs a f clock to drive
■
a programmable CPU clock prescaler
OSC2
external devices. It is controlled by the MCO bit in
the MCCSR register.
■
a clock-out signal to supply external devices
a real time clock timer with interrupt capability
■
10.2.3
Real Time Clock Timer (RTC)
Each function can be used independently and si-
multaneously.
10.2.1
The counter of the real time clock timer allows an
interrupt to be generated based on an accurate
real time clock. Four different time bases depend-
Programmable CPU Clock Prescaler
The programmable CPU clock prescaler supplies
the clock for the ST7 CPU and its internal periph-
erals. It manages SLOW power saving mode (See
Section 8.2 "SLOW MODE" for more details).
ing directly on f
are available. The whole
OSC2
functionality is controlled by 4 bits of the MCCSR
register: TB[1:0], OIE and OIF.
When the RTC interrupt is enabled (OIE bit set),
the ST7 enters ACTIVE HALT mode when the
HALT instruction is executed. See Section 8.5
"ACTIVE HALT MODE" for more details.
The prescaler selects the f
cy and is controlled by three bits in the MCCSR
register: CP[1:0] and SMS.
main clock frequen-
CPU
Figure 39. Main Clock Controller (MCC/RTC) Block Diagram
MCO
fOSC2
TO
RTC
COUNTER
WATCHDOG
TIMER
MCO CP1 CP0 SMS TB1 TB0 OIE OIF
MCCSR
MCC/RTC INTERRUPT
DIV 2, 4, 8, 16
CPU CLOCK
TO CPU AND
PERIPHERALS
fCPU
60/263
ST72561
MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont’d)
10.2.4
Low Power Modes
Bits 6:5 = CP[1:0] CPU clock prescaler
Mode
Description
These bits select the CPU clock prescaler which is
applied in the different slow modes. Their action is
conditioned by the setting of the SMS bit. These
two bits are set and cleared by software
No effect on MCC/RTC peripheral.
MCC/RTC interrupt cause the device to
exit from WAIT mode.
WAIT
No effect on MCC/RTC counter (OIE bit
is set), the registers are frozen.
MCC/RTC interrupt cause the device to
exit from ACTIVE HALT mode.
f
in SLOW mode
CP1
CP0
CPU
ACTIVE HALT
f
f
/ 2
/ 4
/ 8
0
0
1
1
0
1
0
1
OSC2
OSC2
MCC/RTC counter and registers are fro-
zen.
MCC/RTC operation resumes when the
MCU is woken up by an interrupt with
“exit from HALT” capability.
HALT
f
OSC2
and
f
/ 16
OSC2
AWUF HALT
Bit 4 = SMS Slow mode select
This bit is set and cleared by software.
0: Normal mode. f = f
10.2.5
Interrupts
OSC2
CPU
The MCC/RTC interrupt event generates an inter-
rupt if the OIE bit of the MCCSR register is set and
the interrupt mask in the CC register is not active
(RIM instruction).
1: Slow mode. f
is given by CP1, CP0
CPU
See Section 8.2 "SLOW MODE" and Section 10.2
"MAIN CLOCK CONTROLLER WITH REAL TIME
CLOCK MCC/RTC" for more details.
Enable Exit
Control from
Exit
from
Halt
Event
Flag
Interrupt Event
Bits 3:2 = TB[1:0] Time base control
Bit
Wait
These bits select the programmable divider time
base. They are set and cleared by software.
Time base overflow
event
1)
OIF
OIE
Yes
No
Time Base
Counter
TB1 TB0
Note:
Prescaler
f
=4 MHz f
=8 MHz
OSC2
OSC2
The MCC/RTC interrupt wakes up the MCU from
ACTIVE HALT mode, not from HALT or AWUF
HALT mode.
16000
32000
80000
200000
4ms
8ms
2ms
4ms
0
0
1
1
0
1
0
1
10.2.6
Register Description
20ms
50ms
10ms
25ms
MCC CONTROL/STATUS REGISTER (MCCSR)
Read/Write
A modification of the time base is taken into ac-
count at the end of the current period (previously
set) to avoid an unwanted time shift. This allows to
use this time base as a real time clock.
Reset Value: 0000 0000 (00h)
7
0
MCO CP1 CP0 SMS TB1 TB0 OIE OIF
Bit 1 = OIE Oscillator interrupt enable
This bit set and cleared by software.
0: Oscillator interrupt disabled
Bit 7 = MCO Main clock out selection
This bit enables the MCO alternate function on the
corresponding I/O port. It is set and cleared by
software.
0: MCO alternate function disabled (I/O pin free for
general-purpose I/O)
1: Oscillator interrupt enabled
This interrupt can be used to exit from ACTIVE
HALT mode.
When this bit is set, calling the ST7 software HALT
instruction enters the ACTIVE HALT power saving
1: MCO alternate function enabled (f
port)
on I/O
OSC2
mode
.
61/263
ST72561
MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont’d)
Bit 0 = OIF Oscillator interrupt flag
This bit is set by hardware and cleared by software
reading the CSR register. It indicates when set
that the main oscillator has reached the selected
elapsed time (TB1:0).
CAUTION: The BRES and BSET instructions
must not be used on the MCCSR register to avoid
unintentionally clearing the OIF bit.
0: Timeout not reached
1: Timeout reached
Table 15. Main Clock Controller Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
SICSR
Reset Value
WDGRF
x
002Dh
002Eh
0
AVDIE
AVDF
LVDRF
0
0
0
MCCSR
Reset Value
MCO
0
CP1
0
CP0
0
SMS
0
TB1
0
TB0
0
OIE
0
OIF
0
62/263
ST72561
ON-CHIP PERIPHERALS (Cont’d)
10.3 PWM AUTO-RELOAD TIMER (ART)
10.3.1 Introduction
The Pulse Width Modulated Auto-Reload Timer
on-chip peripheral consists of an 8-bit auto reload
counter with compare/capture capabilities and of a
7-bit prescaler clock source.
– Output compare and Time base interrupt
– Up to two input capture functions
– External event detector
– Up to two external interrupt sources
These resources allow five possible operating
modes:
The three first modes can be used together with a
single counter frequency.
– Generation of up to four independent PWM sig-
nals
The timer can be used to wake up the MCU from
WAIT and HALT modes.
Figure 40. PWM Auto-Reload Timer Block Diagram
OCRx
DCRx
OEx
OPx
PWMCR
REGISTER
REGISTER
LOAD
PORT
ALTERNATE
FUNCTION
POLARITY
CONTROL
PWMx
COMPARE
8-BIT COUNTER
(CAR REGISTER)
ARR
REGISTER
LOAD
INPUT CAPTURE
CONTROL
ICRx
LOAD
ARTICx
REGISTER
ICSx
ICIEx
ICFx
ICCSR
ICx INTERRUPT
f
EXT
ARTCLK
f
COUNTER
f
CPU
MUX
f
INPUT
PROGRAMMABLE
PRESCALER
ARTCSR
EXCL CC2
CC1
CC0
TCE FCRL OIE
OVF
OVF INTERRUPT
63/263
ST72561
PWM AUTO-RELOAD TIMER (Cont’d)
10.3.2 Functional Description
Counter
Counter and Prescaler Initialization
The free running 8-bit counter is fed by the output
of the prescaler, and is incremented on every ris-
ing edge of the clock signal.
After RESET, the counter and the prescaler are
cleared and f
= f
.
INPUT
CPU
The counter can be initialized by:
It is possible to read or write the contents of the
counter on the fly by reading or writing the Counter
Access register (ARTCAR).
– Writing to the ARTARR register and then setting
the FCRL (Force Counter Re-Load) and the TCE
(Timer Counter Enable) bits in the ARTCSR reg-
ister.
When a counter overflow occurs, the counter is
automatically reloaded with the contents of the
ARTARR register (the prescaler is not affected).
– Writing to the ARTCAR counter access register,
In both cases the 7-bit prescaler is also cleared,
whereupon counting will start from a known value.
Counter clock and prescaler
The counter clock frequency is given by:
Direct access to the prescaler is not possible.
CC[2:0]
f
= f
/ 2
COUNTER
INPUT
Output compare control
The timer counter’s input clock (f
) feeds the
INPUT
The timer compare function is based on four differ-
ent comparisons with the counter (one for each
PWMx output). Each comparison is made be-
tween the counter value and an output compare
register (OCRx) value. This OCRx register can not
be accessed directly, it is loaded from the duty cy-
cle register (PWMDCRx) at each overflow of the
counter.
7-bit programmable prescaler, which selects one
of the eight available taps of the prescaler, as de-
fined by CC[2:0] bits in the Control/Status Register
(ARTCSR). Thus the division factor of the prescal-
n
er can be set to 2 (where n = 0, 1,..7).
This f
frequency source is selected through
INPUT
the EXCL bit of the ARTCSR register and can be
either the f or an external input frequency f
.
EXT
CPU
This double buffering method avoids glitch gener-
ation when changing the duty cycle on the fly.
The clock input to the counter is enabled by the
TCE (Timer Counter Enable) bit in the ARTCSR
register. When TCE is reset, the counter is
stopped and the prescaler and counter contents
are frozen. When TCE is set, the counter runs at
the rate of the selected clock source.
Figure 41. Output Compare Control
f
COUNTER
ARTARR=FDh
FFh
COUNTER
OCRx
FDh
FEh
FDh
FEh
FFh
FDh
FEh
FFh
FEh
FDh
PWMDCRx
FEh
FDh
PWMx
64/263
ST72561
PWM AUTO-RELOAD TIMER (Cont’d)
Independent PWM signal generation
When the counter reaches the value contained in
one of the output compare register (OCRx) the
corresponding PWMx pin level is restored.
This mode allows up to four Pulse Width Modulat-
ed signals to be generated on the PWMx output
pins with minimum core processing overhead.
This function is stopped during HALT mode.
It should be noted that the reload values will also
affect the value and the resolution of the duty cycle
of the PWM output signal. To obtain a signal on a
PWMx pin, the contents of the OCRx register must
be greater than the contents of the ARTARR reg-
ister.
Each PWMx output signal can be selected inde-
pendently using the corresponding OEx bit in the
PWM Control register (PWMCR). When this bit is
set, the corresponding I/O pin is configured as out-
put push-pull alternate function.
The maximum available resolution for the PWMx
duty cycle is:
The PWM signals all have the same frequency
which is controlled by the counter period and the
ARTARR register value.
Resolution = 1 / (256 - ARTARR)
Note: To get the maximum resolution (1/256), the
ARTARR register must be 0. With this maximum
resolution, 0% and 100% can be obtained by
changing the polarity.
f
= f
/ (256 - ARTARR)
PWM
COUNTER
When a counter overflow occurs, the PWMx pin
level is changed depending on the corresponding
OPx (output polarity) bit in the PWMCR register.
Figure 42. PWM Auto-reload Timer Function
255
DUTY CYCLE
REGISTER
(PWMDCRx)
AUTO-RELOAD
REGISTER
(ARTARR)
000
t
WITH OEx=1
AND OPx=0
WITH OEx=1
AND OPx=1
Figure 43. PWM Signal from 0% to 100% Duty Cycle
f
COUNTER
ARTARR=FDh
FFh
COUNTER
FDh
FEh
FDh
FEh
FFh
FDh
FEh
OCRx=FCh
OCRx=FDh
OCRx=FEh
OCRx=FFh
t
65/263
ST72561
PWM AUTO-RELOAD TIMER (Cont’d)
Output compare and Time base interrupt
External clock and event detector mode
Using the f external prescaler input clock, the
auto-reload timer can be used as an external clock
event detector. In this mode, the ARTARR register
On overflow, the OVF flag of the ARTCSR register
is set and an overflow interrupt request is generat-
ed if the overflow interrupt enable bit, OIE, in the
ARTCSR register, is set. The OVF flag must be re-
set by the user software. This interrupt can be
used as a time base in the application.
EXT
is used to select the n
number of events to
EVENT
be counted before setting the OVF flag.
n
= 256 - ARTARR
EVENT
Caution: The external clock function is not availa-
ble in HALT mode. If HALT mode is used in the ap-
plication, prior to executing the HALT instruction,
the counter must be disabled by clearing the TCE
bit in the ARTCSR register to avoid spurious coun-
ter increments.
Figure 44. External Event Detector Example (3 counts)
f
=f
EXT COUNTER
ARTARR=FDh
FFh
COUNTER
OVF
FDh
FEh
FDh
FEh
FFh
FDh
ARTCSR READ
ARTCSR READ
INTERRUPT
IF OIE=1
INTERRUPT
IF OIE=1
t
66/263
ST72561
PWM AUTO-RELOAD TIMER (Cont’d)
Input Capture Function
set). This means, the ARTICRx register has to be
read at each capture event to clear the CFx flag.
Input Capture mode allows the measurement of
external signal pulse widths through ARTICRx
registers.
The timing resolution is given by auto-reload coun-
Each input capture can generate an interrupt inde-
pendently on a selected input signal transition.
This event is flagged by a set of the corresponding
CFx bits of the Input Capture Control/Status regis-
ter (ARTICCSR).
ter cycle time (1/f
).
COUNTER
Note: During HALT mode, input capture is inhibit-
ed (the ARTICRx is never reloaded) and only the
external interrupt capability can be used.
These input capture interrupts are enabled
through the CIEx bits of the ARTICCSR register.
Note: The ARTICx signal is synchronized on CPU
clock. It takes two rising edges until ARTICRx is
latched with the counter value. Depending on the
prescaler value and the time when the ICAP event
occurs, the value loaded in the ARTICRx register
may be different.
The active transition (falling or rising edge) is soft-
ware programmable through the CSx bits of the
ARTICCSR register.
The read only input capture registers (ARTICRx)
are used to latch the auto-reload counter value
when a transition is detected on the ARTICx pin
(CFx bit set in ARTICCSR register). After fetching
the interrupt vector, the CFx flags can be read to
identify the interrupt source.
If the counter is clocked with the CPU clock, the
value latched in ARTICRx is always the next coun-
ter value after the event on ARTICx occurred (Fig-
ure 45).
Note: After a capture detection, data transfer in
the ARTICRx register is inhibited until the next
read (clearing the CFx bit).
The timer interrupt remains pending while the CFx
flag is set when the interrupt is enabled (CIEx bit
If the counter clock is prescaled, it depends on the
position of the ARTICx event within the counter cy-
cle (Figure 46).
Figure 45. Input Capture Timing Diagram, f
= f
CPU
COUNTER
fCPU
f
COUNTER
COUNTER
01h
02h
03h
04h
05h
06h
07h
INTERRUPT
ARTICx PIN
CFx FLAG
ICAP SAMPLED
05h
xxh
ICAP SAMPLED
t
67/263
ST72561
PWM AUTO-RELOAD TIMER (Cont’d)
Figure 46. input Capture Timing Diagram, f
= f
/ 4
COUNTER
CPU
f
CPU
f
COUNTER
COUNTER
05h
04h
03h
ARTICx PIN
CFx FLAG
INTERRUPT
ICAP SAMPLED
04h
xxh
ICRx REGISTER
t
f
CPU
f
COUNTER
COUNTER
05h
04h
03h
INTERRUPT
ARTICx PIN
CFx FLAG
ICAP SAMPLED
05h
xxh
ICRx REGISTER
t
68/263
ST72561
External Interrupt Capability
this case, the interrupt synchronization is done di-
rectly on the ARTICx pin edge (Figure 47).
This mode allows the Input capture capabilities to
be used as external interrupt sources. The inter-
rupts are generated on the edge of the ARTICx
signal.
Figure 47. ART External Interrupt in Halt Mode
ARTICx PIN
CFx FLAG
The edge sensitivity of the external interrupts is
programmable (CSx bit of ARTICCSR register)
and they are independently enabled through CIEx
bits of the ARTICCSR register. After fetching the
interrupt vector, the CFx flags can be read to iden-
tify the interrupt source.
INTERRUPT
t
During HALT mode, the external interrupts can be
used to wake up the micro (if the CIEx bit is set). In
69/263
ST72561
ON-CHIP PERIPHERALS (Cont’d)
10.3.3 Register Description
CONTROL / STATUS REGISTER (ARTCSR)
Read/Write
0: New transition not yet reached
1: Transition reached
COUNTER ACCESS REGISTER (ARTCAR)
Read/Write
Reset Value: 0000 0000 (00h)
7
0
Reset Value: 0000 0000 (00h)
EXCL CC2
CC1
CC0
TCE FCRL
OIE
OVF
7
0
Bit 7 = EXCLExternal Clock
CA7
CA6
CA5
CA4
CA3
CA2
CA1
CA0
This bit is set and cleared by software. It selects the
input clock for the 7-bit prescaler.
0: CPU clock.
Bit 7:0 = CA[7:0] Counter Access Data
1: External clock.
These bits can be set and cleared either by hard-
ware or by software. The ARTCAR register is used
to read or write the auto-reload counter “on the fly”
(while it is counting).
Bit 6:4 = CC[2:0] Counter Clock Control
These bits are set and cleared by software. They
determine the prescaler division ratio from f
.
INPUT
f
With f
INPUT
=8 MHz CC2 CC1 CC0
COUNTER
f
8 MHz
4 MHz
2 MHz
1 MHz
500 kHz
250 kHz
125 kHz
62.5 kHz
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
INPUT
AUTO-RELOAD REGISTER (ARTARR)
Read/Write
f
f
f
f
f
f
/ 2
/ 4
/ 8
/ 16
/ 32
/ 64
/ 128
INPUT
INPUT
INPUT
Reset Value: 0000 0000 (00h)
INPUT
INPUT
INPUT
7
0
f
INPUT
AR7
AR6
AR5
AR4
AR3
AR2
AR1
AR0
Bit 3 = TCE Timer Counter Enable
Bit 7:0 = AR[7:0]Counter Auto-Reload Data
This bit is set and cleared by software. It puts the
timer in the lowest power consumption mode.
0: Counter stopped (prescaler and counter frozen).
1: Counter running.
These bits are set and cleared by software. They
are used to hold the auto-reload value which is au-
tomatically loaded in the counter when an overflow
occurs. At the same time, the PWM output levels
are changed according to the corresponding OPx
bit in the PWMCR register.
Bit 2 = FCRLForce Counter Re-Load
This bit is write-only and any attempt to read it will
yieldalogicalzero.Whenset,itcausesthecontents
of ARTARR register to be loaded into the counter,
and the content of the prescaler register to be
cleared in order to initialize the timer before starting
to count.
This register has two PWM management func-
tions:
– Adjusting the PWM frequency
– Setting the PWM duty cycle resolution
Bit 1 = OIEOverflow Interrupt Enable
This bit is set and cleared by software. It allows to
enable/disable the interrupt which is generated
when the OVF bit is set.
0: Overflow Interrupt disable.
1: Overflow Interrupt enable.
PWM Frequency vs Resolution:
f
PWM
ARTARR
value
Resolution
Min
Max
0
8-bit
~0.244 kHz
~0.244 kHz
~0.488 kHz
~0.977 kHz
~1.953 kHz
31.25 kHz
62.5 kHz
125 kHz
250 kHz
500 kHz
Bit 0 = OVFOverflow Flag
This bit is set by hardware and cleared by software
reading the ARTCSR register. It indicates the tran-
sition of the counter from FFh to the ARTARR val-
[ 0..127 ]
> 7-bit
> 6-bit
> 5-bit
> 4-bit
[ 128..191 ]
[ 192..223 ]
[ 224..239 ]
ue
.
70/263
ST72561
ON-CHIP PERIPHERALS (Cont’d)
PWM CONTROL REGISTER (PWMCR)
Read/Write
DUTY CYCLE REGISTERS (PWMDCRx)
Read/Write
Reset Value: 0000 0000 (00h)
Reset Value: 0000 0000 (00h)
7
0
7
0
OE3
OE2
OE1
OE0
OP3
OP2
OP1
OP0
DC7
DC6
DC5
DC4
DC3
DC2
DC1
DC0
Bit 7:4 = OE[3:0] PWM Output Enable
Bit 7:0 = DC[7:0] Duty Cycle Data
These bits are set and cleared by software.
These bits are set and cleared by software. They
enable or disable the PWM output channels inde-
pendently acting on the corresponding I/O pin.
0: PWM output disabled.
A PWMDCRx register is associated with the OCRx
register of each PWM channel to determine the
second edge location of the PWM signal (the first
edge location is common to all channels and given
by the ARTARR register). These PWMDCR regis-
ters allow the duty cycle to be set independently
for each PWM channel.
1: PWM output enabled.
Bit 3:0 = OP[3:0] PWM Output Polarity
These bits are set and cleared by software. They
independently select the polarity of the four PWM
output signals.
PWMx output level
OPx
Counter <= OCRx
Counter > OCRx
1
0
0
1
0
1
Note: When an OPx bit is modified, the PWMx out-
put signal polarity is immediately reversed.
71/263
ST72561
ON-CHIP PERIPHERALS (Cont’d)
INPUT CAPTURE
INPUT CAPTURE REGISTERS (ARTICRx)
Read only
CONTROL / STATUS REGISTER (ARTICCSR)
Read/Write
Reset Value: 0000 0000 (00h)
Reset Value: 0000 0000 (00h)
7
0
7
0
0
IC7
IC6
IC5
IC4
IC3
IC2
IC1
IC0
0
CS2
CS1
CIE2 CIE1
CF2
CF1
Bit 7:0 = IC[7:0] Input Capture Data
Bit 7:6 = Reserved, always read as 0.
These read only bits are set and cleared by hard-
ware. An ARTICRx register contains the 8-bit
auto-reload counter value transferred by the input
capture channel x event.
Bit 5:4 = CS[2:1] Capture Sensitivity
These bits are set and cleared by software. They
determine the trigger event polarity on the corre-
sponding input capture channel.
0: Falling edge triggers capture on channel x.
1: Rising edge triggers capture on channel x.
Bit 3:2 = CIE[2:1] Capture Interrupt Enable
These bits are set and cleared by software. They
enable or disable the Input capture channel inter-
rupts independently.
0: Input capture channel x interrupt disabled.
1: Input capture channel x interrupt enabled.
Bit 1:0 = CF[2:1] Capture Flag
These bits are set by hardware and cleared by
software reading the corresponding ARTICRx reg-
ister. Each CFx bit indicates that an input capture x
has occurred.
0: No input capture on channel x.
1: An input capture has occurred on channel x.
72/263
ST72561
PWM AUTO-RELOAD TIMER (Cont’d)
Table 16. PWM Auto-Reload Timer Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
PWMDCR3
DC7
0
DC6
0
DC5
0
DC4
0
DC3
0
DC2
0
DC1
0
DC0
0
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
003Ah
003Bh
Reset Value
PWMDCR2
DC7
0
DC6
0
DC5
0
DC4
0
DC3
0
DC2
0
DC1
0
DC0
0
Reset Value
PWMDCR1
DC7
0
DC6
0
DC5
0
DC4
0
DC3
0
DC2
0
DC1
0
DC0
0
Reset Value
PWMDCR0
DC7
0
DC6
0
DC5
0
DC4
0
DC3
0
DC2
0
DC1
0
DC0
0
Reset Value
PWMCR
OE3
0
OE2
0
OE1
0
OE0
0
OP3
0
OP2
0
OP1
0
OP0
0
Reset Value
ARTCSR
EXCL
0
CC2
0
CC1
0
CC0
0
TCE
0
FCRL
0
RIE
0
OVF
0
Reset Value
ARTCAR
CA7
0
CA6
0
CA5
0
CA4
0
CA3
0
CA2
0
CA1
0
CA0
0
Reset Value
ARTARR
AR7
0
AR6
0
AR5
0
AR4
0
AR3
0
AR2
0
AR1
0
AR0
0
Reset Value
ARTICCSR
CE2
0
CE1
0
CS2
0
CS1
0
CF2
0
CF1
0
0
0
Reset Value
ARTICR1
IC7
0
IC6
0
IC5
0
IC4
0
IC3
0
IC2
0
IC1
0
IC0
0
Reset Value
ARTICR2
IC7
0
IC6
0
IC5
0
IC4
0
IC3
0
IC2
0
IC1
0
IC0
0
Reset Value
73/263
ST72561
10.4 16-BIT TIMER
10.4.1 Introduction
When reading an input signal on a non-bonded
pin, the value will always be ‘1’.
The timer consists of a 16-bit free-running counter
driven by a programmable prescaler.
10.4.3 Functional Description
10.4.3.1 Counter
It may be used for a variety of purposes, including
pulse length measurement of up to two input sig-
nals (input capture) or generation of up to two out-
put waveforms (output compare and PWM).
The main block of the Programmable Timer is a
16-bit free running upcounter and its associated
16-bit registers. The 16-bit registers are made up
of two 8-bit registers called high and low.
Pulse lengths and waveform periods can be mod-
ulated from a few microseconds to several milli-
seconds using the timer prescaler and the CPU
clock prescaler.
Counter Register (CR):
– Counter High Register (CHR) is the most sig-
nificant byte (MS Byte).
Some ST7 devices have two on-chip 16-bit timers.
They are completely independent, and do not
share any resources. They are synchronized after
a MCU reset as long as the timer clock frequen-
cies are not modified.
– Counter Low Register (CLR) is the least sig-
nificant byte (LS Byte).
Alternate Counter Register (ACR)
– Alternate Counter High Register (ACHR) is the
most significant byte (MS Byte).
– Alternate Counter Low Register (ACLR) is the
least significant byte (LS Byte).
This description covers one or two 16-bit timers. In
ST7 devices with two timers, register names are
prefixed with TA (Timer A) or TB (Timer B).
10.4.2 Main Features
■ Programmable prescaler: fCPU divided by 2, 4 or 8
■ Overflow status flag and maskable interrupt
■ External clock input (must be at least four times
slowerthantheCPUclockspeed)withthechoice
of active edge
■ 1 or 2 Output Compare functions each with:
– 2 dedicated 16-bit registers
These two read-only 16-bit registers contain the
same value but with the difference that reading the
ACLR register does not clear the TOF bit (Timer
overflow flag), located in the Status register, (SR),
(see note at the end of paragraph titled 16-bit read
sequence).
Writing in the CLR register or ACLR register resets
the free running counter to the FFFCh value.
Both counters have a reset value of FFFCh (this is
the only value which is reloaded in the 16-bit tim-
er). The reset value of both counters is also
FFFCh in One Pulse mode and PWM mode.
– 2 dedicated programmable signals
– 2 dedicated status flags
– 1 dedicated maskable interrupt
■ 1 or 2 Input Capture functions each with:
– 2 dedicated 16-bit registers
The timer clock depends on the clock control bits
of the CR2 register, as illustrated in Table 1. The
value in the counter register repeats every
131072, 262144 or 524288 CPU clock cycles de-
pending on the CC[1:0] bits.
– 2 dedicated active edge selection signals
– 2 dedicated status flags
– 1 dedicated maskable interrupt
■ Pulse width modulation mode (PWM)
■ One Pulse mode
The timer frequency can be f
or an external frequency.
/2, f
/4, f
/8
CPU
CPU
CPU
■ Reduced Power Mode
■ 5 alternate functions on I/O ports (ICAP1, ICAP2,
OCMP1, OCMP2, EXTCLK)*
The Block Diagram is shown in Figure 1.
*Note: Some timer pins may not be available (not
bonded) in some ST7 devices. Refer to the device
pin out description.
74/263
ST72561
16-BIT TIMER (Cont’d)
Figure 48. Timer Block Diagram
ST7 INTERNAL BUS
f
CPU
MCU-PERIPHERAL INTERFACE
8 low
8-bit
8 high
8
8
8
8
8
8
8
8
buffer
EXEDG
16
INPUT
CAPTURE
REGISTER
INPUT
CAPTURE
REGISTER
OUTPUT
COMPARE
REGISTER
OUTPUT
COMPARE
REGISTER
1/2
1/4
1/8
COUNTER
REGISTER
1
1
2
2
ALTERNATE
COUNTER
REGISTER
EXTCLK
pin
16
16
16
CC[1:0]
TIMER INTERNAL BUS
16 16
OVERFLOW
DETECT
EDGE DETECT
CIRCUIT1
OUTPUT COMPARE
CIRCUIT
ICAP1
pin
CIRCUIT
6
EDGE DETECT
CIRCUIT2
ICAP2
pin
OCMP1
pin
LATCH1
LATCH2
0
ICF1 OCF1 TOF ICF2 OCF2
0
TIMD
(Control/Status Register)
OCMP2
pin
CSR
EXEDG
ICIE OCIE TOIE FOLV2 FOLV1OLVL2 IEDG1 OLVL1
OC1E
OPM PWM CC1 CC0 IEDG2
OC2E
(Control Register 1) CR1
(Control Register 2) CR2
(See note)
Note: If IC, OC and TO interrupt requests have separate vectors
then the last OR is not present (See device Interrupt Vector Table)
TIMER INTERRUPT
75/263
ST72561
16-BIT TIMER (Cont’d)
16-bit read sequence: (from either the Counter
Register or the Alternate Counter Register).
Clearing the overflow interrupt request is done in
two steps:
1. Reading the SR register while the TOF bit is set.
2. An access (read or write) to the CLR register.
Beginning of the sequence
Read
LS Byte
Notes: The TOF bit is not cleared by accesses to
ACLR register. The advantage of accessing the
ACLR register rather than the CLR register is that
it allows simultaneous use of the overflow function
and reading the free running counter at random
times (for example, to measure elapsed time) with-
out the risk of clearing the TOF bit erroneously.
MS Byte
At t0
is buffered
Other
instructions
Returns the buffered
LS Byte value at t0
Read
LS Byte
At t0 +∆t
The timer is not affected by WAIT mode.
In HALT mode, the counter stops counting until the
mode is exited. Counting then resumes from the
previous count (MCU awakened by an interrupt) or
from the reset count (MCU awakened by a Reset).
Sequence completed
The user must read the MS Byte first, then the LS
Byte value is buffered automatically.
This buffered value remains unchanged until the
16-bit read sequence is completed, even if the
user reads the MS Byte several times.
10.4.3.2 External Clock
The external clock (where available) is selected if
CC0 = 1 and CC1 = 1 in the CR2 register.
After a complete reading sequence, if only the
CLR register or ACLR register are read, they re-
turn the LS Byte of the count value at the time of
the read.
The status of the EXEDG bit in the CR2 register
determines the type of level transition on the exter-
nal clock pin EXTCLK that will trigger the free run-
ning counter.
Whatever the timer mode used (input capture, out-
put compare, One Pulse mode or PWM mode) an
overflow occurs when the counter rolls over from
FFFFh to 0000h then:
The counter is synchronized with the falling edge
of the internal CPU clock.
A minimum of four falling edges of the CPU clock
must occur between two consecutive active edges
of the external clock; thus the external clock fre-
quency must be less than a quarter of the CPU
clock frequency.
– The TOF bit of the SR register is set.
– A timer interrupt is generated if:
– TOIE bit of the CR1 register is set and
– I bit of the CC register is cleared.
If one of these conditions is false, the interrupt re-
mains pending to be issued as soon as they are
both true.
76/263
ST72561
16-BIT TIMER (Cont’d)
Figure 49. Counter Timing Diagram, Internal Clock Divided by 2
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
FFFD FFFE FFFF 0000 0001 0002 0003
COUNTER REGISTER
TIMER OVERFLOW FLAG (TOF)
Figure 50. Counter Timing Diagram, Internal Clock Divided by 4
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
FFFC
FFFD
0000
0001
COUNTER REGISTER
TIMER OVERFLOW FLAG (TOF)
Figure 51. Counter Timing Diagram, Internal Clock Divided By 8
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
0000
FFFC
FFFD
COUNTER REGISTER
TIMER OVERFLOW FLAG (TOF)
Note: The MCU is in reset state when the internal reset signal is high, when it is low the MCU is running.
77/263
ST72561
16-BIT TIMER (Cont’d)
10.4.3.3 Input Capture
When an input capture occurs:
In this section, the index, i, may be 1 or 2 because
there are two input capture functions in the 16-bit
timer.
– ICFi bit is set.
– The ICiR register contains the value of the free
running counter on the active transition on the
ICAPi pin (see Figure 6).
The two 16-bit input capture registers (IC1R and
IC2R) are used to latch the value of the free run-
ning counter after a transition is detected on the
ICAPi pin (see figure 5).
– A timer interrupt is generated if the ICIE bit is set
and the I bit is cleared in the CC register. Other-
wise, the interrupt remains pending until both
conditions become true.
MS Byte
LS Byte
ICiR
ICiHR
ICiLR
Clearing the Input Capture interrupt request (that
is, clearing the ICFi bit) is done in two steps:
ICiR register is a read-only register.
1. Reading the SR register while the ICFi bit is set.
2. An access (read or write) to the ICiLR register.
The active transition is software programmable
through the IEDGi bit of Control Registers (CRi).
Timing resolution is one count of the free running
Notes:
counter: (f
/CC[1:0]).
CPU
1. After reading the ICiHR register, transfer of
input capture data is inhibited and ICFi will
never be set until the ICiLR register is also
read.
Procedure:
To use the input capture function select the follow-
ing in the CR2 register:
2. The ICiR register contains the free running
counter value which corresponds to the most
recent input capture.
– Select the timer clock (CC[1:0]) (see Table 1).
– Select the edge of the active transition on the
ICAP2 pin with the IEDG2 bit (the ICAP2 pin
must be configured as floating input or input with
pull-up without interrupt if this configuration is
available).
3. The two input capture functions can be used
together even if the timer also uses the two out-
put compare functions.
4. In One Pulse mode and PWM mode only Input
Capture 2 can be used.
And select the following in the CR1 register:
5. The alternate inputs (ICAP1 and ICAP2) are
always directly connected to the timer. So any
transitions on these pins activates the input
capture function.
– Set the ICIE bit to generate an interrupt after an
input capture coming from either the ICAP1 pin
or the ICAP2 pin
– Select the edge of the active transition on the
ICAP1 pin with the IEDG1 bit (the ICAP1pin must
be configured as floating input or input with pull-
up without interrupt if this configuration is availa-
ble).
Moreover if one of the ICAPi pins is configured
as an input and the second one as an output,
an interrupt can be generated if the user tog-
gles the output pin and if the ICIE bit is set.
This can be avoided if the input capture func-
tion i is disabled by reading the ICiHR (see note
1).
6. The TOF bit can be used with interrupt genera-
tion in order to measure events that go beyond
the timer range (FFFFh).
78/263
ST72561
16-BIT TIMER (Cont’d)
Figure 52. Input Capture Block Diagram
ICAP1
pin
(Control Register 1) CR1
EDGE DETECT
CIRCUIT2
EDGE DETECT
CIRCUIT1
ICIE
IEDG1
ICAP2
pin
(Status Register) SR
ICF1
ICF2
0
0
0
IC2R Register
IC1R Register
(Control Register 2) CR2
16-BIT
16-BIT FREE RUNNING
COUNTER
IEDG2
CC0
CC1
Figure 53. Input Capture Timing Diagram
TIMER CLOCK
FF01
FF02
FF03
COUNTER REGISTER
ICAPi PIN
ICAPi FLAG
FF03
ICAPi REGISTER
Note: The rising edge is the active edge.
79/263
ST72561
16-BIT TIMER (Cont’d)
10.4.3.4 Output Compare
– The OCMPi pin takes OLVLi bit value (OCMPi
pin latch is forced low during reset).
In this section, the index, i, may be 1 or 2 because
there are two output compare functions in the 16-
bit timer.
– A timer interrupt is generated if the OCIE bit is
set in the CR1 register and the I bit is cleared in
the CC register (CC).
This function can be used to control an output
waveform or indicate when a period of time has
elapsed.
The OCiR register value required for a specific tim-
ing application can be calculated using the follow-
ing formula:
When a match is found between the Output Com-
pare register and the free running counter, the out-
put compare function:
– Assigns pins with a programmable value if the
∆t f
PRESC
* CPU
∆ OCiR =
OCiE bit is set
– Sets a flag in the status register
– Generates an interrupt if enabled
Where:
∆t
= Output compare period (in seconds)
= CPU clock frequency (in hertz)
Two 16-bit registers Output Compare Register 1
(OC1R) and Output Compare Register 2 (OC2R)
contain the value to be compared to the counter
register each timer clock cycle.
f
CPU
= Timer prescaler factor (2, 4 or 8 de-
pending on CC[1:0] bits, see Table 1)
PRESC
MS Byte
LS Byte
OCiR
OCiHR
OCiLR
If the timer clock is an external clock, the formula
is:
These registers are readable and writable and are
not affected by the timer hardware. A reset event
changes the OCiR value to 8000h.
∆ OCiR = ∆t f
* EXT
Where:
Timing resolution is one count of the free running
counter: (f
∆t
= Output compare period (in seconds)
= External timer clock frequency (in hertz)
).
CC[1:0]
CPU/
f
EXT
Procedure:
Clearing the output compare interrupt request
(that is, clearing the OCFi bit) is done by:
To use the output compare function, select the fol-
lowing in the CR2 register:
1. Reading the SR register while the OCFi bit is
– Set the OCiE bit if an output is needed then the
OCMPi pin is dedicated to the output compare i
signal.
set.
2. An access (read or write) to the OCiLR register.
– Select the timer clock (CC[1:0]) (see Table 1).
And select the following in the CR1 register:
The following procedure is recommended to pre-
vent the OCFi bit from being set between the time
it is read and the write to the OCiR register:
– Select the OLVLi bit to applied to the OCMPi pins
after the match occurs.
– Write to the OCiHR register (further compares
are inhibited).
– Set the OCIE bit to generate an interrupt if it is
needed.
– Read the SR register (first step of the clearance
of the OCFi bit, which may be already set).
When a match is found between OCRi register
and CR register:
– Write to the OCiLR register (enables the output
compare function and clears the OCFi bit).
– OCFi bit is set.
80/263
ST72561
16-BIT TIMER (Cont’d)
Notes:
Forced Compare Output capability
1. After a processor write cycle to the OCiHR reg-
ister, the output compare function is inhibited
until the OCiLR register is also written.
When the FOLVi bit is set by software, the OLVLi
bit is copied to the OCMPi pin. The OLVi bit has to
be toggled in order to toggle the OCMPi pin when
it is enabled (OCiE bit = 1). The OCFi bit is then
not set by hardware, and thus no interrupt request
is generated.
2. If the OCiE bit is not set, the OCMPi pin is a
general I/O port and the OLVLi bit will not
appear when a match is found but an interrupt
could be generated if the OCIE bit is set.
The FOLVLi bits have no effect in both One Pulse
mode and PWM mode.
3. When the timer clock is f
/2, OCFi and
CPU
OCMPi are set while the counter value equals
the OCiR register value (see Figure 8). This
behavior is the same in OPM or PWM mode.
When the timer clock is f
/4, f
/8 or in
CPU
CPU
external clock mode, OCFi and OCMPi are set
while the counter value equals the OCiR regis-
ter value plus 1 (see Figure 9).
4. The output compare functions can be used both
for generating external events on the OCMPi
pins even if the input capture mode is also
used.
5. The value in the 16-bit OCiR register and the
OLVi bit should be changed after each suc-
cessful comparison in order to control an output
waveform or establish a new elapsed timeout.
Figure 54. Output Compare Block Diagram
16 BIT FREE RUNNING
OC1E
CC1 CC0
OC2E
COUNTER
(Control Register 2) CR2
16-bit
(Control Register 1) CR1
OUTPUT COMPARE
CIRCUIT
Latch
1
OCIE
FOLV2 FOLV1OLVL2
OLVL1
OCMP1
Pin
16-bit
16-bit
Latch
2
OCMP2
Pin
OC1R Register
OCF1
OCF2
0
0
0
OC2R Register
(Status Register) SR
81/263
ST72561
16-BIT TIMER (Cont’d)
Figure 55. Output Compare Timing Diagram, f
= f
/2
TIMER
CPU
INTERNAL CPU CLOCK
TIMER CLOCK
COUNTER REGISTER
2ECF 2ED0 2ED1 2ED2
2ED3
2ED4
2ED3
OUTPUT COMPARE REGISTER i (OCRi)
OUTPUT COMPARE FLAG i (OCFi)
OCMPi PIN (OLVLi = 1)
Figure 56. Output Compare Timing Diagram, f
= f
/4
TIMER
CPU
INTERNAL CPU CLOCK
TIMER CLOCK
2ECF 2ED0 2ED1 2ED2
2ED3
2ED4
2ED3
COUNTER REGISTER
OUTPUT COMPARE REGISTER i (OCRi)
COMPARE REGISTER i LATCH
OUTPUT COMPARE FLAG i (OCFi)
OCMPi PIN (OLVLi = 1)
82/263
ST72561
16-BIT TIMER (Cont’d)
10.4.3.5 One Pulse Mode
Clearing the Input Capture interrupt request (that
is, clearing the ICFi bit) is done in two steps:
One Pulse mode enables the generation of a
pulse when an external event occurs. This mode is
selected via the OPM bit in the CR2 register.
1. Reading the SR register while the ICFi bit is set.
2. An access (read or write) to the ICiLR register.
The One Pulse mode uses the Input Capture1
function and the Output Compare1 function.
The OC1R register value required for a specific
timing application can be calculated using the fol-
lowing formula:
Procedure:
t * f
To use One Pulse mode:
CPU
- 5
OCiR Value =
1. Load the OC1R register with the value corre-
sponding to the length of the pulse (see the for-
mula in the opposite column).
PRESC
Where:
t
= Pulse period (in seconds)
2. Select the following in the CR1 register:
f
= CPU clock frequency (in hertz)
CPU
– Using the OLVL1 bit, select the level to be ap-
plied to the OCMP1 pin after the pulse.
= Timer prescaler factor (2, 4 or 8 depend-
ing on the CC[1:0] bits, see Table 1)
PRESC
– Using the OLVL2 bit, select the level to be ap-
plied to the OCMP1 pin during the pulse.
If the timer clock is an external clock the formula is:
OCiR = t f
-5
– Select the edge of the active transition on the
ICAP1 pin with the IEDG1 bit (the ICAP1 pin
must be configured as floating input).
* EXT
Where:
t
= Pulse period (in seconds)
3. Select the following in the CR2 register:
f
= External timer clock frequency (in hertz)
– Set the OC1E bit, the OCMP1 pin is then ded-
icated to the Output Compare 1 function.
EXT
– Set the OPM bit.
When the value of the counter is equal to the value
of the contents of the OC1R register, the OLVL1
bit is output on the OCMP1 pin, (See Figure 10).
– Select the timer clock CC[1:0] (see Table 1).
One Pulse mode cycle
Notes:
1. The OCF1 bit cannot be set by hardware in
One Pulse mode but the OCF2 bit can generate
an Output Compare interrupt.
ICR1 = Counter
When
OCMP1 = OLVL2
event occurs
on ICAP1
Counter is reset
2. When the Pulse Width Modulation (PWM) and
One Pulse mode (OPM) bits are both set, the
PWM mode is the only active one.
to FFFCh
ICF1 bit is set
3. If OLVL1 = OLVL2 a continuous signal will be
seen on the OCMP1 pin.
When
Counter
OCMP1 = OLVL1
= OC1R
4. The ICAP1 pin can not be used to perform input
capture. The ICAP2 pin can be used to perform
input capture (ICF2 can be set and IC2R can be
loaded) but the user must take care that the
counter is reset each time a valid edge occurs
on the ICAP1 pin and ICF1 can also generates
interrupt if ICIE is set.
Then, on a valid event on the ICAP1 pin, the coun-
ter is initialized to FFFCh and OLVL2 bit is loaded
on the OCMP1 pin, the ICF1 bit is set and the val-
ue FFFDh is loaded in the IC1R register.
Because the ICF1 bit is set when an active edge
occurs, an interrupt can be generated if the ICIE
bit is set.
5. When One Pulse mode is used OC1R is dedi-
cated to this mode. Nevertheless OC2R and
OCF2 can be used to indicate a period of time
has been elapsed but cannot generate an out-
put waveform because the level OLVL2 is dedi-
cated to the One Pulse mode.
83/263
ST72561
16-BIT TIMER (Cont’d)
Figure 57. One Pulse Mode Timing Example
2ED3
01F8
IC1R
FFFC FFFD FFFE
2ED0 2ED1 2ED2
2ED3
FFFC FFFD
01F8
COUNTER
ICAP1
OLVL2
OLVL1
OLVL2
OCMP1
compare1
Note: IEDG1 = 1, OC1R = 2ED0h, OLVL1 = 0, OLVL2 = 1
Figure 58. Pulse Width Modulation Mode Timing Example with 2 Output Compare Functions
2ED0 2ED1 2ED2
34E2 FFFC
FFFC FFFD FFFE
34E2
COUNTER
OCMP1
OLVL2
OLVL1
OLVL2
compare2
compare1
compare2
Note: OC1R = 2ED0h, OC2R = 34E2, OLVL1 = 0, OLVL2 = 1
Note: On timers with only one Output Compare register, a fixed frequency PWM signal can be generated
using the output compare and the counter overflow to define the pulse length.
84/263
ST72561
16-BIT TIMER (Cont’d)
10.4.3.6 Pulse Width Modulation Mode
If OLVL1 = 1 and OLVL2 = 0 the length of the pos-
itive pulse is the difference between the OC2R and
OC1R registers.
Pulse Width Modulation (PWM) mode enables the
generation of a signal with a frequency and pulse
length determined by the value of the OC1R and
OC2R registers.
If OLVL1 = OLVL2 a continuous signal will be
seen on the OCMP1 pin.
Pulse Width Modulation mode uses the complete
Output Compare 1 function plus the OC2R regis-
ter, and so this functionality can not be used when
PWM mode is activated.
The OCiR register value required for a specific tim-
ing application can be calculated using the follow-
ing formula:
t * f
CPU
PRESC
- 5
OCiR Value =
In PWM mode, double buffering is implemented on
the output compare registers. Any new values writ-
ten in the OC1R and OC2R registers are taken
into account only at the end of the PWM period
(OC2) to avoid spikes on the PWM output pin
(OCMP1).
Where:
t
= Signal or pulse period (in seconds)
= CPU clock frequency (in hertz)
f
CPU
= Timer prescaler factor (2, 4 or 8 depend-
ing on CC[1:0] bits, see Table 1)
PRESC
Procedure
To use Pulse Width Modulation mode:
If the timer clock is an external clock the formula is:
1. Load the OC2R register with the value corre-
sponding to the period of the signal using the
formula in the opposite column.
OCiR = t f
-5
* EXT
Where:
t
2. Load the OC1R register with the value corre-
sponding to the period of the pulse if
(OLVL1 = 0 and OLVL2 = 1) using the formula
in the opposite column.
= Signal or pulse period (in seconds)
f
= External timer clock frequency (in hertz)
EXT
3. Select the following in the CR1 register:
The Output Compare 2 event causes the counter
to be initialized to FFFCh (See Figure 11)
– Using the OLVL1 bit, select the level to be ap-
plied to the OCMP1 pin after a successful
comparison with the OC1R register.
Notes:
1. After a write instruction to the OCiHR register,
the output compare function is inhibited until the
OCiLR register is also written.
– Using the OLVL2 bit, select the level to be ap-
plied to the OCMP1 pin after a successful
comparison with the OC2R register.
2. The OCF1 and OCF2 bits cannot be set by
hardware in PWM mode therefore the Output
Compare interrupt is inhibited.
4. Select the following in the CR2 register:
– Set OC1E bit: the OCMP1 pin is then dedicat-
ed to the output compare 1 function.
3. The ICF1 bit is set by hardware when the coun-
ter reaches the OC2R value and can produce a
timer interrupt if the ICIE bit is set and the I bit is
cleared.
– Set the PWM bit.
– Select the timer clock (CC[1:0]) (see Table 1).
Pulse Width Modulation cycle
4. In PWM mode the ICAP1 pin can not be used
to perform input capture because it is discon-
nected to the timer. The ICAP2 pin can be used
to perform input capture (ICF2 can be set and
IC2R can be loaded) but the user must take
care that the counter is reset each period and
ICF1 can also generates interrupt if ICIE is set.
When
Counter
= OC1R
OCMP1 = OLVL1
OCMP1 = OLVL2
5. When the Pulse Width Modulation (PWM) and
One Pulse mode (OPM) bits are both set, the
PWM mode is the only active one.
When
Counter
= OC2R
Counter is reset
to FFFCh
ICF1 bit is set
85/263
ST72561
16-BIT TIMER (Cont’d)
10.4.4 Low Power Modes
Mode
Description
No effect on 16-bit Timer.
Timer interrupts cause the device to exit from WAIT mode.
WAIT
16-bit Timer registers are frozen.
In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous
count when the MCU is woken up by an interrupt with “exit from HALT mode” capability or from the counter
reset value when the MCU is woken up by a RESET.
HALT
If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is armed. Consequent-
ly, when the MCU is woken up by an interrupt with “exit from HALT mode” capability, the ICFi bit is set, and
the counter value present when exiting from HALT mode is captured into the ICiR register.
10.4.5 Interrupts
Enable
Control from
Bit
Exit
Exit
from
Halt
Event
Flag
Interrupt Event
Wait
Input Capture 1 event/Counter reset in PWM mode
Input Capture 2 event
ICF1
ICF2
ICIE
Output Compare 1 event (not available in PWM mode)
Output Compare 2 event (not available in PWM mode)
Timer Overflow event
OCF1
OCF2
TOF
Yes
No
OCIE
TOIE
Note: The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts chap-
ter). These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt
mask in the CC register is reset (RIM instruction).
10.4.6 Summary of Timer Modes
TIMER RESOURCES
MODES
Input Capture 1
Input Capture 2
Output Compare 1 Output Compare 2
Input Capture (1 and/or 2)
Output Compare (1 and/or 2)
One Pulse Mode
Yes
Yes
Yes
No
Yes
1)
3)
2)
Not Recommended
Not Recommended
Partially
No
No
PWM Mode
1) See note 4 in Section 0.1.3.5 One Pulse Mode
2) See note 5 in Section 0.1.3.5 One Pulse Mode
3) See note 4 in Section 0.1.3.6 Pulse Width Modulation Mode
86/263
ST72561
16-BIT TIMER (Cont’d)
10.4.7 Register Description
Bit 4 = FOLV2 Forced Output Compare 2.
This bit is set and cleared by software.
0: No effect on the OCMP2 pin.
Each Timer is associated with three control and
status registers, and with six pairs of data registers
(16-bit values) relating to the two input captures,
the two output compares, the counter and the al-
ternate counter.
1:Forces the OLVL2 bit to be copied to the
OCMP2 pin, if the OC2E bit is set and even if
there is no successful comparison.
Bit 3 = FOLV1 Forced Output Compare 1.
This bit is set and cleared by software.
0: No effect on the OCMP1 pin.
CONTROL REGISTER 1 (CR1)
Read/Write
1: Forces OLVL1 to be copied to the OCMP1 pin, if
the OC1E bit is set and even if there is no suc-
cessful comparison.
Reset Value: 0000 0000 (00h)
7
0
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
Bit 2 = OLVL2 Output Level 2.
This bit is copied to the OCMP2 pin whenever a
successful comparison occurs with the OC2R reg-
ister and OCxE is set in the CR2 register. This val-
ue is copied to the OCMP1 pin in One Pulse mode
and Pulse Width Modulation mode.
Bit 7 = ICIE Input Capture Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the
ICF1 or ICF2 bit of the SR register is set.
Bit 6 = OCIE Output Compare Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the
OCF1 or OCF2 bit of the SR register is set.
Bit 1 = IEDG1 Input Edge 1.
This bit determines which type of level transition
on the ICAP1 pin will trigger the capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
Bit 5 = TOIE Timer Overflow Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is enabled whenever the TOF
bit of the SR register is set.
Bit 0 = OLVL1 Output Level 1.
The OLVL1 bit is copied to the OCMP1 pin when-
ever a successful comparison occurs with the
OC1R register and the OC1E bit is set in the CR2
register.
87/263
ST72561
16-BIT TIMER (Cont’d)
CONTROL REGISTER 2 (CR2)
Read/Write
Bit 4 = PWM Pulse Width Modulation.
0: PWM mode is not active.
1: PWM mode is active, the OCMP1 pin outputs a
programmable cyclic signal; the length of the
pulse depends on the value of OC1R register;
the period depends on the value of OC2R regis-
ter.
Reset Value: 0000 0000 (00h)
7
0
OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG
Bit 3, 2 = CC[1:0] Clock Control.
Bit 7 = OC1E Output Compare 1 Pin Enable.
This bit is used only to output the signal from the
timer on the OCMP1 pin (OLV1 in Output Com-
pare mode, both OLV1 and OLV2 in PWM and
one-pulse mode). Whatever the value of the OC1E
bit, the Output Compare 1 function of the timer re-
mains active.
0: OCMP1 pin alternate function disabled (I/O pin
free for general-purpose I/O).
1: OCMP1 pin alternate function enabled.
The timer clock mode depends on these bits:
Table 17. Clock Control Bits
Timer Clock
CC1
CC0
fCPU / 4
fCPU / 2
fCPU / 8
0
1
0
1
0
1
External Clock (where available)
Note: If the external clock pin is not available, pro-
gramming the external clock configuration stops
the counter.
Bit 6 = OC2E Output Compare 2 Pin Enable.
This bit is used only to output the signal from the
timer on the OCMP2 pin (OLV2 in Output Com-
pare mode). Whatever the value of the OC2E bit,
the Output Compare 2 function of the timer re-
mains active.
0: OCMP2 pin alternate function disabled (I/O pin
free for general-purpose I/O).
1: OCMP2 pin alternate function enabled.
Bit 1 = IEDG2 Input Edge 2.
This bit determines which type of level transition
on the ICAP2 pin will trigger the capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
Bit 5 = OPM One Pulse Mode.
Bit 0 = EXEDG External Clock Edge.
0: One Pulse mode is not active.
This bit determines which type of level transition
on the external clock pin EXTCLK will trigger the
counter register.
1: One Pulse mode is active, the ICAP1 pin can be
used to trigger one pulse on the OCMP1 pin; the
active transition is given by the IEDG1 bit. The
length of the generated pulse depends on the
contents of the OC1R register.
0: A falling edge triggers the counter register.
1: A rising edge triggers the counter register.
88/263
ST72561
16-BIT TIMER (Cont’d)
CONTROL/STATUS REGISTER (CSR)
Read/Write (bits 7:3 read only)
Reset Value: xxxx x0xx (xxh)
7
Note: Reading or writing the ACLR register does
not clear TOF.
Bit 4 = ICF2 Input Capture Flag 2.
0: No input capture (reset value).
1: An input capture has occurred on the ICAP2
pin. To clear this bit, first read the SR register,
then read or write the low byte of the IC2R
(IC2LR) register.
0
0
ICF1 OCF1 TOF ICF2 OCF2 TIMD
0
Bit 7 = ICF1 Input Capture Flag 1.
0: No input capture (reset value).
1: An input capture has occurred on the ICAP1 pin
or the counter has reached the OC2R value in
PWM mode. To clear this bit, first read the SR
register, then read or write the low byte of the
IC1R (IC1LR) register.
Bit 3 = OCF2 Output Compare Flag 2.
0: No match (reset value).
1: The content of the free running counter has
matched the content of the OC2R register. To
clear this bit, first read the SR register, then read
or write the low byte of the OC2R (OC2LR) reg-
ister.
Bit 6 = OCF1 Output Compare Flag 1.
0: No match (reset value).
1: The content of the free running counter has
matched the content of the OC1R register. To
clear this bit, first read the SR register, then read
or write the low byte of the OC1R (OC1LR) reg-
ister.
Bit 2 = TIMD Timer disable.
This bit is set and cleared by software. When set, it
freezes the timer prescaler and counter and disa-
bled the output functions (OCMP1 and OCMP2
pins) to reduce power consumption. Access to the
timer registers is still available, allowing the timer
configuration to be changed, or the counter reset,
while it is disabled.
Bit 5 = TOF Timer Overflow Flag.
0: No timer overflow (reset value).
1:The free running counter rolled over from FFFFh
to 0000h. To clear this bit, first read the SR reg-
ister, then read or write the low byte of the CR
(CLR) register.
0: Timer enabled
1: Timer prescaler, counter and outputs disabled
Bits 1:0 = Reserved, must be kept cleared.
89/263
ST72561
16-BIT TIMER (Cont’d)
INPUT CAPTURE 1 HIGH REGISTER (IC1HR)
OUTPUT COMPARE
(OC1HR)
1
HIGH REGISTER
Read Only
Reset Value: Undefined
Read/Write
Reset Value: 1000 0000 (80h)
This is an 8-bit read only register that contains the
high part of the counter value (transferred by the
input capture 1 event).
This is an 8-bit register that contains the high part
of the value to be compared to the CHR register.
7
0
7
0
MSB
LSB
MSB
LSB
INPUT CAPTURE 1 LOW REGISTER (IC1LR)
OUTPUT COMPARE
(OC1LR)
1
LOW REGISTER
Read Only
Reset Value: Undefined
Read/Write
Reset Value: 0000 0000 (00h)
This is an 8-bit read only register that contains the
low part of the counter value (transferred by the in-
put capture 1 event).
This is an 8-bit register that contains the low part of
the value to be compared to the CLR register.
7
0
7
0
MSB
LSB
MSB
LSB
90/263
ST72561
16-BIT TIMER (Cont’d)
OUTPUT COMPARE
(OC2HR)
2
HIGH REGISTER
ALTERNATE COUNTER HIGH REGISTER
(ACHR)
Read/Write
Reset Value: 1000 0000 (80h)
Read Only
Reset Value: 1111 1111 (FFh)
This is an 8-bit register that contains the high part
of the value to be compared to the CHR register.
This is an 8-bit register that contains the high part
of the counter value.
7
0
7
0
MSB
LSB
MSB
LSB
OUTPUT COMPARE
(OC2LR)
2
LOW REGISTER
ALTERNATE COUNTER LOW REGISTER
(ACLR)
Read/Write
Reset Value: 0000 0000 (00h)
Read Only
Reset Value: 1111 1100 (FCh)
This is an 8-bit register that contains the low part of
the value to be compared to the CLR register.
This is an 8-bit register that contains the low part of
the counter value. A write to this register resets the
counter. An access to this register after an access
to CSR register does not clear the TOF bit in the
CSR register.
7
0
MSB
LSB
7
0
COUNTER HIGH REGISTER (CHR)
MSB
LSB
Read Only
Reset Value: 1111 1111 (FFh)
INPUT CAPTURE 2 HIGH REGISTER (IC2HR)
This is an 8-bit register that contains the high part
of the counter value.
Read Only
Reset Value: Undefined
7
0
This is an 8-bit read only register that contains the
high part of the counter value (transferred by the
Input Capture 2 event).
MSB
LSB
7
0
MSB
LSB
COUNTER LOW REGISTER (CLR)
Read Only
Reset Value: 1111 1100 (FCh)
This is an 8-bit register that contains the low part of
the counter value. A write to this register resets the
counter. An access to this register after accessing
the CSR register clears the TOF bit.
INPUT CAPTURE 2 LOW REGISTER (IC2LR)
Read Only
Reset Value: Undefined
This is an 8-bit read only register that contains the
low part of the counter value (transferred by the In-
put Capture 2 event).
7
0
MSB
LSB
7
0
MSB
LSB
91/263
ST72561
16-BIT TIMER (Cont’d)
Table 18. 16-Bit Timer Register Map
Address
(Hex.)
Register
Name
7
6
5
4
3
2
1
0
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
CR2
OC1E
ICIE
OC2E
OCIE
OCF1
OPM
TOIE
TOF
PWM
FOLV2
ICF2
CC1
FOLV1
OCF2
CC0
OLVL2
TIMD
IEDG2
IEDG1
EXEDG
OLVL1
CR1
CSR
ICF1
MSB
MSB
MSB
MSB
MSB
MSB
MSB
MSB
MSB
MSB
MSB
MSB
IC1HR
IC1LR
OC1HR
OC1LR
CHR
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
CLR
ACHR
ACLR
IC2HR
IC2LR
OC2HR
OC2LR
92/263
ST72561
10.5 8-BIT TIMER (TIM8)
10.5.1 Introduction
When reading an input signal on a non-bonded
pin, the value will always be ‘1’.
The timer consists of a 8-bit free-running counter
driven by a programmable prescaler.
10.5.3 Functional Description
10.5.3.1 Counter
It may be used for a variety of purposes, including
pulse length measurement of up to two input sig-
nals (input capture) or generation of up to two out-
put waveforms (output compare and PWM).
The main block of the Programmable Timer is a 8-
bit free running upcounter and its associated 8-bit
registers.
Pulse lengths and waveform periods can be mod-
ulated from a few microseconds to several milli-
seconds using the timer prescaler and the clock
prescaler.
These two read-only 8-bit registers contain the
same value but with the difference that reading the
ACTR register does not clear the TOF bit (Timer
overflow flag), located in the Status register, (SR).
10.5.2 Main Features
Writing in the CTR register or ACTR register re-
sets the free running counter to the FCh value.
Both counters have a reset value of FCh (this is
the only value which is reloaded in the 8-bit timer).
The reset value of both counters is also FCh in
One Pulse mode and PWM mode.
■ Programmable prescaler: f
divided by 2, 4 , 8
CPU
or f
divided by 8000.
OSC2
■ Overflow status flag and maskable interrupt
■ Output compare functions with
– 2 dedicated 8-bit registers
– 2 dedicated programmable signals
– 2 dedicated status flags
The timer clock depends on the clock control bits
of the CR2 register, as shown in Table 1. The val-
ue in the counter register repeats every 512, 1024,
– 1 dedicated maskable interrupt
■ Input capture functions with
– 2 dedicated 8-bit registers
2048 or 20480000 f
the CC[1:0] bits.
clock cycles depending on
CPU
The timer frequency can be f
/2, f
/4, f
/8
CPU
CPU
CPU
or f
/8000.
– 2 dedicated active edge selection signals
– 2 dedicated status flags
OSC2
For example, if f
/8000 is selected, and
OSC2
f
= 8 MHz, the timer frequency will be 1 ms.
OSC2
– 1 dedicated maskable interrupt
■ Pulse width modulation mode (PWM)
■ One pulse mode
Refer to Table 1 on page 16.
■ Reduced Power Mode
■ 4 alternate functions on I/O ports (ICAP1, ICAP2,
OCMP1, OCMP2)*
The Block Diagram is shown in Figure 1.
*Note: Some timer pins may not be available (not
bonded) in some ST7 devices. Refer to the device
pin out description.
93/263
ST72561
8-BIT TIMER (Cont’d)
Figure 59. Timer Block Diagram
ST7 INTERNAL BUS
f
CPU
MCU-PERIPHERAL INTERFACE
8
8
8
8
8
INPUT
CAPTURE
REGISTER
INPUT
CAPTURE
REGISTER
OUTPUT
COMPARE
REGISTER
OUTPUT
COMPARE
REGISTER
1/2
1/4
1/8
COUNTER
REGISTER
1
1
2
2
1/8000
f
ALTERNATE
COUNTER
REGISTER
OSC2
8
8
8
CC[1:0]
TIMER INTERNAL BUS
8
8
OVERFLOW
EDGE DETECT
CIRCUIT1
OUTPUT COMPARE
CIRCUIT
ICAP1
pin
DETECT
CIRCUIT
6
EDGE DETECT
CIRCUIT2
ICAP2
pin
OCMP1
pin
LATCH1
LATCH2
0
ICF1 OCF1 TOF ICF2 OCF2
0
TIMD
(Control/Status Register)
OCMP2
pin
CSR
0
ICIE OCIE TOIE FOLV2 FOLV1OLVL2 IEDG1 OLVL1
OC1E
OPM PWM CC1 CC0 IEDG2
OC2E
(Control Register 1) CR1
(Control Register 2) CR2
(See note)
Note: If IC, OC and TO interrupt requests have separate vectors
then the last OR is not present (See device Interrupt Vector Table)
TIMER INTERRUPT
94/263
ST72561
8-BIT TIMER (Cont’d)
Whatever the timer mode used (input capture, out-
put compare, one pulse mode or PWM mode) an
overflow occurs when the counter rolls over from
FFh to 00h then:
Notes: The TOF bit is not cleared by accesses to
ACTR register. The advantage of accessing the
ACTR register rather than the CTR register is that
it allows simultaneous use of the overflow function
and reading the free running counter at random
times (for example, to measure elapsed time) with-
out the risk of clearing the TOF bit erroneously.
– The TOF bit of the SR register is set.
– A timer interrupt is generated if:
– TOIE bit of the CR1 register is set and
– I bit of the CC register is cleared.
The timer is not affected by WAIT mode.
In HALT mode, the counter stops counting until the
mode is exited. Counting then resumes from the
previous count (MCU awakened by an interrupt) or
from the reset count (MCU awakened by a Reset).
If one of these conditions is false, the interrupt re-
mains pending to be issued as soon as they are
both true.
Clearing the overflow interrupt request is done in
two steps:
1. Reading the SR register while the TOF bit is set.
2. An access (read or write) to the CTR register.
95/263
ST72561
8-BIT TIMER (Cont’d)
Figure 60. Counter Timing Diagram, Internal Clock Divided by 2
f
CLOCK
CPU
INTERNAL RESET
TIMER CLOCK
FD
FE
FF
00
01
02
03
COUNTER REGISTER
TIMER OVERFLOW FLAG (TOF)
Figure 61. Counter Timing Diagram, Internal Clock Divided by 4
f
CLOCK
CPU
INTERNAL RESET
TIMER CLOCK
FC
FD
00
01
COUNTER REGISTER
TIMER OVERFLOW FLAG (TOF)
Figure 62. Counter Timing Diagram, Internal Clock Divided by 8
f
CLOCK
CPU
INTERNAL RESET
TIMER CLOCK
00
FC
FD
COUNTER REGISTER
TIMER OVERFLOW FLAG (TOF)
Note: The MCU is in reset state when the internal reset signal is high, when it is low the MCU is running.
96/263
ST72561
8-BIT TIMER (Cont’d)
10.5.3.2 Input Capture
When an input capture occurs:
In this section, the index, i, may be 1 or 2 because
there are two input capture functions in the 8-bit
timer.
– ICFi bit is set.
– The ICiR register contains the value of the free
running counter on the active transition on the
ICAPi pin (see Figure 6).
The two 8-bit input capture registers (IC1R and
IC2R) are used to latch the value of the free run-
ning counter after a transition is detected on the
ICAPi pin (see Figure 5).
– A timer interrupt is generated if the ICIE bit is set
and the interrrupt mask is cleared in the CC reg-
ister. Otherwise, the interrupt remains pending
until both conditions become true.
ICiR register is a read-only register.
The active transition is software programmable
through the IEDGi bit of Control Registers (CRi).
Clearing the Input Capture interrupt request (that
is, clearing the ICFi bit) is done in two steps:
Timing resolution is one count of the free running
counter (see Table 1).
1. Reading the SR register while the ICFi bit is set.
2. An access (read or write) to the ICiR register.
Procedure:
Notes:
To use the input capture function select the follow-
ing in the CR2 register:
1. The ICiR register contains the free running
counter value which corresponds to the most re-
cent input capture.
– Select the timer clock (CC[1:0]) (see Table 1).
2. The two input capture functions can be used to-
gether even if the timer also uses the two output
compare functions.
3. Once the ICIE bit is set both input capture fea-
tures may trigger interrupt requests. If only one is
needed in the application, the interrupt routine
software needs to discard the unwanted capture
interrupt. This can be done by checking the ICF1
and ICF2 flags and resetting them both.
4. In One pulse Mode and PWM mode only Input
Capture 2 can be used.
5. The alternate inputs (ICAP1 and ICAP2) are al-
ways directly connected to the timer. So any tran-
sitions on these pins activates the input capture
function.
– Select the edge of the active transition on the
ICAP2 pin with the IEDG2 bit (the ICAP2 pin
must be configured as floating input or input with
pull-up without interrupt if this configuration is
available).
And select the following in the CR1 register:
– Set the ICIE bit to generate an interrupt after an
input capture coming from either the ICAP1 pin
or the ICAP2 pin
– Select the edge of the active transition on the
ICAP1 pin with the IEDG1 bit (the ICAP1 pin
must be configured as floating input or input with
pull-up without interrupt if this configuration is
available).
Moreover if one of the ICAPi pins is configured as
an input and the second one as an output, an inter-
rupt can be generated if the user toggles the output
pin and if the ICIE bit is set.
6. The TOF bit can be used with interrupt genera-
tion in order to measure events that go beyond the
timer range (FFh).
97/263
ST72561
8-BIT TIMER (Cont’d)
Figure 63. Input Capture Block Diagram
ICAP1
pin
(Control Register 1) CR1
EDGE DETECT
CIRCUIT2
EDGE DETECT
CIRCUIT1
ICIE
IEDG1
ICAP2
pin
(Status Register) SR
ICF1
ICF2
0
0
0
IC2R Register
IC1R Register
(Control Register 2) CR2
8-bit
8-bit
FREE RUNNING
COUNTER
IEDG2
CC0
CC1
Figure 64. Input Capture Timing Diagram
TIMER CLOCK
01
02
03
COUNTER REGISTER
ICAPi PIN
ICAPi FLAG
03
ICAPi REGISTER
Note: The rising edge is the active edge.
98/263
ST72561
8-BIT TIMER (Cont’d)
10.5.3.3 Output Compare
– Select the OLVLi bit to applied to the OCMPi pins
after the match occurs.
In this section, the index, i, may be 1 or 2 because
there are two output compare functions in the 8-bit
timer.
– Set the OCIE bit to generate an interrupt if it is
needed.
This function can be used to control an output
waveform or indicate when a period of time has
elapsed.
When a match is found between OCRi register
and CR register:
– OCFi bit is set.
When a match is found between the Output Com-
pare register and the free running counter, the out-
put compare function:
– The OCMPi pin takes OLVLi bit value (OCMPi
pin latch is forced low during reset).
– A timer interrupt is generated if the OCIE bit is
set in the CR1 register and the I bit is cleared in
the CC register (CC).
– Assigns pins with a programmable value if the
OCiE bit is set
– Sets a flag in the status register
– Generates an interrupt if enabled
The OCiR register value required for a specific tim-
ing application can be calculated using the follow-
ing formula:
Two 8-bit registers Output Compare Register 1
(OC1R) and Output Compare Register 2 (OC2R)
contain the value to be compared to the counter
register each timer clock cycle.
∆t f
PRESC
CPU
*
∆ OCiR =
These registers are readable and writable and are
not affected by the timer hardware. A reset event
changes the OCiR value to 00h.
Where:
Timing resolution is one count of the free running
∆t
= Output compare period (in seconds)
= PLL output x2 clock frequency in hertz
counter: (f
).
CPU CC[1:0]
/
f
CPU
(or f
/2 if PLL is not enabled)
OSC
Procedure:
= Timer prescaler factor (2, 4, 8 or 8000
depending on CC[1:0] bits, see Table 1)
PRESC
To use the output compare function, select the fol-
lowing in the CR2 register:
– Set the OCiE bit if an output is needed then the
OCMPi pin is dedicated to the output compare i
signal.
Clearing the output compare interrupt request
(that is, clearing the OCFi bit) is done by:
1. Reading the SR register while the OCFi bit is
– Select the timer clock (CC[1:0]) (see Table 1).
And select the following in the CR1 register:
set.
2. An access (read or write) to the OCiR register.
99/263
ST72561
8-BIT TIMER (Cont’d)
Notes:
waveform or establish a new elapsed timeout.
1. Once the OCIE bit is set both output compare
features may trigger interrupt requests. If only
one is needed in the application, the interrupt
routine software needs to discard the unwanted
compare interrupt. This can be done by check-
ing the OCF1 and OCF2 flags and resetting
them both.
Forced Compare Output capability
When the FOLVi bit is set by software, the OLVLi
bit is copied to the OCMPi pin. The OLVi bit has to
be toggled in order to toggle the OCMPi pin when
it is enabled (OCiE bit = 1). The OCFi bit is then
not set by hardware, and thus no interrupt request
is generated.
2. If the OCiE bit is not set, the OCMPi pin is a
general I/O port and the OLVLi bit will not
appear when a match is found but an interrupt
could be generated if the OCIE bit is set.
The FOLVLi bits have no effect in both one pulse
mode and PWM mode.
3. When the timer clock is f
/2, OCFi and
CPU
OCMPi are set while the counter value equals
the OCiR register value (see Figure 8). This
behaviour is the same in OPM or PWM mode.
When the timer clock is f
/4, f
/8 or f
/
CPU
CPU
CPU
8000, OCFi and OCMPi are set while the coun-
ter value equals the OCiR register value plus 1
(see Figure 9).
4. The output compare functions can be used both
for generating external events on the OCMPi
pins even if the input capture mode is also
used.
5. The value in the 8-bit OCiR register and the
OLVi bit should be changed after each suc-
cessful comparison in order to control an output
Figure 65. Output Compare Block Diagram
8 BIT FREE RUNNING
OC1E
CC1 CC0
OC2E
COUNTER
(Control Register 2) CR2
8-bit
(Control Register 1) CR1
OUTPUT COMPARE
CIRCUIT
Latch
1
OCIE
FOLV2 FOLV1OLVL2
OLVL1
OCMP1
Pin
8-bit
8-bit
Latch
2
OCMP2
Pin
OC1R Register
OCF1
OCF2
0
0
0
OC2R Register
(Status Register) SR
100/263
ST72561
8-BIT TIMER (Cont’d)
Figure 66. Output Compare Timing Diagram, f
= f
/2
TIMER
CPU
f
CLOCK
CPU
TIMER CLOCK
COUNTER REGISTER
CF
D0
D1
D2
D4
D3
OUTPUT COMPARE REGISTER i (OCRi)
D3
OUTPUT COMPARE FLAG i (OCFi)
OCMPi PIN (OLVLi = 1)
Figure 67. Output Compare Timing Diagram, f
= f
/4
TIMER
CPU
f
CLOCK
CPU
TIMER CLOCK
COUNTER REGISTER
CF
D0
D1
D2
D4
D3
OUTPUT COMPARE REGISTER i (OCRi)
D3
COMPARE REGISTER i LATCH
OUTPUT COMPARE FLAG i (OCFi)
OCMPi PIN (OLVLi = 1)
101/263
ST72561
8-BIT TIMER (Cont’d)
10.5.3.4 One Pulse Mode
Clearing the Input Capture interrupt request (that
is, clearing the ICFi bit) is done in two steps:
One Pulse mode enables the generation of a
pulse when an external event occurs. This mode is
selected via the OPM bit in the CR2 register.
1. Reading the SR register while the ICFi bit is set.
2. An access (read or write) to the ICiLR register.
The one pulse mode uses the Input Capture1
function and the Output Compare1 function.
The OC1R register value required for a specific
timing application can be calculated using the fol-
lowing formula:
Procedure:
t * fCPU
To use one pulse mode:
- 5
OCiR Value =
1. Load the OC1R register with the value corre-
sponding to the length of the pulse (see the for-
mula in the opposite column).
PRESC
Where:
t
= Pulse period (in seconds)
2. Select the following in the CR1 register:
f
= PLL output x2 clock frequency in hertz
CPU
– Using the OLVL1 bit, select the level to be ap-
plied to the OCMP1 pin after the pulse.
(or f
/2 if PLL is not enabled)
OSC
= Timer prescaler factor (2, 4, 8 or 8000
depending on the CC[1:0] bits, see Ta-
ble 1)
PRESC
– Using the OLVL2 bit, select the level to be ap-
plied to the OCMP1 pin during the pulse.
– Select the edge of the active transition on the
ICAP1 pin with the IEDG1 bit (the ICAP1 pin
must be configured as floating input).
When the value of the counter is equal to the value
of the contents of the OC1R register, the OLVL1
bit is output on the OCMP1 pin, (See Figure 10).
3. Select the following in the CR2 register:
– Set the OC1E bit, the OCMP1 pin is then ded-
icated to the Output Compare 1 function.
Notes:
– Set the OPM bit.
1. The OCF1 bit cannot be set by hardware in one
pulse mode but the OCF2 bit can generate an
Output Compare interrupt.
– Select the timer clock CC[1:0] (see Table 1).
2. When the Pulse Width Modulation (PWM) and
One Pulse Mode (OPM) bits are both set, the
PWM mode is the only active one.
One pulse mode cycle
ICR1 = Counter
When
3. If OLVL1=OLVL2 a continuous signal will be
seen on the OCMP1 pin.
OCMP1 = OLVL2
event occurs
on ICAP1
Counter is reset
4. The ICAP1 pin can not be used to perform input
capture. The ICAP2 pin can be used to perform
input capture (ICF2 can be set and IC2R can be
loaded) but the user must take care that the
counter is reset each time a valid edge occurs
on the ICAP1 pin and ICF1 can also generates
interrupt if ICIE is set.
to FCh
ICF1 bit is set
When
Counter
OCMP1 = OLVL1
= OC1R
5. When one pulse mode is used OC1R is dedi-
cated to this mode. Nevertheless OC2R and
OCF2 can be used to indicate a period of time
has been elapsed but cannot generate an out-
put waveform because the level OLVL2 is dedi-
cated to the one pulse mode.
Then, on a valid event on the ICAP1 pin, the coun-
ter is initialized to FCh and OLVL2 bit is loaded on
the OCMP1 pin, the ICF1 bit is set and the value
FFFDh is loaded in the IC1R register.
Because the ICF1 bit is set when an active edge
occurs, an interrupt can be generated if the ICIE
bit is set.
102/263
ST72561
8-BIT TIMER (Cont’d)
Figure 68. One Pulse Mode Timing Example
D3
FC
F8
IC1R
FC
FD
FE
D0
D1
D2
D3
FD
F8
COUNTER
ICAP1
OLVL2
OLVL1
OLVL2
OCMP1
compare1
Note: IEDG1 = 1, OC1R = D0h, OLVL1 = 0, OLVL2 = 1
Figure 69. Pulse Width Modulation Mode Timing Example
D0
D1
D2
E2
FC
FC
FD
FE
E2
COUNTER
OCMP1
OLVL2
OLVL1
OLVL2
compare2
compare1
compare2
Note: OC1R = D0h, OC2R = E2, OLVL1 = 0, OLVL2 = 1
103/263
ST72561
8-BIT TIMER (Cont’d)
10.5.3.5 Pulse Width Modulation Mode
If OLVL1 = 1 and OLVL2 = 0 the length of the pos-
itive pulse is the difference between the OC2R and
OC1R registers.
Pulse Width Modulation (PWM) mode enables the
generation of a signal with a frequency and pulse
length determined by the value of the OC1R and
OC2R registers.
If OLVL1 = OLVL2 a continuous signal will be
seen on the OCMP1 pin.
Pulse Width Modulation mode uses the complete
Output Compare 1 function plus the OC2R regis-
ter, and so this functionality can not be used when
PWM mode is activated.
The OCiR register value required for a specific tim-
ing application can be calculated using the follow-
ing formula:
t * fCPU
- 5
OCiR Value =
In PWM mode, double buffering is implemented on
the output compare registers. Any new values writ-
ten in the OC1R and OC2R registers are taken
into account only at the end of the PWM period
(OC2) to avoid spikes on the PWM output pin
(OCMP1).
PRESC
Where:
t
= Signal or pulse period (in seconds)
f
= PLL output x2 clock frequency in hertz
CPU
(or f
/2 if PLL is not enabled)
OSC
Procedure
= Timer prescaler factor (2, 4, 8 or 8000
depending on CC[1:0] bits, see Table 1)
PRESC
To use pulse width modulation mode:
1. Load the OC2R register with the value corre-
sponding to the period of the signal using the
formula in the opposite column.
The Output Compare 2 event causes the counter
to be initialized to FCh (See Figure 11)
2. Load the OC1R register with the value corre-
sponding to the period of the pulse if
(OLVL1 = 0 and OLVL2 = 1) using the formula
in the opposite column.
Notes:
1. The OCF1 and OCF2 bits cannot be set by
hardware in PWM mode therefore the Output
Compare interrupt is inhibited.
3. Select the following in the CR1 register:
2. The ICF1 bit is set by hardware when the coun-
ter reaches the OC2R value and can produce a
timer interrupt if the ICIE bit is set and the I bit is
cleared.
– Using the OLVL1 bit, select the level to be ap-
plied to the OCMP1 pin after a successful
comparison with the OC1R register.
– Using the OLVL2 bit, select the level to be ap-
plied to the OCMP1 pin after a successful
comparison with the OC2R register.
3. In PWM mode the ICAP1 pin can not be used
to perform input capture because it is discon-
nected to the timer. The ICAP2 pin can be used
to perform input capture (ICF2 can be set and
IC2R can be loaded) but the user must take
care that the counter is reset each period and
ICF1 can also generates interrupt if ICIE is set.
4. Select the following in the CR2 register:
– Set OC1E bit: the OCMP1 pin is then dedicat-
ed to the output compare 1 function.
– Set the PWM bit.
4. When the Pulse Width Modulation (PWM) and
One Pulse Mode (OPM) bits are both set, the
PWM mode is the only active one.
– Select the timer clock (CC[1:0]) (see Table 1).
Pulse Width Modulation cycle
When
Counter
= OC1R
OCMP1 = OLVL1
OCMP1 = OLVL2
When
Counter
= OC2R
Counter is reset
to FCh
ICF1 bit is set
104/263
ST72561
8-BIT TIMER (Cont’d)
10.5.4 Low Power Modes
Mode
Description
No effect on 8-bit Timer.
Timer interrupts cause the device to exit from WAIT mode.
WAIT
8-bit Timer registers are frozen.
In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous
count when the MCU is woken up by an interrupt with “exit from HALT mode” capability or from the counter
reset value when the MCU is woken up by a RESET.
HALT
If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is armed. Consequent-
ly, when the MCU is woken up by an interrupt with “exit from HALT mode” capability, the ICFi bit is set, and
the counter value present when exiting from HALT mode is captured into the ICiR register.
10.5.5 Interrupts
Enable
Control from
Bit
Exit
Exit
from
Halt
Event
Flag
Interrupt Event
Wait
Input Capture 1 event/Counter reset in PWM mode
Input Capture 2 event
ICF1
ICF2
ICIE
Output Compare 1 event (not available in PWM mode)
Output Compare 2 event (not available in PWM mode)
Timer Overflow event
OCF1
OCF2
TOF
Yes
No
OCIE
TOIE
Note: The 8-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts chapter).
These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask
in the CC register is reset (RIM instruction).
10.5.6 Summary of Timer modes
AVAILABLE RESOURCES
MODES
Input Capture 1
Input Capture 2
Output Compare 1 Output Compare 2
Input Capture (1 and/or 2)
Output Compare (1 and/or 2)
One Pulse Mode
Yes
Yes
Yes
No
Yes
1)
3)
2)
Not Recommended
Not Recommended
Partially
No
No
PWM Mode
1) See note 4 in “One Pulse Mode” on page 11
2) See note 5 in “One Pulse Mode” on page 11
3) See note 4 in “Pulse Width Modulation Mode” on page 13
105/263
ST72561
8-BIT TIMER (Cont’d)
10.5.7 Register Description
Bit 4 = FOLV2 Forced Output Compare 2.
This bit is set and cleared by software.
0: No effect on the OCMP2 pin.
1:Forces the OLVL2 bit to be copied to the
OCMP2 pin, if the OC2E bit is set and even if
there is no successful comparison.
Each Timer is associated with three control and
status registers, and with six data registers (8-bit
values) relating to the two input captures, the two
output compares, the counter and the alternate
counter.
Bit 3 = FOLV1 Forced Output Compare 1.
This bit is set and cleared by software.
0: No effect on the OCMP1 pin.
CONTROL REGISTER 1 (CR1)
Read/Write
1: Forces OLVL1 to be copied to the OCMP1 pin, if
the OC1E bit is set and even if there is no suc-
cessful comparison.
Reset Value: 0000 0000 (00h)
7
0
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
Bit 2 = OLVL2 Output Level 2.
This bit is copied to the OCMP2 pin whenever a
successful comparison occurs with the OC2R reg-
ister and OCxE is set in the CR2 register. This val-
ue is copied to the OCMP1 pin in One Pulse Mode
and Pulse Width Modulation mode.
Bit 7 = ICIE Input Capture Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the
ICF1 or ICF2 bit of the SR register is set.
Bit 6 = OCIE Output Compare Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the
OCF1 or OCF2 bit of the SR register is set.
Bit 1 = IEDG1 Input Edge 1.
This bit determines which type of level transition
on the ICAP1 pin will trigger the capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
Bit 5 = TOIE Timer Overflow Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is enabled whenever the TOF
bit of the SR register is set.
Bit 0 = OLVL1 Output Level 1.
The OLVL1 bit is copied to the OCMP1 pin when-
ever a successful comparison occurs with the
OC1R register and the OC1E bit is set in the CR2
register.
106/263
ST72561
8-BIT TIMER (Cont’d)
CONTROL REGISTER 2 (CR2)
Read/Write
Bit 4 = PWM Pulse Width Modulation.
0: PWM mode is not active.
1: PWM mode is active, the OCMP1 pin outputs a
programmable cyclic signal; the length of the
pulse depends on the value of OC1R register;
the period depends on the value of OC2R regis-
ter.
Reset Value: 0000 0000 (00h)
7
0
0
OC1E OC2E OPM PWM CC1 CC0 IEDG2
Bit 3, 2 = CC[1:0] Clock Control.
Bit 7 = OC1E Output Compare 1 Pin Enable.
The timer clock mode depends on these bits:
This bit is used only to output the signal from the
timer on the OCMP1 pin (OLV1 in Output Com-
pare mode, both OLV1 and OLV2 in PWM and
one-pulse mode). Whatever the value of the OC1E
bit, the Output Compare 1 function of the timer re-
mains active.
Table 19. Clock Control Bits
Timer Clock
CC1
CC0
f
f
f
/ 4
/ 2
/ 8
0
0
1
1
0
1
0
1
CPU
CPU
CPU
0: OCMP1 pin alternate function disabled (I/O pin
free for general-purpose I/O).
1: OCMP1 pin alternate function enabled.
f
/ 8000*
OSC2
* Not available in Slow mode in ST72F561.
Bit 6 = OC2E Output Compare 2 Pin Enable.
This bit is used only to output the signal from the
timer on the OCMP2 pin (OLV2 in Output Com-
pare mode). Whatever the value of the OC2E bit,
the Output Compare 2 function of the timer re-
mains active.
0: OCMP2 pin alternate function disabled (I/O pin
free for general-purpose I/O).
1: OCMP2 pin alternate function enabled.
Bit 1 = IEDG2 Input Edge 2.
This bit determines which type of level transition
on the ICAP2 pin will trigger the capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
Bit 0 = Reserved, must be kept at 0.
Bit 5 = OPM One Pulse Mode.
0: One Pulse Mode is not active.
1: One Pulse Mode is active, the ICAP1 pin can be
used to trigger one pulse on the OCMP1 pin; the
active transition is given by the IEDG1 bit. The
length of the generated pulse depends on the
contents of the OC1R register.
107/263
ST72561
8-BIT TIMER (Cont’d)
CONTROL/STATUS REGISTER (CSR)
Read Only (except bit 2 R/W)
Reset Value: 0000 0000 (00h)
7
Note: Reading or writing the ACTR register does
not clear TOF.
Bit 4 = ICF2 Input Capture Flag 2.
0: No input capture (reset value).
1: An input capture has occurred on the ICAP2
pin. To clear this bit, first read the SR register,
then read or write the IC2R register.
0
0
ICF1 OCF1 TOF ICF2 OCF2 TIMD
0
Bit 7 = ICF1 Input Capture Flag 1.
0: No input capture (reset value).
Bit 3 = OCF2 Output Compare Flag 2.
0: No match (reset value).
1: The content of the free running counter has
matched the content of the OC2R register. To
clear this bit, first read the SR register, then read
or write the OC2R register.
1: An input capture has occurred on the ICAP1 pin
or the counter has reached the OC2R value in
PWM mode. To clear this bit, first read the SR
register, then read or write the the IC1R register.
Bit 6 = OCF1 Output Compare Flag 1.
0: No match (reset value).
1: The content of the free running counter has
matched the content of the OC1R register. To
clear this bit, first read the SR register, then read
or write the OC1R register.
Bit 2 = TIMD Timer disable.
This bit is set and cleared by software. When set, it
freezes the timer prescaler and counter and disa-
bled the output functions (OCMP1 and OCMP2
pins) to reduce power consumption. Access to the
timer registers is still available, allowing the timer
configuration to be changed, or the counter reset,
while it is disabled.
Bit 5 = TOF Timer Overflow Flag.
0: No timer overflow (reset value).
1:The free running counter rolled over from FFh to
00h. To clear this bit, first read the SR register,
then read or write the CTR register.
0: Timer enabled
1: Timer prescaler, counter and outputs disabled
Bits 1:0 = Reserved, must be kept cleared.
108/263
ST72561
8-BIT TIMER (Cont’d)
INPUT CAPTURE 1 REGISTER (IC1R)
COUNTER REGISTER (CTR)
Read Only
Reset Value: Undefined
Read Only
Reset Value: 1111 1100 (FCh)
This is an 8-bit read only register that contains the
counter value (transferred by the input capture 1
event).
This is an 8-bit register that contains the counter
value. A write to this register resets the counter.
An access to this register after accessing the CSR
register clears the TOF bit.
7
0
7
0
MSB
LSB
MSB
LSB
OUTPUT COMPARE 1 REGISTER (OC1R)
ALTERNATE COUNTER REGISTER (ACTR)
Read/Write
Reset Value: 0000 0000 (00h)
Read Only
Reset Value: 1111 1100 (FCh)
This is an 8-bit register that contains the value to
be compared to the CTR register.
This is an 8-bit register that contains the counter
value. A write to this register resets the counter.
An access to this register after an access to CSR
register does not clear the TOF bit in the CSR reg-
ister.
7
0
MSB
LSB
7
0
MSB
LSB
OUTPUT COMPARE 2 REGISTER (OC2R)
Read/Write
Reset Value: 0000 0000 (00h)
This is an 8-bit register that contains the value to
be compared to the CTR register.
INPUT CAPTURE 2 REGISTER (IC2R)
Read Only
Reset Value: Undefined
7
0
This is an 8-bit read only register that contains the
counter value (transferred by the Input Capture 2
event).
MSB
LSB
7
0
MSB
LSB
109/263
ST72561
8-BIT TIMER (Cont’d)
10.5.8 8-bit Timer Register Map
Address
(Hex.)
Register
Name
7
6
5
4
3
2
1
0
3C
3D
3E
3F
40
41
42
43
44
CR2
OC1E
ICIE
OC2E
OCIE
OCF1
OPM
TOIE
TOF
PWM
FOLV2
ICF2
CC1
FOLV1
OCF2
CC0
OLVL2
TIMD
IEDG2
IEDG1
0
CR1
OLVL1
CSR
ICF1
MSB
MSB
MSB
MSB
MSB
MSB
IC1R
OC1R
CTR
LSB
LSB
LSB
LSB
LSB
LSB
ACTR
IC2R
OC2R
110/263
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ON-CHIP PERIPHERALS (cont’d)
10.6 SERIAL PERIPHERAL INTERFACE (SPI)
10.6.1 Introduction
10.6.3 General Description
The Serial Peripheral Interface (SPI) allows full-
duplex, synchronous, serial communication with
external devices. An SPI system may consist of a
master and one or more slaves or a system in
which devices may be either masters or slaves.
Figure 1 on page 3 shows the serial peripheral in-
terface (SPI) block diagram. There are three regis-
ters:
– SPI Control Register (SPICR)
– SPI Control/Status Register (SPICSR)
– SPI Data Register (SPIDR)
10.6.2 Main Features
■ Full duplex synchronous transfers (on three
The SPI is connected to external devices through
four pins:
lines)
■ Simplex synchronous transfers (on two lines)
■ Master or slave operation
– MISO: Master In / Slave Out data
– MOSI: Master Out / Slave In data
■ 6 master mode frequencies (f
/4 max.)
CPU
– SCK: Serial Clock out by SPI masters and in-
put by SPI slaves
■ f
/2 max. slave mode frequency (see note)
CPU
■ SS Management by software or hardware
■ Programmable clock polarity and phase
■ End of transfer interrupt flag
– SS: Slave select:
This input signal acts as a ‘chip select’ to let
the SPI master communicate with slaves indi-
vidually and to avoid contention on the data
lines. Slave SS inputs can be driven by stand-
ard I/O ports on the master Device.
■ Write collision, Master Mode Fault and Overrun
flags
Note: In slave mode, continuous transmission is
not possible at maximum frequency due to the
software overhead for clearing status flags and to
initiate the next transmission sequence.
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SERIAL PERIPHERAL INTERFACE (SPI) (cont’d)
Figure 70. Serial Peripheral Interface Block Diagram
Data/Address Bus
Read
SPIDR
Interrupt
request
Read Buffer
MOSI
7
0
SPICSR
MISO
8-Bit Shift Register
SPIF WCOL OVR MODF
0
SOD SSM SSI
Write
SOD
bit
1
SS
SPI
STATE
0
SCK
CONTROL
7
0
SPICR
MSTR
SPR0
SPIE SPE SPR2
CPOL CPHA SPR1
MASTER
CONTROL
SERIAL CLOCK
GENERATOR
SS
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SERIAL PERIPHERAL INTERFACE (Cont’d)
10.6.3.1 Functional Description
the MISO pin. This implies full duplex communica-
tion with both data out and data in synchronized
with the same clock signal (which is provided by
the master device via the SCK pin).
A basic example of interconnections between a
single master and a single slave is illustrated in
Figure 2.
To use a single data line, the MISO and MOSI pins
must be connected at each node (in this case only
simplex communication is possible).
The MOSI pins are connected together and the
MISO pins are connected together. In this way
data is transferred serially between master and
slave (most significant bit first).
Four possible data/clock timing relationships may
be chosen (see Figure 5 on page 7) but master
and slave must be programmed with the same tim-
ing mode.
The communication is always initiated by the mas-
ter. When the master device transmits data to a
slave device via MOSI pin, the slave device re-
sponds by sending data to the master device via
Figure 71. Single Master/ Single Slave Application
SLAVE
MASTER
MSBit
LSBit
MSBit
LSBit
MISO
MOSI
MISO
MOSI
8-BIT SHIFT REGISTER
8-BIT SHIFT REGISTER
SPI
CLOCK
GENERATOR
SCK
SS
SCK
SS
+5V
Not used if SS is managed
by software
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SERIAL PERIPHERAL INTERFACE (Cont’d)
10.6.3.2 Slave Select Management
In Slave Mode:
As an alternative to using the SS pin to control the
Slave Select signal, the application can choose to
manage the Slave Select signal by software. This
is configured by the SSM bit in the SPICSR regis-
ter (see Figure 4).
There are two cases depending on the data/clock
timing relationship (see Figure 3):
If CPHA = 1 (data latched on second clock edge):
– SS internal must be held low during the entire
transmission. This implies that in single slave
applications the SS pin either can be tied to
In software management, the external SS pin is
free for other application uses and the internal SS
signal level is driven by writing to the SSI bit in the
SPICSR register.
V
, or made free for standard I/O by manag-
SS
ing the SS function by software (SSM = 1 and
SSI = 0 in the in the SPICSR register)
If CPHA = 0 (data latched on first clock edge):
In Master mode:
– SS internal must be held low during byte
transmission and pulled high between each
byte to allow the slave to write to the shift reg-
ister. If SS is not pulled high, a Write Collision
error will occur when the slave writes to the
shift register (see Section 0.1.5.3).
– SS internal must be held high continuously
Figure 72. Generic SS Timing Diagram
Byte 3
Byte 2
MOSI/MISO
Master SS
Byte 1
Slave SS
(if CPHA = 0)
Slave SS
(if CPHA = 1)
Figure 73. Hardware/Software Slave Select Management
SSM bit
SSI bit
1
0
SS internal
SS external pin
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SERIAL PERIPHERAL INTERFACE (Cont’d)
10.6.3.3 Master Mode Operation
Note: While the SPIF bit is set, all writes to the
SPIDR register are inhibited until the SPICSR reg-
ister is read.
In master mode, the serial clock is output on the
SCK pin. The clock frequency, polarity and phase
are configured by software (refer to the description
of the SPICSR register).
10.6.3.5 Slave Mode Operation
In slave mode, the serial clock is received on the
SCK pin from the master device.
Note: The idle state of SCK must correspond to
the polarity selected in the SPICSR register (by
pulling up SCK if CPOL = 1 or pulling down SCK if
CPOL = 0).
To operate the SPI in slave mode:
1. Write to the SPICSR register to perform the fol-
lowing actions:
How to operate the SPI in master mode
– Select the clock polarity and clock phase by
configuring the CPOL and CPHA bits (see
Figure 5).
To operate the SPI in master mode, perform the
following steps in order:
Note: The slave must have the same CPOL
1. Write to the SPICR register:
and CPHA settings as the master.
– Select the clock frequency by configuring the
– Manage the SS pin as described in Section
0.1.3.2 and Figure 3. If CPHA = 1 SS must be
held low continuously. If CPHA = 0 SS must
be held low during byte transmission and
pulled up between each byte to let the slave
write in the shift register.
SPR[2:0] bits.
– Select the clock polarity and clock phase by
configuring the CPOL and CPHA bits. Figure
5 shows the four possible configurations.
Note: The slave must have the same CPOL
and CPHA settings as the master.
2. Write to the SPICR register to clear the MSTR
bit and set the SPE bit to enable the SPI I/O
functions.
2. Write to the SPICSR register:
– Either set the SSM bit and set the SSI bit or
clear the SSM bit and tie the SS pin high for
the complete byte transmit sequence.
10.6.3.6 Slave Mode Transmit Sequence
When software writes to the SPIDR register, the
data byte is loaded into the 8-bit shift register and
then shifted out serially to the MISO pin most sig-
nificant bit first.
3. Write to the SPICR register:
– Set the MSTR and SPE bits
Note: MSTR and SPE bits remain set only if
SS is high).
The transmit sequence begins when the slave de-
vice receives the clock signal and the most signifi-
cant bit of the data on its MOSI pin.
Important note: if the SPICSR register is not writ-
ten first, the SPICR register setting (MSTR bit)
may be not taken into account.
When data transfer is complete:
– The SPIF bit is set by hardware.
The transmit sequence begins when software
writes a byte in the SPIDR register.
10.6.3.4 Master Mode Transmit Sequence
– An interrupt request is generated if SPIE bit is
set and interrupt mask in the CCR register is
cleared.
When software writes to the SPIDR register, the
data byte is loaded into the 8-bit shift register and
then shifted out serially to the MOSI pin most sig-
nificant bit first.
Clearing the SPIF bit is performed by the following
software sequence:
When data transfer is complete:
– The SPIF bit is set by hardware.
1. An access to the SPICSR register while the
SPIF bit is set
2. A write or a read to the SPIDR register
– An interrupt request is generated if the SPIE
bit is set and the interrupt mask in the CCR
register is cleared.
Notes: While the SPIF bit is set, all writes to the
SPIDR register are inhibited until the SPICSR reg-
ister is read.
Clearing the SPIF bit is performed by the following
software sequence:
The SPIF bit can be cleared during a second
transmission; however, it must be cleared before
the second SPIF bit in order to prevent an Overrun
condition (see Section 0.1.5.2).
1. An access to the SPICSR register while the
SPIF bit is set
2. A read to the SPIDR register
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SERIAL PERIPHERAL INTERFACE (Cont’d)
10.6.4 Clock Phase and Clock Polarity
Figure 5 shows an SPI transfer with the four com-
binations of the CPHA and CPOL bits. The dia-
gram may be interpreted as a master or slave tim-
ing diagram where the SCK pin, the MISO pin and
the MOSI pin are directly connected between the
master and the slave device.
Four possible timing relationships may be chosen
by software, using the CPOL and CPHA bits (See
Figure 5).
Note: The idle state of SCK must correspond to
the polarity selected in the SPICSR register (by
pulling up SCK if CPOL = 1 or pulling down SCK if
CPOL = 0).
Note: If CPOL is changed at the communication
byte boundaries, the SPI must be disabled by re-
setting the SPE bit.
The combination of the CPOL clock polarity and
CPHA (clock phase) bits selects the data capture
clock edge.
Figure 74. Data Clock Timing Diagram
CPHA = 1
SCK
(CPOL = 1)
SCK
(CPOL = 0)
Bit 4
Bit 4
Bit3
Bit3
Bit 2
Bit 2
Bit 1
Bit 1
LSBit
LSBit
MSBit
MSBit
Bit 6
Bit 6
Bit 5
Bit 5
MISO
(from master)
MOSI
(from slave)
SS
(to slave)
CAPTURE STROBE
CPHA = 0
SCK
(CPOL = 1)
SCK
(CPOL = 0)
Bit 4
Bit 4
Bit3
Bit3
Bit 2
Bit 2
Bit 1
Bit 1
LSBit
LSBit
MISO
(from master)
MSBit
Bit 6
Bit 6
Bit 5
Bit 5
MOSI
(from slave)
MSBit
SS
(to slave)
CAPTURE STROBE
Note: This figure should not be used as a replacement for parametric information.
Refer to the Electrical Characteristics chapter.
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SERIAL PERIPHERAL INTERFACE (Cont’d)
10.6.5 Error Flags
10.6.5.2 Overrun Condition (OVR)
10.6.5.1 Master Mode Fault (MODF)
An overrun condition occurs when the master de-
vice has sent a data byte and the slave device has
not cleared the SPIF bit issued from the previously
transmitted byte.
Master mode fault occurs when the master de-
vice’s SS pin is pulled low.
When a Master mode fault occurs:
When an Overrun occurs:
– The MODF bit is set and an SPI interrupt re-
quest is generated if the SPIE bit is set.
– The OVR bit is set and an interrupt request is
generated if the SPIE bit is set.
– The SPE bit is reset. This blocks all output
from the device and disables the SPI periph-
eral.
In this case, the receiver buffer contains the byte
sent after the SPIF bit was last cleared. A read to
the SPIDR register returns this byte. All other
bytes are lost.
– The MSTR bit is reset, thus forcing the device
into slave mode.
The OVR bit is cleared by reading the SPICSR
register.
Clearing the MODF bit is done through a software
sequence:
10.6.5.3 Write Collision Error (WCOL)
1. A read access to the SPICSR register while the
MODF bit is set.
A write collision occurs when the software tries to
write to the SPIDR register while a data transfer is
taking place with an external device. When this
happens, the transfer continues uninterrupted and
the software write will be unsuccessful.
2. A write to the SPICR register.
Notes: To avoid any conflicts in an application
with multiple slaves, the SS pin must be pulled
high during the MODF bit clearing sequence. The
SPE and MSTR bits may be restored to their orig-
inal state during or after this clearing sequence.
Write collisions can occur both in master and slave
mode. See also Section 0.1.3.2 Slave Select Man-
agement.
Hardware does not allow the user to set the SPE
and MSTR bits while the MODF bit is set except in
the MODF bit clearing sequence.
Note: A "read collision" will never occur since the
received data byte is placed in a buffer in which
access is always synchronous with the CPU oper-
ation.
In a slave device, the MODF bit can not be set, but
in a multimaster configuration the device can be in
slave mode with the MODF bit set.
The WCOL bit in the SPICSR register is set if a
write collision occurs.
The MODF bit indicates that there might have
been a multimaster conflict and allows software to
handle this using an interrupt routine and either
perform a reset or return to an application default
state.
No SPI interrupt is generated when the WCOL bit
is set (the WCOL bit is a status flag only).
Clearing the WCOL bit is done through a software
sequence (see Figure 6).
Figure 75. Clearing the WCOL Bit (Write Collision Flag) Software Sequence
Clearing sequence after SPIF = 1 (end of a data byte transfer)
Read SPICSR
1st Step
RESULT
SPIF = 0
WCOL = 0
2nd Step
Read SPIDR
Clearing sequence before SPIF = 1 (during a data byte transfer)
Read SPICSR
1st Step
Note: Writing to the SPIDR regis-
ter instead of reading it does not
reset the WCOL bit
RESULT
2nd Step
Read SPIDR
WCOL = 0
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ST72561
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.6.5.4 Single Master and Multimaster
Configurations
For more security, the slave device may respond
to the master with the received data byte. Then the
master will receive the previous byte back from the
slave device if all MISO and MOSI pins are con-
nected and the slave has not written to its SPIDR
register.
There are two types of SPI systems:
– Single Master System
– Multimaster System
Other transmission security methods can use
ports for handshake lines or data bytes with com-
mand fields.
Single Master System
A typical single master system may be configured
using a device as the master and four devices as
slaves (see Figure 7).
Multimaster System
A multimaster system may also be configured by
the user. Transfer of master control could be im-
plemented using a handshake method through the
I/O ports or by an exchange of code messages
through the serial peripheral interface system.
The master device selects the individual slave de-
vices by using four pins of a parallel port to control
the four SS pins of the slave devices.
The SS pins are pulled high during reset since the
master device ports will be forced to be inputs at
that time, thus disabling the slave devices.
The multimaster system is principally handled by
the MSTR bit in the SPICR register and the MODF
bit in the SPICSR register.
Note: To prevent a bus conflict on the MISO line,
the master allows only one active slave device
during a transmission.
Figure 76. Single Master / Multiple Slave Configuration
SS
SS
SS
SS
SCK
SCK
Slave
SCK
Slave
SCK
Slave
Slave
Device
Device
Device
Device
MOSI MISO
MOSI MISO
MOSI MISO
MOSI MISO
MOSI MISO
SCK
Master
Device
5V
SS
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SERIAL PERIPHERAL INTERFACE (Cont’d)
10.6.6 Low Power Modes
the SPI from HALT mode state to normal state. If
the SPI exits from Slave mode, it returns to normal
state immediately.
Mode
Description
No effect on SPI.
Caution: The SPI can wake up the device from
HALT mode only if the Slave Select signal (exter-
nal SS pin or the SSI bit in the SPICSR register) is
low when the device enters HALT mode. So, if
Slave selection is configured as external (see Sec-
tion 0.1.3.2), make sure the master drives a low
level on the SS pin when the slave enters HALT
mode.
WAIT
SPI interrupt events cause the device to exit
from WAIT mode.
SPI registers are frozen.
In HALT mode, the SPI is inactive. SPI oper-
ation resumes when the device is woken up
by an interrupt with “exit from HALT mode”
capability. The data received is subsequently
read from the SPIDR register when the soft-
ware is running (interrupt vector fetching). If
several data are received before the wake-
up event, then an overrun error is generated.
This error can be detected after the fetch of
the interrupt routine that woke up the Device.
HALT
10.6.7 Interrupts
Enable
Control from
Bit
Exit
Exit
from
Halt
Event
Flag
Interrupt Event
Wait
SPI End of
Transfer Event
SPIF
Yes
10.6.6.1 Using the SPI to wake up the device
from Halt mode
Master Mode
Fault Event
SPIE
Yes
MODF
OVR
No
In slave configuration, the SPI is able to wake up
the device from HALT mode through a SPIF inter-
rupt. The data received is subsequently read from
the SPIDR register when the software is running
(interrupt vector fetch). If multiple data transfers
have been performed before software clears the
SPIF bit, then the OVR bit is set by hardware.
Overrun Error
Note: The SPI interrupt events are connected to
the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding
Enable Control Bit is set and the interrupt mask in
the CC register is reset (RIM instruction).
Note: When waking up from HALT mode, if the
SPI remains in Slave mode, it is recommended to
perform an extra communications cycle to bring
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ST72561
10.6.8 Register Description
CONTROL REGISTER (SPICR)
Read/Write
Bit 3 = CPOL Clock Polarity
This bit is set and cleared by software. This bit de-
termines the idle state of the serial Clock. The
CPOL bit affects both the master and slave
modes.
Reset Value: 0000 xxxx (0xh)
7
0
0: SCK pin has a low level idle state
1: SCK pin has a high level idle state
SPIE
SPE SPR2 MSTR CPOL CPHA SPR1 SPR0
Note: If CPOL is changed at the communication
byte boundaries, the SPI must be disabled by re-
setting the SPE bit.
Bit 7 = SPIE Serial Peripheral Interrupt Enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SPI interrupt is generated whenever an End
of Transfer event, Master Mode Fault or Over-
run error occurs (SPIF = 1, MODF = 1 or
OVR = 1 in the SPICSR register)
Bit 2 = CPHA Clock Phase
This bit is set and cleared by software.
0: The first clock transition is the first data capture
edge.
1: The second clock transition is the first capture
edge.
Bit 6 = SPE Serial Peripheral Output Enable
This bit is set and cleared by software. It is also
cleared by hardware when, in master mode,
SS = 0 (see Section 0.1.5.1 Master Mode Fault
(MODF)). The SPE bit is cleared by reset, so the
SPI peripheral is not initially connected to the ex-
ternal pins.
Note: The slave must have the same CPOL and
CPHA settings as the master.
Bits 1:0 = SPR[1:0] Serial Clock Frequency
These bits are set and cleared by software. Used
with the SPR2 bit, they select the baud rate of the
SPI serial clock SCK output by the SPI in master
mode.
0: I/O pins free for general purpose I/O
1: SPI I/O pin alternate functions enabled
Note: These 2 bits have no effect in slave mode.
Bit 5 = SPR2 Divider Enable
Table 20. SPI Master Mode SCK Frequency
This bit is set and cleared by software and is
cleared by reset. It is used with the SPR[1:0] bits to
set the baud rate. Refer to Table 1 SPI Master
Mode SCK Frequency.
Serial Clock
SPR2
SPR1
SPR0
f
f
/4
/8
1
CPU
CPU
0
1
0
1
0
0: Divider by 2 enabled
1: Divider by 2 disabled
0
1
0
f
f
f
/16
/32
/64
CPU
CPU
CPU
Note: This bit has no effect in slave mode.
1
f
/128
CPU
Bit 4 = MSTR Master Mode
This bit is set and cleared by software. It is also
cleared by hardware when, in master mode,
SS = 0 (see Section 0.1.5.1 Master Mode Fault
(MODF)).
0: Slave mode
1: Master mode. The function of the SCK pin
changes from an input to an output and the func-
tions of the MISO and MOSI pins are reversed.
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SERIAL PERIPHERAL INTERFACE (Cont’d)
CONTROL/STATUS REGISTER (SPICSR)
Read/Write (some bits Read Only)
Reset Value: 0000 0000 (00h)
Bit 2 = SOD SPI Output Disable
This bit is set and cleared by software. When set, it
disables the alternate function of the SPI output
(MOSI in master mode / MISO in slave mode)
0: SPI output enabled (if SPE = 1)
7
0
SPIF WCOL OVR MODF
-
SOD
SSM
SSI
1: SPI output disabled
Bit 7 = SPIF Serial Peripheral Data Transfer Flag
(Read only)
Bit 1 = SSM SS Management
This bit is set and cleared by software. When set, it
disables the alternate function of the SPI SS pin
and uses the SSI bit value instead. See Section
0.1.3.2 Slave Select Management.
This bit is set by hardware when a transfer has
been completed. An interrupt is generated if
SPIE = 1 in the SPICR register. It is cleared by
a software sequence (an access to the SPICSR
register followed by a write or a read to the
SPIDR register).
0: Hardware management (SS managed by exter-
nal pin)
1: Software management (internal SS signal con-
trolled by SSI bit. External SS pin free for gener-
al-purpose I/O)
0: Data transfer is in progress or the flag has been
cleared.
1: Data transfer between the device and an exter-
nal device has been completed.
Bit 0 = SSI SS Internal Mode
Note: While the SPIF bit is set, all writes to the
SPIDR register are inhibited until the SPICSR reg-
ister is read.
This bit is set and cleared by software. It acts as a
‘chip select’ by controlling the level of the SS slave
select signal when the SSM bit is set.
0: Slave selected
Bit 6 = WCOL Write Collision status (Read only)
This bit is set by hardware when a write to the
SPIDR register is done during a transmit se-
quence. It is cleared by a software sequence (see
Figure 6).
0: No write collision occurred
1: A write collision has been detected
1: Slave deselected
DATA I/O REGISTER (SPIDR)
Read/Write
Reset Value: Undefined
7
0
D7
D6
D5
D4
D3
D2
D1
D0
Bit 5 = OVR SPI Overrun error (Read only)
This bit is set by hardware when the byte currently
being received in the shift register is ready to be
transferred into the SPIDR register while SPIF = 1
(See Section 0.1.5.2). An interrupt is generated if
SPIE = 1 in the SPICR register. The OVR bit is
cleared by software reading the SPICSR register.
0: No overrun error
The SPIDR register is used to transmit and receive
data on the serial bus. In a master device, a write
to this register will initiate transmission/reception
of another byte.
Notes: During the last clock cycle the SPIF bit is
set, a copy of the received data byte in the shift
register is moved to a buffer. When the user reads
the serial peripheral data I/O register, the buffer is
actually being read.
1: Overrun error detected
Bit 4 = MODF Mode Fault flag (Read only)
This bit is set by hardware when the SS pin is
pulled low in master mode (see Section 0.1.5.1
Master Mode Fault (MODF)). An SPI interrupt can
be generated if SPIE = 1 in the SPICR register.
This bit is cleared by a software sequence (An ac-
cess to the SPICSR register while MODF = 1 fol-
lowed by a write to the SPICR register).
While the SPIF bit is set, all writes to the SPIDR
register are inhibited until the SPICSR register is
read.
Warning: A write to the SPIDR register places
data directly into the shift register for transmission.
A read to the SPIDR register returns the value lo-
cated in the buffer and not the content of the shift
register (see Figure 1).
0: No master mode fault detected
1: A fault in master mode has been detected
Bit 3 = Reserved, must be kept cleared.
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ST72561
SERIAL PERIPHERAL INTERFACE (Cont’d)
Table 21. SPI Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
SPIDR
Reset Value
MSB
x
LSB
x
21
22
23
x
x
x
x
x
x
SPICR
Reset Value
SPIE
0
SPE
0
SPR2
0
MSTR
0
CPOL
x
CPHA
x
SPR1
x
SPR0
x
SPICSR
Reset Value
SPIF
0
WCOL
0
OVR
0
MODF
0
SOD
0
SSM
0
SSI
0
0
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10.7 LINSCI SERIAL COMMUNICATION INTERFACE (LIN MASTER/SLAVE)
10.7.1 Introduction
■ 6 interrupt sources
The Serial Communications Interface (SCI) offers
a flexible means of full-duplex data exchange with
external equipment requiring an industry standard
NRZ asynchronous serial data format. The SCI of-
fers a very wide range of baud rates using two
baud rate generator systems.
– Transmit data register empty
– Transmission complete
– Receive data register full
– Idle line received
– Overrun error
The LIN-dedicated features support the LIN (Local
Interconnect Network) protocol for both master
and slave nodes.
– Parity interrupt
■ Parity control:
– Transmits parity bit
This chapter is divided into SCI Mode and LIN
mode sections. For information on general SCI
communications, refer to the SCI mode section.
For LIN applications, refer to both the SCI mode
and LIN mode sections.
– Checks parity of received data byte
■ Reduced power consumption mode
10.7.3 LIN Features
– LIN Master
10.7.2 SCI Features
– 13-bit LIN Synch Break generation
– LIN Slave
■ Full duplex, asynchronous communications
■ NRZ standard format (Mark/Space)
– Automatic Header Handling
■ Independently programmable transmit and
receive baud rates up to 500K baud.
– Automatic baud rate resynchronization based
on recognition and measurement of the LIN
Synch Field (for LIN slave nodes)
■ Programmable data word length (8 or 9 bits)
■ Receive buffer full, Transmit buffer empty and
End of Transmission flags
■ 2 receiver wake-up modes:
– Address bit (MSB)
– Automatic baud rate adjustment (at CPU fre-
quency precision)
– 11-bit LIN Synch Break detection capability
– LIN Parity check on the LIN Identifier Field
(only in reception)
– Idle line
■ Mutingfunctionformultiprocessorconfigurations
– LIN Error management
– LIN Header Timeout
– Hot plugging support
■ Separate enable bits for Transmitter and
Receiver
■ Overrun, Noise and Frame error detection
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ST72561
LINSCI™ SERIAL COMMUNICATION INTERFACE (Cont’d)
10.7.4 General Description
– A conventional type for commonly-used baud
rates
The interface is externally connected to another
device by two pins:
– An extended type with a prescaler offering a very
wide range of baud rates even with non-standard
oscillator frequencies
– TDO: Transmit Data Output. When the transmit-
ter is disabled, the output pin returns to its I/O
port configuration. When the transmitter is ena-
bled and nothing is to be transmitted, the TDO
pin is at high level.
– A LIN baud rate generator with automatic resyn-
chronization
– RDI: Receive Data Input is the serial data input.
Oversampling techniques are used for data re-
covery by discriminating between valid incoming
data and noise.
Through these pins, serial data is transmitted and
received as characters comprising:
– An Idle Line prior to transmission or reception
– A start bit
– A data word (8 or 9 bits) least significant bit first
– A Stop bit indicating that the character is com-
plete
This interface uses three types of baud rate gener-
ator:
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ST72561
LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (Cont’d)
Figure 77. SCI Block Diagram (in Conventional Baud Rate Generator Mode)
Write
Read
(DATA REGISTER) SCIDR
Received Data Register (RDR)
Receive Shift Register
Transmit Data Register (TDR)
TDO
RDI
Transmit Shift Register
SCICR1
R8
SCID
PCE
WAKE
T8
M
PS PIE
WAKE
UP
UNIT
TRANSMIT
CONTROL
RECEIVER
CLOCK
RECEIVER
CONTROL
SCISR
SCICR2
OR/
LHE
TIE TCIE RIE ILIE TE RE RWU SBK
NF
TDRE
RDRF
IDLE
TC
FE
PE
SCI
INTERRUPT
CONTROL
TRANSMITTER
CLOCK
TRANSMITTER RATE
CONTROL
f
CPU
/PR
/16
SCIBRR
SCP1
SCT2
SCT1SCT0SCR2 SCR1SCR0
SCP0
RECEIVER RATE
CONTROL
CONVENTIONAL BAUD RATE GENERATOR
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ST72561
LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (Cont’d)
10.7.5 SCI Mode - Functional Description
Conventional Baud Rate Generator Mode
10.7.5.1 Serial Data Format
Word length may be selected as being either 8 or 9
bits by programming the M bit in the SCICR1 reg-
ister (see Figure 2).
The block diagram of the Serial Control Interface
in conventional baud rate generator mode is
shown in Figure 1.
The TDO pin is in low state during the start bit.
The TDO pin is in high state during the stop bit.
It uses four registers:
– 2 control registers (SCICR1 and SCICR2)
– A status register (SCISR)
An Idle character is interpreted as a continuous
logic high level for 10 (or 11) full bit times.
A Break character is a character with a sufficient
number of low level bits to break the normal data
format followed by an extra “1” bit to acknowledge
the start bit.
– A baud rate register (SCIBRR)
Extended Prescaler Mode
Two additional prescalers are available in extend-
ed prescaler mode. They are shown in Figure 3.
– An extended prescaler receiver register (SCIER-
PR)
– An extended prescaler transmitter register (SCI-
ETPR)
Figure 78. Word Length Programming
9-bit Word length (M bit is set)
Possible
Next Data Character
Parity
Data Character
Start
Bit
Next
Start
Bit
Stop
Bit
Bit2
Bit1
Bit3
Bit4
Bit5
Bit6
Bit8
Bit0
Bit7
Bit
Start
Bit
Idle Line
Start
Bit
Extra
’1’
Break Character
8-bit Word length (M bit is reset)
Possible
Parity
Next Data Character
Data Character
Bit
Next
Start
Bit
Start
Bit
Stop
Bit
Bit2
Bit6
Bit1
Bit3
Bit4
Bit5
Bit7
Bit0
Start
Bit
Idle Line
Start
Bit
Extra
’1’
Break Character
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ST72561
LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (Cont’d)
10.7.5.2 Transmitter
When no transmission is taking place, a write in-
struction to the SCIDR register places the data di-
rectly in the shift register, the data transmission
starts, and the TDRE bit is immediately set.
The transmitter can send data words of either 8 or
9 bits depending on the M bit status. When the M
bit is set, word length is 9 bits and the 9th bit (the
MSB) has to be stored in the T8 bit in the SCICR1
register.
When a character transmission is complete (after
the stop bit) the TC bit is set and an interrupt is
generated if the TCIE is set and the I[1:0] bits are
cleared in the CCR register.
Character Transmission
During an SCI transmission, data shifts out least
significant bit first on the TDO pin. In this mode,
the SCIDR register consists of a buffer (TDR) be-
tween the internal bus and the transmit shift regis-
ter (see Figure 1).
Clearing the TC bit is performed by the following
software sequence:
1. An access to the SCISR register
2. A write to the SCIDR register
Note: The TDRE and TC bits are cleared by the
same software sequence.
Procedure
– Select the M bit to define the word length.
Break Characters
– Select the desired baud rate using the SCIBRR
and the SCIETPR registers.
Setting the SBK bit loads the shift register with a
break character. The break character length de-
pends on the M bit (see Figure 2)
– Set the TE bit to send a preamble of 10 (M = 0)
or 11 (M = 1) consecutive ones (Idle Line) as first
transmission.
As long as the SBK bit is set, the SCI sends break
characters to the TDO pin. After clearing this bit by
software, the SCI inserts a logic 1 bit at the end of
the last break character to guarantee the recogni-
tion of the start bit of the next character.
– Access the SCISR register and write the data to
send in the SCIDR register (this sequence clears
the TDRE bit). Repeat this sequence for each
data to be transmitted.
Idle Line
Clearing the TDRE bit is always performed by the
following software sequence:
1. An access to the SCISR register
2. A write to the SCIDR register
Setting the TE bit drives the SCI to send a pream-
ble of 10 (M = 0) or 11 (M = 1) consecutive ‘1’s
(idle line) before the first character.
In this case, clearing and then setting the TE bit
during a transmission sends a preamble (idle line)
after the current word. Note that the preamble du-
ration (10 or 11 consecutive ‘1’s depending on the
M bit) does not take into account the stop bit of the
previous character.
The TDRE bit is set by hardware and it indicates:
– The TDR register is empty.
– The data transfer is beginning.
– The next data can be written in the SCIDR regis-
ter without overwriting the previous data.
Note: Resetting and setting the TE bit causes the
data in the TDR register to be lost. Therefore the
best time to toggle the TE bit is when the TDRE bit
is set, that is, before writing the next byte in the
SCIDR.
This flag generates an interrupt if the TIE bit is set
and the I[|1:0] bits are cleared in the CCR register.
When a transmission is taking place, a write in-
struction to the SCIDR register stores the data in
the TDR register and which is copied in the shift
register at the end of the current transmission.
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ST72561
LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (Cont’d)
10.7.5.3 Receiver
– The OR bit is set.
The SCI can receive data words of either 8 or 9
bits. When the M bit is set, word length is 9 bits
and the MSB is stored in the R8 bit in the SCICR1
register.
– The RDR content will not be lost.
– The shift register will be overwritten.
– An interrupt is generated if the RIE bit is set and
the I[|1:0] bits are cleared in the CCR register.
Character reception
The OR bit is reset by an access to the SCISR reg-
ister followed by a SCIDR register read operation.
During a SCI reception, data shifts in least signifi-
cant bit first through the RDI pin. In this mode, the
SCIDR register consists or a buffer (RDR) be-
tween the internal bus and the received shift regis-
ter (see Figure 1).
Noise Error
Oversampling techniques are used for data recov-
ery by discriminating between valid incoming data
and noise.
Procedure
When noise is detected in a character:
– Select the M bit to define the word length.
– The NF bit is set at the rising edge of the RDRF
bit.
– Select the desired baud rate using the SCIBRR
and the SCIERPR registers.
– Data is transferred from the Shift register to the
SCIDR register.
– Set the RE bit, this enables the receiver which
begins searching for a start bit.
– No interrupt is generated. However this bit rises
at the same time as the RDRF bit which itself
generates an interrupt.
When a character is received:
– The RDRF bit is set. It indicates that the content
of the shift register is transferred to the RDR.
The NF bit is reset by a SCISR register read oper-
ation followed by a SCIDR register read operation.
– An interrupt is generated if the RIE bit is set and
the I[1:0] bits are cleared in the CCR register.
Framing Error
– The error flags can be set if a frame error, noise
or an overrun error has been detected during re-
ception.
A framing error is detected when:
– The stop bit is not recognized on reception at the
expected time, following either a desynchroniza-
tion or excessive noise.
Clearing the RDRF bit is performed by the following
software sequence done by:
– A break is received.
1. An access to the SCISR register
2. A read to the SCIDR register.
When the framing error is detected:
– the FE bit is set by hardware
The RDRF bit must be cleared before the end of the
reception of the next character to avoid an overrun
error.
– Data is transferred from the Shift register to the
SCIDR register.
Idle Line
– No interrupt is generated. However this bit rises
at the same time as the RDRF bit which itself
generates an interrupt.
When an idle line is detected, there is the same
procedure as a data received character plus an in-
terrupt if the ILIE bit is set and the I[|1:0] bits are
cleared in the CCR register.
The FE bit is reset by a SCISR register read oper-
ation followed by a SCIDR register read operation.
Overrun Error
Break Character
An overrun error occurs when a character is re-
ceived when RDRF has not been reset. Data can
not be transferred from the shift register to the
TDR register as long as the RDRF bit is not
cleared.
– When a break character is received, the SCI
handles it as a framing error. To differentiate a
break character from a framing error, it is neces-
sary to read the SCIDR. If the received value is
00h, it is a break character. Otherwise it is a
framing error.
When an overrun error occurs:
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ST72561
LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (Cont’d)
10.7.5.4 Conventional Baud Rate Generation
10.7.5.5 Extended Baud Rate Generation
The baud rates for the receiver and transmitter (Rx
and Tx) are set independently and calculated as
follows:
The extended prescaler option gives a very fine
tuning on the baud rate, using a 255 value prescal-
er, whereas the conventional Baud Rate Genera-
tor retains industry standard software compatibili-
ty.
f
f
CPU
CPU
Rx =
Tx =
The extended baud rate generator block diagram
is described in Figure 3.
(16 PR) RR
(16 PR) TR
*
*
*
*
with:
The output clock rate sent to the transmitter or to
the receiver will be the output from the 16 divider
divided by a factor ranging from 1 to 255 set in the
SCIERPR or the SCIETPR register.
PR = 1, 3, 4 or 13 (see SCP[1:0] bits)
TR = 1, 2, 4, 8, 16, 32, 64,128
(see SCT[2:0] bits)
Note: The extended prescaler is activated by set-
ting the SCIETPR or SCIERPR register to a value
other than zero. The baud rates are calculated as
follows:
RR = 1, 2, 4, 8, 16, 32, 64,128
(see SCR[2:0] bits)
All these bits are in the SCIBRR register.
Example: If f is 8 MHz (normal mode) and if
CPU
f
f
CPU
CPU
PR = 13 and TR = RR = 1, the transmit and re-
ceive baud rates are 38400 baud.
Rx =
16 ERPR*(PR*RR)
Tx =
16 ETPR*(PR*TR)
*
*
Note: The baud rate registers MUST NOT be
changed while the transmitter or the receiver is en-
abled.
with:
ETPR = 1, ..., 255 (see SCIETPR register)
ERPR = 1, ..., 255 (see SCIERPR register)
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ST72561
LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (Cont’d)
Figure 79. SCI Baud Rate and Extended Prescaler Block Diagram
TRANSMITTER
CLOCK
EXTENDED PRESCALER TRANSMITTER RATE CONTROL
SCIETPR
EXTENDED TRANSMITTER PRESCALER REGISTER
SCIERPR
EXTENDED RECEIVER PRESCALER REGISTER
RECEIVER
CLOCK
EXTENDED PRESCALER RECEIVER RATE CONTROL
EXTENDED PRESCALER
f
CPU
TRANSMITTER RATE
CONTROL
/PR
/16
SCIBRR
SCP1
SCT2
SCT1SCT0SCR2 SCR1SCR0
SCP0
RECEIVER RATE
CONTROL
CONVENTIONAL BAUD RATE GENERATOR
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ST72561
LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (Cont’d)
10.7.5.6 Receiver Muting and Wake-up Feature
ceived an address character (most significant bit
= ’1’), the receivers are waken up. The receivers
which are not addressed set RWU bit to enter in
mute mode. Consequently, they will not treat the
next characters constituting the next part of the
message.
In multiprocessor configurations it is often desira-
ble that only the intended message recipient
should actively receive the full message contents,
thus reducing redundant SCI service overhead for
all non-addressed receivers.
10.7.5.7 Parity Control
The non-addressed devices may be placed in
sleep mode by means of the muting function.
Hardware byte Parity control (generation of parity
bit in transmission and parity checking in recep-
tion) can be enabled by setting the PCE bit in the
SCICR1 register. Depending on the character for-
mat defined by the M bit, the possible SCI charac-
ter formats are as listed in Table 1.
Setting the RWU bit by software puts the SCI in
sleep mode:
All the reception status bits can not be set.
All the receive interrupts are inhibited.
Note: In case of wake-up by an address mark, the
MSB bit of the data is taken into account and not
the parity bit
A muted receiver may be woken up in one of the
following ways:
– by Idle Line detection if the WAKE bit is reset,
– by Address Mark detection if the WAKE bit is set.
Idle Line Detection
Table 22. Character Formats
M bit
PCE bit
Character format
| SB | 8 bit data | STB |
| SB | 7-bit data | PB | STB |
| SB | 9-bit data | STB |
| SB | 8-bit data | PB | STB |
Receiver wakes up by Idle Line detection when the
Receive line has recognized an Idle Line. Then the
RWU bit is reset by hardware but the IDLE bit is
not set.
0
1
0
1
0
1
This feature is useful in a multiprocessor system
when the first characters of the message deter-
mine the address and when each message ends
by an idle line: As soon as the line becomes idle,
every receivers is waken up and analyse the first
characters of the message which indicates the ad-
dressed receiver. The receivers which are not ad-
dressed set RWU bit to enter in mute mode. Con-
sequently, they will not treat the next characters
constituting the next part of the message. At the
end of the message, an idle line is sent by the
transmitter: this wakes up every receivers which
are ready to analyse the addressing characters of
the new message.
Legend: SB = Start Bit, STB = Stop Bit,
PB = Parity Bit
Even parity: The parity bit is calculated to obtain
an even number of “1s” inside the character made
of the 7 or 8 LSB bits (depending on whether M is
equal to 0 or 1) and the parity bit.
Example: data = 00110101; 4 bits set => parity bit
will be 0 if even parity is selected (PS bit = 0).
Odd parity: The parity bit is calculated to obtain
an odd number of “1s” inside the character made
of the 7 or 8 LSB bits (depending on whether M is
equal to 0 or 1) and the parity bit.
Example: data = 00110101; 4 bits set => parity bit
will be 1 if odd parity is selected (PS bit = 1).
In such a system, the inter-characters space must
be smaller than the idle time.
Transmission mode: If the PCE bit is set then the
MSB bit of the data written in the data register is
not transmitted but is changed by the parity bit.
Address Mark Detection
Receiver wakes up by Address Mark detection
when it received a “1” as the most significant bit of
a word, thus indicating that the message is an ad-
dress. The reception of this particular word wakes
up the receiver, resets the RWU bit and sets the
RDRF bit, which allows the receiver to receive this
word normally and to use it as an address word.
Reception mode: If the PCE bit is set then the in-
terface checks if the received data byte has an
even number of “1s” if even parity is selected
(PS = 0) or an odd number of “1s” if odd parity is
selected (PS = 1). If the parity check fails, the PE
flag is set in the SCISR register and an interrupt is
generated if PCIE is set in the SCICR1 register.
This feature is useful in a multiprocessor system
when the most significant bit of each character
(except for the break character) is reserved for Ad-
dress Detection. As soon as the receivers re-
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ST72561
LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (Cont’d)
10.7.6 Low Power Modes
10.7.7 Interrupts
Mode
Description
Enable Exit
Control from from
Exit
Event
Flag
Interrupt Event
No effect on SCI.
SCI interrupts cause the device to exit from
Wait mode.
Bit
Wait
Halt
WAIT
TransmitDataRegister
Empty
TDRE
TC
TIE
SCI registers are frozen.
In Halt mode, the SCI stops transmitting/re-
ceiving until Halt mode is exited.
HALT
Transmission Com-
plete
TCIE
RIE
Received Data Ready
to be Read
RDRF
Yes
No
Overrun Error or LIN
Synch Error Detected
OR/
LHE
Idle Line Detected
Parity Error
IDLE
PE
ILIE
PIE
LIN Header Detection LHDF LHIE
The SCI interrupt events are connected to the
same interrupt vector (see Interrupts chapter).
These events generate an interrupt if the corre-
sponding Enable Control Bit is set and the inter-
rupt mask in the CC register is reset (RIM instruc-
tion).
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ST72561
LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (Cont’d)
10.7.8 SCI Mode Register Description
Bit 3 = OR Overrun error
STATUS REGISTER (SCISR)
Read Only
The OR bit is set by hardware when the word cur-
rently being received in the shift register is ready to
be transferred into the RDR register whereas
RDRF is still set. An interrupt is generated if
RIE = 1 in the SCICR2 register. It is cleared by a
software sequence (an access to the SCISR regis-
ter followed by a read to the SCIDR register).
0: No Overrun error
Reset Value: 1100 0000 (C0h)
7
0
1)
1)
1)
1)
TDRE
TC
RDRF IDLE
OR
NF
FE
PE
1: Overrun error detected
Bit 7 = TDRE Transmit data register empty.
Note: When this bit is set, RDR register contents
will not be lost but the shift register will be overwrit-
ten.
This bit is set by hardware when the content of the
TDR register has been transferred into the shift
register. An interrupt is generated if the TIE = 1 in
the SCICR2 register. It is cleared by a software se-
quence (an access to the SCISR register followed
by a write to the SCIDR register).
Bit 2 = NF Character Noise flag
0: Data is not transferred to the shift register
1: Data is transferred to the shift register
This bit is set by hardware when noise is detected
on a received character. It is cleared by a software
sequence (an access to the SCISR register fol-
lowed by a read to the SCIDR register).
0: No noise
Bit 6 = TC Transmission complete.
This bit is set by hardware when transmission of a
character containing Data is complete. An inter-
rupt is generated if TCIE = 1 in the SCICR2 regis-
ter. It is cleared by a software sequence (an ac-
cess to the SCISR register followed by a write to
the SCIDR register).
1: Noise is detected
Note: This bit does not generate interrupt as it ap-
pears at the same time as the RDRF bit which it-
self generates an interrupt.
0: Transmission is not complete
1: Transmission is complete
Bit 1 = FE Framing error.
This bit is set by hardware when a desynchroniza-
tion, excessive noise or a break character is de-
tected. It is cleared by a software sequence (an
access to the SCISR register followed by a read to
the SCIDR register).
Note: TC is not set after the transmission of a Pre-
amble or a Break.
Bit 5 = RDRF Received data ready flag.
This bit is set by hardware when the content of the
RDR register has been transferred to the SCIDR
register. An interrupt is generated if RIE = 1 in the
SCICR2 register. It is cleared by a software se-
quence (an access to the SCISR register followed
by a read to the SCIDR register).
0: No Framing error
1: Framing error or break character detected
Notes:
– This bit does not generate an interrupt as it ap-
pears at the same time as the RDRF bit which it-
self generates an interrupt. If the word currently
being transferred causes both a frame error and
an overrun error, it will be transferred and only
the OR bit will be set.
0: Data is not received
1: Received data is ready to be read
Bit 4 = IDLE Idle line detected.
Bit 0 = PE Parity error.
This bit is set by hardware when an Idle Line is de-
tected. An interrupt is generated if the ILIE = 1 in
the SCICR2 register. It is cleared by a software se-
quence (an access to the SCISR register followed
by a read to the SCIDR register).
This bit is set by hardware when a byte parity error
occurs (if the PCE bit is set) in receiver mode. It is
cleared by a software sequence (a read to the sta-
tus register followed by an access to the SCIDR
data register). An interrupt is generated if PIE = 1
in the SCICR1 register.
0: No Idle Line is detected
1: Idle Line is detected
0: No parity error
1: Parity error detected
Note: The IDLE bit will not be set again until the
RDRF bit has been set itself (that is, a new idle line
occurs).
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ST72561
LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (Cont’d)
CONTROL REGISTER 1 (SCICR1)
Read/Write
Bit 3 = WAKE Wake-Up method.
Reset Value: x000 0000 (x0h)
This bit determines the SCI Wake-Up method, it is
set or cleared by software.
0: Idle Line
7
0
1: Address Mark
1)
R8
T8
SCID
M
WAKE
PS
PIE
PCE
Note: If the LINE bit is set, the WAKE bit is deacti-
vated and replaced by the LHDM bit.
1)
This bit has a different function in LIN mode, please
refer to the LIN mode register description.
Bit 2 = PCE Parity control enable.
Bit 7 = R8 Receive data bit 8.
This bit is set and cleared by software. It selects
the hardware parity control (generation and detec-
tion for byte parity, detection only for LIN parity).
0: Parity control disabled
This bit is used to store the 9th bit of the received
word when M = 1.
1: Parity control enabled
Bit 6 = T8 Transmit data bit 8.
This bit is used to store the 9th bit of the transmit-
ted word when M = 1.
Bit 1 = PS Parity selection.
This bit selects the odd or even parity when the
parity generation/detection is enabled (PCE bit
set). It is set and cleared by software. The parity
will be selected after the current byte.
0: Even parity
Bit 5 = SCID Disabled for low power consumption
When this bit is set the SCI prescalers and outputs
are stopped and the end of the current byte trans-
fer in order to reduce power consumption.This bit
is set and cleared by software.
1: Odd parity
0: SCI enabled
1: SCI prescaler and outputs disabled
Bit 0 = PIE Parity interrupt enable.
This bit enables the interrupt capability of the hard-
ware parity control when a parity error is detected
(PE bit set). The parity error involved can be a byte
parity error (if bit PCE is set and bit LPE is reset) or
a LIN parity error (if bit PCE is set and bit LPE is
set).
Bit 4 = M Word length.
This bit determines the word length. It is set or
cleared by software.
0: 1 Start bit, 8 Data bits, 1 Stop bit
1: 1 Start bit, 9 Data bits, 1 Stop bit
0: Parity error interrupt disabled
Note: The M bit must not be modified during a data
transfer (both transmission and reception).
1: Parity error interrupt enabled
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ST72561
LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (Cont’d)
CONTROL REGISTER 2 (SCICR2)
Read/Write
Reset Value: 0000 0000 (00h)
1: Receiver is enabled and begins searching for a
start bit
Bit 1 = RWU Receiver wake-up.
7
0
This bit determines if the SCI is in mute mode or
not. It is set and cleared by software and can be
cleared by hardware when a wake-up sequence is
recognized.
1)
RWU
1)
TIE
TCIE
RIE
ILIE
TE
RE
SBK
1)
0: Receiver in active mode
This bit has a different function in LIN mode, please
1: Receiver in mute mode
refer to the LIN mode register description.
Notes:
Bit 7 = TIE Transmitter interrupt enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: In SCI interrupt is generated whenever
TDRE = 1 in the SCISR register
– Before selecting Mute mode (by setting the RWU
bit) the SCI must first receive a data byte, other-
wise it cannot function in Mute mode with wake-
up by Idle line detection.
– In Address Mark Detection Wake-Up configura-
tion (WAKE bit = 1) the RWU bit cannot be mod-
ified by software while the RDRF bit is set.
Bit 6 = TCIE Transmission complete interrupt ena-
ble
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever TC = 1
in the SCISR register
Bit 0 = SBK Send break.
This bit set is used to send break characters. It is
set and cleared by software.
0: No break character is transmitted
1: Break characters are transmitted
Bit 5 = RIE Receiver interrupt enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever OR = 1
or RDRF = 1 in the SCISR register
Note: If the SBK bit is set to “1” and then to “0”, the
transmitter will send a BREAK word at the end of
the current word.
DATA REGISTER (SCIDR)
Read/Write
Reset Value: Undefined
Bit 4 = ILIE Idle line interrupt enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever
IDLE = 1 in the SCISR register.
Contains the Received or Transmitted data char-
acter, depending on whether it is read from or writ-
ten to.
Bit 3 = TE Transmitter enable.
This bit enables the transmitter. It is set and
cleared by software.
7
0
DR7
DR6
DR5
DR4
DR3
DR2
DR1
DR0
0: Transmitter is disabled
1: Transmitter is enabled
Notes:
The Data register performs a double function (read
and write) since it is composed of two registers,
one for transmission (TDR) and one for reception
(RDR).
The TDR register provides the parallel interface
between the internal bus and the output shift reg-
ister (see Figure 1).
– During transmission, a “0” pulse on the TE bit
(“0” followed by “1”) sends a preamble (idle line)
after the current word.
– When TE is set there is a 1 bit-time delay before
the transmission starts.
The RDR register provides the parallel interface
between the input shift register and the internal
bus (see Figure 1).
Bit 2 = RE Receiver enable.
This bit enables the receiver. It is set and cleared
by software.
0: Receiver is disabled in the SCISR register
135/263
ST72561
LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (Cont’d)
BAUD RATE REGISTER (SCIBRR)
Read/Write
TR dividing factor
SCT2
SCT1
SCT0
1
2
0
1
0
1
0
1
0
1
Reset Value: 0000 0000 (00h)
0
0
7
0
4
1
0
1
8
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0
16
32
64
128
Note: When LIN slave mode is disabled, the SCI-
BRR register controls the conventional baud rate
generator.
1
Bits 7:6 = SCP[1:0] First SCI Prescaler
These 2 prescaling bits allow several standard
clock division ranges:
Bits 2:0 = SCR[2:0] SCI Receiver rate divider.
These 3 bits, in conjunction with the SCP[1:0] bits
define the total division applied to the bus clock to
yield the receive rate clock in conventional Baud
Rate Generator mode.
PR Prescaling factor
SCP1
SCP0
1
3
0
1
0
1
0
RR dividing factor
SCR2
SCR1
SCR0
4
1
1
2
0
1
0
1
0
1
0
1
13
0
0
4
Bits 5:3 = SCT[2:0] SCI Transmitter rate divisor
These 3 bits, in conjunction with the SCP1 and
SCP0 bits define the total division applied to the
bus clock to yield the transmit rate clock in conven-
tional Baud Rate Generator mode.
1
0
1
8
16
32
64
128
1
136/263
ST72561
LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (Cont’d)
EXTENDED RECEIVE PRESCALER DIVISION
REGISTER (SCIERPR)
EXTENDED TRANSMIT PRESCALER DIVISION
REGISTER (SCIETPR)
Read/Write
Read/Write
Reset Value: 0000 0000 (00h)
Reset Value:0000 0000 (00h)
7
0
7
0
ERPR ERPR ERPR ERPR ERPR ERPR ERPR ERPR
ETPR ETPR ETPR ETPR ETPR ETPR ETPR ETPR
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Bits 7:0 = ERPR[7:0] 8-bit Extended Receive
Prescaler Register.
Bits 7:0 = ETPR[7:0] 8-bit Extended Transmit
Prescaler Register.
The extended Baud Rate Generator is activated
when a value other than 00h is stored in this regis-
ter. The clock frequency from the 16 divider (see
Figure 3) is divided by the binary factor set in the
SCIERPR register (in the range 1 to 255).
The extended Baud Rate Generator is activated
when a value other than 00h is stored in this regis-
ter. The clock frequency from the 16 divider (see
Figure 3) is divided by the binary factor set in the
SCIETPR register (in the range 1 to 255).
The extended baud rate generator is not active af-
ter a reset.
The extended baud rate generator is not active af-
ter a reset.
Note: In LIN slave mode, the Conventional and
Extended Baud Rate Generators are disabled.
137/263
ST72561
LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode)
10.7.9 LIN Mode - Functional Description.
Slave
The block diagram of the Serial Control Interface,
in LIN slave mode is shown in Figure 5.
Set the LSLV bit in the SCICR3 register to enter
LIN slave mode. In this case, setting the SBK bit
will have no effect.
It uses six registers:
In LIN Slave mode the LIN baud rate generator is
selected instead of the Conventional or Extended
Prescaler. The LIN baud rate generator is com-
mon to the transmitter and the receiver.
– 3 control registers: SCICR1, SCICR2 and
SCICR3
– 2 status registers: the SCISR register and the
LHLR register mapped at the SCIERPR address
Then the baud rate can be programmed using
LPR and LPRF registers.
– A baud rate register: LPR mapped at the SCI-
BRR address and an associated fraction register
LPFR mapped at the SCIETPR address
Note: It is mandatory to set the LIN configuration
first before programming LPR and LPRF, because
the LIN configuration uses a different baud rate
generator from the standard one.
The bits dedicated to LIN are located in the
SCICR3. Refer to the register descriptions in Sec-
tion 0.1.10 for the definitions of each bit.
10.7.9.1 Entering LIN Mode
10.7.9.2 LIN Transmission
To use the LINSCI in LIN mode the following con-
figuration must be set in SCICR3 register:
In LIN mode the same procedure as in SCI mode
has to be applied for a LIN transmission.
– Clear the M bit to configure 8-bit word length.
To transmit the LIN Header the proceed as fol-
lows:
– Set the LINE bit.
Master
– First set the SBK bit in the SCICR2 register to
start transmitting a 13-bit LIN Synch Break
To enter master mode the LSLV bit must be reset
In this case, setting the SBK bit will send 13 low
bits.
– reset the SBK bit
– Load the LIN Synch Field (0x55) in the SCIDR
register to request Synch Field transmission
Then the baud rate can programmed using the
SCIBRR, SCIERPR and SCIETPR registers.
– Wait until the SCIDR is empty (TDRE bit set in
the SCISR register)
In LIN master mode, the Conventional and / or Ex-
tended Prescaler define the baud rate (as in stand-
ard SCI mode)
– Load the LIN message Identifier in the SCIDR
register to request Identifier transmission.
138/263
ST72561
LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (Cont’d)
Figure 80. LIN Characters
8-bit Word length (M bit is reset)
Next Data Character
Data Character
Bit2
Next
Start
Bit
Start
Bit
Stop
Bit
Bit6
Bit7
Bit0 Bit1
Bit3 Bit4
Bit5
Start
Bit
Idle Line
LIN Synch Field
LIN Synch Break = 13 low bits
Start
Bit
Extra
‘1’
LIN Synch Field
Bit2
Next
Start
Bit
Start
Bit
Stop
Bit
Bit6
Bit7
Bit0 Bit1
Bit3 Bit4
Bit5
Measurement for baud rate autosynchronization
139/263
ST72561
LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (Cont’d)
Figure 81. SCI Block Diagram in LIN Slave Mode
Write
Read
(DATA REGISTER) SCIDR
Received Data Register (RDR)
Receive Shift Register
Transmit Data Register (TDR)
TDO
RDI
Transmit Shift Register
SCICR1
R8
SCID
PCE
WAKE
T8
M
PS PIE
WAKE
UP
UNIT
TRANSMIT
CONTROL
RECEIVER
CONTROL
RECEIVER
CLOCK
SCISR
SCICR2
OR/
LHE
TIE TCIE RIE ILIE TE RE RWU SBK
TDRE
RDRF
IDLE
TC
NF FE
PE
SCI
INTERRUPT
CONTROL
TRANSMITTER
CLOCK
f
CPU
SCICR3
LDUM LINE
LASE LHDM LHIE LHDF LSF
LSLV
LIN SLAVE BAUD RATE
AUTO SYNCHRONIZATION
UNIT
SCIBRR
CONVENTIONAL BAUD RATE
LPR7
LPR0
GENERATOR
+
EXTENDED PRESCALER
0
f
CPU
1
/ LDIV
/16
LIN SLAVE BAUD RATE GENERATOR
140/263
ST72561
LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (Cont’d)
10.7.9.3 LIN Reception
Note:
In LIN mode the reception of a byte is the same as
in SCI mode but the LINSCI has features for han-
dling the LIN Header automatically (identifier de-
tection) or semiautomatically (Synch Break detec-
tion) depending on the LIN Header detection
mode. The detection mode is selected by the
LHDM bit in the SCICR3.
In LIN slave mode, the FE bit detects all frame er-
ror which does not correspond to a break.
Identifier Detection (LHDM = 1):
This case is the same as the previous one except
that the LHDF and the RDRF flags are set only af-
ter the entire header has been received (this is
true whether automatic resynchronization is ena-
bled or not). This indicates that the LIN Identifier is
available in the SCIDR register.
Additionally, an automatic resynchronization fea-
ture can be activated to compensate for any clock
deviation, for more details please refer to Section
0.1.9.5 LIN Baud Rate.
Notes:
During LIN Synch Field measurement, the SCI
state machine is switched off: no characters are
transferred to the data register.
LIN Header Handling by a Slave
Depending on the LIN Header detection method
the LINSCI will signal the detection of a LIN Head-
er after the LIN Synch Break or after the Identifier
has been successfully received.
LIN Slave parity
In LIN Slave mode (LINE and LSLV bits are set)
LIN parity checking can be enabled by setting the
PCE bit.
Note:
It is recommended to combine the Header detec-
tion function with Mute mode. Putting the LINSCI
in Mute mode allows the detection of Headers only
and prevents the reception of any other charac-
ters.
In this case, the parity bits of the LIN Identifier
Field are checked. The identifier character is rec-
rd
ognized as the 3 received character after a break
character (included):
This mode can be used to wait for the next Header
without being interrupted by the data bytes of the
current message in case this message is not rele-
vant for the application.
parity bits
Synch Break Detection (LHDM = 0):
When a LIN Synch Break is received:
LIN Synch
Break
LIN Synch
Field
Identifier
Field
– The RDRF bit in the SCISR register is set. It in-
dicates that the content of the shift register is
transferred to the SCIDR register, a value of
0x00 is expected for a Break.
The bits involved are the two MSB positions (7th
and 8th bits if M = 0; 8th and 9th bits if M = 0) of
the identifier character. The check is performed as
specified by the LIN specification:
– The LHDF flag in the SCICR3 register indicates
that a LIN Synch Break Field has been detected.
– An interrupt is generated if the LHIE bit in the
SCICR3 register is set and the I[1:0] bits are
cleared in the CCR register.
stop bit
parity bits
start bit
– Then the LIN Synch Field is received and meas-
ured.
identifier bits
ID0 ID1 ID2 ID3 ID4 ID5 P0 P1
– If automatic resynchronization is enabled (LA-
SE bit = 1), the LIN Synch Field is not trans-
ferred to the shift register: there is no need to
clear the RDRF bit.
Identifier Field
P0= ID0 ⊕ ID1 ⊕ ID2 ⊕ ID4
P1= ID1 ⊕ ID3 ⊕ ID4 ⊕ ID5
M = 0
– If automatic resynchronization is disabled (LA-
SE bit = 0), the LIN Synch Field is received as
a normal character and transferred to the
SCIDR register and RDRF is set.
141/263
ST72561
LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (Cont’d)
10.7.9.4 LIN Error Detection
LIN Header Error Flag
edge of the Synch Field. Let us refer to this peri-
od deviation as D:
If the LHE flag is set, it means that:
D > 15.625%
The LIN Header Error Flag indicates that an invalid
LIN Header has been detected.
When a LIN Header Error occurs:
– The LHE flag is set
If LHE flag is not set, it means that:
D < 16.40625%
– An interrupt is generated if the RIE bit is set and
the I[1:0] bits are cleared in the CCR register.
If 15.625% ≤ D < 16.40625%, then the flag can
be either set or reset depending on the dephas-
ing between the signal on the RDI line and the
CPU clock.
If autosynchronization is enabled (LASE bit = 1),
this can mean that the LIN Synch Field is corrupt-
ed, and that the SCI is in a blocked state (LSF bit is
set). The only way to recover is to reset the LSF bit
and then to clear the LHE bit.
– The second check is based on the measurement
of each bit time between both edges of the Synch
Field: this checks that each of these bit times is
large enough compared to the bit time of the cur-
rent baud rate.
– The LHE bit is reset by an access to the SCISR
register followed by a read of the SCIDR register.
When LHE is set due to this error then the SCI
goes into a blocked state (LSF bit is set).
LHE/OVR Error Conditions
When Auto Resynchronization is disabled (LASE
bit = 0), the LHE flag detects:
LIN Header Time-out Error
When the LIN Identifier Field Detection Method is
used (by configuring LHDM to 1) or when LIN
auto-resynchronization is enabled (LASE bit = 1),
– That the received LIN Synch Field is not equal to
55h.
– That an overrun occurred (as in standard SCI
mode)
the
LINSCI
automatically
monitors
the
T
condition given by the LIN protocol.
HEADER_MAX
– Furthermore, if LHDM is set it also detects that a
LIN Header Reception Timeout occurred (only if
LHDM is set).
If the entire Header (up to and including the STOP
bit of the LIN Identifier Field) is not received within
the maximum time limit of 57 bit times then a LIN
Header Error is signalled and the LHE bit is set in
the SCISR register.
When the LIN auto-resynchronization is enabled
(LASE bit = 1), the LHE flag detects:
– That the deviation error on the Synch Field is
outside the LIN specification which allows up to
+/-15.5% of period deviation between the slave
and master oscillators.
Figure 82. LIN Header Reception Timeout
– A LIN Header Reception Timeout occurred.
LIN Synch
Break
LIN Synch
Field
Identifier
Field
If T
> T
then the LHE flag is
HEADER
HEADER_MAX
set. Refer to Figure 6. (only if LHDM is set to 1)
– An overflow during the Synch Field Measure-
ment, which leads to an overflow of the divider
registers. If LHE is set due to this error then the
SCI goes into a blocked state (LSF bit is set).
T
HEADER
The time-out counter is enabled at each break de-
tection. It is stopped in the following conditions:
- A LIN Identifier Field has been received
- An LHE error occurred (other than a timeout er-
ror).
– That an overrun occurred on Fields other than
the Synch Field (as in standard SCI mode)
Deviation Error on the Synch Field
- A software reset of LSF bit (transition from high to
low) occurred during the analysis of the LIN Synch
Field or
The deviation error is checking by comparing the
current baud rate (relative to the slave oscillator)
with the received LIN Synch Field (relative to the
master oscillator). Two checks are performed in
parallel:
If LHE bit is set due to this error during the LIN
Synchr Field (if LASE bit = 1) then the SCI goes
into a blocked state (LSF bit is set).
– The first check is based on a measurement be-
tween the first falling edge and the last falling
142/263
ST72561
LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (Cont’d)
If LHE bit is set due to this error during Fields other
than LIN Synch Field or if LASE bit is reset then
the current received Header is discarded and the
SCI searches for a new Break Field.
LIN Header Length
Even if no timeout occurs on the LIN Header, it is
possible to have access to the effective LIN head-
er Length (T
) through the LHL register.
HEADER
Note on LIN Header Time-out Limit
This allows monitoring at software level the
condition given by the LIN protocol.
T
FRAME_MAX
According to the LIN specification, the maximum
length of a LIN Header which does not cause a
This feature is only available when LHDM bit = 1
or when LASE bit = 1.
timeout
BIT_MASTER
is
equal
to
1.4 * (34 + 1) = 49
T
.
Mute Mode and Errors
T
refers to the master baud rate.
BIT_MASTER
In mute mode when LHDM bit = 1, if an LHE error
occurs during the analysis of the LIN Synch Field
or if a LIN Header Time-out occurs then the LHE
bit is set but it does not wake up from mute mode.
In this case, the current header analysis is discard-
ed. If needed, the software has to reset LSF bit.
Then the SCI searches for a new LIN header.
When checking this timeout, the slave node is de-
synchronized for the reception of the LIN Break
and Synch fields. Consequently, a margin must be
allowed, taking into account the worst case: This
occurs when the LIN identifier lasts exactly 10
T
periods. In this case, the LIN Break
BIT_MASTER
and Synch fields last 49 - 10 = 39T
riods.
pe-
BIT_MASTER
In mute mode, if a framing error occurs on a data
(which is not a break), it is discarded and the FE bit
is not set.
Assuming the slave measures these first 39 bits
with a desynchronized clock of 15.5%. This leads
to a maximum allowed Header Length of:
When LHDM bit = 1, any LIN header which re-
spects the following conditions causes a wake-up
from mute mode:
39 x (1/0.845) T
+ 10T
BIT_MASTER
BIT_MASTER
= 56.15 T
- A valid LIN Break Field (at least 11 dominant bits
followed by a recessive bit)
BIT_SLAVE
A margin is provided so that the time-out occurs
when the header length is greater than 57
- A valid LIN Synch Field (without deviation error)
T
T
periods. If it is less than or equal to 57
periods, then no timeout occurs.
BIT_SLAVE
BIT_SLAVE
- A LIN Identifier Field without framing error. Note
that a LIN parity error on the LIN Identifier Field
does not prevent wake-up from mute mode.
- No LIN Header Time-out should occur during
Header reception.
Figure 83. LIN Synch Field Measurement
= CPU period
t
CPU
t
= 16.LP.t
CPU
t
= Baud Rate period
BR
BR
SM = Synch Measurement Register (15 bits)
t
BR
LIN Synch Field
Next
LIN Synch Break
Extra
’1’
Start
Bit
Start
Stop
Bit2
Bit6
Bit7
Bit5
Bit0 Bit1
Bit3 Bit4
Bit
Bit
Measurement = 8.T = SM.t
BR
CPU
LPR(n+1)
LPR(n)
LPR = t / (16.t
) = Rounding (SM / 128)
CPU
BR
143/263
ST72561
LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (Cont’d)
10.7.9.5 LIN Baud Rate
mitter are both set to the same value, depending
on the LIN Slave baud rate generator:
Baud rate programming is done by writing a value
in the LPR prescaler or performing an automatic
resynchronization as described below.
f
CPU
Automatic Resynchronization
Tx = Rx =
(16 LDIV)
*
To automatically adjust the baud rate based on
measurement of the LIN Synch Field:
with:
– Write the nominal LIN Prescaler value (usually
depending on the nominal baud rate) in the
LPFR / LPR registers.
LDIV is an unsigned fixed point number. The man-
tissa is coded on 8 bits in the LPR register and the
fraction is coded on 4 bits in the LPFR register.
– Set the LASE bit to enable the Auto Synchroni-
zation Unit.
If LASE bit = 1 then LDIV is automatically updated
at the end of each LIN Synch Field.
When Auto Synchronization is enabled, after each
LIN Synch Break, the time duration between five
Three registers are used internally to manage the
auto-update of the LIN divider (LDIV):
falling edges on RDI is sampled on f
and the
CPU
- LDIV_NOM (nominal value written by software at
LPR/LPFR addresses)
result of this measurement is stored in an internal
15-bit register called SM (not user accessible)
(See Figure 7). Then the LDIV value (and its asso-
ciated LPFR and LPR registers) are automatically
updated at the end of the fifth falling edge. During
LIN Synch field measurement, the SCI state ma-
chine is stopped and no data is transferred to the
data register.
- LDIV_MEAS (results of the Field Synch meas-
urement)
- LDIV (used to generate the local baud rate)
The control and interactions of these registers is
explained in Figure 8 and Figure 9. It depends on
the LDUM bit setting (LIN Divider Update Method)
10.7.9.6 LIN Slave Baud Rate Generation
Note:
In LIN mode, transmission and reception are driv-
en by the LIN baud rate generator
As explained in Figure 8 and Figure 9, LDIV
can be updated by two concurrent actions: a
transfer from LDIV_MEAS at the end of the LIN
Sync Field and a transfer from LDIV_NOM due
to a software write of LPR. If both operations
occur at the same time, the transfer from
LDIV_NOM has priority.
Note: LIN Master mode uses the Extended or
Conventional prescaler register to generate the
baud rate.
If LINE bit = 1 and LSLV bit = 1 then the Conven-
tional and Extended Baud Rate Generators are
disabled: the baud rate for the receiver and trans-
144/263
ST72561
LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (Cont’d)
Figure 84. LDIV Read / Write Operations When LDUM = 0
Write LPFR
Write LPR
LIN Sync Field
Measurement
MANT(7:0) FRAC(3:0)
Write LPR
LDIV_NOM
LDIV_MEAS
MANT(7:0) FRAC(3:0)
Update
at end of
Synch Field
Baud Rate
Generation
MANT(7:0) FRAC(3:0)
LDIV
Read LPR
Read LPFR
Figure 85. LDIV Read / Write Operations When LDUM = 1
Write LPFR
Write LPR
LIN Sync Field
Measurement
MANT(7:0) FRAC(3:0)
RDRF = 1
LDIV_NOM
LDIV_MEAS
MANT(7:0) FRAC(3:0)
Update
at end of
Synch Field
Baud Rate
Generation
MANT(7:0) FRAC(3:0)
LDIV
Read LPR
Read LPFR
145/263
ST72561
LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (Cont’d)
10.7.9.7 LINSCI Clock Tolerance
Consequently, the clock frequency should not vary
more than 6/16 (37.5%) within one bit.
LINSCI Clock Tolerance when unsynchronized
The sampling clock is resynchronized at each start
bit, so that when receiving 10 bits (one start bit, 1
data byte, 1 stop bit), the clock deviation should
not exceed 3.75%.
When LIN slaves are unsynchronized (meaning no
characters have been transmitted for a relatively
long time), the maximum tolerated deviation of the
LINSCI clock is +/-15%.
10.7.9.8 Clock Deviation Causes
If the deviation is within this range then the LIN
Synch Break is detected properly when a new re-
ception occurs.
The causes which contribute to the total deviation
are:
This is made possible by the fact that masters
send 13 low bits for the LIN Synch Break, which
can be interpreted as 11 low bits (13 bits -15% =
11.05) by a “fast” slave and then considered as a
LIN Synch Break. According to the LIN specifica-
tion, a LIN Synch Break is valid when its duration
– D
: Deviation due to transmitter error.
TRA
Note: The transmitter can be either a master
or a slave (in case of a slave listening to the
response of another slave).
– D
: Error due to the LIN Synch measure-
MEAS
ment performed by the receiver.
is greater than t
= 10. This means that the
SBRKTS
– D : Error due to the baud rate quantiza-
tion of the receiver.
QUANT
LIN Synch Break must last at least 11 low bits.
Note: If the period desynchronization of the slave
is +15% (slave too slow), the character “00h”
which represents a sequence of 9 low bits must
not be interpreted as a break character (9 bits +
15% = 10.35). Consequently, a valid LIN Synch
break must last at least 11 low bits.
– D
: Deviation of the local oscillator of the
REC
receiver: This deviation can occur during the
reception of one complete LIN message as-
suming that the deviation has been compen-
sated at the beginning of the message.
– D
: Deviation due to the transmission line
TCL
LINSCI Clock Tolerance when Synchronized
(generally due to the transceivers)
When synchronization has been performed, fol-
lowing reception of a LIN Synch Break, the LINS-
CI, in LIN mode, has the same clock deviation tol-
erance as in SCI mode, which is explained below:
All the deviations of the system should be added
and compared to the LINSCI clock tolerance:
D
+ D
+D
+ D
+ D
< 3.75%
TCL
TRA
MEAS
QUANT
REC
During reception, each bit is oversampled 16
times. The mean of the 8th, 9th and 10th samples
is considered as the bit value.
Figure 86.Bit Sampling in Reception Mode
RDI LINE
sampled values
Sample
clock
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
6/16
7/16
7/16
One bit time
146/263
ST72561
LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (Cont’d)
10.7.9.9 Error due to LIN Synch measurement
Consequently, at a given CPU frequency, the
maximum possible nominal baud rate (LPR
should be chosen with respect to the maximum tol-
erated deviation given by the equation:
)
MIN
The LIN Synch Field is measured over eight bit
times.
This measurement is performed using a counter
clocked by the CPU clock. The edge detections
are performed using the CPU clock cycle.
D
+ 2 / (128*LDIV ) + 1 / (2*16*LDIV
)
TRA
MIN
MIN
+ D
+ D
< 3.75%
TCL
REC
This leads to a precision of 2 CPU clock cycles for
the measurement which lasts 16*8*LDIV clock cy-
cles.
Example:
A nominal baud rate of 20Kbits/s at T
= 125ns
CPU
Consequently, this error (D
) is equal to:
MEAS
(8 MHz) leads to LDIV
= 25d.
NOM
2 / (128*LDIV ).
MIN
LDIV
= 25 - 0.15*25 = 21.25
MIN
LDIV
corresponds to the minimum LIN prescal-
MIN
D
D
= 2 / (128*LDIV ) * 100 = 0.00073%
MIN
MEAS
er content, leading to the maximum baud rate, tak-
ing into account the maximum deviation of +/-15%.
= 1 / (2*16*LDIV ) * 100 = 0.0015%
QUANT
MIN
10.7.9.10 Error due to Baud Rate Quantization
LIN Slave systems
The baud rate can be adjusted in steps of 1 / (16 *
LDIV). The worst case occurs when the “real”
baud rate is in the middle of the step.
For LIN Slave systems (the LINE and LSLV bits
are set), receivers wake up by LIN Synch Break or
LIN Identifier detection (depending on the LHDM
bit).
This leads to a quantization error (D
) equal
QUANT
to 1 / (2*16*LDIV ).
MIN
Hot Plugging Feature for LIN Slave Nodes
10.7.9.11 Impact of Clock Deviation on
Maximum Baud Rate
In LIN Slave Mute Mode (the LINE, LSLV and
RWU bits are set) it is possible to hot plug to a net-
work during an ongoing communication flow. In
this case the SCI monitors the bus on the RDI line
until 11 consecutive dominant bits have been de-
tected and discards all the other bits received.
The choice of the nominal baud rate (LDIV
)
)
NOM
will influence both the quantization error (D
QUANT
and the measurement error (D
). The worst
MEAS
case occurs for LDIV
.
MIN
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LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (Cont’d)
10.7.10 LIN Mode Register Description
framing error is detected (if the stop bit is dominant
(0) and at least one of the other bits is recessive
(1). It is not set when a break occurs, the LHDF bit
is used instead as a break flag (if the LHDM
bit = 0). It is cleared by a software sequence (an
access to the SCISR register followed by a read to
the SCIDR register).
STATUS REGISTER (SCISR)
Read Only
Reset Value: 1100 0000 (C0h)
7
0
0: No Framing error
1: Framing error detected
TDRE
TC
RDRF IDLE
LHE
NF
FE
PE
Bits 7:4 = Same function as in SCI mode, please
refer to Section 0.1.8 SCI Mode Register Descrip-
tion.
Bit 0 = PE Parity error.
This bit is set by hardware when a LIN parity error
occurs (if the PCE bit is set) in receiver mode. It is
cleared by a software sequence (a read to the sta-
tus register followed by an access to the SCIDR
data register). An interrupt is generated if PIE = 1
in the SCICR1 register.
Bit 3 = LHE LIN Header Error.
During LIN Header this bit signals three error
types:
0: No LIN parity error
1: LIN Parity error detected
– The LIN Synch Field is corrupted and the SCI is
blocked in LIN Synch State (LSF bit = 1).
– A timeout occurred during LIN Header reception
CONTROL REGISTER 1 (SCICR1)
Read/Write
Reset Value: x000 0000 (x0h)
– An overrun error was detected on one of the
header field (see OR bit description in Section
0.1.8 SCI Mode Register Description)).
An interrupt is generated if RIE = 1 in the SCICR2
register. If blocked in the LIN Synch State, the LSF
bit must first be reset (to exit LIN Synch Field state
and then to be able to clear LHE flag). Then it is
cleared by the following software sequence: An
access to the SCISR register followed by a read to
the SCIDR register.
7
0
R8
T8
SCID
M
WAKE PCE
PS
PIE
Bits 7:3 = Same function as in SCI mode, please
refer to Section 0.1.8 SCI Mode Register Descrip-
tion.
0: No LIN Header error
1: LIN Header error detected
Bit 2 = PCE Parity control enable.
This bit is set and cleared by software. It selects
the hardware parity control for LIN identifier parity
check.
Note:
Apart from the LIN Header this bit signals an Over-
run Error as in SCI mode, (see description in Sec-
tion 0.1.8 SCI Mode Register Description)
0: Parity control disabled
1: Parity control enabled
When a parity error occurs, the PE bit in the
SCISR register is set.
Bit 2 = NF Noise flag
In LIN Master mode (LINE bit = 1 and LSLV bit = 0)
this bit has the same function as in SCI mode,
please refer to Section 0.1.8 SCI Mode Register
Description
Bit 1 = Reserved
In LIN Slave mode (LINE bit = 1 and LSLV bit = 1)
this bit has no meaning.
Bit 0 = Same function as in SCI mode, please refer
to Section 0.1.8 SCI Mode Register Description.
Bit 1 = FE Framing error.
In LIN slave mode, this bit is set only when a real
148/263
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LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (Cont’d)
CONTROL REGISTER 2 (SCICR2)
Read/Write
Reset Value: 0000 0000 (00h)
1: LDIV is updated at the next received character
(when RDRF = 1) after a write to the LPR regis-
ter
Notes:
7
0
- If no write to LPR is performed between the set-
ting of LDUM bit and the reception of the next
character, LDIV will be updated with the old value.
TIE
TCIE
RIE
ILIE
TE
RE
RWU SBK
- After LDUM has been set, it is possible to reset
the LDUM bit by software. In this case, LDIV can
be modified by writing into LPR / LPFR registers.
Bits 7:2 Same function as in SCI mode, please re-
fer to Section 0.1.8 SCI Mode Register Descrip-
tion.
Bit 1 = RWU Receiver wake-up.
Bits 6:5 = LINE, LSLV LIN Mode Enable Bits.
This bit determines if the SCI is in mute mode or
not. It is set and cleared by software and can be
cleared by hardware when a wake-up sequence is
recognized.
These bits configure the LIN mode:
LINE
LSLV
Meaning
0
x
0
1
LIN mode disabled
LIN Master Mode
LIN Slave Mode
0: Receiver in active mode
1: Receiver in mute mode
1
Notes:
– Mute mode is recommended for detecting only
the Header and avoiding the reception of any
other characters. For more details please refer to
Section 0.1.9.3 LIN Reception.
The LIN Master configuration enables:
The capability to send LIN Synch Breaks (13 low
bits) using the SBK bit in the SCICR2 register.
The LIN Slave configuration enables:
– In LIN slave mode, when RDRF is set, the soft-
ware can not set or clear the RWU bit.
– The LIN Slave Baud Rate generator. The LIN
Divider (LDIV) is then represented by the LPR
and LPFR registers. The LPR and LPFR reg-
isters are read/write accessible at the address
of the SCIBRR register and the address of the
SCIETPR register
Bit 0 = SBK Send break.
This bit set is used to send break characters. It is
set and cleared by software.
0: No break character is transmitted
1: Break characters are transmitted
– Management of LIN Headers.
Note: If the SBK bit is set to “1” and then to “0”, the
transmitter will send a BREAK word at the end of
the current word.
– LIN Synch Break detection (11-bit dominant).
– LIN Wake-Up method (see LHDM bit) instead
of the normal SCI Wake-Up method.
– Inhibition of Break transmission capability
(SBK has no effect)
CONTROL REGISTER 3 (SCICR3)
Read/Write
Reset Value: 0000 0000 (00h)
– LIN Parity Checking (in conjunction with the
PCE bit)
7
0
Bit 4 = LASE LIN Auto Synch Enable.
This bit enables the Auto Synch Unit (ASU). It is
set and cleared by software. It is only usable in LIN
Slave mode.
LDUM LINE LSLV
LASE
LHDM LHIE LHDF LSF
Bit 7 = LDUM LIN Divider Update Method.
This bit is set and cleared by software and is also
cleared by hardware (when RDRF = 1). It is only
used in LIN Slave mode. It determines how the LIN
Divider can be updated by software.
0: LDIV is updated as soon as LPR is written (if no
Auto Synchronization update occurs at the
same time).
0: Auto Synch Unit disabled
1: Auto Synch Unit enabled.
Bit 3 = LHDM LIN Header Detection Method
This bit is set and cleared by software. It is only us-
able in LIN Slave mode. It enables the Header De-
tection Method. In addition if the RWU bit in the
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LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (Cont’d)
SCICR2 register is set, the LHDM bit selects the
Wake-Up method (replacing the WAKE bit).
0: LIN Synch Break Detection Method
Figure 87. LSF Bit Set and Clear
11 dominant bits
parity bits
1: LIN Identifier Field Detection Method
LSF bit
Bit 2 = LHIE LIN Header Interrupt Enable
This bit is set and cleared by software. It is only us-
able in LIN Slave mode.
LIN Synch
Break
LIN Synch
Field
Identifier
Field
0: LIN Header Interrupt is inhibited.
1: An SCI interrupt is generated whenever
LHDF = 1.
LIN DIVIDER REGISTERS
Bit 1 = LHDF LIN Header Detection Flag
This bit is set by hardware when a LIN Header is
detected and cleared by a software sequence (an
access to the SCISR register followed by a read of
the SCICR3 register). It is only usable in LIN Slave
mode.
LDIV is coded using the two registers LPR and LP-
FR. In LIN Slave mode, the LPR register is acces-
sible at the address of the SCIBRR register and
the LPFR register is accessible at the address of
the SCIETPR register.
0: No LIN Header detected.
LIN PRESCALER REGISTER (LPR)
Read/Write
Reset Value: 0000 0000 (00h)
1: LIN Header detected.
Notes: The header detection method depends on
the LHDM bit:
7
0
– If LHDM = 0, a header is detected as a LIN
Synch Break.
LPR7 LPR6 LPR5 LPR4 LPR3 LPR2 LPR1 LPR0
– If LHDM = 1, a header is detected as a LIN
Identifier, meaning that a LIN Synch Break
Field + a LIN Synch Field + a LIN Identifier
Field have been consecutively received.
LPR[7:0] LIN Prescaler (mantissa of LDIV)
These 8 bits define the value of the mantissa of the
LIN Divider (LDIV):
Bit 0 = LSF LIN Synch Field State
LPR[7:0]
00h
Rounded Mantissa (LDIV)
This bit indicates that the LIN Synch Field is being
analyzed. It is only used in LIN Slave mode. In
Auto Synchronization Mode (LASE bit = 1), when
the SCI is in the LIN Synch Field State it waits or
counts the falling edges on the RDI line.
SCI clock disabled
01h
1
...
...
FEh
FFh
254
255
It is set by hardware as soon as a LIN Synch Break
is detected and cleared by hardware when the LIN
Synch Field analysis is finished (See Figure 11).
This bit can also be cleared by software to exit LIN
Synch State and return to idle mode.
0: The current character is not the LIN Synch Field
1: LIN Synch Field State (LIN Synch Field under-
going analysis)
Caution: LPR and LPFR registers have different
meanings when reading or writing to them. Conse-
quently bit manipulation instructions (BRES or
BSET) should never be used to modify the
LPR[7:0] bits, or the LPFR[3:0] bits.
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LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (Cont’d)
LIN PRESCALER FRACTION REGISTER
(LPFR)
will effectively update LDIV and so the clock gen-
eration.
Read/Write
2. In LIN Slave mode, if the LPR[7:0] register is
equal to 00h, the transceiver and receiver input
clocks are switched off.
Reset Value: 0000 0000 (00h)
7
0
LPFR LPFR LPFR LPFR
Examples of LDIV coding:
Example 1: LPR = 27d and LPFR = 12d
This leads to:
0
0
0
0
3
2
1
0
Mantissa (LDIV) = 27d
Bits 7:4 = Reserved.
Bits 3:0 = LPFR[3:0] Fraction of LDIV
Fraction (LDIV) = 12/16 = 0.75d
Therefore LDIV = 27.75d
These 4 bits define the fraction of the LIN Divider
(LDIV):
Example 2: LDIV = 25.62d
This leads to:
LPFR[3:0]
Fraction (LDIV)
0h
1h
...
0
LPFR = rounded(16*0.62d)
= rounded(9.92d) = 10d = Ah
LPR = mantissa (25.620d) = 25d = 1Bh
1/16
...
Eh
Fh
14/16
15/16
Example 3: LDIV = 25.99d
This leads to:
1. When initializing LDIV, the LPFR register must
be written first. Then, the write to the LPR register
LPFR = rounded(16*0.99d)
= rounded(15.84d) = 16d
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LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (Cont’d)
LIN HEADER LENGTH REGISTER (LHLR)
Read Only
LHL[1:0]
Fraction (57 - T
)
HEADER
0h
1h
2h
3h
0
Reset Value: 0000 0000 (00h).
1/4
1/2
3/4
7
0
LHL7 LHL6 LHL5 LHL4 LHL3 LHL2 LHL1 LHL0
Example of LHL coding:
Note: In LIN Slave mode when LASE = 1 or LHDM
= 1, the LHLR register is accessible at the address
of the SCIERPR register.
Example 1: LHL = 33h = 001100 11b
LHL(7:3) = 1100b = 12d
LHL(1:0) = 11b = 3d
Otherwise this register is always read as 00h.
This leads to:
Bits 7:0 = LHL[7:0] LIN Header Length.
Mantissa (57 - T
) = 12d
HEADER
This is a read-only register, which is updated by
hardware if one of the following conditions occurs:
- After each break detection, it is loaded with
“FFh”.
Fraction (57 - T
Therefore:
) = 3/4 = 0.75
HEADER
(57 - T
and T
) = 12.75d
= 44.25d
HEADER
- If a timeout occurs on T
00h.
, it is loaded with
HEADER
HEADER
- After every successful LIN Header reception (at
the same time than the setting of LHDF bit), it is
loaded with a value (LHL) which gives access to
the number of bit times of the LIN header length
HEADER
below:
Example 2:
57 - T
= 36.21d
HEADER
LHL(1:0) = rounded(4*0.21d) = 1d
(T
). The coding of this value is explained
LHL(7:2) = Mantissa (36.21d) = 36d = 24h
Therefore LHL(7:0) = 10010001 = 91h
LHL Coding:
T
= 57
HEADER_MAX
LHL(7:2) represents the mantissa of (57 - T
ER
Example 3:
HEAD-
)
57 - T
= 36.90d
HEADER
LHL(1:0) represents the fraction (57 - T
)
HEADER
LHL(1:0) = rounded(4*0.90d) = 4d
Mantissa
The carry must be propagated to the matissa:
LHL(7:2) = Mantissa (36.90d) + 1 = 37d =
Therefore LHL(7:0) = 10110000 = A0h
Mantissa
(T
LHL[7:2]
)
(57 - T
)
HEADER
HEADER
0h
1h
0
57
56
...
1
1
...
...
39h
3Ah
3Bh
...
56
57
58
...
0
Never Occurs
...
3Eh
3Fh
62
63
Never Occurs
Initial value
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ST72561
LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Master/Slave) (Cont’d)
Table 23. LINSCI1 Register Map and Reset Values
Addr.
Register Name
7
6
5
4
3
2
1
0
(Hex.
)
SCI1SR
TDRE
TC
1
RDRF
0
IDLE
OR/LHE
NF
0
FE
0
PE
0
48
49
Reset Value
SCI1DR
1
DR7
-
0
DR4
-
0
DR3
-
DR6
-
DR5
-
DR2
-
DR1
-
DR0
-
Reset Value
SCP1
LPR7
0
SCP0
LPR6
0
SCT2
LPR5
0
SCT1
LPR4
0
SCT0
LPR3
0
SCR2
LPR2
0
SCR1
LPR1
0
SCR0
LPR0
0
SCI1BRR
4A
LPR (LIN Slave Mode)
Reset Value
SCI1CR1
R8
T8
SCID
0
M
WAKE
0
PCE
0
PS
0
PIE
0
4B
4C
4D
Reset Value
SCI1CR2
x
0
0
TIE
0
TCIE
0
RIE
0
ILIE
0
TE
RE
0
RWU
0
SBK
0
Reset Value
SCI1CR3
0
LDUM
0
LINE
0
LSLV
0
LASE
0
LHDM
0
LHIE
0
LHDF
0
LSF
0
Reset Value
SCI1ERPR
ERPR7 ERPR6 ERPR5 ERPR4 ERPR3 ERPR2 ERPR1 ERPR0
LHL7
LHL6
LHL5
LHL4
LHL3
LHL2
LHL1
LHL0
4E
4F
LHLR (LIN Slave Mode)
Reset Value
0
0
0
0
0
0
0
0
ETPR7 ETPR6 ETPR5 ETPR4 ETPR3 ETPR2 ETPR1 ETPR0
SCI1ETPR
0
0
0
0
0
0
0
0
LPFR3
0
LPFR2 LPFR1 LPFR0
LPFR (LIN Slave Mode)
Reset Value
0
0
0
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10.8 LINSCI SERIAL COMMUNICATION INTERFACE (LIN Master Only)
10.8.1 Introduction
10.8.3 General Description
The Serial Communications Interface (SCI) offers
a flexible means of full-duplex data exchange with
external equipment requiring an industry standard
NRZ asynchronous serial data format. The SCI of-
fers a very wide range of baud rates using two
baud rate generator systems.
The interface is externally connected to another
device by three pins (see Figure 1 on page 19).
Any SCI bidirectional communication requires a
minimum of two pins: Receive Data In (RDI) and
Transmit Data Out (TDO):
– SCLK: Transmitter clock output. This pin outputs
the transmitter data clock for synchronous trans-
mission (no clock pulses on start bit and stop bit,
and a software option to send a clock pulse on
the last data bit). This can be used to control pe-
ripherals that have shift registers (e.g. LCD driv-
ers). The clock phase and polarity are software
programmable.
10.8.2 Main Features
■ Full duplex, asynchronous communications
■ NRZ standard format (Mark/Space)
■ Dual baud rate generator systems
■ Independently programmable transmit and
receive baud rates up to 500K baud.
■ Programmable data word length (8 or 9 bits)
■ Receive buffer full, Transmit buffer empty and
End of Transmission flags
■ 2 receiver wake-up modes:
– Address bit (MSB)
– TDO: Transmit Data Output. When the transmit-
ter is disabled, the output pin returns to its I/O
port configuration. When the transmitter is ena-
bled and nothing is to be transmitted, the TDO
pin is at high level.
– RDI: Receive Data Input is the serial data input.
Oversampling techniques are used for data re-
covery by discriminating between valid incoming
data and noise.
– Idle line
■ Mutingfunctionformultiprocessorconfigurations
■ Separate enable bits for Transmitter and
Receiver
■ 4 error detection flags:
– Overrun error
Through these pins, serial data is transmitted and
received as frames comprising:
– An Idle Line prior to transmission or reception
– A start bit
– Noise error
– A data word (8 or 9 bits) least significant bit first
– A Stop bit indicating that the frame is complete.
Thisinterfaceusestwotypesofbaudrategenerator:
– Frame error
– Parity error
■ 5 interrupt sources with flags:
– Transmit data register empty
– Transmission complete
– Receive data register full
– Idle line received
– A conventional type for commonly-used baud
rates,
– An extended type with a prescaler offering a very
wide range of baud rates even with non-standard
oscillator frequencies.
– Overrun error detected
■ Transmitter clock output
■ Parity control:
– Transmits parity bit
– Checks parity of received data byte
■ Reduced power consumption mode
■ LIN Synch Break send capability
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ST72561
LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Master Only) (Cont’d)
Figure 88. SCI Block Diagram
Write
Read
(DATA REGISTER) SCIDR
Received Data Register (RDR)
Received Shift Register
Transmit Data Register (TDR)
TDO
Transmit Shift Register
RDI
LINE
-
-
CLKENCPOL CPHA LBCL
SCICR3
CLOCK EXTRACTION
PHASE AND POLARITY
CONTROL
SCLK
R8
T8 SCID
M
WAKE PCE PS PIE
SCICR1
WAKE
UP
TRANSMIT
CONTROL
RECEIVER
CLOCK
RECEIVER
CONTROL
UNIT
SCISR
SCICR2
TDRE TC RDRF IDLE OR NF FE
PE
TIE TCIE RIE ILIE TE RE RWU SBK
SCI
INTERRUPT
CONTROL
TRANSMITTER
CLOCK
TRANSMITTER RATE
CONTROL
f
CPU
/PR
/16
SCIBRR
SCP1
SCT2
SCT1 SCT0SCR2 SCR1SCR0
SCP0
RECEIVER RATE
CONTROL
CONVENTIONAL BAUD RATE GENERATOR
155/263
ST72561
LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Master Only) (Cont’d)
10.8.4 Functional Description
10.8.4.1 Serial Data Format
The block diagram of the Serial Control Interface,
is shown in Figure 1 on page 19. It contains seven
dedicated registers:
Word length may be selected as being either 8 or 9
bits by programming the M bit in the SCICR1 reg-
ister (see Figure 2).
– Three control registers (SCICR1, SCICR2 and
SCICR3)
The TDO pin is in low state during the start bit.
The TDO pin is in high state during the stop bit.
– A status register (SCISR)
An Idle character is interpreted as an entire frame
of “1”s followed by the start bit of the next frame
which contains data.
– A baud rate register (SCIBRR)
– An extended prescaler receiver register (SCIER-
PR)
A Break character is interpreted on receiving “0”s
for some multiple of the frame period. At the end of
the last break frame the transmitter inserts an ex-
tra “1” bit to acknowledge the start bit.
– An extended prescaler transmitter register (SCI-
ETPR)
Refer to the register descriptions in Section 0.1.8
for the definitions of each bit.
Transmission and reception are driven by their
own baud rate generator.
Figure 89. Word Length Programming
9-bit Word length (M bit is set)
Possible
Next Data Frame
Parity
Data Frame
Start
Bit
Next
Start
Bit
Stop
Bit
Bit2
Bit6
Bit1
Bit3
Bit4
Bit5
Bit7
Bit8
Bit0
Bit
CLOCK
**
Start
Bit
Idle Frame
Start
Bit
Extra
’1’
Break Frame
** LBCL bit controls last data clock pulse
8-bit Word length (M bit is reset)
Possible
Next Data Frame
Parity
Bit
Data Frame
Next
Start
Bit
Start
Bit
Stop
Bit
Bit2
Bit6
Bit1
Bit3
Bit4
Bit5
Bit7
Bit0
CLOCK
**
Start
Bit
Idle Frame
Start
Bit
Extra
’1’
Break Frame
** LBCL bit controls last data clock pulse
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LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Master Only) (Cont’d)
10.8.4.2 Transmitter
When a frame transmission is complete (after the
stop bit or after the break frame) the TC bit is set
and an interrupt is generated if the TCIE is set and
the I bit is cleared in the CCR register.
The transmitter can send data words of either 8 or
9 bits depending on the M bit status. When the M
bit is set, word length is 9 bits and the 9th bit (the
MSB) has to be stored in the T8 bit in the SCICR1
register.
Clearing the TC bit is performed by the following
software sequence:
1. An access to the SCISR register
2. A write to the SCIDR register
When the transmit enable bit (TE) is set, the data
in the transmit shift register is output on the TDO
pin and the corresponding clock pulses are output
on the SCLK pin.
Note: The TDRE and TC bits are cleared by the
same software sequence.
Character Transmission
Break Characters
During an SCI transmission, data shifts out least
significant bit first on the TDO pin. In this mode,
the SCIDR register consists of a buffer (TDR) be-
tween the internal bus and the transmit shift regis-
ter (see Figure 2).
Setting the SBK bit loads the shift register with a
break character. The break frame length depends
on the M bit (see Figure 2).
As long as the SBK bit is set, the SCI send break
frames to the TDO pin. After clearing this bit by
software the SCI insert a logic 1 bit at the end of
the last break frame to guarantee the recognition
of the start bit of the next frame.
Procedure
– Select the M bit to define the word length.
– Select the desired baud rate using the SCIBRR
and the SCIETPR registers.
Idle Characters
Setting the TE bit drives the SCI to send an idle
frame before the first data frame.
– Set the TE bit to send an idle frame as first trans-
mission.
Clearing and then setting the TE bit during a trans-
mission sends an idle frame after the current word.
– Access the SCISR register and write the data to
send in the SCIDR register (this sequence clears
the TDRE bit). Repeat this sequence for each
data to be transmitted.
Note: Resetting and setting the TE bit causes the
data in the TDR register to be lost. Therefore the
best time to toggle the TE bit is when the TDRE bit
is set, that is, before writing the next byte in the
SCIDR.
Clearing the TDRE bit is always performed by the
following software sequence:
1. An access to the SCISR register
2. A write to the SCIDR register
LIN Transmission
The TDRE bit is set by hardware and it indicates:
– The TDR register is empty.
The same procedure has to be applied for LIN
Master transmission with the following differences:
– Clear the M bit to configure 8-bit word length.
– The data transfer is beginning.
– Set the LINE bit to enter LIN master mode. In this
case, setting the SBK bit sends 13 low bits.
– The next data can be written in the SCIDR regis-
ter without overwriting the previous data.
This flag generates an interrupt if the TIE bit is set
and the I bit is cleared in the CCR register.
When a transmission is taking place, a write in-
struction to the SCIDR register stores the data in
the TDR register and which is copied in the shift
register at the end of the current transmission.
When no transmission is taking place, a write in-
struction to the SCIDR register places the data di-
rectly in the shift register, the data transmission
starts, and the TDRE bit is immediately set.
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LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Master Only) (Cont’d)
10.8.4.3 Receiver
Overrun Error
The SCI can receive data words of either 8 or 9
bits. When the M bit is set, word length is 9 bits
and the MSB is stored in the R8 bit in the SCICR1
register.
An overrun error occurs when a character is re-
ceived when RDRF has not been reset. Data can-
not be transferred from the shift register to the
RDR register until the RDRF bit is cleared.
Character reception
When a overrun error occurs:
– The OR bit is set.
During a SCI reception, data shifts in least signifi-
cant bit first through the RDI pin. In this mode, the
SCIDR register consists or a buffer (RDR) be-
tween the internal bus and the received shift regis-
ter (see Figure 1 on page 19).
– The RDR content is not lost.
– The shift register is overwritten.
– An interrupt is generated if the RIE bit is set and
the I bit is cleared in the CCR register.
Procedure
The OR bit is reset by an access to the SCISR reg-
ister followed by a SCIDR register read operation.
– Select the M bit to define the word length.
– Select the desired baud rate using the SCIBRR
and the SCIERPR registers.
Noise Error
Oversampling techniques are used for data recov-
ery by discriminating between valid incoming data
and noise.
– Set the RE bit, this enables the receiver which
begins searching for a start bit.
When a character is received:
When noise is detected in a frame:
– The RDRF bit is set. It indicates that the content
of the shift register is transferred to the RDR.
– The NF is set at the rising edge of the RDRF bit.
– Data is transferred from the Shift register to the
SCIDR register.
– An interrupt is generated if the RIE bit is set and
the I bit is cleared in the CCR register.
– No interrupt is generated. However this bit rises
at the same time as the RDRF bit which itself
generates an interrupt.
– The error flags can be set if a frame error, noise
or an overrun error has been detected during re-
ception.
The NF bit is reset by a SCISR register read oper-
ation followed by a SCIDR register read operation.
Clearing the RDRF bit is performed by the following
software sequence done by:
Framing Error
1. An access to the SCISR register
2. A read to the SCIDR register.
A framing error is detected when:
– The stop bit is not recognized on reception at the
expected time, following either a de-synchroni-
zation or excessive noise.
The RDRF bit must be cleared before the end of the
reception of the next character to avoid an overrun
error.
– A break is received.
Break Character
When the framing error is detected:
– the FE bit is set by hardware
When a break character is received, the SCI han-
dles it as a framing error.
Idle Character
– Data is transferred from the Shift register to the
SCIDR register.
When an idle frame is detected, there is the same
procedure as a data received character plus an in-
terrupt if the ILIE bit is set and the I bit is cleared in
the CCR register.
– No interrupt is generated. However this bit rises
at the same time as the RDRF bit which itself
generates an interrupt.
The FE bit is reset by a SCISR register read oper-
ation followed by a SCIDR register read operation.
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LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Master Only) (Cont’d)
Figure 90. SCI Baud Rate and Extended Prescaler Block Diagram
TRANSMITTER
CLOCK
EXTENDED PRESCALER TRANSMITTER RATE CONTROL
SCIETPR
EXTENDED TRANSMITTER PRESCALER REGISTER
SCIERPR
EXTENDED RECEIVER PRESCALER REGISTER
RECEIVER
CLOCK
EXTENDED PRESCALER RECEIVER RATE CONTROL
EXTENDED PRESCALER
f
CPU
TRANSMITTER RATE
CONTROL
/PR
/16
SCIBRR
SCP1
SCT2
SCT1SCT0SCR2 SCR1SCR0
SCP0
RECEIVER RATE
CONTROL
CONVENTIONAL BAUD RATE GENERATOR
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LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Master Only) (Cont’d)
10.8.4.4 Conventional Baud Rate Generation
other than zero. The baud rates are calculated as
follows:
The baud rates for the receiver and transmitter (Rx
and Tx) are set independently and calculated as
follows
f
f
CPU
CPU
Rx =
16 ERPR*(PR*RR)
Tx =
:
16 ETPR*(PR*TR)
*
*
f
f
CPU
CPU
Rx =
Tx =
with:
(16 PR) RR
(16 PR) TR
*
*
*
*
ETPR = 1, ..., 255 (see SCIETPR register)
ERPR = 1, ..., 255 (see SCIERPR register)
10.8.4.6 Receiver Muting and Wake-up Feature
with:
PR = 1, 3, 4 or 13 (see SCP[1:0] bits)
TR = 1, 2, 4, 8, 16, 32, 64, 128
(see SCT[2:0] bits)
In multiprocessor configurations it is often desira-
ble that only the intended message recipient
should actively receive the full message contents,
thus reducing redundant SCI service overhead for
all non addressed receivers.
RR = 1, 2, 4, 8, 16, 32, 64, 128
(see SCR[2:0] bits)
All these bits are in the SCIBRR register.
The non addressed devices may be placed in
sleep mode by means of the muting function.
Example: If f is 8 MHz (normal mode) and if
CPU
PR = 13 and TR = RR = 1, the transmit and re-
ceive baud rates are 38400 baud.
Setting the RWU bit by software puts the SCI in
sleep mode:
Note: The baud rate registers MUST NOT be
changed while the transmitter or the receiver is en-
abled.
All the reception status bits cannot be set.
All the receive interrupts are inhibited.
A muted receiver may be awakened by one of the
following two ways:
10.8.4.5 Extended Baud Rate Generation
The extended prescaler option gives a very fine
tuning on the baud rate, using a 255 value prescal-
er, whereas the conventional Baud Rate Genera-
tor retains industry standard software compatibili-
ty.
– by Idle Line detection if the WAKE bit is reset,
– by Address Mark detection if the WAKE bit is set.
Receiver wakes-up by Idle Line detection when
the Receive line has recognized an Idle Frame.
Then the RWU bit is reset by hardware but the
IDLE bit is not set.
The extended baud rate generator block diagram
is described in the Figure 3.
Receiver wakes-up by Address Mark detection
when it received a “1” as the most significant bit of
a word, thus indicating that the message is an ad-
dress. The reception of this particular word wakes
up the receiver, resets the RWU bit and sets the
RDRF bit, which allows the receiver to receive this
word normally and to use it as an address word.
The output clock rate sent to the transmitter or to
the receiver is the output from the 16 divider divid-
ed by a factor ranging from 1 to 255 set in the SCI-
ERPR or the SCIETPR register.
Note: The extended prescaler is activated by set-
ting the SCIETPR or SCIERPR register to a value
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LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Master Only) (Cont’d)
10.8.4.7 Parity control
even number of “1s” if even parity is selected
(PS = 0) or an odd number of “1s” if odd parity is
selected (PS = 1). If the parity check fails, the PE
flag is set in the SCISR register and an interrupt is
generated if PIE is set in the SCICR1 register.
Parity control (generation of parity bit in transmis-
sion and parity checking in reception) can be ena-
bled by setting the PCE bit in the SCICR1 register.
Depending on the frame length defined by the M
bit, the possible SCI frame formats are as listed in
Table 1.
10.8.5 Low Power Modes
Table 24. Frame Formats
Mode
Description
No effect on SCI.
M bit
PCE bit
SCI frame
WAIT
SCI interrupts cause the device to exit from
Wait mode.
0
1
0
1
| SB | 8 bit data | STB |
| SB | 7-bit data | PB | STB |
| SB | 9-bit data | STB |
| SB | 8-bit data PB | STB |
0
SCI registers are frozen.
1
HALT
In Halt mode, the SCI stops transmitting/re-
ceiving until Halt mode is exited.
Legend:
SB: Start Bit
10.8.6 Interrupts
Interrupt Event
STB: Stop Bit
PB: Parity Bit
Enable Exit
Control from from
Exit
Event
Flag
Bit
Wait
Halt
Note: In case of wake up by an address mark, the
MSB bit of the data is taken into account and not
the parity bit
TransmitDataRegister
Empty
TDRE
TC
TIE
Transmission Com-
plete
Even parity: The parity bit is calculated to obtain
an even number of “1s” inside the frame made of
the 7 or 8 LSB bits (depending on whether M is
equal to 0 or 1) and the parity bit.
TCIE
RIE
Received Data Ready
to be Read
RDRF
OR
Yes
No
Overrun Error Detect-
ed
Example: data = 00110101; 4 bits set => parity bit
is 0 if even parity is selected (PS bit = 0).
Idle Line Detected
Parity Error
IDLE
PE
ILIE
PIE
Odd parity: The parity bit is calculated to obtain
an odd number of “1s” inside the frame made of
the 7 or 8 LSB bits (depending on whether M is
equal to 0 or 1) and the parity bit.
The SCI interrupt events are connected to the
same interrupt vector.
Example: data = 00110101; 4 bits set => parity bit
is 1 if odd parity is selected (PS bit = 1).
These events generate an interrupt if the corre-
sponding Enable Control Bit is set and the inter-
rupt mask in the CC register is reset (RIM instruc-
tion).
Transmission mode: If the PCE bit is set then the
MSB bit of the data written in the data register is
not transmitted but is changed by the parity bit.
Reception mode: If the PCE bit is set then the in-
terface checks if the received data byte has an
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ST72561
LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Master Only) (Cont’d)
10.8.7 SCI Synchronous Transmission
These options allow the user to serially control pe-
ripherals which consist of shift registers, without
losing any functions of the SCI transmitter which
can still talk to other SCI receivers. These options
do not affect the SCI receiver which is independ-
ent from the transmitter.
The SCI transmitter allows the user to control a
one way synchronous serial transmission. The
SCLK pin is the output of the SCI transmitter clock.
No clock pulses are sent to the SCLK pin during
start bit and stop bit. Depending on the state of the
LBCL bit in the SCICR3 register, clock pulses are
or are not be generated during the last valid data
bit (address mark). The CPOL bit in the SCICR3
register allows the user to select the clock polarity,
and the CPHA bit in the SCICR3 register allows
the user to select the phase of the external clock
(see Figure 4, Figure 5 and Figure 6).
Note: The SCLK pin works in conjunction with the
TDO pin. When the SCI transmitter is disabled (TE
and RE = 0), the SCLK and TDO pins go into high
impedance state.
Note: The LBCL, CPOL and CPHA bits have to be
selected before enabling the transmitter to ensure
that the clock pulses function correctly. These bits
should not be changed while the transmitter is en-
abled.
During idle, preamble and send break, the external
SCLK clock is not activated.
Figure 91. SCI Example of Synchronous and Asynchronous Transmission
Data out
Data in
RDI
Asynchronous
(e.g. modem)
TDO
SCI
Data in
Clock
Synchronous
SCLK
(e.g. shift register)
Enable
Output port
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LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Master Only) (Cont’d)
Figure 92. SCI Data Clock Timing Diagram (M = 0)
Idle or preceding
Idle or next
transmission
Start
Stop
M = 0 (8 data bits)
transmission
Clock (CPOL=0, CPHA=0)
*
Clock (CPOL=0, CPHA=1)
Clock (CPOL=1, CPHA=0)
*
*
*
Clock (CPOL=1, CPHA=1)
Data
0
1
2
3
4
5
6
7
MSB Stop
Start LSB
* LBCL bit controls last data clock pulse
Figure 93. SCI Data Clock Timing Diagram (M = 1)
Idle or preceding
Start
M = 1 (9 data bits)
Idle or next
Stop
transmission
transmission
Clock (CPOL=0, CPHA=0)
*
Clock (CPOL=0, CPHA=1)
Clock (CPOL=1, CPHA=0)
*
*
*
Clock (CPOL=1, CPHA=1)
Data
8
0
1
2
3
4
5
6
7
MSB Stop
Start LSB
* LBCL bit controls last data clock pulse
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LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Master Only) (Cont’d)
10.8.8 Register Description
Note: The IDLE bit is not be set again until the
RDRF bit has been set itself (that is, a new idle line
occurs).
STATUS REGISTER (SCISR)
Read Only
Reset Value: 1100 0000 (C0h)
Bit 3 = OR Overrun error.
7
0
This bit is set by hardware when the word currently
being received in the shift register is ready to be
transferred into the RDR register while RDRF = 1.
An interrupt is generated if RIE = 1 in the SCICR2
register. It is cleared by a software sequence (an
access to the SCISR register followed by a read to
the SCIDR register).
TDRE
TC
RDRF IDLE
OR
NF
FE
PE
Bit 7 = TDRE Transmit data register empty.
This bit is set by hardware when the content of the
TDR register has been transferred into the shift
register. An interrupt is generated if the TIE bit = 1
in the SCICR2 register. It is cleared by a software
sequence (an access to the SCISR register fol-
lowed by a write to the SCIDR register).
0: No Overrun error
1: Overrun error is detected
Note: When this bit is set, the RDR register con-
tent is not lost but the shift register is overwritten.
0: Data is not transferred to the shift register
1: Data is transferred to the shift register
Bit 2 = NF Noise flag.
Note: Data is not be transferred to the shift register
This bit is set by hardware when noise is detected
on a received frame. It is cleared by a software se-
quence (an access to the SCISR register followed
by a read to the SCIDR register).
0: No noise is detected
until the TDRE bit is cleared.
Bit 6 = TC Transmission complete.
This bit is set by hardware when transmission of a
frame containing Data is complete. An interrupt is
generated if TCIE = 1 in the SCICR2 register. It is
cleared by a software sequence (an access to the
SCISR register followed by a write to the SCIDR
register).
1: Noise is detected
Note: This bit does not generate interrupt as it ap-
pears at the same time as the RDRF bit which it-
self generates an interrupt.
0: Transmission is not complete
1: Transmission is complete
Bit 1 = FE Framing error.
This bit is set by hardware when a de-synchroniza-
tion, excessive noise or a break character is de-
tected. It is cleared by a software sequence (an
access to the SCISR register followed by a read to
the SCIDR register).
Note: TC is not set after the transmission of a Pre-
amble or a Break.
Bit 5 = RDRF Received data ready flag.
This bit is set by hardware when the content of the
RDR register has been transferred to the SCIDR
register. An interrupt is generated if RIE = 1 in the
SCICR2 register. It is cleared by a software se-
quence (an access to the SCISR register followed
by a read to the SCIDR register).
0: No Framing error is detected
1: Framing error or break character is detected
Note: This bit does not generate an interrupt as it
appears at the same time as the RDRF bit which it-
self generates an interrupt. If the word currently
being transferred causes both frame error and
overrun error, it is transferred and only the OR bit
is set.
0: Data is not received
1: Received data is ready to be read
Bit 4 = IDLE Idle line detect.
This bit is set by hardware when an Idle Line is de-
tected. An interrupt is generated if the ILIE = 1 in
the SCICR2 register. It is cleared by a software se-
quence (an access to the SCISR register followed
by a read to the SCIDR register).
Bit 0 = PE Parity error.
This bit is set by hardware when a parity error oc-
curs in receiver mode. It is cleared by a software
sequence (a read to the status register followed by
an access to the SCIDR data register). An inter-
rupt is generated if PIE = 1 in the SCICR1 register.
0: No parity error
0: No Idle Line is detected
1: Idle Line is detected
1: Parity error
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LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Master Only) (Cont’d)
CONTROL REGISTER 1 (SCICR1)
Read/Write
Bit 3 = WAKE Wake-Up method.
This bit determines the SCI Wake-Up method, it is
set or cleared by software.
0: Idle Line
Reset Value: x000 0000 (x0h)
7
0
1: Address Mark
R8
T8
SCID
M
WAKE PCE
PS
PIE
Bit 2 = PCE Parity control enable.
This bit selects the hardware parity control (gener-
ation and detection). When the parity control is en-
abled, the computed parity is inserted at the MSB
position (9th bit if M = 1; 8th bit if M = 0) and parity
is checked on the received data. This bit is set and
cleared by software. Once it is set, PCE is active
after the current byte (in reception and in transmis-
sion).
Bit 7 = R8 Receive data bit 8.
This bit is used to store the 9th bit of the received
word when M = 1.
Bit 6 = T8 Transmit data bit 8.
This bit is used to store the 9th bit of the transmit-
ted word when M = 1.
0: Parity control disabled
1: Parity control enabled
Bit 5 = SCID Disabled for low power consumption
When this bit is set the SCI prescalers and outputs
are stopped and the end of the current byte trans-
fer in order to reduce power consumption.This bit
is set and cleared by software.
0: SCI enabled
1: SCI prescaler and outputs disabled
Bit 1 = PS Parity selection.
This bit selects the odd or even parity when the
parity generation/detection is enabled (PCE bit
set). It is set and cleared by software. The parity is
selected after the current byte.
0: Even parity
1: Odd parity
Bit 4 = M Word length.
This bit determines the word length. It is set or
cleared by software.
0: 1 Start bit, 8 Data bits, 1 Stop bit
1: 1 Start bit, 9 Data bits, 1 Stop bit
Bit 0 = PIE Parity interrupt enable.
This bit enables the interrupt capability of the hard-
ware parity control when a parity error is detected
(PE bit set). It is set and cleared by software.
0: Parity error interrupt disabled
Note: The M bit must not be modified during a data
transfer (both transmission and reception).
1: Parity error interrupt enabled
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LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Master Only) (Cont’d)
CONTROL REGISTER 2 (SCICR2)
Read/Write
Bit 2 = RE Receiver enable.
This bit enables the receiver. It is set and cleared
by software.
Reset Value: 0000 0000 (00h)
0: Receiver is disabled
7
0
1: Receiver is enabled and begins searching for a
start bit
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
Bit 1 = RWU Receiver wake-up.
Bit 7 = TIE Transmitter interrupt enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever
TDRE = 1 in the SCISR register
This bit determines if the SCI is in mute mode or
not. It is set and cleared by software and can be
cleared by hardware when a wake-up sequence is
recognized.
0: Receiver in active mode
1: Receiver in mute mode
Bit 6 = TCIE Transmission complete interrupt ena-
ble
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever TC = 1
in the SCISR register
Notes:
– Before selecting Mute mode (by setting the RWU
bit) the SCI must first receive a data byte, other-
wise it cannot function in Mute mode with wake-
up by Idle line detection.
– In Address Mark Detection Wake-Up configura-
tion (WAKE bit = 1) the RWU bit cannot be mod-
ified by software while the RDRF bit is set.
Bit 5 = RIE Receiver interrupt enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever OR = 1
or RDRF = 1 in the SCISR register
Bit 0 = SBK Send break.
This bit set is used to send break characters. It is
set and cleared by software.
0: No break character is transmitted
1: Break characters are transmitted
Bit 4 = ILIE Idle line interrupt enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever
IDLE = 1 in the SCISR register.
Note: If the SBK bit is set to “1” and then to “0”, the
transmitter sends a BREAK word at the end of the
current word.
Bit 3 = TE Transmitter enable.
This bit enables the transmitter. It is set and
cleared by software.
0: Transmitter is disabled
1: Transmitter is enabled
Notes:
– During transmission, a “0” pulse on the TE bit
(“0” followed by “1”) sends a preamble (idle line)
after the current word.
– When TE is set there is a 1 bit-time delay before
the transmission starts.
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LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Master Only) (Cont’d)
CONTROL REGISTER 3 (SCICR3)
Read/Write
0: Steady low value on SCLK pin outside transmis-
sion window.
1: Steady high value on SCLK pin outside trans-
mission window.
Reset Value: 0000 0000 (00h)
7
0
Bit 1 = CPHA Clock Phase.
-
LINE
-
-
CLKEN CPOL CPHA
LBCL
This bit allows the user to select the phase of the
clock output on the SCLK pin. It works in conjunc-
tion with the CPOL bit to produce the desired
clock/data relationship (see Figure 5 and Figure 6)
0: SCLK clock line activated in middle of data bit.
1: SCLK clock line activated at beginning of data
bit.
Bit 7 = Reserved, must be kept cleared.
Bit 6 = LINE LIN Mode Enable.
This bit is set and cleared by software.
0: LIN Mode disabled
1: LIN Master mode enabled
Bit 0 = LBCL Last bit clock pulse.
This bit allows the user to select whether the clock
pulse associated with the last data bit transmitted
(MSB) has to be output on the SCLK pin.
0: The clock pulse of the last data bit is not output
to the SCLK pin.
1: The clock pulse of the last data bit is output to
the SCLK pin.
The LIN Master mode enables the capability to
send LIN Synch Breaks (13 low bits) using the
SBK bit in the SCICR2 register
.In transmission, the LIN Synch Break low phase
duration is shown as below:
Number of low bits sent
during a LIN Synch Break
LINE
M
Note: The last bit is the 8th or 9th data bit transmit-
ted depending on the 8 or 9 bit format selected by
the M bit in the SCICR1 register.
0
1
0
1
10
11
13
14
0
1
Table 25. SCI clock on SCLK pin
Data
format
Number of clock
pulses on SCLK
M bit
LBCL bit
Bits 5:4 = Reserved, forced by hardware to 0.
These bits are not used.
0
1
0
1
7
8
8
9
8 bit
9 bit
0
1
Bit 3 = CLKEN Clock Enable.
This bit allows the user to enable the SCLK pin.
0: SLK pin disabled
1: SLK pin enabled
Note: These 3 bits (CPOL, CPHA, LBCL) should
not be written while the transmitter is enabled.
Bit 2 = CPOL Clock Polarity.
This bit allows the user to select the polarity of the
clock output on the SCLK pin. It works in conjunc-
tion with the CPHA bit to produce the desired
clock/data relationship (see Figure 5 and Figure
6).
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ST72561
LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Master Only) (Cont’d)
DATA REGISTER (SCIDR)
Read/Write
Bits 5:3 = SCT[2:0] SCI Transmitter rate divisor
These 3 bits, in conjunction with the SCP1 and
SCP0 bits define the total division applied to the
bus clock to yield the transmit rate clock in conven-
tional Baud Rate Generator mode.
Reset Value: Undefined
Contains the Received or Transmitted data char-
acter, depending on whether it is read from or writ-
ten to.
TR dividing factor
SCT2
SCT1
SCT0
1
2
0
1
0
1
0
1
0
1
0
7
0
0
4
DR7
DR6
DR5
DR4
DR3
DR2
DR1
DR0
1
0
1
8
16
32
64
128
The Data register performs a double function (read
and write) since it is composed of two registers,
one for transmission (TDR) and one for reception
(RDR).
The TDR register provides the parallel interface
between the internal bus and the output shift reg-
ister (see Figure 1 on page 19).
The RDR register provides the parallel interface
between the input shift register and the internal
bus (see Figure 1).
1
Note: This TR factor is used only when the ETPR
fine tuning factor is equal to 00h; otherwise, TR is
replaced by the (TR*ETPR) dividing factor.
Bits 2:0 = SCR[2:0] SCI Receiver rate divisor.
These 3 bits, in conjunction with the SCP1 and
SCP0 bits define the total division applied to the
bus clock to yield the receive rate clock in conven-
tional Baud Rate Generator mode.
BAUD RATE REGISTER (SCIBRR)
Read/Write
Reset Value: 0000 0000 (00h)
7
0
RR dividing factor
SCR2
SCR1
SCR0
1
2
0
1
0
1
0
1
0
1
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0
0
0
4
Bits 7:6 = SCP[1:0] First SCI Prescaler
These 2 prescaling bits allow several standard
clock division ranges:
1
0
1
8
16
32
64
128
PR Prescaling factor
SCP1
SCP0
1
1
3
0
1
0
1
0
4
1
Note: This RR factor is used only when the ERPR
fine tuning factor is equal to 00h; otherwise, RR is
replaced by the (RR*ERPR) dividing factor.
13
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ST72561
LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Master Only) (Cont’d)
EXTENDED RECEIVE PRESCALER DIVISION
REGISTER (SCIERPR)
EXTENDED TRANSMIT PRESCALER DIVISION
REGISTER (SCIETPR)
Read/Write
Read/Write
Reset Value: 0000 0000 (00h)
Reset Value:0000 0000 (00h)
7
0
7
0
ERPR ERPR ERPR ERPR ERPR ERPR ERPR ERPR
ETPR ETPR ETPR ETPR ETPR ETPR ETPR ETPR
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Bits 7:0 = ERPR[7:0] 8-bit Extended Receive
Prescaler Register.
Bits 7:0 = ETPR[7:0] 8-bit Extended Transmit
Prescaler Register.
The extended Baud Rate Generator is activated
when a value other than 00h is stored in this regis-
ter. The clock frequency from the 16 divider (see
Figure 3) is divided by the binary factor set in the
SCIERPR register (in the range 1 to 255).
The extended Baud Rate Generator is activated
when a value other than 00h is stored in this regis-
ter. The clock frequency from the 16 divider (see
Figure 3) is divided by the binary factor set in the
SCIETPR register (in the range 1 to 255).
The extended baud rate generator is not active af-
ter a reset.
The extended baud rate generator is not active af-
ter a reset.
Table 26. Baud Rate Selection
Conditions
Baud
Rate
Symbol
Parameter
Standard
Unit
Accuracy vs.
Standard
f
Prescaler
CPU
Conventional Mode
TR (or RR) = 128, PR = 13
TR (or RR) = 32, PR = 13
TR (or RR) = 16, PR =13
TR (or RR) = 8, PR = 13
TR (or RR) = 4, PR = 13
TR (or RR) = 16, PR = 3
TR (or RR) = 2, PR = 13
TR (or RR) = 1, PR =13
300
~300.48
1200 ~1201.92
2400 ~2403.84
4800 ~4807.69
9600 ~9615.38
10400 ~10416.67
19200 ~19230.77
38400 ~38461.54
~0.16%
~0.79%
f
Communication
frequency
Tx
8 MHz
Hz
f
Rx
Extended Mode
ETPR (or ERPR) = 35,
TR (or RR) = 1, PR = 1
14400 ~14285.71
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ST72561
LINSCI™ SERIAL COMMUNICATIONS INTERFACE (LIN Master) (Cont’d)
Table 27. LINSCI2 Register Map and Reset Values
Address
(Hex.)
Register
Name
7
6
5
4
3
2
1
0
SCI2SR
TDRE
TC
RDRF
IDLE
OR
NF
FE
PE
60
61
62
63
64
65
66
67
Reset Value
SCI2DR
1
DR7
-
1
DR6
-
0
0
0
0
DR2
-
0
DR1
-
0
DR0
-
DR5
DR4
DR3
Reset Value
SCI2BRR
-
-
-
SCP1
0
SCP0
0
SCT2
SCT1
SCT0
SCR2
0
SCR1
0
SCR0
0
Reset Value
SCI2CR1
0
0
M
-
0
R8
-
T8
SCID
WAKE
PCE
PS
PIE
Reset Value
SCI2CR2
-
-
RIE
0
-
TIE
0
TCIE
0
ILIE
0
TE
RE
0
RWU
SBK
0
Reset Value
SCI2CR3
0
CLKEN
0
0
CPHA
0
LINE
0
-
-
CPOL
0
LBCL
0
Reset Value
SCI2ERPR
Reset Value
SCI2ETPR
Reset Value
0
0
0
ERPR7
0
ERPR6
0
ERPR5 ERPR4
ERPR3
0
ERPR2
0
ERPR1
0
ERPR0
0
0
0
ETPR7
0
ETPR6
0
ETPR5
0
ETPR4
0
ETPR3
0
ETPR2
0
ETPR1
0
ETPR0
0
170/263
ST72561
10.9 beCAN CONTROLLER (beCAN)
The beCAN controller (Basic Enhanced CAN), in-
terfaces the CAN network and supports the CAN
protocol version 2.0A and B. It has been designed
to manage high number of incoming messages ef-
ficiently with a minimum CPU load. It also meets
the priority requirements for transmit messages.
10.9.2 General Description
In today’s CAN applications, the number of nodes
in a network is increasing and often several net-
works are linked together via gateways. Typically
the number of messages in the system (and thus
to be handled by each node) has significantly in-
creased. In addition to the application messages,
Network Management and Diagnostic messages
have been introduced.
10.9.1 Main Features
■ Supports CAN protocol version 2.0 A, B Active
■ Bit rates up to 1Mbit/s
Transmission
■ 2 transmit mailboxes
■ Configurable transmit priority
Reception
– An enhanced filtering mechanism is required to
handle each type of message.
Furthermore, application tasks require more CPU
time, therefore real-time constraints caused by
message reception have to be reduced.
■ 1 receive FIFO with three stages
■ 6 scalable filter banks
■ Identifier list feature
■ Configurable FIFO overrun
Management
– A receive FIFO scheme allows the CPU to be
dedicated to application tasks for a long time pe-
riod without losing messages.
The standard HLP (Higher Layer Protocol) based
on standard CAN drivers requires an efficient in-
terface to the CAN controller.
■ Maskable interrupts
– All mailboxes and registers are organized in 16-
byte pages mapped at the same address and se-
lected via a page select register.
■ Software-efficient mailbox mapping at a unique
address space
Figure 94. CAN Network Topology
ST9 MCU
Application
CAN
Controller
CAN
Rx
CAN
Tx
CAN
Transceiver
CAN
High
CAN
Low
CAN Bus
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beCAN CONTROLLER (Cont’d)
CAN 2.0B Active Core
Tx Mailboxes
The beCAN module handles the transmission and
the reception of CAN messages fully autonomous-
ly. Standard identifiers (11-bit) and extended iden-
tifiers (29-bit) are fully supported by hardware.
Two transmit mailboxes are provided to the soft-
ware for setting up messages. The Transmission
Scheduler decides which mailbox has to be trans-
mitted first.
Control, Status and Configuration Registers
The application uses these registers to:
– Configure CAN parameters, e.g.baud rate
– Request transmissions
Acceptance Filters
The beCAN provides six scalable/configurable
identifier filter banks for selecting the incoming
messages the software needs and discarding the
others.
– Handle receptions
Receive FIFO
– Manage interrupts
The receive FIFO is used by the CAN controller to
store the incoming messages. Three complete
messages can be stored in the FIFO. The software
always accesses the next available message at
the same address. The FIFO is managed com-
pletely by hardware.
– Get diagnostic information
Figure 95. CAN Block Diagram
Receive FIFO
2
Tx Mailboxes
Master Control
Master Status
Mailbox 1
1
Mailbox 0
Transmit Status
Transmit Prio
Receive FIFO
Interrupt Enable
Page Select
Mailbox 0
Error Status
Acceptance Filters
Error Int. Enable
Tx Error Counter
Rx Error Counter
Diagnostic
5
4
Transmission
Scheduler
3
2
1
Filter
0
Bit Timing
CAN 2.0B Active Core
Filter Master
Filter Config.
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beCAN CONTROLLER (Cont’d)
Figure 96. beCAN Operating Modes
RESET
SLEEP
SLAK= 1
INAK = 0
SYNC
SLAK= X
INAK = X
NORMAL
INITIALIZATION
SLAK= 0
INAK = 1
SLAK= 0
INAK = 0
INRQ
10.9.3 Operating Modes
tus of the CAN bus output CANTX is recessive
(high).
The beCAN has three main operating modes: Ini-
tialization, Normal and Sleep. After a hardware re-
set, beCAN is in Sleep mode to reduce power con-
sumption. The software requests beCAN to enter
Initialization or Sleep mode by setting the INRQ or
SLEEP bits in the CMCR register. Once the mode
has been entered, beCAN confirms it by setting
the INAK or SLAK bits in the CMSR register. When
neither INAK nor SLAK are set, beCAN is in Nor-
mal mode. Before entering Normal mode beCAN
always has to synchronize on the CAN bus. To
synchronize, beCAN waits until the CAN bus is
idle, this means 11 consecutive recessive bits
have been monitored on CANRX.
Entering Initialization Mode does not change any
of the configuration registers.
To initialize the CAN Controller, software has to
set up the Bit Timing registers and the filter banks.
If a filter bank is not used, it is recommended to
leave it non active (leave the corresponding FACT
bit cleared).
10.9.3.2 Normal Mode
Once the initialization has been done, the software
must request the hardware to enter Normal mode,
to synchronize on the CAN bus and start reception
and transmission. Entering Normal mode is done
by clearing the INRQ bit in the CMCR register and
waiting until the hardware has confirmed the re-
quest by clearing the INAK bit in the CMSR regis-
ter. Afterwards, the beCAN synchronizes with the
data transfer on the CAN bus by waiting for the oc-
currence of a sequence of 11 consecutive reces-
sive bits (≡ Bus Idle) before it can take part in bus
activities and start message transfer.
10.9.3.1 Initialization Mode
The software initialization can be done while the
hardware is in Initialization mode. To enter this
mode the software sets the INRQ bit in the CMCR
register and waits until the hardware has con-
firmed the request by setting the INAK bit in the
CMSR register.
To leave Initialization mode, the software clears
the INQR bit. beCAN has left Initialization mode
once the INAK bit has been cleared by hardware.
The initialization of the filter values is independent
from Initialization mode but must be done while the
filter bank is not active (corresponding FACTx bit
cleared). The filter bank scale and mode configu-
ration must be configured in initialization mode.
While in Initialization mode, all message transfers
to and from the CAN bus are stopped and the sta-
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beCAN CONTROLLER (Cont’d)
10.9.3.3 Low Power Mode (Sleep)
without affecting it by the transmission of dominant
bits (Acknowledge Bits, Error Frames).
To reduce power consumption, beCAN has a low
power mode called Sleep mode. This mode is en-
tered on software request by setting the SLEEP bit
in the CMCR register. In this mode, the beCAN
clock is stopped. Consequently, software can still
access the beCAN registers and mailboxes but the
beCAN will not update the status bits.
Figure 97. beCAN in Silent Mode
beCAN
Tx
Rx
Example: If software requests entry to initializa-
tion mode by setting the INRQ bit while beCAN is
in sleep mode, it will not be acknowledged by the
hardware, INAK stays cleared.
=1
beCAN can be woken up (exit Sleep mode) either
by software clearing the SLEEP bit or on detection
of CAN bus activity.
CANTX CANRX
10.9.3.6 Loop Back Mode
On CAN bus activity detection, hardware automat-
ically performs the wake-up sequence by clearing
the SLEEP bit if the AWUM bit in the CMCR regis-
ter is set. If the AWUM bit is cleared, software has
to clear the SLEEP bit when a wake-up interrupt
occurs, in order to exit from sleep mode.
The beCAN can be set in Loop Back Mode by set-
ting the LBKM bit in the CDGR register. In Loop
Back Mode, the beCAN treats its own transmitted
messages as received messages and stores them
(if they pass acceptance filtering) in the FIFO.
Note: If the wake-up interrupt is enabled (WKUIE
bit set in CIER register) a wake-up interrupt will be
generated on detection of CAN bus activity, even if
the beCAN automatically performs the wake-up
sequence.
Figure 98. beCAN in Loop Back Mode
After the SLEEP bit has been cleared, Sleep mode
is exited once beCAN has synchronized with the
CAN bus, refer to Figure 3. beCAN Operating
Modes. The sleep mode is exited once the SLAK
bit has been cleared by hardware.
beCAN
Tx
Rx
10.9.3.4 Test Mode
Test mode can be selected by the SILM and LBKM
bits in the CDGR register. These bits must be con-
figured while beCAN is in Initialization mode. Once
test mode has been selected, beCAN is started in
Normal mode.
CANTX CANRX
10.9.3.5 Silent Mode
The beCAN can be put in Silent mode by setting
the SILM bit in the CDGR register.
This mode is provided for self-test functions. To be
independent of external events, the CAN Core ig-
nores acknowledge errors (no dominant bit sam-
pled in the acknowledge slot of a data / remote
frame) in Loop Back Mode. In this mode, the be-
CAN performs an internal feedback from its Tx
output to its Rx input. The actual value of the CAN-
RX input pin is disregarded by the beCAN. The
transmitted messages can be monitored on the
CANTX pin.
In Silent mode, the beCAN is able to receive valid
data frames and valid remote frames, but it sends
only recessive bits on the CAN bus and it cannot
start a transmission. If the beCAN has to send a
dominant bit (ACK bit, overload flag, active error
flag), the bit is rerouted internally so that the CAN
Core monitors this dominant bit, although the CAN
bus may remain in recessive state. Silent mode
can be used to analyze the traffic on a CAN bus
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beCAN CONTROLLER (Cont’d)
10.9.3.7 Loop Back combined with Silent Mode
bitration Lost, and/or the TERR bit, in case of
transmission error detection.
It is also possible to combine Loop Back mode and
Silent mode by setting the LBKM and SILM bits in
the CDGR register. This mode can be used for a
“Hot Selftest”, meaning the beCAN can be tested
like in Loop Back mode but without affecting a run-
ning CAN system connected to the CANTX and
CANRX pins. In this mode, the CANRX pin is dis-
connected from the beCAN and the CANTX pin is
held recessive.
Transmit Priority
By Identifier:
When more than one transmit mailbox is pending,
the transmission order is given by the identifier of
the message stored in the mailbox. The message
with the lowest identifier value has the highest pri-
ority according to the arbitration of the CAN proto-
col. If the identifier values are equal, the lower
mailbox number will be scheduled first.
Figure 99. beCAN in Combined Mode
By Transmit Request Order:
beCAN
The transmit mailboxes can be configured as a
transmit FIFO by setting the TXFP bit in the CMCR
register. In this mode the priority order is given by
the transmit request order.
Tx
Rx
This mode is very useful for segmented transmis-
sion.
=1
Abort
A transmission request can be aborted by the user
setting the ABRQ bit in the MCSR register. In
pending or scheduled state, the mailbox is abort-
ed immediately. An abort request while the mail-
box is in transmit state can have two results. If the
mailbox is transmitted successfully the mailbox
becomes empty with the TXOK bit set in the
MCSR and CTSR registers. If the transmission
fails, the mailbox becomes scheduled, the trans-
mission is aborted and becomes empty with
TXOK cleared. In all cases the mailbox will be-
come empty again at least at the end of the cur-
rent transmission.
CANTX CANRX
10.9.4 Functional Description
10.9.4.1 Transmission Handling
In order to transmit a message, the application
must select one empty transmit mailbox, set up
the identifier, the data length code (DLC) and the
data before requesting the transmission by setting
the corresponding TXRQ bit in the MCSR register.
Once the mailbox has left empty state, the soft-
ware no longer has write access to the mailbox
registers. Immediately after the TXRQ bit has
been set, the mailbox enters pending state and
waits to become the highest priority mailbox, see
Transmit Priority. As soon as the mailbox has the
highest priority it will be scheduled for transmis-
sion. The transmission of the message of the
scheduled mailbox will start (enter transmit state)
when the CAN bus becomes idle. Once the mail-
box has been successfully transmitted, it will be-
come empty again. The hardware indicates a suc-
cessful transmission by setting the RQCP and
TXOK bits in the MCSR and CTSR registers.
Non-Automatic Retransmission Mode
To configure the hardware in this mode the NART
bit in the CMCR register must be set.
In this mode, each transmission is started only
once. If the first attempt fails, due to an arbitration
loss or an error, the hardware will not automatical-
ly restart the message transmission. At the end of
the first transmission attempt, the hardware con-
siders the request as completed and sets the
RQCP bit in the MCSR register. The result of the
transmission is indicated in the MCSR register by
the TXOK, ALST and TERR bits.
If the transmission fails, the cause is indicated by
the ALST bit in the MCSR register in case of an Ar-
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beCAN CONTROLLER (Cont’d)
Figure 100. Transmit Mailbox States
EMPTY
RQCP=X
TXOK=X
TXRQ=1
TME = 1
PENDING
RQCP=0
TXOK=0
TME = 0
Mailbox has
highest priority
ABRQ=1
EMPTY
Mailbox does not
have highest priority
SCHEDULED
RQCP=0
TXOK=0
RQCP=1
TXOK=0
TME = 1
ABRQ=1
TME = 0
CAN Bus = IDLE
TRANSMIT
Transmit failed * NART
Transmit failed * NART
RQCP=0
TXOK=0
TME = 0
EMPTY
Transmit succeeded
RQCP=1
TXOK=1
TME = 1
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beCAN CONTROLLER (Cont’d)
10.9.4.2 Reception Handling
A received message is considered as valid when it
has been received correctly according to the CAN
protocol (no error until the last but one bit of the
EOF field) and It passed through the identifier fil-
tering successfully, see Section 0.1.4.3 Identifier
Filtering.
For the reception of CAN messages, three
mailboxes organized as a FIFO are provided. In
order to save CPU load, simplify the software and
guarantee data consistency, the FIFO is managed
completely by hardware. The application accesses
the messages stored in the FIFO through the FIFO
output mailbox.
Valid Message
Figure 101. Receive FIFO states
EMPTY
FMP=0x00
FOVR=0
Valid Message
Received
PENDING_1
FMP=0x01
FOVR=0
Release
Mailbox
Valid Message
Received
Release
Mailbox
RFOM=1
PENDING_2
FMP=0x10
FOVR=0
Valid Message
Received
Release
Mailbox
RFOM=1
PENDING_3
FMP=0x11
FOVR=0
Valid Message
Received
OVERRUN
FMP=0x11
FOVR=1
Release
Mailbox
RFOM=1
Valid Message
Received
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ST72561
beCAN CONTROLLER (Cont’d)
FIFO Management
On overrun condition, the FOVR bit is set and an
interrupt is generated if the FOVIE bit in the CIER
register is set.
Starting from the empty state, the first valid mes-
sage received is stored in the FIFO which be-
comes pending_1. The hardware signals the
event setting the FMP[1:0] bits in the CRFR regis-
ter to the value 01b. The message is available in
the FIFO output mailbox. The software reads out
the mailbox content and releases it by setting the
RFOM bit in the CRFR register. The FIFO be-
comes empty again. If a new valid message has
been received in the meantime, the FIFO stays in
pending_1 state and the new message is availa-
ble in the output mailbox.
10.9.4.3 Identifier Filtering
In the CAN protocol the identifier of a message is
not associated with the address of a node but re-
lated to the content of the message. Consequently
a transmitter broadcasts its message to all receiv-
ers. On message reception a receiver node de-
cides - depending on the identifier value - whether
the software needs the message or not. If the mes-
sage is needed, it is copied into the RAM. If not,
the message must be discarded without interven-
tion by the software.
If the application does not release the mailbox, the
next valid message will be stored in the FIFO
which enters pending_2 state (FMP[1:0] = 10b).
The storage process is repeated for the next valid
message putting the FIFO into pending_3 state
(FMP[1:0] = 11b). At this point, the software must
release the output mailbox by setting the RFOM
bit, so that a mailbox is free to store the next valid
message. Otherwise the next valid message re-
ceived will cause a loss of message.
To fulfil this requirement, the beCAN Controller
provides six configurable and scalable filter banks
(0-5) in order to receive only the messages the
software needs. This hardware filtering saves
CPU resources which would be otherwise needed
to perform filtering by software. Each filter bank
consists of eight 8-bit registers, CFxR[0:7].
Scalable Width
To optimize and adapt the filters to the application
needs, each filter bank can be scaled independ-
ently. Depending on the filter scale a filter bank
provides:
Refer also to Section 0.1.4.4 Message Storage.
Overrun
Once the FIFO is in pending_3 state (that is, the
three mailboxes are full) the next valid message
reception will lead to an overrun and a message
will be lost. The hardware signals the overrun con-
dition by setting the FOVR bit in the CRFR regis-
ter. Which message is lost depends on the config-
uration of the FIFO:
– One 32-bit filter for the STDID[10:0], IDE, EX-
TID[17:0] and RTR bits.
– Two 16-bit filters for the STDID[10:0], RTR and
IDE bits.
– Four 8-bit filters for the STDID[10:3] bits. The
other bits are considered as “don’t care”.
– If the FIFO lock function is disabled (RFLM bit in
the CMCR register cleared) the last message
stored in the FIFO will be overwritten by the new
incoming message. In this case the latest mes-
sages will be always available to the application.
– One 16-bit filter and two 8-bit filters for filtering
the same set of bits as the 16 and 8-bit filters de-
scribed above.
Refer to Figure 9. Filter Bank Scale Configuration -
Register Organisation.
– If the FIFO lock function is enabled (RFLM bit in
the CMCR register set) the most recent message
will be discarded and the software will have the
three oldest messages in the FIFO available.
Furthermore, the filters can be configured in mask
mode or in identifier list mode.
Mask mode
Reception Related Interrupts
In mask mode the identifier registers are associat-
ed with mask registers specifying which bits of the
identifier are handled as “must match” or as “don’t
care”.
On the storage of the first message in the FIFO -
FMP[1:0] bits change from 00b to 01b - an inter-
rupt is generated if the FMPIE bit in the CIER reg-
ister is set.
Identifier List mode
When the FIFO becomes full (that is, a third mes-
sage is stored) the FULL bit in the CRFR register
is set and an interrupt is generated if the FFIE bit in
the CIER register is set.
In identifier list mode, the mask registers are
used as identifier registers. Thus instead of defin-
ing an identifier and a mask, two identifiers are
specified, doubling the number of single identifi-
ers. All bits of the incoming identifier must match
the bits specified in the filter registers.
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beCAN CONTROLLER (Cont’d)
Figure 102. Filter Bank Scale Configuration - Register Organisation
1
Filter Bank Scale Configuration
Filter Bank Scale Config. Bits
One 32-Bit Filter
FSCx = 3
CFxR2
Identifier
Mask/Ident.
CFxR0
CFxR4
CFxR1
CFxR5
CFxR3
CFxR7
CFxR6
STID10:3
STID2:0 RTR IDE EXID17:15
EXID14:7
EXID6:0
Bit Mapping
Two 16-Bit Filters
Identifier
Mask/Ident.
CFxR0
CFxR2
CFxR1
CFxR3
FSCx = 2
Identifier
Mask/Ident.
CFxR4
CFxR6
CFxR5
CFxR7
Bit Mapping
STID10:3
STID2:0 RTR IDE EXID17:15
One 16-Bit / Two 8-Bit Filters
Identifier
Mask/Ident.
CFxR0
CFxR2
CFxR1
CFxR3
Identifier
Mask/Ident.
CFxR4
CFxR5
FSCx = 1
Identifier
Mask/Ident.
CFxR6
CFxR7
Four 8-Bit Filters
Identifier
Mask/Ident.
CFxR0
CFxR1
Identifier
Mask/Ident.
CFxR2
CFxR3
FSCx = 0
Identifier
Mask/Ident.
CFxR4
CFxR5
Identifier
Mask/Ident.
CFxR6
CFxR7
STID10:3
x = filter bank number
1
These bits are located in the CFCR register
Bit Mapping
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beCAN CONTROLLER (Cont’d)
Filter Bank Scale and Mode Configuration
The filter banks are configured by means of the
corresponding CFCRx register. To configure a fil-
ter bank this must be deactivated by clearing the
FACT bit in the CFCR register. The filter scale is
configured by means of the FSC[1:0] bits in the
corresponding CFCR register, refer to Figure 9.
Filter Bank Scale Configuration - Register Organi-
sation. The identifier list or identifier mask mode
for the corresponding Mask/Identifier registers is
configured by means of the FMCLx and FMCHx
bits in the CFMR register. The FMCLx bit defines
the mode for the two least significant bytes, and
the FMCHx bit the mode for the two most signifi-
cant bytes of filter bank x. Examples:
data are copied into RAM locations. To copy the
data to the right location the application has to
identify the data by means of the identifier. To
avoid this and to ease the access to the RAM loca-
tions, the CAN controller provides a Filter Match
Index.
This index is stored in the mailbox together with
the message according to the filter priority rules.
Thus each received message has its associated
Filter Match Index.
The Filter Match Index can be used in two ways:
– Compare the Filter Match Index with a list of ex-
pected values.
– If filter bank 1 is configured as two 16-bit filters,
then the FMCL1 bit defines the mode of the
CF1R2 and CF1R3 registers and the FMCH1 bit
defines the mode of the CF1R6 and CF1R7 reg-
isters.
– Use the Filter Match Index as an index on an ar-
ray to access the data destination location.
For non-masked filters, the software no longer has
to compare the identifier.
If the filter is masked the software reduces the
comparison to the masked bits only.
– If filter bank 2 is configured as four 8-bit filters,
then the FMCL2 bit defines the mode of the
CF2R1 and CF2R3 registers and the FMCH2 bit
defines the mode of the CF2R5 and CF2R7 reg-
isters.
Filter Priority Rules
Depending on the filter combination it may occur
that an identifier passes successfully through sev-
eral filters. In this case the filter match value stored
in the receive mailbox is chosen according to the
following rules:
Note: In 32-bit configuration, the FMCLx and FM-
CHx bits must have the same value to ensure that
the four Mask/Identifier registers are in the same
mode.
– A filter in identifier list mode prevails on an filter
in mask mode.
To filter a group of identifiers, configure the Mask/
Identifier registers in mask mode.
– A filter with full identifier coverage prevails over
filters covering part of the identifier, e.g. 16-bit fil-
ters prevail over 8-bit filters.
To select single identifiers, configure the Mask/
Identifier registers in identifier list mode.
– Filters configured in the same mode and with
identical coverage are prioritized by filter number
and register number. The lower the number the
higher the priority.
Filters not used by the application should be left
deactivated.
Filter Match Index
Once a message has been received in the FIFO it
is available to the application. Typically application
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beCAN CONTROLLER (Cont’d)
Figure 103. Filtering Mechanism - example
Message Received
Data
Identifier
Ctrl
Receive FIFO
Identifier
Identifier
Identifier
0
1
2
Message
Stored
Identifier #2 Match
Identifier
n
Identifier
Mask
n+1
n+m
Identifier
Mask
No Match
Found
n: number of single identifiers to receive
m: number of identifier groups to receive
n and m values depend on the configuration of the filters
Message Discarded
The example above shows the filtering principle of
the beCAN. On reception of a message, the iden-
tifier is compared first with the filters configured in
identifier list mode. If there is a match, the mes-
sage is stored in the FIFO and the index of the
matching filter is stored in the Filter Match Index.
As shown in the example, the identifier matches
with Identifier #2 thus the message content and
MFMI 2 is stored in the FIFO.
If there is no match, the incoming identifier is then
compared with the filters configured in mask
mode.
If the identifier does not match any of the identifi-
ers configured in the filters, the message is dis-
carded by hardware without software intervention.
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beCAN CONTROLLER (Cont’d)
10.9.4.4 Message Storage
Receive Mailbox
The interface between the software and the hard-
ware for the CAN messages is implemented by
means of mailboxes. A mailbox contains all infor-
mation related to a message; identifier, data, con-
trol and status information.
When a message has been received, it is available
to the software in the FIFO output mailbox. Once
the software has handled the message (e.g. read
it) the software must release the FIFO output mail-
box by means of the RFOM bit in the CRFR regis-
ter to make the next incoming message available.
The filter match index is stored in the MFMI regis-
ter.
Transmit Mailbox
The software sets up the message to be transmit-
ted in an empty transmit mailbox. The status of the
transmission is indicated by hardware in the
MCSR register.
Receive Mailbox Mapping
Offset to Receive
Transmit Mailbox Mapping
Mailbox base ad-
dress (bytes)
Register Name
Offset to Transmit
Mailbox base ad-
dress (bytes)
Register Name
0
1
MFMI
MDLC
0
1
MCSR
2
MIDR0
MIDR1
MIDR2
MIDR3
MDAR0
MDAR1
MDAR2
MDAR3
MDAR4
MDAR5
MDAR6
MDAR7
Reserved
Reserved
MDLC
3
2
MIDR0
4
3
MIDR1
5
4
MIDR2
6
5
MIDR3
7
6
MDAR0
MDAR1
MDAR2
MDAR3
MDAR4
MDAR5
MDAR6
MDAR7
Reserved
Reserved
8
7
9
8
10
11
12
13
14
15
9
10
11
12
13
14
15
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beCAN CONTROLLER (Cont’d)
Figure 104. CAN Error State Diagram
When TEC or REC > 127
ERROR ACTIVE
ERROR PASSIVE
When TEC and REC < 128,
When 128 * 11 recessive bits occur:
When TEC > 255
BUS OFF
10.9.4.5 Error Management
Bus-Off Recovery
The error management as described in the CAN
protocol is handled entirely by hardware using a
Transmit Error Counter (TECR register) and a Re-
ceive Error Counter (RECR register), which get in-
cremented or decremented according to the error
condition. For detailed information about TEC and
REC management, please refer to the CAN stand-
ard.
The Bus-Off state is reached when TECR is great-
er then 255, this state is indicated by BOFF bit in
CESR register. In Bus-Off state, the beCAN acts
as disconnected from the CAN bus, hence it is no
longer able to transmit and receive messages.
Depending on the ABOM bit in the CMCR register
beCAN will recover from Bus-Off (become error
active again) either automatically or on software
request. But in both cases the beCAN has to wait
at least for the recovery sequence specified in the
CAN standard (128 x 11 consecutive recessive
bits monitored on CANRX).
Both of them may be read by software to deter-
mine the stability of the network. Furthermore, the
CAN hardware provides detailed information on
the current error status in CESR register. By
means of CEIER register and ERRIE bit in CIER
register, the software can configure the interrupt
generation on error detection in a very flexible
way.
If ABOM is set, the beCAN will start the recovering
sequence automatically after it has entered Bus-
Off state.
If ABOM is cleared, the software must initiate the
recovering sequence by requesting beCAN to en-
ter initialization mode. Then beCAN starts monitor-
ing the recovery sequence when the beCAN is re-
quested to leave the initialisation mode.
Note: In initialization mode, beCAN does not mon-
itor the CANRX signal, therefore it cannot com-
plete the recovery sequence. To recover, beCAN
must be in normal mode.
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beCAN CONTROLLER (Cont’d)
10.9.4.6 Bit Timing
– Bit segment 2 (BS2): defines the location of the
transmit point. It represents the PHASE_SEG2
of the CAN standard. Its duration is programma-
ble between 1 and 8 time quanta but may also be
automatically shortened to compensate for neg-
ative phase drifts.
The bit timing logic monitors the serial bus-line and
performs sampling and adjustment of the sample
point by synchronizing on the start-bit edge and re-
synchronizing on the following edges.
Its operation may be explained simply by splitting
nominal bit time into three segments as follows:
– Resynchronization Jump Width (RJW): de-
fines an upper bound to the amount of lengthen-
ing or shortening of the bit segments. It is
– Synchronization segment (SYNC_SEG): a bit
change is expected to occur within this time seg-
ment. It has a fixed length of one time quantum
programmable between 1 and 4 time quanta.
To guarantee the correct behaviour of the CAN
controller, SYNC_SEG + BS1 + BS2 must be
greater than or equal to 5 time quanta.
(1 x t
).
CAN
– Bit segment 1 (BS1): defines the location of the
sample point. It includes the PROP_SEG and
PHASE_SEG1 of the CAN standard. Its duration
is programmable between 1 and 16 time quanta
but may be automatically lengthened to compen-
sate for positive phase drifts due to differences in
the frequency of the various nodes of the net-
work.
For a detailed description of the CAN resynchroni-
zation mechanism and other bit timing configura-
tion constraints, please refer to the Bosch CAN
standard 2.0.
As a safeguard against programming errors, the
configuration of the Bit Timing Registers CBTR1
and CBTR0 is only possible while the device is in
Initialization mode.
Figure 105. Bit Timing
NOMINAL BIT TIME
BIT SEGMENT 1 (BS1)
SYNC_SEG
BIT SEGMENT 2 (BS2)
1 x t
t
t
BS2
CAN
BS1
SAMPLE POINT
TRANSMIT POINT
Figure 106. CAN Frames (Part 1of 2)
Inter-Frame Space
or Overload Frame
Inter-Frame Space
Data Frame (Standard identifier)
44 + 8 * N
Ack Field
2
Control Field Data Field
CRC Field
16
Arbitration Field
12
6
8 * N
7
ID
CRC
EOF
DLC
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beCAN CONTROLLER (Cont’d)
Figure 107. CAN Frames (Part 2 of 2)
Inter-Frame Space
or Overload Frame
Inter-Frame Space
Data Frame (Extended Identifier)
64 + 8 * N
Std Arbitr. Field
12
Ext Arbitr. Field
Ack Field
2
Ctrl Field Data Field CRC Field
20
6
8 * N
16
7
ID
CRC
EOF
DLC
Inter-Frame Space
or Overload Frame
Inter-Frame Space
Remote Frame
44
Ack Field End Of Frame
Control Field
6
CRC Field
16
Arbitration Field
12
2
7
ID
CRC
DLC
Data Frame or
Remote Frame
Inter-Frame Space
or Overload Frame
Error Frame
Flag Echo Error Delimiter
Error Flag
≤ 6
8
6
Notes:
Data Frame or
Remote Frame
• 0 <= N <= 8
Any Frame
Inter-Frame Space
Suspend
• SOF = Start Of Frame
• ID = Identifier
Intermission
Bus Idle
• RTR = Remote Transmission Request
• IDE = Identifier Extension Bit
• r0 = Reserved Bit
Transmission
8
3
• DLC = Data Length Code
• CRC = Cyclic Redundancy Code
• Error flag: 6 dominant bits if node is error
active else 6 recessive bits.
• Suspend transmission: applies to error
passive nodes only.
End Of Frame or
Error Delimiter or
Overload Delimiter
Inter-Frame Space
or Error Frame
Overload Frame
Overload Flag Overload Delimiter
6
8
• EOF = End of Frame
• ACK = Acknowledge bit
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beCAN CONTROLLER (Cont’d)
10.9.5 Interrupts
bled or disabled by means of the CAN Interrupt
Enable Register (CIER) and CAN Error Interrupt
Enable register (CEIER).
Two interrupt vectors are dedicated to beCAN.
Each interrupt source can be independently ena-
Figure 108. Event flags and Interrupt Generation
FMPIE
&
FIFO
FMP
FULL
FOVR
INTERRUPT
FFIE
&
&
+
FOVIE
EWGIE
&
EWGF
EPVIE
ERRIE
&
EPVF
&
+
BOFIE
&
TRANSMIT/
ERROR/
BOFF
STATUS CHANGE
INTERRUPT
LECIE
&
LECIEF
+
CIER
TMEIE
RQCP
RQCP
TXMB 0
TXMB 1
&
&
+
WKUIE
WKUI
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beCAN CONTROLLER (Cont’d)
– The FIFO interrupt can be generated by the fol-
CAN Rx signal.
lowing events:
10.9.6 Register Access Protection
– Reception of a new message, FMP bits in the
CRFR0 register incremented.
Erroneous access to certain configuration regis-
ters can cause the hardware to temporarily disturb
the whole CAN network. Therefore the following
registers can be modified by software only while
the hardware is in initialization mode:
– FIFO0 full condition, FULL bit in the CRFR0
register set.
– FIFO0 overrun condition, FOVR bit in the
CRFR0 register set.
CBTR0, CBTR1, CFCR0, CFCR1, CFMR and
CDGR registers.
– The transmit, error and status change inter-
rupt can be generated by the following events:
Although the transmission of incorrect data will not
cause problems at the CAN network level, it can
severely disturb the application. A transmit mail-
box can be only modified by software while it is in
empty state (refer to Figure 7. Transmit Mailbox
States).
– Transmit mailbox 0 becomes empty, RQCP0
bit in the CTSR register set.
– Transmit mailbox 1 becomes empty, RQCP1
bit in the CTSR register set.
– Error condition, for more details on error con-
ditions please refer to the CAN Error Status
register (CESR).
The filters must be deactivated before their value
can be modified by software. The modification of
the filter configuration (scale or mode) can be
done by software only in initialization mode.
– Wake-up condition, SOF monitored on the
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beCAN CONTROLLER (Cont’d)
10.9.7 BeCAN Cell Limitations
10.9.7.1 FIFO Corruption
As the FIFO pointer is not updated correctly, this
causes the last message received to be overwrit-
ten by any incoming message. This means one
message is lost as shown in the example in Figure
16. The beCAN will not recover normal operation
until a device reset occurs.
FIFO corruption occurs in the following case:
WHEN the beCAN RX FIFO already holds two
messages (that is, FMP == 2)
AND the application releases the FIFO (with
the instruction CRFR = B_RFOM;)
WHILE the beCAN requests the transfer of a new
receive message into the FIFO (this lasts one CPU
cycle)
THEN the internal FIFO pointer is not updat-
ed
BUT the FMP bits are updated correctly
Figure 109. FIFO Corruption
FIFO
FMP
*
v
When the FIFO is empty, v and * point to the same location
Initial State
0
1
- - -
v
*
Receive Message A
Receive Message B
Receive Message C
Release Message A
A - -
v
*
A B -
2
3
v
*
* does not move because FIFO is full (normal operation)
Normal operation
A B C
v
*
2
2
A B C
v
*
D B C
Release Message B
and Receive Message D
v
*
D B C
* Does not move, pointer corruption
D is overwritten by E
v
*
3
2
Receive Message E
Release Message C
E B C
v
*
C released
E B C
v
*
1
0
Release Message E
Release Message B
E released instead of B
E B C
v
*
* and v are not pointing to the same message
the FIFO is empty
E B C
* pointer to next receive location
v pointer to next message to be released
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beCAN CONTROLLER (Cont’d)
Workaround
To implement the workaround, use the following
sequence to release the CAN receive FIFO.
This sequence replaces any occurrence of
CRFR |= B_RFOM;.
Figure 110. Workaround 1
if ((CRFR & 0x03) == 0x02)
while
(( CMSR & 0x20) && ( CDGR & 0x08) )
{ };
CRFR |= B_RFOM;
Explanation of Workaround 1
frame at 500 kHz), so we also monitor the Rx pin
of the microcontroller to minimize the time the ap-
plication may wait in the while loop.
First, we need to make sure no interrupt can occur
between the test and the release of the FIFO to
avoid any added delay.
We know the critical window is located at the end
of the frame, 6+ CAN bit times after the acknowl-
edge bit (exactly six full bit times plus the time from
the beginning of the bit to the sample point). Those
bits represent the acknowledge delimiter + the end
of frame slot.
The workaround checks if the first two FIFO levels
are already full (FMP = 2) as the problem happens
only in this case.
If FMP ≠ 2 we release the FIFO immediately, if
FMP = 2, we monitor the reception status of the
cell.
We know also that those 6+ bits are in recessive
state on the bus, therefore if the CAN Rx pin of the
device is at ‘0’, (reflecting a CAN dominant state
on the bus), this is early enough to be sure we can
release the FIFO before the critical time slot.
The reception status is available in the CMSR reg-
ister bit 5 (REC bit). Note: The REC bit was called
RX in older versions of the datasheet.
– If the cell is not receiving, then REC bit in CMSR
is at 0, the software can release the FIFO imme-
diately: there is no risk.
Therefore, if the device hardware pin Rx is at 0
and there is a reception on going, its message will
be transferred to the FIFO only 6+ CAN bit times
later at the earliest (if the dominant bit is the ac-
knowledge) or later if the dominant bit is part of the
message.
– If the cell is receiving, it is important to make sure
the release of the mailbox will not happen at the
time when the received message is loaded into
the FIFO.
Compiled with Cosmic C compiler, the workaround
generates the following assembly lines:
We could simply wait for the end of the reception,
but this could take a long time (200µs for a 100-bit
Cycles
if ((CRFR & 0x03) == 0x02)
ld
and
cp
a, CRFR
a,#3
a,#2
3
2
2
jrne
_RELEASE
3
test: 10 cycles
while
(( CMSR & 0x20) && ( CDGR & 0x08) ) { };
_WHILELOOP:
btjf
btjt
CMSR,#5,_RELEASE
CDGR,#3,_WHILELOOP
5
5
loop: 10 cycles
CRFR |= B_RFOM;
_RELEASE:
bset
CRFR,#5
5
release: 5 cycles
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beCAN CONTROLLER (Cont’d)
In the worst case configuration, if the CAN cell
speed is set to the maximum baud rate, one bit
time is 8 CPU cycle. In this case the minimum time
between the end of the acknowledge and the criti-
cal period is 52 CPU cycles (48 for the 6 bit times
In order to reach the critical FMP = 2, the CAN
node needs to receive two messages without serv-
icing them. Then in order to reach the critical win-
dow, the cell has to receive a third one and the ap-
plication has to release the mailbox at the same
time, at the end of the reception.
+ 4 for the (PROP SEG + T
). According to the
Seg 1
previous code timing, we need less than 15 cycles
from the time we see the dominant state to the
time we perform the FIFO release (one full loop +
the actual release) therefore the application will
never release the FIFO at the critical time when
this workaround is implemented.
In the application, messages are not processed
only if either the interrupt are disabled or higher
level interrupts are being serviced.
Therefore if:
t
+ t
+ t
< 2 x t
IT CAN CAN frame
IT higher level
IT disable
the application will never wait in the workaround
: This the sum of the duration of all the
interrupts with a level strictly higher than the CAN
interrupt level
Timing analysis
t
IT higher level
- Time spent in the workaround
Inside a CAN frame, the longest period that the Rx
pin stays in recessive state is 5 bits. At the end of
the frame, the time between the acknowledge
dominant bit and the end of reception (signaled by
t
: This is the longest time the application
IT disable
disables the CAN interrupt (or all interrupts)
REC bit status) is 8t
, therefore the maximum
t
: This is the maximum duration between the
CANbit
IT CAN
time
8t
CANbit
spent
in
the
workaround
is:
beginning of the CAN interrupt and the actual loca-
tion of the workaround
+t +t +t
in this case or
CANbit loop test release
8t
+25t
.
CPU
t
: This is minimum CAN frame duration
CAN frame
At low speed, this time could represent a long de-
lay for the application, therefore it makes sense to
evaluate how frequently this delay occurs.
Figure 111. Critical Window Timing Diagram
Critical window: the received
message is placed in the FIFO
CAN Frame
Acknowledge: last
dominant bit in the frame
A release is not
allowed at this time
Time to test RX pin and to
release the FIFO 4.5µs@4 MHz
Time between the end of the
acknowledge and the critical windows
- 6 full CAN bit times + time to the sample point
approx. 13µs @ 500 Kbaud
Figure 112. Reception of a Sequence of Frames
FMP
BUS
0
1
2
2
t
1
t
2
t
3
CAN frame
CAN frame
CAN frame
t
t
IT higher level
t
CPU
IT disable
IT CAN
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beCAN CONTROLLER (Cont’d)
Side-effect of Workround 1
case is very rare but happens when a specific se-
quence is present on in the CAN frame.
Because the while loop lasts 10 CPU cycles, at
high baud rate, it is possible to miss a dominant
state on the bus if it lasts just one CAN bit time and
the bus speed is high enough (see Table 1).
The example in Figure 20 shows reception at max-
imum CAN baud rate: In this case t
is 8/f
CAN
CPU
and the sampling time is 10/f
.
CPU
If the application is using the maximum baud rate
and the possible delay caused by the workaround
is not acceptable, there is another workaround
which reduces the Rx pin sampling time.
Table 28. While Loop Timing
Software
timing:
Minimum baud rate for
possible missed
dominant bit
f
CPU
While loop
1.25 µs
2.5 µs
Workaround 2 (see Figure 21) first tests that
FMP = 2 and the CAN cell is receiving, if not the
FIFO can be released immediately. If yes, the pro-
gram goes through a sequence of test instructions
on the RX pin that last longer than the time be-
tween the acknowledge dominant bit and the criti-
cal time slot. If the Rx pin is in recessive state for
more than 8 CAN bit times, it means we are now
after the acknowledge and the critical slot. If a
dominant bit is read on the bus, we can release the
FIFO immediately. This workaround has to be writ-
ten in assembly language to avoid the compiler
optimizing the test sequence.
8 MHz
4 MHz
800 Kbaud
400 Kbaud
f
10/f
f
/10
CPU
CPU
CPU
If this happens, we will continue waiting in the
while loop instead of releasing the FIFO immedi-
ately. The workaround is still valid because we will
not release the FIFO during the critical period. But
the application may lose additional time waiting in
the while loop as we are no longer able to guaran-
tee a maximum of 6 CAN bit times spent in the
workaround.
The implementation shown here is for the CAN
bus maximum speed (1 Mbaud @ 8 MHz CPU
clock).
In this particular case the time the application can
spend in the workaround may increase up to a full
CAN frame, depending of the frame contents. This
Figure 113. Reception at Maximum CAN Baud Rate
CAN Bus signal
R R R R D R R R R D R R R R D R R R R D R R R R D
Sampling of Rx pin
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ST72561
Figure 114. Workaround 2
Ld
And
Cp
a, CRFR
a,#3
a,#2
; test FMP=2 ?
Jrne
_RELEASE
; if not release
Btjf
CMSR,#5,_RELEASE ; test if reception on going.
; if not release
Btjf
Btjf
Btjf
btjf
btjf
btjf
btjf
btjf
btjf
btjf
btjf
btjf
btjf
btjf
CDGR,#3,_RELEASE ; sample RX pin for 8 CAN bit time
CDGR,#3,_RELEASE
CDGR,#3,_RELEASE
CDGR,#3,_RELEASE
CDGR,#3,_RELEASE
CDGR,#3,_RELEASE
CDGR,#3,_RELEASE
CDGR,#3,_RELEASE
CDGR,#3,_RELEASE
CDGR,#3,_RELEASE
CDGR,#3,_RELEASE
CDGR,#3,_RELEASE
CDGR,#3,_RELEASE
CDGR,#3,_RELEASE
_RELEASE:
bset
CRFR,#5
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beCAN CONTROLLER (Cont’d)
10.9.8 Register Description
Bit 3 = RFLM Receive FIFO Locked Mode
- Read/Set/Clear
10.9.8.1 Control and Status Registers
0: Receive FIFO not locked on overrun. Once a re-
ceive FIFO is full the next incoming message
will overwrite the previous one.
CAN MASTER CONTROL REGISTER (CMCR)
Reset Value: 0000 0010 (02h)
1: Receive FIFO locked against overrun. Once a
receive FIFO is full the next incoming message
will be discarded.
7
0
0
ABOM AWUM NART RFLM TXFP SLEEP INRQ
Bit 2 = TXFP Transmit FIFO Priority
- Read/Set/Clear
Bit 7 = Reserved, must be kept cleared.
This bit controls the transmission order when sev-
eral mailboxes are pending at the same time.
0: Priority driven by the identifier of the message
1: Priority driven by the request order (chronologi-
cally)
Bit 6 = ABOM Automatic Bus-Off Management
- Read/Set/Clear
This bit controls the behaviour of the CAN hard-
ware on leaving the Bus-Off state.
0: The Bus-Off state is left on software request.
Refer to Section 0.1.4.5 Error Management,
Bus-Off recovery.
1: The Bus-Off state is left automatically by hard-
ware once 128 x 11 recessive bits have been
monitored.
Bit 1 = SLEEP Sleep Mode Request
- Read/Set/Clear
This bit is set by software to request the CAN hard-
ware to enter the sleep mode. Sleep mode will be
entered as soon as the current CAN activity (trans-
mission or reception of a CAN frame) has been
completed.
For detailed information on the Bus-Off state
please refer to Section 0.1.4.5 Error Management.
This bit is cleared by software to exit sleep mode.
Bit 5 = AWUM Automatic Wake-Up Mode
This bit is cleared by hardware when the AWUM
bit is set and a SOF bit is detected on the CAN Rx
signal.
- Read/Set/Clear
This bit controls the behaviour of the CAN hard-
ware on message reception during sleep mode.
0: The sleep mode is left on software request by
clearing the SLEEP bit of the CMCR register.
1: The sleep mode is left automatically by hard-
ware on CAN message detection. The SLEEP
bit of the CMCR register and the SLAK bit of the
CMSR register are cleared by hardware.
Bit 0 = INRQ Initialization Request
- Read/Set/Clear
The software clears this bit to switch the hardware
into normal mode. Once 11 consecutive recessive
bits have been monitored on the Rx signal the
CAN hardware is synchronized and ready for
transmission and reception. Hardware signals this
event by clearing the INAK bit if the CMSR regis-
ter.
Bit 4 = NART No Automatic Retransmission
- Read/Set/Clear
0: The CAN hardware will automatically retransmit
the message until it has been successfully
transmitted according to the CAN standard.
1: A message will be transmitted only once, inde-
pendently of the transmission result (successful,
error or arbitration lost).
Software sets this bit to request the CAN hardware
to enter initialization mode. Once software has set
the INRQ bit, the CAN hardware waits until the
current CAN activity (transmission or reception) is
completed before entering the initialization mode.
Hardware signals this event by setting the INAK bit
in the CMSR register.
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beCAN CONTROLLER (Cont’d)
CAN MASTER STATUS REGISTER (CMSR)
Reset Value: 0000 0010 (02h)
quest from the software (set SLEEP bit in CMCR
register).
This bit is cleared by hardware when the CAN
hardware has left sleep mode. Sleep mode is left
when the SLEEP bit in the CMCR register is
cleared. Please refer to the AWUM bit of the
CMCR register description for detailed information
for clearing SLEEP bit.
7
0
0
0
REC TRAN WKUI ERRI SLAK INAK
Note: To clear a bit of this register the software
must write this bit with a one.
Bit 0 = INAK Initialization Acknowledge
- Read
This bit is set by hardware and indicates to the
software that the CAN hardware is now in initiali-
zation mode. This bit acknowledges the initializa-
tion request from the software (set INRQ bit in
CMCR register).
Bits 7:4 = Reserved. Forced to 0 by hardware.
Bit 5 = REC Receive
- Read
The CAN hardware is currently receiver.
This bit is cleared by hardware when the CAN
hardware has left the initialization mode and is
now synchronized on the CAN bus. To be syn-
chronized the hardware has to monitor a se-
quence of 11 consecutive recessive bits on the
CAN RX signal.
Bit 4 = TRAN Transmit
- Read
The CAN hardware is currently transmitter.
Bit 3 = WKUI Wake-Up Interrupt
CAN TRANSMIT STATUS REGISTER (CTSR)
Read / Write (
- Read/Clear
This bit is set by hardware to signal that a SOF bit
has been detected while the CAN hardware was in
sleep mode. Setting this bit generates a status
change interrupt if the WKUIE bit in the CIER reg-
ister is set.
Reset Value: 0000 0000 (00h)
7
0
0
0
TXOK1 TXOK0
0
0
RQCP1 RQCP0
This bit is cleared by software.
Note: To clear a bit of this register the software
must write this bit with a one.
Bit 2 = ERRI Error Interrupt
- Read/Clear
This bit is set by hardware when a bit of the CESR
has been set on error detection and the corre-
sponding interrupt in the CEIER is enabled. Set-
ting this bit generates a status change interrupt if
the ERRIE bit in the CIER register is set.
Bits 7:6 = Reserved. Forced to 0 by hardware.
Bit 5 = TXOK1 Transmission OK for mailbox 1
- Read
This bit is set by hardware when the transmission
request on mailbox 1 has been completed suc-
cessfully. Please refer to Figure 7.
This bit is cleared by software.
Bit 1 = SLAK Sleep Acknowledge
- Read
This bit is set by hardware and indicates to the
software that the CAN hardware is now in sleep
mode. This bit acknowledges the sleep mode re-
This bit is cleared by hardware when mailbox 1 is
requested for transmission or when the software
clears the RQCP1 bit.
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beCAN CONTROLLER (Cont’d)
Bit 4 = TXOK0 Transmission OK for mailbox 0
- Read
mailbox are pending for transmission and mailbox
1 has the lowest priority.
This bit is set by hardware when the transmission
request on mailbox 0 has been completed suc-
cessfully. Please refer to Figure 7.
Bit 5 = LOW0 Lowest Priority Flag for Mailbox 0
- Read
This bit is set by hardware when more than one
mailbox are pending for transmission and mailbox
0 has the lowest priority.
This bit is cleared by hardware when mailbox 0 is
requested for transmission or when the software
clears the RQCP0 bit.
Note: These bits are set to zero when only one
mailbox is pending.
Bits 3:2 = Reserved. Forced to 0 by hardware.
Bit 1 = RQCP1 Request Completed for Mailbox 1
- Read/Clear
Bit 4 = Reserved. Forced to 0 by hardware.
This bit is set by hardware to signal that the last re-
quest for mailbox 1 has been completed. The re-
quest could be a transmit or an abort request.
Bit 3 = TME1 Transmit Mailbox 1 Empty
- Read
This bit is set by hardware when no transmit re-
quest is pending for mailbox 1.
This bit is cleared by software.
Bit 0 = RQCP0 Request Completed for Mailbox 0
- Read/Clear
This bit is set by hardware to signal that the last re-
quest for mailbox 0 has been completed. The re-
quest could be a transmit or an abort request.
Bit 2 = TME0 Transmit Mailbox 0 Empty
- Read
This bit is set by hardware when no transmit re-
quest is pending for mailbox 0.
This bit is cleared by software.
Bit 1:0 = CODE Mailbox Code
- Read
In case at least one transmit mailbox is free, the
code value is equal to the number of the next
transmit mailbox free.
CAN TRANSMIT PRIORITY REGISTER (CTPR)
All bits of this register are read only.
Reset Value: 0000 1100 (0Ch)
In case all transmit mailboxes are pending, the
code value is equal to the number of the transmit
mailbox with the lowest priority.
7
0
0
LOW1
LOW0
0
TME1
TME0
0
CODE
Bit 7 = Reserved. Forced to 0 by hardware.
Bit 6 = LOW1 Lowest Priority Flag for Mailbox 1
- Read
This bit is set by hardware when more than one
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CAN RECEIVE FIFO REGISTERS (CRFR)
Read / Write
These bits indicate how many messages are
pending in the receive FIFO.
Reset Value: 0000 0000 (00h)
FMP is increased each time the hardware stores a
new message in to the FIFO. FMP is decreased
each time the software releases the output mail-
box by setting the RFOM bit.
7
0
0
0
RFOM FOVR FULL
0
FMP1 FMP0
CAN INTERRUPT ENABLE REGISTER (CIER)
Note: To clear a bit in this register, software must
write a “1” to the bit.
All bits of this register are set and cleared by soft-
ware.
Read / Write
Reset Value: 0000 0000 (00h)
Bits 7:6 = Reserved. Forced to 0 by hardware.
7
0
Bit 5 = RFOM Release FIFO Output Mailbox
- Read/Set
WKUIE
0
0
0
FOVIE0 FFIE0 FMPIE0 TMEIE
Set by software to release the output mailbox of
the FIFO. The output mailbox can only be released
when at least one message is pending in the FIFO.
Setting this bit when the FIFO is empty has no ef-
fect. If more than one message are pending in the
FIFO, the software has to release the output mail-
box to access the next message.
Bit 7 = WKUIE Wake-Up Interrupt Enable
0: No interrupt when WKUI is set.
1: Interrupt generated when WKUI bit is set.
Cleared by hardware when the output mailbox has
been released.
Bits 6:4 = Reserved. Forced to 0 by hardware.
Bit 3 = FOVIE FIFO Overrun Interrupt Enable
0: No interrupt when FOVR bit is set.
1: Interrupt generated when FOVR bit is set.
Bit 4 = FOVR FIFO Overrun
- Read/Clear
This bit is set by hardware when a new message
has been received and passed the filter while the
FIFO was full.
Bit 2 = FFIE FIFO Full Interrupt Enable
0: No interrupt when FULL bit is set.
1: Interrupt generated when FULL bit is set.
This bit is cleared by software.
Bit 3 = FULL FIFO Full
Bit 1 = FMPIE FIFO Message Pending Interrupt
- Read/Clear
Enable
Set by hardware when three messages are stored
in the FIFO.
This bit can be cleared by software writing a one to
this bit or releasing the FIFO by means of RFOM.
0: No interrupt on FMP[1:0] bits transition from 00b
to 01b.
1: Interrupt generated on FMP[1:0] bits transition
from 00b to 01b.
Bit 2 = Reserved. Forced to 0 by hardware.
Bit 0 = TMEIE Transmit Mailbox Empty Interrupt
Enable
0: No interrupt when RQCPx bit is set.
1: Interrupt generated when RQCPx bit is set.
Bits 1:0 = FMP[1:0] FIFO Message Pending
- Read
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CAN ERROR STATUS REGISTER (CESR)
Bit 1 = EWGF Error Warning Flag
- Read
Read / Write
Reset Value: 0000 0000 (00h)
This bit is set by hardware when the warning limit
has been reached. Receive Error Counter or
Transmit Error Counter greater than 96.
7
0
0
LEC2 LEC1 LEC0
0
BOFF EPVF EWGF
CAN ERROR INTERRUPT ENABLE REGISTER
(CEIER)
Bit 7 = Reserved. Forced to 0 by hardware.
All bits of this register are set and clear by soft-
ware.
Read/Write
Reset Value: 0000 0000 (00h)
Bits 6:4 = LEC[2:0] Last Error Code
- Read/Set/Clear
This field holds a code which indicates the type of
the last error detected on the CAN bus. If a mes-
sage has been transferred (reception or transmis-
sion) without error, this field will be cleared to ‘0’.
The code 7 is unused and may be written by the
CPU to check for update
7
0
ERRIE
0
0
LECIE
0
BOFIE EPVIE EWGIE
Bit 7 = ERRIE Error Interrupt Enable
0: No interrupt will be generated when an error
condition is pending in the CESR.
Table 29. LEC Error Types
1: An interrupt will be generation when an error
condition is pending in the CESR.
Code
Error Type
0
1
2
3
4
5
6
7
No Error
Stuff Error
Form Error
Bits 6:5 = Reserved. Forced to 0 by hardware.
Acknowledgment Error
Bit recessive Error
Bit dominant Error
CRC Error
Bit 4 = LECIE Last Error Code Interrupt Enable
0: ERRI bit will not be set when the error code in
LEC[2:0] is set by hardware on error detection.
1: ERRI bit will be set when the error code in
LEC[2:0] is set by hardware on error detection.
Set by software
Bit 3 = Reserved. Forced to 0 by hardware.
Bit 3 = Reserved. Forced to 0 by hardware.
Bit 2 = BOFF Bus-Off Flag
- Read
Bit 2 = BOFIE Bus-Off Interrupt Enable
This bit is set by hardware when it enters the bus-
off state. The bus-off state is entered on TECR
overrun, TEC greater than 255, refer to section
0.1.4.5 on page 14.
0: ERRI bit will not be set when BOFF is set.
1: ERRI bit will be set when BOFF is set.
Bit 1 = EPVIE Error Passive Interrupt Enable
0: ERRI bit will not be set when EPVF is set.
1: ERRI bit will be set when EPVF is set.
Bit 1 = EPVF Error Passive Flag
- Read
This bit is set by hardware when the Error Passive
limit has been reached (Receive Error Counter or
Transmit Error Counter greater than 127).
Bit 0 = EWGIE Error Warning Interrupt Enable
0: ERRI bit will not be set when EWGF is set.
1: ERRI bit will be set when EWGF is set.
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TRANSMIT ERROR COUNTER REG. (TECR)
Read Only
Bit 1 = SILM Silent Mode
- Read/Set/Clear
0: Normal operation
1: Silent Mode
Reset Value: 00h
7
0
TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0
Bit 0 = LBKM Loop Back Mode
- Read/Set/Clear
0: Loop Back Mode disabled
1: Loop Back Mode enabled
TEC[7:0] is the least significant byte of the 9-bit
Transmit Error Counter implementing part of the
fault confinement mechanism of the CAN protocol.
CAN BIT TIMING REGISTER 0 (CBTR0)
This register can only be accessed by the software
when the CAN hardware is in configuration mode.
Read / Write
RECEIVE ERROR COUNTER REG. (RECR)
Page: 00h — Read Only
Reset Value: 00h
Reset Value: 0000 0000 (00h)
7
0
7
0
SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0
REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0
Bit 7:6 SJW[1:0] Resynchronization Jump Width
These bits define the maximum number of time
quanta the CAN hardware is allowed to lengthen
or shorten a bit to perform the resynchronization.
Resynchronization Jump Width = (SJW+1).
REC[7:0] is the Receive Error Counter implement-
ing part of the fault confinement mechanism of the
CAN protocol. In case of an error during reception,
this counter is incremented by 1 or by 8 depending
on the error condition as defined by the CAN stand-
ard. After every successful reception the counter is
decremented by 1 or reset to 120 if its value was
higher than 128. When the counter value exceeds
127, the CAN controller enters the error passive
state.
Bit 5:0 BRP[5:0] Baud Rate Prescaler
These bits define the length of a time quantum.
tq = (BRP+1)/f
CPU
For more information on bit timing, please refer to
Section 0.1.4.6 Bit Timing.
CAN DIAGNOSIS REGISTER (CDGR)
CAN BIT TIMING REGISTER 1 (CBTR1)
Read / Write
All bits of this register are set and clear by soft-
ware.
Reset Value: 0001 0011 (23h)
Read / Write
Reset Value: 0000 1100 (0Ch)
7
0
0
7
0
0
BS22 BS21 BS20 BS13 BS12 BS11 BS10
0
0
0
RX
SAMP SILM LBKM
Bit 7 = Reserved. Forced to 0 by hardware.
Bit 3 = RX CAN Rx Signal
- Read
Bits 6:4 BS2[2:0] Time Segment 2
These bits define the number of time quanta in
Time Segment 2.
Monitors the actual value of the CAN_RX Pin.
Time Segment 2 = (BS2+1)
Bit 2 = SAMP Last Sample Point
- Read
The value of the last sample point.
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Bits 3:0 BS1[3:0] Time Segment 1
These bits define the number of time quanta in
Time Segment 1
Bits 7:3 = Reserved. Forced to 0 by hardware.
Bits 2:0 = PS[2:0] Page Select
- Read/Write
This register contains the page number.
Time Segment 1 = (BS1+1)
For more information on bit timing, please refer to
Section 0.1.4.6 Bit Timing.
Table 30. Filter Page Selection
CAN FILTER PAGE SELECT REGISTER
(CPSR)
PS[2:0]
Page Selected
0
1
2
3
4
5
6
7
Tx Mailbox 0
Tx Mailbox 1
All bits of this register are set and cleared by soft-
ware.
Read / Write
Reset Value: 0000 0000 (00h)
Acceptance Filter 0:1
Acceptance Filter 2:3
Acceptance Filter 4:5
Reserved
7
0
0
Configuration/Diagnosis
Receive FIFO
0
0
0
0
FPS2 FPS1 FPS0
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10.9.8.2 Mailbox Registers
Bit 3 = TXOK Transmission OK
- Read
This chapter describes the registers of the transmit
and receive mailboxes. Refer to Section 0.1.4.4
Message Storage for detailed register mapping.
The hardware updates this bit after each transmis-
sion attempt.
0: The previous transmission failed
1: The previous transmission was successful
Transmit and receive mailboxes have the same
registers except:
Note: This bit has the same value as the corre-
sponding TXOKx bit in the CTSR register.
– MCSR register in a transmit mailbox is replaced
by MFMI register in a receive mailbox.
– A receive mailbox is always write protected.
Bit 2 = RQCP Request Completed
- Read/Clear
Set by hardware when the last request (transmit or
abort) has been performed.
– A transmit mailbox is write enable only while
empty, corresponding TME bit in the CTPR reg-
ister set.
Cleared by software writing a “1” or by hardware
on transmission request.
MAILBOX CONTROL STATUS REGISTER
(MCSR)
Note: This bit has the same value as the corre-
sponding RQCPx bit of the CTSR register.
Read / Write
Reset Value: 0000 0000 (00h)
Clearing this bit clears all the status bits (TX-
OK, ALST and TERR) in the MCSR register and
the RQCP and TXOK bits in the CTSR register.
7
0
0
0
TERR ALST TXOK RQCP ABRQ TXRQ
Bit 1 = ABRQ Abort Request for Mailbox
- Read/Set
Set by software to abort the transmission request
for the corresponding mailbox.
Bits 7:6 = Reserved. Forced to 0 by hardware.
Cleared by hardware when the mailbox becomes
empty.
Bit 5 = TERR Transmission Error
- Read
This bit is updated by hardware after each trans-
mission attempt.
Setting this bit has no effect when the mailbox is
not pending for transmission.
0: The previous transmission was successful
1: The previous transmission failed due to an error
Bit 0 = TXRQ Transmit Mailbox Request
- Read/Set
Set by software to request the transmission for the
corresponding mailbox.
Bit 4 = ALST Arbitration Lost
- Read
This bit is updated by hardware after each trans-
mission attempt.
Cleared by hardware when the mailbox becomes
empty.
0: The previous transmission was successful
1: The previous transmission failed due to an arbi-
tration lost
Note: This register is implemented only in transmit
mailboxes. In receive mailboxes, the MFMI regis-
ter is mapped at this location.
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MAILBOX FILTER MATCH INDEX (MFMI)
This register is read only.
MIDR1
Reset Value: 0000 0000 (00h)
7
0
7
0
STID5
STID4
STID3
STID2
STID1
STID0 EXID17 EXID16
FMI7
FMI6
FMI5
FMI4
FMI3
FMI2
FMI1
FMI0
Bits 7:0 = FMI[7:0] Filter Match Index
Bits 7:2 = STID[5:0] Standard Identifier
6 least significant bits of the standard part of the
identifier.
This register contains the index of the filter the
message stored in the mailbox passed through.
For more details on identifier filtering please refer
to Section 0.1.4.3 - Filter Match Index paragraph.
Bits 1:0 = EXID[17:16] Extended Identifier
2 most significant bits of the extended part of the
identifier.
Note: This register is implemented only in receive
mailboxes. In transmit mailboxes, the MCSR reg-
ister is mapped at this location.
MIDR2
MAILBOX IDENTIFIER REGISTERS
(MIDR[3:0])
7
0
Read / Write
Reset Value: Undefined
MIDR0
EXID15 EXID14 EXID13 EXID12 EXID11 EXID10 EXID9
EXID8
Bits 7:0 = EXID[15:8] Extended Identifier
7
0
Bits 15 to 8 of the extended part of the identifier.
0
IDE
RTR
STID10 STID9
STID8
STID7
STID6
MIDR3
Bit 7 = Reserved. Forced to 0 by hardware.
7
0
Bit 6 = IDE Extended Identifier
EXID7
EXID6
EXID5
EXID4
EXID3
EXID2
EXID1
EXID0
This bit defines the identifier type of message in
the mailbox.
Bits 7:1 = EXID[6:0] Extended Identifier
6 least significant bits of the extended part of the
identifier.
0: Standard identifier.
1: Extended identifier.
Bit 5 = RTR Remote Transmission Request
0: Data frame
1: Remote frame
Bits 4:0 = STID[10:6] Standard Identifier
5 most significant bits of the standard part of the
identifier.
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MAILBOX DATA LENGTH CONTROL REGIS-
TER (MDLC)
MAILBOX DATA REGISTERS (MDAR[7:0])
All bits of this register are write protected when the
mailbox is not in empty state.
All bits of this register is write protected when the
mailbox is not in empty state.
Read / Write
Reset Value: Undefined
Read / Write
Reset Value: xxxx xxxx (xxh)
7
0
7
0
0
DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0
0
0
0
DLC3
DLC2
DLC1
DLC0
Bits 7:0 = DATA[7:0] Data
A data byte of the message. A message can con-
tain from 0 to 8 data bytes.
Bit 7 = Reserved, must be kept cleared.
Bits 6:4 = Reserved, forced to 0 by hardware.
Bits 3:0 = DLC[3:0] Data Length Code
This field defines the number of data bytes a data
frame contains or a remote frame request.
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10.9.8.3 CAN Filter Registers
CAN FILTER CONFIGURATION REG.0 (CFCR0)
CAN FILTER CONFIGURATION REG.1 (CFCR1)
All bits of this register are set and cleared by soft-
All bits of this register are set and cleared by soft-
ware.
ware.
Read / Write
Reset Value: 0000 0000 (00h)
Read / Write
Reset Value: 0000 0000 (00h)
7
0
0
7
0
0
FSC11 FSC10 FACT1
0
FSC01 FSC00 FACT0
FSC31 FSC30 FACT3
0
FSC21 FSC20 FACT2
Note: To modify the FFAx and FSCx bits, the be-
CAN must be in INIT mode.
Bit 7 = Reserved. Forced to 0 by hardware.
Bits 6:5 = FSC3[1:0] Filter Scale Configuration
These bits define the scale configuration of Filter
3.
Bit 7 = Reserved. Forced to 0 by hardware.
Bits 6:5 = FSC1[1:0] Filter Scale Configuration
These bits define the scale configuration of Filter
1.
Bit 4 = FACT3 Filter Active
The software sets this bit to activate filter 3. To
modify the Filter 3 registers (CF3R[0:7]) the
FACT3 bit must be cleared.
Bit 4 = FACT1 Filter Active
0: Filter 3 is not active
1: Filter 3 is active
The software sets this bit to activate Filter 1. To
modify the Filter 1 registers (CF1R[7:0]), the
FACT1 bit must be cleared.
0: Filter 1 is not active
1: Filter 1 is active
Bit 3 = Reserved. Forced to 0 by hardware.
Bits 2:1 = FSC2[1:0] Filter Scale Configuration
These bits define the scale configuration of Filter
2.
Bit 3 = Reserved. Forced to 0 by hardware.
Bits 2:1 = FSC0[1:0] Filter Scale Configuration
These bits define the scale configuration of Filter
0.
Bit 0 = FACT2 Filter Active
The software sets this bit to activate Filter 2. To
modify the Filter 2 registers (CF2R[0:7]), the
FACT2 bit must be cleared.
Bit 0 = FACT0 Filter Active
0: Filter 2 is not active
1: Filter 2 is active
The software sets this bit to activate Filter 0. To
modify the Filter 0 registers (CF0R[0:7]), the
FACT0 bit must be cleared.
0: Filter 0 is not active
1: Filter 0 is active
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CAN FILTER CONFIGURATION REG.1 (CFCR2)
CAN FILTER MODE REGISTER (CFMR0)
All bits of this register are set and cleared by soft-
All bits of this register are set and cleared by soft-
ware.
ware.
Read / Write
Reset Value: 0000 0000 (00h)
Read / Write
Reset Value: 0000 0000 (00h)
7
0
0
7
0
FSC51 FSC50 FACT5
0
FSC41 FSC40 FACT4
FMH3 FML3 FMH2 FML2 FMH1 FML1 FMH0 FML0
Bit 7 = Reserved. Forced to 0 by hardware.
Bit 7 = FMH3 Filter Mode High
Mode of the high registers of Filter 3.
0: High registers are in mask mode
1: High registers are in identifier list mode
Bits 6:5 = FSC5[1:0] Filter Scale Configuration
These bits define the scale configuration of Filter
5.
Bit 6 = FML3 Filter Mode Low
Mode of the low registers of Filter 3.
0: Low registers are in mask mode
1: Low registers are in identifier list mode
Bit 4 = FACT5 Filter Active
The software sets this bit to activate filter 5. To
modify the Filter 5 registers (CF5R[0:7]) the
FACT5 bit must be cleared.
0: Filter 5 is not active
1: Filter 5 is active
Bit 5 = FMH2 Filter Mode High
Mode of the high registers of Filter 2.
0: High registers are in mask mode
1: High registers are in identifier list mode
Bit 3 = Reserved. Forced to 0 by hardware.
Bit 4 = FML2 Filter Mode Low
Bits 2:1 = FSC4[1:0] Filter Scale Configuration
These bits define the scale configuration of Filter
4.
Mode of the low registers of Filter 2.
0: Low registers are in mask mode
1: Low registers are in identifier list mode
Bit 0 = FACT4 Filter Active
Bit 3 = FMH1 Filter Mode High
The software sets this bit to activate Filter 4. To
modify the Filter 4 registers (CF4R[0:7]), the
FACT4 bit must be cleared.
Mode of the high registers of Filter 1.
0: High registers are in mask mode
1: High registers are in identifier list mode
0: Filter 4 is not active
1: Filter 4 is active
Bit 2 = FML1 Filter Mode Low
Mode of the low registers of filter 1.
0: Low registers are in mask mode
1: Low registers are in identifier list mode
Bit 1 = FMH0 Filter Mode High
Mode of the high registers of filter 0.
0: High registers are in mask mode
1: High registers are in identifier list mode
Bit 0 = FML0 Filter Mode Low
Mode of the low registers of filter 0.
0: Low registers are in mask mode
1: Low registers are in identifier list mode
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CAN FILTER MODE REGISTER (CFMR1)
FILTER x REGISTER[7:0] (CFxR[7:0])
All bits of this register are set and cleared by soft-
Read / Write
ware.
Reset Value: Undefined
Read / Write
Reset Value: 0000 0000 (00h)
7
0
7
0
0
FB7
FB6
FB5
FB4
FB3
FB2
FB1
FB0
0
0
0
FMH5 FML5 FMH4 FML4
In all configurations:
Bits 7:0 = FB[7:0] Filter Bits
Bits 7:4 = Reserved. Forced to 0 by hardware.
Identifier
Each bit of the register specifies the level of the
corresponding bit of the expected identifier.
0: Dominant bit is expected
Bit 3 = FMH5 Filter Mode High
Mode of the high registers of Filter 5.
0: High registers are in mask mode
1: High registers are in identifier list mode
1: Recessive bit is expected
Mask
Each bit of the register specifies whether the bit of
the associated identifier register must match with
the corresponding bit of the expected identifier or
not.
0: Don’t care, the bit is not used for the comparison
1: Must match, the bit of the incoming identifier
must have the same level has specified in the
corresponding identifier register of the filter.
Bit 2 = FML5 Filter Mode Low
Mode of the low registers of filter 5.
0: Low registers are in mask mode
1: Low registers are in identifier list mode
Bit 1 = FMH4 Filter Mode High
Mode of the high registers of filter 4.
0: High registers are in mask mode
1: High registers are in identifier list mode
Note: Each filter x is composed of 8 registers,
CFxR[7:0]. Depending on the scale and mode
configuration of the filter the function of each reg-
ister can differ. For the filter mapping, functions
description and mask registers association, refer
to Section 0.1.4.3 Identifier Filtering.
Bit 0 = FML4 Filter Mode Low
Mode of the low registers of filter 4.
0: Low registers are in mask mode
1: Low registers are in identifier list mode
A Mask/Identifier register in mask mode has the
same bit mapping as in identifier list mode.
Note: To modify these registers, the correspond-
ing FACT bit in the CFCR register must be
cleared.
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Figure 115. CAN Register Mapping
68h
CAN MASTER CONTROL REGISTER
CMCR
CMSR
69h
6Ah
6Bh
6Ch
6Dh
6Eh
6Fh
CAN MASTER STATUS REGISTER
CAN TRANSMIT STATUS REGISTER
CAN TRANSMIT PRIORITY REGISTER
CAN RECEIVE FIFO REGISTER
CTSR
CTPR
CRFR
CIER
CAN INTERRUPT ENABLE REGISTER
CAN DIAGNOSIS REGISTER
CDGR
CPSR
CAN PAGE SELECTION REGISTER
PAGED REGISTER 0
PAGED REGISTER 1
PAGED REGISTER 2
PAGED REGISTER 3
PAGED REGISTER 4
PAGED REGISTER 5
PAGED REGISTER 6
PAGED REGISTER 7
PAGED REGISTER 8
PAGED REGISTER 9
PAGED REGISTER 10
PAGED REGISTER 11
PAGED REGISTER 12
PAGED REGISTER 13
PAGED REGISTER 14
PAGED REGISTER 15
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10.9.8.4 Page Mapping for CAN
PAGE 2
CF0R0
CF0R1
CF0R2
CF0R3
PAGE 3
CF2R0
CF2R1
CF2R2
CF2R3
PAGE 4
PAGE 0
MCSR
MDLC
PAGE 1
70h
71h
72h
73h
74h
75h
76h
77h
78h
79h
7Ah
7Bh
7Ch
7Dh
7Eh
7Fh
CF4R0
CF4R1
CF4R2
CF4R3
MCSR
MDLC
MIDR0
MIDR1
MIDR0
MIDR1
CF2R4
CF2R5
CF2R6
CF2R7
CF4R4
CF4R5
CF4R6
CF4R7
CF5R0
CF5R1
CF5R2
CF5R3
CF0R4
CF0R5
CF0R6
CF0R7
CF1R0
CF1R1
CF1R2
CF1R3
MIDR2
MIDR3
MDAR0
MDAR1
MDAR2
MIDR2
MIDR3
MDAR0
MDAR1
MDAR2
CF3R0
CF3R1
CF3R2
CF3R3
MDAR3
MDAR4
MDAR5
MDAR3
MDAR4
MDAR5
MDAR6
MDAR7
MDAR6
MDAR7
CF3R4
CF3R5
CF5R4
CF5R5
CF1R4
CF1R5
CF1R6
MTSLR
MTSHR
CF3R6
CF5R6
MTSLR
CF3R7
CF5R7
MTSHR
Tx Mailbox 1
PAGE 7
CF1R7
Acceptance Filter 0:1
Acceptance Filter 2:3
Acceptance Filter 4:5
Tx Mailbox 0
PAGE 6
70h
71h
72h
73h
74h
75h
76h
77h
78h
79h
7Ah
7Bh
7Ch
7Dh
7Eh
7Fh
CESR
CEIER
TECR
RECR
MFMI
MDLC
MIDR0
MIDR1
BTCR0
BTCR1
MIDR2
MIDR3
MDAR0
MDAR1
MDAR2
Reserved
Reserved
CFMR0
CFMR1
CFCR0
CFCR1
MDAR3
MDAR4
MDAR5
CFCR2
MDAR6
MDAR7
Reserved
Reserved
Reserved
MTSLR
MTSHR
Configuration/Diagnosis
Receive FIFO
207/263
ST72561
beCAN CONTROLLER (Cont’d)
Table 31. beCAN Control and Status Page - Register Map and Reset Values
Address
(Hex.)
Register
Name
7
6
5
4
3
2
1
0
CMCR
ABOM
0
AWUM
0
NART
0
RFLM
0
TXFP
0
SLEEP
1
INRQ
0
68h
69h
6Ah
6Bh
6Ch
6Dh
6Eh
6Fh
0
Reset Value
CMSR
REC
0
TRAN
0
WKUI
0
ERRI
0
SLAK
1
INAK
0
Reset Value
0
0
0
0
0
CTSR
TXOK1
0
TXOK0
0
RQCP1
0
RQCP0
0
Reset Value
0
0
0
CTPR
LOW1
0
LOW0
0
TME1
1
TME0
1
CODE0
0
Reset Value
1
0
CRFR
RFOM
0
FOVR
0
FULL
0
FMP1
0
FMP0
0
Reset Value
0
0
0
CIER
WKUIE
0
FOVIE0
0
FFIE0
0
FMPIE0
0
TMEIE
0
0
0
Reset Value
CDGR
RX
1
SAMP
1
SILM
0
LBKM
0
Reset Value
0
0
0
0
0
0
0
0
CFPSR
FPS2
0
FPS1
0
FPS0
0
Reset Value
0
Table 32. beCAN Mailbox Pages - Register Map and Reset Values
Address
(Hex.)
Register
Name
7
6
5
4
3
2
1
0
70h
MFMI
FMI7
0
FMI6
0
FMI5
0
FMI4
0
FMI3
0
FMI2
0
FMI1
0
FMI0
0
Receive Reset Value
70h MCSR
TERR
0
ALST
0
TXOK
0
RQCP
0
ABRQ
0
TXRQ
0
Transmit Reset Value
0
0
x
MDLC
71h
0
x
DLC3
x
DLC2
x
DLC1
x
DLC0
x
Reset Value
x
x
MIDR0
72h
IDE
x
RTR
x
STID10
x
STID9
x
STID8
x
STID7
x
STID6
x
Reset Value
x
MIDR1
73h
STID5
x
STID4
x
STID3
x
STID2
x
STID1
x
STID0
x
EXID17
x
EXID16
x
Reset Value
MIDR2
74h
EXID15
x
EXID14
x
EXID13
x
EXID12
x
EXID11
x
EXID10
x
EXID9
x
EXID8
x
Reset Value
MIDR3
75h
EXID7
x
EXID6
x
EXID5
x
EXID4
x
EXID3
x
EXID2
x
EXID1
x
EXID0
x
Reset Value
MDAR[0:7] MDAR7
Reset Value
MDAR6
x
MDAR5
x
MDAR4
x
MDAR3
x
MDAR2
x
MDAR1
x
MDAR0
x
76h:7Dh
x
208/263
ST72561
Address
(Hex.)
Register
Name
7
6
5
4
3
2
1
0
MTSLR
TIME7
x
TIME6
x
TIME5
x
TIME4
x
TIME3
x
TIME2
x
TIME1
x
TIME0
x
7Eh
7Fh
Reset Value
MTSHR
TIME15
x
TIME14
x
TIME13
x
TIME12
x
TIME11
x
TIME10
x
TIME9
x
TIME8
x
Reset Value
Table 33. beCAN Filter Configuration Page - Register Map and Reset Values
Address
(Hex.)
Register
Name
7
6
5
4
3
2
1
0
CESR
LEC2
0
LEC1
0
LEC0
0
BOFF
0
EPVF
0
EWGF
0
70h
71h
72h
73h
74h
75h
76h
77h
78h
79h
7Ah
7Bh
7Ch
Reset Value
0
0
0
CEIER
LECIE
0
BOFIE
0
EPVIE
0
EWGIE
0
ERRIE
0
Reset Value
0
0
TECR
TEC7
0
TEC6
0
TEC5
0
TEC4
0
TEC3
0
TEC2
0
TEC1
0
TEC0
0
Reset Value
RECR
REC7
0
REC6
0
REC5
0
REC4
0
REC3
0
REC2
0
REC1
0
REC0
0
Reset Value
CBTR0
SJW1
0
SJW0
0
BRP5
0
BRP4
0
BRP3
0
BRP2
0
BRP1
0
BRP0
0
Reset Value
CBTR1
BS22
0
BS21
1
BS20
0
BS13
0
BS12
0
BS11
1
BS10
1
Reset Value
0
x
x
Reserved
Reserved
x
x
x
x
x
x
x
x
x
x
x
x
x
x
CFMR0
FMH3
0
FML3
0
FMH2
0
FML2
0
FMH1
0
FML1
0
FMH0
0
FML0
0
Reset Value
CFMR1
FMH5
0
FML5
0
FMH4
0
FML4
0
0
0
0
0
Reset Value
CFCR0
FFA1
0
FSC11
0
FSC10
0
FACT1
0
FFA0
0
FSC01
0
FSC00
0
FACT0
0
Reset Value
CFCR1
FFA3
0
FSC31
0
FSC30
0
FACT3
0
FFA2
0
FSC21
0
FSC20
0
FACT2
0
Reset Value
CFCR2
FFA5
0
FSC51
0
FSC50
0
FACT5
0
FFA4
0
FSC41
0
FSC40
0
FACT4
0
Reset Value
209/263
ST72561
10.10 10-BIT A/D CONVERTER (ADC)
10.10.1 Introduction
10.10.3 Functional Description
The on-chip Analog to Digital Converter (ADC) pe-
ripheral is a 10-bit, successive approximation con-
verter with internal sample and hold circuitry. This
peripheral has up to 16 multiplexed analog input
channels (refer to device pin out description) that
allow the peripheral to convert the analog voltage
levels from up to 16 different sources.
10.10.3.1 Digital A/D Conversion Result
The conversion is monotonic, meaning that the re-
sult never decreases if the analog input does not
and never increases if the analog input does not.
If the input voltage (V ) is greater than V
AIN
DDA
(high-level voltage reference) then the conversion
result is FFh in the ADCDRH register and 03h in
the ADCDRL register (without overflow indication).
The result of the conversion is stored in a 10-bit
Data Register. The A/D converter is controlled
through a Control/Status Register.
If the input voltage (V ) is lower than V
level voltage reference) then the conversion result
in the ADCDRH and ADCDRL registers is 00 00h.
(low-
SSA
AIN
10.10.2 Main Features
■ 10-bit conversion
The A/D converter is linear and the digital result of
the conversion is stored in the ADCDRH and AD-
CDRL registers. The accuracy of the conversion is
described in the Electrical Characteristics Section.
■ Up to 16 channels with multiplexed input
■ Linear successive approximation
■ Data register (DR) which contains the results
■ Conversion complete status flag
■ On/off bit (to reduce consumption)
The block diagram is shown in Figure 116.
R
is the maximum recommended impedance
AIN
for an analog input signal. If the impedance is too
high, this will result in a loss of accuracy due to
leakage and sampling not being completed in the
allotted time.
Figure 116. ADC Block Diagram
f
f
ADC
CPU
f
f
/2 f
/4
CPU, CPU , CPU
CH3
EOC SPEEDADON SLOW
CH2 CH1 CH0
ADCCSR
4
AIN0
AIN1
ANALOG TO DIGITAL
CONVERTER
ANALOG
MUX
AINx
ADCDRH
D9 D8 D7 D6 D5 D4 D3 D2
ADCDRL
0
0
0
0
0
0
D1 D0
210/263
ST72561
10-BIT A/D CONVERTER (ADC) (Cont’d)
10.10.3.2 A/D Conversion
in the ADCCSR register, the current conversion is
stopped, the EOC bit is cleared, and the A/D con-
verter starts converting the newly selected chan-
nel.
The analog input ports must be configured as in-
put, no pull-up, no interrupt. Refer to the “I/O ports”
chapter. Using these pins as analog inputs does
not affect the ability of the port to be read as a logic
input.
10.10.3.4 ADCDR consistency
If an End Of Conversion event occurs after soft-
ware has read the ADCDRLSB but before it has
read the ADCDRMSB, there would be a risk that
the two values read would belong to different sam-
ples.
In the ADCCSR register:
– Select the CS[3:0] bits to assign the analog
channel to convert.
ADC Conversion mode
To guarantee consistency:
In the ADCCSR register:
– The ADCDRL and the ADCDRH registers are
locked when the ADCCRL is read
– The ADCDRL and the ADCDRH registers are
unlocked when the ADCDRH register is read
or when ADON is reset.
– Set the ADON bit to enable the A/D converter
and to start the conversion. From this time on,
the ADC performs a continuous conversion of
the selected channel.
This is important, as the ADCDR register will not
be updated until the ADCDRH register is read.
When a conversion is complete:
10.10.4 Low Power Modes
– The EOC bit is set by hardware.
– The result is in the ADCDR registers.
A read to the ADCDRH resets the EOC bit.
Note: The A/D converter may be disabled by re-
setting the ADON bit. This feature allows reduced
power consumption when no conversion is need-
ed and between single shot conversions.
To read the 10 bits, perform the following steps:
1. Poll EOC bit
Mode
WAIT
Description
No effect on A/D Converter
A/D Converter disabled.
2. Read the ADCDRL register
3. Read the ADCDRH register. This clears EOC
automatically.
After wakeup from Halt mode, the A/D
Converter requires a stabilization time
HALT
t
(see Electrical Characteristics)
STAB
To read only 8 bits, perform the following steps:
1. Poll EOC bit
before accurate conversions can be
performed.
2. Read the ADCDRH register. This clears EOC
automatically.
10.10.5 Interrupts
10.10.3.3 Changing the conversion channel
None.
The application can change channels during con-
version. When software modifies the CH[3:0] bits
211/263
ST72561
10-BIT A/D CONVERTER (ADC) (Cont’d)
10.10.6 Register Description
CONTROL/STATUS REGISTER (ADCCSR)
Read/Write (Except bit 7 read only)
Reset Value: 0000 0000 (00h)
Channel Pin*
CH3 CH2 CH1 CH0
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
7
0
EOC SPEED ADON SLOW CH3
CH2
CH1
CH0
Bit 7 = EOC End of Conversion
This bit is set by hardware. It is cleared by soft-
ware reading the ADCDRH register or writing to
any bit of the ADCCSR register.
AIN9
AIN10
AIN11
AIN12
AIN13
AIN14
AIN15
0: Conversion is not complete
1: Conversion complete
Bit 6 = SPEED A/D clock selection
This bit is set and cleared by software.
DATA REGISTER (ADCDRH)
Read Only
Table 34. A/D Clock Selection
f
SLOW
SPEED
ADC
Reset Value: 0000 0000 (00h)
f
/2
0
0
1
0
1
0
CPU
f
(where f
<= 4 MHz)
CPU
CPU
7
0
f
/4
CPU
f
/2 (same frequency as
SLOW=0, SPEED=0)
CPU
1
1
D9
D8
D7
D6
D5
D4
D3
D2
Bit 5 = ADON A/D Converter on
This bit is set and cleared by software.
0: Disable ADC and stop conversion
1: Enable ADC and start conversion
Bits 7:0 = D[9:2] MSB of Analog Converted Value
DATA REGISTER (ADCDRL)
Read Only
Bit 4 = SLOW A/D Clock Selection
This bit is set and cleared by software. It works to-
gether with the SPEED bit. Refer to Table 34.
Reset Value: 0000 0000 (00h)
7
0
0
Bits 3:0 = CH[3:0] Channel Selection
These bits are set and cleared by software. They
select the analog input to convert.
*The number of channels is device dependent. Refer to
the device pinout description.
0
0
0
0
0
D1
D0
Bits 7:2 = Reserved. Forced by hardware to 0.
Bits 1:0 = D[1:0] LSB of Analog Converted Value
212/263
ST72561
10-BIT A/D CONVERTER (ADC) (Cont’d)
Table 35. ADC Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
ADCCSR
Reset Value
EOC
0
SPEED
0
ADON
0
SLOW
0
CH3
0
CH2
0
CH1
0
CH0
0
45h
46h
47h
ADCDRH
Reset Value
D9
0
D8
0
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
ADCDRL
Reset Value
0
0
0
0
0
0
0
0
0
0
0
0
D1
0
D0
0
213/263
ST72561
11 INSTRUCTION SET
11.1 CPU ADDRESSING MODES
so, most of the addressing modes may be subdi-
vided in two submodes called long and short:
The CPU features 17 different addressing modes
which can be classified in seven main groups:
– Long addressing mode is more powerful be-
cause it can use the full 64 Kbyte address space,
however it uses more bytes and more CPU cy-
cles.
Addressing Mode
Inherent
Example
nop
– Short addressing mode is less powerful because
it can generally only access page zero (0000h -
00FFh range), but the instruction size is more
compact, and faster. All memory to memory in-
structions use short addressing modes only
(CLR, CPL, NEG, BSET, BRES, BTJT, BTJF,
INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP)
Immediate
Direct
ld A,#$55
ld A,$55
ld A,($55,X)
ld A,([$55],X)
jrne loop
Indexed
Indirect
Relative
Bit operation
bset byte,#5
The ST7 Assembler optimizes the use of long and
short addressing modes.
The CPU Instruction set is designed to minimize
the number of bytes required per instruction: To do
Table 36. CPU Addressing Mode Overview
Pointer
Address
(Hex.)
Pointer Size
(Hex.)
Length
(Bytes)
Mode
Syntax
Destination
Inherent
Immediate
Short
Long
nop
+ 0
ld A,#$55
+ 1
+ 1
+ 2
+ 0
+ 1
+ 2
+ 2
+ 2
+ 2
+ 2
+ 1
+ 2
+ 1
+ 2
+ 2
+ 3
Direct
ld A,$10
00..FF
Direct
ld A,$1000
ld A,(X)
0000..FFFF
00..FF
No Offset
Short
Long
Direct
Indexed
Indexed
Indexed
Direct
ld A,($10,X)
ld A,($1000,X)
ld A,[$10]
00..1FE
0000..FFFF
00..FF
Direct
Short
Long
Indirect
Indirect
Indirect
Indirect
Direct
00..FF
00..FF
00..FF
00..FF
byte
word
byte
word
ld A,[$10.w]
ld A,([$10],X)
ld A,([$10.w],X)
jrne loop
0000..FFFF
00..1FE
0000..FFFF
PC+/-127
PC+/-127
00..FF
Short
Long
Indexed
Indexed
Relative
Relative
Bit
Indirect
Direct
jrne [$10]
00..FF
00..FF
00..FF
byte
byte
byte
bset $10,#7
bset [$10],#7
btjt $10,#7,skip
btjt [$10],#7,skip
Bit
Indirect
Direct
00..FF
Bit
Relative
Relative
00..FF
Bit
Indirect
00..FF
214/263
ST72561
INSTRUCTION SET OVERVIEW (Cont’d)
11.1.1 Inherent
11.1.3 Direct
All Inherent instructions consist of a single byte.
The opcode fully specifies all the required informa-
tion for the CPU to process the operation.
In Direct instructions, the operands are referenced
by their memory address.
The direct addressing mode consists of two sub-
modes:
Inherent Instruction
Function
No operation
Direct (short)
NOP
The address is a byte, thus requires only one byte
after the opcode, but only allows 00 - FF address-
ing space.
TRAP
S/W Interrupt
Wait For Interrupt (Low Pow-
er Mode)
WFI
Direct (long)
Halt Oscillator (Lowest Power
Mode)
HALT
The address is a word, thus allowing 64 Kbyte ad-
dressing space, but requires 2 bytes after the op-
code.
RET
Sub-routine Return
Interrupt Sub-routine Return
Set Interrupt Mask (level 3)
Reset Interrupt Mask (level 0)
Set Carry Flag
IRET
SIM
11.1.4 Indexed (No Offset, Short, Long)
RIM
In this mode, the operand is referenced by its
memory address, which is defined by the unsigned
addition of an index register (X or Y) with an offset.
SCF
RCF
Reset Carry Flag
RSP
Reset Stack Pointer
Load
The indirect addressing mode consists of three
submodes:
LD
CLR
Clear
Indexed (No Offset)
PUSH/POP
INC/DEC
TNZ
Push/Pop to/from the stack
Increment/Decrement
Test Negative or Zero
1 or 2 Complement
Byte Multiplication
There is no offset, (no extra byte after the opcode),
and allows 00 - FF addressing space.
Indexed (Short)
CPL, NEG
MUL
The offset is a byte, thus requires only one byte af-
ter the opcode and allows 00 - 1FE addressing
space.
SLL, SRL, SRA, RLC,
RRC
Shift and Rotate Operations
Swap Nibbles
Indexed (long)
SWAP
The offset is a word, thus allowing 64 Kbyte ad-
dressing space and requires 2 bytes after the op-
code.
11.1.2 Immediate
Immediate instructions have 2 bytes, the first byte
contains the opcode, the second byte contains the
operand value.
11.1.5 Indirect (Short, Long)
The required data byte to do the operation is found
by its memory address, located in memory (point-
er).
Immediate Instruction
Function
LD
Load
The pointer address follows the opcode. The indi-
rect addressing mode consists of two submodes:
CP
Compare
BCP
Bit Compare
Indirect (short)
AND, OR, XOR
ADC, ADD, SUB, SBC
Logical Operations
Arithmetic Operations
The pointer address is a byte, the pointer size is a
byte, thus allowing 00 - FF addressing space, and
requires 1 byte after the opcode.
Indirect (long)
The pointer address is a byte, the pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.
215/263
ST72561
INSTRUCTION SET OVERVIEW (Cont’d)
11.1.6 Indirect Indexed (Short, Long)
11.1.7 Relative mode (Direct, Indirect)
This is a combination of indirect and short indexed
addressing modes. The operand is referenced by
its memory address, which is defined by the un-
signed addition of an index register value (X or Y)
with a pointer value located in memory. The point-
er address follows the opcode.
This addressing mode is used to modify the PC
register value, by adding an 8-bit signed offset to
it.
Available Relative
Direct/Indirect
Instructions
Function
The indirect indexed addressing mode consists of
two submodes:
JRxx
CALLR
Conditional Jump
Call Relative
Indirect Indexed (Short)
The pointer address is a byte, the pointer size is a
byte, thus allowing 00 - 1FE addressing space,
and requires 1 byte after the opcode.
The relative addressing mode consists of two sub-
modes:
Relative (Direct)
Indirect Indexed (Long)
The offset is following the opcode.
Relative (Indirect)
The pointer address is a byte, the pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.
The offset is defined in memory, which address
follows the opcode.
Table 37. Instructions Supporting Direct,
Indexed, Indirect and Indirect Indexed
Addressing Modes
Long and Short
Function
Instructions
LD
Load
CP
Compare
AND, OR, XOR
Logical Operations
Arithmetic Additions/Sub-
stractions operations
ADC, ADD, SUB, SBC
BCP
Bit Compare
Short Instructions Only
CLR
Function
Clear
INC, DEC
Increment/Decrement
Test Negative or Zero
1 or 2 Complement
Bit Operations
TNZ
CPL, NEG
BSET, BRES
Bit Test and Jump Opera-
tions
BTJT, BTJF
SLL, SRL, SRA, RLC,
RRC
Shift and Rotate Operations
SWAP
Swap Nibbles
CALL, JP
Call or Jump subroutine
216/263
ST72561
INSTRUCTION SET OVERVIEW (Cont’d)
11.2 INSTRUCTION GROUPS
The ST7 family devices use an Instruction Set
consisting of 63 instructions. The instructions may
be subdivided into 13 main groups as illustrated in
the following table:
Load and Transfer
LD
CLR
POP
DEC
TNZ
OR
Stack operation
PUSH
INC
RSP
BCP
Increment/Decrement
Compare and Tests
Logical operations
CP
AND
BSET
BTJT
ADC
SLL
XOR
CPL
NEG
Bit Operation
BRES
BTJF
ADD
SRL
JRT
Conditional Bit Test and Branch
Arithmetic operations
Shift and Rotates
SUB
SRA
JRF
SBC
RLC
JP
MUL
RRC
CALL
SWAP
CALLR
SLA
Unconditional Jump or Call
Conditional Branch
JRA
JRxx
TRAP
SIM
NOP
RET
Interruption management
Condition Code Flag modification
WFI
RIM
HALT
SCF
IRET
RCF
Using a prebyte
The instructions are described with one to four op-
codes.
These prebytes enable instruction in Y as well as
indirect addressing modes to be implemented.
They precede the opcode of the instruction in X or
the instruction using direct addressing mode. The
prebytes are:
In order to extend the number of available op-
codes for an 8-bit CPU (256 opcodes), three differ-
ent prebyte opcodes are defined. These prebytes
modify the meaning of the instruction they pre-
cede.
PDY 90
Replace an X based instruction
using immediate, direct, indexed, or inherent ad-
dressing mode by a Y one.
The whole instruction becomes:
PIX 92
Replace an instruction using di-
PC-2
PC-1
PC
End of previous instruction
Prebyte
rect, direct bit, or direct relative addressing mode
to an instruction using the corresponding indirect
addressing mode.
Opcode
It also changes an instruction using X indexed ad-
dressing mode to an instruction using indirect X in-
dexed addressing mode.
PC+1
Additional word (0 to 2) according
to the number of bytes required to compute the ef-
fective address
PIY 91
Replace an instruction using X in-
direct indexed addressing mode by a Y one.
217/263
ST72561
INSTRUCTION SET OVERVIEW (Cont’d)
Mnemo
ADC
ADD
AND
BCP
Description
Add with Carry
Function/Example
A = A + M + C
A = A + M
Dst
Src
I1
H
H
H
I0
N
N
N
N
N
Z
Z
Z
Z
Z
C
C
C
A
M
Addition
A
M
M
M
Logical And
A = A . M
A
Bit compare A, Memory
Bit Reset
tst (A . M)
A
BRES
BSET
BTJF
BTJT
CALL
CALLR
CLR
bres Byte, #3
bset Byte, #3
btjf Byte, #3, Jmp1
btjt Byte, #3, Jmp1
M
M
M
M
Bit Set
Jump if bit is false (0)
Jump if bit is true (1)
Call subroutine
Call subroutine relative
Clear
C
C
reg, M
reg
0
N
N
N
1
Z
Z
Z
CP
Arithmetic Compare
One Complement
Decrement
tst(Reg - M)
A = FFH-A
dec Y
M
C
1
CPL
reg, M
reg, M
DEC
HALT
IRET
INC
Halt
1
0
Interrupt routine return
Increment
Pop CC, A, X, PC
inc X
I1
H
I0
N
N
Z
Z
C
reg, M
JP
Absolute Jump
Jump relative always
Jump relative
jp [TBL.w]
JRA
JRT
JRF
Never jump
jrf *
JRIH
JRIL
Jump if ext. INT pin = 1
Jump if ext. INT pin = 0
Jump if H = 1
(ext. INT pin high)
(ext. INT pin low)
H = 1 ?
JRH
JRNH
JRM
Jump if H = 0
H = 0 ?
Jump if I1:0 = 11
Jump if I1:0 <> 11
Jump if N = 1 (minus)
Jump if N = 0 (plus)
Jump if Z = 1 (equal)
I1:0 = 11 ?
I1:0 <> 11 ?
N = 1 ?
JRNM
JRMI
JRPL
JREQ
JRNE
JRC
N = 0 ?
Z = 1 ?
Jump if Z = 0 (not equal) Z = 0 ?
Jump if C = 1
Jump if C = 0
Jump if C = 1
C = 1 ?
JRNC
JRULT
C = 0 ?
Unsigned <
Jmp if unsigned >=
Unsigned >
JRUGE Jump if C = 0
JRUGT Jump if (C + Z = 0)
218/263
ST72561
INSTRUCTION SET OVERVIEW (Cont’d)
Mnemo
JRULE
LD
Description
Jump if (C + Z = 1)
Load
Function/Example
Unsigned <=
dst <= src
Dst
Src
I1
H
I0
N
N
N
N
N
Z
Z
Z
Z
Z
C
reg, M
A, X, Y
reg, M
M, reg
X, Y, A
MUL
NEG
NOP
OR
Multiply
X,A = X * A
neg $10
0
0
Negate (2's compl)
No Operation
OR operation
C
A = A + M
pop reg
pop CC
push Y
C = 0
A
M
reg
CC
M
M
POP
Pop from the Stack
M
I1
1
H
I0
0
C
0
PUSH
RCF
RET
RIM
Push onto the Stack
Reset carry flag
Subroutine Return
Enable Interrupts
Rotate left true C
Rotate right true C
Reset Stack Pointer
Substract with Carry
Set carry flag
reg, CC
I1:0 = 10 (level 0)
C <= A <= C
C => A => C
S = Max allowed
A = A - M - C
C = 1
RLC
RRC
RSP
SBC
SCF
SIM
reg, M
reg, M
N
N
Z
Z
C
C
A
M
N
Z
C
1
Disable Interrupts
Shift left Arithmetic
Shift left Logic
I1:0 = 11 (level 3)
C <= A <= 0
C <= A <= 0
0 => A => C
A7 => A => C
A = A - M
1
1
SLA
reg, M
reg, M
reg, M
reg, M
A
N
N
0
Z
Z
Z
Z
Z
Z
Z
C
C
C
C
C
SLL
SRL
SRA
SUB
SWAP
TNZ
TRAP
WFI
Shift right Logic
Shift right Arithmetic
Substraction
N
N
N
N
M
M
SWAP nibbles
A7-A4 <=> A3-A0
tnz lbl1
reg, M
Test for Neg & Zero
S/W trap
S/W interrupt
1
1
1
0
Wait for Interrupt
Exclusive OR
XOR
A = A XOR M
A
N
Z
219/263
ST72561
12 ELECTRICAL CHARACTERISTICS
12.1 PARAMETER CONDITIONS
Unless otherwise specified, all voltages are re-
12.1.5 Pin Input Voltage
ferred to V
.
SS
The input voltage measurement on a pin of the de-
vice is described in Figure 118.
12.1.1 Minimum and Maximum Values
Unless otherwise specified the minimum and max-
imum values are guaranteed in the worst condi-
tions of ambient temperature, supply voltage and
frequencies by tests in production on 100% of the
Figure 118. Pin input voltage
ST7 PIN
devices with an ambient temperature at T = 25°C
A
and T = T max (given by the selected tempera-
A
A
ture range).
V
IN
Data based on characterization results, design
simulation and/or technology characteristics are
indicated in the table footnotes and are not tested
in production. Based on characterization, the min-
imum and maximum values refer to sample tests
and represent the mean value plus or minus three
times the standard deviation (mean 3Σ).
12.1.2 Typical Values
Unless otherwise specified, typical data is based
on
T = 25°C,
DD
V
= 5V
(for
the
A
DD
4.5V ≤ V ≤ 5.5V voltage range). They are given
only as design guidelines and are not tested.
Typical ADC accuracy values are determined by
characterization of a batch of samples from a
standard diffusion lot over the full temperature
range, where 95% of the devices have an error
less than or equal to the value indicated
(mean 2Σ).
12.1.3 Typical Curves
Unless otherwise specified, all typical curves are
given only as design guidelines and are not tested.
12.1.4 Loading Capacitor
The loading conditions used for pin parameter
measurement are shown in Figure 117.
Figure 117. Pin Loading Conditions
ST7 PIN
C
L
220/263
ST72561
12.2 ABSOLUTE MAXIMUM RATINGS
Stresses above those listed as “absolute maxi-
mum ratings” may cause permanent damage to
the device. This is a stress rating only and func-
tional operation of the device under these condi-
tions is not implied. Exposure to maximum rating
conditions for extended periods may affect device
reliability.
12.2.1 Voltage Characteristics
Symbol
Ratings
Maximum value
Unit
V
- V
- V
Supply voltage
6.5
DD
SS
SS
V
Programming Voltage
13
V
PP
1)2)
V
Input voltage on any pin
VSS - 0.3 to VDD + 0.3
IN
|∆V
| and |∆V
|
SSx
Variations between different digital power pins
Variations between digital and analog ground pins
Electro-static discharge voltage (Human Body Model)
Electro-static discharge voltage (Machine Model)
50
50
DDx
mV
|V
- V
|
SSA
SSx
V
ESD(HBM)
see Section 12.8.3 on page 233
V
ESD(MM)
12.2.2 Current Characteristics
Symbol
Ratings
Maximum value
Unit
3)
3)
I
Total current into V power lines (source)
DD
VDD
150
I
Total current out of V ground lines (sink)
SS
VSS
Output current sunk by any standard I/O and control pin
Output current sunk by any high sink I/O pin
25
50
I
IO
Output current source by any I/Os and control pin
- 25
Injected current on V pin
mA
PP
Injected current on RESET pin
5
2)4)
2)
I
Injected current on OSC1 and OSC2 pins
Injected current on PB3 (on Flash devices)
INJ(PIN)
+5
5
5)
Injected current on any other pin
5)
ΣI
Total injected current (sum of all I/O and control pins)
25
INJ(PIN)
12.2.3 Thermal Characteristics
Symbol
Ratings
Value
Unit
T
Storage temperature range
-65 to +150
°C
STG
T
Maximum junction temperature (see Section 13.2 "THERMAL CHARACTERISTICS")
J
Notes:
1. Directly connecting the RESET and I/O pins to V or V could damage the device if an unintentional internal reset
DD
SS
is generated or an unexpected change of the I/O configuration occurs (for example, due to a corrupted program counter).
To guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7kΩ for
RESET, 10kΩ for I/Os). Unused I/O pins must be tied in the same way to V or V according to their reset configuration.
DD
SS
2. I
must never be exceeded. This is implicitly insured if V maximum is respected. If V maximum cannot be
INJ(PIN)
IN
INJ(PIN)
IN
respected, the injection current must be limited externally to the I
value. A positive injection is induced by V >V
IN DD
while a negative injection is induced by V < V . For true open-drain pads, there is no positive injection current, and the
IN
SS
corresponding V maximum must always be respected
IN
3. All power (V ) and ground (V ) lines must always be connected to the external supply.
DD
SS
4. Negative injection disturbs the analog performance of the device. See note in “10-BIT ADC CHARACTERISTICS” on
page 245.
5. When several inputs are submitted to a current injection, the maximum ΣI
is the absolute sum of the positive
INJ(PIN)
and negative injected currents (instantaneous values). These results are based on characterization with ΣI
maxi-
INJ(PIN)
mum current injection on four I/O port pins of the device.
221/263
ST72561
12.3 OPERATING CONDITIONS
12.3.1 General Operating Conditions
Symbol
Parameter
Conditions
Min
Max
Unit
f
Internal clock frequency
0
8
MHz
CPU
No Flash Write/Erase. Analog
parameters not guaranteed.
Extended Operating voltage
3.8
4.5
V
V
DD
Standard Operating Voltage
4.5
4.5
0
5.5
5.5
70
Operating Voltage for Flash Write/Erase
V
= 11.4 to 12.6V
PP
1 Suffix Version
5 Suffix Version
6 Suffix Version
7 Suffix Version
3 Suffix Version
-10
85
T
Ambient temperature range
85
°C
A
-40
105
125
Figure 119. f
Maximum vs V
DD
CPU
FUNCTIONALITY GUARANTEED IN THIS AREA
UNLESS OTHERWISE SPECIFIED IN THE TABLES OF
PARAMETRIC DATA
f
[MHz]
CPU
FUNCTIONALITY
GUARANTEED
IN THIS AREA
8
6
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
4
2
1
0
3.5
3.8 4.0
4.5
5.0
5.5
SUPPLY VOLTAGE [V]
222/263
ST72561
12.3.2 Operating Conditions with Low Voltage Detector (LVD)
Subject to general operating conditions for T .
A
Symbol
Parameter
Reset release threshold (V rise)
Conditions
Min
Typ
4.2
Max
Unit
1)
V
4.0
3.8
4.5
IT+(LVD)
IT-(LVD)
hys(LVD)
DD
V
1)
V
V
Reset generation threshold (V fall)
4.0
4.25
250
DD
1)
LVD voltage threshold hysteresis
V
-V
150
6
200
mV
µs/V
ms/V
IT+(LVD) IT-(LVD)
1)
Vt
V
V
rise time rate
POR
DD
100
40
glitches filtered (not detected) by
DD
t
Measured at V
ns
1)
g(VDD)
IT-(LVD)
LVD
Notes:
1. Data based on characterization results, not tested in production.
12.3.3 Auxiliary Voltage Detector (AVD) Thresholds
Subject to general operating conditions for T .
A
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
1⇒0 AVDF flag toggle threshold
1)
V
4.4
4.6
4.9
IT+(AVD)
(V rise)
DD
V
0⇒1 AVDF flag toggle threshold
1)
V
V
4.2
4.4
250
450
4.65
IT-(AVD)
hys(AVD)
(V fall)
DD
AVD voltage threshold hysteresis
V
V
-V
IT+(AVD) IT-(AVD)
mV
Voltage drop between AVD flag set
and LVD reset activated
∆V
-V
IT-
IT-(AVD) IT-(LVD)
1. Data based on characterization results, not tested in production.
Figure 120. LVD Startup Behavior
5V
LVD RESET
V
IT+
2V
Reset state
not defined
in this area
t
Note: When the LVD is enabled, the MCU reaches its authorized operating voltage from a reset state.
However, in some devices, the reset signal may be undefined until V is approximately 2V. As a conse-
DD
quence, the I/Os may toggle when V is below this voltage.
DD
Because Flash write access is impossible below this voltage, the Flash memory contents will not be cor-
rupted.
223/263
ST72561
12.4 SUPPLY CURRENT CHARACTERISTICS
The following current consumption specified for
the ST7 functional operating modes over tempera-
ture range does not take into account the clock
source current consumption. To get the total de-
vice consumption, the two current values must be
added (except for HALT mode for which the clock
is stopped).
Flash Devices ROM Devices
Symbol
Parameter
Conditions
Unit
2)
1)
2)
1
Typ
Max
Typ
Max
f
f
f
f
= 2 MHz, f
= 4 MHz, f
= 8 MHz, f
= 1 MHz
= 2 MHz
= 4 MHz
1.8
3.2
6
3
5
1.1
2.2
4.4
8.9
2
OSC
OSC
OSC
OSC
CPU
CPU
CPU
3.5
6
3)
Supply current in RUN mode
8
= 16 MHz, f
= 8 MHz
10
15
12
CPU
f
f
f
f
= 2 MHz, f
= 4 MHz, f
= 8 MHz, f
= 62.5kHz
= 125 kHz
= 250 kHz
0.5
0.6
0.85
1.25
2.7
3
3.6
4
0.1
0.2
0.4
0.8
0.2
0.4
0.8
1.5
OSC
OSC
OSC
OSC
CPU
CPU
CPU
3)
Supply current in SLOW mode
= 16 MHz, f
= 500 kHz
CPU
mA
f
f
f
f
= 2 MHz, f
= 4 MHz, f
= 8 MHz, f
= 1 MHz
= 2 MHz
= 4 MHz
1
3
4
5
7
0.7
1.4
2.9
5.7
3
4
5
7
OSC
OSC
OSC
OSC
CPU
CPU
CPU
1.8
3.4
6.4
3)
Supply current in WAIT mode
= 16 MHz, f
= 8 MHz
CPU
I
DD
f
f
f
f
= 2 MHz, f
= 4 MHz, f
= 8 MHz, f
= 62.5 kHz
= 125 kHz
= 250 kHz
0.4
0.5
0.6
0.8
1.2
1.3
1.8
2
0.07
0.14
0.28
0.56
0.12
0.25
0.5
1
OSC
OSC
OSC
OSC
CPU
CPU
CPU
Supply current in SLOW WAIT
mode
2)
= 16 MHz, f
= 500 kHz
CPU
-40°C ≤ T ≤ +85°C
10
50
10
50
A
4)
Supply current in HALT mode
V
= 5.5V
<1
0.5
25
<1
0.18
25
µA
DD
-40°C ≤ T ≤ +125°C
A
Supply current in ACTIVE HALT
1.2
0.25 mA
4)5)
mode
-40°C ≤ T ≤ +85°C
30
70
30
µA
70
Supply current in AWUFH
A
V
= 5.5V
4)5)
DD
mode
-40°C ≤ T ≤ +125°C
A
Notes:
1. Typical data are based on T = 25°C, V = 5V (4.5V ≤ V ≤ 5.5V range).
A
DD
DD
2. Data based on characterization results, tested in production at V max., f
max. and T max.
A
DD
CPU
3. Measurements are done in the following conditions:
- Program executed from Flash, CPU running with Flash (for flash devices).
- All I/O pins in input mode with a static value at V or V (no load)
DD
SS
- All peripherals in reset state.
- Clock input (OSC1) driven by external square wave.
- In SLOW and SLOW WAIT mode, f is based on f
divided by 32.
OSC
CPU
To obtain the total current consumption of the device, add the clock source (Section 12.5.3) and the peripheral power
consumption (Section 12.4.2).
4. All I/O pins in input mode with a static value at V or V (no load). Data based on characterization results, tested in
DD
SS
production at V max., f
max. and T max.
DD
CPU
A
5. This consumption refers to the Halt period only and not the associated run period which is software dependent.
224/263
ST72561
SUPPLY CURRENT CHARACTERISTICS (Cont’d)
12.4.1 Supply and Clock Managers
The previous current consumption specified for
the ST7 functional operating modes over tempera-
ture range does not take into account the clock
source current consumption. To obtain the total
device consumption, the two current values must
be added (except for HALT mode).
1)
Symbol
Parameter
Supply current of resonator oscillator
PLL supply current
Conditions
Typ
Max
Unit
2)3)
See Section 12.5.3 on page 228
360
I
DD(RES)
I
V
= 5V
DD
µA
DD(PLL)
I
LVD supply current
HALT mode, V = 5V
150
300
DD(LVD)
DD
Notes:
1. Data based on characterization results, not tested in production.
2. Data based on characterization results done with the external components specified in Section 12.5.3, not tested in
production.
3. As the oscillator is based on a current source, the consumption does not depend on the voltage.
225/263
ST72561
12.4.2 On-Chip Peripherals
T = 25°C, f
= 8 MHz.
A
CPU
Symbol
Parameter
Conditions
Typ
50
Unit
1)
I
16-bit Timer supply current
DD(TIM)
1)
I
8-bit Timer supply current
DD(TIM8)
2)
I
ART PWM supply current
75
DD(ART)
µA
3)
V
= 5.0V
I
SPI supply current
DD
DD(SPI)
4)
I
SCI supply current
400
800
DD(SCI)
5)
I
I
ADC supply current when converting
DD(ADC)
DD(CAN)
6)
CAN supply current
Notes:
1. Data based on a differential I measurement between reset configuration (timer counter running at f
/4) and timer
DD
CPU
counter stopped (only TIMD bit set). Data valid for one timer.
2. Data based on a differential I measurement between reset configuration (timer stopped) and timer counter enabled
DD
(only TCE bit set).
3. Data based on a differential I measurement between reset configuration (SPI disabled) and a permanent SPI master
DD
communication at maximum speed (data sent equal to 55h).This measurement includes the pad toggling consumption.
4. Data based on a differential I measurement between SCI low power state (SCID = 1) and a permanent SCI data
DD
transmit sequence. Data valid for one SCI.
5. Data based on a differential I measurement between reset configuration and continuous A/D conversions.
DD
6. Data based on a differential I measurement between reset configuration (CAN disabled) and a permanent CAN data
DD
transmit sequence with RX and TX connected together. This measurement include the pad toggling consumption.
226/263
ST72561
12.5 CLOCK AND TIMING CHARACTERISTICS
Subject to general operating conditions for V , f
, and T .
DD OSC
A
12.5.1 General Timings
1)
Symbol
Parameter
Conditions
Min
2
Typ
Max
12
Unit
tCPU
ns
3
t
Instruction cycle time
c(INST)
f
f
= 8 MHz
250
10
375
1500
22
CPU
CPU
2)
tCPU
µs
Interrupt reaction time
t
v(IT)
t
= ∆t
+ 10
c(INST)
= 8 MHz
1.25
2.75
v(IT)
12.5.2 External Clock Source
Symbol
Parameter
Conditions
Min
0.7 x V
Typ
Max
Unit
V
OSC1 input pin high level voltage
OSC1 input pin low level voltage
V
DD
OSC1H
DD
V
V
V
0.3 x V
DD
OSC1L
SS
t
t
3)
w(OSC1H)
see Figure 121
OSC1 high or low time
25
w(OSC1L)
ns
t
t
3)
r(OSC1)
OSC1 rise or fall time
5
1
f(OSC1)
V
≤ V ≤ V
IN DD
I
OSCx Input leakage current
µA
SS
L
Figure 121. Typical Application with an External Clock Source
90%
V
V
OSC1H
OSC1L
10%
t
t
w(OSC1H)
t
t
w(OSC1L)
f(OSC1)
r(OSC1)
OSC2
Not connected internally
f
OSC
EXTERNAL
CLOCK SOURCE
I
L
OSC1
ST72XXX
Notes:
1. Data based on typical application software.
2. Time measured between interrupt event and interrupt vector fetch. ∆tc(INST) is the number of tCPU cycles needed to finish
the current instruction execution.
3. Data based on design simulation and/or technology characteristics, not tested in production.
227/263
ST72561
CLOCK AND TIMING CHARACTERISTICS (Cont’d)
12.5.3 Crystal and Ceramic Resonator Oscillators
The ST7 internal clock can be supplied with four
different Crystal/Ceramic resonator oscillators. All
the information given in this paragraph is based on
characterization results with specified typical ex-
ternal components. In the application, the resona-
tor and the load capacitors have to be placed as
close as possible to the oscillator pins in order to
minimize output distortion and start-up stabiliza-
tion time. Refer to the crystal/ceramic resonator
manufacturer for more details (frequency, pack-
1)2)
age, accuracy...).
Symbol
Parameter
Conditions
Min
Max
Unit
MHz
kΩ
LP: Low power oscillator
1
2
4
8
MP: Medium power oscillator
MS: Medium speed oscillator
HS: High speed oscillator
>2
>4
>8
3)
f
Oscillator Frequency
OSC
16
R
Feedback resistor
20
40
F
R = 200Ω
S
LP oscillator
MP oscillator
MS oscillator
HS oscillator
22
22
18
15
56
46
33
33
S
Recommended load capacitance ver-
sus equivalent serial resistance of the
C
C
R = 200Ω
L1
L2
pF
R = 200Ω
S
crystal or ceramic resonator (R )
S
R = 100Ω
S
Symbol
Parameter
Conditions
Typ
Max
Unit
V
V
= 5V
LP oscillator
MP oscillator
MS oscillator
HS oscillator
80
150
250
460
910
DD
= V
160
310
610
IN
SS
i
OSC2 driving current
µA
2
Figure 122. Typical Application with a Crystal or Ceramic Resonator
WHEN RESONATOR WITH
INTEGRATED CAPACITORS
i
2
f
OSC
C
L1
OSC1
OSC2
RESONATOR
R
F
C
L2
ST72XXX
Notes:
1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
2. t is the typical oscillator start-up time measured between V = 2.8V and the fetch of the first instruction (with
SU(OSC)
DD
a quick V ramp-up from 0 to 5V (< 50µs).
DD
3. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small R value.
S
Refer to crystal/ceramic resonator manufacturer for more details.
228/263
ST72561
CLOCK CHARACTERISTICS (Cont’d)
12.5.4 PLL Characteristics
1)
Operating conditions: V 3.8 to 5.5V @ T 0 to 70°C or V 4.5 to 5.5V @ T -40 to 125°C
DD
A
DD
A
Symbol
Parameter
Conditions
Min
3.8
4.5
2
Typ
Max
5.5
4
Unit
T = 0 to +70°C
T = -40 to +125°C
A
V
PLL Voltage Range
DD(PLL)
OSC
A
f
PLL input frequency range
MHz
%
f
f
= 4 MHz, V = 4.5 to 5.5V
DD
OSC
1)
∆ f
/f
PLL jitter
Note 2
CPU CPU
= 2 MHz, V = 4.5 to 5.5V
OSC
DD
Notes:
1. Data characterized but not tested.
2. Under characterization
1)
Figure 123. PLL Jitter vs Signal Frequency
The user must take the PLL jitter into account in
the application (for example in serial communica-
tion or sampling of high frequency signals). The
PLL jitter is a periodic effect, which is integrated
over several CPU cycles. Therefore, the longer the
period of the application signal, the less it is im-
pacted by the PLL jitter.
0.8
0.7
PLL ON
0.6
0.5
0.4
0.3
0.2
0.1
0
PLL OFF
Figure 123 shows the PLL jitter integrated on ap-
plication signals in the range 125 kHz to 2 MHz. At
frequencies of less than 125 kHz, the jitter is neg-
ligible.
2000
1000
500
250
125
Application Signal Frequency (KHz)
Notes:
1. Measurement conditions: f
= 4 MHz, T = 25°C
CPU
A
229/263
ST72561
CLOCK CHARACTERISTICS (Cont’d)
12.6 Auto Wakeup from Halt Oscillator (AWU)
Symbol
Parameter
Conditions
Min
Typ
100
10
Max
Unit
kHz
µs
1)
f
AWU oscillator frequency
50
250
AWU
t
AWU oscillator startup time
RCSRT
1. Data based on characterization results, not tested in production.
Figure 124. AWU Oscillator Freq. @ T 25°C
A
200
150
100
Ta=25C
50
4.4
5
Vdd
5.6
230/263
ST72561
12.7 MEMORY CHARACTERISTICS
12.7.1 RAM and Hardware Registers
Symbol
Parameter
Conditions
Min
Typ
Typ
Max
Unit
1)
V
Data retention mode
HALT mode (or RESET)
1.6
V
RM
12.7.2 FLASH Memory
DUAL VOLTAGE HDFLASH MEMORY
Symbol Parameter
2)
2)
Conditions
Read mode
Min
Max
8
Unit
0
1
f
Operating frequency
MHz
CPU
Write / Erase mode
4.5V ≤ VDD ≤ 5.5V
8
3)
V
Programming voltage
11.4
12.6
200
30
V
PP
Read (V = 12V)
µA
mA
µs
PP
4)5)
I
V
current
PP
PP
Write / Erase
4)
t
Internal V stabilization time
10
VPP
RET
PP
T = 85°C
40
25
A
t
Data retention
T = 105°C
years
A
T = 125°C
10
A
N
Write erase cycles
T = 25°C
100
cycles
°C
RW
A
T
Programming or erasing temperature
range
PROG
-40
25
85
T
ERASE
Notes:
1. Minimum V supply voltage without losing data stored in RAM (in HALT mode or under RESET) or in hardware reg-
DD
isters (only in HALT mode). Not tested in production.
2. Data based on characterization results, not tested in production.
3. V must be applied only during the programming or erasing operation and not permanently for reliability reasons.
PP
4. Data based on simulation results, not tested in production.
5. In Write / erase mode the I supply current consumption is the same as in Run mode (see Section 12.2.2)
DD
231/263
ST72561
12.8 EMC CHARACTERISTICS
tion environment and simplified MCU software. It
should be noted that good EMC performance is
highly dependent on the user application and the
software in particular.
Susceptibility tests are performed on a sample ba-
sis during product characterization.
12.8.1 Functional EMS (Electro Magnetic
Susceptibility)
Therefore it is recommended that the user applies
EMC software optimization and prequalification
tests in relation with the EMC level requested for
his application.
Based on a simple running application on the
product (toggling two LEDs through I/O ports), the
product is stressed by two electro magnetic events
until a failure occurs (indicated by the LEDs).
■ ESD: Electro-Static Discharge (positive and
negative) is applied on all pins of the device until
a functional disturbance occurs. This test
conforms with the IEC 1000-4-2 standard.
Software recommendations:
The software flowchart must include the manage-
ment of runaway conditions such as:
– Corrupted program counter
– Unexpected reset
■ FTB: A Burst of Fast Transient voltage (positive
– Critical Data corruption (control registers...)
Prequalification trials:
and negative) is applied to V and V through
DD
SS
a 100pF capacitor, until a functional disturbance
occurs. This test conforms with the IEC 1000-4-
4 standard.
Most of the common failures (unexpected reset
and program counter corruption) can be repro-
duced by manually forcing a low state on the RE-
SET pin or the Oscillator pins for 1 second.
A device reset allows normal operations to be re-
sumed. The test results are given in the table be-
low based on the EMS levels and classes defined
in application note AN1709.
To complete these trials, ESD stress can be ap-
plied directly on the device, over the range of
specification values. When unexpected behavior
is detected, the software can be hardened to pre-
vent unrecoverable errors occurring (see applica-
tion note AN1015).
12.8.1.1 Designing hardened software to avoid
noise problems
EMC characterization and optimization are per-
formed at component level with a typical applica-
Level/
Symbol
Parameter
Conditions
Class
Voltage limits to be applied on any I/O pin to induce a
functional disturbance
V
= 5V, T = +25°C, f
OSC
= 8 MHz
DD
A
V
FESD
conforms to IEC 1000-4-2
= 5V, T = +25°C, f
OSC
3B
Fast transient voltage burst limits to be applied
V
= 8 MHz
DD
A
V
through 100pF on V and V pins to induce a func-
FFTB
DD DD
conforms to IEC 1000-4-4
tional disturbance
12.8.2 Electro Magnetic Interference (EMI)
emission test is in line with the norm SAE J 1752/
3 which specifies the board and the loading of
each pin.
Based on a simple application running on the
product (toggling two LEDs through the I/O ports),
the product is monitored in terms of emission. This
Max vs. [f
/f
]
Unit
Monitored
Frequency Band
OSC CPU
Symbol Parameter
Conditions
8/4 MHz 16/8 MHz
0.1 MHz to 30 MHz
30 MHz to 130 MHz
130 MHz to 1 GHz
SAE EMI Level
31
32
11
3.0
10
15
-3
32
37
16
3.5
18
25
1
Flash devices: V = 5V, T = +25°C,
DD
A
dBµV
LQFP64 package
conforming to SAE J 1752/3
-
dBµV
-
S
Peak level
EMI
0.1 MHz to 30 MHz
30 MHz to 130 MHz
130 MHz to 1 GHz
SAE EMI Level
ROM devices: V = 5V, T = +25°C,
DD
A
LQFP64 package
conforming to SAE J 1752/3
2.0
2.5
Notes:
1. Not tested in production.
232/263
ST72561
EMC CHARACTERISTICS (Cont’d)
12.8.3 Absolute Maximum Ratings (Electrical
Sensitivity)
12.8.3.2 Static and Dynamic Latch-Up
■ LU: Three complementary static tests are
required on 10 parts to assess the latch-up
performance. A supply overvoltage (applied to
each power supply pin) and a current injection
(applied to each input, output and configurable I/
O pin) are performed on each sample. This test
conforms to the EIA/JESD 78 IC latch-up
standard. For more details, refer to application
note AN1181.
Based on three different tests (ESD, LU and DLU)
using specific measurement methods, the product
is stressed in order to determine its performance in
terms of electrical sensitivity (see Table 38 and
Table 39 below). For more details, refer to applica-
tion note AN1181.
12.8.3.1 Electro-Static Discharge (ESD)
Electro-Static Discharges (a positive then a nega-
tive pulse separated by 1 second) are applied to
the pins of each sample according to each pin
combination. The sample size depends on the
number of supply pins in the device (3 parts*(n+1)
supply pin). Two models can be simulated: Human
Body Model and Machine Model. This test con-
forms to the JESD22-A114A/A115A standard.
■ DLU: Electro-Static Discharges (one positive
then one negative test) are applied to each pin
of three samples when the micro is running to
assess the latch-up performance in dynamic
mode. Power supplies are set to the typical
values, the oscillator is connected as near as
possible to the pins of the micro and the
component is put in reset mode. This test
conforms to the IEC1000-4-2 and SAEJ1752/3
standards. For more details, refer to application
note AN1181.
Table 38. Absolute Maximum Ratings
1)
Symbol
Ratings
Conditions
Maximum value
Unit
V
Electro-static discharge voltage (Human Body Model)
Electro-static discharge voltage (Machine Model)
2000
200
ESD(HBM)
V
ESD(MM)
T = +25°C
V
A
750 on corner pins,
500 on others
V
Electro-static discharge voltage (Charge Device Model)
ESD(CDM)
Notes:
1. Data based on characterization results, not tested in production.
Table 39. Electrical Sensitivities
1)
Symbol
Parameter
Static latch-up class
Dynamic latch-up class
Conditions
Class
T = +25°C
A
A
LU
T = +85°C
A
T = +125°C
A
V
= 5.5V, f
= 4 MHz, T = +25°C
OSC A
DLU
DD
Notes:
1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC spec-
ifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the
JEDEC criteria (international standard).
233/263
ST72561
12.9 I/O PORT PIN CHARACTERISTICS
12.9.1 General Characteristics
Subject to general operating conditions for V , f
, and T unless otherwise specified.
A
DD OSC
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
1)
V
Input low level voltage
Input high level voltage
0.3 x VDD
IL
1)
V
CMOS ports
TTL ports
0.7 x VDD
IH
2)
2)
V
Schmitt trigger voltage hysteresis
1
V
hys
1)
V
Input low level voltage
0.8
IL
1)
V
Input high level voltage
2
0
IH
V
Schmitt trigger voltage hysteresis
Injected Current on PB3
400
mV
mA
hys
Flash devices
ROM devices
+4
4
I
INJ(PIN)
V
= 5V
Injected Current on any other I/O pin
Total injected current (sum of all I/O
and control pins)
4
DD
3)
ΣI
25
7)
INJ(PIN)
Input leakage current on robust pins See “10-BIT ADC CHARACTERISTICS” on page 245
I
lkg
4)
Input leakage current
V
SS ≤ VIN ≤ V
1
DD
µA
5)
I
Static current consumption
Floating input mode
200
90
5
S
6)
R
Weak pull-up equivalent resistor
I/O pin capacitance
V
IN = V = 5V
V
DD
50
250
kΩ
PU
SS
C
pF
IO
t
Output high to low level fall time
C = 50pF
Between 10% and 90%
f(IO)out
r(IO)out
L
25
ns
t
Output low to high level rise time
7)
t
External interrupt pulse time
1
t
CPU
w(IT)in
Notes:
1. Data based on characterization results, not tested in production.
2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
3. When the current limitation is not possible, the V absolute maximum rating must be respected, otherwise refer to
IN
I
specification. A positive injection is induced by V > V while a negative injection is induced by V < V . Refer
IN DD IN SS
INJ(PIN)
to Section 12.2 on page 221 for more details.
4. Leakage could be higher than max. if negative current is injected on adjacent pins.
5. Configuration not recommended, all unused pins must be kept at a fixed voltage: Using the output mode of the I/O, for
example, or an external pull-up or pull-down resistor (see Figure 125). Data based on design simulation and/or technol-
ogy characteristics, not tested in production.
6. The R pull-up equivalent resistor is based on a resistive transistor (corresponding I current characteristics de-
PU
PU
scribed in Figure 126).
7. To generate an external interrupt, a minimum pulse width must be applied on an I/O port pin configured as an external
interrupt source.
234/263
ST72561
I/O PORT PIN CHARACTERISTICS (Cont’d)
Figure 125. Connecting Unused I/O Pins
Figure 127. I vs V with V = V
PU DD IN SS
V
ST72XXX
DD
Ta=-45C
Ta=25C
Ta=130C
100
80
60
40
20
0
10kΩ
UNUSED I/O PORT
UNUSED I/O PORT
10kΩ
3.5
4
4.5
Vdd
5
5.5
ST72XXX
Figure 126. R vs V with V = V
PU
DD
IN
SS
200
150
100
50
Ta=-45C
Ta=25C
Ta=130C
0
3.5
4
4.5
5
5.5
Vdd
235/263
ST72561
I/O PORT PIN CHARACTERISTICS (Cont’d)
12.9.2 Output Driving Current
Subject to general operating conditions for V , f
, and T unless otherwise specified.
A
DD OSC
Symbol
Parameter
Conditions
Min
Max
Unit
Output low level voltage for a standard I/O pin
when eight pins are sunk at same time
(see Figure 128)
I
I
I
=+5mA
=+2mA
1.2
IO
IO
IO
0.5
1)
V
OL
=+20mA,T ≤85°C
1.3
1.5
A
Output low level voltage for a high sink I/O pin
when four pins are sunk at same time
(see Figure 129 and Figure 132)
T ≥85°C
A
V
I
I
=+8mA
0.6
IO
=-5mA, T ≤85°C
V
V
-1.4
IO
A
Output high level voltage for an I/O pin
when four pins are sourced at same time
(see Figure 130 and Figure 133)
DD
DD
2)
OH
-1.6
T ≥85°C
V
A
I
=-2mA
V
-0.7
IO
DD
Figure 128. Typical V at V = 5V (Standard)
Figure 130. Typical V at V = 5V
OH DD
OL
DD
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
4.9
4.8
4.7
4.6
4.5
4.4
4.3
4.2
4.1
-45°C
25°C
130°C
-45°C 130°C
25°C
2
5
-2
-5
Iio(mA)
Iio(mA)
Figure 129. Typical V at V = 5V (High-sink)
OL
DD
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
-45°C
25°C
130°C
2
5
8
20
Iol (mA)
Notes:
1. The I current sunk must always respect the absolute maximum rating specified in Section 12.2.2 and the sum of I
IO
IO
(I/O ports and control pins) must not exceed I
.
VSS
2. The I current sourced must always respect the absolute maximum rating specified in Section 12.2.2 and the sum of
IO
I
(I/O ports and control pins) must not exceed I
. True open drain I/O pins does not have V
.
IO
VDD
OH
236/263
ST72561
I/O PORT PIN CHARACTERISTICS (Cont’d)
Figure 131. Typical V vs V (Standard I/Os)
OL
DD
1.1
0.4
0.35
0.3
-45°C
25°C
-45°C
25°C
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
130°C
130°C
0.25
0.2
0.15
0.1
3
4
5
6
3
4
5
6
Vdd(V)
Vdd(V)
Figure 132. Typical V vs V (High-sink I/Os)
OL
DD
0.4
0.35
0.3
1.3
1.2
1.1
1
-45°C
25°C
-45°C
25°C
130°C
130°C
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.25
0.2
0.15
0.1
3
4
5
6
3
4
5
6
Vdd(V)
Vdd(V)
237/263
ST72561
I/O PORT PIN CHARACTERISTICS (Cont’d)
Figure 133. Typical V vs V
OH
DD
6
5
4
3
2
6
5
4
3
2
1
-45°C
25°C
130°C
-45°C
25°C
130°C
3
4
5
6
3
4
5
6
Vdd(V)
Vdd(V)
238/263
ST72561
12.10 CONTROL PIN CHARACTERISTICS
12.10.1 Asynchronous RESET Pin
Subject to general operating conditions for V , f
, and T unless otherwise specified.
A
DD OSC
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
1)
V
Input low level voltage
0.3 x VDD
IL
1)
V
Input high level voltage
0.7 x VDD
IH
2)
V
Schmitt trigger voltage hysteresis
V
V
V
= 5V
1.5
0.68
0.28
40
V
hys
DD
DD
I
I
= +5mA
= +2mA
0.95
0.45
80
IO
IO
3)
V
R
Output low level voltage
= 5V
OL
4)
Weak pull-up equivalent resistor
Generated reset pulse duration
IN = V
20
kΩ
µs
ns
ON
SS
t
Internal reset source
30
w(RSTL)out
5)
t
t
External reset pulse hold time
2.5
h(RSTL)in
g(RSTL)in
6)
Filtered glitch duration
200
Notes:
1. Data based on characterization results, not tested in production.
2. Hysteresis voltage between Schmitt trigger switching levels.
3. The I current sunk must always respect the absolute maximum rating specified in Section 12.2.2 and the sum of I
IO
IO
(I/O ports and control pins) must not exceed I
.
VSS
4. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on
the RESET pin with a duration below t can be ignored.
h(RSTL)in
5. The reset network (the resistor and two capacitors) protects the device against parasitic resets, especially in noisy en-
vironments.
6. Data guaranteed by design, not tested in production.
239/263
ST72561
CONTROL PIN CHARACTERISTICS (Cont’d)
1)2)
Figure 134. RESET Pin Protection When LVD Is Enabled
V
ST72XXX
DD
Optional
(note 2.2)
Recommended
R
ON
Filter
INTERNAL
RESET
EXTERNAL
RESET
0.01µF
1MΩ
WATCHDOG
PULSE
GENERATOR
LVD RESET
1)
Figure 135. RESET Pin Protection When LVD Is Disabled
V
ST72XXX
DD
V
DD
R
ON
Filter
4.7kΩ
INTERNAL
RESET
USER
EXTERNAL
RESET
CIRCUIT
0.01µF
PULSE
GENERATOR
WATCHDOG
Required
Note 1:
1.1 The reset network protects the device against parasitic resets.
1.2 The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the
device can be damaged when the ST7 generates an internal reset (LVD or watchdog).
1.3 Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin can go below
the V max. level specified in Section 12.10.1. Otherwise the reset will not be taken into account internally.
IL
1.4 Because the reset circuit is designed to allow the internal RESET to be output in the RESET pin, the user must ensure
that the current sunk on the RESET pin (by an external pull-up for example) is less than the absolute maximum value
specified for I
in Section 12.2.2 on page 221.
INJ(RESET)
Note 2:
2.1 When the LVD is enabled, it is mandatory not to connect a pull-up resistor. A 10nF pull-down capacitor is recommend-
ed to filter noise on the reset line.
2.2. In case a capacitive power supply is used, it is recommended to connect a1MW pull-down resistor to the RESET pin
to discharge any residual voltage induced by this capacitive power supply (this will add 5µA to the power consumption of
the MCU).
2.3. Tips when using the LVD:
– 1. Check that all recommendations related to reset circuit have been applied (see notes above)
– 2. Check that the power supply is properly decoupled (100nF + 10µF close to the MCU). Refer to AN1709. If this
cannot be done, it is recommended to put a 100nF + 1MW pull-down on the RESET pin.
– 3. The capacitors connected on the RESET pin and also the power supply are key to avoiding any start-up margin-
ality. In most cases, steps 1 and 2 above are sufficient for a robust solution. Otherwise: Replace 10nF pull-down on
the RESET pin with a 5µF to 20µF capacitor.
240/263
ST72561
CONTROL PIN CHARACTERISTICS (Cont’d)
Figure 136. RESET R vs V
PU
DD
100
80
60
40
20
0
Ta=-45C Ta=130
Ta=25C
3.5
4
4.5
Vdd
5
5.5
12.10.2 ICCSEL/V Pin
PP
Subject to general operating conditions for V , f
, and T unless otherwise specified.
A
DD OSC
Symbol
Parameter
Conditions
Min
Max
Unit
V
1)
V
Input low level voltage
V
0.2
IL
IH
L
SS
1)
V
I
Input high level voltage
Input leakage current
V
-0.1 12.6
1
DD
V
= V
µA
IN
SS
2)
Figure 137. Two Typical Applications with ICCSEL/V Pin
PP
ICCSEL/V
V
PP
PP
PROGRAMMING
TOOL
10kΩ
ST72XXX
ST72XXX
Notes:
1. Data based on design simulation and/or technology characteristics, not tested in production.
2. When ICC mode is not required by the application ICCSEL/V pin must be tied to V
.
SS
PP
241/263
ST72561
12.11 TIMER PERIPHERAL CHARACTERISTICS
Subject to general operating conditions for V
,
Refer to I/O port characteristics for more details on
the input/output alternate function characteristics
(output compare, input capture, external clock,
PWM output...).
DD
f
, and T unless otherwise specified.
OSC
A
12.11.1 8-Bit PWM-ART Autoreload Timer
Symbol
Parameter
Conditions
Min
1
Typ
Max
Unit
t
CPU
t
PWM resolution time
res(PWM)
f
= 8 MHz
125
ns
CPU
f
ART external clock frequency
PWM repetition rate
EXT
0
f
/2
MHz
CPU
f
PWM
Res
PWM resolution
8
bit
PWM
V
PWM/DAC output step voltage
V
= 5V, Res = 8-bits
= 8 MHz
20
mV
OS
DD
1
128
16
t
CPU
Timer clock period when internal
clock is selected
t
f
COUNTER
CPU
0.125
µs
12.11.2 8-Bit Timer
Symbol
Parameter
Conditions
Min
1
Typ
Max
Unit
t
Input capture pulse time
w(ICAP)in
t
CPU
2
t
PWM resolution time
res(PWM)
f
f
= 8 MHz
250
0
ns
CPU
f
PWM repetition rate
PWM resolution
f
/4
MHz
bit
PWM
CPU
Res
8
PWM
2
8000
1000
t
CPU
t
Timer clock period
= 8 MHz
COUNTER
CPU
0.250
µs
12.11.3 16-Bit Timer
Symbol
Parameter
Conditions
Min
1
Typ
Max
Unit
t
Input capture pulse time
w(ICAP)in
t
CPU
2
t
PWM resolution time
res(PWM)
f
f
= 8 MHz
250
ns
CPU
f
Timer external clock frequency
PWM repetition rate
EXT
0
f
/4
MHz
CPU
f
PWM
Res
PWM resolution
16
8
bit
PWM
2
t
CPU
Timer clock period when internal
clock is selected
t
= 8 MHz
COUNTER
CPU
0.250
1
µs
242/263
ST72561
12.12 COMMUNICATION INTERFACE CHARACTERISTICS
12.12.1 SPI - Serial Peripheral Interface
Refer to I/O port characteristics for more details on
the input/output alternate function characteristics
(SS, SCK, MOSI, MISO).
Subject to general operating conditions for V
,
DD
f
, and T unless otherwise specified.
OSC
A
Symbol
Parameter
Conditions
Master, f = 8 MHz
Min
Max
Unit
f
/ 128 = 0.0625
0
f
f
/ 4 = 2
CPU
CPU
CPU
CPU
f
= 1 / t
MHz
SPI clock frequency
SCK
c(SCK)
Slave, f
= 8 MHz
/ 2 = 4
CPU
t
t
t
t
t
r(SCK)
f(SCK)
su(SS)
SPI clock rise and fall time
See I/O port pin description
1)
4)
(4 x T
) + 50
SS setup time
CPU
Slave
1)
SS hold time
120
h(SS)
1)
1)
Master
Slave
100
90
w(SCKH)
SCK high and low time
t
w(SCKL)
1)
t
Master
Slave
su(MI)
1)
Data input setup time
Data input hold time
t
t
su(SI)
1)
100
0
Master
Slave
h(MI)
ns
1)
t
h(SI)
1)
t
Data output access time
Data output disable time
Data output valid time
Data output hold time
Data output valid time
Data output hold time
120
240
90
a(SO)
Slave
1)
t
t
t
t
t
dis(SO)
1)
v(SO)
Slave (after enable edge)
Master (after enable edge)
1)
0
0
h(SO)
1)
120
v(MO)
1)
h(MO)
Figure 138. SPI Slave Timing Diagram with CPHA = 03)
SS
INPUT
t
t
su(SS)
c(SCK)
t
h(SS)
CPHA = 0
CPOL = 0
CPHA = 0
CPOL = 1
t
t
w(SCKH)
w(SCKL)
t
t
t
t
dis(SO)
a(SO)
v(SO)
h(SO)
t
t
r(SCK)
f(SCK)
See
note 2
MISO
OUTPUT
INPUT
MSB OUT
See note 2
BIT6 OUT
LSB OUT
t
t
h(SI)
su(SI)
LSB IN
MSB IN
BIT1 IN
MOSI
Notes:
1. Data based on design simulation and/or characterization results, not tested in production.
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has
its alternate function capability released. In this case, the pin status depends on the I/O port configuration.
3. Measurement points are done at CMOS levels: 0.3 x V and 0.7 x V
.
DD
DD
4. Depends on f
. For example, if f
= 8 MHz, then T
= 1 / f
= 125ns and t
= 550ns.
su(SS)
CPU
CPU
CPU
CPU
243/263
ST72561
COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d)
Figure 139. SPI Slave Timing Diagram with CPHA = 11)
SS
INPUT
t
t
su(SS)
c(SCK)
t
h(SS)
CPHA = 0
CPOL = 0
CPHA = 0
CPOL = 1
t
t
w(SCKH)
w(SCKL)
t
t
dis(SO)
a(SO)
t
t
h(SO)
v(SO)
t
t
r(SCK)
f(SCK)
See
note 2
See
note 2
MISO
OUTPUT
MSB OUT
BIT6 OUT
Hz
LSB OUT
t
t
h(SI)
su(SI)
MSB IN
LSB IN
BIT1 IN
MOSI
INPUT
Figure 140. SPI Master Timing Diagram1)
SS
INPUT
t
c(SCK)
CPHA = 0
CPOL = 0
CPHA = 0
CPOL = 1
CPHA = 1
CPOL = 0
CPHA = 1
CPOL = 1
t
t
w(SCKH)
w(SCKL)
t
t
r(SCK)
f(SCK)
t
t
h(MI)
su(MI)
MISO
INPUT
MSB IN
h(MO)
BIT6 IN
LSB IN
t
t
v(MO)
MSB OUT
LSB OUT
See note 2
BIT6 OUT
See note 2
MOSI
OUTPUT
Notes:
1. Measurement points are done at CMOS levels: 0.3 x V and 0.7 x V
.
DD
DD
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has
its alternate function capability released. In this case, the pin status depends on the I/O port configuration.
244/263
ST72561
COMMUNICATIONS INTERFACE CHARACTERISTICS (Cont’d)
12.12.2 CAN - Controller Area Network Interface
Subject to general operating condition for V , f
the input/output alternate function characteristics
(CANTX and CANRX).
DD O-
, and T unless otherwise specified.
SC
A
Refer to I/O port characteristics for more details on
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
1)
t
CAN controller propagation time
60
ns
p(RX:TX)
1. Data based on characterization results, not tested in production.
12.13 10-BIT ADC CHARACTERISTICS
Subject to general operating conditions for V , f
, and T unless otherwise specified.
DD CPU
A
1)
1)
Symbol
Parameter
ADC clock frequency
Conditions
Min
Typ
Max
Unit
f
0.4
4
MHz
V
ADC
2)
V
R
C
Conversion voltage range
External input impedance
V
V
DDA
AIN
AIN
AIN
SSA
kΩ
pF
seeFigure
141 and
Figure
External capacitor on analog input
Variation frequency of analog input
signal
f
Hz
142
AIN
Negative input leakage current on ro-
bust analog pins (refer to Table 1 on
page 9)
V
IN < V | I | < 400µA on
SS, IN
I
5
6
µA
lkg
adjacent robust analog pin
C
Internal sample and hold capacitor
6
pF
ADC
f
= 4 MHz
3.5
14
µs
ADC
t
Conversion time
CONV
1/f
ADC
2)
Analog part
Digital part
Sunk on V
Sunk on V
3.6
0.2
DDA
I
mA
ADC
DD
Notes:
1. Data based on characterization results, not tested in production.
2. When V and V pins are not available on the pinout, the ADC refers to V and V
SS
.
DDA
SSA
DD
245/263
ST72561
ADC CHARACTERISTICS (Cont’d)
1)2)
3)
Figure 141. R
Max vs f
with C
= 0pF
Figure 142. Recommended C /R
Values
AIN
ADC
AIN
AIN AIN
45
40
35
30
25
20
15
10
5
1000
100
10
Cain 10 nF
Cain 22 nF
Cain 47 nF
4 MHz
2 MHz
1 MHz
1
0
0.1
0
10
30
70
0.01
0.1
1
10
CPARASITIC (pF)
fAIN(KHz)
Figure 143. Typical Application with ADC
V
DD
ST72XXX
V
T
0.6V
R
2kΩ(max)
AIN
AINx
10-Bit A/D
Conversion
V
AIN
C
V
0.6V
AIN
T
I
C
ADC
6pF
L
1µA
Notes:
1. C
represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad ca-
PARASITIC
pacitance (3pF). A high C
value will downgrade conversion accuracy. To remedy this, f
should be reduced.
PARASITIC
ADC
2. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10kΩ). Data
based on characterization results, not tested in production.
3. This graph shows that depending on the input signal variation (f ), C
can be increased for stabilization time and
ADC
AIN
AIN
reduced to allow the use of a larger serial resistor (R
. It is valid for all f
frequencies ≤ 4 MHz.
AIN)
246/263
ST72561
ADC CHARACTERISTICS (Cont’d)
12.13.0.1 Analog Power Supply and Reference
Pins
– Filter power to the analog power planes. It is rec-
ommended to connect capacitors, with good high
frequency characteristics, between the power
and ground lines, placing 0.1µF and optionally, if
needed 10pF capacitors as close as possible to
the ST7 power supply pins and a 1 to 10µF ca-
pacitor close to the power source (see Figure
144).
Depending on the MCU pin count, the package
may feature separate V
and V
analog pow-
DDA
SSA
er supply pins. These pins supply power to the A/D
converter cell and function as the high and low ref-
erence voltages for the conversion. In smaller
packages V
and V
pins are not available
DDA
SSA
and the analog supply and reference pads are in-
ternally bonded to the V and V pins.
– The analog and digital power supplies should be
connected in a star network. Do not use a resis-
DD
SS
tor, as V
is used as a reference voltage by the
DDA
Separation of the digital and analog power pins al-
low board designers to improve A/D performance.
Conversion accuracy can be impacted by voltage
drops and noise in the event of heavily loaded or
badly decoupled power supply lines (see Section
12.13.0.2 "General PCB Design Guidelines").
A/D converter and any resistance would cause a
voltage drop and a loss of accuracy.
– Properly place components and route the signal
traces on the PCB to shield the analog inputs.
Analog signals paths should run over the analog
ground plane and be as short as possible. Isolate
analog signals from digital signals that may
switch while the analog inputs are being sampled
by the A/D converter. Do not toggle digital out-
puts on the same I/O port as the A/D input being
converted.
12.13.0.2 General PCB Design Guidelines
To obtain best results, some general design and
layout rules should be followed when designing
the application PCB to shield the noise-sensitive,
analog physical interface from noise-generating
CMOS logic signals.
12.13.0.3 Software Filtering of Spurious
Conversion Results
– Use separate digital and analog planes. The an-
alog ground plane should be connected to the
digital ground plane via a single point on the
PCB.
For EMC performance reasons, it is recommend-
ed to filter A/D conversion outliers using software
filtering techniques.
Figure 144. Power Supply Filtering
ST72XXX
1 to 10µF
0.1µF
V
V
SS
ST7
DIGITAL NOISE
FILTERING
DD
V
DD
POWER
SUPPLY
SOURCE
V
V
0.1µF
DDA
EXTERNAL
NOISE
FILTERING
SSA
247/263
ST72561
ADC CHARACTERISTICS (Cont’d)
ADC Accuracy with f
Symbol
= 8 MHz, f
= 4 MHz R
< 10kΩ, V
= 5V
CPU
ADC
AIN
DD
Conditions
Parameter
Typ
4
Max
Unit
1)
|E |
Total unadjusted error
Note 2
T
1)
|E |
Offset error
2.5
3
O
4
2
1)
|E |
Gain Error
LSB
G
1)
|E |
Differential linearity error
D
1.5
1)
|E |
Integral linearity error
L
Figure 145. ADC Accuracy Characteristics
Digital Result ADCDR
E
G
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line
1023
V
– V
1022
1021
DDA
SSA
1LSB
= ----------------------------------------
IDEAL
1024
(2)
E =Total Unadjusted Error: maximum deviation
T
E
between the actual and the ideal transfer curves.
T
(3)
7
6
5
4
3
2
1
E =Offset Error: deviation between the first actual
O
transition and the first ideal one.
(1)
E =Gain Error: deviation between the last ideal
G
transition and the last actual one.
E
E
O
L
E =Differential Linearity Error: maximum deviation
D
between actual steps and the ideal one.
E =Integral Linearity Error: maximum deviation
L
E
between any actual transition and the end point
correlation line.
D
1 LSB
IDEAL
V
(LSB
)
in
IDEAL
0
1
2
3
4
5
6
7
1021 1022 1023 1024
V
V
DDA
SSA
Notes:
1. Data based on characterization results, not tested in production. ADC Accuracy vs. Negative Injection Current: Inject-
ing negative current on any of the standard (non-robust) analog input pins should be avoided as this significantly reduces
the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin
to ground) to standard analog pins which may potentially inject negative current. The effect of negative injection current
on robust pins is specified in Section 12.9.
Any positive injection current within the limits specified for I
accuracy.
and ΣI
in Section 12.9 does not affect the ADC
INJ(PIN)
INJ(PIN)
2. Under characterization.
248/263
ST72561
13 PACKAGE CHARACTERISTICS
13.1 PACKAGE MECHANICAL DATA
Figure 146. 32-Pin Low Profile Quad Flat Package (7x7)
1)
mm
inches
Dim.
D
D1
Min Typ Max Min Typ Max
A
A2
A
1.60
0.063
0.006
A1 0.05
0.15 0.002
A1
A2 1.35 1.40 1.45 0.053 0.055 0.057
b
C
0.30 0.37 0.45 0.012 0.015 0.018
0.09 0.20 0.004 0.008
e
D
9.00
7.00
9.00
7.00
0.80
3.5°
0.354
0.276
0.354
0.276
0.031
3.5°
E1
E
D1
E
b
E1
e
c
L1
θ
0°
7°
0°
7°
L
L
0.45 0.60 0.75 0.018 0.024 0.030
1.00 0.039
Number of Pins
32
h
L1
N
Note 1. Values in inches are converted from
mm and rounded to 3 decimal digits.
Figure 147. 44-Pin Low Profile Quad Flat Package (10x10)
1)
mm
inches
Dim.
A
D
Min Typ Max Min Typ Max
D1
A2
A
1.60
0.063
0.006
A1 0.05
0.15 0.002
A1
b
A2 1.35 1.40 1.45 0.053 0.055 0.057
b
C
0.30 0.37 0.45 0.012 0.015 0.018
0.09
0.20 0.004 0.000 0.008
D
12.00
10.00
12.00
10.00
0.80
0.472
0.394
0.472
0.394
0.031
D1
E
e
E1
E
E1
e
θ
0°
3.5°
7°
0°
3.5°
7°
L
0.45 0.60 0.75 0.018 0.024 0.030
1.00 0.039
Number of Pins
44
c
L1
L1
L
h
N
Note 1. Values in inches are converted from
mm and rounded to 3 decimal digits.
249/263
ST72561
Figure 148. 64-Pin Low Profile Quad Flat Package (10 x10)
mm
inches
Dim.
Min Typ Max Min Typ Max
D
A
A
1.60
0.063
0.006
D1
A2
A1 0.05
0.15 0.002
A1
A2 1.35 1.40 1.45 0.053 0.055 0.057
b
c
0.17 0.22 0.27 0.007 0.009 0.011
0.09 0.20 0.004 0.008
b
e
D
12.00
10.00
12.00
10.00
0.50
0.472
0.394
0.472
0.394
0.020
3.5°
E1
D1
E
E
E1
e
θ
0°
3.5°
7°
0°
7°
c
L1
L
0.45 0.60 0.75 0.018 0.024 0.030
1.00 0.039
Number of Pins
64
θ
L1
L
N
13.2 THERMAL CHARACTERISTICS
Symbol
Ratings
Value
Unit
Package thermal resistance (junction to ambient)
LQFP64
60
52
70
R
°C/W
thJA
LQFP44
LQFP32
1)
P
Power dissipation
Maximum junction temperature
500
150
mW
°C
D
2)
T
Jmax
Notes:
1. The maximum power dissipation is obtained from the formula P = (T - T ) / R
. The power dissipation of an appli-
D
J
A
thJA
cation can be defined by the user with the formula: P = P
+ P
where P
is the chip internal power (I x V
)
DD
D
INT
PORT
INT
DD
and P
is the port power dissipation depending on the ports used in the application.
PORT
2. The maximum chip-junction temperature is based on technology characteristics.
13.3 SOLDERING AND GLUEABILITY INFORMATION
In order to meet environmental requirements, ST
box label, in compliance with JEDEC Standard
JESD97. The maximum ratings related to solder-
ing conditions are also marked on the inner box la-
TM
offers these devices in ECOPACK
packages.
These packages have a lead-free second level in-
terconnect. The category of second level intercon-
nect is marked on the package and on the inner
TM
bel. ECOPACK is an ST trademark. ECOPACK
specifications are available at www.st.com.
250/263
ST72561
14 DEVICE CONFIGURATION AND ORDERING INFORMATION
Each device is available for production in user pro-
grammable versions (FLASH) as well as in factory
coded versions (ROM/FASTROM).
active.
0: No Reset generation when entering Halt mode
1: Reset generation when entering Halt mode
ST72561 devices are ROM versions. ST72P561
devices are Factory Advanced Service Technique
ROM (FASTROM) versions: They are factory-pro-
grammed HDFlash devices.
OPT6 = WDGSW Hardware or software watchdog
This option bit selects the watchdog type.
0: Hardware (watchdog always enabled)
1: Software (watchdog to be enabled by software)
ST72F561 FLASH devices are shipped to custom-
ers with a default content (FFh), while ROM facto-
ry coded parts contain the code supplied by the
customer. This implies that FLASH devices have
to be configured by the customer using the Option
Bytes while the ROM devices are factory-config-
ured.
OPT5 = Reserved, must be kept at default value.
OPT4 = LVD Voltage detection
This option bit enables the voltage detection block
(LVD).
Selected Low Voltage Detector
VD
14.1 FLASH OPTION BYTES
LVD Off
LVD On
1
0
The option bytes allows the hardware configura-
tion of the microcontroller to be selected. They
have no address in the memory map and can be
accessed only in programming mode (for example
using a standard ST7 programming tool). The de-
fault content of the FLASH is fixed to FFh. To pro-
gram directly the FLASH devices using ICP,
FLASH devices are shipped to customers with a
reserved internal clock source enabled. In masked
ROM devices, the option bytes are fixed in hard-
ware by the ROM code (see option list).
OPT3 = PLL OFF PLL activation
This option bit activates the PLL which allows mul-
tiplication by two of the main input clock frequency.
The PLL is guaranteed only with an input frequen-
cy between 2 and 4 MHz.
0: PLL x2 enabled
1: PLL x2 disabled
Caution: The PLL can be enabled only if the “OSC
RANGE” (OPT11:10) bits are configured to “MP -
2~4 MHz”. Otherwise, the device functionality is
not guaranteed.
OPTION BYTE 0
OPT7 = WDGHALT Watchdog reset on HALT
This option bit determines if a RESET is generated
when entering HALT mode while the Watchdog is
STATIC OPTION BYTE 0
STATIC OPTION BYTE 1
7
0
7
0
WDG
PKG
AFI_MAP
OSCTYPE OSCRANGE
LVD
1
1
1
0
1
1
1
0
1
1
1
0
0
1
1
0
1
De-
fault(*)
1
1
1
1
1
1
1
(*): Option bit values programmed by ST
251/263
ST72561
FLASH OPTION BYTES (Cont’d)
OPT2:1 = PKG[1:0] Package selection
AFI Mapping 0
AFI_MAP(0)
These option bits select the device package.
T16_ICAP2 is mapped on PD1
T16_ICAP2 is mapped on PC1
0
1
PKG
Selected Package
1
0
x
1
0
LQFP 64
LQFP 44
LQFP 32
1
0
0
OPT5:4 = OSCTYPE[1:0] Oscillator Type
These option bits select the ST7 main clock
source type.
OSCTYPE
Note: Pads that are not bonded to external pins
are in input pull-up configuration when the pack-
age selection option bits have been properly pro-
grammed. The configuration of these pads must
be kept in reset state to avoid added current con-
sumption.
Clock Source
1
0
0
0
0
1
Resonator Oscillator
Reserved
Reserved internal clock source
(used only in ICC mode)
1
1
0
1
OPT0 = FMP_R Flash memory read-out protec-
tion
External Source
Read-out protection, when selected provides a
protection against program memory content ex-
traction and against write access to Flash memo-
ry. Erasing the option bytes when the FMP_R op-
tion is selected causes the whole user memory to
be erased first, and the device can be repro-
grammed. Refer to Section 4.3.1 and the ST7
Flash Programming Reference Manual for more
details.
OPT3:2 = OSCRANGE[1:0] Oscillator range
If the resonator oscillator type is selected, these
option bits select the resonator oscillator. This se-
lection corresponds to the frequency range of the
resonator used. If external source is selected with
the OSCTYPE option, then the OSCRANGE op-
tion must be selected with the corresponding
range.
0: Read-out protection enabled
OSCRANGE
1: Read-out protection disabled
Typ. Freq. Range
1
0
0
1
1
0
0
1
0
1
OPTION BYTE 1
LP
1~2 MHz
2~4 MHz
4~8 MHz
8~16 MHz
OPT7:6 = AFI_MAP[1:0] AFI Mapping
These option bits allow the mapping of some of the
Alternate Functions to be changed.
MP
MS
HS
AFI Mapping 1
AFI_MAP(1)
T16_OCMP1 on PD3
T16_OCMP2 on PD5
T16_ICAP1 on PD4
LINSCI2_SCK not available
LINSCI2_TDO not available
LINSCI2_RDI not available
OPT1 = Reserved
OPT0 = RSTC RESET clock cycle selection
This option bit selects the number of CPU cycles
inserted during the RESET phase and when exit-
ing HALT mode. For resonator oscillators, it is ad-
vised to select 4096 due to the long crystal stabili-
zation time.
0
T16_OCMP1 on PB6
T16_OCMP2 on PB7
T16_ICAP1 on PC0
LINSCI2_SCK on PD3
LINSCI2_TDO on PD5
LINSCI2_RDI on PD4
1
0: Reset phase with 4096 CPU cycles
1: Reset phase with 256 CPU cycles
252/263
ST72561
DEVICE CONFIGURATION AND ORDER INFORMATION (cont’d)
14.2 TRANSFER OF CUSTOMER CODE
Refer to application note AN1635 for information
on the counter listing returned by ST after code
has been transferred.
Customer code is made up of the ROM/FAS-
TROM contents and the list of the selected options
(if any). The ROM/FASTROM contents are to be
sent on diskette, or by electronic means, with the
S19 hexadecimal file generated by the develop-
ment tool. All unused bytes must be set to FFh.
The STMicroelectronics Sales Organization will be
pleased to provide detailed information on con-
tractual points.
The selected options are communicated to
STMicroelectronics using the correctly completed
OPTION LIST appended.
Figure 149. ROM Factory Coded Device Types
/
XXX
PACKAGE VERSION
DEVICE
Code name (defined by STMicroelectronics)
6 = Standard -40 to +85 °C
3 = Standard -40 to +125 °C
T= Low Profile Quad Flat Pack
ST72561AR9, ST72561AR7, ST72561AR6, ST72561AR4
ST72561J9, ST72561J7, ST72561J6, ST72561J4
ST72561K9,ST72561K7, ST72561K6, ST72561K4
253/263
ST72561
TRANSFER OF CUSTOMER CODE (cont’d)
Figure 150. FASTROM Factory Coded Device Types
/
XXX
PACKAGE VERSION
DEVICE
Code name (defined by STMicroelectronics)
6 = -40 to +85 °C
3 = -40 to +125 °C
T= Low Profile Quad Flat Pack
ST72P561AR9, ST72P561AR7, ST72P561AR6, ST72P561AR4
ST72P561J9,ST72P561J7, ST72P561J6, ST72P561J4
ST72P561K9,ST72P561K7 ST72P561K6,ST72P561K4
Figure 151. FLASH Device Types
PACKAGE VERSION
DEVICE
6 = -40 to +85 °C
3 = -40 to +125 °C
T= Low Profile Quad Flat Pack
ST72F561AR9, ST72F561AR7, ST72F561AR6
ST72F561J9, ST72F561J7,ST72F561J64
ST72F561K9, ST72F561K7, ST72F561K6
254/263
ST72561
TRANSFER OF CUSTOMER CODE (Cont’d)
ST72561 MICROCONTROLLER OPTION LIST
(Last update: September 2006)
Customer
Address
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact
Phone No
Reference/ROM Code* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
*The ROM/FASTROM code name is assigned by STMicroelectronics.
ROM/FASTROM code must be sent in .S19 format. .Hex extension cannot be processed.
Device Type/Memory Size/Package (check only one option)
----------------------- -------------------------
------------------------- ------------------------ ------------------------
|
|
|
|
|
|
|
|
|
ROM:
Package
60K
48K
32K
16K
|
|
|
------------------------- ------------------------ ------------------------
----------------------- -------------------------
| LQFP64 10x10: | [ ] ST72561AR9 | [ ] ST72561AR7 | [ ] ST72561AR6 | [ ] ST72561AR4
|
|
|
| LQFP44:
| LQFP32:
| [ ] ST72561J9
| [ ] ST72561K9
| [ ] ST72561J7
| [ ] ST72561K7
| [ ] ST72561J6
| [ ] ST72561K6
| [ ] ST72561J4
| [ ] ST72561K4
----------------------- ------------------------- -------------------------
------------------------ ------------------------
|
|
|
|
|
|
|
|
|
|
|
FASTROM:
Conditioning:
Package
60K
48K
32K
16K
|
------------------------ ------------------------
----------------------- ------------------------- -------------------------
| LQFP64 10x10: | [ ] ST72P561AR9 | [ ] ST72P561AR7 | [ ] ST72P561AR6 | [ ] ST72P561AR4 |
| LQFP44:
| LQFP32:
| [ ] ST72P561J9
| [ ] ST72P561J7 | [ ] ST72P561J6 | [ ] ST72P561J4
|
|
| [ ] ST72P561K9 | [ ] ST72P561K7 | [ ] ST72P561K6 | [ ] ST72P561K4
[ ] Tray
[ ] No
[ ] Tape & Reel
[ ] Yes "_ _ _ _ _ _ _ _ _ _ " (10 char. max)
Special Marking:
Authorized characters are letters, digits, '.', '-', '/' and spaces only.
Temp. Range. Please refer to datasheet for specific sales conditions:
---------------------------------------
|
-
Temp. Range
---------------------------------------
[ ]
[ ]
|
|
-40°C to +85°C
-40°C to +125°C
Clock Source Selection:
[ ] Resonator:
[ ] External Source
Oscillator/External source range:
[ ] LP: Low power (1 to 2 MHz)
[ ] MP: Medium power (2 to 4 MHz)
[ ] MS: Medium speed (4 to 8 MHz)
[ ] HS: High speed (8 to 16 MHz)
[ ] Disabled
LVD
[ ] Enabled
PLL1
[ ] Disabled
[ ] Enabled
[ ] Hardware Activation
Watchdog Selection
[ ] Software Activation
Watchdog Reset on Halt
[ ] Reset
[ ] No Reset
Read-out Protection
Reset Delay
[ ] Disabled
[ ] Enabled
[ ] 256 Cycles
[ ] 4096 Cycles
LINSCI2 Mapping
T16_ICAP2 Mapping
[ ] Not available (AFIMAP[1] = 0)
[ ] On PD1 (AFIMAP[0] = 0)
[ ] Mapped (AFIMAP[1] = 1)
[ ] On PC1 (AFIMAP[0] = 1)
Comments:
Supply Operating Range in the application: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Notes
Signature
Date
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1 If PLL is enabled, medium power (2 to 4 MHz range) has to be selected (MP)
Please download the latest version of this option list from:
http://www.st.com/mcu > downloads > ST7 microcontrollers > Option list
255/263
ST72561
15 DEVELOPMENT TOOLS
Full details of tools available for the ST7 from third
party manufacturers can be obtained from the
STMicroelectronics Internet site:
For footprint and other mechanical information
about these sockets and adapters, refer to the
manufacturer’s datasheet.
➟ www.st.com/mcu
ST Programming Tools
Tools from iSystem and Hitex include C compliers,
emulators and gang programmers.
■ ST7MDT25-EPB: For in-socket or ICC
programming
Note: Before designing the board layout, it is rec-
ommended to check the overall dimensions of the
socket as they may be greater than the dimen-
sions of the device.
■ ST7-STICK: For ICC programming
256/263
ST72561
16 IMPORTANT NOTES
16.1 ALL DEVICES
SIM
reset flag or interrupt mask
POP CC
16.1.1 RESET Pin Protection with LVD Enabled
As mentioned in note 2 below Figure 134 on page
240, when the LVD is enabled, it is recommended
not to connect a pull-up resistor or capacitor. A
10nF pull-down capacitor is required to filter noise
on the reset line.
16.1.3 External Interrupt Missed
To avoid any risk of generating a parasitic inter-
rupt, the edge detector is automatically disabled
for one clock cycle during an access to either DDR
and OR. Any input signal edge during this period
will not be detected and will not generate an inter-
rupt.
16.1.2 Clearing Active Interrupts Outside
Interrupt Routine
When an active interrupt request occurs at the
same time as the related flag or interrupt mask is
being cleared, the CC register may be corrupted.
This case can typically occur if the application re-
freshes the port configuration registers at intervals
during runtime.
Concurrent interrupt context
Workaround
The symptom does not occur when the interrupts
are handled normally, that is, when:
The workaround is based on software checking
the level on the interrupt pin before and after writ-
ing to the PxOR or PxDDR registers. If there is a
level change (depending on the sensitivity pro-
grammed for this pin) the interrupt routine is in-
voked using the call instruction with three extra
PUSH instructions before executing the interrupt
routine (this is to make the call compatible with the
IRET instruction at the end of the interrupt service
routine).
– The interrupt request is cleared (flag reset or in-
terrupt mask) within its own interrupt routine
– The interrupt request is cleared (flag reset or in-
terrupt mask) within any interrupt routine
– The interrupt request is cleared (flag reset or in-
terrupt mask) in any part of the code while this in-
terrupt is disabled
If these conditions are not met, the symptom can
be avoided by implementing the following se-
quence:
But detection of the level change does ensure that
edge occurs during the critical 1 cycle duration and
the interrupt has been missed. This may lead to
occurrence of same interrupt twice (one hardware
and another with software call).
Perform SIM and RIM operation before and after
resetting an active interrupt request
Example:
To avoid this, a semaphore is set to '1' before
checking the level change. The semaphore is
changed to level '0' inside the interrupt routine.
When a level change is detected, the semaphore
status is checked and if it is '1' this means that the
last interrupt has been missed. In this case, the in-
terrupt routine is invoked with the call instruction.
SIM
reset flag or interrupt mask
RIM
Nested interrupt context
The symptom does not occur when the interrupts
are handled normally, that is, when:
– The interrupt request is cleared (flag reset or in-
terrupt mask) within its own interrupt routine
There is another possible case, that is, if writing to
PxOR or PxDDR is done with global interrupts dis-
abled (interrupt mask bit set). In this case, the
semaphore is changed to '1' when the level
change is detected. Detecting a missed interrupt is
done after the global interrupts are enabled (inter-
rupt mask bit reset) and by checking the status of
the semaphore. If it is '1' this means that the last
interrupt was missed and the interrupt routine is in-
voked with the call instruction.
– The interrupt request is cleared (flag reset or in-
terrupt mask) within any interrupt routine with
higher or identical priority level
– The interrupt request is cleared (flag reset or in-
terrupt mask) in any part of the code while this in-
terrupt is disabled
If these conditions are not met, the symptom can
be avoided by implementing the following se-
quence:
To implement the workaround, the following soft-
ware sequence is to be followed for writing into the
PxOR/PxDDR registers. The example is for Port
PF1 with falling edge interrupt sensitivity. The
PUSH CC
257/263
ST72561
IMPORTANT NOTES (Cont’d)
software sequence is given for both cases (global
interrupt disabled/enabled).
LD X,A ; store the level before writing to
PxOR/PxDDR
Case 1: Writing to PxOR or PxDDR with Global In-
LD A,#$90
terrupts Enabled:
LD PFDDR,A; Write into PFDDR
LD A,#$ff
LD A,#01
LD sema,A
LD A,PFDR
AND A,#02
; set the semaphore to '1'
LD PFOR,A
LD A,PFDR
AND A,#$02
; Write to PFOR
LD X,A
PxOR/PxDDR
; store the level before writing to
LD Y,A
PxDDR
; store the level after writing to PxOR/
; check for falling edge
LD A,#$90
LD A,X
LD PFDDR,A ; Write to PFDDR
LD A,#$ff
cp A,#$02
jrne OUT
TNZ Y
LD PFOR,A ; Write to PFOR
LD A,PFDR
jrne OUT
LD A,#$01
AND A,#02
LD Y,A
PxOR/PxDDR
; store the level after writing to
LD sema,A ; set the semaphore to '1' if edge is
detected
LD A,X
; check for falling edge
RIM
; reset the interrupt mask
cp A,#02
jrne OUT
TNZ Y
LD A,sema ; check the semaphore status
CP A,#$01
jrne OUT
jrne OUT
LD A,sema
call call_routine; call the interrupt routine
RIM
; check the semaphore status if
edge is detected
OUT:
RIM
CP A,#01
JP while_loop
.call_routine ; entry to call_routine
PUSH A
jrne OUT
call call_routine; call the interrupt routine
OUT:LD A,#00
PUSH X
LD sema,A
PUSH CC
.call_routine ; entry to call_routine
.ext1_rt
; entry to interrupt routine
PUSH A
PUSH X
PUSH CC
LD A,#$00
LD sema,A
IRET
.ext1_rt
; entry to interrupt routine
16.1.4 Unexpected Reset Fetch
LD A,#00
LD sema,A
IRET
If an interrupt request occurs while a "POP CC" in-
struction is executed, the interrupt controller does
not recognise the source of the interrupt and, by
default, passes the RESET vector address to the
CPU.
Case 2: Writing to PxOR or PxDDR with Global In-
terrupts Disabled:
Workaround
SIM
; set the interrupt mask
To solve this issue, a "POP CC" instruction must
always be preceded by a "SIM" instruction.
LD A,PFDR
AND A,#$02
258/263
ST72561
IMPORTANT NOTES (Cont’d)
16.1.5 Header Time-out Does Not Prevent
Wake-up from Mute Mode
reading the SCIDR register in the LINSCI interrupt
routine), the LINSCI will generate another LINSCI
interrupt (due to the RDRF flag setting).
Normally, when LINSCI is configured in LIN slave
mode, if a header time-out occurs during a LIN
header reception (that is, header length > 57 bits),
the LIN Header Error bit (LHE) is set, an interrupt
occurs to inform the application but the LINSCI
should stay in mute mode, waiting for the next
header reception.
Impact on application
Software may execute the interrupt routine twice
after header reception.
Moreover, in reception mode, as the receiver is no
longer in mute mode, an interrupt will be generat-
ed on each data byte reception.
Problem Description
Workaround
The LINSCI sampling period is Tbit / 16. If a LIN
Header time-out occurs between the 9th and the
15th sample of the Identifier Field Stop Bit (refer to
Figure 152), the LINSCI wakes up from mute
mode. Nevertheless, LHE is set and LIN Header
Detection Flag (LHDF) is kept cleared.
The problem can be detected in the LINSCI inter-
rupt routine. In case of timeout error (LHE is set
and LHLR is loaded with 00h), the software can
check the RWU bit in the SCICR2 register. If RWU
is cleared, it can be set by software. Refer to Fig-
ure 153 on page 260. Workaround is shown in
bold characters.
In addition, if LHE is reset by software before this
15th sample (by accessing the SCISR register and
Figure 152. Header Reception Event Sequence
LIN Synch
Break
LIN Synch
Field
Identifier
Field
T
HEADER
ID field STOP bit
Critical
Window
Active mode is set
(RWU is cleared)
RDRF flag is set
259/263
ST72561
IMPORTANT NOTES (Cont’d)
Figure 153.LINSCI Interrupt Routine
@interrupt void LINSCI_IT ( void ) /* LINSCI interrupt routine */
{
/* clear flags */
SCISR_buffer = SCISR;
SCIDR_buffer = SCIDR;
if ( SCISR_buffer & LHE )/* header error ? */
{
if (!LHLR)/* header time-out? */
{
if ( !(SCICR2 & RWU) )/* active mode ? */
{
_asm("sim");/* disable interrupts */
SCISR;
SCIDR;/* Clear RDRF flag */
SCICR2 |= RWU;/* set mute mode */
SCISR;
SCIDR;/* Clear RDRF flag */
SCICR2 |= RWU;/* set mute mode */
_asm("rim");/* enable interrupts */
}
}
}
}
Example using Cosmic compiler syntax
16.1.6 CAN FIFO Corruption
SCIBRR = 0xC9), the wrong break duration occur-
rence is around 1%.
The beCAN FIFO gets corrupted when a message
is received and simultaneously a message is re-
leased while FMP = 2. For details and a descrip-
tion of the workaround refer to Section 10.9.7.1 on
page 188.
Workaround
If this wrong duration is not compliant with the
communication protocol in the application, soft-
ware can request that an Idle line be generated
before the break character. In this case, the break
duration is always correct assuming the applica-
tion is not doing anything between the idle and the
break. This can be ensured by temporarily disa-
bling interrupts.
16.2 FLASH/FASTROM DEVICES ONLY
16.2.1 LINSCI Wrong Break Duration
SCI mode
The exact sequence is:
- Disable interrupts
A single break character is sent by setting and re-
setting the SBK bit in the SCICR2 register. In
some cases, the break character may have a long-
er duration than expected:
- Reset and Set TE (IDLE request)
- Set and Reset SBK (Break Request)
- Re-enable interrupts
- 20 bits instead of 10 bits if M = 0
- 22 bits instead of 11 bits if M = 1
LIN mode
In the same way, as long as the SBK bit is set,
break characters are sent to the TDO pin. This
may lead to generate one break more than expect-
ed.
If the LINE bit in the SCICR3 is set and the M bit in
the SCICR1 register is reset, the LINSCI is in LIN
master mode. A single break character is sent by
setting and resetting the SBK bit in the SCICR2
register. In some cases, the break character may
have a longer duration than expected:
Occurrence
The occurrence of the problem is random and pro-
portional to the baud rate. With a transmit frequen-
- 24 bits instead of 13 bits
cy of 19200 baud (f
= 8 MHz and
CPU
260/263
ST72561
IMPORTANT NOTES (Cont’d)
Occurrence
The workaround is the same as for SCI mode but
considering the low probability of occurrence (1%),
it may be better to keep the break generation se-
quence as it is.
The occurrence of the problem is random and pro-
portional to the baud rate. With a transmit frequen-
cy of 19200 baud (f
SCIBRR = 0xC9), the wrong break duration occur-
rence is around 1%.
= 8 MHz and
CPU
16.2.2 16-bit and 8-bit Timer PWM Mode
In PWM mode, the first PWM pulse is missed after
writing the value FFFCh in the OC1R or OC2R
register.
Analysis
The LIN protocol specifies a minimum of 13 bits for
the break duration, but there is no maximum value.
Nevertheless, the maximum length of the header
is specified as (14+10+10+1) x 1.4 = 49 bits. This
is composed of:
16.3 ROM DEVICES ONLY
16.3.1 16-bit Timer PWM Mode Buffering
Feature Change
- the synch break field (14 bits)
- the synch field (10 bits)
In all devices, the frequency and period of the
PWM signal are controlled by comparing the coun-
ter with a 16-bit buffer updated by the OCiHR and
OCiLR registers. In ROM devices, contrary to the
description in Section 10.5.3.5 on page 104, the
output compare function is not inhibited after a
write instruction to the OCiHR register. Instead the
buffer update at the end of the PWM period is in-
hibited until OCiLR is written. This improved buffer
handling is fully compatible with applications writ-
ten for Flash devices.
- the identifier field (10 bits)
Every LIN frame starts with a break character.
Adding an idle character increases the length of
each header by 10 bits. When the problem occurs,
the header length is increased by 11 bits and be-
comes ((14+11)+10+10+1) = 45 bits.
To conclude, the problem is not always critical for
LIN communication if the software keeps the time
between the sync field and the ID smaller than 4
bits, that is, 208µs at 19200 baud.
261/263
ST72561
17 REVISION HISTORY
Date
Revision
Main changes
Added standard version 16K ROM/Flash devices
Modified data retention in Section 12.7
Added “6” and “3” standard version device type coding to Figure 151 and Figure 149 on page
253
24-Oct-2005
4
Modified power consumption Section 12.4
Added CDM in Section 12.8.3.1
Added “External interrupt missed” Section 16.1.3
Replaced TQFP with LQFP packages throughout document
Changed device summary on page 1
Changed Section 9.2.1 on page 47
Changed title of Section 9.6 on page 51 from “I/O Port Implementation” to “I/O Port Register
Configurations”
Changed Section 10.6.3.3 on page 115
Corrected name of bit 5 in SPICSR register in Table 21 on page 122
Changed Section 12.5.4 on page 229
Added links to Table 38 and Table 39 in Section 12.8.3 on page 233
Removed EMC protection circuitry in Figure 135 on page 240 (device works correctly with-
out these components)
26-Sep-2006
5
Changed Section 12.12.1 on page 243
Changed title of Figure 146 on page 248
Changed title of Figure 146 on page 249
Changed title of Figure 147 on page 249
Changed notes in Section 13.2 on page 250
Changed AFI mapping for “OPTION BYTE 1” on page 252
Changed Figure 149 on page 253, Figure 150 on page 254 and Figure 151 on page 254
Changed “ST72561 MICROCONTROLLER OPTION LIST” on page 255
Deleted Section 15.1.5 “Clearing active interrupts outside interrupt routine” (text already ex-
ists in Section 16.1.2 on page 257)
Added Section 16.1.5 on page 259
Removed automotive part numbers, see separate ST72561-auto datasheet
262/263
ST72561
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
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All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
liability whatsoever relating to the choice, selection or use of the ST products and services described herein.
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WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS
OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT
RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE
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Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
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© 2006 STMicroelectronics - All rights reserved
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263/263
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