ST72631K1B0_技术文档

ST7263

LOW SPEED USB 8-BIT MCU FAMILY with up to 16K MEMORY,

2

up to 512 BYTES RAM, 8-BIT ADC, WDG, TIMER, SCI & I C

DATASHEET

■ Up to 16Kbytes program memory

■ Data RAM: up to 512 bytes with 64 bytes stack

■ Run, Wait and Halt CPU modes

■ 12 or 24 MHz oscillator

■ RAM retention mode

■ USB (Universal Serial Bus) Interface with DMA

for low speed applications compliant with USB

1.5 Mbs specification (version 1.1) and USB

HID specifications (version 1.0)

PSDIP32

■ Integrated 3.3V voltage regulator and

transceivers

■ Suspend and Resume operations

CSDIP32W

■ 3

endpoints with programmable in/out

configuration

■ 19 programmable I/O lines with:

– 8 high current I/Os (10mA at 1.3V)

– 2 very high current pure Open Drain I/Os

(25mA at 1.5V)

– 8 lines individually programmable as interrupt

inputs

SO34 (Shrink)

■ 8-bit A/D Converter (ADC) with 8 channels

■ Fully static operation

■ Optional Low Voltage Detector (LVD)

■ Programmable Watchdog for system reliability

■ 63 basic instructions

■ 16-bit Timer with:

■ 17 main addressing modes

■ 8x8 unsigned multiply instruction

■ True bit manipulation

■ Versatile Development Tools (under Windows)

including assembler, linker, C-compiler,

archiver, source level debugger, software

library, hardware emulator, programming

boards and gang programmers

– 2 Input Captures

– 2 Output Compares

– PWM Generation capabilities

– External Clock input

■ Asynchronous Serial Communications Interface

(8K and 16K program memory versions only)

2

■ I C Multi Master Interface up to 400 KHz

(16K program memory version only)

Table 1. Device Summary

ST72631

16K

Features

ST72632

ST72633

ROM - OTP (bytes)

RAM (stack) - bytes

8K

4K

512 (64)

256 (64)

2

Watchdog, 16-bit timer, SCI, I C, ADC, Watchdog, 16-bit timer,

USB SCI, ADC, USB

Watchdog, 16-bit timer,

ADC, USB

Peripherals

Operating Supply

CPU frequency

4.0V to 5.5V

8 Mhz (with 24 MHz oscillator) or 4 MHz (with 12 MHz oscillator)

Operating temperature

0°C to +70°C

Packages

SO34/SDIP32

1

EPROM device

ST72E631 (CSDIP32W)

Note 1: EPROM version for development only

Rev. 1.8

August 2000

1/109

1

Table of Contents

1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.3 EXTERNAL CONNECTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.4 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.5 EPROM/OTP PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

1.5.1 EPROM ERASURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3 CLOCKS AND RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.1 CLOCK SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.1.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.1.2 External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.2 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.2.1 Low Voltage Detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.2.2 Watchdog Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.2.3 External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4 INTERRUPTS AND POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.1 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.1.1 Interrupt Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.2 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.2.2 HALT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.2.3 WAIT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.1 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.1.2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.1.3 I/O Port Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.1.4 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.1.5 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.1.6 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.1.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.2 MISCELLANEOUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5.3 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.3.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

5.3.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

5.3.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

5.4 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

109

5.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

5.4.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

2/109

Table of Contents

5.4.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

5.4.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

5.4.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

5.4.6 Summary of Timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

5.4.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

5.5 SERIAL COMMUNICATIONS INTERFACE (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

5.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

5.5.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

5.5.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

5.5.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

5.5.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

5.5.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

5.5.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

5.6 USB INTERFACE (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

5.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

5.6.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

5.6.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

5.6.4 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

5.6.5 Programming Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

5.7 I²C BUS INTERFACE (I²C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

5.7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

5.7.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

5.7.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

5.7.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

5.7.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

5.7.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

5.7.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

5.8 8-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

5.8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

5.8.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

5.8.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

5.8.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

5.8.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

5.8.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

6 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . 87

6.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

6.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

6.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

6.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

6.1.4 Indexed (No Offset, Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

6.1.5 Indirect (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

6.1.6 Indirect Indexed (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

6.1.7 Relative Mode (Direct, Indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

6.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

7 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

7.1 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

7.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

3/109

ST7263

7.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

7.4 POWER CONSUMPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

7.5 I/O PORT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

7.6 LOW VOLTAGE DETECTOR (LVD) CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 98

7.7 CONTROL TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

7.8 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . 99

7.8.1 USB - Universal Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

7.8.2 I2C - Inter IC Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

7.9 8-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

8 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

8.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

9 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . 106

9.1 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . . 106

9.2 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

9.3 TO GET MORE INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

10 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

4/109

ST7263

1 GENERAL DESCRIPTION

1.1 INTRODUCTION

The ST7263 Microcontrollers form a sub family of

the ST7 dedicated to USB applications. The de-

vices are based on an industry-standard 8-bit core

and feature an enhanced instruction set. They op-

erate at a 24MHz or 12 MHz oscillator frequency.

Under software control, the ST7263 MCUs may be

placed in either Wait or Halt modes, thus reducing

power consumption. The enhanced instruction set

and addressing modes afford real programming

potential. In addition to standard 8-bit data man-

agement, the ST7263 MCUs feature true bit ma-

nipulation, 8x8 unsigned multiplication and indirect

addressing modes. The devices include an ST7

Core, up to 16K program memory, up to 512 bytes

RAM, 19 I/O lines and the following on-chip pe-

ripherals:

– industry standard asynchronous SCI serial inter-

face (not on all products - see device summary

below)

– digital Watchdog

– 16-bit Timer featuring an External clock input, 2

Input Captures, 2 Output Compares with Pulse

Generator capabilities

– fast I2C Multi Master interface (not on all prod-

ucts - see device summary)

– Low voltage (LVD) reset ensuring proper power-

on or power-off of the device

All ST7263 MCUs are available in ROM and OTP

versions.

The ST72E631 is the EPROM version of the

ST7263 in CSDIP32 windowed packages.

– USB low speed interface with 3 endpoints with

programmable in/out configuration using the

DMA architecture with embedded 3.3V voltage

regulator and transceivers (no external compo-

nents are needed).

A specific mode is available to allow programming

of the EPROM user memory array. This is set by a

specific voltage source applied to the V /TEST

PP

pin.

– 8-bit Analog-to-Digital converter (ADC) with 8

multiplexed analog inputs

Figure 1. General Block Diagram

Internal

CLOCK

OSC/3

OSCIN

OSCILLATOR

OSCOUT

2

I C*

OSC/4 or OSC/2

(for USB)

PA[7:0]

V

PORT A

(8 bits)

DD

POWER

V

SUPPLY

WATCHDOG

CONTROL

SS

16-BIT TIMER

PORT B

PB[7:0]

RESET

(8 bits)

ADC

8-BIT CORE

ALU

PORT C

LVD

PC[2:0]

(3 bits)

SCI*

(UART)

USB DMA

USBDP

USBDM

USBVCC

V

/TEST

USB SIE

PROGRAM

MEMORY

(4K/8K/16K Bytes)

PP

V

DDA

V

SSA

RAM

(256/512 Bytes)

* not on all products (refer to Table 1: Device Summary)

5/109

ST7263

1.2 PIN DESCRIPTION

Figure 2. 34-Pin SO Package Pinout

V

34

33

32

DDA

V

1

DD

USBVCC

USBDM

OSCOUT

OSCIN

2

3

USBDP

V

31

30

29

28

27

26

25

24

23

22

21

20

19

18

4

SS

V

PC2/USBOE

PC1/TDO

PC0/RDI

5

SSA

PA0/MCO

6

PA1(25mA)/SDA

7

NC

RESET

8

NC

AIN7/IT8/PB7(10mA)

AIN6/IT7/PB6(10mA)

9

NC

10

11

12

PA2(25mA)/SCL

V

/TEST

PA3/EXTCLK

PA4/ICAP1/IT1

PA5/ICAP2/IT2

PP

AIN5/IT6/PB5(10mA)

AIN4/IT5/PB4(10mA)

AIN3/PB3(10mA)

AIN2/PB2(10mA)

AIN1/PB1(10mA)

13

14

PA6/OCMP1/IT3

PA7/OCMP2/IT4

PB0(10mA)/AIN0

15

16

17

* V on EPROM/OTP versions only

PP

Figure 3. 32-Pin SDIP Package Pinout

V

1

DDA

DD

32

USBVCC

USBDM

USBDP

OSCOUT

OSCIN

2

3

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

V

4

SS

V

5

PC2/USBOE

PC1/TDO

PC0/RDI

RESET

SSA

6

PA0/MCO

PA1(25mA)/SDA

7

8

NC

AIN7/IT8/PB7(10mA)

AIN6/IT7/PB6(10mA)

NC

9

PA2(25mA)/SCL

10

11

12

13

14

15

16

V

/TEST*

PA3/EXTCLK

PP

AIN5/IT6/PB5(10mA)

AIN4/IT5/PB4(10mA)

AIN3/PB3(10mA)

AIN2/PB2(10mA)

AIN1/PB1/(10mA)

PA4/ICAP1/IT1

PA5/ICAP2/IT2

PA6/COMP1/IT3

PA7/COMP2/IT4

PB0(10mA)/AIN0

* V on EPROM/OTP versions only

PP

6/109

ST7263

PIN DESCRIPTION (Cont’d)

RESET (see Note 1): Bidirectional. This active low

signal forces the initialization of the MCU. This

event is the top priority non maskable interrupt.

This pin is switched low when the Watchdog has

Alternate Functions: Several pins of the I/O ports

assume software programmable alternate func-

tions as shown in the pin description.

Note 1: Adding two 100nF decoupling capacitors

on Reset pin (respectively connected to V_DDand

V_SS) will significantly improve product electromag-

netic susceptibility performances.

triggered or V is low. It can be used to reset ex-

DD

ternal peripherals.

OSCIN/OSCOUT: Input/Output Oscillator pin.

These pins connect a parallel-resonant crystal, or

an external source to the on-chip oscillator.

Note 2: To enhance reliability of operation, it is

recommended to connect V

and V_DDtogether

DDA

V

/TEST: EPROM programming input. This pin

on the application board. The same recommenda-

tions apply to V_SSAand V

PP

must be held low during normal operating modes.

.

SS

V

/V (see Note 2): Main power supply and

DD SS

Ground voltages.

V

/V (see Note 2): Power Supply and

DDA SSA

Ground for analog peripherals.

Table 2. Device Pin Description

Pin n°

Level

Port / Control

Main

Function

(after reset)

Input

Output

Pin Name

Alternate Function

1

2

3

4

5

6

7

8

--

9

1

2

3

4

5

6

7

8

9

V

S

Power supply voltage (4V - 5.5V)

Oscillator output

DD

OSCOUT

OSCIN

O

I

Oscillator input

V

S

Digital ground

SS

PC2/USBOE

PC1/TDO

PC0/RDI

RESET

I/O

--

C

X

Port C2

Port C1

Port C0

Reset

USB Output Enable

T

*)

X

SCI transmit data output

*)

X

SCI Receive Data Input

X

NC

Not connected

Port B7

Port B6

10 PB7/AIN7/IT8

I/O

S

C

10mA

X

ADC analog input 7

ADC analog input 6

T

10 11 PB6/AIN6/IT7

11 12 /TEST

V

Supply for EPROM and test input

PP

12 13 PB5/AIN5/IT6

13 14 PB4/AIN4/IT5

14 15 PB3/AIN3

I/O

C

10mA

X

Port B5

Port B4

Port B3

Port B2

Port B1

Port B0

Port A7

Port A6

ADC analog input 5

ADC analog input 4

ADC analog input 3

ADC analog input 2

ADC analog input 1

ADC Analog Input 0

Timer Output Compare 2

Timer Output Compare 1

T

15 16 PB2/AIN2

16 17 PB1/AIN1

17 18 PB0/AIN0

18 19 PA7/OCMP2/IT4

19 20 PA6/OCMP1/IT3

C

X

T

C

7/109

ST7263

Pin n°

Level

Port / Control

Input Output

Main

Function

(after reset)

Pin Name

Alternate Function

20 21 PA5/ICAP2/IT2

21 22 PA4/ICAP1/IT1

22 23 PA3/EXTCLK

23 24 PA2/SCL

-- 25 NC

I/O

--

C

X

Port A5

Timer Input Capture 2

Timer Input Capture 1

Timer External Clock

T

Port A4

Port A3

*)

2

C

25mA

X

T

Port A2

I C serial clock

T

Not connected

Port A1

24 26 NC

--

25 27 NC

--

*)

2

26 28 PA1/SDA

27 29 PA0/MCO

I/O

S

25mA

I C serial data

C

X

Port A0

Main Clock Output

T

28 30

V

Analog ground

SSA

29 31 USBDP

30 32 USBDM

31 33 USBVCC

I/O

O

USB bidirectional data (data +)

USB bidirectional data (data -)

USB power supply

32 34

V

S

Analog supply voltage

DDA

*: if the peripheral is present on the device (see Table 1 Device Summary)

Legend / Abbreviations for Figure 2 and Table 2:

Type:

I = input, O = output, S = supply

In/Output level: C = CMOS 0.3V /0.7V with input trigger

T

DD

Output level:

10mA = 10mA high sink (on N-buffer only)

25mA = 25mA very high sink (on N-buffer only)

Port and control configuration:

– Input:

float = floating, wpu = weak pull-up, int = interrupt, ana = analog

OD = open drain, PP = push-pull, T = True open drain

– Output:

Refer to “I/O PORTS” on page 25 for more details on the software configuration of the I/O ports.

The RESET configuration of each pin is shown in bold. This configuration is kept as long as the device is

under reset state.

8/109

ST7263

1.3 EXTERNAL CONNECTIONS

The following figure shows the recommended ex-

ternal connections for the device.

The external reset network is intended to protect

the device against parasitic resets, especially in

noisy environments.

The V pin is only used for programming OTP

PP

and EPROM devices and must be tied to ground in

Unused I/Os should be tied high to avoid any un-

necessary power consumption on floating lines.

An alternative solution is to program the unused

ports as inputs with pull-up.

user mode.

The 10 nF and 0.1 µF decoupling capacitors on

the power supply lines are a suggested EMC per-

formance/cost tradeoff.

Figure 4. Recommended External Connections

V

PP

DD

SS

V

DD

+

0.1µF

10nF

Optional if Low Voltage

Detector (LVD) is used

V

DD

4.7K

0.1µF

RESET

EXTERNAL RESET CIRCUIT

See

Clocks

OSCIN

Section

OSCOUT

Or configure unused I/O ports

by software as input with pull-up

10K

V

DD

Unused I/O

9/109

ST7263

1.4 REGISTER & MEMORY MAP

As shown in Figure 5, the MCU is capable of ad-

dressing 64K bytes of memories and I/O registers.

The highest address bytes contain the user reset

and interrupt vectors.

The available memory locations consist of 192

bytes of register location, up to 512 bytes of RAM

and up to 16K bytes of user program memory. The

RAM space includes up to 64 bytes for the stack

from 0100h to 013Fh.

IMPORTANT: Memory locations noted “Re-

served” must never be accessed. Accessing a re-

served area can have unpredictable effects on the

device

Figure 5. Memory Map

0000h

HW Registers

0040h

(see Table

4

Short Addressing

003Fh

0040h

RAM (192 Bytes)

00FFh

256 Bytes RAM*

512 Bytes RAM*

0100h

Stack (64 Bytes)

013Fh

023Fh

0240h

Reserved

0040h

Short Addressing

BFFFh

C000h

RAM (192 Bytes)

00FFh

Program Memory*

16K Bytes

0100h

Stack (64 Bytes)

013Fh

0140h

E000h

F000h

8K Bytes

16-bit Addressing RAM

(256 Bytes)

4K Bytes

023Fh

FFEFh

FFF0h

Interrupt & Reset Vectors

(see Table 3 on page 10)

FFFFh

* Program memory and RAM sizes are product dependent (see Table 1 Device Summary)

Table 3. Interrupt Vector Map

Vector Address

Description

Masked by

Remarks

Exit from Halt Mode

FFF0-FFF1h

FFF2-FFF3h

FFF4-FFF5h

FFF6-FFF7h

FFF8-FFF9h

USB Interrupt Vector

SCI Interrupt Vector*

I- bit

none

Internal Interrupt

External Interrupts

Internal Interrupt

CPU Interrupt

No

2

I C Interrupt Vector*

No

TIMER Interrupt Vector

No

IT1 to IT8 Interrupt Vector

Yes

No

FFFA-FFFBh USB End Suspend Mode Interrupt Vector

FFFC-FFFDh

FFFE-FFFFh

TRAP (software) Interrupt Vector

RESET Vector

Yes

* If the peripheral is present on the device (see Table 1 Device Summary)

10/109

ST7263

Table 4. Hardware Register Memory Map

Address

Block

Register Label

Register name

Port A Data Register

Reset Status

Remarks

R/W

0000h

0001h

PADR

00h

PADDR

Port A Data Direction Register

R/W

0002h

0003h

PBDR

Port B Data Register

00h

R/W

PBDDR

Port B Data Direction Register

0004h

0005h

PCDR

Port C Data Register

1111 x000b

R/W

PCDDR

Port C Data Direction Register

0006h

0007h

Reserved (2 Bytes)

0008h

0009h

ITIFRE

MISCR

Interrupt Register

00h

F0h

R/W

Miscellaneous Register

000Ah

000Bh

DR

ADC Data Register

00h

Read only

R/W

ADC

WDG

CSR

ADC control Status register

000Ch

CR

Watchdog Control Register

7Fh

R/W

000Dh

0010h

Reserved (4 Bytes)

0011h

0012h

0013h

0014h

0015h

0016h

0017h

0018h

0019h

001Ah

001Bh

001Ch

001Dh

001Eh

001Fh

CR2

Timer Control Register 2

00h

xxh

80h

00h

FFh

FCh

FFh

FCh

xxh

80h

00h

R/W

CR1

Timer Control Register 1

R/W

SR

Timer Status Register

Read only

R/W

IC1HR

IC1LR

OC1HR

OC1LR

CHR

Timer Input Capture High Register 1

Timer Input Capture Low Register 1

Timer Output Compare High Register 1

Timer Output Compare Low Register 1

Timer Counter High Register

R/W

TIM

Read only

R/W

CLR

Timer Counter Low Register

ACHR

ACLR

IC2HR

IC2LR

OC2HR

OC2LR

Timer Alternate Counter High Register

Timer Alternate Counter Low Register

Timer Input Capture High Register 2

Timer Input Capture Low Register 2

Timer Output Compare High Register 2

Timer Output Compare Low Register 2

Read only

R/W

Read only

R/W

0020h

0021h

0022h

0023h

0024h

SR

SCI Status Register

SCI Data Register

C0h

Read only

R/W

DR

xxh

1)

SCI

BRR

CR1

CR2

SCI Baud Rate Register

SCI Control Register 1

SCI Control Register 2

00xx xxxxb

xxh

R/W

00h

R/W

11/109

ST7263

Address

Block

Register Label

Register name

USB PID Register

Reset Status

Remarks

Read only

0025h

0026h

0027h

0028h

0029h

002Ah

002Bh

002Ch

002Dh

002Eh

002Fh

0030h

0031h

PIDR

xxh

DMAR

IDR

USB DMA address Register

USB Interrupt/DMA Register

USB Interrupt Status Register

USB Interrupt Mask Register

USB Control Register

xxh

R/W

xxh

ISTR

00h

IMR

00h

CTLR

DADDR

EP0RA

EP0RB

EP1RA

EP1RB

EP2RA

EP2RB

xxxx 0110b

00h

USB

USB Device Address Register

USB Endpoint 0 Register A

USB Endpoint 0 Register B

USB Endpoint 1 Register A

USB Endpoint 1 Register B

USB Endpoint 2 Register A

USB Endpoint 2 Register B

0000 xxxxb

80h

0000 xxxxb

0032h

0038h

Reserved (7 Bytes)

2

0039h

003Ah

003Bh

003Ch

003Dh

003Eh

003Fh

DR

I C Data Register

00h

-

R/W

2

1)

I C

Reserved

OAR

CCR

SR2

SR1

CR

I2C (7 Bits) Slave Address Register

00h

R/W

2

I C Clock Control Register

R/W

2

I C 2nd Status Register

Read only

R/W

2

I C 1st Status Register

2

I C Control Register

Note 1. If the peripheral is present on the device (see Table 1 Device Summary)

12/109

ST7263

1.5 EPROM/OTP PROGRAM MEMORY

The program memory of the ST72T63 may be pro-

grammed using the EPROM programming boards

available from STMicroelectronics (see Table 26).

An opaque coating (paint, tape, label, etc...)

should be placed over the package window if the

product is to be operated under these lighting con-

ditions. Covering the window also reduces I

power-saving modes due to photo-diode leakage

in

DD

1.5.1 EPROM ERASURE

ST72Exxx EPROM devices are erased by expo-

sure to high intensity UV light admitted through the

transparent window. This exposure discharges the

floating gate to its initial state through induced

photo current.

currents.

An Ultraviolet source of wave length 2537 Å yield-

2

ing a total integrated dosage of 15 Watt-sec/cm is

required to erase the ST72Exxx. The device will

be erased in 15 to 30 minutes if such a UV lamp

2

It is recommended that the ST72Exxx devices be

kept out of direct sunlight, since the UV content of

sunlight can be sufficient to cause functional fail-

ure. Extended exposure to room level fluorescent

lighting may also cause erasure.

with a 12mW/cm power rating is placed 1 inch

from the device window without any interposed fil-

ters.

13/109

ST7263

2 CENTRAL PROCESSING UNIT

2.1 INTRODUCTION

Accumulator (A)

The Accumulator is an 8-bit general purpose reg-

ister used to hold operands and the results of the

arithmetic and logic calculations and to manipulate

data.

This CPU has a full 8-bit architecture and contains

six internal registers allowing efficient 8-bit data

manipulation.

Index Registers (X and Y)

2.2 MAIN FEATURES

In indexed addressing modes, these 8-bit registers

are used to create either effective addresses or

temporary storage areas for data manipulation.

(The Cross-Assembler generates a precede in-

struction (PRE) to indicate that the following in-

struction refers to the Y register.)

■ 63 basic instructions

■ Fast 8-bit by 8-bit multiply

■ 17 main addressing modes

■ Two 8-bit index registers

■ 16-bit stack pointer

The Y register is not affected by the interrupt auto-

matic procedures (not pushed to and popped from

the stack).

■ Low power modes

■ Maskable hardware interrupts

■ Non-maskable software interrupt

Program Counter (PC)

The program counter is a 16-bit register containing

the address of the next instruction to be executed

by the CPU. It is made of two 8-bit registers PCL

(Program Counter Low which is the LSB) and PCH

(Program Counter High which is the MSB).

2.3 CPU REGISTERS

The 6 CPU registers shown in Figure 1 are not

present in the memory mapping and are accessed

by specific instructions.

Figure 6. CPU Registers

7

0

ACCUMULATOR

RESET VALUE = XXh

7

0

X INDEX REGISTER

Y INDEX REGISTER

RESET VALUE = XXh

7

RESET VALUE = XXh

PCL

PCH

7

8

15

0

PROGRAM COUNTER

RESET VALUE = RESET VECTOR @ FFFEh-FFFFh

7

1

0

1

H I N Z

C

CONDITION CODE REGISTER

RESET VALUE =

8

1

X 1 X X X

0

15

7

STACK POINTER

RESET VALUE = STACK HIGHER ADDRESS

X = Undefined Value

14/109

ST7263

CPU REGISTERS (Cont’d)

CONDITION CODE REGISTER (CC)

Read/Write

because the I bit is set by hardware at the start of

the routine and reset by the IRET instruction at the

end of the routine. If the I bit is cleared by software

in the interrupt routine, pending interrupts are

serviced regardless of the priority level of the cur-

rent interrupt routine.

Reset Value: 111x1xxx

7

0

1

H

I

N

Z

C

Bit 2 = N Negative.

The 8-bit Condition Code register contains the in-

terrupt mask and four flags representative of the

result of the instruction just executed. This register

can also be handled by the PUSH and POP in-

structions.

This bit is set and cleared by hardware. It is repre-

sentative of the result sign of the last arithmetic,

logical or data manipulation. It is a copy of the 7

th

bit of the result.

0: The result of the last operation is positive or null.

1: The result of the last operation is negative

(i.e. the most significant bit is a logic 1).

These bits can be individually tested and/or con-

trolled by specific instructions.

This bit is accessed by the JRMI and JRPL instruc-

tions.

Bit 4 = H Half carry.

This bit is set by hardware when a carry occurs be-

tween bits 3 and 4 of the ALU during an ADD or

ADC instruction. It is reset by hardware during the

same instructions.

0: No half carry has occurred.

1: A half carry has occurred.

Bit 1 = Z Zero.

This bit is set and cleared by hardware. This bit in-

dicates that the result of the last arithmetic, logical

or data manipulation is zero.

0: The result of the last operation is different from

zero.

This bit is tested using the JRH or JRNH instruc-

tion. The H bit is useful in BCD arithmetic subrou-

tines.

1: The result of the last operation is zero.

This bit is accessed by the JREQ and JRNE test

instructions.

Bit 3 = I Interrupt mask.

This bit is set by hardware when entering in inter-

rupt or by software to disable all interrupts except

the TRAP software interrupt. This bit is cleared by

software.

0: Interrupts are enabled.

1: Interrupts are disabled.

Bit 0 = C Carry/borrow.

This bit is set and cleared by hardware and soft-

ware. It indicates an overflow or an underflow has

occurred during the last arithmetic operation.

0: No overflow or underflow has occurred.

1: An overflow or underflow has occurred.

This bit is controlled by the RIM, SIM and IRET in-

structions and is tested by the JRM and JRNM in-

structions.

This bit is driven by the SCF and RCF instructions

and tested by the JRC and JRNC instructions. It is

also affected by the “bit test and branch”, shift and

rotate instructions.

Note: Interrupts requested while I is set are

latched and can be processed when I is cleared.

By default an interrupt routine is not interruptable

15/109

ST7263

CPU REGISTERS (Cont’d)

Stack Pointer (SP)

Read/Write

The least significant byte of the Stack Pointer

(called S) can be directly accessed by a LD in-

struction.

Reset Value: 01 3Fh

Note: When the lower limit is exceeded, the Stack

Pointer wraps around to the stack upper limit, with-

out indicating the stack overflow. The previously

stored information is then overwritten and there-

fore lost. The stack also wraps in case of an under-

flow.

15

8

1

0

7

0

The stack is used to save the return address dur-

ing a subroutine call and the CPU context during

an interrupt. The user may also directly manipulate

the stack by means of the PUSH and POP instruc-

tions. In the case of an interrupt, the PCL is stored

at the first location pointed to by the SP. Then the

other registers are stored in the next locations as

shown in Figure 7.

0

SP5

SP4

SP3

SP2

SP1

SP0

The Stack Pointer is a 16-bit register which is al-

ways pointing to the next free location in the stack.

It is then decremented after data has been pushed

onto the stack and incremented before data is

popped from the stack (see Figure 7).

– When an interrupt is received, the SP is decre-

mented and the context is pushed on the stack.

Since the stack is 64 bytes deep, the 10 most sig-

nificant bits are forced by hardware. Following an

MCU Reset, or after a Reset Stack Pointer instruc-

tion (RSP), the Stack Pointer contains its reset val-

ue (SP5 to SP0 bits are set) which is the stack

higher address.

– On return from interrupt, the SP is incremented

and the context is popped from the stack.

A subroutine call occupies two locations and an in-

terrupt five locations in the stack area.

Figure 7. Stack Manipulation Example

CALL

Subroutine

RET

or RSP

PUSH Y

POP Y

IRET

Interrupt

Event

@ 0100h

SP

Y

CC

A

CC

A

CC

A

X

PCH

PCL

PCH

PCL

PCH

PCL

PCH

PCL

PCH

PCL

PCH

PCL

SP

PCH

PCL

PCH

PCL

SP

@ 013Fh

Stack Higher Address = 013Fh

0100h

Stack Lower Address =

16/109

ST7263

3 CLOCKS AND RESET

3.1 CLOCK SYSTEM

3.1.1 General Description

Figure 8. External Clock Source Connections

The MCU accepts either a Crystal or Ceramic res-

onator, or an external clock signal to drive the in-

ternal oscillator. The internal clock (f

rived from the external oscillator frequency (f

which is divided by 3 (and by 2 or 4 for USB, de-

) is de-

CPU

),

OSC

pending on the external clock used).

OSCIN

OSCOUT

NC

By setting the CLKDIV bit in the Miscellaneous

Register, a 12 MHz external clock can be used giv-

ing an internal frequency of 4 MHz while maintain-

ing a 6 MHz for USB (refer to Figure 10).

EXTERNAL

CLOCK

The internal clock signal (f

) is also routed to

CPU

the on-chip peripherals. The CPU clock signal

consists of a square wave with a duty cycle of

50%.

Figure 9. Crystal/Ceramic Resonator

The internal oscillator is designed to operate with

an AT-cut parallel resonant quartz or ceramic res-

onator in the frequency range specified for f

.

osc

The circuit shown in Figure 9 is recommended

when using a crystal, and Table 5 Recommended

Values for 24 MHz Crystal Resonator lists the rec-

ommended capacitance. The crystal and associat-

ed components should be mounted as close as

possible to the input pins in order to minimize out-

put distortion and start-up stabilisation time.

OSCOUT

OSCIN

R_P

C

OSCIN

OSCOUT

Table 5. Recommended Values for 24 MHz

Crystal Resonator

Figure 10. Clock block diagram

R

20 Ω

56pF

25 Ω

47pF

70 Ω

22pF

SMAX

8 or 4 MHz

CPU and

C

OSCIN

peripherals)

C

56pF

47pF

22pF

OSCOUT

%3

R_P

1-10 MΩ

Note: R

is the equivalent serial resistor of the

SMAX

CLKDIV

1

crystal (see crystal specification).

6 MHz (USB)

3.1.2 External Clock

%2

24 or

12 MHz

Crystal

An external clock may be applied to the OSCIN in-

put with the OSCOUT pin not connected, as

0

%2

shown on Figure 8. The t

specifications does

OXOV

not apply when using an external clock input. The

equivalent specification of the external clock

source should be used instead of t

tion 6.5 CONTROL TIMING).

(see Sec-

OXOV

17/109

ST7263

3.2 RESET

The Reset procedure is used to provide an orderly

software start-up or to exit low power modes.

During low voltage reset, the RESETpin is held low,

thus permitting the MCU to reset other devices.

Three reset modes are provided: a low voltage

(LVD) reset, a watchdog reset and an external re-

set at the RESET pin.

The Low Voltage Detector can be disabled by set-

ting the LVD bit of the Miscellaneous Register.

A reset causes the reset vector to be fetched from

addresses FFFEh and FFFFh in order to be loaded

into the PC and with program execution starting

from this point.

3.2.2 Watchdog Reset

When a watchdog reset occurs, the RESET pin is

pulled low permitting the MCU to reset other devic-

es in the same way as the low voltage reset (Fig-

ure 11).

An internal circuitry provides a 4096 CPU clock cy-

cle delay from the time that the oscillator becomes

active.

3.2.3 External Reset

The external reset is an active low input signal ap-

plied to the RESET pin of the MCU.

As shown in Figure 14, the RESET signal must

stay low for a minimum of one and a half CPU

clock cycles.

3.2.1 Low Voltage Detector (LVD)

Low voltage reset circuitry generates a reset when

V

is:

DD

■ below V when V is rising,

IT+

DD

■ below V when V is falling.

An internal Schmitt trigger at the RESET pin is pro-

vided to improve noise immunity.

IT-

DD

Table 6. List of sections affected by RESET, WAIT and HALT (Refer to 3.5 for Wait and Halt Modes)

Section

RESET

WAIT

HALT

CPU clock running at 8 MHz

Timer Prescaler reset to zero

Timer Counter set to FFFCh

X

All Timer enable bit set to 0 (disable)

Data Direction Registers set to 0 (as Inputs)

Set Stack Pointer to 013Fh

Force Internal Address Bus to restart vector FFFEh,FFFFh

Set Interrupt Mask Bit (I-Bit, CCR) to 1 (Interrupt Disable)

Set Interrupt Mask Bit (I-Bit, CCR) to 0 (Interrupt Enable)

Reset HALT latch

X

Reset WAIT latch

Disable Oscillator (for 4096 cycles)

Set Timer Clock to 0

X

Watchdog counter reset

Watchdog register reset

Port data registers reset

Other on-chip peripherals: registers reset

18/109

ST7263

Figure 11. Low Voltage Detector functional Diagram

Figure 12. Low Voltage Reset Signal Output

RESET

V

IT+

V

IT-

LOW VOLTAGE

V

DD

DETECTOR

INTERNAL

RESET

V

DD

FROM

WATCHDOG

RESET

Note: Hysteresis (V -V ) = V

IT+ IT-

hys

Figure 13. Temporization timing diagram after an internal Reset

V

IT+

V

DD

temporization (4096 CPU clock cycles)

$FFFE

Addresses

Figure 14. Reset Timing Diagram

t

DDR

V

DD

OSCIN

t

OXOV

f

CPU

FFFF

FFFE

PC

RESET

4096 CPU

CLOCK

CYCLES

DELAY

WATCHDOG RESET

Note: Refer to Electrical Characteristics for values of t

, t_OXOV, V , V and V

IT+ IT- hys

DDR

19/109

ST7263

4 INTERRUPTS AND POWER SAVING MODES

4.1 INTERRUPTS

The ST7 core may be interrupted by one of two dif-

ferent methods: maskable hardware interrupts as

listed in Table 7 Interrupt Mapping and a non-

maskable software interrupt (TRAP). The Interrupt

processing flowchart is shown in Figure 15.

Interrupts and Low power mode

All interrupts allow the processor to leave the Wait

low power mode. Only external and specific men-

tioned interrupts allow the processor to leave the

Halt low power mode (refer to the “Exit from HALT“

column in Table 7 Interrupt Mapping).

The maskable interrupts must be enabled clearing

the I bit in order to be serviced. However, disabled

interrupts may be latched and processed when

they are enabled (see external interrupts subsec-

tion).

External interrupts

The pins ITi/PAk and ITj/PBk (i=1,2; j= 5,6; k=4,5)

can generate an interrupt when a rising edge oc-

curs on this pin. Conversely, pins ITl/PAn and ITm/

PBn (l=3,4; m= 7,8; n=6,7) can generate an inter-

rupt when a falling edge occurs on this pin.

When an interrupt has to be serviced:

– Normal processing is suspended at the end of

the current instruction execution.

Interrupt generation will occur if it is enabled with

the ITiE bit (i=1 to 8) in the ITRFRE register and if

the I bit of the CCR is reset.

– The PC, X, A and CC registers are saved onto

the stack.

– The I bit of the CC register is set to prevent addi-

tional interrupts.

Peripheral interrupts

– The PC is then loaded with the interrupt vector of

the interrupt to service and the first instruction of

the interrupt service routine is fetched (refer to

Table 7 Interrupt Mapping for vector addresses).

Different peripheral interrupt flags in the status

register are able to cause an interrupt when they

are active if both.

– The I bit of the CC register is cleared.

The interrupt service routine should finish with the

IRET instruction which causes the contents of the

saved registers to be recovered from the stack.

– The corresponding enable bit is set in the control

register.

Note: As a consequence of the IRET instruction,

the I bit will be cleared and the main program will

resume.

If any of these two conditions is false, the interrupt

is latched and thus remains pending.

Clearing an interrupt request is done by:

– writing “0” to the corresponding bit in the status

register or

Priority management

By default, a servicing interrupt can not be inter-

rupted because the I bit is set by hardware enter-

ing in interrupt routine.

– an access to the status register while the flag is

set followed by a read or write of an associated

register.

In the case several interrupts are simultaneously

pending, a hardware priority defines which one will

be serviced first (see Table 7 Interrupt Mapping).

Notes:

1. The clearing sequence resets the internal latch.

A pending interrupt (i.e. waiting for being enabled)

will therefore be lost if the clear sequence is exe-

cuted.

Non maskable software interrupts

2. All interrupts allow the processor to leave the

Wait low power mode.

This interrupt is entered when the TRAP instruc-

tion is executed regardless of the state of the I bit.

It will be serviced according to the flowchart on

Figure 15.

3. Exit from Halt mode may only be triggered by an

External Interrupt on one of the ITi ports (PA4-PA7

and PB4-PB7), an end suspend mode Interrupt

coming from USB peripheral, or a reset.

20/109

ST7263

INTERRUPTS (Cont’d)

Figure 15. Interrupt Processing Flowchart

FROM RESET

N

BIT I SET

Y

N

INTERRUPT

Y

FETCH NEXT INSTRUCTION

N

IRET

STACK PC, X, A, CC

SET I BIT

Y

LOAD PC FROM INTERRUPT VECTOR

EXECUTE INSTRUCTION

RESTORE PC, X, A, CC FROM STACK

THIS CLEARS I BIT BY DEFAULT

Table 7. Interrupt Mapping

Vector

Exit

from

HALT

Source

Block

Register Priority

N°

Description

Address

Label

Order

RESET

TRAP

USB

Reset

Highest

Priority

yes

no

FFFEh-FFFFh

FFFCh-FFFDh

FFFAh-FFFBh

FFF8h-FFF9h

FFF6h-FFF7h

N/A

Software Interrupt

End Suspend Mode

External Interrupts

Timer Peripheral Interrupts

ISTR

yes

no

1

2

ITi

ITRFRE

TIMSR

I2CSR1

I2CSR2

SCISR

TIMER

2

3

4

5

I C

I C Peripheral Interrupts

FFF4h-FFF5h

FFF2h-FFF3h

FFF0h-FFF1h

SCI

SCI Peripheral Interrupts

USB Peripheral Interrupts

Lowest

Priority

USB

ISTR

21/109

ST7263

INTERRUPTS (Cont’d)

4.1.1 Interrupt Register

INTERRUPTS REGISTER (ITRFRE)

If an ITiE bit is set, the corresponding interrupt is

generated when

Address: 0008h

—

Read/Write

Reset Value: 0000 0000 (00h)

– a rising edge occurs on the pin PA4/IT1 or PA5/

IT2 or PB4/IT5 or PB5/IT6

7

0

or

IT8E

IT7E

IT6E

IT5E

IT4E

IT3E

IT2E

IT1E

– a falling edge occurs on the pin PA6/IT3 or PA7/

IT4 or PB6/IT7 or PB7/IT8

Bit 7:0 = ITiE (i=1 to 8). Interrupt Enable Control

Bits.

No interrupt is generated elsewhere.

Note: Analog input must be disabled for interrupts

coming from port B.

22/109

ST7263

4.2 POWER SAVING MODES

4.2.1 Introduction

Figure 16. HALT Mode Flow Chart

To give a large measure of flexibility to the applica-

tion in terms of power consumption, two main pow-

er saving modes are implemented in the ST7.

HALT INSTRUCTION

After a RESET the normal operating mode is se-

lected by default (RUN mode). This mode drives

the device (CPU and embedded peripherals) by

means of a master clock which is based on the

OSCILLATOR

PERIPH. CLOCK

CPU CLOCK

I-BIT

OFF

main oscillator frequency divided by 3 (f

).

CPU

OFF

From Run mode, the different power saving

modes may be selected by setting the relevant

register bits or by calling the specific ST7 software

instruction whose action depends on the oscillator

status.

CLEARED

4.2.2 HALT mode

N

RESET

The HALT mode is the MCU lowest power con-

sumption mode. The HALT mode is entered by ex-

ecuting the HALT instruction. The internal oscilla-

tor is then turned off, causing all internal process-

ing to be stopped, including the operation of the

on-chip peripherals.

N

EXTERNAL

Y

INTERRUPT*

Y

When entering HALT mode, the I bit in the Condi-

tion Code Register is cleared. Thus, any of the ex-

ternal interrupts (ITi or USB end suspend mode),

are allowed and if an interrupt occurs, the CPU

clock becomes active.

OSCILLATOR

ON

PERIPH. CLOCK

CPU CLOCK

I-BIT

ON

SET

The MCU can exit HALT mode on reception of ei-

ther an external interrupt on ITi, an end suspend

mode interrupt coming from USB peripheral, or a

reset. The oscillator is then turned on and a stabi-

lization time is provided before releasing CPU op-

eration. The stabilization time is 4096 CPU clock

cycles.

4096 CPU CLOCK

CYCLES DELAY

After the start up delay, the CPU continues opera-

tion by servicing the interrupt which wakes it up or

by fetching the reset vector if a reset wakes it up.

FETCH RESET VECTOR

OR SERVICE INTERRUPT

Note: Before servicing an interrupt, the CC register is

pushed on the stack. The I-Bit is set during the inter-

rupt routine and cleared when the CC register is

popped.

23/109

ST7263

POWER SAVING MODES (Cont’d)

4.2.3 WAIT mode

Figure 17. WAIT Mode Flow Chart

WAIT mode places the MCU in a low power con-

sumption mode by stopping the CPU.

WFI INSTRUCTION

This power saving mode is selected by calling the

“WFI” ST7 software instruction.

All peripherals remain active. During WAIT mode,

the I bit of the CC register is forced to 0, to enable

all interrupts. All other registers and memory re-

main unchanged. The MCU remains in WAIT

mode until an interrupt or Reset occurs, whereup-

on the Program Counter branches to the starting

address of the interrupt or Reset service routine.

The MCU will remain in WAIT mode until a Reset

or an Interrupt occurs, causing it to wake up.

OSCILLATOR

PERIPH. CLOCK

CPU CLOCK

I-BIT

ON

OFF

CLEARED

Refer to Figure 17.

N

RESET

N

Y

INTERRUPT

Y

OSCILLATOR

ON

SET

PERIPH. CLOCK

CPU CLOCK

I-BIT

IF RESET

4096 CPU CLOCK

CYCLES DELAY

FETCH RESET VECTOR

OR SERVICE INTERRUPT

Note: Before servicing an interrupt, the CC register is

pushed on the stack. The I-Bit is set during the inter-

rupt routine and cleared when the CC register is

popped.

24/109

ST7263

5 ON-CHIP PERIPHERALS

5.1 I/O PORTS

5.1.1 Introduction

terrupt request to the CPU. The interrupt sensitivi-

ty is given independently according to the descrip-

tion mentioned in the ITRFRE interrupt register.

The I/O ports offer different functional modes:

– transfer of data through digital inputs and outputs

and for specific pins:

Each pin can independently generate an Interrupt

request.

– analog signal input (ADC)

Each external interrupt vector is linked to a dedi-

cated group of I/O port pins (see Interrupts sec-

tion). If more than one input pin is selected simul-

taneously as interrupt source, this is logically

ORed. For this reason if one of the interrupt pins is

tied low, it masks the other ones.

– alternate signal input/output for the on-chip pe-

ripherals.

– external interrupt generation

An I/O port is composed of up to 8 pins. Each pin

can be programmed independently as digital input

(with or without interrupt generation) or digital out-

put.

Output Mode

The pin is configured in output mode by setting the

corresponding DDR register bit (see Table 7).

5.1.2 Functional description

Each port is associated to 2 main registers:

– Data Register (DR)

In this mode, writing “0” or “1” to the DR register

applies this digital value to the I/O pin through the

latch. Then reading the DR register returns the

previously stored value.

– Data Direction Register (DDR)

Note: In this mode, the interrupt function is disa-

bled.

Each I/O pin may be programmed using the corre-

sponding register bits in DDR register: bit X corre-

sponding to pin X of the port. The same corre-

spondence is used for the DR register.

Digital Alternate Function

Table 8. I/O Pin Functions

When an on-chip peripheral is configured to use a

pin, the alternate function is automatically select-

ed. This alternate function takes priority over

standard I/O programming. When the signal is

coming from an on-chip peripheral, the I/O pin is

automatically configured in output mode (push-pull

or open drain according to the peripheral).

DDR

MODE

Input

0

1

Output

When the signal is going to an on-chip peripheral,

the I/O pin has to be configured in input mode. In

this case, the pin’s state is also digitally readable

by addressing the DR register.

Input Modes

The input configuration is selected by clearing the

corresponding DDR register bit.

In this case, reading the DR register returns the

digital value applied to the external I/O pin.

Notes:

1. Input pull-up configuration can cause an unex-

pected value at the input of the alternate peripher-

al input.

Note 1: All the inputs are triggered by a Schmitt

trigger.

Note 2: When switching from input mode to output

mode, the DR register should be written first to

output the correct value as soon as the port is con-

figured as an output.

2. When the on-chip peripheral uses a pin as input

and output, this pin must be configured as an input

(DDR = 0).

Warning: The alternate function must not be acti-

vated as long as the pin is configured as input with

interrupt, in order to avoid generating spurious in-

terrupts.

Interrupt function

When an I/O is configured in Input with Interrupt,

an event on this I/O can generate an external In-

25/109

ST7263

I/O PORTS (Cont’d)

Analog Alternate Function

have clocking pins located close to a selected an-

alog pin.

When the pin is used as an ADC input the I/O must

be configured as input, floating. The analog multi-

plexer (controlled by the ADC registers) switches

the analog voltage present on the selected pin to

the common analog rail which is connected to the

ADC input.

Warning: The analog input voltage level must be

within the limits stated in the Absolute Maximum

Ratings.

5.1.3 I/O Port Implementation

The hardware implementation on each I/O port de-

pends on the settings in the DDR register and spe-

cific feature of the I/O port such as ADC Input or

true open drain.

It is recommended not to change the voltage level

or loading on any port pin while conversion is in

progress. Furthermore it is recommended not to

26/109

ST7263

I/O PORTS (Cont’d)

5.1.4 Port A

Table 9. Port A0, A3, A4, A5, A6, A7 Description

I / O

Alternate Function

Condition

PORT A

Input*

Output

push-pull

Signal

PA0

PA3

with pull-up

MCO (Main Clock Output) MCO = 1 (MISCR)

CC1 =1

Timer EXTCLK

with pull-up

push-pull

CC0 = 1 (Timer CR2)

Timer ICAP1

PA4

PA5

PA6

push-pull

IT1 Schmitt triggered input IT1E = 1 (ITIFRE)

Timer ICAP2

IT2 Schmitt triggered input IT2E = 1 (ITIFRE)

Timer OCMP1

IT3 Schmitt triggered input IT3E = 1 (ITIFRE)

Timer OCMP2 OC2E = 1

IT4 Schmitt triggered input IT4E = 1 (ITIFRE)

OC1E = 1

PA7

*Reset State

Figure 18. PA0, PA3, PA4, PA5, PA6, PA7 Configuration

ALTERNATE ENABLE

1

0

V_DD

ALTERNATE

OUTPUT

P-BUFFER

V

DD

DR

PULL-UP

LATCH

ALTERNATE ENABLE

DDR

LATCH

PAD

DDR SEL

N-BUFFER

DIODES

1

0

DR SEL

ALTERNATE ENABLE

V_SS

ALTERNATE INPUT

CMOS SCHMITT TRIGGER

27/109

ST7263

I/O PORTS (Cont’d)

Table 10. PA1, PA2 Description

I / O

Alternate Function

Signal Condition

I2C enable

PORT A

Input*

Output

PA1

without pull-up

Very High Current open drain

SDA (I2C data)

SCL (I2C clock)

PA2

*Reset State

Figure 19. PA1, PA2 Configuration

ALTERNATE ENABLE

1

ALTERNATE

OUTPUT

0

DR

LATCH

DDR

LATCH

PAD

DDR SEL

N-BUFFER

DR SEL

1

0

ALTERNATE ENABLE

V_SS

CMOS SCHMITT TRIGGER

28/109

ST7263

I/O PORTS (Cont’d)

5.1.5 Port B

Table 11. Port B Description

PORT B

I/O

Alternate Function

Signal Condition

Input*

Output

push-pull

PB0

PB1

PB2

PB3

without pull-up

Analog input (ADC)

CH[2:0] = 000 (ADCCSR)

CH[2:0] = 001 (ADCCSR)

CH[2:0]= 010 (ADCCSR)

CH[2:0]= 011 (ADCCSR)

CH[2:0]= 100 (ADCCSR)

push-pull

PB4

PB5

PB6

without pull-up

push-pull

IT5 Schmitt triggered input IT4E = 1 (ITIFRE)

Analog input (ADC)

CH[2:0]= 101 (ADCCSR)

IT6 Schmitt triggered input IT5E = 1 (ITIFRE)

Analog input (ADC)

CH[2:0]= 110 (ADCCSR)

IT7 Schmitt triggered input IT6E = 1 (ITIFRE)

Analog input (ADC)

CH[2:0]= 111 (ADCCSR)

PB7

IT8 Schmitt triggered input IT7E = 1 (ITIFRE)

*Reset State

Figure 20. Port B Configuration

ALTERNATE ENABLE

V

ALTERNATE

OUTPUT

DD

1

0

V

DD

P-BUFFER

DR

LATCH

ALTERNATE ENABLE

DDR

PAD

LATCH

ANALOG ENABLE

(ADC)

DDR SEL

ANALOG

SWITCH

DIODES

N-BUFFER

1

DR SEL

ALTERNATE ENABLE

DIGITAL ENABLE

V

0

SS

ALTERNATE INPUT

29/109

ST7263

I/O PORTS (Cont’d)

5.1.6 Port C

Table 12. Port C Description

I / O

Alternate Function

PORT C

Input*

Output

Signal

Condition

PC0

PC1

with pull-up

push-pull

RDI (SCI input)

TDO (SCI output)

SCI enable

USBOE =1

(MISCR)

USBOE (USB output ena-

ble)

PC2

with pull-up

push-pull

*Reset State

Figure 21. Port C Configuration

ALTERNATE ENABLE

1

0

V

ALTERNATE

OUTPUT

DD

P-BUFFER

V

DD

DR

PULL-UP

LATCH

ALTERNATE ENABLE

DDR

PAD

LATCH

DDR SEL

N-BUFFER

DIODES

1

0

DR SEL

ALTERNATE ENABLE

V

SS

ALTERNATE INPUT

CMOS SCHMITT TRIGGER

30/109

ST7263

I/O PORTS (Cont’d)

5.1.7 Register Description

DATA DIRECTION REGISTER (PxDDR)

DATA REGISTERS (PxDR)

Port A Data Direction Register (PADDR): 0001h

Port B Data Direction Register (PBDDR): 0003h

Port C Data Direction Register (PCDDR): 0005h

Read/Write

Port A Data Register (PADR): 0000h

Port B Data Register (PBDR): 0002h

Port C Data Register (PCDR): 0004h

Read/Write

Reset Value Port A: 0000 0000 (00h)

Reset Value Port B: 0000 0000 (00h)

Reset Value Port C: 1111 x000 (FXh)

Reset Value Port A: 0000 0000 (00h)

Reset Value Port B: 0000 0000 (00h)

Reset Value Port C: 1111 x000 (FXh)

Note: for Port C, unused bits (7-3) are not acces-

sible

Note: for Port C, unused bits (7-3) are not acces-

sible.

7

0

7

0

DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0

D7

D6

D5

D4

D3

D2

D1

D0

Bit 7:0 = DD7-DD0 Data Direction Register 8 bits.

The DDR register gives the input/output direction

configuration of the pins. Each bits is set and

cleared by software.

Bit 7:0 = D7-D0 Data Register 8 bits.

The DR register has a specific behaviour accord-

ing to the selected input/output configuration. Writ-

ing the DR register is always taken in account

even if the pin is configured as an input. Reading

the DR register returns either the DR register latch

content (pin configured as output) or the digital val-

ue applied to the I/O pin (pin configured as input).

0: Input mode

1: Output mode

Table 13. I/O Ports Register Map

Address

Register

Label

7

6

5

4

3

2

1

0

(Hex.)

00

PADR

PADDR

PBDR

MSB

LSB

01

02

03

PBDDR

PCDR

04

05

PCDDR

31/109

ST7263

5.2 MISCELLANEOUS REGISTER

Bit 2 = CLKDIV Clock Divider.

Address: 0009h

Reset Value: 1111 0000 (F0h)

—

Read/Write

This bit is set by software and only cleared by hard-

ware after a reset. If this bit is set, it enables the use

of a 12 MHz external oscillator (refer to Figure 10

on page 17).

7

0

0: 24 MHz external oscillator

1: 12 MHz external oscillator.

-

LVD CLKDIV USBOE MCO

Bit 7:4 = Reserved

Bit 1 = USBOE USB enable.

If this bit is set, the port PC2 outputs the USB out-

put enable signal (at “1” when the ST7 USB is

transmitting data).

Bit 3 = LVD Low Voltage Detector.

This bit is set by software and only cleared by hard-

ware after a reset.

Unused bits 7-4 are set.

0: LVD enabled

1: LVD disabled

Bit 0 = MCO Main Clock Out selection

This bit enables the MCO alternate function on the

PA0 I/O port. It is set and cleared by software.

0: MCO alternate function disabled (I/O pin free for

general-purpose I/O)

1: MCO alternate function enabled (f

port)

on I/O

CPU

32/109

ST7263

5.3 WATCHDOG TIMER (WDG)

5.3.1 Introduction

5.3.2 Main Features

■ Programmable timer (64 increments of 49152

The Watchdog timer is used to detect the occur-

rence of a software fault, usually generated by ex-

ternal interference or by unforeseen logical condi-

tions, which causes the application program to

abandon its normal sequence. The Watchdog cir-

cuit generates an MCU reset on expiry of a pro-

grammed time period, unless the program refresh-

es the counter’s contents before the T6 bit be-

comes cleared.

CPU cycles)

■ Programmable reset

■ Reset (if watchdog activated) when the T6 bit

reaches zero

Figure 22. Watchdog Block Diagram

RESET

WATCHDOG CONTROL REGISTER (CR)

T5

T0

T6

WDGA

T1

T4

T2

T3

7-BIT DOWNCOUNTER

CLOCK DIVIDER

f

CPU

÷49152

33/109

ST7263

WATCHDOG TIMER (Cont’d)

5.3.3 Functional Description

reset immediately after waking up the microcon-

troller.

The counter value stored in the CR register (bits

T6:T0), is decremented every 49,152 machine cy-

cles, and the length of the timeout period can be

programmed by the user in 64 increments.

– When using an external interrupt to wake up the

microcontroller, reinitialize the corresponding I/O

as “Input Pull-up with Interrupt” before executing

the HALT instruction. The main reason for this is

that the I/O may be wrongly configured due to ex-

ternal interference or by an unforeseen logical

condition.

If the watchdog is activated (the WDGA bit is set)

and when the 7-bit timer (bits T6:T0) rolls over

from 40h to 3Fh (T6 becomes cleared), it initiates

a reset cycle pulling low the reset pin for typically

500ns.

– For the same reason, reinitialize the level sensi-

tiveness of each external interrupt as a precau-

tionary measure.

The application program must write in the CR reg-

ister at regular intervals during normal operation to

prevent an MCU reset. The value to be stored in

the CR register must be between FFh and C0h

(see Table 14 . Watchdog Timing (fCPU = 8

MHz)):

– The opcode for the HALT instruction is 0x8E. To

avoid an unexpected HALT instruction due to a

program counter failure, it is advised to clear all

occurrences of the data value 0x8E from memo-

ry. For example, avoid defining a constant in

ROM with the value 0x8E.

– The WDGA bit is set (watchdog enabled)

– The T6 bit is set to prevent generating an imme-

diate reset

– As the HALT instruction clears the I bit in the CC

register to allow interrupts, the user may choose

to clear all pending interrupt bits before execut-

ing the HALT instruction. This avoids entering

other peripheral interrupt routines after executing

the external interrupt routine corresponding to

the wake-up event (reset or external interrupt).

– The T5:T0 bits contain the number of increments

which represents the time delay before the

watchdog produces a reset.

Table 14. Watchdog Timing (f

= 8 MHz)

CPU

CR Register

initial value

WDG timeout period

(ms)

5.3.4 Interrupts

Max

Min

FFh

C0h

393.216

6.144

None.

5.3.5 Register Description

CONTROL REGISTER (CR)

Read/Write

Notes: Following a reset, the watchdog is disa-

bled. Once activated it cannot be disabled, except

by a reset.

Reset Value: 0111 1111 (7Fh)

The T6 bit can be used to generate a software re-

set (the WDGA bit is set and the T6 bit is cleared).

7

0

5.3.3.1 Using Halt Mode with the WDG

WDGA T6

T5

T4

T3

T2

T1

T0

The HALT instruction stops the oscillator. When

the oscillator is stopped, the WDG stops counting

and is no longer able to generate a reset until the

microcontroller receives an external interrupt or a

reset.

Bit 7 = WDGA Activation bit.

This bit is set by software and only cleared by

hardware after a reset. When WDGA = 1, the

watchdog can generate a reset.

If an external interrupt is received, the WDG re-

starts counting after 4096 CPU clocks. If a reset is

generated, the WDG is disabled (reset state).

0: Watchdog disabled

1: Watchdog enabled

Recommendations

– Make sure that an external event is available to

wake up the microcontroller from Halt mode.

Bit 6:0 = T[6:0] 7-bit timer (MSB to LSB).

These bits contain the decremented value. A reset

is produced when it rolls over from 40h to 3Fh (T6

becomes cleared).

– Before executing the HALT instruction, refresh

the WDG counter, to avoid an unexpected WDG

34/109

ST7263

WATCHDOG TIMER (Cont’d)

Table 15. Watchdog Timer Register Map and Reset Values

Address

(Hex.)

Register

Label

7

6

5

4

3

2

1

0

WDGCR

WDGA

0

T6

1

T5

1

T4

1

T3

1

T2

1

T1

1

T0

1

0C

Reset Value

35/109

ST7263

5.4 16-BIT TIMER

5.4.1 Introduction

5.4.3 Functional Description

5.4.3.1 Counter

The timer consists of a 16-bit free-running counter

driven by a programmable prescaler.

The main block of the Programmable Timer is a

16-bit free running upcounter and its associated

16-bit registers. The 16-bit registers are made up

of two 8-bit registers called high & low.

It may be used for a variety of purposes, including

measuring the pulse lengths of up to two input sig-

nals (input capture) or generating up to two output

waveforms (output compare and PWM).

Counter Register (CR):

Pulse lengths and waveform periods can be mod-

ulated from a few microseconds to several milli-

seconds using the timer prescaler and the CPU

clock prescaler.

– Counter High Register (CHR) is the most sig-

nificant byte (MS Byte).

– Counter Low Register (CLR) is the least sig-

nificant byte (LS Byte).

Some ST7 devices have two on-chip 16-bit timers.

They are completely independent, and do not

share any resources. They are synchronized after

a MCU reset as long as the timer clock frequen-

cies are not modified.

Alternate Counter Register (ACR)

– Alternate Counter High Register (ACHR) is the

most significant byte (MS Byte).

– Alternate Counter Low Register (ACLR) is the

least significant byte (LS Byte).

This description covers one or two 16-bit timers. In

ST7 devices with two timers, register names are

prefixed with TA (Timer A) or TB (Timer B).

These two read-only 16-bit registers contain the

same value but with the difference that reading the

ACLR register does not clear the TOF bit (Timer

overflow flag), located in the Status register (SR).

(See note at the end of paragraph titled 16-bit read

sequence).

5.4.2 Main Features

■ Programmableprescaler:f_CPUdividedby2, 4or8.

■ Overflow status flag and maskable interrupt

■ External clock input (must be at least 4 times

slowerthan theCPUclockspeed)with thechoice

of active edge

■ Output compare functions with:

– 2 dedicated 16-bit registers

– 2 dedicated programmable signals

– 2 dedicated status flags

Writing in the CLR register or ACLR register resets

the free running counter to the FFFCh value.

Both counters have a reset value of FFFCh (this is

the only value which is reloaded in the 16-bit tim-

er). The reset value of both counters is also

FFFCh in One Pulse mode and PWM mode.

The timer clock depends on the clock control bits

of the CR2 register, as illustrated in Table 1. The

value in the counter register repeats every

131.072, 262.144 or 524.288 CPU clock cycles

depending on the CC[1:0] bits.

– 1 dedicated maskable interrupt

■ Input capture functions with:

– 2 dedicated 16-bit registers

– 2 dedicated active edge selection signals

– 2 dedicated status flags

The timer frequency can be f

or an external frequency.

/2, f

/4, f

/8

CPU

– 1 dedicated maskable interrupt

■ Pulse Width Modulation mode (PWM)

■ One Pulse mode

■ 5 alternate functionson I/O ports (ICAP1, ICAP2,

OCMP1, OCMP2, EXTCLK)*

The Block Diagram is shown in Figure 1.

*Note: Some timer pins may not be available (not

bonded) in some ST7 devices. Refer to the device

pin out description.

When reading an input signal on a non-bonded

pin, the value will always be ‘1’.

36/109

ST7263

16-BIT TIMER (Cont’d)

Figure 23. Timer Block Diagram

ST7 INTERNAL BUS

f

CPU

MCU-PERIPHERAL INTERFACE

8 low

8-bit

8 high

8

buffer

h

EXEDG

g

w

g

w

g

w

g

low

16

INPUT

CAPTURE

REGISTER

INPUT

CAPTURE

REGISTER

OUTPUT

COMPARE

REGISTER

OUTPUT

COMPARE

REGISTER

1/2

1/4

1/8

COUNTER

REGISTER

1

2

ALTERNATE

COUNTER

REGISTER

EXTCLK

16

CC[1:0]

TIMER INTERNAL BUS

16 16

OVERFLOW

DETECT

EDGE DETECT

CIRCUIT1

OUTPUT COMPARE

CIRCUIT

ICAP1

CIRCUIT

6

EDGE DETECT

CIRCUIT2

ICAP2

OCMP1

LATCH1

LATCH2

ICF1 OCF1 TOF ICF2 OCF2

0

OCMP2

(Status Register) SR

EXEDG

ICIE OCIE TOIE FOLV2 FOLV1OLVL2 IEDG1 OLVL1

OC1E

OPM PWM CC1 CC0 IEDG2

OC2E

(Control Register 1) CR1

(Control Register 2) CR2

(See note)

Note: If IC, OC and TO interrupt requests have separate vectors

then the last OR is not present (See device Interrupt Vector Table)

TIMER INTERRUPT

37/109

ST7263

16-BIT TIMER (Cont’d)

16-bit Read Sequence: (from either the Counter

Register or the Alternate Counter Register).

Clearing the overflow interrupt request is done in

two steps:

1. Reading the SR register while the TOF bit is set.

2. An access (read or write) to the CLR register.

Beginning of the sequence

Read

LS Byte

is buffered

Note: The TOF bit is not cleared by accessing the

ACLR register. The advantage of accessing the

ACLR register rather than the CLR register is that

it allows simultaneous use of the overflow function

and reading the free running counter at random

times (for example, to measure elapsed time) with-

out the risk of clearing the TOF bit erroneously.

MS Byte

At t0

Other

instructions

Returns the buffered

LS Byte value at t0

Read

LS Byte

At t0 +∆t

The timer is not affected by WAIT mode.

In HALT mode, the counter stops counting until the

mode is exited. Counting then resumes from the

previous count (MCU awakened by an interrupt) or

from the reset count (MCU awakened by a Reset).

Sequence completed

The user must read the MS Byte first, then the LS

Byte value is buffered automatically.

This buffered value remains unchanged until the

16-bit read sequence is completed, even if the

user reads the MS Byte several times.

5.4.3.2 External Clock

The external clock (where available) is selected if

CC0=1 and CC1=1 in the CR2 register.

After a complete reading sequence, if only the

CLR register or ACLR register are read, they re-

turn the LS Byte of the count value at the time of

the read.

The status of the EXEDG bit in the CR2 register

determines the type of level transition on the exter-

nal clock pin EXTCLK that will trigger the free run-

ning counter.

Whatever the timer mode used (input capture, out-

put compare, One Pulse mode or PWM mode) an

overflow occurs when the counter rolls over from

FFFFh to 0000h then:

The counter is synchronised with the falling edge

of the internal CPU clock.

A minimum of four falling edges of the CPU clock

must occur between two consecutive active edges

of the external clock; thus the external clock fre-

quency must be less than a quarter of the CPU

clock frequency.

– The TOF bit of the SR register is set.

– A timer interrupt is generated if:

– TOIE bit of the CR1 register is set and

– I bit of the CC register is cleared.

If one of these conditions is false, the interrupt re-

mains pending to be issued as soon as they are

both true.

38/109

ST7263

16-BIT TIMER (Cont’d)

Figure 24. Counter Timing Diagram, internal clock divided by 2

CPU CLOCK

INTERNAL RESET

TIMER CLOCK

FFFD FFFE FFFF 0000 0001 0002 0003

COUNTER REGISTER

TIMER OVERFLOW FLAG (TOF)

Figure 25. Counter Timing Diagram, internal clock divided by 4

CPU CLOCK

INTERNAL RESET

TIMER CLOCK

FFFC

FFFD

0000

0001

COUNTER REGISTER

TIMER OVERFLOW FLAG (TOF)

Figure 26. Counter Timing Diagram, internal clock divided by 8

CPU CLOCK

INTERNAL RESET

TIMER CLOCK

0000

FFFC

FFFD

COUNTER REGISTER

TIMER OVERFLOW FLAG (TOF)

Note: The MCU is in reset state when the internal reset signal is high. When it is low, the MCU is running.

39/109

ST7263

16-BIT TIMER (Cont’d)

5.4.3.3 Input Capture

When an input capture occurs:

In this section, the index, i, may be 1 or 2 because

there are 2 input capture functions in the 16-bit

timer.

– The ICFi bit is set.

– The ICiR register contains the value of the free

running counter on the active transition on the

ICAPi pin (see Figure 6).

The two input capture 16-bit registers (IC1R and

IC2R) are used to latch the value of the free run-

ning counter after a transition is detected by the

ICAPi pin (see figure 5).

– A timer interrupt is generated if the ICIE bit is set

and the I bit is cleared in the CC register. Other-

wise, the interrupt remains pending until both

conditions become true.

MS Byte

ICiHR

LS Byte

ICiLR

ICiR

Clearing the Input Capture interrupt request (i.e.

clearing the ICFi bit) is done in two steps:

The ICiR register is a read-only register.

1. Reading the SR register while the ICFi bit is set.

2. An access (read or write) to the ICiLR register.

The active transition is software programmable

through the IEDGi bit of Control Registers (CRi).

Timing resolution is one count of the free running

Notes:

counter: (f

/CC[1:0]).

CPU

1. After reading the ICiHR register, the transfer of

input capture data is inhibited and ICFi will

never be set until the ICiLR register is also

read.

Procedure:

To use the input capture function, select the fol-

lowing in the CR2 register:

2. The ICiR register contains the free running

counter value which corresponds to the most

recent input capture.

– Select the timer clock (CC[1:0]) (see Table 1).

– Select the edge of the active transition on the

ICAP2 pin with the IEDG2 bit (the ICAP2 pin

must be configured as a floating input).

3. The 2 input capture functions can be used

together even if the timer also uses the 2 output

compare functions.

And select the following in the CR1 register:

4. In One Pulse mode and PWM mode only the

input capture 2 function can be used.

– Set the ICIE bit to generate an interrupt after an

input capture coming from either the ICAP1 pin

or the ICAP2 pin

5. The alternate inputs (ICAP1 & ICAP2) are

always directly connected to the timer. So any

transitions on these pins activate the input cap-

ture function.

– Select the edge of the active transition on the

ICAP1 pin with the IEDG1 bit (the ICAP1pin must

be configured as a floating input).

Moreover if one of the ICAPi pin is configured

as an input and the second one as an output,

an interrupt can be generated if the user tog-

gles the output pin and if the ICIE bit is set.

This can be avoided if the input capture func-

tion i is disabled by reading the ICiHR (see note

1).

6. The TOF bit can be used with an interrupt in

order to measure events that exceed the timer

range (FFFFh).

40/109

ST7263

16-BIT TIMER (Cont’d)

Figure 27. Input Capture Block Diagram

ICAP1

(Control Register 1) CR1

EDGE DETECT

CIRCUIT2

EDGE DETECT

CIRCUIT1

ICIE

IEDG1

ICAP2

(Status Register) SR

ICF1

ICF2

0

IC2R Register

IC1R Register

(Control Register 2) CR2

16-BIT

16-BIT FREE RUNNING

IEDG2

CC0

CC1

COUNTER

Figure 28. Input Capture Timing Diagram

TIMER CLOCK

FF01

FF02

FF03

COUNTER REGISTER

ICAPi PIN

ICAPi FLAG

FF03

ICAPi REGISTER

Note: Active edge is rising edge.

41/109

ST7263

16-BIT TIMER (Cont’d)

5.4.3.4 Output Compare

– The OCMPi pin takes OLVLi bit value (OCMPi

pin latch is forced low during reset).

In this section, the index, i, may be 1 or 2 because

there are 2 output compare functions in the 16-bit

timer.

– A timer interrupt is generated if the OCIE bit is

set in the CR2 register and the I bit is cleared in

the CC register (CC).

This function can be used to control an output

waveform or indicate when a period of time has

elapsed.

The OCiR register value required for a specific tim-

ing application can be calculated using the follow-

ing formula:

When a match is found between the Output Com-

pare register and the free running counter, the out-

put compare function:

– Assigns pins with a programmable value if the

OCIE bit is set

∆t f

* CPU

PRESC

∆ OCiR =

– Sets a flag in the status register

– Generates an interrupt if enabled

Where:

∆t

= Output compare period (in seconds)

= CPU clock frequency (in hertz)

Two 16-bit registers Output Compare Register 1

(OC1R) and Output Compare Register 2 (OC2R)

contain the value to be compared to the counter

register each timer clock cycle.

f

CPU

PRESC

= Timer prescaler factor (2, 4 or 8 de-

pending on CC[1:0] bits, see Table 1)

MS Byte

OCiHR

LS Byte

OCiLR

OCiR

If the timer clock is an external clock, the formula

is:

These registers are readable and writable and are

not affected by the timer hardware. A reset event

changes the OCiR value to 8000h.

∆ OCiR = ∆t f

* EXT

Where:

Timing resolution is one count of the free running

∆t

= Output compare period (in seconds)

= External timer clock frequency (in hertz)

counter: (f

).

CC[1:0]

CPU/

f

EXT

Procedure:

Clearing the output compare interrupt request (i.e.

clearing the OCFi bit) is done by:

To use the output compare function, select the fol-

lowing in the CR2 register:

1. Reading the SR register while the OCFi bit is

– Set the OCiE bit if an output is needed then the

OCMPi pin is dedicated to the output compare i

signal.

set.

2. An access (read or write) to the OCiLR register.

– Select the timer clock (CC[1:0]) (see Table 1).

And select the following in the CR1 register:

The following procedure is recommended to pre-

vent the OCFi bit from being set between the time

it is read and the write to the OCiR register:

– Select the OLVLi bit to applied to the OCMPi pins

after the match occurs.

– Write to the OCiHR register (further compares

are inhibited).

– Set the OCIE bit to generate an interrupt if it is

needed.

– Read the SR register (first step of the clearance

of the OCFi bit, which may be already set).

When a match is found between OCRi register

and CR register:

– Write to the OCiLR register (enables the output

compare function and clears the OCFi bit).

– OCFi bit is set.

42/109

ST7263

16-BIT TIMER (Cont’d)

Notes:

Forced Compare Output capability

1. After a processor write cycle to the OCiHR reg-

ister, the output compare function is inhibited

until the OCiLR register is also written.

When the FOLVi bit is set by software, the OLVLi

bit is copied to the OCMPi pin. The OLVi bit has to

be toggled in order to toggle the OCMPi pin when

it is enabled (OCiE bit=1). The OCFi bit is then not

set by hardware, and thus no interrupt request is

generated.

2. If the OCiE bit is not set, the OCMPi pin is a

general I/O port and the OLVLi bit will not

appear when a match is found but an interrupt

could be generated if the OCIE bit is set.

FOLVLi bits have no effect in either One-Pulse

mode or PWM mode.

3. When the timer clock is f

/2, OCFi and

CPU

OCMPi are set while the counter value equals

the OCiR register value (see Figure 8). This

behaviour is the same in OPM or PWM mode.

When the timer clock is f

/4, f

/8 or in

CPU

external clock mode, OCFi and OCMPi are set

while the counter value equals the OCiR regis-

ter value plus 1 (see Figure 9).

4. The output compare functions can be used both

for generating external events on the OCMPi

pins even if the input capture mode is also

used.

5. The value in the 16-bit OCiR register and the

OLVi bit should be changed after each suc-

cessful comparison in order to control an output

waveform or establish a new elapsed timeout.

Figure 29. Output Compare Block Diagram

16 BIT FREE RUNNING

OC1E

CC1 CC0

OC2E

COUNTER

(Control Register 2) CR2

16-bit

(Control Register 1) CR1

OUTPUT COMPARE

CIRCUIT

Latch

1

FOLV2 FOLV1

OCIE

OLVL2

OLVL1

OCMP1

16-bit

Latch

2

OCMP2

OC1R Register

OCF1

OCF2

0

OC2R Register

(Status Register) SR

43/109

ST7263

16-BIT TIMER (Cont’d)

Figure 30. Output Compare Timing Diagram, f

=f

/2

CPU

TIMER

INTERNAL CPU CLOCK

TIMER CLOCK

COUNTER REGISTER

2ECF 2ED0 2ED1 2ED2

2ED3

2ED4

2ED3

OUTPUT COMPARE REGISTER i (OCRi)

OUTPUT COMPARE FLAG i (OCFi)

OCMPi PIN (OLVLi=1)

Figure 31. Output Compare Timing Diagram, f

=f

/4

CPU

TIMER

INTERNAL CPU CLOCK

TIMER CLOCK

2ECF 2ED0 2ED1 2ED2

2ED3

2ED4

2ED3

COUNTER REGISTER

OUTPUT COMPARE REGISTER i (OCRi)

COMPARE REGISTER i LATCH

OUTPUT COMPARE FLAG i (OCFi)

OCMPi PIN (OLVLi=1)

44/109

ST7263

16-BIT TIMER (Cont’d)

5.4.3.5 One Pulse Mode

Clearing the Input Capture interrupt request (i.e.

clearing the ICFi bit) is done in two steps:

One Pulse mode enables the generation of a

pulse when an external event occurs. This mode is

selected via the OPM bit in the CR2 register.

1. Reading the SR register while the ICFi bit is set.

2. An access (read or write) to the ICiLR register.

The One Pulse mode uses the Input Capture1

function and the Output Compare1 function.

The OC1R register value required for a specific

timing application can be calculated using the fol-

lowing formula:

Procedure:

t _*f

To use One Pulse mode:

CPU

- 5

OCiR Value =

1. Load the OC1R register with the value corre-

sponding to the length of the pulse (see the for-

mula in the opposite column).

PRESC

Where:

t

= Pulse period (in seconds)

2. Select the following in the CR1 register:

f

= CPU clock frequency (in hertz)

CPU

PRESC

– Using the OLVL1 bit, select the level to be ap-

plied to the OCMP1 pin after the pulse.

= Timer prescaler factor (2, 4 or 8 depend-

ing on the CC[1:0] bits, see Table 1)

– Using the OLVL2 bit, select the level to be ap-

plied to the OCMP1 pin during the pulse.

If the timer clock is an external clock the formula is:

OCiR = t f

-5

– Select the edge of the active transition on the

ICAP1 pin with the IEDG1 bit (the ICAP1 pin

must be configured as floating input).

* EXT

Where:

t

= Pulse period (in seconds)

3. Select the following in the CR2 register:

f

= External timer clock frequency (in hertz)

EXT

– Set the OC1E bit, the OCMP1 pin is then ded-

icated to the Output Compare 1 function.

– Set the OPM bit.

When the value of the counter is equal to the value

of the contents of the OC1R register, the OLVL1

bit is output on the OCMP1 pin (see Figure 10).

– Select the timer clock CC[1:0] (see Table 1).

One Pulse mode cycle

Notes:

1. The OCF1 bit cannot be set by hardware in

One Pulse mode but the OCF2 bit can generate

an Output Compare interrupt.

When

OCMP1 = OLVL2

event occurs

on ICAP1

Counter is reset

2. When the Pulse Width Modulation (PWM) and

One Pulse mode (OPM) bits are both set, the

PWM mode is the only active one.

to FFFCh

ICF1 bit is set

3. If OLVL1=OLVL2 a continuous signal will be

seen on the OCMP1 pin.

When

Counter

OCMP1 = OLVL1

= OC1R

4. The ICAP1 pin can not be used to perform input

capture. The ICAP2 pin can be used to perform

input capture (ICF2 can be set and IC2R can be

loaded) but the user must take care that the

counter is reset each time a valid edge occurs

on the ICAP1 pin and ICF1 can also generates

interrupt if ICIE is set.

Then, on a valid event on the ICAP1 pin, the coun-

ter is initialized to FFFCh and the OLVL2 bit is

loaded on the OCMP1 pin, the ICF1 bit is set and

the value FFFDh is loaded in the IC1R register.

Because the ICF1 bit is set when an active edge

occurs, an interrupt can be generated if the ICIE

bit is set.

5. When One Pulse mode is used OC1R is dedi-

cated to this mode. Nevertheless OC2R and

OCF2 can be used to indicate that a period of

time has elapsed but cannot generate an output

waveform because the OLVL2 level is dedi-

cated to One Pulse mode.

45/109

ST7263

16-BIT TIMER (Cont’d)

Figure 32. One Pulse Mode Timing Example

FFFC FFFD FFFE

COUNTER

2ED0 2ED1 2ED2

2ED3

FFFC FFFD

ICAP1

OLVL2

OLVL1

OLVL2

OCMP1

compare1

Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1

Figure 33. Pulse Width Modulation Mode Timing Example

2ED0 2ED1 2ED2

34E2 FFFC

FFFC FFFD FFFE

34E2

COUNTER

OCMP1

OLVL2

OLVL1

OLVL2

compare2

compare1

compare2

Note: OC1R=2ED0h, OC2R=34E2, OLVL1=0, OLVL2= 1

46/109

ST7263

16-BIT TIMER (Cont’d)

5.4.3.6 Pulse Width Modulation Mode

Pulse Width Modulation (PWM) mode enables the

generation of a signal with a frequency and pulse

length determined by the value of the OC1R and

OC2R registers.

The OCiR register value required for a specific tim-

ing application can be calculated using the follow-

ing formula:

t _*f

CPU

PRESC

- 5

OCiR Value =

The Pulse Width Modulation mode uses the com-

plete Output Compare 1 function plus the OC2R

register, and so these functions cannot be used

when the PWM mode is activated.

Where:

t

= Signal or pulse period (in seconds)

= CPU clock frequency (in hertz)

f

Procedure

CPU

= Timer prescaler factor (2, 4 or 8 depend-

ing on CC[1:0] bits, see Table 1)

To use Pulse Width Modulation mode:

PRESC

1. Load the OC2R register with the value corre-

sponding to the period of the signal using the

formula in the opposite column.

If the timer clock is an external clock the formula is:

OCiR = t f

-5

* EXT

2. Load the OC1R register with the value corre-

sponding to the period of the pulse if OLVL1=0

and OLVL2=1, using the formula in the oppo-

site column.

Where:

t

= Signal or pulse period (in seconds)

f

= External timer clock frequency (in hertz)

EXT

3. Select the following in the CR1 register:

– Using the OLVL1 bit, select the level to be ap-

plied to the OCMP1 pin after a successful

comparison with OC1R register.

The Output Compare 2 event causes the counter

to be initialized to FFFCh (See Figure 11)

Notes:

– Using the OLVL2 bit, select the level to be ap-

plied to the OCMP1 pin after a successful

comparison with OC2R register.

1. After a write instruction to the OCiHR register,

the output compare function is inhibited until the

OCiLR register is also written.

4. Select the following in the CR2 register:

2. The OCF1 and OCF2 bits cannot be set by

hardware in PWM mode, therefore the Output

Compare interrupt is inhibited.

– Set OC1E bit: the OCMP1 pin is then dedicat-

ed to the output compare 1 function.

– Set the PWM bit.

3. The ICF1 bit is set by hardware when the coun-

ter reaches the OC2R value and can produce a

timer interrupt if the ICIE bit is set and the I bit is

cleared.

– Select the timer clock (CC[1:0]) (see Table 1).

If OLVL1=1 and OLVL2=0, the length of the posi-

tive pulse is the difference between the OC2R and

OC1R registers.

4. In PWM mode the ICAP1 pin can not be used

to perform input capture because it is discon-

nected from the timer. The ICAP2 pin can be

used to perform input capture (ICF2 can be set

and IC2R can be loaded) but the user must

take care that the counter is reset after each

period and ICF1 can also generate an interrupt

if ICIE is set.

If OLVL1=OLVL2 a continuous signal will be seen

on the OCMP1 pin.

Pulse Width Modulation cycle

When

Counter

= OC1R

OCMP1 = OLVL1

5. When the Pulse Width Modulation (PWM) and

One Pulse mode (OPM) bits are both set, the

PWM mode is the only active one.

OCMP1 = OLVL2

When

Counter

= OC2R

Counter is reset

to FFFCh

ICF1 bit is set

47/109

ST7263

16-BIT TIMER (Cont’d)

5.4.4 Low Power Modes

Mode

Description

No effect on 16-bit Timer.

Timer interrupts cause the device to exit from WAIT mode.

WAIT

HALT

16-bit Timer registers are frozen.

In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous

count when the MCU is woken up by an interrupt with “exit from HALT mode” capability or from the counter

reset value when the MCU is woken up by a RESET.

If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is armed. Consequent-

ly, when the MCU is woken up by an interrupt with “exit from HALT mode” capability, the ICFi bit is set, and

the counter value present when exiting from HALT mode is captured into the ICiR register.

5.4.5 Interrupts

Enable

Control from

Bit

Exit

from

Halt

Event

Flag

Interrupt Event

Wait

Yes

Input Capture 1 event/Counter reset in PWM mode

Input Capture 2 event

ICF1

ICF2

No

ICIE

Output Compare 1 event (not available in PWM mode)

Output Compare 2 event (not available in PWM mode)

Timer Overflow event

OCF1

OCF2

TOF

OCIE

TOIE

Note: The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts chap-

ter). These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt

mask in the CC register is reset (RIM instruction).

5.4.6 Summary of Timer modes

AVAILABLE RESOURCES

MODES

Input Capture 1

Input Capture 2

Yes

Output Compare 1 Output Compare 2

Input Capture (1 and/or 2)

Output Compare (1 and/or 2)

One Pulse mode

Yes

No

Yes

No

Yes

1)

3)

2)

Not Recommended

Partially

No

PWM Mode

No

1)

2)

3)

See note 4 in Section 0.1.3.5 One Pulse Mode

See note 5 in Section 0.1.3.5 One Pulse Mode

See note 4 in Section 0.1.3.6 Pulse Width Modulation Mode

48/109

ST7263

16-BIT TIMER (Cont’d)

5.4.7 Register Description

Bit 4 = FOLV2 Forced Output Compare 2.

This bit is set and cleared by software.

0: No effect on the OCMP2 pin.

1:Forces the OLVL2 bit to be copied to the

OCMP2 pin, if the OC2E bit is set and even if

there is no successful comparison.

Each Timer is associated with three control and

status registers, and with six pairs of data registers

(16-bit values) relating to the two input captures,

the two output compares, the counter and the al-

ternate counter.

Bit 3 = FOLV1 Forced Output Compare 1.

This bit is set and cleared by software.

0: No effect on the OCMP1 pin.

CONTROL REGISTER 1 (CR1)

Read/Write

1: Forces OLVL1 to be copied to the OCMP1 pin, if

the OC1E bit is set and even if there is no suc-

cessful comparison.

Reset Value: 0000 0000 (00h)

7

0

ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1

Bit 2 = OLVL2 Output Level 2.

This bit is copied to the OCMP2 pin whenever a

successful comparison occurs with the OC2R reg-

ister and OCxE is set in the CR2 register. This val-

ue is copied to the OCMP1 pin in One Pulse mode

and Pulse Width Modulation mode.

Bit 7 = ICIE Input Capture Interrupt Enable.

0: Interrupt is inhibited.

1: A timer interrupt is generated whenever the

ICF1 or ICF2 bit of the SR register is set.

Bit 1 = IEDG1 Input Edge 1.

Bit 6 = OCIE Output Compare Interrupt Enable.

0: Interrupt is inhibited.

1: A timer interrupt is generated whenever the

OCF1 or OCF2 bit of the SR register is set.

This bit determines which type of level transition

on the ICAP1 pin will trigger the capture.

0: A falling edge triggers the capture.

1: A rising edge triggers the capture.

Bit 5 = TOIE Timer Overflow Interrupt Enable.

0: Interrupt is inhibited.

1: A timer interrupt is enabled whenever the TOF

bit of the SR register is set.

Bit 0 = OLVL1 Output Level 1.

The OLVL1 bit is copied to the OCMP1 pin when-

ever a successful comparison occurs with the

OC1R register and the OC1E bit is set in the CR2

register.

49/109

ST7263

16-BIT TIMER (Cont’d)

CONTROL REGISTER 2 (CR2)

Read/Write

Bit 4 = PWM Pulse Width Modulation.

0: PWM mode is not active.

1: PWM mode is active, the OCMP1 pin outputs a

programmable cyclic signal; the length of the

pulse depends on the value of OC1R register;

the period depends on the value of OC2R regis-

ter.

Reset Value: 0000 0000 (00h)

7

0

OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG

Bits 3:2 = CC[1:0] Clock Control.

Bit 7 = OC1E Output Compare 1 Pin Enable.

This bit is used only to output the signal from the

timer on the OCMP1 pin (OLV1 in Output Com-

pare mode, both OLV1 and OLV2 in PWM and

one-pulse mode). Whatever the value of the OC1E

bit, the internal Output Compare 1 function of the

timer remains active.

0: OCMP1 pin alternate function disabled (I/O pin

free for general-purpose I/O).

1: OCMP1 pin alternate function enabled.

The timer clock mode depends on these bits:

Table 16. Clock Control Bits

Timer Clock

f_CPU/ 4

CC1

CC0

0

1

0

1

0

f_CPU/ 2

f_CPU/ 8

External Clock (where

available)

1

Bit 6 = OC2E Output Compare 2 Pin Enable.

This bit is used only to output the signal from the

timer on the OCMP2 pin (OLV2 in Output Com-

pare mode). Whatever the value of the OC2E bit,

the internal Output Compare 2 function of the timer

remains active.

0: OCMP2 pin alternate function disabled (I/O pin

free for general-purpose I/O).

1: OCMP2 pin alternate function enabled.

Note: If the external clock pin is not available, pro-

gramming the external clock configuration stops

the counter.

Bit 1 = IEDG2 Input Edge 2.

This bit determines which type of level transition

on the ICAP2 pin will trigger the capture.

0: A falling edge triggers the capture.

1: A rising edge triggers the capture.

Bit 5 = OPM One Pulse mode.

0: One Pulse mode is not active.

Bit 0 = EXEDG External Clock Edge.

1: One Pulse mode is active, the ICAP1 pin can be

used to trigger one pulse on the OCMP1 pin; the

active transition is given by the IEDG1 bit. The

length of the generated pulse depends on the

contents of the OC1R register.

This bit determines which type of level transition

on the external clock pin (EXTCLK) will trigger the

counter register.

0: A falling edge triggers the counter register.

1: A rising edge triggers the counter register.

50/109

ST7263

16-BIT TIMER (Cont’d)

STATUS REGISTER (SR)

Read Only

INPUT CAPTURE 1 HIGH REGISTER (IC1HR)

Read Only

Reset Value: Undefined

Reset Value: 0000 0000 (00h)

The three least significant bits are not used.

7

This is an 8-bit read only register that contains the

high part of the counter value (transferred by the

input capture 1 event).

0

ICF1 OCF1 TOF ICF2 OCF2

0

7

0

MSB

LSB

Bit 7 = ICF1 Input Capture Flag 1.

0: No input capture (reset value).

1: An input capture has occurred on the ICAP1 pin

or the counter has reached the OC2R value in

PWM mode. To clear this bit, first read the SR

register, then read or write the low byte of the

IC1R (IC1LR) register.

INPUT CAPTURE 1 LOW REGISTER (IC1LR)

Read Only

Reset Value: Undefined

This is an 8-bit read only register that contains the

low part of the counter value (transferred by the in-

put capture 1 event).

Bit 6 = OCF1 Output Compare Flag 1.

0: No match (reset value).

1: The content of the free running counter matches

the content of the OC1R register. To clear this

bit, first read the SR register, then read or write

the low byte of the OC1R (OC1LR) register.

7

0

MSB

LSB

Bit 5 = TOF Timer Overflow Flag.

0: No timer overflow (reset value).

1: The free running counter has rolled over from

FFFFh to 0000h. To clear this bit, first read the

SR register, then read or write the low byte of

the CR (CLR) register.

OUTPUT COMPARE

(OC1HR)

1

HIGH REGISTER

Read/Write

Reset Value: 1000 0000 (80h)

This is an 8-bit register that contains the high part

of the value to be compared to the CHR register.

Note: Reading or writing the ACLR register does

not clear TOF.

7

0

MSB

LSB

Bit 4 = ICF2 Input Capture Flag 2.

0: No input capture (reset value).

1: An input capture has occurred on the ICAP2

pin. To clear this bit, first read the SR register,

then read or write the low byte of the IC2R

(IC2LR) register.

OUTPUT COMPARE

(OC1LR)

1

LOW REGISTER

Read/Write

Reset Value: 0000 0000 (00h)

Bit 3 = OCF2 Output Compare Flag 2.

0: No match (reset value).

This is an 8-bit register that contains the low part of

the value to be compared to the CLR register.

1: The content of the free running counter matches

the content of the OC2R register. To clear this

bit, first read the SR register, then read or write

the low byte of the OC2R (OC2LR) register.

7

0

MSB

LSB

Bit 2-0 = Reserved, forced by hardware to 0.

51/109

ST7263

16-BIT TIMER (Cont’d)

OUTPUT COMPARE

(OC2HR)

2

HIGH REGISTER

ALTERNATE COUNTER HIGH REGISTER

(ACHR)

Read/Write

Reset Value: 1000 0000 (80h)

Read Only

Reset Value: 1111 1111 (FFh)

This is an 8-bit register that contains the high part

of the value to be compared to the CHR register.

This is an 8-bit register that contains the high part

of the counter value.

7

0

7

0

MSB

LSB

MSB

LSB

OUTPUT COMPARE

(OC2LR)

2

LOW REGISTER

ALTERNATE COUNTER LOW REGISTER

(ACLR)

Read/Write

Reset Value: 0000 0000 (00h)

Read Only

Reset Value: 1111 1100 (FCh)

This is an 8-bit register that contains the low part of

the value to be compared to the CLR register.

This is an 8-bit register that contains the low part of

the counter value. A write to this register resets the

counter. An access to this register after an access

to SR register does not clear the TOF bit in SR

register.

7

0

MSB

LSB

7

0

COUNTER HIGH REGISTER (CHR)

MSB

LSB

Read Only

Reset Value: 1111 1111 (FFh)

INPUT CAPTURE 2 HIGH REGISTER (IC2HR)

This is an 8-bit register that contains the high part

of the counter value.

Read Only

Reset Value: Undefined

7

0

This is an 8-bit read only register that contains the

high part of the counter value (transferred by the

Input Capture 2 event).

MSB

LSB

7

0

MSB

LSB

COUNTER LOW REGISTER (CLR)

Read Only

Reset Value: 1111 1100 (FCh)

This is an 8-bit register that contains the low part of

the counter value. A write to this register resets the

counter. An access to this register after accessing

the SR register clears the TOF bit.

INPUT CAPTURE 2 LOW REGISTER (IC2LR)

Read Only

Reset Value: Undefined

This is an 8-bit read only register that contains the

low part of the counter value (transferred by the In-

put Capture 2 event).

7

0

MSB

LSB

7

0

MSB

LSB

52/109

ST7263

16-BIT TIMER (Cont’d)

Table 17. 16-Bit Timer Register Map and Reset Values

Address

(Hex.)

Register

Label

7

6

5

4

3

2

1

0

CR2

OC1E

0

OC2E

OPM

0

PWM

CC1

CC0

IEDG2

EXEDG

11

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

Reset Value

CR1

0

OCIE

0

FOLV2

0

FOLV1

0

ICIE

0

TOIE

0

OLVL2

IEDG1

OLVL1

Reset Value

SR

0

ICF1

0

OCF1

0

TOF

0

ICF2

0

OCF2

0

Reset Value

IC1HR

MSB

LSB

Reset Value

IC1LR

Reset Value

OC1HR

MSB

1

-

0

-

0

-

0

-

0

-

0

-

0

LSB

0

Reset Value

OC1LR

MSB

0

-

0

-

0

-

0

-

0

-

0

-

0

LSB

0

Reset Value

CHR

MSB

1

-

1

-

1

-

1

-

1

-

1

-

1

LSB

1

Reset Value

CLR

MSB

1

-

1

-

1

-

1

-

1

-

1

-

0

LSB

0

Reset Value

ACHR

MSB

1

-

1

-

1

-

1

-

1

-

1

-

1

LSB

1

Reset Value

ACLR

MSB

1

-

1

-

1

-

1

-

1

-

1

-

0

LSB

0

Reset Value

IC2HR

MSB

LSB

Reset Value

IC2LR

Reset Value

OC2HR

MSB

1

-

0

-

0

-

0

-

0

-

0

-

0

LSB

0

Reset Value

OC2LR

MSB

0

-

0

-

0

-

0

-

0

-

0

-

0

LSB

0

Reset Value

53/109

ST7263

5.5 SERIAL COMMUNICATIONS INTERFACE (SCI)

5.5.1 Introduction

5.5.3 General Description

The Serial Communications Interface (SCI) offers

a flexible means of full-duplex data exchange with

external equipment requiring an industry standard

NRZ asynchronous serial data format.

The interface is externally connected to another

device by two pins (see Figure 1):

– TDO: Transmit Data Output. When the transmit-

ter is disabled, the output pin returns to its I/O

port configuration. When the transmitter is ena-

bled and nothing is to be transmitted, the TDO

pin is at high level.

5.5.2 Main Features

■ Full duplex, asynchronous communications

■ NRZ standard format (Mark/Space)

– RDI: Receive Data Input is the serial data input.

Oversampling techniques are used for data re-

covery by discriminating between valid incoming

data and noise.

■ Independently programmable transmit and

receive baud rates up to 250K baud.

■ Programmable data word length (8 or 9 bits)

■ Receive buffer full, Transmit buffer empty and

Through this pins, serial data is transmitted and re-

ceived as frames comprising:

End of Transmission flags

■ Two receiver wake-up modes:

– Address bit (MSB)

– An Idle Line prior to transmission or reception

– A start bit

– Idle line

– A data word (8 or 9 bits) least significant bit first

– A Stop bit indicating that the frame is complete.

■ Mutingfunctionformultiprocessorconfigurations

■ Separate enable bits for Transmitter and

Receiver

■ Three error detection flags:

– Overrun error

– Noise error

– Frame error

■ Five interrupt sources with flags:

– Transmit data register empty

– Transmission complete

– Receive data register full

– Idle line received

– Overrun error detected

54/109

ST7263

SERIAL COMMUNICATIONS INTERFACE (Cont’d)

Figure 34. SCI Block Diagram

Write

Read

(Data Register) DR

Received Data Register (RDR)

Received Shift Register

Transmit Data Register (TDR)

TDO

Transmit Shift Register

RDI

CR1

R8

-

T8

-

M

WAKE

-

WAKE

TRANSMIT

UP

RECEIVER

CLOCK

RECEIVER

CONTROL

UNIT

CR2

SR

TIE TCIE RIE ILIE TE RE RWU SBK

TDRE TC RDRF

IDLE OR NF FE

-

SCI

INTERRUPT

CONTROL

TRANSMITTER

CLOCK

Transmitter Rate

Control

f

CPU

/PR

/2

/16

BRR

SCP1

SCT2

SCT1SCT0SCR2 SCR1SCR0

SCP0

Receiver Rate

Control

BAUD RATE GENERATOR

55/109

ST7263

SERIAL COMMUNICATIONS INTERFACE (Cont’d)

5.5.4 Functional Description

The TDO pin is in low state during the start bit.

The TDO pin is in high state during the stop bit.

The block diagram of the Serial Control Interface,

is shown in Figure 1. It contains 4 dedicated regis-

ters:

An Idle character is interpreted as an entire frame

of “1”s followed by the start bit of the next frame

which contains data.

– Two control registers (CR1 & CR2)

– A status register (SR)

A Break character is interpreted on receiving “0”s

for some multiple of the frame period. At the end of

the last break frame the transmitter inserts an ex-

tra “1” bit to acknowledge the start bit.

– A baud rate register (BRR)

Refer to the register descriptions in Section 0.1.7

for the definitions of each bit.

Transmission and reception are driven by their

own baud rate generator.

5.5.4.1 Serial Data Format

Word length may be selected as being either 8 or 9

bits by programming the M bit in the CR1 register

(see Figure 1).

Figure 35. Word Length Programming

9-bit Word length (M bit is set)

Possible

Next Data Frame

Parity

Data Frame

Start

Bit

Stop

Bit

Bit2

Bit6

Bit1

Bit3

Bit5

Bit8

Bit0

Bit4

Bit7

Bit

Start

Bit

Idle Frame

Start

Bit

Extra

’1’

Break Frame

8-bit Word length (M bit is reset)

Possible

Parity

Next Data Frame

Data Frame

Start

Bit

Stop

Bit

Bit2

Bit1

Bit3

Bit5

Bit6

Bit0

Bit4

Bit7

Bit

Start

Bit

Idle Frame

Start

Bit

Extra

’1’

Break Frame

56/109

ST7263

SERIAL COMMUNICATIONS INTERFACE (Cont’d)

5.5.4.2 Transmitter

When a frame transmission is complete (after the

stop bit or after the break frame) the TC bit is set

and an interrupt is generated if the TCIE is set and

the I bit is cleared in the CC register.

The transmitter can send data words of either 8 or

9 bits depending on the M bit status. When the M

bit is set, word length is 9 bits and the 9th bit (the

MSB) has to be stored in the T8 bit in the CR1 reg-

ister.

The following software sequence is always to clear

the TC bit:

1. An access to the SR register

Character Transmission

2. A write to the DR register

During an SCI transmission, data shifts out least

significant bit first on the TDO pin. In this mode,

the DR register consists of a buffer (TDR) between

the internal bus and the transmit shift register (see

Figure 1).

Note: The TDRE and TC bits are cleared by the

same software sequence.

Break Characters

Setting the SBK bit loads the shift register with a

break character. The break frame length depends

on the M bit (see Figure 2).

Procedure

– Select the M bit to define the word length.

As long as the SBK bit is set, the SCI sends break

frames to the TDO pin. After clearing this bit by

software, the SCI inserts a logic 1 bit at the end of

the last break frame to guarantee the recognition

of the start bit of the next frame.

– Select the desired baud rate using the BRR reg-

ister.

– Set the TE bit to assign the TDO pin to the alter-

nate function and to send a idle frame as first

transmission.

Idle Characters

– Access the SR register and write the data to

send in the DR register (this sequence clears the

TDRE bit). Repeat this sequence for each data to

be transmitted.

Setting the TE bit drives the SCI to send an idle

frame before the first data frame.

Clearing and then setting the TE bit during a trans-

mission sends an idle frame after the current word.

The following software sequence is always to clear

the TDRE bit:

1. An access to the SR register

2. A write to the DR register

Note: Resetting and setting the TE bit causes the

data in the TDR register to be lost. Therefore the

best time to toggle the TE bit is when the TDRE bit

is set, i.e. before writing the next byte in the DR.

The TDRE bit is set by hardware and it indicates

that:

– The TDR register is empty.

– The data transfer is beginning.

– The next data can be written in the DR register

without overwriting the previous data.

This flag generates an interrupt if the TIE bit is set

and the I bit is cleared in the CC register.

When a transmission is taking place, a write in-

struction to the DR register stores the data in the

TDR register which is copied in the shift register at

the end of the current transmission.

When no transmission is taking place, a write in-

struction to the DR register places the data directly

in the shift register, the data transmission starts,

and the TDRE bit is immediately set.

57/109

ST7263

SERIAL COMMUNICATIONS INTERFACE (Cont’d)

5.5.4.3 Receiver

Overrun Error

An overrun error occurs when a character is re-

ceived when RDRF has not been reset. Data can

not be transferred from the shift register to the

TDR register as long as the RDRF bit is not

cleared.

The SCI can receive data words of either 8 or 9

bits. When the M bit is set, word length is 9 bits

and the MSB is stored in the R8 bit in the CR1 reg-

ister.

Character reception

When a overrun error occurs:

– The OR bit is set.

During a SCI reception, data shifts in least signifi-

cant bit first through the RDI pin. In this mode, the

DR register consists of a buffer (RDR) between

the internal bus and the received shift register (see

Figure 1).

– The RDR content will not be lost.

– The shift register will be overwritten.

– An interrupt is generated if the RIE bit is set and

the I bit is cleared in the CC register.

Procedure

– Select the M bit to define the word length.

The OR bit is reset by an access to the SR register

followed by a DR register read operation.

– Select the desired baud rate using the BRR reg-

ister.

Noise Error

– Set the RE bit to enable the receiverto begin

searching for a start bit.

Oversampling techniques are used for data recov-

ery by discriminating between valid incoming data

and noise.

When a character is received:

– The RDRF bit is set. It indicates that the content

of the shift register is transferred to the RDR.

When noise is detected in a frame:

– The NF is set at the rising edge of the RDRF bit.

– An interrupt is generated if the RIE bit is set and

the I bit is cleared in the CC register.

– Data is transferred from the Shift register to the

DR register.

– The error flags can be set if a frame error, noise

or an overrun error has been detected during re-

ception.

– No interrupt is generated. However this bit rises

at the same time as the RDRF bit which itself

generates an interrupt.

Clearing the RDRF bit is performed by the following

software sequence done by:

The NF bit is reset by a SR register read operation

followed by a DR register read operation.

1. An access to the SR register

2. A read to the DR register.

Framing Error

A framing error is detected when:

The RDRF bit must be cleared before the end of the

reception of the next character to avoid an overrun

error.

– The stop bit is not recognized on reception at the

expected time, following either a de-synchroni-

zation or excessive noise.

Break Character

– A break is received.

When a break character is received, the SCI han-

dles it as a framing error.

When the framing error is detected:

– The FE bit is set by hardware

Idle Character

– Data is transferred from the Shift register to the

DR register.

When a idle frame is detected, there is the same

procedure as a data received character plus an in-

terrupt if the ILIE bit is set and the I bit is cleared in

the CC register.

– No interrupt is generated. However this bit rises

at the same time as the RDRF bit which itself

generates an interrupt.

The FE bit is reset by a SR register read operation

followed by a DR register read operation.

58/109

ST7263

SERIAL COMMUNICATIONS INTERFACE (Cont’d)

5.5.4.4 Baud Rate Generation

should actively receive the full message contents,

thus reducing redundant SCI service overhead for

all non addressed receivers.

The baud rates for the receiver and transmitter (Rx

and Tx) are set independently and calculated as

follows:

The non addressed devices may be placed in

sleep mode by means of the muting function.

f

CPU

Setting the RWU bit by software puts the SCI in

sleep mode:

Rx =

Tx =

(32 PR) RR

(32 PR) TR

*

All the reception status bits can not be set.

All the receive interrupt are inhibited.

with:

PR = 1, 3, 4 or 13 (see SCP0 & SCP1 bits)

TR = 1, 2, 4, 8, 16, 32, 64,128

A muted receiver may be awakened by one of the

following two ways:

(see SCT0, SCT1 & SCT2 bits)

RR = 1, 2, 4, 8, 16, 32, 64,128

– by Idle Line detection if the WAKE bit is reset,

– by Address Mark detection if the WAKE bit is set.

(see SCR0,SCR1 & SCR2 bits)

All these bits are in the BRR register.

The Receiver wakes-up by Idle Line detection

when the Receive line has recognised an Idle

Frame. Then the RWU bit is reset by hardware but

the IDLE bit is not set.

Example: If f

is 8 MHz and if PR=13 and

CPU

TR=RR=1, the transmit and receive baud rates are

19200 bauds.

The Receiver wakes-up by Address Mark detec-

tion when it received a “1” as the most significant

bit of a word, thus indicating that the message is

an address. The reception of this particular word

wakes up the receiver, resets the RWU bit and

sets the RDRF bit, which allows the receiver to re-

ceive this word normally and to use it as an ad-

dress word.

Note: The baud rate registers MUST NOT be

changed while the transmitter or the receiver is en-

abled.

5.5.4.5 Receiver Muting and Wake-up Feature

In multiprocessor configurations it is often desira-

ble that only the intended message recipient

59/109

ST7263

SERIAL COMMUNICATIONS INTERFACE (Cont’d)

5.5.5 Low Power Modes

Mode

Description

No effect on SCI.

WAIT

SCI interrupts exit from Wait mode.

SCI registers are frozen.

HALT

In Halt mode, the SCI stops transmitting/receiving until Halt mode is exited.

5.5.6 Interrupts

Enable

Control from

Bit

Exit

from

Halt

Event

Flag

Interrupt Event

Wait

Yes

Transmit Data Register Empty

Transmission Complete

TDRE

TC

TIE

No

TCIE

Received Data Ready to be Read

Overrrun Error Detected

Idle Line Detected

RDRF

OR

RIE

ILIE

IDLE

The SCI interrupt events are connected to the

same interrupt vector (see Interrupts chapter).

rupt mask in the CC register is reset (RIM instruc-

tion).

These events generate an interrupt if the corre-

sponding Enable Control Bit is set and the inter-

60/109

ST7263

SERIAL COMMUNICATIONS INTERFACE (Cont’d)

5.5.7 Register Description

Note: The IDLE bit will not be set again until the

RDRF bit has been set itself (i.e. a new idle line oc-

curs). This bit is not set by an idle line when the re-

ceiver wakes up from wake-up mode.

STATUS REGISTER (SR)

Read Only

Reset Value: 1100 0000 (C0h)

Bit 3 = OR Overrun error.

7

0

This bit is set by hardware when the word currently

being received in the shift register is ready to be

transferred into the RDR register while RDRF=1.

An interrupt is generated if RIE=1 in the CR2 reg-

ister. It is cleared by hardware when RE=0 by a

software sequence (an access to the SR register

followed by a read to the DR register).

0: No Overrun error

TDRE

TC

RDRF IDLE

OR

NF

FE

Bit 7 = TDRE Transmit data register empty.

This bit is set by hardware when the content of the

TDR register has been transferred into the shift

register. An interrupt is generated if TIE =1 in the

CR2 register. It is cleared by a software sequence

(an access to the SR register followed by a write to

the DR register).

1: Overrun error is detected

Note: When this bit is set the RDR register content

will not be lost but the shift register will be overwrit-

ten.

0: Data is not transferred to the shift register

1: Data is transferred to the shift register

Note: data will not be transferred to the shift regis-

ter as long as the TDRE bit is not reset.

Bit 2 = NF Noise flag.

This bit is set by hardware when noise is detected

on a received frame. It is cleared by hardware

when RE=0 by a software sequence (an access to

the SR register followed by a read to the DR regis-

ter).

0: No noise is detected

1: Noise is detected

Bit 6 = TC Transmission complete.

This bit is set by hardware when transmission of a

frame containing Data, a Preamble or a Break is

complete. An interrupt is generated if TCIE=1 in

the CR2 register. It is cleared by a software se-

quence (an access to the SR register followed by a

write to the DR register).

Note: This bit does not generate interrupt as it ap-

pears at the same time as the RDRF bit which it-

self generates an interrupt.

0: Transmission is not complete

1: Transmission is complete

Bit 1 = FE Framing error.

Bit 5 = RDRF Received data ready flag.

This bit is set by hardware when a de-synchroniza-

tion, excessive noise or a break character is de-

tected. It is cleared by hardware when RE=0 by a

software sequence (an access to the SR register

followed by a read to the DR register).

0: No Framing error is detected

1: Framing error or break character is detected

This bit is set by hardware when the content of the

RDR register has been transferred into the DR

register. An interrupt is generated if RIE=1 in the

CR2 register. It is cleared by hardware when

RE=0 or by a software sequence (an access to the

SR register followed by a read to the DR register).

0: Data is not received

Note: This bit does not generate interrupt as it ap-

pears at the same time as the RDRF bit which it-

self generates an interrupt. If the word currently

being transferred causes both frame error and

overrun error, it will be transferred and only the OR

bit will be set.

1: Received data is ready to be read

Bit 4 = IDLE Idle line detect.

This bit is set by hardware when an Idle Line is de-

tected. An interrupt is generated if ILIE=1 in the

CR2 register. It is cleared by hardware when

RE=0 by a software sequence (an access to the

SR register followed by a read to the DR register).

0: No Idle Line is detected

Bit 0 = Reserved, forced by hardware to 0.

1: Idle Line is detected

61/109

ST7263

SERIAL COMMUNICATIONS INTERFACE (Cont’d)

CONTROL REGISTER 1 (CR1)

Read/Write

0: interrupt is inhibited

1: An SCI interrupt is generated whenever TC=1 in

the SR register

Reset Value: Undefined

Bit 5 = RIE Receiver interrupt enable.

This bit is set and cleared by software.

0: interrupt is inhibited

1: An SCI interrupt is generated whenever OR=1

or RDRF=1 in the SR register

7

0

R8

T8

0

M

WAKE

0

Bit 7 = R8 Receive data bit 8.

This bit is used to store the 9th bit of the received

word when M=1.

Bit 4 = ILIE Idle line interrupt enable.

This bit is set and cleared by software.

0: interrupt is inhibited

1: An SCI interrupt is generated whenever IDLE=1

in the SR register.

Bit 6 = T8 Transmit data bit 8.

This bit is used to store the 9th bit of the transmit-

ted word when M=1.

Bit 3 = TE Transmitter enable.

This bit enables the transmitter and assigns the

TDO pin to the alternate function. It is set and

cleared by software.

Bit 5 = Reserved, forced by hardware to 0.

0: Transmitter is disabled, the TDO pin is back to

the I/O port configuration.

1: Transmitter is enabled

Bit 4 = M Word length.

This bit determines the data length. It is set or

cleared by software.

0: 1 Start bit, 8 Data bits, 1 Stop bit

1: 1 Start bit, 9 Data bits, 1 Stop bit

Note: During transmission, a “0” pulse on the TE

bit (“0” followed by “1”) sends a preamble after the

current word.

Bit 3 = WAKE Wake-Up method.

This bit determines the SCI Wake-Up method, it is

set or cleared by software.

0: Idle Line

Bit 2 = RE Receiver enable.

This bit enables the receiver. It is set and cleared

by software.

0: Receiver is disabled, it resets the RDRF, IDLE,

OR, NF and FE bits of the SR register.

1: Receiver is enabled and begins searching for a

start bit.

1: Address Mark

Bits 2:0 = Reserved, forced by hardware to 0.

Bit 1 = RWU Receiver wake-up.

CONTROL REGISTER 2 (CR2)

Read/Write

This bit determines if the SCI is in mute mode or

not. It is set and cleared by software and can be

cleared by hardware when a wake-up sequence is

recognized.

Reset Value: 0000 0000 (00h)

7

0

0: Receiver in active mode

1: Receiver in mute mode

TIE

TCIE

RIE

ILIE

TE

RE

RWU

SBK

Bit 0 = SBK Send break.

This bit set is used to send break characters. It is

set and cleared by software.

0: No break character is transmitted

1: Break characters are transmitted

Bit 7 = TIE Transmitter interrupt enable.

This bit is set and cleared by software.

0: interrupt is inhibited

1: An SCI interrupt is generated whenever

TDRE=1 in the SR register.

Note: If the SBK bit is set to “1” and then to “0”, the

transmitter will send a BREAK word at the end of

the current word.

Bit 6 = TCIE Transmission complete interrupt ena-

ble

This bit is set and cleared by software.

62/109

ST7263

SERIAL COMMUNICATIONS INTERFACE (Cont’d)

DATA REGISTER (DR)

Bits 5:3 = SCT[2:0] SCI Transmitter rate divisor

Read/Write

These 3 bits, in conjunction with the SCP1 & SCP0

bits, define the total division applied to the bus

clock to yield the transmit rate clock in convention-

al Baud Rate Generator mode.

Reset Value: Undefined

Contains the Received or Transmitted data char-

acter, depending on whether it is read from or writ-

ten to.

TR Dividing Factor

SCT2

SCT1

SCT0

1

2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

7

0

4

DR7

DR6

DR5

DR4

DR3

DR2

DR1

DR0

8

16

32

64

128

The Data register performs a double function (read

and write) since it is composed of two registers,

one for transmission (TDR) and one for reception

(RDR).

The TDR register provides the parallel interface

between the internal bus and the output shift reg-

ister (see Figure 1).

The RDR register provides the parallel interface

between the input shift register and the internal

bus (see Figure 1).

Bits 2:0 = SCR[2:0] SCI Receiver rate divisor.

These 3 bits, in conjunction with the SCP1 & SCP0

bits, define the total division applied to the bus

clock to yield the receive rate clock in conventional

Baud Rate Generator mode.

BAUD RATE REGISTER (BRR)

Read/Write

RR Dividing Factor

SCR2

SCR1

SCR0

Reset Value: 00xx xxxx (XXh)

1

2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

7

0

4

SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0

8

16

32

64

128

Bits 7:6= SCP[1:0] First SCI Prescaler

These 2 prescaling bits allow several standard

clock division ranges:

PR Prescaling Factor

SCP1

SCP0

1

3

0

1

0

1

0

1

4

13

63/109

ST7263

SERIAL COMMUNICATIONS INTERFACE (Cont’d)

Table 18. SCI Register Map and Reset Values

Address

(Hex.)

Register

Label

7

6

5

4

3

2

1

0

20

21

22

23

24

SR

TDRE

TC

1

RDRF

IDLE

0

OR

0

NF

0

FE

0

Reset Value

DR

1

DR7

x

0

DR5

x

DR6

x

DR4

x

DR3

x

DR2

x

DR1

x

DR0

x

Reset Value

BRR

SCP1

0

SCP0

SCT2

SCT1

SCT0

SCR2

SCR1

SCR0

Reset Value

CR1

0

T8

x

0

x

M

x

WAKE

x

0

x

0

R8

x

0

Reset Value

CR2

0

x

0

TIE

0

TCIE

0

RIE

0

ILIE

0

TE

0

RE

0

RWU

0

SBK

0

Reset Value

64/109

ST7263

5.6 USB INTERFACE (USB)

5.6.1 Introduction

For general information on the USB, refer to the

“Universal Serial Bus Specifications” document

available at http//:www.usb.org.

The USB Interface implements a low-speed func-

tion interface between the USB and the ST7 mi-

crocontroller. It is a highly integrated circuit which

includes the transceiver, 3.3 voltage regulator, SIE

and DMA. No external components are needed

apart from the external pull-up on USBDM for low

speed recognition by the USB host. The use of

DMA architecture allows the endpoint definition to

be completely flexible. Endpoints can be config-

ured by software as in or out.

Serial Interface Engine

The SIE (Serial Interface Engine) interfaces with

the USB, via the transceiver.

The SIE processes tokens, handles data transmis-

sion/reception, and handshaking as required by

the USB standard. It also performs frame format-

ting, including CRC generation and checking.

Endpoints

5.6.2 Main Features

The Endpoint registers indicate if the microcontrol-

ler is ready to transmit/receive, and how many

bytes need to be transmitted.

■ USB Specification Version 1.1 Compliant

■ Supports Low-Speed USB Protocol

■ Two or Three Endpoints (including default one)

depending on the device (see device feature list

and register map)

DMA

When a token for a valid Endpoint is recognized by

the USB interface, the related data transfer takes

place, using DMA. At the end of the transaction, an

interrupt is generated.

■ CRC generation/checking, NRZI encoding/

decoding and bit-stuffing

■ USB Suspend/Resume operations

■ DMA Data transfers

Interrupts

By reading the Interrupt Status register, applica-

tion software can know which USB event has oc-

curred.

■ On-Chip 3.3V Regulator

■ On-Chip USB Transceiver

5.6.3 Functional Description

The block diagram in Figure 1, gives an overview

of the USB interface hardware.

Figure 36. USB Block Diagram

6 MHz

ENDPOINT

CPU

REGISTERS

USBDM

Address,

Transceiver

SIE

DMA

USBDP

data buses

and interrupts

3.3V

INTERRUPT

REGISTERS

USBVCC

USBGND

Voltage

Regulator

MEMORY

65/109

ST7263

USB INTERFACE (Cont’d)

5.6.4 Register Description

DMA ADDRESS REGISTER (DMAR)

Read / Write

INTERRUPT/DMA REGISTER (IDR)

Read / Write

Reset Value: xxxx 0000 (x0h)

Reset Value: Undefined

7

0

7

0

DA7

DA6

EP1

EP0 CNT3 CNT2 CNT1 CNT0

DA15 DA14 DA13 DA12 DA11 DA10 DA9

DA8

Bits 7:6 = DA[7:6] DMA address bits 7-6.

Software must reset these bits. See the descrip-

tion of the DMAR register and Figure 2.

Bits 7:0=DA[15:8] DMA address bits 15-8.

Software must write the start address of the DMA

memory area whose most significant bits are given

by DA15-DA6. The remaining 6 address bits are

set by hardware. See the description of the IDR

register and Figure 2.

Bits 5:4 = EP[1:0] Endpoint number (read-only).

These bits identify the endpoint which required at-

tention.

00: Endpoint 0

01: Endpoint 1

10: Endpoint 2

When a CTR interrupt occurs (see register ISTR)

the software should read the EP bits to identify the

endpoint which has sent or received a packet.

Bits 3:0 = CNT[3:0] Byte count (read only).

This field shows how many data bytes have been

received during the last data reception.

Note: Not valid for data transmission.

Figure 37. DMA Buffers

101111

Endpoint 2 TX

Endpoint 2 RX

101000

100111

100000

011111

Endpoint 1 TX

Endpoint 1 RX

011000

010111

010000

001111

Endpoint 0 TX

Endpoint 0 RX

001000

000111

DA15-6,000000

000000

66/109

ST7263

USB INTERFACE (Cont’d)

PID REGISTER (PIDR)

Read only

INTERRUPT STATUS REGISTER (ISTR)

Read / Write

Reset Value: xx00 0000 (x0h)

Reset Value: 0000 0000 (00h)

7

0

7

0

RX_

SEZ

SUSP DOVR CTR ERR IOVR ESUSP RESET SOF

TP3

TP2

0

RXD

When an interrupt occurs these bits are set by

hardware. Software must read them to determine

the interrupt type and clear them after servicing.

Note: These bits cannot be set by software.

Bits 7:6 = TP[3:2] Token PID bits 3 & 2.

USB token PIDs are encoded in four bits. TP[3:2]

correspond to the variable token PID bits 3 & 2.

Note: PID bits 1 & 0 have a fixed value of 01.

When a CTR interrupt occurs (see register ISTR)

the software should read the TP3 and TP2 bits to

retrieve the PID name of the token received.

The USB standard defines TP bits as:

Bit 7 = SUSP Suspend mode request.

This bit is set by hardware when a constant idle

state is present on the bus line for more than 3 ms,

indicating a suspend mode request from the USB

bus. The suspend request check is active immedi-

ately after each USB reset event and its disabled

by hardware when suspend mode is forced

(FSUSP bit of CTLR register) until the end of

resume sequence.

TP3

0

TP2

0

PID Name

OUT

1

0

IN

1

SETUP

Bits 5:3 Reserved. Forced by hardware to 0.

Bit 6 = DOVR DMA over/underrun.

This bit is set by hardware if the ST7 processor

can’t answer a DMA request in time.

0: No over/underrun detected

Bit 2 = RX_SEZ Received single-ended zero

This bit indicates the status of the RX_SEZ trans-

ceiver output.

0: No SE0 (single-ended zero) state

1: USB lines are in SE0 (single-ended zero) state

1: Over/underrun detected

Bit 5 = CTR Correct Transfer. This bit is set by

hardware when a correct transfer operation is per-

formed. The type of transfer can be determined by

looking at bits TP3-TP2 in register PIDR. The End-

point on which the transfer was made is identified

by bits EP1-EP0 in register IDR.

Bit 1 = RXD Received data

0: No K-state

1: USB lines are in K-state

This bit indicates the status of the RXD transceiver

output (differential receiver output).

0: No Correct Transfer detected

1: Correct Transfer detected

Note: If the environment is noisy, the RX_SEZ and

RXD bits can be used to secure the application. By

interpreting the status, software can distinguish a

valid End Suspend event from a spurious wake-up

due to noise on the external USB line. A valid End

Suspend is followed by a Resume or Reset se-

quence. A Resume is indicated by RXD=1, a Re-

set is indicated by RX_SEZ=1.

Note: A transfer where the device sent a NAK or

STALL handshake is considered not correct (the

host only sends ACK handshakes). A transfer is

considered correct if there are no errors in the PID

and CRC fields, if the DATA0/DATA1 PID is sent

as expected, if there were no data overruns, bit

stuffing or framing errors.

Bit 0 = Reserved. Forced by hardware to 0.

Bit 4 = ERR Error.

This bit is set by hardware whenever one of the er-

rors listed below has occurred:

0: No error detected

1: Timeout, CRC, bit stuffing or nonstandard

framing error detected

67/109

ST7263

USB INTERFACE (Cont’d)

Bit 3 = IOVR Interrupt overrun.

of each bit, please refer to the corresponding bit

description in ISTR.

This bit is set when hardware tries to set ERR, or

SOF before they have been cleared by software.

0: No overrun detected

CONTROL REGISTER (CTLR)

Read / Write

1: Overrun detected

Reset Value: 0000 0110 (06h)

Bit 2 = ESUSP End suspend mode.

This bit is set by hardware when, during suspend

mode, activity is detected that wakes the USB in-

terface up from suspend mode.

7

0

RESUME

PDWN FSUSP FRES

This interrupt is serviced by a specific vector, in or-

der to wake up the ST7 from HALT mode.

0: No End Suspend detected

Bits 7:4 = Reserved. Forced by hardware to 0.

1: End Suspend detected

Bit 3 = RESUME Resume.

Bit 1 = RESET USB reset.

This bit is set by software to wake-up the Host

when the ST7 is in suspend mode.

0: Resume signal not forced

This bit is set by hardware when the USB reset se-

quence is detected on the bus.

0: No USB reset signal detected

1: USB reset signal detected

1: Resume signal forced on the USB bus.

Software should clear this bit after the appropriate

delay.

Note: The DADDR, EP0RA, EP0RB, EP1RA,

EP1RB, EP2RA and EP2RB registers are reset by

a USB reset.

Bit 2 = PDWN Power down.

This bit is set by software to turn off the 3.3V on-

chip voltage regulator that supplies the external

pull-up resistor and the transceiver.

0: Voltage regulator on

Bit 0 = SOF Start of frame.

This bit is set by hardware when a low-speed SOF

indication (keep-alive strobe) is seen on the USB

bus. It is also issued at the end of a resume se-

quence.

0: No SOF signal detected

1: SOF signal detected

1: Voltage regulator off

Note: After turning on the voltage regulator, soft-

ware should allow at least 3 µs for stabilisation of

the power supply before using the USB interface.

Note: To avoid spurious clearing of some bits, it is

recommended to clear them using a load instruc-

tion where all bits which must not be altered are

set, and all bits to be cleared are reset. Avoid read-

modify-write instructions like AND , XOR..

Bit 1 = FSUSP Force suspend mode.

This bit is set by software to enter Suspend mode.

The ST7 should also be halted allowing at least

600 ns before issuing the HALT instruction.

0: Suspend mode inactive

INTERRUPT MASK REGISTER (IMR)

Read / Write

1: Suspend mode active

When the hardware detects USB activity, it resets

this bit (it can also be reset by software).

Reset Value: 0000 0000 (00h)

7

0

Bit 0 = FRES Force reset.

This bit is set by software to force a reset of the

USB interface, just as if a RESET sequence came

from the USB.

SUS

PM

DOV

RM

CTR

M

ERR IOVR ESU

SPM

RES

ETM

SOF

M

0: Reset not forced

1: USB interface reset forced.

Bits 7:0 = These bits are mask bits for all interrupt

condition bits included in the ISTR. Whenever one

of the IMR bits is set, if the corresponding ISTR bit

is set, and the I bit in the CC register is cleared, an

interrupt request is generated. For an explanation

The USB is held in RESET state until software

clears this bit, at which point a “USB-RESET” in-

terrupt will be generated if enabled.

68/109

ST7263

USB INTERFACE (Cont’d)

DEVICE ADDRESS REGISTER (DADDR)

Read / Write

Bit 6 = DTOG_TX Data Toggle, for transmission

transfers.

Reset Value: 0000 0000 (00h)

It contains the required value of the toggle bit

(0=DATA0, 1=DATA1) for the next transmitted

data packet. This bit is set by hardware at the re-

ception of a SETUP PID. DTOG_TX toggles only

when the transmitter has received the ACK signal

from the USB host. DTOG_TX and also

DTOG_RX (see EPnRB) are normally updated by

hardware, at the receipt of a relevant PID. They

can be also written by software.

7

0

ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0

Bit 7 = Reserved. Forced by hardware to 0.

Bits 6:0 = ADD[6:0] Device address, 7 bits.

Software must write into this register the address

sent by the host during enumeration.

Bits 5:4 = STAT_TX[1:0] Status bits, for transmis-

sion transfers.

Note: This register is also reset when a USB reset

is received from the USB bus or forced through bit

FRES in the CTLR register.

These bits contain the information about the end-

point status, which are listed below:

STAT_TX1 STAT_TX0 Meaning

DISABLED: transmission

transfers cannot be executed.

0

ENDPOINT n REGISTER A (EPnRA)

Read / Write

STALL: the endpoint is stalled

and all transmission requests

result in a STALL handshake.

0

1

Reset Value: 0000 xxxx (0xh)

NAK: the endpoint is naked

and all transmission requests

result in a NAK handshake.

7

0

1

0

1

ST_

OUT

DTOG

_TX

STAT STAT TBC TBC TBC TBC

VALID: this endpoint is ena-

bled for transmission.

_TX1

_TX0

3

2

1

0

These bits are written by software. Hardware sets

the STAT_TX bits to NAK when a correct transfer

has occurred (CTR=1) related to a IN or SETUP

transaction addressed to this endpoint; this allows

the software to prepare the next set of data to be

transmitted.

These registers (EP0RA, EP1RA and EP2RA) are

used for controlling data transmission. They are

also reset by the USB bus reset.

Note: Endpoint 2 and the EP2RA register are not

available on some devices (see device feature list

and register map).

Bits 3:0 = TBC[3:0] Transmit byte count for End-

point n.

Before transmission, after filling the transmit buff-

er, software must write in the TBC field the trans-

mit packet size expressed in bytes (in the range 0-

8).

Bit 7 = ST_OUT Status out.

This bit is set by software to indicate that a status

out packet is expected: in this case, all nonzero

OUT data transfers on the endpoint are STALLed

instead of being ACKed. When ST_OUT is reset,

OUT transactions can have any number of bytes,

as needed.

69/109

ST7263

USB INTERFACE (Cont’d)

ENDPOINT n REGISTER B (EPnRB)

Read / Write

STAT_RX1 STAT_RX0 Meaning

NAK: the endpoint is na-

ked and all reception re-

quests result in a NAK

handshake.

VALID: this endpoint is

enabled for reception.

Reset Value: 0000 xxxx (0xh)

1

0

1

7

0

DTOG

_RX

STAT

_RX1

STAT

_RX0

CTRL

EA3 EA2 EA1 EA0

These bits are written by software. Hardware sets

the STAT_RX bits to NAK when a correct transfer

has occurred (CTR=1) related to an OUT or SET-

UP transaction addressed to this endpoint, so the

software has the time to elaborate the received

data before acknowledging a new transaction.

These registers (EP1RB and EP2RB) are used for

controlling data reception on Endpoints 1 and 2.

They are also reset by the USB bus reset.

Note: Endpoint 2 and the EP2RB register are not

available on some devices (see device feature list

and register map).

Bits 3:0 = EA[3:0] Endpoint address.

Software must write in this field the 4-bit address

used to identify the transactions directed to this

endpoint. Usually EP1RB contains “0001” and

EP2RB contains “0010”.

Bit 7 = CTRL Control.

This bit should be 0.

Note: If this bit is 1, the Endpoint is a control end-

point. (Endpoint 0 is always a control Endpoint, but

it is possible to have more than one control End-

point).

ENDPOINT 0 REGISTER B (EP0RB)

Read / Write

Reset Value: 1000 0000 (80h)

Bit 6 = DTOG_RX Data toggle, for reception trans-

fers.

7

1

0

It contains the expected value of the toggle bit

(0=DATA0, 1=DATA1) for the next data packet.

This bit is cleared by hardware in the first stage

(Setup Stage) of a control transfer (SETUP trans-

actions start always with DATA0 PID). The receiv-

er toggles DTOG_RX only if it receives a correct

data packet and the packet’s data PID matches

the receiver sequence bit.

DTOG STAT STAT

RX RX1 RX0

0

This register is used for controlling data reception

on Endpoint 0. It is also reset by the USB bus re-

set.

Bit 7 = Forced by hardware to 1.

Bits 5:4 = STAT_RX [1:0] Status bits, for reception

transfers.

These bits contain the information about the end-

point status, which are listed below:

Bits 6:4 = Refer to the EPnRB register for a de-

scription of these bits.

STAT_RX1 STAT_RX0 Meaning

DISABLED: reception

transfers cannot be exe-

cuted.

Bits 3:0 = Forced by hardware to 0.

0

1

STALL: the endpoint is

stalled and all reception

requests result in

STALL handshake.

a

70/109

ST7263

USB INTERFACE (Cont’d)

5.6.5 Programming Considerations

When the operation is completed, they can be ac-

cessed again to enable a new operation.

The interaction between the USB interface and the

application program is described below. Apart

from system reset, action is always initiated by the

USB interface, driven by one of the USB events

associated with the Interrupt Status Register (IS-

TR) bits.

5.6.5.4 Interrupt Handling

Start of Frame (SOF)

The interrupt service routine may monitor the SOF

events for a 1 ms synchronization event to the

USB bus. This interrupt is generated at the end of

a resume sequence and can also be used to de-

tect this event.

5.6.5.1 Initializing the Registers

At system reset, the software must initialize all reg-

isters to enable the USB interface to properly gen-

erate interrupts and DMA requests.

USB Reset (RESET)

When this event occurs, the DADDR register is re-

set, and communication is disabled in all endpoint

registers (the USB interface will not respond to any

packet). Software is responsible for reenabling

endpoint 0 within 10 ms of the end of reset. To do

this, set the STAT_RX bits in the EP0RB register

to VALID.

1. Initialize the DMAR, IDR, and IMR registers

(choice of enabled interrupts, address of DMA

buffers). Refer the paragraph titled initializing

the DMA Buffers.

2. Initialize the EP0RA and EP0RB registers to

enable accesses to address 0 and endpoint 0

to support USB enumeration. Refer to the para-

graph titled Endpoint Initialization.

Suspend (SUSP)

The CPU is warned about the lack of bus activity

for more than 3 ms, which is a suspend request.

The software should set the USB interface to sus-

pend mode and execute an ST7 HALT instruction

to meet the USB-specified power constraints.

3. When addresses are received through this

channel, update the content of the DADDR.

4. If needed, write the endpoint numbers in the EA

fields in the EP1RB and EP2RB register.

5.6.5.2 Initializing DMA buffers

End Suspend (ESUSP)

The DMA buffers are a contiguous zone of memo-

ry whose maximum size is 48 bytes. They can be

placed anywhere in the memory space to enable

the reception of messages. The 10 most signifi-

cant bits of the start of this memory area are spec-

ified by bits DA15-DA6 in registers DMAR and

IDR, the remaining bits are 0. The memory map is

shown in Figure 2.

The CPU is alerted by activity on the USB, which

causes an ESUSP interrupt. The ST7 automatical-

ly terminates HALT mode.

Correct Transfer (CTR)

1. When this event occurs, the hardware automat-

ically sets the STAT_TX or STAT_RX to NAK.

Note: Every valid endpoint is NAKed until soft-

ware clears the CTR bit in the ISTR register,

independently of the endpoint number

addressed by the transfer which generated the

CTR interrupt.

Each buffer is filled starting from the bottom (last 3

address bits=000) up.

5.6.5.3 Endpoint Initialization

Note: If the event triggering the CTR interrupt is

a SETUP transaction, both STAT_TX and

STAT_RX are set to NAK.

To be ready to receive:

Set STAT_RX to VALID (11b) in EP0RB to enable

reception.

2. Read the PIDR to obtain the token and the IDR

to get the endpoint number related to the last

transfer.

To be ready to transmit:

1. Write the data in the DMA transmit buffer.

Note: When a CTR interrupt occurs, the TP3-

TP2 bits in the PIDR register and EP1-EP0 bits

in the IDR register stay unchanged until the

CTR bit in the ISTR register is cleared.

2. In register EPnRA, specify the number of bytes

to be transmitted in the TBC field

3. Enable the endpoint by setting the STAT_TX

bits to VALID (11b) in EPnRA.

3. Clear the CTR bit in the ISTR register.

Note: Once transmission and/or reception are en-

abled, registers EPnRA and/or EPnRB (respec-

tively) must not be modified by software, as the

hardware can change their value on the fly.

71/109

ST7263

USB INTERFACE (Cont’d)

Table 19. USB Register Map and Reset Values

Address

(Hex.)

Register

Name

7

6

5

4

3

2

1

0

PIDR

TP3

TP2

0

RX_SEZ

RXD

0

25

26

27

28

29

2A

2B

2C

2D

2E

2F

30

31

Reset Value

DMAR

x

0

DA11

x

0

DA10

x

0

DA9

x

0

DA15

DA14

DA13

DA12

DA8

Reset Value

IDR

x

DA7

DA6

EP1

EP0

CNT3

0

CNT2

0

CNT1

0

CNT0

Reset Value

ISTR

x

0

SUSP

DOVR

CTR

ERR

IOVR

0

ESUSP

0

RESET

0

SOF

Reset Value

IMR

0

SUSPM

DOVRM

CTRM

ERRM

IOVRM ESUSPM RESETM

SOFM

Reset Value

CTLR

0

RESUME PDWN

FSUSP

FRES

Reset Value

DADDR

0

ADD6

0

ADD5

0

ADD4

0

1

0

ADD3

ADD2

ADD1

ADD0

Reset Value

EP0RA

0

ST_OUT

STAT_TX1 STAT_TX0

TBC3

TBC2

TBC1

TBC0

DTOG_TX

0

Reset Value

EP0RB

0

1

0

x

DTOG_RX STAT_RX1 STAT_RX0

0

Reset Value

EP1RA

0

ST_OUT DTOG_TX STAT_TX1 STAT_TX0

TBC3

x

TBC2

x

TBC1

x

TBC0

x

Reset Value

EP1RB

0

CTRL

0

DTOG_RX STAT_RX1 STAT_RX0

EA3

x

EA2

x

EA1

x

EA0

x

Reset Value

EP2RA

0

ST_OUT DTOG_TX STAT_TX1 STAT_TX0

TBC3

x

TBC2

x

TBC1

x

TBC0

x

Reset Value

EP2RB

0

CTRL

0

DTOG_RX STAT_RX1 STAT_RX0

EA3

x

EA2

x

EA1

x

EA0

x

Reset Value

0

72/109

ST7263

5.7 I²C BUS INTERFACE (I²C)

5.7.1 Introduction

handshake. The interrupts are enabled or disabled

by software. The interface is connected to the I²C

bus by a data pin (SDAI) and by a clock pin (SCLI).

It can be connected both with a standard I²C bus

and a Fast I²C bus. This selection is made by soft-

ware.

The I²C Bus Interface serves as an interface be-

tween the microcontroller and the serial I²C bus. It

provides both multimaster and slave functions,

and controls all I²C bus-specific sequencing, pro-

tocol, arbitration and timing. It supports fast I²C

mode (400 kHz).

Mode Selection

5.7.2 Main Features

The interface can operate in the four following

modes:

■ Parallel-bus/I²C protocol converter

■ Multi-master capability

■ 7-bit Addressing

– Slave transmitter/receiver

– Master transmitter/receiver

By default, it operates in slave mode.

■ Transmitter/Receiver flag

■ End-of-byte transmission flag

■ Transfer problem detection

I²C Master Features:

The interface automatically switches from slave to

master after it generates a START condition and

from master to slave in case of arbitration loss or a

STOP generation, this allows Multi-Master capa-

bility.

■ Clock generation

■ I²C bus busy flag

Communication Flow

■ Arbitration Lost Flag

In Master mode, it initiates a data transfer and

generates the clock signal. A serial data transfer

always begins with a start condition and ends with

a stop condition. Both start and stop conditions are

generated in master mode by software.

■ End of byte transmission flag

■ Transmitter/Receiver Flag

■ Start bit detection flag

■ Start and Stop generation

I²C Slave Features:

In Slave mode, the interface is capable of recog-

nising its own address (7-bit), and the General Call

address. The General Call address detection may

be enabled or disabled by software.

■ Stop bit detection

■ I²C bus busy flag

Data and addresses are transferred as 8-bit bytes,

MSB first. The first byte following the start condi-

tion is the address byte; it is always transmitted in

Master mode.

■ Detection of misplaced start or stop condition

■ Programmable I²C Address detection

■ Transfer problem detection

■ End-of-byte transmission flag

■ Transmitter/Receiver flag

5.7.3 General Description

A 9th clock pulse follows the 8 clock cycles of a

byte transfer, during which the receiver must send

an acknowledge bit to the transmitter. Refer to Fig-

ure 1.

In addition to receiving and transmitting data, this

interface converts it from serial to parallel format

and vice versa, using either an interrupt or polled

Figure 38. I²C BUS Protocol

SDA

MSB

ACK

SCL

1

2

8

9

START

STOP

CONDITION

VR02119B

73/109

ST7263

I²C BUS INTERFACE (Cont’d)

The Acknowledge function may be enabled and

disabled by software.

The SCL frequency (F

grammable clock divider which depends on the I²C

bus mode.

) is controlled by a pro-

SCL

The I²C interface address and/or general call ad-

dress can be selected by software.

When the I²C cell is enabled, the SDA and SCL

ports must be configured as floating open-drain

output or floating input. In this case, the value of

the external pull-up resistor used depends on the

application.

The speed of the I²C interface may be selected be-

tween Standard (0-100 kHz) and Fast I²C (100-

400 kHz).

When the I²C cell is disabled, the SDA and SCL

ports revert to being standard I/O port pins.

SDA/SCL Line Control

Transmitter mode: the interface holds the clock

line low before transmission to wait for the micro-

controller to write the byte in the Data Register.

Receiver mode: the interface holds the clock line

low after reception to wait for the microcontroller to

read the byte in the Data Register.

Figure 39. I²C Interface Block Diagram

DATA REGISTER (DR)

DATA SHIFT REGISTER

SDAI

DATA CONTROL

SDA

COMPARATOR

OWN ADDRESS REGISTER (OAR)

SCLI

CLOCK CONTROL

SCL

CLOCK CONTROL REGISTER (CCR)

CONTROL REGISTER (CR)

STATUS REGISTER 1 (SR1)

STATUS REGISTER 2 (SR2)

CONTROL LOGIC

INTERRUPT

74/109

ST7263

I²C BUS INTERFACE (Cont’d)

5.7.4 Functional Description

Refer to the CR, SR1 and SR2 registers in Section

0.1.7. for the bit definitions.

The slave waits for a read of the SR1 register fol-

lowed by a write in the DR register, holding the

SCL line low (see Figure 3 Transfer sequencing

EV3).

By default the I²C interface operates in Slave

mode (M/SL bit is cleared) except when it initiates

a transmit or receive sequence.

When the acknowledge pulse is received:

5.7.4.1 Slave Mode

– The EVF and BTF bits are set by hardware with

an interrupt if the ITE bit is set.

As soon as a start condition is detected, the

address is received from the SDA line and sent to

the shift register; then it is compared with the

address of the interface or the General Call

address (if selected by software).

Closing Slave Communication

After the last data byte is transferred a Stop Con-

dition is generated by the master. The interface

detects this condition and sets:

Address not matched: the interface ignores it

and waits for another Start condition.

– EVF and STOPF bits with an interrupt if the ITE

bit is set.

Address matched: the interface generates in se-

quence:

Then the interface waits for a read of the SR2 reg-

ister (see Figure 3 Transfer sequencing EV4).

– An Acknowledge pulse is generated if the ACK

bit is set.

– EVF and ADSL bits are set with an interrupt if the

ITE bit is set.

Error Cases

– BERR: Detection of a Stop or a Start condition

during a byte transfer. In this case, the EVF and

BERR bits are set with an interrupt if the ITE bit

is set.

If it is a Stop condition, then the interface dis-

cards the data, released the lines and waits for

another Start condition.

Then the interface waits for a read of the SR1 reg-

ister, holding the SCL line low (see Figure 3

Transfer sequencing EV1).

Next, software must read the DR register to deter-

mine from the least significant bit if the slave must

enter Receiver or Transmitter mode.

If it is a Start condition, then the interface dis-

cards the data and waits for the next slave ad-

dress on the bus.

Slave Receiver

Following the address reception and after SR1

register has been read, the slave receives bytes

from the SDA line into the DR register via the inter-

nal shift register. After each byte the interface gen-

erates in sequence:

– AF: Detection of a non-acknowledge bit. In this

case, the EVF and AF bits are set with an inter-

rupt if the ITE bit is set.

Note: In both cases, the SCL line is not held low;

however, the SDA line can remain low due to pos-

sible “0” bits transmitted last. It is then necessary

to release both lines by software.

– An Acknowledge pulse is generated if the ACK

bit is set

– EVF and BTF bits are set with an interrupt if the

ITE bit is set.

How to Release the SDA / SCL lines

Then the interface waits for a read of the SR1 reg-

ister followed by a read of the DR register, holding

the SCL line low (see Figure 3 Transfer sequenc-

ing EV2).

Set and subsequently clear the STOP bit while

BTF is set. The SDA/SCL lines are released after

the transfer of the current byte.

Slave Transmitter

Following the address reception and after the SR1

register has been read, the slave sends bytes from

the DR register to the SDA line via the internal shift

register.

75/109

ST7263

I²C BUS INTERFACE (Cont’d)

5.7.4.2 Master Mode

To close the communication: before reading the

last byte from the DR register, set the STOP bit to

generate the Stop condition. The interface returns

automatically to slave mode (M/SL bit cleared).

To switch from default Slave mode to Master

mode, a Start condition generation is needed.

Note: In order to generate the non-acknowledge

pulse after the last received data byte, the ACK bit

must be cleared just before reading the second

last data byte.

Start Condition and Transmit Slave Address

Setting the START bit while the BUSY bit is

cleared causes the interface to switch to Master

mode (M/SL bit set) and generates a Start condi-

tion.

Master Transmitter

Once the Start condition is sent:

Following the address transmission and after SR1

register has been read, the master sends bytes

from the DR register to the SDA line via the inter-

nal shift register.

– The EVF and SB bits are set by hardware with

an interrupt if the ITE bit is set.

Then the master waits for a read of the SR1 regis-

ter followed by a write in the DR register with the

Slave address byte, holding the SCL line low

(see Figure 3 Transfer sequencing EV5).

The master waits for a read of the SR1 register fol-

lowed by a write in the DR register, holding the

SCL line low (see Figure 3 Transfer sequencing

EV8).

Then the slave address byte is sent to the SDA

line via the internal shift register.

When the acknowledge bit is received, the

interface sets:

After completion of this transfer (and acknowledge

from the slave if the ACK bit is set):

– EVF and BTF bits with an interrupt if the ITE bit

is set.

– The EVF bit is set by hardware with interrupt

generation if the ITE bit is set.

To close the communication: after writing the last

byte to the DR register, set the STOP bit to gener-

ate the Stop condition. The interface goes auto-

matically back to slave mode (M/SL bit cleared).

Then the master waits for a read of the SR1 regis-

ter followed by a write in the CR register (for exam-

ple set PE bit), holding the SCL line low (see Fig-

ure 3 Transfer sequencing EV6).

Next the master must enter Receiver or Transmit-

ter mode.

Error Cases

– BERR: Detection of a Stop or a Start condition

during a byte transfer. In this case, the EVF and

BERR bits are set by hardware with an interrupt

if the ITE bit is set.

Master Receiver

Following the address transmission and after the

SR1 and CR registers have been accessed, the

master receives bytes from the SDA line into the

DR register via the internal shift register. After

each byte the interface generates in sequence:

– AF: Detection of a non-acknowledge bit. In this

case, the EVF and AF bits are set by hardware

with an interrupt if the ITE bit is set. To resume,

set the START or STOP bit.

– ARLO: Detection of an arbitration lost condition.

In this case the ARLO bit is set by hardware (with

an interrupt if the ITE bit is set and the interface

goes automatically back to slave mode (the M/SL

bit is cleared).

– An Acknowledge pulse is generated if if the ACK

bit is set

– EVF and BTF bits are set by hardware with an in-

terrupt if the ITE bit is set.

Then the interface waits for a read of the SR1 reg-

ister followed by a read of the DR register, holding

the SCL line low (see Figure 3 Transfer sequenc-

ing EV7).

Note: In all these cases, the SCL line is not held

low; however, the SDA line can remain low due to

possible “0” bits transmitted last. It is then neces-

sary to release both lines by software.

76/109

ST7263

I²C BUS INTERFACE (Cont’d)

Figure 40. Transfer Sequencing

Slave Receiver

S

Address

A

Data1

A

Data2

EV3

A

DataN

A

P

.....

EV1

EV2

A

EV2

A

EV2

NA

EV4

Slave Transmitter

S

Address

A

Data1

Data2

DataN

P

.....

EV1 EV3

EV3

EV3-1

EV4

Master Receiver

S

Address

A

Data1

A

Data2

A

DataN NA

P

EV5

EV6

EV7

A

EV7

A

EV7

A

Master Transmitter

S

Address

A

Data1

Data2

DataN

P

.....

EV5

EV6 EV8

EV8

Legend:

S=Start, P=Stop, A=Acknowledge, NA=Non-acknowledge

EVx=Event (with interrupt if ITE=1)

EV1: EVF=1, ADSL=1, cleared by reading the SR1 register.

EV2: EVF=1, BTF=1, cleared by reading the SR1 register followed by reading the DR register.

EV3: EVF=1, BTF=1, cleared by reading the SR1 register followed by writing the DR register.

EV3-1: EVF=1, AF=1, BTF=1; AF is cleared by reading the SR1 register. The BTF is cleared

by releasing the lines (STOP=1, STOP=0) or by writing the DR register (DR=FFh).

Note: If lines are released by STOP=1, STOP=0, the subsequent EV4 is not seen.

EV4: EVF=1, STOPF=1, cleared by reading the SR2 register.

EV5: EVF=1, SB=1, cleared by reading the SR1 register followed by writing the DR register.

EV6: EVF=1, cleared by reading the SR1 register followed by writing the CR register

(for example PE=1).

EV7: EVF=1, BTF=1, cleared by reading the SR1 register followed by reading the DR register.

EV8: EVF=1, BTF=1, cleared by reading the SR1 register followed by writing the DR register.

77/109

ST7263

I²C BUS INTERFACE (Cont’d)

5.7.5 Low Power Modes

Mode

Description

No effect on I²C interface.

I²C interrupts exit from Wait mode.

I²C registers are frozen.

WAIT

In Halt mode, the I²C interface is inactive and does not acknowledge data on the bus. The I²C

interface resumes operation when the MCU is woken up by an interrupt with “exit from Halt

mode” capability.

HALT

5.7.6 Interrupts

Figure 41. Event Flags and Interrupt Generation

BTF

ADSL

SB

ITE

AF

INTERRUPT

EVF

STOPF

ARLO

BERR

*

* EVF can also be set by EV6 or an error from the SR2 register.

Enable

Control from

Bit

Exit

from

Halt

Event

Flag

Interrupt Event

Wait

Yes

End of Byte Transfer Event

BTF

ADSEL

SB

No

Address Matched Event (Slave mode)

Start Bit Generation Event (Master mode)

Acknowledge Failure Event

AF

ITE

Stop Detection Event (Slave mode)

Arbitration Lost Event (Multimaster configuration)

Bus Error Event

STOPF

ARLO

BERR

The I²C interrupt events are connected to the

same interrupt vector (see Interrupts chapter).

They generate an interrupt if the corresponding

Enable Control Bit is set and the I-bit in the CC

register is reset (RIM instruction).

78/109

ST7263

I²C BUS INTERFACE (Cont’d)

5.7.7 Register Description

Bit 2 = ACK Acknowledge enable.

I²C CONTROL REGISTER (CR)

Read / Write

Reset Value: 0000 0000 (00h)

This bit is set and cleared by software. It is also

cleared by hardware when the interface is disa-

bled (PE=0).

7

0

0: No acknowledge returned

1: Acknowledge returned after an address byte or

a data byte is received

0

PE

ENGC START ACK STOP

ITE

Bit 1 = STOP Generation of a Stop condition.

This bit is set and cleared by software. It is also

cleared by hardware in master mode. Note: This

bit is not cleared when the interface is disabled

(PE=0).

Bits 7:6 = Reserved. Forced to 0 by hardware.

Bit 5 = PE Peripheral enable.

This bit is set and cleared by software.

0: Peripheral disabled

1: Master/Slave capability

Notes:

– When PE=0, all the bits of the CR register and

the SR register except the Stop bit are reset. All

outputs are released while PE=0

– In Master mode:

0: No stop generation

1: Stop generation after the current byte transfer

or after the current Start condition is sent. The

STOP bit is cleared by hardware when the Stop

condition is sent.

– When PE=1, the corresponding I/O pins are se-

lected by hardware as alternate functions.

– To enable the I²C interface, write the CR register

TWICE with PE=1 as the first write only activates

the interface (only PE is set).

– In Slave mode:

0: No stop generation

1: Release the SCL and SDA lines after the cur-

rent byte transfer (BTF=1). In this mode the

STOP bit has to be cleared by software.

Bit 4 = ENGC Enable General Call.

This bit is set and cleared by software. It is also

cleared by hardware when the interface is disa-

bled (PE=0). The 00h General Call address is ac-

knowledged (01h ignored).

0: General Call disabled

1: General Call enabled

Bit 0 = ITE Interrupt enable.

This bit is set and cleared by software and cleared

by hardware when the interface is disabled

(PE=0).

0: Interrupts disabled

1: Interrupts enabled

Refer to Figure 4 for the relationship between the

events and the interrupt.

Bit 3 = START Generation of a Start condition.

This bit is set and cleared by software. It is also

cleared by hardware when the interface is disa-

bled (PE=0) or when the Start condition is sent

(with interrupt generation if ITE=1).

SCL is held low when the SB, BTF or ADSL flags

or an EV6 event (See Figure 3) is detected.

– In master mode:

0: No start generation

1: Repeated start generation

– In slave mode:

0: No start generation

1: Start generation when the bus is free

79/109

ST7263

I²C BUS INTERFACE (Cont’d)

I²C STATUS REGISTER 1 (SR1)

Read Only

Bit 3 = BTF Byte transfer finished.

This bit is set by hardware as soon as a byte is cor-

rectly received or transmitted with interrupt gener-

ation if ITE=1. It is cleared by software reading

SR1 register followed by a read or write of DR reg-

ister. It is also cleared by hardware when the inter-

face is disabled (PE=0).

Reset Value: 0000 0000 (00h)

7

0

EVF

0

TRA BUSY BTF ADSL M/SL

SB

– Following a byte transmission, this bit is set after

reception of the acknowledge clock pulse. In

case an address byte is sent, this bit is set only

after the EV6 event (See Figure 3). BTF is

cleared by reading SR1 register followed by writ-

ing the next byte in DR register.

Bit 7 = EVF Event flag.

This bit is set by hardware as soon as an event oc-

curs. It is cleared by software reading SR2 register

in case of error event or as described in Figure 3. It

is also cleared by hardware when the interface is

disabled (PE=0).

0: No event

1: One of the following events has occurred:

– Following a byte reception, this bit is set after

transmission of the acknowledge clock pulse if

ACK=1. BTF is cleared by reading SR1 register

followed by reading the byte from DR register.

– BTF=1 (Byte received or transmitted)

The SCL line is held low while BTF=1.

– ADSL=1 (Address matched in Slave mode

while ACK=1)

0: Byte transfer not done

1: Byte transfer succeeded

– SB=1 (Start condition generated in Master

mode)

Bit 2 = ADSL Address matched (Slave mode).

This bit is set by hardware as soon as the received

slave address matched with the OAR register con-

tent or a general call is recognized. An interrupt is

generated if ITE=1. It is cleared by software read-

ing SR1 register or by hardware when the inter-

face is disabled (PE=0).

– AF=1 (No acknowledge received after byte

transmission)

– STOPF=1 (Stop condition detected in Slave

mode)

– ARLO=1 (Arbitration lost in Master mode)

– BERR=1 (Bus error, misplaced Start or Stop

condition detected)

The SCL line is held low while ADSL=1.

– Address byte successfully transmitted in Mas-

ter mode.

0: Address mismatched or not received

1: Received address matched

Bit 6 = Reserved. Forced to 0 by hardware.

Bit 1 = M/SL Master/Slave.

This bit is set by hardware as soon as the interface

is in Master mode (writing START=1). It is cleared

by hardware after detecting a Stop condition on

the bus or a loss of arbitration (ARLO=1). It is also

cleared when the interface is disabled (PE=0).

0: Slave mode

Bit 5 = TRA Transmitter/Receiver.

When BTF is set, TRA=1 if a data byte has been

transmitted. It is cleared automatically when BTF

is cleared. It is also cleared by hardware after de-

tection of Stop condition (STOPF=1), loss of bus

arbitration (ARLO=1) or when the interface is disa-

bled (PE=0).

1: Master mode

0: Data byte received (if BTF=1)

1: Data byte transmitted

Bit 0 = SB Start bit (Master mode).

This bit is set by hardware as soon as the Start

condition is generated (following

a

write

START=1). An interrupt is generated if ITE=1. It is

cleared by software reading SR1 register followed

by writing the address byte in DR register. It is also

cleared by hardware when the interface is disa-

bled (PE=0).

0: No Start condition

1: Start condition generated

Bit 4 = BUSY Bus busy.

This bit is set by hardware on detection of a Start

condition and cleared by hardware on detection of

a Stop condition. It indicates a communication in

progress on the bus. This information is still updat-

ed when the interface is disabled (PE=0).

0: No communication on the bus

1: Communication ongoing on the bus

80/109

ST7263

I²C BUS INTERFACE (Cont’d)

I²C STATUS REGISTER 2 (SR2)

Read Only

Reset Value: 0000 0000 (00h)

es the arbitration of the bus to another master. An

interrupt is generated if ITE=1. It is cleared by soft-

ware reading SR2 register or by hardware when

the interface is disabled (PE=0).

7

0

After an ARLO event the interface switches back

automatically to Slave mode (M/SL=0).

0

AF STOPF ARLO BERR GCAL

The SCL line is not held low while ARLO=1.

0: No arbitration lost detected

1: Arbitration lost detected

Bits 7:5 = Reserved. Forced to 0 by hardware.

Bit 1 = BERR Bus error.

Bit 4 = AF Acknowledge failure.

This bit is set by hardware when the interface de-

tects a misplaced Start or Stop condition. An inter-

rupt is generated if ITE=1. It is cleared by software

reading SR2 register or by hardware when the in-

terface is disabled (PE=0).

This bit is set by hardware when no acknowledge

is returned. An interrupt is generated if ITE=1. It is

cleared by software reading SR2 register or by

hardware when the interface is disabled (PE=0).

The SCL line is not held low while AF=1.

The SCL line is not held low while BERR=1.

0: No acknowledge failure

1: Acknowledge failure

0: No misplaced Start or Stop condition

1: Misplaced Start or Stop condition

Bit 3 = STOPF Stop detection (Slave mode).

This bit is set by hardware when a Stop condition

is detected on the bus after an acknowledge (if

ACK=1). An interrupt is generated if ITE=1. It is

cleared by software reading SR2 register or by

hardware when the interface is disabled (PE=0).

Bit 0 = GCAL General Call (Slave mode).

This bit is set by hardware when a general call ad-

dress is detected on the bus while ENGC=1. It is

cleared by hardware detecting a Stop condition

(STOPF=1) or when the interface is disabled

(PE=0).

The SCL line is not held low while STOPF=1.

0: No general call address detected on bus

1: general call address detected on bus

0: No Stop condition detected

1: Stop condition detected

Bit 2 = ARLO Arbitration lost.

This bit is set by hardware when the interface los-

81/109

ST7263

I²C BUS INTERFACE (Cont’d)

I²C CLOCK CONTROL REGISTER (CCR)

I²C OWN ADDRESS REGISTER (OAR)

Read / Write

Reset Value: 0000 0000 (00h)

Read / Write

Reset Value: 0000 0000 (00h)

7

0

7

0

FM/SM CC6

CC5

CC4

CC3

CC2

CC1

CC0

ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0

Bit 7 = FM/SM Fast/Standard I²C mode.

This bit is set and cleared by software. It is not

cleared when the interface is disabled (PE=0).

0: Standard I²C mode

Bits 7:1 = ADD7-ADD1 Interface address.

These bits define the I²C bus address of the inter-

face. They are not cleared when the interface is

disabled (PE=0).

1: Fast I²C mode

Bits 6:0 = CC6-CC0 7-bit clock divider.

These bits select the speed of the bus (F

pending on the I²C mode. They are not cleared

when the interface is disabled (PE=0).

Bit 0 = ADD0 Address direction bit.

This bit is don’t care, the interface acknowledges

either 0 or 1. It is not cleared when the interface is

disabled (PE=0).

) de-

SCL

– Standard mode (FM/SM=0): F

<= 100kHz

SCL

Note: Address 01h is always ignored.

F

= f

/(2x([CC6..CC0]+2))

CPU

SCL

– Fast mode (FM/SM=1): F

> 100kHz

SCL

F

= f

/(3x([CC6..CC0]+2))

CPU

SCL

Note: The programmed F

SCL and SDA lines.

assumes no load on

SCL

I²C DATA REGISTER (DR)

Read / Write

Reset Value: 0000 0000 (00h)

7

0

D7

D6

D5

D4

D3

D2

D1

D0

Bits 7:0 = D7-D0 8-bit Data Register.

These bits contains the byte to be received or

transmitted on the bus.

– Transmitter mode: Byte transmission start auto-

matically when the software writes in the DR reg-

ister.

– Receiver mode: the first data byte is received au-

tomatically in the DR register using the least sig-

nificant bit of the address.

Then, the next data bytes are received one by

one after reading the DR register.

82/109

ST7263

2

Table 20. I C Register Map

Address

(Hex.)

39

Register

Name

7

6

5

4

3

2

1

0

DR

OAR

CCR

SR2

SR1

CR

DR7 .. DR0

ADD7 .. ADD0

CC6 .. CC0

3B

3C

FM/SM

EVF

3D

AF

STOPF

BTF

ARLO

ADSL

ACK

BERR

M/SL

GCAL

SB

3E

TRA

PE

BUSY

ENGC

3F

START

STOP

ITE

83/109

ST7263

5.8 8-BIT A/D CONVERTER (ADC)

5.8.1 Introduction

5.8.2 Main Features

■ 8-bit conversion

The on-chip Analog to Digital Converter (ADC) pe-

ripheral is a 8-bit, successive approximation con-

verter with internal sample and hold circuitry. This

peripheral has up to 8 multiplexed analog input

channels (refer to device pin out description) that

allow the peripheral to convert the analog voltage

levels from up to 8 different sources.

■ Up to 8 channels with multiplexed input

■ Linear successive approximation

■ Data register (DR) which contains the results

■ Conversion complete status flag

■ On/Off bit (to reduce consumption)

The result of the conversion is stored in a 8-bit

Data Register. The A/D converter is controlled

through a Control/Status Register.

The block diagram is shown in Figure 42.

Figure 42. ADC Block Diagram

-

ADON

0

-

CH2 CH1 CH0

COCO

(Control Status Register) CSR

AIN0

AIN1

AIN2

AIN3

AIN4

AIN5

AIN6

AIN7

SAMPLE

&

HOLD

ANALOG TO

DIGITAL

CONVERTER

ANALOG

MUX

f

CPU

AD6 AD5 AD4 AD3 AD2 AD1 AD0

(Data Register) DR

AD7

84/109

ST7263

8-BIT A/D CONVERTER (ADC) (Cont’d)

5.8.3 Functional Description

The accuracy of the conversion is described in the

Electrical Characteristics Section.

The high level reference voltage V

must be

pin. The low level

DDA

connected externally to the V

Procedure:

DD

reference voltage V

must be connected exter-

SSA

Refer to the CSR and DR register description sec-

tion for the bit definitions.

nally to the V pin. In some devices (refer to de-

SS

vice pin out description) high and low level refer-

Each analog input pin must be configured as input,

no pull-up, no interrupt. Refer to the “I/O Ports”

chapter. Using these pins as analog inputs does

not affect the ability of the port to be read as a logic

input.

ence voltages are internally connected to the V

DD

and V pins.

SS

Conversion accuracy may therefore be degraded

by voltage drops and noise in the event of heavily

loaded or badly decoupled power supply lines.

In the CSR register:

Figure 43. Recommended Ext. Connections

– Select the CH2 to CH0 bits to assign the ana-

log channel to convert. Refer to Table 21

Channel Selection.

V

DD

V

DDA

SSA

– Set the ADON bit. Then the A/D converter is

enabled after a stabilization time (typically 30

µs). It then performs a continuous conversion

of the selected channel.

0.1µF

ST7

R

When a conversion is complete

– The COCO bit is set by hardware.

– No interrupt is generated.

AIN

V

Px.x/AINx

AIN

– The result is in the DR register.

A write to the CSR register aborts the current con-

version, resets the COCO bit and starts a new

conversion.

Characteristics:

The conversion is monotonic, meaning the result

never decreases if the analog input does not and

never increases if the analog input does not.

5.8.4 Low Power Modes

If input voltage is greater than or equal to V

(voltage reference high) then results = FFh (full

scale) without overflow indication.

DD

Note: The A/D converter may be disabled by re-

setting the ADON bit. This feature allows reduced

power consumption when no conversion is need-

ed.

If input voltage ≤ V (voltage reference low) then

the results = 00h.

SS

Mode

Description

The conversion time is 64 CPU clock cycles in-

cluding a sampling time of 31.5 CPU clock cycles.

WAIT

No effect on A/D Converter

A/D Converter disabled.

R

is the maximum recommended impedance

AIN

for an analog input signal. If the impedance is too

high, this will result in a loss of accuracy due to

leakage and sampling not being completed in the

alloted time.

After wakeup from Halt mode, the A/D

Converter requires a stabilisation time

before accurate conversions can be

performed.

HALT

The A/D converter is linear and the digital result of

the conversion is given by the formula:

255 x Input Voltage

Digital result =

5.8.5 Interrupts

Reference Voltage

None.

Where Reference Voltage is V - V

.

DD

SS

85/109

ST7263

8-BIT A/D CONVERTER (ADC) (Cont’d)

5.8.6 Register Description

CONTROL/STATUS REGISTER (CSR)

Read/Write

Table 21. Channel Selection

Pin*

AIN0

AIN1

AIN2

AIN3

AIN4

AIN5

AIN6

AIN7

CH2

0

CH1

0

CH0

0

Reset Value: 0000 0000 (00h)

0

1

7

0

1

0

1

COCO

-

ADON

0

-

CH2

CH1

CH0

1

0

1

0

1

Bit 7 = COCO Conversion Complete

1

0

This bit is set by hardware. It is cleared by soft-

ware reading the result in the DR register or writing

to the CSR register.

1

*IMPORTANT NOTE: The number of pins AND

the channel selection vary according to the device.

REFER TO THE DEVICE PINOUT).

0: Conversion is not complete.

1: Conversion can be read from the DR register.

Bit 6 = Reserved. Must always be cleared.

Bit 5 = ADON A/D converter On

DATA REGISTER (DR)

Read Only

Reset Value: 0000 0000 (00h)

This bit is set and cleared by software.

0: A/D converter is switched off.

1: A/D converter is switched on.

7

0

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

Note: A typical 30 µs delay time is necessary for

the ADC to stabilize when the ADON bit is set.

Bit 7:0 = AD[7:0] Analog Converted Value

Bit 4 = Reserved. Forced by hardware to 0.

Bit 3 = Reserved. Must always be cleared.

Bits 2:0: CH[2:0] Channel Selection

This register contains the converted analog value

in the range 00h to FFh.

Reading this register resets the COCO flag.

These bits are set and cleared by software. They

select the analog input to convert.

86/109

ST7263

6 INSTRUCTION SET

6.1 ST7 ADDRESSING MODES

so, most of the addressing modes may be subdi-

vided in two sub-modes called long and short:

The ST7 Core features 17 different addressing

modes which can be classified in 7 main groups:

– Long addressing mode is more powerful be-

cause it can use the full 64 Kbyte address space,

however it uses more bytes and more CPU cy-

cles.

Addressing Mode

Inherent

Example

nop

– Short addressing mode is less powerful because

it can generally only access page zero (0000h -

00FFh range), but the instruction size is more

compact, and faster. All memory to memory in-

structions use short addressing modes only

(CLR, CPL, NEG, BSET, BRES, BTJT, BTJF,

INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP)

Immediate

Direct

ld A,#$55

ld A,$55

Indexed

ld A,($55,X)

ld A,([$55],X)

jrne loop

Indirect

Relative

Bit operation

bset byte,#5

The ST7 Assembler optimizes the use of long and

short addressing modes.

The ST7 Instruction set is designed to minimize

the number of bytes required per instruction: To do

Table 22. ST7 Addressing Mode Overview

Pointer

Address

(Hex.)

Pointer

Size

(Hex.)

Destination/

Source

Length

(Bytes)

Mode

Syntax

Inherent

Immediate

Short

nop

+ 0

+ 1

+ 2

ld A,#$55

ld A,$10

Direct

00..FF

Long

ld A,$1000

0000..FFFF

+ 0 (with X register)

+ 1 (with Y register)

No Offset

Direct

Indexed

ld A,(X)

00..FF

Short

Long

Short

Long

Short

Long

Relative

Bit

Direct

Indexed

ld A,($10,X)

ld A,($1000,X)

ld A,[$10]

00..1FE

+ 1

+ 2

+ 1

+ 2

+ 1

+ 2

+ 3

Direct

0000..FFFF

00..FF

Indirect

Direct

00..FF

byte

word

byte

word

ld A,[$10.w]

ld A,([$10],X)

0000..FFFF

00..1FE

Indexed

ld A,([$10.w],X) 0000..FFFF

1)

jrne loop

PC-128/PC+127

Indirect

Direct

jrne [$10]

PC-128/PC+127

00..FF

byte

bset $10,#7

bset [$10],#7

Bit

Indirect

Direct

00..FF

Bit

Relative btjt $10,#7,skip 00..FF

Relative btjt [$10],#7,skip 00..FF

Bit

Indirect

Note 1. At the time the instruction is executed, the Program Counter (PC) points to the instruction follow-

ing JRxx.

87/109

ST7263

ST7 ADDRESSING MODES (Cont’d)

6.1.1 Inherent

6.1.3 Direct

All Inherent instructions consist of a single byte.

The opcode fully specifies all the required informa-

tion for the CPU to process the operation.

In Direct instructions, the operands are referenced

by their memory address.

The direct addressing mode consists of two sub-

modes:

Inherent Instruction

Function

No operation

Direct (short)

NOP

The address is a byte, thus requires only one byte

after the opcode, but only allows 00 - FF address-

ing space.

TRAP

S/W Interrupt

Wait For Interrupt (Low Power

Mode)

WFI

Direct (long)

Halt Oscillator (Lowest Power

Mode)

HALT

The address is a word, thus allowing 64 Kbyte ad-

dressing space, but requires 2 bytes after the op-

code.

RET

Sub-routine Return

Interrupt Sub-routine Return

Set Interrupt Mask

Reset Interrupt Mask

Set Carry Flag

IRET

SIM

6.1.4 Indexed (No Offset, Short, Long)

RIM

In this mode, the operand is referenced by its

memory address, which is defined by the unsigned

addition of an index register (X or Y) with an offset.

SCF

RCF

Reset Carry Flag

Reset Stack Pointer

Load

The indirect addressing mode consists of three

sub-modes:

RSP

LD

Indexed (No Offset)

CLR

Clear

There is no offset, (no extra byte after the opcode),

and allows 00 - FF addressing space.

PUSH/POP

INC/DEC

TNZ

Push/Pop to/from the stack

Increment/Decrement

Test Negative or Zero

1 or 2 Complement

Byte Multiplication

Indexed (Short)

The offset is a byte, thus requires only one byte af-

ter the opcode and allows 00 - 1FE addressing

space.

CPL, NEG

MUL

Indexed (long)

SLL, SRL, SRA, RLC,

RRC

Shift and Rotate Operations

Swap Nibbles

The offset is a word, thus allowing 64 Kbyte ad-

dressing space and requires 2 bytes after the op-

code.

SWAP

6.1.2 Immediate

Immediate instructions have two bytes, the first

byte contains the opcode, the second byte con-

tains the operand value.

6.1.5 Indirect (Short, Long)

The required data byte to do the operation is found

by its memory address, located in memory (point-

er).

Immediate Instruction

Function

The pointer address follows the opcode. The indi-

rect addressing mode consists of two sub-modes:

LD

Load

CP

Compare

Indirect (short)

BCP

Bit Compare

The pointer address is a byte, the pointer size is a

byte, thus allowing 00 - FF addressing space, and

requires 1 byte after the opcode.

AND, OR, XOR

ADC, ADD, SUB, SBC

Logical Operations

Arithmetic Operations

Indirect (long)

The pointer address is a byte, the pointer size is a

word, thus allowing 64 Kbyte addressing space,

and requires 1 byte after the opcode.

88/109

ST7263

ST7 ADDRESSING MODES (Cont’d)

6.1.6 Indirect Indexed (Short, Long)

SWAP

Swap Nibbles

Call or Jump subroutine

This is a combination of indirect and short indexed

addressing modes. The operand is referenced by

its memory address, which is defined by the un-

signed addition of an index register value (X or Y)

with a pointer value located in memory. The point-

er address follows the opcode.

CALL, JP

6.1.7 Relative Mode (Direct, Indirect)

This addressing mode is used to modify the PC

register value by adding an 8-bit signed offset to it.

Available Relative Direct/

Function

The indirect indexed addressing mode consists of

two sub-modes:

Indirect Instructions

JRxx

Conditional Jump

Call Relative

Indirect Indexed (Short)

CALLR

The pointer address is a byte, the pointer size is a

byte, thus allowing 00 - 1FE addressing space,

and requires 1 byte after the opcode.

The relative addressing mode consists of two sub-

modes:

Indirect Indexed (Long)

Relative (Direct)

The pointer address is a byte, the pointer size is a

word, thus allowing 64 Kbyte addressing space,

and requires 1 byte after the opcode.

The offset follows the opcode.

Relative (Indirect)

The offset is defined in memory, of which the ad-

dress follows the opcode.

Table 23. Instructions Supporting Direct,

Indexed, Indirect and Indirect Indexed

Addressing Modes

Long and Short

Function

Instructions

LD

Load

CP

Compare

AND, OR, XOR

Logical Operations

Arithmetic Addition/subtrac-

tion operations

ADC, ADD, SUB, SBC

BCP

Bit Compare

Short Instructions Only

CLR

Function

Clear

INC, DEC

Increment/Decrement

Test Negative or Zero

1 or 2 Complement

Bit Operations

TNZ

CPL, NEG

BSET, BRES

Bit Test and Jump Opera-

tions

BTJT, BTJF

SLL, SRL, SRA, RLC,

RRC

Shift and Rotate Operations

89/109

ST7263

6.2 INSTRUCTION GROUPS

The ST7 family devices use an Instruction Set

consisting of 63 instructions. The instructions may

be subdivided into 13 main groups as illustrated in

the following table:

Load and Transfer

LD

CLR

POP

DEC

TNZ

OR

Stack operation

PUSH

INC

RSP

BCP

Increment/Decrement

Compare and Tests

Logical operations

CP

AND

BSET

BTJT

ADC

SLL

XOR

CPL

NEG

Bit Operation

BRES

BTJF

ADD

SRL

JRT

Conditional Bit Test and Branch

Arithmetic operations

Shift and Rotates

SUB

SRA

JRF

SBC

RLC

JP

MUL

RRC

CALL

SWAP

CALLR

SLA

Unconditional Jump or Call

Conditional Branch

JRA

JRxx

TRAP

SIM

NOP

RET

Interruption management

Code Condition Flag modification

WFI

RIM

HALT

SCF

IRET

RCF

Using a pre-byte

The instructions are described with one to four

bytes.

These prebytes enable instruction in Y as well as

indirect addressing modes to be implemented.

They precede the opcode of the instruction in X or

the instruction using direct addressing mode. The

prebytes are:

In order to extend the number of available op-

codes for an 8-bit CPU (256 opcodes), three differ-

ent prebyte opcodes are defined. These prebytes

modify the meaning of the instruction they pre-

cede.

PDY 90 Replace an X based instruction using

immediate, direct, indexed, or inherent

addressing mode by a Y one.

The whole instruction becomes:

PC-2 End of previous instruction

PC-1 Prebyte

PIX 92 Replace an instruction using direct, di-

rect bit, or direct relative addressing

mode to an instruction using the corre-

sponding indirect addressing mode.

It also changes an instruction using X

indexed addressing mode to an instruc-

tion using indirect X indexed addressing

mode.

PC

Opcode

PC+1 Additional word (0 to 2) according to the

number of bytes required to compute the

effective address

PIY 91 Replace an instruction using X indirect

indexed addressing mode by a Y one.

90/109

ST7263

INSTRUCTION GROUPS (Cont’d)

Mnemo

ADC

ADD

AND

BCP

Description

Add with Carry

Function/Example

A = A + M + C

A = A + M

Dst

Src

H

I

N

Z

C

A

M

Z

Addition

A

Logical And

A = A . M

A

Bit compare A, Memory

Bit Reset

tst (A . M)

A

BRES

BSET

BTJF

BTJT

CALL

CALLR

CLR

bres Byte, #3

bset Byte, #3

btjf Byte, #3, Jmp1

btjt Byte, #3, Jmp1

M

Bit Set

Jump if bit is false (0)

Jump if bit is true (1)

Call subroutine

Call subroutine relative

Clear

C

reg, M

reg

0

N

1

Z

CP

Arithmetic Compare

One Complement

Decrement

tst(Reg - M)

A = FFH-A

dec Y

M

C

1

CPL

reg, M

DEC

HALT

IRET

INC

Halt

0

I

Interrupt routine return

Increment

Pop CC, A, X, PC

inc X

H

N

Z

C

reg, M

JP

Absolute Jump

Jump relative always

Jump relative

jp [TBL.w]

JRA

JRT

JRF

Never jump

jrf *

JRIH

JRIL

Jump if ext. interrupt = 1

Jump if ext. interrupt = 0

Jump if H = 1

JRH

H = 1 ?

JRNH

JRM

Jump if H = 0

H = 0 ?

Jump if I = 1

I = 1 ?

JRNM

JRMI

JRPL

JREQ

JRNE

JRC

Jump if I = 0

I = 0 ?

Jump if N = 1 (minus)

Jump if N = 0 (plus)

Jump if Z = 1 (equal)

Jump if Z = 0 (not equal)

Jump if C = 1

N = 1 ?

N = 0 ?

Z = 1 ?

Z = 0 ?

C = 1 ?

JRNC

JRULT

Jump if C = 0

C = 0 ?

Jump if C = 1

Unsigned <

Jmp if unsigned >=

Unsigned >

JRUGE Jump if C = 0

JRUGT Jump if (C + Z = 0)

91/109

ST7263

INSTRUCTION GROUPS (Cont’d)

Mnemo

JRULE

LD

Description

Jump if (C + Z = 1)

Load

Function/Example

Unsigned <=

dst <= src

Dst

Src

H

I

N

Z

C

reg, M

A, X, Y

reg, M

M, reg

X, Y, A

MUL

NEG

NOP

OR

Multiply

X,A = X * A

0

Negate (2’s compl)

No Operation

OR operation

Pop from the Stack

neg $10

C

A = A + M

pop reg

pop CC

push Y

C = 0

A

M

POP

reg

CC

M

H

I

C

0

PUSH

RCF

RET

RIM

Push onto the Stack

Reset carry flag

Subroutine Return

Enable Interrupts

Rotate left true C

Rotate right true C

Reset Stack Pointer

Subtract with Carry

Set carry flag

reg, CC

I = 0

0

RLC

RRC

RSP

SBC

SCF

SIM

C <= Dst <= C

C => Dst => C

S = Max allowed

A = A - M - C

C = 1

reg, M

N

Z

C

A

M

N

Z

C

1

Disable Interrupts

Shift left Arithmetic

Shift left Logic

I = 1

1

SLA

C <= Dst <= 0

0 => Dst => C

Dst7 => Dst => C

A = A - M

reg, M

A

N

0

Z

C

SLL

SRL

SRA

SUB

SWAP

TNZ

TRAP

WFI

Shift right Logic

Shift right Arithmetic

Subtraction

N

M

SWAP nibbles

Dst[7..4] <=> Dst[3..0] reg, M

tnz lbl1

Test for Neg & Zero

S/W trap

S/W interrupt

1

0

Wait for Interrupt

Exclusive OR

XOR

A = A XOR M

A

M

N

Z

92/109

ST7263

7 ELECTRICAL CHARACTERISTICS

7.1 ABSOLUTE MAXIMUM RATINGS

Devices of the ST72 family contain circuitry to pro-

tect the inputs against damage due to high static

voltage or electric fields. Nevertheless, it is recom-

mended that normal precautions be observed in

order to avoid subjecting this high-impedance cir-

cuit to voltages above those quoted in the Abso-

lute Maximum Ratings. For proper operation, it is

connect them to an appropriate logic voltage level

such as V

connect V

or V . it is also recommended to

SS

DD

and V together on application.

DD

(same rem^Da^Drk^Afor V_SSAand V_SS).

All the voltage in the following tables are refer-

enced to V

.

SS

Stresses above those listed as “Absolute Maxi-

mum Ratings” may cause permanent damage to

the device. Functional operation of the device at

these conditions is not implied. Exposure to maxi-

mum rating conditions for extended periods may

affect device reliability.

recommended that the input voltage V be con-

IN

strained within the range:

(V - 0.3V) ≤ V ≤ (V + 0.3V)

SS

IN

DD

To enhance reliability of operation, it is recom-

mended to configure unused I/Os as inputs and to

Table 24. Absolute Maximum Ratings (Voltage Referenced to V_SS)

Symbol

Ratings

Recommended Supply Voltage

Analog Reference Voltage

Value

- 0.3 to +6.0

50

Unit

V

V_DD

V

DDA

|V

- V

|

DD

Max. variations on Power Line

Max. variations on Ground Line

mV

mA

V

DDA

|V

|

SS

50

SSA

I

- I

Total current into V /V

80/80

VDD VSS

DD SS

V_IN

Input Voltage

V_SS- 0.3 to V_DD+ 0.3

T_Lto T_H

V

Output Voltage

V

OUT

T

Ambient Temperature Range

°C

A

0 to + 70

-65 to +150

150

T_STG

T_J

Storage Temperature Range

Junction Temperature

Power Dissipation

°C

PD

350

mW

V

ESD

ESD susceptibility

2000

93/109

ST7263

7.2 THERMAL CHARACTERISTICS

The average chip-junction temperature, T , in de-

grees Celsius, may be calculated using the follow-

ing equation:

An approximate relationship between P and T

D J

J

(if P is neglected) is given by:

I/O

P = K÷ (T + 273°C) (2)

D

J

T = T + (P x θJ ) (1)*

J

A

D

A

Therefore:

K = P x (T + 273°C) + θJ x P

D

Where:

– T is the Ambient Temperature in °C,

2

A

(3)

D

A

– θJ is the Package Junction-to-Ambient Thermal

A

Resistance, in °C/W,

Where:

– P is the sum of P

and P

,

I/O

D

INT

– P

is the product of I

V

, expressed in

INT

DD and DD

– K is a constant for the particular part, which may

be determined from equation (3) by measuring

Watts. This is the Chip Internal Power

– P represents the Power Dissipation on Input

and Output Pins; User Determined.

I/O

P (at equilibrium) for a known T Using this val-

D

A.

ue of K, the values of P and T may be obtained

D

J

For most applications P <P

glected. P may be significant if the device is con-

figuredtodriveDarlingtonbasesorsinkLEDLoads.

and may be ne-

by solving equations (1) and (2) iteratively for any

I/O

INT

value of T .

I/O

A

Table 25. Thermal Characteristics

Symbol

θJ

Package

SO34

Typical Value

Unit

70

°C/W

A

PSDIP32

50

(*): Maximum chip dissipation can directly be obtained from T (max), θ and T parameters.

j

JA

A

94/109

ST7263

7.3 OPERATING CONDITIONS

General Operating Conditions

(T_A= 0 to +70°C unless otherwise specified)

Symbol

Parameter

Conditions

Min

Max

4.00

Unit

f

= 4 MHz ; USB not guaranteed

= 8 MHz ; USB not guaranteed

= 8 MHz or 4 MHz

3.00

V

CPU

V

IT+

1)

V

Supply voltage

4.0

5.25

DD

USB guaranteed

V

f

= 8 MHz or 4 MHz

CPU

5.25

12

5.50

24

USB not guaranteed

f

External clock frequency

MHz

OSC

Note 1: USB 1.1 specifies that the power supply must be between 4.00 and 5.25 Volts. The USB cell is

therefore guaranteed only in that range.

95/109

ST7263

7.4 POWER CONSUMPTION

(T_A= 0 to +70°C unless otherwise specified)

GENERAL

Symbol

Parameter

Conditions

Min

4

Typ.

Max

Unit

RUN & WAIT mode

V

Operating Supply Voltage

f

= 24 MHz

= 8 MHz

5

5.5

V

DD

OSC

CPU

V

Analog Reference Voltage

CPU RUN mode (see Note 1)

CPU WAIT mode (See Note 2)

CPU HALT mode (see Note 3)

USB Suspend mode (see Note 4)

4

5

14

8

5.5

20

V

DDA

mA

µA

I/O in input mode

12

f

= 8 MHz,

CPU

I

DD

°

T = 20 C

100

450

A

(For V : see Note 5)

350

DD

Note 1: All peripherals running.

Note 2: Oscillator, 16-bit Timer (free running counter) and watchdog running.

All others peripherals (including EPROM/RAM memories) disabled.

Note 3: CPU in HALT mode, USB Transceiver disabled, Low Voltage Reset function enabled.

Note 4: Low voltage reset function enabled.

CPU in HALT mode.

USB in suspend mode. External pull-up (1.5Kohms to USBVCC) and pull-down (15Kohms to V

connected on drivers.

)

SSA

Note 5:

V

= 5.5 V except in USB Suspend mode where V = 5.25 V

DD DD

96/109

ST7263

7.5 I/O PORT CHARACTERISTICS

(T_A= 0 to +70°C unless otherwise specified)

STANDARD I/O PORT PINS

Symbol

Parameter

Conditions

= -25mA V =5V

Min

Typ

Max

Unit

Output Low Level Voltage Port A1,

Port A2 (High Current open drain)

I

-

1.5

0.4

1.3

-

V

OL

DD

Output Low Level Voltage Port A0,

Port A(3:7), Port C(0:2), Push Pull

V

= -1.6mA V =5V

-

V

OL

DD

Output Low Level Voltage Port B (0:7),

Push Pull

= -10mA V =5V

DD

Output High Level Voltage Port A0,

Port A(3:7), Port C(0:2) Push Pull

V

I

= 1.6mA

= 10mA

V

-0.8

OH

DD

Output High Level Voltage Port B (0:7)

Push Pull

I

-1.3

-

V

OH

DD

Input High Level Voltage

PA(0:7),PB(0:7),PC(0:2),RESET

V

Leading Edge

Trailing Edge

0.7xV

V

DD

IH

DD

Input Low Voltage PA(0-7),

PB(0-7), PC(0-2), RESET

Pull-up resistor

V

0.3xV

DD

IL

SS

R

V

= 5V

80

100

5

120

kΩ

PU

DD

1)

CIO

I/O Pin Capacitance

pF

Output High to Low Level Fall Time

All I/O ports

2)

t

25

ns

f(IO)out

CL=50pF

Between 10% and 90%

Output Low to High Level Rise Time

I/O ports in Push Pull mode

2)

t

r(IO)out

1)

External Interrupt pulse time

1

t

CPU

All voltages are referred to V unless otherwise specified.

SS

Note 1: Guaranteed by design, not tested in production.

Note 2: Data based on characterization results, not tested in production.

97/109

ST7263

7.6 LOW VOLTAGE DETECTOR (LVD) CHARACTERISTICS

LOW VOLTAGE RESET Electrical Specifications

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Low Voltage Reset Threshold

V

Max. Variation

50mV/µs

DD

V

3.6

3.75

4.0

V

IT+

V

rising

DD

Low Voltage Reset Threshold

falling

Max. Variation

50mV/µs

DD

V

3.2

3.5

3.7

V

IT-

V

DD

V

Hysteresis (V

- V )

IT-

200

250

mV

hys

IT+

7.7 CONTROL TIMING CHARACTERISTICS

(Operating conditions T_A= 0 to +70°C unless otherwise specified)

CONTROL TIMINGS

Value

Typ.

Symbol

Parameter

Conditions

Unit

Min

Max

f_OSC

f_CPU

Oscillator Frequency

Operating Frequency

External RESET

24

8

MHz

t_RL

1.5

t_CPU

Input pulse Width

t_PORL

Internal Power Reset Duration

4096

200

t_CPU

ns

Watchdog & Low Voltage Reset

Output Pulse Width

T_DOGL

49152

6

3145728

384

t_CPU

ms

t_DOG

Watchdog Time-out

f_cpu= 8MHz

Crystal Oscillator

Start-up Time

t

50

ms

OXOV

t_DDR

Power up rise time

from V = 0 to 4V

100

DD

Note 1: The minimum period t_ILILshould not be less than the number of cycle times it takes to execute the

interrupt service routine plus 21 cycles.

C

98/109

ST7263

7.8 COMMUNICATION INTERFACE CHARACTERISTICS

The values given in the specifications of dedicated

functions are generally not applicable for chips.

Therefore, only the limits listed below are valid for

the product. T = 0... +70°C, V - V = 5 V unless

DD

SS

^{otherwise specified}.

7.8.1 USB - Universal Bus Interface

(Operating conditions T_A= 0 to +70°C, V = 4.0 to 5.25V unless otherwise specified)

DD

USB DC Electrical Characteristics

Parameter

Input Levels:

Symbol

Conditions

Min.

Max.

Unit

Differential Input Sensitivity

Differential Common Mode Range

Single Ended Receiver Threshold

Output Levels

VDI

VCM

VSE

I(D+, D-)

0.2

0.8

V

Includes VDI range

2.5

2.0

Static Output Low

VOL

VOH

RL of 1.5K ohms to 3.6v

0.3

3.6

V

Static Output High

RL of 15K ohm to V

2.8

SS

USBVCC: voltage level

USBV

V

=5v

3.00

3.60

DD

Note 1: RL is the load connected on the USB drivers.

Note 2: All the voltages are measured from the local ground potential.

99/109

ST7263

COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d)

Figure 44. USB: Data signal Rise and fall time

Differential

Data Lines

Crossover

points

VCRS

V_SS

tr

tf

USB: Low speed electrical characteristics

Parameter

Driver characteristics:

Rise time

Symbol

Conditions

Min

75

Max

Unit

tr

tf

Note 1,CL=50 pF

Note 1, CL=600 pF

Note 1, CL=50 pF

Note 1, CL=600 pF

tr/tf

ns

%

300

Fall Time

75

300

120

Rise/ Fall Time matching

trfm

80

Output signal Crossover

Voltage

VCRS

1.3

2.0

V

Note1: Measured from 10% to 90% of the data signal. For more detailed informations, please refer to Chapter 7 (Elec-

trical) of the USB specification (version 1.1).

100/109

ST7263

COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d)

2

7.8.2 I C - Inter IC Control Interface

2

I C/DDC-Bus Timings

2

Standard I C

Fast I C

Min Max

Parameter

Symbol

Unit

ms

Min

Max

Bus free time between a STOP and START con-

dition

4.7

1.3

0.6

T

BUF

Hold time START condition. After this period,

the first clock pulse is generated

LOW period of the SCL clock

HIGH period of the SCL clock

Set-up time for a repeated START condition

Data hold time

4.0

T

µs

HD:STA

4.7

1.3

0.6

T

µs

ns

pF

LOW

4.0

HIGH

SU:STA

HD:DAT

SU:DAT

R

4.7

0 (1)

250

0 (1)

0.9(2)

Data set-up time

100

Rise time of both SDA and SCL signals

Fall time of both SDA and SCL signals

Set-up time for STOP condition

Capacitive load for each bus line

1000

300

20+0.1Cb

0.6

300

TF

4.0

T

:

SU STO

400

Cb

1) The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined

region of the falling edge of SCL

2) The maximum hold time of the START condition has only to be met if the interface does not stretch the low period of

SCL signal

Cb = total capacitance of one bus line in pF

101/109

ST7263

7.9 8-BIT ADC CHARACTERISTICS

GE

Digital Result ADCDR

(1) Example of an actual transfer curve

(2) The ideal transfer curve

(3) End point correlation line

255

V

– V

254

253

DDA

SSA

1LSB

= ----------------------------------------

ideal

256

(2)

TUE=Total Unadjusted Error: maximum deviation

between the actual and the ideal transfer curves.

(3)

TUE

7

6

5

4

3

2

1

OE=Offset Error: deviation between the first actual

transition and the first ideal one.

(1)

GE=Gain Error: deviation between the last ideal

transition and the last actual one.

DLE=Differential Linearity Error: maximum devia-

tion between actual steps and the ideal one.

ILE

OE

ILE=Integral Linearity Error: maximum deviation

between any actual transition and the end point

correlation line.

DLE

1 LSB (ideal)

V

(LSB

)

ideal

in

0

1

2

3

4

5

6

7

253 254 255 256

V_DDA

V

SSA

ADC Analog to Digital Converter (8-bit)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

|TUE|

OE

Total unadjusted error*

Offset error*

2

1

2

1

2

-1

-2

f

V

=f

=V

=4MHz

=5V

DDA

ADC CPU

GE

Gain Error*

LSB

DD

|DLE|

|ILE|

Differential linearity error*

Integral linearity error*

Conversion range voltage

A/D conversion supply current

Stabilization time after enable ADC

V

AIN

ADC

STAB

SSA

DDA

I

t

1

mA

µs

30

f

V

=f

=V

=4MHz

=5V

8

32

µs

1/f

ADC CPU

t

Sample capacitor loading time

Hold conversion time

LOAD

CONV

DD

DDA

ADC

8

32

µs

1/f

t

ADC

R

C

External input resistor

Internal input resistor

Sample capacitor

20

18

22

ΚΩ

AIN

ΚΩ

ADC

pF

SAMPLE

*Note: ADC Accuracy vs. Negative Injection Current:

For I =0.8mA, the typical leakage induced inside the die is 1.6µA and the effect on the ADC accuracy is a loss of 1 LSB

inj-

by 10KΩ increase of the external analog source impedance.

These measurements results and recommandations are done in the worst condition of injection:

- negative injection

- injection to an Input with analog capability ,adjacent to the enabled Analog Input

- at 5V V supply, and worse temperature case.

DD

102/109

ST7263

8-BIT ADC CHARACTERISTICS (Cont’d)

V

Sampling

Switch

DD

V = 0.6V

R

T

AIN

V

AIN

SS

Px.x/AINx

C

5pF

C

hold

22.4 pF

C

= input capacitance

= threshold voltage

= sampling switch

V

T

leakage

±1µA

V = 0.6V

T

SS

C

V

= sample/hold

capacitance

SS

hold

leakage

= leakage current

at the pin due

to various junctions

103/109

ST7263

8 PACKAGE CHARACTERISTICS

8.1 PACKAGE MECHANICAL DATA

Figure 45. 34-Pin Shrink Plastic Small Outline Package, 300-mil Width

mm

inches

Dim.

Min Typ Max Min Typ Max

A

2.46

2.64 0.097

0.29 0.005

0.48 0.014

0.32 0.0091

18.06 0.698

7.59 0.292

0.104

0.0115

0.019

0.0125

0.711

0.299

A1 0.13

B

C

D

E

e

0.36

0.23

0.10mm

.004

seating plane

17.73

7.42

1.02

0.040

H

h

10.16

0.64

10.41 0.400

0.74 0.025

0°

0.410

0.029

8°

K

L

0.61

1.02 0.024

0.040

Number of Pins

N

34

SO34S

Figure 46. 32-Pin Shrink Plastic Dual in Line Package, 400-mil Width

E

mm

inches

Dim.

Min Typ Max Min Typ Max

See Lead Detail

A

3.56 3.76 5.08 0.140 0.148 0.200

A1 0.51

A2 3.05 3.56 4.57 0.120 0.140 0.180

0.36 0.46 0.58 0.014 0.018 0.023

b1 0.76 1.02 1.40 0.030 0.040 0.055

0.020

C

e_A

b1

b

e

B

e

C

D

E

0.20 0.25 0.36 0.008 0.010 0.014

27.43 27.94 28.45 1.080 1.100 1.120

9.91 10.41 11.05 0.390 0.410 0.435

3

D

A

2

N

E1 7.62 8.89 9.40 0.300 0.350 0.370

A

L

e

1.78

0.070

0.400

E

1

A

eA

eB

L

10.16

1

12.70

0.500

e

VR01725J

2.54 3.05 3.81 0.100 0.120 0.150

1

N/2

Number of Pins

N

32

104/109

ST7263

Figure 47. 32-Pin Shrink Ceramic Dual In-Line Package

mm

Min Typ Max Min Typ Max

3.63 0.143

inches

Dim.

A

A1 0.38

0.015

B

0.36 0.46 0.58 0.014 0.018 0.023

B1 0.64 0.89 1.14 0.025 0.035 0.045

C

D

0.20 0.25 0.36 0.008 0.010 0.014

29.41 29.97 30.53 1.158 1.180 1.202

D1

E

26.67

10.16

1.050

0.400

E1 9.45 9.91 10.36 0.372 0.390 0.408

e

G

1.78

9.40

14.73

1.12

3.30

7.37

0.070

0.370

0.580

0.044

0.130

0.290

G1

G2

L

Ø

Number of Pins

32

CDIP32SW

N

105/109

ST7263

9 DEVICE CONFIGURATION AND ORDERING INFORMATION

The following section deals with the procedure for

transfer of customer codes to STMicroelectronics.

9.1 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE

Customer code is made up of the ROM contents.

The ROM contents are to be sent on diskette, or

by electronic means, with the hexadecimal file in

.S19 format generated by the development tool.

All unused bytes must be set to FFh.

The customer code should be communicated to

STMicroelectronics with the correctly completed

OPTION LIST appended.

The STMicroelectronics Sales Organization will be

pleased to provide detailed information on con-

tractual points.

Figure 48. Sales Type Coding Rules

Family

Version Code

Sub family

Subset Index

Number of pins

ROM Size Code

Package Type

Temperature Code

ROM Code (three letters)

ST72 T 63 1 K 4 B 1 / xxx

0 = 25°C

B = Plastic DIP

4 = 16K K = 32/34 pins No letter = ROM

1 = Standard (0 to +70°C) D = Ceramic DIP 2 = 8K

M = Plastic SO 1 = 4K

E = EPROM

T = OTP

Subset index : 1 = fully featured; other number = downgraded versions

Table 26. Ordering Information

Note 1. /xxx stands for the ROM code name as-

signed by STMicroelectronics.

Program

Memory

(bytes)

RAM

1)

Sales Type

Package

(bytes)

Table 27. Development Tools

ST72E631K4D0

ST72631K4M1/xxx

ST72T631K4M1

ST72631K4B1/xxx

ST72T631K4B1

ST72632K2M1/xxx

ST72T632K2M1

ST72632K2B1/xxx

ST72T632K2B1

ST72633K1M1/xxx

ST72T633K1M1

ST72633K1B1/xxx

ST72T633K1B1

16K EPROM

16K ROM

16K OTP

16K ROM

16K OTP

8K ROM

8K OTP

CSDIP32

SO34

Development Tool

Sales Type

Remarks

Real time emulator ST7263-EMU2

512

220V Power

Supply

EPROM

ST72E63-EPB/EU

PSDIP32

SO34

Programming

ST72E63-EPB/US

Board

110V Power

Supply

256

8K ROM

8K OTP

PSDIP32

SO34

4K ROM

4K OTP

4K ROM

4K OTP

PSDIP32

106/109

ST7263

ST7263X MICROCONTROLLER OPTION LIST

Customer: . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Address:

. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contact:

Phone No: . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reference : . . . . . . . . . . . . . . . . . . . . . . . . . . . .

STMicroelectronics references:

Device:

[ ] ST72631K4

[ ] ST72632K2

[ ] ST72633K1

Package:

[ ] Dual in Line Plastic

[ ] Small Outline Plastic

Specify conditioning

[ ] Standard (stick)

[ ] Tape & Reel

[ ] Die form

Specify conditioning

[ ] Inked unscribed wafers

[ ] Inked and scribed wafers

Special Marking:

[ ] No

[ ] Yes "_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _"

For marking, one line is possible with maximum 13 characters.

Authorized characters are letters, digits, ’.’, ’-’, ’/’ and spaces only.

We have checked the ROM code verification file returned to us by STMicroelectronics. It conforms

exactly with the ROM code file orginally supplied. We therefore authorize STMicroelectronics to

proceed with device manufacture.

Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Date

. . . . . . . . . . . . . . . . . . . . . . . . . . . .

107/109

ST7263

9.2 ST7 APPLICATION NOTES

IDENTIFICATION

DESCRIPTION

PROGRAMMING AND TOOLS

AN985

AN986

EXECUTING CODE IN ST7 RAM

USING THE ST7 INDIRECT ADDRESSING MODE

AN987

ST7 IN-CIRCUIT PROGRAMMING

AN988

AN989

STARTING WITH ST7 ASSEMBLY TOOL CHAIN

STARTING WITH ST7 HIWARE C

AN1039

AN1064

AN1106

EXAMPLE DRIVERS

AN969

AN970

AN971

AN972

ST7 MATH UTILITY ROUTINES

WRITING OPTIMIZED HIWARE C LANGUAGE FOR ST7

TRANSLATING ASSEMBLY CODE FROM HC05 TO ST7

ST7 SCI COMMUNICATION BETWEEN THE ST7 AND A PC

ST7 SPI COMMUNICATION BETWEEN THE ST7 AND E²PROM

ST7 I²C COMMUNICATION BETWEEN THE ST7 AND E²PROM

ST7 SOFTWARE SPI MASTER COMMUNICATION

AN973

AN974

AN976

AN979

SCI SOFTWARE COMMUNICATION WITH A PC USING ST72251 16-BIT TIMER

REAL TIME CLOCK WITH THE ST7 TIMER OUTPUT COMPARE

DRIVING A BUZZER USING THE ST7 PWM FUNCTION

DRIVING AN ANALOG KEYBOARD WITH THE ST7 ADC

ST7 KEYPAD DECODING TECHNIQUES, IMPLEMENTING WAKE-UP ON KEYSTROKE

USING THE ST7 USB MICROCONTROLLER

USING ST7 PWM SIGNAL TO GENERATE ANALOG OUTPUT (SINUSOID)

ST7 ROUTINE FOR I²C SLAVE MODE MANAGEMENT

MULTIPLE INTERRUPT SOURCES MANAGEMENT FOR ST7 MCUS

ST7 SOFTWARE IMPLEMENTATION OF I²C BUS MASTER

ST7 UART EMULATION SOFTWARE

MANAGING RECEPTION ERRORS WITH THE ST7 SCI PERIPHERAL

ST7 SOFTWARE LCD DRIVER

ST7 TIMER PWM DUTY CYCLE SWITCH FOR TRUE 0% or 100% DUTY CYCLE

DESCRIPTION OF THE ST72141 MOTOR CONTROL

ST72141 BLDC MOTOR CONTROL SOFTWARE AND FLOWCHART EXAMPLE

PWM MANAGEMENT FOR BLDC MOTOR DRIVES USING THE ST72141

BRUSHLESS DC MOTOR DRIVE WITH ST72141

AN980

AN1017

AN1041

AN1042

AN1044

AN1045

AN1046

AN1047

AN1048

AN1078

AN1082

AN1083

AN1129

AN1130

AN1148

AN1149

AN1180

AN1182

USING THE ST7263 FOR DESIGNING A USB MOUSE

HANDLING SUSPEND MODE ON A USB MOUSE

USING THE ST7263 KIT TO IMPLEMENT A USB GAME PAD

USING THE ST7 USB LOW-SPEED FIRMWARE

PRODUCT OPTIMIZATION

AN982

USING CERAMIC RESONATORS WITH THE ST7

AN1014

AN1070

AN1179

HOW TO MINIMIZE THE ST7 POWER CONSUMPTION

ST7 CHECKSUM SELFCHECKING CAPABILITY

PROGRAMMING ST7 FLASH MICROCONTROLLERS IN REMOTE ISP

PRODUCT EVALUATION

AN910

ST7 AND ST9 PERFORMANCE BENCHMARKING

AN990

ST7 BENEFITS VERSUS INDUSTRY STANDARD

ST7 / ST10U435 CAN-do SOLUTIONS FOR CAR MULTIPLEXING

BENCHMARK ST72 VS PC16

AN1086

AN1150

AN1151

PERFORMANCE COMPARISON BETWEEN ST72254 & PC16F8

9.3 TO GET MORE INFORMATION

To get the latest information on this product please use the ST web server: http://mcu.st.com/

108/109

ST7263

10 SUMMARY OF CHANGES

Description of the changes between the current release of the specification and the previous one.

Revision

Main changes

Date

Changed status of the document (datasheet instead of preliminary data).

Added Section 9.2 and section 9.3 on page 108.

1.8

August 00

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics

Purchase of I²C Components by STMicroelectronics conveys a license under the Philips I²C Patent. Rights to use these components in an

I²C system is granted provided that the system conforms to the I²C Standard Specification as defined by Philips.

STMicroelectronics Group of Companies

Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain

Sweden - Switzerland - United Kingdom - U.S.A.

http://www.st.com

109/109


型号：	ST72631K1B0
厂家：	ST
描述：	LOW SPEED USB 8-BIT MCU FAMILY with up to 16K MEMORY, up to 512 BYTES RAM, 8-BIT ADC, WDG, TIMER, SCI & I2C 低速USB 8位单片机系列具有高达16K内存，高达512字节的RAM ， 8位ADC ， WDG ，定时器， SCI， I2C
文件：	总109页 (文件大小：854K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ST72631K1B0 [STMICROELECTRONICS]

相关型号：

ST72631K1B1

ST72631K1D0

ST72631K1D1

ST72631K1M0

ST72631K1M1

ST72631K2B0

ST72631K2B1

ST72631K2D0

ST72631K2D1

ST72631K2M0

ST72631K2M1

ST72631K4