ST7263BK2U1/XXX [STMICROELECTRONICS]
8-BIT, MROM, 8MHz, MICROCONTROLLER, QCC40, 6 X 6 MM, ROHS COMPLIANT, QFN-40;
| 型号： | ST7263BK2U1/XXX |
| 厂家： | 
ST |
| 描述： | 8-BIT, MROM, 8MHz, MICROCONTROLLER, QCC40, 6 X 6 MM, ROHS COMPLIANT, QFN-40 闪存 |
| 文件： | 总145页 (文件大小：2981K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ST7263BDx ST7263BHx
ST7263BKx ST7263BE
Low speed USB 8-bit MCU family with up to 32K Flash/ROM,
DFU capability, 8-bit ADC, WDG, timer, SCI & I²C
■ Memories
– 4, 8, 16 or 32 Kbytes program memory: high
density Flash (HDFlash), FastROM or ROM
with Read-Out and Write protection
– In-application programming (IAP) and in-cir-
cuit programming (ICP)
– 384, 512 or 1024 bytes RAM memory (128-
byte stack)
PSDIP32
LQFP48 (7x7)
QFN40 (6x6)
■ Clock, reset and supply management
– Run, Wait, Slow and Halt CPU modes
– 12 or 24 MHz oscillator
SO34(Shrink)
■ 2 timers
– Programmable watchdog
SO24
– RAM Retention mode
– Optional low voltage detector (LVD)
■ USB (universal serial bus) Interface
– DMA for low speed applications compliant
with USB 1.5 Mbs (version 2.0) and HID spec-
ifications (version 1.0)
– 16-bit timer with 2 Input Captures, 2 Output
Compares, PWM output and clock input
■ 2 communication Interfaces
– Asynchronous serial communications Inter-
face
– I²C multimaster Interface up to 400 kHz
■ Instruction Set
– Integrated 3.3 V voltage regulator and trans-
ceivers
– Supports USB DFU class specification
– Suspend and Resume operations
– 3 endpoints with programmable Input/Output
configuration
– 63 basic instructions
– 17 main addressing modes
– 8 x 8 unsigned multiply instruction
– True bit manipulation
■ Up to 27 I/O ports
– Up to 8 high sink I/Os (10 mA at 1.3 V)
– 2 very high sink true open drain I/Os (25 mA
at 1.5 V)
■ Development tools
– Versatile development tools (under Windows)
including assembler, linker, C-compiler, ar-
chiver, source level debugger, software li-
brary, hardware emulator, programming
boards and gang programmers, HID and DFU
software layers
– Up to 8 lines individually programmable as in-
terrupt inputs
■ 1 analog peripheral
– 8-bit A/D converter with 8 or 12 channels
Table 1. Device summary
ST7263BE1, ST7263BE2,
ST7263BE4, ST7263BE6
ST7263BH2,
ST7263BH6
ST7263BK1, ST7263BK2, ST7263BK4,
ST7263BK6
ST7263BD6
Features
Program memory
(Flash / ROM) - bytes
32K
16K
8K
32K
32K 16K
8K
4K
32K
16K
512
8K
4K
1024 512
(128) (128) (128)
384
1024
(128)
1024 512
(128) (128)
384
(128)
384 1024
(128) (128) (128) (128) (128)
384
384
RAM (stack) - bytes
Standard peripherals
Other peripherals
I/Os (high current)
Operating supply
CPU frequency
Watchdog timer, 16-bit timer, USB
SCI, I²C, ADC
SCI, ADC ADC
SCI, I²C
14 (6)
27 (10)
19 (10)
4.0 V to 5.5 V
8 MHz (with 24 MHz oscillator) or 4 MHz (with 12 MHz oscillator)
0 °C to +70 °C
Operating temp.
QFN40
(6x6)
SDIP32/
SO34
QFN40
(6x6)
Packages
LQFP48 (7x7)
SDIP32/SO34
SO24
Rev. 7.0
August 2007
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1
Table of Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3 Register & memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4 Flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2 Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2.1 Read-Out protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.3 ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.4 ICP (in-circuit programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.5 IAP (in-application programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.6 Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5 Central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.3 CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6 CPU registers (Cont’d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7 Reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.1.1
Low voltage detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.1.2 Watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.1.3 External reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.2 Clock system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.2.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.2.2 External clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8.1 Interrupt register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
9 Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9.2 Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9.3 Slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
9.4 Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
10 I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
10.2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
10.3 I/O port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
10.3.1 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10.3.2 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
10.3.3 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
10.3.4 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
10.3.5 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
11 Miscellaneous register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
12 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
12.1 Watchdog timer (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
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12.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
12.1.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
12.1.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
12.1.4 Software Watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
12.1.5 Hardware Watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
12.1.6 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
12.1.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
12.1.8 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
12.2 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
12.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
12.2.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
12.2.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
12.2.4 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
12.2.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
12.2.6 Summary of timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
12.2.7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
12.3 Serial communications interface (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
12.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
12.3.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
12.3.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
12.3.4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
12.3.5 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
12.3.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
12.3.7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
12.4 USB interface (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
12.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
12.4.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
12.4.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
12.4.4 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
12.4.5 Programming considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
12.5 I²C bus interface (I²C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
12.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
12.5.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
12.5.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
12.5.4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
12.5.5 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
12.5.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
12.5.7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
12.6 8-bit A/D converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
12.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
12.6.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
12.6.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
12.6.4 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
12.6.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
12.6.6 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
13 Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
13.1 ST7 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
13.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
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13.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
13.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
13.1.4 Indexed (No Offset, Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
13.1.5 Indirect (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
13.1.6 Indirect Indexed (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
13.1.7 Relative mode (Direct, Indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
13.2 insTruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
14 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
14.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
14.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
14.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
14.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
14.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
14.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
14.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
14.2.1 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
14.2.2 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
14.2.3 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
14.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
14.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
14.3.2 Operating conditions with Low Voltage Detector (LVD) . . . . . . . . . . . . . . . . . . . 110
14.4 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
14.5 Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
14.5.1 General timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
14.5.2 Control timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
14.5.3 External clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
14.6 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
14.6.1 RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
14.6.2 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
14.7 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
14.7.1 Functional EMS (Electromagnetic susceptibility) . . . . . . . . . . . . . . . . . . . . . . . . . 115
14.7.2 Electromagnetic interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
14.7.3 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . . . . . . . . 116
14.8 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
14.8.1 General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
14.8.2 Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
14.9 Control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
14.9.1 Asynchronous RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
14.10Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
14.10.1 USB - universal bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
14.10.2 SCI - serial communication interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
14.10.3 I2C - Inter IC control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
14.118-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
15 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
15.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
15.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
4/145
Table of Contents
15.3 Soldering and glueability information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
16 Device configuration and ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
16.1 Option Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
16.2 Device ordering information and transfer of customer code . . . . . . . . . . . . . . . . . . . . . . . 134
16.3 Development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
16.3.1 Evaluation tools and starter kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
16.3.2 Development and debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
16.3.3 Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
16.3.4 Order codes for ST7263B development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
16.4 ST7 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
17 Known limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
17.1 PA2 limitation with OCMP1 enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
17.2 Unexpected reset fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
17.3 USB behavior with LVD disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
17.4 I2C multimaster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
17.5 Halt mode power consumption with ADC on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
17.6 SCI wrong break duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
18 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
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ST7263BDx ST7263BHx ST7263BKx ST7263BE
1 Introduction
The ST7263B microcontrollers form a sub-family
of the ST7 MCUs dedicated to USB applications.
The devices are based on an industry-standard 8-
bit core and feature an enhanced instruction set.
They operate at a 24 MHz or 12 MHz oscillator fre-
quency. Under software control, the ST7263B
MCUs may be placed in either Wait or Halt modes,
regulator and transceivers (no external compo-
nents are needed).
– 8-bit analog-to-digital converter (ADC) with 12
multiplexed analog inputs
– Industry standard asynchronous SCI serial inter-
face
thus reducing power consumption. The enhanced
instruction set and addressing modes afford real
programming potential. In addition to standard 8-
bit data management, the ST7263B MCUs feature
true bit manipulation, 8x8 unsigned multiplication
and indirect addressing modes. The devices in-
clude an ST7 Core, up to 32Kbytes of program
memory, up to 1024 bytes of RAM, 27 I/O lines
and the following on-chip peripherals:
– Watchdog
– 16-bit timer featuring an external clock input, 2
Input Captures, 2 Output Compares with Pulse
Generator capabilities
– Fast I²C multimaster interface
– Low voltage reset (LVD) ensuring proper power-
on or power-off of the device
The ST72F63B devices are Flash versions. They
support programming in IAP mode (in-application
programming) via the on-chip USB interface.
– USB low speed interface with 3 endpoints with
programmable in/out configuration using the
DMA architecture with embedded 3.3V voltage
Figure 1. General block diagram
INTERNAL
CLOCK
OSC/3
OSCIN
OSCILLATOR
OSCOUT
I²C
OSC/4 or OSC/2
2)
for USB
PA[7:0]
(8 bits)
V
PORT A
DD
POWER
SUPPLY
V
SS
16-BIT TIMER
WATCHDOG
CONTROL
PORT B
PB[7:0]
RESET
(8 bits)
1)
ADC
8-BIT CORE
ALU
PD[7:0]
(8 bits)
PORT D
LVD
PORT C
USB DMA
PC[2:0]
(3 bits)
SCI
V
/TEST
PROGRAM
MEMORY
PP
(UART)
V
(32K bytes)
DDA
USBDP
USBDM
USBVCC
USB SIE
V
SSA
RAM
(1024 bytes)
1)
ADC channels:
12 on 48-pin devices (Port B and Port D[3:0])
8 on 34 and 32-pin devices (Port B)
None on 24-pin devices
2)
3)
12 or 24 MHz OSCIN frequency required to generate 6 MHz USB clock.
The drive from USBVCC is sufficient to only drive an external pull-up in additoin to the internal transceiver
6/145
ST7263BDx ST7263BHx ST7263BKx ST7263BE
2 Pin description
Figure 2. 48-pin LQFP package pinout
48 47 46 45 44 43 42 41 40 39 38 37
PA3/EXTCLK
V
1
36
35
34
33
32
31
30
29
28
27
26
25
SSA
PA4/ICAP1/IT1
PA5/ICAP2/IT2
PA6/OCMP1/IT3
PA7/OCMP2/IT4
PB0(10mA)/AIN0
PB1(10mA)/AIN1
PB2(10mA)/AIN2
PB3(10mA)/AIN3
PB4(10mA)/AIN4/IT5
PB5(10mA)/AIN5/IT6
USBDP
USBDM
USBV
2
3
4
CC
V
5
DDA
V
6
DD
OSCOUT
OSCIN
VSS
7
8
9
USBOE/PC2
NC
10
11
12
V
/TEST
NC
PP
13 14 15 16 17 18 19 20 21 22 23
24
7/145
ST7263BDx ST7263BHx ST7263BKx ST7263BE
Figure 3. 40-lead QFN package pinout
40 39 38 37 36 35 34 33 32 31
PA0/MCO
1
30
29
28
27
26
25
24
23
22
21
PA3/EXTCLK
V
PA4/ICAP1/IT1
PA5/ICAP2/IT2
PA6/OCMP1/IT3
PA7/OCMP2/IT4
PB0(10mA)/AIN0
PB1(10mA)/AIN1
PB2(10mA)/AIN2
PB3(10mA)/AIN3
PB4(10mA)/AIN4/IT5
2
3
SSA
USBDP
USBDM
4
USBV
CC
5
V
6
DDA
V
7
DD
OSCOUT
OSCIN
VSS
8
9
10
11 12 13 14 15 16 17 18 19 20
Note:
1. Port D functions are not available on the 8K version of the QFN40 package (ST7263BK2)
and should not be connected.
8/145
ST7263BDx ST7263BHx ST7263BKx ST7263BE
Pin description (Cont’d)
Figure 4. 34-pin SO package pinout
V
DDA
34
33
32
V
DD
1
2
3
4
5
6
USBVCC
USBDM
OSCOUT
OSCIN
USBDP
V
31
30
29
28
27
26
25
24
23
22
21
20
19
18
SS
V
PC2/USBOE
PC1/TDO
PC0/RDI
RESET
SSA
PA0/MCO
PA1(25mA)/SDA/ICCDATA
7
NC
8
NC
NC
AIN7/IT8/PB7(10mA)
AIN6/PB6/IT7(10mA)
9
NC
10
11
12
13
14
PA2(25mA)/SCL/ICCCLK
V
/TEST
PA3/EXTCLK
PA4/ICAP1/IT1
PA5/ICAP2/IT2
PP
AIN5/IT6/PB5(10mA)
AIN4/IT5/PB4(10mA)
AIN3/PB3(10mA)
AIN2/PB2(10mA)
AIN1/PB1(10mA)
PA6/OCMP1/IT3
PA7/OCMP2/IT4
PB0(10mA)/AIN0
15
16
17
Figure 5. 32-pin SDIP package pinout
V
V
DDA
1
DD
32
USBVCC
OSCOUT
OSCIN
2
3
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
USBDM
USBDP
V
4
SS
V
PC2/USBOE
PC1/TDO
PC0/RDI
RESET
5
SSA
PA0/MCO
6
PA1(25mA)/SDA/ICCDATA
7
NC
8
AIN7/IT8/PB7(10mA)
AIN6/IT7/PB6(10mA)
NC
9
PA2(25mA)/SCL/ICCCLK
10
11
12
13
14
15
16
V
/TEST
PA3/EXTCLK
PP
AIN5/IT6/PB5(10mA)
AIN4/IT5/PB4(10mA)
AIN3/PB3(10mA)
AIN2/PB2(10mA)
AIN1/PB1/(10mA)
PA4/ICAP1/IT1
PA5/ICAP2/IT2
PA6/OCMP1/IT3
PA7/OCMP2/IT4
PB0(10mA)/AIN0
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ST7263BDx ST7263BHx ST7263BKx ST7263BE
Figure 6. 24-pin SO package pinout
24
USBVcc
USBDM
USBDP
V
1
DD
23
OSCOUT
OSCIN
2
22
21
20
19
18
17
16
15
14
13
3
V
V
4
SSA
SS
PA0/MCO
5
TDO/PC1
RDI/PC0
PA1(25mA)/SDA/ICCDATA
PA2(25mA)/SCL/ICCCLK
PA3/EXTCLK
6
RESET/
IT7/PB6(10mA)
7
8
V
/TEST
PB3(10mA)
9
PA4/ICAP1/IT1
PP
10
11
12
PA5/ICAP2/IT2
PA7/OCMP2/IT4
PB0(10mA)
PB2(10mA)
USBOE/PB1(10mA)
RESET (see Note 1): bidirectional. This active low
signal forces the initialization of the MCU. This
event is the top priority non maskable interrupt.
This pin is switched low when the Watchdog is trig-
Note 1: Adding two 100 nF decoupling capacitors
on the Reset pin (respectively connected to VDD
and VSS) will significantly improve product electro-
magnetic susceptibility performance.
gered or the V is low. It can be used to reset ex-
ternal peripherals.
DD
Note 2: To enhance the reliability of operation, it is
recommended that VDDA and VDD be connected to-
gether on the application board. This also applies
OSCIN/OSCOUT: input/output oscillator pin.
These pins connect a parallel-resonant crystal, or
an external source, to the on-chip oscillator.
to VSSA and V
.
SS
Note 3: The USBOE alternate function is mapped
on port C2 in 32/34/48 pin devices. In SO24 devic-
es it is mapped on Port B1.
V
/V
(see Note 2): main power supply and
DD SS
Ground voltages.
V
/V (see Note 2): power supply and
Note 4: The timer OCMP1 alternate function is
mapped on Port A6 in 32/34/48 pin devices. In
SO24 devices it is not available.
DDA SSA
ground voltages for analog peripherals.
Alternate Functions: Several pins of the I/O ports
assume software programmable alternate func-
tions as shown in the pin description.
Legend / Abbreviations for Table 2 and Table 3:
Type:
I = input, O = output, S = supply
In/Output level: C = CMOS 0.3V /0.7V with input trigger
T
DD
DD
Output level:
10mA = 10mA high sink (Fn N-buffer only)
25mA = 25mA very high sink (on N-buffer only)
Port and control configuration:
– Input:
float = floating, wpu = weak pull-up, int = interrupt, ana = analog
OD = open drain, PP = push-pull, T = True open drain
– Output:
The RESET configuration of each pin is shown in
bold. This configuration is kept as long as the de-
vice is under reset state.
10/145
ST7263BDx ST7263BHx ST7263BKx ST7263BE
Table 2. Device pin description (QFN40, LQFP48, SO34 and SDIP32)
Pin n°
Level
Port / Control
Main
function
(after
Input
Output
Pin name
Alternate function
reset)
1
2
3
4
5
1
2
3
4
5
7
8
6
7
8
9
V
S
O
I
Power supply voltage (4V - 5.5V)
Oscillator output
DD
OSCOUT
OSCIN
9
Oscillator input
10
V
S
Digital ground
SS
11 10 PC2/USBOE
12 13 PC1/TDO
I/O
C
C
X
X
X
X
X
Port C2
Port C1
USB Output Enable
T
T
SCI Transmit Data Out-
put
6
6
I/O
7
8
-
7
8
9
-
13 14 PC0/RDI
14 15 RESET
15 16 NC
I/O
I/O
--
C
X
X
Port C0
SCI Receive Data Input
T
X
Reset
Not connected
Not connected
Not connected
Not connected
Not connected
Not connected
Not connected
-
16 17 NC
--
-
-
-
-
-
-
-
18 NC
19 NC
20 NC
21 NC
22 NC
--
-
-
--
-
-
--
-
-
--
-
-
--
9
10 17 23 PB7/AIN7/IT8
I/O
I/O
S
C
C
10mA X
10mA X
X
X
X
X
X
X
Port B7
Port B6
ADC analog input 7
ADC analog input 6
T
T
10 11 18 24 PB6/AIN6/IT7
11 12 19 25 /TEST
V
Programming supply
PP
12 13 20 26 PB5/AIN5/IT6
13 14 21 27 PB4/AIN4/IT5
14 15 22 28 PB3/AIN3
15 16 23 29 PB2/AIN2
16 17 24 30 PB1/AIN1
17 18 25 31 PB0/AIN0
I/O
I/O
I/O
I/O
I/O
I/O
C
C
C
C
C
C
10mA X
10mA X
10mA X
10mA X
10mA X
10mA X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Port B5
Port B4
Port B3
Port B2
Port B1
Port B0
ADC analog input 5
T
T
T
T
T
T
ADC analog input 4
ADC analog input 3
ADC analog input 2
ADC analog input 1
ADC analog Input 0
Timer Output Compare
2
18 19 26 32 PA7/OCMP2/IT4
19 20 27 33 PA6/OCMP1/IT3
I/O
I/O
C
X
X
X
X
X
X
Port A7
Port A6
T
T
Timer Output Compare
1
C
20 21 28 34 PA5/ICAP2/IT2
21 22 29 35 PA4/ICAP1/IT1
22 23 30 36 PA3/EXTCLK
I/O
I/O
I/O
C
C
C
X
X
X
X
X
X
X
X
Port A5
Port A4
Port A3
Timer Input Capture 2
Timer Input Capture 1
Timer External Clock
T
T
T
I²C serial clock, ICC
Clock
23 24 31 38 PA2/SCL/ICCCLK
I/O
I/O
C
C
25mA X
T
Port A2
Port D0
T
T
1)
-
-
32 39 PD0 /AIN8
X
X
X
ADC analog Input 8
11/145
ST7263BDx ST7263BHx ST7263BKx ST7263BE
Pin n°
Level
Port / Control
Main
function
(after
Input
Output
Pin name
Alternate function
reset)
1)
-
-
-
-
-
-
-
-
-
-
33 40 PD1 /AIN9
I/O
I/O
I/O
I/O
I/O
I/O
I/O
--
C
C
C
C
C
C
C
X
X
X
X
X
X
X
X
X
X
X
X
X
Port D1
Port D2
Port D3
Port D4
Port D5
Port D6
Port D7
ADC analog Input 9
ADC analog Input 10
ADC analog Input 11
T
1)
34 41 PD2 /AIN10
T
T
T
T
T
T
1)
-
35 42 PD3 /AIN11
1)
-
36 43 PD4
X
X
X
X
1)
-
37 44 PD5
1)
-
38 45 PD6
1)
-
39 46 PD7
25
-
-
-
-
-
-
NC
NC
NC
Not connected
Not connected
Not connected
24 26
25 27
--
--
I²C serial data, ICC
Data
26 28 40 47 PA1/SDA/ICCDATA
I/O
C
25mA X
T
Port A1
Port A0
T
27 29
28 30
29 31
30 32
31 33
32 34
1
2
3
4
5
6
48 PA0/MCO
I/O
S
C
X
X
Main Clock Output
T
1
2
3
4
5
V
Analog ground
SSA
USBDP
USBDM
USBVCC
I/O
I/O
O
USB bidirectional data (data +)
USB bidirectional data (data -)
2)
2)
USB power supply
V
S
Analog supply voltage
DDA
Note:
1. Port D functions are not available on the 8K version of the QFN40 package (ST7263BK2) and should not be connect-
ed.
2. The drive from USBVcc is sufficient to only drive an external pull-up in addition to the internal transceiver.
Table 3. Device pin description (SO24)
Pin n°
Level
Port / Control
Input Output
Main
Function
(after reset)
Pin Name
Alternate Function
1
2
3
4
V
S
O
I
Power supply voltage (4V - 5.5V)
Oscillator output
DD
OSCOUT
OSCIN
Oscillator input
V
S
Digital ground
SS
SCI Transmit Data Out-
put
5
PC1/TDO
I/O
C
X
X
X
Port C1
T
6
7
PC0/RDI
RESET
I/O
I/O
C
X
X
Port C0
SCI Receive Data Input
T
X
Reset
12/145
ST7263BDx ST7263BHx ST7263BKx ST7263BE
Pin n°
Level
Port / Control
Main
Input
Output
Pin Name
Function
Alternate Function
(after reset)
8
PB6/IT7
/TEST
I/O
S
C
10mA
X
X
X
X
Port B6
T
9
V
Programming supply
Port B3
PP
10
11
12
13
14
15
16
17
PB3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
C
C
C
C
10mA
10mA
10mA
10mA
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
T
T
T
T
PB2
Port B2
PB1/USBOE
PB0
Port B1
Port B0
Port A7
Port A5
Port A4
Port A3
USB Output Enable
PA7/OCMP2/IT4
PA5/ICAP2/IT2
PA4/ICAP1/IT1
PA3/EXTCLK
C
X
X
X
X
X
X
X
Timer Output Compare 2
Timer Input Capture 2
Timer Input Capture 1
Timer External Clock
T
T
T
T
C
C
C
PA2/SCL/
ICCCLK
I²C serial clock,
ICC Clock
18
I/O
C
C
25mA
25mA
X
X
T
Port A2
T
T
19
20
21
22
23
24
PA1/SDA/ICCDATA
PA0/MCO
I/O
I/O
S
T
Port A1
Port A0
I²C serial data, ICC Data
Main Clock Output
C
X
X
T
V
Analog ground
SSA
USBDP
USBDM
USBVCC
I/O
I/O
O
USB bidirectional data (data +)
USB bidirectional data (data -)
USB power supply
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ST7263BDx ST7263BHx ST7263BKx ST7263BE
3 Register & memory map
As shown in Figure 7, the MCU is capable of ad-
dressing 32 Kbytes of memories and I/O registers.
The highest address bytes contain the user reset
and interrupt vectors.
The available memory locations consist of up to
1024 bytes of RAM including 64 bytes of register
locations, and up to 32K bytes of user program
memory in which the upper 32 bytes are reserved
for interrupt vectors. The RAM space includes up
to 128 bytes for the stack from 0100h to 017Fh.
IMPORTANT: Memory locations noted “Re-
served” must never be accessed. Accessing a re-
served area can have unpredictable effects on the
device.
Figure 7. Memory map
0040h
0000h
Short Addressing
HW Registers
RAM (192 bytes)
(See Table 5)
00FFh
003Fh
0040h
0100h
Stack
RAM
(128 bytes)
(384 / 512 / 1024 bytes)
017Fh
0180h
01BF / 023F / 043Fh
01C0 / 0240 / 0440h
16-bit Addressing
RAM
Reserved
01BF / 023F / 043Fh
7FFFh
8000h
8000h
Program Memory
32 Kbytes
(4 / 8 / 16 / 32 Kbytes)
FFDFh
C000h
FFE0h
16 Kbytes
Interrupt & Reset Vectors
E000h
(See Table 4)
8 Kbytes
F000h
FFFFh
4 Kbytes
FFDFh
Table 4. interrupt vector map
Vector address
Description
Masked by
Remarks
Exit from Halt mode
FFE0h-FFEDh
FFEEh-FFEFh
FFF0h-FFF1h
FFF2h-FFF3h
FFF4h-FFF5h
FFF6h-FFF7h
Reserved Area
USB Interrupt Vector
SCI Interrupt Vector
I²C Interrupt Vector
I- bit
I- bit
I- bit
I- bit
I- bit
I- bit
I- bit
None
None
Internal Interrupt
Internal Interrupt
Internal Interrupt
Internal Interrupt
External Interrupt
External Interrupts
Internal Interrupt
CPU Interrupt
No
No
No
TIMER Interrupt Vector
IT1 to IT8 Interrupt Vector
No
Yes
Yes
Yes
No
FFF8h-FFF9h USB End Suspend mode Interrupt Vector
FFFAh-FFFBh Flash Start Programming Interrupt Vector
FFFCh-FFFDh
FFFEh-FFFFh
TRAP (software) Interrupt Vector
RESET Vector
Yes
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ST7263BDx ST7263BHx ST7263BKx ST7263BE
Table 5. Hardware register memory map
Address
Block
Register label
Register name
Port A Data Register
Reset status
Remarks
R/W
0000h
0001h
PADR
00h
00h
Port A
PADDR
Port A Data Direction Register
R/W
0002h
0003h
PBDR
Port B Data Register
00h
00h
R/W
R/W
Port B
Port C
Port D
PBDDR
Port B Data Direction Register
0004h
0005h
PCDR
Port C Data Register
1111 x000b
1111 x000b
R/W
R/W
PCDDR
Port C Data Direction Register
0006h
0007h
PDDR
Port D Data Register
00h
00h
R/W
R/W
PDDDR
Port D Data Direction Register
0008h
0009h
ITC
ITIFRE
MISCR
Interrupt Register
00h
00h
R/W
R/W
MISC
Miscellaneous Register
000Ah
000Bh
ADCDR
ADC Data Register
00h
00h
Read only
R/W
ADC
ADCCSR
ADC control Status register
000Ch
WDG
WDGCR
Watchdog Control Register
7Fh
R/W
000Dh
to
Reserved (4 bytes)
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
0019h
001Ah
001Bh
001Ch
001Dh
001Eh
001Fh
TCR2
Timer Control Register 2
00h
00h
00h
xxh
xxh
80h
00h
FFh
FCh
FFh
FCh
xxh
xxh
80h
00h
R/W
TCR1
Timer Control Register 1
R/W
TCSR
Timer Control/Status Register
R/W
TIC1HR
TIC1LR
TOC1HR
TOC1LR
TCHR
Timer Input Capture High Register 1
Timer Input Capture Low Register 1
Timer Output Compare High Register 1
Timer Output Compare Low Register 1
Timer Counter High Register
Read only
Read only
R/W
R/W
TIM
Read only
R/W
TCLR
Timer Counter Low Register
TACHR
TACLR
TIC2HR
TIC2LR
TOC2HR
TOC2LR
Timer Alternate Counter High Register
Timer Alternate Counter Low Register
Timer Input Capture High Register 2
Timer Input Capture Low Register 2
Timer Output Compare High Register 2
Timer Output Compare Low Register 2
Read only
R/W
Read only
Read only
R/W
R/W
0020h
0021h
0022h
0023h
0024h
SCISR
SCI Status Register
SCI Data Register
C0h
Read only
R/W
SCIDR
xxh
SCI
SCIBRR
SCICR1
SCICR2
SCI Baud Rate Register
SCI Control Register 1
SCI Control Register 2
00h
R/W
x000 0000b
00h
R/W
R/W
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ST7263BDx ST7263BHx ST7263BKx ST7263BE
Address
Block
Register label
Register name
USB PID Register
Reset status
Remarks
Read only
0025h
0026h
0027h
0028h
0029h
002Ah
002Bh
002Ch
002Dh
002Eh
002Fh
0030h
0031h
USBPIDR
x0h
USBDMAR
USBIDR
USB DMA address Register
USB Interrupt/DMA Register
USB Interrupt Status Register
USB Interrupt Mask Register
USB Control Register
xxh
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
x0h
USBISTR
00h
USBIMR
00h
USBCTLR
USBDADDR
USBEP0RA
USBEP0RB
USBEP1RA
USBEP1RB
USBEP2RA
USBEP2RB
06h
USB
USB Device Address Register
USB Endpoint 0 Register A
USB Endpoint 0 Register B
USB Endpoint 1 Register A
USB Endpoint 1 Register B
USB Endpoint 2 Register A
USB Endpoint 2 Register B
00h
0000 xxxxb
80h
0000 xxxxb
0000 xxxxb
0000 xxxxb
0000 xxxxb
0032hto
0036h
Reserved (5 bytes)
Reserved (5 bytes)
0032h
0036h
0037h
0038h
Flash
FCSR
Flash Control /Status Register
Reserved (1 byte)
00h
R/W
R/W
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
I2CDR
I²C Data Register
00h
-
Reserved
I2COAR
I2CCCR
I2CSR2
I2CSR1
I2CCR
I²C (7 Bits) Slave Address Register
I²C Clock Control Register
I²C 2nd Status Register
I²C 1st Status Register
I²C Control Register
00h
00h
00h
00h
00h
R/W
I²C
R/W
Read only
Read only
R/W
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ST7263BDx ST7263BHx ST7263BKx ST7263BE
4 Flash program memory
4.1 Introduction
The ST7 dual voltage High Density Flash
be erased independently to avoid unnecessary
erasing of the whole Flash memory when only a
partial erasing is required.
(HDFlash) is a non-volatile memory that can be
electrically erased as a single block or by individu-
al sectors and programmed on a byte-by-byte ba-
The first two sectors have a fixed size of 4 Kbytes
(see Figure 8). They are mapped in the upper part
of the ST7 addressing space so the reset and in-
terrupt vectors are located in Sector 0 (F000h-
FFFFh).
sis using an external V supply.
PP
The HDFlash devices can be programmed and
erased off-board (plugged in a programming tool)
or on-board using ICP (in-circuit programming) or
IAP (in-application programming).
Table 6. Sectors available in Flash devices
The array matrix organisation allows each sector
to be erased and reprogrammed without affecting
other sectors.Main features
Flash size (bytes)
Available sectors
4K
8K
Sector 0
Sectors 0,1
Sectors 0,1, 2
■ 3 Flash programming modes:
– Insertion in a programming tool. In this mode,
all sectors including option bytes can be pro-
grammed or erased.
> 8K
– ICP (in-circuit programming). In this mode, all
sectors including option bytes can be pro-
grammed or erased without removing the de-
vice from the application board.
– IAP (in-application programming) In this
mode, all sectors except Sector 0, can be pro-
grammed or erased without removing the de-
vice from the application board and while the
application is running.
4.2.1 Read-Out protection
Read-Out protection, when selected, provides a
protection against Program Memory content ex-
traction and against write access to Flash memo-
ry. Even if no protection can be considered as to-
tally unbreakable, the feature provides a very high
level of protection for a general purpose microcon-
troller.
■ ICT (in-circuit testing) for downloading and
executing user application test patterns in RAM
■ Read-Out protection
■ Register access security system (RASS) to
In Flash devices, this protection is removed by re-
programming the option. In this case, the entire
program memory is first automatically erased and
the device can be reprogrammed.
prevent accidental programming or erasing
Read-Out protection selection depends on the de-
vice type:
4.2 Structure
– In Flash devices it is enabled and removed
through the FMP_R bit in the option byte.
The Flash memory is organised in sectors and can
be used for both code and data storage.
– In ROM devices it is enabled by mask option
specified in the Option List.
Depending on the overall Flash memory size in the
microcontroller device, there are up to three user
sectors (see Table 6). Each of these sectors can
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Figure 8. Memory map and sector address
4K
8K
10K
16K
24K
32K
48K
60K
FLASH
MEMORY SIZE
1000h
3FFFh
7FFFh
9FFFh
BFFFh
D7FFh
DFFFh
EFFFh
FFFFh
SECTOR 2
52 Kbytes
2 Kbytes 8 Kbytes 16 Kbytes 24 Kbytes 40 Kbytes
4 Kbytes
4 Kbytes
SECTOR 1
SECTOR 0
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Flash program memory (Cont’d)
4.3 ICC interface
ICC (in-circuit communication) needs a minimum
of four and up to six pins to be connected to the
programming tool (see Figure 9). These pins are:
– ICCDATA: ICC input/output serial data pin
– ICCSEL/V : programming voltage
PP
– OSC1(or OSCIN): main clock input for exter-
nal source (optional)
– RESET: device reset
– V : application board power supply (see Fig-
– V : device power supply ground
DD
SS
ure 9, Note 3)
– ICCCLK: ICC output serial clock pin
Figure 9. Typical ICC interface
PROGRAMMING TOOL
ICC CONNECTOR
ICC Cable
APPLICATION BOARD
ICC CONNECTOR
(See Note 3)
OPTIONAL
HE10 CONNECTOR TYPE
9
7
5
6
3
1
2
(See Note 4)
10
8
4
APPLICATION
RESET SOURCE
See Note 2
10kΩ
APPLICATION
POWER SUPPLY
C
C
L2
L1
See Note 1
APPLICATION
I/O
ST7
Notes:
1. If the ICCCLK or ICCDATA pins are only used
as outputs in the application, no signal isolation is
necessary. As soon as the Programming Tool is
plugged to the board, even if an ICC session is not
in progress, the ICCCLK and ICCDATA pins are
not available for the application. If they are used as
inputs by the application, isolation such as a serial
resistor has to implemented in case another de-
vice forces the signal. Refer to the Programming
Tool documentation for recommended resistor val-
ues.
agement IC with open drain output and pull-up
resistor > 1K, no additional components are need-
ed. In all cases the user must ensure that no exter-
nal reset is generated by the application during the
ICC session.
3. The use of Pin 7 of the ICC connector depends
on the Programming Tool architecture. This pin
must be connected when using most ST Program-
ming Tools (it is used to monitor the application
power supply). Please refer to the Programming
Tool manual.
2. During the ICC session, the programming tool
must control the RESET pin. This can lead to con-
flicts between the programming tool and the appli-
cation reset circuit if it drives more than 5mA at
high level (push pull output or pull-up resistor<1K).
A schottky diode can be used to isolate the appli-
cation RESET circuit in this case. When using a
classical RC network with R > 1K or a reset man-
4. Pin 9 has to be connected to the OSC1 or OS-
CIN pin of the ST7 when the clock is not available
in the application or if the selected clock option is
not programmed in the option byte. ST7 devices
with multioscillator capability need to have OSC2
grounded in this case.
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ST7263BDx ST7263BHx ST7263BKx ST7263BE
Flash program memory (Cont’d)
4.4 ICP (in-circuit programming)
4.6 Related documentation
To perform ICP the microcontroller must be
switched to ICC (in-circuit communication) mode
by an external controller or programming tool.
For details on Flash programming and ICC proto-
col, refer to the ST7 Flash Programming Refer-
ence Manual and to the ST7 ICC Protocol Refer-
ence Manual.
Depending on the ICP code downloaded in RAM,
Flash memory programming can be fully custom-
ized (number of bytes to program, program loca-
tions, or selection serial communication interface
for downloading).
4.7 Register description
Flash Control/Status register (FCSR)
When using an STMicroelectronics or third-party
programming tool that supports ICP and the spe-
cific microcontroller device, the user needs only to
implement the ICP hardware interface on the ap-
plication board (see Figure 9). For more details on
the pin locations, refer to the device pinout de-
scription.
Read/Write
Reset value: 0000 0000 (00h)
7
0
0
0
0
0
0
0
0
0
4.5 IAP (in-application programming)
This register is reserved for use by programming
tool software. It controls the Flash programming
and erasing operations.
This mode uses a BootLoader program previously
stored in Sector 0 by the user (in ICP mode or by
plugging the device in a programming tool).
This mode is fully controlled by user software. This
allows it to be adapted to the user application, (us-
er-defined strategy for entering programming
mode, choice of communications protocol used to
fetch the data to be stored, etc.). For example, it is
possible to download code from the SPI, SCI or
other type of serial interface and program it in the
Flash. IAP mode can be used to program any of
the Flash sectors except Sector 0, which is write/
erase protected to allow recovery in case errors
occur during the programming operation.
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5 Central processing unit
5.1 Introduction
Accumulator (A)
The Accumulator is an 8-bit general purpose reg-
ister used to hold operands and the results of the
arithmetic and logic calculations and to manipulate
data.
This CPU has a full 8-bit architecture and contains
six internal registers allowing efficient 8-bit data
manipulation.
Index registers (X and Y)
5.2 Features
In indexed addressing modes, these 8-bit registers
are used to create either effective addresses or
temporary storage areas for data manipulation.
(The cross-assembler generates a precede in-
struction (PRE) to indicate that the following in-
struction refers to the Y register.)
■ 63 basic instructions
■ Fast 8-bit by 8-bit multiply
■ 17 main addressing modes
■ Two 8-bit index registers
■ 16-bit stack pointer
■ Low power modes
■ Maskable hardware interrupts
■ Non-maskable software interrupt
The Y register is not affected by the interrupt auto-
matic procedures (not pushed to and popped from
the stack).
Program Counter (PC)
The program counter is a 16-bit register containing
the address of the next instruction to be executed
by the CPU. It is made of two 8-bit registers PCL
(Program Counter Low which is the LSB) and PCH
(Program Counter High which is the MSB).
5.3 CPU registers
The six CPU registers shown in Figure 10 are not
present in the memory mapping and are accessed
by specific instructions.
Figure 10. CPU registers
7
0
ACCUMULATOR
RESET VALUE = XXh
7
0
0
X INDEX REGISTER
Y INDEX REGISTER
RESET VALUE = XXh
7
RESET VALUE = XXh
PCL
PCH
7
8
15
0
PROGRAM COUNTER
RESET VALUE = RESET VECTOR @ FFFEh-FFFFh
7
1
0
H I N Z C
X 1 X X X
1
1
1
1
CONDITION CODE REGISTER
RESET VALUE =
8
1
15
7
0
STACK POINTER
RESET VALUE = STACK HIGHER ADDRESS
X = Undefined value
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ST7263BDx ST7263BHx ST7263BKx ST7263BE
CPU registers (cont’d)
Condition Code register (CC)
Read/Write
because the I bit is set by hardware at the start of
the routine and reset by the IRET instruction at the
end of the routine. If the I bit is cleared by software
in the interrupt routine, pending interrupts are
serviced regardless of the priority level of the cur-
rent interrupt routine.
Reset value: 111x1xxx
7
0
1
1
1
H
I
N
Z
C
Bit 2 = N Negative
The 8-bit Condition Code register contains the in-
terrupt mask and four flags representative of the
result of the instruction just executed. This register
can also be handled by the PUSH and POP in-
structions.
This bit is set and cleared by hardware. It is repre-
sentative of the result sign of the last arithmetic,
logical or data manipulation. It is a copy of the 7
th
bit of the result.
0: The result of the last operation is positive or null.
1: The result of the last operation is negative
(that is, the most significant bit is a logic 1).
These bits can be individually tested and/or con-
trolled by specific instructions.
This bit is accessed by the JRMI and JRPL instruc-
tions.
Bit 4 = H Half carry
This bit is set by hardware when a carry occurs be-
tween bits 3 and 4 of the ALU during an ADD or
ADC instruction. It is reset by hardware during the
same instructions.
0: No half carry has occurred.
1: A half carry has occurred.
Bit 1 = Z Zero
This bit is set and cleared by hardware. This bit in-
dicates that the result of the last arithmetic, logical
or data manipulation is zero.
0: The result of the last operation is different from
zero.
This bit is tested using the JRH or JRNH instruc-
tion. The H bit is useful in BCD arithmetic subrou-
tines.
1: The result of the last operation is zero.
This bit is accessed by the JREQ and JRNE test
instructions.
Bit 3 = I Interrupt mask
This bit is set by hardware when entering in inter-
rupt or by software to disable all interrupts except
the TRAP software interrupt. This bit is cleared by
software.
0: Interrupts are enabled.
1: Interrupts are disabled.
Bit 0 = C Carry/borrow
This bit is set and cleared by hardware and soft-
ware. It indicates an overflow or an underflow has
occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.
This bit is controlled by the RIM, SIM and IRET in-
structions and is tested by the JRM and JRNM in-
structions.
This bit is driven by the SCF and RCF instructions
and tested by the JRC and JRNC instructions. It is
also affected by the “bit test and branch”, shift and
rotate instructions.
Note: Interrupts requested while I is set are
latched and can be processed when I is cleared.
By default an interrupt routine is not interruptible
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6 CPU registers (Cont’d)
Stack Pointer (SP)
Read/Write
The least significant byte of the Stack Pointer
(called S) can be directly accessed by a LD in-
struction.
Reset value: 017Fh
Note: When the lower limit is exceeded, the Stack
Pointer wraps around to the stack upper limit, with-
out indicating the stack overflow. The previously
stored information is then overwritten and there-
fore lost. The stack also wraps in case of an under-
flow.
15
8
1
0
0
7
0
0
0
0
0
0
0
The stack is used to save the return address dur-
ing a subroutine call and the CPU context during
an interrupt. The user may also directly manipulate
the stack by means of the PUSH and POP instruc-
tions. In the case of an interrupt, the PCL is stored
at the first location pointed to by the SP. Then the
other registers are stored in the next locations as
shown in Figure 11.
SP6 SP5 SP4 SP3 SP2 SP1 SP0
The Stack Pointer is a 16-bit register which is al-
ways pointing to the next free location in the stack.
It is then decremented after data has been pushed
onto the stack and incremented before data is
popped from the stack (see Figure 11).
– When an interrupt is received, the SP is decre-
mented and the context is pushed on the stack.
Since the stack is 128 bytes deep, the 9 most sig-
nificant bits are forced by hardware. Following an
MCU Reset, or after a Reset Stack Pointer instruc-
tion (RSP), the Stack Pointer contains its reset val-
ue (the SP6 to SP0 bits are set) which is the stack
higher address.
– On return from interrupt, the SP is incremented
and the context is popped from the stack.
A subroutine call occupies two locations and an in-
terrupt five locations in the stack area.
Figure 11. Stack manipulation example
CALL
Subroutine
RET
or RSP
PUSH Y
POP Y
IRET
Interrupt
Event
@ 0100h
SP
SP
SP
Y
CC
A
CC
A
CC
A
X
X
X
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
SP
SP
PCH
PCL
PCH
PCL
SP
@ 017Fh
Stack Higher Address = 017Fh
0100h
Stack Lower Address =
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ST7263BDx ST7263BHx ST7263BKx ST7263BE
7 Reset and clock management
7.1 Reset
The Reset procedure is used to provide an orderly
software start-up or to exit low power modes.
7.1.3 External reset
The external reset is an active low input signal ap-
plied to the RESET pin of the MCU.
As shown in Figure 15, the RESET signal must
stay low for a minimum of one and a half CPU
clock cycles.
Three reset modes are provided: a low voltage
(LVD) reset, a watchdog reset and an external re-
set at the RESET pin.
A reset causes the reset vector to be fetched from
addresses FFFEh and FFFFh in order to be loaded
into the PC and with program execution starting
from this point.
An internal Schmitt trigger at the RESET pin is pro-
vided to improve noise immunity.
Figure 12. Low voltage detector functional diagram
An internal circuitry provides a 4096 CPU clock cy-
cle delay from the time that the oscillator becomes
active.
RESET
LOW VOLTAGE
V
DD
DETECTOR
7.1.1 Low voltage detector (LVD)
INTERNAL
RESET
Low voltage reset circuitry generates a reset when
V
is:
DD
FROM
WATCHDOG
RESET
■ below V
when V is rising,
DD
IT+
■ below V when V is falling.
IT-
DD
Figure 13. Low voltage reset signal output
Duringlowvoltagereset, theRESETpinisheldlow,
thus permitting the MCU to reset other devices.
V
IT+
It is recommended to make sure that the V sup-
V
DD
IT-
ply voltage rises monotonously when the device is
exiting from Reset, to ensure the application func-
tions properly.
V
DD
RESET
7.1.2 Watchdog reset
When a watchdog reset occurs, the RESET pin is
pulled low permitting the MCU to reset other devic-
es in the same way as the low voltage reset (Fig-
ure 12).
Note: Hysteresis (V -V ) = V
IT+ IT-
hys
Figure 14. Temporization timing diagram after an internal Reset
V
IT+
V
DD
Temporization (4096 CPU clock cycles)
$FFFE
Addresses
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ST7263BDx ST7263BHx ST7263BKx ST7263BE
Reset (Cont’d)
Figure 15. Reset timing diagram
t
DDR
V
DD
OSCIN
t
OXOV
f
CPU
FFFF
FFFE
PC
RESET
4096 CPU
CLOCK
CYCLES
DELAY
WATCHDOG RESET
Note: Refer to Section 14, "Electrical characteristics" for values of t
, tOXOV, V , V and V
IT+ IT- hys
DDR
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ST7263BDx ST7263BHx ST7263BKx ST7263BE
7.2 Clock system
7.2.1 General description
source should be used instead of t
tion 6.5 CONTROL TIMING).
Figure 16. External clock source connections
(see Sec-
OXOV
The MCU accepts either a crystal or ceramic reso-
nator, or an external clock signal to drive the inter-
nal oscillator. The internal clock (f
from the external oscillator frequency (f
) is derived
CPU
),
OSC
which is divided by 3 (and by 2 or 4 for USB, de-
pending on the external clock used). The internal
clock is further divided by 2 by setting the SMS bit
in the Miscellaneous Register.
Using the OSC24/12 bit in the option byte, a 12
MHz or a 24 MHz external clock can be used to
provide an internal frequency of either 2, 4 or 8
MHz while maintaining a 6 MHz for the USB (refer
to Figure 18).
OSCIN
OSCOUT
NC
EXTERNAL
CLOCK
The internal clock signal (f
) is also routed to
CPU
the on-chip peripherals. The CPU clock signal
consists of a square wave with a duty cycle of
50%.
Figure 17. Crystal/ceramic resonator
The internal oscillator is designed to operate with
an AT-cut parallel resonant quartz or ceramic res-
onator in the frequency range specified for f
.
osc
The circuit shown in Figure 17 is recommended
when using a crystal, and Table 7, "Recommend-
ed values for 24 MHz crystal resonator" lists the
recommended capacitance. The crystal and asso-
ciated components should be mounted as close as
possible to the input pins in order to minimize out-
put distortion and start-up stabilisation time.
OSCIN
OSCOUT
RP
C
C
OSCIN
OSCOUT
Table 7. Recommended values for 24 MHz
crystal resonator
Figure 18. Clock block diagram
R
20 Ω
56pF
25 Ω
47pF
70 Ω
22pF
SMAX
C
OSCIN
8, 4 or 2 MHz
CPU and
peripherals)
0
1
C
56pF
47pF
22pF
OSCOUT
RP
1-10 MΩ
1-10 MΩ
1-10 MΩ
%2
%3
Note: R
is the equivalent serial resistor of the
SMAX
crystal (see crystal specification).
SMS
7.2.2 External clock
An external clock may be applied to the OSCIN in-
put with the OSCOUT pin not connected, as
1
0
6 MHz (USB)
%2
24 or
12 MHz
Crystal
shown on Figure 16. The t
specifications do
OXOV
not apply when using an external clock input. The
equivalent specification of the external clock
%2
OSC24/12
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Interrupts and low power mode
8 Interrupts
The ST7 core may be interrupted by one of two dif-
ferent methods: maskable hardware interrupts as
listed in Table 8, "Interrupt mapping" and a non-
maskable software interrupt (TRAP). The Interrupt
processing flowchart is shown in Figure 19.
All interrupts allow the processor to leave the Wait
low power mode. Only external and specific men-
tioned interrupts allow the processor to leave the
Halt low power mode (refer to the “Exit from Halt“
column in Table 8, "Interrupt mapping").
The maskable interrupts must be enabled clearing
the I bit in order to be serviced. However, disabled
interrupts may be latched and processed when
they are enabled (see external interrupts subsec-
tion).
External interrupts
The pins ITi/PAk and ITj/PBk (i=1,2; j= 5,6; k=4,5)
can generate an interrupt when a rising edge oc-
curs on this pin. Conversely, the ITl/PAn and ITm/
PBn pins (l=3,4; m= 7,8; n=6,7) can generate an
interrupt when a falling edge occurs on this pin.
When an interrupt has to be serviced:
– Normal processing is suspended at the end of
the current instruction execution.
– The PC, X, A and CC registers are saved onto
the stack.
Interrupt generation will occur if it is enabled with
the ITiE bit (i=1 to 8) in the ITRFRE register and if
the I bit of the CCR is reset.
– The I bit of the CC register is set to prevent addi-
tional interrupts.
– The PC is then loaded with the interrupt vector of
the interrupt to service and the first instruction of
the interrupt service routine is fetched (refer to
Table 8, "Interrupt mapping" for vector address-
es).
Peripheral interrupts
Different peripheral interrupt flags in the status
register are able to cause an interrupt when they
are active if both:
The interrupt service routine should finish with the
IRET instruction which causes the contents of the
saved registers to be recovered from the stack.
– The I bit of the CC register is cleared.
– The corresponding enable bit is set in the control
register.
Note: As a consequence of the IRET instruction,
the I bit will be cleared and the main program will
resume.
If any of these two conditions is false, the interrupt
is latched and thus remains pending.
Clearing an interrupt request is done by one of the
two following operations:
Priority management
– Writing “0” to the corresponding bit in the status
register.
By default, a servicing interrupt cannot be inter-
rupted because the I bit is set by hardware enter-
ing in interrupt routine.
– Accessing the status register while the flag is set
followed by a read or write of an associated reg-
ister.
In the case several interrupts are simultaneously
pending, a hardware priority defines which one will
be serviced first (see Table 8, "Interrupt map-
ping").
Notes:
1. The clearing sequence resets the internal latch.
A pending interrupt (i.e. waiting to be enabled) will
therefore be lost if the clear sequence is executed.
Non-maskable software interrupts
2. All interrupts allow the processor to leave the
Wait low power mode.
This interrupt is entered when the TRAP instruc-
tion is executed regardless of the state of the I bit.
It will be serviced according to the flowchart on
Figure 19.
3. Exit from Halt mode may only be triggered by an
External Interrupt on one of the ITi ports (PA4-PA7
and PB4-PB7), an end suspend mode Interrupt
coming from USB peripheral, or a reset.
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Interrupts (Cont’d)
Figure 19. Interrupt processing flowchart
FROM RESET
N
BIT I SET
N
Y
INTERRUPT
Y
FETCH NEXT INSTRUCTION
N
IRET
STACK PC, X, A, CC
SET I BIT
Y
LOAD PC FROM INTERRUPT VECTOR
EXECUTE INSTRUCTION
RESTORE PC, X, A, CC FROM STACK
THIS CLEARS I BIT BY DEFAULT
Table 8. Interrupt mapping
Exit
from
Halt
Vector
Source
block
Register Priority
N°
Description
label
order
address
RESET
TRAP
FLASH
USB
Reset
yes
no
FFFEh-FFFFh
FFFCh-FFFDh
FFFAh-FFFBh
FFF8h-FFF9h
FFF6h-FFF7h
FFF4h-FFF5h
Highest
Priority
N/A
Software Interrupt
Flash Start Programming Interrupt
End Suspend mode
External Interrupts
yes
ISTR
ITRFRE
TIMSR
I²CSR1
I²CSR2
SCISR
ISTR
yes
1
2
ITi
TIMER
Timer Peripheral Interrupts
3
I²C
I²C Peripheral Interrupts
FFF2h-FFF3h
no
Lowest
Priority
4
5
SCI
SCI Peripheral Interrupts
USB Peripheral Interrupts
FFF0h-FFF1h
FFEEh-FFEFh
USB
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Interrupts (Cont’d)
8.1 Interrupt register
Interrupt register (ITRFRE)
Address: 0008h
Reset value: 0000 0000 (00h)
—
Read/Write
If an ITiE bit is set, the corresponding interrupt is
generated when
– a rising edge occurs on the pin PA4/IT1 or PA5/
IT2 or PB4/IT5 or PB5/IT6
7
0
IT8E
IT7E
IT6E
IT5E
IT4E
IT3E
IT2E
IT1E
or
– a falling edge occurs on the pin PA6/IT3 or PA7/
IT4 or PB6/IT7 or PB7/IT8
Bit 7:0 = ITiE (i=1 to 8). Interrupt Enable Control
Bits.
No interrupt is generated elsewhere.
Note: Analog input must be disabled for interrupts
coming from port B.
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9 Power saving modes
9.1 Introduction
To give a large measure of flexibility to the applica-
tion in terms of power consumption, two main pow-
er saving modes are implemented in the ST7.
Figure 20. Halt mode flowchart
HALT INSTRUCTION
After a RESET, the normal operating mode is se-
lected by default (Run mode). This mode drives
the device (CPU and embedded peripherals) by
means of a master clock which is based on the
OSCILLATOR
OFF
main oscillator frequency divided by 3 (f
).
CPU
PERIPH. CLOCK
CPU CLOCK
I-BIT
OFF
From Run mode, the different power saving
modes may be selected by setting the relevant
register bits or by calling the specific ST7 software
instruction whose action depends on the oscillator
status.
OFF
CLEARED
9.2 Halt mode
N
RESET
The MCU consumes the least amount of power in
Halt mode. The Halt mode is entered by executing
the HALT instruction. The internal oscillator is then
turned off, causing all internal processing to be
stopped, including the operation of the on-chip pe-
ripherals.
N
EXTERNAL
Y
INTERRUPT*
Y
When entering Halt mode, the I bit in the Condition
Code Register is cleared. Thus, all external inter-
rupts (ITi or USB end suspend mode) are allowed
and if an interrupt occurs, the CPU clock becomes
active.
OSCILLATOR
ON
ON
ON
SET
PERIPH. CLOCK
CPU CLOCK
I-BIT
The MCU can exit Halt mode on reception of either
an external interrupt on ITi, an end suspend mode
interrupt coming from USB peripheral, or a reset.
The oscillator is then turned on and a stabilization
time is provided before releasing CPU operation.
The stabilization time is 4096 CPU clock cycles.
After the start up delay, the CPU continues opera-
tion by servicing the interrupt which wakes it up or
by fetching the reset vector if a reset wakes it up.
4096 CPU CLOCK
CYCLES DELAY
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Note: Before servicing an interrupt, the CC register is
pushed on the stack. The I-Bit is set during the inter-
rupt routine and cleared when the CC register is
popped.
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Power saving modes (Cont’d)
9.3 Slow mode
In Slow mode, the oscillator frequency can be di-
vided by 2 as selected by the SMS bit in the Mis-
cellaneous Register. The CPU and peripherals are
clocked at this lower frequency. Slow mode is
used to reduce power consumption, and enables
the user to adapt the clock frequency to the avail-
able supply voltage.
Figure 21. Wait mode flowchart
WFI INSTRUCTION
OSCILLATOR
PERIPH. CLOCK
CPU CLOCK
I-BIT
ON
9.4 Wait mode
ON
OFF
Wait mode places the MCU in a low power con-
sumption mode by stopping the CPU.
This power saving mode is selected by calling the
“WFI” ST7 software instruction.
CLEARED
All peripherals remain active. During Wait mode,
the I bit of the CC register is forced to 0 to enable
all interrupts. All other registers and memory re-
main unchanged. The MCU remains in Wait mode
until an interrupt or Reset occurs, whereupon the
Program Counter branches to the starting address
of the interrupt or Reset service routine.
N
RESET
N
The MCU will remain in Wait mode until a Reset or
an Interrupt occurs, causing it to wake up.
Y
INTERRUPT
Y
Refer to Figure 21.
Related documentation
OSCILLATOR
ON
ON
ON
SET
AN 980: ST7 Keypad Decoding Techniques, Im-
plementing Wake-Up on Keystroke
PERIPH. CLOCK
CPU CLOCK
I-BIT
AN1014: How to Minimize the ST7 Power Con-
sumption
AN1605: Using an active RC to wakeup the
ST7LITE0 from power saving mode
IF RESET
4096 CPU CLOCK
CYCLES DELAY
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Note: Before servicing an interrupt, the CC register is
pushed on the stack. The I-Bit is set during the inter-
rupt routine and cleared when the CC register is
popped.
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10 I/O ports
10.1 Introduction
The I/O ports offer different functional modes:
tivity is given independently according to the de-
scription mentioned in the ITRFRE interrupt regis-
ter.
– Transfer of data through digital inputs and out-
puts and for specific pins
Each pin can independently generate an Interrupt
request.
– Analog signal input (ADC)
– Alternate signal input/output for the on-chip pe-
ripherals
Each external interrupt vector is linked to a dedi-
cated group of I/O port pins (see Interrupts sec-
tion). If more than one input pin is selected simul-
taneously as an interrupt source, this is logically
ORed. For this reason if one of the interrupt pins is
tied low, the other ones are masked.
– External interrupt generation
An I/O port consists of up to 8 pins. Each pin can
be programmed independently as a digital input
(with or without interrupt generation) or a digital
output.
Output mode
The pin is configured in output mode by setting the
corresponding DDR register bit (see Table 7).
10.2 Functional description
In this mode, writing “0” or “1” to the DR register
applies this digital value to the I/O pin through the
latch. Therefore, the previously saved value is re-
stored when the DR register is read.
Each port is associated to 2 main registers:
– Data Register (DR)
– Data Direction Register (DDR)
Each I/O pin may be programmed using the corre-
sponding register bits in DDR register: bit X corre-
sponding to pin X of the port. The same corre-
spondence is used for the DR register.
Note: The interrupt function is disabled in this
mode.
Digital alternate function
Table 9. I/O pin functions
When an on-chip peripheral is configured to use a
pin, the alternate function is automatically select-
ed. This alternate function takes priority over
standard I/O programming. When the signal is
coming from an on-chip peripheral, the I/O pin is
automatically configured in output mode (push-pull
or open drain according to the peripheral).
DDR
MODE
Input
0
1
Output
Input modes
When the signal is going to an on-chip peripheral,
the I/O pin has to be configured in input mode. In
this case, the pin’s state is also digitally readable
by addressing the DR register.
The input configuration is selected by clearing the
corresponding DDR register bit.
In this case, reading the DR register returns the
digital value applied to the external I/O pin.
Notes:
1. Input pull-up configuration can cause an unex-
pected value at the input of the alternate peripher-
al input.
2. When the on-chip peripheral uses a pin as input
and output, this pin must be configured as an input
(DDR = 0).
Note 1: All the inputs are triggered by a Schmitt
trigger.
Note 2: When switching from input mode to output
mode, the DR register should be written first to
output the correct value as soon as the port is con-
figured as an output.
Warning: The alternate function must not be acti-
vated as long as the pin is configured as an input
with interrupt in order to avoid generating spurious
interrupts.
Interrupt function
When an I/O is configured as an Input with Inter-
rupt, an event on this I/O can generate an external
Interrupt request to the CPU. The interrupt sensi-
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I/O ports (Cont’d)
Analog alternate function
have clocking pins located close to a selected an-
alog pin.
When the pin is used as an ADC input the I/O must
be configured as a floating input. The analog mul-
tiplexer (controlled by the ADC registers) switches
the analog voltage present on the selected pin to
the common analog rail which is connected to the
ADC input.
Warning: The analog input voltage level must be
within the limits stated in the Absolute Maximum
Ratings.
10.3 I/O port implementation
It is recommended not to change the voltage level
or loading on any port pin while conversion is in
progress. Furthermore it is recommended not to
The hardware implementation on each I/O port de-
pends on the settings in the DDR register and spe-
cific feature of the I/O port such as ADC Input or
true open drain.
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I/O ports (Cont’d)
10.3.1 Port A
Table 10. Port A0, A3, A4, A5, A6, A7 description
I / O
Alternate function
PORT A
1
Input
Output
push-pull
Signal
Condition
PA0
PA3
with pull-up
MCO (Main Clock Output)
MCO = 1 (MISCR)
CC1 =1
with pull-up
with pull-up
with pull-up
with pull-up
with pull-up
push-pull
Timer EXTCLK
CC0 = 1 (Timer CR2)
Timer ICAP1
PA4
PA5
PA6
push-pull
push-pull
push-pull
push-pull
IT1 Schmitt triggered input IT1E = 1 (ITIFRE)
Timer ICAP2
IT2 Schmitt triggered input IT2E = 1 (ITIFRE)
Timer OCMP1
IT3 Schmitt triggered input IT3E = 1 (ITIFRE)
Timer OCMP2 OC2E = 1
IT4 Schmitt triggered input IT4E = 1 (ITIFRE)
OC1E = 1
2
PA7
1
Reset State
2
Not available on SO24
Figure 22. PA0, PA3, PA4, PA5, PA6, PA7 and PD[7:4] configuration
ALTERNATE ENABLE
1
0
VDD
ALTERNATE
OUTPUT
P-BUFFER
V
DD
DR
PULL-UP
LATCH
ALTERNATE ENABLE
DDR
LATCH
PAD
DDR SEL
N-BUFFER
DIODES
1
0
DR SEL
ALTERNATE ENABLE
VSS
ALTERNATE INPUT
CMOS SCHMITT TRIGGER
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I/O ports (Cont’d)
Table 11. PA1, PA2 description
I / O
Alternate function
PORT A
1
Input
Output
Signal
SDA (I²C data)
SCL (I²C clock)
Condition
I²C enable
I²C enable
PA1
PA2
without pull-up
without pull-up
Very High Current open drain
Very High Current open drain
1
Reset State
Figure 23. PA1, PA2 configuration
ALTERNATE ENABLE
1
ALTERNATE
OUTPUT
0
DR
LATCH
DDR
LATCH
PAD
DDR SEL
N-BUFFER
DR SEL
1
0
ALTERNATE ENABLE
VSS
CMOS SCHMITT TRIGGER
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I/O ports (Cont’d)
10.3.2 Port B
Table 12. Port B description
PORT B
I/O
Alternate function
1
Input
Output
push-pull
Signal
Condition
PB0
without pull-up
without pull-up
Analog input (ADC)
CH[3:0] = 000 (ADCCSR)
CH[3:0] = 001 (ADCCSR)
Analog input (ADC)
PB1
push-pull
USBOE =1
(MISCR)
USBOE (USB output ena-
2
ble)
PB2
PB3
without pull-up
without pull-up
push-pull
push-pull
Analog input (ADC)
Analog input (ADC)
Analog input (ADC)
CH[3:0]= 010 (ADCCSR)
CH[3:0]= 011 (ADCCSR)
CH[3:0]= 100 (ADCCSR)
PB4
PB5
PB6
PB7
without pull-up
without pull-up
without pull-up
without pull-up
push-pull
push-pull
push-pull
push-pull
IT5 Schmitt triggered input IT4E = 1 (ITIFRE)
Analog input (ADC)
CH[3:0]= 101 (ADCCSR)
IT6 Schmitt triggered input IT5E = 1 (ITIFRE)
Analog input (ADC)
CH[3:0]= 110 (ADCCSR)
IT7 Schmitt triggered input IT6E = 1 (ITIFRE)
Analog input (ADC)
CH[3:0]= 111 (ADCCSR)
IT8 Schmitt triggered input IT7E = 1 (ITIFRE)
1
Reset State
2
On SO24 only
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Figure 24. Port B and D[3:0] configuration
ALTERNATE ENABLE
VDD
ALTERNATE
OUTPUT
1
0
V
DD
P-BUFFER
DR
LATCH
ALTERNATE ENABLE
DDR
PAD
LATCH
ANALOG ENABLE
(ADC)
DDR SEL
ANALOG
SWITCH
DIODES
N-BUFFER
1
DR SEL
ALTERNATE ENABLE
DIGITAL ENABLE
VSS
0
ALTERNATE INPUT
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I/O ports (Cont’d)
10.3.3 Port C
Table 13. Port C description
I / O
Alternate function
PORT C
1
Input
with pull-up
with pull-up
Output
push-pull
Signal
Condition
PC0
PC1
RDI (SCI input)
push-pull
push-pull
TDO (SCI output)
SCI enable
USBOE =1
(MISCR)
USBOE (USB output ena-
ble)
2
PC2
with pull-up
1
Reset State
2
Not available on SO24
Figure 25. Port C configuration
ALTERNATE ENABLE
1
0
VDD
ALTERNATE
OUTPUT
P-BUFFER
V
DD
DR
PULL-UP
LATCH
ALTERNATE ENABLE
DDR
PAD
LATCH
DDR SEL
N-BUFFER
DIODES
1
0
DR SEL
ALTERNATE ENABLE
VSS
ALTERNATE INPUT
CMOS SCHMITT TRIGGER
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10.3.4 Port D
Table 14. Port D description
I / O
Alternate function
PORT D
Input*
Output
Signal
Condition
CH[3:0] = 1000 (ADCC-
SR)
PD0
PD1
PD2
PD3
without pull-up push-pull
without pull-up push-pull
without pull-up push-pull
without pull-up push-pull
Analog input (ADC)
CH[3:0] = 1001 (ADCC-
SR)
Analog input (ADC)
Analog input (ADC)
Analog input (ADC)
CH[3:0] = 1010 (ADCC-
SR)
CH[3:0] = 1011 (ADCC-
SR)
PD4
with pull-up
with pull-up
with pull-up
with pull-up
push-pull
push-pull
push-pull
push-pull
PD5
PD6
PD7
*Reset State
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I/O ports (Cont’d)
10.3.5 Register description
Data Direction Register (PxDDR)
Data registers (PxDR)
Port A Data Direction Register (PADDR): 0001h
Port B Data Direction Register (PBDDR): 0003h
Port C Data Direction Register (PCDDR): 0005h
Port D Data Direction Register (PDDDR): 0007h
Read/Write
Port A Data Register (PADR): 0000h
Port B Data Register (PBDR): 0002h
Port C Data Register (PCDR): 0004h
Port D Data Register (PDDR): 0006h
Read/Write
Reset value Port A: 0000 0000 (00h)
Reset value Port B: 0000 0000 (00h)
Reset value Port C: 1111 x000 (FXh)
Reset value Port D: 0000 0000 (00h)
Reset value Port A: 0000 0000 (00h)
Reset value Port B: 0000 0000 (00h)
Reset value Port C: 1111 x000 (FXh)
Reset value Port D: 0000 0000 (00h)
Note: For Port C, unused bits (7-3) are not acces-
sible
Note: For Port C, unused bits (7-3) are not acces-
sible.
7
0
7
0
DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0
D7
D6
D5
D4
D3
D2
D1
D0
Bit 7:0 = DD[7:0] Data Direction Register 8 bits.
Bit 7:0 = D[7:0] Data Register 8 bits.
The DDR register gives the input/output direction
configuration of the pins. Each bit is set and
cleared by software.
0: Input mode
1: Output mode
The DR register has a specific behaviour accord-
ing to the selected input/output configuration. Writ-
ing the DR register is always taken into account
even if the pin is configured as an input. Reading
the DR register returns either the DR register latch
content (pin configured as output) or the digital val-
ue applied to the I/O pin (pin configured as input).
Note: When using open-drain I/Os in output con-
figuration, the value read in DR is the digital value
applied to the I/Opin.
Table 15. I/O ports register map
Address
Register
label
7
6
5
4
3
2
1
0
(Hex.)
00
PADR
PADDR
PBDR
MSB
MSB
MSB
MSB
MSB
MSB
MSB
MSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
01
02
03
PBDDR
PCDR
04
05
PCDDR
PDDR
06
07
PDDDR
Related documentation
AN 970: SPI communication between ST7 and EEPROM
AN1045: S/W implementation of I2C bus master
AN1048: Software LCD driver
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11 Miscellaneous register
Address: 0009h
Reset value: 0000 0000 (00h)
—
Read/Write
1: Divide-by-2 enabled and CPU clock frequency is
halved.
Bit 1 = USBOE USB enable.
7
0
If this bit is set, the port PC2 (PB1 on SO24) out-
puts the USB output enable signal (at “1” when the
ST7 USB is transmitting data).
-
-
-
-
-
SMS USBOE MCO
Bit 7:3 = Reserved
Bit 2 = SMS Slow Mode Select.
Unused bits 7-4 are set.
Bit 0 = MCO Main Clock Out selection
This bit enables the MCO alternate function on the
PA0 I/O port. It is set and cleared by software.
0: MCO alternate function disabled (I/O pin free for
general-purpose I/O)
1: MCO alternate function enabled (f
port)
This bit is set by software and only cleared by hard-
ware after a reset. If this bit is set, it enables the use
of an internal divide-by-2 clock divider (refer to Fig-
ure 18 on page 26). The SMS bit has no effect on
the USB frequency.
on I/O
CPU
0: Divide-by-2 disabled and CPU clock frequency
is standard
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12 On-chip peripherals
12.1 Watchdog timer (WDG)
12.1.1 Introduction
cles, and the length of the timeout period can be
programmed by the user in 64 increments.
The Watchdog timer is used to detect the occur-
rence of a software fault, usually generated by ex-
ternal interference or by unforeseen logical condi-
tions, which causes the application program to
abandon its normal sequence. The Watchdog cir-
cuit generates an MCU reset on expiry of a pro-
grammed time period, unless the program refresh-
es the counter’s contents before the T6 bit be-
comes cleared.
If the watchdog is activated (the WDGA bit is set)
and when the 7-bit timer (bits T6:T0) rolls over
from 40h to 3Fh (T6 becomes cleared), it initiates
a reset cycle pulling low the reset pin for typically
30µs.
The application program must write in the CR reg-
ister at regular intervals during normal operation to
prevent an MCU reset. This downcounter is free-
running: it counts down even if the watchdog is
disabled. The value to be stored in the CR register
must be between FFh and C0h (see Table 16, ".
Watchdog timing (fCPU = 8 MHz)"):
12.1.2 Main features
■ Programmable free-running counter (64
increments of 49,152 CPU cycles)
■ Programmable reset
– The WDGA bit is set (watchdog enabled)
■ Reset (if watchdog activated) when the T6 bit
– The T6 bit is set to prevent generating an imme-
diate reset
reaches zero
■ Optional
reset
on
HALT
instruction
(configurable by option byte)
■ Hardware Watchdog selectable by option byte.
– The T5:T0 bits contain the number of increments
which represents the time delay before the
watchdog produces a reset.
12.1.3 Functional description
The counter value stored in the CR register (bits
T6:T0), is decremented every 49,152 machine cy-
Figure 26. Watchdog block diagram
RESET
WATCHDOG CONTROL REGISTER (CR)
T5
T0
WDGA T6
T1
T4
T2
T3
7-BIT DOWNCOUNTER
CLOCK DIVIDER
f
CPU
÷49152
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Watchdog timer (Cont’d)
Table 16. Watchdog timing (f
= 8 MHz)
In this case, the HALT instruction stops the oscilla-
tor. When the oscillator is stopped, the WDG stops
counting and is no longer able to generate a reset
until the microcontroller receives an external inter-
rupt or a reset.
CPU
CR register
initial value
WDG timeout period
(ms)
Max
Min
FFh
C0h
393.216
6.144
If an external interrupt is received, the WDG re-
starts counting after 4096 CPU clocks. If a reset is
generated, the WDG is disabled (reset state).
Notes: Following a reset, the watchdog is disa-
bled. Once activated it cannot be disabled, except
by a reset.
Recommendations
– Make sure that an external event is available to
wake up the microcontroller from Halt mode.
The T6 bit can be used to generate a software re-
set (the WDGA bit is set and the T6 bit is cleared).
– Before executing the HALT instruction, refresh
the WDG counter, to avoid an unexpected WDG
reset immediately after waking up the microcon-
troller.
12.1.4 Software Watchdog option
If Software Watchdog is selected by option byte,
the watchdog is disabled following a reset. Once
activated it cannot be disabled, except by a reset.
– When using an external interrupt to wake up the
microcontroller, reinitialize the corresponding I/O
as “Input Pull-up with Interrupt” before executing
the HALT instruction. The main reason for this is
that the I/O may be wrongly configured due to ex-
ternal interference or by an unforeseen logical
condition.
The T6 bit can be used to generate a software re-
set (the WDGA bit is set and the T6 bit is cleared).
12.1.5 Hardware Watchdog option
If Hardware Watchdog is selected by option byte,
the watchdog is always active and the WDGA bit in
the CR is not used.
– For the same reason, reinitialize the level sensi-
tiveness of each external interrupt as a precau-
tionary measure.
– The opcode for the HALT instruction is 0x8E. To
avoid an unexpected HALT instruction due to a
program counter failure, it is advised to clear all
occurrences of the data value 0x8E from memo-
ry. For example, avoid defining a constant in
ROM with the value 0x8E.
12.1.6 Low power modes
WAIT instruction
No effect on Watchdog.
HALT instruction
– As the HALT instruction clears the I bit in the CC
register to allow interrupts, the user may choose
to clear all pending interrupt bits before execut-
ing the HALT instruction. This avoids entering
other peripheral interrupt routines after executing
the external interrupt routine corresponding to
the wake-up event (reset or external interrupt).
If the Watchdog reset on Halt option is selected by
option byte, a HALT instruction causes an immedi-
ate reset generation if the Watchdog is activated
(WDGA bit is set).
12.1.6.1 Using Halt mode with the WDG
(option)
If the Watchdog reset on Halt option is not select-
ed by option byte, the Halt mode can be used
when the watchdog is enabled.
12.1.7 Interrupts
None.
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Watchdog timer (Cont’d)
12.1.8 Register description
Control Register (CR)
Read/Write
hardware after a reset. When WDGA = 1, the
watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled
Reset value: 0111 1111 (7Fh)
Bit 6:0 = T[6:0] 7-bit timer (MSB to LSB).
These bits contain the decremented value. A reset
is produced when it rolls over from 40h to 3Fh (T6
becomes cleared).
7
0
WDGA T6
T5
T4
T3
T2
T1
T0
Bit 7 = WDGA Activation bit.
This bit is set by software and only cleared by
Table 17. Watchdog timer register map and reset values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
WDGCR
WDGA
0
T6
1
T5
1
T4
1
T3
1
T2
1
T1
1
T0
1
0Ch
Reset value
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ST7263BDx ST7263BHx ST7263BKx ST7263BE
12.2 16-bit timer
12.2.1 Introduction
When reading an input signal on a non-bonded
pin, the value will always be ‘1’.
The timer consists of a 16-bit free-running counter
driven by a programmable prescaler.
12.2.3 Functional description
12.2.3.1 Counter
It may be used for a variety of purposes, including
pulse length measurement of up to two input sig-
nals (input capture) or generation of up to two out-
put waveforms (output compare and PWM).
The main block of the Programmable Timer is a
16-bit free running upcounter and its associated
16-bit registers. The 16-bit registers are made up
of two 8-bit registers called high and low.
Pulse lengths and waveform periods can be mod-
ulated from a few microseconds to several milli-
seconds using the timer prescaler and the CPU
clock prescaler.
Counter Register (CR):
– Counter High Register (CHR) is the most sig-
nificant byte (MS byte).
Some ST7 devices have two on-chip 16-bit timers.
They are completely independent, and do not
share any resources. They are synchronized after
a MCU reset as long as the timer clock frequen-
cies are not modified.
– Counter Low Register (CLR) is the least sig-
nificant byte (LS byte).
Alternate Counter Register (ACR)
– Alternate Counter High Register (ACHR) is the
most significant byte (MS byte).
This description covers one or two 16-bit timers. In
ST7 devices with two timers, register names are
prefixed with TA (Timer A) or TB (Timer B).
– Alternate Counter Low Register (ACLR) is the
least significant byte (LS byte).
12.2.2 Main features
■ Programmable prescaler: fCPU divided by 2, 4 or 8
■ Overflow status flag and maskable interrupt
■ External clock input (must be at least four times
slowerthantheCPUclockspeed)withthechoice
of active edge
■ 1 or 2 Output Compare functions each with:
– 2 dedicated 16-bit registers
These two read-only 16-bit registers contain the
same value but with the difference that reading the
ACLR register does not clear the TOF bit (Timer
overflow flag), located in the Status register, (SR),
(see note at the end of paragraph titled 16-bit read
sequence).
Writing in the CLR register or ACLR register resets
the free running counter to the FFFCh value.
Both counters have a reset value of FFFCh (this is
the only value which is reloaded in the 16-bit tim-
er). The reset value of both counters is also
FFFCh in One Pulse mode and PWM mode.
– 2 dedicated programmable signals
– 2 dedicated status flags
– 1 dedicated maskable interrupt
■ 1 or 2 Input Capture functions each with:
– 2 dedicated 16-bit registers
The timer clock depends on the clock control bits
of the CR2 register, as illustrated in Table 18,
"Clock Control Bits". The value in the counter reg-
ister repeats every 131072, 262144 or 524288
CPU clock cycles depending on the CC[1:0] bits.
– 2 dedicated active edge selection signals
– 2 dedicated status flags
– 1 dedicated maskable interrupt
■ Pulse width modulation mode (PWM)
■ One Pulse mode
The timer frequency can be f
or an external frequency.
/2, f
/4, f
/8
CPU
CPU
CPU
■ Reduced Power mode
■ 5 alternate functions on I/O ports (ICAP1, ICAP2,
OCMP1, OCMP2, EXTCLK)*
The block diagram is shown in Figure 27.
*Note: Some timer pins may not be available (not
bonded) in some ST7 devices. Refer to the device
pin out description.
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ST7263BDx ST7263BHx ST7263BKx ST7263BE
16-bit timer (Cont’d)
Figure 27. Timer block diagram
ST7 INTERNAL BUS
f
CPU
MCU-PERIPHERAL INTERFACE
8 low
8-bit
8 high
8
8
8
8
8
8
8
8
buffer
EXEDG
16
INPUT
CAPTURE
REGISTER
INPUT
CAPTURE
REGISTER
OUTPUT
COMPARE
REGISTER
OUTPUT
COMPARE
REGISTER
1/2
1/4
1/8
COUNTER
REGISTER
1
1
2
2
ALTERNATE
COUNTER
REGISTER
EXTCLK
pin
16
16
16
CC[1:0]
TIMER INTERNAL BUS
16 16
OVERFLOW
DETECT
EDGE DETECT
CIRCUIT1
OUTPUT COMPARE
CIRCUIT
ICAP1
pin
CIRCUIT
6
EDGE DETECT
CIRCUIT2
ICAP2
pin
OCMP1
pin
LATCH1
LATCH2
0
ICF1 OCF1 TOF ICF2 OCF2
0
TIMD
(Control/Status Register)
OCMP2
pin
CSR
EXEDG
ICIE OCIE TOIE FOLV2 FOLV1OLVL2 IEDG1 OLVL1
OC1E
OPM PWM CC1 CC0 IEDG2
OC2E
(Control Register 1) CR1
(Control Register 2) CR2
(See note)
Note: If IC, OC and TO interrupt requests have separate vectors
then the last OR is not present (See device Interrupt Vector Table)
TIMER INTERRUPT
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ST7263BDx ST7263BHx ST7263BKx ST7263BE
16-bit timer (Cont’d)
16-bit read sequence: (from either the Counter
Register or the Alternate Counter Register).
Clearing the overflow interrupt request is done in
two steps:
1. Reading the SR register while the TOF bit is set.
2. An access (read or write) to the CLR register.
Beginning of the sequence
Read
LS byte
Notes: The TOF bit is not cleared by accesses to
ACLR register. The advantage of accessing the
ACLR register rather than the CLR register is that
it allows simultaneous use of the overflow function
and reading the free running counter at random
times (for example, to measure elapsed time) with-
out the risk of clearing the TOF bit erroneously.
MS byte
At t0
is buffered
Other
instructions
Returns the buffered
LS byte value at t0
Read
LS byte
At t0 +∆t
The timer is not affected by Wait mode.
In Halt mode, the counter stops counting until the
mode is exited. Counting then resumes from the
previous count (MCU awakened by an interrupt) or
from the reset count (MCU awakened by a Reset).
Sequence completed
The user must read the MS byte first, then the LS
byte value is buffered automatically.
This buffered value remains unchanged until the
16-bit read sequence is completed, even if the
user reads the MS byte several times.
12.2.3.2 External clock
The external clock (where available) is selected if
CC0 = 1 and CC1 = 1 in the CR2 register.
After a complete reading sequence, if only the
CLR register or ACLR register are read, they re-
turn the LS byte of the count value at the time of
the read.
The status of the EXEDG bit in the CR2 register
determines the type of level transition on the exter-
nal clock pin EXTCLK that will trigger the free run-
ning counter.
Whatever the timer mode used (input capture, out-
put compare, One Pulse mode or PWM mode) an
overflow occurs when the counter rolls over from
FFFFh to 0000h then:
The counter is synchronized with the falling edge
of the internal CPU clock.
A minimum of four falling edges of the CPU clock
must occur between two consecutive active edges
of the external clock; thus the external clock fre-
quency must be less than a quarter of the CPU
clock frequency.
– The TOF bit of the SR register is set.
– A timer interrupt is generated if:
– TOIE bit of the CR1 register is set and
– I bit of the CC register is cleared.
If one of these conditions is false, the interrupt re-
mains pending to be issued as soon as they are
both true.
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ST7263BDx ST7263BHx ST7263BKx ST7263BE
16-bit timer (Cont’d)
Figure 28. Counter timing diagram, internal clock divided by 2
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
FFFD FFFE FFFF 0000 0001 0002 0003
COUNTER REGISTER
TIMER OVERFLOW FLAG (TOF)
Figure 29. Counter timing diagram, internal clock divided by 4
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
FFFC
FFFD
0000
0001
COUNTER REGISTER
TIMER OVERFLOW FLAG (TOF)
Figure 30. Counter timing diagram, internal clock divided by 8
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
0000
FFFC
FFFD
COUNTER REGISTER
TIMER OVERFLOW FLAG (TOF)
Note: The MCU is in reset state when the internal reset signal is high, when it is low the MCU is running.
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ST7263BDx ST7263BHx ST7263BKx ST7263BE
16-bit timer (Cont’d)
12.2.3.3 Input Capture
When an input capture occurs:
In this section, the index, i, may be 1 or 2 because
there are two input capture functions in the 16-bit
timer.
– ICFi bit is set.
– The ICiR register contains the value of the free
running counter on the active transition on the
ICAPi pin (see Figure 32).
The two 16-bit input capture registers (IC1R and
IC2R) are used to latch the value of the free run-
ning counter after a transition is detected on the
ICAPi pin (see Figure 31).
– A timer interrupt is generated if the ICIE bit is set
and the I bit is cleared in the CC register. Other-
wise, the interrupt remains pending until both
conditions become true.
MS byte
LS byte
ICiR
ICiHR
ICiLR
Clearing the Input Capture interrupt request (that
is, clearing the ICFi bit) is done in two steps:
ICiR register is a read-only register.
1. Reading the SR register while the ICFi bit is set.
2. An access (read or write) to the ICiLR register.
The active transition is software programmable
through the IEDGi bit of Control Registers (CRi).
Timing resolution is one count of the free running
Notes:
counter: (f
/CC[1:0]).
CPU
1. After reading the ICiHR register, transfer of
input capture data is inhibited and ICFi will
never be set until the ICiLR register is also
read.
Procedure:
To use the input capture function select the follow-
ing in the CR2 register:
2. The ICiR register contains the free running
counter value which corresponds to the most
recent input capture.
– Select the timer clock (CC[1:0]) (see Table 18,
"Clock Control Bits").
3. The two input capture functions can be used
together even if the timer also uses the two out-
put compare functions.
– Select the edge of the active transition on the
ICAP2 pin with the IEDG2 bit (the ICAP2 pin
must be configured as floating input or input with
pull-up without interrupt if this configuration is
available).
4. In One Pulse mode and PWM mode only Input
Capture 2 can be used.
And select the following in the CR1 register:
5. The alternate inputs (ICAP1 and ICAP2) are
always directly connected to the timer. So any
transitions on these pins activates the input
capture function.
– Set the ICIE bit to generate an interrupt after an
input capture coming from either the ICAP1 pin
or the ICAP2 pin
Moreover if one of the ICAPi pins is configured
as an input and the second one as an output,
an interrupt can be generated if the user tog-
gles the output pin and if the ICIE bit is set.
This can be avoided if the input capture func-
tion i is disabled by reading the ICiHR (see note
1).
– Select the edge of the active transition on the
ICAP1 pin with the IEDG1 bit (the ICAP1pin must
be configured as floating input or input with pull-
up without interrupt if this configuration is availa-
ble).
6. The TOF bit can be used with interrupt genera-
tion in order to measure events that go beyond
the timer range (FFFFh).
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ST7263BDx ST7263BHx ST7263BKx ST7263BE
16-bit timer (Cont’d)
Figure 31. Input Capture block diagram
ICAP1
pin
(Control Register 1) CR1
EDGE DETECT
CIRCUIT2
EDGE DETECT
CIRCUIT1
ICIE
IEDG1
ICAP2
pin
(Status Register) SR
ICF1
ICF2
0
0
0
IC2R Register
IC1R Register
(Control Register 2) CR2
16-BIT
16-BIT FREE RUNNING
COUNTER
IEDG2
CC0
CC1
Figure 32. Input Capture timing diagram
TIMER CLOCK
FF01
FF02
FF03
COUNTER REGISTER
ICAPi PIN
ICAPi FLAG
FF03
ICAPi REGISTER
Note: The rising edge is the active edge.
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ST7263BDx ST7263BHx ST7263BKx ST7263BE
16-bit timer (Cont’d)
12.2.3.4 Output Compare
– The OCMPi pin takes OLVLi bit value (OCMPi
pin latch is forced low during reset).
In this section, the index, i, may be 1 or 2 because
there are two output compare functions in the 16-
bit timer.
– A timer interrupt is generated if the OCIE bit is
set in the CR1 register and the I bit is cleared in
the CC register (CC).
This function can be used to control an output
waveform or indicate when a period of time has
elapsed.
The OCiR register value required for a specific tim-
ing application can be calculated using the follow-
ing formula:
When a match is found between the Output Com-
pare register and the free running counter, the out-
put compare function:
– Assigns pins with a programmable value if the
∆t f
* CPU
∆ OCiR =
OCiE bit is set
PRESC
– Sets a flag in the status register
– Generates an interrupt if enabled
Where:
∆t
= Output compare period (in seconds)
= CPU clock frequency (in hertz)
Two 16-bit registers Output Compare Register 1
(OC1R) and Output Compare Register 2 (OC2R)
contain the value to be compared to the counter
register each timer clock cycle.
f
CPU
= Timer prescaler factor (2, 4 or 8 de-
pending on CC[1:0] bits, see Table 18,
"Clock Control Bits")
PRESC
MS byte
LS byte
OCiR
OCiHR
OCiLR
If the timer clock is an external clock, the formula
is:
These registers are readable and writable and are
not affected by the timer hardware. A reset event
changes the OCiR value to 8000h.
∆ OCiR = ∆t f
* EXT
Timing resolution is one count of the free running
Where:
counter: (f
).
CC[1:0]
CPU/
∆t
= Output compare period (in seconds)
= External timer clock frequency (in hertz)
f
EXT
Procedure:
To use the output compare function, select the fol-
lowing in the CR2 register:
Clearing the output compare interrupt request
(that is, clearing the OCFi bit) is done by:
– Set the OCiE bit if an output is needed then the
OCMPi pin is dedicated to the output compare i
signal.
1. Reading the SR register while the OCFi bit is
set.
2. An access (read or write) to the OCiLR register.
– Select the timer clock (CC[1:0]) (see Table 18,
"Clock Control Bits").
The following procedure is recommended to pre-
vent the OCFi bit from being set between the time
it is read and the write to the OCiR register:
And select the following in the CR1 register:
– Select the OLVLi bit to applied to the OCMPi pins
after the match occurs.
– Write to the OCiHR register (further compares
are inhibited).
– Set the OCIE bit to generate an interrupt if it is
needed.
– Read the SR register (first step of the clearance
of the OCFi bit, which may be already set).
When a match is found between OCiR register
and CR register:
– Write to the OCiLR register (enables the output
compare function and clears the OCFi bit).
– OCFi bit is set.
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ST7263BDx ST7263BHx ST7263BKx ST7263BE
16-bit timer (Cont’d)
Notes:
Forced Compare output capability
1. After a processor write cycle to the OCiHR reg-
ister, the output compare function is inhibited
until the OCiLR register is also written.
When the FOLVi bit is set by software, the OLVLi
bit is copied to the OCMPi pin. The OLVi bit has to
be toggled in order to toggle the OCMPi pin when
it is enabled (OCiE bit = 1). The OCFi bit is then
not set by hardware, and thus no interrupt request
is generated.
2. If the OCiE bit is not set, the OCMPi pin is a
general I/O port and the OLVLi bit will not
appear when a match is found but an interrupt
could be generated if the OCIE bit is set.
The FOLVLi bits have no effect in both One Pulse
mode and PWM mode.
3. In both internal and external clock modes,
OCFi and OCMPi are set while the counter
value equals the OCiR register value (see Fig-
ure 34 on page 53 for an example with f
/2
CPU
and Figure 35 on page 53 for an example with
/4). This behavior is the same in OPM or
f
CPU
PWM mode.
4. The output compare functions can be used both
for generating external events on the OCMPi
pins even if the input capture mode is also
used.
5. The value in the 16-bit OCiR register and the
OLVi bit should be changed after each suc-
cessful comparison in order to control an output
waveform or establish a new elapsed timeout.
Figure 33. Output Compare block diagram
16 BIT FREE RUNNING
OC1E
CC1 CC0
OC2E
COUNTER
(Control Register 2) CR2
16-bit
(Control Register 1) CR1
OUTPUT COMPARE
CIRCUIT
Latch
1
OCIE
FOLV2 FOLV1OLVL2
OLVL1
OCMP1
Pin
16-bit
16-bit
Latch
2
OCMP2
Pin
OC1R Register
OCF1
OCF2
0
0
0
OC2R Register
(Status Register) SR
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ST7263BDx ST7263BHx ST7263BKx ST7263BE
16-bit timer (Cont’d)
Figure 34. Output Compare timing diagram, f
= f
/2
TIMER
CPU
INTERNAL CPU CLOCK
TIMER CLOCK
COUNTER REGISTER
2ECF 2ED0 2ED1 2ED2
2ED3
2ED4
2ED3
OUTPUT COMPARE REGISTER i (OCRi)
OUTPUT COMPARE FLAG i (OCFi)
OCMPi PIN (OLVLi = 1)
Figure 35. Output Compare timing diagram, f
= f
/4
TIMER
CPU
INTERNAL CPU CLOCK
TIMER CLOCK
2ECF 2ED0 2ED1 2ED2
2ED3
2ED4
2ED3
COUNTER REGISTER
OUTPUT COMPARE REGISTER i (OCRi)
OUTPUT COMPARE FLAG i (OCFi)
OCMPi PIN (OLVLi = 1)
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ST7263BDx ST7263BHx ST7263BKx ST7263BE
16-bit timer (Cont’d)
12.2.3.5 One Pulse mode
Clearing the Input Capture interrupt request (that
is, clearing the ICFi bit) is done in two steps:
One Pulse mode enables the generation of a
pulse when an external event occurs. This mode is
selected via the OPM bit in the CR2 register.
1. Reading the SR register while the ICFi bit is set.
2. An access (read or write) to the ICiLR register.
The One Pulse mode uses the Input Capture1
function and the Output Compare1 function.
The OC1R register value required for a specific
timing application can be calculated using the fol-
lowing formula:
Procedure:
t * f
To use One Pulse mode:
CPU
- 5
OCiR value =
1. Load the OC1R register with the value corre-
sponding to the length of the pulse (see the for-
PRESC
Where:
t
mula in the opposite column).
= Pulse period (in seconds)
2. Select the following in the CR1 register:
f
= CPU clock frequency (in hertz)
CPU
– Using the OLVL1 bit, select the level to be ap-
plied to the OCMP1 pin after the pulse.
= Timer prescaler factor (2, 4 or 8 depend-
ing on the CC[1:0] bits, see Table 18,
"Clock Control Bits")
PRESC
– Using the OLVL2 bit, select the level to be ap-
plied to the OCMP1 pin during the pulse.
If the timer clock is an external clock the formula is:
– Select the edge of the active transition on the
ICAP1 pin with the IEDG1 bit (the ICAP1 pin
must be configured as floating input).
OCiR = t f
-5
* EXT
Where:
t
3. Select the following in the CR2 register:
= Pulse period (in seconds)
– Set the OC1E bit, the OCMP1 pin is then ded-
icated to the Output Compare 1 function.
f
= External timer clock frequency (in hertz)
EXT
– Set the OPM bit.
When the value of the counter is equal to the value
of the contents of the OC1R register, the OLVL1
bit is output on the OCMP1 pin, (See Figure 36).
– Select the timer clock CC[1:0] (see Table 18,
"Clock Control Bits").
One Pulse mode cycle
Notes:
1. The OCF1 bit cannot be set by hardware in
One Pulse mode but the OCF2 bit can generate
an Output Compare interrupt.
ICR1 = Counter
When
OCMP1 = OLVL2
event occurs
on ICAP1
Counter is reset
2. When the Pulse Width Modulation (PWM) and
One Pulse mode (OPM) bits are both set, the
PWM mode is the only active one.
to FFFCh
ICF1 bit is set
3. If OLVL1 = OLVL2 a continuous signal will be
seen on the OCMP1 pin.
When
Counter
OCMP1 = OLVL1
= OC1R
4. The ICAP1 pin can not be used to perform input
capture. The ICAP2 pin can be used to perform
input capture (ICF2 can be set and IC2R can be
loaded) but the user must take care that the
counter is reset each time a valid edge occurs
on the ICAP1 pin and ICF1 can also generates
interrupt if ICIE is set.
Then, on a valid event on the ICAP1 pin, the coun-
ter is initialized to FFFCh and OLVL2 bit is loaded
on the OCMP1 pin, the ICF1 bit is set and the val-
ue FFFDh is loaded in the IC1R register.
Because the ICF1 bit is set when an active edge
occurs, an interrupt can be generated if the ICIE
bit is set.
5. When One Pulse mode is used OC1R is dedi-
cated to this mode. Nevertheless OC2R and
OCF2 can be used to indicate a period of time
has been elapsed but cannot generate an out-
put waveform because the level OLVL2 is dedi-
cated to the One Pulse mode.
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ST7263BDx ST7263BHx ST7263BKx ST7263BE
16-bit timer (Cont’d)
Figure 36. One Pulse mode timing example
2ED3
01F8
IC1R
FFFC FFFD FFFE
2ED0 2ED1 2ED2
2ED3
FFFC FFFD
01F8
COUNTER
ICAP1
OLVL2
OLVL1
OLVL2
OCMP1
compare1
Note: IEDG1 = 1, OC1R = 2ED0h, OLVL1 = 0, OLVL2 = 1
Figure 37. Pulse Width Modulation mode timing example with 2 Output Compare functions
2ED0 2ED1 2ED2
34E2 FFFC
FFFC FFFD FFFE
34E2
COUNTER
OCMP1
OLVL2
OLVL1
OLVL2
compare2
compare1
compare2
Note: OC1R = 2ED0h, OC2R = 34E2, OLVL1 = 0, OLVL2 = 1
Note: On timers with only one Output Compare register, a fixed frequency PWM signal can be generated
using the output compare and the counter overflow to define the pulse length.
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ST7263BDx ST7263BHx ST7263BKx ST7263BE
16-bit timer (Cont’d)
12.2.3.6 Pulse Width Modulation mode
If OLVL1 = 1 and OLVL2 = 0 the length of the pos-
itive pulse is the difference between the OC2R and
OC1R registers.
Pulse Width Modulation (PWM) mode enables the
generation of a signal with a frequency and pulse
length determined by the value of the OC1R and
OC2R registers.
If OLVL1 = OLVL2 a continuous signal will be
seen on the OCMP1 pin.
Pulse Width Modulation mode uses the complete
Output Compare 1 function plus the OC2R regis-
ter, and so this functionality can not be used when
PWM mode is activated.
The OCiR register value required for a specific tim-
ing application can be calculated using the follow-
ing formula:
t * f
CPU
PRESC
- 5
OCiR value =
In PWM mode, double buffering is implemented on
the output compare registers. Any new values writ-
ten in the OC1R and OC2R registers are taken
into account only at the end of the PWM period
(OC2) to avoid spikes on the PWM output pin
(OCMP1).
Where:
t
= Signal or pulse period (in seconds)
= CPU clock frequency (in hertz)
f
CPU
= Timer prescaler factor (2, 4 or 8 depend-
ing on CC[1:0] bits, see Table 18,
"Clock Control Bits")
PRESC
Procedure
To use Pulse Width Modulation mode:
If the timer clock is an external clock the formula is:
1. Load the OC2R register with the value corre-
sponding to the period of the signal using the
formula in the opposite column.
OCiR = t f
-5
* EXT
2. Load the OC1R register with the value corre-
sponding to the period of the pulse if
(OLVL1 = 0 and OLVL2 = 1) using the formula
in the opposite column.
Where:
t
= Signal or pulse period (in seconds)
f
= External timer clock frequency (in hertz)
EXT
3. Select the following in the CR1 register:
The Output Compare 2 event causes the counter
to be initialized to FFFCh (See Figure 37)
– Using the OLVL1 bit, select the level to be ap-
plied to the OCMP1 pin after a successful
comparison with the OC1R register.
Notes:
– Using the OLVL2 bit, select the level to be ap-
plied to the OCMP1 pin after a successful
comparison with the OC2R register.
1. After a write instruction to the OCiHR register,
the output compare function is inhibited until the
OCiLR register is also written.
4. Select the following in the CR2 register:
2. The OCF1 and OCF2 bits cannot be set by
hardware in PWM mode therefore the Output
Compare interrupt is inhibited.
– Set OC1E bit: the OCMP1 pin is then dedicat-
ed to the output compare 1 function.
3. The ICF1 bit is set by hardware when the coun-
ter reaches the OC2R value and can produce a
timer interrupt if the ICIE bit is set and the I bit is
cleared.
– Set the PWM bit.
– Select the timer clock (CC[1:0]) (see Table 18,
"Clock Control Bits").
Pulse Width Modulation cycle
4. In PWM mode the ICAP1 pin can not be used
to perform input capture because it is discon-
nected to the timer. The ICAP2 pin can be used
to perform input capture (ICF2 can be set and
IC2R can be loaded) but the user must take
care that the counter is reset each period and
ICF1 can also generates interrupt if ICIE is set.
When
Counter
= OC1R
OCMP1 = OLVL1
OCMP1 = OLVL2
5. When the Pulse Width Modulation (PWM) and
One Pulse mode (OPM) bits are both set, the
PWM mode is the only active one.
When
Counter
= OC2R
Counter is reset
to FFFCh
ICF1 bit is set
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16-bit timer (Cont’d)
12.2.4 Low power modes
Mode
Description
No effect on 16-bit timer.
Timer interrupts cause the device to exit from Wait mode.
Wait
Halt
16-bit timer registers are frozen.
In Halt mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous
count when the MCU is woken up by an interrupt with “exit from Halt mode” capability or from the counter
reset value when the MCU is woken up by a RESET.
If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is armed. Consequent-
ly, when the MCU is woken up by an interrupt with “exit from Halt mode” capability, the ICFi bit is set, and
the counter value present when exiting from Halt mode is captured into the ICiR register.
12.2.5 Interrupts
Enable
control from
bit
Exit
Exit
from
Halt
Event
flag
Interrupt event
Wait
Input Capture 1 event/Counter reset in PWM mode
Input Capture 2 event
ICF1
ICF2
ICIE
Output Compare 1 event (not available in PWM mode)
Output Compare 2 event (not available in PWM mode)
Timer Overflow event
OCF1
OCF2
TOF
Yes
No
OCIE
TOIE
Note: The 16-bit timer interrupt events are connected to the same interrupt vector (see Interrupts chap-
ter). These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt
mask in the CC register is reset (RIM instruction).
12.2.6 Summary of timer modes
Timer resources
MODES
Input Capture 1
Input Capture 2
Output Compare 1 Output Compare 2
Input Capture (1 and/or 2)
Output Compare (1 and/or 2)
One Pulse mode
Yes
Yes
Yes
No
Yes
1)
3)
2)
Not Recommended
Not Recommended
Partially
No
No
PWM mode
1) See note 4 in Section 12.2.3.5, "One Pulse mode"
2) See note 5 in Section 12.2.3.5, "One Pulse mode"
3) See note 4 in Section 12.2.3.6, "Pulse Width Modulation mode"
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ST7263BDx ST7263BHx ST7263BKx ST7263BE
16-bit timer (Cont’d)
12.2.7 Register description
Bit 4 = FOLV2 Forced Output Compare 2.
This bit is set and cleared by software.
0: No effect on the OCMP2 pin.
1:Forces the OLVL2 bit to be copied to the
OCMP2 pin, if the OC2E bit is set and even if
there is no successful comparison.
Each Timer is associated with three control and
status registers, and with six pairs of data registers
(16-bit values) relating to the two input captures,
the two output compares, the counter and the al-
ternate counter.
Bit 3 = FOLV1 Forced Output Compare 1.
This bit is set and cleared by software.
0: No effect on the OCMP1 pin.
Control Register 1 (CR1)
Read/Write
1: Forces OLVL1 to be copied to the OCMP1 pin, if
the OC1E bit is set and even if there is no suc-
cessful comparison.
Reset value: 0000 0000 (00h)
7
0
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
Bit 2 = OLVL2 Output Level 2.
This bit is copied to the OCMP2 pin whenever a
successful comparison occurs with the OC2R reg-
ister and OCxE is set in the CR2 register. This val-
ue is copied to the OCMP1 pin in One Pulse mode
and Pulse Width Modulation mode.
Bit 7 = ICIE Input Capture Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the
ICF1 or ICF2 bit of the SR register is set.
Bit 6 = OCIE Output Compare Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the
OCF1 or OCF2 bit of the SR register is set.
Bit 1 = IEDG1 Input Edge 1.
This bit determines which type of level transition
on the ICAP1 pin will trigger the capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
Bit 5 = TOIE Timer Overflow Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is enabled whenever the TOF
bit of the SR register is set.
Bit 0 = OLVL1 Output Level 1.
The OLVL1 bit is copied to the OCMP1 pin when-
ever a successful comparison occurs with the
OC1R register and the OC1E bit is set in the CR2
register.
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ST7263BDx ST7263BHx ST7263BKx ST7263BE
16-bit timer (Cont’d)
Control Register 2 (CR2)
Read/Write
Bit 4 = PWM Pulse Width Modulation.
0: PWM mode is not active.
1: PWM mode is active, the OCMP1 pin outputs a
programmable cyclic signal; the length of the
pulse depends on the value of OC1R register;
the period depends on the value of OC2R regis-
ter.
Reset value: 0000 0000 (00h)
7
0
OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG
Bit 3, 2 = CC[1:0] Clock Control.
Bit 7 = OC1E Output Compare 1 Pin Enable.
This bit is used only to output the signal from the
timer on the OCMP1 pin (OLV1 in Output Com-
pare mode, both OLV1 and OLV2 in PWM and
one-pulse mode). Whatever the value of the OC1E
bit, the Output Compare 1 function of the timer re-
mains active.
0: OCMP1 pin alternate function disabled (I/O pin
free for general-purpose I/O).
1: OCMP1 pin alternate function enabled.
The timer clock mode depends on these bits:
Table 18. Clock Control Bits
Timer Clock
CC1
CC0
fCPU / 4
fCPU / 2
fCPU / 8
0
1
0
1
0
1
External Clock (where available)
Note: If the external clock pin is not available, pro-
gramming the external clock configuration stops
the counter.
Bit 6 = OC2E Output Compare 2 Pin Enable.
This bit is used only to output the signal from the
timer on the OCMP2 pin (OLV2 in Output Com-
pare mode). Whatever the value of the OC2E bit,
the Output Compare 2 function of the timer re-
mains active.
0: OCMP2 pin alternate function disabled (I/O pin
free for general-purpose I/O).
1: OCMP2 pin alternate function enabled.
Bit 1 = IEDG2 Input Edge 2.
This bit determines which type of level transition
on the ICAP2 pin will trigger the capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
Bit 5 = OPM One Pulse Mode.
0: One Pulse mode is not active.
1: One Pulse mode is active, the ICAP1 pin can be
used to trigger one pulse on the OCMP1 pin; the
active transition is given by the IEDG1 bit. The
length of the generated pulse depends on the
contents of the OC1R register.
Bit 0 = EXEDG External Clock Edge.
This bit determines which type of level transition
on the external clock pin EXTCLK will trigger the
counter register.
0: A falling edge triggers the counter register.
1: A rising edge triggers the counter register.
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ST7263BDx ST7263BHx ST7263BKx ST7263BE
16-bit timer (Cont’d)
Control/status Register (CSR)
Read/Write (bits 7:3 read only)
Reset value: xxxx x0xx (xxh)
Note: Reading or writing the ACLR register does
not clear TOF.
Bit 4 = ICF2 Input Capture flag 2.
0: No input capture (reset value).
1: An input capture has occurred on the ICAP2
pin. To clear this bit, first read the SR register,
then read or write the low byte of the IC2R
(IC2LR) register.
7
0
0
ICF1 OCF1 TOF ICF2 OCF2 TIMD
0
Bit 7 = ICF1 Input Capture flag 1.
0: No input capture (reset value).
1: An input capture has occurred on the ICAP1 pin
or the counter has reached the OC2R value in
PWM mode. To clear this bit, first read the SR
register, then read or write the low byte of the
IC1R (IC1LR) register.
Bit 3 = OCF2 Output Compare flag 2.
0: No match (reset value).
1: The content of the free running counter has
matched the content of the OC2R register. To
clear this bit, first read the SR register, then read
or write the low byte of the OC2R (OC2LR) reg-
ister.
Bit 6 = OCF1 Output Compare flag 1.
0: No match (reset value).
1: The content of the free running counter has
matched the content of the OC1R register. To
clear this bit, first read the SR register, then read
or write the low byte of the OC1R (OC1LR) reg-
ister.
Bit 2 = TIMD Timer disable.
This bit is set and cleared by software. When set, it
freezes the timer prescaler and counter and disa-
bled the output functions (OCMP1 and OCMP2
pins) to reduce power consumption. Access to the
timer registers is still available, allowing the timer
configuration to be changed, or the counter reset,
while it is disabled.
Bit 5 = TOF Timer Overflow flag.
0: No timer overflow (reset value).
1:The free running counter rolled over from FFFFh
to 0000h. To clear this bit, first read the SR reg-
ister, then read or write the low byte of the CR
(CLR) register.
0: Timer enabled
1: Timer prescaler, counter and outputs disabled
Bits 1:0 = Reserved, must be kept cleared.
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ST7263BDx ST7263BHx ST7263BKx ST7263BE
Output Compare 1 High Register (OC1HR)
16-bit timer (Cont’d)
Input Capture 1 High Register (IC1HR)
Read Only
Reset value: Undefined
Read/Write
Reset value: 1000 0000 (80h)
This is an 8-bit read only register that contains the
high part of the counter value (transferred by the
input capture 1 event).
This is an 8-bit register that contains the high part
of the value to be compared to the CHR register.
7
0
7
0
MSB
LSB
MSB
LSB
Output Compare 1 Low Register (OC1LR)
Input Capture 1 Low Register (IC1LR)
Read/Write
Read Only
Reset value: 0000 0000 (00h)
Reset value: Undefined
This is an 8-bit register that contains the low part of
the value to be compared to the CLR register.
This is an 8-bit read only register that contains the
low part of the counter value (transferred by the in-
put capture 1 event).
7
0
7
0
MSB
LSB
MSB
LSB
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ST7263BDx ST7263BHx ST7263BKx ST7263BE
16-bit timer (Cont’d)
Output Compare 2 High Register (OC2HR)
Alternate Counter High Register (ACHR)
Read/Write
Reset value: 1000 0000 (80h)
Read Only
Reset value: 1111 1111 (FFh)
This is an 8-bit register that contains the high part
of the value to be compared to the CHR register.
This is an 8-bit register that contains the high part
of the counter value.
7
0
7
0
MSB
LSB
MSB
LSB
Output Compare 2 Low Register (OC2LR)
Alternate Counter Low Register (ACLR)
Read/Write
Reset value: 0000 0000 (00h)
Read Only
Reset value: 1111 1100 (FCh)
This is an 8-bit register that contains the low part of
the value to be compared to the CLR register.
This is an 8-bit register that contains the low part of
the counter value. A write to this register resets the
counter. An access to this register after an access
to CSR register does not clear the TOF bit in the
CSR register.
7
0
MSB
LSB
7
0
Counter High Register (CHR)
MSB
LSB
Read Only
Reset value: 1111 1111 (FFh)
Input Capture 2 High Register (IC2HR)
This is an 8-bit register that contains the high part
of the counter value.
Read Only
Reset value: Undefined
7
0
This is an 8-bit read only register that contains the
high part of the counter value (transferred by the
Input Capture 2 event).
MSB
LSB
7
0
MSB
LSB
Counter Low Register (CLR)
Read Only
Reset value: 1111 1100 (FCh)
This is an 8-bit register that contains the low part of
the counter value. A write to this register resets the
counter. An access to this register after accessing
the CSR register clears the TOF bit.
Input Capture 2 Low Register (IC2LR)
Read Only
Reset value: Undefined
This is an 8-bit read only register that contains the
low part of the counter value (transferred by the In-
put Capture 2 event).
7
0
MSB
LSB
7
0
MSB
LSB
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ST7263BDx ST7263BHx ST7263BKx ST7263BE
16-bit timer (Cont’d)
Table 19. 16-bit timer register map and reset values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
CR2
OC1E
0
OC2E
OPM
0
PWM
CC1
CC0
IEDG2
EXEDG
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
Reset value
CR1
0
OCIE
0
0
FOLV2
0
0
FOLV1
0
0
OLVL2
0
0
0
ICIE
0
TOIE
0
IEDG1
OLVL1
Reset value
CSR
0
0
0
0
0
0
ICF1
0
OCF1
0
TOF
0
ICF2
0
OCF2
0
TIMD
0
Reset value
IC1HR
MSB
MSB
LSB
LSB
Reset value
IC1LR
Reset value
OC1HR
MSB
1
-
0
-
0
-
0
-
0
-
0
-
0
LSB
0
Reset value
OC1LR
MSB
0
-
0
-
0
-
0
-
0
-
0
-
0
LSB
0
Reset value
CHR
MSB
1
-
1
-
1
-
1
-
1
-
1
-
1
LSB
1
Reset value
CLR
MSB
1
-
1
-
1
-
1
-
1
-
1
-
0
LSB
0
Reset value
ACHR
MSB
1
-
1
-
1
-
1
-
1
-
1
-
1
LSB
1
Reset value
ACLR
MSB
1
-
1
-
1
-
1
-
1
-
1
-
0
LSB
0
Reset value
IC2HR
MSB
MSB
LSB
LSB
Reset value
IC2LR
Reset value
OC2HR
MSB
1
-
0
-
0
-
0
-
0
-
0
-
0
LSB
0
Reset value
OC2LR
MSB
0
-
0
-
0
-
0
-
0
-
0
-
0
LSB
0
Reset value
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ST7263BDx ST7263BHx ST7263BKx ST7263BE
12.3 Serial communications interface (SCI)
12.3.1 Introduction
12.3.3 General description
The Serial Communications Interface (SCI) offers
a flexible means of full-duplex data exchange with
external equipment requiring an industry standard
NRZ asynchronous serial data format. The SCI of-
fers a very wide range of baud rates using two
baud rate generator systems.
The interface is externally connected to another
device by two pins (see Figure 39):
– TDO: Transmit Data Output. When the transmit-
ter and the receiver are disabled, the output pin
returns to its I/O port configuration. When the
transmitter and/or the receiver are enabled and
nothing is to be transmitted, the TDO pin is at
high level.
12.3.2 Main features
■ Full duplex, asynchronous communications
■ NRZ standard format (Mark/Space)
■ Independently programmable transmit and
receive baud rates up to 250K baud.
■ Programmable data word length (8 or 9 bits)
– RDI: Receive Data Input is the serial data input.
Oversampling techniques are used for data re-
covery by discriminating between valid incoming
data and noise.
Through these pins, serial data is transmitted and
received as frames comprising:
■ Receive buffer full, Transmit buffer empty and
End of Transmission flags
■ Two receiver wake-up modes:
– Address bit (MSB)
– An Idle Line prior to transmission or reception
– A start bit
– A data word (8 or 9 bits) least significant bit first
– A Stop bit indicating that the frame is complete.
Thisinterfaceusestwotypesofbaudrategenerator:
– Idle line
■ Mutingfunctionformultiprocessorconfigurations
■ Separate enable bits for Transmitter and
Receiver
■ Four error detection flags:
– Overrun error
– A conventional type for commonly-used baud
rates.
– Noise error
– Frame error
– Parity error
■ Six interrupt sources with flags:
– Transmit data register empty
– Transmission complete
– Receive data register full
– Idle line received
– Overrun error detected
– Parity error
■ Parity control:
– Transmits parity bit
– Checks parity of received data byte
■ Reduced power consumption mode
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ST7263BDx ST7263BHx ST7263BKx ST7263BE
Serial communications interface (Cont’d)
Figure 38. SCI block diagram
Write
Read
(DATA REGISTER) DR
Received Data Register (RDR)
Received Shift Register
Transmit Data Register (TDR)
TDO
Transmit Shift Register
RDI
CR1
R8 T8 SCID
M WAKE PCE PS PIE
WAKE
UP
UNIT
TRANSMIT
CONTROL
RECEIVER
CLOCK
RECEIVER
CONTROL
CR2
SR
TIE TCIE RIE ILIE TE RE RWU SBK
TDRE TC RDRF IDLE OR NF FE
PE
SCI
INTERRUPT
CONTROL
TRANSMITTER
CLOCK
TRANSMITTER RATE
CONTROL
f
CPU
/PR
/16
BRR
SCP1
SCT2
SCT1SCT0SCR2 SCR1SCR0
SCP0
RECEIVER RATE
CONTROL
BAUD RATE GENERATOR
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ST7263BDx ST7263BHx ST7263BKx ST7263BE
Serial communication interface (Cont’d)
12.3.4 Functional description
The TDO pin is in low state during the start bit.
The TDO pin is in high state during the stop bit.
The block diagram of the Serial Control Interface,
is shown in Figure 38 It contains 6 dedicated reg-
isters:
An Idle character is interpreted as an entire frame
of “1”s followed by the start bit of the next frame
which contains data.
– Two control registers (SCICR1 & SCICR2)
– A status register (SCISR)
A Break character is interpreted on receiving “0”s
for some multiple of the frame period. At the end of
the last break frame the transmitter inserts an ex-
tra “1” bit to acknowledge the start bit.
– A baud rate register (SCIBRR)
Refer to the register descriptions in Section 12.3.7
for the definitions of each bit.
Transmission and reception are driven by their
own baud rate generator.
12.3.4.1 Serial data format
Word length may be selected as being either 8 or 9
bits by programming the M bit in the SCICR1 reg-
ister (see Figure 38).
Figure 39. Word length programming
9-bit Word length (M bit is set)
Possible
Next Data Frame
Parity
Data Frame
Start
Bit
Next
Start
Bit
Stop
Bit
Bit2
Bit6
Bit3
Bit4
Bit5
Bit8
Bit0 Bit1
Bit7
Bit
Start
Bit
Idle Frame
Start
Bit
Extra
’1’
Break Frame
8-bit Word length (M bit is reset)
Possible
Parity
Next Data Frame
Data Frame
Bit
Next
Start
Bit
Start
Bit
Stop
Bit
Bit2
Bit6
Bit1
Bit3
Bit4
Bit5
Bit7
Bit0
Start
Bit
Idle Frame
Start
Bit
Extra
’1’
Break Frame
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ST7263BDx ST7263BHx ST7263BKx ST7263BE
Serial communication interface (Cont’d)
12.3.4.2 Transmitter
When a frame transmission is complete (after the
stop bit or after the break frame) the TC bit is set
and an interrupt is generated if the TCIE is set and
the I bit is cleared in the CCR register.
The transmitter can send data words of either 8 or
9 bits depending on the M bit status. When the M
bit is set, word length is 9 bits and the 9th bit (the
MSB) has to be stored in the T8 bit in the SCICR1
register.
Clearing the TC bit is performed by the following
software sequence:
1. An access to the SCISR register
2. A write to the SCIDR register
Character transmission
During an SCI transmission, data shifts out least
significant bit first on the TDO pin. In this mode,
the SCIDR register consists of a buffer (TDR) be-
tween the internal bus and the transmit shift regis-
ter (see Figure 38).
Note: The TDRE and TC bits are cleared by the
same software sequence.
Break characters
Setting the SBK bit loads the shift register with a
break character. The break frame length depends
on the M bit (see Figure 39).
Procedure
– Select the M bit to define the word length.
As long as the SBK bit is set, the SCI send break
frames to the TDO pin. After clearing this bit by
software the SCI insert a logic 1 bit at the end of
the last break frame to guarantee the recognition
of the start bit of the next frame.
– Select the desired baud rate using the SCIBRR
and the SCIETPR registers.
– Set the TE bit to assign the TDO pin to the alter-
nate function and to send a idle frame as first
transmission.
Idle characters
– Access the SCISR register and write the data to
send in the SCIDR register (this sequence clears
the TDRE bit). Repeat this sequence for each
data to be transmitted.
Setting the TE bit drives the SCI to send an idle
frame before the first data frame.
Clearing and then setting the TE bit during a trans-
mission sends an idle frame after the current word.
Clearing the TDRE bit is always performed by the
following software sequence:
1. An access to the SCISR register
2. A write to the SCIDR register
Note: Resetting and setting the TE bit causes the
data in the TDR register to be lost. Therefore the
best time to toggle the TE bit is when the TDRE bit
is set i.e. before writing the next byte in the SCIDR.
The TDRE bit is set by hardware and it indicates:
– The TDR register is empty.
– The data transfer is beginning.
– The next data can be written in the SCIDR regis-
ter without overwriting the previous data.
This flag generates an interrupt if the TIE bit is set
and the I bit is cleared in the CCR register.
When a transmission is taking place, a write in-
struction to the SCIDR register stores the data in
the TDR register and which is copied in the shift
register at the end of the current transmission.
When no transmission is taking place, a write in-
struction to the SCIDR register places the data di-
rectly in the shift register, the data transmission
starts, and the TDRE bit is immediately set.
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Serial communication interface (Cont’d)
12.3.4.3 Receiver
RDR register as long as the RDRF bit is not
cleared.
The SCI can receive data words of either 8 or 9
bits. When the M bit is set, word length is 9 bits
and the MSB is stored in the R8 bit in the SCICR1
register.
When a overrun error occurs:
– The OR bit is set.
– The RDR content will not be lost.
– The shift register will be overwritten.
Character reception
During a SCI reception, data shifts in least signifi-
cant bit first through the RDI pin. In this mode, the
SCIDR register consists or a buffer (RDR) be-
tween the internal bus and the received shift regis-
ter (see Figure 38).
– An interrupt is generated if the RIE bit is set and
the I bit is cleared in the CCR register.
The OR bit is reset by an access to the SCISR reg-
ister followed by a SCIDR register read operation.
Procedure
Noise error
– Select the M bit to define the word length.
Oversampling techniques are used for data recov-
ery by discriminating between valid incoming data
and noise. Normal data bits are considered valid if
three consecutive samples (8th, 9th, 10th) have
the same bit value, otherwise the NF flag is set. In
the case of start bit detection, the NF flag is set on
the basis of an algorithm combining both valid
edge detection and three samples (8th, 9th, 10th).
Therefore, to prevent the NF flag getting set during
start bit reception, there should be a valid edge de-
tection as well as three valid samples.
– Select the desired baud rate using the SCIBRR
and the SCIERPR registers.
– Set the RE bit, this enables the receiver which
begins searching for a start bit.
When a character is received:
– The RDRF bit is set. It indicates that the content
of the shift register is transferred to the RDR.
– An interrupt is generated if the RIE bit is set and
the I bit is cleared in the CCR register.
When noise is detected in a frame:
– The error flags can be set if a frame error, noise
or an overrun error has been detected during re-
ception.
– The NF flag is set at the rising edge of the RDRF
bit.
– Data is transferred from the Shift register to the
SCIDR register.
Clearing the RDRF bit is performed by the following
software sequence done by:
– No interrupt is generated. However this bit rises
at the same time as the RDRF bit which itself
generates an interrupt.
1. An access to the SCISR register
2. A read to the SCIDR register.
The RDRF bit must be cleared before the end of the
reception of the next character to avoid an overrun
error.
The NF flag is reset by a SCISR register read op-
eration followed by a SCIDR register read opera-
tion.
Break characters
During reception, if a false start bit is detected (e.g.
8th, 9th, 10th samples are 011,101,110), the
frame is discarded and the receiving sequence is
not started for this frame. There is no RDRF bit set
for this frame and the NF flag is set internally (not
accessible to the user). This NF flag is accessible
along with the RDRF bit when a next valid frame is
received.
When a break character is received, the SCI han-
dles it as a framing error.
Idle characters
When a idle frame is detected, there is the same
procedure as a data received character plus an in-
terrupt if the ILIE bit is set and the I bit is cleared in
the CCR register.
Note: If the application Start Bit is not long enough
to match the above requirements, then the NF flag
may get set due to the short Start Bit. In this case,
the NF flag may be ignored by the application soft-
ware when the first valid byte is received.
Overrun error
An overrun error occurs when a character is re-
ceived when RDRF has not been reset. Data can
not be transferred from the shift register to the
See also Section 12.3.4.9.
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12.3.4.5 Receiver Muting and Wake-up feature
Serial communication interface (Cont’d)
Framing error
A framing error is detected when:
In multiprocessor configurations it is often desira-
ble that only the intended message recipient
should actively receive the full message contents,
thus reducing redundant SCI service overhead for
all non addressed receivers.
– The stop bit is not recognized on reception at the
expected time, following either a de-synchroni-
zation or excessive noise.
– A break is received.
The non addressed devices may be placed in
sleep mode by means of the muting function.
When the framing error is detected:
– the FE bit is set by hardware
Setting the RWU bit by software puts the SCI in
sleep mode:
– Data is transferred from the Shift register to the
SCIDR register.
All the reception status bits can not be set.
All the receive interrupts are inhibited.
– No interrupt is generated. However this bit rises
at the same time as the RDRF bit which itself
generates an interrupt.
A muted receiver may be awakened by one of the
following two ways:
The FE bit is reset by a SCISR register read oper-
ation followed by a SCIDR register read operation.
– by Idle Line detection if the WAKE bit is reset,
– by Address Mark detection if the WAKE bit is set.
12.3.4.4 Baud rate generation
Receiver wakes-up by Idle Line detection when
the Receive line has recognised an Idle Frame.
Then the RWU bit is reset by hardware but the
IDLE bit is not set.
The baud rate for the receiver and transmitter (Rx
and Tx) are set independently and calculated as
follows:
f
f
CPU
CPU
Receiver wakes-up by Address Mark detection
when it received a “1” as the most significant bit of
a word, thus indicating that the message is an ad-
dress. The reception of this particular word wakes
up the receiver, resets the RWU bit and sets the
RDRF bit, which allows the receiver to receive this
word normally and to use it as an address word.
Rx =
Tx =
(16 PR) RR
(16 PR) TR
*
*
*
*
with:
PR = 1, 3, 4 or 13 (see SCP[1:0] bits)
TR = 1, 2, 4, 8, 16, 32, 64,128
(see SCT[2:0] bits)
Caution: In Mute mode, do not write to the
SCICR2 register. If the SCI is in Mute mode during
the read operation (RWU=1) and a address mark
wake up event occurs (RWU is reset) before the
write operation, the RWU bit will be set again by
this write operation. Consequently the address
RR = 1, 2, 4, 8, 16, 32, 64,128
(see SCR[2:0] bits)
All these bits are in the SCIBRR register.
Example: If f is 8 MHz (normal mode) and if
CPU
byte is lost and the SCI is not woken up from Mute
mode.
PR=13 and TR=RR=1, the transmit and receive
baud rates are 38400 baud.
Note: the baud rate registers MUST NOT be
changed while the transmitter or the receiver is en-
abled.
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Serial communication interface (Cont’d)
12.3.4.6 Parity control
even number of “1s” if even parity is selected
(PS=0) or an odd number of “1s” if odd parity is se-
lected (PS=1). If the parity check fails, the PE flag
is set in the SCISR register and an interrupt is gen-
erated if PIE is set in the SCICR1 register.
Parity control (generation of parity bit in transmis-
sion and parity checking in reception) can be ena-
bled by setting the PCE bit in the SCICR1 register.
Depending on the frame length defined by the M
bit, the possible SCI frame formats are as listed in
Table 20.
12.3.4.7 SCI clock tolerance
During reception, each bit is sampled 16 times.
The majority of the 8th, 9th and 10th samples is
considered as the bit value. For a valid bit detec-
tion, all the three samples should have the same
value otherwise the noise flag (NF) is set. For ex-
ample: if the 8th, 9th and 10th samples are 0, 1
and 1 respectively, then the bit value will be “1”,
but the Noise flag bit is be set because the three
samples values are not the same.
Table 20. Frame formats
M bit
PCE bit
SCI frame
0
0
1
1
0
1
0
1
| SB | 8 bit data | STB |
| SB | 7-bit data | PB | STB |
| SB | 9-bit data | STB |
| SB | 8-bit data PB | STB |
Legend: SB = Start Bit, STB = Stop Bit,
PB = Parity Bit
Consequently, the bit length must be long enough
so that the 8th, 9th and 10th samples have the de-
sired bit value. This means the clock frequency
should not vary more than 6/16 (37.5%) within one
bit. The sampling clock is resynchronized at each
start bit, so that when receiving 10 bits (one start
bit, 1 data byte, 1 stop bit), the clock deviation
must not exceed 3.75%.
Note: In case of wake up by an address mark, the
MSB bit of the data is taken into account and not
the parity bit
Even parity: the parity bit is calculated to obtain
an even number of “1s” inside the frame made of
the 7 or 8 LSB bits (depending on whether M is
equal to 0 or 1) and the parity bit.
Note: The internal sampling clock of the microcon-
troller samples the pin value on every falling edge.
Therefore, the internal sampling clock and the time
the application expects the sampling to take place
may be out of sync. For example: If the baud rate
is 15.625 kbaud (bit length is 64µs), then the 8th,
9th and 10th samples will be at 28µs, 32µs & 36µs
respectively (the first sample starting ideally at
0µs). But if the falling edge of the internal clock oc-
curs just before the pin value changes, the sam-
ples would then be out of sync by ~4us. This
means the entire bit length must be at least 40µs
(36µs for the 10th sample + 4µs for synchroniza-
tion with the internal sampling clock).
Ex: data=00110101; 4 bits set => parity bit will be
0 if even parity is selected (PS bit = 0).
Odd parity: the parity bit is calculated to obtain an
odd number of “1s” inside the frame made of the 7
or 8 LSB bits (depending on whether M is equal to
0 or 1) and the parity bit.
Ex: data=00110101; 4 bits set => parity bit will be
1 if odd parity is selected (PS bit = 1).
Transmission mode: If the PCE bit is set then the
MSB bit of the data written in the data register is
not transmitted but is changed by the parity bit.
Reception mode: If the PCE bit is set then the in-
terface checks if the received data byte has an
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12.3.4.9 Noise error causes
Serial communication interface (Cont’d)
12.3.4.8 Clock deviation causes
The causes which contribute to the total deviation
are:
See also description of Noise error in Section
12.3.4.3.
– D
: Deviation due to transmitter error (Local
Start bit
TRA
oscillator error of the transmitter or the trans-
mitter is transmitting at a different baud rate).
The noise flag (NF) is set during start bit reception
if one of the following conditions occurs:
– D
: Error due to the baud rate quantisa-
QUANT
1. A valid falling edge is not detected. A falling
edge is considered to be valid if the 3 consecu-
tive samples before the falling edge occurs are
detected as '1' and, after the falling edge
occurs, during the sampling of the 16 samples,
if one of the samples numbered 3, 5 or 7 is
detected as a “1”.
tion of the receiver.
– D
: Deviation of the local oscillator of the
REC
receiver: This deviation can occur during the
reception of one complete SCI message as-
suming that the deviation has been compen-
sated at the beginning of the message.
– D
: Deviation due to the transmission line
2. During sampling of the 16 samples, if one of the
samples numbered 8, 9 or 10 is detected as a
“1”.
TCL
(generally due to the transceivers)
All the deviations of the system should be added
and compared to the SCI clock tolerance:
Therefore, a valid Start Bit must satisfy both the
above conditions to prevent the Noise flag getting
set.
D
+ D
+ D
+ D
< 3.75%
TCL
TRA
QUANT
REC
Data bits
The noise flag (NF) is set during normal data bit re-
ception if the following condition occurs:
– During the sampling of 16 samples, if all three
samples numbered 8, 9 and10 are not the same.
The majority of the 8th, 9th and 10th samples is
considered as the bit value.
Therefore, a valid Data Bit must have samples 8, 9
and 10 at the same value to prevent the Noise flag
getting set.
Figure 40. Bit sampling in reception mode
RDI LINE
sampled values
Sample
clock
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
6/16
7/16
7/16
One bit time
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Serial communication interface (Cont’d)
12.3.5 Low power modes
Enable Exit
control from from
Exit
Event
flag
Interrupt event
Mode
Description
bit
Wait
Halt
No effect on SCI.
Transmit Data Register
Empty
TDRE
TC
TIE
Yes
No
Wait
SCI interrupts cause the device to exit
from Wait mode.
Transmission Com-
plete
TCIE
RIE
Yes
Yes
No
No
SCI registers are frozen.
Received Data Ready
to be Read
RDRF
In Halt mode, the SCI stops transmit-
ting/receiving until Halt mode is exit-
ed.
Halt
Overrun Error Detected OR
Yes
Yes
Yes
No
No
No
Idle Line Detected
Parity Error
IDLE
PE
ILIE
PIE
12.3.6 Interrupts
The SCI interrupt events are connected to the
same interrupt vector.
rupt mask in the CC register is reset (RIM instruc-
tion).
These events generate an interrupt if the corre-
sponding Enable Control Bit is set and the inter-
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Serial communication interface (Cont’d)
12.3.7 Register description
Note: The IDLE bit will not be set again until the
RDRF bit has been set itself (i.e. a new idle line oc-
curs).
Status Register (SCISR)
Read Only
Reset value: 1100 0000 (C0h)
Bit 3 = OR Overrun error.
This bit is set by hardware when the word currently
being received in the shift register is ready to be
transferred into the RDR register while RDRF=1.
An interrupt is generated if RIE=1 in the SCICR2
register. It is cleared by a software sequence (an
access to the SCISR register followed by a read to
the SCIDR register).
7
0
TDRE
TC
RDRF IDLE
OR
NF
FE
PE
Bit 7 = TDRE Transmit data register empty.
This bit is set by hardware when the content of the
TDR register has been transferred into the shift
register. An interrupt is generated if the TIE bit=1
in the SCICR2 register. It is cleared by a software
sequence (an access to the SCISR register fol-
lowed by a write to the SCIDR register).
0: No Overrun error
1: Overrun error is detected
Note: When this bit is set RDR register content will
not be lost but the shift register will be overwritten.
0: Data is not transferred to the shift register
1: Data is transferred to the shift register
Bit 2 = NF Noise flag.
Note: Data will not be transferred to the shift reg-
This bit is set by hardware when noise is detected
on a received frame. It is cleared by a software se-
quence (an access to the SCISR register followed
by a read to the SCIDR register).
0: No noise is detected
ister unless the TDRE bit is cleared.
Bit 6 = TC Transmission complete.
This bit is set by hardware when transmission of a
frame containing Data is complete. An interrupt is
generated if TCIE=1 in the SCICR2 register. It is
cleared by a software sequence (an access to the
SCISR register followed by a write to the SCIDR
register).
1: Noise is detected
Note: This bit does not generate interrupt as it ap-
pears at the same time as the RDRF bit which it-
self generates an interrupt.
0: Transmission is not complete
1: Transmission is complete
Bit 1 = FE Framing error.
This bit is set by hardware when a de-synchroniza-
tion, excessive noise or a break character is de-
tected. It is cleared by a software sequence (an
access to the SCISR register followed by a read to
the SCIDR register).
0: No Framing error is detected
1: Framing error or break character is detected
Note: TC is not set after the transmission of a Pre-
amble or a Break.
Bit 5 = RDRF Received data ready flag.
This bit is set by hardware when the content of the
RDR register has been transferred to the SCIDR
register. An interrupt is generated if RIE=1 in the
SCICR2 register. It is cleared by a software se-
quence (an access to the SCISR register followed
by a read to the SCIDR register).
Note: This bit does not generate interrupt as it ap-
pears at the same time as the RDRF bit which it-
self generates an interrupt. If the word currently
being transferred causes both frame error and
overrun error, it will be transferred and only the OR
bit will be set.
0: Data is not received
1: Received data is ready to be read
Bit 4 = IDLE Idle line detect.
This bit is set by hardware when a Idle Line is de-
tected. An interrupt is generated if the ILIE=1 in
the SCICR2 register. It is cleared by a software se-
quence (an access to the SCISR register followed
by a read to the SCIDR register).
0: No Idle Line is detected
1: Idle Line is detected
Bit 0 = PE Parity error.
This bit is set by hardware when a parity error oc-
curs in receiver mode. It is cleared by a software
sequence (a read to the status register followed by
an access to the SCIDR data register). An inter-
rupt is generated if PIE=1 in the SCICR1 register.
0: No parity error
1: Parity error
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Serial communication interface (Cont’d)
Control Register 1 (SCICR1)
Read/Write
Bit 3 = WAKE Wake-Up method.
This bit determines the SCI Wake-Up method, it is
set or cleared by software.
0: Idle Line
Reset value: x000 0000 (x0h)
7
0
1: Address Mark
R8
T8
SCID
M
WAKE PCE
PS
PIE
Bit 2 = PCE Parity control enable.
This bit selects the hardware parity control (gener-
ation and detection). When the parity control is en-
abled, the computed parity is inserted at the MSB
position (9th bit if M=1; 8th bit if M=0) and parity is
checked on the received data. This bit is set and
cleared by software. Once it is set, PCE is active
after the current byte (in reception and in transmis-
sion).
Bit 7 = R8 Receive data bit 8.
This bit is used to store the 9th bit of the received
word when M=1.
Bit 6 = T8 Transmit data bit 8.
This bit is used to store the 9th bit of the transmit-
ted word when M=1.
0: Parity control disabled
1: Parity control enabled
Bit 5 = SCID Disabled for low power consumption
When this bit is set the SCI prescalers and outputs
are stopped and the end of the current byte trans-
fer in order to reduce power consumption.This bit
is set and cleared by software.
0: SCI enabled
1: SCI prescaler and outputs disabled
Bit 1 = PS Parity selection.
This bit selects the odd or even parity when the
parity generation/detection is enabled (PCE bit
set). It is set and cleared by software. The parity
will be selected after the current byte.
0: Even parity
1: Odd parity
Bit 4 = M Word length.
This bit determines the word length. It is set or
cleared by software.
0: 1 Start bit, 8 Data bits, 1 Stop bit
1: 1 Start bit, 9 Data bits, 1 Stop bit
Bit 0 = PIE Parity interrupt enable.
This bit enables the interrupt capability of the hard-
ware parity control when a parity error is detected
(PE bit set). It is set and cleared by software.
0: Parity error interrupt disabled
Note: The M bit must not be modified during a data
transfer (both transmission and reception).
1: Parity error interrupt enabled.
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Serial communication interface (Cont’d)
Control Register 2 (SCICR2)
Read/Write
Notes:
– During transmission, a “0” pulse on the TE bit
(“0” followed by “1”) sends a preamble (idle line)
after the current word.
Reset value: 0000 0000 (00h)
7
0
– When TE is set there is a 1 bit-time delay before
the transmission starts.
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
Caution: The TDO pin is free for general purpose
I/O only when the TE and RE bits are both cleared
(or if TE is never set).
Bit 7 = TIE Transmitter interrupt enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever
TDRE=1 in the SCISR register
Bit 2 = RE Receiver enable.
This bit enables the receiver. It is set and cleared
by software.
0: Receiver is disabled
1: Receiver is enabled and begins searching for a
start bit
Bit 6 = TCIE Transmission complete interrupt ena-
ble
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever TC=1 in
the SCISR register
Bit 1 = RWU Receiver wake-up.
This bit determines if the SCI is in mute mode or
not. It is set and cleared by software and can be
cleared by hardware when a wake-up sequence is
recognized.
0: Receiver in Active mode
1: Receiver in Mute mode
Bit 5 = RIE Receiver interrupt enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever OR=1
or RDRF=1 in the SCISR register
Note: Before selecting Mute mode (setting the
RWU bit), the SCI must receive some data first,
otherwise it cannot function in Mute mode with
wakeup by idle line detection.
Bit 4 = ILIE Idle line interrupt enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever IDLE=1
in the SCISR register.
Bit 0 = SBK Send break.
This bit set is used to send break characters. It is
set and cleared by software.
0: No break character is transmitted
1: Break characters are transmitted
Bit 3 = TE Transmitter enable.
This bit enables the transmitter. It is set and
cleared by software.
0: Transmitter is disabled
1: Transmitter is enabled
Note: If the SBK bit is set to “1” and then to “0”, the
transmitter will send a BREAK word at the end of
the current word.
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Serial communication interface (Cont’d)
Data Register (SCIDR)
Read/Write
PR prescaling factor
SCP1
SCP0
4
1
1
0
1
Reset value: Undefined
13
Contains the Received or Transmitted data char-
acter, depending on whether it is read from or writ-
ten to.
Bits 5:3 = SCT[2:0] SCI Transmitter rate divisor
These 3 bits, in conjunction with the SCP1 & SCP0
bits define the total division applied to the bus
clock to yield the transmit rate clock.
7
0
TR dividing factor
SCT2
SCT1
SCT0
DR7
DR6
DR5
DR4
DR3
DR2
DR1
DR0
1
2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
The Data register performs a double function (read
and write) since it is composed of two registers,
one for transmission (TDR) and one for reception
(RDR).
The TDR register provides the parallel interface
between the internal bus and the output shift reg-
ister (see Figure 38).
The RDR register provides the parallel interface
between the input shift register and the internal
bus (see Figure 38).
4
8
16
32
64
128
Bits 2:0 = SCR[2:0] SCI Receiver rate divisor.
These 3 bits, in conjunction with the SCP[1:0] bits
define the total division applied to the bus clock to
yield the receive rate clock.
Baud Rate Register (SCIBRR)
Read/Write
Reset value: 0000 0000 (00h)
RR dividing factor
SCR2
SCR1
SCR0
7
0
1
2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0
4
8
Bits 7:6= SCP[1:0] First SCI Prescaler
These 2 prescaling bits allow several standard
clock division ranges:
16
32
64
128
PR prescaling factor
SCP1
SCP0
1
3
0
0
0
1
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Table 21. SCI register map and reset values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
20
21
22
23
24
SCISR
TDRE
TC
1
RDRF
IDLE
0
OR
0
NF
0
FE
0
PE
0
Reset value
SCIDR
1
DR7
x
0
DR5
x
DR6
x
DR4
x
DR3
x
DR2
x
DR1
x
DR0
x
Reset value
SCIBRR
SCP1
SCP0
SCT2
SCT1
SCT0
SCR2
SCR1
SCR0
Reset value
SCICR1
0
R8
x
0
T8
x
x
SCID
0
x
M
x
x
WAKE
x
x
PCE
0
x
PS
0
x
PIE
0
Reset value
SCICR2
TIE
0
TCIE
0
RIE
0
ILIE
0
TE
0
RE
0
RWU
0
SBK
0
Reset value
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12.4 USB interface (USB)
12.4.1 Introduction
For general information on the USB, refer to the
“Universal Serial Bus Specifications” document
available at http//:www.usb.org.
The USB Interface implements a low-speed func-
tion interface between the USB and the ST7 mi-
crocontroller. It is a highly integrated circuit which
includes the transceiver, 3.3 voltage regulator, SIE
and DMA. No external components are needed
apart from the external pull-up on USBDM for low
speed recognition by the USB host. The use of
DMA architecture allows the endpoint definition to
be completely flexible. Endpoints can be config-
ured by software as in or out.
Serial interface engine
The SIE (serial interface engine) interfaces with
the USB, via the transceiver.
The SIE processes tokens, handles data transmis-
sion/reception, and handshaking as required by
the USB standard. It also performs frame format-
ting, including CRC generation and checking.
Endpoints
12.4.2 Main features
The Endpoint registers indicate if the microcontrol-
ler is ready to transmit/receive, and how many
bytes need to be transmitted.
■ USB Specification Version 1.1 Compliant
■ Supports Low-Speed USB Protocol
■ Two or Three Endpoints (including default one)
depending on the device (see device feature list
and register map)
DMA
When a token for a valid Endpoint is recognized by
the USB interface, the related data transfer takes
place, using DMA. At the end of the transaction, an
interrupt is generated.
■ CRC generation/checking, NRZI encoding/
decoding and bit-stuffing
■ USB Suspend/Resume operations
■ DMA Data transfers
Interrupts
By reading the Interrupt Status register, applica-
tion software can know which USB event has oc-
curred.
■ On-Chip 3.3V Regulator
■ On-Chip USB Transceiver
12.4.3 Functional description
The block diagram in Figure 41, gives an overview
of the USB interface hardware.
Figure 41. USB block diagram
6 MHz
ENDPOINT
CPU
REGISTERS
USBDM
Address,
Transceiver
SIE
DMA
USBDP
data buses
and interrupts
3.3V
INTERRUPT
REGISTERS
USBVCC
USBGND
Voltage
Regulator
MEMORY
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USB interface (Cont’d)
12.4.4 Register description
DMA address register (DMAR)
Read / Write
Interrupt/DMA register (IDR)
Read / Write
Reset value: xxxx 0000 (x0h)
Reset value: Undefined
7
0
7
0
DA7
DA6
EP1
EP0 CNT3 CNT2 CNT1 CNT0
DA15 DA14 DA13 DA12 DA11 DA10 DA9
DA8
Bits 7:6 = DA[7:6] DMA address bits 7-6.
Software must reset these bits. See the descrip-
tion of the DMAR register and Figure 42.
Bits 7:0=DA[15:8] DMA address bits 15-8.
Software must write the start address of the DMA
memory area whose most significant bits are given
by DA15-DA6. The remaining 6 address bits are
set by hardware. See the description of the IDR
register and Figure 42.
Bits 5:4 = EP[1:0] Endpoint number (read-only).
These bits identify the endpoint which required at-
tention.
00: Endpoint 0
01: Endpoint 1
10: Endpoint 2
When a CTR interrupt occurs (see register ISTR)
the software should read the EP bits to identify the
endpoint which has sent or received a packet.
Bits 3:0 = CNT[3:0] Byte count (read only).
This field shows how many data bytes have been
received during the last data reception.
Note: Not valid for data transmission.
Figure 42. DMA buffers
101111
Endpoint 2 TX
Endpoint 2 RX
101000
100111
100000
011111
Endpoint 1 TX
Endpoint 1 RX
011000
010111
010000
001111
Endpoint 0 TX
Endpoint 0 RX
001000
000111
DA15-6,000000
000000
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USB interface (Cont’d)
PID Register (PIDR)
Read only
INTERRUPT Status Register (ISTR)
Read / Write
Reset value: xx00 0000 (x0h)
Reset value: 0000 0000 (00h)
7
0
0
7
0
RX_
SEZ
SUSP DOVR CTR ERR IOVR ESUSP RESET SOF
TP3
TP2
0
0
0
RXD
When an interrupt occurs these bits are set by
hardware. Software must read them to determine
the interrupt type and clear them after servicing.
Note: These bits cannot be set by software.
Bits 7:6 = TP[3:2] Token PID bits 3 & 2.
USB token PIDs are encoded in four bits. TP[3:2]
correspond to the variable token PID bits 3 & 2.
Note: PID bits 1 & 0 have a fixed value of 01.
When a CTR interrupt occurs (see register ISTR)
the software should read the TP3 and TP2 bits to
retrieve the PID name of the token received.
The USB standard defines TP bits as:
Bit 7 = SUSP Suspend mode request.
This bit is set by hardware when a constant idle
state is present on the bus line for more than 3 ms,
indicating a suspend mode request from the USB
bus. The suspend request check is active immedi-
ately after each USB reset event and its disabled
by hardware when suspend mode is forced
(FSUSP bit of CTLR register) until the end of
resume sequence.
TP3
0
TP2
0
PID Name
OUT
1
0
IN
1
1
SETUP
Bits 5:3 Reserved. Forced by hardware to 0.
Bit 6 = DOVR DMA over/underrun.
This bit is set by hardware if the ST7 processor
can’t answer a DMA request in time.
0: No over/underrun detected
Bit 2 = RX_SEZ Received single-ended zero
This bit indicates the status of the RX_SEZ trans-
ceiver output.
0: No SE0 (single-ended zero) state
1: USB lines are in SE0 (single-ended zero) state
1: Over/underrun detected
Bit 5 = CTR Correct Transfer. This bit is set by
hardware when a correct transfer operation is per-
formed. The type of transfer can be determined by
looking at bits TP3-TP2 in register PIDR. The End-
point on which the transfer was made is identified
by bits EP1-EP0 in register IDR.
Bit 1 = RXD Received data
0: No K-state
1: USB lines are in K-state
This bit indicates the status of the RXD transceiver
output (differential receiver output).
0: No Correct Transfer detected
1: Correct Transfer detected
Note: If the environment is noisy, the RX_SEZ and
RXD bits can be used to secure the application. By
interpreting the status, software can distinguish a
valid End Suspend event from a spurious wake-up
due to noise on the external USB line. A valid End
Suspend is followed by a Resume or Reset se-
quence. A Resume is indicated by RXD=1, a Re-
set is indicated by RX_SEZ=1.
Note: A transfer where the device sent a NAK or
STALL handshake is considered not correct (the
host only sends ACK handshakes). A transfer is
considered correct if there are no errors in the PID
and CRC fields, if the DATA0/DATA1 PID is sent
as expected, if there were no data overruns, bit
stuffing or framing errors.
Bit 0 = Reserved. Forced by hardware to 0.
Bit 4 = ERR Error.
This bit is set by hardware whenever one of the er-
rors listed below has occurred:
0: No error detected
1: Timeout, CRC, bit stuffing or nonstandard
framing error detected
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USB interface (Cont’d)
Bit 3 = IOVR Interrupt overrun.
of each bit, please refer to the corresponding bit
description in ISTR.
This bit is set when hardware tries to set ERR, or
SOF before they have been cleared by software.
0: No overrun detected
Control Register (CTLR)
Read / Write
1: Overrun detected
Reset value: 0000 0110 (06h)
Bit 2 = ESUSP End suspend mode.
This bit is set by hardware when, during suspend
mode, activity is detected that wakes the USB in-
terface up from suspend mode.
7
0
0
0
0
0
RESUME
PDWN FSUSP FRES
This interrupt is serviced by a specific vector, in or-
der to wake up the ST7 from Halt mode.
0: No End Suspend detected
Bits 7:4 = Reserved. Forced by hardware to 0.
1: End Suspend detected
Bit 3 = RESUME Resume.
Bit 1 = RESET USB reset.
This bit is set by software to wake-up the Host
when the ST7 is in suspend mode.
0: Resume signal not forced
This bit is set by hardware when the USB reset se-
quence is detected on the bus.
0: No USB reset signal detected
1: USB reset signal detected
1: Resume signal forced on the USB bus.
Software should clear this bit after the appropriate
delay.
Note: The DADDR, EP0RA, EP0RB, EP1RA,
EP1RB, EP2RA and EP2RB registers are reset by
a USB reset.
Bit 2 = PDWN Power down.
This bit is set by software to turn off the 3.3V on-
chip voltage regulator that supplies the external
pull-up resistor and the transceiver.
0: Voltage regulator on
Bit 0 = SOF Start of frame.
This bit is set by hardware when a low-speed SOF
indication (keep-alive strobe) is seen on the USB
bus. It is also issued at the end of a resume se-
quence.
0: No SOF signal detected
1: SOF signal detected
1: Voltage regulator off
Note: After turning on the voltage regulator, soft-
ware should allow at least 3 µs for stabilisation of
the power supply before using the USB interface.
Note: To avoid spurious clearing of some bits, it is
recommended to clear them using a load instruc-
tion where all bits which must not be altered are
set, and all bits to be cleared are reset. Avoid read-
modify-write instructions like AND , XOR..
Bit 1 = FSUSP Force suspend mode.
This bit is set by software to enter Suspend mode.
The ST7 should also be halted allowing at least
600 ns before issuing the HALT instruction.
0: Suspend mode inactive
Interrupt Mask Register (IMR)
Read / Write
1: Suspend mode active
When the hardware detects USB activity, it resets
this bit (it can also be reset by software).
Reset value: 0000 0000 (00h)
7
0
Bit 0 = FRES Force reset.
This bit is set by software to force a reset of the
USB interface, just as if a RESET sequence came
from the USB.
SUS
PM
DOV
RM
CTR
M
ERR IOVR ESU
SPM
RES
ETM
SOF
M
M
M
0: Reset not forced
1: USB interface reset forced.
Bits 7:0 = These bits are mask bits for all interrupt
condition bits included in the ISTR. Whenever one
of the IMR bits is set, if the corresponding ISTR bit
is set, and the I bit in the CC register is cleared, an
interrupt request is generated. For an explanation
The USB is held in RESET state until software
clears this bit, at which point a “USB-RESET” in-
terrupt will be generated if enabled.
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USB interface (Cont’d)
Device Address Register (DADDR)
Read / Write
Bit 6 = DTOG_TX Data Toggle, for transmission
transfers.
It contains the required value of the toggle bit
(0=DATA0, 1=DATA1) for the next transmitted
data packet. This bit is set by hardware at the re-
ception of a SETUP PID. DTOG_TX toggles only
when the transmitter has received the ACK signal
from the USB host. DTOG_TX and also
DTOG_RX (see EPnRB) are normally updated by
hardware, at the receipt of a relevant PID. They
can be also written by software.
Reset value: 0000 0000 (00h)
7
0
0
ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0
Bit 7 = Reserved. Forced by hardware to 0.
Bits 6:0 = ADD[6:0] Device address, 7 bits.
Bits 5:4 = STAT_TX[1:0] Status bits, for transmis-
sion transfers.
These bits contain the information about the end-
point status, which are listed below:
Software must write into this register the address
sent by the host during enumeration.
Note: This register is also reset when a USB reset
is received from the USB bus or forced through bit
FRES in the CTLR register.
STAT_TX1 STAT_TX0 Meaning
DISABLED: transmission
transfers cannot be executed.
0
0
STALL: the endpoint is stalled
and all transmission requests
result in a STALL handshake.
Endpoint n Register A (EPnRA)
Read / Write
0
1
Reset value: 0000 xxxx (0xh)
NAK: the endpoint is naked
and all transmission requests
result in a NAK handshake.
1
1
0
1
7
0
VALID: this endpoint is ena-
bled for transmission.
ST_
OUT
DTOG
_TX
STAT STAT TBC TBC TBC TBC
_TX1
_TX0
3
2
1
0
These bits are written by software. Hardware sets
the STAT_TX bits to NAK when a correct transfer
has occurred (CTR=1) related to a IN or SETUP
transaction addressed to this endpoint; this allows
the software to prepare the next set of data to be
transmitted.
These registers (EP0RA, EP1RA and EP2RA) are
used for controlling data transmission. They are
also reset by the USB bus reset.
Note: Endpoint 2 and the EP2RA register are not
available on some devices (see device feature list
and register map).
Bits 3:0 = TBC[3:0] Transmit byte count for End-
point n.
Before transmission, after filling the transmit buff-
er, software must write in the TBC field the trans-
mit packet size expressed in bytes (in the range 0-
8).
Bit 7 = ST_OUT Status out.
This bit is set by software to indicate that a status
out packet is expected: in this case, all nonzero
OUT data transfers on the endpoint are STALLed
instead of being ACKed. When ST_OUT is reset,
OUT transactions can have any number of bytes,
as needed.
Warning: Any value outside the range 0-8 will-
induce undesired effects (such as continuous data
transmission).
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USB INTERFACE (Cont’d)
Endpoint n Register B (EPnRB)
Read / Write
STAT_RX1 STAT_RX0 Meaning
NAK: the endpoint is na-
ked and all reception re-
quests result in a NAK
handshake.
VALID: this endpoint is
enabled for reception.
Reset value: 0000 xxxx (0xh)
1
1
0
1
7
0
DTOG
_RX
STAT
_RX1
STAT
_RX0
CTRL
EA3 EA2 EA1 EA0
These bits are written by software. Hardware sets
the STAT_RX bits to NAK when a correct transfer
has occurred (CTR=1) related to an OUT or SET-
UP transaction addressed to this endpoint, so the
software has the time to elaborate the received
data before acknowledging a new transaction.
These registers (EP1RB and EP2RB) are used for
controlling data reception on Endpoints 1 and 2.
They are also reset by the USB bus reset.
Note: Endpoint 2 and the EP2RB register are not
available on some devices (see device feature list
and register map).
Bits 3:0 = EA[3:0] Endpoint address.
Software must write in this field the 4-bit address
used to identify the transactions directed to this
endpoint. Usually EP1RB contains “0001” and
EP2RB contains “0010”.
Bit 7 = CTRL Control.
This bit should be 0.
Note: If this bit is 1, the Endpoint is a control end-
point. (Endpoint 0 is always a control Endpoint, but
it is possible to have more than one control End-
point).
Endpoint 0 Register B (EP0RB)
Read / Write
Reset value: 1000 0000 (80h)
Bit 6 = DTOG_RX Data toggle, for reception trans-
fers.
7
1
0
0
It contains the expected value of the toggle bit
(0=DATA0, 1=DATA1) for the next data packet.
This bit is cleared by hardware in the first stage
(Setup Stage) of a control transfer (SETUP trans-
actions start always with DATA0 PID). The receiv-
er toggles DTOG_RX only if it receives a correct
data packet and the packet’s data PID matches
the receiver sequence bit.
DTOG STAT STAT
RX RX1 RX0
0
0
0
This register is used for controlling data reception
on Endpoint 0. It is also reset by the USB bus re-
set.
Bit 7 = Forced by hardware to 1.
Bits 5:4 = STAT_RX [1:0] Status bits, for reception
transfers.
These bits contain the information about the end-
point status, which are listed below:
Bits 6:4 = Refer to the EPnRB register for a de-
scription of these bits.
STAT_RX1 STAT_RX0 Meaning
DISABLED: reception
transfers cannot be exe-
cuted.
Bits 3:0 = Forced by hardware to 0.
0
0
0
1
STALL: the endpoint is
stalled and all reception
requests result in
STALL handshake.
a
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USB interface (Cont’d)
12.4.5 Programming considerations
tively) must not be modified by software, as the
hardware can change their value on the fly.
The interaction between the USB interface and the
application program is described below. Apart
from system reset, action is always initiated by the
USB interface, driven by one of the USB events
associated with the Interrupt Status Register (IS-
TR) bits.
When the operation is completed, they can be ac-
cessed again to enable a new operation.
12.4.5.4 Interrupt handling
Start of Frame (SOF)
The interrupt service routine may monitor the SOF
events for a 1 ms synchronization event to the
USB bus. This interrupt is generated at the end of
a resume sequence and can also be used to de-
tect this event.
12.4.5.1 Initializing the registers
At system reset, the software must initialize all reg-
isters to enable the USB interface to properly gen-
erate interrupts and DMA requests.
1. Initialize the DMAR, IDR, and IMR registers
(choice of enabled interrupts, address of DMA
buffers). Refer the paragraph titled initializing
the DMA Buffers.
USB Reset (RESET)
When this event occurs, the DADDR register is re-
set, and communication is disabled in all endpoint
registers (the USB interface will not respond to any
packet). Software is responsible for reenabling
endpoint 0 within 10 ms of the end of reset. To do
this, set the STAT_RX bits in the EP0RB register
to VALID.
2. Initialize the EP0RA and EP0RB registers to
enable accesses to address 0 and endpoint 0
to support USB enumeration. Refer to the para-
graph titled Endpoint Initialization.
3. When addresses are received through this
channel, update the content of the DADDR.
Suspend (SUSP)
The CPU is warned about the lack of bus activity
for more than 3 ms, which is a suspend request.
The software should set the USB interface to sus-
pend mode and execute an ST7 HALT instruction
to meet the USB-specified power constraints.
4. If needed, write the endpoint numbers in the EA
fields in the EP1RB and EP2RB register.
12.4.5.2 Initializing DMA buffers
The DMA buffers are a contiguous zone of memo-
ry whose maximum size is 48 bytes. They can be
placed anywhere in the memory space to enable
the reception of messages. The 10 most signifi-
cant bits of the start of this memory area are spec-
ified by bits DA15-DA6 in registers DMAR and
IDR, the remaining bits are 0. The memory map is
shown in Figure 42.
End Suspend (ESUSP)
The CPU is alerted by activity on the USB, which
causes an ESUSP interrupt. The ST7 automatical-
ly terminates Halt mode.
Correct Transfer (CTR)
1. When this event occurs, the hardware automat-
ically sets the STAT_TX or STAT_RX to NAK.
Note: Every valid endpoint is NAKed until soft-
ware clears the CTR bit in the ISTR register,
independently of the endpoint number
addressed by the transfer which generated the
CTR interrupt.
Each buffer is filled starting from the bottom (last 3
address bits=000) up.
12.4.5.3 Endpoint initialization
To be ready to receive:
Set STAT_RX to VALID (11b) in EP0RB to enable
reception.
Note: If the event triggering the CTR interrupt is
a SETUP transaction, both STAT_TX and
STAT_RX are set to NAK.
To be ready to transmit:
1. Write the data in the DMA transmit buffer.
2. Read the PIDR to obtain the token and the IDR
to get the endpoint number related to the last
transfer.
2. In register EPnRA, specify the number of bytes
to be transmitted in the TBC field
Note: When a CTR interrupt occurs, the TP3-
TP2 bits in the PIDR register and EP1-EP0 bits
in the IDR register stay unchanged until the
CTR bit in the ISTR register is cleared.
3. Enable the endpoint by setting the STAT_TX
bits to VALID (11b) in EPnRA.
Note: Once transmission and/or reception are en-
abled, registers EPnRA and/or EPnRB (respec-
3. Clear the CTR bit in the ISTR register.
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USB interface (Cont’d)
Table 22. USB register map and reset values
Address
(Hex.)
Register
Name
7
6
5
4
3
2
1
0
PIDR
TP3
TP2
0
0
0
RX_SEZ
RXD
0
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
Reset value
DMAR
x
x
0
0
0
DA11
x
0
DA10
x
0
DA9
x
0
DA15
DA14
DA13
DA12
DA8
Reset value
IDR
x
x
x
x
x
DA7
DA6
EP1
EP0
CNT3
0
CNT2
0
CNT1
0
CNT0
Reset value
ISTR
x
x
x
x
0
SUSP
DOVR
CTR
ERR
IOVR
0
ESUSP
0
RESET
0
SOF
Reset value
IMR
0
0
0
0
0
SUSPM
DOVRM
CTRM
ERRM
IOVRM ESUSPM RESETM
SOFM
Reset value
CTLR
0
0
0
0
0
0
0
0
0
0
0
0
0
RESUME PDWN
FSUSP
FRES
Reset value
DADDR
0
0
ADD6
0
0
ADD5
0
0
1
1
0
0
ADD4
0
ADD3
ADD2
ADD1
ADD0
Reset value
EP0RA
0
0
0
0
0
ST_OUT
STAT_TX1 STAT_TX0
TBC3
TBC2
TBC1
TBC0
DTOG_TX
0
Reset value
EP0RB
0
1
1
0
0
x
x
x
x
DTOG_RX STAT_RX1 STAT_RX0
0
0
0
0
0
0
0
0
Reset value
EP1RA
0
0
0
ST_OUT DTOG_TX STAT_TX1 STAT_TX0
TBC3
x
TBC2
x
TBC1
x
TBC0
x
Reset value
EP1RB
0
CTRL
0
0
0
0
DTOG_RX STAT_RX1 STAT_RX0
EA3
x
EA2
x
EA1
x
EA0
x
Reset value
EP2RA
0
0
0
ST_OUT DTOG_TX STAT_TX1 STAT_TX0
TBC3
x
TBC2
x
TBC1
x
TBC0
x
Reset value
EP2RB
0
CTRL
0
0
0
0
DTOG_RX STAT_RX1 STAT_RX0
EA3
x
EA2
x
EA1
x
EA0
x
Reset value
0
0
0
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12.5 I²C bus interface (I²C)
12.5.1 Introduction
handshake. The interrupts are enabled or disabled
by software. The interface is connected to the I²C
bus by a data pin (SDAI) and by a clock pin (SCLI).
It can be connected both with a standard I²C bus
and a Fast I²C bus. This selection is made by soft-
ware.
The I²C Bus Interface serves as an interface be-
tween the microcontroller and the serial I²C bus. It
provides both multimaster and slave functions,
and controls all I²C bus-specific sequencing, pro-
tocol, arbitration and timing. It supports fast I²C
mode (400 kHz).
Mode selection
12.5.2 Main features
The interface can operate in the four following
modes:
■ Parallel-bus/I²C protocol converter
■ Multi-master capability
■ 7-bit Addressing
■ Transmitter/Receiver flag
■ End-of-byte transmission flag
■ Transfer problem detection
I²C master features:
– Slave transmitter/receiver
– Master transmitter/receiver
By default, it operates in slave mode.
The interface automatically switches from slave to
master after it generates a START condition and
from master to slave in case of arbitration loss or a
STOP generation, allowing then Multi-Master ca-
pability.
■ Clock generation
■ I²C bus busy flag
■ Arbitration Lost flag
Communication flow
In Master mode, it initiates a data transfer and
generates the clock signal. A serial data transfer
always begins with a start condition and ends with
a stop condition. Both start and stop conditions are
generated in master mode by software.
■ End of byte transmission flag
■ Transmitter/Receiver flag
■ Start bit detection flag
■ Start and Stop generation
I²C slave features:
In Slave mode, the interface is capable of recog-
nising its own address (7-bit), and the General Call
address. The General Call address detection may
be enabled or disabled by software.
■ Stop bit detection
■ I²C bus busy flag
Data and addresses are transferred as 8-bit bytes,
MSB first. The first byte following the start condi-
tion is the address byte; it is always transmitted in
Master mode.
■ Detection of misplaced start or stop condition
■ Programmable I²C Address detection
■ Transfer problem detection
■ End-of-byte transmission flag
■ Transmitter/Receiver flag
12.5.3 General description
A 9th clock pulse follows the 8 clock cycles of a
byte transfer, during which the receiver must send
an acknowledge bit to the transmitter. Refer to Fig-
ure 43.
In addition to receiving and transmitting data, this
interface converts it from serial to parallel format
and vice versa, using either an interrupt or polled
Figure 43. I²C bus protocol
SDA
MSB
ACK
SCL
1
2
8
9
START
STOP
CONDITION
CONDITION
VR02119B
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I²C bus interface (Cont’d)
Acknowledge may be enabled and disabled by
software.
The SCL frequency (F
grammable clock divider which depends on the I²C
bus mode.
) is controlled by a pro-
SCL
The I²C interface address and/or general call ad-
dress can be selected by software.
When the I²C cell is enabled, the SDA and SCL
ports must be configured as floating inputs. In this
case, the value of the external pull-up resistor
used depends on the application.
The speed of the I²C interface may be selected be-
tween Standard (up to 100kHz) and Fast I²C (up to
400kHz).
When the I²C cell is disabled, the SDA and SCL
ports revert to being standard I/O port pins.
SDA/SCL Line Control
Transmitter mode: the interface holds the clock
line low before transmission to wait for the micro-
controller to write the byte in the Data Register.
Receiver mode: the interface holds the clock line
low after reception to wait for the microcontroller to
read the byte in the Data Register.
Figure 44. I²C Interface block diagram
DATA REGISTER (DR)
DATA SHIFT REGISTER
DATA CONTROL
SDA or SDAI
COMPARATOR
OWN ADDRESS REGISTER (OAR)
CLOCK CONTROL
SCL or SCLI
CLOCK CONTROL REGISTER (CCR)
CONTROL REGISTER (CR)
STATUS REGISTER 1 (SR1)
STATUS REGISTER 2 (SR2)
CONTROL LOGIC
INTERRUPT
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I²C bus interface (Cont’d)
12.5.4 Functional description
The slave waits for a read of the SR1 register fol-
lowed by a write in the DR register, holding the
SCL line low (see Figure 45 Transfer sequencing
EV3).
Refer to the CR, SR1 and SR2 registers in Section
12.5.7. for the bit definitions.
By default the I²C interface operates in Slave
mode (M/SL bit is cleared) except when it initiates
a transmit or receive sequence.
When the acknowledge pulse is received:
– The EVF and BTF bits are set by hardware with
an interrupt if the ITE bit is set.
12.5.4.1 Slave mode
Closing slave communication
As soon as a start condition is detected, the
address is received from the SDA line and sent to
the shift register; then it is compared with the
address of the interface or the General Call
address (if selected by software).
After the last data byte is transferred a Stop Con-
dition is generated by the master. The interface
detects this condition and sets:
– EVF and STOPF bits with an interrupt if the ITE
bit is set.
Address not matched: the interface ignores it
and waits for another Start condition.
Then the interface waits for a read of the SR2 reg-
ister (see Figure 45 Transfer sequencing EV4).
Address matched: the interface generates in se-
quence:
– Acknowledge pulse if the ACK bit is set.
Error cases
– EVF and ADSL bits are set with an interrupt if the
ITE bit is set.
– BERR: Detection of a Stop or a Start condition
during a byte transfer. In this case, the EVF and
the BERR bits are set with an interrupt if the ITE
bit is set.
If it is a Stop, then the interface discards the data,
released the lines and waits for another Start
condition.
Then the interface waits for a read of the SR1 reg-
ister, holding the SCL line low (see Figure 45
Transfer sequencing EV1).
Next, software must read the DR register to deter-
mine from the least significant bit (Data Direction
Bit) if the slave must enter Receiver or Transmitter
mode.
If it is a Start, then the interface discards the data
and waits for the next slave address on the bus.
– AF: Detection of a non-acknowledge bit. In this
case, the EVF and AF bits are set with an inter-
rupt if the ITE bit is set.
Slave receiver
The AF bit is cleared by reading the I2CSR2 reg-
ister. However, if read before the completion of
the transmission, the AF flag will be set again,
thus possibly generating a new interrupt. Soft-
ware must ensure either that the SCL line is back
at 0 before reading the SR2 register, or be able
to correctly handle a second interrupt during the
9th pulse of a transmitted byte.
Following the address reception and after SR1
register has been read, the slave receives bytes
from the SDA line into the DR register via the inter-
nal shift register. After each byte the interface gen-
erates in sequence:
– Acknowledge pulse if the ACK bit is set
– EVF and BTF bits are set with an interrupt if the
ITE bit is set.
Note: In case of errors, SCL line is not held low;
however, the SDA line can remain low if the last
bits transmitted are all 0. While AF=1, the SCL line
may be held low due to SB or BTF flags that are
set at the same time. It is then necessary to re-
lease both lines by software.
Then the interface waits for a read of the SR1 reg-
ister followed by a read of the DR register, holding
the SCL line low (see Figure 45 Transfer se-
quencing EV2).
Slave transmitter
How to release the SDA / SCL lines
Following the address reception and after the SR1
register has been read, the slave sends bytes from
the DR register to the SDA line via the internal shift
Set and subsequently clear the STOP bit while
BTF is set. The SDA/SCL lines are released after
the transfer of the current byte.
register.
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I²C bus interface (Cont’d)
12.5.4.2 Master mode
automatically back to slave mode (M/SL bit
cleared).
To switch from default Slave mode to Master
mode, a Start condition generation is needed.
Note: In order to generate the non-acknowledge
pulse after the last received data byte, the ACK bit
must be cleared just before reading the second
last data byte.
Start condition
Setting the START bit while the BUSY bit is
cleared causes the interface to switch to Master
mode (M/SL bit set) and generates a Start condi-
tion.
Master transmitter
Following the address transmission and after SR1
register has been read, the master sends bytes
from the DR register to the SDA line via the inter-
nal shift register.
Once the Start condition is sent:
– The EVF and SB bits are set by hardware with
an interrupt if the ITE bit is set.
The master waits for a read of the SR1 register fol-
lowed by a write in the DR register, holding the
SCL line low (see Figure 45 Transfer sequencing
EV8).
Then the master waits for a read of the SR1 regis-
ter followed by a write in the DR register with the
Slave address byte, holding the SCL line low
(see Figure 45 Transfer sequencing EV5).
When the acknowledge bit is received, the
interface sets:
Slave address transmission
– EVF and BTF bits with an interrupt if the ITE bit
is set.
Then the slave address byte is sent to the SDA
line via the internal shift register.
To close the communication: after writing the last
byte to the DR register, set the STOP bit to gener-
ate the Stop condition. The interface goes auto-
matically back to slave mode (M/SL bit cleared).
After completion of this transfer (and acknowledge
from the slave if the ACK bit is set):
– The EVF bit is set by hardware with interrupt
generation if the ITE bit is set.
Error cases
Then the master waits for a read of the SR1 regis-
ter followed by a write in the CR register (for exam-
ple set PE bit), holding the SCL line low (see Fig-
ure 45 Transfer sequencing EV6).
– BERR: Detection of a Stop or a Start condition
during a byte transfer. In this case, the EVF and
BERR bits are set by hardware with an interrupt
if ITE is set.
Note that BERR will not be set if an error is de-
tected during the first or second pulse of each 9-
bit transaction:
Next the master must enter Receiver or Transmit-
ter mode.
Master receiver
Single Master mode
If a Start or Stop is issued during the first or sec-
ond pulse of a 9-bit transaction, the BERR flag
will not be set and transfer will continue however
the BUSY flag will be reset. To work around this,
slave devices should issue a NACK when they
receive a misplaced Start or Stop. The reception
of a NACK or BUSY by the master in the middle
of communication gives the possibility to reiniti-
ate transmission.
Following the address transmission and after the
SR1 and CR registers have been accessed, the
master receives bytes from the SDA line into the
DR register via the internal shift register. After
each byte the interface generates in sequence:
– Acknowledge pulse if the ACK bit is set
– EVF and BTF bits are set by hardware with an in-
terrupt if the ITE bit is set.
Multimaster mode
Then the interface waits for a read of the SR1 reg-
ister followed by a read of the DR register, holding
the SCL line low (see Figure 45 Transfer se-
quencing EV7).
Normally the BERR bit would be set whenever
unauthorized transmission takes place while
transfer is already in progress. However, an is-
sue will arise if an external master generates an
unauthorized Start or Stop while the I C master
is on the first or second pulse of a 9-bit transac-
tion. It is possible to work around this by polling
2
To close the communication: before reading the
last byte from the DR register, set the STOP bit to
generate the Stop condition. The interface goes
2
the BUSY bit during I C master mode transmis-
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sion. The resetting of the BUSY bit can then be
handled in a similar manner as the BERR flag
being set.
to correctly handle a second interrupt during the
9th pulse of a transmitted byte.
– ARLO: Detection of an arbitration lost condition.
In this case the ARLO bit is set by hardware (with
an interrupt if the ITE bit is set and the interface
goes automatically back to slave mode (the M/SL
bit is cleared).
– AF: Detection of a non-acknowledge bit. In this
case, the EVF and AF bits are set by hardware
with an interrupt if the ITE bit is set. To resume,
set the START or STOP bit.
The AF bit is cleared by reading the I2CSR2 reg-
ister. However, if read before the completion of
the transmission, the AF flag will be set again,
thus possibly generating a new interrupt. Soft-
ware must ensure either that the SCL line is back
at 0 before reading the SR2 register, or be able
Note: In all these cases, the SCL line is not held
low; however, the SDA line can remain low if the
last bits transmitted are all 0. While AF=1, the SCL
line may be held low due to SB or BTF flags that
are set at the same time. It is then necessary to re-
lease both lines by software.
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I²C bus interface (Cont’d)
Figure 45. Transfer sequencing
Slave Receiver
S
Address
A
Data1
A
Data2
EV3
A
DataN
A
P
.....
EV1
EV2
A
EV2
A
EV2
NA
EV4
Slave Transmitter
S
Address
A
Data1
Data2
DataN
P
.....
.....
EV1 EV3
EV3
EV3-1
EV4
Master Receiver
S
Address
A
Data1
A
Data2
A
DataN NA
P
EV5
EV6
EV7
A
EV7
A
EV7
A
Master Transmitter
S
Address
A
Data1
Data2
DataN
P
.....
EV5
EV6 EV8
EV8
EV8
EV8
Legend:
S=Start, P=Stop, A=Acknowledge, NA=Non-acknowledge
EVx=Event (with interrupt if ITE=1)
EV1: EVF=1, ADSL=1, cleared by reading the SR1 register.
EV2: EVF=1, BTF=1, cleared by reading the SR1 register followed by reading the DR register.
EV3: EVF=1, BTF=1, cleared by reading the SR1 register followed by writing the DR register.
EV3-1: EVF=1, AF=1, BTF=1; AF is cleared by reading the SR1 register. The BTF is cleared
by releasing the lines (STOP=1, STOP=0) or by writing the DR register (DR=FFh).
Note: If lines are released by STOP=1, STOP=0, the subsequent EV4 is not seen.
EV4: EVF=1, STOPF=1, cleared by reading the SR2 register.
EV5: EVF=1, SB=1, cleared by reading the SR1 register followed by writing the DR register.
EV6: EVF=1, cleared by reading the SR1 register followed by writing the CR register
(for example PE=1).
EV7: EVF=1, BTF=1, cleared by reading the SR1 register followed by reading the DR register.
EV8: EVF=1, BTF=1, cleared by reading the SR1 register followed by writing the DR register.
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I²C bus interface (Cont’d)
12.5.5 Low power modes
Mode
Description
No effect on I²C interface.
Wait
I²C interrupts cause the device to exit from Wait mode.
I²C registers are frozen.
In Halt mode, the I²C interface is inactive and does not acknowledge data on the bus. The I²C
interface resumes operation when the MCU is woken up by an interrupt with “exit from Halt
mode” capability.
Halt
12.5.6 Interrupts
Figure 46. Event flags and interrupt generation
BTF
ADSL
SB
ITE
AF
INTERRUPT
EVF
STOPF
ARLO
BERR
*
* EVF can also be set by EV6 or an error from the SR2 register.
Enable
control from
bit
Exit
Exit
from
Halt
Event
flag
Interrupt event
Wait
Yes
Yes
Yes
Yes
Yes
Yes
Yes
End of byte Transfer event
BTF
ADSL
SB
No
No
No
No
No
No
No
Address Matched event (Slave mode)
Start Bit Generation event (Master mode)
Acknowledge Failure event
AF
ITE
Stop Detection event (Slave mode)
Arbitration Lost event (Multimaster configuration)
Bus Error event
STOPF
ARLO
BERR
The I²C interrupt events are connected to the
same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding
Enable Control Bit is set and the I-bit in the CC
register is reset (RIM instruction).
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I²C bus interface (Cont’d)
12.5.7 Register description
– In slave mode:
0: No start generation
1: Start generation when the bus is free
I²C Control Register (CR)
Read / Write
Reset value: 0000 0000 (00h)
Bit 2 = ACK Acknowledge enable.
This bit is set and cleared by software. It is also
cleared by hardware when the interface is disa-
7
0
bled (PE=0).
0
0
PE
ENGC START ACK STOP
ITE
0: No acknowledge returned
1: Acknowledge returned after an address byte or
a data byte is received
Bits 7:6 = Reserved. Forced to 0 by hardware.
Bit 1 = STOP Generation of a Stop condition.
This bit is set and cleared by software. It is also
cleared by hardware in master mode. Note: This
bit is not cleared when the interface is disabled
(PE=0).
Bit 5 = PE Peripheral enable.
This bit is set and cleared by software.
0: Peripheral disabled
1: Master/Slave capability
Notes:
– When PE=0, all the bits of the CR register and
the SR register except the Stop bit are reset. All
outputs are released while PE=0
– When PE=1, the corresponding I/O pins are se-
lected by hardware as alternate functions.
– To enable the I²C interface, write the CR register
TWICE with PE=1 as the first write only activates
the interface (only PE is set).
– In Master mode:
0: No stop generation
1: Stop generation after the current byte transfer
or after the current Start condition is sent. The
STOP bit is cleared by hardware when the Stop
condition is sent.
– In Slave mode:
0: No stop generation
1: Release the SCL and SDA lines after the cur-
rent byte transfer (BTF=1). In this mode the
STOP bit has to be cleared by software.
Bit 4 = ENGC Enable General Call.
This bit is set and cleared by software. It is also
cleared by hardware when the interface is disa-
bled (PE=0). The 00h General Call address is ac-
knowledged (01h ignored).
0: General Call disabled
1: General Call enabled
Bit 0 = ITE Interrupt enable.
This bit is set and cleared by software and cleared
by hardware when the interface is disabled
(PE=0).
0: Interrupts disabled
1: Interrupts enabled
Note: In accordance with the I2C standard, when
GCAL addressing is enabled, an I2C slave can
only receive data. It will not transmit data to the
master.
Refer to Figure 46 for the relationship between the
events and the interrupt.
SCL is held low when the SB, BTF or ADSL flags
or an EV6 event (See Figure 45) is detected.
Bit 3 = START Generation of a Start condition.
This bit is set and cleared by software. It is also
cleared by hardware when the interface is disa-
bled (PE=0) or when the Start condition is sent
(with interrupt generation if ITE=1).
– In master mode:
0: No start generation
1: Repeated start generation
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I²C bus interface (Cont’d)
I²C Status Register 1 (SR1)
Read Only
Note:
– The BUSY flag is NOT updated when the inter-
face is disabled (PE=0). This can have conse-
quences when operating in Multimaster mode;
i.e. a second active I C master commencing a
transfer with an unset BUSY bit can cause a con-
flict resulting in lost data. A software workaround
Reset value: 0000 0000 (00h)
2
7
0
EVF
0
TRA BUSY BTF ADSL M/SL
SB
2
consists of checking that the I C is not busy be-
fore enabling the I C Multimaster cell.
2
Bit 7 = EVF Event flag.
This bit is set by hardware as soon as an event oc-
curs. It is cleared by software reading SR2 register
in case of error event or as described in Figure 45.
It is also cleared by hardware when the interface is
disabled (PE=0).
0: No event
1: One of the following events has occurred:
Bit 3 = BTF Byte transfer finished.
This bit is set by hardware as soon as a byte is cor-
rectly received or transmitted with interrupt gener-
ation if ITE=1. It is cleared by software reading
SR1 register followed by a read or write of DR reg-
ister. It is also cleared by hardware when the inter-
face is disabled (PE=0).
– BTF=1 (byte received or transmitted)
– Following a byte transmission, this bit is set after
reception of the acknowledge clock pulse. In
case an address byte is sent, this bit is set only
after the EV6 event (See Figure 45). BTF is
cleared by reading SR1 register followed by writ-
ing the next byte in DR register.
– ADSL=1 (Address matched in Slave mode
while ACK=1)
– SB=1 (Start condition generated in Master
mode)
– AF=1 (No acknowledge received after byte
transmission)
– Following a byte reception, this bit is set after
transmission of the acknowledge clock pulse if
ACK=1. BTF is cleared by reading SR1 register
followed by reading the byte from DR register.
– STOPF=1 (Stop condition detected in Slave
mode)
– ARLO=1 (Arbitration lost in Master mode)
The SCL line is held low while BTF=1.
– BERR=1 (Bus error, misplaced Start or Stop
condition detected)
0: byte transfer not done
1: byte transfer succeeded
– Address byte successfully transmitted in Mas-
ter mode.
Bit 2 = ADSL Address matched (Slave mode).
This bit is set by hardware as soon as the received
slave address matched with the OAR register con-
tent or a general call is recognized. An interrupt is
generated if ITE=1. It is cleared by software read-
ing SR1 register or by hardware when the inter-
face is disabled (PE=0).
Bit 6 = Reserved. Forced to 0 by hardware.
Bit 5 = TRA Transmitter/Receiver.
When BTF is set, TRA=1 if a data byte has been
transmitted. It is cleared automatically when BTF
is cleared. It is also cleared by hardware after de-
tection of Stop condition (STOPF=1), loss of bus
arbitration (ARLO=1) or when the interface is disa-
bled (PE=0).
The SCL line is held low while ADSL=1.
0: Address mismatched or not received
1: Received address matched
0: Data byte received (if BTF=1)
1: Data byte transmitted
Bit 1 = M/SL Master/Slave.
This bit is set by hardware as soon as the interface
is in Master mode (writing START=1). It is cleared
by hardware after detecting a Stop condition on
the bus or a loss of arbitration (ARLO=1). It is also
cleared when the interface is disabled (PE=0).
0: Slave mode
Bit 4 = BUSY Bus busy.
This bit is set by hardware on detection of a Start
condition and cleared by hardware on detection of
a Stop condition. It indicates a communication in
progress on the bus. The BUSY flag of the I2CSR1
register is cleared if a Bus Error occurs.
0: No communication on the bus
1: Master mode
1: Communication ongoing on the bus
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Bit 0 = SB Start bit (Master mode).
This bit is set by hardware as soon as the Start
es the arbitration of the bus to another master. An
interrupt is generated if ITE=1. It is cleared by soft-
condition is generated (following
a
write
ware reading SR2 register or by hardware when
the interface is disabled (PE=0).
START=1). An interrupt is generated if ITE=1. It is
cleared by software reading SR1 register followed
by writing the address byte in DR register. It is also
cleared by hardware when the interface is disa-
bled (PE=0).
After an ARLO event the interface switches back
automatically to Slave mode (M/SL=0).
The SCL line is not held low while ARLO=1.
0: No Start condition
1: Start condition generated
0: No arbitration lost detected
1: Arbitration lost detected
Note:
– In a Multimaster environment, when the interface
is configured in Master Receive mode it does not
perform arbitration during the reception of the
Acknowledge Bit. Mishandling of the ARLO bit
from the I2CSR2 register may occur when a sec-
ond master simultaneously requests the same
data from the same slave and the I C master
does not acknowledge the data. The ARLO bit is
then left at 0 instead of being set.
I²C Status Register 2 (SR2)
Read Only
Reset value: 0000 0000 (00h)
7
0
0
2
0
0
AF STOPF ARLO BERR GCAL
Bit 1 = BERR Bus error.
Bits 7:5 = Reserved. Forced to 0 by hardware.
This bit is set by hardware when the interface de-
tects a misplaced Start or Stop condition. An inter-
rupt is generated if ITE=1. It is cleared by software
reading SR2 register or by hardware when the in-
terface is disabled (PE=0).
Bit 4 = AF Acknowledge failure.
This bit is set by hardware when no acknowledge
is returned. An interrupt is generated if ITE=1. It is
cleared by software reading SR2 register or by
hardware when the interface is disabled (PE=0).
The SCL line is not held low while BERR=1.
0: No misplaced Start or Stop condition
1: Misplaced Start or Stop condition
Note:
– If a Bus Error occurs, a Stop or a repeated Start
condition should be generated by the Master to
re-synchronize communication, get the transmis-
sion acknowledged and the bus released for fur-
ther communication
Note: While AF=1, the SCL line may be held low
due to SB or BTF flags that are set at the same
time. It is then necessary to release both lines by
software.
0: No acknowledge failure
1: Acknowledge failure
Bit 3 = STOPF Stop detection (Slave mode).
This bit is set by hardware when a Stop condition
is detected on the bus after an acknowledge (if
ACK=1). An interrupt is generated if ITE=1. It is
cleared by software reading SR2 register or by
hardware when the interface is disabled (PE=0).
Bit 0 = GCAL General Call (Slave mode).
This bit is set by hardware when a general call ad-
dress is detected on the bus while ENGC=1. It is
cleared by hardware detecting a Stop condition
(STOPF=1) or when the interface is disabled
(PE=0).
The SCL line is not held low while STOPF=1.
0: No general call address detected on bus
1: general call address detected on bus
0: No Stop condition detected
1: Stop condition detected
Bit 2 = ARLO Arbitration lost.
This bit is set by hardware when the interface los-
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I²C bus interface (Cont’d)
I²C Clock Control Register (CCR)
Bits 7:0 = D[7:0] 8-bit Data Register.
These bits contain the byte to be received or trans-
mitted on the bus.
Read / Write
Reset value: 0000 0000 (00h)
– Transmitter mode: byte transmission start auto-
matically when the software writes in the DR reg-
ister.
7
0
FM/SM CC6
CC5
CC4
CC3
CC2
CC1
CC0
– Receiver mode: the first data byte is received au-
tomatically in the DR register using the least sig-
nificant bit of the address.
Bit 7 = FM/SM Fast/Standard I²C mode.
This bit is set and cleared by software. It is not
cleared when the interface is disabled (PE=0).
0: Standard I²C mode
Then, the following data bytes are received one
by one after reading the DR register.
1: Fast I²C mode
I²C Own Address Register (OAR)
Read / Write
Reset value: 0000 0000 (00h)
Bits 6:0 = CC[6:0] 7-bit clock divider.
These bits select the speed of the bus (F
) de-
SCL
pending on the I²C mode. They are not cleared
when the interface is disabled (PE=0).
7
0
ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0
Refer to the Electrical Characteristics section for
the table of value.
Note: The programmed F
SCL and SDA lines.
assumes no load on
SCL
Bits 7:1 = ADD[7:1] Interface address.
These bits define the I²C bus address of the inter-
face. They are not cleared when the interface is
disabled (PE=0).
I²C Data Register (DR)
Read / Write
Reset value: 0000 0000 (00h)
Bit 0 = ADD0 Address direction bit.
This bit is don’t care, the interface acknowledges
either 0 or 1. It is not cleared when the interface is
disabled (PE=0).
7
0
D7
D6
D5
D4
D3
D2
D1
D0
Note: Address 01h is always ignored.
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Table 23. I²C register map
Address
Register
name
7
6
5
4
3
2
1
0
(Hex.)
39
DR
OAR
CCR
SR2
SR1
CR
DR7 .. DR0
ADD7 .. ADD0
CC6 .. CC0
3B
3C
FM/SM
EVF
3D
AF
STOPF
BTF
ARLO
ADSL
ACK
BERR
M/SL
GCAL
SB
3E
TRA
PE
BUSY
ENGC
3F
START
STOP
ITE
Note: Refer to Section 17, "Known limitations" for information regarding a limitation on the alternate func-
tion on pin PA2 (SCL).
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12.6 8-bit A/D converter (ADC)
12.6.1 Introduction
12.6.3 Functional description
12.6.3.1 Analog power supply
and V are the high and low level refer-
ence voltage pins. In some devices (refer to device
pin out description) they are internally connected
The on-chip Analog to Digital Converter (ADC) pe-
ripheral is a 8-bit, successive approximation con-
verter with internal sample and hold circuitry. This
peripheral has up to 16 multiplexed analog input
channels (refer to device pin out description) that
allow the peripheral to convert the analog voltage
levels from up to 16 different sources.
V
DDA
SSA
to the V and V pins.
DD
SS
Conversion accuracy may therefore be impacted
by voltage drops and noise in the event of heavily
loaded or badly decoupled power supply lines.
The result of the conversion is stored in a 8-bit
Data Register. The A/D converter is controlled
through a Control/Status Register.
See electrical characteristics section for more de-
tails.
12.6.2 Main features
■ 8-bit conversion
■ Up to 12 channels with multiplexed input
■ Linear successive approximation
■ Data register (DR) which contains the results
■ Conversion complete status flag
■ On/off bit (to reduce consumption)
The block diagram is shown in Figure 47.
Figure 47. ADC block diagram
f
f
ADC
CPU
DIV 4
COCO
0
ADON
4
0
CH3 CH2 CH1 CH0
ADCCSR
AIN0
AIN1
HOLD CONTROL
R
ADC
ANALOG TO DIGITAL
CONVERTER
ANALOG
MUX
AINx
C
ADC
ADCDR
D7 D6 D5 D4 D3 D2 D1 D0
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8-bit A/D converter (ADC) (Cont’d)
12.6.3.2 Digital A/D conversion result
The analog input ports must be configured as in-
put, no pull-up, no interrupt. Refer to the «I/O
ports» chapter. Using these pins as analog inputs
does not affect the ability of the port to be read as
a logic input.
The conversion is monotonic, meaning that the re-
sult never decreases if the analog input does not
and never increases if the analog input does not.
If the input voltage (V ) is greater than or equal
AIN
In the CSR register:
to V
(high-level voltage reference) then the
DDA
conversion result in the DR register is FFh (full
scale) without overflow indication.
– Select the CH[3:0] bits to assign the analog
channel to be converted.
ADC conversion
If input voltage (V ) is lower than or equal to
AIN
V
(low-level voltage reference) then the con-
SSA
In the CSR register:
version result in the DR register is 00h.
– Set the ADON bit to enable the A/D converter
and to start the first conversion. From this time
on, the ADC performs a continuous conver-
sion of the selected channel.
The A/D converter is linear and the digital result of
the conversion is stored in the ADCDR register.
The accuracy of the conversion is described in the
parametric section.
When a conversion is complete
R
is the maximum recommended impedance
– The COCO bit is set by hardware.
– No interrupt is generated.
– The result is in the DR register and remains
valid until the next conversion has ended.
AIN
for an analog input signal. If the impedance is too
high, this will result in a loss of accuracy due to
leakage and sampling not being completed in the
alloted time.
A write to the CSR register (with ADON set) aborts
the current conversion, resets the COCO bit and
starts a new conversion.
12.6.3.3 A/D conversion phases
The A/D conversion is based on two conversion
phases as shown in Figure 48:
■ Sample capacitor loading [duration: t
Figure 48. ADC conversion timings
]
LOAD
During this phase, the V
input voltage to be
AIN
ADON
measured is loaded into the C
capacitor.
sample
ADC
ADCCSR WRITE
OPERATION
t
CONV
■ A/D conversion [duration: t
]
CONV
During this phase, the A/D conversion is
computed (8 successive approximations cycles)
HOLD
CONTROL
and the C
sample capacitor is disconnected
ADC
from the analog input pin to get the optimum
analog to digital conversion accuracy.
t
LOAD
COCO BIT SET
While the ADC is on, these two phases are contin-
uously repeated.
12.6.4 Low power modes
At the end of each conversion, the sample capaci-
tor is kept loaded with the previous measurement
load. The advantage of this behaviour is that it
minimizes the current consumption on the analog
pin in case of single input channel measurement.
Mode
Wait
Description
No effect on A/D Converter
A/D Converter disabled.
After wakeup from Halt mode, the A/D Con-
verter requires a stabilisation time before ac-
curate conversions can be performed.
Halt
12.6.3.4 Software Procedure
Refer to the control/status register (CSR) and data
register (DR) in Section 12.6.6 for the bit defini-
tions and to Figure 48 for the timings.
Note: The A/D converter may be disabled by reset-
ting the ADON bit. This feature allows reduced
power consumption when no conversion is needed
and between single shot conversions.
ADC configuration
The total duration of the A/D conversion is 12 ADC
12.6.5 Interrupts
clock periods (1/f
=4/f
).
ADC
CPU
None
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ST7263BDx ST7263BHx ST7263BKx ST7263BE
8-bit A/D converter (ADC) (Cont’d)
12.6.6 Register description
Control/Status Register (CSR)
Read/Write
pinout.
2 For SDIP/SO34 devices, the CH3 bit is always at
‘0’. If, however, set to ‘1’ on error, channel (11:8)
becomes enabled which may result in a higher and
unnecessary level of consumption.
Reset value: 0000 0000 (00h)
7
0
Data Register (DR)
Read Only
COCO
0
ADON
0
CH3
CH2
CH1
CH0
Reset value: 0000 0000 (00h)
Bit 7 = COCO Conversion Complete
This bit is set by hardware. It is cleared by soft-
ware reading the result in the DR register or writing
to the CSR register.
7
0
D7
D6
D5
D4
D3
D2
D1
D0
0: Conversion is not complete
1: Conversion can be read from the DR register
Bits 7:0 = D[7:0] Analog Converted value
This register contains the converted analog value
in the range 00h to FFh.
Bit 6 = Reserved. must always be cleared.
Note: Reading this register reset the COCO flag.
Bit 5 = ADON A/D Converter On
This bit is set and cleared by software.
0: A/D converter is switched off
1: A/D converter is switched on
Bit 4 = Reserved. must always be cleared.
Bits 3:0 = CH[3:0] Channel Selection
These bits are set and cleared by software. They
select the analog input to convert.
1
2
Channel Pin
CH3
CH2 CH1 CH0
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
AIN10
AIN11
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
1 The number of pins AND the channel selection
varies according to the device. Refer to the device
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ST7263BDx ST7263BHx ST7263BKx ST7263BE
8-bit A/D converter (ADC) (Cont’d)
Table 24. ADC register map
Address
(Hex.)
0Ah
Register
Name
7
6
0
5
4
3
2
1
0
DR
AD7 .. AD0
CH3
0Bh
CSR
COCO
ADON
0
CH2
CH1
CH0
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ST7263BDx ST7263BHx ST7263BKx ST7263BE
13 Instruction set
13.1 ST7 addressing modes
so, most of the addressing modes may be subdi-
vided in two sub-modes called long and short:
The ST7 Core features 17 different addressing
modes which can be classified in 7 main groups:
– Long addressing mode is more powerful be-
cause it can use the full 64 Kbyte address space,
however it uses more bytes and more CPU cy-
cles.
Addressing mode
Inherent
Example
nop
– Short addressing mode is less powerful because
it can generally only access page zero (0000h -
00FFh range), but the instruction size is more
compact, and faster. All memory to memory in-
structions use short addressing modes only
(CLR, CPL, NEG, BSET, BRES, BTJT, BTJF,
INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP)
Immediate
Direct
ld A,#$55
ld A,$55
ld A,($55,X)
ld A,([$55],X)
jrne loop
Indexed
Indirect
Relative
Bit operation
bset byte,#5
The ST7 Assembler optimizes the use of long and
short addressing modes.
The ST7 instruction set is designed to minimize
the number of bytes required per instruction: To do
Table 25. ST7 addressing mode overview
Pointer
address
(Hex.)
Pointer
size
(Hex.)
Destination/
source
Length
(bytes)
Mode
Syntax
Inherent
Immediate
Short
nop
+ 0
+ 1
+ 1
+ 2
ld A,#$55
ld A,$10
Direct
Direct
00..FF
Long
ld A,$1000
0000..FFFF
+ 0 (with X register)
+ 1 (with Y register)
No Offset
Direct
Indexed
ld A,(X)
00..FF
Short
Long
Short
Long
Short
Long
Relative
Relative
Bit
Direct
Indexed
Indexed
ld A,($10,X)
ld A,($1000,X)
ld A,[$10]
00..1FE
+ 1
+ 2
+ 2
+ 2
+ 2
+ 2
+ 1
+ 2
+ 1
+ 2
+ 2
+ 3
Direct
0000..FFFF
00..FF
Indirect
Indirect
Indirect
Indirect
Direct
00..FF
00..FF
00..FF
00..FF
byte
word
byte
word
ld A,[$10.w]
ld A,([$10],X)
0000..FFFF
00..1FE
Indexed
Indexed
ld A,([$10.w],X) 0000..FFFF
1)
1)
jrne loop
PC-128/PC+127
Indirect
Direct
jrne [$10]
PC-128/PC+127
00..FF
00..FF
00..FF
00..FF
byte
byte
byte
bset $10,#7
bset [$10],#7
Bit
Indirect
Direct
00..FF
Bit
Relative btjt $10,#7,skip 00..FF
Relative btjt [$10],#7,skip 00..FF
Bit
Indirect
Note 1. At the time the instruction is executed, the Program Counter (PC) points to the instruction follow-
ing JRxx.
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ST7263BDx ST7263BHx ST7263BKx ST7263BE
13.1.3 Direct
ST7 addressing modes (Cont’d)
13.1.1 Inherent
All Inherent instructions consist of a single byte.
The opcode fully specifies all the required informa-
tion for the CPU to process the operation.
In Direct instructions, the operands are referenced
by their memory address.
The direct addressing mode consists of two sub-
modes:
Inherent instruction
Function
No operation
Direct (short)
NOP
The address is a byte, thus requires only one byte
after the opcode, but only allows 00 - FF address-
ing space.
TRAP
S/W Interrupt
Wait For Interrupt (Low power
mode)
WFI
Direct (long)
Halt Oscillator (Lowest Power
mode)
HALT
The address is a word, thus allowing 64 Kbyte ad-
dressing space, but requires 2 bytes after the op-
code.
RET
Sub-routine Return
Interrupt Sub-routine Return
Set Interrupt Mask
Reset Interrupt Mask
Set Carry flag
IRET
SIM
13.1.4 Indexed (No Offset, Short, Long)
RIM
In this mode, the operand is referenced by its
memory address, which is defined by the unsigned
addition of an index register (X or Y) with an offset.
SCF
RCF
Reset Carry flag
The indirect addressing mode consists of three
sub-modes:
RSP
Reset Stack Pointer
Load
LD
Indexed (No Offset)
CLR
Clear
There is no offset, (no extra byte after the opcode),
and allows 00 - FF addressing space.
PUSH/POP
INC/DEC
TNZ
Push/Pop to/from the stack
Increment/Decrement
Test Negative or Zero
1 or 2 Complement
Byte Multiplication
Indexed (Short)
The offset is a byte, thus requires only one byte af-
ter the opcode and allows 00 - 1FE addressing
space.
CPL, NEG
MUL
Indexed (long)
SLL, SRL, SRA, RLC,
RRC
Shift and Rotate Operations
Swap Nibbles
The offset is a word, thus allowing 64 Kbyte ad-
dressing space and requires 2 bytes after the op-
code.
SWAP
13.1.2 Immediate
Immediate instructions have two bytes, the first
byte contains the opcode, the second byte con-
tains the operand value.
13.1.5 Indirect (Short, Long)
The required data byte to do the operation is found
by its memory address, located in memory (point-
er).
Immediate instruction
Function
The pointer address follows the opcode. The indi-
rect addressing mode consists of two sub-modes:
LD
Load
CP
Compare
Indirect (short)
BCP
Bit Compare
The pointer address is a byte, the pointer size is a
byte, thus allowing 00 - FF addressing space, and
requires 1 byte after the opcode.
AND, OR, XOR
ADC, ADD, SUB, SBC
Logical Operations
Arithmetic Operations
Indirect (long)
The pointer address is a byte, the pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.
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ST7 addressing modes (Cont’d)
13.1.6 Indirect Indexed (Short, Long)
SWAP
CALL, JP
Swap Nibbles
This is a combination of indirect and short indexed
addressing modes. The operand is referenced by
its memory address, which is defined by the un-
signed addition of an index register value (X or Y)
with a pointer value located in memory. The point-
er address follows the opcode.
Call or Jump subroutine
13.1.7 Relative mode (Direct, Indirect)
This addressing mode is used to modify the PC
register value by adding an 8-bit signed offset to it.
Available Relative Direct/
Function
The indirect indexed addressing mode consists of
two sub-modes:
Indirect instructions
JRxx
Conditional Jump
Call Relative
Indirect Indexed (Short)
CALLR
The pointer address is a byte, the pointer size is a
byte, thus allowing 00 - 1FE addressing space,
and requires 1 byte after the opcode.
The relative addressing mode consists of two sub-
modes:
Indirect Indexed (Long)
Relative (Direct)
The pointer address is a byte, the pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.
The offset follows the opcode.
Relative (Indirect)
The offset is defined in memory, of which the ad-
dress follows the opcode.
Table 26. Instructions supporting Direct,
Indexed, Indirect and Indirect Indexed
addressing modes
Long and Short
Function
instructions
LD
Load
CP
Compare
AND, OR, XOR
Logical Operations
Arithmetic Addition/subtrac-
tion operations
ADC, ADD, SUB, SBC
BCP
Bit Compare
Short instructions only
CLR
Function
Clear
INC, DEC
Increment/Decrement
Test Negative or Zero
1 or 2 Complement
Bit Operations
TNZ
CPL, NEG
BSET, BRES
Bit Test and Jump Opera-
tions
BTJT, BTJF
SLL, SRL, SRA, RLC,
RRC
Shift and Rotate Operations
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ST7263BDx ST7263BHx ST7263BKx ST7263BE
13.2 insTruction groups
The ST7 family devices use an instruction set con-
sisting of 63 instructions. The instructions may be
subdivided into 13 main groups as illustrated in the
following table:
Load and Transfer
LD
CLR
POP
DEC
TNZ
OR
Stack operation
PUSH
INC
RSP
Increment/Decrement
Compare and Tests
Logical operations
CP
BCP
XOR
AND
BSET
BTJT
ADC
SLL
CPL
NEG
Bit Operation
BRES
BTJF
ADD
SRL
JRT
Conditional Bit Test and Branch
Arithmetic operations
Shift and Rotates
SUB
SRA
JRF
SBC
RLC
JP
MUL
RRC
CALL
SWAP
CALLR
SLA
Unconditional Jump or Call
Conditional Branch
JRA
JRxx
TRAP
SIM
NOP
RET
Interruption management
Condition Code flag modification
WFI
RIM
HALT
SCF
IRET
RCF
Using a pre-byte
The instructions are described with one to four
bytes.
These prebytes enable instruction in Y as well as
indirect addressing modes to be implemented.
They precede the opcode of the instruction in X or
the instruction using direct addressing mode. The
prebytes are:
In order to extend the number of available op-
codes for an 8-bit CPU (256 opcodes), three differ-
ent prebyte opcodes are defined. These prebytes
modify the meaning of the instruction they pre-
cede.
PDY 90 Replace an X based instruction using
immediate, direct, indexed, or inherent
addressing mode by a Y one.
The whole instruction becomes:
PC-2 End of previous instruction
PC-1 Prebyte
PIX 92 Replace an instruction using direct, di-
rect bit, or direct relative addressing
mode to an instruction using the corre-
sponding indirect addressing mode.
It also changes an instruction using X
indexed addressing mode to an instruc-
tion using indirect X indexed addressing
mode.
PC
Opcode
PC+1 Additional word (0 to 2) according to the
number of bytes required to compute the
effective address
PIY 91 Replace an instruction using X indirect
indexed addressing mode by a Y one.
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ST7263BDx ST7263BHx ST7263BKx ST7263BE
Instruction groups (Cont’d)
Mnemo
ADC
ADD
AND
BCP
Description
Add with Carry
Function/Example
A = A + M + C
A = A + M
Dst
Src
H
H
H
I
N
N
N
N
N
Z
Z
Z
Z
Z
C
C
C
A
M
M
M
M
Addition
A
Logical And
A = A . M
A
Bit compare A, Memory
Bit Reset
tst (A . M)
A
BRES
BSET
BTJF
BTJT
CALL
CALLR
CLR
bres byte, #3
bset byte, #3
btjf byte, #3, Jmp1
btjt byte, #3, Jmp1
M
M
M
M
Bit Set
Jump if bit is false (0)
Jump if bit is true (1)
Call subroutine
Call subroutine relative
Clear
C
C
reg, M
reg
0
N
N
N
1
Z
Z
Z
CP
Arithmetic Compare
One Complement
Decrement
tst(Reg - M)
A = FFH-A
dec Y
M
C
1
CPL
reg, M
reg, M
DEC
HALT
IRET
INC
Halt
0
I
Interrupt routine return
Increment
Pop CC, A, X, PC
inc X
H
N
N
Z
Z
C
reg, M
JP
Absolute Jump
Jump relative always
Jump relative
jp [TBL.w]
JRA
JRT
JRF
Never jump
jrf *
JRIH
JRIL
Jump if ext. interrupt = 1
Jump if ext. interrupt = 0
Jump if H = 1
JRH
H = 1 ?
JRNH
JRM
Jump if H = 0
H = 0 ?
Jump if I = 1
I = 1 ?
JRNM
JRMI
JRPL
JREQ
JRNE
JRC
Jump if I = 0
I = 0 ?
Jump if N = 1 (minus)
Jump if N = 0 (plus)
Jump if Z = 1 (equal)
Jump if Z = 0 (not equal)
Jump if C = 1
N = 1 ?
N = 0 ?
Z = 1 ?
Z = 0 ?
C = 1 ?
JRNC
JRULT
Jump if C = 0
C = 0 ?
Jump if C = 1
Unsigned <
Jmp if unsigned >=
Unsigned >
JRUGE Jump if C = 0
JRUGT Jump if (C + Z = 0)
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ST7263BDx ST7263BHx ST7263BKx ST7263BE
Instruction groups(Cont’d)
Mnemo
JRULE
LD
Description
Jump if (C + Z = 1)
Load
Function/Example
Unsigned <=
dst <= src
Dst
Src
H
I
N
N
N
N
N
Z
Z
Z
Z
Z
C
reg, M
A, X, Y
reg, M
M, reg
X, Y, A
MUL
NEG
NOP
OR
Multiply
X,A = X * A
0
0
Negate (2's compl)
No Operation
OR operation
Pop from the Stack
neg $10
C
A = A + M
pop reg
pop CC
push Y
C = 0
A
M
POP
reg
CC
M
M
M
H
I
C
0
PUSH
RCF
RET
RIM
Push onto the Stack
Reset carry flag
Subroutine Return
Enable Interrupts
Rotate left true C
Rotate right true C
Reset Stack Pointer
Subtract with Carry
Set carry flag
reg, CC
I = 0
0
RLC
RRC
RSP
SBC
SCF
SIM
C <= Dst <= C
C => Dst => C
S = Max allowed
A = A - M - C
C = 1
reg, M
reg, M
N
N
Z
Z
C
C
A
M
N
Z
C
1
Disable Interrupts
Shift left Arithmetic
Shift left Logic
I = 1
1
SLA
C <= Dst <= 0
C <= Dst <= 0
0 => Dst => C
Dst7 => Dst => C
A = A - M
reg, M
reg, M
reg, M
reg, M
A
N
N
0
Z
Z
Z
Z
Z
Z
Z
C
C
C
C
C
SLL
SRL
SRA
SUB
SWAP
TNZ
TRAP
WFI
Shift right Logic
Shift right Arithmetic
Subtraction
N
N
N
N
M
SWAP nibbles
Dst[7..4] <=> Dst[3..0] reg, M
tnz lbl1
Test for Neg & Zero
S/W trap
S/W interrupt
1
0
Wait for Interrupt
Exclusive OR
XOR
A = A XOR M
A
M
N
Z
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ST7263BDx ST7263BHx ST7263BKx ST7263BE
14 Electrical characteristics
14.1 Parameter conditions
Unless otherwise specified, all voltages are re-
ferred to V
Figure 50. Pin input voltage
.
SS
14.1.1 Minimum and maximum values
Unless otherwise specified the minimum and max-
imum values are guaranteed in the worst condi-
tions of ambient temperature, supply voltage and
frequencies by tests in production on 100% of the
ST7 PIN
V
IN
devices with an ambient temperature at T =25°C
A
and T =T max (given by the selected temperature
A
A
range).
Data based on characterization results, design
simulation and/or technology characteristics are
indicated in the table footnotes and are not tested
in production. Based on characterization, the min-
imum and maximum values refer to sample tests
and represent the mean value plus or minus three
times the standard deviation (mean±3Σ).
14.1.2 Typical values
Unless otherwise specified, typical data are based
on T =25°C, V =5V. They are given only as de-
A
DD
sign guidelines and are not tested.
14.1.3 Typical curves
Unless otherwise specified, all typical curves are
given only as design guidelines and are not tested.
14.1.4 Loading capacitor
The loading conditions used for pin parameter
measurement are shown in Figure 49.
Figure 49. Pin loading conditions
ST7 PIN
C
L
14.1.5 Pin input voltage
The input voltage measurement on a pin of the de-
vice is described in Figure 50.
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ST7263BDx ST7263BHx ST7263BKx ST7263BE
14.2 Absolute maximum ratings
Stresses above those listed as “absolute maxi-
mum ratings” may cause permanent damage to
the device. This is a stress rating only and func-
tional operation of the device under these condi-
tions is not implied. Exposure to maximum rating
conditions for extended periods may affect device
reliability.
14.2.1 Voltage characteristics
Symbol
- V
Ratings
Maximum value
6.0
Unit
V
Supply voltage
DD
SS
Input voltage on true open drain pins
Input voltage on any other pin
VSS-0.3 to 6.0
VSS-0.3 to VDD+0.3
V
1) & 2)
V
IN
See “Absolute maximum ratings
(electrical sensitivity)” on page 116.
V
Electro-static discharge voltage (Human Body model)
ESD(HBM)
14.2.2 Current characteristics
Symbol
Ratings
Maximum value
Unit
mA
µA
3)
3)
I
Total current into V power lines (source)
80
80
VDD
DD
I
Total current out of V ground lines (sink)
SS
VSS
Output current sunk by any standard I/O and control pin
Output current sunk by any high sink I/O pin
25
I
50
IO
Output current source by any I/Os and control pin
- 25
± 5
± 5
± 5
± 5
± 20
- 80
Injected current on V pin
PP
Injected current on RESET pin
2) & 4)
I
I
INJ(PIN)
Injected current on OSCIN and OSCOUT pins
5) & 6)
Injected current on any other pin
2)
5)
ΣI
Total injected current (sum of all I/O and control pins)
Negative injected current to PB0(10mA)/AIN0 pin
INJ(PIN)
2) & 4)
INJ(PIN)
Notes:
1. Directly connecting the RESET and I/O pins to V or V could damage the device if an unintentional internal reset
DD
SS
is generated or an unexpected change of the I/O configuration occurs (for example, due to a corrupted program counter).
To guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7kΩ for
RESET, 10kΩ for I/Os). Unused I/O pins must be tied in the same way to V or V according to their reset configuration.
DD
SS
2. I
must never be exceeded. This is implicitly insured if V maximum is respected. If V maximum cannot be
INJ(PIN)
IN
IN
respected, the injection current must be limited externally to the I
value. A positive injection is induced by V >V
INJ(PIN)
IN DD
while a negative injection is induced by V <V . For true open-drain pads, there is no positive injection current, and the
corresponding V maximum must always be respected
IN
SS
IN
3. All power (V ) and ground (V ) lines must always be connected to the external supply.
DD
SS
4. Negative injection disturbs the analog performance of the device. In particular, it induces leakage currents throughout
the device including the analog inputs. To avoid undesirable effects on the analog functions, care must be taken:
- Analog input pins must have a negative injection less than 0.8 mA (assuming that the impedance of the analog voltage
is lower than the specified limits)
- Pure digital pins must have a negative injection less than 1.6mA. In addition, it is recommended to inject the current as
far as possible from the analog input pins.
5. When several inputs are submitted to a current injection, the maximum ΣI
is the absolute sum of the positive
INJ(PIN)
and negative injected currents (instantaneous values). These results are based on characterization with ΣI
maxi-
INJ(PIN)
mum current injection on four I/O port pins of the device.
6. True open drain I/O port pins do not accept positive injection.
14.2.3 Thermal characteristics
Symbol
Ratings
Storage temperature range
value
Unit
T
-65 to +150
°C
STG
T
Maximum junction temperature: See section 15.2 on page 131 for T
Jmax
J
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ST7263BDx ST7263BHx ST7263BKx ST7263BE
14.3 Operating conditions
14.3.1 General operating conditions
Symbol
Parameter
Operating Supply Voltage
Analog reference voltage
Analog reference voltage
Conditions
Min
Typ
Max
Unit
V
f
= 8 MHz
CPU
4
5
5.5
DD
V
V
V
DD
V
DDA
DD
V
V
V
SS
SSA
SS
f
f
= 24 MHz
= 12 MHz
8
4
OSC
OSC
Operating frequency
f
MHz
°C
CPU
Ambient temperature range
T
0
70
A
Figure 51. f
maximum operating frequency versus VDD supply voltage
CPU
f
[MHz]
8
CPU
FUNCTIONALITY
GUARANTEED
FROM 4 TO 5.5 V
4
2
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
0
SUPPLY VOLTAGE [V]
2.5
3.0
3.5
4
4.5
5
5.5
14.3.2 Operating conditions with Low Voltage Detector (LVD)
Subject to general operating conditions for V , f , and T . Refer to Figure 12 on page 24.
DD CPU
A
Symbol
Parameter
Conditions
Min
3.4
3.2
100
0.5
Typ
3.7
Max
4.0
3.8
220
50
Unit
V
V
Low Voltage Reset Threshold (V rising) V Max. Variation 50V/ms
IT+
DD
DD
V
Low Voltage Reset Threshold (V falling)
V
Max. Variation 50V/ms
3.5
V
IT-
DD
DD
2)
V
Hysteresis (V - V
)
175
mV
V/ms
hyst
IT+
IT-
1)
Vt
V
rise time rate
POR
DD
Notes:
1. The V rise time rate condition is needed to insure a correct device power-on and LVD reset. Not tested in production.
DD
2. Guaranteed by characterization - not tested in production
110/145
ST7263BDx ST7263BHx ST7263BKx ST7263BE
14.4 Supply current characteristics
The following current consumption specified for
the ST7 functional operating modes over tempera-
ture range does not take into account the clock
source current consumption. To get the total de-
vice consumption, the two current values must be
added (except for Halt mode for which the clock is
stopped).
Symbol
Parameter
Conditions
Typ
Max
Unit
3)
Supply current variation vs. temperature Constant V and f
∆I
10
%
DD
CPU
DD(∆Ta)
1)3)
f
f
f
f
= 4 MHz
= 8 MHz
= 4 MHz
= 8 MHz
7.5
9
CPU
CPU
CPU
CPU
CPU Run mode
I/Os in input mode
mA
1)
10.5 13
3)
6
8
CPU Wait mode
CPU Halt mode
mA
µA
µA
1)
3)
I
8.5
25
11
40
DD
2)
LVD disabled
LVD disabled
LVD enabled
100
230
120
4)
USB Suspend mode
Notes:
1. Oscillator and watchdog running. All others peripherals disabled.
2. USB Transceiver and ADC are powered down.
3. Not tested in production, guaranteed by characterization.
4. CPU in Halt mode. Current consumption of external pull-up (1.5Kohms to USBVCC) and pull-down (15Kohms to
) not included.
V
SSA
Figure 52. Typ. I in Run at 4 and 8 MHz f
Figure 53. Typ. I in Wait at 4 and 8 MHz f
CPU
DD
CPU
DD
Idd WFI (mA) at fcpu=4 and 8MHz
Idd Run (mA) at fcpu=4 and 8MHz
12
10
10
8
8
6
4
6
4
8MHz
4MHz
8MHz
4MHz
2
0
2
0
4
4.2
4.4
4.6
4.8
Vdd (V)
5
5.2
5.4
4
4.2
4.4
4.6
4.8
Vdd (V)
5
5.2
5.4
111/145
ST7263BDx ST7263BHx ST7263BKx ST7263BE
14.5 Clock and timing characteristics
Subject to general operating conditions for V , f
, and T .
DD CPU
A
14.5.1 General timings
1)
Symbol
Parameter
Conditions
Min
2
Typ
Max
12
Unit
tCPU
ns
3
t
Instruction cycle time
f
f
=8MHz
c(INST)
CPU
CPU
250
10
375
1500
22
2)
tCPU
µs
Interrupt reaction time
t
=8MHz
v(IT)
t
= ∆t
+ 10 t
c(INST) CPU
1.25
2.75
v(IT)
Notes:
1. Data based on typical application software.
2. Time measured between interrupt event and interrupt vector fetch. ∆tc(INST) is the number of tCPU cycles needed to finish
the current instruction execution.
14.5.2 Control timing characteristics
Control timings
value
Symbol
Parameter
Conditions
Unit
Min
Typ.
Max
24
8
fOSC
fCPU
Oscillator Frequency
Operating Frequency
External RESET
MHz
MHz
tRL
2520
ns
Input pulse Width
tPORL
Internal Power Reset Duration
4096
200
tCPU
ns
Watchdog or Low Voltage Reset
Output Pulse Width
TDOGL
300
30
49152
6.144
3145728
393.216
tCPU
ms
tDOG
Watchdog Time-out
f
cpu = 8MHz
Crystal Oscillator
Start-up Time
1)
1)
t
20
40
ms
ms
OXOV
1)
tDDR
Power up rise time
from V = 0 to 4V
100
DD
Note:
1. Not tested in production, guaranteed by characterization.
112/145
ST7263BDx ST7263BHx ST7263BKx ST7263BE
Clock and timing characteristics (Cont’d)
14.5.3 External clock source
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
V
OSCIN input pin high level voltage
OSCIN input pin low level voltage
0.7xV
V
DD
OSCINH
DD
V
V
V
0.3xV
DD
OSCINL
SS
t
t
1)
w(OSCINH)
see Figure 54
OSCIN high or low time
15
w(OSCINL)
ns
t
t
1)
r(OSCIN)
OSCIN rise or fall time
15
±1
f(OSCIN)
I
OSCx Input leakage current
V
≤V ≤V
DD
µA
L
SS
IN
Note:
1. Data based on design simulation and/or technology characteristics, not tested in production.
Figure 54. Typical application with an external clock source
90%
V
V
OSCINH
10%
OSCINL
t
t
w(OSCINH)
t
t
w(OSCINL)
f(OSCIN)
r(OSCIN)
OSCOUT
OSCIN
Not connected internally
f
OSC
EXTERNAL
CLOCK SOURCE
I
L
ST72XXX
Figure 55. Typical application with a crystal resonator
i
2
f
OSC
C
L1
OSCIN
RESONATOR
R
F
C
L2
OSCOUT
ST72XXX
113/145
ST7263BDx ST7263BHx ST7263BKx ST7263BE
14.6 Memory characteristics
Subject to general operating conditions for f
, and T unless otherwise specified.
A
CPU
14.6.1 RAM and hardware registers
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
1)
V
Data retention mode
Halt mode (or RESET)
2.0
V
RM
Note:
1. Guaranteed by design. Not tested in production.
14.6.2 Flash memory
Operating Conditions: f
= 8 MHz.
CPU
1)
Dual voltage Flash memory
Symbol
Parameter
Conditions
Read mode
Min
Typ
Max
Unit
8
f
Operating Frequency
MHz
Write / Erase mode,
CPU
8
T =25°C
A
V
Programming Voltage
Current
4.0V ≤V ≤ 5.5V
Write / Erase
11.4
12.6
V
PP
DD
I
V
30
10
mA
PP
PP
t
t
Internal V Stabilization Time
µs
VPP
PP
Data Retention
T ≤ 55°C
40
years
cycles
RET
A
N
Write Erase Cycles
T =25°C
100
RW
A
Note:
1. Refer to the Flash Programming Reference Manual for the typical HDFlash programming and erase timing values.
1)
Figure 56. Two typical applications with V pin
PP
V
V
PP
PP
PROGRAMMING
TOOL
10kΩ
ST72XXX
ST72XXX
Note:
1. When the ICP mode is not required by the application, V pin must be tied to V
.
SS
PP
114/145
ST7263BDx ST7263BHx ST7263BKx ST7263BE
14.7 EMC characteristics
tion environment and simplified MCU software. It
should be noted that good EMC performance is
highly dependent on the user application and the
software in particular.
Susceptibility tests are performed on a sample ba-
sis during product characterization.
14.7.1 Functional EMS (Electromagnetic
susceptibility)
Therefore it is recommended that the user applies
EMC software optimization and prequalification
tests in relation with the EMC level requested for
his application.
Based on a simple running application on the
product (toggling 2 LEDs through I/O ports), the
product is stressed by two electro magnetic events
until a failure occurs (indicated by the LEDs).
■ ESD: Electro-Static Discharge (positive and
negative) is applied on all pins of the device until
a functional disturbance occurs. This test
conforms with the IEC 1000-4-2 standard.
Software recommendations:
The software flowchart must include the manage-
ment of runaway conditions such as:
– Corrupted program counter
– Unexpected reset
■ FTB: A Burst of Fast Transient voltage (positive
– Critical Data corruption (control registers...)
Prequalification trials:
and negative) is applied to V and V through
DD
SS
a 100pF capacitor, until a functional disturbance
occurs. This test conforms with the IEC 1000-4-
4 standard.
Most of the common failures (unexpected reset
and program counter corruption) can be repro-
duced by manually forcing a low state on the RE-
SET pin or the Oscillator pins for 1 second.
A device reset allows normal operations to be re-
sumed. The test results are given in the table be-
low based on the EMS levels and classes defined
in application note AN1709.
To complete these trials, ESD stress can be ap-
plied directly on the device, over the range of
specification values. When unexpected behaviour
is detected, the software can be hardened to pre-
vent unrecoverable errors occurring (see applica-
tion note AN1015).
14.7.1.1 Designing hardened software to avoid
noise problems
EMC characterization and optimization are per-
formed at component level with a typical applica-
Level/
Symbol
Parameter
Conditions
Class
Voltage limits to be applied on any I/O pin to induce
a functional disturbance
V
=5V, T =+25°C, f
=8MHz, PSDIP32
=8MHz, PSDIP32
OSC
DD
A
OSC
V
4B
FESD
conforms to IEC 1000-4-2
Fast transient voltage burst limits to be applied
V
=5V, T =+25°C, f
DD
A
V
through 100pF on V and V pins to induce a
4A
FFTB
DD DD
conforms to IEC 1000-4-4
functional disturbance
14.7.2 Electromagnetic interference (EMI)
Based on a simple application running on the
product (toggling 2 LEDs through the I/O ports),
the product is monitored in terms of emission. This
emission test is in line with the norm SAE J 1752/
3 which specifies the board and the loading of
each pin.
Max vs.
[f
/
]
Monitored
frequency band
OSC
Symbol
Parameter
Conditions
Unit
f
CPU
16/8MHz
0.1MHz to 30MHz
36
39
26
3.5
V
=5V, T =+25°C, PSDIP32 package
A
DD
conforming to SAE J 1752/3
30MHz to 130MHz
dBµV
1)
S
Peak level
EMI
Note: Refer to Application Note AN1709 for 130MHz to 1GHz
data on other package types.
SAE EMI Level
-
Note:
1. Data based on characterization results, not tested in production.
115/145
ST7263BDx ST7263BHx ST7263BKx ST7263BE
EMC characteristics (Cont’d)
14.7.3 Absolute maximum ratings (electrical
sensitivity)
14.7.3.1 Electrostatic discharge (ESD)
Electrostatic Discharges (a positive then a nega-
tive pulse separated by 1 second) are applied to
the pins of each sample according to each pin
combination. The sample size depends on the
number of supply pins in the device (3 parts*(n+1)
supply pin). This test conforms to the JESD22-
A114A/A115A standard.
Based on three different tests (ESD, LU and DLU)
using specific measurement methods, the product
is stressed in order to determine its performance in
terms of electrical sensitivity. For more details, re-
fer to the application note AN1181.
Absolute maximum ratings
1)
Symbol
Ratings
Conditions
Maximum value
Unit
Electrostatic discharge voltage
(Human body model)
T =+25°C
V
2000
V
A
ESD(HBM)
Note:
1. Data based on characterization results, not tested in production.
14.7.3.2 Static and dynamic Latch-Up
■ DLU: Electrostatic discharges (one positive
then one negative test) are applied to each pin
of 3 samples when the micro is running to
assess the latch-up performance in dynamic
mode. Power supplies are set to the typical
values, the oscillator is connected as near as
possible to the pins of the micro and the
component is put in reset mode. This test
conforms to the IEC1000-4-2 and SAEJ1752/3
standards. For more details, refer to the
application note AN1181.
■ LU: 3 complementary static tests are required
on 10 parts to assess the latch-up performance.
A supply overvoltage (applied to each power
supply pin) and a current injection (applied to
each input, output and configurable I/O pin) are
performed on each sample. This test conforms
to the EIA/JESD 78 IC latch-up standard. For
more details, refer to the application note
AN1181.
Electrical sensitivities
1)
Symbol
LU
Parameter
Static latch-up class
Dynamic latch-up class
Conditions
Class
T =+25°C
A
A
A
V
=5.5V, f
=4MHz, T =+25°C
OSC A
DLU
DD
Note:
1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC spec-
ifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the
JEDEC criteria (international standard).
116/145
ST7263BDx ST7263BHx ST7263BKx ST7263BE
14.8 I/O port pin characteristics
14.8.1 General characteristics
Subject to general operating conditions for V , f
, and T unless otherwise specified.
A
DD CPU
Symbol
Parameter
Input low level voltage
Input high level voltage
Conditions
Min
Typ
Max
Unit
V
0.3xVDD
IL
V
V
0.7xVDD
IH
True open drain I/O pins
Other I/O pins
6.0
V
Input voltage
V
V
IN
SS
V
DD
V
Schmitt trigger voltage hysteresis
Input leakage current
400
400
mV
hys
I
V
SS≤V ≤V
DD
±1
L
IN
µA
Static current consumption induced
I
Floating input mode
V =V =5V
1)
S
by each floating input pin
2)
R
Weak pull-up equivalent resistor
V
DD
50
90
5
120
kΩ
PU
IN
SS
C
I/O pin capacitance
pF
IO
t
Output high to low level fall time
Output low to high level rise time
25
25
C =50pF
Between 10% and 90%
f(IO)out
r(IO)out
L
ns
t
3)
t
External interrupt pulse time
1
t
CPU
w(IT)in
Notes:
1. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for
example or an external pull-up or pull-down resistor (see Figure 57). Static peak current value taken at a fixed V value,
IN
based on design simulation and technology characteristics, not tested in production. This value depends on V and tem-
DD
perature values.
2. The R pull-up equivalent resistor is based on a resistive transistor (corresponding I current characteristics de-
PU
PU
scribed in Figure 58).
3. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external
interrupt source.
Figure 57. Two typical applications with unused I/O pin
V
ST72XXX
DD
UNUSED I/O PORT
10kΩ
10kΩ
UNUSED I/O PORT
ST72XXX
Figure 58. Typ. I vs. V
PU
DD
Pull-up current (µA)
90
80
70
60
50
40
30
20
10
0
4
4.2
4.4
4.6
4.8
5
5.2
5.4
Vdd (V)
117/145
ST7263BDx ST7263BHx ST7263BKx ST7263BE
Figure 59. Typ. R vs. V
PU
DD
Rpu (KOhm)
140
120
100
80
60
40
20
0
4
4.2
4.4
4.6
4.8
5
5.2
5.4
Vdd (V)
14.8.2 Output driving current
Subject to general operating condition for V , f
, and T unless otherwise specified.
DD CPU
A
Symbol
Parameter
Conditions
Min
Max
Unit
Output low level voltage for a standard I/O pin
when up to 8 pins are sunk at the same time, Port
A0, Port A(3:7), Port C(0:2), Port D(0:7)
I
I
I
=+1.6mA
=+10mA
=+25mA
0.4
IO
IO
IO
Output low level voltage for a high sink I/O pin
when up to 4 pins are sunk at the same time, Port
B(0:7)
1)
V
1.3
1.5
OL
V
Output low level voltage for a very high sink I/O
pin when up to 2 pins are sunk at the same time,
Port A1, Port A2
3)
I
I
=-10mA
=-1.6mA
V
-1.3
DD
Output high level voltage for an I/O pin
when up to 8 pins are sourced at same time
IO
2)
V
OH
V
-0.8
IO
DD
Notes:
1. The I current sunk must always respect the absolute maximum rating specified in Section 14.2 and the sum of I (I/
IO
IO
O ports and control pins) must not exceed I
.
VSS
2. The I current sourced must always respect the absolute maximum rating specified in Section 14.2 and the sum of I
IO
IO
(I/O ports and control pins) must not exceed I
. True open drain I/O pins does not have V
.
VDD
OH
3. The minimum V value (with I =-10mA) depends on the chosen device type. For Flash devices, min = V - 1.3 V
OH
IO
DD
and for ROM devices, min = V - 1.7 V
DD
118/145
ST7263BDx ST7263BHx ST7263BKx ST7263BE
Figure 60. V standard V =5 V
Figure 61. V high sink V =5 V
OL DD
OL
DD
Vol_2mA (mV) at Vdd=5V
Vol_10mA (V) at Vdd=5V
250
200
150
100
50
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
1
1.5
2
2.5
Iio (mA)
3
3.5
4
5
7
9
11
13
Iio (mA)
15
17
19
Figure 62. V very high sink V =5 V
Figure 64. V high sink vs. V
OL DD
OL
DD
Vol_25mA (V) at Vdd=5V
Vol_10mA (V) at Iio=10mA
0.6
0.59
0.58
0.57
0.56
0.55
0.54
0.53
0.52
0.51
0.5
0.95
0.85
0.75
0.65
0.55
0.45
0.35
4
4.2
4.4
4.6
4.8
5
5.2
5.4
15
20
25
30
35
Vdd (V)
Iio (mA)
Figure 63. V standard vs. V
Figure 65. V very high sink vs. V
DD
OL
DD
OL
Vol_25mA (V) at Iio=25mA
Vol_2mA (mV) at Iio=2mA
0.8
130
125
120
115
110
105
0.75
0.7
0.65
0.6
4
4.2
4.4
4.6
4.8
Vdd (V)
5
5.2
5.4
4
4.2
4.4
4.6
4.8
Vdd (V)
5
5.2
5.4
119/145
ST7263BDx ST7263BHx ST7263BKx ST7263BE
Figure 66. |V -V | @ V =5 V (low current)
Figure 67. |V -V | @ V =5 V (high current)
DD OH DD
DD OH
DD
|Vdd - Voh| (V) at Vdd=5V
|Vdd - Voh| (V) at Vdd=5V
0.3
0.25
0.2
2
1.8
1.6
1.4
1.2
1
0.15
0.1
0.8
0.6
0.4
0.2
0
0.05
0
1
1.5
2
2.5
3
3.5
4
2
7
12
17
-Iio (mA)
-Iio (mA)
Figure 68. |V -V | @ I =2 mA (low current)
Figure 69. |V -V
|
@ I =10 mA (high
IO
DD OH
IO
DD OH
current)
|Vdd - Voh| (V) at Iio=-2mA
|Vdd - Voh| (V) at Iio=-10mA
0.165
0.16
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.155
0.15
0.145
0.14
0.135
0.13
0.125
0.12
0
4
4
4.2
4.4
4.6
4.8
Vdd (V)
5
5.2
5.4
4.2
4.4
4.6
4.8
5
5.2
5.4
Vdd (V)
120/145
ST7263BDx ST7263BHx ST7263BKx ST7263BE
14.9 Control pin characteristics
14.9.1 Asynchronous RESET pin
Subject to general operating conditions for V , f
, and T unless otherwise specified.
A
DD CPU
Symbol
Parameter
Input High Level Voltage
Input Low Voltage
Conditions
Min
0.7xV
Typ
400
80
Max
Unit
V
V
V
DD
IH
DD
SS
V
V
0.3xV
V
IL
DD
1)
V
Schmitt trigger voltage hysteresis
mV
hys
I
I
=5mA
=7.5mA
=5V
0.8
1.3
IO
2)
V
R
Output low level voltage
V
=5V
DD
V
OL
IO
3)
Weak pull-up equivalent resistor
Generated reset pulse duration
V =V
V
50
100
kΩ
ON
IN
SS
DD
External pin or
internal reset sources
6
30
1/f
SFOSC
t
w(RSTL)out
µs
4)
t
External reset pulse hold time
5
µs
h(RSTL)in
Notes:
1. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
2. The I current sunk must always respect the absolute maximum rating specified in Section 14.2 and the sum of I (I/
IO
IO
O ports and control pins) must not exceed I
.
VSS
3. The R
pull-up equivalent resistor is based on a resistive transistor. This data is based on characterization results,
ON
not tested in production.
4. To guarantee the reset of the device, a minimum pulse has to be applied to RESET pin. All short pulses applied on
RESET pin with a duration below t
can be ignored.
h(RSTL)in
121/145
ST7263BDx ST7263BHx ST7263BKx ST7263BE
Control pin characteristics (Cont’d)
1)2)3)4)
Figure 70. RESET pin protection when LVD is enabled.
V
ST72XXX
DD
Optional
(note 6)
Required
R
ON
Filter
INTERNAL
RESET
EXTERNAL
RESET
0.01µF
1MΩ
WATCHDOG
PULSE
GENERATOR
LVD RESET
1)
Figure 71. RESET pin protection when LVD is disabled.
Recommended for EMC
V
ST72XXX
DD
V
V
DD
DD
R
ON
Filter
0.01µF
0.01µF
4.7kΩ
INTERNAL
RESET
USER
EXTERNAL
RESET
CIRCUIT
PULSE
GENERATOR
WATCHDOG
Required
Note 1:
– The reset network protects the device against parasitic resets.
– The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the
device can be damaged when the ST7 generates an internal reset (LVD or watchdog).
– Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin can go
below the V max. level specified in section 14.9.1 on page 121. Otherwise the reset will not be taken into account
IL
internally.
– Because the reset circuit is designed to allow the internal RESET to be output in the RESET pin, the user must en-
sure that the current sunk on the RESET pin is less than the absolute maximum value specified for I
section 14.2.2 on page 109.
in
INJ(RESET)
Note 2: When the LVD is enabled, it is recommended not to connect a pull-up resistor or capacitor. A 10nF pull-down
capacitor is required to filter noise on the reset line.
Note 3: In case a capacitive power supply is used, it is recommended to connect a 1MΩ pull-down resistor to the RESET
pin to discharge any residual voltage induced by the capacitive effect of the power supply (this will add 5µA to the power
consumption of the MCU).
Note 4: Tips when using the LVD:
– 1. Check that all recommendations related to ICCCLK and reset circuit have been applied (see notes above).
– 2. Check that the power supply is properly decoupled (100nF + 10µF close to the MCU). Refer to AN1709 and
AN2017. If this cannot be done, it is recommended to put a 100nF + 1MΩ pull-down on the RESET pin.
– 3. The capacitors connected on the RESET pin and also the power supply are key to avoid any start-up marginality.
In most cases, steps 1 and 2 above are sufficient for a robust solution. Otherwise: replace 10nF pull-down on the
RESET pin with a 5µF to 20µF capacitor.”
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ST7263BDx ST7263BHx ST7263BKx ST7263BE
14.10 Communication interface characteristics
14.10.1 USB - universal bus interface
(Operating conditions TA = 0 to +70°C, V = 4.0 to 5.25V unless otherwise specified)
DD
USB DC electrical characteristics
Symbol
Parameter
Conditions
I(D+, D-)
Min.
Max.
Unit
VDI
Differential Input Sensitivity
0.2
Differential Common mode
Range
VCM
VSE
VOL
Includes VDI range
0.8
0.8
2.5
2.0
0.3
Single Ended Receiver Threshold
2)
1)
V
RL of 1.5K ohms to
Static Output Low
3.6v
1)
RL of 15K ohms to
VOH
Static Output High
2.8
3.6
V
SS
3)
USBV
USBVCC: voltage level
V
=5v
3.00
3.60
DD
Notes:
1. RL is the load connected on the USB drivers.
2. All the voltages are measured from the local ground potential.
3. To improve EMC performance (noise immunity), it is recommended to connect a 100nF capacitor to the USBVCC pin.
Figure 72. USB: data signal rise and fall time
Differential
Data Lines
Crossover
points
VCRS
VSS
tr
tf
Table 27. USB: low-speed electrical characteristics
Symbol
Parameter
Conditions
Min
75
Max
Unit
Driver characteristics:
1)
CL=50 pF
ns
ns
ns
ns
%
tr
tf
Rise time
Fall Time
1)
CL=600 pF
300
1)
CL=50 pF
75
1)
CL=600 pF
300
120
trfm
Rise/ Fall Time matching tr/tf
80
Output signal Crossover
Voltage
VCRS
1.3
2.0
V
Note:
1. For more detailed information, please refer to Chapter 7 (Electrical) of the USB specification (version 1.1).
123/145
ST7263BDx ST7263BHx ST7263BKx ST7263BE
Communication interface characteristics (Cont’d)
14.10.2 SCI - serial communication interface
Subject to general operating condition for V , f
, and T unless otherwise specified.
A
DD CPU
Refer to I/O port characteristics for more details on the input/output alternate function characteristics (RDI
and TDO).
Conditions
Baud
Rate
Symbol
Parameter
Standard
Unit
Accuracy
vs. standard
Prescaler
f
CPU
Conventional mode
TR (or RR)=128, PR=13
TR (or RR)= 32, PR=13
TR (or RR)= 16, PR=13
TR (or RR)= 8, PR=13
TR (or RR)= 4, PR=13
TR (or RR)= 16, PR= 3
TR (or RR)= 2, PR=13
TR (or RR)= 1, PR=13
300
~300.48
1200 ~1201.92
2400 ~2403.84
4800 ~4807.69 Hz
9600 ~9615.38
10400 ~10416.67
19200 ~19230.77
38400 ~38461.54
f
Tx
Communication frequency 8MHz ~0.16%
f
Rx
2
14.10.3 I C - Inter IC control interface
Refer to I/O port characteristics for more details on the input/output alternate function characteristics
(SDAI and SCLI).
2
2
The ST7 I C interface meets the requirements of the Standard I C communication protocol described in
the following table.
(Subject to general operating conditions for V , f
, and T unless otherwise specified)
DD OSC
A
2
2
4)
Standard mode I C
Fast mode I C
Symbol
Parameter
Unit
1)
1)
1)
1)
Min
Max
Min
1.3
Max
t
SCL clock low time
SCL clock high time
SDA setup time
4.7
4.0
250
w(SCLL)
µs
t
0.6
w(SCLH)
t
100
su(SDA)
3)
2)
3)
t
SDA data hold time
0
0
900
h(SDA)
t
t
r(SDA)
ns
SDA and SCL rise time
SDA and SCL fall time
1000
300
20+0.1C
20+0.1C
300
300
b
b
r(SCL)
t
t
f(SDA)
f(SCL)
t
START condition hold time
4.0
4.7
4.0
4.7
0.6
0.6
0.6
1.3
h(STA)
µs
t
Repeated START condition setup time
STOP condition setup time
su(STA)
su(STO)
t
µs
µs
pF
t
STOP to START condition time (bus free)
Capacitive load for each bus line
w(STO:STA)
C
400
400
b
Notes:
2
1. Data based on standard I C protocol requirement, not tested in production.
2. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined
region of the falling edge of SCL.
3. The maximum hold time of the START condition has only to be met if the interface does not stretch the low period of
SCL signal.
2
2
4. At 4MHz f
, max.I C speed (400kHz) is not achievable. In this case, max. I C speed will be approximately 260KHz.
CPU
124/145
ST7263BDx ST7263BHx ST7263BKx ST7263BE
Communication interface characteristics (Cont’d)
2
Figure 73. Typical application with I C Bus and timing diagram 1)
V
V
DD
DD
4.7kΩ
4.7kΩ
100Ω
100Ω
SDAI
SCLI
2
I C BUS
ST72XXX
REPEATED START
START
t
t
w(STO:STA)
su(STA)
START
SDA
t
t
r(SDA)
f(SDA)
STOP
t
t
h(SDA)
su(SDA)
SCK
t
t
t
t
t
t
h(STA)
w(SCKH)
w(SCKL)
r(SCK)
su(STO)
f(SCK)
Note:
1. Measurement points are done at CMOS levels: 0.3xV and 0.7xV
.
DD
DD
The following table gives the values to be written in
2
the I2CCCR register to obtain the required I C
SCL line frequency .
Table 28. SCL frequency table
I2CCCR value
f
f
=4 MHz.
f
=8 MHz.
SCL
CPU
CPU
V
= 4.1 V
V
= 5 V
V
= 4.1 V
V
= 5 V
DD
(kHz)
DD
DD
DD
R =3.3kΩ R =4.7kΩ R =3.3kΩ R =4.7kΩ R =3.3kΩ R =4.7kΩ R =3.3kΩ R =4.7kΩ
P
P
P
P
P
P
P
P
400
300
200
100
50
NA
NA
NA
NA
NA
NA
NA
NA
83h
85h
8Ah
24h
4Ch
FFh
83
83h
85h
8Ah
24h
4Ch
FFh
83h
85h
8Ah
23h
4Ch
FFh
85h
89h
23h
4Ch
FFh
83h
10h
24h
5Fh
83h
10h
24h
5Fh
83h
10h
24h
5Fh
83h
10h
24h
5Fh
20
Legend:
R = External pull-up resistance
P
2
f
= I C speed
SCL
NA = Not achievable
Notes:
– For speeds around 200 kHz, achieved speed can have ±5% tolerance
– For other speed ranges, achieved speed can have ±2% tolerance
The above variations depend on the accuracy of the external components used.
125/145
ST7263BDx ST7263BHx ST7263BKx ST7263BE
14.11 8-bit ADC characteristics
Subject to general operating conditions for V , f
, and T unless otherwise specified.
DD OSC
A
1)
Symbol
Parameter
ADC clock frequency
Conversion range voltage
External input resistor
Conditions
Min
Typ
Max
Unit
MHz
V
f
4
ADC
2)
V
R
V
V
AIN
SSA
DDA
3)
10
kΩ
AIN
C
Internal sample and hold capacitor
Stabilization time after ADC enable
Conversion time (Sample+Hold)
6
pF
ADC
STAB
4)
t
0
µs
6
f
=8MHz, f
=2MHz
CPU
ADC
t
- Sample capacitor loading time
- Hold conversion time
4
8
ADC
1/f
ADC
Figure 74. Typical application with ADC
V
DD
V
T
0.6V
R
AIN
AINx
V
AIN
ADC
V
0.6V
T
C
~2pF
I
L
±1µA
IO
V
DD
V
V
DDA
SSA
0.1µF
ST72XXX
Notes:
1. Unless otherwise specified, typical data are based on T =25°C and V -V =5V.
A
DD SS
2. When V
and V
pins are not available on the pinout, the ADC refer to V and V
.
SS
DDA
SSA
DD
3. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10kΩ). Data
based on characterization results, not tested in production.
4. The stabilization time of the AD converter is masked by the first t
always valid.
. The first conversion after the enable is then
LOAD
126/145
ST7263BDx ST7263BHx ST7263BKx ST7263BE
8-bit ADC characteristics (Cont’d)
ADC accuracy with V =5V, f =8 MHz, f
=4 MHz R < 10kΩ
DD
CPU
ADC
AIN
2) 3)
Symbol
|E |
Parameter
Typ
1.5
0.5
0.5
1
Max
1)
2
Total unadjusted error
T
1)
1
|E
|E
Offset error
O|
G|
1)
1.5
1.5
1.5
Gain Error
1)
|E |
Differential linearity error
D
1)
1
|E |
Integral linearity error
L
Notes:
1. ADC Accuracy vs. Negative Injection Current:
For I =0.8mA, the typical leakage induced inside the die is 1.6µA and the effect on the ADC accuracy is a loss of 1 LSB
INJ-
for each 10KΩ increase of the external analog source impedance. This effect on the ADC accuracy has been observed
under worst-case conditions for injection:
- negative injection
- injection to an Input with analog capability, adjacent to the enabled Analog Input
- at 5V V supply, and worst case temperature.
DD
2. Data based on characterization results over the whole temperature range, not tested in production.
3. Data based on characterization results, to guarantee 99.73% within ± max value from 0°C to 70°C ( ± 3σ distribution
limits).
Figure 75. ADC accuracy characteristics
Digital Result ADCDR
E
G
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line
255
254
253
V
– V
DDA
SSA
1LSB
= ----------------------------------------
IDEAL
256
(2)
E =Total Unadjusted Error: maximum deviation
T
E
between the actual and the ideal transfer curves.
T
(3)
7
6
5
4
3
2
1
E =Offset Error: deviation between the first actual
O
transition and the first ideal one.
(1)
E =Gain Error: deviation between the last ideal
G
transition and the last actual one.
E
E
O
L
E =Differential Linearity Error: maximum deviation
D
between actual steps and the ideal one.
E =Integral Linearity Error: maximum deviation
L
E
between any actual transition and the end point
correlation line.
D
1 LSB
IDEAL
V
(LSB
)
IDEAL
in
0
1
2
3
4
5
6
7
253 254 255 256
V
V
DDA
SSA
127/145
ST7263BDx ST7263BHx ST7263BKx ST7263BE
15 Package characteristics
In order to meet environmental requirements, ST
offers these devices in ECOPACK® packages.
These packages have a Lead-free second level in-
terconnect. The category of second Level Inter-
connect is marked on the package and on the in-
ner box label, in compliance with JEDEC Standard
JESD97. The maximum ratings related to solder-
ing conditions are also marked on the inner box la-
bel.
ECOPACK is an ST trademark. ECOPACK speci-
fications are available at: www.st.com
15.1 Package mechanical data
Figure 76. 34-pin Plastic Small Outline Package, shrink 300-mil width
mm
inches
Dim.
Min Typ Max Min Typ Max
h x 45×
L
A
2.464
2.642 0.097
0.292 0.005
0.483 0.014
0.318 0.009
0.104
0.012
0.019
0.013
A
C
A1
A1 0.127
a
B
C
0.356
0.231
e
B
D
17.72
9
18.05
0.698
9
D
0.711
0.299
E
e
7.417
7.595 0.292
1.016
0.040
10.16
0
10.41
0.400
4
H
0.410
E
H
h
α
L
0.635
0°
0.737 0.025
0.029
8°
8°
0°
0.610
1.016 0.024
0.040
Number of Pins
N
34
128/145
ST7263BDx ST7263BHx ST7263BKx ST7263BE
Figure 77. 32-pin Plastic Dual In-Line Package, shrink 400-mil width
mm
inches
Dim.
Min Typ Max Min Typ Max
E
eC
A
3.56 3.76 5.08 0.140 0.148 0.200
A1 0.51
A2 3.05 3.56 4.57 0.120 0.140 0.180
0.36 0.46 0.58 0.014 0.018 0.023
b1 0.76 1.02 1.40 0.030 0.040 0.055
0.020
A2
A
L
b
A1
E1
C
eA
eB
C
D
E
0.20 0.25 0.36 0.008 0.010 0.014
27.43 28.45 1.080 1.100 1.120
9.91 10.41 11.05 0.390 0.410 0.435
b
b2
e
D
E1 7.62 8.89 9.40 0.300 0.350 0.370
e
1.78
0.070
0.400
eA
eB
eC
L
10.16
12.70
1.40
0.500
0.055
2.54 3.05 3.81 0.100 0.120 0.150
Number of Pins
N
32
Figure 78. 24-pin Plastic Small Outline Package, 300-mil width
mm
inches
Dim.
A
D
Min Typ Max Min Typ Max
h x 45×
L
2.35
2.65 0.093
0.30 0.004
0.51 0.013
0.32 0.009
15.60 0.599
7.60 0.291
0.104
0.012
0.020
0.013
0.614
0.299
A
A1 0.10
A1
C
B
C
D
E
e
0.33
0.23
a
e
B
15.20
7.40
1.27
0.050
H
h
α
L
10.00
0.25
0°
10.65 0.394
0.75 0.010
0.419
0.030
8°
E
H
8°
0°
0.40
1.27 0.016
0.050
Number of Pins
N
24
129/145
ST7263BDx ST7263BHx ST7263BKx ST7263BE
Figure 79. 48-pin Low profile Quad Flat package
1)
mm
inches
Dim.
Min Typ Max Min Typ Max
D
A
A
1.60
0.063
0.006
D1
A2
A1 0.05
0.15 0.002
A2 1.35 1.40 1.45 0.053 0.055 0.057
A1
b
b
C
0.17 0.22 0.27 0.007 0.009 0.011
0.09 0.20 0.004 0.008
D
9.00
7.00
9.00
7.00
0.50
3.5°
0.354
0.276
0.354
0.276
0.020
3.5°
D1
E
e
E1
E
E1
e
θ
0°
7°
0°
7°
c
L1
L
0.45 0.60 0.75 0.018 0.024 0.030
1.00 0.039
Number of Pins
48
L
θ
L1
N
Note 1. values in inches are converted from
mm and rounded to 3 decimal digits.
Figure 80. 40-lead Very thin Fine pitch Quad Flat No-Lead Package
A
SEATING
1)
A3
mm
inches
PLANE
Dim.
A1
Min Typ Max Min Typ Max
D
A
A1
A2
A3
b
0.80 0.90 1.00 0.031 0.035 0.039
0.02 0.05
0.65 1.00
0.20
0.001 0.002
0.026 0.039
0.008
0.18 0.25 0.30 0.007 0.010 0.012
5.85 6.00 6.15 0.230 0.236 0.242
2.75 2.9 3.05 0.108 0.114 0.120
D
D2
D2
E
5.85
2.75 2.9 3.05 0.108 0.114 0.120
0.50 0.020
6
6.15 0.230 0.236 0.242
E2
E
E2
e
PIN #1 ID TYPE C
RADIUS
L
0.30 0.40 0.50 0.012 0.016 0.020
2
1
Number of Pins
N
40
Note 1. values in inches are converted from mm
and rounded to 3 decimal digits.
L
e
b
130/145
ST7263BDx ST7263BHx ST7263BKx ST7263BE
15.2 Thermal characteristics
Symbol
Ratings
value
Unit
Package thermal resistance (junction to ambient)
SDIP32
60
75
70
80
34
SO34
SO24
LQFP48
QFN40
R
°C/W
thJA
1)
P
Power dissipation
Maximum junction temperature
500
150
mW
°C
D
2)
T
Jmax
Notes:
1. The power dissipation is obtained from the formula P =P +P
where P
is the chip internal power (I xV
)
D
INT
PORT
INT
DD DD
and P
is the port power dissipation determined by the user.
PORT
2. The average chip-junction temperature can be obtained from the formula T = T + P x RthJA.
J
A
D
131/145
ST7263BDx ST7263BHx ST7263BKx ST7263BE
15.3 Soldering and glueability information
Recommended soldering information given only
as design guidelines in Figure 81 and Figure 82.
Recommended glue for SMD plastic packages
dedicated to molding compound with silicone:
■ Heraeus: PD945, PD955
■ Loctite: 3615, 3298
Figure 81. Recommended wave soldering profile (with 37% Sn and 63% Pb)
250
COOLING PHASE
(ROOM TEMPERATURE)
5 sec
200
150
100
50
SOLDERING
PHASE
80°C
Temp. [°C]
PREHEATING
PHASE
Time [sec]
0
20
40
60
80
100
120
140
160
Figure 82. Recommended reflow soldering oven profile (MID JEDEC)
250
Tmax=220+/-5°C
for 25 sec
200
150
100
50
150 sec above 183°C
90 sec at 125°C
Temp. [°C]
ramp down natural
2°C/sec max
ramp up
2°C/sec for 50sec
Time [sec]
0
100
200
300
400
132/145
ST7263BDx ST7263BHx ST7263BKx ST7263BE
16 Device configuration and ordering information
Each device is available for production in user pro-
grammable versions (High Density FLASH) as
well as in factory coded versions (FASTROM).
1: Reset generation when entering Halt mode
OPT 3 = LVD Low Voltage Detector selection
This option bit selects the LVD.
0: LVD enabled
ST72P63B devices are Factory Advanced Service
Technique ROM (FASTROM) versions: they are
factory programmed FLASH devices.
1: LVD disabled
ST72F63B FLASH devices are shipped to custom-
ers with a default content (FFh).
Important note: on 4K and 8K ROM devices listed
below, this option bit is forced by ST to 0 (LVD
always enabled):
ST7263BK1M1, ST7263BK2M1
ST7263BK2B1, ST7263BK2B1
This implies that FLASH devices have to be con-
figured by the customer using the Option Byte
while the ROM devices are factory-configured.
OPT 2 = Reserved.
16.1 Option Byte
The Option Byte allows the hardware configuration
of the microcontroller to be selected.
OPT 1 = OSC24/12 Oscillator Selection
This option bit selects the clock divider used to
drive the USB interface at 6MHz.
0: 24 MHz oscillator
The Option Byte has no address in the memory
map and can be accessed only in programming
mode using a standard ST7 programming tool.
The default contents of the FLASH is fixed to F7h.
This means that all the options have “1” as their
default value, except LVD.
1: 12 Mhz oscillator
OPT 0 = FMP_R Flash memory Read-Out protec-
In ROM devices, the Option Byte is fixed in hard-
ware by the ROM code.
tion
This option indicates if the user flash memory is
protected against Read-Out. Read-Out protection,
when selected, provides a protection against Pro-
gram Memory content extraction and against write
access to Flash memory. Erasing the option bytes
when the FMP_R option is selected, causes the
whole user memory to be erased first and the de-
vice can be reprogrammed. Refer to the ST7 Flash
Programming Reference Manual and section 4.2.1
on page 17 for more details.
Option Byte
7
0
WDG WD
SW HALT
OSC FMP_
--
--
LVD
--
24/12
R
OPT 7:6 = Reserved.
0: Read-Out protection enabled
1: Read-Out protection disabled
OPT 5 = WDGSW Hardware or Software Watch-
dog
This option bit selects the watchdog type.
0: Hardware enabled
1: Software enabled
OPT 4 = WDHALT Watchdog and Halt mode
This option bit determines if a RESET is generated
when entering Halt mode while the Watchdog is
active.
0: No Reset generation when entering Halt mode
133/145
ST7263BDx ST7263BHx ST7263BKx ST7263BE
16.2 Device ordering information and transfer of customer code
Customer code is made up of the FASTROM con-
tents and the list of the selected options (if any).
The FASTROM contents are to be sent on dis-
kette, or by electronic means, with the hexadeci-
mal file in .S19 format generated by the develop-
ment tool. All unused bytes must be set to FFh.
Refer to application note AN1635 for information
on the counter listing returned by ST after code
has been transferred.
The STMicroelectronics Sales Organization will be
pleased to provide detailed information on con-
tractual points.
The selected options are communicated to STMi-
croelectronics using the correctly completed OP-
TION LIST appended. See page 138.
134/145
ST7263BDx ST7263BHx ST7263BKx ST7263BE
Table 29. Supported part numbers
Program memory
RAM
(bytes)
1)
Sales Type
Package
(bytes)
ST72F63BH6T1
ST72F63BD6U1
ST72F63BK6M1
ST72F63BK6B1
ST72F63BE6M1
ST72F63BH4T1
ST72F63BK4M1
ST72F63BK4B1
ST72F63BE4M1
ST72F63BH2T1
ST72F63BK2U1
ST72F63BK2M1
ST72F63BK2B1
ST72F63BE2M1
ST72F63BK1M1
ST72F63BK1B1
ST72F63BE1M1
ST7263BH6T1/xxx
ST7263BD6U1/xxx
ST7263BK6M1/xxx
ST7263BK6B1/xxx
ST7263BE6M1/xxx
ST7263BH4T1/xxx
ST7263BK4M1/xxx
ST7263BK4B1/xxx
ST7263BE4M1/xxx
ST7263BH2T1/xxx
ST7263BK2U1/xxx
ST7263BK2M1/xxx
ST7263BK2B1/xxx
ST7263BE2M1/xxx
ST7263BK1M1/xxx
ST7263BK1B1/xxx
ST7263BE1M1/xxx
ST72P63BH6T1
ST72P63BD6U1
ST72P63BK6M1
ST72P63BK6B1
ST72P63BE6M1
ST72P63BH4T1
ST72P63BK4M1
ST72P63BK4B1
ST72P63BE4M1
LQFP48
QFN40
SO34
32K Flash
1024
512
SDIP32
SO24
LQFP48
SO34
16K Flash
SDIP32
SO24
LQFP48
QFN40
SO34
8K Flash
4K Flash
32K ROM
384
384
SDIP32
SO24
SO34
SDIP32
SO24
LQFP48
QFN40
SO34
1024
SDIP32
SO24
LQFP48
SO34
16K ROM
512
SDIP32
SO24
LQFP48
QFN40
SO34
8K ROM
4K ROM
384
384
SDIP32
SO24
SO34
SDIP32
SO24
LQFP48
QFN40
SO34
32K FASTROM
1024
SDIP32
SO24
LQFP48
SO34
16K FASTROM
512
SDIP32
SO24
135/145
ST7263BDx ST7263BHx ST7263BKx ST7263BE
ST72P63BH2T1
ST72P63BK2U1
LQFP48
QFN40
SO34
ST72P63BK2M1
ST72P63BK2B1
ST72P63BE2M1
ST72P63BK1M1
ST72P63BK1B1
ST72P63BE1M1
8K FASTROM
4K FASTROM
384
384
SDIP32
SO24
SO34
SDIP32
SO24
Note:
Contact ST sales office for product availability
1. /xxx stands for the ROM code name assigned by STMicroelectronics
136/145
ST7263BDx ST7263BHx ST7263BKx ST7263BE
16.3 Development tools
Development tools for the ST7 microcontrollers in-
clude a complete range of hardware systems and
software tools from STMicroelectronics and third-
party tool suppliers. The range of tools includes
solutions to help you evaluate microcontroller pe-
ripherals, develop and debug your application, and
program your microcontrollers.
fine-tuning of your application. The Cosmic C
Compiler is available in a free version that outputs
up to 16K of code.
The range of hardware tools includes full-featured
ST7-EMU3 series emulators and the low-cost
RLink in-circuit debugger/programmer. These
tools are supported by the ST7 Toolset from
STMicroelectronics, which includes the STVD7 in-
tegrated development environment (IDE) with
high-level language debugger, editor, project man-
ager and integrated programming interface.
16.3.1 Evaluation tools and starter kits
ST offers complete, affordable starter kits and
full-featured evaluation boards that allow you to
evaluate microcontroller features and quickly start
developing ST7 applications. Starter kits are com-
plete, affordable hardware/software tool packages
that include features and samples to to help you
quickly start developing your application. ST eval-
uation boards are open-design, embedded sys-
tems, which are developed and documented to
serve as references for your application design.
They include sample application software to help
you demonstrate, learn about and implement your
ST7’s features.
16.3.3 Programming tools
During the development cycle, the ST7-EMU3 se-
ries emulators and the RLink provide in-circuit
programming capability for programming the Flash
microcontroller on your application board.
In addition ST provides dedicated programming
tools including the ST7-EPB programming
boards, which include all the sockets required to
program any of the devices in a specific ST7 sub-
family.
16.3.2 Development and debugging tools
For production programming of ST7 devices, ST’s
third-party tool partners also provide a complete
range of gang and automated programming solu-
tions, which are ready to integrate into your pro-
duction environment.
Application development for ST7 is supported by
fully optimizing C Compilers and the ST7 Assem-
bler-Linker toolchain, which are all seamlessly in-
tegrated in the ST7 integrated development envi-
ronments in order to facilitate the debugging and
16.3.4 Order codes for ST7263B development tools
Table 30. Development tool order codes for the ST7263B family
In-circuit debugger/
programmer
Dedicated
programmer
MCU
Starter kit
Evaluation board
Emulator
ST72F63B-SK/
RAIS
ST7MDTULS-
EVAL
ST7263B
ST7MDTU3-EMU3
STX-RLINK
ST7MDTU3-EPB
For additional ordering codes for spare parts and
accessories, refer to the online product selector at
www.st.com.
137/145
ST7263BDx ST7263BHx ST7263BKx ST7263BE
ST7263B microcontroller option list
(Last update: Mar 2007)
Customer:
Address:
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact:
Phone No:
Reference:
ROM or FASTROM code must be sent in .S19 format.
Hex extension cannot be processed.
STMicroelectronics references:
Device Type/Memory Size/Package (check only one option):
-----------------------------------------------------------------------------------------------------------------------------------------------------------
ROM DEVICE: |
4K
|
8K
|
16K
|
32K
|
-----------------------------------------------------------------------------------------------------------------------------------------------------------
SO24:
PSDIP32:
SO34:
| [ ] ST7263BE1M1
| [ ] ST7263BK1B1
| [ ] ST7263BE2M1 | [ ] ST7263BE4B1 | [ ] ST7263BE6M1
| [ ] ST7263BK2B1 | [ ] ST7263BK4B1 | [ ] ST7263BK6B1
|
|
|
|
|
| [ ] ST7263BK1M1 | [ ] ST7263BK2M1 | [ ] ST7263BK4M1 | [ ] ST7263BK6M1
QFN40:
LQFP48:
|
|
| [ ] ST7263BK2U1
| [ ] ST7263BH2T1 | [ ] ST7263BH4T1 | [ ] ST7263BH6T1
|
| [ ] ST7263BD6U1
-----------------------------------------------------------------------------------------------------------------------------------------------------------
FASTROM: 4K 8K 16K 32K
-----------------------------------------------------------------------------------------------------------------------------------------------------------
|
|
|
|
|
SO24:
PSDIP32:
SO34:
QFN40:
LQFP48:
| [ ] ST72P63BE1M1 | [ ] ST72P63BE2M1 | [ ] ST72P63BE4M1 | [ ] ST72P63BE6M1
| [ ] ST72P63BK1B1 | [ ] ST72P63BK2B1 | [ ] ST72P63BK4B1 | [ ] ST72P63BK6B1
| [ ] ST72P63BK1M1 | [ ] ST72P63BK2M1 | [ ] ST72P63BK4M1 | [ ] ST72P63BK6M1
|
|
|
|
|
|
|
| [ ] ST72P63BK2U1 |
| [ ] ST72P63BD6U1
| [ ] ST72P63BH2T1 | [ ] ST72P63BH4T1 | [ ] ST72P63BH6T1
-----------------------------------------------------------------------------------------------------------------------------------------------------------
DIE FORM: 4K 8K 16K 32K
|
|
|
|
|
-----------------------------------------------------------------------------------------------------------------------------------------------------------
24-pin:
32-pin:
34-pin:
40-pin:
48-pin:
| [ ] (as E1M1)
| [ ] (as E2M1)
| [ ] (as K2B1)
| [ ] (as K2M1)
| [ ] (as E4M1)
| [ ] (as K4B1)
| [ ] (as K4M1)
|
| [ ] (as E6M1)
| [ ] (as K6B1)
| [ ] (as K6M1)
| [ ] (as D6U1)
| [ ] (as H6T1)
|
|
|
|
|
| [ ] (as K1B1)
| [ ] (as K1M1)
|
|
|
[ ] (as K2U1)
| [ ] (as H2T1)
| [ ] (as H4T1)
Conditioning (check only one option):
Packaged Product
|
Die Product (dice tested at 25°C only)
------------------------------------------------------------------------------------------------------------------------
[ ] Tape & Reel (SO package only)
[ ] Tube
|
|
|
[ ] Tape & Reel
[ ] Inked wafer
[ ] Sawn wafer on sticky foil
Special Marking ( ROM only): [ ] No
[ ] Yes "_ _ _ _ _ _ _ _ _ _ _ _ _"
Authorized characters are letters, digits, '.', '-', '/' and spaces only.
For marking, one line is possible with a maximum of 13 characters.
Watchdog Selection:
[ ] Software activation [ ] Hardware activation
Halt when Watchdog on: [ ] Reset
[ ] No reset
[ ] Enabled*
LVD Reset *
[ ] Disabled*
* LVD is forced to 0 (LVD always enabled) for 4K and 8K ROM devices
(sales types ST7263BK1B1, ST7263BK2B1, ST7263BK1M1, ST72BK2M1 only)
Oscillator Selection:
Read-Out Protection:
[ ] 24 MHz.
[ ] Disabled
[ ] 12 MHz.
[ ] Enabled
Date
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signature
Please download the latest version of this option list from: http://www.st.com
138/145
ST7263BDx ST7263BHx ST7263BKx ST7263BE
16.4 ST7 application notes
Table 31. ST7 application notes
IDENTIFICATION DESCRIPTION
APPLICATION EXAMPLES
AN1658
AN1720
AN1755
AN1756
SERIAL NUMBERING IMPLEMENTATION
MANAGING THE READ-OUT PROTECTION IN FLASH MICROCONTROLLERS
A HIGH RESOLUTION/PRECISION THERMOMETER USING ST7 AND NE555
CHOOSING A DALI IMPLEMENTATION STRATEGY WITH ST7DALI
A HIGH PRECISION, LOW COST, SINGLE SUPPLY ADC FOR POSITIVE AND NEGATIVE IN-
PUT VOLTAGES
AN1812
EXAMPLE DRIVERS
SCI COMMUNICATION BETWEEN ST7 AND PC
AN 969
AN 970
AN 971
AN 972
AN 973
AN 974
AN 976
AN 979
AN 980
AN1017
AN1041
AN1042
AN1044
AN1045
AN1046
AN1047
AN1048
AN1078
AN1082
AN1083
AN1105
AN1129
SPI COMMUNICATION BETWEEN ST7 AND EEPROM
I²C COMMUNICATION BETWEEN ST7 AND M24CXX EEPROM
ST7 SOFTWARE SPI MASTER COMMUNICATION
SCI SOFTWARE COMMUNICATION WITH A PC USING ST72251 16-BIT TIMER
REAL TIME CLOCK WITH ST7 TIMER OUTPUT COMPARE
DRIVING A BUZZER THROUGH ST7 TIMER PWM FUNCTION
DRIVING AN ANALOG KEYBOARD WITH THE ST7 ADC
ST7 KEYPAD DECODING TECHNIQUES, IMPLEMENTING WAKE-UP ON KEYSTROKE
USING THE ST7 UNIVERSAL SERIAL BUS MICROCONTROLLER
USING ST7 PWM SIGNAL TO GENERATE ANALOG OUTPUT (SINUSOÏD)
ST7 ROUTINE FOR I²C SLAVE MODE MANAGEMENT
MULTIPLE INTERRUPT SOURCES MANAGEMENT FOR ST7 MCUS
ST7 S/W IMPLEMENTATION OF I²C BUS MASTER
UART EMULATION SOFTWARE
MANAGING RECEPTION ERRORS WITH THE ST7 SCI PERIPHERALS
ST7 SOFTWARE LCD DRIVER
PWM DUTY CYCLE SWITCH IMPLEMENTING TRUE 0% & 100% DUTY CYCLE
DESCRIPTION OF THE ST72141 MOTOR CONTROL PERIPHERALS REGISTERS
ST72141 BLDC MOTOR CONTROL SOFTWARE AND FLOWCHART EXAMPLE
ST7 PCAN PERIPHERAL DRIVER
PWM MANAGEMENT FOR BLDC MOTOR DRIVES USING THE ST72141
AN INTRODUCTION TO SENSORLESS BRUSHLESS DC MOTOR DRIVE APPLICATIONS
WITH THE ST72141
AN1130
AN1148
AN1149
AN1180
AN1276
AN1321
AN1325
AN1445
AN1475
AN1504
AN1602
AN1633
AN1712
AN1713
AN1753
USING THE ST7263 FOR DESIGNING A USB MOUSE
HANDLING SUSPEND MODE ON A USB MOUSE
USING THE ST7263 KIT TO IMPLEMENT A USB GAME PAD
BLDC MOTOR START ROUTINE FOR THE ST72141 MICROCONTROLLER
USING THE ST72141 MOTOR CONTROL MCU IN SENSOR MODE
USING THE ST7 USB LOW-SPEED FIRMWARE V4.X
EMULATED 16-BIT SLAVE SPI
DEVELOPING AN ST7265X MASS STORAGE APPLICATION
STARTING A PWM SIGNAL DIRECTLY AT HIGH LEVEL USING THE ST7 16-BIT TIMER
16-BIT TIMING OPERATIONS USING ST7262 OR ST7263B ST7 USB MCUS
DEVICE FIRMWARE UPGRADE (DFU) IMPLEMENTATION IN ST7 NON-USB APPLICATIONS
GENERATING A HIGH RESOLUTION SINEWAVE USING ST7 PWMART
SMBUS SLAVE DRIVER FOR ST7 I2C PERIPHERALS
SOFTWARE UART USING 12-BIT ART
139/145
ST7263BDx ST7263BHx ST7263BKx ST7263BE
Table 31. ST7 application notes
IDENTIFICATION DESCRIPTION
AN1947
ST7MC PMAC SINE WAVE MOTOR CONTROL SOFTWARE LIBRARY
GENERAL PURPOSE
AN1476
AN1526
AN1709
AN1752
LOW COST POWER SUPPLY FOR HOME APPLIANCES
ST7FLITE0 QUICK REFERENCE NOTE
EMC DESIGN FOR ST MICROCONTROLLERS
ST72324 QUICK REFERENCE NOTE
PRODUCT EVALUATION
AN 910
AN 990
AN1077
AN1086
AN1103
AN1150
AN1151
AN1278
PERFORMANCE BENCHMARKING
ST7 BENEFITS VS INDUSTRY STANDARD
OVERVIEW OF ENHANCED CAN CONTROLLERS FOR ST7 AND ST9 MCUS
U435 CAN-DO SOLUTIONS FOR CAR MULTIPLEXING
IMPROVED B-EMF DETECTION FOR LOW SPEED, LOW VOLTAGE WITH ST72141
BENCHMARK ST72 VS PC16
PERFORMANCE COMPARISON BETWEEN ST72254 & PC16F876
LIN (LOCAL INTERCONNECT NETWORK) SOLUTIONS
PRODUCT MIGRATION
AN1131
AN1322
AN1365
AN1604
AN2200
MIGRATING APPLICATIONS FROM ST72511/311/214/124 TO ST72521/321/324
MIGRATING AN APPLICATION FROM ST7263 REV.B TO ST7263B
GUIDELINES FOR MIGRATING ST72C254 APPLICATIONS TO ST72F264
HOW TO USE ST7MDT1-TRAIN WITH ST72F264
GUIDELINES FOR MIGRATING ST7LITE1X APPLICATIONS TO ST7FLITE1XB
PRODUCT OPTIMIZATION
AN 982
AN1014
AN1015
AN1040
AN1070
AN1181
AN1324
AN1502
AN1529
USING ST7 WITH CERAMIC RESONATOR
HOW TO MINIMIZE THE ST7 POWER CONSUMPTION
SOFTWARE TECHNIQUES FOR IMPROVING MICROCONTROLLER EMC PERFORMANCE
MONITORING THE VBUS SIGNAL FOR USB SELF-POWERED DEVICES
ST7 CHECKSUM SELF-CHECKING CAPABILITY
ELECTROSTATIC DISCHARGE SENSITIVE MEASUREMENT
CALIBRATING THE RC OSCILLATOR OF THE ST7FLITE0 MCU USING THE MAINS
EMULATED DATA EEPROM WITH ST7 HDFLASH MEMORY
EXTENDING THE CURRENT & VOLTAGE CAPABILITY ON THE ST7265 VDDF SUPPLY
ACCURATE TIMEBASE FOR LOW-COST ST7 APPLICATIONS WITH INTERNAL RC OSCILLA-
TOR
AN1530
AN1605
AN1636
AN1828
AN1946
AN1953
AN1971
USING AN ACTIVE RC TO WAKEUP THE ST7LITE0 FROM POWER SAVING MODE
UNDERSTANDING AND MINIMIZING ADC CONVERSION ERRORS
PIR (PASSIVE INFRARED) DETECTOR USING THE ST7FLITE05/09/SUPERLITE
SENSORLESS BLDC MOTOR CONTROL AND BEMF SAMPLING METHODS WITH ST7MC
PFC FOR ST7MC STARTER KIT
ST7LITE0 MICROCONTROLLED BALLAST
PROGRAMMING AND TOOLS
AN 978
AN 983
AN 985
AN 986
AN 987
AN 988
AN1039
ST7 VISUAL DEVELOP SOFTWARE KEY DEBUGGING FEATURES
KEY FEATURES OF THE COSMIC ST7 C-COMPILER PACKAGE
EXECUTING CODE IN ST7 RAM
USING THE INDIRECT ADDRESSING MODE WITH ST7
ST7 SERIAL TEST CONTROLLER PROGRAMMING
STARTING WITH ST7 ASSEMBLY TOOL CHAIN
ST7 MATH UTILITY ROUTINES
140/145
ST7263BDx ST7263BHx ST7263BKx ST7263BE
Table 31. ST7 application notes
IDENTIFICATION DESCRIPTION
AN1071
AN1106
HALF DUPLEX USB-TO-SERIAL BRIDGE USING THE ST72611 USB MICROCONTROLLER
TRANSLATING ASSEMBLY CODE FROM HC05 TO ST7
PROGRAMMING ST7 FLASH MICROCONTROLLERS IN REMOTE ISP MODE (IN-SITU PRO-
GRAMMING)
AN1179
AN1446
AN1477
AN1527
AN1575
AN1576
AN1577
AN1601
AN1603
AN1635
AN1754
AN1796
AN1900
AN1904
AN1905
USING THE ST72521 EMULATOR TO DEBUG AN ST72324 TARGET APPLICATION
EMULATED DATA EEPROM WITH XFLASH MEMORY
DEVELOPING A USB SMARTCARD READER WITH ST7SCR
ON-BOARD PROGRAMMING METHODS FOR XFLASH AND HDFLASH ST7 MCUS
IN-APPLICATION PROGRAMMING (IAP) DRIVERS FOR ST7 HDFLASH OR XFLASH MCUS
DEVICE FIRMWARE UPGRADE (DFU) IMPLEMENTATION FOR ST7 USB APPLICATIONS
SOFTWARE IMPLEMENTATION FOR ST7DALI-EVAL
USING THE ST7 USB DEVICE FIRMWARE UPGRADE DEVELOPMENT KIT (DFU-DK)
ST7 CUSTOMER ROM CODE RELEASE INFORMATION
DATA LOGGING PROGRAM FOR TESTING ST7 APPLICATIONS VIA ICC
FIELD UPDATES FOR FLASH BASED ST7 APPLICATIONS USING A PC COMM PORT
HARDWARE IMPLEMENTATION FOR ST7DALI-EVAL
ST7MC THREE-PHASE AC INDUCTION MOTOR CONTROL SOFTWARE LIBRARY
ST7MC THREE-PHASE BLDC MOTOR CONTROL SOFTWARE LIBRARY
SYSTEM OPTIMIZATION
AN1711
AN1827
AN2009
AN2030
SOFTWARE TECHNIQUES FOR COMPENSATING ST7 ADC ERRORS
IMPLEMENTATION OF SIGMA-DELTA ADC WITH ST7FLITE05/09
PWM MANAGEMENT FOR 3-PHASE BLDC MOTOR DRIVES USING THE ST7FMC
BACK EMF DETECTION DURING PWM ON TIME BY ST7MC
141/145
ST7263BDx ST7263BHx ST7263BKx ST7263BE
17 Known limitations
17.1 PA2 limitation with OCMP1 enabled
Description
On reception of the NACK, ST7 can send a re-start
and Slave address to re-initiate communication
This limitation affects only Rev B Flash devices
(with Internal Sales Type 72F63Bxxxxx$x7); it has
been corrected in Rev W Flash devices (with Inter-
nal Sales Type 72F63Bxxxxx$x9).
17.5 Halt mode power consumption with ADC
on
Description
Note: Refer to Figure 83 on page 143
If the A/D converter is being used when Halt mode
is entered, the power consumption in Halt mode
may exceed the maximum specified in the datash-
eet.
When Output Compare 1 function (OCMP1) on pin
PA6 is enabled by setting the OC1E bit in the
TCR2 register, pin PA2 is also affected.
Workaround
In particular, PA2 is switched to its alternate func-
tion mode, SCL. As a consequence, the PA2 pin is
forced to be floating (steady level of I C clock)
Switch off the ADC by software (ADON=0) before
executing a HALT instruction.
2
even if port configuration (PADDR+PADR) has set
it as output low. However, it can be still used as an
2
17.6 SCI wrong break duration
Description
input or can be controlled by the I C cell when en-
2
abled (where I C is available).
A single break character is sent by setting and re-
setting the SBK bit in the SCICR2 register. In
some cases, the break character may have a long-
er duration than expected:
17.2 Unexpected reset fetch
Description
If an interrupt request occurs while a "POP CC" in-
struction is executed, the interrupt controller does
not recognise the source of the interrupt and, by
default, passes the RESET vector address to the
CPU.
- 20 bits instead of 10 bits if M=0
- 22 bits instead of 11 bits if M=1.
In the same way, as long as the SBK bit is set,
break characters are sent to the TDO pin. This
may generate one break more than expected.
Workaround
Occurrence
To solve this issue, a "POP CC" instruction must
always be preceded by a "SIM" instruction.
The occurrence of the problem is random and pro-
portional to the baudrate. With a transmit frequen-
cy of 19200 baud (fCPU=8MHz and SCI-
BRR=0xC9), the wrong break duration occurrence
is around 1%.
17.3 USB behavior with LVD disabled
Description
Workaround
On 4K and 8K ROM devices (ST7263BK1M1,
ST72BK2M1, ST7263BKB1, ST7263BK2B1 only)
if the LVD is disabled, the USB is disabled by hard-
ware. So, the LVD is forced by ST to 0 (LVD ena-
bled). Refer to the ST7263B option list for details.
If this wrong duration is not compliant with the
communication protocol in the application, soft-
ware can request that an Idle line be generated
before the break character. In this case, the break
duration is always correct assuming the applica-
tion is not doing anything between the idle and the
break. This can be ensured by temporarily disa-
bling interrupts.
17.4 I2C multimaster
Description
In multimaster configurations, if the ST7 I2C re-
ceives a START condition from another I2C mas-
ter after the START bit is set in the I2CCR register
and before the START condition is generated by
the ST7 I2C, it may ignore the START condition
from the other I2C master. In this case, the ST7
master will receive a NACK from the other device.
The exact sequence is:
- Disable interrupts
- Reset and Set TE (IDLE request)
- Set and Reset SBK (Break Request)
- Re-enable interrupts
142/145
ST7263BDx ST7263BHx ST7263BKx ST7263BE
Figure 83. Identifying silicon revision from device marking and box label
The silicon revision can be identified either by Rev letter or obtained via a trace code.
Follow the procedure below:
1. Identify the silicon revision letter from either the device package or the box label.
For example, “B”, etc.
2. If the revision letter is not present, obtain the silicon revision by contacting your local ST
office with the trace code information printed on either the box label or the device package.
Silicon Rev
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
Trace code
ST7xxxxxxxxx
TYPE
xxxxxxxxxxx$x7
XX
Total Qty
XXXXXXXXX XX XX
Trace code
Marking
Bulk ID
XXXXXXXXXX
B
Silicon Rev
XXXXXXXXXXXX
Device package (SO34 shown)
Example box label
143/145
ST7263BDx ST7263BHx ST7263BKx ST7263BE
18 Revision history
Date
Revision
Main changes
New revision created by merging 32K Flash and non-32K Flash datasheets together
Memory Map, Figure 7, expanded to handle all devices and memory sizes
Operating conditions with LVD values modified, section 14.3.2 on page 110
Supply current characteristics values and notes updated, section 14.4 on page 111
IDD Run and Wait graphs replaced, Figure 52 and Figure 53 on page 111
Control timing characteristics modified, section 14.5.2 on page 112
Flash memory table notes and t
typical value updated, section 14.6.2 on page 114
PROG
Notes added for I/O Port Pin characteristics table, section 14.8.1 on page 117
Note for R modified, removing reference to data characterization, Section 14.8.1
PU
I
and R graphs added, Figure 58 and Figure 59 on page 118
PU
PU
Notes updated for USB low speed electrical characteristics
Output voltage/current graphs added, Figures 60-69
27-May-05
3.0
Thermal Characteristics added for SO24 and TQFP48 packages, section 15.2 on page 131
Important note added for OPT 3 Option Byte (LVD), section 16.1 on page 133
Supported Part Numbers table updated with full sales type codes, Table 29
Option List updated with all device options, page 138
Important notes updated with ‘USB behavior with LVD disabled’, section 17.3 on page 142
Clock block diagram redrawn, Figure 18 on page 26
DFU added to title and features list, page 1
Removed unnecessary notes related to Typical values (already mentioned in section 14.1.2
on page 108) in electrical characteristic tables sections: Section 14.3.2, Section 14.4, Sec-
tion 14.6.2, Section 14.8.1, Section 14.9.1 and Section 14.11
Added note for max values in ADC Accuracy, Section 14.11
Static Latch Up (LU) class tested only for T =25°C, section 14.7.3.2 on page 116
A
Flash memory minimum data retention increased to 40 years, section 14.6.2 on page 114
AF bit text modified concerning SCL, I2C Chapter Section 12.5.7, "Register description"
Reference made to the Flash Programming Reference Manual for Flash timing values
Reset pulse generated by WDG changed to 30µs, section 12.1 on page 42
Modified text in section 12.3 on page 64, adding Parity error as an interrupt
Added ECOPACK information in section 15 on page 128
19-Sep-05
4.0
Modified I value and corresponding note in section 14.8.1 on page 117
S
32K and 8K QFN40 Packages added
4K SO24 Package added
TQFP package renamed to LQFP
06-Apr-06
03-Oct-06
5.0
6.0
Important Notes section renamed to Known Limitations, section 17 on page 142
New PA2 limitation added, section 17 on page 142
Figure 83. on page 143 added for silicon revision identification
Root part numbers added in datasheet header and in Table 1, "Device summary".
New 16K LQFP48 package added to product family.
Note added to V data in section 14.8.2 on page 118
List of supported partnumber availability updated, Table 29, "Supported part numbers"
OH
20-Aug-07
7.0
Download address updated in Section 16.3.4, "Order codes for ST7263B development
tools" and Option list.
144/145
ST7263BDx ST7263BHx ST7263BKx ST7263BE
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
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