ST7265AR4M1 [STMICROELECTRONICS]
LOW-POWER, FULL-SPEED USB 8-BIT MCU WITH 32K FLASH, 5K RAM, FLASH CARD I/F, TIMER, PWM, ADC, I2C, SPI; 低功耗，全速USB的8位MCU 32K FLASH， 5K RAM ，FLASH CARD I / F ，定时器， PWM ， ADC ， I2C ， SPI
| 型号： | ST7265AR4M1 |
| 厂家： | 
ST |
| 描述： | LOW-POWER, FULL-SPEED USB 8-BIT MCU WITH 32K FLASH, 5K RAM, FLASH CARD I/F, TIMER, PWM, ADC, I2C, SPI |
| 文件： | 总166页 (文件大小：2028K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ST7265x
LOW-POWER, FULL-SPEED USB 8-BIT MCU WITH 32K
2
FLASH, 5K RAM, FLASH CARD I/F, TIMER, PWM, ADC, I C, SPI
DATASHEET
■ Memories
– Up to 32K of ROM or High Density Flash (HD-
Flash) program memory with read/write pro-
tection
– For HDFlash devices, In-Application Pro-
gramming (IAP) via USB and In-Circuit pro-
gramming (ICP)
TQFP64 10x10
■ Mass Storage Interface
SO34 shrink
TQFP48
– Up to 5 Kbytes of RAM with up to 256 bytes
stack
– DTC (Data Transfer Coprocessor): Universal
Serial/Parallel communications interface, with
software plug-ins for current and future proto-
col standards:
■ Clock, Reset and Supply Management
– PLL for generating 48 MHz USB clock using a
12 MHz crystal
– Low Voltage Reset (except on E suffix devic-
es)
– Dual supply management: analog voltage de-
tector on the USB power line to enable smart
power switching from USB power to battery
(on E suffix devices).
Compact Flash - Multimedia Card -
Secure Digital Card - SmartMediaCard -
Sony Memory Stick - NAND Flash -
ATA Peripherals
■ 2 Timers
– Programmable Internal Voltage Regulator for
Memory cards (2.8V to 3.5V) supplying:
Flash Card I/O lines (voltage shifting)
Up to 50 mA for Flash card supply
– Configurable Watchdog for system reliability
– 16-bit Timer with 2 output compare functions.
■ 2 Communication Interfaces
– SPI synchronous serial interface
– I C Single Master Interface up to 400 KHz
– Clock-out capability
■ 47 programmable I/O lines
2
■ D/A and A/D Peripherals
– 15 high sink I/Os (8mA @0.6V / 20mA@1.3V)
– 5 true open drain outputs
– 24 lines programmable as interrupt inputs
■ USB (Universal Serial Bus) Interface
– PWM/BRM Generator (with 2 10-bit PWM/
BRM outputs)
– 8-bit A/D Converter (ADC) with 8 channels
■ Instruction Set
– with DMA for full speed bulk applications com-
pliant with USB 12 Mbs specification (version
2.0 compliant)
– On-Chip 3.3V USB voltage regulator and
transceivers with software power-down
– 8-bit data manipulation
– 63 basic instructions
– 17 main addressing modes
– 8 x 8 unsigned multiply instruction
– True bit manipulation
– 5 USB endpoints:
1 control endpoint
2 IN endpoints supporting interrupt and bulk
2 OUT endpoints supporting interrupt and
bulk
■ Development Tools
– Full hardware/software development package
– Hardware conversion between USB bulk
packets and 512-byte blocks
Device Summary
Features
ST72651
ST72F651
ST72652
16K ROM
512 (256)
Program memory
User RAM (stack) - bytes
32K ROM
32K FLASH
5K (256)
2
Peripherals
USB, DTC, Timer, ADC, SPI, I C, PWM, WDT
USB, DTC, WDT
Single 4.0V to 5.5V
Dual 2.7V to 5.5V or
Dual 3.0V to 5.5V or
4.0V to 5.5V (for USB) 4.0V to 5.5V (for USB)
Operating Supply
Package
TQFP64 (10 x10)
TQFP64 (10 x10) / TQFP48 (7x7) / SO34
Operating Temperature
0°C to +70°C
Rev. 2.3
1/166
June 2003
This is preliminary information on a new product. Details are subject to change without notice.
1
Table of Contents
1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.3 STRUCTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.4 PROGRAM MEMORY READ-OUT PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.5 ICP (IN-CIRCUIT PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.6 IAP (IN-APPLICATION PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.7 RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.8 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.1 CLOCK SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.2 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.3 LOW VOLTAGE DETECTOR (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.4 POWER SUPPLY MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . 41
7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7.2 MASKING AND PROCESSING FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7.3 INTERRUPTS AND LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
7.4 CONCURRENT & NESTED MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
7.5 INTERRUPT REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
8.2 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
8.3 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
9 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
9.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
9.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
9.4 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
10 MISCELLANEOUS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
11 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
11.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
11.2 DATA TRANSFER COPROCESSOR (DTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
11.3 USB INTERFACE (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
11.4 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
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11.5 PWM/BRM GENERATOR (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
11.6 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
11.7 I²C SINGLE MASTER BUS INTERFACE (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
11.8 8-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
12 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
12.1 CPU ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
12.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
13 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
13.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
13.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
13.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
13.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
13.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
13.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
13.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
13.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
13.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
13.10TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
13.11COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 149
13.128-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
14 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
14.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
15 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . 159
15.1 OPTION BYTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
15.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . . 160
15.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
15.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
16 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
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1
ST7265x
1 INTRODUCTION
The ST7265x MCU supports volume data ex-
change with a host (computer or kiosk) via a full
speed USB interface. The MCU is capable of han-
dling various transfer protocols, with a particular
emphasis on mass storage applications.
– A dedicated 24 MHz Data Buffer Manager state
machine for handling 512-byte data blocks (this
size corresponds to a sector both on computers
and FLASH media cards).
– A Data Transfer Coprocessor (DTC), able to
handle fast data transfer with external devices.
This DTC also computes the CRC or ECC re-
quired to handle Mass storage media.
ST7265x is compliant with the USB Mass Storage
Class specifications, and supports related proto-
cols such as BOT (Bulk Only Transfer) and CBI
(Control, Bulk, Interrupt).
– An Arbitration block gives the ST7 core priority
over the USB and DTC when accessing the Data
Buffer. In USB mode, the USB interface is serv-
iced before the DTC.
It is based on the ST7 standard 8-bit core, with
specific peripherals for managing USB full speed
data transfer between the host and most types of
FLASH media card:
– A FLASH Supply Block able to provide program-
mable supply voltage and I/O electrical levels to
the FLASH media.
– A full speed USB interface with Serial Interface
Engine, and on-chip 3.3V regulator and trans-
ceivers.
Figure 1. USB Data Transfer Block Diagram
USB
SIE
DATA TRANSFER
BUFFER
USB DATA
TRANSFER
512-byte RAM
Buffer
BUFFER ACCESS
ARBITRATION
ST7 CORE
512-byte RAM
Buffer
DATA
TRANSFER
COPROCESSOR
(DTC)
LEVEL
SHIFTERS
MASS
STORAGE
DEVICE
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1
ST7265x
INTRODUCTION (Cont’d)
In addition to the peripherals for USB full speed
data transfer, the ST7265x includes all the neces-
sary features for stand-alone applications with
FLASH mass storage.
– Serial Peripheral interface (not on all products -
see device summary)
2
– Fast I C Single Master interface (not on all prod-
ucts - see device summary)
– Low voltage reset ensuring proper power-on or
power-off of the device (not on all products)
– 8-bit Analog-to-Digital converter (ADC) with 8
multiplexed analog inputs (not on all products -
see device summary)
– Digital Watchdog
– 16-bit Timer with 2 output compare functions (not
on all products - see device summary).
The ST72F65x are the Flash versions of the
ST7265x in a TQFP64 package.
– Two 10-bit PWM outputs (not on all products -
see device summary)
The ST7265x are the ROM versions in a TQFP64
package.
Figure 2. Digital Audio Player Application Example in Play Mode
DATA TRANSFER
BUFFER
512-byte RAM
Buffer
512-byte RAM
Buffer
BUFFER ACCESS
ARBITRATION
ST7 CORE
DATA
TRANSFER
COPROCESSOR
(DTC)
I2C
LEVEL SHIFTERS
MASS
STORAGE
DEVICE
DIGITAL
AUDIO DEVICE
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1
ST7265x
INTRODUCTION (Cont’d)
Figure 3. ST7265x Block Diagram
OSCIN
12MHz
OSC
OSCOUT
PA[7:0]
(8 bits)
CLOCK
DIVIDER
PORT A
48MHz
PLL
PB[7:0]
(8 bits)
PORT B
SPI *
f
CPU
PC[7:0]
(8 bits)
PORT C
DATA
TRANSFER
BUFFER
DATA
TRANSFER
COPROCESSOR
(1280 bytes)
DTC S/W RAM
(256 Bytes)
PE[7:0]
(8 bits)
PORT E
PWM*
USBDP
USBDM
USBVCC
PORT F
USB
PF[6:0]
(7 bits)
PD[7:0]
(8 bits)
2
I C*
PORT D
16-BIT TIMER*
WATCHDOG
8-BIT ADC*
V
DDF
FLASH SUPPLY
BLOCK
V
RESET
CONTROL
SSF
8-BIT CORE
ALU
V
DDA
POWER SUPPLY
REGULATOR
V
PP
V
SSA
LVD*
V
V
DD1, DD2
DUAL SUPPLY
MANAGER *
V
V
SS1, SS2
RAM
(0.5/5 KBytes)
USBV
USBV
DD
SS
PROGRAM
MEMORY
(16/32 Kbytes)
* not on all products (refer to Table 1: Device Summary)
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1
ST7265x
2 PIN DESCRIPTION
Figure 4. 34-Pin SO Package Pinout
V
V
V
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
DDA
1
2
SSA
V
DD2
SS2
OSCIN
PF6 (HS) / ICCDATA
3
OSCOUT
PF5 (HS) / ICCCLK
RESET
4
5
USBV
SS
6
USBDM
USBDP
V
/ICCSEL
PP
PD6
PD5
7
USBVCC
8
USBV
9
PD4
PD3
DD
ei1
10
11
12
13
14
15
16
17
V
DDF
V
PD2
PD1
PD0
SSF
DTC / PA0
DTC / PA1
ei0
ei2
V
DTC / PA2
SS1
V
DTC / PA3
DD1
PC3 (HS) / DTC
PC2 (HS) / DTC
MCO / (HS) PC0
DTC / (HS) PC1
ei2
I/O pin supplied by V
/ V
SSF
DDF
(HS) high sink capability
ei associated external interrupt vector
x
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1
ST7265x
PIN DESCRIPTION (Cont’d)
Figure 5. 48-Pin TQFP Package Pinout
48 47 46 45 44 43 42 41 40 39 38 37
PE2 (HS) / DTC
PE1 (HS) / DTC
PE0 (HS) / DTC
PD7
USBV
36
1
SS
USBDM
USBDP
2
35
34
33
32
31
30
29
28
27
26
25
3
USBVCC
4
PD6
USBV
DD
5
PD5
V
6
DDF
PD4
PD3
PD2
PD1
PD0
V
7
SSF
ei1
23
DTC/PB0
DTC/PB1
DTC/PB2
8
9
10
ei0
DTC/PB3
DTC/PB4
11
12
V
SS1
24
13 14 15 16 17 18 19 20 21 22
I/O pin supplied by V
/ V
SSF
DDF
(HS) high sink capability
ei
associated external interrupt vector
x
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1
ST7265x
PIN DESCRIPTION (Cont’d)
Figure 6. 64-Pin TQFP Package Pinout
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
PE3 / PWM0 / AIN7 / DTC
PE2 (HS) / AIN6 / DTC
PE1 (HS) / AIN5 / DTC
PE0 (HS) / AIN4 / DTC
PD7 / AIN3
PD6 / AIN2
PD5/OCMP2
PD4/OCMP1
PD3
PD2
PD1
PD0
PC7
PC6
PC5
PC4
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
USBV
USBDM
USBDP
1
SS
2
3
USBVCC
4
USBV
5
DD
V
6
DDF
V
7
SSF
DTC / PE5 (HS)
DTC / PE6 (HS)
DTC / PE7 (HS)
DTC / PB0
8
ei1
ei2
9
10
11
12
13
14
15
16
DTC / PB1
DTC / PB2
DTC / PB3
DTC / PB4
ei0
ei2
DTC / PB5
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
I/O pin supplied by V
/ V
SSF
DDF
(HS) high sink capability
ei
associated external interrupt vector
x
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ST7265x
PIN DESCRIPTION (Cont’d)
Legend / Abbreviations:
Port and control configuration:
Type: I = input, O = output, S = supply
– Input:float = floating, wpu = weak pull-up, int = in-
terrupt
V
powered: I/O powered by the alternate sup-
DDF
ply rail, supplied by V
and V
.
– Output: OD = open drain, T = true open drain, PP
= push-pull, OP = pull-up enabled by option byte.
DDF
SSF
In/Output level: C = CMOS 0.3V /0.7V with
DD
T
DD
input trigger
Refer to “I/O PORTS” on page 49 for more details
on the software configuration of the I/O ports.
Output level: HS = High Sink (on N-buffer only)
The RESET configuration of each pin is shown in
bold.
Table 1. Device Pin Description
Pin
Level Port / Control
Input Output
Main
Pin Name
Function
Alternate Function
(after reset)
5
6
7
1
2
3
1
2
3
USBV
S
USB Digital ground
SS
USBDM
I/O
I/O
USB bidirectional data (data -)
USB bidirectional data (data +)
USBDP
USB power supply, output by the on-chip USB
3.3V linear regulator.
8
9
4
5
4
5
USBVCC
O
S
Note: An external decoupling capacitor (typ.
100nF, min 47nF) must be connected be-
tween this pin and USBV
.
SS
USB Power supply voltage (4V - 5.5V)
Note: External decoupling capacitors (typ.
4.7µF+100nF, min 2.2µF+100nFmust be con-
USBV
DD
nected between this pin and USBV
.
SS
Power Line for alternate supply rail. Can be
used as input (with external supply) or output
(when using the on-chip voltage regulator).
Note: An external decoupling capacitor (min.
20nF) must be connected to this pin to stabi-
lize the regulator.
10
11
6
7
6
7
V
V
S
S
X
X
DDF
SSF
Ground Line for alternate supply rail. Can be
used as input (with external supply) or output
(when using the on-chip voltage regulator)
DTC I/O with serial capability
(MMC_CMD)
2
2
-
-
-
-
-
-
-
-
8
9
PE5/DTC
PE6/DTC
I/O
I/O
I/O
I/O
I/O
I/O
X
X
X
X
X
X
C
C
C
HS X
X
X
X
X
X
X
X
Port E5
T
T
T
DTC I/O with serial capability
(MMC_DAT)
HS X
X
Port E6
DTC I/O with serial capability
(MMC_CLK)
-
10 PE7/DTC
11 PB0/DTC
12 PB1/DTC
HS X
X
Port E7
C
T
8
9
X
X
X
Port B0
Port B1
Port B2
DTC
DTC
DTC
C
T
C
T
10 13 PB2/DTC
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1
ST7265x
Pin
Level Port / Control
Input Output
Main
Pin Name
Function
(after reset)
Alternate Function
C
T
-
-
-
-
-
11 14 PB3/DTC
12 15 PB4/DTC
13 16 PB5/DTC
14 17 PB6/DTC
15 18 PB7/DTC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Port B3
Port B4
Port B5
Port B6
Port B7
Port A0
Port A1
Port A2
Port A3
Port A4
Port A5
Port A6
Port A7
Port C0
DTC
DTC
DTC
DTC
DTC
DTC
DTC
DTC
DTC
DTC
DTC
DTC
DTC
C
T
X
C
T
X
C
T
X
C
T
X
C
T
12 16 19 PA0/DTC
13 17 20 PA1/DTC
14 18 21 PA2/DTC
15 19 22 PA3/DTC
X
X
X
X
X
X
X
X
X
C
T
X
C
T
X
C
T
X
ei
0
C
T
-
-
20 23 PA4/DTC
21 24 PA5/DTC
22 25 PA6/DTC
23 26 PA7/DTC
X
C
T
X
X
C
T
-
C
T
-
X
C
T
Main Clock Output / SPI Slave
Select
16
-
-
27 PC0/MCO/SS
28 PC1/DTC/MIS0
HS X
1
DTC I/O with serial capability
(DATARQ) / SPI Master In
Slave Out
17
I/O
X
C
HS X
X
Port C1
T
1
ei
2
DTC I/O with serial capability
(SDAT) / SPI Master Out Slave
18
19
-
-
29 PC2/DTC/MOSI
30 PC3/DTC/SCK
I/O
I/O
X
X
C
C
HS X
HS X
X
X
Port C2
Port C3
T
1
In
DTC I/O with serial capability
(SCLK) / SPI Serial Clock
1
T
20 24 31
21 25 32
V
V
S
Power supply voltage (2.7V - 5.5V)
Digital ground
DD1
SS1
S
-
-
-
-
-
-
-
-
33 PC4/DTC
34 PC5/DTC
35 PC6/DTC
36 PC7/DTC
I/O
I/O
I/O
I/O
C
C
C
C
X
X
X
X
X
X
X
X
Port C4
Port C5
Port C6
Port C7
DTC
DTC
DTC
DTC
T
T
T
T
ei
2
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1
ST7265x
Pin
Level Port / Control
Input Output
Main
Pin Name
Function
(after reset)
Alternate Function
C
T
22 26 37 PD0
23 27 38 PD1
24 28 39 PD2
25 29 40 PD3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Port D0
Port D1
Port D2
Port D3
Port D4
Port D5
Port D6
Port D7
Port E0
C
T
X
C
T
X
C
T
X
ei
1
C
T
1
26 30 41 PD4/OCMP1
27 31 42 PD5/OCMP2
28 32 43 PD6/AIN2
X
Timer Output Compare 1
C
T
1
X
X
Timer Output Compare 2
C
T
1
Analog Input 2
C
T
1
-
-
33 44 PD7/AIN3
X
Analog Input 3
C
T
1
34 45 PE0/DTC/AIN4
HS X
Analog Input 4 / DTC
1
-
-
35 46 PE1/DTC/AIN5
36 47 PE2/DTC/AIN6
I/O
I/O
C
HS X
HS X
X
X
X
X
Port E1
Port E2
Analog Input 5 / DTC
T
1
C
C
C
Analog Input 6 / DTC
T
1
PE3/AIN7/DTC/
Analog Input 7 / DTC / PWM
-
-
37 48
PWM0
I/O
I/O
S
X
X
X
X
X
X
Port E3
1
T
T
Output 0
1
38 49 PE4/PWM1
Port E4
PWM Output 1
Flash programming voltage. Must be held low
in normal operating mode.
29 39 50
V
/ICCSEL
PP
Bidirectional. This active low signal forces the
initialization of the MCU. This event is the top
priority non maskable interrupt. This pin is
switched low when the Watchdog has trig-
30 40 51 RESET
I/O
X
X
gered or V is low. It can be used to reset ex-
DD
ternal peripherals.
1
2
-
-
-
-
-
-
-
-
52 PF0 / SCL
53 PF1 / SDA
54 PF2 / AIN0
55 PF3 / AIN1
I/O
I/O
I/O
I/O
C
C
C
C
HS X
HS X
X
T
T
Port F0
Port F1
Port F2
Port F3
I C Serial Clock
T
T
T
T
1
2
I C Serial Data
1
X
X
Analog Input 0
Analog Input 1
1
X
USB Power Management USB
Enable (alternate function se-
lected by option bit)
-
-
56 PF4 / USBEN
I/O
C
HS X
T
Port F4
T
31 41 57 PF5 / ICCCLK
32 42 58 PF6 / ICCDATA
I/O
I/O
C
C
HS X
HS X
T
T
Port F5
Port F6
ICC Clock Output
ICC Data Input
T
T
Main Power supply voltage (2.7V - 5.5V on
devices without LVD, otherwise 4V - 5.5V).
33 43 59
34 44 60
V
V
S
S
DD2
DDA
Analog supply voltage
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ST7265x
Pin
Level Port / Control
Input Output
Main
Pin Name
Function
(after reset)
Alternate Function
1
2
3
4
45 61
46 62
V
V
S
S
I
Analog ground
Digital ground
SSA
SS2
Input/Output Oscillator pins. These pins con-
nect a 12 MHz parallel-resonant crystal, or an
external source to the on-chip oscillator.
47 63 OSCIN
48 64 OSCOUT
O
1
2
If the peripheral is present on the device (see Device Summary on page 1)
A weak pull-up can be enabled on PE5 input and open drain output by configuring the PEOR register
and depending on the PE5PU bit in the option byte.
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ST7265x
Figure 7. Multimedia Card Or Secure Digital Card Writer Application Example
100nF
4.7µF
V
DD
USBV
DD
USBVDD
=4.0-5.5V
USB Port
5V
1.5KΩ
USB
VCC
100nF
POWER
USB
DP
DP
MANAGEMENT
(2)
DM
DM
USB
GND
GND
I/O
LOGIC
LED1
LED2
REGULATOR
DTC
12V for
FLASH
VPP
Flash prog.
(connect to
GND if
V
level translator
DDF
not used)
PE7 PE6 PE5
100nF
CLK DAT CMD
V
DD
UP TO 5
MULTIMEDIA
OR SD CARDS
MultiMedia Card Pin
CMD
DAT
CLK
ST72F65 pin
PE5
DTC
PE6
DTC
PE7
DTC
(1)
ST7 / DTC
(1) This line shows if the ST72F65 pin is controlled by the
ST7 core or by the DTC.
used as a normal I/O by configuring it as such by the op-
tion byte.
(2) As this is a single power supply application, the US-
BEN function in not needed. Thus PF4/USBEN pin can be
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ST7265x
Figure 8. Smartmedia Card Writer Or Flash Drive Application Example
100nF
4.7µF
V
DD
USBVDD
=4.0-5.5V
USBVDD
USB Port
5V
1.5KΩ
USB
VCC
100nF
USB
DP
DP
POWER
DM
MANAGEMENT
(4)
DM
USB
GND
GND
I/O
LOGIC
REGULATOR
LED1
LED2
DTC
12V for
Flash prog.
1
5
FLASH
VPP
level translator
(connect to
GND if
V
DDF
not used)
PE
PB PA
8
6
2
100nF
CTRL
I/O
0~7
V
DD
UP TO 2
SMARTMEDIA
CARDS
Table 2. SmartMedia Interface Pin Assignment
(2)
(2)
(2)(3)
SmartMedia Pin
I/O0~7
PB0-7
DTC
CLE
PA0
DTC
WE
PA1
DTC
ALE
PA2
DTC
RE
R/B
PA4
DTC
WP
PA7
ST7
CE1
CE2
ST72F65 pin
PA3
DTC
PE1
ST7
PE0
ST7
(1)
ST7 / DTC
(1): This line shows if the ST72F65 pin is controlled by the
ST7 core or the DTC.
(2): These lines are not controlled by the DTC but by the
user software running on the ST7 core. The ST72F65 pin
choice is at customer discretion. The pins shown here are
only shown as an example.
(3): When a single card is to be handled, PA7 is free for
other functions. When 2 Smartmedia are to be handled,
pins from both cards should be tied together (i.e. CLE1
with CLE2...) except for the CE pins. CE pin from card 1
should be connected to PA6 and CE pin from card 2
should be connect to PA7. Selection of the operating card
is done by ST7 software.
(4) As this is a single power supply application, the US-
BEN function in not needed. Thus PF4/USBEN pin can be
used as a normal I/O by configuring it as such by the op-
tion byte.
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ST7265x
Figure 9. Compact Flash Card Writer Application Example
100nF
4.7µF
V
DD
USBVDD
=4.0-5.5V
USBVDD
USB Port
5V
1.5KΩ
USB
VCC
100nF
POWER
USB
DP
DP
MANAGEMENT
(3)
DM
DM
USB
GND
GND
I/O
LOGIC
REGULATOR
LED1
LED2
DTC
12V for
Flash prog.
(connect to
GND if
not used)
FLASH
VPP
1
5
level
V
DDF
translator
PE
[2]
PA
PB
4.7KΩ
6
8
4.7µF
CF
100nF
8-BIT MEMORY
MODE
Table 3. Compact Flash Card Writer Pin Assignment
CSEL,
RESET,
GND,
VS1, VS2, WAIT,
CD2,
CD1 RDY/BSY,
WP
IORD,
IOWR, REG,
Compact Flash
Card Pin
D0-7 D8-15
A0-2
CE1
RE WE
CS1, INPACK,
BVD1, BVD2
CE2, V
CC
A3-10
PE2
PA6
ST72F65 pin PB0-7 NC
NC
-
V
V
PA0-2 +pull-up PA3 PA5 +pull-up
4.7kΩ 100kΩ
Power DTC ST7 DTC DTC ST7
NC
-
DDF
SSF
(1)
ST7 / DTC
DTC
-
Power
(1) This line shows if the ST72F65 pin is controlled by the
ST7 core or by the DTC.
(2) These lines are not controlled by the DTC but by the
user software running on the ST7 core. The choice of
ST72F65 pin is at the customer’s discretion. The pins
shown here are given only as an example.
(3) As this is a single power supply application, the US-
BEN function in not needed. Thus PF4/USBEN pin can be
used as a normal I/O by configuring it as such by the op-
tion byte.
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ST7265x
Figure 10. Sony Memory Stick Writer Application Example
100nF
4.7µF
V
DD
USBV
DD
USBVDD
=4.0-5.5V
USB Port
5V
1.5KΩ
USB
VCC
100nF
POWER
USB
DP
DP
MANAGEMENT
(2)
DM
DM
USB
GND
GND
I/O
LOGIC
LED1
LED2
REGULATOR
DTC
12V for
FLASH
VPP
Flash prog.
(connect to
GND if
V
level translator
DDF
not used)
PC0 PC3 PC1 PC2
CD CLK BS DAT
4.7µF
100nF
V
DD
SONY
MEMORY STICK
MultiMedia Card Pin
CMD
DAT
CLK
ST72F65 pin
PE5
DTC
PE6
DTC
PE7
DTC
(1)
ST7 / DTC
(1) This line shows if the ST72F65 pin is controlled by the
ST7 core or by the DTC.
used as a normal I/O by configuring it as such by the op-
tion byte.
(2) As this is a single power supply application, the US-
BEN function in not needed. Thus PF4/USBEN pin can be
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ST7265x
3 REGISTER & MEMORY MAP
As shown in Figure 11, the MCU is capable of ad-
dressing 64 Kbytes of memories and I/O registers.
The highest address bytes contain the user reset
and interrupt vectors.
The available memory locations consist of 80
bytes of register locations, up to 5 Kbytes of RAM
and up to 32 Kbytes of user program memory. The
RAM space includes up to 256 bytes for the stack
from 0100h to 01FFh.
IMPORTANT: Memory locations noted “Re-
served” must never be accessed. Accessing a re-
served area can have unpredictable effects on the
device.
Figure 11. Memory Map
0050h
Short Addressing
0000h
HW Registers
RAM (176 Bytes)
00FFh
(see Table 4)
004Fh
0050h
0100h
Stack (256 Bytes)
01FFh
512 Bytes RAM*
0200h
5 KBytes RAM*
144Fh
16-bit Addressing RAM
(80 Bytes)
1450h
DTC RAM (Write protected)
256 Bytes
154Fh
024Fh
USB Data Buffer**
1280 Bytes
1A4Fh
0050h
Short Addressing
RAM (176 Bytes)
Reserved
7FFFh
8000h
00FFh
Program Memory*
0100h
Stack (256 Bytes)
01FFh
32 Kbytes
C000h
0200h
16-bit Addressing RAM
(4688 Bytes)
16 Kbytes
144Fh
FFDFh
FFE0h
Interrupt & Reset Vectors
(see Table 10)
FFFFh
* Program memory and RAM sizes are product dependent (see Table –)
** The ST7 core is not able to read or write in the USB data buffer if the ST7265x is running at 6Mz in stan-
dalone mode.
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ST7265x
Table 4. Hardware Register Memory Map
Address
Block
Register Label
Register name
Port A Data Register
Reset Status
Remarks
0000h
0001h
0002h
PADR
PADDR
PAOR
00h
00h
00h
R/W
Port A Data Direction Register
Port A Option Register
R/W
R/W
0003h
0004h
PBDR
Port B Data Register
00h
00h
R/W
R/W
PBDDR
Port B Data Direction Register
0005h
Reserved Area (1 byte)
0006h
0007h
0008h
PCDR
PCDDR
PCOR
Port C Data Register
00h
00h
00h
R/W
R/W
R/W
Port C Data Direction Register
Port C Option Register
0009h
000Ah
000Bh
PDDR
PDDDR
PDOR
Port D Data Register
00h
00h
00h
R/W
R/W
R/W
Port D Data Direction Register
Port D Option Register
000Ch
000Dh
000Eh
PEDR
PEDDR
PEOR
Port E Data Register
00h
00h
00h
R/W
R/W
R/W
Port E Data Direction Register
Port E Option Register
000Fh
0010h
PFDR
Port F Data Register
00h
00h
R/W
R/W
PFDDR
Port F Data Direction Register
0011h
Reserved Area (1 byte)
0012h
0013h
ADCDR
ADC Data Register
00h
00h
Read only
R/W
1
ADC
ADCCSR
ADC Control Status Register
0014h
WDG
WDGCR
Watchdog Control Register
Reserved Area (3 bytes)
Power Control Register
7Fh
R/W
0015h
to
0017h
0018h
DSM
SPI
PCR
00h
R/W
0019h
001Ah
001Bh
SPIDR
SPICR
SPICSR
SPI Data I/O Register
SPI Control Register
SPI Control/Status Register
xxh
0xh
00h
R/W
R/W
R/W
001Ch
001Dh
001Eh
001Fh
DTCCR
DTCSR
Reserved
DTCPR
DTC Control Register
DTC Status Register
00h
00h
R/W
R/W
DTC
DTC Pointer Register
00h
R/W
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1
ST7265x
Address
Block
Register Label
Register name
Reset Status
Remarks
R/W
0020h
0021h
0022h
0023h
0024h
0025h
0026h
0027h
0028h
0029h
002Ah
TCR1
TCR2
TSR
Timer Control Register 1
00h
00h
00h
FFh
FCh
FFh
FCh
80h
00h
80h
00h
Timer Control Register 2
R/W
Timer Status Register
Read Only
Read Only
Read Only
Read Only
Read Only
R/W
CHR
Timer Counter High Register
CLR
Timer Counter Low Register
TIM
ACHR
ACLR
OC1HR
OC1LR
OC2HR
OC2LR
Timer Alternate Counter High Register
Timer Alternate Counter Low Register
Timer Output Compare 1 High Register
Timer Output Compare 1 Low Register
Timer Output Compare 2 High Register
Timer Output Compare 2 Low Register
R/W
R/W
R/W
002Bh
Flash
ITC
Flash Control Status Register
00h
R/W
002Ch
002Dh
002Eh
002Fh
ITSPR0
ITSPR1
ITSPR2
ITSPR3
Interrupt Software Priority Register 0
Interrupt Software Priority Register 1
Interrupt Software Priority Register 2
Interrupt Software Priority Register 3
FFh
FFh
FFh
FFh
R/W
R/W
R/W
R/W
0030h
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
USBISTR
USBIMR
USBCTLR
DADDR
USB Interrupt Status Register
USB Interrupt Mask Register
USB Control Register
00h
00h
06h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Device Address Register
USB Status Register
USBSR
EP0R
Endpoint 0 Register
CNT0RXR
CNT0TXR
EP1RXR
CNT1RXR
EP1TXR
CNT1TXR
EP2RXR
CNT2RXR
EP2TXR
CNT2TXR
EP 0 Reception Counter Register
EP 0 Transmission Counter Register
Endpoint 1 Register
USB
EP 1 Reception Counter Register
Endpoint 1 Register
EP 1 Transmission Counter Register
Endpoint 2 Register
EP 2 Reception Counter Register
Endpoint 2 Register
EP 2 Transmission Counter Register
2
I2CCR
I C Control Register
00h
00h
00h
00h
R/W
0040h
0041h
0042h
0043h
0044h
0045h
0046h
2
I2CSR1
I2CSR2
I2CCCR
Not used
Not used
I2CDR
I C Status Register 1
Read only
Read only
R/W
2
I C Status Register 2
2
1
2
C
I C Clock Control Register
I
2
I C Data Register
00h
00h
R/W
R/W
0047h
0048h
0049h
004Ah
004Bh
USB
BUFCSR
Buffer Control/Status Register
Reserved Area (1 Byte)
Miscellaneous Register 1
Miscellaneous Register 2
Reserved Area (1 Byte)
MISCR1
MISCR2
00h
00h
R/W
R/W
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ST7265x
Address
Block
Register Label
Register name
Reset Status
Remarks
004Ch
MISCR3
Miscellaneous Register 3
00h
R/W
004Dh
004Eh
004Fh
PWM0
BRM10
PWM1
80h
00h
80h
R/W
R/W
R/W
1
PWM
10-bit PWM/BRM registers
Note 1. If the peripheral is present on the device (see Device Summary on page 1)
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ST7265x
4 FLASH PROGRAM MEMORY
4.1 Introduction
4.3 Structure
The ST7 dual voltage High Density Flash
The Flash memory is organised in sectors and can
be used for both code and data storage.
(HDFlash) is a non-volatile memory that can be
electrically erased as a single block or by individu-
al sectors and programmed on a Byte-by-Byte ba-
Depending on the overall Flash memory size in the
microcontroller device, there are up to three user
sectors (see Table 5). Each of these sectors can
be erased independently to avoid unnecessary
erasing of the whole Flash memory when only a
partial erasing is required.
sis using an external V supply.
PP
The HDFlash devices can be programmed and
erased off-board (plugged in a programming tool)
or on-board using ICP (In-Circuit Programming) or
IAP (In-Application Programming).
The first two sectors have a fixed size of 4 Kbytes
(see Figure 12). They are mapped in the upper
part of the ST7 addressing space so the reset and
interrupt vectors are located in Sector 0 (F000h-
FFFFh).
The array matrix organisation allows each sector
to be erased and reprogrammed without affecting
other sectors.
4.2 Main Features
Table 5. Sectors available in Flash devices
■ Three Flash programming modes:
Flash Memory Size
Available Sectors
(bytes)
– Insertion in a programming tool. In this mode,
all sectors including option bytes can be pro-
grammed or erased.
– ICP (In-Circuit Programming). In this mode, all
sectors including option bytes can be pro-
grammed or erased without removing the de-
vice from the application board.
4K
8K
Sector 0
Sectors 0,1
Sectors 0,1, 2
> 8K
– IAP (In-Application Programming) In this
mode, all sectors except Sector 0, can be pro-
grammed or erased without removing the de-
vice from the application board and while the
application is running.
4.4 Program Memory Read-out Protection
The read-out protection is enabled through an op-
tion bit.
■ ICT (In-Circuit Testing) for downloading and
When this option is selected, the programs and
data stored in the program memory (Flash or
ROM) are protected against read-out piracy (in-
cluding a re-write protection). In Flash devices,
when this protection is removed by reprogram-
ming the Option Byte, the entire program memory
is first automatically erased and the device can be
reprogrammed.
executing user application test patterns in RAM
■ Read-out protection against piracy
■ Register Access Security System (RASS) to
prevent accidental programming or erasing
Refer to the Option Byte description for more de-
tails.
Figure 12. Memory Map and Sector Address
4K
8K
10K
16K
24K
32K
48K
60K
DV FLASH
MEMORY SIZE
1000h
3FFFh
7FFFh
9FFFh
BFFFh
D7FFh
DFFFh
EFFFh
FFFFh
SECTOR 2
52 Kbytes
2 Kbytes 8 Kbytes 16 Kbytes 24 Kbytes 40 Kbytes
4 Kbytes
4 Kbytes
SECTOR 1
SECTOR 0
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FLASH PROGRAM MEMORY (Cont’d)
4.5 ICP (In-Circuit Programming)
– ICCSEL/V : programming voltage
PP
– V : application board power supply
CAUTIONS:
DD
To perform ICP the microcontroller must be
switched to ICC (In-Circuit Communication) mode
by an external controller or programming tool.
1. If RESET, ICCCLK or ICCDATA pins are used
for other purposes in the application, a serial resis-
tor has to be implemented to avoid a conflict in
case one of the other devices forces the signal lev-
el. If these pins are used as outputs in the applica-
tion, the serial resistors are not necessary. As
soon as the external controller is plugged to the
board, even if an ICC session is not in progress,
the ICCCLK and ICCDATA pins are not available
for the application.
Depending on the ICP code downloaded in RAM,
Flash memory programming can be fully custom-
ized (number of bytes to program, program loca-
tions, or selection serial communication interface
for downloading).
When using an STMicroelectronics or third-party
programming tool that supports ICP and the spe-
cific microcontroller device, the user needs only to
implement the ICP hardware interface on the ap-
plication board (see Figure 13). For more details
on the pin locations, refer to the device pinout de-
scription.
2. The use of Pin 7 of the ICC connector depends
on the Programming Tool architecture. Please re-
fer to the documentation of the tool. This pin must
be connected when using ST Programming Tools
(it is used to monitor the application power supply).
ICP needs six pins to be connected to the pro-
gramming tool. These pins are:
– RESET: device reset
Note: To develop a custom programming tool, re-
fer to the ST7 Flash Programming and ICC Refer-
ence Manual which gives full details on the ICC
protocol hardware and software.
– V : device power supply ground
SS
– ICCCLK: ICC output serial clock pin
– ICCDATA: ICC input serial data pin
Figure 13. Typical ICP Interface
PROGRAMMING TOOL
ICC CONNECTOR
ICC Cable
ICC CONNECTOR
HE10 CONNECTOR TYPE
OPTIONAL
(SEE CAUTION 2)
APPLICATION BOARD
9
7
5
6
3
1
2
10
8
4
10kΩ
>4.7kΩ
APPLICATION
POWER SUPPLY
OPTIONAL (SEE CAUTION 1)
ST7
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FLASH PROGRAM MEMORY (Cont’d)
4.6 IAP (In-Application Programming)
4.8 Register Description
This mode uses a BootLoader program previously
stored in Sector 0 by the user (in ICP mode or by
plugging the device in a programming tool).
FLASH CONTROL/STATUS REGISTER (FCSR)
Read/Write
This mode is fully controlled by user software. This
allows it to be adapted to the user application, (us-
er-defined strategy for entering programming
mode, choice of communications protocol used to
fetch the data to be stored, etc.). For example, it is
possible to download code from the SPI, SCI, USB
or CAN interface and program it in the Flash. IAP
mode can be used to program any of the Flash
sectors except Sector 0, which is write/erase pro-
tected to allow recovery in case errors occur dur-
ing the programming operation.
Reset Value: 0000 0000 (00h)
7
0
0
0
0
0
0
0
0
0
This register is reserved for use by Programming
Tool software. It controls the Flash programming
and erasing operations.
4.7 Related Documentation
For details on Flash programming and ICC proto-
col, refer to the ST7 Flash Programming Refer-
ence Manual and to the ST7 ICC Protocol Refer-
ence Manual.
Table 6. FLASH Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
FCSR
Reset Value
002Bh
0
0
0
0
0
0
0
0
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5 CENTRAL PROCESSING UNIT
5.1 INTRODUCTION
5.3 CPU REGISTERS
This CPU has a full 8-bit architecture and contains
six internal registers allowing efficient 8-bit data
manipulation.
The 6 CPU registers shown in Figure 14 are not
present in the memory mapping and are accessed
by specific instructions.
Accumulator (A)
5.2 MAIN FEATURES
The Accumulator is an 8-bit general purpose reg-
ister used to hold operands and the results of the
arithmetic and logic calculations and to manipulate
data.
■ Enable executing 63 basic instructions
■ Fast 8-bit by 8-bit multiply
■ 17 main addressing modes (with indirect
Index Registers (X and Y)
addressing mode)
These 8-bit registers are used to create effective
addresses or as temporary storage areas for data
manipulation. (The Cross-Assembler generates a
precede instruction (PRE) to indicate that the fol-
lowing instruction refers to the Y register.)
■ Two 8-bit index registers
■ 16-bit stack pointer
■ Low power HALT and WAIT modes
■ Priority maskable hardware interrupts
■ Non-maskable software/hardware interrupts
The Y register is not affected by the interrupt auto-
matic procedures.
Program Counter (PC)
The program counter is a 16-bit register containing
the address of the next instruction to be executed
by the CPU. It is made of two 8-bit registers PCL
(Program Counter Low which is the LSB) and PCH
(Program Counter High which is the MSB).
Figure 14. CPU Registers
7
0
ACCUMULATOR
RESET VALUE = XXh
7
0
0
X INDEX REGISTER
Y INDEX REGISTER
RESET VALUE = XXh
7
RESET VALUE = XXh
PCL
PCH
7
8
15
0
PROGRAM COUNTER
RESET VALUE = RESET VECTOR @ FFFEh-FFFFh
7
1
0
1
1
I1 H I0 N Z C
CONDITION CODE REGISTER
RESET VALUE =
8
1
1
X 1 X X X
0
15
7
STACK POINTER
RESET VALUE = STACK HIGHER ADDRESS
X = Undefined Value
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CENTRAL PROCESSING UNIT (Cont’d)
Condition Code Register (CC)
Read/Write
Bit 1 = Z Zero.
This bit is set and cleared by hardware. This bit in-
dicates that the result of the last arithmetic, logical
or data manipulation is zero.
0: The result of the last operation is different from
zero.
Reset Value: 111x1xxx
7
0
1: The result of the last operation is zero.
1
1
I1
H
I0
N
Z
C
This bit is accessed by the JREQ and JRNE test
instructions.
The 8-bit Condition Code register contains the in-
terrupt masks and four flags representative of the
result of the instruction just executed. This register
can also be handled by the PUSH and POP in-
structions.
Bit 0 = C Carry/borrow.
This bit is set and cleared by hardware and soft-
ware. It indicates an overflow or an underflow has
occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.
These bits can be individually tested and/or con-
trolled by specific instructions.
Arithmetic Management Bits
This bit is driven by the SCF and RCF instructions
and tested by the JRC and JRNC instructions. It is
also affected by the “bit test and branch”, shift and
rotate instructions.
Bit 4 = H Half carry.
This bit is set by hardware when a carry occurs be-
tween bits 3 and 4 of the ALU during an ADD or
ADC instructions. It is reset by hardware during
the same instructions.
Interrupt Management Bits
Bit 5,3 = I1, I0 Interrupt
0: No half carry has occurred.
1: A half carry has occurred.
The combination of the I1 and I0 bits gives the cur-
rent interrupt software priority.
This bit is tested using the JRH or JRNH instruc-
tion. The H bit is useful in BCD arithmetic subrou-
tines.
Interrupt Software Priority
Level 0 (main)
I1
1
0
0
1
I0
0
1
0
1
Level 1
Bit 2 = N Negative.
Level 2
This bit is set and cleared by hardware. It is repre-
sentative of the result sign of the last arithmetic,
logical or data manipulation. It’s a copy of the re-
Level 3 (= interrupt disable)
These two bits are set/cleared by hardware when
entering in interrupt. The loaded value is given by
the corresponding bits in the interrupt software pri-
ority registers (IxSPR). They can be also set/
cleared by software with the RIM, SIM, IRET,
HALT, WFI and PUSH/POP instructions.
th
sult 7 bit.
0: The result of the last operation is positive or null.
1: The result of the last operation is negative
(i.e. the most significant bit is a logic 1).
This bit is accessed by the JRMI and JRPL instruc-
tions.
See the interrupt management chapter for more
details.
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CENTRAL PROCESSING UNIT (Cont’d)
Stack Pointer (SP)
Read/Write
The least significant byte of the Stack Pointer
(called S) can be directly accessed by a LD in-
struction.
Reset Value: 01 FFh
Note: When the lower limit is exceeded, the Stack
Pointer wraps around to the stack upper limit, with-
out indicating the stack overflow. The previously
stored information is then overwritten and there-
fore lost. The stack also wraps in case of an under-
flow.
15
8
1
0
7
0
0
0
0
0
0
0
The stack is used to save the return address dur-
ing a subroutine call and the CPU context during
an interrupt. The user may also directly manipulate
the stack by means of the PUSH and POP instruc-
tions. In the case of an interrupt, the PCL is stored
at the first location pointed to by the SP. Then the
other registers are stored in the next locations as
shown in Figure 15.
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
The Stack Pointer is a 16-bit register which is al-
ways pointing to the next free location in the stack.
It is then decremented after data has been pushed
onto the stack and incremented before data is
popped from the stack (see Figure 15).
– When an interrupt is received, the SP is decre-
mented and the context is pushed on the stack.
Since the stack is 256 bytes deep, the 8 most sig-
nificant bits are forced by hardware. Following an
MCU Reset, or after a Reset Stack Pointer instruc-
tion (RSP), the Stack Pointer contains its reset val-
ue (the SP7 to SP0 bits are set) which is the stack
higher address.
– On return from interrupt, the SP is incremented
and the context is popped from the stack.
A subroutine call occupies two locations and an in-
terrupt five locations in the stack area.
Figure 15. Stack Manipulation Example
CALL
Subroutine
RET
or RSP
PUSH Y
POP Y
IRET
Interrupt
Event
@ 0100h
SP
SP
SP
Y
CC
A
CC
A
CC
A
X
X
X
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
SP
SP
PCH
PCL
PCH
PCL
SP
@ 01FFh
Stack Higher Address = 01FFh
0100h
Stack Lower Address =
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6 SUPPLY, RESET AND CLOCK MANAGEMENT
6.1 CLOCK SYSTEM
6.1.1 General Description
6.1.2 External Clock
The MCU accepts either a 12 MHz crystal or an
external clock signal to drive the internal oscillator.
An external clock may be applied to the OSCIN in-
put with the OSCOUT pin not connected, as
The internal clock (f
nal oscillator frequency (f
) is derived from the inter-
shown on Figure 16. The t
specifications
CPU
OXOV
), which is 12 Mhz in
does not apply when using an external clock input.
The equivalent specification of the external clock
OSC
Stand-alone mode and 48Mhz in USB mode.
source should be used instead of t
tion 6.5 CONTROL TIMING).
(see Sec-
OXOV
The internal clock (f ) is software selectable us-
ing the CP[1:0] and CPEN bits in the MISCR1 reg-
ister.
CPU
Figure 16. External Clock Source Connections
In USBV power supply mode, the PLL is active,
DD
generating a 48MHz clock to the USB. In this
mode, f
can be configured to be up to 8 MHz.
CPU
In V mode the PLL and the USB clock are disa-
DD
bled, and the maximum frequency of f
MHz.
is 6
CPU
OSCIN
OSCOUT
NC
The internal clock signal (f
) is also routed to
CPU
the on-chip peripherals. The CPU clock signal
consists of a square wave with a duty cycle of
50%.
EXTERNAL
CLOCK
The internal oscillator is designed to operate with
an AT-cut parallel resonant quartz in the frequency
range specified for f . The circuit shown in Fig-
osc
Figure 17. Crystal Resonator
ure 17 is recommended when using a crystal, and
Table 7 lists the recommended capacitance. The
crystal and associated components should be
mounted as close as possible to the input pins in
order to minimize output distortion and start-up
stabilisation time.
OSCIN
OSCOUT
Table 7. Recommended Values for 12-MHz
Crystal Resonator
C
C
OSCIN
OSCOUT
R
20 Ω
56pF
56pF
25 Ω
47pF
47pF
70 Ω
22pF
22pF
SMAX
C
OSCIN
C
OSCOUT
Note: R
is the equivalent serial resistor of the
SMAX
crystal (see crystal specification).
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6.2 RESET SEQUENCE MANAGER (RSM)
6.2.1 Introduction
The RESET service routine vector is fixed at ad-
dresses FFFEh-FFFFh in the ST7 memory map.
The reset sequence manager includes three RE-
SET sources as shown in Figure 6.2.2:
The basic RESET sequence consists of 3 phases
as shown in Figure 18:
■ External RESET source pulse
■ Active Phase depending on the RESET source
■ Internal LVD RESET (Low Voltage Detection)
■ Internal WATCHDOG RESET
■ Min 512 CPU clock cycle delay (see Figure 20
and Figure 21
These sources act on the RESET pin and it is al-
ways kept low during the delay phase.
■ RESET vector fetch
Figure 18. RESET Sequences
V
DD
V
V
IT+(LVD)
IT-(LVD)
LVD
RESET
SHORT EXT.
RESET
LONG EXT.
RESET
WATCHDOG
RESET
RUN
RUN
RUN
RUN
RUN
ACTIVE
PHASE
ACTIVE
PHASE
ACTIVE
PHASE
ACTIVE PHASE
t
t
w(RSTL)out
w(RSTL)out
t
h(RSTL)in
t
w(RSTL)out
t
h(RSTL)in
DELAY
EXTERNAL
RESET
SOURCE
RESET PIN
WATCHDOG
RESET
WATCHDOG UNDERFLOW
INTERNAL RESET (min 512 TCPU
VECTOR FETCH
)
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RESET SEQUENCE MANAGER (Cont’d)
6.2.2 Asynchronous External RESET pin
Starting from the external RESET pulse recogni-
tion, the device RESET pin acts as an output that
The RESET pin is both an input and an open-drain
is pulled low during at least t
.
w(RSTL)out
output with integrated R
weak pull-up resistor.
ON
This pull-up has no fixed value but varies in ac-
cordance with the input voltage. It can be pulled
low by external circuitry to reset the device. See
electrical characteristics section for more details.
6.2.3 Internal Low Voltage Detection RESET
Two different RESET sequences caused by the in-
ternal LVD circuitry can be distinguished:
■ Power-On RESET
A RESET signal originating from an external
■ Voltage Drop RESET
source must have a duration of at least t
in
h(RSTL)in
order to be recognized. This detection is asynchro-
nous and therefore the MCU can enter reset state
even in HALT mode.
The device RESET pin acts as an output that is
pulled low when V <V
(rising edge) or
DD
IT+
V
<V (falling edge) as shown in Figure 18.
DD
IT-
The RESET pin is an asynchronous signal which
plays a major role in EMS performance. In a noisy
environment, it is recommended to follow the
guidelines mentioned in the electrical characteris-
tics section.
The LVD filters spikes on V shorter than t
to avoid parasitic resets.
DD
g(VDD)
6.2.4 Internal Watchdog RESET
The RESET sequence generated by a internal
Watchdog counter overflow is shown in Figure 18.
If the external RESET pulse is shorter than
t
(see short ext. Reset in Figure 18), the
w(RSTL)out
Starting from the Watchdog counter underflow, the
device RESET pin acts as an output that is pulled
signal on the RESET pin will be stretched. Other-
wise the delay will not be applied (see long ext.
Reset in Figure 18).
low during at least t
.
w(RSTL)out
Figure 19. Reset Block Diagram
INTERNAL
RESET
V
DD
f
CPU
R
ON
RESET
WATCHDOG RESET
LVD RESET
PULSE
GENERATOR
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RESET SEQUENCE MANAGER (Cont’d)
In stand-alone mode, the 512 CPU clock cycle de-
lay allows the oscillator to stabilize and ensures
that recovery has taken place from the Reset
state.
In USB mode the delay is 256 clock cycles count-
ed from when the PLL LOCK signal goes high.
The RESET vector fetch phase duration is 2 clock
cycles.
Figure 20. Reset Delay in Stand-alone Mode
RESET
FETCH VECTOR
512 x t
DELAY
CPU(STAND-ALONE)
Figure 21. Reset Delay in USB Mode
RESET
PLL Startup
time (undefined)
FETCH VECTOR
256 x t
256 x t
CPU(STAND-ALONE)
DELAY
CPU(USB)
400 µs typ.
Note: For a description of Stand-alone mode and USB mode refer to Section 6.4.
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6.3 LOW VOLTAGE DETECTOR (LVD)
To allow the integration of power management
features in the application, the Low Voltage Detec-
tor function (LVD) generates a static reset when
The LVD Reset circuitry generates a reset when
is below:
V
DD
– V
when V is rising
DD
IT+
the V
supply voltage is below a V reference
DD
IT-
– V when V is falling
IT-
DD
value. This means that it secures the power-up as
well as the power-down, keeping the ST7 in reset.
The LVD function is illustrated in Figure 22.
During a Low Voltage Detector Reset, the RESET
pin is held low, thus permitting the MCU to reset
other devices.
The V reference value for a voltage drop is lower
IT-
than the V reference value for power-on in order
IT+
to avoid a parasitic reset when the MCU starts run-
ning and sinks current on the supply (hysteresis).
Figure 22. Low Voltage Detector vs Reset
V
DD
V
hyst
V
V
IT+(LVD)
IT-(LVD)
RESET
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6.4 POWER SUPPLY MANAGEMENT
6.4.1 Single Power Supply Management
troller can operate in two power supply modes:
Stand-alone Mode and USB Mode. This configura-
tion is only available on devices without LVD (E
suffix). Devices with LVD are kept under reset
when the power supply drops below the LVD
threshold voltage and thus Stand-Alone mode can
not be entered.
In applications operating only when connected to
the USB (Flash writers, Backup systems), the mi-
crocontroller must operate from a single power
supply (i.e. USB bus power supply or the local
power source in the case of self-powered devic-
es). Devices with LVD (no E suffix) or without LVD
(E suffix) can support this configuration.
In order to enable Dual Power Supply Manage-
ment:
In order to enable the Single Power Supply Man-
agement, the PLGIE bit in the PCR register should
kept cleared by software (reset default value).
– the USBEN pin function must be selected by pro-
gramming the option byte.
In this case, pin V
and USBV
of the micro-
– the user software must set the PLGIE bit in the
PCR register in the initialization routine.
DD
DD
controller must be connected together and sup-
plied by a 4.0 to 5.5V voltage supply, either from
the USB cable or from the local power source. See
Figure 23.
Stand-Alone Mode
This mode is to be used when no USB communi-
cation is needed. The microcontroller in this mode
can run at very low voltage, making the design of
low power / battery supplied systems easy. In this
mode:
Figure 23. Single Power Supply Mode
.
– The USB cable is unplugged (no voltage input on
USBV pin)
DD
– The PLL is off
V
DD1
– The on-chip USB interface is disabled
V
V
DD2
– The core can run at up to 6 MHz internal frequen-
cy
DDA
– USBEN is kept floating by H/W.
– The microcontroller is supplied through the V
pin
DD
USBV
DD
USB Mode
ST7
When connected to the USB, the microcontroller
can run at full speed, still saving battery power by
using USB power or self power source. To go into
USB mode, a voltage from 4.0V to 5.5V must be
4.0 - 5.5 V
Note: Ground lines not shown
In this mode:
provided to the USBV pin. In this mode:
DD
– The PLL is running at 48 MHz
– The USB cable is plugged in
– The on-chip USB interface is enabled
– USBV pin is supplied by a 4.0 to 5.5V supply
DD
voltage, either from the USB cable or from the
self powering source
– The core can run at up to 8MHz internal frequen-
cy
– The PLL is running at 48 MHz
– The microcontroller can be either USB bus pow-
ered or supplied by the local power source (self
powered)
– The on-chip USB interface is enabled
– The core can run at up to 8 MHz internal frequen-
cy
– The USBEN function is not used. The PF4 pin
can be configured to work as a normal I/O by pro-
gramming the Option Byte.
– USBEN is set to output low level by hardware.
This signal can be used to control an external
transistor (USB SWITCH) to change the power
supply configuration (see Figure 24).
6.4.2 Dual Power Supply Management
In case of a device that can be used both when
powered by the USB or from a battery (Digital Au-
dio Player, Digital Camera, PDA), the microcon-
– The microcontroller can be USB bus powered
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POWER SUPPLY MANAGEMENT (Cont’d)
6.4.2.1 Switching from Stand-Alone Mode to
USB Mode
During and after this (software induced) reset
phase, the USBEN pin is set to output low level by
hardware. This causes the USB SWITCH to be
In Stand-Alone Mode, when the user plugs in the
turned ON. Consequently, V
USBV supply. See Figure 24.
pin is powered by
DD
USB cable, 4V min. is input to USBV . The on-
DD
DD
chip power Supply Manager generates an internal
interrupt when USBV
reaches USBV
(if the
Once in USB mode, no power is drawn from the
step-up converter output.
DD
IT+
PLGIE bit in the PCR register is set). The user pro-
gram then can finish the current processing, and
MUST generate a software RESET afterwards.
For more details, refer to Figure 25.
This puts the microcontroller into reset state and
all I/O ports go into input high impedance mode.
Figure 24. External Power Supply Switch
Step-up converter
V
DD1
V
V
DD2
Option bit
DDA
General Purpose I/O (I/O port DR, DDR)
Alternate Function (USBEN)
USB SWITCH
USBEN
PMOS
(Note 2)
(True OD, H/W crtl)
EDGE DETECTOR
WITH LATCH
Interrupt Request
USBV
DD
PLG PLGIE
VITPF VITMF
DETEN
4V min. from USB
PCR REGISTER
USB VOLTAGE
DETECTOR
S/W RESET
RESET
LOGIC
USBV
IT+
USBV
IT-
USBEN H/W
CONTROL
ST7
USBV
IT+
USBV
USBV
IT-
DD
PLG bit
VITMF Bit
VITPF Bit
Note 1: Ground lines not shown
Note 2: Suggested device: IRLML6302 (International
rectifier) or Si230DS (Siliconix)
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POWER SUPPLY MANAGEMENT (Cont’d)
6.4.2.2 Switching from USB Mode to Stand-
Alone Mode
During and after this (software induced) reset
phase, the USBEN pin is put in high impedance by
hardware. It causes the USB SWITCH to be
In USB Mode, when the user unplugs the USB ca-
turned OFF, so USBV
is disconnected from
DD
ble, the voltage level drops on the USBV
line.
DD
V
. The PLL is automatically stopped and the in-
DD
The on-chip Power Supply Manager generates a
PLG interrupt when USBV reaches USBV
ternal frequency is provided by a division of the
crystal frequency. Refer to Figure 25.
.
IT-
DD
The user program then can finish the current
processing, and MUST generate a software RE-
SET.
The microcontroller is still powered by the residual
USBV
voltage (higher than step-up converter
DD
set output level). This V voltage decreases dur-
DD
Caution: Care should be taken as during this peri-
od the microcontroller clock is provided from the
PLL output. Functionality in this mode is not guar-
ing the reset phase until it reaches the step-up
converter set output voltage. At that time, step-up
converter resumes operation, and powers the ap-
plication.
anteed for voltages below V
.
PLLmin
Software must ensure that the software RESET is
generated before V . drops below V . Fail-
Caution: In order to avoid applying excessive volt-
age to the Storage Media, a minimum delay must
be ensured during (and after if needed) the reset
phase, prior to switching ON the external STOR-
AGE switch. See Figure 26 and Figure 27.
DD
PLLmin
ing to do this will cause the clock circuitry to stop,
freezing the microcontroller operations.
Once the user program has executed the software
reset, the microcontroller goes into reset state and
all I/O ports go into floating input mode.
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ST7265x
POWER SUPPLY MANAGEMENT (Cont’d)
Figure 25. Power Supply Management: Dual Power Supply
STAND-ALONE
SUPPLY
V
PLLmin48
USBV
IT+
USBV
IT-
SUPPLY
VOLTAGES
USBV
DD
PLG INTERRUPT
REQUEST
RESET
S/W
STAND-ALONE
PROCESSING
USB MODE
PROCESS.
STAND-ALONE MODE
PROCESSING
1
2
1
2
RST
RESET
RESET
RESET
STATUS
USBEN
S/W Reset
S/W Reset
HI-Z
HI-Z
ON
USB MODE
V
IT+(LVD)
STAND-ALONE
STAND-ALONE
V
IT-(LVD)
V
pin
DD
voltage
PLL
ON/OFF
PLL OFF
PLL ON
PLL OFF
UNDE
FINED
48 MHz
SIGNAL
4
STABLE 48 MHz
NO CLOCK
NO CLOCK
3
CLOCK
SOURCE
PLL
CRYSTAL (12MHz)
CRYSTAL (12MHz)
1. Interrupt processing
2. Finish current processing
3. PLL start-up time (automatically controlled by hardware following a software reset)
4. PLL running with frequency in the range of 48 to 24 MHz (see section 13.3.3 on page 131)
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ST7265x
POWER SUPPLY MANAGEMENT (Cont’d)
6.4.3 Storage Media Interface I/Os
USB Mode
The microcontroller is able to drive Storage Media
through an interface operating at a different volt-
age from the rest of the circuit.
– In this case the core of the microcontroller is run-
ning from the USB bus power or the self power
supply. V and USBV pins are supplied with
DD
DD
a voltage from 4.0 to 5.5V.
This is achieved by powering the Storage Media
interface I/O circuitry through a specific supply rail
– The Storage Media Interface can be powered
through the on-chip regulator (providing power to
connected to V
either as an input or output.
pin. The V
pin can be used
DDF
DDF
the I/O pins and output on pin V
) if the current
DDF
requirement is within the output capacity of the
on chip regulator.
If the on-chip voltage regulator is off, power to the
interface I/Os should be provided externally to the
V
pin. This should be the case when in Stand-
– The regulator output voltage can be pro-
grammed to 2.8V, 3.3V, 3.4V or 3.5 Volts, de-
pending on the Storage Media specifications.
(see VSET[1:0] bits in PCR register description)
DDF
Alone Mode, or in USB mode when the current re-
quired to power the Storage Media is above the
current capacity of the on-chip regulator.
If the on-chip voltage regulator is on, it powers the
– Should the current requirement for the Storage
Media be higher than the current capacity of the
on chip regulator, an external regulator should be
used (See Figure 27). Thus the on-chip voltage
regulator must be disabled to avoid any conflict
(reset the REGEN bit in the PCR register).
interface I/Os, and V
pin can supply the Stor-
DDF
age Media. This is recommended in USB Mode,
when the current required to power the Storage
Media is within the capacity of the on-chip regula-
tor.
Application Example:
Stand-Alone Mode
Caution: The user should ensure that V
not exceed the maximum rating specified for the
does
DD
Storage Media V
AGE switch on.
max when switching STOR-
DDF
– The Storage Media interface supply is powered
by V enabled by an external switch (see Fig-
DD
ure 26) which connects V to V
. This switch
DD
DDF
can be driven by any True Open Drain I/O pin
and controlled by user software.
– The on-chip voltage regulator must be disabled
to avoid any conflict and to decrease consump-
tion (reset the REGEN bit in the PCR register).
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ST7265x
POWER SUPPLY MANAGEMENT (Cont’d)
Figure 26. Storage Media Interface Supply Switch (for low current Media)
V
V
DD1
DD
(2.7V - 5.5V)
V
V
DD2
DDA
The on-chip Regulator
supplies the Storage Media
I/F in USB mode
PMOS
This Switch is turned ON to
STORAGE SWITCH
I/O pin
(True OD)
power Storage Media I/F
in Stand-Alone Mode
VOLTAGE REGULATOR
2.8V, 3.3V, 3.4V or 3.5V
V
DDF
I/O LOGIC
STORAGE MEDIA STORAGE MEDIA I/Os
LEVEL TRANSLATOR
ST7
Note: Ground lines not shown
Figure 27. Storage Media Interface Supply Switch (for high current Media)
V
DD
(2.7V - 5.5V)
V
DD1
This Switch is turned ON to
V
V
power Storage Media I/F
in Stand-Alone Mode
DD2
DDA
PMOS
This supply is not used
and MUST be disabled
STORAGE SWITCH
I/O pin
(True OD)
This Regulator
REGUL
supplies the Storage Media
I/F in USB Mode
VOLTAGE REGULATOR
2.8V, 3.3V, 3.4V or 3.5V
V
DDF
I/O LOGIC
STORAGE MEDIA STORAGE MEDIA I/Os
LEVEL TRANSLATOR
ST7
Note: Ground lines not shown
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ST7265x
POWER SUPPLY MANAGEMENT (Cont’d)
6.4.4 Power Management Application Example
must be capable of tolerating voltages up to 5.5V
on its Vout pin.
In the example shown in Figure 28, the V supply
DD
is provided by a step up. In this case the step up
Figure 28. Dual Power Supply Application Example (low current Storage Media)
50µH
1.2V
Step Up
USBV Switch
DD
10µF
USBEN
V
DD
USBV
DD
USBVDD
=4.0-5.5V
4.7µF
USB port
USB
VCC
5V
USB
DP
DP
DM
DM
POWER
MANAGEMENT
USB
GND
GND
I/O
LOGIC
DEC Switch
Audio
AMP
KEYBOARD
I2C
2
I C
2
DAC
LED
THRESH
2
DTC
I S
4
FLASH
12V for
Flash prog.
MPEG
VPP
REGULATOR
MP3
1.5Mbit/s Max
Decoder
STA013
V
level translator
DDF
Cbus=40pF max
STORAGE Switch
100nF
4.7µF
LCD DISPLAY
LIGHT
STORAGE
MEDIA
Vdd in Stand-Alone mode
Regulator output (2.8 - 3.5V) in USB mode
2M - 128MByte
TDA7474
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ST7265x
POWER SUPPLY MANAGEMENT (Cont’d)
6.4.5 Register Description
Bit 3:2 = VSET[1:0] Voltage Regulator Output
Voltage.
POWER CONTROL REGISTER (PCR)
Reset Value: 0000 0000 (00h)
These bits are set and cleared by software to se-
lect the output voltage of the on-chip voltage regu-
7
0
lator (for the V
output).
DDF
VSE VSE
ITM
F
PLG VSE VSE DET REG
IE T1 T0 EN EN
Voltage output of the regulator
ITPF
PLG
T1
T0
0
0
3.5V
3.4V
3.3V
2.8V
Bit 7 = ITPF Voltage Input Threshold Plus Flag
This bit is set by hardware when USBV rises
0
1
DD
1
0
over USBV and cleared by hardware when US-
IT+
1
1
BV drops below USBV
.
DD
IT+
0: USBV < USBV
DD
IT+
IT+
1:USBV > USBV
DD
Bit 1 = DETEN USB Voltage Detector Enable.
This bit is set and cleared by software. It is used to
power-off the USB voltage detector in Stand-alone
mode.
0: The USB voltage detector is enabled.
1: The USB voltage detector disabled (ITPF, ITMF
and PLG bits are forced high)
Bit 6 = ITMF Voltage Input Threshold Minus Flag
This bit is set by hardware when USBV rises
DD
over USBV and cleared by hardware when US-
IT-
BV drops below USBV
.
DD
IT-
0: USBV < USBV
DD
IT-
1:USBV > USBV
DD
IT-
Bit 0 = REGEN Voltage Regulator Enable.
This bit is set and cleared by software.
0: The regulator is completely shutdown and no
current is drawn from the power supply by the
voltage reference.
Bit 5 = PLG USB Plug/Unplug detection.
This bit is set by hardware when it detects that the
USB cable has been plugged in. It is cleared by
hardware when the USB cable is unplugged. (De-
tection happens when USBV
rises over USB-
1: The on-chip voltage regulator is powered-on.
DD
V
or when USBV
drops below USBV ). If
IT+
DD IT-
the PLGIE bit is set, the rising edge of the PLG bit
also generates an interrupt request.
0: USB cable unplugged
1: USB cable plugged in
Bit 4 = PLGIE USB Plug/Unplug Interrupt Enable.
This bit is set and cleared by software.
0: Single supply mode: PLG interrupt disabled.
1: Dual supply mode: PLG interrupt enabled (gen-
erates an interrupt on the rising edge of PLG).
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ST7265x
7 INTERRUPTS
7.1 INTRODUCTION
When an interrupt request has to be serviced:
– Normal processing is suspended at the end of
the current instruction execution.
The CPU enhanced interrupt management pro-
vides the following features:
– The PC, X, A and CC registers are saved onto
the stack.
■ Hardware interrupts
■ Software interrupt (TRAP)
■ Nested or concurrent interrupt management
with flexible interrupt priority and level
management:
– I1 and I0 bits of CC register are set according to
the corresponding values in the ISPRx registers
of the serviced interrupt vector.
– The PC is then loaded with the interrupt vector of
the interrupt to service and the first instruction of
the interrupt service routine is fetched (refer to
“Interrupt Mapping” table for vector addresses).
– Up to 4 software programmable nesting levels
– Up to 16 interrupt vectors fixed by hardware
– 3 non maskable events: RESET, TRAP, TLI
This interrupt management is based on:
The interrupt service routine should end with the
IRET instruction which causes the contents of the
saved registers to be recovered from the stack.
– Bit 5 and bit 3 of the CPU CC register (I1:0),
– Interrupt software priority registers (ISPRx),
Note: As a consequence of the IRET instruction,
the I1 and I0 bits will be restored from the stack
and the program in the previous level will resume.
– Fixed interrupt vector addresses located at the
high addresses of the memory map (FFE0h to
FFFFh) sorted by hardware priority order.
This enhanced interrupt controller guarantees full
upward compatibility with the standard (not nest-
ed) CPU interrupt controller.
Table 8. Interrupt Software Priority Levels
Interrupt software priority Level
I1
1
0
0
1
I0
0
1
0
1
Level 0 (main)
Level 1
Low
7.2 MASKING AND PROCESSING FLOW
Level 2
The interrupt masking is managed by the I1 and I0
bits of the CC register and the ISPRx registers
which give the interrupt software priority level of
each interrupt vector (see Table 8). The process-
ing flow is shown in Figure 29.
Level 3 (= interrupt disable)
High
Figure 29. Interrupt Processing Flowchart
PENDING
INTERRUPT
Y
Y
RESET
TLI
N
Interrupt has the same or a
lower software priority
than current one
N
I1:0
FETCH NEXT
INSTRUCTION
THE INTERRUPT
STAYS PENDING
Y
“IRET”
N
RESTORE PC, X, A, CC
FROM STACK
EXECUTE
INSTRUCTION
STACK PC, X, A, CC
LOAD I1:0 FROM INTERRUPT SW REG.
LOAD PC FROM INTERRUPT VECTOR
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INTERRUPTS (Cont’d)
Servicing Pending Interrupts
■ TLI (Top Level Hardware Interrupt)
As several interrupts can be pending at the same
time, the interrupt to be taken into account is deter-
mined by the following two-step process:
This hardware interrupt occurs when a specific
edge is detected on the dedicated TLI pin.
Caution: A TRAP instruction must not be used in a
TLI service routine.
– the highest software priority interrupt is serviced,
■ TRAP (Non Maskable Software Interrupt)
– if several interrupts have the same software pri-
ority then the interrupt with the highest hardware
priority is serviced first.
This software interrupt is serviced when the TRAP
instruction is executed. It will be serviced accord-
ing to the flowchart in Figure 29 as a TLI.
Figure 30 describes this decision process.
Caution: TRAP can be interrupted by a TLI.
■ RESET
Figure 30. Priority Decision Process
The RESET source has the highest priority in the
CPU. This means that the first current routine has
the highest software priority (level 3) and the high-
est hardware priority.
PENDING
INTERRUPTS
See the RESET chapter for more details.
Different
Same
SOFTWARE
PRIORITY
Maskable Sources
Maskable interrupt vector sources can be serviced
if the corresponding interrupt is enabled and if its
own interrupt software priority (in ISPRx registers)
is higher than the one currently being serviced (I1
and I0 in CC register). If any of these two condi-
tions is false, the interrupt is latched and thus re-
mains pending.
HIGHEST SOFTWARE
PRIORITY SERVICED
HIGHEST HARDWARE
PRIORITY SERVICED
■ External Interrupts
External interrupts allow the processor to exit from
HALT low power mode.
External interrupt sensitivity is software selectable
through the ISx bits in the MISCR1 and MISCR3
registers.
When an interrupt request is not serviced immedi-
ately, it is latched and then processed when its
software priority combined with the hardware pri-
ority becomes the highest one.
External interrupt triggered on edge will be latched
and the interrupt request automatically cleared
upon entering the interrupt service routine.
If several input pins of a group connected to the
same interrupt line are selected simultaneously,
these will be logically NANDed.
Note 1: The hardware priority is exclusive while
the software one is not. This allows the previous
process to succeed with only one interrupt.
Note 2: RESET, TRAP and TLI can be considered
as having the highest software priority in the deci-
sion process.
■ Peripheral Interrupts
Different Interrupt Vector Sources
Usually the peripheral interrupts cause the Device
to exit from HALT mode except those mentioned in
the “Interrupt Mapping” table.
A peripheral interrupt occurs when a specific flag
is set in the peripheral status registers and if the
corresponding enable bit is set in the peripheral
control register.
Two interrupt source types are managed by the
CPU interrupt controller: the non-maskable type
(RESET, TRAP, TLI) and the maskable type (ex-
ternal or from internal peripherals).
Non-Maskable Sources
These sources are processed regardless of the
state of the I1 and I0 bits of the CC register (see
Figure 29). After stacking the PC, X, A and CC
registers (except for RESET), the corresponding
vector is loaded in the PC register and the I1 and
I0 bits of the CC are set to disable interrupts (level
3). These sources allow the processor to exit
HALT mode.
The general sequence for clearing an interrupt is
based on an access to the status register followed
by a read or write to an associated register.
Note: The clearing sequence resets the internal
latch. A pending interrupt (i.e. waiting for being
serviced) will therefore be lost if the clear se-
quence is executed.
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INTERRUPTS (Cont’d)
7.3 INTERRUPTS AND LOW POWER MODES
7.4 CONCURRENT & NESTED MANAGEMENT
All interrupts allow the processor to exit the WAIT
low power mode. On the contrary, only external
and other specified interrupts allow the processor
to exit from the HALT modes (see column “Exit
from HALT” in “Interrupt Mapping” table). When
several pending interrupts are present while exit-
ing HALT mode, the first one serviced can only be
an interrupt with exit from HALT mode capability
and it is selected through the same decision proc-
ess shown in Figure 30.
The following Figure 31 and Figure 32 show two
different interrupt management modes. The first is
called concurrent mode and does not allow an in-
terrupt to be interrupted, unlike the nested mode in
Figure 32. The interrupt hardware priority is given
in this order from the lowest to the highest: MAIN,
IT4, IT3, IT2, IT1, IT0, TLI. The software priority is
given for each interrupt.
Warning: A stack overflow may occur without no-
tifying the software of the failure.
Note: If an interrupt, that is not able to Exit from
HALT mode, is pending with the highest priority
when exiting HALT mode, this interrupt is serviced
after the first one serviced.
Figure 31. Concurrent Interrupt Management
SOFTWARE
PRIORITY
LEVEL
I1
I0
TLI
3
1 1
1 1
1 1
1 1
1 1
1 1
IT0
3
IT1
IT1
3
IT2
3
IT3
3
RIM
IT4
3
MAIN
MAIN
3/0
11 / 10
10
Figure 32. Nested Interrupt Management
SOFTWARE
PRIORITY
LEVEL
I1
I0
TLI
3
1 1
1 1
0 0
0 1
1 1
1 1
IT0
3
IT1
IT1
IT2
2
IT2
1
IT3
3
RIM
IT4
IT4
3
MAIN
MAIN
3/0
11 / 10
10
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INTERRUPTS (Cont’d)
7.5 INTERRUPT REGISTER DESCRIPTION
INTERRUPT SOFTWARE PRIORITY REGIS-
TERS (ISPRX)
CPU CC REGISTER INTERRUPT BITS
Read/Write
Read/Write (bit 7:4 of ISPR3 are read only)
Reset Value: 1111 1111 (FFh)
Reset Value: 111x 1010 (xAh)
7
0
7
0
ISPR0
ISPR1
I1_3 I0_3 I1_2 I0_2 I1_1 I0_1 I1_0 I0_0
I1_7 I0_7 I1_6 I0_6 I1_5 I0_5 I1_4 I0_4
1
1
I1
H
I0
N
Z
C
Bit 5, 3 = I1, I0 Software Interrupt Priority
ISPR2 I1_11 I0_11 I1_10 I0_10 I1_9 I0_9 I1_8 I0_8
These two bits indicate the current interrupt soft-
ware priority.
ISPR3
1
1
1
1
I1_13 I0_13 I1_12 I0_12
Interrupt Software Priority Level
I1
1
0
0
1
I0
0
Level 0 (main)
Level 1
Low
These four registers contain the interrupt software
priority of each interrupt vector.
1
Level 2
0
– Each interrupt vector (except RESET and TRAP)
has corresponding bits in these registers where
its own software priority is stored. This corre-
spondance is shown in the following table.
Level 3 (= interrupt disable*)
High
1
These two bits are set/cleared by hardware when
entering in interrupt. The loaded value is given by
the corresponding bits in the interrupt software pri-
ority registers (ISPRx).
Vector address
ISPRx bits
FFFBh-FFFAh
FFF9h-FFF8h
...
I1_0 and I0_0 bits*
I1_1 and I0_1 bits
...
They can be also set/cleared by software with the
RIM, SIM, HALT, WFI, IRET and PUSH/POP in-
structions (see “Interrupt Dedicated Instruction
Set” table).
FFE1h-FFE0h
I1_13 and I0_13 bits
*Note: TLI, TRAP and RESET events can interrupt
a level 3 program.
– Each I1_x and I0_x bit value in the ISPRx regis-
ters has the same meaning as the I1 and I0 bits
in the CC register.
– Level 0 can not be written (I1_x=1, I0_x=0). In
this case, the previously stored value is kept. (ex-
ample: previous=CFh, write=64h, result=44h)
The RESET, TRAP and TLI vectors have no soft-
ware priorities. When one is serviced, the I1 and I0
bits of the CC register are both set.
*Note: Bits in the ISPRx registers which corre-
spond to the TLI can be read and written but they
are not significant in the interrupt process man-
agement.
Caution: If the I1_x and I0_x bits are modified
while the interrupt x is executed the following be-
haviour has to be considered: If the interrupt x is
still pending (new interrupt or flag not cleared) and
the new software priority is higher than the previ-
ous one, the interrupt x is re-entered. Otherwise,
the software priority stays unchanged up to the
next interrupt request (after the IRET of the inter-
rupt x).
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INTERRUPTS (Cont’d)
Table 9. Dedicated Interrupt Instruction Set
Instruction
HALT
IRET
New Description
Entering Halt mode
Function/Example
I1
1
H
I0
0
N
Z
C
Interrupt routine return
Jump if I1:0=11
Pop CC, A, X, PC
I1:0=11 ?
I1
H
I0
N
Z
C
JRM
JRNM
POP CC
RIM
Jump if I1:0<>11
I1:0<>11 ?
Pop CC from the Stack
Enable interrupt (level 0 set)
Disable interrupt (level 3 set)
Software trap
Mem => CC
I1
1
1
1
1
H
I0
0
1
1
0
N
Z
C
Load 10 in I1:0 of CC
Load 11 in I1:0 of CC
Software NMI
SIM
TRAP
WFI
Wait for interrupt
Note: During the execution of an interrupt routine, the HALT, POPCC, RIM, SIM and WFI instructions
change the current software priority up to the next IRET instruction or one of the previously mentioned
instructions.
In order not to lose the current software priority level, the RIM, SIM, HALT, WFI and POP CC instructions
should never be used in an interrupt routine.
Table 10. Interrupt Mapping
Exit
from
HALT
Source
Block
Register Priority
Address
Vector
N°
Description
Label
Order
RESET
TRAP
ICP
Reset
yes
no
FFFEh-FFFFh
FFFCh-FFFDh
FFFAh-FFFBh
FFF8h-FFF9h
FFF6h-FFF7h
FFF4h-FFF5h
FFF2h-FFF3h
FFF0h-FFF1h
FFEEh-FFEFh
FFECh-FFEDh
FFEAh-FFEBh
FFE8h-FFE9h
FFE6h-FFE7h
Highest
Priority
Software Interrupt
N/A
0
1
Flash Start Programming NMI Interrupt
Power Management USB Plug/Unplug
External Interrupt Port A
yes
yes
yes
no
PLG
PCR
N/A
2
EI0
3
DTC
USB
ESUSP
EI1
DTC Peripheral Interrupt
DTCSR
USBISTR
USBISTR
N/A
4
USB Peripheral Interrupt
no
5
USB End Suspend Interrupt
External Interrupt Port D
yes
yes
no
6
2
2
7
I C
I C Interrupt
I2CSRx
TSR
8
TIM
EI2
SPI
Timer interrupt
no
Lowest
Priority
9
External Interrupt Port C
SPI interrupt
N/A
yes
yes
10
SPICSR
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ST7265x
INTERRUPTS (Cont’d)
Table 11. Nested Interrupts Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
DTC
EI0
EI1
SPI
PLG
ISP
USB
TIM
002Ch
002Dh
002Eh
002Fh
I1_3
1
I0_3
1
I1_2
1
I0_2
1
I1_1
1
I0_1
1
ISPR0
Reset Value
1
1
2
I C
ESUSP
I1_5
I1_7
1
I0_7
1
I1_6
1
I0_6
1
I0_5
1
I1_4
1
I0_4
1
ISPR1
Reset Value
1
Not used
EI2
I1_11
I0_11
1
I1_10
1
I0_10
1
I1_9
1
I0_9
1
I1_8
1
I0_8
1
ISPR2
Reset Value
1
1
Not used
Not used
I1_13
1
I0_13
1
I1_12
1
I0_12
1
ISPR3
Reset Value
1
1
1
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8 POWER SAVING MODES
8.1 INTRODUCTION
Figure 33. WAIT Mode Flow Chart
To give a large measure of flexibility to the applica-
tion in terms of power consumption, two main pow-
er saving modes are implemented in the ST7.
WFI INSTRUCTION
After a RESET the normal operating mode is se-
lected by default (RUN mode). This mode drives
the device (CPU and embedded peripherals) by
means of a master clock which is based on the
OSCILLATOR
PERIPH. CLOCK
CPU CLOCK
I1:0] BITS
ON
ON
main oscillator frequency divided by 2 (f
).
CPU
OFF
From Run mode, the different power saving
modes may be selected by setting the relevant
register bits or by calling the specific ST7 software
instruction whose action depends on the oscillator
status.
CLEARED
The user can also switch off any unused on-chip
peripherals individually by programming the
MISCR2 register.
N
RESET
N
8.2 WAIT MODE
Y
INTERRUPT
Y
WAIT mode places the MCU in a low power con-
sumption mode by stopping the CPU.
This power saving mode is selected by calling the
“WFI” ST7 software instruction.
OSCILLATOR
ON
ON
All peripherals remain active. During WAIT mode,
the I1:0] bits in the CC register are forced to 0, to
enable all interrupts. All other registers and mem-
ory remain unchanged. The MCU remains in WAIT
mode until an interrupt or Reset occurs, whereup-
on the Program Counter branches to the starting
address of the interrupt or Reset service routine.
The MCU will remain in WAIT mode until a Reset
or an Interrupt occurs, causing it to wake up.
PERIPH. CLOCK
CPU CLOCK
I1:0] BITS
ON
SET
IF RESET
DELAY
(Refer to Figure 20 and
Figure 21)
Refer to Figure 33.
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Note: Before servicing an interrupt, the CC
register is pushed on the stack. The I1:0] bits are
set during the interrupt routine and cleared
when the CC register is popped.
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ST7265x
POWER SAVING MODES (Cont’d)
8.3 HALT MODE
Figure 34. HALT Mode Flow Chart
The HALT mode is the MCU lowest power con-
sumption mode. The HALT mode is entered by ex-
ecuting the HALT instruction. The internal oscilla-
tor is then turned off, causing all internal process-
ing to be stopped, including the operation of the
on-chip peripherals.
HALT INSTRUCTION
OSCILLATOR
PERIPH. CLOCK
CPU CLOCK
I1:0] BITS
OFF
When entering HALT mode, the I[1:0] bits in the
Condition Code Register are cleared. Thus, any of
the external interrupts (ITi or USB end suspend
mode), are allowed and if an interrupt occurs, the
CPU clock becomes active.
OFF
OFF
CLEARED
The MCU can exit HALT mode on reception of ei-
ther an external interrupt on ITi, an end suspend
mode interrupt coming from USB peripheral, an
SPI interrupt or a reset. The oscillator is then
turned on and a stabilization time is provided be-
fore releasing CPU operation. The stabilization
time is 512 CPU clock cycles.
After the start up delay, the CPU continues opera-
tion by servicing the interrupt which wakes it up or
by fetching the reset vector if a reset wakes it up.
N
RESET
N
EXTERNAL
Y
INTERRUPT*
Y
OSCILLATOR
ON
ON
ON
SET
PERIPH. CLOCK
CPU CLOCK
I1:0] BITS
DELAY
(Refer to Figure 20 and
Figure 21)
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Note: Before servicing an interrupt, the CC
register is pushed on the stack. TheI1:0] bits are
set during the interrupt routine and cleared
when the CC register is popped.
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ST7265x
9 I/O PORTS
9.1 INTRODUCTION
External interrupt function
When an I/O is configured as Input with Interrupt,
an event on this I/O can generate an external inter-
rupt request to the CPU.
Important note:
Please note that the I/O port configurations of this
device differ from those of the other ST7 devices.
Each pin can independently generate an interrupt
request. The interrupt sensitivity is independently
programmable using the sensitivity bits in the Mis-
cellaneous register.
The I/O ports offer different functional modes:
– transfer of data through digital inputs and outputs
and for specific pins:
Each external interrupt vector is linked to a dedi-
cated group of I/O port pins (see pinout description
and interrupt section). If several input pins are se-
lected simultaneously as interrupt source, these
are logically NANDed and inverted. For this rea-
son if one of the interrupt pins is tied low, it masks
the other ones.
– external interrupt generation
– alternate signal input/output for the on-chip pe-
ripherals.
An I/O port contains up to 8 pins. Each pin can be
programmed independently as digital input (with or
without interrupt generation) or digital output.
In case of a floating input with interrupt configura-
tion, special care must be taken when changing
the configuration (see Figure 36).
9.2 FUNCTIONAL DESCRIPTION
Each port has 2 main registers:
– Data Register (DR)
The external interrupts are hardware interrupts,
which means that the request latch (not accessible
directly by the application) is automatically cleared
when the corresponding interrupt vector is
fetched. To clear an unwanted pending interrupt
by software, the sensitivity bits in the Miscellane-
ous register must be modified.
– Data Direction Register (DDR)
and one optional register:
– Option Register (OR)
Each I/O pin may be programmed using the corre-
sponding register bits in the DDR and OR regis-
ters: bit X corresponding to pin X of the port. The
same correspondence is used for the DR register.
9.2.2 Output Modes
Two different output modes can be selected by
software through the OR register: Output push-pull
and open-drain.
The following description takes into account the
OR register, (for specific ports which do not pro-
vide this register refer to the I/O Port Implementa-
tion section). The generic I/O block diagram is
shown in Figure 35
DR register value and output pin status:
DR
0
Push-pull
Open-drain
Vss
V
V
SS
DD
9.2.1 Input Modes
1
Floating
The input configuration is selected by clearing the
corresponding DDR register bit.
The output configuration is selected by setting the
corresponding DDR register bit. In this case, writ-
ing the DR register applies this digital value to the
I/O pin through the latch. Reading the DR register
returns the digital value present on the external I/O
pin. Consequently even in output mode a value
written to an open drain port may differ from the
value read from the port. For example, if software
writes a ‘1’ in the latch, this value will be applied to
the pin, but the pin may stay at ‘0’ depending on
the state of the external circuitry. For this reason,
bit manipulation even using instructions like BRES
and BSET must not be used on open drain ports
as they work by reading a byte, changing a bit and
writing back a byte. A workaround for applications
requiring bit manipulation on Open Drain I/Os is
given in Section 9.2.4.
In this case, reading the DR register returns the
digital value applied to the external I/O pin.
Different input modes can be selected by software
through the OR register.
Notes:
1. Writing the DR register modifies the latch value
but does not affect the pin status.
2. When switching from input to output mode, the
DR register has to be written first to drive the cor-
rect level on the pin as soon as the port is config-
ured as an output.
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ST7265x
I/O PORTS (Cont’d)
put floating mode.
CAUTION: The alternate function must not be ac-
tivated as long as the pin is configured as input
with interrupt, in order to avoid generating spurious
interrupts.
9.2.3 Alternate Functions
When an on-chip peripheral is configured to use a
pin, the alternate function is automatically select-
ed. This alternate function takes priority over the
standard I/O programming.
Analog alternate function
When the pin is used as an ADC input, the I/O
must be configured as floating input. The analog
multiplexer (controlled by the ADC registers)
switches the analog voltage present on the select-
ed pin to the common analog rail which is connect-
ed to the ADC input.
When the signal is coming from an on-chip periph-
eral, the I/O pin is automatically configured in out-
put mode (push-pull or open drain according to the
peripheral).
When the signal is going to an on-chip peripheral,
the I/O pin must be configured in input mode. In
this case, the pin state is also digitally readable by
addressing the DR register.
It is recommended not to change the voltage level
or loading on any port pin while conversion is in
progress. Furthermore it is recommended not to
have clocking pins located close to a selected an-
alog pin.
Note: Input pull-up configuration can cause unex-
pected value at the input of the alternate peripheral
input. When an on-chip peripheral use a pin as in-
put and output, this pin has to be configured in in-
WARNING: The analog input voltage level must
be within the limits stated in the absolute maxi-
mum ratings.
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ST7265x
I/O PORTS (Cont’d)
Figure 35. I/O Port General Block Diagram
ALTERNATE
OUTPUT
1
0
REGISTER
ACCESS
P-BUFFER
(see table below)
V
DD
ALTERNATE
ENABLE
PULL-UP
(see table below)
DR
DDR
OR
V
DD
PULL-UP
CONFIGURATION
PAD
If implemented
OR SEL
DDR SEL
DR SEL
N-BUFFER
DIODES
(see table below)
ANALOG
INPUT
CMOS
SCHMITT
TRIGGER
ALTERNATE
INPUT
EXTERNAL
INTERRUPT
SOURCE (ei )
FROM
OTHER
BITS
x
POLARITY
SELECTION
Table 12. I/O Port Mode Options
Configuration Mode
Diodes
Pull-Up
P-Buffer
to V
to V
SS
DD
Floating with/without Interrupt
Pull-up with/without Interrupt
Push-pull
Off
On
Input
Off
On
On
Off
On
Off
NI
Output
Open Drain (logic level)
True Open Drain
NI
NI (see note)
Legend: NI - not implemented
Off - implemented not activated
On - implemented and activated
Note: The diode to V is not implemented in the true open drain pads. A local protection between the
DD
pad and V is implemented to protect the device against positive stress.
SS
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ST7265x
I/O PORTS (Cont’d)
Table 13. I/O Port Configurations
Hardware Configuration
DR REGISTER ACCESS
W
NOT IMPLEMENTED IN
TRUE OPEN DRAIN
I/O PORTS
V
DD
PULL-UP
CONFIGURATION
R
PU
DR
REGISTER
DATA BUS
PAD
R
ALTERNATE INPUT
FROM
OTHER
PINS
EXTERNAL INTERRUPT
SOURCE (ei )
x
INTERRUPT
CONFIGURATION
POLARITY
SELECTION
ANALOG INPUT
NOT IMPLEMENTED IN
TRUE OPEN DRAIN
I/O PORTS
V
DD
DR REGISTER ACCESS
R
R
PU
PAD
W
DR
REGISTER
DATA BUS
ALTERNATE
ENABLE
ALTERNATE
OUTPUT
NOT IMPLEMENTED IN
TRUE OPEN DRAIN
I/O PORTS
DR REGISTER ACCESS
V
DD
R
PU
R
PAD
W
DR
REGISTER
DATA BUS
ALTERNATE
ENABLE
ALTERNATE
OUTPUT
Notes:
1. When the I/O port is in input configuration and the associated alternate function is enabled as an output,
reading the DR register will read the alternate function output status.
2. When the I/O port is in output configuration and the associated alternate function is enabled as an input,
the alternate function reads the pin status given by the DR register content.
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I/O PORTS (Cont’d)
9.2.4 Bit manipulation on Open Drain Outputs
Switching these I/O ports from one state to anoth-
er should be done in a sequence that prevents un-
wanted side effects. Recommended safe transi-
tions are illustrated in Figure 36 Other transitions
are potentially risky and should be avoided, since
they are likely to present unwanted side-effects
such as spurious interrupt generation.
As mentioned in Section 9.2.2, software should
avoid using bit manipulation instructions on the DR
register in open drain output mode, but must al-
ways access it using byte instructions. If bit manip-
ulation is needed, the solution is to use a copy of
the DR register in RAM, change the bits (using
BRES or BCLR instructions for example) and copy
the whole byte into the DR register each time the
value has to be output on a port. This way, no bit
manipulation is performed on the DR register but
each bit of the DR register can be controlled sepa-
rately.
Figure 36. Interrupt I/O Port State Transitions
01
00
10
11
INPUT
floating/pull-up
interrupt
INPUT
floating
(reset state)
OUTPUT
open-drain
OUTPUT
push-pull
9.3 I/O PORT IMPLEMENTATION
= DDR, OR
XX
The hardware implementation on each I/O port de-
pends on the settings in the DDR and OR registers
and specific feature of the I/O port such as ADC In-
put or true open drain.
The I/O port register configurations are summa-
rized as follows.
Port B (without Option Register)
PB[7:0]
MODE
DDR
floating input
0
1
push-pull output
Table 14. Port Configuration (with Option Register)
Input
Output
Port
Pin name
OR = 0
OR = 1
OR = 0
OR = 1
High-Sink
floating
with interrupt
Port A
PA7:0
floating
open drain
push-pull
No
floating
with interrupt
PC7:4
floating
floating
floating
push-pull
push-pull
No
Port C
Port D
floating
with interrupt
PC3:0
Yes
floating
with interrupt
PD7:0
PE7:6
open drain
open drain
push-pull
push-pull
No
floating
Yes
with pull-up, if se- open drain (with
lected by option pull-up, if select-
byte see Section ed by option byte
PE5
floating
push-pull
Yes
Port E
Port F
15.1)
see Section 15.1)
PE4:3
PE2:0
PF6:4
PF3:2
PF1:0
floating
floating
floating
floating
floating
open drain
push-pull
push-pull
No
Yes
Yes
No
open drain
True open drain
push-pull
True open drain
Yes
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I/O PORTS (Cont’d)
9.4 Register Description
DATA REGISTER (DR)
OPTION REGISTER (OR)
Port x Option Register
PxOR with x = A, C, D, or E
Port x Data Register
PxDR with x = A, B, C, D, E or F.
Read/Write
Reset Value: 0000 0000 (00h)
Read/Write
Reset Value: 0000 0000 (00h)
7
0
7
0
O7
O6
O5
O4
O3
O2
O1
O0
D7
D6
D5
D4
D3
D2
D1
D0
Bits 7:0 = O[7:0] Option register 8 bits.
For specific I/O pins, this register is not implement-
ed. In this case the DDR register is enough to se-
lect the I/O pin configuration.
Bits 7:0 = D[7:0] Data register 8 bits.
The DR register has a specific behaviour accord-
ing to the selected input/output configuration. Writ-
ing the DR register is always taken into account
even if the pin is configured as an input; this allows
to always have the expected level on the pin when
toggling to output mode. Reading the DR register
always returns the digital value applied to the I/O
pin (pin configured as input).
The OR register allows to distinguish: in input
mode if the interrupt capability or the basic config-
uration is selected, in output mode if the push-pull
or open drain configuration is selected.
Each bit is set and cleared by software.
Input mode:
0: Floating input
1: Floating input with interrupt (ports A, C and D).
For port E configuration, refer to Table 14.
DATA DIRECTION REGISTER (DDR)
Port x Data Direction Register
PxDDR with x = A, B, C, D, E or F.
Output mode:
0: Output open drain (with P-Buffer deactivated)
1: Output push-pull
Read/Write
Reset Value: 0000 0000 (00h)
7
0
DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0
Bits 7:0 = DD[7:0] Data direction register 8 bits.
The DDR register gives the input/output direction
configuration of the pins. Each bit is set and
cleared by software.
0: Input mode
1: Output mode
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ST7265x
I/O PORTS (Cont’d)
Table 15. I/O Port Register Map and Reset Values
Address
Register
Label
7
6
5
4
3
2
1
0
(Hex.)
Reset Value
of all I/O port registers
0
0
0
0
0
0
0
0
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
0010h
PADR
PADDR
PAOR
PBDR
MSB
MSB
LSB
LSB
PBDDR
Unused
PCDR
PCDDR
PCOR
PDDR
PDDDR
PDOR
PEDR
MSB
MSB
LSB
LSB
PEDDR
PEOR
PFDR
MSB
MSB
LSB
LSB
PFDDR
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10 MISCELLANEOUS REGISTERS
Bits 2:1 = CP[1:0] CPU clock prescaler
MISCELLANEOUS REGISTER 1 (MISCR1)
Read/Write
These bits select the CPU clock prescaler which is
applied in the different slow modes. Their action is
conditioned by the setting of the CPEN bit. These
two bits are set and cleared by software
Reset Value: 0000 0000 (00h)
7
0
Operating Mode
f
CP1 CP0 CPEN
CPU
3 MHz
x
0
1
0
1
x
0
1
0
1
x
0
0
1
1
x
0
0
1
1
0
1
1
1
1
0
1
1
1
1
IS11 IS10 MCO IS21 IS20 CP1 CP0 CPEN
6 MHz*
1.5 MHz
750 KHz
375 KHz
6 MHz
Stand-alone mode
Bits 7:6 = IS1[1:0] ei0 Interrupt sensitivity
Interrupt sensitivity, defined using the IS1[1:0] bits,
is applied to the ei0 interrupts (Port A):
(f
= 12 MHz)
OSC
IS11 IS10
External Interrupt Sensitivity
Falling edge & low level
Rising edge only
8 MHz
0
0
1
1
0
1
0
1
USB mode
2 MHz
(48 MHz PLL)
1 MHz
Falling edge only
250 KHz
Rising and falling edge
Caution:
These 2 bits can be written only when I1 and I0 of
the CC register are both set to 1 (level 3).
– The ST7 core is not able to read or write in the
USB data buffer if the ST7265x is configured at 6
MHz in standalone mode.
Bit 5 = MCO Main clock out selection
This bit enables the MCO alternate function on the
I/O port. It is set and cleared by software.
0: MCO alternate function disabled (I/O pin free for
general-purpose I/O)
– In USB mode, with f
≤ 2 MHz, if the ST7 core
CPU
accesses the USB data buffer, this may prevent
the USB interface from accessing the buffer, re-
sulting in a USB buffer overrun error. This is be-
cause an access to memory lasts one cycle and
the USB has to send/receive at a fixed baud rate.
1: MCO alternate function enabled (f
I/O port)
output on
CPU
Bits 4:3 = IS2[1:0] ei1 Interrupt sensitivity
Interrupt sensitivity, defined using the IS2[1:0] bits,
is applied to the ei1 external interrupts (Port D):
Bit 0 = CPEN Clock Prescaler Enable
This bit is set and cleared by software. It is used
with the CP[1:0] bits to configure the internal clock
frequency.
IS21 IS20
External Interrupt Sensitivity
Falling edge & low level
Rising edge only
0
0
1
1
0
1
0
1
0: Default f
used (3 or 6 MHz)
CPU
1: f
determined by CP[1:0] bits
CPU
Falling edge only
Rising and falling edge
These 2 bits can be written only when I1 and I0 of
the CC register are both set to 1 (level 3).
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ST7265x
MISCELLANEOUS REGISTERS (Cont’d)
MISCELLANEOUS REGISTER 2 (MISCR2)
In either case, the Watchdog will not reset the
MCU if a HALT instruction is executed while the
USB is in Suspend mode.
0: If the Watchdog is active, it will reset the MCU if
a HALT instruction is executed (unless the USB
is in Suspend mode)
1: When a HALT instruction is executed, the MCU
will enter Halt mode (without generating a reset)
even if the Watchdog is active.
Reset Value: 0000 0000 (00h)
7
0
0
0
0
P4
P3
P2
P1
P0
Bits 7:5 = Reserved.
Bits 4:0 = P[4:0] Power Management Bits
These bits are set and cleared by software. They
can be used to switch the on-chip peripherals of
the microcontroller ON or OFF. The registers are
not changed by switching the peripheral OFF and
then ON (contents are frozen while OFF).
0: Peripheral ON (running)
Bits 6:4 = Reserved, forced by hardware to 0.
Bits 3:2= IS3[1:0] ei2 Interrupt sensitivity
Interrupt sensitivity, defined using the IS3[1:0] bits,
is applied to the ei2 interrupts (Port C):
1: Peripheral OFF
IS31 IS30
External Interrupt Sensitivity
Falling edge & low level
Rising edge only
Bit
P0
P1
P2
P3
P4
Peripheral
PWM
Timer
I2C
0
0
1
1
0
1
0
1
Falling edge only
Rising and falling edge
USB
These 2 bits must be written only when I1 and I0 of
the CC register are both set to 1 (level 3).
DTC
Bit 1 = PWM1 PWM1 Output Control
0: PWM1 Output alternate function disabled (I/O
pin free for general purpose I/O).
MISCELLANEOUS REGISTER 3 (MISCR3)
Read/Write
Reset Value: 0000 0000 (00h)
1: PWM1 Output alternate function enabled
7
0
Bit 0 = PWM0 PWM0 Output Control
0: Output alternate function disabled (I/O pin free
for general purpose I/O).
WDG
HALT
0
0
0
IS31 IS30 PWM1 PWM0
1: PWM0 Output alternate function enabled
Bit 7 = WDGHALT Watchdog and HALT Mode
This bit is set and cleared by software. It deter-
mines if a RESET is generated when entering Halt
mode while the Watchdog is active (WDGA bit =1
in the WDGCR register).
Table 16. Miscellaneous Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
IS11
IS10
MCO
IS21
0
IS20
0
CP1
0
CP0
CPEN
MISCR1
Reset Value
49
4A
4C
0
0
0
0
0
0
0
0
0
0
0
0
P1
0
P0
0
P4
0
P3
0
P2
0
MISCR2
Reset Value
0
0
0
WDGHALT
0
0
IS31
0
IS30
0
PWM1
0
PWM0
0
MISCR3
Reset Value
0
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ST7265x
11 ON-CHIP PERIPHERALS
11.1 WATCHDOG TIMER (WDG)
11.1.1 Introduction
If the watchdog is activated (the WDGA bit is set)
and when the 7-bit timer (bits T[6:0]) rolls over
from 40h to 3Fh (T6 becomes cleared), it initiates
a reset cycle pulling low the reset pin for typically
500ns.
The Watchdog timer is used to detect the occur-
rence of a software fault, usually generated by ex-
ternal interference or by unforeseen logical condi-
tions, which causes the application program to
abandon its normal sequence. The Watchdog cir-
cuit generates an MCU reset on expiry of a pro-
grammed time period, unless the program refresh-
es the counter’s contents before the T6 bit be-
comes cleared.
The application program must write in the CR reg-
ister at regular intervals during normal operation to
prevent an MCU reset. This downcounter is free-
running: it counts down even if the watchdog is
disabled. The value to be stored in the CR register
must be between FFh and C0h (see Table 17):
11.1.2 Main Features
– The WDGA bit is set (watchdog enabled)
■ Programmable free-running downcounter (64
increments of 65536 CPU cycles)
– The T6 bit is set to prevent generating an imme-
diate reset
■ Programmable reset
– The T[5:0] bits contain the number of increments
which represents the time delay before the
watchdog produces a reset.
■ Reset (if watchdog activated) when the T6 bit
reaches zero
■ Hardware Watchdog selectable by option byte
Table 17.Watchdog Timing (f
= 8 MHz)
CPU
11.1.3 Functional Description
CR Register
initial value
WDG timeout period
(ms)
The counter value stored in the CR register (bits
T[6:0]), is decremented every 65,536 machine cy-
cles, and the length of the timeout period can be
programmed by the user in 64 increments.
Max
Min
FFh
C0h
524.288
8.192
Figure 37. Watchdog Block Diagram
RESET
WATCHDOG CONTROL REGISTER (CR)
T5 T0
WDGA T6
T1
T4
T2
T3
7-BIT DOWNCOUNTER
CLOCK DIVIDER
f
CPU
÷65536
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ST7265x
WATCHDOG TIMER (Cont’d)
11.1.4 Software Watchdog Option
11.1.5 Hardware Watchdog Option
If Software Watchdog is selected by option byte,
the watchdog is disabled following a reset. Once
activated it cannot be disabled, except by a reset.
If Hardware Watchdog is selected by option byte,
the watchdog is always active and the WDGA bit in
the CR is not used.
The T6 bit can be used to generate a software re-
set (the WDGA bit is set and the T6 bit is cleared).
11.1.6 Low Power Modes
Mode
Description
WAIT
No effect on Watchdog.
If the WDGHALT bit in the MISCR3 register is set, Halt mode can be used when the watchdog
is enabled. When the oscillator is stopped, the WDG stops counting and is no longer able to
generate a reset until the microcontroller receives an external interrupt or a reset.
HALT
If an external interrupt is received, the WDG restarts counting after 514 CPU clocks. In the case
of the Software Watchdog option, if a reset is generated, the WDG is disabled (reset state).
Note: In USB mode, and in Suspend mode, a reset is not generated by entering Halt mode
Recommendations
– The opcode for the HALT instruction is 0x8E. To
avoid an unexpected HALT instruction due to a
program counter failure, it is advised to clear all
occurrences of the data value 0x8E from memo-
ry. For example, avoid defining a constant in
ROM with the value 0x8E.
– Make sure that an external event is available to
wake up the microcontroller from Halt mode.
– Before executing the HALT instruction, refresh
the WDG counter, to avoid an unexpected WDG
reset immediately after waking up the microcon-
troller.
– As the HALT instruction clears the I bits in the
CC register to allow interrupts, the user may
choose to clear all pending interrupt bits before
executing the HALT instruction. This avoids en-
tering other peripheral interrupt routines after ex-
ecuting the external interrupt routine
– When using an external interrupt to wake up the
microcontroller, reinitialize the corresponding I/O
as Input before executing the HALT instruction.
The main reason for this is that the I/O may be
wrongly configured due to external interference
or by an unforeseen logical condition.
corresponding to the wake-up event (reset or ex-
ternal interrupt).
11.1.7 Interrupts
None.
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WATCHDOG TIMER (Cont’d)
11.1.8 Register Description
CONTROL REGISTER (CR)
Read/Write
hardware after a reset. When WDGA = 1, the
watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled
Reset Value: 0111 1111 (7Fh)
Note: This bit is not used if the hardware watch-
dog option is enabled by option byte.
7
0
WDGA T6
T5
T4
T3
T2
T1
T0
Bits 6:0 = T[6:0] 7-bit timer (MSB to LSB).
These bits contain the decremented value. A reset
is produced when it rolls over from 40h to 3Fh (T6
becomes cleared).
Bit 7 = WDGA Activation bit.
This bit is set by software and only cleared by
Table 18. Watchdog Timer Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
WDGCR
WDGA
0
T6
1
T5
1
T4
1
T3
1
T2
1
T1
1
T0
1
14
Reset Value
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11.2 DATA TRANSFER COPROCESSOR (DTC)
11.2.1 Introduction
started, the I/O ports mapped to the DTC assume
specific alternate functions.
The Data Transfer Coprocessor is a Universal Se-
rial/Parallel Communications Interface. By means
of software plug-ins provided by STMicroelectron-
ics, the user can configure the ST7 to handle a
wide range of protocols and physical interfaces
such as:
Main Features
■ Full-Speed data transfer from USB to I/O ports
without ST7 core intervention
■ Protocol-independency
■ Support for serial and parallel devices
■ Maskable Interrupts
– 8 or 16-bit IDE mode Compact Flash
– Multimedia Card (MMC protocol)
– SmartMediaCard
11.2.2 Functional Description
– Secure Digital Card
The block diagram is shown in Figure 38. The
main function of the DTC is to quickly transfer data
between :
Support for different devices or future protocol
standards does not require changing the micro-
controller hardware, but only installing a different
software plug-in.
■ USB and ST7 I/O ports
■ in between ST7 I/O ports
Once the plug-in (up to 256 bytes) stored in the
ROM or FLASH memory of the ST7 device is load-
ed in the DTC RAM, and that the DTC operation is
The protocol used to read or write from the I/O port
is defined by the S/W plug-in in the DTC RAM.
Figure 38. DTC Block Diagram
ST7 DATA/ADDRESS BUS
DTCPR
MSB
LSB
DATA
TRANSFER
COPROCESSOR
DATA
TO USB
TRANSFER
INTERFACE
I/O PORTS
BUFFER
DTC RAM
DTCCR
STOP
EN
ERR
EN
0
0
0
LOAD INIT RUN
DTCSR
0
0
0
0
0
0 ERRORSTOP
INTERRUPT REQUEST
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When the USB interface is used, data transfer is
typically controlled by a host computer.
4. Restore the write protection by clearing the
LOAD bit in the DTCCR register
The ST7 core can also read from and write to the
data buffer of the DTC. Typically, the ST7 controls
the application when the USB not used (autono-
mous mode). The buffer can potentially be ac-
cessed by any one of three requestors, the ST7,
the DTC and the USB. Mastership of the buffer is
not time limited. While a master is accessing the
buffer, other requests will not be acknowleged until
the buffer is freed by the master. If several re-
quests are pending, when the buffer is free it is
granted to the source with the highest priority in
the daisy-chain (fixed by hardware), first the ST7,
secondly the USB and finally the DTC.
The DTC is then ready for operation.
11.2.4 Executing the Protocol Functions
To execute any of the software plug-in functions
follow the procedure below:
1. Clear the RUN bit to stop the DTC
2. Select the function by writing its address in the
DTCPR register (refer to the separate docu-
ment for address information).
3. Set the INIT bit in the DTCCR register to copy
the DTCPR pointer to the DTC.
4. Clear the INIT bit to return to idle state.
5. Set the RUN bit to start the DTC.
Note: Any access by the ST7 to the buffer requires
more cycles than either a DTC or USB access. For
performance reasons, when the USB interface is
exchanging data with the DTC, ST7 accesses
should be avoided if possible.
11.2.5 Changing the DTCPR pointer on the fly
As shown in Figure 39, the pointer can be changed
by writing INIT=1 while the DTC is running
(RUN=1), however if the DTC is executing an in-
ternal interrupt routine, there will be a delay until
interrupt handling is completed.
11.2.3 Loading the Protocol Software
The DTC must first be initialized by loading the
protocol-specific software plug-in (provided by
STMicroelectronics) into the DTC RAM. To do this:
11.2.6 Low Power Modes
1. Stop the DTC by clearing the RUN bit in the
DTCCR register
Mode
WAIT
HALT
Description
2. Remove the write protection by setting the
LOAD bit in the DTCCR register
No effect on DTC
DTC halted.
3. Load the (null-terminated) software plug-in in
the DTC RAM.
Figure 39. State Diagram of DTC Operations
RUN=0
INIT=0
LOAD=1
RUN=1
INIT=0
LOAD=0
RUN=0
INIT=0
LOAD=0
DTC RAM
LOAD
LOAD=0
RUN=0
DTC
LOAD=1
INIT=1
RUNNING
DTC
IDLE
RUN=1
INIT=1
INIT=0
INIT=0
POINTER
CHANGE
ON-THE-FLY
POINTER
CHANGE
RUN=0
INIT=1
LOAD=0
RUN=1
INIT=1
LOAD=0
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11.2.7 Interrupts
Bit 0 = RUN START/STOP Control
This bit is set and cleared by software. It can only
be set while LOAD=0. It is also cleared by hard-
ware when STOP=1
0: Stop DTC
1: Start DTC
Enable
Control
Bit
Exit
from
Wait
Exit
from
Halt
Event
Flag
Interrupt Event
Error
Stop
ERROR ERREN
STOP STOPEN
Yes
Yes
No
No
DTC STATUS REGISTER (DTCSR)
Read/Write
Reset Value: 0000 0000 (00h)
Note: The DTC interrupt events are connected to
the same interrupt vector (see Interrupts chapter).
7
0
0
They generate an interrupt if the corresponding
Enable Control Bit is set and the I-bit in the CC
register is reset (RIM instruction).
0
0
0
0
0
ERROR STOP
Bit 7:2 = Reserved. Forced by hardware to 0.
11.2.8 Register Description
DTC CONTROL REGISTER (DTCCR)
Read/Write
Reset Value: 0000 0000 (00h)
Bit 1 = ERROR Error Flag
This bit is set by hardware and cleared by software
reading this register.
0: No Error event occurred
7
0
0
1: Error event occurred (DTC is running)
ERR STOP
EN EN
0
0
LOAD
INIT
RUN
Bit 0 = STOP Stop Flag
This bit is set by hardware and cleared by software
reading this register.
Bit 7:5 = Reserved. Must be left at reset value.
0: No Stop event occurred
1: Stop event occurred (DTC terminated execution
at the current intruction)
Bit 4 = ERREN Error Interrupt Enable
This bit is set and cleared by software.
0: Error interrupt disabled
1: Error interrupt enabled
DTC POINTER REGISTER (DTCPR)
Write Only
Reset Value: 0000 0000 (00h)
Bit 3 = STOPEN Stop Interrupt Enable
This bit is set and cleared by software.
0: Stop interrupt disabled
7
0
1: Stop interrupt enabled
MSB
LSB
Bit 2 = LOAD Load Enable
Bit 7:0 = PC[7:0] Pointer Register.
This bit is set and cleared by software. It can only
be set while RUN=0.
0: Write access to DTC RAM disabled
1: Write access DTC RAM enabled
This register is written by software. It gives the ad-
dress of an entry point in the protocol software that
has previously been loaded in the DTC RAM.
Note: To start executing the function, after writing
this address, set the INIT bit.
Bit 1 = INIT Initialization
This bit is set and cleared by software.
0: Do not copy DTCPR to DTC
1: Copy the DTCPR pointer to DTC
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11.2.8.1 Data Transfer Coprocessor (Cont’d)
Table 19. DTC Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
0
0
0
0
0
0
ERREN STOPEN
LOAD
0
INIT
0
RUN
0
1C
DTCCR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ERROR
0
STOP
0
1D
1F
DTCSR
DTCPR
MSB
0
LSB
0
0
0
0
0
0
0
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11.3 USB INTERFACE (USB)
11.3.1 Introduction
For general information on the USB, refer to the
“Universal Serial Bus Specifications” document
available at http//:www.usb.org.
The USB Interface implements a full-speed func-
tion interface between the USB and the ST7 mi-
crocontroller. It is a highly integrated circuit which
includes the transceiver, 3.3 voltage regulator, SIE
and USB Data Buffer interface. No external com-
ponents are needed apart from the external pull-
up on USBDP for full speed recognition by the
USB host.
Serial Interface Engine
The SIE (Serial Interface Engine) interfaces with
the USB, via the transceiver.
The SIE processes tokens, handles data transmis-
sion/reception, and handshaking as required by
the USB standard. It also performs frame format-
ting, including CRC generation and checking.
11.3.2 Main Features
■ USB Specification Version 2.0 Compliant
■ Supports Full-Speed USB Protocol
■ Five Endpoints (including default endpoint)
Endpoints
The Endpoint registers indicate if the microcontrol-
ler is ready to transmit/receive, and how many
bytes need to be transmitted.
■ CRC generation/checking, NRZI encoding/
decoding and bit-stuffing
Data Transfer to/from USB Data Buffer Memory
■ USB Suspend/Resume operations
When a token for a valid Endpoint is recognized by
the USB interface, the related data transfer takes
place to/from the USB data buffer. In normal con-
figuration (MOD[1:0] bits=00 in the CTLR register),
at the end of the transaction, an interrupt is gener-
ated.
■ Special Data transfer mode with USB Data
Buffer Memory (2 x 512 bytes for upload or
download) to DTC
■ On-Chip 3.3V Regulator
■ On-Chip USB Transceiver
11.3.3 Functional Description
Interrupts
By reading the Interrupt Status register, applica-
tion software can know which USB event has oc-
curred.
The block diagram in Figure 40, gives an overview
of the USB interface hardware.
Figure 40. USB Block Diagram
48 MHz
ENDPOINT
CPU
REGISTERS
USBDM
BUFFER
Address,
Transceiver
SIE
INTERFACE
USBDP
USBVCC
USBGND
data busses
and interrupts
3.3V
Voltage
Regulator
USB
USB
DATA
REGISTERS
BUFFER
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USB INTERFACE (Cont’d)
USB Endpoint RAM Buffers
the CTLR register (see Figure 41, Figure 42 and
Figure 43).
There are five bidirectional Endpoints including
one control Endpoint 0. Endpoint 1 and Endpoint 2
are counted as 4 bulk or interrupt Endpoints (two
IN and two OUT).
The USB Data Buffer operates as a double buffer;
while one 512-byte block is being read/written by
the DTC, the USB interface reads/writes the other
512-byte block.
Endpoint 0 and Endpoint 1 are both 2 x 16 bytes in
size. Endpoint 2 is 2 x 64 bytes in size and can be
configured to physically target different USB Data
Buffer areas depending on the MOD[1:0] bits in
The management of the data transfer is performed
in upload and download mode (2 x 512 byte buff-
ers for Endpoint 2) by the USB Data Buffer Manag-
er.
Figure 41. Endpoint 2 Normal Mode selected by (MOD[1:0] Bits = 00h)
1550h
Endpoint 0 Buffer OUT
Endpoint 0 Buffer IN
Endpoint 1 Buffer OUT
Endpoint 1 Buffer IN
16 Bytes
16 Bytes
16 Bytes
16 Bytes
155Fh
156Fh
157Fh
158Fh
15CFh
160Fh
64 Bytes
64 Bytes
Endpoint 2 Buffer OUT
Endpoint 2 Buffer IN
Figure 42. Endpoint 2 Download Mode selected by MOD[1:0] Bits = 10b
1590h
15CFh
1550h
USB DATA
64-byte buffer
Endpoint 0 Buffer OUT
Endpoint 0 Buffer IN
Endpoint 1 Buffer OUT
Endpoint 1 Buffer IN
Endpoint 2 Buffer IN
Endpoint 2 Buffer OUT
1650h
USB DATA
USB DATA
512-byte buffer
as 64-byte slices
158Fh
USB DATA
USB DATA
512-byte buffer
as 64-byte slices
1A4Fh
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USB INTERFACE (Cont’d)
Figure 43. Endpoint 2 Upload Mode selected by MOD[1:0] Bits = 01b
1590h
15CFh
1550h
USB DATA
64-byte buffer
512-byte buffer
Endpoint 0 Buffer OUT
Endpoint 0 Buffer IN
Endpoint 1 Buffer OUT
Endpoint 1 Buffer IN
Endpoint 2 Buffer OUT
Endpoint 2 Buffer IN
1650h
USB DATA
USB DATA
as 64-byte slices
158Fh
USB DATA
USB DATA
512-byte buffer
as 64-byte slices
1A4Fh
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USB INTERFACE (Cont’d)
11.3.4 USB Data Buffer Manager
ST7 software must then write the status bits to
VALID when it is ready to transmit or receive new
data.
The USB Data Buffer Manager performs the data
transfer between the USB interface and the two
512 Bytes RAM areas used for Endpoint 2 in both
Upload and Download modes. It also controls the
status of Endpoint 2, by setting the endpoint as
NAK when the current buffer is not yet available for
either transmission (Upload) or reception (Down-
load).
On the contrary, in Upload or Download mode, the
physical address of Endpoint 2 is automatically in-
cremented every 64 bytes until a 512-byte buffer is
full.
Toggling between the two buffers is automatically
managed as soon as 512 bytes have been trans-
mitted to USB (Upload mode) or received from
USB (Download), if the next buffer is available:
Otherwise, the endpoint is set to invalid until a
buffer has been released by the DTC.
It is based on a stand-alone hardware state-ma-
chine that runs in parallel to the ST7 processing
flow. However, at any time, the ST7 software can
initialize the USB Data Buffer Manager state-ma-
chine in order to synchronize operations by writing
a ‘1’ to the CLR bit in the BUFCSR register.
11.3.4.2 Switching back to Normal Mode
The USB interface is reset by hardware in Normal
mode on reception of a packet with a length below
the maximum packet size. In this case, the few
bytes are received into one of the two 512-byte
buffers and the ST7 must process by software the
data received. For this purpose, the information in-
dicating which 512-byte buffer was last addressed
is given to the ST7 by the USB Data Buffer Manag-
er (BUFNUM bit in the BUFCSR register), and the
number of received bytes is obtained by reading
the USB interface registers. With these two items
of information, the ST7 can determine what kind of
data has been received, and what action has to be
taken.
Dedicated buffer status flags are defined to syn-
chronize the USB Data Buffer Manager with the
Data Transfer Coprocessor (DTC). These flags
are used by the software plug-ins provided by
STMicroelectronics) running on the DTC.
11.3.4.1 Data Transfer Modes
In USB normal mode (MOD[1:0]=00b), the maxi-
mum memory size of Endpoint 2 is 64 bytes, and
therefore reception of 512 bytes packets requires
ST7 software intervention every 64 bytes. This
means that after a CTR interrupt the hardware
puts the Endpoint 2 status bits for the current di-
rection (transmit or receive) in NAK status. The
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USB INTERFACE (Cont’d)
Figure 44. Overview of USB, DTC and ST7 Interconnections
USB
BUFCSR Register (19h)
SIE
STAT STAT
BUF
NUM
DATA TRANSFER
BUFFER (1280 bytes)
0
0
0
0
CLR
B1
B0
1550h
USB EP0
USB EP1
USB EP2
USB DATA
BUFFER
MANAGER
Parameters
1650h
1850h
512-byte RAM
Buffer
BUFFER ACCESS
ARBITRATION
512-byte RAM
Buffer
1A4Fh
DATA
TRANSFER
COPROCESSOR
(DTC)
DTC I/Os
(EXTERNAL
DEVICES)
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11.3.5 Low Power modes
Mode
Description
No effect on USB.
WAIT
USB interrupt events cause the device to exit from WAIT mode.
USB registers are frozen.
In halt mode, the USB is inactive. USB operations resume when the MCU is woken up by an interrupt with
“exit from halt capability” or by an event on the USB line in case of suspend. This event will generate an
ESUSP interrupt which will wake-up from halt mode.
HALT
11.3.6 Interrupts
Exit
From
Halt
Enable Con- ExitFrom
Interrupt Event
Event Flag
trol Bit
Wait
Correct TRansfer
Setup OVeRrun
ERROR
CTR
SOVR
ERR
CTRM
SOVRM
ERRM
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
Yes
No
No
Suspend Mode Request
End of SUSPend mode.
USB RESET
SUSP
ESUSP
RESET
SOF
SUSPM
ESUSPM
RESETM
SOFM
Start Of Frame
Note: The USB end of suspend interrupt event is connected to a single interrupt vector (USB ESUSP) with
the exit from halt capability (wake-up). All the other interrupt events are connected to another interrupt
vector: USB interrupt (USB). They generate an interrupt if the corresponding enable control bit is set and
the interrupt mask bits (I0, I1) in CC register are reset (RIM instruction).
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USB INTERFACE (Cont’d)
11.3.7 Register Description
INTERRUPT STATUS REGISTER (ISTR)
BUFFER
CONTROL/STATUS
REGISTER
Read/Write
(BUFCSR)
Reset Value: 0000 0000 (00h)
Read Only (except bit 0, read/write)
Reset Value: 0000 0000 (00h)
7
0
CTR
0
SOVR ERROR SUSP ESUSP RESET SOF
7
0
These bits cannot be set by software. When an in-
terrupt occurs these bits are set by hardware. Soft-
ware must read them to determine the interrupt
type and clear them after servicing.
BUF- STAT STAT
NUM B1 B0
0
0
0
0
CLR
Bits 7:4 = Reserved, forced by hardware to 0.
Note: The CTR bit (which is an OR of all the end-
point CTR flags) cannot be cleared directly, only
by clearing the CTR flags in the Endpoint regis-
ters.
Bit 3 = BUFNUM Current USB Buffer Number
This bit is set and cleared by hardware. When data
are received by Endpoint 2 in normal mode (refer
to the description of the MOD[1:0] bits in the
EP2RXR register) it indicates which buffer con-
tains the data.
Bit 7 = CTR Correct Transfer.
This bit is set by hardware when a correct transfer
operation is performed. This bit is an OR of all
CTR flags (CTR0 in the EP0R register and
CTR_RX and CTR_TX in the EPnR registers). By
looking in the USBSR register, the type of transfer
can be determined from the PID[1:0] bits for End-
point 0. For the other Endpoints, the Endpoint
number on which the transfer was made is identi-
fied by the EP[1:0] bits and the type of transfer by
the IN/OUT bit.
0: Current buffer is Buffer 0
1: Current buffer is Buffer 1
Bits 2:1 = STATB[1:0] Buffer Status Bits
These bits are set and cleared by hardware. When
data are transmitted or received by Endpoint 2 in
upload or download mode (refer to the description
of the MOD[1:0] bits in the EP2RXR register) the
STATB[1:0] bits indicate the status as follows:
0: No Correct Transfer detected
1: Correct Transfer detected
STATBn
Meaning
Value
Note: A transfer where the device sent a NAK or
STALL handshake is considered not correct (the
host only sends ACK handshakes). A transfer is
considered correct if there are no errors in the PID
and CRC fields, if the DATA0/DATA1 PID is sent
as expected, if there were no data overruns, bit
stuffing or framing errors.
Buffer n not full (USB waiting to
0
read Buffer n)
Upload
Mode
Buffer n full (USB can upload this
buffer)
1
0
1
Buffer n empty (Can be written to
by USB)
Download
Mode
Buffer n not empty (USB waiting
to write to this buffer)
Bit 6 = Reserved, forced by hardware to 0.
Bit 5 = SOVR Setup Overrun.
Bit 0 = CLR Clear Buffer Status
This bit is set by hardware when a correct Setup
transfer operation is performed while the software
is servicing an interrupt which occurred on the
same Endpoint (CTR0 bit in the EP0R register is
still set when SETUP correct transfer occurs).
0: No SETUP overrun detected
This bit is written by software to clear the BUF-
NUM and STATB[1:0] bits (it also resets the pack-
et counter of the Buffer Manager state machine). It
can be used to re-initialize the upload/download
flow (refer to the description of the MOD[1:0] bits in
the EP2RXR register).
1: SETUP overrun detected
0: No effect
1: Clear BUFNUM and STATB[1:0] bits
When this event occurs, the USBSR register is not
updated because the only source of the SOVR
event is the SETUP token reception on the Control
Endpoint (EP0).
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USB INTERFACE (Cont’d)
Bit 4 = ERR Error.
INTERRUPT MASK REGISTER (IMR)
Read/Write
This bit is set by hardware whenever one of the er-
rors listed below has occurred:
0: No error detected
Reset Value: 0000 0000 (00h)
1: Timeout, CRC, bit stuffing, nonstandard
framing or buffer overrun error detected
7
0
Note: Refer to the ERR[2:0] bits in the USBSR
register to determine the error type.
SOVR
M
SUSP ESUSP RESET
CTRM
0
ERRM
SOFM
M
M
M
These bits are mask bits for all the interrupt condi-
tion bits included in the ISTR register. Whenever
one of the IMR bits is set, if the corresponding
ISTR bit is set, and the I- bit in the CC register is
cleared, an interrupt request is generated. For an
explanation of each bit, please refer to the descrip-
tion of the ISTR register.
Bit 3 = SUSP Suspend mode request.
This bit is set by hardware when a constant idle
state is present on the bus line for more than 3 ms,
indicating a suspend mode request from the USB.
The suspend request check is active immediately
after each USB reset event and is disabled by
hardware when suspend mode is forced (FSUSP
bit in the CTLR register) until the end of resume
sequence.
CONTROL REGISTER (CTLR)
Read/Write
Bit 2 = ESUSP End Suspend mode.
Reset value: 0000 0110 (06h)
This bit is set by hardware when, during suspend
mode, activity is detected that wakes the USB in-
terface up from suspend mode.
7
0
USB_
RST
This interrupt is serviced by a specific vector, in or-
der to wake up the ST7 from HALT mode.
0: No End Suspend detected
RESU
ME
RSM
0
0
PDWN FSUSP FRES
1: End Suspend detected
Bit 7 = RSM Resume Detected
This bit shows when a resume sequence has start-
ed on the USB port, requesting the USB interface
to wake-up from suspend state. It can be used to
determine the cause of an ESUSP event.
0: No resume sequence detected on USB
1: Resume sequence detected on USB
Bit 1 = RESET USB reset.
This bit is set by hardware when the USB reset se-
quence is detected on the bus.
0: No USB reset signal detected
1: USB reset signal detected
Note: The DADDR, EP0R, EP1RXR, EP1TXR
and EP2RXR, EP2TXR registers are reset by a
USB reset.
Bit 6 = USB_RST USB Reset detected.
This bit shows that a reset sequence has started
on the USB. It can be used to determine the cause
of an ESUSP event (Reset sequence).
0: No reset sequence detected on USB
1: Reset sequence detected on USB
Bit 0 = SOF Start of frame.
This bit is set by hardware when a SOF token is re-
ceived on the USB.
0: No SOF received
1: SOF received
Bits 5:4 Reserved, forced by hardware to 0.
Note: To avoid spurious clearing of some bits, it is
recommended to clear them using a load instruc-
tion where all bits which must not be altered are
set, and all bits to be cleared are reset. Avoid read-
modify-write instructions like AND, XOR..
Bit 3 = RESUME Resume.
This bit is set by software to wake-up the Host
when the ST7 is in suspend mode.
0: Resume signal not forced
1: Resume signal forced on the USB bus.
Software should clear this bit after the appropriate
delay.
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USB INTERFACE (Cont’d)
Bit 2 = PDWN Power down.
Note: This register is also reset when a USB reset
is received or forced through bit FRES in the CTLR
register.
This bit is set by software to turn off the 3.3V on-
chip voltage regulator that supplies the external
pull-up resistor and the transceiver.
0: Voltage regulator on
USB STATUS REGISTER (USBSR)
Read only
1: Voltage regulator off
Note: After turning on the voltage regulator, soft-
ware should allow at least 3 µs for stabilisation of
the power supply before using the USB interface.
Reset Value: 0000 0000 (00h)
7
0
Bit 1 = FSUSP Force suspend mode.
This bit is set by software to enter Suspend mode.
The ST7 should also be put in Halt mode to reduce
power consumption.
0: Suspend mode inactive
1: Suspend mode active
IN/
OUT
PID1 PID0
EP1
EP0 ERR2 ERR1 ERR0
Bits 7:6 = PID[1:0] Token PID bits 1 & 0 for End-
point 0 Control.
USB token PIDs are encoded in four bits. PID[1:0]
correspond to the most significant bits of the PID
field of the last token PID received by Endpoint 0.
Note: The least significant PID bits have a fixed
value of 01.
When a CTR interrupt occurs on Endpoint 0 (see
register ISTR) the software should read the
PID[1:0] bits to retrieve the PID name of the token
received.
When the hardware detects USB activity, it resets
this bit (it can also be reset by software).
Bit 0 = FRES Force reset.
This bit is set by software to force a reset of the
USB interface, just as if a RESET sequence came
from the USB.
0: Reset not forced
1: USB interface reset forced.
The USB specification defines PID bits as:
PID1
PID0
PID Name
OUT
The USB interface is held in RESET state until
software clears this bit, at which point a “USB-RE-
SET” interrupt will be generated if enabled.
0
1
1
0
0
1
IN
SETUP
DEVICE ADDRESS REGISTER (DADDR)
Read/Write
Bit 5 = IN/OUT Last transaction direction for End-
point 1 or 2.
Reset Value: 0000 0000 (00h)
This bit is set by hardware when a CTR interrupt
occurs on Endpoint 1 or Endpoint 2.
0: OUT transaction
7
0
0
ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0
1: IN transaction
Bit 7 Reserved, forced by hardware to 0.
Bits 4:3 = EP[1:0] Endpoint number.
These bits identify the endpoint which required at-
tention.
Bits 6:0 = ADD[6:0] Device address, 7 bits.
00 = Endpoint 0
01 = Endpoint 1
10 = Endpoint 2
Software must write into this register the address
sent by the host during enumeration.
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USB INTERFACE (Cont’d)
Bits 2:0 = ERR[2:0] Error type.
data packet. This bit is set by hardware on recep-
tion of a SETUP PID. DTOG_TX toggles only
when the transmitter has received the ACK signal
from the USB host. DTOG_TX and also
DTOG_RX are normally updated by hardware, on
receipt of a relevant PID. They can be also written
by the user, both for testing purposes and to force
a specific (DATA0 or DATA1) token.
These bits identify the type of error which oc-
curred:
ERR2 ERR1 ERR0
Meaning
0
0
0
0
0
1
0
1
0
No error
Bitstuffing error
CRC error
EOP error (unexpected end of
packet or SE0 not followed by
J-state)
0
1
1
0
1
0
Bits 5:4 = STAT_TX [1:0] Status bits, for transmis-
sion transfers.
These bits contain the information about the end-
PID error (PID encoding error,
unexpected or unknown PID)
point status, as listed below:
Memory over / underrun (mem-
ory controller has not an-
swered in time to a memory
data request)
Table 20. Transmission Status Encoding
1
1
0
1
1
1
STAT_TX1 STAT_TX0
Meaning
DISABLED: no function can be
executed on this endpoint and
messages related to this end-
point are ignored.
Other error (wrong packet,
timeout error)
0
0
Note: These bits are set by hardware when an er-
ror interrupt occurs and are reset automatically
when the error bit (ISTR bit 4) is cleared by soft-
ware.
STALL: the endpoint is stalled
and all transmission requests
result in a STALL handshake.
0
1
1
0
NAK: the endpoint is NAKed
and all transmission requests
result in a NAK handshake.
ENDPOINT 0 REGISTER (EP0R)
Read/Write
VALID: this endpoint is enabled
(if an address match occurs, the
USB interface handles the
transaction).
1
1
Reset value: 0000 0000 (00h)
7
0
These bits are written by software. Hardware sets
the STAT_TX and STAT_RX bits to NAK when a
correct transfer has occurred (CTR=1) addressed
to this endpoint; this allows software to prepare the
next set of data to be transmitted.
STAT_ STAT_
STAT_ STAT_
DTOG
_TX
DTOG
_RX
CTR0
0
TX1
TX0
RX1
RX0
This register is used for controlling Endpoint 0. Bits
6:4 and bits 2:0 are also reset by a USB reset, ei-
ther received from the USB or forced through the
FRES bit in CTLR.
Bit 3 = Reserved, forced by hardware to 0.
Bit 7 = CTR0 Correct Transfer.
This bit is set by hardware when a correct transfer
operation is performed on Endpoint 0. This bit
must be cleared after the corresponding interrupt
has been serviced.
0: No CTR on Endpoint 0
1: Correct transfer on Endpoint 0
Bit 2 = DTOG_RX Data Toggle, for reception
transfers.
It contains the expected value of the toggle bit
(0=DATA0, 1=DATA1) for the next data packet.
This bit is cleared by hardware in the first stage
(Setup Stage) of a control transfer (SETUP trans-
actions start always with DATA0 PID). The receiv-
er toggles DTOG_RX only if it receives a correct
data packet and the packet’s data PID matches
the receiver sequence bit.
Bit 6 = DTOG_TX Data Toggle, for transmission
transfers.
It contains the required value of the toggle bit
(0=DATA0, 1=DATA1) for the next transmitted
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USB INTERFACE (Cont’d)
Bits 1:0 = STAT_RX [1:0] Status bits, for reception
transfers.
These bits contain the information about the end-
point status, as listed below:
This register is used for controlling Endpoint 1 re-
ception. Bits 2:0 are also reset by a USB reset, ei-
ther received from the USB or forced through the
FRES bit in the CTLR register.
Table 21. Reception Status Encoding
Bits 7:4 Reserved, forced by hardware to 0.
STAT_RX1 STAT_RX0
Meaning
DISABLED: no function can be
executed on this endpoint and
messages related to this end-
point are ignored.
Bit 3 = CTR_RX Correct Reception Transfer.
This bit is set by hardware when a correct transfer
operation is performed in reception. This bit must
be cleared after the corresponding interrupt has
been serviced.
0
0
STALL: the endpoint is stalled
and all reception requests re-
sult in a STALL handshake.
0
1
1
0
NAK: the endpoint is NAKed
and all reception requests re-
sult in a NAK handshake.
Bit 2 = DTOG_RX Data Toggle, for reception
transfers.
It contains the expected value of the toggle bit
(0=DATA0, 1=DATA1) for the next data packet.
The receiver toggles DTOG_RX only if it receives
a correct data packet and the packet’s data PID
matches the receiver sequence bit.
VALID: this endpoint is ena-
bled (if an address match oc-
curs, the USB interface
1
1
handles the transaction).
These bits are written by software. Hardware sets
the STAT_RX and STAT_TX bits to NAK when a
correct transfer has occurred (CTR=1) addressed
to this endpoint, so the software has the time to ex-
amine the received data before acknowledging a
new transaction.
Bits 1:0 = STAT_RX [1:0] Status bits, for reception
transfers.
These bits contain the information about the end-
point status, as listed below:
Table 22. Reception Status Encoding:
Notes:
STAT_RX1 STAT_RX0
Meaning
If a SETUP is received while the status is other
than DISABLED, it is acknowledged and the two
directional status bits are set to NAK by hardware.
DISABLED: reception trans-
fers cannot be executed.
0
0
STALL: the endpoint is stalled
and all reception requests re-
sult in a STALL handshake.
When a STALL is answered by the USB device,
the two directional status bits are set to STALL by
hardware.
0
1
NAK: the endpoint is naked
and all reception requests re-
sult in a NAK handshake.
1
1
0
1
ENDPOINT
(EP1RXR)
1
RECEPTION
REGISTER
VALID: this endpoint is ena-
bled for reception.
Read/Write
Reset value: 0000 0000 (00h)
These bits are written by software, but hardware
sets the STAT_RX bits to NAK when a correct
transfer has occurred (CTR=1) addressed to this
endpoint, so the software has the time to examine
the received data before acknowledging a new
transaction.
7
0
STAT_ STAT_
CTR_R DTOG
_RX
0
0
0
0
X
RX1
RX0
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USB INTERFACE (Cont’d)
ENDPOINT
(EP1TXR)
1
TRANSMISSION REGISTER
These bits are written by software, but hardware
sets the STAT_TX bits to NAK when a correct
transfer has occurred (CTR=1) addressed to this
endpoint. This allows software to prepare the next
set of data to be transmitted.
Read/Write
Reset value: 0000 0000 (00h)
7
0
STAT_ STAT_
CTR_T DTOG
_TX
0
0
0
0
X
TX1
TX0
ENDPOINT
(EP2RXR)
Read/Write
2
RECEPTION
REGISTER
This register is used for controlling Endpoint 1
transmission. Bits 2:0 are also reset by a USB re-
set, either received from the USB or forced
through the FRES bit in the CTLR register.
Reset value: 0000 0000 (00h)
7
0
Bit 3 = CTR_TX Correct Transmission Transfer.
This bit is set by hardware when a correct transfer
operation is performed in transmission. This bit
must be cleared after the corresponding interrupt
has been serviced.
0: No CTR in transmission on Endpoint 1
1: Correct transfer in transmission on Endpoint 1
STAT_ STAT_
CTR_R DTOG
_RX
MOD1 MOD0
0
0
X
RX1
RX0
This register is used for controlling endpoint 2 re-
ception. Bits 2:0 are also reset by a USB reset, ei-
ther received from the USB or forced through the
FRES bit in the CTLR register.
Bit 2 = DTOG_TX Data Toggle, for transmission
transfers.
Bits 7:6 = MOD[1:0] Endpoint 2 mode.
These bits are set and cleared by software. They
select the Endpoint 2 mode (See Figure 42 and
Figure 43).
This bit contains the required value of the toggle
bit (0=DATA0, 1=DATA1) for the next data packet.
DTOG_TX toggles only when the transmitter has
received the ACK signal from the USB host.
DTOG_TX and DTOG_RX are normally updated
by hardware, at the receipt of a relevant PID. They
can be also written by the user, both for testing
purposes and to force a specific (DATA0 or
DATA1) token.
MOD1 MOD0
Mode
Normal mode: Endpoint 2 is managed by
user software
0
0
Upload mode to USB data buffer: Bulk
mode IN under hardware control from
DTC
0
1
1
Bits 1:0 = STAT_TX [1:0] Status bits, for transmis-
sion transfers.
These bits contain the information about the end-
point status, which is listed below
Download mode from USB data buffer:
Bulk mode OUT under hardware control
to DTC .
1
0
2
Notes:
Table 23. Transmission Status Encoding
1. Before selecting Download mode, software
must write the maximum packet size value (for in-
stance 64) in the CNT2RXR register and write the
STAT_RX bits in the EP2RXR register to VALID.
STAT_TX1 STAT_TX0
Meaning
DISABLED: transmission
transfers cannot be executed.
0
0
STALL: the endpoint is stalled
and all transmission requests
result in a STALL handshake.
2. Before selecting Upload mode, software must
write the maximum packet size value (for instance
64) in the CNT2TXR register and write the
STAT_TX bits in the EP2TXR register to NAK.
0
1
NAK: the endpoint is naked
and all transmission requests
result in a NAK handshake.
1
1
0
1
VALID: this endpoint is ena-
bled for transmission.
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USB INTERFACE (Cont’d)
Download Mode
Table 24. Reception Status Encoding
IN transactions are managed the same way as in
normal mode (by software with the help of CTR in-
terrupt) but OUT transactions are managed by
hardware. This means that no CTR interrupt is
generated at the end of an OUT transaction and
the STAT_RX bits are set to valid by hardware
when the buffer is ready to receive new data. This
allows the 512-byte buffer to be written without
software intervention.
STAT_RX1 STAT_RX0
Meaning
DISABLED: reception trans-
fers cannot be executed.
0
0
STALL: the endpoint is stalled
and all reception requests re-
sult in a STALL handshake.
0
1
NAK: the endpoint is naked
and all reception requests re-
sult in a NAK handshake.
1
1
0
1
If the USB interface receives a packet which has a
length lower than the maximum packet size (writ-
ten in the CNT2RXR register, see Note below), the
USB interface switches back to normal mode and
generates a CTR interrupt and the STAT_RX bits
of the EP2R register are set to NAK by hardware
as in normal mode.
VALID: this endpoint is ena-
bled for reception.
These bits are written by software, but hardware
sets the STAT_RX bits to NAK when a correct
transfer has occurred (CTR=1) addressed to this
endpoint, so the software has the time to examine
the received data before acknowledging a new
transaction.
Upload Mode
OUT transactions are managed in the same way
as normal mode and IN transactions are managed
by hardware in the same way as OUT transactions
in download mode.
Note: These bits are write protected in download
mode (if MOD[1:0] =10b in the EP2RXR register)
ENDPOINT
(EP2TXR)
2
TRANSMISSION REGISTER
Bits 5:4 Reserved, forced by hardware to 0.
Read/Write
Reset value: 0000 0000 (00h)
Bit 3 = CTR_RX Reception Correct Transfer.
This bit is set by hardware when a correct transfer
operation is performed in reception. This bit must
be cleared after that the corresponding interrupt
has been serviced.
7
0
STAT_ STAT_
CTR_T DTOG
_TX
0
0
0
0
X
TX1
TX0
Bit 2 = DTOG_RX Data Toggle, for reception
transfers.
It contains the expected value of the toggle bit
(0=DATA0, 1=DATA1) for the next data packet.
USB INTERFACE (Cont’d)
This register is used for controlling Endpoint 2
transmission. Bits 2:0 are also reset by a USB re-
set, either received from the USB or forced
through the FRES bit in the CTLR register.
The receiver toggles DTOG_RX only if it receives
a correct data packet and the packet’s data PID
matches the receiver sequence bit.
Bit 3 = CTR_TX Transmission Transfer Correct.
This bit is set by hardware when a correct transfer
operation is performed in transmission. This bit
must be cleared after the corresponding interrupt
has been serviced.
0: No CTR in transmission on Endpoint 2
1: Correct transfer in transmission on Endpoint 2
Bits 1:0 = STAT_RX [1:0] Status bits, for reception
transfers.
These bits contain the information about the end-
point status, which is listed below:
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USB INTERFACE (Cont’d)
Bit 2= DTOG_TX Data Toggle, for transmission
transfers.
number of bytes received, the software must sub-
tract the content of this register from the allocated
buffer size).
This bit contains the required value of the toggle
bit (0=DATA0, 1=DATA1) for the next data packet.
DTOG_TX and DTOG_RX are normally updated
by hardware, on receipt of a relevant PID. They
can be also written by the user, both for testing
purposes and to force a specific (DATA0 or
DATA1) token.
RECEPTION COUNTER REGISTER (CNT2RXR)
Read/Write
Reset Value: 0000 0000 (00h)
7
0
Bits 1:0 = STAT_TX [1:0] Status bits, for transmis-
sion transfers.
0
CNT6 CNT5 CNT4 CNT3 CNT2 CNT CNT0
These bits contain the information about the end-
point status, which is listed below
This register contains the allocated buffer size for
endpoint 2 reception, setting the maximum
number of bytes the related endpoint can receive
with the next OUT transaction. At the end of a re-
ception, the value of this register is the maximum
size decremented by the number of bytes received
(to determine the number of bytes received, the
software must subtract the content of this register
from the allocated buffer size).
Table 25. Transmission Status Encoding
STAT_TX1 STAT_TX0
Meaning
DISABLED: transmission
transfers cannot be executed.
0
0
STALL: the endpoint is stalled
and all transmission requests
result in a STALL handshake.
0
1
TRANSMISSION COUNTER REGISTER
(CNT0TXR, CNT1TXR)
NAK: the endpoint is naked
and all transmission requests
result in a NAK handshake.
1
1
0
1
Read/Write
VALID: this endpoint is ena-
bled for transmission.
Reset Value 0000 0000 (00h)
7
0
These bits are written by software, but hardware
sets the STAT_TX bits to NAK when a correct
transfer (CTR=1) addressed to this endpoint has
occurred. This allows software to prepare the next
set of data to be transmitted.
0
0
0
CNT4 CNT3 CNT2 CNT1 CNT0
This register contains the number of bytes to be
transmitted by Endpoint 0 or 1 at the next IN token
addressed to it.
Note: These bits are write protected in upload
mode (MOD[1:0] =01b in the EP2RXR register)
TRANSMISSION COUNTER REGISTER
(CNT2TXR)
RECEPTION COUNTER REGISTER (CNT0RXR,
CNT1RXR)
Read/Write
Read/Write
Reset Value 0000 0000 (00h)
Reset Value: 0000 0000 (00h)
7
0
7
0
0
CNT6 CNT5 CNT4 CNT3 CNT2 CNT1 CNT0
0
0
0
CNT4 CNT3 CNT2 CNT1 CNT0
This register contains the number of bytes to be
transmitted by Endpoint 2 at the next IN token ad-
dressed to it.
This register contains the allocated buffer size for
endpoint 0 or 1 reception, setting the maximum
number of bytes the related endpoint can receive
with the next OUT (or SETUP for Endpoint 0)
transaction. At the end of a reception, the value of
this register is the max size decremented by the
number of bytes received (to determine the
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Table 26. USB Register Map and Reset values
Address
(Hex.)
Register
Name
7
6
5
4
3
2
1
0
BUFCSR
Reset Value
0
0
0
0
0
0
0
0
BUFNUM
0
BUF1ST
0
BUF0ST
0
RESETST
0
47
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
USBISTR
Reset Value
CTR
0
0
0
SOVR
0
ERR
0
SUSP
0
ESUSP
0
RESET
0
SOF
0
USBIMR
Reset Value
CTRM
0
0
0
SOVRM
0
ERRM
0
SUSPM
0
ESUSPM
0
RESETM
0
SOFM
0
USBCTLR
Reset Value
RSM
0
USB_RST
0
RESUME
0
PDWN
1
FSUSP
1
FRES
0
0
0
DADDR
Reset Value
ADD6
0
ADD5
0
ADD4
0
ADD3
0
ADD2
0
ADD1
0
ADD0
0
0
USBSR
Reset Value
PID1
0
PID0
0
IN /OUT
0
EP1
0
EP0
0
ERR2
0
ERR1
0
ERR0
0
EP0R
Reset Value
CTR0
0
DTOG_TX STAT_TX1
STAT_TX0
0
0
0
DTOG_RX STAT_RX1 STAT_RX0
0
0
0
0
0
CNT0RXR
Reset Value
0
0
0
0
0
0
CNT4
0
CNT3
0
CNT2
0
CNT1
0
CNT0
0
CNT0TXR
Reset Value
0
0
0
0
0
0
CNT4
0
CNT3
0
CNT2
0
CNT1
0
CNT0
0
EP1RXR
Reset Value
CTR_RX
0
DTOG_RX STAT_RX1 STAT_RX0
0
0
0
0
0
0
0
CNT1RXR
Reset Value
0
0
0
0
0
0
CNT4
0
CNT3
0
CNT2
0
CNT1
0
CNT0
0
EP1TXR
Reset Value
CTR_TX
0
DTOG_TX STAT_TX1
STAT_TX0
0
0
0
0
0
0
0
CNT1TXR
Reset Value
0
0
0
0
0
0
CNT4
0
CNT3
0
CNT2
0
CNT1
0
CNT0
0
EP2RXR
Reset Value
MOD1
0
MOD0
0
CTR_RX
0
DTOG_RX STAT_RX1 STAT_RX0
0
0
0
0
0
CNT2RXR
Reset Value
0
0
CNT6
0
CNT5
0
CNT4
0
CNT3
0
CNT2
0
CNT1
0
CNT0
0
EP2TXR
Reset Value
CTR_TX
0
DTOG_TX STAT_TX1
STAT_TX0
0
0
0
0
0
0
0
CNT2TXR
Reset Value
0
0
CNT6
0
CNT5
0
CNT4
0
CNT3
0
CNT2
0
CNT1
0
CNT0
0
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11.4 16-BIT TIMER
11.4.1 Introduction
11.4.3 Functional Description
11.4.3.1 Counter
The timer consists of a 16-bit free-running counter
driven by a programmable prescaler.
The main block of the Programmable Timer is a
16-bit free running upcounter and its associated
16-bit registers. The 16-bit registers are made up
of two 8-bit registers called high & low.
11.4.2 Main Features
■ Programmableprescaler:fCPU dividedby2, 4or8.
■ Overflow status flag and maskable interrupt
■ Output compare functions with
– 2 dedicated 16-bit registers
Counter Register (CR):
– Counter High Register (CHR) is the most sig-
nificant byte (MS Byte).
– 2 dedicated programmable signals
– 2 dedicated status flags
– Counter Low Register (CLR) is the least sig-
nificant byte (LS Byte).
– 1 dedicated maskable interrupt
Alternate Counter Register (ACR)
■ 2 alternate functions on I/O ports (OCMP1,
– Alternate Counter High Register (ACHR) is the
most significant byte (MS Byte).
OCMP2)
– Alternate Counter Low Register (ACLR) is the
least significant byte (LS Byte).
The Block Diagram is shown in Figure 45.
These two read-only 16-bit registers contain the
same value but with the difference that reading the
ACLR register does not clear the TOF bit (Timer
overflow flag), located in the Status register, (SR),
(see note at the end of paragraph titled 16-bit read
sequence).
Writing in the CLR register or ACLR register resets
the free running counter to the FFFCh value.
Both counters have a reset value of FFFCh (this is
the only value which is reloaded in the 16-bit tim-
er).
The timer clock depends on the clock control bits
of the CR2 register, as illustrated in Table 27 Clock
Control Bits. The value in the counter register re-
peats every 131.072, 262.144 or 524.288 CPU
clock cycles depending on the CC[1:0] bits.
The timer frequency can be f
or an external frequency.
/2, f
/4, f
/8
CPU
CPU
CPU
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ST7265x
16-BIT TIMER (Cont’d)
Figure 45. Timer Block Diagram
ST7 INTERNAL BUS
f
CPU
MCU-PERIPHERAL INTERFACE
8 low
8-bit
8 high
8
8
8
8
buffer
w
w
EXEDG
h
o
h
lo
16
OUTPUT
COMPARE
REGISTER
OUTPUT
COMPARE
REGISTER
1/2
1/4
1/8
COUNTER
REGISTER
1
2
ALTERNATE
COUNTER
REGISTER
16
CC[1:0]
TIMER INTERNAL BUS
16 16
OVERFLOW
DETECT
OUTPUT COMPARE
CIRCUIT
CIRCUIT
6
OCMP1
pin
LATCH1
LATCH2
0
OCF1 TOF
0
OCF2
0
0
0
OCMP2
pin
(Status Register) SR
0
0
OCIE TOIE FOLV2 FOLV1OLVL2
0
OLVL1
OC1E
0
0
CC1 CC0
0
OC2E
(Control Register 1) CR1
(Control Register 2) CR2
TIMER INTERRUPT
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16-BIT TIMER (Cont’d)
16-bit read sequence: (from either the Counter
Register or the Alternate Counter Register).
– A timer interrupt is generated if:
– TOIE bit of the CR1 register is set and
– I bits of the CC register is cleared.
Beginning of the sequence
If one of these conditions is false, the interrupt re-
mains pending to be issued as soon as they are
both true.
Read
MS Byte
LS Byte
is buffered
At t0
Clearing the overflow interrupt request is done in
two steps:
Other
instructions
1. Reading the SR register while the TOF bit is set.
2. An access (read or write) to the CLR register.
Returns the buffered
LS Byte value at t0
Read
LS Byte
At t0 +∆t
Notes: The TOF bit is not cleared by accesses to
ACLR register. The advantage of accessing the
ACLR register rather than the CLR register is that
it allows simultaneous use of the overflow function
and reading the free running counter at random
times (for example, to measure elapsed time) with-
out the risk of clearing the TOF bit erroneously.
Sequence completed
The user must read the MS Byte first, then the LS
Byte value is buffered automatically.
This buffered value remains unchanged until the
16-bit read sequence is completed, even if the
user reads the MS Byte several times.
The timer is not affected by WAIT mode.
In HALT mode, the counter stops counting until the
mode is exited. Counting then resumes from the
previous count (MCU awakened by an interrupt) or
from the reset count (MCU awakened by a Reset).
After a complete reading sequence, if only the
CLR register or ACLR register are read, they re-
turn the LS Byte of the count value at the time of
the read.
Whatever the timer mode used an overflow occurs
when the counter rolls over from FFFFh to 0000h
then:
– The TOF bit of the SR register is set.
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16-BIT TIMER (Cont’d)
Figure 46. Counter Timing Diagram, internal clock divided by 2
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
FFFD FFFE FFFF 0000 0001 0002 0003
COUNTER REGISTER
TIMER OVERFLOW FLAG (TOF)
Figure 47. Counter Timing Diagram, internal clock divided by 4
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
FFFC
FFFD
0000
0001
COUNTER REGISTER
TIMER OVERFLOW FLAG (TOF)
Figure 48. Counter Timing Diagram, internal clock divided by 8
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
0000
FFFC
FFFD
COUNTER REGISTER
TIMER OVERFLOW FLAG (TOF)
Note: The MCU is in reset state when the internal reset signal is high, when it is low the MCU is running.
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ST7265x
16-BIT TIMER (Cont’d)
11.4.3.2 Output Compare
– The OCMPi pin takes OLVLi bit value (OCMPi
pin latch is forced low during reset).
In this section, the index, i, may be 1 or 2 because
there are 2 output compare functions in the 16-bit
timer.
– A timer interrupt is generated if the OCIE bit is
set in the CR2 register and the I bits are cleared
in the CC register (CC).
This function can be used to control an output
waveform or indicate when a period of time has
elapsed.
The OCiR register value required for a specific tim-
ing application can be calculated using the follow-
ing formula:
When a match is found between the Output Com-
pare register and the free running counter, the out-
put compare function:
– Assigns pins with a programmable value if the
OCIE bit is set
∆t f
* CPU
PRESC
∆ OCiR =
– Sets a flag in the status register
– Generates an interrupt if enabled
Where:
∆t
= Output compare period (in seconds)
= CPU clock frequency (in hertz)
Two 16-bit registers Output Compare Register 1
(OC1R) and Output Compare Register 2 (OC2R)
contain the value to be compared to the counter
register each timer clock cycle.
f
CPU
PRESC
= Timer prescaler factor (2, 4 or 8 de-
pending on CC[1:0] bits, see Table 27
Clock Control Bits)
MS Byte
OCiHR
LS Byte
OCiLR
OCiR
If the timer clock is an external clock, the formula
is:
These registers are readable and writable and are
not affected by the timer hardware. A reset event
changes the OCiR value to 8000h.
∆ OCiR = ∆t f
* EXT
Timing resolution is one count of the free running
Where:
counter: (f
).
CC[1:0]
CPU/
∆t
= Output compare period (in seconds)
= External timer clock frequency (in hertz)
f
EXT
Procedure:
To use the output compare function, select the fol-
lowing in the CR2 register:
Clearing the output compare interrupt request (i.e.
clearing the OCFi bit) is done by:
– Set the OCiE bit if an output is needed then the
OCMPi pin is dedicated to the output compare i
signal.
1. Reading the SR register while the OCFi bit is
set.
2. An access (read or write) to the OCiLR register.
– Select the timer clock (CC[1:0]) (see Table 27
Clock Control Bits).
The following procedure is recommended to pre-
vent the OCFi bit from being set between the time
it is read and the write to the OCiR register:
And select the following in the CR1 register:
– Select the OLVLi bit to applied to the OCMPi pins
after the match occurs.
– Write to the OCiHR register (further compares
are inhibited).
– Set the OCIE bit to generate an interrupt if it is
needed.
– Read the SR register (first step of the clearance
of the OCFi bit, which may be already set).
When a match is found between OCRi register
and CR register:
– Write to the OCiLR register (enables the output
compare function and clears the OCFi bit).
– OCFi bit is set.
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ST7265x
16-BIT TIMER (Cont’d)
Notes:
1. After a processor write cycle to the OCiHR reg-
ister, the output compare function is inhibited
until the OCiLR register is also written.
Forced Compare Output capability
When the FOLVi bit is set by software, the OLVLi
bit is copied to the OCMPi pin. The OLVi bit has to
be toggled in order to toggle the OCMPi pin when
it is enabled (OCiE bit=1). The OCFi bit is then not
set by hardware, and thus no interrupt request is
generated.
2. If the OCiE bit is not set, the OCMPi pin is a
general I/O port and the OLVLi bit will not
appear when a match is found but an interrupt
could be generated if the OCIE bit is set.
3. When the timer clock is f
/2, OCFi and
CPU
OCMPi are set while the counter value equals
the OCiR register value (see Figure 50 on
page 86).
When the timer clock is f
/4, f
/8 or in
CPU
CPU
external clock mode, OCFi and OCMPi are set
while the counter value equals the OCiR regis-
ter value plus 1 (see Figure on page 86).
4. The output compare functions can be used both
for generating external events on the OCMPi
pins even if the input capture mode is also
used.
5. The value in the 16-bit OCiR register and the
OLVi bit should be changed after each suc-
cessful comparison in order to control an output
waveform or establish a new timeout period.
Figure 49. Output Compare Block Diagram
16 BIT FREE RUNNING
OC1E
CC1 CC0
OC2E
COUNTER
(Control Register 2) CR2
16-bit
(Control Register 1) CR1
OUTPUT COMPARE
CIRCUIT
Latch
1
FOLV1
OCIE
FOLV2
OLVL2
OLVL1
OCMP1
Pin
16-bit
16-bit
Latch
2
OCMP2
Pin
OC1R Register
OCF1
OCF2
0
0
0
OC2R Register
(Status Register) SR
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ST7265x
16-BIT TIMER (Cont’d)
Figure 50. Output Compare Timing Diagram, f
=f
/2
TIMER
CPU
INTERNAL CPU CLOCK
TIMER CLOCK
COUNTER REGISTER
2ECF 2ED0 2ED1 2ED2
2ED3
2ED4
2ED3
OUTPUT COMPARE REGISTER i (OCRi)
OUTPUT COMPARE FLAG i (OCFi)
OCMPi PIN (OLVLi=1)
Figure 51. Output Compare Timing Diagram, f
=f
/4
TIMER
CPU
INTERNAL CPU CLOCK
TIMER CLOCK
2ECF 2ED0 2ED1 2ED2
2ED3
2ED4
2ED3
COUNTER REGISTER
OUTPUT COMPARE REGISTER i (OCRi)
COMPARE REGISTER i LATCH
OUTPUT COMPARE FLAG i (OCFi)
OCMPi PIN (OLVLi=1)
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16-BIT TIMER (Cont’d)
11.4.4 Low Power Modes
Mode
Description
No effect on 16-bit Timer.
Timer interrupts cause the device to exit from WAIT mode.
WAIT
HALT
16-bit Timer registers are frozen.
In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous
count when the MCU is woken up by an interrupt with “exit from HALT mode” capability or from the counter
reset value when the MCU is woken up by a RESET.
11.4.5 Interrupts
Enable
Control from
Bit
Exit
Exit
from
Halt
Event
Flag
Interrupt Event
Wait
Yes
Yes
Yes
Output Compare 1 event
Output Compare 2 event
Timer Overflow event
OCF1
OCF2
TOF
No
No
No
OCIE
TOIE
Note: The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts chap-
ter). These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt
mask bits in the CC register are reset (RIM instruction).
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ST7265x
16-BIT TIMER (Cont’d)
11.4.6 Register Description
Each Timer is associated with three control and
status registers, and with six pairs of data registers
(16-bit values) relating to the two input captures,
the two output compares, the counter and the al-
ternate counter.
Bit 4 = FOLV2 Forced Output Compare 2.
This bit is set and cleared by software.
0: No effect on the OCMP2 pin.
1: Forces the OLVL2 bit to be copied to the
OCMP2 pin, if the OC2E bit is set and even if
there is no successful comparison.
CONTROL REGISTER 1 (TCR1)
Read/Write
Bit 3 = FOLV1 Forced Output Compare 1.
This bit is set and cleared by software.
0: No effect on the OCMP1 pin.
Reset Value: 0000 0000 (00h)
1: Forces OLVL1 to be copied to the OCMP1 pin, if
the OC1E bit is set and even if there is no suc-
cessful comparison.
7
0
0
OCIE TOIE FOLV2 FOLV1 OLVL2
0
OLVL1
Bit 2 = OLVL2 Output Level 2.
Bit 7 = Reserved, forced by hardware to 0.
This bit is copied to the OCMP2 pin whenever a
successful comparison occurs with the OC2R reg-
ister and OCxE is set in the CR2 register.
Bit 6 = OCIE Output Compare Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the
OCF1 or OCF2 bit of the SR register is set.
Bit 1 = Reserved, forced by hardware to 0.
Bit 0 = OLVL1 Output Level 1.
Bit 5 = TOIE Timer Overflow Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is enabled whenever the TOF
The OLVL1 bit is copied to the OCMP1 pin when-
ever a successful comparison occurs with the
OC1R register and the OC1E bit is set in the CR2
register.
bit of the SR register is set.
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ST7265x
16-BIT TIMER (Cont’d)
CONTROL REGISTER 2 (TCR2)
Read/Write
STATUS REGISTER (TSR)
Read Only
Reset Value: 0000 0000 (00h)
Reset Value: 0000 0000 (00h)
7
0
0
The three least significant bits are not used.
7
OC1E OC2E
0
0
CC1 CC0
0
0
0
0
OCF1 TOF
0
OCF2
0
0
Bit 7 = OC1E Output Compare 1 Pin Enable.
This bit is used only to output the signal from the
timer on the OCMP1 pin (OLV1 in Output Com-
pare mode). Whatever the value of the OC1E bit,
the internal Output Compare 1 function of the timer
remains active.
0: OCMP1 pin alternate function disabled (I/O pin
free for general-purpose I/O).
Bit 7 = Reserved, forced by hardware to 0.
Bit 6 = OCF1 Output Compare Flag 1.
0: No match (reset value).
1: The content of the free running counter has
matched the content of the OC1R register. To
clear this bit, first read the SR register, then read
or write the low byte of the OC1R (OC1LR) reg-
ister.
1: OCMP1 pin alternate function enabled.
Bit 6 = OC2E Output Compare 2 Pin Enable.
This bit is used only to output the signal from the
timer on the OCMP2 pin (OLV2 in Output Com-
pare mode). Whatever the value of the OC2E bit,
the internal Output Compare 2 function of the timer
remains active.
0: OCMP2 pin alternate function disabled (I/O pin
free for general-purpose I/O).
1: OCMP2 pin alternate function enabled.
Bit 5 = TOF Timer Overflow Flag.
0: No timer overflow (reset value).
1: The free running counter rolled over from FFFFh
to 0000h. To clear this bit, first read the SR reg-
ister, then read or write the low byte of the CR
(CLR) register.
Note: Reading or writing the ACLR register does
not clear TOF.
Bits 5:4 = Reserved, forced by hardware to 0.
Bit 4 = Reserved, forced by hardware to 0.
Bits 3:2 = CC[1:0] Clock Control.
Bit 3 = OCF2 Output Compare Flag 2.
0: No match (reset value).
The timer clock mode depends on these bits:
1: The content of the free running counter has
matched the content of the OC2R register. To
clear this bit, first read the SR register, then read
or write the low byte of the OC2R (OC2LR) reg-
ister.
Table 27. Clock Control Bits
Timer Clock
fCPU / 4
CC1
CC0
0
0
1
1
0
1
0
1
fCPU / 2
fCPU / 8
Bits 2:0 = Reserved, forced by hardware to 0.
Reserved
Bits 1:0 = Reserved, forced by hardware to 0.
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ST7265x
16-BIT TIMER (Cont’d)
OUTPUT COMPARE
(OC1HR)
1
HIGH REGISTER
COUNTER HIGH REGISTER (CHR)
Read Only
Read/Write
Reset Value: 1111 1111 (FFh)
Reset Value: 1000 0000 (80h)
This is an 8-bit register that contains the high part
of the counter value.
This is an 8-bit register that contains the high part
of the value to be compared to the CHR register.
7
0
7
0
MSB
LSB
MSB
LSB
COUNTER LOW REGISTER (CLR)
OUTPUT COMPARE
(OC1LR)
1
LOW REGISTER
Read Only
Reset Value: 1111 1100 (FCh)
Read/Write
Reset Value: 0000 0000 (00h)
This is an 8-bit register that contains the low part of
the counter value. A write to this register resets the
counter. An access to this register after accessing
the SR register clears the TOF bit.
This is an 8-bit register that contains the low part of
the value to be compared to the CLR register.
7
0
7
0
MSB
LSB
MSB
LSB
OUTPUT COMPARE
(OC2HR)
2
HIGH REGISTER
ALTERNATE COUNTER HIGH REGISTER
(ACHR)
Read/Write
Reset Value: 1000 0000 (80h)
Read Only
Reset Value: 1111 1111 (FFh)
This is an 8-bit register that contains the high part
of the value to be compared to the CHR register.
This is an 8-bit register that contains the high part
of the counter value.
7
0
7
0
MSB
LSB
MSB
LSB
OUTPUT COMPARE
(OC2LR)
2
LOW REGISTER
ALTERNATE COUNTER LOW REGISTER
(ACLR)
Read/Write
Reset Value: 0000 0000 (00h)
Read Only
Reset Value: 1111 1100 (FCh)
This is an 8-bit register that contains the low part of
the value to be compared to the CLR register.
This is an 8-bit register that contains the low part of
the counter value. A write to this register resets the
counter. An access to this register after an access
to SR register does not clear the TOF bit in SR
register.
7
0
MSB
LSB
7
0
MSB
LSB
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ST7265x
16-BIT TIMER (Cont’d)
Table 28. 16-Bit Timer Register Map and Reset Values
Address
(Hex.)
Register
Name
7
6
5
4
3
2
1
0
TCR1
Reset Value
0
0
OCIE
0
TOIE
0
FOLV2
0
FOLV1
0
OLVL2
0
0
0
OLVL1
0
20
21
22
23
24
25
26
27
28
29
2A
TCR2
Reset Value
OC1E
0
OC2E
0
0
0
0
0
CC1
0
CC0
0
0
0
0
0
TSR
Reset Value
0
0
OCF1
0
TOF
0
0
0
OCF2
0
0
0
0
0
0
0
CHR
Reset Value
MSB
1
LSB
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
1
0
0
0
0
0
CLR
Reset Value
MSB
1
LSB
0
ACHR
Reset Value
MSB
1
LSB
1
ACLR
Reset Value
MSB
1
LSB
0
OC1HR
Reset Value
MSB
1
LSB
0
OC1LR
Reset Value
MSB
0
LSB
0
OC2HR
Reset Value
MSB
1
LSB
0
OC2LR
Reset Value
MSB
0
LSB
0
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ST7265x
11.5 PWM/BRM GENERATOR (DAC)
11.5.1 Introduction
PWM Generation
This PWM/BRM peripheral includes a 6-bit Pulse
Width Modulator (PWM) and a 4-bit Binary Rate
Multiplier (BRM) Generator. It allows the digital to
analog conversion (DAC) when used with external
filtering.
The counter increments continuously, clocked at
internal CPU clock. Whenever the 6 least signifi-
cant bits of the counter (defined as the PWM coun-
ter) overflow, the output level for all active chan-
nels is set.
Note: The number of PWM and BRM channels
available depends on the device. Refer to the de-
vice pin description and register map.
The state of the PWM counter is continuously
compared to the PWM binary weight for each
channel, as defined in the relevant PWM register,
and when a match occurs the output level for that
channel is reset.
11.5.2 Main Features
■ Fixed frequency: f
/64
CPU
This Pulse Width modulated signal must be fil-
tered, using an external RC network placed as
close as possible to the associated pin. This pro-
vides an analog voltage proportional to the aver-
age charge passed to the external capacitor. Thus
for a higher mark/space ratio (high time much
greater than low time) the average output voltage
is higher. The external components of the RC net-
work should be selected for the filtering level re-
quired for control of the system variable.
■ Resolution: TCPU
10
■ Steps of VDD/2 (5mV if VDD=5V)
11.5.3 Functional Description
The 10 bits of the 10-bit PWM/BRM are distributed
as 6 PWM bits and 4 BRM bits. The generator con-
sists of a 10-bit counter (common for all channels),
a comparator and the PWM/BRM generation logic.
Each output may individually have its polarity in-
verted by software, and can also be used as a log-
ical output.
Figure 52. PWM Generation
COUNTER
OVERFLOW
63
OVERFLOW
OVERFLOW
COMPARE
VALUE
000
t
t
PWM OUTPUT
TCPU x 64
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ST7265x
PWM/BRM GENERATOR (Cont’d)
PWM/BRM Outputs
The PWM/BRM outputs are assigned to dedicated
pins.
Table 29. 6-Bit PWM Ripple After Filtering
The PWM/BRM outputs can be connected to an
Cext (µF)
0.128
1.28
V RIPPLE (mV)
RC filter (see Figure 53 for an example).
78
The RC filter time must be higher than T
x64.
CPU
7.8
Figure 53. Typical PWM Output Filter
12.8
0.78
With RC filter (R=1KΩ),
fCPU = 8 MHz
OUTPUT
VOLTAGE
V
DD = 5V
OUTPUT
STAGE
PWM Duty Cycle 50%
R
ext
C
R=R
ext
ext
Note: after a reset these pins are tied low by de-
fault and are not in a high impedance state.
Figure 54. PWM Simplified Voltage Output After Filtering
V
DD
PWMOUT
0V
V
(mV)
V
ripple
V
DD
OUTPUT
VOLTAGE
OUTAVG
0V
"CHARGE"
"DISCHARGE"
"CHARGE"
"DISCHARGE"
V
DD
PWMOUT
0V
V
DD
V
(mV)
ripple
OUTPUT
VOLTAGE
0V
V
OUTAVG
"CHARGE"
"DISCHARGE"
"CHARGE"
"DISCHARGE"
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ST7265x
PWM/BRM GENERATOR (Cont’d)
BRM Generation
Note. If 00h is written to both PWM and BRM reg-
isters, the generator output will remain at “0”. Con-
versely, if both registers hold data 3Fh and 0Fh,
respectively, the output will remain at “1” for all in-
tervals 1 to 15, but it will return to zero at interval 0
for an amount of time corresponding to the PWM
The BRM bits allow the addition of a pulse to wid-
en a standard PWM pulse for specific PWM cy-
cles. This has the effect of “fine-tuning” the PWM
Duty cycle (without modifying the base duty cycle),
thus, with the external filtering, providing additional
fine voltage steps.
resolution (T
).
CPU
An output can be set to a continuous “1” level by
clearing the PWM and BRM values and setting
POL = “1” (inverted polarity) in the PWM register.
This allows a PWM/BRM channel to be used as an
additional I/O pin if the DAC function is not re-
quired.
The incremental pulses (with duration of T
) are
CPU
added to the beginning of the original PWM pulse.
The PWM intervals which are added to are speci-
fied in the 4-bit BRM register and are encoded as
shown in the following table. The BRM values
shown may be combined together to provide a
summation of the incremental pulse intervals
specified.
The pulse increment corresponds to the PWM res-
olution.
Table 30. Bit BRM Added Pulse Intervals
(Interval #0 not selected).
For example,if
– Data 18h is written to the PWM register
BRM 4 - Bit Data
0000
Incremental Pulse Intervals
none
– Data 06h (00000110b) is written to the BRM reg-
ister
0001
i = 8
– with a 8MHz internal clock (125ns resolution)
0010
i = 4,12
Then 3.0 µs-long pulse will be output at 8 µs inter-
vals, except for cycles numbered 2,4,6,10,12,14,
where the pulse is broadened to 3.125 µs.
0100
i = 2,6,10,14
i = 1,3,5,7,9,11,13,15
1000
Figure 55. BRM pulse addition (PWM > 0)
m = 15
m = 0
m = 1
m = 2
TCPU x 64
TCPU x 64
TCPU x 64
TCPU x 64
TCPU x 64 increment
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ST7265x
PWM/BRM GENERATOR (Cont’d)
Figure 56. Simplified Filtered Voltage Output Schematic with BRM Added
=
=
VDD
PWMOUT
0V
VDD
BRM = 1
BRM = 0
OUTPUT
VOLTAGE
0V
TCPU
BRM
EXTENDED PULSE
Figure 57. Graphical Representation of 4-Bit BRM Added Pulse Positions
PWM Pulse Number (0-15)
BRM VALUE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0001 bit0=1
0010 bit1=1
0100 bit2=1
1000 bit3=1
Examples
0110
1111
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ST7265x
PWM/BRM GENERATOR (Cont’d)
Figure 58. Precision for PWM/BRM Tuning for VOUTEFF (After filtering)
11.5.4 Register Description
BRM REGISTERS
On a channel basis, the 10 bits are separated into
two data registers:
Read / Write
Reset Value: 0000 0000 (00h)
Note: The number of PWM and BRM channels
available depends on the device. Refer to the de-
vice pin description and register map.
7
0
B7
B6
B5
B4
B3
B2
B1
B0
PULSE BINARY WEIGHT REGISTERS (PWMi)
Read / Write
Reset Value 1000 0000 (80h)
These registers define the intervals where an in-
cremental pulse is added to the beginning of the
original PWM pulse. Two BRM channel values
share the same register.
7
1
0
POL
P5
P4
P3
P2
P1
P0
Bit 7:4 = B[7:4] BRM Bits (channel i+1).
Bit 3:0 = B[3:0] BRM Bits (channel i)
Bit 7 = Reserved (Forced by hardware to “1”)
Bit 6 = POL Polarity Bit for channel i.
0: The channel i outputs a “1” level during the bina-
ry pulse and a “0” level after.
1: The channel i outputs a “0” level during the bina-
ry pulse and a “1” level after.
Note: From the programmer's point of view, the
PWM and BRM registers can be regarded as be-
ing combined to give one data value.
Bit 5:0 = P[5:0] PWM Pulse Binary Weight for
channel i.
This register contains the binary value of the pulse.
For example :
1
POL
P
P
P
P
P
P
+
B
B
B
B
Effective (with external RC filtering) DAC value
1
POL
P
P
P
P
P
P
B
B
B
B
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PULSE WIDTH MODULATION (Cont’d)
Table 31. PWM Register Map and Reset Values
Address
(Hex.)
Register
Name
7
6
5
4
3
2
1
0
PWM0
1
1
POL
0
P5
0
P4
0
P3
0
P2
0
P1
0
P0
0
4D
4E
4F
Reset Value
BRM10
B7
0
B6
0
B5
0
B4
0
B3
0
B2
0
B1
0
B0
0
Reset Value
PWM1
1
1
POL
0
P5
0
P4
0
P3
0
P2
0
P1
0
P0
0
Reset Value
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ST7265x
11.6 SERIAL PERIPHERAL INTERFACE (SPI)
11.6.1 Introduction
11.6.3 General Description
The Serial Peripheral Interface (SPI) allows full-
duplex, synchronous, serial communication with
external devices. An SPI system may consist of a
master and one or more slaves however the SPI
interface can not be a master in a multi-master
system.
Figure 59 shows the serial peripheral interface
(SPI) block diagram. There are 3 registers:
– SPI Control Register (SPICR)
– SPI Control/Status Register (SPICSR)
– SPI Data Register (SPIDR)
11.6.2 Main Features
■ Full duplex synchronous transfers (on 3 lines)
■ Simplex synchronous transfers (on 2 lines)
■ Master or slave operation
The SPI is connected to external devices through
3 pins:
– MISO: Master In / Slave Out data
– MOSI: Master Out / Slave In data
■ Six master mode frequencies (f
/2 max.)
CPU
■ f
CPU
/2 max. slave mode frequency
– SCK: Serial Clock out by SPI masters and in-
put by SPI slaves
■ SS Management by software or hardware
■ Programmable clock polarity and phase
■ End of transfer interrupt flag
– SS: Slave select:
This input signal acts as a ‘chip select’ to let
the SPI master communicate with slaves indi-
vidually and to avoid contention on the data
lines. Slave SS inputs can be driven by stand-
ard I/O ports on the master MCU.
■ Write collision, Master Mode Fault and Overrun
flags
Figure 59. Serial Peripheral Interface Block Diagram
Data/Address Bus
Read
SPIDR
Interrupt
request
Read Buffer
MOSI
7
0
SPICSR
MISO
8-Bit Shift Register
SPIF WCOL OVR MODF
0
SOD SSM SSI
Write
SOD
bit
1
SS
SPI
STATE
0
SCK
CONTROL
7
0
SPICR
MSTR
CPHA SPR1 SPR0
SPIE SPE SPR2
CPOL
MASTER
CONTROL
SERIAL CLOCK
GENERATOR
SS
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SERIAL PERIPHERAL INTERFACE (Cont’d)
11.6.3.1 Functional Description
sponds by sending data to the master device via
the MISO pin. This implies full duplex communica-
tion with both data out and data in synchronized
with the same clock signal (which is provided by
the master device via the SCK pin).
A basic example of interconnections between a
single master and a single slave is illustrated in
Figure 60.
The MOSI pins are connected together and the
MISO pins are connected together. In this way
data is transferred serially between master and
slave (most significant bit first).
To use a single data line, the MISO and MOSI pins
must be connected at each node (in this case only
simplex communication is possible).
Four possible data/clock timing relationships may
be chosen (see Figure 63) but master and slave
must be programmed with the same timing mode.
The communication is always initiated by the mas-
ter. When the master device transmits data to a
slave device via MOSI pin, the slave device re-
Figure 60. Single Master/ Single Slave Application
SLAVE
MASTER
MSBit
LSBit
MSBit
LSBit
MISO
MOSI
MISO
MOSI
8-BIT SHIFT REGISTER
8-BIT SHIFT REGISTER
SPI
CLOCK
GENERATOR
SCK
SS
SCK
SS
+5V
Not used if SS is managed
by software
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ST7265x
SERIAL PERIPHERAL INTERFACE (Cont’d)
11.6.3.2 Slave Select Management
In Slave Mode:
As an alternative to using the SS pin to control the
Slave Select signal, the application can choose to
manage the Slave Select signal by software. This
is configured by the SSM bit in the SPICSR regis-
ter (see Figure 62)
There are two cases depending on the data/clock
timing relationship (see Figure 61):
If CPHA=1 (data latched on 2nd clock edge):
– SS internal must be held low during the entire
transmission. This implies that in single slave
applications the SS pin either can be tied to
In software management, the external SS pin is
free for other application uses and the internal SS
signal level is driven by writing to the SSI bit in the
SPICSR register.
V
, or made free for standard I/O by manag-
SS
ing the SS function by software (SSM= 1 and
SSI=0 in the in the SPICSR register)
If CPHA=0 (data latched on 1st clock edge):
In Master mode:
– SS internal must be held low during byte
transmission and pulled high between each
byte to allow the slave to write to the shift reg-
ister. If SS is not pulled high, a Write Collision
error will occur when the slave writes to the
shift register (see Section 11.6.5.3).
– SS internal must be held high continuously
Figure 61. Generic SS Timing Diagram
Byte 3
Byte 2
MOSI/MISO
Master SS
Byte 1
Slave SS
(if CPHA=0)
Slave SS
(if CPHA=1)
Figure 62. Hardware/Software Slave Select Management
SSM bit
SSI bit
1
0
SS internal
SS external pin
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ST7265x
SERIAL PERIPHERAL INTERFACE (Cont’d)
11.6.3.3 Master Mode Operation
11.6.3.5 Slave Mode Operation
In master mode, the serial clock is output on the
SCK pin. The clock frequency, polarity and phase
are configured by software (refer to the description
of the SPICSR register).
In slave mode, the serial clock is received on the
SCK pin from the master device.
To operate the SPI in slave mode:
1. Write to the SPICSR register to perform the fol-
lowing actions:
Note: The idle state of SCK must correspond to
the polarity selected in the SPICSR register (by
pulling up SCK if CPOL=1 or pulling down SCK if
CPOL=0).
– Select the clock polarity and clock phase by
configuring the CPOL and CPHA bits (see
Figure 63).
Note: The slave must have the same CPOL
To operate the SPI in master mode, perform the
following two steps in order (if the SPICSR register
is not written first, the SPICR register setting may
be not taken into account):
and CPHA settings as the master.
– Manage the SS pin as described in Section
11.6.3.2 and Figure 61. If CPHA=1 SS must
be held low continuously. If CPHA=0 SS must
be held low during byte transmission and
pulled up between each byte to let the slave
write in the shift register.
1. Write to the SPICSR register:
– Select the clock frequency by configuring the
SPR[2:0] bits.
– Select the clock polarity and clock phase by
configuring the CPOL and CPHA bits. Figure
63 shows the four possible configurations.
Note: The slave must have the same CPOL
and CPHA settings as the master.
2. Write to the SPICR register to clear the MSTR
bit and set the SPE bit to enable the SPI I/O
functions.
11.6.3.6 Slave Mode Transmit Sequence
When software writes to the SPIDR register, the
data byte is loaded into the 8-bit shift register and
then shifted out serially to the MISO pin most sig-
nificant bit first.
– Either set the SSM bit and set the SSI bit or
clear the SSM bit and tie the SS pin high for
the complete byte transmit sequence.
2. Write to the SPICR register:
The transmit sequence begins when the slave de-
vice receives the clock signal and the most signifi-
cant bit of the data on its MOSI pin.
– Set the MSTR and SPE bits
Note: MSTR and SPE bits remain set only if
SS is high).
The transmit sequence begins when software
writes a byte in the SPIDR register.
When data transfer is complete:
– The SPIF bit is set by hardware
11.6.3.4 Master Mode Transmit Sequence
– An interrupt request is generated if SPIE bit is
set and interrupt mask in the CCR register is
cleared.
When software writes to the SPIDR register, the
data byte is loaded into the 8-bit shift register and
then shifted out serially to the MOSI pin most sig-
nificant bit first.
Clearing the SPIF bit is performed by the following
software sequence:
When data transfer is complete:
– The SPIF bit is set by hardware
1. An access to the SPICSR register while the
SPIF bit is set.
– An interrupt request is generated if the SPIE
bit is set and the interrupt mask in the CCR
register is cleared.
2. A write or a read to the SPIDR register.
Notes: While the SPIF bit is set, all writes to the
SPIDR register are inhibited until the SPICSR reg-
ister is read.
Clearing the SPIF bit is performed by the following
software sequence:
The SPIF bit can be cleared during a second
transmission; however, it must be cleared before
the second SPIF bit in order to prevent an Overrun
condition (see Section 11.6.5.2).
1. An access to the SPICSR register while the
SPIF bit is set
2. A read to the SPIDR register.
Note: While the SPIF bit is set, all writes to the
SPIDR register are inhibited until the SPICSR reg-
ister is read.
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SERIAL PERIPHERAL INTERFACE (Cont’d)
11.6.4 Clock Phase and Clock Polarity
Figure 63, shows an SPI transfer with the four
combinations of the CPHA and CPOL bits. The di-
agram may be interpreted as a master or slave
timing diagram where the SCK pin, the MISO pin,
the MOSI pin are directly connected between the
master and the slave device.
Four possible timing relationships may be chosen
by software, using the CPOL and CPHA bits (See
Figure 63).
Note: The idle state of SCK must correspond to
the polarity selected in the SPICSR register (by
pulling up SCK if CPOL=1 or pulling down SCK if
CPOL=0).
Note: If CPOL is changed at the communication
byte boundaries, the SPI must be disabled by re-
setting the SPE bit.
The combination of the CPOL clock polarity and
CPHA (clock phase) bits selects the data capture
clock edge
Figure 63. Data Clock Timing Diagram
CPHA =1
SCK
(CPOL = 1)
SCK
(CPOL = 0)
Bit 4
Bit 4
Bit3
Bit3
Bit 2
Bit 2
Bit 1
Bit 1
LSBit
LSBit
MSBit Bit 6
MSBit Bit 6
Bit 5
Bit 5
MISO
(from master)
MOSI
(from slave)
SS
(to slave)
CAPTURE STROBE
CPHA =0
SCK
(CPOL = 1)
SCK
(CPOL = 0)
Bit 4
Bit 4
Bit3
Bit 2
Bit 2
Bit 1
Bit 1
LSBit
LSBit
MISO
(from master)
MSBit Bit 6
MSBit Bit 6
Bit 5
Bit 5
Bit3
MOSI
(from slave)
SS
(to slave)
CAPTURE STROBE
Note: This figure should not be used as a replacement for parametric information.
Refer to the Electrical Characteristics chapter.
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SERIAL PERIPHERAL INTERFACE (Cont’d)
11.6.5 Error Flags
11.6.5.2 Overrun Condition (OVR)
11.6.5.1 Master Mode Fault (MODF)
An overrun condition occurs, when the master de-
vice has sent a data byte and the slave device has
not cleared the SPIF bit issued from the previously
transmitted byte.
Master mode fault occurs when the master device
has its SS pin pulled low.
When a Master mode fault occurs:
When an Overrun occurs:
– The MODF bit is set and an SPI interrupt re-
quest is generated if the SPIE bit is set.
– The OVR bit is set and an interrupt request is
generated if the SPIE bit is set.
– The SPE bit is reset. This blocks all output
from the device and disables the SPI periph-
eral.
In this case, the receiver buffer contains the byte
sent after the SPIF bit was last cleared. A read to
the SPIDR register returns this byte. All other
bytes are lost.
– The MSTR bit is reset, thus forcing the device
into slave mode.
The OVR bit is cleared by reading the SPICSR
register.
Clearing the MODF bit is done through a software
sequence:
11.6.5.3 Write Collision Error (WCOL)
1. A read access to the SPICSR register while the
MODF bit is set.
A write collision occurs when the software tries to
write to the SPIDR register while a data transfer is
taking place with an external device. When this
happens, the transfer continues uninterrupted;
and the software write will be unsuccessful.
2. A write to the SPICR register.
Notes: To avoid any conflicts in an application
with multiple slaves, the SS pin must be pulled
high during the MODF bit clearing sequence. The
SPE and MSTR bits may be restored to their orig-
inal state during or after this clearing sequence.
Write collisions can occur both in master and slave
mode. See also Section 11.6.3.2 Slave Select
Management.
Hardware does not allow the user to set the SPE
and MSTR bits while the MODF bit is set except in
the MODF bit clearing sequence.
Note: a "read collision" will never occur since the
received data byte is placed in a buffer in which
access is always synchronous with the MCU oper-
ation.
In a slave device, the MODF bit can not be set, but
in a multi master configuration the device can be in
slave mode with the MODF bit set.
The WCOL bit in the SPICSR register is set if a
write collision occurs.
The MODF bit indicates that there might have
been a multi-master conflict and allows software to
handle this using an interrupt routine and either
perform to a reset or return to an application de-
fault state.
No SPI interrupt is generated when the WCOL bit
is set (the WCOL bit is a status flag only).
Clearing the WCOL bit is done through a software
sequence (see Figure 64).
Figure 64. Clearing the WCOL bit (Write Collision Flag) Software Sequence
Clearing sequence after SPIF = 1 (end of a data byte transfer)
Read SPICSR
1st Step
RESULT
SPIF =0
WCOL=0
2nd Step
Read SPIDR
Clearing sequence before SPIF = 1 (during a data byte transfer)
Read SPICSR
1st Step
Note: Writing to the SPIDR regis-
RESULT
ter instead of reading it does not
reset the WCOL bit
2nd Step
Read SPIDR
WCOL=0
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SERIAL PERIPHERAL INTERFACE (Cont’d)
11.6.5.4 Single Master System
Note: To prevent a bus conflict on the MISO line
the master allows only one active slave device
during a transmission.
A typical single master system may be configured,
using an MCU as the master and four MCUs as
slaves (see Figure 65).
For more security, the slave device may respond
to the master with the received data byte. Then the
master will receive the previous byte back from the
slave device if all MISO and MOSI pins are con-
nected and the slave has not written to its SPIDR
register.
The master device selects the individual slave de-
vices by using four pins of a parallel port to control
the four SS pins of the slave devices.
The SS pins are pulled high during reset since the
master device ports will be forced to be inputs at
that time, thus disabling the slave devices.
Other transmission security methods can use
ports for handshake lines or data bytes with com-
mand fields.
Figure 65. Single Master / Multiple Slave Configuration
SS
SS
SS
SS
SCK
SCK
Slave
SCK
Slave
MCU
SCK
Slave
MCU
Slave
MCU
MCU
MOSI MISO
MOSI MISO
MOSI MISO
MOSI MISO
MOSI MISO
SCK
Master
MCU
5V
SS
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SERIAL PERIPHERAL INTERFACE (Cont’d)
11.6.6 Low Power Modes
form an extra communications cycle to bring the
SPI from Halt mode state to normal state. If the
SPI exits from Slave mode, it returns to normal
state immediately.
Mode
Description
No effect on SPI.
WAIT
SPI interrupt events cause the device to exit
from WAIT mode.
Caution: The SPI can wake up the ST7 from Halt
mode only if the Slave Select signal (external SS
pin or the SSI bit in the SPICSR register) is low
when the ST7 enters Halt mode. So if Slave selec-
tion is configured as external (see Section
11.6.3.2), make sure the master drives a low level
on the SS pin when the slave enters Halt mode.
SPI registers are frozen.
In HALT mode, the SPI is inactive. SPI oper-
ation resumes when the MCU is woken up by
an interrupt with “exit from HALT mode” ca-
pability. The data received is subsequently
read from the SPIDR register when the soft-
ware is running (interrupt vector fetching). If
several data are received before the wake-
up event, then an overrun error is generated.
This error can be detected after the fetch of
the interrupt routine that woke up the device.
HALT
11.6.7 Interrupts
Enable
Control from
Bit
Exit
Exit
from
Halt
Event
Flag
Interrupt Event
Wait
SPI End of Transfer
Event
SPIF
Yes
Yes
11.6.6.1 Using the SPI to wakeup the MCU from
Halt mode
Master Mode Fault
Event
SPIE
MODF
OVR
Yes
Yes
No
No
In slave configuration, the SPI is able to wakeup
the ST7 device from HALT mode through a SPIF
interrupt. The data received is subsequently read
from the SPIDR register when the software is run-
ning (interrupt vector fetch). If multiple data trans-
fers have been performed before software clears
the SPIF bit, then the OVR bit is set by hardware.
Overrun Error
Note: The SPI interrupt events are connected to
the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding
Enable Control Bit is set and the interrupt mask in
the CC register is reset (RIM instruction).
Note: When waking up from Halt mode, if the SPI
remains in Slave mode, it is recommended to per-
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SERIAL PERIPHERAL INTERFACE (Cont’d)
11.6.8 Register Description
CONTROL REGISTER (SPICR)
Read/Write
Bit 3 = CPOL Clock Polarity.
This bit is set and cleared by software. This bit de-
termines the idle state of the serial Clock. The
CPOL bit affects both the master and slave
modes.
0: SCK pin has a low level idle state
1: SCK pin has a high level idle state
Reset Value: 0000 xxxx (0xh)
7
0
SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0
Note: If CPOL is changed at the communication
byte boundaries, the SPI must be disabled by re-
setting the SPE bit.
Bit 7 = SPIE Serial Peripheral Interrupt Enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SPI interrupt is generated whenever
SPIF=1, MODF=1 or OVR=1 in the SPICSR
register
Bit 2 = CPHA Clock Phase.
This bit is set and cleared by software.
0: The first clock transition is the first data capture
edge.
1: The second clock transition is the first capture
edge.
Bit 6 = SPE Serial Peripheral Output Enable.
This bit is set and cleared by software. It is also
cleared by hardware when, in master mode, SS=0
(see Section 11.6.5.1 Master Mode Fault
(MODF)). The SPE bit is cleared by reset, so the
SPI peripheral is not initially connected to the ex-
ternal pins.
Note: The slave must have the same CPOL and
CPHA settings as the master.
Bits 1:0 = SPR[1:0] Serial Clock Frequency.
These bits are set and cleared by software. Used
with the SPR2 bit, they select the baud rate of the
SPI serial clock SCK output by the SPI in master
mode.
0: I/O pins free for general purpose I/O
1: SPI I/O pin alternate functions enabled
Bit 5 = SPR2 Divider Enable.
Note: These 2 bits have no effect in slave mode.
This bit is set and cleared by software and is
cleared by reset. It is used with the SPR[1:0] bits to
set the baud rate. Refer to Table 32 SPI Master
mode SCK Frequency.
Table 32. SPI Master mode SCK Frequency
Serial Clock
SPR2 SPR1 SPR0
0: Divider by 2 enabled
1: Divider by 2 disabled
f
f
f
/2
/4
/8
1
0
0
1
0
0
0
0
0
1
1
1
0
0
1
0
0
1
CPU
CPU
CPU
Note: This bit has no effect in slave mode.
f
f
f
/16
/32
/64
CPU
CPU
CPU
Bit 4 = MSTR Master Mode.
This bit is set and cleared by software. It is also
cleared by hardware when, in master mode, SS=0
(see Section 11.6.5.1 Master Mode Fault
(MODF)).
0: Slave mode
1: Master mode. The function of the SCK pin
changes from an input to an output and the func-
tions of the MISO and MOSI pins are reversed.
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SERIAL PERIPHERAL INTERFACE (Cont’d)
CONTROL/STATUS REGISTER (SPICSR)
Read/Write (some bits Read Only)
Reset Value: 0000 0000 (00h)
Bit 2 = SOD SPI Output Disable.
This bit is set and cleared by software. When set, it
disables the alternate function of the SPI output
(MOSI in master mode / MISO in slave mode)
0: SPI output enabled (if SPE=1)
7
0
SPIF
WCOL OVR MODF
-
SOD SSM SSI
1: SPI output disabled
Bit 7 = SPIF Serial Peripheral Data Transfer Flag
(Read only).
Bit 1 = SSM SS Management.
This bit is set and cleared by software. When set, it
disables the alternate function of the SPI SS pin
and uses the SSI bit value instead. See Section
11.6.3.2 Slave Select Management.
0: Hardware management (SS managed by exter-
nal pin)
1: Software management (internal SS signal con-
trolled by SSI bit. External SS pin free for gener-
al-purpose I/O)
This bit is set by hardware when a transfer has
been completed. An interrupt is generated if
SPIE=1 in the SPICR register. It is cleared by a
software sequence (an access to the SPICSR
register followed by a write or a read to the
SPIDR register).
0: Data transfer is in progress or the flag has been
cleared.
1: Data transfer between the device and an exter-
nal device has been completed.
Bit 0 = SSI SS Internal Mode.
Note: While the SPIF bit is set, all writes to the
SPIDR register are inhibited until the SPICSR reg-
ister is read.
This bit is set and cleared by software. It acts as a
‘chip select’ by controlling the level of the SS slave
select signal when the SSM bit is set.
0: Slave selected
Bit 6 = WCOL Write Collision status (Read only).
This bit is set by hardware when a write to the
SPIDR register is done during a transmit se-
quence. It is cleared by a software sequence (see
Figure 64).
1: Slave deselected
DATA I/O REGISTER (SPIDR)
Read/Write
Reset Value: Undefined
0: No write collision occurred
1: A write collision has been detected
7
0
D7
D6
D5
D4
D3
D2
D1
D0
Bit 5 = OVR SPI Overrun error (Read only).
This bit is set by hardware when the byte currently
being received in the shift register is ready to be
transferred into the SPIDR register while SPIF = 1
(See Section 11.6.5.2). An interrupt is generated if
SPIE = 1 in SPICSR register. The OVR bit is
cleared by software reading the SPICSR register.
0: No overrun error
The SPIDR register is used to transmit and receive
data on the serial bus. In a master device, a write
to this register will initiate transmission/reception
of another byte.
Notes: During the last clock cycle the SPIF bit is
set, a copy of the received data byte in the shift
register is moved to a buffer. When the user reads
the serial peripheral data I/O register, the buffer is
actually being read.
1: Overrun error detected
Bit 4 = MODF Mode Fault flag (Read only).
This bit is set by hardware when the SS pin is
pulled low in master mode (see Section 11.6.5.1
Master Mode Fault (MODF)). An SPI interrupt can
be generated if SPIE=1 in the SPICSR register.
This bit is cleared by a software sequence (An ac-
cess to the SPICSR register while MODF=1 fol-
lowed by a write to the SPICR register).
While the SPIF bit is set, all writes to the SPIDR
register are inhibited until the SPICSR register is
read.
Warning: A write to the SPIDR register places
data directly into the shift register for transmission.
A read to the SPIDR register returns the value lo-
cated in the buffer and not the content of the shift
register (see Figure 59).
0: No master mode fault detected
1: A fault in master mode has been detected
Bit 3 = Reserved, must be kept cleared.
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SERIAL PERIPHERAL INTERFACE (Cont’d)
Table 33. SPI Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
SPIDR
Reset Value
MSB
x
LSB
x
19
1A
1B
x
x
x
x
x
x
SPICR
Reset Value
SPIE
0
SPE
0
SPR2
0
MSTR
0
CPOL
x
CPHA
x
SPR1
x
SPR0
x
SPICSR
Reset Value
SPIF
0
WCOL
0
OVR
0
MODF
0
SOD
0
SSM
0
SSI
0
0
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11.7 I²C SINGLE MASTER BUS INTERFACE (I2C)
11.7.1 Introduction
2
and a Fast I C bus. This selection is made by soft-
ware.
2
The I C Bus Interface serves as an interface be-
2
tween the microcontroller and the serial I C bus. It
Mode Selection
provides single master functions, and controls all
I C bus-specific sequencing, protocol and timing.
It supports fast I²C mode (400kHz).
The interface can operate in the two following mo-
des:
2
– Master transmitter/receiver
By default, it is idle.
11.7.2 Main Features
2
– Parallel bus/I C protocol converter
The interface automatically switches from idle to
master after it generates a START condition and
from master to idle after it generates a STOP con-
dition.
– Interrupt generation
2
2
– Standard I C mode/Fast I C mode
– 7-bit Addressing
2
Communication Flow
■ I C single Master Mode
The interface initiates a data transfer and genera-
tes the clock signal. A serial data transfer always
begins with a start condition and ends with a stop
condition. Both start and stop conditions are gene-
rated by software.
– End of byte transmission flag
– Transmitter/Receiver flag
– Clock generation
11.7.3 General Description
Data and addresses are transferred as 8-bit bytes,
MSB first. The first byte following the start condi-
tion is the address byte.
In addition to receiving and transmitting data, this
interface converts it from serial to parallel format
and vice versa, using either an interrupt or polled
handshake. The interrupts are enabled or disabled
A 9th clock pulse follows the 8 clock cycles of a
byte transfer, during which the receiver must send
an acknowledge bit to the transmitter. Refer to Fig-
ure 66.
2
by software. The interface is connected to the I C
bus by a data pin (SDAI) and by a clock pin (SCLI).
2
It can be connected both with a standard I C bus
2
Figure 66. I C BUS Protocol
SDA
MSB
ACK
SCL
1
2
8
9
START
STOP
CONDITION
CONDITION
VR02119B
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I²C SINGLE MASTER BUS INTERFACE (Cont’d)
Acknowledge may be enabled and disabled by
software.
The SCL frequency (F ) is controlled by a pro-
scl
grammable clock divider which depends on the
2
2
I C bus mode.
The speed of the I C interface may be selected
2
between Standard (0-100KHz) and Fast I C (100-
When the I2C cell is enabled, the SDA and SCL
ports must be configured as floating open-drain
output or floating input. In this case, the value of
the external pull-up resistance used depends on
the application.
400KHz).
SDA/SCL Line Control
Transmitter mode: the interface holds the clock
line low before transmission to wait for the micro-
controller to write the byte in the Data Register.
When the I2C cell is disabled, the SDA and SCL
ports revert to being standard I/O port pins.
Receiver mode: the interface holds the clock line
low after reception to wait for the microcontroller to
read the byte in the Data Register.
2
Figure 67. I C Interface Block Diagram
DATA REGISTER (DR)
DATA SHIFT REGISTER
SDAI
DATA CONTROL
SDA
SCLI
CLOCK CONTROL
SCL
CLOCK CONTROL REGISTER (CCR)
CONTROL REGISTER (CR)
STATUS REGISTER 1 (SR1)
STATUS REGISTER 2 (SR2)
CONTROL LOGIC
INTERRUPT
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I²C SINGLE MASTER BUS INTERFACE (Cont’d)
11.7.4 Functional Description (Master Mode)
– Acknowledge pulse if if the ACK bit is set
Refer to the CR, SR1 and SR2 registers in Section
11.7.7. for the bit definitions.
– EVF and BTF bits are set by hardware with an in-
terrupt if the ITE bit is set.
2
By default the I C interface operates in idle mode
Then the interface waits for a read of the SR1 re-
gister followed by a read of the DR register, hol-
ding the SCL line low (see Figure 68 Transfer se-
quencing EV3).
(M/IDL bit is cleared) except when it initiates a
transmit or receive sequence.
To switch from default idle mode to Master mode a
Start condition generation is needed.
To close the communication: before reading the
last byte from the DR register, set the STOP bit to
generate the Stop condition. The interface goes
automatically back to idle mode (M/IDL bit clea-
red).
Start condition and Transmit Slave address
Setting the START bit causes the interface to
switch to Master mode (M/IDL bit set) and genera-
tes a Start condition.
Note: In order to generate the non-acknowledge
pulse after the last received data byte, the ACK bit
must be cleared just before reading the second
last data byte.
Once the Start condition is sent:
– The EVF and SB bits are set by hardware with
an interrupt if the ITE bit is set.
Master Transmitter
Then the master waits for a read of the SR1 regis-
ter followed by a write in the DR register with the
Slave address byte, holding the SCL line low
(see Figure 68 Transfer sequencing EV1).
Following the address transmission and after SR1
register has been read, the master sends bytes
from the DR register to the SDA line via the inter-
nal shift register.
The master waits for a read of the SR1 register fol-
lowed by a write in the DR register, holding the
SCL line low (see Figure 68 Transfer sequencing
EV4).
Then the slave address byte is sent to the SDA
line via the internal shift register.
After completion of this transfer (and acknowledge
from the slave if the ACK bit is set):
When the acknowledge bit is received, the
interface sets:
– The EVF bit is set by hardware with interrupt
generation if the ITE bit is set.
– EVF and BTF bits with an interrupt if the ITE bit
is set.
Then the master waits for a read of the SR1 regis-
ter followed by a write in the CR register (for exam-
ple set PE bit), holding the SCL line low (see Fi-
gure 68 Transfer sequencing EV2).
To close the communication: after writing the last
byte to the DR register, set the STOP bit to gene-
rate the Stop condition. The interface goes auto-
matically back to idle mode (M/IDL bit cleared).
Next the master must enter Receiver or Transmit-
ter mode.
Error Case
– AF: Detection of a non-acknowledge bit. In this
case, the EVF and AF bits are set by hardware
with an interrupt if the ITE bit is set. To resume,
set the START or STOP bit.
Master Receiver
Following the address transmission and after SR1
and CR registers have been accessed, the master
receives bytes from the SDA line into the DR regis-
ter via the internal shift register. After each byte
the interface generates in sequence:
Note: The SCL line is not held low.
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I²C SINGLE MASTER BUS INTERFACE (Cont’d)
Figure 68. Transfer Sequencing
Master receiver:
S
Address
A
Data1
A
Data2
A
DataN NA
P
.....
EV1
EV2
EV3
A
EV3
A
EV3
A
Master transmitter:
S
Address
A
Data1
Data2
DataN
P
.....
EV1
EV2 EV4
EV4
EV4
EV4
Legend:
S=Start, P=Stop, A=Acknowledge, NA=Non-acknowledge
EVx=Event (with interrupt if ITE=1)
EV1: EVF=1, SB=1, cleared by reading SR1 register followed by writing DR register.
EV2: EVF=1, cleared by reading SR1 register followed by writing CR register (for example PE=1).
EV3: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register.
EV4: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register.
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I²C SINGLE MASTER BUS INTERFACE (Cont’d)
11.7.5 Low Power Modes
Mode
Description
2
No effect on I C interface.
WAIT
2
I C interrupts cause the device to exit from WAIT mode.
2
I C registers are frozen.
2
2
HALT
In HALT mode, the I C interface is inactive and does not acknowledge data on the bus. The I C interface
resumes operation when the MCU is woken up by an interrupt with “exit from HALT mode” capability.
11.7.6 Interrupts
Figure 69. Event Flags and Interrupt Generation
ITE
BTF
SB
AF
INTERRUPT
EVF
*
* EVF can also be set by EV2 or an error from the SR2 register.
*
Enable
Control from
Bit
Exit
Exit
from
Halt
Event
Flag
Interrupt Event
Wait
Yes
Yes
Yes
End of Byte Transfer Event
BTF
SB
No
No
No
Start Bit Generation Event (Master mode)
Acknowledge Failure Event
ITE
AF
2
Note: The I C interrupt events are connected to
the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding
Enable Control Bit is set and the I-bits in the CC
register are reset (RIM instruction).
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I²C SINGLE MASTER BUS INTERFACE (Cont’d)
11.7.7 Register Description
– In master mode:
0: No start generation
1: Repeated start generation
2
I C CONTROL REGISTER (CR)
Read / Write
Reset Value: 0000 0000 (00h)
– In idle mode:
0: No start generation
1: Start generation when the bus is free
7
0
0
0
PE
0
START ACK STOP
ITE
Bit 2 = ACK Acknowledge enable.
This bit is set and cleared by software. It is also
cleared by hardware when the interface is disa-
bled (PE=0).
Bit 7:6 = Reserved. Forced to 0 by hardware.
0: No acknowledge returned
1: Acknowledge returned after a data byte is re-
ceived
Bit 5 = PE Peripheral enable.
This bit is set and cleared by software.
0: Peripheral disabled
1: Master capability
Bit 1 = STOP Generation of a Stop condition.
This bit is set and cleared by software. It is also
cleared by hardware when the interface is disa-
bled (PE=0) or when the Stop condition is sent.
Notes:
– When PE=0, all the bits of the CR register and
the SR register except the Stop bit are reset. All
outputs are released while PE=0
– In Master mode only:
0: No stop generation
1: Stop generation after the current byte transfer
or after the current Start condition is sent.
– When PE=1, the corresponding I/O pins are se-
lected by hardware as alternate functions.
2
– To enable the I C interface, write the CR register
TWICE with PE=1 as the first write only activates
the interface (only PE is set).
Bit 0 = ITE Interrupt enable.
This bit is set and cleared by software and cleared
by hardware when the interface is disabled
(PE=0).
Bit 4 = Reserved. Forced to 0 by hardware.
Bit 3 = START Generation of a Start condition.
This bit is set and cleared by software. It is also
cleared by hardware when the interface is disa-
bled (PE=0) or when the Start condition is sent
(with interrupt generation if ITE=1).
0: Interrupts disabled
1: Interrupts enabled
Refer to Figure 4 for the relationship between the
events and the interrupt.
SCL is held low when the SB or BTF flags or an
EV2 event (See Figure 68) is detected.
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I²C SINGLE MASTER BUS INTERFACE (Cont’d)
2
I C STATUS REGISTER 1 (SR1)
SR1 register followed by a read or write of DR reg-
ister. It is also cleared by hardware when the inter-
face is disabled (PE=0).
Read Only
Reset Value: 0000 0000 (00h)
– Following a byte transmission, this bit is set after
reception of the acknowledge clock pulse. In
case an address byte is sent, this bit is set only
after the EV2 event (See Figure 68). BTF is
cleared by reading SR1 register followed by writ-
ing the next byte in DR register.
7
0
EVF
0
TRA
0
BTF
0
M/IDL
SB
Bit 7 = EVF Event flag.
– Following a byte reception, this bit is set after
transmission of the acknowledge clock pulse if
ACK=1. BTF is cleared by reading SR1 register
followed by reading the byte from DR register.
This bit is set by hardware as soon as an event oc-
curs. It is cleared by software reading SR2 register
in case of error event or as described in Figure 68.
It is also cleared by hardware when the interface is
disabled (PE=0).
0: No event
1: One of the following events has occurred:
The SCL line is held low while BTF=1.
0: Byte transfer not done
1: Byte transfer succeeded
– BTF=1 (Byte received or transmitted)
– SB=1 (Start condition generated)
Bit 2 = Reserved. Forced to 0 by hardware.
– AF=1 (No acknowledge received after byte
transmission if ACK=1)
Bit 1 = M/IDL Master/Idle.
– Address byte successfully transmitted.
This bit is set by hardware as soon as the interface
is in Master mode (writing START=1). It is cleared
by hardware after generating a Stop condition on
the bus. It is also cleared when the interface is dis-
abled (PE=0).
0: Idle mode
1: Master mode
Bit 6 = Reserved. Forced to 0 by hardware.
Bit 5 = TRA Transmitter/Receiver.
When BTF is set, TRA=1 if a data byte has been
transmitted. It is cleared automatically when BTF
is cleared. It is also cleared by hardware when the
interface is disabled (PE=0).
0: Data byte received (if BTF=1)
1: Data byte transmitted
Bit 0 = SB Start bit generated.
This bit is set by hardware as soon as the Start
condition is generated (following
a
write
START=1). An interrupt is generated if ITE=1. It is
cleared by software reading SR1 register followed
by writing the address byte in DR register. It is also
cleared by hardware when the interface is disa-
bled (PE=0).
0: No Start condition
1: Start condition generated
Bit 4 = Reserved. Forced to 0 by hardware.
Bit 3 = BTF Byte transfer finished.
This bit is set by hardware as soon as a byte is cor-
rectly received or transmitted with interrupt gener-
ation if ITE=1. It is cleared by software reading
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ST7265x
I²C SINGLE MASTER BUS INTERFACE (Cont’d)
2
I C STATUS REGISTER 2 (SR2)
Bit 4 = AF Acknowledge failure.
Read Only
Reset Value: 0000 0000 (00h)
This bit is set by hardware when no acknowledge
is returned. An interrupt is generated if ITE=1. It is
cleared by software reading SR2 register or by
hardware when the interface is disabled (PE=0).
7
0
0
0
The SCL line is not held low while AF=1.
0
0
AF
0
0
0
0: No acknowledge failure
1: Acknowledge failure
Bit 7:5 = Reserved. Forced to 0 by hardware.
Bit 3:0 = Reserved. Forced to 0 by hardware.
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I²C SINGLE MASTER BUS INTERFACE (Cont’d)
2
2
I C CLOCK CONTROL REGISTER (CCR)
I C DATA REGISTER (DR)
Read / Write
Reset Value: 0000 0000 (00h)
Read / Write
Reset Value: 0000 0000 (00h)
7
0
7
0
FM/SM CC6
CC5
CC4
CC3
CC2
CC1
CC0
D7
D6
D5
D4
D3
D2
D1
D0
2
Bit 7 = FM/SM Fast/Standard I C mode.
This bit is set and cleared by software. It is not
Bit 7:0 = D7-D0 8-bit Data Register.
These bits contains the byte to be received or
transmitted on the bus.
cleared when the interface is disabled (PE=0).
2
0: Standard I C mode
2
1: Fast I C mode
– Transmitter mode: Byte transmission start auto-
matically when the software writes in the DR reg-
ister.
Bit 6:0 = CC6-CC0 7-bit clock divider.
These bits select the speed of the bus (F
pending on the I C mode. They are not cleared
when the interface is disabled (PE=0).
) de-
SCL
– Receiver mode: the first data byte is received au-
tomatically in the DR register using the least sig-
nificant bit of the address.
2
– Standard mode (FM/SM=0): F
<= 100kHz
Then, the next data bytes are received one by
one after reading the DR register.
SCL
F
= F
/(2x([CC6..CC0]+2))
CPU
SCL
– Fast mode (FM/SM=1): F
> 100kHz
SCL
F
= F
/(3x([CC6..CC0]+2))
CPU
SCL
Note: The programmed F
SCL and SDA lines.
assumes no load on
SCL
2
Table 34. I C Register Map
Address
(Hex.)
Register
Name
7
6
5
4
3
2
1
0
CR
PE
0
START
ACK
0
STOP
ITE
0
40
41
42
43
46
Reset Value
SR1
0
0
0
0
BTF
0
0
M/IDL
0
EVF
0
TRA
0
SB
0
Reset Value
SR2
0
0
AF
0
0
Reset Value
CCR
0
FM/SM
0
0
CC6
0
0
CC5
0
0
CC3
0
0
CC2
0
0
CC1
0
0
CC0
0
CC4
0
Reset Value
DR
DR7
0
DR6
0
DR5
0
DR4
0
DR3
0
DR2
0
DR1
0
DR0
0
Reset Value
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11.8 8-BIT A/D CONVERTER (ADC)
11.8.1 Introduction
11.8.3 Functional Description
11.8.3.1 Analog Power Supply
The on-chip Analog to Digital Converter (ADC) pe-
ripheral is a 8-bit, successive approximation con-
verter with internal sample and hold circuitry. This
peripheral has up to 16 multiplexed analog input
channels (refer to device pin out description) that
allow the peripheral to convert the analog voltage
levels from up to 16 different sources.
V
and V
are the high and low level refer-
SSA
DDA
ence voltage pins. In some devices (refer to device
pin out description) they are internally connected
to the V and V pins.
DD
SS
Conversion accuracy may therefore be impacted
by voltage drops and noise in the event of heavily
loaded or badly decoupled power supply lines.
The result of the conversion is stored in a 8-bit
Data Register. The A/D converter is controlled
through a Control/Status Register.
See electrical characteristics section for more de-
tails.
11.8.2 Main Features
■ 8-bit conversion
■ Up to 16 channels with multiplexed input
■ Linear successive approximation
■ Data register (DR) which contains the results
■ Conversion complete status flag
■ On/off bit (to reduce consumption)
The block diagram is shown in Figure 70.
Figure 70. ADC Block Diagram
f
f
ADC
CPU
DIV 4
COCO
0
ADON
4
0
CH3 CH2 CH1 CH0
ADCCSR
AIN0
AIN1
HOLD CONTROL
R
ADC
ANALOG TO DIGITAL
CONVERTER
ANALOG
MUX
AINx
C
ADC
ADCDR
D7
D6
D5
D4
D3
D2
D1
D0
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8-BIT A/D CONVERTER (ADC) (Cont’d)
11.8.3.2 Digital A/D Conversion Result
The analog input ports must be configured as in-
put, no pull-up, no interrupt. Refer to the «I/O
ports» chapter. Using these pins as analog inputs
does not affect the ability of the port to be read as
a logic input.
The conversion is monotonic, meaning that the re-
sult never decreases if the analog input does not
and never increases if the analog input does not.
If the input voltage (V ) is greater than or equal
AIN
In the CSR register:
to V
(high-level voltage reference) then the
DDA
conversion result in the DR register is FFh (full
– Select the CH[3:0] bits to assign the analog
channel to be converted.
scale) without overflow indication.
If input voltage (V ) is lower than or equal to
ADC Conversion
AIN
V
(low-level voltage reference) then the con-
SSA
In the CSR register:
version result in the DR register is 00h.
– Set the ADON bit to enable the A/D converter
and to start the first conversion. From this time
on, the ADC performs a continuous conver-
sion of the selected channel.
The A/D converter is linear and the digital result of
the conversion is stored in the ADCDR register.
The accuracy of the conversion is described in the
parametric section.
When a conversion is complete
R
is the maximum recommended impedance
– The COCO bit is set by hardware.
– No interrupt is generated.
– The result is in the DR register and remains
valid until the next conversion has ended.
AIN
for an analog input signal. If the impedance is too
high, this will result in a loss of accuracy due to
leakage and sampling not being completed in the
alloted time.
A write to the CSR register (with ADON set) aborts
the current conversion, resets the COCO bit and
starts a new conversion.
11.8.3.3 A/D Conversion Phases
The A/D conversion is based on two conversion
phases as shown in Figure 71:
■ Sample capacitor loading [duration: t
Figure 71. ADC Conversion Timings
]
LOAD
During this phase, the V
measured is loaded into the C
input voltage to be
AIN
ADON
sample
ADC
ADCCSR WRITE
OPERATION
t
CONV
capacitor.
■ A/D conversion [duration: t
]
CONV
During this phase, the A/D conversion is
computed (8 successive approximation cycles)
HOLD
CONTROL
and the C
sample capacitor is disconnected
ADC
from the analog input pin to get the optimum
t
LOAD
COCO BIT SET
analog to digital conversion accuracy.
While the ADC is on, these two phases are contin-
uously repeated.
11.8.4 Low Power Modes
At the end of each conversion, the sample capaci-
tor is kept loaded with the previous measurement
load. The advantage of this behaviour is that it
minimizes the current consumption on the analog
pin in case of single input channel measurement.
Mode
WAIT
Description
No effect on A/D Converter
A/D Converter disabled.
After wakeup from Halt mode, the A/D Con-
verter requires a stabilisation time before ac-
curate conversions can be performed.
HALT
11.8.3.4 Software Procedure
Refer to the control/status register (CSR) and data
register (DR) in Section 11.8.6 for the bit defini-
tions and to Figure 71 for the timings.
Note: The A/D converter may be disabled by reset-
ting the ADON bit. This feature allows reduced
power consumption when no conversion is needed
and between single shot conversions.
ADC Configuration
The total duration of the A/D conversion is 12 ADC
11.8.5 Interrupts
clock periods (1/f
=4/f
).
ADC
CPU
None
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8-BIT A/D CONVERTER (ADC) (Cont’d)
11.8.6 Register Description
CONTROL/STATUS REGISTER (CSR)
Read/Write
DATA REGISTER (DR)
Read Only
Reset Value: 0000 0000 (00h)
Reset Value: 0000 0000 (00h)
7
0
7
0
COCO
0
ADON
0
CH3
CH2
CH1
CH0
D7
D6
D5
D4
D3
D2
D1
D0
Bit 7 = COCO Conversion Complete
This bit is set by hardware. It is cleared by soft-
ware reading the result in the DR register or writing
to the CSR register.
0: Conversion is not complete
1: Conversion can be read from the DR register
Bits 7:0 = D[7:0] Analog Converted Value
This register contains the converted analog value
in the range 00h to FFh.
Note: Reading this register reset the COCO flag.
Bit 6 = Reserved. must always be cleared.
Bit 5 = ADON A/D Converter On
This bit is set and cleared by software.
0: A/D converter is switched off
1: A/D converter is switched on
Bit 4 = Reserved. must always be cleared.
Bits 3:0 = CH[3:0] Channel Selection
These bits are set and cleared by software. They
select the analog input to convert.
Channel Pin*
CH3 CH2 CH1 CH0
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
AIN9
AIN10
AIN11
AIN12
AIN13
AIN14
AIN15
*Note: The number of pins AND the channel selec-
tion varies according to the device. Refer to the de-
vice pinout.
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8-BIT A/D CONVERTER (ADC) (Cont’d)
Table 35. ADC Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
ADCDR
Reset Value
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
0012h
0013h
ADCCSR
Reset Value
COCO
0
ADON
0
CH3
0
CH2
0
CH1
0
CH0
0
0
0
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12 INSTRUCTION SET
12.1 CPU ADDRESSING MODES
so, most of the addressing modes may be subdi-
vided in two sub-modes called long and short:
The CPU features 17 different addressing modes
which can be classified in 7 main groups:
– Long addressing mode is more powerful be-
cause it can use the full 64 Kbyte address space,
however it uses more bytes and more CPU cy-
cles.
Addressing Mode
Inherent
Example
nop
– Short addressing mode is less powerful because
it can generally only access page zero (0000h -
00FFh range), but the instruction size is more
compact, and faster. All memory to memory in-
structions use short addressing modes only
(CLR, CPL, NEG, BSET, BRES, BTJT, BTJF,
INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP)
Immediate
Direct
ld A,#$55
ld A,$55
ld A,($55,X)
ld A,([$55],X)
jrne loop
Indexed
Indirect
Relative
Bit operation
bset byte,#5
The ST7 Assembler optimizes the use of long and
short addressing modes.
The CPU Instruction set is designed to minimize
the number of bytes required per instruction: To do
Table 36. CPU Addressing Mode Overview
Pointer
Address
(Hex.)
Pointer Size
(Hex.)
Length
(Bytes)
Mode
Syntax
Destination
Inherent
Immediate
Short
Long
nop
+ 0
ld A,#$55
+ 1
+ 1
+ 2
+ 0
+ 1
+ 2
+ 2
+ 2
+ 2
+ 2
+ 1
+ 2
+ 1
+ 2
+ 2
+ 3
Direct
ld A,$10
00..FF
Direct
ld A,$1000
ld A,(X)
0000..FFFF
00..FF
No Offset
Short
Long
Direct
Indexed
Indexed
Indexed
Direct
ld A,($10,X)
ld A,($1000,X)
ld A,[$10]
00..1FE
0000..FFFF
00..FF
Direct
Short
Long
Indirect
Indirect
Indirect
Indirect
Direct
00..FF
00..FF
00..FF
00..FF
byte
word
byte
word
ld A,[$10.w]
ld A,([$10],X)
ld A,([$10.w],X)
jrne loop
0000..FFFF
00..1FE
0000..FFFF
PC+/-127
PC+/-127
00..FF
Short
Long
Indexed
Indexed
Relative
Relative
Bit
Indirect
Direct
jrne [$10]
00..FF
00..FF
00..FF
byte
byte
byte
bset $10,#7
bset [$10],#7
Bit
Indirect
Direct
00..FF
Bit
Relative btjt $10,#7,skip
Relative btjt [$10],#7,skip
00..FF
Bit
Indirect
00..FF
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INSTRUCTION SET OVERVIEW (Cont’d)
12.1.1 Inherent
12.1.3 Direct
All Inherent instructions consist of a single byte.
The opcode fully specifies all the required informa-
tion for the CPU to process the operation.
In Direct instructions, the operands are referenced
by their memory address.
The direct addressing mode consists of two sub-
modes:
Inherent Instruction
Function
No operation
Direct (short)
NOP
The address is a byte, thus requires only one byte
after the opcode, but only allows 00 - FF address-
ing space.
TRAP
S/W Interrupt
Wait For Interrupt (Low Pow-
er Mode)
WFI
Direct (long)
Halt Oscillator (Lowest Power
Mode)
HALT
The address is a word, thus allowing 64 Kbyte ad-
dressing space, but requires 2 bytes after the op-
code.
RET
Sub-routine Return
Interrupt Sub-routine Return
Set Interrupt Mask (level 3)
Reset Interrupt Mask (level 0)
Set Carry Flag
IRET
SIM
12.1.4 Indexed (No Offset, Short, Long)
RIM
In this mode, the operand is referenced by its
memory address, which is defined by the unsigned
addition of an index register (X or Y) with an offset.
SCF
RCF
Reset Carry Flag
RSP
Reset Stack Pointer
Load
The indirect addressing mode consists of three
sub-modes:
LD
CLR
Clear
Indexed (No Offset)
PUSH/POP
INC/DEC
TNZ
Push/Pop to/from the stack
Increment/Decrement
Test Negative or Zero
1 or 2 Complement
Byte Multiplication
There is no offset, (no extra byte after the opcode),
and allows 00 - FF addressing space.
Indexed (Short)
CPL, NEG
MUL
The offset is a byte, thus requires only one byte af-
ter the opcode and allows 00 - 1FE addressing
space.
SLL, SRL, SRA, RLC,
RRC
Shift and Rotate Operations
Swap Nibbles
Indexed (long)
SWAP
The offset is a word, thus allowing 64 Kbyte ad-
dressing space and requires 2 bytes after the op-
code.
12.1.2 Immediate
Immediate instructions have two bytes, the first
byte contains the opcode, the second byte con-
tains the operand value.
12.1.5 Indirect (Short, Long)
The required data byte to do the operation is found
by its memory address, located in memory (point-
er).
Immediate Instruction
Function
LD
Load
The pointer address follows the opcode. The indi-
rect addressing mode consists of two sub-modes:
CP
Compare
BCP
Bit Compare
Indirect (short)
AND, OR, XOR
ADC, ADD, SUB, SBC
Logical Operations
Arithmetic Operations
The pointer address is a byte, the pointer size is a
byte, thus allowing 00 - FF addressing space, and
requires 1 byte after the opcode.
Indirect (long)
The pointer address is a byte, the pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.
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ST7265x
INSTRUCTION SET OVERVIEW (Cont’d)
12.1.6 Indirect Indexed (Short, Long)
12.1.7 Relative mode (Direct, Indirect)
This is a combination of indirect and short indexed
addressing modes. The operand is referenced by
its memory address, which is defined by the un-
signed addition of an index register value (X or Y)
with a pointer value located in memory. The point-
er address follows the opcode.
This addressing mode is used to modify the PC
register value, by adding an 8-bit signed offset to
it.
Available Relative
Direct/Indirect
Instructions
Function
The indirect indexed addressing mode consists of
two sub-modes:
JRxx
CALLR
Conditional Jump
Call Relative
Indirect Indexed (Short)
The pointer address is a byte, the pointer size is a
byte, thus allowing 00 - 1FE addressing space,
and requires 1 byte after the opcode.
The relative addressing mode consists of two sub-
modes:
Relative (Direct)
Indirect Indexed (Long)
The offset is following the opcode.
Relative (Indirect)
The pointer address is a byte, the pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.
The offset is defined in memory, which address
follows the opcode.
Table 37. Instructions Supporting Direct,
Indexed, Indirect and Indirect Indexed
Addressing Modes
Long and Short
Function
Instructions
LD
Load
CP
Compare
AND, OR, XOR
Logical Operations
Arithmetic Additions/Sub-
stractions operations
ADC, ADD, SUB, SBC
BCP
Bit Compare
Short Instructions
Only
Function
CLR
Clear
INC, DEC
TNZ
Increment/Decrement
Test Negative or Zero
1 or 2 Complement
Bit Operations
CPL, NEG
BSET, BRES
Bit Test and Jump Opera-
tions
BTJT, BTJF
SLL, SRL, SRA, RLC,
RRC
Shift and Rotate Opera-
tions
SWAP
Swap Nibbles
CALL, JP
Call or Jump subroutine
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INSTRUCTION SET OVERVIEW (Cont’d)
12.2 INSTRUCTION GROUPS
The ST7 family devices use an Instruction Set
consisting of 63 instructions. The instructions may
be subdivided into 13 main groups as illustrated in
the following table:
Load and Transfer
LD
CLR
POP
DEC
TNZ
OR
Stack operation
PUSH
INC
RSP
BCP
Increment/Decrement
Compare and Tests
Logical operations
CP
AND
BSET
BTJT
ADC
SLL
XOR
CPL
NEG
Bit Operation
BRES
BTJF
ADD
SRL
JRT
Conditional Bit Test and Branch
Arithmetic operations
Shift and Rotates
SUB
SRA
JRF
SBC
RLC
JP
MUL
RRC
CALL
SWAP
CALLR
SLA
Unconditional Jump or Call
Conditional Branch
JRA
JRxx
TRAP
SIM
NOP
RET
Interruption management
Condition Code Flag modification
WFI
RIM
HALT
SCF
IRET
RCF
Using a pre-byte
The instructions are described with one to four op-
codes.
These prebytes enable instruction in Y as well as
indirect addressing modes to be implemented.
They precede the opcode of the instruction in X or
the instruction using direct addressing mode. The
prebytes are:
In order to extend the number of available op-
codes for an 8-bit CPU (256 opcodes), three differ-
ent prebyte opcodes are defined. These prebytes
modify the meaning of the instruction they pre-
cede.
PDY 90
Replace an X based instruction
using immediate, direct, indexed, or inherent ad-
dressing mode by a Y one.
The whole instruction becomes:
PIX 92
Replace an instruction using di-
PC-2
PC-1
PC
End of previous instruction
Prebyte
rect, direct bit, or direct relative addressing mode
to an instruction using the corresponding indirect
addressing mode.
opcode
It also changes an instruction using X indexed ad-
dressing mode to an instruction using indirect X in-
dexed addressing mode.
PC+1
Additional word (0 to 2) according
to the number of bytes required to compute the ef-
fective address
PIY 91
Replace an instruction using X in-
direct indexed addressing mode by a Y one.
125/166
ST7265x
INSTRUCTION SET OVERVIEW (Cont’d)
Mnemo
ADC
ADD
AND
BCP
Description
Add with Carry
Function/Example
A = A + M + C
A = A + M
Dst
Src
I1
H
H
H
I0
N
N
N
N
N
Z
Z
Z
Z
Z
C
C
C
A
M
M
M
M
Addition
A
Logical And
A = A . M
A
Bit compare A, Memory
Bit Reset
tst (A . M)
A
BRES
BSET
BTJF
BTJT
CALL
CALLR
CLR
bres Byte, #3
bset Byte, #3
btjf Byte, #3, Jmp1
btjt Byte, #3, Jmp1
M
M
M
M
Bit Set
Jump if bit is false (0)
Jump if bit is true (1)
Call subroutine
Call subroutine relative
Clear
C
C
reg, M
reg
0
N
N
N
1
Z
Z
Z
CP
Arithmetic Compare
One Complement
Decrement
tst(Reg - M)
A = FFH-A
dec Y
M
C
1
CPL
reg, M
reg, M
DEC
HALT
IRET
INC
Halt
1
0
Interrupt routine return
Increment
Pop CC, A, X, PC
inc X
I1
H
I0
N
N
Z
Z
C
reg, M
JP
Absolute Jump
Jump relative always
Jump relative
Never jump
jp [TBL.w]
JRA
JRT
JRF
jrf *
JRIH
JRIL
Jump if Port B INT pin = 1 (no Port B Interrupts)
Jump if Port B INT pin = 0 (Port B interrupt)
JRH
Jump if H = 1
H = 1 ?
JRNH
JRM
Jump if H = 0
H = 0 ?
Jump if I1:0 = 11
Jump if I1:0 <> 11
Jump if N = 1 (minus)
Jump if N = 0 (plus)
Jump if Z = 1 (equal)
I1:0 = 11 ?
I1:0 <> 11 ?
N = 1 ?
JRNM
JRMI
JRPL
JREQ
JRNE
JRC
N = 0 ?
Z = 1 ?
Jump if Z = 0 (not equal) Z = 0 ?
Jump if C = 1
Jump if C = 0
Jump if C = 1
C = 1 ?
JRNC
JRULT
C = 0 ?
Unsigned <
Jmp if unsigned >=
Unsigned >
JRUGE Jump if C = 0
JRUGT Jump if (C + Z = 0)
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ST7265x
INSTRUCTION SET OVERVIEW (Cont’d)
Mnemo
JRULE
LD
Description
Jump if (C + Z = 1)
Load
Function/Example
Unsigned <=
dst <= src
Dst
Src
I1
H
I0
N
N
N
N
N
Z
Z
Z
Z
Z
C
reg, M
A, X, Y
reg, M
M, reg
X, Y, A
MUL
NEG
NOP
OR
Multiply
X,A = X * A
neg $10
0
0
Negate (2's compl)
No Operation
OR operation
C
A = A + M
pop reg
pop CC
push Y
C = 0
A
M
reg
CC
M
M
POP
Pop from the Stack
M
I1
1
H
I0
0
C
0
PUSH
RCF
RET
RIM
Push onto the Stack
Reset carry flag
Subroutine Return
Enable Interrupts
Rotate left true C
Rotate right true C
Reset Stack Pointer
Substract with Carry
Set carry flag
reg, CC
I1:0 = 10 (level 0)
C <= A <= C
C => A => C
S = Max allowed
A = A - M - C
C = 1
RLC
RRC
RSP
SBC
SCF
SIM
reg, M
reg, M
N
N
Z
Z
C
C
A
M
N
Z
C
1
Disable Interrupts
Shift left Arithmetic
Shift left Logic
I1:0 = 11 (level 3)
C <= A <= 0
C <= A <= 0
0 => A => C
A7 => A => C
A = A - M
1
1
SLA
reg, M
reg, M
reg, M
reg, M
A
N
N
0
Z
Z
Z
Z
Z
Z
Z
C
C
C
C
C
SLL
SRL
SRA
SUB
SWAP
TNZ
TRAP
WFI
Shift right Logic
Shift right Arithmetic
Substraction
N
N
N
N
M
M
SWAP nibbles
A7-A4 <=> A3-A0
tnz lbl1
reg, M
Test for Neg & Zero
S/W trap
S/W interrupt
1
1
1
0
Wait for Interrupt
Exclusive OR
XOR
A = A XOR M
A
N
Z
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ST7265x
13 ELECTRICAL CHARACTERISTICS
13.1 PARAMETER CONDITIONS
Unless otherwise specified, all voltages are re-
13.1.5 Pin input Voltage
ferred to V
.
SS
The input voltage measurement on a pin of the de-
vice is described in Figure 73.
13.1.1 Minimum and Maximum Values
Unless otherwise specified the minimum and max-
imum values are guaranteed in the worst condi-
tions of ambient temperature, supply voltage and
frequencies by tests in production on 100% of the
Figure 73. Pin input Voltage
devices with an ambient temperature at T =25°C
A
ST7 PIN
and T =T max (given by the selected temperature
A
A
range).
V
Data based on characterization results, design
simulation and/or technology characteristics are
indicated in the table footnotes and are not tested
in production. Based on characterization, the min-
imum and maximum values refer to sample tests
and represent the mean value plus or minus three
times the standard deviation (mean±3Σ).
IN
13.1.2 Typical Values
Unless otherwise specified, typical data are based
on T =25°C, V =5V (for the 4.5V≤V ≤5.5V
A
DD
DD
voltage range) and V =3.3V (for the 3V≤V ≤4V
DD
DD
voltage range). They are given only as design
guidelines and are not tested.
13.1.3 Typical Curves
Unless otherwise specified, all typical curves are
given only as design guidelines and are not tested.
13.1.4 Loading Capacitor
The loading conditions used for pin parameter
measurement is shown in Figure 72.
Figure 72. Pin Loading Conditions
ST7 PIN
C
L
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ST7265x
13.2 ABSOLUTE MAXIMUM RATINGS
Stresses above those listed as “absolute maxi-
mum ratings” may cause permanent damage to
the device. This is a stress rating only and func-
tional operation of the device under these condi-
tions is not implied. Exposure to maximum rating
conditions for extended periods may affect device
reliability.
13.2.1 Voltage Characteristics
Symbol
- V
Ratings
Maximum value
6.0
Unit
V
Supply voltage
DD
SS
1) & 2)
V
Input voltage on any pin
VSS-0.3 to VDD+0.3
1500
V
IN
V
Electro-static discharge voltage (Human Body Model)
ESD(HBM)
13.2.2 Current Characteristics
Symbol
Ratings
Maximum value
Unit
3)
3)
I
Total current into V power lines (source)
100
80
VDD
DD
I
Total current out of V ground lines (sink)
SS
VSS
Output current sunk by any standard I/O and control pin
Output current sunk by any high sink I/O pin
Output current source by any I/Os and control pin
Injected current on VPP pin
25
I
50
IO
- 25
± 5
± 5
± 5
± 5
± 20
mA
Injected current on RESET pin
2) & 4)
I
INJ(PIN)
Injected current on OSC1 and OSC2 pins
5) & 6)
Injected current on any other pin
2)
5)
ΣI
Total injected current (sum of all I/O and control pins)
INJ(PIN)
13.2.3 Thermal Characteristics
Symbol
Ratings
Value
-65 to +150
TBD
Unit
°C
T
Storage temperature range
Maximum junction temperature
STG
T
°C
J
Notes:
1. Directly connecting the RESET and I/O pins to V or V could damage the device if an unintentional internal reset
DD
SS
is generated or an unexpected change of the I/O configuration occurs (for example, due to a corrupted program counter).
To guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7kΩ for
RESET, 10kΩ for I/Os). Unused I/O pins must be tied in the same way to V or V according to their reset configuration.
DD
SS
2. When the current limitation is not possible, the V absolute maximum rating must be respected, otherwise refer to
IN
I
specification. A positive injection is induced by V >V while a negative injection is induced by V <V
.
INJ(PIN)
IN
DD
IN
SS
3. All power (V ) and ground (V ) lines must always be connected to the external supply.
DD
SS
4. Negative injection disturbs the analog performance of the device. In particular, it induces leakage currents throughout
the device including the analog inputs. To avoid undesirable effects on the analog functions, care must be taken:
- Analog input pins must have a negative injection less than 0.8 mA (assuming that the impedance of the analog voltage
is lower than the specified limits)
- Pure digital pins must have a negative injection less than 1.6mA. In addition, it is recommended to inject the current as
far as possible from the analog input pins.
5. When several inputs are submitted to a current injection, the maximum ΣI
is the absolute sum of the positive
INJ(PIN)
and negative injected currents (instantaneous values). These results are based on characterisation with ΣI
maxi-
INJ(PIN)
mum current injection on four I/O port pins of the device.
6. True open drain I/O port pins do not accept positive injection.
129/166
ST7265x
13.3 OPERATING CONDITIONS
13.3.1 General Operating Conditions
Symbol
Parameter
Conditions
see Figure 74
Min
Max
Unit
Supply voltage with USB peripheral ena-
bled
4.0
5.5
V
Supply voltage with USB peripheral disa-
bled and LVD off (ROM version)
V
see Figure 74
see Figure 74
2.7
3.0
5.5
5.5
V
V
DD
Supply voltage with USB peripheral disa-
bled and LVD off (FLASH version)
f
External clock frequency
12
0
12
70
MHz
°C
OSC
T
Ambient temperature range
A
1)
Figure 74. f
Maximum Operating Frequency Versus VDD Supply Voltage
OSC
f
[MHz]
CPU
FUNCTIONALITY
GUARANTEED
IN THIS AREA
2)
8
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
FUNCTIONALITY
GUARANTEED
IN THIS AREA
EXCEPT USB CELL
4
3
2
3)
SUPPLY VOLTAGE [V]
0
2.7
2.0
2.5
3.0
3.5
4.0
4.55
5.0
5.5
See note 4
Notes:
A/D operation not guaranteed below 1MHz.
1. Operating conditions with T =0 to +70°C.
A
2. This mode is supported by all devices.
3. This mode is only supported by ST72(F)651AR6T1E ROM and Flash devices (without LVD)
4. The 2.7V-3.0V voltage range is only supported by ST72651AR6T1E ROM devices (without LVD)
130/166
ST7265x
OPERATING CONDITIONS (Cont’d)
13.3.2 Operating Conditions with Low Voltage Detector (LVD)
Subject to general operating conditions for V , f
, and T .
A
DD OSC
1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Reset release threshold
V
2.9
3.5
3.8
IT+
IT-
(V rise)
DD
V
Reset generation threshold
V
V
2.6
3.1
3.5
(V fall)
DD
LVD voltage threshold hysteresis
V
-V
150
300
10
mV
MHz.
ms
hys
IT+ IT-
2)
f
LVD filter cut-off frequency
Not detected by the LVD
CUTOFF
3)
Vt
V
rise time
0.3
10
POR
DD
Notes:
1. LVD typical data are based on T =25°C. They are given only as design guidelines and are not tested.
A
2. Not tested, guaranteed by construction.
3. The V rise time condition is needed to insure a correct device power-on and LVD reset. Not tested in production.
DD
13.3.3 Power Supply Manager Characteristics
Subject to general operating conditions for V , f
suffix).
, and T . Not guaranteed on LVD devices (without E
A
DD OSC
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Reset release threshold
USBV
3.50
3.80
4.00
IT+
(V rise)
DD
V
Reset generation threshold
USBV
USBV
3.30
100
3.65
200
3.80
300
IT-
(V fall)
DD
USB voltage threshold hysteresis
USBV -USBV
mV
V
hys
IT+
IT-
Minimum voltage required for stable
48MHz PLL operation (PLL locked)
1)
V
3.7
PLLmin48
Minimum voltage required for
40MHz PLL operation (PLL un-
locked)
1)
1)
V
3.4
V
V
PLLmin40
PLLmin24
Minimum voltage required for
24MHz PLL operation (PLL un-
locked)
V
3.0
1. Not tested, guaranteed by construction.
13.3.4 Storage Device Supply Characteristics
Subject to general operating conditions for V , f
, and T .
A
DD OSC
Symbol
Parameter
Conditions
Min
2.5
2.9
3.0
3.1
Typ
2.8
3.3
3.4
3.5
Max
3.2
3.6
3.8
3.9
Unit
USB Mode: VSET[1:0]=11
10
01
00
Voltage output for external storage
V
V
DDF
device (I
max = 50mA)
load
Note: In Stand-alone mode V
must be connected to V
DD
DDF
131/166
ST7265x
13.4 SUPPLY CURRENT CHARACTERISTICS
The following current consumption specified for
the ST7 functional operating modes over tempera-
ture range does not take into account the clock
source current consumption. To get the total de-
vice consumption, the two current values must be
added (except for HALT mode for which the clock
is stopped).
13.4.1 RUN Mode
1)
2)
Symbol
Parameter
Conditions
Typ
Max
Unit
3)
3)
Supply current in RUN mode
(see Figure 75)
f
f
=8MHz
14
20
CPU
I
mA
DD
Supply current in RUN mode
(see Figure 75)
=3MHz
4
8
CPU
Figure 75. Typical I in RUN vs. f
DD
CPU
20
18
16
14
12
10
8
6
8 MHz
4
6 MHz
3 MHz
2
0
2
3
4
5
6
7
Vdd (V)
Notes:
1. Typical data are based on T =25°C, V =5V (4.0V≤V ≤5.5V range) and V =3.3V (2.7V≤V ≤4.0V range).
A
DD
DD
DD
DD
2. Data based on characterization results, tested in production at V =5.5V. and f
= 8MHz
CPU
DD
3. CPU running with memory access, all I/O pins in input mode with a static value at V or V (no load), all peripherals
DD
SS
in reset state; clock input (OSC1) driven by external square wave, LVD disabled.
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ST7265x
SUPPLY CURRENT CHARACTERISTICS (Cont’d)
13.4.2 WAIT Mode
1)
2)
Symbol
Parameter
Conditions
Typ
Max
Unit
3)
3)
Supply current in WAIT mode
(see Figure 76)
f
f
=8MHz
8
11
CPU
I
mA
WFI
Supply current in WAIT mode
(see Figure 76)
=3MHz
3
6
CPU
Figure 76. Typical I in WAIT vs. f
DD
CPU
12
10
8
6
4
8 MHz
6 MHz
3 MHz
2
0
2
3
4
5
6
7
Vdd (V)
Notes:
1. Typical data are based on T =25°C, V =5V (4V≤V ≤5.5V range) and V =3.3V (2.7V≤V ≤4.0V range).
A
DD
DD
DD
DD
2. Data based on characterization results, tested in production at V = 5.5V and f
= 8MHz.
CPU
DD
3. All I/O pins in input mode with a static value at V or V (no load), all peripherals in reset state; clock input (OSC1)
DD
SS
driven by external square wave, LVD disabled.
133/166
ST7265x
SUPPLY CURRENT CHARACTERISTICS (Cont’d)
13.4.3 HALT Mode
1)
Symbol
Parameter
Conditions
Typ
3
Max
TBD
TBD
TBD
TBD
Unit
V
V
V
V
=5.5V
=3.0V
=5.5V
=3.0V
DD
DD
DD
DD
LVD OFF
LVD ON
1
2)
I
Supply current in HALT mode
µA
HALT
110
60
Notes:
1. Typical data are based on T =25°C.
A
2. All I/O pins in input mode with a static value at V or V (no load).
DD
SS
13.4.4 SUSPEND Mode
Symbol
1)
3)
Parameter
Conditions
Typ
Max
230
300
Unit
2)
I
Supply current in SUSPEND mode
LVD OFF
LVD ON
V
V
=4-5.25V
=4-5.25V
150
230
µA
SUSP
DD
DD
Notes:
1. Typical data are based on T =25°C.
A
2. External pull-up (1.5kΩ connected to USBV ) and pull-down (15kΩ connected to USBV ) current not included.
CC
SS
3. T =25°C
A
134/166
ST7265x
13.5 CLOCK AND TIMING CHARACTERISTICS
Subject to general operating conditions for V , f
, and T .
DD OSC
A
13.5.1 General Timings
1)
Symbol
Parameter
Conditions
Min
2
Typ
Max
12
Unit
tCPU
ns
4
t
Instruction cycle time
c(INST)
f
f
=8MHz
250
10
500
1500
22
CPU
2)
tCPU
µs
Interrupt reaction time
t
v(IT)
t
= ∆t
+ 10
=8MHz
1.25
2.75
v(IT)
c(INST)
CPU
13.5.2 External Clock Source
Symbol
Parameter
Conditions
Min
0.7xV
Typ
Max
Unit
V
OSC1 input pin high level voltage
OSC1 input pin low level voltage
V
DD
OSC1H
DD
SS
V
V
V
0.3xV
OSC1L
DD
t
t
3)
w(OSC1H)
OSC1 high or low time
15
w(OSC1L)
ns
t
t
3)
r(OSC1)
OSC1 rise or fall time
15
±1
f(OSC1)
I
OSCx Input leakage current
V
≤V ≤V
DD
µA
L
SS
IN
Figure 77. Typical Application with an External Clock Source
90%
V
V
OSC1H
OSC1L
10%
t
t
w(OSC1H)
t
t
w(OSC1L)
f(OSC1)
r(OSC1)
OSC2
Not connected internally
f
OSC
EXTERNAL
CLOCK SOURCE
I
L
OSC1
ST72XXX
Notes:
1. Data based on typical application software. Not tested in production.
2. Time measured between interrupt event and interrupt vector fetch. ∆tc(INST) is the number of tCPU cycles needed to finish
the current instruction execution.
3. Data based on design simulation and/or technology characteristics, not tested in production.
135/166
ST7265x
13.6 MEMORY CHARACTERISTICS
Subject to general operating conditions for V , f
, and T unless otherwise specified.
A
DD OSC
13.6.1 RAM and Hardware Registers
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
1)
V
Data retention mode
HALT mode (or RESET)
2
V
RM
13.6.2 FLASH Memory
Operating Conditions: f
= 8 MHz.
CPU
DUAL VOLTAGE FLASH MEMORY
Symbol
Parameter
Operating Frequency
Programming Voltage
Conditions
Read mode
Min
Typ
Max
Unit
8
f
MHz
Write / Erase mode,
CPU
8
T =25°C
A
V
4.0V <= V <= 5.5V
11.4
12.6
V
PP
DD
1)
I
V
Current
Write / Erase
30
mA
µs
PP
PP
1)
t
Byte Programming Time
Sector Erasing Time
Device Erasing Time
100
2
500
10
PROG
1)
1)
T =25°C
A
t
sec
ERASE
5
10
t
t
Internal V Stabilization Time
10
µs
VPP
PP
Data Retention
T
≤ 55°C
20
years
cycles
RET
A
N
Write Erase Cycles
T =25°C
100
RW
A
Note 1: Guaranteed by Design.
1)
Figure 78. Two typical Applications with V Pin
PP
V
V
PP
PP
PROGRAMMING
TOOL
10kΩ
ST72XXX
ST72XXX
Note 1: When the ICP mode is not required by the application, V pin must be tied to V
.
PP
SS
136/166
ST7265x
13.7 EMC CHARACTERISTICS
Susceptibility tests are performed on a sample ba-
sis during product characterization.
■ ESD: Electro-Static Discharge (positive and
negative) is applied on all pins of the device until
a functional disturbance occurs. This test
conforms with the IEC 1000-4-2 standard.
13.7.1 Functional EMS
(Electro Magnetic Susceptibility)
■ FTB: Burst of Fast Transient voltage (positive
Based on a simple running application on the
product (toggling 2 LEDs through I/O ports), the
product is stressed by two electro magnetic events
until a failure occurs (indicated by the LEDs).
and negative) is applied to V and V through
DD
SS
a 100pF capacitor, until a functional disturbance
occurs. This test conforms with the IEC 1000-4-
4 standard.
A device reset allows normal operations to be re-
sumed.
1)
1)
Symbol
Parameter
Conditions
=5V, T =+25°C, f
conforms to IEC 1000-4-2
Neg
Pos
Unit
Voltage limits to be applied on any I/O pin
to induce a functional disturbance
V
=8MHz
OSC
DD
A
V
-1
>1.5
2
FESD
kV
Fast transient voltage burst limits to be ap-
V
=5V, T =+25°C, f
=8MHz
OSC
DD
A
V
plied through 100pF on V and V pins
-2
FFTB
DD
DDA
conforms to IEC 1000-4-4
to induce a functional disturbance
2)
Figure 79. EMC Recommended star network power supply connection
ST72XXX
10µF 0.1µF
V
V
DD
SS
ST7
DIGITAL NOISE
FILTERING
V
DD
POWER
SUPPLY
SOURCE
V
V
SSA
DDA
EXTERNAL
NOISE
FILTERING
0.1µF
Notes:
1. Data based on characterization results, not tested in production.
2. The suggested 10µF and 0.1µF decoupling capacitors on the power supply lines are proposed as a good price vs. EMC
performance tradeoff. They have to be put as close as possible to the device power supply pins. Other EMC recommen-
dations are given in other sections (I/Os, RESET, OSCx pin characteristics).
137/166
ST7265x
EMC CHARACTERISTICS (Cont’d)
13.7.2 Electro Magnetic Interference (EMI)
Based on a simple application running on the product (toggling 2 LEDs through the I/O ports), the product
is monitored in terms of emission. This emission test is in line with the norm SAE J 1752/3 which specifies
the board and the loading of each pin.
Max vs. [f
/f
]
Unit
Monitored
Frequency Band
OSC CPU
Symbol
Parameter
Conditions
3MHz
21
16
8
6MHz
28
0.1MHz to 30MHz
30MHz to 130MHz
130MHz to 1GHz
SAE EMI Level
V
=5V, T =+25°C,
A
TQFP64 package
conforming to SAE J 1752/3
DD
30
dBµV
S
Peak level
EMI
31
2
4
-
Note 1. Data based on characterization results, not tested in production.
13.7.3 Absolute Electrical Sensitivity
standard. See Figure 80 and the following test se-
quence.
Based on three different tests (ESD, LU and DLU)
using specific measurement methods, the product
is stressed in order to determine its performance in
terms of electrical sensitivity. For more details, re-
fer to the AN1181 ST7 application note.
Human Body Model Test Sequence
– C is loaded through S1 by the HV pulse gener-
L
ator.
– S1 switches position from generator to R.
13.7.3.1 Electro-Static Discharge (ESD)
– A discharge from C through R (body resistance)
to the ST7 occurs.
L
Electro-Static Discharges (3 positive then 3 nega-
tive pulses separated by 1 second) are applied to
the pins of each sample according to each pin
combination. The sample size depends on the
number of supply pins of the device (3 parts*(n+1)
supply pin). One model is simulated: Human Body
Model. This test conforms to the JESD22-A114A
– S2 must be closed 10 to 100ms after the pulse
delivery period to ensure the ST7 is not left in
charge state. S2 must be opened at least 10ms
prior to the delivery of the next pulse.
Absolute Maximum Ratings
1)
Symbol
Ratings
Conditions
Maximum value
Unit
Electro-static discharge voltage
(Human Body Model)
T =+25°C
V
1500
V
A
ESD(HBM)
Figure 80. Typical equivalent ESD Circuit
R=1500Ω
S1
HIGH VOLTAGE
PULSE
GENERATOR
ST7
CL=100pF
S2
HUMAN BODY MODEL
Note 1: Data based on characterization results, not tested in production.
138/166
ST7265x
EMC CHARACTERISTICS (Cont’d)
13.7.3.2 Static and Dynamic Latch-Up
should be noted that good EMC performance is
highly dependent on the user application and the
software in particular.
■ LU: 3 complementary static tests are required
on 10 parts to assess the latch-up performance.
A supply overvoltage (applied to each power
supply pin), a current injection (applied to each
input, output and configurable I/O pin) and a
power supply switch sequence are performed
on each sample. This test conforms to the EIA/
JESD 78 IC latch-up standard. For more details,
refer to the AN1181 ST7 application note.
■ DLU: Electro-Static Discharges (one positive
then one negative test) are applied to each pin
of 3 samples when the micro is running to
assess the latch-up performance in dynamic
mode. Power supplies are set to the typical
values, the oscillator is connected as near as
possible to the pins of the micro and the
component is put in reset mode. This test
conforms to the IEC1000-4-2 and SAEJ1752/3
standards and is described in Figure 81. For
more details, refer to the AN1181 ST7
application note.
Therefore it is recommended that the user applies
EMC software optimization and prequalification
tests in relation with the EMC level requested for
his application.
Software recommendations:
The software flowchart must include the manage-
ment of runaway conditions such as:
– Corrupted program counter
– Unexpected reset
– Critical Data corruption (control registers...)
Prequalification trials:
Most of the common failures (unexpected reset
and program counter corruption) can be repro-
duced by manually forcing a low state on the RE-
SET pin or the Oscillator pins for 1 second.
To complete these trials, ESD stress can be ap-
plied directly on the device, over the range of
specification values. When unexpected behaviour
is detected, the software can be hardened to pre-
vent unrecoverable errors occurring (see applica-
tion note AN1015).
13.7.3.3 Designing hardened software to avoid
noise problems
EMC characterization and optimization are per-
formed at component level with a typical applica-
tion environment and simplified MCU software. It
Electrical Sensitivities
1)
Symbol
Parameter
Static latch-up class
Dynamic latch-up class
Conditions
Class
T =+25°C
A
A
A
A
LU
T =+85°C
A
T =+125°C
A
V
=5.5V, f
=4MHz, T =+25°C
OSC A
DLU
A
DD
Figure 81. Simplified Diagram of the ESD Generator for DLU
R
=50MΩ
R =330Ω
D
CH
DISCHARGE TIP
V
DD
SS
V
HV RELAY
C =150pF
S
ST7
ESD
2)
DISCHARGE
RETURN CONNECTION
GENERATOR
Notes:
1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC spec-
ifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the
JEDEC criteria (international standard).
2. Schaffner NSG435 with a pointed test finger.
139/166
ST7265x
EMC CHARACTERISTICS (Cont’d)
13.7.4 ESD Pin Protection Strategy
Standard Pin Protection
To protect an integrated circuit against Electro-
Static Discharge the stress must be controlled to
prevent degradation or destruction of the circuit el-
ements. The stress generally affects the circuit el-
ements which are connected to the pads but can
also affect the internal devices when the supply
pads receive the stress. The elements to be pro-
tected must not receive excessive current, voltage
or heating within their structure.
To protect the output structure the following ele-
ments are added:
– A diode to V (3a) and a diode from V (3b)
DD
SS
– A protection device between V and V (4)
DD
SS
To protect the input structure the following ele-
ments are added:
– A resistor in series with the pad (1)
– A diode to V (2a) and a diode from V (2b)
DD
SS
– A protection device between V and V (4)
An ESD network combines the different input and
output ESD protections. This network works, by al-
lowing safe discharge paths for the pins subjected
to ESD stress. Two critical ESD stress cases are
presented in Figure 82 and Figure 83 for standard
pins and in Figure 84 and Figure 85 for true open
drain pins.
DD
SS
Figure 82. Positive Stress on a Standard Pad vs. V
SS
V
V
DD
DD
(3a)
(3b)
(2a)
(1)
(4)
OUT
IN
Main path
(2b)
Path to avoid
V
V
V
SS
SS
Figure 83. Negative Stress on a Standard Pad vs. V
DD
V
DD
DD
(3a)
(3b)
(2a)
(1)
(4)
OUT
IN
Main path
(2b)
V
V
SS
SS
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ST7265x
EMC CHARACTERISTICS (Cont’d)
True Open Drain Pin Protection
Multisupply Configuration
When several types of ground (V , V
The centralized protection (4) is not involved in the
discharge of the ESD stresses applied to true
open drain pads due to the fact that a P-Buffer and
, ...) and
SSA
SS
power supply (V , V
, ...) are available for any
DD
DDA
reason (better noise immunity...), the structure
shown in Figure 86 is implemented to protect the
device against ESD.
diode to V
local protection between the pad and V
are not implemented. An additional
DD
(5a &
SS
5b) is implemented to completely absorb the posi-
tive ESD discharge.
Figure 84. Positive Stress on a True Open Drain Pad vs. V
SS
V
V
DD
DD
Main path
(1)
OUT
(4)
IN
Path to avoid
(5a)
(5b)
(3b)
(2b)
V
V
SS
SS
Figure 85. Negative Stress on a True Open Drain Pad vs. V
DD
V
V
DD
DD
Main path
(1)
OUT
(4)
IN
(3b)
(3b)
(3b)
(2b)
V
V
SS
SS
Figure 86. Multisupply Configuration
V
DD
V
DDA
V
DDA
V
SS
BACK TO BACK DIODE
BETWEEN GROUNDS
V
SSA
V
SSA
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ST7265x
13.8 I/O PORT PIN CHARACTERISTICS
13.8.1 General Characteristics
Subject to general operating conditions for V , f
, and T unless otherwise specified.
DD OSC
A
1)
Symbol
Parameter
Input low level voltage
Conditions
Min
Typ
Max
Unit
V
V
V
V
= 5.0V
= 5.0V
V
ss
0.3xVDD
IL
DD
V
Input high level voltage
Schmitt trigger voltage hysteresis
Input leakage current
0.7xVDD
V
DD
IH
DD
3)
V
400
mV
µA
hys
I
V
SS≤V ≤V
±1
L
IN
DD
4)
I
Static current consumption
Floating input mode
200
130
260
S
V
V
=5V
=3V
70
100
200
5
DD
DD
5)
R
Weak pull-up equivalent resistor
V =V
SS
kΩ
pF
ns
PU
IN
130
6)
C
I/O pin capacitance
IO
6)
t
t
Output high to low level fall time
25
C =50pF
Between 10% and 90%
f(IO)out
r(IO)out
L
6)
Output low to high level rise time
25
7)
t
External interrupt pulse time
1
t
CPU
w(IT)in
.Notes:
1. Unless otherwise specified, typical data are based on T =25°C and V =5V.
A
DD
2. Data based on characterization results, not tested in production.
3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
4. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for
example or an external pull-up or pull-down resistor (see Figure ). Data based on design simulation and/or technology
characteristics, not tested in production.
5. The R pull-up equivalent resistor is based on a resistive transistor (corresponding I current characteristics de-
PU
PU
scribed in Figure 89). This data is based on characterization results, tested in production at V =5V.
DD
6. Data based on characterization results, not tested in production.
7. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external
interrupt source.
Figure 87Two typical Applications with unused I/O Pin
V
ST72XXX
DD
UNUSED I/O PORT
10kΩ
10kΩ
UNUSED I/O PORT
ST72XXX
142/166
ST7265x
. I/O PORT PIN CHARACTERISTICS (Cont’d)
Figure 88. V and V vs. V with V =V
IL
IH
DD
IN
SS
3.5
3
2.5
2
1.5
1
Vih
Vil
0.5
0
2.5
3
3.5
4
4.5
5
5.5
6
Vdd (V)
Figure 89. Typical I vs. V with V =V
Figure 90. Typical R vs. V with V =V
PU DD IN SS
PU
DD
IN
SS
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
300
250
200
150
100
50
0
2
3
4
5
6
7
Vdd (V)
2
3
4
5
6
7
Vdd (V)
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ST7265x
I/O PORT PIN CHARACTERISTICS (Cont’d)
13.8.2 Output Driving Current
Subject to general operating conditions for V , f
, and T unless otherwise specified.
A
DD OSC
Symbol
Parameter
Conditions
Min
Max
Unit
Output low level voltage for a standard I/O pin
when 8 pins are sunk at same time
(see Figure 91 and Figure 94)
I
I
I
I
I
I
=+5mA
=+2mA
=+20mA
=+8mA
=-5mA
=-2mA
1.2
IO
IO
IO
IO
IO
IO
0.5
1.3
0.6
1)
V
OL
Output low level voltage for a high sink I/O pin
when 4 pins are sunk at same time
(see Figure 93 and Figure 95)
V
Output high level voltage for an I/O pin
when 8 pins are sourced at same time
(see Figure 92 and Figure 96)
V
V
-1.4
DD
DD
2)
V
OH
-0.7
Figure 91. Typical V at V =5V (standard)
Figure 93. Typical V at V =5V (high-sink)
OL DD
OL
DD
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
5
10
15
Iol (mA)
20
25
30
0
1
2
3
4
5
6
7
Iol (mA)
Figure 92Typical V -V
at V =5V
DD
DD OH
1.2
1
0.8
0.6
0.4
0.2
0
0
1
2
3
4
5
6
7
-Ioh (mA)
Notes:
1. The I current sunk must always respect the absolute maximum rating specified in Section 13.2.2 and the sum of I
IO
IO
(I/O ports and control pins) must not exceed I
.
VSS
2. The I current sourced must always respect the absolute maximum rating specified in Section 13.2.2 and the sum of
IO
I
(I/O ports and control pins) must not exceed I
. True open drain I/O pins does not have V
.
IO
VDD
OH
144/166
ST7265x
I/O PORT PIN CHARACTERISTICS (Cont’d)
Figure 94.Typical V vs. V (standard I/Os)
OL
DD
0.35
0.3
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.25
0.2
0.15
0.1
0.05
0
2
3
4
5
6
7
2
3
4
5
6
7
Vdd (V)
Vdd (V)
Figure 95. Typical V vs. V (high-sink I/Os)
OL
DD
0.5
0.45
0.4
1.6
1.4
1.2
1
0.35
0.3
0.25
0.2
0.8
0.6
0.4
0.2
0
0.15
0.1
0.05
0
2
3
4
5
6
7
2
3
4
5
6
7
Vdd (V)
Vdd (V)
Figure 96. Typical V
vs. V
DD
OH
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
3
2.5
2
1.5
1
0.5
0
2
3
4
5
6
7
2
3
4
5
6
7
Vdd (V)
Vdd (V)
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ST7265x
13.9 CONTROL PIN CHARACTERISTICS
13.9.1 Asynchronous RESET Pin
Subject to general operating conditions for V , f
, and T unless otherwise specified.
DD OSC
A
1)
Symbol
Parameter
Conditions
=5V
Min
Typ
Max
Unit
V
2)
V
Input low level voltage
V
V
V
SS
0.3xVDD
IL
DD
2)
V
Input high level voltage
=5V
0.7xVDD
V
DD
IH
DD
3)
V
Schmitt trigger voltage hysteresis
400
0.68
0.28
100
200
mV
V
hys
I
I
=+5mA
=+2mA
0.95
0.45
130
260
IO
IO
4)
V
Output low level voltage
V
=5V
OL
ON
DD
V
V
=5V
70
DD
DD
5)
R
Weak pull-up equivalent resistor
Generated reset pulse duration
V =V
kΩ
IN
SS
=3.3V
130
External pin or
internal reset sources
t
4
1/f
SFOSC
w(RSTL)out
6)
t
t
External reset pulse hold time
20
µs
h(RSTL)in
7)
Filtered glitch duration
100
ns
g(RSTL)in
8)
Figure 97. Typical Application with RESET pin
ST72XXX
V
DD
V
V
DD
DD
INTERNAL
RESET CONTROL
R
ON
0.1µF
0.1µF
4.7kΩ
EXTERNAL
RESET
RESET
8)
CIRCUIT
WATCHDOG RESET
LVD RESET
Notes:
1. Unless otherwise specified, typical data are based on T =25°C and V =5V.
A
DD
2. Data based on characterization results, not tested in production.
3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
4. The I current sunk must always respect the absolute maximum rating specified in Section 13.2.2 and the sum of I
IO
IO
(I/O ports and control pins) must not exceed I
. Not tested in production.
VSS
5. The R
pull-up equivalent resistor is based on a resistive transistor (corresponding I current characteristics de-
ON
ON
scribed in Figure 97). This data is based on characterization results, not tested in production.
6. All short pulse applied on RESET pin with a duration below t can be ignored.
h(RSTL)in
7. The reset network protects the device against parasitic resets, especially in a noisy environment.
8. The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device
can be damaged when the ST7 generates an internal reset (LVD or watchdog).
146/166
ST7265x
CONTROL PIN CHARACTERISTICS (Cont’d)
13.9.2 V Pin
PP
Subject to general operating conditions for V , f
, and T unless otherwise specified.
A
DD OSC
Symbol
Parameter
Conditions
Min
Max
Unit
V
1)
V
Input low level voltage
V
0.2
IL
IH
L
SS
1)
V
I
Input high level voltage
Input leakage current
V
-0.1 12.6
±1
DD
V =V
µA
IN
SS
2)
Figure 98. Two typical Applications with V Pin
PP
V
V
PP
PP
PROGRAMMING
TOOL
10kΩ
ST72XXX
ST72XXX
Notes:
1. Data based on design simulation and/or technology characteristics, not tested in production.
2. When the ICP mode is not required by the application, VPP pin must be tied to V
.
SS
147/166
ST7265x
13.10 TIMER PERIPHERAL CHARACTERISTICS
Subject to general operating conditions for V
,
Refer to I/O port characteristics for more details on
the input/output alternate function characteristics
(output compare, input capture, external clock,
PWM output...).
DD
f
, and T unless otherwise specified.
OSC
A
13.10.1 Watchdog Timer
Symbol
Parameter
Watchdog time-out duration
Conditions
Min
Typ
Max
Unit
tCPU
ms
65,536
8.192
4,194,304
524.288
t
w(WDG)
fCPU=8MHz
13.10.2 PWM Generator
Symbol
Parameter
Conditions
Min
Typ
125
125
5
Max
Unit
KHz
ns
T
Res
s
Repetition rate
Resolution
T
T
=125ns
=125ns
-
-
-
-
-
-
CPU
CPU
Output step
V
=5V
mV
DD
148/166
ST7265x
13.11 COMMUNICATION INTERFACE CHARACTERISTICS
13.11.1 SPI - Serial Peripheral Interface
Refer to I/O port characteristics for more details on
the input/output alternate function characteristics
(SS, SCK, MOSI, MISO).
Subject to general operating conditions for V
,
DD
f
, and T unless otherwise specified.
OSC
A
Symbol
Parameter
Conditions
Min
/128
0.0625
Max
Unit
Master
Slave
f
f
f
/4
CPU
2
CPU
f
=8MHz
=8MHz
f
CPU
SCK
SPI clock frequency
MHz
1/t
/2
c(SCK)
CPU
0
f
4
CPU
t
t
r(SCK)
SPI clock rise and fall time
see I/O port pin description
f(SCK)
t
SS setup time
SS hold time
Slave
Slave
120
120
su(SS)
t
h(SS)
t
t
Master
Slave
100
90
w(SCKH)
SCK high and low time
Data input setup time
Data input hold time
w(SCKL)
t
Master
Slave
100
100
su(MI)
t
su(SI)
ns
t
Master
Slave
100
100
h(MI)
t
h(SI)
t
Data output access time
Data output disable time
Data output valid time
Data output hold time
Data output valid time
Data output hold time
Slave
Slave
0
120
240
120
a(SO)
t
dis(SO)
t
v(SO)
h(SO)
v(MO)
h(MO)
Slave (after enable edge)
t
0
t
0.25
0.25
Master (before capture edge)
t
CPU
t
Figure 99. SPI Slave Timing Diagram with CPHA=0 3)
SS
INPUT
t
t
su(SS)
c(SCK)
t
h(SS)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
t
t
w(SCKH)
w(SCKL)
t
t
t
t
dis(SO)
a(SO)
v(SO)
h(SO)
t
t
r(SCK)
f(SCK)
see
note 2
MISO
OUTPUT
INPUT
MSB OUT
see note 2
BIT6 OUT
LSB OUT
t
t
h(SI)
su(SI)
MSB IN
LSB IN
BIT1 IN
MOSI
Notes:
1. Data based on design simulation and/or characterisation results, not tested in production.
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has
its alternate function capability released. In this case, the pin status depends on the I/O port configuration.
3. Measurement points are done at CMOS levels: 0.3xV and 0.7xV
.
DD
DD
149/166
ST7265x
COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d)
Figure 100. SPI Slave Timing Diagram with CPHA=11)
SS
INPUT
t
t
su(SS)
c(SCK)
t
h(SS)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
t
w(SCKH)
t
t
dis(SO)
a(SO)
t
t
t
h(SO)
w(SCKL)
v(SO)
t
t
r(SCK)
f(SCK)
see
note 2
see
note 2
MISO
OUTPUT
MSB OUT
BIT6 OUT
HZ
LSB OUT
t
t
h(SI)
su(SI)
LSB IN
MSB IN
BIT1 IN
MOSI
INPUT
Figure 101. SPI Master Timing Diagram 1)
SS
INPUT
t
c(SCK)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
CPHA=1
CPOL=0
CPHA=1
CPOL=1
t
t
w(SCKH)
w(SCKL)
t
t
r(SCK)
f(SCK)
t
t
h(MI)
su(MI)
MISO
MOSI
INPUT
MSB IN
BIT6 IN
LSB IN
t
t
h(MO)
v(MO)
LSB OUT
MSB OUT
see note 2
BIT6 OUT
see note 2
OUTPUT
Notes:
1. Measurement points are done at CMOS levels: 0.3xV and 0.7xV
.
DD
DD
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has
its alternate function capability released. In this case, the pin status depends of the I/O port configuration.
150/166
ST7265x
COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d)
2
13.11.2 I C - Inter IC Control Interface
Refer to I/O port characteristics for more details on
the input/output alternate function characteristics
Subject to general operating conditions for V
,
DD
2
(SDAI and SCLI). The ST7 I C interface meets the
f
, and T unless otherwise specified.
OSC
A
2
requirements of the Standard I C communication
protocol described in the following table.
2
2
Standard mode I C
Fast mode I C
Symbol
Parameter
Unit
1)
1)
1)
1)
Min
Max
Min
Max
t
SCL clock low time
SCL clock high time
SDA setup time
4.7
4.0
1.3
0.6
100
w(SCLL)
µs
t
w(SCLH)
t
250
su(SDA)
3)
2)
3)
t
SDA data hold time
0
0
900
h(SDA)
t
t
r(SDA)
ns
SDA and SCL rise time
SDA and SCL fall time
1000
300
20+0.1C
300
300
b
b
r(SCL)
t
t
f(SDA)
20+0.1C
f(SCL)
t
START condition hold time
4.0
4.7
4.0
4.7
0.6
0.6
0.6
1.3
h(STA)
µs
t
Repeated START condition setup time
STOP condition setup time
su(STA)
su(STO)
t
ns
ms
pF
t
STOP to START condition time (bus free)
Capacitive load for each bus line
w(STO:STA)
C
400
400
b
2
Figure 102. Typical Application with I C Bus and Timing Diagram 4)
V
V
DD
DD
4.7kΩ
4.7kΩ
100Ω
100Ω
SDAI
SCLI
2
I C BUS
ST72XXX
REPEATED START
START
t
t
su(STA)
w(STO:STA)
STOP
START
SDA
t
t
r(SDA)
f(SDA)
t
t
h(SDA)
su(SDA)
SCK
t
t
t
t
t
su(STO)
t
h(STA)
w(SCKH)
w(SCKL)
r(SCK)
f(SCK)
Notes:
2
1. Data based on standard I C protocol requirement, not tested in production.
2. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined
region of the falling edge of SCL.
3. The maximum hold time of the START condition has only to be met if the interface does not stretch the low period of
SCL signal.
4. Measurement points are done at CMOS levels: 0.3xV and 0.7xV
.
DD
DD
151/166
ST7265x
COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d)
2
13.11.3 I C - Inter IC Control Interface
2
I C-Bus Timings
2
2
Standard I C
Fast I C
Min Max
Parameter
Symbol
Unit
ms
Min
Max
Bus free time between a STOP and START con-
dition
4.7
1.3
0.6
T
BUF
Hold time START condition. After this period,
the first clock pulse is generated
LOW period of the SCL clock
4.0
T
µs
HD:STA
4.7
1.3
0.6
0.6
T
T
T
T
T
T
µs
µs
µs
ns
ns
ns
ns
ns
pF
LOW
HIGH period of the SCL clock
Set-up time for a repeated START condition
Data hold time
4.0
HIGH
SU:STA
HD:DAT
SU:DAT
R
4.7
0 (1)
250
0 (1)
0.9(2)
Data set-up time
100
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Set-up time for STOP condition
Capacitive load for each bus line
1000
300
20+0.1Cb
20+0.1Cb
0.6
300
300
TF
4.0
T
:
SU STO
400
400
Cb
1) The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge
the undefined region of the falling edge of SCL
2) The maximum hold time of the START condition has only to be met if the interface does not stretch the
low period of SCL signal
Cb = total capacitance of one bus line in pF
152/166
ST7265x
COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d)
13.11.4 USB - Universal Bus Interface
USB DC Electrical Characteristics
2)
2)
Parameter
Input Levels:
Symbol
Conditions
Min.
Max.
Unit
Differential Input Sensitivity
Differential Common Mode Range
Single Ended Receiver Threshold
Output Levels
VDI
VCM
VSE
I(D+, D-)
0.2
0.8
1.3
V
V
V
Includes VDI range
2.5
2.0
1)
Static Output Low
VOL
VOH
RL of 1.5K ohms to 3.6V
0.3
3.6
V
V
1)
Static Output High
RL of 15K ohm to V
2.8
SS
V
=4.0V - 5.5V
Max = 3mA
3)
DD
USBV : voltage level
USBV
3.00
3.60
V
CC
I
LOAD
Note 1: RL is the load connected on the USB drivers.
Note 2: All the voltages are measured from the local ground potential.
Note 3: An external decoupling capacitor (typical 100nF, min 47nF) must be connected between this pin
and USBV
.
SS
Figure 103. USB: Data Signal Rise and Fall
Time
Differential
Data Lines
Crossover
points
VCRS
VSS
tr
tf
USB: Full speed electrical characteristics
Parameter
Driver characteristics:
Rise time
Symbol
Conditions
Min
Max
Unit
tr
tf
Note 1,CL=50 pF
Note 1, CL=50 pF
tr/tf
4
4
20
20
ns
ns
%
Fall Time
Rise/ Fall Time matching
trfm
90
110
Output signal Crossover
Voltage
VCRS
1.3
2.0
V
Note1: Measured from 10% to 90% of the data signal. For more detailed informations, please refer to
Chapter 7 (Electrical) of the USB specification (version 1.1).
153/166
ST7265x
13.12 8-BIT ADC CHARACTERISTICS
Subject to general operating conditions for V , f
, and T unless otherwise specified.
DD OSC
A
1)
Symbol
Parameter
ADC clock frequency
Conversion range voltage
External input resistor
Conditions
Min
Typ
Max
Unit
MHz
V
f
4
ADC
2)
V
R
V
V
AIN
AIN
SSA
DDA
3)
10
kΩ
C
Internal sample and hold capacitor
Stabilization time after ADC enable
Conversion time (Sample+Hold)
6
pF
ADC
STAB
4)
t
0
µs
6
f
=8MHz, f
=2MHz
ADC
CPU
t
- Sample capacitor loading time
- Hold conversion time
4
8
ADC
1/f
ADC
Figure 104. Typical Application with ADC
V
DD
V
T
0.6V
R
AIN
AINx
V
AIN
ADC
V
0.6V
T
C
~2pF
I
L
±1µA
IO
V
DD
V
V
DDA
SSA
0.1µF
ST72XXX
Notes:
1. Unless otherwise specified, typical data are based on T =25°C and V -V =5V. They are given only as design guide-
A
DD SS
lines and are not tested.
2. When V and V
pins are not available on the pinout, the ADC refer to V and V .
SS
DDA
SSA
DD
3. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10kΩ). Data
based on characterization results, not tested in production.
4. The stabilization time of the AD converter is masked by the first t
always valid.
. The first conversion after the enable is then
LOAD
154/166
ST7265x
8-BIT ADC CHARACTERISTICS (Cont’d)
ADC Accuracy
2)
3)
3)
V
f
=5.5V,
V
f
=5.0V,
V
=3.3V,
DD
DD
DD
Conditions
1)
1)
=1MHz
=8MHz
f
=8MHz
Symbol
Parameter
CPU
CPU
CPU
Min
Max
Min
Max
2.5
1.5
0
Min
Max
2.5
1.5
0
1)
2.5
1.5
0
E
E
Total Unadjusted Error
Offset Error
T
-0.5
-2.0
-1.0
-2.0
-1.0
-2.0
0
1)
E
Gain Error
G
1)
1.5
2.5
1.5
2.5
1.5
3.0
|E |
Differential linearity error
D
1)
|E |
Integral linearity error
L
Figure 105. ADC Accuracy Characteristics
Digital Result ADCDR
E
G
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line
255
V
V
254
253
DDA
SSA
1LSB
= ----------------------------------------
IDEAL
256
(2)
E =Total Unadjusted Error: maximum deviation
T
E
between the actual and the ideal transfer curves.
T
(3)
7
6
5
4
3
2
1
E =Offset Error: deviation between the first actual
O
(1)
transition and the first ideal one.
E =Gain Error: deviation between the last ideal
G
transition and the last actual one.
E
O
E
L
E =Differential Linearity Error: maximum deviation
D
between actual steps and the ideal one.
E =Integral Linearity Error: maximum deviation
L
E
between any actual transition and the end point
correlation line.
D
1 LSB
IDEAL
7
V
(LSB
)
IDEAL
in
0
1
2
3
4
5
6
253 254 255 256
V
V
DDA
SSA
Notes:
1. ADC Accuracy vs. Negative Injection Current:
For I =0.8mA, the typical leakage induced inside the die is 1.6µA and the effect on the ADC accuracy is a loss of 1 LSB
INJ-
for each 10KΩ increase of the external analog source impedance. This effect on the ADC accuracy has been observed
under worst-case conditions for injection:
- negative injection
- injection to an Input with analog capability, adjacent to the enabled Analog Input
- at 5V V supply, and worst case temperature.
DD
2. Data based on characterization results with T =25°C.
A
3. Data based on characterization results over the whole temperature range, monitored in production.
155/166
ST7265x
14 PACKAGE CHARACTERISTICS
14.1 PACKAGE MECHANICAL DATA
Figure 106. 48-Pin Thin Quad Flat Package
mm
inches
Dim.
Min Typ Max Min Typ Max
D
A
A
1.60
0.063
0.006
D1
A2
A1 0.05
0.15 0.002
A2 1.35 1.40 1.45 0.053 0.055 0.057
A1
b
C
0.17 0.22 0.27 0.007 0.009 0.011
0.09 0.20 0.004 0.008
b
D
9.00
7.00
9.00
7.00
0.50
3.5°
0.354
0.276
0.354
0.276
0.020
3.5°
D1
E
e
E1
E
E1
e
θ
0°
7°
0°
7°
c
L1
L
0.45 0.60 0.75 0.018 0.024 0.030
1.00 0.039
Number of Pins
48
L
h
L1
N
Figure 107. 34-Pin Plastic Small Outline Package, Shrink 300-mil Width
mm
inches
Dim.
Min Typ Max Min Typ Max
h x 45×
L
A
2.464
2.642 0.097
0.292 0.005
0.483 0.014
0.318 0.009
0.104
0.012
0.019
0.013
A
C
A1
A1 0.127
a
B
C
0.356
0.231
e
B
D
17.72
9
18.05
0.698
9
D
0.711
0.299
E
e
7.417
7.595 0.292
1.016
0.040
10.16
0
10.41
0.400
4
H
0.410
E
H
h
α
0.635
0°
0.737 0.025
0.029
8°
8°
0°
L
0.610
1.016 0.024
0.040
Number of Pins
N
34
156/166
ST7265x
PACKAGE MECHANICAL DATA (Cont’d)
Figure 108. 64-Pin 10 x 10 Thin Quad Flat Package
0.10mm
.004
seating plane
mm
inches
Dim
Min Typ Max Min Typ Max
A
1.60
0.063
0.006
A1 0.05
0.15 0.002
A2 1.35 1.40 1.45 0.053 0.055 0.057
b
C
0.17 0.22 0.27 0.007 0.009 0.011
0.09 0.20 0.004 0.008
D
12.00
10.00
12.00
10.00
0.50
0.472
0.394
0.472
0.394
0.020
D1
E
E1
e
K
0° 3.5°
0.45 0.60 0.75 0.018 0.024 0.030
1.00 0.039
Number of Pins
ND 16 NE
7°
0°
3.5° 7°
L
L1
L1
L
N
64
16
K
157/166
ST7265x
PACKAGE MECHANICAL DATA (Cont’d)
Figure 109. Recommended Reflow Oven Profile (MID JEDEC)
250
Tmax=220+/-5°C
for 25 sec
200
150
100
50
150 sec above 183°C
90 sec at 125°C
Temp. [°C]
ramp down natural
2°C/sec max
ramp up
2°C/sec for 50sec
Time [sec]
0
100
200
300
400
158/166
ST7265x
15 DEVICE CONFIGURATION AND ORDERING INFORMATION
Each device is available for production in user pro-
PE5PU
grammable versions (FLASH) as well as in factory
coded versions (ROM). FLASH devices are
shipped to customers with a default content (FFh),
while ROM factory coded parts contain the code
supplied by the customer. This implies that FLASH
devices have to be configured by the customer us-
ing the Option Bytes while the ROM devices are
factory-configured.
Configuration
PEOR.5 PEDDR.5
OPTION
Input floating
0
0
0
1
Output Open Drain
with Pull-up
0
Input with pull-up
Output push pull
Input floating
1
1
0
0
1
1
0
1
0
1
0
1
Output Open Drain
Input floating
15.1 OPTION BYTE
1
The option byte allows the hardware configuration
of the microcontroller to be selected.
Output push pull
OPT5:4 = PSMOD[1:0] Power Supply Mode
These option bits configure the power supply
mode.
The option byte has no address in the memory
map and can be accessed only in programming
mode (for example using a standard ST7 program-
ming tool). The default content of the FLASH is
fixed to FFh. This means that all the options have
“1” as their default value.
Mode
OPT5
OPT4
Stand-alone mode forced
Dual Supply (normal) Mode
USB mode forced
0
x
1
0
1
0
In masked ROM devices, the option byte is fixed in
hardware by the ROM code (see option list)
7
-
0
OPT3 = Reserved. Must be kept at 1.
PS
PS
PE5
PU
WDG USB FMP_
MOD MOD
1
-
SW
EN
R
OPT2= WDG SW Hardware or software watchdog
This option bit selects the watchdog type.
0: Hardware (watchdog always enabled)
0
OPT7 = Reserved. Must be kept at 1.
1: Software (watchdog to be enabled by software)
OPT6 = PE5PU I/O Port PE5 Pull-up Option
This option bit determines if a pull-up is connected
on Port E5.
OPT1 = USBEN
0: USBEN alternate function disabled. Port F4 is
free for general purpose I/O
0: Pull up present on PE5
1: No pull-up on PE5
1: USBEN alternate function enabled on Port F4
(function controlled by hardware)
When PE5PU=00:
– For input, software can enable or disable the
pull-up by programming PEOR.5 and PED-
DR.5=0.
OPT0= FMP_R Flash memory read-out protection
This option indicates if the user flash memory is
protected against read-out piracy. This protection
is based on read and a write protection of the
memory in test modes and IAP. Erasing the option
bytes when the FMP_R option is selected will
cause the whole user memory to be erased first,
and the device can be reprogrammed. Refer to the
ST7 Flash Programming Reference Manual and
section 4.4 on page 22 for more details.
– For output, the pull-up is enabled when Open
Drain is selected by programming PEOR.5= and
PEDDR.5=1.
Refer to the following table.
0: Read-out protection enabled
1: Read-out protection disabled
159/166
ST7265x
15.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE
Customer code is made up of the ROM contents.
The ROM contents are to be sent on diskette, or
by electronic means, with the hexadecimal file in
.S19 format generated by the development tool.
All unused bytes must be set to FFh.
The customer code should be communicated to
STMicroelectronics with the correctly completed
OPTION LIST appended.
The STMicroelectronics Sales Organization will be
pleased to provide detailed information on con-
tractual points.
Figure 110. Sales Type Coding Rules 2)
Family (ROM, FLASH, FASTROM)
Product Line (1,2,3 ...)
Number of pins
ROM size
Package
Temperature Range
No LVD option
ROM Code (three letters)
ST 7265 1 AR 6 T 1 E / xxx
E= without LVD (external
0= 25°C
AR = 64 pins
(TQFP64 (10X10))
T=Thin Quad Flat Pack
6=32K
reset needed)
No letter = with LVD
1= Standard (0 to +70°C) M=Small Outline Package 4=16K C=48 pins
L=34 pins
Table 38. Ordering Information
User
Program
Memory (bytes)
1) 2)
Sales Type
RAM
Package
Operating Voltage
(bytes)
ST72F651AR6T1
32K FLASH
32K ROM
16K ROM
16K ROM
16K ROM
32K FLASH
32K ROM
5K
5K
ST72651AR6T1/xxx
ST72652AR4T1/xxx
ST72652C4T1/xxx
ST72652L4M1/xxx
ST72F651AR6T1E
ST72651AR6T1E/xxx
TQFP 64 (10X10)
512
512
512
5K
4.0V-5.5V
TQFP48
SO34
3.0V-5.5V
2.7V-5.5V
TQFP 64 (10X10)
5K
Note 1. /xxx stands for the ROM code name assigned by STMicroelectronics
Note 2. Devices with E Suffix have no embedded LVD
160/166
ST7265x
ST7265x MICROCONTROLLER OPTION LIST
Customer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact
Phone No . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference/ROM Code*:. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
*ROM code name is assigned by STMicroelectronics.
ROM code must be sent in .S19 format. .Hex extension cannot be processed.
STMicroelectronics references:
Device Type/Memory Size/Package (check only one option):
--------------------------------- ---------------------------------------------------- ------------------------------------------
|
|
|
|
ROM DEVICE:
16K (without low voltage feature)
32K
--------------------------------- ---------------------------------------------------- ------------------------------------------
TQFP64:
TQFP48:
SO34:
|
|
|
[ ] ST72652AR4T1
[ ] ST72652C4T1
[ ] ST72652L4M1
|
|
|
[ ] ST72651AR6T1
Conditioning (check only one option):
[ ] Tray
[ ] Tape & Reel
LVD option:
Marking:
[ ] Yes
[ ] No
[ ] Standard marking
[ ] Special marking:
TQFP64 (10 char. max): _ _ _ _ _ _ _ _ _ _
Authorized characters are letters, digits, '.', '-', '/' and spaces only.
Please consult your local STMicroelectronics sales office for other marking details if required.
Pull-up on PE5:
[ ] Disabled
[ ] Enabled
Power Supply mode:
[ ] Stand-alone mode
[ ] Dual supply mode
[ ] USB mode
Watchdog Selection:
USBEN alternate function:
Readout Protection:
[ ] Software Activation
[ ] Disabled
[ ] Hardware Activation
[ ] Enabled
[ ] Disabled
[ ] Enabled
Software Development:
[ ] STMicroelectronics
[ ] Customer
[ ] External laboratory
Comments: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply Operating Range in the application: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Notes
Date
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
161/166
ST7265x
15.3 DEVELOPMENT TOOLS
STmicroelectronics offers a range of hardware
and software development tools for the ST7 micro-
controller family. Full details of tools available for
the ST7 from third party manufacturers can be ob-
tain from the STMicroelectronics Internet site:
➟ http//mcu.st.com.
STMicroelectronics Tools
Three types of development tool are offered by
ST, all of them connect to a PC via a parallel (LPT)
or USB port: see Table 39 for more details.
Tools from these manufacturers include C compli-
ers, emulators and gang programmers.
Table 39. STMicroelectronics Tool Features
Programming
Capability
In-Circuit Emulation
Sales Type
Remarks
1)
Yes, powerful emulation
features including trace/ No
logic analyzer
ST7 FLASH
HDS2 Emulator
ST7MDTU5-EMU2B
3)
ST7 Programming
Board
ST7MDTU5-EPB/EU
ST7MDTU5-EPB/US
220V
110V
No
Yes
3)
Gang
Programmer
See 3rd Party
TQFP64 package
C Hiware
Compiler
ST7-HICROSS
ST7-HIWAVE
for PC
for PC
Hiware Debugger
Note:
1. In-Application Programming (IAP) and In-Circuit programming for Flash devices.
2. These products come with a CD ROM which contains the following software:
– ST7 Assembly toolchain
– STVD7 and WGDB7 powerful Source Level Debugger for Win 3.1, Win 95 and NT
– C compiler demo versions
– ST Realizer for Win 3.1 and Win 95
– Windows Programming Tools for Win 3.1, Win 95 and NT
3. TQFP64 package only.
162/166
ST7265x
15.4 ST7 APPLICATION NOTES
IDENTIFICATION
DESCRIPTION
EXAMPLE DRIVERS
AN 969
AN 970
AN 971
AN 972
AN 973
AN 974
AN 976
AN 979
AN 980
AN1017
AN1041
AN1042
AN1044
AN1045
AN1046
AN1047
AN1048
AN1078
AN1082
AN1083
AN1105
AN1129
SCI COMMUNICATION BETWEEN ST7 AND PC
SPI COMMUNICATION BETWEEN ST7 AND EEPROM
I²C COMMUNICATING BETWEEN ST7 AND M24CXX EEPROM
ST7 SOFTWARE SPI MASTER COMMUNICATION
SCI SOFTWARE COMMUNICATION WITH A PC USING ST72251 16-BIT TIMER
REAL TIME CLOCK WITH ST7 TIMER OUTPUT COMPARE
DRIVING A BUZZER THROUGH ST7 TIMER PWM FUNCTION
DRIVING AN ANALOG KEYBOARD WITH THE ST7 ADC
ST7 KEYPAD DECODING TECHNIQUES, IMPLEMENTING WAKE-UP ON KEYSTROKE
USING THE ST7 UNIVERSAL SERIAL BUS MICROCONTROLLER
USING ST7 PWM SIGNAL TO GENERATE ANALOG OUTPUT (SINUSOID)
ST7 ROUTINE FOR I²C SLAVE MODE MANAGEMENT
MULTIPLE INTERRUPT SOURCES MANAGEMENT FOR ST7 MCUS
ST7 S/W IMPLEMENTATION OF I²C BUS MASTER
UART EMULATION SOFTWARE
MANAGING RECEPTION ERRORS WITH THE ST7 SCI PERIPHERALS
ST7 SOFTWARE LCD DRIVER
PWM DUTY CYCLE SWITCH IMPLEMENTING TRUE 0% & 100% DUTY CYCLE
DESCRIPTION OF THE ST72141 MOTOR CONTROL PERIPHERAL REGISTERS
ST72141 BLDC MOTOR CONTROL SOFTWARE AND FLOWCHART EXAMPLE
ST7 PCAN PERIPHERAL DRIVER
PERMANENT MAGNET DC MOTOR DRIVE.
AN INTRODUCTION TO SENSORLESS BRUSHLESS DC MOTOR DRIVE APPLICATIONS
WITH THE ST72141
AN1130
AN1148
AN1149
AN1180
AN1276
AN1321
AN1325
AN1445
AN1475
AN1504
USING THE ST7263 FOR DESIGNING A USB MOUSE
HANDLING SUSPEND MODE ON A USB MOUSE
USING THE ST7263 KIT TO IMPLEMENT A USB GAME PAD
BLDC MOTOR START ROUTINE FOR THE ST72141 MICROCONTROLLER
USING THE ST72141 MOTOR CONTROL MCU IN SENSOR MODE
USING THE ST7 USB LOW-SPEED FIRMWARE V4.X
USING THE ST7 SPI TO EMULATE A 16-BIT SLAVE
DEVELOPING AN ST7265X MASS STORAGE APPLICATION
STARTING A PWM SIGNAL DIRECTLY AT HIGH LEVEL USING THE ST7 16-BIT TIMER
PRODUCT EVALUATION
AN 910
AN 990
AN1077
AN1086
AN1150
AN1151
AN1278
PERFORMANCE BENCHMARKING
ST7 BENEFITS VERSUS INDUSTRY STANDARD
OVERVIEW OF ENHANCED CAN CONTROLLERS FOR ST7 AND ST9 MCUS
U435 CAN-DO SOLUTIONS FOR CAR MULTIPLEXING
BENCHMARK ST72 VS PC16
PERFORMANCE COMPARISON BETWEEN ST72254 & PC16F876
LIN (LOCAL INTERCONNECT NETWORK) SOLUTIONS
PRODUCT MIGRATION
AN1131
AN1322
AN1365
MIGRATING APPLICATIONS FROM ST72511/311/214/124 TO ST72521/321/324
MIGRATING AN APPLICATION FROM ST7263 REV.B TO ST7263B
GUIDELINES FOR MIGRATING ST72C254 APPLICATION TO ST72F264
PRODUCT OPTIMIZATION
163/166
ST7265x
IDENTIFICATION
AN 982
DESCRIPTION
USING ST7 WITH CERAMIC RENATOR
AN1014
HOW TO MINIMIZE THE ST7 POWER CONSUMPTION
AN1015
SOFTWARE TECHNIQUES FOR IMPROVING MICROCONTROLLER EMC PERFORMANCE
MONITORING THE VBUS SIGNAL FOR USB SELF-POWERED DEVICES
ST7 CHECKSUM SELF-CHECKING CAPABILITY
AN1040
AN1070
AN1324
CALIBRATING THE RC OSCILLATOR OF THE ST7FLITE0 MCU USING THE MAINS
EMULATED DATA EEPROM WITH XFLASH MEMORY
AN1477
AN1502
EMULATED DATA EEPROM WITH ST7 HDFLASH MEMORY
AN1529
EXTENDING THE CURRENT & VOLTAGE CAPABILITY ON THE ST7265 VDDF SUPPLY
ACCURATE TIMEBASE FOR LOW-COST ST7 APPLICATIONS WITH INTERNAL RC OSCIL-
LATOR
AN1530
PROGRAMMING AND TOOLS
AN 978
AN 983
AN 985
AN 986
AN 987
AN 988
AN 989
AN1039
AN1064
AN1071
AN1106
KEY FEATURES OF THE STVD7 ST7 VISUAL DEBUG PACKAGE
KEY FEATURES OF THE COSMIC ST7 C-COMPILER PACKAGE
EXECUTING CODE IN ST7 RAM
USING THE INDIRECT ADDRESSING MODE WITH ST7
ST7 SERIAL TEST CONTROLLER PROGRAMMING
STARTING WITH ST7 ASSEMBLY TOOL CHAIN
GETTING STARTED WITH THE ST7 HIWARE C TOOLCHAIN
ST7 MATH UTILITY ROUTINES
WRITING OPTIMIZED HIWARE C LANGUAGE FOR ST7
HALF DUPLEX USB-TO-SERIAL BRIDGE USING THE ST72611 USB MICROCONTROLLER
TRANSLATING ASSEMBLY CODE FROM HC05 TO ST7
PROGRAMMING ST7 FLASH MICROCONTROLLERS IN REMOTE ISP MODE (IN-SITU PRO-
GRAMMING)
AN1179
AN1446
AN1478
AN1527
AN1575
USING THE ST72521 EMULATOR TO DEBUG A ST72324 TARGET APPLICATION
PORTING AN ST7 PANTA PROJECT TO CODEWARRIOR IDE
DEVELOPING A USB SMARTCARD READER WITH ST7SCR
ON-BOARD PROGRAMMING METHODS FOR XFLASH AND HDFLASH ST7 MCUS
164/166
ST7265x
16 SUMMARY OF CHANGES
Description of the changes between the current release of the specification and the previous one.
Revision
Main changes
Date
Added TQFP48 and SO34 packages
Changed device summary
Changed section 4.4 on page 22: “and the device can be reprogrammed” added
Added Section 4.7 “Related Documentation” on page 24
Changed section 7 on page 41: removed reference to EICR register (ISx bits are in the
MISCR1 and MISCR3 registers and not in the EICR register).
Changed section 9.1 on page 49: added an important note
Changed section 9.2.4 on page 53: removed references to a second solution when using bit
manipulation
Changed section 9.4 on page 54: modified description of D[7:0] bits
Added text specifying that the watchdog counter is a free-running downcounter: Section
11.1.2 and section 11.1.3 on page 58
Added the following tables: “FLASH Register Map and Reset Values” on page 24, “Miscel-
laneous Register Map and Reset Values” on page 57 and “16-Bit Timer Register Map and
Reset Values” on page 91
2.3
June 03
Added Section 11.3.5 and section 11.3.6 on page 70
Removed reference to PWM mode and One Pulse mode in the description of OLVL2 and
OCIE bits in section 11.4.6 on page 88
Updated section 11.6.5.4 on page 104 (removed reference to multimaster system)
Removed reference to BUSY flag in section 11.7.2 on page 109
Removed reference to BUSY bit and BERR bit in Table 34, “I2C Register Map,” on page 117
Added Section 11.7.5 and section 11.7.6 on page 113
Changed section 13.3.1 on page 130 and Figure 74
Changed section 13.7.1 on page 137 and added section 13.7.2 on page 138
Changed section 14 on page 156
Updated description of option byte 0 (section 15.1 on page 159)
Changed section 15.2 on page 160 and section 15.3 on page 162
Please read carefully Section 9 I/O PORTS
165/166
ST7265x
Notes:
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
2003 STMicroelectronics - All Rights Reserved.
Purchase of I2C Components by STMicroelectronics conveys a license under the Philips I2C Patent. Rights to use these components in an
I2C system is granted provided that the system conforms to the I2C Standard Specification as defined by Philips.
STMicroelectronics Group of Companies
Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan
Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A.
http://www.st.com
166/166
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