ST72681/R20 [STMICROELECTRONICS]
USB 2.0 high-speed Flash drive controller; USB 2.0高速闪存驱动器控制器
| 型号： | ST72681/R20 |
| 厂家： | 
ST |
| 描述： | USB 2.0 high-speed Flash drive controller |
| 文件： | 总32页 (文件大小：610K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ST72681
USB 2.0 high-speed Flash drive controller
Features
■ USB 2.0 interface compatible with mass
storage device class
– Integrated USB 2.0 PHYSupports USB
high speed and full speed
– Suspend and Resume operations
TQFP48 7x7
■ Clock management
– Integrated PLL for generating core and
USB 2.0 clock sources using an external
12 MHz crystal oscillator
■ Mass storage controller interface (MSCI)
– Supports all types of NAND Flash devices
including ST, Hynix, Samsung, Toshiba,
Micron, Renesas
■ Data protection
– Write protect switch control
– Public/private partitions support
– Reed-Solomon encoder/decoder on-the-fly
correction (4 bytes of a 512-byte block)
– Flash identification support
■ Production tool device configurability:
– Up to 12 MB/s for read and 8 MB/s for write
operations in single channel
– Up to 4 NAND devices supported in a
single channel
– USB vendor ID/product ID (VID/PID), serial
number and USB strings with foreign
language support
– SCSI strings
■ Embedded ST7 8-bit MCU
– One or two LED outputs
– Adjustable NAND Flash bus frequency to
reach highest performance
■ Supply management
– 3.3 V operation
■ Code update in the NAND Flash memory
– Integrated 3.3-1.8 V voltage regulator
®
■ TQFP48 7x7 ECOPACK package
■ USB 2.0 low-power device compliant
– Less than 100 mA during write operation
with two NAND Flash devices
– Less than 500 µA in suspend mode
■ AutoRun CDROM partition support
■ Bootability support (HDD mode)
■ Development support
– Complete reference design including
schematics, BOM and gerber files
■ Supports Windows (Vista, XP, 2000, ME),
Linux and MacOS. Drivers available for
Windows 98 SE
Table 1.
Device summary
Features
Orderable part numbers
ST72681/R20
ST72681/R21
USB interface
USB 2.0 high speed
Number of NAND devices supported (1)
up to 1
up to 4
R/W speed
11MB/s and 7MB/s
12MB/s and 8MB/s
Operating voltage
3.0 to 3.6 V
0 to +70 °C
Operating temperature
Package
TQFP48 7x7 / Die form
1. Number of NAND devices supported in a single channel.
August 2007
Rev 5
1/32
www.st.com
1
Contents
ST72681
Contents
1
2
3
4
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Application schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
NAND interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.1
4.2
NAND support table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
NAND error correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.2.1
4.2.2
Hardware error correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Firmware error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.3
Management of bad NAND blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.3.1
4.3.2
4.3.3
Bad block identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Bad block replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Late fail block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.4
4.5
Wear levelling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.4.1
LUT usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
NAND interface configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5
Mass storage implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1
5.2
USB characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
BOT / SCSI implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.2.1
5.2.2
5.2.3
BOT specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
SCSI specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Bootability specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.3
5.4
Multi-LUN device characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.3.1
5.3.2
5.3.3
5.3.4
Public drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Private drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Additional drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
CD-ROM considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Mass storage interface configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6
Human interface implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.1
6.2
LED behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Read only switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2/32
ST72681
Contents
7.1
7.2
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.1.1
7.1.2
7.1.3
7.1.4
7.1.5
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.2.1
7.2.2
7.2.3
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.3
7.4
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.3.1
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.4.1
7.4.2
RUN and SUSPEND modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Supply and clock managers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.5
7.6
Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.5.1
7.5.2
General timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.6.1
7.6.2
7.6.3
Functional EMS (electro magnetic susceptibility) . . . . . . . . . . . . . . . . . 20
Electromagnetic interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 21
7.7
I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.7.1
7.7.2
General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.8
7.9
Control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.8.1
Asynchronous RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Other communication interface characteristics . . . . . . . . . . . . . . . . . . . . 26
7.9.1
7.9.2
MSCI parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Universal serial bus interface (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Device ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
9
10
3/32
Introduction
ST72681
1
Introduction
The ST72681 is a USB 2.0 high-speed Flash drive controller. The USB 2.0 high-speed
interface including PHY and function supports USB 2.0 mass storage device class.
The mass storage controller interface (MSCI) combined with the Reed-Solomon
encoder/decoder on-the-fly correction (4-byte on 512-byte data blocks) provides a flexible,
high transfer rate solution for interfacing a wide of range NAND Flash memory device types.
The internal 60 MHz PLL driven by the 12 MHz oscillator is used to generate the 480 MHz
frequency for the USB 2.0 PHY.
The ST7 8-bit CPU runs the application program from the internal ROM and RAM. USB data
and patch code are stored in internal RAM.
I/O ports provide functions for EEPROM connection, LEDs and write protect switch control.
The internal 3.3 to 1.8 V voltage regulator provides the 1.8 V supply voltage to the digital
part of the circuit.
Figure 1.
Device block diagram
8-bit
CPU
12 MHz
OSC
ROM
RAM
Mass
Storage
Controller
Interface Correction
Reed-
NAND
I/F
USB 2.0
Function
USB 2.0
PHY
Solomon
Error
3.3 V to 1.8 V
voltage
GPIO
regulator
4/32
ST72681
Pin description
2
Pin description
Figure 2 shows the TQFP48 package pinout, while Table 2, Table 3, Table 4, and Table 5
give the pin description.
The legend and abbreviations used in these tables are the following:
●
Type
–
–
–
I = input
O = output
S = supply
●
●
Input level: A = Dedicated analog input
In/Output level
–
–
C = CMOS 0.3V /0.7V with input trigger
T DD DD
T = TTL 0.8V / 2V with Schmitt trigger
T
●
Output level
–
–
–
D8 = 8mA drive
D4 = 4mA drive
D2 = 2mA drive
Figure 2.
48-pin TQFP package pinout
48 47 46 45 44 43 42 41 40 39 38 37
36
NAND WP
READ ONLY
EEPROM SCL
VSS_2
1
2
3
4
5
6
7
8
9
10
VDDA
OSCIN
OSCOUT
VSSA
35
34
33
32
31
30
29
28
27
26
25
RREF
VDD33_2
NC(1)
VSSC
ST72681
VDDC
NC(1)
VDD3
RESET
LED2
LED1
USBDP
USBDM
VSSBL
VDDBL
11
12
NAND ALE/EEPROM SDA
VSS_3
24
13 14 15 16 17 18 19 20 21 22 23
1. Must remain NOT connected in the application.
5/32
Pin description
ST72681
Table 2.
Power supply
Pin name
Pin
Description
48
47
33
32
25
24
14
15
13
VSS_1
VDD33_1
VSS_2
S
S
S
S
S
S
S
S
S
Ground
I/Os and regulator supply voltage
Ground
VDD33_2
VSS_3
I/Os and regulator supply voltage
Ground
VDD33_3
VSS_4
I/Os and regulator supply voltage
Ground
VDD33_4
VDDOUSB
I/Os and regulator supply voltage
USB2 PHY, OSC and PLL power supply output (1.8 V)
Table 3.
Pin
USB 2.0 interface
Pin name
Description
12
11
10
9
VDDBL
VSSBL
USBDM
USBDP
VDD3
S
S
Supply voltage for buffers and deserialization flip flops (1.8 V)
Ground for buffers and deserialization flip flops (1.8 V)
I/O USB2 DATA -
I/O USB2 DATA +
8
S
S
S
Supply voltage for the FS compliance (3.3 V)
7
VDDC
Supply voltage for DLL & XOR tree (1.8 V)
Ground for DLL & XOR tree (1.8 V)
6
VSSC
Ref. resistor for integrated impedance process adaptation
(11.3 kOhms 1% pull down)
5
RREF
I/O
Table 4.
Pin
USB 2.0 and core clock system
Pin name
Description
4
3
2
1
VSSA
S
O
I
Ground for osc & PLL (1.8 V)
OSCOUT
OSCIN
VDDA
12 MHz oscillator output
12 MHz oscillator input
S
Supply voltage for osc & PLL (1.8 V)
6/32
ST72681
Pin description
Table 5.
General Purpose I/O Ports / Mass Storage I/Os
Level
Main function
(after reset)
Pin name
45
44
43
42
41
40
39
38
26
22
21
20
19
18
17
16
37
36
35
34
28
27
NAND D[0]
NAND D[1]
NAND D[2]
NAND D[3]
NAND D[4]
NAND D[5]
NAND D[6]
NAND D[7]
NAND ALE
NAND CLE
NAND WE
NAND RE
NAND CE1
NAND CE2
NAND CE3
NAND CE4
NAND RnB
NAND WP
READ ONLY
EEPROM SCL
LED2
I/O TT D4 NAND Data [0]
I/O TT D4 NAND Data [1]
I/O TT D4 NAND Data [2]
I/O TT D4 NAND Data [3]
I/O TT D4 NAND Data [4]
I/O TT D4 NAND Data [5]
I/O TT D4 NAND Data [6]
I/O TT D4 NAND Data [7]
I/O TT D8 NAND Address Latch Enable
O
O
O
O
O
O
O
I
TT D8 NAND Command Latch Enable
TT D8 NAND WRite Enable
TT D8 NAND read enable
TT D4 NAND Chip Enable 1
TT D4 NAND Chip Enable 2
TT D4 NAND Chip Enable 3
TT D4 NAND Chip Enable 4
TT D2 NAND Ready/Busy
TT D2 NAND Write Protect
O
I
TT D2 Read -only switch (“0”: Read/Write; “1”: Read only)
TT D2 EEPROM serial clock
O
O
O
TT D8 Green LED (USB access)
LED1
TT D8 Red LED (NAND memory access)
7/32
Application schematics
ST72681
3
Application schematics
Figure 3.
Application schematic
V33
USB_V5
On BoardFlash1
On BoardFlash2
U1
1
2
3
5
Vi
n
Vout
GND
C4
4.7uF
4
+
V33
V33
INHIBIT BYPASS
LD3985M33R_SOT23-5L
C3
C5
10nF
220nF
UU1
Decoupling capacitor
s
to
be located close
V33
to U2,U3,U4& U5 V33 inputs
3
2
U2
U3
Vin
Vout
GND
C18
100nF
C19
100nF
C20
100nF
C21
100nF
AME8800_SOT23
NAND_W
P
NAND_WP
R_Toshiba_config
R7
NAND_RnB2
0
V33
V33
R_Multi_CE_config
R8
R_Single_CE_config
R9
R_Dual_CE_config
0
NAND_CE2
0
NAND_CE3
R10
0
V33
Decoupling capacitors to be located close to U1 V33 inputs
On BoardFlash3
On BoardFlash4
V33
R3
4.7K
C6
10nF
C7
10nF
C8
10nF
C9
10nF
C10
10nF
V33
V33
NAND_RnB
V33
R4
10K
V18_USB
XT1
V18_USB
U4
U5
U?
ST72681_QFP48
C15
4
2
1
C16
18pF
18pF
3
S1
CRYSTAL 12MH_NX4025DA
R6
1
2
3
4
5
6
7
8
9
36
VDDA
NAND W P
READ ONL Y
EEPROM SCL
VSS_2
VDD33_2
NC
NC
RESET
LED2
LED1
NAND ALE
VSS_3
35
34
33
32
31
30
29
28
27
26
25
RO
OSCIN
OSCOUT
VSSA
RREF
VSSC
Read Only
500
R5
V33
C17
11.3K 1%
VDDC
RESET
NAND_W
LED1
P
NAND_WP
V33
VDD3
USBDP
USBDM
VSSBL
VDDBL
DP
DM
USB_V5
10
11
12
100nF
R1
LED2
V33
V33
220
GREEN
LED2
LED
C1
C2
R2
LED1
V33
100nF
1uF
220
RED LED
V18_USB
On Board Flash 2-4 only available on ST72681 /R21
C14
10nF
C13
10nF
C12
10nF
C11
470nF
J1
1
2
3
4
VBUS
D-
D+
GND
V33
V33
USB CON
ST72681/R20 only supports single NAND Flash Chip Enable configuration (one NAND
device with one Chip Enable signal). Note that pins NAND_RnB2, NAND_CE2, NAND_CE3
and NAND_CE4 should remain unconnected.
ST72681/R21 can support up to four NAND Flash Chip Enable signals. The application can
use one of the following configurations:
●
One NAND device with four Chip Enable signals; NAND_CE1, NAND_CE2,
NAND_CE3 and NAND_CE4 are used.
●
One NAND device with two Chip Enable signals; NAND_CE1 and NAND_CE2 are
used.
●
●
One NAND device with one Chip Enable signal; only NAND_CE1 is used.
Two NAND devices with two Chip Enable signals; NAND_CE1 and NAND_CE2 are
used to select the first NAND device and NAND_CE3 and NAND_CE4 to select the
second NAND device.
●
●
Two NAND devices with one Chip Enable signal; NAND_CE1 and NAND_CE2 are
used to select is used to select the first NAND device and the 2nd NAND device,
respectively.
4 NAND devices with 1Chip Enable signal; NAND_CE1 selects the first NAND device,
NAND_CE2 the 2nd NAND device, NAND_CE3 to select the third, and NAND_CE4 to
select the fourth NAND device.
8/32
ST72681
NAND interface
4
NAND interface
4.1
NAND support table
Table 6.
Known NAND compatibility guide for R20 and R21 devices
Number of NAND devices
supported
NAND size (Mbytes or Gbytes)
and type
NAND name
R20 device
R21 device
Samsung K9F1G08U
Samsung K9F2G08U
Samsung K9F4G08U
Samsung K9K4G08U
Samsung K9W4G08U
Samsung K9K8G08U
Samsung K9W8G08U
Samsung K9WAG08U
Samsung K9NBG08U
Samsung K9G4G08U
Samsung K9L8G08U
Samsung K9HAG08U
Samsung K9MBG08U
Toshiba TH58NVG0S3
Toshiba TH58NVG1S3
Toshiba TH58NVG2S3
Toshiba TH58NVG1D4
Toshiba TH58NVG2D4
Toshiba TH58NVG3D4
ST NAND01GW3B
128 MB; SLC2K; Single CE
256 MB; SLC2K; Single CE
512 MB; SLC2K; Single CE
512 MB; SLC2K; Single CE
512 MB; SLC2K; Dual CE
1 GB; SLC2K; Single CE
1 GB; SLC2K; Dual CE
1
1
1
1
-
1, 2, 3 or 4
1, 2, 3 or 4
1, 2, 3 or 4
1, 2, 3 or 4
1 or 2
1
-
1, 2, 3 or 4
1 or 2
2 GB; SLC2K; Dual CE
-
1 or 2
4 GB; SLC2K; Quad CE
512 MB; MLC2K; Single CE
1 GB; MLC2K; Single CE
2 GB; MLC2K; Dual CE
-
1
1
1
-
1, 2, 3 or 4
1, 2, 3 or 4
1 or 2
4 GB; MLC2K; Quad CE
128 MB; SLC2K; Single CE
256 MB; SLC2K; Single CE
512 MB; SLC2K; Single CE
256 MB; MLC2K; Single CE
512 MB; MLC2K; Single CE
1 GB; MLC2K; Single CE
128 MB; SLC2K; Single CE
256 MB; SLC2K; Single CE
512 MB; SLC2K; Single CE
1 GB; SLC2K; Single CE
512 MB; MLC2K; Single CE
128 MB; SLC2K; Single CE
256 MB; SLC2K; Single CE
512 MB; SLC2K; Single CE
512 MB; SLC2K; Dual CE
1 GB; SLC2K; Single CE
512 MB; MLC2K; Single CE
1 GB; MLC2K; Dual CE
-
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
-
1, 2, 3 or 4
1, 2, 3 or 4
1, 2, 3 or 4
1, 2, 3 or 4
1, 2, 3 or 4
1, 2, 3 or 4
1, 2, 3 or 4
1, 2, 3 or 4
1, 2, 3 or 4
1, 2, 3 or 4
1, 2, 3 or 4
1, 2, 3 or 4
1, 2, 3 or 4
1, 2, 3 or 4
1 or 2
ST NAND02GW3B
ST NAND04GW3B
ST NAND08GW3B
ST NAND04GW3C
Hynix HY27UF081G2M
Hynix HY27UG082G2M
Hynix HY27UG084G2M
Hynix HY27UH084G5M
Hynix HY27UH088G2M
Hynix HY27UT084G2M
Hynix HY27UU088G5M
Micron 29F2G08AA
1
1
-
1, 2, 3 or 4
1, 2, 3 or 4
1 or 2
256 MB; SLC2K; Single CE
512 MB; SLC2K; Single CE
1 GB; SLC2K; Dual CE
1
1
-
1, 2, 3 or 4
1, 2, 3 or 4
1 or 2
Micron 29F4G08BA
Micron 29F8G08FA
Note:
This list is provided as a guide only as it is not possible to automatically guarantee support
for all the additions and updates across the listed ranges of manufacturers’ devices.
9/32
NAND interface
ST72681
4.2
NAND error correction
No NAND Flash memory arrays are guaranteed by manufacturers to be error-free. Error
occurrence depends on the Flash cell type (MLC or SLC).
The ST72681 embeds hardware and firmware mechanisms to correct the errors.
4.2.1
Hardware error correction
The ST72681 embeds a Reed-Solomon algorithm-based hardware cell. This cell directly
manages 512-byte data packets on the NAND I/O system.
Based on a data packet contents, the cell generates an 80-bit Error Correction Code (ECC)
consisting of 8 words each containing 10 bits.
During write operations to NAND memory, the 512-bytes of data and the ECC are stored
together in the same page. The ECC is stored in the corresponding Redundant Area (RA),
using 10 bytes.
During read operations, the 512-bytes of data and the 8 ECC words are read back and are
passed through the Reed-Solomon cell for decoding. The cell allows the correction of 4
symbols in this 520-symbol packet (512 symbols from data + 8 symbols from ECC).
The hardware cell gives 3 possible results:
■ No error detected: the data packet can be used as it is.
■ Correctable error detected: the corrected data are available in a specific 512-byte buffer
in the Reed-Solomon cell and are ready to use.
■ Uncorrectable error detected: data corruption is not repairable.
4.2.2
Firmware error management
The firmware defines the error correction possibilities with the corrected data packet.
When data is not repairable, the block is considered as bad and replaced by another one.
See below for further information.
4.3
Management of bad NAND blocks
NAND device manufacturers deliver their products with factory-marked bad blocks. This
marking depends on the manufacturer and the NAND type (page size, memory technology,
etc.). The ST72681 supports all bad block markings currently available on the market.
4.3.1
Bad block identification
During firmware initialization, the MCU scans the entire NAND configuration to identify bad
blocks.
A bad block is defined as follows:
■ 5 different Block Status bytes are considered: 4 Status bytes from page 0 and 1 from an
other page (page 127 for MLC NAND; page 1 for SLC NAND).
■ The considered block is declared bad if 1 of these 5 bytes contains 4 bits or more at 0.
10/32
ST72681
NAND interface
4.3.2
Bad block replacement
The firmware works with groups of 1024 blocks, called zones. A complete NAND
configuration can contain several zones.
Each zone is described in a Look Up Table (LUT) containing 1024 entries. A LUT is
composed of 3 parts: used blocks, free blocks and bad blocks.
●
●
●
The “bad blocks” part contains as many entries as the number of bad blocks identified
in that zone.
The “used blocks” part can have a size of 1000, 900 or 500 entries. This size is
configurable and also depends on the number of identified bad blocks.
The “free blocks” part contains the remaining entries.
The used blocks part is used to do a correspondence between NAND blocks and logical
address ranges.
This system allows all bad blocks to be masked from the Host. As a result, bad blocks are
never seen. Only a range of logical addresses are visible which correspond to the sum of
the used blocks part of all zones.
4.3.3
4.4
Late fail block
During normal application life, defects can appear in the NAND memory. Under certain
conditions, these defects are not correctable and the corresponding block is declared as
“bad”.
In this case, new bad blocks are identified in the bad blocks part of the LUT and replaced by
new blocks from the “free blocks” part.
Wear levelling
During normal application life, the NAND is written and erased (by block) many times. The
NAND device is guaranteed for a limited number of writes (about 100 000 cycles). As a
consequence, the controller must keep write/erase operations to a minimum for any
individual block.
A method to limit these cycles is to use a “Wear Levelling” scheme between all NAND
blocks.
4.4.1
LUT usage
The LUT is used for transfers between a logical address range and a block. It contains free
blocks which are used in the “wear levelling” scheme.
During write command treatment, the firmware calculates the zones, blocks and pages for
data write access. In a block write operation, the firmware applies the following scheme to
avoid block wearing:
●
●
●
●
●
The least recently-used block is chosen from the free block part of the LUT.
Valid data from the old block is copied to the new block.
New data from the write command is written to the new block.
The old block is erased.
The LUT is updated after identifying the new block in the used block part and the old
block in the free block part.
11/32
NAND interface
ST72681
Using this scheme, a logical address range doesn’t correspond to a constant block. A write
command repeated several times to the same logical address writes physically into different
blocks.
This method shares the wearing evenly across all blocks of the concerned zone.
4.5
NAND interface configuration
Applications based on ST72681 can be configured through a dedicated PC software tool.
The NAND RE and WE signals frequencies can be independently configured to 30 MHz, 20
MHz, 15 MHz, 12 MHz and 10 MHz.
The logical size reduction factor can be configured to 90% or 50% in the event of having too
many bad blocks. this option resizes the used blocks part of the LUT to 900 or 500.
12/32
ST72681
Mass storage implementation
5
Mass storage implementation
5.1
USB characteristics
The ST72681 is compliant with USB 2.0 specification.
It is able to operate in both high speed and full speed modes using a bidirectional control
endpoint 0 and a bidirectional bulk endpoint 2.
It automatically recognizes the speed to use on the bus by a process of negotiation with
USB Host.
5.2
BOT / SCSI implementation
5.2.1
BOT specification
The USB Mass Storage Class Bulk Only Transport (BOT) specification version 1.0 is
implemented. It allows the device to be recognized by the host as a mass-storage USB
device.
5.2.2
5.2.3
SCSI specification
Moreover, inside BOT transfers, SCSI commands are encapsulated for mass storage
operations.
The related specifications are SBC-2 revision 10 (SCSI Block Commands 2) and SPC-4
revision 7a (SCSI Primary Commands 4).
Bootability specification
The USB Mass Storage Specification for Bootability revision 1.0 is implemented.
It allows the PC host to boot the operating system from the USB mass storage application.
In this case, the Host uses BOT LUN 0 (logical unit number).
A specific tool must be used to format the logical drive in order to make it bootable by
programming the correct information.
5.3
Multi-LUN device characteristics
The application can be configured with a dedicated PC software tool as a multi-LUN device.
In this case, up to 3 different drives are available: public drive, additional drive and private
drive.
Public and additional drives can be configured as removable drive, hard disk drive or CD-
ROM drive.
13/32
Mass storage implementation
ST72681
5.3.1
Public drive
The public drive is the default configuration in a mono-LUN mode. In this default case, it is
declared as a removable drive.
The public drive is mandatory and can not be removed from the configuration. By
customization (using PC software), it can be declared as a removable drive, a CD-ROM
drive or a hard disk drive.
This drive is the LUN 0 in BOT commands.
5.3.2
Private drive
The Private drive is optional. Its type is “removable drive” and is not configurable.
This drive is protected by password and cannot be directly accessed through the PC
operating system. A PC software tool is necessary to send a command with the password to
unlock the device. The device is then open and accessible by the PC operating system until
reset or reception of a new command to lock the drive.
This drive is the LUN 1 in BOT commands.
5.3.3
5.3.4
Additional drive
The additional drive is optional. Its type can be “removable drive”, “hard disk drive” or “CD-
ROM drive”.
This drive is LUN 1 in BOT commands if the private drive option is not active, and is LUN 2 if
the private drive option is active.
CD-ROM considerations
When a drive is declared as CD-ROM, the ST72681/R21 manages this drive with a logical
block size of 2 Kbytes. To be correctly recognized by the host, it is preferable to build a
CDFS partition on this CD-ROM. See the ‘ST7268x Production Tool User Manual’ for more
information.
Note that the ST72681/R20 doesn’t consider the CD-ROM partition as a specific case. The
logical block size is 512 bytes and any file system can be used.
In both cases, the CD-ROM partition allows the use of the autorun operating system feature.
During device connection, the CD-ROM partition is recognized and the host tries to run the
application corresponding to the ‘autorun.inf’ file present into this CD-ROM partition.
5.4
Mass storage interface configuration
In addition to the parameters already described as configurable in the previous chapters,
additional customizable information includes:
●
USB parameters: VID, PID, all string information
SCSI parameters: strings for inquiry commands
●
14/32
ST72681
Human interface implementation
6
Human interface implementation
6.1
LED behavior
The application is designed to manage 2 LEDs. This behavior is configurable through PC
dedicated software: ‘ST7268x Production Tool’.
By default, LED 1 responds to NAND access activity and LED 2 responds to USB activity.
Use of LED 1 is optional. When this option is not active, LED 2 reacts to both USB and
NAND activity.
6.2
Read only switch
The READ ONLY pin of the ST72681 is an input pin to be connected to VDD or GND
depending on the behavior of the device.
●
When this pin is connected to GND, no limitations are applied on the PC command
received.
●
When this pin is connected to VDD or unconnected, the firmware filters all accesses to
the NAND which modify the NAND state (write, erase, etc.) and returns an error to the
PC.
15/32
Electrical characteristics
ST72681
7
Electrical characteristics
7.1
Parameter conditions
Unless otherwise specified, all voltages are referred to V
.
SS
7.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the Devices with an ambient temperature at T = 25°C and T =T max (given by the
A
A
A
selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean 3Σ).
7.1.2
7.1.3
7.1.4
Typical values
Unless otherwise specified, typical data are based on T = 25°C and V
given only as design guidelines and are not tested.
= 3.3V. They are
DD33
A
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 4.
Figure 4.
Pin loading conditions
DEVICE PIN
C
L
7.1.5
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 5.
Figure 5.
Pin input voltage
DEVICE PIN
V
IN
16/32
ST72681
Electrical characteristics
7.2
Absolute maximum ratings
Stresses above those listed as “absolute maximum ratings” may cause permanent damage
to the Device. This is a stress rating only and functional operation of the Device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
7.2.1
Voltage characteristics
Table 7.
Symbol
Voltage characteristics
Ratings
Maximum value Unit
VDD33 - VSS
Supply voltage
4.0
V
V
V
SS - 0.3 to
VDD33 + 0.3
(1) (2)
VIN
Input voltage on any other pin
VESD(HBM)
VESD(MM)
Electro-static discharge voltage (Human Body Model)
Electro-static discharge voltage (Machine Model)
See Section 7.6.3 on
page 21
1. Directly connecting the RESET and I/O pins to VDD33 or VSS could damage the device if an unintentional
internal reset is generated or an unexpected change of the I/O configuration occurs (for example, due to a
corrupted program counter). To guarantee safe operation, this connection has to be done through a pull-up
or pull-down resistor (typical: 4.7kΩ for RESET, 10kΩ for I/Os). For the same reason, unused I/O pins must
not be directly tied to VDD33 or VSS
.
2. When the current limitation is not possible, the VIN absolute maximum rating must be respected, otherwise
refer to IINJ(PIN) specification. A positive injection is induced by VIN > VDD33 while a negative injection is
induced by VIN < VSS
.
7.2.2
Current characteristics
Table 8.
Symbol
IVDD33
IVSS
Current characteristics
Ratings
Maximum value Unit
Total current into VDD33 power lines (source) (1)
Total current out of VSS ground lines (sink) (1)
Output current sunk by any I/O (type D2)
Output current sunk by any I/O (type D4)
Output current sunk by any I/O (type D8)
Output current source by any I/Os and control pin
200
200
25
mA
35
(2)
IIO
50
-25
1. All power supply (VDD33) and ground (VSS) lines must always be connected to the external supply.
2. Refer to Table 5: General Purpose I/O Ports / Mass Storage I/Os for the output drive capability of each of
the I/Os.
7.2.3
Thermal characteristics
Table 9.
Symbol
Thermal characteristics
Ratings
Value
Unit
TSTG
Storage temperature range
-65 to +150
120
°C
°C
TJMAX
Maximum junction temperature
17/32
Electrical characteristics
ST72681
7.3
Operating conditions
7.3.1
General operating conditions
Table 10. General operating conditions
Symbol
Parameter
Conditions
Min
Max
Unit
fCPU
VDD33
TA
Internal clock frequency
Power supply
0
3.0
0
30
3.6
70
MHz
V
Ambient temperature range
°C
Figure 6.
Guaranteed functionality range
fCPU [MHz]
FUNCTIONALITY
GUARANTEED
IN THIS AREA
30
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
15
6
3
SUPPLY VOLTAGE [VDD33
]
0
3.3
2.7
2.0
2.5
3.0
3.6
7.4
Supply current characteristics
7.4.1
RUN and SUSPEND modes
Table 11. RUN and SUSPEND modes
Symbol
Parameter
Conditions
Min. Typ. Max. Unit
Supply current in RUN mode
fOSC = 12 MHz
15
25
90
35
mA
µA
IDD
Supply current in SUSPEND mode VDD33 = 3.3V, TA = +25°C 60
190
7.4.2
Supply and clock managers
Table 12. Supply and clock managers
Symbol
Parameter
Conditions
Typ. (1) Max. (2)
Unit
µA
IDD(CK) Supply current of crystal oscillator (3)
1000
2000
1. Typical data are based on TA = 25°C and fCPU = 12 MHz.
2. Not tested in production, guaranteed by characterization.
3. Data based on characterization results done with the external components specified in Section 7.5.2:
Crystal oscillator, not tested in production.
18/32
ST72681
Electrical characteristics
7.5
Clock and timing characteristics
Subject to general operating conditions for V
, f
, and T .
DD33 OSC A
7.5.1
General timings
Table 13. General timing characteristics
Symbol
Parameter
Conditions
Min. Typ. (1) Max.
Unit
2
3
12
800
22
tCPU
ns
tc(INST) Instruction cycle time
fCPU = 15 MHz
fCPU = 12 MHz
133
10
200
Interrupt reaction time (2)
tv(IT)
tCPU
µs
tv(IT) = Δtc(INST) + 10
0.666
1.466
1. Data based on typical application software.
2. Time measured between interrupt event and interrupt vector fetch. Δtc(INST) is the number of tCPU cycles
required to finish executing the current instruction.
7.5.2
Crystal oscillator
The ST72681 internal clock is supplied from a crystal oscillator. All the information given in
this paragraph are based on characterization results with specified typical external
components. In the application the load capacitors have to be placed as close as possible to
the oscillator pins in order to minimize output distortion and start-up stabilization time. Refer
to the crystal manufacturer for more details (frequency, package, accuracy...).
Table 14. Crystal oscillator characteristics
Symbol
Parameter
Conditions
Min. Typ. Max. Unit
fOSC
Oscillator frequency
12
MHz
ppm
%
CKACC
αOSC
Total crystal oscillator accuracy abs. value + temp + aging
Crystal oscillator duty cycle (1)
60
55
45
50
1. The crystal oscillator duty cycle has to be adjusted through the two CL capacitors. Refer to the crystal
manufacturer for more details.
Figure 7.
Typical application with a crystal oscillator
C
V
L
DDA
OSCIN
CRYSTAL
C
L
OSCOUT
Device
(1)
R
sOscout
1. Depending on the crystal oscillator power dissipation, a serial resistor RsOscout may be added. Refer to the
crystal oscillator manufacturer for more details.
Table 15. Typical C and R values by crystal oscillator
L
S
Supplier
Typical crystal oscillator
CL (pF)
RsOscout (Ω)
NDK
AT51 or AT41
16
560
19/32
Electrical characteristics
ST72681
7.6
EMC characteristics
Susceptibility tests are performed on a sample basis during product characterization.
7.6.1
Functional EMS (electro magnetic susceptibility)
Based on a simple running application on the product (toggling 2 LEDs through I/O ports),
the product is stressed by two electromagnetic events until a failure occurs (indicated by the
LEDs).
■ ESD: Electro-Static Discharge (positive and negative) is applied on all pins of the device
until a functional disturbance occurs. This test conforms with the IEC 1000-4-2 standard.
■ FTB: A Burst of Fast Transient voltage (positive and negative) is applied to V
and
DD33
V
through a 100pF capacitor, until a functional disturbance occurs. This test conforms
SS33
with the IEC 1000-4-4 standard.
A device reset allows normal operations to be resumed. The test results are given in the
table below based on the EMS levels and classes defined in application note AN1709.
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
●
●
●
Corrupted program counter
Unexpected reset
Critical Data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the RESET pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Table 16. EMC characterization and optimization values
Level/
Symbol
Parameter
Conditions
Class
VDD33 = 3.3V, TA = +25°C, fOSC = 12 MHz
complies with IEC 1000-4-2
specifications
Voltage limits to be applied on any I/O
pin to induce a functional disturbance
VFESD
4B
Fast transient voltage burst limits to be
applied through 100pF on VDD33 and
VSS33 pins to induce a functional
disturbance
VDD33 = 3.3V, TA = +25°C, fOSC = 12 MHz
complies with IEC 1000-4-4
specifications
VFFTB
4A
20/32
ST72681
Electrical characteristics
7.6.2
Electromagnetic interference (EMI)
Based on a simple application running on the product (toggling 2 LEDs through the I/O
ports), the product is monitored in terms of emission. This emission test is in line with the
norm SAE J 1752/3 which specifies the board and the loading of each pin.
Table 17. Electromagnetic interference
Monitored
Frequency Band [fOSC@12 MHz]
Max vs.
Symbol Parameter
Conditions(1)
Unit
0.1 MHz to 30 MHz
30 MHz to 130 MHz
130 MHz to 1 GHz
SAE EMI Level
20
25
25
4
VDD33 = 3.3V, TA = +25°C,
Peak level complies with SAE J 1752/3
specifications
dBµV
-
SEMI
1. Refer to Application Note AN1709 for data on other package types.
7.6.3
Absolute maximum ratings (electrical sensitivity)
Based on three different tests (ESD, LU and DLU) using specific measurement methods, the
product is stressed in order to determine its performance in terms of electrical sensitivity.
For more details, refer to the application note AN1181.
Electro-static discharge (ESD)
Electro-Static Discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts*(n+1) supply pin). This test
conforms to the JESD22-A114A/A115A standard.
Table 18. Absolute Maximum Ratings
Symbol
Ratings
Conditions
Max.(1) Unit
2000
VESD(HBM) Electro-static discharge voltage (Human Body Model) TA = +25°C
V
1. Data based on characterization results, not tested in production.
Static and dynamic latch-up
■ LU: 3 complementary static tests are required on 10 parts to assess the latch-up
performance. A supply overvoltage (applied to each power supply pin) and a current
injection (applied to each input, output and configurable I/O pin) are performed on each
sample. This test complies with EIA/JESD 78 IC latch-up specifications. For more details,
refer to the application note AN1181.
■ DLU: Electro-static discharges (one positive then one negative test) are applied to each
pin of 3 samples when the micro is running to assess the latch-up performance in dynamic
mode. Power supplies are set to the typical values, the oscillator is connected as near as
possible to the pins of the micro and the component is put in reset mode. This test
complies with IEC1000-4-2 and SAEJ1752/3 specifications. For more details, refer to the
application note AN1181.
21/32
Electrical characteristics
ST72681
Table 19. Electrical sensitivity values
Symbol
Parameter
Conditions
Class (1)
LU
Static latch-up class
TA = +25°C
VDD33 = 3.3V, fOSC = 12 MHz, TA = +25°C
A
A
DLU
Dynamic latch-up class
1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the
JEDEC specifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B
Class strictly covers all the JEDEC criteria (international standard).
7.7
I/O port pin characteristics
7.7.1
General characteristics
Subject to general operating conditions for V
, f
, and T unless otherwise specified.
DD33 OSC A
Table 20. General I/O port pin characteristics
Symbol
Parameter
Conditions
Min.
Typ. Max. Unit
0.16 x
VDD33
VIL
Input low level voltage
V
TTL ports
0.85 x
VDD33
VIH
Vhys
IL
Input high level voltage
Schmitt trigger voltage hysteresis (1)
Input leakage current
400
mV
VSS ≤ VIN ≤ VDD33
standard I/Os
,
1
µA
VSS ≤ VIN ≤ VDD33
10
IL5V
5V tolerant input leakage current
VIN = 5V, 25°C
30
50
VDD33
3.3V
=
RPU
Weak pull-up equivalent resistor (2) VIN = VSS
32
75
kΩ
1. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested
in production.
2. The RPU pull-up equivalent resistor is based on a resistive transistor. This data is based on
characterization results, tested in production at VDD33 max.
Figure 8.
Typical V and V standard I/Os
IL
IH
Vil/Vih (V)
2.5
2
1.5
1
0.5
0
2.7 2.8 2.9
3
3.1 3.2 3.3 3.4 3.5 3.6
Vdd (V)
22/32
ST72681
Electrical characteristics
Figure 9.
Typical R vs. V
with V =V
PU
DD33 IN SS
I/Os pullup resistance
60
55
50
45
40
35
30
2.7
2.8
2.9
3
3.1
3.2
3.3
3.4
3.5
3.6
Vdd (V)
Figure 10. Two typical Applications with unused I/O Pin
V
DD33
10kΩ
Device
UNUSEDI/OPORTO PORT
10kΩ 1Ω
UNUSED I/O PORT
DeviceDevice
7.7.2
Output driving current
Subject to general operating conditions for V
, f
, and T unless otherwise specified.
DD33 OSC A
Table 21. Output driving current
Symbol
Parameter
Conditions
Min. Max. Unit
Output low level voltage for a D2 I/O pin when 8
pins are sunk at same time (see Figure 11)
IIO = 2 mA
300
Output low level voltage for a D4 I/O pin when 8
pins are sunk at same time (see Figure 12)
(1)
VOL
I
IO = 4 mA
400
500
600
600
600
mV
mV
Output low level voltage for a D8 I/O pin when 8
pins are sunk at same time (see Figure 13 )
IIO = 8 mA
IIO = 2 mA
Output high level voltage for a D2 I/O pin when 8
pins are sourced at same time (see Figure 14)
VDD33
-
Output high level voltage for a D4 I/O pin when 8
pins are sourced at same time (see Figure 15 )
IIO = 4 mA
(2)
VOH
Output high level voltage for a D8 I/O pin when 8
pins are sourced at same time (see Figure 16)
IIO = 8 mA
1. The IIO current sunk must always respect the absolute maximum rating specified in Section 7.2.2: Current
characteristics and the sum of IIO (I/O ports and control pins) must not exceed IVSS
.
2. The IIO current sourced must always respect the absolute maximum rating specified in Section 7.2.2:
Current characteristics and the sum of IIO (I/O ports and control pins) must not exceed IVDD33. True open
drain I/O pins do not have VOH
.
23/32
Electrical characteristics
Figure 11. Typical V at V
ST72681
= 3.3V (I/O D2)
DD33
OL
140
120
100
80
60
40
20
0
0
1
2
3
4
Iol (mA)
Figure 12. Typical V at V
= 3.3V (I/O D4)
OL
DD33
140
120
100
80
60
40
20
0
0
1
2
3
4
5
6
Iol (mA)
Figure 13. Typical V at V
= 3.3V (I/O D8)
DD33
OL
140
120
100
80
60
40
20
0
0
2
4
6
8
10
Iol (mA)
Figure 14. Typical V
-V vs. V
(I/O D2)
DD33 OH
DD33
200
150
100
50
0
0
1
2
3
4
Ioh (mA)
Figure 15. Typical V
-V vs. V
(I/O D4)
DD33 OH
DD33
180
160
140
120
100
80
60
40
20
0
0
1
2
3
4
5
6
Ioh (mA)
24/32
ST72681
Electrical characteristics
Figure 16. Typical V
-V vs. V
(I/O D8)
DD33
DD33 OH
180
160
140
120
100
80
60
40
20
0
0
2
4
6
8
10
Ioh (mA)
7.8
Control pin characteristics
7.8.1
Asynchronous RESET pin
T = 0 to +55 °C unless otherwise specified.
A
Table 22. RESET pin characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
0.16 x
VDD33
VIL
Input low level voltage (1)
V
0.85 x
VDD33
VIH
Input high level voltage
Vhys
Schmitt trigger voltage hysteresis1)
450
40
mV
VDD33 = 3.3V
20
2.5
500
80
RON
Pull-up equivalent resistor
kΩ
VDD33 = 2V
100
teh(RSTL) External reset pulse hold time (2)
tg(RSTL) Filtered glitch duration (3)
tew(RSTL) External reset pulse duration (4)
µs
ns
200
µs
tiw(RSTL) Internal reset pulse duration
2
tCPU
1. The level on the RESET pin must be free to go below the VIL max. level specified in Section 7.8.1:
Asynchronous RESET pin. Otherwise the reset will not be taken into account internally.
2. To guarantee the reset of the Device, a minimum pulse has to be applied to the RESET pin. All short
pulses applied on RESET pin with a duration below teh(RSTL) can be ignored. Not tested in production,
guaranteed by design.
3. The reset network protects the device against parasitic resets.
4. The external reset duration must respect this timing to guarantee a correct start-up of the internal regulator
at power-up. Not tested in production, guaranteed by design.
Figure 17. Typical R on RESET pin
ON
100
90
80
70
60
50
40
2
2.5
3
3.5
Vdd (V)
25/32
Electrical characteristics
ST72681
7.9
Other communication interface characteristics
7.9.1
MSCI parallel interface
Figure 18. Timing diagrams for input mode (with max load on CTRL signal = 50 pF)
CTRL
external
DATA
DATA(i)
DATA(i+1)
ext device
t
DS
t
is the setup time for data sampling
DS
Figure 19. Timing diagrams for output mode (with max CTRL signal = 50 pF, DATA)
CTRL
external
DATA
external
DATA(i)
DATA(i+1)
t
DO
t
is the data output time for data sampling
DO
Table 23. MSCI Parallel Interface: DC Characteristics
Symbol
Parameter
Conditions
Min.
Typ. (1)
Max.
Unit
tDS
tDO
CCTRL
CDATA
Data Setup Time
Data Output time
11
6
ns
ns
pF
pF
CTRL line capacitance
Data line capacitance
50
50
1. Data based on design simulation and not tested in production.
26/32
ST72681
Electrical characteristics
7.9.2
Universal serial bus interface (USB)
Table 24. DC characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max. Unit
V
DD33 = 3.3V, Powerdown
IDDsuspend Suspend current
Pull-up resistor (2)
Full speed mode
VTERM Termination voltage
VOH
60
90
190
uA
mode, 25°C (1)
RPU
1.5
kΩ
0.8
2.8
2.0
3.6
0.8
2.0
V
V
V
V
High level output voltage
Low level output voltage
Crossover voltage
VOL
VCRS
1.3
High speed mode
VHSOH HS data signalling high
VHSOL HS data signalling low
400
5
mV
mV
1. The values provided do not take into account the current through both the 1.5kΩ pull-up resistor (on the
device-side) and the 15kΩ pull-down resistor (on the host-side).
2. Not tested in production, guaranteed by characterization.
Table 25. Timing characteristics
Symbol
Parameter
Conditions
Min.
Max.
Unit
Full speed mode
tFR
tFF
High speed mode
tHSR Rise time
tHSF Fall time
tHSDRAT HS data rate
Rise time
CL= 50 pF
CL= 50 pF
4
4
20
20
ns
ns
Fall time
500 (1)
500 (1)
480.24
ps
ps
479.76
Mb/s
1. Not tested in production, guaranteed by characterization.
Table 26. USB High Speed Transmit Waveform requirements
Voltage Level (DP - DN)
Time
Unit Interval (UI)
Level 1
-
2.082 to 2.084 ns
475 mV
-475 mV
0V
-
Level 2
-
Point 1
5% UI
95% UI
35% UI
65% UI
35% UI
65% UI
Point 2
0V
Point 3
300 mV
300 mV
-300 mV
-300 mV
Point 4
Point 5
Point 6
27/32
Electrical characteristics
Figure 20. USB signal eye diagram
ST72681
28/32
ST72681
Package mechanical data
8
Package mechanical data
®
In order to meet environmental requirements, ST offers these devices in ECOPACK
packages. These packages have a Lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97.
The maximum ratings related to soldering conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
Figure 21. 48-pin low profile quad flat package outline
D
A
A2
D1
A1
b
e
E1
E
c
L1
L
θ
Table 27. 48-pin low profile quad flat package dimensions
mm
inches(1)
Typ.
Dim.
Min.
Typ.
Max.
Min.
Max.
A
A1
A2
b
1.60
0.15
1.45
0.27
0.20
0.063
0.006
0.057
0.011
0.008
0.05
1.35
0.17
0.09
0.002
0.053
0.007
0.004
1.40
0.22
0.055
0.009
C
D
9.00
7.00
9.00
7.00
0.50
3.5°
0.60
1.00
0.354
0.276
0.354
0.276
0.020
3.5°
D1
E
E1
e
θ
0°
7°
0°
7°
L
0.45
0.75
0.018
0.024
0.039
0.030
L1
Number of Pins
48
N
1. Values in inches are converted from mm and rounded to 3 decimal digits.
29/32
Device ordering information
ST72681
9
Device ordering information
Table 28. Feature comparison table
Features added in the
ST72681/R21 versus ST72681/R20
Description
Firmware revision R21 upgrades the number of
supported NAND Flash devices from 1 to 4 in a
single channel.
Support for up to 4 NAND Flash devices
AutoRun runs a program when the USB Flash Drive
is inserted into a computer.
Continued AutoRun CDROM partition support
Table 29. Ordering information
Part number
Operating
voltage
Temperature
range
Package
ST72681/R20
TQFP48 7x7mm
3.0V to 3.6V
3.0V to 3.6V
0°C to +70°C
0°C to +70°C
ST72681/R21 (latest firmware revision) TQFP48 7x7mm
30/32
ST72681
Revision history
10
Revision history
Table 30. Document revision history
Date
Revision
Changes
Changed status of the document
Changed description on 1st page
Removed unconnected pins in Table 5 on page 7
Changed Table 4 on page 6
27-May-2005
1.0
Changed pin 5 description in Table 3 on page 6
Changed section 3 on page 7
Changed Figure 3 on page 8 and Figure 4
Electrical Characteristics section added, Section 4 on page 9
Additional features listed on front page
Status of document changed to Datasheet
18-Nov-2005
2.0
Application schematics modified, Figure 4 removed
Section 4.6 (Memory Characteristics) removed
VDDOUSB marked as O (output) in Table 2 on page 6
Additional features listed on front page
Application schematics modified, Figure 3 on page 8
Feature comparison table added for R20 firmware update, Table 28
Figure 3 on page 8 updated, with note added
06-Feb-2006
09-Jan-2007
3.0
4.0
Additional features listed on front page related to firmware release
R21. Application schematics updated for R21, Figure 3 on page 8
Feature comparison table added for R21 firmware update, Table 28
IDDsuspend values and note updated, Table 24
Updated information in Table 6: Known NAND compatibility guide for
R20 and R21 devices on page 9.
Added Section 4.2: NAND error correction on page 10, Section 4.3:
Management of bad NAND blocks on page 10, Section 4.4: Wear
levelling on page 11 and Section 4.5: NAND interface configuration
on page 12.
30-Aug-2007
5.0
Added Section 5: Mass storage implementation on page 13 and
Section 6: Human interface implementation on page 15.
Added internal clock frequency (fCPU) value in Table 10: General
operating conditions on page 18.
31/32
ST72681
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