ST72754J9B1_技术文档

ST72774/ST72754/ST72734

8-BIT USB MCU FOR MONITORS, WITH UP TO 60K OTP, 1K RAM,

2

ADC, TIMER, SYNC, TMU, PWM/BRM, H/W DDC & I C

■ User ROM/OTP/EPROM: up to 60 Kbytes

■ Data RAM: up to 1 Kbytes (256 bytes stack)

■ 8 MHz Internal Clock Frequency in fast mode,

4 MHz in normal mode

■ Run and Wait CPU modes

■ System protection against illegal address jumps

and illegal opcode execution

PSDIP42

TQFP44

■ Sync Processor for Mode Recognition, power

management and composite video blanking,

clamping and free-running frequency

generation

– Corrector mode

– Analyzer mode

■ USB (Universal Serial Bus) for monitor function¹

– Three endpoints

10 x 10

■ 2 lines programmable as interrupt inputs

■ 16-bit timer with 2 input captures and 2 output

compare functions

■ 8-bit Analog to Digital Converter with 4 channels

on port B

■ 8 10-bit PWM/BRM Digital to Analog outputs

■ Master Reset and Low Voltage Detector (LVD)

– Integrated 3.3V voltage regulator

– Transceiver

– Suspend and Resume operations

reset

■ Programmable Watchdog for system reliability

■ Fully static operation

■ 63 basic instructions / 17 main addressing

■ Timing

Measurement

Unit

(TMU)

for

1

autoposition and autosize

modes

2

■ Fast I C Single Master Interface

■ DDC Bus Interface with:

■ 8x8 unsigned multiply instruction

■ True bit manipulation

– DDC1/2B protocol implemented in hardware

– Programmable DDC CI modes

– Enhanced DDC (EDDC) address decoding

■ 31 I/O lines

■ Complete development support on PC/DOS-

Windows: Real-Time Emulator, EPROM

Programming Board and Gang Programmer

■ Full software package (assembler, linker, C-

compiler, source level debugger)

Device Summary

Features

ST72(T/E)774(J/S)9 ST72(T)754(J/S)9 ST72774(J/S)7 ST72754(J/S)7 ST72(T/E)734J6

Program Memory -

Bytes

60K

48K

32K

RAM (stack) - Bytes

1K (256)

No USB

512 (256)

No USB

ADC , I C,LVD,

DDC,Sync,

USB

3

USB

No USB

4

2

Peripherals

2

ADC , 16-bit timer, I C, DDC, TMU,Sync, PWM, LVD, Watchdog

16-bit timer,

PWM, Watchdog

Operating Supply

4.0V to 5.5V supply operating range

12 or 24 MHz

Oscillator Frequency

Operating Temperature

0 to +70°C

PSDIP42

CSDIP42

Package

CSDIP42 or PSDIP42 or TQFP44

(1) On some devices only, refer to Device Summary; (2) Contact Sales office for availability

(3) 8-bit ±2 LSB A/D converter ; (4) 8-bit ±4 LSB A/D converter.

October 2003

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1

Table of Contents

1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.3 MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.4 EXTERNAL CONNECTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3 CLOCKS, RESET, INTERRUPTS & LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.1 CLOCK SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.1.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.1.2 Crystal Resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.1.3 External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.2 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.2.1 LVD and Watchdog Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.2.2 External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.2.3 Illegal Address Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.2.4 Illegal Opcode Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.3 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . 22

3.4 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.4.1 WAIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.4.2 HALT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.5 MISCELLANEOUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.1 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.1.2 Common Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.1.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4.1.4 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4.1.5 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

4.1.6 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

4.1.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

4.2 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

4.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

4.2.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

4.2.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

4.2.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

4.2.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

4.3 16-BIT TIMER (TIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

4.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

4.3.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

4.3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

4

4.3.4 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

4.4 SYNC PROCESSOR (SYNC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

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ST72774/ST727754/ST72734

4.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

4.4.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

4.4.3 Input Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

4.4.4 Input Signal Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

4.4.5 Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

4.4.6 Input Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

4.4.7 Output Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

4.4.8 Analyzer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

4.4.9 Corrector Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

4.4.10Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

4.5 TIMING MEASUREMENT UNIT (TMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

4.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

4.5.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

4.5.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

4.5.4 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

4.6 USB INTERFACE (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

4.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

4.6.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

4.6.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

4.6.4 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

4.6.5 Programming Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

4.7 I²C SINGLE MASTER BUS INTERFACE (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

4.7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

4.7.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

4.7.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

4.7.4 Functional Description (Master Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

4.7.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

4.8 DDC INTERFACE (DDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

4.8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

4.8.2 DDC Interface Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

4.8.3 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

4.8.4 I2C BUS Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

4.8.5 DDC Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

4.8.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

4.9 PWM/BRM GENERATOR (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

4.9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

4.9.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

4.9.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

4.9.4 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

4.10 8-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

4.10.1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

4.10.2Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

4.10.3Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

4.10.4Low Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

4.10.5Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

4.10.6Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

5 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . 126

5.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

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ST72774/ST727754/ST72734

5.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

5.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

5.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

5.1.4 Indexed (No Offset, Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

5.1.5 Indirect (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

5.1.6 Indirect Indexed (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

5.1.7 Relative mode (Direct, Indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

5.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

6 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

6.1 POWER CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

6.2 AC/DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

7 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

7.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

8 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

8.1 TRANSFER OF CUSTOMER CODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

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ST72774/ST727754/ST72734

Revision follow-up

Changes applied since version 4.0

Version 4.0

March 2001

Page 1:Addition of 72T774 (32KOTP).

Addition of 60K/48K ROM for ST72754

Deletion of table “ device summary”, replaced with cross reference to table 36 on page 147.

page 13 - addition of section 1.4. external connections

July 2001

Version 4.1

Version 4.2

Initial format reapplied, text and related figures in the same page.

Table “Device summary” reinserted in cover page and updated.

Update of table 36: ordering information (p143)

July 2001

Cover - addition of feature about system protection added,

table for device summary: addition of stack values

page 9 - figure 3: replaced 1KByte with 512 Bytes + notes about opcode fetch and HALT

mode

page 10 - table: CR replaced by WDGCR

TIM replaced with Timer and WDG replaced with Watchdog

page 115 - EDF register: addition of “read from RAM”, EDE: few changes

page 135 - Note 1 replaced, note 2 added SUSpend mode limitation..

Whole document: all mentions of HALT mode either deleted or rewritten.

October 2001

Version 4.3

p140, chapter 8, section 8.1-

code for unused bytes ( FFh) replaced with 9Dh (opcode for NOP)

page 141- update of table 36 “Ordering information”

page 142 - list of available devices updated

page 114 - DDC DCR register: bit 5 = 1, text “or read from RAM” deleted

November 2001

page 10, one adddress corrected in the figure 3 “memory map”: 0400h

page 14: addition of mandatory 1K resistor (text and figure)

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ST72774/ST727754/ST72734

1 GENERAL DESCRIPTION

1.1 INTRODUCTION

The ST72774, ST72754 and ST72734 are

HCMOS microcontroller units (MCU) from the

ST727x4 family with dedicated peripherals for

Monitor applications.

They are based around an industry standard 8-bit

core and offer an enhanced instruction set. The

processor runs with an external clock at 12 or 24

MHz with a 5V supply. Due to the fully static design

of this device, operation down to DC is possible.

Under software control the ST727x4 can be placed

in WAIT mode thus reducing power consumption.

The HALT mode is no longer available.

In addition to standard 8-bit data management the

ST7 features true bit manipulation, 8x8 unsigned

multiplication and indirect addressing modes.

The device includes an on-chip oscillator, CPU,

System protection against illegal address jumps,

Sync Processor for video timing & Vfback analysis,

up to 60K Program Memory, up to 1K RAM, USB/

DMA, a Timing Measurement Unit, I/O, a timer with

2 input captures and 2 output compares, a 4-

2

channel Analog to Digital Converter, DDC, I C

Single Master, Watchdog Reset, and eight 10-bit

PWM/BRM outputs for analog DC control of

external functions.

The enhanced instruction set and addressing

modes afford real programming potential. Illegal

opcodes are patched and lead to a reset.

Figure 1. ST727x4 Block Diagram

PA0/OCMP1

PA1

PA2/VSYNCI2

PA3-PA6

PA7/BLANKOUT

Up to 60K Bytes

PORT A

ROM/OTP/EPROM

PORT B

PB6-PB7/AIN2-AIN3/PWM1-PWM2

PB4-PB5/AIN0-AIN1

Up to 1K Bytes

RAM

ADC

PB3/SDAI

PB2/SCLI

I2C

PB1/SDAD

DDC

PB0/SCLD

USBVCC

USBDP

USB

USBDM

CONTROL

RESET

PD0/VSYNCO

PD1/HSYNCO

PD2/CSYNCI

PD3/ITA/VFBACK

PD4/ITB

8-BIT CORE

ALU

PORT D

PD5/HFBACK

PD6/CLAMPOUT

TIMER

WATCHDOG

Mode

VSYNCI

HSYNCI

SYNC

PROCESSOR

OSCIN

:3

OSC

Selection

OSCOUT

TMU

V

DD

POWER SUPPLY

V

PC0/HSYNCDIV

PC1/AV

PC2-PC7/PWM3-PWM8

SS

PORT C

DAC (PWM)

6/144

3

ST72774/ST727754/ST72734

1.2 PIN DESCRIPTION

Figure 2. 44-pin TQFP and 42-Pin SDIP Package Pinouts

44 43 42 41 40 39 38 37 36 35 34

PWM7 / PC6

PA3

1

33

32

31

30

29

28

27

26

25

24

23

PWM8 / PC7

PWM2 / AIN3 / PB7

PWM1 / AIN2 / PB6

AIN1 / PB5

PA4

2

PA5

3

PA6

4

OSCIN

5

AIN0 / PB4

OSCOUT

PA7 / BLANKOUT

PB3 / SDAI

PB2 / SCLI

PB1 / SDAD

NC

6

NC

7

V

8

DD

USBVCC

USBDM

USBDP

9

10

11

12 13 14 15 16 17 18 19 20 21 22

HSYNCDIV / PC0

PA0 / OCMP1

1

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

TEST / V

PP

2

AV / PC1

PWM3 / PC2

RESET

3

PWM4 / PC3

PA1

4

PWM5 / PC4

PA2/VSYNCI2

PA3

5

PWM6 / PC5

6

PWM7 / PC6

PA4

7

PWM8 / PC7

PA5

8

PWM2 / AIN3 / PB7

PWM1 / AIN2 / PB6

AIN1 / PB5

PA6

9

OSCIN

10

11

12

13

14

15

16

17

18

19

20

21

OSCOUT

AIN0 / PB4

PA7 / BLANKOUT

PB3 / SDAI

PB2 / SCLI

PB1 / SDAD

PB0 / SCLD

PD6 / CLAMPOUT

PD5 / HFBACK

PD4 / ITB

V

DD

USBVCC

USBDM

USBDP

V

SS

HSYNCI

VSYNCI

VSYNCO / PD0

HSYNCO / PD1

PD3 / ITA / VFBACK

PD2 / CSYNCI

NC = Not connected

7/144

3

ST72774/ST727754/ST72734

PIN DESCRIPTION (Cont’d)

RESET: Bidirectional. This active low signal forces

the initialization of the MCU. This event is the top

priority non maskable interrupt. This pin is

switched low when the Watchdog has triggered or

TEST/V : Input. EPROM programming voltage.

This pin must be held low during normal operating

modes.

PP

V

: Power supply voltage (4.0V-5.5V)

DD

V

is low. It can be used to reset external

DD

: Digital Ground.

SS

peripherals.

Alternate Functions: several pins of the I/O ports

assume software programmable alternate

functions as shown in the pin description

OSCIN/OSCOUT: Input/Output Oscillator pin.

These pins connect a parallel-resonant crystal, or

an external source to the on-chip oscillator.

Table 1. ST727x4 Pin Description

Pin No.

Type

Pin Name

Description

Remarks

39

40

41

42

43

44

1

2

3

4

5

6

7

8

PC0/HSYNCDIV

PC1/AV

I/O

Port C0 or HSYNCDIV output (HSYNCO divided by 2)

Port C1 or “Active Video” input

PC2/PWM3

PC3/PWM4

PC4/PWM5

PC5/PWM6

PC6/PWM7

PC7/PWM8

Port C2 or 10-bit PWM/BRM output 3

Port C3 or 10-bit PWM/BRM output 4

Port C4 or 10-bit PWM/BRM output5

Port C5 or 10-bit PWM/BRM output 6

Port C6 or 10-bit PWM/BRM output 7

Port C7 or 10-bit PWM/BRM output 8

For analog controls,

after external filtering

2

Port B7 or ADC analog input 3 or 10-bit PWM/BRM

output 2

3

4

9

PB7/AIN3/PWM2

I/O

Port B6 or ADC analog input 2 or 10-bit PWM/BRM

output 1

10 PB6/AIN2/PWM1

5

6

8

9

11 PB5/AIN1

12 PB4/AIN0

I/O

S

Port B5 or ADC analog input 1

Port B4 or ADC analog input 0

Supply (4.0V - 5.5V)

13

V

DD

14 USBVCC

S

USB power supply (output 3.3V +/- 10%)

USB bidirectional data

10 15 USBDM

11 16 USBDP

I/O

Must be tied to ground

for devices without

USB peripheral

I/O

USB bidirectional data

12 17

V

S

I

Ground 0V

SS

13 18 HSYNCI

SYNC horizontal synchronisation input

SYNC vertical synchronisation input

Port D0 or SYNC vertical synchronisation output

Port D1 or SYNC horizontal synchronisation output

TTL levels

Refer to Figure 16

14 19 VSYNCI

I

15 20 PD0/VSYNCO

16 21 PD1/HSYNCO

I/O

TTL levels with pull-up

(SYNC input)

17 22 PD2/CSYNCI

I/O

Port D2 or SYNC composite synchronisation input

8/144

3

ST72774/ST727754/ST72734

Pin No.

Type

Pin Name

Description

Remarks

Refer to Figure 16 and

Table 11 Port D De-

scription

Port D3 or SYNC Vertical flyback input or interrupt fall-

ing edge detector input A

18 23 PD3/VFBACK/ITA

I/O

Refer to Table 11 Port

D Description

19 24 PD4/ITB

I/O

Port D4 or Interrupt falling edge detector input B

Port D5 or SYNC horizontal flyback input

TTL levels with pull-up

(SYNC input)

20 25 PD5/HFBACK

21 26 PD6/CLAMPOUT

22 27 PB0/SCLD

24 28 PB1/SDAD

25 29 PB2/SCLI

26 30 PB3/SDAI

27 31 PA7/BLANKOUT

28 32 OSCOUT

29 33 OSCIN

I/O

O

Port D6 or SYNC clamping/ MOIRE output

Port B0 or DDC serial clock

Port B1 or DDC serial data

Port B2 or I2C serial clock

Port B3 or I2C serial data

Port A7 or SYNC blanking output

Oscillator output

I

Oscillator input

30 34 PA6

I/O

Port A6

31 35 PA5

Port A5

32 36 PA4

Port A4

33 37 PA3

Port A3

34 38 PA2/VSYNCI2

35 39 PA1

Port A2 or SYNC vertical synchronisation input 2

Port A1

DDC1 only

Active low

36 40 RESET

Reset pin

Test mode pin or EPROM programming voltage. This

pin should be tied low in user mode.

37 41 TEST/V

S

PP

38 42 PA0/OCMP1

I/O

Port A0 or TIMER output compare 1

9/144

ST72774/ST727754/ST72734

1.3 MEMORY MAP

Figure 3. Memory Map

0000h

0060h

0100h

HW Registers

Short Addressing

RAM (zero page)

(see Table 2)

005Fh

0060h

512 Bytes RAM

256 Bytes Stack/

16-bit Addressing RAM

01FFh

1 Kbyte RAM

Reserved

03FFh

0400h

0060h

0100h

Short Addressing

RAM (zero page)

0FFFh

1000h

256 Bytes Stack/

16-bit Addressing RAM

60 Kbytes

48 Kbytes

ROM/EPROM

01FFh

0200h

4000h

8000h

16-bit Addressing

RAM

32 Kbytes

FFDFh

FFE0h

512 Bytes

Interrupt & Reset Vectors *

(see Table 3)

03FFh

FFFFh

any opcode fetch in those areas is considered as illegal and generates a reset

(*) this block only contains addresses of interrupts and reset routines, no opcode is run from this block

10/144

ST72774/ST727754/ST72734

MEMORY MAP (Cont’d)

Table 2. Hardware Register Memory Map

Reset

Address

Block

Register Label

Register Name

Port A Data Register

Remarks

Status

0000h

0001h

PADR

00h

R/W

PADDR

Port A Data Direction Register

0002h

0003h

PBDR

Port B Data Register

00h

R/W

PBDDR

Port B Data Direction Register

0004h

0005h

PCDR

Port C Data Register

00h

R/W

PCDDR

Port C Data Direction Register

0006h

0007h

PDDR

Port D Data Register

00h

R/W

PDDDR

Port D Data Direction Register

0008h

0009h

Watchdog

WDGCR

MISCR

Watchdog Control Register

Miscellaneous Register

7Fh

10h

R/W

000Ah

000Bh

ADCDR

ADC Data Register

00h

Read only

R/W

ADC

ADCCSR

ADC Control Status register

000Ch

000Dh

DDCDCR

DDCAHR

DDC1/2B Control Register

00h

xxh

R/W

DDC1/2B

DDC1/2B Address Pointer High Register

000Eh

000Fh

00010h

TMUCSR

TMUT1CR

TMUT2CR

TMU control status register

TMU T1 counter register

TMU T2 counter register

FCh

FFh

R/W

TMU

Read only

0011h

0012h

0013h

0014h

0015h

0016h

0017h

0018h

0019h

001Ah

001Bh

001Ch

001Dh

001Eh

001Fh

TIMCR2

Timer Control Register 2

00h

xxh

80h

00h

FFh

FCh

FFh

FCh

xxh

80h

00h

R/W

TIMCR1

Timer Control Register 1

R/W

TIMSR

Timer Status Register

Read only

R/W

TIMIC1HR

TIMIC1LR

TIMOC1HR

TIMOC1LR

TIMCHR

Timer Input Capture 1 High Register

Timer Input Capture 1 Low Register

Timer Output Compare 1 High Register

Timer Output Compare 1 Low Register

Timer Counter High Register

R/W

Timer

Read only

R/W

TIMCLR

Timer Counter Low Register

TIMACHR

TIMACLR

TIMIC2HR

TIMIC2LR

TIMOC2HR

TIMOC2LR

Timer Alternate Counter High Register

Timer Alternate Counter Low Register

Timer Input Capture 2 High Register

Timer Input Capture 2 Low Register

Timer Output Compare 2 High Register

Timer Output Compare 2 Low Register

Read only

R/W

Read only

R/W

0020h

to

Reserved Area (5 bytes)

0024h

11/144

ST72774/ST727754/ST72734

Reset

Status

Address

Block

Register Label

Register Name

USB PID Register

Remarks

XXh

0025h

0026h

0027h

0028h

0029h

002Ah

002Bh

002Ch

002Dh

002Eh

002Fh

0030h

0031h

USBPIDR

Read only

R/W

XXh

USBDMAR

USBIDR

USB DMA address Register

USB Interrupt/DMA Register

USB Interrupt Status Register

USB Interrupt Mask Register

USB Control Register

XXh

R/W

00h

USBISTR

R/W

00h

USBIMR

R/W

xxxx 0110

00h

USBCTLR

USBDADDR

USBEP0RA

USBEP0RB

USBEP1RA

USBEP1RB

USBEP2RA

USBEP2RB

R/W

USB

USB Device Address Register

USB Endpoint 0 Register A

USB Endpoint 0 Register B

USB Endpoint 1 Register A

USB Endpoint 1 Register B

USB Endpoint 2 Register A

USB Endpoint2 Register B

R/W

0000 xxxx

80h

R/W

0000 xxxx

R/W

0000

xxxx0000

0000

R/W

xxxx0000

0032h

0033h

0034h

0035h

0036h

0037h

0038h

0039h

003Ah

003Bh

003Ch

003Dh

003Eh

PWM1

BRM21

PWM2

PWM3

BRM43

PWM4

PWM5

BRM65

PWM6

PWM7

BRM87

PWM8

PWMCR

80h

00h

80h

00h

80h

00h

80h

00h

80h

00h

R/W

PWM

10 BIT PWM / BRM

PWM output enable register

Reserved Area (1 byte)

003Fh

0040h

0041h

0042h

0043h

0044h

0045h

0046h

0047h

SYNCCFGR

SYNCMCR

SYNCCCR

SYNC Configuration Register

SYNC Multiplexer Register

SYNC Counter Register

00h

20h

00h

08h

00h

C3h

R/W

SYNCPOLR

SYNCLATR

SYNCHGENR

SYNCVGENR

SYNCENR

SYNC Polarity Register

SYNC

SYNC Latch Register

SYNC H Sync Generator Register

SYNC V Sync Generator Register

SYNC Processor Enable Register

0048h

to

Reserved Area (8 bytes)

004Fh

12/144

ST72774/ST727754/ST72734

Reset

Address

Block

Register Label

Register Name

DDC/CI Control Register

Remarks

Status

0050h

0051h

0052h

0053h

0054h

0055h

0056h

DDCCR

DDCSR1

DDCSR2

00h

R/W

DDC/CI Status Register 1

DDC/CI Status Register 2

Reserved

Read only

DDC/CI

DDCOAR

DDCDR

DDC/CI (7 Bits) Slave address Register

Reserved

00h

R/W

DDC/CI Data Register

0057h

0058h

Reserved Area (2 bytes)

0059h

005Ah

005Bh

005Ch

005Dh

005Eh

005Fh

I2CDR

I2C Data Register

Reserved

00h

R/W

Reserved

2

I2C

I2CCCR

I2CSR2

I2CSR1

I2CCR

I C Clock Control Register

00h

R/W

2

I C Status Register 2

Read only

R/W

2

I C Status Register 1

2

I C Control Register

Table 3. Interrupt Vector Map

Vector Address

Description

Remarks

FFE0-FFE1h

FFE2-FFE3h

FFE4-FFE5h

FFE6-FFE7h

FFE8-FFE9h

FFEA-FFEBh

FFEC-FFEDh

FFEE-FFEFh

FFF0-FFF1h

FFF2-FFF3h

FFF4-FFF5h

FFF6-FFF7h

FFF8-FFF9h

FFFA-FFFBh

FFFC-FFFDh

FFFE-FFFFh

Not used

USB interrupt vector

Internal Interrupts

Not used

I2C interrupt vector

Timer Overflow interrupt vector

Timer Output Compare interrupt vector

Timer Input Capture interrupt vector

ITA falling edge interrupt vector

ITB falling edge interrupt vector

DDC1/2B interrupt vector

DDC/CI interrupt vector

USB End Suspend interrupt vector

TRAP (software) interrupt vector

RESET vector

External Interrupts

Internal Interrupt

CPU Interrupt

13/144

ST72774/ST727754/ST72734

1.4 External connections

The following figure shows the recommended ex-

ternal connections for the device.

The external reset network (including the manda-

tory 1K serial resistor) is intended to protect the

device against parasitic resets, especially in noisy

environments.

The V pin is only used for programming OTP

PP

and EPROM devices and must be tied to ground in

user mode.

Unused I/Os should be tied high to avoid any un-

necessary power consumption on floating lines.

An alternative solution is to program the unused

ports as inputs with pull-up.

The 10 nF and 0.1 µF decoupling capacitors on

the power supply lines are a suggested EMC per-

formance/cost tradeoff.

Figure 4. Recommended External Connections

V

PP

DD

SS

V

DD

+

0.1µF

10nF

V

DD

4.7K

0.1µF

RESET

EXTERNAL RESET CIRCUIT

1K

See

Clocks

Section

OSCIN

OSCOUT

Or configure unused I/O ports

by software as input with pull-up

10K

V

DD

Unused I/O

14/144

ST72774/ST727754/ST72734

2 CENTRAL PROCESSING UNIT

2.1 INTRODUCTION

The Accumulator is an 8-bit general purpose

register used to hold operands and the results of

the arithmetic and logic calculations and to

manipulate data.

This CPU has a full 8-bit architecture and contains

six internal registers allowing efficient 8-bit data

manipulation.

Index Registers (X and Y)

2.2 MAIN FEATURES

In indexed addressing modes, these 8-bit registers

are used to create either effective addresses or

temporary storage areas for data manipulation.

(The Cross-Assembler generates a precede

instruction (PRE) to indicate that the following

instruction refers to the Y register.)

■ 63 basic instructions

■ Fast 8-bit by 8-bit multiply

■ 17 main addressing modes

■ Two 8-bit index registers

■ 16-bit stack pointer

The Y register is not affected by the interrupt

automatic procedures (not pushed to and popped

from the stack).

■ Low power modes

■ Maskable hardware interrupts

■ Non-maskable software interrupt

Program Counter (PC)

2.3 CPU REGISTERS

The program counter is a 16-bit register containing

the address of the next instruction to be executed

by the CPU. It is made of two 8-bit registers PCL

(Program Counter Low which is the LSB) and PCH

(Program Counter High which is the MSB).

The 6 CPU registers shown in Figure 5 are not

present in the memory mapping and are accessed

by specific instructions.

Accumulator (A)

Figure 5. CPU Registers

7

0

ACCUMULATOR

RESET VALUE = XXh

7

0

X INDEX REGISTER

Y INDEX REGISTER

RESET VALUE = XXh

7

RESET VALUE = XXh

PCL

PCH

7

8

15

0

PROGRAM COUNTER

RESET VALUE = RESET VECTOR @ FFFEh-FFFFh

7

1

0

1

H I N Z

C

CONDITION CODE REGISTER

RESET VALUE =

8

1

X 1 X X X

0

15

7

STACK POINTER

RESET VALUE = STACK HIGHER ADDRESS

X = Undefined Value

15/144

ST72774/ST727754/ST72734

CPU REGISTERS (Cont’d)

CONDITION CODE REGISTER (CC)

enter it and reset by the IRET instruction at the end

of the interrupt routine. If the I bit is cleared by

software in the interrupt routine, pending interrupts

are serviced regardless of the priority level of the

current interrupt routine.

Read/Write

Reset Value: 111x1xxx

7

0

1

H

I

N

Z

C

Bit 2 = N Negative.

This bit is set and cleared by hardware. It is

representative of the result sign of the last

arithmetic, logical or data manipulation. It is a copy

The 8-bit Condition Code register contains the

interrupt mask and four flags representative of the

result of the instruction just executed. This register

can also be handled by the PUSH and POP

instructions.

th

of the 7 bit of the result.

0: The result of the last operation is positive or null.

1: The result of the last operation is negative

(i.e. the most significant bit is a logic 1).

These bits can be individually tested and/or

controlled by specific instructions.

This bit is accessed by the JRMI and JRPL

instructions.

Bit 4 = H Half carry.

This bit is set by hardware when a carry occurs

between bits 3 and 4 of the ALU during an ADD or

ADC instruction. It is reset by hardware during the

same instructions.

Bit 1 = Z Zero.

This bit is set and cleared by hardware. This bit

indicates that the result of the last arithmetic,

logical or data manipulation is zero.

0: No half carry has occurred.

1: A half carry has occurred.

This bit is tested using the JRH or JRNH

instruction. The H bit is useful in BCD arithmetic

subroutines.

0: The result of the last operation is different from

zero.

1: The result of the last operation is zero.

This bit is accessed by the JREQ and JRNE test

instructions.

Bit 3 = I Interrupt mask.

Bit 0 = C Carry/borrow.

This bit is set by hardware when entering in

interrupt or by software to disable all interrupts

except the TRAP software interrupt. This bit is

cleared by software.

This bit is set and cleared by hardware and

software. It indicates an overflow or an underflow

has occurred during the last arithmetic operation.

0: No overflow or underflow has occurred.

1: An overflow or underflow has occurred.

This bit is driven by the SCF and RCF instructions

and tested by the JRC and JRNC instructions. It is

also affected by the “bit test and branch”, shift and

rotate instructions.

0: Interrupts are enabled.

1: Interrupts are disabled.

This bit is controlled by the RIM, SIM and IRET

instructions and is tested by the JRM and JRNM

instructions.

Note: Interrupts requested while I is set are

latched and can be processed when I is cleared.

By default an interrupt routine is not interruptable

because the I bit is set by hardware when you

16/144

ST72774/ST727754/ST72734

CPU REGISTERS (Cont’d)

Stack Pointer (SP)

The least significant byte of the Stack Pointer

(called S) can be directly accessed by a LD

instruction.

Read/Write

Reset Value: 01 FFh

Note: When the lower limit is exceeded, the Stack

Pointer wraps around to the stack upper limit,

without indicating the stack overflow. The

previously stored information is then overwritten

and therefore lost. The stack also wraps in case of

an underflow.

15

8

1

0

7

0

The stack is used to save the return address

during a subroutine call and the CPU context

during an interrupt. The user may also directly

manipulate the stack by means of the PUSH and

POP instructions. In the case of an interrupt, the

PCL is stored at the first location pointed to by the

SP. Then the other registers are stored in the next

locations as shown in Figure 6.

SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0

The Stack Pointer is a 16-bit register which is

always pointing to the next free location in the

stack. It is then decremented after data has been

pushed onto the stack and incremented before

data is popped from the stack (see Figure 6).

Since the stack is 256 bytes deep, the most

significant byte is forced by hardware. Following

an MCU Reset, or after a Reset Stack Pointer

instruction (RSP), the Stack Pointer contains its

reset value (the SP7 to SP0 bits are set) which is

the stack higher address.

– When an interrupt is received, the SP is decre-

mented and the context is pushed on the stack.

– On return from interrupt, the SP is incremented

and the context is popped from the stack.

A subroutine call occupies two locations and an

interrupt five locations in the stack area.

Figure 6. Stack Manipulation Example

CALL

Subroutine

RET

or RSP

PUSH Y

POP Y

IRET

Interrupt

event

@ 0100h

SP

Y

CC

A

CC

A

CC

A

X

PCH

PCL

PCH

PCL

PCH

PCL

PCH

PCL

PCH

PCL

PCH

PCL

SP

PCH

PCL

PCH

PCL

SP

@ 01FFh

Stack Higher Address = 01FFh

0100h

Stack Lower Address =

17/144

ST72774/ST727754/ST72734

3 CLOCKS, RESET, INTERRUPTS & LOW POWER MODES

3.1 CLOCK SYSTEM

3.1.1 General Description

shown in Figure 7 and a second divider by 2 for the

The MCU accepts either a crystal or an external

6MHz USB clock.

clock signal to drive the internal oscillator. The

The CPU clock is used also as clock for the

ST727x4 peripherals.

internal clock (CPU CLK running at f

) is

CPU

derived from the external oscillator frequency

(f ), which is divided by 3. Depending on the

Note: In the Sync processor, an additional divider

by two is added in fast mode (same external timing

for this peripheral).

OSC

external quartz or clock frequency, a division factor

of 2 is optionally added to generate the 12 MHz

clock for the Sync Processor (clamp function) as

Figure 7. Clock divider chain

f

: 4 or 8 MHz

CPU

%3

(CPU and peripherals)

%2

OSC

12 MHz

(Sync processor Clampout signal)

12 MHz

or

24MHz

FAST

6 MHz

(USB)

%2

12 MHz

or

24MHz

(TMU)

FAST=1 for 24MHZ oscillator

FAST=0 for 12 MHz oscillator

18/144

4

ST72774/ST727754/ST72734

CLOCK SYSTEM (Cont’d)

3.1.2 Crystal Resonator

The internal oscillator is designed to operate with

an AT-cut parallel resonant quartz crystal

resonator in the frequency range specified for f

Table 4. Recommended Crystal Values

24 Mhz

Unit

Ohms

pf

R

70

22

25

47

20

56

SMAX

.

osc

C

L1

L2

The circuit shown in Figure 8 is recommended

when using crystal, and Table 4, “.

pf

a

Recommended Crystal Values,” on page 19 lists

the recommended capacitance and feedback

resistance values. The crystal and associated

components should be mounted as close as

possible to the input pins in order to minimize

output distortion and start-up stabilization time.

Legend:

C , C = Maximum total capacitance on pins

OSCIN and OSCOUT (the value includes the

external capacitance tied to the pin plus the

parasitic capacitance of the board and of the

device).

L1

L2

Figure 8. Crystal/Ceramic Resonator

R

= Maximum series parasitic resistance of

SMAX

the quartz allowed.

CRYSTAL CLOCK

Note: The tables are relative to the quartz crystal

only (not ceramic resonator).

3.1.3 External Clock

An external clock should be applied to the OSCIN

OSCIN

OSCOUT

input with the OSCOUT pin not connected as

shown in Figure 9. The Crystal clock specifications

do not apply when using an external clock input.

The equivalent specification of the external clock

source should be used.

C

L1

L2

1M*

*Recommended for oscillator stability

Figure 9. External Clock Source Connections

OSCOUT

NC

OSCIN

EXTERNAL

CLOCK

19/144

ST72774/ST727754/ST72734

3.2 RESET

The Reset procedure is used to provide an orderly

software start-up or to quit low power modes.

When a watchdog reset occurs, the RESET pin is

pulled low permitting the MCU to reset other

devices as when Power on/off (Figure 10).

Five conditions generate a reset:

3.2.2 External Reset

■

LVD,

watchdog,

external pulse at the RESET pin,

illegal address,

illegal opcode.

The external reset is an active low input signal

applied to the RESET pin of the MCU.

As shown in Figure 12, the RESET signal must

remain low for 1000ns.

A reset causes the reset vector to be fetched from

addresses FFFEh and FFFFh in order to be loaded

into the PC and with program execution starting

from this point.

An internal Schmitt trigger at the RESET pin is

provided to improve noise immunity.

3.2.3 Illegal Address Detection

An opcode fetch from an illegal address (refer to

Figure 3) generates an illegal address reset.

Program execution at those addresses is

forbidden (especially to protect page 0 registers

against spurious accesses).

An internal circuitry provides a 4096 CPU clock

cycle delay from the time that the oscillator

becomes active.

3.2.1 LVD and Watchdog Reset

The Low Voltage Detector (LVD) generates a reset

3.2.4 Illegal Opcode Detection

when V is below V

when V is rising or V

DD

TRH

DD TRL

Illegal instructions corresponding to no valid

when

is falling (refer to Figure 11). This circuitry

VDD

opcode generate

a

reset. Refer to ST7

is active only when V is above V

DD

TRM.

Programming Manual.

During LVD Reset, the RESET pin is held low, thus

permitting the MCU to reset other devices.

Table 5. List of sections affected by RESET and WAIT (Refer to 3.6 for Wait Mode)

Section

Fast bit of the miscellaneous register set to one (24 MHz as external clock)

Timer Prescaler reset to zero

RESET

WAIT

X

Timer Counter set to FFFCh

All Timer enable bits set to 0 (disabled)

Data Direction Registers set to 0 (as Inputs)

Set Stack Pointer to 01FFh

Force Internal Address Bus to restart vector FFFEh, FFFFh

Set Interrupt Mask Bit (I-Bit, CC) to 1 (Interrupt disable)

Set Interrupt Mask Bit (I-Bit, CC) to 0 (Interrupt enable)

Reset WAIT latch

X

Disable Oscillator (for 4096 cycles)

Set Timer Clock to 0

Watchdog counter reset

Watchdog register reset

Port data registers reset

Other on-chip peripherals: registers reset

20/144

ST72774/ST727754/ST72734

RESET (Cont’d)

Figure 10. Low Voltage Detector Functional Diagram

Figure 11. LVD Reset Signal Output

V

RESPOF

LVD

TRH

V

TRL

DD

V

RESET

TRM

V

TRM

V

INTERNAL

RESET

DD

FROM

WATCHDOG

RESET

Note: See electrical characteristics section for

values of V and V

V

TRH, TRL

TRM

Figure 12. Reset Timing Diagram

t

DDR

V

DD

OSCIN

t_OXOV

f

CPU

FFFF

FFFE

PC

t

RL

RESET

4096 CPU

CLOCK

CYCLES

DELAY

WATCHDOG RESET

Note: Refer to Electrical Characteristics for values of t

, t_{OXOV and}t

RL

DDR

21/144

ST72774/ST727754/ST72734

3.3 INTERRUPTS

The ST727x4 may be interrupted by one of two

different methods: maskable hardware interrupts

as listed in Table 6 and a non-maskable software

interrupt (TRAP). The Interrupt processing

flowchart is shown in Figure 13.

The maskable interrupts must be enabled in order

to be serviced. However, disabled interrupts can

be latched and processed when they are enabled.

When an interrupt has to be serviced, the PC, X, A

and CC registers are saved onto the stack and the

interrupt mask (I bit of the Condition Code

Register) is set to prevent additional interrupts.

The Y register is not automatically saved.

ITA, ITB interrupts. The ITA (PD3), ITB (PD4),

pins can generate an interrupt when a falling edge

occurs on these pins, if these interrupts are

enabled with the ITAITE, ITBITE bits respectively

in the miscellaneous register and the I bit of the CC

register is reset. When an enabled interrupt

occurs, normal processing is suspended at the

end of the current instruction execution. It is then

serviced according to the flowchart on Figure 13.

Software in the ITA or ITB service routine must

reset the cause of this interrupt by clearing the

ITALAT, ITBLAT or ITAITE, ITBITE bits in the

miscellaneous register.

The PC is then loaded with the interrupt vector of

the interrupt to service and the interrupt service

routine runs (refer to Table 6, “Interrupt Mapping,”

on page 24 for vector addresses). The interrupt

service routine should finish with the IRET

instruction which causes the contents of the

registers to be recovered from the stack and

normal processing to resume. Note that the I bit is

then cleared if and only if the corresponding bit

stored in the stack is zero.

Peripheral Interrupts. Different peripheral

interrupt flags are able to cause an interrupt when

they are active if both the I bit of the CC register is

reset and if the corresponding enable bit is set. If

either of these conditions is false, the interrupt is

latched and thus remains pending.

The interrupt flags are located in the status

register. The Enable bits are in the control register.

When an enabled interrupt occurs, normal

processing is suspended at the end of the current

instruction execution. It is then serviced according

to the flowchart on Figure 13.

Though many interrupts can be simultaneously

pending, a priority order is defined (see Table 6,

“Interrupt Mapping,” on page 24). The RESET pin

has the highest priority.

The general sequence for clearing an interrupt is

an access to the status register while the flag is set

followed by a read or write of an associated

register. Note that the clearing sequence resets

the internal latch. A pending interrupt (i.e. waiting

for being enabled) will therefore be lost if the clear

sequence is executed.

If the I bit is set, only the TRAP interrupt is enabled.

All interrupts allow the processor to leave the

WAIT low power mode.

Software Interrupt. The software interrupt is the

executable instruction TRAP. The interrupt is

recognized when the TRAP instruction is

executed, regardless of the state of the I bit. When

the interrupt is recognized, it is serviced according

to the flowchart on Figure 13.

22/144

ST72774/ST727754/ST72734

INTERRUPTS (Cont’d)

Figure 13. Interrupt Processing Flowchart

FROM RESET

Y

TRAP?

N

I BIT SET?

Y

N

INTERRUPT?

FETCH NEXT INSTRUCTION

Y

N

EXECUTE INSTRUCTION

IRET?

STACK PC, X, A, CC

SET I BIT

LOAD PC FROM INTERRUPT VECTOR

Y

RESTORE PC, X, A, CC FROM STACK

THIS CLEARS I BIT BY DEFAULT

VR01172D

23/144

ST72774/ST727754/ST72734

INTERRUPTS (Cont’d)

Table 6. Interrupt Mapping

Source

Register

Label

Maskable

by I-bit

Priority

Order

Description

Block

Flag

Vector Address

RESET

TRAP

USB

Reset

N/A

no

FFFEh-FFFFh

FFFCh-FFFDh

FFFAh-FFFBh

Highest

Priority

Software

End Suspend Interrupt

USBISTR

ESUSP

yes

DDCSR1

DDCSR2

DDC/CI

DDC/CI Interrupt

**

yes

FFF8h-FFF9h

DDC1/2B

Port D bit 4

Port D bit 3

DDC1/2B Interrupt

External Interrupt ITB

External Interrupt ITA

Input Capture 1

DDCDCR

EDF

ITBLAT

ITALAT

ICF1

yes

FFF6h-FFF7h

FFF4h-FFF5h

FFF2h-FFF3h

MISCR

yes

FFF0h-FFF1h

Input Capture 2

ICF2

TIM

Output Compare 1

Output Compare 2

Timer Overflow

TIMSR

OCF1

OCF2

TOF

yes

FFEEh-FFEFh

FFECh-FFEDh

FFEAh-FFEBh

I2C Peripheral Inter-

rupts

I2CSR1

I2CSR2

I2C

**

Lowest

Priority

USB

USB Interrupt

USBISTR

**

yes

FFE6h-FFE7h

** Many flags can cause an interrupt, see peripheral interrupt status register description.

24/144

ST72774/ST727754/ST72734

3.4 POWER SAVING MODES

3.4.1 WAIT Mode

This mode is a low power consumption mode. The

Figure 14. WAIT Flow Chart

WFI instruction places the MCU in WAIT mode:

The internal clock remains active but all CPU

processing is stopped; however, all other

peripherals are still running.

WFI INSTRUCTION

Note: In WAIT mode, DMA accesses (DDC, USB)

are possible.

OSCILLATOR

ON

PERIPH. CLOCK

CPU CLOCK

I-BIT

ON

OFF

During WAIT mode, the I bit in the condition code

register is cleared to enable all interrupts, which

causes the MCU to exit WAIT mode, causes the

corresponding interrupt vector to be fetched, the

interrupt routine to be executed and normal

processing to resume. A reset causes the program

counter to fetch the reset vector and processing

starts as for a normal reset.

CLEARED

N

RESET

N

Table 5 gives a list of the different sections

affected by the low power modes. For detailed

information on a particular device, please refer to

the corresponding part.

Y

INTERRUPT

Y

OSCILLATOR

ON

SET

PERIPH. CLOCK

CPU CLOCK

I-BIT

IF RESET

3.4.2 HALT Mode

4096 CPU CLOCK

CYCLES DELAY

The HALT mode is the MCU lowest power

consumption mode. Meanwhile, the HALT mode

also stops the oscillator stage completely which is

the most critical condition in CRT monitors.

FETCH RESET VECTOR

OR SERVICE INTERRUPT

For this reason, the HALT mode has been disabled

and its associated HALT instruction is now

considered as illegal and will generate a reset.

Note: Before servicing an interrupt, the CC register is

pushed on the stack. The I-Bit is set during the inter-

rupt routine and cleared when the CC register is

popped.

25/144

ST72774/ST727754/ST72734

3.5 MISCELLANEOUS REGISTER

MISCELLANEOUS REGISTER (MISCR)

Bit 4= FAST Fast Mode.

Address: 0009h

—

Read/Write

This bit is set and cleared by software. It is used to

select the external clock frequency. If the external

clock frequency is 12 MHz, this bit must be at 0,

else if the external frequency is 24 MHz, this bit

must be at 1.

Reset Value: 0001 0000 (10h)

7

0

VSYNC FLY_S HSYNC

FAST ITBLAT ITALAT ITBITE ITAITE

SEL

YN

DIVEN

Bit 7= VSYNCSEL DDC1 VSYNC Selection.

Bit 3= ITBLAT Falling Edge Detector Latch.

This bit is set by hardware when a falling edge

occurs on pin ITB/PD4 in Port D. An interrupt is

generated if ITBITE=1and the I bit in the CC

register = 0. It is cleared by software.

This bit is set and cleared by software. It is used to

choose the VSYNC signal in DDC1 mode.

0: VSYNCI selected

1: VSYNCI2 selected

0: No falling edge detected on ITB

1: Falling edge detected on ITB

Note: VSYNCI 2 is only available for the DDC cell,

not for the SYNC processor cell.

Bit 2= ITALAT Falling Edge Detector Latch.

This bit is set by hardware when a falling edge

occurs on pin ITA/PD3 in Port D. An interrupt is

generated if ITAITE=1and the I bit in the CC

register = 0. It is cleared by software.

Bit 6= FLY_SYN Flyback or Synchro Switch.

This bit is set and cleared by software. It is used to

choose the signals the Timing Measurement Unit

(TMU) will analyse.

0: horizontal and vertical synchro outputs analysis

1: horizontal and vertical Flyback inputs analysis

0: No falling edge detected on ITA

1: Falling edge detected on ITA

Bit 5= HSYNCDIVEN HSYNCDIV Enable.

Bit 1= ITBITE ITB Interrupt Enable.

This bit is set and cleared by software.

This bit is set and cleared by software. It is used to

enable the output of the HSYNCO output on PC0.

0: ITB interrupt disabled

1: ITB interrupt enabled

0: HSYNCDIV disabled

1:HSYNCDIV enabled

Bit 0= ITAITE ITA Interrupt Enable.

This bit is set and cleared by software.

0: ITA interrupt disabled

1: ITA interrupt enabled

26/144

ST72774/ST727754/ST72734

4 ON-CHIP PERIPHERALS

4.1 I/O PORTS

4.1.1 Introduction

The I/O ports allow the transfer of data through

digital inputs and outputs, and, for specific pins,

the input of analog signals or the Input/Output of

alternate signals for on-chip peripherals (DDC,

TIMER...).

Each pin can be programmed independently as

digital input or digital output. Each pin can be an

analog input when an analog switch is connected

to the Analog to Digital Converter (ADC).

Figure 15. I/O Pin Typical Circuit

Alternate enable

1

V

Alternate

output

DD

0

P-BUFFER

(if required)

DR

latch

PULL-UP (if required)

Alternate enable

DDR

latch

PAD

Analog Enable

(ADC)

Analog

DDR SEL

Switch (if required)

N-BUFFER

1

DR SEL

Alternate Enable

V

0

SS

Digital Enable

Alternate Input

Note: This is the typical I/O pin configuration. For cost optimization, each port is customized with a specific configuration.

27/144

5

ST72774/ST727754/ST72734

I/O PORTS (Cont’d)

Table 7. I/O Pin Functions

from the CMOS Schmitt Trigger output and not

from the Data Register output.

DDR

MODE

Input

4.1.2.2 Output mode

When DDR=1, the corresponding I/O is configured

in Output mode.

0

1

Output

4.1.2 Common Functional Description

Each port pin of the I/O Ports can be individually

configured under software control as either input

or output.

In this case, the output buffer is activated

according to the Data Register’s content.

A read operation is directly performed from the

Data Register output.

Each bit of a Data Direction Register (DDR)

corresponds to an I/O pin of the associated port.

This corresponding bit must be set to configure its

associated pin as output and must be cleared to

configure its associated pin as input (Table 7, “. I/O

Pin Functions,” on page 28). The Data Direction

Registers can be read and written.

4.1.2.3 Analog input

Each I/O can be used as analog input by adding an

analog switch driven by the ADC.

The I/O must be configured in Input before using it

as analog input.

The CMOS Schmitt trigger is OFF and the analog

value directly input through an analog switch to the

Analog to Digital Converter, when the analog

channel is selected by the ADC.

The typical I/O circuit is shown on Figure 15. Any

write to an I/O port updates the port data register

even if it is configured as input. Any read of an I/O

port returns either the data latched in the port data

register (pins configured as output) or the value of

the I/O pins (pins configured as input).

4.1.2.4 Alternate mode

A signal coming from a on-chip peripheral can be

output on the I/O.

In this case, the I/O is automatically configured in

output mode.

This must be controlled directly by the peripheral

with a signal coming from the peripheral which

enables the alternate signal to be output.

Remark: when an I/O pin does not exist inside an

I/O port, the returned value is a logic one (pin

configured as input).

At reset, all DDR registers are cleared, which

configures all port’s I/Os as inputs with or without

pull-ups (see Table 8 to Table 12 I/O Ports

Register Map). The Data Registers (DR) are also

initialized at reset.

A signal coming from an I/O can be input in a on-

chip peripheral.

Before using an I/O as Alternate Input, it must be

configured in Input mode (DDR=0). So both

Alternate Input configuration and I/O Input

configuration are the same (with or without pull-

up). The signal to be input in the peripheral is taken

after the CMOS Schmitt trigger or TTL Schmitt

trigger for SYNC.

4.1.2.1 Input mode

When DDR=0, the corresponding I/O is configured

in Input mode.

In this case, the output buffer is switched off, the

state of the I/O is readable through the Data

Register address, but the I/O state comes directly

The I/O state is readable as in Input mode by

addressing the corresponding I/O Data Register.

28/144

ST72774/ST727754/ST72734

Figure 16. Input Structure for SYNC signals

PA [6:3] can be defined as Input lines (without pull-

up) or as Output Open drain lines.

PA7 and PA[2:0] can be defined as Input lines

(with pull-up) or as Push-pull Outputs.

TTL trigger

HSYNCI Input

VSYNCI Input

(no pull-up)

PA [6:3] can be defined as Input lines (without pull-

up) or as Output Open drain lines.

I/O logic (if existing)

V

DD

pull-up

TTL trigger

CSYNCI Input

HFBACK Input

VFBACK Input

I/O logic (if existing)

4.1.3 Port A

PA7 and PA[2:0] can be defined as Input lines

(with pull-up) or as Push-pull Outputs.

Table 8. Port A Description

I / O

Alternate Function

PORT A

Input*

Output

Signal

Condition

OC1E =1

PA0

PA1

PA2

With pull-up

push-pull

OCMP1

(CR2[TIMER])

-

VSYNCSEL=1

(MISCR)

VSYNCI2

PA3

PA4

PA5

PA6

Without pull-up

open-drain

-

BLKEN = 1

(ENR[SYNC])

PA7

With pull-up

push-pull

BLANKOUT

*Reset State

29/144

ST72774/ST727754/ST72734

I/O PORTS (Cont’d)

Figure 17. PA0 to PA2, PA7

Alternate enable

1

V

Alternate

output

DD

0

P-BUFFER

DR

latch

PULL-UP

OC1E

DDR

latch

PAD

DDR SEL

N-BUFFER

1

0

DR SEL

OC1E

CMOS Schmitt Trigger

V

SS

Figure 18. PA3 to PA6

Alternate enable

DR

latch

1

Alternate

output

0

PAD

DDR

latch

DDR SEL

N-BUFFER

1

0

DR SEL

Alternate enable

V

SS

CMOS Schmitt Trigger

Alternate input

30/144

ST72774/ST727754/ST72734

I/O PORTS (Cont’d)

4.1.4 Port B

All unused I/O lines should be tied to an

The alternate functions are the I/O pins of the on-

appropriate logic level (either V or V

)

SS

DD

chip DDC SCLD & SCDAD for PB0:1, the I/O pins

of the on-chip I2C SCLI & SCDAI for PB2:3, and 4

bits of port B bit can be used as the Analog source

to the Analog to Digital Converter.

Since the ADC is on the same chip as the

microprocessor, the user should not switch heavily

loaded signals during conversion, if high precision

is required. Such switching will affect the supply

voltages used as analog references. the accuracy

of the conversion depends on the quality of the

Only one I/O line must be configured as an analog

input at any time. The user must avoid any

situation in which more than one I/O pin is selected

as an analog input simultaneously to avoid device

malfunction.

power supplies (V and V ). The user must take

DD

SS

special care to ensure that a well regulated

reference voltage is present on the V and V

DD

SS

pins (power supply variations must be less than

5V/ms). This implies, in particular, that a suitable

When the analog function is selected for an I/O pin,

the pull-up of the respective pin of Port B is

disconnected and the digital input is off.

decoupling capacitor is used at the V pin.

DD

Table 9. Port B Description

PORT B

I/O

Alternate Function

Input*

Output

Signal

Condition

DDC enable

SCLD (input with CMOS schmitt trigger or

open drain output)

PB0

PB1

PB2

PB3

Without pull-up Open-drain

SDAD (input with CMOS schmitt trigger or

open drain output)

DDC enable

I2C enable

SCLI (input with CMOS schmitt trigger or

open drain output)

SDAI (input with CMOS schmitt trigger or

open drain output)

PB4

PB5

With pull-up

Push-pull

Analog input (ADC) (without pull-up)

10-bit output 1 (PWM)

CH[2:0]=000 (ADCCSR)

CH[2:0]=001 (ADCCSR)

CH[2:0]=010 (ADCCSR)

OE0=1 (PWMOE)

PB6

With pull-up

Push-pull

Analog input (ADC) (without pull-up)

10-bit output 2 (PWM)

CH[2:0]=011 (ADCCSR)

OE1=1 (PWMOE)

PB7

*Reset state

31/144

ST72774/ST727754/ST72734

I/O PORTS (Cont’d)

Figure 19. PB0 to PB3

Alternate enable

1

DR

latch

Alternate

output

0

PAD

DDR

latch

DDR SEL

N-BUFFER

1

0

DR SEL

Alternate enable

V

SS

CMOS Schmitt Trigger

Alternate input

Figure 20. PB4 to PB7

V

DD

P-BUFFER

DR

latch

PULL-UP

DDR

latch

Analog enable

(ADC)

PAD

Analog

switch

DDR SEL

N-BUFFER

1

0

DR SEL

V

SS

CMOS Schmitt Trigger

32/144

ST72774/ST727754/ST72734

I/O PORTS (Cont’d)

4.1.5 Port C

The alternate functions are the PWM outputs for

PC2:7, HSYNCDIV (HSYNCO divided by 2) for

PC0 and the TMU input for PC1.

The available port pins of port C may be used as

general purpose I/O.

Table 10. Port C Description

I / O

Alternate Function

PORT C

Input*

Output

Signal

Condition

HSYNCDIVEN

=1

PC0

With pull-up

Push-pull

HSYNCDIV (push-pull)

(MISCR)

PC1

PC2

With pull-up

Push-pull

AV (active video) input (TMU)

10-bit output 3 (PWM)

-

OE2=1

(PWMOE)

OE3=1

(PWMOE)

PC3

PC4

PC5

PC6

PC7

With pull-up

Push-pull

10-bit output 4 (PWM)

10-bit output 5 (PWM)

10-bit output 6 (PWM)

10-bit output 7 (PWM)

10-bit output 8 (PWM)

OE4=1

(PWMOE)

OE5=1

(PWMOE)

OE6=1

(PWMOE)

OE7=1

(PWMOE)

* Reset State

33/144

ST72774/ST727754/ST72734

I/O PORTS (Cont’d)

Figure 21. PC0, PC2 to PC7

Alternate enable

1

V

DD

Alternate

output

0

P-BUFFER

DR

latch

PULL-UP

OC1E

DDR

latch

PAD

DDR SEL

N-BUFFER

1

0

DR SEL

OC1E

V

SS

CMOS Schmitt Trigger

Figure 22. PC1

V

DD

DR

latch

P-BUFFER

PULL-UP

DDR

latch

PAD

DDR SEL

N-BUFFER

1

0

DR SEL

V

SS

AV

CMOS Schmitt Trigger

34/144

ST72774/ST727754/ST72734

I/O PORTS (Cont’d)

4.1.6 Port D

Port D, bit 6 is switched to the alternate

(CLAMPOUT) by resetting the CLMPEN bit of the

ENR Register inside SYNC block.

The Port D I/O pins are normally used for the input

and output of video synchronization signals of the

Sync Processor, but are set to I/O Input with pull-

up upon reset. The I/O mode can be set

individually for each port bit to Input with pull-up

and output push-pull through the Port D DDR.

If the SYNC function is selected, Port D bit 5 and 3

MUST be set as input to enable the HFBACK or

VFBACK timing inputs.

The configuration to support the Sync Processor

requires that the SYNOP (bit7) and CLMPEN (bit6)

of the ENR (Enable Register of SYNC) is reset.

SYNOP enables port D bits 0,1 and CLMPEN

enables Port D bit 6 to the sync outputs.

Note: As these inputs are switched from normal

I/O functionality, the video synchronization signals

may also be monitored directly through the Port D

Data Register for such tasks as checking for the

presence of video signals or checking the polarity of

Horizontal and Vertical synchronization signals

(when the Sync Inputs are switched directly to the

outputs using the multiplexers of the Sync Proces-

sor).

Port D, bit 4:3 are the alternate inputs ITA, ITB, (for

the interrupt falling edge detector).

When a falling edge occurs on these inputs, an

interrupt will be generated depending on the status

of the INTX (ITAITE & ITBITE) bits in the MISCR

Register.

Table 11. Port D Description

I / O

Alternate Function

PORT D

Input*

Output

Signal

Condition

SYNOP=0

VSYNCO

PD0

With pull-up

Push-pull

(push pull output)

(ENR [SYNC])

HSYNCO

SYNOP=0

PD1

PD2

With pull-up

Push-pull

(push pull output)

(ENR [SYNC])

CSYNCI (input with TTL Schmitt

trigger & pull-up)

-

ITA (input with CMOS Schmitt

trigger & pull-up)

PD3

With pull-up

Push-pull

VFBACK (input with TTL Schmitt

trigger & pull-up)

ITB (input with CMOS Schmitt

trigger & pull-up)

PD4

PD5

With pull-up

Push-pull

HFBACK (input with TTL Schmitt

trigger & pull-up)

CLAMPOUT

CLMPEN=0

PD6

(push pull output)

(ENR [SYNC])

* Reset state

35/144

ST72774/ST727754/ST72734

I/O PORTS (Cont’d)

Figure 23. PD2 to PD5

V

DD

P-BUFFER

DR

PULL-UP

latch

DDR

latch

PAD

DDR SEL

N-BUFFER

1

0

DR SEL

V

SS

CMOS Schmitt Trigger

alternate input

CSYNCI Input

HFBACK Input

VFBACK Input

TTL Schmitt Trigger

Figure 24. PD0 to PD1

Alternate enable

1

0

VDD

Alternate

output

P-BUFFER

DR

PULL-UP

latch

Alternate enable

DDR

latch

PAD

DDR SEL

DR SEL

N-BUFFER

1

0

Alternate enable

CMOS Schmitt Trigger

V

SS

Alternate input

36/144

ST72774/ST727754/ST72734

I/O PORTS (Cont’d)

Figure 25. PD6

Alternate enable

1

0

VDD

Alternate

output

P-BUFFER

PULL-UP

DR

latch

Alternate enable

DDR

latch

PAD

DDR SEL

DR SEL

N-BUFFER

1

0

Alternate enable

CMOS Schmitt Trigger

V

SS

Alternate input

VSYNCI2 input

TTL Schmitt Trigger

37/144

ST72774/ST727754/ST72734

I/O PORTS (Cont’d)

4.1.7 Register Description

Data Registers (PxDR)

Data Direction Registers (PxDDR)

Read/Write

Reset Value: 0000 0000 (00h)

Read/Write

Reset Value: 0000 0000 (00h) (as inputs)

7

0

7

0

MSB

LSB

MSB

LSB

Table 12. I/O Ports Register Map

Address

(Hex.)

Register

Name

7

6

5

4

3

2

1

0

00

01

02

03

04

05

06

07

PADR

PADDR

PBDR

MSB

LSB

PBDDR

PCDR

PCDDR

PDDR

PDDDR

38/144

ST72774/ST727754/ST72734

4.2 WATCHDOG TIMER (WDG)

4.2.1 Introduction

The Watchdog timer is used to detect the

refreshes the counter’s contents before the T6 bit

becomes cleared.

occurrence of a software fault, usually generated

by external interference or by unforeseen logical

conditions, which causes the application program

to abandon its normal sequence. The Watchdog

circuit generates an MCU reset on expiry of a

programmed time period, unless the program

4.2.2 Main Features

■ Programmable timer (64 increments of 49152

CPU cycles)

■ Programmable reset

■ Reset (if watchdog activated) when the T6 bit

reaches zero

Figure 26. Watchdog Block Diagram

RESET

WATCHDOG CONTROL REGISTER (CR)

T5

T0

T6

WDGA

T1

T4

T2

T3

7-BIT DOWNCOUNTER

CLOCK DIVIDER

f

CPU

÷49152

4.2.3 Functional Description

The counter value stored in the CR register (bits

T6:T0), is decremented every 49,152 machine

cycles, and the length of the timeout period can be

programmed by the user in 64 increments.

operation to prevent an MCU reset. The value to

be stored in the CR register must be between FFh

and C0h (see Table 13 . Watchdog Timing (fCPU =

8 MHz)):

If the watchdog is activated (the WDGA bit is set)

and when the 7-bit timer (bits T6:T0) rolls over

from 40h to 3Fh (T6 becomes cleared), it initiates a

reset cycle pulling low the reset pin for typically

500ns.

– The WDGA bit is set (watchdog enabled)

– The T6 bit is set to prevent generating an imme-

diate reset

– The T5:T0 bits contain the number of increments

which represents the time delay before the

watchdog produces a reset.

The application program must write in the CR

register at regular intervals during normal

39/144

ST72774/ST727754/ST72734

Table 13. Watchdog Timing (f

= 8 MHz)

4.2.5 Register Description

CONTROL REGISTER (CR)

CPU

CR Register

initial value

WDG timeout period

(ms)

Read/Write

Max

Min

FFh

C0h

393.216

6.144

Reset Value: 0111 1111 (7Fh)

7

0

WDGA T6

T5

T4

T3

T2

T1

T0

Notes: Following a reset, the watchdog is

disabled. Once activated it cannot be disabled,

except by a reset.

Bit 7 = WDGA Activation bit.

This bit is set by software and only cleared by

hardware after a reset. When WDGA = 1, the

watchdog can generate a reset.

The T6 bit can be used to generate a software

reset (the WDGA bit is set and the T6 bit is

cleared).

0: Watchdog disabled

1: Watchdog enabled

4.2.4 Interrupts

None.

Bit 6:0 = T[6:0] 7-bit timer (MSB to LSB).

These bits contain the decremented value. A reset

is produced when it rolls over from 40h to 3Fh (T6

becomes cleared).

Table 14. Watchdog Timer Register Map and Reset Values

Address

(Hex.)

Register

Label

7

6

5

4

3

2

1

0

WDGCR

WDGA

0

T6

1

T5

1

T4

1

T3

1

T2

1

T1

1

T0

1

08

Reset Value

40/144

ST72774/ST727754/ST72734

4.3 16-BIT TIMER (TIM)

4.3.1 Introduction

4.3.3 Functional Description

The timer consists of a 16-bit free-running counter

driven by a programmable prescaler.

4.3.3.1 Counter

The principal block of the Programmable Timer is a

16-bit free running counter and its associated 16-

bit registers:

It may be used for a variety of purposes, including

pulse length measurement of up to two input

signals (input capture) or generation of up to two

output waveforms (output compare and PWM).

Counter Registers

– Counter High Register (CHR) is the most sig-

nificant byte (MSB).

Pulse lengths and waveform periods can be

modulated from a few microseconds to several

milliseconds using the timer prescaler and the

CPU clock prescaler.

– Counter Low Register (CLR) is the least sig-

nificant byte (LSB).

Alternate Counter Registers

– Alternate Counter High Register (ACHR) is the

most significant byte (MSB).

4.3.2 Main Features

■ Programmable prescaler: f

divided by 2, 4 or

cpu

– Alternate Counter Low Register (ACLR) is the

least significant byte (LSB).

These two read-only 16-bit registers contain the

same value but with the difference that reading the

ACLR register does not clear the TOF bit (overflow

flag), (see note page 43).

8.

■ Overflow status flag and maskable interrupt

■ External clock input (must be at least 4 times

slower than the CPU clock speed) with the

choice of active edge

■ Output compare functions with

Writing in the CLR register or ACLR register resets

the free running counter to the FFFCh value.

– 2 dedicated 16-bit registers

– 2 dedicated programmable signals

– 2 dedicated status flags

The timer clock depends on the clock control bits

of the CR2 register, as illustrated in Table 15 Clock

Control Bits. The value in the counter register

repeats every 131.072, 262.144 or 524.288

internal processor clock cycles depending on the

CC1 and CC0 bits.

– 1 dedicated maskable interrupt

■ Input capture functions with

– 2 dedicated 16-bit registers

– 2 dedicated active edge selection signals

– 2 dedicated status flags

– 1 dedicated maskable interrupt

■ Pulse width modulation mode (PWM)

■ One pulse mode

■ 5 alternate functions on I/O ports*

The Block Diagram is shown in Figure 27.

Note: Some external pins are not available on all devices.

Refer to the device pin out description.

41/144

ST72774/ST727754/ST72734

16-BIT TIMER (Cont’d)

Figure 27. Timer Block Diagram

ST7 INTERNAL BUS

CPU CLOCK

MCU-PERIPHERAL INTERFACE

8 low

8-bit

8 high

8

buffer

h

w

h

w

h

w

h

w

EXEDG

i

o

i

o

i

o

i

lo

16

INPUT

CAPTURE

REGISTER

INPUT

CAPTURE

REGISTER

OUTPUT

COMPARE

REGISTER

OUTPUT

COMPARE

REGISTER

16 BIT

FREE RUNNING

1/2

1/4

1/8

COUNTER

1

2

COUNTER

ALTERNATE

REGISTER

16

CC1 CC0

TIMER INTERNAL BUS

16

OVERFLOW

DETECT

CIRCUIT

EXTCLK

EDGE DETECT

CIRCUIT1

OUTPUT COMPARE

CIRCUIT

ICAP1

ICAP2

6

EDGE DETECT

CIRCUIT2

OCMP1

OCMP2

LATCH1

LATCH2

ICF1 OCF1 TOF ICF2 OCF2

0

SR

EXEDG

ICIE OCIE TOIE FOLV2FOLV1OLVL2 IEDG1 OLVL1

OC1E

OPM PWM CC1 CC0 IEDG2

OC2E

CR1

CR2

TIMER INTERRUPT

42/144

ST72774/ST727754/ST72734

16-BIT TIMER (Cont’d)

16-bit read sequence: (from either the Counter

Clearing the overflow interrupt request is done by:

Register or the Alternate Counter Register).

1. Reading the SR register while the TOF bit is

set.

Beginning of the sequence

2. An access (read or write) to the CLR register.

Notes: The TOF bit is not cleared by accesses to

Read MSB

At t0

LSB is buffered

ACLR register. This feature allows simultaneous

use of the overflow function and reads of the free

running counter at random times (for example, to

measure elapsed time) without the risk of clearing

the TOF bit erroneously.

Other

instructions

Returns the buffered

LSB value at t0

Read LSB

At t0 +Dt

The timer is not affected by WAIT mode.

Sequence completed

4.3.3.2 External Clock

The external clock (where available) is selected if

CC0=1 and CC1=1 in CR2 register.

The user must read the MSB first, then the LSB

value is buffered automatically.

This buffered value remains unchanged until the

16-bit read sequence is completed, even if the

user reads the MSB several times.

The status of the EXEDG bit determines the type

of level transition on the external clock pin

EXTCLK that will trigger the free running counter.

After a complete reading sequence, if only the CLR

register or ACLR register are read, they return the

LSB of the count value at the time of the read.

The counter is synchronised with the falling edge

of the internal CPU clock.

At least four falling edges of the CPU clock must

occur between two consecutive active edges of

the external clock; thus the external clock

frequency must be less than a quarter of the CPU

clock frequency.

An overflow occurs when the counter rolls over

from FFFFh to 0000h then:

– The TOF bit of the SR register is set.

– A timer interrupt is generated if:

– TOIE bit of the CR1register is set and

– I bit of the CC register is cleared.

If one of these conditions is false, the interrupt

remains pending to be issued as soon as they are

both true.

43/144

ST72774/ST727754/ST72734

16-BIT TIMER (Cont’d)

Figure 28. Counter Timing Diagram, internal clock divided by 2

CPU CLOCK

INTERNAL RESET

TIMER CLOCK

FFFD FFFE FFFF 0000 0001 0002 0003

COUNTER REGISTER

OVERFLOW FLAG TOF

Figure 29. Counter Timing Diagram, internal clock divided by 4

CPU CLOCK

INTERNAL RESET

TIMER CLOCK

FFFC

FFFD

0000

0001

COUNTER REGISTER

OVERFLOW FLAG TOF

Figure 30. Counter Timing Diagram, internal clock divided by 8

CPU CLOCK

INTERNAL RESET

TIMER CLOCK

0000

FFFC

FFFD

COUNTER REGISTER

OVERFLOW FLAG TOF

44/144

ST72774/ST727754/ST72734

16-BIT TIMER (Cont’d)

4.3.3.3 Input Capture

In this section, the index, i, may be 1 or 2.

– Select the edge of the active transition on the

ICAP1 pin with the IEDG1 bit.

When an input capture occurs:

The two input capture 16-bit registers (IC1R and

IC2R) are used to latch the value of the free

running counter after a transition detected by the

ICAPi pin (see figure 5).

– ICFi bit is set.

– The ICiR register contains the value of the free

running counter on the active transition on the

ICAPi pin (see Figure 32).

MS Byte

LS Byte

– A timer interrupt is generated if the ICIE bit is set

and the I bit is cleared in the CC register. Other-

wise, the interrupt remains pending until both

conditions become true.

ICiR

ICiHR

ICiLR

ICi Rregister is a read-only register.

The active transition is software programmable

through the IEDGi bit of the Control Register (CRi).

Clearing the Input Capture interrupt request is

done by:

1. Reading the SR register while the ICFi bit is set.

2. An access (read or write) to the ICiLR register.

Timing resolution is one count of the free running

counter: (f

).

CPU/(CC1.CC0)

Procedure

After reading the ICiHR register, transfer of input

capture data is inhibited until the ICiLR register is

also read.

To use the input capture function select the

following in the CR2 register:

The ICiR register always contains the free running

counter value which corresponds to the most

recent input capture.

– Select the timer clock (CC1-CC0) (see Table 15

Clock Control Bits).

– Select the edge of the active transition on the

ICAP2 pin with the IEDG2 bit.

And select the following in the CR1 register:

– Set the ICIE bit to generate an interrupt after an

input capture.

45/144

ST72774/ST727754/ST72734

16-BIT TIMER (Cont’d)

Figure 31. Input Capture Block Diagram

ICAP1

(Control Register 1) CR1

IEDG1

EDGE DETECT

CIRCUIT2

EDGE DETECT

CIRCUIT1

ICIE

ICAP2

(Status Register) SR

ICF1

ICF2

0

IC1R

IC2R

(Control Register 2) CR2

16-BIT

16-BIT FREE RUNNING

IEDG2

CC0

CC1

COUNTER

Figure 32. Input Capture Timing Diagram

TIMER CLOCK

FF01

FF02

FF03

COUNTER REGISTER

ICAPi PIN

ICAPi FLAG

FF03

ICAPi REGISTER

Note: Active edge is rising edge.

46/144

ST72774/ST727754/ST72734

16-BIT TIMER (Cont’d)

4.3.3.4 Output Compare

In this section, the index, i, may be 1 or 2.

– A timer interrupt is generated if the OCIE bit is

set in the CR2 register and the I bit is cleared in

the CC register (CC).

This function can be used to control an output

waveform or indicating when a period of time has

elapsed.

Clearing the output compare interrupt request is

done by:

3. Reading the SR register while the OCFi bit is

set.

When a match is found between the Output

Compare register and the free running counter, the

output compare function:

4. An access (read or write) to the OCiLR register.

Note: After a processor write cycle to the OCiHR register,

the output compare function is inhibited until the

OCiLR register is also written.

– Assigns pins with a programmable value if the

OCIE bit is set

– Sets a flag in the status register

If the OCiE bit is not set, the OCMPi pin is a

general I/O port and the OLVLi bit will not appear

when match is found but an interrupt could be

generated if the OCIE bit is set.

– Generates an interrupt if enabled

Two 16-bit registers Output Compare Register 1

(OC1R) and Output Compare Register 2 (OC2R)

contain the value to be compared to the free

running counter each timer clock cycle.

The value in the 16-bit OCiR register and the OLVi

bit should be changed after each successful

comparison in order to control an output waveform

or establish a new elapsed timeout.

MS Byte

OCiHR

LS Byte

OCiLR

OCiR

The OCiR register value required for a specific

timing application can be calculated using the

following formula:

These registers are readable and writable and are

not affected by the timer hardware. A reset event

changes the OCiR value to 8000h.

∆t f

* CPU

(CC1.CC0)

∆ OCiR =

Timing resolution is one count of the free running

counter: (f

).

CPU/(CC1.CC0)

Procedure

Where:

∆t

= Desired output compare period (in

seconds)

To use the output compare function, select the

following in the CR2 register:

f

= Internal clock frequency

CPU

– Set the OCiE bit if an output is needed then the

OCMPi pin is dedicated to the output compare i

function.

CC1-CC0 = Timer clock prescaler

The following procedure is recommended to

prevent the OCFi bit from being set between the

time it is read and the write to the OCiR register:

– Select the timer clock (CC1-CC0) (see Table 15

Clock Control Bits).

And select the following in the CR1 register:

– Write to the OCiHR register (further compares

are inhibited).

– Select the OLVLi bit to applied to the OCMPi pins

after the match occurs.

– Read the SR register (first step of the clearance

of the OCFi bit, which may be already set).

– Set the OCIE bit to generate an interrupt if it is

needed.

When match is found:

– Write to the OCiLR register (enables the output

compare function and clears the OCFi bit).

– OCFi bit is set.

– The OCMPi pin takes OLVLi bit value (OCMPi

pin latch is forced low during reset and stays low

until valid compares change it to a high level).

47/144

ST72774/ST727754/ST72734

16-BIT TIMER (Cont’d)

Figure 33. Output Compare Block Diagram

16 BIT FREE RUNNING

OC1E

CC1 CC0

OC2E

COUNTER

(Control Register 2) CR2

16-bit

(Control Register 1) CR1

OUTPUT COMPARE

CIRCUIT

Latch

1

OCIE

OLVL2

OLVL1

OCMP1

OCMP2

Latch

2

16-bit

OCF1

OCF2

0

OC2R

OC1R

(Status Register) SR

Figure 34. Output Compare Timing Diagram, Internal Clock Divided by 2

INTERNAL CPU CLOCK

TIMER CLOCK

FFFC FFFD FFFD FFFE

CPU writes FFFF

0000

FFFF

COUNTER

OUTPUT COMPARE REGISTER

COMPARE REGISTER LATCH

OCFi AND OCMPi PIN (OLVLi=1)

48/144

ST72774/ST727754/ST72734

16-BIT TIMER (Cont’d)

4.3.3.5 Forced Compare Mode

In this section i may represent 1 or 2.

– Set the OPM bit.

– Select the timer clock CC1-CC0 (see Table 15

Clock Control Bits).

Load the OC1R register with the value

The following bits of the CR1 register are used:

corresponding to the length of the pulse (see the

formula in Section 4.3.3.7).

FOLV2 FOLV1 OLVL2

OLVL1

One pulse mode cycle

When the FOLVi bit is set, the OLVLi bit is copied

to the OCMPi pin. The FOLVi bit is not cleared by

software, only by a chip reset. The OLVi bit has to

be toggled in order to toggle the OCMPi pin when

it is enabled (OCiE bit=1).

Counter is

initialized

to FFFCh

When

event occurs

on ICAP1

OCMP1 = OLVL2

OCMP1 = OLVL1

The OCFi bit is not set, and thus no interrupt

request is generated.

When

Counter

= OC1R

4.3.3.6 One Pulse Mode

One Pulse mode enables the generation of a pulse

when an external event occurs. This mode is

selected via the OPM bit in the CR2 register.

The one pulse mode uses the Input Capture1

function and the Output Compare1 function.

Then, on a valid event on the ICAP1 pin, the

counter is initialized to FFFCh and OLVL2 bit is

loaded on the OCMP1 pin. When the value of the

counter is equal to the value of the contents of the

OC1R register, the OLVL1 bit is output on the

OCMP1 pin, (See Figure 35).

Procedure

To use one pulse mode, select the following in the

the CR1 register:

– Using the OLVL1 bit, select the level to be ap-

plied to the OCMP1 pin after the pulse.

Note: The OCF1 bit cannot be set by hardware in one

pulse mode but the OCF2 bit can generate an Out-

put Compare interrupt.

– Using the OLVL2 bit, select the level to be ap-

plied to the OCMP1 pin during the pulse.

The ICF1 bit is set when an active edge occurs and

can generate an interrupt if the ICIE bit is set.

– Select the edge of the active transition on the

ICAP1 pin with the IEDG1 bit.

And select the following in the CR2 register:

When the Pulse Width Modulation (PWM) and

One Pulse Mode (OPM) bits are both set, the

PWM mode is the only active one.

– Set the OC1E bit, the OCMP1 pin is then dedi-

cated to the Output Compare 1 function.

Figure 35. One Pulse Mode Timing

....

FFFC FFFD FFFE

2ED0 2ED1 2ED2

2ED3

FFFC FFFD

COUNTER

ICAP1

OLVL2

OLVL1

OLVL2

OCMP1

compare1

Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1

49/144

ST72774/ST727754/ST72734

16-BIT TIMER (Cont’d)

4.3.3.7 Pulse Width Modulation Mode

Pulse Width Modulation mode enables the

generation of a signal with a frequency and pulse

length determined by the value of the OC1R and

OC2R registers.

The OCiR register value required for a specific

timing application can be calculated using the

following formula:

t f

* CPU

(CC1.CC0)

- 5

OCiR Value =

The pulse width modulation mode uses the

complete Output Compare 1 function plus the

OC2R register.

Where:

– t = Desired output compare period (seconds)

– f = Internal clock frequency (see Miscella-

Procedure

CPU

neous register)

To use pulse width modulation mode select the

following in the CR1 register:

– CC1-CC0 = Timer clock prescaler

The Output Compare 2 event causes the counter

to be initialized to FFFCh (See Figure 36).

– Using the OLVL1 bit, select the level to be ap-

plied to the OCMP1 pin after a successful com-

parison with OC1R register.

Pulse Width Modulation cycle

– Using the OLVL2 bit, select the level to be ap-

plied to the OCMP1 pin after a successful com-

parison with OC2R register.

When

Counter

= OC1R

OCMP1 = OLVL1

OCMP1 = OLVL2

And select the following in the CR2 register:

– Set OC1E bit: the OCMP1 pin is then dedicated

to the output compare 1 function.

When

Counter

= OC2R

– Set the PWM bit.

– Select the timer clock (CC1-CC0) (see Table 15

Clock Control Bits).

Load the OC2R register with the value

Counter is reset

to FFFCh

corresponding to the period of the signal.

Note: After a write instruction to the OCiHR register, the

output compare function is inhibited until the OCiLR

register is also written.

Load the OC1R register with the value

corresponding to the length of the pulse if

(OLVL1=0 and OLVL2=1).

The OCF1 and OCF2 bits cannot be set by

hardware in PWM mode therefore the Output

Compare interrupt is inhibited. The Input Capture

interrupts are available.

If OLVL1=1 and OLVL2=0 the length of the pulse is

the difference between the OC2R and OC1R

registers.

When the Pulse Width Modulation (PWM) and

One Pulse Mode (OPM) bits are both set, the

PWM mode is the only active one.

Figure 36. Pulse Width Modulation Mode Timing

34E2 FFFC FFFD FFFE

COUNTER

2ED0 2ED1 2ED2

34E2 FFFC

OLVL2

OLVL1

OLVL2

OCMP1

compare2

compare1

compare2

Note: OC1R=2ED0h, OC2R=34E2, OLVL1=0, OLVL2= 1

50/144

ST72774/ST727754/ST72734

4.3.4 Register Description

Each Timer is associated with three control and

status registers, and with six pairs of data registers

(16-bit values) relating to the two input captures,

the two output compares, the counter and the

alternate counter.

Bit 4 = FOLV2 Forced Output Compare 2.

This bit is not cleared by software, only by a chip

reset.

0: No effect.

1:Forces the OLVL2 bit to be copied to the

OCMP2 pin.

Bit 3 = FOLV1 Forced Output Compare 1.

This bit is not cleared by software, only by a chip

reset.

CONTROL REGISTER 1 (CR1)

Read/Write

Reset Value: 0000 0000 (00h)

0: No effect.

1: Forces OLVL1 to be copied to the OCMP1

7

0

pin.

ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1

Bit 2 = OLVL2 Output Level 2.

This bit is copied to the OCMP2 pin whenever a

successful comparison occurs with the OC2R

register and OCxE is set in the CR2 register. This

value is copied to the OCMP1 pin in One Pulse

Mode and Pulse Width Modulation mode.

Bit 7 = ICIE Input Capture Interrupt Enable.

0: Interrupt is inhibited.

1: A timer interrupt is generated whenever the

ICF1 or ICF2 bit of the SR register is set.

Bit 6 = OCIE Output Compare Interrupt Enable.

0: Interrupt is inhibited.

Bit 1 = IEDG1 Input Edge 1.

1: A timer interrupt is generated whenever the

This bit determines which type of level transition on

the ICAP1 pin will trigger the capture.

OCF1 or OCF2 bit of the SR register is set.

0: A falling edge triggers the capture.

1: A rising edge triggers the capture.

Bit 5 = TOIE Timer Overflow Interrupt Enable.

0: Interrupt is inhibited.

1: A timer interrupt is enabled whenever the

Bit 0 = OLVL1 Output Level 1.

TOF bit of the SR register is set.

The OLVL1 bit is copied to the OCMP1 pin

whenever a successful comparison occurs with

the OC1R register and the OC1E bit is set in the

CR2 register.

51/144

ST72774/ST727754/ST72734

16-BIT TIMER (Cont’d)

CONTROL REGISTER 2 (CR2)

Bit 3, 2 = CC1-CC0 Clock Control.

Read/Write

The value of the timer clock depends on these bits:

Reset Value: 0000 0000 (00h)

Table 15. Clock Control Bits

7

0

CC1

CC0

Timer Clock

f_CPU/ 4

0

1

0

1

0

OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG

f_CPU/ 2

f_CPU/ 8

Bit 7 = OC1E Output Compare 1 Enable.

External Clock (where

available)

1

0: Output Compare 1 function is enabled, but

the OCMP1 pin is a general I/O.

1: Output Compare 1 function is enabled, the

OCMP1 pin is dedicated to the Output Com-

pare 1 capability of the timer.

Bit 1 = IEDG2 Input Edge 2.

This bit determines which type of level transition on

the ICAP2 pin will trigger the capture.

Bit 6 = OC2E Output Compare 2 Enable.

0: A falling edge triggers the capture.

1: A rising edge triggers the capture.

0: Output Compare 2 function is enabled, but

the OCMP2 pin is a general I/O.

1: Output Compare 2 function is enabled, the

OCMP2 pin is dedicated to the Output Com-

pare 2 capability of the timer.

Bit 0 = EXEDG External Clock Edge.

This bit determines which type of level transition on

the external clock pin EXTCLK will trigger the free

running counter.

Bit 5 = OPM One Pulse Mode.

0: A falling edge triggers the free running coun-

0: One Pulse Mode is not active.

ter.

1: One Pulse Mode is active, the ICAP1 pin can

be used to trigger one pulse on the OCMP1

pin; the active transition is given by the

IEDG1 bit. The length of the generated pulse

depends on the contents of the OC1R regis-

ter.

1: A rising edge triggers the free running coun-

ter.

Bit 4 = PWM Pulse Width Modulation.

0: PWM mode is not active.

1: PWM mode is active, the OCMP1 pin outputs

a programmable cyclic signal; the length of

the pulse depends on the value of OC1R reg-

ister; the period depends on the value of

OC2R register.

52/144

ST72774/ST727754/ST72734

16-BIT TIMER (Cont’d)

STATUS REGISTER (SR)

Read Only

Bit 2-0 = Unused.

Reset Value: 0000 0000 (00h)

INPUT CAPTURE 1 HIGH REGISTER (IC1HR)

The three least significant bits are not used.

Read Only

Reset Value: Undefined

7

0

This is an 8-bit read only register that contains the

high part of the counter value (transferred by the

input capture 1 event).

ICF1 OCF1 TOF ICF2 OCF2

Bit 7 = ICF1 Input Capture Flag 1.

7

0

0: No input capture (reset value).

1: An input capture has occurred. To clear this

bit, first read the SR register, then read or

write the low byte of the IC1R (IC1LR) regis-

ter.

MSB

LSB

INPUT CAPTURE 1 LOW REGISTER (IC1LR)

Bit 6 = OCF1 Output Compare Flag 1.

Read Only

Reset Value: Undefined

0: No match (reset value).

1: The content of the free running counter has

matched the content of the OC1R register. To

clear this bit, first read the SR register, then

read or write the low byte of the OC1R

(OC1LR) register.

This is an 8-bit read only register that contains the

low part of the counter value (transferred by the

input capture 1 event).

Bit 5 = TOF Timer Overflow.

7

0

0: No timer overflow (reset value).

MSB

LSB

1:The free running counter rolled over from

FFFFh to 0000h. To clear this bit, first read

the SR register, then read or write the low

byte of the CR (CLR) register.

OUTPUT COMPARE

(OC1HR)

1

HIGH REGISTER

Read/Write

Reset Value: 1000 0000 (80h)

Note: Reading or writing the ACLR register does not clear

TOF.

This is an 8-bit register that contains the high part

of the value to be compared to the CHR register.

Bit 4 = ICF2 Input Capture Flag 2.

0: No input capture (reset value).

1: An input capture has occurred.To clear this

bit, first read the SR register, then read or

write the low byte of the IC2R (IC2LR) regis-

ter.

7

0

MSB

LSB

Bit 3 = OCF2 Output Compare Flag 2.

OUTPUT COMPARE

(OC1LR)

1

LOW REGISTER

0: No match (reset value).

1: The content of the free running counter has

matched the content of the OC2R register. To

clear this bit, first read the SR register, then

read or write the low byte of the OC2R

(OC2LR) register.

Read/Write

Reset Value: 0000 0000 (00h)

This is an 8-bit register that contains the low part of

53/144

ST72774/ST727754/ST72734

16-BIT TIMER (Cont’d)

OUTPUT COMPARE

2

HIGH REGISTER

7

0

(OC2HR)

Read/Write

MSB

LSB

Reset Value: 1000 0000 (80h)

ALTERNATE COUNTER HIGH REGISTER

(ACHR)

This is an 8-bit register that contains the high part

of the value to be compared to the CHR register.

Read Only

Reset Value: 1111 1111 (FFh)

7

0

This is an 8-bit register that contains the high part

of the counter value.

MSB

LSB

7

0

OUTPUT COMPARE

(OC2LR)

2

LOW REGISTER

MSB

LSB

Read/Write

Reset Value: 0000 0000 (00h)

ALTERNATE COUNTER LOW REGISTER

(ACLR)

This is an 8-bit register that contains the low part of

the value to be compared to the CLR register.

Read/Write

Reset Value: 1111 1100 (FCh)

7

0

This is an 8-bit register that contains the low part of

the counter value. A write to this register resets the

counter. An access to this register after an access

to SR register does not clear the TOF bit in SR

register.

MSB

LSB

COUNTER HIGH REGISTER (CHR)

Read Only

Reset Value: 1111 1111 (FFh)

7

0

This is an 8-bit register that contains the high part

of the counter value.

MSB

LSB

7

0

INPUT CAPTURE 2 HIGH REGISTER (IC2HR)

MSB

LSB

Read Only

Reset Value: Undefined

This is an 8-bit read only register that contains the

high part of the counter value (transferred by the

Input Capture 2 event).

COUNTER LOW REGISTER (CLR)

Read/Write

Reset Value: 1111 1100 (FCh)

7

0

This is an 8-bit register that contains the low part of

the counter value. A write to this register resets the

counter. An access to this register after accessing

the SR register clears the TOF bit.

MSB

LSB

INPUT CAPTURE 2 LOW REGISTER (IC2LR)

Read Only

Reset Value: Undefined

54/144

ST72774/ST727754/ST72734

16-BIT TIMER (Cont’d)

Table 16. 16-Bit Timer Register Map

Address

(Hex.)

Register

Name

7

6

5

4

3

2

1

0

11

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

CR2

OC1E

ICIE

OC2E

OCIE

OCF1

OPM

TOIE

TOF

PWM

FOLV2

ICF2

CC1

FOLV1

OCF2

CC0

OLVL2

0

IEDG2

IEDG1

0

EXEDG

OLVL1

0

CR1

SR

ICF1

MSB

IC1HR

IC1LR

OC1HR

OC1LR

CHR

LSB

CLR

ACHR

ACLR

IC2HR

IC2LR

OC2HR

OC2LR

55/144

ST72774/ST727754/ST72734

4.4 SYNC PROCESSOR (SYNC)

4.4.1 Introduction

The Sync processor handles all the management

– Control the sync output polarities

– Generate free-running frequencies

– Generate a video blanking signal

– Generate a clamping signal or a Moire signal

tasks of the video synchronization signals, and is

used with the timer and software to provide

information and status on the video standard and

timings. This block supports multiple video

standards such as: Separate Sync, Composite

Sync and (via an external extractor) Sync on

Green. The internal clock in the Sync processor is

4 MHz.

■ Analyzer Mode

– Measure the number of scan lines per frame to

simplify OSD vertical centering

– Detect HSYNCI reaching too high a frequency

– Detect pre/post equalization pulses

– Measure the low level of HSYNCO or HFBACK

4.4.2 Main Features

■ Input Processing

■ Corrector Mode

– Presence of incoming signals (edge detection)

– Read the HSYNCI / VSYNCI input signal levels

– Measure the signal periods

– Inhibit Pre/Post equalization pulses

– Program VSYNCO pulse width extension

– Extend VSYNCO pulse widths during:

post-equalization pulse detection only

– Detect the sync polarities

– Detect the composite sync and extract VSYNCO

pre and post-equalization pulse detection

Note: Some external pins are not available on all devices.

■ Output Processing

Refer to the device pinout description.

Figure 37. Sync Processor Block Diagram

ICAP1 TIMER

Polarity

V Sync O

Polarity

HVGEN

0

Latch

Pulse Detect

Detector

1

SYNOP

VSYNCI1

VSYNCI2

VSYNCI

V Sync

Correction

VSYNCO

1

LCV1

Vsync*

1

0

BLKEN

Capture

Register

Control

Logic

VFBACK

LD

HVSEL

Blanking

Generator

BLANKOUT

LCV1

0

FBSEL

V

S

Y

N

C

O

Up / Down

EN

VSYNC Generator

40 - 200 Hz

Typical Pulse Width

20 - 256 µs

Sync

&

Edge

Detect

5-Bit Counter

CLK

0

HFBACK

Sync Generator

Sync Analyzer

Sync Corrector

Hardware Block

1

INT

(see note)

f

Latch

00

Latch

1F

match

HSYNC Generator

15 - 200 kHz

Duty cycle range

3 - 40 %

LCV0

FBSEL

match

(Positive polarity)

Prescaler

ICAP2 TIMER

H-Inhibit

Latch

Pulse Detect

HVSEL

1

PSCD

ON/OFF

HSYNCI1

HSYNCI2

CSYNCI

0

SYNOP

HSYNCI / CSYNCI

HSYNCO

H Sync O

Polarity

0

1

SCI0

1

Back Porch

Clamp

Generator

Latch

Clamp

Polarity

H Sync O

Correction

Pulse Detect

0

HVGEN

CLPINV

Other

HFBACK

Note: CLK is f

in fast mode (see note in Clock System section)

INT/2

00

CLAMPOUT

CLMPEN

BP1, BP0

VR02071C

VFBACK

Pull-Up Resistor (if existing)

56/144

ST72774/ST727754/ST72734

SYNC PROCESSOR (SYNC) (Cont’d)

4.4.3 Input Signals

The Sync Processor has the following inputs (TTL

4.4.5 Output Signals

The Sync Processor has the following outputs:

level):

HSYNCO Horizontal Sync Output

– VSYNCI1 Vertical Sync input1

Enable: SYNOP bit in ENR register

– HSYNCI1 Horizontal Sync input1 or Composite

sync

Programmable polarity:

HS0/HS1 bits in MCR register

– VSYNCI2 Vertical Sync input2

In case of composite sync signal, the signal can be

blanked by software during the vertical period

(HINH bit in ENR register).

– HSYNCI2 Horizontal Sync input2 or Composite

sync

Note: The above input pairs can be used for DSUB or

BNC connectors. To select these inputs use the

HVSEL bit in the POLR register.

In case of separate sync, no blanking is generated.

– CSYNCI Sync on Green (external extractor)

VSYNCO Vertical Sync Output

Enable: SYNOP bit in ENR register

Note: If the CSYNCI pin is needed for another I/O func-

tion, the composite sync signal can be connected to

HSYNCI using the SCI0 bit in the MCR register.

Programmable polarity:

VOP bit in the MCR register

– HFBACK Horizontal Flyback input

– VFBACK Vertical Flyback input

In case of composite sync the delay of the

extracted Vsync signal is:

minimum: 500ns + HSYNCO pulse width

4.4.4 Input Signal Waveforms

maximum: 8750ns (max. threshold in ex-

traction mode)

– The input signals must contain only synchroniza-

tion pulses. In case of serration pulses on CSYN-

CI/HSYNCI, the pulse width should be less than

8µs.

– The VSYNCI signal is internally connected to

Timer Input Capture 1 (ICAP1).

– The HSYNCI or CSYNCI signal, prescaled by

256, is internally connected to Timer Input Cap-

ture 2 (ICAP2).

– Typical timing range: See Figure 38 and 39

– If the timer clock is 2 MHz (external oscillator fre-

quency 24 MHz):

PV accuracy = +/- 1 Timer clock (500ns)

PH*256 accuracy = +/- 1 Timer clock (500ns)

(PV= Vertical pulse, PH = Horizontal pulse)

57/144

ST72774/ST727754/ST72734

SYNC PROCESSOR (SYNC) (Cont’d)

Figure 38. Typical Horizontal Sync Input Timing

or:

5µs < Typical Hor. Total time < 66.66µs

(200kHz)

(15kHz)

Maximum Sync. pulse width: 7µs

Note: Minimum HPeriod: 500ns + S/W interrupt servicing time

VR01961

(1 Timer Clock)

Figure 39. Vertical Sync Input Timing

or:

5ms < Typical Ver. Total time < 25ms

(200Hz)

(40Hz)

Typical Sync. pulse width: 0.0384ms - 0.600ms

Note: Minimum VPeriod: 500ns + S/W interrupt servicing time

VR01961A

(1 Timer Clock)

58/144

ST72774/ST727754/ST72734

SYNC PROCESSOR (SYNC) (Cont’d)

ClampOut and Moire Signal

Moire Signal

Clamp Output signal

The Moire output signal is available (instead of the

clamping signal) to reduce the screen Moire effect

and improve color transitions.

The clamping pulse generator can control the

pulse width and polarity signal and can be

configured as pseudo-front porch or back porch.

The CLAMPOUT pin is alternatively used to output

a Moire signal.

To use the ClampOut signal:

The output signal toggles at each HFBACK rising

edge. After each VFBACK falling edge, the value

of the Moire output is the opposite of the previous

one, independent of the number of HFBACK

pulses during the VFBACK low level.

– Select the Clamping Pulse width:

BP0/BP1 bits in MCR register

– Program the Clamp polarity:

CLPINV bit in POLR register

– Select the ClampOut signal as back-porch (after

falling edge of HSYNCO) or pseudo-front porch

(after the rising edge of HSYNCO):

To use the Moire signal:

HS0/HS1 bits in MCR register.

– Enable the CLAMPOUT signal:

CLMPEN bit in ENR register

– Select the Moire signal:

Reset the BP0/BP1 bits in MCR register

– Enable the output signal:

CLMPEN bit in ENR register

Figure 40. Clamping Pulse (CLAMPOUT) Delay

HSYNCO

Maximum delay:

(Fixed delay of 10 to 30ns) + (f

/2) = approx. 110ns.

OSC

-

CLAMPOUT

Programmable clamping width: 0, 167ns, 333ns, 666ns

59/144

ST72774/ST727754/ST72734

Figure 41. Moire Output (instead of Clamping Output)

VFBACK

HFBACK

Moire

4.4.5.1 Blanking output signal

To use the video blanking signal:

– Program the polarity:

The Video Blanking function uses VSYNCO,

HFBACK, VFBACK as input signals and

BLANKOUT output as Video Blanking Output. This

output pin is a 5V open-drain output and can be

AND-wired with any external video blanking signal.

BLKINV bit in POLR register

– Enable the BLANKOUT output:

BLKEN bit in ENR register

Note: HFBACK, VFBACK, VSYNCO signals must have

positive polarity.

Figure 42. Video Blanking Stage Simplified Schematic

To Edge detector (LATR)

HFBACK

To Edge detector (LATR)

BLANKOUT

BLKINV

VFBACK

VSYNCO

R

S

BLKEN

60/144

ST72774/ST727754/ST72734

SYNC PROCESSOR (SYNC) (Cont’d)

4.4.6 Input Processing

– Check for CSYNCI presence by monitoring inter-

rupt requests from Timer ICAP2.

4.4.6.1 Detecting Signal Presence

The Sync Processor provides two ways of

checking input signal presence, by directly polling

the LATR Latch Register or using the Timer

interrupts.

4.4.6.2 Measuring Sync Period

To measure the sync period, the Sync processor

block uses the Timer Input Capture interrupts:

– ICAP1 connected to VSYNCI signal

Polling check

– ICAP2 connected to HSYNCI/CSYNCI signal

with a 256 prescaler

Use the Latch Register (LATR), to detect the

presence of HSYNCI, VSYNCI, CSYNCI,

HFBACK and VFBACK signals. These latched bits

are set when the falling edge of the corresponding

signal is detected. They are cleared by software.

Calculating

the

difference

between

two

subsequent Input Captures (16-bit value) gives the

period for 256xPH (horizontal period) and PV

(vertical period).

Interrupts check

The period accuracy is one timer clock (500ns at 2

MHz), so that the tolerance is 500ns for PH and

256 * PH (PH accuracy =1.95ns).

Due to the fact that VSYNCI is connected to Timer

Input Capture 1 and HSYNCI or CSYNCI is

connected to Timer Input Capture 2, the Timer

interrupts can be used to detect the presence of

input signals. Refer to the 16-bit Timer chapter for

the description of the Timer registers.

Notes:

1) In case of composite sync, the HSYNCI period

measurement can be synchronized on the

VSYNCI pulse by setting and resetting the

prescaler PSCD bit in the CCR register (for this

function, the ICAP2 detection must be selected

as falling edge).

To use the interrupt method:

– Select Input Capture1 edge detection:

IEDG1 bit in the Timer CR1 register

– Select Input Capture 2 edge detection (must be

falling edge):

IEDG2 bit = 0 in the Timer CR2 register

This avoids errors in the period measurement

due to the Vsync pulse.

– Enable Timer Input Capture interrupts:

ICIE bit in the Timer CR1 register.

2) The Timer Interrupt request should be masked

during a write access to any of the Sync

processor control registers.

– Select the Hsync and Vsync input signals:

HVSEL bit in the POLR register

– Enable the prescaler for HSYNCI or CSYNCI

signal:

PSCD bit in the CCR register.

Important Note:

– Select the normal mode:

Since the recognition of the video mode relies

on the accuracy of the measurements, it is

highly recommended to implement a counter-

style algorithm which performs several

consecutive measurements before switching

between modes.

LCV1/LCV0 bits in the CCR register.

Perform any of the following:

– Check for VSYNCI presence by monitoring inter-

rupt requests from Timer ICAP1. When VSYNCI

is detected then either detect the VSYNCI polar-

ity or check for HSYNCI presence.

The purpose of this algorithm is to filter out any

glitches occurring on the video signals.

– Check for HSYNCI presence by monitoring inter-

rupt requests from Timer ICAP2. On detecting

HSYNCI, either detect its polarity or check if the-

composite sync on HSYNCI pin is detected or

check for CSYNCI presence.

61/144

ST72774/ST727754/ST72734

SYNC PROCESSOR (SYNC) (Cont’d)

4.4.6.3 Detecting Signal Polarity

4.4.6.4 Extracting VSYNCO from CSYNCI

In case of composite sync, the Vertical sync output

signal is extracted with the 5-bit up/down counter.

The Sync Processor provides two ways for

checking input signal polarity by polling the latches

or using the 5-bit up/down counter.

Initially, the width of an Horizontal Sync

component pulse is automatically determined by

hardware which defines a threshold for the 5-bit

counter with a possible user-defined tolerance.

Polling check

– HSYNCI polarity detection:

UPLAT/DWNLAT bits in LATR register

These bits are directly connected to the 5-bit

Up/Down counter.

The circuit then monitors for any incoming period

greater than this previously captured value. This is

then processed as the VSYNCO signal.

UPLAT=1/ DOWNLAT=0 HSYNCI polarity<0

UPLAT=0/ DOWNLAT=1 HSYNCI polarity>0

To use the Vsync extractor, the following steps are

necessary:

– VSYNCI Polarity Detection

– Detection of a composite sync signal:

When the UPLAT and DOWNLAT bits in LATR

– VPOL bit (VSYNCO polarity) in POLR and

register are set, a composite sync signal or a

HSYNCI polarity change is detected.

If these bits are stable during two subsequent

ICAP2 interrupt, the composite sync signal is

stable.

– VOP bit (VSYNCO polarity control) in MCR

The delay between VSYNCI polarity changes

and the VPOL bit typically toggles within 4

msecs. The polarity detector includes an

integrator to filter possible incoming VSYNCI

glitches.

– Defining a threshold:

Select the normal mode (LCV1/LCV0=0 in the

CCR register).

Initialize the counter capture CV4-CV0 to 0.

5-bit Up/Down Counter Check

for HSYNCI Polarity

This method involves the internal 5-bit up/down

counter.

The counter value (CV4-CV0 bits) is updated with

the 5-bit counter value at every detected edge on

the signal monitored.

It is incremented when the signal is high, otherwise

it is decremented.

This automatically measures the HSYNCI pulse

width. It defines a threshold in the CV4-CV0 bits

used by the 5-bit up/down counter.

It also allows to check the HSYNCI polarity

(refer to the “5-bit Up/Down Counter Check”

paragraph.

If a user-defined tolerance is to be added, then

an updated value should be written in the CCR

register (CV4-CV0 bits).

– Start the detection phase:

Initialize the 5-bit counter: write '00000' in the

In a composite sync signal, Hsync and Vsync

always have the same polarity.

CCR register (CV4-CV0 bits).

Select normal mode on falling edge:

LCV1/LCV0 = 0 in the CCR register.

– Starting the VSYNCO hardware extraction

mode:

– Software checks the counter value (CV4-CV0)

after an interrupt (with the signal internally con-

nected or ICAP2) or by polling (timeout 150µs).

Positive polarity: The counter value < 1Fh.

According to the Composite sync polarity, select

the extraction mode (LCV1/LCV0 in CCR

register) and rewrite the counter if necessary.

Negative polarity: minimum threshold (00h)

Positive polarity: maximum threshold (1Fh)

Note:

Negative polarity: The counter value =1Fh on

the falling edge.

In case of a composite incoming signal, the

software just has to check that the VSYNCO

period and polarity are stable.

The extracted VSYNCO signal always has

negative polarity.

62/144

ST72774/ST727754/ST72734

SYNC PROCESSOR (SYNC) (Cont’d)

4.4.6.5 Example of VSYNCO extraction for a

negative composite sync with serration pulses

Refer to Figure 43.

When the vertical period is finished, the counter

starts counting up and when the maximum is

reached, VSYNCO is negated. The extracted

signal may be validated by software since it is input

to Timer ICAP1.

In extraction mode, the 5-bit comparator checks

the counter value with respect to the threshold.

Serration pulses during vertical blanking can be

filtered if the serration pulse widths are less than

8µs.

When the incoming signal is high, the counter is

increased, otherwise it is decreased.

When the counter reaches the threshold on its way

down, VSYNCO is asserted. During the vertical

blanking, the counter value is decreased down to a

programmable minimum, i.e. it does not underflow.

In the same way, positive composite sync signals

can be used by properly selecting the edge

sensitivity in HSYNCI width measurement mode

(LCV0 bit).

Figure 43. VSYNCO Extraction from a Composite Signal (negative polarity)

Serration pulses

Composite signal

Input

Max Pulse width: 8µs

1F-Threshold

Counter value:

1F=Max

8µs

Threshold

0=Min

VSYNCO

generated

VSYNCO Pulse

Max Delay: 8µs

or threshold

HSYNCO

VR01990

Figure 44. Obtaining the 11-bit Vertical Period (V11BITS)

7

0

CFGR

VGENR

Q’2

Q’0

Q’1

Example:

VGENR=CCh, CFGR = 3h

V11bits=663h

10

0

V11BITS

63/144

ST72774/ST727754/ST72734

SYNC PROCESSOR (SYNC) (Cont’d)

4.4.7 Output Processing

– Configure the following bits:

SYNOP = 0

HVGEN = 1

4.4.7.1 Generating Free-Running Frequencies

The free-running frequencies function is used to:

HACQ = 0

VACQ = 0

Horizontal Period

– Drive the monitor when no or bad sync signals

are received.

– Stabilize the OSD screen when the monitor is

unlocked.

PH = Horizontal period = ((HGENR+1)/4) µs

Pulse width: 2 µs => HGENR min=8

Polarity: Positive

– Perform fast alignment for maintenance purpos-

es.

HGENR range: [8..255]

Vertical Period

Note: When free-running mode is active, the analyzer

and corrector modes must be disabled.

– VCORDIS = 1, VEXT = 0 in CFGR and POLR

registers for vertical output measurement

PV = Vertical period = (PH * V11bits) µs

V11bits is a concatenation of VGENR and the Q'2

Q'1 Q'0 bits of the CFGR register.

Refer to Figure 44.

– 2FHINH = 0 in CFGR register for horizontal

low level measurment

– VACQ, HACQ = 0, in CFGR register for ana-

lyzer mode

The Sync processor can generate any of the

following output sync signals HSYNCO, VSYNCO,

CLAMPOUT, BLANKOUT.

Pulse width: 4 * PH => min value= 8µs

Polarity: Positive

VGENR/CFGR range: [5..7FF]

To select the generation mode:

– Program the horizontal period using the HGENR

register.

– Program the vertical period using the VGENR (8

bits) and CFGR (3 bits) registers (2047 scan

lines per frame). Refer to Figure 44.

Table 17. Typical values for generated HSYNC signals

HGENR (hex value)

H Period

5 µs

HFREQ

200 kHz

125 kHz

62.5 kHz

31.25 kHz

15.6 kHz

Pulse Width

2 µs

Duty Cycle

40%

13

1F

3F

7F

FF

8 µs

2 µs

25%

16 µs

32 µs

64 µs

2 µs

12.5%

6.2%

2 µs

3.1%

Table 18. Typical values for generated VSYNC signals

HGENR

V11bits

H Period

H Freq

V Period

V Freq

Pulse width

(hex value)

7FF (2047)

400 (1024)

7FF (2047)

400 (1024)

7FF (2047)

400 (1024)

7FF (2047)

400 (1024)

13

1F

3F

7F

5 µs

8 µs

200 kHz

125 kHz

62.5 kHz

31.25 kHz

10.2 ms

5.1 ms

16.3 ms

8.2 ms

32.6 ms

16.4 ms

65.5 ms

32.8 ms

97.7 Hz

195 Hz

61 Hz

122 Hz

30.6 Hz

60.9 Hz

15 Hz

20 µs

32 µs

64 µs

128 µs

8 µs

16 µs

32 µs

30 Hz

64/144

ST72774/ST727754/ST72734

SYNC PROCESSOR (SYNC) (Cont’d)

4.4.8 Analyzer Mode

The analyzer block is used for all extra

measurements on the sync signals to manage the

monitor functions:

For maximum accuracy, it is possible to measure

the low level of HFBACK with the same technique

(FBSEL bit in the MCR register).

Figure 45. Horizontal Low Level Measurement

– Measure the number of scan lines per frame

(VSYNCO or VFBACK) to simplify the OSD ver-

tical centering.

Measure HLow

– Measure the low level of HSYNCO or HFBACK.

This function can be used for VSYNCO pulse

extension or for a fast estimation of the incoming

Hsync signal period.

Disable H correction Mode

2FHINH=0

– Detection of the pre/post equalization pulses.

Notes:

Disable H internal generation

HVGEN=0

1. Analyzer mode should be performed before

corrector mode.

Necessary if Signals

are H/VSYNCO

HSYNCO Positive polarity

2. When analyzer mode is active, the free-running

frequencies generator and corrector mode must

be disabled.

Select H/VBACK or H/VSYNCO

FBSEL=0 or 1

– HVGEN = 0 in ENR register

HACQ=1

Start measurement

– 2FHINH 0 in CFGR register for Horizontal low

level measurement

– VEXT = 0, VCORDIS = 1 in CFGR, POLR reg-

isters for Vertical output measurement

No

HACQ=0?

3. If H/VBACK are selected (FBSEL=0) corrector

mode must be disabled

4. For all measurements, HSYNCO and VSYNCO

Yes

must be POSITIVE.

HGENR=Result

4.4.8.1 Horizontal Low Level Measurement

The measurement starts in setting HACQ by

software. When this bit is cleared by hardware, the

HGENR register returns the result.

END

VR02118A

The algorithm is shown in Figure 45.

HLow = ((255-HGENR+1)/4) µs

Note: HLow maximum value = 64µs (even if real value is

greater)

65/144

ST72774/ST727754/ST72734

SYNC PROCESSOR (SYNC) (Cont’d)

4.4.8.2 Vertical Output Measurement

The function of vertical pulse measurement is to:

Figure 46. Vertical Output Measurement

Measure H Lines

– Capture the number of HSYNCO pulses during

a Low level of VSYNCO.

– Capture the number of HFBACK pulses during a

Low level of VFBACK (maximum accuracy).

Start the measurement by setting VACQ in the

CFGR. When the measurement is completed this

bit is cleared by hardware. The VGENR and CFGR

registers return the result.

Disable V correction Mode

VCORDIS=1, VEXT=0

Disable H internal generation

HVGEN=0

The algorithm is shown in Figure 46.

Necessary if Signals

are H/VSYNCO

H & VSYNCO Positive polarity

HLine = 2048 - (V11bits)

Hline maximum value = 2048 (even if real value is

greater)

Select H/VBACK or H/VSYNCO

FBSEL=0 or 1

V11bits = VGENR(8 MSB) and Q'2,Q'1,Q'0 (3

LSB). Refer to Figure 44.

VACQ=1

Start measurement

Note: In case of pre/post equalization pulses, set the

2FHINH bit in the CFGR register.

No

VACQ=0?

4.4.8.3 Detection of pre equalization pulses

This function uses two bits:

Yes

– 2FHDET in POLR register continuously updated

by hardware

VGENR & CFGR=Result

– 2FHLAT in LATR register set by hardware when

a higher frequency is detected and reset by soft-

ware

END

A measurement of the low level of HSYNCO is

VR02118B

necessary before reading this information.

Note: Reset the 2FHLAT bit in the LATR register on the

third Hsync pulse after the Vsync pulse.

66/144

ST72774/ST727754/ST72734

SYNC PROCESSOR (SYNC) (Cont’d)

4.4.9 Corrector Mode

In this mode, you can perform the following

Procedure:

1. HSYNCO and VSYNCO polarities must be

positive.

functions:

– Inhibit pre/post equalization pulses

2. Set the 2FHINH bit in the CFGR register to

remove pre/post equalization pulses.

This removes all pre/post equalization pulses

on the HSYNCO signal.

3. Measure the low level of HSYNCO.

The inhibition starts on the falling edge of

HSYNCO and lasts for (((HGENR+1)/4)-2)

µs. The decrease of 2µs (one minimum pulse

width) avoids the removal of the next pulse of

HSYNCO.

4. Update HGENR =(FFh - (HGENR + 1)) + 4

to add tolerance

5. Write VGENR > 0.

6. Reset the VCORDIS bit in the POLR

register

Procedure:

1. HSYNCO and VSYNCO polarities must be

positive.

7. Set the VEXT bit in the CFGR register.

– Extend VSYNCO pulse width during pre and

post equalization pulses (for test only).

2. Measure the low level of HSYNCO.

This function allows extending the VSYNCO

pulse width as long as equalization pulses are

detected. (VSYNCO = VSYNCO + 2FHDET).

3. Set the 2FHINH bit in the CFGR register.

– Extend VSYNCO pulse width by several scan

lines

This function can be also used to extend the

Procedure:

video blanking signal.

1. HSYNCO and VSYNCO polarities must be

positive.

Procedure:

1. HSYNCO and VSYNCO polarities must be

positive.

2. Set the 2FHINH bit in the CFGR register to

remove pre/post equalization pulses.

2. Set the 2FHINH bit in the CFGR register

only if some pre/post equalizations pulses

are detected. (2FHLAT, 2FHDET flags).

3. Measure the low level of HSYNCO.

4. Update HGENR =(FFh - (HGENR + 1)) + 4.

5. Write VGENR > 0.

3. The extension will be the number of

HSYNCO periods set in the VGENR

register.

6. Reset the VCORDIS bit in the POLR register.

7. Set the VEXT bit in the CFGR register.

8. Set the 2FHEN bit in the ENR register.

Notes:

4. Reset the VCORDIS bit in the POLR

register.

– Extend VSYNCO width during all post equaliza-

tion pulses.

1. When corrector mode is active, the free-running

frequencies generator and analyzer mode must

be disabled.

This function extends the VSYNCO pulse

width when post equalization pulses are

detected (2FHDET bit in the POLR register

and 2FHLAT bit in the LATR register).

(HVGEN=0 in ENR register, HACQ=0, VACQ=0

in the CFGR register).

2. If VGENR=0, all VSYNCO correction functions

are disabled except the 2FHEN bit which must

be cleared if VGENR = 0 or VCORDIS = 1.

67/144

ST72774/ST727754/ST72734

SYNC PROCESSOR (SYNC) (Cont’d)

4.4.10 Register Description

CONFIGURATION REGISTER (CFGR)

1: Start measuring the number of scan lines dur-

ing VSYNCO/VFBACK low level.

Read/Write

Bit 5 = Reserved. Must be cleared.

Reset Value: 0000 0000 (00h)

Bit 4 = 2FHINH Inhibition of Pre/Post equalization

pulses.

7

0

This function removes pre/post equalization

pulses on HSYNCO signal. The sync generator

and the Horizontal sync analyzer must both be

disabled (HVGEN=HACQ=0).

HACQ VACQ

-

2FHINH VEXT Q’2

Q’1

Q’0

Bit 7 = HACQ Horizontal Sync Analyzer Mode

Set by software, reset by hardware when the

measurement is done. The sync generator must

be disabled (HVGEN=0).

0: Disable

1: Enable

Bit 3 = VEXT VSYNCO pulse width extension in

case of post-equalization pulses.

0 : Measurement is done, the result can be read

in HGENR.

The sync generator and the Horizontal and

Vertical sync analyzer must be disabled (HVGEN

= 0, HACQ = 0, VACQ = 0, VCORDIS=0). Vertical

extension must be enabled (VGENR > 0).

1: Start measuring HSYNCO/HFBACK low lev-

el.

Bit 6 = VACQ Vertical Sync Analyzer Mode

Set by software, reset by hardware when the

measurement is done. The sync generator must

be disabled (HVGEN=0).

0: Disable

1: Enable

Bits 2:0 = Q’2..Q’0

These are the read/write LSB of the VGENR 11-bit

counter. Refer to Figure 44.

0: Measurement is done, and the result can be

read in VGENR.

68/144

ST72774/ST727754/ST72734

SYNC PROCESSOR (SYNC) (Cont’d)

MUX CONTROL REGISTER (MCR)

HS1 HS0

HSYNCI Selection Mode

Read/Write

CLAMPOUT after HSYNCO rising edge

HSYNC0 <- (HSYNCI, CSYNCI)

0

1

0

1

0

1

Reset Value: 0010 0000 (20h)

CLAMPOUT after HSYNCO rising edge

HSYNC0 <- (HSYNCI, CSYNCI)

7

0

-

CLAMPOUT after HSYNCO falling edge

HSYNC0 <- (HSYNCI, CSYNCI)

BP1 BP0 FBSEL SCI0 HS1 HS0 VOP

CLAMPOUT after HSYNCO falling edge

HSYNC0 <- (HSYNCI,CSYNCI)

Bit 7:6 = BP1, BP0 Back Porch Pulse control

BP1 BP0

Back Porch pulse width

0

1

0

1

0

1

No Back Porch, Moire output selected

167ns Back Porch ± 10 ns

Note: In case of composite sync, if HSYNCO blanking is

enabled (HINH=0 in the ENR register), HS1 must =

1 (CLAMPOUT after HSYNCO rising edge not al-

lowed).

333ns Back Porch ± 10 ns

666ns Back Porch ± 10 ns

Bit 1 = VOP Vertical Polarity control

The VOP bit inverts the VSYNCO Sync signal.

Bit 5 = FBSEL VSYNCO/HSYNCO or VFBACK/

HFBACK analysis

0: No polarity inversion (VSYNC0 <- VSYNCI)

1: Inversion enabled (VSYNC0 <- VSYNCI)

0: HFBACK & VFBACK

1: HSYNCO & VSYNCO

Note: If at each vertical input capture the VPOL bit is cop-

ied by software on the VOP bit, the VSYNCO signal

will have a constant positive polarity.

Bit 4 = SCI0 HSYNCI/CSYNCI selection

0: HSYNCI

1: CSYNCI

Note: The internally extracted VSYNCO has ALWAYS

negative polarity.

Bit 0 = Reserved. Must always be cleared.

Bit 3:2 = HS1, HS0 Horizontal Signal selection

These bits allow inversion of the HSYNCI/CSYNCI

69/144

ST72774/ST727754/ST72734

SYNC PROCESSOR (SYNC) (Cont’d)

COUNTER CONTROL REGISTER (CCR)

Table 19. Sync On Green Window

Read/Write

WINDOW DELAY

min.

max.

Reset Value: 0000 0000 (00h)

dt

165 ns

250 ns

Bit 6 = Reserved, forced by hardware to 0.

7

0

Bit 5 = VPOL Vertical Sync polarity (read only)

PSCD LCV1 LCV0 CV4 CV3 CV2 CV1 CV0

0: Positive polarity

1: Negative polarity

Bit 7 = PSCD Prescaler Enable bit.

Note: If the Vertical Sync polarity is changing, the VPOL

0: Enable the Prescaler by 256

bit will be updated after a typical delay of 4 msec.

1: Disable the Prescaler and reset it to 7Fh. This

also disables the ICAP2 event.

Bit 4 = 2FHDET Detection of Pre/Post Equalization

pulses (read only).

This bit is continuously updated by hardware. It is

valid when the sync generator and horizontal

analyzer are disabled (HVGEN = 0, HACQ = 0).

Bit 6:5 = LCV1, LCV0 VSYNCO Extraction Control

LCV1 LCV0

VSYNC0 Control Bits

Normal mode

Counter capture on input falling edge

0

1

0: None detected

1: Pre/Post Equalization pulses detected

Normal mode

Counter capture on input rising edge

Bit 3 = HVSEL Alternate Sync Input Select.

This bit selects between the two sets of Horizontal

and Vertical Sync inputs

Extraction mode

CSYNCI/HSYNCI Negative polarity

CV4-0 = counter minimum threshold

1

0

1

Extraction mode

CSYNCI/HSYNCI Positive polarity

CV4-0 = counter maximum threshold

0: HSYNCI2 / VSYNCI2

1: HSYNCI1 / VSYNCI1

Bit 2 = VCORDIS Extension Disable Signal

(Extension with VGENR Register)

Bit 4:0 = CV4-CV0 Counter Captured Value.

These bits contain the counter captured value in

different modes.

0: enable

1: disable

In VSYNCO extraction mode, they contain the

HSYNCI pulse-width measurement.

Bit 1 = CLPINV Programmable ClampOut pulse

polarity.

POLARITY REGISTER (POLR)

Bits 5-4 Read Only, other bits Read/Write

Reset Value: 0000 1000 (08h)

0: Positive

1: Negative

Bit 0 = BLKINV Programmable blanking polarity

7

0

0: Negative

1: Positive

SOG

0

VPOL 2FHDET HVSEL VCORDIS CLPINV BLKINV

Bit 7 = SOG Sync On Green Detector

SOG is set by hardware if CSYNCI pulse is not

included in the window between HSYNCI rising

edge and HSYNCI falling edge + dt .

Cleared by software.

70/144

ST72774/ST727754/ST72734

SYNC PROCESSOR (SYNC) (Cont’d)

LATCH REGISTER (LATR)

Bit 1 = DWNLAT Detection of minimum value of 5-

bit up/down counter.

Set when the 5 bit up/down counter reaches its

minimum value (00 or Threshold)

Read/Write

Reset Value: 0000 0000 (00h)

Cleared by software (by writing zero).

7

0

CSYN HSYN VSYN HFLY VFLY UPLAT DWNLAT 2FHLAT

Note: DWNLAT and UPLAT may be used for HSYNCI po-

larity detection and Composite Sync detection as

follows:

Bit 7 = CSYN Detection of pulses on CSYNCI

Set on falling edge of CSYNCI

Cleared by software (by writing zero).

UPLAT

DWNLAT

HSYNCI Characteristics

No Info

0

1

0

1

0

1

Positive Polarity

Negative Polarity

Composite Sync

Bit 6 = HSYN Detection of pulses on HSYNCI

Set on falling edge of HSYNCI1 or HSYNCI2

Cleared by software (by writing zero).

Bit 0 = 2FHLAT equalization pulses latch.

This bit may be used to detect pre/

postequalization pulses or a too high horizontal

frequency.

Bit 5 = VSYN Detection of pulses on VSYNCI

Set on falling edge of VSYNCI1 or VSYNCI2

Cleared by software (by writing zero).

Set by hardware when Pre/Post equalization

pulses are detected.

Must be reset by software.

It is valid when the sync generator and Horizontal

analyzer are disabled (HVGEN = 0, HACQ = 0)

Bit 4 = HFLY Detection of pulses on HFBACK

Set on falling edge of HFBACK input

Cleared by software (by writing zero).

Bit 3 = VFLY Detection of pulses on VFBACK

Set on falling edge of VFBACK input

Cleared by software (by writing zero).

Bit 2 = UPLAT Detection of the maximum value of

5-bit up/down counter.

Set when the 5 bit up/down counter reaches its

maximum value (1Fh or Threshold)

Cleared by software (by writing zero).

71/144

ST72774/ST727754/ST72734

SYNC PROCESSOR (SYNC) (Cont’d)

HORIZONTAL SYNC GENERATOR REGISTER

(HGENR)

VERTICAL SYNC GENERATOR REGISTER

(VGENR)

Read/Write

Reset Value: 0000 0000 (00h)

7

0

7

0

MSB

LSB

MSB

LSB

Case HVGEN = 1: Generation mode

In this mode, this register contains the Hsync free-

running frequency.

The generated signal is:

In this mode, this register contains the Vsync free-

running frequency (11-bit value).

The generated signal is:

- Pulse width: 2 µs.

- Period PH = ((HGENR+1)/4) µs.

- Polarity: Positive

- Pulse width: 4 * PH µs (horizontal period).

- Period PV = PH * (V11bits) µs.

- Polarity: Positive

Note: The value in HGENR must be in the range [8..255].

Case HVGEN = 0: Analyzer/corrector Mode

Note: The value in VGENR must be in the range [5..255]

The Vsync generation mode works as an 11-bit hor-

izontal line counter (2047 scan lines per frame

max.). The 3 LSB are in the CFGR register. Refer

to Figure 44.

Sub-case HACQ = 1: Analyzer Mode

Case HVGEN = 0: Analyzer/Corrector Mode

By setting HACQ bit by software the Analyzer

mode starts. When HACQ is cleared by hardware,

HGENR returns the duration of HSYNCO/

HFBACK low level. The analysis should be done

before corrector mode.

Sub-case VACQ = 1: Analyzer Mode

Set the VACQ bit to start analyzer mode. When

VACQ is cleared by hardware, VGENR/CFGR

returns the number of scan lines during the

VSYNCO/VFBACK low level period.

Sub-case HACQ = 0: Corrector Mode

In this mode, the final HSYNCO signal on the pin

can be corrected in order to detect and inhibit pre/

post equalization pulses.

Sub-case VACQ = 0: Corrector Mode

VSYNCO pulse width is extended by VGENR scan

lines. If VGENR = 0, all VSYNCO corrections are

disabled.

72/144

ST72774/ST727754/ST72734

SYNC PROCESSOR (SYNC) (Cont’d)

ENABLE REGISTER (ENR)

Bit 3 = 2FHEN VSYNCO Extension

VSYNCO is forced high when detecting pre- and

post-equalization pulses. It is valid when the sync

generator and analyzer are disabled (HVGEN = 0,

HACQ = 0, VACQ = 0). Refer to the procedure in

Section 4.4.9 Corrector Mode.

Read/Write

Reset Value: 1100 0011 (C3h)

7

0

0: Disabled

1: Enabled

SYNOP CLMPEN BLKEN HVGEN 2FHEN HINH HSIN1 VSIN1

Bit 2 = HINH HSYNCO Blanking

HSYNCO is blanked during the extracted

VSYNCO pulse.

0: Enabled

1: Disabled

Bit 7 = SYNOP HSYNCO, VSYNCO outputs

enable

0: Enabled

1: Disabled

Bit 6 = CLMPEN Clamping or Moire output ena-

ble

0: Clamping or Moire output (function of BP0,

BP1) enabled

Bit 1 = HSIN1 (read only)

Returns the HSYNCI1 pin level

1: Clamping or Moire output disabled

Bit 0 = VSIN1 (read only)

Returns the VSYNCI1 pin level

Bit 5 = BLKEN Blanking Output

0: Disabled

1: Enabled

Bit 4 = HVGEN Sync Generation function

0: Analyzer/Corrector Mode

1: Generation of HSYNCO and VSYNCO free-

running frequencies

Table 20. Summary of the Main Sync Processor Modes

Sync Processor Mode

DSUB Selected as Inputs

SYNOP

HVSEL

HVGEN

HACQ

VACQ

---

1

---

(HSYNCI1/VSYNCI1)

BNC Selected as Inputs

(HSYNCI2/VSYNCI2)

---

1

0

---

1

---

0

---

0

Don’t drive the monitor

with any Sync signals

---

Generate Sync Signals

to drive the Monitor hardware

0

Use the Sync Processor

to drive the monitor hardware

by incoming Sync signals

0

---

0

---

Analyse the number of Scan Lines

during one vertical frame

---

--

0

---

1

Analyse the HSYNC delay

between two pulses

---

73/144

ST72774/ST727754/ST72734

SYNC PROCESSOR (SYNC) (Cont’d)

Table 21. SYNC Register Map and Reset Values

Address

(Hex.)

Register

Name

7

6

5

4

3

2

1

0

CFGR

HACQ

0

VACQ

0

-

2FHINH

0

VEXT

0

Q’2

0

Q’1

0

Q’0

0

40

41

42

43

44

45

46

47

Reset Value

0

MCR

BP1

0

BP0

0

FBSEL

1

SCI0

0

HS1

0

HS0

0

VOP

0

-

Reset Value

0

CCR

PSCD

0

LCV1

0

LCV0

0

CV4

0

CV3

0

CV2

0

CV1

0

CV0

0

Reset Value

POLR

SOG

0

VPOL

0

2FHDET

0

HVSEL VCORDIS CLPINV

BLKINV

0

Reset Value

1

0

LATR

CSYN

0

HSYN

0

VSYN

0

HFLY

0

VFLY

0

UPLAT DWNLAT 2FHLAT

Reset Value

0

HGENR

MSB

0

LSB

0

Reset Value

0

VGENR

MSB

0

LSB

0

Reset Value

0

ENR

SYNOP CLMPEN BLKEN

HVGEN

0

2FHEN

0

HINH

0

HSIN1

1

VSIN1

1

Reset Value

1

0

74/144

ST72774/ST727754/ST72734

4.5 TIMING MEASUREMENT UNIT (TMU)

4.5.1 Introduction

For horizontal analysis (refer to Figure 48):

The timing measurement unit (TMU) allows the

analysis of the current video timing characteristics

in order to control display position and size.

– Obtain the minimum number of oscillator clock

cycles (H1) between the falling edge of the

horizontal sync signal (HSYNCO or HFBACK)

and the first rising edge of the active video in-

put (AV), for all lines, between 2 consecutive

vertical sync pulses.

It consists of measuring the timing between the

horizontal or vertical sync output signals and the

active video signal input (AV).

4.5.2 Main Features

– Obtain the minimum number of oscillator clock

cycles (H2) between the last falling edge of

the active video input (AV) and the rising edge

of the horizontal sync signal (HSYNCO or HF-

BACK) for all lines, between 2 consecutive

vertical sync pulses.

■ Horizontal or vertical timing measurement

■ Oscillator clock f

(24 or 12 MHz) used for

OSC

horizontal measurement

■ Horizontal sync signal (HSYNCO or HFBACK)

and Vertical sync signal (VSYNCO or VFBACK)

used for all measurements

Note: Horizontal measurement is inhibited during the high

level of VSYNCO or VFLYBACK.

■ Measurements performed on positive signals

only

For vertical analysis (refer to Figure 49):

■ 11-bit counter

– Obtain the minimum number of horizontal

sync pulses (V1) between the falling edge of

the vertical sync signal (VSYNCO or VF-

BACK) and the first rising edge of the active

video input, during 2 consecutive frames.

■ Overflow detection

4.5.3 Functional Description

The Timing Measurement Unit is centered around

an 11-bit counter. Depending on the H_V bit of the

control register, the TMU measures the horizontal

or vertical video characteristics.

Figure 47. TMU Block Diagram

ST7 INTERNAL BUS

TMUT1CR

T1[7:0]

TMUT2CR

T2[7:0]

TMUCSR

T2[10] T2[9] T2[8]

T1[9] T1[8] H_V START

T1[10]

3

8

SUP

COMPARATOR

11

Clock

Start

Stop

CONTROL

11 bit COUNTER

f

OSC

(1)

HSYNCO or HFBACK

VSYNCO or VFBACK

(FROM SYNC PROCESSOR)

Note 1: Selection between Sync outputs or Flyback inputs is made in MISCR register (bit 6: FLY_SYN)

AV

75/144

ST72774/ST727754/ST72734

TIMING MEASUREMENT UNIT (Cont’d)

– Obtain the minimum number of horizontal

sync output pulses (V2) between the last fall-

ing edge of the active video input (AV) and the

rising edge of the vertical sync signal (VSYN-

CO or VFBACK) during two 2 consecutive

frames.

The H_V bit selects horizontal or vertical

measurement. This selection should be made prior

to starting the measurement by setting the START

bit. This bit is set by software but only cleared by

hardware at the end of the measurement.

The values of the H1 and H2 registers are

available only at the end of a measurement, in

other words when the START bit is at 0.

4.5.3.2 Vertical Measurement

When the H_V bit = 0 and, when the START bit is

set by software, the TMU measures the minimum

V1 and V2 values during 2 consecutive vertical

frames. The START bit is then cleared by

hardware.

4.5.3.3 Special cases

When the measurement is finished (rising edge of

AV, horizontal or vertical sync signals), the results

(T1,T2) are transferred into the corresponding

registers (H1,H2) or (V1,V2).

– If an overflow of the counter occurs during any of

the measurements, the measured T1 or T2 val-

ues will be 7FFh.

– If the AV signal is always low (no active video),

the measured T1 or T2 values will also be 7FFh.

Note: The values of the H1/H2 or V1/V2 registers are

available only at the end of a measurement (after

the START bit has been cleared).

– If T1 ≤ 0 (AV already high when the falling edge

of the sync signal occurs), the measured T1 val-

ue will be fixed to 1.

4.5.3.1 Horizontal Measurement

When the H_V bit = 1, and when the START bit is

set by software, the measurement starts after the

next vertical sync pulse. The TMU searches the

minimum values of H1 and H2 until the rising edge

of the next following vertical sync pulse. The

START bit is then cleared by hardware.

– If T2 ≤ 0 (AV still high when the rising edge of the

sync signal occurs), a specific T2 value will be re-

turned.

Note: Refer to Application Note AN1183 for further de-

tails.

Figure 48. Horizontal Measurement

HSYNCO or

HFBACK

H1

H2

AV

H1 and H2 measured in oscillator clock periods

Note: HSYNCO or HFBACK must be positive.

Figure 49. Vertical Measurement

VSYNCO or

VFBACK

V1

V2

AV

V1 and V2 measured in horizontal pulses

Note: VSYNCO or VFBACK must be positive.

76/144

ST72774/ST727754/ST72734

TIMING MEASUREMENT UNIT (Cont’d)

4.5.4 Register Description

T1 COUNTER REGISTER (TMUT1CR)

Read Only

Reset Value: 1111 1111 (FFh)

CONTROL STATUS REGISTER (TMUCSR)

Bit 7:2 - Read only

Bit 1:0 - Read/Write

This is an 8-bit register that contains the low part of

the counter value.

Reset Value: 1111 1100 (FCh)

7

0

7

0

T1[7]

T1[0]

T2[10] T2[9] T2[8] T1[10] T1[9] T1[8] H_V START

When a T1 measurement is finished (rising edge

on AV input), the 11-bit counter value is transferred

to this register and to the T1[10:8] bits in the CSR

register.

Bit 7:5 = T2[10:8] MSB of T2 Counter.

Most Significant Bits of the T2 counter value (see

T2 Counter register description).

T1 is H1 value if the H_V bit = 1.

T1 is V1 value if the H_V bit = 0.

Bit 4:2= T1[10:8] MSB T1 Counter.

Most Significant Bits of the T1 counter value (see

T1 Counter register description).

T2 COUNTER REGISTER (TMUT2CR)

Read Only

Reset Value: 1111 1111(FFh)

Bit 1 = H_V Horizontal or Vertical Measurement.

This bit is set and cleared by software to select the

type of measurement. It cannot be modified while

the START bit = 1 (measurement in progress).

This is an 8-bit register that contains the low part of

the counter value.

7

0

0: Vertical measurement.

1: Horizontal measurement.

T2[7]

T2[0]

Bit 0 = START Start measurement.

This bit is set by software and cleared by hardware

when the measurements are completed. It can not

be cleared by software.

When a T2 measurement is finished (rising edge

on the selected sync signal), the 11-bit counter

value is transferred to this register and to the

T2[10:8] bits in the CSR register.

0: Measurement done.

1: Start measurement.

T2 is H2 value if the H_V bit = 1.

T2 is V2 value if the H_V bit = 0.

77/144

ST72774/ST727754/ST72734

TIMING MEASUREMENT UNIT (Cont’d)

Table 22. TMU Register Map and Reset Values

Address

(Hex.)

Register

Name

7

6

5

4

3

2

1

0

T2[10]

1

T2[9]

1

T2[8]

1

T1[10]

1

T1[9]

1

T1[8]

1

H_V

0

START

0

CSR

0E

Reset Value

T1CR

T1[7]

1

T1[0]

1

0F

10

Reset Value

1

T2CR

T2[7]

1

T2[0]

1

Reset Value

78/144

ST72774/ST727754/ST72734

4.6 USB INTERFACE (USB)

4.6.1 Introduction

Serial Interface Engine

The USB Interface implements a low-speed

The SIE (Serial Interface Engine) interfaces with

the USB, via the transceiver.

function interface between the USB and the ST7

microcontroller. It is a highly integrated circuit

which includes the transceiver, 3.3 voltage

regulator, SIE and DMA. No external components

are needed apart from the external pull-up on

USBDM for low speed recognition by the USB

host.

The SIE processes tokens, handles data

transmission/reception, and handshaking as

required by the USB standard. It also performs

frame formatting, including CRC generation and

checking.

Endpoints

4.6.2 Main Features

The Endpoint registers indicate if the

microcontroller is ready to transmit/receive, and

how many bytes need to be transmitted.

■ USB Specification Version 1.0 Compliant

■ Supports Low-Speed USB Protocol

■ Two or Three Endpoints (including default one)

depending on the device (see device feature list

and register map)

DMA

When a token for a valid Endpoint is recognized by

the USB interface, the related data transfer takes

place, using DMA. At the end of the transaction, an

interrupt is generated.

■ CRC generation/checking, NRZI encoding/

decoding and bit-stuffing

■ USB Suspend/Resume operations

■ DMA Data transfers

Interrupts

■ On-Chip 3.3V Regulator

■ On-Chip USB Transceiver

By reading the Interrupt Status register,

application software can know which USB event

has occurred.

4.6.3 Functional Description

The block diagram in Figure 50, gives an overview

of the USB interface hardware.

For general information on the USB, refer to the

“Universal Serial Bus Specifications” document

available at http//:www.usb.org.

Figure 50. USB block diagram

6 MHz

ENDPOINT

CPU

REGISTERS

USBDM

Address,

Transceiver

SIE

DMA

USBDP

data busses

and interrupts

3.3V

INTERRUPT

REGISTERS

USBVCC

USBGND

Voltage

Regulator

MEMORY

79/144

ST72774/ST727754/ST72734

USB INTERFACE (Cont’d)

4.6.4 Register Description

Bits 7:6 = DA[7:6] DMA address bits 7-6.

The software must write the start address of the

DMA memory area whose most significant bits are

given by DA15-DA6. The remaining 6 address bits

are set by hardware. See Figure 51.

DMA ADDRESS REGISTER (DMAR)

Read / Write

Reset Value: Undefined

Bits 5:4 = EP[1:0] Endpoint number (read-only).

These bits identify the endpoint which required

attention.

7

0

DA15 DA14 DA13 DA12 DA11 DA10 DA9

DA8

00: Endpoint 0

01: Endpoint 1

10: Endpoint 2

When a CTR interrupt occurs (see register ISTR)

the software should read the EP bits to identify the

endpoint which has sent or received a packet.

Bits 7:0=DA[15:8] DMA address bits 15-8.

See the description of bits DA7-6 in the next

register (IDR).

INTERRUPT/DMA REGISTER (IDR)

Read / Write

Bits 3:0 = CNT[3:0] Byte count (read only).

This field shows how many data bytes have been

received during the last data reception.

Reset Value: xxxx 0000 (x0h)

Note: Not valid for data transmission.

7

0

DA7

DA6

EP1

EP0 CNT3 CNT2 CNT1 CNT0

Figure 51. DMA buffers

101111

Endpoint 2 TX

Endpoint 2 RX

101000

100111

100000

011111

Endpoint 1 TX

Endpoint 1 RX

011000

010111

010000

001111

Endpoint 0 TX

Endpoint 0 RX

001000

000111

DA15-6,000000

000000

80/144

ST72774/ST727754/ST72734

USB INTERFACE (Cont’d)

PID REGISTER (PIDR)

Bit 5 = CTR Correct Transfer. This bit is set by

hardware when a correct transfer operation is

performed. The type of transfer can be determined

by looking at bits TP3-TP2 in register PIDR. The

Endpoint on which the transfer was made is

identified by bits EP1-EP0 in register IDR.

Read only

Reset Value: xx00 0000 (x0h)

7

0

TP3

TP2

0

0: No Correct Transfer detected

1: Correct Transfer detected

Bits 7:6 =TP3-TP2 Token PID bits 3 & 2.

USB token PIDs are encoded in four bits. TP3-TP2

correspond to the variable token PID bits 3 & 2.

Note:A transfer where the device sent a NAK or STALL

handshake is considered not correct (the host only

sends ACK handshakes). A transfer is considered

correct if there are no errors in the PID and CRC

fields, if the DATA0/DATA1 PID is sent as expect-

ed, if there were no data overruns, bit stuffing or

framing errors.

Note: PID bits 1 & 0 have a fixed value of 01.

When a CTR interrupt occurs (see register ISTR)

the software should read the TP3 and TP2 bits to

retrieve the PID name of the token received.

Bit 4 = ERR Error.

The USB standard defines TP bits as:

This bit is set by hardware whenever one of the

errors listed below has occurred:

TP3

0

TP2

0

PID Name

OUT

0: No error detected

1: Timeout, CRC, bit stuffing or nonstandard

framing error detected

1

0

IN

1

SETUP

Bit 3 = IOVR Interrupt overrun.

Bit 5:0 Reserved. Forced by hardware to 0.

This bit is set when hardware tries to set ERR,

ESUSP or SOF before they have been cleared by

software.

INTERRUPT STATUS REGISTER (ISTR)

0: No overrun detected

1: Overrun detected

Read / Write

Reset Value: 0000 0000 (00h)

7

0

Bit 2 = ESUSP End suspend mode.

This bit is set by hardware when, during suspend

mode, activity is detected that wakes the USB

interface up from suspend mode.

0

DOVR CTR ERR IOVR ESUSP RESET SOF

When an interrupt occurs these bits are set by

hardware. Software must read them to determine

the interrupt type and clear them after servicing.

This interrupt is serviced by a specific vector.

0: No End Suspend detected

1: End Suspend detected

Note: These bits cannot be set by software.

Bit 1 = RESET USB reset.

This bit is set by hardware when the USB reset

sequence is detected on the bus.

Bit 7 = Reserved. Forced by hardware to 0.

Bit 6 = DOVR DMA over/underrun.

This bit is set by hardware if the ST7 processor

can’t answer a DMA request in time.

0: No USB reset signal detected

1: USB reset signal detected

Note: The DADDR, EP0RA, EP0RB, EP1RA, EP1RB,

EP2RA and EP2RB registers are reset by a USB

reset.

0: No over/underrun detected

1: Over/underrun detected

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ST72774/ST727754/ST72734

USB INTERFACE (Cont’d)

Bit 0 = SOF Start of frame.

Software should clear this bit after the appropriate

delay.

This bit is set by hardware when a low-speed SOF

indication (keep-alive strobe) is seen on the USB

bus.

Bit 2 = PDWN Power down.

This bit is set by software to turn off the 3.3V on-

chip voltage regulator that supplies the external

pull-up resistor and the transceiver.

0: No SOF signal detected

1: SOF signal detected

Note: To avoid spurious clearing of some bits, it is recom-

mended to clear them using a load instruction

where all bits which must not be altered are set, and

all bits to be cleared are reset. Avoid read-modify-

write instructions like AND , XOR..

0: Voltage regulator on

1: Voltage regulator off

Note: After turning on the voltage regulator, software

should allow at least 3 µs for stabilisation of the

power supply before using the USB interface.

Bit 1 = SUSP Suspend mode.

This bit is set by software to enter Suspend mode.

INTERRUPT MASK REGISTER (IMR)

Read / Write

0: Suspend mode inactive

1: Suspend mode active

Reset Value: 0000 0000 (00h)

7

0

When the hardware detects USB activity, it resets

this bit (it can also be reset by software).

DOV

RM

CTR

M

ERR IOVR ESU

SPM

RES

ETM

SOF

M

Bit 0 = FRES Force reset.

This bit is set by software to force a reset of the

USB interface, just as if a RESET sequence came

from the USB.

Bit 7 = Reserved. Forced by hardware to 0.

Bits 6:0 = These bits are mask bits for all interrupt

condition bits included in the ISTR. Whenever one

of the IMR bits is set, if the corresponding ISTR bit

is set, and the I bit in the CC register is cleared, an

interrupt request is generated. For an explanation

of each bit, please refer to the corresponding bit

description in ISTR.

0: Reset not forced

1: USB interface reset forced.

The USB is held in RESET state until software

clears this bit, at which point a “USB-RESET”

interrupt will be generated if enabled.

DEVICE ADDRESS REGISTER (DADDR)

Read / Write

CONTROL REGISTER (CTLR)

Read / Write

Reset Value: 0000 0000 (00h)

Reset Value: 0000 0110 (06h)

7

0

7

0

ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0

0

RESUME

PDWN

SUSP

FRES

Bit 7 = Reserved. Forced by hardware to 0.

Bits 7:4 = Reserved. Forced by hardware to 0.

Bits 6:0 = ADD[6:0] Device address, 7 bits.

Bit 3 = RESUME Resume.

This bit is set by software to wake-up the Host

when the ST7 is in suspend mode.

Software must write into this register the address

sent by the host during enumeration.

Note: This register is also reset when a USB reset is re-

ceived from the USB bus or forced through bit

FRES in the CTLR register.

0: Resume signal not forced

1: Resume signal forced on the USB bus.

82/144

ST72774/ST727754/ST72734

USB INTERFACE (Cont’d)

ENDPOINT n REGISTER A (EPnRA)

Bits 5:4

=

STAT_TX[1:0] Status bits, for

transmission transfers.

These bits contain the information about the

endpoint status, which are listed below:

Read / Write

Reset Value: 0000 xxxx (0xh)

7

0

STAT_TX1 STAT_TX0 Meaning

DISABLED: transmission

transfers cannot be execut-

ed.

ST_

OUT

DTOG STAT STAT TBC TBC TBC TBC

_TX _TX1 _TX0

0

1

3

2

1

0

STALL: the endpoint is

stalled and all transmission

requests result in a STALL

handshake.

These registers (EP0RA, EP1RA and EP2RA) are

used for controlling data transmission. They are

also reset by the USB bus reset.

NAK: the endpoint is naked

and all transmission re-

quests result in a NAK hand-

shake.

Note: Endpoint 2 and the EP2RA register are not availa-

ble on some devices (see device feature list and

register map).

1

0

1

Bit 7 = ST_OUT Status out.

VALID: this endpoint is ena-

bled for transmission.

This bit is set by software to indicate that a status

out packet is expected: in this case, all nonzero

OUT data transfers on the endpoint are STALLed

instead of being ACKed. When ST_OUT is reset,

OUT transactions can have any number of bytes,

as needed.

These bits are written by software. Hardware sets

the STAT_TX bits to NAK when a correct transfer

has occurred (CTR=1) related to a IN or SETUP

transaction addressed to this endpoint; this allows

the software to prepare the next set of data to be

transmitted.

Bit 6 = DTOG_TX Data Toggle, for transmission

transfers.

It contains the required value of the toggle bit

(0=DATA0, 1=DATA1) for the next transmitted

data packet. This bit is set by hardware at the

reception of a SETUP PID. DTOG_TX toggles only

when the transmitter has received the ACK signal

from the USB host. DTOG_TX and also

DTOG_RX (see EPnRB) are normally updated by

hardware, at the receipt of a relevant PID. They

can be also written by software.

Bits 3:0 = TBC[3:0] Transmit byte count for

Endpoint n.

Before transmission, after filling the transmit

buffer, software must write in the TBC field the

transmit packet size expressed in bytes (in the

range 0-8).

83/144

ST72774/ST727754/ST72734

USB INTERFACE (Cont’d)

ENDPOINT n REGISTER B (EPnRB)

Read / Write

STAT_RX1 STAT_RX0 Meaning

Reset Value: 0000 xxxx (0xh)

DISABLED: reception

0

1

transfers

executed.

cannot

be

7

0

DTOG

_RX

STAT

_RX1

STAT

_RX0

STALL: the endpoint is

stalled and all reception

requests result in a STALL

handshake.

CTRL

EA3 EA2 EA1 EA0

These registers (EP1RB and EP2RB) are used for

controlling data reception on Endpoints 1 and 2.

They are also reset by the USB bus reset.

NAK: the endpoint is na-

ked and all reception re-

quests result in a NAK

handshake.

1

0

1

Note: Endpoint 2 and the EP2RB register are not availa-

ble on some devices (see device feature list and

register map).

VALID: this endpoint is

enabled for reception.

Bit 7 = CTRL Control.

This bit should be 0.

These bits are written by software. Hardware sets

the STAT_RX bits to NAK when a correct transfer

has occurred (CTR=1) related to an OUT or

SETUP transaction addressed to this endpoint, so

the software has the time to elaborate the received

data before acknowledging a new transaction.

Note: If this bit is 1, the Endpoint is a control endpoint.

(Endpoint 0 is always a control Endpoint, but it is

possible to have more than one control Endpoint).

Bit 6 = DTOG_RX Data toggle, for reception

transfers.

It contains the expected value of the toggle bit

(0=DATA0, 1=DATA1) for the next data packet.

This bit is cleared by hardware in the first stage

(Setup Stage) of a control transfer (SETUP

transactions start always with DATA0 PID). The

receiver toggles DTOG_RX only if it receives a

correct data packet and the packet’s data PID

matches the receiver sequence bit.

Bits 3:0 = EA[3:0] Endpoint address.

Software must write in this field the 4-bit address

used to identify the transactions directed to this

endpoint. Usually EP1RB contains “0001” and

EP2RB contains “0010”.

ENDPOINT 0 REGISTER B (EP0RB)

Read / Write

Reset Value: 1000 0000 (80h)

Bit 5:4 = STAT_RX [1:0] Status bits, for reception

transfers.

These bits contain the information about the

endpoint status, which are listed in the following

table:

7

1

0

DTOG STAT STAT

RX RX1 RX0

0

This register is used for controlling data reception

on Endpoint 0. It is also reset by the USB bus

reset.

Bit 7 = Forced by hardware to 1.

Bit 6:4 = Refer to the EPnRB register for a

description of these bits.

Bit 3:0 = Forced by hardware to 0.

84/144

ST72774/ST727754/ST72734

USB INTERFACE (Cont’d)

4.6.5 Programming Considerations

In the following, the interaction between the USB

3. Enable the endpoint by setting the STAT_TX

bits to VALID (11b) in EPnRA.

interface and the application program is described.

Apart from system reset, action is always initiated

by the USB interface, driven by one of the USB

events associated with the Interrupt Status

Register (ISTR) bits.

Note: Once transmission and/or reception are enabled,

registers EPnRA and/or EPnRB (respectively) must

not be modified by software, as the hardware can

change their value on the fly.

When the operation is completed, they can be

accessed again to enable a new operation.

4.6.5.1 Initializing the Registers

4.6.5.4 Interrupt Handling

Start of Frame (SOF)

At system reset, the software must initialize all

registers to enable the USB interface to properly

generate interrupts and DMA requests.

The interrupt service routine must monitor the SOF

events and measure the interval between each

SOF event. If 3ms pass without a SOF event, the

software should set the USB interface to suspend

mode.

1. Initialize the DMAR, IDR, and IMR registers

(choice of enabled interrupts, address of DMA

buffers). Refer the paragraph titled initializing

the DMA Buffers.

USB Reset (RESET)

2. Initialize the EP0RA and EP0RB registers to

enable accesses to address 0 and endpoint 0

to support USB enumeration. Refer to the para-

graph titled Endpoint Initialization.

When this event occurs, the DADDR register is

reset, and communication is disabled in all

endpoint registers (the USB interface will not

respond to any packet). Software is responsible for

reenabling endpoint 0 within 10 ms of the end of

reset. To do this you set the STAT_RX bits in the

EP0RB register to VALID.

3. When addresses are received through this

channel, update the content of the DADDR.

4. If needed, write the endpoint numbers in the EA

fields in the EP1RB and EP2RB register.

4.6.5.2 Initializing DMA buffers

End Suspend (ESUSP)

The DMA buffers are a contiguous zone of

memory whose maximum size is 48 bytes. They

can be placed anywhere in the memory space,

typically in RAM, to enable the reception of

messages. The 10 most significant bits of the start

of this memory area are specified by bits DA15-

DA6 in registers DMAR and IDR, the remaining

bits are 0. The memory map is shown in Figure 51.

The CPU is alerted by activity on the USB, which

causes an ESUSP interrupt.

Correct Transfer (CTR)

1. When this event occurs, the hardware automat-

ically sets the STAT_TX or STAT_RX to NAK.

Note: Every valid endpoint is NAKed until software clears

the CTR bit in the ISTR register, independently of

the endpoint number addressed by the transfer

which generated the CTR interrupt.

Each buffer is filled starting from the bottom (last 3

address bits=000) up.

Note: If the event triggering the CTR interrupt is a SETUP

transaction, both STAT_TX and STAT_RX are set

to NAK.

4.6.5.3 Endpoint Initialization

To be ready to receive:

2. Read the PIDR to obtain the token and the IDR

to get the endpoint number related to the last

transfer.

Set STAT_RX to VALID (11b) in EP0RB to enable

reception.

Note: When a CTR interrupt occurs, the TP3-TP2 bits in

the PIDR register and EP1-EP0 bits in the IDR reg-

ister stay unchanged until the CTR bit in the ISTR

register is cleared.

To be ready to transmit:

1. Write the data in the DMA transmit buffer.

2. In register EPnRA, specify the number of bytes

to be transmitted in the TBC field

3. Clear the CTR bit in the ISTR register.

85/144

ST72774/ST727754/ST72734

USB INTERFACE (Cont’d)

Table 23. USB Register Map and Reset Values

Address

(Hex.)

Register

Name

7

6

5

4

3

2

1

0

PIDR

TP3

x

TP2

x

0

RX_SEZ

0

RXD

0

25

26

27

28

29

2A

2B

2C

2D

2E

2F

30

31

Reset Value

0

DMAR

DA15

x

DA14

x

DA13

x

DA12

x

DA11

x

DA10

x

DA9

x

DA8

x

Reset Value

IDR

DA7

x

DA6

x

EP1

x

EP0

x

CNT3

0

CNT2

0

CNT1

0

CNT0

0

Reset Value

ISTR

SUSP

0

DOVR

0

CTR

0

ERR

0

IOVR

0

ESUSP

0

RESET

0

SOF

0

Reset Value

IMR

SUSPM

0

DOVRM

0

CTRM

0

ERRM

0

IOVRM ESUSPM RESETM SOFM

Reset Value

0

CTLR

0

RESUME PDWN

FSUSP

1

FRES

0

Reset Value

0

1

DADDR

0

ADD6

0

ADD5

0

ADD4

0

ADD3

0

ADD2

0

ADD1

0

ADD0

0

Reset Value

EP0RA

ST_OUT DTOG_TX STAT_TX1 STAT_TX0

TBC3

x

TBC2

x

TBC1

x

TBC0

x

Reset Value

0

EP0RB

1

DTOG_RX STAT_RX1 STAT_RX0

0

Reset Value

0

EP1RA

ST_OUT DTOG_TX STAT_TX1 STAT_TX0

TBC3

x

TBC2

x

TBC1

x

TBC0

x

Reset Value

0

EP1RB

CTRL

0

DTOG_RX STAT_RX1 STAT_RX0

EA3

x

EA2

x

EA1

x

EA0

x

Reset Value

0

EP2RA

ST_OUT DTOG_TX STAT_TX1 STAT_TX0

TBC3

x

TBC2

x

TBC1

x

TBC0

x

Reset Value

0

EP2RB

CTRL

0

DTOG_RX STAT_RX1 STAT_RX0

EA3

x

EA2

x

EA1

x

EA0

x

Reset Value

0

86/144

ST72774/ST727754/ST72734

4.7 I²C SINGLE MASTER BUS INTERFACE (I2C)

4.7.1 Introduction

Mode Selection

2

The I C Bus Interface serves as an interface

The interface can operate in the two following

modes:

2

between the microcontroller and the serial I C bus.

It provides single master functions, and controls all

2

– Master transmitter/receiver

By default, it is idle.

I C bus-specific sequencing, protocol and timing.

It supports fast I²C mode (400kHz).

The interface automatically switches from idle to

master after it generates a START condition and

from master to idle after it generates a STOP

condition.

4.7.2 Main Features

2

– Parallel bus/I C protocol converter

– Interrupt generation

2

– Standard I C mode/Fast I C mode

Communication Flow

– 7-bit Addressing

The interface initiates a data transfer and

generates the clock signal. A serial data transfer

always begins with a start condition and ends with

a stop condition. Both start and stop conditions are

generated by software.

2

■ I C single Master Mode

– End of byte transmission flag

– Transmitter/Receiver flag

– Clock generation

4.7.3 General Description

In addition to receiving and transmitting data, this

interface converts it from serial to parallel format

and vice versa, using either an interrupt or polled

handshake. The interrupts are enabled or disabled

Data and addresses are transferred as 8-bit bytes,

MSB first. The first byte following the start

condition is the address byte.

A 9th clock pulse follows the 8 clock cycles of a

byte transfer, during which the receiver must send

an acknowledge bit to the transmitter. Refer to

Figure 52.

2

by software. The interface is connected to the I C

bus by a data pin (SDAI) and by a clock pin (SCLI).

2

It can be connected both with a standard I C bus

2

and a Fast I C bus. This selection is made by

software.

2

Figure 52. I C BUS Protocol

SDA

MSB

ACK

SCL

1

2

8

9

START

STOP

CONDITION

VR02119B

87/144

ST72774/ST727754/ST72734

I²C SINGLE MASTER BUS INTERFACE (Cont’d)

Acknowledge may be enabled and disabled by

The SCL frequency (F ) is controlled by a

scl

software.

programmable clock divider which depends on the

I C bus mode.

2

The speed of the I C interface may be selected

between Standard (0-100KHz) and Fast I C (100-

400KHz).

2

When the I2C cell is enabled, the SDA and SCL

ports must be configured as floating open-drain

output or floating input. In this case, the value of

the external pull-up resistance used depends on

the application.

SDA/SCL Line Control

Transmitter mode: the interface holds the clock

line low before transmission to wait for the

microcontroller to write the byte in the Data

Register.

When the I2C cell is disabled, the SDA and SCL

ports revert to being standard I/O port pins.

Receiver mode: the interface holds the clock line

low after reception to wait for the microcontroller to

read the byte in the Data Register.

2

Figure 53. I C Interface Block Diagram

DATA REGISTER (DR)

DATA SHIFT REGISTER

SDAI

DATA CONTROL

SDA

SCLI

CLOCK CONTROL

SCL

CLOCK CONTROL REGISTER (CCR)

CONTROL REGISTER (CR)

STATUS REGISTER 1 (SR1)

STATUS REGISTER 2 (SR2)

CONTROL LOGIC

INTERRUPT

88/144

ST72774/ST727754/ST72734

I²C SINGLE MASTER BUS INTERFACE (Cont’d)

4.7.4 Functional Description (Master Mode)

Refer to the CR, SR1 and SR2 registers in Section

4.7.5. for the bit definitions.

– Acknowledge pulse if if the ACK bit is set

– EVF and BTF bits are set by hardware with an in-

terrupt if the ITE bit is set.

Then the interface waits for a read of the SR1

2

By default the I C interface operates in idle mode

register followed by a read of the DR register,

holding the SCL line low (see Figure 54 Transfer

sequencing EV3).

(M/IDL bit is cleared) except when it initiates a

transmit or receive sequence.

To switch from default idle mode to Master mode a

Start condition generation is needed.

To close the communication: before reading the

last byte from the DR register, set the STOP bit to

generate the Stop condition. The interface goes

automatically back to idle mode (M/IDL bit

cleared).

Start condition and Transmit Slave address

Setting the START bit causes the interface to

switch to Master mode (M/IDL bit set) and

generates a Start condition.

Note: In order to generate the non-acknowledge pulse af-

ter the last received data byte, the ACK bit must be

cleared just before reading the second last data

byte.

Once the Start condition is sent:

– The EVF and SB bits are set by hardware with

an interrupt if the ITE bit is set.

Master Transmitter

Then the master waits for a read of the SR1

Following the address transmission and after SR1

register has been read, the master sends bytes

from the DR register to the SDA line via the internal

shift register.

register followed by a write in the DR register with

the Slave address byte, holding the SCL line low

(see Figure 54 Transfer sequencing EV1).

The master waits for a read of the SR1 register

followed by a write in the DR register, holding the

SCL line low (see Figure 54 Transfer sequencing

EV4).

Then the slave address byte is sent to the SDA line

via the internal shift register.

After completion of this transfer (and acknowledge

from the slave if the ACK bit is set):

When the acknowledge bit is received, the

interface sets:

– The EVF bit is set by hardware with interrupt

generation if the ITE bit is set.

Then the master waits for a read of the SR1

– EVF and BTF bits with an interrupt if the ITE bit

is set.

To close the communication: after writing the last

register followed by a write in the CR register (for

example set PE bit), holding the SCL line low

(see Figure 54 Transfer sequencing EV2).

byte to the DR register, set the STOP bit to

generate the Stop condition. The interface goes

automatically back to idle mode (M/IDL bit

cleared).

Next the master must enter Receiver or

Transmitter mode.

Error Case

– AF: Detection of a non-acknowledge bit. In this

case, the EVF and AF bits are set by hardware

with an interrupt if the ITE bit is set. To resume,

set the START or STOP bit.

Master Receiver

Following the address transmission and after SR1

and CR registers have been accessed, the master

receives bytes from the SDA line into the DR

register via the internal shift register. After each

byte the interface generates in sequence:

Note: The SCL line is not held low.

89/144

ST72774/ST727754/ST72734

I²C SINGLE MASTER BUS INTERFACE (Cont’d)

Figure 54. Transfer Sequencing

Master receiver:

S

Address

A

Data1

A

Data2

A

DataN NA

P

.....

EV1

EV2

EV3

A

EV3

A

EV3

A

Master transmitter:

S

Address

A

Data1

Data2

DataN

P

.....

EV1

EV2 EV4

EV4

Legend:

S=Start, P=Stop, A=Acknowledge, NA=Non-acknowledge

EVx=Event (with interrupt if ITE=1)

EV1: EVF=1, SB=1, cleared by reading SR1 register followed by writing DR register.

EV2: EVF=1, cleared by reading SR1 register followed by writing CR register (for example PE=1).

EV3: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register.

EV4: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register.

Figure 55. Event Flags and Interrupt Generation

ITE

BTF

SB

AF

INTERRUPT

*

EVF

* EVF can also be set by EV2 or an error from the SR2 register.

*

90/144

ST72774/ST727754/ST72734

I²C SINGLE MASTER BUS INTERFACE (Cont’d)

4.7.5 Register Description

I C CONTROL REGISTER (CR)

Read / Write

Reset Value: 0000 0000 (00h)

Bit 2 = ACK Acknowledge enable.

2

This bit is set and cleared by software. It is also

cleared by hardware when the interface is disabled

(PE=0).

0: No acknowledge returned

1: Acknowledge returned after a data byte is re-

ceived

7

0

PE

0

START ACK STOP

ITE

Bit 1 = STOP Generation of a Stop condition.

This bit is set and cleared by software. It is also

cleared by hardware when the interface is disabled

(PE=0) or when the Stop condition is sent.

Bit 7:6 = Reserved. Forced to 0 by hardware.

Bit 5 = PE Peripheral enable.

This bit is set and cleared by software.

In Master mode only:

0: Peripheral disabled

1: Master capability

0: No stop generation

1: Stop generation after the current byte transfer

or after the current Start condition is sent.

Note: When PE=0, all the bits of the CR register and the

SR register except the Stop bit are reset. All outputs

are released while PE=0

Bit 0 = ITE Interrupt enable.

This bit is set and cleared by software and cleared

by hardware when the interface is disabled

(PE=0).

Note: When PE=1, the corresponding I/O pins are select-

ed by hardware as alternate functions.

2

Note: To enable the I C interface, write the CR register

TWICE with PE=1 as the first write only activates

0: Interrupts disabled

1: Interrupts enabled

the interface (only PE is set).

Bit 4 = Reserved. Forced to 0 by hardware.

Refer to Figure 55 for the relationship between the

events and the interrupt.

Bit 3 = START Generation of a Start condition.

This bit is set and cleared by software. It is also

cleared by hardware when the interface is disabled

(PE=0) or when the Start condition is sent (with

interrupt generation if ITE=1).

SCL is held low when the SB or BTF flags or an

EV2 event (See Figure 54) is detected.

In master mode:

0: No start generation

1: Repeated start generation

In idle mode:

0: No start generation

1: Start generation when the bus is free

91/144

ST72774/ST727754/ST72734

I²C SINGLE MASTER BUS INTERFACE (Cont’d)

I C STATUS REGISTER 1 (SR1)

2

– Following a byte transmission, this bit is set after

reception of the acknowledge clock pulse. In

case an address byte is sent, this bit is set only

after the EV2 event (See Figure 54). BTF is

cleared by reading SR1 register followed by writ-

ing the next byte in DR register.

Read Only

Reset Value: 0000 0000 (00h)

7

0

– Following a byte reception, this bit is set after

transmission of the acknowledge clock pulse if

ACK=1. BTF is cleared by reading SR1 register

followed by reading the byte from DR register.

The SCL line is held low while BTF=1.

EVF

0

TRA

0

BTF

0

M/IDL

SB

Bit 7 = EVF Event flag.

This bit is set by hardware as soon as an event

occurs. It is cleared by software reading SR2

register in case of error event or as described in

Figure 54. It is also cleared by hardware when the

interface is disabled (PE=0).

0: Byte transfer not done

1: Byte transfer succeeded

Bit 2 = Reserved. Forced to 0 by hardware.

Bit 1 = M/IDL Master/Idle.

0: No event

This bit is set by hardware as soon as the interface

is in Master mode (writing START=1). It is cleared

by hardware after generating a Stop condition on

the bus. It is also cleared when the interface is

disabled (PE=0).

1: One of the following events has occurred:

– BTF=1 (Byte received or transmitted)

– SB=1 (Start condition generated)

– AF=1 (No acknowledge received after byte

transmission if ACK=1)

0: Idle mode

1: Master mode

– Address byte successfully transmitted.

Bit 6 = Reserved. Forced to 0 by hardware.

Bit 0 = SB Start bit generated.

This bit is set by hardware as soon as the Start

Bit 5 = TRA Transmitter/Receiver.

condition is generated (following

a

write

When BTF is set, TRA=1 if a data byte has been

transmitted. It is cleared automatically when BTF

is cleared. It is also cleared by hardware when the

interface is disabled (PE=0).

START=1). An interrupt is generated if ITE=1. It is

cleared by software reading SR1 register followed

by writing the address byte in DR register. It is also

cleared by hardware when the interface is disabled

(PE=0).

0: Data byte received (if BTF=1)

1: Data byte transmitted

0: No Start condition

1: Start condition generated

Bit 4 = Reserved. Forced to 0 by hardware.

Bit 3 = BTF Byte transfer finished.

This bit is set by hardware as soon as a byte is

correctly received or transmitted with interrupt

generation if ITE=1. It is cleared by software

reading SR1 register followed by a read or write of

DR register. It is also cleared by hardware when

the interface is disabled (PE=0).

92/144

ST72774/ST727754/ST72734

I²C SINGLE MASTER BUS INTERFACE (Cont’d)

I C STATUS REGISTER 2 (SR2)

Read Only

2

0: Standard I C mode

2

1: Fast I C mode

Reset Value: 0000 0000 (00h)

Bit 6:0 = CC6-CC0 7-bit clock divider.

7

0

These bits select the speed of the bus (F

)

SCL

2

depending on the I C mode. They are not cleared

when the interface is disabled (PE=0).

0

AF

0

– Standard mode (FM/SM=0): F

<= 100kHz

SCL

F

= F

/(2x([CC6..CC0]+2))

SCL

CPU

Bit 7:5 = Reserved. Forced to 0 by hardware.

– Fast mode (FM/SM=1): F

> 100kHz

SCL

F

= F

/(3x([CC6..CC0]+2))

SCL

CPU

Note: The programmed F

assumes no load on SCL

Bit 4 = AF Acknowledge failure.

SCL

and SDA lines.

This bit is set by hardware when no acknowledge

is returned. An interrupt is generated if ITE=1. It is

cleared by software reading SR2 register or by

hardware when the interface is disabled (PE=0).

2

I C DATA REGISTER (DR)

Read / Write

The SCL line is not held low while AF=1.

0: No acknowledge failure

Reset Value: 0000 0000 (00h)

7

0

1: Acknowledge failure

D7

D6

D5

D4

D3

D2

D1

D0

Bit 3:0 = Reserved. Forced to 0 by hardware.

Bit 7:0 = D7-D0 8-bit Data Register.

2

These bits contains the byte to be received or

transmitted on the bus.

I C CLOCK CONTROL REGISTER (CCR)

Read / Write

Reset Value: 0000 0000 (00h)

– Transmitter mode: Byte transmission start auto-

matically when the software writes in the DR reg-

ister.

7

0

– Receiver mode: the first data byte is received au-

tomatically in the DR register using the least sig-

nificant bit of the address.

FM/SM CC6

CC5

CC4

CC3

CC2

CC1

CC0

Then, the next data bytes are received one by

one after reading the DR register.

2

Bit 7 = FM/SM Fast/Standard I C mode.

This bit is set and cleared by software. It is not

cleared when the interface is disabled (PE=0).

93/144

ST72774/ST727754/ST72734

I2C SINGLE MASTER BUS INTERFACE (Cont’d)

2

Table 24. I C Register Map

Address

(Hex.)

Register

Name

7

6

5

4

3

2

1

0

CR

PE

0

START

0

ACK

0

STOP

0

ITE

0

5F

5E

5D

5C

59

Reset Value

0

SR1

EVF

0

TRA

0

BTF

0

M/IDL

0

SB

0

Reset Value

0

SR2

AF

0

Reset Value

0

CCR

FM/SM

0

CC6

0

CC5

0

CC4

0

CC3

0

CC2

0

CC1

0

CC0

0

Reset Value

DR

DR7

0

DR6

0

DR5

0

DR4

0

DR3

0

DR2

0

DR1

0

DR0

0

Reset Value

94/144

ST72774/ST727754/ST72734

4.8 DDC INTERFACE (DDC)

2

4.8.1 Introduction

■ I C byte, random and sequential read modes

The DDC (Display Data Channel) Bus Interface is

■ DMA transfer from any memory location and to

mainly used by the monitor to identify itself to the

video controller, by the monitor manufacturer to

perform factory alignment, and by the user to

adjust the monitor’s parameters.

RAM

■ Automatic memory address incrementation

■ End of data downloading flag and interrupt

capability

The DDC interface consists of two parts:

4.8.2.2 DDC/CI - Factory Interface Features

General I C Features:

■ A

fully hardware-implemented interface,

2

supporting DDC1 and DDC2B (VESA

specification 3.0 compliant). It accesses the

ST7 on-chip memory directly through a built-in

DMA engine.

2

– Parallel bus /I C protocol converter

– Interrupt generation

2

■ A second interface, supporting the slave I C

– Standard I C mode/Fast I C mode

functions for handling DDC/CI mode (DDC2Bi),

factory alignment or Enhanced DDC (EDDC) by

software.

– 7-bit Addressing

I C Slave Features:

2

– I C bus busy flag

4.8.2 DDC Interface Features

– Start bit detection flag

4.8.2.1 Hardware DDC1/2B Interface Features

– Detection of misplaced Start or Stop condition

– Transfer problem detection

■ Full

hardware

support

for

DDC1/2B

communications (VESA specification versions 2

and 3)

– Address Matched detection

■ Hardware detection of DDC2B addresses A0h/

A1h and optionally A2h/A3h (P&D) or A6h/A7h

(FPDI-2)

■ Separate mapping of EDID version 1 (128

bytes) and EDID version 2 (256 bytes) when

both must coexist

– Programmable Address detection and/or

Hardware detection of Enhanced DDC (ED-

DC) addresses (60h/61h)

– End of byte transmission flag

– Transmitter/Receiver flag

– Stop condition Detection

■ Support for error recovery mechanism

■ Detection of misplaced Start and Stop

conditions

Figure 56. DDC Interface Overview

I2C SLAVE

INTERFACE

SDA

SCL

SDAD

SCLD

(DDC/CI - Factory Alignment)

HARDWARE DDC1/2B

INTERFACE

VSYNCI

VSYNC

VSYNC2

VSYNCI2

95/144

ST72774/ST727754/ST72734

DDC INTERFACE (Cont’d)

Figure 57. DDC Interface Block Diagram

DDC1/2B CONTROL REGISTER (DCR)

DMA

ADDRESS LOW REGISTER (ALR)

CONTROLLER

ADDRESS/DATA

CONTROL LOGIC

ADDRESS HIGH REGISTER (AHR)

DATA CONTROL

SDAD

DATA SHIFT REGISTER

DDC1/2B

CONTROL LOGIC

SCLD

VSYNCI

VSYNCI2

HWDDC

INTERRUPT

DDC1/2B (for MONITOR IDENTIFICATION)

Bit in

MISCR

Register

DATA REGISTER (DR)

DATA CONTROL

DATA SHIFT REGISTER

COMPARATOR

OWN ADDRESS REGISTER (OAR)

HARDWARE ADDRESS

DDC/CI-Factory CONTROL REGISTER (CR)

CONTROL LOGIC

DDC

INTERRUPT

STATUS REGISTER 1 (SR1)

STATUS REGISTER 2 (SR2)

(DDC/CI (for MONITOR ADJUSTMENT and CONTROL)

96/144

ST72774/ST727754/ST72734

DDC INTERFACE (Cont’d)

4.8.3 Signal Description

Serial Data (SDA)

Transmit-only Clock (Vsync/Vsync2)

The Vsync input pins are used to synchronize all

data in and out of the device when in Transmit-only

mode.

These pins are ONLY used by the DDC1/2B

interface (when in DDC1 mode).

The SDA bidirectional pin is used to transfer data

in and out of the device. It is an open-drain output

that may be or-wired with other open-drain or

open-collector pins. An external pull-up resistor

must be connected to the SDA line. Its value

depends on the load of the line and the transfer

rate.

Serial Clock (SCL)

The SCL input pin is used to synchronize all data in

2

and out of the device when in I C bidirectional

mode. An external pull-up resistor must be

connected to the SCL line. Its value depends on

the load of the line and the transfer rate.

Note:When the DDC1/2B and DDC/CI-Factory Interfaces

are disabled (HWPE bit=0 in the DCR register and

PE bit=0 in the CR register), SDA and SCL pins re-

vert to standard I/O pins.

97/144

ST72774/ST727754/ST72734

DDC INTERFACE (Cont’d)

2

4.8.4 I C BUS Protocol

4.8.4.3 Data Transfer

2

A standard I C communication is normally based

Once the slave address is acknowledged, the data

transfer can proceed in the direction given by the

R/W bit sent in the address.

on four parts: START condition, device slave

address transmission, data transfer and STOP

condition. They are described brielfly in the

following section and illustrated in Figure 58 (for

Data is transferred with the most significant bit

(MSB) first. Data bits can be changed only when

SCL is low and must be held stable when SCL is

high.

2

more details, refer to the I C bus specification).

4.8.4.1 START condition

One complete data byte transfer requires 9 clock

pulses: 8 bits + 1 acknowledge bit.

When the bus is free (both SCL and SDA lines are

at a high level), a master can initiate a

communication by sending a START signal. This

signal is defined as a high-to-low transition of SDA

while SCL is stable high. The bus is considered to

be busy after a START condition.

4.8.4.4 Acknowledge Bit (ACK / NACK)

Every byte put on the SDA line is 8-bit long

followed by an acknowledge bit.

This bit is used to indicate a successful data

transfer. The bus transmitter, either master or

slave, releases the SDA line during the 9th clock

period (after sending all 8 bits of data), then:

This START condition must precede any

command for data transfer.

4.8.4.2 Slave Address Transmission

The first byte following a START condition is the

slave address transmitted by the master. This

address is 7-bit long followed by an 8th bit (Least

significant bit: LSB) which is the data direction bit

(R/W bit).

– To generate an Acknowledge (ACK) of the cur-

rent byte, the receiver pulls the SDA line low.

– To generate a No-Acknowledge (NACK) of the

current byte, the receiver releases the SDA line

(hence at a high level).

4.8.4.5 STOP Condition

– A “0” indicates a transmission (WRITE) from the

master to the slave.

A STOP condition is defined by a low-to-high

transition of SDA while SCL is stable high. It ends

the communication between the Interface and the

bus master.

– A “1” indicates a request for data (READ) from

the slave to the master.

If a slave device is present on the bus at the given

2

address, an Acknowledge will be generated on the

9th clock pulse.

Figure 58. I C Signal Diagram

SDA

SCL

Ack

STOP

DataN(F0h)

Start

A0h

Ack

00h

Data Address

Ack

Data1(B0h) Ack

Device Slave Address

WRITE DATA TO I2C DEVICE (Slave Address A0h)

SDA

SCL

Start

A1h

Ack

Data1(00h) Ack

Data2(B0h) Ack

DataN(F0h)

STOP

Nack

Device Slave Address

READ DATA FROM I2C DEVICE (Slave Address A1h)

98/144

ST72774/ST727754/ST72734

DDC INTERFACE (Cont’d)

4.8.5 DDC Standard

The DDC standard is divided in several data

transfer protocols: DDC1, DDC2B, DDC/CI.

– Write operations into RAM.

– Read operations from RAM.

In DDC1, the interface reads sequential EDID v1

data bytes from the microcontroller memory, and

transmits them on SDA synchronized with Vsync.

For DDC1/2B, refer to the “VESA DDC Standard

v3.0” specification. For DDC/CI refer to the “VESA

DDC Commands Interface v1.0”

2

In DDC2B mode, it operates in I C slave mode.

– DDC1 is a uni-directional transmission of EDID

v1 (128 bytes) from display to host clocked by

VSYNCI.

The DDC1/2B Interface supports several DDC

versions configured using the CF[2:0] bits in the

DCR register which can only be changed while the

interface is disabled (HWPE bit=0 in the DCR

register). They define which EDID structure

version is used and which Device Addresses are

recognized.

– DDC2B is a uni-directional channel from display

2

to host. The host computer uses base-level I C

commands to read the EDID data from the dis-

play which is always in slave mode.

Specific types of display contain EDID at fixed

2

I C device addresses within the device (refer to

Depending on the DDC version, one or two device

address pairs will be recognized and the

corresponding EDID structure will be validated

(refer to Table 25):

Table 25).

– DDC/CI is a bi-directional channel between the

host computer and the display. The DDC/CI of-

2

fers a display control interface based on I C bus.

It includes the DDC2Bi and DDC2AB standards.

– DDC v2 (CF2=0,CF1=0,CF0=0): DDC1 is ena-

bled and device addresses A0h/A1h are recog-

nized. EDID v1 is used.

Note: The DDC2AB standard is no longer handled by the

interface.

– DDC v2 (CF2=1,CF1=0,CF0=0): DDC1 is disa-

bled and device addresses A0h/A1h are recog-

nized. EDID v1 is used.

4.8.5.1 DDC1/2B Interface

4.8.5.1.1 Functionnal description

Refer to the DCR, AHR registers in Section 4.8.6.

for the bit definitions.

– Plug and Display (CF2=0,CF1=0,CF0=1):

DDC1 is disabled and device addresses A2h/

A3h are recognized. EDID v2 is used.

The DDC1/2B Interface acts as an I/O interface

between a DDC bus and the microcontroller

memory. In addition to receiving and transmitting

serial data, this interface directly transfers parallel

data to and from memory using a DMA engine,

only halting CPU activity for two clock cycles

during each byte transfer.

– Plug and Display + DDC v2 (CF2=0,CF1=1,

CF0=0): DDC1 is enabled and device addresses

A0h/A1h and A2h/A3h are recognized. Both

EDID structures v1 and v2 are used.

– Plug and Display + DDC v2 (CF2=1,CF1=1,

CF0=0): DDC1 is disabled and device addresses

A0h/A1h and A2h/A3h are recognized. Both

EDID structures v1 and v2 are used.

The interface supports by hardware:

– FPDI (CF2=0,CF1=1, CF0=1): DDC1 is disabled

and device addresses A6h/A7h are recognized.

EDID v2 is used.

– Two DDC communication protocols called DDC1

and DDC2B.

Table 25. Valid Device Addresses and EDID structure

Device Address

EDID v1:

A0h / A1h = 1010 000x

CF2 bit

CF1 bit

CF0 bit Transfer Type

x

0

128-byte EDID structure write/read

0

1

0

1

0

EDID v2:

256-byte EDID structure write/read

A2h / A3h = 1010 001x

EDID v2:

A6h / A7h = 1010 011x

reserved

1

x

1

256-byte EDID structure write/read

reserved

99/144

ST72774/ST727754/ST72734

DDC INTERFACE (Cont’d)

The Write and Read operations allow the EDID

register while the HWPE bit=0 and then set the

HWPE bit to enable the DDC1/2B Interface.

A proper initialization sequence (see Figure 59)

must supply nine clock pulses on the VSYNCI pin

in order to internally synchronize the device.

During this initialization sequence, the SDA pin is

in high impedance. On the rising edge of the 10th

pulse applied on VSYNCI, the device outputs on

SDA the most significant (MSB) bit of the byte

located at data address 00h.

data to be downloaded during factory alignment

(for example).

Writes to the memory by the DMA engine can be

inhibited by means of the WP bit in the DCR

register.

A write of the last data structure byte sets a flag

and may be programmed to generate an interrupt

request.

The Data address (sub-address) is either the

second byte of write transfers or is pointed to by

the internal address counter automatically

incremented after each byte transfer.

Physical address mapping of the data structure

within the memory space is performed with a

dedicated register accessible by software.

A byte is clocked out by means of 9 clock pulses

on Vsync, 8 clock pulses for the data byte itself and

an extra pulse for a Don’t Care bit.

As long as SCL is not held low, each byte of the

memory array is transmitted serially on SDA.

The internal address counter is incremented

automatically until the last byte is transmitted.

Then, it rolls over to relative location 00h.

The physical mapping of the data structure

depends on the configuration and on the content of

the AHR register which can be set by software

(see Figure 60).

4.8.5.1.2 Mode description

DDC1 Mode: This mode is only enabled when the

DDC v2 or P&D-DDC v2 standards are validated. It

transmits only the EDID v1 data (128 bytes).

To switch the DDC1/2B Interface to DDC1 mode,

software must first clear the CF0 bit in the DCR

Figure 59. DDC1 Waveforms

PE

SCL

XX

00h

ALR

Bit 6

Bit 7

SDA

Vsync

1

2

8

9

10

11

PE

SCL

7Fh

00h

Bit 7

ALR

Bit 7

Bit 6

Bit 0

Bit 6

SDA

Vsync

100/144

ST72774/ST727754/ST72734

DDC INTERFACE (Cont’d)

Figure 60. Mapping of DDC1 data structure

DDC v2 mode: CF[1:0] bits = 00b

FFFFh

6

15

8 7

0

128-byte Data

Structure

Addr Pointer

ALR

AHR

ALR

256 * AHR

0000h

Note:

MSB of ALR is always ‘0’

DDC v2 + P&D mode: CF[1:0] bits = 10b

FFFFh

128-byte Data

Structure

ALR

15

9 8 7

0

AHR[7:1]

Notes:

1

ALR

Addr Pointer

Reserved

512 * AHR[7:1]

- LSB of AHR is ignored and taken as ‘1’

- MSB of ALR is always ‘0’

0000h

DDC2B Transition Mode: This mode avoids the

display switching to DDC2B mode if spurious

noise is detected on SCL while the host is in DDC1

mode.

received within either 128 Vsync pulses or a period

of approximately 2 seconds, then the interface will

revert to DDC1 mode at the EDID start address.

If the interface decodes a valid DDC2B Device

Address, it will lock into DDC2B mode and

subsequently disregard VSYNCI.

When in transition mode, the Vsync pulse counter

or the 2-sec. timeout counter is reset by any

activity on the SCL line.

When the DDC1/2B interface is in DDC1 mode

and detects a falling edge on SCL, it enters the

transition state (see Figure 61).

2

If a valid I C sequence (START followed by a valid

Device Address for CF0 =0 (see Table 25)) is not

Figure 61. Transition Mode Waveforms

Transition mode

DDC1 mode

SCL

ALR

00h

01h

SDA

Vsync

101/144

ST72774/ST727754/ST72734

DDC INTERFACE (Cont’d)

DDC2B Mode: The DDC1/2B Interface enters

not respond (no acknowledge) until one is found.

A STOP condition at the end of a Read command

(after a NACK) forces the stand-by state. A STOP

condition at the end of a Write command triggers

the internal DMA write cycle.

The Interface samples the SDA line on the rising

edge of SCL and outputs data on the falling edge

of SCL. In any case SDA can only change when

SCL is low.

DDC2B mode either from the transition state or

from the initial state if software sets the HWPE bit

while P&D only or FPDI-2 mode is selected.

Once in DDC2B mode, the Interface always acts

as a slave following the protocol described in

Figure 62.

The DDC1/2B Interface continuously monitors the

SDA and SCL lines for a START condition and will

Figure 62. DDC2B protocol (example)

SDA

SCL

Ack

00h

Data Address

Ack

Nack

Stop

Data1

DataN

Start A0h

StopStart A1h

Device Slave

Address

Device Slave

Address

128 / 256 bytes EDID

Legend:

Bold = data / control signal from host

Italics = data / control signal from display

102/144

ST72774/ST727754/ST72734

Figure 63. DDC1/2B Operation Flowchart

Wait for HWPE = 1

HWPE bit = 0

CF0 = 0

N

and

CF2 = 0 ?

Y

Relative Address (ALR) = 0

Vsync

Y

Send Next Bit

N

SCL

N

Y

SDA Hi-Z

Vsync Counter = 0

Start 2-sec Timer

SCL

Y

Vsync Counter = 0

Re-Start 2-sec Timer

N

Received valid

Device Address?

Y

N

Relative Address (ALR) = 0

N

Vsync

Y

N

Received valid

Device Address?

Vsync Counter += 1

Y

Send Acknowledge

Counter = 128

or Timer expired ?

N

Respond to Command

Y

103/144

ST72774/ST727754/ST72734

DDC INTERFACE (Cont’d)

EDID Data structure mapping: An internal

byte within the data structure currently addressed.

ALR is reset upon entry into the DDC2B mode.

address pointer defines the memory location being

addressed. It is made of two 8-bit registers AHR

and ALR.

AHR is initialized by software. It defines the 256-

byte block within the 64K address space

containing the data structure.

One exception to this arrangement is when the

CF[1:0] bits = 10b. In this case the two EDID

versions must coexist at non-overlapping

addresses. The LSB of AHR is therefore ignored

and automatically set to 1 to address the 128-byte

EDID and set to 0 to address its 256-byte

counterpart (see Figure 64).

ALR is loaded with the data address sent by the

master after a write Device Address. It defines the

Figure 64. Mapping of DDC2B data structure

DDC v2 / P&D / FPDI-2 modes: CF[1:0] bits != 10b

Basic EDID v1

Extended EDID v1 (if present)

FFFFh

EDID v2

FFFFh

128-byte Data

Structure

256-byte Data

Structure

ALR :

80h -> FFh

128-byte Data

Structure

ALR :

00h -> 7Fh

ALR

256

*

AHR

0000h

AHR

0000h

A2h/A3h + A6h/A7h

A0h/A1h

8 7

15

0

Addr Pointer

ALR

DDC v2 + P&D mode: CF[1:0] bits = 10b

Basic EDID v1

Extended EDID v1 (if present)

EDID v2

FFFFh

128-byte Data

Structure

ALR :

80h -> FFh

128-byte Data

Structure

ALR :

00h -> 7Fh

256-byte Data

Structure

ALR

512

*

AHR<7:1>

0000h

A0h/A1h

15

A0h/A1h

0

A2h/A3h

15

0

9 8 7

1

9 8 7

0

Addr Pointer

AHR<7:1>

ALR

AHR<7:1>

ALR

104/144

ST72774/ST727754/ST72734

DDC INTERFACE (Cont’d)

■ Write Operation

Once the DDC1/2B Interface has acknowledged a

After each byte is transferred, the internal address

counter is automatically incremented.

write transfer request, i.e. a Device Address with

RW=0, it waits for a data address. When the latter

is received, it is acknowledged and loaded into the

ALR.

Then, the master may send any number of data

bytes that are all acknowledged by the DDC1/2B

Interface. The data bytes are written in RAM if the

WP bit=0 in the DCR register, otherwise the RAM

location is not modified.

If the counter is pointing to the top of the structure,

it rolls over to the bottom since the incrementation

is performed only on the 7 or 8 LSB’s of the pointer

depending on the selected data structure size. In

other words, ALR rolls over from FFh to 00h for

Device Addresses A2h/A3h and A6h/A7h.

Otherwise, it rolls over from 7Fh to 00h or from FFh

to 80h depending on the MSB of the last data

address received.

Then after that last byte has been effectively

written in RAM, the EDF flag is set and an interrupt

is generated if EDE is set.

In any case, all write operations are performed

in RAM and therefore do not delay DDC

transfers, although concurrent software

execution is halted for 2 cycles.

The transfer is terminated by the master

generating a STOP condition.

Figure 65. Write sequence

Addr.

XXXXh

Pointer

ADDR

ADDR + 1

DATA IN 2

ADDR + n -1 ADDR + n

DEV ADDR

SDA

DATA ADDR.

DATA IN 1

DATA IN n

■ Read Operations

– Random address read: The master performs a

dummy write to load the data address into the

ALR. Then the master sends a RESTART condi-

tion followed by a read Device Address (RW=1).

All read operations consist of retrieving the data

pointed to by an internal address counter which is

initialized by a dummy write and incremented by

any read. The DDC1/2B Interface always waits for

an acknowledge during the 9th bit-time. If the

master does not pull the SDA line low during this

bit-time, the DDC1/2B Interface ends the transfer

and switches to a stand-by state.

– Sequential address read: This mode is similar

to the current and random address reads, except

that the master DOES acknowledge the data

byte for the DDC1/2B Interface to output the next

byte in sequence. To terminate the read opera-

tion the master must NOT acknowledge the last

data byte and must generate a STOP condition.

– Current address read: After generating a

START condition the master sends a read device

address (RW = 1). The DDC1/2B Interface ac-

knowledges this and outputs the data byte point-

ed to by the internal address pointer which is

subsequently incremented. The master must

NOT acknowledge this byte and must terminate

the transfer with a STOP condition.

The data output are from consecutive memory

addresses. The internal address counter is incre-

mented automatically after each byte. If the

counter is pointing to the top of the structure, it

rolls over to the bottom since the incrementation

is performed only on the 7 or 8 LSB’s of the

counter depending on the selected data structure

size.

105/144

ST72774/ST727754/ST72734

DDC INTERFACE (Cont’d)

Figure 66. Read sequences

CURRENT ADDRESS READ

Addr.

ADDR

Pointer

ADDR + 1

DEV ADDR

SDA

DATA OUT

RANDOM ADDRESS READ

Addr.

ADDR + 1

XXXXh

ADDR

Pointer

DEV ADDR

SDA

DATA ADDR.

DATA OUT

SEQUENTIAL ADDRESS READ

Addr.

ADDR

Pointer

ADDR + 1

ADDR + n -1

DATA OUT n

ADDR + n

DEV ADDR

SDA

DATA OUT 2

DATA OUT 1

106/144

ST72774/ST727754/ST72734

DDC INTERFACE (Cont’d)

2

4.8.5.2 DDC/CI - Factory Alignment Interface

4.8.5.2.2 I C Modes

■ General description

In I C mode, the interface can operate in the

4.8.5.2.1 Functional Description

Refer to the CR, SR1 and SR2 registers in Section

2

following modes:

4.8.6. for the bit definitions.

– Slave transmitter/receiver

Both start and stop conditions are generated by

the master. The I2C clock (SCL) is always

received by the interface from a master, but the

interface is able to stretch the clock line.

The DDC/CI interface works as an I/O interface

between the microcontroller and the DDC2Bi,

EDDC or Factory alignment protocols. It receives

and transmits data in Slave I C mode using an

interrupt or polled handshaking.

2

The interface is capable of recognizing both its

own programmable address (7-bit) and its default

hardware address (Enhanced DDC address: 60h/

61h). The Enhanced DDC address detection may

be enabled or disabled by software. It never

recognizes the Start byte (01h) whatever its own

address is.

The interface is connected to the I C bus by a data

pin (SDAD) and a clock pin (SCLD) configured as

open drain.

The DDC/CI interface has five internal register

locations.

Two of them are used for initialization of the

interface:

– Own Address Register OAR

■ Slave Mode

As soon as a start condition is detected, the

address is received from the SDA line and sent to

the shift register; then it is compared with the

programmable address of the interface or the

Enhanced DDC address (if selected by software).

– Control register CR

The following four registers are used during data

transmission/reception:

– Data Register DR

– Control Register CR

– Status Register 1 SR1

– Status Register 2 SR2

Address not matched: the interface ignores it

and waits for another Start condition.

2

The interface decodes an I C or DDC2Bi address

Address matched: the following events occur in

sequence:

stored by software in the OAR register and/or the

EDDC address (60h/61h) as its default hardware

address.

– Acknowledge pulse is generated if the ACK bit is

set.

After a reset, the interface is disabled.

– EVF and ADSL bits are set.

– An interrupt is generated if the ITE bit is set.

Then the interface waits for a read of the SR1

register, holding the SCL line low (see Figure 67

Transfer sequencing EV1).

Next, the DR register must be read to determine

from the least significant bit if the slave must enter

Receiver or Transmitter mode.

107/144

ST72774/ST727754/ST72734

DDC INTERFACE (Cont’d)

Slave Receiver

Then the interface waits for a read of the SR2

register (see Figure 67 Transfer sequencing EV4).

Following the address reception and after SR1

register has been read, the slave receives bytes

from the SDA line into the DR register via the

internal shift register. After each byte, the following

events occur in sequence:

Error Cases

– BERR: Detection of a Stop or a Start condition

during a byte transfer. In this case, the EVF and

the BERR bits are set and an interrupt is gener-

ated if the ITE bit is set.

If it is a Stop then the interface discards the data,

releases the lines and waits for another Start

condition.

– Acknowledge pulse is generated if the ACK bit is

set.

– EVF and BTF bits are set.

– An interrupt is generated if the ITE bit is set.

Then the interface waits for a read of the SR1

register followed by a read of the DR register,

holding the SCL line low (see Figure 67 Transfer

sequencing EV2).

If it is a Start then the interface discards the data

and waits for the next slave address on the bus.

– AF: Detection of a non-acknowledge bit. In this

case, the EVF and AF bits are set and an inter-

rupt is generated if the ITE bit is set.

Note:In both cases, SCL line is not held low; however,

SDA line can remain low due to possible «0» bits

transmitted last. It is then necessary to release both

lines by software.

Slave Transmitter

Following the address reception and after SR1

register has been read, the slave sends bytes from

the DR register to the SDA line via the internal shift

register.

How to release the SDA / SCL lines

Set and subsequently clear the STOP bit while

BTF is set. The SDA/SCL lines are released after

the transfer of the current byte.

The slave waits for a read of the SR1 register

followed by a write in the DR register, holding the

SCL line low (see Figure 67 Transfer sequencing

EV3).

Other Events

When the acknowledge pulse is received:

■ ADSL: Detection of a Start condition after an

acknowledge time-slot.

– EVF and BTF bits are set.

The state machine is reset and starts a new

process. The ADSL bit is set and an interrupt is

generated if the ITE bit is set. The SCL line is

stretched low.

– An interrupt is generated if the ITE bit is set.

Closing slave communication

■ STOPF: Detection of a Stop condition after an

acknowledge time-slot.

After the last data byte is transferred, a Stop

Condition is generated by the master. The

interface detects this condition and in this case:

The state machine is reset. Then the STOPF

flag is set and an interrupt is generated if the ITE

bit is set.

– EVF and STOPF bits are set.

– An interrupt is generated if the ITE bit is set.

108/144

ST72774/ST727754/ST72734

DDC INTERFACE (Cont’d)

Figure 67. Transfer Sequencing

Slave receiver:

S

Address

A

Data1

A

Data2

EV3

A

DataN

A

P

.....

EV1

EV2

A

EV2

A

EV2

NA

EV4

P

Slave transmitter:

S

Address

A

Data1

Data2

DataN

.....

EV1 EV3

EV3

EV4

Legend:

S=Start, P=Stop, A=Acknowledge, NA=Non-acknowledge

EVx=Event (with interrupt if ITE=1)

EV1: EVF=1, ADSL=1, cleared by reading SR1 register.

EV2: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register.

EV3: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register.

EV4: EVF=1, STOPF=1, cleared by reading SR2 register.

Figure 68. Event Flags and Interrupt Generation

ITE

BTF

ADSL

INTERRUPT

AF

STOPF

BERR

EVF

109/144

ST72774/ST727754/ST72734

DDC INTERFACE (Cont’d)

4.8.6 Register Description

Bit 3 = Reserved. Forced to 0 by hardware.

DDC CONTROL REGISTER (CR)

Read / Write

Bit 2 = ACK Acknowledge enable.

This bit is set and cleared by software. It is also

cleared by hardware when the interface is disabled

(PE=0).

Reset Value: 0000 0000 (00h)

7

0

EDDC

EN

0

PE

0

ACK STOP

ITE

0: No acknowledge returned

1: Acknowledge returned after an address byte or

a data byte is received

Bit 7:6 = Reserved. Forced to 0 by hardware.

Bit 1 = STOP Release I2C bus.

This bit is set and cleared by software or when the

interface is disabled (PE=0).

Bit 5 = PE Peripheral enable.

This bit is set and cleared by software.

– Slave Mode:

0: Nothing

0: Peripheral disabled

1: Slave capability

Notes:

1: Release the SCL and SDA lines after the cur-

rent byte transfer (BTF=1). The STOP bit has to

be cleared by software.

– When PE=0, all the bits of the CR register and

the SR register are reset. All outputs are re-

leased while PE=0

Bit 0 = ITE Interrupt enable.

This bit is set and cleared by software and cleared

by hardware when the interface is disabled

(PE=0).

– When PE=1, the corresponding I/O pins are se-

lected by hardware as alternate functions.

2

– To enable the I C interface, write the CR register

TWICE with PE=1 as the first write only activates

the interface (only PE is set).

0: Interrupts disabled

1: Interrupts enabled

Refer to Figure 68 for the relationship between the

events and the interrupt.

SCL is held low when the BTF or ADSL is detect-

ed.

Bit 4 = EDDCEN Enhanced DDC address

detection enabled.

This bit is set and cleared by software. It is also

cleared by hardware when the interface is disabled

(PE=0). The 60h/61h Enhanced DDC address is

acknowledged.

0: Enhanced DDC address detection disabled

1: Enhanced DDC address detection enabled

110/144

ST72774/ST727754/ST72734

DDC INTERFACE (Cont’d)

DDC STATUS REGISTER 1 (SR1)

Bit 4 = BUSY Bus busy.

This bit is set by hardware on detection of a Start

condition and cleared by hardware on detection of

a Stop condition. It indicates a communication in

progress on the bus. This information is still

updated when the interface is disabled (PE=0).

Read Only

Reset Value: 0000 0000 (00h)

7

0

0: No communication on the bus

EVF

0

TRA BUSY BTF ADSL

0

1: Communication ongoing on the bus

Bit 7 = EVF Event flag.

Bit 3 = BTF Byte transfer finished.

This bit is set by hardware as soon as an event

occurs. It is cleared by software reading SR2

register in case of error event or as described in

Figure 67. It is also cleared by hardware when the

interface is disabled (PE=0).

This bit is set by hardware as soon as a byte is

correctly received or transmitted with interrupt

generation if ITE=1. It is cleared by software

reading SR1 register followed by a read or write of

DR register. It is also cleared by hardware when

the interface is disabled (PE=0).

0: No event

1: One of the following events has occurred:

– Following a byte transmission, this bit is set after

reception of the acknowledge clock pulse. . BTF

is cleared by reading SR1 register followed by

writing the next byte in DR register.

– BTF=1 (Byte received or transmitted)

– ADSL=1 (Address matched in Slave mode

while ACK=1)

– Following a byte reception, this bit is set after

transmission of the acknowledge clock pulse if

ACK=1. BTF is cleared by reading SR1 register

followed by reading the byte from DR register.

The SCL line is held low while BTF=1.

– AF=1 (No acknowledge received after byte

transmission if ACK=1)

– STOPF=1 (Stop condition detected in Slave

mode)

0: Byte transfer not done

1: Byte transfer succeeded

– BERR=1 (Bus error, misplaced Start or Stop

condition detected)

Bit 2 = ADSL Address matched (Slave mode). This

bit is set by hardware as soon as the received

slave address matched with the OAR register

content or the Enhanced DDC address is

recognized. An interrupt is generated if ITE=1. It is

cleared by software reading SR1 register or by

hardware when the interface is disabled (PE=0).

Bit 6 = Reserved. Forced to 0 by hardware.

Bit 5 = TRA Transmitter/Receiver.

When BTF is set, TRA=1 if a data byte has been

transmitted. It is cleared automatically when BTF

is cleared. It is also cleared by hardware after

detection of Stop condition (STOPF=1) or when

the interface is disabled (PE=0).

The SCL line is held low while ADSL=1.

0: Data byte received (if BTF=1)

1: Data byte transmitted

0: Address mismatched or not received

1: Received address matched

Bit 1:0 = Reserved. Forced to 0 by hardware.

111/144

ST72774/ST727754/ST72734

DDC INTERFACE (Cont’d)

DDC STATUS REGISTER 2 (SR2)

Bit 1 = BERR Bus error.

Read Only

Reset Value: 0000 0000 (00h)

This bit is set by hardware when the interface

detects a misplaced Start or Stop condition. An

interrupt is generated if ITE=1. It is cleared by

software reading SR2 register or by hardware

when the interface is disabled (PE=0).

7

0

EDDC

F

0

AF STOPF

0

BERR

The SCL line is not held low while BERR=1.

0: No misplaced Start or Stop condition

1: Misplaced Start or Stop condition

Bit 7:5 = Reserved. Forced to 0 by hardware.

Bit 4 = AF Acknowledge failure.

Bit 0 = EDDCF Enhanced DDC address detected.

This bit is set by hardware when the Enhanced

DDC address (60h/61h) is detected on the bus

while EDDCEN=1. It is cleared by hardware when

a Start or a Stop condition (STOPF=1) is detected,

or when the interface is disabled (PE=0).

This bit is set by hardware when no acknowledge

is returned. An interrupt is generated if ITE=1. It is

cleared by software reading SR2 register or by

hardware when the interface is disabled (PE=0).

The SCL line is not held low while AF=1.

0: No Enhanced DDC address detected on bus

1: Enhanced DDC address detected on bus

0: No acknowledge failure

1: Acknowledge failure

Bit 3 = STOPF Stop detection.

This bit is set by hardware when a Stop condition is

detected on the bus after an acknowledge (if

ACK=1). An interrupt is generated if ITE=1. It is

cleared by software reading SR2 register or by

hardware when the interface is disabled (PE=0).

The SCL line is not held low while STOPF=1.

0: No Stop condition detected

1: Stop condition detected

Bit 2 = Reserved. Forced to 0 by hardware.

112/144

ST72774/ST727754/ST72734

DDC INTERFACE (Cont’d)

DDC DATA REGISTER (DR)

DDC OWN ADDRESS REGISTER (OAR)

Read / Write

Reset Value: 0000 0000 (00h)

7

0

7

0

D7

D6

D5

D4

D3

D2

D1

D0

ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0

Bit 7:0 = D7-D0 8-bit Data Register.

These bits contain the byte to be received or

transmitted on the bus.

Bit 7:1 = ADD7-ADD1 Interface address.

These bits define the I C bus programmable

address of the interface. They are not cleared

when the interface is disabled (PE=0).

2

– Transmitter mode: Byte transmission start auto-

matically when the software writes in the DR reg-

ister.

Bit 0 = ADD0.

This bit is Don’t Care, the interface acknowledges

either 0 or 1. It is not cleared when the interface is

disabled (PE=0).

– Receiver mode: the first data byte is received au-

tomatically in the DR register using the least sig-

nificant bit of the address.

Then, the next data bytes are received one by

one after reading the DR register.

Note: Address 01h is always ignored.

113/144

ST72774/ST727754/ST72734

DDC INTERFACE (Cont’d)

DDC1/2B CONTROL REGISTER (DCR)

Bit 1 = WP Write Protect.

Read / Write

This bit is set and cleared by software.

Reset Value: 0000 0000 (00h)

0: Enable writes to the RAM.

1: Disable DMA write transfers and protect the

RAM content. CPU writes to the RAM are not

affected.

7

0

CF2

EDF

EDE

CF1

CF0

WP HWPE

Bit 0= HWPE Peripheral Enable.

This bit is set and cleared by software.

Bit 7 = Reserved.

Forced by hardware to 0.

0: Release the SDA port pin and ignore Vsync

and SCL port pins. The other bits of the DCR

and the content of the AHR are left un-

changed.

1: Enable the DDC Interface and respond to the

DDC1/DDC2B protocol.

Bit 5 = EDF End of Download interrupt Flag.

This bit is set by hardware and cleared by

software.

0: Download not started or not completed yet.

1: Download completed. Last byte of data struc-

ture (relative address 7Fh or FFh) has been

stored in RAM.

ADDRESS POINTER HIGH REGISTER (AHR)

Read / Write

Reset Value: see Register Map

Bit 4 = EDE End of Download interrupt Enable.

7

0

This bit is set and cleared by software.

MSB

LSB

0: Interrupt disabled.

1: A DDC1/2B interrupt is generated if EDF bit is

set.

AHR contains the 8 MSB’s of the 16-bit address

pointer. It therefore defines the location of the 256-

byte block containing the data structure within the

CPU address space.

Bits 6, 3:2 = CF[2:0] Configuration bits.

These bits are set and cleared by software only

when the peripheral is disabled (HWPE = 0). They

define which EDID structure version is used and

which Device Addresses are recognized as shown

in the following table:

Note: AHR0 is ignored when CF[1:0] = 10 (P&D+ v2

mode) to allow non-overlapping 128-byte and 256-

byte data structures.

CF[2:0] Bit

Values

EDID version used

DDC v2

DDC1 Mode support / Transition Mode support

Yes (128b EDID) / Yes

DDC2B Addresses Recognized

128b-EDID

@A0h/A1h

000

256b-EDID

@ A2h/A3h

001

010

011

P&D

No

Yes (128b EDID) / Yes

No

128b-EDID

@A0h/A1h

v2 + P&D

256b-EDID

@ A2h/A3h

256b-EDID

@ A6h/A7h

FPDI-2

128b-EDID

@A0h/A1h

100

101

DDC v2

No

Reserved d sd

128b-EDID

@A0h/A1h

110

111

v2 + P&D

No

256b-EDID

@ A2h/A3h

Reserved d sd

114/144

ST72774/ST727754/ST72734

DDC INTERFACE (Cont’d)

Table 26. DDC Register Map and Reset Values

Address

(Hex.)

Register

Name

7

6

5

4

3

2

1

0

CR

PE

0

EDDCEN

0

ACK

0

STOP

0

ITE

0

50

51

52

54

56

Reset Value

0

SR1

EVF

0

TRA

0

BUSY

0

BTF

0

ADSL

0

Reset Value

0

SR2

AF

0

STOPF

0

BERR

0

EDDCF

0

Reset Value

0

OAR

ADD7

0

ADD6

0

ADD5

0

ADD4

0

ADD3

0

ADD2

0

ADD1

0

ADD0

0

Reset Value

DR

D7

0

D6

0

D5

0

D4

0

D3

0

D2

0

D1

0

D0

0

Reset Value

DCR

CF2

0

EDF

0

EDE

0

CF1

0

CF0

0

WP

0

HWPE

0

0C

0D

Reset Value

0

AHR

AHR7

0

AHR6

0

AHR5

0

AHR4

0

AHR3

0

AHR2

0

AHR1

0

AHR0

0

Reset Value

115/144

ST72774/ST727754/ST72734

4.9 PWM/BRM GENERATOR (DAC)

4.9.1 Introduction

PWM Generation

This PWM/BRM peripheral includes two types of

The counter increments continuously, clocked at

internal CPU clock. Whenever the 6 least

significant bits of the counter (defined as the PWM

counter) overflow, the output level for all active

channels is set.

PWM/BRM outputs, with differing step resolutions

based on the Pulse Width Modulator (PWM) and

Binary Rate Multiplier (BRM) Generator technique

are available. It allows the digital to analog

conversion (DAC) when used with external

filtering.

The state of the PWM counter is continuously

compared to the PWM binary weight for each

channel, as defined in the relevant PWM register,

and when a match occurs the output level for that

channel is reset.

4.9.2 Main Features

■ Fixed frequency: f

■ Resolution: T_CPU

/64

CPU

■ 10-Bit PWM/BRM generator with a step of

10

This Pulse Width modulated signal must be

filtered, using an external RC network placed as

close as possible to the associated pin. This

provides an analog voltage proportional to the

average charge passed to the external capacitor.

Thus for a higher mark/space ratio (High time

much greater than Low time) the average output

voltage is higher. The external components of the

RC network should be selected for the filtering

level required for control of the system variable.

V_DD/2 (5mV if V_DD=5V)

4.9.3 Functional Description

4.9.3.1 PWM/BRM

The 10 bits of the 10-bit PWM/BRM are distributed

as 6 PWM bits and 4 BRM bits. The generator

consists of a 12-bit counter (common for all

channels), a comparator and the PWM/BRM

generation logic.

Each output may individually have its polarity

inverted by software, and can also be used as a

logical output.

Figure 69. PWM Generation

COUNTER

OVERFLOW

63

OVERFLOW

COMPARE

VALUE

000

t

PWM OUTPUT

T_CPUx 64

116/144

ST72774/ST727754/ST72734

PWM/BRM Outputs (Cont’d)

PWM/BRM Outputs

The PWM/BRM outputs are assigned to dedicated

Table 27. 6-Bit PWM Ripple After Filtering

pins.

C

(µF)

V RIPPLE (mV)

ext

The RC filter time must be higher than TCPUx64.

0.128

1.28

12.8

78

7.8

Figure 70. Typical PWM Output Filter

0.78

OUTPUT

VOLTAGE

OUTPUT

STAGE

With RC filter (R=1KΩ),

f

= 8 MHz

= 5V

R

CPU

ext

C

ext

V

DD

PWM Duty Cycle 50%

R=Rext.

Figure 71. PWM Simplified Voltage Output After Filtering

V

DD

PWMOUT

0V

V

(mV)

V

ripple

V

DD

OUTPUT

VOLTAGE

OUTAVG

0V

"CHARGE"

"DISCHARGE"

"CHARGE"

"DISCHARGE"

V

DD

PWMOUT

0V

V

DD

V

(mV)

ripple

OUTPUT

VOLTAGE

0V

V

OUTAVG

VR01956

"CHARGE"

"DISCHARGE"

"CHARGE"

"DISCHARGE"

117/144

ST72774/ST727754/ST72734

PWM/BRM GENERATOR (Cont’d)

BRM Generation

Then 3.0 µs-long pulse will be output at 8 µs

intervals, except for cycles numbered

2,4,6,10,12,14, where the pulse is broadened to

The BRM bits allow the addition of a pulse to widen

a standard PWM pulse for specific PWM cycles.

This has the effect of “fine-tuning” the PWM Duty

cycle (without modifying the base duty cycle), thus,

with the external filtering, providing additional fine

voltage steps.

3.125 µs.

Note: If 00h is written to both PWM and BRM registers,

the generator output will remain at “0”. Conversely,

if both registers hold data 3Fh and 0Fh, respective-

ly, the output will remain at “1” for all intervals #1 to

#15, but it will return to zero at interval #0 for an

amount of time corresponding to the PWM resolu-

The incremental pulses (with duration of T

) are

CPU

tion (T

).

CPU

added to the beginning of the original PWM pulse.

The PWM intervals which are added to are

specified in the 4-bit BRM register and are

encoded as shown in the following table. The BRM

values shown may be combined together to

provide a summation of the incremental pulse

intervals specified.

An output can be set to a continuous “1” level by

clearing the PWM and BRM values and setting

POL = “1” (inverted polarity) in the PWM register.

This allows a PWM/BRM channel to be used as an

additional I/O pin if the DAC function is not

required.

The pulse increment corresponds to the PWM

resolution.

Table 28. Bit BRM Added Pulse Intervals

(Interval #0 not selected).

For example,if

BRM 4 - Bit Data

0000

Incremental Pulse Intervals

none

– Data 18h is written to the PWM register

0001

i = 8

– Data 06h (00000110b) is written to the BRM reg-

ister

0010

i = 4,12

0100

i = 2,6,10,14

i = 1,3,5,7,9,11,13,15

– with a 8MHz internal clock (125ns resolution)

1000

Figure 72. BRM pulse addition (PWM > 0)

m = 15

m = 0

m = 1

m = 2

T_CPUx 64

T_CPUx 64 increment

118/144

ST72774/ST727754/ST72734

PWM/BRM GENERATOR (Cont’d)

Figure 73. Simplified Filtered Voltage Output Schematic with BRM added

=

VDD

PWMOUT

0V

VDD

BRM = 1

BRM = 0

OUTPUT

VOLTAGE

0V

T_CPU

BRM

EXTENDED PULSE

Figure 74. Graphical Representation of 4-Bit BRM Added Pulse Positions

PWM Pulse Number (0-15)

BRM VALUE

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

0001 bit0=1

0100 bit2=1

Examples

0110

1111

119/144

ST72774/ST727754/ST72734

PWM/BRM GENERATOR (Cont’d)

4.9.3.2 PWM/BRM OUTPUTS

The PWM/BRM outputs are assigned to dedicated

pins.

If necessary, these pins can be used in push-pull

or open-drain modes under software control.

In these pins, the PWM/BRM outputs are

connected to a serial resistor which must be taken

into account to calculate the RC filter.

Figure 75. Precision for PWM/BRM Tuning for VOUTEFF (After filtering)

0

V

DD

1

2

3

4

60

61

15

62

63

64

0F

STEPS

V

6 - Bit

PWM

DD

each

64

each

4 - Bit

BRM

1

5

10

V

1024

DD

16 sub steps of

or

6 - Bit

BRM

1

10

20

40

50

63

V

4096

DD

sub steps of

64

120/144

ST72774/ST727754/ST72734

PWM/BRM GENERATOR (Cont’d)

4.9.4 Register Description

BRM REGISTERS

4.9.4.1 PWM/BRM REGISTERS

On a channel basis, the 10 bits are separated into

two data registers:

BRM21 (Channels 2 + 1)

BRM43 (Channels 4 + 3)

BRM65 (Channels 6 + 5)

BRM87 (Channels 8 + 7)

– A 6-bit PWM register corresponding to the binary

weight of the PWM pulse.

– A 4-bit BRM register defining the intervals where

an incremental pulse is added to the beginning of

the original PWM pulse. Two BRM channel val-

ues share the same register.

Read/Write

Reset Value: 0000 0000 (00h)

7

0

Note: The number of PWM and BRM channels available

depends on the device. Refer to the device pin de-

scription and register map.

B7

B6

B5

B4

B3

B2

B1

B0

Bits 7:4 = B[7:4] BRM Bits (channel i+1)

Bits 3:0 = B[3:0] BRM Bits (channel i)

PWM[1:8] REGISTERS

Read/Write

Reset Value 1000 0000 (80h)

4.9.4.2 OUTPUT ENABLE REGISTER

Read/Write

Reset Value 1000 0000 (80h)

7

1

0

7

0

POL

P5

P4

P3

P2

P1

P0

OE7

OE6

OE5

OE4

OE3

OE2

OE1

OE0

Bit 7 = Reserved (read as “1”)

Bit 7:0 = OE[7:0] Output Enable Bit.

Bit 6 = POL Polarity Bit.

When OEi is set, PWM output function is enabled.

When POL is set, output signal polarity is inverse;

otherwise, no change occurs.

0: PWM output is disabled

1: PWM output is enabled

Bits 5:0 = P[5:0] PWM Pulse Binary Weight for

channel i .

Note: From the programmer’s point of view, the PWM and

BRM registers can be regarded as being combined

to give one data value.

For example (10-bit)

0

POL

P

+

B

Effective (with external RC filtering) DAC value

0

POL

P

B

121/144

ST72774/ST727754/ST72734

Table 29. PWM Register Map

Address

(Hex.)

Register

Name

7

6

5

4

3

2

1

0

32

33

34

35

36

37

38

39

3A

3B

3C

3D

3E

PWM1

BRM21

PWM2

PWM3

BRM43

PWM4

PWM5

BRM65

PWM6

PWM7

BRM87

PWM8

PWMCR

POL

P5 ..P0

BRM Channel 2

POL

BRM Channel 1

BRM Channel 3

BRM Channel 5

BRM Channel 7

P5 ..P0

POL

BRM Channel 4

POL

P5 ..P0

POL

BRM Channel 6

POL

P5 ..P0

POL

BRM Channel 8

POL

P5 ..P0

OE7 ..OE0

122/144

ST72774/ST727754/ST72734

4.10 8-BIT A/D CONVERTER (ADC)

4.10.1 Introduction

The on-chip Analog to Digital Converter (ADC)

4.10.3 Functional Description

4.10.3.1 Analog Power Supply

and V are the high and low level

reference voltage pins. In some devices (refer to

device pin out description) they are internally

peripheral is a 8-bit, successive approximation

converter with internal sample and hold circuitry.

This peripheral has up to 16 multiplexed analog

input channels (refer to device pin out description)

that allow the peripheral to convert the analog

voltage levels from up to 16 different sources.

V

DDA

SSA

connected to the V and V pins.

DD

SS

Conversion accuracy may therefore be impacted

by voltage drops and noise in the event of heavily

loaded or badly decoupled power supply lines.

The result of the conversion is stored in a 8-bit

Data Register. The A/D converter is controlled

through a Control/Status Register.

See electrical characteristics section for more

details.

4.10.2 Main Features

■ 8-bit conversion

■ Up to 16 channels with multiplexed input

■ Linear successive approximation

■ Data register (DR) which contains the results

■ Conversion complete status flag

■ On/off bit (to reduce consumption)

The block diagram is shown in Figure 76.

Figure 76. ADC Block Diagram

f

ADC

CPU

DIV 4

COCO

0

ADON

4

0

CH3 CH2 CH1 CH0

ADCCSR

AIN0

AIN1

HOLD CONTROL

R

ADC

ANALOG TO DIGITAL

CONVERTER

ANALOG

MUX

AINx

C

ADC

ADCDR

D7

D6

D5

D4

D3

D2

D1

D0

123/144

ST72774/ST727754/ST72734

4.10.3.2 Digital A/D Conversion Result

ADC Configuration

The total duration of the A/D conversion is 12 ADC

The conversion is monotonic, meaning that the

result never decreases if the analog input does not

and never increases if the analog input does not.

clock periods (1/f

=4/f

).

ADC

CPU

The analog input ports must be configured as

input, no pull-up, no interrupt. Refer to the «I/O

ports» chapter. Using these pins as analog inputs

does not affect the ability of the port to be read as

a logic input.

If the input voltage (V ) is greater than or equal

AIN

to V

(high-level voltage reference) then the

DDA

conversion result in the DR register is FFh (full

scale) without overflow indication.

In the CSR register:

If input voltage (V ) is lower than or equal to

AIN

V

(low-level voltage reference) then the

SSA

– Select the CH[3:0] bits to assign the analog

channel to be converted.

conversion result in the DR register is 00h.

The A/D converter is linear and the digital result of

the conversion is stored in the ADCDR register.

The accuracy of the conversion is described in the

parametric section.

ADC Conversion

In the CSR register:

– Set the ADON bit to enable the A/D converter

and to start the first conversion. From this time

on, the ADC performs a continuous conver-

sion of the selected channel.

R

is the maximum recommended impedance

AIN

for an analog input signal. If the impedance is too

high, this will result in a loss of accuracy due to

leakage and sampling not being completed in the

alloted time.

When a conversion is complete

– The COCO bit is set by hardware.

– No interrupt is generated.

4.10.3.3 A/D Conversion Phases

The A/D conversion is based on two conversion

phases as shown in Figure 77:

– The result is in the DR register and remains

valid until the next conversion has ended.

A write to the CSR register (with ADON set) aborts

the current conversion, resets the COCO bit and

starts a new conversion.

■ Sample capacitor loading [duration: t

]

LOAD

During this phase, the V

input voltage to be

AIN

measured is loaded into the C

capacitor.

sample

ADC

Figure 77. ADC Conversion Timings

■ A/D conversion [duration: t

]

CONV

During this phase, the A/D conversion is

ADON

ADCCSR WRITE

OPERATION

t

computed (8 successive approximations cycles)

CONV

and the C

sample capacitor is disconnected

ADC

from the analog input pin to get the optimum

analog to digital conversion accuracy.

While the ADC is on, these two phases are

continuously repeated.

HOLD

CONTROL

t

LOAD

COCO BIT SET

At the end of each conversion, the sample

capacitor is kept loaded with the previous

measurement load. The advantage of this

behaviour is that it minimizes the current

consumption on the analog pin in case of single

input channel measurement.

4.10.4 Low Power Mode

Mode

WAIT

Description

No effect on A/D Converter

4.10.3.4 Software Procedure

Note: The A/D converter is disabled by resetting the

ADON bit. With this feature, power consumption is

reduced when no conversion is needed and be-

tween single shot conversions.

Refer to the control/status register (CSR) and data

register (DR) in Section 4.10.6 for the bit

definitions and to Figure 77 for the timings.

4.10.5 Interrupts

None

124/144

ST72774/ST727754/ST72734

8-BIT A/D CONVERTER (ADC) (Cont’d)

4.10.6 Register Description

CONTROL/STATUS REGISTER (CSR)

Channel Pin*

CH3 CH2 CH1 CH0

Read/Write

AIN0

AIN1

AIN2

AIN3

AIN4

AIN5

AIN6

AIN7

AIN8

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Reset Value: 0000 0000 (00h)

7

0

COCO

0

ADON

0

CH3

CH2

CH1

CH0

Bit 7 = COCO Conversion Complete

This bit is set by hardware. It is cleared by software

reading the result in the DR register or writing to

the CSR register.

AIN9

AIN10

AIN11

AIN12

AIN13

AIN14

AIN15

0: Conversion is not complete

1: Conversion can be read from the DR register

Bit 6 = Reserved. must always be cleared.

DATA REGISTER (DR)

Read Only

Bit 5 = ADON A/D Converter On

This bit is set and cleared by software.

Reset Value: 0000 0000 (00h)

0: A/D converter is switched off

1: A/D converter is switched on

7

0

Bit 4 = Reserved. must always be cleared.

D7

D6

D5

D4

D3

D2

D1

D0

Bit 3:0 = CH[3:0] Channel Selection

Bit 7:0 = D[7:0] Analog Converted Value

This register contains the converted analog value

in the range 00h to FFh.

These bits are set and cleared by software. They

select the analog input to convert.

Note: The number of pins AND the channel selection var-

ies according to the device. Refer to the device

pinout.

Note: Reading this register reset the COCO flag.

Table 30. ADC Register Map

Address

(Hex.)

Register

Name

7

6

5

4

3

2

1

0

D3

0

ADCDR

Reset Value

D7

0

D6

0

D5

0

D4

0

D2

0

D1

0

D0

0

0A

0B

COCO

0

-

ADON

0

-

CH3

0

CH2

0

CH1

0

CH0

0

ADCCSR

Reset Value

0

125/144

ST72774/ST727754/ST72734

5 INSTRUCTION SET

5.1 ST7 ADDRESSING MODES

so, most of the addressing modes may be

subdivided in two sub-modes called long and

short:

The ST7 Core features 17 different addressing

modes which can be classified in 7 main groups:

– Long addressing mode is more powerful be-

cause it can use the full 64 Kbyte address space,

however it uses more bytes and more CPU cy-

cles.

Addressing Mode

Inherent

Example

nop

Immediate

Direct

ld A,#$55

ld A,$55

– Short addressing mode is less powerful because

it can generally only access page zero (0000h -

00FFh range), but the instruction size is more

compact, and faster. All memory to memory in-

structions use short addressing modes only

(CLR, CPL, NEG, BSET, BRES, BTJT, BTJF,

INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP)

The ST7 Assembler optimizes the use of long and

Indexed

ld A,($55,X)

ld A,([$55],X)

jrne loop

Indirect

Relative

Bit operation

bset byte,#5

The ST7 Instruction set is designed to minimize

the number of bytes required per instruction: To do

short addressing modes.

Table 31. ST7 Addressing Mode Overview

Pointer

Address

(Hex.)

Pointer

Size

(Hex.)

Destination/

Source

Length

(Bytes)

Mode

Syntax

Inherent

Immediate

Short

nop

+ 0

+ 1

+ 2

ld A,#$55

ld A,$10

Direct

00..FF

Long

ld A,$1000

0000..FFFF

+ 0 (with X register)

+ 1 (with Y register)

No Offset

Direct

Indexed

ld A,(X)

00..FF

Short

Long

Short

Long

Short

Long

Relative

Bit

Direct

Indexed

ld A,($10,X)

ld A,($1000,X)

ld A,[$10]

00..1FE

+ 1

+ 2

+ 1

+ 2

+ 1

+ 2

+ 3

Direct

0000..FFFF

00..FF

Indirect

Direct

00..FF

byte

word

byte

word

ld A,[$10.w]

ld A,([$10],X)

0000..FFFF

00..1FE

Indexed

ld A,([$10.w],X) 0000..FFFF

1)

jrne loop

PC-128/PC+127

Indirect

Direct

jrne [$10]

PC-128/PC+127

00..FF

byte

bset $10,#7

bset [$10],#7

Bit

Indirect

Direct

00..FF

Bit

Relative btjt $10,#7,skip 00..FF

Relative btjt [$10],#7,skip 00..FF

Bit

Indirect

Note 1. At the time the instruction is executed, the Program Counter (PC) points to the instruction following

JRxx.

126/144

6

ST72774/ST727754/ST72734

ST7 ADDRESSING MODES (Cont’d)

5.1.1 Inherent

All Inherent instructions consist of a single byte.

5.1.3 Direct

In Direct instructions, the operands are referenced

The opcode fully specifies all the required

information for the CPU to process the operation.

by their memory address.

The direct addressing mode consists of two sub-

modes:

Inherent Instruction

Function

No operation

NOP

Direct (short)

The address is a byte, thus requires only one byte

TRAP

S/W Interrupt

after the opcode, but only allows 00 - FF

addressing space.

Wait For Interrupt (Low Power

Mode)

WFI

HALT

RET

Disabled, forces a RESET

Sub-routine Return

Interrupt Sub-routine Return

Set Interrupt Mask

Reset Interrupt Mask

Set Carry Flag

Direct (long)

The address is a word, thus allowing 64 Kbyte

addressing space, but requires 2 bytes after the

opcode.

IRET

SIM

RIM

5.1.4 Indexed (No Offset, Short, Long)

In this mode, the operand is referenced by its

memory address, which is defined by the unsigned

addition of an index register (X or Y) with an offset.

SCF

RCF

Reset Carry Flag

RSP

Reset Stack Pointer

Load

LD

The indirect addressing mode consists of three

sub-modes:

CLR

Clear

PUSH/POP

INC/DEC

TNZ

Push/Pop to/from the stack

Increment/Decrement

Test Negative or Zero

1 or 2 Complement

Byte Multiplication

Indexed (No Offset)

There is no offset, (no extra byte after the opcode),

and allows 00 - FF addressing space.

CPL, NEG

MUL

Indexed (Short)

The offset is a byte, thus requires only one byte

SLL, SRL, SRA, RLC,

RRC

after the opcode and allows 00 - 1FE addressing

space.

Shift and Rotate Operations

Swap Nibbles

SWAP

Indexed (long)

The offset is a word, thus allowing 64 Kbyte

addressing space and requires 2 bytes after the

opcode.

5.1.2 Immediate

Immediate instructions have two bytes, the first

byte contains the opcode, the second byte

contains the operand value.

5.1.5 Indirect (Short, Long)

Immediate Instruction

Function

The required data byte to do the operation is found

by its memory address, located in memory

(pointer).

LD

Load

CP

Compare

BCP

Bit Compare

The pointer address follows the opcode. The

indirect addressing mode consists of two sub-

modes:

AND, OR, XOR

ADC, ADD, SUB, SBC

Logical Operations

Arithmetic Operations

Indirect (short)

The pointer address is a byte, the pointer size is a

byte, thus allowing 00 - FF addressing space, and

requires 1 byte after the opcode.

Indirect (long)

127/144

ST72774/ST727754/ST72734

The pointer address is a byte, the pointer size is a

word, thus allowing 64 Kbyte addressing space,

and requires 1 byte after the opcode.

Short Instructions Only

CLR

Function

Clear

INC, DEC

Increment/Decrement

Test Negative or Zero

1 or 2 Complement

Bit Operations

5.1.6 Indirect Indexed (Short, Long)

This is a combination of indirect and short indexed

TNZ

addressing modes. The operand is referenced by

its memory address, which is defined by the

unsigned addition of an index register value (X or

Y) with a pointer value located in memory. The

pointer address follows the opcode.

CPL, NEG

BSET, BRES

Bit Test and Jump Opera-

tions

BTJT, BTJF

SLL, SRL, SRA, RLC,

RRC

Shift and Rotate Operations

The indirect indexed addressing mode consists of

two sub-modes:

SWAP

Swap Nibbles

CALL, JP

Call or Jump subroutine

Indirect Indexed (Short)

The pointer address is a byte, the pointer size is a

byte, thus allowing 00 - 1FE addressing space,

and requires 1 byte after the opcode.

5.1.7 Relative mode (Direct, Indirect)

This addressing mode is used to modify the PC

register value, by adding an 8-bit signed offset to it.

Available Relative Direct/

Function

Indirect Instructions

Indirect Indexed (Long)

The pointer address is a byte, the pointer size is a

word, thus allowing 64 Kbyte addressing space,

and requires 1 byte after the opcode.

JRxx

Conditional Jump

Call Relative

CALLR

Table 32. Instructions Supporting Direct,

Indexed, Indirect and Indirect Indexed

Addressing Modes

The relative addressing mode consists of two sub-

modes:

Long and Short

Function

Relative (Direct)

The offset follows the opcode.

Instructions

LD

Load

Relative (Indirect)

CP

Compare

The offset is defined in memory, of which the ad-

dress follows the opcode.

AND, OR, XOR

Logical Operations

Arithmetic Addition/subtrac-

tion operations

ADC, ADD, SUB, SBC

BCP

Bit Compare

128/144

ST72774/ST727754/ST72734

5.2 INSTRUCTION GROUPS

The ST7 family devices use an Instruction Set

consisting of 63 instructions. The instructions may

be subdivided into 13 main groups as illustrated in

the following table:

Load and Transfer

LD

CLR

POP

DEC

TNZ

OR

Stack operation

PUSH

INC

RSP

BCP

Increment/Decrement

Compare and Tests

Logical operations

CP

AND

BSET

BTJT

ADC

SLL

XOR

CPL

NEG

Bit Operation

BRES

BTJF

ADD

SRL

JRT

Conditional Bit Test and Branch

Arithmetic operations

Shift and Rotates

SUB

SRA

JRF

SBC

RLC

JP

MUL

RRC

CALL

SWAP

CALLR

SLA

Unconditional Jump or Call

Conditional Branch

JRA

JRxx

TRAP

SIM

NOP

RET

Interruption management

Code Condition Flag modification

WFI

RIM

IRET

SCF

RCF

Using a pre-byte

The instructions are described with one to four

bytes.

These prebytes enable instruction in Y as well as

indirect addressing modes to be implemented.

They precede the opcode of the instruction in X or

the instruction using direct addressing mode. The

prebytes are:

In order to extend the number of available opcodes

for an 8-bit CPU (256 opcodes), three different

prebyte opcodes are defined. These prebytes

modify the meaning of the instruction they

precede.

PDY 90

Replace an X based instruction

using immediate, direct, indexed, or inherent ad-

dressing mode by a Y one.

The whole instruction becomes:

PIX 92

Replace an instruction using di-

rect, direct bit, or direct relative addressing mode

to an instruction using the corresponding indirect

addressing mode.

It also changes an instruction using X indexed ad-

dressing mode to an instruction using indirect X in-

dexed addressing mode.

PC-2

PC-1

PC

End of previous instruction

Prebyte

opcode

PC+1

Additional word (0 to 2) according

to the number of bytes required to compute the ef-

fective address

PIY 91

Replace an instruction using X in-

direct indexed addressing mode by a Y one.

129/144

ST72774/ST727754/ST72734

INSTRUCTION GROUPS (Cont’d)

Mnemo

ADC

ADD

AND

BCP

Description

Add with Carry

Function/Example

A = A + M + C

A = A + M

Dst

Src

H

I

N

Z

C

A

M

Addition

A

Logical And

A = A . M

A

Bit compare A, Memory

Bit Reset

tst (A . M)

A

BRES

BSET

BTJF

BTJT

CALL

CALLR

CLR

bres Byte, #3

bset Byte, #3

btjf Byte, #3, Jmp1

btjt Byte, #3, Jmp1

M

Bit Set

Jump if bit is false (0)

Jump if bit is true (1)

Call subroutine

Call subroutine relative

Clear

C

reg, M

reg

0

1

Z

CP

Arithmetic Compare

One Complement

Decrement

tst(Reg - M)

A = FFH-A

dec Y

M

N

C

1

CPL

reg, M

DEC

IRET

INC

Interrupt routine return

Increment

Pop CC, A, X, PC

inc X

H

I

C

reg, M

JP

Absolute Jump

Jump relative always

Jump relative

jp [TBL.w]

JRA

JRT

JRF

Never jump

jrf *

JRIH

JRIL

Jump if ext. interrupt = 1

Jump if ext. interrupt = 0

Jump if H = 1

JRH

H = 1 ?

JRNH

JRM

Jump if H = 0

H = 0 ?

Jump if I = 1

I = 1 ?

JRNM

JRMI

JRPL

JREQ

JRNE

JRC

Jump if I = 0

I = 0 ?

Jump if N = 1 (minus)

Jump if N = 0 (plus)

Jump if Z = 1 (equal)

Jump if Z = 0 (not equal)

Jump if C = 1

N = 1 ?

N = 0 ?

Z = 1 ?

Z = 0 ?

C = 1 ?

JRNC

JRULT

Jump if C = 0

C = 0 ?

Jump if C = 1

Unsigned <

Jmp if unsigned >=

Unsigned >

JRUGE Jump if C = 0

JRUGT Jump if (C + Z = 0)

130/144

ST72774/ST727754/ST72734

INSTRUCTION GROUPS (Cont’d)

Mnemo

JRULE

LD

Description

Jump if (C + Z = 1)

Load

Function/Example

Unsigned <=

dst <= src

Dst

Src

H

I

N

Z

C

reg, M

A, X, Y

reg, M

M, reg

X, Y, A

MUL

NEG

NOP

OR

Multiply

X,A = X * A

0

Negate (2’s compl)

No Operation

OR operation

Pop from the Stack

neg $10

C

A = A + M

pop reg

pop CC

push Y

C = 0

A

M

POP

reg

CC

M

H

I

C

0

PUSH

RCF

RET

RIM

Push onto the Stack

Reset carry flag

Subroutine Return

Enable Interrupts

Rotate left true C

Rotate right true C

Reset Stack Pointer

Subtract with Carry

Set carry flag

reg, CC

I = 0

0

RLC

RRC

RSP

SBC

SCF

SIM

C <= Dst <= C

C => Dst => C

S = Max allowed

A = A - M - C

C = 1

reg, M

N

Z

C

A

M

N

Z

C

1

Disable Interrupts

Shift left Arithmetic

Shift left Logic

I = 1

1

SLA

C <= Dst <= 0

0 => Dst => C

Dst7 => Dst => C

A = A - M

reg, M

A

N

0

Z

C

SLL

SRL

SRA

SUB

SWAP

TNZ

TRAP

WFI

Shift right Logic

Shift right Arithmetic

Subtraction

N

M

SWAP nibbles

Dst[7..4] <=> Dst[3..0] reg, M

tnz lbl1

Test for Neg & Zero

S/W trap

S/W interrupt

1

0

Wait for Interrupt

Exclusive OR

XOR

A = A XOR M

A

M

N

Z

131/144

ST72774/ST727754/ST72734

6 ELECTRICAL CHARACTERISTICS

The ST727x4 device contains circuitry to protect

the inputs against damage due to high static

voltage or electric field. Nevertheless it is advised

to take normal precautions and to avoid applying to

this high impedance voltage circuit any voltage

higher than the maximum rated voltages. It is

To enhance reliability of operation, it is

recommended to connect unused inputs to an

appropriate logic voltage level such as V or V

.

SS

DD

All the voltages in the following table, are

referenced to V

.

SS

recommended for proper operation that V and

IN

V

be constrained to the range:

OUT

V

≤ (V or V

) ≤ V

DD

SS

IN

OUT

Table 33. Absolute Maximum Ratings

Symbol

Ratings

Recommended Supply Voltage

Input Voltage

Value

Unit

V

-0.3 to +6.0

DD

V

-0.3 to V + 0.3

V

IN

SS

DD

V

Analog Input Voltage (A/D Converter)

Output Voltage

-0.3 to V + 0.3

V

AIN

DD

V

-0.3 to V + 0.3

V

OUT

DD

I

Input Current

-10......+10

mA

IN

I

Output Current

OUT

Accumulated injected current of all I/O pins (V

,

DD

I

40

mA

INJ

V

)

SS

T

Operating Temperature Range

Storage Temperature Range

Junction Temperature

Power Dissipation

0 to +70

-65 to +150

150

°C

mW

V

A

T

STG

T_J

PD

TBD

ESD

ESD susceptibility

2000

132/144

7

ST72774/ST727754/ST72734

6.1 POWER CONSIDERATIONS

The average chip-junction temperature, T , in

An approximate relationship between P and T

D J

J

degrees Celsius, may be calculated using the

following equation:

(if P is neglected) is given by:

I/O

P = K÷ (T + 273°C) (2)

D

J

T = T + (P x θJ ) (1)

J

A

D

A

Therefore:

Where:

– T is the Ambient Temperature in °C,

2

A

K = P x (T + 273°C) + θJ x P

D

(3)

D

A

– θJ is the Package Junction-to-Ambient Thermal

A

Resistance, in °C/W,

– P is the sum of P

and P

,

I/O

Where:

D

INT

– P

is the product of I

V

, expressed in

INT

DD and DD

Watts. This is the Chip Internal Power

– K is a constant for the particular part, which may

be determined from equation (3) by measuring

– P represents the Power Dissipation on Input

I/O

and Output Pins; User Determined.

P

(at equilibrium) for a known T Using this

D

A.

For most applications P <P

and may be

I/O

INT

value of K, the values of P and T may be ob-

tained by solving equations (1) and (2) iteratively

D

J

neglected. P may be significant if the device is

I/O

configured to drive Darlington bases or sink LED

Loads.

for any value of T .

A

Table 34. Thermal Characteristics

Symbol

Package

PSDIP42

TQFP44

Value

95

Unit

°C/W

θJ

A

95

133/144

ST72774/ST727754/ST72734

6.2 AC/DC ELECTRICAL CHARACTERISTICS

(T_A= 0 to +70°C unless otherwise specified)

GENERAL

Conditions

Symbol

Parameter

Operating Supply Voltage

CPU RUN mode

Min

Typ.

5

Max

5.5

18

Unit

V

RUN & WAIT mode

I/O in input mode

4.0

DD

14

12

mA

CPU WAIT mode

18

V

= 5V

DD

I

DD

f

= 8 MHz,

CPU HALT mode (see Note 1)

USB Suspend mode (see Note 2)

N/A

CPU

°

T = 20 C

A

Note 1: HALT mode no longer exists.

Note 2: The USB cell must be put in suspend mode as well as the MCU in HALT mode. Since the latter no longer exists

for enhanced arcing protection, the measurement of the USB suspend consumption parameter is no longer relevant.

CONTROL TIMING

Value

Symbol

Parameter

Conditions

Unit

Min

Typ.

Max

Frequency of Operation:

external frequency

f_OSC

24

8

MHz

f

internal frequency

f_OSC= 24MHz

f_OSC=12MHz

CPU

internal frequency

4

t_BU

t_RL

t_PORL

t_POWL

t_DOG

t_ILIL

Startup Time Built-Up Time

External RESET

Crystal Resonator

8

20

ms

ns

1000

4096

500

Input pulse Width

Internal Power Reset Duration

Watchdog RESET

t_CPU

ns

Output Pulse Width

49152

6

3145728

384

t_CPU

ms

Watchdog Time-out

f_CPU= 8 MHz

Interrupt Pulse Period

(1)

t_CPU

Crystal Oscillator

Start-up Time

t

50

ms

OXOV

t_DDR

Power up rise time

V

min

1

100

DD

Note: : The minimum period t_ILILshould not be less than the number of cycle times it takes to execute the interrupt service

routine plus 21 cycles.

134/144

ST72774/ST727754/ST72734

AC/DC ELECTRICAL CHARACTERISTICS (Cont’d)

STANDARD I/O PORT PINS

Conditions

Symbol

Parameter

Min

Typ

Max

Unit

Output Low Level Voltage

Port A[7,2:0], Port B[7:4],

Port C[7:0], Port D[6:0]

Push Pull

V

I

= -1.6mA V =5V

-

0.4

V

OL

DD

Output Low Level Voltage Port A[6:3]

Open Drain

V

I

= -1.6mA V =5V

-

0.4

1.5

0.4

V

OL

DD

Output Low Level Voltage

Port A and Port C

I

= -10mA V =5V

DD

OL

Output Low Level Voltage Port B[3:0]

Open Drain

I

= -3mA V =5V

DD

OL

Output High Level Voltage

Port A[7, 2:0], Port B[7:4],

Port C [7:0], Port D [6:0]

Push Pull

V

I

= 1.6mA

V -0.8

DD

-

V

OH

Input High Level Voltage Port A [7:0],

Port B [7:0], Port C [7:0], Port D[6:0],

RESET

V

Leading Edge

0.7xV

2.0

V

DD

IH

DD

HSYNC,VSYNCI, CSYNCI, HFBACK,

VFBACK

V

= 5V

V

IH

DD

HSYNC,VSYNCI, CSYNCI, HFBACK,

VFBACK

V

0.8

IL

DD

Input Low Voltage Port A [7:0],

Trailing Edge

V

0.3xV

V

Port B[7:0], Port C[7:0], Port D [6:0],

RESET

SS

DD

I/O Ports Hi-Z Leakage Current

Port A [7:0], Port B[7:0], Port C[7:0],

Port D [6:0], RESET

I

10

µA

IL

C

12

8

pF

Capacitance: Ports (as Input or

Output), RESET

OUT

C

IN

IRPU

Pull-up resistor current

V

=5V V =V T=25°C

280

µA

DD

IN

SS

Note: Note: All voltages are referred to V unless otherwise specified.

SS

POWER ON/OFF Electrical Specifications

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Power ON/OFF Reset Trigger

V

Variation 50mV/mS

3.35

3.1

3.65

3.9

V

TRH

DD

V

rising edge

DD

Power ON/OFF Reset Trigger

falling edge

V

Variation 50mV/mS

3.4

3.7

2.2

V

TRL

V

DD

V

minimum for Power ON/OFF Reset

active

DD

V

Variation 50mV/mS

2.0

TRM

DD

V

Power ON/OFF LVD Hysteresis

250

mV

TRHyst

DD

135/144

ST72774/ST727754/ST72734

AC/DC ELECTRICAL CHARACTERISTICS (Cont’d)

8-bit A/D Converter

Symbol

Parameter

Conditions

=5V

DD

Min

Typ

Max

Unit

f

Analog control frequency

Total unadjusted error

Offset error

V

2

MHz

ADC

|TUE|

OE

-1

1

f

V

_CPU=8MHz, f_ADC=2MHz

GE

Gain error

1

LSB

=5V

DD

|DLE|

|ILE|

Differential linearity error

Integral linearity error

Conversion range voltage

A/D conversion supply current

Stabilization time after enable ADC

0.5

V

mA

µs

AIN

ADC

STAB

SS

DD

I

t

1

f

V

_CPU=8MHz, f_ADC=2MHz

1

4

µs

t

Sample capacitor loading time

Conversion time

LOAD

CONV

=5V

1/f

DD

ADC

2

8

µs

t

1/f

ADC

R

C

External input resistor

Internal input resistor

Sample capacitor

15

kΩ

AIN

1.5

6

kΩ

ADC

pF

SAMPLE

PWM/BRM Electrical and Timings

Symbol

Parameter

Repetition rate

Conditions

Min

Typ

125

Max

Unit

T

=125ns

kHz

F

CPU

Res

Resolution

Output step

T

125

5

ns

CPU

s

V

=5V, 10 bits

mV

DD

136/144

ST72774/ST727754/ST72734

AC/DC ELECTRICAL CHARACTERISTICS (Cont’d)

I2C/DDC-Bus Electrical specifications

Standard mode I2C

Min Max

Fast mode I2C

Parameter

Symbol

Unit

Min

Max

Hysteresis of Schmitt trigger inputs

Fixed input levels

V

na

0.2

HYS

SP

V

-related input levels

na

0,05 V

DD

Pulse width of spikes which must be sup-

pressed by the input filter

T

I

ns

na

0 ns

50 ns

250

Output fall time from VIH min to VIL max with

a bus capacitance from 10 pF to 400 pF

20+0.1C

b

OF

with up to 3 mA sink current at VOL1

with up to 6 mA sink current at VOL2

250

na

20+0.1C 250

b

Input current each I/O pin with an input voltage

µA

- 10

10

-10

10

between 0.4V and 0.9 V max

DD

Capacitance for each I/O pin

C

pF

na = not applicable

Cb = capacitance of one bus in pF

I2C/DDC-Bus Timings

Standard I2C

Fast I2C

Parameter

Symbol

Unit

ms

Min

Max

Min

Max

Bus free time between a STOP and START con-

dition

4.7

1.3

0.6

T

BUF

Hold time START condition. After this period,

the first clock pulse is generated

LOW period of the SCL clock

HIGH period of the SCL clock

Set-up time for a repeated START condition

Data hold time

4.0

T

µs

HD:STA

4.7

1.3

0.6

T

µs

ns

pF

LOW

4.0

HIGH

SU:STA

HD:DAT

SU:DAT

R

4.7

0 (1)

250

0 (1)

0.9(2)

Data set-up time

100

Rise time of both SDA and SCL signals

Fall time of both SDA and SCL signals

Set-up time for STOP condition

Capacitive load for each bus line

1000

300

20+0.1Cb

0.6

300

TF

4.0

T

:

SU STO

400

Cb

1)The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined

region of the falling edge of SCL

2)The maximum hold time of the START condition has only to be met if the interface does not stretch the low period of

SCL signal

Cb = total capacitance of one bus line in pF

137/144

ST72774/ST727754/ST72734

USB DC Electrical Characteristics

Parameter

Inputs Levels:

Symbol

Conditions

Min.

Max.

Unit

Differential Input Sensitivity

Differential Common Mode Range

Single Ended Receiver Threshold

Output Levels

VDI

VCM

VSE

AbsI((D+) - (D-))

0.2

0.8

V

Includes VDI range

2.5

2.0

RL of 1.5K ohms to

3.6V

Static Output Low

VOL

0.3

V

RL of 15K ohms to

USBGND

Static Output High

VOH

2.8

3

3.6

V

USBVCC: voltage level

USBV

V

=5V

DD

Notes:

– RL is the load connected on the USB drivers.

– All the voltages are measured from the local ground potential (USBGND).

Figure 78. USB: Data signal Rise and fall time

Differential

Datas Lines

Crossover

points

VCRS

USBGND

tr

tf

USB: Low speed electrical characteristics

Parameter

Symbol

Conditions

Min

75

Max

Unit

Driver characteristics:

Rise time

tr

tf

Note 1, CL=50 pF

Note 1, CL=600 pF

Note 1, CL=50 pF

Note 1, CL=600 pF

tr/tf

ns

%

300

Fall Time

75

300

120

Rise/ Fall Time matching

trfm

80

Output signal Crossover

Voltage

VCRS

1.3

2.0

V

Note1: Measured from 10% to 90% of the data signal

138/144

ST72774/ST727754/ST72734

7 GENERAL INFORMATION

7.1 PACKAGE MECHANICAL DATA

Figure 79. 42-Pin Shrink Plastic Dual In-Line Package, 600-mil Width

mm

Min Typ Max Min Typ Max

5.08 0.200

inches

Dim.

A

A1 0.51

A2 3.05 3.81 4.57 0.120 0.150 0.180

0.020

b

b2

C

0.46 0.56

1.02 1.14

0.018 0.022

0.040 0.045

0.23 0.25 0.38 0.009 0.010 0.015

36.58 36.83 37.08 1.440 1.450 1.460

D

E

15.24

16.00 0.600

0.630

E1 12.70 13.72 14.48 0.500 0.540 0.570

e

1.78

0.070

0.600

eA

15.24

eB

18.54

0.730

0.060

eC 0.00

1.52 0.000

PDIP42S

L

2.54 3.30 3.56 0.100 0.130 0.140

Number of Pins

N

42

Figure 80. 42-Pin Shrink Ceramic Dual In-Line Package, 600-mil Width

mm

Min Typ Max Min Typ Max

4.01 0.158

inches

Dim.

A

A1 0.76

0.38 0.46 0.56 0.015 0.018 0.022

B1 0.76 0.89 1.02 0.030 0.035 0.040

0.030

B

C

D

0.23 0.25 0.38 0.009 0.010 0.015

36.68 37.34 38.00 1.444 1.470 1.496

D1

35.56

1.400

E1 14.48 14.99 15.49 0.570 0.590 0.610

e

1.78

0.070

G

14.12 14.38 14.63 0.556 0.566 0.576

G1 18.69 18.95 19.20 0.736 0.746 0.756

G2 1.14 0.045

G3 11.05 11.30 11.56 0.435 0.445 0.455

G4 15.11 15.37 15.62 0.595 0.605 0.615

L

S

2.92

5.08 0.115

0.200

CDIP42SW

0.89

0.035

Number of Pins

N

42

139/144

8

ST72774/ST727754/ST72734

Figure 81. 44-Pin Thin Quad Flat Package

0.10mm

.004

seating plane

mm

inches

Dim

Min Typ Max Min Typ Max

A

1.60

0.063

0.006

A1 0.05

0.15 0.002

A2 1.35 1.40 1.45 0.053 0.055 0.057

b

c

0.30 0.37 0.45 0.012 0.015 0.018

b

0.09

0.20 0.004

0.008

D

12.00

10.00

8.00

0.472

0.394

0.315

0.472

0.394

0.315

0.031

D1

D3

E

12.00

10.00

8.00

E1

E3

e

c

0.80

K

0°

3.5°

7°

L

0.45 0.60 0.75 0.018 0.024 0.030

1.00 0.039

Number of Pins

44

L1

L

N

K

140/144

ST72774/ST727754/ST72734

8 ORDERING INFORMATION

The following section deals with the procedure for

transfer of customer codes to STMicroelectronics.

unused bytes must be set to 9Dh (opcode for

NOP).

The selected mask options are communicated to

STMicroelectronics using the correctly completed

OPTION LIST appended.

8.1 Transfer of Customer Code

Customer code is made up of the ROM contents

and the list of the selected mask options (if any).

The ROM contents are to be sent on diskette, or by

electronic means, with the hexadecimal file in .S19

format generated by the development tool. All

The STMicroelectronics Sales Organization will be

pleased to provide detailed information on

contractual points.

Figure 82. Sales Type Coding Rules

Family

Version Code

Subfamily (with x=subset index)

Number of pins

ROM size

Package

Temperature Range

ROM Code (three letters)

ST72

T

7x4 J 7 B 1 / xxx

0 = 25° C

B = Plastic DIP

9 = 60K

J = 42 pins

S = 44 pins

No letter = ROM

E = EPROM

T = OTP

1 = Standard (0 to +70°C)

D = Ceramic DIP 7 = 48K

T = Plastic QFP

6 = 32K

Table 35. Development Tools

Development Tool

Sales Type

Remarks

Real time Emulator

ST727x4-EMU2B

220V Power Supply EU

110V Power Supply US

1

EPROM Programmer Board

ST727x4-EPB/xx

ST72E774-GP/D42

ST72E774-GP/Q44

DIL42

PQFP44

Gang Programmer

1

xx stands for the power supply code assigned by ST Microelectronics: EU=220V; US=110V

141/144

ST72774/ST727754/ST72734

Table 36. Ordering Information

RAM

(bytes)

Sales Type

ROM/EPROM (bytes)

TMU

USB

Package

ST72X774 (1)

ST72E774J9D0

ST72T774J9B1

ST72774J9B1/xxx

ST72774J7B1/xxx

ST72774S7T1/xxx

ST72T774S9T1

ST72774S9T1/xxx

ST72X754 (1)

60K EPROM

60K OTP

60K ROM

48K ROM

60K OTP

60K ROM

CSDIP42

PSDIP42

1K

Yes

TQFP44

ST72E754J9D0

ST72T754J9B1

ST72754J9B1/xxx

ST72754J7B1/xxx

ST72T754S9T1

ST72754S9T1

60K EPROM

60K OTP

60K ROM

48K ROM

60K OTP

60K ROM

48K ROM

CSDIP42

PSDIP42

1K

Yes

No

TQFP44

ST72754S7T1/xxx

ST72X734 (2)

ST72E734J6D0

ST72T734J6B1/xxx

ST72734J6B1/xxx

32K EPROM

32K OTP

CSDIP42

PSDIP42

512

No

32K ROM

(1) 8 bit ±2 LSB A/D converter

(2) 8 bit ±4 LSB A/D converter

142/144

ST72774/ST727754/ST72734

STMicroelectronics OPTION LIST

ST727x4 MICROCONTROLLER FAMILY

Customer: . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Address:

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contact:

Phone No: . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reference/ROM Code* : . . . . . . . . . . . . . . . . . . .

*The ROM code name assigned by ST.

STMicroelectronics reference:

Device (SDIP42):

[ ]

ST72774J9B1 (60K ROM)

ST72774J7B1 (48K ROM)

ST72754J9B1 (60K ROM)

ST72754J7B1 (48K ROM)

ST72734J6B1 (32K ROM)

ST72774S9T1 (60K ROM)

ST72774S7T1 (48K ROM)

ST72754S9T1 (60K ROM)

ST72754S7T1 (48K ROM)

ST72E774J9D0 (60K EPROM)

ST72E754J9D0 (60K EPROM)

ST72E734J6D0 (32K EPROM)

STMicroelectronics

Device (TQFP44):

Device (CSDIP42):

Software Development:

Customer

External laboratory

Special Marking:

[ ] No

[ ] Yes "_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _"

For marking, one line is possible with maximum 16 characters for SDIP42 and 10 characters for

TQFP44.

Authorized characters are letters, digits, ’.’, ’-’, ’/’ and spaces only.

Mask Options:

None.

We have checked the ROM code verification file returned to us by STMicroelectronics. It conforms exactly

with the ROM code file orginally supplied. We therefore authorize STMicroelectronics to proceed with

device manufacture.

Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Date

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

143/144

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics

Purchase of I²C Components by STMicroelectronics conveys a license under the Philips I²C Patent. Rights to use these components in an

I²C system is granted provided that the system conforms to the I²C Standard Specification as defined by Philips.

STMicroelectronics Group of Companies

Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain

Sweden - Switzerland - United Kingdom - U.S.A.

http://www.st.com

9


型号：	ST72754J9B1
厂家：	ST
描述：	8-BIT USB MCU FOR MONITORS, WITH UP TO 60K OTP, 1K RAM, ADC, TIMER, SYNC, TMU, PWM/BRM, H/W DDC & I2C 8位USB微控制器可作为显示器，拥有高达60K OTP ， 1K RAM ， ADC ，定时器，同步， TMU ， PWM / BRM ， H / W DDC和I2C 显示器微控制器监视器
文件：	总144页 (文件大小：1276K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ST72754J9B1 [STMICROELECTRONICS]

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