ST72C171_技术文档

ST72C171

8-BIT MCU with 8K FLASH, ADC, WDG, SPI, SCI, TIMERS

SPGAs (Software Programmable Gain Amplifiers), OP-AMP

PRODUCT PREVIEW

■ Memories

– 8K of single voltage Flash Program memory

with read-out protection

– In-Situ Programming (Remote ISP)

■ Clock, Reset and Supply Management

– Enhanced Reset System

– Low voltage supervisor (LVD) with 3 program-

mable levels

SO34

– Low consumption resonator or RC oscillators

(internal or external) and by-pass for external

clock source, with safe control capabilities

– 3 Power Saving modes

■ 22 I/O Ports

– 22 multifunctional bidirectional I/O lines:

– 16 interrupt inputs on 2 independent lines

– 8 lines configurable as analog inputs

– 20 alternate functions

PSDIP32

■ 3 Analog peripherals

– 2 Software Programmable Gain Operational

Amplifiers (SPGAs) with rail-to-rail input and

– EMI filtering

■ 2 Timers and Watchdog

output, V

independent (band gap) and pro-

DD

grammable reference voltage (1/8 V

reso-

DD

– One 16-bit Timer with: 2 Input Captures, 2

Output Compares, external Clock input, PWM

and Pulse Generator modes

– One 8-bit Autoreload Timer (ART) with: 2

PWM output channels (internally connectable

to the SPGA inputs), 1 Input Capture, external

clock input

lution), Offset compensation, DAC & on/off

switching capability

– 1 rail-to-rail input and output Op-Amp

– 8-bit A/D Converter with up to 11 channels (in-

cluding 3 internal channels connected to the

Op-Amp & SPGA outputs)

■ Instruction Set

– Configurable watchdog (WDG)

■ 2 Communications Interfaces

– 8-bit data manipulation

– 63 basic Instructions

– 17 main addressing modes

– 8 x 8 unsigned multiply instruction

– True bit manipulation

– Synchronous Serial Peripheral Interface (SPI)

– Serial Communications Interface (SCI)

■ Development Tools

– Full hardware/software development package

Device Summary

Features

Flash - bytes

ST72C171K2M

ST72C171K2B

8K Single Voltage

256 (128)

RAM (stack) - bytes

2 SPGAs, 1 Op-Amp,

2 SPGAs,

Peripherals

Watchdog, 3 Timers, SPI, SCI, ADC (11 chan.) Watchdog, 3 Timers, SPI, SCI, ADC (11 chan.)

Operating Supply

CPU Frequency

Temperature Range

Package

3.2 V to 5.5 V

Up to 8 MHz (with up to 16 MHz oscillator)

- 40°C to + 85°C

SO34

PSDIP32

Rev. 1.4

1/152

October 2000

This is preliminary information on a new product in development or undergoing evaluation. Details are subject to change without notice.

1

Table of Contents

1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.3 MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.3 STRUCTURAL ORGANISATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.4 IN-SITU PROGRAMMING (ISP) MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.5 MEMORY READ-OUT PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.1 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.2 LOW VOLTAGE DETECTOR (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.3 CLOCK SECURITY SYSTEM (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.4 CLOCK, RESET AND SUPPLY REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . 23

5 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . 24

5.1 NON MASKABLE SOFTWARE INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.2 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.3 PERIPHERAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

6 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.2 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.3 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.4 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

7 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.1 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.2 MISCELLANEOUS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.3 OP-AMP MODULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

7.4 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

7.5 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

7.6 PWM AUTO-RELOAD TIMER (ART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

7.7 SERIAL COMMUNICATIONS INTERFACE (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

7.8 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

7.9 8-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

8 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

8.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

152

8.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

2/152

1

Table of Contents

9 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

9.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

9.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

9.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

9.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

9.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

9.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

9.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

9.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

9.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

9.10 TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

9.11 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . 136

9.12 8-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

9.13 OP-AMP MODULE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

10 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

10.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

10.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

10.3 SOLDERING AND GLUEABILITY INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

10.4 PACKAGE/SOCKET FOOTPRINT PROPOSAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

11 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . 147

11.1 OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

11.2 DEVICE ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

11.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

11.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

11.5 TO GET MORE INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

12 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

3/152

ST72C171

1 GENERAL DESCRIPTION

1.1 INTRODUCTION

The ST72C171 is a member of the ST7 family of

Microcontrollers. All devices are based on a com-

mon industry-standard 8-bit core, featuring an en-

hanced instruction set.

signed multiplication and indirect addressing

modes The device includes a low consumption

and fast start on-chip oscillator, CPU, Flash pro-

gram memory, RAM, 22 I/O lines and the following

on-chip peripherals: Analog-to-Digital converter

(ADC) with 8 multiplexed analog inputs, Op-Amp

module, synchronous SPI serial interface, asyn-

cronous serial interface (SCI), Watchdog timer, a

16-bit Timer featuring external Clock Input, Pulse

Generator capabilities, 2 Input Captures and 2

Output Compares, an 8-bit Timer featuring exter-

nal Clock Input, Pulse Generator Capabilities (2

channels), Autoreload and Input Capture.

The ST72C171 features single-voltage FLASH

memory with byte-by-byte In-Situ Programming

(ISP) capability.

Under software control, the device can be placed

in WAIT, SLOW, or HALT mode, reducing power

consumption when the application is in idle or

standby state.

The enhanced instruction set and addressing

modes of the ST7 offer both power and flexibility to

software developers, enabling the design of highly

efficient and compact application code. In addition

to standard 8-bit data management, all ST7 micro-

controllers feature true bit manipulation, 8x8 un-

The Op-Amp module adds on-chip analog fea-

tures to the MCU, that usually require using exter-

nal components.

Figure 1. ST72C171 Block Diagram

Internal

CLOCK

MULTIOSC

+

OSCIN

PORT A

OSCOUT

CLOCK FILTER

PWM/ART TIMER

PA[7:0]

V

DD

POWER

16-BIT TIMER

LVD

SUPPLY

V

SS

8-BIT ADC

CONTROL

RESET

OA3PIN*

OP-AMP

OA1OUT

OA2OUT

OA3OUT*

8-BIT CORE

ALU

V

DDA

PC[5:0]

V

SSA

PORT C

SCI

8K FLASH

MEMORY

PORT B

PB[7:0]

SPI

256b-RAM

WATCHDOG

*only on 34-pin devices

4/152

ST72C171

1.2 PIN DESCRIPTION

Figure 2. 34-Pin SO Package Pinout

OA2OUT

PWM1R / OA2PIN / PC1

OA2NIN / PC0

OA3PIN

PC2 / OA1PIN / PWM0R

PC3 / OA1NIN

OA1OUT

1

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

2

3

PC4 / MCO/ OA3NIN

V_DDA

4

TDO / PB7

5

RDI / PB6

V_SSA

6

ISPDATA / MISO / PB5

MOSI / (HS) PB4

ISPCLK / SCK / (HS) PB3

SS / (HS) PB2

ARTCLK / (HS) PB1

EXTCLK / (HS) PB0

V_DD

OA3OUT

7

PC5/ PWM0

8

ei1

PA7 / AIN7 / PWM1

PA6 / AIN6 / ARTICP0

PA5 / AIN5

9

10

11

12

PA4 / AIN4 / OCMP1

PA3 / AIN3 / OCMP2

PA2 / AIN2 / ICAP1

PA1 / AIN1 / ICAP2

PA0 / AIN0

ei0

13

14

V_SS

OSC2

15

16

17

OSC1

ISPSEL

RESET

(HS) 20mA high sink capability

Figure 3. 32-Pin SDIP Package Pinout

OA2OUT

PWM1R / OA2PIN / PC1

OA2NIN / PC0

TDO / PB7

1

32

PC2 / OA1PIN / PWM0R

PC3 / OA1NIN

OA1OUT

2

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

3

4

PC4 / MCO

V_DDA

RDI / PB6

5

ISPDATA / MISO / PB5

MOSI / (HS) PB4

ISPCLK / SCK/ (HS) PB3

SS / (HS) PB2

ARTCLK / (HS) PB1

EXTCLK / (HS) PB0

V_DD

6

V_SSA

7

PC5 / PWM0

ei1

8

PA7 / AIN7 / PWM1

9

PA6 / AIN6 /ARTICP0

PA5 / AIN5

10

11

12

13

14

15

16

PA4 / AIN4 / OCMP1

PA3 / AIN3 / OCMP2

PA2 / AIN2 / ICAP1

PA1 / AIN1 / ICAP2

PA0 / AIN0

ei0

V_SS

OSC2

OSC1

ISPSEL

RESET

(HS) 20mA high sink capability

5/152

ST72C171

PIN DESCRIPTION (Cont’d)

Legend / Abbreviations:

Type:

I = input, O = output, S = supply

In/Output level: C = CMOS 0.3V /0.7V

,

DD

C = CMOS Levels with resistive output (1K)

R

A = Analog levels

Output level:

HS = high sink (on N-buffer only),

Port configuration capabilities:

– Input:float = floating, wpu = weak pull-up, int = interrupt, ana = analog

– Output: OD = open drain, T = true open drain, PP = push-pull

Note: the Reset configuration of each pin is shown in bold.

Table 1. Device Pin Description

Level

Port

Main

function

(after

n°

Pin Name

Alternate function

Input

Output

reset)

1

2

OA2OUT

O

A

OA2 output

Port C1

PC1/OA2PIN/

PWM1R

OA2 noninverting input and/or

ART PWM1 resistive output

2

I/O

C

C/C

X

R

3

-

3

4

5

6

PC0/OA2NIN

OA3PIN

I/O C/A

C

Port C0

OA2 inverting input

OA3 noninverting input

SCI transmit

I

A

4

5

PB7/TDO

PB6/RDI

I/O

C

X

ei1

X

Port B7

Port B6

C

SCI receive

SPI data master in/slave out or

In Situ Programming Data In-

put

6

7

PB5/MISO/ISPDATA I/O

C

X

ei1

X

Port B5

7

8

9

PB4/MOSI

I/O

C

HS

X

ei1

X

Port B4

Port B3

SPI data master out/slave in

SPI Clock or In Situ Program-

ming Clock Output

PB3/SCK/ISPCLK

HS

9 10 PB2/SS

I/O

S

C

HS

X

ei1

X

Port B2

Port B1

Port B0

SPI Slave Select (active low)

ART External Clock

10 11 PB1/ARTCLK

11 12 PB0/EXTCLK

Timer16 External Clock

12 13 V

13 14 V

Digital Main Supply Voltage

Digital ground voltage

DD

SS

S

Resonator oscillator inverter output or capaci-

tor input for RC oscillator

14 15 OSC2

15 16 OSC1

16 17 ISPSEL

External clock input or Resonator oscillator in-

verter input or resistor input for RC oscillator

In Situ Programming Mode Select

I

C

Must be tied to V in user mode

SS

17 18 RESET

I/O

C

X

External Reset

18 19 PA0/AIN0

X

ei0

X

Port A0

ADC input 0

ADC input 1 orTimer16 input

capture 2

19 20 PA1/AIN1/ICAP2

I/O

C

ei0

X

Port A1

6/152

ST72C171

n°

Level

Port

Main

function

(after

Pin Name

Alternate function

Input

Output

reset)

ADC input 2

or Timer16 input capture 1

20 21 PA2/AIN2/ICAP1

21 22 PA3/AIN3/OCMP2

I/O

C

X

ei0

X

Port A2

ADC input 3 or Timer16 output

compare 2

Port A3

ADC input 4 or Timer16 output

compare 1

22 23 PA4 /AIN4/OCMP1

23 24 PA5/AIN5

I/O

C

X

ei0

X

Port A4

Port A5

Port A6

ADC input 5

ADC input 6 or ART input cap-

ture

24 25 PA6/AIN6/ARTICP0

ADC input 7 or ART PWM1

output

25 26 PA7/AIN7/PWM1

I/O

C

X

ei0

X

Port A7

26 27 PC5 /PWM0

- 28 OA3OUT

I/O

O

C

A

Port C5

ART PWM0 output

OA3 output

Analog ground

Analog supply

27 29 V

28 30 V

SSA

DDA

Main Clock Out or OA3 invert-

ing input

29 31 PC4/MCO/OA3NIN

I/O

O

C

A

X

Port C4

30 32 OA1OUT

OA1 output

Port C3

31 33 PC3/OA1NIN

I/O C/A

C

X

OA1 inverting input

PC2/OA1PIN/

32 34

OA1 non-inverting input and/

or ART PWM0 resistive output

I/O C/A C/C

Port C2

R

PWM0R

Notes:

1. In the interrupt input column, “eix” defines the associated external interrupt vector. If the weak pull-up

column (wpu) is associated with the interrupt column (int), then the I/O configuration is pull-up interrupt

input, else the configuration is floating interrupt input.

2. OSC1 and OSC2 pins connect a crystal or ceramic resonator, an external RC, or an external source to

the on-chip oscillator see dedicated See “PIN DESCRIPTION” on page 5. for more details.

7/152

ST72C171

1.3 MEMORY MAP

1.3.1 Introduction

Figure 4. Program Memory Map

0000h

HW Registers

0080h

Short Addressing

(see Table 1.3.2)

RAM

Zero page

(128 Bytes)

007Fh

0080h

00FFh

0100h

256 bytes RAM

Stack

017Fh

0180h

(128 Bytes)

Reserved

017Fh

DFFFh

E000h

8 Kbytes

FLASH

FFDFh

FFE0h

Interrupt & Reset Vectors

(see Table 4)

FFFFh

8/152

ST72C171

1.3.2 Data Register

Table 2. Hardware Register Memory Map

Block

Name

Register

Label

Reset

Address

Register name

Remarks

Status

0000h

0001h

0002h

0003h

PADR

Data Register

00h

R/W

PADDR

PAOR

Data Direction Register

Option Register

Not Used

Port A

Absent

0004h

0005h

0006h

0007h

PBDR

PBDDR

PBOR

Data Register

00h

R/W

Data Direction Register

Option Register

Not Used

Port B

Port C

Absent

0008h

0009h

000Ah

PCDR

PCDDR

PCOR

Data Register

00h

R/W

Data Direction Register

Option Register

000Bh to

001Ah

Reserved Area (16 Bytes)

001Bh

001Ch

001Dh

001Eh

001Fh

OA1CR

OA1 Control Register

OA2 Control Register

00h

R/W

OA2CR

OA3CR

OAIRR

OPAMP

OA3 Control Register

OA Interrupt & Readout Register

OA Voltage Reference Control Register

R/W

Section 7.3

R/W

OAVRCR

0020h

MISC1

SPI

MISCR1

Miscellaneous Register 1

00h

see Section 4.3.5

0021h

0022h

0023h

SPIDR

SPICR

SPISR

Data I/O Register

Control Register

Status Register

xxh

0xh

00h

R/W

Read Only

0024h

WDG

CRS

WDGCR

Watchdog Control register

7Fh

R/W

Clock, Reset and Supply Control / Status

Register

0025h

CRSR

00h

R/W

0026h to

0030h

Reserved Area (11 Bytes)

0031h

TACR2

TACR1

Control Register2

Control Register1

00h

xxh

80h

00h

FFh

FCh

FFh

FCh

xxh

80h

00h

R/W

0032h

0033h

0034h-

0035h

0036h-

0037h

0038h-

0039h

003Ah-

003Bh

003Ch-

003Dh

003Eh-

003Fh

TASR

Status Register

Read Only

R/W

TAIC1HR

TAIC1LR

TAOC1HR

TAOC1LR

TACHR

Input Capture1 High Register

Input Capture1 Low Register

Output Compare1 High Register

Output Compare1 Low Register

Counter High Register

R/W

TIMER16

Read Only

R/W

TACLR

Counter Low Register

TAACHR

TAACLR

TAIC2HR

TAIC2LR

TAOC2HR

TAOC2LR

Alternate Counter High Register

Alternate Counter Low Register

Input Capture2 High Register

Input Capture2 Low Register

Output Compare2 High Register

Output Compare2 Low Register

R/W

0040h

MISC2

MISCR2

Miscellaneous Register2

00h

see Section 7.2.2

9/152

ST72C171

Block

Name

Register

Label

Reset

Status

Address

Register name

Remarks

0041h to

004Fh

Reserved Area (15 Bytes)

0050h

0051h

0052h

0053h

0054h

SCISR

SCIDR

Status Register

Data Register

0C0h

0xxh

0Xxh

0xxh

00h

Read Only

R/W

SCI

SCIBRR

SCICR1

SCICR2

Baud Rate Register

Control Register 1

Control Register 2

R/W

0055h to

006Fh

Reserved Area (27 Bytes)

0070h

0071h

ADCDR

Data Register

00h

Read Only

R/W

ADC

ADCCSR

Control/Status Register

0072h

0073h

Reserved Area (2 Bytes)

0074h

0075h

0076h

0077h

0078h

0079h

007Ah

007Bh

PWMDCR1

PWMDCR0

PWMCR

ARTCSR

ARTCAR

ARTARR

ARTICCSR

ARTICR1

PWM Duty Cycle Register 1

PWM Duty Cycle Register 0

PWM Control Register

Control/Status Register

Counter Access Register

Auto Reload Register

R/W

00h

ART/PWM

R/W

Input Capture Control Status Register

Input Capture Register 1

Read Only

007Ch to

007Fh

Reserved Area (4 Bytes)

10/152

ST72C171

2 FLASH PROGRAM MEMORY

2.1 INTRODUCTION

This mode needs five signals (plus the V signal

if necessary) to be connected to the programming

tool. This signals are:

DD

FLASH devices have a single voltage non-volatile

FLASH memory that may be programmed in-situ

(or plugged in a programming tool) on a byte-by-

byte basis.

– RESET: device reset

– V : device ground power supply

SS

– ISPCLK: ISP output serial clock pin

– ISPDATA: ISP input serial data pin

2.2 MAIN FEATURES

– ISPSEL: Remote ISP mode selection. This pin

must be connected to V on the application

■ Remote In-Situ Programming (ISP) mode

■ Up to 16 bytes programmed in the same cycle

■ MTP memory (Multiple Time Programmable)

■ Read-out memory protection against piracy

SS

board through a pull-down resistor.

If any of these pins are used for other purposes on

the application, a serial resistor has to be imple-

mented to avoid a conflict if the other device forces

the signal level.

2.3 STRUCTURAL ORGANISATION

Figure 1 shows a typical hardware interface to a

standard ST7 programming tool. For more details

on the pin locations, refer to the device pinout de-

scription.

The FLASH program memory is organised in a

single 8-bit wide memory block which can be used

for storing both code and data constants.

Figure 5. Typical Remote ISP Interface

The FLASH program memory is mapped in the up-

per part of the ST7 addressing space and includes

the reset and interrupt user vector area .

HE10 CONNECTOR TYPE

TO PROGRAMMING TOOL

XTAL

2.4 IN-SITU PROGRAMMING (ISP) MODE

1

C

L1

L0

The FLASH program memory can be programmed

using Remote ISP mode. This ISP mode allows

the contents of the ST7 program memory to be up-

dated using a standard ST7 programming tools af-

ter the device is mounted on the application board.

This feature can be implemented with a minimum

number of added components and board area im-

pact.

ISPSEL

10KΩ

V

SS

RESET

ISPCLK

An example Remote ISP hardware interface to the

standard ST7 programming tool is described be-

low. For more details on ISP programming, refer to

the ST7 Programming Specification.

ST7

ISPDATA

47KΩ

Remote ISP Overview

The Remote ISP mode is initiated by a specific se-

quence on the dedicated ISPSEL pin.

APPLICATION

The Remote ISP is performed in three steps:

– Selection of the RAM execution mode

– Download of Remote ISP code in RAM

2.5 MEMORY READ-OUT PROTECTION

The read-out protection is enabled through an op-

tion bit.

– Execution of Remote ISP code in RAM to pro-

gram the user program into the FLASH

For FLASH devices, when this option is selected,

the program and data stored in the FLASH memo-

ry are protected against read-out piracy (including

a re-write protection). When this protection option

is removed the entire FLASH program memory is

first automatically erased. However, the E PROM

data memory (when available) can be protected

only with ROM devices.

Remote ISP hardware configuration

In Remote ISP mode, the ST7 has to be supplied

2

with power (V

cillator and application crystal circuit for example).

and V ) and a clock signal (os-

DD

SS

11/152

ST72C171

3 CENTRAL PROCESSING UNIT

3.1 INTRODUCTION

Accumulator (A)

The Accumulator is an 8-bit general purpose reg-

ister used to hold operands and the results of the

arithmetic and logic calculations and to manipulate

data.

This CPU has a full 8-bit architecture and contains

six internal registers allowing efficient 8-bit data

manipulation.

Index Registers (X and Y)

3.2 MAIN FEATURES

In indexed addressing modes, these 8-bit registers

are used to create either effective addresses or

temporary storage areas for data manipulation.

(The Cross-Assembler generates a precede in-

struction (PRE) to indicate that the following in-

struction refers to the Y register.)

■ 63 basic instructions

■ Fast 8-bit by 8-bit multiply

■ 17 main addressing modes

■ Two 8-bit index registers

■ 16-bit stack pointer

The Y register is not affected by the interrupt auto-

matic procedures (not pushed to and popped from

the stack).

■ Low power modes

■ Maskable hardware interrupts

■ Non-maskable software interrupt

Program Counter (PC)

The program counter is a 16-bit register containing

the address of the next instruction to be executed

by the CPU. It is made of two 8-bit registers PCL

(Program Counter Low which is the LSB) and PCH

(Program Counter High which is the MSB).

3.3 CPU REGISTERS

The 6 CPU registers shown in Figure 1 are not

present in the memory mapping and are accessed

by specific instructions.

Figure 6. CPU Registers

7

0

ACCUMULATOR

RESET VALUE = XXh

7

0

X INDEX REGISTER

Y INDEX REGISTER

RESET VALUE = XXh

7

RESET VALUE = XXh

PCL

PCH

7

8

15

0

PROGRAM COUNTER

RESET VALUE = RESET VECTOR @ FFFEh-FFFFh

7

1

0

1

H I N Z

C

CONDITION CODE REGISTER

RESET VALUE =

8

1

X 1 X X X

0

15

7

STACK POINTER

RESET VALUE = STACK HIGHER ADDRESS

X = Undefined Value

12/152

ST72C171

CPU REGISTERS (Cont’d)

CONDITION CODE REGISTER (CC)

Read/Write

because the I bit is set by hardware at the start of

the routine and reset by the IRET instruction at the

end of the routine. If the I bit is cleared by software

in the interrupt routine, pending interrupts are

serviced regardless of the priority level of the cur-

rent interrupt routine.

Reset Value: 111x1xxx

7

0

1

H

I

N

Z

C

Bit 2 = N Negative.

The 8-bit Condition Code register contains the in-

terrupt mask and four flags representative of the

result of the instruction just executed. This register

can also be handled by the PUSH and POP in-

structions.

This bit is set and cleared by hardware. It is repre-

sentative of the result sign of the last arithmetic,

logical or data manipulation. It is a copy of the 7

th

bit of the result.

0: The result of the last operation is positive or null.

1: The result of the last operation is negative

(i.e. the most significant bit is a logic 1).

These bits can be individually tested and/or con-

trolled by specific instructions.

This bit is accessed by the JRMI and JRPL instruc-

tions.

Bit 4 = H Half carry.

This bit is set by hardware when a carry occurs be-

tween bits 3 and 4 of the ALU during an ADD or

ADC instruction. It is reset by hardware during the

same instructions.

0: No half carry has occurred.

1: A half carry has occurred.

Bit 1 = Z Zero.

This bit is set and cleared by hardware. This bit in-

dicates that the result of the last arithmetic, logical

or data manipulation is zero.

0: The result of the last operation is different from

zero.

This bit is tested using the JRH or JRNH instruc-

tion. The H bit is useful in BCD arithmetic subrou-

tines.

1: The result of the last operation is zero.

This bit is accessed by the JREQ and JRNE test

instructions.

Bit 3 = I Interrupt mask.

This bit is set by hardware when entering in inter-

rupt or by software to disable all interrupts except

the TRAP software interrupt. This bit is cleared by

software.

0: Interrupts are enabled.

1: Interrupts are disabled.

Bit 0 = C Carry/borrow.

This bit is set and cleared by hardware and soft-

ware. It indicates an overflow or an underflow has

occurred during the last arithmetic operation.

0: No overflow or underflow has occurred.

1: An overflow or underflow has occurred.

This bit is controlled by the RIM, SIM and IRET in-

structions and is tested by the JRM and JRNM in-

structions.

This bit is driven by the SCF and RCF instructions

and tested by the JRC and JRNC instructions. It is

also affected by the “bit test and branch”, shift and

rotate instructions.

Note: Interrupts requested while I is set are

latched and can be processed when I is cleared.

By default an interrupt routine is not interruptable

13/152

ST72C171

CENTRAL PROCESSING UNIT (Cont’d)

Stack Pointer (SP)

The least significant byte of the Stack Pointer

(called S) can be directly accessed by a LD in-

struction.

Read/Write

Reset Value: 01 7Fh

Note: When the lower limit is exceeded, the Stack

Pointer wraps around to the stack upper limit, with-

out indicating the stack overflow. The previously

stored information is then overwritten and there-

fore lost. The stack also wraps in case of an under-

flow.

15

8

1

0

7

0

The stack is used to save the return address dur-

ing a subroutine call and the CPU context during

an interrupt. The user may also directly manipulate

the stack by means of the PUSH and POP instruc-

tions. In the case of an interrupt, the PCL is stored

at the first location pointed to by the SP. Then the

other registers are stored in the next locations as

shown in Figure 7.

1

SP5

SP4

SP3

SP2

SP1

SP0

The Stack Pointer is a 16-bit register which is al-

ways pointing to the next free location in the stack.

It is then decremented after data has been pushed

onto the stack and incremented before data is

popped from the stack (see Figure 7).

– When an interrupt is received, the SP is decre-

mented and the context is pushed on the stack.

Since the stack is 128 bytes deep, the 10 most sig-

nificant bits are forced by hardware. Following an

MCU Reset, or after a Reset Stack Pointer instruc-

tion (RSP), the Stack Pointer contains its reset val-

ue (the SP5 to SP0 bits are set) which is the stack

higher address.

– On return from interrupt, the SP is incremented

and the context is popped from the stack.

A subroutine call occupies two locations and an in-

terrupt five locations in the stack area.

Figure 7. Stack Manipulation Example

CALL

Subroutine

RET

or RSP

PUSH Y

POP Y

IRET

Interrupt

Event

@ 0100h

SP

Y

CC

A

CC

A

CC

A

X

PCH

PCL

PCH

PCL

PCH

PCL

PCH

PCL

PCH

PCL

PCH

PCL

SP

PCH

PCL

PCH

PCL

SP

@ 017Fh

Stack Higher Address = 017Fh

0100h

Stack Lower Address =

14/152

ST72C171

– Global power down

4 SUPPLY, RESET AND CLOCK

MANAGEMENT

■ Reset Sequence Manager (RSM)

■ Multi-Oscillator (MO)

The device includes a range of utility features for

securing the application in critical situations (for

example in case of a power brown-out), and re-

ducing the number of external components. An

overview is shown in Figure 8.

– 4 Crystal/Ceramic resonator oscillators

– 2 External RC oscillators

– 1 Internal RC oscillator

■ Clock Security System (CSS)

– Clock Filter

4.1 Main Features

– Backup Safe Oscillator

■ Supply Manager

■ Main Clock controller (MCC)

– Main supply Low voltage detection (LVD)

Figure 8. Clock, Reset and Supply Block Diagram

MCO

f

CPU

CLOCK SECURITY SYSTEM

(CSS)

MULTI-

OSCILLATOR

(MO)

MAIN CLOCK

CONTROLLER

(MCC)

f

OSCOUT

OSCIN

OSC

CLOCK

FILTER

SAFE

OSC

RESET SEQUENCE

MANAGER

FROM

WATCHDOG

PERIPHERAL

RESET

(RSM)

-

LVD

CSS

WDG

V

DD

LOW VOLTAGE

DETECTOR

(LVD)

-

RF

0

IE SOD RF

V

SS

CRSR

CF INTERRUPT

15/152

ST72C171

4.2 LOW VOLTAGE DETECTOR (LVD)

To allow the integration of power management

features in the application, the Low Voltage Detec-

tor function (LVD) generates a static reset when

In these conditions, secure operation is always en-

sured for the application without the need for ex-

ternal reset hardware.

the V

supply voltage is below a V reference

DD

IT-

During a Low Voltage Detector Reset, the RESET

pin is held low, thus permitting the MCU to reset

other devices.

value. This means that it secures the power-up as

well as the power-down keeping the ST7 in reset.

The V reference value for a voltage drop is lower

IT-

Notes:

than the V reference value for power-on in order

1. The LVD allows the device to be used without

any external RESET circuitry.

IT+

to avoid a parasitic reset when the MCU starts run-

ning and sinks current on the supply (hysteresis).

2. Three different reference levels are selectable

through the option byte according to the applica-

tion requirement.

The LVD Reset circuitry generates a reset when

V

is below:

DD

LVD application note

– V when V is rising

IT+

DD

– V when V is falling

The LVD function is illustrated in the Figure .

Application software can detect a reset caused by

the LVD by reading the LVDRF bit in the CRSR

register.

IT-

DD

Provided the minimum V value (guaranteed for

DD

This bit is set by hardware when a LVD reset is

generated and cleared by software (writing zero).

the oscillator frequency) is above V , the MCU

IT-

can only be in two modes:

– under full software control

– in static safe reset

Figure 9. Low Voltage Detector vs Reset

V

DD

V

hyst

V

IT+

IT-

RESET

16/152

ST72C171

4.2.1 Reset Sequence Manager (RSM)

The RSM block of the CROSS Module includes

three RESET sources as shown in Figure 10:

These sources act on the RESET PIN and it is al-

ways kept low during the READ OPTION RESET

phase.

■ EXTERNAL RESET SOURCE pulse

■ Internal LVD RESET (Low Voltage Detection)

■ Internal WATCHDOG RESET

The RESET service routine vector is fixed at the

FFFEh-FFFFh addresses in the ST7 memory

map.

Figure 10. Reset Block Diagram

INTERNAL

RESET

V

DD

f

CPU

R

ON

RESET

WATCHDOG RESET

READ OPTION RESET

LVD RESET

The basic RESET sequence consists of 4 phases

as shown in Figure 11:

■ OPTION BYTE reading to configure the device

■ Delay depending on the RESET source

■ 4096 cpu clock cycle delay

The duration of the OPTION BYTE reading phase

(t

) is defined in the Electrical Characteristics

ROB

section. This first phase is initiated by an external

RESET pin pulse detection, a Watchdog RESET

detection, or when V rises up to V

.

LVDopt

DD

The 4096 cpu clock cycle delay allows the oscilla-

tor to stabilise and to ensure that recovery has tak-

en place from the Reset state.

■ RESET vector fetch

The RESET vector fetch phase duration is 2 clock

cycles.

Figure 11. RESET Sequence Phases

RESET

READ

INTERNAL RESET

FETCH

DELAY

OPTION BYTE

4096 CLOCK CYCLES VECTOR

t_ROB

17/152

ST72C171

RESET SEQUENCE MANAGER (Cont’d)

4.2.2 Asynchronous External RESET pin

4.2.3 Internal Low Voltage Detection RESET

The RESET pin is both an input and an open-drain

Two different RESET sequences caused by the in-

ternal LVD circuitry can be distinguished:

output with integrated R

weak pull-up resistor.

ON

This pull-up has no fixed value but varies in ac-

cordance with the input voltage. It can be pulled

low by external circuitry to reset the device. See

electrical characteristics section for more details.

■ Power-On RESET

■ Voltage Drop RESET

The device RESET pin acts as an output that is

pulled low when V <V

(rising edge) or

DD

IT+

A RESET signal originating from an external

V

<V (falling edge) as shown in Figure 12.

DD

IT-

source must have a duration of at least t

in

h(RSTL)in

The LVD filters spikes on V larger than t

avoid parasitic resets.

to

g(VDD)

order to be recognized. This detection is asynchro-

nous and therefore the MCU can enter reset state

even in HALT mode.

DD

4.2.4 Internal Watchdog RESET

The RESET pin is an asynchronous signal which

plays a major role in EMS performance. In a noisy

environment, it is recommended to follow the

guidelines mentioned in the electrical characteris-

tics section.

The RESET sequence generated by a internal

Watchdog counter overflow is shown in Figure 12.

Starting from the Watchdog counter underflow, the

device RESET pin acts as an output that is pulled

low during at least t

.

w(RSTL)out

Two RESET sequences can be associated with

this RESET source: short or long external reset

pulse (see Figure 12).

Starting from the external RESET pulse recogni-

tion, the device RESET pin acts as an output that

is pulled low during at least t

.

w(RSTL)out

Figure 12. RESET Sequences

V

DD

V

IT+

IT-

LVD

RESET

SHORT EXT.

RESET

LONG EXT.

RESET

WATCHDOG

RESET

RUN

DELAY

t

w(RSTL)out

h(RSTL)in

t

w(RSTL)out

t

h(RSTL)in

EXTERNAL

RESET

SOURCE

RESET PIN

WATCHDOG

RESET

WATCHDOG UNDERFLOW

INTERNAL RESET (4096 T_CPU

FETCH VECTOR

)

18/152

ST72C171

4.2.4.1 Multi-Oscillator (MO)

has to drive the OSCin pin while the OSCout pin is

tied to ground (see Figure 13).

The Multi-Oscillator (MO) block is the main clock

supplier of the ST7. To insure an optimum integra-

tion in the application, it is based on an external

clock source and six different selectable oscilla-

tors.

Figure 13. MO External Clock

ST7

OSCin

OSCout

The main clock of the ST7 can be generated by 8

different sources comming from the MO block:

■ an External source

■ 4 Crystal or Ceramic resonator oscillators

■ 1 External RC oscillators

EXTERNAL

SOURCE

■ 1 Internal High Frequency RC oscillator

Crystal/Ceramic Oscillators

Each oscillator is optimized for a given frequency

range in term of consumption and is selectable

through the Option Byte.

This family of oscillators allows a high accuracy on

the main clock of the ST7. The selection within the

list of 4 oscillators has to be done by Option Byte

according to the resonator frequency in order to

reduce the consumption. In this mode of the MO

block, the resonator and the load capacitors have

to be connected as shown in Figure 14 and have

to be mounted as close as possible to the oscilla-

tor pins in order to minimize output distortion and

start-up stabilization time.

External Clock Source

The default Option Byte value selects the External

Clock in the MO block. In this mode, a clock signal

(square, sinus or triangle) with ~50% duty cycle

These oscillators, when selected via the Option

Byte, are not stopped during the RESET phase to

avoid losing time in the oscillator starting phase.

Figure 14. MO Crystal/Ceramic Resonator

ST7

OSCin

OSCout

C

L1

L0

LOAD

CAPACITORS

19/152

ST72C171

MULTIOSCILLATOR (MO) (Cont’d)

External RC Oscillator

Internal RC Oscillator

This oscillator allows a low cost solution on the

main clock of the ST7 using only an external resis-

tor and an external capacitor (see Figure 15). The

selection of the external RC oscillator has to be

done by Option Byte.

The Internal RC oscillator mode is based on the

same principle as the External RC one including

the an on-chip resistor and capacitor. This mode is

the most cost effective one with the drawback of a

lower frequency accuracy. Its frequency is in the

range of several MHz.

The frequency of the external RC oscillator is fixed

by the resistor and the capacitor values:

In this mode, the two oscillator pins have to be tied

to ground as shown in Figure 16.

N

. C

f

~

OSC

R

The selection of the internal RC oscillator has to

be done by Option Byte.

EX

The previous formula shows that in this MO mode,

the accuracy of the clock is directly linked to the

accuracy of the discrete components.

Figure 16. MO Internal RC

ST7

Figure 15. MO External RC

OSCin

OSCout

ST7

OSCin

OSCout

R

C

EX

20/152

ST72C171

4.3 CLOCK SECURITY SYSTEM (CSS)

The Clock Security System (CSS) protects the

ST7 against main clock problems. To allow the in-

tegration of the security features in the applica-

tions, it is based on a clock filter control and an In-

ternal safe oscillator. The CSS can be enabled or

disabled by option byte.

Limitation detection

The automatic safe oscillator selection is notified

by hardware setting the CSSD bit of the CRSR

register. An interrupt can be generated if the CS-

SIE bit has been previously set.

These two bits are described in the CRSR register

description.

4.3.1 Clock Filter Control

4.3.3 Low Power Modes

The clock filter is based on a clock frequency limi-

tation function.

Mode

WAIT

Description

This filter function is able to detect and filter high

frequency spikes on the ST7 main clock.

No effect on CSS. CSS interrupt cause the

device to exit from Wait mode.

If the oscillator is not working properly (e.g. work-

ing at a harmonic frequency of the resonator), the

current active oscillator clock can be totally fil-

tered, and then no clock signal is available for the

ST7 from this oscillator anymore. If the original

clock source recovers, the filtering is stopped au-

tomatically and the oscillator supplies the ST7

clock.

The CRSR register is frozen. The CSS (in-

cluding the safe oscillator) is disabled until

HALT mode is exited. The previous CSS

configuration resumes when the MCU is

woken up by an interrupt with “exit from

HALT mode” capability or from the counter

reset value when the MCU is woken up by a

RESET.

HALT

4.3.2 Safe Oscillator Control

4.3.4 Interrupts

The safe oscillator of the CSS block is a low fre-

quency back-up clock source (see Figure 17).

The CSS interrupt event generates an interrupt if

the corresponding Enable Control Bit (CSSIE) is

set and the interrupt mask in the CC register is re-

set (RIM instruction).

If the clock signal disappears (due to a broken or

disconnected resonator...) during a safe oscillator

period, the safe oscillator delivers a low frequency

clock signal which allows the ST7 to perform some

rescue operations.

Enable Exit

Control from

Exit

Event

Flag

Interrupt Event

from

1)

Bit

Wait Halt

Automatically, the ST7 clock source switches back

from the safe oscillator if the original clock source

recovers.

CSS event detection

(safe oscillator acti- CSSD CSSIE

vated as main clock)

Yes No

Note 1: This interrupt allows to exit from active-halt

mode if this mode is available in the MCU.

Figure 17. Clock Filter Function and Safe Oscillator Function

f

/2

OSC

f

CPU

f

/2

OSC

f

SFOSC

f

CPU

21/152

ST72C171

4.3.5 Main Clock Controller (MCC)

The MCC block supplies the clock for the ST7

CPU and its internal peripherals. It allows the pow-

er saving modes such as SLOW mode to be man-

aged by the application.

The prescaler allows the selection of the main

clock frequency and is controlled with three bits of

the MISCR1: CP1, CP0 and SMS.

The clock-out capability is an Alternate Function of

All functions are managed by the Miscellaneous

Register 1 (MISCR1).

an I/O port pin, providing the f

put for driving external devices. It is controlled by

the MCO bit in the MISCR1 register.

clock as an out-

CPU

The MCC block consists of:

– a programmable CPU clock prescaler

– a clock-out signal to supply external devices

Figure 18. Main Clock Controller (MCC) Block Diagram

MULTI-

OSCILLATOR

(MO)

CLOCK

FILTER

(CF)

OSCIN

f

OSC

DIV 2

OSCOUT

DIV 2, 4, 8, 16

MISCR1

MCO

CP1 CP0 SMS

CPU CLOCK

TO CPU AND

PERIPHERALS

f

CPU

PORT

ALTERNATE

FUNCTION

MCO

22/152

ST72C171

4.4 CLOCK, RESET AND SUPPLY REGISTER DESCRIPTION

CLOCK RESET AND SUPPLY REGISTER

(CRSR)

Bit 1 = CSSD CSS Safe Osc. Detection

This bit indicates that the safe oscillator of the CSS

block has been selected. It is set by hardware and

cleared by reading the CRSR register when the

original oscillator recovers.

Read/Write

Reset Value: 000x 000x (00h)

7

0

0: Safe oscillator is not active

1: Safe oscillator has been activated

LVD

RF

CSS CSS WDG

-

IE

D

RF

Bit 0 = WDGRF WatchDog Reset Flag

This bit indicates when set that the last Reset was

generated by the Watchdog peripheral. It is set by

hardware (watchdog reset) and cleared by soft-

ware (writing zero) or an LVD Reset.

Combined with the LVDRF flag information, the

flag description is given by the following table.

Bit 7:5 = Reserved.

Bit 4 = LVDRF LVD Reset Flag

This bit indicates when set that the last Reset was

generated by the LVD block. It is set by hardware

(LVD reset) and cleared by software (writing zero)

or a Watchdog Reset. See WDGRF flag descrip-

tion for more details.

RESET Sources

External RESET pin

Watchdog

LVDRF WDGRF

0

1

0

1

X

LVD

Bit 3 = Reserved.

Bit 2 = CSSIE CSS Interrupt Enable

This bit allows to enable the interrupt when a dis-

trurbance is detected by the Clock Security Sys-

tem (CSSD bit set). It is set and cleared by soft-

ware.

0: Clock Filter interrupt disable

1: Clock Filter interrupt enable

Table 3. Supply, Reset and Clock Register Map and Reset Values

Address

(Hex.)

Register

Label

7

6

5

4

3

2

1

0

MISCR

Reset Value

PEI3

0

PEI2

0

MCO

0

PEI1

0

PEI0

0

CP1

0

CP0

0

SMS

0

0020h

0025h

CRSR

Reset Value

-

0

-

0

-

0

LVDRF

x

-

0

CSSIE

0

CSSD

0

WDGRF

x

23/152

ST72C171

5 INTERRUPTS

The ST7 core may be interrupted by one of two dif-

ferent methods: maskable hardware interrupts as

listed in the Interrupt Mapping Table and a non-

maskable software interrupt (TRAP). The Interrupt

processing flowchart is shown in Figure 19.

The maskable interrupts must be enabled clearing

the I bit in order to be serviced. However, disabled

interrupts may be latched and processed when

they are enabled (see external interrupts subsec-

tion).

It will be serviced according to the flowchart on

Figure 19.

5.2 EXTERNAL INTERRUPTS

External interrupt vectors can be loaded into the

PC register if the corresponding external interrupt

occurred and if the I bit is cleared. These interrupts

allow the processor to leave the Halt low power

mode.

When an interrupt has to be serviced:

The external interrupt polarity is selected through

the miscellaneous register or interrupt register (if

available).

– Normal processing is suspended at the end of

the current instruction execution.

An external interrupt triggered on edge will be

latched and the interrupt request automatically

cleared upon entering the interrupt service routine.

– The PC, X, A and CC registers are saved onto

the stack.

– The I bit of the CC register is set to prevent addi-

tional interrupts.

If several input pins, connected to the same inter-

rupt vector, are configured as interrupts, their sig-

nals are logically ANDed before entering the edge/

level detection block.

– The PC is then loaded with the interrupt vector of

the interrupt to service and the first instruction of

the interrupt service routine is fetched (refer to

the Interrupt Mapping Table for vector address-

es).

Caution: The type of sensitivity defined in the Mis-

cellaneous or Interrupt register (if available) ap-

plies to the ei source. In case of an ANDed source

(as described on the I/O ports section), a low level

on an I/O pin configured as input with interrupt,

masks the interrupt request even in case of rising-

edge sensitivity.

The interrupt service routine should finish with the

IRET instruction which causes the contents of the

saved registers to be recovered from the stack.

Note: As a consequence of the IRET instruction,

the I bit will be cleared and the main program will

resume.

5.3 PERIPHERAL INTERRUPTS

Priority Management

Different peripheral interrupt flags in the status

register are able to cause an interrupt when they

are active if both:

By default, a servicing interrupt cannot be inter-

rupted because the I bit is set by hardware enter-

ing in interrupt routine.

– The I bit of the CC register is cleared.

In the case when several interrupts are simultane-

ously pending, an hardware priority defines which

one will be serviced first (see the Interrupt Map-

ping Table).

– The corresponding enable bit is set in the control

register.

If any of these two conditions is false, the interrupt

is latched and thus remains pending.

Interrupts and Low Power Mode

Clearing an interrupt request is done by:

All interrupts allow the processor to leave the

WAIT low power mode. Only external and specifi-

cally mentioned interrupts allow the processor to

leave the HALT low power mode (refer to the “Exit

from HALT“ column in the Interrupt Mapping Ta-

ble).

– Writing “0” to the corresponding bit in the status

register or

– Access to the status register while the flag is set

followed by a read or write of an associated reg-

ister.

Note: the clearing sequence resets the internal

latch. A pending interrupt (i.e. waiting for being en-

abled) will therefore be lost if the clear sequence is

executed.

5.1 NON MASKABLE SOFTWARE INTERRUPT

This interrupt is entered when the TRAP instruc-

tion is executed regardless of the state of the I bit.

24/152

ST72C171

INTERRUPTS (Cont’d)

Figure 19. Interrupt Processing Flowchart

FROM RESET

N

I BIT SET?

Y

N

INTERRUPT

PENDING?

Y

FETCH NEXT INSTRUCTION

N

IRET?

STACK PC, X, A, CC

SET I BIT

Y

LOAD PC FROM INTERRUPT VECTOR

EXECUTE INSTRUCTION

RESTORE PC, X, A, CC FROM STACK

THIS CLEARS I BIT BY DEFAULT

25/152

ST72C171

INTERRUPTS (Cont’d)

Table 4. Interrupt Mapping

Source

Register

Label

Exit from

HALT

Vector

Address

Priority

Order

Description

Flag

Block

RESET

TRAP

ei0

Reset

N/A

yes

no

FFFEh-FFFFh

FFFCh-FFFDh

FFFAh-FFFBh

FFF8h-FFF9h

FFF6h-FFF7h

Highest

Priority

Software

Ext. Interrupt ei0

Ext. Interrupt ei1

Clock Filter Interrupt

Transfer Complete

Mode Fault

N/A

yes

no

ei1

N/A

CSS

CRSR

CSSD

SPIF

SPI

SPISR

no

FFF4h-FFF5h

MODF

ICF1_1

OCF1_1

ICF2_1

OCF2_1

TOF_1

ICF0

Input Capture 1

Output Compare 1

Input Capture 2

Output Compare 2

Timer Overflow

Input Capture 1

Timer Overflow

OA1 Interrupt

TIMER 16

TASR

no

FFF2h-FFF3h

ARTICCSR

ARTCSR

FFF0h-FFF1h

FFEEh-FFEFh

FFECh-FFEDh

FFEAh-FFEBh

FFE6-FFE9

ART/PWM

OP-AMP

yes

OVF

OA1V

OA2V

OIRR

OA2 Interrupt

NOT USED

SCI Peripheral Interrupts

SCI

no

FFE4-FFE5

Lowest

Priority

NOT USED

FFE0h-FFE3h

26/152

ST72C171

6.2 SLOW MODE

6 POWER SAVING MODES

This mode has two targets:

6.1 INTRODUCTION

– To reduce power consumption by decreasing the

internal clock in the device,

To give a large measure of flexibility to the applica-

tion in terms of power consumption, three main

power saving modes are implemented in the ST7

(see Figure 20).

– To adapt the internal clock frequency (f

the available supply voltage.

) to

CPU

SLOW mode is controlled by three bits in the

MISCR1 register: the SMS bit which enables or

disables Slow mode and two CPx bits which select

After a RESET the normal operating mode is se-

lected by default (RUN mode). This mode drives

the device (CPU and embedded peripherals) by

means of a master clock which is based on the

the internal slow frequency (f

).

CPU

In this mode, the oscillator frequency can be divid-

ed by 4, 8, 16 or 32 instead of 2 in normal operat-

ing mode. The CPU and peripherals are clocked at

this lower frequency.

main oscillator frequency divided by 2 (f

).

CPU

From Run mode, the different power saving

modes may be selected by setting the relevant

register bits or by calling the specific ST7 software

instruction whose action depends on the the oscil-

lator status.

Note: SLOW-WAIT mode is activated when enter-

ring the WAIT mode while the device is already in

SLOW mode.

Figure 20. Power Saving Mode Transitions

Figure 21. SLOW Mode Clock Transitions

High

RUN

f

/4

f

/8

f

/2

OSC

f

CPU

f

/2

OSC

SLOW

WAIT

00

01

CP1:0

SMS

SLOW WAIT

HALT

NORMAL RUN MODE

REQUEST

NEW SLOW

FREQUENCY

REQUEST

Low

POWER CONSUMPTION

27/152

ST72C171

POWER SAVING MODES (Cont’d)

6.3 WAIT MODE

Figure 22. WAIT Mode Flow-chart

WAIT mode places the MCU in a low power con-

sumption mode by stopping the CPU.

This power saving mode is selected by calling the

OSCILLATOR

PERIPHERALS

ON

OFF

0

WFI INSTRUCTION

CPU

“WFI” ST7 software instruction.

I BIT

All peripherals remain active. During WAIT mode,

the I bit of the CC register are forced to 0, to ena-

ble all interrupts. All other registers and memory

remain unchanged. The MCU remains in WAIT

mode until an interrupt or Reset occurs, whereup-

on the Program Counter branches to the starting

address of the interrupt or Reset service routine.

The MCU will remain in WAIT mode until a Reset

or an Interrupt occurs, causing it to wake up.

N

RESET

Y

N

INTERRUPT

Y

OSCILLATOR

PERIPHERALS

CPU

ON

OFF

ON

1

Refer to Figure 22.

I BIT

4096 CPU CLOCK CYCLE

DELAY

OSCILLATOR

PERIPHERALS

CPU

ON

1

I BIT (see note)

FETCH RESET VECTOR

OR SERVICE INTERRUPT

Note: Before servicing an interrupt, the CC regis-

ter is pushed on the stack. The I bit of the CC reg-

ister is set during the interrupt routine and cleared

when the CC register is popped.

28/152

ST72C171

POWER SAVING MODES (Cont’d)

6.4 HALT MODE

Figure 24. HALT Mode Flow-chart

The HALT mode is the lowest power consumption

mode of the MCU. It is entered by executing the

ST7 HALT instruction (see Figure 24).

HALT INSTRUCTION

ENABLE

The MCU can exit HALT mode on reception of ei-

ther an specific interrupt (see Table 4, “Interrupt

Mapping,” on page 26) or a RESET. When exiting

HALT mode by means of a RESET or an interrupt,

the oscillator is immediately turned on and the

4096 CPU cycle delay is used to stabilize the os-

cillator. After the start up delay, the CPU resumes

operation by servicing the interrupt or by fetching

the reset vector which woke it up (see Figure 23).

When entering HALT mode, the I bit in the CC reg-

ister is forced to 0 to enable interrupts. Therefore,

if an interrupt is pending, the MCU wakes immedi-

ately.

WATCHDOG

0

DISABLE

WDGHALT ¹⁾

1

WATCHDOG

RESET

OSCILLATOR

OFF

PERIPHERALS ²⁾

OFF

0

CPU

I BIT

N

RESET

In the HALT mode the main oscillator is turned off

causing all internal processing to be stopped, in-

cluding the operation of the on-chip peripherals.

All peripherals are not clocked except the ones

which get their clock supply from another clock

generator (such as an external or auxiliary oscilla-

tor).

Y

N

INTERRUPT ³⁾

OSCILLATOR

PERIPHERALS

CPU

Y

ON

OFF

ON

1

The compatibility of Watchdog operation with

HALT mode is configured by the “WDGHALT” op-

tion bit of the option byte. The HALT instruction

when executed while the Watchdog system is en-

abled, can generate a Watchdog RESET (see

Section 11.1 OPTION BYTES for more details).

I BIT

4096 CPU CLOCK CYCLE

DELAY

OSCILLATOR

PERIPHERALS

CPU

I BIT ⁴⁾

ON

1

Figure 23. HALT Mode Timing Overview

4096 CPU CYCLE

RUN

HALT

RUN

DELAY

FETCH RESET VECTOR

OR SERVICE INTERRUPT

HALT

INSTRUCTION

Notes:

1. WDGHALT is an option bit. See option byte sec-

tion for more details.

2. Peripheral clocked with an external clock source

RESET

OR

INTERRUPT

FETCH

VECTOR

can still be active.

3. Only some specific interrupts can exit the MCU

from HALT mode (such as external interrupt). Re-

fer to Table 4, “Interrupt Mapping,” on page 26 for

more details.

4. Before servicing an interrupt, the CC register is

pushed on the stack. The I bit of the CC register is

set during the interrupt routine and cleared when

the CC register is popped.

29/152

ST72C171

7 ON-CHIP PERIPHERALS

7.1 I/O PORTS

7.1.1 Introduction

Interrupt function

The I/O ports offer different functional modes:

– transfer of data through digital inputs and outputs

and for specific pins:

When an I/O is configured in Input with Interrupt,

an event on this I/O can generate an external In-

terrupt request to the CPU. The interrupt sensitivi-

ty is given independently according to the descrip-

tion mentioned in the Miscellaneous register or in

the interrupt register (where available).

– analog signal input (ADC)

– alternate signal input/output for the on-chip pe-

ripherals.

Each pin can independently generate an Interrupt

request.

– external interrupt generation

Each external interrupt vector is linked to a dedi-

cated group of I/O port pins (see Interrupts sec-

tion). If more than one input pin is selected simul-

taneously as interrupt source, this is logically

ORed. For this reason if one of the interrupt pins is

tied low, it masks the other ones.

An I/O port is composed of up to 8 pins. Each pin

can be programmed independently as digital input

(with or without interrupt generation) or digital out-

put.

7.1.2 Functional Description

Each port is associated to 2 main registers:

– Data Register (DR)

7.1.2.2 Output Mode

The pin is configured in output mode by setting the

corresponding DDR register bit.

– Data Direction Register (DDR)

In this mode, writing “0” or “1” to the DR register

applies this digital value to the I/O pin through the

latch. Then reading the DR register returns the

previously stored value.

and some of them to an optional register (see reg-

ister description):

– Option Register (OR)

Each I/O pin may be programmed using the corre-

sponding register bits in DDR and OR registers: bit

X corresponding to pin X of the port. The same cor-

respondence is used for the DR register.

Note: In this mode, the interrupt function is disa-

bled.

7.1.2.3 Digital Alternate Function

When an on-chip peripheral is configured to use a

pin, the alternate function is automatically select-

ed. This alternate function takes priority over

standard I/O programming. When the signal is

coming from an on-chip peripheral, the I/O pin is

automatically configured in output mode (push-pull

or open drain according to the peripheral).

The following description takes into account the

OR register, for specific ports which do not provide

this register refer to the I/O Port Implementation

Section 7.1.2.5. The generic I/O block diagram is

shown on Figure 26.

7.1.2.1 Input Modes

The input configuration is selected by clearing the

corresponding DDR register bit.

When the signal is going to an on-chip peripheral,

the I/O pin has to be configured in input mode. In

this case, the pin’s state is also digitally readable

by addressing the DR register.

In this case, reading the DR register returns the

digital value applied to the external I/O pin.

Different input modes can be selected by software

through the OR register.

Notes:

1. Input pull-up configuration can cause an unex-

pected value at the input of the alternate peripher-

al input.

2. When the on-chip peripheral uses a pin as input

and output, this pin must be configured as an input

(DDR = 0).

Notes:

1. All the inputs are triggered by a Schmitt trigger.

2. When switching from input mode to output

mode, the DR register should be written first to

output the correct value as soon as the port is con-

figured as an output.

Warning: The alternate function must not be acti-

vated as long as the pin is configured as input with

interrupt, in order to avoid generating spurious in-

terrupts.

30/152

ST72C171

I/O PORTS (Cont’d)

7.1.2.4 Analog Alternate Function

7.1.2.5 I/O Port Implementation

When the pin is used as an ADC input the I/O must

be configured as input, floating. The analog multi-

plexer (controlled by the ADC registers) switches

the analog voltage present on the selected pin to

the common analog rail which is connected to the

ADC input.

The hardware implementation on each I/O port de-

pends on the settings in the DDR and OR registers

and specific feature of the I/O port such as ADC In-

put (see Figure 26) or true open drain. Switching

these I/O ports from one state to another should

be done in a sequence that prevents unwanted

side effects. Recommended safe transitions are il-

lustrated in Figure 25. Other transitions are poten-

tially risky and should be avoided, since they are

likely to present unwanted side-effects such as

spurious interrupt generation.

It is recommended not to change the voltage level

or loading on any port pin while conversion is in

progress. Furthermore it is recommended not to

have clocking pins located close to a selected an-

alog pin.

Warning: The analog input voltage level must be

within the limits stated in the Absolute Maximum

Ratings.

Figure 25. Recommended I/O State Transition Diagram

OUTPUT

push-pull

INPUT

no interrupt

OUTPUT

INPUT

with interrupt

open-drain

31/152

ST72C171

I/O PORTS (Cont’d)

Figure 26. I/O Block Diagram

ALTERNATE ENABLE

1

V

ALTERNATE

OUTPUT

DD

M

U

X

P-BUFFER

(SEE TABLE BELOW)

0

DR

LATCH

ALTERNATE

ENABLE

PULL-UP (SEE TABLE BELOW)

PULL-UP

CONDITION

DDR

LATCH

PAD

OR

ANALOG ENABLE

(ADC)

LATCH

(SEE TABLE BELOW)

ANALOG

SWITCH

OR SEL

(SEE NOTE BELOW)

DDR SEL

N-BUFFER

ALTERNATE

ENABLE

1

0

DR SEL

M

U

X

GND

ALTERNATE INPUT

CMOS

SCHMITT TRIGGER

SENSITIVITY

SEL

FROM

OTHER

BITS

EXTERNAL

INTERRUPT

SOURCE (EIx)

Table 5. Port Mode Configuration

Configuration Mode

Floating

Pull-up

P-buffer

0

Pull-up

1

0

Push-pull

0

1

True Open Drain

Open Drain (logic level)

not present

0

not present

0

Legend:

Notes:

– No OR Register on some ports (see register map).

– ADC Switch on ports with analog alternate functions.

0 -

1 -

present, not activated

present and activated

32/152

ST72C171

I/O PORTS (Cont’d)

7.1.2.6 Device Specific Configurations

Table 6. Port Configuration

Input (DDR =0)

OR = 1

Output (DDR=1)

Port

Pin name

PA7: PA0

PB0:PB4

OR = 0

OR = 1

Port A

floating*

pull-up with interrupt

open drain

push-pull

open drain

floating*

push-pull

high sink capability

Port B

PB5:PB7

PC0:PC5

floating*

pull-up with interrupt

pull-up

open drain

push-pull

Port C

*Reset state.

33/152

ST72C171

I/O PORTS (Cont’d)

7.1.3 Register Description

DATA REGISTERS

Port A Data Register (PADR)

Port B Data Register (PBDR)

Port C Data Register (PCDR)

OPTION REGISTERS

PORT A Option Register (PAOR)

PORT B Option Register (PBOR)

PORT C Option Register (PCOR)

Read/Write

Reset Value: 0000 0000 (00h)

Read/Write

Reset Value: 0000 0000 (00h) (no interrupt)

7

0

7

0

D7

D6

D5

D4

D3

D2

D1

D0

O7

O6

O5

O4

O3

O2

O1

O0

Bit 7:0 = D[7:0] Data Register 8 bits.

The DR register has a specific behaviour accord-

ing to the selected input/output configuration. Writ-

ing the DR register is always taken in account

even if the pin is configured as an input. Reading

the DR register returns either the DR register latch

content (pin configured as output) or the digital val-

ue applied to the I/O pin (pin configured as input).

Bit 7:0 = O[7:0] Option Register 8 bits.

The PAOR, PBOR and PCOR registers are used

to select pull-up or floating configuration in input

mode.

Each bit is set and cleared by software.

Input mode:

0: Floating input

1: Input pull-up (with or without interrupt see Table

6)

DATA DIRECTION REGISTERS

Port A Data Direction Register (PADDR)

Port B Data Direction Register (PBDDR)

Port C Data Direction Register (PCDDR)

Read/Write

Reset Value: 0000 0000 (00h) (input mode)

7

0

DD7

DD6

DD5

DD4

DD3 DD2

DD1

DD0

Bit 7:0 = DD[7:0] Data Direction Register 8 bits.

The DDR register gives the input/output direction

configuration of the pins. Each bits is set and

cleared by software.

0: Input mode

1: Output mode

34/152

ST72C171

I/O PORTS (Cont’d)

Table 7. I/O Port Register Map and Reset Values

Address

(Hex.)

Register

Label

7

6

5

4

3

2

1

0

PADR

D7

0

D6

0

D5

0

D4

0

D3

0

D2

0

D1

0

D0

0

0000h

0001h

0002h

0004h

0005h

0006h

0008h

0009h

000Ah

Reset Value

PADDR

D7

0

D6

0

D5

0

DD4

0

DD3

0

DD2

0

DD1

0

DD0

0

Reset Value

PAOR

D7

0

D6

0

D5

0

O4

0

O3

0

O2

0

O1

0

O0

0

Reset Value

PBDR

D7

0

D6

0

D5

0

D4

0

D3

0

D2

0

D1

0

D0

0

Reset Value

PBDDR

DD7

0

DD6

0

DD5

0

DD4

0

DD3

0

DD2

0

DD1

0

DD0

0

Reset Value

PBOR

O7

0

O6

0

O5

0

O4

0

O3

0

O2

0

O1

0

O0

0

Reset Value

PCDR

D7

0

D6

0

D5

0

D4

0

D3

0

D2

0

D1

0

D0

0

Reset Value

PCDDR

DD7

0

DD6

0

DD5

0

DD4

0

DD3

0

DD2

0

DD1

0

DD0

0

Reset Value

PCOR

O7

0

O6

0

O5

0

O4

0

O3

0

O2

0

O1

0

O0

0

Reset Value

35/152

ST72C171

7.2 MISCELLANEOUS REGISTERS

7.2.1 Miscellaneous Register 1 (MISCR1)

Miscellaneous register 1 is used select SLOW op-

erating mode. Bits 3, 4, 6, and 7 determine the po-

larity of external interrupt requests.

Bit 4:3 = PEI[1:0] Polarity Options of External In-

terrupt ei0. (Port A)

These bits determine which event causes the ex-

ternal interrupt (ei0) on port A according to Table

9.

Register Address: 0020h

—

Read/Write

Reset Value: 0000 0000 (00h)

Table 9. ei0 Ext. Int. Polarity Options

MODE

PEI1

PEI0

7

0

Falling edge and low level

(Reset state)

0

PEI3 PEI2 MCO PEI1 PEI0 CP1 CP0 SMS

Rising edge only

Falling edge only

0

1

0

1

Bit 7:6 = PEI[3:2] Polarity Options of External In-

terrupt ei1. (Port B).

These bits are set and cleared by software. These

bits determine which event causes the external in-

terrupt (ei1) on port B according to Table 8.

Rising and falling edge

Table 8. ei1 Ext. Int. Polarity Options

Bit 2:1 = CP[1:0] CPU clock prescaler

These bits are set and cleared by software. They

determine the CPU clock when the SMS bit is set

according to the following table.

MODE

PEI3 PEI2

Falling edge and low level

(Reset state)

0

Table 10. f

Value in Slow Mode

Rising edge only

Falling edge only

0

1

0

1

CPU

f

Value

CP1

CP0

CPU

f_OSC/ 4

_OSC/ 8

Rising and falling edge

0

1

0

1

0

1

f

Bit 5 = MCO Main clock out selection

f

_OSC/ 16

_OSC/ 32

This bit enables the MCO alternate function on the

I/O port. It is set and cleared by software.

0: MCO alternate function disabled

f

(I/O pin free for general-purpose I/O)

1: MCO alternate function enabled

Bit 0 = SMS Slow Mode Select

This bit is set and cleared by software.

0: Normal Mode - f = f / 2

(f

/2 on I/O port)

OSC

CPU

OSC

This bit is set and cleared by software. When set it

can be used to output the internal clock to the ded-

icated I/O port.

1: Slow Mode - the f

PC[1:0] bits.

value is determined by the

CPU

36/152

ST72C171

7.2.2 Miscellaneous Register 2 (MISCR2)

floating input. This should be done prior to setting

the P1OS bit.

Miscellaneous register 2 is used to configure of

SPI and the output selection of the PWMs.

Register Address: 0040h

—

Read/Write

Bit 2 = P0OS PWM0 output select

This bit is used to select the output for the PWM0

channel of ART/PWM Timer.

Reset Value: 0000 0000 (00h)

0: PWM0 output on PWM0 pin

1: PWM0 output on PWM0R pin and connected to

the OA1PIN pin

7

0

-

SPIOD P1OS P0OS SSM SSI

Note: In order to use the PC2 port pin as a PWM

output pin, bit 2 of port C must be programmed as

floating input. This should be done prior to setting

the P0OS bit.

Bit 7:5 = not used

Bit 4 = SPIOD SPI output disable

This bit is used to disable the SPI output on the I/O

port (in both master or slave mode).

0: SPI output enabled

Bit 1 = SSM SS mode selection

It is set and cleared by software.

0: Normal mode - SS uses information coming

from the SS pin of the SPI.

1: SPI output disabled

(I/O pin free for general-purpose I/O)

1: I/O mode, the SPI uses the information stored

into bit SSI.

Bit 3 = P1OS PWM1 output select

This bit is used to select the output for the PWM1

channel of the ART/PWM Timer.

0: PWM1 output on PWM1 pin

1: PWM1 output on PWM1R pin and connected to

the OA2PIN pin

Bit 0 = SSI SS internal mode

This bit replaces pin SS of the SPI when bit SSM is

set to 1. (see SPI description). It is set and cleared

by software.

Note: In order to use the PC1 port pin as a PWM

output pin, bit 1 of port C must be programmed as

37/152

ST72C171

7.3 OP-AMP MODULE

7.3.1 Introduction

have a gain of 2, 4 or 8, they may be used for ex-

tending the ADC precision (analog zooming).

The ST7 Op-Amp module is designed to cover

most types of microcontroller applications where

analog signal amplifiers are used.

The 2 inverting inputs of OA1 or OA2 may be used

to achieve this function. The input impedance of

these inputs is around 2K.

It may be used to perform a a variety of functions

such as: differential voltage amplifier, comparator/

threshold detector, ADC zooming, impedance

adaptor, general purpose operational amplifier.

The ART Timer PWM resistive outputs are inter-

nally connected to OA1PIN and OA2PIN pins. The

PWM outputs are enabled by the PWMCR register

and the resistive outputs are selected by Miscella-

neous register 2. Refer to Figure 28.

7.3.2 Main features

This module includes:

The inverting input of OA1 or OA2 may be con-

nected to an I/O pin, to the analog ground or may

be left unconnected (in this case the SPGA can be

used as a repeater, with the output of the SPGA

connected to this input via the resistive loopback).

■ 2 rail-to-rail SPGAs (Software Programmable

Gain Amplifier), and 1 stand alone rail-to-rail

Op-Amp that may be externally connected using

I/O pins

■ A band gap voltage reference

■ A programmable eight-step reference voltage

7.3.3.2 Outputs

■ ART Timer PWM outputs internally connected

The SPGA outputs are connected either to exter-

nal pins or, internally, to the ADC input (Channel 8

& 9). The output value, digitized by a Schmitt trig-

ger, may be read by the application software or

may generate an interrupt.

to SPGAs input 1 and 2.

■ SPGAs and Op-Amp outputs are internally

connected to the ADC inputs (Channel 8, 9 &

10).

■ Input offset compensation

The OA3 output is connected to an ADC input

(Channel 10).

7.3.3 General description

The module contains two SPGAs (OA1 & OA2)

and 1 stand alone operational amplifier (OA3) de-

pending on the device package. OA1 and OA2

each have associated circuitry for input and gain

selection. The third operational amplifier, OA3,

without input and gain selection circuitry, is availa-

ble in some devices (see device pin out descrip-

tion).

7.3.3.3 Advanced features

The gain of OA1 or OA2 is programmed using an

internal resistive network. The possible values are:

1, 2, 4, 8 and 16. The internal resistive loopback

may also be de-activated in order to obtain the

open-loop gain (comparator) or to use the op-amp

with an external loopback network.

7.3.3.1 Inputs

Input offset compensation

The non-inverting input of OA1 or OA2 may be

connected to an I/O pin, to the band-gap reference

voltage, to an 8-step voltage reference or to the

analog ground.

In a special calibration mode (autozero mode), the

negative input pin of OA1 or OA2 can be connect-

ed internally to the positive input pin. This mode al-

lows the measurement of the input offset voltage

of the SPGA using the ADC. This value may be

stored in RAM and subsequently used for offset

correction (for ADC conversions). Refer to Section

9.3.4.

The eight-step voltage reference uses a resistive

network in order to generate two voltages between

1/8 V

and V

(in 1/8 V

steps) that can be

DD

connected to the non-inverting input of the two SP-

GAs. These voltages may be used as programma-

ble thresholds with the corresponding SPGA used

as a comparator or, with the SPGA programmed to

38/152

ST72C171

OP-AMP MODULE (Cont’d)

Figure 27. Op-Amp Module Block Diagram

NS1[2:0] bits

OA1NIN

G1[2:0] bits

15R /16R

V

SSA

R=2K

AZ1 bit

ART Timer

PWM0R

Output

R

AV =1, 2, 4, 8, 16, ∞

CL

VR1E, PS1[1:0] bits

R=2K

To ADC Channel 8

OA1PIN

OA1

OA1O

VR1[2:0] bits

x V /8

OA1V

bit

DDA

Band Gap

Reference

Voltage

8-Step Reference

Voltage 1

OA1IE bit

OA1

Interrupt

(1.2V)

NS2[2:0] bits

OA2NIN

G2[2:0] bits

15R /16R

V

SSA

R=2K

ART Timer

PWM1R

Output

R

AZ2 bit

AV =1, 2, 4, 8, 16, ∞

CL

VR2E, PS2[1:0] bits

To ADC Channel 9

OA2PIN

OA2

R=2K

OA2O

VR2[2:0] bits

x V /8

OA2V

bit

DDA

Band Gap

8-Step Reference

Voltage 2

Reference

Voltage

(1.2V)

OA2IE bit

OA2

Interrupt

To ADC Channel 10

OA3NIN

OA3PIN

OA3

OA3O

Note: OA3 is not present on some package types. Refer to the device pin description.

39/152

ST72C171

OP-AMP MODULE (Cont’d)

7.3.4 Autozero Mode

Voff =( Vo- V’o) /G

When the following description refers to both OA1

or OA2, x stands for 1 or 2.

As the offset voltage of the SPGAs may vary with

the common mode voltage value, the measure-

ment must be done choosing VRx to match the ap-

plication conditions. Alternatively, nine measure-

ments may be done with the noninverting input

In order to eliminate the ADC errors due to the

SPGA offset voltage, this voltage may be deter-

mined, prior to the A/D conversion (at power on or

periodically) and stored in RAM. The stored value

may be used afterwards to eliminate the errors of

any A/D conversion that uses the SPGA (ADC

zooming). The measurement may be done inde-

pendently for OA1 and OA2.

voltage varying between 0 and V

in 1/8 V

DDA

DD

steps, in order to fully characterise the offset volt-

age of the op-amp.

The measurement algorithm has 3 steps:

7.3.5 Comparator mode with Interrupts

1. The SPGA is in repeater mode (NSx[1:0] = 01),

with the lowest gain (Gx[2:0]=000), the autoze-

roing switch is left open (AZx = 0). The positive

input of the op-amp is connected to a DC value,

using the VRx reference voltage generator

(PSx[1:0] = 00), and the output is sent to the

ADC. Under these conditions, the ADC meas-

ures the value:

The 2 SPGAs can be configured in comparator

mode (GX[2:0]=111). In this case the positive in-

put can be connected to the internal reference

voltage. The negative input can be used to receive

the analog voltage to be compared with the volt-

age connected to the positive input.

By means of a Schmitt trigger, the SPGA output is

readable as a logical level in the OAxVR bit in the

OAIRR register. These bits are read only.

Vo = VRx -Voff

of the SPGA output.

2. Set the gain (G) according the application

requirement. The AZx bit is set to 1. The output

voltage of the SPGA becomes:

An interrupt request remains pending as long as

the output value (OAxVR) is equal to the corre-

sponding polarity bit (OAxPR) and when the inter-

rupt enable bit (OAxIE) is set. There is one inter-

rupt vector for each SPGA.

V’o = VRx - Voff - G * Voff

3.Voff calculated with 1) - 2)

40/152

ST72C171

OP-AMP MODULE (Cont’d)

This feature allows the microcontroller to be used

as a Digital to Analog converter and generating a

DC voltage on the positive input pin, so the SPGAs

may be used for the following functions:

7.3.6 DAC Function using ART Timer PWMR

Outputs

The PWMR outputs are connected to a serial re-

sistor and internally connected to the OA1PIN/

OA2PIN inputs. An external capacitor must be

connected to the PWM0R/OA1PIN and/or

PWM1R/OA2PIN pins (see Figure 28) if the

PWMR outputs are used.

– A comparator

– An amplifier of an external voltage connected to

the negative input pin (OA1NIN or OA2NIN).

– A repeater, to obtain the same voltage on the OA

output pin as on the input pin, with increased cur-

rent capability.

Figure 28. Connection of PWMR outputs to OA1 or OA2 for DAC Function

MISC2 REGISTER

P1OS

P0OS

PWMCR REGISTER

OE0

OE1

0.7K (typ)

PWM0R/OA1PIN

PWM0

R

int

C

ext

PWM/ART TIMER

OA1

P1OS

OE1

0.7K (max)

PWM1R/OA2PIN

PWM1

R

int

C

ext

OA2

OPAMP MODULE

41/152

ST72C171

OP-AMP MODULE (Cont’d)

7.3.7 Low Power Modes

Mode

Description

No effect on op-amp.

WAIT

SPGA interrupts cause the device to exit from WAIT mode.

No effect on op-amp.

SPGA interrupts cause the device to exit from HALT mode.

HALT

Note: Low Power modes have no effect on the SPGAs & the Op-Amp. They can be switched off to reduce

the power consumption of the ST7 (OAxON bits).

7.3.8 Interrupts

Enable

Control from

Bit

Exit

from

Halt

Event

Flag

Interrupt Event

Wait

Yes

Op-Amp 1 output in comparator mode equals to OA1P bit value

Op-Amp 2 output in comparator mode equals to OA2P bit value

NA*

OA1IE

OA2IE

Yes

* The interrupt event occurs when the OAxP bit equals the OAxV bit value.

Note: The SPGA interrupt events are connected to 2 interrupt vectors (see Interrupts chapter). These

events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the

CC register is reset (RIM instruction).

42/152

ST72C171

7.3.9 Register Description

Bit 1:0 = NS1[1:0] Negative Input Select.

OA1 CONTROL REGISTER (OA1CR)

Read/Write

These bits are set and reset by software and con-

trol the OA1 positive input selection.

Reset value: 0000 00000 (00h)

OA1 Negative Input

AGND

NS11

NS10

7

0

1

0

1

X

Floating - Repeater mode

OA1NIN

AZ1

G12

G11

G10

PS11 PS10 NS11 NS10

Bit 7 = AZ1 OA1 Autozero Mode.

This bit is set and reset by hardware. It enables

Autozero mode (used to measure the OA1 input

offset).

0: Autozero mode disabled

1: Autozero mode enabled

OA2 CONTROL REGISTER (OA2CR)

Read/Write

Reset value: 0000 0000 (00h)

7

0

AZ2

G22

G21

G20

PS21 PS20 NS21 NS20

Bit 6:4 = G1[2:0] Gain Control.

These bits are set and reset by software and con-

trol the OA1 gain by modifying the resistive loop-

back network. The value of the gain is adjusted to

the desired value (for inverting / non-inverting am-

plification) corresponding to the selected positive

input source - see PS1[1:0] table, Gain Adjust col-

umn.

Bit 7 = AZ2 OA2 Autozero Mode.

This bit is set and reset by hardware. It enables

Autozero mode (used to measure the OA2 input

offset).

0: Autozero mode disabled

1: Autozero mode enabled

Gain

G12

G11

G10

Bit 6:4 = G2[2:0] Gain Control.

inv / Ninv

-1 / 2

These bits are set and reset by software and con-

trol the OA2 gain by modifying the resistive loop-

back network. The value of the gain is adjusted to

the desired value (for inverting/noninverting ampli-

fication) corresponding to the selected positive in-

put source - see PS2[1:0] table, Gain Adjust col-

umn.

0

1

0

1

0

1

0

1

0

1

-2 / 3

-3 / 4

-4 / 5

-8 / 8

-16 / 16

Comparator

External Loopback

Gain

1

G22

G21

G20

inv / Ninv

-1 / 2

0

1

0

1

0

1

0

1

0

1

-2 / 3

Bit 3:2 = PS1[1:0] Positive Input Select / Gain ad-

-3 / 4

^just.

-4 / 5

These bits are set and reset by software and con-

trol the OA1 positive input selection.

-8 / 8

-16 / 16

Gain

Adj.

Comparator

External Loopback

OA1 Positive Input

PS11 PS10

1

8-step Ref.Voltage 1

OA1PIN

inv

0

1

0

1

0

ninv

inv

Band Gap Ref. Voltage (1.2V)

43/152

ST72C171

OP-AMP MODULE (Cont’d)

Bit 3:2 = PS2[1:0] Positive Input Select / Gain ad-

just.

OA3 CONTROL REGISTER

(OA3CR)

Read/Write

Reset value: 0000 0000 (00h)

These bits are set and reset by software and con-

trol the OA2 positive input selection.t

7

0

-

Gain

Adj.

OA2 Positive Input

PS21 PS20

OA3ON

-

8-step Ref.Voltage 1

OA2PIN

inv

0

1

0

1

0

1

ninv

inv

Bit 7 = OA3ON OA3 on/off (low power)

Band Gap Ref. Voltage (1.2V)

Floating

Stand Alone Op-Amp on/off control bit, it is set and

reset by software. It reduces power consumption

when reset.

ninv

0: Op-amp 3 off

1: Op-amp 3 on

Bit 1:0 = NS2[1:0] Negative Input Select.

These bits are set and reset by software and con-

trol the OA2 negative input selection.

Note: This bit must be kept cleared in devices

without OA3 (refer to device block diagram and pin

description)

OA2 Negative Input

AGND

NS21

NS20

0

1

0

1

X

Floating -Repeater mode

OA2NIN

Bit 6:0 = Reserved.

44/152

ST72C171

OP-AMP MODULE (Cont’d)

OP-AMP INTERRUPT AND READOUT REGIS-

TER (OAIRR)

Read/Write*

Bit 3 = OA2IE OA2 interrupt enable

This bit is set and reset by software. When it is set,

it enables an interrupt to be generated if the OA2P

bit and the OA2V bit have the same value.

0: OA2 interrupt disabled

Reset value: 0000 0000 (00h)

7

0

OA1IE OA1P OA1V OA1ON OA2IE OA2P OA2V OA2ON

1: OA2 interrupt enabled

Bit 7 = OA1IE OA1 interrupt enable

This bit is set and reset by software. When it is set,

it enables an interrupt to be generated if the OA1P

bit and the OA1V bit have the same value.

0: OA1 interrupt disabled

Bit 2 = OA2P OA2 interrupt polarity select

This bit is set and reset by software. It specifies the

OA2 SPGA output level which will generate an in-

terrupt if the bit OA2IE is set.

0: Active low

1: OA1 interrupt enabled

1: Active high

Bit 6 = OA1P OA1 interrupt polarity select

This bit is set and reset by software. It specifies the

OA1 SPGA output level which will generate an in-

terrupt if the bit OA1IE is set.

0: Active low

1: Active high

Bit 1- OA2V OA2 output value (read only)

This bit is set and reset by hardware. It contains

the OA2 SPGA output voltage value filtered by a

Schmitt trigger.

0: OA2+ voltage < OA2- voltage

1: OA2+ voltage > OA2- voltage

Bit 5 = OA1V OA1 output value (read only)

This bit is set and reset by hardware. It contains

the OA1 SPGA output voltage value filtered by a

Schmitt trigger.

Bit 0 - OA2ON OA2 on/off (low power)

0: Op-amp 2 off (reducing power consumption)

1: Op-amp 2 on

0: OA1+ voltage < OA1- voltage

1: OA1+ voltage > OA1- voltage

Note: If OA1ON, OA2ON and OA3ON are 0, The

entire module is disabled, giving the lowest power

consumption.

Bit 4 = OA1ON OA1 on/off (low power)

* OA1V and OA2V are read only.

This bit is set and reset by software. It reduces

power consumption when reset.

0: Op-amp 1 off

1: Op-amp 1 on

45/152

ST72C171

OP-AMP MODULE (Cont’d)

VOLTAGE REFERENCE CONTROL REGISTER

(OAVRCR)

Read/Write

Bit 3= VR1E VR1 Enable

This bit is set and reset by software. When the ref-

ererence voltage is selected (PS1[1:0] = 00 in the

Reset value: 0000 0000 (00h)

OA1CR register) it connects V

or Reference Voltage 1 (VR1) to the OA1 positive

input.

(analog ground)

SSA

7

0

0: OA1 positive input is connected to V

1: OA1 positive input is connected to VR1 voltage

value

SSA

VR2E VR22 VR21 VR20 VR1E VR12 VR11 VR10

Bit 7 = VR2E: VR2 Enable

This bit is set and reset by software. When the ref-

ererence voltage is selected (PS2[1:0] = 00 in the

Bit 2:0 - VR1[2:0] Voltage selection for channel 1

of the 8-step reference voltage

OA2CR register) it connects V

(analog ground)

SSA

or Reference Voltage 2 (VR2) to the OA2 positive

input.

These bits are set and reset by software, they

specify the Reference Voltage 1 (VR1) connected

to the OA1 positive input when PS1[1:0] = 00 in

the OA1CR register.

0: OA2 positive input is connected to V

SSA

1: OA2 positive input is connected to VR2 voltage

value

Reference

VR1E

VR12

VR11

VR10

Voltage 1

Bit 6:4 = VR2[2:0] Voltage selection for channel 2

of the 8-step reference voltage

These bits are set and reset by software, they

specify the Reference Voltage 2 (VR2) connected

to the OA2 positive input when PS2[1:0] = 00 in

the OA2CR register..

0 (V

)

0

1

x

0

1

x

0

1

0

1

x

0

1

0

1

0

1

SSA

V

/8

DDA

2 x V

3 x V

4 x V

5 x V

6 x V

7 x V

/8

DDA

/8

Reference

Voltage 2

VR2E

VR22

VR21

VR20

0 (V

)

0

1

x

0

1

x

0

1

0

1

x

0

1

0

1

0

1

0

1

SSA

V

/8

DDA

2 x V

3 x V

4 x V

5 x V

6 x V

7 x V

/8

DDA

Note: When both VR2E and VR1E are reset, the

8-step voltage reference cell is disabled and en-

ters low power mode.

V

46/152

ST72C171

Table 11. OP-AMP Module Register Map and Reset Values

Address

(Hex.)

Register

Label

7

6

5

4

3

2

1

0

OA1CR

AZ1

0

G12

0

G11

0

G10

0

PS11

0

PS10

0

NS11

0

NS10

0

001Bh

001Ch

001Dh

001Eh

001Fh

Reset Value

OA2CR

AZ2

0

G22

0

G21

0

G20

0

PS21

0

PS20

0

NS21

0

NS20

0

Reset Value

OA3CR

OA3ON

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

Reset Value

OIRR

OA1IE

0

OA1P

0

OA1V

0

OA2ON

0

OA2IE

0

OA2P

0

OA2V

0

OA1ON

0

Reset Value

VRCR

VR2E

0

VR22

0

VR21

0

VR20

0

VR1E

0

VR12

0

VR11

0

VR10

0

Reset Value

47/152

ST72C171

7.4 WATCHDOG TIMER (WDG)

7.4.1 Introduction

cles, and the length of the timeout period can be

programmed by the user in 64 increments.

The Watchdog timer is used to detect the occur-

rence of a software fault, usually generated by ex-

ternal interference or by unforeseen logical condi-

tions, which causes the application program to

abandon its normal sequence. The Watchdog cir-

cuit generates an MCU reset on expiry of a pro-

grammed time period, unless the program refresh-

es the counter’s contents before the T6 bit be-

comes cleared.

If the watchdog is activated (the WDGA bit is set)

and when the 7-bit timer (bits T6:T0) rolls over

from 40h to 3Fh (T6 becomes cleared), it initiates

a reset cycle pulling low the reset pin for typically

500ns.

The application program must write in the CR reg-

ister at regular intervals during normal operation to

prevent an MCU reset. The value to be stored in

the CR register must be between FFh and C0h

(see Table 13 . Watchdog Timing (fCPU = 8

MHz)):

7.4.2 Main Features

■ Programmable timer (64 increments of 12288

CPU cycles)

– The WDGA bit is set (watchdog enabled)

■ Programmable reset

– The T6 bit is set to prevent generating an imme-

diate reset

■ Reset (if watchdog activated) when the T6 bit

reaches zero

■ Optional

reset

on

HALT

instruction

– The T5:T0 bits contain the number of increments

which represents the time delay before the

watchdog produces a reset.

(configurable by option byte)

■ Hardware Watchdog selectable by option byte.

7.4.3 Functional Description

The counter value stored in the CR register (bits

T6:T0), is decremented every 12,288 machine cy-

Figure 29. Watchdog Block Diagram

RESET

WATCHDOG CONTROL REGISTER (CR)

T5

WDGA T6

T1

T0

T4

T2

T3

7-BIT DOWNCOUNTER

CLOCK DIVIDER

f

CPU

÷12288

48/152

ST72C171

WATCHDOG TIMER (Cont’d)

Table 12. Watchdog Timing (f

= 8 MHz)

reset immediately after waking up the microcon-

troller.

CPU

CR Register

initial value

WDG timeout period

(ms)

– When using an external interrupt to wake up the

microcontroller, reinitialize the corresponding I/O

as “Input Pull-up with Interrupt” before executing

the HALT instruction. The main reason for this is

that the I/O may be wrongly configured due to ex-

ternal interference or by an unforeseen logical

condition.

Max

Min

FFh

C0h

98.304

1.536

Notes: Following a reset, the watchdog is disa-

bled. Once activated it cannot be disabled, except

by a reset.

– For the same reason, reinitialize the level sensi-

tiveness of each external interrupt as a precau-

tionary measure.

The T6 bit can be used to generate a software re-

set (the WDGA bit is set and the T6 bit is cleared).

– The opcode for the HALT instruction is 0x8E. To

avoid an unexpected HALT instruction due to a

program counter failure, it is advised to clear all

occurrences of the data value 0x8E from memo-

ry. For example, avoid defining a constant in

ROM with the value 0x8E.

7.4.4 Hardware Watchdog Option

If Hardware Watchdog is selected by option byte,

the watchdog is always active and the WDGA bit in

the CR is not used.

– As the HALT instruction clears the I bit in the CC

register to allow interrupts, the user may choose

to clear all pending interrupt bits before execut-

ing the HALT instruction. This avoids entering

other peripheral interrupt routines after executing

the external interrupt routine corresponding to

the wake-up event (reset or external interrupt).

Refer to the device-specific Option Byte descrip-

tion.

7.4.5 Low Power Modes

WAIT Instruction

No effect on Watchdog.

HALT Instruction

7.4.6 Interrupts

If the Watchdog reset on HALT option is selected

by option byte, a HALT instruction causes an im-

mediate reset generation if the Watchdog is acti-

vated (WDGA bit is set).

None.

7.4.7 Register Description

CONTROL REGISTER (CR)

Read/Write

7.4.5.1 Using Halt Mode with the WDG (option)

If the Watchdog reset on HALT option is not se-

lected by option byte, the Halt mode can be used

when the watchdog is enabled.

Reset Value: 0111 1111 (7Fh)

7

0

In this case, the HALT instruction stops the oscilla-

tor. When the oscillator is stopped, the WDG stops

counting and is no longer able to generate a reset

until the microcontroller receives an external inter-

rupt or a reset.

WDGA T6

T5

T4

T3

T2

T1

T0

Bit 7 = WDGA Activation bit.

This bit is set by software and only cleared by

hardware after a reset. When WDGA = 1, the

watchdog can generate a reset.

0: Watchdog disabled

1: Watchdog enabled

If an external interrupt is received, the WDG re-

starts counting after 4096 CPU clocks. If a reset is

generated, the WDG is disabled (reset state).

Recommendations

– Make sure that an external event is available to

wake up the microcontroller from Halt mode.

Bit 6:0 = T[6:0] 7-bit timer (MSB to LSB).

These bits contain the decremented value. A reset

is produced when it rolls over from 40h to 3Fh (T6

becomes cleared).

– Before executing the HALT instruction, refresh

the WDG counter, to avoid an unexpected WDG

49/152

ST72C171

WATCHDOG TIMER (Cont’d)

Table 13. WDG Register Map

Address

(Hex.)

Register

Name

7

6

5

4

3

2

1

0

CR

24

WDGA

0

T6

1

T5

1

T4

1

T3

1

T2

1

T1

1

T0

1

Reset Value

50/152

ST72C171

7.5 16-BIT TIMER

7.5.1 Introduction

7.5.3 Functional Description

7.5.3.1 Counter

The timer consists of a 16-bit free-running counter

driven by a programmable prescaler.

The main block of the Programmable Timer is a

16-bit free running upcounter and its associated

16-bit registers. The 16-bit registers are made up

of two 8-bit registers called high & low.

It may be used for a variety of purposes, including

measuring the pulse lengths of up to two input sig-

nals (input capture) or generating up to two output

waveforms (output compare and PWM).

Counter Register (CR):

Pulse lengths and waveform periods can be mod-

ulated from a few microseconds to several milli-

seconds using the timer prescaler and the CPU

clock prescaler.

– Counter High Register (CHR) is the most sig-

nificant byte (MS Byte).

– Counter Low Register (CLR) is the least sig-

nificant byte (LS Byte).

Some ST7 devices have two on-chip 16-bit timers.

They are completely independent, and do not

share any resources. They are synchronized after

a MCU reset as long as the timer clock frequen-

cies are not modified.

Alternate Counter Register (ACR)

– Alternate Counter High Register (ACHR) is the

most significant byte (MS Byte).

– Alternate Counter Low Register (ACLR) is the

least significant byte (LS Byte).

This description covers one or two 16-bit timers. In

ST7 devices with two timers, register names are

prefixed with TA (Timer A) or TB (Timer B).

These two read-only 16-bit registers contain the

same value but with the difference that reading the

ACLR register does not clear the TOF bit (Timer

overflow flag), located in the Status register (SR).

(See note at the end of paragraph titled 16-bit read

sequence).

7.5.2 Main Features

■ Programmableprescaler:f_CPUdividedby2, 4or8.

■ Overflow status flag and maskable interrupt

■ External clock input (must be at least 4 times

slowerthan theCPUclockspeed)with thechoice

of active edge

■ Output compare functions with:

– 2 dedicated 16-bit registers

– 2 dedicated programmable signals

– 2 dedicated status flags

Writing in the CLR register or ACLR register resets

the free running counter to the FFFCh value.

Both counters have a reset value of FFFCh (this is

the only value which is reloaded in the 16-bit tim-

er). The reset value of both counters is also

FFFCh in One Pulse mode and PWM mode.

The timer clock depends on the clock control bits

of the CR2 register, as illustrated in Table 1. The

value in the counter register repeats every

131.072, 262.144 or 524.288 CPU clock cycles

depending on the CC[1:0] bits.

– 1 dedicated maskable interrupt

■ Input capture functions with:

– 2 dedicated 16-bit registers

– 2 dedicated active edge selection signals

– 2 dedicated status flags

The timer frequency can be f

or an external frequency.

/2, f

/4, f

/8

CPU

– 1 dedicated maskable interrupt

■ Pulse Width Modulation mode (PWM)

■ One Pulse mode

■ 5 alternate functionson I/O ports (ICAP1, ICAP2,

OCMP1, OCMP2, EXTCLK)*

The Block Diagram is shown in Figure 1.

*Note: Some timer pins may not be available (not

bonded) in some ST7 devices. Refer to the device

pin out description.

When reading an input signal on a non-bonded

pin, the value will always be ‘1’.

51/152

ST72C171

16-BIT TIMER (Cont’d)

Figure 30. Timer Block Diagram

ST7 INTERNAL BUS

f

CPU

MCU-PERIPHERAL INTERFACE

8 low

8-bit

8 high

8

buffer

h

EXEDG

g

w

g

w

g

w

g

low

16

INPUT

CAPTURE

REGISTER

INPUT

CAPTURE

REGISTER

OUTPUT

COMPARE

REGISTER

OUTPUT

COMPARE

REGISTER

1/2

1/4

1/8

COUNTER

REGISTER

1

2

ALTERNATE

COUNTER

REGISTER

EXTCLK

16

CC[1:0]

TIMER INTERNAL BUS

16 16

OVERFLOW

DETECT

EDGE DETECT

CIRCUIT1

OUTPUT COMPARE

CIRCUIT

ICAP1

CIRCUIT

6

EDGE DETECT

CIRCUIT2

ICAP2

OCMP1

LATCH1

LATCH2

ICF1 OCF1 TOF ICF2 OCF2

0

OCMP2

(Status Register) SR

EXEDG

ICIE OCIE TOIE FOLV2 FOLV1OLVL2 IEDG1 OLVL1

OC1E

OPM PWM CC1 CC0 IEDG2

OC2E

(Control Register 1) CR1

(Control Register 2) CR2

(See note)

Note: If IC, OC and TO interrupt requests have separate vectors

then the last OR is not present (See device Interrupt Vector Table)

TIMER INTERRUPT

52/152

ST72C171

16-BIT TIMER (Cont’d)

16-bit Read Sequence: (from either the Counter

Register or the Alternate Counter Register).

Clearing the overflow interrupt request is done in

two steps:

1. Reading the SR register while the TOF bit is set.

2. An access (read or write) to the CLR register.

Beginning of the sequence

Read

LS Byte

is buffered

Note: The TOF bit is not cleared by accessing the

ACLR register. The advantage of accessing the

ACLR register rather than the CLR register is that

it allows simultaneous use of the overflow function

and reading the free running counter at random

times (for example, to measure elapsed time) with-

out the risk of clearing the TOF bit erroneously.

MS Byte

At t0

Other

instructions

Returns the buffered

LS Byte value at t0

Read

LS Byte

At t0 +∆t

The timer is not affected by WAIT mode.

In HALT mode, the counter stops counting until the

mode is exited. Counting then resumes from the

previous count (MCU awakened by an interrupt) or

from the reset count (MCU awakened by a Reset).

Sequence completed

The user must read the MS Byte first, then the LS

Byte value is buffered automatically.

This buffered value remains unchanged until the

16-bit read sequence is completed, even if the

user reads the MS Byte several times.

7.5.3.2 External Clock

The external clock (where available) is selected if

CC0=1 and CC1=1 in the CR2 register.

After a complete reading sequence, if only the

CLR register or ACLR register are read, they re-

turn the LS Byte of the count value at the time of

the read.

The status of the EXEDG bit in the CR2 register

determines the type of level transition on the exter-

nal clock pin EXTCLK that will trigger the free run-

ning counter.

Whatever the timer mode used (input capture, out-

put compare, One Pulse mode or PWM mode) an

overflow occurs when the counter rolls over from

FFFFh to 0000h then:

The counter is synchronised with the falling edge

of the internal CPU clock.

A minimum of four falling edges of the CPU clock

must occur between two consecutive active edges

of the external clock; thus the external clock fre-

quency must be less than a quarter of the CPU

clock frequency.

– The TOF bit of the SR register is set.

– A timer interrupt is generated if:

– TOIE bit of the CR1 register is set and

– I bit of the CC register is cleared.

If one of these conditions is false, the interrupt re-

mains pending to be issued as soon as they are

both true.

53/152

ST72C171

16-BIT TIMER (Cont’d)

Figure 31. Counter Timing Diagram, internal clock divided by 2

CPU CLOCK

INTERNAL RESET

TIMER CLOCK

FFFD FFFE FFFF 0000 0001 0002 0003

COUNTER REGISTER

TIMER OVERFLOW FLAG (TOF)

Figure 32. Counter Timing Diagram, internal clock divided by 4

CPU CLOCK

INTERNAL RESET

TIMER CLOCK

FFFC

FFFD

0000

0001

COUNTER REGISTER

TIMER OVERFLOW FLAG (TOF)

Figure 33. Counter Timing Diagram, internal clock divided by 8

CPU CLOCK

INTERNAL RESET

TIMER CLOCK

0000

FFFC

FFFD

COUNTER REGISTER

TIMER OVERFLOW FLAG (TOF)

Note: The MCU is in reset state when the internal reset signal is high. When it is low, the MCU is running.

54/152

ST72C171

16-BIT TIMER (Cont’d)

7.5.3.3 Input Capture

When an input capture occurs:

In this section, the index, i, may be 1 or 2 because

there are 2 input capture functions in the 16-bit

timer.

– The ICFi bit is set.

– The ICiR register contains the value of the free

running counter on the active transition on the

ICAPi pin (see Figure 6).

The two input capture 16-bit registers (IC1R and

IC2R) are used to latch the value of the free run-

ning counter after a transition is detected by the

ICAPi pin (see figure 5).

– A timer interrupt is generated if the ICIE bit is set

and the I bit is cleared in the CC register. Other-

wise, the interrupt remains pending until both

conditions become true.

MS Byte

ICiHR

LS Byte

ICiLR

ICiR

Clearing the Input Capture interrupt request (i.e.

clearing the ICFi bit) is done in two steps:

The ICiR register is a read-only register.

1. Reading the SR register while the ICFi bit is set.

2. An access (read or write) to the ICiLR register.

The active transition is software programmable

through the IEDGi bit of Control Registers (CRi).

Timing resolution is one count of the free running

Notes:

counter: (f

/CC[1:0]).

CPU

1. After reading the ICiHR register, the transfer of

input capture data is inhibited and ICFi will

never be set until the ICiLR register is also

read.

Procedure:

To use the input capture function, select the fol-

lowing in the CR2 register:

2. The ICiR register contains the free running

counter value which corresponds to the most

recent input capture.

– Select the timer clock (CC[1:0]) (see Table 1).

– Select the edge of the active transition on the

ICAP2 pin with the IEDG2 bit (the ICAP2 pin

must be configured as a floating input).

3. The 2 input capture functions can be used

together even if the timer also uses the 2 output

compare functions.

And select the following in the CR1 register:

4. In One Pulse mode and PWM mode only the

input capture 2 function can be used.

– Set the ICIE bit to generate an interrupt after an

input capture coming from either the ICAP1 pin

or the ICAP2 pin

5. The alternate inputs (ICAP1 & ICAP2) are

always directly connected to the timer. So any

transitions on these pins activate the input cap-

ture function.

– Select the edge of the active transition on the

ICAP1 pin with the IEDG1 bit (the ICAP1pin must

be configured as a floating input).

Moreover if one of the ICAPi pin is configured

as an input and the second one as an output,

an interrupt can be generated if the user tog-

gles the output pin and if the ICIE bit is set.

This can be avoided if the input capture func-

tion i is disabled by reading the ICiHR (see note

1).

6. The TOF bit can be used with an interrupt in

order to measure events that exceed the timer

range (FFFFh).

55/152

ST72C171

16-BIT TIMER (Cont’d)

Figure 34. Input Capture Block Diagram

ICAP1

(Control Register 1) CR1

IEDG1

EDGE DETECT

CIRCUIT2

EDGE DETECT

CIRCUIT1

ICIE

ICAP2

(Status Register) SR

ICF1

ICF2

0

IC2R Register

IC1R Register

(Control Register 2) CR2

16-BIT

16-BIT FREE RUNNING

IEDG2

CC0

CC1

COUNTER

Figure 35. Input Capture Timing Diagram

TIMER CLOCK

FF01

FF02

FF03

COUNTER REGISTER

ICAPi PIN

ICAPi FLAG

FF03

ICAPi REGISTER

Note: Active edge is rising edge.

56/152

ST72C171

16-BIT TIMER (Cont’d)

7.5.3.4 Output Compare

– The OCMPi pin takes OLVLi bit value (OCMPi

pin latch is forced low during reset).

In this section, the index, i, may be 1 or 2 because

there are 2 output compare functions in the 16-bit

timer.

– A timer interrupt is generated if the OCIE bit is

set in the CR2 register and the I bit is cleared in

the CC register (CC).

This function can be used to control an output

waveform or indicate when a period of time has

elapsed.

The OCiR register value required for a specific tim-

ing application can be calculated using the follow-

ing formula:

When a match is found between the Output Com-

pare register and the free running counter, the out-

put compare function:

– Assigns pins with a programmable value if the

OCIE bit is set

∆t f

* CPU

PRESC

∆ OCiR =

– Sets a flag in the status register

– Generates an interrupt if enabled

Where:

∆t

= Output compare period (in seconds)

= CPU clock frequency (in hertz)

Two 16-bit registers Output Compare Register 1

(OC1R) and Output Compare Register 2 (OC2R)

contain the value to be compared to the counter

register each timer clock cycle.

f

CPU

PRESC

= Timer prescaler factor (2, 4 or 8 de-

pending on CC[1:0] bits, see Table 1)

MS Byte

OCiHR

LS Byte

OCiLR

OCiR

If the timer clock is an external clock, the formula

is:

These registers are readable and writable and are

not affected by the timer hardware. A reset event

changes the OCiR value to 8000h.

∆ OCiR = ∆t f

* EXT

Where:

Timing resolution is one count of the free running

∆t

= Output compare period (in seconds)

= External timer clock frequency (in hertz)

counter: (f

).

CC[1:0]

CPU/

f

EXT

Procedure:

Clearing the output compare interrupt request (i.e.

clearing the OCFi bit) is done by:

To use the output compare function, select the fol-

lowing in the CR2 register:

1. Reading the SR register while the OCFi bit is

– Set the OCiE bit if an output is needed then the

OCMPi pin is dedicated to the output compare i

signal.

set.

2. An access (read or write) to the OCiLR register.

– Select the timer clock (CC[1:0]) (see Table 1).

And select the following in the CR1 register:

The following procedure is recommended to pre-

vent the OCFi bit from being set between the time

it is read and the write to the OCiR register:

– Select the OLVLi bit to applied to the OCMPi pins

after the match occurs.

– Write to the OCiHR register (further compares

are inhibited).

– Set the OCIE bit to generate an interrupt if it is

needed.

– Read the SR register (first step of the clearance

of the OCFi bit, which may be already set).

When a match is found between OCRi register

and CR register:

– Write to the OCiLR register (enables the output

compare function and clears the OCFi bit).

– OCFi bit is set.

57/152

ST72C171

16-BIT TIMER (Cont’d)

Notes:

Forced Compare Output capability

1. After a processor write cycle to the OCiHR reg-

ister, the output compare function is inhibited

until the OCiLR register is also written.

When the FOLVi bit is set by software, the OLVLi

bit is copied to the OCMPi pin. The OLVi bit has to

be toggled in order to toggle the OCMPi pin when

it is enabled (OCiE bit=1). The OCFi bit is then not

set by hardware, and thus no interrupt request is

generated.

2. If the OCiE bit is not set, the OCMPi pin is a

general I/O port and the OLVLi bit will not

appear when a match is found but an interrupt

could be generated if the OCIE bit is set.

FOLVLi bits have no effect in either One-Pulse

mode or PWM mode.

3. When the timer clock is f

/2, OCFi and

CPU

OCMPi are set while the counter value equals

the OCiR register value (see Figure 8). This

behaviour is the same in OPM or PWM mode.

When the timer clock is f

/4, f

/8 or in

CPU

external clock mode, OCFi and OCMPi are set

while the counter value equals the OCiR regis-

ter value plus 1 (see Figure 9).

4. The output compare functions can be used both

for generating external events on the OCMPi

pins even if the input capture mode is also

used.

5. The value in the 16-bit OCiR register and the

OLVi bit should be changed after each suc-

cessful comparison in order to control an output

waveform or establish a new elapsed timeout.

Figure 36. Output Compare Block Diagram

16 BIT FREE RUNNING

OC1E

CC1 CC0

OC2E

COUNTER

(Control Register 2) CR2

16-bit

(Control Register 1) CR1

OUTPUT COMPARE

CIRCUIT

Latch

1

FOLV2 FOLV1

OCIE

OLVL2

OLVL1

OCMP1

16-bit

Latch

2

OCMP2

OC1R Register

OCF1

OCF2

0

OC2R Register

(Status Register) SR

58/152

ST72C171

16-BIT TIMER (Cont’d)

Figure 37. Output Compare Timing Diagram, f

=f

/2

CPU

TIMER

INTERNAL CPU CLOCK

TIMER CLOCK

COUNTER REGISTER

2ECF 2ED0 2ED1 2ED2

2ED3

2ED4

2ED3

OUTPUT COMPARE REGISTER i (OCRi)

OUTPUT COMPARE FLAG i (OCFi)

OCMPi PIN (OLVLi=1)

Figure 38. Output Compare Timing Diagram, f

=f

/4

CPU

TIMER

INTERNAL CPU CLOCK

TIMER CLOCK

2ECF 2ED0 2ED1 2ED2

2ED3

2ED4

2ED3

COUNTER REGISTER

OUTPUT COMPARE REGISTER i (OCRi)

COMPARE REGISTER i LATCH

OUTPUT COMPARE FLAG i (OCFi)

OCMPi PIN (OLVLi=1)

59/152

ST72C171

16-BIT TIMER (Cont’d)

7.5.3.5 One Pulse Mode

Clearing the Input Capture interrupt request (i.e.

clearing the ICFi bit) is done in two steps:

One Pulse mode enables the generation of a

pulse when an external event occurs. This mode is

selected via the OPM bit in the CR2 register.

1. Reading the SR register while the ICFi bit is set.

2. An access (read or write) to the ICiLR register.

The One Pulse mode uses the Input Capture1

function and the Output Compare1 function.

The OC1R register value required for a specific

timing application can be calculated using the fol-

lowing formula:

Procedure:

t _*f

To use One Pulse mode:

CPU

- 5

OCiR Value =

1. Load the OC1R register with the value corre-

sponding to the length of the pulse (see the for-

mula in the opposite column).

PRESC

Where:

t

= Pulse period (in seconds)

2. Select the following in the CR1 register:

f

= CPU clock frequency (in hertz)

CPU

PRESC

– Using the OLVL1 bit, select the level to be ap-

plied to the OCMP1 pin after the pulse.

= Timer prescaler factor (2, 4 or 8 depend-

ing on the CC[1:0] bits, see Table 1)

– Using the OLVL2 bit, select the level to be ap-

plied to the OCMP1 pin during the pulse.

If the timer clock is an external clock the formula is:

OCiR = t f

-5

– Select the edge of the active transition on the

ICAP1 pin with the IEDG1 bit (the ICAP1 pin

must be configured as floating input).

* EXT

Where:

t

= Pulse period (in seconds)

3. Select the following in the CR2 register:

f

= External timer clock frequency (in hertz)

EXT

– Set the OC1E bit, the OCMP1 pin is then ded-

icated to the Output Compare 1 function.

– Set the OPM bit.

When the value of the counter is equal to the value

of the contents of the OC1R register, the OLVL1

bit is output on the OCMP1 pin (see Figure 10).

– Select the timer clock CC[1:0] (see Table 1).

One Pulse mode cycle

Notes:

1. The OCF1 bit cannot be set by hardware in

One Pulse mode but the OCF2 bit can generate

an Output Compare interrupt.

When

OCMP1 = OLVL2

event occurs

on ICAP1

Counter is reset

2. When the Pulse Width Modulation (PWM) and

One Pulse mode (OPM) bits are both set, the

PWM mode is the only active one.

to FFFCh

ICF1 bit is set

3. If OLVL1=OLVL2 a continuous signal will be

seen on the OCMP1 pin.

When

Counter

OCMP1 = OLVL1

= OC1R

4. The ICAP1 pin can not be used to perform input

capture. The ICAP2 pin can be used to perform

input capture (ICF2 can be set and IC2R can be

loaded) but the user must take care that the

counter is reset each time a valid edge occurs

on the ICAP1 pin and ICF1 can also generates

interrupt if ICIE is set.

Then, on a valid event on the ICAP1 pin, the coun-

ter is initialized to FFFCh and the OLVL2 bit is

loaded on the OCMP1 pin, the ICF1 bit is set and

the value FFFDh is loaded in the IC1R register.

Because the ICF1 bit is set when an active edge

occurs, an interrupt can be generated if the ICIE

bit is set.

5. When One Pulse mode is used OC1R is dedi-

cated to this mode. Nevertheless OC2R and

OCF2 can be used to indicate that a period of

time has elapsed but cannot generate an output

waveform because the OLVL2 level is dedi-

cated to One Pulse mode.

60/152

ST72C171

16-BIT TIMER (Cont’d)

Figure 39. One Pulse Mode Timing Example

FFFC FFFD FFFE

COUNTER

2ED0 2ED1 2ED2

2ED3

FFFC FFFD

ICAP1

OLVL2

OLVL1

OLVL2

OCMP1

compare1

Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1

Figure 40. Pulse Width Modulation Mode Timing Example

2ED0 2ED1 2ED2

34E2 FFFC

FFFC FFFD FFFE

34E2

COUNTER

OCMP1

OLVL2

OLVL1

OLVL2

compare2

compare1

compare2

Note: OC1R=2ED0h, OC2R=34E2, OLVL1=0, OLVL2= 1

61/152

ST72C171

16-BIT TIMER (Cont’d)

7.5.3.6 Pulse Width Modulation Mode

Pulse Width Modulation (PWM) mode enables the

generation of a signal with a frequency and pulse

length determined by the value of the OC1R and

OC2R registers.

The OCiR register value required for a specific tim-

ing application can be calculated using the follow-

ing formula:

t _*f

CPU

PRESC

- 5

OCiR Value =

The Pulse Width Modulation mode uses the com-

plete Output Compare 1 function plus the OC2R

register, and so these functions cannot be used

when the PWM mode is activated.

Where:

t

= Signal or pulse period (in seconds)

= CPU clock frequency (in hertz)

f

Procedure

CPU

= Timer prescaler factor (2, 4 or 8 depend-

ing on CC[1:0] bits, see Table 1)

To use Pulse Width Modulation mode:

PRESC

1. Load the OC2R register with the value corre-

sponding to the period of the signal using the

formula in the opposite column.

If the timer clock is an external clock the formula is:

OCiR = t f

-5

* EXT

2. Load the OC1R register with the value corre-

sponding to the period of the pulse if OLVL1=0

and OLVL2=1, using the formula in the oppo-

site column.

Where:

t

= Signal or pulse period (in seconds)

f

= External timer clock frequency (in hertz)

EXT

3. Select the following in the CR1 register:

– Using the OLVL1 bit, select the level to be ap-

plied to the OCMP1 pin after a successful

comparison with OC1R register.

The Output Compare 2 event causes the counter

to be initialized to FFFCh (See Figure 11)

Notes:

– Using the OLVL2 bit, select the level to be ap-

plied to the OCMP1 pin after a successful

comparison with OC2R register.

1. After a write instruction to the OCiHR register,

the output compare function is inhibited until the

OCiLR register is also written.

4. Select the following in the CR2 register:

2. The OCF1 and OCF2 bits cannot be set by

hardware in PWM mode, therefore the Output

Compare interrupt is inhibited.

– Set OC1E bit: the OCMP1 pin is then dedicat-

ed to the output compare 1 function.

– Set the PWM bit.

3. The ICF1 bit is set by hardware when the coun-

ter reaches the OC2R value and can produce a

timer interrupt if the ICIE bit is set and the I bit is

cleared.

– Select the timer clock (CC[1:0]) (see Table 1).

If OLVL1=1 and OLVL2=0, the length of the posi-

tive pulse is the difference between the OC2R and

OC1R registers.

4. In PWM mode the ICAP1 pin can not be used

to perform input capture because it is discon-

nected from the timer. The ICAP2 pin can be

used to perform input capture (ICF2 can be set

and IC2R can be loaded) but the user must

take care that the counter is reset after each

period and ICF1 can also generate an interrupt

if ICIE is set.

If OLVL1=OLVL2 a continuous signal will be seen

on the OCMP1 pin.

Pulse Width Modulation cycle

When

Counter

= OC1R

OCMP1 = OLVL1

5. When the Pulse Width Modulation (PWM) and

One Pulse mode (OPM) bits are both set, the

PWM mode is the only active one.

OCMP1 = OLVL2

When

Counter

= OC2R

Counter is reset

to FFFCh

ICF1 bit is set

62/152

ST72C171

16-BIT TIMER (Cont’d)

7.5.4 Low Power Modes

Mode

Description

No effect on 16-bit Timer.

Timer interrupts cause the device to exit from WAIT mode.

WAIT

HALT

16-bit Timer registers are frozen.

In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous

count when the MCU is woken up by an interrupt with “exit from HALT mode” capability or from the counter

reset value when the MCU is woken up by a RESET.

If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is armed. Consequent-

ly, when the MCU is woken up by an interrupt with “exit from HALT mode” capability, the ICFi bit is set, and

the counter value present when exiting from HALT mode is captured into the ICiR register.

7.5.5 Interrupts

Enable

Control from

Bit

Exit

from

Halt

Event

Flag

Interrupt Event

Wait

Yes

Input Capture 1 event/Counter reset in PWM mode

Input Capture 2 event

ICF1

ICF2

No

ICIE

Output Compare 1 event (not available in PWM mode)

Output Compare 2 event (not available in PWM mode)

Timer Overflow event

OCF1

OCF2

TOF

OCIE

TOIE

Note: The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts chap-

ter). These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt

mask in the CC register is reset (RIM instruction).

7.5.6 Summary of Timer modes

AVAILABLE RESOURCES

MODES

Input Capture 1

Input Capture 2

Yes

Output Compare 1 Output Compare 2

Input Capture (1 and/or 2)

Output Compare (1 and/or 2)

One Pulse mode

Yes

No

Yes

No

Yes

1)

3)

2)

Not Recommended

Partially

No

PWM Mode

No

1)

2)

3)

See note 4 in Section 0.1.3.5 One Pulse Mode

See note 5 in Section 0.1.3.5 One Pulse Mode

See note 4 in Section 0.1.3.6 Pulse Width Modulation Mode

63/152

ST72C171

16-BIT TIMER (Cont’d)

7.5.7 Register Description

Bit 4 = FOLV2 Forced Output Compare 2.

This bit is set and cleared by software.

0: No effect on the OCMP2 pin.

1:Forces the OLVL2 bit to be copied to the

OCMP2 pin, if the OC2E bit is set and even if

there is no successful comparison.

Each Timer is associated with three control and

status registers, and with six pairs of data registers

(16-bit values) relating to the two input captures,

the two output compares, the counter and the al-

ternate counter.

Bit 3 = FOLV1 Forced Output Compare 1.

This bit is set and cleared by software.

0: No effect on the OCMP1 pin.

CONTROL REGISTER 1 (CR1)

Read/Write

1: Forces OLVL1 to be copied to the OCMP1 pin, if

the OC1E bit is set and even if there is no suc-

cessful comparison.

Reset Value: 0000 0000 (00h)

7

0

ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1

Bit 2 = OLVL2 Output Level 2.

This bit is copied to the OCMP2 pin whenever a

successful comparison occurs with the OC2R reg-

ister and OCxE is set in the CR2 register. This val-

ue is copied to the OCMP1 pin in One Pulse mode

and Pulse Width Modulation mode.

Bit 7 = ICIE Input Capture Interrupt Enable.

0: Interrupt is inhibited.

1: A timer interrupt is generated whenever the

ICF1 or ICF2 bit of the SR register is set.

Bit 1 = IEDG1 Input Edge 1.

Bit 6 = OCIE Output Compare Interrupt Enable.

0: Interrupt is inhibited.

1: A timer interrupt is generated whenever the

OCF1 or OCF2 bit of the SR register is set.

This bit determines which type of level transition

on the ICAP1 pin will trigger the capture.

0: A falling edge triggers the capture.

1: A rising edge triggers the capture.

Bit 5 = TOIE Timer Overflow Interrupt Enable.

0: Interrupt is inhibited.

1: A timer interrupt is enabled whenever the TOF

bit of the SR register is set.

Bit 0 = OLVL1 Output Level 1.

The OLVL1 bit is copied to the OCMP1 pin when-

ever a successful comparison occurs with the

OC1R register and the OC1E bit is set in the CR2

register.

64/152

ST72C171

16-BIT TIMER (Cont’d)

CONTROL REGISTER 2 (CR2)

Read/Write

Bit 4 = PWM Pulse Width Modulation.

0: PWM mode is not active.

1: PWM mode is active, the OCMP1 pin outputs a

programmable cyclic signal; the length of the

pulse depends on the value of OC1R register;

the period depends on the value of OC2R regis-

ter.

Reset Value: 0000 0000 (00h)

7

0

OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG

Bits 3:2 = CC[1:0] Clock Control.

Bit 7 = OC1E Output Compare 1 Pin Enable.

This bit is used only to output the signal from the

timer on the OCMP1 pin (OLV1 in Output Com-

pare mode, both OLV1 and OLV2 in PWM and

one-pulse mode). Whatever the value of the OC1E

bit, the internal Output Compare 1 function of the

timer remains active.

0: OCMP1 pin alternate function disabled (I/O pin

free for general-purpose I/O).

1: OCMP1 pin alternate function enabled.

The timer clock mode depends on these bits:

Table 14. Clock Control Bits

Timer Clock

f_CPU/ 4

CC1

CC0

0

1

0

1

0

f_CPU/ 2

f_CPU/ 8

External Clock (where

available)

1

Bit 6 = OC2E Output Compare 2 Pin Enable.

This bit is used only to output the signal from the

timer on the OCMP2 pin (OLV2 in Output Com-

pare mode). Whatever the value of the OC2E bit,

the internal Output Compare 2 function of the timer

remains active.

0: OCMP2 pin alternate function disabled (I/O pin

free for general-purpose I/O).

1: OCMP2 pin alternate function enabled.

Note: If the external clock pin is not available, pro-

gramming the external clock configuration stops

the counter.

Bit 1 = IEDG2 Input Edge 2.

This bit determines which type of level transition

on the ICAP2 pin will trigger the capture.

0: A falling edge triggers the capture.

1: A rising edge triggers the capture.

Bit 5 = OPM One Pulse mode.

0: One Pulse mode is not active.

Bit 0 = EXEDG External Clock Edge.

1: One Pulse mode is active, the ICAP1 pin can be

used to trigger one pulse on the OCMP1 pin; the

active transition is given by the IEDG1 bit. The

length of the generated pulse depends on the

contents of the OC1R register.

This bit determines which type of level transition

on the external clock pin (EXTCLK) will trigger the

counter register.

0: A falling edge triggers the counter register.

1: A rising edge triggers the counter register.

65/152

ST72C171

16-BIT TIMER (Cont’d)

STATUS REGISTER (SR)

Read Only

INPUT CAPTURE 1 HIGH REGISTER (IC1HR)

Read Only

Reset Value: Undefined

Reset Value: 0000 0000 (00h)

The three least significant bits are not used.

7

This is an 8-bit read only register that contains the

high part of the counter value (transferred by the

input capture 1 event).

0

ICF1 OCF1 TOF ICF2 OCF2

0

7

0

MSB

LSB

Bit 7 = ICF1 Input Capture Flag 1.

0: No input capture (reset value).

1: An input capture has occurred on the ICAP1 pin

or the counter has reached the OC2R value in

PWM mode. To clear this bit, first read the SR

register, then read or write the low byte of the

IC1R (IC1LR) register.

INPUT CAPTURE 1 LOW REGISTER (IC1LR)

Read Only

Reset Value: Undefined

This is an 8-bit read only register that contains the

low part of the counter value (transferred by the in-

put capture 1 event).

Bit 6 = OCF1 Output Compare Flag 1.

0: No match (reset value).

1: The content of the free running counter matches

the content of the OC1R register. To clear this

bit, first read the SR register, then read or write

the low byte of the OC1R (OC1LR) register.

7

0

MSB

LSB

Bit 5 = TOF Timer Overflow Flag.

0: No timer overflow (reset value).

1: The free running counter has rolled over from

FFFFh to 0000h. To clear this bit, first read the

SR register, then read or write the low byte of

the CR (CLR) register.

OUTPUT COMPARE

(OC1HR)

1

HIGH REGISTER

Read/Write

Reset Value: 1000 0000 (80h)

This is an 8-bit register that contains the high part

of the value to be compared to the CHR register.

Note: Reading or writing the ACLR register does

not clear TOF.

7

0

MSB

LSB

Bit 4 = ICF2 Input Capture Flag 2.

0: No input capture (reset value).

1: An input capture has occurred on the ICAP2

pin. To clear this bit, first read the SR register,

then read or write the low byte of the IC2R

(IC2LR) register.

OUTPUT COMPARE

(OC1LR)

1

LOW REGISTER

Read/Write

Reset Value: 0000 0000 (00h)

Bit 3 = OCF2 Output Compare Flag 2.

0: No match (reset value).

This is an 8-bit register that contains the low part of

the value to be compared to the CLR register.

1: The content of the free running counter matches

the content of the OC2R register. To clear this

bit, first read the SR register, then read or write

the low byte of the OC2R (OC2LR) register.

7

0

MSB

LSB

Bit 2-0 = Reserved, forced by hardware to 0.

66/152

ST72C171

16-BIT TIMER (Cont’d)

OUTPUT COMPARE

(OC2HR)

2

HIGH REGISTER

ALTERNATE COUNTER HIGH REGISTER

(ACHR)

Read/Write

Reset Value: 1000 0000 (80h)

Read Only

Reset Value: 1111 1111 (FFh)

This is an 8-bit register that contains the high part

of the value to be compared to the CHR register.

This is an 8-bit register that contains the high part

of the counter value.

7

0

7

0

MSB

LSB

MSB

LSB

OUTPUT COMPARE

(OC2LR)

2

LOW REGISTER

ALTERNATE COUNTER LOW REGISTER

(ACLR)

Read/Write

Reset Value: 0000 0000 (00h)

Read Only

Reset Value: 1111 1100 (FCh)

This is an 8-bit register that contains the low part of

the value to be compared to the CLR register.

This is an 8-bit register that contains the low part of

the counter value. A write to this register resets the

counter. An access to this register after an access

to SR register does not clear the TOF bit in SR

register.

7

0

MSB

LSB

7

0

COUNTER HIGH REGISTER (CHR)

MSB

LSB

Read Only

Reset Value: 1111 1111 (FFh)

INPUT CAPTURE 2 HIGH REGISTER (IC2HR)

This is an 8-bit register that contains the high part

of the counter value.

Read Only

Reset Value: Undefined

7

0

This is an 8-bit read only register that contains the

high part of the counter value (transferred by the

Input Capture 2 event).

MSB

LSB

7

0

MSB

LSB

COUNTER LOW REGISTER (CLR)

Read Only

Reset Value: 1111 1100 (FCh)

This is an 8-bit register that contains the low part of

the counter value. A write to this register resets the

counter. An access to this register after accessing

the SR register clears the TOF bit.

INPUT CAPTURE 2 LOW REGISTER (IC2LR)

Read Only

Reset Value: Undefined

This is an 8-bit read only register that contains the

low part of the counter value (transferred by the In-

put Capture 2 event).

7

0

MSB

LSB

7

0

MSB

LSB

67/152

ST72C171

Table 15. 16-Bit Timer Register Map and Reset Values

Address

(Hex.)

Register

Name

7

6

5

4

3

2

1

0

CR1

ICIE

0

OCIE

0

TOIE

0

FOLV2

0

FOLV1

0

OLVL2

0

IEDG1

0

OLVL1

0

0032h

0031h

0033h

Reset Value

CR2

OC1E

0

OC2E

0

OPM

0

PWM

0

CC1

0

CC0

0

IEDG2

0

EXEDG

0

Reset Value

SR

ICF1

0

OCF1

0

TOF

0

ICF2

0

OCF2

0

-

Reset Value

0

IC1HR

MSB

-

LSB

-

Reset Value

0034h-

0035h

IC1LR

MSB

-

LSB

-

Reset Value

OC1HR

MSB

1

-

0

-

0

-

0

-

0

-

0

-

0

LSB

0

Reset Value

0036h-

0037h

OC1LR

MSB

0

-

0

-

0

-

0

-

0

-

0

-

0

LSB

0

Reset Value

OC2HR

MSB

1

-

0

-

0

-

0

-

0

-

0

-

0

LSB

0

Reset Value

003Eh-

003Fh

OC2LR

MSB

0

-

0

-

0

-

0

-

0

-

0

-

0

LSB

0

Reset Value

CHR

MSB

1

LSB

1

0

1

Reset Value

0038h-

0039h

CLR

MSB

1

LSB

0

Reset Value

ACHR

MSB

1

LSB

1

Reset Value

003Ah-

003Bh

ACLR

MSB

1

LSB

0

1

-

1

-

1

-

1

-

1

-

0

-

Reset Value

IC2HR

MSB

-

LSB

-

Reset Value

003Ch-

003Dh

IC2LR

MSB

-

LSB

-

Reset Value

68/152

ST72C171

7.6 PWM AUTO-RELOAD TIMER (ART)

7.6.1 Introduction

The Pulse Width Modulated Auto-Reload Timer

on-chip peripheral consists of an 8-bit auto reload

counter with compare/capture capabilities and of a

7-bit prescaler clock source.

– Up to two input capture functions

– External event detector

– Up to two external interrupt sources

The three first modes can be used together with a

single counter frequency.

These resources allow five possible operating

modes:

The timer can be used to wake up the MCU from

WAIT and HALT modes.

– Generation of up to 4 independent PWM signals

– Output compare and Time base interrupt

Figure 41. PWM Auto-Reload Timer Block Diagram

OCRx

DCRx

OEx

OPx

PWMCR

REGISTER

LOAD

PORT

ALTERNATE

FUNCTION

POLARITY

CONTROL

PWMx

COMPARE

8-BIT COUNTER

(CAR REGISTER)

ARR

REGISTER

LOAD

INPUT CAPTURE

CONTROL

ICRx

LOAD

ARTICx

REGISTER

ICSx

ICIEx

ICFx

ICCSR

ICx INTERRUPT

f

EXT

ARTCLK

f

COUNTER

f

CPU

MUX

f

INPUT

PROGRAMMABLE

PRESCALER

ARTCSR

EXCL CC2

CC1

CC0

TCE FCRL OIE

OVF

OVF INTERRUPT

69/152

ST72C171

PWM AUTO-RELOAD TIMER (Cont’d)

7.6.2 Functional Description

Counter

When TCE is set, the counter runs at the rate of

the selected clock source.

The free running 8-bit counter is fed by the output

of the prescaler, and is incremented on every ris-

ing edge of the clock signal.

Counter and Prescaler Initialization

After RESET, the counter and the prescaler are

It is possible to read or write the contents of the

counter on the fly by reading or writing the Counter

Access register (CAR).

cleared and f

= f

.

INPUT

CPU

The counter can be initialized by:

– Writing to the ARR register and then setting the

FCRL (Force Counter Re-Load) and the TCE

(Timer Counter Enable) bits in the CSR register.

When a counter overflow occurs, the counter is

automatically reloaded with the contents of the

ARR register (the prescaler is not affected).

– Writing to the CAR counter access register,

Counter clock and prescaler

In both cases the 7-bit prescaler is also cleared,

whereupon counting will start from a known value.

The counter clock frequency is given by:

CC[2:0]

f

= f

/ 2

COUNTER

INPUT

Direct access to the prescaler is not possible.

The timer counter’s input clock (f

) feeds the

INPUT

Output compare control

7-bit programmable prescaler, which selects one

of the 8 available taps of the prescaler, as defined

by CC[2:0] bits in the Control/Status Register

(CSR). Thus the division factor of the prescaler

The timer compare function is based on four differ-

ent comparisons with the counter (one for each

PWMx output). Each comparison is made be-

tween the counter value and an output compare

register (OCRx) value. This OCRx register can not

be accessed directly, it is loaded from the duty cy-

cle register (DCRx) at each overflow of the coun-

ter.

n

can be set to 2 (where n = 0, 1,..7).

This f

frequency source is selected through

INPUT

the EXCL bit of the CSR register and can be either

the f or an external input frequency f

.

EXT

CPU

The clock input to the counter is enabled by the

TCE (Timer Counter Enable) bit in the CSR regis-

ter. When TCE is reset, the counter is stopped and

the prescaler and counter contents are frozen.

This double buffering method avoids glitch gener-

ation when changing the duty cycle on the fly.

Figure 42. Output compare control

f_COUNTER

ARR=FDh

FFh

COUNTER

OCRx

FDh

FEh

FDh

FEh

FFh

FDh

FEh

FFh

FEh

FDh

DCRx

FEh

FDh

PWMx

70/152

ST72C171

PWM AUTO-RELOAD TIMER (Cont’d)

Independent PWM signal generation

OPx (output polarity) bit in the PWMCR register.

When the counter reaches the value contained in

one of the output compare register (OCRx) the

corresponding PWMx pin level is restored.

This mode allows up to four Pulse Width Modulat-

ed signals to be generated on the PWMx output

pins with minimum core processing overhead.

This function is stopped during HALT mode.

It should be noted that the reload values will also

affect the value and the resolution of the duty cycle

of the PWM output signal. To obtain a signal on a

PWMx pin, the contents of the OCRx register must

be greater than the contents of the ARR register.

Each PWMx output signal can be selected inde-

pendently using the corresponding OEx bit in the

PWM Control register (PWMCR). When this bit is

set, the corresponding I/O pin is configured as out-

put push-pull alternate function.

The maximum available resolution for the PWMx

duty cycle is:

The PWM signals all have the same frequency

which is controlled by the counter period and the

ARR register value.

Resolution = 1 / (256 - ARR)

Note: To get the maximum resolution (1/256), the

ARR register must be 0. With this maximum reso-

lution, 0% and 100% can be obtained by changing

the polarity.

f

= f

/ (256 - ARR)

PWM

COUNTER

When a counter overflow occurs, the PWMx pin

level is changed depending on the corresponding

Figure 43. PWM Auto-reload Timer Function

255

DUTY CYCLE

REGISTER

(DCRx)

AUTO-RELOAD

REGISTER

(ARR)

000

t

WITH OEx=1

AND OPx=0

WITH OEx=1

AND OPx=1

Figure 44. PWM Signal from 0% to 100% Duty Cycle

f_COUNTER

ARR=FDh

COUNTER

FDh

FEh

FFh

FDh

FEh

FFh

FDh

FEh

OCRx=FCh

OCRx=FDh

OCRx=FEh

OCRx=FFh

t

71/152

ST72C171

PWM AUTO-RELOAD TIMER (Cont’d)

Output compare and Time base interrupt

External clock and event detector mode

Using the f external prescaler input clock, the

auto-reload timer can be used as an external clock

event detector. In this mode, the ARR register is

On overflow, the OVF flag of the CSR register is

set and an overflow interrupt request is generated

if the overflow interrupt enable bit, OIE, in the CSR

register, is set. The OVF flag must be reset by the

user software. This interrupt can be used as a time

base in the application.

EXT

used to select the n

counted before setting the OVF flag.

number of events to be

EVENT

n

= 256 - ARR

EVENT

When entering HALT mode while f

is selected,

EXT

all the timer control registers are frozen but the

counter continues to increment. If the OIE bit is

set, the next overflow of the counter will generate

an interrupt which wakes up the MCU.

Figure 45. External Event Detector Example (3 counts)

f_EXT=f_COUNTER

ARR=FDh

COUNTER

FDh

FEh

FFh

FDh

FEh

FFh

FDh

OVF

CSR READ

INTERRUPT

IF OIE=1

INTERRUPT

IF OIE=1

t

72/152

ST72C171

PWM AUTO-RELOAD TIMER (Cont’d)

Input capture function

This mode allows the measurement of external

signal pulse widths through ICRx registers.

External interrupt capability

This mode allows the Input capture capabilities to

be used as external interrupt sources. The inter-

rupts are generated on the edge of the ARTICx

signal.

Each input capture can generate an interrupt inde-

pendently on a selected input signal transition.

This event is flagged by a set of the corresponding

CFx bits of the Input Capture Control/Status regis-

ter (ICCSR).

The edge sensitivity of the external interrupts is

programmable (CSx bit of ICCSR register) and

they are independently enabled through CIEx bits

of the ICCSR register. After fetching the interrupt

vector, the CFx flags can be read to identify the in-

terrupt source.

These input capture interrupts are enabled

through the CIEx bits of the ICCSR register.

The active transition (falling or rising edge) is soft-

ware programmable through the CSx bits of the

ICCSR register.

During HALT mode, the external interrupts can be

used to wake up the micro (if the CIEx bit is set).

The read only input capture registers (ICRx) are

used to latch the auto-reload counter value when a

transition is detected on the ARTICx pin (CFx bit

set in ICCSR register). After fetching the interrupt

vector, the CFx flags can be read to identify the in-

terrupt source.

Note: After a capture detection, data transfer in

the ICRx register is inhibited until it is read (clear-

ing the CFx bit).

The timer interrupt remains pending while the CFx

flag is set when the interrupt is enabled (CIEx bit

set). This means, the ICRx register has to be read

at each capture event to clear the CFx flag.

The timing resolution is given by auto-reload coun-

ter cycle time (1/f

).

COUNTER

Note: During HALT mode, if both input capture

and external clock are enabled, the ICRx register

value is not guaranteed if the input capture pin and

the external clock change simultaneously.

Figure 46. Input Capture Timing Diagram

f_COUNTER

COUNTER

01h

02h

03h

04h

05h

06h

07h

INTERRUPT

04h

ARTICx PIN

CFx FLAG

xxh

ICRx REGISTER

t

73/152

ST72C171

PWM AUTO-RELOAD TIMER (Cont’d)

7.6.3 Register Description

CONTROL / STATUS REGISTER (CSR)

Read/Write

COUNTER ACCESS REGISTER (CAR)

Read/Write

Reset Value: 0000 0000 (00h)

7

0

7

0

EXCL CC2

CC1

CC0

TCE FCRL

OIE

OVF

CA7

CA6

CA5

CA4

CA3

CA2

CA1

CA0

Bit 7 = EXCLExternal Clock

Bit 7:0 = CA[7:0] Counter Access Data

This bit is set and cleared by software. It selects the

input clock for the 7-bit prescaler.

0: CPU clock.

These bits can be set and cleared either by hard-

ware or by software. The CAR register is used to

read or write the auto-reload counter “on the fly”

(while it is counting).

1: External clock.

Bit 6:4 = CC[2:0] Counter Clock Control

These bits are set and cleared by software. They

determine the prescaler division ratio from f

.

INPUT

AUTO-RELOAD REGISTER (ARR)

Read/Write

f

With f

INPUT

=8 MHz CC2 CC1 CC0

COUNTER

f

8 MHz

4 MHz

2 MHz

1 MHz

500 KHz

250 KHz

125 KHz

62.5 KHz

0

1

0

1

0

1

0

1

0

1

0

1

0

1

INPUT

f

/ 2

/ 4

/ 8

INPUT

Reset Value: 0000 0000 (00h)

7

0

f

/ 16

/ 32

/ 64

/ 128

INPUT

AR7

AR6

AR5

AR4

AR3

AR2

AR1

AR0

f

INPUT

Bit 7:0 = AR[7:0]Counter Auto-Reload Data

These bits are set and cleared by software. They

are used to hold the auto-reload value which is au-

tomatically loaded in the counter when an overflow

occurs. At the same time, the PWM output levels

are changed according to the corresponding OPx

bit in the PWMCR register.

Bit 3 = TCE Timer Counter Enable

This bit is set and cleared by software. It puts the

timer in the lowest power consumption mode.

0: Counter stopped (prescaler and counter frozen).

1: Counter running.

Bit 2 = FCRLForce Counter Re-Load

This register has two PWM management func-

tions:

This bit is write-only and any attempt to read it will

yielda logicalzero. When set, itcausesthecontents

of ARR register to be loaded into the counter, and

the content of the prescaler register to be cleared in

order to initialize the timer before starting to count.

– Adjusting the PWM frequency

– Setting the PWM duty cycle resolution

PWM Frequency vs. Resolution:

Bit 1 = OIEOverflow Interrupt Enable

This bit is set and cleared by software. It allows to

enable/disable the interrupt which is generated

when the OVF bit is set.

f

PWM

ARR value Resolution

Min

Max

0

8-bit

~0.244-KHz 31.25-KHz

0: Overflow Interrupt disable.

1: Overflow Interrupt enable.

[ 0..127 ]

> 7-bit

> 6-bit

> 5-bit

> 4-bit

~0.244-KHz

~0.488-KHz

~0.977-KHz

~1.953-KHz

62.5-KHz

125-KHz

250-KHz

500-KHz

[ 128..191 ]

[ 192..223 ]

[ 224..239 ]

Bit 0 = OVFOverflow Flag

This bit is set by hardware and cleared by software

reading the CSR register. It indicates the transition

of the counter from FFh to the ARR value

0: New transition not yet reached

1: Transition reached

.

74/152

ST72C171

PWM AUTO-RELOAD TIMER (Cont’d)

PWM CONTROL REGISTER (PWMCR)

Read/Write

DUTY CYCLE REGISTERS (DCRx)

Read/Write

Reset Value: 0000 0000 (00h)

7

0

7

0

OE1

OE0

0

OP1

OP0

DC7

DC6

DC5

DC4

DC3

DC2

DC1

DC0

Bit 7:6 = Reserved.

Bit 5:4 = OE[1:0] PWM Output Enable

These bits are set and cleared by software. They

enable or disable the PWM output channels inde-

pendently acting on the corresponding I/O pin.

0: PWM output disabled.

Bit 7:0 = DC[7:0] Duty Cycle Data

These bits are set and cleared by software.

A DCRx register is associated with the OCRx reg-

ister of each PWM channel to determine the sec-

ond edge location of the PWM signal (the first

edge location is common to all channels and given

by the ARR register). These DCR registers allow

the duty cycle to be set independently for each

PWM channel.

1: PWM output enabled.

Bit 3:2 = Reserved.

Bit 1:0 = OP[1:0] PWM Output Polarity

These bits are set and cleared by software. They

independently select the polarity of the two PWM

output signals.

PWMx output level

OPx

Counter <= OCRx

Counter > OCRx

1

0

1

0

1

Note: When an OPx bit is modified, the PWMx out-

put signal polarity is immediately reversed.

75/152

ST72C171

PWM AUTO-RELOAD TIMER (Cont’d)

INPUT CAPTURE

CONTROL / STATUS REGISTER (ICCSR)

INPUT CAPTURE REGISTERS (ICRx)

Read only

Read/Write

Reset Value: 0000 0000 (00h)

7

0

7

0

IC7

IC6

IC5

IC4

IC3

IC2

IC1

IC0

0

CS2

CS1

CIE2 CIE1

CF2

CF1

Bit 7:0 = IC[7:0] Input Capture Data

Bit 7:6 = Reserved, always read as 0.

These read only bits are set and cleared by hard-

ware. An ICRx register contains the 8-bit auto-re-

load counter value transferred by the input capture

channel x event.

Bit 5:4 = CS[2:1] Capture Sensitivity

These bits are set and cleared by software. They

determine the trigger event polarity on the corre-

sponding input capture channel.

0: Falling edge triggers capture on channel x.

1: Rising edge triggers capture on channel x.

Bit 3:2 = CIE[2:1] Capture Interrupt Enable

These bits are set and cleared by software. They

allow to enable or not the Input capture channel in-

terrupts independently.

0: Input capture channel x interrupt disabled.

1: Input capture channel x interrupt enabled.

Bit 1:0 = CF[2:1] Capture Flag

These bits are set by hardware and cleared by

software reading the corresponding ICRx register.

Each CFx bit indicates that an input capture x has

occurred.

0: No input capture on channel x.

1: An input capture has occured on channel x.

76/152

ST72C171

PWM AUTO-RELOAD TIMER (Cont’d)

Table 16. PWM Auto-Reload Timer Register Map and Reset Values

Address

(Hex.)

Register

Label

7

6

5

4

3

2

1

0

PWMDCR1

Reset Value

DC7

0

DC6

0

DC5

0

DC4

0

DC3

0

DC2

0

DC1

0

DC0

0

0074h

0075h

0076h

0077h

0078h

0079h

007Ah

007Bh

PWMDCR0

Reset Value

DC7

0

DC6

0

DC5

0

DC4

0

DC3

0

DC2

0

DC1

0

DC0

0

PWMCR

0

OE1

0

OE0

0

OP1

0

OP0

0

Reset Value

ARTCSR

EXCL

0

CC2

0

CC1

0

CC0

0

TCE

0

FCRL

0

RIE

0

OVF

0

Reset Value

ARTCAR

CA7

0

CA6

0

CA5

0

CA4

0

CA3

0

CA2

0

CA1

0

CA0

0

Reset Value

ARTARR

AR7

0

AR6

0

AR5

0

AR4

0

AR3

0

AR2

0

AR1

0

AR0

0

Reset Value

ARTICCSR

Reset Value

CE2

0

CE1

0

CS2

0

CS1

0

CF2

0

CF1

0

ARTICR1

IC7

0

IC6

0

IC5

0

IC4

0

IC3

0

IC2

0

IC1

0

IC0

0

Reset Value

77/152

ST72C171

7.7 SERIAL COMMUNICATIONS INTERFACE (SCI)

7.7.1 Introduction

7.7.3 General Description

The Serial Communications Interface (SCI) offers

a flexible means of full-duplex data exchange with

external equipment requiring an industry standard

NRZ asynchronous serial data format.

The interface is externally connected to another

device by two pins (see Figure 47):

– TDO: Transmit Data Output. When the transmit-

ter is disabled, the output pin returns to its I/O

port configuration. When the transmitter is ena-

bled and nothing is to be transmitted, the TDO

pin is at high level.

7.7.2 Main Features

■ Full duplex, asynchronous communications

■ NRZ standard format (Mark/Space)

– RDI: Receive Data Input is the serial data input.

Oversampling techniques are used for data re-

covery by discriminating between valid incoming

data and noise.

■ Independently programmable transmit and

receive baud rates up to 250K baud.

■ Programmable data word length (8 or 9 bits)

■ Receive buffer full, Transmit buffer empty and

Through this pins, serial data is transmitted and re-

ceived as frames comprising:

End of Transmission flags

■ Two receiver wake-up modes:

– Address bit (MSB)

– An Idle Line prior to transmission or reception

– A start bit

– Idle line

– A data word (8 or 9 bits) least significant bit first

– A Stop bit indicating that the frame is complete.

■ Mutingfunctionformultiprocessorconfigurations

■ Separate enable bits for Transmitter and

Receiver

■ Three error detection flags:

– Overrun error

– Noise error

– Frame error

■ Five interrupt sources with flags:

– Transmit data register empty

– Transmission complete

– Receive data register full

– Idle line received

– Overrun error detected

78/152

ST72C171

SERIAL COMMUNICATIONS INTERFACE (Cont’d)

Figure 47. SCI Block Diagram

Write

Read

(Data Register) DR

Received Data Register (RDR)

Received Shift Register

Transmit Data Register (TDR)

TDO

Transmit Shift Register

RDI

CR1

R8

-

T8

-

M

WAKE

-

WAKE

TRANSMIT

UP

RECEIVER

CLOCK

RECEIVER

CONTROL

UNIT

CR2

SR

TIE TCIE RIE ILIE TE RE RWU SBK

TDRE TC RDRF

IDLE OR NF FE

-

SCI

INTERRUPT

CONTROL

TRANSMITTER

CLOCK

Transmitter Rate

Control

f

CPU

/PR

/2

/16

BRR

SCP1

SCT2

SCT1SCT0SCR2 SCR1SCR0

SCP0

Receiver Rate

Control

BAUD RATE GENERATOR

79/152

ST72C171

SERIAL COMMUNICATIONS INTERFACE (Cont’d)

7.7.4 Functional Description

The TDO pin is in low state during the start bit.

The TDO pin is in high state during the stop bit.

The block diagram of the Serial Control Interface,

is shown in Figure 47. It contains 4 dedicated reg-

isters:

An Idle character is interpreted as an entire frame

of “1”s followed by the start bit of the next frame

which contains data.

– Two control registers (CR1 & CR2)

– A status register (SR)

A Break character is interpreted on receiving “0”s

for some multiple of the frame period. At the end of

the last break frame the transmitter inserts an ex-

tra “1” bit to acknowledge the start bit.

– A baud rate register (BRR)

Refer to the register descriptions in Section 9.7.7

for the definitions of each bit.

Transmission and reception are driven by their

own baud rate generator.

7.7.4.1 Serial Data Format

Word length may be selected as being either 8 or 9

bits by programming the M bit in the CR1 register

(see Figure 47).

Figure 48. Word Length Programming

9-bit Word length (M bit is set)

Possible

Next Data Frame

Parity

Data Frame

Start

Bit

Stop

Bit

Bit2

Bit1

Bit3

Bit5

Bit6

Bit8

Bit0

Bit4

Bit7

Bit

Start

Bit

Idle Frame

Start

Bit

Extra

’1’

Break Frame

8-bit Word length (M bit is reset)

Possible

Parity

Next Data Frame

Data Frame

Start

Bit

Stop

Bit

Bit2

Bit1

Bit3

Bit5

Bit6

Bit0

Bit4

Bit7

Bit

Start

Bit

Idle Frame

Start

Bit

Extra

’1’

Break Frame

80/152

ST72C171

SERIAL COMMUNICATIONS INTERFACE (Cont’d)

7.7.4.2 Transmitter

When a frame transmission is complete (after the

stop bit or after the break frame) the TC bit is set

and an interrupt is generated if the TCIE is set and

the I bit is cleared in the CC register.

The transmitter can send data words of either 8 or

9 bits depending on the M bit status. When the M

bit is set, word length is 9 bits and the 9th bit (the

MSB) has to be stored in the T8 bit in the CR1 reg-

ister.

The following software sequence is always to clear

the TC bit:

1. An access to the SR register

Character Transmission

2. A write to the DR register

During an SCI transmission, data shifts out least

significant bit first on the TDO pin. In this mode,

the DR register consists of a buffer (TDR) between

the internal bus and the transmit shift register (see

Figure 47).

Note: The TDRE and TC bits are cleared by the

same software sequence.

Break Characters

Setting the SBK bit loads the shift register with a

break character. The break frame length depends

on the M bit (see Figure 48).

Procedure

– Select the M bit to define the word length.

As long as the SBK bit is set, the SCI sends break

frames to the TDO pin. After clearing this bit by

software, the SCI inserts a logic 1 bit at the end of

the last break frame to guarantee the recognition

of the start bit of the next frame.

– Select the desired baud rate using the BRR reg-

ister.

– Set the TE bit to assign the TDO pin to the alter-

nate function and to send a idle frame as first

transmission.

Idle Characters

– Access the SR register and write the data to

send in the DR register (this sequence clears the

TDRE bit). Repeat this sequence for each data to

be transmitted.

Setting the TE bit drives the SCI to send an idle

frame before the first data frame.

Clearing and then setting the TE bit during a trans-

mission sends an idle frame after the current word.

The following software sequence is always to clear

the TDRE bit:

1. An access to the SR register

2. A write to the DR register

Note: Resetting and setting the TE bit causes the

data in the TDR register to be lost. Therefore the

best time to toggle the TE bit is when the TDRE bit

is set, i.e. before writing the next byte in the DR.

The TDRE bit is set by hardware and it indicates

that:

– The TDR register is empty.

– The data transfer is beginning.

– The next data can be written in the DR register

without overwriting the previous data.

This flag generates an interrupt if the TIE bit is set

and the I bit is cleared in the CC register.

When a transmission is taking place, a write in-

struction to the DR register stores the data in the

TDR register which is copied in the shift register at

the end of the current transmission.

When no transmission is taking place, a write in-

struction to the DR register places the data directly

in the shift register, the data transmission starts,

and the TDRE bit is immediately set.

81/152

ST72C171

SERIAL COMMUNICATIONS INTERFACE (Cont’d)

7.7.4.3 Receiver

Overrun Error

An overrun error occurs when a character is re-

ceived when RDRF has not been reset. Data can

not be transferred from the shift register to the

TDR register as long as the RDRF bit is not

cleared.

The SCI can receive data words of either 8 or 9

bits. When the M bit is set, word length is 9 bits

and the MSB is stored in the R8 bit in the CR1 reg-

ister.

Character reception

When a overrun error occurs:

– The OR bit is set.

During a SCI reception, data shifts in least signifi-

cant bit first through the RDI pin. In this mode, the

DR register consists of a buffer (RDR) between

the internal bus and the received shift register (see

Figure 47).

– The RDR content will not be lost.

– The shift register will be overwritten.

– An interrupt is generated if the RIE bit is set and

the I bit is cleared in the CC register.

Procedure

– Select the M bit to define the word length.

The OR bit is reset by an access to the SR register

followed by a DR register read operation.

– Select the desired baud rate using the BRR reg-

ister.

Noise Error

– Set the RE bit to enable the receiverto begin

searching for a start bit.

Oversampling techniques are used for data recov-

ery by discriminating between valid incoming data

and noise.

When a character is received:

– The RDRF bit is set. It indicates that the content

of the shift register is transferred to the RDR.

When noise is detected in a frame:

– The NF is set at the rising edge of the RDRF bit.

– An interrupt is generated if the RIE bit is set and

the I bit is cleared in the CC register.

– Data is transferred from the Shift register to the

DR register.

– The error flags can be set if a frame error, noise

or an overrun error has been detected during re-

ception.

– No interrupt is generated. However this bit rises

at the same time as the RDRF bit which itself

generates an interrupt.

Clearing the RDRF bit is performed by the following

software sequence done by:

The NF bit is reset by a SR register read operation

followed by a DR register read operation.

1. An access to the SR register

2. A read to the DR register.

Framing Error

A framing error is detected when:

The RDRF bit must be cleared before the end of the

reception of the next character to avoid an overrun

error.

– The stop bit is not recognized on reception at the

expected time, following either a de-synchroni-

zation or excessive noise.

Break Character

– A break is received.

When a break character is received, the SCI han-

dles it as a framing error.

When the framing error is detected:

– The FE bit is set by hardware

Idle Character

– Data is transferred from the Shift register to the

DR register.

When a idle frame is detected, there is the same

procedure as a data received character plus an in-

terrupt if the ILIE bit is set and the I bit is cleared in

the CC register.

– No interrupt is generated. However this bit rises

at the same time as the RDRF bit which itself

generates an interrupt.

The FE bit is reset by a SR register read operation

followed by a DR register read operation.

82/152

ST72C171

SERIAL COMMUNICATIONS INTERFACE (Cont’d)

7.7.4.4 Baud Rate Generation

should actively receive the full message contents,

thus reducing redundant SCI service overhead for

all non addressed receivers.

The baud rates for the receiver and transmitter (Rx

and Tx) are set independently and calculated as

follows:

The non addressed devices may be placed in

sleep mode by means of the muting function.

f

CPU

Setting the RWU bit by software puts the SCI in

sleep mode:

Rx =

Tx =

(32 PR) RR

(32 PR) TR

*

All the reception status bits can not be set.

All the receive interrupt are inhibited.

with:

PR = 1, 3, 4 or 13 (see SCP0 & SCP1 bits)

TR = 1, 2, 4, 8, 16, 32, 64,128

A muted receiver may be awakened by one of the

following two ways:

(see SCT0, SCT1 & SCT2 bits)

RR = 1, 2, 4, 8, 16, 32, 64,128

– by Idle Line detection if the WAKE bit is reset,

– by Address Mark detection if the WAKE bit is set.

(see SCR0,SCR1 & SCR2 bits)

All these bits are in the BRR register.

The Receiver wakes-up by Idle Line detection

when the Receive line has recognised an Idle

Frame. Then the RWU bit is reset by hardware but

the IDLE bit is not set.

Example: If f

is 8 MHz and if PR=13 and

CPU

TR=RR=1, the transmit and receive baud rates are

19200 bauds.

The Receiver wakes-up by Address Mark detec-

tion when it received a “1” as the most significant

bit of a word, thus indicating that the message is

an address. The reception of this particular word

wakes up the receiver, resets the RWU bit and

sets the RDRF bit, which allows the receiver to re-

ceive this word normally and to use it as an ad-

dress word.

Note: The baud rate registers MUST NOT be

changed while the transmitter or the receiver is en-

abled.

7.7.4.5 Receiver Muting and Wake-up Feature

In multiprocessor configurations it is often desira-

ble that only the intended message recipient

83/152

ST72C171

SERIAL COMMUNICATIONS INTERFACE (Cont’d)

7.7.5 Low Power Modes

Mode

Description

No effect on SCI.

WAIT

SCI interrupts exit from Wait mode.

SCI registers are frozen.

HALT

In Halt mode, the SCI stops transmitting/receiving until Halt mode is exited.

7.7.6 Interrupts

Enable

Control from

Bit

Exit

from

Halt

Event

Flag

Interrupt Event

Wait

Yes

Transmit Data Register Empty

Transmission Complete

TDRE

TC

TIE

No

TCIE

Received Data Ready to be Read

Overrrun Error Detected

Idle Line Detected

RDRF

OR

RIE

ILIE

IDLE

The SCI interrupt events are connected to the

same interrupt vector (see Interrupts chapter).

rupt mask in the CC register is reset (RIM instruc-

tion).

These events generate an interrupt if the corre-

sponding Enable Control Bit is set and the inter-

84/152

ST72C171

SERIAL COMMUNICATIONS INTERFACE (Cont’d)

7.7.7 Register Description

Note: The IDLE bit will not be set again until the

RDRF bit has been set itself (i.e. a new idle line oc-

curs). This bit is not set by an idle line when the re-

ceiver wakes up from wake-up mode.

STATUS REGISTER (SR)

Read Only

Reset Value: 1100 0000 (C0h)

Bit 3 = OR Overrun error.

7

0

This bit is set by hardware when the word currently

being received in the shift register is ready to be

transferred into the RDR register while RDRF=1.

An interrupt is generated if RIE=1 in the CR2 reg-

ister. It is cleared by hardware when RE=0 by a

software sequence (an access to the SR register

followed by a read to the DR register).

0: No Overrun error

TDRE

TC

RDRF IDLE

OR

NF

FE

Bit 7 = TDRE Transmit data register empty.

This bit is set by hardware when the content of the

TDR register has been transferred into the shift

register. An interrupt is generated if TIE =1 in the

CR2 register. It is cleared by a software sequence

(an access to the SR register followed by a write to

the DR register).

1: Overrun error is detected

Note: When this bit is set the RDR register content

will not be lost but the shift register will be overwrit-

ten.

0: Data is not transferred to the shift register

1: Data is transferred to the shift register

Note: data will not be transferred to the shift regis-

ter as long as the TDRE bit is not reset.

Bit 2 = NF Noise flag.

This bit is set by hardware when noise is detected

on a received frame. It is cleared by hardware

when RE=0 by a software sequence (an access to

the SR register followed by a read to the DR regis-

ter).

0: No noise is detected

1: Noise is detected

Bit 6 = TC Transmission complete.

This bit is set by hardware when transmission of a

frame containing Data, a Preamble or a Break is

complete. An interrupt is generated if TCIE=1 in

the CR2 register. It is cleared by a software se-

quence (an access to the SR register followed by a

write to the DR register).

Note: This bit does not generate interrupt as it ap-

pears at the same time as the RDRF bit which it-

self generates an interrupt.

0: Transmission is not complete

1: Transmission is complete

Bit 1 = FE Framing error.

Bit 5 = RDRF Received data ready flag.

This bit is set by hardware when a de-synchroniza-

tion, excessive noise or a break character is de-

tected. It is cleared by hardware when RE=0 by a

software sequence (an access to the SR register

followed by a read to the DR register).

0: No Framing error is detected

1: Framing error or break character is detected

This bit is set by hardware when the content of the

RDR register has been transferred into the DR

register. An interrupt is generated if RIE=1 in the

CR2 register. It is cleared by hardware when

RE=0 or by a software sequence (an access to the

SR register followed by a read to the DR register).

0: Data is not received

Note: This bit does not generate interrupt as it ap-

pears at the same time as the RDRF bit which it-

self generates an interrupt. If the word currently

being transferred causes both frame error and

overrun error, it will be transferred and only the OR

bit will be set.

1: Received data is ready to be read

Bit 4 = IDLE Idle line detect.

This bit is set by hardware when an Idle Line is de-

tected. An interrupt is generated if ILIE=1 in the

CR2 register. It is cleared by hardware when

RE=0 by a software sequence (an access to the

SR register followed by a read to the DR register).

0: No Idle Line is detected

Bit 0 = Reserved, forced by hardware to 0.

1: Idle Line is detected

85/152

ST72C171

SERIAL COMMUNICATIONS INTERFACE (Cont’d)

CONTROL REGISTER 1 (CR1)

Read/Write

0: interrupt is inhibited

1: An SCI interrupt is generated whenever TC=1 in

the SR register

Reset Value: Undefined

Bit 5 = RIE Receiver interrupt enable.

This bit is set and cleared by software.

0: interrupt is inhibited

1: An SCI interrupt is generated whenever OR=1

or RDRF=1 in the SR register

7

0

R8

T8

0

M

WAKE

0

Bit 7 = R8 Receive data bit 8.

This bit is used to store the 9th bit of the received

word when M=1.

Bit 4 = ILIE Idle line interrupt enable.

This bit is set and cleared by software.

0: interrupt is inhibited

1: An SCI interrupt is generated whenever IDLE=1

in the SR register.

Bit 6 = T8 Transmit data bit 8.

This bit is used to store the 9th bit of the transmit-

ted word when M=1.

Bit 3 = TE Transmitter enable.

This bit enables the transmitter and assigns the

TDO pin to the alternate function. It is set and

cleared by software.

Bit 5 = Reserved, forced by hardware to 0.

0: Transmitter is disabled, the TDO pin is back to

the I/O port configuration.

1: Transmitter is enabled

Bit 4 = M Word length.

This bit determines the data length. It is set or

cleared by software.

0: 1 Start bit, 8 Data bits, 1 Stop bit

1: 1 Start bit, 9 Data bits, 1 Stop bit

Note: During transmission, a “0” pulse on the TE

bit (“0” followed by “1”) sends a preamble after the

current word.

Bit 3 = WAKE Wake-Up method.

This bit determines the SCI Wake-Up method, it is

set or cleared by software.

0: Idle Line

Bit 2 = RE Receiver enable.

This bit enables the receiver. It is set and cleared

by software.

0: Receiver is disabled, it resets the RDRF, IDLE,

OR, NF and FE bits of the SR register.

1: Receiver is enabled and begins searching for a

start bit.

1: Address Mark

Bit 2:0 = Reserved, forced by hardware to 0.

Bit 1 = RWU Receiver wake-up.

CONTROL REGISTER 2 (CR2)

Read/Write

This bit determines if the SCI is in mute mode or

not. It is set and cleared by software and can be

cleared by hardware when a wake-up sequence is

recognized.

Reset Value: 0000 0000 (00h)

7

0

0: Receiver in active mode

1: Receiver in mute mode

TIE

TCIE

RIE

ILIE

TE

RE

RWU

SBK

Bit 0 = SBK Send break.

This bit set is used to send break characters. It is

set and cleared by software.

0: No break character is transmitted

1: Break characters are transmitted

Bit 7 = TIE Transmitter interrupt enable.

This bit is set and cleared by software.

0: interrupt is inhibited

1: An SCI interrupt is generated whenever

TDRE=1 in the SR register.

Note: If the SBK bit is set to “1” and then to “0”, the

transmitter will send a BREAK word at the end of

the current word.

Bit 6 = TCIE Transmission complete interrupt ena-

ble

This bit is set and cleared by software.

86/152

ST72C171

SERIAL COMMUNICATIONS INTERFACE (Cont’d)

DATA REGISTER (DR)

Bit 5:3 = SCT[2:0] SCI Transmitter rate divisor

Read/Write

These 3 bits, in conjunction with the SCP1 & SCP0

bits, define the total division applied to the bus

clock to yield the transmit rate clock in convention-

al Baud Rate Generator mode.

Reset Value: Undefined

Contains the Received or Transmitted data char-

acter, depending on whether it is read from or writ-

ten to.

TR dividing factor

SCT2

SCT1

SCT0

1

2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

7

0

4

DR7

DR6

DR5

DR4

DR3

DR2

DR1

DR0

8

16

32

64

128

The Data register performs a double function (read

and write) since it is composed of two registers,

one for transmission (TDR) and one for reception

(RDR).

The TDR register provides the parallel interface

between the internal bus and the output shift reg-

ister (see Figure 47).

The RDR register provides the parallel interface

between the input shift register and the internal

bus (see Figure 47).

Bit 2:0 = SCR[2:0] SCI Receiver rate divisor.

These 3 bits, in conjunction with the SCP1 & SCP0

bits, define the total division applied to the bus

clock to yield the receive rate clock in conventional

Baud Rate Generator mode.

BAUD RATE REGISTER (BRR)

Read/Write

RR dividing factor

SCR2

SCR1

SCR0

Reset Value: 00xx xxxx (XXh)

1

2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

7

0

4

SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0

8

16

32

64

128

Bit 7:6= SCP[1:0] First SCI Prescaler

These 2 prescaling bits allow several standard

clock division ranges:

PR Prescaling factor

SCP1

SCP0

1

3

0

1

0

1

0

1

4

13

87/152

ST72C171

Table 17. SCI Register Map and Reset Values

Address

(Hex.)

Register

Name

7

6

5

4

3

2

1

0

SR

D7

D6

D5

-

D4

D3

D2

D1

D0

0050h

0051h

0052h

0053h

0054h

Reset Value

DR

-

SPIE

0

-

SPE

0

-

MSTR

CPOL

CPHA

SPR1

SPR0

Reset Value

BRR

0

-

0

x

SPIF

0

WCOL

0

MODF

-

Reset Value

CR1

0

D5

-

0

D7

-

D6

-

D4

D3

D2

D1

D0

Reset Value

CR2

-

MSTR

0

-

CPOL

x

-

CPHA

x

-

SPR1

x

-

SPR0

x

SPIE

0

SPE

0

-

Reset Value

0

88/152

ST72C171

7.8 SERIAL PERIPHERAL INTERFACE (SPI)

7.8.1 Introduction

7.8.3 General description

The Serial Peripheral Interface (SPI) allows full-

duplex, synchronous, serial communication with

external devices. An SPI system may consist of a

master and one or more slaves or a system in

which devices may be either masters or slaves.

The SPI is connected to external devices through

4 alternate pins:

– MISO: Master In Slave Out pin

– MOSI: Master Out Slave In pin

– SCK: Serial Clock pin

The SPI is normally used for communication be-

tween the microcontroller and external peripherals

or another microcontroller.

– SS: Slave select pin

Refer to the Pin Description chapter for the device-

specific pin-out.

A basic example of interconnections between a

single master and a single slave is illustrated on

Figure 49.

7.8.2 Main Features

The MOSI pins are connected together as are

MISO pins. In this way data is transferred serially

between master and slave (most significant bit

first).

■ Full duplex, three-wire synchronous transfers

■ Master or slave operation

■ Four master mode frequencies

■ Maximum slave mode frequency = fCPU/2.

■ Four programmable master bit rates

■ Programmable clock polarity and phase

■ End of transfer interrupt flag

When the master device transmits data to a slave

device via MOSI pin, the slave device responds by

sending data to the master device via the MISO

pin. This implies full duplex transmission with both

data out and data in synchronized with the same

clock signal (which is provided by the master de-

vice via the SCK pin).

■ Write collision flag protection

■ Master mode fault protection capability.

Thus, the byte transmitted is replaced by the byte

received and eliminates the need for separate

transmit-empty and receiver-full bits. A status flag

is used to indicate that the I/O operation is com-

plete.

Four possible data/clock timing relationships may

be chosen (see Figure 52) but master and slave

must be programmed with the same timing mode.

Figure 49. Serial Peripheral Interface Master/Slave

MASTER

SLAVE

MSBit

LSBit

MSBit

LSBit

MISO

MOSI

MISO

MOSI

8-BIT SHIFT REGISTER

SPI

CLOCK

SCK

GENERATOR

SS

+5V

89/152

ST72C171

SERIAL PERIPHERAL INTERFACE (Cont’d)

Figure 50. Serial Peripheral Interface Block Diagram

Internal Bus

Read

DR

IT

Read Buffer

request

MOSI

SR

MISO

8-Bit Shift Register

Write

MODF

WCOL

SPIF

-

SPI

STATE

CONTROL

SCK

SS

CR

SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0

MASTER

CONTROL

SERIAL

CLOCK

GENERATOR

90/152

ST72C171

SERIAL PERIPHERAL INTERFACE (Cont’d)

7.8.4 Functional Description

In this configuration the MOSI pin is a data output

and to the MISO pin is a data input.

Figure 49 shows the serial peripheral interface

(SPI) block diagram.

This interface contains 3 dedicated registers:

– A Control Register (CR)

Transmit sequence

The transmit sequence begins when a byte is writ-

ten the DR register.

– A Status Register (SR)

The data byte is parallel loaded into the 8-bit shift

register (from the internal bus) during a write cycle

and then shifted out serially to the MOSI pin most

significant bit first.

– A Data Register (DR)

Refer to the CR, SR and DR registers in Section

9.8.7for the bit definitions.

7.8.4.1 Master Configuration

When data transfer is complete:

– The SPIF bit is set by hardware

In a master configuration, the serial clock is gener-

ated on the SCK pin.

– An interrupt is generated if the SPIE bit is set

and the I bit in the CCR register is cleared.

Procedure

– Select the SPR0 & SPR1 bits to define the se-

rial clock baud rate (see CR register).

During the last clock cycle the SPIF bit is set, a

copy of the data byte received in the shift register

is moved to a buffer. When the DR register is read,

the SPI peripheral returns this buffered value.

– Select the CPOL and CPHA bits to define one

of the four relationships between the data

transfer and the serial clock (see Figure 52).

Clearing the SPIF bit is performed by the following

software sequence:

– The SS pin must be connected to a high level

signal during the complete byte transmit se-

quence.

1. An access to the SR register while the SPIF bit

is set

– The MSTR and SPE bits must be set (they re-

main set only if the SS pin is connected to a

high level signal).

2. A read to the DR register.

Note: While the SPIF bit is set, all writes to the DR

register are inhibited until the SR register is read.

91/152

ST72C171

SERIAL PERIPHERAL INTERFACE (Cont’d)

7.8.4.2 Slave Configuration

When data transfer is complete:

– The SPIF bit is set by hardware

In slave configuration, the serial clock is received

on the SCK pin from the master device.

– An interrupt is generated if SPIE bit is set and

I bit in CCR register is cleared.

The value of the SPR0 & SPR1 bits is not used for

the data transfer.

During the last clock cycle the SPIF bit is set, a

copy of the data byte received in the shift register

is moved to a buffer. When the DR register is read,

the SPI peripheral returns this buffered value.

Procedure

– For correct data transfer, the slave device

must be in the same timing mode as the mas-

ter device (CPOL and CPHA bits). See Figure

52.

Clearing the SPIF bit is performed by the following

software sequence:

1. An access to the SR register while the SPIF bit

is set.

– The SS pin must be connected to a low level

signal during the complete byte transmit se-

quence.

2.A read to the DR register.

– Clear the MSTR bit and set the SPE bit to as-

sign the pins to alternate function.

Notes: While the SPIF bit is set, all writes to the

DR register are inhibited until the SR register is

read.

In this configuration the MOSI pin is a data input

and the MISO pin is a data output.

The SPIF bit can be cleared during a second

transmission; however, it must be cleared before

the second SPIF bit in order to prevent an overrun

condition (see Section 9.8.4.6).

Transmit Sequence

The data byte is parallel loaded into the 8-bit shift

register (from the internal bus) during a write cycle

and then shifted out serially to the MISO pin most

significant bit first.

Depending on the CPHA bit, the SS pin has to be

set to write to the DR register between each data

byte transfer to avoid a write collision (see Section

9.8.4.4).

The transmit sequence begins when the slave de-

vice receives the clock signal and the most signifi-

cant bit of the data on its MOSI pin.

92/152

ST72C171

SERIAL PERIPHERAL INTERFACE (Cont’d)

7.8.4.3 Data Transfer Format

The master device applies data to its MOSI pin-

clock edge before the capture clock edge.

During an SPI transfer, data is simultaneously

transmitted (shifted out serially) and received

(shifted in serially). The serial clock is used to syn-

chronize the data transfer during a sequence of

eight clock pulses.

CPHA bit is set

The second edge on the SCK pin (falling edge if

the CPOL bit is reset, rising edge if the CPOL bit is

set) is the MSBit capture strobe. Data is latched on

the occurrence of the second clock transition.

The SS pin allows individual selection of a slave

device; the other slave devices that are not select-

ed do not interfere with the SPI transfer.

No write collision should occur even if the SS pin

stays low during a transfer of several bytes (see

Figure 51).

Clock Phase and Clock Polarity

Four possible timing relationships may be chosen

by software, using the CPOL and CPHA bits.

CPHA bit is reset

The CPOL (clock polarity) bit controls the steady

state value of the clock when no data is being

transferred. This bit affects both master and slave

modes.

The first edge on the SCK pin (falling edge if CPOL

bit is set, rising edge if CPOL bit is reset) is the

MSBit capture strobe. Data is latched on the oc-

currence of the first clock transition.

The combination between the CPOL and CPHA

(clock phase) bits selects the data capture clock

edge.

The SS pin must be toggled high and low between

each byte transmitted (see Figure 51).

To protect the transmission from a write collision a

low value on the SS pin of a slave device freezes

the data in its DR register and does not allow it to

be altered. Therefore the SS pin must be high to

write a new data byte in the DR without producing

a write collision.

Figure 52, shows an SPI transfer with the four

combinations of the CPHA and CPOL bits. The di-

agram may be interpreted as a master or slave

timing diagram where the SCK pin, the MISO pin,

the MOSI pin are directly connected between the

master and the slave device.

The SS pin is the slave device select input and can

be driven by the master device.

Figure 51. CPHA / SS Timing Diagram

Byte 3

Byte 2

MOSI/MISO

Byte 1

Master SS

Slave SS

(CPHA=0)

Slave SS

(CPHA=1)

VR02131A

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ST72C171

SERIAL PERIPHERAL INTERFACE (Cont’d)

Figure 52. Data Clock Timing Diagram

CPHA =1

SCLK (with

CPOL = 1)

SCLK (with

CPOL = 0)

Bit 4

Bit3

Bit 2

Bit 1

LSBit

MSBit

Bit 6

Bit 5

MISO

(from master)

Bit3

MOSI

(from slave)

SS

(to slave)

CAPTURE STROBE

CPHA =0

CPOL = 1

CPOL = 0

Bit 4

Bit3

Bit 2

Bit 1

LSBit

MSBit

Bit 6

Bit 5

MISO

(from master)

MSBit

Bit3

MOSI

(from slave)

SS

(to slave)

CAPTURE STROBE

Note: This figure should not be used as a replacement for parametric information.

Refer to the Electrical Characteristics chapter.

VR02131B

94/152

ST72C171

SERIAL PERIPHERAL INTERFACE (Cont’d)

7.8.4.4 Write Collision Error

When the CPHA bit is reset:

A write collision occurs when the software tries to

write to the DR register while a data transfer is tak-

ing place with an external device. When this hap-

pens, the transfer continues uninterrupted; and

the software write will be unsuccessful.

Data is latched on the occurrence of the first clock

transition. The slave device does not have any

way of knowing when that transition will occur;

therefore, the slave device collision occurs when

software attempts to write the DR register after its

SS pin has been pulled low.

Write collisions can occur both in master and slave

mode.

For this reason, the SS pin must be high, between

each data byte transfer, to allow the CPU to write

in the DR register without generating a write colli-

sion.

Note: a "read collision" will never occur since the

received data byte is placed in a buffer in which

access is always synchronous with the MCU oper-

ation.

In Slave mode

In Master mode

When the CPHA bit is set:

Collision in the master device is defined as a write

of the DR register while the internal serial clock

(SCK) is in the process of transfer.

The slave device will receive a clock (SCK) edge

prior to the latch of the first data transfer. This first

clock edge will freeze the data in the slave device

DR register and output the MSBit on to the exter-

nal MISO pin of the slave device.

The SS pin signal must be always high on the

master device.

The SS pin low state enables the slave device but

the output of the MSBit onto the MISO pin does

not take place until the first data transfer clock

edge.

WCOL bit

The WCOL bit in the SR register is set if a write

collision occurs.

No SPI interrupt is generated when the WCOL bit

is set (the WCOL bit is a status flag only).

Clearing the WCOL bit is done through a software

sequence (see Figure 53).

Figure 53. Clearing the WCOL bit (Write Collision Flag) Software Sequence

Clearing sequence after SPIF = 1 (end of a data byte transfer)

Read SR

1st Step

2nd Step

OR

THEN

SPIF =0

WCOL=0

SPIF =0

WCOL=0 if no transfer has started

WCOL=1 if a transfer has started

before the 2nd step

Read DR

Write DR

Clearing sequence before SPIF = 1 (during a data byte transfer)

Read SR

1st Step

THEN

Note: Writing in DR register in-

2nd Step

Read DR

stead of reading in it do not reset

WCOL bit

WCOL=0

95/152

ST72C171

SERIAL PERIPHERAL INTERFACE (Cont’d)

7.8.4.5 Master Mode Fault

may be restored to their original state during or af-

ter this clearing sequence.

Master mode fault occurs when the master device

has its SS pin pulled low, then the MODF bit is set.

Hardware does not allow the user to set the SPE

and MSTR bits while the MODF bit is set except in

the MODF bit clearing sequence.

Master mode fault affects the SPI peripheral in the

following ways:

In a slave device the MODF bit can not be set, but

in a multi master configuration the device can be in

slave mode with this MODF bit set.

– The MODF bit is set and an SPI interrupt is

generated if the SPIE bit is set.

– The SPE bit is reset. This blocks all output

from the device and disables the SPI periph-

eral.

The MODF bit indicates that there might have

been a multi-master conflict for system control and

allows a proper exit from system operation to a re-

set or default system state using an interrupt rou-

tine.

– The MSTR bit is reset, thus forcing the device

into slave mode.

Clearing the MODF bit is done through a software

sequence:

7.8.4.6 Overrun Condition

An overrun condition occurs when the master de-

vice has sent several data bytes and the slave de-

vice has not cleared the SPIF bit issuing from the

previous data byte transmitted.

1. A read or write access to the SR register while

the MODF bit is set.

2. A write to the CR register.

In this case, the receiver buffer contains the byte

sent after the SPIF bit was last cleared. A read to

the DR register returns this byte. All other bytes

are lost.

Notes: To avoid any multiple slave conflicts in the

case of a system comprising several MCUs, the

SS pin must be pulled high during the clearing se-

quence of the MODF bit. The SPE and MSTR bits

This condition is not detected by the SPI peripher-

al.

96/152

ST72C171

SERIAL PERIPHERAL INTERFACE (Cont’d)

7.8.4.7 Single Master and Multimaster Configurations

There are two types of SPI systems:

– Single Master System

For more security, the slave device may respond

to the master with the received data byte. Then the

master will receive the previous byte back from the

slave device if all MISO and MOSI pins are con-

nected and the slave has not written its DR regis-

ter.

– Multimaster System

Single Master System

Other transmission security methods can use

ports for handshake lines or data bytes with com-

mand fields.

A typical single master system may be configured,

using an MCU as the master and four MCUs as

slaves (see Figure 54).

Multi-master System

The master device selects the individual slave de-

vices by using four pins of a parallel port to control

the four SS pins of the slave devices.

A multi-master system may also be configured by

the user. Transfer of master control could be im-

plemented using a handshake method through the

I/O ports or by an exchange of code messages

through the serial peripheral interface system.

The SS pins are pulled high during reset since the

master device ports will be forced to be inputs at

that time, thus disabling the slave devices.

The multi-master system is principally handled by

the MSTR bit in the CR register and the MODF bit

in the SR register.

Note: To prevent a bus conflict on the MISO line

the master allows only one active slave device

during a transmission.

Figure 54. Single Master Configuration

SS

SCK

Slave

SCK

Slave

SCK

Slave

MCU

Slave

MCU

MOSI MISO

SCK

Master

MCU

5V

SS

97/152

ST72C171

SERIAL PERIPHERAL INTERFACE (Cont’d)

7.8.5 Low Power Modes

Mode

Description

No effect on SPI.

WAIT

SPI interrupt events cause the device to exit from WAIT mode.

SPI registers are frozen.

HALT

In HALT mode, the SPI is inactive. SPI operation resumes when the MCU is woken up by an interrupt with

“exit from HALT mode” capability.

7.8.6 Interrupts

Enable

Control from

Bit

Exit

from

Halt

Event

Flag

Interrupt Event

Wait

Yes

SPI End of Transfer Event

Master Mode Fault Event

SPIF

No

SPIE

MODF

Note: The SPI interrupt events are connected to

the same interrupt vector (see Interrupts chapter).

They generate an interrupt if the corresponding

Enable Control Bit is set and the interrupt mask in

the CC register is reset (RIM instruction).

98/152

ST72C171

SERIAL PERIPHERAL INTERFACE (Cont’d)

7.8.7 Register Description

CONTROL REGISTER (CR)

Read/Write

Bit 3 = CPOL Clock polarity.

This bit is set and cleared by software. This bit de-

termines the steady state of the serial Clock. The

CPOL bit affects both the master and slave

modes.

Reset Value: 0000xxxx (0xh)

7

0

SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0

0: The steady state is a low value at the SCK pin.

1: The steady state is a high value at the SCK pin.

Bit 7 = SPIE Serial peripheral interrupt enable.

This bit is set and cleared by software.

0: Interrupt is inhibited

1: An SPI interrupt is generated whenever SPIF=1

or MODF=1 in the SR register

Bit 2 = CPHA Clock phase.

This bit is set and cleared by software.

0: The first clock transition is the first data capture

edge.

1: The second clock transition is the first capture

edge.

Bit 6 = SPE Serial peripheral output enable.

This bit is set and cleared by software. It is also

cleared by hardware when, in master mode, SS=0

(see Section 9.8.4.5 Master Mode Fault).

0: I/O port connected to pins

Bit 1:0 = SPR[1:0] Serial peripheral rate.

These bits are set and cleared by software.Used

with the SPR2 bit, they select one of six baud rates

to be used as the serial clock when the device is a

master.

1: SPI alternate functions connected to pins

The SPE bit is cleared by reset, so the SPI periph-

eral is not initially connected to the external pins.

These 2 bits have no effect in slave mode.

Table 18. Serial Peripheral Baud Rate

Bit 5 = SPR2 Divider Enable.

Serial Clock

SPR2 SPR1 SPR0

this bit is set and cleared by software and it is

cleared by reset. It is used with the SPR[1:0] bits to

set the baud rate. Refer to Table 19.

0: Divider by 2 enabled

f

/4

/8

1

0

1

0

1

0

1

0

1

CPU

f

/16

/32

/64

CPU

1: Divider by 2 disabled

Bit 4 = MSTR Master.

f

/128

CPU

This bit is set and cleared by software. It is also

cleared by hardware when, in master mode, SS=0

(see Section 9.8.4.5 Master Mode Fault).

0: Slave mode is selected

1: Master mode is selected, the function of the

SCK pin changes from an input to an output and

the functions of the MISO and MOSI pins are re-

versed.

99/152

ST72C171

SERIAL PERIPHERAL INTERFACE (Cont’d)

STATUS REGISTER (SR)

Read Only

DATA I/O REGISTER (DR)

Read/Write

Reset Value: 0000 0000 (00h)

Reset Value: Undefined

7

0

-

7

0

SPIF

WCOL

-

MODF

-

D7

D6

D5

D4

D3

D2

D1

D0

Bit 7 = SPIF Serial Peripheral data transfer flag.

This bit is set by hardware when a transfer has

been completed. An interrupt is generated if

SPIE=1 in the CR register. It is cleared by a soft-

ware sequence (an access to the SR register fol-

lowed by a read or write to the DR register).

0: Data transfer is in progress or has been ap-

proved by a clearing sequence.

The DR register is used to transmit and receive

data on the serial bus. In the master device only a

write to this register will initiate transmission/re-

ception of another byte.

Notes: During the last clock cycle the SPIF bit is

set, a copy of the received data byte in the shift

register is moved to a buffer. When the user reads

the serial peripheral data I/O register, the buffer is

actually being read.

1: Data transfer between the device and an exter-

nal device has been completed.

Warning:

Note: While the SPIF bit is set, all writes to the DR

register are inhibited.

A write to the DR register places data directly into

the shift register for transmission.

A write to the the DR register returns the value lo-

cated in the buffer and not the contents of the shift

register (See Figure 50 ).

Bit 6 = WCOL Write Collision status.

This bit is set by hardware when a write to the DR

register is done during a transmit sequence. It is

cleared by a software sequence (see Figure 53).

0: No write collision occurred

1: A write collision has been detected

Bit 5 = Unused.

Bit 4 = MODF Mode Fault flag.

This bit is set by hardware when the SS pin is

pulled low in master mode (see Section 9.8.4.5

Master Mode Fault). An SPI interrupt can be gen-

erated if SPIE=1 in the CR register. This bit is

cleared by a software sequence (An access to the

SR register while MODF=1 followed by a write to

the CR register).

0: No master mode fault detected

1: A fault in master mode has been detected

Bits 3-0 = Unused.

100/152

ST72C171

Table 19. SPI Register Map and Reset Values

Address

(Hex.)

Register

Name

7

6

5

4

3

2

1

0

DR

D7

-

D6

D5

-

D4

D3

D2

D1

-

D0

-

21

22

23

Reset Value

CR

-

SPE

0

-

MSTR

0

-

SPIE

0

-

CPOL

CPHA

SPR1

SPR0

Reset Value

SR

0

-

x

-

x

-

x

-

x

-

SPIF

0

WCOL

0

MODF

0

Reset Value

0

101/152

ST72C171

7.9 8-BIT A/D CONVERTER (ADC)

7.9.1 Introduction

7.9.3 Functional Description

7.9.3.1 Analog Power Supply

The on-chip Analog to Digital Converter (ADC) pe-

ripheral is a 8-bit, successive approximation con-

verter with internal sample and hold circuitry. This

peripheral has up to 16 multiplexed analog input

channels (refer to device pin out description) that

allow the peripheral to convert the analog voltage

levels from up to 16 different sources.

V

and V

are the high and low level refer-

SSA

DDA

ence voltage pins. In some devices (refer to device

pin out description) they are internally connected

to the V and V pins.

DD

SS

Conversion accuracy may therefore be impacted

by voltage drops and noise in the event of heavily

loaded or badly decoupled power supply lines.

The result of the conversion is stored in a 8-bit

Data Register. The A/D converter is controlled

through a Control/Status Register.

See electrical characteristics section for more de-

tails.

7.9.2 Main Features

■ 8-bit conversion

■ Up to 16 channels with multiplexed input

■ Linear successive approximation

■ Data register (DR) which contains the results

■ Conversion complete status flag

■ On/off bit (to reduce consumption)

The block diagram is shown in Figure 55.

Figure 55. ADC Block Diagram

f

ADC

CPU

DIV 2

COCO

0

ADON

4

0

CH3 CH2 CH1 CH0

ADCCSR

AIN0

AIN1

HOLD CONTROL

R

ADC

ANALOG TO DIGITAL

CONVERTER

ANALOG

MUX

AINx

C

ADC

ADCDR

D7

D6

D5

D4

D3

D2

D1

D0

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ST72C171

8-BIT A/D CONVERTER (ADC) (Cont’d)

7.9.3.2 Digital A/D Conversion Result

The analog input ports must be configured as in-

put, no pull-up, no interrupt. Refer to the «I/O

ports» chapter. Using these pins as analog inputs

does not affect the ability of the port to be read as

a logic input.

The conversion is monotonic, meaning that the re-

sult never decreases if the analog input does not

and never increases if the analog input does not.

If the input voltage (V ) is greater than or equal

AIN

In the CSR register:

to V

(high-level voltage reference) then the

DDA

conversion result in the DR register is FFh (full

scale) without overflow indication.

– Select the CH[3:0] bits to assign the analog

channel to be converted.

ADC Conversion

If input voltage (V ) is lower than or equal to

AIN

V

(low-level voltage reference) then the con-

version result in the DR register is 00h.

SSA

In the CSR register:

– Set the ADON bit to enable the A/D converter

and to start the first conversion. From this time

on, the ADC performs a continuous conver-

sion of the selected channel.

The A/D converter is linear and the digital result of

the conversion is stored in the ADCDR register.

The accuracy of the conversion is described in the

parametric section.

When a conversion is complete

R

is the maximum recommended impedance

– The COCO bit is set by hardware.

– No interrupt is generated.

– The result is in the DR register and remains

valid until the next conversion has ended.

AIN

for an analog input signal. If the impedance is too

high, this will result in a loss of accuracy due to

leakage and sampling not being completed in the

alloted time.

A write to the CSR register (with ADON set) aborts

the current conversion, resets the COCO bit and

starts a new conversion.

7.9.3.3 A/D Conversion Phases

The A/D conversion is based on two conversion

phases as shown in Figure 56:

Figure 56. ADC Conversion Timings

■ Sample capacitor loading [duration: t

]

LOAD

During this phase, the V

input voltage to be

AIN

ADON

measured is loaded into the C

capacitor.

sample

ADC

ADCCSR WRITE

OPERATION

t

CONV

■ A/D conversion [duration: t

]

CONV

During this phase, the A/D conversion is

computed (8 successive approximations cycles)

HOLD

CONTROL

and the C

sample capacitor is disconnected

ADC

from the analog input pin to get the optimum

analog to digital conversion accuracy.

t

LOAD

COCO BIT SET

While the ADC is on, these two phases are contin-

uously repeated.

7.9.4 Low Power Modes

At the end of each conversion, the sample capaci-

tor is kept loaded with the previous measurement

load. The advantage of this behaviour is that it

minimizes the current consumption on the analog

pin in case of single input channel measurement.

Mode

WAIT

Description

No effect on A/D Converter

A/D Converter disabled.

After wakeup from Halt mode, the A/D Con-

verter requires a stabilisation time before ac-

curate conversions can be performed.

HALT

7.9.3.4 Software Procedure

Refer to the control/status register (CSR) and data

register (DR) in Section 9.9.6 for the bit definitions

and to Figure 56 for the timings.

Note: The A/D converter may be disabled by reset-

ting the ADON bit. This feature allows reduced

power consumption when no conversion is needed

and between single shot conversions.

ADC Configuration

The total duration of the A/D conversion is 12 ADC

7.9.5 Interrupts

clock periods (1/f

=2/f

).

ADC

CPU

None

103/152

ST72C171

8-BIT A/D CONVERTER (ADC) (Cont’d)

7.9.6 Register Description

CONTROL/STATUS REGISTER (CSR)

Read/Write

DATA REGISTER (DR)

Read Only

Reset Value: 0000 0000 (00h)

7

0

7

0

COCO

0

ADON

0

CH3

CH2

CH1

CH0

D7

D6

D5

D4

D3

D2

D1

D0

Bit 7 = COCO Conversion Complete

This bit is set by hardware. It is cleared by soft-

ware reading the result in the DR register or writing

to the CSR register.

0: Conversion is not complete

1: Conversion can be read from the DR register

Bit 7:0 = D[7:0] Analog Converted Value

This register contains the converted analog value

in the range 00h to FFh.

Note: Reading this register reset the COCO flag.

Bit 6 = Reserved. must always be cleared.

Bit 5 = ADON A/D Converter On

This bit is set and cleared by software.

0: A/D converter is switched off

1: A/D converter is switched on

Bit 4 = Reserved. must always be cleared.

Bit 3:0 = CH[3:0] Channel Selection

These bits are set and cleared by software. They

select the analog input to convert.

Channel Pin*

CH3 CH2 CH1 CH0

AIN0

AIN1

AIN2

AIN3

AIN4

AIN5

AIN6

AIN7

AIN8

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

AIN9

AIN10

AIN11

AIN12

AIN13

AIN14

AIN15

*Note: The number of pins AND the channel selec-

tion varies according to the device. Refer to the de-

vice pinout.

104/152

ST72C171

Table 20. ADC Register Map

Address

(Hex.)

Register

Name

7

6

5

4

3

2

1

0

DR

0070h

AD7

0

AD6

0

AD5

0

AD4

0

AD3

0

AD2

0

AD1

0

AD0

0

Reset Value

CSR

0071h

COCO

0

EXTCK

0

ADON

0

CH3

0

CH2

0

CH1

0

CH0

0

Reset Value

105/152

ST72C171

8 INSTRUCTION SET

8.1 ST7 ADDRESSING MODES

so, most of the addressing modes may be subdi-

vided in two sub-modes called long and short:

The ST7 Core features 17 different addressing

modes which can be classified in 7 main groups:

– Long addressing mode is more powerful be-

cause it can use the full 64 Kbyte address space,

however it uses more bytes and more CPU cy-

cles.

Addressing Mode

Inherent

Example

nop

– Short addressing mode is less powerful because

it can generally only access page zero (0000h -

00FFh range), but the instruction size is more

compact, and faster. All memory to memory in-

structions use short addressing modes only

(CLR, CPL, NEG, BSET, BRES, BTJT, BTJF,

INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP)

Immediate

Direct

ld A,#$55

ld A,$55

Indexed

ld A,($55,X)

ld A,([$55],X)

jrne loop

Indirect

Relative

Bit operation

bset byte,#5

The ST7 Assembler optimizes the use of long and

short addressing modes.

The ST7 Instruction set is designed to minimize

the number of bytes required per instruction: To do

Table 21. ST7 Addressing Mode Overview

Pointer

Address

(Hex.)

Pointer

Size

(Hex.)

Destination/

Source

Length

(Bytes)

Mode

Syntax

Inherent

Immediate

Short

nop

+ 0

+ 1

+ 2

ld A,#$55

ld A,$10

Direct

00..FF

Long

ld A,$1000

0000..FFFF

+ 0 (with X register)

+ 1 (with Y register)

No Offset

Direct

Indexed

ld A,(X)

00..FF

Short

Long

Short

Long

Short

Long

Relative

Bit

Direct

Indexed

ld A,($10,X)

ld A,($1000,X)

ld A,[$10]

00..1FE

+ 1

+ 2

+ 1

+ 2

+ 1

+ 2

+ 3

Direct

0000..FFFF

00..FF

Indirect

Direct

00..FF

byte

word

byte

word

ld A,[$10.w]

ld A,([$10],X)

0000..FFFF

00..1FE

Indexed

ld A,([$10.w],X) 0000..FFFF

1)

jrne loop

PC-128/PC+127

Indirect

Direct

jrne [$10]

PC-128/PC+127

00..FF

byte

bset $10,#7

bset [$10],#7

Bit

Indirect

Direct

00..FF

Bit

Relative btjt $10,#7,skip 00..FF

Relative btjt [$10],#7,skip 00..FF

Bit

Indirect

Note 1. At the time the instruction is executed, the Program Counter (PC) points to the instruction follow-

ing JRxx.

106/152

ST72C171

ST7 ADDRESSING MODES (Cont’d)

8.1.1 Inherent

8.1.3 Direct

All Inherent instructions consist of a single byte.

The opcode fully specifies all the required informa-

tion for the CPU to process the operation.

In Direct instructions, the operands are referenced

by their memory address.

The direct addressing mode consists of two sub-

modes:

Inherent Instruction

Function

No operation

Direct (short)

NOP

The address is a byte, thus requires only one byte

after the opcode, but only allows 00 - FF address-

ing space.

TRAP

S/W Interrupt

Wait For Interrupt (Low Power

Mode)

WFI

Direct (long)

Halt Oscillator (Lowest Power

Mode)

HALT

The address is a word, thus allowing 64 Kbyte ad-

dressing space, but requires 2 bytes after the op-

code.

RET

Sub-routine Return

Interrupt Sub-routine Return

Set Interrupt Mask

Reset Interrupt Mask

Set Carry Flag

IRET

SIM

8.1.4 Indexed (No Offset, Short, Long)

RIM

In this mode, the operand is referenced by its

memory address, which is defined by the unsigned

addition of an index register (X or Y) with an offset.

SCF

RCF

Reset Carry Flag

Reset Stack Pointer

Load

The indirect addressing mode consists of three

sub-modes:

RSP

LD

Indexed (No Offset)

CLR

Clear

There is no offset, (no extra byte after the opcode),

and allows 00 - FF addressing space.

PUSH/POP

INC/DEC

TNZ

Push/Pop to/from the stack

Increment/Decrement

Test Negative or Zero

1 or 2 Complement

Byte Multiplication

Indexed (Short)

The offset is a byte, thus requires only one byte af-

ter the opcode and allows 00 - 1FE addressing

space.

CPL, NEG

MUL

Indexed (long)

SLL, SRL, SRA, RLC,

RRC

Shift and Rotate Operations

Swap Nibbles

The offset is a word, thus allowing 64 Kbyte ad-

dressing space and requires 2 bytes after the op-

code.

SWAP

8.1.2 Immediate

Immediate instructions have two bytes, the first

byte contains the opcode, the second byte con-

tains the operand value.

8.1.5 Indirect (Short, Long)

The required data byte to do the operation is found

by its memory address, located in memory (point-

er).

Immediate Instruction

Function

The pointer address follows the opcode. The indi-

rect addressing mode consists of two sub-modes:

LD

Load

CP

Compare

Indirect (short)

BCP

Bit Compare

The pointer address is a byte, the pointer size is a

byte, thus allowing 00 - FF addressing space, and

requires 1 byte after the opcode.

AND, OR, XOR

ADC, ADD, SUB, SBC

Logical Operations

Arithmetic Operations

Indirect (long)

The pointer address is a byte, the pointer size is a

word, thus allowing 64 Kbyte addressing space,

and requires 1 byte after the opcode.

107/152

ST72C171

ST7 ADDRESSING MODES (Cont’d)

8.1.6 Indirect Indexed (Short, Long)

SWAP

Swap Nibbles

This is a combination of indirect and short indexed

addressing modes. The operand is referenced by

its memory address, which is defined by the un-

signed addition of an index register value (X or Y)

with a pointer value located in memory. The point-

er address follows the opcode.

CALL, JP

Call or Jump subroutine

8.1.7 Relative Mode (Direct, Indirect)

This addressing mode is used to modify the PC

register value by adding an 8-bit signed offset to it.

Available Relative Direct/

Function

The indirect indexed addressing mode consists of

two sub-modes:

Indirect Instructions

JRxx

Conditional Jump

Call Relative

Indirect Indexed (Short)

CALLR

The pointer address is a byte, the pointer size is a

byte, thus allowing 00 - 1FE addressing space,

and requires 1 byte after the opcode.

The relative addressing mode consists of two sub-

modes:

Indirect Indexed (Long)

Relative (Direct)

The pointer address is a byte, the pointer size is a

word, thus allowing 64 Kbyte addressing space,

and requires 1 byte after the opcode.

The offset follows the opcode.

Relative (Indirect)

The offset is defined in memory, of which the ad-

dress follows the opcode.

Table 22. Instructions Supporting Direct,

Indexed, Indirect and Indirect Indexed

Addressing Modes

Long and Short

Function

Instructions

LD

Load

CP

Compare

AND, OR, XOR

Logical Operations

Arithmetic Addition/subtrac-

tion operations

ADC, ADD, SUB, SBC

BCP

Bit Compare

Short Instructions Only

CLR

Function

Clear

INC, DEC

Increment/Decrement

Test Negative or Zero

1 or 2 Complement

Bit Operations

TNZ

CPL, NEG

BSET, BRES

Bit Test and Jump Opera-

tions

BTJT, BTJF

SLL, SRL, SRA, RLC,

RRC

Shift and Rotate Operations

108/152

ST72C171

8.2 INSTRUCTION GROUPS

The ST7 family devices use an Instruction Set

consisting of 63 instructions. The instructions may

be subdivided into 13 main groups as illustrated in

the following table:

Load and Transfer

LD

CLR

POP

DEC

TNZ

OR

Stack operation

PUSH

INC

RSP

BCP

Increment/Decrement

Compare and Tests

Logical operations

CP

AND

BSET

BTJT

ADC

SLL

XOR

CPL

NEG

Bit Operation

BRES

BTJF

ADD

SRL

JRT

Conditional Bit Test and Branch

Arithmetic operations

Shift and Rotates

SUB

SRA

JRF

SBC

RLC

JP

MUL

RRC

CALL

SWAP

CALLR

SLA

Unconditional Jump or Call

Conditional Branch

JRA

JRxx

TRAP

SIM

NOP

RET

Interruption management

Code Condition Flag modification

WFI

RIM

HALT

SCF

IRET

RCF

Using a pre-byte

The instructions are described with one to four

bytes.

These prebytes enable instruction in Y as well as

indirect addressing modes to be implemented.

They precede the opcode of the instruction in X or

the instruction using direct addressing mode. The

prebytes are:

In order to extend the number of available op-

codes for an 8-bit CPU (256 opcodes), three differ-

ent prebyte opcodes are defined. These prebytes

modify the meaning of the instruction they pre-

cede.

PDY 90 Replace an X based instruction using

immediate, direct, indexed, or inherent

addressing mode by a Y one.

The whole instruction becomes:

PC-2 End of previous instruction

PC-1 Prebyte

PIX 92 Replace an instruction using direct, di-

rect bit, or direct relative addressing

mode to an instruction using the corre-

sponding indirect addressing mode.

It also changes an instruction using X

indexed addressing mode to an instruc-

tion using indirect X indexed addressing

mode.

PC

Opcode

PC+1 Additional word (0 to 2) according to the

number of bytes required to compute the

effective address

PIY 91 Replace an instruction using X indirect

indexed addressing mode by a Y one.

109/152

ST72C171

INSTRUCTION GROUPS (Cont’d)

Mnemo

ADC

ADD

AND

BCP

Description

Add with Carry

Function/Example

A = A + M + C

A = A + M

Dst

Src

H

I

N

Z

C

A

M

Addition

A

Logical And

A = A . M

A

Bit compare A, Memory

Bit Reset

tst (A . M)

A

BRES

BSET

BTJF

BTJT

CALL

CALLR

CLR

bres Byte, #3

bset Byte, #3

btjf Byte, #3, Jmp1

btjt Byte, #3, Jmp1

M

Bit Set

Jump if bit is false (0)

Jump if bit is true (1)

Call subroutine

Call subroutine relative

Clear

C

reg, M

reg

0

N

1

Z

CP

Arithmetic Compare

One Complement

Decrement

tst(Reg - M)

A = FFH-A

dec Y

M

C

1

CPL

reg, M

DEC

HALT

IRET

INC

Halt

0

I

Interrupt routine return

Increment

Pop CC, A, X, PC

inc X

H

N

Z

C

reg, M

JP

Absolute Jump

Jump relative always

Jump relative

jp [TBL.w]

JRA

JRT

JRF

Never jump

jrf *

JRIH

JRIL

Jump if ext. interrupt = 1

Jump if ext. interrupt = 0

Jump if H = 1

JRH

H = 1 ?

JRNH

JRM

Jump if H = 0

H = 0 ?

Jump if I = 1

I = 1 ?

JRNM

JRMI

JRPL

JREQ

JRNE

JRC

Jump if I = 0

I = 0 ?

Jump if N = 1 (minus)

Jump if N = 0 (plus)

Jump if Z = 1 (equal)

Jump if Z = 0 (not equal)

Jump if C = 1

N = 1 ?

N = 0 ?

Z = 1 ?

Z = 0 ?

C = 1 ?

JRNC

JRULT

Jump if C = 0

C = 0 ?

Jump if C = 1

Unsigned <

Jmp if unsigned >=

Unsigned >

JRUGE Jump if C = 0

JRUGT Jump if (C + Z = 0)

110/152

ST72C171

INSTRUCTION GROUPS (Cont’d)

Mnemo

JRULE

LD

Description

Jump if (C + Z = 1)

Load

Function/Example

Unsigned <=

dst <= src

Dst

Src

H

I

N

Z

C

reg, M

A, X, Y

reg, M

M, reg

X, Y, A

MUL

NEG

NOP

OR

Multiply

X,A = X * A

0

Negate (2’s compl)

No Operation

OR operation

Pop from the Stack

neg $10

C

A = A + M

pop reg

pop CC

push Y

C = 0

A

M

POP

reg

CC

M

H

I

C

0

PUSH

RCF

RET

RIM

Push onto the Stack

Reset carry flag

Subroutine Return

Enable Interrupts

Rotate left true C

Rotate right true C

Reset Stack Pointer

Subtract with Carry

Set carry flag

reg, CC

I = 0

0

RLC

RRC

RSP

SBC

SCF

SIM

C <= Dst <= C

C => Dst => C

S = Max allowed

A = A - M - C

C = 1

reg, M

N

Z

C

A

M

N

Z

C

1

Disable Interrupts

Shift left Arithmetic

Shift left Logic

I = 1

1

SLA

C <= Dst <= 0

0 => Dst => C

Dst7 => Dst => C

A = A - M

reg, M

A

N

0

Z

C

SLL

SRL

SRA

SUB

SWAP

TNZ

TRAP

WFI

Shift right Logic

Shift right Arithmetic

Subtraction

N

M

SWAP nibbles

Dst[7..4] <=> Dst[3..0] reg, M

tnz lbl1

Test for Neg & Zero

S/W trap

S/W interrupt

1

0

Wait for Interrupt

Exclusive OR

XOR

A = A XOR M

A

M

N

Z

111/152

ST72C171

9 ELECTRICAL CHARACTERISTICS

9.1 PARAMETER CONDITIONS

Unless otherwise specified, all voltages are re-

9.1.5 Pin input voltage

ferred to V

.

SS

The input voltage measurement on a pin of the de-

vice is described in Figure 58.

9.1.1 Minimum and Maximum values

Unless otherwise specified the minimum and max-

imum values are guaranteed in the worst condi-

tions of ambient temperature, supply voltage and

frequencies by tests in production on 100% of the

Figure 58. Pin input voltage

devices with an ambient temperature at T =25°C

A

ST7 PIN

and T =T max (given by the selected temperature

A

range).

V

Data based on characterization results, design

simulation and/or technology characteristics are

indicated in the table footnotes and are not tested

in production. Based on characterization, the min-

imum and maximum values refer to sample tests

and represent the mean value plus or minus three

times the standard deviation (mean±3Σ).

IN

9.1.2 Typical values

Unless otherwise specified, typical data are based

on T =25°C, V =5V (for the 4.5V≤V ≤5.5V

A

DD

voltage range) and V =3.3V (for the 3V≤V ≤4V

DD

voltage range). They are given only as design

guidelines and are not tested.

9.1.3 Typical curves

Unless otherwise specified, all typical curves are

given only as design guidelines and are not tested.

9.1.4 Loading capacitor

The loading conditions used for pin parameter

measurement are shown in Figure 57.

Figure 57. Pin loading conditions

ST7 PIN

C

L

112/152

ST72C171

9.2 ABSOLUTE MAXIMUM RATINGS

Stresses above those listed as “absolute maxi-

mum ratings” may cause permanent damage to

the device. This is a stress rating only and func-

tional operation of the device under these condi-

tions is not implied. Exposure to maximum rating

conditions for extended periods may affect device

reliability.

9.2.1 Voltage Characteristics

Symbol

Ratings

Maximum value

6.5

Unit

V

- V

Supply voltage

DD

SS

V

1) & 2)

V

Input voltage on any pin

V_SS-0.3 to V_DD+0.3

IN

V

Electro-static discharge voltage (Human Body Model)

Electro-static discharge voltage (Machine Model)

see Section 9.7.2 Absolute Electri-

cal Sensitivity

ESD(HBM)

V

ESD(MM)

9.2.2 Current Characteristics

Symbol

Ratings

Maximum value

Unit

3)

I

Total current into V power lines (source)

80

VDD

DD

I

Total current out of V ground lines (sink)

SS

VSS

Output current sunk by any standard I/O and control pin

Output current sunk by any high sink I/O pin

Output current source by any I/Os and control pin

Injected current on ISPSEL pin

25

I

50

IO

- 25

± 5

± 20

mA

Injected current on RESET pin

2) & 4)

I

INJ(PIN)

Injected current on OSC1 and OSC2 pins

5) & 6)

Injected current on any other pin

2)

5)

ΣI

Total injected current (sum of all I/O and control pins)

INJ(PIN)

9.2.3 Thermal Characteristics

Symbol

Ratings

Value

Unit

T

Storage temperature range

-65 to +150

°C

STG

Maximum junction temperature

(see Section 10.2 THERMAL CHARACTERISTICS )

T

J

Notes:

1. Directly connecting the RESET and I/O pins to V or V could damage the device if an unintentional internal reset

DD

SS

is generated or an unexpected change of the I/O configuration occurs (for example, due to a corrupted program counter).

To guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7kΩ for

RESET, 10kΩ for I/Os). Unused I/O pins must be tied in the same way to V or V according to their reset configuration.

DD

SS

2. When the current limitation is not possible, the V absolute maximum rating must be respected, otherwise refer to

IN

I

specification. A positive injection is induced by V >V while a negative injection is induced by V <V

.

INJ(PIN)

IN

DD

IN

SS

3. All power (V ) and ground (V ) lines must always be connected to the external supply.

DD

SS

4. Negative injection disturbs the analog performance of the device. In particular, it induces leakage currents throughout

the device including the analog inputs. To avoid undesirable effects on the analog functions, care must be taken:

- Analog input pins must have a negative injection less than 0.8 mA (assuming that the impedance of the analog voltage

is lower than the specified limits)

- Pure digital pins must have a negative injection less than 1.6mA. In addition, it is recommended to inject the current as

far as possible from the analog input pins.

5. When several inputs are submitted to a current injection, the maximum ΣI

is the absolute sum of the positive

INJ(PIN)

and negative injected currents (instantaneous values). These results are based on characterisation with ΣI

maxi-

INJ(PIN)

mum current injection on four I/O port pins of the device.

6. True open drain I/O port pins do not accept positive injection.

113/152

ST72C171

9.3 OPERATING CONDITIONS

9.3.1 General Operating Conditions

Symbol

Parameter

Supply voltage

Conditions

Min

Max

5.5

16

8

Unit

V

see Figure 59 and Figure 60

3.2

V

DD

1)

V

≥4.5V

≥3.0V

0

DD

f

External clock frequency

MHz

OSC

1)

0

T

Ambient temperature range

-40

85

°C

A

Figure 59. f

Maximum Operating Frequency Versus V_DDSupply Voltage for FLASH devices

OSC

FUNCTIONALITY NOT GUARANTEED IN THIS AREA

3)

FOR TEMPERATURE HIGHER THAN 85°C

f

[MHz]

FUNCTIONALITY

GUARANTEED

IN THIS AREA

OSC

2)

16

FUNCTIONALITY

NOT GUARANTEED

IN THIS AREA

FUNCTIONALITY

NOT GUARANTEED

IN THIS AREA

8

4

1)

WITH RESONATOR

1

0

SUPPLY VOLTAGE [V]

2.5

3

3.2

3.5

3.85

4

4.5

5

5.5

Notes:

1. Guaranteed by construction. A/D operation and resonator oscillator start-up are not guaranteed below 1MHz.

3. FLASH programming tested in production at maximum T with two different conditions: V =5.5V, f =8MHz and

A

DD

CPU

V

=3V, f

=4MHz.

DD

CPU

114/152

ST72C171

OPERATING CONDITIONS (Cont’d)

9.3.2 Operating Conditions with Low Voltage Detector (LVD)

Subject to general operating conditions for V , f

, and T .

A

DD OSC

Conditions

High Threshold

1)

Symbol

Parameter

Min

Typ

Max

Unit

2)

4.10

3.75

3.25

4.30

3.90

3.35

4.50

4.05

3.45

Reset release threshold

2)

V

Med. Threshold

Low Threshold

IT+

(V rise)

DD

V

2)

High Threshold

Med. Threshold

Low Threshold

3.85

3.50

4.05

3.65

3.10

4.25

3.80

3.20

Reset generation threshold

V

IT-

(V fall)

4)

DD

3.00

200

0.2

LVD voltage threshold hysteresis

V

-V

250

300

50

mV

V/ms

ns

hyst

IT+ IT-

3)

Vt

V

rise time rate

POR

DD

2)

t

Filtered glitch delay on V

Not detected by the LVD

40

g(VDD)

DD

3)

Figure 60. High LVD Threshold Versus V_DDand f

for FLASH devices

OSC

FUNCTIONALITY AND RESET NOT GUARANTEED IN THIS AREA

FOR TEMPERATURES HIGHER THAN 85°C

f

[MHz]

FUNCTIONALITY

NOT GUARANTEED

IN THIS AREA

OSC

16

DEVICE UNDER

RESET

IN THIS AREA

FUNCTIONAL AREA

8

0

SUPPLY VOLTAGE [V]

V

≥3.85

IT-

2.5

3

3.5

4

4.5

5

5.5

3)

Figure 61. Medium LVD Threshold Versus V_DDand f

for FLASH devices

OSC

FUNCTIONALITY AND RESET NOT GUARANTEED IN THIS AREA

FOR TEMPERATURES HIGHER THAN 85°C

f

[MHz]

FUNCTIONALITY

NOT GUARANTEED

IN THIS AREA

OSC

16

DEVICE UNDER

RESET

IN THIS AREA

FUNCTIONAL AREA

8

0

SUPPLY VOLTAGE [V]

2.5

3

V

_IT-≥3.5V

4

4.5

5

5.5

2)4)

Figure 62. Low LVD Threshold Versus V_DDand f

for FLASH devices

OSC

FUNCTIONALITY NOT GUARANTEED IN THIS AREA

FOR TEMPERATURES HIGHER THAN 85°C

f

[MHz]

FUNCTIONALITY

NOT GUARANTEED

IN THIS AREA

OSC

16

DEVICE UNDER

RESET

IN THIS AREA

FUNCTIONAL AREA

8

0

SUPPLY VOLTAGE [V]

2.5

V

_IT-≥3

3.5

4

4.5

5

5.5

Notes:

1. LVD typical data are based on T =25°C. They are given only as design guidelines and are not tested.

A

2. Data based on characterization results, not tested in production.

3. The V rise time rate condition is needed to insure a correct device power-on and LVD reset. Not tested in production.

DD

4. If the low LVD threshold is selected, when V

falls below 3.2V, (V

minimum operating voltage), the device is guar-

DD

anteed to continue functioning until it goes into reset state. The specified V

min. value is necessary in the device power

on phase, but during a power down phase or voltage drop the device will function below this min. level.

115/152

ST72C171

9.4 SUPPLY CURRENT CHARACTERISTICS

The following current consumption specified for

the ST7 functional operating modes over tempera-

ture range does not take into account the clock

source current consumption. To get the total de-

vice consumption, the two current values must be

added (except for HALT mode for which the clock

is stopped).

Symbol

∆I

Parameter

Conditions

Max

Unit

Supply current variation vs. temperature

Constant V and f

10

%

DD(∆Ta)

DD

CPU

9.4.1 RUN and SLOW Modes

1)

2)

Symbol

Parameter

Conditions

Typ

Max

Unit

500

1500

5600

900

2500

9000

f

=1MHz, f

=500kHz

=2MHz

=8MHz

3)

OSC

CPU

Supply current in RUN mode

(see Figure 63)

=4MHz, f

CPU

=16MHz, f

CPU

150

250

670

450

550

1250

f

=1MHz, f

=31.25kHz

=125kHz

=500kHz

4)

OSC

CPU

Supply current in SLOW mode

(see Figure 64)

=4MHz, f

=16MHz, f

CPU

I

µA

DD

300

970

3600

550

1350

4500

f

=1MHz, f

=500kHz

=2MHz

=8MHz

3)

OSC

CPU

Supply current in RUN mode

(see Figure 63)

=4MHz, f

CPU

=16MHz, f

CPU

100

170

420

250

300

700

f

=1MHz, f

=31.25kHz

=125kHz

=500kHz

OSC

CPU

Supply current in SLOW mode

(see Figure 64)

=4MHz, f

CPU

=16MHz, f

CPU

Figure 63. Typical IDD in RUN vs. fCPU

Figure 64. Typical I in SLOW vs. f

DD

CPU

IDD [mA]

0.8

IDD [mA]

7

500kHz

250kHz

125kHz

31.25kHz

8MHz

4MHz

2MHz

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

6

5

4

3

2

1

0

500kHz

3.2

3.5

4

4.5

5

5.5

3.2

3.5

4

4.5

5

5.5

VDD [V]

Notes:

1. Typical data are based on T =25°C, V =5V (4.5V≤V ≤5.5V range) and V =3.4V (3.2V≤V ≤3.6V range).

A

DD

2. Data based on characterization results, tested in production at V max. and f

max.

DD

CPU

3. CPU running with memory access, all I/O pins in output mode with a static value at V or V (no load), all peripherals

DD

SS

in reset state; clock input (OSC1) driven by external square wave, CSS and LVD disabled.

4. SLOW mode selected with f

SS

based on f

divided by 32. All I/O pins in input mode with a static value at V or

OSC DD

CPU

V

(no load), all peripherals in reset state; clock input (OSC1) driven by external square wave, CSS and LVD disabled.

116/152

ST72C171

SUPPLY CURRENT CHARACTERISTICS (Cont’d)

9.4.2 WAIT and SLOW WAIT Modes

1)

2)

Symbol

Parameter

Conditions

Typ

Max

Unit

150

560

2200

280

900

3000

f

=1MHz, f

=500kHz

=2MHz

=8MHz

3)

OSC

CPU

Supply current in WAIT mode

(see Figure 65)

=4MHz, f

CPU

=16MHz, f

CPU

20

90

340

70

190

850

f

=1MHz, f

=31.25kHz

=125kHz

=500kHz

4)

OSC

CPU

Supply current in SLOW WAIT mode

(see Figure 66)

=4MHz, f

=16MHz, f

CPU

I

µA

DD

90

350

1370

200

550

1900

f

=1MHz, f

=500kHz

=2MHz

=8MHz

3)

OSC

CPU

Supply current in WAIT mode

=4MHz, f

CPU

(see Figure 65)

=16MHz, f

CPU

10

50

200

20

80

350

f

=1MHz, f

=31.25kHz

=125kHz

=500kHz

OSC

CPU

Supply current in SLOW WAIT mode

(see Figure 66)

=4MHz, f

CPU

=16MHz, f

CPU

Figure 65. Typical I in WAIT vs. f

Figure 66. Typical I in SLOW-WAIT vs. f

DD

CPU

DD

CPU

IDD [mA]

3

IDD [mA]

0.35

8MHz

4MHz

2MHz

500kHz

250kHz

125kHz

31.25kHz

0.3

0.25

0.2

2.5

2

1.5

1

0.15

0.1

0.5

0

0.05

0

3.2

3.5

4

4.5

5

5.5

3.2

3.5

4

4.5

5

5.5

VDD [V]

Notes:

1. Typical data are based on T =25°C, V =5V (4.5V≤V ≤5.5V range) and V =3.4V (3.2V≤V ≤3.6V range).

A

DD

2. Data based on characterization results, tested in production at V max. and f

max.

DD

CPU

3. All I/O pins in output mode with a static value at V or V (no load), all peripherals in reset state; clock input (OSC1)

DD

SS

driven by external square wave, CSS and LVD disabled.

4. SLOW-WAIT mode selected with f

based on f

divided by 32. All I/O pins in input mode with a static value at

OSC

CPU

V

or V (no load), all peripherals in reset state; clock input (OSC1) driven by external square wave, CSS and LVD

DD

SS

disabled.

117/152

ST72C171

SUPPLY CURRENT CHARACTERISTICS (Cont’d)

9.4.3 HALT Mode

1)

Symbol

Parameter

Conditions

=5.5V -40°C≤T ≤+85°C

Typ

Max

10

6

Unit

V

0

µA

DD

A

2)

I

Supply current in HALT mode

DD

=3.6V -40°C≤T ≤+85°C

DD

A

9.4.4 Supply and Clock Managers

The previous current consumption specified for

the ST7 functional operating modes over tempera-

ture range does not take into account the clock

source current consumption. To get the total de-

vice consumption, the two current values must be

added (except for HALT mode).

1)

3)

Symbol

Parameter

Conditions

Typ

Max

Unit

Supply current of internal RC oscillator

Supply current of external RC oscillator

500

525

750

4)

200

300

450

700

400

550

750

LP: Low power oscillator

I

DD(CK)

MP: Medium power oscillator

MS: Medium speed oscillator

HS: High speed oscillator

4) & 5)

Supply current of resonator oscillator

µA

1000

Clock security system supply current

LVD supply current

150

100

350

150

I

HALT mode

DD(LVD)

9.4.5 On-Chip Peripherals

Symbol

Parameter

Conditions

Typ

50

Unit

V

=3.4V

=5.0V

=3.4V

=5.0V

=3.4V

=5.0V

=3.4V

=5.0V

DD

6)

I

16-bit Timer supply current

f

=8MHz

=4MHz

DD(TIM)

CPU

ADC

150

250

350

250

350

800

1100

7)

I

SPI supply current

DD(SPI)

µA

2

8)

I

I C supply current

DD(I2C)

9)

I

ADC supply current when converting

DD(ADC)

Notes:

1. Typical data are based on T =25°C.

A

2. All I/O pins in input mode with a static value at V or V (no load), CSS and LVD disabled. Data based on charac-

DD

SS

CPU

terization results, tested in production at V max. and f

max.

DD

3. Data based on characterization results, not tested in production.

4. Data based on characterization results done with the external components specified in Section 9.5.3 and Section 9.5.4,

not tested in production.

5. As the oscillator is based on a current source, the consumption does not depend on the voltage.

6. Data based on a differential I measurement between reset configuration (timer counter running at f

/4) and timer

DD

CPU

counter stopped (selecting external clock capability). Data valid for one timer.

7. Data based on a differential I measurement between reset configuration and a permanent SPI master communica-

DD

tion (data sent equal to 55h).

8. Data based on a differential I measurement between reset configuration and I2C peripheral enabled (PE bit set).

DD

9. Data based on a differential I measurement between reset configuration and continuous A/D conversions.

DD

118/152

ST72C171

9.5 CLOCK AND TIMING CHARACTERISTICS

Subject to general operating conditions for V , f

, and T .

DD OSC

A

9.5.1 General Timings

1)

Symbol

Parameter

Conditions

Min

2

Typ

Max

Unit

t_CPU

ns

3

12

1500

22

t

Instruction cycle time

c(INST)

f

=8MHz

250

10

375

CPU

2)

t_CPU

µs

Interrupt reaction time

t

v(IT)

t

= ∆t

+ 10

=8MHz

1.25

2.75

v(IT)

c(INST)

CPU

9.5.2 External Clock Source

Symbol

Parameter

Conditions

Min

0.7xV

Typ

Max

Unit

V

OSC1 input pin high level voltage

OSC1 input pin low level voltage

V

DD

OSC1H

DD

SS

V

0.3xV

OSC1L

DD

t

3)

w(OSC1H)

see Figure 67

OSC1 high or low time

15

w(OSC1L)

ns

t

3)

r(OSC1)

OSC1 rise or fall time

15

f(OSC1)

I

OSCx Input leakage current

V

≤V ≤V

DD

±1

µA

L

SS

IN

Figure 67. Typical Application with an External Clock Source

90%

V

OSC1H

OSC1L

10%

t

w(OSC1H)

t

w(OSC1L)

f(OSC1)

r(OSC1)

OSC2

Not connected internally

f

OSC

EXTERNAL

CLOCK SOURCE

I

L

OSC1

ST72XXX

Notes:

1. Data based on typical application software.

2. Time measured between interrupt event and interrupt vector fetch. ∆t_c(INST)is the number of t_CPUcycles needed to finish

the current instruction execution.

3. Data based on design simulation and/or technology characteristics, not tested in production.

119/152

ST72C171

CLOCK AND TIMING CHARACTERISTICS (Cont’d)

9.5.3 Crystal and Ceramic Resonator Oscillators

The ST7 internal clock can be supplied with four

different Crystal/Ceramic resonator oscillators. All

the information given in this paragraph are based

on characterization results with specified typical

external componants. In the application, the reso-

nator and the load capacitors have to be placed as

close as possible to the oscillator pins in order to

minimize output distortion and start-up stabiliza-

tion time. Refer to the crystal/ceramic resonator

manufacturer for more details (frequency, pack-

age, accuracy...).

Symbol

Parameter

Conditions

Min

Max

Unit

MHz

kΩ

LP: Low power oscillator

1

2

4

8

MP: Medium power oscillator

MS: Medium speed oscillator

HS: High speed oscillator

>2

>4

>8

3)

f

Oscillator Frequency

OSC

16

R

Feedback resistor

20

40

F

R =200Ω

LP oscillator

MP oscillator

MS oscillator

HS oscillator

38

32

18

15

56

46

26

21

S

Recommanded load capacitances ver-

sus equivalent serial resistance of the

C

R =200Ω

L1

L2

S

pF

R =200Ω

S

crystal or ceramic resonator (R )

S

R =100Ω

S

V

=5V

LP oscillator

MP oscillator

MS oscillator

HS oscillator

40

50

100

250

130

300

550

820

DD

V =V

IN

SS

i

OSC2 driving current

µA

2

Typical Crystal or Ceramic Resonators

C

L2

t

L1

SU(osc)

Oscil.

2)

1)

[ms]

[pF] [pF]

Reference

Freq.

2MHz

4MHz

8MHz

16MHz

2MHz

4MHz

8MHz

16MHz

Characteristic

LP

MP

MS

HS

LP

S-200-30-30/50

SS3-400-30-30/30

SS3-800-30-30/30

SS3-1600-30-30/30

CSA2.00MG

∆f

=[±30ppm

,±30ppm ], Typ. R =200Ω

33 34 10~15

33 34 7~10

33 34 2.5~3

33 34 1~1.5

OSC

25°C

∆Ta

S

,±30ppm ], Typ. R =60Ω

∆Ta

S

,±30ppm ], Typ. R =25Ω

25°C

∆Ta

S

,±30ppm ], Typ. R =15Ω

25°C

∆Ta

S

=[±0.5%

,±0.3% ,±0.3%

,±x.x%

]

33 30

4.2

2.1

1.1

0.7

tolerance

∆Ta

aging

correl

MP

MS

HS

CSA4.00MG

,±0.3% ,±0.3%

∆Ta

CSA8.00MTZ

,±0.5% ,±0.3%

∆Ta

CSA16.00MXZ040

,±0.3% ,±0.3%

∆Ta

Figure 68. Typical Application with a Crystal or Ceramic Resonator

WHEN RESONATOR WITH

INTEGRATED CAPACITORS

i

2

f

OSC

C

L1

OSC1

OSC2

RESONATOR

R

F

C

L2

ST72XXX

Notes:

1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.

2. t is the typical oscillator start-up time measured between V =2.8V and the fetch of the first instruction (with a

SU(OSC)

DD

quick V ramp-up from 0 to 5V (<50µs).

DD

3. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small R value.

S

Refer to crystal/ceramic resonator manufacturer for more details.

120/152

ST72C171

CLOCK CHARACTERISTICS (Cont’d)

9.5.4 RC Oscillators

The ST7 internal clock can be supplied with an RC

oscillator. This oscillator can be used with internal

or external components (selectable by option

byte).

Symbol

Parameter

Conditions

see Figure 69

Min

3.60

1

Typ

Max

5.10

14

Unit

1)

Internal RC oscillator frequency

f

t

MHz

OSC

2)

External RC oscillator frequency

Internal RC Oscillator Start-up Time

3)

2.0

R

=47KΩ, C =”0”pF

1.0

6.5

0.7

3.0

EX

ms

=47KΩ, C =100pF

SU(OSC)

3)

EX

External RC Oscillator Start-up Time

=10KΩ, C =6.8pF

EX

=10KΩ, C =470pF

EX

4)

R

C

Oscillator external resistor

10

47

KΩ

EX

see Figure 70

5)

Oscillator external capacitor

0

470

pF

Figure 69. Typical Application with RC oscillator

ST72XXX

V

DD

INTERNAL RC

Current copy

EXTERNAL RC

+

-

V

f

REF

OSC

R

EX

OSC1

OSC2

C

EX

Voltage generator

C_EXdischarge

Figure 70. Typical Internal RC Oscillator

Figure 71. Typical External RC Oscillator

fosc [MHz]

Rex=10KOhm

-40°C

+25°C

+85°C

20

15

10

5

4.25

4.2

Rex=15KOhm

Rex=22KOhm

Rex=33KOhm

Rex=39KOhm

Rex=47KOhm

4.15

4.1

4.05

4

3.95

3.9

3.85

0

3.2

5.5

0

6.8

22

47

100

270

470

VDD [V]

Cex [pF]

Notes:

1. Data based on characterization results.

2. Guaranteed frequency range with the specified C and R ranges taking into account the device process variation.

EX

Data based on design simulation.

3. Data based on characterization results done with V nominal at 5V, not tested in production.

DD

4. R must have a positive temperature coefficient (ppm/°C), carbon resistors should therefore not be used.

EX

5. Important: when no external C is applied, the capacitance to be considered is the global parasitic capacitance which

EX

is subject to high variation (package, application...). In this case, the RC oscillator frequency tuning has to be done by

trying out several resistor values.

121/152

ST72C171

CLOCK CHARACTERISTICS (Cont’d)

9.5.5 Clock Security System (CSS)

Symbol

Parameter

Conditions

T =25°C, V =5.0V

Min

250

190

Typ

340

260

30

Max

430

330

Unit

kHz

A

DD

1)

f

Safe Oscillator Frequency

SFOSC

GFOSC

T =25°C, V =3.4V

A

DD

2)

f

Glitch Filtered Frequency

MHz

Figure 72. Typical Safe Oscillator Frequencies

fosc [kHz]

-40°C

+25°C

+85°C

400

350

300

250

200

3.2

5.5

VDD [V]

Note:

1. Data based on characterization results, tested in production between 90KHz and 500KHz.

2. Filtered glitch on the f signal. See functional description in section 4.3 on page 21 for more details.

OSC

122/152

ST72C171

9.6 MEMORY CHARACTERISTICS

Subject to general operating conditions for V , f

, and T unless otherwise specified.

DD OSC

A

9.6.1 RAM and Hardware Registers

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

1)

V

Data retention mode

HALT mode (or RESET)

1.6

V

RM

9.6.2 FLASH Program Memory

Symbol

Parameter

Conditions

Min

Typ

25

8

Max

70

Unit

°C

2)

0

T

Programming temperature range

Programming time for 1~16 bytes

A(prog)

3)

T =+25°C

25

ms

A

t

prog

T =+25°C

2.1

6.4

Programming time for 4 or 8kBytes

sec

A

5)

4)

t

Data retention

T =+55°C

20

years

cycles

ret

A

5)

N

Write erase cycles

T =+25°C

100

RW

A

Notes:

1. Minimum V

supply voltage without losing data stored in RAM (in in HALT mode or under RESET) or in hardware

DD

registers (only in HALT mode). Guaranteed by construction, not tested in production.

2. Data based on characterization results, tested in production at T =25°C.

A

3. Up to 16 bytes can be programmed at a time for a 4kBytes FLASH block (then up to 32 bytes at a time for an 8k device)

4. The data retention time increases when the T decreases.

A

5. Data based on reliability test results and monitored in production.

123/152

ST72C171

9.7 EMC CHARACTERISTICS

Susceptibility tests are performed on a sample ba-

sis during product characterization.

– ESD: Electro-Static Discharge (positive and neg-

ative) is applied on all pins of the device until a

functional disturbance occurs. This test con-

forms with the IEC 1000-4-2 standard.

9.7.1 Functional EMS

(Electro Magnetic Susceptibility)

– FTB: A Burst of Fast Transient voltage (positive

Based on a simple running application on the

product (toggling 2 LEDs through I/O ports), the

product is stressed by two electro magnetic events

until a failure occurs (indicated by the LEDs).

and negative) is applied to V and V through

DD

SS

a 100pF capacitor, until a functional disturbance

occurs. This test conforms with the IEC 1000-4-

4 standard.

A device reset allows normal operations to be re-

sumed.

1)

Symbol

Parameter

Conditions

=5V, T =+25°C, f

conforms to IEC 1000-4-2

Neg

Pos

Unit

Voltage limits to be applied on any I/O pin

to induce a functional disturbance

V

=8MHz

OSC

DD

A

V

-1

1

FESD

kV

Fast transient voltage burst limits to be ap-

V

=5V, T =+25°C, f

=8MHz

OSC

DD

A

V

plied through 100pF on V and V pins

-4

4

FFTB

DD

conforms to IEC 1000-4-4

to induce a functional disturbance

2)

Figure 73. EMC Recommended star network power supply connection

ST72XXX

10nF 0.1µF

V

DD

SS

ST7

DIGITAL NOISE

FILTERING

V

DD

POWER

SUPPLY

SOURCE

V

SSA

DDA

EXTERNAL

NOISE

FILTERING

0.1µF

Notes:

1. Data based on characterization results, not tested in production.

2. The suggested 10nF and 0.1µF decoupling capacitors on the power supply lines are proposed as a good price vs. EMC

performance tradeoff. They have to be put as close as possible to the device power supply pins. Other EMC recommen-

dations are given in other sections (I/Os, RESET, OSCx pin characteristics).

124/152

ST72C171

EMC CHARACTERISTICS (Cont’d)

9.7.2 Absolute Electrical Sensitivity

Machine Model Test Sequence

Based on three different tests (ESD, LU and DLU)

using specific measurement methods, the product

is stressed in order to determine its performance in

terms of electrical sensitivity. For more details, re-

fer to the AN1181 ST7 application note.

– C is loaded through S1 by the HV pulse gener-

ator.

L

– S1 switches position from generator to ST7.

– A discharge from C to the ST7 occurs.

L

– S2 must be closed 10 to 100ms after the pulse

delivery period to ensure the ST7 is not left in

charge state. S2 must be opened at least 10ms

prior to the delivery of the next pulse.

9.7.2.1 Electro-Static Discharge (ESD)

Electro-Static Discharges (3 positive then 3 nega-

tive pulses separated by 1 second) are applied to

the pins of each sample according to each pin

combination. The sample size depends of the

number of supply pins of the device (3 parts*(n+1)

supply pin). Two models are usually simulated:

Human Body Model and Machine Model. This test

conforms to the JESD22-A114A/A115A standard.

See Figure 74 and the following test sequences.

– R (machine resistance), in series with S2, en-

sures a slow discharge of the ST7.

Human Body Model Test Sequence

– C is loaded through S1 by the HV pulse gener-

L

ator.

– S1 switches position from generator to R.

– A discharge from C through R (body resistance)

L

to the ST7 occurs.

– S2 must be closed 10 to 100ms after the pulse

delivery period to ensure the ST7 is not left in

charge state. S2 must be opened at least 10ms

prior to the delivery of the next pulse.

Absolute Maximum Ratings

1)

Symbol

Ratings

Conditions

Maximum value

Unit

Electro-static discharge voltage

(Human Body Model)

T =+25°C

V

2000

A

ESD(HBM)

V

Electro-static discharge voltage

(Machine Model)

T =+25°C

V

200

A

ESD(MM)

Figure 74. Typical Equivalent ESD Circuits

S1

R=1500Ω

S1

HIGH VOLTAGE

PULSE

GENERATOR

HIGH VOLTAGE

PULSE

GENERATOR

ST7

C =100pF

S2

L

S2

C =200pF

L

HUMAN BODY MODEL

MACHINE MODEL

Notes:

1. Data based on characterization results, not tested in production.

125/152

ST72C171

EMC CHARACTERISTICS (Cont’d)

9.7.2.2 Static and Dynamic Latch-Up

– DLU: Electro-Static Discharges (one positive

then one negative test) are applied to each pin of

3 samples when the micro is running to assess

the latch-up performance in dynamic mode.

Power supplies are set to the typical values, the

oscillator is connected as near as possible to the

pins of the micro and the component is put in re-

set mode. This test conforms to the IEC1000-4-2

and SAEJ1752/3 standards and is described in

Figure 75. For more details, refer to the AN1181

ST7 application note.

– LU: 3 complementary static tests are required on

10 parts to assess the latch-up performance. A

supply overvoltage (applied to each power sup-

ply pin), a current injection (applied to each input,

output and configurable I/O pin) and a power

supply switch sequence are performed on each

sample. This test conforms to the EIA/JESD 78

IC latch-up standard. For more details, refer to

the AN1181 ST7 application note.

Electrical Sensitivities

1)

Symbol

LU

Parameter

Static latch-up class

Dynamic latch-up class

Conditions

Class

T =+25°C

A

T =+85°C

A

V

=5.5V, f

=4MHz, T =+25°C

DLU

A

DD

OSC

A

Figure 75. Simplified Diagram of the ESD Generator for DLU

R

=50MΩ

R =330Ω

D

CH

DISCHARGE TIP

V

DD

SS

HV RELAY

C =150pF

S

ST7

ESD

2)

DISCHARGE

RETURN CONNECTION

GENERATOR

Notes:

1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC spec-

ifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the

JEDEC criteria (international standard).

2. Schaffner NSG435 with a pointed test finger.

126/152

ST72C171

EMC CHARACTERISTICS (Cont’d)

9.7.3 ESD Pin Protection Strategy

Standard Pin Protection

To protect an integrated circuit against Electro-

Static Discharge the stress must be controlled to

prevent degradation or destruction of the circuit el-

ements. The stress generally affects the circuit el-

ements which are connected to the pads but can

also affect the internal devices when the supply

pads receive the stress. The elements to be pro-

tected must not receive excessive current, voltage

or heating within their structure.

To protect the output structure the following ele-

ments are added:

– A diode to V (3a) and a diode from V (3b)

DD

SS

– A protection device between V and V (4)

DD

SS

To protect the input structure the following ele-

ments are added:

– A resistor in series with the pad (1)

– A diode to V (2a) and a diode from V (2b)

DD

SS

– A protection device between V and V (4)

DD

SS

An ESD network combines the different input and

output ESD protections. This network works, by al-

lowing safe discharge paths for the pins subjected

to ESD stress. Two critical ESD stress cases are

presented in Figure 76 and Figure 77 for standard

pins and in Figure 78 and Figure 79 for true open

drain pins.

Figure 76. Positive Stress on a Standard Pad vs. V

SS

V

DD

(3a)

(3b)

(2a)

(1)

(4)

OUT

IN

Main path

(2b)

Path to avoid

V

SS

Figure 77. Negative Stress on a Standard Pad vs. V

DD

V

DD

(3a)

(3b)

(2a)

(1)

(4)

OUT

IN

Main path

(2b)

V

SS

127/152

ST72C171

EMC CHARACTERISTICS (Cont’d)

True Open Drain Pin Protection

Multisupply Configuration

When several types of ground (V , V

The centralized protection (4) is not involved in the

discharge of the ESD stresses applied to true

open drain pads due to the fact that a P-Buffer and

, ...) and

SSA

SS

power supply (V , V

, ...) are available for any

DD

DDA

reason (better noise immunity...), the structure

shown in Figure 80 is implemented to protect the

device against ESD.

diode to V

local protection between the pad and V

are not implemented. An additional

DD

(5a &

SS

5b) is implemented to completly absorb the posi-

tive ESD discharge.

Figure 78. Positive Stress on a True Open Drain Pad vs. V

SS

V

DD

Main path

(1)

Path to avoid

OUT

(4)

IN

(5a)

(5b)

(3b)

(2b)

V

SS

Figure 79. Negative Stress on a True Open Drain Pad vs. V

DD

V

DD

Main path

(1)

OUT

(4)

IN

(3b)

(2b)

V

SS

Figure 80. Multisupply Configuration

V

DD

V

DDA

V

DDA

V

SS

BACK TO BACK DIODE

BETWEEN GROUNDS

V

SSA

V

SSA

128/152

ST72C171

9.8 I/O PORT PIN CHARACTERISTICS

9.8.1 General Characteristics

Subject to general operating conditions for V , f

, and T unless otherwise specified.

DD OSC

A

1)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V

2)

V

Input low level voltage

0.3xV_DD

IL

2)

V

Input high level voltage

0.7xV_DD

IH

3)

V

Schmitt trigger voltage hysteresis

Input leakage current

400

mV

µA

hys

I

V

_SS≤V ≤V

DD

±1

L

IN

4)

I

Static current consumption

Floating input mode

200

250

230

S

V

=5V

70

120

200

5

DD

5)

R

Weak pull-up equivalent resistor

V =V

SS

kΩ

pF

ns

PU

IN

=3.3V

170

C

I/O pin capacitance

IO

6)

t

Output high to low level fall time

25

C =50pF

Between 10% and 90%

f(IO)out

r(IO)out

L

6)

t

Output low to high level rise time

25

7)

t

External interrupt pulse time

1

t

CPU

w(IT)in

Figure 81. Two typical Applications with unused I/O Pin

V

DD

ST72XXX

UNUSED I/O PORT

10kΩ

UNUSED I/O PORT

ST72XXX

Figure 82. Typical I vs. V with V =V

SS

PU

DD

IN

Ipu [µA]

70

Ta=-40°C

Ta=25°C

Ta=85°C

60

50

40

30

20

10

0

3.2

3.5

4

4.5

5

5.5

Vdd [V]

Notes:

1. Unless otherwise specified, typical data are based on T =25°C and V =5V.

A

DD

2. Data based on characterization results, not tested in production.

3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.

4. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for

example or an external pull-up or pull-down resistor (see Figure 81). Data based on design simulation and/or technology

characteristics, not tested in production.

5. The R

pull-up equivalent resistor is based on a resistive transistor (corresponding I current characteristics de-

PU

scribed in Figure 82). This data is based on characterization results, tested in production at V max.

DD

6. Data based on characterization results, not tested in production.

7. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external

interrupt source.

129/152

ST72C171

I/O PORT PIN CHARACTERISTICS (Cont’d)

9.8.2 Output Driving Current

Subject to general operating conditions for V , f

, and T unless otherwise specified.

A

DD OSC

Symbol

Parameter

Conditions

Min

Max

Unit

Output low level voltage for a standard I/O pin

when 8 pins are sunk at same time

(see Figure 83 and Figure 86)

I

=+5mA

=+2mA

=+20mA

=+8mA

=-5mA

=-2mA

1.2

IO

0.5

1.5

0.6

1)

V

OL

OH

Output low level voltage for a high sink I/O pin

when 4 pins are sunk at same time

(see Figure 85 and Figure 87)

V

Output high level voltage for an I/O pin

when 4 pins are sourced at same time

(see Figure 86 and Figure 88)

V

-1.8

DD

2)

V

-0.7

DD

Figure 83. Typical V at V =5V (standard)

Figure 85. Typical V -V

at V =5V

OL

DD

DD OH DD

Vol [V] at Vdd=5V

2

Vdd-Voh [V] at Vdd=5V

5.5

5

Ta=-40°C Ta=25°C Ta=85°C

1.5

4.5

4

1

Ta=-40°C Ta=85°C

Ta=25°C

3.5

3

0.5

0

2.5

2

0

2

4

6

8

10

-8

-6

-4

Iio [mA]

-2

0

Iio [mA]

Figure 84. Typical V at V =5V (high-sink)

OL

DD

Vol [V] at Vdd=5V

1.5

Ta=-40°C Ta=25°C Ta=85°C

1

0.5

0

5

10

15

20

25

30

Iio [mA]

Notes:

1. The I current sunk must always respect the absolute maximum rating specified in Section 9.2.2 and the sum of I

IO

(I/O ports and control pins) must not exceed I

.

VSS

2. The I current sourced must always respect the absolute maximum rating specified in Section 9.2.2 and the sum of

IO

I

(I/O ports and control pins) must not exceed I

. True open drain I/O pins does not have V

.

IO

VDD

OH

130/152

ST72C171

I/O PORT PIN CHARACTERISTICS (Cont’d)

Figure 86. Typical V vs. V (standard I/Os)

OL

DD

Ta=-40°C Ta=85°C

Vol [V] at Iio=2mA

0.45

Vol [V] at Iio=5mA

Ta=-40°C Ta=25°C Ta=85°C

1.4

1.3

1.2

1.1

1

0.9

0.8

0.7

0.6

0.5

Ta=25°C

0.4

0.35

0.3

0.25

0.2

3.2

3.5

4

4.5

5

5.5

3.2

3.5

4

4.5

5

5.5

Vdd [V]

Figure 87. Typical V vs. V (high-sink I/Os)

OL

DD

Vol [V] at Iio=8mA

0.5

Vol [V] at Iio=20mA

Ta=-40°C Ta=25°C Ta=85°C

1.4

1.3

1.2

1.1

1

0.45

0.4

0.35

0.3

0.9

0.8

0.7

0.6

0.5

0.25

0.2

3.2

3.5

4

4.5

5

5.5

3.2

3.5

4

4.5

5

5.5

Vdd [V]

Figure 88. Typical V -V vs. V

DD OH

DD

Vdd-Voh [V] at Iio=-2mA

Vdd-Voh [V] at Iio=-5mA

5

5.5

5

4

3

2

1

0

4.5

4

Ta=-40°C Ta=85°C

Ta=25°C

3.5

Ta=-40°C Ta=85°C

Ta=25°C

3

2.5

2

3.2

3.5

4

4.5

5

5.5

3.5

4

4.5

Vdd [V]

5

5.5

Vdd [V]

131/152

ST72C171

9.9 CONTROL PIN CHARACTERISTICS

9.9.1 Asynchronous RESET Pin

Subject to general operating conditions for V , f

, and T unless otherwise specified.

DD OSC

A

1)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V

2)

V

Input low level voltage

0.3xV_DD

IL

2)

V

Input high level voltage

0.7xV_DD

IH

3)

V

Schmitt trigger voltage hysteresis

400

0.68

0.28

40

mV

V

hys

4)

I =+5mA

0.95

0.45

60

Output low level voltage

IO

V

=5V

DD

OL

(see Figure 91, Figure 92)

I =+2mA

IO

V

=5V

20

80

DD

5)

R

Weak pull-up equivalent resistor

V =V

SS

kΩ

ON

IN

=3.4V

100

120

External pin or

internal reset sources

6

30

1/f

SFOSC

t

Generated reset pulse duration

w(RSTL)out

µs

6)

t

External reset pulse hold time

20

µs

h(RSTL)in

7)

Filtered glitch duration

100

ns

g(RSTL)in

8)

Figure 89. Typical Application with RESET pin

ST72XXX

V

DD

V

DD

INTERNAL

RESET CONTROL

R

ON

0.1µF

4.7kΩ

USER

EXTERNAL

RESET

8)

CIRCUIT

WATCHDOG RESET

LVD RESET

Notes:

1. Unless otherwise specified, typical data are based on T =25°C and V =5V.

A

DD

2. Data based on characterization results, not tested in production.

3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.

4. The I current sunk must always respect the absolute maximum rating specified in Section 9.2.2 and the sum of I

IO

(I/O ports and control pins) must not exceed I

.

VSS

5. The R

pull-up equivalent resistor is based on a resistive transistor (corresponding I

current characteristics de-

ON

scribed in Figure 90). This data is based on characterization results, not tested in production.

5. To guarantee the reset of the device, a minimum pulse has to be applied to RESET pin.

6. All short pulse applied on RESET pin with a duration below t

can be ignored.

h(RSTL)in

7. The reset network (the resistor and two capacitors) protects the device against parasitic resets, especially in a noisy

environment.

8. The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device

can be damaged when the ST7 generates an internal reset (LVD or watchdog).

132/152

ST72C171

CONTROL PIN CHARACTERISTICS (Cont’d)

Figure 90. Typical I vs. V with V =V

Figure 91. Typical V at V =5V (RESET)

OL DD

ON

DD

IN

SS

Ion [µA]

Vol [V] at Vdd=5V

1.5

Ta=-40°C Ta=85°C

Ta=25°C

200

Ta=-40°C

Ta=25°C

Ta=85°C

150

100

50

1

0.5

0

1

2

3

4

5

6

7

8

3.2

3.5

4

4.5

5

5.5

Iio [mA]

Vdd [V]

Figure 92. Typical V vs. V (RESET)

OL

DD

Vol [V] at Iio=5mA

Ta=-40°C Ta=85°C

Ta=25°C

Vol [V] at Iio=2mA

0.45

Ta=-40°C Ta=85°C

Ta=25°C

1.2

1

0.4

0.35

0.3

0.8

0.6

0.4

0.25

0.2

0.15

3.2

3.5

4

4.5

5

5.5

3.2

3.5

4

4.5

5

5.5

Vdd [V]

133/152

ST72C171

CONTROL PIN CHARACTERISTICS (Cont’d)

9.9.2 ISPSEL Pin

Subject to general operating conditions for V , f

, and T unless otherwise specified.

A

DD OSC

Symbol

Parameter

Conditions

Min

Max

Unit

V

1)

V

Input low level voltage

V

0.2

IL

IH

L

SS

1)

V

I

Input high level voltage

Input leakage current

V

-0.1 12.6

DD

V =V

±1

µA

IN

SS

2)

Figure 93. Two typical Applications with ISPSEL Pin

ISPSEL

PROGRAMMING

TOOL

10kΩ

ST72XXX

Notes:

1. Data based on design simulation and/or technology characteristics, not tested in production.

2. When the ISP Remote mode is not required by the application ISPSEL pin must be tied to V

.

SS

134/152

ST72C171

9.10 TIMER PERIPHERAL CHARACTERISTICS

Subject to general operating conditions for V

,

Refer to I/O port characteristics for more details on

the input/output alternate function characteristics

(output compare, input capture, external clock,

PWM output...).

DD

f

, and T unless otherwise specified.

OSC

A

9.10.1 Watchdog Timer

Symbol

Parameter

Watchdog time-out duration

Conditions

Min

12,288

1.54

Typ

Max

786,432

98.3

Unit

t_CPU

ms

t

w(WDG)

f_CPU=8MHz

9.10.2 8-Bit PWM Auto-reload Timer

Symbol

Parameter

Conditions

Min

1

Typ

Max

Unit

t

Input capture pulse time

t

w(ICAP)in

CPU

1

CPU

t

PWM resolution time

res(PWM)

f

=8MHz

125

0

ns

CPU

f

Timer external clock frequency

PWM repetition rate

f

/2

MHz

bit

EXT

CPU

f

0

PWM

CPU

Res

PWM resolution

8

PWM

9.10.3 16-Bit Timer

Symbol

Parameter

Conditions

Min

1

Typ

Max

Unit

t

Input capture pulse time

t

w(ICAP)in

CPU

2

CPU

t

PWM resolution time

res(PWM)

f

=8MHz

250

0

ns

CPU

f

Timer external clock frequency

PWM repetition rate

f

/4

MHz

bit

EXT

CPU

f

0

/4

CPU

PWM

Res

PWM resolution

16

PWM

135/152

ST72C171

9.11 COMMUNICATION INTERFACE CHARACTERISTICS

9.11.1 SPI - Serial Peripheral Interface

Refer to I/O port characteristics for more details on

the input/output alternate function characteristics

(SS, SCK, MOSI, MISO).

Subject to general operating conditions for V

,

DD

f

, and T unless otherwise specified.

OSC

A

Symbol

Parameter

Conditions

Min

/128

0.0625

Max

Unit

Master

Slave

f

/4

CPU

2

CPU

f

=8MHz

f

CPU

SCK

SPI clock frequency

MHz

1/t

f

/2

c(SCK)

CPU

0

f

4

CPU

t

r(SCK)

f(SCK)

SPI clock rise and fall time

see I/O port pin description

t

SS setup time

SS hold time

Slave

120

su(SS)

t

h(SS)

t

Master

Slave

100

90

w(SCKH)

SCK high and low time

Data input setup time

Data input hold time

w(SCKL)

t

Master

Slave

100

su(MI)

t

su(SI)

ns

t

Master

Slave

100

h(MI)

t

h(SI)

t

Data output access time

Data output disable time

Data output valid time

Data output hold time

Data output valid time

Data output hold time

Slave

0

120

240

120

a(SO)

t

dis(SO)

t

v(SO)

h(SO)

v(MO)

h(MO)

Slave (after enable edge)

t

0

t

0.25

Master (before capture edge)

t

CPU

t

Figure 94. SPI Slave Timing Diagram with CPHA=0 ³⁾

SS

INPUT

t

su(SS)

c(SCK)

t

h(SS)

CPHA=0

CPOL=0

CPHA=0

CPOL=1

t

w(SCKH)

w(SCKL)

t

dis(SO)

a(SO)

v(SO)

h(SO)

t

r(SCK)

t

f(SCK)

see

note 2

MISO

OUTPUT

INPUT

MSB OUT

see note 2

BIT6 OUT

LSB OUT

t

h(SI)

su(SI)

LSB IN

MSB IN

BIT1 IN

MOSI

Notes:

1. Data based on design simulation and/or characterisation results, not tested in production.

2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has

its alternate function capability released. In this case, the pin status depends on the I/O port configuration.

3. Measurement points are done at CMOS levels: 0.3xV and 0.7xV

.

DD

136/152

ST72C171

COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d)

Figure 95. SPI Slave Timing Diagram with CPHA=1¹⁾

SS

INPUT

t

su(SS)

c(SCK)

t

h(SS)

CPHA=0

CPOL=0

CPHA=0

CPOL=1

t

w(SCKH)

w(SCKL)

t

dis(SO)

a(SO)

t

h(SO)

v(SO)

t

r(SCK)

f(SCK)

see

note 2

see

note 2

MISO

OUTPUT

HZ

MSB OUT

BIT6 OUT

LSB OUT

t

h(SI)

su(SI)

MSB IN

LSB IN

BIT1 IN

MOSI

INPUT

Figure 96. SPI Master Timing Diagram ¹⁾

SS

INPUT

t

c(SCK)

CPHA=0

CPOL=0

CPHA=0

CPOL=1

CPHA=1

CPOL=0

CPHA=1

CPOL=1

t

w(SCKH)

t

r(SCK)

t

w(SCKL)

t

f(SCK)

t

h(MI)

su(MI)

MISO

MOSI

INPUT

MSB IN

h(MO)

BIT6 IN

LSB IN

t

v(MO)

MSB OUT

LSB OUT

see note 2

BIT6 OUT

see note 2

OUTPUT

Notes:

1. Measurement points are done at CMOS levels: 0.3xV and 0.7xV

.

DD

2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has

its alternate function capability released. In this case, the pin status depends of the I/O port configuration.

137/152

ST72C171

COMMUNICATIONS INTERFACE CHARACTERISTICS (Cont’d)

9.11.2 SCI - Serial Communications Interface

Subject to general operating conditions for V

Refer to I/O port characteristics for more details on

the input/output alternate function characteristics

(RDI and TDO).

,

DD

f

, and T unless otherwise specified.

OSC

A

Conditions

Baud

Rate

Symbol

Parameter

Standard

Unit

Accuracy

vs. Standard

Prescaler

f

CPU

Conventional Mode

TR (or RR)=64, PR=13

TR (or RR)=16, PR=13

TR (or RR)= 8, PR=13

TR (or RR)= 4, PR=13

TR (or RR)= 2, PR=13

TR (or RR)= 8, PR= 3

TR (or RR)= 1, PR=13

300

~300.48

1200 ~1201.92

2400 ~2403.84

4800 ~4807.69

9600 ~9615.38

10400 ~10416.67

19200 ~19230.77

~0.16%

~0.79%

f

Tx

Communication frequency 8MHz

Hz

Rx

Extended Mode

ETPR (or ERPR) = 13

38400 ~38461.54

14400 ~14285.71

Extended Mode

ETPR (or ERPR) = 35

138/152

ST72C171

9.12 8-BIT ADC CHARACTERISTICS

Subject to general operating conditions for V , f

, and T unless otherwise specified.

DD OSC

A

1)

Symbol

Parameter

ADC clock frequency

Conversion range voltage

External input resistor

Conditions

Min

Typ

Max

Unit

f

4

MHz

ADC

2)

V

R

V

AIN

SSA

DDA

3)

10

kΩ

pF

C

Internal sample and hold capacitor

Stabilization time after ADC enable

Conversion time (Sample+Hold)

6

ADC

4)

t

0

STAB

µs

3

f

=8MHz, f

=4MHz

ADC

CPU

t

- Sample capacitor loading time

- Hold conversion time

4

8

ADC

1/f

ADC

Figure 97. Typical Application with ADC

V

DD

V

T

0.6V

R

AIN

AINx

V

AIN

ADC

V

0.6V

T

C

~2pF

I

L

±1µA

IO

V

DD

V

DDA

SSA

0.1µF

ST72XXX

Notes:

1. Unless otherwise specified, typical data are based on T =25°C and V -V =5V. They are given only as design guide-

A

DD SS

lines and are not tested.

2. When V and V

pins are not available on the pinout, the ADC refer to V and V .

SS

DDA

SSA

DD

3. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10kΩ). Data

based on characterization results, not tested in production.

4. The stabilization time of the AD converter is masked by the first t

always valid.

. The first conversion after the enable is then

LOAD

139/152

ST72C171

8-BIT ADC CHARACTERISTICS (Cont’d)

ADC Accuracy

Symbol

|E |

Parameter

Conditions

Min

Max

1

Unit

1)

Total unadjusted error

T

1)

-0.5

0.5

E

Offset error

O

G

3)

V

=5.0V,

1)

DD

LSB

Gain Error

f

=8MHz

CPU

1)

|E |

Differential linearity error

D

1)

|E |

Integral linearity error

L

Figure 98. ADC Accuracy Characteristics

Digital Result ADCDR

E

G

(1) Example of an actual transfer curve

(2) The ideal transfer curve

(3) End point correlation line

255

V

– V

254

253

DDA

SSA

1LSB

= ----------------------------------------

IDEAL

256

(2)

E =Total Unadjusted Error: maximum deviation

T

E

between the actual and the ideal transfer curves.

T

(3)

7

6

5

4

3

2

1

E =Offset Error: deviation between the first actual

O

transition and the first ideal one.

(1)

E =Gain Error: deviation between the last ideal

G

transition and the last actual one.

E

O

E

L

E =Differential Linearity Error: maximum deviation

D

between actual steps and the ideal one.

E =Integral Linearity Error: maximum deviation

L

E

between any actual transition and the end point

correlation line.

D

1 LSB

IDEAL

V

(LSB

)

IDEAL

in

0

1

2

3

4

5

6

7

253 254 255 256

V

DDA

SSA

Notes:

1. ADC Accuracy vs. Negative Injection Current:

For I =0.8mA, the typical leakage induced inside the die is 1.6µA and the effect on the ADC accuracy is a loss of 1 LSB

INJ-

for each 10KΩ increase of the external analog source impedance. This effect on the ADC accuracy has been observed

under worst-case conditions for injection:

- negative injection

- injection to an Input with analog capability, adjacent to the enabled Analog Input

- at 5V V supply, and worst case temperature.

DD

3. Data based on characterization results over the whole temperature range, monitored in production.

140/152

ST72C171

9.13 OP-AMP Module Characteristics

These op-amp specific values take precedence over any generic values given elsewhere in the docu-

ment.

o

(T =25 C, V_DD- V = 5 V ).

SS

SPGA1 / SPGA2 - Software Programmable Gain Operational Amplifiers

Symbol Parameter

Condition

Min

Typ

Max

Unit

|Vio|

Input Offset Voltage

Supply Current per amplifier

3

10

mV

V

load

=5.0V, A

=1, no

VCL

2)

DD

I

0.8

2

mA

1)

CC

3)

CMR

SVR

Common Mode Rejection Ratio

Supply Voltage Rejection Ratio

Voltage Gain

70

dB

V/mV

V

3)

70

3)

Avd

(R =1KΩ)

100

4.9

L

V

High Level Ouput Voltage

Low Level Ouput Voltage

(R =10KΩ) V =5V

L DD

OH

OL

(R =10KΩ) V =5V

0.10

V

L

DD

Short circuit Current Sourced

Short circuit Current Sunk

Vo= 5V connected to V

Vo= 0V connected to V

45

70

mA

SS

I

SC 3)

DD

GPB

Gain Bandwidth Product

4

1

MHz

V/µs

+

5)

1)

SR

Slew Rate

A

=1

VCL

-

5)

1)

SR

Slew Rate

=1

V/µs

VCL

3)

–1

en

Thermal Noise

Phase margin

50

nV Hz

3)

Φm

40

55

10

Degrees

pF

4)

Cin

Input Capacitance

Common Mode Input Voltage

Range

V

0.2

-

V

+0.2

4)

SS

DD

V

icm

Reference Voltage (V

step) Precision

/8

DDA

∆VRef

∆V

±10

%

Band Gap Precision

±10

%

BG

∆Gain

Programmable Gain Precision

1) A

= Closed loop gain (repeater configuration)

VCL

2) Tested with positve input connected to internal band gap (reference voltage enabled) and negative in-

put floating.

3) Data based on characterization, not tested in production

4) Data guaranteed by design, not tested in production

5) Slew rate is the rate of change from 10% to 90% of the output voltage step.

141/152

ST72C171

OP-AMP MODULE CHARACTERISTICS (Cont’d)

OA3 Operational Amplifier

Symbol Parameter

Condition

Min

Typ

Max

Unit

|Vio|

Input Offset Voltage

3

10

mV

V

load

=5.0V, A

=1, no

VCL

DD

1)

I

Supply Current per amplifier

300

500

µA

CC

2)

CMR

SVR

Common Mode Rejection Ratio

Supply Voltage Rejection Ratio

Voltage Gain

70

dB

V/mV

V

2)

70

2)

Avd

(R =1KΩ)

100

4.9

L

V

High Level Ouput Voltage

Low Level Ouput Voltage

(R =10KΩ) V

=5V

OH

OL

L

DDA

V

(R =10KΩ) V

0.10

V

L

DDA

Short circuit Current Sourced

Short circuit Current Sunk

Vo= 1 connected to V

Vo= 0 connected to V

45

70

mA

SS

2)

I

SC

DD

GPB

Gain Bandwidth Product

6

1

MHz

V/µs

+

4)

1)

SR

Slew Rate

A

=1

VCL

-

4)

1)

SR

Slew Rate

=1

V/µs

VCL

2)

–1

en

Thermal Noise

Phase margin

50

nV Hz

2)

Φm

40

55

10

Degrees

pF

3)

Cin

Input Capacitance

Common Mode Input Voltage

Range

V

0.2

-

V

+0.2

3)

SS

DD

V

icm

1) A

= Closed loop gain (repeater configuration)

VCL

2) Data based on characterization, not tested in production

3) Data guaranteed by design, not tested in production

4) Slew rate is the rate of change from 10% to 90% of the output voltage step.

142/152

ST72C171

9.13.1 Typical Phase Gain vs. Frequency

Figure 99. Gain vs Frequency

60

40

180

150

120

90

20

0

60

30

0

-30

-60

-90

-120

-20

-40

1.00E+3

1.00E+4

1.00E+5

1.00E+6

1.00E+7

Gain (dB)

Phase (Deg)

load RL=2Kohm CL= 120pF VDD=5V

9.13.2 Typical Total Harmonic Distorsion

average value of V /2. This signal is input to the

SPGA configured in non-inverter mode with a gain

of 1. The SPGA output is loaded with a 1K resistor.

DD

Figure 100 shows three typical curves for different

V

values. This characterisation has been done

A

DD

at T 25°C using a 1 kHz sine wave signal with an

Figure 100. Total Harmonic Distorsion vs Vout

0.2

0.15

0.1

0.05

0

Vd d =6 V

Vd d =5 V

Vd d =3 V

0

1

2

3

4

5

6

7

VOUT pe a k-pe a k (V)

RL =10Kohm, F= 1KHz

143/152

ST72C171

10 GENERAL INFORMATION

10.1 PACKAGE MECHANICAL DATA

Figure 101. 32-Pin Shrink Plastic Dual In Line Package

mm

inches

Dim.

A

E

Min Typ Max Min Typ Max

3.56 3.76 5.08 0.140 0.148 0.200

See Lead Detail

A1 0.51

A2 3.05 3.56 4.57 0.120 0.140 0.180

0.36 0.46 0.58 0.014 0.018 0.023

b1 0.76 1.02 1.40 0.030 0.040 0.055

0.020

C

b

e_A

b1

b

C

D

E

0.20 0.25 0.36 0.008 0.010 0.014

27.43 27.94 28.45 1.080 1.100 1.120

9.91 10.41 11.05 0.390 0.410 0.435

e

B

e

3

D

E1 7.62 8.89 9.40 0.300 0.350 0.370

A

2

e

eA

eB

L

1.78

0.070

0.400

N

10.16

A

L

E

1

12.70

0.500

A

1

2.54 3.05 3.81 0.100 0.120 0.150

e

Number of Pins

VR01725J

1

N/2

N

32

Figure 102. 34-Pin Small Outline

mm

inches

Dim.

Min Typ Max Min Typ Max

A

2.46

2.64 0.097

0.29 0.005

0.48 0.014

0.32 0.0091

18.06 0.698

7.59 0.292

0.104

0.0115

0.019

0.0125

0.711

0.299

A1 0.13

B

C

D

E

e

0.36

0.23

0.10mm

.004

seating plane

17.73

7.42

1.02

0.040

H

h

10.16

0.64

10.41 0.400

0.74 0.025

0°

0.410

0.029

8°

K

L

0.61

1.02 0.024

0.040

Number of Pins

N

34

SO34S

144/152

ST72C171

10.2 THERMAL CHARACTERISTICS

Symbol

Ratings

Value

Unit

Package thermal resistance (junction to ambient)

SDIP32

SO34

R

60

70

°C/W

thJA

1)

P

Power dissipation

Maximum junction temperature

500

150

mW

°C

D

2)

T

Jmax

Notes:

1. The power dissipation is obtained from the formula P =P +P

where P

is the chip internal power (I xV

)

D

INT

PORT

INT

DD DD

and P

is the port power dissipation determined by the user.

PORT

2. The average chip-junction temperature can be obtained from the formula T = T + P x RthJA.

J

A

D

145/152

ST72C171

10.3 SOLDERING AND GLUEABILITY INFORMATION

Recommended soldering information given only

as design guidelines in Figure 103 and Figure 104.

Recommended glue for SMD plastic packages

dedicated to molding compound with silicone:

■ Heraeus: PD945, PD955

■ Loctite: 3615, 3298

Figure 103. Recommended Wave Soldering Profile (with 37% Sn and 63% Pb)

250

COOLING PHASE

(ROOM TEMPERATURE)

5 sec

200

150

100

50

SOLDERING

PHASE

80°C

Temp. [°C]

PREHEATING

PHASE

Time [sec]

0

20

40

60

80

100

120

140

160

Figure 104. Recommended Reflow Soldering Oven Profile (MID JEDEC)

250

Tmax=220+/-5°C

for 25 sec

200

150

100

50

150 sec above 183°C

90 sec at 125°C

Temp. [°C]

ramp down natural

2°C/sec max

ramp up

2°C/sec for 50sec

Time [sec]

0

100

200

300

400

10.4 PACKAGE/SOCKET FOOTPRINT PROPOSAL

Table 23. Suggested List of SDIP32 Socket Types

Same

Footprint

Package / Probe

Adaptor / Socket Reference

Socket Type

Textool

SDIP32

EMU PROBE

TEXTOOL

232-1291-00

X

Table 24. Suggested List of SO34 Socket Types

Same

Footprint

Package / Probe

Adaptor / Socket Reference

Socket Type

N/A

Emulator Probe includes an adapter with S034 footprint to be sol-

dered on user PCB

SO34 EMU PROBE

X

146/152

ST72C171

0: Clock filter enabled

1: Clock filter disabled

11 DEVICE CONFIGURATION AND

ORDERING INFORMATION

The device is available for production a user pro-

grammable version (FLASH). FLASH devices are

shipped to customers with a default content (FFh).

FLASH devices have to be configured by the cus-

tomer using the Option Bytes.

Bit 6:4 = OSC[2:0] Oscillator selection

These three option bits can be used to select the

main oscillator as shown in Table 25.

Bit 3:2 = LVD[1:0] Low voltage detection selection

These option bits enable the LVD block with a se-

lected threshold as shown in Table 26.

11.1 OPTION BYTES

The two option bytes allow the hardware configu-

ration of the microcontroller to be selected.

The option bytes have no address in the memory

map and can be accessed only in programming

mode (for example using a standard ST7 program-

ming tool). The default content of the FLASH is

fixed to FFh.

In masked ROM devices, the option bytes are

fixed in hardware by the ROM code (see option

list).

Bit 1 = WDG HALT Watchdog and halt mode

This option bit determines if a RESET is generated

when entering HALT mode while the Watchdog is

active.

0: No Reset generation when entering Halt mode

1: Reset generation when entering Halt mode

Bit 0 = WDG SW Hardware or software watchdog

This option bit selects the watchdog type.

0: Hardware (watchdog always enabled)

USER OPTION BYTE 0

Bit 7:1 = Reserved, must always be 1.

1: Software (watchdog to be enabled by software)

Table 25. Main Oscillator Configuration

Bit 1= OA3E Op-Amp 3 Enable

This option bit enables or disables the third Op-

Amp of the on-chip Op-Amp Module.

0: OE3 disabled

Selected Oscillator

External Clock (Stand-by)

~4 MHz Internal RC

OSC2 OSC1 OSC0

1

0

1

0

1

0

1

0

X

1

0

1

0

1: OE3 enabled

1~14 MHz External RC

Low Power Resonator (LP)

Medium Power Resonator (MP)

Medium Speed Resonator (MS)

High Speed Resonator (HS)

Bit 0 = FMP Full memory protection.

This option bit enables or disables external access

to the internal program memory (read-out protec-

tion). Clearing this bit causes the erasing (to 00h)

of the whole memory (including the option byte).

0: Program memory not read-out protected

1: Program memory read-out protected

Table 26. LVD Threshold Configuration

Configuration

LVD1 LVD0

1

0

1

0

1

0

LVD Off

USER OPTION BYTE 1

Highest Voltage Threshold ( 4.50V)

Medium Voltage Threshold ( 4.05V)

Lowest Voltage Threshold ( 3.45V)

Bit 7 = CFC Clock filter control on/off

This option bit enables or disables the clock filter

(CF) features.

USER OPTION BYTE 0

USER OPTION BYTE 1

7

0

7

0

OSC OSC OSC

WDG WDG

HALT SW

Reserved

OA3E FMP CFC

LVD1 LVD0

2

1

0

Default

Value

1

0

1

0

1

147/152

ST72C171

11.2 DEVICE ORDERING INFORMATION

Figure 105. FLASH User Programmable Device Type

TEMP.

PACKAGE RANGE

DEVICE

6= industrial -40 to +85 °C

B= Plastic DIP

M= Plastic SOIC

ST72C171K2

148/152

ST72C171

11.3 DEVELOPMENT TOOLS

STmicroelectronics offers a range of hardware

and software development tools for the ST7 micro-

controller family. Full details of tools available for

the ST7 from third party manufacturers can be ob-

tain from the STMicroelectronics Internet site:

http//mcu.st.com.

STMicroelectronics Tools

Two types of development tool are offered by ST,

all of them connect to a PC via a parallel (LPT)

port: see Table 27 and Table 28 for more details.

Third Party Tools

■ ACTUM

■ BP

■ COSMIC

■ CMX

■ DATA I/O

■ HITEX

■ HIWARE

■ ISYSTEM

■ KANDA

■ LEAP

Tools from these manufacturers include C compli-

ers, emulators and gang programmers.

Table 27. STMicroelectronic Tool Features

1)

In-Circuit Emulation

Programming Capability

Software Included

ST7 CD ROM with:

Yes, powerful emulation

ST7 HDS2 Emulator

features including trace/

logic analyzer

No

– ST7 Assembly toolchain

– STVD7 and WGDB7 powerful

Source Level Debugger for Win

3.1, Win 95 and NT

– C compiler demo versions

– ST Realizer for Win 3.1 and Win

95.

Yes (All packages),support

also ISP

ST7 Programming Board

No

1)

– Windows Programming Tools

for Win 3.1, Win 95 and NT

Table 28. Dedicated STMicroelectronics Development Tools

Supported Product

ST7 HDS2 Emulator

ST7 Programming Board

ST7MDT6-EPB2/EU

ST7MDT6-EPB2/US

ST7MDT6-EPB2/UK

ST7MDT6-EMU2B

ST72C171K2,

Note:

1. In-Situ Programming (ISP) interface for FLASH devices.

149/152

ST72C171

11.4 ST7 APPLICATION NOTES

IDENTIFICATION

DESCRIPTION

PROGRAMMING AND TOOLS

AN985

AN986

EXECUTING CODE IN ST7 RAM

USING THE ST7 INDIRECT ADDRESSING MODE

AN987

ST7 IN-CIRCUIT PROGRAMMING

AN988

AN989

STARTING WITH ST7 ASSEMBLY TOOL CHAIN

STARTING WITH ST7 HIWARE C

AN1039

AN1064

AN1106

EXAMPLE DRIVERS

AN969

AN970

AN971

AN972

ST7 MATH UTILITY ROUTINES

WRITING OPTIMIZED HIWARE C LANGUAGE FOR ST7

TRANSLATING ASSEMBLY CODE FROM HC05 TO ST7

ST7 SCI COMMUNICATION BETWEEN THE ST7 AND A PC

ST7 SPI COMMUNICATION BETWEEN THE ST7 AND E²PROM

ST7 I²C COMMUNICATION BETWEEN THE ST7 AND E²PROM

ST7 SOFTWARE SPI MASTER COMMUNICATION

AN973

AN974

AN976

AN979

SCI SOFTWARE COMMUNICATION WITH A PC USING ST72251 16-BIT TIMER

REAL TIME CLOCK WITH THE ST7 TIMER OUTPUT COMPARE

DRIVING A BUZZER USING THE ST7 PWM FUNCTION

DRIVING AN ANALOG KEYBOARD WITH THE ST7 ADC

ST7 KEYPAD DECODING TECHNIQUES, IMPLEMENTING WAKE-UP ON KEYSTROKE

USING THE ST7 USB MICROCONTROLLER

USING ST7 PWM SIGNAL TO GENERATE ANALOG OUTPUT (SINUSOID)

ST7 ROUTINE FOR I²C SLAVE MODE MANAGEMENT

MULTIPLE INTERRUPT SOURCES MANAGEMENT FOR ST7 MCUS

ST7 SOFTWARE IMPLEMENTATION OF I²C BUS MASTER

ST7 UART EMULATION SOFTWARE

MANAGING RECEPTION ERRORS WITH THE ST7 SCI PERIPHERAL

ST7 SOFTWARE LCD DRIVER

ST7 TIMER PWM DUTY CYCLE SWITCH FOR TRUE 0% or 100% DUTY CYCLE

DESCRIPTION OF THE ST72141 MOTOR CONTROL

ST72141 BLDC MOTOR CONTROL SOFTWARE AND FLOWCHART EXAMPLE

PERMANENT MAGNET DC MOTOR DRIVE.

BRUSHLESS DC MOTOR DRIVE WITH ST72141

AN980

AN1017

AN1041

AN1042

AN1044

AN1045

AN1046

AN1047

AN1048

AN1078

AN1082

AN1083

AN1129

AN1130

AN1148

AN1149

AN1180

AN1182

USING THE ST7263 FOR DESIGNING A USB MOUSE

HANDLING SUSPEND MODE ON A USB MOUSE

USING THE ST7263 KIT TO IMPLEMENT A USB GAME PAD

USING THE ST7 USB LOW-SPEED FIRMWARE

PRODUCT OPTIMIZATION

AN982

USING CERAMIC RESONATORS WITH THE ST7

AN1014

AN1070

AN1179

HOW TO MINIMIZE THE ST7 POWER CONSUMPTION

ST7 CHECKSUM SELFCHECKING CAPABILITY

PROGRAMMING ST7 FLASH MICROCONTROLLERS IN REMOTE ISP

PRODUCT EVALUATION

AN910

ST7 AND ST9 PERFORMANCE BENCHMARKING

AN990

ST7 BENEFITS VERSUS INDUSTRY STANDARD

ST7 / ST10U435 CAN-do SOLUTIONS FOR CAR MULTIPLEXING

BENCHMARK ST72 VS PC16

AN1086

AN1150

AN1151

PERFORMANCE COMPARISON BETWEEN ST72254 & PC16F8

11.5 TO GET MORE INFORMATION

To get the latest information on this product please use the ST web server: http://mcu.st.com/

150/152

ST72C171

12 SUMMARY OF CHANGES

Description of the changes between the current release of the specification and the previous one.

Revision

Main changes

Date

1.4

Added Figure 99 and Figure 100.

Oct-00

151/152

ST72C171

Notes:

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics

Purchase of I²C Components by STMicroelectronics conveys a license under the Philips I²C Patent. Rights to use these components in an

I²C system is granted provided that the system conforms to the I²C Standard Specification as defined by Philips.

STMicroelectronics Group of Companies

Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain

Sweden - Switzerland - United Kingdom - U.S.A.

http://www.st.com

152/152


型号：	ST72C171
厂家：	ST
描述：	8-BIT MCU with 8K FLASH, ADC, WDG, SPI, SCI, TIMERS SPGAs Software Programmable Gain Amplifiers, OP-AMP 8位MCU具有8K闪存， ADC ， WDG ， SPI ， SCI ，定时器SPGAs软件可编程增益放大器，OP -AMP 闪存放大器
文件：	总152页 (文件大小：1379K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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