ST72C314J4B7 [STMICROELECTRONICS]
8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES; 8位MCU单电压闪存， ADC ， 16位定时器， SPI ， SCI INTERFACES
| 型号： | ST72C314J4B7 |
| 厂家： | 
ST |
| 描述： | 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES |
| 文件： | 总125页 (文件大小：769K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ST72334J/N,
ST72314J/N, ST72124J
8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY,
ADC, 16-BIT TIMERS, SPI, SCI INTERFACES
PRODUCT PREVIEW
■ 8K or 16K Program memory
(ROM or Single voltage FLASH)
with read-out protection
■ 256-bytes EEPROM Data memory
■ In-Situ Programming (Remote ISP)
■ Enhanced Reset System
■ Low voltage supply supervisor with
3 programmable levels
■ Low consumption resonator or RC oscillators
and by-pass for external clock source, with safe
control capabilities
PSDIP42
PSDIP56
■ 4 Power saving modes
■ Standard Interrupt Controller
■ 44 or 32 multifunctional bidirectional I/O lines:
– External interrupt capability (4 vectors)
– 21 or 19 alternate function lines
– 12 or 8 high sink outputs
■ Real time base, Beep and Clock-out capabilities
TQFP64
14 x 14
TQFP44
10 x 10
■ Configurable watchdog reset
■ Two 16-bit timers with:
– 2 input captures (only one on timer A)
– 2 output compares (only one on timer A)
– External clock input on timer A
■ 8-bit data manipulation
■ 63 basic instructions
■ 17 main addressing modes
– PWM and Pulse generator modes
■ SPI synchronous serial interface
■ 8 x 8 unsigned multiply instruction
■ True bit manipulation
■ SCI asynchronous serial interface
■ 8-bit ADC with 8 input pins
(6 only on ST72334Jx,
not available on ST72124J2)
■ Full hardware/software development package
Device Summary
Features
ST72124J2 ST72314J2 ST72314J4 ST72314N2 ST72314N4 ST72334J2 ST72334J4 ST72334N2 ST72334N4
Program memory - bytes
RAM (stack) - bytes
EEPROM - bytes
8K
8K
16K
8K
16K
512 (256)
-
8K
384 (256)
256
16K
512 (256)
256
8K
384 (256)
256
16K
512 (256)
256
384 (256)
-
384 (256) 512 (256)
384 (256)
-
-
-
Watchdog,
16-bit Tim-
ers, SPI,
SCI
Peripherals
Watchdog, 16-bit Timers, SPI, SCI, ADC
Operating Supply
CPU Frequency
Operating Temperature
Packages
3.0V to 5.5V
500 kHz to 8 MHz (with 1 to 16 MHz oscillator)
-40°C to +85°C (-40°C to +105/125°C optional)
TQFP44 / SDIP42
TQFP64 / SDIP56
TQFP44 / SDIP42
TQFP64 / SDIP56
Rev. 1.0
1/125
September 1999
This is preliminary information on a new product in development or undergoing evaluation. Details are subject to change without notice.
1
Table of Contents
1 PREAMBLE: ST72C334 VERSUS ST72E331 SPECIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.4.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.4.3 Structural organisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.4.4 In-Situ Programming (ISP) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.5 PROGRAM MEMORY READ-OUT PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.6 DATA EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.6.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.6.3 Memory Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.6.4 Data EEPROM and Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.6.5 Data EEPROM Access Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.6.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.1 LOW VOLTAGE DETECTOR (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.2 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.3 CLOCK SECURITY SYSTEM (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.3.1 Clock Filter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.3.2 Safe Oscillator Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.4 SUPPLY, RESET AND CLOCK REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . 33
4.5 MAIN CLOCK CONTROLLER (MCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5 INTERRUPTS & POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.1 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.2 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.2.2 HALT Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.2.3 WAIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.2.4 SLOW Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.1 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.1.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.1.3 I/O Port Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6.1.4 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
125
6.2 MISCELLANEOUS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.2.1 I/O Port Interrupt Sensitivity Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
2/125
2
Table of Contents
6.2.2 I/O Port Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.2.3 Miscellaneous Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.3 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6.3.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6.3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6.3.4 Hardware Watchdog Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6.3.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6.3.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6.3.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6.4 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.4.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.4.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.4.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.4.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.4.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
6.5 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
6.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
6.5.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
6.5.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
6.5.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6.5.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.5.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.5.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
6.6 SERIAL COMMUNICATIONS INTERFACE (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
6.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
6.6.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
6.6.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
6.6.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
6.6.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
6.6.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
6.6.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
6.7 8-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
6.7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
6.7.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
6.7.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
6.7.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
6.7.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
6.7.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
7 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
7.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
7.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
7.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
7.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
7.1.4 Indexed (No Offset, Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
7.1.5 Indirect (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
7.1.6 Indirect Indexed (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
3/125
3
Table of Contents
7.1.7 Relative mode (Direct, Indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
7.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
8 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
8.1 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
8.2 RECOMMENDED OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
8.3 DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
8.4 GENERAL TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
8.5 I/O PORT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
8.6 SUPPLY, RESET AND CLOCK CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . 109
8.6.1 Supply Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
8.6.2 Reset Sequence Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
8.6.3 Multi-Oscillator, Clock Security System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
8.7 MEMORY AND PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
9 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
9.1 PACKAGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
9.1.1 Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
9.1.2 User-supplied TQFP64 Adaptor / Socket . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
9.1.3 User-supplied TQFP44 Adaptor / Socket . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
9.2 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . 121
9.2.1 Option Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
9.2.2 Transfer Of Customer Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
10 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
125
4/125
Table of Contents
1 PREAMBLE: ST72C334 VERSUS ST72E331 SPECIFICATION
New Features available on the ST72C334
■ 8 or 16K FLASH/ROM with In-Situ Programming and Read-out protection
■ New ADC with a better accuracy and conversion time
■ New configurable Clock, Reset and Supply system
■ New power saving mode with real time base: Active Halt
■ Beep capability on PF1
■ New interrupt source: Clock security system (CSS) or Main clock controller (MCC)
ST72C334 I/O Confuguration and Pinout
■ Same pinout as ST72E331
■ PA6 and PA7 are true open drain I/O ports without pull-up (same as ST72E331)
■ PA3, PB3, PB4 and PF2 have no pull-up configuration (all IOs present on TQFP44)
■ PA5:4, PC3:2, PE7:4 and PF7:6 have high sink capabilities (20mA on N-buffer, 2mA on P-buffer and
pull-up). On the ST72E331, all these pads (except PA5:4) were 2mA push-pull pad without high sink
capabilities. PA4 and PA5 were 20mA true open drain.
New Memory Locations in ST72C334
■ 20h: MISCR register becomes MISCR1 register (naming change)
■ 29h: new control/status register for the MCC module
■ 2Bh: new control/status register for the Clock, Reset and Supply control. This register replaces the
WDGSR register keeping the WDOGF flag compatibility.
■ 40h: new MISCR2 register
5/125
4
ST72334J/N, ST72314J/N, ST72124J
2 GENERAL DESCRIPTION
2.1 INTRODUCTION
The ST72334J/N, ST72314J/N and ST72124J de-
vices are members of the ST7 microcontroller fam-
ily. They can be grouped as follows:
The
ST72C334J/N,
ST72C314J/N
and
ST72C124J versions feature single-voltage
FLASH memory with byte-by-byte In-Situ Pro-
gramming (ISP) capability.
– ST72334J/Ndevices are designed for mid-range
applications with Data EEPROM, ADC, SPI and
SCI interface capabilities.
Under software control, all devices can be placed
in WAIT, SLOW, ACTIVE-HALT or HALT mode,
reducing power consumption when the application
is in idle or standby state.
– ST72314J/N devices target the same range of
applications but without Data EEPROM.
The enhanced instruction set and addressing
modes of the ST7 offer both power and flexibility to
software developers, enabling the design of highly
efficient and compact application code. In addition
to standard 8-bit data management, all ST7 micro-
controllers feature true bit manipulation, 8x8 un-
signed multiplication and indirect addressing
modes.
– ST72124J devices are for applications that do
not need Data EEPROM and the ADC peripher-
al.
All devices are based on a common industry-
standard 8-bit core, featuring an enhanced instruc-
tion set.
Figure 1. Device Block Diagram
MULTI OSC
+
CLOCK FILTER
Internal
CLOCK
OSC1
OSC2
PA7:0
(8 bits for N versions)
(5 bits for J versions)
PORT A
V
SS
POWER
SUPPLY
PORT B
PB7:0
(8 bits for N versions)
(5 bits for J versions)
V
DD
TIMER B
PORT C
SPI
PORT D
PD7:0
(8 bits for N versions)
(6 bits for J versions)
PC7:0
(8 bits)
8-BIT ADC
V
SSA
V
DDA
PORT F
PF7,6,4,2:0
(6 bits)
RESET
/TEST
CONTROL
AND LVD
TIMER A
V
PP
8-BIT CORE
ALU
PORT E
SCI
PE7:0
(6 bits for N versions)
(2 bits for J versions)
PROGRAM
MEMORY
(8 or 16K Bytes)
WATCHDOG
Data-EEPROM
(256 Bytes)
RAM
(384 or 512 Bytes)
6/125
5
ST72334J/N, ST72314J/N, ST72124J
2.2 PIN DESCRIPTION
Figure 2. 64-Pin TQFP Package Pinout (N versions)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
V
V
(HS) PE4
1
(HS) PE5
2
(HS) PE6
3
(HS) PE7
4
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SS_1
DD_1
PA3
PA2
EI0
PA1
PB0
5
PB1
6
PB2
7
PA0
EI2
PC7 / SS
PC6 / SCK / ISPCLK
PC5 / MOSI
PC4 / MISO / ISPDATA
PC3 (HS) / ICAP1_B
PC2 (HS) / ICAP2_B
PC1 / OCMP1_B
PC0 / OCMP2_B
PB3
PB4
8
9
PB5
10
11
12
13
14
15
16
EI3
PB6
PB7
AIN0 / PD0
AIN1 / PD1
AIN2 / PD2
AIN3 / PD3
EI1
V
SS_0
V
DD_0
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
7/125
6
ST72334J/N, ST72314J/N, ST72124J
PIN DESCRIPTION (Cont’d)
Figure 3. 56-Pin SDIP Package Pinout (N versions)
1
PB4
PB5
PB3
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
2
PB2
EI3
EI2
PB6
3
PB1
PB7
4
PB0
PE7 (HS)
AIN0 / PD0
AIN1 / PD1
AIN2 / PD2
AIN3 / PD3
AIN4 / PD4
AIN5 / PD5
AIN6 / PD6
AIN7 / PD7
5
6
PE6 (HS)
PE5 (HS)
PE4 (HS)
PE1 / RDI
PE0 / TDO
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
V
_2
DD
OSC1
OSC2
V
DDA
V
V
_2
SSA
SS
MCO / PF0
BEEP / PF1
RESET
ISPSEL
EI1
PF2
PA7 (HS)
PA6 (HS)I
PA5 (HS)
PA4 (HS)
OCMP1_A / PF4
ICAP1_A / (HS) PF6
EXTCLK_A / (HS) PF7
V
V
V
DD_0
SS_1
V
SS_0
DD_1
OCMP2_B / PC0
OCMP1_B / PC1
PA3
PA2
EI0
ICAP2_B / (HS) PC2
ICAP1_B / (HS) PC3
ISPDATA/ MISO / PC4
MOSI / PC5
PA1
PA0
PC7 / SS
PC6 / SCK / ISPCLK
8/125
ST72334J/N, ST72314J/N, ST72124J
PIN DESCRIPTION (Cont’d)
Figure 4. 44-Pin TQFP and 42-Pin SDIP Package Pinouts (J versions)
44 43 42 41 40 39 38 37 36 35 34
PE1 / RDI
PB0
V
V
1
33
SS_1
DD_1
2
32
PB1
PA3
3
EI0 31
30
EI2
EI3
PB2
PC7 / SS
4
PB3
PC6 / SCK / ISPCLK
PC5 / MOSI
5
29
PB4
6
28
AIN0 / PD0
AIN1 / PD1
AIN2 / PD2
AIN3 / PD3
AIN4 / PD4
PC4 / MISO / ISPDATA
PC3 (HS) / ICAP1_B
PC2 (HS) / ICAP2_B
PC1 / OCMP1_B
PC0 / OCMP2_B
7
27
8
26
9
25
EI1
10
24
11
23
12 13 14 15 16 17 18 19 20 21 22
1
PB4
EI3
PB3
PB2
PB1
PB0
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
AIN0 / PD0
AIN1 / PD1
AIN2 / PD2
AIN3 / PD3
AIN4 / PD4
AIN5 / PD5
2
EI2
3
4
PE1 / RDI
5
6
PE0 / TDO
V
_2
7
DD
V
8
OSC1
OSC2
DDA
V
9
SSA
MCO / PF0
BEEP / PF1
V
_2
SS
10
11
12
13
14
15
16
17
18
19
20
21
RESET
EI1
PF2
ISPSEL
OCMP1_A / PF4
ICAP1_A / (HS) PF6
EXTCLK_A / (HS) PF7
OCMP2_B / PC0
PA7 (HS)
PA6 (HS)
PA5 (HS)
PA4 (HS)
OCMP1_B / PC1
ICAP2_B/ (HS) PC2
ICAP1_B / (HS) PC3
ISPDATA / MISO / PC4
MOSI / PC5
V
SS_1
V
DD_1
PA3
EI0 24
23
PC7 / SS
PC6 / SCK / ISPCLK
22
9/125
ST72334J/N, ST72314J/N, ST72124J
PIN DESCRIPTION (Cont’d)
Legend / Abbreviations:
Type:
I = input, O = output, S = supply
A = Dedicated analog input
Input level:
In/Output level: C = CMOS 0.3V /0.7V
,
DD
DD
C = CMOS 0.3V /0.7V with input trigger
T
DD
DD
Output level:
HS = high sink (on N-buffer only),
Port configuration capabilities:
– Input:
float = floating, wpu = weak pull-up, int = interrupt, ana = analog
OD = open drain, T = true open drain, PP = push-pull
– Output:
Note: the Reset configuration of each pin is shown in bold.
Table 1. Device Pin Description
Pin n°
Level
Port
Main
function
(after
Input
Output
Pin Name
Alternate function
reset)
1 49
PE4 (HS)
I/O C HS
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Port E4
Port E5
Port E6
Port E7
Port B0
Port B1
Port B2
Port B3
Port B4
Port B5
Port B6
Port B7
T
2 50
3 51
4 52
PE5 (HS)
PE6 (HS)
PE7 (HS)
I/O C HS
X
T
I/O C HS
X
T
I/O C HS
X
T
5 53 2 39 PB0
6 54 3 40 PB1
7 55 4 41 PB2
8 56 5 42 PB3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
S
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
EI2
EI2
EI2
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
EI2
EI3
EI3
9
1
6
1
PB4
10 2
11 3
12 4
13 5
14 6
15 7
PB5
PB6
EI3
EI3
PB7
7
8
9
2
3
4
PD0/AIN0
PD1/AIN1
PD2/AIN2
X
X
X
X
X
X
X
X
X
Port D0 ADC Analog Input 0
Port D1 ADC Analog Input 1
Port D2 ADC Analog Input 2
Port D3 ADC Analog Input 3
Port D4 ADC Analog Input 4
Port D5 ADC Analog Input 5
Port D6 ADC Analog Input 6
Port D7 ADC Analog Input 7
Analog Power Supply Voltage
Analog Ground Voltage
X
X
X
X
X
X
X
16 8 10 5 PD3/AIN3
17 9 11 6 PD4/AIN4
18 10 12 7 PD5/AIN5
19 11
PD6/AIN6
PD7/AIN7
20 12
21 13 13 8
22 14 14 9
23
V
V
V
V
DDA
SSA
S
S
Digital Main Supply Voltage
Digital Ground Voltage
DD_3
SS_3
24
S
25 15 15 10 PF0/MCO
26 16 16 11 PF1/BEEP
27 17 17 12 PF2
I/O
I/O
I/O
C
C
C
X
X
X
EI1
EI1
EI1
X
X
X
X
X
X
Port F0 Main clock output (f
Port F1 Beep signal output
Port F2
/2)
OSC
T
T
T
28
NC
Not Connected
10/125
ST72334J/N, ST72314J/N, ST72124J
Pin n°
Level
Port
Main
function
(after
Input
Output
Pin Name
Alternate function
reset)
29 18 18 13 PF4/OCMP1_A
30 NC
31 19 19 14 PF6 (HS)/ICAP1_A
I/O
I/O
C
X
X
X
X
Port F4 Timer A Output Compare 1
T
Not Connected
C
C
HS
X
X
X
X
X
X
X
Port F6 Timer A Input Capture 1
T
32 20 20 15 PF7 (HS)/EXTCLK_A I/O
HS
X
Port F7 Timer A External Clock Source
Digital Main Supply Voltage
Digital Ground Voltage
Port C0 Timer B Output Compare 2
Port C1 Timer B Output Compare 1
Port C2 Timer B Input Capture 2
Port C3 Timer B Input Capture 1
Port C4 SPI Master In / Slave Out Data
Port C5 SPI Master Out / Slave In Data
Port C6 SPI Serial Clock
Port C7 SPI Slave Select (active low)
Port A0
T
33 21 21
34 22 22
V
V
S
S
DD_0
SS_0
35 23 23 16 PC0/OCMP2_B
36 24 24 17 PC1/OCMP1_B
I/O
I/O
C
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
T
C
X
T
37 25 25 18 PC2 (HS)/ICAP2_B I/O
38 26 26 19 PC3 (HS)/ICAP1_B I/O
C
C
HS
X
T
HS
X
T
39 27 27 20 PC4/MISO
40 28 28 21 PC5/MOSI
41 29 29 22 PC6/SCK
42 30 30 23 PC7/SS
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
S
C
X
T
C
C
C
C
C
C
C
X
T
T
T
T
T
T
T
X
X
43 31
44 32
45 33
PA0
PA1
PA2
EI0
EI0
EI0
Port A1
Port A2
46 34 31 24 PA3
EI0
Port A3
47 35 32 25 V
48 36 33 26 V
Digital Main Supply Voltage
Digital Ground Voltage
Port A4
DD_1
SS_1
S
49 37 34 27 PA4 (HS)
50 38 35 28 PA5 (HS)
51 39 36 29 PA6 (HS)
52 40 37 30 PA7 (HS)
I/O
I/O
I/O
I/O
C
C
C
C
HS
X
X
X
X
X
X
X
X
T
T
X
X
T
HS
HS
HS
Port A5
T
T
T
Port A6
Port A7
Must be tied low in user mode. In pro-
gramming mode when available, this pin
acts as In-Situ Programming mode se-
lection.
53 41 38 31 ISPSEL
I
Top priority non maskable interrupt (ac-
tive low)
54 42 39 32 RESET
I/O
C
X
X
55
56
NC
NC
Not Connected
Digital Ground Voltage
57 43 40 33 V
S
SS_3
58 44 41 34 OSC2
59 45 42 35 OSC1
These pins connect a parallel-resonant
crystal or an external clock source to the
on-chip main oscillator.
60 46 43 36 V
S
Digital Main Supply Voltage
Port E0 SCI Transmit Data Out
Port E1 SCI Receive Data In
DD_3
61 47 44 37 PE0/TDO
62 48 1 38 PE1/RDI
I/O
I/O
C
X
X
X
X
X
X
X
X
T
C
T
63
64
NC
NC
Not Connected
11/125
ST72334J/N, ST72314J/N, ST72124J
2.3 REGISTER & MEMORY MAP
As shown in the Figure 5, the MCU is capable of
addressing 64K bytes of memories and I/O regis-
ters.
8 Kbytes of user program memory. The RAM
space includes up to 256 bytes for the stack from
0100h to 01FFh.
The available memory locations consist of 128
bytes of register locations, 384 or 512 bytes of
RAM, up to 256 bytes of data EEPROM and 4 or
The highest address bytes contain the user reset
and interrupt vectors.
Figure 5. Memory Map
0000h
0080h
HW Registers
Short Addressing
(see Table 2)
RAM (zero page)
00FFh
007Fh
0080h
0100h
256 Bytes Stack or
384 Bytes RAM
01FFh
16-bit Addressing RAM
01FFh
512 Bytes RAM
027Fh
0200h / 0280h
Reserved
0080h
Short Addressing
RAM (zero page)
0BFFh
00FFh
0100h
0C00h
256 Bytes Data EEPROM
0CFFh
0D00h
256 Bytes Stack or
Reserved
BFFFh
16-bit Addressing RAM
C000h
01FFh
0200h
16K Bytes
E000h
16-bit Addressing
RAM
8K Bytes
Program
Memory
Program
Memory
027Fh
FFDFh
FFE0h
Interrupt & Reset Vectors
(see Table 6 page 37)
FFFFh
12/125
ST72334J/N, ST72314J/N, ST72124J
REGISTER & MEMORY MAP (Cont’d)
Table 2. Hardware Register Map
Register
Label
Reset
Status
Address
Block
Register Name
Remarks
0000h
0001h
0002h
PADR
PADDR
PAOR
Port A Data Register
Port A Data Direction Register
Port A Option Register
00h
00h
00h
R/W
R/W
R/W
Port A
1)
0003h
Reserved Area (1 Byte)
0004h
0005h
0006h
PCDR
PCDDR
PCOR
Port C Data Register
Port C Data Direction Register
Port C Option Register
00h
00h
00h
R/W
R/W
R/W
Port C
Port B
Port E
Port D
Port F
0007h
Reserved Area (1 Byte)
R/W
R/W
0008h
0009h
000Ah
PBDR
PBDDR
PBOR
Port B Data Register
Port B Data Direction Register
Port B Option Register
00h
00h
00h
1)
1)
1)
R/W
000Bh
Reserved Area (1 Byte)
000Ch
000Dh
000Eh
PEDR
PEDDR
PEOR
Port E Data Register
Port E Data Direction Register
Port E Option Register
00h
00h
00h
R/W
R/W
R/W
000Fh
Reserved Area (1 Byte)
0010h
0011h
0012h
PDDR
PDDDR
PDOR
Port D Data Register
Port D Data Direction Register
Port D Option Register
00h
00h
00h
R/W
R/W
R/W
0013h
Reserved Area (1 Byte)
0014h
0015h
0016h
PFDR
PFDDR
PFOR
Port F Data Register
Port F Data Direction Register
Port F Option Register
00h
00h
00h
R/W
R/W
R/W
0017h
to
001Fh
Reserved Area (9 Bytes)
Miscellaneous Register 1
0020h
MISCR1
00h
R/W
0021h
0022h
0023h
SPIDR
SPICR
SPISR
SPI Data I/O Register
SPI Control Register
SPI Status Register
xxh
0xh
00h
R/W
R/W
Read Only
SPI
0024h
to
Reserved Area (5 Bytes)
0028h
0029h
MCC
MCCSR
Main Clock Control / Status Register
01h
R/W
13/125
ST72334J/N, ST72314J/N, ST72124J
Register
Label
Reset
Status
Address
Block
Register Name
Remarks
002Ah
002Bh
002Ch
WATCHDOG WDGCR
CRSR
Watchdog Control Register
7Fh
00h
00h
R/W
Clock, Reset, Supply Control / Status Register
Data-EEPROM Control/Status Register
R/W
R/W
Data-EEPROM EECSR
002Dh
0030h
Reserved Area (4 Bytes)
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
TACR2
TACR1
TASR
TAIC1HR
TAIC1LR
TAOC1HR
TAOC1LR
TACHR
TACLR
TAACHR
TAACLR
TAIC2HR
TAIC2LR
TAOC2HR
TAOC2LR
Timer A Control Register 2
Timer A Control Register 1
Timer A Status Register
Timer A Input Capture 1 High Register
Timer A Input Capture 1 Low Register
Timer A Output Compare 1 High Register
Timer A Output Compare 1 Low Register
Timer A Counter High Register
00h
00h
xxh
xxh
xxh
80h
00h
FFh
FCh
FFh
FCh
xxh
xxh
80h
00h
R/W
R/W
Read Only
Read Only
Read Only
R/W
R/W
TIMER A
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Timer A Counter Low Register
Timer A Alternate Counter High Register
Timer A Alternate Counter Low Register
Timer A Input Capture 2 High Register
Timer A Input Capture 2 Low Register
Timer A Output Compare 2 High Register
Timer A Output Compare 2 Low Register
2)
2)
2)
R/W
R/W
2)
0040h
MISCR2
Miscellaneous Register 2
00h
R/W
0041h
0042h
0043h
0044h
0045h
0046h
0047h
0048h
0049h
004Ah
004Bh
004Ch
004Dh
004Eh
004Fh
TBCR2
TBCR1
TBSR
TBIC1HR
TBIC1LR
TBOC1HR
TBOC1LR
TBCHR
Timer B Control Register 2
Timer B Control Register 1
Timer B Status Register
Timer B Input Capture 1 High Register
Timer B Input Capture 1 Low Register
Timer B Output Compare 1 High Register
Timer B Output Compare 1 Low Register
Timer B Counter High Register
00h
00h
xxh
xxh
xxh
80h
00h
FFh
FCh
FFh
FCh
xxh
xxh
80h
00h
R/W
R/W
Read Only
Read Only
Read Only
R/W
R/W
TIMER B
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
R/W
TBCLR
Timer B Counter Low Register
TBACHR
TBACLR
TBIC2HR
TBIC2LR
TBOC2HR
TBOC2LR
Timer B Alternate Counter High Register
Timer B Alternate Counter Low Register
Timer B Input Capture 2 High Register
Timer B Input Capture 2 Low Register
Timer B Output Compare 2 High Register
Timer B Output Compare 2 Low Register
R/W
0050h
0051h
0052h
0053h
0054h
0055h
0056h
0057h
SCISR
SCIDR
SCIBRR
SCICR1
SCICR2
SCIERPR
SCI Status Register
SCI Data Register
SCI Baud Rate Register
SCI Control Register 1
SCI Control Register 2
SCI Extended Receive Prescaler Register
Reserved area
SCI Extended Transmit Prescaler Register
C0h
xxh
Read Only
R/W
00xx xxxx R/W
xxh
00h
00h
---
R/W
R/W
R/W
SCI
SCIETPR
00h
R/W
14/125
ST72334J/N, ST72314J/N, ST72124J
Register
Label
Reset
Status
Address
Block
Register Name
Remarks
0058h
006Fh
Reserved Area (24 Bytes)
0070h
0071h
ADCDR
ADCCSR
Data Register
Control/Status Register
xxh
00h
Read Only
R/W
ADC
0072h
to
Reserved Area (14 Bytes)
007Fh
Notes:
1) The bits corresponding to unavailable pins are forced to 1 by hardware, this affects the reset status value.
2) External pin not available.
3) Not used in versions without Low Voltage Detector Reset.
15/125
ST72334J/N, ST72314J/N, ST72124J
2.4 FLASH PROGRAM MEMORY
2.4.1 Introduction
This mode needs five signals (plus the V signal
if necessary) to be connected to the programming
tool. This signals are:
DD
Flash devices have a single voltage non-volatile
FLASH memory that may be programmed in-situ
(or plugged in a programming tool) on a byte-by-
byte basis.
– RESET: device reset
– V : device ground power supply
SS
– ISPCLK: ISP output serial clock pin
– ISPDATA: ISP input serial data pin
2.4.2 Main features
■ Remote In-Situ Programming (ISP) mode
■ Up to 16 bytes programmed in the same cycle
■ MTP memory (Multiple Time Programmable)
■ Read-out memory protection against piracy
2.4.3 Structural organisation
– ISPSEL: Remote ISP mode selection. This pin
must be connected to V on the application
SS
board
If any of these pins are used for other purposes on
the application, a serial resistor has to be imple-
mented to avoid a conflict if the other device forces
the signal level.
The FLASH program memory is organised in a
single 8-bit wide memory block which can be used
for storing both code and data constants.
Figure 6 shows a typical hardware interface to a
standard ST7 programming tool. For more details
on the pin locations, refer to the device pinout de-
scription.
The FLASH program memory is mapped in the up-
per part of the ST7 addressing space (F000h-
FFFFh) and includes the reset and interrupt user
vector area .
Figure 6. Typical Remote ISP Interface
HE10 CONNECTOR TYPE
2.4.4 In-Situ Programming (ISP) mode
TO PROGRAMMING TOOL
XTAL
The FLASH program memory can be programmed
using Remote ISP mode. This ISP mode allows
the contents of the ST7 program memory to be up-
dated using a standard ST7 programming tools af-
ter the device is mounted on the application board.
This feature can be implemented with a minimum
number of added components and board area im-
pact.
1
C
C
L1
L0
ISPSEL
10kΩ
An exampleRemote ISP hardware interface to the
standard ST7 programming tool is described be-
low. For more details on ISP programming, refer to
the ST7 Programming Specification.
V
SS
RESET
ISPCLK
Remote ISP Overview
ST7
ISPDATA
The Remote ISP mode is initiated by a specific se-
quence on the dedicated ISPSEL pin.
4.7kΩ
The Remote ISP is performed in three steps:
– Selection of the RAM execution mode
– Download of Remote ISP code in RAM
APPLICATION
– Execution of Remote ISP code in RAM to pro-
gram the user program into the FLASH
2.5 Program Memory Read-out Protection
The read-out protection is enabled through an op-
tion bit.
Remote ISP hardware configuration
In Remote ISP mode, the ST7 has to be supplied
For FLASH devices, when this option is selected,
the program and data stored in the FLASH memo-
ry are protected against read-out piracy (including
a re-write protection). When this protection option
is removed the entire FLASH program memory is
first automatically erased.
with power (V and V ) and a clock signal (os-
DD
SS
cillator and application crystal circuit for example).
1
16/125
ST72334J/N, ST72314J/N, ST72124J
2.6 DATA EEPROM
2.6.1 Introduction
2.6.2 Main Features
■ Up to 16 Bytes programmed in the same cycle
■ EEPROM mono-voltage (charge pump)
■ Chained erase and programming cycles
The Electrically Erasable Programmable Read
Only Memory can be used as a non volatile back-
up for storing data. Using the EEPROM requires a
basic access protocol described in this chapter.
■ Internal control of the global programming cycle
duration
■ End of programming cycle interrupt flag
■ WAIT mode management
Figure 7. EEPROM Block Diagram
FALLING
EDGE
DETECTOR
EEPROM INTERRUPT
HIGH VOLTAGE
PUMP
RESERVED
EEPROM
EECSR
0
0
0
0
0
IE LAT PGM
EEPROM
ADDRESS
DECODER
ROW
4
MEMORY MATRIX
(1 ROW = 16 x 8 BITS)
DECODER
128
128
DATA
MULTIPLEXER
16 x 8 BITS
4
4
DATA LATCHES
ADDRESS BUS
DATA BUS
17/125
ST72334J/N, ST72314J/N, ST72124J
DATA EEPROM (Cont’d)
2.6.3 Memory Access
When PGM bit is set by the software, all the previ-
ous bytes written in the data latches (up to 16) are
programmed in the EEPROM cells. The effective
high address (row) is determined by the last EEP-
ROM write sequence. To avoid wrong program-
ming, the user must take care that all the bytes
written between two programming sequences
have the same high address: only the four Least
Significant Bits of the address can change.
The Data EEPROM memory read/write access
modes are controlled by the LAT bit of the EEP-
ROM Control/Status register (EECSR). The flow-
chart in Figure 8 describes these different memory
access modes.
Read Operation (LAT=0)
The EEPROM can be read as a normal ROM loca-
tion when the LAT bit of the EECSR register is
cleared. In a read cycle, the byte to be accessed is
put on the data bus in less than 1 CPU clock cycle.
This means that reading data from EEPROM
takes the same time as reading data from
EPROM, but this memory cannot be used to exe-
cute machine code.
At the end of the programming cycle, the PGM and
LAT bits are cleared simultaneously, and an inter-
rupt is generated if the IE bit is set. The Data EEP-
ROM interrupt request is cleared by hardware
when the Data EEPROM interrupt vector is
fetched.
Note: Care should be taken during the program-
ming cycle. Writing to the same memory location
will over-program the memory (logical AND be-
tween the two write access data result) because
the data latches are only cleared at the end of the
programming cycle and by the falling edge of LAT
bit.
Write Operation (LAT=1)
To access the write mode, the LAT bit has to be
set by software (the PGM bit remains cleared).
When a write access to the EEPROM area occurs,
the value is latched inside the 16 data latches ac-
cording to its address.
It is not possible to read the latched data.
This note is ilustrated by the Figure 9.
Figure 8. Data EEPROM Programming Flowchart
READ MODE
LAT=0
WRITE MODE
LAT=1
PGM=0
PGM=0
WRITE UP TO 16 BYTES
IN EEPROM AREA
(with the same 12 MSB of the address)
READ BYTES
IN EEPROM AREA
START PROGRAMMING CYCLE
LAT=1
PGM=1 (set by software)
INTERRUPT GENERATION
IF IE=1
0
1
LAT
CLEARED BY HARDWARE
18/125
ST72334J/N, ST72314J/N, ST72124J
2.6.5 Data EEPROM Access Error Handling
DATA EEPROM (Cont’d)
2.6.4 Data EEPROM and Power Saving Modes
Wait mode
If a read access occurs while LAT=1, then the data
bus will not be driven.
The DATA EEPROM can enter WAIT mode on ex-
ecution of the WFI instruction of the microcontrol-
ler. The DATA EEPROM will immediately enter
this mode if there is no programming in progress,
otherwise the DATA EEPROM will finish the cycle
and then enter WAIT mode.
If a write access occurs while LAT=0, then the
data on the bus will not be latched.
If a programming cycle is interrupted (by software/
RESET action), the memory data will not be guar-
anteed.
Halt mode
The DATA EEPROM immediatly enters HALT
mode if the microcontroller executes the HALT in-
struction. Therefore the EEPROM will stop the
function in progress, and data may be corrupted.
Figure 9. Data EEPROM Programming Cycle
READ OPERATION NOT POSSIBLE
READ OPERATION POSSIBLE
INTERNAL
PROGRAMMING
VOLTAGE
ERASE CYCLE
WRITE CYCLE
WRITE OF
DATA LATCHES
tPROG
LAT
PGM
EEPROM INTERRUPT
19/125
ST72334J/N, ST72314J/N, ST72124J
DATA EEPROM (Cont’d)
2.6.6 Register Description
CONTROL/STATUS REGISTER (CSR)
Read/Write
Reset Value: 0000 0000 (00h)
7
0
0
0
0
0
0
IE
LAT
PGM
Bit 7:3 = Reserved, forced by hardware to 0.
Bit 2 = IE Interrupt enable
This bitisset andclearedby software. Itenables the
Data EEPROM interrupt capability when the PGM
bit is cleared by hardware. The interrupt request is
automatically cleared when the software enters the
interrupt routine.
0: Interrupt disabled
1: Interrupt enabled
Bit 1 = LAT Latch Access Transfer
This bit is set by software. It is cleared by hard-
ware at the end of the programming cycle. It can
only be cleared by software if PGM bit is cleared.
0: Read mode
1: Write mode
Bit 0 = PGM Programming control and status
This bit is set by software to begin the programming
cycle. At the end of the programming cycle, this bit
is clearedby hardware and aninterrupt isgenerated
if the ITE bit is set.
0: Programming finished or not yet started
1: Programming cycle is in progress
Note: if the PGM bit is cleared during the program-
ming cycle, the memory data is not guaranteed.
Table 3. DATA EEPROM Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
EECSR
IE
0
RWM
0
PGM
0
002Ch
0
0
0
0
0
Reset Value
20/125
ST72334J/N, ST72314J/N, ST72124J
3 CENTRAL PROCESSING UNIT
3.1 INTRODUCTION
Accumulator (A)
The Accumulator is an 8-bit general purpose reg-
ister used to hold operands and the results of the
arithmetic and logic calculations and to manipulate
data.
This CPU has a full 8-bit architecture and contains
six internal registers allowing efficient 8-bit data
manipulation.
Index Registers (X and Y)
3.2 MAIN FEATURES
In indexed addressing modes, these 8-bit registers
are used to create either effective addresses or
temporary storage areas for data manipulation.
(The Cross-Assembler generates a precede in-
struction (PRE) to indicate that the following in-
struction refers to the Y register.)
■ 63 basic instructions
■ Fast 8-bit by 8-bit multiply
■ 17 main addressing modes
■ Two 8-bit index registers
■ 16-bit stack pointer
The Y register is not affected by the interrupt auto-
matic procedures (not pushed to and popped from
the stack).
■ Low power modes
■ Maskable hardware interrupts
■ Non-maskable software interrupt
Program Counter (PC)
The program counter is a 16-bit register containing
the address of the next instruction to be executed
by the CPU. It is made of two 8-bit registers PCL
(Program Counter Low which is the LSB) and PCH
(Program Counter High which is the MSB).
3.3 CPU REGISTERS
The 6 CPU registers shown in Figure 10 are not
present in the memory mapping and are accessed
by specific instructions.
Figure 10. CPU Registers
7
0
ACCUMULATOR
RESET VALUE = XXh
7
0
0
X INDEX REGISTER
Y INDEX REGISTER
RESET VALUE = XXh
7
RESET VALUE = XXh
PCL
PCH
7
8
15
0
PROGRAM COUNTER
RESET VALUE = RESET VECTOR @ FFFEh-FFFFh
7
1
0
1
1
1
1
H I N Z
C
X
CONDITION CODE REGISTER
RESET VALUE =
8
1
X 1 X X
15
7
0
STACK POINTER
RESET VALUE = STACK HIGHER ADDRESS
X = Undefined Value
21/125
ST72334J/N, ST72314J/N, ST72124J
CENTRAL PROCESSING UNIT (Cont’d)
CONDITION CODE REGISTER (CC)
Read/Write
Bit 2 = N Negative.
This bit is set and cleared by hardware. It is repre-
sentative of the result sign of the last arithmetic,
logical or data manipulation. It is a copy of the 7
Reset Value: 111x1xxx
th
7
0
bit of the result.
0: The result of the last operation is positive or null.
1: The result of the last operation is negative
(i.e. the most significant bit is a logic 1).
1
1
1
H
I
N
Z
C
This bit is accessed by the JRMI and JRPL instruc-
tions.
The 8-bit Condition Code register contains the in-
terrupt mask and four flags representative of the
result of the instruction just executed. This register
can also be handled by the PUSH and POP in-
structions.
Bit 1 = Z Zero.
This bit is set and cleared by hardware. This bit in-
dicates that the result of the last arithmetic, logical
or data manipulation is zero.
These bits can be individually tested and/or con-
trolled by specific instructions.
0: The result of the last operation is different from
zero.
Bit 4 = H Half carry.
1: The result of the last operation is zero.
This bit is set by hardware when a carry occurs be-
tween bits 3 and 4 of the ALU during an ADD or
ADC instruction. It is reset by hardware during the
same instructions.
This bit is accessed by the JREQ and JRNE test
instructions.
0: No half carry has occurred.
1: A half carry has occurred.
Bit 0 = C Carry/borrow.
This bit is tested using the JRH or JRNH instruc-
tion. The H bit is useful in BCD arithmetic subrou-
tines.
This bit is set and cleared by hardware and soft-
ware. It indicates an overflow or an underflow has
occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.
Bit 3 = I Interrupt mask.
This bit is driven by the SCF and RCF instructions
and tested by the JRC and JRNC instructions. It is
also affected by the “bit test and branch”, shift and
rotate instructions.
This bit is set by hardware when entering in inter-
rupt or by software to disable all interrupts except
the TRAP software interrupt. This bit is cleared by
software.
0: Interrupts are enabled.
1: Interrupts are disabled.
This bit is controlled by the RIM, SIM and IRET in-
structions and is tested by the JRM and JRNM in-
structions.
Note: Interrupts requested while I is set are
latched and can be processed when I is cleared.
By default an interrupt routine is not interruptable
because the I bit is set by hardware when you en-
ter it and reset by the IRET instruction at the end of
the interrupt routine. If the I bit is cleared by soft-
ware in the interrupt routine, pending interrupts are
serviced regardless of the priority level of the cur-
rent interrupt routine.
22/125
ST72334J/N, ST72314J/N, ST72124J
CENTRAL PROCESSING UNIT (Cont’d)
Stack Pointer (SP)
The least significant byte of the Stack Pointer
(called S) can be directly accessed by a LD in-
struction.
Read/Write
Reset Value: 01 FFh
Note: When the lower limit is exceeded, the Stack
Pointer wraps around to the stack upper limit, with-
out indicating the stack overflow. The previously
stored information is then overwritten and there-
fore lost. The stack also wraps in case of an under-
flow.
15
8
1
0
7
0
0
0
0
0
0
0
The stack is used to save the return address dur-
ing a subroutine call and the CPU context during
an interrupt. The user may also directly manipulate
the stack by means of the PUSH and POP instruc-
tions. In the case of an interrupt, the PCL is stored
at the first location pointed to by the SP. Then the
other registers are stored in the next locations as
shown in Figure 11.
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
The Stack Pointer is a 16-bit register which is al-
ways pointing to the next free location in the stack.
It is then decremented after data has been pushed
onto the stack and incremented before data is
popped from the stack (see Figure 11).
– When an interrupt is received, the SP is decre-
mented and the context is pushed on the stack.
Since the stack is 256 bytes deep, the 8th most
significant bits are forced by hardware. Following
an MCU Reset, or after a Reset Stack Pointer in-
struction (RSP), the Stack Pointer contains its re-
set value (the SP7 to SP0 bits are set) which is the
stack higher address.
– On return from interrupt, the SP is incremented
and the context is popped from the stack.
A subroutine call occupies two locations and an in-
terrupt five locations in the stack area.
Figure 11. Stack Manipulation Example
CALL
Subroutine
RET
or RSP
PUSH Y
POP Y
IRET
Interrupt
Event
@ 0100h
SP
SP
SP
Y
CC
A
CC
CC
A
A
X
X
X
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
SP
SP
PCH
PCH
PCL
SP
@ 01FFh PCL
Stack Higher Address = 01FFh
0100h
Stack Lower Address =
23/125
ST72334J/N, ST72314J/N, ST72124J
4 SUPPLY, RESET AND CLOCK MANAGEMENT
The ST72334J/N, ST72314J/N and ST72124J mi-
crocontrollers include a range of utility features for
securing the application in critical situations (for
example in case of a power brown-out), and re-
ducing the number of external components. An
overview is shown in Figure 12.
■ Reset Sequence Manager (RSM)
■ Multi-Oscillator (MO)
– 4 Crystal/Ceramic resonator oscillators
– 1 External RC oscillator
– 1 Internal RC oscillator
■ Clock Security System (CSS)
Main Features
– Clock Filter
– Backup Safe Oscillator
■ Supply Manager with Main supply Low voltage
detection (LVD)
Figure 12. Clock, Reset and Supply Block Diagram
MCO
CLOCK SECURITY SYSTEM
(CSS)
MAIN CLOCK
MULTI-
OSCILLATOR
(MO)
OSC2
OSC1
f
f
CPU
OSC
CLOCK
FILTER
SAFE
OSC
CONTROLLER
(MCC)
RESET SEQUENCE
MANAGER
FROM
RESET
WATCHDOG
PERIPHERAL
(RSM)
VDD
VSS
LOW VOLTAGE
DETECTOR
(LVD)
LVD
CSS
WDG
RF
CRSR
0
0
0
RF
0
IE
D
CSS INTERRUPT
24/125
ST72334J/N, ST72314J/N, ST72124J
4.1 LOW VOLTAGE DETECTOR (LVD)
To allow the integration of power management
features in the application, the Low Voltage Detec-
tor function (LVD) generates a static reset when
In these conditions, secure operation is always en-
sured for the application without the need for ex-
ternal reset hardware.
the V supply voltage is below a V
reference
DD
LVDf
During a Low Voltage Detector Reset, the RESET
pin is held low, thus permitting the MCU to reset
other devices.
value. This means that it secures the power-up as
well as the power-down keeping the ST7 in reset.
The V
lower than the V
in order to avoid a parasitic reset when the MCU
starts running and sinks current on the supply
(hysteresis).
reference value for a voltage drop is
Notes:
LVDf
1) the LVD allows the device to be used without any exter-
nal RESET circuitry.
reference value for power-on
LVDr
2) three different reference levels are selectable through
the OPTION BYTE according to the application require-
ment.
The LVD Reset circuitry generates a reset when
LVD application note
V
is below:
DD
Application software can detect a reset caused by
the LVD by reading the LVDRF bit in the CRSR
register.
– V
when V is rising
DD
when V is falling
DD
LVDr
– V
LVDf
The LVD function is illustrated in the Figure 13.
This bit is set by hardware when a LVD reset is
generated and cleared by software (writing zero).
Provided the minimum V value (guaranteed for
the oscillator frequency) is below V
can only be in two modes:
DD
, the MCU
LVDf
– under full software control
– in static safe reset
Figure 13. Low Voltage Detector vs Reset
V
DD
HYSTERESIS
V
LVDhyst
V
V
LVDr
LVDf
RESET
25/125
ST72334J/N, ST72314J/N, ST72124J
4.2 RESET SEQUENCE MANAGER (RSM)
The reset sequence manager includes three RE-
SET sources as shown in Figure 15:
■ EXTERNAL RESET SOURCE pulse
■ Internal LVD RESET (Low Voltage Detection)
■ Internal WATCHDOG RESET
The 4096 CPU clock cycle delay allows the oscil-
lator to stabilise and ensures that recovery has
taken place from the Reset state.
The RESET vector fetch phase duration is 2 clock
cycles.
These sources act on the RESET PIN and it is al-
ways kept low during the delay phase.
Figure 14. RESET Sequence Phases
The RESET service routine vector is fixed at ad-
dresses FFFEh-FFFFh in the ST7 memory map.
RESET
The basic RESET sequence consists of 3 phases
as shown in Figure 14:
INTERNAL RESET
FETCH
DELAY
4096 CLOCK CYCLES
VECTOR
■ Delay depending on the RESET source
■ 4096 CPU clock cycle delay
■ RESET vector fetch
Figure 15. Reset Block Diagram
INTERNAL
RESET
V
DD
f
CPU
R
ON
RESET
WATCHDOG RESET
LVD RESET
26/125
ST72334J/N, ST72314J/N, ST72124J
RESET SEQUENCE MANAGER (Cont’d)
External RESET pin
A RESET signal originating from an external
source must have a duration of at least t
in
PULSE
The RESET pin is both an input and an open-drain
output with integrated R
This pull-up has no fixed value but varies in ac-
cordance with the input voltage. It can be pulled
low by external circuitry to reset the device.
order to be recognized. Two RESET sequences
can be associated with this RESET source as
shown in Figure 16.
weak pull-up resistor.
ON
Starting from the external RESET pulse recogni-
tion, the device RESET pin acts as an output that
is pulled low during at least t
.
DELAYmin
Figure 16. External RESET Sequences
V
DD
V
DDnominal
V
LVDf
RESET
RUN
RUN
INTERNAL RESET
FETCH
DELAY
4096 CLOCK CYCLES VECTOR
tDELAYmin
tPULSE
EXTERNAL RESET SOURCE
RESET PIN
WATCHDOG RESET
V
DD
V
DDnominal
V
LVDf
RESET
RUN
RUN
INTERNAL RESET
FETCH
DELAY
4096 CLOCK CYCLES VECTOR
tPULSE
EXTERNAL RESET SOURCE
RESET PIN
WATCHDOG RESET
27/125
ST72334J/N, ST72314J/N, ST72124J
RESET SEQUENCE MANAGER (Cont’d)
Internal Low Voltage Detection RESET
■ Voltage Drop RESET
Two different RESET sequences caused by the in-
ternal LVD circuitry can be distinguished:
■ Power-On RESET
The device RESET pin acts as an output that is
pulled low when V <V
(rising edge) or
DD
LVDr
V
<V
(falling edge) as shown in Figure 9.
DD
LVDf
Figure 17. LVD RESET Sequences
V
DD
V
V
DDnominal
LVDr
RESET
RUN
INTERNAL RESET
FETCH
DELAY
4096 CLOCK CYCLES VECTOR
EXTERNAL RESET SOURCE
RESET PIN
WATCHDOG RESET
V
DD
V
V
V
DDnominal
LVDr
LVDf
RESET
RUN
RUN
INTERNAL RESET
FETCH
DELAY
4096 CLOCK CYCLES VECTOR
EXTERNAL RESET SOURCE
RESET PIN
WATCHDOG RESET
28/125
ST72334J/N, ST72314J/N, ST72124J
RESET SEQUENCE MANAGER (Cont’d)
Internal Watchdog RESET
Starting from the Watchdog counter underflow, the
device RESET pin acts as an output that is pulled
The RESET sequence generated by a internal
Watchdog counter overflow is shown in Figure 18.
low during at least t
.
DELAYmin
Figure 18. Watchdog RESET Sequence
V
DD
V
DDnominal
V
LVDf
RESET
RUN
RUN
INTERNAL RESET
FETCH
DELAY
4096 CLOCK CYCLES VECTOR
EXTERNAL RESET SOURCE
tDELAYmin
RESET PIN
WATCHDOG RESET
WATCHDOG UNDERFLOW
29/125
ST72334J/N, ST72314J/N, ST72124J
MULTI-OSCILLATOR (MO)
The main clock of the ST7 can be generated by 7
different sources coming from the multi-oscillator
block:
Crystal/Ceramic Oscillators
This family of oscillators has the advantage of pro-
ducing a high accuracy on the main clock of the
ST7. The selection within a list of 4 oscillators with
different frequency ranges has to be done by OP-
TION BYTE in order to reduce the consumption. In
this mode of the MO block, the resonator and the
load capacitances have to be connected as shown
in Figure 20 and have to be mounted as close as
possible to the oscillator pins in order to minimize
output distortion and start-up stabilization time.
The loading capacitance values must be adjusted
according to the selected oscillator.
■ an external source
■
4 crystal or ceramic resonator oscillators
■ 1 external RC oscillator
■ 1 internal high frequency RC oscillator
Each oscillator is optimized for a given frequency
range in terms of consumption and is selectable
through the OPTION BYTE.
External Clock Source
The default OPTION BYTE value selects the Ex-
ternal Clock in the MO block. In this mode, a clock
signal (square, sinus or triangle) with ~50% duty
cycle has to drive the OSC1 pin while the OSC2
pin is tied to ground (see Figure 19).
These oscillators, when selected via the OPTION
BYTE, are not stopped during the RESET phase
to avoid losing time in the oscillator start-up phase.
Figure 20. MO Crystal/Ceramic Resonator
Figure 19. MO External Clock
ST7
OSC1
OSC2
ST7
OSC1
OSC2
C
C
L1
L0
EXTERNAL
SOURCE
LOAD
CAPACITANCES
30/125
ST72334J/N, ST72314J/N, ST72124J
MULTI-OSCILLATOR (Cont’d)
External RC Oscillator
Internal RC Oscillator
This oscillator allows a low cost solution for the
main clock of the ST7 using only an external resis-
tor and an external capacitor (see Figure 21). The
selection of the external RC oscillator has to be
done by OPTION BYTE.
The Internal RC oscillator mode is based on the
same principle as the External RC oscillator in-
cluding the resistance and the capacitance of the
device. This mode is the most cost effective one
with the drawback of a lower frequency accuracy.
Its frequency is in the range of several MHz.
The frequency of the external RC oscillator (in the
range of some MHz.) is fixed by the resistor and
the capacitor values:
In this mode, the two oscillator pins have to be tied
to ground as shown in Figure 22.
1)
4
. C
The selection of the internal RC oscillator has to
be done by OPTION BYTE.
f
~
OSC
R
EX
EX
The previous formula shows that in this MO mode,
the accuracy of the clock is directly linked to the
accuracy of the discrete components.
Figure 21. MO External RC
Figure 22. MO Internal RC
ST7
OSC1
OSC2
ST7
OSC1
OSC2
R
C
EX
EX
Note:
1) This formula provides an approximation of the frequency with typical R and C values at V =5V.
EX
EX
DD
It is given only as design guidelines.
31/125
ST72334J/N, ST72314J/N, ST72124J
4.3 CLOCK SECURITY SYSTEM (CSS)
The Clock Security System (CSS) protects the
ST7 against main clock problems. To allow the in-
tegration of the security features in the applica-
tions, it is based on a clock filter control and an In-
ternal Safe Oscillator. The CSS can be disabled by
OPTION BYTE.
4.3.2 Safe Oscillator Control
The Safe Oscillator of the CSS block is a low fre-
quency back-up clock source (see Figure 24).
If the clock signal disappears (due to a broken or
disconnected resonator...) during a Safe Oscillator
period, the Safe oscillator delivers a low frequency
clock signal which allows the ST7 to perform some
rescue operations.
4.3.1 Clock Filter Control
The Clock Filter is based on a clock frequency lim-
itation function.
Automatically, the ST7 clock source switches back
from the Safe Oscillator if the original clock source
recovers.
This filter function is able to detect and filter high
frequency spikes on the ST7 main clock.
If the oscillator is not working properly (e.g. work-
ing at a harmonic frequency of the resonator), the
current active oscillator clock can be totally fil-
tered, and then no clock signal is available for the
ST7 from this oscillator anymore. If the original
clock source recovers, the filtering is stopped au-
tomatically and the oscillator supplies the ST7
clock.
Limitation detection
The automatic Safe Oscillator selection is notified
by hardware setting the CSSD bit of the CRSR
register. An interrupt can be generated if the CS-
SIE bit has been previously set.
These two bits are described in the CRSR register
description.
Figure 23. Clock Filter Function
MAIN
OSCILLATOR
CLOCK
INTERNAL
ST7
CLOCK
Figure 24. Safe Oscillator Function
MAIN
OSCILLATOR
CLOCK
SAFE
OSCILLATOR
CLOCK
INTERNAL
ST7
CLOCK
32/125
ST72334J/N, ST72314J/N, ST72124J
4.4 SUPPLY, RESET AND CLOCK REGISTER DESCRIPTION
CLOCK RESET AND SUPPLY REGISTER
(CRSR)
Bit 1 = CSSD Clock security system detection
This bit indicates that the safe oscillator of the
Clock Security System block has been selected by
hardware due to a disturbance on the main clock
Read/Write
Reset Value: 000x 000x (00h)
signal (f
). It is set by hardware and cleared by
OSC
a read of the CRSR register when the original os-
cillator recovers.
7
0
0: Safe oscillator is not active
LVD
RF
CSS CSS WDG
IE RF
0
0
0
0
1: Safe oscillator has been activated
When the CSS is disabled by OPTION BYTE, the
CSSD bit value is forced to 0.
D
Bit 7:5 = Reserved, always read as 0.
Bit 4 = LVDRF LVD reset flag
This bit indicates that the last Reset was generat-
ed by the LVD block. It is set by hardware (LVD re-
set) and cleared by software (writing zero). See
WDGRF flag description for more details. When
the LVD is disabled by OPTION BYTE, the LVDRF
bit value is undefined.
Bit 0 = WDGRF Watchdog reset flag
This bit indicates that the last Reset was generat-
ed by the Watchdog peripheral. It is set by hard-
ware (watchdog reset) and cleared by software
(writing zero) or a LVD Reset (to ensure a stable
cleared state of the WDGRF flag when CPU
starts).
Combined with the LVDRF flag information, the
flag description is given by the following table.
RESET Sources
LVDRF WDGRF
Bit 3 = Reserved, always read as 0.
External RESET pin
Watchdog
0
0
1
0
1
Bit 2 = CSSIE Clock security syst interrupt enable
.
This bit enables the interrupt when a disturbance
is detected by the Clock Security System (CSSD
bit set). It is set and cleared by software.
0: Clock security system interrupt disabled
1: Clock security system interrupt enabled
When the CSS is disabled by OPTION BYTE, the
CSSIE bit has no effect.
LVD
X
Application notes
In case the LVDRF flag is not cleared upon anoth-
er RESET type occurs (extern or watchdog), the
LVDRF flag remains set to keep trace of the origi-
nal failure.
In this condition, a watchdog reset can be detect-
ed by the software while an external reset not.
Table 4. Clock, Reset and Supply Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
CRSR
Reset Value
LVDRF
x
CFIE
0
CSSD
0
WDGRF
x
002Bh
0
0
0
0
33/125
ST72334J/N, ST72314J/N, ST72124J
4.5 MAIN CLOCK CONTROLLER (MCC)
The MCC block supplies the clock for the ST7
CPU and its internal peripherals. It allows to man-
age the power saving modes such as the SLOW
and ACTIVE-HALT modes. The whole functionali-
ty is managed by the Main Clock Control/Status
Register (MCCSR) and the Miscellaneous Regis-
ter 1 (MISCR1).
The counter allows to generate an interrupt based
on a accurate real time clock. Four different time
bases depending directly on f
are available.
OSC
The whole functionality is controlled by four bits of
the MCCSR register: TB1, TB0, OIE and OIF.
The clock-out capability allows to configure a ded-
icated I/O port pin as an f
/2 clock out to drive
OSC
The MCC block consists of:
external devices. It is controlled by the MCO bit in
the MISCR1 register.
– a programmable CPU clock prescaler
– a time base counter with interrupt capability
– a clock-out signal to supply external devices
When selected, the clock out pin suspends the
clock during ACTIVE-HALT mode.
The prescaler allows to select the main clock fre-
quency and is controlled with three bits of the
MISCR1: CP1, CP0 and SMS.
Figure 25. Main Clock Controller (MCC) Block Diagram
MCC
OSC2
f
OSC
OSCILLATOR
DIV 2
OSC1
DIV 2, 4, 8, 16
PROGRAMMABLE
DIVIDER
MCCSR
0
0
0
0
TB1 TB0 OIE OIF
MCC INTERRUPT
MISCR1
-
-
MCO
-
-
CP1 CP0 SMS
CPU CLOCK
TO CPU AND
PERIPHERALS
f
CPU
PORT
f
/2
MCO
ALTERNATE
FUNCTION
OSC
34/125
ST72334J/N, ST72314J/N, ST72124J
MAIN CLOCK CONTROLLER (Cont’d)
MISCELLANEOUS REGISTER 1 (MISCR1)
A modification of the time base is taken into ac-
count at the end of the current period (previously
set) to avoid unwanted time shift. This allows to
use this time base as a real time clock.
See section 6.2 on page 47.
MAIN CLOCK CONTROL/STATUS REGISTER
(MCCSR)
Read/Write
Bit 1 = OIE Oscillator interrupt enable
Reset Value: 0000 0001 (01h)
This bit set and cleared by software.
0: Oscillator interrupt disabled
7
0
0
1: Oscillator interrupt enabled
This interrupt allows to exit from ACTIVE-HALT
mode.
0
0
0
TB1
TB0
OIE
OIF
When this bit is set, calling the ST7 software HALT
instruction enters the ACTIVE-HALT power saving
mode
.
Bit 7:4 = Reserved, always read as 0.
Bit 0 = OIF Oscillator interrupt flag
This bit is set by hardware and cleared by software
reading the CSR register. It indicates when set
that the main oscillator has measured the selected
elapsed time (TB1:0).
Bit 3:2 = TB1-TB0 Time base control
These bits select the programmable divider time
base. They are set and cleared by software.
0: Timeout not reached
1: Timeout reached
Time Base
Counter
TB1 TB0
Prescaler
Warning: The BRES and BSET instructions must
not be used on the MCCSR register to avoid unin-
tentionally clearing the OIF bit.
f
=8MHz
f
=16MHz
OSC
OSC
32000
64000
4ms
8ms
2ms
4ms
0
0
1
1
0
1
0
1
160000
400000
20ms
50ms
10ms
25ms
Table 5. MCC Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
MCCSR
Reset Value
TB1
0
TB0
0
OIE
0
OIF
1
0029h
0
0
0
0
35/125
ST72334J/N, ST72314J/N, ST72124J
5 INTERRUPTS & POWER SAVING MODES
5.1 INTERRUPTS
The ST7 core may be interrupted by one of two dif-
ferent methods: maskable hardware interrupts as
listed in the Interrupt Mapping Table and a non-
maskable software interrupt (TRAP). The Interrupt
processing flowchart is shown in Figure 26.
The maskable interrupts must be enabled clearing
the I bit in order to be serviced. However, disabled
interrupts may be latched and processed when
they are enabled (see external interrupts subsec-
tion).
Halt low power mode (refer to the “Exit from HALT“
column in the Interrupt Mapping Table).
External Interrupts
External interrupt vectors can be loaded in the PC
register if the corresponding external interrupt oc-
curred and if the I bit is cleared. These interrupts
allow the processor to leave the Halt low power
mode.
When an interrupt has to be serviced:
The external interrupt polarity is selected through
the miscellaneous register or interrupt register (if
available).
– Normal processing is suspended at the end of
the current instruction execution.
External interrupt triggered on edge will be latched
and the interrupt request automatically cleared
upon entering the interrupt service routine.
– The PC, X, A and CC registers are saved onto
the stack.
– The I bit of the CC register is set to prevent addi-
tional interrupts.
If several input pins, connected to the same inter-
rupt vector, are configured as interrupts, their sig-
nals are logically ANDed before entering the edge/
level detection block.
– ThePC is then loaded with the interrupt vector of
the interrupt to service and the first instruction of
the interrupt service routine is fetched (refer to
the Interrupt Mapping Table for vector address-
es).
Warning: The type of sensitivity defined in the
Miscellaneous or Interrupt register (if available)
applies to the EI source. In case of an ANDed
source (as described on the I/O ports section), a
low level on an I/O pin configured as input with in-
terrupt, masks the interrupt request even in case
of rising-edge sensitivity.
The interrupt service routine should finish with the
IRET instruction which causes the contents of the
saved registers to be recovered from the stack.
Note: As a consequence of the IRET instruction,
the I bit will be cleared and the main program will
resume.
Peripheral Interrupts
Different peripheral interrupt flags in the status
register are able to cause an interrupt when they
are active if both:
Priority management
By default, the interrupt being serviced cannot be
interrupted because the I bit is set by hardware
when entering an interrupt routine.
– The I bit of the CC register is cleared.
– The corresponding enable bit is set in the control
register.
If several interrupts are simultaneously pending, a
hardware priority defines which one will be serv-
iced first (see the Interrupt Mapping Table).
If any of these two conditions is false, the interrupt
is latched and thus remains pending.
Non Maskable Software Interrupts
Clearing an interrupt request is done by:
This interrupt is entered when the TRAP instruc-
tion is executed regardless of the state of the I bit.
It will be serviced according to the flowchart on
Figure 26.
– writing “0” to the corresponding bit in the status
register or
– an access to the status register while the flag is
set followed by a read or write of an associated
register.
Interrupts and Low power mode
Note: the clearing sequence resets the internal
latch. A pending interrupt (i.e. waiting for being en-
abled) will therefore be lost if the clear sequence is
executed.
All interrupts allow the processor to leave the Wait
low power mode. Only external and specific men-
tioned interrupts allow the processor to leave the
36/125
ST72334J/N, ST72314J/N, ST72124J
INTERRUPTS (Cont’d)
Figure 26. Interrupt Processing Flowchart
FROM RESET
N
BIT I SET
Y
N
BIT I SET
Y
FETCH NEXT INSTRUCTION
N
IRET
STACK PC, X, A, CC
SET I BIT
Y
LOAD PC FROM INTERRUPT VECTOR
EXECUTE INSTRUCTION
RESTORE PC, X, A, CC FROM STACK
THIS CLEARS I BIT BY DEFAULT
Table 6. Interrupt Mapping
Exit
from
HALT
Source
Block
Register Priority
Address
Vector
N°
Description
Label
Order
RESET
TRAP
Reset
Highest
Priority
yes
no
FFFEh-FFFFh
FFFCh-FFFDh
FFFAh-FFFBh
N/A
Software Interrupt
Not used
0
1
MCC
CSS
Main Clock Controller Time Base Interrupt
or Clock Security System Interrupt
MCCSR
CRSR
yes
FFF8h-FFF9h
2
3
EI0
EI1
EI2
EI3
External Interrupt Port A3..0
External Interrupt Port F2..0
External Interrupt Port B3..0
External Interrupt Port B7..4
Not used
FFF6h-FFF7h
FFF4h-FFF5h
FFF2h-FFF3h
FFF0h-FFF1h
FFEEh-FFEFh
FFECh-FFEDh
FFEAh-FFEBh
FFE8h-FFE9h
FFE6h-FFE7h
FFE4h-FFE5h
FFE2h-FFE3h
FFE0h-FFE1h
N/A
4
5
6
7
SPI
SPI Peripheral Interrupts
TIMER A Peripheral Interrupts
TIMER B Peripheral Interrupts
SCI Peripheral Interrupts
SPISR
TASR
no
8
TIMER A
TIMER B
SCI
9
TBSR
10
SCISR
EECSR
11 Data-EEPROM Data EEPROM Interrupt
12
Lowest
Priority
Not used
13
37/125
ST72334J/N, ST72314J/N, ST72124J
5.2 POWER SAVING MODES
5.2.1 Introduction
To give a large measure of flexibility to the applica-
tion in terms of power consumption, four main
power saving modes are implemented in the ST7.
means of a master clock which is based on the
main oscillator frequency divided by 2 (f ).
CPU
From Run mode, the different power saving
modes may be selected by setting the relevant
register bits or by calling the specific ST7 software
instruction whose action depends on the the oscil-
lator status.
After a RESET the normal operating mode is se-
lected by default (RUN mode). This mode drives
the device (CPU and embedded peripherals) by
Figure 27. Power saving mode consumption / transitions
HALT
ACTIVE-HALT
SLOW WAIT
WAIT
SLOW
RUN
Low
High
POWER CONSUMPTION
5.2.2 HALT Modes
The HALT modes are the lowest power consump-
tion modes of the MCU. They are entered by exe-
cuting the ST7 HALT instruction (see Figure 29).
Mode capability or a reset (see Table 6 page 37).
A 4096 CPU clock cycles delay is performed be-
fore the CPU operation resumes (see Figure 28).
Two different HALT modes can be distinguished:
– HALT: main oscillator is turned off,
After the start up delay, the CPU resumes opera-
tion by servicing the interrupt or by fetching the re-
set vector which woke it up.
– ACTIVE-HALT: only main oscillator is running.
Table 7. HALT Modes selection
The decision to enter either in HALT or ACTIVE-
HALT mode is given by the main oscillator enable
interrupt flag (OIE bit in CROSS-MCCSR register:
see Table 7).
When entering HALT modes, the I bit in the CC
register is forced to 0 to enable interrupts.
MCCSR
OIE
Power Saving Mode entered when HALT
instruction is executed
flag
0
1
HALT (reset if watchdog enabled)
ACTIVE-HALT (no reset if watchdog enabled)
The MCU can exit HALT or ACTIVE-HALT modes
on reception of an interrupt with Exit from Halt
Figure 28. HALT /ACTIVE-HALT Modes timing overview
4096 CPU CYCLE
DELAY
HALT OR ACTIVE-HALT
RUN
RUN
FETCH
VECTOR
RESET
OR
HALT
INSTRUCTION
INTERRUPT
38/125
ST72334J/N, ST72314J/N, ST72124J
Specific ACTIVE-HALT mode
POWER SAVING MODES (Cont’d)
Standard HALT mode
In this mode the main oscillator is turned off caus-
ing all internal processing to be stopped, including
the operation of the on-chip peripherals. All periph-
erals are not clocked except the ones which get
their clock supply from another clock generator
(such as an external or auxiliary oscillator).
The compatibility of Watchdog operation with Halt
mode is configured by the “WDGHALT” option bit
of the OPTION BYTE. The HALT instruction when
executed while the Watchdog system is enabled,
can generate a Watchdog RESET (see dedicated
section for more details).
As soon as the interrupt capability of the main os-
cillator is selected (OIE bit set), the HALT instruc-
tion will make the device enter a specific ACTIVE-
HALT power saving mode instead of the standard
HALT one.
This mode consists of having only the main oscil-
lator and its associated counter running to keep a
wake-up time base. All other peripherals are not
clocked except the ones which get their clock sup-
ply from another clock generator (such as external
or auxiliary oscillator).
The safeguard against staying locked in this AC-
TIVE-HALT mode is insured by the oscillator inter-
rupt.
When exiting HALT mode by means of a RESET
or an interrupt, the oscillator is immediately turned
on and the 4096 CPU cycle delay is used to stabi-
lize the oscillator.
Note: As soon as the interrupt capability of one of
the oscillators is selected (OIE bit set), entering in
ACTIVE-HALT mode while the Watchdog is active
does not generate a RESET.
This means that the device cannot to spend more
than a defined delay in this power saving mode.
Figure 29. HALT modes flow-chart
If WDGHALT
bit reset in
HALT INSTRUCTION
OPTION BYTE
MAIN
1
0
N
Y
WATCHDOG
ENABLE
OSCILLATOR
OIE BIT
HALT
ACTIVE-HALT
OSCILLATOR
PERIPHERALS
CPU
OSCILLATOR
PERIPHERALS
CPU
OFF
OFF
OFF
0
ON
OFF
OFF
0
I BIT
I BIT
N
4096 clock cycles delay
RESET
Y
N
EXTERNAL*
INTERRUPT
OSCILLATOR
PERIPHERALS
CPU
ON
ON
ON
OSCILLATOR
PERIPHERALS
CPU
ON
OFF
OFF
FETCH RESET VECTOR
OR SERVICE INTERRUPT **
Y
Notes:
External interrupt or internal interrupts with Exit from Halt Mode capability
Before servicing an interrupt, the CC register is pushed on the stack.
*
**
39/125
ST72334J/N, ST72314J/N, ST72124J
POWER SAVING MODES (Cont’d)
5.2.3 WAIT Mode
WAIT mode places the MCU in a low power con-
sumption mode by stopping the CPU.
This power saving mode is selected by calling the
“WFI” ST7 software instruction.
All peripherals remain active. During WAIT mode,
the I bit of the CC register is forced to 0 to enable
all interrupts. All other registers and memory re-
main unchanged. The MCU remains in WAIT
mode until an interrupt or Reset occurs, whereup-
on the Program Counter branches to the starting
address of the interrupt or Reset service routine.
The MCU will remain in WAIT mode until a Reset
or an Interrupt occurs, causing it to wake up.
Refer to Figure 30.
Figure 30. WAIT mode flow-chart
OSCILLATOR
PERIPHERALS
CPU
I BIT
ON
ON
OFF
0
WFI INSTRUCTION
N
RESET
if exit caused by a RESET, a 4096 CPU
clock cycle delay is inserted.
Y
N
INTERRUPT
Y
OSCILLATOR
PERIPHERALS
CPU
ON
ON
ON
OSCILLATOR
PERIPHERALS
CPU
ON
OFF*
OFF
FETCH RESET VECTOR
OR SERVICE INTERRUPT**
Note:
The peripheral clock is stopped only when exit caused by RESET and not by an interrupt.
Before servicing an interrupt, the CC register is pushed on the stack.
*
**
40/125
ST72334J/N, ST72314J/N, ST72124J
POWER SAVING MODES (Cont’d)
5.2.4 SLOW Mode
This mode has two targets:
disables Slow mode and two CPx bits which select
the internal slow frequency (f
).
CPU
– Toreduce power consumption bydecreasing the
internal clock in the device,
In this mode, the oscillator frequency can be divid-
ed by 4, 8, 16 or 32 instead of 2 in normal operat-
ing mode. The CPU and peripherals are clocked at
this lower frequency.
– To adapt the internal clock frequency (f
the available supply voltage.
) to
CPU
SLOW mode is controlled by three bits in the
MISCR1 register: the SMS bit which enables or
Note: SLOW-WAIT mode is activated when enter-
ring the WAIT mode while the device is already in
SLOW mode.
Figure 31. SLOW Mode: timing diagram for internal CPU clock transitions
NEW FREQUENCY
ACTIVE WHEN
OSC/4 & OSC/8 = 0
NORMAL MODE ACTIVE
(OSC/4, OSC/8 STOPPED)
f
f
/4
/8
OSC
OSC
f
CPU
00
01
CP1:0
SMS
MISCR1
REGISTER
1
0
NEW FREQUENCY
REQUEST
NORMAL MODE
REQUEST
41/125
ST72334J/N, ST72314J/N, ST72124J
6 ON-CHIP PERIPHERALS
6.1 I/O PORTS
6.1.1 Introduction
Each external interrupt vector is linked to a dedi-
cated group of I/O port pins (see Interrupt section).
If more than one input pins are selected simultane-
ously as interrupt source, these are logically AND-
ed. For this reason if one of the interrupt pins is
tied low, it masks the other ones.
The I/O ports offer different functional modes:
– transfer of data through digital inputs and outputs
and for specific pins:
– external interrupt generation
– alternate signal input/output for the on-chip pe-
ripherals (SPI, SCI, TIMERs...).
In case of a floating input with interrupt configura-
tion, special cares mentioned in the I/O port imple-
mentation section have to be taken.
An I/O port contains up to 8 pins. Each pin can be
programmed independently as digital input (with or
without interrupt generation) or digital output.
Output Mode
6.1.2 Functional Description
Each port is associated to 2 main registers:
– Data Register (DR)
The output configuration is selected by setting the
corresponding DDR register bit.
In this case, writing the DR register applies this
digital value to the I/O pin through the latch. Then
reading the DR register returns the previously
stored value.
– Data Direction Register (DDR)
and one optional register:
Two different output modes can be selected by
software through the OR register: Output push-pull
and open-drain.
– Option Register (OR)
Each I/O pin may be programmed using the corre-
sponding register bits in DDR and OR registers: bit
X corresponding to pin X of the port. The same cor-
respondence is used for the DR register.
DR register value and output pin status:
DR
0
Push-pull
Open-drain
Vss
The following description takes into account the
OR register, for specific port which do not provide
this register refer to the I/O Port Implementation
section. The generic I/O block diagram is shown
on Figure 32
V
SS
DD
1
V
Floating
Note: In this mode, interrupt function is disabled.
Alternate function
Input Modes
When an on-chip peripheral is configured to use a
pin, the alternate function is automatically select-
ed. This alternate function takes priority over the
standard I/O programming.
The input configuration is selected by clearing the
corresponding DDR register bit.
In this case, reading the DR register returns the
digital value applied to the external I/O pin.
When the signal is coming from an on-chip periph-
eral, the I/O pin is automatically configured in out-
put mode (push-pull or open drain according to the
peripheral).
Different input modes can be selected by software
through the OR register.
Note1: Writing the DR register modifies the latch
value but does not affect the pin status.
Note2: When switching from input to output mode,
the DR register has to be written first to drive the
correct level on the pin as soon as the ports is con-
figured as an output.
When the signal is going to an on-chip peripheral,
the I/O pin has to be configured in input mode. In
this case, the pin’s state is also digitally readable
by addressing the DR register.
Note: Input pull-up configuration can cause unex-
pected value at the input of the alternate peripheral
input. When an on chip peripheral use a pin as in-
put and output, this pin has to be configured in in-
put floating mode.
External interrupt function
When an I/O is configured in Input with Interrupt,
an event on this I/O can generate an external In-
terrupt request to the CPU.
Each pin can independently generate an Interrupt
request. The interrupt sensitivity is given inde-
pendently according to the description mentioned
in the Miscellaneous register.
WARNING: The alternate function must not be ac-
tivated as long as the pin is configured as input
with interrupt, in order to avoid generating spurious
interrupts.
42/125
ST72334J/N, ST72314J/N, ST72124J
I/O PORTS (Cont’d)
Figure 32. I/O Block Diagram
ALTERNATE
OUTPUT
1
0
P-BUFFER
(see table below)
V
DD
ALTERNATE
ENABLE
PULL-UP
(see table below)
DR
V
DD
DDR
PULL-UP
CONDITION
PAD
OR
If implemented
OR SEL
N-BUFFER
DIODES
(see table below)
DDR SEL
DR SEL
ANALOG
INPUT
CMOS
SCHMITT
TRIGGER
1
0
ALTERNATE
INPUT
EXTERNAL
INTERRUPT
SOURCE (EIx)
FROM
OTHER
BITS
POLARITY
SELECTION
Table 8. Port Mode Options
Configuration Mode
Diodes
Pull-Up
P-Buffer
to V
to V
SS
DD
Floating with/without Interrupt
Pull-up with/without Interrupt
Off
On
Input
Off
On
Push-pull
On
Off
NI
On
Off
NI
Output
Open Drain (logic level)
True Open Drain
NI (see note)
Legend:NI - not implemented
Off - implemented not activated
On - implemented and activated
Note: the diode to V is not implemented in the
DD
true open drain pads. A local protection between
the pad and V is implemented to protect the de-
SS
vice against positive stress.
43/125
ST72334J/N, ST72314J/N, ST72124J
I/O PORTS (Cont’d)
6.1.3 I/O Port Implementation
Switching these I/O ports from one state to anoth-
er should be done in a sequence that prevents un-
wanted side effects. Recommended safe transi-
tions are illustrated in Figure 33 Other transitions
are potentially risky and should be avoided, since
they are likely to present unwanted side-effects
such as spurious interrupt generation.
The I/O port register configurations are summa-
rised as following.
Standard Ports
PA5:4, PC7:0, PD7:0, PE7:4, PE1:0, PF7:6, PF4
MODE
DDR
OR
Figure 33. Interrupt I/O Port State Transition
floating input
pull-up input
0
0
1
1
0
1
0
1
01
00
10
11
open drain output
push-pull output
INPUT
pull-up/floating
interrupt
INPUT
floating
(reset state)
OUTPUT
open-drain
OUTPUT
push-pull
Interrupt Ports
PA2:0, PB6:4, PB2:0, PF1:0 (with pull-up)
= DDR, OR
XX
MODE
DDR
OR
floating input
0
0
1
1
0
1
0
1
True Open Drain Ports
PA7:6
pull-up interrupt input
open drain output
push-pull output
MODE
DDR
floating input
0
1
PA3, PB7, PB3, PF2 (without pull-up)
open drain (high sink ports)
MODE
DDR
OR
floating input
0
0
1
1
0
1
0
1
floating interrupt input
open drain output
push-pull output
Table 9. Port Configuration
Input
Output
Port
Pin name
OR = 0
OR = 1
OR = 0
true open-drain
open drain push-pull
OR = 1
PA7:6
floating
PA5:4
floating
floating
floating
floating
floating
floating
floating
floating
floating
floating
floating
pull-up
Port A
Port B
PA3
floating interrupt
pull-up interrupt
floating interrupt
pull-up interrupt
pull-up
open drain
open drain
open drain
open drain
open drain
open drain
open drain
open drain
open drain
open drain
push-pull
push-pull
push-pull
push-pull
push-pull
push-pull
push-pull
push-pull
push-pull
push-pull
PA2:0
PB7, PB3
PB6:4, PB2:0
PC7:0
Port C
Port D
Port E
PD7:0
pull-up
PE7:4, PE1:0
PF7:6, PF4
PF2
pull-up
pull-up
Port F
floating interrupt
pull-up interrupt
PF1:0
44/125
ST72334J/N, ST72314J/N, ST72124J
I/O PORTS (Cont’d)
6.1.4 Register Description
DATA REGISTER (DR)
OPTION REGISTER (OR)
Port x Data Register
PxDR with x = A, B, C, D, E or F.
Port x Option Register
PxOR with x = A, B, C, D, E or F.
Read/Write
Read/Write
Reset Value: 0000 0000 (00h)
Reset Value: 0000 0000 (00h)
7
0
7
0
D7
D6
D5
D4
D3
D2
D1
D0
O7
O6
O5
O4
O3
O2
O1
O0
Bit 7:0 = D[7:0] Data register 8 bits.
Bit 7:0 = O[7:0] Option register 8 bits.
The DR register has a specific behaviour accord-
ing to the selected input/output configuration. Writ-
ing the DR register is always taken into account
even if the pin is configured as an input; this allows
to always have the expected level on the pin when
toggling to output mode. Reading the DR register
returns either the DR register latch content (pin
configured as output) or the digital value applied to
the I/O pin (pin configured as input).
For specific I/O pins, this register is not implement-
ed. In this case the DDR register is enough to se-
lect the I/O pin configuration.
The OR register allows to distinguish: in input
mode if the pull-up with interrupt capability or the
basic pull-up configuration is selected, in output
mode if the push-pull or open drain configuration is
selected.
Each bit is set and cleared by software.
Input mode:
0: floating input
1: pull-up input with or without interrupt
DATA DIRECTION REGISTER (DDR)
Port x Data Direction Register
PxDDR with x = A, B, C, D, E or F.
Output mode:
0: output open drain (with P-Buffer unactivated)
1: output push-pull
Read/Write
Reset Value: 0000 0000 (00h)
7
0
DD7
DD6
DD5
DD4
DD3
DD2
DD1
DD0
Bit 7:0 = DD[7:0] Data direction register 8 bits.
The DDR register gives the input/output direction
configuration of the pins. Each bits is set and
cleared by software.
0: Input mode
1: Output mode
45/125
ST72334J/N, ST72314J/N, ST72124J
I/O PORTS (Cont’d)
Table 10. I/O Port Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
Reset Value
of all IO port registers
0
0
0
0
0
0
0
0
0000h
0001h
0002h
0004h
0005h
0006h
0008h
0009h
000Ah
000Ch
000Dh
000Eh
0010h
0011h
0012h
0014h
0015h
0016h
PADR
PADDR
MSB
MSB
MSB
MSB
MSB
MSB
LSB
LSB
LSB
LSB
LSB
LSB
1)
PAOR
PCDR
PCDDR
PCOR
PBDR
PBDDR
1)
PBOR
PEDR
PEDDR
1)
PEOR
PDDR
PDDDR
1)
PDOR
PFDR
PFDDR
PFOR
Notes:
1) The bits corresponding to unavailable pins are forced to 1 by hardware, this affects the reset status value.
46/125
ST72334J/N, ST72314J/N, ST72124J
6.2.2 I/O Port Alternate Functions
6.2 MISCELLANEOUS REGISTERS
The miscellaneous registers allow control over
several different features such as the external in-
terrupts or the I/O alternate functions.
The MISCR registers manage four I/O port miscel-
laneous alternate functions:
■ Main clock signal (f
) output on PF0
6.2.1 I/O Port Interrupt Sensitivity Description
CPU
■ A beep signal output on PF1 (with 3 selectable
The external interrupt sensitivity is controlled by
the ISxx bits of the MISCR1 miscellaneous regis-
ter. This control allows to have two fully independ-
ent external interrupt source sensitivities.
audio frequencies)
■ SPI pin configuration:
– SS pin internal control to use the PC7 I/O port
function while the SPI is active.
These functions are described in detail in the Sec-
tion 6.2.3 Miscellaneous Registers Description.
Each external interrupt source can be generated
on four different events on the pin:
■ Falling edge
■ Rising edge
■ Falling and rising edge
■ Falling edge and low level
To guarantee correct functionality, the sensitivity
bits in the MISCR1 register must be modified only
when the I bit of the CC register is set to 1 (inter-
rupt masked). See I/O port register and Miscella-
neous register descriptions for more details on the
programming.
47/125
ST72334J/N, ST72314J/N, ST72124J
MISCELLANEOUS REGISTERS (Cont’d)
6.2.3 Miscellaneous Registers Description
MISCELLANEOUS REGISTER 1 (MISCR1)
Read/Write
Bit 4:3 = IS2[1:0] EI0 and EI1 sensitivity
The interrupt sensitivity, defined using the IS2[1:0]
bits, is applied to the following external interrupts:-
EI0 (port A3..0) and EI1 (port F2..0). These 2 bits
can be written only when the I bit of the CC register
is set to 1 (interrupt disabled).
Reset Value: 0000 0000 (00h)
7
0
IS11 IS10 MCO IS21 IS20 CP1 CP0 SMS
Bit 2:1 = CP[1:0] CPU clock prescaler
These bits select the CPU clock prescaler which is
applied in the different slow modes. Their action is
conditioned by the setting of the SMS bit. These
two bits are set and cleared by software
Bit 7:6 = IS1[1:0] EI2 and EI3 sensitivity
The interrupt sensitivity, defined using the IS1[1:0]
bits, is applied to the following external interrupts:
EI2 (port B3..0) and EI3 (port B7..4). These 2 bits
can be written only when the I bit of the CC register
is set to 1 (interrupt disabled).
CP1 CP0
f
in SLOW mode
CPU
0
1
0
1
0
0
1
1
f
f
f
f
/ 4
OSC
OSC
OSC
OSC
/ 8
/ 16
/ 32
IS11 IS10
External Interrupt Sensitivity
Falling edge & low level
Rising edge only
0
0
1
1
0
1
0
1
Falling edge only
Bit 0 = SMS Slow mode select
This bit is set and cleared by software.
Rising and falling edge
0: Normal mode. f
= fOSC / 2
is given by CP1, CP0
CPU
1: Slow mode. f
CPU
See low power consumption mode and MCC
chapters for more details.
Bit 5 = MCO Main clock out selection
This bit enables the MCO alternate function on the
I/O port. It is set and cleared by software.
0: MCO alternate function disabled
(I/O pin free for general-purpose I/O)
1: MCO alternate function enabled
(f
/2 on I/O port)
OSC
Note: To reduce power consumption, the MCO
function is not active in ACTIVE-HALT mode.
48/125
ST72334J/N, ST72314J/N, ST72124J
MISCELLANEOUS REGISTERS (Cont’d)
MISCELLANEOUS REGISTER 2 (MISCR2)
Read/Write
Reset Value: 0000 0000 (00h)
7
0
-
-
BC1 BC0
-
-
SSM SSI
Bit 7:6 = Reserved Must always be cleared
Bit 5:4 = BC[1:0] Beep control
These 2 bits select the PF1 pin beep capability.
BC1 BC0
Beep mode with f
Off
=16MHz
OSC
0
0
1
1
0
1
0
1
~2-KHz
Output
Beep signal
~1-KHz
~50% duty cycle
~500-Hz
The beep output signal is available in ACTIVE-
HALT mode but has to be disabled to reduce the
consumption.
Bit 3:2 = Reserved Must always be cleared
Bit 1 = SSM SS mode selection
It is set and cleared by software.
0: Normal mode - SS uses information coming
from the SS pin of the SPI.
1: I/O mode, the SPI uses the information stored
into bit SSI.
Bit 0 = SSI SS internal mode
This bit replaces pin SS of the SPI when bit SSM is
set to 1. (see SPI description). It is set and cleared
by software.
Table 11. Miscellaneous Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
MISCR1
Reset Value
IS11
0
IS10
0
MCO
0
IS21
0
IS20
0
CP1
0
CP0
0
SMS
0
0020h
0040h
MISCR2
Reset Value
BC1
0
BC0
0
SSM
0
SSI
0
0
0
0
0
49/125
ST72334J/N, ST72314J/N, ST72124J
6.3 WATCHDOG TIMER (WDG)
6.3.1 Introduction
■ Hardware Watchdog selectable by option byte
■ Watchdog Reset indicated by status flag (in
The Watchdog timer is used to detect the occur-
rence of a software fault, usually generated by ex-
ternal interference or by unforeseen logical condi-
tions, which causes the application program to
abandon its normal sequence. The Watchdog cir-
cuit generates an MCU reset on expiry of a pro-
grammed time period, unless the program refresh-
es the counter’s contents before the T6 bit be-
comes cleared.
versions with Safe Reset option only)
6.3.3 Functional Description
The counter value stored in the CR register (bits
T[6:0]), is decremented every 12,288 machine cy-
cles, and the length of the timeout period can be
programmed by the user in 64 increments.
6.3.2 Main Features
■ Programmable timer (64 increments of 12288
If the watchdog is activated (the WDGA bit is set)
and when the 7-bit timer (bits T[6:0]) rolls over
from 40h to 3Fh (T6 becomes cleared), it initiates
a reset cycle pulling low the reset pin for typically
500ns.
CPU cycles)
■ Programmable reset
■ Reset (if watchdog activated) after a HALT
instruction or when the T6 bit reaches zero
Figure 34. Watchdog Block Diagram
RESET
WATCHDOG CONTROL REGISTER (CR)
T5 T1 T0
WDGA T6
T4
T2
T3
7-BIT DOWNCOUNTER
CLOCK DIVIDER
f
CPU
÷12288
50/125
ST72334J/N, ST72314J/N, ST72124J
WATCHDOG TIMER (Cont’d)
The application program must write in the CR reg-
ister at regular intervals during normal operation to
prevent an MCU reset. The value to be stored in
the CR register must be between FFh and C0h
(see Table 12 .Watchdog Timing (fCPU = 8 MHz)):
6.3.7 Register Description
CONTROL REGISTER (CR)
Read/Write
Reset Value: 0111 1111 (7Fh)
– The WDGA bit is set (watchdog enabled)
7
0
– The T6 bit is set to prevent generating an imme-
diate reset
WDGA T6
T5
T4
T3
T2
T1
T0
– The T[5:0] bits contain the number of increments
which represents the time delay before the
watchdog produces a reset.
Bit 7 = WDGA Activation bit.
This bit is set by software and only cleared by
hardware after a reset. When WDGA = 1, the
watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled
Table 12.Watchdog Timing (f
= 8 MHz)
CPU
CR Register
initial value
WDG timeout period
(ms)
Max
Min
FFh
C0h
98.304
1.536
Note: This bit is not used if the hardware watch-
dog option is enabled by option byte.
Bit 6:0 = T[6:0] 7-bit timer (MSB to LSB).
These bits contain the decremented value. A reset
is produced when it rolls over from 40h to 3Fh (T6
becomes cleared).
Notes: Following a reset, the watchdog is disa-
bled. Once activated it cannot be disabled, except
by a reset.
The T6 bit can be used to generate a software re-
set (the WDGA bit is set and the T6 bit is cleared).
STATUS REGISTER (SR)
Read/Write
If the watchdog is activated, the HALT instruction
will generate a Reset.
Reset Value*: 0000 0000 (00h)
6.3.4 Hardware Watchdog Option
7
-
0
If Hardware Watchdog Is selected by option byte,
the watchdog is always active and the WDGA bit in
the CR is not used.
-
-
-
-
-
-
WDOGF
Refer to the device-specific Option Byte descrip-
tion.
Bit 0 = WDOGF Watchdog flag.
This bit is set by a watchdog reset and cleared by
software or a power on/off reset. This bit is useful
for distinguishing power/on off or external reset
and watchdog reset.
6.3.5 Low Power Modes
Mode
Description
0: No Watchdog reset occurred
1: Watchdog reset occurred
WAIT
No effect on Watchdog.
Immediate reset generation as soon as
the HALT instruction is executed if the
Watchdog is activated (WDGA bit is
set).
* Only by software and power on/off reset
HALT
Note: This register is not used in versions without
LVD Reset.
6.3.6 Interrupts
None.
51/125
ST72334J/N, ST72314J/N, ST72124J
WATCHDOG TIMER (Cond’t)
Table 13. Watchdog Timer Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
WDGCR
WDGA
0
T6
1
T5
1
T4
1
T3
1
T2
1
T1
1
T0
1
002Ah
Reset Value
52/125
ST72334J/N, ST72314J/N, ST72124J
6.4 16-BIT TIMER
6.4.1 Introduction
6.4.3 Functional Description
6.4.3.1 Counter
The timer consists of a 16-bit free-running counter
driven by a programmable prescaler.
The principal block of the Programmable Timer is
a 16-bit free running increasing counter and its as-
sociated 16-bit registers:
It may be used for a variety of purposes, including
pulse length measurement of up to two input sig-
nals (input capture) or generation of up to two out-
put waveforms (output compare and PWM).
Counter Registers
– Counter High Register (CHR) is the most sig-
nificant byte (MSB).
Pulse lengths and waveform periods can be mod-
ulated from a few microseconds to several milli-
seconds using the timer prescaler and the CPU
clock prescaler.
– Counter Low Register (CLR) is the least sig-
nificant byte (LSB).
Alternate Counter Registers
– Alternate Counter High Register (ACHR) is the
most significant byte (MSB).
6.4.2 Main Features
■ Programmable prescaler:fCPU dividedby2, 4or 8.
■ Overflow status flag and maskable interrupt
– Alternate Counter Low Register (ACLR) is the
least significant byte (LSB).
■ External clock input (must be at least 4 times
slower thanthe CPUclock speed)with the choice
of active edge
These two read-only 16-bit registers contain the
same value but with the difference that reading the
ACLR register does not clear the TOF bit (overflow
flag), (see note at the end of paragraph titled 16-bit
read sequence).
■ Output compare functions with
– 2 dedicated 16-bit registers
– 2 dedicated programmable signals
– 2 dedicated status flags
Writing in the CLR register or ACLR register resets
the free running counter to the FFFCh value.
– 1 dedicated maskable interrupt
■ Input capture functions with
The timer clock depends on the clock control bits
of the CR2 register, as illustrated in Table 14 Clock
Control Bits. The value in the counter register re-
peats every 131.072, 262.144 or 524.288 internal
processorclock cycles depending on the CC1 and
CC0 bits.
– 2 dedicated 16-bit registers
– 2 dedicated active edge selection signals
– 2 dedicated status flags
– 1 dedicated maskable interrupt
■ Pulse width modulation mode (PWM)
■ One pulse mode
■ 5 alternate functionson I/O ports (ICAP1,ICAP2,
OCMP1, OCMP2, EXTCLK)*
The Block Diagram is shown in Figure 35.
*Note: Some external pins are not available on all
devices. Refer to the device pin out description.
When reading an input signal which is not availa-
ble on an external pin, the value will always be ‘1’.
53/125
ST72334J/N, ST72314J/N, ST72124J
16-BIT TIMER (Cont’d)
Figure 35. Timer Block Diagram
ST7 INTERNAL BUS
f
CPU
MCU-PERIPHERAL INTERFACE
8 low
8-bit
8 high
8
8
8
8
8
8
8
8
buffer
EXEDG
h
w
h
w
h
w
h
low
16
INPUT
CAPTURE
REGISTER
INPUT
CAPTURE
REGISTER
OUTPUT
COMPARE
REGISTER
OUTPUT
COMPARE
REGISTER
16 BIT
FREE RUNNING
1/2
1/4
1/8
COUNTER
1
1
2
2
COUNTER
ALTERNATE
REGISTER
16
16
16
CC1 CC0
TIMER INTERNAL BUS
16
16
OVERFLOW
DETECT
EXTCLK
EDGE DETECT
CIRCUIT1
OUTPUT COMPARE
CIRCUIT
ICAP1
ICAP2
CIRCUIT
6
EDGE DETECT
CIRCUIT2
OCMP1
OCMP2
LATCH1
LATCH2
ICF1 OCF1 TOF ICF2 OCF2
0
0
0
SR
ICIE OCIE TOIE FOLV2 FOLV1OLVL2 IEDG1 OLVL1
OC1E
OPM PWM CC1 CC0 IEDG2 EXEDG
OC2E
CR1
CR2
TIMER INTERRUPT
54/125
ST72334J/N, ST72314J/N, ST72124J
16-BIT TIMER (Cont’d)
16-bit read sequence: (from either the Counter
Register or the Alternate Counter Register).
Clearing the overflow interrupt request is done in
two steps:
1. Reading the SR register while the TOF bit is set.
2. An access (read or write) to the CLR register.
Beginning of the sequence
Notes: The TOF bit is not cleared by accesses to
ACLR register. This feature allows simultaneous
use of the overflow function and reads of the free
running counter at random times (for example, to
measure elapsed time) without the risk of clearing
the TOF bit erroneously.
Read MSB
At t0
LSB is buffered
Other
instructions
Returns the buffered
LSB value at t0
The timer is not affected by WAIT mode.
Read LSB
At t0 +∆t
In HALT mode, the counter stops counting until the
mode is exited. Counting then resumes from the
previous count (MCU awakened by an interrupt) or
from the reset count (MCU awakened by a Reset).
Sequence completed
The user must read the MSB first, then the LSB
value is buffered automatically.
This buffered value remains unchanged until the
16-bit read sequence is completed, even if the
user reads the MSB several times.
6.4.3.2 External Clock
The external clock (where available) is selected if
CC0=1 and CC1=1 in CR2 register.
After a complete reading sequence, if only the
CLR register or ACLR register are read, they re-
turn the LSB of the count value at the time of the
read.
The status of the EXEDG bit determines the type
of level transition on the external clock pin EXT-
CLK that will trigger the free running counter.
The counter is synchronised with the falling edge
of the internal CPU clock.
Whatever the timer mode used (input capture, out-
put compare, one pulse mode or PWM mode) an
overflow occurs when the counter rolls over from
FFFFh to 0000h then:
At least four falling edges of the CPU clock must
occur between two consecutive active edges of
the external clock; thus the external clock frequen-
cy must be less than a quarter of the CPU clock
frequency.
– The TOF bit of the SR register is set.
– A timer interrupt is generated if:
– TOIE bit of the CR1 register is set and
– I bit of the CC register is cleared.
If one of these conditions is false, the interrupt re-
mains pending to be issued as soon as they are
both true.
55/125
ST72334J/N, ST72314J/N, ST72124J
16-BIT TIMER (Cont’d)
Figure 36. Counter Timing Diagram, internal clock divided by 2
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
FFFD FFFE FFFF 0000 0001 0002 0003
COUNTER REGISTER
OVERFLOW FLAG TOF
Figure 37. Counter Timing Diagram, internal clock divided by 4
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
FFFC
FFFD
0000
0001
COUNTER REGISTER
OVERFLOW FLAG TOF
Figure 38. Counter Timing Diagram, internal clock divided by 8
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
0000
FFFC
FFFD
COUNTER REGISTER
OVERFLOW FLAG TOF
56/125
ST72334J/N, ST72314J/N, ST72124J
16-BIT TIMER (Cont’d)
6.4.3.3 Input Capture
When an input capture occurs:
– ICFi bit is set.
In this section, the index, i, may be 1 or 2.
The two input capture 16-bit registers (IC1R and
IC2R) are used to latch the value of the free run-
ning counter after a transition detected by the
ICAPi pin (see figure 5).
– The ICiR register contains the value of the free
running counter on the active transition on the
ICAPi pin (see Figure 40).
– A timer interrupt is generated if the ICIE bit is set
and the I bit is cleared in the CC register. Other-
wise, the interrupt remains pending until both
conditions become true.
MS Byte
ICiHR
LS Byte
ICiLR
ICiR
Clearing the Input Capture interrupt request is
done in two steps:
ICi register is a read-only register.
The active transition is software programmable
through the IEDGi bit of the Control Register (CRi).
1. Reading the SR register while the ICFi bit is set.
2. An access (read or write) to the ICiLR register.
Timing resolution is one count of the free running
counter: (f
/(CC1.CC0)).
CPU
Notes:
Procedure:
2. After reading the ICiHR register, transfer of
input capture data is inhibited until the ICiLR
register is also read.
To use the input capture function select the follow-
ing in the CR2 register:
3. The ICiR register always contains the free run-
ning counter value which corresponds to the
most recent input capture.
– Select the timer clock (CC1-CC0) (see Table 14
Clock Control Bits).
– Select the edge of the active transition on the
ICAP2 pin with the IEDG2 bit (the ICAP2 pin
must be configured as floating input).
4. The 2 input capture functions can be used
together even if the timer also uses the output
compare mode.
And select the following in the CR1 register:
5. In One pulse Mode and PWM mode only the
input capture 2 can be used.
– Set the ICIE bit to generate an interrupt after an
input capture coming from both the ICAP1 pin or
the ICAP2 pin
6. The alternate inputs (ICAP1 & ICAP2) are
always directly connected to the timer. So any
transitions on these pins activate the input cap-
ture process.
– Select the edge of the active transition on the
ICAP1 pin with the IEDG1 bit (the ICAP1pin must
be configured as floating input).
7. Moreover if one of the ICAPi pin is configured
as an input and the second one as an output,
an interrupt can be generated if the user toggle
the output pin and if the ICIE bit is set.
8. The TOF bit can be used with interrupt in order
to measure event that go beyond the timer
range (FFFFh).
57/125
ST72334J/N, ST72314J/N, ST72124J
16-BIT TIMER (Cont’d)
Figure 39. Input Capture Block Diagram
ICAP1
pin
(Control Register 1) CR1
IEDG1
EDGE DETECT
CIRCUIT2
EDGE DETECT
CIRCUIT1
ICIE
ICAP2
pin
(Status Register) SR
ICF1
ICF2
0
0
0
IC2R Register
IC1R Register
(Control Register 2) CR2
16-BIT
16-BIT FREE RUNNING
COUNTER
IEDG2
CC0
CC1
Figure 40. Input Capture Timing Diagram
TIMER CLOCK
FF01
FF02
FF03
COUNTER REGISTER
ICAPi PIN
ICAPi FLAG
FF03
ICAPi REGISTER
Note: Active edge is rising edge.
58/125
ST72334J/N, ST72314J/N, ST72124J
16-BIT TIMER (Cont’d)
6.4.3.4 Output Compare
∆t f
In this section, the index, i, may be 1 or 2.
* CPU
∆ OCiR =
This function can be used to control an output
waveform or indicating when a period of time has
elapsed.
PRESC
Where:
∆t
= Desired output compare period (in sec-
onds)
When a match is found between the Output Com-
pare register and the free running counter, the out-
put compare function:
f
= Internal clock frequency
CPU
= Timer prescaler factor (2, 4 or 8 de-
pending on CC1-CC0 bits, see Table 14
Clock Control Bits)
PRESC
– Assigns pins with a programmable value if the
OCIE bit is set
– Sets a flag in the status register
– Generates an interrupt if enabled
Clearing the output compare interrupt request is
done by:
Two 16-bit registers Output Compare Register 1
(OC1R) and Output Compare Register 2 (OC2R)
contain the value to be compared to the free run-
ning counter each timer clock cycle.
1. Reading the SR register while the OCFi bit is
set.
2. An access (read or write) to the OCiLR register.
The following procedure is recommended to pre-
vent the OCFi bit from being set between the time
it is read and the write to the OCiR register:
MS Byte
OCiHR
LS Byte
OCiLR
OCiR
– Write to the OCiHR register (further compares
are inhibited).
These registers are readable and writable and are
not affected by the timer hardware. A reset event
changes the OCiR value to 8000h.
– Read the SR register (first step of the clearance
of the OCFi bit, which may be already set).
Timing resolution is one count of the free running
counter: (f
).
– Write to the OCiLR register (enables the output
compare function and clears the OCFi bit).
CPU/(CC1.CC0)
Procedure:
Notes:
To use the output compare function, select the fol-
lowing in the CR2 register:
1. After a processor write cycle to the OCiHR reg-
ister, the output compare function is inhibited
until the OCiLR register is also written.
– Set the OCiE bit if an output is needed then the
OCMPi pin is dedicated to the output compare i
function.
2. If the OCiE bit is not set, the OCMPi pin is a
general I/O port and the OLVLi bit will not
appear when a match is found but an interrupt
could be generated if the OCIE bit is set.
– Select the timer clock (CC1-CC0) (see Table 14
Clock Control Bits).
And select the following in the CR1 register:
3. When the clock is divided by 2, OCFi and
OCMPi are set while the counter value equals
the OCiR register value (see Figure 42). This
behaviour is the same in OPM or PWM mode.
When the clock is divided by 4, 8 or in external
clock mode, OCFi and OCMPi are set while the
counter value equals the OCiR register value
plus 1 (see Figure 43).
– Select the OLVLi bit to applied to the OCMPi pins
after the match occurs.
– Set the OCIE bit to generate an interrupt if it is
needed.
When a match is found:
– OCFi bit is set.
– The OCMPi pin takes OLVLi bit value (OCMPi
pin latch is forced low during reset and stays low
until valid compares change it to a high level).
4. The output compare functions can be used both
for generating external events on the OCMPi
pins even if the input capture mode is also
used.
– A timer interrupt is generated if the OCIE bit is
set in the CR2 register and the I bit is cleared in
the CC register (CC).
5. The value in the 16-bit OCiR register and the
OLVi bit should be changed after each suc-
cessful comparison in order to control an output
waveform or establish a new elapsed timeout.
The OCiR register value required for a specific tim-
ing application can be calculated using the follow-
ing formula:
59/125
ST72334J/N, ST72314J/N, ST72124J
16-BIT TIMER (Cont’d)
Figure 41. Output Compare Block Diagram
16 BIT FREE RUNNING
OC1E
CC1 CC0
OC2E
COUNTER
(Control Register 2) CR2
16-bit
(Control Register 1) CR1
OUTPUT COMPARE
CIRCUIT
Latch
1
OCIE
OLVL2
OLVL1
OCMP1
Pin
16-bit
16-bit
Latch
2
OCMP2
Pin
OC1R Register
OCF1
OCF2
0
0
0
OC2R Register
(Status Register) SR
Figure 42. Output Compare Timing Diagram, Internal Clock Divided by 2
INTERNAL CPU CLOCK
TIMER CLOCK
2ECF 2ED0 2ED1 2ED2
2ED3
2ED4
2ED3
COUNTER
OUTPUT COMPARE REGISTER
OUTPUT COMPARE FLAG (OCFi)
OCMPi PIN (OLVLi=1)
Figure 43. Output Compare Timing Diagram, Internal Clock Divided by 4
INTERNAL CPU CLOCK
TIMER CLOCK
2ECF 2ED0 2ED1 2ED2
2ED3
2ED4
2ED3
COUNTER
OUTPUT COMPARE REGISTER
COMPARE REGISTER LATCH
OCFi AND OCMPi PIN (OLVLi=1)
60/125
ST72334J/N, ST72314J/N, ST72124J
16-BIT TIMER (Cont’d)
6.4.3.5 Forced Compare
In this section i may represent 1 or 2.
The following bits of the CR1 register are used:
One pulse mode cycle
When
OCMP1 = OLVL2
event occurs
FOLV2 FOLV1 OLVL2
OLVL1
on ICAP1
Counter is reset
to FFFCh
When the FOLVi bit is set by software, the OLVLi
bit is copied to the OCMPi pin. The OLVi bit has to
be toggled in order to toggle the OCMPi pin when
it is enabled (OCiE bit=1). The OCFi bit is then not
set by hardware, and thus no interrupt request is
generated.
ICF1 bit is set
When
Counter
OCMP1 = OLVL1
= OC1R
FOLVLi bits have no effect in both one pulse mode
and PWM mode.
Then, on a valid event on the ICAP1 pin, the coun-
ter is initialized to FFFCh and OLVL2 bit is loaded
on the OCMP1 pin, the ICF1 bit is set and the val-
ue FFFDh is loaded in the IC1R register.
6.4.3.6 One Pulse Mode
One Pulse mode enables the generation of a
pulse when an external event occurs. This mode is
selected via the OPM bit in the CR2 register.
When the value of the counter is equal to the value
of the contents of the OC1R register, the OLVL1
bit is output on the OCMP1 pin, (See Figure 44).
The one pulse mode uses the Input Capture1
function and the Output Compare1 function.
Procedure:
Notes:
To use one pulse mode:
1. The OCF1 bit cannot be set by hardware in one
pulse mode but the OCF2 bit can generate an
Output Compare interrupt.
1. Load the OC1R register with the value corre-
sponding to the length of the pulse (see the for-
mula in Section 6.4.3.7).
2. The ICF1 bit is set when an active edge occurs
and can generate an interrupt if the ICIE bit is
set.
2. Select the following in the CR1 register:
– Using the OLVL1 bit, select the level to be ap-
plied to the OCMP1 pin after the pulse.
3. When the Pulse Width Modulation (PWM) and
One Pulse Mode (OPM) bits are both set, the
PWM mode is the only active one.
– Using the OLVL2 bit, select the level to be ap-
plied to the OCMP1 pin during the pulse.
4. If OLVL1=OLVL2 a continuous signal will be
seen on the OCMP1 pin.
– Select the edge of the active transition on the
ICAP1 pin with the IEDG1 bit (the ICAP1 pin
must be configured as floating input).
5. The ICAP1 pin can not be used to perform input
capture. The ICAP2 pin can be used to perform
input capture (ICF2 can be set and IC2R can be
loaded) but the user must take care that the
counter is reset each time a valid edge occurs
on the ICAP1 pin and ICF1 can also generates
interrupt if ICIE is set.
3. Select the following in the CR2 register:
– Set the OC1E bit, the OCMP1 pin is then ded-
icated to the Output Compare 1 function.
– Set the OPM bit.
– Select the timer clock CC1-CC0 (see Table 14
Clock Control Bits).
6. When the one pulse mode is used OC1R is
dedicated to this mode. Nevertheless OC2R
and OCF2 can be used to indicate a period of
time has been elapsed but cannot generate an
output waveform because the level OLVL2 is
dedicated to the one pulse mode.
61/125
ST72334J/N, ST72314J/N, ST72124J
Figure 44. One Pulse Mode Timing Example
....
FFFC FFFD FFFE
2ED0 2ED1 2ED2
2ED3
FFFC FFFD
COUNTER
ICAP1
OLVL2
OLVL1
OLVL2
OCMP1
compare1
Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1
Figure 45. Pulse Width Modulation Mode Timing Example
34E2 FFFC FFFD FFFE
2ED0 2ED1 2ED2
34E2 FFFC
COUNTER
OCMP1
OLVL2
OLVL1
OLVL2
compare2
compare1
compare2
Note: OC1R=2ED0h, OC2R=34E2, OLVL1=0, OLVL2= 1
62/125
ST72334J/N, ST72314J/N, ST72124J
16-BIT TIMER (Cont’d)
6.4.3.7 Pulse Width Modulation Mode
The Output Compare 2 event causes the counter
to be initialized to FFFCh (See Figure 45).
Pulse Width Modulation (PWM) mode enables the
generation of a signal with a frequency and pulse
length determined by the value of the OC1R and
OC2R registers.
Pulse Width Modulation cycle
When
The pulse width modulation mode uses the com-
plete Output Compare 1 function plus the OC2R
register, and so these functionality can not be
used when the PWM mode is activated.
Counter
= OC1R
OCMP1 = OLVL1
Procedure
OCMP1 = OLVL2
To use pulse width modulation mode:
When
Counter
= OC2R
Counter is reset
to FFFCh
1. Load the OC2R register with the value corre-
sponding to the period of the signal.
2. Load the OC1R register with the value corre-
sponding to the length of the pulse if (OLVL1=0
and OLVL2=1).
ICF1 bit is set
Notes:
3. Select the following in the CR1 register:
1. After a write instruction to the OCiHR register,
the output compare function is inhibited until the
OCiLR register is also written.
– Using the OLVL1 bit, select the level to be ap-
plied to the OCMP1 pin after a successful
comparison with OC1R register.
Therefore the Input Capture 1 function is inhib-
ited but the Input Capture 2 is available.
– Using the OLVL2 bit, select the level to be ap-
plied to the OCMP1 pin after a successful
comparison with OC2R register.
2. The OCF1 and OCF2 bits cannot be set by
hardware in PWM mode therefore the Output
Compare interrupt is inhibited.
4. Select the following in the CR2 register:
– Set OC1E bit: the OCMP1 pin is then dedicat-
ed to the output compare 1 function.
3. The ICF1 bit is set by hardware when the coun-
ter reaches the OC2R value and can produce a
timer interrupt if the ICIE bit is set and the I bit is
cleared.
– Set the PWM bit.
– Select the timer clock (CC1-CC0) (see Table
14 Clock Control Bits).
4. In PWM mode the ICAP1 pin can not be used
to perform input capture because it is discon-
nected to the timer. The ICAP2 pin can be used
to perform input capture (ICF2 can be set and
IC2R can be loaded) but the user must take
care that the counter is reset each period and
ICF1 can also generates interrupt if ICIE is set.
If OLVL1=1 and OLVL2=0 the length of the posi-
tive pulse is the difference between the OC2R and
OC1R registers.
If OLVL1=OLVL2 a continuous signal will be seen
on the OCMP1 pin.
The OCiR register value required for a specific tim-
ing application can be calculated using the follow-
ing formula:
5. When the Pulse Width Modulation (PWM) and
One Pulse Mode (OPM) bits are both set, the
PWM mode is the only active one.
t * f
CPU
PRESC
- 5
OCiR Value =
Where:
t
= Desired output compare period (in sec-
onds)
f
= Internal clock frequency
CPU
= Timer prescaler factor (2, 4 or 8 de-
pending on CC1-CC0 bits, see Table 14
Clock Control Bits)
PRESC
63/125
ST72334J/N, ST72314J/N, ST72124J
16-BIT TIMER (Cont’d)
6.4.4 Low Power Modes
Mode
Description
No effect on 16-bit Timer.
WAIT
Timer interrupts cause the device to exit from WAIT mode.
16-bit Timer registers are frozen.
In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous
count when the MCU is woken up by an interrupt with “exit from HALT mode” capability or from the counter
reset value when the MCU is woken up by a RESET.
HALT
If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is armed. Consequent-
ly, when the MCU is woken up by an interrupt with “exit from HALT mode” capability, the ICFi bit is set, and
the counter value present when exiting from HALT mode is captured into the ICiR register.
6.4.5 Interrupts
Enable
Control from
Bit
Exit
Exit
from
Halt
Event
Flag
Interrupt Event
Wait
Yes
Yes
Yes
Yes
Yes
Input Capture 1 event/Counter reset in PWM mode
Input Capture 2 event
ICF1
ICF2
No
No
No
No
No
ICIE
Output Compare 1 event (not available in PWM mode)
Output Compare 2 event (not available in PWM mode)
Timer Overflow event
OCF1
OCF2
TOF
OCIE
TOIE
Note: The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts chap-
ter). These events generate an interrupt if the corresponding Enable Control Bit is set and the I-bit in the
CC register is reset (RIM instruction).
64/125
ST72334J/N, ST72314J/N, ST72124J
16-BIT TIMER (Cont’d)
6.4.6 Register Description
Bit 4 = FOLV2 Forced Output Compare 2.
This bit is set and cleared by software.
0: No effect on the OCMP2 pin.
1:Forces the OLVL2 bit to be copied to the
OCMP2 pin, if the OC2E bit is set and even if
there is no successful comparison.
Each Timer is associated with three control and
status registers, and with six pairs of data registers
(16-bit values) relating to the two input captures,
the two output compares, the counter and the al-
ternate counter.
Bit 3 = FOLV1 Forced Output Compare 1.
This bit is set and cleared by software.
0: No effect on the OCMP1 pin.
CONTROL REGISTER 1 (CR1)
Read/Write
1: Forces OLVL1 to becopied to the OCMP1 pin, if
the OC1E bit is set and even if there is no suc-
cessful comparison.
Reset Value: 0000 0000 (00h)
7
0
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
Bit 2 = OLVL2 Output Level 2.
This bit is copied to the OCMP2 pin whenever a
successful comparison occurs with the OC2R reg-
ister and OCxE is set in the CR2 register. This val-
ue is copied to the OCMP1 pin in One Pulse Mode
and Pulse Width Modulation mode.
Bit 7 = ICIE Input Capture Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the
ICF1 or ICF2 bit of the SR register is set.
Bit 6 = OCIE Output Compare Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the
OCF1 or OCF2 bit of the SR register is set.
Bit 1 = IEDG1 Input Edge 1.
This bit determines which type of level transition
on the ICAP1 pin will trigger the capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
Bit 5 = TOIE Timer Overflow Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is enabled whenever the TOF
bit of the SR register is set.
Bit 0 = OLVL1 Output Level 1.
The OLVL1 bit is copied to the OCMP1 pin when-
ever a successful comparison occurs with the
OC1R register and the OC1E bit is set in the CR2
register.
65/125
ST72334J/N, ST72314J/N, ST72124J
16-BIT TIMER (Cont’d)
CONTROL REGISTER 2 (CR2)
Read/Write
Bit 4 = PWM Pulse Width Modulation.
0: PWM mode is not active.
1: PWM mode is active, the OCMP1 pin outputs a
programmable cyclic signal; the length of the
pulse depends on the value of OC1R register;
the period depends on the value of OC2R regis-
ter.
Reset Value: 0000 0000 (00h)
7
0
OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG
Bit 3, 2 = CC1-CC0 Clock Control.
Bit 7 = OC1E Output Compare 1 Pin Enable.
This bit is used only to output the signal from the
timer on the OCMP1 pin (OLV1 in Output Com-
pare mode, both OLV1 and OLV2 in PWM and
one-pulse mode). Whatever the value of the OC1E
bit, the Output Compare 1 function of the timer re-
mains active.
0: OCMP1 pin alternate function disabled (I/O pin
free for general-purpose I/O).
1: OCMP1 pin alternate function enabled.
The value of the timer clock depends on these bits:
Table 14. Clock Control Bits
Timer Clock
fCPU / 4
CC1
CC0
0
0
1
0
1
0
fCPU / 2
fCPU / 8
External Clock (where
available)
1
1
Bit 6 = OC2E Output Compare 2 Enable.
This bit is used only to output the signal from the
timer on the OCMP2 pin (OLV2 in Output Com-
pare mode). Whatever the value of the OC2E bit,
the Output Compare 2 function of the timer re-
mains active.
Bit 1 = IEDG2 Input Edge 2.
This bit determines which type of level transition
on the ICAP2 pin will trigger the capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
0: OCMP2 pin alternate function disabled (I/O pin
free for general-purpose I/O).
Bit 0 = EXEDG External Clock Edge.
1: OCMP2 pin alternate function enabled.
This bit determines which type of level transition
on the external clock pin EXTCLK will trigger the
free running counter.
0: A falling edge triggers the free running counter.
1: A rising edge triggers the free running counter.
Bit 5 = OPM One Pulse Mode.
0: One Pulse Mode is not active.
1: One Pulse Mode is active, the ICAP1 pin can be
used to trigger one pulse on the OCMP1 pin; the
active transition is given by the IEDG1 bit. The
length of the generated pulse depends on the
contents of the OC1R register.
66/125
ST72334J/N, ST72314J/N, ST72124J
16-BIT TIMER (Cont’d)
STATUS REGISTER (SR)
Read Only
Bit 2-0 = Reserved, forced by hardware to 0.
INPUT CAPTURE 1 HIGH REGISTER (IC1HR)
Reset Value: 0000 0000 (00h)
The three least significant bits are not used.
7
Read Only
Reset Value: Undefined
This is an 8-bit read only register that contains the
high part of the counter value (transferred by the
input capture 1 event).
0
0
ICF1 OCF1 TOF ICF2 OCF2
0
0
7
0
Bit 7 = ICF1 Input Capture Flag 1.
0: No input capture (reset value).
MSB
LSB
1: An input capture has occurred or the counter
has reached the OC2R value in PWM mode. To
clear this bit, first read the SR register, then read
or write the low byte of the IC1R (IC1LR) regis-
ter.
INPUT CAPTURE 1 LOW REGISTER (IC1LR)
Read Only
Reset Value: Undefined
Bit 6 = OCF1 Output Compare Flag 1.
0: No match (reset value).
1: The content of the free running counter has
matched the content of the OC1R register. To
clear this bit, first read the SR register, then read
or write the low byte of the OC1R (OC1LR) reg-
ister.
This is an 8-bit read only register that contains the
low part of the counter value (transferred by the in-
put capture 1 event).
7
0
MSB
LSB
Bit 5 = TOF Timer Overflow.
OUTPUT COMPARE
(OC1HR)
1
HIGH REGISTER
0: No timer overflow (reset value).
1: The free running counter rolled over from FFFFh
to 0000h. To clear this bit, first read the SR reg-
ister, then read or write the low byte of the CR
(CLR) register.
Read/Write
Reset Value: 1000 0000 (80h)
This is an 8-bit register that contains the high part
of the value to be compared to the CHR register.
Note: Reading or writing the ACLR register does
not clear TOF.
7
0
Bit 4 = ICF2 Input Capture Flag 2.
MSB
LSB
0: No input capture (reset value).
1: An input capture has occurred.To clear this bit,
first read the SR register, then read or write the
low byte of the IC2R (IC2LR) register.
OUTPUT COMPARE
(OC1LR)
1
LOW REGISTER
Bit 3 = OCF2 Output Compare Flag 2.
0: No match (reset value).
1: The content of the free running counter has
matched the content of the OC2R register. To
clear this bit, first read the SR register, then read
or write the low byte of the OC2R (OC2LR) reg-
ister.
Read/Write
Reset Value: 0000 0000 (00h)
This is an 8-bit register that contains the low part of
the value to be compared to the CLR register.
7
0
MSB
LSB
67/125
ST72334J/N, ST72314J/N, ST72124J
16-BIT TIMER (Cont’d)
OUTPUT COMPARE
(OC2HR)
2
HIGH REGISTER
ALTERNATE COUNTER HIGH REGISTER
(ACHR)
Read/Write
Reset Value: 1000 0000 (80h)
Read Only
Reset Value: 1111 1111 (FFh)
This is an 8-bit register that contains the high part
of the value to be compared to the CHR register.
This is an 8-bit register that contains the high part
of the counter value.
7
0
7
0
MSB
LSB
MSB
LSB
OUTPUT COMPARE
(OC2LR)
2
LOW REGISTER
ALTERNATE COUNTER LOW REGISTER
(ACLR)
Read/Write
Reset Value: 0000 0000 (00h)
Read Only
Reset Value: 1111 1100 (FCh)
This is an 8-bit register that contains the low part of
the value to be compared to the CLR register.
This is an 8-bit register that contains the low part of
the counter value. A write to this register resets the
counter. An access to this register after an access
to SR register does not clear the TOF bit in SR
register.
7
0
MSB
LSB
7
0
COUNTER HIGH REGISTER (CHR)
MSB
LSB
Read Only
Reset Value: 1111 1111 (FFh)
INPUT CAPTURE 2 HIGH REGISTER (IC2HR)
This is an 8-bit register that contains the high part
of the counter value.
Read Only
Reset Value: Undefined
7
0
This is an 8-bit read only register that contains the
high part of the counter value (transferred by the
Input Capture 2 event).
MSB
LSB
7
0
MSB
LSB
COUNTER LOW REGISTER (CLR)
Read Only
Reset Value: 1111 1100 (FCh)
This is an 8-bit register that contains the low part of
the counter value. A write to this register resets the
counter. An access to this register after accessing
the SR register clears the TOF bit.
INPUT CAPTURE 2 LOW REGISTER (IC2LR)
Read Only
Reset Value: Undefined
This is an 8-bit read only register that contains the
low part of the counter value (transferred by the In-
put Capture 2 event).
7
0
MSB
LSB
7
0
MSB
LSB
68/125
ST72334J/N, ST72314J/N, ST72124J
16-BIT TIMER (Cont’d)
Table 15. 16-Bit Timer Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
Timer A: 32 CR1
ICIE
0
OCIE
0
TOIE
0
FOLV2
0
FOLV1
0
OLVL2
0
IEDG1
0
OLVL1
0
Timer B: 42 Reset Value
Timer A: 31 CR2
OC1E
0
OC2E
0
OPM
0
PWM
0
CC1
0
CC0
0
IEDG2
0
EXEDG
0
Timer B: 41 Reset Value
Timer A: 33 SR
ICF1
0
OCF1
0
TOF
0
ICF2
0
OCF2
0
-
-
-
Timer B: 43 Reset Value
0
0
0
Timer A: 34 ICHR1
MSB
-
LSB
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Timer B: 44 Reset Value
Timer A: 35 ICLR1
MSB
-
LSB
-
Timer B: 45 Reset Value
Timer A: 36 OCHR1
MSB
-
LSB
-
Timer B: 46 Reset Value
Timer A: 37 OCLR1
MSB
-
LSB
-
Timer B: 47 Reset Value
Timer A: 3E OCHR2
MSB
-
LSB
-
Timer B: 4E Reset Value
Timer A: 3F OCLR2
MSB
-
LSB
-
Timer B: 4F Reset Value
Timer A: 38 CHR
MSB
1
LSB
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
Timer B: 48 Reset Value
Timer A: 39 CLR
MSB
1
LSB
0
Timer B: 49 Reset Value
Timer A: 3A ACHR
MSB
1
LSB
1
Timer B: 4A Reset Value
Timer A: 3B ACLR
MSB
1
LSB
0
1
-
1
-
1
-
1
-
1
-
0
-
Timer B: 4B Reset Value
Timer A: 3C ICHR2
MSB
-
LSB
-
Timer B: 4C Reset Value
Timer A: 3D ICLR2
MSB
-
LSB
-
-
-
-
-
-
-
Timer B: 4D Reset Value
69/125
ST72334J/N, ST72314J/N, ST72124J
6.5 SERIAL PERIPHERAL INTERFACE (SPI)
6.5.1 Introduction
6.5.3 General description
The Serial Peripheral Interface (SPI) allows full-
duplex, synchronous, serial communication with
external devices. An SPI system may consist of a
master and one or more slaves or a system in
which devices may be either masters or slaves.
The SPI is connected to external devices through
4 alternate pins:
– MISO: Master In Slave Out pin
– MOSI: Master Out Slave In pin
– SCK: Serial Clock pin
The SPI is normally used for communication be-
tween the microcontroller and external peripherals
or another microcontroller.
– SS: Slave select pin
Refer to the Pin Description chapter for the device-
specific pin-out.
A basic example of interconnections between a
single master and a single slave is illustrated on
Figure 46.
6.5.2 Main Features
The MOSI pins are connected together as are
MISO pins. In this way data is transferred serially
between master and slave (most significant bit
first).
■ Full duplex, three-wire synchronous transfers
■ Master or slave operation
■ Four master mode frequencies
■ Maximum slave mode frequency = fCPU/2.
■ Four programmable master bit rates
■ Programmable clock polarity and phase
■ End of transfer interrupt flag
When the master device transmits data to a slave
device via MOSI pin, the slave device responds by
sending data to the master device via the MISO
pin. This implies full duplex transmission with both
data out and data in synchronized with the same
clock signal (which is provided by the master de-
vice via the SCK pin).
■ Write collision flag protection
■ Master mode fault protection capability.
Thus, the byte transmitted is replaced by the byte
received and eliminates the need for separate
transmit-empty and receiver-full bits. A status flag
is used to indicate that the I/O operation is com-
plete.
Four possible data/clock timing relationships may
be chosen (see Figure 49) but master and slave
must be programmed with the same timing mode.
Figure 46. Serial Peripheral Interface Master/Slave
MASTER
SLAVE
MSBit
LSBit
MSBit
LSBit
MISO
MOSI
MISO
MOSI
8-BIT SHIFT REGISTER
8-BIT SHIFT REGISTER
SPI
CLOCK
GENERATOR
SCK
SS
SCK
SS
+5V
70/125
ST72334J/N, ST72314J/N, ST72124J
SERIAL PERIPHERAL INTERFACE (Cont’d)
Figure 47. Serial Peripheral Interface Block Diagram
Internal Bus
Read
DR
IT
Read Buffer
request
MOSI
SR
MISO
8-Bit Shift Register
Write
MODF
WCOL
SPIF
-
-
-
-
-
SPI
STATE
CONTROL
SCK
SS
CR
SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0
MASTER
CONTROL
SERIAL
CLOCK
GENERATOR
71/125
ST72334J/N, ST72314J/N, ST72124J
SERIAL PERIPHERAL INTERFACE (Cont’d)
6.5.4 Functional Description
In this configuration the MOSI pin is a data output
and to the MISO pin is a data input.
Figure 46 shows the serial peripheral interface
(SPI) block diagram.
This interface contains 3 dedicated registers:
– A Control Register (CR)
Transmit sequence
The transmit sequence begins when a byte is writ-
ten the DR register.
– A Status Register (SR)
The data byte is parallel loaded into the 8-bit shift
register (from the internal bus) during a write cycle
and then shifted out serially to the MOSI pin most
significant bit first.
– A Data Register (DR)
Refer to the CR, SR and DR registers in Section
6.5.7for the bit definitions.
6.5.4.1 Master Configuration
When data transfer is complete:
– The SPIF bit is set by hardware
In a master configuration, the serial clock is gener-
ated on the SCK pin.
– An interrupt is generated if the SPIE bit is set
and the I bit in the CCR register is cleared.
Procedure
– Select the SPR0 & SPR1 bits to define the se-
rial clock baud rate (see CR register).
During the last clock cycle the SPIF bit is set, a
copy of the data byte received in the shift register
is moved to a buffer. When the DR register is read,
the SPI peripheral returns this buffered value.
– Select the CPOL and CPHA bits to define one
of the four relationships between the data
transfer and the serial clock (see Figure 49).
Clearing the SPIF bit is performed by the following
software sequence:
– The SS pin must be connected to a high level
signal during the complete byte transmit se-
quence.
1. An access to the SR register while the SPIF bit
is set
– The MSTR and SPE bits must be set (they re-
main set only if the SS pin is connected to a
high level signal).
2. A write or a read of the DR register.
Note: While the SPIF bit is set, all writes to the DR
register are inhibited until the SR register is read.
72/125
ST72334J/N, ST72314J/N, ST72124J
SERIAL PERIPHERAL INTERFACE (Cont’d)
6.5.4.2 Slave Configuration
When data transfer is complete:
– The SPIF bit is set by hardware
In slave configuration, the serial clock is received
on the SCK pin from the master device.
– An interrupt is generated if SPIE bit is set and
I bit in CCR register is cleared.
The value of the SPR0 & SPR1 bits is not used for
the data transfer.
During the last clock cycle the SPIF bit is set, a
copy of the data byte received in the shift register
is moved to a buffer. When the DR register is read,
the SPI peripheral returns this buffered value.
Procedure
– For correct data transfer, the slave device
must be in the same timing mode as the mas-
ter device (CPOL and CPHA bits). See Figure
49.
Clearing the SPIF bit is performed by the following
software sequence:
1. An access to the SR register while the SPIF bit
is set.
– The SS pin must be connected to a low level
signal during the complete byte transmit se-
quence.
2. A write or a read of the DR register.
– Clear the MSTR bit and set the SPE bit to as-
sign the pins to alternate function.
Notes: While the SPIF bit is set, all writes to the
DR register are inhibited until the SR register is
read.
In this configuration the MOSI pin is a data input
and the MISO pin is a data output.
The SPIF bit can be cleared during a second
transmission; however, it must be cleared before
the second SPIF bit in order to prevent an overrun
condition (see Section 6.5.4.6).
Transmit Sequence
The data byte is parallel loaded into the 8-bit shift
register (from the internal bus) during a write cycle
and then shifted out serially to the MISO pin most
significant bit first.
Depending on the CPHA bit, the SS pin has to be
set to write to the DR register between each data
byte transfer to avoid a write collision (see Section
6.5.4.4).
The transmit sequence begins when the slave de-
vice receives the clock signal and the most signifi-
cant bit of the data on its MOSI pin.
73/125
ST72334J/N, ST72314J/N, ST72124J
SERIAL PERIPHERAL INTERFACE (Cont’d)
6.5.4.3 Data Transfer Format
The master device applies data to its MOSI pin-
clock edge before the capture clock edge.
During an SPI transfer, data is simultaneously
transmitted (shifted out serially) and received
(shifted in serially). The serial clock is used to syn-
chronize the data transfer during a sequence of
eight clock pulses.
CPHA bit is set
The second edge on the SCK pin (falling edge if
the CPOL bit is reset, rising edge if the CPOL bit is
set) is the MSBit capture strobe. Data is latched on
the occurrence of the first clock transition.
The SS pin allows individual selection of a slave
device; the other slave devices that are not select-
ed do not interfere with the SPI transfer.
No write collision should occur even if the SS pin
stays low during a transfer of several bytes (see
Figure 48).
Clock Phase and Clock Polarity
Four possible timing relationships may be chosen
by software, using the CPOL and CPHA bits.
CPHA bit is reset
The CPOL (clock polarity) bit controls the steady
state value of the clock when no data is being
transferred. This bit affects both master and slave
modes.
The first edge on the SCK pin (falling edge if CPOL
bit is set, rising edge if CPOL bit is reset) is the
MSBit capture strobe. Data is latched on the oc-
currence of the second clock transition.
The combination between the CPOL and CPHA
(clock phase) bits selects the data capture clock
edge.
This pin must be toggled high and low between
each byte transmitted (see Figure 48).
To protect the transmission from a write collision a
low value on the SS pin of a slave device freezes
the data in its DR register and does not allow it to
be altered. Therefore the SS pin must be high to
write a new data byte in the DR without producing
a write collision.
Figure 49, shows an SPI transfer with the four
combinations of the CPHA and CPOL bits. The di-
agram may be interpreted as a master or slave
timing diagram where the SCK pin, the MISO pin,
the MOSI pin are directly connected between the
master and the slave device.
The SS pin is the slave device select input and can
be driven by the master device.
Figure 48. CPHA / SS Timing Diagram
Byte 3
Byte 2
MOSI/MISO
Master SS
Byte 1
Slave SS
(CPHA=0)
Slave SS
(CPHA=1)
VR02131A
74/125
ST72334J/N, ST72314J/N, ST72124J
SERIAL PERIPHERAL INTERFACE (Cont’d)
Figure 49. Data Clock Timing Diagram
CPHA =1
CPOL = 1
CPOL = 0
Bit 4
Bit 4
Bit3
Bit3
Bit 2
Bit 2
Bit 1
Bit 1
LSBit
LSBit
MSBit
MSBit
Bit 6
Bit 6
Bit 5
Bit 5
MISO
(from master)
MOSI
(from slave)
SS
(to slave)
CAPTURE STROBE
CPHA =0
CPOL = 1
CPOL = 0
Bit 4
Bit 4
Bit3
Bit 2
Bit 2
Bit 1
Bit 1
LSBit
LSBit
MSBit
Bit 6
Bit 6
Bit 5
Bit 5
MISO
(from master)
MSBit
Bit3
MOSI
(from slave)
SS
(to slave)
CAPTURE STROBE
Note: This figure should not be used as a replacement for parametric information.
Refer to the Electrical Characteristics chapter.
VR02131B
75/125
ST72334J/N, ST72314J/N, ST72124J
SERIAL PERIPHERAL INTERFACE (Cont’d)
6.5.4.4 Write Collision Error
When the CPHA bit is reset:
A write collision occurs when the software tries to
write to the DR register while a data transfer is tak-
ing place with an external device. When this hap-
pens, the transfer continues uninterrupted; and
the software write will be unsuccessful.
Data is latched on the occurrence of the first clock
transition. The slave device does not have any
way of knowing when that transition will occur;
therefore, the slave device collision occurs when
software attempts to write the DR register after its
SS pin has been pulled low.
Write collisions can occur both in master and slave
mode.
For this reason, the SS pin must be high, between
each data byte transfer, to allow the CPU to write
in the DR register without generating a write colli-
sion.
Note: a ”read collision” will never occur since the
received data byte is placed in a buffer in which
access is always synchronous with the MCU oper-
ation.
In Slave mode
In Master mode
When the CPHA bit is set:
Collision in the master device is defined as a write
of the DR register while the internal serial clock
(SCK) is in the process of transfer.
The slave device will receive a clock (SCK) edge
prior to the latch of the first data transfer. This first
clock edge will freeze the data in the slave device
DR register and output the MSBit on to the exter-
nal MISO pin of the slave device.
The SS pin signal must be always high on the
master device.
The SS pin low state enables the slave device but
the output of the MSBit onto the MISO pin does
not take place until the first data transfer clock
edge.
WCOL bit
The WCOL bit in the SR register is set if a write
collision occurs.
No SPI interrupt is generated when the WCOL bit
is set (the WCOL bit is a status flag only).
Clearing the WCOL bit is done through a software
sequence (see Figure 50).
Figure 50. Clearing the WCOL bit (Write Collision Flag) Software Sequence
Clearing sequence after SPIF = 1 (end of a data byte transfer)
Read SR
Read SR
1st Step
2nd Step
OR
THEN
THEN
SPIF =0
WCOL=0
SPIF =0
WCOL=0 if no transfer has started
WCOL=1 if a transfer has started
before the 2nd step
Read DR
Write DR
Clearing sequence before SPIF = 1 (during a data byte transfer)
Read SR
1st Step
THEN
Note: Writing in DR register in-
2nd Step
Read DR
stead of reading in it do not reset
WCOL bit
WCOL=0
76/125
ST72334J/N, ST72314J/N, ST72124J
SERIAL PERIPHERAL INTERFACE (Cont’d)
6.5.4.5 Master Mode Fault
may be restored to their original state during or af-
ter this clearing sequence.
Master mode fault occurs when the master device
has its SS pin pulled low, then the MODF bit is set.
Hardware does not allow the user to set the SPE
and MSTR bits while the MODF bit is set except in
the MODF bit clearing sequence.
Master mode fault affects the SPI peripheral in the
following ways:
In a slave device the MODF bit can not be set, but
in a multi master configuration the device can be in
slave mode with this MODF bit set.
– The MODF bit is set and an SPI interrupt is
generated if the SPIE bit is set.
– The SPE bit is reset. This blocks all output
from the device and disables the SPI periph-
eral.
The MODF bit indicates that there might have
been a multi-master conflict for system control and
allows a proper exit from system operation to a re-
set or default system state using an interrupt rou-
tine.
– The MSTR bit is reset, thus forcing the device
into slave mode.
Clearing the MODF bit is done through a software
sequence:
6.5.4.6 Overrun Condition
An overrun condition occurs, when the master de-
vice has sent several data bytes and the slave de-
vice has not cleared the SPIF bit issuing from the
previous data byte transmitted.
1. A read or write access to the SR register while
the MODF bit is set.
2. A write to the CR register.
In this case, the receiver buffer contains the byte
sent after the SPIF bit was last cleared. A read to
the DR register returns this byte. All other bytes
are lost.
Notes: To avoid any multiple slave conflicts in the
case of a system comprising several MCUs, the
SS pin must be pulled high during the clearing se-
quence of the MODF bit. The SPE and MSTR bits
This condition is not detected by the SPI peripher-
al.
77/125
ST72334J/N, ST72314J/N, ST72124J
SERIAL PERIPHERAL INTERFACE (Cont’d)
6.5.4.7 Single Master and Multimaster Configurations
There are two types of SPI systems:
– Single Master System
For more security, the slave device may respond
to the master with the received data byte. Then the
master will receive the previous byte back from the
slave device if all MISO and MOSI pins are con-
nected and the slave has not written its DR regis-
ter.
– Multimaster System
Single Master System
Other transmission security methods can use
ports for handshake lines or data bytes with com-
mand fields.
A typical single master system may be configured,
using an MCU as the master and four MCUs as
slaves (see Figure 51).
Multi-master System
The master device selects the individual slave de-
vices by using four pins of a parallel port to control
the four SS pins of the slave devices.
A multi-master system may also be configured by
the user. Transfer of master control could be im-
plemented using a handshake method through the
I/O ports or by an exchange of code messages
through the serial peripheral interface system.
The SS pins are pulled high during reset since the
master device ports will be forced to be inputs at
that time, thus disabling the slave devices.
The multi-master system is principally handled by
the MSTR bit in the CR register and the MODF bit
in the SR register.
Note: To prevent a bus conflict on the MISO line
the master allows only one slave device during a
transmission.
Figure 51. Single Master Configuration
SS
SS
SS
SS
SCK
SCK
Slave
SCK
Slave
SCK
Slave
MCU
Slave
MCU
MCU
MCU
MOSI MISO
MOSI MISO
MOSI MISO
MOSI MISO
MOSI MISO
SCK
Master
MCU
5V
SS
78/125
ST72334J/N, ST72314J/N, ST72124J
SERIAL PERIPHERAL INTERFACE (Cont’d)
6.5.5 Low Power Modes
Mode
Description
No effect on SPI.
WAIT
SPI interrupt events cause the device to exit from WAIT mode.
SPI registers are frozen.
HALT
In HALT mode, the SPI is inactive. SPI operation resumes when the MCU is woken up by an interrupt with
“exit from HALT mode” capability.
6.5.6 Interrupts
Enable
Control from
Bit
Exit
Exit
from
Halt
Event
Flag
Interrupt Event
Wait
Yes
Yes
SPI End of Transfer Event
Master Mode Fault Event
SPIF
No
No
SPIE
MODF
Note: The SPI interrupt events are connected to
the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding
Enable Control Bit is set and the I-bit in the CC reg-
ister is reset (RIM instruction).
79/125
ST72334J/N, ST72314J/N, ST72124J
SERIAL PERIPHERAL INTERFACE (Cont’d)
6.5.7 Register Description
CONTROL REGISTER (CR)
Read/Write
Bit 3 = CPOL Clock polarity.
This bit is set and cleared by software. This bit de-
termines the steady state of the serial Clock. The
CPOL bit affects both the master and slave
modes.
0: The steady state is a low value at the SCK pin.
1: The steady state is a high value at the SCK pin.
Reset Value: 0000xxxx (0xh)
7
0
SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0
Bit 7 = SPIE Serial peripheral interrupt enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SPI interrupt is generated whenever SPIF=1
or MODF=1 in the SR register
Bit 2 = CPHA Clock phase.
This bit is set and cleared by software.
0: The first clock transition is the first data capture
edge.
1: The second clock transition is the first capture
edge.
Bit 6 = SPE Serial peripheral output enable.
This bit is set and cleared by software. It is also
cleared by hardware when, in master mode, SS=0
(see Section 6.5.4.5 Master Mode Fault).
0: I/O port connected to pins
Bit 1:0 = SPR[1:0] Serial peripheral rate.
These bits are set and cleared by software.Used
with the SPR2 bit, they select one of six baud rates
to be used as the serial clock when the device is a
master.
1: SPI alternate functions connected to pins
The SPE bit is cleared by reset, so the SPI periph-
eral is not initially connected to the external pins.
These 2 bits have no effect in slave mode.
Table 16. Serial Peripheral Baud Rate
Bit 5 = SPR2 Divider Enable.
Serial Clock
SPR2 SPR1 SPR0
this bit is set and cleared by software and it is
cleared by reset. It is used with the SPR[1:0] bits to
set the baud rate. Refer to Table 16.
0: Divider by 2 enabled
f
f
/2
/8
1
0
0
1
0
0
0
0
0
1
1
1
0
0
1
0
0
1
CPU
CPU
f
f
f
/16
/32
/64
CPU
CPU
CPU
1: Divider by 2 disabled
Bit 4 = MSTR Master.
f
/128
CPU
This bit is set and cleared by software. It is also
cleared by hardware when, in master mode, SS=0
(see Section 6.5.4.5 Master Mode Fault).
0: Slave mode is selected
1: Master mode is selected, the function of the
SCK pin changes from an input to an output and
the functions of the MISO and MOSI pins are re-
versed.
80/125
ST72334J/N, ST72314J/N, ST72124J
SERIAL PERIPHERAL INTERFACE (Cont’d)
STATUS REGISTER (SR)
Read Only
DATA I/O REGISTER (DR)
Read/Write
Reset Value: 0000 0000 (00h)
Reset Value: Undefined
7
0
-
7
0
SPIF
WCOL
-
MODF
-
-
-
D7
D6
D5
D4
D3
D2
D1
D0
Bit 7 = SPIF Serial Peripheral data transfer flag.
This bit is set by hardware when a transfer has
been completed. An interrupt is generated if
SPIE=1 in the CR register. It is cleared by a soft-
ware sequence (an access to the SR register fol-
lowed by a read or write to the DR register).
0: Data transfer is in progress or has been ap-
proved by a clearing sequence.
The DR register is used to transmit and receive
data on the serial bus. In the master device only a
write to this register will initiate transmission/re-
ception of another byte.
Notes: During the last clock cycle the SPIF bit is
set, a copy of the received data byte in the shift
register is moved to a buffer. When the user reads
the serial peripheral data I/O register, the buffer is
actually being read.
1: Data transfer between the device and an exter-
nal device has been completed.
Warning:
Note: While the SPIF bit is set, all writes to the DR
register are inhibited.
A write to the DR register places data directly into
the shift register for transmission.
A write to the the DR register returns the value lo-
cated in the buffer and not the contents of the shift
register (See Figure 47 ).
Bit 6 = WCOL Write Collision status.
This bit is set by hardware when a write to the DR
register is done during a transmit sequence. It is
cleared by a software sequence (see Figure 50).
0: No write collision occurred
1: A write collision has been detected
Bit 5 = Unused.
Bit 4 = MODF Mode Fault flag.
This bit is set by hardware when the SS pin is
pulled low in master mode (see Section 6.5.4.5
Master Mode Fault). An SPI interrupt can be gen-
erated if SPIE=1 in the CR register. This bit is
cleared by a software sequence (An access to the
SR register while MODF=1 followed by a write to
the CR register).
0: No master mode fault detected
1: A fault in master mode has been detected
Bits 3-0 = Unused.
81/125
ST72334J/N, ST72314J/N, ST72124J
SERIAL PERIPHERAL INTERFACE (Cont’d)
Table 17. SPI Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
SPIDR
Reset Value
MSB
x
LSB
x
0021h
0022h
0023h
x
x
x
x
x
x
SPICR
Reset Value
SPIE
0
SPE
0
SPR2
0
MSTR
0
CPOL
x
CPHA
x
SPR1
x
SPR0
x
SPISR
Reset Value
SPIF
0
WCOL
0
MODF
0
0
0
0
0
0
82/125
ST72334J/N, ST72314J/N, ST72124J
6.6.3 General Description
6.6 SERIAL COMMUNICATIONS INTERFACE (SCI)
6.6.1 Introduction
The Serial Communications Interface (SCI) offers
a flexible means of full-duplex data exchange with
external equipment requiring an industry standard
NRZ asynchronous serial data format. The SCI of-
fers a very wide range of baud rates using two
baud rate generator systems.
The interface is externally connected to another
device by two pins (see Figure 53):
– TDO: Transmit Data Output. When the transmit-
ter is disabled, the output pin returns to its I/O
port configuration. When the transmitter is ena-
bled and nothing is to be transmitted, the TDO
pin is at high level.
6.6.2 Main Features
■ Full duplex, asynchronous communications
■ NRZ standard format (Mark/Space)
■ Dual baud rate generator systems
■ Independently programmable transmit and
receive baud rates up to 250K baud.
■ Programmable data word length (8 or 9 bits)
– RDI: Receive Data Input is the serial data input.
Oversampling techniques are used for data re-
covery by discriminating between valid incoming
data and noise.
Through this pins, serial data is transmitted and re-
ceived as frames comprising:
– An Idle Line prior to transmission or reception
– A start bit
■ Receive buffer full, Transmit buffer empty and
End of Transmission flags
– A data word (8 or 9 bits) least significant bit first
– A Stop bit indicating that the frame is complete.
This interface usestwo typesofbaud rategenerator:
■ Two receiver wake-up modes:
– Address bit (MSB)
– Idle line
■ Muting functionfor multiprocessor configurations
■ Separate enable bits for Transmitter and
– A conventional type for commonly-used baud
rates,
Receiver
– An extended type with a prescaler offering a very
wide range of baud rates even with non-standard
oscillator frequencies.
■ Three error detection flags:
– Overrun error
– Noise error
– Frame error
■ Five interrupt sources with flags:
– Transmit data register empty
– Transmission complete
– Receive data register full
– Idle line received
– Overrun error detected
83/125
ST72334J/N, ST72314J/N, ST72124J
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
Figure 52. SCI Block Diagram
Write
Read
(DATA REGISTER) DR
Received Data Register (RDR)
Received Shift Register
Transmit Data Register (TDR)
TDO
Transmit Shift Register
RDI
CR1
R8
-
-
T8
M
WAKE
-
-
WAKE
UP
TRANSMIT
RECEIVER
CLOCK
RECEIVER
CONTROL
CONTROL
UNIT
SR
CR2
TIE TCIE RIE ILIE TE RE RWU SBK
TDRE TC RDRF
IDLE OR NF FE
-
SCI
INTERRUPT
CONTROL
TRANSMITTER
CLOCK
TRANSMITTER RATE
CONTROL
f
CPU
/2
/PR
/16
BRR
SCP1SCP0SCT2 SCT1 SCT0SCR2SCR1SCR0
RECEIVER RATE
CONTROL
CONVENTIONAL BAUD RATE GENERATOR
84/125
ST72334J/N, ST72314J/N, ST72124J
6.6.4.1 Serial Data Format
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
6.6.4 Functional Description
The block diagram of the Serial Control Interface,
is shown in Figure 52. It contains 6 dedicated reg-
isters:
Word length may be selected as being either 8 or 9
bits by programming the M bit in the CR1 register
(see Figure 52).
– Two control registers (CR1 & CR2)
– A status register (SR)
The TDO pin is in low state during the start bit.
The TDO pin is in high state during the stop bit.
– A baud rate register (BRR)
An Idle character is interpreted as an entire frame
of “1”s followed by the start bit of the next frame
which contains data.
– An extended prescaler receiver register (ERPR)
– Anextendedprescalertransmitter register(ETPR)
A Break character is interpreted on receiving “0”s
for some multiple of the frame period. At the end of
the last break frame the transmitter inserts an ex-
tra “1” bit to acknowledge the start bit.
Refer to the register descriptions in Section
6.6.7for the definitions of each bit.
Transmission and reception are driven by their
own baud rate generator.
Figure 53. Word length programming
9-bit Word length (M bit is set)
Possible
Next Data Frame
Parity
Data Frame
Start
Bit
Next
Start
Bit
Stop
Bit
Bit2
Bit0
Bit1
Bit3
Bit4 Bit5
Bit6
Bit7 Bit8
Bit
Start
Bit
Idle Frame
Start
Bit
Extra
’1’
Break Frame
8-bit Word length (M bit is reset)
Possible
Parity
Next Data Frame
Data Frame
Start
Bit
Next
Start
Bit
Stop
Bit
Bit2
Bit5
Bit6
Bit0
Bit1
Bit3
Bit4
Bit7
Bit
Start
Bit
Idle Frame
Start
Bit
Extra
’1’
Break Frame
85/125
ST72334J/N, ST72314J/N, ST72124J
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
6.6.4.2 Transmitter
When a frame transmission is complete (after the
stop bit or after the break frame) the TC bit is set
and an interrupt is generated if the TCIE is set and
the I bit is cleared in the CCR register.
The transmitter can send data words of either 8 or
9 bits depending on the M bit status. When the M
bit is set, word length is 9 bits and the 9th bit (the
MSB) has to be stored in the T8 bit in the CR1 reg-
ister.
Clearing the TC bit is performed by the following
software sequence:
1. An access to the SR register
2. A write to the DR register
Character Transmission
During an SCI transmission, data shifts out least
significant bit first on the TDO pin. In this mode,
the DR register consists of a buffer (TDR) between
the internal bus and the transmit shift register (see
Figure 52).
Note: The TDRE and TC bits are cleared by the
same software sequence.
Break Characters
Setting the SBK bit loads the shift register with a
break character. The break frame length depends
on the M bit (see Figure 53).
Procedure
– Select the M bit to define the word length.
As long as the SBK bit is set, the SCI send break
frames to the TDO pin. After clearing this bit by
software the SCI insert a logic 1 bit at the end of
the last break frame to guarantee the recognition
of the start bit of the next frame.
– Select the desired baud rate using the BRR and
the ETPR registers.
– Set the TE bit to assign the TDO pin to the alter-
nate function and to send a idle frame as first
transmission.
Idle Characters
– Access the SR register and write the data to
send in the DR register (this sequence clears the
TDRE bit).Repeat this sequence for each data to
be transmitted.
Setting the TE bit drives the SCI to send an idle
frame before the first data frame.
Clearing and then setting the TE bit during a trans-
mission sends an idle frame after the current word.
Clearing the TDRE bit is always performed by the
following software sequence:
1. An access to the SR register
Note: Resetting and setting the TE bit causes the
data in the TDR register to be lost. Therefore the
best time to toggle the TE bit is when the TDRE bit
is set i.e. before writing the next byte in the DR.
2. A write to the DR register
The TDRE bit is set by hardware and it indicates:
– The TDR register is empty.
– The data transfer is beginning.
– The next data can be written in the DR register
without overwriting the previous data.
This flag generates an interrupt if the TIE bit is set
and the I bit is cleared in the CCR register.
When a transmission is taking place, a write in-
struction to the DR register stores the data in the
TDR register and which is copied in the shift regis-
ter at the end of the current transmission.
When no transmission is taking place, a write in-
struction to the DR register places the data directly
in the shift register, the data transmission starts,
and the TDRE bit is immediately set.
86/125
ST72334J/N, ST72314J/N, ST72124J
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
6.6.4.3 Receiver
Overrun Error
The SCI can receive data words of either 8 or 9
bits. When the M bit is set, word length is 9 bits
and the MSB is stored in the R8 bit in the CR1 reg-
ister.
An overrun error occurs when a character is re-
ceived when RDRF has not been reset. Data can
not be transferred from the shift register to the
TDR register as long as the RDRF bit is not
cleared.
Character reception
When a overrun error occurs:
– The OR bit is set.
During a SCI reception, data shifts in least signifi-
cant bit first through the RDI pin. In this mode, DR
register consists in a buffer (RDR) between the in-
ternal bus and the received shift register (see Fig-
ure 52).
– The RDR content will not be lost.
– The shift register will be overwritten.
– An interrupt is generated if the RIE bit is set and
the I bit is cleared in the CCR register.
Procedure
– Select the M bit to define the word length.
The OR bit is reset by an access to the SR register
followed by a DR register read operation.
– Select the desired baud rate using the BRR and
the ERPR registers.
Noise Error
– Set the RE bit, this enables the receiver which
begins searching for a start bit.
Oversampling techniques are used for data recov-
ery by discriminating between valid incoming data
and noise.
When a character is received:
– The RDRF bit is set. It indicates that the content
of the shift register is transferred to the RDR.
When noise is detected in a frame:
– The NF is set at the rising edge of the RDRF bit.
– An interrupt is generated if the RIE bit is set and
the I bit is cleared in the CCR register.
– Data is transferred from the Shift register to the
DR register.
– The error flags can be set if a frame error, noise
or an overrun error has been detected during re-
ception.
– No interrupt is generated. However this bit rises
at the same time as the RDRF bit which itself
generates an interrupt.
Clearing theRDRF bit isperformed by the following
software sequence done by:
The NF bit is reset by a SR register read operation
followed by a DR register read operation.
1. An access to the SR register
2. A read to the DR register.
Framing Error
A framing error is detected when:
The RDRF bit must be cleared before the endof the
reception of the next character to avoid an overrun
error.
– The stop bit is not recognized on reception at the
expected time, following either a de-synchroni-
zation or excessive noise.
Break Character
– A break is received.
When a break character is received, the SPI han-
dles it as a framing error.
When the framing error is detected:
– the FE bit is set by hardware
Idle Character
– Data is transferred from the Shift register to the
DR register.
When a idle frame is detected, there is the same
procedure as a data received character plus an in-
terrupt if the ILIE bit is set and the I bit is cleared in
the CCR register.
– No interrupt is generated. However this bit rises
at the same time as the RDRF bit which itself
generates an interrupt.
The FE bit is reset by a SR register read operation
followed by a DR register read operation.
87/125
ST72334J/N, ST72314J/N, ST72124J
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
Figure 54. SCI Baud Rate and Extended Prescaler Block Diagram
EXTENDED PRESCALER TRANSMITTER RATE CONTROL
ETPR
EXTENDED TRANSMITTER PRESCALER REGISTER
ERPR
EXTENDED RECEIVER PRESCALER REGISTER
EXTENDED PRESCALER RECEIVER RATE CONTROL
EXTENDED PRESCALER
f
TRANSMITTER
CLOCK
CPU
TRANSMITTER RATE
CONTROL
/2
/PR
/16
BRR
SCP1SCP0SCT2 SCT1 SCT0SCR2SCR1SCR0
RECEIVER
CLOCK
RECEIVER RATE
CONTROL
CONVENTIONAL BAUD RATE GENERATOR
88/125
ST72334J/N, ST72314J/N, ST72124J
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
6.6.4.4 Conventional Baud Rate Generation
than zero. The baud rates are calculated as fol-
lows:
The baud rate for the receiver and transmitter (Rx
and Tx) are set independently and calculated as
follows:
f
f
CPU
CPU
Rx =
Tx =
f
f
16 ERPR
16 ETPR
CPU
CPU
*
*
Rx =
(32 PR) RR
Tx =
(32 PR) TR
*
*
*
*
with:
with:
ETPR = 1,..,255 (see ETPR register)
PR = 1, 3, 4 or 13 (see SCP0 & SCP1 bits)
TR = 1, 2, 4, 8, 16, 32, 64,128
ERPR = 1,.. 255 (see ERPR register)
6.6.4.6 Receiver Muting and Wake-up Feature
(see SCT0, SCT1 & SCT2 bits)
RR = 1, 2, 4, 8, 16, 32, 64,128
In multiprocessor configurations it is often desira-
ble that only the intended message recipient
should actively receive the full message contents,
thus reducing redundant SCI service overhead for
all non addressed receivers.
(see SCR0,SCR1 & SCR2 bits)
All this bits are in the BRR register.
Example: If f
PR=13 and TR=RR=1, the transmit and receive
baud rates are 19200 baud.
is 8 MHz (normal mode) and if
The non addressed devices may be placed in
sleep mode by means of the muting function.
CPU
Setting the RWU bit by software puts the SCI in
sleep mode:
Note: the baud rate registers MUST NOT be
changed while the transmitter or the receiver is en-
abled.
All the reception status bits can not be set.
All the receive interrupt are inhibited.
6.6.4.5 Extended Baud Rate Generation
A muted receiver may be awakened by one of the
following two ways:
The extended prescaler option gives a very fine
tuning onthe baud rate, using a 255 value prescal-
er, whereas the conventional Baud Rate Genera-
tor retains industry standard software compatibili-
ty.
– by Idle Line detection if the WAKE bit is reset,
– by Address Mark detection if the WAKE bit is set.
Receiver wakes-up by Idle Line detection when
the Receive line has recognised an Idle Frame.
Then the RWU bit is reset by hardware but the
IDLE bit is not set.
The extended baud rate generator block diagram
is described in the Figure 54.
The output clock rate sent to the transmitter or to
the receiver will be the output from the 16 divider
divided by a factor ranging from 1 to 255 set in the
ERPR or the ETPR register.
Receiver wakes-up by Address Mark detection
when it received a “1” as the most significant bit of
a word, thus indicating that the message is an ad-
dress. The reception of this particular word wakes
up the receiver, resets the RWU bit and sets the
RDRF bit, which allows the receiver to receive this
word normally and to use it as an address word.
Note: the extended prescaler is activated by set-
ting the ETPR or ERPR register to a value other
89/125
ST72334J/N, ST72314J/N, ST72124J
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
6.6.5 Low Power Modes
Mode
Description
No effect on SCI.
WAIT
SCI interrupts cause the device to exit from Wait mode.
SCI registers are frozen.
HALT
In Halt mode, the SCI stops transmitting/receiving until Halt mode is exited.
6.6.6 Interrupts
Enable
Control from
Bit
Exit
Exit
from
Halt
Event
Flag
Interrupt Event
Wait
Yes
Yes
Yes
Yes
Yes
Transmit Data Register Empty
Transmission Complete
TDRE
TC
TIE
No
No
No
No
No
TCIE
Received Data Ready to be Read
Overrrun Error Detected
Idle Line Detected
RDRF
OR
RIE
IDLE
ILIE
The SCI interrupt events are connected to the
same interrupt vector (see Interrupts chapter).
These events generate an interrupt if the corre-
sponding Enable Control Bit is set and the I-bit in
the CC register is reset (RIM instruction).
90/125
ST72334J/N, ST72314J/N, ST72124J
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
6.6.7 Register Description
STATUS REGISTER (SR)
Note: The IDLE bit will not be set again until the
RDRF bit has been set itself (i.e. a new idle line oc-
curs). This bit is not set by an idle line when the re-
ceiver wakes up from wake-up mode.
Read Only
Reset Value: 1100 0000 (C0h)
Bit 3 = OR Overrun error.
7
0
-
This bit is set by hardware when the word currently
being received in the shift register is ready to be
transferred into the RDR register while RDRF=1.
An interrupt is generated if RIE=1 in the CR2 reg-
ister. It is cleared by hardware when RE=0 by a
software sequence (an access to the SR register
followed by a read to the DR register).
0: No Overrun error
TDRE
TC
RDRF IDLE
OR
NF
FE
Bit 7 = TDRE Transmit data register empty.
This bit is set by hardware when the content of the
TDR register has been transferred into the shift
register. An interrupt is generated if the TIE =1 in
the CR2 register. It is cleared by a software se-
quence (an access to the SR register followed by a
write to the DR register).
1: Overrun error is detected
Note: When this bit is set RDR register content will
not be lost but the shift register will be overwritten.
0: Data is not transferred to the shift register
1: Data is transferred to the shift register
Bit 2 = NF Noise flag.
Note: data will not be transferred to the shift regis-
ter as long as the TDRE bit is not reset.
This bit is set by hardware when noise is detected
on a received frame. It is cleared by hardware
when RE=0 by a software sequence (an access to
the SR register followed by a read to the DR regis-
ter).
Bit 6 = TC Transmission complete.
This bit is set by hardware when transmission of a
frame containing Data, a Preamble or a Break is
complete. An interrupt is generated if TCIE=1 in
the CR2 register. It is cleared by a software se-
quence (an access to the SR register followed by a
write to the DR register).
0: No noise is detected
1: Noise is detected
Note: This bit does not generate interrupt as it ap-
pears at the same time as the RDRF bit which it-
self generates an interrupt.
0: Transmission is not complete
1: Transmission is complete
Bit 1 = FE Framing error.
This bit is set by hardware when a de-synchroniza-
tion, excessive noise or a break character is de-
tected. It is cleared by hardware when RE=0 by a
software sequence (an access to the SR register
followed by a read to the DR register).
Bit 5 = RDRF Received data ready flag.
This bit is set by hardware when the content of the
RDR register has been transferred into the DR
register. An interrupt is generated if RIE=1 in the
CR2 register. It is cleared by hardware when
RE=0 or by a software sequence (an access to the
SR register followed by a read to the DR register).
0: Data is not received
0: No Framing error is detected
1: Framing error or break character is detected
Note: This bit does not generate interrupt as it ap-
pears at the same time as the RDRF bit which it-
self generates an interrupt. If the word currently
being transferred causes both frame error and
overrun error, it will be transferred and only the OR
bit will be set.
1: Received data is ready to be read
Bit 4 = IDLE Idle line detect.
This bit is set by hardware when a Idle Line is de-
tected. An interrupt is generated if the ILIE=1 in
the CR2 register. It is cleared by hardware when
RE=0 by a software sequence (an access to the
SR register followed by a read to the DR register).
0: No Idle Line is detected
Bit 0 = Unused.
1: Idle Line is detected
91/125
ST72334J/N, ST72314J/N, ST72124J
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
CONTROL REGISTER 1 (CR1)
Read/Write
1: AnSCI interrupt is generated whenever TC=1 in
the SR register
Reset Value: Undefined
Bit 5 = RIE Receiver interrupt enable.
This bit is set and cleared by software.
0: interrupt is inhibited
1: An SCI interrupt is generated whenever OR=1
or RDRF=1 in the SR register
7
0
-
R8
T8
-
M
WAKE
-
-
Bit 7 = R8 Receive data bit 8.
This bit is used to store the 9th bit of the received
word when M=1.
Bit 4 = ILIE Idle line interrupt enable.
This bit is set and cleared by software.
0: interrupt is inhibited
1: An SCI interrupt is generated whenever IDLE=1
in the SR register.
Bit 6 = T8 Transmit data bit 8.
This bit is used to store the 9th bit of the transmit-
ted word when M=1.
Bit 3 = TE Transmitter enable.
This bit enables the transmitter and assigns the
TDO pin to the alternate function. It is set and
cleared by software.
0: Transmitter is disabled, the TDO pin is back to
the I/O port configuration.
Bit 4 = M Word length.
This bit determines the word length. It is set or
cleared by software.
0: 1 Start bit, 8 Data bits, 1 Stop bit
1: 1 Start bit, 9 Data bits, 1 Stop bit
1: Transmitter is enabled
Note: during transmission, a “0” pulse on the TE
bit (“0” followed by “1”) sends a preamble after the
current word.
Bit 3 = WAKE Wake-Up method.
This bit determines the SCI Wake-Up method, it is
set or cleared by software.
0: Idle Line
Bit 2 = RE Receiver enable.
This bit enables the receiver. It is set and cleared
by software.
1: Address Mark
0: Receiver is disabled, it resets the RDRF, IDLE,
OR, NF and FE bits of the SR register.
1: Receiver is enabled and begins searching for a
start bit.
CONTROL REGISTER 2 (CR2)
Read/Write
Reset Value: 0000 0000 (00h)
7
0
Bit 1 = RWU Receiver wake-up.
This bit determines if the SCI is in mute mode or
not. It is set and cleared by software and can be
cleared by hardware when a wake-up sequence is
recognized.
0: Receiver in active mode
1: Receiver in mute mode
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
Bit 7 = TIE Transmitter interrupt enable.
This bit is set and cleared by software.
0: interrupt is inhibited
1: An SCI interrupt is generated whenever
TDRE=1 in the SR register.
Bit 0 = SBK Send break.
This bit set is used to send break characters. It is
set and cleared by software.
0: No break character is transmitted
1: Break characters are transmitted
Bit 6 = TCIE Transmission complete interrupt ena-
ble
This bit is set and cleared by software.
0: interrupt is inhibited
Note: If the SBK bit is set to “1” and then to “0”, the
transmitter will send a BREAK word at the end of
the current word.
92/125
ST72334J/N, ST72314J/N, ST72124J
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
DATA REGISTER (DR)
Bit 5:3 = SCT[2:0] SCI Transmitter rate divisor
Read/Write
These 3 bits, in conjunction with the SCP1 & SCP0
bits define the total division applied to the bus
clock to yield the transmit rate clock in convention-
al Baud Rate Generator mode.
Reset Value: Undefined
Contains the Received or Transmitted data char-
acter, depending on whether it is read from or writ-
ten to.
TR dividing factor
SCT2
SCT1
SCT0
1
2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
7
0
4
DR7
DR6
DR5
DR4
DR3
DR2
DR1
DR0
8
The Data register performs a double function (read
and write) since it is composed of two registers,
one for transmission (TDR) and one for reception
(RDR).
The TDR register provides the parallel interface
between the internal bus and the output shift reg-
ister (see Figure 52).
The RDR register provides the parallel interface
between the input shift register and the internal
bus (see Figure 52).
16
32
64
128
Note: this TR factor is used only when the ETPR
fine tuning factor is equal to 00h; otherwise, TR is
replaced by the ETPR dividing factor.
Bit 2:0 = SCR[2:0] SCI Receiver rate divisor.
BAUD RATE REGISTER (BRR)
Read/Write
These 3 bits, in conjunction with the SCP1 & SCP0
bits define the total division applied to the bus
clock to yield the receive rate clock in conventional
Baud Rate Generator mode.
Reset Value: 00xx xxxx (XXh)
7
0
RR dividing factor
SCR2
SCR1
SCR0
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0
1
2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Bit 7:6= SCP[1:0] First SCI Prescaler
These 2 prescaling bits allow several standard
clock division ranges:
4
8
16
32
64
128
PR Prescaling factor
SCP1
SCP0
1
3
0
0
1
1
0
1
0
1
4
13
Note: this RR factor is used only when the ERPR
fine tuning factor is equal to 00h; otherwise, RR is
replaced by the ERPR dividing factor.
93/125
ST72334J/N, ST72314J/N, ST72124J
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
EXTENDED RECEIVE PRESCALER DIVISION
REGISTER (ERPR)
EXTENDED TRANSMIT PRESCALER DIVISION
REGISTER (ETPR)
Read/Write
Read/Write
Reset Value: 0000 0000 (00h)
Reset Value:0000 0000 (00h)
Allows setting of the Extended Prescaler rate divi-
sion factor for the receive circuit.
Allows setting of the External Prescaler rate divi-
sion factor for the transmit circuit.
7
0
7
0
ERPR ERPR ERPR ERPR ERPR ERPR ERPR ERPR
ETPR ETPR ETPR ETPR ETPR ETPR ETPR ETPR
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Bit 7:1 = ERPR[7:0] 8-bit Extended Receive Pres-
caler Register.
Bit 7:1 = ETPR[7:0] 8-bit Extended Transmit Pres-
caler Register.
The extended Baud Rate Generator is activated
when a value different from 00h is stored in this
register. Therefore the clock frequency issued
from the 16 divider (see Figure 54) is divided by
the binary factor set in the ERPR register (in the
range 1 to 255).
The extended Baud Rate Generator is activated
when a value different from 00h is stored in this
register. Therefore the clock frequency issued
from the 16 divider (see Figure 54) is divided by
the binary factor set in the ETPR register (in the
range 1 to 255).
The extended baud rate generator is not used af-
ter a reset.
The extended baud rate generator is not used af-
ter a reset.
Table 18. SCI Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
SCISR
Reset Value
TDRE
1
TC
1
RDRF
0
IDLE
0
OR
0
NF
0
FE
0
0050h
0051h
0052h
0053h
0054h
0055h
0057h
0
SCIDR
Reset Value
MSB
x
LSB
x
x
x
x
x
x
x
SCIBRR
Reset Value
SOG
0
VPOL
x
2FHDET
x
HVSEL VCORDIS CLPINV
BLKINV
x
0
x
x
x
SCICR1
Reset Value
R8
x
T8
x
M
x
WAKE
x
0
0
0
0
SCICR2
Reset Value
TIE
0
TCIE
0
RIE
0
ILIE
0
TE
0
RE
0
RWU
0
SBK
0
SCIPBRR
Reset Value
MSB
0
LSB
0
0
0
0
0
0
0
0
0
0
0
0
0
SCIPBRT
Reset Value
MSB
0
LSB
0
94/125
ST72334J/N, ST72314J/N, ST72124J
6.7 8-BIT A/D CONVERTER (ADC)
6.7.1 Introduction
6.7.3 Functional Description
6.7.3.1 Analog Power Supply
The on-chip Analog to Digital Converter (ADC) pe-
ripheral is a 8-bit, successive approximation con-
verter with internal sample and hold circuitry. This
peripheral has up to 16 multiplexed analog input
channels (refer to device pin out description) that
allow the peripheral to convert the analog voltage
levels from up to 16 different sources.
V
and V
are the high and low level refer-
SSA
DDA
ence voltage pins. In some devices (refer to device
pin out description) they are internally connected
to the V and V pins.
DD
SS
Conversion accuracy may therefore be impacted
by voltage drops and noise in the event of heavily
loaded or badly decoupled power supply lines.
The result of the conversion is stored in a 8-bit
Data Register. The A/D converter is controlled
through a Control/Status Register.
Figure 55. Recommended Ext. Connections
6.7.2 Main Features
V
■ 8-bit conversion
DD
V
V
DDA
SSA
0.1pF
■ Up to 16 channels with multiplexed input
■ Linear successive approximation
■ Data register (DR) which contains the results
■ Conversion complete status flag
■ On/off bit (to reduce consumption)
The block diagram is shown in Figure 56.
ST7
R
AIN
V
Px.x/AINx
AIN
Figure 56. ADC Block Diagram
f
f
CPU
ADC
DIV 2
COCO
0
ADON
4
0
CH3 CH2 CH1 CH0
ADCCSR
AIN0
AIN1
HOLD CONTROL
R
ADC
ANALOG TO DIGITAL
CONVERTER
ANALOG
MUX
C
SAMPLE
AINx
ADCDR
D7
D6
D5
D4 D3
D2
D1
D0
95/125
ST72334J/N, ST72314J/N, ST72124J
8-BIT A/D CONVERTER (ADC) (Cont’d)
6.7.3.2 Digital A/D Conversion Result
The analog input ports must be configured as in-
put, no pull-up, no interrupt. Refer to the «I/O
ports» chapter. Using these pins as analog inputs
does not affect the ability of the port to be read as
a logic input.
The conversion is monotonic, meaning that the re-
sult never decreases if the analog input does not
and never increases if the analog input does not.
If the input voltage (V ) is greater than or equal
AIN
In the CSR register:
to V
(high-level voltage reference) then the
DDA
conversion result in the DR register is FFh (full
scale) without overflow indication.
– Select the CH[3:0] bits to assign the analog
channel to convert.
ADC Conversion
If input voltage (V ) is lower than or equal to
AIN
V
(low-level voltage reference) then the con-
SSA
In the CSR register:
version result in the DR register is 00h.
– Set the ADON bit to enable the A/D converter
and to start the first conversion. From this time
on, the ADC performs a continuous conver-
sion of the selected channel.
The A/D converter is linear and the digital result of
the conversion is stored in the ADCDR register.
The accuracy of the conversion is described in the
Electrical Characteristics Section.
When a conversion is complete
– The COCO bit is set by hardware.
– No interrupt is generated.
– The result is in the DR register and remains
valid until the next conversion has ended.
A write to the CSR register (with ADON set) aborts
the current conversion, resets the COCO bit and
starts a new conversion.
R
is the maximum recommended impedance
AIN
for an analog input signal. If the impedance is too
high, this will result in a loss of accuracy due to
leakage and sampling not being completed in the
alloted time.
6.7.3.3 A/D Conversion Phases
The A/D conversion is based on two conversion
phases as shown in Figure 57:
Figure 57. ADC Conversion Timings
■ Sample capacitor loading
[duration: t
]
LOAD
ADON
During this phase, the V
input voltage to be
AIN
ADCCSR WRITE
measured is loaded into the C
capacitor.
sample
SAMPLE
OPERATION
t
CONV
■ A/D conversion
[duration: t
]
HOLD
CONV
CONTROL
During this phase, the A/D conversion is
computed (8 successive approximations cycles)
and the
C
sample capacitor is
SAMPLE
COCO BIT SET
disconnected from the analog input pin to get
the optimum A/D conversion accuracy.
t
LOAD
6.7.4 Low Power Modes
While the ADC is on, these two phases are contin-
uously repeated.
Note: The A/D converter may be disabled by re-
setting the ADON bit. This feature allows reduced
power consumption when no conversion is need-
ed and between single shot conversions..
At the end of each conversion, the sample capaci-
tor is kept loaded with the previous measurement
load. The advantage of this behaviour is that it
minimizes the current consumption on the analog
pin in case of single input channel measurement.
Mode
Description
WAIT
No effect on A/D Converter
A/D Converter disabled.
6.7.3.4 Software Procedure
Refer to the control/status register (CSR) and data
register (DR) in Section 6.7.6 for the bit definitions
and to Figure 57 for the timings.
After wakeup from Halt mode, the A/D
Converter requires a stabilisation time
before accurate conversions can be
performed.
HALT
ADC Configuration
The total duration of the A/D conversion is 12 ADC
clock periods (1/f
=2/f ).
CPU
6.7.5 Interrupts
ADC
None
96/125
ST72334J/N, ST72314J/N, ST72124J
8-BIT A/D CONVERTER (ADC) (Cont’d)
6.7.6 Register Description
CONTROL/STATUS REGISTER (CSR)
Read/Write
DATA REGISTER (DR)
Read Only
Reset Value: 0000 0000 (00h)
Reset Value: 0000 0000 (00h)
7
0
7
0
COCO
0
ADON
0
CH3
CH2
CH1
CH0
D7
D6
D5
D4
D3
D2
D1
D0
Bit 7 = COCO Conversion Complete
This bit is set by hardware. It is cleared by soft-
ware reading the result in the DR register or writing
to the CSR register.
0: Conversion is not complete
1: Conversion can be read from the DR register
Bit 7:0 = D[7:0] Analog Converted Value
This register contains the converted analog value
in the range 00h to FFh.
Note: Reading this register reset the COCO flag.
Bit 6 = Reserved. must always be cleared.
Bit 5 = ADON A/D Converter On
This bit is set and cleared by software.
0: A/D converter is switched off
1: A/D converter is switched on
Bit 4 = Reserved. must always be cleared.
Bit 3:0 = CH[3:0] Channel Selection
These bits are set and cleared by software. They
select the analog input to convert.
Channel Pin*
CH3 CH2 CH1 CH0
AIN0
AIN1
AIN2
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
AIN10
AIN11
AIN12
AIN13
AIN14
AIN15
*Note: The number of pins AND the channel selection var-
ies according to the device. Refer to the device pinout.
97/125
ST72334J/N, ST72314J/N, ST72124J
8-BIT A/D CONVERTER (ADC) (Cont’d)
Table 19. ADC Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
ADCDR
Reset Value
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
0070h
0071h
ADCCSR
Reset Value
COCO
0
ADON
0
CH3
0
CH2
0
CH1
0
CH0
0
0
0
98/125
ST72334J/N, ST72314J/N, ST72124J
7 INSTRUCTION SET
7.1 ST7 ADDRESSING MODES
so, most of the addressing modes may be subdi-
vided in two sub-modes called long and short:
The ST7 Core features 17 different addressing
modes which can be classified in 7 main groups:
– Long addressing mode is more powerful be-
cause itcan use the full 64 Kbyte address space,
however it uses more bytes and more CPU cy-
cles.
Addressing Mode
Inherent
Example
nop
– Short addressing mode is less powerful because
it can generally only access page zero (0000h -
00FFh range), but the instruction size is more
compact, and faster. All memory to memory in-
structions use short addressing modes only
(CLR, CPL, NEG, BSET, BRES, BTJT, BTJF,
INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP)
Immediate
Direct
ld A,#$55
ld A,$55
ld A,($55,X)
ld A,([$55],X)
jrne loop
Indexed
Indirect
Relative
Bit operation
bset byte,#5
The ST7 Assembler optimizes the use of long and
short addressing modes.
The ST7 Instruction set is designed to minimize
the number of bytes required per instruction: To do
Table 20. ST7 Addressing Mode Overview
Pointer Pointer
Destination/
Source
Length
(Bytes)
Mode
Syntax
Address
(Hex.)
Size
(Hex.)
Inherent
Immediate
Short
nop
+ 0
+ 1
+ 1
+ 2
ld A,#$55
ld A,$10
Direct
Direct
00..FF
Long
ld A,$1000
0000..FFFF
+ 0 (with X register)
+ 1 (with Y register)
No Offset
Direct
Indexed
ld A,(X)
00..FF
Short
Long
Short
Long
Short
Long
Relative
Relative
Bit
Direct
Indexed
Indexed
ld A,($10,X)
ld A,($1000,X)
ld A,[$10]
00..1FE
+ 1
+ 2
+ 2
+ 2
+ 2
+ 2
+ 1
+ 2
+ 1
+ 2
+ 2
+ 3
Direct
0000..FFFF
00..FF
Indirect
Indirect
Indirect
Indirect
Direct
00..FF
00..FF
00..FF
00..FF
byte
word
byte
word
ld A,[$10.w]
ld A,([$10],X)
0000..FFFF
00..1FE
Indexed
Indexed
ld A,([$10.w],X) 0000..FFFF
1)
1)
jrne loop
PC-128/PC+127
Indirect
Direct
jrne [$10]
PC-128/PC+127
00..FF
00..FF
00..FF
00..FF
byte
byte
byte
bset $10,#7
bset [$10],#7
Bit
Indirect
Direct
00..FF
Bit
Relative
Relative
btjt $10,#7,skip 00..FF
btjt [$10],#7,skip 00..FF
Bit
Indirect
Note 1. At the time the instruction is executed, the Program Counter (PC) points to the instruction follow-
ing JRxx.
99/125
ST72334J/N, ST72314J/N, ST72124J
ST7 ADDRESSING MODES (Cont’d)
7.1.1 Inherent
7.1.3 Direct
All Inherent instructions consist of a single byte.
The opcode fully specifies all the required informa-
tion for the CPU to process the operation.
In Direct instructions, the operands are referenced
by their memory address.
The direct addressing mode consists of two sub-
modes:
Inherent Instruction
Function
No operation
Direct (short)
NOP
The address is a byte, thus requires only one byte
after the opcode, but only allows 00 - FF address-
ing space.
TRAP
S/W Interrupt
Wait For Interrupt (Low Power
Mode)
WFI
Direct (long)
Halt Oscillator (Lowest Power
Mode)
HALT
The address is a word, thus allowing 64 Kbyte ad-
dressing space, but requires 2 bytes after the op-
code.
RET
Sub-routine Return
Interrupt Sub-routine Return
Set Interrupt Mask
Reset Interrupt Mask
Set Carry Flag
IRET
SIM
7.1.4 Indexed (No Offset, Short, Long)
RIM
In this mode, the operand is referenced by its
memory address, which is defined by the unsigned
addition of an index register (X or Y) with an offset.
SCF
RCF
Reset Carry Flag
Reset Stack Pointer
Load
The indirect addressing mode consists of three
sub-modes:
RSP
LD
Indexed (No Offset)
CLR
Clear
There is no offset, (no extra byte after the opcode),
and allows 00 - FF addressing space.
PUSH/POP
INC/DEC
TNZ
Push/Pop to/from the stack
Increment/Decrement
Test Negative or Zero
1 or 2 Complement
Byte Multiplication
Indexed (Short)
The offset is a byte, thus requires only one byte af-
ter the opcode and allows 00 - 1FE addressing
space.
CPL, NEG
MUL
Indexed (long)
SLL, SRL, SRA, RLC,
RRC
Shift and Rotate Operations
Swap Nibbles
The offset is a word, thus allowing 64 Kbyte ad-
dressing space and requires 2 bytes after the op-
code.
SWAP
7.1.2 Immediate
Immediate instructions have two bytes, the first
byte contains the opcode, the second byte con-
tains the the operand value.
7.1.5 Indirect (Short, Long)
The required data byte to do the operation is found
by its memory address, located in memory (point-
er).
Immediate Instruction
Function
The pointer address follows the opcode. The indi-
rect addressing mode consists of two sub-modes:
LD
Load
CP
Compare
Indirect (short)
BCP
Bit Compare
The pointer address is a byte, the pointer size is a
byte, thus allowing 00 - FF addressing space, and
requires 1 byte after the opcode.
AND, OR, XOR
ADC, ADD, SUB, SBC
Logical Operations
Arithmetic Operations
Indirect (long)
The pointer address is a byte, the pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.
100/125
ST72334J/N, ST72314J/N, ST72124J
7.1.7 Relative mode (Direct, Indirect)
ST7 ADDRESSING MODES (Cont’d)
7.1.6 Indirect Indexed (Short, Long)
This is a combination of indirect and short indexed
addressing modes. The operand is referenced by
its memory address, which is defined by the un-
signed addition of an index register value (X or Y)
with a pointer value located in memory. The point-
er address follows the opcode.
This addressing mode is used to modify the PC
register value, by adding an 8-bit signed offset to
it.
Available Relative Direct/
Function
Indirect Instructions
JRxx
Conditional Jump
Call Relative
The indirect indexed addressing mode consists of
two sub-modes:
CALLR
Indirect Indexed (Short)
The pointer address is a byte, the pointer size is a
byte, thus allowing 00 - 1FE addressing space,
and requires 1 byte after the opcode.
The relative addressing mode consists of two sub-
modes:
Relative (Direct)
The offset is following the opcode.
Relative (Indirect)
Indirect Indexed (Long)
The pointer address is a byte, the pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.
The offset is defined in memory, which address
follows the opcode.
Table 21. Instructions Supporting Direct,
Indexed, Indirect and Indirect Indexed
Addressing Modes
Long and Short
Function
Instructions
LD
Load
CP
Compare
AND, OR, XOR
Logical Operations
Arithmetic Addition/subtrac-
tion operations
ADC, ADD, SUB, SBC
BCP
Bit Compare
Short Instructions Only
CLR
Function
Clear
INC, DEC
Increment/Decrement
Test Negative or Zero
1 or 2 Complement
Bit Operations
TNZ
CPL, NEG
BSET, BRES
Bit Test and Jump Opera-
tions
BTJT, BTJF
SLL, SRL, SRA, RLC,
RRC
Shift and Rotate Operations
SWAP
Swap Nibbles
CALL, JP
Call or Jump subroutine
101/125
ST72334J/N, ST72314J/N, ST72124J
7.2 INSTRUCTION GROUPS
The ST7 family devices use an Instruction Set
consisting of 63 instructions. The instructions may
be subdivided into 13 main groups as illustrated in
the following table:
Load and Transfer
LD
CLR
POP
DEC
TNZ
OR
Stack operation
PUSH
INC
RSP
BCP
Increment/Decrement
Compare and Tests
Logical operations
CP
AND
BSET
BTJT
ADC
SLL
XOR
CPL
NEG
Bit Operation
BRES
BTJF
ADD
SRL
JRT
Conditional Bit Test and Branch
Arithmetic operations
Shift and Rotates
SUB
SRA
JRF
SBC
RLC
JP
MUL
RRC
CALL
SWAP
CALLR
SLA
Unconditional Jump or Call
Conditional Branch
JRA
JRxx
TRAP
SIM
NOP
RET
Interruption management
Code Condition Flag modification
WFI
RIM
HALT
SCF
IRET
RCF
Using a pre-byte
The instructions are described with one to four
bytes.
These prebytes enable instruction in Y as well as
indirect addressing modes to be implemented.
They precede the opcode of the instruction in X or
the instruction using direct addressing mode. The
prebytes are:
In order to extend the number of available op-
codes for an 8-bit CPU (256 opcodes), three differ-
ent prebyte opcodes are defined. These prebytes
modify the meaning of the instruction they pre-
cede.
PDY 90
Replace an X based instruction
using immediate, direct, indexed, or inherent ad-
dressing mode by a Y one.
The whole instruction becomes:
PIX 92
Replace an instruction using di-
PC-2
PC-1
PC
End of previous instruction
Prebyte
rect, direct bit, or direct relative addressing mode
to an instruction using the corresponding indirect
addressing mode.
It also changes an instruction using X indexed ad-
dressing mode to an instruction using indirect X in-
dexed addressing mode.
opcode
PC+1
Additional word (0 to 2) according
to the number of bytes required to compute the ef-
fective address
PIY 91
Replace an instruction using X in-
direct indexed addressing mode by a Y one.
102/125
ST72334J/N, ST72314J/N, ST72124J
INSTRUCTION GROUPS (Cont’d)
Mnemo
ADC
ADD
AND
BCP
Description
Add with Carry
Function/Example
A = A + M + C
A = A + M
Dst
Src
H
H
H
I
N
N
N
N
N
Z
Z
Z
Z
Z
C
C
C
A
M
M
M
M
Addition
A
Logical And
A = A . M
A
Bit compare A, Memory
Bit Reset
tst (A . M)
A
BRES
BSET
BTJF
BTJT
CALL
CALLR
CLR
bres Byte, #3
bset Byte, #3
btjf Byte, #3, Jmp1
btjt Byte, #3, Jmp1
M
M
M
M
Bit Set
Jump if bit is false (0)
Jump if bit is true (1)
Call subroutine
Call subroutine relative
Clear
C
C
reg, M
reg
0
N
N
N
1
Z
Z
Z
CP
Arithmetic Compare
One Complement
Decrement
tst(Reg - M)
A = FFH-A
dec Y
M
C
1
CPL
reg, M
reg, M
DEC
HALT
IRET
INC
Halt
0
I
Interrupt routine return
Increment
Pop CC, A, X, PC
inc X
H
N
N
Z
Z
C
reg, M
JP
Absolute Jump
Jump relative always
Jump relative
jp [TBL.w]
JRA
JRT
JRF
Never jump
jrf *
JRIH
JRIL
Jump if ext. interrupt = 1
Jump if ext. interrupt = 0
Jump if H = 1
JRH
H = 1 ?
JRNH
JRM
Jump if H = 0
H = 0 ?
Jump if I = 1
I = 1 ?
JRNM
JRMI
JRPL
JREQ
JRNE
JRC
Jump if I = 0
I = 0 ?
Jump if N = 1 (minus)
Jump if N = 0 (plus)
Jump if Z = 1 (equal)
Jump if Z = 0 (not equal)
Jump if C = 1
N = 1 ?
N = 0 ?
Z = 1 ?
Z = 0 ?
C = 1 ?
JRNC
JRULT
Jump if C = 0
C = 0 ?
Jump if C = 1
Unsigned <
Jmp if unsigned >=
Unsigned >
JRUGE Jump if C = 0
JRUGT Jump if (C + Z = 0)
103/125
ST72334J/N, ST72314J/N, ST72124J
INSTRUCTION GROUPS (Cont’d)
Mnemo
JRULE
LD
Description
Jump if (C + Z = 1)
Load
Function/Example
Unsigned <=
dst <= src
Dst
Src
H
I
N
N
N
N
N
Z
Z
Z
Z
Z
C
reg, M
A, X, Y
reg, M
M, reg
MUL
NEG
NOP
OR
Multiply
X,A = X * A
X, Y, A
0
0
Negate (2’s compl)
No Operation
OR operation
Pop from the Stack
neg $10
C
A = A + M
pop reg
pop CC
push Y
C = 0
A
M
POP
reg
CC
M
M
M
H
I
C
0
PUSH
RCF
RET
RIM
Push onto the Stack
Reset carry flag
Subroutine Return
Enable Interrupts
Rotate left true C
Rotate right true C
Reset Stack Pointer
Subtract with Carry
Set carry flag
reg, CC
I = 0
0
RLC
RRC
RSP
SBC
SCF
SIM
C <= Dst <= C
C => Dst => C
S = Max allowed
A = A - M - C
C = 1
reg, M
reg, M
N
N
Z
Z
C
C
A
M
N
Z
C
1
Disable Interrupts
Shift left Arithmetic
Shift left Logic
I = 1
1
SLA
C <= Dst <= 0
C <= Dst <= 0
0 => Dst => C
Dst7 => Dst => C
A = A - M
reg, M
reg, M
reg, M
reg, M
A
N
N
0
Z
Z
Z
Z
Z
Z
Z
C
C
C
C
C
SLL
SRL
SRA
SUB
SWAP
TNZ
TRAP
WFI
Shift right Logic
Shift right Arithmetic
Subtraction
N
N
N
N
M
SWAP nibbles
Dst[7..4] <=> Dst[3..0] reg, M
tnz lbl1
Test for Neg & Zero
S/W trap
S/W interrupt
1
0
Wait for Interrupt
Exclusive OR
XOR
A = A XOR M
A
M
N
Z
104/125
ST72334J/N, ST72314J/N, ST72124J
8 ELECTRICAL CHARACTERISTICS
8.1 ABSOLUTE MAXIMUM RATINGS
This product contains devices for protecting the in-
puts against damage due to high static voltages,
however it is advisable to take normal precautions
to avoid applying any voltage higher than the
specified maximum rated voltages.
Power Considerations. The average chip-junc-
tion temperature, T , in Celsius can be obtained
J
from:
T =
A
TA + PD x RthJA
Ambient Temperature.
J
Where: T =
RthJA =Package thermal resistance
(junction-to ambient).
For proper operation it is recommended that V
I
and V be higher than V and lower than V .
O
SS
DD
P
P
P
=
INT
PORT
P
DD
+ P
DD
.
Reliability is enhanced if unused inputs are con-
D
INT
PORT
= I x V (chip internal power).
nected to an appropriate logic voltage level (V
or V ).
DD
=Port power dissipation
determined by the user)
SS
Symbol
Ratings
Value
Unit
V
- V
- V
Supply voltage
Analog reference voltage
> VSS
6.5
V
DD
SS
V
6.5
50
V
DDA
SSA
DD_j
V
DDA
|V
|V
- V
|
|
DD_i
Max. variations (power line)
Max. variations (ground line)
mV
- V
DD_i
DDA
|V
|V
- V
|
|
SS_i
SS_j
50
mV
- V
SS_i
SSA
V
Input voltage
VSS - 0.3 to VDD + 0.3
V
V
V
IN
V
Output voltage
ESD susceptibility
VSS - 0.3 to VDD + 0.3
OUT
ESD
2000
150
I
Total current into V
(source)
DD_i
VDD_i
mA
I
Total current out of V
(sink)
SS_i
150
VSS_i
Note:
Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating con-
ditions for extended periods may affect device reliability.
General Warning:
Directly connecting the RESET and I/O pins to V or V could damage the device if an unintentional internal reset is
DD
SS
generated or the program counter is corrupted (by an expected change to the I/O configuration). To guarantee safe op-
eration, this connection has to be done through a pull-up or pull-down resistor (10KΩ typical).
Thermal Characteristics
Symbol
Ratings
Value
Unit
Package thermal resistance
TQFP64
SDIP56
TQFP44
SDIP42
60
TBD
TBD
TBD
R
°C/W
thJA
TJmax
TSTG
PD
Max. junction temperature
Storage temperature range
Power dissipation
150
-65 to +150
500
°C
°C
mW
105/125
ST72334J/N, ST72314J/N, ST72124J
8.2 RECOMMENDED OPERATING CONDITIONS
GENERAL
Symbol
Parameter
Supply voltage
Conditions
Min
Typ
Max
Unit
V
see Figure 58
≥ 3.5V
3.0
1
5.5
16
8
V
DD
V
V
V
V
DD
DD
DD
DD
Resonator oscillator frequency
External clock source
≥ 3.0V
1
f
MHz
OSC
2)
≥ 3.5V
0
16
8
2)
≥ 3.0V
0
1 Suffix Version
6 Suffix Version
7 Suffix Version
3 Suffix Version
0
70
85
105
125
-40
-40
-40
T
Ambient temperature range
°C
A
3)
Figure 58. f
Maximum Operating Frequency Versus VDD Supply Voltage
OSC
FUNCTIONALITY NOT GUARANTEED IN THIS AREA
FUNCTIONA LITY GUARANTEED IN THIS AREA
FUNCTIONALITY NOT GUARANTEED IN THIS AREA
FOR TEMPERATURE HIGHER THAN 85°C
f
OSC
[MHz]
16
8
4
1
0
SUPPLY VOLTAGE [V]
2.5
3
3.5
4
4.5
5
5.5
FUNCTIONALITY NOT GUARANTEED IN THIS AREA WITH RESONATOR
Notes:
1) Unless otherwise specified, typical data are based on T =25°C and V -V =5V. They are given only as design guide-
A
DD SS
lines and are not tested.
2) A/D operation and resonator oscillator start-up are not guaranteed below 1MHz.
3) Operating conditions T =-40 to +85°C. The shaded area is outside the recommended operating range; device func-
A
tionality is not guaranteed under these conditions.
106/125
ST72334J/N, ST72314J/N, ST72124J
8.3 DC ELECTRICAL CHARACTERISTICS
o
Recommended operating conditions with T =-40 to +85 C, V -V =5V unless otherwise specified.
A
DD SS
1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
f
f
f
= 4 MHz, f
= 8 MHz, f
= 16 MHz, f
= 2 MHz
= 4 MHz
OSC
OSC
OSC
CPU
CPU
2)
Supply current in RUN mode
TBD
= 8 MHz
CPU
f
f
f
= 4 MHz, f
= 8 MHz, f
= 16 MHz, f
= 125 kHz
= 250 kHz
OSC
OSC
OSC
CPU
CPU
2)
Supply current in SLOW mode
TBD
TBD
= 500 kHz
CPU
mA
I
f
f
f
= 4 MHz, f
= 2 MHz
= 4 MHz
DD
OSC
OSC
OSC
CPU
= 8MHz, f
CPU
3)
Supply current in WAIT mode
= 16MHz, f
= 8 MHz
CPU
f
f
f
= 4 MHz, f
= 8 MHz, f
= 16 MHz, f
= 2 MHz
= 250 kHz
OSC
OSC
OSC
CPU
CPU
3)
Supply current in SLOW WAIT mode
TBD
TBD
= 500 kHz
CPU
4)
Supply current in HALT mode
I
= 0mA (current on I/Os)
µA
LOAD
5)
V
Data retention mode
HALT mode
2
V
RM
8.4 GENERAL TIMING CHARACTERISTICS
Symbol
Parameter
Instruction time
Interrupt reaction time
Conditions
Min
Typ
Max
Unit
t
2
12
22
tCPU
tCPU
INST
6)
t
tIRT = ∆tINST + 10
10
IRT
Notes:
1) Unless otherwise specified, typical data are based on T =25°C and V -V =5V. They are given only as design guide-
A
DD SS
lines and are not tested.
2) CPU running with memory access, all I/O pins in input mode with a static value at V
off; clock input (OSC1) driven by external square wave.
or V , all peripherals switched
SS
DD
3) All I/O pins in input mode with a static value at V or V , all peripherals switched off; clock input (OSC1) driven by
DD
SS
external square wave.
4) All I/O pins in input mode with a static value at V or V , LVD disabled.
DD
SS
5) Data based on characterization results, not tested in production.
6) ∆tINST is the number of tCPU to finish the current instruction execution.
107/125
ST72334J/N, ST72314J/N, ST72124J
8.5 I/O PORT CHARACTERISTICS
Recommended operating conditions
o
with T =-40 to +85 C and 4.5V<V -V <5.5V unless otherwise specified.
A
DD SS
I/O PORT PINS
1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
2)
V
Input low level voltage
0.3xVDD
IL
V
2)
V
Input high level voltage
3V<V -V <5.5V
0.7xVDD
IH
DD SS
3)
V
Schmitt trigger voltage hysteresis
400
mV
HYS
I=-5mA
I=-2mA
I=-20mA
I=-8mA
I=-5mA
I=-2mA
1.3
0.5
1.3
0.5
Output low level voltage
for Standard I/O port pins
V
OL
Output low level voltage
for high sink I/O port pins
V
V
V
-2.0
-0.8
DD
V
Output high level voltage
OH
DD
35
100
50
140
V
V
> V
< V
20
60
IN
IN
IH
IL
R
Pull-up equivalent resistor
Input leakage current
kΩ
µA
PU
I
V
<V <V
DD
1
200
5
L
SS
PIN
2)
I
Static current consumption
Floating input mode
SV
5)
Positive : V
>V
DD
EXT
I
Single pin injected current
PINJ
6)
Negative : V
<V
-5
EXT
SS
mA
7)
Positive: V
>V
tbd
tbd
Total injected current
EXT
DD
I
INJ
(sum of all I/O and control pins)
Negative: V
<V
SS
EXT
4)
4)
4)
t
Output high to low level fall time
Output low to high rise time
14.8
14.4
1
25
25
45.6
OHL
C =50pF
ns
l
4)
t
45.9
OLH
8)
t
External interrupt pulse time
t
CPU
ITEXT
Notes:
1) Unless otherwise specified, typical data are based on T =25°C and V -V =5V. They are given only as design guide-
A
DD SS
lines and are not tested.
2) Data based on design simulation and/or technology characteristics, not tested in production.
3) Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
4) Data based on characterization results, not tested in production.
5) Positive injection (I
)
INJ+
The I
is performed through protection diodes insulated from the substrate of the die.
INJ+
The true open-drain pins do not accept positive injection. In this case the maximum voltage rating must be respected.
6) ADC accuracy reduced by negative injection (I
)
INJ-
The I
is performed through protection diodes NOT INSULATED from the substrate of the die. The drawback is a small
INJ-
leakage (a few µA) induced inside the die when a negative injection is performed. This leakage is tolerated by the digital
structure, but it acts on the analog line depending on the impedance versus a leakage current of a few µA (if the MCU
has an AD converter). The effect depends on the pin which is submitted to the injection. Of course, external digital signals
applied to the component must have a maximum impedance close to 50KΩ.
Location of the negative current injection:
- Pins with analog input capability are the most sensitive. I
maximum is 0.8 mA (assuming that the impedance of the
INJ-
analog voltage is lower than 25KΩ)
- Pure digital pins can tolerate 1.6mA. In addition, the best choice is to inject the current as far as possible from the analog
input pins.
7) When several inputs are submitted to a current injection, the maximum I is the sum of the positive (or negative) cur-
INJ
rents (instantaneous values). These results are based on characterisation with I
O port pins of the device.
maximum current injection on four I/
INJ
8) To generate anexternal interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external
interrupt source.
108/125
ST72334J/N, ST72314J/N, ST72124J
8.6 SUPPLY, RESET AND CLOCK CHARACTERISTICS
8.6.1 Supply Manager
Recommended operating conditions
o
with T =-40 to +85 C and voltage are referred to V unless otherwise specified.
A
SS
LOW VOLTAGE DETECTOR (LVD)
1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
High Threshold
Med. Threshold (f
Low Threshold (f
4.30
3.90
3.35
4.50
4.05
3.45
Reset release threshold
V
≤16MHz)
≤8MHz)
LVDr
OSC
(V rise)
DD
OSC
V
High Threshold
Med. Threshold (f
Low Threshold (f
3.85
≤16MHz) 3.50
4.05
3.65
3.10
4.25
3.80
3.20
Reset generation threshold
V
V
LVDf
OSC
(V fall)
DD
≤8MHz)
3.00
OSC
2)
V
Hysteresis
V
- V
LVDf
250*
100
mV
LVDhyst
LVD
LVDr
3)
I
LVD Supply Current
HALT mode
150
µA
DD
8.6.2 Reset Sequence Manager
Recommended operating conditions
o
with T =-40...+85 C and 4.5V<V -V <5.5V unless otherwise specified.
A
DD SS
RESET SEQUENCE MANAGER (RSM)
4)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
V
V
> V
< V
5
40
10
80
20
160
IN
IH
IL
R
Reset weak pull-up resistance
kΩ
ON
IN
Reset delay for external and
watchdog reset sources
6
30
1/f
SFOSC
t
t
DELAYmin
PULSE
µs
External RESET pin Pulse time
20
µs
8.6.3 Multi-Oscillator, Clock Security System
Recommended operating conditions
o
with T =-40 to +85 C and voltage are referred to V unless otherwise specified.
A
SS
EXTERNAL CLOCK SOURCE
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
V
OSC1 input pin high level voltage
OSC1 input pin low level voltage
0.7xV
V
Square wave signal
with ~50% Duty Cycle
DD
DD
OSC1h
OSC1l
V
V
0.3xV
V
SS
DD
Notes:
1) LVD typical data are based on T =25°C. They are given only as design guidelines and are not tested.
A
2) The V
hysteresis is constant.
LVDhyst
3) Data based on characterization results, not tested in production.
4) Unless otherwise specified, typical data are based on T =25°C and V -V =5V. They are given only as design guide-
A
DD SS
lines and are not tested.
109/125
ST72334J/N, ST72314J/N, ST72124J
SUPPLY, RESET AND CLOCK CHARACTERISTICS (Cont’d)
CRYSTAL AND CERAMIC RESONATOR OSCILLATORS
1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Low speed resonator
Medium-low speed resonator
Medium-high speed resonator
1
2
4
8
>2
>4
>8
2)
f
Oscillator Frequency
MHz
OSC
High speed resonator
16
3)
4)
4)
Low speed
Medium-low speed
Capacitance Medium-high speed
High speed
R
R
R
R
=200
=200
=200
=100
Ω
Ω
Ω
Ω
38
32
18
15
47
56
46
26
21
Smax
Smax
Smax
Smax
3)
3)
3)
4)
4)
4)
4)
4)
4)
Load
39
22
18
C
I
pF
Li
5)
Low speed
150
200
400
700
700
700
750
5)
5)
Supply
Current
Medium-low speed
Medium-high speed
High speed
µA
DD
5)
1100
t
Oscillator start-up time
Depends on resonator quality. A typical value is 10ms
START
EXTERNAL RC OSCILLATOR
4)
1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
4)
f
External RC Oscillator Frequency
Oscillator External Resistance
Oscillator External Capacitance
Supply Current
1
14
47
MHz
kΩ
OSC
4)
4)
R
C
V
=5V
DD
10
33
EX
EX
6)
0
47
470
750
pF
5)
I
525
µA
DD
INTERNAL RC OSCILLATOR
1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
V
V
=5.5V
=3.0V
3.50
3.35
4.25
4.10
500
5.00
4.85
DD
f
I
Internal RC Oscillator Frequency
Supply Current
MHz
OSC
DD
DD
5)
750
µA
CLOCK SECURITY SYSTEM (CSS)
1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
V
V
=5.5V
=3.0V
250
190
340
430
330
DD
f
Safe Oscillator Frequency
kHz
SFOSC
260
30
DD
f
I
Clock Filter Frequency limitation
Supply Current
MHz
CFL
DD
5)
150
350
µA
Notes:
1) Unless otherwise specified, typical data are based on T =25°C and V -V =5V. They are given only as design guide-
A
DD SS
lines and are not tested.
2) These data are based on typical R
quality resonator.
. The oscillator selection can be optimized in terms of supply current with high
Smax
3) R
is the equivalent serial resistance of the crystal or ceramic resonator.
Smax
4) Data based on design simulation and/or technology characteristics, not tested in production.
5) Data based on characterization results, not tested in production.
6) In this condition, the capacitor to be considered is the global parasitic capacitor. In this case, the RC oscillator frequen-
cy tuning has to be done by trying out several resistor values.
110/125
ST72334J/N, ST72314J/N, ST72124J
8.7 MEMORY AND PERIPHERAL CHARACTERISTICS
Recommended operating conditions
o
with T =-40 to +85 C and 3V<V -V <5.5V unless otherwise specified.
A
DD SS
FLASH Program Memory
1)
Symbol
Parameter
Typical programming time
Conditions
Min
Typ
Max
Unit
t
8 or 16kBytes FLASH
2.1
6.4
sec
ISPPROG
t
Data retention
T =55°C
20
years
cycles
RET
A
N
Write erase cycles
1000
RW
Data-EEPROM
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
t
Programming time
25
ms
PROG
t
Data retention
10
Years
Cycles
RET
N
Write erase cycles
100 000
RW
WATCHDOG
Symbol
Parameter
Watchdog time-out
Conditions
Min
Typ
Max
Unit
12,288
1.54
786,432
98.3
tCPU
ms
t
DOG
fCPU = 8MHz
Note:
1) Unless otherwise specified, typical data are based on T =25°C and V -V =5V. They are given only as design guide-
A
DD SS
lines and are not tested.
111/125
ST72334J/N, ST72314J/N, ST72124J
MEMORY AND PERIPHERAL CHARACTERISTICS (Cont’d)
SPI Serial Peripheral Interface
1)
Value
Min
Ref.
Symbol
Parameter
Condition
Unit
Max
Master
Slave
1/128
dc
1/4
1/2
f
t
SPI frequency
f
t
SPI
SPI
CPU
CPU
Master
Slave
4
2
1
SPI clock period
2
3
t
Enable lead time
Enable lag time
Slave
Slave
120
120
ns
ns
Lead
t
Lag
Master
Slave
100
90
4
5
t
Clock (SCK) high time
Clock (SCK) low time
Data set-up time
ns
ns
ns
ns
ns
ns
SPI_H
Master
Slave
100
90
t
SPI_L
Master
Slave
100
100
6
t
SU
Master
Slave
100
100
7
t
t
Data hold time (inputs)
H
A
Access time (time to data active
from high impedance state)
8
0
120
240
Slave
Disable time (hold time to high im-
pedance state)
9
t
Dis
Master (before capture edge)
Slave (after enable edge)
0.25
t
t
CPU
ns
10
11
12
13
t
Data valid
V
120
Master (before capture edge)
Slave (after enable edge)
0.25
0
CPU
ns
t
Data hold time (outputs)
Rise time
Hold
Outputs: SCK,MOSI,MISO
(20% V to 70% V , C = 200pF) Inputs: SCK,MOSI,MISO,SS
100
100
ns
µs
t
Rise
DD
DD
L
Fall time
Outputs: SCK,MOSI,MISO
(70% V to 20% V , C = 200pF) Inputs: SCK,MOSI,MISO,SS
100
100
ns
µs
t
Fall
DD
DD
L
Figure 59. SPI Master Timing Diagram CPHA=0, CPOL=0 2)
SS
(INPUT)
1
13
12
SCK
(OUTPUT)
5
4
MISO
(INPUT)
D7-IN
7
D6-IN
D0-IN
6
MOSI
(OUTPUT)
D7-OUT
11
D6-OUT
D0-OUT
10
VR000109
Notes:
1) Data based on characterization results, not tested in production.
2) Measurement points are V , V , V and V in the SPI timing diagram.
OL OH
IL
IH
112/125
ST72334J/N, ST72314J/N, ST72124J
MEMORY AND PERIPHERAL CHARACTERISTICS (Cont’d)
Figure 60. SPI Master Timing Diagram CPHA=0, CPOL=1 1)
SS
(INPUT)
1
13
12
SCK
(OUTPUT)
5
4
MISO
(INPUT)
D7-IN
7
D6-IN
D0-IN
6
MOSI
(OUTPUT)
D7-OUT
11
D6-OUT
D0-OUT
10
VR000110
Figure 61. SPI Master Timing Diagram CPHA=1, CPOL=0 1)
SS
(INPUT)
1
13
12
SCK
(OUTPUT)
4
5
MISO
(INPUT)
D7-OUT
D6-OUT
D0-OUT
6
7
MOSI
(OUTPUT)
D7-IN
11
D6-IN
D0-IN
10
VR000107
Figure 62. SPI Master Timing Diagram CPHA=1, CPOL=1 1)
SS
(INPUT)
1
12
13
SCK
(OUTPUT)
5
4
MISO
(INPUT)
D7-IN
7
D6-IN
D0-IN
6
MOSI
(OUTPUT)
D7-OUT
11
D6-OUT
D0-OUT
10
VR000108
Note:
1) Measurement points are V , V , V and V in the SPI timing diagram.
OL OH
IL
IH
113/125
ST72334J/N, ST72314J/N, ST72124J
MEMORY AND PERIPHERAL CHARACTERISTICS (Cont’d)
Measurement points are V , V , V and V in the SPI Timing Diagram
OL
OH
IL
IH
Figure 63. SPI Slave Timing Diagram CPHA=0, CPOL=0 1)
SS
(INPUT)
2
1
12
3
13
11
SCK
(INPUT)
4
5
MISO HIGH-Z
D7-OUT
D6-OUT
D6-IN
D0-OUT
D0-IN
(OUTPUT)
8
10
9
MOSI
(INPUT)
D7-IN
7
6
VR000113
Figure 64. SPI Slave Timing Diagram CPHA=0, CPOL=1 1)
SS
(INPUT)
2
1
13
12
11
3
SCK
(INPUT)
5
4
MISO
HIGH-Z
8
D7-OUT
D6-OUT
D6-IN
D0-OUT
D0-IN
(OUTPUT)
10
9
MOSI
(INPUT)
D7-IN
7
6
VR000114
Figure 65. SPI Slave Timing Diagram CPHA=1, CPOL=0 1)
SS
(INPUT)
2
1
13
12
3
SCK
(INPUT)
4
5
HIGH-Z
8
MISO
D7-OUT
D6-OUT
D6-IN
D0-OUT
(OUTPUT)
11
9
10
MOSI
(INPUT)
D7-IN
D0-IN
7
6
VR000111
Figure 66. SPI Slave Timing Diagram CPHA=1, CPOL=1 1)
SS
(INPUT)
2
1
12
13
3
SCK
(INPUT)
5
4
HIGH-Z
8
MISO
D7-OUT
D6-OUT
D6-IN
D0-OUT
(OUTPUT)
11
10
9
MOSI
(INPUT)
D7-IN
D0-IN
6
7
VR000112
Note:
1) Measurement points are V , V , V and V in the SPI timing diagram.
OL OH
IL
IH
114/125
ST72334J/N, ST72314J/N, ST72124J
MEMORY AND PERIPHERAL CHARACTERISTICS (Cont’d)
SCI Serial Communication Interface
1)
Symbol
Parameter
Conditions
Standard Mode
Typ
Unit
TR (resp.RR)=64, PR=13
TR (resp.RR)=16, PR=13
TR (resp.RR)= 8, PR=13
TR (resp.RR)= 4, PR=13
TR (resp.RR)= 2, PR=13
TR (resp.RR)= 8, PR= 3
TR (resp.RR)= 1, PR=13
~300.48
~1201.92
~2403.84
~4807.69
~9615.38
~10416.67
~19230,77
Communication frequency
(precision vs. standard ~0.16%)
f
or f
f =8MHz
CPU
Hz
Tx
Rx
Extended Mode
ETPR (resp.ERPR) = 13
~38461.54
See “STANDARD I/O PORT PINS” description for more details.
Note:
1) Unless otherwise specified, typical data are based on T =25°C and V -V =5V. They are given only as design guide-
A
DD SS
lines and are not tested.
115/125
ST72334J/N, ST72314J/N, ST72124J
MEMORY AND PERIPHERAL CHARACTERISTICS (Cont’d)
ADC Analog to Digital Converter (8-bit)
1)
Symbol
Parameter
Conditions
=V =5V
DDA
Min
Typ
Max
Unit
2)
f
Analog control frequency
V
4
MHz
ADC
DD
4)
|TUE|
OE
Total unadjusted error
1
4)
Offset error
-0.5
-0.5
0.5
0.5
0.5
0.5
3)
T =25°C,V =V =5V,
DDA
fCPU=8MHz,fADC=4MHz
4)
A
DD
GE
Gain Error
LSB
4)
|DLE|
|ILE|
Differential linearity error
4)
Integral linearity error
V
Conversion range voltage
V
V
V
mA
µs
µs
AIN
ADC
STAB
SSA
DDA
I
t
A/D conversion supply current
Stabilization time after ADC enable
1
1
fCPU=8MHz, fADC=4MHz
=V =5V
1
4
t
t
Sample capacitor loading time
LOAD
CONV
V
1/f
DD
DDA
ADC
2
8
µs
Hold conversion time
External input resistor
1/f
ADC
2)
R
15
kΩ
AIN
R
C
Internal input resistor
Sample capacitor
1.5
6
kΩ
ADC
pF
SAMPLE
Notes:
1) Unless otherwise specified, typical data are based on T =25°C and V -V =5V. They are given only as design guide-
A
DD SS
lines and are not tested.
2) Data based on characterization results, not tested in production.
3) Tested in production at T =25°C, characterized over the whole temperature range.
A
4) ADC Accuracy vs. Negative Injection Current:
For I =0.8mA, the typical leakage induced inside the die is 1.6µA and the effect on the ADC accuracy is a loss of 1 LSB
INJ-
for each 10KΩ increase of the external analog source impedance. This effect on the ADC accuracy has been observed
under worst-case conditions for injection:
- negative injection
- injection to an Input with analog capability, adjacent to the enabled Analog Input
- at 5V V supply, and worst case temperature.
DD
Digital Result ADCDR
GE
(1) Example of an actual transfer curve
255
(2) The ideal transfer curve
V
– V
254
253
(3) End point correlation line
DDA
SSA
1LSB
= ----------------------------------------
ideal
256
(2)
TUE=Total Unadjusted Error: maximum deviation
between the actual and the ideal transfer curves.
OE=Offset Error: deviation between the first actual
transition and the first ideal one.
(3)
TUE
7
6
5
4
3
2
1
(1)
GE=Gain Error: deviation between the last ideal
transition and the last actual one.
ILE
OE
DLE=Differential Linearity Error: maximum devia-
tion between actual steps and the ideal one.
ILE=Integral Linearity Error: maximum deviation
between any actual transition and the end point
correlation line.
DLE
1 LSB (ideal)
V
(LSB
)
in
ideal
0
1
2
3
4
5
6
7
253 254 255 256
V
V
DDA
SSA
116/125
ST72334J/N, ST72314J/N, ST72124J
9 GENERAL INFORMATION
9.1 PACKAGES
9.1.1 Package Mechanical Data
Figure 67. 64-Pin Thin Quad Flat Package
mm
inches
Dim
Min Typ Max Min Typ Max
A
1.60
0.063
0.006
A1 0.05
0.15 0.002
A2 1.35 1.40 1.45 0.053 0.055 0.057
B
C
0.30 0.37 0.45 0.012 0.015 0.018
0.09
0.20 0.004
0.008
D
16.00
14.00
12.00
16.00
14.00
12.00
0.80
0.630
0.551
0.472
0.630
0.551
0.472
0.031
D1
D3
E
E1
E3
e
K
0°
3.5°
7°
L
0.45 0.60 0.75 0.018 0.024 0.030
L1
1.00
0.039
L1
L
Number of Pins
ND 16 NE
N
64
16
K
Figure 68. 56-Pin Shrink Plastic Dual In-Line Package, 600-mil Width
mm
inches
Dim.
A
Min Typ Max Min Typ Max
6.35
0.250
A1 0.38
0.015
A2 3.18
4.95 0.125
0.195
b
0.41
0.89
0.016
0.035
b2
C
D
E
0.20
0.38 0.008
53.21 1.980
0.015
2.095
50.29
15.01
0.591
E1 12.32
14.73 0.485
0.580
e
1.78
0.070
0.600
eA
eB
15.24
17.78
0.700
0.200
L
2.92
5.08 0.115
PDIP56S
Number of Pins
N
56
117/125
ST72334J/N, ST72314J/N, ST72124J
PACKAGES (Cont’d)
Figure 69. 44-Pin Thin Quad Flat Package
mm
inches
Dim
Min Typ Max Min Typ Max
A
1.60
0.063
0.006
A1 0.05
0.15 0.002
A2 1.35 1.40 1.45 0.053 0.055 0.057
b
c
0.30 0.37 0.45 0.012 0.015 0.018
0.09
0.20 0.004
0.008
b
D
12.00
10.00
8.00
0.472
0.394
0.315
0.472
0.394
0.315
0.031
D1
D3
E
12.00
10.00
8.00
E1
E3
e
c
0.80
K
0° 3.5°
7°
L
0.45 0.60 0.75 0.018 0.024 0.030
1.00 0.039
Number of Pins
44
L1
L1
L
N
K
Figure 70. 42-Pin Shrink Plastic Dual In-Line Package, 600-mil Width
mm
Min Typ Max Min Typ Max
5.08 0.200
inches
Dim.
A
A1 0.51
A2 3.05 3.81 4.57 0.120 0.150 0.180
0.020
b
b2
C
0.46 0.56
1.02 1.14
0.018 0.022
0.040 0.045
0.23 0.25 0.38 0.009 0.010 0.015
36.58 36.83 37.08 1.440 1.450 1.460
D
E
15.24
16.00 0.600
0.630
E1 12.70 13.72 14.48 0.500 0.540 0.570
e
1.78
0.070
0.600
eA
15.24
eB
18.54
0.730
0.060
eC 0.00
1.52 0.000
PDIP42S
L
2.54 3.30 3.56 0.100 0.130 0.140
Number of Pins
N
42
118/125
ST72334J/N, ST72314J/N, ST72124J
PACKAGES (Cont’d)
9.1.2 User-supplied TQFP64 Adaptor / Socket
■ Direct TQFP64 soldering
■ YAMAICHI
IC149-064-008-S5*
socket
To solder the TQFP64 device directly on the appli-
cation board, or to solder a socket for connecting
the emulator probe, the application board should
provide the footprint described in Figure 71. This
footprint allows both configurations:
soldering to plug either the emulator probe or an
adaptor board with an TQFP64 clamshell
socket.
* Not compatible with TQFP64 package.
Figure 71. TQFP64 Device And Emulator Probe Compatible Footprint
SK
E
mm
inches
Dim
Min Typ Max Min
Typ Max
E1
E3
B
E
0.35 0.45 0.50 0.014 0.018 0.020
20.80 0.819
E1
14.00
0.551
e
E3 11.90 12.00 12.10 0.468 0.472 0.476
e
0.75 0.80 0.85 0.029 0.031 0.033
26 1.023
Number of Pins
64 (4x16)
B
SOCKET
SK*
DETAIL
N
* SK: Plastic socket overall dimensions.
Table 22. Suggested List of TQFP64 Socket Types
Package / Probe
TQFP64
EMU PROBE
Adaptor / Socket Reference
Socket type
ENPLAS
OTQ-64-0.8-02
Open Top
YAMAICHI
YAMAICHI
IC51-0644-1240.KS-14584
Clamshell
SMC
IC149-064-008-S5
119/125
ST72334J/N, ST72314J/N, ST72124J
PACKAGES (Cont’d)
9.1.3 User-supplied TQFP44 Adaptor / Socket
■ Direct TQFP44 soldering
■ YAMAICHI IC149-044-*52-S5 socket soldering
to plug either the emulator probe or an adaptor
board with an TQFP44 clamshell socket.
To solder the TQFP44 device directly on the appli-
cation board, or to solder a socket for connecting
the emulator probe, the application board should
provide the footprint described in Figure 72. This
footprint allows both configurations:
Figure 72. TQFP44 Device And Emulator Probe Compatible Footprint
SK
E
mm
inches
Dim
Min Typ Max Min
Typ Max
E1
E3
B
E
0.35 0.45 0.50 0.014 0.018 0.020
13.40 0.527
E1
10.00
0.394
e
E3 7.95 8.00 8.05 0.313 0.315 0.317
e
0.75 0.80 0.85 0.029 0.031 0.033
24.2 0.953
Number of Pins
44 (4x11)
B
SOCKET
SK*
DETAIL
N
* SK: Plastic socket overall dimensions.
Table 23. Suggested List of TQFP44 Socket Types
Package / Probe
TQFP44
Adaptor / Socket Reference
OTQ-44-0.8-04
Socket type
Open Top
ENPLAS
YAMAICHI
IC51-0444-467-KS-11787
Clamshell
TQFP44
EMU PROBE
YAMAICHI
IC149-044-*52-S5
SMC
120/125
ST72334J/N, ST72314J/N, ST72124J
9.2 DEVICE CONFIGURATION AND ORDERING
INFORMATION
USER OPTION BYTE 2
7
0
Each device is available for production in user pro-
grammable versions (FLASH) as well as in factory
coded versions (ROM).
WDG WDG
HALT SW
CFC OSC2 OSC1 OSC0 LVD1 LVD0
FLASH devices are shipped to customers with a
default content (FFh), while ROM factory coded
parts contain the code supplied by the customer.
This implies that FLASH devices have to be con-
figured by the customer using the Option Bytes
while the ROM devices are factory-configured.
Bit 7 = CFC Clock filter control on/off
This option bit enables or disables the clock filter
(CF) features.
0: Clock filter enabled
1: Clock filter disabled
9.2.1 Option Bytes
The two Option Bytes allow the hardware configu-
ration of the microcontroller to be selected.
The Option Bytes have no address in the memory
map and can be accessed only in programming
Bit 6:4 = OSC[2:0] Oscillator selection
These three option bits can be used to select the
main oscillator as shown in Table 24.
Table 24. Main Oscillator Configuration
mode (for example using
a standard ST7
Selected Oscillator
External Clock (Stand-by)
Internal RC
OSC2 OSC1 OSC0
4programming tool). The default contents of the
FLASH is fixed to FFh. This means that all the op-
tions have “1” as their default value.
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
In masked ROM devices, the Option Bytes are
fixed in hardware by the ROM code.
External RC
USER OPTION BYTE 1
Low Speed Resonator
Medium-low Speed Resonator
Medium-high Speed Resonator
High Speed Resonator
7
1
0
1
1
1
1
1
56/42 FMP
Bit 3:2 = LVD[1:0] Low voltage detection selection
These option bits enable the LVD block with a se-
lected threshold as shown in Table 25.
Bit 7:2 = Reserved, must always be 1.
Table 25. LVD Threshold Configuration
Bit 1 = 56/42 Package configuration.
This option bit allows to configure the device ac-
cording to the package.
0: 42 and 44 pin.
1: 56 and 64 pin.
Configuration
LVD1 LVD0
LVD Off
1
1
0
0
1
0
1
0
Highest Voltage Threshold (V ~5V)
DD
Medium Voltage Threshold (f
≤16MHz)
OSC
OSC
Bit 0 = FMP Full memory protection.
Lowest Voltage Threshold (f
≤8MHz)
This option bit enables or disables external access
to the internal program memory (read-out protec-
tion). Clearing this bit causes the erasing (to 00h)
of the whole memory (including the option byte).
0: Program memory not read-out protected
1: Program memory read-out protected
Bit 1 = WDG HALT Watchdog and halt mode
This option bit determines if a RESET is generated
when entering HALT mode while the Watchdog is
active.
0: No Reset generation when entering Halt mode
1: Reset generation when entering Halt mode
Bit 0 = WDG SW Hardware or software watchdog
This option bit selects the watchdog type.
0: Hardware (watchdog always enabled)
1: Software (watchdog to be enabled by software)
121/125
ST72334J/N, ST72314J/N, ST72124J
DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d)
9.2.2 Transfer Of Customer Code
The selected options are communicated to STMi-
croelectronics using the correctly completed OP-
TION LIST appended.
Customer code is made up of the ROM contents
and the list of the selected options (if any). The
ROM contents are to be sent on diskette, or by
electronic means, with the hexadecimal file in .S19
format generated by the development tool. All un-
used bytes must be set to FFh.
The STMicroelectronics Sales Organization will be
pleased to provide detailed information on con-
tractual points.
Figure 73. ROM Factory Coded Device Types
TEMP.
PACKAGE RANGE
/ XXX
DEVICE
Code name (defined by STMicroelectronics)
1 = standard 0 to +70 °C
6 = industrial -40 to +85 °C
7 = automotive -40 to +125 °C
3 = automotive -40 to +125 °C
B = Plastic DIP
T = Plastic TQFP
ST72334J2, ST72334J4, ST72334N2, ST72334N4,
ST72314J2, ST72314J4, ST72314N2, ST72314N4,
ST72124J2
Figure 74. FLASH User Programmable Device Types
TEMP.
PACKAGE RANGE XXX
DEVICE
Code name (defined by STMicroelectronics)
1 = standard 0 to +70 °C
6 = industrial -40 to +85 °C
7 = automotive -40 to +125 °C
3 = automotive -40 to +125 °C
B = Plastic DIP
T = Plastic TQFP
ST72C334J2, ST72C334J4, ST72C334N2, ST72C334N4,
ST72C314J2, ST72C314J4, ST72C314N2, ST72C314N4,
ST72C124J2
122/125
ST72334J/N, ST72314J/N, ST72124J
MICROCONTROLLER OPTION LIST
Customer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address
Contact
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Phone No . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
STMicroelectronics references
Device:
[ ] ST72334J2
[ ] ST72334J4
[ ] ST72334N2
[ ] ST72334N4
[ ] ST72314J2
[ ] ST72314J4
[ ] ST72314N2
[ ] ST72314N4
[ ] ST72124J2
Package:
[ ] TQFP64
[ ] TQFP44
[ ] SDIP56
[ ] SDIP42
Temperature Range:
[ ] 0°C to + 70°C
[ ] - 40°C to + 85°C
[ ] - 40°C to + 125°C
Clock Source Selection:
[ ] Resonator:
[ ] LP: Low power resonator (1 to 2 MHz)
[ ] MP: Medium power resonator (2 to 4 MHz)
[ ] MS: Medium speed resonator (4 to 8 MHz)
[ ] HS: High speed resonator (8 to 16 MHz)
[ ] RC Network: [ ] Internal
[ ] External
[ ] External Clock
Clock Security System:
[ ] Disabled
[ ] Enabled
Watchdog Selection:
[ ] Software Activation
[ ] Hardware Activation
Halt when Watchdog on:
[ ] Reset
[ ] No reset
Readout Protection:
LVD Reset
[ ] Disabled
[ ] Enabled
[ ] Disabled
[ ] Enabled: [ ] Highest threshold (4.30V/4.05V)
[ ] Medium threshold (3.90V/3.65V)
[ ] Lowest threshold (3.35V/3.10V)
Comments : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply Operating Range in the application: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Notes
Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Date . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
123/125
ST72334J/N, ST72314J/N, ST72124J
10 SUMMARY OF CHANGES
Description of the changes between the current release of the specification and the previous one.
Revision
Main changes
Date
New chapter to compare ST72334 versus ST72331 (section 2.1 on page 6)
Correction of the address of the CRSR register to 2Bh instead of 25h (Table 4 page 33)
Correction of port A pin name column in Table 9 page 44 (PA2:0 instead of PA3:0)
Correction of MISCR2 register description (section 6.2.3 on page 48)
Correction of the FLASH and data EEPROM programming time (section 8.7 on page 111)
Correction of the TQFP44 socket proposal (Table 23 page 120)
1.0
Sept-99
More information on the FMP option bit (section 9.2.1 on page 121)
Added .S19 format in transfer of Code (section 9.2.2 on page 122)
Correction of the microcontroller option list (section 9.2.2 on page 122)
History page added (section 10 on page 124)
124/125
ST72334J/N, ST72314J/N, ST72124J
Notes:
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of useof such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
1999 STMicroelectronics - All Rights Reserved.
Purchase of I2C Components by STMicroelectronics conveys a license under the Philips I2C Patent. Rights to use these components in an
I2C system is granted provided that the system conforms to the I2C Standard Specification as defined by Philips.
STMicroelectronics Group of Companies
Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain
Sweden - Switzerland - United Kingdom - U.S.A.
http://www.st.com
125/125
相关型号：
ST72C314J4B7XXX
8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACESWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 211
-
STMICROELECTR
ST72C314J4T1
8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACESWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 211
-
STMICROELECTR
ST72C314J4T1XXX
8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACESWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 211
-
STMICROELECTR
ST72C314J4T3
8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACESWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 211
-
STMICROELECTR
ST72C314J4T3XXX
8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACESWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 211
-
STMICROELECTR
ST72C314J4T6
8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACESWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 211
-
STMICROELECTR
ST72C314J4T6XXX
8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACESWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 211
-
STMICROELECTR
ST72C314J4T7
8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACESWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 211
-
STMICROELECTR
ST72C314J4T7XXX
8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACESWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 211
-
STMICROELECTR
ST72C314J4TA
8-bit MCU for automotive with single voltage Flash/ROM memory, ADC, 16-bit timers, SPI, SCI interfacesWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 211
-
STMICROELECTR
©2020 ICPDF网 联系我们和版权申明