ST72F264G1M6 [STMICROELECTRONICS]
8-BIT MCU WITH FLASH OR ROM MEMORY, ADC, TWO 16-BIT TIMERS, I2C, SPI, SCI INTERFACES; 8位MCU的Flash或ROM存储器， ADC ，两个16位定时器， I2C ， SPI ， SCI INTERFACES
| 型号： | ST72F264G1M6 |
| 厂家： | 
ST |
| 描述： | 8-BIT MCU WITH FLASH OR ROM MEMORY, ADC, TWO 16-BIT TIMERS, I2C, SPI, SCI INTERFACES |
| 文件： | 总171页 (文件大小：2059K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ST72260G, ST72262G,
ST72264G
8-BIT MCU WITH FLASH OR ROM MEMORY,
2
ADC, TWO 16-BIT TIMERS, I C, SPI, SCI INTERFACES
■ Memories
– 4 K or 8 Kbytes Program memory: ROM or
Single voltage extended Flash (XFlash) with
read-out protection write protection and In-
Circuit Programming and In-Application Pro-
gramming (ICP and IAP). 10K write/erase cy-
cles guaranteed, data retention: 20 years at
55°C.
– 256 bytes RAM
■ Clock, Reset and Supply Management
SDIP32
– Enhanced reset system
– Enhanced low voltage supply supervisor
(LVD) with 3 programmable levels and auxil-
iary voltage detector (AVD) with interrupt ca-
pability for implementing safe power-down
procedures
– Clock sources: crystal/ceramic resonator os-
cillators, internal RC oscillator, clock security
system and bypass for external clock
SO28
LFBGA 6x6mm
– Two 16-bit timers with: 2 input captures, 2 out-
put compares, external clock input on one tim-
er, PWM and Pulse generator modes
– PLL for 2x frequency multiplication
– Clock-out capability
– 4 Power Saving Modes: Halt, Active Halt,Wait
and Slow
■ 3 Communications Interfaces
– SPI synchronous serial interface
■ Interrupt Management
2
– I C multimaster interface
– Nested interrupt controller
– 10 interrupt vectors plus TRAP and RESET
– 22 external interrupt lines (on 2 vectors)
■ 22 I/O Ports
– SCI asynchronous serial interface (LIN com-
patible)
■ 1 Analog peripheral
– 10-bit ADC with 6 input channels
■ Instruction Set
– 22 multifunctional bidirectional I/O lines
– 20 alternate function lines
– 8 high sink outputs
– 8-bit data manipulation
– 63 basic instructions
– 17 main addressing modes
– 8 x 8 unsigned multiply instruction
■ Development Tools
■ 4 Timers
– Main Clock Controller with Real time base and
Clock-out capabilities
– Configurable watchdog timer
– Full hardware/software development package
Device Summary
Features
ST72260G1
ST72262G1
ST72262G2
ST72264G1
ST72264G2
Program memory - bytes
RAM (stack) - bytes
4K
4K
8K
4K
8K
256 (128)
Watchdog timer,
RTC,
Two16-bit timers,
SPI
Watchdog timer, RTC
Two 16-bit timers,
SPI, ADC
Watchdog timer, RTC
Peripherals
Two 16-bit timers,
2
SPI, SCI, I C, ADC
Operating Supply
CPU Frequency
Operating Temperature
Packages
2.4 V to 5.5 V
Up to 8 MHz (with oscillator up to 16 MHz) PLL 4/8 Mhz
-40° C to +85° C
0° C to +70° C
LFBGA
SO28 / SDIP32
Rev. 1.7
August 2003
1/171
1
Table of Contents
ST72260G, ST72262G,
ST72264G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.3 PROGRAMMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.4 ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.5 MEMORY PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.6 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.1 PHASE LOCKED LOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.2 MULTI-OSCILLATOR (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.3 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.4 SYSTEM INTEGRITY MANAGEMENT (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . 28
7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.2 MASKING AND PROCESSING FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.3 INTERRUPTS AND LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.4 CONCURRENT & NESTED MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.5 INTERRUPT REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
8 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
8.2 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
8.3 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8.4 ACTIVE-HALT AND HALT MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
8.5 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
9 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
9.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
9.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
9.4 UNUSED I/O PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
9.5 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
9.6 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
9.7 DEVICE-SPECIFIC I/O PORT CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
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Table of Contents
9.8 I/O PORT REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
10 MISCELLANEOUS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
10.1 I/O PORT INTERRUPT SENSITIVITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
10.2 I/O PORT ALTERNATE FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
10.3 MISCELLANEOUS REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
11 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
11.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
11.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (MCC/RTC) . . . . . . . . . . . . . 53
11.3 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
11.4 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
11.5 SERIAL COMMUNICATIONS INTERFACE (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
11.6 I2C BUS INTERFACE (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
11.7 10-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
12 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
12.1 CPU ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
12.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
13 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
13.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
13.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
13.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
13.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
13.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
13.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
13.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
13.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
13.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
13.10 TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
13.11 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 149
13.12 10-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
14 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
14.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
14.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
14.3 SOLDERING AND GLUEABILITY INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
15 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . 157
15.1 OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
15.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . 159
15.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
15.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
16 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
ERRATA SHEET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
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3
ST72260G, ST72262G, ST72264G
17 SILICON IDENTIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
18 REFERENCE SPECIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
19 SILICON LIMITATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
19.1 EXECUTION OF BTJX INSTRUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
19.2 I/O PORT B AND C CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
19.3 16-BIT TIMER PWM MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
19.4 SPI MULTIMASTER MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
19.5 MINIMUM OPERATING VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
19.6 CSS FUNCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
19.7 INTERNAL AND EXTERNAL RC OSCILLATOR WITH LVD . . . . . . . . . . . . . . . . . . . . 167
19.8 EXTERNAL CLOCK WITH PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
19.9 HALT MODE POWER CONSUMPTION WITH ADC ON . . . . . . . . . . . . . . . . . . . . . . . 168
19.10 ACTIVE HALT WAKE-UP BY EXTERNAL INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . 168
19.11 A/D CONVERTER ACCURACY FOR FIRST CONVERSION . . . . . . . . . . . . . . . . . . . . 168
19.12 NEGATIVE INJECTION IMPACT ON ADC ACCURACY . . . . . . . . . . . . . . . . . . . . . . . 168
19.13 ADC CONVERSION SPURIOUS RESULTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
19.14 FUNCTIONAL EMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
20 DEVICE MARKING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
21 ERRATA SHEET REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
To obtain the most recent version of this datasheet,
please check at www.st.com>products>technical literature>datasheet
Please note that an errata sheet can be found at the end of this document on page 166.
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ST72260G, ST72262G, ST72264G
1 INTRODUCTION
The ST72260G, ST72262G and ST72264G devic-
es are members of the ST7 microcontroller family.
They can be grouped as follows :
with byte-by-byte In-Circuit Programming (ICP)
capabilities.
Under software control, all devices can be placed
in WAIT, SLOW, Active-HALT or HALT mode, re-
ducing power consumption when the application is
in idle or stand-by state.
– ST72264G devices are designed for mid-range
2
applications with ADC, I C and SCI interface ca-
pabilities.
– ST72262G devices target the same range of ap-
plications but without I C interface or SCI.
The enhanced instruction set and addressing
modes of the ST7 offer both power and flexibility to
software developers, enabling the design of highly
efficient and compact application code. In addition
to standard 8-bit data management, all ST7 micro-
controllers feature true bit manipulation, 8x8 un-
signed multiplication and indirect addressing
modes.
2
– ST72260G devices are for applications that do
2
not need ADC, I C peripherals or SCI.
All devices are based on a common industry-
standard 8-bit core, featuring an enhanced instruc-
tion set.
The ST72F260G, ST72F262G, and ST72F264G
versions feature single-voltage FLASH memory
For easy reference, all parametric data is located
in Section 13 on page 122.
Figure 1. General Block Diagram
Internal
CLOCK
OSC1
OSC2
2
I C*
MULTI OSC
+
CLOCK FILTER
SCI*
PA7:0
(8 bits)
MCC/RTC
LVD
PORT A
ICD
V
DD
POWER
SUPPLY
V
SS
SPI
PB7:0
(8 bits)
RESET
CONTROL
PORT B
16-BIT TIMER A
PORT C
8-BIT CORE
ALU
PROGRAM
MEMORY
PC5:0
(6 bits)
(4 or 8K Bytes)
10-BIT ADC*
16-BIT TIMER B
WATCHDOG
RAM
(256 Bytes)
*Not available on some devices, see device summary on page 1.
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ST72260G, ST72262G, ST72264G
2 PIN DESCRIPTION
Figure 2. 28-Pin SO Package Pinout
RESET
V
V
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
DD
OSC1
OSC2
2
SS
ICCSEL
3
SS/PB7
SCK/PB6
PA0 (HS)/ICCCLK
PA1 (HS)/ICCDATA
PA2 (HS)
4
5
MISO/PB5
6
MOSI/PB4
PA3 (HS)
7
ei1
ei0
3
OCMP2_A/PB3
PA4 (HS)/SCLI
8
3
ICAP2_A/PB2
OCMP1_A/PB1
ICAP1_A/PB0
9
PA5(HS)/RDI
3
PA6 (HS)/SDAI
10
11
3
PA7 (HS)/TDO
2
AIN5/EXTCLK_A/PC5
PC0/ICAP1_B/AIN0
PC1/OCMP1_B/AIN1
12
13
14
2
2
AIN4 /OCMP2_B/PC4
1
ei0 or ei1
2
2
AIN3 /ICAP2_B/PC3
PC2/MCO/AIN2
(HS) 20mA high sink capability
eiX associated external interrupt vector
1
Configurable by option byte
2
Alternate function not available on ST72260
Alternate function not available on ST72260 and ST72262
3
Figure 3. 32-Pin SDIP Package Pinout
V
V
RESET
1
DD
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OSC1
OSC2
2
SS
3
ICCSEL
PA0 (HS)/ICCCLK
PA1 (HS)/ICCDATA
PA2 (HS)
SS/PB7
SCK/PB6
MISO/PB5
MOSI/PB4
NC
4
5
ei1
ei0
6
PA3 (HS)
7
8
NC
NC
NC
OCMP2_A/PB3
ICAP2_A/PB2
OCMP1_A/PB1
ICAP1_A/PB0
9
3
PA4 (HS)/SCLI
10
11
12
13
14
15
16
3
PA5 (HS)/RDI
ei1
ei0
3
PA6 (HSI/SDAI
3
PA7 (HS)/TDO
2
2
PC0/ICAP1_B/AIN0
AIN5 /EXTCLK_A/PC5
2
2
1
PC1/OCMP1_B/AIN1
AIN4 /OCMP2_B/PC4
ei0 or ei1
2
2
PC2/MCO/AIN2
AIN3 /ICAP2_B/PC3
1
2
3
Configurable by option byte
Alternate function not available on ST72260
Alternate function not available on ST72260 and ST72262
(HS) 20mA high sink capability
eiX associated external interrupt vector
6/171
ST72260G, ST72262G, ST72264G
Figure 4. TFBGA Package Pinout (view through package)
1
2
3
4
5
6
A
B
C
D
E
F
7/171
ST72260G, ST72262G, ST72264G
PIN DESCRIPTION (Cont’d)
For external pin connection guidelines, refer to Section 13 "ELECTRICAL CHARACTERISTICS" on page
122.
Legend / Abbreviations for Table 1:
Type:
I = input, O = output, S = supply
A = Dedicated analog input
Input level:
In/Output level: C = CMOS 0.3 V /0.7 V with input trigger
T
DD
DD
Output level:
Port and control configuration:
HS = 20 mA high sink (on N-buffer only)
1)
– Input:
float = floating, wpu = weak pull-up, int = interrupt , ana = analog
2)
– Output:
OD = open drain , PP = push-pull
Refer to Section 9 "I/O PORTS" on page 38 for more details on the software configuration of the I/O ports.
The RESET configuration of each pin is shown in bold. This configuration is valid as long as the device is
in reset state.
Table 1. Device Pin Description
Pin n°
Level
Port / Control
Main
Function
(after
Input
Output
Pin Name
Alternate Function
reset)
Top priority non maskable interrupt (ac-
tive low)
1
2
3
1
2
3
A3 RESET
I/O C
X
X
T
External clock input or Resonator oscilla-
tor inverter input or resistor input for RC
oscillator
3)
3)
C4 OSC1
B3 OSC2
I
Resonator oscillator inverter output or ca-
pacitor input for RC oscillator
O
4
5
6
7
8
9
4
5
6
7
A2 PB7/SS
A1 PB6/SCK
B1 PB5/MISO
B2 PB4/MOSI
C1 NC
I/O
I/O
I/O
I/O
C
X
X
X
X
ei1
ei1
ei1
ei1
X
X
X
X
X
X
X
X
Port B7 SPI Slave Select (active low)
Port B6 SPI Serial Clock
T
T
T
T
C
C
C
Port B5 SPI Master In/ Slave Out Data
Port B4 SPI Master Out / Slave In Data
C2 NC
Not Connected
D1 NC
10
11
8
9
C3 PB3/OCMP2_A
D2 PB2/ICAP2_A
I/O
I/O
I/O
I/O
C
C
C
C
X
X
X
X
ei1
ei1
ei1
ei1
X
X
X
X
X
Port B3 Timer A Output Compare 2
T
T
T
T
X
X
X
Port B2 Timer A Input Capture 2
Port B1 Timer A Output Compare 1
Port B0 Timer A Input Capture 1
12 10 E1 PB1 /OCMP1_A
13 11 F1 PB0 /ICAP1_A
Timer A Input Clock or ADC
Port C5
14 12 F2 PC5/EXTCLK_A/AIN5 I/O
15 13 E2 PC4/OCMP2_B/AIN4 I/O
C
C
C
X
X
X
ei0/ei1
ei0/ei1
ei0/ei1
X
X
X
X
X
X
X
X
X
T
T
T
Analog Input 5
Timer B Output Compare 2 or
Port C4
ADC Analog Input 4
Timer B Input Capture 2 or
Port C3
16 14 F3 PC3/ ICAP2_B/AIN3
I/O
ADC Analog Input 3
8/171
ST72260G, ST72262G, ST72264G
Pin n°
Level
Port / Control
Main
Function
Input
Output
Pin Name
Alternate Function
(after
reset)
Main clock output (f
ADC Analog Input 2
) or
CPU
17 15 E3 PC2/MCO/AIN2
I/O
C
C
C
X
X
X
ei0/ei1
ei0/ei1
ei0/ei1
X
X
X
X
X
X
X
X
Port C2
Port C1
Port C0
T
T
T
Timer B Output Compare 1 or
ADC Analog Input 1
18 16 F4 PC1/OCMP1_B/AIN1 I/O
Timer B Input Capture 1 or
ADC Analog Input 0
19 17 D3 PC0/ICAP1_B/AIN0
I/O
X
X
20 18 E4 PA7/TDO
21 19 F5 PA6/SDAI
22 20 F6 PA5 /RDI
23 21 E6 PA4/SCLI
I/O C HS
X
X
X
X
ei0
ei0
ei0
ei0
X
T
X
T
Port A7 SCI output
T
2
I/O C HS
Port A6 I C DATA
T
I/O C HS
X
Port A5 SCI input
T
2
I/O C HS
Port A4 I C CLOCK
T
24
25
E5 NC
D6 NC
D5 NC
Not Connected
26 22 C6 PA3
27 23 D4 PA2
C5 NC
I/O C HS
X
X
ei0
ei0
X
X
X
X
Port A3
Port A2
T
I/O C HS
T
Not Connected
B6 NC
28 24 A6 PA1/ICCDATA
I/O C HS
X
X
X
ei0
ei0
X
X
X
Port A1 In Circuit Communication Data
T
In Circuit Communication
Clock
29 25 A5 PA0/ICCCLK
30 26 B5 ICCSEL
I/O C HS
X
Port A0
T
I
C
ICC mode pin, must be tied low
Ground
T
31 27 A4 V
32 28 B4 V
S
S
SS
DD
Main power supply
Notes:
1. In the interrupt input column, “eiX” defines the associated external interrupt vector. If the weak pull-up
column (wpu) is merged with the interrupt column (int), then the I/O configuration is a pull-up interrupt in-
put, otherwise the configuration is a floating interrupt input. Port C is mapped to ei0 or ei1 by option byte.
2. In the open drain output column, “T” defines a true open drain I/O (P-Buffer and protection diode to V
are not implemented). See Section 9 "I/O PORTS" on page 38 for more details.
DD
3. OSC1 and OSC2 pins connect a crystal or ceramic resonator, an external RC, or an external source to
the on-chip oscillator see Section 2 "PIN DESCRIPTION" on page 6 and Section 6.2 "MULTI-OSCILLA-
TOR (MO)" on page 21 for more details.
9/171
ST72260G, ST72262G, ST72264G
3 REGISTER & MEMORY MAP
As shown in Figure 5, the MCU is capable of ad-
dressing 64K bytes of memories and I/O registers.
dressing space so the reset and interrupt vectors
are located in Sector 0 (F000h-FFFFh).
The available memory locations consist of 128
bytes of register location, 256 bytes of RAM and
up to 8 Kbytes of user program memory. The RAM
space includes up to 128 bytes for the stack from
0100h to 017Fh.
The size of Flash Sector 0 and other device op-
tions are configurable by Option byte (refer to Sec-
tion 15.1 on page 157).
IMPORTANT: Memory locations marked as “Re-
served” must never be accessed. Accessing a re-
seved area can have unpredictable effects on the
device.
The highest address bytes contain the user reset
and interrupt vectors.
The Flash memory contains two sectors (see Fig-
ure 5) mapped in the upper part of the ST7 ad-
Figure 5. Memory Map
0000h
HW Registers
(see Table 2)
0080h
Short Addressing RAM
007Fh
0080h
Zero page
(128 Bytes)
00FFh
0100h
RAM
(256 Bytes)
Stack or
16-bit Addressing RAM
017Fh
0180h
(128 Bytes)
017Fh
8K FLASH
Reserved
PROGRAM MEMORY
E000h
DFFFh
E000h
4 Kbytes
SECTOR 1
EFFFh
Program Memory
F000h
FFFFh
4 Kbytes
SECTOR 0
(4K, 8 KBytes)
FFDFh
FFE0h
Interrupt & Reset Vectors
(see Table 5 on page 32)
FFFFh
10/171
ST72260G, ST72262G, ST72264G
Table 2. Hardware Register Map
Register
Reset
Status
Address
Block
Register Name
Remarks
Label
1)
2)
0000h
0001h
0002h
PCDR
PCDDR
PCOR
Port C Data Register
Port C Data Direction Register
Port C Option Register
xx000000h R/W
2)
2)
Port C
00h
00h
R/W
R/W
0003h
Reserved (1 Byte)
1)
0004h
0005h
0006h
PBDR
PBDDR
PBOR
Port B Data Register
Port B Data Direction Register
Port B Option Register
00h
R/W
R/W
R/W.
Port B
Port A
00h
00h
0007h
Reserved (1 Byte)
1)
R/W
R/W
0008h
0009h
000Ah
PADR
PADDR
PAOR
Port A Data Register
Port A Data Direction Register
Port A Option Register
00h
00h
00h
R/W
000Bh
to
Reserved (17 Bytes)
001Bh
001Ch
001Dh
001Eh
001Fh
ISPR0
ISPR1
ISPR2
ISPR3
Interrupt software priority register0
Interrupt software priority register1
Interrupt software priority register2
Interrupt software priority register3
FFh
FFh
FFh
FFh
R/W
R/W
R/W
R/W
ITC
SPI
0020h
MISCR1
Miscellanous register 1
00h
R/W
0021h
0022h
0023h
SPIDR
SPICR
SPICSR
SPI Data I/O Register
SPI Control Register
SPI Status Register
xxh
0xh
00h
R/W
R/W
R/W
0024h
0025h
0026h
0027h
WATCHDOG WDGCR
SICSR
Watchdog Control Register
7Fh
R/W
System Integrity Control / Status Register
Main Clock Control / Status Register
Reserved (1 Byte)
000x 000x R/W
MCC
MCCSR
00h
R/W
2
0028h
0029h
002Ah
002Bh
002Ch
002Dh
002Eh
I2CCR
I C Control Register
00h
00h
00h
00h
00h
40h
00h
R/W
2
I2CSR1
I2CSR2
I2CCCR
I2COAR1
I2COAR2
I2CDR
I C Status Register 1
Read Only
Read Only
R/W
R/W
R/W
2
I C Status Register 2
2
2
I C
I C Clock Control Register
2
I C Own Address Register 1
2
I C Own Address Register2
2
I C Data Register
R/W
002Fh
0030h
Reserved (2 Bytes)
11/171
ST72260G, ST72262G, ST72264G
Register
Label
Reset
Status
Address
Block
Register Name
Remarks
R/W
R/W
R/W
Read Only
Read Only
R/W
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
TACR2
TACR1
Timer A Control Register 2
Timer A Control Register 1
Timer A Control/Status Register
Timer A Input Capture 1 High Register
Timer A Input Capture 1 Low Register
Timer A Output Compare 1 High Register
Timer A Output Compare 1 Low Register
Timer A Counter High Register
00h
00h
xxh
xxh
xxh
80h
00h
FFh
FCh
FFh
FCh
xxh
xxh
80h
00h
TASCSR
TAIC1HR
TAIC1LR
TAOC1HR
TAOC1LR
TACHR
R/W
TIMER A
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
R/W
TACLR
Timer A Counter Low Register
TAACHR
TAACLR
TAIC2HR
TAIC2LR
TAOC2HR
TAOC2LR
Timer A Alternate Counter High Register
Timer A Alternate Counter Low Register
Timer A Input Capture 2 High Register
Timer A Input Capture 2 Low Register
Timer A Output Compare 2 High Register
Timer A Output Compare 2 Low Register
R/W
0040h
MISCR2
Miscellanous register 2
00h
R/W
0041h
0042h
0043h
0044h
0045h
0046h
0047h
0048h
0049h
004Ah
004Bh
004Ch
004Dh
004Eh
004Fh
TBCR2
TBCR1
Timer B Control Register 2
Timer B Control Register 1
Timer B Control/Status Register
Timer B Input Capture 1 High Register
Timer B Input Capture 1 Low Register
Timer B Output Compare 1 High Register
Timer B Output Compare 1 Low Register
Timer B Counter High Register
00h
00h
xxh
xxh
xxh
80h
00h
FFh
FCh
FFh
FCh
xxh
xxh
80h
00h
R/W
R/W
R/W
Read Only
Read Only
R/W
TBSCSR
TBIC1HR
TBIC1LR
TBOC1HR
TBOC1LR
TBCHR
R/W
TIMER B
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
R/W
TBCLR
Timer B Counter Low Register
TBACHR
TBACLR
TBIC2HR
TBIC2LR
TBOC2HR
TBOC2LR
Timer B Alternate Counter High Register
Timer B Alternate Counter Low Register
Timer B Input Capture 2 High Register
Timer B Input Capture 2 Low Register
Timer B Output Compare 2 High Register
Timer B Output Compare 2 Low Register
R/W
0050h
0051h
0052h
0053h
0054h
0055h
0056h
SCISR
SCIDR
SCI Status Register
SCI Data Register
SCI Baud Rate Register
SCI Control Register1
SCI Control Register2
SCI Extended Receive Prescaler Register
SCI Extended Transmit Prescaler Register
C0h
xxh
00h
Read Only
R/W
R/W
SCIBRR
SCICR1
SCICR2
SCIERPR
SCIETPR
SCI
x000 0000h R/W
00h
00h
00h
R/W
R/W
R/W
0057h
to
Reserved (24 Bytes)
006Eh
3)
006Fh
0070h
0071h
ADCDRL
ADCDRH
ADCCSR
Data Register Low
00h
00h
00h
Read Only
Read Only
R/W
3)
ADC
Data Register High
Control/Status Register
0072h
FLASH
FCSR
Flash Control Register
00h
R/W
0073h
to
Reserved (13 Bytes)
007Fh
12/171
ST72260G, ST72262G, ST72264G
Legend: x=Undefined, R/W=Read/Write
Notes:
1. The contents of the I/O port DR registers are readable only in output configuration. In input configura-
tion, the values of the I/O pins are returned instead of the DR register contents.
2. The bits associated with unavailable pins must always keep their reset value.
3. For compatibility with the ST72C254, the ADCDRL and ADCDRH data registers are located with the
LSB on the lower address (6Fh) and the MSB on the higher address (70h). As this scheme is not little En-
dian, the ADC data registers cannot be treated by C programs as an integer, but have to be treated as two
char registers.
13/171
ST72260G, ST72262G, ST72264G
board and while the application is running.
4.3.1 In-Circuit Programming (ICP)
4 FLASH PROGRAM MEMORY
ICP uses a protocol called ICC (In-Circuit Commu-
nication) which allows an ST7 plugged on a print-
ed circuit board (PCB) to communicate with an ex-
ternal programming device connected via cable.
ICP is performed in three steps:
4.1 Introduction
The ST7 single voltage extended Flash (XFlash) is
a non-volatile memory that can be electrically
erased and programmed either on a byte-by-byte
basis or up to 32 bytes in parallel.
Switch the ST7 to ICC mode (In-Circuit Communi-
cations). This is done by driving a specific signal
sequence on the ICCCLK/DATA pins while the
RESET pin is pulled low. When the ST7 enters
ICC mode, it fetches a specific RESET vector
which points to the ST7 System Memory contain-
ing the ICC protocol routine. This routine enables
the ST7 to receive bytes from the ICC interface.
The XFlash devices can be programmed off-board
(plugged in a programming tool) or on-board using
In-Circuit Programming or In-Application Program-
ming.
The array matrix organisation allows each sector
to be erased and reprogrammed without affecting
other sectors.
– Download ICP Driver code in RAM from the
ICCDATA pin
4.2 Main Features
– Execute ICP Driver code in RAM to program
the FLASH memory
■ ICP (In-Circuit Programming)
■ IAP (In-Application Programming)
Depending on the ICP Driver code downloaded in
RAM, FLASH memory programming can be fully
customized (number of bytes to program, program
locations, or selection of the serial communication
interface for downloading).
■ ICT (In-Circuit Testing) for downloading and
executing user application test patterns in RAM
■ Sector 0 size configurable by option byte
■ Read-out and write protection against piracy
4.3.2 In Application Programming (IAP)
4.3 PROGRAMMING MODES
This mode uses an IAP Driver program previously
programmed in Sector 0 by the user (in ICP
mode).
The ST7 can be programmed in three different
ways:
This mode is fully controlled by user software. This
allows it to be adapted to the user application, (us-
er-defined strategy for entering programming
mode, choice of communications protocol used to
fetch the data to be stored etc.)
IAP mode can be used to program any memory ar-
eas except Sector 0, which is write/erase protect-
ed to allow recovery in case errors occur during
the programming operation.
– Insertion in a programming tool. In this mode,
FLASH sectors 0 and 1 and option byte row
can be programmed or erased.
– In-Circuit Programming. In this mode, FLASH
sectors 0 and 1 and option byte row can be
programmed or erased without removing the
device from the application board.
– In-Application Programming. In this mode,
sector 1 can be programmed or erased with-
out removing the device from the application
14/171
ST72260G, ST72262G, ST72264G
FLASH PROGRAM MEMORY (Cont’d)
4.4 ICC interface
Tool documentation for recommended resistor val-
ues.
ICP needs a minimum of 4 and up to 7 pins to be
connected to the programming tool. These pins
are:
2. During the ICP session, the programming tool
must control the RESET pin. This can lead to con-
flicts between the programming tool and the appli-
cation reset circuit if it drives more than 5mA at
high level (push pull output or pull-up resistor<1K).
A schottky diode can be used to isolate the appli-
cation RESET circuit in this case. When using a
classical RC network with R>1K or a reset man-
agement IC with open drain output and pull-up re-
sistor>1K, no additional components are needed.
In all cases the user must ensure that no external
reset is generated by the application during the
ICC session.
– RESET: device reset
– V : device power supply ground
SS
– ICCCLK: ICC output serial clock pin
– ICCDATA: ICC input serial data pin
– ICCSEL: ICC selection (not required on devic-
es without ICCSEL pin)
– OSC1: main clock input for external source
(not required on devices without OSC1/OSC2
pins)
– V : application board power supply (option-
DD
al, see Note 3)
3. The use of Pin 7 of the ICC connector depends
on the Programming Tool architecture. This pin
must be connected when using most ST Program-
ming Tools (it is used to monitor the application
power supply). Please refer to the Programming
Tool manual.
Notes:
1. If the ICCCLK or ICCDATA pins are only used
as outputs in the application, no signal isolation is
necessary. As soon as the Programming Tool is
plugged to the board, even if an ICC session is not
in progress, the ICCCLK and ICCDATA pins are
not available for the application. If they are used as
inputs by the application, isolation such as a serial
resistor has to be implemented in case another de-
vice forces the signal. Refer to the Programming
4. Pin 9 has to be connected to the OSC1 pin of
the ST7 when the clock is not available in the ap-
plication or if the selected clock option is not pro-
grammed in the option byte. ST7 devices with mul-
ti-oscillator capability need to have OSC2 ground-
ed in this case.
Figure 6. Typical ICC Interface
PROGRAMMING TOOL
ICC CONNECTOR
ICC Cable
ICC CONNECTOR
HE10 CONNECTOR TYPE
OPTIONAL
(See Note 3)
OPTIONAL
(See Note 4)
APPLICATION BOARD
9
7
5
6
3
1
2
10
8
4
APPLICATION
RESET SOURCE
See Note 2
10kΩ
APPLICATION
POWER SUPPLY
C
L2
C
L1
APPLICATION
See Note 1
I/O
ST7
15/171
ST72260G, ST72262G, ST72264G
FLASH PROGRAM MEMORY (Cont’d)
4.5 Memory Protection
Warning: Once set, Write/erase protection can
never be removed. A write-protected flash device
is no longer reprogrammable.
There are two different types of memory protec-
tion: Read Out Protection and Write/Erase Protec-
tion which can be applied individually.
Write/erase protection is enabled through the
FMP_W bit in the option byte.
4.5.1 Read out Protection
Read out protection, when selected, makes it im-
possible to extract the memory content from the
microcontroller, thus preventing piracy.
4.6 Register Description
FLASH CONTROL/STATUS REGISTER (FCSR)
Read/Write
Reset Value: 000 0000 (00h)
1st RASS Key: 0101 0110 (56h)
2nd RASS Key: 1010 1110 (AEh)
In flash devices, this protection is removed by re-
programming the option. In this case the program
memory is automatically erased and the device
can be reprogrammed.
Read-out protection selection depends on the de-
vice type:
7
0
0
– In Flash devices it is enabled and removed
through the FMP_R bit in the option byte.
0
0
0
0
OPT
LAT
PGM
– In ROM devices it is enabled by mask option
specified in the Option List.
Note: This register is reserved for programming
using ICP, IAP or other programming methods. It
controls the XFlash programming and erasing op-
erations. For details on XFlash programming, refer
to the ST7 Flash Programming Reference Manual.
4.5.2 Flash Write/Erase Protection
Write/erase protection, when set, makes it impos-
sible to both overwrite and erase program memo-
ry. Its purpose is to provide advanced security to
applications and prevent any change being made
to the memory content.
When an EPB or another programming tool is
used (in socket or ICP mode), the RASS keys are
sent automatically.
16/171
ST72260G, ST72262G, ST72264G
5 CENTRAL PROCESSING UNIT
5.1 INTRODUCTION
5.3 CPU REGISTERS
This CPU has a full 8-bit architecture and contains
six internal registers allowing efficient 8-bit data
manipulation.
The 6 CPU registers shown in Figure 7 are not
present in the memory mapping and are accessed
by specific instructions.
Accumulator (A)
5.2 MAIN FEATURES
The Accumulator is an 8-bit general purpose reg-
ister used to hold operands and the results of the
arithmetic and logic calculations and to manipulate
data.
■ Enable executing 63 basic instructions
■ Fast 8-bit by 8-bit multiply
■ 17 main addressing modes (with indirect
Index Registers (X and Y)
addressing mode)
These 8-bit registers are used to create effective
addresses or as temporary storage areas for data
manipulation. (The Cross-Assembler generates a
precede instruction (PRE) to indicate that the fol-
lowing instruction refers to the Y register.)
■ Two 8-bit index registers
■ 16-bit stack pointer
■ Low power HALT and WAIT modes
■ Priority maskable hardware interrupts
■ Non-maskable software/hardware interrupts
The Y register is not affected by the interrupt auto-
matic procedures.
Program Counter (PC)
The program counter is a 16-bit register containing
the address of the next instruction to be executed
by the CPU. It is made of two 8-bit registers PCL
(Program Counter Low which is the LSB) and PCH
(Program Counter High which is the MSB).
Figure 7. CPU Registers
7
0
ACCUMULATOR
RESET VALUE = XXh
7
0
0
X INDEX REGISTER
Y INDEX REGISTER
RESET VALUE = XXh
7
RESET VALUE = XXh
PCL
PCH
7
8
15
0
PROGRAM COUNTER
RESET VALUE = RESET VECTOR @ FFFEh-FFFFh
7
1
0
1
1
I1 H I0 N Z C
CONDITION CODE REGISTER
RESET VALUE =
8
1
1
X 1 X X X
0
15
7
STACK POINTER
RESET VALUE = STACK HIGHER ADDRESS
X = Undefined Value
17/171
ST72260G, ST72262G, ST72264G
CENTRAL PROCESSING UNIT (Cont’d)
Condition Code Register (CC)
Read/Write
Bit 1 = Z Zero.
This bit is set and cleared by hardware. This bit in-
dicates that the result of the last arithmetic, logical
or data manipulation is zero.
0: The result of the last operation is different from
zero.
Reset Value: 111x1xxx
7
0
1: The result of the last operation is zero.
1
1
I1
H
I0
N
Z
C
This bit is accessed by the JREQ and JRNE test
instructions.
The 8-bit Condition Code register contains the in-
terrupt masks and four flags representative of the
result of the instruction just executed. This register
can also be handled by the PUSH and POP in-
structions.
Bit 0 = C Carry/borrow.
This bit is set and cleared by hardware and soft-
ware. It indicates an overflow or an underflow has
occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.
These bits can be individually tested and/or con-
trolled by specific instructions.
Arithmetic Management Bits
This bit is driven by the SCF and RCF instructions
and tested by the JRC and JRNC instructions. It is
also affected by the “bit test and branch”, shift and
rotate instructions.
Bit 4 = H Half carry.
This bit is set by hardware when a carry occurs be-
tween bits 3 and 4 of the ALU during an ADD or
ADC instructions. It is reset by hardware during
the same instructions.
Interrupt Management Bits
Bit 5,3 = I1, I0 Interrupt
0: No half carry has occurred.
1: A half carry has occurred.
The combination of the I1 and I0 bits gives the cur-
rent interrupt software priority.
This bit is tested using the JRH or JRNH instruc-
tion. The H bit is useful in BCD arithmetic subrou-
tines.
Interrupt Software Priority
Level 0 (main)
I1
1
0
0
1
I0
0
1
0
1
Level 1
Bit 2 = N Negative.
Level 2
This bit is set and cleared by hardware. It is repre-
sentative of the result sign of the last arithmetic,
logical or data manipulation. It’s a copy of the re-
Level 3 (= interrupt disable)
These two bits are set/cleared by hardware when
entering in interrupt. The loaded value is given by
the corresponding bits in the interrupt software pri-
ority registers (IxSPR). They can be also set/
cleared by software with the RIM, SIM, IRET,
HALT, WFI and PUSH/POP instructions.
th
sult 7 bit.
0: The result of the last operation is positive or null.
1: The result of the last operation is negative
(i.e. the most significant bit is a logic 1).
This bit is accessed by the JRMI and JRPL instruc-
tions.
See the interrupt management chapter for more
details.
18/171
ST72260G, ST72262G, ST72264G
CENTRAL PROCESSING UNIT (Cont’d)
Stack Pointer (SP)
Read/Write
The least significant byte of the Stack Pointer
(called S) can be directly accessed by a LD in-
struction.
Reset Value: 01 7Fh
Note: When the lower limit is exceeded, the Stack
Pointer wraps around to the stack upper limit, with-
out indicating the stack overflow. The previously
stored information is then overwritten and there-
fore lost. The stack also wraps in case of an under-
flow.
15
8
1
0
7
0
0
0
0
0
0
0
The stack is used to save the return address dur-
ing a subroutine call and the CPU context during
an interrupt. The user may also directly manipulate
the stack by means of the PUSH and POP instruc-
tions. In the case of an interrupt, the PCL is stored
at the first location pointed to by the SP. Then the
other registers are stored in the next locations as
shown in Figure 8
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
The Stack Pointer is a 16-bit register which is al-
ways pointing to the next free location in the stack.
It is then decremented after data has been pushed
onto the stack and incremented before data is
popped from the stack (see Figure 8).
– When an interrupt is received, the SP is decre-
mented and the context is pushed on the stack.
Since the stack is 128 bytes deep, the 8 most sig-
nificant bits are forced by hardware. Following an
MCU Reset, or after a Reset Stack Pointer instruc-
tion (RSP), the Stack Pointer contains its reset val-
ue (the SP7 to SP0 bits are set) which is the stack
higher address.
– On return from interrupt, the SP is incremented
and the context is popped from the stack.
A subroutine call occupies two locations and an in-
terrupt five locations in the stack area.
Figure 8. Stack Manipulation Example
CALL
Subroutine
RET
or RSP
PUSH Y
POP Y
IRET
Interrupt
Event
@ 0100h
SP
SP
SP
Y
CC
A
CC
A
CC
A
X
X
X
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
SP
SP
PCH
PCL
PCH
PCL
SP
@ 017Fh
Stack Higher Address = 017Fh
0100h
Stack Lower Address =
19/171
ST72260G, ST72262G, ST72264G
6 SUPPLY, RESET AND CLOCK MANAGEMENT
The device includes a range of utility features for
securing the application in critical situations (for
example in case of a power brown-out), and re-
ducing the number of external components. An
overview is shown in Figure 10.
6.1 PHASE LOCKED LOOP
If the clock frequency input to the PLL is in the 2 to
4 MHz range, the PLL can be used to multiply the
frequency by two to obtain an f
of 4 to 8 MHz.
OSC2
The PLL is enabled by option byte. If the PLL is
disabled, then f /2.
For more details, refer to dedicated parametric
section.
f
OSC2 = OSC
Caution: The PLL is not recommended for appli-
cations where timing accuracy is required. See
“PLL Characteristics” on page 134.
Main Features
■ Optional PLL for multiplying the frequency by 2
(not to be used with internal RC oscillator)
Figure 9. PLL Block Diagram
■ Reset Sequence Manager (RSM)
■ Multi-Oscillator Clock Management (MO)
– 4 Crystal/Ceramic resonator oscillators
– 1 Internal RC oscillator
■ System Integrity Management (SI)
PLL x 2
/ 2
0
1
f
OSC
f
OSC2
– Main supply Low Voltage Detector (LVD)
– Auxiliary Voltage Detector (AVD) with inter-
rupt capability for monitoring the main supply
PLL OPTION BIT
– Clock Security System (CSS) with Clock Filter
and Backup Safe Oscillator (enabled by op-
tion byte)
Figure 10. Clock, Reset and Supply Block Diagram
SYSTEM INTEGRITY MANAGEMENT
CLOCK SECURITY SYSTEM
(CSS)
MAIN CLOCK
CONTROLLER
WITH REALTIME
CLOCK (MCC/RTC)
MULTI-
OSCILLATOR
(MO)
f
OSC2
OSC1
f
f
CPU
f
OSC2
OSC
CLOCK
FILTER
SAFE
OSC
OSC2
PLL
(option)
RESET SEQUENCE
MANAGER
WATCHDOG
TIMER (WDG)
AVD Interrupt Request
RESET
SICSR
AVD AVD
CSS
IE
CSS WDG
LVD
RF
(RSM)
0
0
IE
F
D
RF
CSS Interrupt Request
LOW VOLTAGE
DETECTOR
(LVD)
V
V
SS
DD
AUXILIARY VOLTAGE
DETECTOR
(AVD)
20/171
ST72260G, ST72262G, ST72264G
6.2 MULTI-OSCILLATOR (MO)
The main clock of the ST7 can be generated by
four different source types coming from the multi-
oscillator block:
Internal RC Oscillator
This oscillator allows a low cost solution for the
main clock of the ST7 using only an internal resis-
tor and capacitor. Internal RC oscillator mode has
the drawback of a lower frequency accuracy and
should not be used in applications that require ac-
curate timing.
■ an external source
■ 5 crystal or ceramic resonator oscillators
■ an internal high frequency RC oscillator
Each oscillator is optimized for a given frequency
range in terms of consumption and is selectable
through the option byte. The associated hardware
configurations are shown in Table 3. Refer to the
electrical characteristics section for more details.
In this mode, the two oscillator pins have to be tied
to ground.
Table 3. ST7 Clock Sources
Hardware Configuration
Caution: The OSC1 and/or OSC2 pins must not
be left unconnected. For the purposes of Failure
Mode and Effects Analysis, it should be noted that
if the OSC1 and/or OSC2 pins are left unconnect-
ed, the ST7 main oscillator may start and, in this
ST7
OSC1
OSC2
configuration, could generate an f
clock fre-
OSC
quency in excess of the allowed maximum
(>16MHz.), putting the ST7 in an unsafe/unde-
fined state. The product behaviour must therefore
be considered undefined when the OSC pins are
left unconnected.
EXTERNAL
SOURCE
External Clock Source
ST7
In this external clock mode, a clock signal (square,
sinus or triangle) with ~50% duty cycle has to drive
the OSC1 pin while the OSC2 pin is tied to ground.
OSC1
OSC2
Crystal/Ceramic Oscillators
This family of oscillators has the advantage of pro-
ducing a very accurate rate on the main clock of
the ST7. The selection within a list of 5 oscillators
with different frequency ranges has to be done by
option byte in order to reduce consumption (refer
to Section 15.1 on page 157 for more details on
the frequency ranges). In this mode of the multi-
oscillator, the resonator and the load capacitors
have to be placed as close as possible to the oscil-
lator pins in order to minimize output distortion and
start-up stabilization time. The loading capaci-
tance values must be adjusted according to the
selected oscillator.
C
C
L2
L1
LOAD
CAPACITORS
ST7
OSC1
OSC2
These oscillators are not stopped during the
RESET phase to avoid losing time in the oscillator
start-up phase.
21/171
ST72260G, ST72262G, ST72264G
6.3 RESET SEQUENCE MANAGER (RSM)
6.3.1 Introduction
The RESET vector fetch phase duration is 2 clock
cycles.
The reset sequence manager includes three RE-
SET sources as shown in Figure 12:
Figure 11. RESET Sequence Phases
■ External RESET source pulse
■ Internal LVD RESET (Low Voltage Detection)
■ Internal WATCHDOG RESET
RESET
These sources act on the RESET pin and it is al-
ways kept low during the delay phase.
INTERNAL RESET
FETCH
Active Phase
4096 CLOCK CYCLES
VECTOR
The RESET service routine vector is fixed at ad-
dresses FFFEh-FFFFh in the ST7 memory map.
6.3.2 Asynchronous External RESET pin
The basic RESET sequence consists of 3 phases
as shown in Figure 11:
The RESET pin is both an input and an open-drain
output with integrated R
weak pull-up resistor.
ON
■ Active Phase depending on the RESET source
This pull-up has no fixed value but varies in ac-
cordance with the input voltage. It can be pulled
low by external circuitry to reset the device. See
Electrical Characteristic section for more details.
■ 4096 CPU clock cycle delay (selected by option
byte)
■ RESET vector fetch
A RESET signal originating from an external
The 4096 CPU clock cycle delay allows the oscil-
lator to stabilise and ensures that recovery has
taken place from the Reset state. The shorter or
longer clock cycle delay should be selected by op-
tion byte to correspond to the stabilization time of
the external oscillator used in the application.
source must have a duration of at least t
in
h(RSTL)in
order to be recognized (see Figure 13). This de-
tection is asynchronous and therefore the MCU
can enter reset state even in HALT mode.
Figure 12. Reset Block Diagram
V
DD
R
ON
INTERNAL
RESET
Filter
RESET
PULSE
GENERATOR
WATCHDOG RESET
LVD RESET
22/171
ST72260G, ST72262G, ST72264G
RESET SEQUENCE MANAGER (Cont’d)
The RESET pin is an asynchronous signal which
plays a major role in EMS performance. In a noisy
environment, it is recommended to follow the
guidelines mentioned in the electrical characteris-
tics section.
6.3.4 Internal Low Voltage Detector (LVD)
RESET
Two different RESET sequences caused by the in-
ternal LVD circuitry can be distinguished:
■ Power-On RESET
6.3.3 External Power-On RESET
■ Voltage Drop RESET
If the LVD is disabled by option byte, to start up the
microcontroller correctly, the user must ensure by
means of an external reset circuit that the reset
The device RESET pin acts as an output that is
pulled low when V <V
(rising edge) or
DD
IT+
V
<V (falling edge) as shown in Figure 13.
DD
IT-
signal is held low until V
level specified for the selected f
is over the minimum
DD
The LVD filters spikes on V larger than t
avoid parasitic resets.
to
g(VDD)
frequency.
DD
OSC
A proper reset signal for a slow rising V
can generally be provided by an external RC net-
supply
DD
6.3.5 Internal Watchdog RESET
work connected to the RESET pin.
The RESET sequence generated by a internal
Watchdog counter overflow is shown in Figure 13.
Starting from the Watchdog counter underflow, the
device RESET pin acts as an output that is pulled
low during at least t
.
w(RSTL)out
Figure 13. RESET Sequences
V
DD
V
V
IT+(LVD)
IT-(LVD)
LVD
RESET
EXTERNAL
RESET
WATCHDOG
RESET
RUN
RUN
RUN
RUN
ACTIVE
PHASE
ACTIVE
PHASE
ACTIVE PHASE
t
w(RSTL)out
t
h(RSTL)in
EXTERNAL
RESET
SOURCE
RESET PIN
WATCHDOG
RESET
WATCHDOG UNDERFLOW
INTERNAL RESET (4096 TCPU
VECTOR FETCH
)
23/171
ST72260G, ST72262G, ST72264G
6.4 SYSTEM INTEGRITY MANAGEMENT (SI)
The System Integrity Management block contains
group the Low voltage Detector (LVD), Auxiliary
Voltage Detector (AVD) and Clock Security Sys-
tem (CSS) functions. It is managed by the SICSR
register.
The voltage threshold can be configured by option
byte to be low, medium or high.
Provided the minimum V
the oscillator frequency) is above V , the MCU
value (guaranteed for
DD
IT-
6.4.1 Low Voltage Detector (LVD)
can only be in two modes:
The Low Voltage Detector function (LVD) gener-
– under full software control
– in static safe reset
In these conditions, secure operation is always en-
sured for the application without the need for ex-
ternal reset hardware.
ates a static reset when the V supply voltage is
DD
below a V reference value. This means that it
IT-
secures the power-up as well as the power-down
keeping the ST7 in reset.
The V reference value for a voltage drop is lower
IT-
During a Low Voltage Detector Reset, the RESET
pin is held low, thus permitting the MCU to reset
other devices.
than the V reference value for power-on in order
IT+
to avoid a parasitic reset when the MCU starts run-
ning and sinks current on the supply (hysteresis).
The LVD Reset circuitry generates a reset when
V
is below:
Notes:
DD
– V when V is rising
The LVD allows the device to be used without any
external RESET circuitry.
IT+
DD
– V when V is falling
IT-
DD
The LVD function is illustrated in Figure 14.
The LVD is an optional function which can be se-
lected by option byte.
Figure 14. Low Voltage Detector vs Reset
V
DD
V
hys
V
V
IT+
IT-
RESET
24/171
ST72260G, ST72262G, ST72264G
SYSTEM INTEGRITY MANAGEMENT (Cont’d)
6.4.2 Auxiliary Voltage Detector (AVD)
In the case of a drop in voltage, the AVD interrupt
acts as an early warning, allowing software to shut
down safely before the LVD resets the microcon-
troller. See Figure 15.
The Voltage Detector function (AVD) is based on
an analog comparison between a V and V ref-
IT-
IT+
erence value and the V
main supply. The V
DD
IT-
reference value for falling voltage is lower than the
The interrupt on the rising edge is used to inform
V
reference value for rising voltage in order to
the application that the V warning state is over.
IT+
DD
avoid parasitic detection (hysteresis).
If the voltage rise time t is less than 256 or 4096
rv
The output of the AVD comparator is directly read-
able by the application software through a real
time status bit (VDF) in the SICSR register. This bit
is read only.
Caution: The AVD functions only if the LVD is en-
abled through the option byte.
CPU cycles (depending on the reset delay select-
ed by option byte), no AVD interrupt will be gener-
ated when V
is reached.
IT+(AVD)
If t is greater than 256 or 4096 cycles then:
rv
– If the AVD interrupt is enabled before the
V
threshold is reached, then 2 AVD inter-
IT+(AVD)
6.4.2.1 Monitoring the V Main Supply
DD
rupts will be received: the first when the AVDIE
bit is set, and the second when the threshold is
reached.
The AVD voltage threshold value is relative to the
selected LVD threshold configured by option byte
(see Section 15.1 on page 157).
– If the AVD interrupt is enabled after the V
IT+(AVD)
threshold is reached then only one AVD interrupt
will occur.
If the AVD interrupt is enabled, an interrupt is gen-
erated when the voltage crosses the V
or
IT+(AVD)
V
threshold (AVDF bit toggles).
IT-(AVD)
Figure 15. Using the AVD to Monitor V
DD
V
DD
Early Warning Interrupt
(Power has dropped, MCU not
not yet in reset)
V
hyst
V
IT+(AVD)
V
IT-(AVD)
V
V
IT+(LVD)
t
VOLTAGE RISE TIME
rv
IT-(LVD)
1
1
AVDF bit
0
RESET VALUE
0
AVD INTERRUPT
REQUEST
IF AVDIE bit = 1
INTERRUPT PROCESS
INTERRUPT PROCESS
LVD RESET
25/171
ST72260G, ST72262G, ST72264G
SYSTEM INTEGRITY MANAGEMENT (Cont’d)
6.4.3 Clock Security System (CSS)
CSSIE bit has been previously set.
These two bits are described in the SICSR register
description.
The Clock Security System (CSS) protects the
ST7 against breakdowns, spikes and overfrequen-
cies occurring on the main clock source (f
is based on a clock filter and a clock detection con-
). It
6.4.4 Low Power Modes
OSC
Mode
WAIT
Description
trol with an internal safe oscillator (f
).
SFOSC
No effect on SI. CSS and AVD interrupts
cause the device to exit from Wait mode.
6.4.3.1 Clock Filter Control
The PLL has an integrated glitch filtering capability
making it possible to protect the internal clock from
overfrequencies created by individual spikes. This
feature is available only when the PLL is enabled.
The SICSR register is frozen.
The CSS (including the safe oscillator) is
disabled until HALT mode is exited. The
previous CSS configuration resumes when
the MCU is woken up by an interrupt with
“exit from HALT mode” capability or from
the counter reset value when the MCU is
woken up by a RESET.
If glitches occur on f
connection or noise), the CSS filters these auto-
(for example, due to loose
HALT
OSC
matically, so the internal CPU frequency (f
continues deliver a glitch-free signal (see Figure
16).
)
CPU
6.4.3.2 Clock detection Control
6.4.4.1 Interrupts
If the clock signal disappears (due to a broken or
disconnected resonator...), the safe oscillator de-
The CSS or AVD interrupt events generate an in-
terrupt if the corresponding Enable Control Bit
(CSSIE or AVDIE) is set and the interrupt mask in
the CC register is reset (RIM instruction).
livers a low frequency clock signal (f
allows the ST7 to perform some rescue opera-
) which
SFOSC
tions.
Enable Exit
Control from
Exit
from
Halt
Automatically, the ST7 clock source switches back
Event
Flag
Interrupt Event
from the safe oscillator (f
) if the main clock
SFOSC
Bit
Wait
source (f
) recovers.
OSC
CSS event detection
(safe oscillator acti- CSSD CSSIE
vated as main clock)
When the internal clock (f
) is driven by the safe
CPU
Yes
Yes
No
No
oscillator (f
), the application software is noti-
SFOSC
fied by hardware setting the CSSD bit in the SIC-
AVD event
AVDF AVDIE
SR register. An interrupt can be generated if the
Figure 16. Clock Filter Function
Clock Filter Function
f
OSC2
f
CPU
Clock Detection Function
f
OSC2
f
SFOSC
f
CPU
26/171
ST72260G, ST72262G, ST72264G
SYSTEM INTEGRITY MANAGEMENT (Cont’d)
6.4.5 Register Description
SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR)
Read/Write
bit set). It is set and cleared by software.
0: Clock security system interrupt disabled
1: Clock security system interrupt enabled
When the CSS is disabled by OPTION BYTE, the
CSSIE bit has no effect.
Reset Value: 000x 000x (00h)
7
0
AVD AVD LVD
CSS CSS WDG
0
0
IE
F
RF
IE
D
RF
Bit 1 = CSSD Clock security system detection
This bit indicates that the safe oscillator of the
Clock Security System block has been selected by
hardware due to a disturbance on the main clock
Bit 7 = Reserved, always read as 0.
signal (f
). It is set by hardware and cleared by
OSC
Bit 6 = AVDIE Voltage Detector interrupt enable
This bit is set and cleared by software. It enables
an interrupt to be generated when the AVDF flag
changes (toggles). The pending interrupt informa-
tion is automatically cleared when software enters
the AVD interrupt routine.
reading the SICSR register when the original oscil-
lator recovers.
0: Safe oscillator is not active
1: Safe oscillator has been activated
When the CSS is disabled by OPTION BYTE, the
CSSD bit value is forced to 0.
0: AVD interrupt disabled
1: AVD interrupt enabled
Bit 0 = WDGRF Watchdog reset flag
This bit indicates that the last Reset was generat-
ed by the Watchdog peripheral. It is set by hard-
ware (watchdog reset) and cleared by software
(writing zero) or an LVD Reset (to ensure a stable
cleared state of the WDGRF flag when CPU
starts).
Bit 5 = AVDF Voltage Detector flag
This read-only bit is set and cleared by hardware.
If the AVDIE bit is set, an interrupt request is gen-
erated when the AVDF bit changes value.
0: V over V
threshold
threshold
IT-(AVD)
DD
IT+(AVD)
1: V under V
DD
Combined with the LVDRF flag information, the
flag description is given by the following table.
Bit 4 = LVDRF LVD reset flag
RESET Sources
LVDRF WDGRF
This bit indicates that the last Reset was generat-
ed by the LVD block. It is set by hardware (LVD re-
set) and cleared by software (writing zero). See
WDGRF flag description for more details. When
the LVD is disabled by OPTION BYTE, the LVDRF
bit value is undefined.
External RESET pin
Watchdog
0
0
1
0
1
X
LVD
Application Notes
The LVDRF flag is not cleared when another RE-
SET type occurs (external or watchdog), the
LVDRF flag remains set to keep trace of the origi-
nal failure. In this case, a watchdog reset can be
detected by software while an external reset can
not.
Bit 3 = Reserved, must be kept cleared.
Bit 2 = CSSIE Clock security syst interrupt enable
.
This bit enables the interrupt when a disturbance
is detected by the Clock Security System (CSSD
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
SICSR
Reset Value
AVDIE
0
AVDF
0
LVDRF
x
CSSIE
0
CSSD
0
WDGRF
x
0025h
0
0
27/171
ST72260G, ST72262G, ST72264G
7 INTERRUPTS
7.1 INTRODUCTION
When an interrupt request has to be serviced:
– Normal processing is suspended at the end of
the current instruction execution.
The ST7 enhanced interrupt management pro-
vides the following features:
– The PC, X, A and CC registers are saved onto
the stack.
■ Hardware interrupts
■ Software interrupt (TRAP)
■ Nested or concurrent interrupt management
with flexible interrupt priority and level
management:
– I1 and I0 bits of CC register are set according to
the corresponding values in the ISPRx registers
of the serviced interrupt vector.
– The PC is then loaded with the interrupt vector of
the interrupt to service and the first instruction of
the interrupt service routine is fetched (refer to
“Interrupt Mapping” table for vector addresses).
– Up to 4 software programmable nesting levels
– Up to 16 interrupt vectors fixed by hardware
– 2 non-maskable events: RESET and TRAP
This interrupt management is based on:
The interrupt service routine should end with the
IRET instruction which causes the contents of the
saved registers to be recovered from the stack.
– Bit 5 and bit 3 of the CPU CC register (I1:0),
– Interrupt software priority registers (ISPRx),
Note: As a consequence of the IRET instruction,
the I1 and I0 bits will be restored from the stack
and the program in the previous level will resume.
– Fixed interrupt vector addresses located at the
high addresses of the memory map (FFE0h to
FFFFh) sorted by hardware priority order.
This enhanced interrupt controller guarantees full
upward compatibility with the standard (not nest-
ed) ST7 interrupt controller.
Table 4. Interrupt Software Priority Levels
Interrupt software priority Level
I1
1
0
0
1
I0
0
1
0
1
Level 0 (main)
Level 1
Low
7.2 MASKING AND PROCESSING FLOW
Level 2
The interrupt masking is managed by the I1 and I0
bits of the CC register and the ISPRx registers
which give the interrupt software priority level of
each interrupt vector (see Table 4). The process-
ing flow is shown in Figure 17
Level 3 (= interrupt disable)
High
Figure 17. Interrupt Processing Flowchart
PENDING
INTERRUPT
Y
RESET
Interrupt has the same or a
lower software priority
than current one
N
I1:0
FETCH NEXT
INSTRUCTION
THE INTERRUPT
STAYS PENDING
Y
“IRET”
N
RESTORE PC, X, A, CC
FROM STACK
EXECUTE
INSTRUCTION
STACK PC, X, A, CC
LOAD I1:0 FROM INTERRUPT SW REG.
LOAD PC FROM INTERRUPT VECTOR
28/171
ST72260G, ST72262G, ST72264G
INTERRUPTS (Cont’d)
Servicing Pending Interrupts
3). These sources allow the processor to exit
HALT mode.
■ TRAP (Non Maskable Software Interrupt)
As several interrupts can be pending at the same
time, the interrupt to be taken into account is deter-
mined by the following two-step process:
This software interrupt is serviced when the TRAP
instruction is executed. It will be serviced accord-
ing to the flowchart on Figure 17 as a TLI.
– the highest software priority interrupt is serviced,
– if several interrupts have the same software pri-
ority then the interrupt with the highest hardware
priority is serviced first.
■ RESET
The RESET source has the highest priority in the
ST7. This means that the first current routine has
the highest software priority (level 3) and the high-
est hardware priority.
Figure 18 describes this decision process.
Figure 18. Priority Decision Process
See the RESET chapter for more details.
PENDING
INTERRUPTS
Maskable Sources
Maskable interrupt vector sources can be serviced
if the corresponding interrupt is enabled and if its
own interrupt software priority (in ISPRx registers)
is higher than the one currently being serviced (I1
and I0 in CC register). If any of these two condi-
tions is false, the interrupt is latched and thus re-
mains pending.
Different
Same
SOFTWARE
PRIORITY
■ External Interrupts
HIGHEST SOFTWARE
PRIORITY SERVICED
External interrupts allow the processor to exit from
HALT low power mode.
External interrupt sensitivity is software selectable
through the Miscellaneous registers (MISCRx).
External interrupt triggered on edge will be latched
and the interrupt request automatically cleared
upon entering the interrupt service routine.
If several input pins of a group connected to the
same interrupt vector request an interrupt simulta-
neously, the interrupt vector will be serviced. Soft-
ware can read the pin levels to identify which
pin(s) are the source of the interrupt.
HIGHEST HARDWARE
PRIORITY SERVICED
When an interrupt request is not serviced immedi-
ately, it is latched and then processed when its
software priority combined with the hardware pri-
ority becomes the highest one.
Note 1: The hardware priority is exclusive while
the software one is not. This allows the previous
process to succeed with only one interrupt.
Note 2: RESET and TRAP are non-maskable and
they can be considered as having the highest soft-
ware priority in the decision process.
If several input pins are selected simultaneously
as interrupt source, these are logically NANDed.
For this reason if one of the interrupt pins is tied
low, it masks the other ones.
■ Peripheral Interrupts
Usually the peripheral interrupts cause the MCU to
exit from HALT mode except those mentioned in
the “Interrupt Mapping” table.
A peripheral interrupt occurs when a specific flag
is set in the peripheral status registers and if the
corresponding enable bit is set in the peripheral
control register.
The general sequence for clearing an interrupt is
based on an access to the status register followed
by a read or write to an associated register.
Note: The clearing sequence resets the internal
latch. A pending interrupt (i.e. waiting for being
serviced) will therefore be lost if the clear se-
quence is executed.
Different Interrupt Vector Sources
Two interrupt source types are managed by the
ST7 interrupt controller: the non-maskable type
(RESET and TRAP) and the maskable type (exter-
nal or from internal peripherals).
Non-Maskable Sources
These sources are processed regardless of the
state of the I1 and I0 bits of the CC register (see
Figure 17). After stacking the PC, X, A and CC
registers (except for RESET), the corresponding
vector is loaded in the PC register and the I1 and
I0 bits of the CC are set to disable interrupts (level
29/171
ST72260G, ST72262G, ST72264G
INTERRUPTS (Cont’d)
7.3 INTERRUPTS AND LOW POWER MODES
7.4 CONCURRENT & NESTED MANAGEMENT
All interrupts allow the processor to exit the WAIT
low power mode. On the contrary, only external
and other specified interrupts allow the processor
to exit the HALT modes (see column “Exit from
HALT” in “Interrupt Mapping” table). When several
pending interrupts are present while exiting HALT
mode, the first one serviced can only be an inter-
rupt with exit from HALT mode capability and it is
selected through the same decision process
shown in Figure 18.
The following Figure 19 and Figure 20 show two
different interrupt management modes. The first is
called concurrent mode and does not allow an in-
terrupt to be interrupted, unlike the nested mode in
Figure 20. The interrupt hardware priority is given
in this order from the lowest to the highest: MAIN,
IT4, IT3, IT2, IT1, IT0. The software priority is giv-
en for each interrupt.
Warning: A stack overflow may occur without no-
tifying the software of the failure.
Note: If an interrupt, that is not able to Exit from
HALT mode, is pending with the highest priority
when exiting HALT mode, this interrupt is serviced
after the first one serviced.
Note: TLI (Top Level Interrupt) is not available in
this product.
Figure 19. Concurrent Interrupt Management
SOFTWARE
PRIORITY
LEVEL
I1
I0
TLI
3
1 1
1 1
1 1
1 1
1 1
1 1
IT0
3
IT1
IT1
3
IT2
3
IT3
3
RIM
IT4
3
MAIN
MAIN
3/0
11 / 10
10
Figure 20. Nested Interrupt Management
SOFTWARE
PRIORITY
LEVEL
I1
I0
TLI
3
1 1
1 1
0 0
0 1
1 1
1 1
IT0
3
IT1
IT1
IT2
2
IT2
1
IT3
3
RIM
IT4
IT4
3
MAIN
MAIN
3/0
11 / 10
10
30/171
ST72260G, ST72262G, ST72264G
INTERRUPTS (Cont’d)
7.5 INTERRUPT REGISTER DESCRIPTION
INTERRUPT SOFTWARE PRIORITY REGIS-
TERS (ISPRX)
CPU CC REGISTER INTERRUPT BITS
Read/Write
Read/Write (bits 7:4 of ISPR3 are read only)
Reset Value: 111x 1010 (xAh)
Reset Value: 1111 1111 (FFh)
7
0
7
0
ISPR0
ISPR1
I1_3 I0_3 I1_2 I0_2 I1_1 I0_1 I1_0 I0_0
I1_7 I0_7 I1_6 I0_6 I1_5 I0_5 I1_4 I0_4
1
1
I1
H
I0
N
Z
C
Bit 5, 3 = I1, I0 Software Interrupt Priority
These two bits indicate the current interrupt soft-
ware priority.
ISPR2 I1_11 I0_11 I1_10 I0_10 I1_9 I0_9 I1_8 I0_8
Interrupt Software Priority Level
I1
1
0
0
1
I0
0
ISPR3
1
1
1
1
I1_13 I0_13 I1_12 I0_12
Level 0 (main)
Level 1
Low
1
These four registers contain the interrupt software
priority of each interrupt vector.
Level 2
0
Level 3 (= interrupt disable*)
High
1
– Each interrupt vector (except RESET and TRAP)
has corresponding bits in these registers where
its own software priority is stored. This corre-
spondance is shown in the following table.
These two bits are set/cleared by hardware when
entering in interrupt. The loaded value is given by
the corresponding bits in the interrupt software pri-
ority registers (ISPRx).
Vector Address
ISPRx Bits
They can be also set/cleared by software with the
RIM, SIM, HALT, WFI, IRET and PUSH/POP in-
structions (see “Interrupt Dedicated Instruction
Set” table).
FFFBh-FFFAh
FFF9h-FFF8h
...
ei0
ei1
...
FFE1h-FFE0h
Not used
*Note: TRAP and RESET events are non maska-
ble sources and can interrupt a level 3 program.
– Each I1_x and I0_x bit value in the ISPRx regis-
ters has the same meaning as the I1 and I0 bits
in the CC register.
– Level 0 can not be written (I1_x=1, I0_x=0). In
this case, the previously stored value is kept. (ex-
ample: previous=CFh, write=64h, result=44h)
The RESET and TRAP vectors have no software
priorities. When one is serviced, the I1 and I0 bits
of the CC register are both set.
Caution: If the I1_x and I0_x bits are modified
while the interrupt x is executed the following be-
haviour has to be considered: If the interrupt x is
still pending (new interrupt or flag not cleared) and
the new software priority is higher than the previ-
ous one, the interrupt x is re-entered. Otherwise,
the software priority stays unchanged up to the
next interrupt request (after the IRET of the inter-
rupt x).
31/171
ST72260G, ST72262G, ST72264G
Table 5. Interrupt Mapping
Source
Exit
from
HALT
Register Priority
Address
Vector
N°
Description
Block
Label
Order
RESET
TRAP
ei0
Reset
yes
no
FFFEh-FFFFh
FFFCh-FFFDh
FFFAh-FFFBh
FFF8h-FFF9h
FFF6h-FFF7h
FFF4h-FFF5h
FFF2h-FFF3h
FFF0h-FFF1h
FFEEh-FFEFh
FFECh-FFEDh
FFEAh-FFEBh
FFE8h-FFE9h
FFE6h-FFE7h
FFE4h-FFE5h
FFE2h-FFE3h
FFE0h-FFE1h
Highest
Priority
Software Interrupt
N/A
1
0
1
External Interrupt Port A7..0 (C5..0 )
yes
1
ei1
External Interrupt Port B7..0 (C5..0 )
2
CSS
Clock Filter Interrupt
CRSR
SPISR
TASR
no
yes
no
3
SPI
SPI Peripheral Interrupts
TIMER A Peripheral Interrupts
Time base interrupt
4
TIMER A
MCC
5
MCCSR
TBSR
yes
6
TIMER B
AVD
TIMER B Peripheral Interrupts
Auxiliary Voltage Detector interrupt
Not used
no
7
SICSR
8
9
Not used
10
11
12
13
SCI
SCI Peripheral Interrupt
SCISR
no
no
2
2
I C
I C Peripheral Interrupt
I2CSRx
Not Used
Not Used
Lowest
Priority
Note 1. Configurable by option byte.
Table 6. Nested Interrupts Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
SPI
CSS
EI1
EI0
001Ch
001Dh
001Eh
001Fh
ISPR0
Reset Value
I1_3
1
I0_3
1
I1_2
1
I0_2
1
I1_1
1
I0_1
1
I0_1
1
I0_0
1
AVD
TIMERB
MCC
TIMERA
ISPR1
Reset Value
I1_7
1
I0_7
1
I1_6
1
I0_6
1
I1_5
1
I0_5
1
I1_4
1
I0_4
1
2
I C
SCI
Not Used
Not Used
ISPR2
Reset Value
I1_11
1
I0_11
1
I1_10
1
I0_10
1
I1_9
1
I0_9
1
I1_8
1
I0_8
1
Not Used
Not Used
ISPR3
Reset Value
I1_13
1
I0_13
1
I1_12
1
I0_12
1
1
1
1
1
32/171
ST72260G, ST72262G, ST72264G
8 POWER SAVING MODES
8.1 INTRODUCTION
8.2 SLOW MODE
To give a large measure of flexibility to the applica-
tion in terms of power consumption, three main
power saving modes are implemented in the ST7
(see Figure 21).
This mode has two targets:
– To reduce power consumption by decreasing the
internal clock in the device,
– To adapt the internal clock frequency (f
the available supply voltage.
) to
CPU
After a RESET the normal operating mode is se-
lected by default (RUN mode). This mode drives
the device (CPU and embedded peripherals) by
means of a master clock which is based on the
SLOW mode is controlled by three bits in the
MISR1 register: the SMS bit which enables or dis-
ables Slow mode and two CPx bits which select
main oscillator frequency divided by 2 (f
).
CPU
the internal slow frequency (f
).
CPU
From Run mode, the different power saving
modes may be selected by setting the relevant
register bits or by calling the specific ST7 software
instruction whose action depends on the oscillator
status.
In this mode, the oscillator frequency can be divid-
ed by 4, 8, 16 or 32 instead of 2 in normal operat-
ing mode. The CPU and peripherals are clocked at
this lower frequency.
Note: SLOW-WAIT mode is activated when enter-
ring the WAIT mode while the device is already in
SLOW mode.
Figure 21. Power Saving Mode Transitions
High
RUN
Figure 22. SLOW Mode Clock Transitions
f
/2
f
/4
f
OSC2
OSC2
OSC2
f
CPU
SLOW
WAIT
f
OSC2
00
01
CP1:0
SMS
SLOW WAIT
HALT
NORMAL RUN MODE
REQUEST
NEW SLOW
FREQUENCY
REQUEST
Low
POWER CONSUMPTION
33/171
ST72260G, ST72262G, ST72264G
POWER SAVING MODES (Cont’d)
8.3 WAIT MODE
Figure 23. WAIT Mode Flowchart
WAIT mode places the MCU in a low power con-
sumption mode by stopping the CPU.
This power saving mode is selected by calling the
“WFI” ST7 software instruction.
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
ON
ON
OFF
0
WFI INSTRUCTION
All peripherals remain active. During WAIT mode,
‘10b’
the I [1:0] bits in the CC register are forced to
,
to enable all interrupts. All other registers and
memory remain unchanged. The MCU remains in
WAIT mode until an interrupt or Reset occurs,
whereupon the Program Counter branches to the
starting address of the interrupt or Reset service
routine.
N
RESET
Y
N
INTERRUPT
The MCU will remain in WAIT mode until a Reset
or an Interrupt occurs, causing it to wake up.
Y
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
ON
OFF
ON
1
Refer to Figure 23.
4096 CPU CLOCK CYCLE
DELAY
OSCILLATOR
PERIPHERALS
CPU
ON
ON
ON
1)
I[1:0] BITS
XX
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Note:
1. Before servicing an interrupt, the CC register is
pushed on the stack. The I[1:0] bits in the CC reg-
ister are set during the interrupt routine and
cleared when the CC register is popped.
34/171
ST72260G, ST72262G, ST72264G
8.4 ACTIVE-HALT AND HALT MODES
Figure 24. ACTIVE-HALT Timing Overview
ACTIVE-HALT and HALT modes are the two low-
est power consumption modes of the MCU. They
are both entered by executing the ‘HALT’ instruc-
tion. The decision to enter either in ACTIVE-HALT
or HALT mode is given by the MCC/RTC interrupt
enable flag (OIE bit in MCCSR register).
ACTIVE
HALT
4096 CPU
CYCLE DELAY
RUN
RUN
1)
RESET
OR
INTERRUPT
HALT
INSTRUCTION
[MCCSR.OIE=1]
FETCH
VECTOR
MCCSR Power Saving Mode entered when HALT
OIE bit
instruction is executed
HALT mode
ACTIVE-HALT mode
Figure 25. ACTIVE-HALT Mode Flowchart
0
1
OSCILLATOR
PERIPHERALS
CPU
ON
OFF
OFF
10
2)
HALT INSTRUCTION
(MCCSR.OIE=1)
8.4.1 ACTIVE-HALT MODE
I[1:0] BITS
ACTIVE-HALT mode is the lowest power con-
sumption mode of the MCU with a real time clock
available. It is entered by executing the ‘HALT’ in-
struction when the OIE bit of the Main Clock Con-
troller Status register (MCCSR) is set.
N
RESET
N
Y
INTERRUPT 3)
The MCU can exit ACTIVE-HALT mode on recep-
tion of either an MCC/RTC interrupt, a specific in-
terrupt (see Table 5, “Interrupt Mapping,” on page
32) or a RESET. When exiting ACTIVE-HALT
mode by means of an interrupt, no 4096 CPU cy-
cle delay occurs. The CPU resumes operation by
servicing the interrupt or by fetching the reset vec-
tor which woke it up (see Figure 25).
OSCILLATOR
PERIPHERALS
CPU
ON
OFF
ON
Y
I[1:0] BITS
XX 4)
4096 CPU CLOCK
CYCLE DELAY
When entering ACTIVE-HALT mode, the I[1:0] bits
in the CC register are forced to ‘10b’ to enable in-
terrupts. Therefore, if an interrupt is pending, the
MCU wakes up immediately.
OSCILLATOR
PERIPHERALS
CPU
ON
ON
ON
I[1:0] BITS
XX 4)
In ACTIVE-HALT mode, only the main oscillator
and its associated counter (MCC/RTC) are run-
ning to keep a wake-up time base. All other periph-
erals are not clocked except those which get their
clock supply from another clock generator (such
as external or auxiliary oscillator).
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Notes:
The safeguard against staying locked in ACTIVE-
HALT mode is provided by the oscillator interrupt.
1. This delay occurs only if the MCU exits ACTIVE-
HALT mode by means of a RESET.
2. Peripheral clocked with an external clock source
Note: As soon as the interrupt capability of one of
the oscillators is selected (MCCSR.OIE bit set),
entering ACTIVE-HALT mode while the Watchdog
is active does not generate a RESET.
This means that the device cannot spend more
than a defined delay in this power saving mode.
can still be active.
3. Only the MCC/RTC interrupt and some specific
interrupts can exit the MCU from ACTIVE-HALT
mode (such as external interrupt). Refer to Table
5, “Interrupt Mapping,” on page 32 for more details.
4. Before servicing an interrupt, the CC register is
pushed on the stack. The I[1:0] bits of the CC reg-
ister are set to the current software priority level of
the interrupt routine and restored when the CC
register is popped.
35/171
ST72260G, ST72262G, ST72264G
POWER SAVING MODES (Cont’d)
8.5 HALT MODE
Figure 27. HALT Mode Flowchart
The HALT mode is the lowest power consumption
mode of the MCU. It is entered by executing the
ST7 HALT instruction (see Figure 27).
HALT INSTRUCTION
ENABLE
The MCU can exit HALT mode on reception of ei-
ther a specific interrupt (see Table 5, “Interrupt
Mapping,” on page 32) or a RESET. When exiting
HALT mode by means of a RESET or an interrupt,
the oscillator is immediately turned on and the
4096 CPU cycle delay is used to stabilize the os-
cillator. After the start up delay, the CPU resumes
operation by servicing the interrupt or by fetching
the reset vector which woke it up (see Figure 26).
When entering HALT mode, the I[1:0] bits in the
CC register are forced to ‘10b’ to enable interrupts.
Therefore, if an interrupt is pending, the MCU
wakes immediately.
WATCHDOG
0
DISABLE
WDGHALT 1)
1
WATCHDOG
RESET
OSCILLATOR
OFF
PERIPHERALS 2)
CPU
OFF
OFF
0
I[1:0] BITS
N
RESET
In the HALT mode the main oscillator is turned off
causing all internal processing to be stopped, in-
cluding the operation of the on-chip peripherals.
All peripherals are not clocked except the ones
which get their clock supply from another clock
generator (such as an external or auxiliary oscilla-
tor).
Y
N
INTERRUPT 3)
Y
OSCILLATOR
PERIPHERALS
CPU
ON
OFF
ON
1
The compatibility of Watchdog operation with
HALT mode is configured by the “WDGHALT” op-
tion bit of the option byte. The HALT instruction
when executed while the Watchdog system is en-
abled, can generate a Watchdog RESET (see
Section 15.1 "OPTION BYTES" on page 157 for
more details).
I[1:0] BITS
4096 CPU CLOCK CYCLE
DELAY
OSCILLATOR
PERIPHERALS
CPU
ON
ON
Figure 26. HALT Mode Timing Overview
ON
I[1:0] BITS
XX 4)
4096 CPU CYCLE
RUN
HALT
RUN
DELAY
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Notes:
HALT
INSTRUCTION
1. WDGHALT is an option bit. See option byte sec-
tion for more details.
2. Peripheral clocked with an external clock source
can still be active.
RESET
OR
INTERRUPT
FETCH
VECTOR
3. Only some specific interrupts can exit the MCU
from HALT mode (such as external interrupt). Re-
fer to Table 5, “Interrupt Mapping,” on page 32 for
more details.
4. Before servicing an interrupt, the CC register is
pushed on the stack. The I[1:0] bits in the CC reg-
ister are set during the interrupt routine and
cleared when the CC register is popped.
36/171
ST72260G, ST72262G, ST72264G
POWER SAVING MODES (Cont’d)
8.5.0.1 Halt Mode Recommendations
– The opcode for the HALT instruction is 0x8E. To
avoid an unexpected HALT instruction due to a
program counter failure, it is advised to clear all
occurrences of the data value 0x8E from memo-
ry. For example, avoid defining a constant in
ROM with the value 0x8E.
– Make sure that an external event is available to
wake up the microcontroller from Halt mode.
– When using an external interrupt to wake up the
microcontroller, reinitialize the corresponding I/O
as “Input Pull-up with Interrupt” before executing
the HALT instruction. The main reason for this is
that the I/O may be wrongly configured due to ex-
ternal interference or by an unforeseen logical
condition.
– As the HALT instruction clears the interrupt mask
in the CC register to allow interrupts, the user
may choose to clear all pending interrupt bits be-
fore executing the HALT instruction. This avoids
entering other peripheral interrupt routines after
executing the external interrupt routine corre-
sponding to the wake-up event (reset or external
interrupt).
– For the same reason, reinitialize the level sensi-
tiveness of each external interrupt as a precau-
tionary measure.
37/171
ST72260G, ST72262G, ST72264G
9 I/O PORTS
9.1 INTRODUCTION
If several I/O interrupt pins on the same interrupt
vector are selected simultaneously, they are logi-
cally combined. For this reason if one of the inter-
rupt pins is tied low, it may mask the others.
The I/O ports allow data transfer. An I/O port can
contain up to 8 pins. Each pin can be programmed
independently either as a digital input or digital
output. In addition, specific pins may have several
other functions. These functions can include exter-
nal interrupt, alternate signal input/output for on-
chip peripherals or analog input.
External interrupts are hardware interrupts. Fetch-
ing the corresponding interrupt vector automatical-
ly clears the request latch. Modifying the sensitivity
bits will clear any pending interrupts.
9.2.2 Output Modes
9.2 FUNCTIONAL DESCRIPTION
Setting the DDRx bit selects output mode. Writing
to the DR bits applies a digital value to the I/O
through the latch. Reading the DR bits returns the
previously stored value.
A Data Register (DR) and a Data Direction Regis-
ter (DDR) are always associated with each port.
The Option Register (OR), which allows input/out-
put options, may or may not be implemented. The
following description takes into account the OR
register. Refer to the Port Configuration table for
device specific information.
If an OR bit is available, different output modes
can be selected by software: push-pull or open-
drain. Refer to I/O Port Implementation section for
configuration.
DR Value and Output Pin Status
An I/O pin is programmed using the corresponding
bits in the DDR, DR and OR registers: bit x corre-
sponding to pin x of the port.
DR
Push-Pull
Open-Drain
0
1
V
V
OL
Floating
OL
Figure 28 shows the generic I/O block diagram.
V
OH
9.2.1 Input Modes
9.2.3 Alternate Functions
Clearing the DDRx bit selects input mode. In this
mode, reading its DR bit returns the digital value
from that I/O pin.
Many ST7s I/Os have one or more alternate func-
tions. These may include output signals from, or
input signals to, on-chip peripherals. The Device
Pin Description table describes which peripheral
signals can be input/output to which ports.
If an OR bit is available, different input modes can
be configured by software: floating or pull-up. Re-
fer to I/O Port Implementation section for configu-
ration.
A signal coming from an on-chip peripheral can be
output on an I/O. To do this, enable the on-chip
peripheral as an output (enable bit in the peripher-
al’s control register). The peripheral configures the
I/O as an output and takes priority over standard I/
O programming. The I/O’s state is readable by ad-
dressing the corresponding I/O data register.
Notes:
1. Writing to the DR modifies the latch value but
does not change the state of the input pin.
2. Do not use read/modify/write instructions
(BSET/BRES) to modify the DR register.
External Interrupt Function
Configuring an I/O as floating enables alternate
function input. It is not recommended to configure
an I/O as pull-up as this will increase current con-
sumption. Before using an I/O as an alternate in-
put, configure it without interrupt. Otherwise spuri-
ous interrupts can occur.
Depending on the device, setting the ORx bit while
in input mode can configure an I/O as an input with
interrupt. In this configuration, a signal edge or lev-
el input on the I/O generates an interrupt request
via the corresponding interrupt vector (eix).
Falling or rising edge sensitivity is programmed in-
dependently for each interrupt vector. The Exter-
nal Interrupt Control Register (EICR) or the Miscel-
laneous Register controls this sensitivity, depend-
ing on the device.
Configure an I/O as input floating for an on-chip
peripheral signal which can be input and output.
Caution:
I/Os which can be configured as both an analog
and digital alternate function need special atten-
tion. The user must control the peripherals so that
the signals do not arrive at the same time on the
same pin. If an external clock is used, only the
clock alternate function should be employed on
that I/O pin and not the other alternate function.
A device may have up to 7 external interrupts.
Several pins may be tied to one external interrupt
vector. Refer to Pin Description to see which ports
have external interrupts.
38/171
ST72260G, ST72262G, ST72264G
I/O PORTS (Cont’d)
Figure 28. I/O Port General Block Diagram
ALTERNATE
OUTPUT
From on-chip peripheral
1
0
REGISTER
ACCESS
P-BUFFER
(see table below)
V
DD
ALTERNATE
ENABLE
BIT
PULL-UP
(see table below)
DR
V
DD
DDR
OR
PULL-UP
CONDITION
PAD
If implemented
OR SEL
DDR SEL
DR SEL
N-BUFFER
DIODES
(see table below)
ANALOG
INPUT
CMOS
SCHMITT
TRIGGER
1
0
ALTERNATE
INPUT
To on-chip peripheral
EXTERNAL
INTERRUPT
REQUEST (ei )
Combinational
Logic
FROM
OTHER
BITS
x
SENSITIVITY
SELECTION
Note: Refer to the Port Configuration
table for device specific information.
Table 7. I/O Port Mode Options
Configuration Mode
Diodes
Pull-Up
P-Buffer
to V
to V
SS
DD
Floating with/without Interrupt
Input
Off
On
Off
Pull-up with/without Interrupt
On
Push-pull
On
Off
NI
On
Off
NI
Output
Open Drain (logic level)
True Open Drain
NI (see note)
Legend: NI - not implemented
Off - implemented not activated
On - implemented and activated
Note: The diode to V is not implemented in the
DD
true open drain pads. A local protection between
the pad and V is implemented to protect the de-
OL
vice against positive stress.
39/171
ST72260G, ST72262G, ST72264G
I/O PORTS (Cont’d)
Table 8. I/O Configurations
Hardware Configuration
DR REGISTER ACCESS
V
DD
NOTE 3
PULL-UP
CONDITION
R
W
R
PU
DR
REGISTER
DATA BUS
PAD
ALTERNATE INPUT
To on-chip peripheral
FROM
OTHER
PINS
EXTERNAL INTERRUPT
SOURCE (ei )
x
COMBINATIONAL
LOGIC
INTERRUPT
CONDITION
POLARITY
SELECTION
ANALOG INPUT
V
NOTE 3
DD
DR REGISTER ACCESS
R
PU
PAD
R/W
DR
REGISTER
DATA BUS
DR REGISTER ACCESS
NOTE 3
V
DD
R
PU
R/W
DR
REGISTER
DATA BUS
PAD
ALTERNATE
ENABLE
BIT
ALTERNATE
OUTPUT
From on-chip peripheral
Notes:
1. When the I/O port is in input configuration and the associated alternate function is enabled as an output,
reading the DR register will read the alternate function output status.
2. When the I/O port is in output configuration and the associated alternate function is enabled as an input,
the alternate function reads the pin status given by the DR register content.
3. For true open drain, these elements are not implemented.
40/171
ST72260G, ST72262G, ST72264G
I/O PORTS (Cont’d)
Analog alternate function
9.4 UNUSED I/O PINS
Configure the I/O as floating input to use an ADC
input. The analog multiplexer (controlled by the
ADC registers) switches the analog voltage
present on the selected pin to the common analog
rail, connected to the ADC input.
Unused I/O pins must be connected to fixed volt-
age levels. Refer to Section 13.8.
9.5 LOW POWER MODES
Analog Recommendations
Mode
WAIT
HALT
Description
Do not change the voltage level or loading on any
I/O while conversion is in progress. Do not have
clocking pins located close to a selected analog
pin.
No effect on I/O ports. External interrupts
cause the device to exit from WAIT mode.
No effect on I/O ports. External interrupts
cause the device to exit from HALT mode.
WARNING: The analog input voltage level must
be within the limits stated in the absolute maxi-
mum ratings.
9.6 INTERRUPTS
The external interrupt event generates an interrupt
if the corresponding configuration is selected with
DDR and OR registers and if the I bit in the CC
register is cleared (RIM instruction).
9.3 I/O PORT IMPLEMENTATION
The hardware implementation on each I/O port de-
pends on the settings in the DDR and OR registers
and specific I/O port features such as ADC input or
open drain.
Enable Exit
Control from
Exit
from
Halt
Event
Flag
Interrupt Event
Bit
Wait
Switching these I/O ports from one state to anoth-
er should be done in a sequence that prevents un-
wanted side effects. Recommended safe transi-
tions are illustrated in Figure 29. Other transitions
are potentially risky and should be avoided, since
they may present unwanted side-effects such as
spurious interrupt generation.
External interrupt on
selected external
event
DDRx
ORx
-
Yes
Yes
Figure 29. Interrupt I/O Port State Transitions
01
00
10
11
INPUT
floating/pull-up
interrupt
INPUT
floating
(reset state)
OUTPUT
open-drain
OUTPUT
push-pull
= DDR, OR
XX
41/171
ST72260G, ST72262G, ST72264G
I/O PORTS (Cont’d)
9.7 DEVICE-SPECIFIC I/O PORT CONFIGURATION
The I/O port register configurations are summa-
rised as follows.
True Open Drain Interrupt Ports
PA6, PA4 (without pull-up)
Interrupt Ports
MODE
DDR
OR
PA7, PA5, PA3:0, PB7:0, PC5:0 (with pull-up)
floating input
0
0
1
0
1
X
MODE
DDR
OR
floating interrupt input
open drain (high sink ports)
floating input
0
0
1
1
0
1
0
1
pull-up interrupt input
open drain output
push-pull output
Table 9. Port Configuration
Input (DDR = 0)
Output (DDR = 1)
Port
Pin Name
PA7
OR = 0
OR = 1
OR = 0
OR = 1
High-Sink
floating
floating
floating
floating
floating
floating
floating
pull-up interrupt
floating interrupt
pull-up interrupt
floating interrupt
pull-up interrupt
pull-up interrupt
pull-up interrupt
open drain
push-pull
PA6
true open-drain
Port A
PA5
open drain
push-pull
Yes
PA4
true open-drain
PA3:0
PB7:0
PC5:0
open drain
open drain
open drain
push-pull
push-pull
push-pull
Port B
Port C
No
42/171
ST72260G, ST72262G, ST72264G
I/O PORTS (Cont’d)
9.8 I/O PORT REGISTER DESCRIPTION
DATA REGISTER (DR)
Bits 7:0 = DD[7:0] Data direction register 8 bits.
The DDR register gives the input/output direction
configuration of the pins. Each bit is set and
cleared by software.
Port x Data Register
PxDR with x = A, B or C.
0: Input mode
1: Output mode
Read/Write
Reset Value: 0000 0000 (00h)
OPTION REGISTER (OR)
Port x Option Register
7
0
PxOR with x = A, B or C.
Read/Write
D7
D6
D5
D4
D3
D2
D1
D0
Reset Value: 0000 0000 (00h)
Bits 7:0 = D[7:0] Data register 8 bits.
7
0
The DR register has a specific behaviour accord-
ing to the selected input/output configuration. Writ-
ing the DR register is always taken into account
even if the pin is configured as an input; this allows
always having the expected level on the pin when
toggling to output mode. Reading the DR register
returns either the DR register latch content (pin
configured as output) or the digital value applied to
the I/O pin (pin configured as input).
O7
O6
O5
O4
O3
O2
O1
O0
Bits 7:0 = O[7:0] Option register 8 bits.
For specific I/O pins, this register is not implement-
ed. In this case the DDR register is enough to se-
lect the I/O pin configuration.
The OR register allows to distinguish: in input
mode if the pull-up with interrupt capability or the
basic pull-up configuration is selected, in output
mode if the push-pull or open drain configuration is
selected.
DATA DIRECTION REGISTER (DDR)
Port x Data Direction Register
PxDDR with x = A, B or C.
Each bit is set and cleared by software.
Read/Write
Reset Value: 0000 0000 (00h)
Input mode:
0: Floating input
1: Pull-up input with or without interrupt
7
0
Output mode:
0: Output open drain (with P-Buffer unactivated)
1: Output push-pull (when available)
DD7
DD6
DD5
DD4
DD3
DD2
DD1
DD0
43/171
ST72260G, ST72262G, ST72264G
I/O PORTS (Cont’d)
Table 10. I/O Port Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
Reset Value
of all I/O port registers
0
0
0
0
0
0
0
0
0000h
0001h
0002h
0004h
0005h
0006h
0008h
0009h
000Ah
PCDR
PCDDR
PCOR
PBDR
PBDDR
PBOR
PADR
PADDR
PAOR
MSB
MSB
MSB
LSB
LSB
LSB
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ST72260G, ST72262G, ST72264G
10 MISCELLANEOUS REGISTERS
The miscellaneous registers allow control over
several different features such as the external in-
terrupts or the I/O alternate functions.
Figure 30. Ext. Interrupt Sensitivity (EXTIT=0)
MISCR1
IS00 IS01
PA7
ei0
10.1 I/O PORT INTERRUPT SENSITIVITY
INTERRUPT
SOURCE
The external interrupt sensitivity is controlled by
the ISxx bits of the Miscellaneous register and the
OPTION BYTE. This control allows you to have
two fully independent external interrupt source
sensitivities with configurable sources (using the
EXTIT option bit) as shown in Figure 30 and Fig-
ure 31.
SENSITIVITY
CONTROL
PA0
PC5
PC0
MISCR1
IS10
IS11
ei1
Each external interrupt source can be generated
on four different events on the pin:
PB7
PB0
INTERRUPT
SOURCE
SENSITIVITY
CONTROL
■ Falling edge
■ Rising edge
■ Falling and rising edge
■ Falling edge and low level
To guarantee correct functionality, the sensitivity
bits in the MISCR1 register must be modified only
when the I[1:0] bits in the CC register are set to 1
(interrupt masked). See Section 9.8 "I/O PORT
REGISTER DESCRIPTION" on page 43 and Sec-
tion 10.3 "MISCELLANEOUS REGISTER DE-
SCRIPTION" on page 46 for more details on the
programming.
Figure 31. Ext. Interrupt Sensitivity (EXTIT=1)
MISCR1
IS00
IS01
ei0
PA7
INTERRUPT
SOURCE
SENSITIVITY
CONTROL
PA0
PB7
10.2 I/O PORT ALTERNATE FUNCTIONS
MISCR1
The MISCR registers manage four I/O port miscel-
laneous alternate functions:
IS10
IS11
ei1
INTERRUPT
SOURCE
SENSITIVITY
CONTROL
PB0
PC5
■ Main clock signal (f
) output on PC2
CPU
■ SPI pin configuration:
– SS pin internal control to use the PB7 I/O port
function while the SPI is active.
– Master output capability on the MOSI pin
(PB4) deactivated while the SPI is active.
PC0
– Slave output capability on the MISO pin (PB5)
deactivated while the SPI is active.
These functions are described in detail in the Sec-
tion 10.3 "MISCELLANEOUS REGISTER DE-
SCRIPTION" on page 46.
45/171
ST72260G, ST72262G, ST72264G
MISCELLANEOUS REGISTERS (Cont’d)
10.3 MISCELLANEOUS REGISTER DESCRIPTION
MISCELLANEOUS REGISTER 1 (MISCR1)
Read/Write
Bits 2:1 = CP[1:0] CPU clock prescaler
These bits select the CPU clock prescaler which is
applied in the various slow modes. Their action is
conditioned by the setting of the SMS bit. These
two bits are set and cleared by software
Reset Value: 0000 0000 (00h)
7
0
f
in SLOW mode
CP1
CP0
CPU
IS11 IS10 MCO IS01 IS00 CP1 CP0 SMS
f
f
f
/ 2
/ 4
0
1
0
1
0
0
1
1
OSC2
OSC2
OSC2
/ 8
Bits 7:6 = IS1[1:0] ei1 sensitivity
f
/ 16
OSC2
The interrupt sensitivity, defined using the IS1[1:0]
bits, is applied to the ei1 external interrupts. These
two bits can be written only when the I[1:0] bits in
the CC register are set to 1 (interrupt masked).
Bit 0 = SMS Slow mode select
This bit is set and cleared by software.
0: Normal mode. f = f
ei1: Port B (C optional)
OSC2
CPU
1: Slow mode. f
is given by CP1, CP0
CPU
External Interrupt Sensitivity
IS11 IS10
See low power consumption mode and MCC
chapters for more details.
Falling edge & low level
Rising edge only
0
0
1
1
0
1
0
1
Falling edge only
Rising and falling edge
Bit 5 = MCO Main clock out selection
This bit enables the MCO alternate function on the
PC2 I/O port. It is set and cleared by software.
0: MCO alternate function disabled (I/O pin free for
general-purpose I/O)
1: MCO alternate function enabled (f
port)
on I/O
CPU
Bits 4:3 = IS0[1:0] ei0 sensitivity
The interrupt sensitivity, defined using the IS0[1:0]
bits, is applied to the ei0 external interrupts. These
two bits can be written only when the I[1:0] bits in-
the CC register are set to 1 (interrupt masked).
ei0: Port A (C optional)
External Interrupt Sensitivity
IS01 IS00
Falling edge & low level
Rising edge only
0
0
1
1
0
1
0
1
Falling edge only
Rising and falling edge
46/171
ST72260G, ST72262G, ST72264G
MISCELLANEOUS REGISTERS (Cont’d)
MISCELLANEOUS REGISTER 2 (MISCR2)
Read/Write
Reset Value: 0000 0000 (00h)
7
0
0
0
0
0
MOD SOD SSM SSI
Caution: This register has been provided for com-
patibility with the ST72254 family only. The same
bits are available in the SPICSR register. New ap-
plications must use the SPICSR register. Do not
use both registers, this will cause the SPI to mal-
function.
Bits 7:4 = Reserved always read as 0
Bits 3 = MOD SPI Master Output Disable
This bit is set and cleared by software. When set, it
disables the SPI Master (MOSI) output signal.
0: SPI Master Output enabled.
1: SPI Master Output disabled.
Bit 2 = SOD SPI Slave Output Disable
This bit is set and cleared by software. When set it
disable the SPI Slave (MISO) output signal.
0: SPI Slave Output enabled.
1: SPI Slave Output disabled.
Bit 1 = SSM SS mode selection
This bit is set and cleared by software.
0: Normal mode - the level of the SPI SS signal is
input from the external SS pin.
1: I/O mode, the level of the SPI SS signal is read
from the SSI bit.
Bit 0 = SSI SS internal mode
This bit replaces the SS pin of the SPI when the
SSM bit is set to 1. (see SPI description). It is set
and cleared by software.
Table 11. Miscellaneous Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
MISCR1
Reset Value
IS11
0
IS10
0
MCO
0
IS01
0
IS00
0
CP1
0
CP0
0
SMS
0
0020h
0040h
MISCR2
Reset Value
MOD
0
SOD
0
SSM
0
SSI
0
0
0
0
0
47/171
ST72260G, ST72262G, ST72264G
11 ON-CHIP PERIPHERALS
11.1 WATCHDOG TIMER (WDG)
11.1.1 Introduction
If the watchdog is activated (the WDGA bit is set)
and when the 7-bit timer (bits T[6:0]) rolls over
from 40h to 3Fh (T6 becomes cleared), it initiates
a reset cycle pulling low the reset pin for typically
500ns.
The Watchdog timer is used to detect the occur-
rence of a software fault, usually generated by ex-
ternal interference or by unforeseen logical condi-
tions, which causes the application program to
abandon its normal sequence. The Watchdog cir-
cuit generates an MCU reset on expiry of a pro-
grammed time period, unless the program refresh-
es the counter’s contents before the T6 bit be-
comes cleared.
The application program must write in the
WDGCR register at regular intervals during normal
operation to prevent an MCU reset. This down-
counter is free-running: it counts down even if the
watchdog is disabled. The value to be stored in the
WDGCR register must be between FFh and C0h:
11.1.2 Main Features
– The WDGA bit is set (watchdog enabled)
■ Programmable free-running downcounter
■ Programmable reset
– The T6 bit is set to prevent generating an imme-
diate reset
■ Reset (if watchdog activated) when the T6 bit
– The T[5:0] bits contain the number of increments
which represents the time delay before the
watchdog produces a reset (see Figure 33. Ap-
proximate Timeout Duration). The timing varies
between a minimum and a maximum value due
to the unknown status of the prescaler when writ-
ing to the WDGCR register (see Figure 34).
reaches zero
■ Optional
reset
on
HALT
instruction
(configurable by option byte)
■ Hardware Watchdog selectable by option byte
11.1.3 Functional Description
Following a reset, the watchdog is disabled. Once
activated it cannot be disabled, except by a reset.
The counter value stored in the Watchdog Control
register (WDGCR bits T[6:0]), is decremented
every 16384 f
length of the timeout period can be programmed
by the user in 64 increments.
cycles (approx.), and the
The T6 bit can be used to generate a software re-
set (the WDGA bit is set and the T6 bit is cleared).
OSC2
If the watchdog is activated, the HALT instruction
will generate a Reset.
Figure 32. Watchdog Block Diagram
RESET
f
OSC2
MCC/RTC
WATCHDOG CONTROL REGISTER (WDGCR)
T6 T5 T0
DIV 64
WDGA
T1
T4
T2
T3
6-BIT DOWNCOUNTER (CNT)
12-BIT MCC
RTC COUNTER
WDG PRESCALER
DIV 4
TB[1:0] bits
(MCCSR
Register)
MSB
LSB
0
6 5
11
48/171
ST72260G, ST72262G, ST72264G
WATCHDOG TIMER (Cont’d)
11.1.4 How to Program the Watchdog Timeout
more precision is needed, use the formulae in Fig-
ure 34.
Figure 33 shows the linear relationship between
the 6-bit value to be loaded in the Watchdog Coun-
ter (CNT) and the resulting timeout duration in mil-
liseconds. This can be used for a quick calculation
without taking the timing variations into account. If
Caution: When writing to the WDGCR register, al-
ways write 1 in the T6 bit to avoid generating an
immediate reset.
Figure 33. Approximate Timeout Duration
3F
38
30
28
20
18
10
08
00
1.5
18
34
50
65
82
98
114
128
Watchdog timeout (ms) @ 8 MHz. f
OSC2
49/171
ST72260G, ST72262G, ST72264G
WATCHDOG TIMER (Cont’d)
Figure 34. Exact Timeout Duration (t
and t
)
max
min
WHERE:
t
t
t
= (LSB + 128) x 64 x t
min0
OSC2
= 16384 x t
= 125ns if f
max0
OSC2
OSC2
=8 MHz
OSC2
CNT = Value of T[5:0] bits in the WDGCR register (6 bits)
MSB and LSB are values from the table below depending on the timebase selected by the TB[1:0] bits
in the MCCSR register
TB1 Bit
TB0 Bit
Selected MCCSR
Timebase
MSB
LSB
(MCCSR Reg.) (MCCSR Reg.)
0
0
1
1
0
1
0
1
2ms
4ms
4
8
59
53
35
54
10ms
25ms
20
49
To calculate the minimum Watchdog Timeout (t ):
min
MSB
4
IF
-------------
THEN
ELSE
CNT <
t
= t
16384 × CNT × t
osc2
min
min0
4CNT
----------------
MSB
4CNT
----------------
MSB
t
= t
+ 16384 × CNT
(192 + LSB) × 64 ×
× t
osc2
min
min0
To calculate the maximum Watchdog Timeout (t
):
max
MSB
4
IF
THEN
ELSE
-------------
CNT ≤
t
= t
16384 × CNT × t
osc2
max
max0
4CNT
----------------
4CNT
----------------
t
= t
+ 16384 × CNT
(192 + LSB) × 64 ×
× t
osc2
max
max0
MSB
MSB
Note: In the above formulae, division results must be rounded down to the next integer value.
Example:
With 2ms timeout selected in MCCSR register
Min. Watchdog
Timeout (ms)
Max. Watchdog
Timeout (ms)
Value of T[5:0] Bits in
WDGCR Register (Hex.)
t
t
min
max
00
3F
1.496
128
2.048
128.552
50/171
ST72260G, ST72262G, ST72264G
WATCHDOG TIMER (Cont’d)
11.1.5 Low Power Modes
Mode Description
SLOW No effect on Watchdog.
WAIT No effect on Watchdog.
OIE bit in
MCCSR
register
WDGHALT bit
in Option
Byte
No Watchdog reset is generated. The MCU enters Halt mode. The Watch-
dog counter is decremented once and then stops counting and is no longer
able to generate a watchdog reset until the MCU receives an external inter-
rupt or a reset.
0
0
If an external interrupt is received, the Watchdog restarts counting after 256
or 4096 CPU clocks. If a reset is generated, the Watchdog is disabled (reset
state) unless Hardware Watchdog is selected by option byte. For applica-
tion recommendations see Section 11.1.7 below.
HALT
0
1
1
x
A reset is generated.
No reset is generated. The MCU enters Active Halt mode. The Watchdog
counter is not decremented. It stop counting. When the MCU receives an
oscillator interrupt or external interrupt, the Watchdog restarts counting im-
mediately. When the MCU receives a reset the Watchdog restarts counting
after 256 or 4096 CPU clocks.
11.1.6 Hardware Watchdog Option
11.1.9 Register Description
If Hardware Watchdog is selected by option byte,
the watchdog is always active and the WDGA bit in
the WDGCR is not used. Refer to the Option Byte
description.
CONTROL REGISTER (WDGCR)
Read/Write
Reset Value: 0111 1111 (7Fh)
11.1.7 Using Halt Mode with the WDG
(WDGHALT option)
7
0
WDGA T6
T5
T4
T3
T2
T1
T0
The following recommendation applies if Halt
mode is used when the watchdog is enabled.
– Before executing the HALT instruction, refresh
the WDG counter, to avoid an unexpected WDG
reset immediately after waking up the microcon-
troller.
Bit 7 = WDGA Activation bit.
This bit is set by software and only cleared by
hardware after a reset. When WDGA = 1, the
watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled
11.1.8 Interrupts
None.
Note: This bit is not used if the hardware watch-
dog option is enabled by option byte.
Bit 6:0 = T[6:0] 7-bit counter (MSB to LSB).
These bits contain the value of the watchdog
counter. It is decremented every 16384 f
cy-
OSC2
cles (approx.). A reset is produced when it rolls
over from 40h to 3Fh (T6 becomes cleared).
51/171
ST72260G, ST72262G, ST72264G
Table 12. Watchdog Timer Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
WDGCR
Reset Value
WDGA
0
T6
1
T5
1
T4
1
T3
1
T2
1
T1
1
T0
1
0024h
52/171
ST72260G, ST72262G, ST72264G
11.2
MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (MCC/RTC)
The Main Clock Controller consists of a real time
clock timer with interrupt capability
When the RTC interrupt is enabled (OIE bit set),
the ST7 enters ACTIVE-HALT mode when the
HALT instruction is executed. See Section 8.4
"ACTIVE-HALT AND HALT MODES" on page 35
for more details.
11.2.1
Real Time Clock Timer (RTC)
The counter of the real time clock timer allows an
interrupt to be generated based on an accurate
real time clock. Four different time bases depend-
ing directly on f
are available. The whole
OSC2
functionality is controlled by four bits of the MCC-
SR register: TB[1:0], OIE and OIF.
Figure 35. Main Clock Controller (MCC/RTC) Block Diagram
f
OSC2
TO WATCHDOG
RTC
COUNTER
TB1 TB0 OIE OIF
MCCSR
MCC/RTC INTERRUPT
53/171
ST72260G, ST72262G, ST72264G
MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont’d)
11.2.2
Bit 7:4 = reserved
Low Power Modes
Mode
Description
Bit 3:2 = TB[1:0] Time base control
No effect on MCC/RTC peripheral.
MCC/RTC interrupt cause the device to exit
from WAIT mode.
These bits select the programmable divider time
base. They are set and cleared by software.
WAIT
No effect on MCC/RTC counter (OIE bit is
ACTIVE- set), the registers are frozen.
Time Base
Counter
TB1 TB0
Prescaler
HALT
MCC/RTC interrupt cause the device to exit
f
=4MHz f
=8MHz
OSC2
OSC2
from ACTIVE-HALT mode.
16000
32000
80000
200000
4ms
2ms
4ms
0
0
1
1
0
1
0
1
MCC/RTC counter and registers are frozen.
MCC/RTC operation resumes when the
MCU is woken up by an interrupt with “exit
from HALT” capability.
8ms
20ms
50ms
HALT
10ms
25ms
11.2.3
Interrupts
A modification of the time base is taken into ac-
count at the end of the current period (previously
set) to avoid an unwanted time shift. This allows to
use this time base as a real time clock.
The MCC/RTC interrupt event generates an inter-
rupt if the OIE bit of the MCCSR register is set and
the interrupt mask in the CC register is not active
(RIM instruction).
Bit 1 = OIE Oscillator interrupt enable
This bit set and cleared by software.
0: Oscillator interrupt disabled
Enable Exit
Control from
Exit
from
Halt
Event
Flag
Interrupt Event
Bit
Wait
1: Oscillator interrupt enabled
This interrupt can be used to exit from ACTIVE-
HALT mode.
Time base overflow
event
1)
OIF
OIE
Yes
No
When this bit is set, calling the ST7 software HALT
instruction enters the ACTIVE-HALT power saving
Note:
The MCC/RTC interrupt wakes up the MCU from
ACTIVE-HALT mode, not from HALT mode.
modeMAIN CLOCK CONTROLLER WITH REAL
.
TIME CLOCK (Cont’d)
Bit 0 = OIF Oscillator interrupt flag
This bit is set by hardware and cleared by software
reading the CSR register. It indicates when set
that the main oscillator has reached the selected
elapsed time (TB1:0).
11.2.4
Register Description
MCC CONTROL/STATUS REGISTER (MCCSR)
Read/Write
0: Timeout not reached
1: Timeout reached
Reset Value: 0000 0000 (00h
)
7
0
CAUTION: The BRES and BSET instructions
must not be used on the MCCSR register to avoid
unintentionally clearing the OIF bit.
0
0
0
0
TB1 TB0 OIE
OIF
Table 13. Main Clock Controller Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
SICSR
Reset Value
VDS
0
VDIE
0
VDF
0
LVDRF
x
CFIE
0
CSSD
0
WDGRF
x
0025h
0026h
0
MCCSR
Reset Value
TB1
0
TB0
0
OIE
0
OIF
0
0
0
0
0
54/171
ST72260G, ST72262G, ST72264G
11.3 16-BIT TIMER
11.3.1 Introduction
When reading an input signal on a non-bonded
pin, the value will always be ‘1’.
The timer consists of a 16-bit free-running counter
driven by a programmable prescaler.
11.3.3 Functional Description
11.3.3.1 Counter
It may be used for a variety of purposes, including
pulse length measurement of up to two input sig-
nals (input capture) or generation of up to two out-
put waveforms (output compare and PWM).
The main block of the Programmable Timer is a
16-bit free running upcounter and its associated
16-bit registers. The 16-bit registers are made up
of two 8-bit registers called high & low.
Pulse lengths and waveform periods can be mod-
ulated from a few microseconds to several milli-
seconds using the timer prescaler and the CPU
clock prescaler.
Counter Register (CR):
– Counter High Register (CHR) is the most sig-
nificant byte (MS Byte).
Some ST7 devices have two on-chip 16-bit timers.
They are completely independent, and do not
share any resources. They are synchronized after
a MCU reset as long as the timer clock frequen-
cies are not modified.
– Counter Low Register (CLR) is the least sig-
nificant byte (LS Byte).
Alternate Counter Register (ACR)
– Alternate Counter High Register (ACHR) is the
most significant byte (MS Byte).
This description covers one or two 16-bit timers. In
ST7 devices with two timers, register names are
prefixed with TA (Timer A) or TB (Timer B).
– Alternate Counter Low Register (ACLR) is the
least significant byte (LS Byte).
11.3.2 Main Features
These two read-only 16-bit registers contain the
same value but with the difference that reading the
ACLR register does not clear the TOF bit (Timer
overflow flag), located in the Status register, (SR),
(see note at the end of paragraph titled 16-bit read
sequence).
■ Programmableprescaler:fCPU dividedby2, 4or8.
■ Overflow status flag and maskable interrupt
■ External clock input (must be at least 4 times
slowerthan theCPUclockspeed)with thechoice
of active edge
■ 1 or 2 Output Compare functions each with:
– 2 dedicated 16-bit registers
Writing in the CLR register or ACLR register resets
the free running counter to the FFFCh value.
Both counters have a reset value of FFFCh (this is
the only value which is reloaded in the 16-bit tim-
er). The reset value of both counters is also
FFFCh in One Pulse mode and PWM mode.
– 2 dedicated programmable signals
– 2 dedicated status flags
– 1 dedicated maskable interrupt
■ 1 or 2 Input Capture functions each with:
– 2 dedicated 16-bit registers
The timer clock depends on the clock control bits
of the CR2 register, as illustrated in Table 14 Clock
Control Bits. The value in the counter register re-
peats every 131072, 262144 or 524288 CPU clock
cycles depending on the CC[1:0] bits.
– 2 dedicated active edge selection signals
– 2 dedicated status flags
– 1 dedicated maskable interrupt
■ Pulse width modulation mode (PWM)
■ One pulse mode
The timer frequency can be f
or an external frequency.
/2, f
/4, f
/8
CPU
CPU
CPU
■ Reduced Power Mode
■ 5 alternate functionson I/O ports (ICAP1, ICAP2,
OCMP1, OCMP2, EXTCLK)*
The Block Diagram is shown in Figure 36.
*Note: Some timer pins may not available (not
bonded) in some ST7 devices. Refer to the device
pin out description.
55/171
ST72260G, ST72262G, ST72264G
16-BIT TIMER (Cont’d)
Figure 36. Timer Block Diagram
ST7 INTERNAL BUS
f
CPU
MCU-PERIPHERAL INTERFACE
8 low
8-bit
8 high
8
8
8
8
8
8
8
8
buffer
w
w
w
w
EXEDG
h
o
h
o
h
o
h
lo
16
INPUT
CAPTURE
REGISTER
INPUT
CAPTURE
REGISTER
OUTPUT
COMPARE
REGISTER
OUTPUT
COMPARE
REGISTER
1/2
1/4
1/8
COUNTER
REGISTER
1
1
2
2
ALTERNATE
COUNTER
REGISTER
EXTCLK
pin
16
16
16
CC[1:0]
TIMER INTERNAL BUS
16 16
OVERFLOW
DETECT
EDGE DETECT
CIRCUIT1
OUTPUT COMPARE
CIRCUIT
ICAP1
pin
CIRCUIT
6
EDGE DETECT
CIRCUIT2
ICAP2
pin
OCMP1
pin
LATCH1
LATCH2
0
ICF1 OCF1 TOF ICF2 OCF2
0
TIMD
(Control/Status Register)
OCMP2
pin
CSR
EXEDG
ICIE OCIE TOIE FOLV2 FOLV1OLVL2 IEDG1 OLVL1
OC1E
OPM PWM CC1 CC0 IEDG2
OC2E
(Control Register 1) CR1
(Control Register 2) CR2
(See note)
Note: If IC, OC and TO interrupt requests have separate vectors
then the last OR is not present (See device Interrupt Vector Table)
TIMER INTERRUPT
56/171
ST72260G, ST72262G, ST72264G
16-BIT TIMER (Cont’d)
16-bit read sequence: (from either the Counter
Register or the Alternate Counter Register).
Clearing the overflow interrupt request is done in
two steps:
1. Reading the SR register while the TOF bit is set.
2. An access (read or write) to the CLR register.
Beginning of the sequence
Read
LS Byte
is buffered
Notes: The TOF bit is not cleared by accesses to
ACLR register. The advantage of accessing the
ACLR register rather than the CLR register is that
it allows simultaneous use of the overflow function
and reading the free running counter at random
times (for example, to measure elapsed time) with-
out the risk of clearing the TOF bit erroneously.
MS Byte
At t0
Other
instructions
Returns the buffered
LS Byte value at t0
Read
LS Byte
At t0 +∆t
The timer is not affected by WAIT mode.
In HALT mode, the counter stops counting until the
mode is exited. Counting then resumes from the
previous count (MCU awakened by an interrupt) or
from the reset count (MCU awakened by a Reset).
Sequence completed
The user must read the MS Byte first, then the LS
Byte value is buffered automatically.
This buffered value remains unchanged until the
16-bit read sequence is completed, even if the
user reads the MS Byte several times.
11.3.3.2 External Clock
The external clock (where available) is selected if
CC0=1 and CC1=1 in the CR2 register.
After a complete reading sequence, if only the
CLR register or ACLR register are read, they re-
turn the LS Byte of the count value at the time of
the read.
The status of the EXEDG bit in the CR2 register
determines the type of level transition on the exter-
nal clock pin EXTCLK that will trigger the free run-
ning counter.
Whatever the timer mode used (input capture, out-
put compare, one pulse mode or PWM mode) an
overflow occurs when the counter rolls over from
FFFFh to 0000h then:
The counter is synchronized with the falling edge
of the internal CPU clock.
A minimum of four falling edges of the CPU clock
must occur between two consecutive active edges
of the external clock; thus the external clock fre-
quency must be less than a quarter of the CPU
clock frequency.
– The TOF bit of the SR register is set.
– A timer interrupt is generated if:
– TOIE bit of the CR1 register is set and
– I bit of the CC register is cleared.
If one of these conditions is false, the interrupt re-
mains pending to be issued as soon as they are
both true.
57/171
ST72260G, ST72262G, ST72264G
16-BIT TIMER (Cont’d)
Figure 37. Counter Timing Diagram, internal clock divided by 2
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
FFFD FFFE FFFF 0000 0001 0002 0003
COUNTER REGISTER
TIMER OVERFLOW FLAG (TOF)
Figure 38. Counter Timing Diagram, internal clock divided by 4
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
FFFC
FFFD
0000
0001
COUNTER REGISTER
TIMER OVERFLOW FLAG (TOF)
Figure 39. Counter Timing Diagram, internal clock divided by 8
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
0000
FFFC
FFFD
COUNTER REGISTER
TIMER OVERFLOW FLAG (TOF)
Note: The MCU is in reset state when the internal reset signal is high, when it is low the MCU is running.
58/171
ST72260G, ST72262G, ST72264G
16-BIT TIMER (Cont’d)
11.3.3.3 Input Capture
When an input capture occurs:
In this section, the index, i, may be 1 or 2 because
there are 2 input capture functions in the 16-bit
timer.
– ICFi bit is set.
– The ICiR register contains the value of the free
running counter on the active transition on the
ICAPi pin (see Figure 41).
The two 16-bit input capture registers (IC1R and
IC2R) are used to latch the value of the free run-
ning counter after a transition is detected on the
ICAPi pin (see figure 5).
– A timer interrupt is generated if the ICIE bit is set
and the I bit is cleared in the CC register. Other-
wise, the interrupt remains pending until both
conditions become true.
MS Byte
ICiHR
LS Byte
ICiLR
Clearing the Input Capture interrupt request (i.e.
clearing the ICFi bit) is done in two steps:
ICiR
ICiR register is a read-only register.
1. Reading the SR register while the ICFi bit is set.
2. An access (read or write) to the ICiLR register.
The active transition is software programmable
through the IEDGi bit of Control Registers (CRi).
Timing resolution is one count of the free running
Notes:
counter: (f
/CC[1:0]).
CPU
1. After reading the ICiHR register, transfer of
input capture data is inhibited and ICFi will
never be set until the ICiLR register is also
read.
Procedure:
To use the input capture function select the follow-
ing in the CR2 register:
2. The ICiR register contains the free running
counter value which corresponds to the most
recent input capture.
– Select the timer clock (CC[1:0]) (see Table 14
Clock Control Bits).
3. The 2 input capture functions can be used
together even if the timer also uses the 2 output
compare functions.
– Select the edge of the active transition on the
ICAP2 pin with the IEDG2 bit (the ICAP2 pin
must be configured as floating input or input with
pull-up without interrupt if this configuration is
available).
4. In One pulse Mode and PWM mode only Input
Capture 2 can be used.
And select the following in the CR1 register:
5. The alternate inputs (ICAP1 & ICAP2) are
always directly connected to the timer. So any
transitions on these pins activates the input
capture function.
– Set the ICIE bit to generate an interrupt after an
input capture coming from either the ICAP1 pin
or the ICAP2 pin
Moreover if one of the ICAPi pins is configured
as an input and the second one as an output,
an interrupt can be generated if the user tog-
gles the output pin and if the ICIE bit is set.
This can be avoided if the input capture func-
tion i is disabled by reading the ICiHR (see note
1).
– Select the edge of the active transition on the
ICAP1 pin with the IEDG1 bit (the ICAP1pin must
be configured as floating input or input with pull-
up without interrupt if this configuration is availa-
ble).
6. The TOF bit can be used with interrupt genera-
tion in order to measure events that go beyond
the timer range (FFFFh).
59/171
ST72260G, ST72262G, ST72264G
16-BIT TIMER (Cont’d)
Figure 40. Input Capture Block Diagram
ICAP1
pin
(Control Register 1) CR1
IEDG1
EDGE DETECT
CIRCUIT2
EDGE DETECT
CIRCUIT1
ICIE
ICAP2
pin
(Status Register) SR
ICF1
ICF2
0
0
0
IC2R Register
IC1R Register
(Control Register 2) CR2
16-BIT
16-BIT FREE RUNNING
COUNTER
IEDG2
CC0
CC1
Figure 41. Input Capture Timing Diagram
TIMER CLOCK
FF01
FF02
FF03
COUNTER REGISTER
ICAPi PIN
ICAPi FLAG
FF03
ICAPi REGISTER
Note: The rising edge is the active edge.
60/171
ST72260G, ST72262G, ST72264G
16-BIT TIMER (Cont’d)
11.3.3.4 Output Compare
– The OCMPi pin takes OLVLi bit value (OCMPi
pin latch is forced low during reset).
In this section, the index, i, may be 1 or 2 because
there are 2 output compare functions in the 16-bit
timer.
– A timer interrupt is generated if the OCIE bit is
set in the CR1 register and the I bit is cleared in
the CC register (CC).
This function can be used to control an output
waveform or indicate when a period of time has
elapsed.
The OCiR register value required for a specific tim-
ing application can be calculated using the follow-
ing formula:
When a match is found between the Output Com-
pare register and the free running counter, the out-
put compare function:
– Assigns pins with a programmable value if the
OCiE bit is set
∆t f
* CPU
PRESC
∆ OCiR =
– Sets a flag in the status register
– Generates an interrupt if enabled
Where:
∆t
= Output compare period (in seconds)
= CPU clock frequency (in hertz)
Two 16-bit registers Output Compare Register 1
(OC1R) and Output Compare Register 2 (OC2R)
contain the value to be compared to the counter
register each timer clock cycle.
f
CPU
PRESC
= Timer prescaler factor (2, 4 or 8 de-
pending on CC[1:0] bits, see Table 14
Clock Control Bits)
MS Byte
OCiHR
LS Byte
OCiLR
OCiR
If the timer clock is an external clock, the formula
is:
These registers are readable and writable and are
not affected by the timer hardware. A reset event
changes the OCiR value to 8000h.
∆ OCiR = ∆t f
* EXT
Timing resolution is one count of the free running
Where:
counter: (f
).
CC[1:0]
CPU/
∆t
= Output compare period (in seconds)
= External timer clock frequency (in hertz)
f
EXT
Procedure:
To use the output compare function, select the fol-
lowing in the CR2 register:
Clearing the output compare interrupt request (i.e.
clearing the OCFi bit) is done by:
– Set the OCiE bit if an output is needed then the
OCMPi pin is dedicated to the output compare i
signal.
1. Reading the SR register while the OCFi bit is
set.
2. An access (read or write) to the OCiLR register.
– Select the timer clock (CC[1:0]) (see Table 14
Clock Control Bits).
The following procedure is recommended to pre-
vent the OCFi bit from being set between the time
it is read and the write to the OCiR register:
And select the following in the CR1 register:
– Select the OLVLi bit to applied to the OCMPi pins
after the match occurs.
– Write to the OCiHR register (further compares
are inhibited).
– Set the OCIE bit to generate an interrupt if it is
needed.
– Read the SR register (first step of the clearance
of the OCFi bit, which may be already set).
When a match is found between OCRi register
and CR register:
– Write to the OCiLR register (enables the output
compare function and clears the OCFi bit).
– OCFi bit is set.
61/171
ST72260G, ST72262G, ST72264G
16-BIT TIMER (Cont’d)
Notes:
1. After a processor write cycle to the OCiHR reg-
ister, the output compare function is inhibited
until the OCiLR register is also written.
Forced Compare Output capability
When the FOLVi bit is set by software, the OLVLi
bit is copied to the OCMPi pin. The OLVi bit has to
be toggled in order to toggle the OCMPi pin when
it is enabled (OCiE bit=1). The OCFi bit is then not
set by hardware, and thus no interrupt request is
generated.
2. If the OCiE bit is not set, the OCMPi pin is a
general I/O port and the OLVLi bit will not
appear when a match is found but an interrupt
could be generated if the OCIE bit is set.
3. When the timer clock is f
/2, OCFi and
The FOLVLi bits have no effect in both one pulse
mode and PWM mode.
CPU
OCMPi are set while the counter value equals
the OCiR register value (see Figure 43 on page
63). This behaviour is the same in OPM or
PWM mode.
When the timer clock is f
/4, f
/8 or in
CPU
CPU
external clock mode, OCFi and OCMPi are set
while the counter value equals the OCiR regis-
ter value plus 1 (see Figure 44 on page 63).
4. The output compare functions can be used both
for generating external events on the OCMPi
pins even if the input capture mode is also
used.
5. The value in the 16-bit OCiR register and the
OLVi bit should be changed after each suc-
cessful comparison in order to control an output
waveform or establish a new elapsed timeout.
Figure 42. Output Compare Block Diagram
16 BIT FREE RUNNING
OC1E
CC1 CC0
OC2E
COUNTER
(Control Register 2) CR2
16-bit
(Control Register 1) CR1
OUTPUT COMPARE
CIRCUIT
Latch
1
OCIE
FOLV2 FOLV1OLVL2
OLVL1
OCMP1
Pin
16-bit
16-bit
Latch
2
OCMP2
Pin
OC1R Register
OCF1
OCF2
0
0
0
OC2R Register
(Status Register) SR
62/171
ST72260G, ST72262G, ST72264G
16-BIT TIMER (Cont’d)
Figure 43. Output Compare Timing Diagram, f
=f
/2
TIMER
CPU
INTERNAL CPU CLOCK
TIMER CLOCK
COUNTER REGISTER
2ECF 2ED0 2ED1 2ED2
2ED3
2ED4
2ED3
OUTPUT COMPARE REGISTER i (OCRi)
OUTPUT COMPARE FLAG i (OCFi)
OCMPi PIN (OLVLi=1)
Figure 44. Output Compare Timing Diagram, f
=f
/4
TIMER
CPU
INTERNAL CPU CLOCK
TIMER CLOCK
2ECF 2ED0 2ED1 2ED2
2ED3
2ED4
2ED3
COUNTER REGISTER
OUTPUT COMPARE REGISTER i (OCRi)
COMPARE REGISTER i LATCH
OUTPUT COMPARE FLAG i (OCFi)
OCMPi PIN (OLVLi=1)
63/171
ST72260G, ST72262G, ST72264G
16-BIT TIMER (Cont’d)
11.3.3.5 One Pulse Mode
Clearing the Input Capture interrupt request (i.e.
clearing the ICFi bit) is done in two steps:
One Pulse mode enables the generation of a
pulse when an external event occurs. This mode is
selected via the OPM bit in the CR2 register.
1. Reading the SR register while the ICFi bit is set.
2. An access (read or write) to the ICiLR register.
The one pulse mode uses the Input Capture1
function and the Output Compare1 function.
The OC1R register value required for a specific
timing application can be calculated using the fol-
lowing formula:
Procedure:
t * f
To use one pulse mode:
CPU
- 5
OCiR Value =
1. Load the OC1R register with the value corre-
sponding to the length of the pulse (see the for-
mula in the opposite column).
PRESC
Where:
t
= Pulse period (in seconds)
2. Select the following in the CR1 register:
f
= CPU clock frequency (in hertz)
CPU
PRESC
– Using the OLVL1 bit, select the level to be ap-
plied to the OCMP1 pin after the pulse.
= Timer prescaler factor (2, 4 or 8 depend-
ing on the CC[1:0] bits, see Table 14
Clock Control Bits)
– Using the OLVL2 bit, select the level to be ap-
plied to the OCMP1 pin during the pulse.
If the timer clock is an external clock the formula is:
– Select the edge of the active transition on the
ICAP1 pin with the IEDG1 bit (the ICAP1 pin
must be configured as floating input).
OCiR = t f
-5
* EXT
Where:
t
3. Select the following in the CR2 register:
= Pulse period (in seconds)
– Set the OC1E bit, the OCMP1 pin is then ded-
icated to the Output Compare 1 function.
f
= External timer clock frequency (in hertz)
EXT
– Set the OPM bit.
When the value of the counter is equal to the value
of the contents of the OC1R register, the OLVL1
bit is output on the OCMP1 pin, (See Figure 45).
– Select the timer clock CC[1:0] (see Table 14
Clock Control Bits).
One pulse mode cycle
Notes:
ICR1 = Counter
When
1. The OCF1 bit cannot be set by hardware in one
pulse mode but the OCF2 bit can generate an
Output Compare interrupt.
OCMP1 = OLVL2
event occurs
on ICAP1
Counter is reset
2. When the Pulse Width Modulation (PWM) and
One Pulse Mode (OPM) bits are both set, the
PWM mode is the only active one.
to FFFCh
ICF1 bit is set
3. If OLVL1=OLVL2 a continuous signal will be
seen on the OCMP1 pin.
When
Counter
OCMP1 = OLVL1
= OC1R
4. The ICAP1 pin can not be used to perform input
capture. The ICAP2 pin can be used to perform
input capture (ICF2 can be set and IC2R can be
loaded) but the user must take care that the
counter is reset each time a valid edge occurs
on the ICAP1 pin and ICF1 can also generates
interrupt if ICIE is set.
Then, on a valid event on the ICAP1 pin, the coun-
ter is initialized to FFFCh and OLVL2 bit is loaded
on the OCMP1 pin, the ICF1 bit is set and the val-
ue FFFDh is loaded in the IC1R register.
Because the ICF1 bit is set when an active edge
occurs, an interrupt can be generated if the ICIE
bit is set.
5. When one pulse mode is used OC1R is dedi-
cated to this mode. Nevertheless OC2R and
OCF2 can be used to indicate a period of time
has been elapsed but cannot generate an out-
put waveform because the level OLVL2 is dedi-
cated to the one pulse mode.
64/171
ST72260G, ST72262G, ST72264G
16-BIT TIMER (Cont’d)
Figure 45. One Pulse Mode Timing Example
2ED3
01F8
IC1R
FFFC FFFD FFFE
2ED0 2ED1 2ED2
2ED3
FFFC FFFD
01F8
COUNTER
ICAP1
OLVL2
OLVL1
OLVL2
OCMP1
compare1
Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1
Figure 46. Pulse Width Modulation Mode Timing Example with 2 Output Compare Functions
2ED0 2ED1 2ED2
34E2 FFFC
FFFC FFFD FFFE
34E2
COUNTER
OCMP1
OLVL2
OLVL1
OLVL2
compare2
compare1
compare2
Note: OC1R=2ED0h, OC2R=34E2, OLVL1=0, OLVL2= 1
Note: On timers with only 1 Output Compare register, a fixed frequency PWM signal can be generated us-
ing the output compare and the counter overflow to define the pulse length.
65/171
ST72260G, ST72262G, ST72264G
16-BIT TIMER (Cont’d)
11.3.3.6 Pulse Width Modulation Mode
If OLVL1=1 and OLVL2=0 the length of the posi-
tive pulse is the difference between the OC2R and
OC1R registers.
Pulse Width Modulation (PWM) mode enables the
generation of a signal with a frequency and pulse
length determined by the value of the OC1R and
OC2R registers.
If OLVL1=OLVL2 a continuous signal will be seen
on the OCMP1 pin.
Pulse Width Modulation mode uses the complete
Output Compare 1 function plus the OC2R regis-
ter, and so this functionality can not be used when
PWM mode is activated.
The OCiR register value required for a specific tim-
ing application can be calculated using the follow-
ing formula:
t * f
CPU
PRESC
- 5
OCiR Value =
In PWM mode, double buffering is implemented on
the output compare registers. Any new values writ-
ten in the OC1R and OC2R registers are taken
into account only at the end of the PWM period
(OC2) to avoid spikes on the PWM output pin
(OCMP1).
Where:
t
= Signal or pulse period (in seconds)
= CPU clock frequency (in hertz)
f
CPU
PRESC
= Timer prescaler factor (2, 4 or 8 depend-
ing on CC[1:0] bits, see Table 14 Clock
Control Bits)
Procedure
To use pulse width modulation mode:
If the timer clock is an external clock the formula is:
1. Load the OC2R register with the value corre-
sponding to the period of the signal using the
formula in the opposite column.
OCiR = t f
-5
* EXT
2. Load the OC1R register with the value corre-
sponding to the period of the pulse if (OLVL1=0
and OLVL2=1) using the formula in the oppo-
site column.
Where:
t
= Signal or pulse period (in seconds)
f
= External timer clock frequency (in hertz)
EXT
3. Select the following in the CR1 register:
The Output Compare 2 event causes the counter
to be initialized to FFFCh (See Figure 46)
– Using the OLVL1 bit, select the level to be ap-
plied to the OCMP1 pin after a successful
comparison with the OC1R register.
Notes:
– Using the OLVL2 bit, select the level to be ap-
plied to the OCMP1 pin after a successful
comparison with the OC2R register.
1. After a write instruction to the OCiHR register,
the output compare function is inhibited until the
OCiLR register is also written.
4. Select the following in the CR2 register:
2. The OCF1 and OCF2 bits cannot be set by
hardware in PWM mode therefore the Output
Compare interrupt is inhibited.
– Set OC1E bit: the OCMP1 pin is then dedicat-
ed to the output compare 1 function.
3. The ICF1 bit is set by hardware when the coun-
ter reaches the OC2R value and can produce a
timer interrupt if the ICIE bit is set and the I bit is
cleared.
– Set the PWM bit.
– Select the timer clock (CC[1:0]) (see Table 14
Clock Control Bits).
Pulse Width Modulation cycle
4. In PWM mode the ICAP1 pin can not be used
to perform input capture because it is discon-
nected to the timer. The ICAP2 pin can be used
to perform input capture (ICF2 can be set and
IC2R can be loaded) but the user must take
care that the counter is reset each period and
ICF1 can also generates interrupt if ICIE is set.
When
Counter
= OC1R
OCMP1 = OLVL1
OCMP1 = OLVL2
5. When the Pulse Width Modulation (PWM) and
One Pulse Mode (OPM) bits are both set, the
PWM mode is the only active one.
When
Counter
= OC2R
Counter is reset
to FFFCh
ICF1 bit is set
66/171
ST72260G, ST72262G, ST72264G
16-BIT TIMER (Cont’d)
11.3.4 Low Power Modes
Mode
Description
No effect on 16-bit Timer.
Timer interrupts cause the device to exit from WAIT mode.
WAIT
HALT
16-bit Timer registers are frozen.
In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous
count when the MCU is woken up by an interrupt with “exit from HALT mode” capability or from the counter
reset value when the MCU is woken up by a RESET.
If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is armed. Consequent-
ly, when the MCU is woken up by an interrupt with “exit from HALT mode” capability, the ICFi bit is set, and
the counter value present when exiting from HALT mode is captured into the ICiR register.
11.3.5 Interrupts
Enable
Control from
Bit
Exit
Exit
from
Halt
Event
Flag
Interrupt Event
Wait
Yes
Yes
Yes
Yes
Yes
Input Capture 1 event/Counter reset in PWM mode
Input Capture 2 event
ICF1
ICF2
No
No
No
No
No
ICIE
Output Compare 1 event (not available in PWM mode)
Output Compare 2 event (not available in PWM mode)
Timer Overflow event
OCF1
OCF2
TOF
OCIE
TOIE
Note: The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts chap-
ter). These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt
mask in the CC register is reset (RIM instruction).
11.3.6 Summary of Timer modes
TIMER RESOURCES
MODES
Input Capture 1
Input Capture 2
Yes
Output Compare 1 Output Compare 2
Input Capture (1 and/or 2)
Output Compare (1 and/or 2)
One Pulse Mode
Yes
Yes
No
Yes
Yes
No
Yes
Yes
Yes
1)
3)
2)
Not Recommended
Not Recommended
Partially
No
PWM Mode
No
No
1) See note 4 in Section 11.3.3.5 "One Pulse Mode" on page 64
2) See note 5 in Section 11.3.3.5 "One Pulse Mode" on page 64
3) See note 4 in Section 11.3.3.6 "Pulse Width Modulation Mode" on page 66
67/171
ST72260G, ST72262G, ST72264G
16-BIT TIMER (Cont’d)
11.3.7 Register Description
Bit 4 = FOLV2 Forced Output Compare 2.
This bit is set and cleared by software.
0: No effect on the OCMP2 pin.
1: Forces the OLVL2 bit to be copied to the
OCMP2 pin, if the OC2E bit is set and even if
there is no successful comparison.
Each Timer is associated with three control and
status registers, and with six pairs of data registers
(16-bit values) relating to the two input captures,
the two output compares, the counter and the al-
ternate counter.
Bit 3 = FOLV1 Forced Output Compare 1.
This bit is set and cleared by software.
0: No effect on the OCMP1 pin.
CONTROL REGISTER 1 (CR1)
Read/Write
1: Forces OLVL1 to be copied to the OCMP1 pin, if
the OC1E bit is set and even if there is no suc-
cessful comparison.
Reset Value: 0000 0000 (00h)
7
0
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
Bit 2 = OLVL2 Output Level 2.
This bit is copied to the OCMP2 pin whenever a
successful comparison occurs with the OC2R reg-
ister and OCxE is set in the CR2 register. This val-
ue is copied to the OCMP1 pin in One Pulse Mode
and Pulse Width Modulation mode.
Bit 7 = ICIE Input Capture Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the
ICF1 or ICF2 bit of the SR register is set.
Bit 6 = OCIE Output Compare Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the
Bit 1 = IEDG1 Input Edge 1.
This bit determines which type of level transition
on the ICAP1 pin will trigger the capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
OCF1 or OCF2 bit of the SR register is set.
Bit 5 = TOIE Timer Overflow Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is enabled whenever the TOF
Bit 0 = OLVL1 Output Level 1.
The OLVL1 bit is copied to the OCMP1 pin when-
ever a successful comparison occurs with the
OC1R register and the OC1E bit is set in the CR2
register.
bit of the SR register is set.
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ST72260G, ST72262G, ST72264G
16-BIT TIMER (Cont’d)
CONTROL REGISTER 2 (CR2)
Read/Write
Bit 4 = PWM Pulse Width Modulation.
0: PWM mode is not active.
1: PWM mode is active, the OCMP1 pin outputs a
programmable cyclic signal; the length of the
pulse depends on the value of OC1R register;
the period depends on the value of OC2R regis-
ter.
Reset Value: 0000 0000 (00h)
7
0
OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG
Bit 3, 2 = CC[1:0] Clock Control.
Bit 7 = OC1E Output Compare 1 Pin Enable.
This bit is used only to output the signal from the
timer on the OCMP1 pin (OLV1 in Output Com-
pare mode, both OLV1 and OLV2 in PWM and
one-pulse mode). Whatever the value of the OC1E
bit, the Output Compare 1 function of the timer re-
mains active.
0: OCMP1 pin alternate function disabled (I/O pin
free for general-purpose I/O).
1: OCMP1 pin alternate function enabled.
The timer clock mode depends on these bits:
Table 14. Clock Control Bits
Timer Clock
fCPU / 4
CC1
CC0
0
0
1
0
1
0
fCPU / 2
fCPU / 8
External Clock (where
available)
1
1
Bit 6 = OC2E Output Compare 2 Pin Enable.
This bit is used only to output the signal from the
timer on the OCMP2 pin (OLV2 in Output Com-
pare mode). Whatever the value of the OC2E bit,
the Output Compare 2 function of the timer re-
mains active.
0: OCMP2 pin alternate function disabled (I/O pin
free for general-purpose I/O).
1: OCMP2 pin alternate function enabled.
Note: If the external clock pin is not available, pro-
gramming the external clock configuration stops
the counter.
Bit 1 = IEDG2 Input Edge 2.
This bit determines which type of level transition
on the ICAP2 pin will trigger the capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
Bit 5 = OPM One Pulse Mode.
0: One Pulse Mode is not active.
Bit 0 = EXEDG External Clock Edge.
1: One Pulse Mode is active, the ICAP1 pin can be
used to trigger one pulse on the OCMP1 pin; the
active transition is given by the IEDG1 bit. The
length of the generated pulse depends on the
contents of the OC1R register.
This bit determines which type of level transition
on the external clock pin EXTCLK will trigger the
counter register.
0: A falling edge triggers the counter register.
1: A rising edge triggers the counter register.
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ST72260G, ST72262G, ST72264G
16-BIT TIMER (Cont’d)
CONTROL/STATUS REGISTER (CSR)
Read Only (except bit 2 R/W)
Reset Value: xxxx x0xx (xxh)
7
Note: Reading or writing the ACLR register does
not clear TOF.
Bit 4 = ICF2 Input Capture Flag 2.
0: No input capture (reset value).
1: An input capture has occurred on the ICAP2
pin. To clear this bit, first read the SR register,
then read or write the low byte of the IC2R
(IC2LR) register.
0
0
ICF1 OCF1 TOF ICF2 OCF2 TIMD
0
Bit 7 = ICF1 Input Capture Flag 1.
0: No input capture (reset value).
1: An input capture has occurred on the ICAP1 pin
or the counter has reached the OC2R value in
PWM mode. To clear this bit, first read the SR
register, then read or write the low byte of the
IC1R (IC1LR) register.
Bit 3 = OCF2 Output Compare Flag 2.
0: No match (reset value).
1: The content of the free running counter has
matched the content of the OC2R register. To
clear this bit, first read the SR register, then read
or write the low byte of the OC2R (OC2LR) reg-
ister.
Bit 6 = OCF1 Output Compare Flag 1.
0: No match (reset value).
1: The content of the free running counter has
matched the content of the OC1R register. To
clear this bit, first read the SR register, then read
or write the low byte of the OC1R (OC1LR) reg-
ister.
Bit 2 = TIMD Timer disable.
This bit is set and cleared by software. When set, it
freezes the timer prescaler and counter and disa-
bled the output functions (OCMP1 and OCMP2
pins) to reduce power consumption. Access to the
timer registers is still available, allowing the timer
configuration to be changed, or the counter reset,
while it is disabled.
Bit 5 = TOF Timer Overflow Flag.
0: No timer overflow (reset value).
1:The free running counter rolled over from FFFFh
to 0000h. To clear this bit, first read the SR reg-
ister, then read or write the low byte of the CR
(CLR) register.
0: Timer enabled
1: Timer prescaler, counter and outputs disabled
Bits 1:0 = Reserved, must be kept cleared.
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ST72260G, ST72262G, ST72264G
16-BIT TIMER (Cont’d)
INPUT CAPTURE 1 HIGH REGISTER (IC1HR)
OUTPUT COMPARE
(OC1HR)
1
HIGH REGISTER
Read Only
Reset Value: Undefined
Read/Write
Reset Value: 1000 0000 (80h)
This is an 8-bit read only register that contains the
high part of the counter value (transferred by the
input capture 1 event).
This is an 8-bit register that contains the high part
of the value to be compared to the CHR register.
7
0
7
0
MSB
LSB
MSB
LSB
INPUT CAPTURE 1 LOW REGISTER (IC1LR)
OUTPUT COMPARE
(OC1LR)
1
LOW REGISTER
Read Only
Reset Value: Undefined
Read/Write
Reset Value: 0000 0000 (00h)
This is an 8-bit read only register that contains the
low part of the counter value (transferred by the in-
put capture 1 event).
This is an 8-bit register that contains the low part of
the value to be compared to the CLR register.
7
0
7
0
MSB
LSB
MSB
LSB
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ST72260G, ST72262G, ST72264G
16-BIT TIMER (Cont’d)
OUTPUT COMPARE
(OC2HR)
2
HIGH REGISTER
ALTERNATE COUNTER HIGH REGISTER
(ACHR)
Read/Write
Reset Value: 1000 0000 (80h)
Read Only
Reset Value: 1111 1111 (FFh)
This is an 8-bit register that contains the high part
of the value to be compared to the CHR register.
This is an 8-bit register that contains the high part
of the counter value.
7
0
7
0
MSB
LSB
MSB
LSB
OUTPUT COMPARE
(OC2LR)
2
LOW REGISTER
ALTERNATE COUNTER LOW REGISTER
(ACLR)
Read/Write
Reset Value: 0000 0000 (00h)
Read Only
Reset Value: 1111 1100 (FCh)
This is an 8-bit register that contains the low part of
the value to be compared to the CLR register.
This is an 8-bit register that contains the low part of
the counter value. A write to this register resets the
counter. An access to this register after an access
to CSR register does not clear the TOF bit in the
CSR register.
7
0
MSB
LSB
7
0
COUNTER HIGH REGISTER (CHR)
MSB
LSB
Read Only
Reset Value: 1111 1111 (FFh)
INPUT CAPTURE 2 HIGH REGISTER (IC2HR)
This is an 8-bit register that contains the high part
of the counter value.
Read Only
Reset Value: Undefined
7
0
This is an 8-bit read only register that contains the
high part of the counter value (transferred by the
Input Capture 2 event).
MSB
LSB
7
0
MSB
LSB
COUNTER LOW REGISTER (CLR)
Read Only
Reset Value: 1111 1100 (FCh)
This is an 8-bit register that contains the low part of
the counter value. A write to this register resets the
counter. An access to this register after accessing
the CSR register clears the TOF bit.
INPUT CAPTURE 2 LOW REGISTER (IC2LR)
Read Only
Reset Value: Undefined
This is an 8-bit read only register that contains the
low part of the counter value (transferred by the In-
put Capture 2 event).
7
0
MSB
LSB
7
0
MSB
LSB
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ST72260G, ST72262G, ST72264G
16-BIT TIMER (Cont’d)
Table 15. 16-Bit Timer Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
Timer A: 32 CR1
ICIE
0
OCIE
0
TOIE
0
FOLV2
0
FOLV1
0
OLVL2
0
IEDG1
0
OLVL1
0
Timer B: 42 Reset Value
Timer A: 31 CR2
OC1E
0
OC2E
0
OPM
0
PWM
0
CC1
0
CC0
0
IEDG2
0
EXEDG
0
Timer B: 41 Reset Value
Timer A: 33 CSR
ICF1
x
OCF1
x
TOF
x
ICF2
x
OCF2
x
TIMD
0
-
-
Timer B: 43 Reset Value
x
x
Timer A: 34 IC1HR
MSB
-
LSB
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Timer B: 44 Reset Value
Timer A: 35 IC1LR
MSB
-
LSB
-
Timer B: 45 Reset Value
Timer A: 36 OC1HR
MSB
-
LSB
-
Timer B: 46 Reset Value
Timer A: 37 OC1LR
MSB
-
LSB
-
Timer B: 47 Reset Value
Timer A: 3E OC2HR
MSB
-
LSB
-
Timer B: 4E Reset Value
Timer A: 3F OC2LR
MSB
-
LSB
-
Timer B: 4F Reset Value
Timer A: 38 CHR
MSB
1
LSB
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
Timer B: 48 Reset Value
Timer A: 39 CLR
MSB
1
LSB
0
Timer B: 49 Reset Value
Timer A: 3A ACHR
MSB
1
LSB
1
Timer B: 4A Reset Value
Timer A: 3B ACLR
MSB
1
LSB
0
1
-
1
-
1
-
1
-
1
-
0
-
Timer B: 4B Reset Value
Timer A: 3C ICHR2
MSB
-
LSB
-
Timer B: 4C Reset Value
Timer A: 3D ICLR2
MSB
-
LSB
-
-
-
-
-
-
-
Timer B: 4D Reset Value
73/171
ST72260G, ST72262G, ST72264G
11.4 SERIAL PERIPHERAL INTERFACE (SPI)
11.4.1 Introduction
11.4.3 General Description
The Serial Peripheral Interface (SPI) allows full-
duplex, synchronous, serial communication with
external devices. An SPI system may consist of a
master and one or more slaves or a system in
which devices may be either masters or slaves.
Figure 47 shows the serial peripheral interface
(SPI) block diagram. There are 3 registers:
– SPI Control Register (SPICR)
– SPI Control/Status Register (SPICSR)
– SPI Data Register (SPIDR)
11.4.2 Main Features
■ Full duplex synchronous transfers (on 3 lines)
■ Simplex synchronous transfers (on 2 lines)
■ Master or slave operation
The SPI is connected to external devices through
3 pins:
– MISO: Master In / Slave Out data
– MOSI: Master Out / Slave In data
■ Six master mode frequencies (f
/4 max.)
CPU
■ f
CPU
/2 max. slave mode frequency
– SCK: Serial Clock out by SPI masters and in-
put by SPI slaves
■ SS Management by software or hardware
■ Programmable clock polarity and phase
■ End of transfer interrupt flag
– SS: Slave select:
This input signal acts as a ‘chip select’ to let
the SPI master communicate with slaves indi-
vidually and to avoid contention on the data
lines. Slave SS inputs can be driven by stand-
ard I/O ports on the master Device.
■ Write collision, Master Mode Fault and Overrun
flags
Figure 47. Serial Peripheral Interface Block Diagram
Data/Address Bus
Read
SPIDR
Interrupt
request
Read Buffer
MOSI
7
0
SPICSR
MISO
8-Bit Shift Register
SPIF WCOL OVR MODF
0
SOD SSM SSI
Write
SOD
bit
1
SS
SPI
STATE
0
SCK
CONTROL
7
0
SPICR
MSTR
CPHA SPR1 SPR0
SPIE SPE SPR2
CPOL
MASTER
CONTROL
SERIAL CLOCK
GENERATOR
SS
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ST72260G, ST72262G, ST72264G
SERIAL PERIPHERAL INTERFACE (Cont’d)
11.4.3.1 Functional Description
sponds by sending data to the master device via
the MISO pin. This implies full duplex communica-
tion with both data out and data in synchronized
with the same clock signal (which is provided by
the master device via the SCK pin).
A basic example of interconnections between a
single master and a single slave is illustrated in
Figure 48.
The MOSI pins are connected together and the
MISO pins are connected together. In this way
data is transferred serially between master and
slave (most significant bit first).
To use a single data line, the MISO and MOSI pins
must be connected at each node ( in this case only
simplex communication is possible).
Four possible data/clock timing relationships may
be chosen (see Figure 51) but master and slave
must be programmed with the same timing mode.
The communication is always initiated by the mas-
ter. When the master device transmits data to a
slave device via MOSI pin, the slave device re-
Figure 48. Single Master/ Single Slave Application
SLAVE
MASTER
MSBit
LSBit
MSBit
LSBit
MISO
MOSI
MISO
MOSI
8-BIT SHIFT REGISTER
8-BIT SHIFT REGISTER
SPI
CLOCK
GENERATOR
SCK
SS
SCK
SS
+5V
Not used if SS is managed
by software
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ST72260G, ST72262G, ST72264G
SERIAL PERIPHERAL INTERFACE (Cont’d)
11.4.3.2 Slave Select Management
In Slave Mode:
As an alternative to using the SS pin to control the
Slave Select signal, the application can choose to
manage the Slave Select signal by software. This
is configured by the SSM bit in the SPICSR regis-
ter (see Figure 50)
There are two cases depending on the data/clock
timing relationship (see Figure 49):
If CPHA=1 (data latched on 2nd clock edge):
– SS internal must be held low during the entire
transmission. This implies that in single slave
applications the SS pin either can be tied to
In software management, the external SS pin is
free for other application uses and the internal SS
signal level is driven by writing to the SSI bit in the
SPICSR register.
V
, or made free for standard I/O by manag-
SS
ing the SS function by software (SSM= 1 and
SSI=0 in the in the SPICSR register)
If CPHA=0 (data latched on 1st clock edge):
In Master mode:
– SS internal must be held low during byte
transmission and pulled high between each
byte to allow the slave to write to the shift reg-
ister. If SS is not pulled high, a Write Collision
error will occur when the slave writes to the
shift register (see Section 11.4.5.3).
– SS internal must be held high continuously
Figure 49. Generic SS Timing Diagram
Byte 3
Byte 2
MOSI/MISO
Master SS
Byte 1
Slave SS
(if CPHA=0)
Slave SS
(if CPHA=1)
Figure 50. Hardware/Software Slave Select Management
SSM bit
SSI bit
1
0
SS internal
SS external pin
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ST72260G, ST72262G, ST72264G
SERIAL PERIPHERAL INTERFACE (Cont’d)
11.4.3.3 Master Mode Operation
11.4.3.5 Slave Mode Operation
In master mode, the serial clock is output on the
SCK pin. The clock frequency, polarity and phase
are configured by software (refer to the description
of the SPICSR register).
In slave mode, the serial clock is received on the
SCK pin from the master device.
To operate the SPI in slave mode:
1. Write to the SPICSR register to perform the fol-
lowing actions:
Note: The idle state of SCK must correspond to
the polarity selected in the SPICSR register (by
pulling up SCK if CPOL=1 or pulling down SCK if
CPOL=0).
– Select the clock polarity and clock phase by
configuring the CPOL and CPHA bits (see
Figure 51).
Note: The slave must have the same CPOL
To operate the SPI in master mode, perform the
following two steps in order (if the SPICSR register
is not written first, the SPICR register setting may
be not taken into account):
and CPHA settings as the master.
– Manage the SS pin as described in Section
11.4.3.2 and Figure 49. If CPHA=1 SS must
be held low continuously. If CPHA=0 SS must
be held low during byte transmission and
pulled up between each byte to let the slave
write in the shift register.
1. Write to the SPICSR register:
– Select the clock frequency by configuring the
SPR[2:0] bits.
– Select the clock polarity and clock phase by
configuring the CPOL and CPHA bits. Figure
51 shows the four possible configurations.
Note: The slave must have the same CPOL
and CPHA settings as the master.
2. Write to the SPICR register to clear the MSTR
bit and set the SPE bit to enable the SPI I/O
functions.
11.4.3.6 Slave Mode Transmit Sequence
When software writes to the SPIDR register, the
data byte is loaded into the 8-bit shift register and
then shifted out serially to the MISO pin most sig-
nificant bit first.
– Either set the SSM bit and set the SSI bit or
clear the SSM bit and tie the SS pin high for
the complete byte transmit sequence.
2. Write to the SPICR register:
The transmit sequence begins when the slave de-
vice receives the clock signal and the most signifi-
cant bit of the data on its MOSI pin.
– Set the MSTR and SPE bits
Note: MSTR and SPE bits remain set only if
SS is high).
The transmit sequence begins when software
writes a byte in the SPIDR register.
When data transfer is complete:
– The SPIF bit is set by hardware
11.4.3.4 Master Mode Transmit Sequence
– An interrupt request is generated if SPIE bit is
set and interrupt mask in the CCR register is
cleared.
When software writes to the SPIDR register, the
data byte is loaded into the 8-bit shift register and
then shifted out serially to the MOSI pin most sig-
nificant bit first.
Clearing the SPIF bit is performed by the following
software sequence:
When data transfer is complete:
– The SPIF bit is set by hardware
1. An access to the SPICSR register while the
SPIF bit is set.
– An interrupt request is generated if the SPIE
bit is set and the interrupt mask in the CCR
register is cleared.
2. A write or a read to the SPIDR register.
Notes: While the SPIF bit is set, all writes to the
SPIDR register are inhibited until the SPICSR reg-
ister is read.
Clearing the SPIF bit is performed by the following
software sequence:
The SPIF bit can be cleared during a second
transmission; however, it must be cleared before
the second SPIF bit in order to prevent an Overrun
condition (see Section 11.4.5.2).
1. An access to the SPICSR register while the
SPIF bit is set
2. A read to the SPIDR register.
Note: While the SPIF bit is set, all writes to the
SPIDR register are inhibited until the SPICSR reg-
ister is read.
77/171
ST72260G, ST72262G, ST72264G
SERIAL PERIPHERAL INTERFACE (Cont’d)
11.4.4 Clock Phase and Clock Polarity
Figure 51, shows an SPI transfer with the four
combinations of the CPHA and CPOL bits. The di-
agram may be interpreted as a master or slave
timing diagram where the SCK pin, the MISO pin,
the MOSI pin are directly connected between the
master and the slave device.
Four possible timing relationships may be chosen
by software, using the CPOL and CPHA bits (See
Figure 51).
Note: The idle state of SCK must correspond to
the polarity selected in the SPICSR register (by
pulling up SCK if CPOL=1 or pulling down SCK if
CPOL=0).
Note: If CPOL is changed at the communication
byte boundaries, the SPI must be disabled by re-
setting the SPE bit.
The combination of the CPOL clock polarity and
CPHA (clock phase) bits selects the data capture
clock edge
Figure 51. Data Clock Timing Diagram
CPHA =1
SCK
(CPOL = 1)
SCK
(CPOL = 0)
Bit 4
Bit 4
Bit3
Bit3
Bit 2
Bit 2
Bit 1
Bit 1
LSBit
LSBit
MSBit Bit 6
MSBit Bit 6
Bit 5
Bit 5
MISO
(from master)
MOSI
(from slave)
SS
(to slave)
CAPTURE STROBE
CPHA =0
SCK
(CPOL = 1)
SCK
(CPOL = 0)
Bit 4
Bit 4
Bit3
Bit 2
Bit 2
Bit 1
Bit 1
LSBit
LSBit
MISO
(from master)
MSBit Bit 6
MSBit Bit 6
Bit 5
Bit 5
Bit3
MOSI
(from slave)
SS
(to slave)
CAPTURE STROBE
Note: This figure should not be used as a replacement for parametric information.
Refer to the Electrical Characteristics chapter.
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ST72260G, ST72262G, ST72264G
SERIAL PERIPHERAL INTERFACE (Cont’d)
11.4.5 Error Flags
11.4.5.2 Overrun Condition (OVR)
11.4.5.1 Master Mode Fault (MODF)
An overrun condition occurs, when the master de-
vice has sent a data byte and the slave device has
not cleared the SPIF bit issued from the previously
transmitted byte.
Master mode fault occurs when the master device
has its SS pin pulled low.
When a Master mode fault occurs:
When an Overrun occurs:
– The MODF bit is set and an SPI interrupt re-
quest is generated if the SPIE bit is set.
– The OVR bit is set and an interrupt request is
generated if the SPIE bit is set.
– The SPE bit is reset. This blocks all output
from the Device and disables the SPI periph-
eral.
In this case, the receiver buffer contains the byte
sent after the SPIF bit was last cleared. A read to
the SPIDR register returns this byte. All other
bytes are lost.
– The MSTR bit is reset, thus forcing the Device
into slave mode.
The OVR bit is cleared by reading the SPICSR
register.
Clearing the MODF bit is done through a software
sequence:
11.4.5.3 Write Collision Error (WCOL)
1. A read access to the SPICSR register while the
MODF bit is set.
A write collision occurs when the software tries to
write to the SPIDR register while a data transfer is
taking place with an external device. When this
happens, the transfer continues uninterrupted;
and the software write will be unsuccessful.
2. A write to the SPICR register.
Notes: To avoid any conflicts in an application
with multiple slaves, the SS pin must be pulled
high during the MODF bit clearing sequence. The
SPE and MSTR bits may be restored to their orig-
inal state during or after this clearing sequence.
Write collisions can occur both in master and slave
mode. See also Section 11.4.3.2 "Slave Select
Management" on page 76.
Hardware does not allow the user to set the SPE
and MSTR bits while the MODF bit is set except in
the MODF bit clearing sequence.
Note: a "read collision" will never occur since the
received data byte is placed in a buffer in which
access is always synchronous with the CPU oper-
ation.
In a slave device, the MODF bit can not be set, but
in a multi master configuration the Device can be in
slave mode with the MODF bit set.
The WCOL bit in the SPICSR register is set if a
write collision occurs.
The MODF bit indicates that there might have
been a multi-master conflict and allows software to
handle this using an interrupt routine and either
perform to a reset or return to an application de-
fault state.
No SPI interrupt is generated when the WCOL bit
is set (the WCOL bit is a status flag only).
Clearing the WCOL bit is done through a software
sequence (see Figure 52).
Figure 52. Clearing the WCOL bit (Write Collision Flag) Software Sequence
Clearing sequence after SPIF = 1 (end of a data byte transfer)
Read SPICSR
1st Step
RESULT
SPIF =0
WCOL=0
2nd Step
Read SPIDR
Clearing sequence before SPIF = 1 (during a data byte transfer)
Read SPICSR
1st Step
Note: Writing to the SPIDR regis-
RESULT
ter instead of reading it does not
reset the WCOL bit
2nd Step
Read SPIDR
WCOL=0
79/171
ST72260G, ST72262G, ST72264G
SERIAL PERIPHERAL INTERFACE (Cont’d)
11.4.5.4 Single Master and Multimaster
Configurations
For more security, the slave device may respond
to the master with the received data byte. Then the
master will receive the previous byte back from the
slave device if all MISO and MOSI pins are con-
nected and the slave has not written to its SPIDR
register.
There are two types of SPI systems:
– Single Master System
– Multimaster System
Other transmission security methods can use
ports for handshake lines or data bytes with com-
mand fields.
Single Master System
A typical single master system may be configured,
using a device as the master and four devices as
slaves (see Figure 53).
Multi-Master System
A multi-master system may also be configured by
the user. Transfer of master control could be im-
plemented using a handshake method through the
I/O ports or by an exchange of code messages
through the serial peripheral interface system.
The master device selects the individual slave de-
vices by using four pins of a parallel port to control
the four SS pins of the slave devices.
The SS pins are pulled high during reset since the
master device ports will be forced to be inputs at
that time, thus disabling the slave devices.
The multi-master system is principally handled by
the MSTR bit in the SPICR register and the MODF
bit in the SPICSR register.
Note: To prevent a bus conflict on the MISO line
the master allows only one active slave device
during a transmission.
Figure 53. Single Master / Multiple Slave Configuration
SS
SS
SS
SS
SCK
SCK
Slave
SCK
Slave
SCK
Slave
Slave
Device
Device
Device
Device
MOSI MISO
MOSI MISO
MOSI MISO
MOSI MISO
MOSI MISO
SCK
Master
Device
5V
SS
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ST72260G, ST72262G, ST72264G
SERIAL PERIPHERAL INTERFACE (Cont’d)
11.4.6 Low Power Modes
SS pin or the SSI bit in the SPICSR register) is low
when the Device enters Halt mode. So if Slave se-
lection is configured as external (see Section
11.4.3.2), make sure the master drives a low level
on the SS pin when the slave enters Halt mode.
Mode
Description
No effect on SPI.
WAIT
SPI interrupt events cause the Device to exit
from WAIT mode.
11.4.7 Interrupts
SPI registers are frozen.
In HALT mode, the SPI is inactive. SPI oper-
ation resumes when the Device is woken up
by an interrupt with “exit from HALT mode”
capability. The data received is subsequently
read from the SPIDR register when the soft-
ware is running (interrupt vector fetching). If
several data are received before the wake-
up event, then an overrun error is generated.
This error can be detected after the fetch of
the interrupt routine that woke up the Device.
Enable
Control from
Bit
Exit
Exit
from
Halt
Event
Flag
Interrupt Event
Wait
SPI End of Trans-
fer Event
HALT
SPIF
Yes
Yes
Master Mode
Fault Event
SPIE
MODF
OVR
Yes
Yes
No
No
Overrun Error
Note: The SPI interrupt events are connected to
the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding
Enable Control Bit is set and the interrupt mask in
the CC register is reset (RIM instruction).
11.4.6.1 Using the SPI to wake-up the Device
from Halt mode
In slave configuration, the SPI is able to wake-up
the Device from HALT mode through a SPIF inter-
rupt. The data received is subsequently read from
the SPIDR register when the software is running
(interrupt vector fetch). If multiple data transfers
have been performed before software clears the
SPIF bit, then the OVR bit is set by hardware.
Note: When waking up from Halt mode, if the SPI
remains in Slave mode, it is recommended to per-
form an extra communications cycle to bring the
SPI from Halt mode state to normal state. If the
SPI exits from Slave mode, it returns to normal
state immediately.
Caution: The SPI can wake-up the Device from
Halt mode only if the Slave Select signal (external
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ST72260G, ST72262G, ST72264G
SERIAL PERIPHERAL INTERFACE (Cont’d)
11.4.8 Register Description
CONTROL REGISTER (SPICR)
Read/Write
Bit 3 = CPOL Clock Polarity.
This bit is set and cleared by software. This bit de-
termines the idle state of the serial Clock. The
CPOL bit affects both the master and slave
modes.
0: SCK pin has a low level idle state
1: SCK pin has a high level idle state
Reset Value: 0000 xxxx (0xh)
7
0
SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0
Note: If CPOL is changed at the communication
byte boundaries, the SPI must be disabled by re-
setting the SPE bit.
Bit 7 = SPIE Serial Peripheral Interrupt Enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SPI interrupt is generated whenever an End
of Transfer event, Master Mode Fault or Over-
run error occurs (SPIF=1, MODF=1 or OVR=1
in the SPICSR register)
Bit 2 = CPHA Clock Phase.
This bit is set and cleared by software.
0: The first clock transition is the first data capture
edge.
1: The second clock transition is the first capture
edge.
Bit 6 = SPE Serial Peripheral Output Enable.
This bit is set and cleared by software. It is also
cleared by hardware when, in master mode, SS=0
(see Section 11.4.5.1 "Master Mode Fault
(MODF)" on page 79). The SPE bit is cleared by
reset, so the SPI peripheral is not initially connect-
ed to the external pins.
Note: The slave must have the same CPOL and
CPHA settings as the master.
Bits 1:0 = SPR[1:0] Serial Clock Frequency.
These bits are set and cleared by software. Used
with the SPR2 bit, they select the baud rate of the
SPI serial clock SCK output by the SPI in master
mode.
0: I/O pins free for general purpose I/O
1: SPI I/O pin alternate functions enabled
Note: These 2 bits have no effect in slave mode.
Bit 5 = SPR2 Divider Enable.
This bit is set and cleared by software and is
cleared by reset. It is used with the SPR[1:0] bits to
set the baud rate. Refer to Table 16 SPI Master
mode SCK Frequency.
0: Divider by 2 enabled
1: Divider by 2 disabled
Table 16. SPI Master mode SCK Frequency
Serial Clock
SPR2 SPR1 SPR0
f
f
/4
/8
1
0
0
1
0
0
0
0
0
1
1
1
0
0
1
0
0
1
CPU
CPU
f
f
f
/16
/32
/64
CPU
CPU
CPU
Note: This bit has no effect in slave mode.
Bit 4 = MSTR Master Mode.
This bit is set and cleared by software. It is also
cleared by hardware when, in master mode, SS=0
(see Section 11.4.5.1 "Master Mode Fault
(MODF)" on page 79).
f
/128
CPU
0: Slave mode
1: Master mode. The function of the SCK pin
changes from an input to an output and the func-
tions of the MISO and MOSI pins are reversed.
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ST72260G, ST72262G, ST72264G
SERIAL PERIPHERAL INTERFACE (Cont’d)
CONTROL/STATUS REGISTER (SPICSR)
Read/Write (some bits Read Only)
Reset Value: 0000 0000 (00h)
Bit 3 = Reserved, must be kept cleared.
Bit 2 = SOD SPI Output Disable.
7
0
This bit is set and cleared by software. When set, it
disables the alternate function of the SPI output
(MOSI in master mode / MISO in slave mode)
0: SPI output enabled (if SPE=1)
SPIF
WCOL OVR MODF
-
SOD SSM SSI
1: SPI output disabled
Bit 7 = SPIF Serial Peripheral Data Transfer Flag
(Read only).
Bit 1 = SSM SS Management.
This bit is set by hardware when a transfer has
been completed. An interrupt is generated if
SPIE=1 in the SPICR register. It is cleared by a
software sequence (an access to the SPICSR
register followed by a write or a read to the
SPIDR register).
This bit is set and cleared by software. When set, it
disables the alternate function of the SPI SS pin
and uses the SSI bit value instead. See Section
11.4.3.2 "Slave Select Management" on page 76.
0: Hardware management (SS managed by exter-
nal pin)
1: Software management (internal SS signal con-
trolled by SSI bit. External SS pin free for gener-
al-purpose I/O)
0: Data transfer is in progress or the flag has been
cleared.
1: Data transfer between the Device and an exter-
nal device has been completed.
Note: While the SPIF bit is set, all writes to the
SPIDR register are inhibited until the SPICSR reg-
ister is read.
Bit 0 = SSI SS Internal Mode.
This bit is set and cleared by software. It acts as a
‘chip select’ by controlling the level of the SS slave
select signal when the SSM bit is set.
0 : Slave selected
Bit 6 = WCOL Write Collision status (Read only).
This bit is set by hardware when a write to the
SPIDR register is done during a transmit se-
quence. It is cleared by a software sequence (see
Figure 52).
0: No write collision occurred
1: A write collision has been detected
1 : Slave deselected
DATA I/O REGISTER (SPIDR)
Read/Write
Reset Value: Undefined
7
0
Bit 5 = OVR SPI Overrun error (Read only).
This bit is set by hardware when the byte currently
being received in the shift register is ready to be
transferred into the SPIDR register while SPIF = 1
(See Section 11.4.5.2). An interrupt is generated if
SPIE = 1 in SPICSR register. The OVR bit is
cleared by software reading the SPICSR register.
0: No overrun error
D7
D6
D5
D4
D3
D2
D1
D0
The SPIDR register is used to transmit and receive
data on the serial bus. In a master device, a write
to this register will initiate transmission/reception
of another byte.
1: Overrun error detected
Notes: During the last clock cycle the SPIF bit is
set, a copy of the received data byte in the shift
register is moved to a buffer. When the user reads
the serial peripheral data I/O register, the buffer is
actually being read.
Bit 4 = MODF Mode Fault flag (Read only).
This bit is set by hardware when the SS pin is
pulled low in master mode (see Section 11.4.5.1
"Master Mode Fault (MODF)" on page 79). An SPI
interrupt can be generated if SPIE=1 in the SPIC-
SR register. This bit is cleared by a software se-
quence (An access to the SPICSR register while
MODF=1 followed by a write to the SPICR regis-
ter).
While the SPIF bit is set, all writes to the SPIDR
register are inhibited until the SPICSR register is
read.
Warning: A write to the SPIDR register places
data directly into the shift register for transmission.
A read to the SPIDR register returns the value lo-
cated in the buffer and not the content of the shift
register (see Figure 47).
0: No master mode fault detected
1: A fault in master mode has been detected
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ST72260G, ST72262G, ST72264G
SERIAL PERIPHERAL INTERFACE (Cont’d)
Table 17. SPI Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
SPIDR
Reset Value
MSB
x
LSB
x
0021h
0022h
0023h
x
x
x
x
x
x
SPICR
Reset Value
SPIE
0
SPE
0
SPR2
0
MSTR
0
CPOL
x
CPHA
x
SPR1
x
SPR0
x
SPICSR
Reset Value
SPIF
0
WCOL
0
OR
0
MODF
0
SOD
0
SSM
0
SSI
0
0
84/171
ST72260G, ST72262G, ST72264G
11.5 SERIAL COMMUNICATIONS INTERFACE (SCI)
11.5.1 Introduction
11.5.3 General Description
The Serial Communications Interface (SCI) offers
a flexible means of full-duplex data exchange with
external equipment requiring an industry standard
NRZ asynchronous serial data format. The SCI of-
fers a very wide range of baud rates using two
baud rate generator systems.
The interface is externally connected to another
device by two pins (see Figure 55):
– TDO: Transmit Data Output. When the transmit-
ter and the receiver are disabled, the output pin
returns to its I/O port configuration. When the
transmitter and/or the receiver are enabled and
nothing is to be transmitted, the TDO pin is at
high level.
11.5.2 Main Features
■ Full duplex, asynchronous communications
■ NRZ standard format (Mark/Space)
■ Dual baud rate generator systems
– RDI: Receive Data Input is the serial data input.
Oversampling techniques are used for data re-
covery by discriminating between valid incoming
data and noise.
■ Independently programmable transmit and
receive baud rates up to 500K baud.
■ Programmable data word length (8 or 9 bits)
Through these pins, serial data is transmitted and
received as frames comprising:
■ Receive buffer full, Transmit buffer empty and
– An Idle Line prior to transmission or reception
– A start bit
End of Transmission flags
■ Two receiver wake-up modes:
– Address bit (MSB)
– A data word (8 or 9 bits) least significant bit first
– A Stop bit indicating that the frame is complete.
Thisinterfaceusestwotypesofbaudrategenerator:
– Idle line
■ Mutingfunctionformultiprocessorconfigurations
– A conventional type for commonly-used baud
rates,
■ Separate enable bits for Transmitter and
Receiver
– An extended type with a prescaler offering a very
wide range of baud rates even with non-standard
oscillator frequencies.
■ Four error detection flags:
– Overrun error
– Noise error
– Frame error
– Parity error
■ Five interrupt sources with flags:
– Transmit data register empty
– Transmission complete
– Receive data register full
– Idle line received
– Overrun error detected
■ Parity control:
– Transmits parity bit
– Checks parity of received data byte
■ Reduced power consumption mode
85/171
ST72260G, ST72262G, ST72264G
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
Figure 54. SCI Block Diagram
Write
Read
(DATA REGISTER) DR
Received Data Register (RDR)
Received Shift Register
Transmit Data Register (TDR)
TDO
Transmit Shift Register
RDI
CR1
R8
T8 SCID
M WAKE PCE PS PIE
WAKE
UP
TRANSMIT
RECEIVER
CLOCK
RECEIVER
CONTROL
CONTROL
UNIT
CR2
SR
TIE TCIE RIE ILIE TE RE RWU SBK
TDRE TC RDRF IDLE OR NF FE
PE
SCI
INTERRUPT
CONTROL
TRANSMITTER
CLOCK
TRANSMITTER RATE
CONTROL
f
CPU
/PR
/16
BRR
SCP1SCP0 SCT2
SCT1SCT0SCR2 SCR1SCR0
RECEIVER RATE
CONTROL
CONVENTIONAL BAUD RATE GENERATOR
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ST72260G, ST72262G, ST72264G
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
11.5.4 Functional Description
11.5.4.1 Serial Data Format
The block diagram of the Serial Control Interface,
is shown in Figure 54. It contains 6 dedicated reg-
isters:
Word length may be selected as being either 8 or 9
bits by programming the M bit in the SCICR1 reg-
ister (see Figure 54).
– Two control registers (SCICR1 & SCICR2)
– A status register (SCISR)
The TDO pin is in low state during the start bit.
The TDO pin is in high state during the stop bit.
– A baud rate register (SCIBRR)
An Idle character is interpreted as an entire frame
of “1”s followed by the start bit of the next frame
which contains data.
– An extended prescaler receiver register (SCIER-
PR)
A Break character is interpreted on receiving “0”s
for some multiple of the frame period. At the end of
the last break frame the transmitter inserts an ex-
tra “1” bit to acknowledge the start bit.
– An extended prescaler transmitter register (SCI-
ETPR)
Refer to the register descriptions in Section
11.5.7for the definitions of each bit.
Transmission and reception are driven by their
own baud rate generator.
Figure 55. Word Length Programming
9-bit Word length (M bit is set)
Possible
Next Data Frame
Parity
Data Frame
Start
Bit
Next
Start
Bit
Stop
Bit
Bit2
Bit5
Bit6
Bit0
Bit1
Bit3
Bit4
Bit7 Bit8
Bit
Start
Bit
Idle Frame
Start
Bit
Extra
’1’
Break Frame
8-bit Word length (M bit is reset)
Possible
Parity
Next Data Frame
Data Frame
Start
Bit
Next
Start
Bit
Stop
Bit
Bit2
Bit6
Bit0
Bit1
Bit3
Bit4 Bit5
Bit7
Bit
Start
Bit
Idle Frame
Start
Bit
Extra
’1’
Break Frame
87/171
ST72260G, ST72262G, ST72264G
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
11.5.4.2 Transmitter
When a frame transmission is complete (after the
stop bit or after the break frame) the TC bit is set
and an interrupt is generated if the TCIE is set and
the I bit is cleared in the CCR register.
The transmitter can send data words of either 8 or
9 bits depending on the M bit status. When the M
bit is set, word length is 9 bits and the 9th bit (the
MSB) has to be stored in the T8 bit in the SCICR1
register.
Clearing the TC bit is performed by the following
software sequence:
1. An access to the SCISR register
2. A write to the SCIDR register
Character Transmission
During an SCI transmission, data shifts out least
significant bit first on the TDO pin. In this mode,
the SCIDR register consists of a buffer (TDR) be-
tween the internal bus and the transmit shift regis-
ter (see Figure 54).
Note: The TDRE and TC bits are cleared by the
same software sequence.
Break Characters
Setting the SBK bit loads the shift register with a
break character. The break frame length depends
on the M bit (see Figure 55).
Procedure
– Select the M bit to define the word length.
As long as the SBK bit is set, the SCI send break
frames to the TDO pin. After clearing this bit by
software the SCI insert a logic 1 bit at the end of
the last break frame to guarantee the recognition
of the start bit of the next frame.
– Select the desired baud rate using the SCIBRR
and the SCIETPR registers.
– Set the TE bit to assign the TDO pin to the alter-
nate function and to send a idle frame as first
transmission.
Idle Characters
– Access the SCISR register and write the data to
send in the SCIDR register (this sequence clears
the TDRE bit). Repeat this sequence for each
data to be transmitted.
Setting the TE bit drives the SCI to send an idle
frame before the first data frame.
Clearing and then setting the TE bit during a trans-
mission sends an idle frame after the current word.
Clearing the TDRE bit is always performed by the
following software sequence:
1. An access to the SCISR register
2. A write to the SCIDR register
Note: Resetting and setting the TE bit causes the
data in the TDR register to be lost. Therefore the
best time to toggle the TE bit is when the TDRE bit
is set i.e. before writing the next byte in the SCIDR.
The TDRE bit is set by hardware and it indicates:
– The TDR register is empty.
– The data transfer is beginning.
– The next data can be written in the SCIDR regis-
ter without overwriting the previous data.
This flag generates an interrupt if the TIE bit is set
and the I bit is cleared in the CCR register.
When a transmission is taking place, a write in-
struction to the SCIDR register stores the data in
the TDR register and which is copied in the shift
register at the end of the current transmission.
When no transmission is taking place, a write in-
struction to the SCIDR register places the data di-
rectly in the shift register, the data transmission
starts, and the TDRE bit is immediately set.
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ST72260G, ST72262G, ST72264G
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
11.5.4.3 Receiver
Overrun Error
The SCI can receive data words of either 8 or 9
bits. When the M bit is set, word length is 9 bits
and the MSB is stored in the R8 bit in the SCICR1
register.
An overrun error occurs when a character is re-
ceived when RDRF has not been reset. Data can
not be transferred from the shift register to the
RDR register as long as the RDRF bit is not
cleared.
Character reception
When a overrun error occurs:
– The OR bit is set.
During a SCI reception, data shifts in least signifi-
cant bit first through the RDI pin. In this mode, the
SCIDR register consists or a buffer (RDR) be-
tween the internal bus and the received shift regis-
ter (see Figure 54).
– The RDR content will not be lost.
– The shift register will be overwritten.
– An interrupt is generated if the RIE bit is set and
the I bit is cleared in the CCR register.
Procedure
– Select the M bit to define the word length.
The OR bit is reset by an access to the SCISR reg-
ister followed by a SCIDR register read operation.
– Select the desired baud rate using the SCIBRR
and the SCIERPR registers.
Noise Error
– Set the RE bit, this enables the receiver which
begins searching for a start bit.
Oversampling techniques are used for data recov-
ery by discriminating between valid incoming data
and noise.
When a character is received:
– The RDRF bit is set. It indicates that the content
of the shift register is transferred to the RDR.
When noise is detected in a frame:
– The NF is set at the rising edge of the RDRF bit.
– An interrupt is generated if the RIE bit is set and
the I bit is cleared in the CCR register.
– Data is transferred from the Shift register to the
SCIDR register.
– The error flags can be set if a frame error, noise
or an overrun error has been detected during re-
ception.
– No interrupt is generated. However this bit rises
at the same time as the RDRF bit which itself
generates an interrupt.
Clearing the RDRF bit is performed by the following
software sequence done by:
The NF bit is reset by a SCISR register read oper-
ation followed by a SCIDR register read operation.
1. An access to the SCISR register
2. A read to the SCIDR register.
Framing Error
A framing error is detected when:
The RDRF bit must be cleared before the end of the
reception of the next character to avoid an overrun
error.
– The stop bit is not recognized on reception at the
expected time, following either a de-synchroni-
zation or excessive noise.
Break Character
– A break is received.
When a break character is received, the SPI han-
dles it as a framing error.
When the framing error is detected:
– the FE bit is set by hardware
Idle Character
– Data is transferred from the Shift register to the
SCIDR register.
When a idle frame is detected, there is the same
procedure as a data received character plus an in-
terrupt if the ILIE bit is set and the I bit is cleared in
the CCR register.
– No interrupt is generated. However this bit rises
at the same time as the RDRF bit which itself
generates an interrupt.
The FE bit is reset by a SCISR register read oper-
ation followed by a SCIDR register read operation.
89/171
ST72260G, ST72262G, ST72264G
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
Figure 56. SCI Baud Rate and Extended Prescaler Block Diagram
TRANSMITTER
CLOCK
EXTENDED PRESCALER TRANSMITTER RATE CONTROL
SCIETPR
EXTENDED TRANSMITTER PRESCALER REGISTER
SCIERPR
EXTENDED RECEIVER PRESCALER REGISTER
RECEIVER
CLOCK
EXTENDED PRESCALER RECEIVER RATE CONTROL
EXTENDED PRESCALER
f
CPU
TRANSMITTER RATE
CONTROL
/PR
/16
SCIBRR
SCP1
SCT2
SCT1SCT0 SCR2 SCR1SCR0
SCP0
RECEIVER RATE
CONTROL
CONVENTIONAL BAUD RATE GENERATOR
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ST72260G, ST72262G, ST72264G
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
11.5.4.4 Conventional Baud Rate Generation
with:
The baud rate for the receiver and transmitter (Rx
and Tx) are set independently and calculated as
follows:
ETPR = 1,..,255 (see SCIETPR register)
ERPR = 1,.. 255 (see SCIERPR register)
11.5.4.6 Receiver Muting and Wake-up Feature
f
f
CPU
CPU
In multiprocessor configurations it is often desira-
ble that only the intended message recipient
should actively receive the full message contents,
thus reducing redundant SCI service overhead for
all non addressed receivers.
Rx =
Tx =
(16 PR) RR
(16 PR) TR
*
*
*
*
with:
PR = 1, 3, 4 or 13 (see SCP[1:0] bits)
TR = 1, 2, 4, 8, 16, 32, 64,128
(see SCT[2:0] bits)
The non addressed devices may be placed in
sleep mode by means of the muting function.
Setting the RWU bit by software puts the SCI in
sleep mode:
RR = 1, 2, 4, 8, 16, 32, 64,128
(see SCR[2:0] bits)
All the reception status bits can not be set.
All the receive interrupts are inhibited.
All these bits are in the SCIBRR register.
Example: If f is 8 MHz (normal mode) and if
PR=13 and TR=RR=1, the transmit and receive
baud rates are 38400 baud.
CPU
A muted receiver may be awakened by one of the
following two ways:
– by Idle Line detection if the WAKE bit is reset,
– by Address Mark detection if the WAKE bit is set.
Note: the baud rate registers MUST NOT be
changed while the transmitter or the receiver is en-
abled.
Receiver wakes-up by Idle Line detection when
the Receive line has recognised an Idle Frame.
Then the RWU bit is reset by hardware but the
IDLE bit is not set.
11.5.4.5 Extended Baud Rate Generation
The extended prescaler option gives a very fine
tuning on the baud rate, using a 255 value prescal-
er, whereas the conventional Baud Rate Genera-
tor retains industry standard software compatibili-
ty.
Receiver wakes-up by Address Mark detection
when it received a “1” as the most significant bit of
a word, thus indicating that the message is an ad-
dress. The reception of this particular word wakes
up the receiver, resets the RWU bit and sets the
RDRF bit, which allows the receiver to receive this
word normally and to use it as an address word.
The extended baud rate generator block diagram
is described in the Figure 56.
The output clock rate sent to the transmitter or to
the receiver will be the output from the 16 divider
divided by a factor ranging from 1 to 255 set in the
SCIERPR or the SCIETPR register.
Caution: In Mute mode, do not write to the
SCICR2 register. If the SCI is in Mute mode during
the read operation (RWU=1) and a address mark
wake up event occurs (RWU is reset) before the
write operation, the RWU bit will be set again by
this write operation. Consequently the address
byte is lost and the SCI is not woken up from Mute
mode.
Note: the extended prescaler is activated by set-
ting the SCIETPR or SCIERPR register to a value
other than zero. The baud rates are calculated as
follows:
f
f
CPU
CPU
Rx =
16 ERPR*(PR*RR)
Tx =
16 ETPR*(PR*TR)
*
*
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SERIAL COMMUNICATIONS INTERFACE (Cont’d)
11.5.4.7 Parity Control
(PS=0) or an odd number of “1s” if odd parity is se-
lected (PS=1). If the parity check fails, the PE flag
is set in the SCISR register and an interrupt is gen-
erated if PIE is set in the SCICR1 register.
Parity control (generation of parity bit in trasmis-
sion and and parity chencking in reception) can be
enabled by setting the PCE bit in the SCICR1 reg-
ister. Depending on the frame length defined by
the M bit, the possible SCI frame formats are as
listed in Table 18.
11.5.5 Low Power Modes
Mode
Description
Table 18. Frame Formats
No effect on SCI.
M bit
PCE bit
SCI frame
WAIT
SCI interrupts cause the device to exit
from Wait mode.
0
0
1
1
0
1
0
1
| SB | 8 bit data | STB |
| SB | 7-bit data | PB | STB |
| SB | 9-bit data | STB |
| SB | 8-bit data PB | STB |
SCI registers are frozen.
In Halt mode, the SCI stops transmit-
ting/receiving until Halt mode is exit-
ed.
HALT
Legend: SB = Start Bit, STB = Stop Bit,
PB = Parity Bit
Note: In case of wake up by an address mark, the
MSB bit of the data is taken into account and not
the parity bit
11.5.6 Interrupts
Interrupt Event
Enable Exit
Control from from
Exit
Event
Flag
Even parity: the parity bit is calculated to obtain
an even number of “1s” inside the frame made of
the 7 or 8 LSB bits (depending on whether M is
equal to 0 or 1) and the parity bit.
Bit
Wait
Halt
Transmit Data Register
Empty
TDRE
TC
TIE
Yes
No
Transmission Com-
plete
TCIE
RIE
Yes
Yes
No
No
Ex: data=00110101; 4 bits set => parity bit will be
0 if even parity is selected (PS bit = 0).
Received Data Ready
to be Read
RDRF
Odd parity: the parity bit is calculated to obtain an
odd number of “1s” inside the frame made of the 7
or 8 LSB bits (depending on whether M is equal to
0 or 1) and the parity bit.
Overrun Error Detected OR
Yes
Yes
Yes
No
No
No
Idle Line Detected
Parity Error
IDLE
PE
ILIE
PIE
Ex: data=00110101; 4 bits set => parity bit will be
1 if odd parity is selected (PS bit = 1).
The SCI interrupt events are connected to the
same interrupt vector.
Transmission mode: If the PCE bit is set then the
MSB bit of the data written in the data register is
not transmitted but is changed by the parity bit.
These events generate an interrupt if the corre-
sponding Enable Control Bit is set and the inter-
rupt mask in the CC register is reset (RIM instruc-
tion).
Reception mode: If the PCE bit is set then the in-
terface checks if the received data byte has an
even number of “1s” if even parity is selected
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SERIAL COMMUNICATIONS INTERFACE (Cont’d)
11.5.7 Register Description
Note: The IDLE bit will not be set again until the
RDRF bit has been set itself (i.e. a new idle line oc-
curs).
STATUS REGISTER (SCISR)
Read Only
Reset Value: 1100 0000 (C0h)
Bit 3 = OR Overrun error.
7
0
This bit is set by hardware when the word currently
being received in the shift register is ready to be
transferred into the RDR register while RDRF=1.
An interrupt is generated if RIE=1 in the SCICR2
register. It is cleared by a software sequence (an
access to the SCISR register followed by a read to
the SCIDR register).
TDRE
TC
RDRF IDLE
OR
NF
FE
PE
Bit 7 = TDRE Transmit data register empty.
This bit is set by hardware when the content of the
TDR register has been transferred into the shift
register. An interrupt is generated if the TIE bit=1
in the SCICR2 register. It is cleared by a software
sequence (an access to the SCISR register fol-
lowed by a write to the SCIDR register).
0: No Overrun error
1: Overrun error is detected
Note: When this bit is set RDR register content will
not be lost but the shift register will be overwritten.
0: Data is not transferred to the shift register
1: Data is transferred to the shift register
Bit 2 = NF Noise flag.
Note: Data will not be transferred to the shift reg-
This bit is set by hardware when noise is detected
on a received frame. It is cleared by a software se-
quence (an access to the SCISR register followed
by a read to the SCIDR register).
0: No noise is detected
ister unless the TDRE bit is cleared.
Bit 6 = TC Transmission complete.
This bit is set by hardware when transmission of a
frame containing Data, a Preamble or a Break is
complete. An interrupt is generated if TCIE=1 in
the SCICR2 register. It is cleared by a software se-
quence (an access to the SCISR register followed
by a write to the SCIDR register).
1: Noise is detected
Note: This bit does not generate interrupt as it ap-
pears at the same time as the RDRF bit which it-
self generates an interrupt.
0: Transmission is not complete
1: Transmission is complete
Bit 1 = FE Framing error.
This bit is set by hardware when a de-synchroniza-
tion, excessive noise or a break character is de-
tected. It is cleared by a software sequence (an
access to the SCISR register followed by a read to
the SCIDR register).
0: No Framing error is detected
1: Framing error or break character is detected
Note: TC is not set after the transmission of a Pre-
amble or a Break.
Bit 5 = RDRF Received data ready flag.
This bit is set by hardware when the content of the
RDR register has been transferred to the SCIDR
register. An interrupt is generated if RIE=1 in the
SCICR2 register. It is cleared by a software se-
quence (an access to the SCISR register followed
by a read to the SCIDR register).
Note: This bit does not generate interrupt as it ap-
pears at the same time as the RDRF bit which it-
self generates an interrupt. If the word currently
being transferred causes both frame error and
overrun error, it will be transferred and only the OR
bit will be set.
0: Data is not received
1: Received data is ready to be read
Bit 4 = IDLE Idle line detect.
This bit is set by hardware when a Idle Line is de-
tected. An interrupt is generated if the ILIE=1 in
the SCICR2 register. It is cleared by a software se-
quence (an access to the SCISR register followed
by a read to the SCIDR register).
0: No Idle Line is detected
1: Idle Line is detected
Bit 0 = PE Parity error.
This bit is set by hardware when a parity error oc-
curs in receiver mode. It is cleared by a software
sequence (a read to the status register followed by
an access to the SCIDR data register). An inter-
rupt is generated if PIE=1 in the SCICR1 register.
0: No parity error
1: Parity error
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SERIAL COMMUNICATIONS INTERFACE (Cont’d)
CONTROL REGISTER 1 (SCICR1)
Read/Write
Bit 3 = WAKE Wake-Up method.
This bit determines the SCI Wake-Up method, it is
set or cleared by software.
0: Idle Line
Reset Value: x000 0000 (x0h)
7
0
1: Address Mark
R8
T8
SCID
M
WAKE PCE
PS
PIE
Bit 2 = PCE Parity control enable.
This bit selects the hardware parity control (gener-
ation and detection). When the parity control is en-
abled, the computed parity is inserted at the MSB
position (9th bit if M=1; 8th bit if M=0) and parity is
checked on the received data. This bit is set and
cleared by software. Once it is set, PCE is active
after the current byte (in reception and in transmis-
sion).
Bit 7 = R8 Receive data bit 8.
This bit is used to store the 9th bit of the received
word when M=1.
Bit 6 = T8 Transmit data bit 8.
This bit is used to store the 9th bit of the transmit-
ted word when M=1.
0: Parity control disabled
1: Parity control enabled
Bit 5 = SCID Disabled for low power consumption
When this bit is set the SCI prescalers and outputs
are stopped and the end of the current byte trans-
fer in order to reduce power consumption.This bit
is set and cleared by software.
0: SCI enabled
1: SCI prescaler and outputs disabled
Bit 1 = PS Parity selection.
This bit selects the odd or even parity when the
parity generation/detection is enabled (PCE bit
set). It is set and cleared by software. The parity
will be selected after the current byte.
0: Even parity
1: Odd parity
Bit 4 = M Word length.
This bit determines the word length. It is set or
cleared by software.
0: 1 Start bit, 8 Data bits, 1 Stop bit
1: 1 Start bit, 9 Data bits, 1 Stop bit
Bit 0 = PIE Parity interrupt enable.
This bit enables the interrupt capability of the hard-
ware parity control when a parity error is detected
(PE bit set). It is set and cleared by software.
0: Parity error interrupt disabled
Note: The M bit must not be modified during a data
transfer (both transmission and reception).
1: Parity error interrupt enabled.
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ST72260G, ST72262G, ST72264G
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
CONTROL REGISTER 2 (SCICR2)
Read/Write
Notes:
– During transmission, a “0” pulse on the TE bit
(“0” followed by “1”) sends a preamble (idle line)
after the current word.
Reset Value: 0000 0000 (00h)
7
0
– When TE is set there is a 1 bit-time delay before
the transmission starts.
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
Caution: The TDO pin is free for general purpose
I/O only when the TE and RE bits are both cleared
(or if TE is never set).
Bit 7 = TIE Transmitter interrupt enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever
TDRE=1 in the SCISR register
Bit 2 = RE Receiver enable.
This bit enables the receiver. It is set and cleared
by software.
0: Receiver is disabled
1: Receiver is enabled and begins searching for a
start bit
Bit 6 = TCIE Transmission complete interrupt ena-
ble
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever TC=1 in
the SCISR register
Bit 1 = RWU Receiver wake-up.
This bit determines if the SCI is in mute mode or
not. It is set and cleared by software and can be
cleared by hardware when a wake-up sequence is
recognized.
0: Receiver in Active mode
1: Receiver in Mute mode
Bit 5 = RIE Receiver interrupt enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever OR=1
or RDRF=1 in the SCISR register
Note: Before selecting Mute mode (setting the
RWU bit), the SCI must receive some data first,
otherwise it cannot function in Mute mode with
wakeup by idle line detection.
Bit 4 = ILIE Idle line interrupt enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever IDLE=1
in the SCISR register.
Bit 0 = SBK Send break.
This bit set is used to send break characters. It is
set and cleared by software.
0: No break character is transmitted
1: Break characters are transmitted
Bit 3 = TE Transmitter enable.
This bit enables the transmitter. It is set and
cleared by software.
0: Transmitter is disabled
1: Transmitter is enabled
Note: If the SBK bit is set to “1” and then to “0”, the
transmitter will send a BREAK word at the end of
the current word.
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ST72260G, ST72262G, ST72264G
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
DATA REGISTER (SCIDR)
Read/Write
Bits 5:3 = SCT[2:0] SCI Transmitter rate divisor
These 3 bits, in conjunction with the SCP1 & SCP0
bits define the total division applied to the bus
clock to yield the transmit rate clock in convention-
al Baud Rate Generator mode.
Reset Value: Undefined
Contains the Received or Transmitted data char-
acter, depending on whether it is read from or writ-
ten to.
TR dividing factor
SCT2
SCT1
SCT0
1
2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
7
0
4
DR7
DR6
DR5
DR4
DR3
DR2
DR1
DR0
8
16
32
64
128
The Data register performs a double function (read
and write) since it is composed of two registers,
one for transmission (TDR) and one for reception
(RDR).
The TDR register provides the parallel interface
between the internal bus and the output shift reg-
ister (see Figure 54).
The RDR register provides the parallel interface
between the input shift register and the internal
bus (see Figure 54).
Bits 2:0 = SCR[2:0] SCI Receiver rate divisor.
These 3 bits, in conjunction with the SCP[1:0] bits
define the total division applied to the bus clock to
yield the receive rate clock in conventional Baud
Rate Generator mode.
RR Dividing factor
SCR2
SCR1
SCR0
BAUD RATE REGISTER (SCIBRR)
Read/Write
1
2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reset Value: 0000 0000 (00h)
4
7
0
8
16
32
64
128
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0
Bits 7:6= SCP[1:0] First SCI Prescaler
These 2 prescaling bits allow several standard
clock division ranges:
PR Prescaling factor
SCP1
SCP0
1
3
0
0
1
1
0
1
0
1
4
13
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ST72260G, ST72262G, ST72264G
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
EXTENDED RECEIVE PRESCALER DIVISION
REGISTER (SCIERPR)
EXTENDED TRANSMIT PRESCALER DIVISION
REGISTER (SCIETPR)
Read/Write
Read/Write
Reset Value: 0000 0000 (00h)
Reset Value:0000 0000 (00h)
Allows setting of the Extended Prescaler rate divi-
sion factor for the receive circuit.
Allows setting of the External Prescaler rate divi-
sion factor for the transmit circuit.
7
0
7
0
ERPR ERPR ERPR ERPR ERPR ERPR ERPR ERPR
ETPR ETPR ETPR ETPR ETPR ETPR ETPR ETPR
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Bits 7:0 = ERPR[7:0] 8-bit Extended Receive
Prescaler Register.
Bits 7:0 = ETPR[7:0] 8-bit Extended Transmit
Prescaler Register.
The extended Baud Rate Generator is activated
when a value different from 00h is stored in this
register. Therefore the clock frequency issued
from the 16 divider (see Figure 56) is divided by
the binary factor set in the SCIERPR register (in
the range 1 to 255).
The extended Baud Rate Generator is activated
when a value different from 00h is stored in this
register. Therefore the clock frequency issued
from the 16 divider (see Figure 56) is divided by
the binary factor set in the SCIETPR register (in
the range 1 to 255).
The extended baud rate generator is not used af-
ter a reset.
The extended baud rate generator is not used af-
ter a reset.
Table 19. Baudrate Selection
Conditions
Baud
Rate
Symbol
Parameter
Standard
Unit
Accuracy
vs. Standard
Prescaler
f
CPU
Conventional Mode
TR (or RR)=128, PR=13
TR (or RR)= 32, PR=13
TR (or RR)= 16, PR=13
TR (or RR)= 8, PR=13
TR (or RR)= 4, PR=13
TR (or RR)= 16, PR= 3
TR (or RR)= 2, PR=13
TR (or RR)= 1, PR=13
300
~300.48
1200 ~1201.92
2400 ~2403.84
4800 ~4807.69
9600 ~9615.38
10400 ~10416.67
19200 ~19230.77
38400 ~38461.54
~0.16%
~0.79%
f
f
Tx
Communication frequency 8MHz
Hz
Rx
Extended Mode
ETPR (or ERPR) = 35,
TR (or RR)= 1, PR=1
14400 ~14285.71
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SERIAL COMMUNICATIONS INTERFACE (Cont’d)
Table 20. SCI Register Map and Reset Values
Address
(Hex.)
Register
Name
7
6
5
4
3
2
1
0
SCISR
TDRE
1
TC
1
RDRF
0
IDLE
0
OR
0
NF
0
FE
0
PE
0
50
51
52
53
54
55
56
Reset Value
SCIDR
DR7
DR6
DR5
x
DR4
DR3
DR2
x
DR1
DR0
x
Reset Value
SCIBRR
x
SCP1
0
x
SCP0
0
x
SCT1
0
x
SCT0
0
x
SCR1
0
SCT2
0
SCR2
0
SCR0
0
Reset Value
SCICR1
R8
x
T8
SCID
0
M
WAKE
0
PCE
0
PS
0
PIE
0
Reset Value
SCICR2
0
0
TIE
0
TCIE
0
RIE
0
ILIE
0
TE
RE
0
RWU
0
SBK
0
Reset Value
SCIERPR
Reset Value
SCIETPR
Reset Value
0
ERPR7
0
ERPR6
0
ERPR5 ERPR4
ERPR3
0
ERPR2
0
ERPR1
0
ERPR0
0
0
0
ETPR7
0
ETPR6
0
ETPR5 ETPR4
ETPR3
0
ETPR2
0
ETPR1
0
ETPR0
0
0
0
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2
11.6 I C BUS INTERFACE (I2C)
11.6.1 Introduction
handshake. The interrupts are enabled or disabled
by software. The interface is connected to the I C
2
2
The I C Bus Interface serves as an interface be-
2
bus by a data pin (SDAI) and by a clock pin (SCLI).
tween the microcontroller and the serial I C bus. It
2
It can be connected both with a standard I C bus
provides both multimaster and slave functions,
2
2
and a Fast I C bus. This selection is made by soft-
and controls all I C bus-specific sequencing, pro-
2
ware.
tocol, arbitration and timing. It supports fast I C
mode (400kHz).
Mode Selection
11.6.2 Main Features
The interface can operate in the four following
modes:
2
■ Parallel-bus/I C protocol converter
– Slave transmitter/receiver
■ Multi-master capability
– Master transmitter/receiver
By default, it operates in slave mode.
■ 7-bit/10-bit Addressing
■ Transmitter/Receiver flag
■ End-of-byte transmission flag
■ Transfer problem detection
The interface automatically switches from slave to
master after it generates a START condition and
from master to slave in case of arbitration loss or a
STOP generation, allowing then Multi-Master ca-
pability.
2
I C Master Features:
■ Clock generation
2
■ I C bus busy flag
Communication Flow
■ Arbitration Lost Flag
In Master mode, it initiates a data transfer and
generates the clock signal. A serial data transfer
always begins with a start condition and ends with
a stop condition. Both start and stop conditions are
generated in master mode by software.
■ End of byte transmission flag
■ Transmitter/Receiver Flag
■ Start bit detection flag
■ Start and Stop generation
In Slave mode, the interface is capable of recog-
nising its own address (7 or 10-bit), and the Gen-
eral Call address. The General Call address de-
tection may be enabled or disabled by software.
2
I C Slave Features:
■ Stop bit detection
2
■ I C bus busy flag
Data and addresses are transferred as 8-bit bytes,
MSB first. The first byte(s) following the start con-
dition contain the address (one in 7-bit mode, two
in 10-bit mode). The address is always transmitted
in Master mode.
■ Detection of misplaced start or stop condition
2
■ Programmable I C Address detection
■ Transfer problem detection
■ End-of-byte transmission flag
■ Transmitter/Receiver flag
11.6.3 General Description
A 9th clock pulse follows the 8 clock cycles of a
byte transfer, during which the receiver must send
an acknowledge bit to the transmitter. Refer to Fig-
ure 57.
In addition to receiving and transmitting data, this
interface converts it from serial to parallel format
and vice versa, using either an interrupt or polled
2
Figure 57. I C BUS Protocol
SDA
MSB
ACK
SCL
1
2
8
9
START
STOP
CONDITION
CONDITION
VR02119B
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2
I C BUS INTERFACE (Cont’d)
Acknowledge may be enabled and disabled by
software.
The SCL frequency (F ) is controlled by a pro-
scl
grammable clock divider which depends on the
2
2
I C bus mode.
The I C interface address and/or general call ad-
2
dress can be selected by software.
When the I C cell is enabled, the SDA and SCL
2
ports must be configured as floating inputs. In this
case, the value of the external pull-up resistor
used depends on the application.
The speed of the I C interface may be selected
2
between Standard (0-100KHz) and Fast I C (100-
400KHz).
2
When the I C cell is disabled, the SDA and SCL
ports revert to being standard I/O port pins.
SDA/SCL Line Control
Transmitter mode: the interface holds the clock
line low before transmission to wait for the micro-
controller to write the byte in the Data Register.
Receiver mode: the interface holds the clock line
low after reception to wait for the microcontroller to
read the byte in the Data Register.
2
Figure 58. I C Interface Block Diagram
DATA REGISTER (DR)
DATA CONTROL
SDA or SDAI
DATA SHIFT REGISTER
COMPARATOR
OWN ADDRESS REGISTER 1 (OAR1)
OWN ADDRESS REGISTER 2 (OAR2)
CLOCK CONTROL
SCL or SCLI
CLOCK CONTROL REGISTER (CCR)
CONTROL REGISTER (CR)
STATUS REGISTER 1 (SR1)
STATUS REGISTER 2 (SR2)
CONTROL LOGIC
INTERRUPT
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2
I C BUS INTERFACE (Cont’d)
11.6.4 Functional Description
– EVF and BTF bits are set with an interrupt if the
ITE bit is set.
Refer to the CR, SR1 and SR2 registers in Section
11.6.7. for the bit definitions.
Then the interface waits for a read of the SR1 reg-
ister followed by a read of the DR register, holding
the SCL line low (see Figure 59 Transfer se-
quencing EV2).
2
By default the I C interface operates in Slave
mode (M/SL bit is cleared) except when it initiates
a transmit or receive sequence.
First the interface frequency must be configured
using the FRi bits in the OAR2 register.
Slave Transmitter
Following the address reception and after SR1
register has been read, the slave sends bytes from
the DR register to the SDA line via the internal shift
register.
11.6.4.1 Slave Mode
As soon as a start condition is detected, the
address is received from the SDA line and sent to
the shift register; then it is compared with the
address of the interface or the General Call
address (if selected by software).
The slave waits for a read of the SR1 register fol-
lowed by a write in the DR register, holding the
SCL line low (see Figure 59 Transfer sequencing
EV3).
Note: In 10-bit addressing mode, the comparision
includes the header sequence (11110xx0) and the
two most significant bits of the address.
When the acknowledge pulse is received:
Header matched (10-bit mode only): the interface
generates an acknowledge pulse if the ACK bit is
set.
– The EVF and BTF bits are set by hardware with
an interrupt if the ITE bit is set.
Address not matched: the interface ignores it
and waits for another Start condition.
Closing slave communication
After the last data byte is transferred a Stop Con-
dition is generated by the master. The interface
detects this condition and sets:
Address matched: the interface generates in se-
quence:
– Acknowledge pulse if the ACK bit is set.
– EVF and STOPF bits with an interrupt if the ITE
bit is set.
– EVF and ADSL bits are set with an interrupt if the
ITE bit is set.
Then the interface waits for a read of the SR2 reg-
ister (see Figure 59 Transfer sequencing EV4).
Then the interface waits for a read of the SR1 reg-
ister, holding the SCL line low (see Figure 59
Transfer sequencing EV1).
Next, in 7-bit mode read the DR register to deter-
mine from the least significant bit (Data Direction
Bit) if the slave must enter Receiver or Transmitter
mode.
Error Cases
– BERR: Detection of a Stop or a Start condition
during a byte transfer. In this case, the EVF and
the BERR bits are set with an interrupt if the ITE
bit is set.
If it is a Stop then the interface discards the data,
released the lines and waits for another Start
condition.
In 10-bit mode, after receiving the address se-
quence the slave is always in receive mode. It will
enter transmit mode on receiving a repeated Start
condition followed by the header sequence with
matching address bits and the least significant bit
set (11110xx1) .
If it is a Start then the interface discards the data
and waits for the next slave address on the bus.
– AF: Detection of a non-acknowledge bit. In this
case, the EVF and AF bits are set with an inter-
rupt if the ITE bit is set.
Slave Receiver
Following the address reception and after SR1
register has been read, the slave receives bytes
from the SDA line into the DR register via the inter-
nal shift register. After each byte the interface gen-
erates in sequence:
Note: In both cases, SCL line is not held low; how-
ever, SDA line can remain low due to possible «0»
bits transmitted last. It is then necessary to release
both lines by software.
– Acknowledge pulse if the ACK bit is set
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2
I C BUS INTERFACE (Cont’d)
How to release the SDA / SCL lines
After completion of this transfer (and acknowledge
from the slave if the ACK bit is set):
Set and subsequently clear the STOP bit while
BTF is set. The SDA/SCL lines are released after
the transfer of the current byte.
– The EVF bit is set by hardware with interrupt
generation if the ITE bit is set.
11.6.4.2 Master Mode
Then the master waits for a read of the SR1 regis-
ter followed by a write in the CR register (for exam-
ple set PE bit), holding the SCL line low (see Fig-
ure 59 Transfer sequencing EV6).
To switch from default Slave mode to Master
mode a Start condition generation is needed.
Start condition
Next the master must enter Receiver or Transmit-
ter mode.
Setting the START bit while the BUSY bit is
cleared causes the interface to switch to Master
mode (M/SL bit set) and generates a Start condi-
tion.
Note: In 10-bit addressing mode, to switch the
master to Receiver mode, software must generate
a repeated Start condition and resend the header
sequence with the least significant bit set
(11110xx1).
Once the Start condition is sent:
– The EVF and SB bits are set by hardware with
an interrupt if the ITE bit is set.
Then the master waits for a read of the SR1 regis-
ter followed by a write in the DR register with the
Slave address, holding the SCL line low (see
Figure 59 Transfer sequencing EV5).
Master Receiver
Following the address transmission and after SR1
and CR registers have been accessed, the master
receives bytes from the SDA line into the DR reg-
ister via the internal shift register. After each byte
the interface generates in sequence:
Slave address transmission
– Acknowledge pulse if if the ACK bit is set
Then the slave address is sent to the SDA line via
the internal shift register.
– EVF and BTF bits are set by hardware with an in-
terrupt if the ITE bit is set.
In 7-bit addressing mode, one address byte is
sent.
Then the interface waits for a read of the SR1 reg-
ister followed by a read of the DR register, holding
the SCL line low (see Figure 59 Transfer se-
quencing EV7).
In 10-bit addressing mode, sending the first byte
including the header sequence causes the follow-
ing event:
– The EVF bit is set by hardware with interrupt
generation if the ITE bit is set.
Then the master waits for a read of the SR1 regis-
ter followed by a write in the DR register, holding
the SCL line low (see Figure 59 Transfer se-
quencing EV9).
To close the communication: before reading the
last byte from the DR register, set the STOP bit to
generate the Stop condition. The interface goes
automatically back to slave mode (M/SL bit
cleared).
Note: In order to generate the non-acknowledge
pulse after the last received data byte, the ACK bit
must be cleared just before reading the second
last data byte.
Then the second address byte is sent by the inter-
face.
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2
I C BUS INTERFACE (Cont’d)
Master Transmitter
BERR bits are set by hardware with an interrupt
if ITE is set.
Following the address transmission and after SR1
register has been read, the master sends bytes
from the DR register to the SDA line via the inter-
nal shift register.
– AF: Detection of a non-acknowledge bit. In this
case, the EVF and AF bits are set by hardware
with an interrupt if the ITE bit is set. To resume,
set the START or STOP bit.
The master waits for a read of the SR1 register fol-
lowed by a write in the DR register, holding the
SCL line low (see Figure 59 Transfer sequencing
EV8).
– ARLO: Detection of an arbitration lost condition.
In this case the ARLO bit is set by hardware (with
an interrupt if the ITE bit is set and the interface
goes automatically back to slave mode (the M/SL
bit is cleared).
When the acknowledge bit is received, the
interface sets:
Note: In all these cases, the SCL line is not held
low; however, the SDA line can remain low due to
possible «0» bits transmitted last. It is then neces-
sary to release both lines by software.
– EVF and BTF bits with an interrupt if the ITE bit
is set.
To close the communication: after writing the last
byte to the DR register, set the STOP bit to gener-
ate the Stop condition. The interface goes auto-
matically back to slave mode (M/SL bit cleared).
Error Cases
– BERR: Detection of a Stop or a Start condition
during a byte transfer. In this case, the EVF and
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2
I C BUS INTERFACE (Cont’d)
Figure 59. Transfer Sequencing
7-bit Slave receiver:
S
Address
A
Data1
A
Data1
Data1
Data2
EV3
A
Data2
Data2
DataN
A
P
.....
EV1
EV2
A
EV2
A
EV2
NA
EV4
7-bit Slave transmitter:
S
Address
A
DataN
P
.....
.....
EV1 EV3
EV3
EV3-1
EV4
7-bit Master receiver:
S
Address
A
A
A
DataN NA
P
EV5
EV6
EV7
A
EV7
A
EV7
A
7-bit Master transmitter:
S
Address
A
Data1
Data2
DataN
P
.....
EV5
EV6 EV8
EV8
EV8
EV8
10-bit Slave receiver:
S
Header
A
Address
A
Data1
A
DataN
A
P
.....
EV1
EV2
EV2
EV4
10-bit Slave transmitter:
S
Header
A
Data1
A
A
DataN
....
.
A
P
r
EV1 EV3
EV6 EV8
EV3
EV3-1
EV4
10-bit Master transmitter
S
Header
A
Address
A
Data1
DataN
A
P
.....
EV5
EV9
EV8
A
EV8
A
10-bit Master receiver:
S
Header
A
Data1
DataN
P
r
.....
EV5
EV6
EV7
EV7
Legend: S=Start, S = Repeated Start, P=Stop, A=Acknowledge, NA=Non-acknowledge,
r
EVx=Event (with interrupt if ITE=1)
EV1: EVF=1, ADSL=1, cleared by reading SR1 register.
EV2: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register.
EV3: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register.
EV3-1: EVF=1, AF=1, BTF=1; AF is cleared by reading SR1 register. BTF is cleared by releasing the
lines (STOP=1, STOP=0) or by writing DR register (DR=FFh). Note: If lines are released by
STOP=1, STOP=0, the subsequent EV4 is not seen.
EV4: EVF=1, STOPF=1, cleared by reading SR2 register.
EV5: EVF=1, SB=1, cleared by reading SR1 register followed by writing DR register.
EV6: EVF=1, cleared by reading SR1 register followed by writing CR register (for example PE=1).
EV7: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register.
EV8: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register.
EV9: EVF=1, ADD10=1, cleared by reading SR1 register followed by writing DR register.
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2
I C BUS INTERFACE (Cont’d)
11.6.5 Low Power Modes
Mode
Description
2
No effect on I C interface.
WAIT
HALT
2
I C interrupts cause the device to exit from WAIT mode.
2
I C registers are frozen.
2
2
In HALT mode, the I C interface is inactive and does not acknowledge data on the bus. The I C interface
resumes operation when the MCU is woken up by an interrupt with “exit from HALT mode” capability.
11.6.6 Interrupts
Figure 60. Event Flags and Interrupt Generation
ADD10
ITE
BTF
ADSL
SB
INTERRUPT
EVF
AF
STOPF
ARLO
BERR
*
* EVF can also be set by EV6 or an error from the SR2 register.
Enable
Control from
Bit
Exit
Exit
from
Halt
Event
Flag
Interrupt Event
Wait
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
10-bit Address Sent Event (Master mode)
End of Byte Transfer Event
ADD10
BTF
No
No
No
No
No
No
No
No
Address Matched Event (Slave mode)
Start Bit Generation Event (Master mode)
Acknowledge Failure Event
ADSEL
SB
ITE
AF
Stop Detection Event (Slave mode)
Arbitration Lost Event (Multimaster configuration)
Bus Error Event
STOPF
ARLO
BERR
2
Note: The I C interrupt events are connected to
the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding
Enable Control Bit is set and the I-bit in the CC reg-
ister is reset (RIM instruction).
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2
I C BUS INTERFACE (Cont’d)
11.6.7 Register Description
– In slave mode:
0: No start generation
1: Start generation when the bus is free
2
I C CONTROL REGISTER (CR)
Read / Write
Reset Value: 0000 0000 (00h)
Bit 2 = ACK Acknowledge enable.
This bit is set and cleared by software. It is also
cleared by hardware when the interface is disa-
bled (PE=0).
7
0
0
0
PE
ENGC START ACK STOP
ITE
0: No acknowledge returned
1: Acknowledge returned after an address byte or
a data byte is received
Bit 7:6 = Reserved. Forced to 0 by hardware.
Bit 1 = STOP Generation of a Stop condition.
This bit is set and cleared by software. It is also
cleared by hardware in master mode. Note: This
bit is not cleared when the interface is disabled
(PE=0).
Bit 5 = PE Peripheral enable.
This bit is set and cleared by software.
0: Peripheral disabled
1: Master/Slave capability
Notes:
– When PE=0, all the bits of the CR register and
the SR register except the Stop bit are reset. All
outputs are released while PE=0
– In master mode:
0: No stop generation
1: Stop generation after the current byte transfer
or after the current Start condition is sent. The
STOP bit is cleared by hardware when the Stop
condition is sent.
– When PE=1, the corresponding I/O pins are se-
lected by hardware as alternate functions.
2
– To enable the I C interface, write the CR register
TWICE with PE=1 as the first write only activates
the interface (only PE is set).
– In slave mode:
0: No stop generation
1: Release the SCL and SDA lines after the cur-
rent byte transfer (BTF=1). In this mode the
STOP bit has to be cleared by software.
Bit 4 = ENGC Enable General Call.
This bit is set and cleared by software. It is also
cleared by hardware when the interface is disa-
bled (PE=0). The 00h General Call address is ac-
knowledged (01h ignored).
0: General Call disabled
1: General Call enabled
Bit 0 = ITE Interrupt enable.
This bit is set and cleared by software and cleared
by hardware when the interface is disabled
(PE=0).
0: Interrupts disabled
1: Interrupts enabled
Refer to Figure 60 for the relationship between the
events and the interrupt.
SCL is held low when the ADD10, SB, BTF or
ADSL flags or an EV6 event (See Figure 59) is de-
tected.
Note: In accordance with the I2C standard, when
GCAL addressing is enabled, an I2C slave can
only receive data. It will not transmit data to the
master.
Bit 3 = START Generation of a Start condition.
This bit is set and cleared by software. It is also
cleared by hardware when the interface is disa-
bled (PE=0) or when the Start condition is sent
(with interrupt generation if ITE=1).
– In master mode:
0: No start generation
1: Repeated start generation
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2
I C BUS INTERFACE (Cont’d)
2
I C STATUS REGISTER 1 (SR1)
arbitration (ARLO=1) or when the interface is disa-
bled (PE=0).
0: Data byte received (if BTF=1)
1: Data byte transmitted
Read Only
Reset Value: 0000 0000 (00h)
7
0
Bit 4 = BUSY Bus busy.
EVF ADD10 TRA BUSY BTF ADSL M/SL
SB
This bit is set by hardware on detection of a Start
condition and cleared by hardware on detection of
a Stop condition. It indicates a communication in
progress on the bus. This information is still updat-
ed when the interface is disabled (PE=0).
0: No communication on the bus
Bit 7 = EVF Event flag.
This bit is set by hardware as soon as an event oc-
curs. It is cleared by software reading SR2 register
in case of error event or as described in Figure 59.
It is also cleared by hardware when the interface is
disabled (PE=0).
0: No event
1: One of the following events has occurred:
1: Communication ongoing on the bus
Bit 3 = BTF Byte transfer finished.
This bit is set by hardware as soon as a byte is cor-
rectly received or transmitted with interrupt gener-
ation if ITE=1. It is cleared by software reading
SR1 register followed by a read or write of DR reg-
ister. It is also cleared by hardware when the inter-
face is disabled (PE=0).
– BTF=1 (Byte received or transmitted)
– ADSL=1 (Address matched in Slave mode
while ACK=1)
– SB=1 (Start condition generated in Master
mode)
– Following a byte transmission, this bit is set after
reception of the acknowledge clock pulse. In
case an address byte is sent, this bit is set only
after the EV6 event (See Figure 59). BTF is
cleared by reading SR1 register followed by writ-
ing the next byte in DR register.
– AF=1 (No acknowledge received after byte
transmission)
– STOPF=1 (Stop condition detected in Slave
mode)
– Following a byte reception, this bit is set after
transmission of the acknowledge clock pulse if
ACK=1. BTF is cleared by reading SR1 register
followed by reading the byte from DR register.
– ARLO=1 (Arbitration lost in Master mode)
– BERR=1 (Bus error, misplaced Start or Stop
condition detected)
– ADD10=1 (Master has sent header byte)
The SCL line is held low while BTF=1.
– Address byte successfully transmitted in Mas-
ter mode.
0: Byte transfer not done
1: Byte transfer succeeded
Bit 6 = ADD10 10-bit addressing in Master mode.
This bit is set by hardware when the master has
sent the first byte in 10-bit address mode. It is
cleared by software reading SR2 register followed
by a write in the DR register of the second address
byte. It is also cleared by hardware when the pe-
ripheral is disabled (PE=0).
Bit 2 = ADSL Address matched (Slave mode).
This bit is set by hardware as soon as the received
slave address matched with the OAR register con-
tent or a general call is recognized. An interrupt is
generated if ITE=1. It is cleared by software read-
ing SR1 register or by hardware when the inter-
face is disabled (PE=0).
0: No ADD10 event occurred.
1: Master has sent first address byte (header)
The SCL line is held low while ADSL=1.
0: Address mismatched or not received
1: Received address matched
Bit 5 = TRA Transmitter/Receiver.
When BTF is set, TRA=1 if a data byte has been
transmitted. It is cleared automatically when BTF
is cleared. It is also cleared by hardware after de-
tection of Stop condition (STOPF=1), loss of bus
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2
I C BUS INTERFACE (Cont’d)
Bit 1 = M/SL Master/Slave.
Bit 2 = ARLO Arbitration lost.
This bit is set by hardware as soon as the interface
is in Master mode (writing START=1). It is cleared
by hardware after detecting a Stop condition on
the bus or a loss of arbitration (ARLO=1). It is also
cleared when the interface is disabled (PE=0).
0: Slave mode
This bit is set by hardware when the interface los-
es the arbitration of the bus to another master. An
interrupt is generated if ITE=1. It is cleared by soft-
ware reading SR2 register or by hardware when
the interface is disabled (PE=0).
After an ARLO event the interface switches back
automatically to Slave mode (M/SL=0).
1: Master mode
The SCL line is not held low while ARLO=1.
Bit 0 = SB Start bit (Master mode).
This bit is set by hardware as soon as the Start
condition is generated (following
0: No arbitration lost detected
1: Arbitration lost detected
a
write
START=1). An interrupt is generated if ITE=1. It is
cleared by software reading SR1 register followed
by writing the address byte in DR register. It is also
cleared by hardware when the interface is disa-
bled (PE=0).
0: No Start condition
1: Start condition generated
Bit 1 = BERR Bus error.
This bit is set by hardware when the interface de-
tects a misplaced Start or Stop condition. An inter-
rupt is generated if ITE=1. It is cleared by software
reading SR2 register or by hardware when the in-
terface is disabled (PE=0).
The SCL line is not held low while BERR=1.
2
I C STATUS REGISTER 2 (SR2)
0: No misplaced Start or Stop condition
1: Misplaced Start or Stop condition
Read Only
Reset Value: 0000 0000 (00h)
7
0
0
Bit 0 = GCAL General Call (Slave mode).
This bit is set by hardware when a general call ad-
dress is detected on the bus while ENGC=1. It is
cleared by hardware detecting a Stop condition
(STOPF=1) or when the interface is disabled
(PE=0).
0
0
AF STOPF ARLO BERR GCAL
Bit 7:5 = Reserved. Forced to 0 by hardware.
0: No general call address detected on bus
1: general call address detected on bus
Bit 4 = AF Acknowledge failure.
This bit is set by hardware when no acknowledge
is returned. An interrupt is generated if ITE=1. It is
cleared by software reading SR2 register or by
hardware when the interface is disabled (PE=0).
The SCL line is not held low while AF=1.
0: No acknowledge failure
1: Acknowledge failure
Bit 3 = STOPF Stop detection (Slave mode).
This bit is set by hardware when a Stop condition
is detected on the bus after an acknowledge (if
ACK=1). An interrupt is generated if ITE=1. It is
cleared by software reading SR2 register or by
hardware when the interface is disabled (PE=0).
The SCL line is not held low while STOPF=1.
0: No Stop condition detected
1: Stop condition detected
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2
I C BUS INTERFACE (Cont’d)
2
I C CLOCK CONTROL REGISTER (CCR)
2
Read / Write
I C DATA REGISTER (DR)
Reset Value: 0000 0000 (00h)
Read / Write
Reset Value: 0000 0000 (00h)
7
0
7
0
FM/SM CC6
CC5
CC4
CC3
CC2
CC1
CC0
D7
D6
D5
D4
D3
D2
D1
D0
2
Bit 7 = FM/SM Fast/Standard I C mode.
This bit is set and cleared by software. It is not
cleared when the interface is disabled (PE=0).
2
Bit 7:0 = D[7:0] 8-bit Data Register.
These bits contain the byte to be received or trans-
mitted on the bus.
0: Standard I C mode
2
1: Fast I C mode
– Transmitter mode: Byte transmission start auto-
matically when the software writes in the DR reg-
ister.
Bit 6:0 = CC[6:0] 7-bit clock divider.
These bits select the speed of the bus (F
) de-
SCL
2
pending on the I C mode. They are not cleared
when the interface is disabled (PE=0).
– Receiver mode: the first data byte is received au-
tomatically in the DR register using the least sig-
nificant bit of the address.
– Standard mode (FM/SM=0): F
<= 100kHz
SCL
F
= F
/(2x([CC6..CC0]+2))
CPU
Then, the following data bytes are received one
by one after reading the DR register.
SCL
– Fast mode (FM/SM=1): F
> 100kHz
SCL
F
= F
/(3x([CC6..CC0]+2))
CPU
SCL
Note: The programmed F
SCL and SDA lines.
assumes no load on
SCL
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2
I C BUS INTERFACE (Cont’d)
2
2
I C OWN ADDRESS REGISTER (OAR1)
I C OWN ADDRESS REGISTER (OAR2)
Read / Write
Reset Value: 0000 0000 (00h)
Read / Write
Reset Value: 0100 0000 (40h)
7
0
7
0
0
ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0
FR1
FR0
0
0
0
ADD9 ADD8
7-bit Addressing Mode
Bit 7:6 = FR[1:0] Frequency bits.
Bit 7:1 = ADD[7:1] Interface address.
These bits define the I C bus address of the inter-
face. They are not cleared when the interface is
disabled (PE=0).
These bits are set by software only when the inter-
face is disabled (PE=0). To configure the interface
to I C specifed delays select the value corre-
2
2
sponding to the microcontroller frequency F
.
CPU
f
FR1
0
FR0
CPU
Bit 0 = ADD0 Address direction bit.
This bit is don’t care, the interface acknowledges
either 0 or 1. It is not cleared when the interface is
disabled (PE=0).
< 6 MHz
0
1
6 to 8 MHz
0
Note: Address 01h is always ignored.
Bit 5:3 = Reserved
10-bit Addressing Mode
Bit 2:1 = ADD[9:8] Interface address.
2
These are the most significant bits of the I C bus
address of the interface (10-bit mode only). They
are not cleared when the interface is disabled
(PE=0).
Bit 7:0 = ADD[7:0] Interface address.
These are the least significant bits of the I C bus
address of the interface. They are not cleared
when the interface is disabled (PE=0).
2
Bit 0 = Reserved.
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ST72260G, ST72262G, ST72264G
I²C BUS INTERFACE (Cont’d)
2
Table 21. I C Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
I2CCR
Reset Value
PE
0
ENGC
0
START
0
ACK
0
STOP
0
ITE
0
0028h
0029h
002Ah
02Bh
0
0
I2CSR1
Reset Value
EVF
0
ADD10
0
TRA
0
BUSY
0
BTF
0
ADSL
0
M/SL
0
SB
0
I2CSR2
Reset Value
AF
0
STOPF
0
ARLO
0
BERR
0
GCAL
0
0
0
0
I2CCCR
Reset Value
FM/SM
0
CC6
0
CC5
0
CC4
0
CC3
0
CC2
0
CC1
0
CC0
0
I2COAR1
Reset Value
ADD7
0
ADD6
0
ADD5
0
ADD4
0
ADD3
0
ADD2
0
ADD1
0
ADD0
0
02Ch
I2COAR2
Reset Value
FR1
0
FR0
1
ADD9
0
ADD8
0
002Dh
002Eh
0
0
0
0
0
0
0
I2CDR
Reset Value
MSB
0
LSB
0
0
0
0
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ST72260G, ST72262G, ST72264G
11.7 10-BIT A/D CONVERTER (ADC)
11.7.1 Introduction
■ Data register (DR) which contains the results
■ Conversion complete status flag
The on-chip Analog to Digital Converter (ADC) pe-
ripheral is a 10-bit, successive approximation con-
verter with internal sample and hold circuitry. This
peripheral has 6 multiplexed analog input chan-
nels (refer to device pin out description) that allow
the peripheral to convert the analog voltage levels
from 6 different sources.
■ On/off bit (to reduce consumption)
The block diagram is shown in Figure 61.
11.7.3 Functional Description
11.7.3.1 Analog Power Supply
V
and V
are the high and low level refer-
SSA
DDA
The result of the conversion is stored in a 10-bit
Data Register. The A/D converter is controlled
through a Control/Status Register.
ence voltage pins. In some devices (refer to device
pin out description) they are internally connected
to the V and V pins.
DD
SS
11.7.2 Main Features
Conversion accuracy may therefore be impacted
by voltage drops and noise in the event of heavily
loaded or badly decoupled power supply lines.
■ 10-bit conversion
■ 6 channels with multiplexed input
■ Linear successive approximation
Figure 61. ADC Block Diagram
f
f
ADC
CPU
f
f
/2 f
/4
CPU, CPU , CPU
0
EOC SPEEDADON SLOW
CH2 CH1 CH0
ADCCSR
3
AIN0
AIN1
ANALOG TO DIGITAL
CONVERTER
ANALOG
MUX
AINx
ADCDRH
D9
D8
D7
D6
D5
D4
D3
D2
ADCDRL
0
0
0
0
0
0
D1
D0
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10-BIT A/D CONVERTER (ADC) (Cont’d)
11.7.3.2 Digital A/D Conversion Result
When a conversion is complete:
The conversion is monotonic, meaning that the re-
sult never decreases if the analog input does not
and never increases if the analog input does not.
– The EOC bit is set by hardware.
– The result is in the ADCDR registers.
A read to the ADCDRH or a write to any bit of the
ADCCSR resets the EOC bit.
If the input voltage (V ) is greater than V
AIN
DDA
(high-level voltage reference) then the conversion
result is FFh in the ADCDRH register and 03h in
the ADCDRL register (without overflow indication).
To read the 10 bits, perform the following steps:
1. Poll EOC bit
If the input voltage (V ) is lower than V
level voltage reference) then the conversion result
(low-
SSA
AIN
2. Read ADCDRL. This locks the ADCDRH until it
is read.
in the ADCDRH and ADCDRL registers is 00 00h.
The A/D converter is linear and the digital result of
the conversion is stored in the ADCDRH and AD-
CDRL registers. The accuracy of the conversion is
described in the Electrical Characteristics Section.
3. Read ADCDRH. This clears EOC automati-
cally.
To read only 8 bits, perform the following steps:
1. Poll EOC bit
R
is the maximum recommended impedance
AIN
for an analog input signal. If the impedance is too
high, this will result in a loss of accuracy due to
leakage and sampling not being completed in the
alloted time.
2. Read ADCDRH. This clears EOC automati-
cally.
11.7.3.3 A/D Conversion
11.7.4 Low Power Modes
The analog input ports must be configured as in-
put, no pull-up, no interrupt. Refer to the «I/O
ports» chapter. Using these pins as analog inputs
does not affect the ability of the port to be read as
a logic input.
Note: The A/D converter may be disabled by re-
setting the ADON bit. This feature allows reduced
power consumption when no conversion is need-
ed and between single shot conversions.
In the ADCCSR register:
Mode
Description
– Select the CH[2:0] bits to assign the analog
channel to convert.
WAIT
No effect on A/D Converter
A/D Converter disabled.
ADC Conversion mode
After wakeup from Halt mode, the A/D
Converter requires a stabilisation time
In the ADCCSR register:
HALT
t
(see Electrical Characteristics)
STAB
- Set the SPEED or the SLOW bits
before accurate conversions can be
performed.
– Set the ADON bit to enable the A/D converter
and to start the conversion. From this time on,
the ADC performs a continuous conversion of
the selected channel.
11.7.5 Interrupts
None.
113/171
ST72260G, ST72262G, ST72264G
10-BIT A/D CONVERTER (ADC) (Cont’d)
11.7.6 Register Description
CONTROL/STATUS REGISTER (ADCCSR)
Read/Write (Except bit 7 read only)
Reset Value: 0000 0000 (00h)
Bit 2:0 = CH[2:0] Channel Selection
These bits are set and cleared by software. They
select the analog input to convert.
Channel Pin
CH2 CH1 CH0
7
0
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
EOC SPEED ADON SLOW
0
CH2
CH1
CH0
Bit 7 = EOC End of Conversion
This bit is set by hardware. It is cleared by soft-
ware reading the ADCDRH register or writing to
any bit of the ADCCSR register.
0: Conversion is not complete
1: Conversion complete
DATA REGISTER (ADCDRH)
Read Only
Reset Value: 0000 0000 (00h)
7
0
Bit 6 = SPEED A/D clock selection
This bit is set and cleared by software.
D9
D8
D7
D6
D5
D4
D3
D2
Table 22. A/D Clock Selection (See Note 1)
f
Frequency
SLOW
SPEED
ADC
Bit 7:0 = D[9:2] MSB of Analog Converted Value
f
(See Note 2)
0
1
0
1
1
1
0
0
CPU
f
f
/2
/4
CPU
CPU
DATA REGISTER (ADCDRL)
Read Only
1)
The SPEED and SLOW bits must be updated before
Reset Value: 0000 0000 (00h)
setting the ADON bit.
2)
Use this setting only if fCPU ≤ 4 MHz
7
0
0
0
0
0
0
0
D1
D0
Bit 5 = ADON A/D Converter on
This bit is set and cleared by software.
0: Disable ADC and stop conversion
1: Enable ADC and start conversion
Bit 7:2 = Reserved. Forced by hardware to 0.
Bit 1:0 = D[1:0] LSB of Analog Converted Value
Bit 4 = SLOW A/D Clock Selection
This bit is set and cleared by software. It works to-
gether with the SPEED bit. Refer to Table 22.
114/171
ST72260G, ST72262G, ST72264G
10-BIT A/D CONVERTER (ADC) (Cont’d)
Table 23. ADC Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
ADCDRL
Reset Value
D1
0
D0
0
006Fh
0070h
0071h
0
0
0
0
0
0
ADCDRH
Reset Value
D9
0
D8
0
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
ADCCSR
Reset Value
EOC
0
SPEED
0
ADON
0
SLOW
0
CH2
0
CH1
0
CH0
0
0
115/171
ST72260G, ST72262G, ST72264G
12 INSTRUCTION SET
12.1 CPU ADDRESSING MODES
so, most of the addressing modes may be subdi-
vided in two sub-modes called long and short:
The CPU features 17 different addressing modes
which can be classified in 7 main groups:
– Long addressing mode is more powerful be-
cause it can use the full 64 Kbyte address space,
however it uses more bytes and more CPU cy-
cles.
Addressing Mode
Inherent
Example
nop
– Short addressing mode is less powerful because
it can generally only access page zero (0000h -
00FFh range), but the instruction size is more
compact, and faster. All memory to memory in-
structions use short addressing modes only
(CLR, CPL, NEG, BSET, BRES, BTJT, BTJF,
INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP)
Immediate
Direct
ld A,#$55
ld A,$55
ld A,($55,X)
ld A,([$55],X)
jrne loop
Indexed
Indirect
Relative
Bit operation
bset byte,#5
The ST7 Assembler optimizes the use of long and
short addressing modes.
The CPU Instruction set is designed to minimize
the number of bytes required per instruction: To do
Table 24. CPU Addressing Mode Overview
Pointer
Address
(Hex.)
Pointer Size
(Hex.)
Length
(Bytes)
Mode
Syntax
Destination
Inherent
Immediate
Short
Long
nop
+ 0
ld A,#$55
+ 1
+ 1
+ 2
+ 0
+ 1
+ 2
+ 2
+ 2
+ 2
+ 2
+ 1
+ 2
+ 1
+ 2
+ 2
+ 3
Direct
ld A,$10
00..FF
Direct
ld A,$1000
ld A,(X)
0000..FFFF
00..FF
No Offset
Short
Long
Direct
Indexed
Indexed
Indexed
Direct
ld A,($10,X)
ld A,($1000,X)
ld A,[$10]
00..1FE
0000..FFFF
00..FF
Direct
Short
Long
Indirect
Indirect
Indirect
Indirect
Direct
00..FF
00..FF
00..FF
00..FF
byte
word
byte
word
ld A,[$10.w]
ld A,([$10],X)
ld A,([$10.w],X)
jrne loop
0000..FFFF
00..1FE
0000..FFFF
PC+/-127
PC+/-127
00..FF
Short
Long
Indexed
Indexed
Relative
Relative
Bit
Indirect
Direct
jrne [$10]
00..FF
00..FF
00..FF
byte
byte
byte
bset $10,#7
bset [$10],#7
Bit
Indirect
Direct
00..FF
Bit
Relative btjt $10,#7,skip
Relative btjt [$10],#7,skip
00..FF
Bit
Indirect
00..FF
116/171
ST72260G, ST72262G, ST72264G
INSTRUCTION SET OVERVIEW (Cont’d)
12.1.1 Inherent
12.1.3 Direct
All Inherent instructions consist of a single byte.
The opcode fully specifies all the required informa-
tion for the CPU to process the operation.
In Direct instructions, the operands are referenced
by their memory address.
The direct addressing mode consists of two sub-
modes:
Inherent Instruction
Function
No operation
Direct (short)
NOP
The address is a byte, thus requires only one byte
after the opcode, but only allows 00 - FF address-
ing space.
TRAP
S/W Interrupt
Wait For Interrupt (Low Pow-
er Mode)
WFI
Direct (long)
Halt Oscillator (Lowest Power
Mode)
HALT
The address is a word, thus allowing 64 Kbyte ad-
dressing space, but requires 2 bytes after the op-
code.
RET
Sub-routine Return
Interrupt Sub-routine Return
Set Interrupt Mask (level 3)
Reset Interrupt Mask (level 0)
Set Carry Flag
IRET
SIM
12.1.4 Indexed (No Offset, Short, Long)
RIM
In this mode, the operand is referenced by its
memory address, which is defined by the unsigned
addition of an index register (X or Y) with an offset.
SCF
RCF
Reset Carry Flag
RSP
Reset Stack Pointer
Load
The indirect addressing mode consists of three
sub-modes:
LD
CLR
Clear
Indexed (No Offset)
PUSH/POP
INC/DEC
TNZ
Push/Pop to/from the stack
Increment/Decrement
Test Negative or Zero
1 or 2 Complement
Byte Multiplication
There is no offset, (no extra byte after the opcode),
and allows 00 - FF addressing space.
Indexed (Short)
CPL, NEG
MUL
The offset is a byte, thus requires only one byte af-
ter the opcode and allows 00 - 1FE addressing
space.
SLL, SRL, SRA, RLC,
RRC
Shift and Rotate Operations
Swap Nibbles
Indexed (long)
SWAP
The offset is a word, thus allowing 64 Kbyte ad-
dressing space and requires 2 bytes after the op-
code.
12.1.2 Immediate
Immediate instructions have two bytes, the first
byte contains the opcode, the second byte con-
tains the operand value.
12.1.5 Indirect (Short, Long)
The required data byte to do the operation is found
by its memory address, located in memory (point-
er).
Immediate Instruction
Function
LD
Load
The pointer address follows the opcode. The indi-
rect addressing mode consists of two sub-modes:
CP
Compare
BCP
Bit Compare
Indirect (short)
AND, OR, XOR
ADC, ADD, SUB, SBC
Logical Operations
Arithmetic Operations
The pointer address is a byte, the pointer size is a
byte, thus allowing 00 - FF addressing space, and
requires 1 byte after the opcode.
Indirect (long)
The pointer address is a byte, the pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.
117/171
ST72260G, ST72262G, ST72264G
INSTRUCTION SET OVERVIEW (Cont’d)
12.1.6 Indirect Indexed (Short, Long)
12.1.7 Relative mode (Direct, Indirect)
This is a combination of indirect and short indexed
addressing modes. The operand is referenced by
its memory address, which is defined by the un-
signed addition of an index register value (X or Y)
with a pointer value located in memory. The point-
er address follows the opcode.
This addressing mode is used to modify the PC
register value, by adding an 8-bit signed offset to
it.
Available Relative
Direct/Indirect
Instructions
Function
The indirect indexed addressing mode consists of
two sub-modes:
JRxx
CALLR
Conditional Jump
Call Relative
Indirect Indexed (Short)
The pointer address is a byte, the pointer size is a
byte, thus allowing 00 - 1FE addressing space,
and requires 1 byte after the opcode.
The relative addressing mode consists of two sub-
modes:
Relative (Direct)
Indirect Indexed (Long)
The offset is following the opcode.
Relative (Indirect)
The pointer address is a byte, the pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.
The offset is defined in memory, which address
follows the opcode.
Table 25. Instructions Supporting Direct,
Indexed, Indirect and Indirect Indexed
Addressing Modes
Long and Short
Function
Instructions
LD
Load
CP
Compare
AND, OR, XOR
Logical Operations
Arithmetic Additions/Sub-
stractions operations
ADC, ADD, SUB, SBC
BCP
Bit Compare
Short Instructions
Only
Function
CLR
Clear
INC, DEC
TNZ
Increment/Decrement
Test Negative or Zero
1 or 2 Complement
Bit Operations
CPL, NEG
BSET, BRES
Bit Test and Jump Opera-
tions
BTJT, BTJF
SLL, SRL, SRA, RLC,
RRC
Shift and Rotate Opera-
tions
SWAP
Swap Nibbles
CALL, JP
Call or Jump subroutine
118/171
ST72260G, ST72262G, ST72264G
INSTRUCTION SET OVERVIEW (Cont’d)
12.2 INSTRUCTION GROUPS
The ST7 family devices use an Instruction Set
consisting of 63 instructions. The instructions may
be subdivided into 13 main groups as illustrated in
the following table:
Load and Transfer
LD
CLR
POP
DEC
TNZ
OR
Stack operation
PUSH
INC
RSP
BCP
Increment/Decrement
Compare and Tests
Logical operations
CP
AND
BSET
BTJT
ADC
SLL
XOR
CPL
NEG
Bit Operation
BRES
BTJF
ADD
SRL
JRT
Conditional Bit Test and Branch
Arithmetic operations
Shift and Rotates
SUB
SRA
JRF
SBC
RLC
JP
MUL
RRC
CALL
SWAP
CALLR
SLA
Unconditional Jump or Call
Conditional Branch
JRA
JRxx
TRAP
SIM
NOP
RET
Interruption management
Condition Code Flag modification
WFI
RIM
HALT
SCF
IRET
RCF
Using a pre-byte
The instructions are described with one to four op-
codes.
These prebytes enable instruction in Y as well as
indirect addressing modes to be implemented.
They precede the opcode of the instruction in X or
the instruction using direct addressing mode. The
prebytes are:
In order to extend the number of available op-
codes for an 8-bit CPU (256 opcodes), three differ-
ent prebyte opcodes are defined. These prebytes
modify the meaning of the instruction they pre-
cede.
PDY 90
Replace an X based instruction
using immediate, direct, indexed, or inherent ad-
dressing mode by a Y one.
The whole instruction becomes:
PIX 92
Replace an instruction using di-
PC-2
PC-1
PC
End of previous instruction
Prebyte
rect, direct bit, or direct relative addressing mode
to an instruction using the corresponding indirect
addressing mode.
opcode
It also changes an instruction using X indexed ad-
dressing mode to an instruction using indirect X in-
dexed addressing mode.
PC+1
Additional word (0 to 2) according
to the number of bytes required to compute the ef-
fective address
PIY 91
Replace an instruction using X in-
direct indexed addressing mode by a Y one.
119/171
ST72260G, ST72262G, ST72264G
INSTRUCTION SET OVERVIEW (Cont’d)
Mnemo
ADC
ADD
AND
BCP
Description
Add with Carry
Function/Example
A = A + M + C
A = A + M
Dst
Src
I1
H
H
H
I0
N
N
N
N
N
Z
Z
Z
Z
Z
C
C
C
A
M
M
M
M
Addition
A
Logical And
A = A . M
A
Bit compare A, Memory
Bit Reset
tst (A . M)
A
BRES
BSET
BTJF
BTJT
CALL
CALLR
CLR
bres Byte, #3
bset Byte, #3
btjf Byte, #3, Jmp1
btjt Byte, #3, Jmp1
M
M
M
M
Bit Set
Jump if bit is false (0)
Jump if bit is true (1)
Call subroutine
Call subroutine relative
Clear
C
C
reg, M
reg
0
N
N
N
1
Z
Z
Z
CP
Arithmetic Compare
One Complement
Decrement
tst(Reg - M)
A = FFH-A
dec Y
M
C
1
CPL
reg, M
reg, M
DEC
HALT
IRET
INC
Halt
1
0
Interrupt routine return
Increment
Pop CC, A, X, PC
inc X
I1
H
I0
N
N
Z
Z
C
reg, M
JP
Absolute Jump
Jump relative always
Jump relative
Never jump
jp [TBL.w]
JRA
JRT
JRF
jrf *
JRIH
JRIL
Jump if Port B INT pin = 1 (no Port B Interrupts)
Jump if Port B INT pin = 0 (Port B interrupt)
JRH
Jump if H = 1
H = 1 ?
JRNH
JRM
Jump if H = 0
H = 0 ?
Jump if I1:0 = 11
Jump if I1:0 <> 11
Jump if N = 1 (minus)
Jump if N = 0 (plus)
Jump if Z = 1 (equal)
I1:0 = 11 ?
I1:0 <> 11 ?
N = 1 ?
JRNM
JRMI
JRPL
JREQ
JRNE
JRC
N = 0 ?
Z = 1 ?
Jump if Z = 0 (not equal) Z = 0 ?
Jump if C = 1
Jump if C = 0
Jump if C = 1
C = 1 ?
JRNC
JRULT
C = 0 ?
Unsigned <
Jmp if unsigned >=
Unsigned >
JRUGE Jump if C = 0
JRUGT Jump if (C + Z = 0)
120/171
ST72260G, ST72262G, ST72264G
INSTRUCTION SET OVERVIEW (Cont’d)
Mnemo
JRULE
LD
Description
Jump if (C + Z = 1)
Load
Function/Example
Unsigned <=
dst <= src
Dst
Src
I1
H
I0
N
N
N
N
N
Z
Z
Z
Z
Z
C
reg, M
A, X, Y
reg, M
M, reg
X, Y, A
MUL
NEG
NOP
OR
Multiply
X,A = X * A
neg $10
0
0
Negate (2's compl)
No Operation
OR operation
C
A = A + M
pop reg
pop CC
push Y
C = 0
A
M
reg
CC
M
M
POP
Pop from the Stack
M
I1
1
H
I0
0
C
0
PUSH
RCF
RET
RIM
Push onto the Stack
Reset carry flag
Subroutine Return
Enable Interrupts
Rotate left true C
Rotate right true C
Reset Stack Pointer
Substract with Carry
Set carry flag
reg, CC
I1:0 = 10 (level 0)
C <= A <= C
C => A => C
S = Max allowed
A = A - M - C
C = 1
RLC
RRC
RSP
SBC
SCF
SIM
reg, M
reg, M
N
N
Z
Z
C
C
A
M
N
Z
C
1
Disable Interrupts
Shift left Arithmetic
Shift left Logic
I1:0 = 11 (level 3)
C <= A <= 0
C <= A <= 0
0 => A => C
A7 => A => C
A = A - M
1
1
SLA
reg, M
reg, M
reg, M
reg, M
A
N
N
0
Z
Z
Z
Z
Z
Z
Z
C
C
C
C
C
SLL
SRL
SRA
SUB
SWAP
TNZ
TRAP
WFI
Shift right Logic
Shift right Arithmetic
Substraction
N
N
N
N
M
M
SWAP nibbles
A7-A4 <=> A3-A0
tnz lbl1
reg, M
Test for Neg & Zero
S/W trap
S/W interrupt
1
1
1
0
Wait for Interrupt
Exclusive OR
XOR
A = A XOR M
A
N
Z
121/171
ST72260G, ST72262G, ST72264G
13 ELECTRICAL CHARACTERISTICS
13.1 PARAMETER CONDITIONS
Unless otherwise specified, all voltages are re-
ferred to V
.
SS
13.1.5 Pin input voltage
13.1.1 Minimum and Maximum values
The input voltage measurement on a pin of the de-
vice is described in Figure 63.
Unless otherwise specified the minimum and max-
imum values are guaranteed in the worst condi-
tions of ambient temperature, supply voltage and
frequencies by tests in production on 100% of the
Figure 63. Pin input voltage
devices with an ambient temperature at T =25°C
A
and T =T max (given by the selected temperature
range).
A
A
ST7 PIN
Data based on characterization results, design
simulation and/or technology characteristics are
indicated in the table footnotes and are not tested
in production. Based on characterization, the min-
imum and maximum values refer to sample tests
and represent the mean value plus or minus three
times the standard deviation (mean±3Σ).
V
IN
13.1.2 Typical values
Unless otherwise specified, typical data are based
on T =25°C, V =5V (for the 3V≤V ≤5.5V volt-
A
DD
DD
age range) and V =2.7V (for the 2.4V≤V ≤3V
DD
DD
voltage range). They are given only as design
guidelines and are not tested.
Typical ADC accuracy values are determined by
characterization of a batch of samples from a
standard diffusion lot over the full temperature
range, where 95% of the devices have an error
less than or equal to the value indicated
(mean±2Σ).
13.1.3 Typical curves
Unless otherwise specified, all typical curves are
given only as design guidelines and are not tested.
13.1.4 Loading capacitor
The loading conditions used for pin parameter
measurement are shown in Figure 62.
Figure 62. Pin loading conditions
ST7 PIN
C
L
122/171
ST72260G, ST72262G, ST72264G
13.2 ABSOLUTE MAXIMUM RATINGS
Stresses above those listed as “absolute maxi-
mum ratings” may cause permanent damage to
the device. This is a stress rating only and func-
tional operation of the device under these condi-
tions is not implied. Exposure to maximum rating
conditions for extended periods may affect device
reliability.
13.2.1 Voltage Characteristics
Symbol
Ratings
Maximum value
6.5
Unit
V
- V
Supply voltage
DD
SS
V
1) & 2)
V
Input voltage on any pin
VSS-0.3 to VDD+0.3
IN
V
Electrostatic discharge voltage (Human Body Model)
Electrostatic discharge voltage (Machine Model)
ESD(HBM)
see Section 13.7.3 on page 137
V
ESD(MM)
13.2.2 Current Characteristics
Symbol
Ratings
Maximum value
Unit
3)
3)
I
Total current into V power lines (source)
100
150
25
VDD
DD
I
Total current out of V ground lines (sink)
SS
VSS
Output current sunk by any standard I/O and control pin
Output current sunk by any high sink I/O pin
Output current source by any I/Os and control pin
Injected current on ICCSEL pin
I
50
IO
- 25
± 5
± 5
± 5
± 5
± 20
mA
Injected current on RESET pin
2) & 4)
I
INJ(PIN)
Injected current on OSC1 and OSC2 pins
5) & 6)
Injected current on any other pin
2)
5)
ΣI
Total injected current (sum of all I/O and control pins)
INJ(PIN)
13.2.3 Thermal Characteristics
Symbol
Ratings
Value
Unit
T
Storage temperature range
-65 to +150
°C
STG
Maximum junction temperature (see Section Figure 111. "Low Profile Fine Pitch Ball Grid Array
Package" on page 155)
T
J
Notes:
1. Directly connecting the RESET and I/O pins to V or V could damage the device if an unintentional internal reset
DD
SS
is generated or an unexpected change of the I/O configuration occurs (for example, due to a corrupted program counter).
To guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7kΩ for
RESET, 10kΩ for I/Os). Unused I/O pins must be tied in the same way to V or V according to their reset configuration.
DD
SS
2. When the current limitation is not possible, the V absolute maximum rating must be respected, otherwise refer to
IN
I
specification. A positive injection is induced by V >V while a negative injection is induced by V <V
.
INJ(PIN)
IN
DD
IN
SS
3. All power (V ) and ground (V ) lines must always be connected to the external supply.
DD
SS
4. Negative injection disturbs the analog performance of the device. See note in “10-BIT ADC CHARACTERISTICS” on
page 152. For best reliability, it is recommended to avoid negative injection of more than 1.6mA.
5. When several inputs are submitted to a current injection, the maximum ΣI
is the absolute sum of the positive
INJ(PIN)
and negative injected currents (instantaneous values). These results are based on characterisation with ΣI
maxi-
INJ(PIN)
mum current injection on four I/O port pins of the device.
6. True open drain I/O port pins do not accept positive injection.
123/171
ST72260G, ST72262G, ST72264G
13.3 OPERATING CONDITIONS
13.3.1 General Operating Conditions
T = -40 to +85°C unless otherwise specified.
A
Symbol
Parameter
Conditions
Min
2.4
2.7
3.3
0
Max
5.5
5.5
5.5
16
Unit
f
f
f
= 8 MHz. max., T = 0 to 70°C
OSC
OSC
OSC
A
V
Supply voltage
= 8 MHz. max.
= 16 MHz. max.
≥3.3V
V
DD
V
V
V
DD
DD
DD
External clock frequency on OSC1
pin
f
≥2.4V, T = 0 to +70°C
MHz
OSC
A
0
8
≥2.7V, T = -40 to +85°C
A
Figure 64. f
Maximum Operating Frequency Versus VDD Supply Voltage
OSC
FUNCTIONALITY
GUARANTEED
IN THIS AREA
f
[MHz]
OSC
(UNLESS OTHERWISE
STATED IN THE
TABLES OF
PARAMETRIC DATA)
16
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
8
4
FUNCTIONALITY
GUARANTEED
IN THIS AREA
1
0
AT T 0 to 70°C
A
SUPPLY VOLTAGE [V]
5.5
2.7
2.0
2.4
3.3
3.5
4.0
4.5
5.0
124/171
ST72260G, ST72262G, ST72264G
OPERATING CONDITIONS (Cont’d)
13.3.2 Low Voltage Detector (LVD) Thresholds
T = -40 to +85°C unless otherwise specified
A
Symbol
Parameter
Conditions
High Threshold
Med. Threshold
Low Threshold
Min
Typ
Max
Unit
1)
4.0
4.2
3.75
3.15
4.5
4.0
3.35
Reset release threshold
1)
1)
V
3.55
2.95
IT+(LVD)
(V rise)
DD
V
1)
High Threshold
Med. Threshold
Low Threshold
3.75
3.3
2.75
4.0
3.55
3.0
4.25
3.75
3.15
Reset generation threshold
1)
1)
V
V
IT-(LVD)
hys(LVD)
(V fall)
DD
LVD voltage threshold hysteresis
V
-V
150
20
200
250
mV
µs/V
ms/V
ns
IT+(LVD) IT-(LVD)
1)2)
Vt
V
rise time rate
POR
DD
100
40
1)
t
Filtered glitch delay on V
Not detected by the LVD
g(VDD)
DD
Notes:
1. Data based on characterization results, not tested in production.
2. When Vt is faster than 100 µs/V, the Reset signal is released after a delay of max. 42µs after V
crosses the
DD
POR
threshold.
V
IT+(LVD)
Figure 65. LVD Startup Behaviour
5V
LVD RESET
V
IT+
1.5V
0.8V
Window
t
Note: When the LVD is enabled, the MCU reaches its authorized operating voltage from a reset state.
However, in some devices, the reset state is released when V is approximately between 0.8V and 1.5V.
DD
As a consequence, depending on the ramp-up speed, the I/Os may toggle when V
dow.
is within this win-
DD
This may be an issue especially for applications where the MCU drives power components.
Because Flash write access is impossible within this window, the Flash memory contents will not be cor-
rupted.
125/171
ST72260G, ST72262G, ST72264G
OPERATING CONDITIONS (Cont’d)
13.3.3 Auxiliary Voltage Detector (AVD) Thresholds
T = -40 to +85°C unless otherwise specified
A
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
1)
VD level = Low in option byte
VD level = Med. in option byte 3.9
VD level = High in option byte 3.4
4.4
4.6
4.2
3.6
4.9
4.4
3.8
1
0 AVDF flag toggle threshold
1)
1)
V
IT+(AVD)
(V rise)
DD
V
1)
VD level = Low in option byte
VD level = Med. in option byte 3.75
VD level = High in option byte 3.1
4.15
4.4
3.95
3.4
4.65
4.2
3.6
0
1 AVDF flag toggle threshold
1)
V
V
IT-(AVD)
hys(AVD)
(V fall)
1)
DD
AVD voltage threshold hysteresis
V
-V
250
IT+(AVD) IT-(AVD)
mV
Voltage drop between AVD flag set
and LVD reset activated
∆V
V -V
IT-(AVD) IT-(LVD)
450
IT-
1. Data based on characterization results, not tested in production.
126/171
ST72260G, ST72262G, ST72264G
13.4 SUPPLY CURRENT CHARACTERISTICS
The following current consumption specified for the ST7 functional operating modes over temperature
range does not take into account the clock source current consumption. To get the total device consump-
tion, the two current values must be added (except for HALT mode for which the clock is stopped).
Symbol
∆I
Parameter
Conditions
Max
Unit
Supply current variation vs. temperature
Constant V and f
CPU
10
%
DD(∆Ta)
DD
13.4.1 RUN, SLOW, WAIT and SLOW WAIT Modes
T = -40 to +85°C unless otherwise specified
A
Symbol
Parameter
Conditions
Typ
Max
Unit
2)
1)
Supply current in RUN mode
(see Figure 66)
V
V
=5.5V,f
=2.7V, f
=16MHz, f
=8MHz
CPU
7.2
3.5
11
DD
DD
OSC
4)
=8MHz, f
=4MHz
5.25
OSC
CPU
3)
1)
4)
Supply current in SLOW mode
(see Figure 67)
V
V
=5.5V, f
=2.7V, f
=16MHz, f
=500kHz
CPU
0.7
0.38
1.2
0.6
DD
DD
OSC
OSC
=8MHz, f
=250MHz
CPU
I
mA
DD
2)
1)
4)
Supply current in WAIT mode
(see Figure 68)
V
V
=5.5V,f
=2.7V, f
=16MHz, f
=8MHz
CPU
3.6
1.8
5.55
3
DD
DD
OSC
=8MHz, f
=4MHz
OSC
CPU
3)
1)
Supply current in SLOW WAIT mode
(see Figure 69)
V
V
=5.5V, f
=2.7V, f
=500kHz
CPU
0.45
0.25
1
DD
DD
OSC
OSC
4)
=250MHz
0.5
Figure 66. Typical I in RUN at T =25°C
Figure 68. Typical I in WAIT at T =25°C
DD
A
DD
A
10
9
8
7
6
5
4
3
2
1
0
Fosc=16MHz
Fosc=8MHz
Fosc=4MHz
Fosc=2MHz
Fosc=16MHz
Fosc=8MHz
Fosc=4MHz
Fosc=2MHz
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
2.5
3
3.5
4
4.5
5
5.5
6
6.5
2.5
3
3.5
4
4.5
5
5.5
6
6.5
Vdd(V)
Vdd (V)
Figure 67. Typical I in SLOW at T =25°C
Figure 69. Typ. I in SLOW-WAIT at T =25°C
DD A
DD
A
0.6
0.5
0.4
0.3
0.2
0.1
0
Fosc=16MHz
Fosc=8MHz
Fosc=4MHz
Fosc=2MHz
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
Fosc=16MHz
Fosc=8MHz
Fosc=4MHz
Fosc=2MHz
2.5
3
3.5
4
4.5
5
5.5
6
6.5
2.5
3
3.5
4
4.5
5
5.5
6
6.5
Vdd(V)
Vdd(V)
Notes:
1. Data based on characterization results, tested in production at V max. and f
max.
CPU
DD
2. Program executed from RAM, CPU running with memory access, all I/O pins in input mode with a static value at V
DD
or V (no load), all peripherals in reset state; clock input (OSC1) driven by external square wave, CSS and LVD disabled.
SS
3. All I/O pins in input mode with a static value at V or V (no load), all peripherals in reset state; clock input (OSC1)
DD
SS
driven by external square wave, CSS and LVD disabled.
4. Data based on characterization results, not tested in production.
127/171
ST72260G, ST72262G, ST72264G
SUPPLY CURRENT CHARACTERISTICS (Cont’d)
13.4.2 HALT and ACTIVE-HALT Modes
Symbol
Parameter
Conditions
=5.5V -40°C≤T ≤+85°C
Typ
Max
10
6
Unit
V
V
DD
A
1)
Supply current in HALT mode
=2.7V -40°C≤T ≤+85°C
DD
A
I
µA
DD
Nomax.
guaran-
teed
2)
Supply current in ACTIVE-HALT mode
500
13.4.3 Supply and Clock Managers
The previous current consumption specified for
the ST7 functional operating modes over tempera-
ture range does not take into account the clock
source current consumption. To get the total de-
vice consumption, the two current values must be
added (except for HALT mode).
Symbol
Parameter
Conditions
Typ
Max
Unit
I
Supply current of internal RC oscillator
900
DD(RCINT)
see Section
13.5.3 on page
131
3) & 4)
I
I
Supply current of resonator oscillator
DD(RES)
µA
I
PLL supply current
V
V
=5V
=5V
100
220
100
DD(PLL)
DD
Clock security system supply current
LVD supply current
DD(CSS)
DD
I
HALT mode
DD(LVD)
Notes:
1. All I/O pins in output mode with a static value at V (no load), CSS and LVD disabled. Data based on characterization
SS
max.
results, tested in production at V max. and f
DD
CPU
2. Data based on characterisation results, not tested in production. All I/O pins in output mode with a static value at V
SS
(no load); clock input (OSC1) driven by external square wave, LVD disabled. To obtain the total current consumption of
the device, add the clock source consumption (Section 13.5.3 and Section 13.5.4).
3. Data based on characterization results done with the external components specified in Section 13.5.3 and Section
13.5.4, not tested in production.
4. As the oscillator is based on a current source, the consumption does not depend on the voltage.
128/171
ST72260G, ST72262G, ST72264G
SUPPLY CURRENT CHARACTERISTICS (Cont’d)
13.4.4 On-chip peripherals
Symbol
Parameter
Conditions
Typ
TBD
60
Unit
f
f
f
f
f
f
f
f
=4MHz
=8MHz
=4MHz
=8MHz
=4MHz
=8MHz
=4MHz
=8MHz
V
V
V
V
V
V
V
V
V
V
=3.0V
=5.0V
=3.0V
=5.0V
=3.0V
=5.0V
=3.0V
=5.0V
=3.0V
=5.0V
CPU
CPU
CPU
CPU
CPU
CPU
CPU
CPU
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
1)
I
16-bit Timer supply current
DD(TIM)
TBD
200
TBD
400
TBD
500
TBD
500
2)
3)
4)
I
I
SPI supply current
SCI supply current
I2C supply current
DD(SPI)
µA
DD(SCI)
I
DD(I2C)
5)
I
ADC supply current when converting
f
=4MHz
DD(ADC)
ADC
Notes:
1. Data based on a differential I measurement between reset configuration (timer counter running at f
/2) and timer
DD
CPU
counter stopped (only TIMD bit set). Data valid for one timer.
2. Data based on a differential I measurement between reset configuration (SPI disabled) and a permanent SPI master
DD
communication at maximum speed (data sent equal to FFh).This measurement includes the pad toggling consumption.
3. Data based on a differential I measurement between SCI running at maximum speed configuration (500 kbaud, con-
DD
tinuous transmission of AA +RE enabled and SCI off. This measurement includes the pad toggling consumption.
4. Data based on a differential I measurement between reset configuration (I2C disabled) and a permanent I2C master
DD
communication at 300kHz (data sent equal to AAh). This measurement includes the pad toggling consumption
(4.7kOhm external pull-up on clock and data lines).
5. Data based on a differential I measurement between reset configuration (ADC off) and continuous A/D conversion
DD
(f
=4MHz).
ADC
129/171
ST72260G, ST72262G, ST72264G
13.5 CLOCK AND TIMING CHARACTERISTICS
Subject to general operating conditions for V , f
, and T .
DD OSC
A
13.5.1 General Timings
1)
Symbol
Parameter
Conditions
Min
2
Typ
Max
12
Unit
tCPU
ns
3
t
Instruction cycle time
c(INST)
f
f
=8MHz
250
10
375
1500
22
CPU
2)
tCPU
µs
Interrupt reaction time
t
v(IT)
t
= ∆t
+ 10
=8MHz
1.25
2.75
v(IT)
c(INST)
CPU
13.5.2 External Clock Source
Symbol
Parameter
Conditions
Min
0.7xV
Typ
Max
Unit
V
OSC1 input pin high level voltage
OSC1 input pin low level voltage
V
DD
OSC1H
DD
SS
V
V
V
0.3xV
OSC1L
DD
t
t
3)
w(OSC1H)
see Figure 70
OSC1 high or low time
15
w(OSC1L)
ns
t
t
3)
r(OSC1)
OSC1 rise or fall time
15
±1
f(OSC1)
I
OSCx Input leakage current
V
≤V ≤V
DD
µA
L
SS
IN
Figure 70. Typical Application with an External Clock Source
90%
V
V
OSC1H
OSC1L
10%
t
t
w(OSC1H)
t
t
w(OSC1L)
f(OSC1)
r(OSC1)
OSC2
Not connected internally
f
OSC
EXTERNAL
CLOCK SOURCE
I
L
OSC1
ST72XXX
Notes:
1. Data based on typical application software.
2. Time measured between interrupt event and interrupt vector fetch. ∆tc(INST) is the number of tCPU cycles needed to finish
the current instruction execution.
3. Data based on design simulation and/or technology characteristics, not tested in production.
130/171
ST72260G, ST72262G, ST72264G
CLOCK AND TIMING CHARACTERISTICS (Cont’d)
13.5.3 Crystal and Ceramic Resonator Oscillators
The ST7 internal clock can be supplied with four
different Crystal/Ceramic resonator oscillators. All
the information given in this paragraph are based
on characterization results with specified typical
external components. In the application, the reso-
nator and the load capacitors have to be placed as
close as possible to the oscillator pins in order to
minimize output distortion and start-up stabiliza-
tion time. Refer to the crystal/ceramic resonator
manufacturer for more details (frequency, pack-
age, accuracy...).
Symbol
Parameter
Conditions
Min
Max
Unit
MHz
kΩ
VLP : Very Low power oscillator
LP: Low power oscillator
MP: Medium power oscillator
MS: Medium speed oscillator
HS: High speed oscillator
0.032
1
>2
>4
>8
0.1
2
4
8
16
1)
f
Oscillator Frequency
OSC
R
Feedback resistor
20
40
F
VLP oscillator
60
38
32
10
10
100
100
47
47
30
Recommended load capacitance ver- R =200Ω
LP oscillator
MP oscillator
MS oscillator
HS oscillator
S
C
C
L1
L2
sus equivalent serial resistance of the R =200Ω
pF
S
crystal or ceramic resonator (R )
R =200Ω
S
S
R =100Ω
S
Symbol
Parameter
Conditions
Typ
Max
Unit
VLP oscillator
LP oscillator
MP oscillator
MS oscillator
HS oscillator
2.5
80
160
310
610
5
V
=5V
150
250
460
900
DD
i
OSC2 driving current
V =V
µA
2
IN
SS
Figure 71. Typical Application with a Crystal or Ceramic Resonator
WHEN RESONATOR WITH
INTEGRATED CAPACITORS
i
2
f
OSC
C
L1
OSC1
OSC2
RESONATOR
R
F
C
L2
R
D
ST72XXX
Notes:
1. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small R value.
S
Refer to crystal/ceramic resonator manufacturer for more details.
131/171
ST72260G, ST72262G, ST72264G
CLOCK AND TIMING CHARACTERISTICS (Cont’d)
Typical Crystal or Ceramic Resonators
C
C
L2
R
L1
D
Oscil.
Freq.
2)
3)
1)
[ohm]
[pF] [pF]
Reference
Type
Characteristic
(MHz)
SMD
LEAD
SMD
SMD
LEAD
SMD
LEAD
SMD
LEAD
SMD
LEAD
CSBFB1M00J58-R0
CSBLA1M00J58-B0
CSTCC2M00G56-R0
CSTCR4M00G55-R0
CSTLS4M00G56-B0
CSTCE8M00G52-R0
CSTLS8M00G53-B0
CSTCE12M0G52-R0
CSTLA12M0T55-B0
CSTCE16M0V53-R0
CSALS16M0X55-B0
∆f
∆f
∆f
∆f
∆f
∆f
∆f
∆f
∆f
∆f
∆f
=[±0.5%
=[±0.5%
=[±0.5%
=[±0.5%
=[±0.5%
=[±0.5%
=[±0.5%
=[±0.5%
=[±0.5%
=[±0.5%
=[±0.5%
,±0.3% ,±0.3%
,0.01%
,0.01%
]
]
100 100 3.3k
100 100 3.3k
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
tolerance
tolerance
tolerance
tolerance
tolerance
tolerance
tolerance
tolerance
tolerance
tolerance
tolerance
∆Ta
aging
aging
aging
aging
aging
aging
aging,
correl
correl
1
2
4
,±0.3% ,±0.3%
∆Ta
,±0.3% ,±0.3%
,-0.19%
,-0.24%
]
]
(47) (47)
(39) (39)
(47) (47)
(10) (10)
(15) (15)
(10) (10)
(30) (30)
(15) (15)
0
0
0
0
0
0
0
0
∆Ta
correl
correl
,±0.2% ,±0.1%
∆Ta
,±0.2% ,±0.2%
,0.1%
]
∆Ta
correl
,±0.2% ,±0.1%
,-0.16%
]
]
]
∆Ta
correl
8
,±0.2% ,±0.2%
0.13%
]
∆Ta
correl
,±0.2% ,±0.1%
,-0.18%
correl
∆Ta
aging
aging
aging
aging
12
16
,±0.3% ,±0.3%
,0.29%
]
∆Ta
correl
,±0.3% ,±0.3%
,-0.08%
correl
∆Ta
,±0.2% ,±0.2%
,0.11%
]
correl
10 10 470
∆Ta
Notes:
1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
2. CSTxx types have built-in loading capacitors (values shown in parentheses)
3. SMD = [-R0: Plastic tape package ( =180mm), -B0: Bulk]
LEAD = [-A0: Flat pack package (Radial taping Ho= 18mm), -B0: Bulk]
For more information, please consult the Murata report (02gc_5959_ST72F264G2.zip) on www.murata.com or http//
:mcu.st.com
132/171
ST72260G, ST72262G, ST72264G
CLOCK CHARACTERISTICS (Cont’d)
13.5.4 RC Oscillators
The ST7 internal clock can be supplied with an in-
ternal RC oscillator.
Symbol
Parameter
Internal RC oscillator frequency
See Figure 73
Conditions
Min
Typ
Max
Unit
T =25°C, V =5V
f
2
3.5
6
MHz
A
DD
OSC (RCINT)
Figure 72. Typical Application with RC oscillator
ST72XXX
V
DD
INTERNAL RC
Current copy
C
IN
R
IN
+
-
V
f
REF
OSC
Voltage generator
C
EX discharge
Figure 73. Typical f
vs V
DD
OSC(RCINT)
4.5
4
3.5
3
2.5
2
T=25C
T=130C
T=-45C
1.5
1
0.5
0
2.35
5
5.5
Vdd(V
)
133/171
ST72260G, ST72262G, ST72264G
CLOCK CHARACTERISTICS (Cont’d)
Clock Security System (CSS)
13.5.5
T = -40 to +85°C unless otherwise specified
A
Symbol
Parameter
Conditions
Conditions
Min
Typ
Max
Unit
1)
f
Safe Oscillator Frequency
3
MHz
SFOSC
Note:
1. Data based on characterisation results.
13.5.6 PLL Characteristics
Symbol
Parameter
Min
Typ
Max
Unit
T 0 to 70°C
3.5
4.5
2
5.5
5.5
4
A
V
PLL Operating Range
PLL input frequency range
V
DD(PLL)
OSC
T -40 to +85°C
A
f
MHz
%
f
f
= 4 MHz.
= 2 MHz.
1.0
2.5
2.5
4.0
OSC
1)
∆ f
/f
Instantaneous PLL jitter
CPU CPU
%
OSC
Note:
1. Data characterized but not tested.
1
Figure 74. PLL Jitter vs. Signal frequency
The user must take the PLL jitter into account in
the application (for example in serial communica-
tion or sampling of high frequency signals). The
PLL jitter is a periodic effect, which is integrated
over several CPU cycles. Therefore the longer the
period of the application signal, the less it will be
impacted by the PLL jitter.
0.8
0.7
PLL ON
0.6
0.5
0.4
0.3
0.2
0.1
0
PLL OFF
Figure 74 shows the PLL jitter integrated on appli-
cation signals in the range 125kHz to 2MHz. At fre-
quencies of less than 125KHz, the jitter is negligi-
ble.
2000
1000
500
250
125
Application Signal Frequency (KHz)
Note 1: Measurement conditions: f
= 4MHz, T = 25°C
A
CPU
134/171
ST72260G, ST72262G, ST72264G
13.6 MEMORY CHARACTERISTICS
13.6.1 RAM and Hardware Registers
Symbol
Parameter
Conditions
Min
Typ
Typ
Max
Unit
1)
V
Data retention mode
HALT mode (or RESET)
1.6
V
RM
13.6.2 XFlash Program Memory
Symbol
Parameter
Conditions
Min
Max
Unit
V
Operating voltage for Flash write/
erase
2.4
5.5
V
DD
2)
T =−40 to +85°C
5
10
Programming time for 1~32 bytes
Programming time for 1.5kBytes
ms
A
t
t
prog
T =+25°C
0.24
0.48
A
4)
3)
Data retention
T =+55°C
20
10
years
RET
A
N
Write erase cycles
T =+25°C
kcycles
RW
A
Read / Write / Erase
3)
modes
2.6
mA
f
= 8MHz, V = 5.5V
I
Supply current
CPU
DD
DD
No Read/No Write Mode
Power down mode / HALT
100
µA
µA
5)
0
0.1
Notes:
1. Minimum V supply voltage without losing data stored in RAM (in HALT mode or under RESET) or in hardware reg-
DD
isters (only in HALT mode). Guaranteed by construction, not tested in production.
2. Up to 32 bytes can be programmed at a time.
3. The data retention time increases when the T decreases.
A
4. Data based on reliability test results and monitored in production.
5. Data based on characterization results, not tested in production.
135/171
ST72260G, ST72262G, ST72264G
13.7 EMC CHARACTERISTICS
Susceptibility tests are performed on a sample ba-
sis during product characterization.
■ ESD: Electro-Static Discharge (positive and
negative) is applied on all pins of the device until
a functional disturbance occurs. This test
conforms with the IEC 1000-4-2 standard.
13.7.1 Functional EMS
(Electro Magnetic Susceptibility)
■ FTB: A Burst of Fast Transient voltage (positive
Based on a simple running application on the
product (toggling 2 LEDs through I/O ports), the
product is stressed by two electro magnetic events
until a failure occurs (indicated by the LEDs).
and negative) is applied to V and V through
DD
SS
a 100pF capacitor, until a functional disturbance
occurs. This test conforms with the IEC 1000-4-
4 standard.
The level classification is described in application
note AN1637.
A device reset allows normal operations to be re-
sumed.
1)
1)
Symbol
Parameter
Conditions
=5V, T =+25°C, f
conforms to IEC 1000-4-2
Neg
Pos
Unit
Voltage limits to be applied on any I/O pin
to induce a functional disturbance
V
=8MHz
OSC
DD
A
V
TBD
TBD
TBD
TBD
FESD
kV
Fast transient voltage burst limits to be ap-
V
=5V, T =+25°C, f
=8MHz
OSC
DD
A
V
plied through 100pF on V and V pins
FFTB
DD DD
conforms to IEC 1000-4-4
to induce a functional disturbance
13.7.2 Electro Magnetic Interference (EMI)
Based on a simple application running on the product (toggling 2 LEDs through the I/O ports), the product
is monitored in terms of emission. This emission test is in line with the norm SAE J 1752/3 which specifies
the board and the loading of each pin.
Max vs. [f
/f
]
Unit
Monitored
Frequency Band
OSC CPU
Symbol
Parameter
Conditions
8/4MHz 16/8MHz
0.1MHz to 30MHz
30MHz to 130MHz
130MHz to 1GHz
SAE EMI Level
10
13
16
2.5
13
24
31
4
dBµV
V
=5V, T =+25°C,
A
DD
S
Peak level
EMI
conforming to SAE J 1752/3
-
Notes:
1. Data based on characterization results, not tested in production.
136/171
ST72260G, ST72262G, ST72264G
EMC CHARACTERISTICS (Cont’d)
13.7.3 Absolute Electrical Sensitivity
Machine Model Test Sequence
Based on three different tests (ESD, LU and DLU)
using specific measurement methods, the product
is stressed in order to determine its performance in
terms of electrical sensitivity. For more details, re-
fer to the AN1181 ST7 application note.
– C is loaded through S1 by the HV pulse gener-
ator.
L
– S1 switches position from generator to ST7.
– A discharge from C to the ST7 occurs.
L
– S2 must be closed 10 to 100ms after the pulse
delivery period to ensure the ST7 is not left in
charge state. S2 must be opened at least 10ms
prior to the delivery of the next pulse.
13.7.3.1 Electro-Static Discharge (ESD)
Electro-Static Discharges (a positive then a nega-
tive pulse separated by 1 second) are applied to
the pins of each sample according to each pin
combination. The sample size depends of the
number of supply pins of the device (3 parts*(n+1)
supply pin). Two models are usually simulated:
Human Body Model and Machine Model. This test
conforms to the JESD22-A114A/A115A standard.
See Figure 75 and the following test sequences.
– R (machine resistance), in series with S2, en-
sures a slow discharge of the ST7.
Human Body Model Test Sequence
– C is loaded through S1 by the HV pulse gener-
L
ator.
– S1 switches position from generator to R.
– A discharge from C through R (body resistance)
L
to the ST7 occurs.
– S2 must be closed 10 to 100ms after the pulse
delivery period to ensure the ST7 is not left in
charge state. S2 must be opened at least 10ms
prior to the delivery of the next pulse.
Absolute Maximum Ratings
1)
Symbol
Ratings
Conditions
Maximum value
Unit
Electro-static discharge voltage
(Human Body Model)
T =+25°C
V
2000
A
ESD(HBM)
V
Electro-static discharge voltage
(Machine Model)
T =+25°C
V
200
A
ESD(MM)
Figure 75. Typical Equivalent ESD Circuits
S1
R=1500Ω
S1
HIGH VOLTAGE
PULSE
GENERATOR
HIGH VOLTAGE
PULSE
GENERATOR
ST7
ST7
C =100pF
S2
L
S2
C =200pF
L
HUMAN BODY MODEL
MACHINE MODEL
Notes:
1. Data based on characterization results, not tested in production.
137/171
ST72260G, ST72262G, ST72264G
EMC CHARACTERISTICS (Cont’d)
13.7.3.2 Static and Dynamic Latch-Up
should be noted that good EMC performance is
highly dependent on the user application and the
software in particular.
■ LU: 3 complementary static tests are required
on 10 parts to assess the latch-up performance.
A supply overvoltage (applied to each power
supply pin) and a current injection (applied to
each input, output and configurable I/O pin) are
performed on each sample. This test conforms
to the EIA/JESD 78 IC latch-up standard. For
more details, refer to the AN1181 ST7
application note.
■ DLU: Electro-Static Discharges (one positive
then one negative test) are applied to each pin
of 3 samples when the micro is running to
assess the latch-up performance in dynamic
mode. Power supplies are set to the typical
values, the oscillator is connected as near as
possible to the pins of the micro and the
component is put in reset mode. This test
conforms to the IEC1000-4-2 and SAEJ1752/3
standards and is described in Figure 76. For
more details, refer to the AN1181 ST7
application note.
Therefore it is recommended that the user applies
EMC software optimization and prequalification
tests in relation with the EMC level requested for
his application.
Software recommendations:
The software flowchart must include the manage-
ment of runaway conditions such as:
– Corrupted program counter
– Unexpected reset
– Critical Data corruption (control registers...)
Prequalification trials:
Most of the common failures (unexpected reset
and program counter corruption) can be repro-
duced by manually forcing a low state on the RE-
SET pin or the Oscillator pins for 1 second.
To complete these trials, ESD stress can be ap-
plied directly on the device, over the range of
specification values. When unexpected behaviour
is detected, the software can be hardened to pre-
vent unrecoverable errors occurring (see applica-
tion note AN1015).
13.7.3.3 Designing hardened software to avoid
noise problems
EMC characterization and optimization are per-
formed at component level with a typical applica-
tion environment and simplified MCU software. It
Electrical Sensitivities
1)
Symbol
LU
Parameter
Static latch-up class
Dynamic latch-up class
Conditions
Class
T =+25°C
A
A
A
T =+85°C
A
V
=5.5V, f
=4MHz, T =+25°C
DLU
A
DD
OSC
A
Figure 76. Simplified Diagram of the ESD Generator for DLU
R
2)
=50MΩ
R =330Ω
D
CH
DISCHARGE TIP
V
V
DD
SS
HV RELAY
C =150pF
S
ST7
ESD
DISCHARGE
RETURN CONNECTION
GENERATOR
Notes:
1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC spec-
ifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the
JEDEC criteria (international standard).
2. Schaffner NSG435 with a pointed test finger.
138/171
ST72260G, ST72262G, ST72264G
EMC CHARACTERISTICS (Cont’d)
13.7.4 ESD Pin Protection Strategy
Standard Pin Protection
To protect an integrated circuit against Electro-
Static Discharge the stress must be controlled to
prevent degradation or destruction of the circuit el-
ements. The stress generally affects the circuit el-
ements which are connected to the pads but can
also affect the internal devices when the supply
pads receive the stress. The elements to be pro-
tected must not receive excessive current, voltage
or heating within their structure.
To protect the output structure the following ele-
ments are added:
– A diode to V (3a) and a diode from V (3b)
DD
SS
– A protection device between V and V (4)
DD
SS
To protect the input structure the following ele-
ments are added:
– A resistor in series with the pad (1)
– A diode to V (2a) and a diode from V (2b)
DD
SS
– A protection device between V and V (4)
An ESD network combines the different input and
output ESD protections. This network works, by al-
lowing safe discharge paths for the pins subjected
to ESD stress. Two critical ESD stress cases are
presented in Figure 77 and Figure 78 for standard
pins and in Figure 79 and Figure 80 for true open
drain pins.
DD
SS
Figure 77. Positive Stress on a Standard Pad vs. V
SS
V
V
DD
DD
(3a)
(3b)
(2a)
(1)
(4)
OUT
IN
Main path
(2b)
Path to avoid
V
V
V
SS
SS
Figure 78. Negative Stress on a Standard Pad vs. V
DD
V
DD
DD
(3a)
(3b)
(2a)
(1)
(4)
OUT
IN
Main path
(2b)
V
V
SS
SS
139/171
ST72260G, ST72262G, ST72264G
EMC CHARACTERISTICS (Cont’d)
True Open Drain Pin Protection
Multisupply Configuration
When several types of ground (V , V
The centralized protection (4) is not involved in the
discharge of the ESD stresses applied to true
open drain pads due to the fact that a P-Buffer and
, ...) and
SSA
SS
power supply (V , V
, ...) are available for
DD
AREF
any reason (better noise immunity...), the structure
shown in Figure 81 is implemented to protect the
device against ESD.
diode to V
local protection between the pad and V
are not implemented. An additional
DD
(5a &
SS
5b) is implemented to completely absorb the posi-
tive ESD discharge.
Figure 79. Positive Stress on a True Open Drain Pad vs. V
SS
V
V
DD
DD
Main path
(1)
OUT
(4)
IN
Path to avoid
(5a)
(5b)
(3b)
(2b)
V
V
SS
SS
Figure 80. Negative Stress on a True Open Drain Pad vs. V
DD
V
V
DD
DD
Main path
(1)
OUT
(4)
IN
(3b)
(3b)
(3b)
(2b)
V
V
SS
SS
Figure 81. Multisupply Configuration
V
DD
V
AREF
V
AREF
V
SS
BACK TO BACK DIODE
BETWEEN GROUNDS
V
SSA
V
SSA
140/171
ST72260G, ST72262G, ST72264G
13.8 I/O PORT PIN CHARACTERISTICS
13.8.1 General Characteristics
T = -40 to +85°C unless otherwise specified
A
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
V
1)
V
Input low level voltage
Input high level voltage
0.3xVDD
IL
1)
V
0.7xVDD
IH
1)
V
Schmitt trigger voltage hysteresis
Injected Current on an I/O pin
400
mV
hys
2)
I
±4
INJ(PIN)
V
V
=5V
mA
Total injected current (sum of all I/O
and control pins)
DD
2)
ΣI
±25
INJ(PIN)
I
Input leakage current
SS≤V ≤V
DD
±1
L
IN
µA
3)
I
Static current consumption
Floating input mode
200
S
V
V
=5V
=3V
50
85
190
5
250
DD
DD
4)
R
Weak pull-up equivalent resistor
V =V
SS
kΩ
pF
ns
PU
IN
1)
1)
170
230
C
I/O pin capacitance
IO
1)
t
Output high to low level fall time
25
25
C =50pF
f(IO)out
r(IO)out
L
1)
Between 10% and 90%
t
Output low to high level rise time
5)
t
External interrupt pulse time
1
t
CPU
w(IT)in
Notes:
1. Data based on characterization results, not tested in production.
2. When the current limitation is not possible, the V maximum must be respected, otherwise refer to I
specifica-
INJ(PIN)
IN
tion. A positive injection is induced by V >V while a negative injection is induced by V <V . Refer to Section 13.2.2
IN DD
IN
SS
on page 123 for more details.
3. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for
example or an external pull-up or pull-down resistor (see Figure 82). Data based on design simulation and/or technology
characteristics, not tested in production.
4. The R pull-up equivalent resistor is based on a resistive transistor (corresponding I current characteristics de-
PU
PU
scribed in Figure 83).
5. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external
interrupt source.
Figure 82. Two typical Applications with unused I/O Pin
V
DD
ST7XXX
UNUSED I/O PORT
10kΩ
10kΩ
UNUSED I/O PORT
ST7XXX
141/171
ST72260G, ST72262G, ST72264G
I/O PORT PIN CHARACTERISTICS (Cont’d)
Figure 83. Typical I vs. V with V =V
SS
PU
DD
IN
120
100
80
60
40
20
0
T=25C
T=-45C
T=90C
2 2.5 3 3.5 4 4.5 5 5.5 6
Vdd(V)
Figure 84. Typical V
IL
2.5
2
1.5
1
T=25C
T=-45C
0.5
0
2
3
4
5
6
Vdd(V)
Figure 85. Typical V
IH
4
3
2
1
T=25C
T=-45C
2
3
4
5
6
Vdd(V)
142/171
ST72260G, ST72262G, ST72264G
I/O PORT PIN CHARACTERISTICS (Cont’d)
13.8.2 Output Driving Current
T = -40 to +85°C unless otherwise specified
A
Symbol
Parameter
Conditions
Min
Max
1.2
Unit
I
I
I
I
I
I
=+5mA
IO
Output low level voltage for a standard I/O pin
when 8 pins are sunk at same time
=+2mA
=+20mA,
=+8mA
=-5mA,
=-2mA
0.5
IO
IO
IO
IO
IO
1)
V
OL
1.3
Output low level voltage for a high sink I/O pin
when 4 pins are sunk at same time
0.75
V
V
-1.6
Output high level voltage for an I/O pin
when 4 pins are sourced at same time
DD
2)
V
OH
-0.8
DD
Output low level voltage for a standard I/O pin
when 8 pins are sunk at same time
I
I
I
I
I
I
=+2mA
=+8mA
0.6
0.6
IO
IO
IO
IO
IO
IO
1)3)
2)3)
1)3)
2)3)
V
OL
OH
Output low level voltage for a high sink I/O pin
when 4 pins are sunk at same time
V
Output high level voltage for an I/O pin
when 4 pins are sourced at same time
=-2mA T ≤85°C
V
V
-0.8
A
DD
Output low level voltage for a standard I/O pin
when 8 pins are sunk at same time
=+2mA
=+8mA
=-2mA
0.7
0.7
V
OL
Output low level voltage for a high sink I/O pin
when 4 pins are sunk at same time
Output high level voltage for an I/O pin
when 4 pins are sourced at same time
V
V -0.9
DD
OH
Notes:
1. The I current sunk must always respect the absolute maximum rating specified in Section 13.2.2 and the sum of I
IO
IO
(I/O ports and control pins) must not exceed I
.
VSS
2. The I current sourced must always respect the absolute maximum rating specified in Section 13.2.2 and the sum of
IO
I
(I/O ports and control pins) must not exceed I
. True open drain I/O pins does not have V
.
IO
VDD
OH
3. Not tested in production, based on characterization results.
143/171
ST72260G, ST72262G, ST72264G
I/O PORT PIN CHARACTERISTICS (Cont’d)
Figure 86. Typ. V at V =2.4V (standard)
Figure 89. Typ. V at V =2.7V (standard)
OL DD
OL
DD
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0.5
0.5
0.4
0.4
0.3
0.3
0.2
0.2
0.1
0.1
0.0
T=25C
T=90C
T=-45C
T=25C
T=90C
T=-45C
0
1
2
0
1
2
Iio (mA)
Iio(mA)
Figure 87. Typ. V at V =5V (standard)
Figure 90. Typ. V at V =2.4V (high-sink)
OL DD
OL
DD
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1.8
1.6
1.4
1.2
1
T=25C
T=90C
T=-45C
T=25C
T=90C
T=-45C
0.8
0.6
0.4
0.2
0
0
2
4
6
8
10
0
1
2
3
4
5
6
7
8
9
10
Iol(mA)
Iio(mA)
Figure 88. Typ. V at V =3V (high-sink)
Figure 91. Typ. V at V =5V (high-sink)
OL DD
OL
DD
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
T=25C
T=90C
T=-45C
T=25C
T=90C
T=-45C
0 1 2 3 4 5 6 7 8 9 1011 121314151617181920
Iio(mA)
0
2
4
6
8
10
12
14
16
Iol(mA)
144/171
ST72260G, ST72262G, ST72264G
I/O PORT PIN CHARACTERISTICS (Cont’d)
Figure 92. Typ. V
at V =2.7V
Figure 95. Typ. V
at V =3V
OH
DD
OH DD
3
2.5
2
3.5
3
2.5
2
T=25C
T=90C
T=-45C
T=25C
T=90C
T=-45C
1.5
1
1.5
1
0.5
0
0.5
0
0
1
2
3
0
0.5
1
1.5
2
Iio(mA)
Iio(mA)
Figure 96. Typ. V
at V =5V
DD
Figure 93. Typ. V
at V =4V
DD
OH
OH
4.5
4
6
5
4
3.5
3
T=25C
T=90C
T=-45C
2.5
2
T=25C
T=90C
T=-45C
3
2
1
0
1.5
1
0.5
0
0
1
2
3
4
5
0
1
2
3
4
5
Iio(mA)
Iio(mA)
Figure 94. Typ. V
at V =2.4V
DD
OH
3
2.5
2
T=25C
T=90C
T=-45C
1.5
1
0.5
0
0
0.5
1
1.5
2
Iio(mA)
Notes:
1. The I current sunk must always respect the absolute maximum rating specified in Section 13.2.2 and the sum of I
IO
IO
(I/O ports and control pins) must not exceed I
.
VSS
2. The I current sourced must always respect the absolute maximum rating specified in Section 13.2.2 and the sum of
IO
I
(I/O ports and control pins) must not exceed I
. True open drain I/O pins does not have V
.
IO
VDD
OH
145/171
ST72260G, ST72262G, ST72264G
I/O PORT PIN CHARACTERISTICS (Cont’d)
Figure 97. Typical V vs. V on standard I/O port (Ports B and C)
OL
DD
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
T=25C
T=90C
T=-45C
0.6
0.5
0.4
0.3
0.2
0.1
0.0
T=25C
T=90C
T=-45C
2.5
3
3.5
4
5
5.5
6
3.5
4
5
5.5
6
Vdd (V)
Vdd (V)
Figure 98. Typical V vs. V on high sink I/O port (Port A)
OL
DD
0.6
0.5
0.4
0.3
0.2
0.1
0.0
1.2
1.0
0.8
0.6
0.4
0.2
0.0
T=25C
T=90C
T=-45C
T=25C
T=90C
T=-45C
3
3.5
4
5
5.5
6
2.4
3
3.5
4
5
5.5
6
Vdd (V)
Vdd (V)
146/171
ST72260G, ST72262G, ST72264G
13.9 CONTROL PIN CHARACTERISTICS
13.9.1 Asynchronous RESET Pin
T = -40 to +85°C unless otherwise specified
A
Symbol
Parameter
Input low level voltage
Conditions
Min
Typ
Max
Unit
V
V
0.16xVDD
IL
V
Input high level voltage
0.85xVDD
IH
1)
V
Schmitt trigger voltage hysteresis
2.5
0.68
0.28
40
V
hys
I
I
=+5mA
=+2mA
0.95
0.45
80
IO
IO
2)
V
Output low level voltage
V
=5V
V
OL
ON
DD
V
V
=5V
=3V
20
20
DD
R
Pull-up equivalent resistor
kΩ
85
DD
t
Generated reset pulse duration
Internal reset sources
30
µs
µs
ns
w(RSTL)out
4)
t
t
External reset pulse hold time
h(RSTL)in
g(RSTL)in
5)
Filtered glitch duration
200
6)7)8)
Figure 99. Typical Application with RESET pin
Recommended
V
ST72XXX
DD
if LVD is disabled
VDD
VDD
R
ON
Filter
0.01µF
0.01µF
4.7kΩ
INTERNAL
RESET
USER
EXTERNAL
RESET
CIRCUIT 5)
PULSE
GENERATOR
WATCHDOG
LVD RESET
Required if LVD is disabled
Notes:
1. Data based on characterization results, not tested in production.
2. The I current sunk must always respect the absolute maximum rating specified in Section 13.2.2 and the sum of I
IO
IO
(I/O ports and control pins) must not exceed I
.
VSS
3. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on
RESET pin with a duration below t can be ignored.
h(RSTL)in
4. The reset network protects the device against parasitic resets.
5. The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device
can be damaged when the ST7 generates an internal reset (LVD or watchdog).
6. Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin can go below
the V max. level specified in Section 13.9.1 . Otherwise the reset will not be taken into account internally.
IL
7. Because the reset circuit is designed to allow the internal RESET to be output in the RESET pin, the user must ensure
that the current sunk on the RESET pin (by an external pull-up for example) is less than the absolute maximum value
specified for I
in Section 13.2.2 on page 123.
INJ(RESET)
147/171
ST72260G, ST72262G, ST72264G
CONTROL PIN CHARACTERISTICS (Cont’d)
Figure 100. Typical I on RESET pin
PU
250
T=25C
T=90C
200
T=-45C
150
100
50
0
2.4
3
4
5
5.5
6
Vdd (V)
13.10 TIMER PERIPHERAL CHARACTERISTICS
Subject to general operating conditions for V
,
DD
f
, and T unless otherwise specified.
OSC
A
Refer to I/O port characteristics for more details on
the input/output alternate function characteristics
(output compare, input capture, external clock,
PWM output...).
13.10.1 16-Bit Timer
T = -40 to +85°C unless otherwise specified
A
Symbol
Parameter
Conditions
Min
1
Typ
Max
Unit
t
Input capture pulse time
t
t
w(ICAP)in
CPU
2
CPU
t
PWM resolution time
res(PWM)
f
=8MHz
250
0
ns
CPU
f
Timer external clock frequency
PWM repetition rate
f
f
/4
MHz
MHz
bit
EXT
CPU
f
0
/4
CPU
PWM
Res
PWM resolution
16
PWM
148/171
ST72260G, ST72262G, ST72264G
13.11 COMMUNICATION INTERFACE CHARACTERISTICS
13.11.1 SPI - Serial Peripheral Interface
Refer to I/O port characteristics for more details on
the input/output alternate function characteristics
(SS, SCK, MOSI, MISO).
Subject to general operating conditions for V
,
DD
f
, and T unless otherwise specified.
OSC
A
Symbol
Parameter
Conditions
Min
/128
0.0625
Max
Unit
Master
Slave
f
f
f
/4
CPU
2
CPU
f
=8MHz
=8MHz
f
CPU
SCK
SPI clock frequency
MHz
1/t
/2
c(SCK)
CPU
0
f
4
CPU
t
t
r(SCK)
SPI clock rise and fall time
see I/O port pin description
f(SCK)
t
SS setup time
SS hold time
Slave
Slave
120
120
su(SS)
t
h(SS)
t
t
Master
Slave
100
90
w(SCKH)
SCK high and low time
Data input setup time
Data input hold time
w(SCKL)
t
Master
Slave
100
100
su(MI)
t
su(SI)
ns
t
Master
Slave
100
100
h(MI)
t
h(SI)
t
Data output access time
Data output disable time
Data output valid time
Data output hold time
Data output valid time
Data output hold time
Slave
Slave
0
120
240
120
a(SO)
t
dis(SO)
t
v(SO)
h(SO)
v(MO)
h(MO)
Slave (after enable edge)
t
0
t
0.25
0.25
Master (before capture edge)
t
CPU
t
Figure 101. SPI Slave Timing Diagram with CPHA=0 3)
SS
INPUT
t
t
su(SS)
c(SCK)
t
h(SS)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
t
t
w(SCKH)
w(SCKL)
t
t
t
t
dis(SO)
a(SO)
v(SO)
h(SO)
t
t
r(SCK)
f(SCK)
see
note 2
MISO
OUTPUT
INPUT
MSB OUT
see note 2
BIT6 OUT
LSB OUT
t
t
h(SI)
su(SI)
MSB IN
LSB IN
BIT1 IN
MOSI
Notes:
1. Data based on design simulation and/or characterisation results, not tested in production.
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has
its alternate function capability released. In this case, the pin status depends on the I/O port configuration.
3. Measurement points are done at CMOS levels: 0.3xV and 0.7xV
.
DD
DD
149/171
ST72260G, ST72262G, ST72264G
COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d)
Figure 102. SPI Slave Timing Diagram with CPHA=11)
SS
INPUT
t
t
su(SS)
c(SCK)
t
h(SS)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
t
w(SCKH)
t
t
dis(SO)
a(SO)
t
t
t
h(SO)
w(SCKL)
v(SO)
t
t
r(SCK)
f(SCK)
see
note 2
see
note 2
MISO
OUTPUT
MSB OUT
BIT6 OUT
HZ
LSB OUT
t
t
h(SI)
su(SI)
LSB IN
MSB IN
BIT1 IN
MOSI
INPUT
Figure 103. SPI Master Timing Diagram 1)
SS
INPUT
t
c(SCK)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
CPHA=1
CPOL=0
CPHA=1
CPOL=1
t
t
w(SCKH)
w(SCKL)
t
t
r(SCK)
f(SCK)
t
t
h(MI)
su(MI)
MISO
MOSI
INPUT
MSB IN
BIT6 IN
LSB IN
t
t
h(MO)
v(MO)
LSB OUT
MSB OUT
see note 2
BIT6 OUT
see note 2
OUTPUT
Notes:
1. Measurement points are done at CMOS levels: 0.3xV and 0.7xV
.
DD
DD
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has
its alternate function capability released. In this case, the pin status depends of the I/O port configuration.
150/171
ST72260G, ST72262G, ST72264G
COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d)
2
13.11.2 I C - Inter IC Control Interface
Refer to I/O port characteristics for more details on
the input/output alternate function characteristics
Subject to general operating conditions for V
,
DD
2
(SDAI and SCLI). The ST7 I C interface meets the
f
, and T unless otherwise specified.
OSC
A
2
requirements of the Standard I C communication
protocol described in the following table.
2
2
Standard mode I C
Fast mode I C
Symbol
Parameter
Unit
1)
1)
1)
1)
Min
Max
Min
Max
t
SCL clock low time
SCL clock high time
SDA setup time
4.7
4.0
1.3
0.6
100
w(SCLL)
µs
t
w(SCLH)
t
250
su(SDA)
3)
2)
3)
t
SDA data hold time
0
0
900
h(SDA)
t
t
r(SDA)
ns
SDA and SCL rise time
SDA and SCL fall time
1000
300
20+0.1C
300
300
b
b
r(SCL)
t
t
f(SDA)
20+0.1C
f(SCL)
t
START condition hold time
4.0
4.7
4.0
4.7
0.6
0.6
0.6
1.3
h(STA)
µs
t
Repeated START condition setup time
STOP condition setup time
su(STA)
su(STO)
t
ns
ms
pF
t
STOP to START condition time (bus free)
Capacitive load for each bus line
w(STO:STA)
C
400
400
b
2
Figure 104. Typical Application with I C Bus and Timing Diagram 4)
V
V
DD
DD
4.7kΩ
4.7kΩ
100Ω
100Ω
SDAI
SCLI
2
I C BUS
ST72XXX
REPEATED START
START
t
t
su(STA)
w(STO:STA)
START
SDA
t
t
r(SDA)
f(SDA)
STOP
t
t
h(SDA)
su(SDA)
SCL
t
t
t
t
t
su(STO)
t
h(STA)
w(SCKH)
w(SCKL)
r(SCK)
f(SCK)
Notes:
2
1. Data based on standard I C protocol requirement, not tested in production.
2. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined
region of the falling edge of SCL.
3. The maximum hold time of the START condition has only to be met if the interface does not stretch the low period of
SCL signal.
4. Measurement points are done at CMOS levels: 0.3xV and 0.7xV
.
DD
DD
151/171
ST72260G, ST72262G, ST72264G
13.12 10-BIT ADC CHARACTERISTICS
T = -40°C to 85°C, unless otherwise specified
A
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
MHz
V
1)
f
ADC clock frequency
0.4
4
ADC
V
Conversion voltage range
Internal sample and hold capacitor
V
V
DD
AIN
SS
C
6
pF
ADC
f
=4MHz
28
µs
ADC
t
Conversion time
CONV
112
1/f
ADC
R
C
External input impedance
see
kΩ
AIN
AIN
Figure
105 and
Figure
External capacitor on analog input
pF
Variation frequency of analog input
signal
f
Hz
AIN
2)3)4)
106
3)
4)
Figure 105. R
max. vs f
with C =0pF
Figure 106. Recommended C /R values
AIN AIN
AIN
ADC
AIN
45
40
35
30
25
20
15
10
5
1000
100
10
Cain 10 nF
Cain 22 nF
Cain 47 nF
4 MHz
2 MHz
1 MHz
1
0
0.1
0
10
30
70
0.01
0.1
1
10
CPARASITIC (pF)
fAIN(KHz)
Figure 107. Analog Input equivalent circuit
VDD
ST72XXX
VT
0.6V
RAIN
AINx
2kΩ(max)
10-Bit A/D
Conversion
VAIN
CAIN
VT
0.6V
IL
±1µA
CADC
6pF
Notes:
1. Data based on design simulation.
2. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10kΩ). Data
based on characterization results, not tested in production.
3. C
represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad ca-
PARASITIC
pacitance (3pF). A high C
value will downgrade conversion accuracy. To remedy this, f
should be reduced.
PARASITIC
ADC
4. This graph shows that depending on the input signal variation (f ), C
can be increased for stabilization time and
AIN
AIN
decreased to allow the use of a larger serial resistor (R
. It is valid for all f
frequencies ≤ 4MHz.
AIN)
ADC
152/171
ST72260G, ST72262G, ST72264G
ADC CHARACTERISTICS (Cont’d)
13.12.0.1 General PCB Design Guidelines
Analog signals paths should run over the analog
ground plane and be as short as possible. Isolate
analog signals from digital signals that may
switch while the analog inputs are being sampled
by the A/D converter. Do not toggle digital out-
puts on the same I/O port as the A/D input being
converted.
To obtain best results, some general design and
layout rules should be followed when designing
the application PCB to shield the noise-sensitive,
analog physical interface from noise-generating
CMOS logic signals.
– Properly place components and route the signal
traces on the PCB to shield the analog inputs.
ADC Accuracy with f
Symbol
=8 MHz, f
=4 MHz R < 10kΩ, V = 4.5V to 5.5V
ADC AIN DD
CPU
2)
Parameter
Conditions
Typ
4
Max
Unit
1)
|E |
Total unadjusted error
T
1)
E
E
Offset error
1
-2.5/+2.5
O
G
1)
Gain Error
1
-1.5/+3
LSB
1)
|E |
Differential linearity error
1.5
3
3
5
D
1)
|E |
Integral linearity error
L
Figure 108. ADC Accuracy Characteristics
Digital Result ADCDR
EG
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line
1023
V
V
1022
1021
DD SS
1024
1LSB
= -------------------------------
IDEAL
(2)
E =Total Unadjusted Error: maximum deviation
T
ET
between the actual and the ideal transfer curves.
(3)
7
6
5
4
3
2
1
E =Offset Error: deviation between the first actual
O
transition and the first ideal one.
(1)
E =Gain Error: deviation between the last ideal
G
transition and the last actual one.
EO
EL
E =Differential Linearity Error: maximum deviation
D
between actual steps and the ideal one.
E =Integral Linearity Error: maximum deviation
L
ED
between any actual transition and the end point
correlation line.
1 LSBIDEAL
V
(LSB
)
IDEAL
in
0
1
2
3
4
5
6
7
102110221023 1024
VDD
VSS
Notes:
1. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the analog input pins significantly
reduces the accuracy of the conversion being performed on another analog input.
For I =0.8mA, the typical leakage induced inside the die is 1.6µA and the effect on the ADC accuracy is a loss of 4 LSB
INJ-
for each 10KΩ increase of the external analog source impedance. It is recommended to add a Schottky diode (pin to
ground) to analog pins which may potentially inject negative current. Any positive injection current within the limits spec-
ified for I
and ΣI
in Section 13.8 does not affect the ADC accuracy.
INJ(PIN)
INJ(PIN)
2. Refer to “Typical values” on page 122 for more information on typical ADC accuracy values.
153/171
ST72260G, ST72262G, ST72264G
14 PACKAGE CHARACTERISTICS
14.1 PACKAGE MECHANICAL DATA
Figure 109. 32-Pin Plastic Dual In-Line Package, Shrink 400-mil Width
mm
inches
Dim.
Min Typ Max Min Typ Max
E
eC
A
3.56 3.76 5.08 0.140 0.148 0.200
A1 0.51
A2 3.05 3.56 4.57 0.120 0.140 0.180
0.36 0.46 0.58 0.014 0.018 0.023
b1 0.76 1.02 1.40 0.030 0.040 0.055
0.020
A2
A
L
b
A1
E1
C
eA
eB
C
D
E
0.20 0.25 0.36 0.008 0.010 0.014
27.43 28.45 1.080 1.100 1.120
9.91 10.41 11.05 0.390 0.410 0.435
b
b2
e
D
E1 7.62 8.89 9.40 0.300 0.350 0.370
e
1.78
0.070
0.400
eA
eB
eC
L
10.16
12.70
1.40
0.500
0.055
2.54 3.05 3.81 0.100 0.120 0.150
Number of Pins
N
32
Figure 110. 28-Pin Plastic Small Outline Package, 300-mil Width
mm
inches
Dim.
A
Min Typ Max Min Typ Max
D
h x 45×
2.35
2.65 0.093
0.30 0.004
0.51 0.013
0.32 0.009
18.10 0.697
7.60 0.291
0.104
0.012
0.020
0.013
0.713
0.299
L
A
A1 0.10
C
A1
B
C
D
E
e
0.33
0.23
a
e
B
17.70
7.40
1.27
0.050
H
h
α
10.00
0.25
0°
10.65 0.394
0.75 0.010
0.419
0.030
8°
E
H
8°
0°
L
0.40
1.27 0.016
0.050
Number of Pins
N
28
154/171
ST72260G, ST72262G, ST72264G
Figure 111. Low Profile Fine Pitch Ball Grid Array Package
mm
inches
Dim
A
Min Typ Max Min Typ Max
1.210
1.700 0.048
0.011
0.067
A1 0.270
A2
1.120
0.044
b
D
0.450 0.500 0.550 0.018 0.020 0.022
5.750 6.000 6.150 0.226 0.236 0.242
D1
E
4.000
5.750 6.000 6.150 0.226 0.236 0.242
4.000 0.157
0.157
E1
e
0.720 0.800 0.880 0.028 0.031 0.035
0.850 1.000 1.150 0.033 0.039 0.045
f
ddd
0.120
0.005
14.2 THERMAL CHARACTERISTICS
Symbol
Ratings
Value
Unit
Package thermal resistance (junction to ambient)
SDIP32
60
75
56
72
R
SO28
LFBGA 6x6 (on multilayer PCB)
LFBGA 6x6 (on single-layer PCB)
°C/W
thJA
1)
P
Power dissipation
Maximum junction temperature
500
150
mW
°C
D
2)
T
Jmax
Notes:
1. The power dissipation is obtained from the formula P =P +P
where P
is the chip internal power (I xV
)
D
INT
PORT
INT
DD DD
and P
is the port power dissipation determined by the user.
PORT
2. The average chip-junction temperature can be obtained from the formula T = T + P x RthJA.
J
A
D
155/171
ST72260G, ST72262G, ST72264G
14.3 SOLDERING AND GLUEABILITY INFORMATION
Recommended soldering information given only
as design guidelines in Figure 112 and Figure 113.
Recommended glue for SMD plastic packages
dedicated to molding compound with silicone:
■ Heraeus: PD945, PD955
■ Loctite: 3615, 3298
Figure 112. Recommended Wave Soldering Profile (with 37% Sn and 63% Pb)
250
COOLING PHASE
(ROOM TEMPERATURE)
5 sec
200
150
100
50
SOLDERING
PHASE
80°C
Temp. [°C]
PREHEATING
PHASE
Time [sec]
0
20
60
40
80
100
140
120
160
Figure 113. Recommended Reflow Soldering Oven Profile (MID JEDEC)
250
Tmax=235+/-5°C
for 25 sec
200
150
100
50
150 sec above 183°C
90 sec at 125°C
Temp. [°C]
ramp down natural
2°C/sec max
ramp up
2°C/sec for 50sec
Time [sec]
0
100
200
300
400
156/171
ST72260G, ST72262G, ST72264G
15 DEVICE CONFIGURATION AND ORDERING INFORMATION
Each device is available for production in user pro-
grammable versions (FLASH) as well as in factory
coded versions (ROM/FASTROM).
0: Hardware (watchdog always enabled)
1: Software (watchdog to be enabled by software)
OPT 5:4 = VD[1:0] Voltage detection selection
These option bits enable the voltage detection
block (LVD and AVD) with a selected threshold ot
the LVD and AVD.
ST7226x devices are ROM versions. ST72P26x
devices are Factory Advanced Service Technique
ROM (FASTROM) versions: they are factory-pro-
grammed XFlash devices.
Configuration
VD1 VD0
ST72F26x XFlash devices are shipped to custom-
ers with a default program memory content (FFh).
The option bytes are programmed to enable the in-
ternal RC oscillator. The ROM/FASTROM factory
coded parts contain the code supplied by the cus-
tomer. This implies that FLASH devices have to be
configured by the customer using the Option Bytes
while the ROM/FASTROM devices are factory-
configured.
1
1
0
0
1
0
1
0
LVD Off
Lowest Voltage Threshold ( 3.05V)
Medium Voltage Threshold ( 3.6V)
Highest Voltage Threshold ( 4.1V)
OPT 3:2 = SEC[1:0] Sector 0 size definition
These option bits indicate the size of sector 0 ac-
cording to the following table.
15.1 OPTION BYTES
Sector 0 Size
SEC1
SEC0
The two option bytes allow the hardware configu-
ration of the microcontroller to be selected.
The option bytes have no address in the memory
map and can be accessed only in programming
mode (for example using a standard ST7 program-
ming tool). The default content of the FLASH is
fixed to FFh.
0.5k
1k
2
0
0
1
1
0
1
0
1
4k
In masked ROM devices, the option bytes are
fixed in hardware by the ROM code (see option
list).
OPT 1 = FMP_R Read-out protection
This option indicates if the program memory is pro-
tected against piracy See “Memory Protection” on
page 16.. The read-out protection blocks access
to the program memory in any mode except user
mode and IAP mode. Erasing the option bytes
when the FMP_R option is selected will cause the
whole memory to be erased first, and the device
can be reprogrammed. Refer to Section 4.5 and
the ST7 Flash Programming Reference Manual for
more details.
USER OPTION BYTE 0
OPT 7 = WDG HALT Watchdog reset on HALT
This option bit determines if a RESET is generated
when entering HALT mode while the Watchdog is
active.
0: No Reset generation when entering Halt mode
1: Reset generation when entering Halt mode
0: Read-out protection off
1: Read-out protection on
OPT 6 = WDG SW Hardware or software watch-
dog
This option bit selects the watchdog type.
USER OPTION BYTE 0
USER OPTION BYTE 1
7
0
7
0
OSC OSC OSC OSC OSC
EXTIT CSS TYPE TYPE RNGE RNGE RNGE
PLL
WDG WDG
HALT SW
SEC SEC FMP FMP
VD1 VD0
1
0
R
W
OFF
1
0
2
1
0
Default
Value
1
1
1
1
1
1
0
0
1
1
1
0
1
1
1
1
157/171
ST72260G, ST72262G, ST72264G
DEVICE CONFIGURATION (Cont’d)
OPT 0 = FMP_W FLASH write protection
This option indicates if the FLASH program mem-
ory is write protected.
OPT 5:4 = OSCTYPE[1:0] Oscillator Type selec-
tion
These option bits select the Oscillator Type.
Warning: When this option is selected, the pro-
gram memory (and the option bit itself) can never
be erased or programmed again.
0: Write protection off
Clock Source
Resonator Oscillator
Reserved
OSCTYPE1 OSCTYPE0
0
0
1
1
0
1
0
1
1: Write protection on
Internal RC Oscillator
External Source
USER OPTION BYTE 1
OPT 7 = EXTIT Port C External Interrupt Configu-
ration.
This option bit allows the Port C external interrupt
mapping to be configured as ei0 or ei1.
OPT 3:1 = OSCRNGE[2:0] Oscillator Range se-
lection
These option bits select the oscillator range.
Table 26. External Interrupt Configuration
EXTIT
ei0
ei1
option
bit
OSC
RNGE2
OSC
RNGE1
OSC
RNGE0
Typ. Freq. Range
PB[7:0] Ports
PC[5:0] Ports
VLP 32~100kHz
1
0
0
0
0
x
0
0
1
1
x
0
1
0
1
PA[7:0] Ports
1
0
LP
1~2MHz
2~4MHz
4~8MHz
8~16MHz
PA[7:0] Ports
PC[5:0] Ports
PB[7:0] Ports
MP
MS
HS
OPT 6 = CSS Clock Security System on/off
This option bit enables or disables the clock secu-
rity system (CSS) which include the clock filter and
the backup safe oscillator.
OPT 0 = PLL PLL selection
0: CSS enabled
1: CSS disabled
This option bit selects the PLL which allows multi-
plication by two of the oscillator frequency. The
PLL must not be used with the internal RC oscilla-
tor. It is guaranteed only with a f
cy between 2 and 4MHz.
0: PLL x2 enabled
Caution: The Clock Security System is not guar-
anteed. The features described in Section 6.4.3 on
page 26 are subject to revision.
input frequen-
OSC
1: PLL x2 disabled
CAUTION: the PLL can be enabled only if the
“OSC RANGE” (OPT3:1) bits are configured to
“MP - 2~4MHz”. Otherwise, the device functionali-
ty is not guaranteed.
158/171
ST72260G, ST72262G, ST72264G
15.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE
Customer code is made up of the ROM/FAS-
TROM contents and the list of the selected options
(if any). The ROM/FASTROM contents are to be
sent on diskette, or by electronic means, with the
S19 hexadecimal file generated by the develop-
ment tool. All unused bytes must be set to FFh.
The selected options are communicated to
STMicroelectronics using the correctly completed
OPTION LIST appended.
Refer to application note AN1635 for information
on the counter listing returned by ST after code
has been transferred.
The STMicroelectronics Sales Organization will be
pleased to provide detailed information on con-
tractual points.
Table 27. Supported Part Numbers
Program Memory
(Bytes)
RAM
(Bytes)
Part Number
Temp. Range
Package
ST72F264G1B6
SDIP32
SO28
ST72F264G1M6
4K FLASH
8K FLASH
256
ST72F262G1B6
SDIP32
SO28
-40°C +85°C
0°C +70°C
ST72F262G1M6
ST72F264G2B6
SDIP32
SO28
ST72F264G2M6
ST72F264G2H1
256
256
256
LFBGA
SDIP32
SO28
ST72F262G2B6
ST72F262G2M6
ST72F262G1B6
SDIP32
SO28
-40°C +85°C
ST72F262G1M6
4K FLASH
ST72F260G1B6
SDIP32
SO28
ST72F260G1M6
ST72P264G2B6/xxx
ST72P264G2M6/xxx
ST72P264G2H1/xxx
ST72P262G2B6/xxx
ST72P262G2M6/xxx
ST72P262G1B6/xxx
ST72P262G1M6/xxx
ST72P260G1B6/xxx
ST72P260G1M6/xxx
ST72264G2B6/xxx
ST72264G2M6/xxx
ST72262G2B6/xxx
ST72262G2M6/xxx
ST72262G1B6/xxx
ST72262G1M6/xxx
ST72260G1B6/xxx
ST72260G1M6/xxx
SDIP32
SO28
-40°C +85°C
0°C +70°C
8K FASTROM
LFBGA
SDIP32
SO28
SDIP32
SO28
-40°C +85°C
4K FASTROM
8K ROM
256
256
256
SDIP32
SO28
SDIP32
SO28
SDIP32
SO28
-40°C +85°C
SDIP32
SO28
4K ROM
SDIP32
SO28
159/171
ST72260G, ST72262G, ST72264G
TRANSFER OF CUSTOMER CODE (Cont’d)
ST72264 ROM/FASTROM MICROCONTROLLER OPTION LIST
Customer
Address
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact
Phone No
Reference /ROM or FAST ROM Code*
ROM or FASTROM code is assigned by STMicroelectronics.
Code must be sent in .S19 format. .Hex extension cannot be processed.
Package/Memory:
SO28:
[ ] 8K (G2M)
[ ] 8K (G2B)
[ ] 8K (G2H)
[ ] 8K (as G2)
[ ] 4K (G1M)
[ ] 4K (G1B)
DIP32:
LFBGA6x6
Die Form:
[ ] 4K (as G1)
Conditioning:
SO package:
Die form:
[ ] Tape & Reel
[ ] Tape & Reel
[ ] Tube
[ ] Inked wafer
[ ] Sawn wafer on sticky foil
Special Marking [ ] No
[ ] Yes “ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _” ( DIP32 15 ch, S028 13 ch, LFBGA6x6 7 ch max.)”
Authorized characters are letters, digits ‘.’, ‘-’, ‘/’ and spaces only.
Temperature Range:
Packaged form:
[ ] 0°C to + 70°C
[ ] - 10°C to + 85°C (except LFBGA)
[ ] - 40°C to + 85°C (except LFBGA)
Die form:
Tested at 25°C only
Watchdog Selection:
Watchdog Reset on Halt:
LVD Reset
[ ] Software Activation
[ ] Hardware Activation
[ ] Reset
[ ] No Reset
[ ] Disabled
[ ] Enabled:
[ ] Highest threshold
[ ] Medium threshold
[ ] Lowest threshold
Sector 0 Size:
Readout Protection:
External Interrupt:
[ ] 0.5K
[ ] 1K
[ ] 2K
[ ] 4K
[ ] Disabled
[ ] Enabled
[ ] Port C mapped to ei0 interrupt vector
[ ] Port C mapped to ei1 interrupt vector
[ ] Disabled
[ ] Resonator:
Clock Security System:
Clock Source Selection:
[ ] Enabled
[ ] VLP: Very Low power resonator (32 to 100 kHz)
[ ] LP: Low power resonator (1 to 2 MHz)
[ ] MP: Medium power resonator (2 to 4 MHz)
[ ] MS: Medium speed resonator (4 to 8 MHz)
[ ] HS: High speed resonator (8 to 16 MHz)
1
[ ] Internal RC Network :
[ ] External Clock
[ ] Disabled
1
PLL :
[ ] Enabled
Comments : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply Operating Range in the application: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Notes:
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signature:
1
Use of the PLL with the internal RC oscillator is not supported.
Important note: Not all configurations are available. See Table 27 on page 159 for the list of supported part numbers.
160/171
ST72260G, ST72262G, ST72264G
15.3 DEVELOPMENT TOOLS
STMicroelectronics offers a range of hardware
and software development tools for the ST7 micro-
controller family. Full details of tools available for
the ST7 from third party manufacturers can be ob-
tain from the STMicroelectronics Internet site:
➟ http//www.stmcu.com.
Note: Before designing the board layout, it is rec-
ommended to check the overall dimensions of the
socket as they may be greater than the dimen-
sions of the device.
For footprint and other mechanical information
about these sockets and adapters, refer to the
manufacturer’s datasheet.
Third Party Tools
Tools from these manufacturers include C compli-
ers, emulators and gang programmers.
ST Emulators
The emulator is delivered with everything (probes,
TEB, adapters etc.) needed to start emulating the
devices. To configure the emulator to emulate dif-
ferent ST7 subfamily devices, the active probe for
the ST7 EMU3 can be changed and the ST7EMU3
probe is designed for easy interchange of TEBs
(Target Emulation Board). See Table 28 for more
details.
15.3.1
Socket
and
Emulator
Adapter
Information
For information on the type of socket that is sup-
plied with the emulator, refer to the suggested list
of sockets in Table 29 and Table 30.
Table 28. STMicroelectronics Development Tools
ST7 Programming
Supported Products
Evaluation Board
ST7 Emulator
ST7MDT10-EMU3
Active Probe & TEB
Board
ST7FOPTIONS-
EVAL
ST72F264,ST72F262,
ST72F260
1
2
ST7MDT10-TEB
ST7MDT10-EPB
Notes:
1. BGA adapter not available for ST7MDT10-EMU3.
2. ST7MDT10-EPB has no BGA socket, it can program BGA devices via ICC only.
161/171
ST72260G, ST72262G, ST72264G
15.3.2 PACKAGE/SOCKET FOOTPRINT PROPOSAL
Table 29. Suggested List of SDIP32 Socket Types
Same
Footprint
Package / Probe
Adaptor / Socket Reference
Socket Type
Textool
SDIP32
EMU PROBE
TEXTOOL
232-1291-00
X
Table 30. Suggested List of SO28 Socket Types
Same
Footprint
Package / Probe
Adaptor / Socket Reference
Socket Type
SO28
YAMAICHI
IC51-0282-334-1
Clamshell
EMU PROBE
Adapter from SO28 to SDIP32 footprint (delivered with emulator)
X
SMD to SDIP
Table 31. Suggested LFBGA Socket Type
Package
Socket Reference
LFBGA 6 X6
ENPLAS OTB-36(144)-0.8-04
162/171
ST72260G, ST72262G, ST72264G
15.4 ST7 APPLICATION NOTES
IDENTIFICATION
DESCRIPTION
EXAMPLE DRIVERS
AN 969
AN 970
AN 971
AN 972
AN 973
AN 974
AN 976
AN 979
AN 980
AN1017
AN1041
AN1042
AN1044
AN1045
AN1046
AN1047
AN1048
AN1078
AN1082
AN1083
AN1105
AN1129
SCI COMMUNICATION BETWEEN ST7 AND PC
SPI COMMUNICATION BETWEEN ST7 AND EEPROM
I²C COMMUNICATING BETWEEN ST7 AND M24CXX EEPROM
ST7 SOFTWARE SPI MASTER COMMUNICATION
SCI SOFTWARE COMMUNICATION WITH A PC USING ST72251 16-BIT TIMER
REAL TIME CLOCK WITH ST7 TIMER OUTPUT COMPARE
DRIVING A BUZZER THROUGH ST7 TIMER PWM FUNCTION
DRIVING AN ANALOG KEYBOARD WITH THE ST7 ADC
ST7 KEYPAD DECODING TECHNIQUES, IMPLEMENTING WAKE-UP ON KEYSTROKE
USING THE ST7 UNIVERSAL SERIAL BUS MICROCONTROLLER
USING ST7 PWM SIGNAL TO GENERATE ANALOG OUTPUT (SINUSOID)
ST7 ROUTINE FOR I²C SLAVE MODE MANAGEMENT
MULTIPLE INTERRUPT SOURCES MANAGEMENT FOR ST7 MCUS
ST7 S/W IMPLEMENTATION OF I²C BUS MASTER
UART EMULATION SOFTWARE
MANAGING RECEPTION ERRORS WITH THE ST7 SCI PERIPHERALS
ST7 SOFTWARE LCD DRIVER
PWM DUTY CYCLE SWITCH IMPLEMENTING TRUE 0% & 100% DUTY CYCLE
DESCRIPTION OF THE ST72141 MOTOR CONTROL PERIPHERAL REGISTERS
ST72141 BLDC MOTOR CONTROL SOFTWARE AND FLOWCHART EXAMPLE
ST7 PCAN PERIPHERAL DRIVER
PERMANENT MAGNET DC MOTOR DRIVE.
AN INTRODUCTION TO SENSORLESS BRUSHLESS DC MOTOR DRIVE APPLICATIONS
WITH THE ST72141
AN1130
AN1148
AN1149
AN1180
AN1276
AN1321
AN1325
AN1445
AN1475
AN1504
USING THE ST7263 FOR DESIGNING A USB MOUSE
HANDLING SUSPEND MODE ON A USB MOUSE
USING THE ST7263 KIT TO IMPLEMENT A USB GAME PAD
BLDC MOTOR START ROUTINE FOR THE ST72141 MICROCONTROLLER
USING THE ST72141 MOTOR CONTROL MCU IN SENSOR MODE
USING THE ST7 USB LOW-SPEED FIRMWARE V4.X
USING THE ST7 SPI TO EMULATE A 16-BIT SLAVE
DEVELOPING AN ST7265X MASS STORAGE APPLICATION
STARTING A PWM SIGNAL DIRECTLY AT HIGH LEVEL USING THE ST7 16-BIT TIMER
PRODUCT EVALUATION
AN 910
AN 990
AN1077
AN1086
AN1150
AN1151
AN1278
PERFORMANCE BENCHMARKING
ST7 BENEFITS VERSUS INDUSTRY STANDARD
OVERVIEW OF ENHANCED CAN CONTROLLERS FOR ST7 AND ST9 MCUS
U435 CAN-DO SOLUTIONS FOR CAR MULTIPLEXING
BENCHMARK ST72 VS PC16
PERFORMANCE COMPARISON BETWEEN ST72254 & PC16F876
LIN (LOCAL INTERCONNECT NETWORK) SOLUTIONS
PRODUCT MIGRATION
AN1131
AN1322
AN1365
MIGRATING APPLICATIONS FROM ST72511/311/214/124 TO ST72521/321/324
MIGRATING AN APPLICATION FROM ST7263 REV.B TO ST7263B
GUIDELINES FOR MIGRATING ST72C254 APPLICATION TO ST72F264
PRODUCT OPTIMIZATION
163/171
ST72260G, ST72262G, ST72264G
IDENTIFICATION
DESCRIPTION
AN 982
AN1014
AN1015
AN1040
AN1070
AN1324
AN1477
AN1502
AN1529
USING ST7 WITH CERAMIC RESONATOR
HOW TO MINIMIZE THE ST7 POWER CONSUMPTION
SOFTWARE TECHNIQUES FOR IMPROVING MICROCONTROLLER EMC PERFORMANCE
MONITORING THE VBUS SIGNAL FOR USB SELF-POWERED DEVICES
ST7 CHECKSUM SELF-CHECKING CAPABILITY
CALIBRATING THE RC OSCILLATOR OF THE ST7FLITE0 MCU USING THE MAINS
EMULATED DATA EEPROM WITH XFLASH MEMORY
EMULATED DATA EEPROM WITH ST7 HDFLASH MEMORY
EXTENDING THE CURRENT & VOLTAGE CAPABILITY ON THE ST7265 VDDF SUPPLY
ACCURATE TIMEBASE FOR LOW-COST ST7 APPLICATIONS WITH INTERNAL RC OSCIL-
LATOR
AN1530
PROGRAMMING AND TOOLS
AN 978
AN 983
AN 985
AN 986
AN 987
AN 988
AN 989
AN1039
AN1064
AN1071
AN1106
KEY FEATURES OF THE STVD7 ST7 VISUAL DEBUG PACKAGE
KEY FEATURES OF THE COSMIC ST7 C-COMPILER PACKAGE
EXECUTING CODE IN ST7 RAM
USING THE INDIRECT ADDRESSING MODE WITH ST7
ST7 SERIAL TEST CONTROLLER PROGRAMMING
STARTING WITH ST7 ASSEMBLY TOOL CHAIN
GETTING STARTED WITH THE ST7 HIWARE C TOOLCHAIN
ST7 MATH UTILITY ROUTINES
WRITING OPTIMIZED HIWARE C LANGUAGE FOR ST7
HALF DUPLEX USB-TO-SERIAL BRIDGE USING THE ST72611 USB MICROCONTROLLER
TRANSLATING ASSEMBLY CODE FROM HC05 TO ST7
PROGRAMMING ST7 FLASH MICROCONTROLLERS IN REMOTE ISP MODE (IN-SITU PRO-
GRAMMING)
AN1179
AN1446
AN1478
AN1527
AN1575
USING THE ST72521 EMULATOR TO DEBUG A ST72324 TARGET APPLICATION
PORTING AN ST7 PANTA PROJECT TO CODEWARRIOR IDE
DEVELOPING A USB SMARTCARD READER WITH ST7SCR
ON-BOARD PROGRAMMING METHODS FOR XFLASH AND HDFLASH ST7 MCUS
164/171
1
ST72260G, ST72262G, ST72264G
16 SUMMARY OF CHANGES
Description of the changes between the current release of the specification and the previous one.
Rev.
Main changes
Date
Added LFBGA package on page 1 and throughout document
Added RTC timer on page 1.
Removed External RC oscillator option on page 1 and throughout document
Added “can be reprogrammed” to “Memory Protection” on page 16 and “OPTION BYTES” on
page 157.
Added “freerunning” to description of counter in “WATCHDOG TIMER (WDG)” on page 48
Changed reset value of SCIBRR register in “Hardware Register Map” on page 11
Changed SLOW and SPEED bit table in ADC “Register Description” on page 114
1.6
April-03
Removed references to Temp. range -40 to +125°C and -40 to +105°C in“OPERATING CONDI-
TIONS” on page 124 and throughout section.
Changed Vtpor values in “Low Voltage Detector (LVD) Thresholds” on page 125
Changed EMS and EMI values in “EMC CHARACTERISTICS” on page 136
Changed option list and added mention of FASTROM to “DEVICE CONFIGURATION AND OR-
DERING INFORMATION” on page 157
Added “ERRATA SHEET” on page 166
Modified description of internal RC oscillator in Section 6.2 on page 21.
Added Caution about disconnecting OSC pins in Section 6.2 on page 21
1.7 Added note on GCAL to I2C Section 11.6 on page 99.
Added note on ADC data register in Table 2 on page 11
Updated Errata sheet
Aug-03
165/171
ERRATA SHEET
ST72264 LIMITATIONS AND CORRECTIONS
17 SILICON IDENTIFICATION
This document refers to ST72F264 devices and subsets (ST72F260, ST72F262).
They are identifiable:
■
On the device package, by the last letter of the Trace code marked on the device package
On the box, by the last 3 digits of the Internal Sales Type printed on the box label.
■
Table 32. Device Identification
Trace Code marked on device
Internal Sales Type on box label
72F264xxxx$U2
72F264xxxx$A2
Flash Devices: “xxxxxxxxxZ”
18 REFERENCE SPECIFICATION
Limitations in this document are with reference to the ST72264 Datasheet Revision 1.7 (Au-
gust 2003).
19 SILICON LIMITATIONS
This section lists the known limitations of the devices referenced in Table 32.
19.1 EXECUTION OF BTJX INSTRUCTION
When testing the address $FF with the "BTJT" or "BTJF" instructions, the CPU may perform
an incorrect operation when the relative jump is negative and performs an address page
change.
To avoid this issue, including when using a C compiler, it is recommended to never use ad-
dress $00FF as a variable (using the linker parameter for example).
19.2 I/O PORT B AND C CONFIGURATION
When using an external quartz crystal or ceramic resonator, the f
clock may be disturbed
OSC2
because the device goes into reserved mode controlled by Port B and C.
This happens with either one of the following configurations:
Rev. 2.3
August 2003
166/171
1
ERRATA SHEET
– PB1=0, PC2=1, PB3=0 while CSS and PLL options are both disabled and PC4 is toggling
– PB1=0, PC2=1, PB3=0, PC4=1 while CSS or PLL options are enabled
This is detailed in the following table:
CSS
PLL
PB1
PC2
PB3
PC4
Clock Disturbance
Max. 2 clock cycles lost at each rising or
falling edge of PC4
x
x
0
1
0
Toggling
x
ON
x
0
1
0
1
Max. 1 clock cycle lost out of every 16
ON
As a consequence, for cycle-accurate operations, these configurations are prohibited in either
input or output mode.
Workaround:
To avoid this occurring, it is recommended to connect one of these pins to GND (PC2 or PC4)
or V (PB1 or PB3).
DD
19.3 16-BIT TIMER PWM MODE
In PWM mode, the first PWM pulse is missed after writing the value FFFCh in the OC12R reg-
ister.
19.4 SPI MULTIMASTER MODE
Multi master mode is not supported.
19.5 MINIMUM OPERATING VOLTAGE
The minimum V voltage is 2.7V.
DD
19.6 CSS FUNCTION
The Clock Security System is not guaranteed. The features described in Section 6.4.3 are
subject to revision.
19.7 INTERNAL AND EXTERNAL RC OSCILLATOR WITH LVD
If the LVD is disabled, the internal or external RC oscillator clock source cannot be used.
In ICP mode, new flash devices must be programmed with an external clock connected to the
OSC1 pin or using a crystal or ceramic resonator. In the STVP7 programming tool software,
select the “OPTIONS DISABLED” mode.
19.8 EXTERNAL CLOCK WITH PLL
The PLL option is not supported for use with external clock source.
167/171
1
ERRATA SHEET
19.9 HALT MODE POWER CONSUMPTION WITH ADC ON
If the A/D converter is being used when Halt mode is entered, the power consumption in Halt
Mode may exceed the maximum specified in the datasheet.
Workaround
Switch off the ADC by software (ADON=0) before executing a HALT instruction.
19.10 ACTIVE HALT WAKE-UP BY EXTERNAL INTERRUPT
External interrupts are not able to wake-up the MCU from Active Halt mode. The MCU can
only exit from Active Halt mode by means of an MCC/RTC interrupt or a reset.
Workaround
Use WAIT mode if external interrupt capability is required in low power mode.
19.11 A/D CONVERTER ACCURACY FOR FIRST CONVERSION
When the ADC is enabled after being powered down (for example when waking up from
HALT, ACTIVE-HALT or setting the ADON bit in the ADCCSR register), the first conversion
(8-bit or 10-bit) accuracy does not meet the accuracy specified in the data sheet.
Workaround
In order to have the accuracy specified in the datasheet, the first conversion after a ADC
switch-on has to be ignored.
19.12 NEGATIVE INJECTION IMPACT ON ADC ACCURACY
Injecting a negative current on an analog input pins significantly reduces the accuracy of the
AD Converter. Whenever necessary, the negative injection should be prevented by the addi-
tion of a Schottky diode between the concerned I/Os and ground.
Injecting a negative current on digital input pins degrades ADC accuracy especially if per-
formed on a pin close to ADC channel in use.
19.13 ADC CONVERSION SPURIOUS RESULTS
Spurious conversions occur with a rate lower than 50 per million. Such conversions happen
when the measured voltage is just between 2 consecutive digital values.
Workaround
A software filter should be implemented to remove erratic conversion results whenever they
may cause unwanted consequences.
168/171
1
ERRATA SHEET
19.14 FUNCTIONAL EMS
Functional EMS (Electro Magnetic Susceptibility) levels do not reach the ST standards.
Special care should be taken when designing the PCB layout and firmware (refer to applica-
tion notes AN898, AN901 and AN1015) in sensitive applications (that use switches for in-
stance). For more information refer to application note AN1637.
20 DEVICE MARKING
Figure 114. Revision Marking on Box Label and Device Marking
TYPE xxxx
Internalxxx$xx
Trace Code
LAST 2 DIGITS AFTER $
IN INTERNAL SALES TYPE
ON BOX LABEL
INDICATE SILICON REV.
LAST LETTER OF TRACE CODE
ON DEVICE INDICATES
SILICON REV.
169/171
ERRATA SHEET
21 ERRATA SHEET REVISION HISTORY
Revision
Main Changes
Date
Modified Section 19.5 "MINIMUM OPERATING VOLTAGE" on page 167
Added “16-BIT TIMER PWM MODE” on page 167
Added “FUNCTIONAL EMS” on page 169
2.3
05/06/03
Removed External RC Oscillator section
2.4
08/07/03
Added “CSS Function not guaranteed” section
170/171
ERRATA SHEET
Notes:
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
2003 STMicroelectronics - All Rights Reserved.
Purchase of I2C Components by STMicroelectronics conveys a license under the Philips I2C Patent. Rights to use these components in an
I2C system is granted provided that the system conforms to the I2C Standard Specification as defined by Philips.
STMicroelectronics Group of Companies
Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan
Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A.
http://www.st.com
171/171
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