ST72F324J6T3/XXX [STMICROELECTRONICS]
IC,MICROCONTROLLER,8-BIT,ST72 CPU,CMOS,QFP,44PIN,PLASTIC;
| 型号： | ST72F324J6T3/XXX |
| 厂家： | 
ST |
| 描述： | IC,MICROCONTROLLER,8-BIT,ST72 CPU,CMOS,QFP,44PIN,PLASTIC 闪存 微控制器和处理器 外围集成电路 时钟 |
| 文件： | 总163页 (文件大小：1328K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ST72324
5V RANGE 8-BIT MCU WITH 8 TO 32K FLASH,
10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE
■ Memories
– 8 to 32K dual voltage High Density Flash (HD-
Flash) with read-out protection capability. In-
Application Programming and In-Circuit Pro-
gramming for HDFlash devices
TQFP32
7 x 7
– 384 to 1K bytes RAM
TQFP44
10 x 10
– HDFlash endurance: 100 cycles, data reten-
tion: 20 years at 55°C
■ Clock, Reset And Supply Management
– Enhanced low voltage supervisor (LVD) for
main supply with programmable reset thresh-
olds and auxiliary voltage detector (AVD) with
interrupt capability
– Clock sources: crystal/ceramic resonator os-
cillators, internal RC oscillator, clock security
system and bypass for external clock
SDIP32
400 mil
SDIP42
600 mil
– PLL for 2x frequency multiplication
– Four Power Saving Modes: Halt, Active-Halt,
Wait and Slow
■ Interrupt Management
■ 2 Communication Interfaces
– SPI synchronous serial interface
– SCI asynchronous serial interface
■ 1 Analog Peripheral (low current coupling)
– Nested interrupt controller
– 10 interrupt vectors plus TRAP and RESET
– 9/6 external interrupt lines (on 4 vectors)
■ Up to 32 I/O Ports
– 10-bit ADC with up to 12 robust input ports
– 32/24 multifunctional bidirectional I/O lines
– 22/17 alternate function lines
– 12/10 high sink outputs
■ Instruction Set
– 8-bit Data Manipulation
– 63 Basic Instructions
– 17 main Addressing Modes
– 8 x 8 Unsigned Multiply Instruction
■ 4 Timers
– Main Clock Controller with: Real time base,
Beep and Clock-out capabilities
– Configurable watchdog timer
– 16-bit Timer A with: 1 input capture, 1 output
compare, external clock input, PWM and
pulse generator modes
■ Development Tools
– Full hardware/software development package
– In-Circuit Testing capability
– 16-bit Timer B with: 2 input captures, 2 output
compares, PWM and pulse generator modes
Device Summary
Features
Program memory -
bytes
ST72F324(J/K)61
Flash 32K
ST72F324(J/K)41
Flash 16K
ST72F324(J/K)21
Flash 8K
RAM (stack) - bytes
Voltage Range
Temp. Range
1024 (256)
512 (256)
384 (256)
3.8V to 5.5V
up to -40°C to +125°C
Packages
SDIP42, TQFP44 10x10,SDIP32, TQFP32 7x7
1
For new designs in standard and industrial applications, use ST72F324B(J/K) order codes, refer to separate datasheet
Rev. 4
1/163
November 2005
1
Table of Contents
1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.3 STRUCTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.3.1 Read-out Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.4 ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.5 ICP (IN-CIRCUIT PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.6 IAP (IN-APPLICATION PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.7 RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.7.1 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.1 PHASE LOCKED LOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.2 MULTI-OSCILLATOR (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.3 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.3.2 Asynchronous External RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.3.3 External Power-On RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.3.4 Internal Low Voltage Detector (LVD) RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.3.5 Internal Watchdog RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.4 SYSTEM INTEGRITY MANAGEMENT (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.4.1 Low Voltage Detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.4.2 Auxiliary Voltage Detector (AVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.4.3 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.4.4 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.2 MASKING AND PROCESSING FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.3 INTERRUPTS AND LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.4 CONCURRENT & NESTED MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.5 INTERRUPT REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.6 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.6.1 I/O Port Interrupt Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.7 EXTERNAL INTERRUPT CONTROL REGISTER (EICR) . . . . . . . . . . . . . . . . . . . . . . . 38
8 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8.2 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8.3 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
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8.4 ACTIVE-HALT AND HALT MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.4.1 ACTIVE-HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.4.2 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9.2.1 Input Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9.2.2 Output Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9.2.3 Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
9.4 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
9.5 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
9.5.1 I/O Port Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
10 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
10.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
10.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
10.1.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
10.1.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
10.1.4 How to Program the Watchdog Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
10.1.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
10.1.6 Hardware Watchdog Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
10.1.7 Using Halt Mode with the WDG (WDGHALT option) . . . . . . . . . . . . . . . . . . . . . . . 54
10.1.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
10.1.9 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
10.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK AND BEEPER (MCC/RTC) . 56
10.2.1 Programmable CPU Clock Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
10.2.2 Clock-out Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
10.2.3 Real Time Clock Timer (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
10.2.4 Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
10.2.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
10.2.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
10.2.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
10.3 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
10.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
10.3.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
10.3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
10.3.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
10.3.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
10.3.6 Summary of Timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
10.3.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
10.4 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
10.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
10.4.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
10.4.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
10.4.4 Clock Phase and Clock Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
10.4.5 Error Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
10.4.6 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
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10.4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
10.4.8 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
10.5 SERIAL COMMUNICATIONS INTERFACE (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
10.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
10.5.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
10.5.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
10.5.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
10.5.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
10.5.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
10.5.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
10.6 10-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
10.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
10.6.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
10.6.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
10.6.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
10.6.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
10.6.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
11 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
11.1 CPU ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
11.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
11.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
11.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
11.1.4 Indexed (No Offset, Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
11.1.5 Indirect (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
11.1.6 Indirect Indexed (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
11.1.7 Relative mode (Direct, Indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
11.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
12 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
12.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
12.1.1 Minimum and Maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
12.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
12.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
12.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
12.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
12.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
12.2.1 Voltage Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
12.2.2 Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
12.2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
12.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
12.3.1 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
12.4 LVD/AVD CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
12.4.1 Operating Conditions with Low Voltage Detector (LVD) . . . . . . . . . . . . . . . . . . . . 119
12.4.2 Auxiliary Voltage Detector (AVD) Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
12.5 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
12.5.1 CURRENT CONSUMPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
12.5.2 Supply and Clock Managers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
12.5.3 On-Chip Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
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12.6 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
12.6.1 General Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
12.6.2 External Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
12.6.3 Crystal and Ceramic Resonator Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
12.6.4 RC Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
12.6.5 PLL Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
12.7 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
12.7.1 RAM and Hardware Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
12.7.2 FLASH Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
12.8 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
12.8.1 Functional EMS (Electro Magnetic Susceptibility) . . . . . . . . . . . . . . . . . . . . . . . . 130
12.8.2 Electro Magnetic Interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
12.8.3 Absolute Maximum Ratings (Electrical Sensitivity) . . . . . . . . . . . . . . . . . . . . . . . . 132
12.9 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
12.9.1 General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
12.9.2 Output Driving Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
12.10 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
12.10.1Asynchronous RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
12.10.2ICCSEL/VPP Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
12.11 TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
12.11.116-Bit Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
12.12 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 140
12.12.1SPI - Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
12.13 10-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
12.13.1Analog Power Supply and Reference Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
12.13.2General PCB Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
12.13.3ADC Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
13 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
13.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
13.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
13.3 SOLDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
14 ST72324 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . 150
14.1 FLASH OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
14.2 VERSION-SPECIFIC SALES CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
14.3 FLASH DEVICE ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
14.4 SILICON IDENTIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
14.5 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
14.5.1 Socket and Emulator Adapter Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
14.6 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
15 KNOWN LIMITATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
15.1 ALL DEVICES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
15.1.1 External RC option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
15.1.2 CSS Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
15.1.3 Safe Connection of OSC1/OSC2 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
15.1.4 Unexpected Reset Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
15.1.5 Clearing active interrupts outside interrupt routine . . . . . . . . . . . . . . . . . . . . . . . . 159
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15.1.6 16-bit Timer PWM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
15.1.7 SCI Wrong Break duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
15.2 FLASH DEVICES ONLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
15.2.1 Internal RC Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
16 IMPORTANT NOTES ON ST72F324B FLASH DEVICES: . . . . . . . . . . . . . . . . . . . . . . . . . . 161
16.1 RESET PIN LOGIC LEVELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
16.2 WAKE-UP FROM ACTIVE HALT MODE USING EXTERNAL INTERRUPTS . . . . . . . 161
16.3 PLL JITTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
16.4 ACTIVE HALT POWER CONSUMPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
16.5 TIMER A REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
17 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
To obtain the most recent version of this datasheet,
please check at www.st.com>products>technical literature>datasheet.
Please also pay special attention to the Section “KNOWN LIMITATIONS” on page 159.
163
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1
ST72324
tion set and are available with FLASH program
memory.
1 INTRODUCTION
The ST72F324 devices are members of the ST7
microcontroller family designed for the 5V operat-
ing range.
Under software control, all devices can be placed
in WAIT, SLOW, ACTIVE-HALT or HALT mode,
reducing power consumption when the application
is in idle or stand-by state.
– The 32-pin devices are designed for mid-range
applications
The enhanced instruction set and addressing
modes of the ST7 offer both power and flexibility to
software developers, enabling the design of highly
efficient and compact application code. In addition
to standard 8-bit data management, all ST7 micro-
controllers feature true bit manipulation, 8x8 un-
signed multiplication and indirect addressing
modes.
– The 42/44-pin devices target the same range of
applications requiring more than 24 I/O ports.
For a description of the differences between
ST72F324 and ST72F324B devices refer to Sec-
tion 14.3 on page 152
All devices are based on a common industry-
standard 8-bit core, featuring an enhanced instruc-
Figure 1. Device Block Diagram
8-BIT CORE
ALU
PROGRAM
MEMORY
(8K - 32K Bytes)
RESET
CONTROL
V
PP
RAM
(384 - 1024 Bytes)
V
V
SS
DD
LVD
WATCHDOG
OSC1
OSC2
OSC
MCC/RTC/BEEP
PA7:3
PORT A
(5 bits on J devices)
(4 bits on K devices)
PORT F
TIMER A
BEEP
PF7:6,4,2:0
(6 bits on J devices)
(5 bits on K devices)
PB4:0
PORT B
(5 bits on J devices)
(3 bits on K devices)
PORT E
PE1:0
(2 bits)
PORT C
SCI
PC7:0
TIMER B
(8 bits)
PORT D
PD5:0
(6 bits on J devices)
(2 bits on K devices)
SPI
10-BIT ADC
V
AREF
V
SSA
7/163
3
ST72324
2 PIN DESCRIPTION
Figure 2. 42-Pin SDIP and 44-Pin TQFP Package Pinouts
44 43 42 41 40 39 38 37 36 35 34
RDI / PE1
V
V
1
33
32
31
30
29
28
27
26
25
24
23
SS_1
DD_1
PB0
PB1
2
PA3 (HS)
3
ei0
ei2
ei3
PB2
PC7 / SS / AIN15
4
PB3
PC6 / SCK / ICCCLK
PC5 / MOSI / AIN14
PC4 / MISO / ICCDATA
PC3 (HS) / ICAP1_B
PC2 (HS) / ICAP2_B
PC1 / OCMP1_B / AIN13
PC0 / OCMP2_B / AIN12
5
(HS) PB4
AIN0 / PD0
AIN1 / PD1
AIN2 / PD2
AIN3 / PD3
AIN4 / PD4
6
7
8
9
ei1
10
11
12 13 14 15 16 17 18 19 20 21 22
(HS) PB4
AIN0 / PD0
PB3
1
ei3
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
PB2
PB1
PB0
2
ei2
AIN1 / PD1
AIN2 / PD2
AIN3 / PD3
AIN4 / PD4
AIN5 / PD5
3
4
PE1 / RDI
PE0 / TDO
5
6
V
_2
7
DD
V
OSC1
OSC2
8
AREF
V
9
SSA
MCO / AIN8 / PF0
BEEP / (HS) PF1
V
_2
SS
10
11
12
13
14
15
16
17
18
19
20
21
RESET
/ ICCSEL
ei1
(HS) PF2
V
PP
AIN10 / OCMP1_A / PF4
ICAP1_A / (HS) PF6
EXTCLK_A / (HS) PF7
AIN12 / OCMP2_B / PC0
AIN13 / OCMP1_B / PC1
ICAP2_B/ (HS) PC2
ICAP1_B / (HS) PC3
ICCDATA / MISO / PC4
AIN14 / MOSI / PC5
PA7 (HS)
PA6 (HS)
PA5 (HS)
PA4 (HS)
V
SS_1
V
DD_1
PA3 (HS)
ei0
PC7 / SS / AIN15
PC6 / SCK / ICCCLK
(HS) 20mA high sink capability
eix associated external interrupt vector
8/163
ST72324
PIN DESCRIPTION (Cont’d)
Figure 3. 32-Pin SDIP Package Pinout
PB3
PB0
(HS) PB4
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
ei3
ei1
ei2
AIN0 / PD0
AIN1 / PD1
2
PE1 / RDI
PE0 / TDO
3
V
4
AREF
V
_2
V
5
DD
SSA
OSC1
OSC2
MCO / AIN8 / PF0
BEEP / (HS) PF1
6
7
OCMP1_A / AIN10 / PF4
V
_2
8
SS
ICAP1_A / (HS) PF6
EXTCLK_A / (HS) PF7
AIN12 / OCMP2_B / PC0
RESET
/ ICCSEL
9
V
10
11
12
13
14
15
16
PP
PA7 (HS)
AIN13 / OCMP1_B / PC1
ICAP2_B / (HS) PC2
ICAP1_B / (HS) PC3
ICCDATA/ MISO / PC4
AIN14 / MOSI / PC5
PA6 (HS)
PA4 (HS)
PA3 (HS)
ei0
PC7 / SS / AIN15
PC6 / SCK / ICCCLK
(HS) 20mA high sink capability
eix associated external interrupt vector
Figure 4. 32-Pin TQFP 7x7 Package Pinout
32 31 30 29 28 27 26 25
V
24
23
22
21
20
19
18
17
OSC1
OSC2
1
2
3
4
5
6
7
8
AREF
ei3 ei2
V
SSA
MCO / AIN8 / PF0
BEEP / (HS) PF1
V
_2
SS
ei1
RESET
/ ICCSEL
OCMP1_A / AIN10 / PF4
ICAP1_A / (HS) PF6
V
PP
PA7 (HS)
PA6 (HS)
PA4 (HS)
EXTCLK_A / (HS) PF7
AIN12 / OCMP2_B / PC0
ei0
9 10 11 12 13 14 15 16
(HS) 20mA high sink capability
eix associated external interrupt vector
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1
ST72324
PIN DESCRIPTION (Cont’d)
For external pin connection guidelines, refer to See “ELECTRICAL CHARACTERISTICS” on page 116.
Legend / Abbreviations for Table 1:
Type:
I = input, O = output, S = supply
A = Dedicated analog input
Input level:
In/Output level: C = CMOS 0.3V /0.7V
DD
DD
DD
C = CMOS 0.3V /0.7V with input trigger
T
DD
Output level:
HS = 20mA high sink (on N-buffer only)
Port and control configuration:
1)
– Input:
float = floating, wpu = weak pull-up, int = interrupt , ana = analog ports
2)
– Output:
OD = open drain , PP = push-pull
Refer to “I/O PORTS” on page 45 for more details on the software configuration of the I/O ports.
The RESET configuration of each pin is shown in bold. This configuration is valid as long as the device is
in reset state.
Table 1. Device Pin Description
Pin n°
Level
Port
Main
function
(after
Input
Output
Pin Name
Alternate Function
reset)
6
7
1
2
3
4
5
6
7
8
9
30
31
32
1
2
3
PB4 (HS)
I/O C
I/O C
I/O C
I/O C
I/O C
I/O C
I/O C
S
HS
X
X
X
X
X
X
X
ei3
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Port B4
T
T
T
T
T
T
T
PD0/AIN0
PD1/AIN1
PD2/AIN2
PD3/AIN3
PD4/AIN4
PD5/AIN5
X
X
X
X
X
X
Port D0 ADC Analog Input 0
Port D1 ADC Analog Input 1
Port D2 ADC Analog Input 2
Port D3 ADC Analog Input 3
Port D4 ADC Analog Input 4
Port D5 ADC Analog Input 5
Analog Reference Voltage for ADC
Analog Ground Voltage
8
X
9
X
10
11
12
13
14
X
X
X
1
2
4
5
V
V
AREF
SSA
S
Main clock
out (f
ADC Analog
Input 8
15 10
3
4
6
7
PF0/MCO/AIN8
I/O C
X
ei1
ei1
X
X
X
Port F0
T
)
CPU
16 11
17 12
PF1 (HS)/BEEP
PF2 (HS)
I/O C
I/O C
HS
HS
X
X
X
X
X
X
Port F1 Beep signal output
Port F2
T
ei1
T
Timer A Out-
Port F4 put Com-
pare 1
PF4/OCMP1_A/
AIN10
ADC Analog
Input 10
18 13
5
8
I/O C
X
X
X
X
X
T
19 14
20 15
6
7
9
PF6 (HS)/ICAP1_A I/O C
HS
HS
X
X
X
X
X
X
X
X
Port F6 Timer A Input Capture 1
T
T
PF7 (HS)/
I/O C
Timer A External Clock
10
Port F7
Source
EXTCLK_A
21
22
V
V
S
S
Digital Main Supply Voltage
Digital Ground Voltage
DD_0
SS_0
Timer B Out-
ADC Analog
PC0/OCMP2_B/
AIN12
23 16
8
11
I/O C
X
X
X
X
X
Port C0 put Com-
Input 12
T
pare 2
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1
ST72324
Pin n°
Level
Port
Main
function
(after
Input
Output
Pin Name
Alternate Function
reset)
Timer B Out-
Port C1 put Com-
pare 1
PC1/OCMP1_B/
AIN13
ADC Analog
Input 13
24 17
9
12
I/O C
X
X
X
X
X
T
25 18 10 13 PC2 (HS)/ICAP2_B I/O C
26 19 11 14 PC3 (HS)/ICAP1_B I/O C
HS
HS
X
X
X
X
X
X
X
X
Port C2 Timer B Input Capture 2
Port C3 Timer B Input Capture 1
T
T
SPI Master
ICC Data In-
Port C4 In / Slave
put
PC4/MISO/ICCDA-
TA
27 20 12 15
I/O C
X
X
X
X
T
Out Data
SPI Master
ADC Analog
28 21 13 16 PC5/MOSI/AIN14
29 22 14 17 PC6/SCK/ICCCLK
I/O C
I/O C
I/O C
X
X
X
X
X
X
X
X
X
X
X
Port C5 Out / Slave
Input 14
T
In Data
SPI Serial
Clock
ICC Clock
Output
Port C6
T
SPI Slave
Port C7 Select (ac-
tive low)
ADC Analog
Input 15
30 23 15 18 PC7/SS/AIN15
31 24 16 19 PA3 (HS)
X
X
X
X
X
X
T
I/O C
S
HS
ei0
Port A3
T
32 25
33 26
V
V
Digital Main Supply Voltage
Digital Ground Voltage
Port A4
DD_1
SS_1
S
34 27 17 20 PA4 (HS)
35 28 PA5 (HS)
I/O C
I/O C
I/O C
I/O C
HS
HS
HS
HS
X
X
X
X
X
X
X
X
T
T
X
X
T
T
T
T
Port A5
1)
36 29 18 21 PA6 (HS)
37 30 19 22 PA7 (HS)
Port A6
1)
Port A7
Must be tied low. In the flash pro-
gramming mode, this pin acts as the
38 31 20 23 V /ICCSEL
I
PP
programming voltage input V . See
PP
Section 12.10.2 for more details.
Top priority non maskable interrupt.
Digital Ground Voltage
39 32 21 24 RESET
I/O C
T
40 33 22 25 V
S
SS_2
41 34 23 26 OSC2
O
Resonator oscillator inverter output
External clock input or Resonator os-
cillator inverter input
42 35 24 27 OSC1
I
43 36 25 28 V
S
Digital Main Supply Voltage
DD_2
44 37 26 29 PE0/TDO
I/O C
I/O C
X
X
X
X
X
X
X
X
Port E0 SCI Transmit Data Out
Port E1 SCI Receive Data In
T
T
1
38 27 30 PE1/RDI
Caution: Negative current
2
39 28 31 PB0
I/O C
X
ei2
X
X
Port B0 injection not allowed on this
T
5)
pin
3
4
5
40
41
PB1
PB2
I/O C
I/O C
I/O C
X
X
X
ei2
ei2
X
X
X
X
X
X
Port B1
Port B2
Port B3
T
T
T
42 29 32 PB3
ei2
Notes:
1. In the interrupt input column, “eiX” defines the associated external interrupt vector. If the weak pull-up
11/163
1
ST72324
column (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input,
else the configuration is floating interrupt input.
2. In the open drain output column, “T” defines a true open drain I/O (P-Buffer and protection diode to V
DD
are not implemented). See See “I/O PORTS” on page 45. and Section 12.9 I/O PORT PIN CHARACTER-
ISTICS for more details.
3. OSC1 and OSC2 pins connect a crystal/ceramic resonator, or an external source to the on-chip oscil-
lator; see Section 1 INTRODUCTION and Section 12.6 CLOCK AND TIMING CHARACTERISTICS for
more details.
4. On the chip, each I/O port has 8 pads. Pads that are not bonded to external pins are in input pull-up con-
figuration after reset. The configuration of these pads must be kept at reset state to avoid added current
consumption.
5. For details refer to Section 12.9.1 on page 133
12/163
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ST72324
3 REGISTER & MEMORY MAP
As shown in Figure 5, the MCU is capable of ad-
dressing 64K bytes of memories and I/O registers.
The highest address bytes contain the user reset
and interrupt vectors.
The available memory locations consist of 128
bytes of register locations, up to 1024 bytes of
RAM and up to 32 Kbytes of user program memo-
ry. The RAM space includes up to 256 bytes for
the stack from 0100h to 01FFh.
IMPORTANT: Memory locations marked as “Re-
served” must never be accessed. Accessing a re-
served area can have unpredictable effects on the
device.
Figure 5. Memory Map
0000h
0080h
HW Registers
(see Table 2)
Short Addressing
RAM (zero page)
007Fh
0080h
00FFh
0100h
RAM
(1024,
512 or 384 Bytes)
256 Bytes Stack
01FFh
0200h
047Fh
0480h
16-bit Addressing
RAM
Reserved
027Fh
or 047Fh
7FFFh
8000h
8000h
Program Memory
(32K, 16K or 8K)
32 KBytes
C000h
16 KBytes
FFDFh
FFE0h
E000h
Interrupt & Reset Vectors
(see Table 8)
8 Kbytes
FFFFh
FFFFh
13/163
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ST72324
Table 2. Hardware Register Map
Register
Label
Reset
Status
Address
Block
Register Name
Remarks
1)
0000h
0001h
0002h
PADR
PADDR
PAOR
Port A Data Register
Port A Data Direction Register
Port A Option Register
00h
R/W
R/W
R/W
2)
Port A
Port B
00h
00h
1)
0003h
0004h
0005h
PBDR
PBDDR
PBOR
Port B Data Register
Port B Data Direction Register
Port B Option Register
00h
R/W
R/W
R/W
2)
00h
00h
1)
0006h
0007h
0008h
PCDR
PCDDR
PCOR
Port C Data Register
Port C Data Direction Register
Port C Option Register
00h
R/W
R/W
R/W
Port C
00h
00h
1)
0009h
000Ah
000Bh
PDADR
PDDDR
PDOR
Port D Data Register
Port D Data Direction Register
Port D Option Register
00h
R/W
R/W
R/W
2)
Port D
Port E
Port F
00h
00h
1)
000Ch
000Dh
000Eh
PEDR
PEDDR
PEOR
Port E Data Register
Port E Data Direction Register
Port E Option Register
00h
R/W
R/W
R/W
2)
2)
2)
2)
00h
00h
1)
000Fh
0010h
0011h
PFDR
PFDDR
PFOR
Port F Data Register
Port F Data Direction Register
Port F Option Register
00h
R/W
R/W
R/W
00h
00h
0012h
to
Reserved Area (15 Bytes)
0020h
0021h
0022h
0023h
SPIDR
SPICR
SPICSR
SPI Data I/O Register
SPI Control Register
SPI Control/Status Register
xxh
0xh
00h
R/W
R/W
R/W
SPI
ITC
0024h
0025h
0026h
0027h
ISPR0
ISPR1
ISPR2
ISPR3
Interrupt Software Priority Register 0
Interrupt Software Priority Register 1
Interrupt Software Priority Register 2
Interrupt Software Priority Register 3
FFh
FFh
FFh
FFh
R/W
R/W
R/W
R/W
0028h
0029h
002Ah
002Bh
EICR
External Interrupt Control Register
Flash Control/Status Register
Watchdog Control Register
Reserved Area (1 Byte)
00h
00h
7Fh
R/W
R/W
R/W
FLASH
FCSR
WATCHDOG
WDGCR
002Ch
002Dh
MCCSR
MCCBCR
Main Clock Control / Status Register
Main Clock Controller: Beep Control Register
00h
00h
R/W
R/W
MCC
002Eh
to
Reserved Area (3 Bytes)
0030h
14/163
1
ST72324
Register
Label
Reset
Status
Address
Block
Register Name
Remarks
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
TACR2
TACR1
TACSR
TAIC1HR
TAIC1LR
TAOC1HR
TAOC1LR
TACHR
Timer A Control Register 2
Timer A Control Register 1
Timer A Control/Status Register
Timer A Input Capture 1 High Register
Timer A Input Capture 1 Low Register
Timer A Output Compare 1 High Register
Timer A Output Compare 1 Low Register
Timer A Counter High Register
Timer A Counter Low Register
Timer A Alternate Counter High Register
Timer A Alternate Counter Low Register
Timer A Input Capture 2 High Register
Timer A Input Capture 2 Low Register
00h
00h
R/W
R/W
3)4)
xxxx x0xxb R/W
xxh
xxh
80h
00h
FFh
FCh
FFh
FCh
xxh
xxh
80h
00h
Read Only
Read Only
R/W
R/W
TIMER A
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
R/W
TACLR
TAACHR
TAACLR
TAIC2HR
TAIC2LR
TAOC2HR
TAOC2LR
3)
3)
4)
Timer A Output Compare 2 High Register
4)
Timer A Output Compare 2 Low Register
Reserved Area (1 Byte)
R/W
0040h
0041h
0042h
0043h
0044h
0045h
0046h
0047h
0048h
0049h
004Ah
004Bh
004Ch
004Dh
004Eh
004Fh
TBCR2
TBCR1
TBCSR
TBIC1HR
TBIC1LR
TBOC1HR
TBOC1LR
TBCHR
Timer B Control Register 2
Timer B Control Register 1
Timer B Control/Status Register
Timer B Input Capture 1 High Register
Timer B Input Capture 1 Low Register
Timer B Output Compare 1 High Register
Timer B Output Compare 1 Low Register
Timer B Counter High Register
00h
00h
R/W
R/W
xxxx x0xxb R/W
xxh
xxh
80h
00h
FFh
FCh
FFh
FCh
xxh
xxh
80h
00h
Read Only
Read Only
R/W
R/W
TIMER B
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
R/W
TBCLR
Timer B Counter Low Register
TBACHR
TBACLR
TBIC2HR
TBIC2LR
TBOC2HR
TBOC2LR
Timer B Alternate Counter High Register
Timer B Alternate Counter Low Register
Timer B Input Capture 2 High Register
Timer B Input Capture 2 Low Register
Timer B Output Compare 2 High Register
Timer B Output Compare 2 Low Register
R/W
0050h
0051h
0052h
0053h
0054h
0055h
0056h
0057h
SCISR
SCIDR
SCIBRR
SCICR1
SCICR2
SCIERPR
SCI Status Register
SCI Data Register
SCI Baud Rate Register
SCI Control Register 1
SCI Control Register 2
SCI Extended Receive Prescaler Register
Reserved area
SCI Extended Transmit Prescaler Register
C0h
xxh
00h
Read Only
R/W
R/W
x000 0000h R/W
SCI
00h
00h
---
R/W
R/W
SCIETPR
00h
R/W
0058h
to
Reserved Area (24 Bytes)
006Fh
0070h
0071h
0072h
ADCCSR
ADCDRH
ADCDRL
Control/Status Register
Data High Register
Data Low Register
00h
00h
00h
R/W
Read Only
Read Only
ADC
0073h
007Fh
Reserved Area (13 Bytes)
15/163
1
ST72324
Legend: x=undefined, R/W=read/write
Notes:
1. The contents of the I/O port DR registers are readable only in output configuration. In input configura-
tion, the values of the I/O pins are returned instead of the DR register contents.
2. The bits associated with unavailable pins must always keep their reset value.
3. The Timer A Input Capture 2 pin is not available (not bonded).
– In Flash devices:
The TAIC2HR and TAIC2LR registers are not present. Bit 5 of the TACSR register (ICF2) is forced
by hardware to 0. Consequently, the corresponding interrupt cannot be used.
4. The Timer A Output Compare 2 pin is not available (not bonded).
– The TAOC2HR and TAOC2LR Registers are write only, reading them will return undefined values.
Bit 4 of the TACSR register (OCF2) is forced by hardware to 0. Consequently, the corresponding in-
terrupt cannot be used.
Caution: The TAIC2HR and TAIC2LR registers and the ICF2 and OCF2 flags are not present in Flash de-
vices but are present in the emulator. For compatibility with the emulator, it is recommended to perform a
dummy access (read or write) to the TAIC2LR and TAOC2LR registers to clear the interrupt flags.
16/163
1
ST72324
4 FLASH PROGRAM MEMORY
4.1 Introduction
Depending on the overall Flash memory size in the
microcontroller device, there are up to three user
sectors (see Table 3). Each of these sectors can
be erased independently to avoid unnecessary
erasing of the whole Flash memory when only a
partial erasing is required.
The ST7 dual voltage High Density Flash
(HDFlash) is a non-volatile memory that can be
electrically erased as a single block or by individu-
al sectors and programmed on a Byte-by-Byte ba-
sis using an external V supply.
PP
The first two sectors have a fixed size of 4 Kbytes
(see Figure 6). They are mapped in the upper part
of the ST7 addressing space so the reset and in-
terrupt vectors are located in Sector 0 (F000h-
FFFFh).
The HDFlash devices can be programmed and
erased off-board (plugged in a programming tool)
or on-board using ICP (In-Circuit Programming) or
IAP (In-Application Programming).
The array matrix organisation allows each sector
to be erased and reprogrammed without affecting
other sectors.
Table 3. Sectors available in Flash devices
Flash Size (bytes)
Available Sectors
4K
8K
Sector 0
Sectors 0,1
Sectors 0,1, 2
4.2 Main Features
■ Three Flash programming modes:
> 8K
– Insertion in a programming tool. In this mode,
all sectors including option bytes can be pro-
grammed or erased.
4.3.1 Read-out Protection
– ICP (In-Circuit Programming). In this mode, all
sectors including option bytes can be pro-
grammed or erased without removing the de-
vice from the application board.
– IAP (In-Application Programming) In this
mode, all sectors except Sector 0, can be pro-
grammed or erased without removing the de-
vice from the application board and while the
application is running.
Read-out protection, when selected, provides a
protection against Program Memory content ex-
traction and against write access to Flash memo-
ry. Even if no protection can be considered as to-
tally unbreakable, the feature provides a very high
level of protection for a general purpose microcon-
troller.
In flash devices, this protection is removed by re-
programming the option. In this case, the entire
program memory is first automatically erased.
■ ICT (In-Circuit Testing) for downloading and
executing user application test patterns in RAM
■ Read-out protection
Read-out protection selection depends on the de-
vice type:
■ Register Access Security System (RASS) to
prevent accidental programming or erasing
– In Flash devices it is enabled and removed
through the FMP_R bit in the option byte.
4.3 Structure
– In ROM devices it is enabled by mask option
specified in the Option List.
The Flash memory is organised in sectors and can
be used for both code and data storage.
Figure 6. Memory Map and Sector Address
4K
8K
10K
16K
24K
32K
48K
60K
FLASH
MEMORY SIZE
1000h
3FFFh
7FFFh
9FFFh
BFFFh
D7FFh
DFFFh
EFFFh
FFFFh
SECTOR 2
52 Kbytes
2 Kbytes 8 Kbytes 16 Kbytes 24 Kbytes 40 Kbytes
4 Kbytes
4 Kbytes
SECTOR 1
SECTOR 0
17/163
1
ST72324
FLASH PROGRAM MEMORY (Cont’d)
4.4 ICC Interface
– ICCCLK: ICC output serial clock pin
– ICCDATA: ICC input/output serial data pin
ICC needs a minimum of 4 and up to 6 pins to be
connected to the programming tool (see Figure 7).
These pins are:
– ICCSEL/V : programming voltage
PP
– OSC1(or OSCIN): main clock input for exter-
nal source (optional)
– RESET: device reset
– V : application board power supply (option-
DD
– V : device power supply ground
al, see Figure 7, Note 3)
SS
Figure 7. Typical ICC Interface
PROGRAMMING TOOL
ICC CONNECTOR
ICC Cable
APPLICATION BOARD
ICC CONNECTOR
(See Note 3)
OPTIONAL
HE10 CONNECTOR TYPE
IN SOME CASES
(See Note 4)
9
7
5
6
3
1
2
10
8
4
APPLICATION
RESET SOURCE
See Note 2
10kΩ
APPLICATION
POWER SUPPLY
C
C
L2
L1
See Note 1
APPLICATION
I/O
ST7
Notes:
1. If the ICCCLK or ICCDATA pins are only used
as outputs in the application, no signal isolation is
necessary. As soon as the Programming Tool is
plugged to the board, even if an ICC session is not
in progress, the ICCCLK and ICCDATA pins are
not available for the application. If they are used as
inputs by the application, isolation such as a serial
resistor has to implemented in case another de-
vice forces the signal. Refer to the Programming
Tool documentation for recommended resistor val-
ues.
sistor>1K, no additional components are needed.
In all cases the user must ensure that no external
reset is generated by the application during the
ICC session.
3. The use of Pin 7 of the ICC connector depends
on the Programming Tool architecture. This pin
must be connected when using most ST Program-
ming Tools (it is used to monitor the application
power supply). Please refer to the Programming
Tool manual.
4. Pin 9 has to be connected to the OSC1 or OS-
CIN pin of the ST7 when the clock is not available
in the application or if the selected clock option is
not programmed in the option byte. ST7 devices
with multi-oscillator capability need to have OSC2
grounded in this case.
2. During the ICC session, the programming tool
must control the RESET pin. This can lead to con-
flicts between the programming tool and the appli-
cation reset circuit if it drives more than 5mA at
high level (push pull output or pull-up resistor<1K).
A schottky diode can be used to isolate the appli-
cation RESET circuit in this case. When using a
classical RC network with R>1K or a reset man-
agement IC with open drain output and pull-up re-
18/163
1
ST72324
FLASH PROGRAM MEMORY (Cont’d)
4.5 ICP (In-Circuit Programming)
possible to download code from the SPI, SCI, USB
or CAN interface and program it in the Flash. IAP
mode can be used to program any of the Flash
sectors except Sector 0, which is write/erase pro-
tected to allow recovery in case errors occur dur-
ing the programming operation.
To perform ICP the microcontroller must be
switched to ICC (In-Circuit Communication) mode
by an external controller or programming tool.
Depending on the ICP code downloaded in RAM,
Flash memory programming can be fully custom-
ized (number of bytes to program, program loca-
tions, or selection serial communication interface
for downloading).
4.7 Related Documentation
For details on Flash programming and ICC proto-
col, refer to the ST7 Flash Programming Refer-
ence Manual and to the ST7 ICC Protocol Refer-
ence Manual.
When using an STMicroelectronics or third-party
programming tool that supports ICP and the spe-
cific microcontroller device, the user needs only to
implement the ICP hardware interface on the ap-
plication board (see Figure 7). For more details on
the pin locations, refer to the device pinout de-
scription.
4.7.1 Register Description
FLASH CONTROL/STATUS REGISTER (FCSR)
Read/Write
Reset Value: 0000 0000 (00h)
4.6 IAP (In-Application Programming)
7
0
0
0
This mode uses a BootLoader program previously
stored in Sector 0 by the user (in ICP mode or by
plugging the device in a programming tool).
0
0
0
0
0
0
This mode is fully controlled by user software. This
allows it to be adapted to the user application, (us-
er-defined strategy for entering programming
mode, choice of communications protocol used to
fetch the data to be stored, etc.). For example, it is
This register is reserved for use by Programming
Tool software. It controls the Flash programming
and erasing operations.
Table 4. Flash Control/Status Register Address and Reset Value
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
FCSR
Reset Value
0029h
0
0
0
0
0
0
0
0
19/163
1
ST72324
5 CENTRAL PROCESSING UNIT
5.1 INTRODUCTION
5.3 CPU REGISTERS
This CPU has a full 8-bit architecture and contains
six internal registers allowing efficient 8-bit data
manipulation.
The 6 CPU registers shown in Figure 8 are not
present in the memory mapping and are accessed
by specific instructions.
Accumulator (A)
5.2 MAIN FEATURES
The Accumulator is an 8-bit general purpose reg-
ister used to hold operands and the results of the
arithmetic and logic calculations and to manipulate
data.
■ Enable executing 63 basic instructions
■ Fast 8-bit by 8-bit multiply
■ 17 main addressing modes (with indirect
Index Registers (X and Y)
addressing mode)
These 8-bit registers are used to create effective
addresses or as temporary storage areas for data
manipulation. (The Cross-Assembler generates a
precede instruction (PRE) to indicate that the fol-
lowing instruction refers to the Y register.)
■ Two 8-bit index registers
■ 16-bit stack pointer
■ Low power HALT and WAIT modes
■ Priority maskable hardware interrupts
■ Non-maskable software/hardware interrupts
The Y register is not affected by the interrupt auto-
matic procedures.
Program Counter (PC)
The program counter is a 16-bit register containing
the address of the next instruction to be executed
by the CPU. It is made of two 8-bit registers PCL
(Program Counter Low which is the LSB) and PCH
(Program Counter High which is the MSB).
Figure 8. CPU Registers
7
0
ACCUMULATOR
RESET VALUE = XXh
7
0
0
X INDEX REGISTER
Y INDEX REGISTER
RESET VALUE = XXh
7
RESET VALUE = XXh
PCL
PCH
7
8
15
0
PROGRAM COUNTER
RESET VALUE = RESET VECTOR @ FFFEh-FFFFh
7
1
0
1
1
I1 H I0 N Z C
CONDITION CODE REGISTER
RESET VALUE =
8
1
1
X 1 X X X
0
15
7
STACK POINTER
RESET VALUE = STACK HIGHER ADDRESS
X = Undefined Value
20/163
1
ST72324
CENTRAL PROCESSING UNIT (Cont’d)
Condition Code Register (CC)
Read/Write
Bit 1 = Z Zero.
This bit is set and cleared by hardware. This bit in-
dicates that the result of the last arithmetic, logical
or data manipulation is zero.
0: The result of the last operation is different from
zero.
1: The result of the last operation is zero.
Reset Value: 111x1xxx
7
0
1
1
I1
H
I0
N
Z
C
This bit is accessed by the JREQ and JRNE test
instructions.
The 8-bit Condition Code register contains the in-
terrupt masks and four flags representative of the
result of the instruction just executed. This register
can also be handled by the PUSH and POP in-
structions.
Bit 0 = C Carry/borrow.
This bit is set and cleared by hardware and soft-
ware. It indicates an overflow or an underflow has
occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.
These bits can be individually tested and/or con-
trolled by specific instructions.
Arithmetic Management Bits
This bit is driven by the SCF and RCF instructions
and tested by the JRC and JRNC instructions. It is
also affected by the “bit test and branch”, shift and
rotate instructions.
Bit 4 = H Half carry.
This bit is set by hardware when a carry occurs be-
tween bits 3 and 4 of the ALU during an ADD or
ADC instructions. It is reset by hardware during
the same instructions.
Interrupt Management Bits
Bit 5,3 = I1, I0 Interrupt
0: No half carry has occurred.
1: A half carry has occurred.
The combination of the I1 and I0 bits gives the cur-
rent interrupt software priority.
This bit is tested using the JRH or JRNH instruc-
tion. The H bit is useful in BCD arithmetic subrou-
tines.
Interrupt Software Priority
Level 0 (main)
I1
1
0
0
1
I0
0
1
0
1
Level 1
Bit 2 = N Negative.
Level 2
This bit is set and cleared by hardware. It is repre-
sentative of the result sign of the last arithmetic,
logical or data manipulation. It’s a copy of the re-
Level 3 (= interrupt disable)
These two bits are set/cleared by hardware when
entering in interrupt. The loaded value is given by
the corresponding bits in the interrupt software pri-
ority registers (IxSPR). They can be also set/
cleared by software with the RIM, SIM, IRET,
HALT, WFI and PUSH/POP instructions.
th
sult 7 bit.
0: The result of the last operation is positive or null.
1: The result of the last operation is negative
(i.e. the most significant bit is a logic 1).
This bit is accessed by the JRMI and JRPL instruc-
tions.
See the interrupt management chapter for more
details.
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ST72324
CENTRAL PROCESSING UNIT (Cont’d)
Stack Pointer (SP)
Read/Write
The least significant byte of the Stack Pointer
(called S) can be directly accessed by a LD in-
struction.
Reset Value: 01 FFh
Note: When the lower limit is exceeded, the Stack
Pointer wraps around to the stack upper limit, with-
out indicating the stack overflow. The previously
stored information is then overwritten and there-
fore lost. The stack also wraps in case of an under-
flow.
15
8
1
0
7
0
0
0
0
0
0
0
The stack is used to save the return address dur-
ing a subroutine call and the CPU context during
an interrupt. The user may also directly manipulate
the stack by means of the PUSH and POP instruc-
tions. In the case of an interrupt, the PCL is stored
at the first location pointed to by the SP. Then the
other registers are stored in the next locations as
shown in Figure 9.
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
The Stack Pointer is a 16-bit register which is al-
ways pointing to the next free location in the stack.
It is then decremented after data has been pushed
onto the stack and incremented before data is
popped from the stack (see Figure 9).
– When an interrupt is received, the SP is decre-
mented and the context is pushed on the stack.
Since the stack is 256 bytes deep, the 8 most sig-
nificant bits are forced by hardware. Following an
MCU Reset, or after a Reset Stack Pointer instruc-
tion (RSP), the Stack Pointer contains its reset val-
ue (the SP7 to SP0 bits are set) which is the stack
higher address.
– On return from interrupt, the SP is incremented
and the context is popped from the stack.
A subroutine call occupies two locations and an in-
terrupt five locations in the stack area.
Figure 9. Stack Manipulation Example
CALL
Subroutine
RET
or RSP
PUSH Y
POP Y
IRET
Interrupt
Event
@ 0100h
SP
SP
SP
Y
CC
A
CC
A
CC
A
X
X
X
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
SP
SP
PCH
PCL
PCH
PCL
SP
@ 01FFh
Stack Higher Address = 01FFh
0100h
Stack Lower Address =
22/163
1
ST72324
6 SUPPLY, RESET AND CLOCK MANAGEMENT
The device includes a range of utility features for
securing the application in critical situations (for
example in case of a power brown-out), and re-
ducing the number of external components. An
overview is shown in Figure 11.
6.1 PHASE LOCKED LOOP
If the clock frequency input to the PLL is in the
range 2 to 4 MHz, the PLL can be used to multiply
the frequency by two to obtain an f
of 4 to 8
OSC2
MHz. The PLL is enabled by option byte. If the PLL
is disabled, then f /2.
For more details, refer to dedicated parametric
section.
f
OSC2 = OSC
Caution: The PLL is not recommended for appli-
cations where timing accuracy is required.
Main features
■ Optional PLL for multiplying the frequency by 2
(not to be used with internal RC oscillator in
order to respect the max. operating frequency)
Caution: The PLL must not be used with the inter-
nal RC oscillator.
■ Reset Sequence Manager (RSM)
■ Multi-Oscillator Clock Management (MO)
Figure 10. PLL Block Diagram
– 5 Crystal/Ceramic resonator oscillators
– 1 Internal RC oscillator
■ System Integrity Management (SI)
PLL x 2
/ 2
0
1
f
OSC
f
OSC2
– Main supply Low voltage detection (LVD)
– Auxiliary Voltage detector (AVD) with interrupt
PLL OPTION BIT
capability for monitoring the main supply
Figure 11. Clock, Reset and Supply Block Diagram
MAIN CLOCK
CONTROLLER
WITH REALTIME
MULTI-
f
OSC2
f
f
CPU
OSC2
OSC
PLL
(option)
OSCILLATOR
(MO)
OSC1
CLOCK (MCC/RTC)
SYSTEM INTEGRITY MANAGEMENT
RESET SEQUENCE
MANAGER
WATCHDOG
TIMER (WDG)
AVD Interrupt Request
RESET
SICSR
AVD AVD
LVD
RF
WDG
RF
(RSM)
0
0
0
0
IE
F
LOW VOLTAGE
DETECTOR
(LVD)
V
V
SS
DD
AUXILIARY VOLTAGE
DETECTOR
(AVD)
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ST72324
6.2 MULTI-OSCILLATOR (MO)
The main clock of the ST7 can be generated by
three different source types coming from the multi-
oscillator block:
■ an external source
■ 4 crystal or ceramic resonator oscillators
■ an internal high frequency RC oscillator
Internal RC Oscillator
This oscillator allows a low cost solution for the
main clock of the ST7 using only an internal resis-
tor and capacitor. Internal RC oscillator mode has
the drawback of a lower frequency accuracy and
should not be used in applications that require ac-
curate timing.
Each oscillator is optimized for a given frequency
range in terms of consumption and is selectable
through the option byte. The associated hardware
configurations are shown in Table 5. Refer to the
electrical characteristics section for more details.
In this mode, the two oscillator pins have to be tied
to ground.
In order not to exceed the max. operating frequen-
cy, the internal RC oscillator must not be used with
the PLL.
Caution: The OSC1 and/or OSC2 pins must not
be left unconnected. For the purposes of Failure
Mode and Effect Analysis, it should be noted that if
the OSC1 and/or OSC2 pins are left unconnected,
the ST7 main oscillator may start and, in this con-
Table 5. ST7 Clock Sources
Hardware Configuration
figuration, could generate an f
clock frequency
OSC
in excess of the allowed maximum (>16MHz.),
putting the ST7 in an unsafe/undefined state. The
product behaviour must therefore be considered
undefined when the OSC pins are left unconnect-
ed.
ST7
OSC1
OSC2
EXTERNAL
SOURCE
External Clock Source
In this external clock mode, a clock signal (square,
sinus or triangle) with ~50% duty cycle has to drive
the OSC1 pin while the OSC2 pin is tied to ground.
ST7
Crystal/Ceramic Oscillators
OSC1
OSC2
This family of oscillators has the advantage of pro-
ducing a very accurate rate on the main clock of
the ST7. The selection within a list of 4 oscillators
with different frequency ranges has to be done by
option byte in order to reduce consumption (refer
to Section 14.1 on page 150 for more details on
the frequency ranges). In this mode of the multi-
oscillator, the resonator and the load capacitors
have to be placed as close as possible to the oscil-
lator pins in order to minimize output distortion and
start-up stabilization time. The loading capaci-
tance values must be adjusted according to the
selected oscillator.
C
C
L2
L1
LOAD
CAPACITORS
ST7
OSC1
OSC2
These oscillators are not stopped during the
RESET phase to avoid losing time in the oscillator
start-up phase.
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1
ST72324
6.3 RESET SEQUENCE MANAGER (RSM)
6.3.1 Introduction
The RESET vector fetch phase duration is 2 clock
cycles.
The reset sequence manager includes three RE-
SET sources as shown in Figure 13:
■ External RESET source pulse
Figure 12. RESET Sequence Phases
■ Internal LVD RESET (Low Voltage Detection)
■ Internal WATCHDOG RESET
RESET
These sources act on the RESET pin and it is al-
ways kept low during the delay phase.
INTERNAL RESET
256 or 4096 CLOCK CYCLES
FETCH
VECTOR
Active Phase
The RESET service routine vector is fixed at ad-
dresses FFFEh-FFFFh in the ST7 memory map.
6.3.2 Asynchronous External RESET pin
The basic RESET sequence consists of 3 phases
as shown in Figure 12:
■ Active Phase depending on the RESET source
■ 256 or 4096 CPU clock cycle delay (selected by
option byte)
■ RESET vector fetch
The RESET pin is both an input and an open-drain
output with integrated R
weak pull-up resistor.
ON
This pull-up has no fixed value but varies in ac-
cordance with the input voltage. It can be pulled
low by external circuitry to reset the device. See
Electrical Characteristic section for more details.
A RESET signal originating from an external
The 256 or 4096 CPU clock cycle delay allows the
oscillator to stabilise and ensures that recovery
has taken place from the Reset state. The shorter
or longer clock cycle delay should be selected by
option byte to correspond to the stabilization time
of the external oscillator used in the application.
source must have a duration of at least t
in
h(RSTL)in
order to be recognized (see Figure 14). This de-
tection is asynchronous and therefore the MCU
can enter reset state even in HALT mode.
Figure 13. Reset Block Diagram
V
DD
R
ON
INTERNAL
RESET
Filter
RESET
PULSE
GENERATOR
WATCHDOG RESET
LVD RESET
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ST72324
RESET SEQUENCE MANAGER (Cont’d)
The RESET pin is an asynchronous signal which
plays a major role in EMS performance. In a noisy
environment, it is recommended to follow the
guidelines mentioned in the electrical characteris-
tics section.
6.3.4 Internal Low Voltage Detector (LVD)
RESET
Two different RESET sequences caused by the in-
ternal LVD circuitry can be distinguished:
■ Power-On RESET
6.3.3 External Power-On RESET
■ Voltage Drop RESET
If the LVD is disabled by option byte, to start up the
microcontroller correctly, the user must ensure by
means of an external reset circuit that the reset
The device RESET pin acts as an output that is
pulled low when V <V
(rising edge) or
DD
IT+
V
<V (falling edge) as shown in Figure 14.
DD
IT-
signal is held low until V
is over the minimum
DD
The LVD filters spikes on V larger than t
to
level specified for the selected f
frequency.
DD
g(VDD)
OSC
avoid parasitic resets.
A proper reset signal for a slow rising V supply
DD
can generally be provided by an external RC net-
work connected to the RESET pin.
6.3.5 Internal Watchdog RESET
The RESET sequence generated by a internal
Watchdog counter overflow is shown in Figure 14.
Starting from the Watchdog counter underflow, the
device RESET pin acts as an output that is pulled
low during at least t
.
w(RSTL)out
Figure 14. RESET Sequences
V
DD
V
V
IT+(LVD)
IT-(LVD)
LVD
RESET
EXTERNAL
RESET
WATCHDOG
RESET
RUN
RUN
RUN
RUN
ACTIVE
PHASE
ACTIVE
PHASE
ACTIVE PHASE
t
w(RSTL)out
t
h(RSTL)in
EXTERNAL
RESET
SOURCE
RESET PIN
WATCHDOG
RESET
WATCHDOG UNDERFLOW
INTERNAL RESET (256 or 4096 TCPU
VECTOR FETCH
)
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ST72324
6.4 SYSTEM INTEGRITY MANAGEMENT (SI)
The System Integrity Management block contains
the Low Voltage Detector (LVD) and Auxiliary Volt-
age Detector (AVD) functions. It is managed by
the SICSR register.
– under full software control
– in static safe reset
In these conditions, secure operation is always en-
sured for the application without the need for ex-
ternal reset hardware.
6.4.1 Low Voltage Detector (LVD)
The Low Voltage Detector function (LVD) gener-
During a Low Voltage Detector Reset, the RESET
pin is held low, thus permitting the MCU to reset
other devices.
ates a static reset when the V supply voltage is
DD
below a V reference value. This means that it
IT-
secures the power-up as well as the power-down
keeping the ST7 in reset.
Notes:
The V reference value for a voltage drop is lower
IT-
The LVD allows the device to be used without any
external RESET circuitry.
than the V reference value for power-on in order
IT+
to avoid a parasitic reset when the MCU starts run-
ning and sinks current on the supply (hysteresis).
If the medium or low thresholds are selected, the
detection may occur outside the specified operat-
ing voltage range. Below 3.8V, device operation is
not guaranteed.
The LVD Reset circuitry generates a reset when
V
is below:
DD
– V when V is rising
IT+
DD
The LVD is an optional function which can be se-
lected by option byte.
– V when V is falling
IT-
DD
The LVD function is illustrated in Figure 15.
It is recommended to make sure that the V sup-
DD
The voltage threshold can be configured by option
byte to be low, medium or high.
ply voltage rises monotonously when the device is
exiting from Reset, to ensure the application func-
tions properly.
Provided the minimum V value (guaranteed for
DD
the oscillator frequency) is above V , the MCU
IT-
can only be in two modes:
Figure 15. Low Voltage Detector vs Reset
V
DD
V
hys
V
V
IT+
IT-
RESET
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ST72324
SYSTEM INTEGRITY MANAGEMENT (Cont’d)
6.4.2 Auxiliary Voltage Detector (AVD)
In the case of a drop in voltage, the AVD interrupt
acts as an early warning, allowing software to shut
down safely before the LVD resets the microcon-
troller. See Figure 16.
The Voltage Detector function (AVD) is based on
an analog comparison between a V
and
IT-(AVD)
V
reference value and the V
main sup-
IT+(AVD)
DD
ply. The V reference value for falling voltage is
The interrupt on the rising edge is used to inform
IT-
lower than the V reference value for rising volt-
the application that the V warning state is over.
IT+
DD
age in order to avoid parasitic detection (hystere-
sis).
If the voltage rise time t is less than 256 or 4096
rv
CPU cycles (depending on the reset delay select-
ed by option byte), no AVD interrupt will be gener-
The output of the AVD comparator is directly read-
able by the application software through a real
time status bit (AVDF) in the SICSR register. This
bit is read only.
Caution: The AVD function is active only if the
LVD is enabled through the option byte (see Sec-
tion 14.1 on page 150).
ated when V
is reached.
IT+(AVD)
If t is greater than 256 or 4096 cycles then:
rv
– If the AVD interrupt is enabled before the
V
threshold is reached, then 2 AVD inter-
IT+(AVD)
rupts will be received: the first when the AVDIE
bit is set, and the second when the threshold is
reached.
6.4.2.1 Monitoring the V Main Supply
DD
The AVD voltage threshold value is relative to the
selected LVD threshold configured by option byte
(see
– If the AVD interrupt is enabled after the V
threshold is reached then only one AVD interrupt
will occur.
IT+(AVD)
If the AVD interrupt is enabled, an interrupt is gen-
erated when the voltage crosses the V
IT-(AVD)
or
IT+(AVD)
V
threshold (AVDF bit toggles).
Figure 16. Using the AVD to Monitor V
DD
V
DD
Early Warning Interrupt
(Power has dropped, MCU not
not yet in reset)
V
hyst
V
IT+(AVD)
V
IT-(AVD)
V
V
IT+(LVD)
t
VOLTAGE RISE TIME
rv
IT-(LVD)
1
1
AVDF bit
0
RESET VALUE
0
AVD INTERRUPT
REQUEST
IF AVDIE bit = 1
INTERRUPT PROCESS
INTERRUPT PROCESS
LVD RESET
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ST72324
SYSTEM INTEGRITY MANAGEMENT (Cont’d)
6.4.3 Low Power Modes
Mode
Description
No effect on SI. AVD interrupt causes the
device to exit from Wait mode.
WAIT
HALT
The CRSR register is frozen.
6.4.3.1 Interrupts
The AVD interrupt event generates an interrupt if
the AVDIE bit is set and the interrupt mask in the
CC register is reset (RIM instruction).
Enable Exit
Control from
Exit
from
Halt
Event
Flag
Interrupt Event
Bit
Wait
AVD event
AVDF AVDIE
Yes
No
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ST72324
SYSTEM INTEGRITY MANAGEMENT (Cont’d)
6.4.4 Register Description
SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR)
Read/Write
Bits 3:1 = Reserved, must be kept cleared.
Reset Value: 000x 000x (00h)
Bit 0 = WDGRF Watchdog reset flag
7
0
This bit indicates that the last Reset was generat-
ed by the Watchdog peripheral. It is set by hard-
ware (watchdog reset) and cleared by software
(writing zero) or an LVD Reset (to ensure a stable
cleared state of the WDGRF flag when CPU
starts).
AVD
IE
AVD LVD
RF
WDG
RF
0
0
0
0
F
Bit 7 = Reserved, must be kept cleared.
Combined with the LVDRF flag information, the
flag description is given by the following table.
Bit 6 = AVDIE Voltage Detector interrupt enable
This bit is set and cleared by software. It enables
an interrupt to be generated when the AVDF flag
changes (toggles). The pending interrupt informa-
tion is automatically cleared when software enters
the AVD interrupt routine.
RESET Sources
LVDRF WDGRF
External RESET pin
Watchdog
0
0
1
0
1
LVD
X
0: AVD interrupt disabled
1: AVD interrupt enabled
Application notes
The LVDRF flag is not cleared when another RE-
SET type occurs (external or watchdog), the
LVDRF flag remains set to keep trace of the origi-
nal failure.
In this case, a watchdog reset can be detected by
software while an external reset can not.
Bit 5 = AVDF Voltage Detector flag
This read-only bit is set and cleared by hardware.
If the AVDIE bit is set, an interrupt request is gen-
erated when the AVDF bit changes value. Refer to
Figure 16 and to Section 6.4.2.1 for additional de-
tails.
CAUTION: When the LVD is not activated with the
associated option byte, the WDGRF flag can not
be used in the application.
0: V over V
threshold
threshold
IT-(AVD)
DD
IT+(AVD)
1: V under V
DD
Bit 4 = LVDRF LVD reset flag
This bit indicates that the last Reset was generat-
ed by the LVD block. It is set by hardware (LVD re-
set) and cleared by software (writing zero). See
WDGRF flag description for more details. When
the LVD is disabled by OPTION BYTE, the LVDRF
bit value is undefined.
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ST72324
7 INTERRUPTS
7.1 INTRODUCTION
When an interrupt request has to be serviced:
– Normal processing is suspended at the end of
the current instruction execution.
– The PC, X, A and CC registers are saved onto
the stack.
– I1 and I0 bits of CC register are set according to
the corresponding values in the ISPRx registers
of the serviced interrupt vector.
– The PC is then loaded with the interrupt vector of
the interrupt to service and the first instruction of
the interrupt service routine is fetched (refer to
“Interrupt Mapping” table for vector addresses).
The ST7 enhanced interrupt management pro-
vides the following features:
■ Hardware interrupts
■ Software interrupt (TRAP)
■ Nested or concurrent interrupt management
with flexible interrupt priority and level
management:
– Up to 4 software programmable nesting levels
– Up to 16 interrupt vectors fixed by hardware
– 2 non maskable events: RESET, TRAP
This interrupt management is based on:
The interrupt service routine should end with the
IRET instruction which causes the contents of the
saved registers to be recovered from the stack.
– Bit 5 and bit 3 of the CPU CC register (I1:0),
– Interrupt software priority registers (ISPRx),
– Fixed interrupt vector addresses located at the
high addresses of the memory map (FFE0h to
FFFFh) sorted by hardware priority order.
Note: As a consequence of the IRET instruction,
the I1 and I0 bits will be restored from the stack
and the program in the previous level will resume.
This enhanced interrupt controller guarantees full
upward compatibility with the standard (not nest-
ed) ST7 interrupt controller.
Table 6. Interrupt Software Priority Levels
Interrupt software priority Level
I1
1
I0
0
Level 0 (main)
Level 1
Low
7.2 MASKING AND PROCESSING FLOW
0
1
Level 2
0
0
The interrupt masking is managed by the I1 and I0
bits of the CC register and the ISPRx registers
which give the interrupt software priority level of
each interrupt vector (see Table 6). The process-
ing flow is shown in Figure 17
Level 3 (= interrupt disable)
High
1
1
Figure 17. Interrupt Processing Flowchart
PENDING
INTERRUPT
Y
Y
RESET
TRAP
N
Interrupt has the same or a
lower software priority
than current one
N
I1:0
FETCH NEXT
INSTRUCTION
THE INTERRUPT
STAYS PENDING
Y
“IRET”
N
RESTORE PC, X, A, CC
FROM STACK
EXECUTE
INSTRUCTION
STACK PC, X, A, CC
LOAD I1:0 FROM INTERRUPT SW REG.
LOAD PC FROM INTERRUPT VECTOR
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ST72324
INTERRUPTS (Cont’d)
Servicing Pending Interrupts
vector is loaded in the PC register and the I1 and
I0 bits of the CC are set to disable interrupts (level
3). These sources allow the processor to exit
HALT mode.
As several interrupts can be pending at the same
time, the interrupt to be taken into account is deter-
mined by the following two-step process:
■ TRAP (Non Maskable Software Interrupt)
– the highest software priority interrupt is serviced,
This software interrupt is serviced when the TRAP
instruction is executed. It will be serviced accord-
ing to the flowchart in Figure 17.
– if several interrupts have the same software pri-
ority then the interrupt with the highest hardware
priority is serviced first.
■ RESET
Figure 18 describes this decision process.
The RESET source has the highest priority in the
ST7. This means that the first current routine has
the highest software priority (level 3) and the high-
est hardware priority.
Figure 18. Priority Decision Process
PENDING
INTERRUPTS
See the RESET chapter for more details.
Maskable Sources
Maskable interrupt vector sources can be serviced
if the corresponding interrupt is enabled and if its
own interrupt software priority (in ISPRx registers)
is higher than the one currently being serviced (I1
and I0 in CC register). If any of these two condi-
tions is false, the interrupt is latched and thus re-
mains pending.
Different
Same
SOFTWARE
PRIORITY
HIGHEST SOFTWARE
PRIORITY SERVICED
■ External Interrupts
HIGHEST HARDWARE
PRIORITY SERVICED
External interrupts allow the processor to exit from
HALT low power mode. External interrupt sensitiv-
ity is software selectable through the External In-
terrupt Control register (EICR).
External interrupt triggered on edge will be latched
and the interrupt request automatically cleared
upon entering the interrupt service routine.
If several input pins of a group connected to the
same interrupt line are selected simultaneously,
these will be logically ORed.
When an interrupt request is not serviced immedi-
ately, it is latched and then processed when its
software priority combined with the hardware pri-
ority becomes the highest one.
Note 1: The hardware priority is exclusive while
the software one is not. This allows the previous
process to succeed with only one interrupt.
Note 2: RESET and TRAP can be considered as
having the highest software priority in the decision
process.
■ Peripheral Interrupts
Usually the peripheral interrupts cause the MCU to
exit from HALT mode except those mentioned in
the “Interrupt Mapping” table. A peripheral inter-
rupt occurs when a specific flag is set in the pe-
ripheral status registers and if the corresponding
enable bit is set in the peripheral control register.
The general sequence for clearing an interrupt is
based on an access to the status register followed
by a read or write to an associated register.
Note: The clearing sequence resets the internal
latch. A pending interrupt (i.e. waiting for being
serviced) will therefore be lost if the clear se-
quence is executed.
Different Interrupt Vector Sources
Two interrupt source types are managed by the
ST7 interrupt controller: the non-maskable type
(RESET,TRAP) and the maskable type (external
or from internal peripherals).
Non-Maskable Sources
These sources are processed regardless of the
state of the I1 and I0 bits of the CC register (see
Figure 17). After stacking the PC, X, A and CC
registers (except for RESET), the corresponding
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ST72324
INTERRUPTS (Cont’d)
7.3 INTERRUPTS AND LOW POWER MODES
7.4 CONCURRENT & NESTED MANAGEMENT
All interrupts allow the processor to exit the WAIT
low power mode. On the contrary, only external
and other specified interrupts allow the processor
to exit from the HALT modes (see column “Exit
from HALT” in “Interrupt Mapping” table). When
several pending interrupts are present while exit-
ing HALT mode, the first one serviced can only be
an interrupt with exit from HALT mode capability
and it is selected through the same decision proc-
ess shown in Figure 18.
The following Figure 19 and Figure 20 show two
different interrupt management modes. The first is
called concurrent mode and does not allow an in-
terrupt to be interrupted, unlike the nested mode in
Figure 20. The interrupt hardware priority is given
in this order from the lowest to the highest: MAIN,
IT4, IT3, IT2, IT1, IT0. The software priority is giv-
en for each interrupt.
Warning: A stack overflow may occur without no-
tifying the software of the failure.
Note: If an interrupt, that is not able to Exit from
HALT mode, is pending with the highest priority
when exiting HALT mode, this interrupt is serviced
after the first one serviced.
Figure 19. Concurrent Interrupt Management
SOFTWARE
PRIORITY
I1
I0
LEVEL
TRAP
3
1 1
1 1
1 1
1 1
1 1
1 1
IT0
3
IT1
IT1
3
IT2
3
IT3
3
RIM
IT4
3
MAIN
MAIN
3/0
11 / 10
10
Figure 20. Nested Interrupt Management
SOFTWARE
PRIORITY
LEVEL
I1
I0
TRAP
3
1 1
1 1
0 0
0 1
1 1
1 1
IT0
3
IT1
IT1
IT2
2
IT2
1
IT3
3
RIM
IT4
IT4
3
MAIN
MAIN
3/0
11 / 10
10
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1
ST72324
INTERRUPTS (Cont’d)
7.5 INTERRUPT REGISTER DESCRIPTION
CPU CC REGISTER INTERRUPT BITS
Read/Write
INTERRUPT SOFTWARE PRIORITY REGIS-
TERS (ISPRX)
Reset Value: 111x 1010 (xAh)
Read/Write (bit 7:4 of ISPR3 are read only)
7
0
Reset Value: 1111 1111 (FFh)
7
0
1
1
I1
H
I0
N
Z
C
ISPR0
ISPR1
I1_3 I0_3 I1_2 I0_2 I1_1 I0_1 I1_0 I0_0
I1_7 I0_7 I1_6 I0_6 I1_5 I0_5 I1_4 I0_4
Bit 5, 3 = I1, I0 Software Interrupt Priority
These two bits indicate the current interrupt soft-
ware priority.
ISPR2 I1_11 I0_11 I1_10 I0_10 I1_9 I0_9 I1_8 I0_8
Interrupt Software Priority Level
I1
1
I0
0
Level 0 (main)
Level 1
Low
ISPR3
1
1
1
1
I1_13 I0_13 I1_12 I0_12
0
1
Level 2
0
0
These four registers contain the interrupt software
priority of each interrupt vector.
Level 3 (= interrupt disable*)
High
1
1
These two bits are set/cleared by hardware when
entering in interrupt. The loaded value is given by
the corresponding bits in the interrupt software pri-
ority registers (ISPRx).
– Each interrupt vector (except RESET and TRAP)
has corresponding bits in these registers where
its own software priority is stored. This corre-
spondance is shown in the following table.
They can be also set/cleared by software with the
RIM, SIM, HALT, WFI, IRET and PUSH/POP in-
structions (see “Interrupt Dedicated Instruction
Set” table).
Vector address
ISPRx bits
FFFBh-FFFAh
FFF9h-FFF8h
...
I1_0 and I0_0 bits*
I1_1 and I0_1 bits
...
*Note: TRAP and RESET events can interrupt a
level 3 program.
FFE1h-FFE0h
I1_13 and I0_13 bits
– Each I1_x and I0_x bit value in the ISPRx regis-
ters has the same meaning as the I1 and I0 bits
in the CC register.
– Level 0 can not be written (I1_x=1, I0_x=0). In
this case, the previously stored value is kept. (ex-
ample: previous=CFh, write=64h, result=44h)
The RESET, and TRAP vectors have no software
priorities. When one is serviced, the I1 and I0 bits
of the CC register are both set.
Caution: If the I1_x and I0_x bits are modified
while the interrupt x is executed the following be-
haviour has to be considered: If the interrupt x is
still pending (new interrupt or flag not cleared) and
the new software priority is higher than the previ-
ous one, the interrupt x is re-entered. Otherwise,
the software priority stays unchanged up to the
next interrupt request (after the IRET of the inter-
rupt x).
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ST72324
INTERRUPTS (Cont’d)
Table 7. Dedicated Interrupt Instruction Set
Instruction
New Description
Entering Halt mode
Function/Example
I1
H
I0
N
Z
C
HALT
IRET
JRM
1
0
Interrupt routine return
Jump if I1:0=11 (level 3)
Jump if I1:0<>11
Pop CC, A, X, PC
I1:0=11?
I1
H
I0
N
Z
C
JRNM
POP CC
RIM
I1:0<>11?
Pop CC from the Stack
Enable interrupt (level 0 set)
Disable interrupt (level 3 set)
Software trap
Mem => CC
I1
1
H
I0
0
1
1
0
N
Z
C
Load 10 in I1:0 of CC
Load 11 in I1:0 of CC
Software NMI
SIM
1
TRAP
WFI
1
Wait for interrupt
1
Note: During the execution of an interrupt routine, the HALT, POPCC, RIM, SIM and WFI instructions change the current
software priority up to the next IRET instruction or one of the previously mentioned instructions.
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ST72324
INTERRUPTS (Cont’d)
Table 8. Interrupt Mapping
Exit
from
Source
Block
Register Priority
Address
Vector
N°
Description
HALT/
ACTIVE
Label
Order
1)
HALT
RESET
TRAP
Reset
Software interrupt
Not used
yes
no
FFFEh-FFFFh
FFFCh-FFFDh
FFFAh-FFFBh
FFF8h-FFF9h
FFF6h-FFF7h
FFF4h-FFF5h
FFF2h-FFF3h
FFF0h-FFF1h
FFEEh-FFEFh
FFECh-FFEDh
FFEAh-FFEBh
FFE8h-FFE9h
FFE6h-FFE7h
FFE4h-FFE5h
N/A
MCCSR
N/A
0
1
MCC/RTC
Main clock controller time base interrupt
External interrupt port A3..0
External interrupt port F2..0
External interrupt port B3..0
External interrupt port B7..4
Not used
yes
yes
yes
yes
yes
Higher
Priority
2
ei0
ei1
ei2
ei3
3
4
5
6
7
SPI
TIMER A
TIMER B
SCI
SPI peripheral interrupts
SPICSR
TASR
yes
no
no
no
no
8
TIMER A peripheral interrupts
TIMER B peripheral interrupts
SCI Peripheral interrupts
9
TBSR
10
11
SCISR
SICSR
Lower
Priority
AVD
Auxiliary Voltage detector interrupt
Notes:
1. In Flash devices only a RESET or MCC/RTC interrupt can be used to wake-up from Active Halt mode.
7.6 EXTERNAL INTERRUPTS
7.6.1 I/O Port Interrupt Sensitivity
■ Falling edge and low level
■ Rising edge and high level (only for ei0 and ei2)
The external interrupt sensitivity is controlled by
the IPA, IPB and ISxx bits of the EICR register
(Figure 21). This control allows to have up to 4 fully
independent external interrupt source sensitivities.
To guarantee correct functionality, the sensitivity
bits in the EICR register can be modified only
when the I1 and I0 bits of the CC register are both
set to 1 (level 3). This means that interrupts must
be disabled before changing sensitivity.
Each external interrupt source can be generated
on four (or five) different events on the pin:
■ Falling edge
■ Rising edge
■ Falling and rising edge
The pending interrupts are cleared by writing a dif-
ferent value in the ISx[1:0], IPA or IPB bits of the
EICR.
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ST72324
Figure 21. External Interrupt Control bits
EICR
IS20 IS21
PORT A3 INTERRUPT
PAOR.3
PADDR.3
ei0 INTERRUPT SOURCE
SENSITIVITY
CONTROL
PA3
IPA BIT
EICR
PORT F [2:0] INTERRUPTS
IS20
IS21
PFOR.2
PFDDR.2
SENSITIVITY
CONTROL
PF2
PF1
PF0
ei1 INTERRUPT SOURCE
PF2
EICR
PORT B [3:0] INTERRUPTS
IS10
IS11
PBOR.3
PBDDR.3
SENSITIVITY
CONTROL
PB3
PB2
PB1
PB0
PB3
ei2 INTERRUPT SOURCE
IPB BIT
EICR
PORT B4 INTERRUPT
IS10
IS11
PBOR.4
PBDDR.4
SENSITIVITY
CONTROL
ei3 INTERRUPT SOURCE
PB4
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ST72324
INTERRUPTS (Cont’d)
7.7 EXTERNAL INTERRUPT CONTROL REGISTER (EICR)
Read/Write
Bit 4:3 = IS2[1:0] ei0 and ei1 sensitivity
The interrupt sensitivity, defined using the IS2[1:0]
bits, is applied to the following external interrupts:
Reset Value: 0000 0000 (00h)
7
0
0
IS11 IS10 IPB IS21 IS20 IPA
0
- ei0 (port A3..0)
Bit 7:6 = IS1[1:0] ei2 and ei3 sensitivity
The interrupt sensitivity, defined using the IS1[1:0]
bits, is applied to the following external interrupts:
- ei2 (port B3..0)
External Interrupt Sensitivity
IS21 IS20
IPA bit =0
IPA bit =1
Falling edge &
low level
Rising edge
& high level
0
0
External Interrupt Sensitivity
IS11 IS10
0
1
1
1
0
1
Rising edge only
Falling edge only
Falling edge only
Rising edge only
IPB bit =0
IPB bit =1
Falling edge &
low level
Rising edge
& high level
0
0
Rising and falling edge
0
1
1
1
0
1
Rising edge only
Falling edge only
Falling edge only
Rising edge only
- ei1 (port F2..0)
Rising and falling edge
IS21 IS20
External Interrupt Sensitivity
- ei3 (port B4)
0
0
1
1
0
1
0
1
Falling edge & low level
Rising edge only
IS11 IS10
External Interrupt Sensitivity
0
0
1
1
0
1
0
1
Falling edge & low level
Rising edge only
Falling edge only
Rising and falling edge
Falling edge only
These 2 bits can be written only when I1 and I0 of
the CC register are both set to 1 (level 3).
Rising and falling edge
These 2 bits can be written only when I1 and I0 of
the CC register are both set to 1 (level 3).
Bit 2 = IPA Interrupt polarity for port A
This bit is used to invert the sensitivity of the port A
[3:0] external interrupts. It can be set and cleared
by software only when I1 and I0 of the CC register
are both set to 1 (level 3).
Bit 5 = IPB Interrupt polarity for port B
This bit is used to invert the sensitivity of the port B
[3:0] external interrupts. It can be set and cleared
by software only when I1 and I0 of the CC register
are both set to 1 (level 3).
0: No sensitivity inversion
1: Sensitivity inversion
0: No sensitivity inversion
1: Sensitivity inversion
Bits 1:0 = Reserved, must always be kept cleared.
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ST72324
INTERRUPTS (Cont’d)
Table 9. Nested Interrupts Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
ei1
SPI
ei0
MCC + SI
0024h
0025h
0026h
I1_3
1
I0_3
1
I1_2
1
I0_2
1
I1_1
1
I0_1
1
ISPR0
Reset Value
1
1
ei3
ei2
I1_7
1
I0_7
1
I1_6
1
I0_6
1
I1_5
1
I0_5
1
I1_4
1
I0_4
1
ISPR1
Reset Value
AVD
SCI
TIMER B
TIMER A
I1_11
1
I0_11
1
I1_10
1
I0_10
1
I1_9
I0_9
1
I1_8
1
I0_8
1
ISPR2
Reset Value
1
0027h
0028h
I1_13
1
I0_13
1
I1_12
1
I0_12
1
ISPR3
Reset Value
1
1
1
1
EICR
Reset Value
IS11
0
IS10
0
IPB
0
IS21
0
IS20
0
IPA
0
0
0
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ST72324
8 POWER SAVING MODES
8.1 INTRODUCTION
8.2 SLOW MODE
To give a large measure of flexibility to the applica-
tion in terms of power consumption, four main
power saving modes are implemented in the ST7
(see Figure 22): SLOW, WAIT (SLOW WAIT), AC-
TIVE HALT and HALT.
This mode has two targets:
– To reduce power consumption by decreasing the
internal clock in the device,
– To adapt the internal clock frequency (f
the available supply voltage.
) to
CPU
After a RESET the normal operating mode is se-
lected by default (RUN mode). This mode drives
the device (CPU and embedded peripherals) by
means of a master clock which is based on the
main oscillator frequency divided or multiplied by 2
SLOW mode is controlled by three bits in the
MCCSR register: the SMS bit which enables or
disables Slow mode and two CPx bits which select
the internal slow frequency (f
).
CPU
(f
).
In this mode, the master clock frequency (f
)
OSC2
OSC2
can be divided by 2, 4, 8 or 16. The CPU and pe-
ripherals are clocked at this lower frequency
CPU
From RUN mode, the different power saving
modes may be selected by setting the relevant
register bits or by calling the specific ST7 software
instruction whose action depends on the oscillator
status.
(f
).
Note: SLOW-WAIT mode is activated when enter-
ing the WAIT mode while the device is already in
SLOW mode.
Figure 22. Power Saving Mode Transitions
Figure 23. SLOW Mode Clock Transitions
High
RUN
f
/2
f
/4
f
OSC2
OSC2
OSC2
f
CPU
f
OSC2
SLOW
WAIT
00
01
CP1:0
SMS
SLOW WAIT
ACTIVE HALT
HALT
NORMAL RUN MODE
REQUEST
NEW SLOW
FREQUENCY
REQUEST
Low
POWER CONSUMPTION
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ST72324
POWER SAVING MODES (Cont’d)
8.3 WAIT MODE
Figure 24. WAIT Mode Flow-chart
WAIT mode places the MCU in a low power con-
sumption mode by stopping the CPU.
This power saving mode is selected by calling the
‘WFI’ instruction.
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
ON
ON
OFF
10
WFI INSTRUCTION
All peripherals remain active. During WAIT mode,
the I[1:0] bits of the CC register are forced to ‘10’,
to enable all interrupts. All other registers and
memory remain unchanged. The MCU remains in
WAIT mode until an interrupt or RESET occurs,
whereupon the Program Counter branches to the
starting address of the interrupt or Reset service
routine.
N
RESET
Y
N
INTERRUPT
The MCU will remain in WAIT mode until a Reset
or an Interrupt occurs, causing it to wake up.
Y
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
ON
OFF
ON
10
Refer to Figure 24.
256 OR 4096 CPU CLOCK
CYCLE DELAY
OSCILLATOR
ON
PERIPHERALS
CPU
I[1:0] BITS
ON
ON
XX 1)
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Note:
1. Before servicing an interrupt, the CC register is
pushed on the stack. The I[1:0] bits of the CC reg-
ister are set to the current software priority level of
the interrupt routine and recovered when the CC
register is popped.
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ST72324
POWER SAVING MODES (Cont’d)
8.4 ACTIVE-HALT AND HALT MODES
pending on option byte). Otherwise, the ST7 en-
ters HALT mode for the remaining t period.
DELAY
ACTIVE-HALT and HALT modes are the two low-
est power consumption modes of the MCU. They
are both entered by executing the ‘HALT’ instruc-
tion. The decision to enter either in ACTIVE-HALT
or HALT mode is given by the MCC/RTC interrupt
enable flag (OIE bit in MCCSR register).
Figure 25. ACTIVE-HALT Timing Overview
ACTIVE
HALT
256 OR 4096 CPU
CYCLE DELAY
RUN
RUN
1)
RESET
OR
INTERRUPT
MCCSR Power Saving Mode entered when HALT
HALT
INSTRUCTION
[MCCSR.OIE=1]
OIE bit
instruction is executed
HALT mode
ACTIVE-HALT mode
FETCH
VECTOR
0
1
Figure 26. ACTIVE-HALT Mode Flow-chart
8.4.1 ACTIVE-HALT MODE
OSCILLATOR
PERIPHERALS
CPU
ON
OFF
OFF
10
2)
HALT INSTRUCTION
(MCCSR.OIE=1)
ACTIVE-HALT mode is the lowest power con-
sumption mode of the MCU with a real time clock
available. It is entered by executing the ‘HALT’ in-
struction when the OIE bit of the Main Clock Con-
troller Status register (MCCSR) is set (see Section
10.2 on page 56 for more details on the MCCSR
register).
I[1:0] BITS
N
RESET
Y
N
3)
INTERRUPT
Y
The MCU can exit ACTIVE-HALT mode on recep-
tion of either an MCC/RTC interrupt, a specific in-
terrupt (see Table 8, “Interrupt Mapping,” on
page 36) or a RESET. When exiting ACTIVE-
HALT mode by means of an interrupt, no 256 or
4096 CPU cycle delay occurs. The CPU resumes
operation by servicing the interrupt or by fetching
the reset vector which woke it up (see Figure 26).
OSCILLATOR
PERIPHERALS
CPU
ON
OFF
ON
4)
I[1:0] BITS
XX
256 OR 4096 CPU CLOCK
CYCLE DELAY
When entering ACTIVE-HALT mode, the I[1:0] bits
in the CC register are forced to ‘10b’ to enable in-
terrupts. Therefore, if an interrupt is pending, the
MCU wakes up immediately.
OSCILLATOR
PERIPHERALS
CPU
ON
ON
ON
4)
I[1:0] BITS
XX
In ACTIVE-HALT mode, only the main oscillator
and its associated counter (MCC/RTC) are run-
ning to keep a wake-up time base. All other periph-
erals are not clocked except those which get their
clock supply from another clock generator (such
as external or auxiliary oscillator).
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Notes:
1. This delay occurs only if the MCU exits ACTIVE-
HALT mode by means of a RESET.
2. Peripheral clocked with an external clock source
can still be active.
3. Only the MCC/RTC interrupt and some specific
interrupts can exit the MCU from ACTIVE-HALT
mode (such as external interrupt). Refer to
Table 8, “Interrupt Mapping,” on page 36 for more
details.
4. Before servicing an interrupt, the CC register is
pushed on the stack. The I[1:0] bits of the CC reg-
ister are set to the current software priority level of
the interrupt routine and restored when the CC
register is popped.
The safeguard against staying locked in ACTIVE-
HALT mode is provided by the oscillator interrupt.
Note: As soon as the interrupt capability of one of
the oscillators is selected (MCCSR.OIE bit set),
entering ACTIVE-HALT mode while the Watchdog
is active does not generate a RESET.
This means that the device cannot spend more
than a defined delay in this power saving mode.
CAUTION: When exiting ACTIVE-HALT mode fol-
lowing an interrupt, OIE bit of MCCSR register
must not be cleared before t
after the inter-
CPU
DELAY
rupt occurs (t
= 256 or 4096 t
delay de-
DELAY
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ST72324
POWER SAVING MODES (Cont’d)
8.4.2 HALT MODE
Figure 28. HALT Mode Flow-chart
The HALT mode is the lowest power consumption
mode of the MCU. It is entered by executing the
‘HALT’ instruction when the OIE bit of the Main
Clock Controller Status register (MCCSR) is
cleared (see Section 10.2 on page 56 for more de-
tails on the MCCSR register).
HALT INSTRUCTION
(MCCSR.OIE=0)
ENABLE
WATCHDOG
0
DISABLE
WDGHALT 1)
The MCU can exit HALT mode on reception of ei-
ther a specific interrupt (see Table 8, “Interrupt
Mapping,” on page 36) or a RESET. When exiting
HALT mode by means of a RESET or an interrupt,
the oscillator is immediately turned on and the 256
or 4096 CPU cycle delay is used to stabilize the
oscillator. After the start up delay, the CPU
resumes operation by servicing the interrupt or by
fetching the reset vector which woke it up (see Fig-
ure 28).
When entering HALT mode, the I[1:0] bits in the
CC register are forced to ‘10b’to enable interrupts.
Therefore, if an interrupt is pending, the MCU
wakes up immediately.
1
WATCHDOG
RESET
OSCILLATOR
OFF
PERIPHERALS 2)
CPU
OFF
OFF
10
I[1:0] BITS
N
RESET
Y
N
INTERRUPT 3)
In HALT mode, the main oscillator is turned off
causing all internal processing to be stopped, in-
cluding the operation of the on-chip peripherals.
All peripherals are not clocked except the ones
which get their clock supply from another clock
generator (such as an external or auxiliary oscilla-
tor).
Y
OSCILLATOR
PERIPHERALS
CPU
ON
OFF
ON
I[1:0] BITS
XX 4)
256 OR 4096 CPU CLOCK
CYCLE DELAY
The compatibility of Watchdog operation with
HALT mode is configured by the “WDGHALT” op-
tion bit of the option byte. The HALT instruction
when executed while the Watchdog system is en-
abled, can generate a Watchdog RESET (see
Section 14.1 on page 150) for more details.
OSCILLATOR
PERIPHERALS
CPU
ON
ON
ON
I[1:0] BITS
XX 4)
Figure 27. HALT Timing Overview
FETCH RESET VECTOR
OR SERVICE INTERRUPT
256 OR 4096 CPU
CYCLE DELAY
RUN
HALT
RUN
Notes:
RESET
OR
INTERRUPT
1. WDGHALT is an option bit. See option byte sec-
tion for more details.
HALT
INSTRUCTION
[MCCSR.OIE=0]
2. Peripheral clocked with an external clock source
can still be active.
FETCH
VECTOR
3. Only some specific interrupts can exit the MCU
from HALT mode (such as external interrupt). Re-
fer to Table 8, “Interrupt Mapping,” on page 36 for
more details.
4. Before servicing an interrupt, the CC register is
pushed on the stack. The I[1:0] bits of the CC reg-
ister are set to the current software priority level of
the interrupt routine and recovered when the CC
register is popped.
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ST72324
POWER SAVING MODES (Cont’d)
8.4.2.1 Halt Mode Recommendations
– The opcode for the HALT instruction is 0x8E. To
avoid an unexpected HALT instruction due to a
program counter failure, it is advised to clear all
occurrences of the data value 0x8E from memo-
ry. For example, avoid defining a constant in
ROM with the value 0x8E.
– Make sure that an external event is available to
wake up the microcontroller from Halt mode.
– When using an external interrupt to wake up the
microcontroller, reinitialize the corresponding I/O
as “Input Pull-up with Interrupt” before executing
the HALT instruction. The main reason for this is
that the I/O may be wrongly configured due to ex-
ternal interference or by an unforeseen logical
condition.
– As the HALT instruction clears the interrupt mask
in the CC register to allow interrupts, the user
may choose to clear all pending interrupt bits be-
fore executing the HALT instruction. This avoids
entering other peripheral interrupt routines after
executing the external interrupt routine corre-
sponding to the wake-up event (reset or external
interrupt).
– For the same reason, reinitialize the level sensi-
tiveness of each external interrupt as a precau-
tionary measure.
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ST72324
9 I/O PORTS
9.1 INTRODUCTION
Each pin can independently generate an interrupt
request. The interrupt sensitivity is independently
programmable using the sensitivity bits in the
EICR register.
The I/O ports offer different functional modes:
– transfer of data through digital inputs and outputs
and for specific pins:
Each external interrupt vector is linked to a dedi-
cated group of I/O port pins (see pinout description
and interrupt section). If several input pins are se-
lected simultaneously as interrupt sources, these
are first detected according to the sensitivity bits in
the EICR register and then logically ORed.
– external interrupt generation
– alternate signal input/output for the on-chip pe-
ripherals.
An I/O port contains up to 8 pins. Each pin can be
programmed independently as digital input (with or
without interrupt generation) or digital output.
The external interrupts are hardware interrupts,
which means that the request latch (not accessible
directly by the application) is automatically cleared
when the corresponding interrupt vector is
fetched. To clear an unwanted pending interrupt
by software, the sensitivity bits in the EICR register
must be modified.
9.2 FUNCTIONAL DESCRIPTION
Each port has 2 main registers:
– Data Register (DR)
– Data Direction Register (DDR)
and one optional register:
– Option Register (OR)
9.2.2 Output Modes
The output configuration is selected by setting the
corresponding DDR register bit. In this case, writ-
ing the DR register applies this digital value to the
I/O pin through the latch. Then reading the DR reg-
ister returns the previously stored value.
Each I/O pin may be programmed using the corre-
sponding register bits in the DDR and OR regis-
ters: bit X corresponding to pin X of the port. The
same correspondence is used for the DR register.
Two different output modes can be selected by
software through the OR register: Output push-pull
and open-drain.
The following description takes into account the
OR register, (for specific ports which do not pro-
vide this register refer to the I/O Port Implementa-
tion section). The generic I/O block diagram is
shown in Figure 29
DR register value and output pin status:
DR
0
Push-pull
Open-drain
Vss
V
9.2.1 Input Modes
SS
1
V
Floating
DD
The input configuration is selected by clearing the
corresponding DDR register bit.
9.2.3 Alternate Functions
In this case, reading the DR register returns the
digital value applied to the external I/O pin.
When an on-chip peripheral is configured to use a
pin, the alternate function is automatically select-
ed. This alternate function takes priority over the
standard I/O programming.
Different input modes can be selected by software
through the OR register.
Notes:
When the signal is coming from an on-chip periph-
eral, the I/O pin is automatically configured in out-
put mode (push-pull or open drain according to the
peripheral).
1. Writing the DR register modifies the latch value
but does not affect the pin status.
2. When switching from input to output mode, the
DR register has to be written first to drive the cor-
rect level on the pin as soon as the port is config-
ured as an output.
When the signal is going to an on-chip peripheral,
the I/O pin must be configured in input mode. In
this case, the pin state is also digitally readable by
addressing the DR register.
3. Do not use read/modify/write instructions (BSET
or BRES) to modify the DR register
External interrupt function
Note: Input pull-up configuration can cause unex-
pected value at the input of the alternate peripheral
input. When an on-chip peripheral use a pin as in-
put and output, this pin has to be configured in in-
put floating mode.
When an I/O is configured as Input with Interrupt,
an event on this I/O can generate an external inter-
rupt request to the CPU.
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ST72324
I/O PORTS (Cont’d)
Figure 29. I/O Port General Block Diagram
ALTERNATE
OUTPUT
1
0
REGISTER
ACCESS
P-BUFFER
(see table below)
V
DD
ALTERNATE
ENABLE
PULL-UP
(see table below)
DR
DDR
OR
V
DD
PULL-UP
CONDITION
PAD
If implemented
OR SEL
DDR SEL
DR SEL
N-BUFFER
DIODES
(see table below)
ANALOG
INPUT
CMOS
SCHMITT
TRIGGER
1
0
ALTERNATE
INPUT
EXTERNAL
INTERRUPT
SOURCE (ei )
x
Table 10. I/O Port Mode Options
Configuration Mode
Diodes
Pull-Up
P-Buffer
to V
to V
SS
DD
Floating with/without Interrupt
Input
Off
On
Off
Pull-up with/without Interrupt
On
Push-pull
On
Off
NI
On
Off
NI
Output
Open Drain (logic level)
True Open Drain
NI (see note)
Legend: NI - not implemented
Off - implemented not activated
On - implemented and activated
Note: The diode to V is not implemented in the
DD
true open drain pads. A local protection between
the pad and V is implemented to protect the de-
SS
vice against positive stress.
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ST72324
I/O PORTS (Cont’d)
Table 11. I/O Port Configurations
Hardware Configuration
DR REGISTER ACCESS
NOT IMPLEMENTED IN
TRUE OPEN DRAIN
I/O PORTS
V
DD
PULL-UP
CONDITION
R
W
R
PU
DR
REGISTER
DATA BUS
PAD
ALTERNATE INPUT
EXTERNAL INTERRUPT
SOURCE (ei )
x
INTERRUPT
CONDITION
ANALOG INPUT
NOT IMPLEMENTED IN
TRUE OPEN DRAIN
I/O PORTS
DR REGISTER ACCESS
V
DD
R
PU
R/W
DR
REGISTER
DATA BUS
PAD
ALTERNATE
ENABLE
ALTERNATE
OUTPUT
NOT IMPLEMENTED IN
TRUE OPEN DRAIN
I/O PORTS
DR REGISTER ACCESS
V
DD
R
PU
R/W
DR
REGISTER
DATA BUS
PAD
ALTERNATE
ENABLE
ALTERNATE
OUTPUT
Notes:
1. When the I/O port is in input configuration and the associated alternate function is enabled as an output,
reading the DR register will read the alternate function output status.
2. When the I/O port is in output configuration and the associated alternate function is enabled as an input,
the alternate function reads the pin status given by the DR register content.
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ST72324
I/O PORTS (Cont’d)
CAUTION: The alternate function must not be ac-
tivated as long as the pin is configured as input
with interrupt, in order to avoid generating spurious
interrupts.
Figure 30. Interrupt I/O Port State Transitions
01
00
10
11
Analog alternate function
INPUT
floating/pull-up
interrupt
INPUT
floating
(reset state)
OUTPUT
open-drain
OUTPUT
push-pull
When the pin is used as an ADC input, the I/O
must be configured as floating input. The analog
multiplexer (controlled by the ADC registers)
switches the analog voltage present on the select-
ed pin to the common analog rail which is connect-
ed to the ADC input.
= DDR, OR
XX
9.4 LOW POWER MODES
It is recommended not to change the voltage level
or loading on any port pin while conversion is in
progress. Furthermore it is recommended not to
have clocking pins located close to a selected an-
alog pin.
Mode
WAIT
HALT
Description
No effect on I/O ports. External interrupts
cause the device to exit from WAIT mode.
No effect on I/O ports. External interrupts
cause the device to exit from HALT mode.
WARNING: The analog input voltage level must
be within the limits stated in the absolute maxi-
mum ratings.
9.5 INTERRUPTS
9.3 I/O PORT IMPLEMENTATION
The external interrupt event generates an interrupt
if the corresponding configuration is selected with
DDR and OR registers and the interrupt mask in
the CC register is not active (RIM instruction).
The hardware implementation on each I/O port de-
pends on the settings in the DDR and OR registers
and specific feature of the I/O port such as ADC In-
put or true open drain.
Enable Exit
Control from
Exit
from
Halt
Event
Flag
Interrupt Event
Switching these I/O ports from one state to anoth-
er should be done in a sequence that prevents un-
wanted side effects. Recommended safe transi-
tions are illustrated in Figure 30 Other transitions
are potentially risky and should be avoided, since
they are likely to present unwanted side-effects
such as spurious interrupt generation.
Bit
Wait
External interrupt on
selected external
event
DDRx
ORx
-
Yes
Yes
48/163
1
ST72324
I/O PORTS (Cont’d)
9.5.1 I/O Port Implementation
The I/O port register configurations are summa-
rised as follows.
PA3, PB3, PF2 (without pull-up)
MODE
floating input
DDR
OR
0
Standard Ports
0
0
1
1
floating interrupt input
open drain output
push-pull output
1
PA5:4, PC7:0, PD5:0,
PE1:0, PF7:6, 4
0
1
MODE
DDR
OR
0
floating input
pull-up input
0
0
1
1
1
True Open Drain Ports
PA7:6
open drain output
push-pull output
0
1
MODE
floating input
DDR
0
1
Interrupt Ports
open drain (high sink ports)
PB4, PB2:0, PF1:0 (with pull-up)
MODE
floating input
DDR
OR
0
0
0
1
1
pull-up interrupt input
open drain output
push-pull output
1
0
1
Table 12. Port Configuration
Input
floating
Output
Port
Port A
Port B
Pin name
PA7:6
OR = 0
OR = 1
OR = 0
OR = 1
true open-drain
PA5:4
PA3
floating
floating
floating
floating
floating
floating
floating
floating
floating
floating
pull-up
open drain
open drain
open drain
open drain
open drain
open drain
open drain
open drain
open drain
open drain
push-pull
push-pull
push-pull
push-pull
push-pull
push-pull
push-pull
push-pull
push-pull
push-pull
floating interrupt
floating interrupt
pull-up interrupt
pull-up
PB3
PB4, PB2:0
PC7:0
PD5:0
PE1:0
PF7:6, 4
PF2
Port C
Port D
Port E
pull-up
pull-up
pull-up
Port F
floating interrupt
pull-up interrupt
PF1:0
49/163
1
ST72324
I/O PORTS (Cont’d)
Table 13. I/O Port Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
Reset Value
of all I/O port registers
0
0
0
0
0
0
0
0
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
0010h
0011h
PADR
PADDR
PAOR
PBDR
PBDDR
PBOR
PCDR
PCDDR
PCOR
PDDR
PDDDR
PDOR
PEDR
MSB
MSB
MSB
MSB
MSB
MSB
LSB
LSB
LSB
LSB
LSB
LSB
PEDDR
PEOR
PFDR
PFDDR
PFOR
50/163
1
ST72324
10 ON-CHIP PERIPHERALS
10.1 WATCHDOG TIMER (WDG)
10.1.1 Introduction
If the watchdog is activated (the WDGA bit is set)
and when the 7-bit timer (bits T[6:0]) rolls over
from 40h to 3Fh (T6 becomes cleared), it initiates
a reset cycle pulling low the reset pin for typically
500ns.
The Watchdog timer is used to detect the occur-
rence of a software fault, usually generated by ex-
ternal interference or by unforeseen logical condi-
tions, which causes the application program to
abandon its normal sequence. The Watchdog cir-
cuit generates an MCU reset on expiry of a pro-
grammed time period, unless the program refresh-
es the counter’s contents before the T6 bit be-
comes cleared.
The application program must write in the
WDGCR register at regular intervals during normal
operation to prevent an MCU reset. This down-
counter is free-running: it counts down even if the
watchdog is disabled. The value to be stored in the
WDGCR register must be between FFh and C0h:
10.1.2 Main Features
■ Programmable free-running downcounter
■ Programmable reset
– The WDGA bit is set (watchdog enabled)
– The T6 bit is set to prevent generating an imme-
diate reset
■ Reset (if watchdog activated) when the T6 bit
– The T[5:0] bits contain the number of increments
which represents the time delay before the
watchdog produces a reset (see Figure 32. Ap-
proximate Timeout Duration). The timing varies
between a minimum and a maximum value due
to the unknown status of the prescaler when writ-
ing to the WDGCR register (see Figure 33).
reaches zero
■ Optional
reset
on
HALT
instruction
(configurable by option byte)
■ Hardware Watchdog selectable by option byte
10.1.3 Functional Description
Following a reset, the watchdog is disabled. Once
activated it cannot be disabled, except by a reset.
The counter value stored in the Watchdog Control
register (WDGCR bits T[6:0]), is decremented
every 16384 f
cycles (approx.), and the
The T6 bit can be used to generate a software re-
set (the WDGA bit is set and the T6 bit is cleared).
OSC2
length of the timeout period can be programmed
by the user in 64 increments.
If the watchdog is activated, the HALT instruction
will generate a Reset.
Figure 31. Watchdog Block Diagram
RESET
f
OSC2
MCC/RTC
WATCHDOG CONTROL REGISTER (WDGCR)
T5
DIV 64
WDGA T6
T1
T0
T4
T2
T3
6-BIT DOWNCOUNTER (CNT)
12-BIT MCC
RTC COUNTER
WDG PRESCALER
DIV 4
TB[1:0] bits
(MCCSR
Register)
MSB
LSB
0
6 5
11
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1
ST72324
WATCHDOG TIMER (Cont’d)
10.1.4 How to Program the Watchdog Timeout
more precision is needed, use the formulae in Fig-
ure 33.
Figure 32 shows the linear relationship between
the 6-bit value to be loaded in the Watchdog Coun-
ter (CNT) and the resulting timeout duration in mil-
liseconds. This can be used for a quick calculation
without taking the timing variations into account. If
Caution: When writing to the WDGCR register, al-
ways write 1 in the T6 bit to avoid generating an
immediate reset.
Figure 32. Approximate Timeout Duration
3F
38
30
28
20
18
10
08
00
1.5
18
34
50
65
82
98
114
128
Watchdog timeout (ms) @ 8 MHz. f
OSC2
52/163
1
ST72324
WATCHDOG TIMER (Cont’d)
Figure 33. Exact Timeout Duration (t
and t
)
max
min
WHERE:
t
t
t
= (LSB + 128) x 64 x t
min0
OSC2
= 16384 x t
= 125ns if f
max0
OSC2
OSC2
=8 MHz
OSC2
CNT = Value of T[5:0] bits in the WDGCR register (6 bits)
MSB and LSB are values from the table below depending on the timebase selected by the TB[1:0] bits
in the MCCSR register
TB1 Bit
TB0 Bit
Selected MCCSR
Timebase
MSB
LSB
(MCCSR Reg.) (MCCSR Reg.)
0
0
1
1
0
1
0
1
2ms
4ms
4
8
59
53
35
54
10ms
25ms
20
49
To calculate the minimum Watchdog Timeout (t ):
min
MSB
4
IF
THEN
ELSE
-------------
CNT <
t
= t
+ 16384 × CNT × t
min
min0
osc2
4CNT
----------------
4CNT
----------------
⎛
⎞
⎠
t
= t
+ 16384 × CNT –
+ (192 + LSB) × 64 ×
× t
min
min0
⎝
osc2
MSB
MSB
To calculate the maximum Watchdog Timeout (t
):
max
MSB
4
IF
-------------
THEN
ELSE
CNT ≤
t
= t
+ 16384 × CNT × t
max
max0
osc2
4CNT
----------------
4CNT
----------------
⎛
⎞
t
= t
+ 16384 × CNT –
+ (192 + LSB) × 64 ×
× t
max
max0
osc2
⎝
⎠
MSB
MSB
Note: In the above formulae, division results must be rounded down to the next integer value.
Example:
With 2ms timeout selected in MCCSR register
Min. Watchdog
Timeout (ms)
Max. Watchdog
Timeout (ms)
Value of T[5:0] Bits in
WDGCR Register (Hex.)
t
t
min
max
00
3F
1.496
128
2.048
128.552
53/163
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ST72324
WATCHDOG TIMER (Cont’d)
10.1.5 Low Power Modes
Mode Description
SLOW No effect on Watchdog.
WAIT No effect on Watchdog.
OIE bit in
MCCSR
register
WDGHALT bit
in Option
Byte
No Watchdog reset is generated. The MCU enters Halt mode. The Watch-
dog counter is decremented once and then stops counting and is no longer
able to generate a watchdog reset until the MCU receives an external inter-
rupt or a reset.
0
0
If an external interrupt is received, the Watchdog restarts counting after 256
or 4096 CPU clocks. If a reset is generated, the Watchdog is disabled (reset
state) unless Hardware Watchdog is selected by option byte. For applica-
tion recommendations see Section 10.1.7 below.
HALT
0
1
1
x
A reset is generated.
No reset is generated. The MCU enters Active Halt mode. The Watchdog
counter is not decremented. It stop counting. When the MCU receives an
oscillator interrupt or external interrupt, the Watchdog restarts counting im-
mediately. When the MCU receives a reset the Watchdog restarts counting
after 256 or 4096 CPU clocks.
10.1.6 Hardware Watchdog Option
10.1.9 Register Description
If Hardware Watchdog is selected by option byte,
the watchdog is always active and the WDGA bit in
the WDGCR is not used. Refer to the Option Byte
description.
CONTROL REGISTER (WDGCR)
Read/Write
Reset Value: 0111 1111 (7Fh)
10.1.7 Using Halt Mode with the WDG
(WDGHALT option)
7
0
WDGA T6
T5
T4
T3
T2
T1
T0
The following recommendation applies if Halt
mode is used when the watchdog is enabled.
– Before executing the HALT instruction, refresh
the WDG counter, to avoid an unexpected WDG
reset immediately after waking up the microcon-
troller.
Bit 7 = WDGA Activation bit.
This bit is set by software and only cleared by
hardware after a reset. When WDGA = 1, the
watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled
10.1.8 Interrupts
None.
Note: This bit is not used if the hardware watch-
dog option is enabled by option byte.
Bit 6:0 = T[6:0] 7-bit counter (MSB to LSB).
These bits contain the value of the watchdog
counter. It is decremented every 16384 f
cles (approx.). A reset is produced when it rolls
over from 40h to 3Fh (T6 becomes cleared).
cy-
OSC2
54/163
1
ST72324
Table 14. Watchdog Timer Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
WDGCR
Reset Value
WDGA
0
T6
1
T5
1
T4
1
T3
1
T2
1
T1
1
T0
1
002Ah
55/163
1
ST72324
10.2
MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK AND BEEPER (MCC/RTC)
The Main Clock Controller consists of three differ-
ent functions:
external devices. It is controlled by the MCO bit in
the MCCSR register.
CAUTION: When selected, the clock out pin sus-
pends the clock during ACTIVE-HALT mode.
■
a programmable CPU clock prescaler
■
a clock-out signal to supply external devices
10.2.3
Real Time Clock Timer (RTC)
■
a real time clock timer with interrupt capability
The counter of the real time clock timer allows an
interrupt to be generated based on an accurate
real time clock. Four different time bases depend-
Each function can be used independently and si-
multaneously.
10.2.1
Programmable CPU Clock Prescaler
ing directly on f
are available. The whole
OSC2
functionality is controlled by four bits of the MCC-
SR register: TB[1:0], OIE and OIF.
The programmable CPU clock prescaler supplies
the clock for the ST7 CPU and its internal periph-
erals. It manages SLOW power saving mode (See
Section 8.2 SLOW MODE for more details).
When the RTC interrupt is enabled (OIE bit set),
the ST7 enters ACTIVE-HALT mode when the
HALT instruction is executed. See Section 8.4 AC-
TIVE-HALT AND HALT MODES for more details.
The prescaler selects the f
main clock frequen-
CPU
cy and is controlled by three bits in the MCCSR
register: CP[1:0] and SMS.
10.2.4
Beeper
10.2.2
Clock-out Capability
The clock-out capability is an alternate function of
an I/O port pin that outputs the f clock to drive
The beep function is controlled by the MCCBCR
register. It can output three selectable frequencies
on the BEEP pin (I/O port alternate function).
CPU
Figure 34.
Main Clock Controller (MCC/RTC) Block Diagram
BC1 BC0
MCCBCR
BEEP
MCO
BEEP SIGNAL
SELECTION
12-BIT MCC RTC
COUNTER
TO
DIV 64
WATCHDOG
TIMER
MCO CP1 CP0 SMS TB1 TB0 OIE OIF
MCCSR
MCC/RTC INTERRUPT
fCPU
fOSC2
DIV 2, 4, 8, 16
1
0
CPU CLOCK
TO CPU AND
PERIPHERALS
56/163
1
ST72324
MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont’d)
10.2.5
Low Power Modes
Bit 6:5 = CP[1:0] CPU clock prescaler
Mode
Description
These bits select the CPU clock prescaler which is
applied in the different slow modes. Their action is
conditioned by the setting of the SMS bit. These
two bits are set and cleared by software
No effect on MCC/RTC peripheral.
MCC/RTC interrupt cause the device to exit
from WAIT mode.
WAIT
No effect on MCC/RTC counter (OIE bit is
f
in SLOW mode
CP1
CP0
ACTIVE- set), the registers are frozen.
CPU
HALT
MCC/RTC interrupt cause the device to exit
from ACTIVE-HALT mode.
f
f
f
/ 2
/ 4
0
0
1
1
0
1
0
1
OSC2
OSC2
OSC2
MCC/RTC counter and registers are frozen.
MCC/RTC operation resumes when the
MCU is woken up by an interrupt with “exit
from HALT” capability.
/ 8
HALT
f
/ 16
OSC2
10.2.6
Bit 4 = SMS Slow mode select
This bit is set and cleared by software.
0: Normal mode. f = f
Interrupts
The MCC/RTC interrupt event generates an inter-
rupt if the OIE bit of the MCCSR register is set and
the interrupt mask in the CC register is not active
(RIM instruction).
OSC2
CPU
1: Slow mode. f
is given by CP1, CP0
CPU
See Section 8.2 SLOW MODE and Section 10.2
MAIN CLOCK CONTROLLER WITH REAL TIME
CLOCK AND BEEPER (MCC/RTC) for more de-
tails.
Enable Exit
Control from
Exit
from
Halt
Event
Flag
Interrupt Event
Bit
Wait
Time base overflow
event
1)
Bit 3:2 = TB[1:0] Time base control
OIF
OIE
Yes
No
These bits select the programmable divider time
base. They are set and cleared by software.
Note:
The MCC/RTC interrupt wakes up the MCU from
ACTIVE-HALT mode, not from HALT mode.
Time Base
Counter
TB1 TB0
Prescaler
f
=4MHz
f
=8MHz
OSC2
OSC2
16000
32000
80000
200000
4ms
2ms
4ms
0
0
1
1
0
1
0
1
8ms
20ms
50ms
10.2.7
Register Description
10ms
25ms
MCC CONTROL/STATUS REGISTER (MCCSR)
Read/Write
Reset Value: 0000 0000 (00h
)
A modification of the time base is taken into ac-
count at the end of the current period (previously
set) to avoid an unwanted time shift. This allows to
use this time base as a real time clock.
7
0
MCO CP1 CP0 SMS TB1 TB0 OIE OIF
Bit 1 = OIE Oscillator interrupt enable
This bit set and cleared by software.
0: Oscillator interrupt disabled
Bit 7 = MCO Main clock out selection
This bit enables the MCO alternate function on the
PF0 I/O port. It is set and cleared by software.
0: MCO alternate function disabled (I/O pin free for
general-purpose I/O)
1: Oscillator interrupt enabled
This interrupt can be used to exit from ACTIVE-
HALT mode.
1: MCO alternate function enabled (f
port)
on I/O
CPU
When this bit is set, calling the ST7 software HALT
instruction enters the ACTIVE-HALT power saving
mode
.
Note: To reduce power consumption, the MCO
function is not active in ACTIVE-HALT mode.
57/163
1
ST72324
MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont’d)
MCC BEEP CONTROL REGISTER (MCCBCR)
Bit 0 = OIF Oscillator interrupt flag
This bit is set by hardware and cleared by software
reading the MCCSR register. It indicates when set
that the main oscillator has reached the selected
elapsed time (TB1:0).
Read/Write
Reset Value: 0000 0000 (00h)
7
0
0: Timeout not reached
1: Timeout reached
0
0
0
0
0
0
BC1 BC0
CAUTION: The BRES and BSET instructions
must not be used on the MCCSR register to avoid
unintentionally clearing the OIF bit.
Bit 7:2 = Reserved, must be kept cleared.
Bit 1:0 = BC[1:0] Beep control
These 2 bits select the PF1 pin beep capability.
BC1
BC0
Beep mode with f
=8MHz
OSC2
0
0
1
1
0
1
0
1
Off
~2-KHz
Output
Beep signal
~50% duty cycle
~1-KHz
~500-Hz
The beep output signal is available in ACTIVE-
HALT mode but has to be disabled to reduce the
consumption.
Table 15. Main Clock Controller Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
SICSR
Reset Value
AVDIE
0
AVDF
0
LVDRF
x
WDGRF
x
002Bh
002Ch
002Dh
0
0
0
0
MCCSR
Reset Value
MCO
0
CP1
0
CP0
0
SMS
0
TB1
0
TB0
0
OIE
0
OIF
0
MCCBCR
Reset Value
BC1
0
BC0
0
0
0
0
0
0
0
58/163
1
ST72324
10.3 16-BIT TIMER
10.3.1 Introduction
When reading an input signal on a non-bonded
pin, the value will always be ‘1’.
The timer consists of a 16-bit free-running counter
driven by a programmable prescaler.
10.3.3 Functional Description
10.3.3.1 Counter
It may be used for a variety of purposes, including
pulse length measurement of up to two input sig-
nals (input capture) or generation of up to two out-
put waveforms (output compare and PWM).
The main block of the Programmable Timer is a
16-bit free running upcounter and its associated
16-bit registers. The 16-bit registers are made up
of two 8-bit registers called high & low.
Pulse lengths and waveform periods can be mod-
ulated from a few microseconds to several milli-
seconds using the timer prescaler and the CPU
clock prescaler.
Counter Register (CR):
– Counter High Register (CHR) is the most sig-
nificant byte (MS Byte).
Some ST7 devices have two on-chip 16-bit timers.
They are completely independent, and do not
share any resources. They are synchronized after
a MCU reset as long as the timer clock frequen-
cies are not modified.
– Counter Low Register (CLR) is the least sig-
nificant byte (LS Byte).
Alternate Counter Register (ACR)
– Alternate Counter High Register (ACHR) is
the most significant byte (MS Byte).
This description covers one or two 16-bit timers. In
ST7 devices with two timers, register names are
prefixed with TA (Timer A) or TB (Timer B).
– Alternate Counter Low Register (ACLR) is the
least significant byte (LS Byte).
These two read-only 16-bit registers contain the
same value but with the difference that reading the
ACLR register does not clear the TOF bit (Timer
overflow flag), located in the Status register, (SR),
(see note at the end of paragraph titled 16-bit read
sequence).
10.3.2 Main Features
■ Programmableprescaler:fCPU dividedby2,4or8.
■ Overflow status flag and maskable interrupt
■ External clock input (must be at least 4 times
slowerthantheCPUclockspeed)withthechoice
of active edge
■ 1 or 2 Output Compare functions each with:
– 2 dedicated 16-bit registers
Writing in the CLR register or ACLR register resets
the free running counter to the FFFCh value.
Both counters have a reset value of FFFCh (this is
the only value which is reloaded in the 16-bit tim-
er). The reset value of both counters is also
FFFCh in One Pulse mode and PWM mode.
– 2 dedicated programmable signals
– 2 dedicated status flags
– 1 dedicated maskable interrupt
■ 1 or 2 Input Capture functions each with:
– 2 dedicated 16-bit registers
The timer clock depends on the clock control bits
of the CR2 register, as illustrated in Table 16 Clock
Control Bits. The value in the counter register re-
peats every 131072, 262144 or 524288 CPU clock
cycles depending on the CC[1:0] bits.
– 2 dedicated active edge selection signals
– 2 dedicated status flags
The timer frequency can be f
or an external frequency.
/2, f
/4, f
/8
CPU
CPU
CPU
– 1 dedicated maskable interrupt
■ Pulse width modulation mode (PWM)
■ One pulse mode
Caution: In Flash devices, Timer A functionality
has the following restrictions:
■ Reduced Power Mode
■ 5 alternate functions on I/O ports (ICAP1, ICAP2,
– TAOC2HR and TAOC2LR registers are write
only
OCMP1, OCMP2, EXTCLK)*
– Input Capture 2 is not implemented
The Block Diagram is shown in Figure 35.
– The corresponding interrupts cannot be used
(ICF2, OCF2 forced by hardware to zero)
*Note: Some timer pins may not be available (not
bonded) in some ST7 devices. Refer to the device
pin out description.
59/163
1
ST72324
16-BIT TIMER (Cont’d)
Figure 35. Timer Block Diagram
ST7 INTERNAL BUS
f
CPU
MCU-PERIPHERAL INTERFACE
8 low
8-bit
8 high
8
8
8
8
8
8
8
8
buffer
EXEDG
16
INPUT
CAPTURE
REGISTER
INPUT
CAPTURE
REGISTER
OUTPUT
COMPARE
REGISTER
OUTPUT
COMPARE
REGISTER
1/2
1/4
1/8
COUNTER
REGISTER
1
1
2
2
ALTERNATE
COUNTER
REGISTER
EXTCLK
pin
16
16
16
CC[1:0]
TIMER INTERNAL BUS
16 16
OVERFLOW
DETECT
EDGE DETECT
CIRCUIT1
OUTPUT COMPARE
CIRCUIT
ICAP1
pin
CIRCUIT
6
EDGE DETECT
CIRCUIT2
ICAP2
pin
OCMP1
pin
LATCH1
LATCH2
0
ICF1 OCF1 TOF ICF2 OCF2
0
TIMD
(Control/Status Register)
OCMP2
pin
CSR
EXEDG
ICIE OCIE TOIE FOLV2 FOLV1OLVL2 IEDG1 OLVL1
OC1E
OPM PWM CC1 CC0 IEDG2
OC2E
(Control Register 1) CR1
(Control Register 2) CR2
(See note)
Note: If IC, OC and TO interrupt requests have separate vectors
then the last OR is not present (See device Interrupt Vector Table)
TIMER INTERRUPT
60/163
1
ST72324
16-BIT TIMER (Cont’d)
16-bit read sequence: (from either the Counter
Register or the Alternate Counter Register).
Clearing the overflow interrupt request is done in
two steps:
1. Reading the SR register while the TOF bit is set.
2. An access (read or write) to the CLR register.
Beginning of the sequence
Read
LS Byte
Notes: The TOF bit is not cleared by accesses to
ACLR register. The advantage of accessing the
ACLR register rather than the CLR register is that
it allows simultaneous use of the overflow function
and reading the free running counter at random
times (for example, to measure elapsed time) with-
out the risk of clearing the TOF bit erroneously.
MS Byte
At t0
is buffered
Other
instructions
Returns the buffered
LS Byte value at t0
Read
LS Byte
At t0 +∆t
The timer is not affected by WAIT mode.
In HALT mode, the counter stops counting until the
mode is exited. Counting then resumes from the
previous count (MCU awakened by an interrupt) or
from the reset count (MCU awakened by a Reset).
Sequence completed
The user must read the MS Byte first, then the LS
Byte value is buffered automatically.
This buffered value remains unchanged until the
16-bit read sequence is completed, even if the
user reads the MS Byte several times.
10.3.3.2 External Clock
The external clock (where available) is selected if
CC0=1 and CC1=1 in the CR2 register.
After a complete reading sequence, if only the
CLR register or ACLR register are read, they re-
turn the LS Byte of the count value at the time of
the read.
The status of the EXEDG bit in the CR2 register
determines the type of level transition on the exter-
nal clock pin EXTCLK that will trigger the free run-
ning counter.
Whatever the timer mode used (input capture, out-
put compare, one pulse mode or PWM mode) an
overflow occurs when the counter rolls over from
FFFFh to 0000h then:
The counter is synchronized with the falling edge
of the internal CPU clock.
A minimum of four falling edges of the CPU clock
must occur between two consecutive active edges
of the external clock; thus the external clock fre-
quency must be less than a quarter of the CPU
clock frequency.
– The TOF bit of the SR register is set.
– A timer interrupt is generated if:
– TOIE bit of the CR1 register is set and
– I bit of the CC register is cleared.
If one of these conditions is false, the interrupt re-
mains pending to be issued as soon as they are
both true.
61/163
1
ST72324
16-BIT TIMER (Cont’d)
Figure 36. Counter Timing Diagram, internal clock divided by 2
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
FFFD FFFE FFFF 0000 0001 0002 0003
COUNTER REGISTER
TIMER OVERFLOW FLAG (TOF)
Figure 37. Counter Timing Diagram, internal clock divided by 4
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
FFFC
FFFD
0000
0001
COUNTER REGISTER
TIMER OVERFLOW FLAG (TOF)
Figure 38. Counter Timing Diagram, internal clock divided by 8
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
0000
FFFC
FFFD
COUNTER REGISTER
TIMER OVERFLOW FLAG (TOF)
Note: The MCU is in reset state when the internal reset signal is high, when it is low the MCU is running.
62/163
1
ST72324
16-BIT TIMER (Cont’d)
10.3.3.3 Input Capture
When an input capture occurs:
In this section, the index, i, may be 1 or 2 because
there are 2 input capture functions in the 16-bit
timer.
– ICFi bit is set.
– The ICiR register contains the value of the free
running counter on the active transition on the
ICAPi pin (see Figure 40).
The two 16-bit input capture registers (IC1R and
IC2R) are used to latch the value of the free run-
ning counter after a transition is detected on the
ICAPi pin (see figure 5).
– A timer interrupt is generated if the ICIE bit is set
and the I bit is cleared in the CC register. Other-
wise, the interrupt remains pending until both
conditions become true.
MS Byte
LS Byte
ICiR
ICiHR
ICiLR
Clearing the Input Capture interrupt request (i.e.
clearing the ICFi bit) is done in two steps:
ICiR register is a read-only register.
1. Reading the SR register while the ICFi bit is set.
2. An access (read or write) to the ICiLR register.
The active transition is software programmable
through the IEDGi bit of Control Registers (CRi).
Timing resolution is one count of the free running
Notes:
counter: (f
/CC[1:0]).
CPU
1. After reading the ICiHR register, transfer of
input capture data is inhibited and ICFi will
never be set until the ICiLR register is also
read.
Procedure:
To use the input capture function select the follow-
ing in the CR2 register:
2. The ICiR register contains the free running
counter value which corresponds to the most
recent input capture.
– Select the timer clock (CC[1:0]) (see Table 16
Clock Control Bits).
3. The 2 input capture functions can be used
together even if the timer also uses the 2 output
compare functions.
– Select the edge of the active transition on the
ICAP2 pin with the IEDG2 bit (the ICAP2 pin
must be configured as floating input or input with
pull-up without interrupt if this configuration is
available).
4. In One pulse Mode and PWM mode only Input
Capture 2 can be used.
And select the following in the CR1 register:
5. The alternate inputs (ICAP1 & ICAP2) are
always directly connected to the timer. So any
transitions on these pins activates the input
capture function.
– Set the ICIE bit to generate an interrupt after an
input capture coming from either the ICAP1 pin
or the ICAP2 pin
Moreover if one of the ICAPi pins is configured
as an input and the second one as an output,
an interrupt can be generated if the user tog-
gles the output pin and if the ICIE bit is set.
This can be avoided if the input capture func-
tion i is disabled by reading the ICiHR (see note
1).
– Select the edge of the active transition on the
ICAP1 pin with the IEDG1 bit (the ICAP1pin must
be configured as floating input or input with pull-
up without interrupt if this configuration is availa-
ble).
6. The TOF bit can be used with interrupt genera-
tion in order to measure events that go beyond
the timer range (FFFFh).
7. In Flash devices, the ICAP2 registers
(TAIC2HR, TAIC2LR) are not available on
Timer A. The corresponding interrupts cannot
be used (ICF2 is forced by hardware to 0).
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1
ST72324
16-BIT TIMER (Cont’d)
Figure 39. Input Capture Block Diagram
ICAP1
pin
(Control Register 1) CR1
EDGE DETECT
CIRCUIT2
EDGE DETECT
CIRCUIT1
ICIE
IEDG1
ICAP2
pin
(Status Register) SR
ICF1
ICF2
0
0
0
IC2R Register
IC1R Register
(Control Register 2) CR2
16-BIT
16-BIT FREE RUNNING
COUNTER
IEDG2
CC0
CC1
Figure 40. Input Capture Timing Diagram
TIMER CLOCK
FF01
FF02
FF03
COUNTER REGISTER
ICAPi PIN
ICAPi FLAG
FF03
ICAPi REGISTER
Note: The rising edge is the active edge.
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1
ST72324
16-BIT TIMER (Cont’d)
10.3.3.4 Output Compare
– The OCMPi pin takes OLVLi bit value (OCMPi
pin latch is forced low during reset).
In this section, the index, i, may be 1 or 2 because
there are 2 output compare functions in the 16-bit
timer.
– A timer interrupt is generated if the OCIE bit is
set in the CR1 register and the I bit is cleared in
the CC register (CC).
This function can be used to control an output
waveform or indicate when a period of time has
elapsed.
The OCiR register value required for a specific tim-
ing application can be calculated using the follow-
ing formula:
When a match is found between the Output Com-
pare register and the free running counter, the out-
put compare function:
– Assigns pins with a programmable value if the
∆t f
* CPU
PRESC
∆ OCiR =
OCiE bit is set
– Sets a flag in the status register
– Generates an interrupt if enabled
Where:
∆t
= Output compare period (in seconds)
= CPU clock frequency (in hertz)
Two 16-bit registers Output Compare Register 1
(OC1R) and Output Compare Register 2 (OC2R)
contain the value to be compared to the counter
register each timer clock cycle.
f
CPU
= Timer prescaler factor (2, 4 or 8 de-
pending on CC[1:0] bits, see Table 16
Clock Control Bits)
PRESC
MS Byte
LS Byte
OCiR
OCiHR
OCiLR
If the timer clock is an external clock, the formula
is:
These registers are readable and writable and are
not affected by the timer hardware. A reset event
changes the OCiR value to 8000h.
∆ OCiR = ∆t f
* EXT
Timing resolution is one count of the free running
Where:
counter: (f
).
CC[1:0]
CPU/
∆t
= Output compare period (in seconds)
= External timer clock frequency (in hertz)
f
EXT
Procedure:
To use the output compare function, select the fol-
lowing in the CR2 register:
Clearing the output compare interrupt request (i.e.
clearing the OCFi bit) is done by:
– Set the OCiE bit if an output is needed then the
OCMPi pin is dedicated to the output compare i
signal.
1. Reading the SR register while the OCFi bit is
set.
2. An access (read or write) to the OCiLR register.
– Select the timer clock (CC[1:0]) (see Table 16
Clock Control Bits).
The following procedure is recommended to pre-
vent the OCFi bit from being set between the time
it is read and the write to the OCiR register:
And select the following in the CR1 register:
– Select the OLVLi bit to applied to the OCMPi pins
after the match occurs.
– Write to the OCiHR register (further compares
are inhibited).
– Set the OCIE bit to generate an interrupt if it is
needed.
– Read the SR register (first step of the clearance
of the OCFi bit, which may be already set).
When a match is found between OCRi register
and CR register:
– Write to the OCiLR register (enables the output
compare function and clears the OCFi bit).
– OCFi bit is set.
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ST72324
16-BIT TIMER (Cont’d)
Notes:
6. In Flash devices, the TAOC2HR, TAOC2LR
registers are “write only” in Timer A. The corre-
sponding event cannot be generated (OCF2 is
forced by hardware to 0).
1. After a processor write cycle to the OCiHR reg-
ister, the output compare function is inhibited
until the OCiLR register is also written.
Forced Compare Output capability
2. If the OCiE bit is not set, the OCMPi pin is a
general I/O port and the OLVLi bit will not
appear when a match is found but an interrupt
could be generated if the OCIE bit is set.
When the FOLVi bit is set by software, the OLVLi
bit is copied to the OCMPi pin. The OLVi bit has to
be toggled in order to toggle the OCMPi pin when
it is enabled (OCiE bit=1). The OCFi bit is then not
set by hardware, and thus no interrupt request is
generated.
3. When the timer clock is f
/2, OCFi and
CPU
OCMPi are set while the counter value equals
the OCiR register value (see Figure 42 on page
67). This behaviour is the same in OPM or
PWM mode.
The FOLVLi bits have no effect in both one pulse
mode and PWM mode.
When the timer clock is f
/4, f
/8 or in
CPU
CPU
external clock mode, OCFi and OCMPi are set
while the counter value equals the OCiR regis-
ter value plus 1 (see Figure 43 on page 67).
4. The output compare functions can be used both
for generating external events on the OCMPi
pins even if the input capture mode is also
used.
5. The value in the 16-bit OCiR register and the
OLVi bit should be changed after each suc-
cessful comparison in order to control an output
waveform or establish a new elapsed timeout.
Figure 41. Output Compare Block Diagram
16 BIT FREE RUNNING
OC1E
CC1 CC0
OC2E
COUNTER
(Control Register 2) CR2
16-bit
(Control Register 1) CR1
OUTPUT COMPARE
CIRCUIT
Latch
1
OCIE
FOLV2 FOLV1OLVL2
OLVL1
OCMP1
Pin
16-bit
16-bit
Latch
2
OCMP2
Pin
OC1R Register
OCF1
OCF2
0
0
0
OC2R Register
(Status Register) SR
66/163
1
ST72324
16-BIT TIMER (Cont’d)
Figure 42. Output Compare Timing Diagram, f
=f
/2
TIMER
CPU
INTERNAL CPU CLOCK
TIMER CLOCK
COUNTER REGISTER
2ECF 2ED0 2ED1 2ED2
2ED3
2ED4
2ED3
OUTPUT COMPARE REGISTER i (OCRi)
OUTPUT COMPARE FLAG i (OCFi)
OCMPi PIN (OLVLi=1)
Figure 43. Output Compare Timing Diagram, f
=f
/4
TIMER
CPU
INTERNAL CPU CLOCK
TIMER CLOCK
2ECF 2ED0 2ED1 2ED2
2ED3
2ED4
2ED3
COUNTER REGISTER
OUTPUT COMPARE REGISTER i (OCRi)
COMPARE REGISTER i LATCH
OUTPUT COMPARE FLAG i (OCFi)
OCMPi PIN (OLVLi=1)
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ST72324
16-BIT TIMER (Cont’d)
10.3.3.5 One Pulse Mode
Clearing the Input Capture interrupt request (i.e.
clearing the ICFi bit) is done in two steps:
One Pulse mode enables the generation of a
pulse when an external event occurs. This mode is
selected via the OPM bit in the CR2 register.
1. Reading the SR register while the ICFi bit is set.
2. An access (read or write) to the ICiLR register.
The one pulse mode uses the Input Capture1
function and the Output Compare1 function.
The OC1R register value required for a specific
timing application can be calculated using the fol-
lowing formula:
Procedure:
t f
To use one pulse mode:
* CPU
- 5
OCiR Value =
1. Load the OC1R register with the value corre-
sponding to the length of the pulse (see the for-
mula in the opposite column).
PRESC
Where:
t
= Pulse period (in seconds)
2. Select the following in the CR1 register:
f
= CPU clock frequency (in hertz)
CPU
– Using the OLVL1 bit, select the level to be ap-
plied to the OCMP1 pin after the pulse.
= Timer prescaler factor (2, 4 or 8 depend-
ing on the CC[1:0] bits, see Table 16
Clock Control Bits)
PRESC
– Using the OLVL2 bit, select the level to be ap-
plied to the OCMP1 pin during the pulse.
If the timer clock is an external clock the formula is:
– Select the edge of the active transition on the
ICAP1 pin with the IEDG1 bit (the ICAP1 pin
must be configured as floating input).
OCiR = t fEXT -5
*
Where:
t
3. Select the following in the CR2 register:
= Pulse period (in seconds)
– Set the OC1E bit, the OCMP1 pin is then ded-
icated to the Output Compare 1 function.
f
= External timer clock frequency (in hertz)
EXT
– Set the OPM bit.
When the value of the counter is equal to the value
of the contents of the OC1R register, the OLVL1
bit is output on the OCMP1 pin, (See Figure 44).
– Select the timer clock CC[1:0] (see Table 16
Clock Control Bits).
Notes:
One pulse mode cycle
1. The OCF1 bit cannot be set by hardware in one
pulse mode but the OCF2 bit can generate an
Output Compare interrupt.
ICR1 = Counter
When
OCMP1 = OLVL2
event occurs
2. When the Pulse Width Modulation (PWM) and
One Pulse Mode (OPM) bits are both set, the
PWM mode is the only active one.
on ICAP1
Counter is reset
to FFFCh
3. If OLVL1=OLVL2 a continuous signal will be
seen on the OCMP1 pin.
ICF1 bit is set
When
4. The ICAP1 pin can not be used to perform input
capture. The ICAP2 pin can be used to perform
input capture (ICF2 can be set and IC2R can be
loaded) but the user must take care that the
counter is reset each time a valid edge occurs
on the ICAP1 pin and ICF1 can also generates
interrupt if ICIE is set.
Counter
OCMP1 = OLVL1
= OC1R
Then, on a valid event on the ICAP1 pin, the coun-
ter is initialized to FFFCh and OLVL2 bit is loaded
on the OCMP1 pin, the ICF1 bit is set and the val-
ue FFFDh is loaded in the IC1R register.
5. When one pulse mode is used OC1R is dedi-
cated to this mode. Nevertheless OC2R and
OCF2 can be used to indicate a period of time
has been elapsed but cannot generate an out-
put waveform because the level OLVL2 is dedi-
cated to the one pulse mode.
Because the ICF1 bit is set when an active edge
occurs, an interrupt can be generated if the ICIE
bit is set.
6. In Flash devices, Timer A OCF2 bit is forced by
hardware to 0.
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1
ST72324
16-BIT TIMER (Cont’d)
Figure 44. One Pulse Mode Timing Example
2ED3
01F8
IC1R
FFFC FFFD FFFE
2ED0 2ED1 2ED2
2ED3
FFFC FFFD
01F8
COUNTER
ICAP1
OLVL2
OLVL1
OLVL2
OCMP1
compare1
Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1
Figure 45. Pulse Width Modulation Mode Timing Example with 2 Output Compare Functions
2ED0 2ED1 2ED2
34E2 FFFC
FFFC FFFD FFFE
34E2
COUNTER
OCMP1
OLVL2
OLVL1
OLVL2
compare2
compare1
compare2
Note: OC1R=2ED0h, OC2R=34E2, OLVL1=0, OLVL2= 1
69/163
1
ST72324
16-BIT TIMER (Cont’d)
10.3.3.6 Pulse Width Modulation Mode
If OLVL1=1 and OLVL2=0 the length of the posi-
tive pulse is the difference between the OC2R and
OC1R registers.
Pulse Width Modulation (PWM) mode enables the
generation of a signal with a frequency and pulse
length determined by the value of the OC1R and
OC2R registers.
If OLVL1=OLVL2 a continuous signal will be seen
on the OCMP1 pin.
Pulse Width Modulation mode uses the complete
Output Compare 1 function plus the OC2R regis-
ter, and so this functionality can not be used when
PWM mode is activated.
The OCiR register value required for a specific tim-
ing application can be calculated using the follow-
ing formula:
t * fCPU
- 5
OCiR Value =
In PWM mode, double buffering is implemented on
the output compare registers. Any new values writ-
ten in the OC1R and OC2R registers are taken
into account only at the end of the PWM period
(OC2) to avoid spikes on the PWM output pin
(OCMP1).
PRESC
Where:
t
= Signal or pulse period (in seconds)
= CPU clock frequency (in hertz)
f
CPU
= Timer prescaler factor (2, 4 or 8 depend-
ing on CC[1:0] bits, see Table 16)
PRESC
Procedure
If the timer clock is an external clock the formula is:
To use pulse width modulation mode:
OCiR = t fEXT -5
1. Load the OC2R register with the value corre-
sponding to the period of the signal using the
formula in the opposite column.
*
Where:
t
f
= Signal or pulse period (in seconds)
2. Load the OC1R register with the value corre-
sponding to the period of the pulse if (OLVL1=0
and OLVL2=1) using the formula in the oppo-
site column.
= External timer clock frequency (in hertz)
EXT
The Output Compare 2 event causes the counter
to be initialized to FFFCh (See Figure 45)
3. Select the following in the CR1 register:
Notes:
– Using the OLVL1 bit, select the level to be ap-
plied to the OCMP1 pin after a successful
comparison with the OC1R register.
1. After a write instruction to the OCiHR register,
the output compare function is inhibited until the
OCiLR register is also written.
– Using the OLVL2 bit, select the level to be ap-
plied to the OCMP1 pin after a successful
comparison with the OC2R register.
2. The OCF1 and OCF2 bits cannot be set by
hardware in PWM mode therefore the Output
Compare interrupt is inhibited.
4. Select the following in the CR2 register:
3. The ICF1 bit is set by hardware when the coun-
ter reaches the OC2R value and can produce a
timer interrupt if the ICIE bit is set and the I bit is
cleared.
– Set OC1E bit: the OCMP1 pin is then dedicat-
ed to the output compare 1 function.
– Set the PWM bit.
4. In PWM mode the ICAP1 pin can not be used
to perform input capture because it is discon-
nected to the timer. The ICAP2 pin can be used
to perform input capture (ICF2 can be set and
IC2R can be loaded) but the user must take
care that the counter is reset each period and
ICF1 can also generates interrupt if ICIE is set.
– Select the timer clock (CC[1:0]) (see Table 16
Clock Control Bits).
Pulse Width Modulation cycle
When
Counter
= OC1R
OCMP1 = OLVL1
5. When the Pulse Width Modulation (PWM) and
One Pulse Mode (OPM) bits are both set, the
PWM mode is the only active one.
OCMP1 = OLVL2
6. In Flash devices, the TAOC2HR, TAOC2LR
registers in Timer A are “write only”. A read
operation returns an undefined value.
When
Counter
= OC2R
Counter is reset
to FFFCh
7. In Flash devices, the ICAP2 registers
(TAIC2HR, TAIC2LR) are not available in Timer A.
The ICF2 bit is forced by hardware to 0.
ICF1 bit is set
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ST72324
16-BIT TIMER (Cont’d)
10.3.4 Low Power Modes
Mode
Description
No effect on 16-bit Timer.
Timer interrupts cause the device to exit from WAIT mode.
WAIT
16-bit Timer registers are frozen.
In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous
count when the MCU is woken up by an interrupt with “exit from HALT mode” capability or from the counter
reset value when the MCU is woken up by a RESET.
HALT
If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is armed. Consequent-
ly, when the MCU is woken up by an interrupt with “exit from HALT mode” capability, the ICFi bit is set, and
the counter value present when exiting from HALT mode is captured into the ICiR register.
10.3.5 Interrupts
Enable
Control from
Bit
Exit
Exit
from
Halt
Event
Flag
Interrupt Event
Wait
Yes
Yes
Yes
Yes
Yes
Input Capture 1 event/Counter reset in PWM mode
Input Capture 2 event
ICF1
ICF2*
OCF1
OCF2*
TOF
No
No
No
No
No
ICIE
Output Compare 1 event (not available in PWM mode)
Output Compare 2 event (not available in PWM mode)
Timer Overflow event
OCIE
TOIE
Note: The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts chap-
ter). These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt
mask in the CC register is reset (RIM instruction).
* In Flash devices, the ICF2 and OCF2 bits are forced by hardware to 0 in Timer A, hence there is no in-
terrupt event for these flags.
10.3.6 Summary of Timer modes
TIMER RESOURCES
MODES
Input Capture 1
Input Capture 2
Output Compare 1 Output Compare 2
2)5)
4)
Input Capture (1 and/or 2)
Yes
Yes
Yes
Yes
Yes
Yes
Yes
5)
4)
Output Compare (1 and/or 2)
Yes
Not
2)
One Pulse Mode
PWM Mode
No
No
No
No
Partially
No
1)5)
3)5)
Recommended
Not
Recommended
1) See note 4 in Section 10.3.3.5 One Pulse Mode
2) See note 5 and 6 in Section 10.3.3.5 One Pulse Mode
3) See note 4 in Section 10.3.3.6 Pulse Width Modulation Mode
4) In Flash devices, the TAOC2HR, TAOC2LR registers are write only in Timer A. Output Compare 2
event cannot be generated, OCF2 is forced by hardware to 0.
5) In Flash devices, Input Capture 2 is not implemented in Timer A. ICF2 bit is forced by hardware to 0.
71/163
1
ST72324
16-BIT TIMER (Cont’d)
10.3.7 Register Description
Bit 4 = FOLV2 Forced Output Compare 2.
This bit is set and cleared by software.
0: No effect on the OCMP2 pin.
1:Forces the OLVL2 bit to be copied to the
OCMP2 pin, if the OC2E bit is set and even if
there is no successful comparison.
Each Timer is associated with three control and
status registers, and with six pairs of data registers
(16-bit values) relating to the two input captures,
the two output compares, the counter and the al-
ternate counter.
Bit 3 = FOLV1 Forced Output Compare 1.
This bit is set and cleared by software.
0: No effect on the OCMP1 pin.
CONTROL REGISTER 1 (CR1)
Read/Write
1: Forces OLVL1 to be copied to the OCMP1 pin, if
the OC1E bit is set and even if there is no suc-
cessful comparison.
Reset Value: 0000 0000 (00h)
7
0
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
Bit 2 = OLVL2 Output Level 2.
This bit is copied to the OCMP2 pin whenever a
successful comparison occurs with the OC2R reg-
ister and OCxE is set in the CR2 register. This val-
ue is copied to the OCMP1 pin in One Pulse Mode
and Pulse Width Modulation mode.
Bit 7 = ICIE Input Capture Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the
ICF1 or ICF2 bit of the SR register is set.
Bit 6 = OCIE Output Compare Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the
OCF1 or OCF2 bit of the SR register is set.
Bit 1 = IEDG1 Input Edge 1.
This bit determines which type of level transition
on the ICAP1 pin will trigger the capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
Bit 5 = TOIE Timer Overflow Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is enabled whenever the TOF
bit of the SR register is set.
Bit 0 = OLVL1 Output Level 1.
The OLVL1 bit is copied to the OCMP1 pin when-
ever a successful comparison occurs with the
OC1R register and the OC1E bit is set in the CR2
register.
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1
ST72324
16-BIT TIMER (Cont’d)
CONTROL REGISTER 2 (CR2)
Read/Write
Bit 4 = PWM Pulse Width Modulation.
0: PWM mode is not active.
1: PWM mode is active, the OCMP1 pin outputs a
programmable cyclic signal; the length of the
pulse depends on the value of OC1R register;
the period depends on the value of OC2R regis-
ter.
Reset Value: 0000 0000 (00h)
7
0
OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG
Bit 3, 2 = CC[1:0] Clock Control.
Bit 7 = OC1E Output Compare 1 Pin Enable.
This bit is used only to output the signal from the
timer on the OCMP1 pin (OLV1 in Output Com-
pare mode, both OLV1 and OLV2 in PWM and
one-pulse mode). Whatever the value of the OC1E
bit, the Output Compare 1 function of the timer re-
mains active.
0: OCMP1 pin alternate function disabled (I/O pin
free for general-purpose I/O).
1: OCMP1 pin alternate function enabled.
The timer clock mode depends on these bits:
Table 16. Clock Control Bits
Timer Clock
fCPU / 4
CC1
CC0
0
0
1
0
1
0
fCPU / 2
fCPU / 8
External Clock (where
available)
1
1
Bit 6 = OC2E Output Compare 2 Pin Enable.
This bit is used only to output the signal from the
timer on the OCMP2 pin (OLV2 in Output Com-
pare mode). Whatever the value of the OC2E bit,
the Output Compare 2 function of the timer re-
mains active.
0: OCMP2 pin alternate function disabled (I/O pin
free for general-purpose I/O).
1: OCMP2 pin alternate function enabled.
Note: If the external clock pin is not available, pro-
gramming the external clock configuration stops
the counter.
Bit 1 = IEDG2 Input Edge 2.
This bit determines which type of level transition
on the ICAP2 pin will trigger the capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
Note: In Flash devices, this bit is not available for
Timer A. It must be kept at its reset value.
Bit 0 = EXEDG External Clock Edge.
Bit 5 = OPM One Pulse Mode.
This bit determines which type of level transition
on the external clock pin EXTCLK will trigger the
counter register.
0: One Pulse Mode is not active.
1: One Pulse Mode is active, the ICAP1 pin can be
used to trigger one pulse on the OCMP1 pin; the
active transition is given by the IEDG1 bit. The
length of the generated pulse depends on the
contents of the OC1R register.
0: A falling edge triggers the counter register.
1: A rising edge triggers the counter register.
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ST72324
16-BIT TIMER (Cont’d)
CONTROL/STATUS REGISTER (CSR)
Read Only (except bit 2 R/W)
Reset Value: xxxx x0xx (xxh)
7
Bit 4 = ICF2 Input Capture Flag 2.
0: No input capture (reset value).
1: An input capture has occurred on the ICAP2
pin. To clear this bit, first read the SR register,
then read or write the low byte of the IC2R
(IC2LR) register.
0
0
ICF1 OCF1 TOF ICF2 OCF2 TIMD
0
Note: In Flash devices, this bit is not available for
Timer A and is forced by hardware to 0.
Bit 7 = ICF1 Input Capture Flag 1.
0: No input capture (reset value).
1: An input capture has occurred on the ICAP1 pin
or the counter has reached the OC2R value in
PWM mode. To clear this bit, first read the SR
register, then read or write the low byte of the
IC1R (IC1LR) register.
Bit 3 = OCF2 Output Compare Flag 2.
0: No match (reset value).
1: The content of the free running counter has
matched the content of the OC2R register. To
clear this bit, first read the SR register, then read
or write the low byte of the OC2R (OC2LR) reg-
ister.
Bit 6 = OCF1 Output Compare Flag 1.
0: No match (reset value).
1: The content of the free running counter has
matched the content of the OC1R register. To
clear this bit, first read the SR register, then read
or write the low byte of the OC1R (OC1LR) reg-
ister.
Note: In Flash devices, this bit is not available for
Timer A and is forced by hardware to 0.
Bit 2 = TIMD Timer disable.
This bit is set and cleared by software. When set, it
freezes the timer prescaler and counter and disa-
bled the output functions (OCMP1 and OCMP2
pins) to reduce power consumption. Access to the
timer registers is still available, allowing the timer
configuration to be changed, or the counter reset,
while it is disabled.
Bit 5 = TOF Timer Overflow Flag.
0: No timer overflow (reset value).
1:The free running counter rolled over from FFFFh
to 0000h. To clear this bit, first read the SR reg-
ister, then read or write the low byte of the CR
(CLR) register.
0: Timer enabled
1: Timer prescaler, counter and outputs disabled
Note: Reading or writing the ACLR register does
not clear TOF.
Bits 1:0 = Reserved, must be kept cleared.
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ST72324
16-BIT TIMER (Cont’d)
INPUT CAPTURE 1 HIGH REGISTER (IC1HR)
OUTPUT COMPARE
(OC1HR)
1
HIGH REGISTER
Read Only
Reset Value: Undefined
Read/Write
Reset Value: 1000 0000 (80h)
This is an 8-bit read only register that contains the
high part of the counter value (transferred by the
input capture 1 event).
This is an 8-bit register that contains the high part
of the value to be compared to the CHR register.
7
0
7
0
MSB
LSB
MSB
LSB
INPUT CAPTURE 1 LOW REGISTER (IC1LR)
OUTPUT COMPARE
(OC1LR)
1
LOW REGISTER
Read Only
Reset Value: Undefined
Read/Write
Reset Value: 0000 0000 (00h)
This is an 8-bit read only register that contains the
low part of the counter value (transferred by the in-
put capture 1 event).
This is an 8-bit register that contains the low part of
the value to be compared to the CLR register.
7
0
7
0
MSB
LSB
MSB
LSB
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ST72324
16-BIT TIMER (Cont’d)
OUTPUT COMPARE
(OC2HR)
2
HIGH REGISTER
COUNTER HIGH REGISTER (CHR)
Read/Write
Reset Value: 1000 0000 (80h)
Read Only
Reset Value: 1111 1111 (FFh)
This is an 8-bit register that contains the high part
of the value to be compared to the CHR register.
This is an 8-bit register that contains the high part
of the counter value.
7
0
7
0
MSB
LSB
MSB
LSB
Note: In Flash devices, the Timer A OC2HR regis-
ter is write-only.
COUNTER LOW REGISTER (CLR)
Read Only
OUTPUT COMPARE
(OC2LR)
2
LOW REGISTER
Reset Value: 1111 1100 (FCh)
This is an 8-bit register that contains the low part of
the counter value. A write to this register resets the
counter. An access to this register after accessing
the CSR register clears the TOF bit.
Read/Write
Reset Value: 0000 0000 (00h)
This is an 8-bit register that contains the low part of
the value to be compared to the CLR register.
7
0
7
0
MSB
LSB
MSB
LSB
Note: In Flash devices, the Timer A OC2LR regis-
ter is write-only.
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ST72324
ALTERNATE COUNTER HIGH REGISTER
INPUT CAPTURE 2 HIGH REGISTER (IC2HR)
Read Only
(ACHR)
Read Only
Reset Value: 1111 1111 (FFh)
Reset Value: Undefined
This is an 8-bit read only register that contains the
high part of the counter value (transferred by the
Input Capture 2 event).
This is an 8-bit register that contains the high part
of the counter value.
7
0
7
0
MSB
LSB
MSB
LSB
Note: In Flash devices, this register is not imple-
mented for Timer A.
ALTERNATE COUNTER LOW REGISTER
(ACLR)
Read Only
Reset Value: 1111 1100 (FCh)
INPUT CAPTURE 2 LOW REGISTER (IC2LR)
Read Only
Reset Value: Undefined
This is an 8-bit register that contains the low part of
the counter value. A write to this register resets the
counter. An access to this register after an access
to CSR register does not clear the TOF bit in the
CSR register.
This is an 8-bit read only register that contains the
low part of the counter value (transferred by the In-
put Capture 2 event).
7
0
7
0
MSB
LSB
MSB
LSB
Note: In Flash devices, this register is not imple-
mented for Timer A.
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ST72324
16-BIT TIMER (Cont’d)
Table 17. 16-Bit Timer Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
1
Timer A: 32 CR1
Timer B: 42 Reset Value
ICIE
0
OCIE
0
TOIE
0
FOLV2
0
FOLV1
0
OLVL2
0
IEDG1
0
OLVL1
0
1
1
Timer A: 31 CR2
Timer B: 41 Reset Value
OC1E
0
OC2E
0
OPM
0
PWM
0
CC1
0
CC0
0
IEDG2
0
EXEDG
0
2
2
Timer A: 33 CSR
Timer B: 43 Reset Value
ICF1
x
OCF1
x
TOF
x
ICF2
OCF2
TIMD
0
-
x
-
x
x
x
x
0
0
0
0
1
1
1
1
x
x
x
x
x
0
0
0
0
1
1
1
1
x
x
Timer A: 34 IC1HR
Timer B: 44 Reset Value
MSB
x
LSB
x
x
x
0
0
0
0
1
1
1
1
x
x
x
x
0
0
0
0
1
1
1
1
x
x
x
x
0
0
0
0
1
1
1
1
x
x
x
x
0
0
0
0
1
0
1
0
x
x
Timer A: 35 IC1LR
Timer B: 45 Reset Value
MSB
x
LSB
x
Timer A: 36 OC1HR
Timer B: 46 Reset Value
MSB
1
LSB
0
Timer A: 37 OC1LR
MSB
0
LSB
0
Timer B: 47 Reset Value
3
Timer A: 3E OC2HR
MSB
1
LSB
0
Timer B: 4E Reset Value
3
Timer A: 3F OC2LR
MSB
0
LSB
0
Timer B: 4F Reset Value
Timer A: 38 CHR
Timer B: 48 Reset Value
MSB
1
LSB
1
Timer A: 39 CLR
Timer B: 49 Reset Value
MSB
1
LSB
0
Timer A: 3A ACHR
Timer B: 4A Reset Value
MSB
1
LSB
1
Timer A: 3B ACLR
MSB
1
LSB
0
Timer B: 4B Reset Value
4
Timer A: 3C IC2HR
MSB
x
LSB
x
Timer B: 4C Reset Value
4
Timer A: 3D IC2LR
MSB
x
LSB
x
Timer B: 4D Reset Value
1
2
In Flash devices, these bits are not used in Timer A and must be kept cleared.
In Flash devices, these bits are forced by hardware to 0 in Timer A
3
In Flash devices, the TAOC2HR and TAOC2LR Registers are write only, reading them will return unde-
fined values
4
In Flash devices, the TAIC2HR and TAIC2LR registers are not present.
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ST72324
10.4 SERIAL PERIPHERAL INTERFACE (SPI)
10.4.1 Introduction
Note: In slave mode, continuous transmission is
not possible at maximum frequency due to the
software overhead for clearing status flags and to
initiate the next transmission sequence.
The Serial Peripheral Interface (SPI) allows full-
duplex, synchronous, serial communication with
external devices. An SPI system may consist of a
master and one or more slaves however the SPI
interface can not be a master in a multi-master
system.
10.4.3 General Description
Figure 46 shows the serial peripheral interface
(SPI) block diagram. There are 3 registers:
10.4.2 Main Features
– SPI Control Register (SPICR)
– SPI Control/Status Register (SPICSR)
– SPI Data Register (SPIDR)
■ Full duplex synchronous transfers (on 3 lines)
■ Simplex synchronous transfers (on 2 lines)
■ Master or slave operation
The SPI is connected to external devices through
4 pins:
■ Six master mode frequencies (f
/4 max.)
CPU
■ f
/2 max. slave mode frequency (see note)
CPU
– MISO: Master In / Slave Out data
– MOSI: Master Out / Slave In data
■ SS Management by software or hardware
■ Programmable clock polarity and phase
■ End of transfer interrupt flag
– SCK: Serial Clock out by SPI masters and in-
put by SPI slaves
■ Write collision, Master Mode Fault and Overrun
flags
Figure 46. Serial Peripheral Interface Block Diagram
Data/Address Bus
Read
SPIDR
Interrupt
request
Read Buffer
MOSI
7
0
SPICSR
MISO
8-Bit Shift Register
SPIF WCOL OVR MODF
0
SOD SSM SSI
Write
SOD
bit
1
SS
SPI
STATE
0
SCK
CONTROL
7
0
SPICR
MSTR
SPR0
SPIE SPE SPR2
CPOL CPHA SPR1
MASTER
CONTROL
SERIAL CLOCK
GENERATOR
SS
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SERIAL PERIPHERAL INTERFACE (Cont’d)
– SS: Slave select:
The communication is always initiated by the mas-
ter. When the master device transmits data to a
slave device via MOSI pin, the slave device re-
sponds by sending data to the master device via
the MISO pin. This implies full duplex communica-
tion with both data out and data in synchronized
with the same clock signal (which is provided by
the master device via the SCK pin).
This input signal acts as a ‘chip select’ to let
the SPI master communicate with slaves indi-
vidually and to avoid contention on the data
lines. Slave SS inputs can be driven by stand-
ard I/O ports on the master MCU.
10.4.3.1 Functional Description
A basic example of interconnections between a
single master and a single slave is illustrated in
Figure 47.
To use a single data line, the MISO and MOSI pins
must be connected at each node (in this case only
simplex communication is possible).
The MOSI pins are connected together and the
MISO pins are connected together. In this way
data is transferred serially between master and
slave (most significant bit first).
Four possible data/clock timing relationships may
be chosen (see Figure 50) but master and slave
must be programmed with the same timing mode.
Figure 47. Single Master/ Single Slave Application
SLAVE
MASTER
MSBit
LSBit
MSBit
LSBit
MISO
MOSI
MISO
MOSI
8-BIT SHIFT REGISTER
8-BIT SHIFT REGISTER
SPI
CLOCK
GENERATOR
SCK
SS
SCK
SS
+5V
Not used if SS is managed
by software
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ST72324
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.4.3.2 Slave Select Management
In Slave Mode:
As an alternative to using the SS pin to control the
Slave Select signal, the application can choose to
manage the Slave Select signal by software. This
is configured by the SSM bit in the SPICSR regis-
ter (see Figure 49)
There are two cases depending on the data/clock
timing relationship (see Figure 48):
If CPHA=1 (data latched on 2nd clock edge):
– SS internal must be held low during the entire
transmission. This implies that in single slave
applications the SS pin either can be tied to
In software management, the external SS pin is
free for other application uses and the internal SS
signal level is driven by writing to the SSI bit in the
SPICSR register.
V
, or made free for standard I/O by manag-
SS
ing the SS function by software (SSM= 1 and
SSI=0 in the in the SPICSR register)
If CPHA=0 (data latched on 1st clock edge):
In Master mode:
– SS internal must be held low during byte
transmission and pulled high between each
byte to allow the slave to write to the shift reg-
ister. If SS is not pulled high, a Write Collision
error will occur when the slave writes to the
shift register (see Section 10.4.5.3).
– SS internal must be held high continuously
Figure 48. Generic SS Timing Diagram
Byte 3
Byte 2
MOSI/MISO
Master SS
Byte 1
Slave SS
(if CPHA=0)
Slave SS
(if CPHA=1)
Figure 49. Hardware/Software Slave Select Management
SSM bit
SSI bit
1
0
SS internal
SS external pin
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ST72324
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.4.3.3 Master Mode Operation
Note: While the SPIF bit is set, all writes to the
SPIDR register are inhibited until the SPICSR reg-
ister is read.
In master mode, the serial clock is output on the
SCK pin. The clock frequency, polarity and phase
are configured by software (refer to the description
of the SPICSR register).
10.4.3.5 Slave Mode Operation
In slave mode, the serial clock is received on the
SCK pin from the master device.
Note: The idle state of SCK must correspond to
the polarity selected in the SPICSR register (by
pulling up SCK if CPOL=1 or pulling down SCK if
CPOL=0).
To operate the SPI in slave mode:
1. Write to the SPICSR register to perform the fol-
lowing actions:
To operate the SPI in master mode, perform the
following steps in order (if the SPICSR register is
not written first, the SPICR register setting (MSTR
bit) may be not taken into account):
– Select the clock polarity and clock phase by
configuring the CPOL and CPHA bits (see
Figure 50).
Note: The slave must have the same CPOL
and CPHA settings as the master.
1. Write to the SPICR register:
– Manage the SS pin as described in Section
10.4.3.2 and Figure 48. If CPHA=1 SS must
be held low continuously. If CPHA=0 SS must
be held low during byte transmission and
pulled up between each byte to let the slave
write in the shift register.
– Select the clock frequency by configuring the
SPR[2:0] bits.
– Select the clock polarity and clock phase by
configuring the CPOL and CPHA bits. Figure
50 shows the four possible configurations.
Note: The slave must have the same CPOL
and CPHA settings as the master.
2. Write to the SPICR register to clear the MSTR
bit and set the SPE bit to enable the SPI I/O
functions.
2. Write to the SPICSR register:
– Either set the SSM bit and set the SSI bit or
clear the SSM bit and tie the SS pin high for
the complete byte transmit sequence.
10.4.3.6 Slave Mode Transmit Sequence
When software writes to the SPIDR register, the
data byte is loaded into the 8-bit shift register and
then shifted out serially to the MISO pin most sig-
nificant bit first.
3. Write to the SPICR register:
– Set the MSTR and SPE bits
Note: MSTR and SPE bits remain set only if
SS is high).
The transmit sequence begins when the slave de-
vice receives the clock signal and the most signifi-
cant bit of the data on its MOSI pin.
The transmit sequence begins when software
writes a byte in the SPIDR register.
10.4.3.4 Master Mode Transmit Sequence
When data transfer is complete:
– The SPIF bit is set by hardware
When software writes to the SPIDR register, the
data byte is loaded into the 8-bit shift register and
then shifted out serially to the MOSI pin most sig-
nificant bit first.
– An interrupt request is generated if SPIE bit is
set and interrupt mask in the CCR register is
cleared.
When data transfer is complete:
– The SPIF bit is set by hardware
Clearing the SPIF bit is performed by the following
software sequence:
– An interrupt request is generated if the SPIE
bit is set and the interrupt mask in the CCR
register is cleared.
1. An access to the SPICSR register while the
SPIF bit is set.
2. A write or a read to the SPIDR register.
Clearing the SPIF bit is performed by the following
software sequence:
Notes: While the SPIF bit is set, all writes to the
SPIDR register are inhibited until the SPICSR reg-
ister is read.
1. An access to the SPICSR register while the
SPIF bit is set
The SPIF bit can be cleared during a second
transmission; however, it must be cleared before
the second SPIF bit in order to prevent an Overrun
condition (see Section 10.4.5.2).
2. A read to the SPIDR register.
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ST72324
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.4.4 Clock Phase and Clock Polarity
Figure 50, shows an SPI transfer with the four
combinations of the CPHA and CPOL bits. The di-
agram may be interpreted as a master or slave
timing diagram where the SCK pin, the MISO pin,
the MOSI pin are directly connected between the
master and the slave device.
Four possible timing relationships may be chosen
by software, using the CPOL and CPHA bits (See
Figure 50).
Note: The idle state of SCK must correspond to
the polarity selected in the SPICSR register (by
pulling up SCK if CPOL=1 or pulling down SCK if
CPOL=0).
Note: If CPOL is changed at the communication
byte boundaries, the SPI must be disabled by re-
setting the SPE bit.
The combination of the CPOL clock polarity and
CPHA (clock phase) bits selects the data capture
clock edge
Figure 50. Data Clock Timing Diagram
CPHA =1
SCK
(CPOL = 1)
SCK
(CPOL = 0)
Bit 4
Bit 4
Bit3
Bit3
Bit 2
Bit 2
Bit 1
Bit 1
LSBit
LSBit
MSBit Bit 6
MSBit Bit 6
Bit 5
Bit 5
MISO
(from master)
MOSI
(from slave)
SS
(to slave)
CAPTURE STROBE
CPHA =0
SCK
(CPOL = 1)
SCK
(CPOL = 0)
Bit 4
Bit 4
Bit3
Bit 2
Bit 2
Bit 1
Bit 1
LSBit
LSBit
MISO
(from master)
MSBit Bit 6
MSBit Bit 6
Bit 5
Bit 5
Bit3
MOSI
(from slave)
SS
(to slave)
CAPTURE STROBE
Note: This figure should not be used as a replacement for parametric information.
Refer to the Electrical Characteristics chapter.
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ST72324
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.4.5 Error Flags
not cleared the SPIF bit issued from the previously
transmitted byte.
10.4.5.1 Master Mode Fault (MODF)
When an Overrun occurs:
Master mode fault occurs when the master device
has its SS pin pulled low.
– The OVR bit is set and an interrupt request is
generated if the SPIE bit is set.
When a Master mode fault occurs:
In this case, the receiver buffer contains the byte
sent after the SPIF bit was last cleared. A read to
the SPIDR register returns this byte. All other
bytes are lost.
– The MODF bit is set and an SPI interrupt re-
quest is generated if the SPIE bit is set.
– The SPE bit is reset. This blocks all output
from the device and disables the SPI periph-
eral.
The OVR bit is cleared by reading the SPICSR
register.
– The MSTR bit is reset, thus forcing the device
into slave mode.
10.4.5.3 Write Collision Error (WCOL)
A write collision occurs when the software tries to
write to the SPIDR register while a data transfer is
taking place with an external device. When this
happens, the transfer continues uninterrupted;
and the software write will be unsuccessful.
Clearing the MODF bit is done through a software
sequence:
1. A read access to the SPICSR register while the
MODF bit is set.
2. A write to the SPICR register.
Write collisions can occur both in master and slave
mode. See also Section 10.4.3.2 Slave Select
Management.
Notes: To avoid any conflicts in an application
with multiple slaves, the SS pin must be pulled
high during the MODF bit clearing sequence. The
SPE and MSTR bits may be restored to their orig-
inal state during or after this clearing sequence.
Note: a “read collision” will never occur since the
received data byte is placed in a buffer in which
access is always synchronous with the MCU oper-
ation.
Hardware does not allow the user to set the SPE
and MSTR bits while the MODF bit is set except in
the MODF bit clearing sequence.
The WCOL bit in the SPICSR register is set if a
write collision occurs.
10.4.5.2 Overrun Condition (OVR)
No SPI interrupt is generated when the WCOL bit
is set (the WCOL bit is a status flag only).
An overrun condition occurs, when the master de-
vice has sent a data byte and the slave device has
Clearing the WCOL bit is done through a software
sequence (see Figure 51).
Figure 51. Clearing the WCOL bit (Write Collision Flag) Software Sequence
Clearing sequence after SPIF = 1 (end of a data byte transfer)
Read SPICSR
1st Step
RESULT
SPIF =0
WCOL=0
2nd Step
Read SPIDR
Clearing sequence before SPIF = 1 (during a data byte transfer)
Read SPICSR
1st Step
Note: Writing to the SPIDR regis-
ter instead of reading it does not
reset the WCOL bit
RESULT
2nd Step
Read SPIDR
WCOL=0
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ST72324
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.4.5.4 Single Master Systems
Note: To prevent a bus conflict on the MISO line
the master allows only one active slave device
during a transmission.
A typical single master system may be configured,
using an MCU as the master and four MCUs as
slaves (see Figure 52).
For more security, the slave device may respond
to the master with the received data byte. Then the
master will receive the previous byte back from the
slave device if all MISO and MOSI pins are con-
nected and the slave has not written to its SPIDR
register.
The master device selects the individual slave de-
vices by using four pins of a parallel port to control
the four SS pins of the slave devices.
The SS pins are pulled high during reset since the
master device ports will be forced to be inputs at
that time, thus disabling the slave devices.
Other transmission security methods can use
ports for handshake lines or data bytes with com-
mand fields.
Figure 52. Single Master / Multiple Slave Configuration
SS
SS
SS
SS
SCK
SCK
Slave
SCK
Slave
MCU
SCK
Slave
MCU
Slave
MCU
MCU
MOSI MISO
MOSI MISO
MOSI MISO
MOSI MISO
MOSI MISO
SCK
Master
MCU
5V
SS
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ST72324
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.4.6 Low Power Modes
Note: When waking up from Halt mode, if the SPI
remains in Slave mode, it is recommended to per-
form an extra communications cycle to bring the
SPI from Halt mode state to normal state. If the
SPI exits from Slave mode, it returns to normal
state immediately.
Mode
Description
No effect on SPI.
WAIT
SPI interrupt events cause the device to exit
from WAIT mode.
SPI registers are frozen.
Caution: The SPI can wake up the ST7 from Halt
mode only if the Slave Select signal (external SS
pin or the SSI bit in the SPICSR register) is low
when the ST7 enters Halt mode. So if Slave selec-
tion is configured as external (see Section
10.4.3.2), make sure the master drives a low level
on the SS pin when the slave enters Halt mode.
In HALT mode, the SPI is inactive. SPI oper-
ation resumes when the MCU is woken up by
an interrupt with “exit from HALT mode” ca-
pability. The data received is subsequently
read from the SPIDR register when the soft-
ware is running (interrupt vector fetching). If
several data are received before the wake-
up event, then an overrun error is generated.
This error can be detected after the fetch of
the interrupt routine that woke up the device.
HALT
10.4.7 Interrupts
Enable
Control from
Bit
Exit
Exit
from
Halt
Event
Flag
Interrupt Event
Wait
10.4.6.1 Using the SPI to wakeup the MCU from
Halt mode
SPI End of Transfer
Event
SPIF
Yes
Yes
In slave configuration, the SPI is able to wakeup
the ST7 device from HALT mode through a SPIF
interrupt. The data received is subsequently read
from the SPIDR register when the software is run-
ning (interrupt vector fetch). If multiple data trans-
fers have been performed before software clears
the SPIF bit, then the OVR bit is set by hardware.
Master Mode Fault
Event
SPIE
MODF
OVR
Yes
Yes
No
No
Overrun Error
Note: The SPI interrupt events are connected to
the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding
Enable Control Bit is set and the interrupt mask in
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ST72324
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.4.8 Register Description
CONTROL REGISTER (SPICR)
Read/Write
Bit 3 = CPOL Clock Polarity.
This bit is set and cleared by software. This bit de-
termines the idle state of the serial Clock. The
CPOL bit affects both the master and slave
modes.
Reset Value: 0000 xxxx (0xh)
7
0
SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0
0: SCK pin has a low level idle state
1: SCK pin has a high level idle state
Note: If CPOL is changed at the communication
byte boundaries, the SPI must be disabled by re-
setting the SPE bit.
Bit 7 = SPIE Serial Peripheral Interrupt Enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SPI interrupt is generated whenever
SPIF=1, MODF=1 or OVR=1 in the SPICSR
register
Bit 2 = CPHA Clock Phase.
This bit is set and cleared by software.
0: The first clock transition is the first data capture
edge.
1: The second clock transition is the first capture
edge.
Bit 6 = SPE Serial Peripheral Output Enable.
This bit is set and cleared by software. It is also
cleared by hardware when, in master mode, SS=0
(see Section 10.4.5.1 Master Mode Fault
(MODF)). The SPE bit is cleared by reset, so the
SPI peripheral is not initially connected to the ex-
ternal pins.
Note: The slave must have the same CPOL and
CPHA settings as the master.
Bits 1:0 = SPR[1:0] Serial Clock Frequency.
These bits are set and cleared by software. Used
with the SPR2 bit, they select the baud rate of the
SPI serial clock SCK output by the SPI in master
mode.
0: I/O pins free for general purpose I/O
1: SPI I/O pin alternate functions enabled
Bit 5 = SPR2 Divider Enable.
Note: These 2 bits have no effect in slave mode.
This bit is set and cleared by software and is
cleared by reset. It is used with the SPR[1:0] bits to
set the baud rate. Refer to Table 18 SPI Master
mode SCK Frequency.
Table 18. SPI Master mode SCK Frequency
Serial Clock
SPR2 SPR1 SPR0
0: Divider by 2 enabled
1: Divider by 2 disabled
f
f
/4
/8
1
0
0
1
0
0
0
0
0
1
1
1
0
0
1
0
0
1
CPU
CPU
Note: This bit has no effect in slave mode.
f
f
f
/16
/32
/64
CPU
CPU
CPU
Bit 4 = MSTR Master Mode.
This bit is set and cleared by software. It is also
cleared by hardware when, in master mode, SS=0
(see Section 10.4.5.1 Master Mode Fault
(MODF)).
f
/128
CPU
0: Slave mode
1: Master mode. The function of the SCK pin
changes from an input to an output and the func-
tions of the MISO and MOSI pins are reversed.
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ST72324
SERIAL PERIPHERAL INTERFACE (Cont’d)
CONTROL/STATUS REGISTER (SPICSR)
Read/Write (some bits Read Only)
Reset Value: 0000 0000 (00h)
Bit 3 = Reserved, must be kept cleared.
Bit 2 = SOD SPI Output Disable.
7
0
This bit is set and cleared by software. When set, it
disables the alternate function of the SPI output
(MOSI in master mode / MISO in slave mode)
0: SPI output enabled (if SPE=1)
SPIF
WCOL OVR MODF
-
SOD SSM SSI
1: SPI output disabled
Bit 7 = SPIF Serial Peripheral Data Transfer Flag
(Read only).
Bit 1 = SSM SS Management.
This bit is set by hardware when a transfer has
been completed. An interrupt is generated if
SPIE=1 in the SPICR register. It is cleared by a
software sequence (an access to the SPICSR
register followed by a write or a read to the
SPIDR register).
This bit is set and cleared by software. When set, it
disables the alternate function of the SPI SS pin
and uses the SSI bit value instead. See Section
10.4.3.2 Slave Select Management.
0: Hardware management (SS managed by exter-
nal pin)
0: Data transfer is in progress or the flag has been
cleared.
1: Data transfer between the device and an exter-
nal device has been completed.
1: Software management (internal SS signal con-
trolled by SSI bit. External SS pin free for gener-
al-purpose I/O)
Note: While the SPIF bit is set, all writes to the
SPIDR register are inhibited until the SPICSR reg-
ister is read.
Bit 0 = SSI SS Internal Mode.
This bit is set and cleared by software. It acts as a
‘chip select’ by controlling the level of the SS slave
select signal when the SSM bit is set.
0: Slave selected
Bit 6 = WCOL Write Collision status (Read only).
This bit is set by hardware when a write to the
SPIDR register is done during a transmit se-
quence. It is cleared by a software sequence (see
Figure 51).
0: No write collision occurred
1: A write collision has been detected
1: Slave deselected
DATA I/O REGISTER (SPIDR)
Read/Write
Reset Value: Undefined
7
0
Bit 5 = OVR SPI Overrun error (Read only).
This bit is set by hardware when the byte currently
being received in the shift register is ready to be
transferred into the SPIDR register while SPIF = 1
(See Section 10.4.5.2). An interrupt is generated if
SPIE = 1 in SPICR register. The OVR bit is cleared
by software reading the SPICSR register.
0: No overrun error
D7
D6
D5
D4
D3
D2
D1
D0
The SPIDR register is used to transmit and receive
data on the serial bus. In a master device, a write
to this register will initiate transmission/reception
of another byte.
1: Overrun error detected
Notes: During the last clock cycle the SPIF bit is
set, a copy of the received data byte in the shift
register is moved to a buffer. When the user reads
the serial peripheral data I/O register, the buffer is
actually being read.
Bit 4 = MODF Mode Fault flag (Read only).
This bit is set by hardware when the SS pin is
pulled low in master mode (see Section 10.4.5.1
Master Mode Fault (MODF)). An SPI interrupt can
be generated if SPIE=1 in the SPICSR register.
This bit is cleared by a software sequence (An ac-
cess to the SPICR register while MODF=1 fol-
lowed by a write to the SPICR register).
While the SPIF bit is set, all writes to the SPIDR
register are inhibited until the SPICSR register is
read.
Warning: A write to the SPIDR register places
data directly into the shift register for transmission.
0: No master mode fault detected
1: A fault in master mode has been detected
A read to the SPIDR register returns the value lo-
cated in the buffer and not the content of the shift
register (see Figure 46).
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ST72324
SERIAL PERIPHERAL INTERFACE (Cont’d)
Table 19. SPI Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
SPIDR
Reset Value
MSB
x
LSB
x
0021h
0022h
0023h
x
x
x
x
x
x
SPICR
Reset Value
SPIE
0
SPE
0
SPR2
0
MSTR
0
CPOL
x
CPHA
x
SPR1
x
SPR0
x
SPICSR
Reset Value
SPIF
0
WCOL
0
OR
0
MODF
0
SOD
0
SSM
0
SSI
0
0
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ST72324
10.5 SERIAL COMMUNICATIONS INTERFACE (SCI)
10.5.1 Introduction
10.5.3 General Description
The Serial Communications Interface (SCI) offers
a flexible means of full-duplex data exchange with
external equipment requiring an industry standard
NRZ asynchronous serial data format. The SCI of-
fers a very wide range of baud rates using two
baud rate generator systems.
The interface is externally connected to another
device by two pins (see Figure 54):
– TDO: Transmit Data Output. When the transmit-
ter and the receiver are disabled, the output pin
returns to its I/O port configuration. When the
transmitter and/or the receiver are enabled and
nothing is to be transmitted, the TDO pin is at
high level.
10.5.2 Main Features
■ Full duplex, asynchronous communications
■ NRZ standard format (Mark/Space)
■ Dual baud rate generator systems
– RDI: Receive Data Input is the serial data input.
Oversampling techniques are used for data re-
covery by discriminating between valid incoming
data and noise.
■ Independently programmable transmit and
receive baud rates up to 500K baud.
Through these pins, serial data is transmitted and
received as frames comprising:
■ Programmable data word length (8 or 9 bits)
■ Receive buffer full, Transmit buffer empty and
– An Idle Line prior to transmission or reception
– A start bit
End of Transmission flags
■ Two receiver wake-up modes:
– Address bit (MSB)
– A data word (8 or 9 bits) least significant bit first
– A Stop bit indicating that the frame is complete.
Thisinterfaceusestwotypesofbaudrategenerator:
– Idle line
■ Mutingfunctionformultiprocessorconfigurations
– A conventional type for commonly-used baud
rates,
■ Separate enable bits for Transmitter and
Receiver
– An extended type with a prescaler offering a very
wide range of baud rates even with non-standard
oscillator frequencies.
■ Four error detection flags:
– Overrun error
– Noise error
– Frame error
– Parity error
■ Five interrupt sources with flags:
– Transmit data register empty
– Transmission complete
– Receive data register full
– Idle line received
– Overrun error detected
■ Parity control:
– Transmits parity bit
– Checks parity of received data byte
■ Reduced power consumption mode
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ST72324
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
Figure 53. SCI Block Diagram
Write
Read
(DATA REGISTER) DR
Received Data Register (RDR)
Received Shift Register
Transmit Data Register (TDR)
TDO
Transmit Shift Register
RDI
CR1
R8 T8 SCID
M WAKE PCE PS PIE
WAKE
UP
TRANSMIT
CONTROL
RECEIVER
CLOCK
RECEIVER
CONTROL
UNIT
CR2
SR
TIE TCIE RIE ILIE TE RE RWU SBK
TDRE TC RDRF IDLE OR NF FE
PE
SCI
INTERRUPT
CONTROL
TRANSMITTER
CLOCK
TRANSMITTER RATE
CONTROL
f
CPU
/PR
/16
BRR
SCP1
SCT2
SCT1 SCT0 SCR2 SCR1SCR0
SCP0
RECEIVER RATE
CONTROL
CONVENTIONAL BAUD RATE GENERATOR
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ST72324
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.5.4 Functional Description
10.5.4.1 Serial Data Format
The block diagram of the Serial Control Interface,
is shown in Figure 53. It contains 6 dedicated reg-
isters:
Word length may be selected as being either 8 or 9
bits by programming the M bit in the SCICR1 reg-
ister (see Figure 53).
– Two control registers (SCICR1 & SCICR2)
– A status register (SCISR)
The TDO pin is in low state during the start bit.
The TDO pin is in high state during the stop bit.
– A baud rate register (SCIBRR)
An Idle character is interpreted as an entire frame
of “1”s followed by the start bit of the next frame
which contains data.
– An extended prescaler receiver register (SCIER-
PR)
A Break character is interpreted on receiving “0”s
for some multiple of the frame period. At the end of
the last break frame the transmitter inserts an ex-
tra “1” bit to acknowledge the start bit.
– An extended prescaler transmitter register (SCI-
ETPR)
Refer to the register descriptions in Section
10.5.7for the definitions of each bit.
Transmission and reception are driven by their
own baud rate generator.
Figure 54. Word Length Programming
9-bit Word length (M bit is set)
Possible
Next Data Frame
Parity
Data Frame
Start
Bit
Next
Start
Bit
Stop
Bit
Bit2
Bit6
Bit3
Bit4
Bit5
Bit7
Bit8
Bit0 Bit1
Bit
Start
Bit
Idle Frame
Start
Bit
Extra
’1’
Break Frame
8-bit Word length (M bit is reset)
Possible
Parity
Next Data Frame
Data Frame
Bit
Next
Start
Bit
Start
Bit
Stop
Bit
Bit2
Bit1
Bit3
Bit4
Bit5
Bit6
Bit0
Bit7
Start
Bit
Idle Frame
Start
Bit
Extra
’1’
Break Frame
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ST72324
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.5.4.2 Transmitter
When a frame transmission is complete (after the
stop bit) the TC bit is set and an interrupt is gener-
ated if the TCIE is set and the I bit is cleared in the
CCR register.
The transmitter can send data words of either 8 or
9 bits depending on the M bit status. When the M
bit is set, word length is 9 bits and the 9th bit (the
MSB) has to be stored in the T8 bit in the SCICR1
register.
Clearing the TC bit is performed by the following
software sequence:
1. An access to the SCISR register
2. A write to the SCIDR register
Character Transmission
During an SCI transmission, data shifts out least
significant bit first on the TDO pin. In this mode,
the SCIDR register consists of a buffer (TDR) be-
tween the internal bus and the transmit shift regis-
ter (see Figure 53).
Note: The TDRE and TC bits are cleared by the
same software sequence.
Break Characters
Setting the SBK bit loads the shift register with a
break character. The break frame length depends
on the M bit (see Figure 54).
Procedure
– Select the M bit to define the word length.
As long as the SBK bit is set, the SCI send break
frames to the TDO pin. After clearing this bit by
software the SCI insert a logic 1 bit at the end of
the last break frame to guarantee the recognition
of the start bit of the next frame.
– Select the desired baud rate using the SCIBRR
and the SCIETPR registers.
– Set the TE bit to assign the TDO pin to the alter-
nate function and to send a idle frame as first
transmission.
Idle Characters
– Access the SCISR register and write the data to
send in the SCIDR register (this sequence clears
the TDRE bit). Repeat this sequence for each
data to be transmitted.
Setting the TE bit drives the SCI to send an idle
frame before the first data frame.
Clearing and then setting the TE bit during a trans-
mission sends an idle frame after the current word.
Clearing the TDRE bit is always performed by the
following software sequence:
1. An access to the SCISR register
2. A write to the SCIDR register
Note: Resetting and setting the TE bit causes the
data in the TDR register to be lost. Therefore the
best time to toggle the TE bit is when the TDRE bit
is set i.e. before writing the next byte in the SCIDR.
The TDRE bit is set by hardware and it indicates:
– The TDR register is empty.
– The data transfer is beginning.
– The next data can be written in the SCIDR regis-
ter without overwriting the previous data.
This flag generates an interrupt if the TIE bit is set
and the I bit is cleared in the CCR register.
When a transmission is taking place, a write in-
struction to the SCIDR register stores the data in
the TDR register and which is copied in the shift
register at the end of the current transmission.
When no transmission is taking place, a write in-
struction to the SCIDR register places the data di-
rectly in the shift register, the data transmission
starts, and the TDRE bit is immediately set.
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ST72324
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.5.4.3 Receiver
RDR register as long as the RDRF bit is not
cleared.
The SCI can receive data words of either 8 or 9
bits. When the M bit is set, word length is 9 bits
and the MSB is stored in the R8 bit in the SCICR1
register.
When a overrun error occurs:
– The OR bit is set.
– The RDR content will not be lost.
– The shift register will be overwritten.
Character reception
During a SCI reception, data shifts in least signifi-
cant bit first through the RDI pin. In this mode, the
SCIDR register consists or a buffer (RDR) be-
tween the internal bus and the received shift regis-
ter (see Figure 53).
– An interrupt is generated if the RIE bit is set and
the I bit is cleared in the CCR register.
The OR bit is reset by an access to the SCISR reg-
ister followed by a SCIDR register read operation.
Procedure
Noise Error
– Select the M bit to define the word length.
Oversampling techniques are used for data recov-
ery by discriminating between valid incoming data
and noise. Normal data bits are considered valid if
three consecutive samples (8th, 9th, 10th) have
the same bit value, otherwise the NF flag is set. In
the case of start bit detection, the NF flag is set on
the basis of an algorithm combining both valid
edge detection and three samples (8th, 9th, 10th).
Therefore, to prevent the NF flag getting set during
start bit reception, there should be a valid edge de-
tection as well as three valid samples.
– Select the desired baud rate using the SCIBRR
and the SCIERPR registers.
– Set the RE bit, this enables the receiver which
begins searching for a start bit.
When a character is received:
– The RDRF bit is set. It indicates that the content
of the shift register is transferred to the RDR.
– An interrupt is generated if the RIE bit is set and
the I bit is cleared in the CCR register.
When noise is detected in a frame:
– The error flags can be set if a frame error, noise
or an overrun error has been detected during re-
ception.
– The NF flag is set at the rising edge of the RDRF
bit.
– Data is transferred from the Shift register to the
SCIDR register.
Clearing the RDRF bit is performed by the following
software sequence done by:
– No interrupt is generated. However this bit rises
at the same time as the RDRF bit which itself
generates an interrupt.
1. An access to the SCISR register
2. A read to the SCIDR register.
The RDRF bit must be cleared before the end of the
reception of the next character to avoid an overrun
error.
The NF flag is reset by a SCISR register read op-
eration followed by a SCIDR register read opera-
tion.
Break Character
During reception, if a false start bit is detected (e.g.
8th, 9th, 10th samples are 011,101,110), the
frame is discarded and the receiving sequence is
not started for this frame. There is no RDRF bit set
for this frame and the NF flag is set internally (not
accessible to the user). This NF flag is accessible
along with the RDRF bit when a next valid frame is
received.
When a break character is received, the SPI han-
dles it as a framing error.
Idle Character
When a idle frame is detected, there is the same
procedure as a data received character plus an in-
terrupt if the ILIE bit is set and the I bit is cleared in
the CCR register.
Note: If the application Start Bit is not long enough
to match the above requirements, then the NF
Flag may get set due to the short Start Bit. In this
case, the NF flag may be ignored by the applica-
tion software when the first valid byte is received.
Overrun Error
An overrun error occurs when a character is re-
ceived when RDRF has not been reset. Data can
not be transferred from the shift register to the
See also Section 10.5.4.10.
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ST72324
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
Figure 55. SCI Baud Rate and Extended Prescaler Block Diagram
TRANSMITTER
CLOCK
EXTENDED PRESCALER TRANSMITTER RATE CONTROL
SCIETPR
EXTENDED TRANSMITTER PRESCALER REGISTER
SCIERPR
EXTENDED RECEIVER PRESCALER REGISTER
RECEIVER
CLOCK
EXTENDED PRESCALER RECEIVER RATE CONTROL
EXTENDED PRESCALER
f
CPU
TRANSMITTER RATE
CONTROL
/PR
/16
SCIBRR
SCP1
SCT2
SCT1SCT0SCR2 SCR1SCR0
SCP0
RECEIVER RATE
CONTROL
CONVENTIONAL BAUD RATE GENERATOR
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ST72324
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
Framing Error
Note: the extended prescaler is activated by set-
ting the SCIETPR or SCIERPR register to a value
other than zero. The baud rates are calculated as
follows:
A framing error is detected when:
– The stop bit is not recognized on reception at the
expected time, following either a de-synchroni-
zation or excessive noise.
f
f
CPU
CPU
Rx =
16 ERPR*(PR*RR)
Tx =
16 ETPR*(PR*TR)
– A break is received.
*
*
When the framing error is detected:
– the FE bit is set by hardware
with:
– Data is transferred from the Shift register to the
SCIDR register.
ETPR = 1,..,255 (see SCIETPR register)
ERPR = 1,.. 255 (see SCIERPR register)
10.5.4.6 Receiver Muting and Wake-up Feature
– No interrupt is generated. However this bit rises
at the same time as the RDRF bit which itself
generates an interrupt.
In multiprocessor configurations it is often desira-
ble that only the intended message recipient
should actively receive the full message contents,
thus reducing redundant SCI service overhead for
all non addressed receivers.
The FE bit is reset by a SCISR register read oper-
ation followed by a SCIDR register read operation.
10.5.4.4 Conventional Baud Rate Generation
The baud rate for the receiver and transmitter (Rx
and Tx) are set independently and calculated as
follows:
The non addressed devices may be placed in
sleep mode by means of the muting function.
Setting the RWU bit by software puts the SCI in
sleep mode:
f
f
CPU
CPU
Rx =
Tx =
All the reception status bits can not be set.
All the receive interrupts are inhibited.
(16 PR) RR
(16 PR) TR
*
*
*
*
with:
A muted receiver may be awakened by one of the
following two ways:
PR = 1, 3, 4 or 13 (see SCP[1:0] bits)
TR = 1, 2, 4, 8, 16, 32, 64,128
(see SCT[2:0] bits)
– by Idle Line detection if the WAKE bit is reset,
– by Address Mark detection if the WAKE bit is set.
RR = 1, 2, 4, 8, 16, 32, 64,128
(see SCR[2:0] bits)
Receiver wakes-up by Idle Line detection when
the Receive line has recognised an Idle Frame.
Then the RWU bit is reset by hardware but the
IDLE bit is not set.
All these bits are in the SCIBRR register.
Example: If f is 8 MHz (normal mode) and if
CPU
Receiver wakes-up by Address Mark detection
when it received a “1” as the most significant bit of
a word, thus indicating that the message is an ad-
dress. The reception of this particular word wakes
up the receiver, resets the RWU bit and sets the
RDRF bit, which allows the receiver to receive this
word normally and to use it as an address word.
PR=13 and TR=RR=1, the transmit and receive
baud rates are 38400 baud.
Note: the baud rate registers MUST NOT be
changed while the transmitter or the receiver is en-
abled.
10.5.4.5 Extended Baud Rate Generation
The extended prescaler option gives a very fine
tuning on the baud rate, using a 255 value prescal-
er, whereas the conventional Baud Rate Genera-
tor retains industry standard software compatibili-
ty.
Caution: In Mute mode, do not write to the
SCICR2 register. If the SCI is in Mute mode during
the read operation (RWU=1) and a address mark
wake up event occurs (RWU is reset) before the
write operation, the RWU bit will be set again by
this write operation. Consequently the address
byte is lost and the SCI is not woken up from Mute
mode.
The extended baud rate generator block diagram
is described in the Figure 55.
The output clock rate sent to the transmitter or to
the receiver will be the output from the 16 divider
divided by a factor ranging from 1 to 255 set in the
SCIERPR or the SCIETPR register.
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ST72324
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.5.4.7 Parity Control
even number of “1s” if even parity is selected
(PS=0) or an odd number of “1s” if odd parity is se-
lected (PS=1). If the parity check fails, the PE flag
is set in the SCISR register and an interrupt is gen-
erated if PIE is set in the SCICR1 register.
Parity control (generation of parity bit in transmis-
sion and parity checking in reception) can be ena-
bled by setting the PCE bit in the SCICR1 register.
Depending on the frame length defined by the M
bit, the possible SCI frame formats are as listed in
Table 20.
10.5.4.8 SCI Clock Tolerance
During reception, each bit is sampled 16 times.
The majority of the 8th, 9th and 10th samples is
considered as the bit value. For a valid bit detec-
tion, all the three samples should have the same
value otherwise the noise flag (NF) is set. For ex-
ample: if the 8th, 9th and 10th samples are 0, 1
and 1 respectively, then the bit value will be “1”,
but the Noise Flag bit is be set because the three
samples values are not the same.
Table 20. Frame Formats
M bit
PCE bit
SCI frame
0
0
1
1
0
1
0
1
| SB | 8 bit data | STB |
| SB | 7-bit data | PB | STB |
| SB | 9-bit data | STB |
| SB | 8-bit data PB | STB |
Legend: SB = Start Bit, STB = Stop Bit,
PB = Parity Bit
Consequently, the bit length must be long enough
so that the 8th, 9th and 10th samples have the de-
sired bit value. This means the clock frequency
should not vary more than 6/16 (37.5%) within one
bit. The sampling clock is resynchronized at each
start bit, so that when receiving 10 bits (one start
bit, 1 data byte, 1 stop bit), the clock deviation
must not exceed 3.75%.
Note: In case of wake up by an address mark, the
MSB bit of the data is taken into account and not
the parity bit
Even parity: the parity bit is calculated to obtain
an even number of “1s” inside the frame made of
the 7 or 8 LSB bits (depending on whether M is
equal to 0 or 1) and the parity bit.
Note: The internal sampling clock of the microcon-
troller samples the pin value on every falling edge.
Therefore, the internal sampling clock and the time
the application expects the sampling to take place
may be out of sync. For example: If the baud rate
is 15.625 kbaud (bit length is 64µs), then the 8th,
9th and 10th samples will be at 28µs, 32µs & 36µs
respectively (the first sample starting ideally at
0µs). But if the falling edge of the internal clock oc-
curs just before the pin value changes, the sam-
ples would then be out of sync by ~4us. This
means the entire bit length must be at least 40µs
(36µs for the 10th sample + 4µs for synchroniza-
tion with the internal sampling clock).
Ex: data=00110101; 4 bits set => parity bit will be
0 if even parity is selected (PS bit = 0).
Odd parity: the parity bit is calculated to obtain an
odd number of “1s” inside the frame made of the 7
or 8 LSB bits (depending on whether M is equal to
0 or 1) and the parity bit.
Ex: data=00110101; 4 bits set => parity bit will be
1 if odd parity is selected (PS bit = 1).
Transmission mode: If the PCE bit is set then the
MSB bit of the data written in the data register is
not transmitted but is changed by the parity bit.
Reception mode: If the PCE bit is set then the in-
terface checks if the received data byte has an
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ST72324
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.5.4.9 Clock Deviation Causes
10.5.4.10 Noise Error Causes
The causes which contribute to the total deviation
are:
See also description of Noise error in Section
10.5.4.3.
– D
: Deviation due to transmitter error (Local
Start bit
TRA
oscillator error of the transmitter or the trans-
mitter is transmitting at a different baud rate).
The noise flag (NF) is set during start bit reception
if one of the following conditions occurs:
– D
: Error due to the baud rate quantisa-
QUANT
1. A valid falling edge is not detected. A falling
edge is considered to be valid if the 3 consecu-
tive samples before the falling edge occurs are
detected as '1' and, after the falling edge
occurs, during the sampling of the 16 samples,
if one of the samples numbered 3, 5 or 7 is
detected as a “1”.
tion of the receiver.
– D
: Deviation of the local oscillator of the
REC
receiver: This deviation can occur during the
reception of one complete SCI message as-
suming that the deviation has been compen-
sated at the beginning of the message.
– D
: Deviation due to the transmission line
2. During sampling of the 16 samples, if one of the
samples numbered 8, 9 or 10 is detected as a
“1”.
TCL
(generally due to the transceivers)
All the deviations of the system should be added
and compared to the SCI clock tolerance:
Therefore, a valid Start Bit must satisfy both the
above conditions to prevent the Noise Flag getting
set.
D
+ D
+ D
+ D
< 3.75%
TCL
TRA
QUANT
REC
Data Bits
The noise flag (NF) is set during normal data bit re-
ception if the following condition occurs:
– During the sampling of 16 samples, if all three
samples numbered 8, 9 and10 are not the same.
The majority of the 8th, 9th and 10th samples is
considered as the bit value.
Therefore, a valid Data Bit must have samples 8, 9
and 10 at the same value to prevent the Noise
Flag getting set.
Figure 56. Bit Sampling in Reception Mode
RDI LINE
sampled values
Sample
clock
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
6/16
7/16
7/16
One bit time
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ST72324
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.5.5 Low Power Modes
Enable Exit
Control from from
Exit
Event
Flag
Interrupt Event
Mode
Description
Bit
Wait
Halt
No effect on SCI.
Transmit Data Register
Empty
TDRE
TC
TIE
Yes
No
WAIT
SCI interrupts cause the device to exit
from Wait mode.
Transmission Com-
plete
TCIE
RIE
Yes
Yes
No
No
SCI registers are frozen.
Received Data Ready
to be Read
RDRF
In Halt mode, the SCI stops transmit-
ting/receiving until Halt mode is exit-
ed.
HALT
Overrun Error Detected OR
Yes
Yes
Yes
No
No
No
Idle Line Detected
Parity Error
IDLE
PE
ILIE
PIE
10.5.6 Interrupts
The SCI interrupt events are connected to the
same interrupt vector.
rupt mask in the CC register is reset (RIM instruc-
tion).
These events generate an interrupt if the corre-
sponding Enable Control Bit is set and the inter-
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ST72324
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.5.7 Register Description
Note: The IDLE bit will not be set again until the
RDRF bit has been set itself (i.e. a new idle line oc-
curs).
STATUS REGISTER (SCISR)
Read Only
Reset Value: 1100 0000 (C0h)
Bit 3 = OR Overrun error.
7
0
This bit is set by hardware when the word currently
being received in the shift register is ready to be
transferred into the RDR register while RDRF=1.
An interrupt is generated if RIE=1 in the SCICR2
register. It is cleared by a software sequence (an
access to the SCISR register followed by a read to
the SCIDR register).
TDRE
TC
RDRF IDLE
OR
NF
FE
PE
Bit 7 = TDRE Transmit data register empty.
This bit is set by hardware when the content of the
TDR register has been transferred into the shift
register. An interrupt is generated if the TIE bit=1
in the SCICR2 register. It is cleared by a software
sequence (an access to the SCISR register fol-
lowed by a write to the SCIDR register).
0: No Overrun error
1: Overrun error is detected
Note: When this bit is set RDR register content will
not be lost but the shift register will be overwritten.
0: Data is not transferred to the shift register
1: Data is transferred to the shift register
Bit 2 = NF Noise flag.
Note: Data will not be transferred to the shift reg-
This bit is set by hardware when noise is detected
on a received frame. It is cleared by a software se-
quence (an access to the SCISR register followed
by a read to the SCIDR register).
0: No noise is detected
ister unless the TDRE bit is cleared.
Bit 6 = TC Transmission complete.
This bit is set by hardware when transmission of a
frame containing Data is complete. An interrupt is
generated if TCIE=1 in the SCICR2 register. It is
cleared by a software sequence (an access to the
SCISR register followed by a write to the SCIDR
register).
1: Noise is detected
Note: This bit does not generate interrupt as it ap-
pears at the same time as the RDRF bit which it-
self generates an interrupt.
0: Transmission is not complete
1: Transmission is complete
Bit 1 = FE Framing error.
This bit is set by hardware when a de-synchroniza-
tion, excessive noise or a break character is de-
tected. It is cleared by a software sequence (an
access to the SCISR register followed by a read to
the SCIDR register).
Note: TC is not set after the transmission of a Pre-
amble or a Break.
Bit 5 = RDRF Received data ready flag.
This bit is set by hardware when the content of the
RDR register has been transferred to the SCIDR
register. An interrupt is generated if RIE=1 in the
SCICR2 register. It is cleared by a software se-
quence (an access to the SCISR register followed
by a read to the SCIDR register).
0: No Framing error is detected
1: Framing error or break character is detected
Note: This bit does not generate interrupt as it ap-
pears at the same time as the RDRF bit which it-
self generates an interrupt. If the word currently
being transferred causes both frame error and
overrun error, it will be transferred and only the OR
bit will be set.
0: Data is not received
1: Received data is ready to be read
Bit 4 = IDLE Idle line detect.
This bit is set by hardware when a Idle Line is de-
tected. An interrupt is generated if the ILIE=1 in
the SCICR2 register. It is cleared by a software se-
quence (an access to the SCISR register followed
by a read to the SCIDR register).
Bit 0 = PE Parity error.
This bit is set by hardware when a parity error oc-
curs in receiver mode. It is cleared by a software
sequence (a read to the status register followed by
an access to the SCIDR data register). An inter-
rupt is generated if PIE=1 in the SCICR1 register.
0: No parity error
0: No Idle Line is detected
1: Idle Line is detected
1: Parity error
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ST72324
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
CONTROL REGISTER 1 (SCICR1)
Read/Write
Bit 3 = WAKE Wake-Up method.
This bit determines the SCI Wake-Up method, it is
set or cleared by software.
0: Idle Line
Reset Value: x000 0000 (x0h)
7
0
1: Address Mark
R8
T8
SCID
M
WAKE PCE
PS
PIE
Bit 2 = PCE Parity control enable.
This bit selects the hardware parity control (gener-
ation and detection). When the parity control is en-
abled, the computed parity is inserted at the MSB
position (9th bit if M=1; 8th bit if M=0) and parity is
checked on the received data. This bit is set and
cleared by software. Once it is set, PCE is active
after the current byte (in reception and in transmis-
sion).
Bit 7 = R8 Receive data bit 8.
This bit is used to store the 9th bit of the received
word when M=1.
Bit 6 = T8 Transmit data bit 8.
This bit is used to store the 9th bit of the transmit-
ted word when M=1.
0: Parity control disabled
1: Parity control enabled
Bit 5 = SCID Disabled for low power consumption
When this bit is set the SCI prescalers and outputs
are stopped and the end of the current byte trans-
fer in order to reduce power consumption.This bit
is set and cleared by software.
0: SCI enabled
1: SCI prescaler and outputs disabled
Bit 1 = PS Parity selection.
This bit selects the odd or even parity when the
parity generation/detection is enabled (PCE bit
set). It is set and cleared by software. The parity
will be selected after the current byte.
0: Even parity
1: Odd parity
Bit 4 = M Word length.
This bit determines the word length. It is set or
cleared by software.
0: 1 Start bit, 8 Data bits, 1 Stop bit
1: 1 Start bit, 9 Data bits, 1 Stop bit
Bit 0 = PIE Parity interrupt enable.
This bit enables the interrupt capability of the hard-
ware parity control when a parity error is detected
(PE bit set). It is set and cleared by software.
0: Parity error interrupt disabled
Note: The M bit must not be modified during a data
transfer (both transmission and reception).
1: Parity error interrupt enabled.
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ST72324
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
CONTROL REGISTER 2 (SCICR2)
Read/Write
Notes:
– During transmission, a “0” pulse on the TE bit
(“0” followed by “1”) sends a preamble (idle line)
after the current word.
Reset Value: 0000 0000 (00h)
7
0
– When TE is set there is a 1 bit-time delay before
the transmission starts.
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
Caution: The TDO pin is free for general purpose
I/O only when the TE and RE bits are both cleared
(or if TE is never set).
Bit 7 = TIE Transmitter interrupt enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever
TDRE=1 in the SCISR register
Bit 2 = RE Receiver enable.
This bit enables the receiver. It is set and cleared
by software.
0: Receiver is disabled
1: Receiver is enabled and begins searching for a
start bit
Bit 6 = TCIE Transmission complete interrupt ena-
ble
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever TC=1 in
the SCISR register
Bit 1 = RWU Receiver wake-up.
This bit determines if the SCI is in mute mode or
not. It is set and cleared by software and can be
cleared by hardware when a wake-up sequence is
recognized.
Bit 5 = RIE Receiver interrupt enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever OR=1
or RDRF=1 in the SCISR register
0: Receiver in Active mode
1: Receiver in Mute mode
Note: Before selecting Mute mode (setting the
RWU bit), the SCI must receive some data first,
otherwise it cannot function in Mute mode with
wakeup by idle line detection.
Bit 4 = ILIE Idle line interrupt enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever IDLE=1
in the SCISR register.
Bit 0 = SBK Send break.
This bit set is used to send break characters. It is
set and cleared by software.
0: No break character is transmitted
1: Break characters are transmitted
Bit 3 = TE Transmitter enable.
This bit enables the transmitter. It is set and
cleared by software.
Note: If the SBK bit is set to “1” and then to “0”, the
transmitter will send a BREAK word at the end of
the current word.
0: Transmitter is disabled
1: Transmitter is enabled
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ST72324
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
DATA REGISTER (SCIDR)
Read/Write
Bits 5:3 = SCT[2:0] SCI Transmitter rate divisor
These 3 bits, in conjunction with the SCP1 & SCP0
bits define the total division applied to the bus
clock to yield the transmit rate clock in convention-
al Baud Rate Generator mode.
Reset Value: Undefined
Contains the Received or Transmitted data char-
acter, depending on whether it is read from or writ-
ten to.
TR dividing factor
SCT2
SCT1
SCT0
1
2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
7
0
4
DR7
DR6
DR5
DR4
DR3
DR2
DR1
DR0
8
16
32
64
128
The Data register performs a double function (read
and write) since it is composed of two registers,
one for transmission (TDR) and one for reception
(RDR).
The TDR register provides the parallel interface
between the internal bus and the output shift reg-
ister (see Figure 53).
The RDR register provides the parallel interface
between the input shift register and the internal
bus (see Figure 53).
Bits 2:0 = SCR[2:0] SCI Receiver rate divisor.
These 3 bits, in conjunction with the SCP[1:0] bits
define the total division applied to the bus clock to
yield the receive rate clock in conventional Baud
Rate Generator mode.
RR Dividing factor
SCR2
SCR1
SCR0
BAUD RATE REGISTER (SCIBRR)
Read/Write
1
2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reset Value: 0000 0000 (00h)
4
7
0
8
16
32
64
128
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0
Bits 7:6= SCP[1:0] First SCI Prescaler
These 2 prescaling bits allow several standard
clock division ranges:
PR Prescaling factor
SCP1
SCP0
1
3
0
0
1
1
0
1
0
1
4
13
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1
ST72324
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
EXTENDED RECEIVE PRESCALER DIVISION
REGISTER (SCIERPR)
EXTENDED TRANSMIT PRESCALER DIVISION
REGISTER (SCIETPR)
Read/Write
Read/Write
Reset Value: 0000 0000 (00h)
Reset Value:0000 0000 (00h)
Allows setting of the Extended Prescaler rate divi-
sion factor for the receive circuit.
Allows setting of the External Prescaler rate divi-
sion factor for the transmit circuit.
7
0
7
0
ERPR ERPR ERPR ERPR ERPR ERPR ERPR ERPR
ETPR ETPR ETPR ETPR ETPR ETPR ETPR ETPR
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Bits 7:0 = ERPR[7:0] 8-bit Extended Receive
Prescaler Register.
Bits 7:0 = ETPR[7:0] 8-bit Extended Transmit
Prescaler Register.
The extended Baud Rate Generator is activated
when a value different from 00h is stored in this
register. Therefore the clock frequency issued
from the 16 divider (see Figure 55) is divided by
the binary factor set in the SCIERPR register (in
the range 1 to 255).
The extended Baud Rate Generator is activated
when a value different from 00h is stored in this
register. Therefore the clock frequency issued
from the 16 divider (see Figure 55) is divided by
the binary factor set in the SCIETPR register (in
the range 1 to 255).
The extended baud rate generator is not used af-
ter a reset.
The extended baud rate generator is not used af-
ter a reset.
Table 21. Baudrate Selection
Conditions
Baud
Rate
Symbol
Parameter
Standard
Unit
Accuracy
vs. Standard
Prescaler
f
CPU
Conventional Mode
TR (or RR)=128, PR=13
TR (or RR)= 32, PR=13
TR (or RR)= 16, PR=13
TR (or RR)= 8, PR=13
TR (or RR)= 4, PR=13
TR (or RR)= 16, PR= 3
TR (or RR)= 2, PR=13
TR (or RR)= 1, PR=13
300
~300.48
1200 ~1201.92
2400 ~2403.84
4800 ~4807.69
9600 ~9615.38
10400 ~10416.67
19200 ~19230.77
38400 ~38461.54
~0.16%
~0.79%
f
f
Tx
Communication frequency 8MHz
Hz
Rx
Extended Mode
ETPR (or ERPR) = 35,
TR (or RR)= 1, PR=1
14400 ~14285.71
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ST72324
SERIAL COMMUNICATION INTERFACE (Cont’d)
Table 22. SCI Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
SCISR
Reset Value
TDRE
1
TC
1
RDRF
0
IDLE
0
OR
0
NF
0
FE
0
PE
0
0050h
0051h
0052h
0053h
0054h
0055h
0057h
SCIDR
Reset Value
MSB
x
LSB
x
x
x
x
x
x
x
SCIBRR
Reset Value
SCP1
0
SCP0
0
SCT2
0
SCT1
0
SCT0
0
SCR2
0
SCR1
0
SCR0
0
SCICR1
Reset Value
R8
x
T8
0
SCID
0
M
0
WAKE
0
PCE
0
PS
0
PIE
0
SCICR2
Reset Value
TIE
0
TCIE
0
RIE
0
ILIE
0
TE
0
RE
0
RWU
0
SBK
0
SCIERPR
Reset Value
MSB
0
LSB
0
0
0
0
0
0
0
0
0
0
0
0
0
SCIPETPR
Reset Value
MSB
0
LSB
0
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ST72324
10.6 10-BIT A/D CONVERTER (ADC)
10.6.1 Introduction
10.6.2 Main Features
■ 10-bit conversion
The on-chip Analog to Digital Converter (ADC) pe-
ripheral is a 10-bit, successive approximation con-
verter with internal sample and hold circuitry. This
peripheral has up to 16 multiplexed analog input
channels (refer to device pin out description) that
allow the peripheral to convert the analog voltage
levels from up to 16 different sources.
■ Up to 16 channels with multiplexed input
■ Linear successive approximation
■ Data register (DR) which contains the results
■ Conversion complete status flag
■ On/off bit (to reduce consumption)
The block diagram is shown in Figure 57.
The result of the conversion is stored in a 10-bit
Data Register. The A/D converter is controlled
through a Control/Status Register.
Figure 57. ADC Block Diagram
f
CPU
DIV 4
DIV 2
0
1
f
ADC
CH3
EOC SPEEDADON
0
CH2 CH1 CH0
ADCCSR
4
AIN0
AIN1
ANALOG TO DIGITAL
CONVERTER
ANALOG
MUX
AINx
ADCDRH
D9 D8 D7 D6 D5 D4
D3
D2
ADCDRL
0
0
0
0
0
0
D1
D0
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ST72324
10-BIT A/D CONVERTER (ADC) (Cont’d)
10.6.3 Functional Description
The conversion is monotonic, meaning that the re-
sult never decreases if the analog input does not
and never increases if the analog input does not.
To read the 10 bits, perform the following steps:
1. Poll the EOC bit
2. Read the ADCDRL register
If the input voltage (V ) is greater than V
AIN
AREF
3. Read the ADCDRH register. This clears EOC
automatically.
(high-level voltage reference) then the conversion
result is FFh in the ADCDRH register and 03h in
the ADCDRL register (without overflow indication).
Note: The data is not latched, so both the low and
the high data register must be read before the next
conversion is complete, so it is recommended to
disable interrupts while reading the conversion re-
sult.
If the input voltage (V ) is lower than V
(low-
SSA
AIN
level voltage reference) then the conversion result
in the ADCDRH and ADCDRL registers is 00 00h.
The A/D converter is linear and the digital result of
the conversion is stored in the ADCDRH and AD-
CDRL registers. The accuracy of the conversion is
described in the Electrical Characteristics Section.
To read only 8 bits, perform the following steps:
1. Poll the EOC bit
2. Read the ADCDRH register. This clears EOC
automatically.
R
is the maximum recommended impedance
AIN
for an analog input signal. If the impedance is too
high, this will result in a loss of accuracy due to
leakage and sampling not being completed in the
alloted time.
10.6.3.3 Changing the conversion channel
The application can change channels during con-
version. When software modifies the CH[3:0] bits
in the ADCCSR register, the current conversion is
stopped, the EOC bit is cleared, and the A/D con-
verter starts converting the newly selected chan-
nel.
10.6.3.1 A/D Converter Configuration
The analog input ports must be configured as in-
put, no pull-up, no interrupt. Refer to the «I/O
ports» chapter. Using these pins as analog inputs
does not affect the ability of the port to be read as
a logic input.
10.6.4 Low Power Modes
Note: The A/D converter may be disabled by re-
setting the ADON bit. This feature allows reduced
power consumption when no conversion is need-
ed.
In the ADCCSR register:
– Select the CS[3:0] bits to assign the analog
channel to convert.
10.6.3.2 Starting the Conversion
Mode
Description
WAIT
No effect on A/D Converter
A/D Converter disabled.
In the ADCCSR register:
– Set the ADON bit to enable the A/D converter
and to start the conversion. From this time on,
the ADC performs a continuous conversion of
the selected channel.
After wakeup from Halt mode, the A/D
Converter requires a stabilization time
HALT
t
(see Electrical Characteristics)
STAB
before accurate conversions can be
performed.
When a conversion is complete:
– The EOC bit is set by hardware.
– The result is in the ADCDR registers.
A read to the ADCDRH resets the EOC bit.
10.6.5 Interrupts
None.
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1
ST72324
10-BIT A/D CONVERTER (ADC) (Cont’d)
10.6.6 Register Description
CONTROL/STATUS REGISTER (ADCCSR)
Read/Write (Except bit 7 read only)
Reset Value: 0000 0000 (00h)
Bit 3:0 = CH[3:0] Channel Selection
These bits are set and cleared by software. They
select the analog input to convert.
Channel Pin*
CH3 CH2 CH1 CH0
7
0
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
EOC SPEED ADON
0
CH3
CH2
CH1
CH0
Bit 7 = EOC End of Conversion
This bit is set by hardware. It is cleared by hard-
ware when software reads the ADCDRH register
or writes to any bit of the ADCCSR register.
0: Conversion is not complete
1: Conversion complete
AIN9
AIN10
AIN11
AIN12
AIN13
AIN14
AIN15
Bit 6 = SPEED ADC clock selection
This bit is set and cleared by software.
0: f
1: f
= f
= f
/4
/2
ADC
ADC
CPU
CPU
*The number of channels is device dependent. Refer to
the device pinout description.
Bit 5 = ADON A/D Converter on
This bit is set and cleared by software.
0: Disable ADC and stop conversion
1: Enable ADC and start conversion
DATA REGISTER (ADCDRH)
Read Only
Bit 4 = Reserved. Must be kept cleared.
Reset Value: 0000 0000 (00h)
7
0
D9
D8
D7
D6
D5
D4
D3
D2
Bit 7:0 = D[9:2] MSB of Converted Analog Value
DATA REGISTER (ADCDRL)
Read Only
Reset Value: 0000 0000 (00h)
7
0
0
0
0
0
0
0
D1
D0
Bit 7:2 = Reserved. Forced by hardware to 0.
Bit 1:0 = D[1:0] LSB of Converted Analog Value
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ST72324
10-BIT A/D CONVERTER (Cont’d)
Table 23. ADC Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
ADCCSR
Reset Value
EOC
0
SPEED
0
ADON
0
CH3
0
CH2
0
CH1
0
CH0
0
0070h
0071h
0072h
0
ADCDRH
Reset Value
D9
0
D8
0
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
ADCDRL
Reset Value
D1
0
D0
0
0
0
0
0
0
0
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ST72324
11 INSTRUCTION SET
11.1 CPU ADDRESSING MODES
so, most of the addressing modes may be subdi-
vided in two sub-modes called long and short:
The CPU features 17 different addressing modes
which can be classified in 7 main groups:
– Long addressing mode is more powerful be-
cause it can use the full 64 Kbyte address space,
however it uses more bytes and more CPU cy-
cles.
Addressing Mode
Inherent
Example
nop
– Short addressing mode is less powerful because
it can generally only access page zero (0000h -
00FFh range), but the instruction size is more
compact, and faster. All memory to memory in-
structions use short addressing modes only
(CLR, CPL, NEG, BSET, BRES, BTJT, BTJF,
INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP)
Immediate
Direct
ld A,#$55
ld A,$55
ld A,($55,X)
ld A,([$55],X)
jrne loop
Indexed
Indirect
Relative
Bit operation
bset byte,#5
The ST7 Assembler optimizes the use of long and
short addressing modes.
The CPU Instruction set is designed to minimize
the number of bytes required per instruction: To do
Table 24. CPU Addressing Mode Overview
Pointer
Address
(Hex.)
Pointer Size
(Hex.)
Length
(Bytes)
Mode
Syntax
Destination
Inherent
Immediate
Short
Long
nop
+ 0
ld A,#$55
+ 1
+ 1
+ 2
+ 0
+ 1
+ 2
+ 2
+ 2
+ 2
+ 2
+ 1
+ 2
+ 1
+ 2
+ 2
+ 3
Direct
Direct
Direct
Direct
Direct
Indirect
Indirect
ld A,$10
00..FF
ld A,$1000
ld A,(X)
0000..FFFF
00..FF
No Offset
Short
Long
Indexed
Indexed
Indexed
ld A,($10,X)
ld A,($1000,X)
ld A,[$10]
00..1FE
0000..FFFF
00..FF
Short
Long
00..FF
byte
word
byte
word
ld A,[$10.w]
ld A,([$10],X)
ld A,([$10.w],X)
jrne loop
0000..FFFF 00..FF
00..1FE 00..FF
Short
Long
Indirect Indexed
Indirect Indexed
Direct
0000..FFFF 00..FF
PC+/-127
Relative
Relative
Bit
Indirect
jrne [$10]
PC+/-127
00..FF
00..FF
00..FF
00..FF
00..FF
00..FF
00..FF
byte
byte
byte
Direct
bset $10,#7
bset [$10],#7
Bit
Indirect
Bit
Direct
Relative btjt $10,#7,skip
Bit
Indirect Relative btjt [$10],#7,skip
110/163
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ST72324
INSTRUCTION SET OVERVIEW (Cont’d)
11.1.1 Inherent
11.1.3 Direct
All Inherent instructions consist of a single byte.
The opcode fully specifies all the required informa-
tion for the CPU to process the operation.
In Direct instructions, the operands are referenced
by their memory address.
The direct addressing mode consists of two sub-
modes:
Inherent Instruction
Function
No operation
Direct (short)
NOP
The address is a byte, thus requires only one byte
after the opcode, but only allows 00 - FF address-
ing space.
TRAP
S/W Interrupt
Wait For Interrupt (Low Pow-
er Mode)
WFI
Direct (long)
Halt Oscillator (Lowest Power
Mode)
HALT
The address is a word, thus allowing 64 Kbyte ad-
dressing space, but requires 2 bytes after the op-
code.
RET
Sub-routine Return
Interrupt Sub-routine Return
Set Interrupt Mask (level 3)
Reset Interrupt Mask (level 0)
Set Carry Flag
IRET
SIM
11.1.4 Indexed (No Offset, Short, Long)
RIM
In this mode, the operand is referenced by its
memory address, which is defined by the unsigned
addition of an index register (X or Y) with an offset.
SCF
RCF
Reset Carry Flag
RSP
Reset Stack Pointer
Load
The indirect addressing mode consists of three
sub-modes:
LD
CLR
Clear
Indexed (No Offset)
PUSH/POP
INC/DEC
TNZ
Push/Pop to/from the stack
Increment/Decrement
Test Negative or Zero
1 or 2 Complement
Byte Multiplication
There is no offset, (no extra byte after the opcode),
and allows 00 - FF addressing space.
Indexed (Short)
CPL, NEG
MUL
The offset is a byte, thus requires only one byte af-
ter the opcode and allows 00 - 1FE addressing
space.
SLL, SRL, SRA, RLC,
RRC
Shift and Rotate Operations
Swap Nibbles
Indexed (long)
SWAP
The offset is a word, thus allowing 64 Kbyte ad-
dressing space and requires 2 bytes after the op-
code.
11.1.2 Immediate
Immediate instructions have two bytes, the first
byte contains the opcode, the second byte con-
tains the operand value.
11.1.5 Indirect (Short, Long)
The required data byte to do the operation is found
by its memory address, located in memory (point-
er).
Immediate Instruction
Function
LD
Load
The pointer address follows the opcode. The indi-
rect addressing mode consists of two sub-modes:
CP
Compare
BCP
Bit Compare
Indirect (short)
AND, OR, XOR
ADC, ADD, SUB, SBC
Logical Operations
Arithmetic Operations
The pointer address is a byte, the pointer size is a
byte, thus allowing 00 - FF addressing space, and
requires 1 byte after the opcode.
Indirect (long)
The pointer address is a byte, the pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.
111/163
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ST72324
INSTRUCTION SET OVERVIEW (Cont’d)
11.1.6 Indirect Indexed (Short, Long)
11.1.7 Relative mode (Direct, Indirect)
This is a combination of indirect and short indexed
addressing modes. The operand is referenced by
its memory address, which is defined by the un-
signed addition of an index register value (X or Y)
with a pointer value located in memory. The point-
er address follows the opcode.
This addressing mode is used to modify the PC
register value, by adding an 8-bit signed offset to
it.
Available Relative
Direct/Indirect
Instructions
Function
The indirect indexed addressing mode consists of
two sub-modes:
JRxx
CALLR
Conditional Jump
Call Relative
Indirect Indexed (Short)
The pointer address is a byte, the pointer size is a
byte, thus allowing 00 - 1FE addressing space,
and requires 1 byte after the opcode.
The relative addressing mode consists of two sub-
modes:
Relative (Direct)
Indirect Indexed (Long)
The offset is following the opcode.
Relative (Indirect)
The pointer address is a byte, the pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.
The offset is defined in memory, which address
follows the opcode.
Table 25. Instructions Supporting Direct,
Indexed, Indirect and Indirect Indexed
Addressing Modes
Long and Short
Function
Instructions
LD
Load
CP
Compare
AND, OR, XOR
Logical Operations
Arithmetic Additions/Sub-
stractions operations
ADC, ADD, SUB, SBC
BCP
Bit Compare
Short Instructions
Only
Function
CLR
Clear
INC, DEC
TNZ
Increment/Decrement
Test Negative or Zero
1 or 2 Complement
Bit Operations
CPL, NEG
BSET, BRES
Bit Test and Jump Opera-
tions
BTJT, BTJF
SLL, SRL, SRA, RLC,
RRC
Shift and Rotate Opera-
tions
SWAP
Swap Nibbles
CALL, JP
Call or Jump subroutine
112/163
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ST72324
INSTRUCTION SET OVERVIEW (Cont’d)
11.2 INSTRUCTION GROUPS
The ST7 family devices use an Instruction Set
consisting of 63 instructions. The instructions may
be subdivided into 13 main groups as illustrated in
the following table:
Load and Transfer
LD
CLR
POP
DEC
TNZ
OR
Stack operation
PUSH
INC
RSP
BCP
Increment/Decrement
Compare and Tests
Logical operations
CP
AND
BSET
BTJT
ADC
SLL
XOR
CPL
NEG
Bit Operation
BRES
BTJF
ADD
SRL
JRT
Conditional Bit Test and Branch
Arithmetic operations
Shift and Rotates
SUB
SRA
JRF
SBC
RLC
JP
MUL
RRC
CALL
SWAP
CALLR
SLA
Unconditional Jump or Call
Conditional Branch
JRA
JRxx
TRAP
SIM
NOP
RET
Interruption management
Condition Code Flag modification
WFI
RIM
HALT
SCF
IRET
RCF
Using a pre-byte
The instructions are described with one to four op-
codes.
These prebytes enable instruction in Y as well as
indirect addressing modes to be implemented.
They precede the opcode of the instruction in X or
the instruction using direct addressing mode. The
prebytes are:
In order to extend the number of available op-
codes for an 8-bit CPU (256 opcodes), three differ-
ent prebyte opcodes are defined. These prebytes
modify the meaning of the instruction they pre-
cede.
PDY 90
Replace an X based instruction
using immediate, direct, indexed, or inherent ad-
dressing mode by a Y one.
The whole instruction becomes:
PIX 92
Replace an instruction using di-
PC-2
PC-1
PC
End of previous instruction
Prebyte
rect, direct bit, or direct relative addressing mode
to an instruction using the corresponding indirect
addressing mode.
opcode
It also changes an instruction using X indexed ad-
dressing mode to an instruction using indirect X in-
dexed addressing mode.
PC+1
Additional word (0 to 2) according
to the number of bytes required to compute the ef-
fective address
PIY 91
Replace an instruction using X in-
direct indexed addressing mode by a Y one.
113/163
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ST72324
INSTRUCTION SET OVERVIEW (Cont’d)
Mnemo
ADC
ADD
AND
BCP
Description
Add with Carry
Function/Example
A = A + M + C
A = A + M
Dst
Src
I1
H
H
H
I0
N
N
N
N
N
Z
Z
Z
Z
Z
C
C
C
A
M
Addition
A
M
M
M
Logical And
A = A . M
A
Bit compare A, Memory
Bit Reset
tst (A . M)
A
BRES
BSET
BTJF
BTJT
CALL
CALLR
CLR
bres Byte, #3
bset Byte, #3
btjf Byte, #3, Jmp1
btjt Byte, #3, Jmp1
M
M
M
M
Bit Set
Jump if bit is false (0)
Jump if bit is true (1)
Call subroutine
Call subroutine relative
Clear
C
C
reg, M
reg
0
1
Z
Z
Z
CP
Arithmetic Compare
One Complement
Decrement
tst(Reg - M)
A = FFH-A
dec Y
M
N
N
N
C
1
CPL
reg, M
reg, M
DEC
HALT
IRET
INC
Halt
1
0
Interrupt routine return
Increment
Pop CC, A, X, PC
inc X
I1
H
I0
N
N
Z
Z
C
reg, M
JP
Absolute Jump
Jump relative always
Jump relative
jp [TBL.w]
JRA
JRT
JRF
Never jump
jrf *
JRIH
JRIL
Jump if ext. INT pin = 1
Jump if ext. INT pin = 0
Jump if H = 1
(ext. INT pin high)
(ext. INT pin low)
H = 1?
JRH
JRNH
JRM
Jump if H = 0
H = 0?
Jump if I1:0 = 11
Jump if I1:0 <> 11
Jump if N = 1 (minus)
Jump if N = 0 (plus)
Jump if Z = 1 (equal)
I1:0 = 11?
I1:0 <> 11?
N = 1?
JRNM
JRMI
JRPL
JREQ
JRNE
JRC
N = 0?
Z = 1?
Jump if Z = 0 (not equal) Z = 0?
Jump if C = 1
Jump if C = 0
Jump if C = 1
C = 1?
JRNC
JRULT
C = 0?
Unsigned <
Jmp if unsigned >=
Unsigned >
JRUGE Jump if C = 0
JRUGT Jump if (C + Z = 0)
114/163
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ST72324
INSTRUCTION SET OVERVIEW (Cont’d)
Mnemo
JRULE
LD
Description
Jump if (C + Z = 1)
Load
Function/Example
Unsigned <=
dst <= src
Dst
Src
I1
H
I0
N
N
N
N
N
Z
Z
Z
Z
Z
C
reg, M
A, X, Y
reg, M
M, reg
X, Y, A
MUL
NEG
NOP
OR
Multiply
X,A = X * A
neg $10
0
0
Negate (2's compl)
No Operation
OR operation
C
A = A + M
pop reg
pop CC
push Y
C = 0
A
M
reg
CC
M
M
POP
Pop from the Stack
M
I1
1
H
I0
0
C
0
PUSH
RCF
RET
RIM
Push onto the Stack
Reset carry flag
Subroutine Return
Enable Interrupts
Rotate left true C
Rotate right true C
Reset Stack Pointer
Substract with Carry
Set carry flag
reg, CC
I1:0 = 10 (level 0)
C <= A <= C
C => A => C
S = Max allowed
A = A - M - C
C = 1
RLC
RRC
RSP
SBC
SCF
SIM
reg, M
reg, M
N
N
Z
Z
C
C
A
M
N
Z
C
1
Disable Interrupts
Shift left Arithmetic
Shift left Logic
I1:0 = 11 (level 3)
C <= A <= 0
C <= A <= 0
0 => A => C
A7 => A => C
A = A - M
1
1
SLA
reg, M
reg, M
reg, M
reg, M
A
N
N
0
Z
Z
Z
Z
Z
Z
Z
C
C
C
C
C
SLL
SRL
SRA
SUB
SWAP
TNZ
TRAP
WFI
Shift right Logic
Shift right Arithmetic
Substraction
N
N
N
N
M
M
SWAP nibbles
A7-A4 <=> A3-A0
tnz lbl1
reg, M
Test for Neg & Zero
S/W trap
S/W interrupt
1
1
1
0
Wait for Interrupt
Exclusive OR
XOR
A = A XOR M
A
N
Z
115/163
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ST72324
12 ELECTRICAL CHARACTERISTICS
12.1 PARAMETER CONDITIONS
Unless otherwise specified, all voltages are re-
ferred to V
.
SS
12.1.5 Pin input voltage
12.1.1 Minimum and Maximum values
The input voltage measurement on a pin of the de-
vice is described in Figure 59.
Unless otherwise specified the minimum and max-
imum values are guaranteed in the worst condi-
tions of ambient temperature, supply voltage and
frequencies by tests in production on 100% of the
Figure 59. Pin input voltage
devices with an ambient temperature at T =25°C
A
and T =T max (given by the selected temperature
A
A
ST7 PIN
range).
Data based on characterization results, design
simulation and/or technology characteristics are
indicated in the table footnotes and are not tested
in production. Based on characterization, the min-
imum and maximum values refer to sample tests
and represent the mean value plus or minus three
times the standard deviation (mean 3Σ).
V
IN
12.1.2 Typical values
Unless otherwise specified, typical data are based
on T =25°C, V =5V. They are given only as de-
A
DD
sign guidelines and are not tested.
12.1.3 Typical curves
Unless otherwise specified, all typical curves are
given only as design guidelines and are not tested.
12.1.4 Loading capacitor
The loading conditions used for pin parameter
measurement are shown in Figure 58.
Figure 58. Pin loading conditions
ST7 PIN
C
L
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ST72324
12.2 ABSOLUTE MAXIMUM RATINGS
Stresses above those listed as “absolute maxi-
mum ratings” may cause permanent damage to
the device. This is a stress rating only and func-
tional operation of the device under these condi-
tions is not implied. Exposure to maximum rating
conditions for extended periods may affect device
reliability.
12.2.1 Voltage Characteristics
Symbol
Ratings
Maximum value
Unit
V
- V
- V
Supply voltage
6.5
DD
SS
SS
V
Programming Voltage
13
PP
V
Input Voltage on true open drain pin
VSS-0.3 to 6.5
1) & 2)
V
IN
Input voltage on any other pin
VSS-0.3 to VDD+0.3
|∆V
| and |∆V
|
SSx
Variations between different digital power pins
Variations between digital and analog ground pins
Electro-static discharge voltage (Human Body Model)
Electro-static discharge voltage (Machine Model)
50
50
DDx
mV
|V
- V
|
SSA
SSx
V
ESD(HBM)
see Section 12.8.3 on page 132
V
ESD(MM)
12.2.2 Current Characteristics
Symbol
Ratings
Maximum value
Unit
32-pin devices
44-pin devices
32-pin devices
44-pin devices
75
150
75
150
25
50
- 25
5
Total current into V power lines
(source)
DD
I
mA
3)
VDD
Total current out of V ground lines
SS
I
mA
3)
VSS
(sink)
Output current sunk by any standard I/O and control pin
Output current sunk by any high sink I/O pin
I
IO
Output current source by any I/Os and control pin
Injected current on V pin
PP
Injected current on RESET pin
5
mA
2) & 4)
I
Injected current on OSC1 and OSC2 pins
Injected current on Flash device pin PB0
5
INJ(PIN)
+5
5
5) & 6)
Injected current on any other pin
2)
5)
ΣI
Total injected current (sum of all I/O and control pins)
25
INJ(PIN)
Notes:
1. Directly connecting the RESET and I/O pins to V or V could damage the device if an unintentional internal reset
DD
SS
is generated or an unexpected change of the I/O configuration occurs (for example, due to a corrupted program counter).
To guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7kΩ for
RESET, 10kΩ for I/Os). For the same reason, unused I/O pins must not be directly tied to V or V
.
DD
SS
2. I
must never be exceeded. This is implicitly insured if V maximum is respected. If V maximum cannot be
INJ(PIN)
IN
INJ(PIN)
IN
respected, the injection current must be limited externally to the I
value. A positive injection is induced by V >V
IN DD
while a negative injection is induced by V <V . For true open-drain pads, there is no positive injection current, and the
corresponding V maximum must always be respected
IN
SS
IN
3. All power (V ) and ground (V ) lines must always be connected to the external supply.
DD
SS
4. Negative injection disturbs the analog performance of the device. See note in “ADC Accuracy” on page 145.
For best reliability, it is recommended to avoid negative injection of more than 1.6mA.
5. When several inputs are submitted to a current injection, the maximum ΣI
is the absolute sum of the positive
INJ(PIN)
and negative injected currents (instantaneous values). These results are based on characterisation with ΣI
maxi-
INJ(PIN)
mum current injection on four I/O port pins of the device.
6. True open drain I/O port pins do not accept positive injection.
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ST72324
12.2.3 Thermal Characteristics
Symbol
Ratings
Value
Unit
T
Storage temperature range
-65 to +150
°C
STG
T
Maximum junction temperature (see Section 13.2 THERMAL CHARACTERISTICS)
J
12.3 OPERATING CONDITIONS
12.3.1 Operating Conditions
Symbol
Parameter
Conditions
Min
Max
Unit
f
Internal clock frequency
0
8
MHz
CPU
Operating voltage (except Flash Write/
Erase)
3.8
5.5
V
V
DD
Operating Voltage for Flash Write/Erase
Ambient temperature range
V
= 11.4 to 12.6V
4.5
0
5.5
70
PP
1 Suffix Version
5 Suffix Version
-10
-40
-40
-40
85
T
6 or A Suffix Versions
7 or B Suffix Versions
C Suffix Version
85
°C
A
105
125
Figure 60. f
Max Versus VDD
CPU
f
[MHz]
CPU
FUNCTIONALITY
GUARANTEED
IN THIS AREA
(UNLESS
OTHERWISE
SPECIFIED
IN THE TABLES
OF PARAMETRIC
DATA)
8
6
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
4
2
1
0
3.5
3.8 4.0
4.5
5.5
SUPPLY VOLTAGE [V]
Note: Some temperature ranges are only available with a specific package and memory size. Refer to Or-
dering Information.
Warning: Do not connect 12V to V before V is powered on, as this may damage the device.
PP
DD
118/163
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ST72324
OPERATING CONDITIONS (Cont’d)
12.4 LVD/AVD CHARACTERISTICS
12.4.1 Operating Conditions with Low Voltage Detector (LVD)
Subject to general operating conditions for T
A
Symbol
Parameter
Conditions
VD level = High in option byte
Min
Typ
4.2
Max
4.5
Unit
1)
4.0
Reset release threshold
2)
1)
1)
1)
V
VD level = Med. in option byte 3.55
3.75
3.15
4.0
4.0
IT+(LVD)
(V rise)
DD
2)
1)
VD level = Low in option byte
VD level = High in option byte
VD level = Med. in option byte
2.95
3.8
3.35
4.25
3.75
3.15
V
1)
1)
1)
Reset generation threshold
2)
1)
V
V
3.35
3.55
3.0
IT-(LVD)
hys(LVD)
(V fall)
DD
2)
1)
VD level = Low in option byte
-V
2.8
1)
LVD voltage threshold hysteresis
V
150
200
250
100ms/V
40
mV
ns
IT+(LVD) IT-(LVD)
1)
Vt
V
rise time
DD
6µs/V
POR
1)
t
Filtered glitch delay on V
Not detected by the LVD
g(VDD)
DD
Notes:
1. Data based on characterization results, not tested in production.
2. If the medium or low thresholds are selected, the detection may occur outside the specified operating voltage range.
12.4.2 Auxiliary Voltage Detector (AVD) Thresholds
Subject to general operating conditions for T
A
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
1)
VD level = High in option byte
4.4
4.6
4.9
1⇒0 AVDF flag toggle threshold
1)
1)
V
VD level = Med. in option byte
VD level = Low in option byte
3.95
3.4
4.15
3.6
4.4
3.8
IT+(AVD)
(V rise)
DD
1)
1)
V
1)
VD level = High in option byte
4.2
4.4
4.65
0⇒1 AVDF flag toggle threshold
1)
1)
V
V
VD level = Med. in option byte
VD level = Low in option byte
3.75
3.2
4.0
3.4
4.2
3.6
IT-(AVD)
hys(AVD)
(V fall)
DD
1)
1)
AVD voltage threshold hysteresis
V
-V
200
mV
mV
IT+(AVD) IT-(AVD)
Voltage drop between AVD flag set
and LVD reset activated
∆V
V
-V
450
IT-
IT-(AVD) IT-(LVD)
1. Data based on characterization results not tested in production.
119/163
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ST72324
12.5 SUPPLY CURRENT CHARACTERISTICS
The following current consumption specified for the ST7 functional operating modes over temperature
range does not take into account the clock source current consumption. To get the total device consump-
tion, the two current values must be added (except for HALT mode for which the clock is stopped).
12.5.1 CURRENT CONSUMPTION
Flash Devices
Symbol
Parameter
Conditions
Unit
1)
Typ
Max
f
f
f
f
=2MHz, f
=1MHz
=2MHz
=4MHz
1.3
2.0
3.6
7.1
3.0
5.0
8.0
OSC
OSC
OSC
OSC
CPU
CPU
CPU
=4MHz, f
=8MHz, f
2)
Supply current in RUN mode
mA
=16MHz, f
=8MHz
15.0
CPU
f
f
f
f
=2MHz, f
=4MHz, f
=8MHz, f
=62.5kHz
=125kHz
=250kHz
600
700
2700
3000
3600
4000
OSC
OSC
OSC
OSC
CPU
CPU
CPU
2)
Supply current in SLOW mode
µA
mA
µA
800
=16MHz, f
=500kHz
1100
CPU
f
f
f
f
=2MHz, f
=4MHz, f
=8MHz, f
=1MHz
=2MHz
=4MHz
1.0
1.5
2.5
4.5
3.0
4.0
5.0
7.0
OSC
OSC
OSC
OSC
CPU
CPU
CPU
I
DD
2)
Supply current in WAIT mode
=16MHz, f
=8MHz
CPU
f
f
f
f
=2MHz, f
=4MHz, f
=8MHz, f
=62.5kHz
=125kHz
=250kHz
580
650
770
1050
1200
1300
1800
2000
OSC
OSC
OSC
OSC
CPU
CPU
CPU
2)
Supply current in SLOW WAIT mode
=16MHz, f
=500kHz
CPU
-40°C≤T ≤+85°C
<1
<1
10
50
A
3)
Supply current in HALT mode
-40°C≤T ≤+125°C
A
f
f
f
f
=2MHz
=4MHz
=8MHz
=16MHz
80
OSC
OSC
OSC
OSC
µA
No max.
guaran-
teed
160
325
650
4)
I
Supply current in ACTIVE-HALT mode
DD
Notes:
1. Data based on characterization results, tested in production at V max. and f
max.
CPU
DD
2. Measurements are done in the following conditions:
- Program executed from RAM, CPU running with RAM access. The increase in consumption when executing from Flash
is 50%.
- All I/O pins in input mode with a static value at V or V (no load)
DD
SS
- All peripherals in reset state.
- LVD disabled.
- Clock input (OSC1) driven by external square wave.
- In SLOW and SLOW WAIT mode, f is based on f
divided by 32.
OSC
CPU
To obtain the total current consumption of the device, add the clock source (Section 12.6.3) and the peripheral power
consumption (Section 12.5.3).
3. All I/O pins in push-pull 0 mode (when applicable) with a static value at V or V (no load), LVD disabled. Data based
DD
max.
SS
on characterization results, tested in production at V max. and f
DD
CPU
4. Data based on characterisation results, not tested in production. All I/O pins in push-pull 0 mode (when applicable) with
a static value at V or V (no load); clock input (OSC1) driven by external square wave, LVD disabled. To obtain
DD
SS
the total current consumption of the device, add the clock source consumption (Section 12.6.3).
120/163
1
ST72324
SUPPLY CURRENT CHARACTERISTICS (Cont’d)
12.5.1.1 Power Consumption vs f : Flash Devices
CPU
Figure 61. Typical I in RUN mode
Figure 63. Typical I in WAIT mode
DD
DD
8MHz
9
8MHz
6
5
4
3
2
1
0
4MHz
2MHz
4MHz
2MHz
1MHz
8
1MHz
7
6
5
4
3
2
1
0
4
4.4
4.8
5.2
5.5
4
4.4
4.8
5.2
5.5
Vdd (V)
Vdd (V)
Figure 62. Typical I in SLOW mode
Figure 64. Typ. I in SLOW-WAIT mode
DD
DD
500kHz
1.20
1.20
500kHz
250kHz
250kHz
125kHz
62.5kHz
125kHz
62.5kHz
0.80
1.00
0.80
0.60
0.40
0.20
0.00
1.00
0.60
0.40
0.20
0.00
4
4.4
4.8
5.2
5.5
4
4.4
4.8
5.2
5.5
Vdd (V)
Vdd (V)
121/163
1
ST72324
SUPPLY CURRENT CHARACTERISTICS (Cont’d)
12.5.2 Supply and Clock Managers
The previous current consumption specified for the ST7 functional operating modes over temperature
range does not take into account the clock source current consumption. To get the total device consump-
tion, the two current values must be added (except for HALT mode).
Symbol
Parameter
Conditions
Typ
Max
Unit
I
Supply current of internal RC oscillator
625
DD(RCINT)
see Section
12.6.3 on page
125
µA
1) & 2)
I
Supply current of resonator oscillator
DD(RES)
µA
I
PLL supply current
LVD supply current
V
V
= 5V
= 5V
360
DD(PLL)
DD
DD
I
150
300
DD(LVD)
Notes:
1. Data based on characterization results done with the external components specified in Section 12.6.3, not tested in
production.
2. As the oscillator is based on a current source, the consumption does not depend on the voltage.
122/163
1
ST72324
SUPPLY CURRENT CHARACTERISTICS (Cont’d)
12.5.3 On-Chip Peripherals
T = 25°C f
=4MHz.
A
CPU
Symbol
Parameter
Conditions
=5.0V
Typ
50
Unit
1)
I
16-bit Timer supply current
V
V
V
V
DD(TIM)
DD
DD
DD
DD
2)
I
SPI supply current
=5.0V
400
400
400
DD(SPI)
µA
3)
I
SCI supply current
=5.0V
DD(SCI)
4)
I
ADC supply current when converting
=5.0V
DD(ADC)
Notes:
1. Data based on a differential I measurement between reset configuration (timer counter running at f
/4) and timer
DD
CPU
counter stopped (only TIMD bit set). Data valid for one timer.
2. Data based on a differential I measurement between reset configuration (SPI disabled) and a permanent SPI master
DD
communication at maximum speed (data sent equal to 55h). This measurement includes the pad toggling consump-
tion.
3. Data based on a differential I measurement between SCI low power state (SCID=1) and a permanent SCI data trans-
DD
mit sequence.
4. Data based on a differential I measurement between reset configuration and continuous A/D conversions.
DD
123/163
1
ST72324
12.6 CLOCK AND TIMING CHARACTERISTICS
Subject to general operating conditions for V , f
, and T .
DD CPU
A
12.6.1 General Timings
1)
Symbol
Parameter
Conditions
Min
2
Typ
Max
12
Unit
tCPU
ns
3
t
Instruction cycle time
c(INST)
f
f
=8MHz
250
10
375
1500
22
CPU
CPU
2)
tCPU
µs
Interrupt reaction time
t
v(IT)
t
= ∆t
+ 10
c(INST)
=8MHz
1.25
2.75
v(IT)
12.6.2 External Clock Source
Symbol
Parameter
Conditions
Min
-1
Typ
Max
Unit
V
OSC1 input pin high level voltage
OSC1 input pin low level voltage
V
V
DD
OSC1H
DD
V
V
V
V
+1
SS
OSC1L
SS
t
t
3)
w(OSC1H)
see Figure 65
OSC1 high or low time
5
w(OSC1L)
ns
t
t
3)
r(OSC1)
OSC1 rise or fall time
15
1
f(OSC1)
I
OSC1 Input leakage current
V
≤V ≤V
DD
µA
L
SS
IN
Figure 65. Typical Application with an External Clock Source
90%
V
V
OSC1H
OSC1L
10%
t
t
w(OSC1H)
t
t
w(OSC1L)
f(OSC1)
r(OSC1)
OSC2
Not connected internally
f
OSC
EXTERNAL
CLOCK SOURCE
I
L
OSC1
ST72XXX
Notes:
1. Data based on typical application software.
2. Time measured between interrupt event and interrupt vector fetch. ∆tc(INST) is the number of tCPU cycles needed to finish
the current instruction execution.
3. Data based on design simulation and/or technology characteristics, not tested in production.
124/163
1
ST72324
CLOCK AND TIMING CHARACTERISTICS (Cont’d)
12.6.3 Crystal and Ceramic Resonator Oscillators
The ST7 internal clock can be supplied with four
different Crystal/Ceramic resonator oscillators. All
the information given in this paragraph are based
on characterization results with specified typical
external components. In the application, the reso-
nator and the load capacitors have to be placed as
close as possible to the oscillator pins in order to
minimize output distortion and start-up stabiliza-
tion time. Refer to the crystal/ceramic resonator
manufacturer for more details (frequency, pack-
age, accuracy...).
Symbol
Parameter
Conditions
Min
Max
Unit
MHz
kΩ
LP: Low power oscillator
1
2
4
8
MP: Medium power oscillator
MS: Medium speed oscillator
HS: High speed oscillator
>2
>4
>8
1)
f
Oscillator Frequency
OSC
16
2)
R
Feedback resistor
20
40
F
R =200Ω
LP oscillator
MP oscillator
MS oscillator
HS oscillator
22
22
18
15
56
46
33
33
S
Recommended load capacitance ver-
sus equivalent serial resistance of the
C
C
R =200Ω
L1
L2
S
pF
R =200Ω
S
crystal or ceramic resonator (R )
S
R =100Ω
S
Symbol
Parameter
Conditions
Typ
Max
Unit
V =V
LP oscillator
MP oscillator
MS oscillator
HS oscillator
80
150
250
460
910
IN
SS
160
310
610
i
OSC2 driving current
µA
2
Figure 66. Typical Application with a Crystal or Ceramic Resonator
WHEN RESONATOR WITH
INTEGRATED CAPACITORS
i
2
f
OSC
C
L1
OSC1
OSC2
RESONATOR
R
F
C
L2
ST72XXX
Notes:
1. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small R value.
S
Refer to crystal/ceramic resonator manufacturer for more details.
2. Data based on characterisation results, not tested in production.
125/163
1
ST72324
CLOCK AND TIMING CHARACTERISTICS (Cont’d)
Typical Ceramic Resonators (information for guidance only)
C
C
L2
t
L1
SU(osc)
2)
Oscil.
3)
1)
[ms]
[pF] [pF]
22 22
22 22
33 33
33 33
Reference
CSA2.00MG
CSA4.00MG
CSA8.00MTZ
Freq.
2MHz
4MHz
8MHz
16MHz
Characteristic
LP
MP
MS
HS
∆f
∆f
∆f
∆f
=[ 0.5%
=[ 0.5%
=[ 0.5%
=[ 0.5%
, 0.3% , 0.3%
, x.x%
, x.x%
, x.x%
, x.x%
]
]
]
]
4
2
OSC
OSC
OSC
OSC
tolerance
tolerance
tolerance
tolerance
∆Ta
aging
aging
aging
aging
correl
correl
correl
correl
, 0.3% , 0.3%
∆Ta
, 0.5% , 0.3%
1
∆Ta
4)
CSA16.00MXZ040
, 0.3% , 0.3%
0.7
∆Ta
Notes:
1. Resonator characteristics given by the ceramic resonator manufacturer.
2. t
is the typical oscillator start-up time measured between V =2.8V and the fetch of the first instruction (with a
SU(OSC)
DD
quick V ramp-up from 0 to 5V (<50µs).
DD
3. Resonators all have different characteristics. Contact the manufacturer to obtain the appropriate values of external
components and to verify oscillator performance.
4. 3rd overtone resonators require specific validation by the resonator manufacturer.
126/163
1
ST72324
CLOCK CHARACTERISTICS (Cont’d)
12.6.4 RC Oscillators
Symbol
Parameter
Internal RC oscillator frequency
See Figure 67
Conditions
Min
Typ
Max
5.6
Unit
T =25°C, V =5V
f
2
3.5
MHz
A
DD
OSC (RCINT)
Figure 67. Typical f
vs T
A
Note: To reduce disturbance to the RC oscillator,
OSC(RCINT)
it is recommended to place decoupling capacitors
between V and V as shown in Figure 86
DD
SS
4
3.8
3.6
3.4
3.2
3
Vdd = 5V
Vdd = 5.5V
-45
0
25
70
130
TA(°C)
127/163
1
ST72324
CLOCK CHARACTERISTICS (Cont’d)
12.6.5 PLL Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
f
PLL input frequency range
2
4
MHz
OSC
Flash ST72F324,
= 4 MHz.
1.0
2.5
2.5
4.0
f
OSC
1)
∆ f
/ f
Instantaneous PLL jitter
%
CPU CPU
Flash ST72F324,
= 2 MHz.
f
OSC
Note:
1. Data characterized but not tested.
The user must take the PLL jitter into account in the application (for example in serial communication or
sampling of high frequency signals). The PLL jitter is a periodic effect, which is integrated over several
CPU cycles. Therefore the longer the period of the application signal, the less it will be impacted by the
PLL jitter.
Figure 68 shows the PLL jitter integrated on application signals in the range 125kHz to 2MHz. At frequen-
cies of less than 125KHz, the jitter is negligible.
1
Figure 68. Integrated PLL Jitter vs signal frequency
+/-Jitter (%)
1.2
FLASH typ
1
ROM max
ROM typ
0.8
0.6
0.4
0.2
0
4 MHz 2 MHz 1 MHz 500 kHz 250 kHz 125 kHz
Application Frequency
Note 1: Measurement conditions: f
= 8MHz.
CPU
128/163
1
ST72324
12.7 MEMORY CHARACTERISTICS
12.7.1 RAM and Hardware Registers
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
1)
V
Data retention mode
HALT mode (or RESET)
1.6
V
RM
12.7.2 FLASH Memory
DUAL VOLTAGE HDFLASH MEMORY
2)
2)
Symbol
Parameter
Conditions
Read mode
Min
0
Typ
Max
8
Unit
f
Operating frequency
MHz
CPU
Write / Erase mode
4.5V ≤ VDD ≤ 5.5V
Write / Erase
1
8
3)
V
Programming voltage
11.4
12.6
V
mA
PP
4)
I
Supply current
0
DD
Read (V =12V)
200
30
µA
PP
4)
I
V
current
PP
PP
Write / Erase
mA
t
t
Internal V stabilization time
10
µs
VPP
PP
Data retention
T =55°C
20
years
cycles
RET
A
N
Write erase cycles
T =25°C
100
RW
A
T
Programming or erasing tempera-
ture range
PROG
-40
25
85
°C
T
ERASE
Notes:
1. Minimum V supply voltage without losing data stored in RAM (in HALT mode or under RESET) or in hardware reg-
DD
isters (only in HALT mode). Not tested in production.
2. Data based on characterization results, not tested in production.
3. V must be applied only during the programming or erasing operation and not permanently for reliability reasons.
PP
4. Data based on simulation results, not tested in production.
129/163
1
ST72324
12.8 EMC CHARACTERISTICS
should be noted that good EMC performance is
highly dependent on the user application and the
software in particular.
Susceptibility tests are performed on a sample ba-
sis during product characterization.
Therefore it is recommended that the user applies
EMC software optimization and prequalification
tests in relation with the EMC level requested for
his application.
12.8.1 Functional EMS (Electro Magnetic
Susceptibility)
Based on a simple running application on the
product (toggling 2 LEDs through I/O ports), the
product is stressed by two electro magnetic events
until a failure occurs (indicated by the LEDs).
■ ESD: Electro-Static Discharge (positive and
negative) is applied on all pins of the device until
a functional disturbance occurs. This test
conforms with the IEC 1000-4-2 standard.
Software recommendations:
The software flowchart must include the manage-
ment of runaway conditions such as:
– Corrupted program counter
– Unexpected reset
– Critical Data corruption (control registers...)
Prequalification trials:
■ FTB: A Burst of Fast Transient voltage (positive
and negative) is applied to V and V through
DD
SS
a 100pF capacitor, until a functional disturbance
occurs. This test conforms with the IEC 1000-4-
4 standard.
Most of the common failures (unexpected reset
and program counter corruption) can be repro-
duced by manually forcing a low state on the RE-
SET pin or the Oscillator pins for 1 second.
A device reset allows normal operations to be re-
sumed. The test results are given in the table be-
low based on the EMS levels and classes defined
in application note AN1709.
To complete these trials, ESD stress can be ap-
plied directly on the device, over the range of
specification values. When unexpected behaviour
is detected, the software can be hardened to pre-
vent unrecoverable errors occurring (see applica-
tion note AN1015)
12.8.1.1 Designing hardened software to avoid
noise problems
EMC characterization and optimization are per-
formed at component level with a typical applica-
tion environment and simplified MCU software. It
.
Level/
Symbol
Parameter
Conditions
Class
8 or 16K Flash device, V =5V,
DD
Voltage limits to be applied on any I/O pin to induce a
functional disturbance
V
T =+25°C, f
=8MHz conforms to IEC
4B
4A
FESD
A
OSC
1000-4-2
Fast transient voltage burst limits to be applied
V
=5V, T =+25°C, f
=8MHz
OSC
DD
A
V
through 100pF on V and V pins to induce a func-
FFTB
DD DD
conforms to IEC 1000-4-4
tional disturbance
130/163
1
ST72324
EMC CHARACTERISTICS (Cont’d)
12.8.2 Electro Magnetic Interference (EMI)
Based on a simple application running on the
product (toggling 2 LEDs through the I/O ports),
the product is monitored in terms of emission. This
emission test is in line with the norm SAE J 1752/
3 which specifies the board and the loading of
each pin.
Max vs. [f
/f
]
Monitored
Frequency Band
OSC CPU
Symbol
Parameter
Conditions
Device/ Package
Unit
8/4MHz 16/8MHz
0.1MHz to 30MHz
30MHz to 130MHz
130MHz to 1GHz
SAE EMI Level
12
19
15
3
18
25
22
3.5
21
31
28
4.0
27
36
23
3.5
dBµV
8/16K Flash/
TQFP44
-
0.1MHz to 30MHz
30MHz to 130MHz
130MHz to 1GHz
SAE EMI Level
20
26
22
3.5
25
30
18
3.0
V
=5V,
DD
dBµV
T =+25°C
conforming to
A
S
Peak level
32K Flash/TQFP44
Flash/TQFP32
EMI
SAE J 1752/3
-
dBµV
-
0.1MHz to 30MHz
30MHz to 130MHz
130MHz to 1GHz
SAE EMI Level
Notes:
1. Data based on characterization results, not tested in production.
2. Refer to Application Note AN1709 for data on other package types.
131/163
1
ST72324
EMC CHARACTERISTICS (Cont’d)
12.8.3 Absolute Maximum Ratings (Electrical
Sensitivity)
12.8.3.1 Electro-Static Discharge (ESD)
Electro-Static Discharges (a positive then a nega-
tive pulse separated by 1 second) are applied to
the pins of each sample according to each pin
combination. The sample size depends on the
number of supply pins in the device (3 parts*(n+1)
supply pin). Two models can be simulated: Human
Body Model and Machine Model. This test con-
forms to the JESD22-A114A/A115A standard.
Based on three different tests (ESD, LU and DLU)
using specific measurement methods, the product
is stressed in order to determine its performance in
terms of electrical sensitivity. For more details, re-
fer to the application note AN1181.
Absolute Maximum Ratings
1)
Symbol
Ratings
Conditions
Maximum value
Unit
Electro-static discharge voltage
(Human Body Model)
T =+25°C
V
2000
A
ESD(HBM)
Electro-static discharge voltage
(Machine Model)
T =+25°C
V
200
250
V
A
ESD(MM)
Electro-static discharge voltage
(Charged Device Model)
T =+25°C
V
A
ESD(CD)
Notes:
1. Data based on characterization results, not tested in production.
12.8.3.2 Static and Dynamic Latch-Up
■ DLU: Electro-Static Discharges (one positive
then one negative test) are applied to each pin
of 3 samples when the micro is running to
assess the latch-up performance in dynamic
mode. Power supplies are set to the typical
values, the oscillator is connected as near as
possible to the pins of the micro and the
component is put in reset mode. This test
conforms to the IEC1000-4-2 and SAEJ1752/3
standards. For more details, refer to the
application note AN1181.
■ LU: 3 complementary static tests are required
on 10 parts to assess the latch-up performance.
A supply overvoltage (applied to each power
supply pin) and a current injection (applied to
each input, output and configurable I/O pin) are
performed on each sample. This test conforms
to the EIA/JESD 78 IC latch-up standard. For
more details, refer to the application note
AN1181.
Electrical Sensitivities
1)
Symbol
Parameter
Static latch-up class
Dynamic latch-up class
Conditions
Class
T =+25°C
A
A
A
A
LU
T =+85°C
A
T =+125°C
A
V
=5.5V, f
=4MHz, T =+25°C
OSC A
DLU
A
DD
Notes:
1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC spec-
ifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the
JEDEC criteria (international standard).
132/163
1
ST72324
12.9 I/O PORT PIN CHARACTERISTICS
12.9.1 General Characteristics
Subject to general operating conditions for V , f
, and T unless otherwise specified.
A
DD OSC
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Input low level voltage (standard voltage
V
0.3xVDD
V
1)
IL
devices)
1)
V
Input high level voltage
0.7xVDD
0
IH
V
2)
V
Schmitt trigger voltage hysteresis
0.7
hys
Injected Current on Flash device pin PB0
Injected Current on other I/O pins
+4
3)
I
INJ(PIN)
±4
V
V
=5V
mA
DD
Total injected current (sum of all I/O and
control pins)
3)
ΣI
±25
INJ(PIN)
I
Input leakage current
SS ≤ VIN ≤ V
1
lkg
DD
µA
Static current consumption induced by each
floating input pin
4)
I
Floating input mode
V =V =5V
200
S
5)
R
Weak pull-up equivalent resistor
V
DD
50
1
120
5
250
kΩ
PU
IN
SS
C
I/O pin capacitance
pF
IO
1)
t
Output high to low level fall time
C =50pF
25
f(IO)out
L
Between 10% and
90%
ns
1)
t
Output low to high level rise time
25
r(IO)out
6)
t
External interrupt pulse time
t
CPU
w(IT)in
Notes:
1. Data based on characterization results, not tested in production.
2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
3. When the current limitation is not possible, the V maximum must be respected, otherwise refer to I
specifica-
INJ(PIN)
IN
tion. A positive injection is induced by V >V while a negative injection is induced by V <V . Refer to Section 12.2.2
IN
DD
IN
SS
on page 117 for more details.
4. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for
example and leaving the I/O unconnected on the board or an external pull-up or pull-down resistor (see Figure 69). Data
based on design simulation and/or technology characteristics, not tested in production.
5. The R pull-up equivalent resistor is based on a resistive transistor (corresponding I current characteristics de-
PU
PU
scribed in Figure 70).
6. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external
interrupt source.
Figure 69. Unused I/O Pins configured as input
Figure 70. Typical I vs. V with V =V
PU DD IN SS
90
80
70
60
50
40
30
20
10
0
V
DD
Ta=140°C
ST7XXX
Ta=95°C
Ta=25°C
Ta=-45°C
10kΩ
UNUSED I/O PORT
UNUSED I/O PORT
10kΩ
ST7XXX
2
2.5
3
3.5
4
4.5
5
5.5
6
Vdd(V)
Note: I/O can be left unconnected if it is configured as output
(0 or 1) by the software. This has the advantage of
greater EMC robustness and lower cost.
133/163
1
ST72324
I/O PORT PIN CHARACTERISTICS (Cont’d)
12.9.2 Output Driving Current
Subject to general operating conditions for V , f
, and T unless otherwise specified.
A
DD CPU
Symbol
Parameter
Conditions
I =+5mA
Min
Max
Unit
Output low level voltage for a standard I/O pin
when 8 pins are sunk at same time
(see Figure 71)
1.2
IO
I =+2mA
0.5
IO
1)
V
OL
I =+20mA,T ≤85°C
1.3
1.5
IO
A
Output low level voltage for a high sink I/O pin
when 4 pins are sunk at same time
(see Figure 72 and Figure 74)
T >85°C
A
V
I =+8mA
0.6
IO
I =-5mA, T ≤85°C
V
V
-1.4
IO
A
Output high level voltage for an I/O pin
when 4 pins are sourced at same time
(see Figure 73 and Figure 76)
DD
DD
2)
-1.6
T >85°C
V
A
OH
I =-2mA
V
-0.7
IO
DD
Figure 71. Typical V at V =5V (std. ports)
Figure 73. Typical V at V =5V
OH DD
OL
DD
5.5
1.2
5
1
4.5
4
0.8
0.6
0.4
0.2
0
3.5
3
Ta=140°C "
Vdd=5V 140°C min
Vdd=5v 95°C min
Vdd=5v 25°C min
Vdd=5v -45°C min
Ta=95°C
Ta=25°C
Ta=-45°C
2.5
2
5
10
15
IIO (mA)
-10
-8
-6
-4
-2
0
I
(mA)
IO
Figure 72. Typ. V at V =5V (high-sink ports)
OL
DD
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
Ta= 140°C
Ta= 95°C
Ta= 25°C
Ta=-45°C
10
20
30
IIO (mA)
Notes:
1. The I current sunk must always respect the absolute maximum rating specified in Section 12.2.2 and the sum of I
IO
IO
(I/O ports and control pins) must not exceed I
.
VSS
2. The I current sourced must always respect the absolute maximum rating specified in Section 12.2.2 and the sum of
IO
I
(I/O ports and control pins) must not exceed I
. True open drain I/O pins do not have V
.
IO
VDD
OH
134/163
1
ST72324
I/O PORT PIN CHARACTERISTICS (Cont’d)
Figure 74. Typical V vs. V (std. ports)
OL
DD
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.45
0.4
Ta= -45°C
Ta= 25°C
Ta=-45°C
Ta=25°C
Ta=95°C
Ta=140°C
Ta= 95°C
0.35
0.3
Ta= 140°C
0.25
0.2
0.15
0.1
0.05
0
2
2.5
3
3.5
4
4.5
5
5.5
6
2
2.5
3
3.5
4
4.5
5
5.5
6
Vdd(V)
Vdd(V)
Figure 75. Typical V vs. V (high-sink ports)
OL
DD
1.6
1.4
1.2
1
0.6
Ta= 140°C
Ta=95°C
Ta=25°C
Ta=-45°C
0.5
0.4
0.3
0.2
0.8
0.6
0.4
0.2
0
Ta= 140°C
Ta=95°C
Ta=25°C
Ta=-45°C
0.1
0
2
2.5
3
3.5
4
4.5
5
5.5
6
2
2.5
3
3.5
4
4.5
5
5.5
6
V dd(V )
Vdd(V )
Figure 76. Typical V vs. V
OH
DD
5.5
6
5
4
3
2
1
0
Ta=-45°C
Ta=25°C
Ta=95°C
Ta=140°C
5
4.5
4
3.5
3
Ta=-45°C
Ta=25°C
Ta=95°C
Ta=140°C
2.5
2
2
2.5
3
3.5
4
4.5
5
5.5
6
2
2.5
3
3.5
4
4.5
5
5.5
6
Vdd(V)
Vdd(V)
135/163
1
ST72324
12.10 CONTROL PIN CHARACTERISTICS
12.10.1 Asynchronous RESET Pin
Subject to general operating conditions for V , f
, and T unless otherwise specified.
A
DD CPU
Symbol
Parameter
Conditions
Min
Typ
Max
0.16xVDD
0.5
Unit
2)
V
Schmitt trigger voltage hysteresis
2.5
V
hys
1)
V
Input low level voltage
IL
V
1)
V
Input high level voltage
0.85xVDD
IH
3)
V
Output low level voltage
V
V
=5V I =+2mA
0.2
2
V
mA
kΩ
µs
µs
ns
OL
IO
DD
DD
IO
I
Driving current on RESET pin
Weak pull-up equivalent resistor
Generated reset pulse duration
R
=5V
20
20
30
30
120
ON
w(RSTL)out
6)
t
Internal reset sources
42
4)
t
t
External reset pulse hold time
2.5
h(RSTL)in
5)
Filtered glitch duration
200
g(RSTL)in
Notes:
1. Data based on characterization results, not tested in production.
2. Hysteresis voltage between Schmitt trigger switching levels.
3. The I current sunk must always respect the absolute maximum rating specified in Section 12.2.2 and the sum of I
IO
IO
(I/O ports and control pins) must not exceed I
.
VSS
4. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on
the RESET pin with a duration below t can be ignored.
h(RSTL)in
5. The reset network (the resistor and two capacitors) protects the device against parasitic resets, especially in noisy en-
vironments.
6. Data guaranteed by design, not tested in production.
136/163
1
ST72324
CONTROL PIN CHARACTERISTICS (Cont’d)
1)2)3)4)5)6)7)
Figure 77. RESET pin protection when LVD is enabled.
V
ST72XXX
DD
Optional
(note 6)
Recommended
R
ON
Filter
INTERNAL
RESET
EXTERNAL
RESET
0.01µF
1MΩ
WATCHDOG
PULSE
GENERATOR
LVD RESET
1)2)3)4)
Figure 78. RESET pin protection when LVD is disabled.
Recommended
V
ST72XXX
DD
V
V
DD
DD
R
ON
Filter
0.01µF
0.01µF
4.7kΩ
INTERNAL
RESET
USER
EXTERNAL
RESET
CIRCUIT
PULSE
GENERATOR
WATCHDOG
Required
1. The reset network protects the device against parasitic resets.
2. The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device
can be damaged when the ST7 generates an internal reset (LVD or watchdog).
3. Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin can go below
the V max. level specified in Section 12.10.1. Otherwise the reset will not be taken into account internally.
IL
4. Because the reset circuit is designed to allow the internal RESET to be output in the RESET pin, the user must ensure
that the current sunk on the RESET pin (by an external pull-up for example) is less than the absolute maximum value
specified for I
in Section 12.2.2 on page 117.
INJ(RESET)
5. When the LVD is enabled, it is mandatory not to connect a pull-up resistor. A 10nF pull-down capacitor is recommended
to filter noise on the reset line.
6. In case a capacitive power supply is used, it is recommended to connect a1MΩ pull-down resistor to the RESET pin
to discharge any residual voltage induced by this capacitive power supply (this will add 5µA to the power consumption of
the MCU).
7. Tips when using the LVD:
– 1. Check that all recommendations related to ICCCLK and reset circuit have been applied (see notes above)
– 2. Check that the power supply is properly decoupled (100nF + 10µF close to the MCU). Refer to AN1709. If this
cannot be done, it is recommended to put a 100nF + 1MΩ pull-down on the RESET pin.
– 3. The capacitors connected on the RESET pin and also the power supply are key to avoiding any start-up margin-
ality. In most cases, steps 1 and 2 above are sufficient for a robust solution. Otherwise: replace 10nF pull-down on
the RESET pin with a 5µF to 20µF capacitor.”
137/163
1
ST72324
CONTROL PIN CHARACTERISTICS (Cont’d)
12.10.2 ICCSEL/V Pin
PP
Subject to general operating conditions for V , f
, and T unless otherwise specified.
A
DD CPU
Symbol
Parameter
Conditions
Min
Max
Unit
V
1)
V
Input low level voltage
V
0.2
IL
IH
L
SS
1)
V
I
Input high level voltage
Input leakage current
V
-0.1 12.6
1
DD
V =V
µA
IN
SS
2)
Figure 79. Two typical Applications with ICCSEL/V Pin
PP
ICCSEL/V
V
PP
PP
PROGRAMMING
TOOL
10kΩ
ST72XXX
ST72XXX
Notes:
1. Data based on design simulation and/or technology characteristics, not tested in production.
2. When ICC mode is not required by the application ICCSEL/V pin must be tied to V
.
PP
SS
138/163
1
ST72324
12.11 TIMER PERIPHERAL CHARACTERISTICS
Subject to general operating conditions for V , f
, and T unless otherwise specified.
DD OSC
A
Refer to I/O port characteristics for more details on the input/output alternate function characteristics (out-
put compare, input capture, external clock, PWM output...).
Data based on design simulation and/or characterisation results, not tested in production.
12.11.1 16-Bit Timer
Symbol
Parameter
Conditions
Min
1
Typ
Max
Unit
t
Input capture pulse time
t
t
w(ICAP)in
CPU
2
CPU
t
PWM resolution time
res(PWM)
f
=8MHz
250
0
ns
CPU
f
Timer external clock frequency
PWM repetition rate
f
f
/4
MHz
MHz
bit
EXT
CPU
f
0
/4
CPU
PWM
Res
PWM resolution
16
PWM
139/163
1
ST72324
12.12 COMMUNICATION INTERFACE CHARACTERISTICS
12.12.1 SPI - Serial Peripheral Interface
Subject to general operating conditions for V , f
, and T unless otherwise specified. Data based on
A
DD CPU
design simulation and/or characterisation results, not tested in production.
When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave
mode) has its alternate function capability released. In this case, the pin status depends on the I/O port
configuration. Refer to I/O port characteristics for more details on the input/output alternate function char-
acteristics (SS, SCK, MOSI, MISO).
Symbol
Parameter
Conditions
Min
/128
0.0625
Max
Unit
Master
Slave
f
f
f
/4
CPU
2
CPU
f
=8MHz
=8MHz
f
CPU
SCK
MHz
SPI clock frequency
1/t
/2
c(SCK)
CPU
0
f
4
CPU
t
t
r(SCK)
SPI clock rise and fall time
see I/O port pin description
f(SCK)
t
SS setup time
SS hold time
Slave
Slave
120
120
su(SS)
t
h(SS)
t
t
Master
Slave
100
90
w(SCKH)
SCK high and low time
Data input setup time
Data input hold time
w(SCKL)
t
Master
Slave
100
100
su(MI)
t
su(SI)
ns
t
Master
Slave
100
100
h(MI)
t
h(SI)
t
Data output access time
Data output disable time
Data output valid time
Data output hold time
Data output valid time
Data output hold time
Slave
Slave
0
120
240
90
a(SO)
t
dis(SO)
t
v(SO)
h(SO)
v(MO)
h(MO)
Slave (after enable edge)
t
0
t
0.25
0.25
Master (before capture edge)
t
CPU
t
Figure 80. SPI Slave Timing Diagram with CPHA=0 1)
SS
INPUT
t
t
su(SS)
c(SCK)
t
h(SS)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
t
t
w(SCKH)
w(SCKL)
t
t
t
t
dis(SO)
a(SO)
v(SO)
h(SO)
t
t
r(SCK)
f(SCK)
see
note 2
MISO
OUTPUT
INPUT
MSB OUT
see note 2
BIT6 OUT
LSB OUT
t
t
h(SI)
su(SI)
MSB IN
LSB IN
BIT1 IN
MOSI
Notes:
1. Measurement points are done at CMOS levels: 0.3xV and 0.7xV
.
DD
DD
140/163
1
ST72324
COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d)
Figure 81. SPI Slave Timing Diagram with CPHA=11)
SS
INPUT
t
t
su(SS)
c(SCK)
t
h(SS)
CPHA=1
CPOL=0
CPHA=1
CPOL=1
t
t
w(SCKH)
w(SCKL)
t
t
dis(SO)
a(SO)
t
t
h(SO)
v(SO)
t
t
r(SCK)
f(SCK)
see
note 2
see
note 2
MISO
OUTPUT
MSB OUT
BIT6 OUT
HZ
LSB OUT
t
t
h(SI)
su(SI)
MSB IN
LSB IN
BIT1 IN
MOSI
INPUT
Figure 82. SPI Master Timing Diagram 1)
SS
INPUT
t
c(SCK)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
CPHA=1
CPOL=0
CPHA=1
CPOL=1
t
t
w(SCKH)
w(SCKL)
t
t
r(SCK)
f(SCK)
t
t
h(MI)
su(MI)
MISO
MOSI
INPUT
MSB IN
h(MO)
BIT6 IN
LSB IN
t
t
v(MO)
MSB OUT
LSB OUT
see note 2
BIT6 OUT
see note 2
OUTPUT
Notes:
1. Measurement points are done at CMOS levels: 0.3xV and 0.7xV
.
DD
DD
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has
its alternate function capability released. In this case, the pin status depends of the I/O port configuration.
141/163
1
ST72324
12.13 10-BIT ADC CHARACTERISTICS
Subject to general operating conditions for V , f
, and T unless otherwise specified.
A
DD CPU
Symbol
Parameter
ADC clock frequency
Conditions
Min
0.4
3.8
Typ
Max
Unit
f
2
MHz
ADC
V
Analog reference voltage
Conversion voltage range
0.7*V ≤V
≤V
V
DD
AREF
DD
AREF
DD
V
1)
V
V
V
AREF
AIN
SSA
-40°C≤T ≤+85°C
250
nA
µA
kΩ
pF
Positive input leakage current for analog
input
A
I
2)
lkg
+85°C≤T ≤+125°C
1
A
R
C
External input impedance
see
Figure 83
and
AIN
AIN
External capacitor on analog input
Figure
84
f
Variation freq. of analog input signal
Hz
AIN
2)3)4)
C
Internal sample and hold capacitor
Conversion time (Sample+Hold)
12
pF
ADC
t
t
7.5
µs
ADC
f
=8MHz, SPEED=0 f
=2MHz
CPU
ADC
- No of sample capacitor loading cycles
- No. of Hold conversion cycles
4
11
1/f
ADC
ADC
Notes:
1. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10kΩ). Data
based on characterization results, not tested in production.
2.For Flash devices: injecting negative current on any of the analog input pins significantly reduces the accuracy of any
conversion being performed on any analog input. Analog pins of ST72F324 devices can be protected against negative
injection by adding a Schottky diode (pin to ground). Injecting negative current on digital input pins degrades ADC accu-
racy especially if performed on a pin close to the analog input pins. Any positive injection current within the limits specified
for I
and ΣI
in Section 12.9 does not affect the ADC accuracy.
INJ(PIN)
INJ(PIN)
142/163
1
ST72324
ADC CHARACTERISTICS (Cont’d)
1)
2)
Figure 83. R
max. vs f
with C =0pF
Figure 84. Recommended C
& R
AIN AIN values.
AIN
ADC
AIN
45
40
35
30
25
20
15
10
5
1000
Cain 10 nF
Cain 22 nF
Cain 47 nF
2 MHz
1 MHz
100
10
1
0
0.1
0
10
30
70
0.01
0.1
1
10
CPARASITIC (pF)
fAIN(KHz)
Figure 85. Typical A/D Converter Application
V
DD
ST72XXX
V
T
0.6V
R
2kΩ(max)
AIN
AINx
10-Bit A/D
V
AIN
Conversion
C
V
0.6V
AIN
T
I
C
ADC
12pF
L
1µA
Notes:
1. C
represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad ca-
PARASITIC
pacitance (3pF). A high C
value will downgrade conversion accuracy. To remedy this, f
should be reduced.
PARASITIC
ADC
2. This graph shows that depending on the input signal variation (f ), C
can be increased for stabilization time and
AIN
AIN
decreased to allow the use of a larger serial resistor (R
.
AIN)
143/163
1
ST72324
ADC CHARACTERISTICS (Cont’d)
12.13.1 Analog Power Supply and Reference
Pins
digital ground plane via a single point on the
PCB.
Depending on the MCU pin count, the package
– Filter power to the analog power planes. It is rec-
ommended to connect capacitors, with good high
frequency characteristics, between the power
and ground lines, placing 0.1µF and optionally, if
needed 10pF capacitors as close as possible to
the ST7 power supply pins and a 1 to 10µF ca-
pacitor close to the power source (see Figure
86).
may feature separate V
and V
analog
AREF
SSA
power supply pins. These pins supply power to the
A/D converter cell and function as the high and low
reference voltages for the conversion. In some
packages, V
and V
pins are not available
AREF
SSA
(refer to Section 2 on page 8). In this case the an-
alog supply and reference pads are internally
bonded to the V and V pins.
DD
SS
– The analog and digital power supplies should be
connected in a star network. Do not use a resis-
Separation of the digital and analog power pins al-
low board designers to improve A/D performance.
Conversion accuracy can be impacted by voltage
drops and noise in the event of heavily loaded or
badly decoupled power supply lines (see Section
12.13.2 General PCB Design Guidelines).
tor, as V
is used as a reference voltage by
AREF
the A/D converter and any resistance would
cause a voltage drop and a loss of accuracy.
– Properly place components and route the signal
traces on the PCB to shield the analog inputs.
Analog signals paths should run over the analog
ground plane and be as short as possible. Isolate
analog signals from digital signals that may
switch while the analog inputs are being sampled
by the A/D converter. Do not toggle digital out-
puts on the same I/O port as the A/D input being
converted.
12.13.2 General PCB Design Guidelines
To obtain best results, some general design and
layout rules should be followed when designing
the application PCB to shield the noise-sensitive,
analog physical interface from noise-generating
CMOS logic signals.
– Use separate digital and analog planes. The an-
alog ground plane should be connected to the
Figure 86. Power Supply Filtering
ST72XXX
1 to 10µF
0.1µF
V
V
SS
DD
ST7
DIGITAL NOISE
FILTERING
V
DD
POWER
SUPPLY
SOURCE
0.1µF
V
V
AREF
SSA
EXTERNAL
NOISE
FILTERING
144/163
1
ST72324
10-BIT ADC CHARACTERISTICS (Cont’d)
12.13.3 ADC Accuracy
Conditions: V =5V 1)
DD
Flash Devices
Symbol
|E |
Parameter
Conditions
Unit
2)
Max
6
Typ
4
1)
Total unadjusted error
T
1)
3
5
|E |
Offset error
O
1)
0.5
4.5
4.5
4.5
|E |
Gain Error
G
LSB
Differential linearity error
1.5
1.5
|E |
CPU in run mode @ f
2 MHz.
2 MHz.
1)
D
ADC
ADC
1)
|E |
Integral linearity error
CPU in run mode @ f
L
Notes:
1. ADC Accuracy vs. Negative Injection Current: Injecting negative current may reduce the accuracy of the conversion
being performed on another analog input.
Any positive injection current within the limits specified for I
accuracy.
and ΣI
in Section 12.9 does not affect the ADC
INJ(PIN)
INJ(PIN)
2. Data based on characterization results, monitored in production to guarantee 99.73% within max value from -40°C
to 125°C ( 3σ distribution limits).
Figure 87. ADC Accuracy Characteristics
Digital Result ADCDR
E
G
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line
1023
1022
1021
V
– V
AREF
SSA
1LSB
= --------------------------------------------
IDEAL
1024
(2)
E =Total Unadjusted Error: maximum deviation
T
E
between the actual and the ideal transfer curves.
T
(3)
7
6
5
4
3
2
1
E =Offset Error: deviation between the first actual
O
transition and the first ideal one.
(1)
E =Gain Error: deviation between the last ideal
G
transition and the last actual one.
E
E
O
L
E =Differential Linearity Error: maximum deviation
D
between actual steps and the ideal one.
E =Integral Linearity Error: maximum deviation
L
E
between any actual transition and the end point
correlation line.
D
1 LSB
IDEAL
V
(LSB
)
in
IDEAL
0
1
2
3
4
5
6
7
1021 1022 1023 1024
V
V
SSA
AREF
145/163
1
ST72324
13 PACKAGE CHARACTERISTICS
13.1 PACKAGE MECHANICAL DATA
Figure 88. 44-Pin Thin Quad Flat Package
mm
inches
Dim.
A
D
D1
Min Typ Max Min Typ Max
A2
A
1.60
0.063
0.006
A1 0.05
0.15 0.002
A1
b
A2 1.35 1.40 1.45 0.053 0.055 0.057
b
C
0.30 0.37 0.45 0.012 0.015 0.018
0.09
0.20 0.004 0.000 0.008
D
12.00
10.00
12.00
10.00
0.80
0.472
0.394
0.472
0.394
0.031
e
D1
E
E1
E
E1
e
θ
0°
3.5°
7°
0°
3.5°
7°
L
0.45 0.60 0.75 0.018 0.024 0.030
1.00 0.039
Number of Pins
44
c
L1
L1
L
h
N
Figure 89. 32-Pin Thin Quad Flat Package
mm
inches
Dim.
Min Typ Max Min Typ Max
D
A
1.60
0.063
0.006
A
D1
A2
A1 0.05
0.15 0.002
A2 1.35 1.40 1.45 0.053 0.055 0.057
A1
b
C
0.30 0.37 0.45 0.012 0.015 0.018
0.09 0.20 0.004 0.008
e
b
D
9.00
7.00
9.00
7.00
0.80
3.5°
0.354
0.276
0.354
0.276
0.031
3.5°
D1
E
E
E1
E1
e
θ
0°
7°
0°
7°
c
L1
L
0.45 0.60 0.75 0.018 0.024 0.030
1.00 0.039
Number of Pins
32
L
L1
h
N
146/163
1
ST72324
PACKAGE MECHANICAL DATA (Cont’d)
Figure 90. 42-Pin Plastic Dual In-Line Package, Shrink 600-mil Width
-
mm
inches
Dim.
Min Typ Max Min Typ Max
5.08 0.200
E
A
A2
A
L
A1 0.51
A2 3.05 3.81 4.57 0.120 0.150 0.180
0.38 0.46 0.56 0.015 0.018 0.022
b2 0.89 1.02 1.14 0.035 0.040 0.045
0.020
A1
c
E1
b
b2
b
e
eA
eB
E
D
c
D
E
0.23 0.25 0.38 0.009 0.010 0.015
36.58 36.83 37.08 1.440 1.450 1.460
0.015
15.24
16.00 0.600
0.630
GAGE PLANE
E1 12.70 13.72 14.48 0.500 0.540 0.570
e
1.78
0.070
0.600
eA
eB
eC
L
15.24
eC
18.54
0.730
0.060
eB
1.52 0.000
2.54 3.30 3.56 0.100 0.130 0.140
Number of Pins
N
42
Figure 91. 32-Pin Plastic Dual In-Line Package, Shrink 400-mil Width
mm
inches
Dim.
Min Typ Max Min Typ Max
E
eC
A
3.56 3.76 5.08 0.140 0.148 0.200
A1 0.51
A2 3.05 3.56 4.57 0.120 0.140 0.180
0.36 0.46 0.58 0.014 0.018 0.023
b1 0.76 1.02 1.40 0.030 0.040 0.055
0.020
A2
A
L
b
A1
E1
C
eA
eB
C
D
E
0.20 0.25 0.36 0.008 0.010 0.014
27.43 28.45 1.080 1.100 1.120
9.91 10.41 11.05 0.390 0.410 0.435
b
b2
e
D
E1 7.62 8.89 9.40 0.300 0.350 0.370
e
1.78
0.070
0.400
eA
eB
eC
L
10.16
12.70
1.40
0.500
0.055
2.54 3.05 3.81 0.100 0.120 0.150
Number of Pins
N
32
147/163
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ST72324
13.2 THERMAL CHARACTERISTICS
Symbol
Ratings
Value
Unit
Package thermal resistance (junction to ambient)
TQFP44 10x10
52
70
55
50
R
TQFP32 7x7
SDIP42 600mil
SDIP32 200mil
°C/W
thJA
1)
P
Power dissipation
Maximum junction temperature
500
150
mW
°C
D
2)
T
Jmax
Notes:
1. The power dissipation is obtained from the formula P =P +P
where P
is the chip internal power (I xV
)
D
INT
PORT
INT
DD DD
and P
is the port power dissipation determined by the user.
PORT
2. The average chip-junction temperature can be obtained from the formula T = T + P x RthJA.
J
A
D
148/163
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ST72324
13.3 SOLDERING INFORMATION
In accordance with the RoHS European directive,
all STMicroelectronics packages will be converted
Backward and forward compatibility:
The main difference between Pb and Pb-free sol-
dering process is the temperature range.
in 2005 to lead-free technology, named ECO-
TM
PACK
(for a detailed roadmap, please refer to
TM
– ECOPACK TQFP, SDIP and SO packages
PCN CRP/04/744 “Lead-free Conversion Program
- Compliance with RoHS”, issued November 18th,
2004).
are fully compatible with Lead (Pb) containing
soldering process (see application note AN2034)
TM
– TQFP, SDIP and SO Pb-packages are compati-
ble with Lead-free soldering process, neverthe-
less it's the customer's duty to verify that the Pb-
packages maximum temperature (mentioned on
the Inner box label) is compatible with their Lead-
free soldering temperature.
■ ECOPACK packages are qualified according
to the JEDEC STD-020B compliant soldering
profile.
■ Detailed information on the STMicroelectronics
TM
ECOPACK transition program is available on
www.st.com/stonline/leadfree/, with specific
technical Application notes covering the main
technical aspects related to lead-free
conversion (AN2033, AN2034, AN2035,
AN2036).
Table 26. Soldering Compatibility (wave and reflow soldering process)
Package
SDIP & PDIP
TQFP and SO
Plating material devices
Sn (pure Tin)
NiPdAu (Nickel-palladium-Gold)
Pb solder paste
Pb-free solder paste
Yes
Yes
Yes *
Yes *
* Assemblers must verify that the Pb-package maximum temperature (mentioned on the Inner box label)
is compatible with their Lead-free soldering process.
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ST72324
14 ST72324 DEVICE CONFIGURATION AND ORDERING INFORMATION
14.1 FLASH OPTION BYTES
STATIC OPTION BYTE 0
STATIC OPTION BYTE 1
7
0
7
0
WDG
VD
OSCTYPE
OSCRANGE
1
0
0
0
1
1
0
0
1
1
0
1
2
1
Default
1
1
1
1
1
1
1
1
1
The option bytes allows the hardware configura-
tion of the microcontroller to be selected. They
have no address in the memory map and can be
accessed only in programming mode (for example
using a standard ST7 programming tool). The de-
fault content of the FLASH is fixed to FFh. To pro-
gram directly the FLASH devices using ICP,
FLASH devices are shipped to customers with the
internal RC clock source.
Selected Low Voltage Detector
VD1
VD0
LVD and AVD Off
1
1
0
0
1
0
1
0
Lowest Voltage Threshold (V ~3V)
DD
Medium Voltage Threshold (V ~3.5V)
DD
Highest Voltage Threshold (V ~4V)
DD
Caution: If the medium or low thresholds are se-
lected, the detection may occur outside the speci-
fied operating voltage range. Below 3.8V, device
operation is not guaranteed. For details on the
AVD and LVD threshold levels refer to Section
12.4.1 on page 119
OPTION BYTE 0
OPT7= WDG HALT Watchdog reset on HALT
This option bit determines if a RESET is generated
when entering HALT mode while the Watchdog is
active.
0: No Reset generation when entering Halt mode
1: Reset generation when entering Halt mode
OPT2:1 = Reserved, must be kept at default value.
OPT0= FMP_R Flash memory read-out protection
Read-out protection, when selected, provides a
protection against Program Memory content ex-
traction and against write access to Flash memo-
ry.
OPT6= WDG SW Hardware or software watchdog
This option bit selects the watchdog type.
0: Hardware (watchdog always enabled)
1: Software (watchdog to be enabled by software)
Erasing the option bytes when the FMP_R option
is selected causes the whole user memory to be
erased first, and the device can be reprogrammed.
Refer to Section 7.3.1 on page 37 and the ST7
Flash Programming Reference Manual for more
details.
OPT5 = Reserved, must be kept at default value.
OPT4:3= VD[1:0] Voltage detection
These option bits enable the voltage detection
block (LVD, and AVD) with a selected threshold for
the LVD and AVD.
0: Read-out protection enabled
1: Read-out protection disabled
150/163
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ST72324
ST72324 DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d)
OPTION BYTE 1
these option bits select the resonator oscillator
current source corresponding to the frequency
range of the used resonator. Otherwise, these bits
are used to select the normal operating frequency
OPT7= PKG1 Pin package selection bit
This option bit selects the package.
Version
Selected Package
TQFP44 / SDIP42
TQFP32 / SDIP32
PKG1
range.
J
1
0
OSCRANGE
Typ. Freq. Range
K
2
0
0
0
0
1
0
0
1
1
0
0
1
0
1
Note: On the chip, each I/O port has 8 pads. Pads
that are not bonded to external pins are in input
pull-up configuration after reset. The configuration
of these pads must be kept at reset state to avoid
added current consumption.
LP
1~2MHz
2~4MHz
4~8MHz
8~16MHz
MP
MS
HS
OPT6 = RSTC RESET clock cycle selection
This option bit selects the number of CPU cycles
applied during the RESET phase and when exiting
HALT mode. For resonator oscillators, it is advised
to select 4096 due to the long crystal stabilization
time.
OPT0 = PLL OFF PLL activation
This option bit activates the PLL which allows mul-
tiplication by two of the main input clock frequency.
The PLL must not be used with the internal RC os-
cillator. The PLL is guaranteed only with an input
frequency between 2 and 4MHz.
0: Reset phase with 4096 CPU cycles
1: Reset phase with 256 CPU cycles
0: PLL x2 enabled
1: PLL x2 disabled
CAUTION: the PLL can be enabled only if the
“OSC RANGE” (OPT3:1) bits are configured to
“MP - 2~4MHz”. Otherwise, the device functionali-
ty is not guaranteed.
OPT5:4 = OSCTYPE[1:0] Oscillator Type
These option bits select the ST7 main clock
source type.
OSCTYPE
Clock Source
1
0
0
1
1
0
0
1
0
1
Resonator Oscillator
Reserved
Internal RC Oscillator
External Source
OPT3:1 = OSCRANGE[2:0] Oscillator range
When the resonator oscillator type is selected,
151/163
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ST72324
DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d)
14.2 VERSION-SPECIFIC SALES CONDITIONS
To satisfy the different customer requirements and
to ensure that ST Standard Microcontrollers will
consistently meet or exceed the expectations of
each Market Segment, the Codification System for
Standard Microcontrollers clearly distinguishes
products intended for use in automotive environ-
ments, from products intended for use in non-auto-
motive environments.
It is the responsibility of the Customer to select the
appropriate product for his application.
14.3 FLASH DEVICE ORDERING INFORMATiON
With the objective of continuous improvement, ST
is developing new ST72F324B devices and is
transferring the production to higher capacity fabs.
Refer to the following tables for guidance on order-
ing.
Standard and Industrial Versions
■ For new designs the ST72F324B devices from
to the separate ST72324B datasheet.
■ For for running production orders select the
devices from Table 27
Automotive applications
■ For existing and new designs in Automotive
applications select the devices from Table 28.
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ST72324
DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d)
Table 27. Standard and Industrial ST72F324 Flash Order Codes
Part Number
ST72F324K2B5
ST72F324K4B5
ST72F324K6B5
ST72F324J6B5
ST72F324K6T5
ST72F324K2T6
ST72F324K4T6
ST72F324K6T6
ST72F324K2T3
ST72F324K4T3
ST72F324K6T3
ST72F324J6T5
ST72F324J2T6
ST72F324J4T6
ST72F324J6T6
ST72F324J2T3
ST72F324J4T3
ST72F324J6T3
Package
SDIP32
SDIP42
Flash Memory (KBytes)
Temp. Range
8
16
32
32
32
8
-10°C +85°C
-10°C +85°C
-40°C +85°C
16
32
8
TQFP32
16
32
32
8
-40°C +125°C
-10°C +85°C
-40°C +85°C
16
32
8
TQFP44
16
32
-40°C +125°C
Table 28. Automotive Flash Order Codes
Part Number
ST72F324K2TA
ST72F324K4TA
ST72F324K6TA
ST72F324K6TC
ST72F324J2TA
ST72F324J4TA
ST72F324J6TA
ST72F324J6TC
Package
Flash Memory (KBytes)
Temp. Range
-40°C +85°C
-40°C +125°C
-40°C +85°C
-40°C +125°C
8
16
32
32
8
TQFP32
16
32
32
TQFP44
153/163
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ST72324
14.4 SILICON IDENTIFICATION
The various ST72F324, ST72F324B and
ST72324B devices are identifiable both by the last
letter of the Trace code marked on the device
package and by the last 3 digits of the Internal
Sales Type printed on the box label.
Table 29. Silicon Identification (Automotive versions)
Trace Code
marked on
device
Internal Sales Types
on box label
Device
Status
Fab
Memory
For existing and
new designs
8K to 32K
Flash
ST72F324xxxx
ST72324Bxxxx
ST72324Bxxxx
Rousset
Phoenix
Phoenix
“xxxxxxxxxW”
“xxxxxxxxxA”
72F324xxxx$x5
72324Bx6xx$x1
72324Bxxxx$x3
For existing and
new designs
32K ROM
For existing and
new designs
8K/16K ROM “xxxxxxxxxB”
Table 30. Silicon Identification (Standard and Industrial Versions)
Trace Code
marked on device
Internal Sales Types
on box label
Device
Status
Fab
Memory
Current production Phoenix
“xxxxxxxxx1”
72F324xxxx$x7
8K to 32K
Flash
ST72F324xxxx
End of production
Rousset
“xxxxxxxxxW”
72F324xxxx$x5
Dec. 2005
Currentproduction.
ST72F324Bxxxx
ST72324Bxxxx
Rousset
8K/16K Flash “xxxxxxxxxB”
72F324Bxxxx$x4
Recommended for
new designs
32K ROM
“xxxxxxxxxA”
72324Bxxxx$x1
72324Bxxxx$x3
Current production Phoenix
8K/16K ROM “xxxxxxxxxB”
154/163
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ST72324
14.5 DEVELOPMENT TOOLS
Two configurations are available from ST:
■ STXF521-IND/USB: Low-cost In-Circuit
STMicroelectronics offers a range of hardware
and software development tools for the ST7 micro-
controller family. Full details of tools available for
the ST7 from third party manufacturers can be ob-
tain from the STMicroelectronics Internet site:
➟ http//:mcu.st.com.
Debugging kit from Softec Microsystems.
Includes STX-InDART/USB board (USB port)
and a specific demo board for ST72521
(TQFP64)
■ STxF-INDART
Flash Programming tools
Tools from these manufacturers include C compli-
ers, emulators and gang programmers.
■ ST7-STICK ST7 In-circuit Communication Kit, a
complete software/hardware package for
programming ST7 Flash devices. It connects to
a host PC parallel port and to the target board or
socket board via ST7 ICC connector.
Emulators
Two types of emulators are available from ST for
the ST72324 family:
■ ST7 DVP3 entry-level emulator offers a flexible
and modular debugging and programming
solution. SDIP42 & SDIP32 probes/adapters
are included, other packages need a specific
connection kit (refer to Table 31)
■ ST7 EMU3 high-end emulator is delivered with
everything (probes, TEB, adapters etc.) needed
to start emulating the ST72324 family. To
configure it to emulate other ST7 subfamily
devices, the active probe for the ST7EMU3 can
be changed and the ST7EMU3 probe is
designed for easy interchange of TEBs (Target
Emulation Board). See Table 31.
■ ICC Socket Boards provide an easy to use and
flexible means of programming ST7 Flash
devices. They can be connected to any tool that
supports the ST7 ICC interface, such as ST7
EMU3, ST7-DVP3, inDART, ST7-STICK, or
many third-party development tools.
Evaluation board
■ ST7232x-EVAL with ICC connector for
programming capability. Provides direct
connection to ST7-DVP3 emulator. Supplied
with daughter boards (core module) for
ST72F321, ST72F324
&
ST72F521 (the
ST72F321 & ST72F324 chips are not included)
In-circuit Debugging Kit
Table 31. STMicroelectronics Development Tools
Emulation
Programming
Supported
Products
ST7 DVP3 Series
ST7 EMU3 series
ICC Socket Board
Active Probe &
Emulator
Connection kit
Emulator
T.E.B.
ST72324BJ,
ST72F324J,
ST72F324BJ
ST7MDT20-T44/
DVP
ST7MDT20-DVP3
ST7MDT20J-
EMU3
1
ST7MDT20J-TEB
ST7SB20J/xx
ST72324BK,
ST72F324K,
ST72F324BK
ST7MDT20-T32/
DVP
ST7MDT20-DVP3
Note 1: Add suffix /EU, /UK, /US for the power supply of your region.
155/163
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ST72324
14.5.1
Socket
and
Emulator
Adapter
Information
For information on the type of socket that is sup-
plied with the emulator, refer to the suggested list
of sockets in Table 32.
Note: Before designing the board layout, it is rec-
ommended to check the overall dimensions of the
socket as they may be greater than the dimen-
sions of the device.
For footprint and other mechanical information
about these sockets and adapters, refer to the
manufacturer’s datasheet (www.yamaichi.de for
TQFP44 10 x 10 and www.ironwoodelectron-
ics.com for TQFP32 7 x 7).
Table 32. Suggested List of Socket Types
Socket (supplied with
ST7MDT20J-EMU3)
Emulator Adapter (supplied with
ST7MDT20J-EMU3)
Device
TQFP32 7 X 7
IRONWOOD SF-QFE32SA-L-01
YAMAICHI IC149-044-*52-*5
IRONWOOD SK-UGA06/32A-01
YAMAICHI ICP-044-5
TQFP44 10 X10
156/163
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ST72324
14.6 ST7 APPLICATION NOTES
Table 33. ST7 Application Notes
IDENTIFICATION DESCRIPTION
APPLICATION EXAMPLES
AN1658
AN1720
AN1755
SERIAL NUMBERING IMPLEMENTATION
MANAGING THE READ-OUT PROTECTION IN FLASH MICROCONTROLLERS
A HIGH RESOLUTION/PRECISION THERMOMETER USING ST7 AND NE555
EXAMPLE DRIVERS
AN 969
AN 970
AN 972
AN 973
AN 974
AN 976
AN 979
AN 980
AN1041
AN1044
AN1046
AN1047
AN1048
AN1078
AN1445
AN1504
SCI COMMUNICATION BETWEEN ST7 AND PC
SPI COMMUNICATION BETWEEN ST7 AND EEPROM
ST7 SOFTWARE SPI MASTER COMMUNICATION
SCI SOFTWARE COMMUNICATION WITH A PC USING ST72251 16-BIT TIMER
REAL TIME CLOCK WITH ST7 TIMER OUTPUT COMPARE
DRIVING A BUZZER THROUGH ST7 TIMER PWM FUNCTION
DRIVING AN ANALOG KEYBOARD WITH THE ST7 ADC
ST7 KEYPAD DECODING TECHNIQUES, IMPLEMENTING WAKE-UP ON KEYSTROKE
USING ST7 PWM SIGNAL TO GENERATE ANALOG OUTPUT (SINUSOÏD)
MULTIPLE INTERRUPT SOURCES MANAGEMENT FOR ST7 MCUS
UART EMULATION SOFTWARE
MANAGING RECEPTION ERRORS WITH THE ST7 SCI PERIPHERALS
ST7 SOFTWARE LCD DRIVER
PWM DUTY CYCLE SWITCH IMPLEMENTING TRUE 0% & 100% DUTY CYCLE
EMULATED 16 BIT SLAVE SPI
STARTING A PWM SIGNAL DIRECTLY AT HIGH LEVEL USING THE ST7 16-BIT TIMER
GENERAL PURPOSE
AN1476
AN1709
AN1752
LOW COST POWER SUPPLY FOR HOME APPLIANCES
EMC DESIGN FOR ST MICROCONTROLLERS
ST72324 QUICK REFERENCE NOTE
PRODUCT EVALUATION
AN 910
AN 990
AN1150
AN1151
AN1278
PERFORMANCE BENCHMARKING
ST7 BENEFITS VERSUS INDUSTRY STANDARD
BENCHMARK ST72 VS PC16
PERFORMANCE COMPARISON BETWEEN ST72254 & PC16F876
LIN (LOCAL INTERCONNECT NETWORK) SOLUTIONS
PRODUCT MIGRATION
AN1131
MIGRATING APPLICATIONS FROM ST72511/311/214/124 TO ST72521/321/324
GUIDELINES FOR MIGRATING ST72F324 & ST72F321 APPLICATIONS TO ST72F324B,
ST72F321B OR ST72F325
AN2197
PRODUCT OPTIMIZATION
AN 982
AN1014
AN1015
AN1070
AN1181
AN1502
USING ST7 WITH CERAMIC RESONATOR
HOW TO MINIMIZE THE ST7 POWER CONSUMPTION
SOFTWARE TECHNIQUES FOR IMPROVING MICROCONTROLLER EMC PERFORMANCE
ST7 CHECKSUM SELF-CHECKING CAPABILITY
ELECTROSTATIC DISCHARGE SENSITIVE MEASUREMENT
EMULATED DATA EEPROM WITH ST7 HDFLASH MEMORY
ACCURATE TIMEBASE FOR LOW-COST ST7 APPLICATIONS WITH INTERNAL RC OSCILLA-
TOR
AN1530
AN1636
UNDERSTANDING AND MINIMIZING ADC CONVERSION ERRORS
PROGRAMMING AND TOOLS
157/163
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ST72324
Table 33. ST7 Application Notes
IDENTIFICATION DESCRIPTION
AN 978
AN 983
AN 985
AN 986
AN 987
AN 988
AN 989
AN1039
AN1064
AN1106
AN1446
AN1478
AN1575
AN1576
AN1635
AN1754
AN1796
ST7 VISUAL DEVELOP SOFTWARE KEY DEBUGGING FEATURES
KEY FEATURES OF THE COSMIC ST7 C-COMPILER PACKAGE
EXECUTING CODE IN ST7 RAM
USING THE INDIRECT ADDRESSING MODE WITH ST7
ST7 SERIAL TEST CONTROLLER PROGRAMMING
STARTING WITH ST7 ASSEMBLY TOOL CHAIN
GETTING STARTED WITH THE ST7 HIWARE C TOOLCHAIN
ST7 MATH UTILITY ROUTINES
WRITING OPTIMIZED HIWARE C LANGUAGE FOR ST7
TRANSLATING ASSEMBLY CODE FROM HC05 TO ST7
USING THE ST72521 EMULATOR TO DEBUG A ST72324 TARGET APPLICATION
PORTING AN ST7 PANTA PROJECT TO CODEWARRIOR IDE
ON-BOARD PROGRAMMING METHODS FOR XFLASH AND HDFLASH ST7 MCUS
IN-APPLICATION PROGRAMMING (IAP) DRIVERS FOR ST7 HDFLASH OR XFLASH MCUS
ST7 CUSTOMER ROM CODE RELEASE INFORMATION
DATA LOGGING PROGRAM FOR TESTING ST7 APPLICATIONS VIA ICC
FIELD UPDATES FOR FLASH BASED ST7 APPLICATIONS USING A PC COMM PORT
SYSTEM OPTIMIZATION
AN1711
SOFTWARE TECHNIQUES FOR COMPENSATING ST7 ADC ERRORS
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ST72324
15 KNOWN LIMITATIONS
15.1 ALL DEVICES
Example:
SIM
15.1.1 External RC option
reset interrupt flag
The External RC clock source option described in
previous datasheet revisions is no longer support-
ed and has been removed from this specification.
RIM
Nested interrupt context:
15.1.2 CSS Function
The symptom does not occur when the interrupts
are handled normally, i.e.
The Clock Security System function has been re-
moved from the datasheet.
when:
15.1.3 Safe Connection of OSC1/OSC2 Pins
– The interrupt flag is cleared within its own inter-
rupt routine
The OSC1 and/or OSC2 pins must not be left un-
connected otherwise the ST7 main oscillator may
start and, in this configuration, could generate an
– The interrupt flag is cleared within any interrupt
routine with higher or identical priority level
f
clock frequency in excess of the allowed
OSC
– The interrupt flag is cleared in any part of the
code while this interrupt is disabled
maximum (>16MHz.), putting the ST7 in an un-
safe/undefined state. Refer to Section 6.2 on page
24.
If these conditions are not met, the symptom can
be avoided by implementing the following se-
quence:
15.1.4 Unexpected Reset Fetch
If an interrupt request occurs while a “POP CC” in-
struction is executed, the interrupt controller does
not recognise the source of the interrupt and, by
default, passes the RESET vector address to the
CPU.
PUSH CC
SIM
reset interrupt flag
POP CC
Workaround
15.1.6 16-bit Timer PWM Mode
To solve this issue, a “POP CC” instruction must
always be preceded by a “SIM” instruction.
In PWM mode, the first PWM pulse is missed after
writing the value FFFCh in the OC1R register
(OC1HR, OC1LR). It leads to either full or no PWM
during a period, depending on the OLVL1 and
OLVL2 settings.
15.1.5 Clearing active interrupts outside
interrupt routine
When an active interrupt request occurs at the
same time as the related flag is being cleared, an
unwanted reset may occur.
15.1.7 SCI Wrong Break duration
Description
Note: clearing the related interrupt mask will not
generate an unwanted reset
A single break character is sent by setting and re-
setting the SBK bit in the SCICR2 register. In
some cases, the break character may have a long-
er duration than expected:
Concurrent interrupt context
The symptom does not occur when the interrupts
are handled normally, i.e.
- 20 bits instead of 10 bits if M=0
- 22 bits instead of 11 bits if M=1.
when:
– The interrupt flag is cleared within its own inter-
rupt routine
In the same way, as long as the SBK bit is set,
break characters are sent to the TDO pin. This
may lead to generate one break more than expect-
ed.
– The interrupt flag is cleared within any interrupt
routine
– The interrupt flag is cleared in any part of the
code while this interrupt is disabled
Occurrence
The occurrence of the problem is random and pro-
portional to the baudrate. With a transmit frequen-
cy of 19200 baud (fCPU=8MHz and SCI-
BRR=0xC9), the wrong break duration occurrence
is around 1%.
If these conditions are not met, the symptom can
be avoided by implementing the following se-
quence:
Perform SIM and RIM operation before and after
resetting an active interrupt request.
159/163
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ST72324
Workaround
- Set and Reset SBK (Break Request)
- Re-enable interrupts
If this wrong duration is not compliant with the
communication protocol in the application, soft-
ware can request that an Idle line be generated
before the break character. In this case, the break
duration is always correct assuming the applica-
tion is not doing anything between the idle and the
break. This can be ensured by temporarily disa-
bling interrupts.
15.2 FLASH DEVICES ONLY
15.2.1 Internal RC Operation
In ST72F324J and ST72F324K devices, the inter-
nal RC oscillator is not supported if the LVD is dis-
abled.
The exact sequence is:
- Disable interrupts
- Reset and Set TE (IDLE request)
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ST72324
16 IMPORTANT NOTES ON ST72F324B FLASH DEVICES:
With the objective of continuous improvement, ST
has developed new ST72F324B devices. These
devices are fully compatible with all ROM features
and provide an improved price/performance ratio
compared to the ST72F324 flash devices.
16.5 Timer A Registers
In ST72F324B Flash devices, all Timer A registers
are present and their functionality is the same as
described for ROM devices in the ST72324B da-
tasheet.
A summary of the technical improvements is given
below.
Refer to separate ST72324B datasheet for the or-
dering information and full specifications.
16.1 Reset Pin Logic levels
In ST72F324B Flash devices, the V /V levels for
IH IL
the reset pin are the same as specified for ROM
devices
16.2 Wake-Up from Active Halt mode using
external interrupts
In ST72F324B Flash devices, any external inter-
rupt that capable of waking-up the MCU from Halt
mode can also wake-up the MCU from Active Halt
mode. Consequently note 1 below Table 8 on
page 36 does not apply to ‘B’ devices.
16.3 PLL Jitter
In ST72F324B Flash devices, PLL clock accuracy
is improved and the jitter is the same as specified
for ROM devices
16.4 Active Halt Power Consumption
In ST72F324B Flash devices, the power con-
sumption in Active Halt mode is specified as
230µA max. See Table 12.5.1 on page 120 for test
conditions.
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ST72324
17 REVISION HISTORY
Table 34. Revision History
Date
Revision
Description of Changes
Merged ST72F324 Flash with ST72324B ROM datasheet.
Vt POR max modified in Section 12.4 on page 119
Added Figure 78 on page 137
05-May-2004
2.0
Modified V
min in “10-BIT ADC CHARACTERISTICS” on page 142
AREF
Modified I INJ for PB0 in Section 12.9
Added “Clearing active interrupts outside interrupt routine” on page 159
Modified “32K ROM DEVICES ONLY” on page 164
Removed Clock Security System (CSS) throughout document
Added notes on ST72F324B 8K/16K Flash devices in Table 1 and Table 27
Corrected MCO description in Table 1 and Section 10.2
Modified VtPOR in Section 12.4 on page 119
Static current consumption modified in Section 12.9 on page 133
Updated footnote and Figure 77 and Figure 78 on page 137
Modified Soldering information in Section 13.3
30-Mar-2005
3
Updated Section 14 on page 150
Added Table 27
Modified Figure 7 and note 4 in “FLASH PROGRAM MEMORY” on page 17
Added limitation on ICC entry mode with 39 pulses to “KNOWN LIMITATIONS” on
page 159
Added Section 16 on page 161 for ST72F324B 8K/16K Flash devices
Modified “Internal Sales Types on box label” in Table 29
08-Nov-2005
4
Removed information on ST72F324B and ROM devices (now in separate datasheet)
162/163
1
ST72324
Notes:
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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All other names are the property of their respective owners
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163/163
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