ST72F345S4T6_技术文档

ST72344xx

ST72345xx

8-bit MCU with up to 16K Flash memory, 10-bit ADC

two 16-bit timers, two I2C, SPI, SCI

Features

■ Memories

– up to 16 Kbytes Program memory: single

voltage extended Flash (XFlash) with read-

out and write protection, in-circuit and in-

application programming (ICP and IAP).

10K write/erase cycles guaranteed, data

retention: 20 years at 55 °C.

LQFP48

7 x 7 mm

LQFP32

7 × 7 mm

LQFP44

10 × 10 mm

– 16-bit timer B with: 2 input captures, 2

output compares, PWM and pulse

generator modes

– up to 1 Kbyte RAM

– 256 bytes data EEPROM with readout

protection. 300K write/erase cycles

guaranteed, data retention: 20 years at

55 °C.

■ 3 communication interfaces

2

– I C multimaster / slave

2

– I C slave 3 addresses no stretch with DMA

access and byte pair coherency on I²C

Read

■ Clock, reset and supply management

– Power on / power off safe reset with 3

programmable threshold levels (LVD)

– SCI asynchronous serial interface (LIN

compatible)

– Auxiliary voltage detector (AVD)

– SPI synchronous serial interface

– Clock sources: crystal/ceramic resonator

oscillators, high-accuracy internal RC

oscillator or external clock

– PLL for 4x or 8x frequency multiplication

– 5 power-saving modes: Slow, Wait, Halt,

Auto-wakeup from Halt and Active-halt

■ 1 analog peripheral

– 10-bit ADC with 12 input channels (8 on 32-

pin devices)

■ Instruction set

– 8-bit data manipulation

– 63 basic instructions with illegal opcode

detection

– Clock output capability (f

)

CPU

■ Interrupt management

– 17 main addressing modes

– 8 x 8 unsigned multiply instruction

– Nested interrupt controller

– 10 interrupt vectors plus TRAP and RESET

– 9 external interrupt lines on 4 vectors

■ Development tools

– Full hardware/software development

package

■ Up to 34 I/O ports

– up to 34 multifunctional bidirectional I/O

lines

– On-chip debug module

– up to 12 high sink outputs (10 on 32-pin

devices)

Table 1.

Device summary

Part numbers

References

■ 4 timers

ST72344K2, ST72344K4,

ST72344S2, ST72344S4

– Configurable window watchdog timer

– Real-time base

– 16-bit timer A with: 1 input capture, 1 output

compares, external clock input, PWM and

pulse generator modes

ST72344xx

ST72345xx

ST72345C4

September 2008

Rev 3

1/246

www.st.com

1

Contents

ST72344xx, ST72345xx

Contents

1

2

3

4

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Register and memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.1

4.2

4.3

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Programming modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.3.1

4.3.2

In-circuit programming (ICP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

In-application programming (IAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.4

4.5

ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4.5.1

4.5.2

Readout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Flash write/erase protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

4.6

Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

4.6.1

Flash control/status register (FCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5

Data EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.1

5.2

5.3

5.4

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Memory access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.4.1

5.4.2

5.4.3

Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Active-halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.5

5.6

5.7

Access error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Data EEPROM readout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

5.7.1

EEPROM control/status register (EECSR) . . . . . . . . . . . . . . . . . . . . . . 35

6

Central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

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Contents

6.1

6.2

6.3

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

6.3.1

6.3.2

Condition code register (CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Stack pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

7

Supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . 41

7.1

7.2

7.3

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Phase locked loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Multioscillator (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

7.3.1

7.3.2

7.3.3

External clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Crystal/ceramic oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Internal RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

7.4

7.5

Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

7.4.1

7.4.2

RC control register (RCCRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

RC control register (RCCRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Reset sequence manager (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

7.5.1

7.5.2

7.5.3

7.5.4

7.5.5

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Asynchronous external RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

External power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Internal low-voltage detector (LVD) reset . . . . . . . . . . . . . . . . . . . . . . . . 48

Internal watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

7.6

System integrity management (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

7.6.1

7.6.2

7.6.3

7.6.4

7.6.5

Low-voltage detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Auxiliary-voltage detector (AVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

8

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

8.1

8.2

8.3

8.4

8.5

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Masking and processing flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Interrupts and low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Concurrent & nested management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Interrupt register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

8.5.1

CPU CC register interrupt bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

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8.5.2

Interrupt software priority registers (ISPRX) . . . . . . . . . . . . . . . . . . . . . 58

8.6

8.7

External interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

8.6.1

I/O port interrupt sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

External interrupt control register (EICR) . . . . . . . . . . . . . . . . . . . . . . . . . 61

9

Power-saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

9.1

9.2

9.3

9.4

9.5

9.6

9.7

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Active-halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Auto-wakeup from Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

9.7.1

9.7.2

AWUFH control/status register (AWUCSR) . . . . . . . . . . . . . . . . . . . . . . 72

AWUFH prescaler register (AWUPR) . . . . . . . . . . . . . . . . . . . . . . . . . . 73

10

I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

10.2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

10.2.1 Input modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

10.2.2 Output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

10.2.3 Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

10.3 I/O port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

10.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

10.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

10.5.1 I/O port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

11

On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

11.1 Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

11.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

11.1.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

11.1.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

11.1.4 Using Halt mode with the WDG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

11.1.5 How to program the watchdog timeout . . . . . . . . . . . . . . . . . . . . . . . . . 84

11.1.6 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

11.1.7 Hardware watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

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11.1.8 Using Halt mode with the WDG (WDGHALT option) . . . . . . . . . . . . . . . 87

11.1.9 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

11.1.10 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

11.2 Main clock controller with real-time clock and beeper (MCC/RTC) . . . . . 88

11.2.1 Programmable CPU clock prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

11.2.2 Clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

11.2.3 Real-time clock timer (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

11.2.4 Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

11.2.5 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

11.2.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

11.2.7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

11.3 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

11.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

11.3.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

11.3.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

11.3.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

11.3.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

11.3.6 Summary of timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

11.3.7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

11.4 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

11.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

11.4.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

11.4.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

11.4.4 Clock phase and clock polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

11.4.5 Error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

11.4.6 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

11.4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

11.4.8 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

11.5 SCI serial communication interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

11.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

11.5.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

11.5.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

11.5.4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

11.5.5 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

11.5.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

11.5.7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

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11.6 I2C bus interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

11.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

11.6.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

11.6.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

11.6.4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

11.6.5 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

11.6.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

11.6.7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

11.7 I2C triple slave interface with DMA (I2C3S) . . . . . . . . . . . . . . . . . . . . . . 166

11.7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

11.7.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

11.7.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

11.7.4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

11.7.5 Address handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

11.7.6 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

11.7.7 Interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

11.7.8 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

11.8 10-bit A/D converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

11.8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

11.8.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

11.8.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

11.8.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

11.8.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

11.8.6 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

12

Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

12.1 ST7 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

12.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

12.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

12.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

12.1.4 Indexed (No Offset, Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

12.1.5 Indirect (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

12.1.6 Indirect Indexed (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

12.1.7 Relative Mode (direct, indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

12.2 Instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

12.2.1 Illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

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13

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

13.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

13.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

13.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

13.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

13.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

13.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

13.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

13.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

13.4 Internal RC oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

13.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

13.6 Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

13.6.1 Crystal and ceramic resonator oscillators . . . . . . . . . . . . . . . . . . . . . . 209

13.7 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

13.8 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

13.8.1 Functional EMS (electromagnetic susceptibility) . . . . . . . . . . . . . . . . . 212

13.8.2 EMI (electromagnetic interference) . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

13.8.3 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 213

13.9 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

13.10 Control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

13.10.1 Asynchronous RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

13.11 Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . 223

13.11.1 I2C and I²C3SNS interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

13.12 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

14

15

Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226

Device configuration and ordering information . . . . . . . . . . . . . . . . . 231

15.1 Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

15.1.1 Option byte 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

15.1.2 Option byte 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232

15.1.3 Option byte 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233

15.1.4 Option byte 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234

15.2 Device ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235

15.3 Development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235

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15.3.1 Starter kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235

15.3.2 Development and debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

15.3.3 Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

15.3.4 Order codes for ST72F34x development tools . . . . . . . . . . . . . . . . . . 237

16

Known limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238

16.1 External interrupt missed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238

16.1.1 Workaround . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238

16.1.2 Unexpected reset fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

16.2 Clearing active interrupts outside interrupt routine . . . . . . . . . . . . . . . . . 240

16.3 16-bit timer PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

16.4 TIMD set simultaneously with OC interrupt . . . . . . . . . . . . . . . . . . . . . . 241

16.4.1 Impact on the application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

16.4.2 Workaround . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

16.5 SCI wrong break duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

16.5.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

16.5.2 Occurrence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

16.5.3 Workaround . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

16.6 In-application programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

16.7 Programming of EEPROM data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

16.7.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

16.7.2 Impact on application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

16.7.3 Workaround . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

16.8 Flash write/erase protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

17

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

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List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Device pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Data EEPROM register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Interrupt software priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

PLL configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

ST7 clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Low-power mode description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Interrupt event. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

LVDRF and WDGRF description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Interrupt software priority levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Interrupt software priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Interrupt vector addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Dedicated interrupt instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

External interrupt sensitivity (ei2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

External interrupt sensitivity (ei3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

External interrupt sensitivity (ei0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

External interrupt sensitivity (ei1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Nested interrupts register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Power saving mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

AWUPR dividing factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

AWU register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

I/O Port mode options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

I/O port configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Description of interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

I/O port register configurations (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

I/O port register configurations (interrupt ports with pull-up). . . . . . . . . . . . . . . . . . . . . . . . 79

I/O port register configurations (interrupt ports without pull-up) . . . . . . . . . . . . . . . . . . . . . 79

I/O port register configurations (true open drain ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

I/O port register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Watchdog timer register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Mode description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Interrupt event. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

CPU clock prescaler selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Time base control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Beep control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Main clock controller register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

ICiR register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

OCiR register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Low-power mode description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Interrupt events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Table 9.

Table 10.

Table 11.

Table 12.

Table 13.

Table 14.

Table 15.

Table 16.

Table 17.

Table 18.

Table 19.

Table 20.

Table 21.

Table 22.

Table 23.

Table 24.

Table 25.

Table 26.

Table 27.

Table 28.

Table 29.

Table 30.

Table 31.

Table 32.

Table 33.

Table 34.

Table 35.

Table 36.

Table 37.

Table 38.

Table 39.

Table 40.

Table 41.

Table 42.

Table 43.

Table 44.

Table 45.

Table 46.

Table 47.

Table 48.

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List of tables

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Table 49.

Table 50.

Table 51.

Table 52.

Table 53.

Table 54.

Table 55.

Table 56.

Table 57.

Table 58.

Table 59.

Table 60.

Table 61.

Table 62.

Table 63.

Table 64.

Table 65.

Table 66.

Table 67.

Table 68.

Table 69.

Table 70.

Table 71.

Table 72.

Table 73.

Table 74.

Table 75.

Table 76.

Table 77.

Table 78.

Table 79.

Table 80.

Table 81.

Table 82.

Table 83.

Table 84.

Table 85.

Table 86.

Table 87.

Table 88.

Table 89.

Table 90.

Table 91.

Table 92.

Table 93.

Table 94.

Table 95.

Table 96.

Table 97.

Table 98.

Table 99.

Timer modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Clock control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

16-bit timer register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Interrupt events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

SPI master mode SCK frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

SPI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Mode description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Interrupt events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

SCP[1:0] configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

SCT[2:0] configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

SCR[2:0] configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

Baud rate selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

SCI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

Mode description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

FR[1:0] configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

I2C register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

Mode description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Interrupt events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

PL configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

I2C3S register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

Mode description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

Channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

ADC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

Addressing mode groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

ST7 addressing mode overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

Inherent instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

Immediate instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

Instructions supporting direct, indexed, indirect and indirect indexed addressing modes 193

Short instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

Relative direct/indirect instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

Main instruction groups. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

Illegal opcode detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

LVD thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

AVD thresholds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

Internal RC oscillator and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

Internal RC oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

Supply current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

General timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

External clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

Auto-wakeup from Halt oscillator (AWU) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 209

Crystal/ceramic resonator oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

Recommended load capacitance vs. equivalent serial resistance of ceramic

resonator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

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Table 100. RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

Table 101. Flash program memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

Table 102. EEPROM data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

Table 103. EMS test results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

Table 104. EMI emissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

Table 105. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

Table 106. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

Table 107. General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

Table 108. Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

Table 109. Asynchronous RESET pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

Table 110. I2C and I²C3SNS interfaces characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

2

Table 111. SCL frequency table (multimaster I C interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

Table 112. ADC accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

Table 113. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

Table 114. 32-pin low profile quad flat package (7 x 7 mm) mechanical data . . . . . . . . . . . . . . . . . . 226

Table 115. 40-lead very thin fine pitch quad flat no-lead package mechanical data . . . . . . . . . . . . . 227

Table 116. 44-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . 228

Table 117. 48-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

Table 118. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230

Table 119. LVD threshold configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

Table 120. Size of sector 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

Table 121. Selection of the resonator oscillator range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233

Table 122. List of valid option combinations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233

Table 123. Package selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234

Table 124. Option byte default values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234

Table 126. Silicon revision identification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

Table 127. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

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List of figures

Figure 1.

Figure 2.

Figure 3.

Figure 4.

Figure 5.

Figure 6.

Figure 7.

Figure 8.

Figure 9.

General block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

LQFP32 package pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

LQFP44 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

LQFP48 package pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Typical ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

EEPROM block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Data EEPROM programming flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Data EEPROM write operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 10. Data EEPROM programming cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 11. CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 12. Stack manipulation example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 13. Clock, reset and supply block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 14. PLL output frequency timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 15. reset sequence phases. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 16. Reset block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 17. Reset sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 18. Low voltage detector vs. reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 19. Using the AVD to monitor VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 20. Interrupt processing flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 21. Priority decision process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 22. Concurrent interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 23. Nested interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Figure 24. External interrupt control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Figure 25. Power saving mode transitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Figure 26. Slow mode clock transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Figure 27. Wait mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Figure 28. Halt timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Figure 29. Halt mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Figure 30. Active-halt timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Figure 31. Active-halt mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Figure 32. AWUFH mode block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Figure 33. AWUF Halt timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 34. AWUFH mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 35. I/O port general block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Figure 36. Interrupt I/O port state transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Figure 37. Watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Figure 38. Approximate timeout duration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Figure 39. Exact timeout duration (tmin and tmax) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Figure 40. Window watchdog timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Figure 41. Main clock controller (MCC/RTC) block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Figure 42. Timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Figure 43. 16-bit read sequence (from either the counter register or the alternate

counter register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Figure 44. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Figure 45. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Figure 46. Counter timing diagram, internal clock divided by 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Figure 47. Input capture block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

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List of figures

Figure 48. Input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Figure 49. Output compare block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Figure 50. Output compare timing diagram, f

Figure 51. Output compare timing diagram, f

= f

/2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

/4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

TIMER

CPU

TIMER

CPU

Figure 52. One-pulse mode cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Figure 53. One-pulse mode timing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Figure 54. Pulse width modulation mode timing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Figure 55. Pulse width modulation cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Figure 56. Serial peripheral interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Figure 57. Single master/ single slave application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Figure 58. Generic SS timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Figure 59. Hardware/software slave select management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Figure 60. Data clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Figure 61. Clearing the WCOL bit (write collision flag) software sequence . . . . . . . . . . . . . . . . . . . . 123

Figure 62. Single master / multiple slave configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Figure 63. SCI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Figure 64. Word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Figure 65. SCI baud rate and extended prescaler block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

Figure 66. Bit sampling in reception mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Figure 67. I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

Figure 68. I2C interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Figure 69. Transfer sequencing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

Figure 70. Event flags and interrupt generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Figure 71. I2C3S interface block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

Figure 72. I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

Figure 73. 16-bit word write operation flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Figure 74. 16-bit word read operation flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

Figure 75. Transfer sequencing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

Figure 76. Byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

Figure 77. Page write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

Figure 78. Current address read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

Figure 79. Random read (dummy write + restart + current address read). . . . . . . . . . . . . . . . . . . . . 174

Figure 80. Random read (dummy write + stop + start + current address read). . . . . . . . . . . . . . . . . 175

Figure 81. Sequential read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Figure 82. Combined format for read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Figure 83. Event flags and interrupt generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

Figure 84. ADC block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

Figure 85. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

Figure 86. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

Figure 87.

Figure 88. Typical RC frequency vs. RCCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

Figure 89. Typical I in Run vs. f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

f

maximum operating frequency versus V supply voltage . . . . . . . . . . . . . . . . . . . 201

CPU DD

DD

CPU

Figure 90. Typical I in Run at f

= 8 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

DD

CPU

Figure 91. Typical I in Slow vs. f

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

CPU

DD

Figure 92. Typical I in Wait vs. f

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

DD

CPU

Figure 93. Typical I in Wait at f

= 8 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

DD

CPU

Figure 94. Typical I in Slow-wait vs. f

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

DD

CPU

Figure 95. Typical I vs. temp. at V = 5 V and f = 8 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

DD

CPU

Figure 96. Typical application with an external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

Figure 97. Typical application with a crystal or ceramic resonator . . . . . . . . . . . . . . . . . . . . . . . . . . 210

Figure 98. Two typical applications with unused I/O pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

Figure 99. Typical V at V = 2.4 V (std I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

OL

DD

13/246

List of figures

ST72344xx, ST72345xx

Figure 100. Typical V at V = 3 V (std I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

OL

DD

Figure 101. Typical V at V = 5 V (std I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

OL

DD

Figure 102. Typical V at V = 2.4 V (high-sink I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

OL

DD

Figure 103. Typical V at V = 3 V (high-sink I/Os). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

OL

DD

Figure 104. Typical V at V = 5 V (high-sink I/Os). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

OL

DD

Figure 105. Typical V vs. V (std I/Os, 2 mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

OL

DD

Figure 106. Typical V vs. V (std I/Os, 6 mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

OL

DD

Figure 107. Typical V vs. V (HS I/Os, I = 8 mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

OL

DD

IO

Figure 108. Typical V vs. V (HS I/Os, I = 2 mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

OL

DD

IO

Figure 109. Typical V vs. V (HS I/Os, I = 12 mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

OL

DD

IO

Figure 110. Typical V – v at V = 2.4 V (std I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

DD

OH

DD

Figure 111. Typical V – V at V = 3 V (std I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

DD

OH

DD

Figure 112. Typical V – V at V = 4 V (std). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

DD

OH

DD

Figure 113. Typical V – V at V = 5 V (std) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

DD

OH

DD

Figure 114. Typical V – V vs. VDD (high sink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

DD

OH

Figure 115. RESET pin protection when LVD is enabled(1)(2)(3)(4). . . . . . . . . . . . . . . . . . . . . . . . . . 222

Figure 116. RESET pin protection when LVD is disabled(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222

Figure 117. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

Figure 118. Typical A/D converter application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

Figure 119. 32-pin low profile quad flat package (7 x 7 mm) outline . . . . . . . . . . . . . . . . . . . . . . . . . . 226

Figure 120. 40-lead very thin fine pitch quad flat no-lead package outline . . . . . . . . . . . . . . . . . . . . . 227

Figure 121. 44-pin low profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228

Figure 122. 48-pin low profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

Figure 123. ST7234x ordering information scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235

14/246

ST72344xx, ST72345xx

Introduction

1

Introduction

The ST7234x devices are members of the ST7 microcontroller family. Table 2 gives the

available part numbers and details on the devices. All devices are based on a common

industry-standard 8-bit core, featuring an enhanced instruction set.

They feature single-voltage Flash memory with byte-by-byte in-circuit programming (ICP)

and in-application programming (IAP) capabilities.

Under software control, all devices can be placed in Wait, Slow, Auto-wakeup from Halt,

Active-halt or Halt mode, reducing power consumption when the application is in idle or

stand-by state.

The enhanced instruction set and addressing modes of the ST7 offer both power and

flexibility to software developers, enabling the design of highly efficient and compact

application code. In addition to standard 8-bit data management, all ST7 microcontrollers

feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes.

The devices feature an on-chip debug module (DM) to support in-circuit debugging (ICD).

For a description of the DM registers, refer to the ST7 ICC Protocol Reference Manual.

Figure 1.

General block diagram

8-BIT CORE

ALU

PROGRAM

MEMORY

(16K - 32K Bytes)

RESET

CONTROL

RAM

(512- 1024 Bytes)

V_SS

V_DD

LVD

AVD

WATCHDOG

I2CMMS

OSC1

OSC2

CLOCK CONTROL

PA

(5-bits)

INTERNAL RC

PORT A

MCC/RTC/BEEP

PORT B

PB

(5-bits)

PORT F

TIMER A

BEEP

PWM ART

PF

(6-bits)

PORT C

TIMER B

SPI

PC

(8-bits)

I2C3SNS

PD

(6-bits)

PORT D

PORT E

SCI

10-BIT ADC

PE

(2-bits)

V_AREF

V_SSA

15/246

Introduction

ST72344xx, ST72345xx

ST72345C4

Table 2.

Device summary

ST72344K2, ST72344K4, ST72344S2,

Features

ST72344S4

Program memory - bytes

RAM (stack) - bytes

EEPROM data - bytes

Common peripherals

Other peripherals

CPU frequency

8K

512 (256)

256

16K

1K (256)

256

16K

1K (256)

256

Window Watchdog, 2 16-bit timers, SCI, SPI, I2CMMS

10-bit ADC I2C3SNS, 10-bit ADC

8 MHz @ 3.3 V to 5.5 V, 4 MHz @ 2.7 V to 5.5 V

-40 °C to +85 °C

Temperature range

Package

LQFP32 7x7, LQFP44 10x10

LQFP48 7x7

16/246

ST72344xx, ST72345xx

Pin description

2

Pin description

Figure 2.

LQFP32 package pinout

32 31 30 29 28 27 26 25

ei3 ei2 ei0

V_DDA

V_SSA

AIN8 / PF0

1

2

3

24

23

22

OSC1

OSC2

V

_SS_2

ei1

4

21

(HS) PF1

OCMP1_A / AIN10 / PF4

ICAP1_A / (HS) PF6

EXTCLK_A / (HS) PF7

AIN12 / OCMP2_B / PC0

RESET

ICCSEL

PA7 (HS) / SCL

PA6 (HS) / SDA

PA4 (HS)

5

6

7

8

20

19

18

17

ei0

10 11 12 13 14 15 16

9

(HS) 20mA high sink capability

eix associated external interrupt vector

17/246

Pin description

Figure 3.

ST72344xx, ST72345xx

LQFP44 package pinout

44 43 42 41 40 39 38 37 36 35 34

ei0

RDI / PE1

PB0

1

33 V_{SS_1}

2

32

31

30

29

28

27

26

25

24

23

V_{DD_1}

3

ei0

PB1

PA3 (HS)

ei2

ei3

4

PB2

PC7 / SS / AIN15

5

PB3

PC6 / SCK / ICCCLK

PC5 / MOSI / AIN14

PC4 / MISO / ICCDATA

PC3 (HS) / ICAP1_B

PC2 (HS) / ICAP2_B

PC1 / OCMP1_B / AIN13

PC0 / OCMP2_B / AIN12

6

(HS) PB4

AIN0 / PD0

AIN1 / PD1

AIN2 / PD2

AIN3 / PD3

AIN4 / PD4

7

8

9

10

11

ei1

12 13 14 15 16 17 18 19 20 21 22

18/246

ST72344xx, ST72345xx

Figure 4.

Pin description

LQFP48 package pinout

48 47 46 45 44 43 42 41 40 39 38 37

36

35

34

33

32

31

30

29

28

27

26

25

1

V_{SS_1}

PE0/TD0

RDI / PE1

PB0

2

ei0

ei2

ei3

V_{DD_1}

ei0

3

PA3 (HS)

PC7 / SS / AIN15

4

PB1

5

PB2

PC6 / SCK / ICCCLK

PC5 / MOSI / AIN14

PC4 / MISO / ICCDATA

PC3 (HS) / ICAP1_B

PC2 (HS) / ICAP2_B

PC1 / OCMP1_B / AIN13

NC

6

PB3

7

(HS) PB4

AIN0 / PD0

AIN1 / PD1

AIN2 / PD2

AIN3 / PD3

AIN4 / PD4

8

9

10

11

12

ei1

NC

24

13 14 15 16 17 18 19 20 21 22 23

Note:

For external pin connection guidelines, refer to Section 13: Electrical characteristics on

page 198

19/246

Pin description

Legend / Abbreviations for Table 3:

ST72344xx, ST72345xx

Type:

I = input, O = output, S = supply

A = Dedicated analog input

Input level:

In/Output level: C = CMOS 0.3V /0.7V with input trigger

T

DD

Output level:

HS = 20 mA high sink (on N-buffer only)

Port and control configuration:

1)

●

Input:

float = floating, wpu = weak pull-up, int = interrupt , ana = analog

2)

Output:

OD = open drain , PP = push-pull

The reset configuration of each pin is shown in bold. This configuration is valid as long as

the device is in reset state.

On the chip, each I/O port may have up to 8 pads. Pads that are not bonded to external pins

are set in input pull-up configuration after reset through the option byte Package selection.

The configuration of these pads must be kept at reset state to avoid added current

consumption.

Table 3.

Pin n°

Device pin description

Level

Port

Input ⁽¹⁾

Main

function

(after

Output

Pin name

Alternate function

reset)

(2)

1

2

13 14 V_DDA

14 15 V_SSA

S

Analog supply voltage

Analog ground voltage

Main clock ADC

out analog

(f_OSC/2) input 8

3

15 16 PF0/MCO/AIN8

I/O C_T

X

ei1

X

Port F0

4

-

16 17 PF1 (HS)/BEEP

17 18 PF2 (HS) ⁽³⁾

I/O C_THS

X

Port F1

Port F2

Beep signal output

ei1

Timer A

output

ADC

analog

5

18 19 PF4/OCMP1_A/AIN10

I/O C_T

X

Port F4

compare 1 input 10

Timer A Input

Capture 1

6

7

19 20 PF6 (HS)/ICAP1_A

20 21 PF7 (HS)/EXTCLK_A

I/O C_THS

X

Port F6

Port F7

Timer A external

clock source

(2)

-

21 22 V_{DD_0}

S

Digital main supply voltage

Digital ground voltage

(2)

22 23 V_{SS_0}

Timer B

Port C0 output

ADC

analog

8

9

23 24 PC0/OCMP2_B/AIN12

24 27 PC1/OCMP1_B/AIN13

I/O C_T

X

compare 2 input 12

Timer B

ADC

Port C1 output

analog

compare 1 input 13

20/246

ST72344xx, ST72345xx

Pin description

Alternate function

Table 3.

Pin n°

Device pin description (continued)

Level

Port

Input ⁽¹⁾

Main

function

(after

Output

Pin name

reset)

Timer B input capture

2

10 25 28 PC2 (HS)/ICAP2_B

11 26 29 PC3 (HS)/ICAP1_B

I/O C_THS

X

Port C2

Port C3

Timer B input capture

1

SPIMaster

ICC data

12 27 30 PC4/MISO/ICCDATA

13 28 31 PC5/MOSI/AIN14

14 29 32 PC6/SCK/ICCCLK

I/O C_T

X

Port C4 In / Slave

Out data

input

SPIMaster ADC

Port C5 Out / Slave analog

X

In data

input 14

ICC

clock

output

SPI serial

clock

Port C6

SPI slave

select

(active

low)

ADC

analog

input 15

15 30 33 PC7/SS/AIN15

I/O C_T

X

Port C7

Port A3

16 31 34 PA3 (HS)

I/O C_THS

ei0

(2)

-

32 35 V_{DD_1}

33 36 V_{SS_1}

S

Digital main supply voltage

Digital ground voltage

(2)

T

-

37 PD7 ⁽³⁾/ SCL3SNS

38 PD6 ⁽³⁾/ SDA3SNS

I/O C_THS

X

Port D7 I2C3SNS serial clock

(4)

I/O C_THS

I

X

T

X

T

Port D6 I2C3SNS serial data

Port A4

17 34 39 PA4 (HS)

35 40 PA5 (HS) ⁽³⁾

X

-

Port A5

18 36 41 PA6 (HS)/SDA

19 37 42 PA7 (HS)/SCL

20 38 43 ICCSEL ⁽⁵⁾

Port A6 I2C serial data

Port A7 I2C serial clock

ICC mode selection

Top priority non maskable

interrupt.

21 39 44 RESET

I/O C_T

(2)

22 40 45 V_{SS_2}

S

Digital ground voltage

Resonator oscillator inverter

output

23 41 46 OSC2

24 42 47 OSC1

O

External clock input or resonator

oscillator inverter input

I

(2)

25 43 48 V_{DD_2}

S

Digital main supply voltage

26 44

1

PE0/TDO

I/O C_T

X

Port E0 SCI transmit data out

21/246

Pin description

ST72344xx, ST72345xx

Table 3.

Pin n°

Device pin description (continued)

Level

Port

Input ⁽¹⁾

Main

function

(after

Output

Pin name

Alternate function

reset)

27

28

-

1

2

3

4

5

6

7

8

9

2

3

4

5

6

7

8

9

PE1/RDI

I/O C_T

X

ei0

ei2

X

Port E1 SCI receive data in

Port B0

PB0

I/O C_T

I/O C_THS

I/O C_T

PB1 ⁽³⁾

PB2 ⁽³⁾

PB3

ei2

Port B1

-

Port B2

29

30

31

32

-

ei2

ei3

Port B3

PB4 (HS)

PD0/AIN0

PD1/AIN1

Port B4

X

Port D0 ADC analog input 0

Port D1 ADC analog input 1

Port D2 ADC analog input 2

Port D3 ADC analog input 3

Port D4 ADC analog input 4

Port D5 ADC analog input 5

10 PD2/AIN2

-

10 11 PD3/AIN3

11 12 PD4/AIN4

12 13 PD5/AIN5

-

1. In the interrupt input column, “eiX” defines the associated external interrupt vector. If the weak pull-up column (wpu) is

merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input, else the configuration is floating

interrupt input.

2. It is mandatory to connect all available V_DDand V_DDApins to the supply voltage and all V_SSand V_SSApins to ground.

3. Pulled-up by hardware when not present on the package.

4. In the open drain output column, “T” defines a true open drain I/O (P-Buffer and protection diode to V_DDare not

implemented).

5. Internal weak pull-down.

22/246

ST72344xx, ST72345xx

Register and memory map

3

Register and memory map

As shown in Figure 5, the MCU is capable of addressing 64 Kbytes of memories and I/O

registers.

The available memory locations consist of 128 bytes of register locations, up to 1 Kbytes of

RAM, 256 bytes of Data EEPROM and up to 16 Kbytes of user program memory. The RAM

space includes up to 256 bytes for the stack from 0100h to 01FFh.

The highest address bytes contain the user reset and interrupt vectors.

Figure 5.

Memory map

0000h

0080h

HW registers

Short addressing

RAM (zero page)

See Table 4

007Fh

0080h

00FFh

0100h

RAM

(512 or 1K Bytes)

047Fh

0480h

256 Bytes stack

01FFh

0200h

Reserved

16-bit addressing

RAM

0BFFh

0C00h

Data EEPROM

(256 Bytes)

047Fh

C000h

0CFFh

0D00h

C000h

E000h

Reserved

SECTOR 2

SECTOR 1

SECTOR 0

BFFFh

C000h

16 Kbytes

8 Kbytes

Program memory

(8 or 16 KBytes)

E000h

FFFFh

FFDFh

FFE0h

F000h (4k)

or FB00h (2k)

or FC00h (1k)

or FE00h (0.5k)

Interrupt & Reset Vectors

See Table 17

FFFFh

23/246

Register and memory map

ST72344xx, ST72345xx

Table 4.

Address

Hardware register map

Register

label

Reset

Block

Register name

Remarks⁽²⁾

status⁽¹⁾

0000h

0001h

0002h

PADR

Port A Data Register

Port A Data Direction Register

Port A Option Register

00h ⁽⁴⁾

00h

R/W

Port A⁽³⁾PADDR

PAOR

0003h

0004h

0005h

PBDR

Port B⁽³⁾PBDDR

PBOR

Port B Data Register

Port B Data Direction Register

Port B Option Register

00h ⁽⁴⁾

00h

R/W

0006h

0007h

0008h

PCDR

Port C⁽³⁾PCDDR

PCOR

Port C Data Register

Port C Data Direction Register

Port C Option Register

00h ⁽⁴⁾

00h

R/W

0009h

000Ah

000Bh

PDADR

Port D⁽³⁾PDDDR

PDOR

Port D Data Register

Port D Data Direction Register

Port D Option Register

00h⁽⁴⁾

00h

R/W

000Ch

000Dh

000Eh

PEDR

Port E⁽³⁾PEDDR

PEOR

Port E Data Register

Port E Data Direction Register

Port E Option Register

00h ⁽⁴⁾

00h

R/W

000Fh

0010h

0011h

PFDR

Port F⁽³⁾PFDDR

PFOR

Port F Data Register

Port F Data Direction Register

Port F Option Register

00h ⁽⁴⁾

00h

R/W

0012h to

0016h

Reserved area (5 bytes)

0017h

0018h

RCCRH

RC

RC oscillator Control Register High

RC oscillator Control Register Low

FFh

03h

R/W

RCCRL

0019h

Reserved area (1 byte)

001Ah to

001Fh

DM⁽⁵⁾

Reserved area (6 bytes)

00020h

EEPROM EECSR

SPIDR

Data EEPROM Control/Status Register

00h

R/W

0021h

0022h

0023h

SPI Data I/O Register

SPI Control Register

SPI Control Status Register

xxh

0xh

00h

R/W

SPI

SPICR

SPICSR

0024h

0025h

0026h

0027h

ISPR0

ISPR1

ISPR2

ISPR3

Interrupt Software Priority Register 0

Interrupt Software Priority Register 1

Interrupt Software Priority Register 2

Interrupt Software Priority Register 3

FFh

R/W

ITC

0028h

00029h

002Ah

002Bh

EICR

External Interrupt Control Register

Flash Control/Status Register

00h

7Fh

R/W

Flash

FCSR

WWDG WDGCR

Watchdog Control Register

SI

SICSR

System Integrity Control/Status Register

000x 000xb R/W

002Ch

002Dh

MCCSR

MCCBCR

Main Clock Control/Status Register

MCC Beep Control Register

00h

R/W

MCC

002Eh

002Fh

AWUCSR

AWUPR

AWU Control/Status Register

AWU Prescaler Register

00h

FFh

R/W

AWU

0030h

WWDG WDGWR

Window Watchdog Control Register

7Fh

R/W

24/246

ST72344xx, ST72345xx

Register and memory map

Table 4.

Address

Hardware register map (continued)

Register

label

Reset

Block

Register name

Remarks⁽²⁾

status⁽¹⁾

0031h

0032h

0033h

0034h

0035h

0036h

0037h

0038h

0039h

003Ah

003Bh

003Ch

003Dh

003Eh

003Fh

TACR2

TACR1

TACSR

TAIC1HR

TAIC1LR

TAOC1HR

TAOC1LR

Timer A Control Register 2

Timer A Control Register 1

Timer A Control/Status Register

Timer A Input Capture 1 High Register

Timer A Input Capture 1 Low Register

Timer A Output Compare 1 High Register

Timer A Output Compare 1 Low Register

Timer A Counter High Register

00h

xxh

80h

00h

FFh

FCh

FFh

FCh

xxh

80h

00h

R/W

Read Only

R/W

TIMER A TACHR

TACLR

Read Only

R/W

Timer A Counter Low Register

TAACHR

TAACLR

TAIC2HR

TAIC2LR

TAOC2HR

TAOC2LR

Timer A Alternate Counter High Register

Timer A Alternate Counter Low Register

Timer A Input Capture 2 High Register

Timer A Input Capture 2 Low Register

Timer A Output Compare 2 High Register

Timer A Output Compare 2 Low Register

R/W

0040h

Reserved area (1 Byte)

0041h

0042h

0043h

0044h

0045h

0046h

0047h

0048h

0049h

004Ah

004Bh

004Ch

004Dh

004Eh

004Fh

TBCR2

TBCR1

TBCSR

TBIC1HR

TBIC1LR

Timer B Control Register 2

Timer B Control Register 1

Timer B Control/Status Register

Timer B Input Capture 1 High Register

Timer B Input Capture 1 Low Register

Timer B Output Compare 1 High Register

Timer B Output Compare 1 Low Register

Timer B Counter High Register

00h

xxh

80h

00h

FFh

FCh

FFh

FCh

xxh

80h

00h

R/W

Read Only

R/W

TBOC1HR

TBOC1LR

TIMER B TBCHR

TBCLR

R/W

Read Only

R/W

Timer B Counter Low Register

TBACHR

TBACLR

TBIC2HR

TBIC2LR

TBOC2HR

TBOC2LR

Timer B Alternate Counter High Register

Timer B Alternate Counter Low Register

Timer B Input Capture 2 High Register

Timer B Input Capture 2 Low Register

Timer B Output Compare 2 High Register

Timer B Output Compare 2 Low Register

R/W

0050h

0051h

0052h

0053h

0054h

0055h

0056h

0057h

SCISR

SCIDR

SCIBRR

SCICR1

SCICR2

SCI Status Register

SCI Data Register

SCI Baud Rate Register

SCI Control Register 1

SCI Control Register 2

Reserved area

SCI Extended Receive Prescaler Register

SCI Extended Transmit Prescaler Register

C0h

xxh

00h

Read Only

R/W

x000 0000b R/W

SCI

00h

--

00h

R/W

SCIERPR

SCIETPR

R/W

0058h

0059h

005Ah

005Bh

005Ch

005Dh

005Eh

I2CCR

I2CSR1

I2CSR2

I2CCCR

I2COAR1

I2COAR2

I2CDR

I²C Control Register

00h

40h

00h

R/W

I²C Status Register 1

I²C Status Register 2

I²C Clock Control Register

I²C Own Address Register 1

I²C Own Address Register2

I²C Data Register

Read Only

R/W

I²C

R/W

005Fh

Reserved area (1 byte)

25/246

Register and memory map

ST72344xx, ST72345xx

Table 4.

Address

Hardware register map (continued)

Register

label

Reset

Block

Register name

Remarks⁽²⁾

status⁽¹⁾

0060h

0061h

0062h

0063h

0064h

0065h

0066h

0067h

0068h

0069h

I2C3SCR1

I2C3SCR2

I2C3SSR

I²C3SNS Control Register 1

I²C3SNS Control Register 2

I²C3SNS Status Register

00h

R/W

Read Only

R/W

I2C3SBCR

I²C3SNS Byte Count Register

I2C3SSAR1 I²C3SNS Slave Address 1 Register

I2C3SCAR1 I²C3SNS Current Address 1 Register

I2C3SSAR2 I²C3SNS Slave Address 2 Register

I2C3SCAR2 I²C3SNS Current Address 2 Register

I2C3SSAR3 I²C3SNS Slave Address 3 Register

I2C3SCAR3 I²C3SNS Current Address 3 Register

I²C3SNS

R/W

0070h

0071h

0072h

ADCCSR

ADCDRH

ADCDRL

A/D Control Status Register

A/D Data Register High

A/D Data Low Register

00h

xxh

R/W

Read Only

ADC

0000 00xxb Read Only

0073h to

007Fh

Reserved area (13 bytes)

1. x = undefined.

2. R/W = read/write.

3. The bits associated with unavailable pins must always keep their reset value.

4. The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the

I/O pins are returned instead of the DR register contents.

5. For a description of the Debug Module registers, see ST7 ICC protocol reference manual.

26/246

ST72344xx, ST72345xx

Flash program memory

4

Flash program memory

4.1

Introduction

The ST7 single voltage extended Flash (XFlash) is a non-volatile memory that can be

electrically erased and programmed either on a byte-by-byte basis or up to 32 bytes in

parallel.

The XFlash devices can be programmed off-board (plugged in a programming tool) or on-

board using In-Circuit Programming or In-Application Programming.

The array matrix organization allows each sector to be erased and reprogrammed without

affecting other sectors.

4.2

4.3

Main features

●

ICP (in-circuit programming)

IAP (in-application programming)

ICT (in-circuit testing) for downloading and executing user application test patterns in

RAM

●

Sector 0 size configurable by option byte

Read-out and write protection

Programming modes

The ST7 can be programmed in three different ways:

●

Insertion in a programming tool. In this mode, Flash sectors 0 and 1, option byte row

and data EEPROM (if present) can be programmed or erased.

●

In-circuit programming. In this mode, Flash sectors 0 and 1, option byte row and data

EEPROM (if present) can be programmed or erased without removing the device from

the application board.

●

In-application programming. In this mode, sector 1 and data EEPROM (if present) can

be programmed or erased without removing the device from the application board and

while the application is running.

27/246

Flash program memory

ST72344xx, ST72345xx

4.3.1

In-circuit programming (ICP)

ICP uses a protocol called ICC (in-circuit communication) which allows an ST7 plugged on a

printed circuit board (PCB) to communicate with an external programming device connected

via cable. ICP is performed in three steps:

Switch the ST7 to ICC mode (in-circuit communications). This is done by driving a specific

signal sequence on the ICCCLK/DATA pins while the RESET pin is pulled low. When the

ST7 enters ICC mode, it fetches a specific reset vector which points to the ST7 System

Memory containing the ICC protocol routine. This routine enables the ST7 to receive bytes

from the ICC interface.

●

Download ICP Driver code in RAM from the ICCDATA pin

●

Execute ICP Driver code in RAM to program the Flash memory

Depending on the ICP Driver code downloaded in RAM, Flash memory programming can

be fully customized (number of bytes to program, program locations, or selection of the

serial communication interface for downloading).

4.3.2

In-application programming (IAP)

This mode uses an IAP Driver program previously programmed in Sector 0 by the user (in

ICP mode).

This mode is fully controlled by user software. This allows it to be adapted to the user

application, (user-defined strategy for entering programming mode, choice of

communications protocol used to fetch the data to be stored etc.)

IAP mode can be used to program any memory areas except Sector 0, which is write/erase

protected to allow recovery in case errors occur during the programming operation.

4.4

ICC interface

ICP needs a minimum of 4 and up to 7 pins to be connected to the programming tool. These

pins are:

●

RESET: device reset

: device power supply ground

V

SS

ICCCLK: ICC output serial clock pin

ICCDATA: ICC input serial data pin

ICCSEL: ICC selection

OSC1: main clock input for external source (not required on devices without

OSC1/OSC2 pins)

●

V

: application board power supply (optional, see Note 3)

DD

Note:

1

2

If the ICCCLK or ICCDATA pins are only used as outputs in the application, no signal

isolation is necessary. As soon as the Programming Tool is plugged to the board, even if an

ICC session is not in progress, the ICCCLK and ICCDATA pins are not available for the

application. If they are used as inputs by the application, isolation such as a serial resistor

has to be implemented in case another device forces the signal. Refer to the Programming

Tool documentation for recommended resistor values.

During the ICP session, the programming tool must control the RESET pin. This can lead to

conflicts between the programming tool and the application reset circuit if it drives more than

5 mA at high level (push pull output or pull-up resistor<1K). A schottky diode can be used to

28/246

ST72344xx, ST72345xx

Flash program memory

isolate the application reset circuit in this case. When using a classical RC network with

R>1K or a reset management IC with open drain output and pull-up resistor>1K, no

additional components are needed. In all cases the user must ensure that no external reset

is generated by the application during the ICC session.

3

4

5

The use of Pin 7 of the ICC connector depends on the Programming Tool architecture. This

pin must be connected when using most ST Programming Tools (it is used to monitor the

application power supply). Please refer to the Programming Tool manual.

Pin 9 has to be connected to the OSC1 pin of the ST7 when the clock is not available in the

application or if the selected clock option is not programmed in the option byte. ST7 devices

with multi-oscillator capability need to have OSC2 grounded in this case.

In “enabled option byte” mode (38-pulse ICC mode), the internal RC oscillator is forced as a

clock source, regardless of the selection in the option byte.

Caution:

During normal operation the ICCCLK pin must be internally or externally pulled- up (external

pull-up of 10 kΩ mandatory in noisy environment) to avoid entering ICC mode unexpectedly

during a reset. In the application, even if the pin is configured as output, any reset will put it

back in input pull-up.

Figure 6.

Typical ICC interface

PROGRAMMING TOOL

ICC CONNECTOR

ICC Cable

ICC CONNECTOR

HE10 CONNECTOR TYPE

(See Note 3)

OPTIONAL

APPLICATION BOARD

(See Note 4)

9

7

5

6

3

1

2

10

8

4

APPLICATION

RESET SOURCE

See Note 2

10kΩ

APPLICATION

POWER SUPPLY

C_L2

C_L1

APPLICATION

I/O

See Note 1

ST7

4.5

Memory protection

There are two different types of memory protection: Read Out Protection and Write/Erase

Protection which can be applied individually.

4.5.1

Readout protection

Readout protection, when selected provides a protection against program memory content

extraction and against write access to Flash memory. Even if no protection can be

considered as totally unbreakable, the feature provides a very high level of protection for a

2

general purpose microcontroller. Both program and data E memory are protected.

29/246

Flash program memory

ST72344xx, ST72345xx

In Flash devices, this protection is removed by reprogramming the option. In this case, both

2

program and data E memory are automatically erased, and the device can be

reprogrammed.

Read-out protection selection depends on the device type:

●

In Flash devices it is enabled and removed through the FMP_R bit in the option byte.

In ROM devices it is enabled by mask option specified in the Option List.

●

4.5.2

Flash write/erase protection

Write/erase protection, when set, makes it impossible to both overwrite and erase program

2

memory. It does not apply to E data. Its purpose is to provide advanced security to

applications and prevent any change being made to the memory content.

Warning: Once set, Write/erase protection can never be removed. A

write-protected Flash device is no longer reprogrammable.

Write/erase protection is enabled through the FMP_W bit in the option byte.

4.6

Register description

4.6.1

Flash control/status register (FCSR)

Reset value: 0000 0000 (00h)

1st RASS Key: 0101 0110 (56h)

2nd RASS Key: 1010 1110 (AEh)

7

0

OPT

LAT

PGM

Read/Write

Note:

This register is reserved for programming using ICP, IAP or other programming methods. It

controls the XFlash programming and erasing operations. For details on XFlash

programming, refer to the ST7 Flash Programming Reference Manual.

When an EPB or another programming tool is used (in socket or ICP mode), the RASS keys

are sent automatically.

30/246

ST72344xx, ST72345xx

Data EEPROM

5

Data EEPROM

5.1

Introduction

The electrically erasable programmable read only memory can be used as a non-volatile

backup for storing data. Using the EEPROM requires a basic access protocol described in

this chapter.

5.2

Main features

●

Up to 32 bytes programmed in the same cycle

EEPROM mono-voltage (charge pump)

Chained erase and programming cycles

Internal control of the global programming cycle duration

Wait mode management

Readout protection

Figure 7.

EEPROM block diagram

HIGH VOLTAGE

PUMP

EECSR

0

E2LAT E2PGM

EEPROM

ROW

ADDRESS

DECODER

4

MEMORY MATRIX

(1 ROW = 32 x 8 BITS)

DECODER

128

DATA

MULTIPLEXER

32 x 8 BITS

4

DATA LATCHES

ADDRESS BUS

DATA BUS

5.3

Memory access

The Data EEPROM memory read/write access modes are controlled by the E2LAT bit of the

EEPROM Control/Status register (EECSR). The flowchart in Figure 8 describes these

different memory access modes.

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Data EEPROM

ST72344xx, ST72345xx

Read operation (E2LAT = 0)

The EEPROM can be read as a normal ROM location when the E2LAT bit of the EECSR

register is cleared.

On this device, Data EEPROM can also be used to execute machine code. Take care not to

write to the Data EEPROM while executing from it. This would result in an unexpected code

being executed.

Write operation (E2LAT = 1)

To access the write mode, the E2LAT bit has to be set by software (the E2PGM bit remains

cleared). When a write access to the EEPROM area occurs, the value is latched inside the

32 data latches according to its address.

When E2PGM bit is set by the software, all the previous bytes written in the data latches (up

to 32) are programmed in the EEPROM cells. The effective high address (row) is

determined by the last EEPROM write sequence. To avoid wrong programming, the user

must take care that all the bytes written between two programming sequences have the

same high address: only the five Least Significant Bits of the address can change.

The programming cycle is fully completed when the E2PGM bit is cleared.

Note:

Care should be taken during the programming cycle. Writing to the same memory location

will over-program the memory (logical AND between the two write access data result)

because the data latches are only cleared at the end of the programming cycle and by the

falling edge of the E2LAT bit.

It is not possible to read the latched data.

This note is illustrated by the Figure 10.

Figure 8.

Data EEPROM programming flowchart

READ MODE

E2LAT = 0

WRITE MODE

E2LAT = 1

E2PGM = 0

WRITE UP TO 32 BYTES

IN EEPROM AREA

(with the same 11 MSB of the address)

READ BYTES

IN EEPROM AREA

START PROGRAMMING CYCLE

E2LAT=1

E2PGM=1 (set by software)

0

1

E2PGM

CLEARED BY HARDWARE

32/246

ST72344xx, ST72345xx

Figure 9.

Data EEPROM

Data EEPROM write operation

⇓ Row / Byte ⇒ 0

1

2

3

... 30 31

Physical address

Row

0

1

00h...1Fh

20h...3Fh

definition

...

N

Nx20h...Nx20h+1Fh

Read operation impossible

Read operation possible

Programming cycle

PHASE 2

Waiting E2PGM and E2LAT to fall

Byte 1 Byte 2

PHASE 1

Byte 32

Writing data latches

E2LAT bit

Set by USER application

Cleared by hardware

E2PGM bit

Note:

If a programming cycle is interrupted (by reset action), the integrity of the data in memory

will not be guaranteed.

5.4

Power saving modes

5.4.1

Wait mode

The data EEPROM can enter Wait mode on execution of the WFI instruction of the

microcontroller or when the microcontroller enters Active Halt mode.The data EEPROM will

immediately enter this mode if there is no programming in progress, otherwise the data

EEPROM will finish the cycle and then enter Wait mode.

5.4.2

5.4.3

Active-halt mode

Refer to Wait mode.

Halt mode

The data EEPROM immediately enters Halt mode if the microcontroller executes the Halt

instruction. Therefore the EEPROM will stop the function in progress, and data may be

corrupted.

5.5

Access error handling

If a read access occurs while E2LAT = 1, then the data bus will not be driven.

If a write access occurs while E2LAT = 0, then the data on the bus will not be latched.

If a programming cycle is interrupted (by reset action), the integrity of the data in memory

will not be guaranteed.

33/246

Data EEPROM

ST72344xx, ST72345xx

5.6

Data EEPROM readout protection

The readout protection is enabled through an option bit (see option byte section).

When this option is selected, the programs and data stored in the EEPROM memory are

protected against read-out (including a rewrite protection). In Flash devices, when this

protection is removed by reprogramming the option byte, the entire Program memory and

EEPROM is first automatically erased.

Note:

Both program memory and data EEPROM are protected using the same option bit.

Figure 10. Data EEPROM programming cycle

READ OPERATION NOT POSSIBLE

READ OPERATION POSSIBLE

INTERNAL

PROGRAMMING

VOLTAGE

ERASE CYCLE

WRITE CYCLE

WRITE OF

DATA

LATCHES

t

PROG

E2LAT

E2PGM

I bit in CC register

1)

All interrupts must be masked

Note 1: refer to Programming of EEPROM data on page 243

34/246

ST72344xx, ST72345xx

Data EEPROM

5.7

Register description

5.7.1

EEPROM control/status register (EECSR)

Reset value: 0000 0000 (00h)

7

0

E2LAT

E2PGM

Read/Write

Bits 7:2 = Reserved, forced by hardware to 0.

Bit 1 = E2LAT Latch Access Transfer

This bit is set by software. It is cleared by hardware at the end of the programming

cycle. It can only be cleared by software if the E2PGM bit is cleared.

0: Read mode

1: Write mode

Bit 0 = E2PGM Programming control and status

This bit is set by software to begin the programming cycle. At the end of the

programming cycle, this bit is cleared by hardware.

0: Programming finished or not yet started

1: Programming cycle is in progress

Note:

If the E2PGM bit is cleared during the programming cycle, the memory data is not

guaranteed

Table 5.

Data EEPROM register map and reset values

Address Register

7

6

5

4

3

2

1

0

(Hex.)

label

EECSR

Reset value

E2LAT E2PGM

0020h

0

35/246

Central processing unit

ST72344xx, ST72345xx

6

Central processing unit

6.1

Introduction

This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-

bit data manipulation.

6.2

Main features

●

Enable executing 63 basic instructions

Fast 8-bit by 8-bit multiply

17 main addressing modes (with indirect addressing mode)

Two 8-bit index registers

16-bit stack pointer

Low power Halt and Wait modes

Priority maskable hardware interrupts

Non-maskable software/hardware interrupts

6.3

CPU registers

The six CPU registers shown in Figure 11 are not present in the memory mapping and are

accessed by specific instructions.

Accumulator (A)

The Accumulator is an 8-bit general purpose register used to hold operands and the results

of the arithmetic and logic calculations and to manipulate data.

Index Registers (X and Y)

These 8-bit registers are used to create effective addresses or as temporary storage areas

for data manipulation. (The Cross-Assembler generates a precede instruction (PRE) to

indicate that the following instruction refers to the Y register.)

The Y register is not affected by the interrupt automatic procedures.

Program Counter (PC)

The program counter is a 16-bit register containing the address of the next instruction to be

executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is

the LSB) and PCH (Program Counter High which is the MSB).

36/246

ST72344xx, ST72345xx

Figure 11. CPU registers

Central processing unit

7

0

ACCUMULATOR

RESET VALUE = XXh

7

X INDEX REGISTER

Y INDEX REGISTER

RESET VALUE = XXh

7

RESET VALUE = XXh

PCL

PCH

7

8

15

0

PROGRAM COUNTER

RESET VALUE = RESET VECTOR @ FFFEh-FFFFh

7

1

0

1

I1 H I0 N

Z

X

C

X

CONDITION CODE REGISTER

STACK POINTER

RESET VALUE =

8

1

1 X 1 X

15

7

0

RESET VALUE = STACK HIGHER ADDRESS

X = Undefined Value

6.3.1

Condition code register (CC)

Reset value: 111x1xxx

7

0

1

I1

H

I0

N

Z

C

Read/Write

The 8-bit Condition Code register contains the interrupt masks and four flags representative

of the result of the instruction just executed. This register can also be handled by the PUSH

and POP instructions.

These bits can be individually tested and/or controlled by specific instructions.

Arithmetic management bits

Bit 4 = H Half carry.

This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during

an ADD or ADC instructions. It is reset by hardware during the same instructions.

0: No half carry has occurred.

1: A half carry has occurred.

This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD

arithmetic subroutines.

37/246

Central processing unit

Bit 2 = N Negative.

ST72344xx, ST72345xx

This bit is set and cleared by hardware. It is representative of the result sign of the last

th

arithmetic, logical or data manipulation. It’s a copy of the result 7 bit.

0: The result of the last operation is positive or null.

1: The result of the last operation is negative

(that is, the most significant bit is a logic 1).

This bit is accessed by the JRMI and JRPL instructions.

Bit 1 = Z Zero.

This bit is set and cleared by hardware. This bit indicates that the result of the last

arithmetic, logical or data manipulation is zero.

0: The result of the last operation is different from zero.

1: The result of the last operation is zero.

This bit is accessed by the JREQ and JRNE test instructions.

Bit 0 = C Carry/borrow.

This bit is set and cleared by hardware and software. It indicates an overflow or an

underflow has occurred during the last arithmetic operation.

0: No overflow or underflow has occurred.

1: An overflow or underflow has occurred.

This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC

instructions. It is also affected by the “bit test and branch”, shift and rotate instructions.

Interrupt management bits

Bits 5,3 = I1, I0 Interrupt

The combination of the I1 and I0 bits gives the current interrupt software priority.

Table 6.

Priority

Interrupt software priority

I1

I0

Level 0 (main)

Level 1

1

0

1

0

1

0

1

Level 2

Level 3 (= interrupt disable)

These two bits are set/cleared by hardware when entering in interrupt. The loaded value is

given by the corresponding bits in the interrupt software priority registers (IxSPR). They can

be also set/cleared by software with the RIM, SIM, IRET, HALT, WFI and PUSH/POP

instructions.

See the interrupt management chapter for more details.

38/246

ST72344xx, ST72345xx

Central processing unit

6.3.2

Stack pointer (SP)

Reset value: 01 FFh

15

8

0

1

Read/Write

7

0

SP7

SP6

SP5

SP4

SP3

SP2

SP1

SP0

Read/Write

The Stack pointer is a 16-bit register which is always pointing to the next free location in the

stack. It is then decremented after data has been pushed onto the stack and incremented

before data is popped from the stack (see Figure 12).

Since the stack is 256 bytes deep, the 8 most significant bits are forced by hardware.

Following an MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack pointer

contains its reset value (the SP7 to SP0 bits are set) which is the stack higher address.

The least significant byte of the Stack pointer (called S) can be directly accessed by a LD

instruction.

Note:

When the lower limit is exceeded, the Stack pointer wraps around to the stack upper limit,

without indicating the stack overflow. The previously stored information is then overwritten

and therefore lost. The stack also wraps in case of an underflow.

The stack is used to save the return address during a subroutine call and the CPU context

during an interrupt. The user may also directly manipulate the stack by means of the PUSH

and POP instructions. In the case of an interrupt, the PCL is stored at the first location

pointed to by the SP. Then the other registers are stored in the next locations as shown in

Figure 12.

●

When an interrupt is received, the SP is decremented and the context is pushed on the

stack.

●

On return from interrupt, the SP is incremented and the context is popped from the

stack.

A subroutine call occupies two locations and an interrupt five locations in the stack area.

39/246

Central processing unit

Figure 12. Stack manipulation example

ST72344xx, ST72345xx

CALL

Subroutine

RET

or RSP

PUSH Y

POP Y

IRET

Interrupt

Event

@ 0100h

SP

Y

CC

A

CC

A

CC

A

X

PCH

PCL

PCH

PCL

PCH

PCL

PCH

PCL

PCH

PCL

PCH

PCL

SP

PCH

PCL

PCH

PCL

SP

@ 01FFh

Stack Higher Address = 01FFh

0100h

Stack Lower Address =

40/246

ST72344xx, ST72345xx

Supply, reset and clock management

7

Supply, reset and clock management

The device includes a range of utility features for securing the application in critical

situations (for example in case of a power brown-out), and reducing the number of external

components.

7.1

Main features

●

Clock management

–

1 MHz high-accuracy internal RC oscillator (enabled by option byte)

1 to 16 MHz External crystal/ceramic resonator (enabled by option byte)

External Clock Input (enabled by option byte)

PLL for multiplying the frequency by 8 or 4 (enabled by option byte)

●

Reset sequence manager (RSM)

System integrity management (SI)

–

Main supply low voltage detection (LVD) with reset generation (enabled by option

byte)

–

Auxiliary voltage detector (AVD) with interrupt capability for monitoring the main

supply (enabled by option byte)

Figure 13. Clock, reset and supply block diagram

RCCRH/RCCRL Register

MAIN CLOCK

CONTROLLER

f

CPU

CR9 CR8 CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0

WITH REAL-TIME

CLOCK(MCC/RTC)

Tunable

External Clock (0.5-8 MHz)

RC Oscillator

RC Clock (1 MHz)

1 MHz

f

OSC2

8 MHz

PLL 1 MHz --> 8 MHz

/2

DIVIDER

/2

4 MHz

PLL 1 MHz --> 4 MHz

DIVIDER*

PLL Clock 8/4 MHz

OSC Option bit

PLLx4x8

Option bit

DIV2EN

OSC, PLLOFF

OSCRANGE[2:0]

Option bits

Option bit*

OSC

1-16 MHz

OSC1

OSC2

Crystal OSC (0.5-8 MHz)

/2

DIVIDER

*not available if PLLx4 is enabled

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ST72344xx, ST72345xx

7.2

Phase locked loop

The PLL can be used to multiply a 1 MHz frequency from the RC oscillator or the external

clock by 4 or 8 to obtain f of 4 or 8 MHz. The PLL is enabled and the multiplication factor

OSC

of 4 or 8 is selected by 3 option bits. Refer to Table 7 for the PLL configuration depending on

the required frequency and the application voltage. Refer to Section 15.1 for the option byte

description.

Table 7.

PLL configurations

Target ratio

V_DD

PLL ratio

DIV2

x4⁽¹⁾

x4

2.7 V - 3.65 V

x4

x8

OFF

ON

3.3 V - 5.5 V

x8

OFF

1. For a target ratio of x4 between 3.3 V - 3.65 V, this is the recommended configuration.

Figure 14. PLL output frequency timing diagram

LOCKED bit set

4/8 x

input

freq.

t_STAB

t_LOCK

t_STARTUP

t

When the PLL is started, after reset or wakeup from Halt mode or AWUFH mode, it outputs

the clock after a delay of t

.

STARTUP

When the PLL output signal reaches the operating frequency, the LOCKED bit in the

SICSCR register is set. Full PLL accuracy (ACC ) is reached after a stabilization time of

PLL

t

(see Figure 14).

STAB

Refer to Section 7.6.5 on page 51 for a description of the LOCKED bit in the SICSR register.

Caution:

The PLL is not recommended for applications where timing accuracy is required.

When the RC oscillator and the PLL are enabled, it is recommended to calibrate this clock

through the RCCRH and RCCRL registers.

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ST72344xx, ST72345xx

Supply, reset and clock management

7.3

Multioscillator (MO)

The main clock of the ST7 can be generated by three different source types coming from the

multioscillator block:

●

an external source

4 crystal or ceramic resonator oscillators

an internal high-accuracy RC oscillator

Each oscillator is optimized for a given frequency range in terms of consumption and is

selectable through the option byte. The associated hardware configurations are shown in

Table 8. Refer to the electrical characteristics section for more details.

Caution:

The OSC1 and/or OSC2 pins must not be left unconnected. For the purposes of Failure

Mode and Effect Analysis, it should be noted that if the OSC1 and/or OSC2 pins are left

unconnected, the ST7 main oscillator may start and, in this configuration, could generate an

f

clock frequency in excess of the allowed maximum (>16 MHz.), putting the ST7 in an

OSC

unsafe/undefined state. The product behavior must therefore be considered undefined when

the OSC pins are left unconnected.

7.3.1

7.3.2

External clock source

In this external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle

has to drive the OSC1 pin while the OSC2 pin is tied to ground.

Crystal/ceramic oscillators

This family of oscillators has the advantage of producing a very accurate rate on the main

clock of the ST7. The selection within a list of 4 oscillators with different frequency ranges

has to be done by option byte in order to reduce consumption (refer to Section 15.1 on page

231 for more details on the frequency ranges). In this mode of the multi-oscillator, the

resonator and the load capacitors have to be placed as close as possible to the oscillator

pins in order to minimize output distortion and startup stabilization time. The loading

capacitance values must be adjusted according to the selected oscillator.

These oscillators are not stopped during the reset phase to avoid losing time in the oscillator

startup phase.

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Supply, reset and clock management

ST72344xx, ST72345xx

Table 8.

ST7 clock sources

Hardware configuration

ST7

OSC1

OSC2

EXTERNAL

SOURCE

ST7

OSC1

OSC2

C

L2

L1

LOAD

CAPACITORS

ST7

OSC1

OSC2

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ST72344xx, ST72345xx

Supply, reset and clock management

7.3.3

Internal RC oscillator

The device contains a high-precision internal RC oscillator. It must be calibrated to obtain

the frequency required in the application. This is done by software writing a calibration value

in the RCCRH and RCCRL Registers.

Whenever the microcontroller is reset, the RCCR returns to its default value (FF 03h), i.e.

each time the device is reset, the calibration value must be loaded in the RCCRH and

RCCRL registers. Predefined calibration values are stored in XFlash for 3 and 5V V

supply voltages at 25 °C, as shown in the following table:

DD

Table 9.

Calibration values

Conditions

_DD= 5 V

RCCR

Address

V

RCCR0

T_A= 25 °C

BEE0, BEE1

f_RC= 1 MHz

V_DD= 3 V

RCCR1

T_A= 25 °C

BEE4, BEE5

f_RC= 1 MHz

Note:

To improve clock stability, it is recommended to place a decoupling capacitor between the

and V pins.

V

DD

SS

These two 10-bit values are systematically programmed by ST.

RCCR0 and RCCR1 calibration values will be erased if the read-out protection bit is reset

after it has been set. See Memory protection on page 29.

Caution:

If the voltage or temperature conditions change in the application, the frequency may need

to be recalibrated.

Refer to application note AN1324 for information on how to calibrate the RC frequency using

an external reference signal.

7.4

Register description

7.4.1

RC control register (RCCRH)

Reset value: 1111 1111 (FFh)

7

0

CR9

CR8

CR7

CR6

Read/Write

Bits 7:0 = CR[9:2] RC oscillator frequency adjustment bits

CR5

CR4

CR3

CR2

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ST72344xx, ST72345xx

7.4.2

RC control register (RCCRL)

Reset value: 0000 0011 (03h)

7

0

CR1

CR0

Read/Write

Bits 7:2 = Reserved, must be kept cleared.

Bits 1:0 = CR[1:0] RC Oscillator Frequency Adjustment Bits

This 10-bit value must be written immediately after reset to adjust the RC oscillator

frequency in order to obtain the specified accuracy. The application can store the

correct value for each voltage range in EEPROM and write it to this register at startup.

0000h = maximum available frequency

03FFh = lowest available frequency

Note:

To tune the oscillator, write a series of different values in the register until the correct

frequency is reached. The fastest method is to use a dichotomy starting with 200h.

7.5

Reset sequence manager (RSM)

7.5.1

Introduction

The reset sequence manager includes three reset sources as shown in Figure 16:

●

External RESET source pulse

Internal LVD reset (low voltage detection)

Internal watchdog reset

Note:

A reset can also be triggered following the detection of an illegal opcode or prebyte code.

Refer to Section 12.2.1: Illegal opcode reset on page 195 for further details.

These sources act on the RESET pin and it is always kept low during the delay phase.

The reset service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory

map.

The basic reset sequence consists of 3 phases as shown in Figure 15:

●

Active phase depending on the reset source

256 or 4096 CPU clock cycle delay (selected by option byte)

reset vector fetch

Caution:

When the ST7 is unprogrammed or fully erased, the Flash is blank and the reset vector is

not programmed. For this reason, it is recommended to keep the RESET pin in low state

until programming mode is entered, in order to avoid unwanted behavior.

The 256 or 4096 CPU clock cycle delay allows the oscillator to stabilise and ensures that

recovery has taken place from the Reset state. The shorter or longer clock cycle delay

should be selected by option byte to correspond to the stabilization time of the external

oscillator used in the application (see Section 15.1 on page 231).

The reset vector fetch phase duration is 2 clock cycles.

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ST72344xx, ST72345xx

Figure 15. reset sequence phases

Supply, reset and clock management

RESET

Internal Reset

256 or 4096 clock cycles

Fetch

vector

Active phase

7.5.2

Asynchronous external RESET pin

The RESET pin is both an input and an open-drain output with integrated R weak pull-up

ON

resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It

can be pulled low by external circuitry to reset the device. See Section 13 on page 198 for

more details.

A reset signal originating from an external source must have a duration of at least t

h(RSTL)in

in order to be recognized (see Figure 17). This detection is asynchronous and therefore the

MCU can enter reset state even in Halt mode.

Figure 16. Reset block diagram

V_DD

R_ON

INTERNAL

RESET

Filter

RESET

WATCHDOG RESET

ILLEGAL OPCODE RESET

LVD RESET

PULSE

GENERATOR

(1)

1. See “Illegal opcode reset” on page 198.for more details on illegal opcode reset conditions.

The RESET pin is an asynchronous signal which plays a major role in EMS performance. In

a noisy environment, it is recommended to follow the guidelines mentioned in the electrical

characteristics section.

If the external RESET pulse is shorter than t

(see short ext. Reset in Figure 17),

w(RSTL)out

the signal on the RESET pin may be stretched. Otherwise the delay will not be applied (see

long ext. Reset in Figure 17). Starting from the external RESET pulse recognition, the

device RESET pin acts as an output that is pulled low during at least t

.

w(RSTL)out

7.5.3

External power-on reset

If the LVD is disabled by option byte, to start up the microcontroller correctly, the user must

ensure by means of an external reset circuit that the reset signal is held low until V is over

DD

the minimum level specified for the selected f

frequency (see Operating conditions on

OSC

page 201).

A proper reset signal for a slow rising V supply can generally be provided by an external

DD

RC network connected to the RESET pin.

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ST72344xx, ST72345xx

7.5.4

Internal low-voltage detector (LVD) reset

Two different reset sequences caused by the internal LVD circuitry can be distinguished:

●

Power-on reset

●

Voltage-drop reset

The device RESET pin acts as an output that is pulled low when V <V (rising edge) or

DD

IT+

V

<V (falling edge) as shown in Figure 17.

DD

IT-

The LVD filters spikes on V larger than t

to avoid parasitic resets.

g(VDD)

DD

Note:

It is recommended to make sure that the V supply voltage rises monotonously when the

DD

device is exiting from Reset, to ensure the application functions properly.

7.5.5

Internal watchdog reset

The reset sequence generated by a internal Watchdog counter overflow is shown in

Figure 17.

Starting from the Watchdog counter underflow, the device RESET pin acts as an output that

is pulled low during at least t

.

w(RSTL)out

Figure 17. Reset sequences

V

DD

V_IT+(LVD)

V_IT-(LVD)

LVD

RESET

SHORT EXT.

RESET

LONG EXT.

RESET

WATCHDOG

RESET

Run

ACTIVE

PHASE

ACTIVE

PHASE

ACTIVE

PHASE

ACTIVE PHASE

t

w(RSTL)out

t

w(RSTL)out

t

h(RSTL)in

DELAY

EXTERNAL

RESET

SOURCE

RESET PIN

WATCHDOG

RESET

WATCHDOG UNDERFLOW

INTERNAL RESET (256 or 4096 T_CPU

)

VECTOR FETCH

7.6

System integrity management (SI)

The system integrity management block contains the low-voltage detector (LVD) and

auxiliary-voltage detector (AVD) functions. It is managed by the SICSR register.

Note:

A reset can also be triggered following the detection of an illegal opcode or prebyte code.

Refer to Illegal opcode reset on page 195 for further details.

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ST72344xx, ST72345xx

Supply, reset and clock management

7.6.1

Low-voltage detector (LVD)

The low-voltage detector function (LVD) generates a static reset when the V supply

DD

voltage is below a V reference value. This means that it secures the power-up as well as

IT-

the power-down keeping the ST7 in reset.

The V reference value for a voltage drop is lower than the V reference value for power-

IT-

IT+

on in order to avoid a parasitic reset when the MCU starts running and sinks current on the

supply (hysteresis).

The LVD Reset circuitry generates a reset when V is below:

DD

●

V

when V is rising

DD

IT+

IT-

●

when V is falling

DD

The LVD function is illustrated in Figure 18.

The LVD is an optional function which can be selected by option byte.

LVD threshold configuration: the voltage threshold can be configured by option byte to be

Note:

low, medium or high. The configuration should be chosen depending on the f

and V

OSC

DD

parameters in the application. When correctly configured, the LVD ensures safe power-on

and power-off conditions for the microcontroller without using any external components.

To determine which LVD thresholds to use:

●

Define the minimum operating voltage for the application V

APP(min)

●

Refer to the Electrical Characteristics section to get the minimum operating voltage for

the MCU at the application frequency V

.

DD(min)

●

Select the LVD threshold that ensures that the internal reset is released at V

APP(min)

and activated at V

DD(MCUmin)

During a low-voltage detector reset, the RESET pin is held low, thus permitting the MCU to

reset other devices.

Figure 18. Low voltage detector vs. reset

V_DD

V_hys

V_IT+(LVD)

V_IT-((LVD)

RESET

7.6.2

Auxiliary-voltage detector (AVD)

The AVD is used to provide the application with an early warning of a drop in voltage. If

enabled, an interrupt can be generated allowing software to shut down safely before the LVD

resets the microcontroller. See Figure 19.

Note:

The AVD function is active only if the LVD is enabled through the option byte (see 15.1:

Option bytes on page 231). The activation level of the AVD is fixed at around 0.5 mV above

the selected LVD threshold.

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Supply, reset and clock management

In the case of a drop in voltage below V

ST72344xx, ST72345xx

, the AVDF flag is set and an interrupt request

IT-(AVD)

is issued.

If V rises above the V

threshold voltage the AVDF bit is cleared automatically by

IT+(AVD)

DD

hardware. No interrupt is generated, and therefore software should poll the AVDF bit to

detect when the voltage has risen, and resume normal processing.

Figure 19. Using the AVD to monitor V

V_DD

DD

Early warning interrupt

(Power has dropped, MCU not

not yet in reset)

V_hys

V_IT+(AVD)

V_IT-(AVD)

V_IT-(LVD)

1

0

AVDF bit

0

RESET VALUE

1

AVD INTERRUPT

REQUEST

IF AVDIE bit = 1

INTERRUPT PROCESS

LVD RESET

7.6.3

7.6.4

Low-power modes

Table 10. Low-power mode description

Mode

Description

Wait

Halt

No effect on SI. AVD interrupts cause the device to exit from Wait mode.

The SICSR register is frozen.

Interrupts

The AVD interrupt event generates an interrupt if the corresponding AVDIE Bit is set and the

interrupt mask in the CC register is reset (RIM instruction).

Table 11. Interrupt event

Enable

Control bit

Exit from

Wait

Exit from

Halt

Interrupt event

Event flag

AVD event

AVDF

AVDIE

Yes

No

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ST72344xx, ST72345xx

Supply, reset and clock management

7.6.5

Register description

System integrity (SI) control/status register (SICSR)

Reset value: 000x 000x (xxh)

7

0

PDVDIE

AVDF

LVDRF

LOCKED

0

WDGRF

Read/Write

Bit 7 = Reserved, must be kept cleared.

Bit 6 = AVDIE Voltage detector interrupt enable

This bit is set and cleared by software. It enables an interrupt to be generated when the

AVDF flag goes from 0 to 1. The pending interrupt information is automatically cleared

when software enters the AVD interrupt routine.

0: PDVD interrupt disabled

1: PDVD interrupt enabled

Bit 5 = AVDF Voltage Detector flag

This read-only bit is set and cleared by hardware. If the AVDIE bit is set, an interrupt

request is generated when the AVDF bit goes from 0 to 1. Refer to Figure 19 and to

Section 7.6.2 for additional details.

0: V over V

threshold

IT-(AVD)

DD

IT+(AVD)

1: V under V

DD

Bit 4 = LVDRF LVD reset flag

This bit indicates that the last Reset was generated by the LVD block. It is set by

hardware (LVD reset) and cleared by software (writing zero). See WDGRF flag

description for more details. When the LVD is disabled by OPTION BYTE, the LVDRF

bit value is undefined.

Bit 3 = LOCKED PLL Locked Flag

This bit is set and cleared by hardware. It is set automatically when the PLL reaches its

operating frequency.

0: PLL not locked

1: PLL locked

Bits 2:1 = Reserved, must be kept cleared.

Bit 0 = WDGRF Watchdog reset flag

This bit indicates that the last Reset was generated by the Watchdog peripheral. It is

set by hardware (watchdog reset) and cleared by software (writing zero) or an LVD

Reset (to ensure a stable cleared state of the WDGRF flag when CPU starts).

Combined with the LVDRF flag information, the flag description is given by the following

table.

Table 12. LVDRF and WDGRF description

Reset sources

LVDRF

WDGRF

External RESET pin

Watchdog

0

1

0

1

LVD

X

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Supply, reset and clock management

Application notes

ST72344xx, ST72345xx

The LVDRF flag is not cleared when another reset type occurs (external or watchdog), the

LVDRF flag remains set to keep trace of the original failure.

In this case, a watchdog reset can be detected by software while an external reset can not.

Caution:

When the LVD is not activated with the associated option byte, the WDGRF flag can not be

used in the application.

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ST72344xx, ST72345xx

Interrupts

8

Interrupts

8.1

Introduction

The ST7 enhanced interrupt management provides the following features:

●

Hardware interrupts

Software interrupt (TRAP)

Nested or concurrent interrupt management with flexible interrupt priority and level

management:

–

Up to 4 software programmable nesting levels

Up to 16 interrupt vectors fixed by hardware

2 non maskable events: reset, TRAP

This interrupt management is based on:

●

Bit 5 and bit 3 of the CPU CC register (I1:0),

Interrupt software priority registers (ISPRx),

Fixed interrupt vector addresses located at the high addresses of the memory map

(FFE0h to FFFFh) sorted by hardware priority order.

This enhanced interrupt controller guarantees full upward compatibility with the standard

(not nested) ST7 interrupt controller.

8.2

Masking and processing flow

The interrupt masking is managed by the I1 and I0 bits of the CC register and the ISPRx

registers which give the interrupt software priority level of each interrupt vector (see

Table 6). The processing flow is shown in Figure 20.

When an interrupt request has to be serviced:

●

Normal processing is suspended at the end of the current instruction execution.

The PC, X, A and CC registers are saved onto the stack.

I1 and I0 bits of CC register are set according to the corresponding values in the ISPRx

registers of the serviced interrupt vector.

●

The PC is then loaded with the interrupt vector of the interrupt to service and the first

instruction of the interrupt service routine is fetched (refer to “Interrupt Mapping” table

for vector addresses).

The interrupt service routine should end with the IRET instruction which causes the

contents of the saved registers to be recovered from the stack.

Note:

As a consequence of the IRET instruction, the I1 and I0 bits will be restored from the stack

and the program in the previous level will resume.

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Interrupts

ST72344xx, ST72345xx

Table 13. Interrupt software priority levels

Interrupt software priority

Level

I1

I0

1

0

1

0

1

0

1

Level 0 (main)

Level 1

Low

Level 2

High

Level 3 (= interrupt disable)

Figure 20. Interrupt processing flowchart

PENDING

INTERRUPT

Y

RESET

TRAP

N

Interrupt has the same or a

lower software priority

than current one

N

I1:0

FETCH NEXT

INSTRUCTION

THE INTERRUPT

STAYS PENDING

Y

“IRET”

N

RESTORE PC, X, A, CC

FROM STACK

EXECUTE

INSTRUCTION

STACK PC, X, A, CC

LOAD I1:0 FROM INTERRUPT SW REG.

LOAD PC FROM INTERRUPT VECTOR

Servicing pending interrupts

As several interrupts can be pending at the same time, the interrupt to be taken into account

is determined by the following two-step process:

●

the highest software priority interrupt is serviced,

●

if several interrupts have the same software priority then the interrupt with the highest

hardware priority is serviced first.

Figure 21 describes this decision process.

Figure 21. Priority decision process

PENDING

INTERRUPTS

Different

Same

SOFTWARE

PRIORITY

HIGHEST SOFTWARE

PRIORITY SERVICED

HIGHEST HARDWARE

PRIORITY SERVICED

54/246

ST72344xx, ST72345xx

Interrupts

When an interrupt request is not serviced immediately, it is latched and then processed

when its software priority combined with the hardware priority becomes the highest one.

Note:

1

2

The hardware priority is exclusive while the software one is not. This allows the previous

process to succeed with only one interrupt.

TLI, reset and TRAP can be considered as having the highest software priority in the

decision process.

Different interrupt vector sources

Two interrupt source types are managed by the ST7 interrupt controller: the non-maskable

type (reset, TRAP) and the maskable type (external or from internal peripherals).

Non-maskable sources

These sources are processed regardless of the state of the I1 and I0 bits of the CC register

(see Figure 20). After stacking the PC, X, A and CC registers (except for reset), the

corresponding vector is loaded in the PC register and the I1 and I0 bits of the CC are set to

disable interrupts (level 3). These sources allow the processor to exit Halt mode.

●

TRAP (non-maskable software interrupt)

This software interrupt is serviced when the TRAP instruction is executed. It will be serviced

according to the flowchart in Figure 20.

●

reset

The reset source has the highest priority in the ST7. This means that the first current routine

has the highest software priority (level 3) and the highest hardware priority.

See the reset chapter for more details.

Maskable sources

Maskable interrupt vector sources can be serviced if the corresponding interrupt is enabled

and if its own interrupt software priority (in ISPRx registers) is higher than the one currently

being serviced (I1 and I0 in CC register). If any of these two conditions is false, the interrupt

is latched and thus remains pending.

●

External interrupts

External interrupts allow the processor to exit from Halt low-power mode. External

interrupt sensitivity is software selectable through the External Interrupt Control register

(EICR).

External interrupt triggered on edge will be latched and the interrupt request

automatically cleared upon entering the interrupt service routine.

If several input pins of a group connected to the same interrupt line are selected

simultaneously, these will be logically ORed.

●

Peripheral interrupts

Usually the peripheral interrupts cause the MCU to exit from Halt mode except those

mentioned in the “Interrupt Mapping” table. A peripheral interrupt occurs when a

specific flag is set in the peripheral status registers and if the corresponding enable bit

is set in the peripheral control register.

The general sequence for clearing an interrupt is based on an access to the status

register followed by a read or write to an associated register.

Note:

The clearing sequence resets the internal latch. A pending interrupt (i.e. waiting for being

serviced) will therefore be lost if the clear sequence is executed.

55/246

Interrupts

ST72344xx, ST72345xx

8.3

Interrupts and low-power modes

All interrupts allow the processor to exit the Wait low-power mode. On the contrary, only

external and other specified interrupts allow the processor to exit from the Halt modes (see

column “Exit from Halt” in “Interrupt Mapping” table). When several pending interrupts are

present while exiting Halt mode, the first one serviced can only be an interrupt with exit from

Halt mode capability and it is selected through the same decision process shown in

Figure 21.

Note:

If an interrupt, that is not able to Exit from Halt mode, is pending with the highest priority

when exiting Halt mode, this interrupt is serviced after the first one serviced.

8.4

Concurrent & nested management

The following Figure 22 and Figure 23 show two different interrupt management modes. The

first is called concurrent mode and does not allow an interrupt to be interrupted, unlike the

nested mode in Figure 23. The interrupt hardware priority is given in this order from the

lowest to the highest: MAIN, IT4, IT3, IT2, IT1, IT0, TLI. The software priority is given for

each interrupt.

Warning: A stack overflow may occur without notifying the software of

the failure.

Figure 22. Concurrent interrupt management

SOFTWARE

PRIORITY

LEVEL

I1

I0

TRAP

3

1 1

IT0

3

IT1

3

IT2

3

IT3

3

RIM

IT4

3

MAIN

3/0

11 / 10

10

56/246

ST72344xx, ST72345xx

Figure 23. Nested interrupt management

Interrupts

SOFTWARE

PRIORITY

LEVEL

I1

I0

TRAP

3

1 1

IT0

3

1 1

0 0

0 1

1 1

IT1

2

IT2

1

IT3

3

RIM

IT4

3

MAIN

3/0

11 / 10

10

8.5

Interrupt register description

8.5.1

CPU CC register interrupt bits

Reset value: 111x 1010 (xAh)

7

0

1

I1

H

I0

Read/Write

Bits 5, 3 = I1, I0 Software interrupt priority

N

Z

C

These two bits indicate the current interrupt software priority.

Table 14. Interrupt software priority

Priority

Level

I1

I0

Level 0 (main)

Level 1

1

0

1

0

1

0

1

Low

Level 2

High

Level 3 (= interrupt disable⁽¹⁾

)

1. TRAP and reset events can interrupt a level 3 program.

These two bits are set/cleared by hardware when entering in interrupt. The loaded value is

given by the corresponding bits in the interrupt software priority registers (ISPRx).

They can be also set/cleared by software with the RIM, SIM, HALT, WFI, IRET and

PUSH/POP instructions (see “Interrupt Dedicated Instruction Set” table).

57/246

Interrupts

ST72344xx, ST72345xx

8.5.2

Interrupt software priority registers (ISPRX)

Reset value: 1111 1111 (FFh)

7

0

ISPR0

ISPR1

ISPR2

ISPR3

I1_3

I1_7

I1_11

1

I0_3

I0_7

I0_11

1

I1_2

I1_6

I1_10

1

I0_2

I0_6

I0_10

1

I1_1

I1_5

I0_1

I0_5

I1_0

I1_4

I0_0

I0_4

I1_9

I0_9

I1_8

I0_8

I1_13

I0_13

I1_12

I0_12

Read/Write (bits 7:4 of ISPR3 are read only)

These four registers contain the interrupt software priority of each interrupt vector.

Each interrupt vector (except reset and TRAP) has corresponding bits in these

●

registers where its own software priority is stored. This correspondence is shown in the

following table.

Table 15. Interrupt vector addresses

Vector address

ISPRx bits

FFFBh-FFFAh

FFF9h-FFF8h

...

I1_0 and I0_0 bits*

I1_1 and I0_1 bits

...

FFE1h-FFE0h

I1_13 and I0_13 bits

●

Each I1_x and I0_x bit value in the ISPRx registers has the same meaning as the I1

and I0 bits in the CC register.

Level 0 can not be written (I1_x=1, I0_x=0). In this case, the previously stored value is

kept. (example: previous = CFh, write = 64h, result = 44h)

The reset, and TRAP vectors have no software priorities. When one is serviced, the I1 and

I0 bits of the CC register are both set.

Caution:

If the I1_x and I0_x bits are modified while the interrupt x is executed the following behavior

has to be considered: If the interrupt x is still pending (new interrupt or flag not cleared) and

the new software priority is higher than the previous one, the interrupt x is re-entered.

Otherwise, the software priority stays unchanged up to the next interrupt request (after the

IRET of the interrupt x).

Table 16. Dedicated interrupt instruction set

Instruction

HALT

New description

Function/example

I1

H

I0

N

Z

C

Entering Halt mode

Interrupt routine return

Jump if I1:0=11 (level 3)

Jump if I1:0<>11

1

0

IRET

Pop CC, A, X, PC

I1:0=11 ?

I1

H

I0

N

Z

C

JRM

JRNM

POP CC

RIM

I1:0<>11 ?

Pop CC from the stack

Mem => CC

I1

H

I0

N

Z

C

Enable interrupt (level 0 set) Load 10 in I1:0 of CC

1

0

58/246

ST72344xx, ST72345xx

Interrupts

Table 16. Dedicated interrupt instruction set (continued)

Instruction New description Function/example

SIM Disable interrupt (level 3 set) Load 11 in I1:0 of CC

I1

H

I0

N

Z

C

1

TRAP

WFI

Software trap

Software NMI

1

0

Wait for interrupt

Note:

During the execution of an interrupt routine, the HALT, POPCC, RIM, SIM and WFI

instructions change the current software priority up to the next IRET instruction or one of the

previously mentioned instructions.

Table 17. Interrupt mapping

Source

block

Register Priority Exit from

Address

vector

No.

Description

label

order

Halt⁽¹⁾

Reset

yes

no

FFFEh-FFFFh

FFFCh-FFFDh

FFFAh-FFFBh

FFF8h-FFF9h

FFF6h-FFF7h

FFF4h-FFF5h

FFF2h-FFF3h

FFF0h-FFF1h

FFEEh-FFEFh

N/A

TRAP/ICD Software or ICD interrupt

AWU Auto wakeup interrupt

MCC/RTC RTC time base interrupt

0

1

2

3

4

5

6

AWUCSR

MCCSR

N/A

yes

no

Highest

priority

ei0

ei1

ei2

ei3

External interrupt Port PA3, PE1

External interrupt Port PF2:0

External interrupt Port PB3:0

External interrupt Port PB4

N/A

I2C3SNS I2C3SNS address 3 interrupt

I2C3SSR

I2C3SNS address 1 & 2

7

I2C3SNS

interrupt

no

FFECh-FFEDh

8

9

SPI

SPI peripheral interrupts

SPISR

TASR

yes⁽²⁾

no

FFEAh-FFEBh

FFE8h-FFE9h

FFE6h-FFE7h

FFE4h-FFE5h

TIMER A TIMER A peripheral interrupts

Lowest

priority

10 TIMER B TIMER B peripheral interrupts

TBSR

SCISR

no

11

12

13

SCI

AVD

I²C

SCI peripheral interrupt

no

Auxiliary-voltage-detector

interrupt

SICSR

no

FFE2h-FFE3h

FFE0h-FFE1h

I²C peripheral interrupt

I2CSRx

1. Valid for Halt and Active-halt modes except for the MCC/RTC interrupt source which exits from Active-halt

mode only and AWU interrupt which exits from AWUFH mode only.

2. Exit from Halt possible when SPI is in slave mode.

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Interrupts

ST72344xx, ST72345xx

8.6

External interrupts

8.6.1

I/O port interrupt sensitivity

The external interrupt sensitivity is controlled by the IPA, IPB and ISxx bits of the EICR

register (Figure 24). This control allows to have up to 4 fully independent external interrupt

source sensitivities.

Each external interrupt source can be generated on four (or five) different events on the pin:

●

Falling edge

Rising edge

Falling and rising edge

Falling edge and low level

Rising edge and high level (only for ei0 and ei2)

To guarantee correct functionality, the sensitivity bits in the EICR register can be modified

only when the I1 and I0 bits of the CC register are both set to 1 (level 3). This means that

interrupts must be disabled before changing sensitivity.

The pending interrupts are cleared by writing a different value in the ISx[1:0], IPA or IPB bits

of the EICR.

Figure 24. External interrupt control bits

PORT A3, E1 INTERRUPTS

EICR

IS20 IS21

PAOR.3

PADDR.3

PA3

PE1

ei0 INTERRUPT SOURCE

SENSITIVITY

CONTROL

PA3

IPA BIT

EICR

PORT F [2:0] INTERRUPTS

IS20

IS21

PFOR.2

PF2

PF1

PFDDR.2

ei1 INTERRUPT SOURCE

SENSITIVITY

CONTROL

PF2

PF0

EICR

PORT B [3:0] INTERRUPTS

IS10

IS11

PB3

PBOR.3

PBDDR.3

ei2 INTERRUPT SOURCE

PB2

PB1

PB0

SENSITIVITY

CONTROL

PB3

IPB BIT

EICR

PORT B4 INTERRUPT

IS10

IS11

PBOR.4

PBDDR.4

ei3 INTERRUPT SOURCE

SENSITIVITY

CONTROL

PB4

60/246

ST72344xx, ST72345xx

Interrupts

8.7

External interrupt control register (EICR)

Reset value: 0000 0000 (00h)

7

0

IS11

IS10

IPB

IS21

IS20

IPA

0

Read/Write

Bits 7:6 = IS1[1:0] ei2 and ei3 sensitivity

The interrupt sensitivity, defined using the IS1[1:0] bits, is applied to the following

external interrupts:

●

ei2 (port B3..0)

Table 18. External interrupt sensitivity (ei2)

Sensitivity

IS11

IS10

IPB bit =0

IPB bit =1

0

1

0

1

0

1

Falling edge & low level

Rising edge only

Rising edge & high level

Falling edge only

Rising edge only

Rising and falling edge

●

ei3 (port B4)

Table 19. External interrupt sensitivity (ei3)

IS11

IS10

Sensitivity

0

1

0

1

0

1

Falling edge & low level

Rising edge only

Falling edge only

Rising and falling edge

These 2 bits can be written only when I1 and I0 of the CC register are both set to 1 (level 3).

Bit 5 = IPB Interrupt polarity for port B

This bit is used to invert the sensitivity of the port B [3:0] external interrupts. It can be

set and cleared by software only when I1 and I0 of the CC register are both set to 1

(level 3).

0: No sensitivity inversion

1: Sensitivity inversion

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Interrupts

ST72344xx, ST72345xx

Bits 4:3 = IS2[1:0] ei0 and ei1 sensitivity

The interrupt sensitivity, defined using the IS2[1:0] bits, is applied to the following

external interrupts:

●

ei0 (port A3, port E1)

Table 20. External interrupt sensitivity (ei0)

Sensitivity

IS21

IS20

IPA bit =0

IPA bit =1

0

1

0

1

0

1

Falling edge & low level

Rising edge only

Rising edge & high level

Falling edge only

Rising edge only

Rising and falling edge

●

ei1 (port F2..0)

Table 21. External interrupt sensitivity (ei1)

IS21

IS20

Sensitivity

0

1

0

1

0

1

Falling edge & low level

Rising edge only

Falling edge only

Rising and falling edge

These 2 bits can be written only when I1 and I0 of the CC register are both set to 1 (level 3).

Bit 2 = IPA Interrupt polarity for ports A3 and E1

This bit is used to invert the sensitivity of the port A3 and E1 external interrupts. It can

be set and cleared by software only when I1 and I0 of the CC register are both set to 1

(level 3).

0: No sensitivity inversion

1: Sensitivity inversion

Bits 1:0 = Reserved, must always be kept cleared.

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ST72344xx, ST72345xx

Interrupts

Table 22. Nested interrupts register map and reset values

Address Register

7

6

5

4

3

2

1

0

(Hex.)

label

ei1

ei0

MCC + SI

AWU

0024h

ISPR0

Reset value

I1_3

1

I0_3

1

I1_2

1

I0_2

1

I1_1

1

I0_1

1

I1_0

1

I0_0

1

I2C3SNS

ei3

ei2

SPI

AVD

0025h

0026h

ISPR1

Reset value

I1_7

1

I0_7

1

I1_6

1

I0_6

1

I1_5

1

I0_5

1

I1_4

1

I0_4

1

SCI

TIMER B

TIMER A

ISPR2

Reset value

I1_11

1

I0_11

1

I1_10

1

I0_10

1

I1_9

1

I0_9

1

I1_8

1

I0_8

1

I2C

0027h

0028h

ISPR3

Reset value

I1_13

1

I0_13

1

I1_12

1

I0_12

1

EICR

Reset value

IS11

0

IS10

0

IPB

0

IS21

0

IS20

0

IPA

0

63/246

Power-saving modes

ST72344xx, ST72345xx

9

Power-saving modes

9.1

Introduction

To give a large measure of flexibility to the application in terms of power consumption, five

main power saving modes are implemented in the ST7 (see Figure 25):

●

Slow

Wait (and Slow-Wait)

Active-halt

Auto-wakeup from Halt (AWUFH)

Halt

After a reset the normal operating mode is selected by default (Run mode). This mode

drives the device (CPU and embedded peripherals) by means of a master clock which is

based on the main oscillator frequency divided or multiplied by 2 (f

).

OSC2

From Run mode, the different power saving modes may be selected by setting the relevant

register bits or by calling the specific ST7 software instruction whose action depends on the

oscillator status.

Figure 25. Power saving mode transitions

High

Run

Slow

Wait

Slow-wait

Active-halt

Auto-wakeup from Halt

Halt

Low

Power consumption

64/246

ST72344xx, ST72345xx

Power-saving modes

9.2

Slow mode

This mode has two targets:

●

To reduce power consumption by decreasing the internal clock in the device,

To adapt the internal clock frequency (f ) to the available supply voltage.

●

CPU

Slow mode is controlled by three bits in the MCCSR register: the SMS bit which enables or

disables Slow mode and two CPx bits which select the internal slow frequency (f ).

CPU

In this mode, the master clock frequency (f

) can be divided by 2, 4, 8 or 16. The CPU

OSC2

and peripherals are clocked at this lower frequency (f

).

CPU

Note:

Slow-wait mode is activated by entering Wait mode while the device is in Slow mode.

Figure 26. Slow mode clock transitions

f

/2

f

/4

f

OSC2

f

CPU

f

OSC2

00

01

CP1:0

SMS

Normal Run mode

request

New slow

frequency

request

9.3

Wait mode

Wait mode places the MCU in a low-power consumption mode by stopping the CPU.

This power saving mode is selected by calling the ‘WFI’ instruction.

All peripherals remain active. During Wait mode, the I[1:0] bits of the CC register are forced

to ‘10’, to enable all interrupts. All other registers and memory remain unchanged. The MCU

remains in Wait mode until an interrupt or reset occurs, whereupon the Program Counter

branches to the starting address of the interrupt or Reset service routine.

The MCU will remain in Wait mode until a Reset or an Interrupt occurs, causing it to wake

up.

Refer to Figure 27.

65/246

Power-saving modes

Figure 27. Wait mode flowchart

ST72344xx, ST72345xx

OSCILLATOR

PERIPHERALS

CPU

ON

OFF

10

WFI INSTRUCTION

I[1:0] BITS

N

RESET

Y

N

INTERRUPT

Y

OSCILLATOR

PERIPHERALS

CPU

ON

OFF

ON

10

I[1:0] BITS

256 OR 4096 CPU CLOCK

CYCLE DELAY

OSCILLATOR

PERIPHERALS

CPU

ON

I[1:0] BITS

XX ⁽¹⁾

FETCH RESET VECTOR

OR SERVICE INTERRUPT

Note:

1

Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the

CC register are set to the current software priority level of the interrupt routine and

recovered when the CC register is popped.

9.4

Halt mode

The Halt mode is the lowest power consumption mode of the MCU. It is entered by

executing the ‘HALT’ instruction when the OIE bit of the Main Clock Controller Status

register (MCCSR) is cleared (see Section 11.2 on page 88 for more details on the MCCSR

register) and when the AWUEN bit in the AWUCSR register is cleared.

The MCU can exit Halt mode on reception of either a specific interrupt (see Table 17:

Interrupt mapping on page 59) or a reset. When exiting Halt mode by means of a reset or an

interrupt, the oscillator is immediately turned on and the 256 or 4096 CPU cycle delay is

used to stabilize the oscillator. After the start up delay, the CPU resumes operation by

servicing the interrupt or by fetching the reset vector which woke it up (see Figure 29).

When entering Halt mode, the I[1:0] bits in the CC register are forced to ‘10b’to enable

interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately.

In Halt mode, the main oscillator is turned off causing all internal processing to be stopped,

including the operation of the on-chip peripherals. All peripherals are not clocked except the

ones which get their clock supply from another clock generator (such as an external or

auxiliary oscillator).

The compatibility of Watchdog operation with Halt mode is configured by the “WDGHALT”

option bit of the option byte. The HALT instruction when executed while the Watchdog

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ST72344xx, ST72345xx

Power-saving modes

system is enabled, can generate a Watchdog reset (see Section 11.1 on page 82 for more

details).

Figure 28. Halt timing overview

256 OR 4096 CPU

Run

Halt

Run

cycle delay

Reset

or

interrupt

Halt

instruction

[MCCSR.OIE=0]

Fetch

vector

Figure 29. Halt mode flowchart

HALT INSTRUCTION

(MCCSR.OIE=0)

(AWUCSR.AWUEN=0)

WATCHDOG

DISABLE

ENABLE

0

WDGHALT ¹⁾

1

WATCHDOG

RESET

OSCILLATOR

OFF

10

PERIPHERALS ²⁾

CPU

I[1:0] BITS

N

RESET

Y

N

INTERRUPT ³⁾

Y

OSCILLATOR

PERIPHERALS

CPU

ON

OFF

ON

I[1:0] BITS

XX ⁴⁾

256 OR 4096 CPU CLOCK

CYCLE DELAY

OSCILLATOR

PERIPHERALS

CPU

ON

I[1:0] BITS

XX ⁴⁾

FETCH RESET VECTOR

OR SERVICE INTERRUPT

Note:

1

2

3

WDGHALT is an option bit. See option byte section for more details.

Peripheral clocked with an external clock source can still be active.

Only some specific interrupts can exit the MCU from Halt mode (such as external interrupt).

Refer to Table 17: Interrupt mapping on page 59 for more details.

4

Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the

CC register are set to the current software priority level of the interrupt routine and

recovered when the CC register is popped.

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Power-saving modes

Halt mode recommendations

ST72344xx, ST72345xx

●

Make sure that an external event is available to wake up the microcontroller from Halt

mode.

●

When using an external interrupt to wake up the microcontroller, reinitialize the

corresponding I/O as “Input Pull-up with Interrupt” before executing the HALT

instruction. The main reason for this is that the I/O may be wrongly configured due to

external interference or by an unforeseen logical condition.

●

For the same reason, reinitialize the level sensitiveness of each external interrupt as a

precautionary measure.

The opcode for the HALT instruction is 0x8E. To avoid an unexpected HALT instruction

due to a program counter failure, it is advised to clear all occurrences of the data value

0x8E from memory. For example, avoid defining a constant in ROM with the value

0x8E.

●

As the HALT instruction clears the interrupt mask in the CC register to allow interrupts,

the user may choose to clear all pending interrupt bits before executing the HALT

instruction. This avoids entering other peripheral interrupt routines after executing the

external interrupt routine corresponding to the wake-up event (reset or external

interrupt).

9.5

Active-halt mode

Active-halt mode is the lowest power consumption mode of the MCU with a real-time clock

available. It is entered by executing the ‘HALT’ instruction when MCC/RTC interrupt enable

flag (OIE bit in MCCSR register) is set and when the AWUEN bit in the AWUCSR register is

cleared (see Register description on page 72).

Table 23. Power saving mode

MCCSR OIE bit

Power saving mode entered when HALT instruction is executed

Halt mode

Active-halt mode

0

1

The MCU can exit Active-halt mode on reception of the RTC interrupt and some specific

interrupts (see Table 17: Interrupt mapping on page 59) or a reset. When exiting Active-halt

mode by means of a reset a 4096 or 256 CPU cycle delay occurs (depending on the option

byte). After the start up delay, the CPU resumes operation by servicing the interrupt or by

fetching the reset vector which woke it up (see Figure 31).

When entering Active-halt mode, the I[1:0] bits in the CC register are cleared to enable

interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately.

In Active-Halt mode, only the main oscillator and its associated counter (MCC/RTC) are

running to keep a wake-up time base. All other peripherals are not clocked except those

which get their clock supply from another clock generator (such as external or auxiliary

oscillator).

The safeguard against staying locked in Active-halt mode is provided by the oscillator

interrupt.

Note:

As soon as active halt is enabled, executing a HALT instruction while the Watchdog is active

does not generate a reset. This means that the device cannot spend more than a defined

delay in this power saving mode.

68/246

ST72344xx, ST72345xx

Figure 30. Active-halt timing overview

Power-saving modes

Active-

halt

256 OR 4096 cycle

delay (after reset)

Run

Reset

or

interrupt

HALT

instruction

Fetch

vector

(Active-halt enabled)

Figure 31. Active-halt mode flowchart

OSCILLATOR

ON

HALT INSTRUCTION

(MCCSR.OIE=1)

(AWUCSR.AWUEN=0)

PERIPHERALS ²⁾

CPU

OFF

10

I[1:0] BITS

N

RESET

N

Y

INTERRUPT ³⁾

OSCILLATOR

PERIPHERALS

CPU

ON

OFF

ON

Y

I[1:0] BITS

XX ⁴⁾

256 OR 4096 CPU CLOCK

CYCLE DELAY

OSCILLATOR

PERIPHERALS

CPU

ON

I[1:0] BITS

XX ⁴⁾

FETCH RESET VECTOR

OR SERVICE INTERRUPT

Note:

1

2

3

This delay occurs only if the MCU exits Active-Halt mode by means of a reset.

Peripheral clocked with an external clock source can still be active.

Only the RTC interrupt and some specific interrupts can exit the MCU from Active-halt mode

(such as external interrupt). Refer to Table 17 on page 59 for more details.

4

Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits in the

CC register are set to the current software priority level of the interrupt routine and restored

when the CC register is popped.

9.6

Auto-wakeup from Halt mode

Auto-wakeup from Halt (AWUFH) mode is similar to Halt mode with the addition of an

internal RC oscillator for wake-up. Compared to Active-Halt mode, AWUFH has lower power

consumption because the main clock is not kept running, but there is no accurate real-time

clock available.

69/246

Power-saving modes

ST72344xx, ST72345xx

It is entered by executing the HALT instruction when the AWUEN bit in the AWUCSR

register has been set and the OIE bit in the MCCSR register is cleared (see Section 11.2 on

page 88 for more details).

Figure 32. AWUFH mode block diagram

AWU RC

oscillator

to Timer input capture

f

AWU_RC

AWUFH

interrupt

AWUFH

/64

divider

prescaler

/1 .. 255

As soon as Halt mode is entered, and if the AWUEN bit has been set in the AWUCSR

register, the AWU RC oscillator provides a clock signal (f ). Its frequency is divided by

AWU_RC

a fixed divider and a programmable prescaler controlled by the AWUPR register. The output

of this prescaler provides the delay time. When the delay has elapsed the AWUF flag is set

by hardware and an interrupt wakes-up the MCU from Halt mode. At the same time the main

oscillator is immediately turned on and a 256 or 4096 cycle delay is used to stabilize it. After

this startup delay, the CPU resumes operation by servicing the AWUFH interrupt. The AWU

flag and its associated interrupt are cleared by software reading the AWUCSR register.

To compensate for any frequency dispersion of the AWU RC oscillator, it can be calibrated

by measuring the clock frequency f

and then calculating the right prescaler value.

AWU_RC

Measurement mode is enabled by setting the AWUM bit in the AWUCSR register in Run

mode. This connects internally f to the ICAP2 input of the 16-bit timer A, allowing the

AWU_RC

f

to be measured using the main oscillator clock as a reference timebase.

AWU_RC

Similarities with Halt mode

The following AWUFH mode behavior is the same as normal Halt mode:

●

The MCU can exit AWUFH mode by means of any interrupt with exit from Halt

capability or a reset (see Section 9.4: Halt mode on page 66).

When entering AWUFH mode, the I[1:0] bits in the CC register are forced to 10b to

enable interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately.

In AWUFH mode, the main oscillator is turned off causing all internal processing to be

stopped, including the operation of the on-chip peripherals. None of the peripherals are

clocked except those which get their clock supply from another clock generator (such

as an external or auxiliary oscillator like the AWU oscillator).

●

The compatibility of Watchdog operation with AWUFH mode is configured by the

WDGHALT option bit in the option byte. Depending on this setting, the HALT instruction

when executed while the Watchdog system is enabled, can generate a Watchdog

reset.

70/246

ST72344xx, ST72345xx

Figure 33. AWUF Halt timing diagram

Power-saving modes

t

AWU

Run mode

Halt mode

256 or 4096 t

Run mode

Clear

CPU

f_CPU

f_{AWU_RC}

by software

AWUFH interrupt

Figure 34. AWUFH mode flowchart

HALT INSTRUCTION

(MCCSR.OIE=0)

(AWUCSR.AWUEN=1)

ENABLE

WATCHDOG

0

DISABLE

WDGHALT ⁽¹⁾

1

AWU RC OSC

MAIN OSC

ON

OFF

10

WATCHDOG

RESET

PERIPHERALS ⁽²⁾

CPU

I[1:0] BITS

N

RESET

Y

N

INTERRUPT ⁽³⁾

AWU RC OSC

MAIN OSC

OFF

ON

Y

PERIPHERALS

CPU

I[1:0] BITS

OFF

ON

XX ⁽⁴⁾

256 OR 4096 CPU CLOCK

CYCLE DELAY

AWU RC OSC

MAIN OSC

PERIPHERALS

CPU

OFF

ON

I[1:0] BITS

XX ⁽⁴⁾

FETCH RESET VECTOR

OR SERVICE INTERRUPT

1. WDGHALT is an option bit. See option byte section for more details.

2. Peripheral clocked with an external clock source can still be active.

3. Only an AWUFH interrupt and some specific interrupts can exit the MCU from Halt mode (such as external

interrupt). Refer to Table 17: Interrupt mapping on page 59 for more details.

4. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are

set to the current software priority level of the interrupt routine and recovered when the CC register is

popped.

71/246

Power-saving modes

ST72344xx, ST72345xx

9.7

Register description

9.7.1

AWUFH control/status register (AWUCSR)

Reset value: 0000 0000 (00h)

7

0

AWU

F

0

AWUM

AWUEN

Read/Write (except bit 2 read only)

Bits 7:3 = Reserved.

Bit 2= AWUF Auto-wakeup flag

This bit is set by hardware when the AWU module generates an interrupt and cleared

by software on reading AWUCSR.

0: No AWU interrupt occurred

1: AWU interrupt occurred

Bit 1= AWUM Auto-wakeup measurement

This bit enables the AWU RC oscillator and connects internally its output to the ICAP2

input of 16-bit timer A. This allows the timer to be used to measure the AWU RC

oscillator dispersion and then compensate this dispersion by providing the right value in

the AWUPR register.

0: Measurement disabled

1: Measurement enabled

Bit 0 = AWUEN Auto-wakeup from Halt Enabled

This bit enables the Auto-wakeup from Halt feature: once Halt mode is entered, the

AWUFH wakes up the microcontroller after a time delay defined by the AWU prescaler

value. It is set and cleared by software.

0: AWUFH (Auto-wakeup from Halt) mode disabled

1: AWUFH (Auto-wakeup from Halt) mode enabled

72/246

ST72344xx, ST72345xx

Power-saving modes

9.7.2

AWUFH prescaler register (AWUPR)

Reset value: 1111 1111 (FFh)

7

0

AWUPR7 AWUPR6 AWUPR5 AWUPR4 AWUPR3 AWUPR2 AWUPR1 AWUPR0

Read/Write

Bits 7:0= AWUPR[7:0] Auto-wakeup Prescaler

These 8 bits define the AWUPR Dividing factor (as explained below:

Table 24. AWUPR dividing factor

AWUPR[7:0]

Dividing factor

00h

01h

...

Forbidden ⁽¹⁾

1

...

FEh

FFh

254

255

1. If 00h is written to AWUPR, depending on the product, an interrupt is generated immediately after a HALT

instruction, or the AWUPR remains unchanged.

In AWU mode, the period that the MCU stays in Halt mode (t

in Figure 33) is defined by

AWU

1

t

= 64 × AWUPR × ------------------------- + t

RCSTRT

AWU

f

AWURC

This prescaler register can be programmed to modify the time that the MCU stays in Halt

mode before waking up automatically.

Table 25. AWU register map and reset values

Address Register

7

6

5

4

3

2

1

0

(Hex.)

label

AWUCSR

Reset value

AWUF

0

AWUM

0

AWUEN

0

002Eh

0

AWUPR

Reset value

AWUPR7 AWUPR6 AWUPR5 AWUPR4 AWUPR3 AWUPR2 AWUPR1 AWUPR0

002Fh

1

73/246

I/O ports

ST72344xx, ST72345xx

10

I/O ports

10.1

Introduction

The I/O ports offer different functional modes:

●

transfer of data through digital inputs and outputs

and for specific pins:

●

external interrupt generation

alternate signal input/output for the on-chip peripherals.

An I/O port contains up to 8 pins. Each pin can be programmed independently as digital

input (with or without interrupt generation) or digital output.

10.2

Functional description

Each port has two main registers:

●

Data Register (DR)

●

Data Direction Register (DDR)

and one optional register:

Option Register (OR)

●

Each I/O pin may be programmed using the corresponding register bits in the DDR and OR

registers: Bit X corresponding to pin X of the port. The same correspondence is used for the

DR register.

The following description takes into account the OR register, (for specific ports which do not

provide this register refer to the I/O Port Implementation section). The generic I/O block

diagram is shown in Figure 35.

10.2.1

Input modes

The input configuration is selected by clearing the corresponding DDR register bit.

In this case, reading the DR register returns the digital value applied to the external I/O pin.

Different input modes can be selected by software through the OR register.

Writing the DR register modifies the latch value but does not affect the pin status.

Note:

1

2

When switching from input to output mode, the DR register has to be written first to drive the

correct level on the pin as soon as the port is configured as an output.

3

Do not use read/modify/write instructions (BSET or BRES) to modify the DR register as this

might corrupt the DR content for I/Os configured as input.

External interrupt function

When an I/O is configured as Input with Interrupt, an event on this I/O can generate an

external interrupt request to the CPU.

Each pin can independently generate an interrupt request. The interrupt sensitivity is

independently programmable using the sensitivity bits in the EICR register.

74/246

ST72344xx, ST72345xx

I/O ports

Each external interrupt vector is linked to a dedicated group of I/O port pins (see pinout

description and interrupt section). If several input pins are selected simultaneously as

interrupt sources, these are first detected according to the sensitivity bits in the EICR

register and then logically ORed.

The external interrupts are hardware interrupts, which means that the request latch (not

accessible directly by the application) is automatically cleared when the corresponding

interrupt vector is fetched. To clear an unwanted pending interrupt by software, the

sensitivity bits in the EICR register must be modified.

10.2.2

Output modes

The output configuration is selected by setting the corresponding DDR register bit. In this

case, writing the DR register applies this digital value to the I/O pin through the latch. Then

reading the DR register returns the previously stored value.

Two different output modes can be selected by software through the OR register: Output

push-pull and open-drain.

DR register value and output pin status:

Table 26. Output modes

DR

Push-pull

Open-drain

0

1

V_SS

V_DD

V_SS

Floating

10.2.3

Alternate functions

When an on-chip peripheral is configured to use a pin, the alternate function is automatically

selected. This alternate function takes priority over the standard I/O programming.

When the signal is coming from an on-chip peripheral, the I/O pin is automatically

configured in output mode (push-pull or open drain according to the peripheral).

When the signal is going to an on-chip peripheral, the I/O pin must be configured in input

mode. In this case, the pin state is also digitally readable by addressing the DR register.

Note:

Input pull-up configuration can cause unexpected value at the input of the alternate

peripheral input. When an on-chip peripheral use a pin as input and output, this pin has to

be configured in input floating mode.

75/246

I/O ports

ST72344xx, ST72345xx

Figure 35. I/O port general block diagram

ALTERNATE

OUTPUT

1

0

REGISTER

ACCESS

P-BUFFER

(see table below)

V_DD

ALTERNATE

ENABLE

PULL-UP

(see table below)

DR

DDR

OR

V_DD

PULL-UP

CONDITION

PAD

If implemented

OR SEL

DDR SEL

DR SEL

N-BUFFER

DIODES

(see table below)

ANALOG

INPUT

CMOS

SCHMITT

TRIGGER

1

0

ALTERNATE

INPUT

EXTERNAL

INTERRUPT

SOURCE (ei_x)

(1)

Table 27. I/O Port mode options

Configuration mode

Diodes

to V_SS

Pull-up

P-Buffer

to V_DD

Floating with/without Interrupt

Pull-up with/without Interrupt

Push-pull

Off

On

Input

Off

On

Off

NI

On

Off

NI

Output

Open drain (logic level)

True open drain

NI⁽²⁾

1. NI = not implemented, Off = implemented not activated, On = implemented and activated.

2. The diode to VDD is not implemented in the true open drain pads. A local protection between the pad and

VSS is implemented to protect the device against positive stress.

76/246

ST72344xx, ST72345xx

I/O ports

Table 28. I/O port configurations

Hardware configuration

DR REGISTER ACCESS

NOT IMPLEMENTED IN

TRUE OPEN DRAIN

I/O PORTS

V_DD

PULL-UP

CONDITION

R_PU

W

R

DR

REGISTER

DATA BUS

PAD

ALTERNATE INPUT

EXTERNAL INTERRUPT

SOURCE (ei_x)

INTERRUPT

CONDITION

ANALOG INPUT

NOT IMPLEMENTED IN

TRUE OPEN DRAIN

I/O PORTS

DR REGISTER ACCESS

V_DD

R_PU

R/W

DR

REGISTER

DATA BUS

PAD

ALTERNATE

ENABLE

ALTERNATE

OUTPUT

NOT IMPLEMENTED IN

TRUE OPEN DRAIN

I/O PORTS

DR REGISTER ACCESS

V_DD

R_PU

R/W

DR

REGISTER

DATA BUS

PAD

ALTERNATE

ENABLE

ALTERNATE

OUTPUT

1. When the I/O port is in input configuration and the associated alternate function is enabled as an output,

reading the DR register will read the alternate function output status.

2. When the I/O port is in output configuration and the associated alternate function is enabled as an input,

the alternate function reads the pin status given by the DR register content.

Caution:

The alternate function must not be activated as long as the pin is configured as input with

interrupt, in order to avoid generating spurious interrupts.

Analog alternate function

When the pin is used as an ADC input, the I/O must be configured as floating input. The

analog multiplexer (controlled by the ADC registers) switches the analog voltage present on

the selected pin to the common analog rail which is connected to the ADC input.

It is recommended not to change the voltage level or loading on any port pin while

conversion is in progress. Furthermore it is recommended not to have clocking pins located

close to a selected analog pin.

77/246

I/O ports

ST72344xx, ST72345xx

Warning: The analog input voltage level must be within the limits

stated in the absolute maximum ratings.

10.3

I/O port implementation

The hardware implementation on each I/O port depends on the settings in the DDR and OR

registers and specific feature of the I/O port such as ADC Input or true open drain.

Switching these I/O ports from one state to another should be done in a sequence that

prevents unwanted side effects. Recommended safe transitions are illustrated in Figure 36

on page 78. Other transitions are potentially risky and should be avoided, since they are

likely to present unwanted side-effects such as spurious interrupt generation.

Figure 36. Interrupt I/O port state transitions

01

00

10

11

INPUT

floating/pull-up

interrupt

INPUT

floating

(reset state)

OUTPUT

open-drain

OUTPUT

push-pull

= DDR, OR

XX

10.4

10.5

Low-power modes

Table 29. Description

Mode

Description

Wait

Halt

No effect on I/O ports. External interrupts cause the device to exit from Wait mode.

No effect on I/O ports. External interrupts cause the device to exit from Halt mode.

Interrupts

The external interrupt event generates an interrupt if the corresponding configuration is

selected with DDR and OR registers and the interrupt mask in the CC register is not active

(RIM instruction).

Table 30. Description of interrupt events

Enable

Control bit

Exit from

Wait

Exit from

Halt

Interrupt event

Event flag

External interrupt on selected

external event

DDRx

ORx

-

Yes

78/246

ST72344xx, ST72345xx

I/O ports

10.5.1

I/O port implementation

The I/O port register configurations are summarized as follows.

Standard ports: PA[5:4], PC[7:0], PD[5:0], PE0, PF[7:6], PF4

Table 31. I/O port register configurations (standard ports)

Mode

DDR

OR

floating input

0

1

0

1

0

1

pull-up input

open drain output

push-pull output

Interrupt ports: PB4, PB[2:0], PF[1:0] (with pull-up)

Table 32. I/O port register configurations (interrupt ports with pull-up)

Mode

DDR

OR

floating input

0

1

0

1

0

1

pull-up interrupt input

open drain output

push-pull output

PA3, PE1, PB3, PF2 (without pull-up)

Table 33. I/O port register configurations (interrupt ports without pull-up)

Mode

DDR

OR

floating input

0

1

0

1

0

1

floating interrupt input

open drain output

push-pull output

True open-drain ports: PA[7:6], PD[7:6]

Table 34. I/O port register configurations (true open drain ports)

Mode

DDR

floating input

0

1

open drain (high sink ports)

79/246

I/O ports

ST72344xx, ST72345xx

Output

Table 35. Port configuration

Input

Port

Pin name

OR = 0

OR = 1

OR = 0

OR = 1

PA7:6

PA5:4

PA3

floating

true open-drain

Port A

floating

pull-up

open drain

push-pull

floating interrupt

PB3

Port B

PB4,

PB2:0

floating

pull-up interrupt

pull-up

open drain

push-pull

Port C

Port D

PC7:0

PD7:6

PD5:0

PE1

floating

true open-drain

floating

pull-up

floating interrupt

pull-up

open drain

push-pull

Port E

Port F

PE0

PF7:6, 4

PF2

pull-up

floating interrupt

pull-up interrupt

PF1:0

Caution:

In small packages, an internal pull-up is applied permanently to the non-bonded I/O pins. So

they have to be kept in input floating configuration to avoid unwanted consumption.

Table 36. I/O port register map and reset values

Address Register

7

6

5

4

3

2

1

0

(Hex.)

label

Reset value

of all I/O port registers

0

0000h

0001h

0002h

0003h

0004h

0005h

0006h

0007h

0008h

0009h

000Ah

000Bh

PADR

PADDR

PAOR

MSB

LSB

PBDR

PBDDR

PBOR

PCDR

PCDDR

PCOR

PDDR

PDDDR

PDOR

80/246

ST72344xx, ST72345xx

Table 36. I/O port register map and reset values (continued)

I/O ports

Address Register

7

6

5

4

3

2

1

0

(Hex.)

label

000Ch

000Dh

000Eh

000Fh

0010h

0011h

PEDR

PEDDR

PEOR

PFDR

MSB

LSB

PFDDR

PFOR

MSB

LSB

81/246

On-chip peripherals

ST72344xx, ST72345xx

11

On-chip peripherals

11.1

Window watchdog (WWDG)

11.1.1

Introduction

The window watchdog is used to detect the occurrence of a software fault, usually

generated by external interference or by unforeseen logical conditions, which causes the

application program to abandon its normal sequence. The Watchdog circuit generates an

MCU reset on expiry of a programmed time period, unless the program refreshes the

contents of the downcounter before the T6 bit becomes cleared. An MCU reset is also

generated if the 7-bit downcounter value (in the control register) is refreshed before the

downcounter has reached the window register value. This implies that the counter must be

refreshed in a limited window.

11.1.2

Main features

●

Programmable free-running downcounter

Conditional reset

–

Reset (if watchdog activated) when the downcounter value becomes less than 40h

Reset (if watchdog activated) if the downcounter is reloaded outside the window

(see Figure 40)

●

Hardware/Software Watchdog activation (selectable by option byte)

Optional reset on HALT instruction (configurable by option byte)

11.1.3

Functional description

The counter value stored in the WDGCR register (bits T[6:0]), is decremented every 16384

f

cycles (approx.), and the length of the timeout period can be programmed by the user

OSC2

in 64 increments.

If the watchdog is activated (the WDGA bit is set) and when the 7-bit downcounter (T[6:0]

bits) rolls over from 40h to 3Fh (T6 becomes cleared), it initiates a reset cycle pulling low the

reset pin for typically 30 μs. If the software reloads the counter while the counter is greater

than the value stored in the window register, then a reset is generated.

82/246

ST72344xx, ST72345xx

Figure 37. Watchdog block diagram

On-chip peripherals

WATCHDOG WINDOW REGISTER (WDGWR)

W5

W0

W1

RESET

-

W6

W4

W2

W3

comparator

= 1 when

T6:0 > W6:0

CMP

Write WDGCR

WATCHDOG CONTROL REGISTER (WDGCR)

T5

T0

WDGA T6

T1

T4

T2

T3

6-BIT DOWNCOUNTER (CNT)

MCC/RTC

f

OSC2

DIV 64

WDG PRESCALER

DIV 4

12-BIT MCC

RTC COUNTER

TB[1:0] bits

(MCCSR

Register)

MSB

LSB

0

6 5

11

The application program must write in the WDGCR register at regular intervals during

normal operation to prevent an MCU reset. This operation must occur only when the counter

value is lower than the window register value. The value to be stored in the WDGCR register

must be between FFh and C0h (see Figure 38):

●

Enabling the watchdog:

When Software Watchdog is selected (by option byte), the watchdog is disabled after a

reset. It is enabled by setting the WDGA bit in the WDGCR register, then it cannot be

disabled again except by a reset.

When Hardware Watchdog is selected (by option byte), the watchdog is always active

and the WDGA bit is not used.

●

Controlling the downcounter:

This downcounter is free-running: It counts down even if the watchdog is disabled.

When the watchdog is enabled, the T6 bit must be set to prevent generating an

immediate reset.

The T[5:0] bits contain the number of increments which represents the time delay

before the watchdog produces a reset (see Figure 38: Approximate timeout duration).

The timing varies between a minimum and a maximum value due to the unknown

status of the prescaler when writing to the WDGCR register (see Figure 39).

The window register (WDGWR) contains the high limit of the window: To prevent a

reset, the downcounter must be reloaded when its value is lower than the window

register value and greater than 3Fh. Figure 40 describes the window watchdog

process.

83/246

On-chip peripherals

ST72344xx, ST72345xx

Note:

The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is

cleared).

●

Watchdog reset on Halt option

If the watchdog is activated and the watchdog reset on halt option is selected, then the

HALT instruction will generate a Reset.

11.1.4

11.1.5

Using Halt mode with the WDG

If Halt mode with Watchdog is enabled by option byte (no watchdog reset on HALT

instruction), it is recommended before executing the HALT instruction to refresh the WDG

counter, to avoid an unexpected WDG reset immediately after waking up the microcontroller.

How to program the watchdog timeout

Figure 38 shows the linear relationship between the 6-bit value to be loaded in the watchdog

counter (CNT) and the resulting timeout duration in milliseconds. This can be used for a

quick calculation without taking the timing variations into account. If more precision is

needed, use the formulae in Figure 39.

Caution:

When writing to the WDGCR register, always write 1 in the T6 bit to avoid generating an

immediate reset.

Figure 38. Approximate timeout duration

3F

38

30

28

20

18

10

08

00

1.5

18

34

50

65

82

98

114

128

Watchdog timeout (ms) @ 8 MHz f_OSC2

84/246

ST72344xx, ST72345xx

Figure 39. Exact timeout duration (t

On-chip peripherals

and t

)

min

max

Where:

t

= (LSB + 128) x 64 x t

OSC2

min0

= 16384 x t

max0

OSC2

= 125 ns if f

= 8 MHz

OSC2

CNT = Value of T[5:0] bits in the WDGCR register (6 bits)

MSB and LSB are values from the table below depending on the timebase selected by the TB[1:0]

bits in the MCCSR register

TB1 bit

(MCCSR Reg.)

TB0 bit

(MCCSR Reg.)

Selected MCCSR

time base

MSB

LSB

0

1

0

1

0

1

2 ms

4 ms

4

59

53

35

54

8

10 ms

25 ms

20

49

To calculate the minimum watchdog timeout (t ):

min

MSB

-------------

If CNT <

then

else

t

= t_min0+ 16384 × CNT × t

min

= t

osc2

4

4CNT

----------------

⎛

⎞

⎠

----------------

t

+

16384 × CNT –

+ (192 + LSB) × 64 ×

× t

osc2

min

min0

⎝

MSB

To calculate the maximum Watchdog Timeout (t_max):

MSB

-------------

If CNT ≤

then

t

= t_max0+ 16384 × CNT × t

osc2

max

4

4CNT

MSB

4CNT

----------------

⎛

⎞

----------------

else t

= t

+

16384 × CNT –

+ (192 + LSB) × 64 ×

× t

osc2

max

max0

⎝

⎠

MSB

Note:

In the above formulae, division results must be rounded down to the next integer

value.

Example:

With 2 ms timeout selected in MCCSR register

Value of T[5:0] Bits in

WDGCR Register (Hex.)

Min. watchdog timeout (ms)

Max. watchdog timeout (ms)

t_max

t_min

00

3F

1.496

128

2.048

128.552

85/246

On-chip peripherals

Figure 40. Window watchdog timing diagram

ST72344xx, ST72345xx

T[5:0] CNT downcounter

WDGWR

3Fh

time

(step = 16384/f

)

Refresh not allowed Refresh Window

OSC2

T6 bit

Reset

11.1.6

Low-power modes

Table 37. Descriptions

Mode

Description

Slow

Wait

No effect on Watchdog: The downcounter continues to decrement at normal speed.

No effect on Watchdog: The downcounter continues to decrement.

OIE bit in

MCCSR

register

WDGHALT

bit in

Option Byte

No Watchdog reset is generated. The MCU enters Halt

mode. The Watchdog counter is decremented once and

then stops counting and is no longer able to generate a

watchdog reset until the MCU receives an external

interrupt or a reset.

Halt

If an interrupt is received (refer to interrupt table mapping

to see interrupts which can occur in halt mode), the

Watchdog restarts counting after 256 or 4096 CPU clocks.

If a reset is generated, the Watchdog is disabled (reset

state) unless Hardware Watchdog is selected by option

byte. For application recommendations see Section 11.1.8

below.

0

1

x

A reset is generated instead of entering halt mode.

No reset is generated. The MCU enters Active Halt mode.

The Watchdog counter is not decremented. It stop

counting. When the MCU receives an oscillator interrupt or

external interrupt, the Watchdog restarts counting

immediately. When the MCU receives a reset the

Watchdog restarts counting after 256 or 4096 CPU clocks.

Active-halt

86/246

ST72344xx, ST72345xx

On-chip peripherals

11.1.7

11.1.8

Hardware watchdog option

If hardware watchdog is selected by option byte, the watchdog is always active and the

WDGA bit in the WDGCR is not used. Refer to the Option Byte description.

Using Halt mode with the WDG (WDGHALT option)

The following recommendation applies if Halt mode is used when the watchdog is enabled.

●

Before executing the HALT instruction, refresh the WDG counter, to avoid an

unexpected WDG reset immediately after waking up the microcontroller.

11.1.9

Interrupts

None.

11.1.10 Register description

Control register (WDGCR)

Reset value: 0111 1111 (7Fh)

7

0

WDGA

T6

T5

T4

T3

T2

T1

T0

Read/Write

Bit 7 = WDGA Activation bit.

This bit is set by software and only cleared by hardware after a reset. When WDGA = 1,

the watchdog can generate a reset.

0: Watchdog disabled

1: Watchdog enabled

Note:

This bit is not used if the hardware watchdog option is enabled by option byte.

Bits 6:0 = T[6:0] 7-bit counter (MSB to LSB).

These bits contain the value of the watchdog counter. It is decremented every 16384

f

cycles (approx.). A reset is produced when it rolls over from 40h to 3Fh (T6

OSC2

becomes cleared).

Window register (WDGWR)

Reset value: 0111 1111 (7Fh)

7

0

-

W6

W5

W4

W3

W2

W1

W0

Read/Write

Bit 7 = Reserved

Bits 6:0 = W[6:0] 7-bit window value

These bits contain the window value to be compared to the downcounter.

87/246

On-chip peripherals

ST72344xx, ST72345xx

Table 38. Watchdog timer register map and reset values

Address

(Hex.)

Register

label

7

6

5

4

3

2

1

0

WDGCR

WDGA

0

T6

1

T5

1

T4

1

T3

1

T2

1

T1

1

T0

1

2A

30

Reset value

WDGWR

-

W6

1

W5

1

W4

1

W3

1

W2

1

W1

1

W0

1

Reset value

0

11.2

Main clock controller with real-time clock and beeper

(MCC/RTC)

The main clock controller consists of three different functions:

●

a programmable CPU clock prescaler

●

a clock-out signal to supply external devices

●

a real-time clock timer with interrupt capability

Each function can be used independently and simultaneously.

11.2.1

11.2.2

Programmable CPU clock prescaler

The programmable CPU clock prescaler supplies the clock for the ST7 CPU and its internal

peripherals. It manages Slow power-saving mode (See Section 9.2: Slow mode for more

details).

The prescaler selects the f

main clock frequency and is controlled by three bits in the

CPU

MCCSR register: CP[1:0] and SMS.

Clock-out capability

The clock-out capability is an alternate function of an I/O port pin that outputs a f

to drive external devices. It is controlled by the MCO bit in the MCCSR register.

clock

OSC2

Caution:

When selected, the clock out pin suspends the clock during Active-halt mode.

11.2.3

Real-time clock timer (RTC)

The counter of the real-time clock timer allows an interrupt to be generated based on an

accurate real-time clock. Four different time bases depending directly on f are available.

OSC2

The whole functionality is controlled by four bits of the MCCSR register: TB[1:0], OIE and

OIF.

When the RTC interrupt is enabled (OIE bit set), the ST7 enters Active-halt mode when the

HALT instruction is executed. See Section 9.5: Active-halt mode on page 68 for more

details.

11.2.4

Beeper

The beep function is controlled by the MCCBCR register. It can output three selectable

frequencies on the BEEP pin (I/O port alternate function).

88/246

ST72344xx, ST72345xx

Figure 41.

On-chip peripherals

Main clock controller (MCC/RTC) block diagram

BC1 BC0

MCCBCR

BEEP

MCO

BEEP SIGNAL

SELECTION

12-BIT MCC RTC

COUNTER

TO

DIV 64

WATCHDOG

TIMER

MCO CP1 CP0 SMS TB1 TB0 OIE OIF

MCCSR

MCC/RTC INTERRUPT

f_CPU

f_OSC2

DIV 2, 4, 8, 16

1

0

CPU CLOCK

TO CPU AND

PERIPHERALS

11.2.5

Low-power modes

Table 39. Mode description

Mode

Description

No effect on MCC/RTC peripheral.

MCC/RTC interrupt cause the device to exit from Wait mode.

Wait

No effect on MCC/RTC counter (OIE bit is set), the registers are frozen.

MCC/RTC interrupt cause the device to exit from Active-halt mode.

Active-halt

MCC/RTC counter and registers are frozen.

Halt

MCC/RTC operation resumes when the MCU is woken up by an interrupt with “exit

from Halt” capability.

11.2.6

Interrupts

The MCC/RTC interrupt event generates an interrupt if the OIE bit of the MCCSR register is

set and the interrupt mask in the CC register is not active (RIM instruction).

Table 40. Interrupt event

Enable

Control bit

Exit from

Wait

Exit from

Halt

Interrupt event

Event flag

Time base overflow event

OIF

OIE

Yes

No ⁽¹⁾

1. The MCC/RTC interrupt wakes up the MCU from Active-halt mode, not from Halt mode.

89/246

On-chip peripherals

ST72344xx, ST72345xx

11.2.7

Register description

MCC control/status register (MCCSR)

Reset value: 0000 0000 (00h)

7

0

MCO

CP1

CP0

SMS

TB1

TB0

OIE

OIF

Read/Write

Bit 7 = MCO Main clock out selection

This bit enables the MCO alternate function on the PF0 I/O port. It is set and cleared by

software.

0: MCO alternate function disabled (I/O pin free for general-purpose I/O)

1: MCO alternate function enabled (f

on I/O port)

CPU

Note:

To reduce power consumption, the MCO function is not active in Active-halt mode.

Bits 6:5 = CP[1:0] CPU clock prescaler

These bits select the CPU clock prescaler which is applied in the different slow modes.

Their action is conditioned by the setting of the SMS bit. These two bits are set and

cleared by software.

Table 41. CPU clock prescaler selection

f_CPUin Slow mode

_OSC2/ 2

CP1

CP0

f

0

1

0

1

0

1

f_OSC2/ 4

f_OSC2/ 8

_OSC2/ 16

f

Bit 4 = SMS Slow mode select

This bit is set and cleared by software.

0: Normal mode. f

= f

OSC2

CPU

1: Slow mode. f

is given by CP1, CP0

CPU

See Section 9.2: Slow mode and Section 11.1: Window watchdog (WWDG) on

page 82 for more details.

Bits 3:2 = TB[1:0] Time base control

These bits select the programmable divider time base. They are set and cleared by

software.

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On-chip peripherals

Table 42. Time base control

Time base

Counter

prescaler

TB1

TB0

f_OSC2= 4 MHz

f_OSC2= 8 MHz

16000

32000

80000

200000

4 ms

8 ms

2 ms

4 ms

0

1

0

1

0

1

20 ms

50 ms

10 ms

25 ms

A modification of the time base is taken into account at the end of the current period

(previously set) to avoid an unwanted time shift. This allows to use this time base as a real-

time clock.

Bit 1 = OIE Oscillator interrupt enable

This bit set and cleared by software.

0: Oscillator interrupt disabled

1: Oscillator interrupt enabled

This interrupt can be used to exit from Active-halt mode.

When this bit is set, calling the ST7 software HALT instruction enters the Active-halt

power-saving mode

.

Bit 0 = OIF Oscillator interrupt flag

This bit is set by hardware and cleared by software reading the MCCSR register. It

indicates when set that the main oscillator has reached the selected elapsed time

(TB1:0).

0: Timeout not reached

1: Timeout reached

Caution:

The BRES and BSET instructions must not be used on the MCCSR register to avoid

unintentionally clearing the OIF bit.

MCC beep control register (MCCBCR)

Reset value: 0000 0000 (00h)

7

0

BC1

BC0

Read/Write

Bits 7:2 = Reserved, must be kept cleared.

Bits 1:0 = BC[1:0] Beep control

These 2 bits select the PF1 pin beep capability.

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On-chip peripherals

ST72344xx, ST72345xx

Table 43. Beep control

BC1

BC0

Beep mode with f_OSC2= 8 MHz

Off

0

1

0

1

0

1

~2-kHz

~1-kHz

Output

Beep signal

~50% duty cycle

~500-Hz

The beep output signal is available in Active-halt mode but has to be disabled to reduce the

consumption.

Table 44. Main clock controller register map and reset values

Address Register

7

6

5

4

3

2

1

0

(Hex.)

label

SICSR

Reset value

AVDIE AVDF LVDRF LOCKED

WDGRF

x

002Bh

0

x

0

MCCSR

Reset value

MCO

0

CP1

0

CP0

0

SMS

0

TB1

0

TB0

0

OIE

0

OIF

0

002Ch

002Dh

MCCBCR

Reset value

BC1

0

BC0

0

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On-chip peripherals

11.3

16-bit timer

11.3.1

Introduction

The timer consists of a 16-bit free-running counter driven by a programmable prescaler.

It may be used for a variety of purposes, including pulse length measurement of up to two

input signals (input capture) or generation of up to two output waveforms (output compare

and PWM).

Pulse lengths and waveform periods can be modulated from a few microseconds to several

milliseconds using the timer prescaler and the CPU clock prescaler.

Some devices of the ST7 family have two on-chip 16-bit timers. They are completely

independent, and do not share any resources. They are synchronized after a Device reset

as long as the timer clock frequencies are not modified.

This description covers one or two 16-bit timers. In the devices with two timers, register

names are prefixed with TA (Timer A) or TB (Timer B).

11.3.2

Main features

●

Programmable prescaler: f

divided by 2, 4 or 8.

CPU

Overflow status flag and maskable interrupt

External clock input (must be at least 4 times slower than the CPU clock speed) with

the choice of active edge

●

Output compare functions with

–

2 dedicated 16-bit registers

2 dedicated programmable signals

2 dedicated status flags

1 dedicated maskable interrupt

●

Input capture functions with

–

2 dedicated 16-bit registers

2 dedicated active edge selection signals

2 dedicated status flags

1 dedicated maskable interrupt

●

Pulse width modulation mode (PWM)

One-pulse mode

Reduced-power mode

5 alternate functions on I/O ports (ICAP1, ICAP2, OCMP1, OCMP2, EXTCLK). See

note below.

The block diagram is shown in Figure 42.

Note:

Some timer pins may not available (not bonded) in some devices. Refer to the device pin out

description.

When reading an input signal on a non-bonded pin, the value will always be ‘1’.

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On-chip peripherals

ST72344xx, ST72345xx

11.3.3

Functional description

Counter

The main block of the programmable timer is a 16-bit free running upcounter and its

associated 16-bit registers. The 16-bit registers are made up of two 8-bit registers called

high & low.

Counter Register (CR):

●

Counter High Register (CHR) is the most significant byte (MS Byte).

Counter Low Register (CLR) is the least significant byte (LS Byte).

●

Alternate Counter Register (ACR)

●

Alternate Counter High Register (ACHR) is the most significant byte (MS Byte).

Alternate Counter Low Register (ACLR) is the least significant byte (LS Byte).

●

These two read-only 16-bit registers contain the same value but with the difference that

reading the ACLR register does not clear the TOF bit (Timer overflow flag), located in the

Status register, (SR), (see note at the end of paragraph titled 16-bit read sequence).

Writing in the CLR register or ACLR register resets the free running counter to the FFFCh

value.

Both counters have a reset value of FFFCh (this is the only value which is reloaded in the

16-bit timer). The reset value of both counters is also FFFCh in One-pulse mode and PWM

mode.

The timer clock depends on the clock control bits of the CR2 register, as illustrated in

Table 50: Clock control bits on page 110. The value in the counter register repeats every

131 072, 262 144 or 524 288 CPU clock cycles depending on the CC[1:0] bits.

The timer frequency can be f

/2, f

/4, f

/8 or an external frequency.

CPU

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ST72344xx, ST72345xx

Figure 42. Timer block diagram

On-chip peripherals

INTERNAL BUS

f_CPU

16-BIT TIMER PERIPHERAL INTERFACE

8 low

8-bit

8 high

8

buffer

EXEDG

16

INPUT

CAPTURE

REGISTER

INPUT

CAPTURE

REGISTER

OUTPUT

COMPARE

REGISTER

OUTPUT

COMPARE

REGISTER

1/2

1/4

1/8

COUNTER

REGISTER

1

2

ALTERNATE

COUNTER

REGISTER

EXTCLK

16

CC[1:0]

TIMER INTERNAL BUS

16 16

OVERFLOW

DETECT

EDGE DETECT

CIRCUIT1

OUTPUT COMPARE

CIRCUIT

ICAP1

CIRCUIT

6

EDGE DETECT

CIRCUIT2

ICAP2

OCMP1

LATCH1

LATCH2

0

ICF1 OCF1 TOF ICF2 OCF2

0

TIMD

(Control/Status Register)

OCMP2

CSR

EXEDG

ICIE OCIE TOIE FOLV2 FOLV1OLVL2 IEDG1 OLVL1

OC1E

OPM PWM CC1 CC0 IEDG2

OC2E

(Control Register 1) CR1

(Control Register 2) CR2

(See note 1)

TIMER INTERRUPT

1. If IC, OC and TO interrupt requests have separate vectors then the last OR is not present (See Device

Interrupt Vector Table).

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On-chip peripherals

ST72344xx, ST72345xx

Figure 43. 16-bit read sequence (from either the counter register or the alternate

counter register)

Beginning of the sequence

Read

MS Byte

LS Byte

is buffered

At t0

Other

instructions

Returns the buffered

LS Byte value at t0

Read

LS Byte

At t0 +Δt

Sequence completed

The user must read the MS Byte first, then the LS Byte value is buffered automatically.

This buffered value remains unchanged until the 16-bit read sequence is completed, even if

the user reads the MS Byte several times.

After a complete reading sequence, if only the CLR register or ACLR register are read, they

return the LS Byte of the count value at the time of the read.

Whatever the timer mode used (input capture, output compare, one-pulse mode or PWM

mode) an overflow occurs when the counter rolls over from FFFFh to 0000h then:

●

The TOF bit of the SR register is set.

A timer interrupt is generated if:

●

–

TOIE bit of the CR1 register is set and

I bit of the CC register is cleared.

If one of these conditions is false, the interrupt remains pending to be issued as soon as

they are both true.

Clearing the overflow interrupt request is done in two steps:

1. Reading the SR register while the TOF bit is set.

2. An access (read or write) to the CLR register.

Note:

The TOF bit is not cleared by accesses to ACLR register. The advantage of accessing the

ACLR register rather than the CLR register is that it allows simultaneous use of the overflow

function and reading the free running counter at random times (for example, to measure

elapsed time) without the risk of clearing the TOF bit erroneously.

The timer is not affected by Wait mode.

In Halt mode, the counter stops counting until the mode is exited. Counting then resumes

from the previous count (Device awakened by an interrupt) or from the reset count (Device

awakened by a Reset).

External clock

The external clock (where available) is selected if CC0=1 and CC1=1 in CR2 register.

The status of the EXEDG bit in the CR2 register determines the type of level transition on

the external clock pin EXTCLK that will trigger the free running counter.

The counter is synchronised with the falling edge of the internal CPU clock.

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ST72344xx, ST72345xx

On-chip peripherals

A minimum of four falling edges of the CPU clock must occur between two consecutive

active edges of the external clock; thus the external clock frequency must be less than a

quarter of the CPU clock frequency.

Figure 44. Counter timing diagram, internal clock divided by 2

CPU CLOCK

INTERNAL RESET

TIMER CLOCK

FFFD FFFE FFFF 0000 0001 0002 0003

COUNTER REGISTER

TIMER OVERFLOW FLAG (TOF)

Figure 45. Counter timing diagram, internal clock divided by 4

CPU CLOCK

INTERNAL RESET

TIMER CLOCK

FFFC

FFFD

0000

0001

COUNTER REGISTER

TIMER OVERFLOW FLAG (TOF)

Figure 46. Counter timing diagram, internal clock divided by 8

CPU CLOCK

INTERNAL RESET

TIMER CLOCK

0000

FFFC

FFFD

COUNTER REGISTER

TIMER OVERFLOW FLAG (TOF)

Note:

The device is in reset state when the internal reset signal is high, when it is low the Device is

running.

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On-chip peripherals

ST72344xx, ST72345xx

Input capture

In this section, the index, i, may be 1 or 2 because there are 2 input capture functions in the

16-bit timer.

The two input-capture 16-bit registers (IC1R and IC2R) are used to latch the value of the

free-running counter after a transition detected by the ICAPi pin.

Table 45. ICiR register

MS Byte

LS Byte

ICiR

ICiHR

ICiLR

ICiR register is a read-only register.

The active transition is software-programmable through the IEDGi bit of Control Registers

(CRi).

The timing resolution is one count of the free-running counter: (f_CPU/CC[1:0]).

Procedure:

To use the input capture function, select the following in the CR2 register:

●

Select the timer clock (CC[1:0]) (see Table 50: Clock control bits on page 110).

●

Select the edge of the active transition on the ICAP2 pin with the IEDG2 bit (the ICAP2

pin must be configured as floating input).

And select the following in the CR1 register:

●

Set the ICIE bit to generate an interrupt after an input capture coming from either the

ICAP1 pin or the ICAP2 pin

●

Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the

ICAP1pin must be configured as floating input).

When an input capture occurs:

●

ICFi bit is set.

●

The ICiR register contains the value of the free running counter on the active transition

on the ICAPi pin (see Figure 48).

●

A timer interrupt is generated if the ICIE bit is set and the I bit is cleared in the CC

register. Otherwise, the interrupt remains pending until both conditions become true.

Clearing the Input Capture interrupt request (i.e. clearing the ICFi bit) is done in two steps:

1. Reading the SR register while the ICFi bit is set.

2. An access (read or write) to the ICiLR register.

Note:

1

2

3

After reading the ICiHR register, transfer of input capture data is inhibited and ICFi will never

be set until the ICiLR register is also read.

The ICiR register contains the free running counter value which corresponds to the most

recent input capture.

The 2 input capture functions can be used together even if the timer also uses the 2 output

compare functions.

4

5

In One-pulse Mode and PWM mode only the input capture 2 can be used.

The alternate inputs (ICAP1 & ICAP2) are always directly connected to the timer. So any

transitions on these pins activate the input capture function.

Moreover if one of the ICAPi pin is configured as an input and the second one as an output,

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ST72344xx, ST72345xx

On-chip peripherals

an interrupt can be generated if the user toggle the output pin and if the ICIE bit is set.

This can be avoided if the input capture function i is disabled by reading the ICiHR (see note

1).

6

The TOF bit can be used with interrupt in order to measure event that go beyond the timer

range (FFFFh).

Figure 47. Input capture block diagram

ICAP1

(Control Register 1) CR1

EDGE DETECT

CIRCUIT2

EDGE DETECT

CIRCUIT1

ICIE

IEDG1

ICAP2

(Status Register) SR

ICF1

ICF2

0

IC2R Register

IC1R Register

(Control Register 2) CR2

16-BIT

16-BIT FREE RUNNING

COUNTER

IEDG2

CC0

CC1

Figure 48. Input capture timing diagram

TIMER CLOCK

FF01

FF02

FF03

COUNTER REGISTER

ICAPi PIN

ICAPi FLAG

FF03

ICAPi REGISTER

1. The active edge is the rising edge.

2. The time between an event on the ICAPi pin and the appearance of the corresponding flag is from 2 to 3

CPU clock cycles. This depends on the moment when the ICAP event happens relative to the timer clock.

Output compare

In this section, the index, i, may be 1 or 2 because there are 2 output compare functions in

the 16-bit timer.

This function can be used to control an output waveform or indicate when a period of time

has elapsed.

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On-chip peripherals

ST72344xx, ST72345xx

When a match is found between the Output Compare register and the free running counter,

the output compare function:

●

Assigns pins with a programmable value if the OCIE bit is set

Sets a flag in the status register

Generates an interrupt if enabled

Two 16-bit registers Output Compare Register 1 (OC1R) and Output Compare Register 2

(OC2R) contain the value to be compared to the counter register each timer clock cycle.

Table 46. OCiR register

MS Byte

LS Byte

OCiR

OCiHR

OCiLR

These registers are readable and writable and are not affected by the timer hardware. A

reset event changes the OCⁱR value to 8000h.

The timing resolution is one count of the free running counter: (f_CPU/

).

CC[1:0]

Procedure:

To use the output compare function, select the following in the CR2 register:

●

Set the OCiE bit if an output is needed then the OCMPi pin is dedicated to the output

compare i signal.

●

Select the timer clock (CC[1:0]) (see Table 50).

And select the following in the CR1 register:

●

Select the OLVLi bit to applied to the OCMPi pins after the match occurs.

●

Set the OCIE bit to generate an interrupt if it is needed.

When a match is found between OCRi register and CR register:

●

OCFi bit is set.

The OCMPi pin takes OLVLi bit value (OCMPi pin latch is forced low during reset).

A timer interrupt is generated if the OCIE bit is set in the CR2 register and the I bit is

cleared in the CC register (CC).

The OCⁱR register value required for a specific timing application can be calculated using

the following formula:

Δt _*f_CPU

PRESC

Δ OCiR =

Where:

●

Δt = Output compare period (in seconds)

= CPU clock frequency (in Hertz)

f

CPU

PRESC = Timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits, see Table 50:

Clock control bits)

If the timer clock is an external clock, the formula is:

Δ OCiR = Δt _*f_EXT

Where:

●

Δt = Output compare period (in seconds)

= External timer clock frequency (in Hertz)

●

f

EXT

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ST72344xx, ST72345xx

On-chip peripherals

Clearing the output compare interrupt request (i.e. clearing the OCFi bit) is done by:

1. Reading the SR register while the OCFi bit is set.

2. An access (read or write) to the OCiLR register.

The following procedure is recommended to prevent the OCFi bit from being set between

the time it is read and the write to the OCⁱR register:

●

Write to the OCiHR register (further compares are inhibited).

●

Read the SR register (first step of the clearance of the OCFi bit, which may be already

set).

●

Write to the OCiLR register (enables the output compare function and clears the OCFi

bit).

Note:

1

2

3

After a processor write cycle to the OCiHR register, the output compare function is inhibited

until the OCiLR register is also written.

If the OCiE bit is not set, the OCMPi pin is a general I/O port and the OLVLi bit will not

appear when a match is found but an interrupt could be generated if the OCIE bit is set.

In both internal and external clock modes, OCFi and OCMPi are set while the counter value

equals the OCiR register value (see Figure 50 on page 102 and Figure 51 on page 102).

This behavior is the same in OPM or PWM mode.

4

5

The output compare functions can be used both for generating external events on the

OCMPi pins even if the input capture mode is also used.

The value in the 16-bit OCⁱR register and the OLVi bit should be changed after each

successful comparison in order to control an output waveform or establish a new elapsed

timeout.

Forced compare output capability

When the FOLVi bit is set by software, the OLVLi bit is copied to the OCMPi pin. The OLVi bit

has to be toggled in order to toggle the OCMPi pin when it is enabled (OCiE bit=1). The

OCFi bit is then not set by hardware, and thus no interrupt request is generated.

FOLVLi bits have no effect in both one-pulse mode and PWM mode.

Figure 49. Output compare block diagram

16 BIT FREE RUNNING

OC1E

CC1 CC0

OC2E

OCIE

COUNTER

(Control Register 2) CR2

16-bit

(Control Register 1) CR1

OUTPUT COMPARE

CIRCUIT

Latch

1

FOLV2 FOLV1 OLVL2

OLVL1

OCMP1

16-bit

Latch

2

OCMP2

OC1R Register

OCF1

OCF2

0

OC2R Register

(Status Register) SR

101/246

On-chip peripherals

Figure 50. Output compare timing diagram, f

ST72344xx, ST72345xx

= f

/2

CPU

TIMER

INTERNAL CPU CLOCK

TIMER CLOCK

COUNTER REGISTER

2ECF 2ED0 2ED1 2ED2

2ED3

2ED4

2ED3

OUTPUT COMPARE REGISTER i (OCRi)

OUTPUT COMPARE FLAG i (OCFi)

OCMPi PIN (OLVLi=1)

Figure 51. Output compare timing diagram, f

= f

/4

CPU

TIMER

INTERNAL CPU CLOCK

TIMER CLOCK

2ECF 2ED0 2ED1 2ED2

2ED3

2ED4

2ED3

COUNTER REGISTER

OUTPUT COMPARE REGISTER i (OCRi)

COMPARE REGISTER i LATCH

OUTPUT COMPARE FLAG i (OCFi)

OCMPi PIN (OLVLi=1)

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ST72344xx, ST72345xx

On-chip peripherals

One-pulse mode

One-pulse mode enables the generation of a pulse when an external event occurs. This

mode is selected via the OPM bit in the CR2 register.

The one-pulse mode uses the Input Capture1 function and the Output Compare1 function.

Procedure:

To use one-pulse mode:

1. Load the OC1R register with the value corresponding to the length of the pulse (see the

formula in the opposite column).

2. Select the following in the CR1 register:

–

Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after the

pulse.

Using the OLVL2 bit, select the level to be applied to the OCMP1 pin during the

pulse.

Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the

ICAP1 pin must be configured as floating input).

3. Select the following in the CR2 register:

–

Set the OC1E bit, the OCMP1 pin is then dedicated to the Output Compare 1

function.

–

Set the OPM bit.

Select the timer clock CC[1:0] (see Table 50: Clock control bits on page 110).

Figure 52. One-pulse mode cycle

One-pulse mode cycle

ICR1 = Counter

OCMP1 = OLVL2

When

event occurs

on ICAP1

Counter is reset

to FFFCh

ICF1 bit is set

When

Counter

= OC1R

OCMP1 = OLVL1

When a valid event occurs on the ICAP1 pin, the counter value is loaded in the ICR1

register. The counter is then initialized to FFFCh, the OLVL2 bit is output on the OCMP1 pin

and the ICF1 bit is set.

Because the ICF1 bit is set when an active edge occurs, an interrupt can be generated if the

ICIE bit is set.

Clearing the Input Capture interrupt request (i.e. clearing the ICFi bit) is done in two steps:

1. Reading the SR register while the ICFi bit is set.

2. An access (read or write) to the ICiLR register.

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On-chip peripherals

ST72344xx, ST72345xx

The OC1R register value required for a specific timing application can be calculated using

the following formula:

t _*f_CPU

- 5

OCiR Value =

PRESC

Where:

●

t = Pulse period (in seconds)

f

= CPU clock frequency (in Hertz)

CPU

PRESC = Timer prescaler factor (2, 4 or 8 depending on the CC[1:0] bits, see Table 50:

Clock control bits)

If the timer clock is an external clock the formula is:

OCiR = t _*f_EXT-5

Where:

●

t = Pulse period (in seconds)

= External timer clock frequency (in Hertz)

●

f

EXT

When the value of the counter is equal to the value of the contents of the OC1R register, the

OLVL1 bit is output on the OCMP1 pin (See Figure 53).

Note:

1

2

The OCF1 bit cannot be set by hardware in One-pulse mode but the OCF2 bit can generate

an Output Compare interrupt.

When the Pulse Width Modulation (PWM) and One-pulse mode (OPM) bits are both set, the

PWM mode is the only active one.

3

4

If OLVL1=OLVL2 a continuous signal will be seen on the OCMP1 pin.

The ICAP1 pin can not be used to perform input capture. The ICAP2 pin can be used to

perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take

care that the counter is reset each time a valid edge occurs on the ICAP1 pin and ICF1 can

also generates interrupt if ICIE is set.

5

When One-pulse mode is used OC1R is dedicated to this mode. Nevertheless OC2R and

OCF2 can be used to indicate a period of time has been elapsed but cannot generate an

output waveform because the level OLVL2 is dedicated to the One-pulse mode.

Figure 53. One-pulse mode timing example

2ED3

01F8

IC1R

FFFC FFFD FFFE

2ED0 2ED1 2ED2

2ED3

FFFC FFFD

01F8

COUNTER

ICAP1

OLVL2

OLVL1

OLVL2

OCMP1

compare1

1. IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1.

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ST72344xx, ST72345xx

Figure 54. Pulse width modulation mode timing example

On-chip peripherals

2ED0 2ED1 2ED2

34E2 FFFC

FFFC FFFD FFFE

34E2

COUNTER

OCMP1

OLVL2

OLVL1

OLVL2

compare2

compare1

compare2

1. OC1R = 2ED0h, OC2R = 34E2, OLVL1 = 0, OLVL2 = 1

Pulse-width modulation mode

Pulse-width modulation (PWM) mode enables the generation of a signal with a frequency

and pulse length determined by the value of the OC1R and OC2R registers.

Pulse-width modulation mode uses the complete Output Compare 1 function plus the OC2R

register, and so this functionality can not be used when PWM mode is activated.

In PWM mode, double buffering is implemented on the output compare registers. Any new

values written in the OC1R and OC2R registers are loaded in their respective shadow

registers (double buffer) only at the end of the PWM period (OC2) to avoid spikes on the

PWM output pin (OCMP1). The shadow registers contain the reference values for

comparison in PWM “double buffering” mode.

Note:

There is a locking mechanism for transferring the OCiR value to the buffer. After a write to

the OCiHR register, transfer of the new compare value to the buffer is inhibited until OCiLR

is also written.

Unlike in Output Compare mode, the compare function is always enabled in PWM mode.

Procedure:

To use pulse-width modulation mode:

1. Load the OC2R register with the value corresponding to the period of the signal using

the formula in the opposite column.

2. Load the OC1R register with the value corresponding to the period of the pulse if

(OLVL1=0 and OLVL2=1) using the formula in the opposite column.

3. Select the following in the CR1 register:

–

Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after a

successful comparison with OC1R register.

–

Using the OLVL2 bit, select the level to be applied to the OCMP1 pin after a

successful comparison with OC2R register.

4. Select the following in the CR2 register:

–

Set OC1E bit: the OCMP1 pin is then dedicated to the output compare 1 function.

Set the PWM bit.

Select the timer clock (CC[1:0]) (see Table 50: Clock control bits).

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On-chip peripherals

Figure 55. Pulse width modulation cycle

Pulse-width modulation cycle

ST72344xx, ST72345xx

When

Counter

= OC1R

OCMP1 = OLVL1

OCMP1 = OLVL2

When

Counter

= OC2R

Counter is reset

to FFFCh

ICF1 bit is set

If OLVL1=1 and OLVL2=0 the length of the positive pulse is the difference between the

OC2R and OC1R registers.

If OLVL1=OLVL2 a continuous signal will be seen on the OCMP1 pin.

The OCⁱR register value required for a specific timing application can be calculated using

the following formula:

t _*f_CPU

- 5

OCiR Value =

PRESC

Where:

●

t = Signal or pulse period (in seconds)

= CPU clock frequency (in Hertz)

f

CPU

PRESC = Timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits, see Table 50:

Clock control bits)

If the timer clock is an external clock the formula is:

OCiR = t _*f_EXT-5

Where:

●

t = Signal or pulse period (in seconds)

= External timer clock frequency (in Hertz)

●

f

EXT

The Output Compare 2 event causes the counter to be initialized to FFFCh (See Figure 54)

Note:

1

2

3

The OCF1 and OCF2 bits cannot be set by hardware in PWM mode therefore the Output

Compare interrupt is inhibited.

The ICF1 bit is set by hardware when the counter reaches the OC2R value and can produce

a timer interrupt if the ICIE bit is set and the I bit is cleared.

In PWM mode the ICAP1 pin can not be used to perform input capture because it is

disconnected to the timer. The ICAP2 pin can be used to perform input capture (ICF2 can be

set and IC2R can be loaded) but the user must take care that the counter is reset each

period and ICF1 can also generate interrupt if ICIE is set.

4

When the pulse-width modulation (PWM) and One-pulse mode (OPM) bits are both set, the

PWM mode is the only active one.

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On-chip peripherals

11.3.4

Low-power modes

Table 47. Low-power mode description

Mode

Description

No effect on 16-bit timer.

Wait

Timer interrupts cause the Device to exit from Wait mode.

16-bit timer registers are frozen.

In Halt mode, the counter stops counting until Halt mode is exited. Counting resumes from

the previous count when the Device is woken up by an interrupt with “exit from Halt mode”

capability or from the counter reset value when the Device is woken up by a reset.

Halt

If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is

armed. Consequently, when the Device is woken up by an interrupt with “exit from Halt

mode” capability, the ICFi bit is set, and the counter value present when exiting from Halt

mode is captured into the ICiR register.

11.3.5

Interrupts

Table 48. Interrupt events

Interrupt event

Event

flag

Enable Exit from Exitfrom

control bit

Wait

Halt

Input Capture 1 event/Counter reset in PWM mode

Input Capture 2 event

ICF1

ICF2

Yes

No

ICIE

Output Compare 1 event (not available in PWM mode) OCF1

Output Compare 2 event (not available in PWM mode) OCF2

OCIE

TOIE

Timer overflow event

TOF

Note:

The 16-bit timer interrupt events are connected to the same interrupt vector (see Interrupts

chapter). These events generate an interrupt if the corresponding Enable Control Bit is set

and the interrupt mask in the CC register is reset (RIM instruction).

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On-chip peripherals

ST72344xx, ST72345xx

11.3.6

Summary of timer modes

Table 49. Timer modes

Available resources

Modes

Input Capture 1

Input Capture 2

Output Compare 1 Output Compare 2

Input Capture (1 and/or 2)

Output Compare (1 and/or 2)

One-pulse mode

Yes

No

Yes

No

Yes

Not recommended ⁽¹⁾

Not recommended ⁽³⁾

Partially ⁽²⁾

PWM mode

No

1. See note 4 in One-pulse mode on page 103

2. See note 5 in One-pulse mode on page 103

3. See note 4 in : Pulse-width modulation mode on page 105

11.3.7

Register description

Each timer is associated with three control and status registers, and with six pairs of data

registers (16-bit values) relating to the two input captures, the two output compares, the

counter and the alternate counter.

Control register 1 (CR1)

Read/Write

Reset value: 0000 0000 (00h)

7

0

ICIE

OCIE

TOIE

FOLV2

FOLV1

OLVL2

IEDG1

OLVL1

Read/Write

Bit 7 = ICIE Input Capture Interrupt Enable.

0: Interrupt is inhibited.

1: A timer interrupt is generated whenever the ICF1 or ICF2 bit of the SR register is set.

Bit 6 = OCIE Output Compare Interrupt Enable.

0: Interrupt is inhibited.

1: A timer interrupt is generated whenever the OCF1 or OCF2 bit of the SR register is

set.

Bit 5 = TOIE Timer Overflow Interrupt Enable.

0: Interrupt is inhibited.

1: A timer interrupt is enabled whenever the TOF bit of the SR register is set.

Bit 4 = FOLV2 Forced Output Compare 2.

This bit is set and cleared by software.

0: No effect on the OCMP2 pin.

1:Forces the OLVL2 bit to be copied to the OCMP2 pin, if the OC2E bit is set and even

if there is no successful comparison.

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ST72344xx, ST72345xx

Bit 3 = FOLV1 Forced Output Compare 1.

On-chip peripherals

This bit is set and cleared by software.

0: No effect on the OCMP1 pin.

1: Forces OLVL1 to be copied to the OCMP1 pin, if the OC1E bit is set and even if there

is no successful comparison.

Bit 2 = OLVL2 Output Level 2.

This bit is copied to the OCMP2 pin whenever a successful comparison occurs with the

OC2R register and OCxE is set in the CR2 register. This value is copied to the OCMP1

pin in One-pulse mode and Pulse-width modulation mode.

Bit 1 = IEDG1 Input Edge 1.

This bit determines which type of level transition on the ICAP1 pin will trigger the

capture.

0: A falling edge triggers the capture.

1: A rising edge triggers the capture.

Bit 0 = OLVL1 Output Level 1.

The OLVL1 bit is copied to the OCMP1 pin whenever a successful comparison occurs

with the OC1R register and the OC1E bit is set in the CR2 register.

Control register 2 (CR2)

Reset value: 0000 0000 (00h)

7

0

OC1E

OC2E

OPM

PWM

Read/Write

Bit 7 = OC1E Output Compare 1 Pin Enable.

CC1

CC0

IEDG2

EXEDG

This bit is used only to output the signal from the timer on the OCMP1 pin (OLV1 in

Output Compare mode, both OLV1 and OLV2 in PWM and one-pulse mode). Whatever

the value of the OC1E bit, the Output Compare 1 function of the timer remains active.

0: OCMP1 pin alternate function disabled (I/O pin free for general-purpose I/O).

1: OCMP1 pin alternate function enabled.

Bit 6 = OC2E Output Compare 2 Pin Enable.

This bit is used only to output the signal from the timer on the OCMP2 pin (OLV2 in

Output Compare mode). Whatever the value of the OC2E bit, the Output Compare 2

function of the timer remains active.

0: OCMP2 pin alternate function disabled (I/O pin free for general-purpose I/O).

1: OCMP2 pin alternate function enabled.

Bit 5 = OPM One-pulse Mode.

0: One-pulse Mode is not active.

1: One-pulse Mode is active, the ICAP1 pin can be used to trigger one pulse on the

OCMP1 pin; the active transition is given by the IEDG1 bit. The length of the generated

pulse depends on the contents of the OC1R register.

Bit 4 = PWM Pulse-Width Modulation.

0: PWM mode is not active.

1: PWM mode is active, the OCMP1 pin outputs a programmable cyclic signal; the

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length of the pulse depends on the value of OC1R register; the period depends on the

value of OC2R register.

Bits 3:2 = CC[1:0] Clock Control.

The timer clock mode depends on these bits:

Table 50. Clock control bits

Timer clock

CC1

CC0

f

_CPU/ 4

_CPU/ 2

_CPU/ 8

0

1

0

1

0

1

External clock (where available)

Note:

If the external clock pin is not available, programming the external clock configuration stops

the counter.

Bit 1 = IEDG2 Input Edge 2.

This bit determines which type of level transition on the ICAP2 pin will trigger the

capture.

0: A falling edge triggers the capture.

1: A rising edge triggers the capture.

Bit 0 = EXEDG External Clock Edge.

This bit determines which type of level transition on the external clock pin EXTCLK will

trigger the counter register.

0: A falling edge triggers the counter register.

1: A rising edge triggers the counter register.

Control/status register (CSR)

Reset value: 0000 0000 (00h)

The three least significant bits are not used.

7

0

ICF1

OCF1

TOF

ICF2

OCF2

TIMD

0

Read-only

Bit 7 = ICF1 Input Capture Flag 1.

0: No input capture (reset value).

1: An input capture has occurred on the ICAP1 pin or the counter has reached the

OC2R value in PWM mode. To clear this bit, first read the SR register, then read or

write the low byte of the IC1R (IC1LR) register.

Bit 6 = OCF1 Output Compare Flag 1.

0: No match (reset value).

1: The content of the free running counter has matched the content of the OC1R

register. To clear this bit, first read the SR register, then read or write the low byte of the

OC1R (OC1LR) register.

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On-chip peripherals

Bit 5 = TOF Timer Overflow Flag.

0: No timer overflow (reset value).

1: The free running counter rolled over from FFFFh to 0000h. To clear this bit, first read

the SR register, then read or write the low byte of the CR (CLR) register.

Note:

Reading or writing the ACLR register does not clear TOF.

Bit 4 = ICF2 Input Capture Flag 2.

0: No input capture (reset value).

1: An input capture has occurred on the ICAP2 pin. To clear this bit, first read the SR

register, then read or write the low byte of the IC2R (IC2LR) register.

Bit 3 = OCF2 Output Compare Flag 2.

0: No match (reset value).

1: The content of the free running counter has matched the content of the OC2R

register. To clear this bit, first read the SR register, then read or write the low byte of the

OC2R (OC2LR) register.

Bit 2 = TIMD Timer disable.

This bit is set and cleared by software. When set, it freezes the timer prescaler and

counter and disabled the output functions (OCMP1 and OCMP2 pins) to reduce power

consumption. Access to the timer registers is still available, allowing the timer

configuration to be changed while it is disabled.

0: Timer enabled

1: Timer prescaler, counter and outputs disabled

Bits 1:0 = Reserved, must be kept cleared.

Input capture 1 high register (IC1HR)

Reset value: Undefined

This is an 8-bit read-only register that contains the high part of the counter value (transferred

by the input capture 1 event).

7

0

MSB

LSB

Read Only

Input capture 1 low register (IC1LR)

Reset value: Undefined

This is an 8-bit read only register that contains the low part of the counter value (transferred

by the input capture 1 event).

7

0

MSB

LSB

Read Only

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ST72344xx, ST72345xx

Output compare 1 high register (OC1HR)

Read/Write

Reset value: 1000 0000 (80h)

This is an 8-bit register that contains the high part of the value to be compared to the CHR

register.

7

0

MSB

LSB

Read/Write

Output compare 1 low register (OC1LR)

Reset value: 0000 0000 (00h)

This is an 8-bit register that contains the low part of the value to be compared to the CLR

register.

7

0

MSB

LSB

Read/Write

Output compare 2 high register (OC2HR)

Reset value: 1000 0000 (80h)

This is an 8-bit register that contains the high part of the value to be compared to the CHR

register.

7

0

MSB

LSB

Read/Write

Output compare 2 low register (OC2LR)

Reset value: 0000 0000 (00h)

This is an 8-bit register that contains the low part of the value to be compared to the CLR

register.

7

0

MSB

LSB

Read/Write

Counter high register (CHR)

Reset value: 1111 1111 (FFh)

This is an 8-bit register that contains the high part of the counter value.

7

0

MSB

LSB

Read-only

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On-chip peripherals

Counter low register (CLR)

Reset value: 1111 1100 (FCh)

This is an 8-bit register that contains the low part of the counter value. A write to this register

resets the counter. An access to this register after accessing the CSR register clears the

TOF bit.

7

0

MSB

LSB

Read-only

Alternate counter high register (ACHR)

Reset value: 1111 1111 (FFh)

This is an 8-bit register that contains the high part of the counter value.

7

0

MSB

LSB

Read-only

Alternate counter low register (ACLR)

Reset value: 1111 1100 (FCh)

This is an 8-bit register that contains the low part of the counter value. A write to this register

resets the counter. An access to this register after an access to CSR register does not clear

the TOF bit in the CSR register.

7

0

MSB

LSB

Read-only

Input capture 2 high register (IC2HR)

Reset value: Undefined

This is an 8-bit read only register that contains the high part of the counter value (transferred

by the Input Capture 2 event).

7

0

MSB

LSB

Read-only

Input capture 2 low register (IC2LR)

Reset value: Undefined

This is an 8-bit read only register that contains the low part of the counter value (transferred

by the Input Capture 2 event).

7

0

MSB

LSB

Read-only

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ST72344xx, ST72345xx

Table 51. 16-bit timer register map and reset values

Address

(Hex.)

Register

label

7

6

5

4

3

2

1

0

Timer A: 32 CR1

Timer B: 42 Reset value 0

ICIE

OCIE

0

TOIE

0

FOLV2 FOLV1 OLVL2 IEDG1 OLVL1

0

Timer A: 31 CR2

OC1E OC2E OPM

Timer B: 41 Reset value 0

PWM

0

CC1

0

CC0

0

IEDG2 EXEDG

0

Timer A: 33 CSR

Timer B: 43 Reset value x

ICF1

OCF1 TOF

ICF2

x

OCF2 TIMD

-

x

-

x

0

1

x

0

1

x

0

1

0

x

0

1

Timer A: 34 IC1HR

Timer B: 44 Reset value x

MSB

LSB

x

0

1

x

0

1

0

Timer A: 35 IC1LR

Timer B: 45 Reset value x

MSB

LSB

x

Timer A: 36 OC1HR

Timer B: 46 Reset value 1

MSB

LSB

0

Timer A: 37 OC1LR

Timer B: 47 Reset value 0

MSB

LSB

0

Timer A: 3E OC2HR

Timer B: 4E Reset value 1

MSB

LSB

0

Timer A: 3F OC2LR

Timer B: 4F Reset value 0

MSB

LSB

0

Timer A: 38 CHR

Timer B: 48 Reset value 1

MSB

LSB

1

Timer A: 39 CLR

Timer B: 49 Reset value 1

MSB

LSB

0

Timer A: 3A ACHR

Timer B: 4A Reset value 1

MSB

LSB

1

Timer A: 3B ACLR

Timer B: 4B Reset value 1

MSB

LSB

0

1

0

x

Timer A: 3C IC2HR

Timer B: 4C Reset value x

MSB

LSB

x

Timer A: 3D IC2LR

Timer B: 4D Reset value x

MSB

LSB

x

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On-chip peripherals

11.4

Serial peripheral interface (SPI)

11.4.1

Introduction

The serial peripheral interface (SPI) allows full-duplex, synchronous, serial communication

with external devices. An SPI system may consist of a master and one or more slaves or a

system in which devices may be either masters or slaves.

11.4.2

Main features

●

Full-duplex synchronous transfers (on three lines)

Simplex synchronous transfers (on two lines)

Master or slave operation

6 master mode frequencies (f

/4 max.)

CPU

f

/2 max. slave mode frequency (see note)

CPU

SS Management by software or hardware

Programmable clock polarity and phase

End-of-transfer interrupt flag

Write collision, master mode fault and Overrun flags

Note:

In slave mode, continuous transmission is not possible at maximum frequency due to the

software overhead for clearing status flags and to initiate the next transmission sequence.

11.4.3

General description

Figure 56 on page 116 shows the serial peripheral interface (SPI) block diagram. There are

three registers:

●

SPI Control Register (SPICR)

SPI Control/Status Register (SPICSR)

SPI Data Register (SPIDR)

The SPI is connected to external devices through four pins:

●

MISO: Master In / Slave Out data

MOSI: Master Out / Slave In data

SCK: Serial Clock out by SPI masters and input by SPI slaves

SS: Slave select:

This input signal acts as a ‘chip select’ to let the SPI master communicate with slaves

individually and to avoid contention on the data lines. Slave SS inputs can be driven by

standard I/O ports on the master Device.

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On-chip peripherals

Figure 56. Serial peripheral interface block diagram

ST72344xx, ST72345xx

Data/Address Bus

Read

SPIDR

Interrupt

request

Read Buffer

MOSI

MISO

7

0

SPICSR

8-bit Shift Register

SPIF WCOL OVR MODF

0

SOD SSM SSI

Write

SOD

bit

1

SS

SPI

STATE

0

SCK

CONTROL

7

0

SPICR

MSTR

SPR0

SPIE SPE SPR2

CPOL CPHA SPR1

MASTER

CONTROL

SERIAL CLOCK

GENERATOR

SS

Functional description

A basic example of interconnections between a single master and a single slave is

illustrated in Figure 57.

The MOSI pins are connected together and the MISO pins are connected together. In this

way data is transferred serially between master and slave (most significant bit first).

The communication is always initiated by the master. When the master device transmits

data to a slave device via MOSI pin, the slave device responds by sending data to the

master device via the MISO pin. This implies full duplex communication with both data out

and data in synchronized with the same clock signal (which is provided by the master device

via the SCK pin).

To use a single data line, the MISO and MOSI pins must be connected at each node (in this

case only simplex communication is possible).

Four possible data/clock timing relationships may be chosen (see Figure 60 on page 121)

but master and slave must be programmed with the same timing mode.

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ST72344xx, ST72345xx

Figure 57. Single master/ single slave application

On-chip peripherals

SLAVE

MASTER

MSBit

LSBit

MSBit

LSBit

MISO

MOSI

MISO

MOSI

8-bit SHIFT REGISTER

SPI

CLOCK

GENERATOR

SCK

SS

SCK

SS

+5V

Not used if SS is managed

by software

Slave select management

As an alternative to using the SS pin to control the Slave Select signal, the application can

choose to manage the Slave Select signal by software. This is configured by the SSM bit in

the SPICSR register (see Figure 59).

In software management, the external SS pin is free for other application uses and the

internal SS signal level is driven by writing to the SSI bit in the SPICSR register.

●

In Master mode:

–

SS internal must be held high continuously

●

In Slave Mode:

There are two cases depending on the data/clock timing relationship (see Figure 58):

If CPHA = 1 (data latched on second clock edge):

–

SS internal must be held low during the entire transmission. This implies that in

single slave applications the SS pin either can be tied to V , or made free for

SS

standard I/O by managing the SS function by software (SSM = 1 and SSI = 0 in

the in the SPICSR register)

If CPHA = 0 (data latched on first clock edge):

–

SS internal must be held low during byte transmission and pulled high between

each byte to allow the slave to write to the shift register. If SS is not pulled high, a

Write Collision error will occur when the slave writes to the shift register (see Write

collision error (WCOL) on page 122).

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On-chip peripherals

Figure 58. Generic SS timing diagram

ST72344xx, ST72345xx

Byte 3

Byte 1

Byte 2

MOSI/MISO

Master SS

Slave SS

(if CPHA = 0)

Figure 59. Hardware/software slave select management

SSM bit

SSI bit

1

0

SS internal

SS external pin

Master mode operation

In master mode, the serial clock is output on the SCK pin. The clock frequency, polarity and

phase are configured by software (refer to the description of the SPICSR register).

Note:

The idle state of SCK must correspond to the polarity selected in the SPICSR register (by

pulling up SCK if CPOL = 1 or pulling down SCK if CPOL = 0).

How to operate the SPI in master mode

To operate the SPI in master mode, perform the following steps in order:

1. Write to the SPICR register:

–

Select the clock frequency by configuring the SPR[2:0] bits.

Select the clock polarity and clock phase by configuring the CPOL and CPHA bits.

Figure 60 shows the four possible configurations.

Note that the slave must have the same CPOL and CPHA settings as the master.

2. Write to the SPICSR register:

Either set the SSM bit and set the SSI bit or clear the SSM bit and tie the SS pin

high for the complete byte transmit sequence.

3. Write to the SPICR register:

–

Set the MSTR and SPE bits

Note that the MSTR and SPE bits remain set only if SS is high).

Note:

Important: if the SPICSR register is not written first, the SPICR register setting (MSTR bit)

may be not taken into account.

The transmit sequence begins when software writes a byte in the SPIDR register.

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ST72344xx, ST72345xx

On-chip peripherals

Master mode transmit sequence

When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift

register and then shifted out serially to the MOSI pin most significant bit first.

When data transfer is complete:

●

The SPIF bit is set by hardware.

●

An interrupt request is generated if the SPIE bit is set and the interrupt mask in the

CCR register is cleared.

Clearing the SPIF bit is performed by the following software sequence:

1. An access to the SPICSR register while the SPIF bit is set

2. A read to the SPIDR register

Note:

While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR

register is read.

Slave mode operation

In slave mode, the serial clock is received on the SCK pin from the master device.

To operate the SPI in slave mode:

1. Write to the SPICSR register to perform the following actions:

–

Select the clock polarity and clock phase by configuring the CPOL and CPHA bits

(see Figure 60).

Note that the slave must have the same CPOL and CPHA settings as the master.

–

Manage the SS pin as described in Slave select management on page 117 and

Figure 58. If CPHA = 1 SS must be held low continuously. If CPHA = 0 SS must be

held low during byte transmission and pulled up between each byte to let the slave

write in the shift register.

2. Write to the SPICR register to clear the MSTR bit and set the SPE bit to enable the SPI

I/O functions.

Slave mode transmit sequence

When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift

register and then shifted out serially to the MISO pin most significant bit first.

The transmit sequence begins when the slave device receives the clock signal and the most

significant bit of the data on its MOSI pin.

When data transfer is complete:

●

The SPIF bit is set by hardware.

●

An interrupt request is generated if SPIE bit is set and interrupt mask in the CCR

register is cleared.

Clearing the SPIF bit is performed by the following software sequence:

1. An access to the SPICSR register while the SPIF bit is set

2. A write or a read to the SPIDR register

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On-chip peripherals

ST72344xx, ST72345xx

Note:

While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR

register is read.

The SPIF bit can be cleared during a second transmission; however, it must be cleared

before the second SPIF bit in order to prevent an Overrun condition (see Overrun condition

(OVR) on page 122).

11.4.4

Clock phase and clock polarity

Four possible timing relationships may be chosen by software, using the CPOL and CPHA

bits (See Figure 60).

Note:

The idle state of SCK must correspond to the polarity selected in the SPICSR register (by

pulling up SCK if CPOL = 1 or pulling down SCK if CPOL = 0).

The combination of the CPOL clock polarity and CPHA (clock phase) bits selects the data

capture clock edge.

Figure 60 shows an SPI transfer with the four combinations of the CPHA and CPOL bits.

The diagram may be interpreted as a master or slave timing diagram where the SCK pin, the

MISO pin and the MOSI pin are directly connected between the master and the slave

device.

Note:

If CPOL is changed at the communication byte boundaries, the SPI must be disabled by

resetting the SPE bit.

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ST72344xx, ST72345xx

Figure 60. Data clock timing diagram

On-chip peripherals

CPHA = 1

SCK

(CPOL = 1)

SCK

(CPOL = 0)

Bit 4

Bit3

Bit 2

Bit 1

LSBit

MSBit

Bit 6

Bit 5

MISO

(from master)

Bit 1

MOSI

(from slave)

SS

(to slave)

CAPTURE STROBE

CPHA = 0

SCK

(CPOL = 1)

SCK

(CPOL = 0)

Bit 4

Bit3

Bit 2

Bit 1

LSBit

MISO

(from master)

MSBit

Bit 6

Bit 5

MOSI

(from slave)

MSBit

SS

(to slave)

CAPTURE STROBE

1. This figure should not be used as a replacement for parametric information. Refer to the Electrical

Characteristics chapter.

11.4.5

Error flags

Master mode fault (MODF)

Master mode fault occurs when the master device’s SS pin is pulled low.

When a Master mode fault occurs:

●

The MODF bit is set and an SPI interrupt request is generated if the SPIE bit is set.

●

The SPE bit is reset. This blocks all output from the device and disables the SPI

peripheral.

●

The MSTR bit is reset, thus forcing the device into slave mode.

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On-chip peripherals

Clearing the MODF bit is done through a software sequence:

ST72344xx, ST72345xx

1. A read access to the SPICSR register while the MODF bit is set.

2. A write to the SPICR register.

Notes: To avoid any conflicts in an application with multiple slaves, the SS pin must be

pulled high during the MODF bit clearing sequence. The SPE and MSTR bits may be

restored to their original state during or after this clearing sequence.

Hardware does not allow the user to set the SPE and MSTR bits while the MODF bit is set

except in the MODF bit clearing sequence.

In a slave device, the MODF bit can not be set, but in a multimaster configuration the device

can be in slave mode with the MODF bit set.

The MODF bit indicates that there might have been a multimaster conflict and allows

software to handle this using an interrupt routine and either perform a reset or return to an

application default state.

Overrun condition (OVR)

An overrun condition occurs when the master device has sent a data byte and the slave

device has not cleared the SPIF bit issued from the previously transmitted byte.

When an Overrun occurs:

●

The OVR bit is set and an interrupt request is generated if the SPIE bit is set.

In this case, the receiver buffer contains the byte sent after the SPIF bit was last cleared. A

read to the SPIDR register returns this byte. All other bytes are lost.

The OVR bit is cleared by reading the SPICSR register.

Write collision error (WCOL)

A write collision occurs when the software tries to write to the SPIDR register while a data

transfer is taking place with an external device. When this happens, the transfer continues

uninterrupted and the software write will be unsuccessful.

Write collisions can occur both in master and slave mode. See also Slave select

management on page 117.

Note:

A “read collision” will never occur since the received data byte is placed in a buffer in which

access is always synchronous with the CPU operation.

The WCOL bit in the SPICSR register is set if a write collision occurs.

No SPI interrupt is generated when the WCOL bit is set (the WCOL bit is a status flag only).

Clearing the WCOL bit is done through a software sequence (see Figure 61).

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ST72344xx, ST72345xx

On-chip peripherals

Figure 61. Clearing the WCOL bit (write collision flag) software sequence

Clearing sequence after SPIF = 1 (end of a data byte transfer)

Read SPICSR

1st Step

RESULT

SPIF = 0

WCOL = 0

2nd Step

Read SPIDR

Clearing sequence before SPIF = 1 (during a data byte transfer)

Read SPICSR

1st Step

RESULT

2nd Step

Read SPIDR

WCOL = 0

1. Writing to the SPIDR register instead of reading it does not reset the WCOL bit.

Single master and multimaster configurations

There are two types of SPI systems: Single master system and Multimaster system.

●

Single master system

A typical single master system may be configured using a device as the master and

four devices as slaves (see Figure 62).

The master device selects the individual slave devices by using four pins of a parallel

port to control the four SS pins of the slave devices.

The SS pins are pulled high during reset since the master device ports will be forced to

be inputs at that time, thus disabling the slave devices.

Note: To prevent a bus conflict on the MISO line, the master allows only one active

slave device during a transmission.

For more security, the slave device may respond to the master with the received data

byte. Then the master will receive the previous byte back from the slave device if all

MISO and MOSI pins are connected and the slave has not written to its SPIDR register.

Other transmission security methods can use ports for handshake lines or data bytes

with command fields.

●

Multimaster system

A multimaster system may also be configured by the user. Transfer of master control

could be implemented using a handshake method through the I/O ports or by an

exchange of code messages through the serial peripheral interface system.

The multimaster system is principally handled by the MSTR bit in the SPICR register

and the MODF bit in the SPICSR register.

123/246

On-chip peripherals

ST72344xx, ST72345xx

Figure 62. Single master / multiple slave configuration

SS

SCK

Slave

Device

SCK

Slave

SCK

Slave

Device

SCK

Slave

Device

MOSI MISO

SCK

Master

Device

5V

SS

11.4.6

Low-power modes

Table 52. Description

Mode

Description

No effect on SPI.

Wait

SPI interrupt events cause the device to exit from Wait mode.

SPI registers are frozen.

In Halt mode, the SPI is inactive. SPI operation resumes when the device is woken up by

an interrupt with “exit from Halt mode” capability. The data received is subsequently read

from the SPIDR register when the software is running (interrupt vector fetching). If several

data are received before the wake-up event, then an overrun error is generated. This error

can be detected after the fetch of the interrupt routine that woke up the Device.

Halt

Using the SPI to wake up the device from Halt mode

In slave configuration, the SPI is able to wake up the device from Halt mode through a SPIF

interrupt. The data received is subsequently read from the SPIDR register when the

software is running (interrupt vector fetch). If multiple data transfers have been performed

before software clears the SPIF bit, then the OVR bit is set by hardware.

Note:

When waking up from Halt mode, if the SPI remains in Slave mode, it is recommended to

perform an extra communications cycle to bring the SPI from Halt mode state to normal

state. If the SPI exits from Slave mode, it returns to normal state immediately.

Caution:

The SPI can wake up the device from Halt mode only if the Slave Select signal (external SS

pin or the SSI bit in the SPICSR register) is low when the device enters Halt mode. So, if

Slave selection is configured as external (see Slave select management), make sure the

master drives a low level on the SS pin when the slave enters Halt mode.

124/246

ST72344xx, ST72345xx

On-chip peripherals

11.4.7

Interrupts

Table 53. Interrupt events

Interrupt event

Enable control

bit

Event flag

Exit from Wait Exit from Halt

SPI end of transfer event

Master mode fault event

Overrun error

SPIF

MODF

OVR

Yes

SPIE

Yes

No

Note:

The SPI interrupt events are connected to the same interrupt vector (see Interrupts chapter).

They generate an interrupt if the corresponding Enable Control Bit is set and the interrupt

mask in the CC register is reset (RIM instruction).

11.4.8

Register description

SPI control register (SPICR)

Reset value: 0000 xxxx (0xh)

7

0

SPIE

SPE

SPR2

MSTR

CPOL

CPHA

SPR1

SPR0

Read/Write

Bit 7 = SPIE Serial Peripheral Interrupt Enable

This bit is set and cleared by software.

0: Interrupt is inhibited

1: An SPI interrupt is generated whenever an End of Transfer event, Master Mode Fault

or Overrun error occurs (SPIF = 1, MODF = 1 or OVR = 1 in the SPICSR register)

Bit 6 = SPE Serial Peripheral Output Enable

This bit is set and cleared by software. It is also cleared by hardware when, in master

mode, SS = 0 (see Master mode fault (MODF) on page 121). The SPE bit is cleared by

reset, so the SPI peripheral is not initially connected to the external pins.

0: I/O pins free for general purpose I/O

1: SPI I/O pin alternate functions enabled

Bit 5 = SPR2 Divider Enable

This bit is set and cleared by software and is cleared by reset. It is used with the

SPR[1:0] bits to set the baud rate. Refer to Table 54: SPI master mode SCK frequency.

0: Divider by 2 enabled

1: Divider by 2 disabled

Note:

This bit has no effect in slave mode.

Bit 4 = MSTR Master Mode

This bit is set and cleared by software. It is also cleared by hardware when, in master

mode, SS = 0 (see Master mode fault (MODF) on page 121).

0: Slave mode

1: Master mode. The function of the SCK pin changes from an input to an output and

the functions of the MISO and MOSI pins are reversed.

125/246

On-chip peripherals

Bit 3 = CPOL Clock Polarity

ST72344xx, ST72345xx

This bit is set and cleared by software. This bit determines the idle state of the serial

Clock. The CPOL bit affects both the master and slave modes.

0: SCK pin has a low level idle state

1: SCK pin has a high level idle state

Note:

If CPOL is changed at the communication byte boundaries, the SPI must be disabled by

resetting the SPE bit.

Bit 2 = CPHA Clock Phase

This bit is set and cleared by software.

0: The first clock transition is the first data capture edge.

1: The second clock transition is the first capture edge.

Note:

The slave must have the same CPOL and CPHA settings as the master.

Bits 1:0 = SPR[1:0] Serial clock frequency

These bits are set and cleared by software. Used with the SPR2 bit, they select the

baud rate of the SPI serial clock SCK output by the SPI in master mode.

These 2 bits have no effect in slave mode.

Table 54. SPI master mode SCK frequency

Serial clock

_CPU/4

SPR2

SPR1

SPR0

f

1

0

1

0

1

f_CPU/8

0

1

0

f_CPU/16

f

_CPU/32

f_CPU/64

1

f_CPU/128

SPI control/status register (SPICSR)

Reset value: 0000 0000 (00h)

7

0

SPIF

WCOL

OVR

MODF

-

SOD

SSM

SSI

Read-only

Reserved

Read/Write

Bit 7 = SPIF Serial Peripheral Data Transfer Flag (Read-only)

This bit is set by hardware when a transfer has been completed. An interrupt is

generated if SPIE = 1 in the SPICR register. It is cleared by a software sequence (an

access to the SPICSR register followed by a write or a read to the SPIDR register).

0: Data transfer is in progress or the flag has been cleared.

1: Data transfer between the device and an external device has been completed.

Note:

While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR

register is read.

126/246

ST72344xx, ST72345xx

Bit 6 = WCOL Write collision status (Read-only)

On-chip peripherals

This bit is set by hardware when a write to the SPIDR register is done during a transmit

sequence. It is cleared by a software sequence (see Figure 61).

0: No write collision occurred

1: A write collision has been detected

Bit 5 = OVR SPI overrun error (Read-only)

This bit is set by hardware when the byte currently being received in the shift register is

ready to be transferred into the SPIDR register while SPIF = 1 (See Overrun condition

(OVR)). An interrupt is generated if SPIE = 1 in the SPICR register. The OVR bit is

cleared by software reading the SPICSR register.

0: No overrun error

1: Overrun error detected

Bit 4 = MODF Mode fault flag (Read-only)

This bit is set by hardware when the SS pin is pulled low in master mode (see Master

mode fault (MODF) on page 121). An SPI interrupt can be generated if SPIE = 1 in the

SPICR register. This bit is cleared by a software sequence (An access to the SPICSR

register while MODF = 1 followed by a write to the SPICR register).

0: No master mode fault detected

1: A fault in master mode has been detected

Bit 3 = Reserved, must be kept cleared.

Bit 2 = SOD SPI Output disable

This bit is set and cleared by software. When set, it disables the alternate function of

the SPI output (MOSI in master mode / MISO in slave mode)

0: SPI output enabled (if SPE = 1)

1: SPI output disabled

Bit 1 = SSM SS management

This bit is set and cleared by software. When set, it disables the alternate function of

the SPI SS pin and uses the SSI bit value instead. See Slave select management on

page 117.

0: Hardware management (SS managed by external pin)

1: Software management (internal SS signal controlled by SSI bit. External SS pin free

for general-purpose I/O)

Bit 0 = SSI SS internal mode

This bit is set and cleared by software. It acts as a ‘chip select’ by controlling the level of

the SS slave select signal when the SSM bit is set.

0: Slave selected

1: Slave deselected

127/246

On-chip peripherals

ST72344xx, ST72345xx

SPI data I/O register (SPIDR)

Reset value: Undefined

7

0

D7

D6

D5

D4

D3

D2

D1

D0

Read/Write

The SPIDR register is used to transmit and receive data on the serial bus. In a master

device, a write to this register will initiate transmission/reception of another byte.

Note:

During the last clock cycle the SPIF bit is set, a copy of the received data byte in the shift

register is moved to a buffer. When the user reads the serial peripheral data I/O register, the

buffer is actually being read.

While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR

register is read.

Warning: A write to the SPIDR register places data directly into the

shift register for transmission.

A read to the SPIDR register returns the value located in the buffer and not the content of

the shift register (see Figure 56).

Table 55. SPI register map and reset values

Address

(Hex.)

Register

label

7

6

5

4

3

2

1

0

SPIDR

Reset value

MSB

x

LSB

x

0021h

0022h

0023h

x

SPICR

Reset value

SPIE

0

SPE

0

SPR2

0

MSTR CPOL CPHA

SPR1

x

SPR0

x

0

x

SPICSR

Reset value

SPIF

0

WCOL OR

0

MODF

0

SOD

0

SSM

0

SSI

0

128/246

ST72344xx, ST72345xx

On-chip peripherals

11.5

SCI serial communication interface

11.5.1

Introduction

The serial communications interface (SCI) offers a flexible means of full-duplex data

exchange with external equipment requiring an industry standard NRZ asynchronous serial

data format. The SCI offers a very wide range of baud rates using two baud rate generator

systems.

11.5.2

Main features

●

Full-duplex, asynchronous communications

NRZ standard format (Mark/Space)

Dual baud rate generator systems

Independently programmable transmit and receive baud rates up to 500K baud

Programmable data word length (8 or 9 bits)

Receive buffer full, Transmit buffer empty and End of Transmission flags

2 receiver wake-up modes:

–

Address bit (MSB)

Idle line

●

Muting function for multiprocessor configurations

Separate enable bits for Transmitter and Receiver

4 error detection flags:

–

Overrun error

Noise error

Frame error

Parity error

●

5 interrupt sources with flags:

–

Transmit data register empty

Transmission complete

Receive data register full

Idle line received

Overrun error detected

●

Parity control:

–

Transmits parity bit

Checks parity of received data byte

Reduced power consumption mode

11.5.3

General description

The interface is externally connected to another device by three pins (see Figure 63). Any

SCI bidirectional communication requires a minimum of two pins: Receive Data In (RDI) and

Transmit Data Out (TDO):

●

SCLK: Transmitter clock output. This pin outputs the transmitter data clock for

synchronous transmission (no clock pulses on start bit and stop bit, and a software

option to send a clock pulse on the last data bit). This can be used to control

129/246

On-chip peripherals

ST72344xx, ST72345xx

peripherals that have shift registers (e.g. LCD drivers). The clock phase and polarity

are software programmable.

●

TDO: Transmit Data Output. When the transmitter is disabled, the output pin returns to

its I/O port configuration. When the transmitter is enabled and nothing is to be

transmitted, the TDO pin is at high level.

RDI: Receive Data Input is the serial data input. Oversampling techniques are used for

data recovery by discriminating between valid incoming data and noise.

Through these pins, serial data is transmitted and received as frames comprising:

●

An Idle Line prior to transmission or reception

A start bit

A data word (8 or 9 bits) least significant bit first

A Stop bit indicating that the frame is complete.

This interface uses two types of baud rate generator:

●

A conventional type for commonly-used baud rates,

●

An extended type with a prescaler offering a very wide range of baud rates even with

non-standard oscillator frequencies.

130/246

ST72344xx, ST72345xx

Figure 63. SCI block diagram

On-chip peripherals

Write

Read

(DATA REGISTER) SCIDR

Receive Data Register (RDR)

Receive Shift Register

Transmit Data Register (TDR)

TDO

RDI

Transmit Shift Register

R8

T8 SCID

M

WAKE PCE PS PIE

SCICR1

WAKE

UP

TRANSMIT

CONTROL

RECEIVER

CLOCK

RECEIVER

CONTROL

UNIT

SCISR

SCICR2

TDRE TC RDRF IDLE OR NF FE

PE

TIE TCIE RIE ILIE TE RE RWU SBK

SCI

INTERRUPT

CONTROL

TRANSMITTER

CLOCK

TRANSMITTER RATE

CONTROL

f

CPU

/PR

/16

SCIBRR

SCP1

SCT2

SCT1SCT0SCR2 SCR1SCR0

SCP0

RECEIVER RATE

CONTROL

CONVENTIONAL BAUD RATE GENERATOR

131/246

On-chip peripherals

ST72344xx, ST72345xx

11.5.4

Functional description

The block diagram of the Serial Control Interface, is shown in Figure 63. It contains six

dedicated registers:

●

2 control registers (SCICR1 and SCICR2)

A status register (SCISR)

A baud rate register (SCIBRR)

An extended prescaler receiver register

(SCIERPR)

●

An extended prescaler transmitter register

(SCIETPR)

Refer to the register descriptions in Section 11.5.7 for the definitions of each bit.

Serial data format

Word length may be selected as being either 8 or 9 bits by programming the M bit in the

SCICR1 register (see Figure 64).

The TDO pin is in low state during the start bit.

The TDO pin is in high state during the stop bit.

An Idle character is interpreted as an entire frame of “1”s followed by the start bit of the next

frame which contains data.

A Break character is interpreted on receiving “0”s for some multiple of the frame period. At

the end of the last break frame the transmitter inserts an extra “1” bit to acknowledge the

start bit.

Transmission and reception are driven by their own baud rate generator.

132/246

ST72344xx, ST72345xx

Figure 64. Word length programming

On-chip peripherals

9-bit (M bit is set)

Data Frame

Possible

Parity

Next Data Frame

Bit

Start

Bit

Stop

Bit

Bit2

Bit6

Bit3

Bit4

Bit5

Bit7

Bit8

Bit0 Bit1

CLOCK

(1)

Start

Bit

Idle Frame

Start

Bit

Extra

’1’

Break Frame

8-bit (M bit is reset)

Data Frame

Possible

Parity

Next Data Frame

Bit

Start

Bit

Stop

Bit

Bit2

Bit6

Bit0

Bit1

Bit3

Bit4

Bit5

Bit7

CLOCK

****

(1)

Start

Bit

Idle Frame

Start

Bit

Extra

’1’

Break Frame

1. LBCL bit controls last data clock pulse.

Transmitter

The transmitter can send data words of either 8 or 9 bits depending on the M bit status.

When the M bit is set, word length is 9 bits and the 9th bit (the MSB) has to be stored in the

T8 bit in the SCICR1 register.

When the transmit enable bit (TE) is set, the data in the transmit shift register is output on

the TDO pin.

133/246

On-chip peripherals

Character transmission

ST72344xx, ST72345xx

During an SCI transmission, data shifts out least significant bit first on the TDO pin. In

this mode, the SCIDR register consists of a buffer (TDR) between the internal bus and

the transmit shift register (see Figure 64).

Procedure:

–

Select the M bit to define the word length.

Select the desired baud rate using the SCIBRR and the SCIETPR registers.

Set the TE bit to send an idle frame as first transmission.

Access the SCISR register and write the data to send in the SCIDR register (this

sequence clears the TDRE bit). Repeat this sequence for each data to be

transmitted.

Clearing the TDRE bit is always performed by the following software sequence:

a) An access to the SCISR register

b) A write to the SCIDR register

The TDRE bit is set by hardware and it indicates:

–

The TDR register is empty.

The data transfer is beginning.

The next data can be written in the SCIDR register without overwriting the

previous data.

This flag generates an interrupt if the TIE bit is set and the I bit is cleared in the CCR

register.

When a transmission is taking place, a write instruction to the SCIDR register stores

the data in the TDR register and which is copied in the shift register at the end of the

current transmission.

When no transmission is taking place, a write instruction to the SCIDR register places

the data directly in the shift register, the data transmission starts, and the TDRE bit is

immediately set.

When a frame transmission is complete (after the stop bit or after the break frame) the

TC bit is set and an interrupt is generated if the TCIE is set and the I bit is cleared in the

CCR register.

Clearing the TC bit is performed by the following software sequence:

a) An access to the SCISR register

b) A write to the SCIDR register

Note:

The TDRE and TC bits are cleared by the same software sequence.

Break characters

Setting the SBK bit loads the shift register with a break character. The break frame

length depends on the M bit (see Figure 64).

As long as the SBK bit is set, the SCI send break frames to the TDO pin. After clearing

this bit by software the SCI insert a logic 1 bit at the end of the last break frame to

guarantee the recognition of the start bit of the next frame.

Idle characters

Setting the TE bit drives the SCI to send an idle frame before the first data frame.

Clearing and then setting the TE bit during a transmission sends an idle frame after the

current word.

134/246

ST72344xx, ST72345xx

Note:

On-chip peripherals

Resetting and setting the TE bit causes the data in the TDR register to be lost. Therefore the

best time to toggle the TE bit is when the TDRE bit is set, that is, before writing the next byte

in the SCIDR.

Receiver

The SCI can receive data words of either 8 or 9 bits. When the M bit is set, word length is 9

bits and the MSB is stored in the R8 bit in the SCICR1 register.

Character reception

During a SCI reception, data shifts in least significant bit first through the RDI pin. In

this mode, the SCIDR register consists or a buffer (RDR) between the internal bus and

the received shift register (see Figure 63).

Procedure:

–

Select the M bit to define the word length.

Select the desired baud rate using the SCIBRR and the SCIERPR registers.

Set the RE bit, this enables the receiver which begins searching for a start bit.

When a character is received:

–

The RDRF bit is set. It indicates that the content of the shift register is transferred

to the RDR.

An interrupt is generated if the RIE bit is set and the I bit is cleared in the CCR

register.

The error flags can be set if a frame error, noise or an overrun error has been

detected during reception.

Clearing the RDRF bit is performed by the following software sequence done by:

a) An access to the SCISR register

b) A read to the SCIDR register.

The RDRF bit must be cleared before the end of the reception of the next character to

avoid an overrun error.

Break character

When a break character is received, the SCI handles it as a framing error.

Idle character

When an idle frame is detected, there is the same procedure as a data received

character plus an interrupt if the ILIE bit is set and the I bit is cleared in the CCR

register.

135/246

On-chip peripherals

Overrun error

ST72344xx, ST72345xx

An overrun error occurs when a character is received when RDRF has not been reset.

Data cannot be transferred from the shift register to the RDR register until the RDRF bit

is cleared.

When a overrun error occurs:

–

The OR bit is set.

The RDR content is not lost.

The shift register is overwritten.

An interrupt is generated if the RIE bit is set and the I bit is cleared in the CCR

register.

The OR bit is reset by an access to the SCISR register followed by a SCIDR register

read operation.

Noise error

Oversampling techniques are used for data recovery by discriminating between valid

incoming data and noise.

Normal data bits are considered valid if three consecutive samples (8th, 9th, 10th) have

the same bit value, otherwise the NF flag is set. In the case of start bit detection, the NF

flag is set on the basis of an algorithm combining both valid edge detection and three

samples (8th, 9th, 10th). Therefore, to prevent the NF flag getting set during start bit

reception, there should be a valid edge detection as well as three valid samples.

When noise is detected in a frame:

–

The NF flag is set at the rising edge of the RDRF bit.

Data is transferred from the Shift register to the SCIDR register.

No interrupt is generated. However this bit rises at the same time as the RDRF bit

which itself generates an interrupt.

The NF flag is reset by a SCISR register read operation followed by a SCIDR register

read operation.

During reception, if a false start bit is detected (e.g. 8th, 9th, 10th samples are

011,101,110), the frame is discarded and the receiving sequence is not started for this

frame. There is no RDRF bit set for this frame and the NF flag is set internally (not

accessible to the user). This NF flag is accessible along with the RDRF bit when a next

valid frame is received.

Note:

If the application Start Bit is not long enough to match the above requirements, then the NF

Flag may get set due to the short Start Bit. In this case, the NF flag may be ignored by the

application software when the first valid byte is received.


型号：	ST72F345S4T6
厂家：	ST
描述：	MICROCONTROLLER, PQFP44, 10 X 10 MM, ROHS COMPLIANT, LQFP-44
文件：	总246页 (文件大小：2101K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ST72F345S4T6 [STMICROELECTRONICS]

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