ST72FSCR1R4M1 [STMICROELECTRONICS]
8-BIT LOW-POWER, FULL-SPEED USB MCU WITH 16K FLASH, 768 RAM, SMARTCARD I/F, TIMER; 8位低功耗，全速带16K闪存， 768 RAM ，智能卡I / F ，定时器USB微控制器
| 型号： | ST72FSCR1R4M1 |
| 厂家： | 
ST |
| 描述： | 8-BIT LOW-POWER, FULL-SPEED USB MCU WITH 16K FLASH, 768 RAM, SMARTCARD I/F, TIMER |
| 文件： | 总102页 (文件大小：1360K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ST7SCR
8-BIT LOW-POWER, FULL-SPEED USB MCU WITH 16K
FLASH, 768 RAM, SMARTCARD I/F, TIMER
■ Memories
– Up to 16K of ROM or High Density Flash (HD-
Flash) program memory with read/write pro-
tection, HDFlash In-Circuit and In-Application
Programming. 100 write/erase cycles guaran-
teed, data retention: 20 years at 55°C
– Up to 768 bytes of RAM including up to 128
bytes stack and 256 bytes USB buffer
■ Clock, Reset and Supply Management
– Low Voltage Reset
SO24
TQFP64 14x14
■ ISO7816-3 UART Interface:
– 2 power saving modes: Halt and Wait modes
– PLL for generating 48 MHz USB clock using a
– 4 Mhz Clock generation
– Synchronous/Asynchronous protocols (T=0,
T=1)
4 MHz crystal
■ Interrupt Management
– Automatic retry on parity error
– Nested Interrupt Controller
■ USB (Universal Serial Bus) Interface
– Programmable Baud rate from 372 clock puls-
es up to 11.625 clock pulses (D=32/F=372)
– 256-byte buffer for full speed bulk, control and
interrupt transfer types compliant with USB
specification (version 2.0)
– On-Chip 3.3V USB voltage regulator and
transceivers with software power-down
– Card Insertion/Removal Detection
■ Smartcard Power Supply:
– Selectable card V
1.8V, 3V, and 5V
CC
– Internal Step-up converter for 5V supplied
Smartcards (with a current of up to 55mA) us-
ing only two external components.
– Programmable Smartcard Internal Voltage
Regulator (1.8V to 3.0V) with current overload
protection and 4 KV ESD protection (Human
Body Model) for all Smartcard Interface I/Os
– 7 USB Endpoints:
One 8-byte Bidirectional Control Endpoint
One 64-byte In Endpoint,
One 64-byte Out Endpoint
Four 8-byte In Endpoints
■ 35 or 4 I/O ports:
■ One 8-bit Timer
– Up to 4 LED outputs with software program-
mable constant current (3 or 7 mA).
– 2 General purpose I/Os programmable as in-
terrupts
– Time Base Unit (TBU) for generating periodic
interrupts.
■ Development Tools
– Up to 8 line inputs programmable as interrupts
– Up to 20 Outputs
– Full hardware/software development package
– 1 line assigned by default as static input after
reset
Table 1. Device Summary
Features
ST7FSCR1R4
ST7SCR1R4
16K ROM
ST7FSCR1E4
ST7SCR1E4
Program memory
16K FLASH
16K FLASH
16K ROM
User RAM (stack) - bytes
Peripherals
768 (128)
USB Full-Speed (7 Ep), TBU, Watchdog timer, ISO7816-3 Interface
4.0 to 5.5V
Operating Supply
Package
TQFP64
SO24
CPU Frequency
Operating temperature
4 or 8 Mhz
0°C to +70°C
Rev. 1.3
1/102
March 2003
1
Table of Contents
ST7SCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.3 STRUCTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.4 ICP (IN-CIRCUIT PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.5 IAP (IN-APPLICATION PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.6 PROGRAM MEMORY READ-OUT PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.1 CLOCK SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.2 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.2 MASKING AND PROCESSING FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.3 INTERRUPTS AND LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.4 CONCURRENT & NESTED MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.5 INTERRUPT REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.2 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.3 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
9 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
9.4 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10 MISCELLANEOUS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
11 LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
12 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
12.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
12.2 TIME BASE UNIT (TBU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
12.3 USB INTERFACE (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
102
12.4 SMARTCARD INTERFACE (CRD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
2/102
1
Table of Contents
13 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
13.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
13.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
14 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
14.1 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
14.2 RECOMMENDED OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
14.3 SUPPLY AND RESET CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
14.4 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
14.5 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
14.6 SMARTCARD SUPPLY SUPERVISOR ELECTRICAL CHARACTERISTICS . . . . . . . . 82
14.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
14.8 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . 89
15 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
15.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
16 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . 92
16.1 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . . 93
16.2 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
16.3 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
17 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
ERRATA SHEET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
18 SILICON IDENTIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
19 REFERENCE SPECIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
20 SILICON LIMITATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
20.1 UNEXPECTED RESET FETCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
20.2 USB: TWO CONSECUTIVE SETUP TOKENS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
20.3 USB BUFFER SHARED MEMORY ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
20.4 WDG (WATCHDOG) LIMITATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
20.5 SUPPLY CURRENT IN HALT MODE (SUSPEND) LIMITATIONS . . . . . . . . . . . . . . . . 100
20.6 START-UP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
20.7 I/O PORT INPUT HIGH LEVEL (VIH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
21 Device Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
22 ERRATA SHEET ReVISION History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
To obtain the most recent version of this datasheet,
please check at www.st.com>products>technical literature>datasheet
Please note that an errata sheet can be found at the end of this document on
page 99.
3/102
1
ST7SCR
1 INTRODUCTION
The ST7SCR and ST7FSCR devices are mem-
bers of the ST7 microcontroller family designed for
USB applications. All devices are based on a com-
mon industry-standard 8-bit core, featuring an en-
hanced instruction set.
signed multiplication and indirect addressing
modes.
The devices include an ST7 Core, up to 16 Kbytes
of program memory, up to 512 bytes of user RAM,
up to 35 I/O lines and the following on-chip periph-
erals:
The ST7SCR ROM devices are factory-pro-
grammed and are not reprogrammable.
– USB full speed interface with 7 endpoints, pro-
grammable in/out configuration and embedded
3.3V voltage regulator and transceivers (no ex-
ternal components are needed).
The ST7FSCR versions feature dual-voltage
Flash memory with Flash Programming capability.
They operate at a 4MHz external oscillator fre-
quency.
– ISO7816-3 UART interface with Programmable
Baud rate from 372 clock pulses up to 11.625
clock pulses
Under software control, all devices can be placed
in WAIT or HALT mode, reducing power consump-
tion when the application is in idle or stand-by
state.
– Smartcard Supply Block able to provide pro-
grammable supply voltage and I/O voltage levels
to the smartcards
The enhanced instruction set and addressing
modes of the ST7 offer both power and flexibility to
software developers, enabling the design of highly
efficient and compact application code. In addition
to standard 8-bit data management, all ST7 micro-
controllers feature true bit manipulation, 8x8 un-
– Low voltage reset ensuring proper power-on or
power-off of the device (selectable by option)
– Watchdog Timer
– 8-bit Timer (TBU)
Figure 1. ST7SCR Block Diagram
OSCIN
4MHz
PA[5:0]
OSCILLATOR
PORT A
OSCOUT
PB[7:0]
PC[7:0]
PD[7:0]
PORT B
PORT C
PORT D
PLL
48 MHz
8 MHz
DIVIDER
or 4 MHz
USB
DATA
BUFFER
(256 bytes)
LED[3:0]
LED
USBDP
USBDM
USBVCC
ISO7816 UART
USB
SUPPLY
MANAGER
WATCHDOG
8-BIT TIMER
CONTROL
DIODE
SELF
PA6
DC/DC
CRDVCC
CONVERTER
8-BIT CORE
ALU
V
PP
CRDDET
CRDIO
LVD
CRDC4
CRDC8
RAM
(512 Bytes)
3V/1.8V Vreg
CRDRST
CRDCLK
PROGRAM
MEMORY
(16K Bytes)
4/102
1
ST7SCR
2 PIN DESCRIPTION
Figure 2. 64-Pin TQFP Package Pinout
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
NC
DP
DM
LED0
PA6
CRDRST
NC
CRDCLK
NC
C4
CRDIO
C8
1
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
2
3
4
5
V
6
PP
PC7/WAKUP1
PC6/WAKUP1
PC5/WAKUP1
PC4/WAKUP1
PC3/WAKUP1
PC2/WAKUP1
PC1/WAKUP1
PC0/WAKUP1
GND
7
GND
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
8
9
10
11
12
13
14
15
16
VDD
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
NC = Not Connected
5/102
1
ST7SCR
PIN DESCRIPTION (Cont’d)
Figure 3. 24-Pin SO Package Pinout
24
23
SELF
DIODE
1
V
GNDA
GND
2
DD
V
22
21
20
19
18
17
16
15
14
13
3
DDA
USBVcc
DP
CRDVCC
CRDRST
4
5
DM
6
CRDCLK
C4
CRDIO
LED0
PA6
7
8
C8
CRDDET
9
V
PP
10
11
12
OSCOUT
OSCIN
NC
ICCDATA/WAKUP2/PA0
ICCCLK/WAKUP2/PA1
6/102
1
ST7SCR
PIN DESCRIPTION (Cont’d)
Legend / Abbreviations:
Port and control configuration:
Type: I = input, O = output, S = supply
– Input:float = floating, wpu = weak pull-up, int = in-
terrupt, ana = analog
In/Output level: C = CMOS 0.3V /0.7V with
DD
T
DD
input trigger
– Output: OD = open drain, PP = push-pull
Output level: HS = 10mA high sink (on N-buffer
only)
Refer to “I/O PORTS” on page 30 for more details
on the software configuration of the I/O ports.
Table 1. Pin Description
Pin n°
Level
Port / Control
Input Output
Main
Pin Name
Function
(after reset)
Alternate Function
1
2
5
6
CRDRST
O
O
C
C
C
X
X
X
X
X
Smartcard Reset
Not Connected
Smartcard Clock
Not Connected
Smartcard C4
Smartcard I/O
Smartcard C8
Ground
T
T
T
T
NC
3
CRDCLK
NC
4
5
7
8
9
3
C4
O
I/O
O
S
X
X
X
6
CRDIO
C8
C
X
X
T
7
C
X
8
GND
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
1)
9
O
O
O
O
O
O
O
O
I
C
C
C
C
C
C
C
C
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Port B0
T
T
T
T
T
T
T
T
1)
10
11
12
13
14
15
16
Port B1
1)
Port B2
1)
Port B3
1)
Port B4
1)
Port B5
1)
Port B6
1)
Port B7
17 10 CRDDET
C
X
Smartcard Detection
T
18
VDD
S
Power Supply voltage 4V-5.5V
PA0/WAKUP2/
ICCDATA
Interrupt,In-CircuitCommunication
Data Input
19 11
I/O
I/O
C
C
X
X
X
X
X
X
X
X
Port A0
Port A1
T
PA1/WAKUP2/
ICCCLK
Interrupt,In-CircuitCommunication
Clock Input
20 12
T
1)
1)
1)
1)
1)
21
22
23
24
25
PA2/WAKUP2
PA3/WAKUP2
PD0
I/O
I/O
O
C
C
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Port A2
Port A3
Port D0
Port D1
Port D2
Interrupt
Interrupt
T
T
C
T
T
T
PD1
O
C
C
PD2
O
7/102
1
ST7SCR
Pin n°
Level
Port / Control
Input Output
Main
Pin Name
Function
(after reset)
Alternate Function
1)
26
27
28
29
30
PD3
O
O
O
O
O
C
C
C
C
C
X
X
X
X
X
X
X
X
X
X
Port D3
T
T
T
T
T
1)
PD4
PD5
PD6
PD7
Port D4
1)
Port D5
1)
Port D6
1)
Port D7
Input/Output Oscillator pins. These pins connect a
4MHz parallel-resonant crystal, or an external source
to the on-chip oscillator.
31 14 OSCIN
C
T
32 15 OSCOUT
C
T
33
34
35
36
37
38
39
40
41
42
VDD
S
S
I
Power Supply voltage 4V-5.5V
GND
Ground
1)
PC0/WAKUP1
PC1/WAKUP1
PC2/WAKUP1
PC3/WAKUP1
PC4/WAKUP1
PC5/WAKUP1
PC6/WAKUP1
PC7/WAKUP1
C
C
C
C
C
C
C
C
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
External interrupt
External interrupt
External interrupt
External interrupt
External interrupt
External interrupt
External interrupt
External interrupt
T
T
T
T
T
T
T
T
1)
1)
1)
1)
1)
1)
1)
I
I
I
I
I
I
I
Flash programming voltage. Must be held low in nor-
mal operating mode.
43 16 V
S
PP
44 17 PA6
45 18 LED0
46 19 DM
47 20 DP
I
C
PA6
T
O
HS
X
Constant Current Output
USB Data Minus line
USB Data Plus line
Not Connected
I/O
I/O
C
T
T
C
48
NC
49 21 USBVCC
O
S
C
3.3 V Output for USB
power Supply voltage 4V-5.5V
power Supply voltage 4V-5.5V
Constant Current Output
Constant Current Output
Constant Current Output
Not Connected
T
50 22 V
51 23 V
DDA
S
DD
52
53
54
55
56
57
LED1
LED2
LED3
NC
O
O
O
HS
HS
HS
X
X
X
NC
Not Connected
PA4
I/O
C
X
X
X
X
Port A4
T
8/102
1
ST7SCR
Pin n°
Level
Port / Control
Input Output
Main
Pin Name
Function
(after reset)
Alternate Function
58
PA5
I/O
O
C
X
X
X
X
Port A5
T
An External inductance must be connected to these
pins for the step up converter (refer to Figure 4 to
choose the right capacitance)
59 24 SELF2
60 24 SELF1
C
T
T
O
C
An External diode must be connected to this pin for
the step up converter (refer to Figure 4 to choose the
right component)
61 1 DIODE
S
C
T
62 2 GNDA
63 3 GND
S
S
O
Ground
64 4 CDRVCC
C
X
Smartcard Supply pin
T
Note 1 : Keyboard interface
9/102
ST7SCR
PIN DESCRIPTION (Cont’d)
Figure 4. Smartcard Interface Reference Application
V
DD
VBUS
D-
D+
V
DD
C1
C2
C3
C4
GND
SHIELD
L1
D1
C5
SELF
DIODE
V
DD
V
GNDA
DD
V
GND
DDA
C6
USBVcc
DP
CRDVCC
CRDRST
CRDCLK
R
C7
D+
D-
DM
C8
C9
LED
LED0
PA6
C4
CRDIO
V
DD
C8
V
C
PP
L1
CRDDET
OSCOUT
OSCIN
NC
PA0
PA1
C
L2
Mandatory values for the external components :
C1 : 100nF
C2 : 4.7 µF,ESR 0.5 Ohm
L1 : 10 µH, 2 Ohm
C3 : 1 µF
C4 : 4.7 µF
C5 : 1 nF
C6 : 100 nF
R : 1.5kOhm
C7 : 4.7 µF,ESR 0.5 Ohm
C8 : 470 pF
C9 : 100 pF
Crystal 4.0 MHz, Impedance max100 Ohm
1)
Cl1, Cl2
D1: BAT42 SHOTTKY
Note 1: Refer to Section 6 on page 20.
10/102
1
ST7SCR
3 REGISTER & MEMORY MAP
As shown in Figure 5, the MCU is capable of ad-
dressing 64K bytes of memories and I/O registers.
The highest address bytes contain the user reset
and interrupt vectors.
The available memory locations consist of 40
bytes of register locations, up to 512 bytes of RAM
and up to 16K bytes of user program memory. The
RAM space includes up to 128 bytes for the stack
from 0100h to 017Fh.
IMPORTANT: Memory locations noted “Re-
served” must never be accessed. Accessing a re-
served area can have unpredictable effects on the
device.
Figure 5. Memory Map
0000h
HW Registers
0040h
(see Table 2)
Short Addressing
003Fh
0040h
RAM (192 Bytes)
00FFh
0100h
RAM
Stack (128 Bytes)
017Fh
(512 Bytes)
0180h
023Fh
0240h
16-bit Addressing RAM
( 192 Bytes)
USB RAM
023Fh
256 Bytes
033Fh
Unused
C000h
Program Memory
(16K Bytes)
FFDFh
FFE0h
Interrupt & Reset Vectors
(see Table 7)
FFFFh
11/102
1
ST7SCR
Table 2. Hardware Register Memory Map
Register
Register
name
Address
Block
Reset Status Remarks
Label
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
000Ah
000Bh
000Ch
000Dh
CRDCR
Smartcard Interface Control Register
Smartcard Interface Status Register
Smartcard Contact Control Register
Smartcard Elementary Time Unit 1
Smartcard Elementary Time Unit 0
Smartcard Guard time 1
00h
80h
xxh
01h
74h
00h
0Ch
00h
25h
80h
00h
00h
00h
00h
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
CRDSR
CRDCCR
CRDETU1
CRDETU0
CRDGT1
CRDGT0
CRDWT2
CRDWT1
CRDWT0
CRDIER
CRDIPR
CRDTXB
CRDRXB
Smartcard Guard time 0
CRD
Smartcard Character Waiting Time 2
Smartcard Character Waiting Time 1
Smartcard Character Waiting Time 0
Smartcard Interrupt Enable Register
Smartcard Interrupt Pending Register
Smartcard Transmit Buffer Register
Smartcard Receive Buffer Register
R/W
R
000Eh
Watchdog
Port A
WDGCR
Watchdog Control Register
00h
R/W
0011h
0012h
0013h
0014h
PADR
Port A Data Register
Port A Data Direction Register
Option Register
00h
00h
00h
00h
R/W
R/W
R/W
R/W
PADDR
PAOR
PAPUCR
Pull up Control Register
0015h
0016h
0017h
PBDR
Port B Data Register
Option Register
00h
00h
00h
R/W
R/W
R/W
Port B
Port C
Port D
PBOR
PBPUCR
Pull up Control Register
0018h
PCDR
Port C Data Register
00h
R/W
0019h
001Ah
001Bh
PDDR
Port D Data Register
Option Register
00h
00h
00h
R/W
R/W
R/W
PDOR
PDPUCR
Pull up Control Register
001Ch
001Dh
001Eh
001Fh
MISCR1
MISCR2
MISCR3
MISCR4
Miscellaneous Register 1
Miscellaneous Register 2
Miscellaneous Register 3
Miscellaneous Register 4
00h
00h
00h
00h
R/W
R/W
R/W
R/W
MISC
12/102
1
ST7SCR
Register
Label
Register
name
Address
Block
Reset Status Remarks
0020h
0021h
0022h
0023h
0024h
0025h
0026h
0027h
0028h
0029h
002Ah
002Bh
002Ch
002Dh
002Eh
002Fh
0030h
0031h
0032h
0033h
0034h
USBISTR
USBIMR
USBCTLR
DADDR
USB Interrupt Status Register
USB Interrupt Mask Register
USB Control Register
00h
00h
06h
00h
00h
0xh
00h
00h
00h
00h
00h
0xh
00h
00h
00h
00h
00h
00h
00h
00h
00h
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Device Address Register
USBSR
USB Status Register
EPOR
Endpoint 0 Register
CNT0RXR
CNT0TXR
EP1TXR
CNT1TXR
EP2RXR
CNT2RXR
EP2TXR
CNT2TXR
EP3TXR
CNT3TXR
EP4TXR
CNT4TXR
EP5TXR
CNT5TXR
ERRSR
EP 0 ReceptionCounter Register
EP 0 Transmission Counter Register
EP 1 Transmission Register
EP 1 Transmission Counter Register
EP 2 Reception Register
USB
EP 2 Reception Counter Register
EP 2 Transmission Register
EP 2 Transmission Counter Register
EP 3 Transmission Register
EP 3 Transmission Counter Register
EP 4 Transmission Register
EP 4 Transmission Counter Register
EP 5 Transmission Register
EP 5 Transmission Counter Register
Error Status Register
0035h
0036h
TBUCV
Timer counter value
Timer control status
00h
00h
R/W
R/W
TBU
TBUCSR
0037h
0038h
0039h
003Ah
ITSPR0
ITSPR1
ITSPR2
ITSPR3
Interrupt Software Priority Register 0
Interrupt Software Priority Register 1
Interrupt Software Priority Register 2
Interrupt Software Priority Register 3
FFh
FFh
FFh
FFh
R/W
R/W
R/W
R/W
ITC
003Bh
003Eh
Flash
FCSR
Flash Control Status Register
LED Control Register
00h
00h
R/W
R/W
LED_CTRL
13/102
1
ST7SCR
4 FLASH PROGRAM MEMORY
4.1 Introduction
user sectors (see Table 3). Each of these sectors
can be erased independently to avoid unneces-
sary erasing of the whole Flash memory when only
a partial erasing is required.
The ST7 dual voltage High Density Flash (HD-
Flash) is a non-volatile memory that can be electri-
cally erased as a single block or by individual sec-
tors and programmed on a Byte-by-Byte basis us-
The first two sectors have a fixed size of 4 Kbytes
(see Figure 6). They are mapped in the upper part
of the ST7 addressing space so the reset and in-
terrupt vectors are located in Sector 0 (F000h-
FFFFh).
ing an external V supply.
PP
The HDFlash devices can be programmed and
erased off-board (plugged in a programming tool)
or on-board using ICP (In-Circuit Programming) or
IAP (In-Application Programming).
Table 3. Sectors available in FLASH devices
The array matrix organisation allows each sector
to be erased and reprogrammed without affecting
other sectors.
Flash Memory Size
Available Sectors
(bytes)
4K
8K
Sector 0
Sectors 0,1
Sectors 0,1, 2
4.2 Main Features
> 8K
■ Three Flash programming modes:
– Insertion in a programming tool. In this mode,
all sectors including option bytes can be pro-
grammed or erased.
Figure 6. Memory map and sector address
– ICP (In-Circuit Programming). In this mode, all
sectors including option bytes can be pro-
grammed or erased without removing the de-
vice from the application board.
16K USER FLASH MEMORY SIZE
C000h
– IAP (In-Application Programming) In this
mode, all sectors except Sector 0, can be pro-
grammed or erased without removing the de-
vice from the application board and while the
application is running.
ex.: user program
8 Kbytes
SECTOR 2
■ ICT (In-Circuit Testing) for downloading and
executing user application test patterns in RAM
■ Read-out protection against piracy
ex.: user data
DFFFh
E000h
+ library
4 Kbytes
SECTOR 1
■ Register Access Security System (RASS) to
EFFFh
F000h
ex.: user system library
+ IAP BootLoader
prevent accidental programming or erasing
4 Kbytes
SECTOR 0
FFFFh
4.3 Structure
The Flash memory is organised in sectors and can
be used for both code and data storage.
Depending on the overall FLASH memory size in
the microcontroller device, there are up to three
14/102
1
ST7SCR
FLASH PROGRAM MEMORY (Cont’d)
4.4 ICP (In-Circuit Programming)
If ICCCLK or ICCDATA are used for other purpos-
es in the application, a serial resistor has to be im-
plemented to avoid a conflict in case one of the
other devices forces the signal level.
Note: To develop a custom programming tool, re-
fer to the ST7 FLASH Programming and ICC Ref-
erence Manual which gives full details on the ICC
protocol hardware and software.
To perform ICP the microcontroller must be
switched to ICC (In-Circuit Communication) mode
by an external controller or programming tool.
Depending on the ICP code downloaded in RAM,
Flash memory programming can be fully custom-
ized (number of bytes to program, program loca-
tions, or selection serial communication interface
for downloading).
4.5 IAP (In-Application Programming)
When using an STMicroelectronics or third-party
programming tool that supports ICP and the spe-
cific microcontroller device, the user needs only to
implement the ICP hardware interface on the ap-
plication board (see Figure 7). For more details on
the pin locations, refer to the device pinout de-
scription.
This mode uses a BootLoader program previously
stored in Sector 0 by the user (in ICP mode or by
plugging the device in a programming tool).
This mode is fully controlled by user software. This
allows it to be adapted to the user application, (us-
er-defined strategy for entering programming
mode, choice of communications protocol used to
fetch the data to be stored, etc.). For example, it is
possible to download code from the USB interface
and program it in the Flash. IAP mode can be used
to program any of the Flash sectors except Sector
0, which is write/erase protected to allow recovery
in case errors occur during the programming oper-
ation.
ICP needs six signals to be connected to the pro-
gramming tool. These signals are:
– V : device power supply ground
SS
– V : for reset by LVD
DD
– OSCIN: to force the clock during power-up
– ICCCLK: ICC output serial clock pin
– ICCDATA: ICC input serial data pin
– V : ICC mode selection and programming
PP
voltage.
Figure 7. Typical ICP Interface
PROGRAMMING TOOL
ICC CONNECTOR
ICC Cable
ICP PROGRAMMING TOOL CONNECTOR
HE10 CONNECTOR TYPE
9
7
5
6
3
1
2
10
8
4
APPLICATION BOARD
10kΩ
C
C
L2
L1
4.7kΩ
ST7
15/102
1
ST7SCR
FLASH PROGRAM MEMORY (Cont’d)
Note: If the ICCCLK or ICCDATA pins are only
used as outputs in the application, no signal isola-
tion is necessary. As soon as the Programming
Tool is plugged to the board, even if an ICC ses-
sion is not in progress, the ICCCLK and ICCDATA
pins are not available for the application. If they
are used as inputs by the application, isolation
such as a serial resistor has to implemented in
case another device forces the signal. Refer to the
Programming Tool documentation for recom-
mended resistor values.
tire Flash program memory is first automatically
erased.
Refer to the Option Byte description for more de-
tails.
4.6.1 Register Description
FLASH CONTROL/STATUS REGISTER (FCSR)
Read/Write
Reset Value: 0000 0000 (00h)
7
0
0
0
4.6 Program Memory Read-out Protection
0
0
0
0
0
0
The read-out protection is enabled through an op-
tion bit.
For Flash devices, when this option is selected,
the program and data stored in the Flash memory
are protected against read-out piracy (including a
re-write protection). When this protection is re-
moved by reprogramming the Option Byte, the en-
This register is reserved for use by Programming
Tool software. It controls the FLASH programming
and erasing operations. For details on customizing
FLASH programming methods and In-Circuit Test-
ing, refer to the ST7 FLASH Programming and
ICC Reference Manual.
16/102
1
ST7SCR
5 CENTRAL PROCESSING UNIT
5.1 INTRODUCTION
5.3 CPU REGISTERS
This CPU has a full 8-bit architecture and contains
six internal registers allowing efficient 8-bit data
manipulation.
The 6 CPU registers shown in Figure 8 are not
present in the memory mapping and are accessed
by specific instructions.
Accumulator (A)
5.2 MAIN FEATURES
The Accumulator is an 8-bit general purpose reg-
ister used to hold operands and the results of the
arithmetic and logic calculations and to manipulate
data.
■ Enable executing 63 basic instructions
■ Fast 8-bit by 8-bit multiply
■ 17 main addressing modes (with indirect
Index Registers (X and Y)
addressing mode)
These 8-bit registers are used to create effective
addresses or as temporary storage areas for data
manipulation. (The Cross-Assembler generates a
precede instruction (PRE) to indicate that the fol-
lowing instruction refers to the Y register.)
■ Two 8-bit index registers
■ 16-bit stack pointer
■ Low power HALT and WAIT modes
■ Priority maskable hardware interrupts
■ Non-maskable software/hardware interrupts
The Y register is not affected by the interrupt auto-
matic procedures.
Program Counter (PC)
The program counter is a 16-bit register containing
the address of the next instruction to be executed
by the CPU. It is made of two 8-bit registers PCL
(Program Counter Low which is the LSB) and PCH
(Program Counter High which is the MSB).
Figure 8. CPU Registers
7
0
ACCUMULATOR
RESET VALUE = XXh
7
0
0
X INDEX REGISTER
Y INDEX REGISTER
RESET VALUE = XXh
7
RESET VALUE = XXh
PCL
8 7
PCH
15
0
PROGRAM COUNTER
RESET VALUE = RESET VECTOR @ FFFEh-FFFFh
7
1
0
1
1
I1 H I0 N Z
C
CONDITION CODE REGISTER
RESET VALUE =
8
1
7
1
X 1 X X X
0
15
STACK POINTER
RESET VALUE = STACK HIGHER ADDRESS
X = Undefined Value
17/102
1
ST7SCR
CENTRAL PROCESSING UNIT (Cont’d)
Condition Code Register (CC)
Read/Write
Bit 1 = Z Zero.
This bit is set and cleared by hardware. This bit in-
dicates that the result of the last arithmetic, logical
or data manipulation is zero.
Reset Value: 111x1xxx
7
0
0: The result of the last operation is different from
zero.
1: The result of the last operation is zero.
1
1
I1
H
I0
N
Z
C
This bit is accessed by the JREQ and JRNE test
instructions.
The 8-bit Condition Code register contains the in-
terrupt masks and four flags representative of the
result of the instruction just executed. This register
can also be handled by the PUSH and POP in-
structions.
Bit 0 = C Carry/borrow.
This bit is set and cleared by hardware and soft-
ware. It indicates an overflow or an underflow has
occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.
These bits can be individually tested and/or con-
trolled by specific instructions.
Arithmetic Management Bits
This bit is driven by the SCF and RCF instructions
and tested by the JRC and JRNC instructions. It is
also affected by the “bit test and branch”, shift and
rotate instructions.
Bit 4 = H Half carry.
This bit is set by hardware when a carry occurs be-
tween bits 3 and 4 of the ALU during an ADD or
ADC instructions. It is reset by hardware during
the same instructions.
Interrupt Management Bits
Bit 5,3 = I1, I0 Interrupt
0: No half carry has occurred.
1: A half carry has occurred.
The combination of the I1 and I0 bits gives the cur-
rent interrupt software priority.
This bit is tested using the JRH or JRNH instruc-
tion. The H bit is useful in BCD arithmetic subrou-
tines.
Interrupt Software Priority
Level 0 (main)
I1
1
0
0
1
I0
0
1
0
1
Level 1
Bit 2 = N Negative.
Level 2
This bit is set and cleared by hardware. It is repre-
sentative of the result sign of the last arithmetic,
logical or data manipulation. It’s a copy of the re-
Level 3 (= interrupt disable)
These two bits are set/cleared by hardware when
entering in interrupt. The loaded value is given by
the corresponding bits in the interrupt software pri-
ority registers (IxSPR). They can be also set/
cleared by software with the RIM, SIM, IRET,
HALT, WFI and PUSH/POP instructions.
th
sult 7 bit.
0: The result of the last operation is positive or null.
1: The result of the last operation is negative
(i.e. the most significant bit is a logic 1).
This bit is accessed by the JRMI and JRPL instruc-
tions.
See the interrupt management chapter for more
details.
18/102
1
ST7SCR
CENTRAL PROCESSING UNIT (Cont’d)
Stack Pointer (SP)
Read/Write
The least significant byte of the Stack Pointer
(called S) can be directly accessed by a LD in-
struction.
Reset Value: 017Fh
Note: When the lower limit is exceeded, the Stack
Pointer wraps around to the stack upper limit, with-
out indicating the stack overflow. The previously
stored information is then overwritten and there-
fore lost. The stack also wraps in case of an under-
flow.
15
8
1
0
7
0
0
0
0
0
0
0
The stack is used to save the return address dur-
ing a subroutine call and the CPU context during
an interrupt. The user may also directly manipulate
the stack by means of the PUSH and POP instruc-
tions. In the case of an interrupt, the PCL is stored
at the first location pointed to by the SP. Then the
other registers are stored in the next locations as
shown in Figure 9
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
The Stack Pointer is a 16-bit register which is al-
ways pointing to the next free location in the stack.
It is then decremented after data has been pushed
onto the stack and incremented before data is
popped from the stack (see Figure 9).
– When an interrupt is received, the SP is decre-
mented and the context is pushed on the stack.
Since the stack is 256 bytes deep, the 8 most sig-
nificant bits are forced by hardware. Following an
MCU Reset, or after a Reset Stack Pointer instruc-
tion (RSP), the Stack Pointer contains its reset val-
ue (the SP7 to SP0 bits are set) which is the stack
higher address.
– On return from interrupt, the SP is incremented
and the context is popped from the stack.
A subroutine call occupies two locations and an in-
terrupt five locations in the stack area.
Figure 9. Stack Manipulation Example
CALL
Subroutine
RET
or RSP
PUSH Y
POP Y
IRET
Interrupt
Event
@ 0100h
SP
SP
SP
Y
CC
A
CC
A
CC
A
X
X
X
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
SP
SP
PCH
PCL
PCH
PCL
SP
@ 017Fh
Stack Higher Address = 017Fh
0100h
Stack Lower Address =
19/102
1
ST7SCR
6 SUPPLY, RESET AND CLOCK MANAGEMENT
6.1 CLOCK SYSTEM
6.1.1 General Description
The user can then select an internal frequency
(f ) of either 4 MHz or 8MHz by programming
the CLK_SEL bit in the MISCR4 register (refer to
MISCELLANEOUS REGISTERS section on page
37).
CPU
The MCU accepts either a 4MHz crystal or an ex-
ternal clock signal to drive the internal oscillator.
The internal clock (f
nal oscillator frequency (f
) is derived from the inter-
OSC
CPU
), which is 4Mhz.
The PLL provides a signal with a duty cycle of 50
%.
After reset, the internal clock (f
the internal oscillator (4Mhz frequency).
) is provided by
CPU
The internal clock signal (f
) is also routed to
CPU
To activate the 48-MHz clock for the USB inter-
face, the user must turn on the PLL by setting the
PLL_ON bit in the MISCR4 register. When the PLL
is locked, the LOCK bit is set by hardware.
the on-chip peripherals. The CPU clock signal
consists of a square wave with a duty cycle of
50%.
Figure 10. Clock, Reset and Supply Block Diagram
PLL_ CLK_
MISCR4
-
-
-
-
-
LOCK
ON
SEL
-
INTERNAL
CLOCK (f
4 Mhz
8 Mhz
48 MHz
48 MHz
PLL
X 12
)
CPU
DIV
4 MHz
(f
)
OSC
USB
The internal oscillator is designed to operate with
an AT-cut parallel resonant quartz in the frequen-
Table 4. Recommended Values for 4 MHz
Crystal Resonator
cy range specified for f . The circuit shown in
osc
Figure 12 is recommended when using a crystal,
and Table 4 lists the recommended capacitance.
The crystal and associated components should be
mounted as close as possible to the input pins in
order to minimize output distortion and start-up
stabilisation time. The LOCK bit in the MISCR4
R
20 Ω
56pF
56pF
25 Ω
47pF
47pF
70 Ω
22pF
22pF
SMAX
C
OSCIN
C
OSCOUT
Note: R
is the equivalent serial resistor of the
SMAX
crystal (see crystal specification).
register can also be used to generate the f
di-
CPU
rectly from f
if the PLL and the USB interface
OSC
are not active.
20/102
1
ST7SCR
CLOCK SYSTEM (Cont’d)
6.1.2 External Clock
Figure 12. Crystal Resonator
An external clock may be applied to the OSCIN in-
put with the OSCOUT pin not connected, as
shown on Figure 11.
OSCIN
OSCOUT
Figure 11. .External Clock Source Connections
C
C
OSCIN
OSCOUT
OSCIN
OSCOUT
NC
EXTERNAL
CLOCK
21/102
1
ST7SCR
6.2 RESET SEQUENCE MANAGER (RSM)
6.2.1 Introduction
■ A first delay of 30µs + 127 t
cycles during
CPU
which the internal reset is maintained.
The reset sequence manager has two reset sourc-
es:
■ A second delay of 512 t cycles after the
CPU
internal reset is generated. It allows the
oscillator to stabilize and ensures that recovery
has taken place from the Reset state.
■ Internal LVD reset (Low Voltage Detection)
which includes both a power-on and a voltage
drop reset
■ Reset vector fetch (duration: 2 clock cycles)
Low Voltage Detector
■ Internal watchdog reset generated by an
internal watchdog counter underflow as shown
in Figure 14.
The low voltage detector generates a reset when
6.2.2 Functional Description
V
<V
(rising edge) or V <V (falling edge),
DD
IT+ DD IT-
as shown in Figure 13.
The reset service routine vector is fixed at ad-
dresses FFFEh-FFFFh in the ST7 memory map.
The LVD filters spikes on V larger than t
to
g(VDD)
DD
avoid parasitic resets. See “SUPPLY AND RESET
CHARACTERISTICS” on page 79.
The basic reset sequence consists of 3 phases as
shown in Figure 13:
Figure 13. LVD RESET Sequence
V
IT+
V
IT-
V
DD
LVD
RESET
RUN
DELAY 1
DELAY 2
LVD
RESET
INTERNAL
RESET
DELAY 1 = 30µs + 127 tCPU
DELAY 2 = 512 tCPU
FETCH VECTOR (2 tCPU
)
Figure 14. Watchdog RESET Sequence
WATCHDOG
RESET
RUN
DELAY 1
DELAY 2
WATCHDOG
RESET
WATCHDOG UNDERFLOW
DELAY 1 = 30µs + 127 tCPU
DELAY 2 = 512 tCPU
FETCH VECTOR (2 tCPU
)
22/102
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ST7SCR
7 INTERRUPTS
7.1 INTRODUCTION
When an interrupt request has to be serviced:
– Normal processing is suspended at the end of
the current instruction execution.
The ST7 enhanced interrupt management pro-
vides the following features:
– The PC, X, A and CC registers are saved onto
the stack.
■ Hardware interrupts
■ Software interrupt (TRAP)
■ Nested or concurrent interrupt management
with flexible interrupt priority and level
management:
– I1 and I0 bits of CC register are set according to
the corresponding values in the ISPRx registers
of the serviced interrupt vector.
– The PC is then loaded with the interrupt vector of
the interrupt to service and the first instruction of
the interrupt service routine is fetched (refer to
“Interrupt Mapping” table for vector addresses).
– Up to 4 software programmable nesting levels
– Up to 16 interrupt vectors fixed by hardware
– 3 non maskable events: TLI, RESET, TRAP
This interrupt management is based on:
The interrupt service routine should end with the
IRET instruction which causes the contents of the
saved registers to be recovered from the stack.
– Bit 5 and bit 3 of the CPU CC register (I1:0),
– Interrupt software priority registers (ISPRx),
Note: As a consequence of the IRET instruction,
the I1 and I0 bits will be restored from the stack
and the program in the previous level will resume.
– Fixed interrupt vector addresses located at the
high addresses of the memory map (FFE0h to
FFFFh) sorted by hardware priority order.
This enhanced interrupt controller guarantees full
upward compatibility with the standard (not nest-
ed) ST7 interrupt controller.
Table 5. Interrupt Software Priority Levels
Interrupt software priority Level
I1
1
0
0
1
I0
0
1
0
1
Level 0 (main)
Level 1
Low
7.2 MASKING AND PROCESSING FLOW
Level 2
The interrupt masking is managed by the I1 and I0
bits of the CC register and the ISPRx registers
which give the interrupt software priority level of
each interrupt vector (see Table 5). The process-
ing flow is shown in Figure 15.
High
Level 3 (= interrupt disable)
Figure 15. Interrupt Processing Flowchart
PENDING
INTERRUPT
Y
Y
RESET
TLI
N
Interrupt has the same or a
lower software priority
than current one
N
I1:0
FETCH NEXT
INSTRUCTION
THE INTERRUPT
STAYS PENDING
Y
“IRET”
N
RESTORE PC, X, A, CC
FROM STACK
EXECUTE
INSTRUCTION
STACK PC, X, A, CC
LOAD I1:0 FROM INTERRUPT SW REG.
LOAD PC FROM INTERRUPT VECTOR
23/102
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ST7SCR
INTERRUPTS (Cont’d)
Servicing Pending Interrupts
■ TLI (Top Level Hardware Interrupt)
As several interrupts can be pending at the same
time, the interrupt to be taken into account is deter-
mined by the following two-step process:
This hardware interrupt occurs when a specific
edge is detected on the dedicated TLI pin.
Caution: A TRAP instruction must not be used in a
TLI service routine.
– the highest software priority interrupt is serviced,
■ TRAP (Non Maskable Software Interrupt)
– if several interrupts have the same software pri-
ority then the interrupt with the highest hardware
priority is serviced first.
This software interrupt is serviced when the TRAP
instruction is executed. It will be serviced accord-
ing to the flowchart in Figure 15 as a TLI.
Figure 16 describes this decision process.
Caution: TRAP can be interrupted by a TLI.
■ RESET
Figure 16. Priority Decision Process
The RESET source has the highest priority in the
ST7. This means that the first current routine has
the highest software priority (level 3) and the high-
est hardware priority.
PENDING
INTERRUPTS
See the RESET chapter for more details.
Different
Same
SOFTWARE
PRIORITY
Maskable Sources
Maskable interrupt vector sources can be serviced
if the corresponding interrupt is enabled and if its
own interrupt software priority (in ISPRx registers)
is higher than the one currently being serviced (I1
and I0 in CC register). If any of these two condi-
tions is false, the interrupt is latched and thus re-
mains pending.
HIGHEST SOFTWARE
PRIORITY SERVICED
HIGHEST HARDWARE
PRIORITY SERVICED
■ External Interrupts
External interrupts allow the processor to exit from
HALT low power mode.
External interrupt sensitivity is software selectable
through the External Interrupt Control register
(EICR).
When an interrupt request is not serviced immedi-
ately, it is latched and then processed when its
software priority combined with the hardware pri-
ority becomes the highest one.
External interrupt triggered on edge will be latched
and the interrupt request automatically cleared
upon entering the interrupt service routine.
If several input pins of a group connected to the
same interrupt line are selected simultaneously,
these will be logically NANDed.
Note 1: The hardware priority is exclusive while
the software one is not. This allows the previous
process to succeed with only one interrupt.
Note 2: RESET, TRAP and TLI are non maskable
and they can be considered as having the highest
software priority in the decision process.
■ Peripheral Interrupts
Different Interrupt Vector Sources
Usually the peripheral interrupts cause the MCU to
exit from HALT mode except those mentioned in
the “Interrupt Mapping” table.
A peripheral interrupt occurs when a specific flag
is set in the peripheral status registers and if the
corresponding enable bit is set in the peripheral
control register.
Two interrupt source types are managed by the
ST7 interrupt controller: the non-maskable type
(RESET, TLI, TRAP) and the maskable type (ex-
ternal or from internal peripherals).
Non-Maskable Sources
These sources are processed regardless of the
state of the I1 and I0 bits of the CC register (see
Figure 15). After stacking the PC, X, A and CC
registers (except for RESET), the corresponding
vector is loaded in the PC register and the I1 and
I0 bits of the CC are set to disable interrupts (level
3). These sources allow the processor to exit
HALT mode.
The general sequence for clearing an interrupt is
based on an access to the status register followed
by a read or write to an associated register.
Note: The clearing sequence resets the internal
latch. A pending interrupt (i.e. waiting for being
serviced) will therefore be lost if the clear se-
quence is executed.
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ST7SCR
INTERRUPTS (Cont’d)
7.3 INTERRUPTS AND LOW POWER MODES
7.4 CONCURRENT & NESTED MANAGEMENT
All interrupts allow the processor to exit the WAIT
low power mode. On the contrary, only external
and other specified interrupts allow the processor
to exit from the HALT modes (see column “Exit
from HALT” in “Interrupt Mapping” table). When
several pending interrupts are present while exit-
ing HALT mode, the first one serviced can only be
an interrupt with exit from HALT mode capability
and it is selected through the same decision proc-
ess shown in Figure 16.
The following Figure 17 and Figure 18 show two
different interrupt management modes. The first is
called concurrent mode and does not allow an in-
terrupt to be interrupted, unlike the nested mode in
Figure 18. The interrupt hardware priority is given
in this order from the lowest to the highest: MAIN,
IT4, IT3, IT2, IT1, IT0, TLI. The software priority is
given for each interrupt.
Warning: A stack overflow may occur without no-
tifying the software of the failure.
Note: If an interrupt, that is not able to Exit from
HALT mode, is pending with the highest priority
when exiting HALT mode, this interrupt is serviced
after the first one serviced.
Figure 17. Concurrent Interrupt Management
SOFTWARE
PRIORITY
LEVEL
I1
I0
TLI
3
1 1
1 1
1 1
1 1
1 1
1 1
IT0
3
IT1
IT1
3
IT2
3
IT3
3
RIM
IT4
3
MAIN
MAIN
3/0
11 / 10
10
Figure 18. Nested Interrupt Management
SOFTWARE
PRIORITY
LEVEL
I1
I0
TLI
3
1 1
1 1
0 0
0 1
1 1
1 1
IT0
3
IT1
IT2
IT1
2
IT2
1
IT3
3
RIM
IT4
IT4
3
MAIN
MAIN
3/0
11 / 10
10
25/102
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ST7SCR
INTERRUPTS (Cont’d)
7.5 INTERRUPT REGISTER DESCRIPTION
INTERRUPT SOFTWARE PRIORITY REGIS-
TERS (ISPRX)
CPU CC REGISTER INTERRUPT BITS
Read/Write
Read/Write (bit 7:4 of ISPR3 are read only)
Reset Value: 1111 1111 (FFh)
Reset Value: 111x 1010 (xAh)
7
0
7
0
ISPR0
ISPR1
I1_3 I0_3 I1_2 I0_2 I1_1 I0_1 I1_0 I0_0
I1_7 I0_7 I1_6 I0_6 I1_5 I0_5 I1_4 I0_4
1
1
I1
H
I0
N
Z
C
Bit 5, 3 = I1, I0 Software Interrupt Priority
ISPR2 I1_11 I0_11 I1_10 I0_10 I1_9 I0_9 I1_8 I0_8
These two bits indicate the current interrupt soft-
ware priority.
ISPR3
1
1
1
1
I1_13 I0_13 I1_12 I0_12
Interrupt Software Priority Level
I1
1
0
0
1
I0
0
Level 0 (main)
Level 1
Low
These four registers contain the interrupt software
priority of each interrupt vector.
1
Level 2
0
– Each interrupt vector (except RESET and TRAP)
has corresponding bits in these registers where
its own software priority is stored. This corre-
spondance is shown in the following table.
High
Level 3 (= interrupt disable*)
1
These two bits are set/cleared by hardware when
entering in interrupt. The loaded value is given by
the corresponding bits in the interrupt software pri-
ority registers (ISPRx).
Vector address
ISPRx bits
FFFBh-FFFAh
FFF9h-FFF8h
...
I1_0 and I0_0 bits*
I1_1 and I0_1 bits
...
They can be also set/cleared by software with the
RIM, SIM, HALT, WFI, IRET and PUSH/POP in-
structions (see “Interrupt Dedicated Instruction
Set” table).
FFE1h-FFE0h
I1_13 and I0_13 bits
*Note: TLI, TRAP and RESET events are non
maskable sources and can interrupt a level 3 pro-
gram.
– Each I1_x and I0_x bit value in the ISPRx regis-
ters has the same meaning as the I1 and I0 bits
in the CC register.
– Level 0 can not be written (I1_x=1, I0_x=0). In
this case, the previously stored value is kept. (ex-
ample: previous=CFh, write=64h, result=44h)
The RESET, TRAP and TLI vectors have no soft-
ware priorities. When one is serviced, the I1 and I0
bits of the CC register are both set.
*Note: Bits in the ISPRx registers which corre-
spond to the TLI can be read and written but they
are not significant in the interrupt process man-
agement.
Caution: If the I1_x and I0_x bits are modified
while the interrupt x is executed the following be-
haviour has to be considered: If the interrupt x is
still pending (new interrupt or flag not cleared) and
the new software priority is higher than the previ-
ous one, the interrupt x is re-entered. Otherwise,
the software priority stays unchanged up to the
next interrupt request (after the IRET of the inter-
rupt x).
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ST7SCR
INTERRUPTS (Cont’d)
Table 6. Dedicated Interrupt Instruction Set
Instruction
HALT
IRET
New Description
Entering Halt mode
Function/Example
I1
1
H
I0
0
N
Z
C
Interrupt routine return
Jump if I1:0=11
Pop CC, A, X, PC
I1:0=11 ?
I1
H
I0
N
Z
C
JRM
JRNM
POP CC
RIM
Jump if I1:0<>11
I1:0<>11 ?
Pop CC from the Stack
Enable interrupt (level 0 set)
Disable interrupt (level 3 set)
Software trap
Mem => CC
I1
1
1
1
1
H
I0
0
1
1
0
N
Z
C
Load 10 in I1:0 of CC
Load 11 in I1:0 of CC
Software NMI
SIM
TRAP
WFI
Wait for interrupt
Note: During the execution of an interrupt routine, the HALT, POPCC, RIM, SIM and WFI instructions
change the current software priority up to the next IRET instruction or one of the previously mentioned
instructions.
In order not to lose the current software priority level, the RIM, SIM, HALT, WFI and POP CC instructions
should never be used in an interrupt routine.
Table 7. Interrupt Mapping
Exit
from
HALT
Source
Block
Register Priority
Address
Vector
N°
Description
Label
Order
RESET
TRAP
Reset
Highest
Priority
yes
FFFEh-FFFFh
FFFCh-FFFDh
FFFAh-FFFBh
FFF8h-FFF9h
FFF6h-FFF7h
FFF4h-FFF5h
FFF2h-FFF3h
FFF0h-FFF1h
FFEEh-FFEFh
FFECh-FFEDh
Software Interrupt
N/A
0
1
2
3
4
5
6
7
ICP
FLASH Start programming NMI interrupt
ISO7816-3 UART Interrupt
USB Communication Interrupt
External Interrupt Port C
External Interrupt Port A
TBU Timer Interrupt
no
UART
UIC
USB
USBISTR
WAKUP1
WAKUP2
TIM
yes
yes
no
TBUSR
USCUR
1)
1)
CARDDET
ESUSP
Smartcard Insertion/Removal Interrupt
End suspend Interrupt
yes
no
USBISTR
Lowest
Priority
8
Not used
FFEAh-FFEBh
Note 1: This interrupt can be used to exit from USB suspend mode.
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ST7SCR
8 POWER SAVING MODES
8.1 INTRODUCTION
Figure 19. WAIT Mode Flow Chart
To give a large measure of flexibility to the applica-
tion in terms of power consumption, two main pow-
er saving modes are implemented in the ST7.
WFI INSTRUCTION
After a RESET the normal operating mode is se-
lected by default (RUN mode). This mode drives
the device (CPU and embedded peripherals) by
means of a master clock which is based on the
main oscillator frequency.
OSCILLATOR
PERIPH. CLOCK
CPU CLOCK
I-BIT
ON
ON
OFF
From Run mode, the different power saving
modes may be selected by setting the relevant
register bits or by calling the specific ST7 software
instruction whose action depends on the oscillator
status.
CLEARED
8.2 WAIT MODE
N
RESET
WAIT mode places the MCU in a low power con-
sumption mode by stopping the CPU.
N
This power saving mode is selected by calling the
“WFI” ST7 software instruction.
Y
INTERRUPT
All peripherals remain active. During WAIT mode,
the I bit of the CC register is forced to 0, to enable
all interrupts. All other registers and memory re-
main unchanged. The MCU remains in WAIT
mode until an interrupt or Reset occurs, whereup-
on the Program Counter branches to the starting
address of the interrupt or Reset service routine.
The MCU will remain in WAIT mode until a Reset
or an Interrupt occurs, causing it to wake up.
Y
OSCILLATOR
ON
ON
ON
SET
PERIPH. CLOCK
CPU CLOCK
I-BIT
IF RESET
Refer to Figure 19.
512 CPU CLOCK
CYCLES DELAY
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Note: Before servicing an interrupt, the CC
register is pushed on the stack. The I-Bit is set
during the interrupt routine and cleared when
the CC register is popped.
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ST7SCR
POWER SAVING MODES (Cont’d)
8.3 HALT MODE
Figure 20. HALT Mode Flow Chart
The HALT mode is the MCU lowest power con-
sumption mode. The HALT mode is entered by ex-
ecuting the HALT instruction. The internal oscilla-
tor is then turned off, causing all internal process-
ing to be stopped, including the operation of the
on-chip peripherals.
HALT INSTRUCTION
OSCILLATOR
PERIPH. CLOCK
CPU CLOCK
I-BIT
OFF
OFF
Note: The PLL must be disabled before a HALT
instruction.
OFF
CLEARED
When entering HALT mode, the I bit in the Condi-
tion Code Register is cleared. Thus, any of the ex-
ternal interrupts (ITi or USB end suspend mode),
are allowed and if an interrupt occurs, the CPU
clock becomes active.
The MCU can exit HALT mode on reception of ei-
ther an external interrupt on ITi, an end suspend
mode interrupt coming from USB peripheral, or a
reset. The oscillator is then turned on and a stabi-
lization time is provided before releasing CPU op-
eration. The stabilization time is 512 CPU clock cy-
cles.
N
RESET
N
EXTERNAL
Y
INTERRUPT*
After the start up delay, the CPU continues opera-
tion by servicing the interrupt which wakes it up or
by fetching the reset vector if a reset wakes it up.
Y
OSCILLATOR
ON
ON
PERIPH. CLOCK
CPU CLOCK
I-BIT
ON
SET
512 CPU CLOCK
CYCLES DELAY
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Note: Before servicing an interrupt, the CC
register is pushed on the stack. The I-Bit is set
during the interrupt routine and cleared when
the CC register is popped.
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ST7SCR
9 I/O PORTS
9.1 Introduction
The I/O ports offer different functional modes:
– transfer of data through digital inputs and outputs
and for specific pins:
terrupt request to the CPU. The interrupt sensitivi-
ty is given independently according to the descrip-
tion mentioned in the ITRFRE interrupt register.
Each pin can independently generate an Interrupt
request.
– alternate signal input/output for the on-chip pe-
ripherals.
Each external interrupt vector is linked to a dedi-
cated group of I/O port pins (see Interrupts sec-
tion). If more than one input pin is selected simul-
taneously as interrupt source, this is logically
ORed. For this reason if one of the interrupt pins is
tied low, it masks the other ones.
– external interrupt detection
An I/O port is composed of up to 8 pins. Each pin
can be programmed independently as digital input
(with or without interrupt generation) or digital out-
put.
Output Mode
9.2 Functional description
The pin is configured in output mode by setting the
corresponding DDR register bit (see Table 7).
Each port is associated to 4 main registers:
– Data Register (DR)
In this mode, writing “0” or “1” to the DR register
applies this digital value to the I/O pin through the
latch. Then reading the DR register returns the
previously stored value.
– Data Direction Register (DDR)
– Option Register (OR)
Note: In this mode, the interrupt function is disa-
bled.
– Pull Up Register (PU)
Each I/O pin may be programmed using the corre-
sponding register bits in DDR register: bit X corre-
sponding to pin X of the port. The same corre-
spondence is used for the DR register.
Digital Alternate Function
When an on-chip peripheral is configured to use a
pin, the alternate function is automatically select-
ed. This alternate function takes priority over
standard I/O programming. When the signal is
coming from an on-chip peripheral, the I/O pin is
automatically configured in output mode (push-pull
or open drain according to the peripheral).
Table 8. I/O Pin Functions
DDR
MODE
Input
0
1
Output
When the signal is going to an on-chip peripheral,
the I/O pin has to be configured in input mode. In
this case, the pin’s state is also digitally readable
by addressing the DR register.
Input Modes
The input configuration is selected by clearing the
corresponding DDR register bit.
Notes:
In this case, reading the DR register returns the
digital value applied to the external I/O pin.
1. Input pull-up configuration can cause an unex-
pected value at the input of the alternate peripher-
al input.
2. When the on-chip peripheral uses a pin as input
and output, this pin must be configured as an input
(DDR = 0).
Note 1: All the inputs are triggered by a Schmitt
trigger.
Note 2: When switching from input mode to output
mode, the DR register should be written first to
output the correct value as soon as the port is con-
figured as an output.
Warning: The alternate function must not be acti-
vated as long as the pin is configured as input with
interrupt, in order to avoid generating spurious in-
terrupts.
Interrupt function
When an I/O is configured in Input with Interrupt,
an event on this I/O can generate an external In-
30/102
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ST7SCR
I/O PORTS (Cont’d)
9.3 I/O Port Implementation
The hardware implementation on each I/O port de-
pends on the settings in the DDR register and spe-
cific feature of the I/O port such as true open drain.
9.3.1 Port A
Table 9. Port A Description
I / O
PORT A
Input
Output
PA[5:0]
PA6
without pull-up *
without pull-up
push-pull or open drain with software selectable pull-up
-
*Reset State
Figure 21. PA0, PA1, PA2, PA3, PA4, PA5 Configuration
ALTERNATE ENABLE
1
0
VDD
ALTERNATE
OUTPUT
P-BUFFER
V
DD
DR
PULL-UP 1)
LATCH
ALTERNATE ENABLE
DDR
LATCH
PAD
DDR SEL
N-BUFFER
DIODES
1
0
DR SEL
ALTERNATE ENABLE
VSS
ALTERNATE INPUT
CMOS SCHMITT TRIGGER
Note 1: selectable by PAPUCR register
Figure 22. PA6 Configuration
V
DD
DR SEL
PAD
CMOS SCHMITT TRIGGER
DIODES
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ST7SCR
I/O PORTS (Cont’d)
9.3.2 Ports B and D
Table 10. Port B and D Description
PORTS B AND D
PB[7:0]
Output *
push-pull or open drain with software selectable pull-up
PD[7:0]
*Reset State = open drain
Figure 23. Port B and D Configuration
ALTERNATE ENABLE
1
VDD
ALTERNATE
OUTPUT
1
0
‘0’
P-BUFFER
0
V
DD
DR
PULL-UP 1)
LATCH
ALTERNATE ENABLE
OM
LATCH
PAD
PULL_UP
LATCH
N-BUFFER
DIODES
DR SEL
ALTERNATE ENABLE
VSS
Note 1: selectable by PAPUCR register
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ST7SCR
I/O PORTS (Cont’d)
9.3.3 Port C
Table 11. Port C Description
PORT C
Input
PC[7:0]
with pull-up
Figure 24. Port C Configuration
V
DD
V
DD
PULL-UP
DR SEL
PAD
CMOS SCHMITT TRIGGER
DIODES
ALTERNATE INPUT
33/102
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ST7SCR
I/O PORTS (Cont’d)
9.4 Register Description
DATA REGISTERS (PxDR)
OPTION REGISTER (PxOR)
Port A Data Register (PADR): 0011h
Port B Data Register (PBDR): 0015h
Port C Data Register (PCDR): 0018h
Port D Data Register (PCDR): 0019h
Read/Write
Port x Option Register
PxOR with x = A, B, or D
Port A Option Register (PAOR): 0013h
Port B Option Register (PBOR): 0016h
Port D Option Register (PDOR): 001Ah
Read/Write
Reset Value Port A: 0000 0000 (00h)
Reset Value Port B: 0000 0000 (00h)
Reset Value Port C: 0000 0000 (00h)
Reset Value Port D: 0000 0000 (00h)
Reset Value: 0000 0000 (00h)
7
0
OM7 OM6 OM5 OM4 OM3 OM2 OM1 OM0
7
0
Bits 7:0 = OM[7:0] Option register 8 bits.
D7
D6
D5
D4
D3
D2
D1
D0
The OR register allows to distinguish in output
mode if the push-pull or open drain configuration is
selected.
Bits 7:0 = D[7:0] Data Register 8 bits.
Each bit is set and cleared by software.
0: Output open drain
1: Output push-pull
The DR register has a specific behaviour accord-
ing to the selected input/output configuration. Writ-
ing the DR register is always taken in account
even if the pin is configured as an input. Reading
the DR register returns either the DR register latch
content (pin configured as output) or the digital val-
ue applied to the I/O pin (pin configured as input).
PULL UP CONTROL REGISTER (PxPUCR)
Port x Pull Up Register
PxPUCR with x = A, B, or D
Port A Pull up Register (PAPUCR): 0014h
Port B Pull up Register (PBPUCR): 0017h
Port D Pull up Register (PDPUCR): 001Bh
DATA DIRECTION REGISTER (PADDR)
Port A Data Direction Register (PADDR): 0012h
Read/Write
Reset Value Port A: 0000 0000 (00h)
Read/Write
Reset Value: 0000 0000 (00h)
7
0
7
0
DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0
PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0
Bits 7:0 = DD7-DD0 Data Direction Register 8 bits.
Bits 7:0 = PU[7:0] Pull up register 8 bits.
The DDR register gives the input/output direction
configuration of the pins. Each bits is set and
cleared by software.
The PU register is used to control the pull up.
Each bit is set and cleared by software.
0: Pull up inactive
1: Pull up active
0: Input mode
1: Output mode
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ST7SCR
I/O PORTS (Cont’d)
Table 12. I/O Ports Register Map
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
PADR
Reset Value
MSB
0
LSB
0
11
12
13
14
15
16
17
18
19
1A
1B
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PADDR
Reset Value
MSB
0
LSB
0
0
0
0
0
0
0
0
0
0
0
PAOR
Reset Value
MSB
0
LSB
0
PAPUCR
Reset Value
MSB
0
LSB
0
PBDR
Reset Value
MSB
0
LSB
0
PBOR
Reset Value
MSB
0
LSB
0
PBPUCR
Reset Value
MSB
0
LSB
0
PCDR
Reset Value
MSB
0
LSB
0
PDDR
Reset Value
MSB
0
LSB
0
PDOR
Reset Value
MSB
0
LSB
0
PDPUCR
Reset Value
MSB
0
LSB
0
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ST7SCR
10 MISCELLANEOUS REGISTERS
MISCELLANEOUS REGISTER 1 (MISCR1)
Reset Value : 0000 0000 (00h)
Read/Write
MISCELLANEOUS REGISTER 2 (MISCR2)
Reset Value : 0000 0000 (00h)
Read/Write
7
0
7
0
ITM ITM ITM ITM ITM ITM ITM ITM
CRD ITM ITM ITM ITM ITM ITM
IRM 14 13 12 11 10
-
7
6
5
4
3
2
1
0
9
Writing the ITIFREC register enables or disables
external interrupt on Port C. Each bit can be
masked independantly. The ITMx bit masks the
external interrupt on PC.x.
Writing the ITIFREA register enables or disables
external interrupt on port A.
Bit 7 = Reserved.
Bits[7:0] = ITM [7:0] Interrupt Mask
0: external interrupt disabled
1: external interrupt enabled
Bit 6 = CRDIRM CRD Insertion/Removal Interrupt
Mask
0: CRDIR interrupt disabled
1: CRDIR interrupt enabled
Bits [5:0] = ITM [14:9] Interrupt Mask
Bit x of MISCR2 masks the external interrupt on
port A.x.
Bit x = ITM n Interrupt Mask n
0: external interrupt disabled on PA.x.
1: external interrupt enabled on PA.x.
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ST7SCR
MISCELLANEOUS REGISTER 3 (MISCR3)
Reset Value: 0000 0000 (00h)
Read/Write
MISCELLANEOUS REGISTER 4 (MISCR4)
Reser Value : 0000 0000 (00h).
Read/Write
7
0
-
7
0
CTR CTR CTR CTR
L1_A L0_A L1_C L0_C
PLL CLK_
_ON SEL
-
-
-
-
-
-
-
-
LOCK
This register is used to configure the edge and the
level sensitivity of the Port A and Port C external
interrupt. This means that all bits of a port must
have the same sensitivity.
Bit 7 = Reserved.
Bit 6 = PLL_ON PLL Activation
0: PLL disabled
1: PLL enabled
If a write access modifies bits 7:4, it clears the
pending interrupts.
Note: The PLL must be disabled before a HALT
instruction.
CTRL0_C, CTRL1_C : Sensitivity on port C
CTRL0_A, CTRL1_A : Sensitivity on port A
Bit 5 = CLK_SEL Clock Selection
External
CTR CTR
L1_X L0_X
This bit is set and cleared by software.
0: CPU frequency = 4MHz
1: CPU frequency = 8MHz
Interrupt Sensitivity
Falling edge & low level
Rising edge only
0
0
1
1
0
1
0
1
Falling edge only
Bits 4:1 = Reserved.
Rising and falling edge
Bit 0 = LOCK PLL status bit
0: PLL not locked. f
= f
external clock fre-
CPU
OSC
quency.
1: PLL locked. f
CLKSEL bit.
= 4 or 8 MHz depending on
CPU
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ST7SCR
MISCELLANEOUS REGISTERS (Cont’d)
Table 13. Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
MISCR1
Reset Value
ITM7
0
ITM6
0
ITM5
0
ITM4
0
ITM3
0
ITM2
0
ITM1
0
ITM0
0
001C
001D
001E
001Fh
MISCR2
Reset Value
ITM14
0
ITM13
0
ITM12
0
ITM11
0
ITM10
0
ITM9
0
0
0
MISCR3
Reset Value
CTRL1_A CTRL0_A CTRL1_C CTRL0_C
0
0
0
0
0
0
0
0
0
0
0
MISCR4
Reset Value
PLL_ON RST_IN CLK_SE
0L
LOCK
0
0
0
0
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ST7SCR
11 LEDs
Each of the four available LEDs can be selected
using the LED_CTRL register. Two types of LEDs
are supported: 3mA and 7mA.
Bits 3:0 = LDx_I Current selection on LDx
0: 3mA current on LDx pad
1: 7mA current on LDx pad
LED_CTRL REGISTER
Reset Value: 0000 0000 (00h)
Read/Write
7
0
LD3
LD2
LD1
LD0 LD3_I LD2_I LD1_I LD0_I
Bits 7:4 = LDx LED Enable
0: LED disabled
1: LED enabled
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ST7SCR
12 ON-CHIP PERIPHERALS
12.1 WATCHDOG TIMER (WDG)
12.1.1 Introduction
If the watchdog is activated (the WDGA bit is set)
and when the 7-bit timer (bits T[6:0]) rolls over
from 40h to 3Fh (T6 becomes cleared), it initiates
a reset cycle pulling low the reset pin for typically
500ns.
The Watchdog timer is used to detect the occur-
rence of a software fault, usually generated by ex-
ternal interference or by unforeseen logical condi-
tions, which causes the application program to
abandon its normal sequence. The Watchdog cir-
cuit generates an MCU reset on expiry of a pro-
grammed time period, unless the program refresh-
es the counter’s contents before the T6 bit be-
comes cleared.
The application program must write in the CR reg-
ister at regular intervals during normal operation to
prevent an MCU reset. The value to be stored in
the CR register must be between FFh and C0h
(see Table 14):
12.1.2 Main Features
– The WDGA bit is set (watchdog enabled)
■ Programmable timer (64 increments of 65536
– The T6 bit is set to prevent generating an imme-
diate reset
CPU cycles)
■ Programmable reset
– The T[5:0] bits contain the number of increments
which represents the time delay before the
watchdog produces a reset.
■ Reset (if watchdog activated) when the T6 bit
reaches zero
■ Hardware Watchdog selectable by option byte
■ Watchdog Reset indicated by status flag
Table 14.Watchdog Timing (f
= 8 MHz)
CPU
CR Register
initial value
WDG timeout period
(ms)
12.1.3 Functional Description
Max
Min
FFh
C0h
524.288
8.192
The counter value stored in the CR register (bits
T[6:0]), is decremented every 65,536 machine cy-
cles, and the length of the timeout period can be
programmed by the user in 64 increments.
Figure 25. Watchdog Block Diagram
RESET
WATCHDOG CONTROL REGISTER (CR)
T5
T0
T6
WDGA
T1
T4
T2
T3
7-BIT DOWNCOUNTER
CLOCK DIVIDER
f
CPU
÷65536
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ST7SCR
WATCHDOG TIMER (Cont’d)
12.1.4 Software Watchdog Option
occurrences of the data value 0x8E from memo-
ry. For example, avoid defining a constant in
ROM with the value 0x8E.
If Software Watchdog is selected by option byte,
the watchdog is disabled following a reset. Once
activated it cannot be disabled, except by a reset.
– As the HALT instruction clears the I bit in the CC
register to allow interrupts, the user may choose
to clear all pending interrupt bits before execut-
ing the HALT instruction. This avoids entering
other peripheral interrupt routines after executing
the external interrupt routine corresponding to
the wake-up event (reset or external interrupt).
The T6 bit can be used to generate a software re-
set (the WDGA bit is set and the T6 bit is cleared).
12.1.5 Hardware Watchdog Option
If Hardware Watchdog is selected by option byte,
the watchdog is always active and the WDGA bit in
the CR is not used.
12.1.7 Interrupts
None.
12.1.6 Low Power Modes
WAIT Instruction
12.1.8 Register Description
CONTROL REGISTER (CR)
Read/Write
No effect on Watchdog.
HALT Instruction
Halt mode can be used when the watchdog is en-
abled. When the oscillator is stopped, the WDG
stops counting and is no longer able to generate a
reset until the microcontroller receives an external
interrupt or a reset.
Reset Value: 0111 1111 (7Fh)
7
0
WDGA T6
T5
T4
T3
T2
T1
T0
If an external interrupt is received, the WDG re-
starts counting after 514 CPU clocks. In the case
of the Software Watchdog option, if a reset is gen-
erated, the WDG is disabled (reset state).
Bit 7 = WDGA Activation bit.
This bit is set by software and only cleared by
hardware after a reset. When WDGA = 1, the
watchdog can generate a reset.
Recommendations
0: Watchdog disabled
1: Watchdog enabled
– Make sure that an external event is available to
wake up the microcontroller from Halt mode.
Note: This bit is not used if the hardware watch-
dog option is enabled by option byte.
– Before executing the HALT instruction, refresh
the WDG counter, to avoid an unexpected WDG
reset immediately after waking up the microcon-
troller.
Bit 6:0 = T[6:0] 7-bit timer (MSB to LSB).
These bits contain the decremented value. A reset
is produced when it rolls over from 40h to 3Fh (T6
becomes cleared).
– When using an external interrupt to wake up the
microcontroller, reinitialize the corresponding I/O
as Input before executing the HALT instruction.
The main reason for this is that the I/O may be
wrongly configured due to external interference
or by an unforeseen logical condition.
– The opcode for the HALT instruction is 0x8E. To
avoid an unexpected HALT instruction due to a
program counter failure, it is advised to clear all
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ST7SCR
12.2 TIME BASE UNIT (TBU)
12.2.1 Introduction
When the counter rolls over from FFh to 00h, the
OVF bit is set and an interrupt request is generat-
ed if ITE is set.
The Timebase unit (TBU) can be used to generate
periodic interrupts.
The user can write a value at any time in the
TBUCV register.
12.2.2 Main Features
■ 8-bit upcounter
■ Programmable prescaler
■ Period between interrupts: max. 8.1ms (at 8
12.2.4 Programming Example
In this example, timer is required to generate an in-
terrupt after a delay of 1 ms.
MHz f
)
CPU
■ Maskable interrupt
Assuming that f
is 8 MHz and a prescaler divi-
CPU
12.2.3 Functional Description
The TBU operates as a free-running upcounter.
sion factor of 256 will be programmed using the
PR[2:0] bits in the TBUCSR register, 1 ms = 32
TBU timer ticks.
When the TCEN bit in the TBUCSR register is set
by software, counting starts at the current value of
the TBUCV register. The TBUCV register is incre-
mented at the clock rate output from the prescaler
selected by programming the PR[2:0] bits in the
TBUCSR register.
In this case, the initial value to be loaded in the
TBUCV must be (256-32) = 224 (E0h).
ld A, E0h
ld TBUCV, A ; Initialize counter value
ld A 1Fh
;
ld TBUCSR, A ; Prescaler factor = 256,
; interrupt enable,
; TBU enable
Figure 26. TBU Block Diagram
1
MSB
LSB
0
TBU 8-BIT UPCOUNTER (TBUCV REGISTER)
TBU PRESCALER
f
CPU
0
0
OVF ITE TCEN PR2 PR1 PR0
TBUCSR REGISTER
INTERRUPT REQUEST
TBU
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ST7SCR
TIMEBASE UNIT (Cont’d)
12.2.5 Low Power Modes
TBU CONTROL/STATUS REGISTER (TBUCSR)
Read/Write
Reset Value: 0000 0000 (00h)
Mode
WAIT
HALT
Description
No effect on TBU
TBU halted.
7
0
0
0
OVF ITE TCEN PR2
PR1 PR0
12.2.6 Interrupts
Bits [7:6] = Reserved. Forced by hardware to 0.
Bit 5 = OVF Overflow Flag
Enable
Control from
Bit
Exit
Exit
from
Halt
Interrupt
Event
Event
Flag
Wait
Counter Over-
flow Event
This bit is set only by hardware, when the counter
value rolls over from FFh to 00h. It is cleared by
software reading the TBUCSR register. Writing to
this bit does not change the bit value.
0: No overflow
OVF
ITE
Yes
No
Note: The OVF interrupt event is connected to an
interrupt vector (see Interrupts chapter).
It generates an interrupt if the ITE bit is set in the
TBUCSR register and the I-bit in the CC register is
reset (RIM instruction).
1: Counter overflow
Bit 4 = ITE Interrupt enabled.
This bit is set and cleared by software.
0: Overflow interrupt disabled
1: Overflow interrupt enabled. An interrupt request
is generated when OVF=1.
12.2.7 Register Description
TBU COUNTER VALUE REGISTER (TBUCV)
Read/Write
Reset Value: 0000 0000 (00h)
Bit 3 = TCEN TBU Enable.
7
0
This bit is set and cleared by software.
0: TBU counter is frozen and the prescaler is reset.
1: TBU counter and prescaler running.
CV7 CV6 CV5 CV4 CV3 CV2 CV1 CV0
Bits 2:0 = PR[2:0] Prescaler Selection
Bits 7:0 = CV[7:0] Counter Value
These bits are set and cleared by software to se-
lect the prescaling factor.
This register contains the 8-bit counter value
which can be read and written anytime by soft-
ware. It is continuously incremented by hardware if
TCEN=1.
PR2 PR1 PR0
Prescaler Division Factor
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2
4
8
16
32
64
128
256
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ST7SCR
12.3 USB INTERFACE (USB)
12.3.1 Introduction
For general information on the USB, refer to the
“Universal Serial Bus Specifications” document
available at http//:www.usb.org.
The USB Interface implements a full-speed func-
tion interface between the USB and the ST7 mi-
crocontroller. It is a highly integrated circuit which
includes the transceiver, 3.3 voltage regulator, SIE
and USB Data Buffer interface. No external com-
ponents are needed apart from the external pull-
up on USBDP for full speed recognition by the
USB host.
Serial Interface Engine
The SIE (Serial Interface Engine) interfaces with
the USB, via the transceiver.
The SIE processes tokens, handles data transmis-
sion/reception, and handshaking as required by
the USB standard. It also performs frame format-
ting, including CRC generation and checking.
12.3.2 Main Features
■ USB Specification Version 1.1 Compliant
■ Supports Full-Speed USB Protocol
■ Seven Endpoints (including default endpoint)
Endpoints
The Endpoint registers indicate if the microcontrol-
ler is ready to transmit/receive, and how many
bytes need to be transmitted.
■ CRC generation/checking, NRZI encoding/
decoding and bit-stuffing
Data Transfer to/from USB Data Buffer Memory
■ USB Suspend/Resume operations
■ On-Chip 3.3V Regulator
When a token for a valid Endpoint is recognized by
the USB interface, the related data transfer takes
place to/from the USB data buffer. At the end of
the transaction, an interrupt is generated.
■ On-Chip USB Transceiver
12.3.3 Functional Description
Interrupts
The block diagram in Figure 27, gives an overview
of the USB interface hardware.
By reading the Interrupt Status register, applica-
tion software can know which USB event has oc-
curred.
Figure 27. USB Block Diagram
48 MHz
ENDPOINT
CPU
REGISTERS
USBDM
BUFFER
Address,
Transceiver
SIE
INTERFACE
USBDP
USBVCC
USBGND
data busses
and interrupts
3.3V
Voltage
Regulator
USB
USB
DATA
REGISTERS
BUFFER
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ST7SCR
USB INTERFACE (Cont’d)
USB Endpoint RAM Buffers
Endpoint 0 is 2 x 8 bytes in size, Endpoint 1, 3, 4,
and Endpoint 5 are 8 bytes in size and Endpoint 2
is 2 x 64 bytes in size .
There are seven Endpoints including one bidirec-
tional control Endpoint (Endpoint 0), five IN End-
points (Endpoint 1, 2, 3, 4, 5) and one OUT end-
point (Endpoint 2).
Figure 28. Endpoint Buffer Size
Endpoint 0 Buffer OUT
Endpoint 0 Buffer IN
8 Bytes
8 Bytes
8 Bytes
Endpoint 1 Buffer IN
64 Bytes
64 Bytes
Endpoint 2 Buffer OUT
Endpoint 2 Buffer IN
Endpoint 3 Buffer IN
Endpoint 4 Buffer IN
Endpoint 5 Buffer IN
8 Bytes
8 Bytes
8 Bytes
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ST7SCR
USB INTERFACE (Cont’d)
12.3.4 Register Description
INTERRUPT STATUS REGISTER (USBISTR)
Read/Write
event is the SETUP token reception on the Control
Endpoint (EP0).
Bit 4 = ERR Error.
Reset Value: 0000 0000 (00h)
This bit is set by hardware whenever one of the er-
rors listed below has occurred:
0: No error detected
7
0
1: Timeout, CRC, bit stuffing, nonstandard
framing or buffer overrun error detected
CTR
0
SOVR ERROR SUSP ESUSP RESET SOF
These bits cannot be set by software. When an in-
terrupt occurs these bits are set by hardware. Soft-
ware must read them to determine the interrupt
type and clear them after servicing.
Note: The CTR bit (which is an OR of all the end-
point CTR flags) cannot be cleared directly, only
by clearing the CTR flags in the Endpoint regis-
ters.
Note: Refer to the ERR[2:0] bits in the USBSR
register to determine the error type.
Bit 3 = SUSP Suspend mode request.
This bit is set by hardware when a constant idle
state is present on the bus line for more than 3 ms,
indicating a suspend mode request from the USB.
The suspend request check is active immediately
after each USB reset event and is disabled by
hardware when suspend mode is forced (FSUSP
bit in the USBCTLR register) until the end of
resume sequence.
Bit 7 = CTR Correct Transfer.
This bit is set by hardware when a correct transfer
operation is performed. This bit is an OR of all
CTR flags (CTR0 in the EP0R register and
CTR_RX and CTR_TX in the EPnRXR and EP-
nTXR registers). By looking in the USBSR regis-
ter, the type of transfer can be determined from the
PID[1:0] bits for Endpoint 0. For the other End-
points, the Endpoint number on which the transfer
was made is identified by the EP[1:0] bits and the
type of transfer by the IN/OUT bit.
Bit 2 = ESUSP End Suspend mode.
This bit is set by hardware when, during suspend
mode, activity is detected that wakes the USB in-
terface up from suspend mode.
This interrupt is serviced by a specific vector, in or-
der to wake up the ST7 from HALT mode.
0: No End Suspend detected
0: No Correct Transfer detected
1: Correct Transfer detected
1: End Suspend detected
Note: A transfer where the device sent a NAK or
STALL handshake is considered not correct (the
host only sends ACK handshakes). A transfer is
considered correct if there are no errors in the PID
and CRC fields, if the DATA0/DATA1 PID is sent
as expected, if there were no data overruns, bit
stuffing or framing errors.
Bit 1 = RESET USB reset.
This bit is set by hardware when the USB reset se-
quence is detected on the bus.
0: No USB reset signal detected
1: USB reset signal detected
Note: The DADDR, EP0R, EP1RXR, EP1TXR,
EP2RXR and EP2TXR registers are reset by a
USB reset.
Bit 6 = Reserved, forced by hardware to 0.
Bit 5 = SOVR Setup Overrun.
Bit 0 = SOF Start of frame.
This bit is set by hardware when a SOF token is re-
ceived on the USB.
0: No SOF received
1: SOF received
This bit is set by hardware when a correct Setup
transfer operation is performed while the software
is servicing an interrupt which occured on the
same Endpoint (CTR0 bit in the EP0R register is
still set when SETUP correct transfer occurs).
0: No SETUP overrun detected
Note: To avoid spurious clearing of some bits, it is
recommended to clear them using a load instruc-
tion where all bits which must not be altered are
set, and all bits to be cleared are reset. Avoid read-
modify-write instructions like AND, XOR...
1: SETUP overrun detected
When this event occurs, the USBSR register is not
updated because the only source of the SOVR
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ST7SCR
USB INTERFACE (Cont’d)
INTERRUPT MASK REGISTER (USBIMR)
Read/Write
Bits [5:4] = Reserved, forced by hardware to 0.
Reset Value: 0000 0000 (00h)
Bit 3 = RESUME Resume.
This bit is set by software to wake-up the Host
when the ST7 is in suspend mode.
0: Resume signal not forced
7
0
1: Resume signal forced on the USB bus.
SOVR
M
SUSP ESUSP RESET
CTRM
0
ERRM
SOFM
M
M
M
Software should clear this bit after the appropriate
delay.
These bits are mask bits for all the interrupt condi-
tion bits included in the USBISTR register. When-
ever one of the USBIMR bits is set, if the corre-
sponding USBISTR bit is set, and the I- bit in the
CC register is cleared, an interrupt request is gen-
erated. For an explanation of each bit, please refer
to the description of the USBISTR register.
Bit 2 = PDWN Power down.
This bit is set by software to turn off the 3.3V on-
chip voltage regulator that supplies the external
pull-up resistor and the transceiver.
0: Voltage regulator on
1: Voltage regulator off
Note: After turning on the voltage regulator, soft-
ware should allow at least 3 µs for stabilisation of
the power supply before using the USB interface.
CONTROL REGISTER (USBCTLR)
Read/Write
Reset value: 0000 0110 (06h)
Bit 1 = FSUSP Force suspend mode.
This bit is set by software to enter Suspend mode.
The ST7 should also be put in Halt mode to reduce
power consumption.
7
0
USB_
RST
RESU
ME
RSM
0
0
PDWN FSUSP FRES
0: Suspend mode inactive
1: Suspend mode active
Bit 7 = RSM Resume Detected
When the hardware detects USB activity, it resets
this bit (it can also be reset by software).
This bit shows when a resume sequence has start-
ed on the USB port, requesting the USB interface
to wake-up from suspend state. It can be used to
determine the cause of an ESUSP event.
0: No resume sequence detected on USB
1: Resume sequence detected on USB
Bit 0 = FRES Force reset.
This bit is set by software to force a reset of the
USB interface, just as if a RESET sequence came
from the USB.
0: Reset not forced
1: USB interface reset forced.
Bit 6 = USB_RST USB Reset detected.
This bit shows that a reset sequence has started
on the USB. It can be used to determine the cause
of an ESUSP event (Reset sequence).
0: No reset sequence detected on USB
1: Reset sequence detected on USB
The USB is held in RESET state until software
clears this bit, at which point a “USB-RESET” in-
terrupt will be generated if enabled.
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ST7SCR
USB INTERFACE (Cont’d)
DEVICE ADDRESS REGISTER (DADDR)
Read/Write
Bits 4:3 = Reserved, forced by hardware to 0.
Reset Value: 0000 0000 (00h)
Bits 2:0 = EP[2:0] Endpoint number.
These bits identify the endpoint which required at-
tention.
7
0
0
ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0
000 = Endpoint 0
001 = Endpoint 1
010 = Endpoint 2
011 = Endpoint 3
Bit 7 = Reserved, forced by hardware to 0.
100 = Endpoint 4
101 = Endpoint 5
Bits 6:0 = ADD[6:0] Device address, 7 bits.
Software must write into this register the address
sent by the host during enumeration.
ERROR STATUS REGISTER (ERRSR)
Read only
Note: This register is also reset when a USB reset
is received or forced through bit FRES in the US-
BCTLR register.
Reset Value: 0000 0000 (00h)
7
0
0
USB STATUS REGISTER (USBSR)
Read only
0
0
0
0
ERR2 ERR1 ERR0
Reset Value: 0000 0000 (00h)
7
0
Bits 7:3 = Reserved, forced by hardware to 0.
IN/
OUT
PID1 PID0
0
0
EP2
EP1
EP0
Bits 2:0 = ERR[2:0] Error type.
These bits identify the type of error which oc-
curred.
Bits 7:6 = PID[1:0] Token PID bits 1 & 0 for End-
point 0 Control.
USB token PIDs are encoded in four bits. PID[1:0]
correspond to the most significant bits of the PID
field of the last token PID received by Endpoint 0.
Note: The least significant PID bits have a fixed
value of 01.
When a CTR interrupt occurs on Endpoint 0 (see
register USBISTR) the software should read the
PID[1:0] bits to retrieve the PID name of the token
received.
ERR2 ERR1 ERR0
Meaning
0
0
0
0
0
1
0
1
0
No error
Bitstuffing error
CRC error
EOP error (unexpected end of
packet or SE0 not followed by
J-state)
0
1
1
0
1
0
PID error (PID encoding error,
unexpected or unknown PID)
The USB specification defines PID bits as:
Memory over / underrun (mem-
ory controller has not an-
swered in time to a memory
data request)
PID1
PID0
PID Name
OUT
1
1
0
1
1
1
0
1
1
0
0
1
IN
Other error (wrong packet,
timeout error)
SETUP
Note: these bits are set by hardware when an er-
ror interrupt occurs and are reset automatically
when the error bit (USBISTR bit 4) is cleared by
software.
Bit 5 = IN/OUT Last transaction direction for End-
point 1, 2 , 3, 4 or 5.
This bit is set by hardware when a CTR interrupt
occurs on Endpoint 1, 2, 3, 4 or 5.
0: OUT transaction
1: IN transaction
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ST7SCR
USB INTERFACE (Cont’d)
ENDPOINT 0 REGISTER (EP0R)
Read/Write
These bits contain the information about the end-
point status, which are listed below
Reset value: 0000 0000(00h)
Table 15. Transmission Status Encoding
STAT_TX1 STAT_TX0
Meaning
7
0
DISABLED: no function can be
executed on this endpoint and
messages related to this end-
point are ignored.
STAT_ STAT_
STAT_ STAT_
DTOG
_TX
DTOG
_RX
0
0
CTR0
0
TX1
TX0
RX1
RX0
STALL: the endpoint is stalled
and all transmission requests
result in a STALL handshake.
This register is used for controlling Endpoint 0.
Bits 6:4 and bits 2:0 are also reset by a USB reset,
either received from the USB or forced through the
FRES bit in USBCTLR.
0
1
1
0
NAK: the endpoint is NAKed
and all transmission requests
result in a NAK handshake.
Bit 7 = CTR0 Correct Transfer.
This bit is set by hardware when a correct transfer
operation is performed on Endpoint 0. This bit
must be cleared after the corresponding interrupt
has been serviced.
VALID: this endpoint is enabled
(if an address match occurs, the
USB interface handles the
transaction).
1
1
0: No CTR on Endpoint 0
1: Correct transfer on Endpoint 0
These bits are written by software. Hardware sets
the STAT_TX and STAT_RX bits to NAK when a
correct transfer has occurred (CTR=1) addressed
to this endpoint; this allows software to prepare the
next set of data to be transmitted.
Bit 6 = DTOG_TX Data Toggle, for transmission
transfers.
It contains the required value of the toggle bit
(0=DATA0, 1=DATA1) for the next transmitted
data packet. This bit is set by hardware on recep-
tion of a SETUP PID. DTOG_TX toggles only
when the transmitter has received the ACK signal
from the USB host. DTOG_TX and also
DTOG_RX are normally updated by hardware, on
receipt of a relevant PID. They can be also written
by the user, both for testing purposes and to force
a specific (DATA0 or DATA1) token.
Bit 3 = Reserved, forced by hardware to 0.
Bit 2 = DTOG_RX Data Toggle, for reception
transfers.
It contains the expected value of the toggle bit
(0=DATA0, 1=DATA1) for the next data packet.
This bit is cleared by hardware in the first stage
(Setup Stage) of a control transfer (SETUP trans-
actions start always with DATA0 PID). The receiv-
er toggles DTOG_RX only if it receives a correct
data packet and the packet’s data PID matches
the receiver sequence bit.
Bits 5:4 = STAT_TX [1:0] Status bits, for transmis-
sion transfers.
49/102
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ST7SCR
USB INTERFACE (Cont’d)
Bits 1:0 = STAT_RX [1:0] Status bits, for reception
transfers.
USB reset, either received from the USB or forced
through the FRES bit in the USBCTLR register.
These bits contain the information about the end-
point status, which are listed below:
Bits [7:4] = Reserved, forced by hardware to 0.
Table 16. Reception Status Encoding
Bit 3 = CTR_TX Correct Transmission Transfer.
This bit is set by hardware when a correct transfer
operation is performed in transmission. This bit
must be cleared after the corresponding interrupt
has been serviced.
0: No CTR in transmission on Endpoint 1, 2, 3, 4 or
5
STAT_RX1 STAT_RX0
Meaning
DISABLED: no function can be
executed on this endpoint and
messages related to this end-
point are ignored.
0
0
STALL: the endpoint is stalled
and all reception requests re-
sult in a STALL handshake.
1: Correct transfer in transmission on Endpoint 1,
2, 3, 4 or 5
0
1
1
0
NAK: the endpoint is NAKed
and all reception requests re-
sult in a NAK handshake.
Bit 2 = DTOG_TX Data Toggle, for transmission
transfers.
This bit contains the required value of the toggle
bit (0=DATA0, 1=DATA1) for the next data packet.
DTOG_TX toggles only when the transmitter has
received the ACK signal from the USB host.
DTOG_TX and DTOG_RX are normally updated
by hardware, at the receipt of a relevant PID. They
can be also written by the user, both for testing
purposes and to force a specific (DATA0 or
DATA1) token.
VALID: this endpoint is ena-
bled (if an address match oc-
curs, the USB interface
1
1
handles the transaction).
These bits are written by software. Hardware sets
the STAT_RX and STAT_TX bits to NAK when a
correct transfer has occurred (CTR=1) addressed
to this endpoint, so the software has the time to ex-
amine the received data before acknowledging a
new transaction.
Bits [1:0] = STAT_TX [1:0] Status bits, for trans-
mission transfers.
These bits contain the information about the end-
Note 1:
point status, which is listed below
If a SETUP transaction is received while the status
is different from DISABLED, it is acknowleded and
the two directional status bits are set to NAK by
hardware.
Table 17. Transmission Status Encoding
STAT_TX1 STAT_TX0
Meaning
Note 2:
DISABLED: transmission
transfers cannot be executed.
0
0
When a STALL is answered by the USB device,
the two directional status bits are set to STALL by
hardware.
STALL: the endpoint is stalled
and all transmission requests
result in a STALL handshake.
0
1
NAK: the endpoint is naked
and all transmission requests
result in a NAK handshake.
ENDPOINT
(EP1TXR,
EP5TXR)
TRANSMISSION
EP2TXR, EP3TXR,
REGISTER
EP4TXR,
1
1
0
1
VALID: this endpoint is ena-
bled for transmission.
Read/Write
Reset value: 0000 0000 (00h)
These bits are written by software, but hardware
sets the STAT_TX bits to NAK when a correct
transfer has occurred (CTR=1) addressed to this
endpoint. This allows software to prepare the next
set of data to be transmitted.
7
0
STAT_ STAT_
CTR_T DTOG
_TX
0
0
0
0
X
TX1
TX0
This register is used for controlling Endpoint 1, 2,
3, 4 or 5 transmission. Bits 2:0 are also reset by a
50/102
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ST7SCR
USB INTERFACE (Cont’d)
ENDPOINT
(EP2RXR)
2
RECEPTION
REGISTER
The receiver toggles DTOG_RX only if it receives
acorrect data packet and the packet’s data PID
matches the receiver sequence bit.
Read/Write
Reset value: 0000 0000 (00h)
Bits [1:0] = STAT_RX [1:0] Status bits, for recep-
tion transfers.
7
0
These bits contain the information about the end-
point status, which is listed below:
STAT_ STAT_
CTR_R DTOG
_RX
0
0
0
0
X
RX1
RX0
Table 18. Reception Status Encoding
This register is used for controlling Endpoint 2 re-
ception. Bits 2:0 are also reset by a USB reset, ei-
ther received from the USB or forced through the
FRES bit in the USBCTLR register.
STAT_RX1 STAT_RX0
Meaning
DISABLED: reception trans-
fers cannot be executed.
0
0
STALL: the endpoint is stalled
and all reception requests re-
sult in a STALL handshake.
0
1
Bits [7:4] = Reserved, forced by hardware to 0.
NAK: the endpoint is naked
and all reception requests re-
sult in a NAK handshake.
Bit 3 = CTR_RX Reception Correct Transfer.
This bit is set by hardware when a correct transfer
operation is performed in reception. This bit must
be cleared after that the corresponding interrupt
has been serviced.
1
1
0
1
VALID: this endpoint is ena-
bled for reception.
These bits are written by software, but hardware
sets the STAT_RX bits to NAK when a correct
transfer has occurred (CTR=1) addressed to this
endpoint, so the software has the time to examine
the received data before acknowledging a new
transaction.
Bit 2 = DTOG_RX Data Toggle, for reception
transfers.
It contains the expected value of the toggle bit
(0=DATA0, 1=DATA1) for the next data packet.
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ST7SCR
USB INTERFACE (Cont’d)
RECEPTION COUNTER REGISTER (CNT0RXR)
Read/Write
RECEPTION COUNTER REGISTER (CNT2RXR)
Read/Write
Reset Value: 0000 0000 (00h)
Reset Value: 0000 0000 (00h)
7
0
7
0
0
0
0
0
CNT3 CNT2 CNT1 CNT0
0
CNT6 CNT5 CNT4 CNT3 CNT2 CNT CNT0
This register contains the allocated buffer size for
endpoint 0 reception, setting the maximum
number of bytes the related endpoint can receive
with the next OUT or SETUP transaction. At the
end of a reception, the value of this register is the
max size decremented by the number of bytes re-
ceived (to determine the number of bytes re-
ceived, the software must subtract the content of
this register from the allocated buffer size).
This register contains the allocated buffer size for
endpoint 2 reception, setting the maximum
number of bytes the related endpoint can receive
with the next OUT transaction. At the end of a re-
ception, the value of this register is the max size
decremented by the number of bytes received (to
determine the number of bytes received, the soft-
ware must subtract the content of this register from
the allocated buffer size).
TRANSMISSION COUNTER REGISTER
(CNT0TXR, CNT1TXR, CNT3TXR, CNT4TXR,
CNT5TXR)
TRANSMISSION COUNTER REGISTER
(CNT2TXR)
Read/Write
Read/Write
Reset Value 0000 0000 (00h)
Reset Value 0000 0000 (00h)
7
0
7
0
0
CNT6 CNT5 CNT4 CNT3 CNT2 CNT1 CNT0
0
0
0
0
CNT3 CNT2 CNT1 CNT0
This register contains the number of bytes to be
transmitted by Endpoint 2 at the next IN token ad-
dressed to it.
This register contains the number of bytes to be
transmitted by Endpoint 0, 1, 3, 4 or 5 at the next
IN token addressed to it.
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ST7SCR
USB INTERFACE (Cont’d)
Table 19. USB Register Map and Reset values
Address
(Hex.)
Register
Name
7
6
5
4
3
2
1
0
USBISTR
Reset Value
CTR
0
0
0
SOVR
0
ERR
0
SUSP
0
ESUSP
0
RESET
0
SOF
0
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
USBIMR
Reset Value
CTRM
0
0
0
SOVRM
0
ERRM
0
SUSPM
0
ESUSPM
0
RESETM
0
SOFM
0
USBCTLR
Reset Value
RSM
0
USB_RST
0
RESUME
0
PDWN
1
FSUSP
1
FRES
0
0
0
DADDR
Reset Value
ADD6
0
ADD5
0
ADD4
0
ADD3
0
ADD2
0
ADD1
0
ADD0
0
0
USBSR
Reset Value
PID1
0
PID0
0
IN /OUT
0
EP2
0
EP1
0
EP0
0
0
0
EP0R
Reset Value
CTR0
0
DTOG_TX STAT_TX1 STAT_TX0
0
0
DTOG_RX STAT_RX1 STAT_RX0
0
0
0
0
0
0
CNT0RXR
Reset Value
CNT3
0
CNT2
0
CNT1
0
CNT0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CNT0TXR
Reset Value
CNT3
0
CNT2
0
CNT1
0
CNT0
0
0
0
0
0
0
0
0
0
0
0
0
0
EP1TXR
Reset Value
CTR_TX
0
DTOG_TX STAT_TX1 STAT_TX0
0
0
0
CNT1TXR
Reset Value
CNT3
0
CNT2
0
CNT1
0
CNT0
0
EP2RXR
Reset Value
CTR_RX
0
DTOG_RX STAT_RX1 STAT_RX0
0
0
0
CNT2RXR
Reset Value
CNT6
0
CNT5
0
CNT4
0
CNT3
0
CNT2
0
CNT1
0
CNT0
0
EP2TXR
Reset Value
CTR_TX
0
DTOG_TX STAT_TX1 STAT_TX0
0
0
0
0
0
0
CNT2TXR
Reset Value
CNT6
0
CNT5
0
CNT4
0
CNT3
0
CNT2
0
CNT1
0
CNT0
0
EP3TXR
Reset Value
CTR_TX
0
DTOG_TX STAT_TX1 STAT_TX0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CNT3TXR
Reset Value
CNT3
0
CNT2
0
CNT1
0
CNT0
0
EP4TXR
Reset Value
CTR_TX
0
DTOG_TX STAT_TX1 STAT_TX0
0
0
0
CNT4TXR
Reset Value
CNT3
0
CNT2
0
CNT1
0
CNT0
0
EP5TXR
Reset Value
CTR_TX
0
DTOG_TX STAT_TX1 STAT_TX0
0
0
0
53/102
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ST7SCR
Address
(Hex.)
Register
Name
7
6
5
4
3
2
1
0
CNT3
0
CNT2
0
CNT1
0
CNT0
0
33
34
CNT5TXR
ERRSR
0
0
0
0
0
0
0
0
ERR2
0
ERR1
0
ERR0
0
0
54/102
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ST7SCR
12.4 SMARTCARD INTERFACE (CRD)
12.4.1 Introduction
(CRDIPR) and Smartcard Status (CRDSR) Regis-
ters.
The Smartcard Interface (CRD) provides all the re-
quired signals for acting as a smartcard interface
device.
12.4.2 Main features
■ Support for ISO 7816-3 standard
■ Character mode
The interface is electrically compatible with (and
certifiable to) the ISO7816, EMV, GSM and WHQL
standards.
■ 1 transmit buffer and 1 receive buffer
■ 4-Mhz fixed card clock
Both synchronous (e.g. memory cards) and asyn-
chronous smartcards (e.g. microprocessor cards)
are supported.
■ 11-bit etu (elementary time unit) counter
■ 9-bit guardtime counter
■ 24-bit general purpose waiting time counter
■ Parity generation and checking
The CRD generates the required voltages to be
applied to the smartcard lines.
■ Automatic character repetition on parity error
The power-off sequence is managed by the CRD.
detection in transmission mode
Card insertion or card removal is detected by the
CRD using a card presence switch connected to
the external CRDDET pin. If a card is removed, the
CRD automatically deactivates the smartcard us-
ing the ISO7816 deactivation sequence.
■ Automatic retry on parity error detection in
reception mode
■ Card
power-off
deactivation
sequence
generation
An maskable interrupt is generated when a card is
inserted or removed.
■ Manual mode for driving the card I/O directly for
synchronous protocols
Any malfunction is reported to the microcontroller
via the Smartcard Interrupt Pending Register
12.4.3 Functional Description
Figure 29 gives an overview of the smartcard inter-
face.
Figure 29. Smartcard Interface Block Diagram
CRDC4
CRDC8
4 MHz
CRDVCC
POWER-OFF LOGIC
CRDCCR
11-BIT
ETU COUNTER
CLK
SEL
CRD
CRD CRD CRD
CLK RST VCC
CRD CRD
C8 IO
C4
CRDRST
CRDCLK
COMMUNICATIONS CONTROL
CLOCK
CONTROL
9-BIT GUARDTIME COUNTER
24-BIT WAITING TIME COUNTER
PARITY GENERATION/CHECKING
0
1
CRDIO
CRD INTERRUPT
UART SHIFT REGISTER
UART BIT
CARD DETECTION
LOGIC
CRDDET
UART RECEIVE BUFFER
UART TRANSMIT BUFFER
CRDTXB
CRDRXB
CARD INSERTION/REMOVALINTERRUPT
55/102
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ST7SCR
SMARTCARD INTERFACE (Cont’d)
12.4.3.1 Power Supply Management
Smartcard Power Supply Selection
Elementary Time Unit Counter
This 11-bit counter controls the working frequency
of the UART. The operating frequency of the clock
is the same as the card clock frequency (i.e. 4
MHz).
The Smartcard interface consists of a power sup-
ply output on the CRDVCC pin and a set of card in-
terface I/Os which are powered by the same rail.
A compensation mode can be activated via the
COMP bit of the CRDETU1 register to allow a fre-
quency granularity down to a half-etu.
The card voltage (CRDVCC) is user programma-
ble via the VCARD [1:0] bits in the CRDCR regis-
ter (refer to the Smartcard Interface section).
Note: The decimal value is limited to a half clock
cycle. The bit duration is not fixed. It alternates be-
tween n clock cycles and n-1 clock cycles, where n
is the value to be written in the CRDETU register.
The character duration (10 bits) is also equal to
10*(n - ½) clock cycles This is precise enough to
obtain the character duration specified by the
ISO7816-3 standard.
Four voltage values can be selected:
5V, 3 V, 1.8 V or 0V.
Current Overload Detection and Card Removal
For each voltage, when an overload current is de-
tected (refer to Section 12.4 on page 55), or when
a card is removed, the CRDVCC power supply
output is directly connected to ground.
For example, if F=372 and D=32 (F being the clock
rate conversion factor and D the baud rate adjust-
ment), then etu =11.625 clock cycles.
To achieve this clock rate, compensation mode
must be activated and the etu duration must be
programmed to 12 clock cycles.
12.4.3.2 I/O Driving Modes
Smartcard I/Os are driven in two principal modes:
– UART mode (i.e. when the UART bit of the
CRDCR register is set)
– Manual mode, driven directly by software using
the Smartcard Contact register (i.e. when the
UART bit of the CRDCR register is reset).
The result will be an average character duration of
11.5 clock cycles (for 10 bits).
See Figure 30.
Card power-on activation must driven by software.
Guardtime counter
Card deactivation is handled automatically by the
Power-off functional state machine hardware.
The guardtime counter is a 9-bit counter which
manages the character frame. It controls the dura-
tion between two consecutive characters in trans-
mission.
12.4.3.3 UART Mode
Two registers are connected to the UART shift
register: CRDTXB for transmission and CRDRXB
for reception. They act as buffers to off-load the
CPU.
It is incremented at the etu rate.
No guardtime is inserted for the first character
transmitted.
The guardtime between the last byte received
from the card and the next byte transmitted by the
reader must be handled by software.
A parity checker and generator is coupled to the
shifter.
Character repetition and retry are supported.
The UART is in reception mode by default and
switches automatically to transmission mode
when a byte is written in the buffer.
Priority is given to transmission.
56/102
1
ST7SCR
Figure 30. Compensation Mode
Parity bit
Start bit
Data bits
CRDIO
UART
Working Clock
12cy
11cy
12cy
12cy
12cy
12cy
11cy
11cy
11cy
11cy
F=372
D= 32
57/102
1
ST7SCR
SMARTCARD INTERFACE (Cont’d)
Waiting Time Counter
bit of the last transmitted character.
Then, after transmission of this last character, sig-
nalled by the TXC interrupt, software must write
the CWT value (Character Waiting Time) in the
CRDWT registers. See example in Figure 31.
The Waiting Time counter is a 24-bit counter used
to generate a timeout signal.
The elementary time unit counter acts as a pres-
caler to the Waiting Time counter which is incre-
mented at the etu rate.
Manual mode
The load conditions are:
The Waiting Time Counter can be used in both
UART mode and Manual mode and acts in differ-
ent ways depending on the selected mode.
– A write access to the CRDWT2 register is per-
formed while the UART bit = 0 and the WTEN bit
= 0
The CRDWT2, CRDWT1 and CRDWT0 are load
registers only, the counter itself is not directly ac-
cessible.
In Manual mode, if the WTEN bit of the CRDCR
register is reset, the timer acts as a general pur-
pose timer. The timer is loaded when a write ac-
cess to the CRDWT2 register occurs. The timer
starts when the WTEN bit = 1.
UART Mode
The load conditions are either:
– A Start bit is detected while UART bit =1 and the
WTEN bit =1.
12.4.3.4 Interrupt generator
The Smartcard Interface has 2 interrupt vectors:
– Card Insertion/Removal Interrupt
– CRD Interrupt
or
– A write access to the CRDWT2 register is per-
formed while the UART bit = 1 and the WTEN bit
= 0. In this case, the Waiting Time counter can be
used as a general purpose timer.
The CRD interrupt is cleared when software reads
the CRDIPR register. The Card Insertion/Removal
is an external interrupt and is cleared automatical-
ly by hardware at the end of the interrupt service
routine (IRET instruction).
In UART mode, if the WTEN bit of the CRDCR reg-
ister is set, the counter is loaded automatically on
start bit detection. Software can change the time
out value on-the-fly by writing to the
CRDWT registers. For example, in T=1 mode,
software must load the Block Waiting Time (BWT)
time-out in the CRDWT registers before the start
If an interrupt occurs while the CRDIPR register is
being read, the corresponding bit will be set by
hardware after the read access is done.
Figure 31. Waiting Time Counter Example
Firmware must program BWT
Firmware must program CWT
Reader
CHARn
CHAR1
CHAR0
TXC Interrupt
Smartcard
CHAR0
CHAR1
BWT
CWT
Waiting Time Counter
loaded on start bit
Start bit
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ST7SCR
SMARTCARD INTERFACE (Cont’d)
12.4.3.5 Card detection mechanism
CRDIRF bit in the CRDSR register is set. De-
bouncing is managed by software. After the time
required for debouncing, if the CRDIRF bit is set,
the CRDVCC bit in the CRDCR register is set by
software to apply the selected voltage to the
CRDVCC pin
The CRDDET bit in the CRDCR Register indicates
if the card presence detector (card switch) is open
or closed when a card is inserted. When the
CRDIRF bit of the CRDSR is set, it indicates that a
card is present.
– The microcontroller is in suspend mode and a
card is inserted:
The ST7 is woken up by the interrupt. The card
insertion is then handled in the same way as in
the previous case.
To be able to power-on the smartcard, card pres-
ence is mandatory. Removing the smartcard will
automatically start the ISO7816-3 card deactiva-
tion sequence (see Section 12.4.3.6).
There is no hardware debouncing: The CRDIRF
bit changes whenever the level on the CRDDET
pin changes. The card switch can generate an in-
terrupt which can be used to wake up the device
from suspend mode and for software debouncing.
– The card is removed:
– The CRDIRF bit is reset without hardware de-
bouncing
– A Card Insertion/Removal interrupt is generat-
ed, (if enabled by the CRDIRM bit in the
MISCR2 register)
Three different cases can occur:
– The CRDVCC bit is immediately reset by
hardware, starting the card deactivation se-
quence.
– The microcontroller is in run mode, waiting for
card insertion:
Card insertion generates an interrupt and the
Figure 32. Card detection block diagram
SMARTCARD INTERFACE (CRD)
Pull-up
EDGE DETECTOR
1
0
CRDDET
CARD INSERTION/REMOVAL
Interrupt Request
7
0
DET
CNF
CRDCR
7
0
CRD
IRF
CRDSR
0
7
CRD
IRM
MISCR2
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ST7SCR
SMARTCARD INTERFACE (Cont’d)
12.4.3.6 Card Deactivation Sequence
Figure 33. Card deactivation sequence
This sequence can be activated in two different
ways:
8 CPU Clk cycles
– Automatically as soon as the card presence de-
tector detects a card removal (via the CRDIRF bit
in the CRDSR register, refer to Section 12.4.3.5).
CRDVCC pin
CRDRST pin
CRDCLK pin
CRDIO pin
– By software, writing the CRDVCC bit in the CRD-
CR register, for example:
– If there is a smartcard current overflow (i.e.
when the IOVFF bit in the CRDSR register is
set)
– If the voltage is not within the specified range
(i.e. when the VCARDOK bit in the CRDSR
register is cleared), but software must clear
the CRDVCC bit in the CRDCCR register to
start the deactivation sequence.
CRDC4 pin
CRDC8 pin
When the CRDVCC bit is cleared, this starts the
deactivation sequence. CRDCLK, CRDIO,
CRDC4 and CRDC8 pins are then deactivated as
shown in Figure 33:
Figure 34. Card voltage selection and power OFF block diagram
5V
SMARTCARD
POWER SUPPLY
BLOCK
CRDVCC
Card voltage selection
2
2
2
VCARDVCARD
0
7
7
0
CRD
IRF
VCARD
OK
IOVF
1
0
CRDCR
CRDSR
7
0
0
7
CRD
VCC
VCRD
M
IOVM
CRDCCR
CRDIER
7
0
POWER OFF
BLOCK
VCRD
P
IOVP
CRDIPR
VCARDOK Interrupt Request
IOVF Interrupt Request
60/102
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ST7SCR
SMARTCARD INTERFACE (Cont’d)
Figure 35. Power Off Timing Diagram
VCARD[1:0]
00
11
00
11
Voltage Error
Software Power-Off
V
CARDOK
Power-On
t
Power-On
0.4V
CRDVCC
t
t
OFF
OFF
t
ON
ON
VCRDP Interrupt
VCRDP Interrupt
VCARDOK
Note: Refer to the Electrical Characteristics sec-
tion for the values of t and t
.
OFF
ON
Figure 36. Card clock selection block diagram
POWER OFF
BLOCK
OSC
4 MHz
4 MHz
PLL
ISOCLK
DIV
1
0
CRDCLK
CRDCCR
CLK
SEL
CRD
CLK
61/102
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ST7SCR
SMARTCARD INTERFACE (Cont’d)
12.4.4 Register Description
Bit 2 = WTEN Waiting Time Counter enable.
0: Waiting Time counter stopped. While WTEN =
0, a write access to the CRDWT2 register loads
the Waiting time counter with the load value held
in the CRDWT0, CRDWT1 and CRDWT2 regis-
ters.
SMARTCARD INTERFACE CONTROL REGIS-
TER (CRDCR)
Read/Write
Reset Value: 0000 0000 (00h)
1: Start counter. In UART mode, the counter is au-
tomatically reloaded on start bit detection.
7
0
Bit 1 = CREP Automatic character repetition in
case of parity error.
CRD CRD VCAR
VCAR
D 0
U
ART
WT
EN
C
REP
CO
NV
RST DET
D 1
0: In reception mode: no parity error signal indica-
tion (no retry on parity error).
In transmission mode: no error signal process-
ing. No retransmission of a refused character on
parity error.
1: Automatic parity management:
In transmission mode: up to 4 character repeti-
tions on parity error.
Bit 7 = CRDRST Smartcard Interface Reset.
This bit is set by software to reset the UART of the
Smartcard interface.
0: No Smartcard UART Reset
1: Smartcard UART Reset
In reception mode: up to 4 retries are made on
parity error.
Bit 6 = CRDDET Card Presence Detector.
This bit is set and cleared by software to configure
the card presence detector switch.
The PARF parity error flag is set by hardware if a
parity error is detected.
0: Switch open if no card is present
1: Switch closed if no card is present
If the transmitted character is refused, the PARF
bit is set (but the TXCF bit is reset) and an interrupt
is generated if the PARM bit is set.
Bits [5:4] = VCARD[1:0] Card voltage selection.
Note: If CREP=1, the PARF flag is set at the 5th
error (after 4 character repetitions or 4 retries).
These bits select the card voltage.
Bit 1
Bit 0
Vcard
0V
If CREP=0, the PARF bit is set after the first parity
error.
0
0
1
1
0
1
0
1
1.8V
3V
Bit 0 = CONV ISO convention selection.
0: Direct convention, the B0 bit (LSB) is sent first, a
’1’ is a level 1 on the Card I/O pin, the parity bit is
added after the B7 bit.
1: Inverse convention, the B7 bit (MSB) is sent
first, a ’1’ is a level 0 on Card I/O pin, the parity
bit is added after the B0 bit.
5V
Bit 3 = UART UART Mode Selection.
This bit is set and cleared by software to select
UART or manual mode.
0: CRDIO pin is a copy of the CRDIO bit in the
CRDCCR register (Manual mode).
1: CRDIO pin is the output of the smartcard UART
(UART mode).
Note: To detect the convention used by any card,
apply the following rule. If a card uses the conven-
tion selected by the reader, an RXC event occurs
at answer to reset. Otherwise a parity error also
occurs.
Caution: Before switching from Manual mode to
UART mode, software must set the CRDIO bit in
the CRDCCR register.
62/102
1
ST7SCR
SMARTCARD INTERFACE (Cont’d)
SMARTCARD INTERFACE STATUS REGISTER
(CRDSR)
Read only (Read/Write on some bits)
Bit 3 = WTF Waiting Time Counter overflow Flag.
- Read only
0: The WT Counter has not reached its maximum
Reset Value: 1000 0000 (80h)
value
1: The WT Counter has reached its maximum val-
ue
7
0
CRD
IRF
VCARD
OK
TXBE
F
TXC
F
RXC PAR
IOVF
WTF
Bit 2 = TXCF Transmitted character Flag.
- Read/Write
F
F
This bit is set by hardware and cleared by soft-
ware.
0: No character transmitted
1: A character has been transmitted
Bit 7 =TxBEF Transmit Buffer Empty Flag.
- Read only
0: Transmit buffer is not empty
1: Transmit buffer is empty
Bit 1 = RXCF Received character Flag.
- Read only
This bit is set by hardware and cleared by hard-
ware when the CRDRXB buffer is read.
0: No character received
Bit 6 = CRDIRF Card Insertion/Removal Flag.
- Read only
0: No card is present
1: A character has been received
1: A card is present
Bit 0 = PARF Parity Error Flag.
- Read/Write
This bit is set by hardware and cleared by soft-
ware.
Bit 5 = IOVF Card Overload Current Flag.
- Read only
0: No card overload current
1: Card overload current
0: No parity error
1: Parity error
Bit 4 = VCARDOK Card voltage status Flag.
Note: When a character is received, the RXCF bit
is always set.When a character is received with a
parity error, the PARF bit is also set.
- Read only
0: The card voltage is not in the specified range
1: The card voltage is within the specified range
63/102
ST7SCR
SMARTCARD INTERFACE (Cont’d)
SMARTCARD CONTACT CONTROL REGISTER
(CRDCCR)
Read/Write
Bit 3 = CRDIO CRDIO pin control.
This bit is active only if the UART bit in the CRDCR
Register is reset. Reading this bit returns the value
present on the CRDIO pin.
Reset Value: 00xx xx00 (xxh)
7
0
If the UART bit is reset:
CLK
SEL
-
CRD
C8
CRD
C4
CRD
IO
CRD
CLK
CRD
RST
CRD
VCC
– Writing “0” forces a low level on the CRDIO pin
– Writing “1” forces the CRDIO pin to open drain
Hi-Z.
Note: To modify the content of this register, the LD
instruction must be used (do not use the BSET
and BRES instructions).
Bit 2 = CRDCLK CRDCLK pin control
This bit is active only if the CLKSEL bit of the CRD-
CCR register is reset. Reading this bit returns the
value present in the register (not the CRDCLK pin
value).
Bit 7 = CLKSEL Card clock selection.
This bit is set and cleared by software.
0: The signal on the CRDCLK pin is a copy of the
CRDCLK bit.
When the CLKSEL bit is reset:
0: Level 0 to be applied on CRDCLK pin.
1: Level 1 to be applied on CRDCLK pin.
1: The signal on the CRDCLK pin is a 4MHz fre-
quency clock.
Note: To ensure that the clock stops at a given
value, write the desired value in the CRDCLK bit
prior to changing the CLKSEL bit from 1 to 0.
Note: To start the clock at a known level, the CRD-
CLK bit should be changed before the CLKSEL
bit.
Bit 1 = CRDRST CRDRST pin control.
Bit 6 = Reserved, must be kept cleared.
Reading this bit returns the value present on the
CRDRST pin. Writing this bit outputs the bit value
on the pin.
Bit 5 = CRDC8 CRDC8 pin control.
Reading this bit returns the value present on the
CRDC8 pin. Writing this bit outputs the bit value on
the pin.
Bit 0 = CRDVCC CRDVCC Pin Control.
This bit is set and cleared by software and forced
to 0 by hardware when no card is present
(CRDIRF bit=0).
0: No voltage to be applied on the CRDVCC pin.
1: The selected voltage must be applied on the
CRDVCC pin.
Bit 4 = CRDC4 CRDC4 pin control
Reading this bit returns the value present on the
CRDC4 pin. Writing this bit outputs the bit value on
the pin.
Figure 37. Smartcard I/O Pin Structure
CRDCCR
I/O PIN
DATA BUS
REGISTER
64/102
ST7SCR
SMARTCARD INTERFACE (Cont’d)
SMARTCARD ELEMENTARY TIME UNIT REG-
ISTER (CRDETUx)
GUARDTIME REGISTER (CRDGTx)
CRDGT1
Read/Write
CRDETU1
Read/Write
Reset Value: 0000 0000 (00h)
Reset Value: 0000 0001 (01h)
7
0
7
0
0
0
0
0
0
0
0
GT8
COMP
0
0
0
0
ETU10
ETU9 ETU8
CRDGT0
Read/Write
Reset Value: 0000 1100 (0Ch)
Bit 7 = COMP Elementary Time Unit Compensa-
tion.
0: Compensation mode disabled.
1: Compensation mode enabled. To allow non in-
teger value, one clock cycle is subtracted from
the ETU value on odd bits. See Figure 30.
7
0
GT7
GT6
GT5
GT4
GT3
GT2
GT1
GT0
Bit [6:3] = Reserved
Software writes the Guardtime value in this regis-
ter. The value is loaded at the end of the current
Guard period.
Bits 2:0 = ETU [10:8] ETU value in card clock cy-
cles.
GT: Guard Time: Minimum time between two con-
secutive start bits in transmission mode. Value ex-
pressed in Elementary Time Units (from 11 to
511).
Writing CRDETU1 register reloads the ETU coun-
ter.
The Guardtime between the last byte received
from the card and the next byte transmitted by the
reader must be handled by software.
CRDETU0
Read/Write
Reset Value: 0111 0100 (74h)
7
0
ETU7 ETU6 ETU5 ETU4 ETU3 ETU2 ETU1 ETU0
Bits 7:0 = ETU [7:0] ETU value in card clock cy-
cles.
Note: The value of ETU [10:0] must in the range
12 to 2047. To write 2048, clear all the bits.
65/102
ST7SCR
SMARTCARD INTERFACE (Cont’d)
CRDWT0
CHARACTER WAITING TIME REGISTER (CRD-
WTx)
Read/Write
Reset Value: 1000 0000 (80h)
CRDWT2
7
0
Read/Write
Reset Value: 0000 0000 (00h)
.
WT 7 WT6
WT5
WT4 WT3 WT2 WT1 WT0
7
0
WT: Character waiting time value expressed in
ETU (0 / 16777215).
WT
23
WT
22
WT
21
WT
20
WT
19
WT
18
WT
17
WT
16
The CRDWT0, CRDWT1 and CRDWT2 registers
hold the load value of the Waiting Time counter.
Note: A read operation does not return the counter
value.
CRDWT1
Read/Write
Reset Value: 0010 0101 (25h)
This counter can be used as a general purpose
timer.
7
0
If the WTEN bit of the CRDCR register is reset, the
counter is reloaded when a write access in the
CRDWT2 register occurs. It starts when the
WTEN bit is set.
WT
15
WT
14
WT
13
WT
12
WT
11
WT
10
WT9 WT8
If the WTEN bit in the CRDCR register is set and if
UART mode is activated, the counter acts as an
autoreload timer. The timer is reloaded when a
start bit is sent or detected. An interrupt is generat-
ed if the timer overflows between two consecutive
start bits.
Note: When loaded with a 0 value, the Waiting
Time counter stays at 0 and the WTF bit = 1.
66/102
ST7SCR
SMARTCARD INTERFACE (Cont’d)
Bit 4= VCRDM Card Voltage Error Interrupt Mask.
SMARTCARD INTERRUPT ENABLE REGISTER
(CRDIER)
Read/Write
This bit is set and cleared by software to enable or
disable the VCRD interrupt.
Reset Value: 0000 0000 (00h)
0: VCRD interrupt disabled
1: VCRD interrupt enabled
7
0
Bit 3 = WTM Waiting Timer Interrupt Mask.
This bit is set and cleared by software to enable or
disable the Waiting Timer overflow interrupt.
0: WT interrupt disabled
TXBE
M
-
IOVF VCRDM WTM TXC RXC PAR
M
M
M
M
1: WT interrupt enabled
Bit 7 = TXBEM Transmit buffer empty interrupt
mask.
Bit 2 =TXCM Transmitted Character Interrupt
Mask
This bit is set and cleared by software to enable or
disable the TXC interrupt.
0: TXC interrupt disabled
This bit is set and cleared by software to enable or
disable the TXBE interrupt.
0: TXBE interrupt disabled
1: TXBE interrupt enabled
1: TXC interrupt enabled
Bit 6 = Reserved.
Bit 1 =RXCM Received Character Interrupt Mask
This bit is set and cleared by software to enable or
disable the RXC interrupt.
0: RXC interrupt disabled
1: RXC interrupt enabled
Bit 5 = IOVFM Card Overload Current Interrupt
Mask.
This bit is set and cleared by software to enable or
disable the IOVF interrupt.
0: IOVF interrupt disabled
1: IOVF interrupt enabled
Bit 0 = PARM Parity Error Interrupt. Mask
This bit is set and cleared by software to enable or
disable the parity error interrupt for parity error.
0: PAR interrupt disabled
1: PAR error interrupt enabled
67/102
ST7SCR
SMARTCARD INTERFACE (Cont’d)
SMARTCARD INTERRUPT PENDING REGIS-
TER (CRDIPR)
Read Only
that the CRDTXB buffer can be loaded with the
next character to be transmitted.
0: No TXC interrupt pending
Reset Value: 0000 0000 (00h)
1: TXC interrupt pending
7
0
Bit 1 = RXCP Received character interrupt pend-
ing.
TXBE
P
-
IOVF VCRD WTP TXCP RXC
PAR
P
P
P
P
This bit is set by hardware when a character is re-
ceived and the RXCM bit is set. It indicates that the
CRDRXB buffer can be read.
This register indicates the interrupt source. It is
cleared after a read operation.
0: No RXC interrupt pending
1: RXC interrupt pending
Bit 7 = TXBEP Transmit buffer empty interrupt
pending.
This bit is set by hardware when a TXBE event oc-
curs and the TXBEM bit is set.
0: No TXBE interrupt pending
Bit 0 = PARP Parity Error interrupt pending.
This bit is set by hardware when a PAR event oc-
curs and the PARM bit is set.
0: No PAR interrupt pending
1: TXBE interrupt pending
1: PAR interrupt pending
Bit 6 = Reserved.
SMARTCARD TRANSMIT BUFFER (CRDTXB)
Read/Write
Reset Value: 0000 0000 (00h)
Bit 5 = IOVF Card Overload Current interrupt
pending.
This bit is set by hardware when a IOVF event oc-
curs and the IOVFM bit is set.
7
0
0: No IOVF interrupt pending
1: IOVF interrupt pending
TB7 TB6 TB5 TB4 TB3 TB2 TB1 TB0
Bit 4 = VCRDP Card Voltage Error interrupt pend-
ing.
This register is used to send a byte to the smart-
card.
This bit is set by hardware when the VCARDOK bit
goes from 1 to 0 while the VCRDM bit is set.
0: No VCRD interrupt pending.
SMARTCARD RECEIVE BUFFER (CRDRXB)
Read
Reset Value: 0000 0000 (00h)
1: VCRD interrupt pending.
7
0
Bit 3 = WTP Waiting Timer Overflow interrupt
pending.
RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0
This bit is set by hardware when a WTP event oc-
curs and the WTPM bit is set.
0: No WT interrupt pending
This register is used to receive a byte from the
smartcard.
1: WT interrupt pending
Bit 2 = TXCP Transmitted character interrupt
pending.
This bit is set by hardware when a character is
transmitted and the TXCM bit is set. It indicates
68/102
ST7SCR
SMARTCARD INTERFACE (Cont’d)
Table 20. Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
CRDCR
Reset Value
CRDRST DETCNF VCARD1 VCARD0
UART
0
WTEN
0
CREP
0
CONV
0
00
01
02
0
0
0
0
CRDSR
Reset Value
TXBEF
1
CRDIRF
0
IOVF VCARDOK WTF
TXCF
0
RXCF
0
PARF
0
0
0
0
CRDCCR
Reset Value
CLKSEL
0
-
0
CRDC8
x
CRDC4
x
CRDIO CRDCLK CRDRST CRDVCC
x
0
x
0
COMP
0
-
0
-
0
-
0
-
0
ETU10
1
ETU9
0
ETU8
0
CRDETU1
Reset Value
03
04
05
06
07
08
09
CRDETU0
Reset Value
ETU7
0
ETU6
1
ETU5
1
ETU4
1
ETU3
0
ETU2
1
ETU1
0
ETU0
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
GT8
0
CRDGT1
Reset Value
CRDGT0
Reset Value
GT7
0
GT6
0
GT5
0
GT4
0
GT3
1
GT2
1
GT1
0
GT0
0
WT23
0
WT22
0
WT21
0
WT20
0
WT19
0
WT18
0
WT17
0
WT16
0
CRDWT2
Reset Value
WT15
0
WT14
0
WT13
1
WT12
0
WT11
0
WT10
1
WT9
0
WT8
1
CRDWT1
Reset Value
WT7
1
WT6
0
WT5
0
WT4
0
WT3
0
WT2
0
WT1
0
WT0
0
CRDWT0
Reset Value
CRDIER
Reset Value
TXBEM
0
-
0
IOVM
0
VCRDM
0
WTM
0
TXCM
0
RXCM
0
PARM
0
0A
0B
CRDIPR
Reset Value
TXBEP
0
-
0
IOVP
0
VCRDP
WTP
0
TXCP
0
RXCP
0
PARP
0
TB7
0
TB6
0
TB5
0
TB4
0
TB3
0
TB2
0
TB1
0
TB0
0
CRDTXB
Reset Value
0C
0D
RB7
0
RB6
0
RB5
0
RB4
0
RB3
0
RB2
0
RB1
0
RB0
0
CRDRXB
Reset Value
69/102
ST7SCR
13 INSTRUCTION SET
13.1 ST7 ADDRESSING MODES
so, most of the addressing modes may be subdi-
vided in two sub-modes called long and short:
The ST7 Core features 17 different addressing
modes which can be classified in 7 main groups:
– Long addressing mode is more powerful be-
cause it can use the full 64 Kbyte address space,
however it uses more bytes and more CPU cy-
cles.
Addressing Mode
Inherent
Example
nop
– Short addressing mode is less powerful because
it can generally only access page zero (0000h -
00FFh range), but the instruction size is more
compact, and faster. All memory to memory in-
structions use short addressing modes only
(CLR, CPL, NEG, BSET, BRES, BTJT, BTJF,
INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP)
Immediate
Direct
ld A,#$55
ld A,$55
ld A,($55,X)
ld A,([$55],X)
jrne loop
Indexed
Indirect
Relative
Bit operation
bset byte,#5
The ST7 Assembler optimizes the use of long and
short addressing modes.
The ST7 Instruction set is designed to minimize
the number of bytes required per instruction: To do
Table 21. ST7 Addressing Mode Overview
Pointer
Address
(Hex.)
Pointer Size
(Hex.)
Length
(Bytes)
Mode
Syntax
Destination
Inherent
Immediate
Short
Long
nop
+ 0
ld A,#$55
+ 1
+ 1
+ 2
+ 0
+ 1
+ 2
+ 2
+ 2
+ 2
+ 2
+ 1
+ 2
+ 1
+ 2
+ 2
+ 3
Direct
ld A,$10
00..FF
Direct
ld A,$1000
ld A,(X)
0000..FFFF
00..FF
No Offset
Short
Long
Direct
Indexed
Indexed
Indexed
Direct
ld A,($10,X)
ld A,($1000,X)
ld A,[$10]
00..1FE
0000..FFFF
00..FF
Direct
Short
Long
Indirect
Indirect
Indirect
Indirect
Direct
00..FF
00..FF
00..FF
00..FF
byte
word
byte
word
ld A,[$10.w]
ld A,([$10],X)
ld A,([$10.w],X)
jrne loop
0000..FFFF
00..1FE
0000..FFFF
PC+/-127
PC+/-127
00..FF
Short
Long
Indexed
Indexed
Relative
Relative
Bit
Indirect
Direct
jrne [$10]
00..FF
00..FF
00..FF
byte
byte
byte
bset $10,#7
bset [$10],#7
Bit
Indirect
Direct
00..FF
Bit
Relative btjt $10,#7,skip
Relative btjt [$10],#7,skip
00..FF
Bit
Indirect
00..FF
70/102
ST7SCR
INSTRUCTION SET OVERVIEW (Cont’d)
13.1.1 Inherent
13.1.3 Direct
All Inherent instructions consist of a single byte.
The opcode fully specifies all the required informa-
tion for the CPU to process the operation.
In Direct instructions, the operands are referenced
by their memory address.
The direct addressing mode consists of two sub-
modes:
Inherent Instruction
Function
No operation
Direct (short)
NOP
The address is a byte, thus requires only one byte
after the opcode, but only allows 00 - FF address-
ing space.
TRAP
S/W Interrupt
Wait For Interrupt (Low Pow-
er Mode)
WFI
Direct (long)
Halt Oscillator (Lowest Power
Mode)
HALT
The address is a word, thus allowing 64 Kbyte ad-
dressing space, but requires 2 bytes after the op-
code.
RET
Sub-routine Return
Interrupt Sub-routine Return
Set Interrupt Mask (level 3)
Reset Interrupt Mask (level 0)
Set Carry Flag
IRET
SIM
13.1.4 Indexed (No Offset, Short, Long)
RIM
In this mode, the operand is referenced by its
memory address, which is defined by the unsigned
addition of an index register (X or Y) with an offset.
SCF
RCF
Reset Carry Flag
RSP
Reset Stack Pointer
Load
The indirect addressing mode consists of three
sub-modes:
LD
CLR
Clear
Indexed (No Offset)
PUSH/POP
INC/DEC
TNZ
Push/Pop to/from the stack
Increment/Decrement
Test Negative or Zero
1 or 2 Complement
Byte Multiplication
There is no offset, (no extra byte after the opcode),
and allows 00 - FF addressing space.
Indexed (Short)
CPL, NEG
MUL
The offset is a byte, thus requires only one byte af-
ter the opcode and allows 00 - 1FE addressing
space.
SLL, SRL, SRA, RLC,
RRC
Shift and Rotate Operations
Swap Nibbles
Indexed (long)
The offset is a word, thus allowing 64 Kbyte ad-
dressing space and requires 2 bytes after the op-
code.
SWAP
13.1.2 Immediate
Immediate instructions have two bytes, the first
byte contains the opcode, the second byte con-
tains the operand value.
13.1.5 Indirect (Short, Long)
The required data byte to do the operation is found
by its memory address, located in memory (point-
er).
Immediate Instruction
Function
LD
Load
The pointer address follows the opcode. The indi-
rect addressing mode consists of two sub-modes:
CP
Compare
BCP
Bit Compare
Indirect (short)
AND, OR, XOR
ADC, ADD, SUB, SBC
Logical Operations
Arithmetic Operations
The pointer address is a byte, the pointer size is a
byte, thus allowing 00 - FF addressing space, and
requires 1 byte after the opcode.
Indirect (long)
The pointer address is a byte, the pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.
71/102
ST7SCR
INSTRUCTION SET OVERVIEW (Cont’d)
13.1.6 Indirect Indexed (Short, Long)
13.1.7 Relative mode (Direct, Indirect)
This is a combination of indirect and short indexed
addressing modes. The operand is referenced by
its memory address, which is defined by the un-
signed addition of an index register value (X or Y)
with a pointer value located in memory. The point-
er address follows the opcode.
This addressing mode is used to modify the PC
register value, by adding an 8-bit signed offset to
it.
Available Relative
Direct/Indirect
Instructions
Function
The indirect indexed addressing mode consists of
two sub-modes:
JRxx
CALLR
Conditional Jump
Call Relative
Indirect Indexed (Short)
The pointer address is a byte, the pointer size is a
byte, thus allowing 00 - 1FE addressing space,
and requires 1 byte after the opcode.
The relative addressing mode consists of two sub-
modes:
Relative (Direct)
Indirect Indexed (Long)
The offset is following the opcode.
Relative (Indirect)
The pointer address is a byte, the pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.
The offset is defined in memory, which address
follows the opcode.
Table 22. Instructions Supporting Direct,
Indexed, Indirect and Indirect Indexed
Addressing Modes
Long and Short
Function
Instructions
LD
Load
CP
Compare
AND, OR, XOR
Logical Operations
Arithmetic Additions/Sub-
stractions operations
ADC, ADD, SUB, SBC
BCP
Bit Compare
Short Instructions
Only
Function
CLR
Clear
INC, DEC
TNZ
Increment/Decrement
Test Negative or Zero
1 or 2 Complement
Bit Operations
CPL, NEG
BSET, BRES
Bit Test and Jump Opera-
tions
BTJT, BTJF
SLL, SRL, SRA, RLC,
RRC
Shift and Rotate Opera-
tions
SWAP
Swap Nibbles
CALL, JP
Call or Jump subroutine
72/102
ST7SCR
INSTRUCTION SET OVERVIEW (Cont’d)
13.2 INSTRUCTION GROUPS
The ST7 family devices use an Instruction Set
consisting of 63 instructions. The instructions may
be subdivided into 13 main groups as illustrated in
the following table:
Load and Transfer
LD
CLR
POP
DEC
TNZ
OR
Stack operation
PUSH
INC
RSP
BCP
Increment/Decrement
Compare and Tests
Logical operations
CP
AND
BSET
BTJT
ADC
SLL
XOR
CPL
NEG
Bit Operation
BRES
BTJF
ADD
SRL
JRT
Conditional Bit Test and Branch
Arithmetic operations
Shift and Rotates
SUB
SRA
JRF
SBC
RLC
JP
MUL
RRC
CALL
SWAP
CALLR
SLA
Unconditional Jump or Call
Conditional Branch
JRA
JRxx
TRAP
SIM
NOP
RET
Interruption management
Condition Code Flag modification
WFI
RIM
HALT
SCF
IRET
RCF
Using a pre-byte
The instructions are described with one to four op-
codes.
These prebytes enable instruction in Y as well as
indirect addressing modes to be implemented.
They precede the opcode of the instruction in X or
the instruction using direct addressing mode. The
prebytes are:
In order to extend the number of available op-
codes for an 8-bit CPU (256 opcodes), three differ-
ent prebyte opcodes are defined. These prebytes
modify the meaning of the instruction they pre-
cede.
PDY 90
Replace an X based instruction
using immediate, direct, indexed, or inherent ad-
dressing mode by a Y one.
The whole instruction becomes:
PIX 92
Replace an instruction using di-
PC-2
PC-1
PC
End of previous instruction
Prebyte
rect, direct bit, or direct relative addressing mode
to an instruction using the corresponding indirect
addressing mode.
opcode
It also changes an instruction using X indexed ad-
dressing mode to an instruction using indirect X in-
dexed addressing mode.
PC+1
Additional word (0 to 2) according
to the number of bytes required to compute the ef-
fective address
PIY 91
Replace an instruction using X in-
direct indexed addressing mode by a Y one.
73/102
ST7SCR
INSTRUCTION SET OVERVIEW (Cont’d)
Mnemo
ADC
ADD
AND
BCP
Description
Add with Carry
Function/Example
A = A + M + C
A = A + M
Dst
Src
I1
H
H
H
I0
N
N
N
N
N
Z
Z
Z
Z
Z
C
C
C
A
M
Addition
A
M
M
M
Logical And
A = A . M
A
Bit compare A, Memory
Bit Reset
tst (A . M)
A
BRES
BSET
BTJF
BTJT
CALL
CALLR
CLR
bres Byte, #3
bset Byte, #3
btjf Byte, #3, Jmp1
btjt Byte, #3, Jmp1
M
M
M
M
Bit Set
Jump if bit is false (0)
Jump if bit is true (1)
Call subroutine
Call subroutine relative
Clear
C
C
reg, M
reg
0
N
N
N
1
Z
Z
Z
CP
Arithmetic Compare
One Complement
Decrement
tst(Reg - M)
A = FFH-A
dec Y
M
C
1
CPL
reg, M
reg, M
DEC
HALT
IRET
INC
Halt
1
0
Interrupt routine return
Increment
Pop CC, A, X, PC
inc X
I1
H
I0
N
N
Z
Z
C
reg, M
JP
Absolute Jump
Jump relative always
Jump relative
Never jump
jp [TBL.w]
JRA
JRT
JRF
jrf *
JRIH
JRIL
Jump if Port B INT pin = 1 (no Port B Interrupts)
Jump if Port B INT pin = 0 (Port B interrupt)
JRH
Jump if H = 1
H = 1 ?
JRNH
JRM
Jump if H = 0
H = 0 ?
Jump if I1:0 = 11
Jump if I1:0 <> 11
Jump if N = 1 (minus)
Jump if N = 0 (plus)
Jump if Z = 1 (equal)
I1:0 = 11 ?
I1:0 <> 11 ?
N = 1 ?
JRNM
JRMI
JRPL
JREQ
JRNE
JRC
N = 0 ?
Z = 1 ?
Jump if Z = 0 (not equal) Z = 0 ?
Jump if C = 1
Jump if C = 0
Jump if C = 1
C = 1 ?
JRNC
JRULT
C = 0 ?
Unsigned <
Jmp if unsigned >=
Unsigned >
JRUGE Jump if C = 0
JRUGT Jump if (C + Z = 0)
74/102
ST7SCR
INSTRUCTION SET OVERVIEW (Cont’d)
Mnemo
JRULE
LD
Description
Jump if (C + Z = 1)
Load
Function/Example
Unsigned <=
dst <= src
Dst
Src
I1
H
I0
N
N
N
N
N
Z
Z
Z
Z
Z
C
reg, M
A, X, Y
reg, M
M, reg
X, Y, A
MUL
NEG
NOP
OR
Multiply
X,A = X * A
neg $10
0
0
Negate (2’s compl)
No Operation
OR operation
C
A = A + M
pop reg
pop CC
push Y
C = 0
A
M
reg
CC
M
M
POP
Pop from the Stack
M
I1
1
H
I0
0
C
0
PUSH
RCF
RET
RIM
Push onto the Stack
Reset carry flag
Subroutine Return
Enable Interrupts
Rotate left true C
Rotate right true C
Reset Stack Pointer
Substract with Carry
Set carry flag
reg, CC
I1:0 = 10 (level 0)
C <= A <= C
C => A => C
S = Max allowed
A = A - M - C
C = 1
RLC
RRC
RSP
SBC
SCF
SIM
reg, M
reg, M
N
N
Z
Z
C
C
A
M
N
Z
C
1
Disable Interrupts
Shift left Arithmetic
Shift left Logic
I1:0 = 11 (level 3)
C <= A <= 0
C <= A <= 0
0 => A => C
A7 => A => C
A = A - M
1
1
SLA
reg, M
reg, M
reg, M
reg, M
A
N
N
0
Z
Z
Z
Z
Z
Z
Z
C
C
C
C
C
SLL
SRL
SRA
SUB
SWAP
TNZ
TRAP
WFI
Shift right Logic
Shift right Arithmetic
Substraction
N
N
N
N
M
M
SWAP nibbles
A7-A4 <=> A3-A0
tnz lbl1
reg, M
Test for Neg & Zero
S/W trap
S/W interrupt
1
1
1
0
Wait for Interrupt
Exclusive OR
XOR
A = A XOR M
A
N
Z
75/102
ST7SCR
14 ELECTRICAL CHARACTERISTICS
14.1 ABSOLUTE MAXIMUM RATINGS
This product contains devices for protecting the in-
puts against damage due to high static voltages,
however it is advisable to take normal precautions
to avoid appying any voltage higher than the spec-
ified maximum rated voltages.
Power Considerations. The average chip-junc-
tion temperature, T , in Celsius can be obtained
J
from:
T =
TA + PD x RthJA
Ambient Temperature.
J
Where: T =
A
RthJA =Package thermal resistance
(junction-to ambient).
For proper operation it is recommended that V
I
.
and V be higher than V
and lower than V
O
SS
DD
P =
P
+ P
.
Reliability is enhanced if unused inputs are con-
D
INT
PORT
P
= I x V (chip internal power).
nected to an appropriate logic voltage level (V
or V ).
INT
DD DD
DD
P
=Port power dissipation
determined by the user)
SS
PORT
Stresses above those listed as “absolute maxi-
mum ratings” may cause permanent damage to
the device. This is a stress rating only and func-
tional operation of the device at these conditions is
not implied. Exposure to maximum rating for ex-
tended periods may affect device reliability.
Symbol
- V
Ratings
Value
Unit
V
Supply voltage
Input voltage
6.0
V
V
V
V
V
DD
SS
V
VSS - 0.3 to VDD + 0.3
IN
V
Output voltage
ESD susceptibility
VSS - 0.3 to VDD + 0.3
OUT
ESD
ESDCard
2000
4000
250
ESD susceptibility for card pads
Total current into V (source)
I
VDD_i
DD_i
mA
I
Total current out of V
(sink)
250
VSS_i
SS_i
General Warning: Direct connection to V or V of the I/O pins could damage the device in case of program counter
DD
SS
corruption (due to unwanted change of the I/O configuration). To guarantee safe conditions, this connection has to be
done through a typical 10KΩ pull-up or pull-down resistor.
Thermal Characteristics
Symbol
Ratings
Value
Unit
Package thermal resistance
TQFP64
SO24
60
80
R
°C/W
thJA
TJmax
TSTG
PD
Max. junction temperature
150
-65 to +150
500
°C
°C
Storage temperature range
Power dissipation (maximum value)
mW
76/102
ST7SCR
14.2 RECOMMENDED OPERATING CONDITIONS
GENERAL
Symbol
Parameter
Supply voltage
Conditions
Min
Typ
Max
Unit
V
4.0
5.5
V
DD
f
External clock source
4
MHz
°C
OSC
T
Ambient temperature range
0
70
A
(Operating conditions TA = 0 to +70°C unless otherwise specified)
CURRENT INJECTION ON I/O PORT AND CONTROL PINS
Symbol
Parameter
Conditions
> V
Min
Typ
Max
Unit
V
EXTERNAL
DD
(Standard I/Os)
(1)
I
Total positive injected current
20
mA
INJ+
V
> V
EXTERNAL
SC_PWR
(Smartcard I/Os)
V
< V
EXTERNAL
SS
(2,3)
I
Total negative injected current
mA
Digital pins
Analog pins
INJ-
20
Note 1: Positive injection
The I is done through protection diodes insulated from the substrate of the die.
INJ+
Note 2: For SmartCard I/Os, V
Note 3: Negative injection
has to be considered.
CARD
– The I
is done through protection diodes NOT INSULATED from the substrate of the die. The draw-
INJ-
back is a small leakage (few µA) induced inside the die when a negative injection is performed. This leak-
age is tolerated by the digital structure, but it acts on the analog line according to the impedance versus
a leakage current of few µA (if the MCU has an AD converter). The effect depends on the pin which is
submitted to the injection. Of course, external digital signals applied to the component must have a max-
imum impedance close to 50KΩ.
Location of the negative current injection:
– Pure digital pins can tolerate 1.6mA. In addition, the best choice is to inject the current as far as possible
from the analog input pins.
General Note: When several inputs are submitted to a current injection, the maximum I
the positive (resp. negative) currrents (instantaneous values).
is the sum of
INJ
77/102
ST7SCR
RECOMMENDED OPERATING CONDITIONS (Cont’d)
o
(T =0 to +70 C, V -V =5.5V unless otherwise specified)
A
DD SS
Parameter
Supply current in RUN mode
Symbol
Conditions
= 4MHz
Min
Typ.
Max
Unit
1)
2)
10
3
15
mA
mA
f
OSC
Supply current in WAIT mode
External I
= 0mA
LOAD
I
Supply current in suspend mode
Supply current in HALT mode
500
100
DD
(USB transceiver enabled)
External I = 0mA
µA
LOAD
50
(USB transceiver disabled)
Notes:
1. CPU running with memory access, all I/O pins in input mode with a static value at V or V ; clock input (OSC1)
DD
SS
driven by external square wave.
2. All I/O pins in input mode with a static value at V or V ; clock input (OSC1) driven by external square wave.
DD
SS
o
T = 0... +70 C, voltages are referred to V unless otherwise specified:
SS
I/O PORT PINS
Symbol
Parameter
Input low level voltage
Conditions
Min
Typ
Max
Unit
V
0.3xVDD
IL
V
V
Input high level voltage
0.7xVDD
IH
1)
V
Schmidt trigger voltage hysteresis
400
mV
HYS
I=-5mA
I=-2mA
I=3mA
1.3
0.4
Output low level voltage
for Standard I/O port pins
V
OL
V
V
Output high level voltage
Input leakage current
V
-0.8
OH
DD
I
V
<V <V
DD
1
µA
L
SS
PIN
R
Pull-up equivalent resistor
50
90
8
170
KΩ
PU
Output high to low level fall time
for high sink I/O port pins (Port D)
t
6
13
2)
OHL
OHL
Output high to low level fall time
t
for standard I/O port pins (Port A, B or
18
23
2)
C =50pF
ns
l
C)
2)
t
t
Output L-H rise time (Port D)
7
19
1
9
14
28
OLH
Output L-H rise time for standard I/O
2)
OLH
port pins (Port A, B or C)
t
External interrupt pulse time
t
CPU
ITEXT
Note 1 : Hysteresis voltage between Schmitt trigger switching levels. Based on characterisation results, not tested.
Note 2 : Guaranteed by Characterization
LED PINS
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
I
I
Low current
High current
Vpad > VDD-2.4
Vpad > VDD-2.4
2
4
Lsink
mA
5.6
8.4
Lsink
78/102
ST7SCR
14.3 SUPPLY AND RESET CHARACTERISTICS
o
(T = 0 to +70 C, V - V = 5.5V unless otherwise specified.
DD
SS
LOW VOLTAGE DETECTOR AND SUPERVISOR (LVDS)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Reset release threshold
V
3.7
3.9
V
IT+
(V rising)
DD
Reset generation threshold
V
3.3
20
3.5
V
IT-
(V falling)
DD
V
V
Hysteresis V - V
IT-
200
mV
hys
IT+
V
rise time rate
ms/V
tPOR
DD
14.4 CLOCK AND TIMING CHARACTERISTICS
14.4.1 General Timings
(Operating conditions TA = 0 to +70°C unless otherwise specified)
1)
Symbol
Parameter
Conditions
Min
2
Typ
Max
12
Unit
tCPU
ns
3
t
Instruction cycle time
c(INST)
f
f
=4MHz
500
10
750
3000
22
CPU
2)
tCPU
µs
Interrupt reaction time
= ∆t + 10
t
v(IT)
t
=4MHz
2.5
5.5
v(IT)
c(INST)
CPU
* ∆tINST is the number of tCPU to finish the current instruction execution.
14.4.2 External Clock Source
Symbol
Parameter
Conditions
Min
0.7xV
Typ
Max
Unit
V
OSC1 input pin high level voltage
OSC1 input pin low level voltage
V
DD
OSC1H
DD
SS
V
V
V
0.3xV
OSC1L
DD
t
t
3)
w(OSC1H)
see Figure 38
OSC1 high or low time
15
w(OSC1L)
ns
t
t
3)
r(OSC1)
OSC1 rise or fall time
15
f(OSC1)
I
OSCx Input leakage current
V
≤V ≤V
DD
±1
µA
L
SS
IN
79/102
ST7SCR
CLOCK AND TIMING CHARACTERISTICS (Cont’d)
Figure 38. Typical Application with an External Clock Source
90%
V
V
OSC1H
OSC1L
10%
t
t
w(OSC1H)
t
t
w(OSC1L)
f(OSC1)
r(OSC1)
OSC2
Not connected internally
f
OSC
EXTERNAL
CLOCK SOURCE
I
L
OSC1
ST7XXX
Notes:
1. Data based on typical application software.
2. Time measured between interrupt event and interrupt vector fetch. ∆tc(INST) is the number of tCPU cycles needed to finish
the current instruction execution.
3. Data based on design simulation and/or technology characteristics, not tested in production.
80/102
ST7SCR
CLOCK AND TIMING CHARACTERISTICS (Cont’d)
14.4.3 Crystal Resonator Oscillators
The ST7 internal clock is supplied with one Crystal
resonator oscillator. All the information given in
this paragraph are based on characterization re-
sults with specified typical external componants. In
the application, the resonator and the load capaci-
tors have to be placed as close as possible to the
oscillator pins in order to minimize output distortion
and start-up stabilization time. Refer to the crystal
resonator manufacturer for more details (frequen-
cy, package, accuracy...).
Symbol
Parameter
Oscillator Frequency
Feedback resistor
Conditions
Min
Typ
Max
Unit
MHz
kΩ
3)
f
MP: Medium power oscillator
4
OSC
R
20
40
F
Recommanded load capaci-
tances versus equivalent se-
rial resistance of the crystal
C
C
L1
L2
See Table 4 on page 20 (MP oscillator)
22
56
pF
resonator (R )
S
V
=5V
DD
i
OSC2 driving current
(MP oscillator)
110
190
µA
2
V =V
IN
SS
Typical Crystal Resonator
Freq. Characteristic
C
C
L2
t
L1
SU(osc)
Oscil.
2)
1)
[ms]
[pF] [pF]
Reference
4MHz
∆f
=[±30ppm
,±30ppm ], Typ. R =60Ω
MP JAUCH
SS3-400-30-30/30
33 34 7~10
OSC
25°C ∆Ta S
Figure 39. Typical Application with a Crystal Resonator
WHEN RESONATOR WITH
INTEGRATED CAPACITORS
i
2
f
OSC
C
L1
OSC1
OSC2
RESONATOR
R
F
C
L2
ST7XXX
Notes:
1. Resonator characteristics given by the crystal resonator manufacturer.
2. t is the typical oscillator start-up time measured between V =2.8V and the fetch of the first instruction (with a
SU(OSC)
DD
quick V ramp-up from 0 to 5V (<50µs).
DD
3. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small R value.
S
Refer to crystal resonator manufacturer for more details.
81/102
ST7SCR
14.5 MEMORY CHARACTERISTICS
Subject to general operating conditions for V , f
, and T unless otherwise specified.
A
DD OSC
14.5.1 RAM and Hardware Registers
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
1)
V
Data retention mode
HALT mode (or RESET)
2
V
RM
14.5.2 FLASH Memory
Operating Conditions: f
= 8 MHz.
CPU
DUAL VOLTAGE FLASH MEMORY
Symbol
Parameter
Operating Frequency
Programming Voltage
Conditions
Read mode
Min
Typ
Max
Unit
8
f
MHz
Write / Erase mode,
CPU
8
T =25°C
A
V
4.0V <= V <= 5.5V
11.4
12.6
30
V
PP
DD
I
V
Current
Write / Erase
mA
µs
PP
PP
t
Byte Programming Time
Sector Erasing Time
Device Erasing Time
100
2
500
10
PROG
T =25°C
A
t
sec
ERASE
5
10
t
t
Internal V Stabilization Time
10
µs
VPP
PP
Data Retention
T ≤ 55°C
20
years
cycles
RET
A
N
Write Erase Cycles
T =25°C
100
RW
A
Warning: Do not connect 12V to V before V is powered on, as this may damage the device.
PP
DD
14.6 SMARTCARD SUPPLY SUPERVISOR ELECTRICAL CHARACTERISTICS
o
(T = 0... +70 C, 4.0 < V - V < 5.5V unless otherwise specified)
A
DD
SS
SMARTCARD SUPPLY SUPERVISOR
Symbol Parameter
5V regulator output (for IEC7816-3 Class A Cards)
Conditions
Min
Typ
Max
Unit
V
SmartCard Power Supply Voltage
SmartCard Supply Current
4.6
5.00
5.4
55
V
CARD
I
I
t
mA
mA
µs
SC
1)
Current Overload Detection
120
OVDET
IDET
1)
1)
Detection time on Current Overload
170
1400
V
Turn off Time (see Figure 35 on
CARD
t
C
C
≤ 4.7uF
750
µs
OFF
LOADmax
page 61)
V
Turn on Time (see Figure 35 on
CARD
t
I
≤ 4.7uF
150
500
100
µs
ON
LOADmax
page 61)
V
supply current
See note
mA
VDD
DD
3V regulator output (for IEC7816-3 Class B Cards)
V
SmartCard Power Supply Voltage
SmartCard Supply Current
2.7
3.3
50
V
CARD
I
I
t
mA
mA
us
SC
1)
Current Overload Detection
100
OVDET
IDET
1)
1)
Detection time on Current Overload
170
1400
V
Turn off Time (see Figure 35 on
CARD
t
C
≤4.7uF
750
us
OFF
LOADmax
page 61)
82/102
ST7SCR
SMARTCARD SUPPLY SUPERVISOR
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
V
Turn on Time (see Figure 35 on
CARD
t
C
≤ 4.7uF
150
500
µs
ON
LOADmax
page 61)
1.8V regulator output (for IEC7816-3 Class C Cards)
V
SmartCard Power Supply Voltage
SmartCard Supply Current
1.65
1.95
20
V
CARD
I
I
t
mA
mA
us
SC
1)
Current Overload Detection
100
OVDET
IDET
1)
1)
Detection time on Current Overload
170
1400
V
Turn off Time (see Figure 35 on
CARD
t
C
C
≤ 4.7uF
≤ 4.7uF
750
500
us
µs
OFF
LOADmax
page 61)
V
Turn on Time (see Figure 35 on
CARD
t
150
ON
LOADmax
page 61)
Smartcard CLKPin
2)
V
Output Low Level Voltage
Output High Level Voltage
Output H-L Fall Time
Output L-H Rise Time
Frequency variation
Duty cycle
I=-50uA
I=50uA
-
-
-
0.4
V
V
OL
OH
2)
V
VCARD-0.5
-
T
T
F
C =30pF
-
-
20
20
1
ns
ns
%
OHL
OLH
VAR
l
C=30pF
l
-
F
45
55
%
DUTY
I
Short-circuit to Ground
15
mA
SGND
Smartcard I/O Pin
2)
2)
V
Input Low Level Voltage
Input High Level Voltage
Output Low Level Voltage
Output High Level Voltage
Input Leakage Current
Pull-up Equivalent Resistance
Output H-L Fall Time
-
0.6VCARD
-
-
-
0.5
-
V
V
IL
IH
2)
V
V
I=-0.5mA
I=20uA
-
0.4
V
OL
2)
2)
V
0.8VCARD
-10
-
V
V
OH
CARD
I
V
<V <V
-
10
µA
KΩ
us
us
mA
L
SS
IN
SC_PWR
I
V =V
24
30
0.8
0.8
RPU
IN
SS
T
T
C =30pF
-
-
OHL
OLH
l
Output L-H Rise Time
C=30pF
l
I
Short-circuit to Ground
15
SGND
Smartcard RST C4 and C8 Pin
2)
V
Output Low Level Voltage
Output High Level Voltage
Output H-L Fall Time
I=-0.5mA
I=20uA
-
-
-
0.4
V
V
OL
OH
2)
2)
V
VCARD-0.5
VCARD
0.8
T
T
C =30pF
-
-
us
us
mA
OHL
OLH
l
Output L-H Rise Time
Short-circuit to Ground
C=30pF
0.8
l
I
15
SGND
Note 1 : Guaranteed by design.
Note 2 : Data based on characterization results, not tested in production.
Notes: V = 4.75 V, Card consumption = 55mA, CRDCLK frequency = 4MHz, LED with a 3mA current, USB in recep-
DD
tion mode and CPU in WFI mode.
83/102
ST7SCR
14.7 EMC CHARACTERISTICS
Susceptibility tests are performed on a sample ba-
sis during product characterization.
■ ESD: Electro-Static Discharge (positive and
negative) is applied on all pins of the device until
a functional disturbance occurs. This test
conforms with the IEC 1000-4-2 standard.
14.7.1 Functional EMS
(Electro Magnetic Susceptibility)
■ FTB: A Burst of Fast Transient voltage (positive
Based on a simple running application on the
product (toggling 2 LEDs through I/O ports), the
product is stressed by two electro magnetic events
until a failure occurs (indicated by the LEDs).
and negative) is applied to V and V through
DD
SS
a 100pF capacitor, until a functional disturbance
occurs. This test conforms with the IEC 1000-4-
4 standard.
A device reset allows normal operations to be re-
sumed.
1)
1)
Symbol
Parameter
Conditions
=5V, T =+25°C, f
conforms to IEC 1000-4-2
Neg
Pos
Unit
Voltage limits to be applied on any I/O pin
to induce a functional disturbance
V
=8MHz
OSC
DD
A
V
1
0.7
FESD
kV
Fast transient voltage burst limits to be ap-
V
=5V, T =+25°C, f
=8MHz
OSC
DD
A
V
plied through 100pF on V and V pins
2
2
FFTB
DD
DD
conforms to IEC 1000-4-4
to induce a functional disturbance
Notes:
1. Data based on characterization results, not tested in production.
84/102
ST7SCR
EMC CHARACTERISTICS (Cont’d)
14.7.2 Absolute Electrical Sensitivity
14.7.2.2 Designing hardened software to avoid
noise problems
Based on three different tests (ESD, LU and DLU)
using specific measurement methods, the product
is stressed in order to determine its performance in
terms of electrical sensitivity. For more details, re-
fer to the AN1181 ST7 application note.
EMC characterization and optimization are per-
formed at component level with a typical applica-
tion environment and simplified MCU software. It
should be noted that good EMC performance is
highly dependent on the user application and the
software in particular.
14.7.2.1 Electro-Static Discharge (ESD)
Electro-Static Discharges (1 positive then 1 nega-
tive pulse separated by 1 second) are applied to
the pins of each sample according to each pin
combination. The sample size depends of the
number of supply pins of the device (3 parts*(n+1)
supply pin). The Human Body Model is simulated.
This test conforms to the JESD22-A114A stand-
ard. See Figure 40 and the following test sequenc-
es.
Therefore it is recommended that the user applies
EMC software optimization and prequalification
tests in relation with the EMC level requested for
his application.
Software recommendations:
The software flowchart must include the manage-
ment of runaway conditions such as:
– Corrupted program counter
– Unexpected reset
Human Body Model Test Sequence
– C is loaded through S1 by the HV pulse gener-
L
– Critical Data corruption (control registers...)
Prequalification trials:
ator.
– S1 switches position from generator to R.
Most of the common failures (unexpected reset
and program counter corruption) can be repro-
duced by manually forcing a low state on the RE-
SET pin or the Oscillator pins for 1 second.
– A discharge from C through R (body resistance)
L
to the ST7 occurs.
– S2 must be closed 10 to 100ms after the pulse
delivery period to ensure the ST7 is not left in
charge state. S2 must be opened at least 10ms
prior to the delivery of the next pulse.
To complete these trials, ESD stress can be ap-
plied directly on the device,over the range of spec-
ification values.When unexpected behaviour is de-
tected,the sofware can be hardened to prevent un-
recoverable errors occurring (see application note
AN1015).
Absolute Maximum Ratings
1)
Symbol
Ratings
Conditions
Maximum value
Unit
Electro-static discharge voltage
(Human Body Model)
T =+25°C
V
1500
V
A
ESD(HBM)
Figure 40. Typical Equivalent ESD Circuits
S1
R=1500Ω
HIGH VOLTAGE
PULSE
GENERATOR
ST7
C =100pF
S2
L
HUMAN BODY MODEL
Notes:
1. Data based on characterization results, not tested in production.
85/102
ST7SCR
EMC CHARACTERISTICS (Cont’d)
14.7.2.3 Static and Dynamic Latch-Up
■ DLU: Electro-Static Discharges (one positive
then one negative test) are applied to each pin
of 3 samples when the micro is running to
assess the latch-up performance in dynamic
mode. Power supplies are set to the typical
values, the oscillator is connected as near as
possible to the pins of the micro and the
component is put in reset mode. This test
conforms to the IEC1000-4-2 and SAEJ1752/3
standards and is described in Figure 41. For
more details, refer to the AN1181 ST7
application note.
■ LU: 3 complementary static tests are required
on 10 parts to assess the latch-up performance.
A supply overvoltage (applied to each power
supply pin), a current injection (applied to each
input, output and configurable I/O pin) and a
power supply switch sequence are performed
on each sample. This test conforms to the EIA/
JESD 78 IC latch-up standard. For more details,
refer to the AN1181 ST7 application note.
Electrical Sensitivities
1)
Symbol
LU
Parameter
Static latch-up class
Dynamic latch-up class
Conditions
Class
T =+25°C
A
A
A
V
=5.5V, f
=4MHz, T =+25°C
DLU
DD
OSC
A
Figure 41. Simplified Diagram of the ESD Generator for DLU
R
=50MΩ
R =330Ω
D
CH
DISCHARGE TIP
V
V
DD
SS
HV RELAY
C =150pF
S
ST7
ESD
2)
DISCHARGE
RETURN CONNECTION
GENERATOR
Notes:
1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC spec-
ifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the
JEDEC criteria (international standard).
2. Schaffner NSG435 with a pointed test finger.
86/102
ST7SCR
EMC CHARACTERISTICS (Cont’d)
14.7.3 ESD Pin Protection Strategy
Standard Pin Protection
To protect an integrated circuit against Electro-
Static Discharge the stress must be controlled to
prevent degradation or destruction of the circuit el-
ements. The stress generally affects the circuit el-
ements which are connected to the pads but can
also affect the internal devices when the supply
pads receive the stress. The elements to be pro-
tected must not receive excessive current, voltage
or heating within their structure.
To protect the output structure the following ele-
ments are added:
– A diode to V (3a) and a diode from V (3b)
DD
SS
– A protection device between V and V (4)
DD
SS
To protect the input structure the following ele-
ments are added:
– A resistor in series with the pad (1)
– A diode to V (2a) and a diode from V (2b)
DD
SS
– A protection device between V and V (4)
DD
SS
An ESD network combines the different input and
output ESD protections. This network works, by al-
lowing safe discharge paths for the pins subjected
to ESD stress. Two critical ESD stress cases are
presented in Figure 42 and Figure 43 for standard
pins.
Figure 42. Positive Stress on a Standard Pad vs. V
SS
V
V
DD
DD
(3a)
(3b)
(2a)
(1)
(4)
OUT
IN
Main path
(2b)
Path to avoid
V
V
V
SS
SS
Figure 43. Negative Stress on a Standard Pad vs. V
DD
V
DD
DD
(3a)
(3b)
(2a)
(1)
(4)
OUT
IN
Main path
(2b)
V
V
SS
SS
87/102
ST7SCR
EMC CHARACTERISTICS (Cont’d)
Multisupply Configuration
shown in Figure 44 is implemented to protect the
device against ESD.
When several types of ground (V , V
, ...) and
SS
SSA
power supply (V , V
reason (better noise immunity...), the structure
, ...) are available for any
DD
DDA
Figure 44. Multisupply Configuration
V
DD
V
DDA
V
DDA
V
SS
BACK TO BACK DIODE
BETWEEN GROUNDS
V
SSA
V
SSA
88/102
ST7SCR
14.8 COMMUNICATION INTERFACE CHARACTERISTICS
14.8.1 USB - Universal Bus Interface
USB DC Electrical Characteristics
Parameter
Input Levels:
Symbol
Conditions
Min.
Max.
Unit
Differential Input Sensitivity
Differential Common Mode Range
Single Ended Receiver Threshold
Output Levels
VDI
VCM
VSE
I(D+, D-)
0.2
0.8
1.3
V
V
V
Includes VDI range
2.5
2.0
Static Output Low
VOL
VOH
RL of 1.5K ohms to 3.6v
0.3
3.6
V
V
V
Static Output High
RL of 15K ohm to V
2.8
SS
USBVCC: voltage level
USBV
V
=5v
3.00
3.60
DD
Note 1: RL is the load connected on the USB drivers.
Note 2: All the voltages are measured from the local ground potential.
Figure 45. USB: Data Signal Rise and Fall Time
Differential
Data Lines
Crossover
points
VCRS
VSS
tr
tf
USB: Full speed electrical characteristics
Parameter
Driver characteristics:
Rise time
Symbol
Conditions
Min
Max
Unit
tr
tf
Note 1,CL=50 pF
Note 1, CL=50 pF
tr/tf
4
4
20
20
ns
ns
%
Fall Time
Rise/ Fall Time matching
trfm
90
110
Output signal Crossover
Voltage
VCRS
1.3
2.0
V
Note1: Measured from 10% to 90% of the data signal. For more detailed informations, please refer to
Chapter 7 (Electrical) of the USB specification (version 1.1).
89/102
ST7SCR
15 PACKAGE CHARACTERISTICS
15.1 PACKAGE MECHANICAL DATA
Figure 46. 64-Pin Thin Quad Flat Package
A
mm
inches
D
Dim.
A2
Min Typ Max Min Typ Max
D1
A
1.60
0.063
0.006
A1
b
A1 0.05
0.15 0.002
A2 1.35 1.40 1.45 0.053 0.055 0.057
b
c
0.30 0.37 0.45 0.012 0.015 0.018
0.09
0.20 0.004
0.008
D
16.00
14.00
16.00
14.00
0.80
0.630
0.551
0.630
0.551
0.031
3.5°
e
D1
E
E
E1
E1
e
θ
0°
3.5°
7°
0°
7°
L
0.45 0.60 0.75 0.018 0.024 0.030
1.00 0.039
Number of Pins
64
L
L1
L1
c
N
h
Figure 47. 24-Pin Plastic Small Outline Package, 300-mil Width
mm
inches
Dim.
A
D
Min Typ Max Min Typ Max
h x 45×
L
2.35
2.65 0.093
0.30 0.004
0.51 0.013
0.32 0.009
15.60 0.599
7.60 0.291
0.104
0.012
0.020
0.013
0.614
0.299
A
A1 0.10
A1
C
B
C
D
E
e
0.33
0.23
a
e
B
15.20
7.40
1.27
0.050
H
h
α
10.00
0.25
0°
10.65 0.394
0.75 0.010
0.419
0.030
8°
E
H
8°
0°
L
0.40
1.27 0.016
0.050
Number of Pins
N
24
mm
inches
Dim.
Min Typ Max Min Typ Max
90/102
ST7SCR
Figure 48. PACKAGE MECHANICAL DATA (Cont’d)
Figure 49. Recommended Reflow Oven Profile (MID JEDEC)
250
200
Tmax=220+/-5°C
for 25 sec
150 sec above 183°C
150
100
50
90 sec at 125°C
Temp. [°C]
ramp down natural
2°C/sec max
ramp up
2°C/sec for 50sec
Time [sec]
0
100
200
300
400
91/102
ST7SCR
16 DEVICE CONFIGURATION AND ORDERING INFORMATION
Each device is available for production in ROM
versions and in user programmable versions (High
Density FLASH).
OPT4 = NEST Interrupt Controller
This bit enables the nested Interrupt Controller.
0: Nested interrupt controller disabled
1: Nested interrupt controller enabled
FLASH devices are shipped to customers with a
default content (FFh).
This implies that FLASH devices have to be con-
figured by the customer using the Option Byte
while the ROM devices are factory-configured.
OPT3 = ISOCLK Clock source selection
0: Card clock is generated by the divider (48MHz/
12 = 4MHz).
1: Card clock is generated by the oscillator.
16.0.1 Option Bytes
The 8 option bits from the flash are programmed
through the static option byte SOB1. The descrip-
tion of each of these 8 bits is given below.
OPT2 = RETRY Number of Retries for UART ISO
0: In case of an erroneous transfer, character is
transmitted 4 times.
1: In case of an erroneous transfer, character is
transmitted 5 times.
Static option Byte (SOB1)
OPT
7
OPT
0
6
5
4
3
2
1
-
OPT1 = Reserved, must be kept at 1.
WDG-
SW
--
--
NEST ISOCLK RETRY
FMP_R
OPT0 = FMP_R Flash memory read-out protec-
tion
OPT7:6 = Reserved
This option indicates if the user flash memory is
protected against read-out piracy. This protection
is based on read and a write protection of the
memory in test modes and ICP mode. Erasing the
option bytes when the FMP_R option is selected
induce the whole user memory erasing first.
0 : read-out protection enabled
OPT5= WDGSW Hardware or software watchdog
This option bit selects the watchdog type.
0: Hardware (watchdog always activated)
1: Software (watchdog to be activated by software)
1 : read-out protection disabled
92/102
ST7SCR
16.1 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE
Customer code is made up of the ROM contents
and the list of the selected options (if any). The
ROM contents are to be sent on diskette, or by
electronic means, with the hexadecimal file in .S19
format generated by the development tool. All un-
used bytes must be set to FFh.
The selected options are communicated to STMi-
croelectronics using the correctly completed OP-
TION LIST appended. See page 94.
The STMicroelectronics Sales Organization will be
pleased to provide detailed information on con-
tractual points.
Figure 50. Sales Type Coding Rules
Family
Version Code
Sub family
Number of pins
ROM Size Code
Package Type
Temperature Code
ROM Code (three letters)
ST7
F SCR1 R 4 B 1 / xxx
1 = Standard (0 to +70°C) T = TQFP
M = Plastic SO
4 = 16K R = 64 pins
x = 24pins
No letter = ROM
F = Flash
P = FASTROM
Table 23. Ordering Information
Program
Memory (bytes) (bytes)
RAM
1)
Sales Type
Package
ST7SCR1R4T1/xxx 16K ROM
ST7PSCR1R4T1/xxx 16K FASTROM
TQFP64
SO24
ST7FSCR1R4T1
16K Flash
768
ST7SCR1E4M1/xxx 16K ROM
ST7PSCR1E4M1/xxx 16K FASTROM
ST7FSCR1E4M1
16K Flash
Note 1. /xxx stands for the ROM or FASTROM-
code name assigned by STMicroelectronics.
93/102
ST7SCR
ST7SCR MICROCONTROLLER OPTION LIST
Customer: . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address:
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact:
Phone No: . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference/ROM Code* : . . . . . . . . . . . . . . . . . .
*The ROM code name is assigned by STMicroelectronics.
ROM code must be sent in .S19 format. .Hex extension cannot be processed.
Device Type/Memory Size/Package (check only one option):
-------------------------- ------------------------------------
|
|
|
ROM Device:
16K
|
-------------------------- ------------------------------------
|
|
SO24:
TQFP64:
|
|
[ ] ST7SCR1E4M1
[ ] ST7SCR1R4T1
-------------------------- ------------------------------------
|
|
|
FASTROM Device:
16K
|
-------------------------- ------------------------------------
|
|
SO24:
TQFP64:
|
|
[ ] ST7PSCR1E4M1
[ ] ST7PSCR1R4T1
Conditioning (check only one option):
----------------------------------------------------------------- ----------------------------------------------------
|
Packaged Product:
Die Product (dice tested at 25°C only)
|
----------------------------------------------------------------- ----------------------------------------------------
[ ] Tape & Reel [ ] Tray (TQFP package only) | [ ] Tape & Reel
[ ] Tube (SO package only)
|
|
[ ] Inked wafer
[ ] Sawn wafer on sticky foil
Note: Die product only for ROM device
Special Marking: [ ] No
[ ] Yes "_ _ _ _ _ _ _ _ _ _ "
Authorized characters are letters, digits, ’.’, ’-’, ’/’ and spaces only.
Maximum character count:
S024 (13 char. max) : _ _ _ _ _ _ _ _
TQFP64 (10 char. max) : _ _ _ _ _ _ _ _ _ _
Watchdog:
WDGSW
NEST
[ ] Software Activation
[ ] Hardware Activation
[ ] Nested Interrupts
[ ] Non Nested Interrupts
[ ] Oscillator
[ ] Divider
[ ] 5
Nested Interrupts
ISO Clock Source ISOCLK
No. of Retries RETRY
[ ] 4
Readout Protection: FMP_R
[ ] Disabled
[ ] Enabled
Signature
Date
94/102
ST7SCR
16.2 DEVELOPMENT TOOLS
Table 24. Development Tools
Development Tool
Emulator
Sales Type
Remarks
ST7MDTS1-EMU2B
ST7MDTS1-EPB2
Programming Board
16.2.1 ADAPTOR/SOCKET PROPOSAL
TBD
95/102
ST7SCR
16.3 ST7 APPLICATION NOTES
IDENTIFICATION
DESCRIPTION
EXAMPLE DRIVERS
AN 969
AN 970
AN 971
AN 972
AN 973
AN 974
AN 976
AN 979
AN 980
AN1017
AN1041
AN1042
AN1044
AN1045
AN1046
AN1047
AN1048
AN1078
AN1082
AN1083
AN1105
AN1129
SCI COMMUNICATION BETWEEN ST7 AND PC
SPI COMMUNICATION BETWEEN ST7 AND EEPROM
I²C COMMUNICATING BETWEEN ST7 AND M24CXX EEPROM
ST7 SOFTWARE SPI MASTER COMMUNICATION
SCI SOFTWARE COMMUNICATION WITH A PC USING ST72251 16-BIT TIMER
REAL TIME CLOCK WITH ST7 TIMER OUTPUT COMPARE
DRIVING A BUZZER THROUGH ST7 TIMER PWM FUNCTION
DRIVING AN ANALOG KEYBOARD WITH THE ST7 ADC
ST7 KEYPAD DECODING TECHNIQUES, IMPLEMENTING WAKE-UP ON KEYSTROKE
USING THE ST7 UNIVERSAL SERIAL BUS MICROCONTROLLER
USING ST7 PWM SIGNAL TO GENERATE ANALOG OUTPUT (SINUSOID)
ST7 ROUTINE FOR I²C SLAVE MODE MANAGEMENT
MULTIPLE INTERRUPT SOURCES MANAGEMENT FOR ST7 MCUS
ST7 S/W IMPLEMENTATION OF I²C BUS MASTER
UART EMULATION SOFTWARE
MANAGING RECEPTION ERRORS WITH THE ST7 SCI PERIPHERALS
ST7 SOFTWARE LCD DRIVER
PWM DUTY CYCLE SWITCH IMPLEMENTING TRUE 0% & 100% DUTY CYCLE
DESCRIPTION OF THE ST72141 MOTOR CONTROL PERIPHERAL REGISTERS
ST72141 BLDC MOTOR CONTROL SOFTWARE AND FLOWCHART EXAMPLE
ST7 PCAN PERIPHERAL DRIVER
PERMANENT MAGNET DC MOTOR DRIVE.
AN INTRODUCTION TO SENSORLESS BRUSHLESS DC MOTOR DRIVE APPLICATIONS
WITH THE ST72141
AN1130
AN1148
AN1149
AN1180
AN1276
AN1321
AN1325
AN1445
AN1475
AN1504
USING THE ST7263 FOR DESIGNING A USB MOUSE
HANDLING SUSPEND MODE ON A USB MOUSE
USING THE ST7263 KIT TO IMPLEMENT A USB GAME PAD
BLDC MOTOR START ROUTINE FOR THE ST72141 MICROCONTROLLER
USING THE ST72141 MOTOR CONTROL MCU IN SENSOR MODE
USING THE ST7 USB LOW-SPEED FIRMWARE V4.X
USING THE ST7 SPI TO EMULATE A 16-BIT SLAVE
DEVELOPING AN ST7265X MASS STORAGE APPLICATION
STARTING A PWM SIGNAL DIRECTLY AT HIGH LEVEL USING THE ST7 16-BIT TIMER
PRODUCT EVALUATION
AN 910
AN 990
AN1077
AN1086
AN1150
AN1151
AN1278
PERFORMANCE BENCHMARKING
ST7 BENEFITS VERSUS INDUSTRY STANDARD
OVERVIEW OF ENHANCED CAN CONTROLLERS FOR ST7 AND ST9 MCUS
U435 CAN-DO SOLUTIONS FOR CAR MULTIPLEXING
BENCHMARK ST72 VS PC16
PERFORMANCE COMPARISON BETWEEN ST72254 & PC16F876
LIN (LOCAL INTERCONNECT NETWORK) SOLUTIONS
PRODUCT MIGRATION
AN1131
AN1322
AN1365
MIGRATING APPLICATIONS FROM ST72511/311/214/124 TO ST72521/321/324
MIGRATING AN APPLICATION FROM ST7263 REV.B TO ST7263B
GUIDELINES FOR MIGRATING ST72C254 APPLICATION TO ST72F264
PRODUCT OPTIMIZATION
96/102
ST7SCR
IDENTIFICATION
AN 982
DESCRIPTION
USING ST7 WITH CERAMIC RESONATOR
HOW TO MINIMIZE THE ST7 POWER CONSUMPTION
AN1014
AN1015
SOFTWARE TECHNIQUES FOR IMPROVING MICROCONTROLLER EMC PERFORMANCE
MONITORING THE VBUS SIGNAL FOR USB SELF-POWERED DEVICES
ST7 CHECKSUM SELF-CHECKING CAPABILITY
AN1040
AN1070
AN1324
CALIBRATING THE RC OSCILLATOR OF THE ST7FLITE0 MCU USING THE MAINS
EMULATED DATA EEPROM WITH XFLASH MEMORY
AN1477
AN1502
EMULATED DATA EEPROM WITH ST7 HDFLASH MEMORY
AN1529
EXTENDING THE CURRENT & VOLTAGE CAPABILITY ON THE ST7265 VDDF SUPPLY
ACCURATE TIMEBASE FOR LOW-COST ST7 APPLICATIONS WITH INTERNAL RC OSCIL-
LATOR
AN1530
PROGRAMMING AND TOOLS
AN 978
AN 983
AN 985
AN 986
AN 987
AN 988
AN 989
AN1039
AN1064
AN1071
AN1106
KEY FEATURES OF THE STVD7 ST7 VISUAL DEBUG PACKAGE
KEY FEATURES OF THE COSMIC ST7 C-COMPILER PACKAGE
EXECUTING CODE IN ST7 RAM
USING THE INDIRECT ADDRESSING MODE WITH ST7
ST7 SERIAL TEST CONTROLLER PROGRAMMING
STARTING WITH ST7 ASSEMBLY TOOL CHAIN
GETTING STARTED WITH THE ST7 HIWARE C TOOLCHAIN
ST7 MATH UTILITY ROUTINES
WRITING OPTIMIZED HIWARE C LANGUAGE FOR ST7
HALF DUPLEX USB-TO-SERIAL BRIDGE USING THE ST72611 USB MICROCONTROLLER
TRANSLATING ASSEMBLY CODE FROM HC05 TO ST7
PROGRAMMING ST7 FLASH MICROCONTROLLERS IN REMOTE ISP MODE (IN-SITU PRO-
GRAMMING)
AN1179
AN1446
AN1478
AN1527
AN1575
USING THE ST72521 EMULATOR TO DEBUG A ST72324 TARGET APPLICATION
PORTING AN ST7 PANTA PROJECT TO CODEWARRIOR IDE
DEVELOPING A USB SMARTCARD READER WITH ST7SCR
ON-BOARD PROGRAMMING METHODS FOR XFLASH AND HDFLASH ST7 MCUS
97/102
ST7SCR
17 SUMMARY OF CHANGES
Description of the changes between the current release of the specification and the previous one.
Revision
Main changes
Date
Removed LVD option bit (LVD cannot be disabled)
Updated Figure 7 on page 15
1.2
Dec-01
Changed status of the document
Changed Table 1, “Device Summary,” on page 1
Changed Figure 4 on page 10
Changed Section 4.2 on page 14
Added note in Section 4.5 on page 15
Changed description of the following registers in Section 12.3.4 on page 46: EP0R, Endpoint
Transmission Register and Endpoint 2 Reception Register.
Moved “Power Supply Management” chapter to Section 12.4.3.1 on page 56
Updated Section 14 on page 76
1.3
March-03
Added Section 14.7 on page 84
Changed Figure 46 on page 90
Removed references to true open drain pins
Changed Section 16.1 on page 93
Added warning in Section 14.5.2 on page 82
Added Erratasheet on page 99
98/102
ERRATA SHEET
ST7SCR LIMITATIONS AND CORRECTIONS
18 SILICON IDENTIFICATION
This document refers only to ST7FSCR devices shown in Table 25. They are identifiable both
by the last letter of the Trace code marked on the device package and by the last 3 digits of
the Internal Sales Type printed on the box label (see also Figure 51)
Table 25. Device Identification
Trace Code marked on device
Flash Devices: “xxxxxxxxxX”
Internal Sales Type on box label
7FSCRxxxx$M1
7FSCRxxxx$T1
19 REFERENCE SPECIFICATION
ST7SCR Datasheet 1.3 (March 2003).
20 SILICON LIMITATIONS
20.1 UNEXPECTED RESET FETCH
If an interrupt request occurs while a "POP CC" instruction is executed, the interrupt controller
does not recognise the source of the interrupt and, by default, passes the RESET vector ad-
dress to the CPU.
To solve this issue, a "POP CC" instruction must always be preceded by a "SIM" instruction.
20.2 USB: TWO CONSECUTIVE SETUP TOKENS
Description
When two consecutive SETUP tokens are received and the software does not have time to
write the value 8 in the Endpoint 0 Reception Counter Register (CNT0RXR), the data associ-
ated with the second SETUP are not copied to the buffer.
Impact
The impact depends on the host behaviour. In the USB Spec 2.0 it is stated (chapter 5.5.5
p43) that: “A Setup transaction should not normally be sent before the completion of a pre-
vious control transfer. However, if a transfer is aborted, for example, due to errors on the bus,
the host can send the next Setup transaction prematurely from the endpoint’s perspective”. If
the new Setup token is sent because an error occurs in the previous one, it should contain the
same data so no application malfunction will occur.
Rev. 1.2
March 2003
99/102
ERRATA SHEET
This limitation will be corrected in the next silicon revision. In the new revision, when a SETUP
token is received, the value loaded in the internal counter is fixed to 8 by hardware independ-
ently of the value in the CNT0RXR register.
20.3 USB BUFFER SHARED MEMORY ACCESS
Description
When f
is at 4 MHz, a value written in the USB buffer may be corrupted when V is less
DD
CPU
than 4.4V. This limitation will be corrected in the next silicon revision.
Impact
USB buffer access cannot be guaranteed over the full V range when f
is at 4 MHz.
DD
CPU
20.4 WDG (WATCHDOG) LIMITATIONS
In flash devices, the WDG prescaler value is not 65536 as described in Section 12.1.3 on
page 40 (Figure 25), it is actually 16.
This will be corrected in the next revision of the silicon.
20.5 SUPPLY CURRENT IN HALT MODE (SUSPEND) LIMITATIONS
The current consumption (I ) in some devices may exceed the maximum specified in the
DD
documentation (up to 1mA).
Workaround
Declare 200mA max. power value in the USB Configuration Descriptor.
20.5.1 V Pin Limitation
PP
In the impacted flash devices, contrary to the datasheet specification (which specifies that it
must be tied to V ), the V pin must be tied to V in operating mode. This will be fixed in
DD
SS
PP
the next silicon revision .
20.6 START-UP
The ST7SCR relies on internal LVD and it may not start-up correctly if the power supply is
slow.
Workaround
Put a 1MΩ resistor between V
and V to eliminate the offset on V that may cause this
SS DD
DD
power-on problem.
100/102
ERRATA SHEET
20.7 I/O PORT INPUT HIGH LEVEL (V )
IH
The V min value is 0.8*V and not 0.7*V as specified for the final silicon.
IH
DD
DD
21 DEVICE MARKING
Figure 51. Revision Marking on Box Label and Device Marking
TYPE xxxx
Internalxxx$xx
Trace Code
LAST 2 DIGITS AFTER $
IN INTERNAL SALES TYPE
ON BOX LABEL
INDICATE SILICON REV.
LAST LETTER OF TRACE CODE
ON DEVICE INDICATES
SILICON REV.
22 ERRATA SHEET REVISION HISTORY
Revision
Main Changes
Date
Updated Section 20.5 "SUPPLY CURRENT IN HALT MODE (SUSPEND) Limi-
tations" on page 100
1.2
03/13/03
Added Section 20.6 "Start-UP" on page 100
101/102
ERRATA SHEET
Notes:
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
2003 STMicroelectronics - All Rights Reserved.
Purchase of I2C Components by STMicroelectronics conveys a license under the Philips I2C Patent. Rights to use these components in an
I2C system is granted provided that the system conforms to the I2C Standard Specification as defined by Philips.
STMicroelectronics Group of Companies
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http://www.st.com
102/102
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