ST72P325J4TA/XXXE [STMICROELECTRONICS]
ST72P325J4TA/XXXE;ST72325xxx-Auto
8-bit MCU for automotive with 16 to 60 Kbyte Flash, ADC,
CSS, 5 timers, SPI, SCI, I2C interface
Features
Memories
LQFP32
7 x 7
LQFP44
10 x 10
■ 16 to 60 Kbyte dual voltage High Density Flash
(HDFlash) with readout protection capability.
In-application programming and in-circuit
programming for HDFlash devices
LQFP64
10 x 10
LQFP64
14 x 14
■ 512 to 2048 bytes RAM
■ HDFlash endurance: 100 cycles, data retention
20 years
5 timers
■ Main clock controller with Real-time base,
Clock, reset and supply management
Beep and Clock-out capabilities
■ Enhanced low voltage supervisor (LVD) for
main supply and auxiliary voltage detector
(AVD) with interrupt capability
■ Configurable watchdog timer
■ Two 16-bit timers with 2 input captures, 2
output compares, external clock input on 1
timer, PWM and pulse generator modes
■ Clock sources: crystal/ceramic resonator
oscillators, internal RC oscillator and bypass
for external clock
■ 8-bit PWM auto-reload timer with 2 input
captures, 4 PWM outputs, output compare and
time base interrupt, external clock with event
detector
■ PLL for 2x frequency multiplication
■ 4 power saving modes: Halt, Active Halt, Wait
and Slow
■ Clock security system
3 communications interfaces
■ SPI synchronous serial interface
■ SCI asynchronous serial interface
Interrupt management
■ Nested interrupt controller
2
■ I C multimaster interface
■ 14 interrupt vectors plus TRAP and RESET
■ Top Level Interrupt (TLI) pin on 64-pin devices
■ 9/6 external interrupt lines (on 4 vectors)
Instruction set
■ 8-bit data manipulation
■ 63 basic instructions
1 analog peripheral (low current coupling)
■ 17 main addressing modes
■ 8x8 unsigned multiply instruction
■ 10-bit ADC with up to 16 input ports
Up to 48 I/O ports
Development tools
■ 48/32/24 multifunctional bidirectional I/O lines
■ 34/22/17 alternate function lines
■ 16/12/10 high sink outputs
■ Full hardware/software development package
■ DM (debug module)
August 2007
Rev 1
1/250
www.st.com
1
Contents
ST72325xxx-Auto
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.1
1.2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Differences between ST72325-Auto and ST72325 datasheets . . . . . . . . 20
1.2.1
1.2.2
1.2.3
Principal differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Minor content differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Editing and formatting differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2
Package pinout and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.1
2.2
Package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3
4
Register and memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.1
4.2
4.3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.3.1
Readout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.4
4.5
4.6
4.7
4.8
ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
ICP (in-circuit programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
IAP (in-application programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Flash control/status register (FCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5
Central processing unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.1
5.2
5.3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Index registers (X and Y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Program counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Condition code (CC) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Stack pointer (SP) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
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Contents
6
Supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.1
6.2
6.3
6.4
6.5
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Phase locked loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Multi-oscillator (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Reset sequence manager (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.5.1
6.5.2
6.5.3
6.5.4
6.5.5
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Asynchronous external RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
External power-on RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Internal low voltage detector (LVD) RESET . . . . . . . . . . . . . . . . . . . . . . 51
Internal watchdog RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6.6
System integrity management (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.6.1
6.6.2
6.6.3
6.6.4
6.6.5
6.6.6
Low voltage detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Auxiliary voltage detector (AVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
System Integrity (SI) Control/Status register (SICSR) . . . . . . . . . . . . . . 57
7
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
7.1
7.2
7.3
7.4
7.5
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Masking and processing flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Interrupts and low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Concurrent and nested management . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Interrupt register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
7.5.1
7.5.2
CPU CC register interrupt bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Interrupt software priority registers (ISPRx) . . . . . . . . . . . . . . . . . . . . . . 64
7.6
External interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
7.6.1
7.6.2
I/O port interrupt sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
External interrupt control register (EICR) . . . . . . . . . . . . . . . . . . . . . . . . 68
8
Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
8.1
8.2
8.3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
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ST72325xxx-Auto
8.4
Active Halt and Halt modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
8.4.1
8.4.2
Active Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
9
I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
9.1
9.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
9.2.1
9.2.2
9.2.3
Input modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
9.3
9.4
9.5
I/O port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
10
Watchdog timer (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
10.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
10.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
10.4 How to program the watchdog timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
10.5 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
10.6 Hardware watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
10.7 Using Halt mode with the WDG (WDGHALT option) . . . . . . . . . . . . . . . . 89
10.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
10.9 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
10.9.1 Control register (WDGCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
11
Main clock controller with real-time clock and beeper (MCC/RTC) . . 91
11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
11.2 Programmable CPU clock prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
11.3 Clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
11.4 Real-time clock timer (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
11.5 Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
11.6 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
11.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
11.8 Main clock controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
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11.8.1 MCC control/status register (MCCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . 93
11.8.2 MCC beep control register (MCCBCR) . . . . . . . . . . . . . . . . . . . . . . . . . 94
12
PWM auto-reload timer (ART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
12.2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
12.2.1 Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
12.2.2 Counter clock and prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
12.2.3 Counter and prescaler initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
12.2.4 Output compare control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
12.2.5 Independent PWM signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
12.2.6 Output compare and time base interrupt . . . . . . . . . . . . . . . . . . . . . . . . 99
12.2.7 External clock and event detector mode . . . . . . . . . . . . . . . . . . . . . . . . 99
12.2.8 Input capture function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
12.2.9 External interrupt capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
12.3 ART registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
12.3.1 Control/status register (ARTCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
12.3.2 Counter access register (ARTCAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
12.3.3 Auto-reload register (ARTARR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
12.3.4 PWM control register (PWMCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
12.3.5 Duty cycle registers (PWMDCRx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
12.3.6 Input capture control / status register (ARTICCSR) . . . . . . . . . . . . . . . 105
12.3.7 Input capture registers (ARTICRx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
13
16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
13.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
13.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
13.3.1 Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
13.3.2 External clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
13.3.3 Input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
13.3.4 Output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
13.3.5 Forced compare output capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
13.3.6 One Pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
13.3.7 Pulse width modulation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
13.4 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
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13.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
13.6 Summary of timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
13.7 16-bit timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
13.7.1 Control register 1 (CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
13.7.2 Control register 2 (CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
13.7.3 Control/status register (CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
13.7.4 Input capture 1 high register (IC1HR) . . . . . . . . . . . . . . . . . . . . . . . . . 125
13.7.5 Input capture 1 low register (IC1LR) . . . . . . . . . . . . . . . . . . . . . . . . . . 126
13.7.6 Output compare 1 high register (OC1HR) . . . . . . . . . . . . . . . . . . . . . . 126
13.7.7 Output compare 1 low register (OC1LR) . . . . . . . . . . . . . . . . . . . . . . . 126
13.7.8 Output compare 2 high register (OC2HR) . . . . . . . . . . . . . . . . . . . . . . 126
13.7.9 Output compare 2 low register (OC2LR) . . . . . . . . . . . . . . . . . . . . . . . 127
13.7.10 Counter high register (CHR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
13.7.11 Counter low register (CLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
13.7.12 Alternate counter high register (ACHR) . . . . . . . . . . . . . . . . . . . . . . . . 127
13.7.13 Alternate counter low register (ACLR) . . . . . . . . . . . . . . . . . . . . . . . . . 128
13.7.14 Input capture 2 high register (IC2HR) . . . . . . . . . . . . . . . . . . . . . . . . . 128
13.7.15 Input capture 2 low register (IC2LR) . . . . . . . . . . . . . . . . . . . . . . . . . . 128
14
Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
14.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
14.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
14.3.1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
14.3.2 Slave select management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
14.3.3 Master mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
14.3.4 Master mode transmit sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
14.3.5 Slave mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
14.3.6 Slave mode transmit sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
14.4 Clock phase and clock polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
14.5 Error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
14.5.1 Master mode fault (MODF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
14.5.2 Overrun condition (OVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
14.5.3 Write collision error (WCOL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
14.5.4 Single master systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
14.6 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
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14.6.1 Using the SPI to wake up the MCU from Halt mode . . . . . . . . . . . . . . 139
14.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
14.8 SPI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
14.8.1 Control register (SPICR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
14.8.2 Control/status register (SPICSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
14.8.3 Data I/O register (SPIDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
15
Serial communications interface (SCI) . . . . . . . . . . . . . . . . . . . . . . . . 144
15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
15.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
15.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
15.4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
15.4.1 Serial data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
15.4.2 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
15.4.3 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
15.5 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
15.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
15.7 SCI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
15.7.1 Status register (SCISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
15.7.2 Control register 1 (SCICR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
15.7.3 Control register 2 (SCICR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
15.7.4 Data register (SCIDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
15.7.5 Baud rate register (SCIBRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
15.7.6 Extended receive prescaler division register (SCIERPR) . . . . . . . . . . 161
15.7.7 Extended transmit prescaler division register (SCIETPR) . . . . . . . . . . 162
16
I2C bus interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
16.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
16.2.1 I2C master features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
16.2.2 I2C slave features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
16.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
16.3.1 Mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
16.3.2 Communication flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
16.3.3 SDA/SCL line control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
16.4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
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16.4.1 Slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
16.4.2 Master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
16.5 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
16.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
16.7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
16.7.1 I2C control register (CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
16.7.2 I2C status register 1 (SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
16.7.3 I2C status register 2 (SR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
16.7.4 I2C clock control register (CCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
16.7.5 I2C data register (DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
16.7.6 I2C own address register (OAR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
16.7.7 I2C own address register (OAR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
17
10-bit A/D converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
17.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
17.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
17.3.1 A/D converter configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
17.3.2 Starting the conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
17.3.3 Changing the conversion channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
17.4 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
17.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
17.6 ADC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
17.6.1 Control/status register (ADCCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
17.6.2 Data register (ADCDRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
17.6.3 Data register (ADCDRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
17.6.4 ADC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
18
Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
18.1 CPU addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
18.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
18.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
18.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
18.1.4 Indexed (no offset, short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
18.1.5 Indirect (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
18.1.6 Indirect Indexed (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
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18.1.7 Relative (Direct, Indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
18.2 Instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
18.2.1 Using a prebyte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
19
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
19.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
19.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
19.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
19.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
19.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
19.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
19.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
19.2.1 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
19.2.2 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
19.2.3 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
19.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
19.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
19.3.2 Operating conditions with low voltage detector (LVD) . . . . . . . . . . . . . 198
19.3.3 Auxiliary voltage detector (AVD) thresholds . . . . . . . . . . . . . . . . . . . . . 198
19.3.4 External voltage detector (EVD) thresholds . . . . . . . . . . . . . . . . . . . . . 199
19.4 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
19.4.1 Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
19.4.2 Supply and clock managers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
19.4.3 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
19.5 Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
19.5.1 General timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
19.5.2 External clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
19.5.3 Crystal and ceramic resonator oscillators . . . . . . . . . . . . . . . . . . . . . . 204
19.5.4 RC oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
19.5.5 Clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
19.5.6 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
19.6 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
19.6.1 RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
19.6.2 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
19.7 EMC (electromagnetic compatibility) characteristics . . . . . . . . . . . . . . . 208
19.7.1 Functional EMS (electromagnetic susceptibility) . . . . . . . . . . . . . . . . . 208
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19.7.2 EMI (electromagnetic interference) . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
19.7.3 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 209
19.8 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
19.8.1 General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
19.8.2 Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
19.9 Control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
19.9.1 Asynchronous RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
19.9.2 ICCSEL/VPP pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
19.10 Timer peripheral characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
19.11 Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . 219
19.11.1 SPI (serial peripheral interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
19.11.2 I2C - inter IC control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
19.12 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
19.12.1 Analog power supply and reference pins . . . . . . . . . . . . . . . . . . . . . . . 225
19.12.2 General PCB design guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
19.12.3 ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
20
21
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
20.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
20.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
20.3 Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
20.3.1 Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Device configuration and ordering information . . . . . . . . . . . . . . . . . 233
21.1 Flash devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
21.1.1 Flash configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
21.1.2 Flash ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
21.2 FASTROM device ordering information and transfer of customer code . 237
21.3 Development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
21.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
21.3.2 Evaluation tools and starter kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
21.3.3 Development and debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
21.3.4 Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
21.3.5 Socket and emulator adapter information . . . . . . . . . . . . . . . . . . . . . . 242
21.4 ST7 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
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22
Known limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
22.1 All devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
22.1.1 Unexpected reset fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
22.1.2 External interrupt missed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
22.1.3 Clearing active interrupts outside interrupt routine . . . . . . . . . . . . . . . 246
22.1.4 SCI wrong break duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
22.1.5 16-bit timer PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
22.1.6 TIMD set simultaneously with OC interrupt . . . . . . . . . . . . . . . . . . . . . 248
22.1.7 I2C multimaster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
22.1.8 Pull-up always active on PE2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
23
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
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List of tables
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List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Device pin descriptions (LQFP64 and LQFP44). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Device pin descriptions (LQFP32) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Sectors available in Flash devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Flash control/status register address and reset value . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Arithmetic management bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Interrupt management bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Interrupt software priority selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
ST7 clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Effect of low power modes on SI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
CSS AVD interrupt control/wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
SICSR description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Reset source flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Interrupt software priority levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
CPU CC register interrupt bits description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Interrupt software priority levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Interrupt priority bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Interrupt dedicated instruction set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
EICR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Interrupt sensitivity - ei2 (port B3..0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Interrupt sensitivity - ei3 (port B4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Interrupt sensitivity - ei0 (port A3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Interrupt sensitivity - ei1 (port F2..0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Nested interrupts register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
MCC/RTC low power mode selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
I/O output mode selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
I/O port mode options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
I/O port configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
I/O port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Effect of low power modes on I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
I/O port interrupt control/wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
I/O port register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Effect of low power modes on WDG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
WDGCR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Watchdog timer register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Effect of low power modes on MCC/RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
MCC/RTC interrupt control/wake-up capability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
MCCSR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Time base selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
MCCBCR register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Beep frequency selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Main clock controller register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
ARTCSR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Prescaler selection for ART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
ARTCAR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
ARTAAR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
12/250
ST72325xxx-Auto
List of tables
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
Table 82.
Table 83.
Table 84.
Table 85.
Table 86.
Table 87.
Table 88.
Table 89.
Table 90.
Table 91.
Table 92.
Table 93.
Table 94.
Table 95.
Table 96.
Table 97.
Table 98.
Table 99.
PWM frequency versus resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
PWMCR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
PWM output signal polarity selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
PWMDCRx register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
ARTICCSR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
ARTICRx register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
PWM auto-reload timer register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Effect of low power modes on 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
16-bit timer interrupt control/wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Timer modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
CR1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
CR2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Timer clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
CSR register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
16-bit timer register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Effect of low power modes on SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
SPI interrupt control/wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
SPICR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
SPI master mode SCK frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
SPICSR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
SPI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Effect of low power modes on SCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
SCI interrupt control/wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
SCISR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
SCICR1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
SCICR2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
SCIBRR register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
SCIERPR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
SCIETPR register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Baud rate selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
SCI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Effect of low power modes on I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
I2C interrupt control/wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
CR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
SR1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
SR2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
CCR register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
DR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
OAR1 register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
OAR2 register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
I2C register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Effect of low power modes on ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
ADCCSR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
ADCDRH register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
ADCDRL register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
ADC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
CPU addressing mode overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Inherent instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Immediate instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Table 100. Instructions supporting direct, indexed, indirect, and indirect indexed addressing modes 189
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Table 101. Available relative direct/indirect instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Table 102. Instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Table 103. Instruction set overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Table 104. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Table 105. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Table 106. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Table 107. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Table 108. Operating conditions with low voltage detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Table 109. Auxiliary voltage detector (AVD) thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Table 110. External voltage detector (EVD) thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Table 111. Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Table 112. Oscillators, CSS, PLL and LVD current consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Table 113. On-chip peripherals current consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Table 114. General timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Table 115. External clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Table 116. Crystal and ceramic resonator oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Table 117. Resonator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Table 118. RC oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Table 119. CSS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Table 120. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Table 121. RAM supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Table 122. Dual voltage HDFlash memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Table 123. EMS test results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Table 124. EMI emissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Table 125. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Table 126. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Table 127. I/O port pin general characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Table 128. Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Table 129. Asynchronous RESET pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Table 130. ICCSEL/VPP pin characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Table 131. 8-bit PWM-ART auto-reload timer characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Table 132. 16-bit timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Table 133. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Table 134. I2C control interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Table 135. SCL frequency table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Table 136. 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Table 137. ADC accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Table 138. 64-pin (14x14) low profile quad flat package mechanical data. . . . . . . . . . . . . . . . . . . . . 228
Table 139. 64-pin (10x10) low profile quad flat package mechanical data. . . . . . . . . . . . . . . . . . . . . 229
Table 140. 44-pin (10x10) low profile quad flat package mechanical data. . . . . . . . . . . . . . . . . . . . . 230
Table 141. 32-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Table 142. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Table 143. Soldering compatibility (wave and reflow soldering process) . . . . . . . . . . . . . . . . . . . . . . 232
Table 144. Flash option bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Table 145. Option byte 0 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Table 146. Option byte 1 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Table 147. Package selection (OPT7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Table 148. Flash user programmable device types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Table 149. FASTROM factory coded device types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Table 150. STMicroelectronics development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
Table 151. Suggested list of socket types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
Table 152. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
14/250
ST72325xxx-Auto
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
64-pin LQFP 14x14 and 10x10 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
44-pin LQFP package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
32-pin LQFP package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Memory map and sector address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Typical ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Stack manipulation example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 10. Clock, reset and supply block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 11. PLL block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 12. Reset block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 13. RESET sequence phases. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 14. RESET sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 15. Low voltage detector versus reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 16. Using the AVD to monitor VDD (AVDS bit = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 17. Using the voltage detector to monitor the EVD pin (AVDS bit = 1). . . . . . . . . . . . . . . . . . . 55
Figure 18. Clock filter function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 19. Interrupt processing flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 20. Priority decision process flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 21. Concurrent interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 22. Nested interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 23. External interrupt control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 24. Power saving mode transitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 25. Slow mode clock transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 26. Wait mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 27. Active Halt timing overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 28. Active Halt mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 29. Halt timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 30. Halt mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 31. I/O port general block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 32. Interrupt I/O port state transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 33. Watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 34. Approximate timeout duration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 35. Exact timeout duration (tmin and tmax) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 36. Main clock controller (MCC/RTC) block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 37. PWM auto-reload timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 38. Output compare control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Figure 39. PWM auto-reload timer function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 40. PWM signal from 0% to 100% duty cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 41. External event detector example (3 counts) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 42. Input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 43. Timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 44. 16-bit read sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 45. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Figure 46. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Figure 47. Counter timing diagram, internal clock divided by 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Figure 48. Input capture block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
15/250
List of figures
ST72325xxx-Auto
Figure 49. Input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Figure 50. Output compare block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Figure 51. Output compare timing diagram, fTIMER = fCPU/2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Figure 52. Output compare timing diagram, fTIMER = fCPU/4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Figure 53. One pulse mode cycle flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 54. One pulse mode timing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Figure 55. Pulse width modulation mode timing example with 2 output compare functions . . . . . . . 119
Figure 56. Pulse width modulation cycle flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Figure 57. Serial peripheral interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Figure 58. Single master/single slave application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Figure 59. Generic SS timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Figure 60. Hardware/Software slave select management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Figure 61. Data clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Figure 62. Clearing the WCOL bit (Write Collision Flag) software sequence . . . . . . . . . . . . . . . . . . 138
Figure 63. Single master / multiple slave configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Figure 64. SCI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Figure 65. Word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Figure 66. SCI baud rate and extended prescaler block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Figure 67. Bit sampling in reception mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Figure 68. I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Figure 69. I2C interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Figure 70. Transfer sequencing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Figure 71. Interrupt control logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Figure 72. ADC block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Figure 73. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Figure 74. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Figure 75. fCPU max versus V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
DD
Figure 76. Typical application with an external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Figure 77. Typical application with a crystal or ceramic resonator. . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Figure 78. Typical fOSC(RCINT) versus TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Figure 79. Integrated PLL jitter versus signal frequency(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Figure 80. Unused I/O pins configured as input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Figure 81. Typical IPU vs VDD with VIN = VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Figure 82. Typical VOL at VDD = 5V (standard) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Figure 83. Typical VOL at VDD = 5V (high-sink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Figure 84. Typical VOH at VDD = 5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Figure 85. Typical VOL versus VDD (standard). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Figure 86. Typical VOL versus VDD (high-sink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Figure 87. Typical VDD-VOH versus VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Figure 88. RESET pin protection when LVD is enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Figure 89. RESET pin protection when LVD is disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Figure 90. Two typical applications with ICCSEL/VPP pin(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Figure 91. SPI slave timing diagram with CPHA = 0(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Figure 92. SPI slave timing diagram with CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Figure 93. SPI master timing diagram(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Figure 94. Typical application with I2C BUS and timing diagram(1) . . . . . . . . . . . . . . . . . . . . . . . . . 223
Figure 95. RAIN maximum versus fADC with CAIN = 0pF(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Figure 96. Recommended CAIN and RAIN values(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Figure 97. Typical A/D converter application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Figure 98. Power supply filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Figure 99. ADC error classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Figure 100. 64-pin (14x14) low profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
16/250
ST72325xxx-Auto
List of figures
Figure 101. 64-pin (10x10) low profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Figure 102. 44-pin (10x10) low profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Figure 103. 32-pin low profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Figure 104. Flash commercial product code structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Figure 105. FASTROM commercial product code structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
17/250
Introduction
ST72325xxx-Auto
1
Introduction
1.1
Description
The ST72325-Auto devices are members of the ST7 microcontroller family designed for
mid-range automotive applications running from 3.8 to 5.5V. Different package options offer
up to 48 I/O pins.
They are derivatives of the ST72321 and ST72324 devices, with enhanced characteristics
and robust Clock Security System.
All devices are based on a common industry-standard 8-bit core, featuring an enhanced
instruction set and are available with Flash program memory. The ST7 family architecture
offers both power and flexibility to software developers, enabling the design of highly
efficient and compact application code.
The on-chip peripherals include an A/D converter, a PWM autoreload timer, two general
2
purpose timers, I C, SPI and SCI interfaces.
For power economy, the microcontroller can switch dynamically into Wait, Slow, Active Halt
or Halt mode when the application is in idle or standby state.
Typical applications include
●
all types of car body applications such as window lift, DC motor control, rain sensors
safety microcontroller in airbag and engine management applications
auxiliary functions in car radios
●
●
The devices feature an on-chip Debug Module (DM) to support in-circuit debugging (ICD).
For a description of the DM registers, refer to the ST7 ICC Protocol Reference Manual.
Main differences with ST72321:
●
●
●
●
●
LQFP32 package
Clock Security System
Internal RC, readout protection, LVD and PLL without limitations
Negative current injection not allowed on I/O port PB0 (instead of PC6)
External interrupts have Exit from Active Halt mode capability
Table 1.
Device summary
Reference
Program memory
RAM (stack)
Voltage range
Temp. range
Package
ST72325K4-Auto
ST72325K6-Auto
ST72325J4-Auto
ST72325J6-Auto
ST72325J7-Auto
ST72325J9-Auto
ST72325AR6-Auto
ST72325AR7-Auto
ST72325AR9-Auto
Flash 16 Kbytes
Flash 32 Kbytes
Flash 16 Kbytes
Flash 32 Kbytes
Flash 48 Kbytes
Flash 60 Kbytes
Flash 32 Kbytes
Flash 48 Kbytes
Flash 60 Kbytes
512 (256) bytes
1024 (256) bytes
512 (256) bytes
1024 (256) bytes
1536 (256) bytes
2048 (256) bytes
1024 (256) bytes
1536 (256) bytes
2048 (256) bytes
LQFP32
LQFP44
up to
-40 to 125°C
3.8 to 5.5V
LQFP64
10x10
18/250
ST72325xxx-Auto
Introduction
Package
Table 1.
Device summary (continued)
Reference
Program memory
RAM (stack)
Voltage range
Temp. range
ST72325R6-Auto
ST72325R7-Auto
ST72325R9-Auto
Flash 32 Kbytes
Flash 48 Kbytes
Flash 60 Kbytes
1024 (256) bytes
1536 (256) bytes
2048 (256) bytes
up to
-40 to 125°C
LQFP64
14x14
3.8 to 5.5V
Figure 1.
Device block diagram
8-BIT CORE
PROGRAM
MEMORY
ALU
(1)
16 - 60 Kbytes
RESET
CONTROL
V
PP
RAM
TLI
(1)
512 - 2048 bytes
V
SS
DD
LVD
AVD
OSC
V
EVD
WATCHDOG
DEBUG MODULE
I2C
OSC1
OSC2
MCC/RTC/BEEP
PA7:0
(8 bits on R/AR devices)
PORT F
TIMER A
BEEP
(5 bits on J devices)
(4 bits on K devices)
PORT A
PF7:0
(8 bits on R/AR devices)
(6 bits on J devices)
(5 bits on K devices)
PORT B
PB7:0
(8 bits on R/AR devices)
(5 bits on J devices)
(3 bits on K devices)
PWM ART
PORT E
PE7:0
(8 bits on R/AR devices)
(2 bits on J/K devices)
PORT C
TIMER B
SPI
SCI
PC7:0
(8 bits)
PORT D
PD7:0
(8 bits on R/AR devices)
(6 bits on J devices)
10-BIT ADC
(2 bits on K devices)
V
AREF
V
SSA
1. On certain devices only (see Device summary)
19/250
Introduction
ST72325xxx-Auto
1.2
Differences between ST72325-Auto and ST72325 datasheets
The following sections list the differences between the ST72325-Auto datasheet (version 1)
and the ST72325 datasheet (version 3 dated 4 April 2007).
1.2.1
Principal differences
Principal differences between the ST72325-Auto datasheet (version 1) and the ST72325
datasheet (version 3 dated 4 April 2007) are listed as follows:
1. Removed ROM devices throughout document
2. Changed document title and description on page 1
3. Removed SDIP packages and LQFP48 from package outlines on page 1
4. Memories on page 1:
–
–
removed ROM from features
modified data retention period and removed temperature
5. Table 105: Current characteristics on page 196:
–
–
–
–
–
–
removed 48-pin device from ratings for I
/ I
VDD VSS
changed max value for Output current sunk by any standard I/O and control pin
changed max value for Output current sunk by any high sink I/O pin
removed ‘(Flash devices only)’ from rating ‘Injected current on PB0 pin’
reorganized order of footnotes
modified Note 3 on page 196
6. Table 111: Current consumption on page 200:
–
–
removed ROM-specific values
changed typ and max values in Active Halt mode
7. Table 116: Crystal and ceramic resonator oscillators on page 204:
–
–
–
modified conditions for C , C
L1 L2
modified conditions for i
reorganized footnotes
2
8. Table 122: Dual voltage HDFlash memory on page 207:
–
–
modified data retention conditions and min value
modified conditions for write erase cycles
9. Table 123: EMS test results on page 209: Removed phrase ‘All Flash and ROM
devices’ from V conditions
FESD
10. Table 124: EMI emissions on page 209:
–
–
–
–
–
added LQFP44 to 48/60 Kbyte Flash device conditions
added 32 Kbyte Flash device in LQFP64 to conditions
added LQFP32 to conditions for 16/32 Kbyte Flash
removed ROM devices from conditions
removed footnote 2 referencing AN1709
11. Table 136: 10-bit ADC characteristics on page 224:
–
replaced ‘positive input leakage current’ with ‘input leakage current’ and added
Note 2
–
removed ‘negative input leakage current’ parameter, conditions and values
20/250
ST72325xxx-Auto
12. Table 137: ADC accuracy on page 227:
Introduction
–
–
–
added max values specific to 16/32Kbyte Flash devices
removed ROM devices from max values
added conditions to total unadjusted error, to offset error and to gain error
13. Section 20.1: Package mechanical data on page 228:
–
–
removed 48-pin LQFP package
removed DIP packages
14. Table 142: Thermal characteristics on page 232:
–
–
added LQFP64 14x14 package to R
thJA
removed LQFP48 and SDIP packages from R
thJA
15. Table 144: Flash option bytes on page 233:
–
–
–
Option byte 0: Changed OPT1 to reserved
Option byte 1: Replaced OPT7 default value with footnote
Option byte 1: Changed reset value of OPT3 from 1 to 0
16. Table 145: Option byte 0 bit description on page 233: Changed OPT1 to reserved
17. Table 146: Option byte 1 bit description on page 234: Modified function text for
OSCRANGE[2:0]
18. Table 147: Package selection (OPT7) on page 235:
–
–
removed LQFP48 packages and related note concerning unbonded pads
removed SDIP packages
19. Section 21.2: FASTROM device ordering information and transfer of customer code on
page 237:
–
–
–
changed title
edited introductory paragraphs and removed references to ROM
removed caution concerning inverted readout protection value between ROM and
Flash
–
–
–
–
–
removed figure ROM factory coded device types
added Table 149: FASTROM factory coded device types on page 237
added Figure 105: FASTROM commercial product code structure on page 239
removed note inviting reader to contact sales office for updated order codes list
replaced separate FASTROM and ROM option lists with one ST72325-Auto
Microcontroller FASTROM Option List on page 240
20. Chapter 22: Known limitations on page 243: Removed section ADC accuracy
16/32 Kbyte Flash devices
21. Section 22.1.6: TIMD set simultaneously with OC interrupt on page 248: Added timer B
registers TBCR1 and TBCSR to disable and enable sequences in Workaround
1.2.2
Minor content differences
1. Section 1.1: Description on page 18:
–
–
–
removed LQFP48 from list of differences with ST72321
modified text in introductory paragraphs
removed all references to ROM
2. Table 1: Device summary on page 18:
21/250
Introduction
ST72325xxx-Auto
–
–
–
transferred from cover page to Section 1.1: Description
updated to include only automotive devices
removed ROM from program memory column
3. Figure 1: Device block diagram on page 19:
–
–
–
added R devices to bit counts for ports F, E, D, C, B and A
removed C devices from bit counts for ports F, E, D, B and A
modified Note 1
4. Chapter 2: Package pinout and pin description on page 25: Removed following figures:
–
–
48-pin LQFP pinout
32-pin DIP and 42-pin DIP pinouts
5. Figure 4: 32-pin LQFP package pinout on page 27: Removed DIP package
6. Table 2: Device pin descriptions (LQFP64 and LQFP44) on page 28:
–
–
–
–
–
–
removed LQFP48 and SDIP42 devices
reorganized footnotes
removed ‘High voltage must not be applied to ROM devices’ from V function text
PP
removed footnote link from PA6 and PA7 alternate functions cells
linked Note 1 to unbonded I/O pins in LQFP44 column
defined pin EVD as type ‘I’ and as input level ‘A’
7. Table 3: Device pin descriptions (LQFP32) on page 32:
–
–
–
–
–
removed DIP32 device
reorganized footnotes
removed ‘High voltage must not be applied to ROM devices’ from V function text
PP
removed footnote link from PA6 and PA7 alternate functions cells
removed footnote concerning pads that are not bonded
8. Section 4.3.1: Readout protection on page 40: Removed references to ROM devices
9. Figure 3: 44-pin LQFP package pinout on page 26: Aligned pin names for pins 2, 3, 4, 5
and 6 to those in Table 2
10. Section 4.6: IAP (in-application programming) on page 42: Removed reference to USB
and CAN interfaces in second paragraph
11. Section 9.3: I/O port implementation on page 83: Removed following five tables:
–
–
–
–
–
Standard ports PA5:4, PC7:0, PD7:0, PE7:3, PE1:0, PF7:3
Interrupt ports PA2:0, PB6:5, PB4, PB2:0, PF1:0 (with pull-up)
Interrupt ports PA3, PB7, PB3, PF2 (without pull-up)
True open-drain ports PA7:6
Pull-up input port PE2 (configurations of these five tables already exist in Table 31:
I/O port configuration on page 83)
12. Table 31: I/O port configuration on page 83:
–
–
added DDR values to input and output column headers
modified Note 1
13. Table 104: Voltage characteristics on page 195: Removed note 2 (this note exists only
as Note 2 for Table 105)
14. Section 17.3.2: Starting the conversion on page 182: Replaced ‘A read to the ADCDRH
resets the EOC bit’ with ‘A read to the ADCDRH or a write to any bit of the ADCCSR
22/250
ST72325xxx-Auto
register resets the EOC bit’
Introduction
15. Table 107: General operating conditions on page 197: Modified conditions for ambient
temperature range to include only automotive specific versions
16. Table 108: Operating conditions with low voltage detector (LVD) on page 198:
–
–
reorganized order of footnotes
removed ‘tested in production for ROM devices only’ from Note 1
17. Table 109: Auxiliary voltage detector (AVD) thresholds on page 198: Removed ‘tested
in production for ROM devices only’ from Note 1
18. Table 117: Resonator characteristics on page 205:
–
–
–
removed Lead-type part numbers
removed SMD-type code from part numbers
removed note 2 detailing Lead- and SMD-types
19. Table 127: I/O port pin general characteristics on page 211:
–
–
removed ‘(Flash devices only)’ from rating ‘Injected current on PB0 pin’
modified Note 4
20. Table 133: SPI characteristics on page 219: Reorganized footnotes
21. Table 138: 64-pin (14x14) low profile quad flat package mechanical data on page 228:
Added Note 1
22. Table 139: 64-pin (10x10) low profile quad flat package mechanical data on page 229:
Added Note 1
23. Table 143: Soldering compatibility (wave and reflow soldering process) on page 232:
Updated plating materials to be package specific
24. Table 148: Flash user programmable device types on page 236:
–
–
–
changed title
updated to include only automotive devices
added Note 1
25. Added Figure 104: Flash commercial product code structure on page 237
26. Section 21.3: Development tools on page 241: Updated content
27. Table 150: STMicroelectronics development tools on page 242:
–
–
–
removed C and S device versions
added R device version
updated listed tools
28. Table 151: Suggested list of socket types on page 242: Removed LQFP48 device
29. Section 21.4: ST7 application notes on page 242: Removed table ST7 Application
Notes
1.2.3
Editing and formatting differences
1. Reformatted document
2. Feature 1 analog peripheral (low current coupling) on page 1: Replaced ‘up to 16
robust input ports’ with ‘up to 16 input ports’
3. Table 115: External clock source on page 203: Replaced symbol for input leakage
current I with I
L
lkg
4. Figure 76: Typical application with an external clock source on page 203: Changed
symbol for ‘input leakage current’ from I to I
L
lkg
23/250
Introduction
ST72325xxx-Auto
5. Table 130: ICCSEL/VPP pin characteristics on page 217: Replaced symbol for input
leakage current I with I
L
lkg
6. Figure 97: Typical A/D converter application on page 225:
–
–
changed symbol for ‘input leakage current’ from I to I
L lkg
removed I value ‘ 1µA’
lkg
7. Section 18.1.4: Indexed (no offset, short, long) on page 188: Replaced ‘The indirect
addressing mode consists of’ with ‘The indexed addressing mode consists of’
8. Chapter 21: Device configuration and ordering information on page 233: Reorganized
subsections and made minor text editing changes
9. Table 127: I/O port pin general characteristics on page 211: Replaced symbol for input
leakage current I with I
L
lkg
10. Table 142: Thermal characteristics on page 232: Corrected order of footnotes
24/250
ST72325xxx-Auto
Package pinout and pin description
2
Package pinout and pin description
2.1
Package pinout
Figure 2.
64-pin LQFP 14x14 and 10x10 package pinout
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
VSS_1
VDD_1
PA3 (HS)
PA2
PA1
PA0
PC7 / SS / AIN15
PC6 / SCK / ICCCLK
PC5 / MOSI / AIN14
PC4 / MISO / ICCDATA
PC3 (HS) / ICAP1_B
PC2 (HS) / ICAP2_B
PC1 / OCMP1_B / AIN13
PC0 / OCMP2_B / AIN12
VSS_0
(HS) PE4
(HS) PE5
(HS) PE6
1
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
2
3
(HS) PE7
4
ei0
PWM3 / PB0
PWM2 / PB1
PWM1 / PB2
PWM0 / PB3
5
6
ei2
ei3
7
8
ARTCLK / (HS) PB4
ARTIC1 / PB5
ARTIC2 / PB6
PB7
9
10
11
12
13
14
15
16
AIN0 / PD0
AIN1 / PD1
AIN2 / PD2
AIN3 / PD3
ei1
VDD_0
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
(HS) 20mA high sink capability
eix associated external interrupt vector
25/250
Package pinout and pin description
ST72325xxx-Auto
Figure 3.
44-pin LQFP package pinout
44 43 42 41 40 39 38 37 36 35 34
RDI / PE1
PWM3 / PB0
PWM2 / PB1
PWM1 / PB2
PWM0 / PB3
ARTCLK / (HS) PB4
AIN0 / PD0
1
2
3
4
5
6
7
8
9
VSS_1
VDD_1
PA3 (HS)
PC7 / SS / AIN15
33
32
31
30
ei0
ei2
ei3
29 PC6 / SCK / ICCCLK
28 PC5 / MOSI / AIN14
27 PC4 / MISO / ICCDATA
26 PC3 (HS) / ICAP1_B
25 PC2 (HS) / ICAP2_B
24 PC1 / OCMP1_B / AIN13
AIN1 / PD1
AIN2 / PD2
ei1
AIN3 / PD3 10
AIN4 / PD4 11
23
PC0 / OCMP2_B / AIN12
12 13 14 15 16 17 18 19 20 21 22
(HS) 20mA high sink capability
eix associated external interrupt vector
26/250
ST72325xxx-Auto
Figure 4. 32-pin LQFP package pinout
Package pinout and pin description
32 31 30 29 28 27 26 25
24
VAREF
VSSA
MCO / AIN8 / PF0
BEEP / (HS) PF1
1
2
3
4
5
6
7
8
OSC1
OSC2
ei3 ei2
23
22
21
20
19
18
17
VSS 2
RESET
PP / ICCSEL
_
ei1
OCMP1_A / AIN10 / PF4
ICAP1_A / (HS) PF6
EXTCLK_A / (HS) PF7
AIN12 / OCMP2_B / PC0
V
PA7 (HS) / SCLI
PA6 (HS) / SDAI
PA4 (HS)
ei0
9 10 11 12 13 14 15 16
(HS) 20mA high sink capability
eix associated external interrupt vector
For external pin connection guidelines, refer to Chapter 19: Electrical characteristics.
27/250
Package pinout and pin description
ST72325xxx-Auto
2.2
Pin description
In the device pin description table, the RESET configuration of each pin is shown in bold.
This configuration is valid as long as the device is in reset state.
Refer to Chapter 9: I/O ports on page 79 for more details on the software configuration of
the I/O ports.
Table 2.
No.
Device pin descriptions (LQFP64 and LQFP44)
Pin
Level
Port
Main
function
(after
Input
Output
Alternate function
Name
reset)
1
2
3
4
-
-
-
-
PE4 (HS)
PE5 (HS)
PE6 (HS)
PE7 (HS)
I/O CT HS
I/O CT HS
I/O CT HS
I/O CT HS
X
X
X
X
X
X
X
X
X
X
X
X
X
Port E4
Port E5
Port E6
Port E7
X
X
X
PWM Output 3
Caution: Negative
current injection not
allowed on this pin
5
2
PB0/PWM3
I/O CT
X
ei2
X
X
Port B0
6
7
8
3
4
5
PB1/PWM2
PB2/PWM1
PB3/PWM0
I/O CT
I/O CT
I/O CT
X
X
X
ei2
ei2
X
X
X
X
X
X
Port B1
Port B2
Port B3
PWM Output 2
PWM Output 1
PWM Output 0
ei2
PWM-ART External
Clock
9
6
PB4 (HS)/ARTCLK
PB5 / ARTIC1
I/O CT HS
I/O CT
X
X
X
ei3
ei3
ei3
X
X
X
X
X
X
Port B4
Port B5
Port B6
PWM-ART Input
Capture 1
(1)
10
11
-
PWM-ART Input
Capture 2
(1)
(1)
-
-
PB6 / ARTIC2
I/O CT
12
13
14
15
PB7
I/O CT
I/O CT
I/O CT
I/O CT
I/O CT
I/O CT
I/O CT
I/O CT
I/O CT
I
X
X
X
X
X
X
X
X
X
ei3
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Port B7
Port D0
Port D1
Port D2
Port D3
Port D4
Port D5
Port D6
Port D7
7
8
9
PD0/AIN0
PD1/AIN1
PD2/AIN2
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
ADC Analog Input 0
ADC Analog Input 1
ADC Analog Input 2
ADC Analog Input 3
ADC Analog Input 4
ADC Analog Input 5
ADC Analog Input 6
ADC Analog Input 7
16 10 PD3/AIN3
17 11 PD4/AIN4
18 12 PD5/AIN5
(1)
19
20
-
-
PD6/AIN6
(1)
PD7/AIN7
(2)
21 13 VAREF
Analog Reference Voltage for ADC
Analog Ground Voltage
(2)
22 14 VSSA
S
28/250
ST72325xxx-Auto
Package pinout and pin description
Table 2.
No.
Device pin descriptions (LQFP64 and LQFP44) (continued)
Pin
Level
Port
Main
function
(after
Input
Output
Alternate function
Name
reset)
(2)
23
24
-
-
VDD_3
S
S
Digital Main Supply Voltage
Digital Ground Voltage
(2)
VSS_3
ADC
Analog
Input 8
Main clock
out (fOSC/2)
25 15 PF0/MCO/AIN8
I/O CT
X
ei1
ei1
X
X
X
Port F0
26 16 PF1 (HS)/BEEP
27 17 PF2 (HS)
I/O CT HS
I/O CT HS
X
X
X
X
X
X
Port F1
Port F2
Beep signal output
ei1
Timer A
Output
Compare 2 Input 9
ADC
Analog
PF3/OCMP2_A/
AIN9
(1)
28
-
I/O CT
I/O CT
X
X
X
X
X
X
X
X
X
X
X
X
X
Port F3
Port F4
Port F5
Timer A
Output
Compare 1 Input 10
ADC
Analog
PF4/OCMP1_A/
AIN10
29 18
X
X
Timer A
Input
Capture 2
ADC
Analog
Input 11
(1)
30
-
PF5/ICAP2_A/AIN11 I/O CT
I/O CT HS
31 19 PF6 (HS)/ICAP1_A
X
X
X
X
X
X
X
X
Port F6
Port F7
Timer A Input Capture 1
Timer A External Clock
Source
32 20 PF7 (HS)/EXTCLK_A I/O CT HS
(2)
33 21 VDD_0
S
S
Digital Main Supply Voltage
Digital Ground Voltage
(2)
34 22 VSS_0
Timer B
Output
Compare 2 Input 12
ADC
Analog
PC0/OCMP2_B/
AIN12
35 23
36 24
I/O CT
I/O CT
X
X
X
X
X
X
X
X
X
X
Port C0
Port C1
Timer B
Output
Compare 1 Input 13
Timer B Input Capture 2
Timer B Input Capture 1
ADC
Analog
PC1/OCMP1_B/
AIN13
37 25 PC2 (HS)/ICAP2_B
38 26 PC3 (HS)/ICAP1_B
I/O CT HS
I/O CT HS
X
X
X
X
X
X
X
X
Port C2
Port C3
SPI Master
ICC Data
In / Slave
Input
39 27 PC4/MISO/ICCDATA I/O CT
X
X
X
X
Port C4
Out Data
SPI Master ADC
40 28 PC5/MOSI/AIN14
41 29 PC6/SCK/ICCCLK
I/O CT
I/O CT
X
X
X
X
X
X
X
X
X
Port C5
Port C6
Out / Slave Analog
In Data
Input 14
SPI Serial ICC Clock
Clock Output
29/250
Package pinout and pin description
ST72325xxx-Auto
Alternate function
Table 2.
No.
Device pin descriptions (LQFP64 and LQFP44) (continued)
Pin
Level
Port
Main
function
(after
Input
Output
Name
reset)
SPI Slave
Select
ADC
Analog
42 30 PC7/SS/AIN15
I/O CT
X
X
X
X
X
Port C7
(active low) Input 15
(1)
43
44
45
-
-
-
PA0
PA1
PA2
I/O CT
X
X
X
X
ei0
ei0
ei0
X
X
X
X
X
X
X
X
Port A0
Port A1
Port A2
Port A3
(1)
(1)
I/O CT
I/O CT
46 31 PA3 (HS)
I/O CT HS
S
ei0
(2)
47 32 VDD_1
Digital Main Supply Voltage
Digital Ground Voltage
Port A4
(2)
48 33 VSS_1
S
49 34 PA4 (HS)
I/O CT HS
I/O CT HS
I/O CT HS
I/O CT HS
X
X
X
X
X
X
X
X
T
T
X
X
50 35 PA5 (HS)
Port A5
51 36 PA6 (HS)/SDAI
52 37 PA7 (HS)/SCLI
Port A6
Port A7
I2C Data
I2C Clock
Must be tied low. In Flash
programming mode, this pin acts as
53 38 VPP/ ICCSEL
54 39 RESET
I
the programming voltage input VPP.
See Section 19.9.2: ICCSEL/VPP
pin for more details.
I/O CT
Top priority non maskable interrupt.
External voltage detector
55
56
-
-
EVD
TLI
I
I
A
CT
X
Top level interrupt input pin
Digital Ground Voltage
(2)
57 40 VSS_2
S
58 41 OSC2(3)
I/O
Resonator oscillator inverter output
External clock input or Resonator
oscillator inverter input
59 42 OSC1(3)
I
(2)
60 43 VDD_2
S
Digital Main Supply Voltage
61 44 PE0/TDO
I/O CT
I/O CT
I/O CT
I/O CT
X
X
X
X
X
X
X
X
X
X
X
X
Port E0
SCI Transmit Data Out
SCI Receive Data In
62
63
64
1
PE1/RDI
PE2
Port E1
(1)
-
-
X(4) X(4) Port E2
(1)
PE3
X
X
Port E3
1. On the chip, each I/O port may have up to eight pads. Pads that are not bonded to external pins are in input pull-up
configuration after reset. The configuration of these pads must be kept at reset state to avoid added current consumption.
2. It is mandatory to connect all available VDD and VAREF pins to the supply voltage and all VSS and VSSA pins to ground.
3. OSC1 and OSC2 pins connect a crystal/ceramic resonator, or an external source to the on-chip oscillator; see Chapter 1:
Introduction and Section 19.5: Clock and timing characteristics for more details.
30/250
ST72325xxx-Auto
Package pinout and pin description
4. Pull-up always activated on PE2 (see Section 22.1.8: Pull-up always active on PE2 on page 248).
Legend / Abbreviations for Table 2:
Type:
I = input
O = output
S = supply
Input level:
A = dedicated analog input
In/Output level:
C = CMOS 0.3V /0.7V
DD DD
C = CMOS 0.3V /0.7V with input trigger
T
DD
DD
Output level:
HS = 20mA high sink (on N-buffer only)
Port and control configuration:
●
Input:
float = floating
wpu = weak pull-up
(a)
int = interrupt
ana = analog
(b)
●
Output:
OD = open-drain
PP = push-pull
a. In the interrupt input column, “eiX” defines the associated external interrupt vector. If the weak pull-up column
(wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input, otherwise
the configuration is floating interrupt input.
b. In the open-drain output column, “T” defines a true open-drain I/O (P-Buffer and protection diode to VDD are not
implemented). See Chapter 9: I/O ports on page 79 and Section 19.8: I/O port pin characteristics on page 211
for more details.
31/250
Package pinout and pin description
ST72325xxx-Auto
Alternate function
Table 3.
Device pin descriptions (LQFP32)
Level
Port
Pin
Main
function
Input
Output
(after reset)
No.
Name
(1)
1
2
VAREF
I
Analog Reference Voltage for ADC
Analog Ground Voltage
(1)
VSSA
S
Main clock
out (fOSC/2) Input 8
ADC Analog
3
4
PF0/MCO/AIN8
PF1 (HS)/BEEP
I/O CT
X
X
ei1
ei1
X
X
X
X
X
X
Port F0
Port F1
I/O CT HS
Beep signal output
Timer A
Output
Compare 1
ADC Analog
Input 10
5
PF4/OCMP1_A/AIN10 I/O CT
X
X
X
X
Port F4
6
7
PF6 (HS)/ICAP1_A
I/O CT HS
X
X
X
X
X
X
X
X
Port F6
Port F7
Timer A Input Capture 1
Timer A External Clock
Source
PF7 (HS)/EXTCLK_A I/O CT HS
Timer B
Output
Compare 2
ADC Analog
Input 12
8
9
PC0/OCMP2_B/AIN12 I/O CT
PC1/OCMP1_B/AIN13 I/O CT
X
X
X
X
X
X
X
X
X
X
Port C0
Port C1
Timer B
Output
Compare 1
ADC Analog
Input 13
10 PC2 (HS)/ICAP2_B
11 PC3 (HS)/ICAP1_B
I/O CT HS
I/O CT HS
X
X
X
X
X
X
X
X
Port C2
Port C3
Timer B Input Capture 2
Timer B Input Capture 1
SPI Master
ICC Data
In / Slave
Input
12 PC4/MISO/ICCDATA
I/O CT
X
X
X
X
Port C4
Out Data
SPI Master
ADC Analog
Out / Slave
Input 14
13 PC5/MOSI/AIN14
14 PC6/SCK/ICCCLK
15 PC7/SS/AIN15
16 PA3 (HS)
I/O CT
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Port C5
Port C6
Port C7
Port A3
In Data
SPI Serial
Clock
ICC Clock
Output
I/O CT
SPI Slave
Select
(active low)
ADC Analog
Input 15
I/O CT
ei
0
I/O CT HS
X
X
17 PA4 (HS)
I/O CT HS
I/O CT HS
I/O CT HS
X
X
X
X
X
T
T
Port A4
Port A6
Port A7
18 PA6 (HS)/SDAI
19 PA7 (HS)/SCLI
I2C Data
I2C Clock
Must be tied low. In Flash programming
mode, this pin acts as the programming
voltage input VPP. See Section 19.9.2:
ICCSEL/VPP pin for more details.
20 VPP/ ICCSEL
I
32/250
ST72325xxx-Auto
Package pinout and pin description
Table 3.
Device pin descriptions (LQFP32) (continued)
Level Port
Pin
Main
function
Input
Output
Alternate function
(after reset)
No.
Name
21 RESET
I/O CT
Top priority non maskable interrupt
Digital Ground Voltage
(1)
22 VSS_2
S
23 OSC2(2)
I/O
Resonator oscillator inverter output
External clock input or Resonator
oscillator inverter input
24 OSC1(2)
I
(1)
25 VDD_2
S
Digital Main Supply Voltage
26 PE0/TDO
27 PE1/RDI
I/O CT
I/O CT
X
X
X
X
X
X
X
X
Port E0
Port E1
SCI Transmit Data Out
SCI Receive Data In
PWM Output 3
Caution: Negative current
injection not allowed on this
pin
28 PB0/PWM3
I/O CT
X
ei2
X
X
Port B0
ei
2
29 PB3/PWM0
I/O CT
X
X
X
Port B3
PWM Output 0
30 PB4 (HS)/ARTCLK
31 PD0/AIN0
I/O CT HS
I/O CT
X
X
X
ei3
X
X
X
X
X
X
Port B4
Port D0
Port D1
PWM-ART External Clock
ADC Analog Input 0
ADC Analog Input 1
X
X
X
32 PD1/AIN1
I/O CT
X
1. It is mandatory to connect all available VDD and VAREF pins to the supply voltage and all VSS and VSSA pins to ground.
2. OSC1 and OSC2 pins connect a crystal/ceramic resonator, or an external source to the on-chip oscillator; see Chapter 1:
Introduction and Section 19.5: Clock and timing characteristics for more details.
Legend / Abbreviations for Table 3:
Type:
I = input
O = output
S = supply
Input level:
A = Dedicated analog input
In/Output level:
C = CMOS 0.3V /0.7V
DD DD
C = CMOS 0.3V /0.7V with input trigger
T
DD
DD
Output level:
HS = 20mA high sink (on N-buffer only)
Port and control configuration:
●
Input:
float = floating
wpu = weak pull-up
(c)
int = interrupt
c. In the interrupt input column, “eiX” defines the associated external interrupt vector. If the weak pull-up column
(wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input, else the
configuration is floating interrupt input.
33/250
Package pinout and pin description
ana = analog
ST72325xxx-Auto
(d)
●
Output:
OD = open-drain
PP = push-pull
d. In the open-drain output column, “T” defines a true open-drain I/O (P-Buffer and protection diode to VDD are not
implemented). See Chapter 9: I/O ports on page 79 and Section 19.8: I/O port pin characteristics on page 211
for more details.
34/250
ST72325xxx-Auto
Register and memory map
3
Register and memory map
As shown in Figure 5, the MCU is capable of addressing 64 Kbytes of memories and I/O
registers.
The available memory locations consist of 128 bytes of register locations, up to 2 Kbytes of
RAM and up to 60 Kbytes of user program memory. The RAM space includes up to 256
bytes for the stack from 0100h to 01FFh.
The highest address bytes contain the user reset and interrupt vectors.
Caution:
Memory locations marked as “Reserved” must never be accessed. Accessing a reserved
area can have unpredictable effects on the device.
Related documentation
Executing Code in ST7 RAM (AN 985)
Figure 5.
Memory map
0000h
0080h
HW Registers
Short Addressing
RAM (zero page)
(see Table 4)
007Fh
0080h
00FFh
0100h
RAM
(2048, 1536, 1024,
256 bytes Stack
01FFh
0200h
or 512 bytes)
Reserved
1000h
4000h
60 Kbytes
48 Kbytes
087Fh
0880h
16-bit Addressing
RAM
027Fh
or 047Fh
or 067Fh
or 087Fh
0FFFh
1000h
8000h
C000h
Program Memory
(60, 48, 32 or 16 Kbytes)
32 Kbytes
16 Kbytes
FFDFh
FFE0h
Interrupt and Reset Vectors
FFFFh
(see Table 20)
FFFFh
35/250
Register and memory map
ST72325xxx-Auto
Table 4.
Address
Hardware register map
Block
Register label
Register name
Port A Data Register
Port A Data Direction Register
Port A Option Register
Reset status Remarks
0000h
0001h
0002h
PADR
PADDR
PAOR
00h(1)
00h
R/W
R/W
R/W
Port A
00h
0003h
0004h
0005h
PBDR
PBDDR
PBOR
Port B Data Register
Port B Data Direction Register
Port B Option Register
00h(1)
00h
00h
R/W
R/W
R/W
Port B
Port C
Port D
Port E
Port F
0006h
0007h
0008h
PCDR
PCDDR
PCOR
Port C Data Register
Port C Data Direction Register
Port C Option Register
00h(1)
00h
00h
R/W
R/W
R/W
0009h
000Ah
000Bh
PDDR
PDDDR
PDOR
Port D Data Register
Port D Data Direction Register
Port D Option Register
00h(1)
00h
00h
R/W
R/W
R/W
000Ch
000Dh
000Eh
PEDR
PEDDR
PEOR
Port E Data Register
Port E Data Direction Register
Port E Option Register
00h(1)
00h
00h
R/W
R/W(2)
R/W(2)
000Fh
0010h
0011h
PFDR
PFDDR
PFOR
Port F Data Register
Port F Data Direction Register
Port F Option Register
00h(1)
00h
00h
R/W
R/W
R/W
0018h
0019h
001Ah
001Bh
001Ch
001Dh
001Eh
I2CCR
I2C Control Register
00h
00h
00h
00h
00h
00h
00h
R/W
I2CSR1
I2CSR2
I2CCCR
I2COAR1
I2COAR2
I2CDR
I2C Status Register 1
I2C Status Register 2
I2C Clock Control Register
I2C Own Address Register 1
I2C Own Address Register2
I2C Data Register
Read only
Read only
R/W
R/W
R/W
I2C
R/W
001Fh
0020h
Reserved area (2 bytes)
0021h
0022h
0023h
SPIDR
SPICR
SPICSR
SPI Data I/O Register
SPI Control Register
SPI Control/Status Register
xxh
0xh
00h
R/W
R/W
R/W
SPI
0024h
0025h
0026h
0027h
ISPR0
ISPR1
ISPR2
ISPR3
Interrupt Software Priority Register 0
Interrupt Software Priority Register 1
Interrupt Software Priority Register 2
Interrupt Software Priority Register 3
FFh
FFh
FFh
FFh
R/W
R/W
R/W
R/W
ITC
0028h
0029h
EICR
External Interrupt Control Register
Flash Control/Status Register
00h
00h
7Fh
R/W
R/W
R/W
FLASH
FCSR
002Ah WATCHDOG WDGCR
Watchdog Control Register
002Bh
SICSR
System Integrity Control/Status Register
000x 000x b R/W
002Ch
002Dh
MCCSR
MCCBCR
Main Clock Control/Status Register
Main Clock Controller/Beep Control Register
00h
00h
R/W
R/W
MCC
002Eh
to
Reserved area (3 bytes)
0030h
36/250
ST72325xxx-Auto
Register and memory map
Reset status Remarks
Table 4.
Address
Hardware register map (continued)
Block
Register label
Register name
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
TACR2
TACR1
TACSR
TAIC1HR
TAIC1LR
TAOC1HR
TAOC1LR
TACHR
Timer A Control Register 2
Timer A Control Register 1
Timer A Control/Status Register
Timer A Input Capture 1 High Register
Timer A Input Capture 1 Low Register
Timer A Output Compare 1 High Register
Timer A Output Compare 1 Low Register
Timer A Counter High Register
00h
00h
R/W
R/W
xxxx x0xxb R/W
xxh
xxh
80h
00h
FFh
FCh
FFh
FCh
xxh
xxh
80h
00h
Read only
Read only
R/W
R/W
TIMER A
Read only
Read only
Read only
Read only
Read only
Read only
R/W
TACLR
Timer A Counter Low Register
TAACHR
TAACLR
TAIC2HR
TAIC2LR
TAOC2HR
TAOC2LR
Timer A Alternate Counter High Register
Timer A Alternate Counter Low Register
Timer A Input Capture 2 High Register
Timer A Input Capture 2 Low Register
Timer A Output Compare 2 High Register
Timer A Output Compare 2 Low Register
R/W
0040h
Reserved area (1 byte)
0041h
0042h
0043h
0044h
0045h
0046h
0047h
0048h
0049h
004Ah
004Bh
004Ch
004Dh
004Eh
004Fh
TBCR2
TBCR1
TBCSR
TBIC1HR
TBIC1LR
TBOC1HR
TBOC1LR
TBCHR
Timer B Control Register 2
Timer B Control Register 1
Timer B Control/Status Register
Timer B Input Capture 1 High Register
Timer B Input Capture 1 Low Register
Timer B Output Compare 1 High Register
Timer B Output Compare 1 Low Register
Timer B Counter High Register
00h
00h
R/W
R/W
xxxx x0xxb R/W
xxh
xxh
80h
00h
FFh
FCh
FFh
FCh
xxh
xxh
80h
00h
Read only
Read only
R/W
R/W
TIMER B
Read only
Read only
Read only
Read only
Read only
Read only
R/W
TBCLR
Timer B Counter Low Register
TBACHR
TBACLR
TBIC2HR
TBIC2LR
TBOC2HR
TBOC2LR
Timer B Alternate Counter High Register
Timer B Alternate Counter Low Register
Timer B Input Capture 2 High Register
Timer B Input Capture 2 Low Register
Timer B Output Compare 2 High Register
Timer B Output Compare 2 Low Register
R/W
0050h
0051h
0052h
0053h
0054h
0055h
0056h
0057h
SCISR
SCIDR
SCIBRR
SCICR1
SCICR2
SCIERPR
SCI Status Register
SCI Data Register
SCI Baud Rate Register
SCI Control Register 1
SCI Control Register 2
SCI Extended Receive Prescaler Register
Reserved area
SCI Extended Transmit Prescaler Register
C0h
xxh
00h
Read only
R/W
R/W
x000 0000b R/W
SCI
00h
00h
---
R/W
R/W
SCIETPR
00h
R/W
0058h
0059h
005Ah
005Bh
005Ch
005Dh
DMCR
DMSR
DMBK1H
DMBK1L
DMBK2H
DMBK2L
DM Control Register
DM Status Register
DM Breakpoint Register 1 High
DM Breakpoint Register 1 Low
DM Breakpoint Register 2 High
DM Breakpoint Register 2 Low
00h
00h
00h
00h
00h
00h
R/W
R/W
R/W
R/W
R/W
R/W
DM(3)
005Eh
to
Reserved Area (18 bytes)
006Fh
37/250
Register and memory map
ST72325xxx-Auto
Table 4.
Address
Hardware register map (continued)
Block
Register label
Register name
Reset status Remarks
0070h
0071h
0072h
ADCCSR
ADCDRH
ADCDRL
Control/Status Register
Data High Register
Data Low Register
00h
00h
00h
R/W
Read only
Read only
ADC
0073h
0074h
0075h
0076h
0077h
0078h
0079h
007Ah
007Bh
007Ch
007Dh
PWMDCR3
PWMDCR2
PWMDCR1
PWMDCR0
PWMCR
PWM AR Timer Duty Cycle Register 3
PWM AR Timer Duty Cycle Register 2
PWM AR Timer Duty Cycle Register 1
PWM AR Timer Duty Cycle Register 0
PWM AR Timer Control Register
Auto-Reload Timer Control/Status Register
Auto-Reload Timer Counter Access Register
Auto-Reload Timer Auto-Reload Register
AR Timer Input Capture Control/Status Reg.
AR Timer Input Capture Register 1
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PWM ART ARTCSR
ARTCAR
ARTARR
ARTICCSR
ARTICR1
R/W
Read only
Read only
ARTICR2
AR Timer Input Capture Register 1
007Eh
007Fh
Reserved area (2 bytes)
1. The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the
I/O pins are returned instead of the DR register contents.
2. The bits associated with unavailable pins must always keep their reset value.
3. For a description of the Debug Module registers, see the ST7 ICC Protocol Reference Manual.
Legend: x = undefined, R/W = read/write
38/250
ST72325xxx-Auto
Flash program memory
4
Flash program memory
4.1
Introduction
The ST7 dual voltage High Density Flash (HDFlash) is a non-volatile memory that can be
electrically erased as a single block or by individual sectors and programmed on a byte-by-
byte basis using an external V supply.
PP
The HDFlash devices can be programmed and erased off-board (plugged in a programming
tool) or on-board using ICP (in-circuit programming) or IAP (in-application programming).
The array matrix organization allows each sector to be erased and reprogrammed without
affecting other sectors.
4.2
Main features
●
3 Flash programming modes:
–
–
–
Insertion in a programming tool. In this mode, all sectors including option bytes
can be programmed or erased.
ICP (in-circuit programming). In this mode, all sectors including option bytes can
be programmed or erased without removing the device from the application board.
IAP (in-application programming). In this mode, all sectors except Sector 0 can be
programmed or erased without removing the device from the application board
and while the application is running.
●
ICT (in-circuit testing) for downloading and executing user application test patterns in
RAM
●
●
Readout protection
Register Access Security System (RASS) to prevent accidental programming or
erasing
4.3
Structure
The Flash memory is organized in sectors and can be used for both code and data storage.
Depending on the overall Flash memory size in the microcontroller device, there are up to
three user sectors (see Table 5). Each of these sectors can be erased independently to
avoid unnecessary erasing of the whole Flash memory when only a partial erasing is
required.
Table 5.
Sectors available in Flash devices
Flash size (bytes)
Available sectors
4K
8K
Sector 0
Sectors 0, 1
Sectors 0, 1, 2
> 8K
The first two sectors have a fixed size of 4 Kbytes (see Figure 6). They are mapped in the
upper part of the ST7 addressing space so the reset and interrupt vectors are located in
Sector 0 (F000h-FFFFh).
39/250
Flash program memory
ST72325xxx-Auto
Figure 6.
Memory map and sector address
4K
8K
10K
16K
24K
32K
48K
60K
FLASH
MEMORY SIZE
1000h
3FFFh
7FFFh
9FFFh
BFFFh
D7FFh
DFFFh
EFFFh
FFFFh
SECTOR 2
52 Kbytes
2 Kbytes
8 Kbytes 16 Kbytes 24 Kbytes 40 Kbytes
4 Kbytes
4 Kbytes
SECTOR 1
SECTOR 0
4.3.1
Readout protection
Readout protection, when selected, provides a protection against program memory content
extraction and against write access to Flash memory. Even if no protection can be
considered as totally unbreakable, the feature provides a very high level of protection for a
general purpose microcontroller.
In Flash devices, this protection is removed by reprogramming the option. In this case, the
entire program memory is first automatically erased and the device can be reprogrammed.
Note:
Readout protection selection is enabled and removed through the FMP_R bit in the option
byte.
4.4
ICC interface
ICC needs a minimum of 4 and up to 6 pins to be connected to the programming tool (see
Figure 7). These pins are:
RESET:
device reset
V
:
device power supply ground
ICC output serial clock pin
ICC input/output serial data pin
programming voltage
SS
ICCCLK:
ICCDATA:
ICCSEL/V
:
PP
OSC1 (or OSCIN):main clock input for external source (optional)
application board power supply (optional, see Figure 7, Note 3)
V
:
DD
40/250
ST72325xxx-Auto
Figure 7. Typical ICC interface
Flash program memory
PROGRAMMING TOOL
ICC CONNECTOR
ICC Cable
APPLICATION BOARD
ICC CONNECTOR
HE10 CONNECTOR TYPE
(See Note 3)
OPTIONAL
9
7
5
6
3
1
2
(See Note 4)
10
8
4
APPLICATION
RESET SOURCE
See Note 2
10kΩ
APPLICATION
POWER SUPPLY
CL2
CL1
See Note 1
APPLICATION
I/O
ST7
1. If the ICCCLK or ICCDATA pins are only used as outputs in the application, no signal isolation is necessary. As soon as the
programming tool is plugged to the board, even if an ICC session is not in progress, the ICCCLK and ICCDATA pins are
not available for the application. If they are used as inputs by the application, isolation such as a serial resistor has to
implemented in case another device forces the signal. Refer to the programming tool documentation for recommended
resistor values.
2. During the ICC session, the programming tool must control the RESET pin. This can lead to conflicts between the
programming tool and the application reset circuit if it drives more than 5mA at high level (push-pull output or pull-up
resistor < 1K). A schottky diode can be used to isolate the application RESET circuit in this case. When using a classical
RC network with R > 1K or a reset management IC with open-drain output and pull-up resistor > 1K, no additional
components are needed. In all cases the user must ensure that no external reset is generated by the application during the
ICC session.
3. The use of Pin 7 of the ICC connector depends on the programming tool architecture. This pin must be connected when
using most ST programming tools (it is used to monitor the application power supply). Please refer to the programming tool
manual.
4. Pin 9 has to be connected to the OSC1 or OSCIN pin of the ST7 when the clock is not available in the application or if the
selected clock option is not programmed in the option byte. ST7 devices with multi-oscillator capability need to have OSC2
grounded in this case.
4.5
ICP (in-circuit programming)
To perform ICP the microcontroller must be switched to ICC (in-circuit communication) mode
by an external controller or programming tool.
Depending on the ICP code downloaded in RAM, Flash memory programming can be fully
customized (number of bytes to program, program locations, or selection serial
communication interface for downloading).
When using an STMicroelectronics or third-party programming tool that supports ICP and
the specific microcontroller device, the user needs only to implement the ICP hardware
interface on the application board (see Figure 7). For more details on the pin locations, refer
to the device pinout description.
41/250
Flash program memory
ST72325xxx-Auto
4.6
IAP (in-application programming)
This mode uses a BootLoader program previously stored in Sector 0 by the user (in ICP
mode or by plugging the device in a programming tool).
This mode is fully controlled by user software. This allows it to be adapted to the user
application, (such as user-defined strategy for entering programming mode, choice of
communications protocol used to fetch the data to be stored). For example, it is possible to
download code from the serial peripheral or serial communication interface and program it in
the Flash. IAP mode can be used to program any of the Flash sectors except Sector 0,
which is write/erase protected to allow recovery in case errors occur during the
programming operation.
4.7
4.8
Related documentation
For details on Flash programming and ICC protocol, refer to the ST7 Flash Programming
Reference Manual and to the ST7 ICC Protocol Reference Manual.
Flash control/status register (FCSR)
FSCR
7
Reset value: 0000 0000 (00h)
6
0
5
0
4
0
3
0
2
0
1
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
This register is reserved for use by programming tool software. It controls the Flash
programming and erasing operations.
Table 6.
Flash control/status register address and reset value
Address (Hex.) Register label
7
6
5
4
3
2
1
0
FCSR
0029h
Reset value
0
0
0
0
0
0
0
0
42/250
ST72325xxx-Auto
Central processing unit (CPU)
5
Central processing unit (CPU)
5.1
Introduction
This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-
bit data manipulation.
5.2
Main features
●
●
●
●
●
●
●
●
Enable executing 63 basic instructions
Fast 8-bit by 8-bit multiply
17 main addressing modes (with indirect addressing mode)
Two 8-bit index registers
16-bit stack pointer
Low power Halt and Wait modes
Priority maskable hardware interrupts
Non-maskable software/hardware interrupts
5.3
CPU registers
The six CPU registers shown in Figure 8 are not present in the memory mapping and are
accessed by specific instructions.
Figure 8.
CPU registers
7
0
Accumulator
Reset value = XXh
7
0
0
X index register
Y index register
Reset value = XXh
7
Reset value = XXh
15
PCH
8 7
PCL
0
0
Program counter
Condition code register
Stack pointer
Reset value = reset vector @ FFFEh-FFFFh
7
1 1 I1 H I0 N Z C
Reset value =1 1 1 X 1 X X X
15
8 7
0
Reset value = stack higher address
X = undefined value
43/250
Central processing unit (CPU)
ST72325xxx-Auto
5.3.1
5.3.2
Accumulator (A)
The accumulator is an 8-bit general purpose register used to hold operands and the results
of the arithmetic and logic calculations as well as data manipulations.
Index registers (X and Y)
These 8-bit registers are used to create effective addresses or as temporary storage areas
for data manipulation (the Cross-Assembler generates a precede instruction (PRE) to
indicate that the following instruction refers to the Y register.)
The Y register is not affected by the interrupt automatic procedures.
5.3.3
5.3.4
Program counter (PC)
The program counter is a 16-bit register containing the address of the next instruction to be
executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is
the LSB) and PCH (Program Counter High which is the MSB).
Condition code (CC) register
The 8-bit condition code register contains the interrupt masks and four flags representative
of the result of the instruction just executed. This register can also be handled by the PUSH
and POP instructions.
These bits can be individually tested and/or controlled by specific instructions.
CC
Reset value: 111x1xxx
7
1
6
1
5
4
3
2
1
Z
0
I1
H
I0
N
C
RW
RW
RW
RW
RW
RW
Table 7.
Arithmetic management bits
Bit Name
Function
Half carry
This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU
during an ADD or ADC instructions. It is reset by hardware during the same
instructions.
0: No half carry has occurred.
1: A half carry has occurred.
H
N
4
2
This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD
arithmetic subroutines.
Negative
This bit is set and cleared by hardware. It is representative of the result sign of the
last arithmetic, logical or data manipulation. It is a copy of the result 7th bit.
0: The result of the last operation is positive or null.
1: The result of the last operation is negative (that is, the most significant bit is a logic
1).
This bit is accessed by the JRMI and JRPL instructions.
44/250
ST72325xxx-Auto
Central processing unit (CPU)
Table 7.
Bit Name
Arithmetic management bits (continued)
Function
Zero
This bit is set and cleared by hardware. This bit indicates that the result of the last
arithmetic, logical or data manipulation is zero.
0: The result of the last operation is different from zero.
1: The result of the last operation is zero.
1
Z
This bit is accessed by the JREQ and JRNE test instructions.
Carry/borrow
This bit is set and cleared by hardware and software. It indicates an overflow or an
underflow has occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
C
0
1: An overflow or underflow has occurred.
This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC
instructions. It is also affected by the “bit test and branch”, shift and rotate
instructions.
Table 8.
Interrupt management bits
Bit Name
Function
Interrupt Software Priority 1
The combination of the I1 and I0 bits gives the current interrupt software priority.
5
I1
I0
Interrupt Software Priority 0
The combination of the I1 and I0 bits gives the current interrupt software priority.
3
Table 9.
Interrupt software priority selection
Interrupt software priority
Level
I1
I0
Level 0 (main)
Level 1
1
0
0
1
0
1
0
1
Low
Level 2
High
Level 3 (= interrupt disable)
These two bits are set/cleared by hardware when entering in interrupt. The loaded value is
given by the corresponding bits in the interrupt software priority registers (ISPRx). They can
be also set/cleared by software with the RIM, SIM, IRET, HALT, WFI and PUSH/POP
instructions.
See Chapter 7: Interrupts on page 59 for more details.
5.3.5
Stack pointer (SP) register
7
SP
15
Reset value: 01 FFh
14
0
13
0
12
0
11
0
10
0
9
0
8
1
7
6
5
4
3
2
1
0
0
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
RW RW RW RW RW RW RW RW
45/250
Central processing unit (CPU)
ST72325xxx-Auto
The stack pointer is a 16-bit register which is always pointing to the next free location in the
stack. It is then decremented after data has been pushed onto the stack and incremented
before data is popped from the stack (see Figure 9).
Since the stack is 256 bytes deep, the 8 most significant bits are forced by hardware.
Following an MCU Reset, or after a reset stack pointer instruction (RSP), the stack pointer
contains its reset value (the SP7 to SP0 bits are set) which is the stack higher address.
The least significant byte of the stack pointer (called S) can be directly accessed by an LD
instruction.
Note:
When the lower limit is exceeded, the stack pointer wraps around to the stack upper limit,
without indicating the stack overflow. The previously stored information is then overwritten
and therefore lost. The stack also wraps in case of an underflow.
The stack is used to save the return address during a subroutine call and the CPU context
during an interrupt. The user may also directly manipulate the stack by means of the PUSH
and POP instructions. In the case of an interrupt, the PCL is stored at the first location
pointed to by the SP. The other registers are then stored in the next locations as shown in
Figure 9.
●
When an interrupt is received, the SP is decremented and the context is pushed on the
stack.
●
On return from interrupt, the SP is incremented and the context is popped from the
stack.
A subroutine call occupies two locations and an interrupt five locations in the stack area.
Figure 9. Stack manipulation example
CALL
Subroutine
RET
or RSP
PUSH Y
POP Y
IRET
Interrupt
Event
@ 0100h
SP
SP
SP
Y
CC
A
CC
A
CC
A
X
X
X
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
SP
SP
PCH
PCL
PCH
PCL
SP
@ 01FFh
Stack Higher Address = 01FFh
0100h
Stack Lower Address =
46/250
ST72325xxx-Auto
Supply, reset and clock management
6
Supply, reset and clock management
6.1
Introduction
The device includes a range of utility features for securing the application in critical
situations (for example in case of a power brown-out), and reducing the number of external
components. An overview is shown in Figure 10.
For more details, refer to the dedicated parametric section.
6.2
Main features
●
Optional PLL for multiplying the frequency by 2 (not to be used with internal RC
oscillator)
●
●
Reset Sequence Manager (RSM)
Multi-oscillator Clock Management (MO)
–
–
5 crystal/ceramic resonator oscillators
1 internal RC oscillator
●
System Integrity Management (SI)
–
–
Main supply low voltage detection (LVD)
Auxiliary voltage detector (AVD) with interrupt capability for monitoring the main
supply
–
Clock security system (CSS) with clock filter and backup safe oscillator (enabled
by option byte)
Figure 10. Clock, reset and supply block diagram
SYSTEM INTEGRITY MANAGEMENT
CLOCK SECURITY SYSTEM
(CSS)
MAIN CLOCK
CONTROLLER
WITH REALTIME
MULTI-
OSCILLATOR
(MO)
f
OSC2
OSC1
f
f
CPU
f
OSC2
OSC
CLOCK
FILTER
SAFE
OSC
OSC2
PLL
(option)
CLOCK (MCC/RTC)
RESET SEQUENCE
MANAGER
WATCHDOG
AVD Interrupt Request
RESET
TIMER (WDG)
SICSR
AVD
S
CSS
IE
AVD AVD
CSS WDG
LVD
RF
(RSM)
0
IE
F
D
RF
CSS Interrupt Request
LOW VOLTAGE
DETECTOR
(LVD)
V
V
SS
DD
0
1
AUXILIARY VOLTAGE
DETECTOR
(AVD)
EVD
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6.3
Phase locked loop
If the clock frequency input to the PLL is in the range 2 to 4 MHz, the PLL can be used to
multiply the frequency by two to obtain an f of 4 to 8 MHz. The PLL is enabled by option
OSC2
byte. If the PLL is disabled, then f
= f
/2.
OSC2
OSC
Caution:
The PLL is not recommended for applications where timing accuracy is required (see
Section 19.5.6: PLL characteristics on page 206).
Figure 11. PLL block diagram
PLL x 2
/ 2
0
fOSC
fOSC2
1
PLL OPTION BIT
6.4
Multi-oscillator (MO)
The main clock of the ST7 can be generated by three different source types coming from the
multi-oscillator block:
●
●
●
an external source
4 crystal or ceramic resonator oscillators
an internal high frequency RC oscillator
Each oscillator is optimized for a given frequency range in terms of consumption and is
selectable through the option byte. The associated hardware configurations are shown in
Table 10. Refer to Chapter 19: Electrical characteristics for more details.
External clock source
In this external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle
has to drive the OSC1 pin while the OSC2 pin is tied to ground.
Crystal/ceramic oscillators
This family of oscillators has the advantage of producing a very accurate rate on the main
clock of the ST7. The selection within a list of four oscillators with different frequency ranges
has to be done by option byte in order to reduce consumption (refer to Section 21.1.1: Flash
configuration on page 233 for more details on the frequency ranges). In this mode of the
multi-oscillator, the resonator and the load capacitors have to be placed as close as possible
to the oscillator pins in order to minimize output distortion and start-up stabilization time.
The loading capacitance values must be adjusted according to the selected oscillator.
These oscillators are not stopped during the RESET phase to avoid losing time in the
oscillator start-up phase.
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ST72325xxx-Auto
Supply, reset and clock management
Internal RC oscillator
This oscillator allows a low cost solution for the main clock of the ST7 using only an internal
resistor and capacitor. Internal RC oscillator mode has the drawback of a lower frequency
accuracy and should not be used in applications that require accurate timing.
In this mode, the two oscillator pins have to be tied to ground.
Table 10. ST7 clock sources
Hardware configuration
ST7
OSC1
OSC2
EXTERNAL
SOURCE
ST7
OSC1
OSC2
C
C
L2
L1
LOAD
CAPACITORS
ST7
OSC1
OSC2
6.5
Reset sequence manager (RSM)
6.5.1
Introduction
The reset sequence manager includes three RESET sources as shown in Figure 12:
●
●
●
External RESET source pulse
Internal LVD RESET (low voltage detection)
Internal WATCHDOG RESET
These sources act on the RESET pin and it is always kept low during the delay phase.
The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory
map.
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ST72325xxx-Auto
The basic RESET sequence consists of three phases as shown in Figure 13:
●
●
●
Active phase depending on the RESET source
256 or 4096 CPU clock cycle delay (selected by option byte)
RESET vector fetch
Caution:
When the ST7 is unprogrammed or fully erased, the Flash is blank and the RESET vector is
not programmed. For this reason, it is recommended to keep the RESET pin in low state
until programming mode is entered, in order to avoid unwanted behavior.
The 256 or 4096 CPU clock cycle delay allows the oscillator to stabilize and ensures that
recovery has taken place from the Reset state. The shorter or longer clock cycle delay
should be selected by option byte to correspond to the stabilization time of the external
oscillator used in the application (see Section 21.1.1: Flash configuration on page 233).
The RESET vector fetch phase duration is 2 clock cycles.
Figure 12. Reset block diagram
V
DD
R
ON
INTERNAL
RESET
Filter
RESET
PULSE
GENERATOR
WATCHDOG RESET
LVD RESET
Figure 13. RESET sequence phases
RESET
INTERNAL RESET
FETCH
VECTOR
ACTIVE PHASE
256 or 4096 CLOCK CYCLES
6.5.2
Asynchronous external RESET pin
The RESET pin is both an input and an open-drain output with integrated R weak pull-up
ON
resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It
can be pulled low by external circuitry to reset the device. See Section 19.9: Control pin
characteristics on page 215 for more details.
A RESET signal originating from an external source must have a duration of at least
t
in order to be recognized (see Figure 14). This detection is asynchronous and
h(RSTL)in
therefore the MCU can enter reset state even in Halt mode.
50/250
ST72325xxx-Auto
Supply, reset and clock management
The RESET pin is an asynchronous signal which plays a major role in EMS performance. In
a noisy environment, it is recommended to follow the guidelines mentioned in Chapter 19:
Electrical characteristics.
If the external RESET pulse is shorter than t
(see short ext. Reset in Figure 14),
w(RSTL)out
the signal on the RESET pin may be stretched. Otherwise the delay will not be applied (see
long ext. Reset in Figure 14). Starting from the external RESET pulse recognition, the
device RESET pin acts as an output that is pulled low during at least t
.
w(RSTL)out
6.5.3
6.5.4
External power-on RESET
If the LVD is disabled by option byte, to start up the microcontroller correctly, the user must
ensure by means of an external reset circuit that the reset signal is held low until V is over
the minimum level specified for the selected f
DD
frequency (see Section 19.3: Operating
OSC
conditions on page 197).
A proper reset signal for a slow rising V supply can generally be provided by an external
RC network connected to the RESET pin.
DD
Internal low voltage detector (LVD) RESET
Two different RESET sequences caused by the internal LVD circuitry can be distinguished:
●
Power-on RESET
●
Voltage drop RESET
The device RESET pin acts as an output that is pulled low when V < V (rising edge) or
DD
IT+
V
< V (falling edge) as shown in Figure 14.
DD
IT-
The LVD filters spikes on V larger than t
to avoid parasitic resets.
g(VDD)
DD
6.5.5
Internal watchdog RESET
The RESET sequence generated by an internal Watchdog counter overflow is shown in
Figure 14.
Starting from the Watchdog counter underflow, the device RESET pin acts as an output that
is pulled low during at least t
.
w(RSTL)out
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Supply, reset and clock management
ST72325xxx-Auto
Figure 14. RESET sequences
VDD
VIT+(LVD)
VIT-(LVD)
LVD
RESET
SHORT EXT.
RESET
LONG EXT.
RESET
WATCHDOG
RESET
RUN
RUN
RUN
RUN
RUN
Active
Phase
Active
Phase
Active
Phase
Active Phase
t
t
w(RSTL)out
w(RSTL)out
t
h(RSTL)in
t
w(RSTL)out
t
h(RSTL)in
DELAY
EXTERNAL
RESET
SOURCE
RESET PIN
WATCHDOG
RESET
WATCHDOG UNDERFLOW
INTERNAL RESET (256 or 4096 T
VECTOR FETCH
)
CPU
6.6
System integrity management (SI)
The System Integrity Management block contains the Low Voltage Detector (LVD) and
Auxiliary Voltage Detector (AVD) functions and Clock Security System (CSS). It is managed
by the SICSR register.
6.6.1
Low voltage detector (LVD)
The low voltage detector function (LVD) generates a static reset when the V supply
DD
voltage is below a V reference value. This means that it secures the power-up as well as
IT-
the power-down keeping the ST7 in reset.
The V reference value for a voltage drop is lower than the V reference value for power-
IT-
IT+
on in order to avoid a parasitic reset when the MCU starts running and sinks current on the
supply (hysteresis).
The LVD reset circuitry generates a reset when V is below:
DD
–
–
V
V
when V is rising
DD
IT+
IT-
when V is falling
DD
The LVD function is illustrated in Figure 15.
The voltage threshold can be configured by option byte to be low, medium or high.
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ST72325xxx-Auto
Supply, reset and clock management
Provided the minimum V value (guaranteed for the oscillator frequency) is above V , the
DD
IT-
MCU can only be in two modes:
–
–
under full software control
in static safe reset
In these conditions, secure operation is always ensured for the application without the need
for external reset hardware.
During a low voltage detector reset, the RESET pin is held low, thus permitting the MCU to
reset other devices.
Note:
The LVD allows the device to be used without any external RESET circuitry.
If the medium or low thresholds are selected, the detection may occur outside the specified
operating voltage range. Below 3.8V, device operation is not guaranteed.
The LVD is an optional function which can be selected by option byte.
It is recommended to make sure that the V supply voltage rises monotonously when the
DD
device is exiting from Reset, to ensure the application functions properly.
Figure 15. Low voltage detector versus reset
V
DD
V
hys
V
IT+
V
IT-
RESET
6.6.2
Auxiliary voltage detector (AVD)
The auxiliary voltage detector function (AVD) is based on an analog comparison between a
and V reference value and the V main supply or the external EVD pin
V
IT-(AVD)
IT+(AVD)
DD
voltage level (V
). The V reference value for falling voltage is lower than the V
EVD
IT- IT+
reference value for rising voltage in order to avoid parasitic detection (hysteresis).
The output of the AVD comparator can be read directly by the application software through a
real-time status bit (AVDF) in the SICSR register. This bit is read only.
Caution:
The AVD function is active only if the LVD is enabled through the option byte.
Monitoring the VDD main supply
This mode is selected by clearing the AVDS bit in the SICSR register.
The AVD voltage threshold value is relative to the selected LVD threshold configured by
option byte (see Section 21.1.1: Flash configuration on page 233).
If the AVD interrupt is enabled, an interrupt is generated when the voltage crosses the
V
or V
threshold (AVDF bit toggles).
IT+(AVD)
IT-(AVD)
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ST72325xxx-Auto
In the case of a drop in voltage, the AVD interrupt acts as an early warning, allowing
software to shut down safely before the LVD resets the microcontroller. See Figure 16.
The interrupt on the rising edge is used to inform the application that the V warning state
DD
is over.
If the voltage rise time t is less than 256 or 4096 CPU cycles (depending on the reset delay
rv
selected by option byte), no AVD interrupt will be generated when V
is reached.
IT+(AVD)
If t is greater than 256 or 4096 cycles
rv
●
●
two AVD interrupts will be received if the AVD interrupt is enabled before the V
IT+(AVD)
threshold is reached: the first when the AVDIE bit is set, and the second when the
threshold is reached.
only one AVD interrupt will occur if the AVD interrupt is enabled after the V
IT+(AVD)
threshold is reached.
Figure 16. Using the AVD to monitor V (AVDS bit = 0)
DD
VDD
Early Warning Interrupt
(Power has dropped, MCU not
not yet in reset)
Vhyst
VIT+(AVD)
VIT-(AVD)
VIT+(LVD)
VIT-(LVD)
trv
VOLTAGE RISE TIME
1
1
AVDF bit
0
RESET VALUE
0
AVD INTERRUPT
REQUEST
IF AVDIE bit = 1
INTERRUPT PROCESS
INTERRUPT PROCESS
LVD RESET
Monitoring a voltage on the EVD pin
This mode is selected by setting the AVDS bit in the SICSR register.
The AVD circuitry can generate an interrupt when the AVDIE bit of the SICSR register is set.
This interrupt is generated on the rising and falling edges of the comparator output. This
means it is generated when either one of these two events occur:
●
V
V
rises up to V
IT+(EVD)
EVD
EVD
●
falls down to V
IT-(EVD)
The EVD function is illustrated in Figure 17.
For more details, refer to Chapter 19: Electrical characteristics.
54/250
ST72325xxx-Auto
Supply, reset and clock management
Figure 17. Using the voltage detector to monitor the EVD pin (AVDS bit = 1)
VEVD
Vhyst
VIT+(EVD)
VIT-(EVD)
AVDF
0
1
0
AVD INTERRUPT
REQUEST
IF AVDIE = 1
INTERRUPT PROCESS
INTERRUPT PROCESS
6.6.3
Clock security system (CSS)
The Clock Security System (CSS) protects the ST7 against breakdowns, spikes and
overfrequencies occurring on the main clock source (f ). It is based on a clock filter and a
OSC
clock detection control with an internal safe oscillator (f
).
SFOSC
Clock filter control
The PLL has an integrated glitch filtering capability making it possible to protect the internal
clock from overfrequencies created by individual spikes. This feature is available only when
the PLL is enabled. If glitches occur on f
(for example, due to loose connection or noise),
OSC
the CSS filters these automatically, so the internal CPU frequency (f
) continues
CPU
delivering a glitch-free signal (see Figure 18).
Clock detection control
If the clock signal disappears (due to a broken or disconnected resonator...), the safe
oscillator delivers a low frequency clock signal (f
some rescue operations.
) which allows the ST7 to perform
SFOSC
Automatically, the ST7 clock source switches back from the safe oscillator (f
) if the
SFOSC
main clock source (f
) recovers.
OSC
When the internal clock (f
) is driven by the safe oscillator (f
), the application
CPU
SFOSC
software is notified by hardware setting the CSSD bit in the SICSR register. An interrupt can
be generated if the CSSIE bit has been previously set. These two bits are described in the
SICSR register description.
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ST72325xxx-Auto
6.6.4
Low power modes
Table 11. Effect of low power modes on SI
Mode
Effect
Wait
No effect on SI. CSS and AVD interrupts cause the device to exit from Wait mode.
The SICSR register is frozen.The CSS (including the safe oscillator) is disabled until
HALT mode is exited. The previous CSS configuration resumes when the MCU is woken
up by an interrupt with “exit from HALT mode” capability or from the counter reset value
when the MCU is woken up by a RESET.
Halt
6.6.5
Interrupts
The CSS or AVD interrupt eventsgenerate an interrupt if the corresponding Enable Control
Bit (CSSIE or AVDIE) is set and the interrupt mask in the CC register is reset (RIM
instruction).
Table 12. CSS AVD interrupt control/wake-up capability
Interrupt event
Event flag
Enable control bit
Exit from Wait
Exit from Halt
CSS event
detection (safe
oscillator
activated as main
clock)
CSSD
AVDF
CSSIE
AVDIE
Yes
Yes
No
No
AVD event
Figure 18. Clock filter function
Clock Filter Function
f
f
OSC2
CPU
Clock Detection Function
f
f
OSC2
SFOSC
f
CPU
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ST72325xxx-Auto
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6.6.6
System Integrity (SI) Control/Status register (SICSR)
SICSR
7
Reset value: 000x 000x (00h)
6
5
4
3
2
1
0
AVDS
RW
AVDIE
AVDF
LVDRF
WDGRF
Reserved
-
RW
RW
RW
RW
Table 13. SICSR description
Bit
Name
Function
Voltage Detection selection
This bit is set and cleared by software. Voltage Detection is available only if the
LVD is enabled by option byte.
7
AVDS
0: Voltage detection on VDD supply
1: Voltage detection on EVD pin
Voltage Detector interrupt enable
This bit is set and cleared by software. It enables an interrupt to be generated
when the AVDF flag changes (toggles). The pending interrupt information is
automatically cleared when software enters the AVD interrupt routine.
0: AVD interrupt disabled
6
5
AVDIE
AVDF
1: AVD interrupt enabled
Voltage Detector flag
This read-only bit is set and cleared by hardware. If the AVDIE bit is set, an
interrupt request is generated when the AVDF bit changes value. Refer to
Figure 16 and to Monitoring the VDD main supply on page 53 for additional
details.
0: VDD or VEVD over VIT+(AVD) threshold
1: VDD or VEVD under VIT-(AVD) threshold
LVD reset flag
This bit indicates that the last Reset was generated by the LVD block. It is set by
hardware (LVD reset) and cleared by software (writing zero). See Table 14: Reset
source flags for more details. When the LVD is disabled by OPTION BYTE, the
LVDRF bit value is undefined.
4
3
LVDRF
-
Reserved, must be kept cleared.
Clock security system interrupt enable
This bit enables the interrupt when a disturbance is detected by the Clock Security
System (CSSD bit set). It is set and cleared by software.
0: Clock security system interrupt disabled
2
CSSIE
1: Clock security system interrupt enabled
When the CSS is disabled by OPTION BYTE, the CSSIE bit has no effect.
Clock security system detection
This bit indicates that the safe oscillator of the Clock Security System block has
been selected by hardware due to a disturbance on the main clock signal (fOSC). It
is set by hardware and cleared by reading the SICSR register when the original
oscillator recovers.
1
CSSD
0: Safe oscillator is not active
1: Safe oscillator has been activated
When the CSS is disabled by OPTION BYTE, the CSSD bit value is forced to 0.
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Supply, reset and clock management
Table 13. SICSR description (continued)
ST72325xxx-Auto
Bit
Name
Function
Watchdog reset flag
This bit indicates that the last Reset was generated by the Watchdog peripheral. It
is set by hardware (watchdog reset) and cleared by software (writing zero) or an
LVD Reset (to ensure a stable cleared state of the WDGRF flag when CPU starts).
Combined with the LVDRF flag information, the flag description is given in
Table 14.
0
WDGRF
Table 14. Reset source flags
Reset sources
LVDRF
WDGRF
External RESET pin
Watchdog
0
0
1
0
1
LVD
X
Application notes
The LVDRF flag is not cleared when another RESET type occurs (external or watchdog); the
LVDRF flag remains set to keep trace of the original failure.
In this case, software can detect a watchdog reset but cannot detect an external reset.
Caution:
When the LVD is not activated with the associated option byte, the WDGRF flag cannot be
used in the application.
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ST72325xxx-Auto
Interrupts
7
Interrupts
7.1
Introduction
The ST7 enhanced interrupt management provides the following features:
●
●
●
Hardware interrupts
Software interrupt (TRAP)
Nested or concurrent interrupt management with flexible interrupt priority and level
management:
–
–
–
–
Up to 4 software programmable nesting levels
Up to 16 interrupt vectors fixed by hardware
2 non-maskable events: RESET, TRAP
1 maskable Top Level event: TLI
This interrupt management is based on:
●
●
●
Bit 5 and bit 3 of the CPU CC register (I1:0)
Interrupt software priority registers (ISPRx)
Fixed interrupt vector addresses located at the high addresses of the memory map
(FFE0h to FFFFh) sorted by hardware priority order
This enhanced interrupt controller guarantees full upward compatibility with the standard
(not nested) ST7 interrupt controller.
7.2
Masking and processing flow
The interrupt masking is managed by the I1 and I0 bits of the CC register and the ISPRx
registers which give the interrupt software priority level of each interrupt vector (see Table
15). The processing flow is shown in Figure 19.
When an interrupt request has to be serviced:
●
●
●
Normal processing is suspended at the end of the current instruction execution.
The PC, X, A and CC registers are saved onto the stack.
I1 and I0 bits of CC register are set according to the corresponding values in the ISPRx
registers of the serviced interrupt vector.
●
The PC is then loaded with the interrupt vector of the interrupt to service and the first
instruction of the interrupt service routine is fetched (refer to Table 20: Interrupt
mapping for vector addresses).
The interrupt service routine should end with the IRET instruction which causes the
contents of the saved registers to be recovered from the stack.
Note:
As a consequence of the IRET instruction, the I1 and I0 bits will be restored from the stack
and the program in the previous level will resume.
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Interrupts
ST72325xxx-Auto
I0
Table 15. Interrupt software priority levels
Interrupt software priority
Level
I1
Level 0 (main)
Level 1
1
0
0
1
0
1
0
1
Low
Level 2
High
Level 3 (= interrupt disable)
Figure 19. Interrupt processing flowchart
PENDING
INTERRUPT
Y
Y
RESET
TRAP
N
Interrupt has the same or a
lower software priority
than current one
N
I1:0
FETCH NEXT
INSTRUCTION
THE INTERRUPT
STAYS PENDING
Y
“IRET”
N
RESTORE PC, X, A, CC
FROM STACK
EXECUTE
INSTRUCTION
STACK PC, X, A, CC
LOAD I1:0 FROM INTERRUPT SW REG.
LOAD PC FROM INTERRUPT VECTOR
Servicing pending interrupts
As several interrupts can be pending at the same time, the interrupt to be taken into account
is determined by the following two-step process:
●
the highest software priority interrupt is serviced,
●
if several interrupts have the same software priority then the interrupt with the highest
hardware priority is serviced first.
Figure 20 describes this decision process.
Figure 20. Priority decision process flowchart
PENDING
INTERRUPTS
Different
Same
SOFTWARE
PRIORITY
HIGHEST SOFTWARE
PRIORITY SERVICED
HIGHEST HARDWARE
PRIORITY SERVICED
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ST72325xxx-Auto
Interrupts
When an interrupt request is not serviced immediately, it is latched and then processed
when its software priority combined with the hardware priority becomes the highest one.
Note:
1
2
The hardware priority is exclusive while the software one is not. This allows the previous
process to succeed with only one interrupt.
TLI, RESET and TRAP can be considered as having the highest software priority in the
decision process.
Different interrupt vector sources
Two interrupt source types are managed by the ST7 interrupt controller: the non-maskable
type (RESET, TRAP) and the maskable type (external or from internal peripherals).
Non-maskable sources
These sources are processed regardless of the state of the I1 and I0 bits of the CC register
(see Figure 19). After stacking the PC, X, A and CC registers (except for RESET), the
corresponding vector is loaded in the PC register and the I1 and I0 bits of the CC are set to
disable interrupts (level 3). These sources allow the processor to exit Halt mode.
●
TRAP (non-maskable software interrupt)
This software interrupt is serviced when the TRAP instruction is executed. It will be
serviced according to the flowchart in Figure 19.
Caution:
TRAP can be interrupted by a TLI.
●
RESET
The RESET source has the highest priority in the ST7. This means that the first current
routine has the highest software priority (level 3) and the highest hardware priority.
See Section 6.5: Reset sequence manager (RSM) for more details.
Maskable sources
Maskable interrupt vector sources can be serviced if the corresponding interrupt is enabled
and if its own interrupt software priority (in ISPRx registers) is higher than the one currently
being serviced (I1 and I0 in CC register). If any of these two conditions is false, the interrupt
is latched and thus remains pending.
●
TLI (top level hardware interrupt)
Caution:
This hardware interrupt occurs when a specific edge is detected on the dedicated TLI pin. It
will be serviced according to the flowchart in Figure 19 as a trap.
A TRAP instruction must not be used in a TLI service routine.
●
External Interrupts
External interrupts allow the processor to exit from HALT low power mode. External
interrupt sensitivity is software selectable through the External Interrupt Control register
(EICR).
External interrupt triggered on edge will be latched and the interrupt request
automatically cleared upon entering the interrupt service routine.
If several input pins of a group connected to the same interrupt line are selected
simultaneously, these will be logically ORed.
●
Peripheral Interrupts
Usually the peripheral interrupts cause the MCU to exit from Halt mode except those
mentioned in Table 20: Interrupt mapping. A peripheral interrupt occurs when a specific
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Interrupts
ST72325xxx-Auto
flag is set in the peripheral status registers and if the corresponding enable bit is set in
the peripheral control register.
The general sequence for clearing an interrupt is based on an access to the status
register followed by a read or write to an associated register.
Note:
The clearing sequence resets the internal latch. A pending interrupt (that is, waiting to be
serviced) will therefore be lost if the clear sequence is executed.
7.3
Interrupts and low power modes
All interrupts allow the processor to exit the Wait low power mode. On the contrary, only
external and other specified interrupts allow the processor to exit from the Halt modes (see
column “Exit from Halt/Active Halt” in Table 20: Interrupt mapping). When several pending
interrupts are present while exiting Halt mode, the first one serviced can only be an interrupt
with “exit from Halt mode” capability and it is selected through the same decision process
shown in Figure 20.
Note:
If an interrupt that is not able to exit from Halt mode is pending with the highest priority when
exiting Halt mode, this interrupt is serviced after the first one serviced.
7.4
Concurrent and nested management
The following Figure 21 and Figure 22 show two different interrupt management modes. The
first is called concurrent mode and does not allow an interrupt to be interrupted, unlike the
nested mode in Figure 22. The interrupt hardware priority is given in this order from the
lowest to the highest: MAIN, IT4, IT3, IT2, IT1, IT0, TLI. The software priority is given for
each interrupt.
Warning: A stack overflow may occur without notifying the software of
the failure.
Figure 21. Concurrent interrupt management
SOFTWARE
PRIORITY
LEVEL
I1
I0
TRAP
3
1
1
1
1
1
1
1
1
1
1
1
1
IT0
3
IT1
IT1
3
IT2
3
IT3
3
RIM
IT4
3
MAIN
MAIN
10
3/0
11 / 10
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Figure 22. Nested interrupt management
SOFTWARE
PRIORITY
LEVEL
I1
I0
TRAP
3
1
1
0
0
1
1
1
1
0
1
1
1
IT0
3
IT1
IT1
IT2
2
IT2
1
IT3
3
RIM
IT4
IT4
3
MAIN
MAIN
10
3/0
11 / 10
7.5
Interrupt register description
CPU CC register interrupt bits
CPU CC
7.5.1
Reset value: 111x 1010 (xAh)
7
1
6
1
5
4
3
2
1
Z
0
I1
H
I0
N
C
RW
RW
RW
RW
RW
RW
Table 16. CPU CC register interrupt bits description
Bit
Name
Function
Interrupt Software Priority 1
Interrupt Software Priority 0
5
3
I1
I0
These two bits indicate the current interrupt software priority (see Table 17) and are
set/cleared by hardware when entering in interrupt. The loaded value is given by the
corresponding bits in the interrupt software priority registers (ISPRx).
They can be also set/cleared by software with the RIM, SIM, HALT, WFI, IRET and
PUSH/POP instructions (see Table 19: Interrupt dedicated instruction set).
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I0
Table 17. Interrupt software priority levels
Interrupt software priority
Level
I1
Level 0 (main)
Level 1
1
0
0
1
0
1
0
1
Low
Level 2
Level 3 (= interrupt disable(1)
)
High
1. TRAP and RESET events can interrupt a level 3 program.
7.5.2
Interrupt software priority registers (ISPRx)
These four registers are read/write, with the exception of bits 7:4 of ISPR3, which are read
only.
ISPRx
Reset value: 1111 1111 (FFh)
7
6
5
4
3
2
1
0
ISPR0
I1_3
I0_3
I1_2
I0_2
I1_1
I0_1
I1_0
I0_0
ISPR1
ISPR2
ISPR3
I1_7
I1_11
1
I0_7
I0_11
1
I1_6
I1_10
1
I0_6
I0_10
1
I1_5
I1_9
I0_5
I0_9
I1_4
I1_8
I0_4
I0_8
I1_13
I0_13
I1_12
I0_12
These four registers contain the interrupt software priority of each interrupt vector.
Each interrupt vector (except RESET and TRAP) has corresponding bits in these
●
registers where its own software priority is stored. This correspondence is shown in the
following Table 18.
Table 18. Interrupt priority bits
Vector address
ISPRx bits
FFFBh-FFFAh
FFF9h-FFF8h
...
I1_0 and I0_0 bits(1)
I1_1 and I0_1 bits
...
FFE1h-FFE0h
I1_13 and I0_13 bits
1. Bits in the ISPRx registers which correspond to the TLI can be read and written but they are not significant
in the interrupt process management.
●
Each I1_x and I0_x bit value in the ISPRx registers has the same meaning as the I1
and I0 bits in the CC register.
●
Level 0 cannot be written (I1_x = 1, I0_x = 0). In this case, the previously stored value
is kept (Example: previous = CFh, write = 64h, result = 44h).
The TLI, RESET, and TRAP vectors have no software priorities. When one is serviced, the
I1 and I0 bits of the CC register are both set.
Caution:
If the I1_x and I0_x bits are modified while the interrupt x is executed the following behavior
has to be considered: If the interrupt x is still pending (new interrupt or flag not cleared) and
the new software priority is higher than the previous one, the interrupt x is re-entered.
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Interrupts
Otherwise, the software priority stays unchanged up to the next interrupt request (after the
IRET of the interrupt x).
Table 19. Interrupt dedicated instruction set
Instruction
New description
Function/Example
I1
H
I0
N
Z
C
HALT
IRET
JRM
Entering Halt mode
Interrupt routine return
Jump if I1:0 = 11 (level 3)
Jump if I1:0 <> 11
1
0
Pop CC, A, X, PC
I1:0 = 11 ?
I1
H
I0
N
Z
C
JRNM
I1:0 <> 11 ?
Mem => CC
POP CC Pop CC from the Stack
I1
1
1
1
1
H
I0
0
N
Z
C
RIM
SIM
Enable interrupt (level 0 set) Load 10 in I1:0 of CC
Disable interrupt (level 3 set) Load 11 in I1:0 of CC
1
TRAP
WFI
Software trap
Software NMI
1
Wait for interrupt
0
Note:
During the execution of an interrupt routine, the HALT, POPCC, RIM, SIM and WFI
instructions change the current software priority up to the next IRET instruction or one of the
previously mentioned instructions.
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Table 20. Interrupt mapping
Exit
from
Halt /
Active
Halt
Source
No.
Register Priority
Address
vector
Description
block
label
order
RESET
TRAP
TLI
Reset
yes
no
FFFEh-FFFFh
FFFCh-FFFDh
FFFAh-FFFBh
N/A
Software interrupt
0
1
External top level interrupt
EICR
yes
MCC/RTC Main clock controller time base interrupt
MCCSRSI
CSR
yes
FFF8h-FFF9h
Higher
priority
CSS
Safe oscillator activation interrupt
External interrupt port A3..0
External interrupt port F2..0
External interrupt port B3..0
External interrupt port B7..4
Not used
2
3
ei0
yes
yes
yes
yes
FFF6h-FFF7h
FFF4h-FFF5h
FFF2h-FFF3h
FFF0h-FFF1h
FFEEh-FFEFh
FFECh-FFEDh
FFEAh-FFEBh
FFE8h-FFE9h
FFE6h-FFE7h
FFE4h-FFE5h
ei1
N/A
4
ei2
5
ei3
6
7
SPI
SPI peripheral interrupts
SPICSR
TASR
yes(1)
no
8
TIMER A TIMER A peripheral interrupts
TIMER B TIMER B peripheral interrupts
9
TBSR
no
10
11
SCI
SCI peripheral interrupts
SCISR
SICSR
no
Lower
priority
AVD
Auxiliary voltage detector interrupt
no
(see
peripheral)
12
I2C
I2C peripheral interrupts
no
FFE2h-FFE3h
FFE0h-FFE1h
13 PWM ART PWM ART interrupt
ARTCSR
yes(2)
1. Exit from HALT possible when SPI is in slave mode.
2. Exit from HALT possible when PWM ART is in external clock mode.
7.6
External interrupts
7.6.1
I/O port interrupt sensitivity
The external interrupt sensitivity is controlled by the IPA, IPB and ISxx bits of the EICR
register (Figure 23). This control allows to have up to four fully independent external
interrupt source sensitivities.
Each external interrupt source can be generated on four (or five) different events on the pin:
●
●
●
●
●
Falling edge
Rising edge
Falling and rising edge
Falling edge and low level
Rising edge and high level (only for ei0 and ei2)
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To guarantee correct functionality, the sensitivity bits in the EICR register can be modified
only when the I1 and I0 bits of the CC register are both set to 1 (level 3). This means that
interrupts must be disabled before changing sensitivity.
The pending interrupts are cleared by writing a different value in the ISx[1:0], IPA or IPB bits
of the EICR.
Figure 23. External interrupt control bits
EICR
IS20 IS21
PORT A3 INTERRUPT
PAOR.3
PADDR.3
ei0 INTERRUPT SOURCE
SENSITIVITY
CONTROL
PA3
IPA BIT
EICR
PORT F [2:0] INTERRUPTS
IS20
IS21
PFOR.2
PFDDR.2
SENSITIVITY
CONTROL
PF2
PF1
PF0
ei1 INTERRUPT SOURCE
PF2
EICR
PORT B [3:0] INTERRUPTS
IS10
IS11
PBOR.3
PBDDR.3
SENSITIVITY
CONTROL
PB3
PB2
PB1
PB0
PB3
ei2 INTERRUPT SOURCE
IPB BIT
EICR
PORT B4 INTERRUPT
IS10
IS11
PBOR.4
PBDDR.4
SENSITIVITY
CONTROL
ei3 INTERRUPT SOURCE
PB4
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7.6.2
External interrupt control register (EICR)
EICR
Reset value: 0000 0000 (00h)
7
6
5
4
3
2
1
0
IS1[1:0]
RW
IPB
IS2[1:0]
RW
IPA
TLIS
TLIE
RW
RW
RW
RW
Table 21. EICR register description
Bit Name
Function
ei2 and ei3 sensitivity
The interrupt sensitivity, defined using the IS1[1:0] bits, is applied to the following
external interrupts:
- ei2 (port B3..0) (see Table 22)
7:6 IS1[1:0]
- ei3 (port B4) (see Table 23)
These 2 bits can be written only when I1 and I0 of the CC register are both set to 1
(level 3).
Interrupt polarity for port B
This bit is used to invert the sensitivity of the port B [3:0] external interrupts. It can
be set and cleared by software only when I1 and I0 of the CC register are both set
to 1 (level 3).
5
IPB
0: No sensitivity inversion
1: Sensitivity inversion
ei0 and ei1 sensitivity
The interrupt sensitivity, defined using the IS2[1:0] bits, is applied to the following
external interrupts:
4:3 IS2[1:0]
- ei0 (port A3) (see Table 24)
- ei1 (port F2..0) (see Table 25)
These 2 bits can be written only when I1 and I0 of the CC register are both set to 1
(level 3).
Interrupt polarity for port A
This bit is used to invert the sensitivity of the port A [3:0] external interrupts. It can
be set and cleared by software only when I1 and I0 of the CC register are both set
to 1 (level 3).
0: No sensitivity inversion
1: Sensitivity inversion
2
1
0
IPA
TLI sensitivity
This bit allows to toggle the TLI edge sensitivity. It can be set and cleared by
software only when TLIE bit is cleared.
0: Falling edge
TLIS
TLIE
1: Rising edge
TLI enable
This bit allows to enable or disable the TLI capability on the dedicated pin. It is set
and cleared by software.
0: TLI disabled
1: TLI enabled
Note: A parasitic interrupt can be generated when clearing the TLIE bit.
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Table 22. Interrupt sensitivity - ei2 (port B3..0)
External interrupt sensitivity
IS11
IS10
IPB bit = 0
IPB bit = 1
0
0
1
1
0
1
0
1
Falling edge and low level
Rising edge only
Rising edge and high level
Falling edge only
Falling edge only
Rising edge only
Rising and falling edge
Table 23. Interrupt sensitivity - ei3 (port B4)
IS11
IS10
External interrupt sensitivity
0
0
1
1
0
1
0
1
Falling edge and low level
Rising edge only
Falling edge only
Rising and falling edge
Table 24. Interrupt sensitivity - ei0 (port A3)
External interrupt sensitivity
IS21
IS20
IPA bit = 0
IPA bit = 1
0
0
1
1
0
1
0
1
Falling edge and low level
Rising edge only
Rising edge and high level
Falling edge only
Falling edge only
Rising edge only
Rising and falling edge
Table 25. Interrupt sensitivity - ei1 (port F2..0)
IS21
IS20
External interrupt sensitivity
0
0
1
1
0
1
0
1
Falling edge and low level
Rising edge only
Falling edge only
Rising and falling edge
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Table 26. Nested interrupts register map and reset values
Address (Hex.) Register label
7
6
5
4
3
2
1
0
ei1
SPI
AVD
ei0
MCC + SI
TLI
ei2
0024h
0025h
0026h
ISPR0
Reset value
I1_3
1
I0_3
1
I1_2
1
I0_2
1
I1_1
1
I0_1
1
1
1
ei3
ISPR1
Reset value
I1_7
1
I0_7
1
I1_6
1
I0_6
1
I1_5
1
I0_5
1
I1_4
1
I0_4
1
SCI
TIMER B
TIMER A
ISPR2
Reset value
I1_11
1
I0_11
1
I1_10
1
I0_10
1
I1_9
1
I0_9
1
I1_8
1
I0_8
1
PWMART
I2C
0027h
0028h
ISPR3
Reset value
I1_13
1
I0_13
1
I1_12
1
I0_12
1
1
1
1
1
EICR
Reset value
IS11
0
IS10
0
IPB
0
IS21
0
IS20
0
IPA
0
TLIS
0
TLIE
0
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Power saving modes
8
Power saving modes
8.1
Introduction
To give a large measure of flexibility to the application in terms of power consumption, four
main power saving modes are implemented in the ST7 (see Figure 24): Slow, Wait (Slow
Wait), Active Halt and Halt.
After a RESET the normal operating mode is selected by default (Run mode). This mode
drives the device (CPU and embedded peripherals) by means of a master clock which is
based on the main oscillator frequency divided or multiplied by 2 (f
).
OSC2
From Run mode, the different power saving modes may be selected by setting the relevant
register bits or by calling the specific ST7 software instruction whose action depends on the
oscillator status.
Figure 24. Power saving mode transitions
High
RUN
SLOW
WAIT
SLOW WAIT
ACTIVE HALT
HALT
Low
POWER CONSUMPTION
8.2
Slow mode
This mode has two targets:
●
To reduce power consumption by decreasing the internal clock in the device,
To adapt the internal clock frequency (f ) to the available supply voltage.
●
CPU
Slow mode is controlled by three bits in the MCCSR register: the SMS bit which enables or
disables Slow mode and two CPx bits which select the internal slow frequency (f ).
CPU
In this mode, the master clock frequency (f
) can be divided by 2, 4, 8 or 16. The CPU
OSC2
and peripherals are clocked at this lower frequency (f
).
CPU
Note:
Slow Wait mode is activated when entering the Wait mode while the device is already in
Slow mode.
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Power saving modes
Figure 25. Slow mode clock transitions
fOSC2/2
ST72325xxx-Auto
fOSC2/4
fOSC2
fCPU
fOSC2
00
01
CP1:0
SMS
NORMAL RUN MODE
REQUEST
NEW SLOW
FREQUENCY
REQUEST
8.3
Wait mode
Wait mode places the MCU in a low power consumption mode by stopping the CPU.
This power saving mode is selected by calling the ‘WFI’ instruction.
All peripherals remain active. During Wait mode, the I[1:0] bits of the CC register are forced
to ‘10’, to enable all interrupts. All other registers and memory remain unchanged. The MCU
remains in Wait mode until an interrupt or RESET occurs, whereupon the Program Counter
branches to the starting address of the interrupt or Reset service routine.
The MCU will remain in Wait mode until a Reset or an Interrupt occurs, causing it to wake
up.
Refer to the following Figure 26.
72/250
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Figure 26. Wait mode flowchart
Power saving modes
OSCILLATOR
PERIPHERALS
CPU
ON
ON
OFF
10
WFI INSTRUCTION
I[1:0] BITS
N
RESET
Y
N
INTERRUPT
Y
OSCILLATOR
PERIPHERALS
CPU
ON
OFF
ON
10
I[1:0] BITS
256 OR 4096 CPU CLOCK
CYCLE DELAY
OSCILLATOR
PERIPHERALS
CPU
ON
ON
ON
XX(1)
I[1:0] BITS
FETCH RESET VECTOR
OR SERVICE INTERRUPT
1. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are
set to the current software priority level of the interrupt routine and recovered when the CC register is
popped.
8.4
Active Halt and Halt modes
Active Halt and Halt modes are the two lowest power consumption modes of the MCU. They
are both entered by executing the ‘HALT’ instruction. The decision to enter either in Active
Halt or Halt mode is given by the MCC/RTC interrupt enable flag (OIE bit in MCCSR
register) as shown in Table 27.
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Table 27. MCC/RTC low power mode selection
MCCSR OIE bit
Power saving mode entered when HALT instruction is executed
0
1
Halt
Active Halt
8.4.1
Active Halt mode
Active Halt mode is the lowest power consumption mode of the MCU with a real-time clock
available. It is entered by executing the ‘HALT’ instruction when the OIE bit of the Main Clock
Controller Status register (MCCSR) is set (see Section 12.3: ART registers for more details
on the MCCSR register).
The MCU can exit Active Halt mode on reception of an external interrupt, MCC/RTC
interrupt or a RESET. When exiting Active Halt mode by means of an interrupt, no 256 or
4096 CPU cycle delay occurs. The CPU resumes operation by servicing the interrupt or by
fetching the reset vector which woke it up (see Figure 28).
When entering Active Halt mode, the I[1:0] bits in the CC register are forced to ‘10b’ to
enable interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately.
In Active Halt mode, only the main oscillator and its associated counter (MCC/RTC) are
running to keep a wake-up time base. All other peripherals are not clocked except those
which get their clock supply from another clock generator (such as external or auxiliary
oscillator).
The safeguard against staying locked in Active Halt mode is provided by the oscillator
interrupt.
Note:
As soon as the interrupt capability of one of the oscillators is selected (MCCSR.OIE bit set),
entering Active Halt mode while the Watchdog is active does not generate a RESET.
This means that the device cannot spend more than a defined delay in this power saving
mode.
Caution:
When exiting Active Halt mode following an MCC/RTC interrupt, OIE bit of MCCSR register
must not be cleared before t
after the interrupt occurs (t
= 256 or 4096 t
DELAY
DELAY CPU
delay depending on option byte). Otherwise, the ST7 enters Halt mode for the remaining
period.
t
DELAY
Figure 27. Active Halt timing overview
ACTIVE
HALT
256 OR 4096 CPU
CYCLE DELAY(1)
RUN
RUN
RESET
OR
INTERRUPT
HALT
INSTRUCTION
FETCH
VECTOR
[MCCSR.OIE = 1]
1. This delay occurs only if the MCU exits Active Halt mode by means of a RESET.
74/250
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Figure 28. Active Halt mode flowchart
Power saving modes
OSCILLATOR
PERIPHERALS(1)
CPU
ON
OFF
OFF
10
HALT INSTRUCTION
(MCCSR.OIE = 1)
I[1:0] BITS
N
RESET
N
Y
INTERRUPT
OSCILLATOR
PERIPHERALS
CPU
ON
OFF
ON
Y
I[1:0] BITS
XX(2)
256 OR 4096 CPU CLOCK
CYCLE DELAY
OSCILLATOR
PERIPHERALS
CPU
ON
ON
ON
XX(2)
I[1:0] BITS
FETCH RESET VECTOR
OR SERVICE INTERRUPT
1. Peripheral clocked with an external clock source can still be active.
2. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are
set to the current software priority level of the interrupt routine and restored when the CC register is
popped.
8.4.2
Halt mode
The Halt mode is the lowest power consumption mode of the MCU. It is entered by
executing the ‘HALT’ instruction when the OIE bit of the Main Clock Controller Status
register (MCCSR) is cleared (see Chapter 11: Main clock controller with real-time clock and
beeper (MCC/RTC) for more details on the MCCSR register).
The MCU can exit Halt mode on reception of either a specific interrupt (see Table 20:
Interrupt mapping on page 66) or a RESET. When exiting Halt mode by means of a RESET
or an interrupt, the oscillator is immediately turned on and the 256 or 4096 CPU cycle delay
is used to stabilize the oscillator. After the start up delay, the CPU resumes operation by
servicing the interrupt or by fetching the reset vector which woke it up (see Figure 30).
When entering Halt mode, the I[1:0] bits in the CC register are forced to ‘10b’ to enable
interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately.
In Halt mode, the main oscillator is turned off causing all internal processing to be stopped,
including the operation of the on-chip peripherals. All peripherals are not clocked except the
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Power saving modes
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ones which get their clock supply from another clock generator (such as an external or
auxiliary oscillator).
The compatibility of Watchdog operation with Halt mode is configured by the ‘WDGHALT’
option bit of the option byte. The HALT instruction when executed while the Watchdog
system is enabled, can generate a Watchdog RESET (see Section 21.1.1: Flash
configuration on page 233 for more details).
Figure 29. Halt timing overview
256 OR 4096 CPU
CYCLE DELAY
RUN
HALT
RUN
RESET
OR
INTERRUPT
HALT
INSTRUCTION
[MCCSR.OIE = 0]
FETCH
VECTOR
76/250
ST72325xxx-Auto
Figure 30. Halt mode flowchart
Power saving modes
HALT INSTRUCTION
(MCCSR.OIE = 0)
ENABLE
0
WATCHDOG
DISABLE
WDGHALT (1)
1
WATCHDOG
RESET
OSCILLATOR
OFF
OFF
OFF
10
PERIPHERALS (2)
CPU
I[1:0] BITS
N
RESET
Y
N
INTERRUPT (3)
Y
OSCILLATOR
PERIPHERALS
CPU
ON
OFF
ON
I[1:0] BITS
XX (4)
256 OR 4096 CPU CLOCK
CYCLE DELAY
OSCILLATOR
PERIPHERALS
CPU
ON
ON
ON
XX (4)
I[1:0] BITS
FETCH RESET VECTOR
OR SERVICE INTERRUPT
1. WDGHALT is an option bit. See Section 21.1.1: Flash configuration for more details.
2. Peripheral clocked with an external clock source can still be active.
3. Only some specific interrupts can exit the MCU from Halt mode (such as external interrupt). Refer to
Table 20: Interrupt mapping for more details.
4. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are
set to the current software priority level of the interrupt routine and recovered when the CC register is
popped.
77/250
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Halt mode recommendations
●
Make sure that an external event is available to wake up the microcontroller from Halt
mode.
●
When using an external interrupt to wake up the microcontroller, re-initialize the
corresponding I/O as “Input Pull-up with Interrupt” before executing the HALT
instruction. The main reason for this is that the I/O may be wrongly configured due to
external interference or by an unforeseen logical condition.
●
●
For the same reason, reinitialize the level sensitiveness of each external interrupt as a
precautionary measure.
The opcode for the HALT instruction is 0x8E. To avoid an unexpected HALT instruction
due to a program counter failure, it is advised to clear all occurrences of the data value
0x8E from memory.
●
As the HALT instruction clears the interrupt mask in the CC register to allow interrupts,
the user may choose to clear all pending interrupt bits before executing the HALT
instruction. This avoids entering other peripheral interrupt routines after executing the
external interrupt routine corresponding to the wake-up event (reset or external
interrupt).
Related documentation
ST7 Keypad Decoding Techniques, Implementing Wake-Up on Keystroke (AN 980)
How to Minimize the ST7 Power Consumption (AN1014)
Using an active RC to wake up the ST7LITE0 from power saving mode (AN1605)
78/250
ST72325xxx-Auto
I/O ports
9
I/O ports
9.1
Introduction
The I/O ports offer different functional modes:
●
transfer of data through digital inputs and outputs
and for specific pins:
●
●
external interrupt generation
alternate signal input/output for the on-chip peripherals.
An I/O port contains up to eight pins. Each pin can be programmed independently as digital
input (with or without interrupt generation) or digital output.
9.2
Functional description
Each port has two main registers:
●
Data Register (DR)
●
Data Direction Register (DDR)
and one optional register:
Option Register (OR)
●
Each I/O pin may be programmed using the corresponding register bits in the DDR and OR
registers (bit X corresponding to pin X of the port). The same correspondence is used for
the DR register.
The following description takes into account the OR register (for specific ports which do not
provide this register refer to Section 9.3: I/O port implementation on page 83). The generic
I/O block diagram is shown in Figure 31.
9.2.1
Input modes
The input configuration is selected by clearing the corresponding DDR register bit.
In this case, reading the DR register returns the digital value applied to the external I/O pin.
Different input modes can be selected by software through the OR register.
Writing the DR register modifies the latch value but does not affect the pin status.
Note:
1
2
When switching from input to output mode, the DR register has to be written first to drive the
correct level on the pin as soon as the port is configured as an output.
3
Do not use read/modify/write instructions (BSET or BRES) to modify the DR register as this
might corrupt the DR content for I/Os configured as input.
External interrupt function
When an I/O is configured as Input with Interrupt, an event on this I/O can generate an
external interrupt request to the CPU.
Each pin can independently generate an interrupt request. The interrupt sensitivity is
independently programmable using the sensitivity bits in the EICR register.
79/250
I/O ports
ST72325xxx-Auto
Each external interrupt vector is linked to a dedicated group of I/O port pins (see pinout
description and interrupt section). If several input pins are selected simultaneously as
interrupt sources, these are first detected according to the sensitivity bits in the EICR
register and then logically ORed.
The external interrupts are hardware interrupts, which means that the request latch (not
accessible directly by the application) is automatically cleared when the corresponding
interrupt vector is fetched. To clear an unwanted pending interrupt by software, the
sensitivity bits in the EICR register must be modified.
9.2.2
Output modes
The output configuration is selected by setting the corresponding DDR register bit. In this
case, writing the DR register applies this digital value to the I/O pin through the latch. Then
reading the DR register returns the previously stored value.
Two different output modes can be selected by software through the OR register: Output
push-pull and open-drain. The DR register value and output pin status are shown in the
following Table 28.
Table 28. I/O output mode selection
DR
Push-pull
Open-drain
0
1
VSS
VDD
VSS
Floating
9.2.3
Alternate functions
When an on-chip peripheral is configured to use a pin, the alternate function is automatically
selected. This alternate function takes priority over the standard I/O programming.
When the signal is coming from an on-chip peripheral, the I/O pin is automatically
configured in output mode (push-pull or open-drain according to the peripheral).
When the signal is going to an on-chip peripheral, the I/O pin must be configured in input
mode. In this case, the pin state is also digitally readable by addressing the DR register.
Note:
Input pull-up configuration can cause unexpected value at the input of the alternate
peripheral input. When an on-chip peripheral use a pin as input and output, this pin has to
be configured in input floating mode.
80/250
ST72325xxx-Auto
Figure 31. I/O port general block diagram
I/O ports
ALTERNATE
OUTPUT
1
0
REGISTER
ACCESS
P-BUFFER
(see table below)
VDD
ALTERNATE
ENABLE
PULL-UP
(see table below)
VDD
DR
DDR
OR
PULL-UP
CONDITION
PAD
If implemented
OR SEL
DDR SEL
DR SEL
N-BUFFER
DIODES
(see table below)
ANALOG
INPUT
CMOS
SCHMITT
TRIGGER
1
0
ALTERNATE
INPUT
EXTERNAL
INTERRUPT
SOURCE (eix)
Table 29. I/O port mode options
Configuration mode
Diodes
to VSS
Pull-up
P-buffer
to VDD
Floating with/without Interrupt
Input
Off
On
Off
Pull-up with/without Interrupt
On
Push-pull
On
Off
NI
On
Off
NI
Output
Open-drain (logic level)
True open-drain
NI(1)
1. The diode to VDD is not implemented in the true open-drain pads. A local protection between the pad and
SS is implemented to protect the device against positive stress.
V
Legend:
Off - Implemented not activated
On - Implemented and activated
NI - Not implemented
81/250
I/O ports
ST72325xxx-Auto
Table 30. I/O port configurations
Hardware configuration
DR REGISTER ACCESS
NOT IMPLEMENTED IN
TRUE OPEN DRAIN
I/O PORTS
V
DD
PULL-UP
CONDITION
R
PU
DR
REGISTER
W
R
DATA BUS
PAD
ALTERNATE INPUT
EXTERNAL INTERRUPT
SOURCE (ei )
x
INTERRUPT
CONDITION
ANALOG INPUT
NOT IMPLEMENTED IN
TRUE OPEN DRAIN
I/O PORTS
DR REGISTER ACCESS
V
DD
R
PU
R/W
DR
REGISTER
DATA BUS
PAD
ALTERNATE
ENABLE
ALTERNATE
OUTPUT
NOT IMPLEMENTED IN
TRUE OPEN DRAIN
I/O PORTS
DR REGISTER ACCESS
V
DD
R
PU
R/W
DR
REGISTER
DATA BUS
PAD
ALTERNATE
ENABLE
ALTERNATE
OUTPUT
1. When the I/O port is in input configuration and the associated alternate function is enabled as an output, reading the DR
register will read the alternate function output status.
2. When the I/O port is in output configuration and the associated alternate function is enabled as an input, the alternate
function reads the pin status given by the DR register content.
82/250
ST72325xxx-Auto
I/O ports
Caution:
The alternate function must not be activated as long as the pin is configured as input with
interrupt, in order to avoid generating spurious interrupts.
Analog alternate function
When the pin is used as an ADC input, the I/O must be configured as floating input. The
analog multiplexer (controlled by the ADC registers) switches the analog voltage present on
the selected pin to the common analog rail which is connected to the ADC input.
It is recommended not to change the voltage level or loading on any port pin while
conversion is in progress. Furthermore it is recommended not to have clocking pins located
close to a selected analog pin.
Warning: The analog input voltage level must be within the limits
stated in the absolute maximum ratings.
9.3
I/O port implementation
The hardware implementation on each I/O port depends on the settings in the DDR and OR
registers and specific feature of the I/O port such as ADC Input or true open-drain.
Switching these I/O ports from one state to another should be done in a sequence that
prevents unwanted side effects. Recommended safe transitions are illustrated in Figure 32.
Other transitions are potentially risky and should be avoided, since they are likely to present
unwanted side-effects such as spurious interrupt generation.
Figure 32. Interrupt I/O port state transitions
01
00
10
11
INPUT
floating/pull-up
interrupt
INPUT
floating
(reset state)
OUTPUT
open-drain
OUTPUT
push-pull
XX = DDR, OR
The I/O port register configurations are summarized in the following table.
Table 31. I/O port configuration
Input (DDR = 0)
OR = 0 OR = 1
Output (DDR = 1)
Port
Pin name
OR = 0
OR = 1
PA7:6
floating
true open-drain
PA5:4
PA3
floating
floating
floating
pull-up
open-drain
open-drain
open-drain
push-pull
push-pull
push-pull
Port A
floating interrupt
pull-up interrupt
PA2:0
83/250
I/O ports
ST72325xxx-Auto
Table 31. I/O port configuration (continued)
Input (DDR = 0)
Output (DDR = 1)
Port
Pin name
OR = 0
OR = 1
OR = 0
OR = 1
PB7, PB3
floating
floating
floating
floating
floating
floating interrupt
pull-up interrupt
pull-up
open-drain
open-drain
open-drain
open-drain
open-drain
open-drain(1)
open-drain
open-drain
open-drain
push-pull
push-pull
push-pull
push-pull
push-pull
push-pull(1)
push-pull
push-pull
push-pull
Port B
PB6:5, PB4, PB2:0
Port C PC7:0
Port D PD7:0
pull-up
PE7:3, PE1:0
pull-up
Port E
PE2
pull-up
PF7:3
floating
floating
floating
pull-up
Port F PF2
PF1:0
floating interrupt
pull-up interrupt
1. Pull-up is always enabled leading to unwanted power consumption if output is tied to low level
9.4
9.5
Low power modes
Table 32. Effect of low power modes on I/O ports
Mode
Effect
Wait
Halt
No effect on I/O ports. External interrupts cause the device to exit from Wait mode.
No effect on I/O ports. External interrupts cause the device to exit from Halt mode.
Interrupts
The external interrupt event generates an interrupt if the corresponding configuration is
selected with DDR and OR registers and the interrupt mask in the CC register is not active
(RIM instruction).
Table 33. I/O port interrupt control/wake-up capability
Enable
control bit
Exit from
Wait
Exit from
Halt
Interrupt event
Event flag
External interrupt on selected
external event
-
DDRx, ORx
Yes
Yes
Table 34. I/O port register map and reset values
Address (Hex.)
Register label
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Reset value of all I/O port registers
0000h
0001h
0002h
PADR
PADDR
PAOR
MSB
LSB
84/250
ST72325xxx-Auto
Table 34. I/O port register map and reset values (continued)
I/O ports
Address (Hex.)
Register label
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Reset value of all I/O port registers
0003h
0004h
0005h
0006h
0007h
0008h
0009h
000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
0010h
0011h
PBDR
PBDDR
PBOR
PCDR
PCDDR
PCOR
PDDR
PDDDR
PDOR
PEDR
PEDDR
PEOR
PFDR
MSB
MSB
MSB
MSB
MSB
LSB
LSB
LSB
LSB
LSB
PFDDR
PFOR
Related documentation
SPI Communication between ST7 and EEPROM (AN 970)
S/W implementation of I2C bus master (AN1045)
Software LCD driver (AN1048)
85/250
Watchdog timer (WDG)
ST72325xxx-Auto
10
Watchdog timer (WDG)
10.1
Introduction
The Watchdog timer is used to detect the occurrence of a software fault, usually generated
by external interference or by unforeseen logical conditions, which causes the application
program to abandon its normal sequence. The Watchdog circuit generates an MCU reset on
expiry of a programmed time period, unless the program refreshes the counter’s contents
before the T6 bit becomes cleared.
10.2
10.3
Main features
●
●
●
●
●
Programmable free-running downcounter
Programmable reset
Reset (if watchdog activated) when the T6 bit reaches zero
Optional reset on HALT instruction (configurable by option byte)
Hardware Watchdog selectable by option byte
Functional description
The counter value stored in the Watchdog Control register (WDGCR bits T[6:0]), is
decremented every 16384 f
cycles (approx.), and the length of the timeout period can
OSC2
be programmed by the user in 64 increments.
If the watchdog is activated (the WDGA bit is set) and when the 7-bit timer (bits T[6:0]) rolls
over from 40h to 3Fh (T6 becomes cleared), it initiates a reset cycle pulling the RESET pin
low for typically 30µs.
The application program must write in the WDGCR register at regular intervals during
normal operation to prevent an MCU reset. This downcounter is free-running: It counts down
even if the watchdog is disabled. The value to be stored in the WDGCR register must be
between FFh and C0h:
–
–
–
The WDGA bit is set (watchdog enabled)
The T6 bit is set to prevent generating an immediate reset
The T[5:0] bits contain the number of increments which represents the time delay
before the watchdog produces a reset (see Figure 34: Approximate timeout
duration). The timing varies between a minimum and a maximum value due to the
unknown status of the prescaler when writing to the WDGCR register (see
Figure 35).
Following a reset, the watchdog is disabled. Once activated it cannot be disabled, except by
a reset.
The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is
cleared).
If the watchdog is activated, the HALT instruction will generate a Reset.
86/250
ST72325xxx-Auto
Figure 33. Watchdog block diagram
Watchdog timer (WDG)
RESET
f
OSC2
MCC/RTC
WATCHDOG CONTROL REGISTER (WDGCR)
T6 T5 T4 T3 T2 T1
DIV 64
WDGA
T0
6-BIT DOWNCOUNTER (CNT)
12-BIT MCC
RTC COUNTER
WDG PRESCALER
DIV 4
TB[1:0] bits
(MCCSR
Register)
MSB
LSB
11
6 5
0
10.4
How to program the watchdog timeout
Figure 34 shows the linear relationship between the 6-bit value to be loaded in the
Watchdog Counter (CNT) and the resulting timeout duration in milliseconds. This can be
used for a quick calculation without taking the timing variations into account. If more
precision is needed, use the formulae in Figure 35.
Caution:
When writing to the WDGCR register, always write 1 in the T6 bit to avoid generating an
immediate reset.
Figure 34. Approximate timeout duration
3F
38
30
28
20
18
10
08
00
1.5
18
34
50
65
82
98
114
128
Watchdog timeout (ms) @ 8 MHz fOSC2
87/250
Watchdog timer (WDG)
Figure 35. Exact timeout duration (t
ST72325xxx-Auto
and t
)
min
max
WHERE:
min0 = (LSB + 128) x 64 x tOSC2
t
tmax0 = 16384 x tOSC2
tOSC2 = 125ns if fOSC2= 8 MHz
CNT = Value of T[5:0] bits in the WDGCR register (6 bits)
MSB and LSB are values from the table below depending on the timebase selected by the TB[1:0] bits
in the MCCSR register
TB1 bit
TB0 bit
Selected MCCSR
timebase
MSB
LSB
(MCCSR reg.) (MCCSR reg.)
0
0
1
1
0
1
0
1
2ms
4ms
4
8
59
53
35
54
10ms
25ms
20
49
To calculate the minimum Watchdog Timeout (tmin):
MSB
4
IF
-------------
THEN
ELSE
CNT <
t
= tmin0 + 16384 × CNT × t
min
osc2
4CNT
----------------
4CNT
----------------
⎛
⎞
⎠
t
= t
+
16384 × CNT –
+ (192 + LSB) × 64 ×
× t
osc2
min
min0
⎝
MSB
MSB
To calculate the maximum Watchdog Timeout (tmax):
MSB
4
IF
-------------
THEN
ELSE
CNT ≤
t
= tmax0 + 16384 × CNT × t
osc2
max
4CNT
----------------
4CNT
----------------
⎛
⎞
t
= t
+
16384 × CNT –
+ (192 + LSB) × 64 ×
× t
osc2
max
max0
⎝
⎠
MSB
MSB
Note: In the above formulae, division results must be rounded down to the next integer value.
Example:
With 2ms timeout selected in MCCSR register
Min. Watchdog
Timeout (ms)
Max. Watchdog
Timeout (ms)
Value of T[5:0] bits in
WDGCR register (Hex.)
t
t
min
max
00
3F
1.496
128
2.048
128.552
88/250
ST72325xxx-Auto
Watchdog timer (WDG)
10.5
Low power modes
Table 35. Effect of low power modes on WDG
Mode
Effect
Slow No effect on Watchdog
Wait
No effect on Watchdog
WDGHALT
OIE bit in
bit in
MCCSR
register
Option
Byte
No Watchdog reset is generated. The MCU enters Halt mode.
The Watchdog counter is decremented once and then stops
counting and is no longer able to generate a watchdog reset
until the MCU receives an external interrupt or a reset.
0
0
If an external interrupt is received, the Watchdog restarts
counting after 256 or 4096 CPU clocks. If a reset is generated,
the Watchdog is disabled (reset state) unless Hardware
Watchdog is selected by option byte. For application
recommendations see Section 10.7 below.
Halt
0
1
1
x
A reset is generated.
No reset is generated. The MCU enters Active Halt mode. The
Watchdog counter is not decremented. It stop counting. When
the MCU receives an oscillator interrupt or external interrupt,
the Watchdog restarts counting immediately. When the MCU
receives a reset the Watchdog restarts counting after 256 or
4096 CPU clocks.
10.6
10.7
10.8
Hardware watchdog option
If Hardware Watchdog is selected by option byte, the watchdog is always active and the
WDGA bit in the WDGCR is not used. Refer to the option byte description in Section 21.1.1:
Flash configuration on page 233.
Using Halt mode with the WDG (WDGHALT option)
The following recommendation applies if Halt mode is used when the watchdog is enabled:
Before executing the HALT instruction, refresh the WDG counter to avoid an unexpected
WDG reset immediately after waking up the microcontroller.
Interrupts
None.
89/250
Watchdog timer (WDG)
ST72325xxx-Auto
10.9
Register description
10.9.1
Control register (WDGCR)
WDGCR
Reset value: 0111 1111 (7Fh)
7
6
5
4
3
2
1
0
WDGA
T[6:0]
RW
RW
Table 36. WDGCR register description
Bit Name
Function
Activation bit
This bit is set by software and only cleared by hardware after a reset. When
WDGA = 1, the watchdog can generate a reset.
0: Watchdog disabled
7
WDGA
1: Watchdog enabled
Note: This bit is not used if the hardware watchdog option is enabled by option byte.
7-bit counter (MSB to LSB)
These bits contain the value of the watchdog counter. It is decremented every 16384
6:0 T[6:0]
f
OSC2 cycles (approx.). A reset is produced when it rolls over from 40h to 3Fh (T6
becomes cleared).
Table 37. Watchdog timer register map and reset values
Address
(Hex.)
Register
label
7
6
5
4
3
2
1
0
WDGCR
Reset Value
WDGA
0
T6
1
T5
1
T4
1
T3
1
T2
1
T1
1
T0
1
002Ah
90/250
ST72325xxx-Auto
Main clock controller with real-time clock and beeper (MCC/RTC)
11
Main clock controller with real-time clock and beeper
(MCC/RTC)
11.1
Introduction
The Main Clock Controller consists of three different functions:
●
a programmable CPU clock prescaler
●
a clock-out signal to supply external devices
●
a real-time clock timer with interrupt capability
Each function can be used independently and simultaneously.
11.2
11.3
Programmable CPU clock prescaler
The programmable CPU clock prescaler supplies the clock for the ST7 CPU and its internal
peripherals. It manages Slow power saving mode (see Section 8.2: Slow mode on page 71
for more details).
The prescaler selects the f
main clock frequency and is controlled by three bits in the
CPU
MCCSR register: CP[1:0] and SMS.
Clock-out capability
The clock-out capability is an alternate function of an I/O port pin that outputs a f
drive external devices. It is controlled by the MCO bit in the MCCSR register.
clock to
CPU
Caution:
When selected, the clock out pin suspends the clock during Active Halt mode.
11.4
Real-time clock timer (RTC)
The counter of the real-time clock timer allows an interrupt to be generated based on an
accurate real-time clock. Four different time bases depending directly on f are available.
OSC2
The whole functionality is controlled by four bits of the MCCSR register: TB[1:0], OIE and
OIF.
When the RTC interrupt is enabled (OIE bit set), the ST7 enters Active Halt mode when the
HALT instruction is executed. See Section 8.4: Active Halt and Halt modes on page 73 for
more details.
11.5
Beeper
The beep function is controlled by the MCCBCR register. It can output three selectable
frequencies on the BEEP pin (I/O port alternate function).
91/250
Main clock controller with real-time clock and beeper (MCC/RTC)
ST72325xxx-Auto
Figure 36.
Main clock controller (MCC/RTC) block diagram
BC1 BC0
MCCBCR
BEEP
MCO
BEEP SIGNAL
SELECTION
12-BIT MCC RTC
COUNTER
TO
DIV 64
WATCHDOG
TIMER
MCO CP1 CP0 SMS TB1 TB0 OIE
OIF
MCCSR
MCC/RTC INTERRUPT
f
OSC2
DIV 2, 4, 8, 16
1
0
CPU CLOCK
TO CPU AND
PERIPHERALS
f
CPU
11.6
Low power modes
Table 38. Effect of low power modes on MCC/RTC
Mode
Effect
No effect on MCC/RTC peripheral.
MCC/RTC interrupt causes the device to exit from Wait mode.
Wait
No effect on MCC/RTC counter (OIE bit is set), the registers are frozen.
MCC/RTC interrupt causes the device to exit from Active Halt mode.
Active Halt
Halt
MCC/RTC counter and registers are frozen.
MCC/RTC operation resumes when the MCU is woken up by an interrupt with
“exit from HALT” capability.
11.7
Interrupts
The MCC/RTC interrupt event generates an interrupt if the OIE bit of the MCCSR register is
set and the interrupt mask in the CC register is not active (RIM instruction).
Table 39. MCC/RTC interrupt control/wake-up capability
Enable
control bit
Exit from
Wait
Exit from
Halt
Interrupt event
Event flag
Time base overflow event
OIF
OIE
Yes
No(1)
1. The MCC/RTC interrupt wakes up the MCU from Active Halt mode, not from Halt mode.
92/250
ST72325xxx-Auto
Main clock controller with real-time clock and beeper (MCC/RTC)
11.8
Main clock controller registers
11.8.1
MCC control/status register (MCCSR)
MCCSR
Reset value: 0000 0000 (00h)
7
6
5
4
3
2
1
0
MCO
CP[1:0]
RW
SMS
OIE
OIF
TB[1:0]
RW
RW
RW
RW
RW
Table 40. MCCSR register description
Bit Name
Function
Main clock out selection
This bit enables the MCO alternate function on the PF0 I/O port. It is set and
cleared by software.
7
MCO
0: MCO alternate function disabled (I/O pin free for general-purpose I/O)
1: MCO alternate function enabled (fCPU on I/O port)
Note: To reduce power consumption, the MCO function is not active in Active Halt
mode.
CPU clock prescaler
These bits select the CPU clock prescaler which is applied in the different slow
modes. Their action is conditioned by the setting of the SMS bit. These two bits are
set and cleared by software.
6:5 CP[1:0]
00: fCPU in Slow mode = fOSC2/2
01: fCPU in Slow mode = fOSC2/4
10: fCPU in Slow mode = fOSC2/8
11: fCPU in Slow mode = fOSC2/16
Slow mode select
This bit is set and cleared by software.
0: Normal mode. fCPU = fOSC2
1: Slow mode. fCPU is given by CP1, CP0
4
SMS
See
and Chapter 11: Main clock controller with
Section 8.2: Slow mode on page 71
real-time clock and beeper (MCC/RTC) for more details.
Time base control
These bits select the programmable divider time base. They are set and cleared by
Table 41)
software (see
.
3:2
TB[1:0]
A modification of the time base is taken into account at the end of the current period
(previously set) to avoid an unwanted time shift. This allows to use this time base
as a real-time clock.
Oscillator interrupt enable
This bit set and cleared by software.
0: Oscillator interrupt disabled
1: Oscillator interrupt enabled
1
OIE
This interrupt can be used to exit from Active Halt mode.
When this bit is set, calling the ST7 software HALT instruction enters the Active Halt
power saving mode
.
93/250
Main clock controller with real-time clock and beeper (MCC/RTC)
Table 40. MCCSR register description (continued)
ST72325xxx-Auto
Bit Name
Function
Oscillator interrupt flag
This bit is set by hardware and cleared by software reading the MCCSR register. It
indicates when set that the main oscillator has reached the selected elapsed time
(TB1:0).
0
OIF
0: Timeout not reached
1: Timeout reached
Caution: The BRES and BSET instructions must not be used on the MCCSR
register to avoid unintentionally clearing the OIF bit.
Table 41. Time base selection
Time base
Counter prescaler
TB1
TB0
fOSC2 = 4 MHz
4ms
fOSC2 = 8 MHz
16000
32000
80000
200000
2ms
4ms
0
0
1
1
0
1
0
1
8ms
20ms
50ms
10ms
25ms
11.8.2
MCC beep control register (MCCBCR)
MCCBCR
Reset value: 0000 0000 (00h)
7
6
5
4
3
2
1
0
Reserved
-
BC[1:0]
RW
Table 42. MCCBCR register description
Bit Name
Function
7:2
-
Reserved, must be kept cleared.
Beep control
1:0 BC[1:0]
These 2 bits select the PF1 pin beep capability (see Table 43).
Table 43. Beep frequency selection
BC1
BC0
Beep mode with fOSC2 = 8 MHz
0
0
1
1
0
1
0
1
Off
~2 kHz
Output
Beep signal
~50% duty cycle
~1 kHz
~500 Hz
The beep output signal is available in Active Halt mode but has to be disabled to reduce
consumption.
94/250
ST72325xxx-Auto
Main clock controller with real-time clock and beeper (MCC/RTC)
Table 44. Main clock controller register map and reset values
Address (Hex.) Register label
7
6
5
4
3
0
2
1
0
SICSR
002Bh
AVDS
0
AVDIE
0
AVDF
0
LVDRF
x
CSSIE
0
CSSD WDGRF
Reset value
0
x
MCCSR
002Ch
MCO
0
CP1
0
CP0
0
SMS
0
TB1
0
TB0
0
OIE
0
OIF
0
Reset value
MCCBCR
002Dh
BC1
0
BC0
0
Reset value
0
0
0
0
0
0
95/250
PWM auto-reload timer (ART)
ST72325xxx-Auto
12
PWM auto-reload timer (ART)
12.1
Introduction
The Pulse Width Modulated Auto-Reload Timer on-chip peripheral consists of an 8-bit auto-
reload counter with compare/capture capabilities and of a 7-bit prescaler clock source.
These resources allow five possible operating modes:
●
●
●
●
●
Generation of up to 4 independent PWM signals
Output compare and Time base interrupt
Up to 2 input capture functions
External event detector
Up to 2 external interrupt sources
The three first modes can be used together with a single counter frequency.
The timer can be used to wake up the MCU from Wait and Halt modes.
Figure 37. PWM auto-reload timer block diagram
OCRx
DCRx
OEx
OPx
PWMCR
REGISTER
REGISTER
LOAD
PORT
ALTERNATE
FUNCTION
POLARITY
CONTROL
PWMx
COMPARE
8-BIT COUNTER
(CAR REGISTER)
ARR
REGISTER
LOAD
INPUT CAPTURE
CONTROL
ICRx
LOAD
ARTICx
REGISTER
ICSx
ICIEx
ICFx
ICCSR
ICx INTERRUPT
f
EXT
ARTCLK
f
COUNTER
f
CPU
MUX
f
INPUT
PROGRAMMABLE
PRESCALER
ARTCSR
EXCL CC2 CC1 CC0 TCE FCRL OIE
OVF
OVF INTERRUPT
96/250
ST72325xxx-Auto
PWM auto-reload timer (ART)
12.2
Functional description
12.2.1
Counter
The free running 8-bit counter is fed by the output of the prescaler, and is incremented on
every rising edge of the clock signal.
It is possible to read or write the contents of the counter on the fly by reading or writing the
Counter Access register (ARTCAR).
When a counter overflow occurs, the counter is automatically reloaded with the contents of
the ARTARR register (the prescaler is not affected).
12.2.2
Counter clock and prescaler
The counter clock frequency is given by:
CC[2:0]
f
= f
/ 2
COUNTER
INPUT
The timer counter’s input clock (f
) feeds the 7-bit programmable prescaler, which
INPUT
selects one of the 8 available taps of the prescaler, as defined by CC[2:0] bits in the
Control/Status Register (ARTCSR). Thus the division factor of the prescaler can be set to 2
(where n = 0, 1,..7).
n
This f
frequency source is selected through the EXCL bit of the ARTCSR register and
INPUT
can be either the f
or an external input frequency f
.
CPU
EXT
The clock input to the counter is enabled by the TCE (Timer Counter Enable) bit in the
ARTCSR register. When TCE is reset, the counter is stopped and the prescaler and counter
contents are frozen. When TCE is set, the counter runs at the rate of the selected clock
source.
12.2.3
Counter and prescaler initialization
After RESET, the counter and the prescaler are cleared and f
The counter can be initialized by:
= f
.
INPUT
CPU
●
writing to the ARTARR register and then setting the FCRL (Force Counter Re-Load)
and the TCE (Timer Counter Enable) bits in the ARTCSR register
●
writing to the ARTCAR counter access register
In both cases the 7-bit prescaler is also cleared, whereupon counting will start from a known
value.
Direct access to the prescaler is not possible.
12.2.4
Output compare control
The timer compare function is based on four different comparisons with the counter (one for
each PWMx output). Each comparison is made between the counter value and an output
compare register (OCRx) value. This OCRx register can not be accessed directly, it is
loaded from the duty cycle register (PWMDCRx) at each overflow of the counter.
This double buffering method avoids glitch generation when changing the duty cycle on the
fly.
97/250
PWM auto-reload timer (ART)
Figure 38. Output compare control
ST72325xxx-Auto
f
COUNTER
ARTARR = FDh
FFh
COUNTER
OCRx
FDh
FEh
FDh
FEh
FFh
FDh
FEh
FFh
FEh
FDh
PWMDCRx
FEh
FDh
PWMx
12.2.5
Independent PWM signal generation
This mode allows up to four Pulse Width Modulated signals to be generated on the PWMx
output pins with minimum core processing overhead. This function is stopped during Halt
mode.
Each PWMx output signal can be selected independently using the corresponding OEx bit
in the PWM Control register (PWMCR). When this bit is set, the corresponding I/O pin is
configured as output push-pull alternate function.
The PWM signals all have the same frequency which is controlled by the counter period and
the ARTARR register value.
f
= f
/ (256 - ARTARR)
PWM
COUNTER
When a counter overflow occurs, the PWMx pin level is changed depending on the
corresponding OPx (output polarity) bit in the PWMCR register. When the counter reaches
the value contained in one of the output compare register (OCRx) the corresponding PWMx
pin level is restored.
It should be noted that the reload values will also affect the value and the resolution of the
duty cycle of the PWM output signal. To obtain a signal on a PWMx pin, the contents of the
OCRx register must be greater than the contents of the ARTARR register.
The maximum available resolution for the PWMx duty cycle is:
Resolution = 1 / (256 - ARTARR)
Note:
To get the maximum resolution (1/256), the ARTARR register must be 0. With this maximum
resolution, 0% and 100% can be obtained by changing the polarity.
98/250
ST72325xxx-Auto
PWM auto-reload timer (ART)
Figure 39. PWM auto-reload timer function
255
DUTY CYCLE
REGISTER
(PWMDCRx)
AUTO-RELOAD
REGISTER
(ARTARR)
000
t
WITH OEx=1
AND OPx=0
WITH OEx=1
AND OPx=1
Figure 40. PWM signal from 0% to 100% duty cycle
f
COUNTER
ARTARR = FDh
FFh
COUNTER
FDh
FEh
FDh
FEh
FFh
FDh
FEh
OCRx=FCh
OCRx=FDh
OCRx=FEh
OCRx=FFh
t
12.2.6
Output compare and time base interrupt
On overflow, the OVF flag of the ARTCSR register is set and an overflow interrupt request is
generated if the overflow interrupt enable bit, OIE, in the ARTCSR register, is set. The OVF
flag must be reset by the user software. This interrupt can be used as a time base in the
application.
12.2.7
External clock and event detector mode
Using the f
external prescaler input clock, the auto-reload timer can be used as an
EXT
external clock event detector. In this mode, the ARTARR register is used to select the
number of events to be counted before setting the OVF flag.
n
EVENT
n
= 256 - ARTARR
EVENT
Caution:
The external clock function is not available in Halt mode. If Halt mode is used in the
application, prior to executing the HALT instruction, the counter must be disabled by clearing
the TCE bit in the ARTCSR register to avoid spurious counter increments.
99/250
PWM auto-reload timer (ART)
Figure 41. External event detector example (3 counts)
ST72325xxx-Auto
f
= f
COUNTER
EXT
ARTARR = FDh
FFh
COUNTER
OVF
FDh
FEh
FDh
FEh
FFh
FDh
ARTCSR READ
ARTCSR READ
INTERRUPT
IF OIE = 1
INTERRUPT
IF OIE = 1
t
12.2.8
Input capture function
This mode allows the measurement of external signal pulse widths through ARTICRx
registers.
Each input capture can generate an interrupt independently on a selected input signal
transition. This event is flagged by a set of the corresponding CFx bits of the Input Capture
Control/Status register (ARTICCSR).
These input capture interrupts are enabled through the CIEx bits of the ARTICCSR register.
The active transition (falling or rising edge) is software programmable through the CSx bits
of the ARTICCSR register.
The read only input capture registers (ARTICRx) are used to latch the auto-reload counter
value when a transition is detected on the ARTICx pin (CFx bit set in ARTICCSR register).
After fetching the interrupt vector, the CFx flags can be read to identify the interrupt source.
Note:
Note:
After a capture detection, data transfer in the ARTICRx register is inhibited until it is read
(clearing the CFx bit).
The timer interrupt remains pending while the CFx flag is set when the interrupt is enabled
(CIEx bit set). This means that the ARTICRx register has to be read at each capture event to
clear the CFx flag.
The timing resolution is given by auto-reload counter cycle time (1/f
).
COUNTER
During Halt mode, if both the input capture and the external clock are enabled, the ARTICRx
register value is not guaranteed if the input capture pin and the external clock change
simultaneously.
100/250
ST72325xxx-Auto
PWM auto-reload timer (ART)
12.2.9
External interrupt capability
This mode allows the input capture capabilities to be used as external interrupt sources. The
interrupts are generated on the edge of the ARTICx signal.
The edge sensitivity of the external interrupts is programmable (CSx bit of ARTICCSR
register) and they are independently enabled through CIEx bits of the ARTICCSR register.
After fetching the interrupt vector, the CFx flags can be read to identify the interrupt source.
During Halt mode, the external interrupts can be used to wake up the micro (if the CIEx bit is
set).
Figure 42. Input capture timing diagram
f
COUNTER
COUNTER
01h
02h
03h
04h
05h
06h
07h
INTERRUPT
04h
ARTICx PIN
CFx FLAG
xxh
ICRx REGISTER
t
101/250
PWM auto-reload timer (ART)
ST72325xxx-Auto
12.3
ART registers
12.3.1
Control/status register (ARTCSR)
ARTCSR
Reset value: 0000 0000 (00h)
7
6
5
4
3
2
1
0
EXCL
CC[2:0]
TCE
FCRL
OIE
OVF
RW
RW
RW
RW
RW
RW
Table 45. ARTCSR register description
Bit Name
Function
External Clock
This bit is set and cleared by software. It selects the input clock for the 7-bit
prescaler.
7
EXCL
0: CPU clock
1: External clock
Counter Clock Control
6:4 CC[2:0]
These bits are set and cleared by software. They determine the prescaler division
ratio from fINPUT (see Table 46).
Timer Counter Enable
This bit is set and cleared by software. It puts the timer in the lowest power
consumption mode.
0: Counter stopped (prescaler and counter frozen)
1: Counter running
3
2
1
0
TCE
FCRL
OIE
Force Counter Re-Load
This bit is write-only and any attempt to read it will yield a logical zero. When set, it
causes the contents of ARTARR register to be loaded into the counter, and the
content of the prescaler register to be cleared in order to initialize the timer before
starting to count.
Overflow Interrupt Enable
This bit is set and cleared by software. It allows to enable/disable the interrupt which
is generated when the OVF bit is set.
0: Overflow Interrupt disable
1: Overflow Interrupt enable
Overflow Flag
This bit is set by hardware and cleared by software reading the ARTCSR register. It
indicates the transition of the counter from FFh to the ARTARR value.
0: New transition not yet reached
OVF
1: Transition reached
Table 46. Prescaler selection for ART
fCOUNTER
With fINPUT = 8 MHz
CC2
CC1
CC0
fINPUT
8 MHz
4 MHz
2 MHz
0
0
0
0
0
1
0
1
0
f
INPUT / 2
fINPUT / 4
102/250
ST72325xxx-Auto
Table 46. Prescaler selection for ART (continued)
PWM auto-reload timer (ART)
fCOUNTER
With fINPUT = 8 MHz
CC2
CC1
CC0
fINPUT / 8
1 MHz
500 kHz
250 kHz
125 kHz
62.5 kHz
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
f
INPUT / 16
fINPUT / 32
fINPUT / 64
INPUT / 128
f
12.3.2
Counter access register (ARTCAR)
ARTCAR
Reset value: 0000 0000 (00h)
7
6
5
4
3
2
1
0
CA[7:0]
RW
Table 47. ARTCAR register description
Bit Name
Function
Counter Access Data
These bits can be set and cleared either by hardware or by software. The
ARTCAR register is used to read or write the auto-reload counter “on the fly”
(while it is counting).
7:0 CA[7:0]
12.3.3
Auto-reload register (ARTARR)
ARTARR
Reset value: 0000 0000 (00h)
7
6
5
4
3
2
1
0
AR[7:0]
RW
Table 48. ARTAAR register description
Bit Name
Function
Counter Auto-Reload Data
These bits are set and cleared by software. They are used to hold the auto-reload
value which is automatically loaded in the counter when an overflow occurs. At the
same time, the PWM output levels are changed according to the corresponding
OPx bit in the PWMCR register.
7:0 AR[7:0]
This register has two PWM management functions:
–
–
Adjusting the PWM frequency
Setting the PWM duty cycle resolution
103/250
PWM auto-reload timer (ART)
ST72325xxx-Auto
Table 49. PWM frequency versus resolution
fPWM
ARTARR value
Resolution
Min
Max
0
8-bit
~0.244 kHz
~0.244 kHz
~0.488 kHz
~0.977 kHz
~1.953 kHz
31.25 kHz
62.5 kHz
125 kHz
250 kHz
500 kHz
[ 0..127 ]
> 7-bit
> 6-bit
> 5-bit
> 4-bit
[ 128..191 ]
[ 192..223 ]
[ 224..239 ]
12.3.4
PWM control register (PWMCR)
PWMCR
Reset value: 0000 0000 (00h)
7
6
5
4
3
2
1
0
OE[3:0]
RW
OP[3:0]
RW
Table 50. PWMCR register description
Bit Name
Function
PWM Output Enable
These bits are set and cleared by software. They enable or disable the PWM
output channels independently acting on the corresponding I/O pin.
0: PWM output disabled
7:4 OE[3:0]
3:0 OP[3:0]
1: PWM output enabled
PWM Output Polarity
These bits are set and cleared by software. They independently select the polarity
of the four PWM output signals (see Table 51).
Table 51. PWM output signal polarity selection
PWMx output level
OPx(1)
Counter <= OCRx
Counter > OCRx
1
0
0
1
0
1
1. When an OPx bit is modified, the PWMx output signal polarity is immediately reversed.
104/250
ST72325xxx-Auto
PWM auto-reload timer (ART)
12.3.5
Duty cycle registers (PWMDCRx)
PWMDCRx
7
Reset value: 0000 0000 (00h)
6
5
4
3
2
1
0
DC[7:0]
RW
Table 52. PWMDCRx register description
Bit Name
Function
Duty Cycle Data
7:0 DC[7:0]
These bits are set and cleared by software.
A PWMDCRx register is associated with the OCRx register of each PWM channel to
determine the second edge location of the PWM signal (the first edge location is common to
all channels and given by the ARTARR register). These PWMDCR registers allow the duty
cycle to be set independently for each PWM channel.
12.3.6
Input capture control / status register (ARTICCSR)
ARTICCSR
7
Reset value: 0000 0000 (00h)
6
5
4
3
2
1
0
Reserved
CS[2:1]
RW
CIE[2:1]
RW
CF[2:1]
RW
-
Table 53. ARTICCSR register description
Bit
Name
Function
7:6
-
Reserved, always read as 0.
Capture Sensitivity
These bits are set and cleared by software. They determine the trigger event
polarity on the corresponding input capture channel.
0: Falling edge triggers capture on channel x
5:4 CS[2:1]
3:2 CIE[2:1]
1: Rising edge triggers capture on channel x
Capture Interrupt Enable
These bits are set and cleared by software. They enable or disable the Input
capture channel interrupts independently.
0: Input capture channel x interrupt disabled
1: Input capture channel x interrupt enabled
Capture Flag
These bits are set by hardware and cleared by software reading the
corresponding ARTICRx register. Each CFx bit indicates that an input capture x
has occurred.
1:0 CF[2:1]
0: No input capture on channel x
1: An input capture has occurred on channel x.
105/250
PWM auto-reload timer (ART)
ST72325xxx-Auto
12.3.7
Input capture registers (ARTICRx)
ARTICRx
7
Reset value: 0000 0000 (00h)
6
5
4
3
2
1
0
IC[7:0]
RO
Table 54. ARTICRx register description
Bit Name
Function
Input Capture Data
These read only bits are set and cleared by hardware. An ARTICRx register
contains the 8-bit auto-reload counter value transferred by the input capture
channel x event.
7:0 IC[7:0]
Table 55. PWM auto-reload timer register map and reset values
Address (Hex.) Register label
7
6
5
4
3
2
1
0
PWMDCR3
0073h
DC7
0
DC6 DC5 DC4
DC3
0
DC2
0
DC1
0
DC0
0
Reset value
0
0
0
PWMDCR2
0074h
DC7
0
DC6 DC5 DC4
DC3
0
DC2
0
DC1
0
DC0
0
Reset value
0
0
0
PWMDCR1
0075h
DC7
0
DC6 DC5 DC4
DC3
0
DC2
0
DC1
0
DC0
0
Reset value
0
0
0
PWMDCR0
0076h
DC7
0
DC6 DC5 DC4
DC3
0
DC2
0
DC1
0
DC0
0
Reset value
0
0
0
PWMCR
0077h
OE3
0
OE2 OE1 OE0
OP3
0
OP2
0
OP1
0
OP0
0
Reset value
0
0
0
ARTCSR
0078h
EXCL
0
CC2 CC1 CC0
TCE
0
FCRL
0
RIE
0
OVF
0
Reset value
0
0
0
ARTCAR
0079h
CA7
0
CA6
0
CA5
0
CA4
0
CA3
0
CA2
0
CA1
0
CA0
0
Reset value
ARTARR
007Ah
AR7
0
AR6
0
AR5
0
AR4
0
AR3
0
AR2
0
AR1
0
AR0
0
Reset value
ARTICCSR
007Bh
CS2
0
CS1
0
CIE2
0
CIE1
0
CF2
0
CF1
0
Reset value
0
0
ARTICR1
007Ch
IC7
0
IC6
0
IC5
0
IC4
0
IC3
0
IC2
0
IC1
0
IC0
0
Reset value
ARTICR2
007Dh
IC7
0
IC6
0
IC5
0
IC4
0
IC3
0
IC2
0
IC1
0
IC0
0
Reset value
106/250
ST72325xxx-Auto
16-bit timer
13
16-bit timer
13.1
Introduction
The timer consists of a 16-bit free-running counter driven by a programmable prescaler.
It may be used for a variety of purposes, including pulse length measurement of up to two
input signals (input capture) or generation of up to two output waveforms (output compare
and PWM).
Pulse lengths and waveform periods can be modulated from a few microseconds to several
milliseconds using the timer prescaler and the CPU clock prescaler.
Some ST7 devices have two on-chip 16-bit timers. They are completely independent, and
do not share any resources. They are synchronized after an MCU reset as long as the timer
clock frequencies are not modified.
This description covers one or two 16-bit timers. In ST7 devices with two timers, register
names are prefixed with TA (Timer A) or TB (Timer B).
13.2
Main features
●
●
●
Programmable prescaler: f
divided by 2, 4 or 8
CPU
Overflow status flag and maskable interrupt
External clock input (must be at least four times slower than the CPU clock speed) with
the choice of active edge
●
1 or 2 Output Compare functions each with:
–
–
–
–
2 dedicated 16-bit registers
2 dedicated programmable signals
2 dedicated status flags
1 dedicated maskable interrupt
●
1 or 2 Input Capture functions each with:
–
–
–
–
2 dedicated 16-bit registers
2 dedicated active edge selection signals
2 dedicated status flags
1 dedicated maskable interrupt
●
●
●
●
Pulse Width Modulation mode (PWM)
One Pulse mode
Reduced Power mode
(a)
5 alternate functions on I/O ports (ICAP1, ICAP2, OCMP1, OCMP2, EXTCLK)
The block diagram is shown in Figure 43.
Note:
When reading an input signal on a non-bonded pin, the value will always be ‘1’.
a. Some timer pins may not be available (not bonded) in some ST7 devices. Refer to the device pinout
description.
107/250
16-bit timer
ST72325xxx-Auto
13.3
Functional description
13.3.1
Counter
The main block of the Programmable Timer is a 16-bit free running upcounter and its
associated 16-bit registers. The 16-bit registers are made up of two 8-bit registers called
high and low.
Counter Register (CR)
●
Counter High Register (CHR) is the most significant byte (MS Byte)
Counter Low Register (CLR) is the least significant byte (LS Byte)
●
Alternate Counter Register (ACR)
●
Alternate Counter High Register (ACHR) is the most significant byte (MS Byte)
Alternate Counter Low Register (ACLR) is the least significant byte (LS Byte)
●
These two read-only 16-bit registers contain the same value but with the difference that
reading the ACLR register does not clear the TOF bit (Timer overflow flag), located in the
Status register (SR) (see note at the end of paragraph entitled 16-bit read sequence).
Writing in the CLR register or ACLR register resets the free running counter to the FFFCh
value.
Both counters have a reset value of FFFCh (this is the only value which is reloaded in the
16-bit timer). The reset value of both counters is also FFFCh in One Pulse mode and PWM
mode.
The timer clock depends on the clock control bits of the CR2 register, as illustrated in
Table 61: Timer clock selection. The value in the counter register repeats every 131072,
262144 or 524288 CPU clock cycles depending on the CC[1:0] bits.
The timer frequency can be f
/2, f
/4, f
/8 or an external frequency.
CPU
CPU
CPU
108/250
ST72325xxx-Auto
16-bit timer
Figure 43. Timer block diagram
ST7 INTERNAL BUS
fCPU
MCU-PERIPHERAL INTERFACE
8 low
8 high
8-bit
buffer
8
8
8
8
8
8
8
8
EXEDG
16
INPUT
CAPTURE
REGISTER
INPUT
CAPTURE
REGISTER
OUTPUT
COMPARE
REGISTER REGISTER
OUTPUT
COMPARE
1/2
1/4
1/8
COUNTER
REGISTER
1
1
2
2
ALTERNATE
COUNTER
REGISTER
EXTCLK
pin
16
16
16
CC[1:0]
TIMER INTERNAL BUS
16
16
OVERFLOW
DETECT
CIRCUIT
EDGE DETECT
CIRCUIT1
OUTPUT COMPARE
CIRCUIT
ICAP1
pin
6
EDGE DETECT
CIRCUIT2
ICAP2
pin
LATCH1
LATCH2
OCMP1
pin
ICF1 OCF1 TOF ICF2 OCF2 TIMD
0
0
(Control/Status Register)
OCMP2
pin
CSR
ICIE OCIE TOIE FOLV2 FOLV1OLVL2 IEDG1 OLVL1
OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG
(Control Register 1) CR1
(Control Register 2) CR2
(1)
TIMER INTERRUPT
1. If IC, OC and TO interrupt request have separate vectors, then the last OR is not present (see device interrupt vector table).
109/250
16-bit timer
ST72325xxx-Auto
16-bit read sequence
The 16-bit read sequence (from either the Counter Register or the Alternate Counter
Register) is illustrated in Figure 44.
Figure 44. 16-bit read sequence
Beginning of the sequence
Read
MS Byte
LS Byte
is buffered
At t0
Other
instructions
Returns the buffered
LS Byte value at t0
Read
LS Byte
At t0 +Dt
Sequence completed
The user must read the MS Byte first; the LS Byte value is then buffered automatically.
This buffered value remains unchanged until the 16-bit read sequence is completed, even if
the user reads the MS Byte several times.
After a complete reading sequence, if only the CLR register or ACLR register are read, they
return the LS Byte of the count value at the time of the read.
Whatever timer mode is used (input capture, output compare, one pulse mode or PWM
mode) an overflow occurs when the counter rolls over from FFFFh to 0000h, after which
●
the TOF bit of the SR register is set
a timer interrupt is generated if
●
–
–
the TOIE bit of the CR1 register is set and
the I bit of the CC register is cleared
If one of these conditions is false, the interrupt remains pending to be issued as soon as
they are both true.
Clearing the overflow interrupt request is done in two steps:
1. Reading the SR register while the TOF bit is set
2. An access (read or write) to the CLR register
Note:
The TOF bit is not cleared by accesses to ACLR register. The advantage of accessing the
ACLR register rather than the CLR register is that it allows simultaneous use of the overflow
function and reading the free running counter at random times (for example, to measure
elapsed time) without the risk of clearing the TOF bit erroneously.
The timer is not affected by Wait mode.
In Halt mode, the counter stops counting until the mode is exited. Counting then resumes
from the previous count (MCU awakened by an interrupt) or from the reset count (MCU
awakened by a Reset).
110/250
ST72325xxx-Auto
16-bit timer
13.3.2
External clock
The external clock (where available) is selected if CC0 = 1 and CC1 = 1 in the CR2 register.
The status of the EXEDG bit in the CR2 register determines the type of level transition on
the external clock pin EXTCLK that will trigger the free running counter.
The counter is synchronized with the falling edge of the internal CPU clock.
A minimum of four falling edges of the CPU clock must occur between two consecutive
active edges of the external clock; thus, the external clock frequency must be less than a
quarter of the CPU clock frequency.
Figure 45. Counter timing diagram, internal clock divided by 2
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
FFFD FFFE FFFF 0000 0001 0002 0003
COUNTER REGISTER
TIMER OVERFLOW FLAG (TOF)
Figure 46. Counter timing diagram, internal clock divided by 4
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
FFFC
FFFD
0000
0001
COUNTER REGISTER
TIMER OVERFLOW FLAG (TOF)
Figure 47. Counter timing diagram, internal clock divided by 8
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
0000
FFFC
FFFD
COUNTER REGISTER
TIMER OVERFLOW FLAG (TOF)
Note:
The MCU is in reset state when the internal reset signal is high; when it is low the MCU is
running.
111/250
16-bit timer
ST72325xxx-Auto
13.3.3
Input capture
In this section, the index, i, may be 1 or 2 because there are two input capture functions in
the 16-bit timer.
The two 16-bit input capture registers (IC1R and IC2R) are used to latch the value of the
free running counter after a transition is detected on the ICAPi pin (see Figure 48).
MS Byte
LS Byte
ICiR
ICiHR
ICiLR
ICiR register is a read-only register.
The active transition is software programmable through the IEDGi bit of Control Registers
(CRi).
Timing resolution is one count of the free running counter: (f
Procedure:
/CC[1:0]).
CPU
To use the input capture function select the following in the CR2 register:
●
Select the timer clock (CC[1:0]) (see Table 61: Timer clock selection).
●
Select the edge of the active transition on the ICAP2 pin with the IEDG2 bit (the ICAP2
pin must be configured as floating input or input with pull-up without interrupt if this
configuration is available).
And select the following in the CR1 register:
●
Set the ICIE bit to generate an interrupt after an input capture coming from either the
ICAP1 pin or the ICAP2 pin
●
Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the
ICAP1pin must be configured as floating input or input with pull-up without interrupt if
this configuration is available).
When an input capture occurs:
●
ICFi bit is set.
●
The ICiR register contains the value of the free running counter on the active transition
on the ICAPi pin (see Figure 49).
●
A timer interrupt is generated if the ICIE bit is set and the I bit is cleared in the CC
register. Otherwise, the interrupt remains pending until both conditions become true.
Clearing the input capture interrupt request (that is, clearing the ICFi bit) is done in two
steps:
1. Reading the SR register while the ICFi bit is set
2. An access (read or write) to the ICiLR register
Note:
1
2
3
4
After reading the ICiHR register, transfer of input capture data is inhibited and ICFi will never
be set until the ICiLR register is also read.
The ICiR register contains the free running counter value which corresponds to the most
recent input capture.
The two input capture functions can be used together even if the timer also uses the two
output compare functions.
In One pulse Mode and PWM mode only Input Capture 2 can be used.
112/250
ST72325xxx-Auto
16-bit timer
5
6
7
8
The alternate inputs (ICAP1 and ICAP2) are always directly connected to the timer. So any
transitions on these pins activates the input capture function.
Moreover if one of the ICAPi pins is configured as an input and the second one as an output,
an interrupt can be generated if the user toggles the output pin and if the ICIE bit is set.
This can be avoided if the input capture function i is disabled by reading the ICiHR (see note
1).
The TOF bit can be used with interrupt generation in order to measure events that go
beyond the timer range (FFFFh).
Figure 48. Input capture block diagram
ICAP1
pin
(Control Register 1) CR1
EDGE DETECT
CIRCUIT1
EDGE DETECT
CIRCUIT2
ICIE
IEDG1
ICAP2
pin
(Status Register) SR
IC2R Register
IC1R Register
ICF1
ICF2
0
0
0
(Control Register 2) CR2
16-BIT
16-BIT FREE RUNNING
COUNTER
CC1
CC0 IEDG2
Figure 49. Input capture timing diagram
TIMER CLOCK
FF01
FF02
FF03
COUNTER REGISTER
ICAPi PIN
ICAPi FLAG
FF03
ICAPi REGISTER
Note: The rising edge is the active edge.
113/250
16-bit timer
ST72325xxx-Auto
13.3.4
Output compare
In this section, the index, i, may be 1 or 2 because there are two output compare functions in
the 16-bit timer.
This function can be used to control an output waveform or indicate when a period of time
has elapsed.
When a match is found between the Output Compare register and the free running counter,
the output compare function:
●
●
●
Assigns pins with a programmable value if the OCiE bit is set
Sets a flag in the status register
Generates an interrupt if enabled
Two 16-bit registers Output Compare Register 1 (OC1R) and Output Compare Register 2
(OC2R) contain the value to be compared to the counter register each timer clock cycle.
MS byte
LS byte
OCiR
OCiHR
OCiLR
These registers are readable and writable and are not affected by the timer hardware. A
reset event changes the OCiR value to 8000h.
Timing resolution is one count of the free running counter: (f
).
CPU/CC[1:0]
Procedure
To use the output compare function, select the following in the CR2 register:
●
Set the OCiE bit if an output is needed then the OCMPi pin is dedicated to the output
compare i signal.
●
Select the timer clock (CC[1:0]) (see Table 61: Timer clock selection).
And select the following in the CR1 register:
●
Select the OLVLi bit to applied to the OCMPi pins after the match occurs.
●
Set the OCIE bit to generate an interrupt if it is needed.
When a match is found between OCRi register and CR register:
●
●
●
OCFi bit is set.
The OCMPi pin takes OLVLi bit value (OCMPi pin latch is forced low during reset).
A timer interrupt is generated if the OCIE bit is set in the CR1 register and the I bit is
cleared in the CC register (CC).
The OCiR register value required for a specific timing application can be calculated using
the following formula:
∆t f
* CPU
PRESC
∆ OCiR =
Where:
∆t
= Output compare period (in seconds)
= CPU clock frequency (in hertz)
f
CPU
PRESC = Timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits; see Table 61:
Timer clock selection)
114/250
ST72325xxx-Auto
16-bit timer
If the timer clock is an external clock, the formula is:
∆ OCiR = ∆t f
* EXT
Where:
∆t
= Output compare period (in seconds)
f
= External timer clock frequency (in hertz)
CPU
Clearing the output compare interrupt request (that is, clearing the OCFi bit) is done by:
1. Reading the SR register while the OCFi bit is set
2. An access (read or write) to the OCiLR register
The following procedure is recommended to prevent the OCFi bit from being set between
the time it is read and the write to the OCiR register:
●
Write to the OCiHR register (further compares are inhibited).
●
Read the SR register (first step of the clearance of the OCFi bit, which may be already
set).
●
Write to the OCiLR register (enables the output compare function and clears the OCFi
bit).
Note:
1
2
3
After a processor write cycle to the OCiHR register, the output compare function is inhibited
until the OCiLR register is also written.
If the OCiE bit is not set, the OCMPi pin is a general I/O port and the OLVLi bit will not
appear when a match is found but an interrupt could be generated if the OCIE bit is set.
In both internal and external clock modes, OCFi and OCMPi are set while the counter value
equals the OCiR register value (see Figure 51 on page 116 for an example with f
/2 and
CPU
Figure 52 on page 116 for an example with f
PWM mode.
/4). This behavior is the same in OPM or
CPU
4
5
The output compare functions can be used both for generating external events on the
OCMPi pins even if the input capture mode is also used.
The value in the 16-bit OCiR register and the OLVi bit should be changed after each
successful comparison in order to control an output waveform or establish a new elapsed
timeout.
13.3.5
Forced compare output capability
When the FOLVi bit is set by software, the OLVLi bit is copied to the OCMPi pin. The OLVi bit
has to be toggled in order to toggle the OCMPi pin when it is enabled (OCiE bit = 1). The
OCFi bit is then not set by hardware, and thus no interrupt request is generated.
The FOLVLi bits have no effect in both one pulse mode and PWM mode.
115/250
16-bit timer
ST72325xxx-Auto
Figure 50. Output compare block diagram
16-BIT FREE RUNNING
COUNTER
OC1E OC2E
CC1 CC0
(Control Register 2) CR2
16-bit
(Control Register 1) CR1
FOLV2 FOLV1 OLVL2 OLVL1
OUTPUT COMPARE
CIRCUIT
Latch
1
OCIE
OCMP1
pin
16-bit
OC1R Register
16-bit
Latch
2
OCMP2
pin
OCF1
OCF2
0
0
0
OC2R Register
(Status Register) SR
Figure 51. Output compare timing diagram, f
= f
/2
CPU
TIMER
INTERNAL CPU CLOCK
TIMER CLOCK
COUNTER REGISTER
2ECF 2ED0 2ED1 2ED2
2ED3
2ED4
2ED3
OUTPUT COMPARE REGISTER i (OCRi)
OUTPUT COMPARE FLAG i (OCFi)
OCMPi PIN (OLVLi = 1)
Figure 52. Output compare timing diagram, f
= f
/4
CPU
TIMER
INTERNAL CPU CLOCK
TIMER CLOCK
2ECF 2ED0 2ED1 2ED2
2ED3
2ED4
2ED3
COUNTER REGISTER
OUTPUT COMPARE REGISTER i (OCRi)
OUTPUT COMPARE FLAG i (OCFi)
OCMPi PIN (OLVLi = 1)
116/250
ST72325xxx-Auto
16-bit timer
13.3.6
One Pulse mode
One Pulse mode enables the generation of a pulse when an external event occurs. This
mode is selected via the OPM bit in the CR2 register.
The one pulse mode uses the Input Capture1 function and the Output Compare1 function.
Procedure
To use one pulse mode:
1. Load the OC1R register with the value corresponding to the length of the pulse (using
the appropriate formula below according to the timer clock source used).
2. Select the following in the CR1 register:
–
–
–
Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after the
pulse.
Using the OLVL2 bit, select the level to be applied to the OCMP1 pin during the
pulse.
Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the
ICAP1 pin must be configured as floating input).
3. Select the following in the CR2 register:
–
Set the OC1E bit, the OCMP1 pin is then dedicated to the Output Compare 1
function.
–
–
Set the OPM bit.
Select the timer clock CC[1:0] (see Table 61: Timer clock selection).
Then, on a valid event on the ICAP1 pin, the counter is initialized to FFFCh and OLVL2 bit is
loaded on the OCMP1 pin, the ICF1 bit is set and the value FFFDh is loaded in the IC1R
register.
Figure 53. One pulse mode cycle flowchart
ICR1 = Counter
OCMP1 = OLVL2
When event occurs
on ICAP1
Counter is reset
to FFFCh
ICF1 bit is set
When counter = OC1R
OCMP1 = OLVL1
Because the ICF1 bit is set when an active edge occurs, an interrupt can be generated if the
ICIE bit is set.
Clearing the input capture interrupt request (that is, clearing the ICFi bit) is done in two
steps:
1. Reading the SR register while the ICFi bit is set
2. An access (read or write) to the ICiLR register
117/250
16-bit timer
ST72325xxx-Auto
The OC1R register value required for a specific timing application can be calculated using
the following formula:
t f
* CPU - 5
PRESC
OCiR value =
Where:
t
= Pulse period (in seconds)
= CPU clock frequency (in hertz)
f
CPU
PRESC = Timer prescaler factor (2, 4 or 8 depending on the CC[1:0] bits; see Table 61:
Timer clock selection)
If the timer clock is an external clock the formula is:
OCiR = t f
- 5
* EXT
Where:
t
= Pulse period (in seconds)
= External clock frequency (in hertz)
f
EXT
When the value of the counter is equal to the value of the contents of the OC1R register, the
OLVL1 bit is output on the OCMP1 pin (see Figure 54).
Note:
1
2
The OCF1 bit cannot be set by hardware in one pulse mode but the OCF2 bit can generate
an Output Compare interrupt.
When the Pulse Width Modulation (PWM) and One Pulse Mode (OPM) bits are both set, the
PWM mode is the only active one.
3
4
If OLVL1 = OLVL2 a continuous signal will be seen on the OCMP1 pin.
The ICAP1 pin cannot be used to perform input capture. The ICAP2 pin can be used to
perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take
care that the counter is reset each time a valid edge occurs on the ICAP1 pin and ICF1 can
also generates interrupt if ICIE is set.
5
When one pulse mode is used OC1R is dedicated to this mode. Nevertheless OC2R and
OCF2 can be used to indicate a period of time has been elapsed but cannot generate an
output waveform because the level OLVL2 is dedicated to the one pulse mode.
Figure 54. One pulse mode timing example
2ED3
01F8
IC1R
FFFC FFFD FFFE
2ED0 2ED1 2ED2
2ED3
FFFC FFFD
01F8
COUNTER
ICAP1
OLVL2
OLVL1
OLVL2
OCMP1
compare1
Note: IEDG1 = 1, OC1R = 2ED0h, OLVL1 = 0, OLVL2 = 1
118/250
ST72325xxx-Auto
16-bit timer
Figure 55. Pulse width modulation mode timing example with 2 output compare
functions
2ED0 2ED1 2ED2
34E2 FFFC
FFFC FFFD FFFE
34E2
COUNTER
OCMP1
OLVL2
OLVL1
OLVL2
compare2
compare1
compare2
Note: OC1R = 2ED0h, OC2R = 34E2, OLVL1 = 0, OLVL2 = 1
Note:
On timers with only one Output Compare register, a fixed frequency PWM signal can be
generated using the output compare and the counter overflow to define the pulse length.
13.3.7
Pulse width modulation mode
Pulse Width Modulation (PWM) mode enables the generation of a signal with a frequency
and pulse length determined by the value of the OC1R and OC2R registers.
Pulse Width Modulation mode uses the complete Output Compare 1 function plus the
OC2R register, and so this functionality cannot be used when PWM mode is activated.
In PWM mode, double buffering is implemented on the output compare registers. Any new
values written in the OC1R and OC2R registers are taken into account only at the end of the
PWM period (OC2) to avoid spikes on the PWM output pin (OCMP1).
Procedure
To use pulse width modulation mode:
1. Load the OC2R register with the value corresponding to the period of the signal using
the appropriate formula below according to the timer clock source used.
2. Load the OC1R register with the value corresponding to the period of the pulse if
OLVL1 = 0 and OLVL2 = 1 using the appropriate formula below according to the timer
clock source used.
3. Select the following in the CR1 register:
–
Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after a
successful comparison with the OC1R register.
–
Using the OLVL2 bit, select the level to be applied to the OCMP1 pin after a
successful comparison with the OC2R register.
4. Select the following in the CR2 register:
–
–
–
Set OC1E bit: the OCMP1 pin is then dedicated to the output compare 1 function.
Set the PWM bit.
Select the timer clock (CC[1:0]) (see Table 61: Timer clock selection).
119/250
16-bit timer
ST72325xxx-Auto
Figure 56. Pulse width modulation cycle flowchart
When
Counter
= OC1R
OCMP1 = OLVL1
OCMP1 = OLVL2
When
Counter
= OC2R
Counter is reset
to FFFCh
ICF1 bit is set
If OLVL1 = 1 and OLVL2 = 0 the length of the positive pulse is the difference between the
OC2R and OC1R registers.
If OLVL1 = OLVL2 a continuous signal will be seen on the OCMP1 pin.
The OCiR register value required for a specific timing application can be calculated using
the following formula:
t f
* CPU - 5
PRESC
OCiR value =
Where:
t
= Signal or pulse period (in seconds)
= CPU clock frequency (in hertz)
f
CPU
PRESC = Timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits; see Table 61:
Timer clock selection)
If the timer clock is an external clock the formula is:
OCiR = t f
-5
* EXT
Where:
t
= Signal or pulse period (in seconds)
= External timer clock frequency (in hertz)
f
EXT
The Output Compare 2 event causes the counter to be initialized to FFFCh (see Figure 55).
Note:
1
2
3
4
After a write instruction to the OCiHR register, the output compare function is inhibited until
the OCiLR register is also written.
The OCF1 and OCF2 bits cannot be set by hardware in PWM mode therefore the Output
Compare interrupt is inhibited.
The ICF1 bit is set by hardware when the counter reaches the OC2R value and can produce
a timer interrupt if the ICIE bit is set and the I bit is cleared.
In PWM mode the ICAP1 pin cannot be used to perform input capture because it is
disconnected to the timer. The ICAP2 pin can be used to perform input capture (ICF2 can be
set and IC2R can be loaded) but the user must take care that the counter is reset each
period and ICF1 can also generates interrupt if ICIE is set.
5
When the Pulse Width Modulation (PWM) and One Pulse Mode (OPM) bits are both set, the
PWM mode is the only active one.
120/250
ST72325xxx-Auto
16-bit timer
13.4
Low power modes
Table 56. Effect of low power modes on 16-bit timer
Mode
Effect
No effect on 16-bit timer.
Timer interrupts cause the device to exit from Wait mode.
Wait
16-bit timer registers are frozen.
In Halt mode, the counter stops counting until Halt mode is exited. Counting resumes from
the previous count when the MCU is woken up by an interrupt with “exit from Halt mode”
capability or from the counter reset value when the MCU is woken up by a RESET.
If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is
armed. Consequently, when the MCU is woken up by an interrupt with “exit from Halt
mode” capability, the ICFi bit is set, and the counter value present when exiting from Halt
mode is captured into the ICiR register.
Halt
13.5
Interrupts
Table 57. 16-bit timer interrupt control/wake-up capability
Enable
control
bit
Exit
from
Wait
Exit
from
Halt
Event
flag
Interrupt event
Input Capture 1 event/Counter reset in PWM mode
Input Capture 2 event
ICF1
ICF2
OCF1
OCF2
TOF
ICIE
Output Compare 1 event (not available in PWM mode)
Output Compare 2 event (not available in PWM mode)
Timer Overflow event
Yes
No
OCIE
TOIE
Note:
The 16-bit timer interrupt events are connected to the same interrupt vector (see Chapter 7:
Interrupts on page 59). These events generate an interrupt if the corresponding Enable
Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction).
13.6
Summary of timer modes
Table 58. Timer modes
Timer resources
Modes
Input
Input
Output
Output
Capture 1
Capture 2
Compare 1
Compare 2
Input Capture
(1 and/or 2)
Yes
Yes
Yes
Yes
Output Compare
(1 and/or 2)
121/250
16-bit timer
ST72325xxx-Auto
Table 58. Timer modes
Timer resources
Modes
Input
Input
Output
Output
Capture 1
Capture 2
Compare 1
Compare 2
Not
One Pulse mode
No
Partially(2)
No
recommended(1)
No
Not
PWM mode
recommended(3)
1. See Note 4 in Section 13.3.6 One Pulse mode
2. See Note 5 in Section 13.3.6 One Pulse mode
3. See Note 4 in Section 13.3.7 Pulse width modulation mode
13.7
16-bit timer registers
Each timer is associated with 3 control and status registers, and with 6 pairs of data
registers (16-bit values) relating to the 2 input captures, the 2 output compares, the counter
and the alternate counter.
13.7.1
Control register 1 (CR1)
CR1
Reset value: 0000 0000 (00h)
7
6
5
4
3
2
1
0
ICIE
RW
OCIE
TOIE
FOLV2
FOLV1
OLVL2
IEDG1
OLVL1
RW
RW
RW
RW
RW
RW
RW
Table 59. CR1 register description
Bit Name
Function
Input Capture Interrupt Enable
0: Interrupt is inhibited
7
ICIE
1: A timer interrupt is generated whenever the ICF1 or ICF2 bit of the SR register is
set.
Output Compare Interrupt Enable
0: Interrupt is inhibited
1: A timer interrupt is generated whenever the OCF1 or OCF2 bit of the SR register
is set.
6
5
OCIE
TOIE
Timer Overflow Interrupt Enable
0: Interrupt is inhibited
1: A timer interrupt is enabled whenever the TOF bit of the SR register is set.
Forced Output Compare 2
This bit is set and cleared by software.
0: No effect on the OCMP2 pin
4
FOLV2
1: Forces the OLVL2 bit to be copied to the OCMP2 pin, if the OC2E bit is set and
even if there is no successful comparison
122/250
ST72325xxx-Auto
16-bit timer
Table 59. CR1 register description (continued)
Bit Name Function
Forced Output Compare 1
This bit is set and cleared by software.
0: No effect on the OCMP1 pin
1: Forces OLVL1 to be copied to the OCMP1 pin, if the OC1E bit is set and even if
there is no successful comparison
3
2
FOLV1
OLVL2
Output Level 2
This bit is copied to the OCMP2 pin whenever a successful comparison occurs with
the OC2R register and OCxE is set in the CR2 register. This value is copied to the
OCMP1 pin in One Pulse Mode and Pulse Width Modulation mode.
Input Edge 1
This bit determines which type of level transition on the ICAP1 pin will trigger the
capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
1
0
IEDG1
OLVL1
Output Level 1
The OLVL1 bit is copied to the OCMP1 pin whenever a successful comparison
occurs with the OC1R register and the OC1E bit is set in the CR2 register.
13.7.2
Control register 2 (CR2)
CR2
Reset value: 0000 0000 (00h)
7
6
5
4
3
2
1
0
OC1E
OC2E
OPM
PWM
CC[1:0]
RW
IEDG2
EXEDG
RW
RW
RW
RW
RW
RW
Table 60. CR2 register description
Bit Name
Function
Output Compare 1 Pin Enable
This bit is used only to output the signal from the timer on the OCMP1 pin (OLV1 in
Output Compare mode, both OLV1 and OLV2 in PWM and one-pulse mode).
Whatever the value of the OC1E bit, the Output Compare 1 function of the timer
remains active.
0: OCMP1 pin alternate function disabled (I/O pin free for general-purpose I/O)
1: OCMP1 pin alternate function enabled
7
6
OC1E
OC2E
Output Compare 2 Pin Enable
This bit is used only to output the signal from the timer on the OCMP2 pin (OLV2 in
Output Compare mode). Whatever the value of the OC2E bit, the Output Compare
2 function of the timer remains active.
0: OCMP2 pin alternate function disabled (I/O pin free for general-purpose I/O)
1: OCMP2 pin alternate function enabled
123/250
16-bit timer
ST72325xxx-Auto
Table 60. CR2 register description (continued)
Bit Name Function
One Pulse Mode
0: One Pulse Mode is not active.
5
4
OPM
PWM
1: One Pulse Mode is active, the ICAP1 pin can be used to trigger one pulse on the
OCMP1 pin; the active transition is given by the IEDG1 bit. The length of the
generated pulse depends on the contents of the OC1R register.
Pulse Width Modulation
0: PWM mode is not active.
1: PWM mode is active, the OCMP1 pin outputs a programmable cyclic signal; the
length of the pulse depends on the value of OC1R register; the period depends on
the value of OC2R register.
Clock Control
3:2 CC[1:0]
The timer clock mode depends on these bits (see Table 61).
Input Edge 2
This bit determines which type of level transition on the ICAP2 pin will trigger the
capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
1
0
IEDG2
External Clock Edge
This bit determines which type of level transition on the external clock pin EXTCLK
will trigger the counter register.
EXEDG
0: A falling edge triggers the counter register.
1: A rising edge triggers the counter register.
Table 61. Timer clock selection
Timer clock
CC1
CC0
f
f
f
CPU / 4
CPU / 2
CPU / 8
0
0
1
1
0
1
0
1
External clock (where available)(1)
1. If the external clock pin is not available, programming the external clock configuration stops the counter.
13.7.3
Control/status register (CSR)
CSR
Reset value: xxxx x0xx (xxh)
7
6
5
4
3
2
1
0
ICF1
RO
OCF1
TOF
ICF2
OCF2
TIMD
Reserved
-
RO
RO
RO
RO
RW
124/250
ST72325xxx-Auto
16-bit timer
Table 62. CSR register description
Bit
Name
Function
Input Capture Flag 1
0: No input capture (reset value)
7
ICF1
1: An input capture has occurred on the ICAP1 pin or the counter has reached the
OC2R value in PWM mode. To clear this bit, first read the SR register, then read
or write the low byte of the IC1R (IC1LR) register.
Output Compare Flag 1
0: No match (reset value)
6
OCF1
1: The content of the free running counter has matched the content of the OC1R
register. To clear this bit, first read the SR register, then read or write the low byte
of the OC1R (OC1LR) register.
Timer Overflow Flag
0: No timer overflow (reset value)
5
4
3
TOF
ICF2
OCF2
1: The free running counter rolled over from FFFFh to 0000h. To clear this bit, first
read the SR register, then read or write the low byte of the CR (CLR) register.
Note: Reading or writing the ACLR register does not clear TOF.
Input Capture Flag 2
0: No input capture (reset value).
1: An input capture has occurred on the ICAP2 pin. To clear this bit, first read the
SR register, then read or write the low byte of the IC2R (IC2LR) register.
Output Compare Flag 2
0: No match (reset value)
1: The content of the free running counter has matched the content of the OC2R
register. To clear this bit, first read the SR register, then read or write the low byte
of the OC2R (OC2LR) register.
Timer disable
This bit is set and cleared by software. When set, it freezes the timer prescaler
and counter and disabled the output functions (OCMP1 and OCMP2 pins) to
reduce power consumption. Access to the timer registers is still available, allowing
the timer configuration to be changed, or the counter reset, while it is disabled.
0: Timer enabled
2
TIMD
1: Timer prescaler, counter and outputs disabled
1:0
-
Reserved, must be kept cleared
13.7.4
Input capture 1 high register (IC1HR)
This is an 8-bit read only register that contains the high part of the counter value (transferred
by the input capture 1 event).
IC1HR
7
Reset value: Undefined
6
5
4
3
2
1
0
MSB
RO
LSB
RO
RO
RO
RO
RO
RO
RO
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16-bit timer
ST72325xxx-Auto
13.7.5
Input capture 1 low register (IC1LR)
This is an 8-bit read only register that contains the low part of the counter value (transferred
by the input capture 1 event).
IC1LR
7
Reset value: Undefined
6
5
4
3
2
1
0
MSB
RO
LSB
RO
RO
RO
RO
RO
RO
RO
13.7.6
13.7.7
13.7.8
Output compare 1 high register (OC1HR)
This is an 8-bit register that contains the high part of the value to be compared to the CHR
register.
OC1HR
7
Reset value: 1000 0000 (80h)
6
5
4
3
2
1
0
MSB
RW
LSB
RW
RW
RW
RW
RW
RW
RW
Output compare 1 low register (OC1LR)
This is an 8-bit register that contains the low part of the value to be compared to the CLR
register.
OC1LR
7
Reset value: 0000 0000 (00h)
6
5
4
3
2
1
0
MSB
RW
LSB
RW
RW
RW
RW
RW
RW
RW
Output compare 2 high register (OC2HR)
This is an 8-bit register that contains the high part of the value to be compared to the CHR
register.
OC2HR
7
Reset value: 1000 0000 (80h)
6
5
4
3
2
1
0
MSB
RW
LSB
RW
RW
RW
RW
RW
RW
RW
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16-bit timer
13.7.9
Output compare 2 low register (OC2LR)
This is an 8-bit register that contains the low part of the value to be compared to the CLR
register.
OC2LR
7
Reset value: 0000 0000 (00h)
6
5
4
3
2
1
0
MSB
RW
LSB
RW
RW
RW
RW
RW
RW
RW
13.7.10 Counter high register (CHR)
This is an 8-bit register that contains the high part of the counter value.
CHR Reset value: 1111 1111 (FFh)
7
6
5
4
3
2
1
0
MSB
RO
LSB
RO
RO
RO
RO
RO
RO
RO
13.7.11 Counter low register (CLR)
This is an 8-bit register that contains the low part of the counter value. A write to this register
resets the counter. An access to this register after accessing the CSR register clears the
TOF bit.
CLR
Reset value: 1111 1100 (FCh)
7
6
5
4
3
2
1
0
MSB
RO
LSB
RO
RO
RO
RO
RO
RO
RO
13.7.12 Alternate counter high register (ACHR)
This is an 8-bit register that contains the high part of the counter value.
ACHR
7
Reset value: 1111 1111 (FFh)
6
5
4
3
2
1
0
MSB
RO
LSB
RO
RO
RO
RO
RO
RO
RO
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16-bit timer
ST72325xxx-Auto
13.7.13 Alternate counter low register (ACLR)
This is an 8-bit register that contains the low part of the counter value. A write to this register
resets the counter. An access to this register after an access to CSR register does not clear
the TOF bit in the CSR register.
ACLR
7
Reset value: 1111 1100 (FCh)
6
5
4
3
2
1
0
MSB
RO
LSB
RO
RO
RO
RO
RO
RO
RO
13.7.14 Input capture 2 high register (IC2HR)
This is an 8-bit read only register that contains the high part of the counter value (transferred
by the Input Capture 2 event).
IC2HR
7
Reset value: Undefined
6
5
4
3
2
1
0
MSB
RO
LSB
RO
RO
RO
RO
RO
RO
RO
13.7.15 Input capture 2 low register (IC2LR)
This is an 8-bit read only register that contains the low part of the counter value (transferred
by the Input Capture 2 event).
IC2LR
7
Reset value: Undefined
6
5
4
3
2
1
0
MSB
RO
LSB
RO
RO
RO
RO
RO
RO
RO
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ST72325xxx-Auto
16-bit timer
Table 63. 16-bit timer register map and reset values
Address
(Hex.)
Register
label
7
6
5
4
3
2
1
0
Timer A: 32 CR1
Timer B: 42 Reset value
ICIE
0
OCIE
0
TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
0
0
0
0
0
0
Timer A: 31 CR2
Timer B: 41 Reset value
OC1E OC2E
OPM
0
PWM
0
CC1
0
CC0 IEDG2 EXEDG
0
0
0
0
0
Timer A: 33 CSR
Timer B: 43 Reset value
ICF1
x
OCF1
x
TOF
x
ICF2
x
OCF2
x
TIMD
0
-
x
-
x
Timer A: 34 IC1HR
Timer B: 44 Reset value
MSB
x
LSB
x
x
x
0
0
0
0
1
1
1
1
x
x
x
x
0
0
0
0
1
1
1
1
x
x
x
x
0
0
0
0
1
1
1
1
x
x
x
x
0
0
0
0
1
1
1
1
x
x
x
x
0
0
0
0
1
1
1
1
x
x
x
x
0
0
0
0
1
0
1
0
x
x
Timer A: 35 IC1LR
Timer B: 45 Reset value
MSB
x
LSB
x
Timer A: 36 OC1HR
Timer B: 46 Reset value
MSB
1
LSB
0
Timer A: 37 OC1LR
Timer B: 47 Reset value
MSB
0
LSB
0
Timer A: 3E OC2HR
Timer B: 4E Reset value
MSB
1
LSB
0
Timer A: 3F OC2LR
Timer B: 4F Reset value
MSB
0
LSB
0
Timer A: 38 CHR
Timer B: 48 Reset value
MSB
1
LSB
1
Timer A: 39 CLR
Timer B: 49 Reset value
MSB
1
LSB
0
Timer A: 3A ACHR
Timer B: 4A Reset value
MSB
1
LSB
1
Timer A: 3B ACLR
Timer B: 4B Reset value
MSB
1
LSB
0
Timer A: 3C IC2HR
Timer B: 4C Reset value
MSB
x
LSB
x
Timer A: 3D IC2LR
Timer B: 4D Reset value
MSB
x
LSB
x
Related documentation
SCI software communications using 16-bit timer (AN 973)
Real-time Clock with ST7 Timer Output Compare (AN 974)
Driving a buzzer through the ST7 Timer PWM function (AN 976)
Using ST7 PWM signal to generate analog input (sinusoid) (AN1041)
UART emulation software (AN1046)
PWM duty cycle switch implementing true 0 or 100 per cent duty cycle (AN1078)
Starting a PWM signal directly at high level using the ST7 16-bit timer (AN1504)
129/250
Serial peripheral interface (SPI)
ST72325xxx-Auto
14
Serial peripheral interface (SPI)
14.1
Introduction
The Serial Peripheral Interface (SPI) allows full-duplex, synchronous, serial communication
with external devices. An SPI system may consist of a master and one or more slaves
however the SPI interface cannot be a master in a multimaster system.
14.2
Main features
●
●
●
●
●
●
●
●
●
Full duplex synchronous transfers (on 3 lines)
Simplex synchronous transfers (on 2 lines)
Master or slave operation
6 master mode frequencies (f
/4 max.)
CPU
f
/2 max. slave mode frequency (see note)
CPU
SS Management by software or hardware
Programmable clock polarity and phase
End of transfer interrupt flag
Write collision, Master Mode Fault and Overrun flags
Note:
In slave mode, continuous transmission is not possible at maximum frequency due to the
software overhead for clearing status flags and to initiate the next transmission sequence.
14.3
General description
Figure 57 shows the serial peripheral interface (SPI) block diagram. There are three
registers:
●
●
●
SPI Control Register (SPICR)
SPI Control/Status Register (SPICSR)
SPI Data Register (SPIDR)
The SPI is connected to external devices through four pins:
●
●
●
●
MISO (Master In / Slave Out data)
MOSI (Master Out / Slave In data)
SCK (Serial Clock out by SPI masters and input by SPI slaves)
SS (Slave select): This input signal acts as a ‘chip select’ to let the SPI master
communicate with slaves individually and to avoid contention on the data lines. Slave
SS inputs can be driven by standard I/O ports on the master MCU.
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Serial peripheral interface (SPI)
Figure 57. Serial peripheral interface block diagram
Data/Address Bus
Read
SPIDR
Interrupt
request
Read Buffer
MOSI
7
0
SPICSR
MISO
8-bit Shift Register
SPIF WCOL OVR MODF
0
SOD SSM
SSI
Write
SOD
bit
1
0
SS
SPI
STATE
SCK
CONTROL
7
SPICR
0
SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0
MASTER
CONTROL
SERIAL CLOCK
GENERATOR
SS
14.3.1
Functional description
A basic example of interconnections between a single master and a single slave is
illustrated in Figure 58.
The MOSI pins are connected together and the MISO pins are connected together. In this
way data is transferred serially between master and slave (most significant bit first).
The communication is always initiated by the master. When the master device transmits
data to a slave device via MOSI pin, the slave device responds by sending data to the
master device via the MISO pin. This implies full duplex communication with both data out
and data in synchronized with the same clock signal (which is provided by the master device
via the SCK pin).
To use a single data line, the MISO and MOSI pins must be connected at each node (in this
case only simplex communication is possible).
Four possible data/clock timing relationships may be chosen (see Figure 61) but master and
slave must be programmed with the same timing mode.
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Serial peripheral interface (SPI)
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Figure 58. Single master/single slave application
MASTER
SLAVE
MSBit
LSBit
MSBit
LSBit
MISO
MOSI
MISO
MOSI
8-BIT SHIFT REGISTER
8-BIT SHIFT REGISTER
SPI
CLOCK
GENERATOR
SCK
SS
SCK
SS
+5V
Not used if SS is managed
by software
14.3.2
Slave select management
As an alternative to using the SS pin to control the Slave Select signal, the application can
choose to manage the Slave Select signal by software. This is configured by the SSM bit in
the SPICSR register (see Figure 60)
In software management, the external SS pin is free for other application uses and the
internal SS signal level is driven by writing to the SSI bit in the SPICSR register.
In Master mode
●
SS internal must be held high continuously
In Slave mode
There are two cases depending on the data/clock timing relationship (see Figure 59):
If CPHA = 1 (data latched on 2nd clock edge):
●
SS internal must be held low during the entire transmission. This implies that in single
slave applications the SS pin either can be tied to V , or made free for standard I/O by
SS
managing the SS function by software (SSM = 1 and SSI = 0 in the in the SPICSR
register)
If CPHA = 0 (data latched on 1st clock edge):
●
SS internal must be held low during byte transmission and pulled high between each
byte to allow the slave to write to the shift register. If SS is not pulled high, a Write
Collision error will occur when the slave writes to the shift register (see Write collision
error (WCOL) on page 137).
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Figure 59. Generic SS timing diagram
Serial peripheral interface (SPI)
MOSI/MISO
Master SS
Byte 1
Byte 2
Byte 3
Slave SS
(if CPHA=0)
Slave SS
(if CPHA=1)
Figure 60. Hardware/Software slave select management
SSM bit
SSI bit
1
0
SS internal
SS external pin
14.3.3
Master mode operation
In master mode, the serial clock is output on the SCK pin. The clock frequency, polarity and
phase are configured by software (refer to the description of the SPICSR register).
Note:
The idle state of SCK must correspond to the polarity selected in the SPICSR register (by
pulling up SCK if CPOL = 1 or pulling down SCK if CPOL = 0).
How to operate the SPI in master mode
To operate the SPI in master mode, perform the following steps in order:
1. Write to the SPICR register:
a) Select the clock frequency by configuring the SPR[2:0] bits.
b) Select the clock polarity and clock phase by configuring the CPOL and CPHA bits.
Figure 61 shows the four possible configurations.
Note:
Note:
The slave must have the same CPOL and CPHA settings as the master.
2. Write to the SPICSR register:
Either set the SSM bit and set the SSI bit or clear the SSM bit and tie the SS pin high
for the complete byte transmit sequence.
3. Write to the SPICR register:
Set the MSTR and SPE bits
MSTR and SPE bits remain set only if SS is high).
IMPORTANT: If the SPICSR register is not written first, the SPICR register setting (MSTR
bit) may not be taken into account.
The transmit sequence begins when software writes a byte in the SPIDR register.
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Serial peripheral interface (SPI)
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14.3.4
Master mode transmit sequence
When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift
register and then shifted out serially to the MOSI pin most significant bit first.
When data transfer is complete:
–
–
The SPIF bit is set by hardware
An interrupt request is generated if the SPIE bit is set and the interrupt mask in the
CCR register is cleared.
Clearing the SPIF bit is performed by the following software sequence:
1. An access to the SPICSR register while the SPIF bit is set
2. A read to the SPIDR register.
Note:
While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR
register is read.
14.3.5
Slave mode operation
In slave mode, the serial clock is received on the SCK pin from the master device.
To operate the SPI in slave mode:
1. Write to the SPICSR register to perform the following actions:
a) Select the clock polarity and clock phase by configuring the CPOL and CPHA bits
(see Figure 61).
Note:
The slave must have the same CPOL and CPHA settings as the master.
b) Manage the SS pin as described in Slave select management on page 132 and
Figure 59. If CPHA = 1, SS must be held low continuously. If CPHA = 0, SS must
be held low during byte transmission and pulled up between each byte to let the
slave write in the shift register.
2. Write to the SPICR register to clear the MSTR bit and set the SPE bit to enable the SPI
I/O functions.
14.3.6
Slave mode transmit sequence
When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift
register and then shifted out serially to the MISO pin most significant bit first.
The transmit sequence begins when the slave device receives the clock signal and the most
significant bit of the data on its MOSI pin.
When data transfer is complete:
–
–
The SPIF bit is set by hardware.
An interrupt request is generated if SPIE bit is set and interrupt mask in the CCR
register is cleared.
Clearing the SPIF bit is performed by the following software sequence:
1. An access to the SPICSR register while the SPIF bit is set
2. A write or a read to the SPIDR register
Note:
While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR
register is read.
134/250
ST72325xxx-Auto
Serial peripheral interface (SPI)
The SPIF bit can be cleared during a second transmission; however, it must be cleared
before the second SPIF bit in order to prevent an Overrun condition (see Overrun condition
(OVR) on page 137).
14.4
Clock phase and clock polarity
Four possible timing relationships may be chosen by software, using the CPOL and CPHA
bits (see Figure 61).
Note:
The idle state of SCK must correspond to the polarity selected in the SPICSR register (by
pulling up SCK if CPOL = 1 or pulling down SCK if CPOL = 0).
The combination of the CPOL clock polarity and CPHA (clock phase) bits selects the data
capture clock edge
Figure 61 shows an SPI transfer with the four combinations of the CPHA and CPOL bits.
The diagram may be interpreted as a master or slave timing diagram where the SCK pin, the
MISO pin, the MOSI pin are directly connected between the master and the slave device.
Note:
If CPOL is changed at the communication byte boundaries, the SPI must be disabled by
resetting the SPE bit.
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Serial peripheral interface (SPI)
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Figure 61. Data clock timing diagram
CPHA = 1
SCK
(CPOL = 1)
SCK
(CPOL = 0)
MISO
(from master)
MSBit
MSBit
Bit 6
Bit 6
Bit 5
Bit 5
Bit 4
Bit 4
Bit3
Bit3
Bit 2
Bit 2
Bit 1
Bit 1
LSBit
LSBit
MOSI
(from slave)
SS
(to slave)
CAPTURE STROBE
CPHA = 0
SCK
(CPOL = 1)
SCK
(CPOL = 0)
MISO
(from master)
MSBit
Bit 6
Bit 6
Bit 5
Bit 5
Bit 4
Bit 4
Bit3
Bit3
Bit 2
Bit 2
Bit 1
Bit 1
LSBit
LSBit
MOSI
(from slave)
MSBit
SS
(to slave)
CAPTURE STROBE
Note: This figure should not be used as a replacement for parametric information.
Refer to Chapter 19: Electrical characteristics.
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ST72325xxx-Auto
Serial peripheral interface (SPI)
14.5
Error flags
14.5.1
Master mode fault (MODF)
Master mode fault occurs when the master device has its SS pin pulled low.
When a Master mode fault occurs:
●
The MODF bit is set and an SPI interrupt request is generated if the SPIE bit is set.
●
The SPE bit is reset. This blocks all output from the device and disables the SPI
peripheral.
●
The MSTR bit is reset, thus forcing the device into slave mode.
Clearing the MODF bit is done through a software sequence:
1. A read access to the SPICSR register while the MODF bit is set.
2. A write to the SPICR register.
Note:
To avoid any conflicts in an application with multiple slaves, the SS pin must be pulled high
during the MODF bit clearing sequence. The SPE and MSTR bits may be restored to their
original state during or after this clearing sequence.
Hardware does not allow the user to set the SPE and MSTR bits while the MODF bit is set
except in the MODF bit clearing sequence.
14.5.2
Overrun condition (OVR)
An overrun condition occurs, when the master device has sent a data byte and the slave
device has not cleared the SPIF bit issued from the previously transmitted byte.
When an Overrun occurs:
●
The OVR bit is set and an interrupt request is generated if the SPIE bit is set.
In this case, the receiver buffer contains the byte sent after the SPIF bit was last cleared. A
read to the SPIDR register returns this byte. All other bytes are lost.
The OVR bit is cleared by reading the SPICSR register.
14.5.3
Write collision error (WCOL)
A write collision occurs when the software tries to write to the SPIDR register while a data
transfer is taking place with an external device. When this happens, the transfer continues
uninterrupted; and the software write will be unsuccessful.
Write collisions can occur both in master and slave mode. See also Slave select
management on page 132.
Note:
A “read collision” will never occur since the received data byte is placed in a buffer in which
access is always synchronous with the MCU operation.
The WCOL bit in the SPICSR register is set if a write collision occurs.
No SPI interrupt is generated when the WCOL bit is set (the WCOL bit is a status flag only).
Clearing the WCOL bit is done through a software sequence (see Figure 62).
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Serial peripheral interface (SPI)
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Figure 62. Clearing the WCOL bit (Write Collision Flag) software sequence
Clearing sequence after SPIF = 1 (end of a data byte transfer)
Read SPICSR
1st Step
RESULT
SPIF = 0
WCOL = 0
2nd Step
Read SPIDR
Clearing sequence before SPIF = 1 (during a data byte transfer)
Read SPICSR
1st Step
RESULT
Note: Writing to the SPIDR register
instead of reading it does not reset the
WCOL bit.
2nd Step
Read SPIDR
WCOL = 0
14.5.4
Single master systems
A typical single master system may be configured, using an MCU as the master and four
MCUs as slaves (see Figure 63).
The master device selects the individual slave devices by using four pins of a parallel port to
control the four SS pins of the slave devices.
The SS pins are pulled high during reset since the master device ports will be forced to be
inputs at that time, thus disabling the slave devices.
Note:
To prevent a bus conflict on the MISO line the master allows only one active slave device
during a transmission.
For more security, the slave device may respond to the master with the received data byte.
Then the master will receive the previous byte back from the slave device if all MISO and
MOSI pins are connected and the slave has not written to its SPIDR register.
Other transmission security methods can use ports for handshake lines or data bytes with
command fields.
Figure 63. Single master / multiple slave configuration
SS
SS
SS
SS
SCK
SCK
Slave
SCK
Slave
MCU
SCK
Slave
MCU
Slave
MCU
MCU
MOSI
MISO
MISO
MOSI
MISO
MOSI
MISO
MOSI
MISO
MOSI
SCK
Master
MCU
5V
SS
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Serial peripheral interface (SPI)
14.6
Low power modes
Table 64. Effect of low power modes on SPI
Mode
Effect
No effect on SPI.
Wait
SPI interrupt events cause the device to exit from Wait mode.
SPI registers are frozen.
In Halt mode, the SPI is inactive. SPI operation resumes when the MCU is woken up by
an interrupt with “exit from Halt mode” capability. The data received is subsequently
read from the SPIDR register when the software is running (interrupt vector fetching). If
several data are received before the wake-up event, then an overrun error is generated.
This error can be detected after the fetch of the interrupt routine that woke up the
device.
Halt
14.6.1
Using the SPI to wake up the MCU from Halt mode
In slave configuration, the SPI is able to wake up the ST7 device from Halt mode through a
SPIF interrupt. The data received is subsequently read from the SPIDR register when the
software is running (interrupt vector fetch). If multiple data transfers have been performed
before software clears the SPIF bit, then the OVR bit is set by hardware.
Note:
When waking up from Halt mode, if the SPI remains in Slave mode, it is recommended to
perform an extra communications cycle to bring the SPI from Halt mode state to normal
state. If the SPI exits from Slave mode, it returns to normal state immediately.
Caution:
The SPI can wake up the ST7 from Halt mode only if the Slave Select signal (external SS
pin or the SSI bit in the SPICSR register) is low when the ST7 enters Halt mode. So if Slave
selection is configured as external (see Slave select management on page 132), make sure
the master drives a low level on the SS pin when the slave enters Halt mode.
14.7
Interrupts
Table 65. SPI interrupt control/wake-up capability
Enable
control bit
Exit from
Wait
Exit from
Halt
Interrupt event
Event flag
SPI End of Transfer event
Master Mode Fault event
Overrun error
SPIF
MODF
OVR
Yes
No
SPIE
Yes
Note:
The SPI interrupt events are connected to the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding Enable Control Bit is set and the interrupt
mask in the CC register is reset (RIM instruction).
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Serial peripheral interface (SPI)
ST72325xxx-Auto
14.8
SPI registers
Control register (SPICR)
SPICR
14.8.1
Reset value: 0000 xxxx (0xh)
7
6
5
4
3
2
1
0
SPIE
SPE
SPR2
MSTR
CPOL
CPHA
SPR[1:0]
RW
RW
RW
RW
RW
RW
RW
Table 66. SPICR register description
Bit
Name
Function
Serial Peripheral Interrupt Enable
This bit is set and cleared by software.
0: Interrupt is inhibited
7
SPIE
1: An SPI interrupt is generated whenever SPIF = 1, MODF = 1 or OVR = 1 in the
SPICSR register.
Serial Peripheral Output Enable
This bit is set and cleared by software. It is also cleared by hardware when, in
master mode, SS = 0 (see Master mode fault (MODF) on page 137). The SPE bit
is cleared by reset, so the SPI peripheral is not initially connected to the external
pins.
6
SPE
0: I/O pins free for general purpose I/O
1: SPI I/O pin alternate functions enabled
Divider Enable
This bit is set and cleared by software and is cleared by reset. It is used with the
SPR[1:0] bits to set the baud rate. Refer to Table 67.
0: Divider by 2 enabled
1: Divider by 2 disabled
Note: This bit has no effect in slave mode.
5
4
SPR2
MSTR
Master Mode
This bit is set and cleared by software. It is also cleared by hardware when, in
master mode, SS = 0 (see Master mode fault (MODF) on page 137).
0: Slave mode
1: Master mode. The function of the SCK pin changes from an input to an output
and the functions of the MISO and MOSI pins are reversed.
Clock Polarity
This bit is set and cleared by software. This bit determines the idle state of the
serial Clock. The CPOL bit affects both the master and slave modes.
0: SCK pin has a low level idle state
1: SCK pin has a high level idle state
Note: If CPOL is changed at the communication byte boundaries, the SPI must be
disabled by resetting the SPE bit.
3
2
CPOL
CPHA
Clock Phase
This bit is set and cleared by software.
0: The first clock transition is the first data capture edge.
1: The second clock transition is the first capture edge.
Note: The slave must have the same CPOL and CPHA settings as the master.
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Serial peripheral interface (SPI)
Table 66. SPICR register description (continued)
Bit Name Function
Serial Clock Frequency
These bits are set and cleared by software. Used with the SPR2 bit, they select
the baud rate of the SPI serial clock SCK output by the SPI in master mode.
Note: These 2 bits have no effect in slave mode.
1:0 SPR[1:0]
Table 67. SPI master mode SCK frequency
Serial clock SPR2
CPU/4
SPR1
SPR0
f
1
0
0
1
0
0
0
0
0
1
1
1
0
0
1
0
0
1
fCPU/8
f
CPU/16
fCPU/32
fCPU/64
CPU/128
f
14.8.2
Control/status register (SPICSR)
SPICSR
Reset value: 0000 0000 (00h)
7
6
5
4
3
2
1
0
SPIF
WCOL
OVR
MODF
Reserved
-
SOD
SSM
SSI
RO
RO
RO
RO
RW
RW
RW
Table 68. SPICSR register description
Bit Name
Function
Serial Peripheral Data Transfer Flag
This bit is set by hardware when a transfer has been completed. An interrupt is
generated if SPIE = 1 in the SPICR register. It is cleared by a software sequence (an
access to the SPICSR register followed by a write or a read to the SPIDR register).
0: Data transfer is in progress or the flag has been cleared
7
SPIF
1: Data transfer between the device and an external device has been completed.
While the SPIF bit is set, all writes to the SPIDR register are inhibited until the
SPICSR register is read.
Write Collision status
This bit is set by hardware when a write to the SPIDR register is done during a
transmit sequence. It is cleared by a software sequence (see Figure 62).
0: No write collision occurred.
6
5
WCOL
OVR
1: A write collision has been detected.
SPI Overrun error
This bit is set by hardware when the byte currently being received in the shift register
is ready to be transferred into the SPIDR register while SPIF = 1 (see Overrun
condition (OVR) on page 137). An interrupt is generated if SPIE = 1 in SPICR
register. The OVR bit is cleared by software reading the SPICSR register.
0: No overrun error
1: Overrun error detected
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Serial peripheral interface (SPI)
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Table 68. SPICSR register description (continued)
Bit Name Function
Mode Fault flag
This bit is set by hardware when the SS pin is pulled low in master mode (see
Master mode fault (MODF) on page 137). An SPI interrupt can be generated if
SPIE = 1 in the SPICSR register. This bit is cleared by a software sequence (An
access to the SPICR register while MODF = 1 followed by a write to the SPICR
register).
4
MODF
0: No master mode fault detected
1: A fault in master mode has been detected
3
2
-
Reserved, must be kept cleared
SPI Output Disable
This bit is set and cleared by software. When set, it disables the alternate function of
the SPI output (MOSI in master mode / MISO in slave mode).
0: SPI output enabled (if SPE = 1)
SOD
1: SPI output disabled
SS Management
This bit is set and cleared by software. When set, it disables the alternate function of
the SPI SS pin and uses the SSI bit value instead. See Slave select management on
page 132.
0: Hardware management (SS managed by external pin)
1: Software management (internal SS signal controlled by SSI bit. External SS pin
free for general-purpose I/O)
1
0
SSM
SSI
SS Internal Mode
This bit is set and cleared by software. It acts as a ‘chip select’ by controlling the
level of the SS slave select signal when the SSM bit is set.
0: Slave selected
1: Slave deselected
14.8.3
Data I/O register (SPIDR)
SPIDR
Reset value: Undefined
7
6
5
4
3
2
1
0
D[7:0]
RW
The SPIDR register is used to transmit and receive data on the serial bus. In a master
device, a write to this register will initiate transmission/reception of another byte.
Note:
During the last clock cycle the SPIF bit is set, a copy of the received data byte in the shift
register is moved to a buffer. When the user reads the serial peripheral data I/O register, the
buffer is actually being read.
While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR
register is read.
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Serial peripheral interface (SPI)
Warning: A write to the SPIDR register places data directly into the
shift register for transmission.
A read to the SPIDR register returns the value located in the buffer and not the content of
the shift register (see Figure 57).
Table 69. SPI register map and reset values
Address
(Hex.)
Register
label
7
6
5
4
3
2
1
0
SPIDR
Reset value
MSB
x
LSB
x
0021h
0022h
0023h
x
x
x
x
x
x
SPICR
Reset value
SPIE
0
SPE
0
SPR2 MSTR CPOL CPHA SPR1 SPR0
0
0
x
x
x
x
SPICSR
Reset value
SPIF WCOL OVR
0
MODF
0
SOD
0
SSM
0
SSI
0
0
0
0
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Serial communications interface (SCI)
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15
Serial communications interface (SCI)
15.1
Introduction
The Serial Communications Interface (SCI) offers a flexible means of full-duplex data
exchange with external equipment requiring an industry standard NRZ asynchronous serial
data format. The SCI offers a very wide range of baud rates using two baud rate generator
systems.
15.2
Main features
●
●
●
●
●
●
●
Full duplex, asynchronous communications
NRZ standard format (Mark/Space)
Dual baud rate generator systems
Independently programmable transmit and receive baud rates up to 500K baud
Programmable data word length (8 or 9 bits)
Receive buffer full, Transmit buffer empty and End of Transmission flags
2 receiver wake-up modes:
–
–
Address bit (MSB)
Idle line
●
●
●
Muting function for multiprocessor configurations
Separate enable bits for Transmitter and Receiver
4 error detection flags:
–
–
–
–
Overrun error
Noise error
Frame error
Parity error
●
5 interrupt sources with flags:
–
–
–
–
–
Transmit data register empty
Transmission complete
Receive data register full
Idle line received
Overrun error detected
●
●
Parity control:
–
–
Transmits parity bit
Checks parity of received data byte
Reduced power consumption mode
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Serial communications interface (SCI)
15.3
General description
The interface is externally connected to another device by two pins (see Figure 65):
●
TDO: Transmit Data Output. When the transmitter and the receiver are disabled, the
output pin returns to its I/O port configuration. When the transmitter and/or the receiver
are enabled and nothing is to be transmitted, the TDO pin is at high level.
●
RDI: Receive Data Input is the serial data input. Oversampling techniques are used for
data recovery by discriminating between valid incoming data and noise.
Through these pins, serial data is transmitted and received as frames comprising:
●
●
●
●
An Idle Line prior to transmission or reception
A start bit
A data word (8 or 9 bits) least significant bit first
A Stop bit indicating that the frame is complete
This interface uses two types of baud rate generator:
●
A conventional type for commonly-used baud rates
●
An extended type with a prescaler offering a very wide range of baud rates even with
non-standard oscillator frequencies
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Serial communications interface (SCI)
Figure 64. SCI block diagram
ST72325xxx-Auto
Write
Read
(DATA REGISTER) DR
Received Data Register (RDR)
Received Shift Register
Transmit Data Register (TDR)
TDO
RDI
Transmit Shift Register
CR1
R8
T8 SCID
M
WAKE PCE PS
PIE
WAKE
UP
UNIT
TRANSMIT
CONTROL
RECEIVER
CLOCK
RECEIVER
CONTROL
CR2
SR
TIE TCIE RIE ILIE TE RE RWU SBK
TDRE TC RDRF IDLE OR
NF FE
PE
SCI
INTERRUPT
CONTROL
TRANSMITTER
CLOCK
TRANSMITTER RATE
CONTROL
fCPU
/PR
/16
BRR
SCP1
SCT2
SCT1SCT0SCR2 SCR1SCR0
SCP0
RECEIVER RATE
CONTROL
CONVENTIONAL BAUD RATE GENERATOR
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Serial communications interface (SCI)
15.4
Functional description
The block diagram of the Serial Control Interface, is shown in Figure 64. It contains six
dedicated registers:
●
●
●
●
●
2 control registers (SCICR1 and SCICR2)
a status register (SCISR)
a baud rate register (SCIBRR)
an extended prescaler receiver register (SCIERPR)
an extended prescaler transmitter register (SCIETPR)
Refer to the register descriptions in Section 15.7 for the definitions of each bit.
15.4.1
Serial data format
Word length may be selected as being either 8 or 9 bits by programming the M bit in the
SCICR1 register (see Figure 64).
The TDO pin is in low state during the start bit.
The TDO pin is in high state during the stop bit.
An Idle character is interpreted as an entire frame of ‘1’s followed by the start bit of the next
frame which contains data.
A Break character is interpreted on receiving ‘0’s for some multiple of the frame period. At
the end of the last break frame the transmitter inserts an extra ‘1’ bit to acknowledge the
start bit.
Transmission and reception are driven by their own baud rate generator.
Figure 65. Word length programming
9-bit Word length (M bit is set)
Possible
Parity
Next Data Frame
Data Frame
Bit
Next
Start
Bit
Start
Bit
Stop
Bit
Bit2
Bit6
Bit5
Bit8
Bit0
Bit1
Bit3
Bit4
Bit7
Start
Bit
Idle Frame
Start
Bit
Extra
‘1’
Break Frame
8-bit Word length (M bit is reset)
Possible
Parity
Next Data Frame
Data Frame
Bit
Next
Start
Start
Bit
Stop
Bit
Bit2
Bit6
Bit1
Bit3
Bit4
Bit5
Bit7
Bit0
Bit
Start
Bit
Idle Frame
Start
Bit
Extra
‘1’
Break Frame
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Serial communications interface (SCI)
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15.4.2
Transmitter
The transmitter can send data words of either 8 or 9 bits depending on the M bit status.
When the M bit is set, word length is 9 bits and the 9th bit (the MSB) has to be stored in the
T8 bit in the SCICR1 register.
Character transmission
During an SCI transmission, data shifts out least significant bit first on the TDO pin. In this
mode, the SCIDR register consists of a buffer (TDR) between the internal bus and the
transmit shift register (see Figure 64).
Procedure
1. Select the M bit to define the word length.
2. Select the desired baud rate using the SCIBRR and the SCIETPR registers.
3. Set the TE bit to assign the TDO pin to the alternate function and to send an idle frame
as first transmission.
4. Access the SCISR register and write the data to send in the SCIDR register (this
sequence clears the TDRE bit). Repeat this sequence for each data to be transmitted.
Clearing the TDRE bit is always performed by the following software sequence:
1. An access to the SCISR register
2. A write to the SCIDR register
The TDRE bit is set by hardware and it indicates:
●
●
●
The TDR register is empty.
The data transfer is beginning.
The next data can be written in the SCIDR register without overwriting the previous
data.
This flag generates an interrupt if the TIE bit is set and the I bit is cleared in the CCR
register.
When a transmission is taking place, a write instruction to the SCIDR register stores the
data in the TDR register and which is copied in the shift register at the end of the current
transmission.
When no transmission is taking place, a write instruction to the SCIDR register places the
data directly in the shift register, the data transmission starts, and the TDRE bit is
immediately set.
When a frame transmission is complete (after the stop bit) the TC bit is set and an interrupt
is generated if the TCIE is set and the I bit is cleared in the CCR register.
Clearing the TC bit is performed by the following software sequence:
1. An access to the SCISR register
2. A write to the SCIDR register
Note:
The TDRE and TC bits are cleared by the same software sequence.
Break characters
Setting the SBK bit loads the shift register with a break character. The break frame length
depends on the M bit (see Figure 65).
As long as the SBK bit is set, the SCI send break frames to the TDO pin. After clearing this
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ST72325xxx-Auto
Serial communications interface (SCI)
bit by software the SCI insert a logic 1 bit at the end of the last break frame to guarantee the
recognition of the start bit of the next frame.
Idle characters
Setting the TE bit drives the SCI to send an idle frame before the first data frame.
Clearing and then setting the TE bit during a transmission sends an idle frame after the
current word.
Note:
Resetting and setting the TE bit causes the data in the TDR register to be lost. Therefore the
best time to toggle the TE bit is when the TDRE bit is set, that is, before writing the next byte
in the SCIDR.
15.4.3
Receiver
The SCI can receive data words of either 8 or 9 bits. When the M bit is set, word length is 9
bits and the MSB is stored in the R8 bit in the SCICR1 register.
Character reception
During a SCI reception, data shifts in least significant bit first through the RDI pin. In this
mode, the SCIDR register consists or a buffer (RDR) between the internal bus and the
received shift register (see Figure 64).
Procedure
1. Select the M bit to define the word length.
2. Select the desired baud rate using the SCIBRR and the SCIERPR registers.
3. Set the RE bit, this enables the receiver which begins searching for a start bit.
When a character is received:
●
The RDRF bit is set. It indicates that the content of the shift register is transferred to the
RDR.
●
●
An interrupt is generated if the RIE bit is set and the I bit is cleared in the CCR register.
The error flags can be set if a frame error, noise or an overrun error has been detected
during reception.
Clearing the RDRF bit is performed by the following software sequence done by:
1. An access to the SCISR register
2. A read to the SCIDR register.
The RDRF bit must be cleared before the end of the reception of the next character to avoid
an overrun error.
Break character
When a break character is received, the SCI handles it as a framing error.
Idle character
When an idle frame is detected, there is the same procedure as a data received character
plus an interrupt if the ILIE bit is set and the I bit is cleared in the CCR register.
Overrun error
An overrun error occurs when a character is received when RDRF has not been reset. Data
cannot be transferred from the shift register to the RDR register as long as the RDRF bit is
not cleared.
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Serial communications interface (SCI)
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When an overrun error occurs:
●
●
●
●
The OR bit is set.
The RDR content is not lost.
The shift register is overwritten.
An interrupt is generated if the RIE bit is set and the I bit is cleared in the CCR register.
The OR bit is reset by an access to the SCISR register followed by a SCIDR register read
operation.
Noise error
Oversampling techniques are used for data recovery by discriminating between valid
incoming data and noise. Normal data bits are considered valid if three consecutive samples
(8th, 9th, 10th) have the same bit value, otherwise the NF flag is set. In the case of start bit
detection, the NF flag is set on the basis of an algorithm combining both valid edge
detection and three samples (8th, 9th, 10th). Therefore, to prevent the NF flag getting set
during start bit reception, there should be a valid edge detection as well as three valid
samples.
When noise is detected in a frame:
●
●
●
The NF flag is set at the rising edge of the RDRF bit.
Data is transferred from the Shift register to the SCIDR register.
No interrupt is generated. However this bit rises at the same time as the RDRF bit
which itself generates an interrupt.
The NF flag is reset by a SCISR register read operation followed by a SCIDR register read
operation.
During reception, if a false start bit is detected (for example, 8th, 9th, 10th samples are 011,
101, 110), the frame is discarded and the receiving sequence is not started for this frame.
There is no RDRF bit set for this frame and the NF flag is set internally (not accessible to the
user). This NF flag is accessible along with the RDRF bit when a next valid frame is
received.
Note:
If the application Start Bit is not long enough to match the above requirements, then the NF
Flag may get set due to the short Start Bit. In this case, the NF flag may be ignored by the
application software when the first valid byte is received.
See also Noise error causes on page 154.
150/250
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Serial communications interface (SCI)
Figure 66. SCI baud rate and extended prescaler block diagram
TRANSMITTER
CLOCK
EXTENDED PRESCALER TRANSMITTER RATE CONTROL
SCIETPR
EXTENDED TRANSMITTER PRESCALER REGISTER
SCIERPR
EXTENDED RECEIVER PRESCALER REGISTER
RECEIVER
CLOCK
EXTENDED PRESCALER RECEIVER RATE CONTROL
EXTENDED PRESCALER
f
CPU
TRANSMITTER RATE
CONTROL
/PR
/16
SCIBRR
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0
RECEIVER RATE
CONTROL
CONVENTIONAL BAUD RATE GENERATOR
Framing error
A framing error is detected when:
●
The stop bit is not recognized on reception at the expected time, following either a de-
synchronization or excessive noise.
●
A break is received.
When the framing error is detected:
●
●
●
The FE bit is set by hardware.
Data is transferred from the Shift register to the SCIDR register.
No interrupt is generated. However this bit rises at the same time as the RDRF bit
which itself generates an interrupt.
The FE bit is reset by a SCISR register read operation followed by a SCIDR register read
operation.
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Serial communications interface (SCI)
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Conventional baud rate generation
The baud rate for the receiver and transmitter (Rx and Tx) are set independently and
calculated as follows:
f
f
CPU
CPU
Rx =
Tx =
(16 PR) RR
(16 PR) TR
*
*
*
*
with:
PR = 1, 3, 4 or 13 (see SCP[1:0] bits)
TR = 1, 2, 4, 8, 16, 32, 64,128 (see SCT[2:0] bits)
RR = 1, 2, 4, 8, 16, 32, 64,128 (see SCR[2:0] bits)
All these bits are in the SCIBRR register.
Example: If f is 8 MHz (normal mode) and if PR = 13 and TR = RR = 1, the transmit and
CPU
receive baud rates are 38400 baud.
Note:
The baud rate registers MUST NOT be changed while the transmitter or the receiver is
enabled.
Extended baud rate generation
The extended prescaler option provides a very fine tuning of the baud rate, using a 255
value prescaler, whereas the conventional baud rate generator retains industry standard
software compatibility.
The extended baud rate generator block diagram is described in the Figure 66.
The output clock rate sent to the transmitter or to the receiver is the output from the 16
divider divided by a factor ranging from 1 to 255 set in the SCIERPR or the SCIETPR
register.
Note:
The extended prescaler is activated by setting the SCIETPR or SCIERPR register to a value
other than zero. The baud rates are calculated as follows:
f
f
CPU
CPU
Rx =
Tx =
16 ERPR (PR RR)
16 ETPR (PR TR)
*
*
*
*
*
*
with:
ETPR = 1,..,255 (see SCIETPR register)
ERPR = 1,..,255 (see SCIERPR register)
Receiver muting and wake-up feature
In multiprocessor configurations it is often desirable that only the intended message
recipient should actively receive the full message contents, thus reducing redundant SCI
service overhead for all non-addressed receivers.
The non-addressed devices may be placed in sleep mode by means of the muting function.
Setting the RWU bit by software puts the SCI in sleep mode:
●
All the reception status bits cannot be set.
All the receive interrupts are inhibited.
●
A muted receiver may be awakened by one of the following two ways:
●
by Idle Line detection if the WAKE bit is reset
by Address Mark detection if the WAKE bit is set
●
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ST72325xxx-Auto
Serial communications interface (SCI)
A receiver wakes up by Idle Line detection when the Receive line has recognized an Idle
Frame. Then the RWU bit is reset by hardware but the IDLE bit is not set.
Receiver wakes up by Address Mark detection when it received a ‘1’ as the most significant
bit of a word, thus indicating that the message is an address. The reception of this particular
word wakes up the receiver, resets the RWU bit and sets the RDRF bit, which allows the
receiver to receive this word normally and to use it as an address word.
Caution:
In Mute mode, do not write to the SCICR2 register. If the SCI is in Mute mode during the
read operation (RWU = 1) and a address mark wake-up event occurs (RWU is reset) before
the write operation, the RWU bit is set again by this write operation. Consequently the
address byte is lost and the SCI is not woken up from Mute mode.
Parity control
Parity control (generation of parity bit in transmission and parity checking in reception) can
be enabled by setting the PCE bit in the SCICR1 register. Depending on the frame length
defined by the M bit, the possible SCI frame formats are as listed in Table 70.
Table 70. Frame formats
M bit
PCE bit
SCI frame
0
0
1
1
0
1
0
1
| SB | 8 bit data | STB |
| SB | 7-bit data | PB | STB |
| SB | 9-bit data | STB |
| SB | 8-bit data PB | STB |
Legend: SB = Start Bit, STB = Stop Bit, PB = Parity Bit
Note:
In case of wake-up by an address mark, the MSB bit of the data is taken into account and
not the parity bit
Even parity: the parity bit is calculated to obtain an even number of ‘1’s inside the frame
made of the 7 or 8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit.
Example: data = 00110101; 4 bits set => parity bit is 0 if even parity is selected (PS bit = 0).
Odd parity: the parity bit is calculated to obtain an odd number of ‘1’s inside the frame
made of the 7 or 8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit.
Example: data = 00110101; 4 bits set => parity bit is 1 if odd parity is selected (PS bit = 1).
Transmission mode: If the PCE bit is set then the MSB bit of the data written in the data
register is not transmitted but is changed by the parity bit.
Reception mode: If the PCE bit is set then the interface checks if the received data byte
has an even number of ‘1’s if even parity is selected (PS = 0) or an odd number of ‘1’s if odd
parity is selected (PS = 1). If the parity check fails, the PE flag is set in the SCISR register
and an interrupt is generated if PIE is set in the SCICR1 register.
SCI clock tolerance
During reception, each bit is sampled 16 times. The majority of the 8th, 9th and 10th
samples is considered as the bit value. For a valid bit detection, all the three samples should
have the same value otherwise the noise flag (NF) is set. For example: If the 8th, 9th and
10th samples are 0, 1 and 1 respectively, then the bit value is ‘1’, but the Noise Flag bit is set
because the three samples values are not the same.
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Serial communications interface (SCI)
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Consequently, the bit length must be long enough so that the 8th, 9th and 10th samples
have the desired bit value. This means the clock frequency should not vary more than 6/16
(37.5%) within one bit. The sampling clock is resynchronized at each start bit, so that when
receiving 10 bits (one start bit, 1 data byte, 1 stop bit), the clock deviation must not exceed
3.75%.
Note:
The internal sampling clock of the microcontroller samples the pin value on every falling
edge. Therefore, the internal sampling clock and the time the application expects the
sampling to take place may be out of sync. For example: If the baud rate is 15.625 Kbaud
(bit length is 64µs), then the 8th, 9th and 10th samples are at 28µs, 32µs and 36µs
respectively (the first sample starting ideally at 0µs). But if the falling edge of the internal
clock occurs just before the pin value changes, the samples would then be out of sync by
~4us. This means the entire bit length must be at least 40µs (36µs for the 10th sample + 4µs
for synchronization with the internal sampling clock).
Clock deviation causes
The causes which contribute to the total deviation are:
–
D
: Deviation due to transmitter error (Local oscillator error of the transmitter or
TRA
the transmitter is transmitting at a different baud rate).
–
–
D
D
: Error due to the baud rate quantization of the receiver.
QUANT
: Deviation of the local oscillator of the receiver: This deviation can occur
REC
during the reception of one complete SCI message assuming that the deviation
has been compensated at the beginning of the message.
–
D
: Deviation due to the transmission line (generally due to the transceivers)
TCL
All the deviations of the system should be added and compared to the SCI clock tolerance:
+ D + D + D < 3.75%
D
TRA
QUANT
REC
TCL
Noise error causes
See also description of noise error in Receiver on page 149.
Start bit
The noise flag (NF) is set during start bit reception if one of the following conditions occurs:
1. A valid falling edge is not detected. A falling edge is considered to be valid if the 3
consecutive samples before the falling edge occurs are detected as ‘1’ and, after the
falling edge occurs, during the sampling of the 16 samples, if one of the samples
numbered 3, 5 or 7 is detected as a ‘1’.
2. During sampling of the 16 samples, if one of the samples numbered 8, 9 or 10 is
detected as a ‘1’.
Therefore, a valid Start Bit must satisfy both the above conditions to prevent the Noise Flag
getting set.
Data bits
The noise flag (NF) is set during normal data bit reception if the following condition occurs:
●
During the sampling of 16 samples, if all three samples numbered 8, 9 and10 are not
the same. The majority of the 8th, 9th and 10th samples is considered as the bit value.
Therefore, a valid Data Bit must have samples 8, 9 and 10 at the same value to prevent the
Noise Flag from getting set.
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Serial communications interface (SCI)
Figure 67. Bit sampling in reception mode
RDI LINE
Sample
sampled values
clock
1
2
3
4
5
6
7
8
9
10 11 12
13 14 15 16
6/16
7/16
7/16
One bit time
15.5
Low power modes
Table 71. Effect of low power modes on SCI
Mode
Effect
No effect on SCI.
SCI interrupts cause the device to exit from Wait mode.
Wait
SCI registers are frozen.
In Halt mode, the SCI stops transmitting/receiving until Halt mode is exited.
Halt
15.6
Interrupts
The SCI interrupt events are connected to the same interrupt vector.
These events generate an interrupt if the corresponding Enable Control Bit is set and the
interrupt mask in the CC register is reset (RIM instruction).
Table 72. SCI interrupt control/wake-up capability
Enable control
bit
Exit from
Wait
Exit from
Halt
Interrupt event
Event flag
Transmit Data Register Empty
Transmission Complete
TDRE
TC
TIE
Yes
Yes
Yes
Yes
No
No
No
No
TCIE
Received Data Ready to be Read
Overrun Error Detected
RDRF
OR
RIE
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Serial communications interface (SCI)
Table 72. SCI interrupt control/wake-up capability
ST72325xxx-Auto
Enable control
bit
Exit from
Exit from
Halt
Interrupt event
Event flag
Wait
Idle Line Detected
IDLE
PE
ILIE
PIE
Yes
Yes
No
No
Parity Error
15.7
SCI registers
Status register (SCISR)
SCISR
15.7.1
Reset value: 1100 0000 (C0h)
7
6
5
4
3
2
1
0
TDRE
RO
TC
RO
RDRF
RO
IDLE
RO
OR
RO
NF
RO
FE
RO
PE
RO
Table 73. SCISR register description
Bit Name
Function
Transmit data register empty
This bit is set by hardware when the content of the TDR register has been
transferred into the shift register. An interrupt is generated if the TIE bit = 1 in the
SCICR2 register. It is cleared by a software sequence (an access to the SCISR
register followed by a write to the SCIDR register).
7
TDRE
0: Data is not transferred to the shift register
1: Data is transferred to the shift register
Note: Data is not transferred to the shift register unless the TDRE bit is cleared.
Transmission complete
This bit is set by hardware when transmission of a frame containing Data is
complete. An interrupt is generated if TCIE = 1 in the SCICR2 register. It is cleared
by a software sequence (an access to the SCISR register followed by a write to the
SCIDR register).
0: Transmission is not complete
1: Transmission is complete
6
5
TC
Note: TC is not set after the transmission of a Preamble or a Break.
Received data ready flag
This bit is set by hardware when the content of the RDR register has been
transferred to the SCIDR register. An interrupt is generated if RIE = 1 in the SCICR2
register. It is cleared by a software sequence (an access to the SCISR register
followed by a read to the SCIDR register).
RDRF
0: Data is not received
1: Received data is ready to be read
156/250
ST72325xxx-Auto
Serial communications interface (SCI)
Table 73. SCISR register description (continued)
Bit Name Function
Idle line detect
This bit is set by hardware when an Idle Line is detected. An interrupt is generated if
the ILIE = 1 in the SCICR2 register. It is cleared by a software sequence (an access
to the SCISR register followed by a read to the SCIDR register).
0: No Idle Line is detected
1: Idle Line is detected
Note: The IDLE bit is not set again until the RDRF bit has been set itself (that is, a
new idle line occurs).
4
3
2
IDLE
Overrun error
This bit is set by hardware when the word currently being received in the shift
register is ready to be transferred into the RDR register while RDRF = 1. An interrupt
is generated if RIE = 1 in the SCICR2 register. It is cleared by a software sequence
(an access to the SCISR register followed by a read to the SCIDR register).
0: No Overrun error
1: Overrun error is detected
Note: When this bit is set RDR register content is not lost but the shift register is
overwritten.
OR
Noise flag
This bit is set by hardware when noise is detected on a received frame. It is cleared
by a software sequence (an access to the SCISR register followed by a read to the
SCIDR register).
NF
0: No noise is detected
1: Noise is detected
Note: This bit does not generate interrupt as it appears at the same time as the
RDRF bit which itself generates an interrupt.
Framing error
This bit is set by hardware when a de-synchronization, excessive noise or a break
character is detected. It is cleared by a software sequence (an access to the SCISR
register followed by a read to the SCIDR register).
0: No Framing error is detected
1: Framing error or break character is detected
1
FE
Note: This bit does not generate interrupt as it appears at the same time as the
RDRF bit which itself generates an interrupt. If the word currently being transferred
causes both frame error and overrun error, it will be transferred and only the OR bit
will be set.
Parity error
This bit is set by hardware when a parity error occurs in receiver mode. It is cleared
by a software sequence (a read to the status register followed by an access to the
SCIDR data register). An interrupt is generated if PIE = 1 in the SCICR1 register.
0: No parity error
0
PE
1: Parity error
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Serial communications interface (SCI)
ST72325xxx-Auto
15.7.2
Control register 1 (SCICR1)
SCICR1
Reset value: X000 0000 (x0h)
7
6
5
4
3
2
1
0
R8
T8
SCID
M
WAKE
PCE
PS
PIE
RW
RW
RW
RW
RW
RW
RW
RW
Table 74. SCICR1 register description
Bit Name
Function
Receive data bit 8
7
6
R8
T8
This bit is used to store the 9th bit of the received word when M = 1.
Transmit data bit 8
This bit is used to store the 9th bit of the transmitted word when M = 1.
Disabled for low power consumption
When this bit is set the SCI prescalers and outputs are stopped and the end of the
current byte transfer in order to reduce power consumption.This bit is set and
cleared by software.
5
SCID
0: SCI enabled
1: SCI prescaler and outputs disabled
Word length
This bit determines the word length. It is set or cleared by software.
0: 1 Start bit, 8 Data bits, 1 Stop bit
1: 1 Start bit, 9 Data bits, 1 Stop bit
Note: The M bit must not be modified during a data transfer (both transmission and
reception).
4
3
M
Wake-up method
This bit determines the SCI wake-up method. It is set or cleared by software.
0: Idle line
WAKE
1: Address mark
Parity control enable
This bit selects the hardware parity control (generation and detection). When the
parity control is enabled, the computed parity is inserted at the MSB position (9th
bit if M = 1; 8th bit if M = 0) and parity is checked on the received data. This bit is
set and cleared by software. Once it is set, PCE is active after the current byte (in
reception and in transmission).
2
1
PCE
0: Parity control disabled
1: Parity control enabled
Parity selection
This bit selects the odd or even parity when the parity generation/detection is
enabled (PCE bit set). It is set and cleared by software. The parity is selected after
the current byte.
0: Even parity
1: Odd parity
PS
158/250
ST72325xxx-Auto
Serial communications interface (SCI)
Table 74. SCICR1 register description (continued)
Bit Name Function
Parity interrupt enable
This bit enables the interrupt capability of the hardware parity control when a parity
error is detected (PE bit set). It is set and cleared by software.
0: Parity error interrupt disabled
0
PIE
1: Parity error interrupt enabled
15.7.3
Control register 2 (SCICR2)
SCICR2
Reset value: 0000 0000 (00h)
7
6
5
4
3
2
1
0
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
RW
RW
RW
RW
RW
RW
RW
RW
Table 75. SCICR2 register description
Bit Name
Function
Transmitter interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever TDRE = 1 in the SCISR register.
7
6
TIE
Transmission complete interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
TCIE
1: An SCI interrupt is generated whenever TC = 1 in the SCISR register.
Receiver interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever OR = 1 or RDRF = 1 in the SCISR
register.
5
4
RIE
ILIE
Idle line interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever IDLE = 1 in the SCISR register.
Transmitter enable
This bit enables the transmitter. It is set and cleared by software.
0: Transmitter is disabled
1: Transmitter is enabled
Notes:
3
TE
During transmission, a ‘0’ pulse on the TE bit (‘0’ followed by ‘1’) sends a preamble
(idle line) after the current word.
When TE is set there is a 1 bit-time delay before the transmission starts.
Caution: The TDO pin is free for general purpose I/O only when the TE and RE bits
are both cleared (or if TE is never set).
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Serial communications interface (SCI)
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Table 75. SCICR2 register description (continued)
Bit Name Function
Receiver enable
This bit enables the receiver. It is set and cleared by software.
0: Receiver is disabled
2
RE
1: Receiver is enabled and begins searching for a start bit
Receiver wake-up
This bit determines if the SCI is in mute mode or not. It is set and cleared by software
and can be cleared by hardware when a wake-up sequence is recognized.
0: Receiver in Active mode
1
RWU
1: Receiver in Mute mode
Note: Before selecting Mute mode (setting the RWU bit), the SCI must receive some
data first, otherwise it cannot function in Mute mode with wake-up by idle line
detection.
Send break
This bit set is used to send break characters. It is set and cleared by software.
0: No break character is transmitted
1: Break characters are transmitted
0
SBK
Note: If the SBK bit is set to ‘1’ and then to ‘0’, the transmitter sends a BREAK word
at the end of the current word.
15.7.4
Data register (SCIDR)
This register contains the Received or Transmitted data character, depending on whether it
is read from or written to.
SCIDR
7
Reset value: Undefined
6
5
4
3
2
1
0
DR[7:0]
RW
The Data register performs a double function (read and write) since it is composed of two
registers, one for transmission (TDR) and one for reception (RDR).
The TDR register provides the parallel interface between the internal bus and the output
shift register (see Figure 64).
The RDR register provides the parallel interface between the input shift register and the
internal bus (see Figure 64).
15.7.5
Baud rate register (SCIBRR)
SCIBRR
7
Reset value: 0000 0000 (00h)
6
5
4
3
2
1
0
SCP[1:0]
RW
SCT[2:0]
RW
SCR[2:0]
RW
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Serial communications interface (SCI)
Function
Table 76. SCIBRR register description
Bit Name
First SCI Prescaler
These 2 prescaling bits allow several standard clock division ranges.
00: PR prescaling factor = 1
01: PR prescaling factor = 3
7:6 SCP[1:0]
10: PR prescaling factor = 4
11: PR prescaling factor = 13
SCI Transmitter rate divisor
These 3 bits, in conjunction with the SCP1 and SCP0 bits define the total division
applied to the bus clock to yield the transmit rate clock in conventional Baud Rate
Generator mode.
000: TR dividing factor = 1
001: TR dividing factor = 2
010: TR dividing factor = 4
5:3 SCT[2:0]
011: TR dividing factor = 8
100: TR dividing factor = 16
101: TR dividing factor = 32
110: TR dividing factor = 64
111: TR dividing factor = 128
SCI Receiver rate divisor
These 3 bits, in conjunction with the SCP[1:0] bits define the total division applied
to the bus clock to yield the receive rate clock in conventional Baud Rate
Generator mode.
000: RR dividing factor = 1
001: RR dividing factor = 2
010: RR dividing factor = 4
2:0 SCR[2:0]
011: RR dividing factor = 8
100: RR dividing factor = 16
101: RR dividing factor = 32
110: RR dividing factor = 64
111: RR dividing factor = 128
15.7.6
Extended receive prescaler division register (SCIERPR)
This register allows setting of the extended prescaler rate division factor for the receive
circuit.
SCIERPR
7
Reset value: 0000 0000 (00h)
6
5
4
3
2
1
0
ERPR[7:0]
RW
161/250
Serial communications interface (SCI)
ST72325xxx-Auto
Table 77. SCIERPR register description
Bit Name
Function
8-bit Extended Receive Prescaler Register
The extended baud rate generator is activated when a value different from 00h is
stored in this register. Therefore the clock frequency issued from the 16 divider
(see Figure 66) is divided by the binary factor set in the SCIERPR register (in
the range 1 to 255).
7:0 ERPR[7:0]
The extended baud rate generator is not used after a reset.
15.7.7
Extended transmit prescaler division register (SCIETPR)
This register allows setting of the external prescaler rate division factor for the transmit
circuit.
SCIETPR
7
Reset value: 0000 0000 (00h)
6
5
4
3
2
1
0
ETPR[7:0]
RW
Table 78. SCIETPR register description
Bit Name
Function
8-bit Extended Transmit Prescaler Register
The extended baud rate generator is activated when a value different from 00h is
stored in this register. Therefore the clock frequency issued from the 16 divider
(see Figure 66) is divided by the binary factor set in the SCIETPR register (in the
range 1 to 255).
7:0 ETPR[7:0]
The extended baud rate generator is not used after a reset.
Table 79. Baud rate selection
Conditions
Accuracy
versus
Symbol
Parameter
Standard Baud rate Unit
fCPU
Prescaler
standard
Conventional mode
TR (or RR) = 128, PR = 13
TR (or RR) = 32, PR = 13
TR (or RR) = 16, PR = 13
300
1200
2400
4800
9600
10400 ~10416.67
19200 ~19230.77
38400 ~38461.54
~300.48
~1201.92
~2403.84
~4807.69
~9615.38
~0.16% TR (or RR) = 8, PR = 13
TR (or RR) = 4, PR = 13
TR (or RR) = 16, PR = 3
TR (or RR) = 2, PR = 13
TR (or RR) = 1, PR = 13
fTx
fRx
Communication
frequency
8 MHz
Hz
Extended mode
~0.79% ETPR (or ERPR) = 35,
TR (or RR) = 1, PR = 1
14400 ~14285.71
162/250
ST72325xxx-Auto
Serial communications interface (SCI)
Table 80. SCI register map and reset values
Address (Hex.) Register label
7
6
5
4
3
2
1
0
SCISR
0050h
TDRE
1
TC
1
RDRF
0
IDLE
0
OR
0
NF
0
FE
0
PE
0
Reset value
SCIDR
0051h
MSB
x
LSB
x
Reset value
x
x
x
x
x
x
SCIBRR
0052h
SCP1
0
SCP0
0
SCT2
0
SCT1
0
SCT0
0
SCR2
0
SCR1
0
SCR0
0
Reset value
SCICR1
0053h
R8
x
T8
0
SCID
0
M
0
WAKE
0
PCE
0
PS
0
PIE
0
Reset value
SCICR2
0054h
TIE
0
TCIE
0
RIE
0
ILIE
0
TE
0
RE
0
RWU
0
SBK
0
Reset value
SCIERPR
0055h
MSB
0
LSB
0
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
SCIPETPR
0057h
MSB
0
LSB
0
Reset value
163/250
I2C bus interface (I2C)
ST72325xxx-Auto
2
16
I C bus interface (I2C)
16.1
Introduction
2
2
The I C bus interface serves as an interface between the microcontroller and the serial I C
2
bus. It provides both multimaster and slave functions, and controls all I C bus-specific
sequencing, protocol, arbitration and timing. It supports fast I C mode (400 kHz).
2
16.2
Main features
2
●
●
●
●
●
●
●
Parallel-bus/I C protocol converter
Multimaster capability
7-bit/10-bit addressing
SMBus V1.1 compliant
Transmitter/Receiver flag
End-of-byte transmission flag
Transfer problem detection
2
16.2.1
I C master features
●
●
●
●
●
●
●
Clock generation
2
I C bus busy flag
Arbitration Lost flag
End of byte transmission flag
Transmitter/Receiver flag
Start bit detection flag
Start and Stop generation
2
16.2.2
I C slave features
●
●
●
●
●
●
●
Stop bit detection
2
I C bus busy flag
Detection of misplaced start or stop condition
2
Programmable I C address detection
Transfer problem detection
End-of-byte transmission flag
Transmitter/Receiver flag
164/250
ST72325xxx-Auto
I2C bus interface (I2C)
16.3
General description
In addition to receiving and transmitting data, this interface converts it from serial to parallel
format and vice versa, using either an interrupt or polled handshake. The interrupts are
2
enabled or disabled by software. The interface is connected to the I C bus by a data pin
2
(SDAI) and by a clock pin (SCLI). It can be connected both with a standard I C bus and a
2
fast I C bus. This selection is made by software.
16.3.1
Mode selection
The interface can operate in the four following modes:
●
Slave transmitter/receiver
Master transmitter/receiver
●
By default, it operates in slave mode.
The interface automatically switches from slave to master after it generates a START
condition and from master to slave in case of arbitration loss or a STOP generation, allowing
then Multimaster capability.
16.3.2
Communication flow
In Master mode, it initiates a data transfer and generates the clock signal. A serial data
transfer always begins with a start condition and ends with a stop condition. Both start and
stop conditions are generated in master mode by software.
In Slave mode, the interface is capable of recognizing its own address (7- or 10-bit), and the
General Call address. The General Call address detection may be enabled or disabled by
software.
Data and addresses are transferred as 8-bit bytes, MSB first. The first byte(s) following the
start condition contain the address (one in 7-bit mode, two in 10-bit mode). The address is
always transmitted in Master mode.
A 9th clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver must
send an acknowledge bit to the transmitter. Refer to Figure 68.
2
Figure 68. I C bus protocol
SDA
ACK
9
MSB
1
SCL
2
8
START
STOP
CONDITION
CONDITION
VR02119B
Acknowledge may be enabled and disabled by software.
2
The I C interface address and/or general call address can be selected by software.
2
The speed of the I C interface may be selected between standard (up to 100 kHz) and fast
2
I C (up to 400 kHz).
165/250
I2C bus interface (I2C)
ST72325xxx-Auto
16.3.3
SDA/SCL line control
Transmitter mode
The interface holds the clock line low before transmission to wait for the microcontroller to
write the byte in the data register.
Receiver mode
The interface holds the clock line low after reception to wait for the microcontroller to read
the byte in the data register.
The SCL frequency (f
the I C bus mode.
) is controlled by a programmable clock divider which depends on
SCL
2
2
When the I C cell is enabled, the SDA and SCL ports must be configured as floating inputs.
In this case, the value of the external pull-up resistor used depends on the application.
2
When the I C cell is disabled, the SDA and SCL ports revert to being standard I/O port pins.
2
Figure 69. I C interface block diagram
DATA REGISTER (DR)
DATA CONTROL
SDA or SDAI
DATA SHIFT REGISTER
COMPARATOR
OWN ADDRESS REGISTER 1 (OAR1)
OWN ADDRESS REGISTER 2 (OAR2)
CLOCK CONTROL
SCL or SCLI
CLOCK CONTROL REGISTER (CCR)
CONTROL REGISTER (CR)
STATUS REGISTER 1 (SR1)
STATUS REGISTER 2 (SR2)
CONTROL LOGIC
INTERRUPT
166/250
ST72325xxx-Auto
I2C bus interface (I2C)
16.4
Functional description
Refer to the CR, SR1 and SR2 registers in Section 16.7 for the bit definitions.
2
By default the I C interface operates in Slave mode (M/SL bit is cleared) except when it
initiates a transmit or receive sequence.
First the interface frequency must be configured using the FRi bits in the OAR2 register.
16.4.1
Slave mode
As soon as a start condition is detected, the address is received from the SDA line and sent
to the shift register; then it is compared with the address of the interface or the General Call
address (if selected by software).
Note:
In 10-bit addressing mode, the comparison includes the header sequence (11110xx0) and
the two most significant bits of the address.
Header matched (10-bit mode only): The interface generates an acknowledge pulse if the
ACK bit is set.
Address not matched: The interface ignores it and waits for another Start condition.
Address matched: The interface generates in sequence:
●
an acknowledge pulse if the ACK bit is set
●
EVF and ADSL bits are set with an interrupt if the ITE bit is set.
Then the interface waits for a read of the SR1 register, holding the SCL line low (see
Figure 70: Transfer sequencing EV1).
Next, in 7-bit mode read the DR register to determine from the least significant bit (Data
Direction Bit) if the slave must enter Receiver or Transmitter mode.
In 10-bit mode, after receiving the address sequence the slave is always in receive mode. It
will enter transmit mode on receiving a repeated Start condition followed by the header
sequence with matching address bits and the least significant bit set (11110xx1).
Slave receiver
Following the address reception and after the SR1 register has been read, the slave
receives bytes from the SDA line into the DR register via the internal shift register. After
each byte the interface generates in sequence:
●
an acknowledge pulse if the ACK bit is set
●
EVF and BTF bits are set with an interrupt if the ITE bit is set.
Then the interface waits for a read of the SR1 register followed by a read of the DR register,
holding the SCL line low (see Figure 70: Transfer sequencing EV2).
Slave transmitter
Following the address reception and after SR1 register has been read, the slave sends
bytes from the DR register to the SDA line via the internal shift register.
The slave waits for a read of the SR1 register followed by a write in the DR register, holding
the SCL line low (see Figure 70: Transfer sequencing EV3).
When the acknowledge pulse is received:
●
The EVF and BTF bits are set by hardware with an interrupt if the ITE bit is set.
167/250
I2C bus interface (I2C)
ST72325xxx-Auto
Closing slave communication
After the last data byte is transferred, a Stop Condition is generated by the master. The
interface detects this condition and sets:
●
EVF and STOPF bits with an interrupt if the ITE bit is set.
Then the interface waits for a read of the SR2 register (see Figure 70: Transfer sequencing
EV4).
Error cases
●
BERR: Detection of a Stop or a Start condition during a byte transfer. In this case, the
EVF and the BERR bits are set with an interrupt if the ITE bit is set.
If it is a Stop then the interface discards the data, released the lines and waits for
another Start condition.
If it is a Start then the interface discards the data and waits for the next slave address
on the bus.
●
AF: Detection of a non-acknowledge bit. In this case, the EVF and AF bits are set with
an interrupt if the ITE bit is set.
The AF bit is cleared by reading the I2CSR2 register. However, if read before the
completion of the transmission, the AF flag will be set again, thus possibly generating a
new interrupt. Software must ensure either that the SCL line is back at 0 before reading
the SR2 register, or be able to correctly handle a second interrupt during the 9th pulse
of a transmitted byte.
Note:
In case of errors, the SCL line is not held low; however, the SDA line can remain low if the
last bits transmitted are all 0. While AF = 1, the SCL line may be held low due to SB or BTF
flags that are set at the same time. It is then necessary to release both lines by software.
How to release the SDA / SCL lines
Set and subsequently clear the STOP bit while BTF is set. The SDA/SCL lines are released
after the transfer of the current byte.
SMBus compatibility
2
The ST7 I C is compatible with the SMBus V1.1 protocol. It supports all SMBus addressing
modes, SMBus bus protocols and CRC-8 packet error checking. Refer to SMBus Slave
2
Driver For ST7 I C Peripheral (AN1713).
16.4.2
Master mode
To switch from default Slave mode to Master mode a Start condition generation is needed.
Start condition
Setting the START bit while the BUSY bit is cleared causes the interface to switch to Master
mode (M/SL bit set) and generates a Start condition.
Once the Start condition is sent:
●
The EVF and SB bits are set by hardware with an interrupt if the ITE bit is set.
Then the master waits for a read of the SR1 register followed by a write in the DR register
with the Slave address, holding the SCL line low (see Figure 70: Transfer sequencing
EV5).
168/250
ST72325xxx-Auto
I2C bus interface (I2C)
Slave address transmission
Then the slave address is sent to the SDA line via the internal shift register.
●
In 7-bit addressing mode, one address byte is sent.
●
In 10-bit addressing mode, sending the first byte including the header sequence
causes the following event:
–
The EVF bit is set by hardware with interrupt generation if the ITE bit is set.
Then the master waits for a read of the SR1 register followed by a write in the DR register,
holding the SCL line low (see Figure 70: Transfer sequencing EV9).
Then the second address byte is sent by the interface.
After completion of this transfer (and acknowledge from the slave if the ACK bit is set):
●
The EVF bit is set by hardware with interrupt generation if the ITE bit is set.
Then the master waits for a read of the SR1 register followed by a write in the CR register
(for example set PE bit), holding the SCL line low (see Figure 70: Transfer sequencing
EV6).
Next, the master must enter Receiver or Transmitter mode.
Note:
In 10-bit addressing mode, to switch the master to Receiver mode, software must generate
a repeated Start condition and resend the header sequence with the least significant bit set
(11110xx1).
Master receiver
Following the address transmission and after SR1 and CR registers have been accessed,
the master receives bytes from the SDA line into the DR register via the internal shift
register. After each byte the interface generates in sequence:
●
Acknowledge pulse if the ACK bit is set
●
EVF and BTF bits are set by hardware with an interrupt if the ITE bit is set.
Then the interface waits for a read of the SR1 register followed by a read of the DR register,
holding the SCL line low (see Figure 70: Transfer sequencing EV7).
To close the communication: Before reading the last byte from the DR register, set the STOP
bit to generate the Stop condition. The interface goes automatically back to slave mode
(M/SL bit cleared).
Note:
In order to generate the non-acknowledge pulse after the last received data byte, the ACK
bit must be cleared just before reading the second last data byte.
Master transmitter
Following the address transmission and after SR1 register has been read, the master sends
bytes from the DR register to the SDA line via the internal shift register.
The master waits for a read of the SR1 register followed by a write in the DR register,
holding the SCL line low (see Figure 70: Transfer sequencing EV8).
When the acknowledge bit is received, the interface sets:
●
EVF and BTF bits with an interrupt if the ITE bit is set.
To close the communication: After writing the last byte to the DR register, set the STOP bit to
generate the Stop condition. The interface goes automatically back to slave mode (M/SL bit
cleared).
169/250
I2C bus interface (I2C)
Error cases
ST72325xxx-Auto
●
BERR: Detection of a Stop or a Start condition during a byte transfer. In this case, the
EVF and BERR bits are set by hardware with an interrupt if ITE is set.
Note that BERR will not be set if an error is detected during the first or second pulse of
each 9-bit transaction:
–
Single Master Mode
If a Start or Stop is issued during the first or second pulse of a 9-bit transaction,
the BERR flag will not be set and transfer will continue however the BUSY flag will
be reset. To work around this, slave devices should issue a NACK when they
receive a misplaced Start or Stop. The reception of a NACK or BUSY by the
master in the middle of communication makes it possible to re-initiate
transmission.
–
Multimaster Mode
Normally the BERR bit would be set whenever unauthorized transmission takes
place while transfer is already in progress. However, an issue will arise if an
2
external master generates an unauthorized Start or Stop while the I C master is
on the first or second pulse of a 9-bit transaction. It is possible to work around this
2
by polling the BUSY bit during I C master mode transmission. The resetting of the
BUSY bit can then be handled in a similar manner as the BERR flag being set.
●
AF: Detection of a non-acknowledge bit. In this case, the EVF and AF bits are set by
hardware with an interrupt if the ITE bit is set. To resume, set the Start or Stop bit.
The AF bit is cleared by reading the I2CSR2 register. However, if read before the
completion of the transmission, the AF flag will be set again, thus possibly generating a
new interrupt. Software must ensure either that the SCL line is back at 0 before reading
the SR2 register, or be able to correctly handle a second interrupt during the 9th pulse
of a transmitted byte.
●
ARLO: Detection of an arbitration lost condition.
In this case the ARLO bit is set by hardware (with an interrupt if the ITE bit is set and
the interface goes automatically back to slave mode (the M/SL bit is cleared).
Note:
In all these cases, the SCL line is not held low; however, the SDA line can remain low due to
possible ‘0’ bits transmitted last. It is then necessary to release both lines by software.
170/250
ST72325xxx-Auto
I2C bus interface (I2C)
Figure 70. Transfer sequencing
7-bit Slave receiver:
S Address
A
Data1
A
Data1
Data1
Data2
A
Data2
Data2
DataN
A
P
.....
EV1
7-bit Slave transmitter:
S Address
EV2
A
EV2
A
EV2
EV4
A
DataN NA
DataN NA
P
.....
.....
EV1 EV3
7-bit Master receiver:
Address
EV3
EV3
EV3-1
EV4
S
A
A
A
P
EV5
7-bit Master transmitter:
Address
EV6
EV7
A
EV7
A
EV7
S
A
Data1
Data2
DataN
.....
A
P
EV5
10-bit Slave receiver:
Header Address
EV6 EV8
EV8
A
EV8
EV8
S
A
A
Data1
DataN
EV3
A
P
.....
EV1
EV2
EV2
EV4
10-bit Slave transmitter:
Sr Header
Address
A
Data1
Data1
A
DataN
A
P
....
.
EV1 EV3
EV6 EV8
EV3-1
A
EV4
P
10-bit Master transmitter:
S
Header
A
A
A
DataN
DataN
.....
EV5
EV9
EV8
EV8
10-bit Master receiver:
Sr
Header
A
Data1
A
A
P
.....
EV5
EV6
EV7
EV7
Legend:
S = Start, Sr = Repeated Start, P = Stop, A = Acknowledge, NA = Non-acknowledge, EVx = Event (with interrupt if ITE = 1)
EV1: EVF = 1, ADSL = 1, cleared by reading SR1 register.
EV2: EVF = 1, BTF = 1, cleared by reading SR1 register followed by reading DR register.
EV3: EVF = 1, BTF = 1, cleared by reading SR1 register followed by writing DR register.
EV3-1: EVF = 1, AF = 1, BTF = 1; AF is cleared by reading SR1 register. BTF is cleared by releasing the lines (STOP = 1, STOP = 0) or
by writing DR register (DR = FFh). Note: If lines are released by STOP = 1, STOP = 0, the subsequent EV4 is not seen.
EV4: EVF = 1, STOPF = 1, cleared by reading SR2 register.
EV5: EVF = 1, SB = 1, cleared by reading SR1 register followed by writing DR register.
EV6: EVF = 1, cleared by reading SR1 register followed by writing CR register (for example PE = 1).
EV7: EVF = 1, BTF = 1, cleared by reading SR1 register followed by reading DR register.
EV8: EVF = 1, BTF = 1, cleared by reading SR1 register followed by writing DR register.
EV9: EVF = 1, ADD10 = 1, cleared by reading SR1 register followed by writing DR register.
171/250
I2C bus interface (I2C)
ST72325xxx-Auto
16.5
Low power modes
2
Table 81. Effect of low power modes on I C
Mode
Effect
No effect on I2C interface.
Wait
I2C interrupts cause the device to exit from Wait mode.
I2C registers are frozen.
In Halt mode, the I2C interface is inactive and does not acknowledge data on the bus. The
I2C interface resumes operation when the MCU is woken up by an interrupt with “exit from
Halt mode” capability.
Halt
16.6
Interrupts
Figure 71. Interrupt control logic diagram
ADD10
ITE
BTF
ADSL
SB
INTERRUPT
EVF
AF
STOPF
ARLO
BERR
*
* EVF can also be set by EV6 or an error from the SR2 register.
2
Table 82. I C interrupt control/wake-up capability
Enable
control bit
Exit from Exit from
Interrupt event
Event flag
Wait
Halt
10-bit Address Sent Event (Master mode)
End of Byte Transfer Event
ADD10
BTF
Address Matched Event (Slave mode)
Start Bit Generation Event (Master mode)
Acknowledge Failure Event
ADSEL
SB
ITE
Yes
No
AF
Stop Detection Event (Slave mode)
Arbitration Lost Event (Multimaster configuration)
Bus Error Event
STOPF
ARLO
BERR
2
Note:
The I C interrupt events are connected to the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding Enable Control bit is set and the I-bit in the
CC register is reset (RIM instruction).
172/250
ST72325xxx-Auto
I2C bus interface (I2C)
16.7
Register description
2
16.7.1
I C control register (CR)
CR
Reset value: 0000 0000 (00h)
7
6
5
4
3
2
1
0
Reserved
-
PE
ENGC
START
ACK
STOP
ITE
RW
RW
RW
RW
RW
RW
Table 83. CR register description
Bit Name
Function
7:6
-
Reserved. Forced to 0 by hardware.
Peripheral enable
This bit is set and cleared by software.
0: Peripheral disabled
1: Master/Slave capability
Notes:
- When PE = 0, all the bits of the CR register and the SR register except the Stop
bit are reset. All outputs are released while PE = 0
5
PE
- When PE = 1, the corresponding I/O pins are selected by hardware as alternate
functions.
To enable the I2C interface, write the CR register TWICE with PE = 1 as the first
write only activates the interface (only PE is set).
Enable General Call
This bit is set and cleared by software. It is also cleared by hardware when the
interface is disabled (PE = 0). The 00h General Call address is acknowledged (01h
ignored).
4
ENGC
0: General Call disabled
1: General Call enabled
Note: In accordance with the I2C standard, when GCAL addressing is enabled, an
I2C slave can only receive data. It will not transmit data to the master.
Generation of a Start condition
This bit is set and cleared by software. It is also cleared by hardware when the
interface is disabled (PE = 0) or when the Start condition is sent (with interrupt
generation if ITE = 1).
In Master mode
0: No start generation
1: Repeated start generation
In Slave mode
0: No start generation
1: Start generation when the bus is free
3
2
START
Acknowledge enable
This bit is set and cleared by software. It is also cleared by hardware when the
interface is disabled (PE = 0).
ACK
0: No acknowledge returned
1: Acknowledge returned after an address byte or a data byte is received
173/250
I2C bus interface (I2C)
ST72325xxx-Auto
Table 83. CR register description (continued)
Bit Name Function
Generation of a Stop condition
This bit is set and cleared by software. It is also cleared by hardware in master
mode.
Note: This bit is not cleared when the interface is disabled (PE = 0).
In Master mode
0: No stop generation
1
STOP
1: Stop generation after the current byte transfer or after the current Start condition
is sent. The STOP bit is cleared by hardware when the Stop condition is sent.
In Slave mode
0: No stop generation
1: Release the SCL and SDA lines after the current byte transfer (BTF = 1). In this
mode the STOP bit has to be cleared by software.
Interrupt enable
This bit is set and cleared by software and cleared by hardware when the interface
is disabled (PE = 0).
0: Interrupts disabled
1: Interrupts enabled
0
ITE
Refer to Figure 71 and Table 82 for the relationship between the events and the
interrupt.
SCL is held low when the ADD10, SB, BTF or ADSL flags or an EV6 event (see
Figure 70) is detected.
2
16.7.2
I C status register 1 (SR1)
SR1
Reset value: 0000 0000 (00h)
7
6
5
4
3
2
1
0
EVF
ADD10
TRA
BUSY
BTF
ADSL
M/SL
SB
RO
RO
RO
RO
RO
RO
RO
RO
Table 84. SR1 register description
Bit Name
Function
Event flag
This bit is set by hardware as soon as an event occurs. It is cleared by software
reading SR2 register in case of error event or as described in Figure 70. It is also
cleared by hardware when the interface is disabled (PE = 0).
0: No event
1: One of the following events has occurred:
- BTF = 1 (Byte received or transmitted)
7
EVF
- ADSL = 1 (Address matched in Slave mode while ACK = 1)
- SB = 1 (Start condition generated in Master mode)
- AF = 1 (No acknowledge received after byte transmission)
- STOPF = 1 (Stop condition detected in Slave mode)
- ARLO = 1 (Arbitration lost in Master mode)
- BERR = 1 (Bus error, misplaced Start or Stop condition detected)
- ADD10 = 1 (Master has sent header byte)
- Address byte successfully transmitted in Master mode
174/250
ST72325xxx-Auto
I2C bus interface (I2C)
Table 84. SR1 register description (continued)
Bit Name Function
10-bit addressing in Master mode
This bit is set by hardware when the master has sent the first byte in 10-bit address
mode. It is cleared by software reading SR2 register followed by a write in the DR
register of the second address byte. It is also cleared by hardware when the
peripheral is disabled (PE = 0).
0: No ADD10 event occurred.
1: Master has sent first address byte (header)
6
5
ADD10
Transmitter/Receiver
When BTF is set, TRA = 1 if a data byte has been transmitted. It is cleared
automatically when BTF is cleared. It is also cleared by hardware after detection of
Stop condition (STOPF = 1), loss of bus arbitration (ARLO = 1) or when the
interface is disabled (PE = 0).
TRA
0: Data byte received (if BTF = 1)
1: Data byte transmitted
Bus busy
This bit is set by hardware on detection of a Start condition and cleared by hardware
on detection of a Stop condition. It indicates a communication in progress on the
bus. The BUSY flag of the I2CSR1 register is cleared if a Bus Error occurs.
0: No communication on the bus
4
BUSY
1: Communication ongoing on the bus
Note: The BUSY flag is NOT updated when the interface is disabled (PE = 0). This
can have consequences when operating in Multimaster mode; that is, a second
active I2C master commencing a transfer with an unset BUSY bit can cause a
conflict resulting in lost data. A software workaround consists of checking that the
I2C is not busy before enabling the I2C Multimaster cell.
Byte transfer finished
This bit is set by hardware as soon as a byte is correctly received or transmitted with
interrupt generation if ITE = 1. It is cleared by software reading SR1 register
followed by a read or write of DR register. It is also cleared by hardware when the
interface is disabled (PE = 0).
Following a byte transmission, this bit is set after reception of the acknowledge clock
pulse. In case an address byte is sent, this bit is set only after the EV6 event (see
Figure 70). BTF is cleared by reading SR1 register followed by writing the next byte
in DR register.
3
BTF
Following a byte reception, this bit is set after transmission of the acknowledge clock
pulse if ACK = 1. BTF is cleared by reading SR1 register followed by reading the
byte from DR register.
The SCL line is held low while BTF = 1.
0: Byte transfer not done
1: Byte transfer succeeded
Address matched (Slave mode)
This bit is set by hardware as soon as the received slave address matched with the
OAR register content or a general call is recognized. An interrupt is generated if
ITE = 1. It is cleared by software reading SR1 register or by hardware when the
interface is disabled (PE = 0).
2
ADSL
The SCL line is held low while ADSL = 1.
0: Address mismatched or not received
1: Received address matched
175/250
I2C bus interface (I2C)
ST72325xxx-Auto
Table 84. SR1 register description (continued)
Bit Name Function
Master/Slave
This bit is set by hardware as soon as the interface is in Master mode (writing
START = 1). It is cleared by hardware after detecting a Stop condition on the bus or
a loss of arbitration (ARLO = 1). It is also cleared when the interface is disabled
(PE = 0).
0: Slave mode
1: Master mode
1
0
M/SL
Start bit (Master mode)
This bit is set by hardware as soon as the Start condition is generated (following a
write START = 1). An interrupt is generated if ITE = 1. It is cleared by software
reading SR1 register followed by writing the address byte in DR register. It is also
cleared by hardware when the interface is disabled (PE = 0).
0: No Start condition
SB
1: Start condition generated
2
16.7.3
I C status register 2 (SR2)
SR2
Reset value: 0000 0000 (00h)
7
6
5
4
3
2
1
0
Reserved
AF
STOPF
ARLO
BERR
GCAL
-
RO
RO
RO
RO
RO
Table 85. SR2 register description
Bit Name
Function
7:5
-
Reserved. Forced to 0 by hardware.
Acknowledge failure
This bit is set by hardware when no acknowledge is returned. An interrupt is
generated if ITE = 1. It is cleared by software reading SR2 register or by hardware
when the interface is disabled (PE = 0).
The SCL line is not held low while AF = 1 but by other flags (SB or BTF) that are set
at the same time.
4
AF
0: No acknowledge failure
1: Acknowledge failure
Note: When an AF event occurs, the SCL line is not held low; however, the SDA line
can remain low if the last bits transmitted are all 0. It is then necessary to release
both lines by software.
Stop detection (Slave mode)
This bit is set by hardware when a Stop condition is detected on the bus after an
acknowledge (if ACK = 1). An interrupt is generated if ITE = 1. It is cleared by
software reading SR2 register or by hardware when the interface is disabled
(PE = 0).
3
STOPF
The SCL line is not held low while STOPF = 1.
0: No Stop condition detected
1: Stop condition detected
176/250
ST72325xxx-Auto
I2C bus interface (I2C)
Table 85. SR2 register description (continued)
Bit Name Function
Arbitration lost
This bit is set by hardware when the interface loses the arbitration of the bus to
another master. An interrupt is generated if ITE = 1. It is cleared by software reading
SR2 register or by hardware when the interface is disabled (PE = 0).
After an ARLO event the interface switches back automatically to Slave mode
(M/SL = 0).
The SCL line is not held low while ARLO = 1.
2
ARLO
0: No arbitration lost detected
1: Arbitration lost detected
Note: In a Multimaster environment, when the interface is configured in Master
Receive mode it does not perform arbitration during the reception of the
Acknowledge bit. Mishandling of the ARLO bit from the I2CSR2 register may occur
when a second master simultaneously requests the same data from the same slave
and the I2C master does not acknowledge the data. The ARLO bit is then left at 0
instead of being set.
Bus error
This bit is set by hardware when the interface detects a misplaced Start or Stop
condition. An interrupt is generated if ITE = 1. It is cleared by software reading SR2
register or by hardware when the interface is disabled (PE = 0).
The SCL line is not held low while BERR = 1.
1
BERR
0: No misplaced Start or Stop condition
1: Misplaced Start or Stop condition
Note: If a Bus Error occurs, a Stop or a repeated Start condition should be
generated by the Master to re-synchronize communication, get the transmission
acknowledged and the bus released for further communication.
General Call (Slave mode)
This bit is set by hardware when a general call address is detected on the bus while
ENGC = 1. It is cleared by hardware detecting a Stop condition (STOPF = 1) or
when the interface is disabled (PE = 0).
0
GCAL
0: No general call address detected on bus
1: General call address detected on bus
2
16.7.4
I C clock control register (CCR)
CCR
Reset value: 0000 0000 (00h)
7
6
5
4
3
2
1
0
FM/SM
CC[6:0]
RW
RW
Table 86. CCR register description
Bit Name
Function
Fast/Standard I2C mode
This bit is set and cleared by software. It is not cleared when the interface is
7
FM/SM
disabled (PE = 0).
0: Standard I2C mode
1: Fast I2C mode
177/250
I2C bus interface (I2C)
Table 86. CCR register description (continued)
ST72325xxx-Auto
Bit Name
Function
7-bit clock divider
These bits select the speed of the bus (fSCL) depending on the I2C mode. They are
not cleared when the interface is disabled (PE = 0).
6:0 CC[6:0]
Refer to the Electrical characteristics chapter for the table of values.
Note: The programmed fSCL assumes no load on SCL and SDA lines.
2
16.7.5
I C data register (DR)
DR
Reset value: 0000 0000 (00h)
7
6
5
4
3
2
1
0
D[7:0]
RW
Table 87. DR register description
Bit Name
Function
8-bit Data Register
These bits contain the byte to be received or transmitted on the bus.
Transmitter mode: Byte transmission start automatically when the software writes
in the DR register.
Receiver mode: The first data byte is received automatically in the DR register
using the least significant bit of the address.
7:0 D[7:0]
Then, the following data bytes are received one by one after reading the DR
register.
2
16.7.6
I C own address register (OAR1)
OAR1
Reset value: 0000 0000 (00h)
7
6
5
4
3
2
1
0
ADD7
ADD6
ADD5
ADD4
ADD3
ADD2
ADD1
ADD0
RW
RW
RW
RW
RW
RW
RW
RW
178/250
ST72325xxx-Auto
I2C bus interface (I2C)
Table 88. OAR1 register description
Bit Name
Function
7-bit addressing mode
10-bit addressing mode
Interface address
These bits define the I2C bus address
of the interface. They are not cleared
when the interface is disabled
(PE = 0).
7:1 ADD[7:1]
Not applicable
Address direction bit
This bit is ‘don’t care’, the interface
acknowledges either 0 or 1. It is not
cleared when the interface is disabled
(PE = 0).
0
ADD0
Address 01h is always ignored.
Interface address
These are the least significant bits of
the I2C bus address of the interface.
They are not cleared when the
interface is disabled (PE = 0).
7:0 ADD[7:0]
Not applicable
2
16.7.7
I C own address register (OAR2)
OAR2
Reset value: 0100 0000 (40h)
7
6
5
4
3
2
1
0
FR[1:0]
RW
Reserved
ADD[9:8]
RW
Reserved
-
-
Table 89. OAR2 register description
Bit
Name
Function
Frequency bits
These bits are set by software only when the interface is disabled (PE = 0). To
configure the interface to I2C specified delays, select the value corresponding to
7:6
5:3
FR[1:0]
-
the CPU frequency fCPU
.
00: CPU < 6 MHz
f
01: fCPU = 6 to 8 MHz
Reserved
Interface address
These are the most significant bits of the I2C bus address of the interface (10-bit
mode only). They are not cleared when the interface is disabled (PE = 0).
2:1 ADD[9:8]
0
-
Reserved
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I2C bus interface (I2C)
ST72325xxx-Auto
2
Table 90. I C register map and reset values
Address
(Hex.)
Register
label
7
6
5
4
3
2
1
0
I2CCR
Reset value
PE
0
ENGC START
ACK
0
STOP
0
ITE
0
0018h
0019h
001Ah
001Bh
001Ch
001Dh
001Eh
0
0
0
0
I2CSR1
Reset value
EVF
0
ADD10
0
TRA
0
BUSY
0
BTF
0
ADSL
0
M/SL
0
SB
0
I2CSR2
Reset value
AF
0
STOPF ARLO BERR GCAL
0
0
0
0
0
0
0
I2CCCR
Reset value
FM/SM
0
CC6
0
CC5
0
CC4
0
CC3
0
CC2
0
CC1
0
CC0
0
I2COAR1
Reset value
ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
I2COAR2
Reset value
FR1
0
FR0
1
ADD9 ADD8
0
0
0
I2CDR
Reset value
MSB
0
LSB
0
0
0
0
180/250
ST72325xxx-Auto
10-bit A/D converter (ADC)
17
10-bit A/D converter (ADC)
17.1
Introduction
The on-chip Analog to Digital Converter (ADC) peripheral is a 10-bit, successive
approximation converter with internal sample and hold circuitry. This peripheral has up to 16
multiplexed analog input channels (refer to device pin out description) that allow the
peripheral to convert the analog voltage levels from up to 16 different sources.
The result of the conversion is stored in a 10-bit data register. The A/D converter is
controlled through a control/status register.
17.2
Main features
●
●
●
●
●
●
10-bit conversion
Up to 16 channels with multiplexed input
Linear successive approximation
Data register (DR) which contains the results
Conversion complete status flag
On/off bit (to reduce consumption)
The block diagram is shown in Figure 72.
Figure 72. ADC block diagram
f
CPU
DIV 4
DIV 2
0
1
f
ADC
CH3
EOC SPEED ADON
0
CH2
CH1
CH0
ADCCSR
4
AIN0
AIN1
ANALOG TO DIGITAL
CONVERTER
ANALOG
MUX
AINx
ADCDRH
D9
D8
D7
D6
D5
D4
D3
D2
ADCDRL
0
0
0
0
0
0
D1
D0
181/250
10-bit A/D converter (ADC)
ST72325xxx-Auto
17.3
Functional description
The conversion is monotonic, meaning that the result never decreases if the analog input
does not and never increases if the analog input does not.
If the input voltage (V ) is greater than V
(high-level voltage reference) then the
AIN
AREF
conversion result is FFh in the ADCDRH register and 03h in the ADCDRL register (without
overflow indication).
If the input voltage (V ) is lower than V
(low-level voltage reference) then the
SSA
AIN
conversion result in the ADCDRH and ADCDRL registers is 00 00h.
The A/D converter is linear and the digital result of the conversion is stored in the ADCDRH
and ADCDRL registers. The accuracy of the conversion is described in Chapter 19:
Electrical characteristics.
R
is the maximum recommended impedance for an analog input signal. If the impedance
AIN
is too high, this will result in a loss of accuracy due to leakage and sampling not being
completed in the allotted time.
17.3.1
17.3.2
A/D converter configuration
The analog input ports must be configured as input, no pull-up, no interrupt. Refer to the
Chapter 9: I/O ports. Using these pins as analog inputs does not affect the ability of the port
to be read as a logic input.
In the ADCCSR register:
●
Select the CS[3:0] bits to assign the analog channel to convert.
Starting the conversion
In the ADCCSR register:
●
Set the ADON bit to enable the A/D converter and to start the conversion. From this
time on, the ADC performs a continuous conversion of the selected channel.
When a conversion is complete:
●
The EOC bit is set by hardware.
●
The result is in the ADCDR registers.
A read to the ADCDRH or a write to any bit of the ADCCSR register resets the EOC bit.
To read the 10 bits, perform the following steps:
1. Poll the EOC bit.
2. Read the ADCDRL register.
3. Read the ADCDRH register. This clears EOC automatically.
Note:
The data is not latched, so both the low and the high data register must be read before the
next conversion is complete, so it is recommended to disable interrupts while reading the
conversion result.
To read only 8 bits, perform the following steps:
1. Poll the EOC bit.
2. Read the ADCDRH register. This clears EOC automatically.
182/250
ST72325xxx-Auto
10-bit A/D converter (ADC)
17.3.3
Changing the conversion channel
The application can change channels during conversion. When software modifies the
CH[3:0] bits in the ADCCSR register, the current conversion is stopped, the EOC bit is
cleared, and the A/D converter starts converting the newly selected channel.
17.4
Low power modes
Note:
The A/D converter may be disabled by resetting the ADON bit. This feature allows reduced
power consumption when no conversion is needed and between single shot conversions.
Table 91. Effect of low power modes on ADC
Mode
Effect
Wait
No effect on A/D converter
A/D converter disabled.
Halt
After wake-up from Halt mode, the A/D converter requires a stabilization time tSTAB (see
Electrical characteristics) before accurate conversions can be performed.
17.5
Interrupts
None.
17.6
ADC registers
17.6.1
Control/status register (ADCCSR)
ADCCSR
Reset value: 0000 0000 (00h)
7
6
5
4
3
2
1
0
EOC
SPEED
ADON
Reserved
CH[3:0]
RW
RO
RW
RW
-
Table 92. ADCCSR register description
Bit Name
Function
End of Conversion
This bit is set by hardware. It is cleared by hardware when software reads the
ADCDRH register or writes to any bit of the ADCCSR register.
0: Conversion is not complete
7
6
EOC
1: Conversion complete
ADC clock selection
This bit is set and cleared by software.
0: fADC = fCPU/4
SPEED
1: fADC = fCPU/2
183/250
10-bit A/D converter (ADC)
ST72325xxx-Auto
Table 92. ADCCSR register description (continued)
Bit Name Function
A/D Converter on
This bit is set and cleared by software.
0: Disable ADC and stop conversion
1: Enable ADC and start conversion
5
4
ADON
-
Reserved. Must be kept cleared
Channel Selection
These bits are set and cleared by software. They select the analog input to convert.
0000: Channel pin = AIN0
0001: Channel pin = AIN1
0010: Channel pin = AIN2
0011: Channel pin = AIN3
0100: Channel pin = AIN4
0101: Channel pin = AIN5
0110: Channel pin = AIN6
0111: Channel pin = AIN7
1000: Channel pin = AIN8
3:0 CH[3:0]
1001: Channel pin = AIN9
1010: Channel pin = AIN10
1011: Channel pin = AIN11
1100: Channel pin = AIN12
1101: Channel pin = AIN13
1110: Channel pin = AIN14
1111: Channel pin = AIN15
Note: The number of channels is device dependent. Refer to the device pinout
description.
17.6.2
Data register (ADCDRH)
ADCDRH
Reset value: 0000 0000 (00h)
7
6
5
4
3
2
1
0
D[9:2]
RO
Table 93. ADCDRH register description
Bit Name
Function
7:0 D[9:2] MSB of Converted Analog Value
184/250
ST72325xxx-Auto
10-bit A/D converter (ADC)
17.6.3
Data register (ADCDRL)
ADCDRL
7
Reset value: 0000 0000 (00h)
6
5
4
3
2
1
0
Reserved
-
D[1:0]
RO
Table 94. ADCDRL register description
Bit Name
Function
7:2
-
Reserved. Forced by hardware to 0.
1:0 D[1:0] LSB of Converted Analog Value
17.6.4
ADC register map and reset values
Table 95. ADC register map and reset values
Address
(Hex.)
Register
label
7
6
5
4
3
2
1
0
ADCCSR
Reset value
EOC SPEED ADON
CH3
0
CH2
0
CH1
0
CH0
0
0070h
0071h
0072h
0
0
0
0
ADCDRH
Reset value
D9
0
D8
0
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
ADCDRL
Reset value
D1
0
D0
0
0
0
0
0
0
0
185/250
Instruction set
ST72325xxx-Auto
18
Instruction set
18.1
CPU addressing modes
The CPU features 17 different addressing modes which can be classified in seven main
groups as listed in the following table:
Table 96. Addressing modes
Group
Example
Inherent
Immediate
Direct
NOP
LD A,#$55
LD A,$55
Indexed
Indirect
LD A,($55,X)
LD A,([$55],X)
JRNE loop
Relative
Bit operation
BSET byte,#5
The CPU instruction set is designed to minimize the number of bytes required per
instruction: To do so, most of the addressing modes may be divided in two submodes called
long and short:
●
Long addressing mode is more powerful because it can use the full 64 Kbyte address
space; however, it uses more bytes and more CPU cycles.
●
Short addressing mode is less powerful because it can generally only access page
zero (0000h - 00FFh range), but the instruction size is more compact, and faster. All
memory to memory instructions use short addressing modes only (CLR, CPL, NEG,
BSET, BRES, BTJT, BTJF, INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP).
The ST7 Assembler optimizes the use of long and short addressing modes.
Table 97. CPU addressing mode overview
Pointer
Destination address
(Hex.)
Pointer
size
(Hex.)
Length
(bytes)
Mode
Syntax
Inherent
Immediate
Short
nop
+ 0
+ 1
+ 1
+ 2
+ 0
+ 1
+ 2
+ 2
+ 2
+ 2
ld A,#$55
ld A,$10
Direct
Direct
00..FF
Long
ld A,$1000
0000..FFFF
00..FF
No Offset Direct
Indexed ld A,(X)
Short
Long
Short
Long
Short
Direct
Indexed ld A,($10,X)
Indexed ld A,($1000,X)
ld A,[$10]
00..1FE
Direct
0000..FFFF
Indirect
Indirect
00..FF
00..FF
00..FF
00..FF
byte
word
byte
ld A,[$10.w]
0000..FFFF
00..1FE
Indirect Indexed ld A,([$10],X)
186/250
ST72325xxx-Auto
Instruction set
Table 97. CPU addressing mode overview (continued)
Pointer
Destination address
(Hex.)
Pointer
size
(Hex.)
Length
(bytes)
Mode
Syntax
Long
Indirect Indexed ld A,([$10.w],X) 0000..FFFF
00..FF
00..FF
00..FF
00..FF
word
byte
byte
byte
+ 2
+ 1
+ 2
+ 1
+ 2
+ 2
+ 3
Relative
Direct
jrne loop
PC+/-127
PC+/-127
00..FF
Relative
Bit
Indirect
Direct
jrne [$10]
bset $10,#7
bset [$10],#7
Bit
Indirect
Direct
00..FF
Bit
Relative btjt $10,#7,skip 00..FF
Bit
Indirect Relative btjt [$10],#7,skip 00..FF
18.1.1
Inherent
All Inherent instructions consist of a single byte. The opcode fully specifies all the required
information for the CPU to process the operation.
Table 98. Inherent instructions
Instruction
Function
NOP
No operation
S/W Interrupt
TRAP
WFI
Wait For Interrupt (Low Power Mode)
Halt Oscillator (Lowest Power Mode)
Sub-routine Return
HALT
RET
IRET
SIM
Interrupt Sub-routine Return
Set Interrupt Mask (level 3)
Reset Interrupt Mask (level 0)
Set Carry Flag
RIM
SCF
RCF
Reset Carry Flag
RSP
Reset Stack Pointer
Load
LD
CLR
Clear
PUSH/POP
INC/DEC
TNZ
Push/Pop to/from the stack
Increment/Decrement
Test Negative or Zero
1 or 2 Complement
CPL, NEG
MUL
Byte Multiplication
SLL, SRL, SRA, RLC, RRC
SWAP
Shift and Rotate Operations
Swap Nibbles
187/250
Instruction set
ST72325xxx-Auto
18.1.2
Immediate
Immediate instructions have 2 bytes. The first byte contains the opcode and the second byte
contains the operand value.
Table 99. Immediate instructions
Instruction
Function
LD
Load
CP
Compare
BCP
Bit Compare
Logical Operations
Arithmetic Operations
AND, OR, XOR
ADC, ADD, SUB, SBC
18.1.3
Direct
In Direct instructions, the operands are referenced by their memory address.
The direct addressing mode consists of two submodes:
Direct (short)
The address is a byte, thus requires only one byte after the opcode, but only allows 00 - FF
addressing space.
Direct (long)
The address is a word, thus allowing 64 Kbyte addressing space, but requires 2 bytes after
the opcode.
18.1.4
Indexed (no offset, short, long)
In this mode, the operand is referenced by its memory address, which is defined by the
unsigned addition of an index register (X or Y) with an offset.
The indexed addressing mode consists of three submodes:
Indexed (no offset)
There is no offset, (no extra byte after the opcode), and allows 00 - FF addressing space.
Indexed (short)
The offset is a byte, thus requires only one byte after the opcode and allows 00 - 1FE
addressing space.
Indexed (long)
The offset is a word, thus allowing 64 Kbyte addressing space and requires 2 bytes after the
opcode.
188/250
ST72325xxx-Auto
Instruction set
18.1.5
Indirect (short, long)
The required data byte to do the operation is found by its memory address, located in
memory (pointer).
The pointer address follows the opcode. The indirect addressing mode consists of two
submodes:
Indirect (short)
The pointer address is a byte, the pointer size is a byte, thus allowing 00 - FF addressing
space, and requires 1 byte after the opcode.
Indirect (long)
The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing
space, and requires 1 byte after the opcode.
18.1.6
Indirect indexed (short, long)
This is a combination of indirect and short indexed addressing modes. The operand is
referenced by its memory address, which is defined by the unsigned addition of an index
register value (X or Y) with a pointer value located in memory. The pointer address follows
the opcode.
The indirect indexed addressing mode consists of two submodes:
Indirect indexed (short)
The pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1FE addressing
space, and requires 1 byte after the opcode.
Indirect indexed (long)
The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing
space, and requires 1 byte after the opcode.
Table 100. Instructions supporting direct, indexed, indirect, and indirect indexed
addressing modes
Type
Instruction
Function
LD
CP
Load
Compare
AND, OR, XOR
ADC, ADD, SUB, SBC
BCP
Logical operations
Long and short instructions
Arithmetic Additions/Subtractions
operations
Bit Compare
189/250
Instruction set
ST72325xxx-Auto
Table 100. Instructions supporting direct, indexed, indirect, and indirect indexed
addressing modes (continued)
Type
Instruction
Function
CLR
Clear
INC, DEC
TNZ
Increment/Decrement
Test Negative or Zero
1 or 2 Complement
CPL, NEG
BSET, BRES
BTJT, BTJF
Short instructions only
Bit Operations
Bit Test and Jump Operations
SLL, SRL, SRA, RLC, RRC Shift and Rotate Operations
SWAP
Swap Nibbles
CALL, JP
Call or Jump subroutine
18.1.7
Relative (direct, indirect)
This addressing mode is used to modify the PC register value, by adding an 8-bit signed
offset to it.
Table 101. Available relative direct/indirect instructions
Instruction
Function
JRxx
Conditional Jump
Call Relative
CALLR
The relative addressing mode consists of two submodes:
Relative (direct)
The offset is following the opcode.
Relative (indirect)
The offset is defined in memory, which address follows the opcode.
18.2
Instruction groups
The ST7 family devices use an Instruction Set consisting of 63 instructions. The instructions
may be subdivided into 13 main groups as illustrated in the following table:
Table 102. Instruction groups
Group
Load and Transfer
Instructions
LD
CLR
Stack operation
PUSH POP
RSP
BCP
Increment/Decrement
Compare and Tests
INC
CP
DEC
TNZ
190/250
ST72325xxx-Auto
Instruction set
Table 102. Instruction groups (continued)
Group
Logical operations
Instructions
AND
OR
XOR CPL NEG
Bit Operation
BSET BRES
BTJT BTJF
Conditional Bit Test and Branch
Arithmetic operations
ADC
SLL
ADD
SRL
JRT
SUB SBC MUL
Shift and Rotates
SRA RLC RRC SWAP SLA
JRF JP CALL CALLR NOP RET
Unconditional Jump or Call
Conditional Branch
JRA
JRxx
TRAP
SIM
Interruption management
Condition Code Flag modification
WFI
RIM
HALT IRET
SCF RCF
18.2.1
Using a prebyte
The instructions are described with one to four opcodes.
In order to extend the number of available opcodes for an 8-bit CPU (256 opcodes), three
different prebyte opcodes are defined. These prebytes modify the meaning of the instruction
they precede.
The whole instruction becomes:
PC - 2
PC - 1
PC
End of previous instruction
Prebyte
Opcode
PC + 1
Additional word (0 to 2) according to the number of bytes required to
compute the effective address
These prebytes enable instruction in Y as well as indirect addressing modes to be
implemented. They precede the opcode of the instruction in X or the instruction using direct
addressing mode. The prebytes are:
PDY 90
Replace an X based instruction using immediate, direct, indexed, or
inherent addressing mode by a Y one.
PIX 92
Replace an instruction using direct, direct bit, or direct relative
addressing mode to an instruction using the corresponding indirect
addressing mode.
It also changes an instruction using X indexed addressing mode to an
instruction using indirect X indexed addressing mode.
PIY 91
Replace an instruction using X indirect indexed addressing mode by a Y
one.
191/250
Instruction set
ST72325xxx-Auto
Table 103. Instruction set overview
Mnemo
Description
Add with Carry
Function/Example
Dst
Src
I1
H
I0
N
Z
C
ADC
ADD
AND
BCP
A = A + M + C
A = A + M
A
M
M
M
M
H
H
N
N
N
N
Z
Z
Z
Z
C
C
Addition
A
Logical And
A = A . M
A
Bit compare A, Memory
tst (A . M)
A
BRES Bit Reset
bres Byte, #3
bset Byte, #3
btjf Byte, #3, Jmp1
btjt Byte, #3, Jmp1
M
M
M
M
BSET
BTJF
BTJT
CALL
Bit Set
Jump if bit is false (0)
Jump if bit is true (1)
Call subroutine
C
C
CALLR Call subroutine relative
CLR
CP
Clear
reg, M
reg
0
N
N
N
1
Z
Z
Z
Arithmetic Compare
One Complement
Decrement
tst(Reg - M)
A = FFH-A
dec Y
M
C
1
CPL
DEC
HALT
IRET
INC
reg, M
reg, M
Halt
1
0
Interrupt routine return
Increment
Pop CC, A, X, PC
inc X
I1
H
I0
N
N
Z
Z
C
reg, M
JP
Absolute Jump
Jump relative always
Jump relative
jp [TBL.w]
JRA
JRT
JRF
JRIH
JRIL
JRH
JRNH
JRM
Never jump
jrf *
Jump if ext. INT pin = 1
Jump if ext. INT pin = 0
Jump if H = 1
(ext. INT pin high)
(ext. INT pin low)
H = 1 ?
Jump if H = 0
H = 0 ?
Jump if I1:0 = 11
I1:0 = 11 ?
I1:0 <> 11 ?
N = 1 ?
JRNM Jump if I1:0 <> 11
JRMI
JRPL
JREQ
JRNE
JRC
Jump if N = 1 (minus)
Jump if N = 0 (plus)
Jump if Z = 1 (equal)
Jump if Z = 0 (not equal)
Jump if C = 1
N = 0 ?
Z = 1 ?
Z = 0 ?
C = 1 ?
JRNC
Jump if C = 0
C = 0 ?
JRULT Jump if C = 1
JRUGE Jump if C = 0
Unsigned <
Jmp if unsigned >=
192/250
ST72325xxx-Auto
Instruction set
Table 103. Instruction set overview (continued)
Mnemo
Description
Function/Example
Dst
Src
I1
H
I0
N
Z
C
JRUGT Jump if (C + Z = 0)
JRULE Jump if (C + Z = 1)
Unsigned >
Unsigned <=
dst <= src
X,A = X * A
neg $10
LD
Load
reg, M
M, reg
N
N
N
N
Z
Z
Z
Z
MUL
NEG
NOP
OR
Multiply
A, X, Y X, Y, A
reg, M
0
0
Negate (2's compl)
No Operation
OR operation
C
A = A + M
pop reg
pop CC
push Y
C = 0
A
M
reg
CC
M
M
POP
Pop from the Stack
M
I1
1
H
I0
0
C
0
PUSH Push onto the Stack
reg, CC
RCF
RET
RIM
RLC
RRC
RSP
SBC
SCF
SIM
Reset carry flag
Subroutine Return
Enable Interrupts
Rotate left true C
Rotate right true C
Reset Stack Pointer
Subtract with Carry
Set carry flag
I1:0 = 10 (level 0)
C <= A <= C
C => A => C
S = Max allowed
A = A - M - C
C = 1
reg, M
reg, M
N
N
Z
Z
C
C
A
M
N
Z
C
1
Disable Interrupts
Shift left Arithmetic
Shift left Logic
I1:0 = 11 (level 3)
C <= A <= 0
C <= A <= 0
0 => A => C
A7 => A => C
A = A - M
1
1
SLA
SLL
reg, M
reg, M
reg, M
reg, M
A
N
N
0
Z
Z
Z
Z
Z
Z
Z
C
C
C
C
C
SRL
SRA
SUB
Shift right Logic
Shift right Arithmetic
Subtraction
N
N
N
N
M
M
SWAP SWAP nibbles
A7-A4 <=> A3-A0
tnz lbl1
reg, M
TNZ
Test for Neg & Zero
TRAP
WFI
S/W trap
S/W interrupt
1
1
1
0
Wait for Interrupt
Exclusive OR
XOR
A = A XOR M
A
N
Z
193/250
Electrical characteristics
ST72325xxx-Auto
19
Electrical characteristics
19.1
Parameter conditions
Unless otherwise specified, all voltages are referred to V
.
SS
19.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at T = 25°C and T = T (given by the
A
A
Amax
selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean 3Σ).
19.1.2
19.1.3
19.1.4
Typical values
Unless otherwise specified, typical data is based on T = 25°C, V = 5V. The typical values
are given only as design guidelines and are not tested.
A
DD
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 73.
Figure 73. Pin loading conditions
ST7 PIN
C
L
19.1.5
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 74.
Figure 74. Pin input voltage
ST7 PIN
V
IN
194/227
ST72325xxx-Auto
Electrical characteristics
19.2
Absolute maximum ratings
Stresses above those listed as “absolute maximum ratings” may cause permanent damage
to the device. This is a stress rating only and functional operation of the device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
19.2.1
Voltage characteristics
Table 104. Voltage characteristics
Symbol
Ratings
Maximum value
Unit
VDD - VSS
Supply voltage
6.5
V
PP - VSS
Programming voltage
13
V
Input voltage on true open-drain pin
VSS - 0.3 to 6.5
(1)
VIN
Input voltage on any other pin
VSS - 0.3 to VDD + 0.3
|∆VDDx| and |∆VSSx
|
Variations between different digital power pins
Variations between digital and analog ground pins
Electrostatic discharge voltage (Human Body Model)
Electrostatic discharge voltage (Machine Model)
50
50
mV
|VSSA - VSSx
VESD(HBM)
VESD(MM)
|
See Section 19.7.3 on page 209.
1. Directly connecting the RESET and I/O pins to VDD or VSS could damage the device if an unintentional internal reset is
generated or an unexpected change of the I/O configuration occurs (for example, due to a corrupted program counter). To
guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7kΩ for RESET,
10kΩ for I/Os). For the same reason, unused I/O pins must not be directly tied to VDD or VSS
.
195/227
Electrical characteristics
ST72325xxx-Auto
19.2.2
Current characteristics
Table 105. Current characteristics
Symbol
Ratings
Maximum value Unit
32-pin devices
75
mA
150
Total current into VDD power lines
(source) and VSS ground lines (sink)
(1)
I
VDD / IVSS
44-/64-pin devices
Output current sunk by any standard I/O and control pin
Output current sunk by any high sink I/O pin
Output current source by any I/Os and control pin
Injected current on VPP pin
20
40
- 25
5
IIO
Injected current on RESET pin
5
5
mA
(2)(3)
(2)
IINJ(PIN)
Injected current on OSC1 and OSC2 pins
Injected current on PB0 pin
+ 5
5
Injected current on any other pin(4)(5)
ΣIINJ(PIN)
Total injected current (sum of all I/O and control pins)(4)
25
1. All power (VDD) and ground (VSS) lines must always be connected to the external supply.
2. IINJ(PIN) must never be exceeded. This is implicitly ensured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS. For true open-drain
pads, there is no positive injection current, and the corresponding VIN maximum must always be respected.
3. Negative injection may disturb the analog performance of the device. See Note 1 in Table 137: ADC
accuracy on page 227.
4. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values). These results are based on
characterization with ΣIINJ(PIN) maximum current injection on four I/O port pins of the device.
5. True open-drain I/O port pins do not accept positive injection.
19.2.3
Thermal characteristics
Table 106. Thermal characteristics
Symbol
TSTG Storage temperature range
TJ
Ratings
Value
Unit
-65 to +150
°C
Maximum junction temperature (see Section 20.2: Thermal characteristics on page 232)
196/227
ST72325xxx-Auto
Electrical characteristics
19.3
Operating conditions
19.3.1
General operating conditions
Table 107. General operating conditions
Symbol
Parameter
Internal clock frequency
Conditions
Min
Max
Unit
fCPU
0
8
MHz
Standard voltage range (except Flash
Write/Erase)
3.8
4.5
5.5
VDD
V
Operating voltage for Flash Write/Erase
V
PP = 11.4 to 12.6V
5.5
85
A suffix version
B suffix version
C suffix version
TA
Ambient temperature range
-40
105
125
°C
Note:
Some temperature ranges are only available with a specific package and memory size.
Refer to Chapter 21: Device configuration and ordering information.
Figure 75. f
max versus V
DD
CPU
f
[MHz]
CPU
FUNCTIONALITY
GUARANTEED
IN THIS AREA
(UNLESS
8
6
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
OTHERWISE
SPECIFIED
4
2
IN THE TABLES
OF PARAMETRIC
DATA)
1
0
3.5
3.8 4.0
4.5
5.5
SUPPLY VOLTAGE [V]
197/227
Electrical characteristics
ST72325xxx-Auto
19.3.2
Operating conditions with low voltage detector (LVD)
Subject to general operating conditions for V , f
, and T .
A
DD CPU
Table 108. Operating conditions with low voltage detector (LVD)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VD level = High in option byte
4.0(1)
4.2
3.75
3.15
4.0
4.5
Reset release threshold
(VDD rise)
VIT+(LVD)
VD level = Med. in option byte(2) 3.55(1)
4.0(1)
VD level = Low in option byte(2)
2.95(1)
3.35(1)
4.25(1)
3.75(1)
3.15(1)
V
VD level = High in option byte
3.8
Reset generation threshold
(VDD fall)
VIT-(LVD)
VD level = Med. in option byte(2) 3.35(1)
3.55
3.0
VD level = Low in option byte(2)
2.8(1)
LVD voltage threshold
hysteresis
Vhys(LVD)
VIT+(LVD)-VIT-(LVD)
200
mV
-
VtPOR VDD rise time(2)
LVD enabled
6µs/V
100ms/V
40
VDD glitches filtered (not
tg(VDD)
ns
detected) by LVD(3)
1. Data based on characterization results
2. Data based on characterization results, not tested in production
3. If the medium or low thresholds are selected, the detection may occur outside the specified operating voltage range. Below
3.8V, device operation is not guaranteed.
19.3.3
Auxiliary voltage detector (AVD) thresholds
Subject to general operating conditions for V , f
, and T .
A
DD CPU
Table 109. Auxiliary voltage detector (AVD) thresholds
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VD level = High in option byte
4.4(1)
4.6
4.15
3.6
4.9(1)
4.4(1)
3.8(1)
4.65(1)
4.2(1)
3.6(1)
1⇒0 AVDF flag toggle threshold
(VDD rise)
VIT+(AVD)
VD level = Med. in option byte 3.95(1)
VD level = Low in option byte
3.4(1)
4.2(1)
V
VD level = High in option byte
4.4
0⇒1 AVDF flag toggle threshold
(VDD fall)
VIT-(AVD)
VD level = Med. in option byte 3.75(1)
4.0
VD level = Low in option byte
VIT+(AVD)-VIT-(AVD)
3.2(1)
3.4
Vhys(AVD) AVD voltage threshold hysteresis
200
mV
Voltage drop between AVD flag set
and LVD reset activated
∆VIT-
VIT-(AVD)-VIT-(LVD)
450
1. Data based on characterization results
198/227
ST72325xxx-Auto
Electrical characteristics
19.3.4
External voltage detector (EVD) thresholds
Subject to general operating conditions for V , f
, and T .
A
DD CPU
Table 110. External voltage detector (EVD) thresholds
Symbol Parameter
VIT+(EVD) 1⇒0 AVDF flag toggle threshold (VDD rise(1)
VIT-(EVD)
0⇒1 AVDF flag toggle threshold (VDD fall)(1)
Conditions
Min
Typ
Max
Unit
1.15
1.1
1.26
1.2
1.35
1.3
V
Vhys(EVD) EVD voltage threshold hysteresis
VIT+(EVD)-VIT-(EVD)
200
mV
1. Data based on characterization results, not tested in production
199/227
Electrical characteristics
ST72325xxx-Auto
19.4
Supply current characteristics
The following current consumption specified for the ST7 functional operating modes over
temperature range does not take into account the clock source current consumption. To
obtain the total device consumption, the two current values must be added (except for Halt
mode, for which the clock is stopped).
19.4.1
Current consumption
Table 111. Current consumption
Symbol
Parameter
Conditions
Typ
Max(1) Unit
fOSC = 2 MHz, fCPU = 1 MHz
fOSC = 4 MHz, fCPU = 2 MHz
fOSC = 8 MHz, fCPU = 4 MHz
fOSC = 16 MHz, fCPU = 8 MHz
1.3
2.0
3.6
7.1
3.0
5.0
mA
8.0
Supply current in Run
mode(2)
15.0
fOSC = 2 MHz, fCPU = 62.5 kHz
fOSC = 4 MHz, fCPU = 125 kHz
fOSC = 8 MHz, fCPU = 250 kHz
600
700
800
2700
3000
3600
Supply current in Slow
mode(2)
µA
f
OSC = 16 MHz, fCPU = 500 kHz
1100
4000
fOSC = 2 MHz, fCPU = 1 MHz
fOSC = 4 MHz, fCPU = 2 MHz
fOSC = 8 MHz, fCPU = 4 MHz
fOSC = 16 MHz, fCPU = 8 MHz
0.8
1.2
2.0
3.5
3.0
4.0
mA
5.0
Supply current in Wait
mode(2)
7.0
IDD
fOSC = 2 MHz, fCPU = 62.5 kHz
fOSC = 4 MHz, fCPU = 125 kHz
fOSC = 8 MHz, fCPU = 250 kHz
fOSC = 16 MHz, fCPU = 500 kHz
580
650
770
1200
1300
1800
2000
Supply current in Slow Wait
mode(2)
µA
1050
-40°C ≤ TA ≤ +85°C
-40°C ≤ TA ≤ +125°C
fOSC = 2 MHz
<1
5
10
µA
50
Supply current in Halt
mode(3)
415
430
460
550
525
Supply current in Active Halt fOSC = 4 MHz
550
600
µA
mode(4)
fOSC = 8 MHz
fOSC = 16 MHz
700
1. Data based on characterization results, tested in production at VDD max. and fCPU max.
2. Measurements are done in the following conditions:
- Program executed from RAM, CPU running with RAM access
- All I/O pins in input mode with a static value at VDD or VSS (no load)
- All peripherals in reset state
- CSS and LVD disabled
- Clock input (OSC1) driven by external square wave
- In Slow and Slow Wait mode, fCPU is based on fOSC divided by 32
- To obtain the total current consumption of the device, add the clock source (Section 19.4.2) and the
peripheral power consumption (Section 19.4.3).
3. All I/O pins in push-pull 0 mode (when applicable) with a static value at VDD or VSS (no load), LVD
disabled. Data based on characterization results, tested in production at VDD max. and fCPU max.
4. Data based on characterization results, not tested in production. All I/O pins in push-pull 0 mode (when
applicable) with a static value at VDD or VSS (no load); clock input (OSC1) driven by external square wave,
LVD disabled. To obtain the total current consumption of the device, add the clock source consumption
(Section 19.4.2).
200/227
ST72325xxx-Auto
Electrical characteristics
19.4.2
Supply and clock managers
The previous current consumption specified for the ST7 functional operating modes over
temperature range does not take into account the clock source current consumption. To
obtain the total device consumption, the two current values must be added (except for Halt
mode).
Table 112. Oscillators, CSS, PLL and LVD current consumption
Symbol
Parameter
Conditions
Typ
Max
Unit
IDD(RCINT) Supply current of internal RC oscillator
625
Supply current of resonator
see section 19.5.3 on page
IDD(RES)
oscillator(1)(2)
204
µA
IDD(CSS) Clock security system supply current
IDD(PLL) PLL supply current
250
360
VDD = 5V
IDD(LVD) LVD supply current
150
300
1. Data based on characterization results done with the external components specified in Section 19.5.3, not
tested in production
2. As the oscillator is based on a current source, the consumption does not depend on the voltage.
201/227
Electrical characteristics
ST72325xxx-Auto
19.4.3
On-chip peripherals
Measured on LQFP64 generic board T = 25°C, f
= 4 MHz.
A
CPU
Table 113. On-chip peripherals current consumption
Symbol Parameter
Conditions
Typ
Unit
IDD(TIM) 16-bit timer supply current(1)
IDD(ART) ART PWM supply current(2)
IDD(SPI) SPI supply current(3)
VDD = 5.0V
VDD = 5.0V
50
75
µA
µA
VDD = 5.0V
400
µA
IDD(SCI) SCI supply current(4)
IDD(I2C) I2C supply current(5)
VDD = 5.0V
VDD = 5.0V
175
400
µA
µA
IDD(ADC) ADC supply current when converting(6)
1. Data based on a differential IDD measurement between reset configuration (timer counter running at
CPU/4) and timer counter stopped (only TIMD bit set). Data valid for one timer.
f
2. Data based on a differential IDD measurement between reset configuration (timer stopped) and timer
counter enabled (only TCE bit set).
3. Data based on a differential IDD measurement between reset configuration (SPI disabled) and a permanent
SPI master communication at maximum speed (data sent equal to 55h). This measurement includes the
pad toggling consumption.
4. Data based on a differential IDD measurement between SCI low power state (SCID = 1) and a permanent
SCI data transmit sequence.
5. Data based on a differential IDD measurement between reset configuration (I2C disabled) and a permanent
I2C master communication at 100 kHz (data sent equal to 55h). This measurement includes the pad
toggling consumption (27k ohm external pull-up on clock and data lines).
6. Data based on a differential IDD measurement between reset configuration and continuous A/D
conversions.
202/227
ST72325xxx-Auto
Electrical characteristics
19.5
Clock and timing characteristics
Subject to general operating conditions for V , f
, and T .
A
DD CPU
19.5.1
General timings
Table 114. General timings
Symbol
Parameter
Conditions
Min
Typ(1)
Max
Unit
2
3
12
1500
22
tCPU
ns
tc(INST) Instruction cycle time
fCPU = 8 MHz
fCPU = 8 MHz
250
10
375
Interrupt reaction time(2)
tv(IT)
tCPU
µs
tv(IT) = ∆tc(INST) + 10
1.25
2.75
1. Data based on typical application software.
2. Time measured between interrupt event and interrupt vector fetch. ∆tc(INST) is the number of tCPU cycles
needed to finish the current instruction execution.
19.5.2
External clock source
Table 115. External clock source
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VOSC1H OSC1 input pin high level voltage
VOSC1L OSC1 input pin low level voltage
0.7xVDD
VSS
VDD
V
0.3xVDD
tw(OSC1H)
tw(OSC1L)
OSC1 high or low time(1)
5
See Figure 76
ns
tr(OSC1)
tf(OSC1)
OSC1 rise or fall time(1)
15
1
Ilkg
OSC1 input leakage current
VSS < VIN < VDD
µA
1. Data based on design simulation and/or technology characteristics, not tested in production.
Figure 76. Typical application with an external clock source
90%
VOSC1H
10%
VOSC1L
tf(OSC1)
tw(OSC1H)
tr(OSC1)
tw(OSC1L)
OSC2
Not connected internally
fOSC
EXTERNAL
CLOCK SOURCE
Ilkg
OSC1
ST72XXX
203/227
Electrical characteristics
ST72325xxx-Auto
19.5.3
Crystal and ceramic resonator oscillators
The ST7 internal clock can be supplied with four different crystal/ceramic resonator
oscillators. All the information given in this paragraph is based on characterization results
with specified typical external components. In the application, the resonator and the load
capacitors have to be placed as close as possible to the oscillator pins in order to minimize
output distortion and start-up stabilization time. Refer to the crystal/ceramic resonator
manufacturer for more details (such as frequency, package or accuracy).
Table 116. Crystal and ceramic resonator oscillators
Symbol
Parameter
Conditions
Min Typ Max Unit
fOSC Oscillator frequency(1)
-
-
1
16 MHz
RF
Feedback resistor(2)
20
-
-
40
kΩ
Recommended load
capacitance versus
equivalent serial resistance of
the crystal or ceramic
resonator (RS)(3)
RS = 200Ω
RS = 200Ω
RS = 200Ω
RS = 100Ω
LP oscillator 20
MP oscillator 20
MS oscillator 15
HS oscillator 15
60
50
35
35
CL1
CL2
pF
LP oscillator
MP oscillator
MS oscillator
HS oscillator
426
425
456
660
i2
OSC2 driving current
VDD = 5V, VIN = VSS
-
-
µA
1. The oscillator selection can be optimized in terms of supply current using a high quality resonator with
small RS value. Refer to crystal/ceramic resonator manufacturer for more details.
2. Data based on characterization results, not tested in production. The relatively low value of the RF resistor
offers a good protection against issues resulting from use in a humid environment, due to the induced
leakage and the bias condition change. However, it is recommended to take this point into account if the
microcontroller is used in tough humidity conditions.
3. For CL1 and CL2 it is recommended to use high-quality ceramic capacitors in the 5pF to 25pF range (typ.)
designed for high-frequency applications and selected to match the requirements of the crystal or
resonator. CL1 and CL2, are usually the same size. The crystal manufacturer typically specifies a load
capacitance which is the series combination of CL1 and CL2. PCB and MCU pin capacitance must be
included when sizing CL1 and CL2 (10pF can be used as a rough estimate of the combined pin and board
capacitance).
Figure 77. Typical application with a crystal or ceramic resonator
WHEN RESONATOR WITH
INTEGRATED CAPACITORS
f
OSC
POWER DOWN
LOGIC
C
L1
OSC1
LINEAR
AMPLIFIER
FEEDBACK
LOOP
i
V
Ref
/2
2
DD
RESONATOR
OSC2
R
F
C
L2
ST72XXX
204/227
ST72325xxx-Auto
Electrical characteristics
Table 117. Resonator characteristics
Supplier
fOSC (MHz)
Typical ceramic resonators(1)
2
4
CSTCC2M00G56Z-R0
CSTCR4M00G53Z-R0
CSTCE8M00G52Z-R0
CSTCE16M0V51Z-R0
Murata
8
16
1. Resonator characteristics given by the ceramic resonator manufacturer. For more information on these
resonators, please consult www.murata.com.
19.5.4
RC oscillators
Table 118. RC oscillator characteristics
Symbol
Parameter
Conditions
Min
Typ
Max Unit
Internal RC oscillator frequency
(see Figure 78)
fOSC(RCINT)
TA = 25°C, VDD = 5V
2
3.5 5.6
MHz
Figure 78. Typical f
versus T
A
OSC(RCINT)
4
3.8
3.6
3.4
3.2
Vdd = 5V
Vdd = 5.5V
3
-45
0
25
70
130
TA(°C)
Note:
To reduce disturbance to the RC oscillator, it is recommended to place decoupling
capacitors between V and V as shown in Figure 98.
DD
SS
19.5.5
Clock security system (CSS)
Table 119. CSS characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fSFOSC Safe oscillator frequency(1)
1. Data based on characterization results
3
MHz
205/227
Electrical characteristics
ST72325xxx-Auto
19.5.6
PLL characteristics
Table 120. PLL characteristics
Symbol
Parameter
Conditions
Min Typ Max Unit
fOSC
PLL input frequency range
Instantaneous PLL jitter(1)
2
4
2
MHz
%
∆ fCPU CPU
/f
fOSC = 4 MHz
0.7
1. Data characterized but not tested
The user must take the PLL jitter into account in the application (for example, in serial
communication or sampling of high frequency signals). The PLL jitter is a periodic effect,
which is integrated over several CPU cycles. Therefore, the longer the period of the
application signal, the less it is impacted by the PLL jitter.
Figure 79 shows the PLL jitter integrated on application signals in the range 125 kHz to
4 MHz. At frequencies of less than 125 kHz, the jitter is negligible.
(1)
Figure 79. Integrated PLL jitter versus signal frequency
+/-Jitter (%)
1.2
Max
Typ
1
0.8
0.6
0.4
0.2
0
4 MHz 2 MHz 1 MHz 500 kHz 250 kHz 125 kHz
Application Frequency
1. Measurement conditions: fCPU = 8 MHz
19.6
Memory characteristics
19.6.1
RAM and hardware registers
Table 121. RAM supply voltage
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VRM
Data retention mode(1)
Halt mode (or RESET)
1.6
V
1. Minimum VDD supply voltage without losing data stored in RAM (in Halt mode or under RESET) or in
hardware registers (only in Halt mode). Not tested in production.
206/227
ST72325xxx-Auto
Electrical characteristics
19.6.2
Flash memory
Table 122. Dual voltage HDFlash memory
Symbol
Parameter
Conditions
Read mode
Min(1) Typ Max(1) Unit
0
1
8
8
fCPU
VPP
Operating frequency
MHz
V
Write / Erase mode
4.5V < VDD < 5.5V
Run mode (fCPU = 4 MHz)
Write / Erase
Programming voltage(2)
11.4
12.6
3
mA
IDD
Supply current(3)
VPP current(3)
0
1
Power down mode / HALT
Read (VPP = 12V)
Write / Erase
10
200
30
µA
IPP
mA
µs
Internal VPP stabilization
time
tVPP
10
25
tRET
NRW
Data retention
TA = 55°C
TA = 85°C
20
years
Write erase cycles
100
cycles
TPROG Programming or erasing
TERASE temperature range
-40
85
°C
1. Data based on characterization results, not tested in production
2. VPP must be applied only during the programming or erasing operation and not permanently for reliability
reasons.
3. Data based on simulation results, not tested in production
Warning: Do not connect 12V to V before V is powered on, as this
PP
DD
may damage the device.
207/227
Electrical characteristics
ST72325xxx-Auto
19.7
EMC (electromagnetic compatibility) characteristics
Susceptibility tests are performed on a sample basis during product characterization.
19.7.1
Functional EMS (electromagnetic susceptibility)
Based on a simple running application on the product (toggling two LEDs through I/O ports),
the product is stressed by two electromagnetic events until a failure occurs (indicated by the
LEDs).
●
ESD: Electrostatic discharge (positive and negative) is applied on all pins of the device
until a functional disturbance occurs. This test conforms with the IEC 1000-4-2
standard.
●
FTB: A burst of fast transient voltage (positive and negative) is applied to V and V
DD
SS
through a 100pF capacitor until a functional disturbance occurs. This test conforms with
the IEC 1000-4-4 standard.
A device reset allows normal operations to be resumed. The test results given in Table 123
below are based on the EMS levels and classes defined in application note AN1709.
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
●
●
●
Corrupted program counter
Unexpected reset
Critical Data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the RESET pin or the oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
208/227
ST72325xxx-Auto
Electrical characteristics
Conditions Level/Class
.
Table 123. EMS test results
Symbol
Parameter
Voltage limits to be applied on any I/O pin to
induce a functional disturbance
VDD = 5V, TA = +25°C, fOSC = 8 MHz,
conforms to IEC 1000-4-2
VFESD
3B
3B
Fast transient voltage burst limits to be applied LQFP44:
VFFTB through 100pF on VDD and VDD pins to induce a
functional disturbance
VDD = 5V, TA = +25°C, fOSC = 8 MHz,
conforms to IEC 1000-4-4
19.7.2
EMI (electromagnetic interference)
Based on a simple application running on the product (toggling two LEDs through the I/O
ports), the product is monitored in terms of emission. This emission test is in line with the
norm SAE J 1752/3 which specifies the board and the loading of each pin.
Table 124. EMI emissions
(1)
Conditions
Max vs [fOSC/fCPU
]
Monitored
frequency band
Symbol Parameter
Unit
VDD = 5V, TA = +25°C,
conforming to SAE J 1752/3
8/4 MHz 16/8 MHz
0.1 MHz to 30 MHz
30 MHz to 130 MHz
130 MHz to 1 GHz
SAE EMI Level
15
20
7
20
27
12
3
48/60 Kbyte Flash devices in
LQFP44 and LQFP64 packages
and
dBµV
SEMI
Peak level
Peak level
32 Kbyte Flash devices in
LQFP64 package
2.5
13
20
16
3
-
dBµV
-
0.1 MHz to 30 MHz
30 MHz to 130 MHz
130 MHz to 1 GHz
SAE EMI Level
14
25
21
3.5
16/32 Kbyte Flash devices in
LQFP32 and LQFP44 packages
SEMI
1. Data based on characterization results, not tested in production.
19.7.3
Absolute maximum ratings (electrical sensitivity)
Based on three different tests (ESD, LU and DLU) using specific measurement methods, the
product is stressed in order to determine its performance in terms of electrical sensitivity.
For more details, refer to the application note AN1181.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts*(n+1) supply pin). Two models
can be simulated: Human Body Model and Machine Model. This test conforms to the
JESD22-A114A/A115A standard.
209/227
Electrical characteristics
ST72325xxx-Auto
Max. value(1) Unit
Table 125. ESD absolute maximum ratings
Symbol
Ratings
Conditions
Electrostatic discharge voltage
(Human Body Model)
VESD(HBM)
2000
TA = +25°C
V
Electrostatic discharge voltage
(Machine Model)
VESD(MM)
200
1. Data based on characterization results, not tested in production.
Static and dynamic latch-up
●
LU: Three complementary static tests are required on 10 parts to assess the latch-up
performance. A supply overvoltage (applied to each power supply pin) and a current
injection (applied to each input, output and configurable I/O pin) are performed on each
sample. This test conforms to the EIA/JESD 78 IC latch-up standard. For more details,
refer to the application note AN1181.
●
DLU: Electrostatic discharges (one positive then one negative test) are applied to each
pin of three samples when the micro is running to assess the latch-up performance in
dynamic mode. Power supplies are set to the typical values, the oscillator is connected
as near as possible to the pins of the micro and the component is put in reset mode.
This test conforms to the IEC1000-4-2 and SAEJ1752/3 standards. For more details,
refer to the application note AN1181.
Table 126. Electrical sensitivities
Symbol
Parameter
Conditions
Class(1)
TA = +25°C
TA = +85°C
TA = +125°C
A
A
A
LU
Static latch-up class
DLU
Dynamic latch-up class VDD = 5.5V, fOSC = 4 MHz, TA = +25°C
A
1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the
JEDEC specifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B
Class strictly covers all the JEDEC criteria (international standard).
210/227
ST72325xxx-Auto
Electrical characteristics
19.8
I/O port pin characteristics
19.8.1
General characteristics
Subject to general operating conditions for V
f
, and T unless otherwise specified.
DD, OSC A
Table 127. I/O port pin general characteristics
Symbol
Parameter
Input low level voltage(1)
Conditions
Min
Typ
Max
Unit
VIL
VIH
0.3xVDD
Input high level voltage(1)
CMOS ports
0.7xVDD
V
Vhys
Schmitt trigger voltage hysteresis(2)
Injected current on PB0 pin
Injected current on an I/O pin
0.7
0
+4
4
(3)
IINJ(PIN)
VDD = 5V
mA
µA
Total injected current (sum of all I/O and
control pins)
(3)
ΣIINJ(PIN)
25
1
Ilkg
IS
Input leakage current
VSS < VIN < VDD
Static current consumption
Weak pull-up equivalent resistor(6)
I/O pin capacitance
Floating input mode(4)(5)
400
120
5
RPU
VIN = VSS VDD = 5V
50
250
kΩ
CIO
pF
tf(IO)out
tr(IO)out
tw(IT)in
Output high to low level fall time(1)
Output low to high level rise time(1)
External interrupt pulse time(7)
25
CL = 50pF
Between 10% and 90%
ns
25
1
tCPU
1. Data based on characterization results, not tested in production.
2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
3. When the current limitation is not possible, the VIN maximum must be respected, otherwise refer to IINJ(PIN) specification. A
positive injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS. Refer to Section 19.2.2:
Current characteristics for more details.
4. Static peak current value taken at a fixed VIN value, based on design simulation and technology characteristics, not tested
in production. This value depends on VDD and temperature values.
5. The Schmitt trigger that is connected to every I/O port is disabled for analog inputs only when ADON bit is ON and the
particular ADC channel is selected (with port configured in input floating mode). When the ADON bit is OFF, static current
consumption may result. This can be avoided by keeping the input voltage of this pin close to VDD or VSS
.
6. The RPU pull-up equivalent resistor is based on a resistive transistor (corresponding IPU current characteristics described in
Figure 81).
7. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external
interrupt source.
211/227
Electrical characteristics
ST72325xxx-Auto
Figure 80. Unused I/O pins configured as
input
Figure 81. Typical I vs V with V = V
PU DD IN SS
90
80
70
60
50
40
30
20
10
0
V
Ta=140°C
DD
ST7XXX
Ta=95°C
Ta=25°C
Ta=-45°C
10kΩ
UNUSED I/O PORT
UNUSED I/O PORT
10kΩ
ST7XXX
Note: I/O can be left unconnected if it is configured as output
(0 or 1) by the software. This has the advantage of
greater EMC robustness and lower cost.
2
2.5
3
3.5
4
4.5
5
5.5
6
Vdd(V)
19.8.2
Output driving current
Subject to general operating conditions for V , f
, and T unless otherwise specified.
A
DD CPU
Table 128. Output driving current
Symbol
Parameter
Conditions
IO = +5mA
Min
Max
1.2
Unit
Output low level voltage for a standard I/O pin
when 8 pins are sunk at same time
(see Figure 82)
I
IIO = +2mA
0.5
(1)
IIO = +20mA,
VOL
Output low level voltage for a high sink I/O pin
when 4 pins are sunk at same time
(see Figure 83 and Figure 85)
TA < 85°C
TA > 85°C
1.3
1.5
VDD = 5V
V
IIO = +8mA
IIO = -5mA,
0.6
Output high level voltage for an I/O pin
when 4 pins are sourced at same time
(see Figure 84 and Figure 87)
TA < 85°C
TA > 85°C
V
DD - 1.4
(2)
VOH
VDD - 1.6
I
IO = -2mA
VDD - 0.7
1. The IIO current sunk must always respect the absolute maximum rating specified in Section 19.2.2 and the sum of IIO (I/O
ports and control pins) must not exceed IVSS
.
2. The IIO current sourced must always respect the absolute maximum rating specified in Section 19.2.2 and the sum of IIO
(I/O ports and control pins) must not exceed IVDD. True open-drain I/O pins do not have VOH
.
212/227
ST72325xxx-Auto
Electrical characteristics
Figure 82. Typical V at V = 5V (standard) Figure 83. Typical V at V = 5V (high-sink)
OL
DD
OL
DD
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1.4
1.2
1
0.8
0.6
0.4
0.2
0
Ta= 140°C
Ta= 95°C
Ta= 25°C
Ta=-45°C
Ta=140°C "
Ta=95°C
Ta=25°C
Ta=-45°C
0
0.01
0.02
0.03
0
0.005
0.01
0.015
Iio(A)
Iio(A)
Figure 84. Typical V at V = 5V
OH
DD
5.5
5
4.5
4
3.5
3
Vdd=5V 140°C min
Vdd=5v 95°C min
Vdd=5v 25°C min
Vdd=5v -45°C min
2.5
2
-0.01 -0.008 -0.006 -0.004 -0.002
Iio (A )
0
213/227
Electrical characteristics
Figure 85. Typical V versus V (standard)
ST72325xxx-Auto
OL
DD
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.45
0.4
Ta= -45°C
Ta= 25°C
Ta=-45°C
Ta=25°C
Ta=95°C
Ta=140°C
Ta= 95°C
0.35
0.3
Ta= 140°C
0.25
0.2
0.15
0.1
0.05
0
2
2.5
3
3.5
4
4.5
5
5.5
6
2
2.5
3
3.5
4
4.5
5
5.5
6
Vdd(V)
Vdd(V)
Figure 86. Typical V versus V (high-sink)
OL
DD
1.6
0.6
Ta= 140°C
Ta=95°C
Ta=25°C
Ta=-45°C
1.4
1.2
1
0.5
0.4
0.3
0.2
0.8
0.6
0.4
0.2
0
Ta= 140°C
Ta=95°C
Ta=25°C
Ta=-45°C
0.1
0
2
2.5
3
3.5
4
4.5
5
5.5
6
2
2.5
3
3.5
4
4.5
5
5.5
6
V dd(V )
Vdd(V )
Figure 87. Typical V -V versus V
DD OH
DD
5.5
6
Ta=-45°C
Ta=25°C
Ta=95°C
Ta=140°C
5
5
4
3
2
1
0
4.5
4
3.5
Ta=-45°C
Ta=25°C
Ta=95°C
Ta=140°C
3
2.5
2
2
2.5
3
3.5
4
4.5
5
5.5
6
2
2.5
3
3.5
4
4.5
5
5.5
6
Vdd(V)
Vdd(V)
214/227
ST72325xxx-Auto
Electrical characteristics
19.9
Control pin characteristics
19.9.1
Asynchronous RESET pin
Subject to general operating conditions for V , f
, and T unless otherwise specified.
A
DD CPU
Table 129. Asynchronous RESET pin characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIL
Input low level voltage(1)
Input high level voltage(1)
0.3xVDD
VIH
0.7xVDD
V
Schmitt trigger voltage
hysteresis(2)
Vhys
2.5
VOL
IIO
Output low level voltage(3)
Input current on RESET pin
Weak pull-up equivalent resistor
VDD = 5V, IIO = +2mA
0.2
2
0.5
mA
RON
20
0
30
120
42(4)
42(4)
kΩ
Stretch applied on external pulse
Internal reset sources
tw(RSTL)out Generated reset pulse duration
20
2.5
30
µs
ns
th(RSTL)in External reset pulse hold time(5)
tg(RSTL)in Filtered glitch duration(6)
200
1. Data based on characterization results, not tested in production.
2. Hysteresis voltage between Schmitt trigger switching levels.
3. The IIO current sunk must always respect the absolute maximum rating specified in Section 19.2.2 and the sum of IIO (I/O
ports and control pins) must not exceed IVSS
.
4. Data guaranteed by design, not tested in production.
5. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on the
RESET pin with a duration below th(RSTL)in can be ignored.
6. The reset network (the resistor and two capacitors) protects the device against parasitic resets, especially in noisy
environments.
215/227
Electrical characteristics
ST72325xxx-Auto
Figure 88. RESET pin protection when LVD is enabled
V
ST72XXX
DD
Optional
(note 3)
Required
R
ON
Filter
INTERNAL
RESET
EXTERNAL
RESET
0.01µF
1MΩ
WATCHDOG
LVD RESET
PULSE
GENERATOR
Note:
1
- The reset network protects the device against parasitic resets.
- The output of the external reset circuit must have an open-drain output to drive the ST7
reset pad. Otherwise the device can be damaged when the ST7 generates an internal reset
(LVD or watchdog).
- Whether the reset source is internal or external, the user must ensure that the level on the
RESET pin can go below the V maximum level specified in Section 19.9.1 on page 215.
IL
Otherwise the reset will not be taken into account internally.
- Because the reset circuit is designed to allow the internal RESET to be output in the
RESET pin, the user must ensure that the current sunk on the RESET pin is less than the
absolute maximum value specified for I
in Section 19.2.2 on page 196.
INJ(RESET)
2
3
When the LVD is enabled, it is recommended not to connect a pull-up resistor or capacitor. A
10nF pull-down capacitor is required to filter noise on the reset line.
In case a capacitive power supply is used, it is recommended to connect a 1MΩ pull-down
resistor to the RESET pin to discharge any residual voltage induced by the capacitive effect
of the power supply (this will add 5µA to the power consumption of the MCU).
4
Tips when using the LVD:
A. Check that all recommendations related to reset circuit have been applied (see notes
above).
B. Check that the power supply is properly decoupled (100nF + 10µF close to the MCU).
Refer to AN1709 and AN2017. If this cannot be done, it is recommended to put a 100nF +
1MΩ pull-down on the RESET pin.
C. The capacitors connected on the RESET pin and also the power supply are key to avoid
any start-up marginality. In most cases, steps A and B above are sufficient for a robust
solution. Otherwise, replace 10nF pull-down on the RESET pin with a 5µF to 20µF
capacitor.
216/227
ST72325xxx-Auto
Electrical characteristics
Figure 89. RESET pin protection when LVD is disabled
VDD
ST72XXX
RON
INTERNAL
RESET
USER
EXTERNAL
RESET
Filter
CIRCUIT
0.01µF
PULSE
GENERATOR
WATCHDOG
Required
Note:
- The reset network protects the device against parasitic resets.
- The output of the external reset circuit must have an open-drain output to drive the ST7
reset pad. Otherwise the device can be damaged when the ST7 generates an internal reset
(LVD or watchdog).
- Whether the reset source is internal or external, the user must ensure that the level on the
RESET pin can go below the V maximum level specified in Section 19.9.1 on page 215.
IL
Otherwise the reset will not be taken into account internally.
- Because the reset circuit is designed to allow the internal RESET to be output in the
RESET pin, the user must ensure that the current sunk on the RESET pin is less than the
absolute maximum value specified for I
in Section 19.2.2 on page 196.
INJ(RESET)
19.9.2
ICCSEL/V pin
PP
Subject to general operating conditions for V , f
, and T unless otherwise specified.
DD CPU
A
Table 130. ICCSEL/V pin characteristics
PP
Symbol
Parameter
Conditions
Min
Max(1)
Unit
Ilkg
Input leakage current
VIN = VSS
1
µA
1. Data based on design simulation and/or technology characteristics, not tested in production
(1)
Figure 90. Two typical applications with ICCSEL/V pin
PP
ICCSEL/V
V
PP
PP
PROGRAMMING
TOOL
10kΩ
ST72XXX
ST72XXX
1. When ICC mode is not required by the application, the ICCSEL/VPP pin must be tied to VSS
.
217/227
Electrical characteristics
ST72325xxx-Auto
19.10
Timer peripheral characteristics
Subject to general operating conditions for V , f
, and T unless otherwise specified.
A
DD OSC
Refer to Section 19.8: I/O port pin characteristics for more details on the input/output
alternate function characteristics (such as output compare, input capture, external clock, or
PWM output).
Table 131. 8-bit PWM-ART auto-reload timer characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
1
tCPU
ns
tres(PWM) PWM resolution time
fCPU = 8 MHz
125
fEXT
ART external clock frequency
PWM repetition rate
0
fCPU/2 MHz
fPWM
ResPWM PWM resolution
VOS PWM/DAC output step voltage
8
bit
VDD = 5V,
Resolution = 8 bits
20
mV
Table 132. 16-bit timer characteristics
Symbol Parameter
Conditions
Min
Typ
Max
Unit
tw(ICAP)in Input capture pulse time
tres(PWM) PWM resolution time
1
2
tCPU
tCPU
ns
fCPU = 8 MHz
250
fEXT
Timer external clock frequency
PWM repetition rate
0
fCPU/4 MHz
16 bit
fPWM
ResPWM PWM resolution
218/227
ST72325xxx-Auto
Electrical characteristics
19.11
Communication interface characteristics
19.11.1 SPI (serial peripheral interface)
Subject to general operating conditions for V , f
, and T unless otherwise specified.
A
DD CPU
Refer to Section 19.8: I/O port pin characteristics for more details on the input/output
alternate function characteristics (SS, SCK, MOSI, MISO).
Table 133. SPI characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
Master, fCPU = 8 MHz
Slave, fCPU = 8 MHz
fCPU/128 = 0.0625
0
fCPU/4 = 2
fCPU/2 = 4
fSCK
1/tc(SCK)
SPI clock frequency
MHz
tr(SCK)
tf(SCK)
SPI clock rise and fall time
see I/O port pin description
tCPU + 50
tsu(SS)
SS setup time(2)
SS hold time
Slave
Slave
(1)
(1)
th(SS)
120
(1)
tw(SCKH)
tw(SCKL)
Master
Slave
100
90
SCK high and low time
Data input setup time
Data input hold time
(1)
(1)
tsu(MI)
tsu(SI)
Master
Slave
100
100
(1)
ns
(1)
th(MI)
th(SI)
Master
Slave
100
100
(1)
(1)
ta(SO)
Data output access time
Data output disable time
Data output valid time
Data output hold time
Data output valid time
Data output hold time
Slave
Slave
0
120
240
120
(1)
tdis(SO)
(1)
tv(SO)
th(SO)
tv(MO)
th(MO)
Slave (after enable edge)
Master (after enable edge)
(1)
0
0
(1)
(1)
120
tCPU
1. Data based on design simulation and/or characterization results, not tested in production.
2. Depends on fCPU. For example, if fCPU = 8 MHz, then tCPU = 1 / fCPU = 125 ns and tsu(SS) = 175 ns.
219/227
Electrical characteristics
ST72325xxx-Auto
(1)
Figure 91. SPI slave timing diagram with CPHA = 0
SS INPUT
tsu(SS)
tc(SCK)
th(SS)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
tw(SCKH)
tw(SCKL)
ta(SO)
tv(SO)
th(SO)
tdis(SO)
tr(SCK)
tf(SCK)
See
note 2
MISO OUTPUT
See note 2
MSB OUT
BIT6 OUT
LSB OUT
tsu(SI)
th(SI)
LSB IN
MSB IN
BIT1 IN
MOSI INPUT
1. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD
.
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has its
alternate function capability released. In this case, the pin status depends on the I/O port configuration.
(1)
Figure 92. SPI slave timing diagram with CPHA = 1
SS INPUT
tsu(SS)
tc(SCK)
th(SS)
CPHA=1
CPOL=0
CPHA=1
CPOL=1
tw(SCKH)
tw(SCKL)
ta(SO)
tdis(SO)
tv(SO)
th(SO)
tr(SCK)
tf(SCK)
See
note 2
See
note 2
MISO OUTPUT
MSB OUT
BIT6 OUT
HZ
LSB OUT
tsu(SI)
th(SI)
LSB IN
MSB IN
BIT1 IN
MOSI INPUT
1. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD
.
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has its
alternate function capability released. In this case, the pin status depends of the I/O port configuration.
220/227
ST72325xxx-Auto
Electrical characteristics
(1)
Figure 93. SPI master timing diagram
SS INPUT
tc(SCK)
CPHA = 0
CPOL = 0
CPHA = 0
CPOL = 1
CPHA = 1
CPOL = 0
CPHA = 1
CPOL = 1
tw(SCKH)
tw(SCKL)
tr(SCK)
tf(SCK)
th(MI)
tsu(MI)
MISO INPUT
MSB IN
BIT6 IN
LSB IN
tv(MO)
th(MO)
MSB OUT
LSB OUT
See note 2
BIT6 OUT
See note 2
MOSI OUTPUT
1. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD
.
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has its
alternate function capability released. In this case, the pin status depends of the I/O port configuration.
221/227
Electrical characteristics
2
ST72325xxx-Auto
I C - inter IC control interface
19.11.2
Subject to general operating conditions for V
,
, and T unless otherwise specified.
f
DD
A
CPU
Refer to Section 19.8: I/O port pin characteristics for more details on the input/output
alternate function characteristics (SDAI and SCLI). The ST7 I2C interface meets the
requirements of the standard I2C communication protocol described in the following table.
Table 134. I2C control interface characteristics
Standard mode I2C
Fast mode I2C(1)
Symbol
Parameter
Unit
Min(2)
Max(2)
Min(2)
Max(2)
tw(SCLL)
SCL clock low time
4.7
4.0
1.3
0.6
µs
tw(SCLH) SCL clock high time
tsu(SDA)
th(SDA)
tr(SDA)
SDA setup time
250
0(3)
100
0(4)
SDA data hold time
900(3)
300
ns
SDA and SCL rise time
SDA and SCL fall time
1000
300
tr(SCL)
20+0.1Cb
tf(SDA)
tf(SCL)
th(STA)
tsu(STA)
tsu(STO)
START condition hold time
4.0
4.7
4.0
4.7
Repeated START condition setup time
STOP condition setup time
0.6
1.3
µs
tw(STO:STA) STOP to START condition time (bus free)
Cb Capacitive load for each bus line
400
400
pF
1. At 4 MHz fCPU, maximum I2C speed (400 kHz) is not achievable. In this case, maximum I2C speed will be approximately
260 kHz.
Data based on standard I2C protocol requirement, not tested in production.
2.
The maximum hold time of the START condition has only to be met if the interface does not stretch the low period of SCL
signal.
3.
4.
The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region
of the falling edge of SCL.
222/227
ST72325xxx-Auto
Electrical characteristics
2
(1)
Typical application with I C BUS and timing diagram
Figure 94.
I2C BUS
SDA
VDD
VDD
4.7kΩ
4.7kΩ
100Ω
100Ω
SDAI
SCLI
ST72XXX
REPEATED START
START
tsu(STA)
tw(STO:STA)
START
tf(SDA)
tr(SDA)
STOP
tsu(SDA)
th(SDA)
SCK
th(STA) tw(SCKH) tw(SCKL)
tr(SCK)
tf(SCK)
tsu(STO)
Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD
.
1.
The following table provides the values to be written in the I2CCCR register to obtain the
2
required I C SCL line frequency.
Table 135. SCL frequency table
I2CCCR value
f
CPU = 4 MHz
fCPU = 8 MHz
fSCL
(kHz)
VDD = 4.1V
VDD = 5V
VDD = 4.1V
VDD = 5V
RP = 3.3kΩ RP = 4.7kΩ RP = 3.3kΩ RP = 4.7kΩ RP = 3.3kΩ RP = 4.7kΩ RP = 3.3kΩ RP = 4.7kΩ
400
300
200
100
50
Not achievable
83h
85h
Not achievable
83h
10h
24h
5Fh
8Ah
24h
89h
23h
8Ah
24h
23h
4Ch
FFh
20
Legend:
R
= External pull-up resistance
P
2
f
= I C speed
SCL
Note:
- For speeds around 200 kHz, the achieved speed can have a 5% tolerance.
- For other speed ranges, the achieved speed can have a 2% tolerance.
The above variations depend on the accuracy of the external components used.
223/227
Electrical characteristics
ST72325xxx-Auto
19.12
10-bit ADC characteristics
Subject to general operating conditions for V , f
, and T unless otherwise specified.
A
DD CPU
Table 136. 10-bit ADC characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fADC
ADC clock frequency
0.4
3.8
2
VDD
VAREF
250
1
MHz
VAREF Analog reference voltage
0.7*VDD < VAREF < VDD
V
VAIN
Conversion voltage range(1)
VSSA
-40°C < TA < 85°C range
Other TA ranges
nA
µA
kΩ
pF
Input leakage current for analog
input(2)
Ilkg
RAIN External input impedance
See
Figure 95
and
CAIN External capacitor on analog input
Variation frequency of analog input
signal
Figure 96
fAIN
Hz
pF
CADC Internal sample and hold capacitor
Conversion time (Sample + Hold)
12
tADC
fCPU = 8 MHz, speed = 0,
fADC = 2 MHz
7.5
µs
No. of sample capacitor loading
cycles
4
tADC
1/fADC
No. of hold conversion cycles
11
1. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10kΩ). Data
based on characterization results, not tested in production.
2. Injecting negative current on adjacent pins may result in increased leakage currents. Software filtering of the converted
analog value is recommended.
224/227
ST72325xxx-Auto
Electrical characteristics
Figure 95. R
C
maximum versus f
= 0pF
with
Figure 96. Recommended C
and R
AIN AIN
AIN
AIN
ADC
(1)
(1)
values
45
40
35
30
25
20
15
10
5
1000
100
10
Cain 10 nF
Cain 22 nF
Cain 47 nF
2 MHz
1 MHz
1
0
0.1
0
10
30
70
0.01
0.1
1
10
CPARASITIC (pF)
fAIN(KHz)
1.
C
PARASITIC represents the capacitance of the PCB
1. This graph shows that, depending on the input signal
variation (fAIN), CAIN can be increased for stabilization
time and decreased to allow the use of a larger serial
(dependent on soldering and PCB layout quality) plus
the pad capacitance (3pF). A high CPARASITIC value will
downgrade conversion accuracy. To remedy this, fADC
should be reduced.
resistor (RAIN)
.
Figure 97. Typical A/D converter application
V
DD
ST72XXX
V
T
0.6V
R
2kΩ(max)
AIN
AINx
10-bit A/D
conversion
V
AIN
C
V
T
0.6V
AIN
I
C
ADC
12pF
lkg
19.12.1 Analog power supply and reference pins
Depending on the MCU pin count, the package may feature separate V
and V
SSA
AREF
analog power supply pins. These pins supply power to the A/D converter cell and function
as the high and low reference voltages for the conversion.
Separation of the digital and analog power pins allow board designers to improve A/D
performance. Conversion accuracy can be impacted by voltage drops and noise in the event
of heavily loaded or badly decoupled power supply lines (see Section 19.12.2: General PCB
design guidelines).
225/227
Electrical characteristics
ST72325xxx-Auto
19.12.2 General PCB design guidelines
To obtain best results, some general design and layout rules should be followed when
designing the application PCB to shield the noise-sensitive, analog physical interface from
noise-generating CMOS logic signals.
●
Use separate digital and analog planes. The analog ground plane should be connected
to the digital ground plane via a single point on the PCB.
●
Filter power to the analog power planes. It is recommended to connect capacitors, with
good high frequency characteristics, between the power and ground lines, placing
0.1µF and optionally, if needed 10pF capacitors as close as possible to the ST7 power
supply pins and a 1 to 10µF capacitor close to the power source (see Figure 98).
●
●
The analog and digital power supplies should be connected in a star network. Do not
use a resistor, as V
is used as a reference voltage by the A/D converter and any
AREF
resistance would cause a voltage drop and a loss of accuracy.
Properly place components and route the signal traces on the PCB to shield the analog
inputs. Analog signals paths should run over the analog ground plane and be as short
as possible. Isolate analog signals from digital signals that may switch while the analog
inputs are being sampled by the A/D converter. Do not toggle digital outputs on the
same I/O port as the A/D input being converted.
Figure 98. Power supply filtering
ST72XXX
1 to 10µF
ST7
0.1µF
V
V
SS
DD
DIGITAL NOISE
FILTERING
+
V
DD
POWER
SUPPLY
SOURCE
0.1µF
V
V
AREF
SSA
EXTERNAL
NOISE
FILTERING
226/227
ST72325xxx-Auto
Electrical characteristics
19.12.3 ADC accuracy
Table 137. ADC accuracy
Max(2)
Symbol
Parameter(1)
Conditions
Typ
Unit
48/60 Kbyte 16/32 Kbyte
Flash
Flash
|ET|
|EO|
|EG|
|ED|
|EL|
Total unadjusted error
Offset error
3
2
4
3
3
6
5
VDD = 5V(1)
CPU in run mode @ fADC 2 MHz
Gain error
0.5
4.5
2
LSB
Differential linearity error
Integral linearity error
1
2
3
1. ADC Accuracy versus Negative Injection Current: Injecting negative current may reduce the accuracy of the conversion
being performed on another analog input. Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN)
in Section 19.8 does not affect the ADC accuracy.
2. Data based on characterization results, monitored in production to guarantee 99.73% within max value from -40°C to
125°C ( 3σ distribution limits).
Figure 99. ADC error classification
Digital Result ADCDR
Legend:
E
G
1023
1022
1021
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line
V
– V
AREF
SSA
1LSB
= --------------------------------------------
IDEAL
1024
E
= Total Unadjusted Error: maximum deviation
T
between the actual and the ideal transfer curves.
(2)
E
= Offset Error: deviation between the first
O
E
T
actual transition and the first ideal one.
(3)
7
6
5
4
3
2
1
E
= Gain Error: deviation between the last ideal
(1)
G
transition and the last actual one.
E
= Differential Linearity Error: maximum
D
E
O
E
L
deviation between actual steps and the ideal
one.
E
= Integral Linearity Error: maximum deviation
L
E
D
between any actual transition and the end point
correlation line.
1 LSB
IDEAL
V
(LSB
)
IDEAL
in
0
1
2
3
4
5
6
7
1021 1022 1023 1024
V
V
AREF
SSA
227/227
Package characteristics
ST72325xxx-Auto
20
Package characteristics
20.1
Package mechanical data
Figure 100. 64-pin (14x14) low profile quad flat package outline
A
D
A2
D1
A1
b
e
E1 E
L
L1
c
h
Table 138. 64-pin (14x14) low profile quad flat package mechanical data
mm
Typ
inches(1)
Dimension
Min
Max
Min
Typ
Max
A
A1
A2
b
1.60
0.15
1.45
0.45
0.20
0.063
0.006
0.057
0.018
0.008
0.05
1.35
0.30
0.09
0.002
0.053
0.012
0.004
1.40
0.37
0.055
0.015
c
D
16.00
14.00
16.00
14.00
0.80
0.630
0.551
0.630
0.551
0.031
3.5°
D1
E
E1
e
θ
0°
3.5°
7°
0°
7°
L
0.45
0.60
0.75
0.018
0.024
0.039
0.030
L1
1.00
1. Values in inches are converted from mm and rounded to 3 decimal digits.
228/250
ST72325xxx-Auto
Package characteristics
Figure 101. 64-pin (10x10) low profile quad flat package outline
D
A
D1
A2
A1
b
e
E1
E
c
L1
h
L
Table 139. 64-pin (10x10) low profile quad flat package mechanical data
mm
Typ
inches(1)
Dimension
Min
Max
Min
Typ
Max
A
A1
A2
b
1.60
0.15
1.45
0.27
0.20
0.063
0.006
0.057
0.011
0.008
0.05
1.35
0.17
0.09
0.002
0.053
0.007
0.004
1.40
0.22
0.055
0.009
c
D
12.00
10.00
12.00
10.00
0.50
0.472
0.394
0.472
0.394
0.020
3.5°
D1
E
E1
e
θ
0°
3.5°
7°
0°
7°
L
0.45
0.60
0.75
0.018
0.024
0.039
0.030
L1
1.00
1. Values in inches are converted from mm and rounded to 3 decimal digits.
229/250
Package characteristics
Figure 102. 44-pin (10x10) low profile quad flat package outline
ST72325xxx-Auto
A
D
D1
A2
A1
b
e
E1
E
c
L1
L
h
Table 140. 44-pin (10x10) low profile quad flat package mechanical data
mm
Typ
inches(1)
Dimension
Min
Max
Min
Typ
Max
A
A1
A2
b
1.60
0.15
1.45
0.45
0.20
0.063
0.006
0.057
0.018
0.008
0.05
1.35
0.30
0.09
0.002
0.053
0.012
0.004
1.40
0.37
0.055
0.015
0.000
0.472
0.394
0.472
0.394
0.031
3.5°
C
D
12.00
10.00
12.00
10.00
0.80
D1
E
E1
e
θ
0°
3.5°
7°
0°
7°
L
0.45
0.60
0.75
0.018
0.024
0.039
0.030
L1
1.00
1. Values in inches are converted from mm and rounded to 3 decimal digits.
230/250
ST72325xxx-Auto
Figure 103. 32-pin low profile quad flat package outline
Package characteristics
D
A
D1
A2
A1
e
b
E
E1
c
L1
L
h
Table 141. 32-pin low profile quad flat package mechanical data
mm
Typ
inches(1)
Dim.
Min
Max
1.60
0.15
1.45
0.45
0.20
Min
Typ
Max
A
A1
A2
b
0.063
0.006
0.057
0.018
0.008
0.05
1.35
0.30
0.09
0.002
0.053
0.012
0.004
1.40
0.37
0.055
0.015
C
D
9.00
7.00
9.00
7.00
0.80
3.5°
0.60
1.00
0.354
0.276
0.354
0.276
0.031
3.5°
D1
E
E1
e
θ
0°
7°
0°
7°
L
0.45
0.75
0.018
0.024
0.039
0.030
L1
1. Values in inches are converted from mm and rounded to 3 decimal digits.
231/250
Package characteristics
ST72325xxx-Auto
20.2
Thermal characteristics
Table 142. Thermal characteristics
Symbol
Ratings
Value
Unit
Package thermal resistance (junction to ambient)
LQFP64 14x14
LQFP64 10x10
LQFP44 10x10
LQFP32 7x7
47
50
52
70
RthJA
°C/W
PD
Power dissipation(1)
500
150
mW
°C
TJmax
Maximum junction temperature(2)
1. The maximum power dissipation is obtained from the formula PD = (TJ -TA) / RthJA. The power dissipation
of an application can be defined by the user with the formula: PD = PINT + PPORT where PINT is the chip
internal power (IDD x VDD) and PPORT is the port power dissipation depending on the ports used in the
application.
2. The maximum chip-junction temperature is based on technology characteristics.
20.3
Soldering information
In accordance with the RoHS European directive, all STMicroelectronics packages have
®
been converted to lead-free technology, named ECOPACK .
®
●
ECOPACK packages are qualified according to the JEDEC STD-020B compliant
soldering profile.
®
●
Detailed information on the STMicroelectronics ECOPACK transition program is
available on www.st.com/stonline/leadfree/, with specific technical application notes
covering the main technical aspects related to lead-free conversion (AN2033, AN2034,
AN2035 and AN2036).
20.3.1
Compatibility
®
ECOPACK LQFP packages are fully compatible with lead (Pb) containing soldering
process (see application note AN2034).
Table 143. Soldering compatibility (wave and reflow soldering process)
Package
Plating material
Pb solder paste
Pb-free solder paste
LQFP32
NiPdAu (nickel-palladium-gold)
Yes
Yes
LQFP44
LQFP64
Sn (pure tin)
232/250
ST72325xxx-Auto
Device configuration and ordering information
21
Device configuration and ordering information
Each device is available for production in user programmable versions (Flash) as well as in
factory coded versions (FASTROM).
ST72P325 devices are Factory Advanced Service Technique ROM (FASTROM) versions:
They are factory-programmed HDFlash devices. Flash devices are shipped to customers
with a default content, whereas ROM/FASTROM factory coded parts contain the code
supplied by the customer. This implies that Flash devices have to be configured by the
customer using the option bytes while the ROM/FASTROM devices are factory-configured.
Detailed device configuration and ordering information is presented in the following
Section 21.1: Flash devices and Section 21.2: FASTROM device ordering information and
transfer of customer code.
21.1
Flash devices
21.1.1
Flash configuration
Table 144. Flash option bytes
Static option byte 0
Static option byte 1
7
6
5
4
3
2
1
0
1
7
6
1
5
4
3
2
1
0
1
WDG
HALT SW
VD
OSCTYPE
OSCRANGE
CSS
Reserved
1
0
0
0
1
1
0
0
2
1
1
0
Default
value:
(1)
1
1
1
1
1
0
1
1. Depends on device type as defined in Table 147: Package selection (OPT7) on page 235
The option bytes allow the hardware configuration of the microcontroller to be selected.
They have no address in the memory map and can be accessed only in programming mode
(for example, using a standard ST7 programming tool). The default content of the Flash is
fixed to FFh. To program the Flash devices directly using ICP, Flash devices are shipped to
customers with the internal RC clock source enabled. In masked ROM devices, the option
bytes are fixed in hardware by the ROM code (see option list).
Table 145. Option byte 0 bit description
Bit
Name
Function
Watchdog and Halt mode
This option bit determines if a RESET is generated when entering
Halt mode while the Watchdog is active.
OPT7
WDG HALT
0: No Reset generation when entering Halt mode
1: Reset generation when entering Halt mode
Hardware or software watchdog
This option bit selects the watchdog type.
0: Hardware (watchdog always enabled)
1: Software (watchdog to be enabled by software)
OPT6
WDG SW
233/250
Device configuration and ordering information
ST72325xxx-Auto
Table 145. Option byte 0 bit description (continued)
Bit Name Function
Clock security system on/off
This option bit enables or disables the clock security system (CSS)
function which includes the clock filter and the backup safe oscillator.
0: CSS enabled
OPT5
CSS
1: CSS disabled
Voltage detection
These option bits enable the voltage detection block (LVD and AVD)
with a selected threshold for the LVD and AVD (EVD + AVD).
00: Selected LVD = Highest threshold (VDD~4V)
01: Selected LVD = Medium threshold (VDD~3.5V)
10: Selected LVD = Lowest threshold (VDD~3V)
11: LVD and AVD off
OPT4:3
VD[1:0]
Caution: If the medium or low thresholds are selected, the detection
may occur outside the specified operating voltage range. Below 3.8V,
device operation is not guaranteed. For details on the AVD and LVD
threshold levels refer to Section 19.3.2: Operating conditions with low
voltage detector (LVD) on page 198.
OPT2:1
OPT0
-
Reserved, must be kept at default value
Flash memory readout protection
Readout protection, when selected, provides a protection against
program memory content extraction and against write access to Flash
memory.
Erasing the option bytes when the FMP_R option is selected causes
the whole user memory to be erased first, after which the device can
be reprogrammed. Refer to Section 4.3.1: Readout protection on
page 40 and the ST7 Flash Programming Reference Manual for more
details.
FMP_R
0: Readout protection enabled
1: Readout protection disabled
Table 146. Option byte 1 bit description
Bit
Name
Function
Package selection bit 1
OPT7
PKG1
This option bit selects the package (see Table 147: Package selection
(OPT7)).
RESET clock cycle selection
This option bit selects the number of CPU cycles applied during the
RESET phase and when exiting Halt mode. For resonator oscillators,
it is advised to select 4096 due to the long crystal stabilization time.
0: Reset phase with 4096 CPU cycles
OPT6
RSTC
1: Reset phase with 256 CPU cycles
Oscillator type
These option bits select the ST7 main clock source type.
00: Clock source = Resonator oscillator
01: Reserved
OPT5:4 OSCTYPE[1:0]
10: Clock source = Internal RC oscillator
11: Clock source = External source
234/250
ST72325xxx-Auto
Device configuration and ordering information
Function
Table 146. Option byte 1 bit description (continued)
Bit
Name
Oscillator range
When the resonator oscillator type is selected, these option bits select
the resonator oscillator current source corresponding to the frequency
range of the resonator used. When the external clock source is
selected, these bits are set to medium power (2 ~ 4 MHz).
000: Typ. frequency range = 1 ~ 2 MHz
OPT3:1 OSCRANGE[2:0]
001: Typ. frequency range = 2 ~ 4 MHz
010: Typ. frequency range = 4 ~ 8 MHz
011: Typ. frequency range = 8 ~ 16 MHz
PLL activation
This option bit activates the PLL which allows multiplication by two of
the main input clock frequency. The PLL is guaranteed only with an
input frequency between 2 and 4 MHz. For this reason the PLL must
not be used with the internal RC oscillator.
OPT0
PLLOFF
0: PLL x2 enabled
1: PLL x2 disabled
Caution: The PLL can be enabled only if the OSCRANGE (OPT3:1) bits
are configured to 2 ~ 4 MHz. Otherwise, the device functionality is not
guaranteed.
Table 147. Package selection (OPT7)
Version
Selected package
Flash size
PKG1
R/AR
LQFP64
LQFP44
LQFP32
32/48/60 Kbytes
48/60 Kbytes
16/32 Kbytes
16/32 Kbytes
1
0
1
0
J
K
Note:
On the chip, each I/O port has up to eight pads. Pads that are not bonded to external pins
are in input pull-up configuration after reset. The configuration of these pads must be kept at
reset state to avoid added current consumption.
235/250
Device configuration and ordering information
ST72325xxx-Auto
21.1.2
Flash ordering information
The following Table 148 serves as a guide for ordering.
Table 148. Flash user programmable device types
Order code(1)
Package
Memory (Kbytes)
Temperature range
ST72F325K4TATRE
ST72F325K6TATRE
ST72F325J4TATRE
ST72F325J6TATRE
ST72F325J7TATRE
ST72F325J9TATRE
ST72F325AR6TATRE
ST72F325AR7TATRE
ST72F325AR9TATRE
ST72F325R6TATRE
ST72F325R7TATRE
ST72F325R9TATRE
ST72F325K4TCTRE
ST72F325K6TCTRE
ST72F325J4TCTRE
ST72F325J6TCTRE
ST72F325J7TCTRE
ST72F325J9TCTRE
ST72F325AR6TCTRE
ST72F325AR7TCTRE
ST72F325AR9TCTRE
ST72F325R6TCTRE
ST72F325R7TCTRE
ST72F325R9TCTRE
16
32
16
32
48
60
32
48
60
32
48
60
16
32
16
32
48
60
32
48
60
32
48
60
LQFP32 (7 x 7)
LQFP44 (10 x 10)
LQFP64 (10 x 10)
-40°C to +85°C
LQFP64 (14 x 14)
LQFP32 (7 x 7)
LQFP44 (10 x 10)
-40°C to +125°C
LQFP64 (10 x 10)
LQFP64 (14 x 14)
1. TR = Tape and Reel (left blank if Tray)
236/250
ST72325xxx-Auto
Device configuration and ordering information
Figure 104. Flash commercial product code structure
DEVICE PINOUT PROG MEM PACKAGE TEMP RANGE TR E
®
E = Lead-free (ECOPACK )
Conditioning options:
TR = Tape and Reel (left blank if Tray)
A = -40 to +85°C
C = -40 to +125°C
T = Low profile quad flat pack
4 = 16 Kbytes
6 = 32 Kbytes
7 = 48 Kbytes
9 = 60 Kbytes
K = 32 pins
J = 44 pins
AR = 64 pins (10x10)
R = 64 pins (14x14)
ST72F325
21.2
FASTROM device ordering information and transfer of
customer code
Customer code is made up of the FASTROM contents and the list of the selected options (if
any). The FASTROM contents are to be sent on diskette, or by electronic means, with the
S19 hexadecimal file generated by the development tool. All unused bytes must be set to
FFh.
Complete the appended ST72325-Auto Microcontroller FASTROM Option List on page 240
to communicate the selected options to STMicroelectronics and check for regular updates of
the option list on the ST website or ask your ST representative.
Refer to application note AN1635 for information on the counter listing returned by ST after
code has been transferred.
The following Table 149: FASTROM factory coded device types serves as a guide for
ordering. The STMicroelectronics Sales Organization will be pleased to provide detailed
information on contractual points.
Table 149. FASTROM factory coded device types
Order code(1)
Package
Memory (Kbytes)
Temperature range
ST72P325(K4)TA/xxxRE
ST72P325(K6)TA/xxxRE
ST72P325(J4)TA/xxxRE
ST72P325(J6)TA/xxxRE
ST72P325(J7)TA/xxxRE
ST72P325(J9)TA/xxxRE
16
32
16
32
48
60
LQFP32 (7 x 7)
-40°C to +85°C
LQFP44 (10 x 10)
237/250
Device configuration and ordering information
Table 149. FASTROM factory coded device types (continued)
ST72325xxx-Auto
Temperature range
Order code(1)
Package
Memory (Kbytes)
ST72P325(AR6)TA/xxxRE
ST72P325(AR7)TA/xxxRE
ST72P325(AR9)TA/xxxRE
ST72P325(R6)TA/xxxRE
ST72P325(R7)TA/xxxRE
ST72P325(R9)TA/xxxRE
ST72P325(K4)TB/xxxRE
ST72P325(K6)TB/xxxRE
ST72P325(J4)TB/xxxRE
ST72P325(J6)TB/xxxRE
ST72P325(J7)TB/xxxRE
ST72P325(J9)TB/xxxRE
ST72P325(AR6)TB/xxxRE
ST72P325(AR7)TB/xxxRE
ST72P325(AR9)TB/xxxRE
ST72P325(R6)TB/xxxRE
ST72P325(R7)TB/xxxRE
ST72P32(5R9)TB/xxxRE
ST72P325(K4)TC/xxxRE
ST72P325(K6)TC/xxxRE
ST72P325(J4)TC/xxxRE
ST72P325(J6)TC/xxxRE
ST72P325(J7)TC/xxxRE
ST72P325(J9)TC/xxxRE
ST72P325(AR6)TC/xxxRE
ST72P325(AR7)TC/xxxRE
ST72P325(AR9)TC/xxxRE
ST72P325(R6)TC/xxxRE
ST72P325(R7)TC/xxxRE
ST72P325(R9)TC/xxxRE
32
48
60
32
48
60
16
32
16
32
48
60
32
48
60
32
48
60
16
32
16
32
48
60
32
48
60
32
48
60
LQFP64 (10 x 10)
-40°C to +85°C
LQFP64 (14 x 14)
LQFP32 (7 x 7)
LQFP44 (10 x 10)
LQFP64 (10 x 10)
-40°C to +105°C
LQFP64 (14 x 14)
LQFP32 (7 x 7)
LQFP44 (10 x 10)
-40°C to +125°C
LQFP64 (10 x 10)
LQFP64 (14 x 14)
1. - The two or three characters in parentheses which represent the pinout and program memory size are for
reference only and are not visible in the final commercial product order code.
- ‘xxx’ represents the code name defined by STMicroelectronics: It denotes the ROM code, pinout and
program memory size.
- R = Tape and Reel (left blank if Tray)
238/250
ST72325xxx-Auto
Device configuration and ordering information
Figure 105. FASTROM commercial product code structure
DEVICE PACKAGE TEMP RANGE
/ xxx R E
®
E = Lead-free (ECOPACK )
Conditioning options:
R = Tape and Reel (left blank if Tray)
Code name (defined by STMicroelectronics)
(denotes ROM code, pinout and program memory size)
A = -40 to +85°C
B = -40 to +105°C
C = -40 to +125°C
T = Low profile quad flat pack
ST72P325
239/250
Device configuration and ordering information
ST72325xxx-Auto
ST72325-Auto Microcontroller FASTROM Option List
(Last update: August 2007)
Customer:
Address:
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact:
Phone No:
Reference:
The FASTROM/ROM code name is assigned by STMicroelectronics)
FASTROM/ROM code must be sent in .S19 format. .Hex extension cannot be processed.
Device Type/Memory Size/Package (check only one option):
----------------------------------|------------------------------|-----------------------------|----------------------------- |----------------------------- |
FASTROM DEVICE:
|
60K
|
48K
|
32K
|
16K
|
----------------------------------|------------------------------|-----------------------------|----------------------------- |----------------------------- |
LQFP64 14x14:
LQFP64 10x10:
LQFP44 10x10:
LQFP32 7x7:
| [ ] ST72P325R9T
| [ ] ST72P325AR9T | [ ] ST72P325AR7T | [ ] ST72P325AR6T
| [ ] ST72P325J9T
|
| [ ] ST72P325R7T
| [ ] ST72P325R6T
|
|
|
|
|
|
| [ ] ST72P325J7T
|
| [ ] ST72P325J6T
| [ ] ST72P325K6T
| [ ] ST72P325J4T
| [ ] ST72P325K4T
----------------------------------|------------------------------|-----------------------------|----------------------------- |----------------------------- |
Conditioning for LQFP package (check only one option):
[ ] Tape and Reel
[ ] Tray
Temperature range:
Special marking:
[ ] A (-40°C to +85°C)
[ ] B (-40°C to +105°C)
[ ] C (-40°C to +125°C)
[ ] No
[ ] Yes "_ _ _ _ _ _ _ _ _ _ "
LQFP32 7 characters, other packages 10 characters max.
Authorized characters are letters, digits, '.', '-', '/' and spaces only.
Clock source selection: [ ] Resonator:
[ ] LP: Low power resonator (1 to 2 MHz)
[ ] MP: Medium power resonator (2 to 4 MHz)
[ ] MS: Medium speed resonator (4 to 8 MHz)
[ ] HS: High speed resonator (8 to 16 MHz)
[ ] Internal RC
[ ] External clock (sets MP Medium Power resonator in Option Byte)
(1)(2)
PLL
[ ] Disabled
[ ] Disabled
[ ] 256 Cycles
[ ] Enabled
LVD reset
[ ] High threshold
[ ] 4096 Cycles
[ ] Med. threshold
[ ] Low threshold
Reset delay
Watchdog selection
[ ] Software activation [ ] Hardware activation
Halt when Watchdog on [ ] Reset
Readout protection [ ] Disabled
[ ] No reset
[ ] Enabled
Date . . . . . . . . . . . . . . Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1. PLL must be disabled if internal RC network is selected.
2. The PLL can be enabled only if the resonator is configured to “Medium Power : 2~4 MHz”.
Please download the latest version of this option list from www.st.com.
240/250
ST72325xxx-Auto
Device configuration and ordering information
21.3
Development tools
21.3.1
Introduction
Development tools for the ST7 microcontrollers include a complete range of hardware
systems and software tools from STMicroelectronics and third-party tool suppliers. The
range of tools includes solutions to help you evaluate microcontroller peripherals, develop
and debug your application, and program your microcontrollers.
21.3.2
21.3.3
Evaluation tools and starter kits
ST offers complete, affordable starter kits and full-featured evaluation boards that allow you
to evaluate microcontroller features and quickly start developing ST7 applications. Starter
kits are complete, affordable hardware/software tool packages that include features and
samples to help you quickly start developing your application. ST evaluation boards are
open-design, embedded systems, which are developed and documented to serve as
references for your application design. They include sample application software to help you
demonstrate, learn about and implement your ST7’s features.
Development and debugging tools
Application development for ST7 is supported by fully optimizing C Compilers and the ST7
Assembler-Linker toolchain, which are all seamlessly integrated in the ST7 integrated
development environments in order to facilitate the debugging and fine-tuning of your
application. The Cosmic C Compiler is available in a free version that outputs up to
16 Kbytes of code.
The range of hardware tools includes cost effective ST7-DVP3 series emulators. These
tools are supported by the ST7 Toolset from STMicroelectronics, which includes the STVD7
integrated development environment (IDE) with high-level language debugger, editor,
project manager and integrated programming interface.
21.3.4
Programming tools
During the development cycle, the ST7-DVP3 and ST7-EMU3 series emulators and the
RLink provide in-circuit programming capability for programming the Flash microcontroller
on your application board.
ST also provides a low-cost dedicated in-circuit programmer, the ST7-STICK, as well as
ST7 socket boards which provide all the sockets required for programming any of the
devices in a specific ST7 subfamily on a platform that can be used with any tool with in-
circuit programming capability for ST7.
For production programming of ST7 devices, ST’s third-party tool partners also provide a
complete range of gang and automated programming solutions, which are ready to integrate
into your production environment.
For additional ordering codes for spare parts, accessories and tools available for the ST7
(including from third party manufacturers), refer to the online product selector at
www.st.com/mcu.
241/250
Device configuration and ordering information
Table 150. STMicroelectronics development tools
ST72325xxx-Auto
Programming
Emulation
Supported
products
ST7 DVP3 series
ST7 EMU3 series
ICC socket
board
Active probe
Emulator
Connection kit
Emulator
and T.E.B.
ST72325AR,
ST72F325AR
ST7MDT20-
T6A/DVP
ST7MDT20M-
EMU3
ST7MDT20M-
TEB
ST7SB20M/xx(1)
ST7SB20J/xx(1)
ST72325R,
ST72F325R,
ST7MDT20-
T64/DVP
ST7MDT20-
DVP3
ST72325J,
ST72F325J
ST7MDT20-
T44/DVP
ST7MDT20J-
EMU3
ST7MDT20J-
TEB
ST72325K,
ST72F325K
ST7MDT20-
T32/DVP
1. Add suffix /EU, /UK, /US for the power supply of your region.
Table 151. Suggested list of socket types
Device
Socket
Emulator adapter
CAB 3303351
LQFP64 14 x14
LQFP64 10 x10
LQFP44 10 x10
LQFP32 7 x 7
CAB 3303262
YAMAICHI IC149-064-*75-*5
YAMAICHI IC149-044-*52-*5
IRONWOOD SF-QFE32SA-L-01
YAMAICHI ICP-064-6
YAMAICHI ICP-044-5
IRONWOOD SK-UGA06/32A-01
21.3.5
Socket and emulator adapter information
For information on the type of socket that is supplied with the emulator, refer to the
suggested list of sockets in Table 151.
Note:
Before designing the board layout, it is recommended to check the overall dimensions of the
socket as they may be greater than the dimensions of the device.
For footprint and other mechanical information about these sockets and adapters, refer to
the manufacturer’s datasheet.
Related documentation
ST7 Visual Develop Software Key Debugging Features (AN 978)
ST7 Visual Develop for ST7 Cosmic C toolset users (AN 1938)
ST7 Visual Develop for ST7 Assembler Linker toolset users (AN 1940)
21.4
ST7 application notes
All relevant ST7 application notes can be found on www.st.com.
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Known limitations
22
Known limitations
22.1
All devices
22.1.1
Unexpected reset fetch
If an interrupt request occurs while a “POP CC” instruction is executed, the interrupt
controller does not recognize the source of the interrupt and, by default, passes the RESET
vector address to the CPU.
Workaround
To solve this issue, a “POP CC” instruction must always be preceded by a “SIM” instruction.
22.1.2
External interrupt missed
To avoid any risk of generating a parasitic interrupt, the edge detector is automatically
disabled for one clock cycle during an access to either DDR and OR. Any input signal edge
during this period will not be detected and will not generate an interrupt.
This case can typically occur if the application refreshes the port configuration registers at
intervals during runtime.
Workaround
The workaround is based on software checking the level on the interrupt pin before and after
writing to the PxOR or PxDDR registers. If there is a level change (depending on the
sensitivity programmed for this pin) the interrupt routine is invoked using the call instruction
with three extra PUSH instructions before executing the interrupt routine (this is to make the
call compatible with the IRET instruction at the end of the interrupt service routine).
But detection of the level change does not make sure that edge occurs during the critical 1
cycle duration and the interrupt has been missed. This may lead to occurrence of same
interrupt twice (one hardware and another with software call).
To avoid this, a semaphore is set to ‘1’ before checking the level change. The semaphore is
changed to level '0' inside the interrupt routine. When a level change is detected, the
semaphore status is checked. If it is ‘1’, it means that the last interrupt has been missed. In
this case, the interrupt routine is invoked with the call instruction.
There is another possible case, that is, if PxOR or PxDDR are written to with global
interrupts disabled (interrupt mask bit set). In this case, the semaphore is changed to ‘1’
when the level change is detected. Detecting a missed interrupt is done after the global
interrupts are enabled (interrupt mask bit reset) and by checking the status of the
semaphore. If it is ‘1’, it means that the last interrupt was missed and the interrupt routine is
invoked with the call instruction.
To implement the workaround, the following software sequence is to be followed for writing
into the PxOR/PxDDR registers. The example is for Port PF1 with falling edge interrupt
sensitivity. The software sequence is given for both cases (global interrupts disabled / global
interrupts enabled):
Case 1: Writing to PxOR or PxDDR with global interrupts enabled:
LD A,#01
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LD sema,A
; set the semaphore to '1'
LD A,PFDR
AND A,#02
LD X,A
; store the level before writing to PxOR/PxDDR
LD A,#$90
LD PFDDR,A
; Write to PFDDR
LD A,#$ff
LD PFOR,A
; Write to PFOR
LD A,PFDR
AND A,#02
LD Y,A
; store the level after writing to PxOR/PxDDR
LD A,X
; check for falling edge
cp A,#02
jrne OUT
TNZ Y
jrne OUT
LD A,sema
; check the semaphore status if edge is detected
CP A,#01
jrne OUT
call call_routine
; call the interrupt routine
OUT:LD A,#00
LD sema,A
.call_routine
; entry to call_routine
PUSH A
PUSH X
PUSH CC
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.ext1_rt
; entry to interrupt routine
LD A,#00
LD sema,A
IRET
Case 2: Writing to PxOR or PxDDR with global interrupts disabled:
SIM
; set the interrupt mask
LD A,PFDR
AND A,#$02
LD X,A
; store the level before writing to PxOR/PxDDR
LD A,#$90
LD PFDDR,A
; Write into PFDDR
LD A,#$ff
LD PFOR,A
; Write to PFOR
LD A,PFDR
AND A,#$02
LD Y,A
; store the level after writing to PxOR/PxDDR
LD A,X
; check for falling edge
cp A,#$02
jrne OUT
TNZ Y
jrne OUT
LD A,#$01
LD sema,A
; set the semaphore to '1' if edge is detected
RIM
; reset the interrupt mask
LD A,sema
; check the semaphore status
CP A,#$01
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jrne OUT
call call_routine
; call the interrupt routine
RIM
OUT:
RIM
JP while_loop
.call_routine
; entry to call_routine
PUSH A
PUSH X
PUSH CC
.ext1_rt
; entry to interrupt routine
LD A,#$00
LD sema,A
IRET
22.1.3
Clearing active interrupts outside interrupt routine
When an active interrupt request occurs at the same time as the related flag is being
cleared, an unwanted reset may occur.
Note:
Clearing the related interrupt mask will not generate an unwanted reset.
Concurrent interrupt context
The symptom does not occur when the interrupts are handled normally, that is, when:
●
●
●
The interrupt flag is cleared within its own interrupt routine
The interrupt flag is cleared within any interrupt routine
The interrupt flag is cleared in any part of the code while this interrupt is disabled
If these conditions are not met, the symptom can be avoided by implementing the following
sequence:
Perform SIM and RIM operation before and after resetting an active interrupt request.
Example:
SIM
Reset interrupt flag
RIM
Nested interrupt context
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The symptom does not occur when the interrupts are handled normally, that is, when:
●
●
The interrupt flag is cleared within its own interrupt routine
The interrupt flag is cleared within any interrupt routine with higher or identical priority
level
●
The interrupt flag is cleared in any part of the code while this interrupt is disabled
If these conditions are not met, the symptom can be avoided by implementing the following
sequence:
PUSH CC
SIM
Reset interrupt flag
POP CC
22.1.4
SCI wrong break duration
Description
A single break character is sent by setting and resetting the SBK bit in the SCICR2 register.
In some cases, the break character may have a longer duration than expected:
●
20 bits instead of 10 bits if M = 0
22 bits instead of 11 bits if M = 1
●
In the same way, as long as the SBK bit is set, break characters are sent to the TDO pin.
This may lead to generating one break more than expected.
Occurrence
The occurrence of the problem is random and proportional to the baud rate. With a transmit
frequency of 19200 baud (f
occurrence is around 1%.
= 8 MHz and SCIBRR = 0xC9), the wrong break duration
CPU
Workaround
If this wrong duration is not compliant with the communication protocol in the application,
software can request that an Idle line be generated before the break character. In this case,
the break duration is always correct assuming the application is not doing anything between
the idle and the break. This can be ensured by temporarily disabling interrupts.
The exact sequence is:
●
●
●
●
Disable interrupts
Reset and Set TE (IDLE request)
Set and Reset SBK (Break Request)
Re-enable interrupts
22.1.5
16-bit timer PWM mode
In PWM mode, the first PWM pulse is missed after writing the value FFFCh in the OC1R
register (OC1HR, OC1LR). It leads to either full or no PWM during a period, depending on
the OLVL1 and OLVL2 settings.
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22.1.6
TIMD set simultaneously with OC interrupt
If the 16-bit timer is disabled at the same time the output compare event occurs, the output
compare flag then gets locked and cannot be cleared before the timer is enabled again.
Impact on the application
If the output compare interrupt is enabled, then the output compare flag cannot be cleared in
the timer interrupt routine. Consequently, the interrupt service routine is called repeatedly.
Workaround
Disable the timer interrupt before disabling the timer. Again while enabling, first enable the
timer, then the timer interrupts.
●
Perform the following to disable the timer:
–
–
TACR1 or TBCR1 = 0x00h; // Disable the compare interrupt
TACSR | or TBCSR | = 0x40; // Disable the timer
●
Perform the following to enable the timer again:
–
–
TACSR & or TBCSR & = ~0x40; // Enable the timer
TACR1 or TBCR1 = 0x40; // Enable the compare interrupt
22.1.7
22.1.8
I2C multimaster
In multimaster configurations, if the ST7 I2C receives a START condition from another I2C
master after the START bit is set in the I2CCR register and before the START condition is
generated by the ST7 I2C, it may ignore the START condition from the other I2C master. In
this case, the ST7 master will receive a NACK from the other device. On reception of the
NACK, ST7 can send a restart and Slave address to re-initiate communication.
Pull-up always active on PE2
The I/O port internal pull-up is always active on I/O port E2. As a result, if PE2 is in output
mode low level, current consumption in Halt/Active Halt mode is increased.
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Revision history
23
Revision history
Table 152. Document revision history
Date
Revision
Changes
30-Aug-2007
1
Initial release
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