ST72P334J4B [STMICROELECTRONICS]
8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES; 8位MCU单电压闪存， ADC ， 16位定时器， SPI ， SCI INTERFACES
| 型号： | ST72P334J4B |
| 厂家： | 
ST |
| 描述： | 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES |
| 文件： | 总153页 (文件大小：1929K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ST72334J/N,
ST72314J/N, ST72124J
8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY,
ADC, 16-BIT TIMERS, SPI, SCI INTERFACES
■ Memories
– 8K or 16K Program memory (ROM or single
voltage FLASH) with read-out protection and
in-situ programming (remote ISP)
– 256 bytes EEPROM Data memory (with read-
out protection option in ROM devices)
– 384 or 512 bytes RAM
■ Clock, Reset and Supply Management
PSDIP42
PSDIP56
– Enhanced reset system
– Enhanced low voltage supply supervisor with
3 programmable levels
– Clock sources: crystal/ceramic resonator os-
cillators or RC oscillators, external clock,
backup Clock Security System
– 4 Power Saving Modes: Halt, Active-Halt,
Wait and Slow
– Beep and clock-out capabilities
■ Interrupt Management
TQFP64
14 x 14
TQFP44
10 x 10
– 10 interrupt vectors plus TRAP and RESET
– 15 external interrupt lines (4 vectors)
■ 44 or 32 I/O Ports
■ 1 Analog Peripheral
– 44 or 32 multifunctional bidirectional I/O lines:
– 21 or 19 alternate function lines
– 12 or 8 high sink outputs
– 8-bit ADC with 8 input channels (6 only on
ST72334Jx, not available on ST72124J2)
■ 4 Timers
■ Instruction Set
– Configurable watchdog timer
– Realtime base
– Two 16-bit timers with: 2 input captures (only
one on timer A), 2 output compares (only one
on timer A), External clock input on timer A,
PWM and Pulse generator modes
– 8-bit data manipulation
– 63 basic instructions
– 17 main addressing modes
– 8 x 8 unsigned multiply instruction
– True bit manipulation
■ 2 Communications Interfaces
– SPI synchronous serial interface
– SCI asynchronous serial interface (LIN com-
patible)
■ Development Tools
– Full hardware/software development package
Device Summary
Features
ST72124J2 ST72314J2 ST72314J4 ST72314N2 ST72314N4 ST72334J2 ST72334J4 ST72334N2 ST72334N4
Program memory - bytes
RAM (stack) - bytes
EEPROM - bytes
8K
8K
16K
512 (256)
-
8K
16K
8K
384 (256)
256
16K
512 (256)
256
8K
384 (256)
256
16K
512 (256)
256
384 (256)
-
384 (256)
-
384 (256)
512 (256)
Watchdog, Two 16-bit Timers, SPI, SCI
Peripherals
-
ADC
3.2V to 5.5V
Operating Supply
CPU Frequency
Operating Temperature
Packages
Up to 8 MHz (with up to 16 MHz oscillator)
-40°C to +85°C (-40°C to +105/125°C optional)
TQFP64 / SDIP56 TQFP44 / SDIP42
TQFP44 / SDIP42
TQFP64 / SDIP56
Rev. 2.5
April 2003
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1
Table of Contents
1 PREAMBLE: ST72C334 VERSUS ST72E331 SPECIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.3 STRUCTURAL ORGANISATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.4 IN-SITU PROGRAMMING (ISP) MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.5 MEMORY READ-OUT PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6 DATA EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.3 MEMORY ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.4 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.5 ACCESS ERROR HANDLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.6 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7 DATA EEPROM Register Map and Reset Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.1 READ-OUT PROTECTION OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
9 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
9.1 LOW VOLTAGE DETECTOR (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
9.2 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
9.3 MULTI-OSCILLATOR (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9.4 CLOCK SECURITY SYSTEM (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
9.5 SUPPLY, RESET AND CLOCK REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . 32
10 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
10.1 NON MASKABLE SOFTWARE INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
10.2 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
10.3 PERIPHERAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
11 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
11.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
11.2 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
11.3 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
11.4 ACTIVE-HALT AND HALT MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
12 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
12.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
12.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
12.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
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12.4 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
12.5 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
13 MISCELLANEOUS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
13.1 I/O PORT INTERRUPT SENSITIVITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
13.2 I/O PORT ALTERNATE FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
13.3 REGISTERS DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
14 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
14.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
14.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK TIMER (MCC/RTC) . . . . . . . 52
14.3 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
14.4 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
14.5 SERIAL COMMUNICATIONS INTERFACE (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
14.6 8-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
15 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
15.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
15.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
16 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
16.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
16.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
16.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
16.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
16.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
16.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
16.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
16.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
16.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
16.10 TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
16.11 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 135
16.12 8-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
17 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
17.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
17.2 SOLDERING AND GLUEABILITY INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
18 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . 144
18.1 OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
18.2 TRANSFER OF CUSTOMER CODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
18.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
18.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
19 IMPORTANT NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
19.1 SCI BAUD RATE REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
20 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
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3
ST72334J/N, ST72314J/N, ST72124J
To obtain the most recent version of this datasheet,
please check at www.st.com>products>technical literature>datasheet.
Please also pay special attention to the Section “IMPORTANT NOTES” on page 151
4/153
ST72334J/N, ST72314J/N, ST72124J
1 PREAMBLE: ST72C334 VERSUS ST72E331 SPECIFICATION
New Features available on the ST72C334
or 16K FLASH/ROM with In-Situ
New Memory Locations in ST72C334
■ 20h: MISCR register becomes MISCR1 register
■ 8
Programming and Read-out protection
(naming change)
■ New ADC with a better accuracy and conversion
■ 29h: new control/status register for the MCC
time
module
■ New configurable Clock, Reset and Supply
■ 2Bh: new control/status register for the Clock,
Reset and Supply control. This register replaces
the WDGSR register keeping the WDOGF flag
compatibility.
system
■ New power saving mode with real time base:
Active Halt
■ 40h: new MISCR2 register
■ Beep capability on PF1
■ New interrupt source: Clock security system
(CSS) or Main clock controller (MCC)
ST72C334 I/O Configuration and Pinout
■ Same pinout as ST72E331
■ PA6 and PA7 are true open drain I/O ports
without pull-up (same as ST72E331)
■ PA3, PB3, PB4 and PF2 have no pull-up
configuration (all I/Os present on TQFP44)
■ PA5:4, PC3:2, PE7:4 and PF7:6 have high sink
capabilities (20mA on N-buffer, 2mA on P-buffer
and pull-up). On the ST72E331, all these pads
(except PA5:4) were 2mA push-pull pads
without high sink capabilities. PA4 and PA5
were 20mA true open drains.
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ST72334J/N, ST72314J/N, ST72124J
2 INTRODUCTION
FLASH memory with byte-by-byte In-Situ Pro-
gramming (ISP) capability.
The ST72334J/N, ST72314J/N and ST72124J de-
vices are members of the ST7 microcontroller fam-
ily. They can be grouped as follows:
Under software control, all devices can be placed
in WAIT, SLOW, ACTIVE-HALT or HALT mode,
reducing power consumption when the application
is in idle or standby state.
– ST72334J/N devices are designed for mid-range
applications with Data EEPROM, ADC, SPI and
SCI interface capabilities.
The enhanced instruction set and addressing
modes of the ST7 offer both power and flexibility to
software developers, enabling the design of highly
efficient and compact application code. In addition
to standard 8-bit data management, all ST7 micro-
controllers feature true bit manipulation, 8x8 un-
signed multiplication and indirect addressing
modes.
– ST72314J/N devices target the same range of
applications but without Data EEPROM.
– ST72124J devices are for applications that do
not need Data EEPROM and the ADC peripher-
al.
All devices are based on a common industry-
standard 8-bit core, featuring an enhanced instruc-
tion set.
For easy reference, all parametric data are located
in Section 16 on page 107.
The
ST72C334J/N,
ST72C314J/N
and
ST72C124J versions feature single-voltage
Figure 1. General Block Diagram
8-BIT CORE
ALU
PROGRAM
MEMORY
(8K or 16K Bytes)
RESET
ISPSEL
CONTROL
RAM
V
V
DD
(384 or 512 Bytes)
LVD
SS
EEPROM
(256 Bytes)
MULTI OSC
+
CLOCK FILTER
OSC1
OSC2
PA7:0
PORT A
MCC/RTC
(8-BIT for N versions)
(5-BIT for J versions)
PB7:0
PORT B
PORT F
TIMER A
BEEP
(8-BIT for N versions)
(5-BIT for J versions)
PF7,6,4,2:0
(6-BIT)
PORT C
PC7:0
TIMER B
(8-BIT)
SPI
PORT E
SCI
PE7:0
(6-BIT for N versions)
PORT D
(2-BIT for J versions)
PD7:0
(8-BIT for N versions)
(6-BIT for J versions)
8-BIT ADC
WATCHDOG
V
V
DDA
SSA
6/153
ST72334J/N, ST72314J/N, ST72124J
3 PIN DESCRIPTION
Figure 2. 64-Pin TQFP Package Pinout (N versions)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
V
V
(HS) PE4
1
(HS) PE5
2
(HS) PE6
3
(HS) PE7
4
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SS_1
DD_1
PA3
PA2
ei0
PA1
PB0
5
PB1
6
PB2
7
PB3
8
PA0
ei2
PC7 / SS
PC6 / SCK / ISPCLK
PC5 / MOSI
PC4 / MISO / ISPDATA
PC3 (HS) / ICAP1_B
PC2 (HS) / ICAP2_B
PC1 / OCMP1_B
PC0 / OCMP2_B
PB4
9
PB5
10
ei3
PB6
PB7
11
12
13
14
15
16
AIN0 / PD0
AIN1 / PD1
AIN2 / PD2
AIN3 / PD3
ei1
V
SS_0
V
DD_0
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
(HS) 20mA high sink capability
ei
associated external interrupt vector
x
7/153
ST72334J/N, ST72314J/N, ST72124J
PIN DESCRIPTION (Cont’d)
Figure 3. 56-Pin SDIP Package Pinout (N versions)
1
PB4
PB5
PB3
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
PB2
2
ei3
ei2
PB6
PB1
3
PB7
PB0
4
PE7 (HS)
AIN0 / PD0
AIN1 / PD1
AIN2 / PD2
AIN3 / PD3
AIN4 / PD4
AIN5 / PD5
AIN6 / PD6
AIN7 / PD7
5
PE6 (HS)
PE5 (HS)
PE4 (HS)
PE1 / RDI
PE0 / TDO
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
V
_2
DD
OSC1
OSC2
V
DDA
V
V
_2
SSA
SS
MCO / PF0
BEEP / PF1
RESET
ISPSEL
ei1
PF2
PA7 (HS)
PA6 (HS)I
PA5 (HS)
PA4 (HS)
OCMP1_A / PF4
ICAP1_A / (HS) PF6
EXTCLK_A / (HS) PF7
V
V
V
DD_0
SS_1
V
SS_0
DD_1
OCMP2_B / PC0
OCMP1_B / PC1
PA3
PA2
ei0
ICAP2_B / (HS) PC2
ICAP1_B / (HS) PC3
ISPDATA/ MISO / PC4
MOSI / PC5
PA1
PA0
PC7 / SS
PC6 / SCK / ISPCLK
(HS) 20mA high sink capability
ei associated external interrupt vector
x
8/153
ST72334J/N, ST72314J/N, ST72124J
PIN DESCRIPTION (Cont’d)
Figure 4. 44-Pin TQFP and 42-Pin SDIP Package Pinouts (J versions)
44 43 42 41 40 39 38 37 36 35 34
PE1 / RDI
PB0
V
V
1
33
32
31
30
29
28
27
26
25
24
23
SS_1
DD_1
2
PB1
PA3
3
ei0
ei2
ei3
PB2
PC7 / SS
4
PB3
PC6 / SCK / ISPCLK
PC5 / MOSI
5
PB4
6
AIN0 / PD0
AIN1 / PD1
AIN2 / PD2
AIN3 / PD3
AIN4 / PD4
PC4 / MISO / ISPDATA
PC3 (HS) / ICAP1_B
PC2 (HS) / ICAP2_B
PC1 / OCMP1_B
PC0 / OCMP2_B
7
8
9
ei1
10
11
12 13 14 15 16 17 18 19 20 21 22
1
PB4
EI3
PB3
PB2
PB1
PB0
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
AIN0 / PD0
AIN1 / PD1
AIN2 / PD2
AIN3 / PD3
AIN4 / PD4
AIN5 / PD5
2
ei2
3
4
PE1 / RDI
PE0 / TDO
5
6
V
_2
7
DD
V
OSC1
OSC2
8
DDA
V
9
SSA
MCO / PF0
BEEP / PF1
V
_2
SS
10
11
12
13
14
15
16
17
18
19
20
21
RESET
ei1
PF2
ISPSEL
OCMP1_A / PF4
ICAP1_A / (HS) PF6
EXTCLK_A / (HS) PF7
OCMP2_B / PC0
PA7 (HS)
PA6 (HS)
PA5 (HS)
PA4 (HS)
OCMP1_B / PC1
ICAP2_B/ (HS) PC2
ICAP1_B / (HS) PC3
ISPDATA / MISO / PC4
MOSI / PC5
V
SS_1
V
DD_1
PA3
ei0
PC7 / SS
PC6 / SCK / ISPCLK
(HS) 20mA high sink capability
ei associated external interrupt vector
x
9/153
ST72334J/N, ST72314J/N, ST72124J
PIN DESCRIPTION (Cont’d)
For external pin connection guidelines, refer to Section 16 "ELECTRICAL CHARACTERISTICS" on page
107.
Legend / Abbreviations for Table 1:
Type:
I = input, O = output, S = supply
A = Dedicated analog input
Input level:
In/Output level: C = CMOS 0.3V /0.7V
,
DD
DD
C = CMOS 0.3V /0.7V with input trigger
T
DD
DD
Output level:
HS = 20mA high sink (on N-buffer only)
Port and control configuration:
1)
– Input:
float = floating, wpu = weak pull-up, int = interrupt , ana = analog
2)
– Output:
OD = open drain , PP = push-pull
Refer to Section 12 "I/O PORTS" on page 39 for more details on the software configuration of the I/O
ports.
The RESET configuration of each pin is shown in bold. This configuration is valid as long as the device is
in reset state.
Table 1. Device Pin Description
Pin n°
Level
Port
Main
function
(after
Input
Output
Pin Name
Alternate function
reset)
1 49
PE4 (HS)
I/O C HS
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Port E4
Port E5
Port E6
Port E7
Port B0
Port B1
Port B2
Port B3
Port B4
Port B5
Port B6
Port B7
T
2 50
3 51
4 52
PE5 (HS)
PE6 (HS)
PE7 (HS)
I/O C HS
X
T
I/O C HS
X
T
I/O C HS
X
T
5 53 2 39 PB0
6 54 3 40 PB1
7 55 4 41 PB2
8 56 5 42 PB3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
S
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
ei2
ei2
ei2
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
ei2
ei3
ei3
9
1
6
1
PB4
10 2
11 3
12 4
13 5
14 6
15 7
PB5
PB6
ei3
ei3
PB7
7
8
9
2
3
4
PD0/AIN0
PD1/AIN1
PD2/AIN2
X
X
X
X
X
X
X
X
X
Port D0 ADC Analog Input 0
Port D1 ADC Analog Input 1
Port D2 ADC Analog Input 2
Port D3 ADC Analog Input 3
Port D4 ADC Analog Input 4
Port D5 ADC Analog Input 5
Port D6 ADC Analog Input 6
Port D7 ADC Analog Input 7
Analog Power Supply Voltage
Analog Ground Voltage
X
X
X
X
X
X
X
16 8 10 5 PD3/AIN3
17 9 11 6 PD4/AIN4
18 10 12 7 PD5/AIN5
19 11
PD6/AIN6
PD7/AIN7
20 12
21 13 13 8
22 14 14 9
23
V
V
V
DDA
SSA
S
S
Digital Main Supply Voltage
DD_3
10/153
ST72334J/N, ST72314J/N, ST72124J
Pin n°
Level
Port
Main
function
(after
Input
Output
Pin Name
Alternate function
reset)
24
V
S
Digital Ground Voltage
Port F0 Main clock output (f
Port F1 Beep signal output
Port F2
SS_3
25 15 15 10 PF0/MCO
26 16 16 11 PF1/BEEP
27 17 17 12 PF2
I/O
I/O
I/O
C
C
C
X
X
X
ei1
ei1
X
X
X
X
X
X
/2)
OSC
T
T
T
ei1
28
29 18 18 13 PF4/OCMP1_A
30 NC
31 19 19 14 PF6 (HS)/ICAP1_A
32 20 20 15 PF7 (HS)/EXTCLK_A I/O C HS
NC
Not Connected
Port F4 Timer A Output Compare 1
Not Connected
I/O
C
X
X
X
X
T
I/O C HS
X
X
X
X
X
X
X
Port F6 Timer A Input Capture 1
T
X
Port F7 Timer A External Clock Source
Digital Main Supply Voltage
Digital Ground Voltage
Port C0 Timer B Output Compare 2
Port C1 Timer B Output Compare 1
Port C2 Timer B Input Capture 2
Port C3 Timer B Input Capture 1
Port C4 SPI Master In / Slave Out Data
Port C5 SPI Master Out / Slave In Data
Port C6 SPI Serial Clock
Port C7 SPI Slave Select (active low)
Port A0
T
33 21 21
34 22 22
V
V
S
S
DD_0
SS_0
35 23 23 16 PC0/OCMP2_B
36 24 24 17 PC1/OCMP1_B
37 25 25 18 PC2 (HS)/ICAP2_B
38 26 26 19 PC3 (HS)/ICAP1_B
39 27 27 20 PC4/MISO
I/O
I/O
C
C
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
T
T
I/O C HS
T
I/O C HS
T
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
S
C
C
C
C
C
C
C
C
T
T
T
T
T
T
T
T
40 28 28 21 PC5/MOSI
41 29 29 22 PC6/SCK
42 30 30 23 PC7/SS
43 31
44 32
45 33
PA0
PA1
PA2
ei0
ei0
ei0
Port A1
Port A2
46 34 31 24 PA3
ei0
Port A3
47 35 32 25 V
48 36 33 26 V
Digital Main Supply Voltage
Digital Ground Voltage
Port A4
DD_1
SS_1
S
49 37 34 27 PA4 (HS)
50 38 35 28 PA5 (HS)
51 39 36 29 PA6 (HS)
52 40 37 30 PA7 (HS)
I/O C HS
X
X
X
X
X
X
X
T
T
X
X
T
I/O C HS
X
Port A5
T
I/O C HS
Port A6
T
I/O C HS
Port A7
T
Must be tied low in user mode. In pro-
gramming mode when available, this pin
acts as In-Situ Programming mode se-
lection.
53 41 38 31 ISPSEL
I
Top priority non maskable interrupt (ac-
tive low)
54 42 39 32 RESET
I/O
C
X
X
55
56
NC
NC
Not Connected
Digital Ground Voltage
57 43 40 33 V
S
SS_3
Resonator oscillator inverter output or
capacitor input for RC oscillator
3)
58 44 41 34 OSC2
O
11/153
ST72334J/N, ST72314J/N, ST72124J
Pin n°
Level
Port
Main
function
(after
Input
Output
Pin Name
Alternate function
reset)
External clock input or Resonator oscilla-
tor inverter input or resistor input for RC
oscillator
3)
59 45 42 35 OSC1
60 46 43 36 V
I
S
Digital Main Supply Voltage
Port E0 SCI Transmit Data Out
Port E1 SCI Receive Data In
DD_3
61 47 44 37 PE0/TDO
62 48 1 38 PE1/RDI
I/O
I/O
C
C
X
X
X
X
X
X
X
X
T
T
63
64
NC
NC
Not Connected
Notes:
1. In the interrupt input column, “ei ” defines the associated external interrupt vector. If the weak pull-up
x
column (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input,
else the configuration is floating interrupt input.
2. In the open drain output column, “T” defines a true open drain I/O (P-Buffer and protection diode to V
are not implemented). See Section 12 "I/O PORTS" on page 39 and Section 16.8 "I/O PORT PIN CHAR-
ACTERISTICS" on page 128 for more details.
DD
3. OSC1 and OSC2 pins connect a crystal or ceramic resonator, an external RC, or an external source to
the on-chip oscillator see Section 3 "PIN DESCRIPTION" on page 7 and Section 16.5 "CLOCK AND TIM-
ING CHARACTERISTICS" on page 116 for more details.
12/153
ST72334J/N, ST72314J/N, ST72124J
4 REGISTER & MEMORY MAP
As shown in the Figure 5, the MCU is capable of
addressing 64K bytes of memories and I/O regis-
ters.
space includes up to 256 bytes for the stack from
0100h to 01FFh.
The highest address bytes contain the user reset
and interrupt vectors.
The available memory locations consist of 128
bytes of register locations, 384 or 512 bytes of
RAM, up to 256 bytes of data EEPROM and 4 or
8 Kbytes of user program memory. The RAM
IMPORTANT: Memory locations marked as “Re-
served” must never be accessed. Accessing a re-
served area can have unpredictable effects on the
device.
Figure 5. Memory Map
0080h
0000h
Short Addressing RAM
HW Registers
(see Table 2)
Zero page
(128 Bytes)
00FFh
007Fh
0080h
Stack or
16-bit Addressing RAM
(256 Bytes)
0100h
01FFh
384 Bytes RAM
01FFh
512 Bytes RAM
027Fh
0080h
Short Addressing RAM
Zero page
0200h / 0280h
Reserved
00FFh
0100h
(128 Bytes)
0BFFh
0C00h
Stack or
16-bit Addressing RAM
(256 Bytes)
256 Bytes Data EEPROM
0CFFh
01FFh
0200h
0D00h
Reserved
16-bit Addressing
RAM
BFFFh
027Fh
C000h
C000h
16K Bytes
E000h
8K Bytes
Program
Memory
Program
Memory
16 KBytes
8 KBytes
FFDFh
FFE0h
E000h
FFFFh
Interrupt & Reset Vectors
(see Table 5 on page 34)
FFFFh
13/153
ST72334J/N, ST72314J/N, ST72124J
REGISTER & MEMORY MAP (Cont’d)
Table 2. Hardware Register Map
Register
Label
Reset
Status
Address
Block
Register Name
Remarks
1)
0000h
0001h
0002h
PADR
PADDR
PAOR
Port A Data Register
Port A Data Direction Register
Port A Option Register
00h
R/W
R/W
R/W
Port A
00h
00h
2)
0003h
Reserved Area (1 Byte)
1)
0004h
0005h
0006h
PCDR
PCDDR
PCOR
Port C Data Register
Port C Data Direction Register
Port C Option Register
00h
R/W
R/W
R/W
Port C
Port B
00h
00h
0007h
Reserved Area (1 Byte)
1)
R/W
R/W
0008h
0009h
000Ah
PBDR
PBDDR
PBOR
Port B Data Register
Port B Data Direction Register
Port B Option Register
00h
00h
00h
2)
2)
2)
R/W
000Bh
Reserved Area (1 Byte)
1)
000Ch
000Dh
000Eh
PEDR
PEDDR
PEOR
Port E Data Register
Port E Data Direction Register
Port E Option Register
00h
R/W
R/W
R/W
Port E
Port D
Port F
00h
00h
000Fh
Reserved Area (1 Byte)
1)
0010h
0011h
0012h
PDDR
PDDDR
PDOR
Port D Data Register
Port D Data Direction Register
Port D Option Register
00h
R/W
R/W
R/W
00h
00h
0013h
Reserved Area (1 Byte)
1)
0014h
0015h
0016h
PFDR
PFDDR
PFOR
Port F Data Register
Port F Data Direction Register
Port F Option Register
00h
R/W
R/W
R/W
00h
00h
0017h
to
001Fh
Reserved Area (9 Bytes)
Miscellaneous Register 1
0020h
MISCR1
00h
R/W
0021h
0022h
0023h
SPIDR
SPICR
SPISR
SPI Data I/O Register
SPI Control Register
SPI Status Register
xxh
0xh
00h
R/W
R/W
Read Only
SPI
0024h
to
Reserved Area (5 Bytes)
0028h
0029h
MCC
MCCSR
Main Clock Control / Status Register
01h
R/W
14/153
ST72334J/N, ST72314J/N, ST72124J
Register
Label
Reset
Status
Address
Block
Register Name
Remarks
002Ah
002Bh
002Ch
WATCHDOG WDGCR
CRSR
Watchdog Control Register
7Fh
R/W
Clock, Reset, Supply Control / Status Register 000x 000x R/W
Data-EEPROM EECSR
Data-EEPROM Control/Status Register
Reserved Area (4 Bytes)
00h
R/W
002Dh
0030h
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
TACR2
TACR1
TASR
TAIC1HR
TAIC1LR
TAOC1HR
TAOC1LR
TACHR
TACLR
TAACHR
TAACLR
TAIC2HR
TAIC2LR
TAOC2HR
TAOC2LR
Timer A Control Register 2
Timer A Control Register 1
Timer A Status Register
Timer A Input Capture 1 High Register
Timer A Input Capture 1 Low Register
Timer A Output Compare 1 High Register
Timer A Output Compare 1 Low Register
Timer A Counter High Register
00h
00h
xxh
xxh
xxh
80h
00h
FFh
FCh
FFh
FCh
xxh
xxh
80h
00h
R/W
R/W
Read Only
Read Only
Read Only
R/W
R/W
TIMER A
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Timer A Counter Low Register
Timer A Alternate Counter High Register
Timer A Alternate Counter Low Register
Timer A Input Capture 2 High Register
Timer A Input Capture 2 Low Register
Timer A Output Compare 2 High Register
Timer A Output Compare 2 Low Register
3)
3)
3)
R/W
R/W
3)
0040h
MISCR2
Miscellaneous Register 2
00h
R/W
0041h
0042h
0043h
0044h
0045h
0046h
0047h
0048h
0049h
004Ah
004Bh
004Ch
004Dh
004Eh
004Fh
TBCR2
TBCR1
TBSR
TBIC1HR
TBIC1LR
TBOC1HR
TBOC1LR
TBCHR
Timer B Control Register 2
Timer B Control Register 1
Timer B Status Register
Timer B Input Capture 1 High Register
Timer B Input Capture 1 Low Register
Timer B Output Compare 1 High Register
Timer B Output Compare 1 Low Register
Timer B Counter High Register
00h
00h
xxh
xxh
xxh
80h
00h
FFh
FCh
FFh
FCh
xxh
xxh
80h
00h
R/W
R/W
Read Only
Read Only
Read Only
R/W
R/W
TIMER B
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
R/W
TBCLR
Timer B Counter Low Register
TBACHR
TBACLR
TBIC2HR
TBIC2LR
TBOC2HR
TBOC2LR
Timer B Alternate Counter High Register
Timer B Alternate Counter Low Register
Timer B Input Capture 2 High Register
Timer B Input Capture 2 Low Register
Timer B Output Compare 2 High Register
Timer B Output Compare 2 Low Register
R/W
0050h
0051h
0052h
0053h
0054h
0055h
0056h
0057h
SCISR
SCIDR
SCIBRR
SCICR1
SCICR2
SCIERPR
SCI Status Register
SCI Data Register
SCI Baud Rate Register
SCI Control Register 1
SCI Control Register 2
SCI Extended Receive Prescaler Register
Reserved area
SCI Extended Transmit Prescaler Register
C0h
xxh
Read Only
R/W
00xx xxxx R/W
xxh
00h
00h
---
R/W
R/W
R/W
SCI
SCIETPR
00h
R/W
15/153
ST72334J/N, ST72314J/N, ST72124J
Register
Label
Reset
Status
Address
Block
Register Name
Remarks
0058h
006Fh
Reserved Area (24 Bytes)
0070h
0071h
ADCDR
ADCCSR
Data Register
Control/Status Register
xxh
00h
Read Only
R/W
ADC
0072h
to
Reserved Area (14 Bytes)
007Fh
Legend: x=undefined, R/W=read/write
Notes:
1. The contents of the I/O port DR registers are readable only in output configuration. In input configura-
tion, the values of the I/O pins are returned instead of the DR register contents.
2. The bits corresponding to unavailable pins are forced to 1 by hardware, affecting accordingly the reset
status value. These bits must always keep their reset value.
3. External pin not available.
16/153
ST72334J/N, ST72314J/N, ST72124J
5 FLASH PROGRAM MEMORY
5.1 INTRODUCTION
This mode needs five signals (plus the V signal
if necessary) to be connected to the programming
tool. This signals are:
DD
FLASH devices have a single voltage non-volatile
FLASH memory that may be programmed in-situ
(or plugged in a programming tool) on a byte-by-
byte basis.
– RESET: device reset
– V : device ground power supply
SS
– ISPCLK: ISP output serial clock pin
– ISPDATA: ISP input serial data pin
5.2 MAIN FEATURES
– ISPSEL: Remote ISP mode selection. This pin
must be connected to V on the application
■ Remote In-Situ Programming (ISP) mode
■ Up to 16 bytes programmed in the same cycle
■ MTP memory (Multiple Time Programmable)
■ Read-out memory protection against piracy
SS
board through a pull-down resistor.
If any of these pins are used for other purposes on
the application, a serial resistor has to be imple-
mented to avoid a conflict if the other device forces
the signal level.
5.3 STRUCTURAL ORGANISATION
Figure 6 shows a typical hardware interface to a
standard ST7 programming tool. For more details
on the pin locations, refer to the device pinout de-
scription.
The FLASH program memory is organised in a
single 8-bit wide memory block which can be used
for storing both code and data constants.
Figure 6. Typical Remote ISP Interface
The FLASH program memory is mapped in the up-
per part of the ST7 addressing space and includes
the reset and interrupt user vector area .
HE10 CONNECTOR TYPE
TO PROGRAMMING TOOL
XTAL
5.4 IN-SITU PROGRAMMING (ISP) MODE
1
C
C
L1
L0
The FLASH program memory can be programmed
using Remote ISP mode. This ISP mode allows
the contents of the ST7 program memory to be up-
dated using a standard ST7 programming tools af-
ter the device is mounted on the application board.
This feature can be implemented with a minimum
number of added components and board area im-
pact.
ISPSEL
10KΩ
V
SS
RESET
ISPCLK
An example Remote ISP hardware interface to the
standard ST7 programming tool is described be-
low. For more details on ISP programming, refer to
the ST7 Programming Specification.
ST7
ISPDATA
47KΩ
Remote ISP Overview
The Remote ISP mode is initiated by a specific se-
quence on the dedicated ISPSEL pin.
APPLICATION
The Remote ISP is performed in three steps:
– Selection of the RAM execution mode
– Download of Remote ISP code in RAM
5.5 MEMORY READ-OUT PROTECTION
The read-out protection is enabled through an op-
tion bit.
– Execution of Remote ISP code in RAM to pro-
gram the user program into the FLASH
For FLASH devices, when this option is selected,
the program and data stored in the FLASH memo-
ry are protected against read-out piracy (including
a re-write protection). When this protection option
is removed the entire FLASH program memory is
first automatically erased. However, the E PROM
data memory (when available) can be protected
Remote ISP hardware configuration
In Remote ISP mode, the ST7 has to be supplied
2
with power (V and V ) and a clock signal (os-
DD
SS
cillator and application crystal circuit for example).
only with ROM devices.
17/153
ST72334J/N, ST72314J/N, ST72124J
6 DATA EEPROM
6.1 INTRODUCTION
6.2 MAIN FEATURES
The Electrically Erasable Programmable Read
Only Memory can be used as a non volatile back-
up for storing data. Using the EEPROM requires a
basic access protocol described in this chapter.
■ Up to 16 Bytes programmed in the same cycle
■ EEPROM mono-voltage (charge pump)
■ Chained erase and programming cycles
■ Internal control of the global programming cycle
duration
■ End of programming cycle interrupt flag
■ WAIT mode management
Figure 7. EEPROM Block Diagram
FALLING
EDGE
DETECTOR
EEPROM INTERRUPT
HIGH VOLTAGE
PUMP
RESERVED
EEPROM
EECSR
0
0
0
0
0
IE LAT PGM
EEPROM
ROW
ADDRESS
DECODER
4
MEMORY MATRIX
(1 ROW = 16 x 8 BITS)
DECODER
128
128
DATA
MULTIPLEXER
16 x 8 BITS
4
4
DATA LATCHES
ADDRESS BUS
DATA BUS
18/153
ST72334J/N, ST72314J/N, ST72124J
DATA EEPROM (Cont’d)
6.3 MEMORY ACCESS
When PGM bit is set by the software, all the previ-
ous bytes written in the data latches (up to 16) are
programmed in the EEPROM cells. The effective
high address (row) is determined by the last EEP-
ROM write sequence. To avoid wrong program-
ming, the user must take care that all the bytes
written between two programming sequences
have the same high address: only the four Least
Significant Bits of the address can change.
The Data EEPROM memory read/write access
modes are controlled by the LAT bit of the EEP-
ROM Control/Status register (EECSR). The flow-
chart in Figure 8 describes these different memory
access modes.
Read Operation (LAT=0)
The EEPROM can be read as a normal ROM loca-
tion when the LAT bit of the EECSR register is
cleared. In a read cycle, the byte to be accessed is
put on the data bus in less than 1 CPU clock cycle.
This means that reading data from EEPROM
takes the same time as reading data from
EPROM, but this memory cannot be used to exe-
cute machine code.
At the end of the programming cycle, the PGM and
LAT bits are cleared simultaneously, and an inter-
rupt is generated if the IE bit is set. The Data EEP-
ROM interrupt request is cleared by hardware
when the Data EEPROM interrupt vector is
fetched.
Note: Care should be taken during the program-
ming cycle. Writing to the same memory location
will over-program the memory (logical AND be-
tween the two write access data result) because
the data latches are only cleared at the end of the
programming cycle and by the falling edge of LAT
bit.
Write Operation (LAT=1)
To access the write mode, the LAT bit has to be
set by software (the PGM bit remains cleared).
When a write access to the EEPROM area occurs,
the value is latched inside the 16 data latches ac-
cording to its address.
It is not possible to read the latched data.
This note is ilustrated by the Figure 9.
Figure 8. Data EEPROM Programming Flowchart
READ MODE
LAT=0
WRITE MODE
LAT=1
PGM=0
PGM=0
WRITE UP TO 16 BYTES
IN EEPROM AREA
(with the same 11 MSB of the address)
READ BYTES
IN EEPROM AREA
START PROGRAMMING CYCLE
LAT=1
PGM=1 (set by software)
INTERRUPT GENERATION
IF IE=1
0
1
LAT
CLEARED BY HARDWARE
19/153
ST72334J/N, ST72314J/N, ST72124J
DATA EEPROM (Cont’d)
6.4 POWER SAVING MODES
Wait mode
6.5 ACCESS ERROR HANDLING
If a read access occurs while LAT=1, then the data
bus will not be driven.
The DATA EEPROM can enter WAIT mode on ex-
ecution of the WFI instruction of the microcontrol-
ler. The DATA EEPROM will immediately enter
this mode if there is no programming in progress,
otherwise the DATA EEPROM will finish the cycle
and then enter WAIT mode.
If a write access occurs while LAT=0, then the
data on the bus will not be latched.
If a programming cycle is interrupted (by software/
RESET action), the memory data will not be guar-
anteed.
Halt mode
The DATA EEPROM immediatly enters HALT
mode if the microcontroller executes the HALT in-
struction. Therefore the EEPROM will stop the
function in progress, and data may be corrupted.
Figure 9. Data EEPROM Programming Cycle
READ OPERATION NOT POSSIBLE
READ OPERATION POSSIBLE
INTERNAL
PROGRAMMING
VOLTAGE
ERASE CYCLE
WRITE CYCLE
WRITE OF
DATA LATCHES
tPROG
LAT
PGM
EEPROM INTERRUPT
20/153
ST72334J/N, ST72314J/N, ST72124J
DATA EEPROM (Cont’d)
6.6 REGISTER DESCRIPTION
Bit 1 = LAT Latch Access Transfer
This bit is set by software. It is cleared by hard-
ware at the end of the programming cycle. It can
only be cleared by software if PGM bit is cleared.
0: Read mode
CONTROL/STATUS REGISTER (CSR)
Read/Write
Reset Value: 0000 0000 (00h)
1: Write mode
7
0
Bit 0 = PGM Programming control and status
This bit is set by software to begin the programming
cycle. At the end of the programming cycle, this bit
isclearedbyhardware andan interruptisgenerated
if the ITE bit is set.
0
0
0
0
0
IE
LAT
PGM
Bit 7:3 = Reserved, forced by hardware to 0.
0: Programming finished or not yet started
1: Programming cycle is in progress
Bit 2 = IE Interrupt enable
This bitissetand cleared bysoftware. Itenables the
Data EEPROM interrupt capability when the PGM
bit is cleared by hardware. The interrupt request is
automatically cleared when the software enters the
interrupt routine.
Note: if the PGM bit is cleared during the program-
ming cycle, the memory data is not guaranteed
0: Interrupt disabled
1: Interrupt enabled
21/153
ST72334J/N, ST72314J/N, ST72124J
7 DATA EEPROM Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
EECSR
IE
0
RWM
0
PGM
0
002Ch
0
0
0
0
0
Reset Value
7.1 READ-OUT PROTECTION OPTION
The Data EEPROM can be optionally read-out
protected in ST72334 ROM devices (see option
list on page 146). ST72C334 Flash devices do not
have this protection option.
22/153
ST72334J/N, ST72314J/N, ST72124J
8 CENTRAL PROCESSING UNIT
8.1 INTRODUCTION
Accumulator (A)
The Accumulator is an 8-bit general purpose reg-
ister used to hold operands and the results of the
arithmetic and logic calculations and to manipulate
data.
This CPU has a full 8-bit architecture and contains
six internal registers allowing efficient 8-bit data
manipulation.
Index Registers (X and Y)
8.2 MAIN FEATURES
In indexed addressing modes, these 8-bit registers
are used to create either effective addresses or
temporary storage areas for data manipulation.
(The Cross-Assembler generates a precede in-
struction (PRE) to indicate that the following in-
struction refers to the Y register.)
■ 63 basic instructions
■ Fast 8-bit by 8-bit multiply
■ 17 main addressing modes
■ Two 8-bit index registers
■ 16-bit stack pointer
The Y register is not affected by the interrupt auto-
matic procedures (not pushed to and popped from
the stack).
■ Low power modes
■ Maskable hardware interrupts
■ Non-maskable software interrupt
Program Counter (PC)
The program counter is a 16-bit register containing
the address of the next instruction to be executed
by the CPU. It is made of two 8-bit registers PCL
(Program Counter Low which is the LSB) and PCH
(Program Counter High which is the MSB).
8.3 CPU REGISTERS
The 6 CPU registers shown in Figure 10 are not
present in the memory mapping and are accessed
by specific instructions.
Figure 10. CPU Registers
7
0
ACCUMULATOR
RESET VALUE = XXh
7
0
0
X INDEX REGISTER
Y INDEX REGISTER
RESET VALUE = XXh
7
RESET VALUE = XXh
PCL
PCH
7
8
15
0
PROGRAM COUNTER
RESET VALUE = RESET VECTOR @ FFFEh-FFFFh
7
1
0
H I N Z C
X 1 X X X
1
1
1
1
CONDITION CODE REGISTER
RESET VALUE =
8
1
15
7
0
STACK POINTER
RESET VALUE = STACK HIGHER ADDRESS
X = Undefined Value
23/153
ST72334J/N, ST72314J/N, ST72124J
CPU REGISTERS (Cont’d)
CONDITION CODE REGISTER (CC)
Read/Write
Bit 2 = N Negative.
Reset Value: 111x1xxx
This bit is set and cleared by hardware. It is repre-
sentative of the result sign of the last arithmetic,
logical or data manipulation. It is a copy of the 7
7
0
th
bit of the result.
1
1
1
H
I
N
Z
C
0: The result of the last operation is positive or null.
1: The result of the last operation is negative
(i.e. the most significant bit is a logic 1).
The 8-bit Condition Code register contains the in-
terrupt mask and four flags representative of the
result of the instruction just executed. This register
can also be handled by the PUSH and POP in-
structions.
This bit is accessed by the JRMI and JRPL instruc-
tions.
These bits can be individually tested and/or con-
trolled by specific instructions.
Bit 1 = Z Zero.
This bit is set and cleared by hardware. This bit in-
dicates that the result of the last arithmetic, logical
or data manipulation is zero.
0: The result of the last operation is different from
zero.
Bit 4 = H Half carry.
This bit is set by hardware when a carry occurs be-
tween bits 3 and 4 of the ALU during an ADD or
ADC instruction. It is reset by hardware during the
same instructions.
0: No half carry has occurred.
1: A half carry has occurred.
1: The result of the last operation is zero.
This bit is accessed by the JREQ and JRNE test
instructions.
This bit is tested using the JRH or JRNH instruc-
tion. The H bit is useful in BCD arithmetic subrou-
tines.
Bit 0 = C Carry/borrow.
This bit is set and cleared by hardware and soft-
ware. It indicates an overflow or an underflow has
occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.
Bit 3 = I Interrupt mask.
This bit is set by hardware when entering in inter-
rupt or by software to disable all interrupts except
the TRAP software interrupt. This bit is cleared by
software.
This bit is driven by the SCF and RCF instructions
and tested by the JRC and JRNC instructions. It is
also affected by the “bit test and branch”, shift and
rotate instructions.
0: Interrupts are enabled.
1: Interrupts are disabled.
This bit is controlled by the RIM, SIM and IRET in-
structions and is tested by the JRM and JRNM in-
structions.
Note: Interrupts requested while I is set are
latched and can be processed when I is cleared.
By default an interrupt routine is not interruptable
because the I bit is set by hardware at the start of
the routine and reset by the IRET instruction at the
end of the routine. If the I bit is cleared by software
in the interrupt routine, pending interrupts are
serviced regardless of the priority level of the cur-
rent interrupt routine.
24/153
ST72334J/N, ST72314J/N, ST72124J
CENTRAL PROCESSING UNIT (Cont’d)
Stack Pointer (SP)
The least significant byte of the Stack Pointer
(called S) can be directly accessed by a LD in-
struction.
Read/Write
Reset Value: 01 FFh
Note: When the lower limit is exceeded, the Stack
Pointer wraps around to the stack upper limit, with-
out indicating the stack overflow. The previously
stored information is then overwritten and there-
fore lost. The stack also wraps in case of an under-
flow.
15
8
1
0
7
0
0
0
0
0
0
0
The stack is used to save the return address dur-
ing a subroutine call and the CPU context during
an interrupt. The user may also directly manipulate
the stack by means of the PUSH and POP instruc-
tions. In the case of an interrupt, the PCL is stored
at the first location pointed to by the SP. Then the
other registers are stored in the next locations as
shown in Figure 11.
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
The Stack Pointer is a 16-bit register which is al-
ways pointing to the next free location in the stack.
It is then decremented after data has been pushed
onto the stack and incremented before data is
popped from the stack (see Figure 11).
– When an interrupt is received, the SP is decre-
mented and the context is pushed on the stack.
Since the stack is 256 bytes deep, the 8th most
significant bits are forced by hardware. Following
an MCU Reset, or after a Reset Stack Pointer in-
struction (RSP), the Stack Pointer contains its re-
set value (the SP7 to SP0 bits are set) which is the
stack higher address.
– On return from interrupt, the SP is incremented
and the context is popped from the stack.
A subroutine call occupies two locations and an in-
terrupt five locations in the stack area.
Figure 11. Stack Manipulation Example
CALL
Subroutine
RET
or RSP
PUSH Y
POP Y
IRET
Interrupt
Event
@ 0100h
SP
SP
SP
Y
CC
A
CC
A
CC
A
X
X
X
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
SP
SP
PCH
PCL
PCH
PCL
SP
@ 01FFh
Stack Higher Address = 01FFh
0100h
Stack Lower Address =
25/153
ST72334J/N, ST72314J/N, ST72124J
9 SUPPLY, RESET AND CLOCK MANAGEMENT
The ST72334J/N, ST72314J/N and ST72124J mi-
crocontrollers include a range of utility features for
securing the application in critical situations (for
example in case of a power brown-out), and re-
ducing the number of external components. An
overview is shown in Figure 12.
■ Multi-Oscillator (MO)
– 4 Crystal/Ceramic resonator oscillators
– 1 External RC oscillator
– 1 Internal RC oscillator
■ Clock Security System (CSS)
– Clock Filter
– Backup Safe Oscillator
See Section 16 "ELECTRICAL CHARACTERIS-
TICS" on page 107 for more details.
Main Features
■ Supply Manager with main supply low voltage
detection (LVD)
■ Reset Sequence Manager (RSM)
Figure 12. Clock, Reset and Supply Block Diagram
CLOCK SECURITY SYSTEM
(CSS)
MULTI-
OSCILLATOR
(MO)
f
OSC2
OSC1
TO
OSC
CLOCK
FILTER
SAFE
OSC
MAIN CLOCK
CONTROLLER
RESET SEQUENCE
MANAGER
FROM
RESET
WATCHDOG
PERIPHERAL
(RSM)
VDD
VSS
LOW VOLTAGE
DETECTOR
(LVD)
LVD
CSS
WDG
RF
CRSR
0
0
0
RF
0
IE
D
CSS INTERRUPT
26/153
ST72334J/N, ST72314J/N, ST72124J
9.1 LOW VOLTAGE DETECTOR (LVD)
To allow the integration of power management
features in the application, the Low Voltage Detec-
tor function (LVD) generates a static reset when
In these conditions, secure operation is always en-
sured for the application without the need for ex-
ternal reset hardware.
the V
supply voltage is below a V reference
DD
IT-
During a Low Voltage Detector Reset, the RESET
pin is held low, thus permitting the MCU to reset
other devices.
value. This means that it secures the power-up as
well as the power-down keeping the ST7 in reset.
The V reference value for a voltage drop is lower
IT-
Notes:
than the V reference value for power-on in order
1. The LVD allows the device to be used without
any external RESET circuitry.
IT+
to avoid a parasitic reset when the MCU starts run-
ning and sinks current on the supply (hysteresis).
2. Three different reference levels are selectable
through the option byte according to the applica-
tion requirement.
The LVD Reset circuitry generates a reset when
V
is below:
DD
LVD application note
– V when V is rising
IT+
DD
– V when V is falling
The LVD function is illustrated in the Figure 13.
Application software can detect a reset caused by
the LVD by reading the LVDRF bit in the CRSR
register.
IT-
DD
Provided the minimum V value (guaranteed for
DD
This bit is set by hardware when a LVD reset is
generated and cleared by software (writing zero).
the oscillator frequency) is above V , the MCU
IT-
can only be in two modes:
– under full software control
– in static safe reset
Figure 13. Low Voltage Detector vs Reset
V
DD
V
hyst
V
V
IT+
IT-
RESET
27/153
ST72334J/N, ST72314J/N, ST72124J
9.2 RESET SEQUENCE MANAGER (RSM)
9.2.1 Introduction
The 4096 CPU clock cycle delay allows the oscil-
lator to stabilise and ensures that recovery has
taken place from the Reset state.
The reset sequence manager includes three RE-
SET sources as shown in Figure 15:
The RESET vector fetch phase duration is 2 clock
cycles.
■ External RESET source pulse
■ Internal LVD RESET (Low Voltage Detection)
■ Internal WATCHDOG RESET
Figure 14. RESET Sequence Phases
These sources act on the RESET pin and it is al-
ways kept low during the delay phase.
RESET
The RESET service routine vector is fixed at ad-
dresses FFFEh-FFFFh in the ST7 memory map.
INTERNAL RESET
FETCH
DELAY
4096 CLOCK CYCLES
VECTOR
The basic RESET sequence consists of 3 phases
as shown in Figure 14:
■ Delay depending on the RESET source
■ 4096 CPU clock cycle delay
■ RESET vector fetch
Figure 15. Reset Block Diagram
INTERNAL
RESET
V
DD
f
CPU
R
ON
RESET
WATCHDOG RESET
LVD RESET
28/153
ST72334J/N, ST72314J/N, ST72124J
9.2.3 Internal Low Voltage Detection RESET
RESET SEQUENCE MANAGER (Cont’d)
9.2.2 Asynchronous External RESET pin
The RESET pin is both an input and an open-drain
Two different RESET sequences caused by the in-
ternal LVD circuitry can be distinguished:
output with integrated R
weak pull-up resistor.
ON
This pull-up has no fixed value but varies in ac-
cordance with the input voltage. It can be pulled
low by external circuitry to reset the device. See
electrical characteristics section for more details.
■ Power-On RESET
■ Voltage Drop RESET
The device RESET pin acts as an output that is
pulled low when V <V
(rising edge) or
DD
IT+
A RESET signal originating from an external
V
<V (falling edge) as shown in Figure 16.
DD
IT-
source must have a duration of at least t
in
h(RSTL)in
The LVD filters spikes on V larger than t
avoid parasitic resets.
to
g(VDD)
order to be recognized. This detection is asynchro-
nous and therefore the MCU can enter reset state
even in HALT mode.
DD
9.2.4 Internal Watchdog RESET
The RESET pin is an asynchronous signal which
plays a major role in EMS performance. In a noisy
environment, it is recommended to follow the
guidelines mentioned in the electrical characteris-
tics section.
The RESET sequence generated by a internal
Watchdog counter overflow is shown in Figure 16.
Starting from the Watchdog counter underflow, the
device RESET pin acts as an output that is pulled
low during at least t
.
w(RSTL)out
Two RESET sequences can be associated with
this RESET source: short or long external reset
pulse (see Figure 16).
Starting from the external RESET pulse recogni-
tion, the device RESET pin acts as an output that
is pulled low during at least t
.
w(RSTL)out
Figure 16. RESET Sequences
V
DD
V
V
IT+
IT-
LVD
RESET
SHORT EXT.
RESET
LONG EXT.
RESET
WATCHDOG
RESET
RUN
RUN
RUN
RUN
RUN
DELAY
DELAY
DELAY
DELAY
t
w(RSTL)out
t
w(RSTL)out
t
t
h(RSTL)in
h(RSTL)in
EXTERNAL
RESET
SOURCE
RESET PIN
WATCHDOG
RESET
WATCHDOG UNDERFLOW
INTERNAL RESET (4096 TCPU
FETCH VECTOR
)
29/153
ST72334J/N, ST72314J/N, ST72124J
9.3 MULTI-OSCILLATOR (MO)
The main clock of the ST7 can be generated by
four different source types coming from the multi-
oscillator block:
Table 3. ST7 Clock Sources
Hardware Configuration
■ an external source
■ 4 crystal or ceramic resonator oscillators
■ an external RC oscillator
ST7
OSC1
OSC2
■ an internal high frequency RC oscillator
Each oscillator is optimized for a given frequency
range in terms of consumption and is selectable
through the option byte. The associated hardware
configuration are shown in Table 3. Refer to the
electrical characteristics section for more details.
EXTERNAL
SOURCE
External Clock Source
ST7
OSC1
OSC2
In this external clock mode, a clock signal (square,
sinus or triangle) with ~50% duty cycle has to drive
the OSC1 pin while the OSC2 pin is tied to ground.
Crystal/Ceramic Oscillators
This family of oscillators has the advantage of pro-
ducing a very accurate rate on the main clock of
the ST7. The selection within a list of 4 oscillators
with different frequency ranges has to be done by
option byte in order to reduce consumption. In this
mode of the multi-oscillator, the resonator and the
load capacitors have to be placed as close as pos-
sible to the oscillator pins in order to minimize out-
put distortion and start-up stabilization time. The
loading capacitance values must be adjusted ac-
cording to the selected oscillator.
C
C
L2
L1
LOAD
CAPACITORS
ST7
OSC1
OSC2
R
C
EX
EX
These oscillators are not stopped during the
RESET phase to avoid losing time in the oscillator
start-up phase.
External RC Oscillator
ST7
This oscillator allows a low cost solution for the
main clock of the ST7 using only an external resis-
tor and an external capacitor. The frequency of the
external RC oscillator (in the range of some MHz.)
is fixed by the resistor and the capacitor values.
Consequently in this MO mode, the accuracy of
the clock is directly linked to the accuracy of the
discrete components. The corresponding formula
OSC1
OSC2
is f
=4/(R
C
)
OSC
EX EX
Internal RC Oscillator
The internal RC oscillator mode is based on the
same principle as the external RC oscillator includ-
ing the resistance and the capacitance of the de-
vice. This mode is the most cost effective one with
the drawback of a lower frequency accuracy. Its
frequency is in the range of several MHz.
In this mode, the two oscillator pins have to be tied
to ground.
30/153
ST72334J/N, ST72314J/N, ST72124J
9.4 CLOCK SECURITY SYSTEM (CSS)
The Clock Security System (CSS) protects the
ST7 against main clock problems. To allow the in-
tegration of the security features in the applica-
tions, it is based on a clock filter control and an In-
ternal safe oscillator. The CSS can be enabled or
disabled by option byte.
Limitation detection
The automatic safe oscillator selection is notified
by hardware setting the CSSD bit of the CRSR
register. An interrupt can be generated if the CS-
SIE bit has been previously set.
These two bits are described in the CRSR register
description.
9.4.1 Clock Filter Control
9.4.3 Low Power Modes
The clock filter is based on a clock frequency limi-
tation function.
Mode
WAIT
Description
This filter function is able to detect and filter high
frequency spikes on the ST7 main clock.
No effect on CSS. CSS interrupt cause the
device to exit from Wait mode.
If the oscillator is not working properly (e.g. work-
ing at a harmonic frequency of the resonator), the
current active oscillator clock can be totally fil-
tered, and then no clock signal is available for the
ST7 from this oscillator anymore. If the original
clock source recovers, the filtering is stopped au-
tomatically and the oscillator supplies the ST7
clock.
The CRSR register is frozen. The CSS (in-
cluding the safe oscillator) is disabled until
HALT mode is exited. The previous CSS
configuration resumes when the MCU is
woken up by an interrupt with “exit from
HALT mode” capability or from the counter
reset value when the MCU is woken up by a
RESET.
HALT
9.4.2 Safe Oscillator Control
9.4.4 Interrupts
The safe oscillator of the CSS block is a low fre-
quency back-up clock source (see Figure 17).
The CSS interrupt event generates an interrupt if
the corresponding Enable Control Bit (CSSIE) is
set and the interrupt mask in the CC register is re-
set (RIM instruction).
If the clock signal disappears (due to a broken or
disconnected resonator...) during a safe oscillator
period, the safe oscillator delivers a low frequency
clock signal which allows the ST7 to perform some
rescue operations.
Enable Exit
Control from
Exit
Event
Flag
Interrupt Event
from
1)
Bit
Wait Halt
Automatically, the ST7 clock source switches back
from the safe oscillator if the original clock source
recovers.
CSS event detection
(safe oscillator acti- CSSD CSSIE
vated as main clock)
Yes
No
Note 1: This interrupt allows to exit from active-halt
mode if this mode is available in the MCU.
Figure 17. Clock Filter Function and Safe Oscillator Function
f
f
/2
OSC
CPU
f
f
/2
OSC
SFOSC
CPU
f
31/153
ST72334J/N, ST72314J/N, ST72124J
9.5 SUPPLY, RESET AND CLOCK REGISTER DESCRIPTION
Read/Write
Bit 1 = CSSD Clock security system detection
This bit indicates that the safe oscillator of the
clock security system block has been selected by
hardware due to a disturbance on the main clock
Reset Value: 000x 000x (xxh)
7
0
signal (f
). It is set by hardware and cleared by
OSC
reading the CRSR register when the original oscil-
lator recovers.
LVD
RF
CSS CSS WDG
0
0
0
0
IE
D
RF
0: Safe oscillator is not active
1: Safe oscillator has been activated
When the CSS is disabled by option byte, the
CSSD bit value is forced to 0.
Bit 7:5 = Reserved, always read as 0.
Bit 4 = LVDRF LVD reset flag
This bit indicates that the last RESET was gener-
ated by the LVD block. It is set by hardware (LVD
reset) and cleared by software (writing zero). See
WDGRF flag description for more details. When
the LVD is disabled by option byte, the LVDRF bit
value is undefined.
Bit 0 = WDGRF Watchdog reset flag
This bit indicates that the last RESET was gener-
ated by the watchdog peripheral. It is set by hard-
ware (Watchdog RESET) and cleared by software
(writing zero) or an LVD RESET (to ensure a sta-
ble cleared state of the WDGRF flag when the
CPU starts).
Combined with the LVDRF flag information, the
flag description is given by the following table.
Bit 3 = Reserved, always read as 0.
RESET Sources
External RESET pin
LVDRF WDGRF
Bit 2 = CSSIE Clock security syst interrupt enable
.
0
0
1
0
1
X
This bit enables the interrupt when a disturbance
is detected by the clock security system (CSSD bit
set). It is set and cleared by software.
Watchdog
LVD
0: Clock security system interrupt disabled
1: Clock security system interrupt enabled
Refer to Table 5, “Interrupt mapping,” on page 34
for more details on the CSS interrupt vector. When
the CSS is disabled by option byte, the CSSIE bit
has no effect.
Application notes
The LVDRF flag is not cleared when another RE-
SET type occurs (external or watchdog), the
LVDRF flag remains set to keep trace of the origi-
nal failure.
In this case, a watchdog reset can be detected by
software while an external reset can not.
Table 4. Clock, Reset and Supply Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
CRSR
Reset Value
LVDRF
x
CFIE
0
CSSD
0
WDGRF
x
002Bh
0
0
0
0
32/153
ST72334J/N, ST72314J/N, ST72124J
10 INTERRUPTS
The ST7 core may be interrupted by one of two dif-
ferent methods: maskable hardware interrupts as
listed in the Interrupt Mapping Table and a non-
maskable software interrupt (TRAP). The Interrupt
processing flowchart is shown in Figure 18.
The maskable interrupts must be enabled by
clearing the I bit in order to be serviced. However,
disabled interrupts may be latched and processed
when they are enabled (see external interrupts
subsection).
It will be serviced according to the flowchart on
Figure 18.
10.2 EXTERNAL INTERRUPTS
External interrupt vectors can be loaded into the
PC register if the corresponding external interrupt
occurred and if the I bit is cleared. These interrupts
allow the processor to leave the Halt low power
mode.
Note: After reset, all interrupts are disabled.
When an interrupt has to be serviced:
The external interrupt polarity is selected through
the miscellaneous register or interrupt register (if
available).
– Normal processing is suspended at the end of
the current instruction execution.
An external interrupt triggered on edge will be
latched and the interrupt request automatically
cleared upon entering the interrupt service routine.
– The PC, X, A and CC registers are saved onto
the stack.
If several input pins, connected to the same inter-
rupt vector, are configured as interrupts, their sig-
nals are logically NANDed before entering the
edge/level detection block.
– The I bit of the CC register is set to prevent addi-
tional interrupts.
– The PC is then loaded with the interrupt vector of
the interrupt to service and the first instruction of
the interrupt service routine is fetched (refer to
the Interrupt Mapping Table for vector address-
es).
Caution: The type of sensitivity defined in the Mis-
cellaneous or Interrupt register (if available) ap-
plies to the ei source. In case of a NANDed source
(as described on the I/O ports section), a low level
on an I/O pin configured as input with interrupt,
masks the interrupt request even in case of rising-
edge sensitivity.
The interrupt service routine should finish with the
IRET instruction which causes the contents of the
saved registers to be recovered from the stack.
Note: As a consequence of the IRET instruction,
the I bit will be cleared and the main program will
resume.
10.3 PERIPHERAL INTERRUPTS
Different peripheral interrupt flags in the status
register are able to cause an interrupt when they
are active if both:
Priority Management
By default, a servicing interrupt cannot be inter-
rupted because the I bit is set by hardware enter-
ing in interrupt routine.
– The I bit of the CC register is cleared.
– The corresponding enable bit is set in the control
register.
In the case when several interrupts are simultane-
ously pending, an hardware priority defines which
one will be serviced first (see the Interrupt Map-
ping Table).
If any of these two conditions is false, the interrupt
is latched and thus remains pending.
Clearing an interrupt request is done by:
Interrupts and Low Power Mode
– Writing “0” to the corresponding bit in the status
register or
All interrupts allow the processor to leave the
WAIT low power mode. Only external and specifi-
cally mentioned interrupts allow the processor to
leave the HALT low power mode (refer to the “Exit
from HALT“ column in the Interrupt Mapping Ta-
ble).
– Access to the status register while the flag is set
followed by a read or write of an associated reg-
ister.
Note: the clearing sequence resets the internal
latch. A pending interrupt (i.e. waiting for being en-
abled) will therefore be lost if the clear sequence is
executed.
10.1
NON
MASKABLE
SOFTWARE
INTERRUPT
This interrupt is entered when the TRAP instruc-
tion is executed regardless of the state of the I bit.
33/153
ST72334J/N, ST72314J/N, ST72124J
INTERRUPTS (Cont’d)
Figure 18. Interrupt Processing Flowchart
FROM RESET
N
I BIT SET?
Y
N
INTERRUPT
PENDING?
Y
FETCH NEXT INSTRUCTION
N
IRET?
STACK PC, X, A, CC
SET I BIT
Y
LOAD PC FROM INTERRUPT VECTOR
EXECUTE INSTRUCTION
RESTORE PC, X, A, CC FROM STACK
THIS CLEARS I BIT BY DEFAULT
Table 5. Interrupt mapping
Exit
Source
Block
Register Priority
Address
Vector
N°
Description
from
Label
Order
1)
HALT
RESET
TRAP
Reset
Highest
Priority
yes
FFFEh-FFFFh
FFFCh-FFFDh
FFFAh-FFFBh
N/A
Software Interrupt
Not used
no
0
1
MCC/RTC
CSS
Main Clock Controller Time Base Interrupt
or Clock Security System Interrupt
MCCSR
CRSR
yes
FFF8h-FFF9h
2
3
ei0
ei1
ei2
ei3
External Interrupt Port A3..0
External Interrupt Port F2..0
External Interrupt Port B3..0
External Interrupt Port B7..4
Not used
FFF6h-FFF7h
FFF4h-FFF5h
FFF2h-FFF3h
FFF0h-FFF1h
FFEEh-FFEFh
FFECh-FFEDh
FFEAh-FFEBh
FFE8h-FFE9h
FFE6h-FFE7h
FFE4h-FFE5h
FFE2h-FFE3h
FFE0h-FFE1h
N/A
4
5
6
7
SPI
SPI Peripheral Interrupts
TIMER A Peripheral Interrupts
TIMER B Peripheral Interrupts
SCI Peripheral Interrupts
SPISR
TASR
no
8
TIMER A
TIMER B
SCI
9
TBSR
10
SCISR
EECSR
11 Data-EEPROM Data EEPROM Interrupt
12
Lowest
Priority
Not used
13
Note 1. Valid for HALT and ACTIVE-HALT modes except for the MCC/RTC or CSS interrupt source which exits from
ACTIVE-HALT mode only.
34/153
ST72334J/N, ST72314J/N, ST72124J
11 POWER SAVING MODES
11.1 INTRODUCTION
11.2 SLOW MODE
To give a large measure of flexibility to the applica-
tion in terms of power consumption, four main
power saving modes are implemented in the ST7
(see Figure 19): SLOW, WAIT (SLOW WAIT), AC-
TIVE HALT and HALT.
This mode has two targets:
– To reduce power consumption by decreasing the
internal clock in the device,
– To adapt the internal clock frequency (f
the available supply voltage.
) to
CPU
After a RESET the normal operating mode is se-
lected by default (RUN mode). This mode drives
the device (CPU and embedded peripherals) by
means of a master clock which is based on the
SLOW mode is controlled by three bits in the
MISCR1 register: the SMS bit which enables or
disables Slow mode and two CPx bits which select
the internal slow frequency (f
).
CPU
main oscillator frequency divided by 2 (f
).
CPU
In this mode, the oscillator frequency can be divid-
ed by 4, 8, 16 or 32 instead of 2 in normal operat-
ing mode. The CPU and peripherals are clocked at
this lower frequency.
From RUN mode, the different power saving
modes may be selected by setting the relevant
register bits or by calling the specific ST7 software
instruction whose action depends on the oscillator
status.
Note: SLOW-WAIT mode is activated when enter-
ing the WAIT mode while the device is already in
SLOW mode.
Figure 19. Power Saving Mode Transitions
Figure 20. SLOW Mode Clock Transitions
High
f
/4
f
/8
f
/2
OSC
OSC
OSC
RUN
f
CPU
SLOW
WAIT
f
/2
OSC
00
01
CP1:0
SMS
SLOW WAIT
ACTIVE HALT
HALT
NORMAL RUN MODE
REQUEST
NEW SLOW
FREQUENCY
REQUEST
Low
POWER CONSUMPTION
35/153
ST72334J/N, ST72314J/N, ST72124J
POWER SAVING MODES (Cont’d)
11.3 WAIT MODE
Figure 21. WAIT Mode Flow-chart
WAIT mode places the MCU in a low power con-
sumption mode by stopping the CPU.
This power saving mode is selected by calling the
‘WFI’ instruction.
OSCILLATOR
PERIPHERALS
CPU
I BIT
ON
ON
OFF
0
WFI INSTRUCTION
All peripherals remain active. During WAIT mode,
the I bit of the CC register is cleared, to enable all
interrupts. All other registers and memory remain
unchanged. The MCU remains in WAIT mode until
an interrupt or RESET occurs, whereupon the Pro-
gram Counter branches to the starting address of
the interrupt or Reset service routine.
N
RESET
Y
N
INTERRUPT
The MCU will remain in WAIT mode until a Reset
or an Interrupt occurs, causing it to wake up.
Y
OSCILLATOR
PERIPHERALS
ON
OFF
ON
0
Refer to Figure 21.
CPU
I BIT
4096 CPU CLOCK CYCLE
DELAY
OSCILLATOR
PERIPHERALS
CPU
ON
ON
ON
1)
I BIT
X
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Note:
1. Before servicing an interrupt, the CC register is
pushed on the stack. The I bit of the CC register is
set during the interrupt routine and cleared when
the CC register is popped.
36/153
ST72334J/N, ST72314J/N, ST72124J
Figure 22. ACTIVE-HALT Timing Overview
POWER SAVING MODES (Cont’d)
11.4 ACTIVE-HALT AND HALT MODES
ACTIVE-HALT and HALT modes are the two low-
est power consumption modes of the MCU. They
are both entered by executing the ‘HALT’ instruc-
tion. The decision to enter either in ACTIVE-HALT
or HALT mode is given by the MCC/RTC interrupt
enable flag (OIE bit in MCCSR register).
ACTIVE
HALT
4096 CPU CYCLE
RUN
RUN
DELAY
RESET
OR
HALT
INSTRUCTION
[MCCSR.OIE=1]
INTERRUPT
FETCH
VECTOR
MCCSR Power Saving Mode entered when HALT
OIE bit
instruction is executed
HALT mode
ACTIVE-HALT mode
Figure 23. ACTIVE-HALT Mode Flow-chart
0
1
OSCILLATOR
PERIPHERALS 1)
CPU
ON
OFF
OFF
0
HALT INSTRUCTION
(MCCSR.OIE=1)
11.4.1 ACTIVE-HALT MODE
I BIT
ACTIVE-HALT mode is the lowest power con-
sumption mode of the MCU with a real time clock
available. It is entered by executing the ‘HALT’ in-
struction when the OIE bit of the Main Clock Con-
troller Status register (MCCSR) is set (see Section
14.2 "MAIN CLOCK CONTROLLER WITH REAL
TIME CLOCK TIMER (MCC/RTC)" on page 52 for
more details on the MCCSR register).
N
RESET
Y
N
INTERRUPT 2)
The MCU can exit ACTIVE-HALT mode on recep-
tion of either an MCC/RTC interrupt, a specific in-
terrupt (see Table 5, “Interrupt mapping,” on
page 34) or a RESET. When exiting ACTIVE-
HALT mode by means of a RESET or an interrupt,
a 4096 CPU cycle delay occurs. After the start up
delay, the CPU resumes operation by servicing
the interrupt or by fetching the reset vector which
woke it up (see Figure 23).
When entering ACTIVE-HALT mode, the I bit in
the CC register is cleared to enable interrupts.
Therefore, if an interrupt is pending, the MCU
wakes up immediately.
OSCILLATOR
PERIPHERALS 1)
CPU
Y
ON
OFF
ON
I BIT
X 3)
4096 CPU CLOCK CYCLE
DELAY
OSCILLATOR
PERIPHERALS
CPU
ON
ON
ON
X 3)
I BITS
In ACTIVE-HALT mode, only the main oscillator
and its associated counter (MCC/RTC) are run-
ning to keep a wake-up time base. All other periph-
erals are not clocked except those which get their
clock supply from another clock generator (such
as external or auxiliary oscillator).
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Notes:
1. Peripheral clocked with an external clock source
can still be active.
The safeguard against staying locked in ACTIVE-
HALT mode is provided by the oscillator interrupt.
2. Only the MCC/RTC interrupt and some specific
interrupts can exit the MCU from ACTIVE-HALT
mode (such as external interrupt). Refer to
Table 5, “Interrupt mapping,” on page 34 for more
details.
Note: As soon as the interrupt capability of one of
the oscillators is selected (MCCSR.OIE bit set),
entering ACTIVE-HALT mode while the Watchdog
is active does not generate a RESET.
This means that the device cannot spend more
than a defined delay in this power saving mode.
3. Before servicing an interrupt, the CC register is
pushed on the stack. The I bit of the CC register is
set during the interrupt routine and cleared when
the CC register is popped.
37/153
ST72334J/N, ST72314J/N, ST72124J
POWER SAVING MODES (Cont’d)
11.4.2 HALT MODE
Figure 25. HALT Mode Flow-chart
The HALT mode is the lowest power consumption
mode of the MCU. It is entered by executing the
‘HALT’ instruction when the OIE bit of the Main
Clock Controller Status register (MCCSR) is
cleared (see Section 14.2 "MAIN CLOCK CON-
TROLLER WITH REAL TIME CLOCK TIMER
(MCC/RTC)" on page 52 for more details on the
MCCSR register).
HALT INSTRUCTION
(MCCSR.OIE=0)
ENABLE
WATCHDOG
0
DISABLE
WDGHALT 1)
1
The MCU can exit HALT mode on reception of ei-
ther a specific interrupt (see Table 5, “Interrupt
mapping,” on page 34) or a RESET. When exiting
HALT mode by means of a RESET or an interrupt,
the oscillator is immediately turned on and the
4096 CPU cycle delay is used to stabilize the os-
cillator. After the start up delay, the CPU resumes
operation by servicing the interrupt or by fetching
the reset vector which woke it up (see Figure 25).
When entering HALT mode, the I bit in the CC reg-
ister is forced to 0 to enable interrupts. Therefore,
if an interrupt is pending, the MCU wakes immedi-
ately.
WATCHDOG
RESET
OSCILLATOR
OFF
PERIPHERALS 2)
OFF
OFF
0
CPU
I BIT
N
RESET
Y
N
INTERRUPT 3)
OSCILLATOR
PERIPHERALS
CPU
Y
ON
OFF
ON
In HALT mode, the main oscillator is turned off
causing all internal processing to be stopped, in-
cluding the operation of the on-chip peripherals.
All peripherals are not clocked except the ones
which get their clock supply from another clock
generator (such as an external or auxiliary oscilla-
tor).
I BIT
X 4)
4096 CPU CLOCK CYCLE
DELAY
The compatibility of Watchdog operation with
HALT mode is configured by the “WDGHALT” op-
tion bit of the option byte. The HALT instruction
when executed while the Watchdog system is en-
abled, can generate a Watchdog RESET (see
Section 18.1 on page 144 for more details).
OSCILLATOR
PERIPHERALS
CPU
ON
ON
ON
X 4)
I BITS
Figure 24. HALT Timing Overview
FETCH RESET VECTOR
OR SERVICE INTERRUPT
4096 CPU CYCLE
RUN
HALT
RUN
Notes:
DELAY
1. WDGHALT is an option bit. See option byte sec-
RESET
OR
INTERRUPT
tion for more details.
2. Peripheral clocked with an external clock source
can still be active.
HALT
INSTRUCTION
[MCCSR.OIE=0]
FETCH
VECTOR
3. Only some specific interrupts can exit the MCU
from HALT mode (such as external interrupt). Re-
fer to Table 5, “Interrupt mapping,” on page 34 for
more details.
4. Before servicing an interrupt, the CC register is
pushed on the stack. The I bit of the CC register is
set during the interrupt routine and cleared when
the CC register is popped.
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ST72334J/N, ST72314J/N, ST72124J
12 I/O PORTS
12.1 INTRODUCTION
programmable using the sensitivity bits in the Mis-
cellaneous register.
The I/O ports offer different functional modes:
– transfer of data through digital inputs and outputs
Each external interrupt vector is linked to a dedi-
cated group of I/O port pins (see pinout description
and interrupt section). If several input pins are se-
lected simultaneously as interrupt source, these
are logically NANDed. For this reason if one of the
interrupt pins is tied low, it masks the other ones.
and for specific pins:
– external interrupt generation
– alternate signal input/output for the on-chip pe-
ripherals.
An I/O port contains up to 8 pins. Each pin can be
programmed independently as digital input (with or
without interrupt generation) or digital output.
In case of a floating input with interrupt configura-
tion, special care must be taken when changing
the configuration (see Figure 27).
The external interrupts are hardware interrupts,
which means that the request latch (not accessible
directly by the application) is automatically cleared
when the corresponding interrupt vector is
fetched. To clear an unwanted pending interrupt
by software, the sensitivity bits in the Miscellane-
ous register must be modified.
12.2 FUNCTIONAL DESCRIPTION
Each port has 2 main registers:
– Data Register (DR)
– Data Direction Register (DDR)
and one optional register:
– Option Register (OR)
12.2.2 Output Modes
The output configuration is selected by setting the
corresponding DDR register bit. In this case, writ-
ing the DR register applies this digital value to the
I/O pin through the latch. Then reading the DR reg-
ister returns the previously stored value.
Each I/O pin may be programmed using the corre-
sponding register bits in the DDR and OR regis-
ters: bit X corresponding to pin X of the port. The
same correspondence is used for the DR register.
The following description takes into account the
OR register, (for specific ports which do not pro-
vide this register refer to the I/O Port Implementa-
tion section). The generic I/O block diagram is
shown in Figure 26
Two different output modes can be selected by
software through the OR register: Output push-pull
and open-drain.
DR register value and output pin status:
12.2.1 Input Modes
DR
0
Push-pull
Open-drain
Vss
V
The input configuration is selected by clearing the
corresponding DDR register bit.
SS
1
V
Floating
DD
In this case, reading the DR register returns the
digital value applied to the external I/O pin.
12.2.3 Alternate Functions
When an on-chip peripheral is configured to use a
pin, the alternate function is automatically select-
ed. This alternate function takes priority over the
standard I/O programming.
Different input modes can be selected by software
through the OR register.
Notes:
1. Writing the DR register modifies the latch value
but does not affect the pin status.
When the signal is coming from an on-chip periph-
eral, the I/O pin is automatically configured in out-
put mode (push-pull or open drain according to the
peripheral).
2. When switching from input to output mode, the
DR register has to be written first to drive the cor-
rect level on the pin as soon as the port is config-
ured as an output.
When the signal is going to an on-chip peripheral,
the I/O pin must be configured in input mode. In
this case, the pin state is also digitally readable by
addressing the DR register.
3. Do not use read/modify/write instructions (BSET
or BRES) to modify the DR register
External interrupt function
When an I/O is configured as Input with Interrupt,
an event on this I/O can generate an external inter-
rupt request to the CPU.
Note: Input pull-up configuration can cause unex-
pected value at the input of the alternate peripheral
input. When an on-chip peripheral use a pin as in-
put and output, this pin has to be configured in in-
put floating mode.
Each pin can independently generate an interrupt
request. The interrupt sensitivity is independently
39/153
ST72334J/N, ST72314J/N, ST72124J
I/O PORTS (Cont’d)
Figure 26. I/O Port General Block Diagram
ALTERNATE
OUTPUT
1
0
REGISTER
ACCESS
P-BUFFER
(see table below)
V
DD
ALTERNATE
ENABLE
PULL-UP
(see table below)
DR
DDR
OR
V
DD
PULL-UP
CONFIGURATION
PAD
If implemented
OR SEL
DDR SEL
DR SEL
N-BUFFER
DIODES
(see table below)
ANALOG
INPUT
CMOS
SCHMITT
TRIGGER
1
0
ALTERNATE
INPUT
EXTERNAL
INTERRUPT
SOURCE (ei )
FROM
OTHER
BITS
x
POLARITY
SELECTION
Table 6. I/O Port Mode Options
Configuration Mode
Diodes
Pull-Up
P-Buffer
to V
to V
SS
DD
Floating with/without Interrupt
Pull-up with/without Interrupt
Push-pull
Off
On
Input
Off
On
On
Off
On
Off
NI
Output
Open Drain (logic level)
True Open Drain
NI
NI (see note)
Legend: NI - not implemented
Off - implemented not activated
On - implemented and activated
Note: The diode to V
is not implemented in the
DD
true open drain pads. A local protection between
the pad and V is implemented to protect the de-
SS
vice against positive stress.
40/153
ST72334J/N, ST72314J/N, ST72124J
I/O PORTS (Cont’d)
Table 7. I/O Port Configurations
Hardware Configuration
DR REGISTER ACCESS
NOT IMPLEMENTED IN
TRUE OPEN DRAIN
I/O PORTS
V
DD
R
PULL-UP
CONFIGURATION
W
R
PU
DR
REGISTER
DATA BUS
PAD
ALTERNATE INPUT
FROM
OTHER
PINS
EXTERNAL INTERRUPT
SOURCE (ei )
x
INTERRUPT
POLARITY
CONFIGURATION
SELECTION
ANALOG INPUT
NOT IMPLEMENTED IN
TRUE OPEN DRAIN
I/O PORTS
DR REGISTER ACCESS
V
DD
R
PU
R/W
DR
REGISTER
DATA BUS
PAD
ALTERNATE
ENABLE
ALTERNATE
OUTPUT
NOT IMPLEMENTED IN
TRUE OPEN DRAIN
I/O PORTS
DR REGISTER ACCESS
V
DD
R
PU
R/W
DR
REGISTER
DATA BUS
PAD
ALTERNATE
ENABLE
ALTERNATE
OUTPUT
Notes:
1. When the I/O port is in input configuration and the associated alternate function is enabled as an output,
reading the DR register will read the alternate function output status.
2. When the I/O port is in output configuration and the associated alternate function is enabled as an input,
the alternate function reads the pin status given by the DR register content.
41/153
ST72334J/N, ST72314J/N, ST72124J
I/O PORTS (Cont’d)
CAUTION: The alternate function must not be ac-
tivated as long as the pin is configured as input
with interrupt, in order to avoid generating spurious
interrupts.
Standard Ports
PA5:4, PC7:0, PD7:0, PE7:4, PE1:0, PF7:6, PF4
MODE
DDR
OR
Analog alternate function
floating input
pull-up input
0
0
1
1
0
1
0
1
When the pin is used as an ADC input, the I/O
must be configured as floating input. The analog
multiplexer (controlled by the ADC registers)
switches the analog voltage present on the select-
ed pin to the common analog rail which is connect-
ed to the ADC input.
open drain output
push-pull output
Interrupt Ports
PA2:0, PB7:5, PB2:0, PF1:0 (with pull-up)
It is recommended not to change the voltage level
or loading on any port pin while conversion is in
progress. Furthermore it is recommended not to
have clocking pins located close to a selected an-
alog pin.
MODE
DDR
OR
floating input
0
0
1
1
0
1
0
1
pull-up interrupt input
open drain output
push-pull output
WARNING: The analog input voltage level must
be within the limits stated in the absolute maxi-
mum ratings.
PA3, PB4, PB3, PF2 (without pull-up)
12.3 I/O PORT IMPLEMENTATION
MODE
DDR
OR
The hardware implementation on each I/O port de-
pends on the settings in the DDR and OR registers
and specific feature of the I/O port such as ADC In-
put or true open drain.
floating input
0
0
1
1
0
1
0
1
floating interrupt input
open drain output
push-pull output
Switching these I/O ports from one state to anoth-
er should be done in a sequence that prevents un-
wanted side effects. Recommended safe transi-
tions are illustrated in Figure 27 Other transitions
are potentially risky and should be avoided, since
they are likely to present unwanted side-effects
such as spurious interrupt generation.
True Open Drain Ports
PA7:6
MODE
DDR
floating input
0
1
open drain (high sink ports)
Figure 27. Interrupt I/O Port State Transitions
01
00
10
11
INPUT
floating/pull-up
interrupt
INPUT
floating
(reset state)
OUTPUT
open-drain
OUTPUT
push-pull
= DDR, OR
XX
The I/O port register configurations are summa-
rized as follows.
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ST72334J/N, ST72314J/N, ST72124J
I/O PORTS (Cont’d)
12.4 LOW POWER MODES
12.5 INTERRUPTS
The external interrupt event generates an interrupt
if the corresponding configuration is selected with
DDR and OR registers and the I-bit in the CC reg-
ister is reset (RIM instruction).
Mode
WAIT
HALT
Description
No effect on I/O ports. External interrupts
cause the device to exit from WAIT mode.
No effect on I/O ports. External interrupts
cause the device to exit from HALT mode.
Enable Exit
Control from
Exit
from
Halt
Event
Flag
Interrupt Event
Bit
Wait
External interrupt on
selected external
event
DDRx
ORx
-
Yes
Yes
Table 8. Port Configuration
Input
Output
OR = 1
Port
Pin name
OR = 0
OR = 1
OR = 0
High-Sink
PA7:6
PA5:4
PA3
floating
true open-drain
open drain
Yes
floating
floating
floating
floating
floating
floating
floating
floating
floating
floating
floating
floating
floating
floating
pull-up
push-pull
push-pull
push-pull
push-pull
push-pull
push-pull
push-pull
push-pull
push-pull
push-pull
push-pull
push-pull
push-pull
push-pull
Port A
Port B
floating interrupt
pull-up interrupt
floating interrupt
pull-up interrupt
pull-up
open drain
open drain
open drain
open drain
open drain
open drain
open drain
open drain
open drain
open drain
open drain
open drain
open drain
PA2:0
PB4:3
PB7:5, PB2:0
PC7:4, PC1:0
PC3:2
PD7:0
PE7:4
PE1:0
PF7:6
No
Port C
Port D
Port E
pull-up
Yes
No
pull-up
pull-up
Yes
No
pull-up
pull-up
Yes
PF4
pull-up
Port F
PF2
floating interrupt
pull-up interrupt
No
PF1:0
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ST72334J/N, ST72314J/N, ST72124J
I/O PORTS (Cont’d)
12.5.1 Register Description
DATA REGISTER (DR)
OPTION REGISTER (OR)
Port x Data Register
PxDR with x = A, B, C, D, E or F.
Port x Option Register
PxOR with x = A, B, C, D, E or F.
Read/Write
Read/Write
Reset Value: 0000 0000 (00h)
Reset Value: 0000 0000 (00h)
7
0
7
0
D7
D6
D5
D4
D3
D2
D1
D0
O7
O6
O5
O4
O3
O2
O1
O0
Bit 7:0 = D[7:0] Data register 8 bits.
Bit 7:0 = O[7:0] Option register 8 bits.
The DR register has a specific behaviour accord-
ing to the selected input/output configuration. Writ-
ing the DR register is always taken into account
even if the pin is configured as an input; this allows
to always have the expected level on the pin when
toggling to output mode. Reading the DR register
returns either the DR register latch content (pin
configured as output) or the digital value applied to
the I/O pin (pin configured as input).
For specific I/O pins, this register is not implement-
ed. In this case the DDR register is enough to se-
lect the I/O pin configuration.
The OR register allows to distinguish: in input
mode if the pull-up with interrupt capability or the
basic pull-up configuration is selected, in output
mode if the push-pull or open drain configuration is
selected.
Each bit is set and cleared by software.
Input mode:
0: floating input
1: pull-up input with or without interrupt
DATA DIRECTION REGISTER (DDR)
Port x Data Direction Register
PxDDR with x = A, B, C, D, E or F.
Output mode:
0: output open drain (with P-Buffer deactivated)
1: output push-pull
Read/Write
Reset Value: 0000 0000 (00h)
7
0
DD7
DD6
DD5
DD4
DD3
DD2
DD1
DD0
Bit 7:0 = DD[7:0] Data direction register 8 bits.
The DDR register gives the input/output direction
configuration of the pins. Each bits is set and
cleared by software.
0: Input mode
1: Output mode
44/153
ST72334J/N, ST72314J/N, ST72124J
I/O PORTS (Cont’d)
Table 9. I/O Port Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
Reset Value
of all IO port registers
0
0
0
0
0
0
0
0
0000h
0001h
0002h
0004h
0005h
0006h
0008h
0009h
000Ah
000Ch
000Dh
000Eh
0010h
0011h
0012h
0014h
0015h
0016h
PADR
PADDR
MSB
MSB
MSB
MSB
MSB
MSB
LSB
LSB
LSB
LSB
LSB
LSB
1)
PAOR
PCDR
PCDDR
PCOR
PBDR
PBDDR
1)
PBOR
PEDR
PEDDR
1)
PEOR
PDDR
PDDDR
1)
PDOR
PFDR
PFDDR
PFOR
Notes:
1) The bits corresponding to unavailable pins are forced to 1 by hardware, this affects the reset status value.
45/153
ST72334J/N, ST72314J/N, ST72124J
13 MISCELLANEOUS REGISTERS
The miscellaneous registers allow control over
several different features such as the external in-
terrupts or the I/O alternate functions.
Figure 28. Ext. Interrupt Sensitivity
MISCR1
IS10 IS11
13.1 I/O PORT INTERRUPT SENSITIVITY
PB0
INTERRUPT
SOURCE
ei2
The external interrupt sensitivity is controlled by
the ISxx bits of the MISCR1 miscellaneous regis-
ter. This control allows to have two fully independ-
ent external interrupt source sensitivities.
SENSITIVITY
CONTROL
PB1
PB2
ei3
PB3
PB4
Each external interrupt source can be generated
on four different events on the pin:
PB5
PB6
■ Falling edge
PB7
MISCR1
■ Rising edge
■ Falling and rising edge
■ Falling edge and low level
IS20
IS21
PA0
INTERRUPT
SOURCE
ei0
SENSITIVITY
CONTROL
PA1
PA2
To guarantee correct functionality, the sensitivity
bits in the MISCR1 register must be modified only
when the I bit of the CC register is set to 1 (inter-
rupt masked). See I/O port register and Miscella-
neous register descriptions for more details on the
programming.
ei1
PA3
PF0
PF1
PF2
13.2 I/O PORT ALTERNATE FUNCTIONS
The MISCR registers manage four I/O port miscel-
laneous alternate functions:
■ Main clock signal (f
) output on PF0
CPU
■ A beep signal output on PF1 (with 3 selectable
audio frequencies)
■ SPI pin configuration:
– SS pin internal control to use the PC7 I/O port
function while the SPI is active.
These functions are described in detail in the Sec-
tion 13 "MISCELLANEOUS REGISTERS" on
page 46.
46/153
ST72334J/N, ST72314J/N, ST72124J
MISCELLANEOUS REGISTERS (Cont’d)
13.3 REGISTERS DESCRIPTION
Bit 4:3 = IS2[1:0] ei0 and ei1 sensitivity
MISCELLANEOUS REGISTER 1 (MISCR1)
Read/Write
The interrupt sensitivity, defined using the IS2[1:0]
bits, is applied to the following external interrupts:-
ei0 (port A3..0) and ei1 (port F2..0). These 2 bits
can be written only when the I bit of the CC register
is set to 1 (interrupt disabled).
Reset Value: 0000 0000 (00h)
7
0
IS11 IS10 MCO IS21 IS20 CP1 CP0 SMS
Bit 2:1 = CP[1:0] CPU clock prescaler
These bits select the CPU clock prescaler which is
applied in the different slow modes. Their action is
conditioned by the setting of the SMS bit. These
two bits are set and cleared by software
Bit 7:6 = IS1[1:0] ei2 and ei3 sensitivity
The interrupt sensitivity, defined using the IS1[1:0]
bits, is applied to the following external interrupts:
ei2 (port B3..0) and ei3 (port B7..4). These 2 bits
can be written only when the I bit of the CC register
is set to 1 (interrupt disabled).
f
in SLOW mode
CP1 CP0
CPU
f
f
f
f
/ 4
0
1
0
1
0
0
1
1
OSC
OSC
OSC
OSC
/ 8
/ 16
/ 32
External Interrupt Sensitivity
Falling edge & low level
Rising edge only
IS11 IS10
0
0
1
1
0
1
0
1
Bit 0 = SMS Slow mode select
This bit is set and cleared by software.
Falling edge only
Rising and falling edge
0: Normal mode. f
= fOSC / 2
is given by CP1, CP0
CPU
1: Slow mode. f
CPU
See low power consumption mode and MCC
Bit 5 = MCO Main clock out selection
chapters for more details.
This bit enables the MCO alternate function on the
I/O port. It is set and cleared by software.
0: MCO alternate function disabled
(I/O pin free for general-purpose I/O)
1: MCO alternate function enabled
(f
/2 on I/O port)
OSC
Note: To reduce power consumption, the MCO
function is not active in ACTIVE-HALT mode.
47/153
ST72334J/N, ST72314J/N, ST72124J
MISCELLANEOUS REGISTERS (Cont’d)
MISCELLANEOUS REGISTER 2 (MISCR2)
Read/Write
Reset Value: 0000 0000 (00h)
7
0
-
-
BC1 BC0
-
-
SSM SSI
Bit 7:6 = Reserved Must always be cleared
Bit 5:4 = BC[1:0] Beep control
These 2 bits select the PF1 pin beep capability.
Beep mode with f
Off
=16MHz
BC1 BC0
OSC
0
0
1
1
0
1
0
1
~2-KHz
Output
Beep signal
~1-KHz
~50% duty cycle
~500-Hz
The beep output signal is available in ACTIVE-
HALT mode but has to be disabled to reduce the
consumption.
Bit 3:2 = Reserved Must always be cleared
Bit 1 = SSM SS mode selection
It is set and cleared by software.
0: Normal mode - SS uses information coming
from the SS pin of the SPI.
1: I/O mode, the SPI uses the information stored
into bit SSI.
Bit 0 = SSI SS internal mode
This bit replaces pin SS of the SPI when bit SSM is
set to 1. (see SPI description). It is set and cleared
by software.
Table 10. Miscellaneous Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
MISCR1
Reset Value
IS11
0
IS10
0
MCO
0
IS21
0
IS20
0
CP1
0
CP0
0
SMS
0
0020h
0040h
MISCR2
Reset Value
BC1
0
BC0
0
SSM
0
SSI
0
0
0
0
0
48/153
ST72334J/N, ST72314J/N, ST72124J
14 ON-CHIP PERIPHERALS
14.1 WATCHDOG TIMER (WDG)
14.1.1 Introduction
■ Hardware Watchdog selectable by option byte
■ Watchdog Reset indicated by status flag (in
The Watchdog timer is used to detect the occur-
rence of a software fault, usually generated by ex-
ternal interference or by unforeseen logical condi-
tions, which causes the application program to
abandon its normal sequence. The Watchdog cir-
cuit generates an MCU reset on expiry of a pro-
grammed time period, unless the program refresh-
es the counter’s contents before the T6 bit be-
comes cleared.
versions with Safe Reset option only)
14.1.3 Functional Description
The counter value stored in the CR register (bits
T[6:0]), is decremented every 12,288 machine cy-
cles, and the length of the timeout period can be
programmed by the user in 64 increments.
14.1.2 Main Features
If the watchdog is activated (the WDGA bit is set)
and when the 7-bit timer (bits T[6:0]) rolls over
from 40h to 3Fh (T6 becomes cleared), it initiates
a reset cycle pulling low the reset pin for typically
500ns.
■ Programmable timer (64 increments of 12288
CPU cycles)
■ Programmable reset
■ Reset (if watchdog activated) after a HALT
instruction or when the T6 bit reaches zero
Figure 29. Watchdog Block Diagram
RESET
WATCHDOG CONTROL REGISTER (CR)
T5
WDGA T6
T1
T0
T4
T2
T3
7-BIT DOWNCOUNTER
CLOCK DIVIDER
f
CPU
÷12288
49/153
ST72334J/N, ST72314J/N, ST72124J
WATCHDOG TIMER (Cont’d)
The application program must write in the CR reg-
ister at regular intervals during normal operation to
prevent an MCU reset. The value to be stored in
the CR register must be between FFh and C0h
(see Table 11 .Watchdog Timing (fCPU = 8 MHz)):
14.1.7 Register Description
CONTROL REGISTER (CR)
Read/Write
Reset Value: 0111 1111 (7Fh)
– The WDGA bit is set (watchdog enabled)
7
0
– The T6 bit is set to prevent generating an imme-
diate reset
WDGA T6
T5
T4
T3
T2
T1
T0
– The T[5:0] bits contain the number of increments
which represents the time delay before the
watchdog produces a reset.
Bit 7 = WDGA Activation bit.
This bit is set by software and only cleared by
hardware after a reset. When WDGA = 1, the
watchdog can generate a reset.
Table 11.Watchdog Timing (f
= 8 MHz)
CPU
CR Register
initial value
WDG timeout period
(ms)
0: Watchdog disabled
1: Watchdog enabled
Max
Min
FFh
C0h
98.304
1.536
Note: This bit is not used if the hardware watch-
dog option is enabled by option byte.
Bit 6:0 = T[6:0] 7-bit timer (MSB to LSB).
These bits contain the decremented value. A reset
is produced when it rolls over from 40h to 3Fh (T6
becomes cleared).
Notes: Following a reset, the watchdog is disa-
bled. Once activated it cannot be disabled, except
by a reset.
The T6 bit can be used to generate a software re-
set (the WDGA bit is set and the T6 bit is cleared).
STATUS REGISTER (SR)
Read/Write
If the watchdog is activated, the HALT instruction
will generate a Reset.
Reset Value*: 0000 0000 (00h)
14.1.4 Hardware Watchdog Option
7
-
0
If Hardware Watchdog is selected by option byte,
the watchdog is always active and the WDGA bit in
the CR is not used.
-
-
-
-
-
-
WDOGF
Refer to the device-specific Option Byte descrip-
tion.
Bit 0 = WDOGF Watchdog flag.
This bit is set by a watchdog reset and cleared by
software or a power on/off reset. This bit is useful
for distinguishing power/on off or external reset
and watchdog reset.
14.1.5 Low Power Modes
Mode
Description
0: No Watchdog reset occurred
1: Watchdog reset occurred
WAIT
No effect on Watchdog.
Immediate reset generation as soon as
the HALT instruction is executed if the
Watchdog is activated (WDGA bit is
set).
* Only by software and power on/off reset
HALT
Note: This register is not used in versions without
LVD Reset.
14.1.6 Interrupts
None.
50/153
ST72334J/N, ST72314J/N, ST72124J
WATCHDOG TIMER (Cont’d)
Table 12. Watchdog Timer Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
WDGCR
WDGA
0
T6
1
T5
1
T4
1
T3
1
T2
1
T1
1
T0
1
002Ah
Reset Value
51/153
ST72334J/N, ST72314J/N, ST72124J
14.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK TIMER (MCC/RTC)
The Main Clock Controller consists of three differ-
ent functions:
14.2.2 Clock-out capability
The clock-out capability is an alternate function of
an I/O port pin that outputs a f
external devices. It is controlled by the MCO bit in
the MISCR1 register.
CAUTION: When selected, the clock out pin sus-
pends the clock during ACTIVE-HALT mode.
■ a programmable CPU clock prescaler
/2 clock to drive
OSC
■ a clock-out signal to supply external devices
■ a real time clock timer with interrupt capability
Each function can be used independently and si-
multaneously.
14.2.3 Real time clock timer (RTC)
14.2.1 Programmable CPU clock prescaler
The counter of the real time clock timer allows an
interrupt to be generated based on an accurate
real time clock. Four different time bases depend-
The programmable CPU clock prescaler supplies
the clock for the ST7 CPU and its internal periph-
erals. It manages SLOW power saving mode (See
Section 11.2 "SLOW MODE" on page 35 for more
details).
ing directly on f
are available. The whole func-
OSC
tionality is controlled by four bits of the MCCSR
register: TB[1:0], OIE and OIF.
The prescaler selects the f
cy and is controlled by three bits in the MISCR1
register: CP[1:0] and SMS.
main clock frequen-
When the RTC interrupt is enabled (OIE bit set),
the ST7 enters ACTIVE-HALT mode when the
HALT instruction is executed. See Section 11.4
"ACTIVE-HALT AND HALT MODES" on page 37
for more details.
CPU
CAUTION: The prescaler does not act on the CAN
peripheral clock source. This peripheral is always
supplied by the f
/2 clock source.
OSC
Figure 30. Main Clock Controller (MCC/RTC) Block Diagram
PORT
ALTERNATE
FUNCTION
MCO
f
/2
OSC
MISCR1
-
-
MCO
-
-
CP1 CP0 SMS
f
OSC
DIV 2, 4, 8, 16
DIV 2
CPU CLOCK
TO CPU AND
PERIPHERALS
f
CPU
RTC
COUNTER
MCCSR
0
0
0
0
TB1 TB0 OIE OIF
MCC/RTC INTERRUPT
52/153
ST72334J/N, ST72314J/N, ST72124J
MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK TIMER (Cont’d)
MISCELLANEOUS REGISTER 1 (MISCR1)
Bit 0 = OIF Oscillator interrupt flag
See Section 13 on page 46.
This bit is set by hardware and cleared by software
reading the CSR register. It indicates when set
that the main oscillator has measured the selected
elapsed time (TB1:0).
MAIN CLOCK CONTROL/STATUS REGISTER
(MCCSR)
0: Timeout not reached
1: Timeout reached
Read/Write
Reset Value: 0000 0001 (01h)
CAUTION: The BRES and BSET instructions
must not be used on the MCCSR register to avoid
unintentionally clearing the OIF bit.
7
0
0
0
0
0
TB1
TB0
OIE
OIF
14.2.4 Low Power Modes
Mode
Description
Bit 7:4 = Reserved, always read as 0.
No effect on MCC/RTC peripheral.
MCC/RTC interrupt cause the device to exit
from WAIT mode.
WAIT
Bit 3:2 = TB[1:0] Time base control
No effect on MCC/RTC counter (OIE bit is
ACTIVE- set), the registers are frozen.
These bits select the programmable divider time
base. They are set and cleared by software.
HALT
MCC/RTC interrupt cause the device to exit
from ACTIVE-HALT mode.
Time Base
Counter
TB1 TB0
MCC/RTC counter and registers are frozen.
MCC/RTC operation resumes when the
MCU is woken up by an interrupt with “exit
from HALT” capability.
Prescaler
f
=8MHz
f
=16MHz
OSC
OSC
HALT
32000
64000
4ms
8ms
2ms
4ms
0
0
1
1
0
1
0
1
160000
400000
20ms
50ms
10ms
25ms
14.2.5 Interrupts
The MCC/RTC interrupt event generates an inter-
rupt if the OIE bit of the MCCSR register is set and
the interrupt mask in the CC register is not active
(RIM instruction).
A modification of the time base is taken into ac-
count at the end of the current period (previously
set) to avoid unwanted time shift. This allows to
use this time base as a real time clock.
Enable Exit
Control from
Bit
Exit
from
Halt
Event
Flag
Interrupt Event
Wait
Bit 1 = OIE Oscillator interrupt enable
Time base overflow
event
1)
OIF
OIE
Yes
No
This bit set and cleared by software.
0: Oscillator interrupt disabled
1: Oscillator interrupt enabled
This interrupt allows to exit from ACTIVE-HALT
Note:
1. The MCC/RTC interrupt allows to exit from AC-
TIVE-HALT mode, not from HALT mode.
mode.
When this bit is set, calling the ST7 software HALT
instruction enters the ACTIVE-HALT power saving
mode
.
Table 13. MCC Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
MCCSR
Reset Value
TB1
0
TB0
0
OIE
0
OIF
1
0029h
0
0
0
0
53/153
ST72334J/N, ST72314J/N, ST72124J
14.3 16-BIT TIMER
14.3.1 Introduction
14.3.3 Functional Description
14.3.3.1 Counter
The timer consists of a 16-bit free-running counter
driven by a programmable prescaler.
The main block of the Programmable Timer is a
16-bit free running upcounter and its associated
16-bit registers. The 16-bit registers are made up
of two 8-bit registers called high & low.
It may be used for a variety of purposes, including
measuring the pulse lengths of up to two input sig-
nals (input capture) or generating up to two output
waveforms (output compare and PWM).
Counter Register (CR):
Pulse lengths and waveform periods can be mod-
ulated from a few microseconds to several milli-
seconds using the timer prescaler and the CPU
clock prescaler.
– Counter High Register (CHR) is the most sig-
nificant byte (MS Byte).
– Counter Low Register (CLR) is the least sig-
nificant byte (LS Byte).
Some ST7 devices have two on-chip 16-bit timers.
They are completely independent, and do not
share any resources. They are synchronized after
a MCU reset as long as the timer clock frequen-
cies are not modified.
Alternate Counter Register (ACR)
– Alternate Counter High Register (ACHR) is the
most significant byte (MS Byte).
– Alternate Counter Low Register (ACLR) is the
least significant byte (LS Byte).
This description covers one or two 16-bit timers. In
ST7 devices with two timers, register names are
prefixed with TA (Timer A) or TB (Timer B).
These two read-only 16-bit registers contain the
same value but with the difference that reading the
ACLR register does not clear the TOF bit (Timer
overflow flag), located in the Status register (SR).
(See note at the end of paragraph titled 16-bit read
sequence).
14.3.2 Main Features
■ Programmableprescaler:fCPU dividedby2, 4or8.
■ Overflow status flag and maskable interrupt
■ External clock input (must be at least 4 times
slowerthan theCPUclockspeed)with thechoice
of active edge
■ Output compare functions with:
– 2 dedicated 16-bit registers
– 2 dedicated programmable signals
– 2 dedicated status flags
Writing in the CLR register or ACLR register resets
the free running counter to the FFFCh value.
Both counters have a reset value of FFFCh (this is
the only value which is reloaded in the 16-bit tim-
er). The reset value of both counters is also
FFFCh in One Pulse mode and PWM mode.
The timer clock depends on the clock control bits
of the CR2 register, as illustrated in Table 14 Clock
Control Bits. The value in the counter register re-
peats every 131072, 262144 or 524288 CPU clock
cycles depending on the CC[1:0] bits.
– 1 dedicated maskable interrupt
■ Input capture functions with:
– 2 dedicated 16-bit registers
– 2 dedicated active edge selection signals
– 2 dedicated status flags
The timer frequency can be f
or an external frequency.
/2, f
/4, f
/8
CPU
CPU
CPU
– 1 dedicated maskable interrupt
■ Pulse Width Modulation mode (PWM)
■ One Pulse mode
■ 5 alternate functionson I/O ports (ICAP1, ICAP2,
OCMP1, OCMP2, EXTCLK)*
The Block Diagram is shown in Figure 31.
*Note: Some timer pins may not be available (not
bonded) in some ST7 devices. Refer to the device
pin out description.
When reading an input signal on a non-bonded
pin, the value will always be ‘1’.
54/153
ST72334J/N, ST72314J/N, ST72124J
16-BIT TIMER (Cont’d)
Figure 31. Timer Block Diagram
ST7 INTERNAL BUS
f
CPU
MCU-PERIPHERAL INTERFACE
8 low
8-bit
8 high
8
8
8
8
8
8
8
8
buffer
w
w
w
w
EXEDG
h
o
h
o
h
o
h
lo
16
INPUT
CAPTURE
REGISTER
INPUT
CAPTURE
REGISTER
OUTPUT
COMPARE
REGISTER
OUTPUT
COMPARE
REGISTER
1/2
1/4
1/8
COUNTER
REGISTER
1
1
2
2
ALTERNATE
COUNTER
REGISTER
EXTCLK
pin
16
16
16
CC[1:0]
TIMER INTERNAL BUS
16 16
OVERFLOW
DETECT
EDGE DETECT
CIRCUIT1
OUTPUT COMPARE
CIRCUIT
ICAP1
pin
CIRCUIT
6
EDGE DETECT
CIRCUIT2
ICAP2
pin
OCMP1
pin
LATCH1
LATCH2
ICF1 OCF1 TOF ICF2 OCF2
0
0
0
OCMP2
pin
(Status Register) SR
EXEDG
ICIE OCIE TOIE FOLV2 FOLV1OLVL2 IEDG1 OLVL1
OC1E
OPM PWM CC1 CC0 IEDG2
OC2E
(Control Register 1) CR1
(Control Register 2) CR2
(See note)
Note: If IC, OC and TO interrupt requests have separate vectors
then the last OR is not present (See device Interrupt Vector Table)
TIMER INTERRUPT
55/153
ST72334J/N, ST72314J/N, ST72124J
16-BIT TIMER (Cont’d)
16-bit Read Sequence: (from either the Counter
Register or the Alternate Counter Register).
Clearing the overflow interrupt request is done in
two steps:
1. Reading the SR register while the TOF bit is set.
2. An access (read or write) to the CLR register.
Beginning of the sequence
Read
LS Byte
is buffered
Note: The TOF bit is not cleared by accessing the
ACLR register. The advantage of accessing the
ACLR register rather than the CLR register is that
it allows simultaneous use of the overflow function
and reading the free running counter at random
times (for example, to measure elapsed time) with-
out the risk of clearing the TOF bit erroneously.
MS Byte
At t0
Other
instructions
Returns the buffered
LS Byte value at t0
Read
LS Byte
At t0 +∆t
The timer is not affected by WAIT mode.
In HALT mode, the counter stops counting until the
mode is exited. Counting then resumes from the
previous count (MCU awakened by an interrupt) or
from the reset count (MCU awakened by a Reset).
Sequence completed
The user must read the MS Byte first, then the LS
Byte value is buffered automatically.
This buffered value remains unchanged until the
16-bit read sequence is completed, even if the
user reads the MS Byte several times.
14.3.3.2 External Clock
The external clock (where available) is selected if
CC0=1 and CC1=1 in the CR2 register.
After a complete reading sequence, if only the
CLR register or ACLR register are read, they re-
turn the LS Byte of the count value at the time of
the read.
The status of the EXEDG bit in the CR2 register
determines the type of level transition on the exter-
nal clock pin EXTCLK that will trigger the free run-
ning counter.
Whatever the timer mode used (input capture, out-
put compare, One Pulse mode or PWM mode) an
overflow occurs when the counter rolls over from
FFFFh to 0000h then:
The counter is synchronised with the falling edge
of the internal CPU clock.
A minimum of four falling edges of the CPU clock
must occur between two consecutive active edges
of the external clock; thus the external clock fre-
quency must be less than a quarter of the CPU
clock frequency.
– The TOF bit of the SR register is set.
– A timer interrupt is generated if:
– TOIE bit of the CR1 register is set and
– I bit of the CC register is cleared.
If one of these conditions is false, the interrupt re-
mains pending to be issued as soon as they are
both true.
56/153
ST72334J/N, ST72314J/N, ST72124J
16-BIT TIMER (Cont’d)
Figure 32. Counter Timing Diagram, internal clock divided by 2
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
FFFD FFFE FFFF 0000 0001 0002 0003
COUNTER REGISTER
TIMER OVERFLOW FLAG (TOF)
Figure 33. Counter Timing Diagram, internal clock divided by 4
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
FFFC
FFFD
0000
0001
COUNTER REGISTER
TIMER OVERFLOW FLAG (TOF)
Figure 34. Counter Timing Diagram, internal clock divided by 8
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
0000
FFFC
FFFD
COUNTER REGISTER
TIMER OVERFLOW FLAG (TOF)
Note: The MCU is in reset state when the internal reset signal is high. When it is low, the MCU is running.
57/153
ST72334J/N, ST72314J/N, ST72124J
16-BIT TIMER (Cont’d)
14.3.3.3 Input Capture
When an input capture occurs:
– The ICFi bit is set.
In this section, the index, i, may be 1 or 2 because
there are 2 input capture functions in the 16-bit
timer.
– The ICiR register contains the value of the free
running counter on the active transition on the
ICAPi pin (see Figure 36).
The two input capture 16-bit registers (IC1R and
IC2R) are used to latch the value of the free run-
ning counter after a transition is detected by the
ICAPi pin (see figure 5).
– A timer interrupt is generated if the ICIE bit is set
and the I bit is cleared in the CC register. Other-
wise, the interrupt remains pending until both
conditions become true.
MS Byte
ICiHR
LS Byte
ICiLR
Clearing the Input Capture interrupt request (i.e.
clearing the ICFi bit) is done in two steps:
ICiR
The ICiR register is a read-only register.
1. Reading the SR register while the ICFi bit is set.
2. An access (read or write) to the ICiLR register.
The active transition is software programmable
through the IEDGi bit of Control Registers (CRi).
Timing resolution is one count of the free running
Notes:
counter: (f
/CC[1:0]).
CPU
1. After reading the ICiHR register, the transfer of
input capture data is inhibited and ICFi will
never be set until the ICiLR register is also
read.
Procedure:
To use the input capture function, select the fol-
lowing in the CR2 register:
2. The ICiR register contains the free running
counter value which corresponds to the most
recent input capture.
– Select the timer clock (CC[1:0]) (see Table 14
Clock Control Bits).
3. The 2 input capture functions can be used
together even if the timer also uses the 2 output
compare functions.
– Select the edge of the active transition on the
ICAP2 pin with the IEDG2 bit (the ICAP2 pin
must be configured as a floating input or input
with pull-up without interrupt if this configuration
is available).
4. In One Pulse mode and PWM mode only the
input capture 2 function can be used.
And select the following in the CR1 register:
5. The alternate inputs (ICAP1 & ICAP2) are
always directly connected to the timer. So any
transitions on these pins activate the input cap-
ture function.
– Set the ICIE bit to generate an interrupt after an
input capture coming from either the ICAP1 pin
or the ICAP2 pin
Moreover if one of the ICAPi pin is configured
as an input and the second one as an output,
an interrupt can be generated if the user tog-
gles the output pin and if the ICIE bit is set.
This can be avoided if the input capture func-
tion i is disabled by reading the ICiHR (see note
1).
– Select the edge of the active transition on the
ICAP1 pin with the IEDG1 bit (the ICAP1 pin
must be configured as a floating input or input
with pull-up without interrupt if this configuration
is available).
6. The TOF bit can be used with an interrupt in
order to measure events that exceed the timer
range (FFFFh).
58/153
ST72334J/N, ST72314J/N, ST72124J
16-BIT TIMER (Cont’d)
Figure 35. Input Capture Block Diagram
ICAP1
pin
(Control Register 1) CR1
EDGE DETECT
CIRCUIT2
EDGE DETECT
CIRCUIT1
ICIE
IEDG1
ICAP2
pin
(Status Register) SR
ICF1
ICF2
0
0
0
IC2R Register
IC1R Register
(Control Register 2) CR2
16-BIT
16-BIT FREE RUNNING
COUNTER
IEDG2
CC0
CC1
Figure 36. Input Capture Timing Diagram
TIMER CLOCK
FF01
FF02
FF03
COUNTER REGISTER
ICAPi PIN
ICAPi FLAG
FF03
ICAPi REGISTER
Note: Active edge is rising edge.
59/153
ST72334J/N, ST72314J/N, ST72124J
16-BIT TIMER (Cont’d)
14.3.3.4 Output Compare
– The OCMPi pin takes OLVLi bit value (OCMPi
pin latch is forced low during reset).
In this section, the index, i, may be 1 or 2 because
there are 2 output compare functions in the 16-bit
timer.
– A timer interrupt is generated if the OCIE bit is
set in the CR1 register and the I bit is cleared in
the CC register (CC).
This function can be used to control an output
waveform or indicate when a period of time has
elapsed.
The OCiR register value required for a specific tim-
ing application can be calculated using the follow-
ing formula:
When a match is found between the Output Com-
pare register and the free running counter, the out-
put compare function:
– Assigns pins with a programmable value if the
OCiE bit is set
∆t f
* CPU
PRESC
∆ OCiR =
– Sets a flag in the status register
– Generates an interrupt if enabled
Where:
∆t
= Output compare period (in seconds)
= CPU clock frequency (in hertz)
Two 16-bit registers Output Compare Register 1
(OC1R) and Output Compare Register 2 (OC2R)
contain the value to be compared to the counter
register each timer clock cycle.
f
CPU
PRESC
= Timer prescaler factor (2, 4 or 8 de-
pending on CC[1:0] bits, see Table 14
Clock Control Bits)
MS Byte
OCiHR
LS Byte
OCiLR
OCiR
If the timer clock is an external clock, the formula
is:
These registers are readable and writable and are
not affected by the timer hardware. A reset event
changes the OCiR value to 8000h.
∆ OCiR = ∆t f
* EXT
Timing resolution is one count of the free running
Where:
counter: (f
).
CC[1:0]
CPU/
∆t
= Output compare period (in seconds)
= External timer clock frequency (in hertz)
f
EXT
Procedure:
To use the output compare function, select the fol-
lowing in the CR2 register:
Clearing the output compare interrupt request (i.e.
clearing the OCFi bit) is done by:
– Set the OCiE bit if an output is needed then the
OCMPi pin is dedicated to the output compare i
signal.
1. Reading the SR register while the OCFi bit is
set.
2. An access (read or write) to the OCiLR register.
– Select the timer clock (CC[1:0]) (see Table 14
Clock Control Bits).
The following procedure is recommended to pre-
vent the OCFi bit from being set between the time
it is read and the write to the OCiR register:
And select the following in the CR1 register:
– Select the OLVLi bit to applied to the OCMPi pins
after the match occurs.
– Write to the OCiHR register (further compares
are inhibited).
– Set the OCIE bit to generate an interrupt if it is
needed.
– Read the SR register (first step of the clearance
of the OCFi bit, which may be already set).
When a match is found between OCRi register
and CR register:
– Write to the OCiLR register (enables the output
compare function and clears the OCFi bit).
– OCFi bit is set.
60/153
ST72334J/N, ST72314J/N, ST72124J
Forced Compare Output capability
16-BIT TIMER (Cont’d)
Notes:
1. After a processor write cycle to the OCiHR reg-
ister, the output compare function is inhibited
until the OCiLR register is also written.
When the FOLVi bit is set by software, the OLVLi
bit is copied to the OCMPi pin. The OLVi bit has to
be toggled in order to toggle the OCMPi pin when
it is enabled (OCiE bit=1). The OCFi bit is then not
set by hardware, and thus no interrupt request is
generated.
2. If the OCiE bit is not set, the OCMPi pin is a
general I/O port and the OLVLi bit will not
appear when a match is found but an interrupt
could be generated if the OCIE bit is set.
3. When the timer clock is f
/2, OCFi and
FOLVLi bits have no effect in either One-Pulse
mode or PWM mode.
CPU
OCMPi are set while the counter value equals
the OCiR register value (see Figure 38 on page
62). This behaviour is the same in OPM or
PWM mode.
When the timer clock is f
/4, f
/8 or in
CPU
CPU
external clock mode, OCFi and OCMPi are set
while the counter value equals the OCiR regis-
ter value plus 1 (see Figure 39 on page 62).
4. The output compare functions can be used both
for generating external events on the OCMPi
pins even if the input capture mode is also
used.
5. The value in the 16-bit OCiR register and the
OLVi bit should be changed after each suc-
cessful comparison in order to control an output
waveform or establish a new elapsed timeout.
Figure 37. Output Compare Block Diagram
16 BIT FREE RUNNING
OC1E
CC1 CC0
OC2E
COUNTER
(Control Register 2) CR2
16-bit
(Control Register 1) CR1
OUTPUT COMPARE
CIRCUIT
Latch
1
OCIE
FOLV2 FOLV1OLVL2
OLVL1
OCMP1
Pin
16-bit
16-bit
Latch
2
OCMP2
Pin
OC1R Register
OCF1
OCF2
0
0
0
OC2R Register
(Status Register) SR
61/153
ST72334J/N, ST72314J/N, ST72124J
16-BIT TIMER (Cont’d)
Figure 38. Output Compare Timing Diagram, f
=f
/2
TIMER
CPU
INTERNAL CPU CLOCK
TIMER CLOCK
COUNTER REGISTER
2ECF 2ED0 2ED1 2ED2
2ED3
2ED4
2ED3
OUTPUT COMPARE REGISTER i (OCRi)
OUTPUT COMPARE FLAG i (OCFi)
OCMPi PIN (OLVLi=1)
Figure 39. Output Compare Timing Diagram, f
=f
/4
TIMER
CPU
INTERNAL CPU CLOCK
TIMER CLOCK
2ECF 2ED0 2ED1 2ED2
2ED3
2ED4
2ED3
COUNTER REGISTER
OUTPUT COMPARE REGISTER i (OCRi)
COMPARE REGISTER i LATCH
OUTPUT COMPARE FLAG i (OCFi)
OCMPi PIN (OLVLi=1)
62/153
ST72334J/N, ST72314J/N, ST72124J
16-BIT TIMER (Cont’d)
14.3.3.5 One Pulse Mode
Clearing the Input Capture interrupt request (i.e.
clearing the ICFi bit) is done in two steps:
One Pulse mode enables the generation of a
pulse when an external event occurs. This mode is
selected via the OPM bit in the CR2 register.
1. Reading the SR register while the ICFi bit is set.
2. An access (read or write) to the ICiLR register.
The One Pulse mode uses the Input Capture1
function and the Output Compare1 function.
The OC1R register value required for a specific
timing application can be calculated using the fol-
lowing formula:
Procedure:
t * f
To use One Pulse mode:
CPU
- 5
OCiR Value =
1. Load the OC1R register with the value corre-
sponding to the length of the pulse (see the for-
mula in the opposite column).
PRESC
Where:
t
= Pulse period (in seconds)
2. Select the following in the CR1 register:
f
= CPU clock frequency (in hertz)
CPU
PRESC
– Using the OLVL1 bit, select the level to be ap-
plied to the OCMP1 pin after the pulse.
= Timer prescaler factor (2, 4 or 8 depend-
ing on the CC[1:0] bits, see Table 14
Clock Control Bits)
– Using the OLVL2 bit, select the level to be ap-
plied to the OCMP1 pin during the pulse.
If the timer clock is an external clock the formula is:
– Select the edge of the active transition on the
ICAP1 pin with the IEDG1 bit (the ICAP1 pin
must be configured as floating input).
OCiR = t f
-5
* EXT
Where:
t
3. Select the following in the CR2 register:
= Pulse period (in seconds)
– Set the OC1E bit, the OCMP1 pin is then ded-
icated to the Output Compare 1 function.
f
= External timer clock frequency (in hertz)
EXT
– Set the OPM bit.
When the value of the counter is equal to the value
of the contents of the OC1R register, the OLVL1
bit is output on the OCMP1 pin (see Figure 40).
– Select the timer clock CC[1:0] (see Table 14
Clock Control Bits).
One Pulse mode cycle
When
Notes:
1. The OCF1 bit cannot be set by hardware in
One Pulse mode but the OCF2 bit can generate
an Output Compare interrupt.
OCMP1 = OLVL2
event occurs
on ICAP1
Counter is reset
2. When the Pulse Width Modulation (PWM) and
One Pulse mode (OPM) bits are both set, the
PWM mode is the only active one.
to FFFCh
ICF1 bit is set
3. If OLVL1=OLVL2 a continuous signal will be
seen on the OCMP1 pin.
When
Counter
OCMP1 = OLVL1
= OC1R
4. The ICAP1 pin can not be used to perform input
capture. The ICAP2 pin can be used to perform
input capture (ICF2 can be set and IC2R can be
loaded) but the user must take care that the
counter is reset each time a valid edge occurs
on the ICAP1 pin and ICF1 can also generates
interrupt if ICIE is set.
Then, on a valid event on the ICAP1 pin, the coun-
ter is initialized to FFFCh and the OLVL2 bit is
loaded on the OCMP1 pin, the ICF1 bit is set and
the value FFFDh is loaded in the IC1R register.
Because the ICF1 bit is set when an active edge
occurs, an interrupt can be generated if the ICIE
bit is set.
5. When One Pulse mode is used OC1R is dedi-
cated to this mode. Nevertheless OC2R and
OCF2 can be used to indicate that a period of
time has elapsed but cannot generate an output
waveform because the OLVL2 level is dedi-
cated to One Pulse mode.
63/153
ST72334J/N, ST72314J/N, ST72124J
16-BIT TIMER (Cont’d)
Figure 40. One Pulse Mode Timing Example
FFFC FFFD FFFE
COUNTER
2ED0 2ED1 2ED2
2ED3
FFFC FFFD
ICAP1
OLVL2
OLVL1
OLVL2
OCMP1
compare1
Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1
Figure 41. Pulse Width Modulation Mode Timing Example
2ED0 2ED1 2ED2
34E2 FFFC
FFFC FFFD FFFE
34E2
COUNTER
OCMP1
OLVL2
OLVL1
OLVL2
compare2
compare1
compare2
Note: OC1R=2ED0h, OC2R=34E2, OLVL1=0, OLVL2= 1
64/153
ST72334J/N, ST72314J/N, ST72124J
16-BIT TIMER (Cont’d)
14.3.3.6 Pulse Width Modulation Mode
Pulse Width Modulation (PWM) mode enables the
generation of a signal with a frequency and pulse
length determined by the value of the OC1R and
OC2R registers.
The OCiR register value required for a specific tim-
ing application can be calculated using the follow-
ing formula:
t * f
CPU
PRESC
- 5
OCiR Value =
The Pulse Width Modulation mode uses the com-
plete Output Compare 1 function plus the OC2R
register, and so these functions cannot be used
when the PWM mode is activated.
Where:
t
= Signal or pulse period (in seconds)
= CPU clock frequency (in hertz)
f
Procedure
CPU
= Timer prescaler factor (2, 4 or 8 depend-
ing on CC[1:0] bits, see Table 14 Clock
Control Bits)
To use Pulse Width Modulation mode:
PRESC
1. Load the OC2R register with the value corre-
sponding to the period of the signal using the
formula in the opposite column.
If the timer clock is an external clock the formula is:
2. Load the OC1R register with the value corre-
sponding to the period of the pulse if OLVL1=0
and OLVL2=1, using the formula in the oppo-
site column.
OCiR = t f
-5
* EXT
Where:
t
= Signal or pulse period (in seconds)
3. Select the following in the CR1 register:
f
= External timer clock frequency (in hertz)
EXT
– Using the OLVL1 bit, select the level to be ap-
plied to the OCMP1 pin after a successful
comparison with OC1R register.
The Output Compare 2 event causes the counter
to be initialized to FFFCh (See Figure 41)
– Using the OLVL2 bit, select the level to be ap-
plied to the OCMP1 pin after a successful
comparison with OC2R register.
Notes:
1. After a write instruction to the OCiHR register,
the output compare function is inhibited until the
OCiLR register is also written.
4. Select the following in the CR2 register:
– Set OC1E bit: the OCMP1 pin is then dedicat-
ed to the output compare 1 function.
2. The OCF1 and OCF2 bits cannot be set by
hardware in PWM mode, therefore the Output
Compare interrupt is inhibited.
– Set the PWM bit.
– Select the timer clock (CC[1:0]) (see Table 14
Clock Control Bits).
3. The ICF1 bit is set by hardware when the coun-
ter reaches the OC2R value and can produce a
timer interrupt if the ICIE bit is set and the I bit is
cleared.
If OLVL1=1 and OLVL2=0, the length of the posi-
tive pulse is the difference between the OC2R and
OC1R registers.
4. In PWM mode the ICAP1 pin can not be used
to perform input capture because it is discon-
nected from the timer. The ICAP2 pin can be
used to perform input capture (ICF2 can be set
and IC2R can be loaded) but the user must
take care that the counter is reset after each
period and ICF1 can also generate an interrupt
if ICIE is set.
If OLVL1=OLVL2 a continuous signal will be seen
on the OCMP1 pin.
Pulse Width Modulation cycle
When
Counter
= OC1R
OCMP1 = OLVL1
OCMP1 = OLVL2
5. When the Pulse Width Modulation (PWM) and
One Pulse mode (OPM) bits are both set, the
PWM mode is the only active one.
When
Counter
= OC2R
Counter is reset
to FFFCh
ICF1 bit is set
65/153
ST72334J/N, ST72314J/N, ST72124J
16-BIT TIMER (Cont’d)
14.3.4 Low Power Modes
Mode
Description
No effect on 16-bit Timer.
WAIT
Timer interrupts cause the device to exit from WAIT mode.
16-bit Timer registers are frozen.
In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous
count when the MCU is woken up by an interrupt with “exit from HALT mode” capability or from the counter
reset value when the MCU is woken up by a RESET.
HALT
If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is armed. Consequent-
ly, when the MCU is woken up by an interrupt with “exit from HALT mode” capability, the ICFi bit is set, and
the counter value present when exiting from HALT mode is captured into the ICiR register.
14.3.5 Interrupts
Enable
Control from
Bit
Exit
Exit
from
Halt
Event
Flag
Interrupt Event
Wait
Yes
Yes
Yes
Yes
Yes
Input Capture 1 event/Counter reset in PWM mode
Input Capture 2 event
ICF1
ICF2
No
No
No
No
No
ICIE
Output Compare 1 event (not available in PWM mode)
Output Compare 2 event (not available in PWM mode)
Timer Overflow event
OCF1
OCF2
TOF
OCIE
TOIE
Note: The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts chap-
ter). These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt
mask in the CC register is reset (RIM instruction).
14.3.6 Summary of Timer modes
AVAILABLE RESOURCES
MODES
Input Capture 1
Input Capture 2
Yes
Output Compare 1 Output Compare 2
Input Capture (1 and/or 2)
Output Compare (1 and/or 2)
One Pulse mode
Yes
Yes
No
Yes
Yes
No
Yes
Yes
Yes
1)
3)
2)
Not Recommended
Not Recommended
Partially
No
PWM Mode
No
No
1)
2)
3)
See note 4 in Section 14.3.3.5 "One Pulse Mode" on page 63
See note 5 in Section 14.3.3.5 "One Pulse Mode" on page 63
See note 4 in Section 14.3.3.6 "Pulse Width Modulation Mode" on page 65
66/153
ST72334J/N, ST72314J/N, ST72124J
16-BIT TIMER (Cont’d)
14.3.7 Register Description
Bit 4 = FOLV2 Forced Output Compare 2.
This bit is set and cleared by software.
0: No effect on the OCMP2 pin.
1: Forces the OLVL2 bit to be copied to the
OCMP2 pin, if the OC2E bit is set and even if
there is no successful comparison.
Each Timer is associated with three control and
status registers, and with six pairs of data registers
(16-bit values) relating to the two input captures,
the two output compares, the counter and the al-
ternate counter.
Bit 3 = FOLV1 Forced Output Compare 1.
This bit is set and cleared by software.
0: No effect on the OCMP1 pin.
CONTROL REGISTER 1 (CR1)
Read/Write
1: Forces OLVL1 to be copied to the OCMP1 pin, if
the OC1E bit is set and even if there is no suc-
cessful comparison.
Reset Value: 0000 0000 (00h)
7
0
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
Bit 2 = OLVL2 Output Level 2.
This bit is copied to the OCMP2 pin whenever a
successful comparison occurs with the OC2R reg-
ister and OCxE is set in the CR2 register. This val-
ue is copied to the OCMP1 pin in One Pulse mode
and Pulse Width Modulation mode.
Bit 7 = ICIE Input Capture Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the
ICF1 or ICF2 bit of the SR register is set.
Bit 1 = IEDG1 Input Edge 1.
Bit 6 = OCIE Output Compare Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the
This bit determines which type of level transition
on the ICAP1 pin will trigger the capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
OCF1 or OCF2 bit of the SR register is set.
Bit 5 = TOIE Timer Overflow Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is enabled whenever the TOF
Bit 0 = OLVL1 Output Level 1.
The OLVL1 bit is copied to the OCMP1 pin when-
ever a successful comparison occurs with the
OC1R register and the OC1E bit is set in the CR2
register.
bit of the SR register is set.
67/153
ST72334J/N, ST72314J/N, ST72124J
16-BIT TIMER (Cont’d)
CONTROL REGISTER 2 (CR2)
Read/Write
Bit 4 = PWM Pulse Width Modulation.
0: PWM mode is not active.
1: PWM mode is active, the OCMP1 pin outputs a
programmable cyclic signal; the length of the
pulse depends on the value of OC1R register;
the period depends on the value of OC2R regis-
ter.
Reset Value: 0000 0000 (00h)
7
0
OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG
Bits 3:2 = CC[1:0] Clock Control.
Bit 7 = OC1E Output Compare 1 Pin Enable.
This bit is used only to output the signal from the
timer on the OCMP1 pin (OLV1 in Output Com-
pare mode, both OLV1 and OLV2 in PWM and
one-pulse mode). Whatever the value of the OC1E
bit, the internal Output Compare 1 function of the
timer remains active.
0: OCMP1 pin alternate function disabled (I/O pin
free for general-purpose I/O).
1: OCMP1 pin alternate function enabled.
The timer clock mode depends on these bits:
Table 14. Clock Control Bits
Timer Clock
fCPU / 4
CC1
CC0
0
0
1
0
1
0
fCPU / 2
fCPU / 8
External Clock (where
available)
1
1
Bit 6 = OC2E Output Compare 2 Pin Enable.
This bit is used only to output the signal from the
timer on the OCMP2 pin (OLV2 in Output Com-
pare mode). Whatever the value of the OC2E bit,
the internal Output Compare 2 function of the timer
remains active.
0: OCMP2 pin alternate function disabled (I/O pin
free for general-purpose I/O).
1: OCMP2 pin alternate function enabled.
Note: If the external clock pin is not available, pro-
gramming the external clock configuration stops
the counter.
Bit 1 = IEDG2 Input Edge 2.
This bit determines which type of level transition
on the ICAP2 pin will trigger the capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
Bit 5 = OPM One Pulse mode.
0: One Pulse mode is not active.
Bit 0 = EXEDG External Clock Edge.
1: One Pulse mode is active, the ICAP1 pin can be
used to trigger one pulse on the OCMP1 pin; the
active transition is given by the IEDG1 bit. The
length of the generated pulse depends on the
contents of the OC1R register.
This bit determines which type of level transition
on the external clock pin (EXTCLK) will trigger the
counter register.
0: A falling edge triggers the counter register.
1: A rising edge triggers the counter register.
68/153
ST72334J/N, ST72314J/N, ST72124J
16-BIT TIMER (Cont’d)
STATUS REGISTER (SR)
Read Only
INPUT CAPTURE 1 HIGH REGISTER (IC1HR)
Read Only
Reset Value: Undefined
Reset Value: 0000 0000 (00h)
The three least significant bits are not used.
7
This is an 8-bit read only register that contains the
high part of the counter value (transferred by the
input capture 1 event).
0
0
ICF1 OCF1 TOF ICF2 OCF2
0
0
7
0
MSB
LSB
Bit 7 = ICF1 Input Capture Flag 1.
0: No input capture (reset value).
1: An input capture has occurred on the ICAP1 pin
or the counter has reached the OC2R value in
PWM mode. To clear this bit, first read the SR
register, then read or write the low byte of the
IC1R (IC1LR) register.
INPUT CAPTURE 1 LOW REGISTER (IC1LR)
Read Only
Reset Value: Undefined
This is an 8-bit read only register that contains the
low part of the counter value (transferred by the in-
put capture 1 event).
Bit 6 = OCF1 Output Compare Flag 1.
0: No match (reset value).
1: The content of the free running counter matches
the content of the OC1R register. To clear this
bit, first read the SR register, then read or write
the low byte of the OC1R (OC1LR) register.
7
0
MSB
LSB
Bit 5 = TOF Timer Overflow Flag.
0: No timer overflow (reset value).
1:The free running counter has rolled over from
FFFFh to 0000h. To clear this bit, first read the
SR register, then read or write the low byte of
the CR (CLR) register.
OUTPUT COMPARE
(OC1HR)
1
HIGH REGISTER
Read/Write
Reset Value: 1000 0000 (80h)
This is an 8-bit register that contains the high part
of the value to be compared to the CHR register.
Note: Reading or writing the ACLR register does
not clear TOF.
7
0
MSB
LSB
Bit 4 = ICF2 Input Capture Flag 2.
0: No input capture (reset value).
1: An input capture has occurred on the ICAP2
pin. To clear this bit, first read the SR register,
then read or write the low byte of the IC2R
(IC2LR) register.
OUTPUT COMPARE
(OC1LR)
1
LOW REGISTER
Read/Write
Reset Value: 0000 0000 (00h)
Bit 3 = OCF2 Output Compare Flag 2.
0: No match (reset value).
This is an 8-bit register that contains the low part of
the value to be compared to the CLR register.
1: The content of the free running counter matches
the content of the OC2R register. To clear this
bit, first read the SR register, then read or write
the low byte of the OC2R (OC2LR) register.
7
0
MSB
LSB
Bit 2-0 = Reserved, forced by hardware to 0.
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16-BIT TIMER (Cont’d)
OUTPUT COMPARE
(OC2HR)
2
HIGH REGISTER
ALTERNATE COUNTER HIGH REGISTER
(ACHR)
Read/Write
Reset Value: 1000 0000 (80h)
Read Only
Reset Value: 1111 1111 (FFh)
This is an 8-bit register that contains the high part
of the value to be compared to the CHR register.
This is an 8-bit register that contains the high part
of the counter value.
7
0
7
0
MSB
LSB
MSB
LSB
OUTPUT COMPARE
(OC2LR)
2
LOW REGISTER
ALTERNATE COUNTER LOW REGISTER
(ACLR)
Read/Write
Reset Value: 0000 0000 (00h)
Read Only
Reset Value: 1111 1100 (FCh)
This is an 8-bit register that contains the low part of
the value to be compared to the CLR register.
This is an 8-bit register that contains the low part of
the counter value. A write to this register resets the
counter. An access to this register after an access
to SR register does not clear the TOF bit in SR
register.
7
0
MSB
LSB
7
0
COUNTER HIGH REGISTER (CHR)
MSB
LSB
Read Only
Reset Value: 1111 1111 (FFh)
INPUT CAPTURE 2 HIGH REGISTER (IC2HR)
This is an 8-bit register that contains the high part
of the counter value.
Read Only
Reset Value: Undefined
7
0
This is an 8-bit read only register that contains the
high part of the counter value (transferred by the
Input Capture 2 event).
MSB
LSB
7
0
MSB
LSB
COUNTER LOW REGISTER (CLR)
Read Only
Reset Value: 1111 1100 (FCh)
This is an 8-bit register that contains the low part of
the counter value. A write to this register resets the
counter. An access to this register after accessing
the SR register clears the TOF bit.
INPUT CAPTURE 2 LOW REGISTER (IC2LR)
Read Only
Reset Value: Undefined
This is an 8-bit read only register that contains the
low part of the counter value (transferred by the In-
put Capture 2 event).
7
0
MSB
LSB
7
0
MSB
LSB
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16-BIT TIMER (Cont’d)
Table 15. 16-Bit Timer Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
Timer A: 32 CR1
ICIE
0
OCIE
0
TOIE
0
FOLV2
0
FOLV1
0
OLVL2
0
IEDG1
0
OLVL1
0
Timer B: 42 Reset Value
Timer A: 31 CR2
OC1E
0
OC2E
0
OPM
0
PWM
0
CC1
0
CC0
0
IEDG2
0
EXEDG
0
Timer B: 41 Reset Value
Timer A: 33 SR
ICF1
0
OCF1
0
TOF
0
ICF2
0
OCF2
0
-
-
-
Timer B: 43 Reset Value
0
0
0
Timer A: 34 ICHR1
MSB
-
LSB
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Timer B: 44 Reset Value
Timer A: 35 ICLR1
MSB
-
LSB
-
Timer B: 45 Reset Value
Timer A: 36 OCHR1
MSB
-
LSB
-
Timer B: 46 Reset Value
Timer A: 37 OCLR1
MSB
-
LSB
-
Timer B: 47 Reset Value
Timer A: 3E OCHR2
MSB
-
LSB
-
Timer B: 4E Reset Value
Timer A: 3F OCLR2
MSB
-
LSB
-
Timer B: 4F Reset Value
Timer A: 38 CHR
MSB
1
LSB
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
Timer B: 48 Reset Value
Timer A: 39 CLR
MSB
1
LSB
0
Timer B: 49 Reset Value
Timer A: 3A ACHR
MSB
1
LSB
1
Timer B: 4A Reset Value
Timer A: 3B ACLR
MSB
1
LSB
0
1
-
1
-
1
-
1
-
1
-
0
-
Timer B: 4B Reset Value
Timer A: 3C ICHR2
MSB
-
LSB
-
Timer B: 4C Reset Value
Timer A: 3D ICLR2
MSB
-
LSB
-
-
-
-
-
-
-
Timer B: 4D Reset Value
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14.4 SERIAL PERIPHERAL INTERFACE (SPI)
14.4.1 Introduction
14.4.3 General description
The Serial Peripheral Interface (SPI) allows full-
duplex, synchronous, serial communication with
external devices. An SPI system may consist of a
master and one or more slaves or a system in
which devices may be either masters or slaves.
The SPI is connected to external devices through
4 alternate pins:
– MISO: Master In Slave Out pin
– MOSI: Master Out Slave In pin
– SCK: Serial Clock pin
The SPI is normally used for communication be-
tween the microcontroller and external peripherals
or another microcontroller.
– SS: Slave select pin
Refer to the Pin Description chapter for the device-
specific pin-out.
A basic example of interconnections between a
single master and a single slave is illustrated on
Figure 42.
14.4.2 Main Features
The MOSI pins are connected together as are
MISO pins. In this way data is transferred serially
between master and slave (most significant bit
first).
■ Full duplex, three-wire synchronous transfers
■ Master or slave operation
■ Four master mode frequencies
When the master device transmits data to a slave
device via MOSI pin, the slave device responds by
sending data to the master device via the MISO
pin. This implies full duplex transmission with both
data out and data in synchronized with the same
clock signal (which is provided by the master de-
vice via the SCK pin).
■ Maximum slave mode frequency = f
/4.
CPU
■ Four programmable master bit rates
■ Programmable clock polarity and phase
■ End of transfer interrupt flag
■ Write collision flag protection
■ Master mode fault protection capability.
Thus, the byte transmitted is replaced by the byte
received and eliminates the need for separate
transmit-empty and receiver-full bits. A status flag
is used to indicate that the I/O operation is com-
plete.
Four possible data/clock timing relationships may
be chosen (see Figure 45) but master and slave
must be programmed with the same timing mode.
Figure 42. Serial Peripheral Interface Master/Slave
MASTER
SLAVE
MSBit
LSBit
MSBit
LSBit
MISO
MOSI
MISO
MOSI
8-BIT SHIFT REGISTER
8-BIT SHIFT REGISTER
SPI
CLOCK
GENERATOR
SCK
SS
SCK
SS
+5V
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SERIAL PERIPHERAL INTERFACE (Cont’d)
Figure 43. Serial Peripheral Interface Block Diagram
Internal Bus
Read
DR
Read Buffer
IT
request
MOSI
SR
MISO
8-Bit Shift Register
Write
MODF
WCOL
SPIF
-
-
-
-
-
SPI
STATE
CONTROL
SCK
SS
CR
SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0
MASTER
CONTROL
SERIAL
CLOCK
GENERATOR
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SERIAL PERIPHERAL INTERFACE (Cont’d)
14.4.4 Functional Description
In this configuration the MOSI pin is a data output
and to the MISO pin is a data input.
Figure 42 shows the serial peripheral interface
(SPI) block diagram.
This interface contains 3 dedicated registers:
– A Control Register (CR)
Transmit sequence
The transmit sequence begins when a byte is writ-
ten the DR register.
– A Status Register (SR)
The data byte is parallel loaded into the 8-bit shift
register (from the internal bus) during a write cycle
and then shifted out serially to the MOSI pin most
significant bit first.
– A Data Register (DR)
Refer to the CR, SR and DR registers in Section
14.4.7for the bit definitions.
14.4.4.1 Master Configuration
When data transfer is complete:
– The SPIF bit is set by hardware
In a master configuration, the serial clock is gener-
ated on the SCK pin.
– An interrupt is generated if the SPIE bit is set
and the I bit in the CCR register is cleared.
Procedure
– Select the SPR0 & SPR1 bits to define the se-
rial clock baud rate (see CR register).
During the last clock cycle the SPIF bit is set, a
copy of the data byte received in the shift register
is moved to a buffer. When the DR register is read,
the SPI peripheral returns this buffered value.
– Select the CPOL and CPHA bits to define one
of the four relationships between the data
transfer and the serial clock (see Figure 45).
Clearing the SPIF bit is performed by the following
software sequence:
– The SS pin must be connected to a high level
signal during the complete byte transmit se-
quence.
1. An access to the SR register while the SPIF bit
is set
– The MSTR and SPE bits must be set (they re-
main set only if the SS pin is connected to a
high level signal).
2. A read to the DR register.
Note: While the SPIF bit is set, all writes to the DR
register are inhibited until the SR register is read.
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SERIAL PERIPHERAL INTERFACE (Cont’d)
14.4.4.2 Slave Configuration
When data transfer is complete:
– The SPIF bit is set by hardware
In slave configuration, the serial clock is received
on the SCK pin from the master device.
– An interrupt is generated if SPIE bit is set and
I bit in CCR register is cleared.
The value of the SPR0 & SPR1 bits is not used for
the data transfer.
During the last clock cycle the SPIF bit is set, a
copy of the data byte received in the shift register
is moved to a buffer. When the DR register is read,
the SPI peripheral returns this buffered value.
Procedure
– For correct data transfer, the slave device
must be in the same timing mode as the mas-
ter device (CPOL and CPHA bits). See Figure
45.
Clearing the SPIF bit is performed by the following
software sequence:
1. An access to the SR register while the SPIF bit
is set.
– The SS pin must be connected to a low level
signal during the complete byte transmit se-
quence.
2.A read to the DR register.
– Clear the MSTR bit and set the SPE bit to as-
sign the pins to alternate function.
Notes: While the SPIF bit is set, all writes to the
DR register are inhibited until the SR register is
read.
In this configuration the MOSI pin is a data input
and the MISO pin is a data output.
The SPIF bit can be cleared during a second
transmission; however, it must be cleared before
the second SPIF bit in order to prevent an overrun
condition (see Section 14.4.4.6).
Transmit Sequence
The data byte is parallel loaded into the 8-bit shift
register (from the internal bus) during a write cycle
and then shifted out serially to the MISO pin most
significant bit first.
Depending on the CPHA bit, the SS pin has to be
set to write to the DR register between each data
byte transfer to avoid a write collision (see Section
14.4.4.4).
The transmit sequence begins when the slave de-
vice receives the clock signal and the most signifi-
cant bit of the data on its MOSI pin.
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SERIAL PERIPHERAL INTERFACE (Cont’d)
14.4.4.3 Data Transfer Format
The master device applies data to its MOSI pin-
clock edge before the capture clock edge.
During an SPI transfer, data is simultaneously
transmitted (shifted out serially) and received
(shifted in serially). The serial clock is used to syn-
chronize the data transfer during a sequence of
eight clock pulses.
CPHA bit is set
The second edge on the SCK pin (falling edge if
the CPOL bit is reset, rising edge if the CPOL bit is
set) is the MSBit capture strobe. Data is latched on
the occurrence of the second clock transition.
The SS pin allows individual selection of a slave
device; the other slave devices that are not select-
ed do not interfere with the SPI transfer.
No write collision should occur even if the SS pin
stays low during a transfer of several bytes (see
Figure 44).
Clock Phase and Clock Polarity
Four possible timing relationships may be chosen
by software, using the CPOL and CPHA bits.
CPHA bit is reset
The CPOL (clock polarity) bit controls the steady
state value of the clock when no data is being
transferred. This bit affects both master and slave
modes.
The first edge on the SCK pin (falling edge if CPOL
bit is set, rising edge if CPOL bit is reset) is the
MSBit capture strobe. Data is latched on the oc-
currence of the first clock transition.
The combination between the CPOL and CPHA
(clock phase) bits selects the data capture clock
edge.
The SS pin must be toggled high and low between
each byte transmitted (see Figure 44).
To protect the transmission from a write collision a
low value on the SS pin of a slave device freezes
the data in its DR register and does not allow it to
be altered. Therefore the SS pin must be high to
write a new data byte in the DR without producing
a write collision.
Figure 45, shows an SPI transfer with the four
combinations of the CPHA and CPOL bits. The di-
agram may be interpreted as a master or slave
timing diagram where the SCK pin, the MISO pin,
the MOSI pin are directly connected between the
master and the slave device.
The SS pin is the slave device select input and can
be driven by the master device.
Figure 44. CPHA / SS Timing Diagram
Byte 3
Byte 2
MOSI/MISO
Master SS
Byte 1
Slave SS
(CPHA=0)
Slave SS
(CPHA=1)
VR02131A
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SERIAL PERIPHERAL INTERFACE (Cont’d)
Figure 45. Data Clock Timing Diagram
CPHA =1
SCLK (with
CPOL = 1)
SCLK (with
CPOL = 0)
Bit 4
Bit 4
Bit3
Bit3
Bit 2
Bit 2
Bit 1
Bit 1
LSBit
LSBit
MSBit
MSBit
Bit 6
Bit 6
Bit 5
Bit 5
MISO
(from master)
MOSI
(from slave)
SS
(to slave)
CAPTURE STROBE
CPHA =0
CPOL = 1
CPOL = 0
Bit 4
Bit 4
Bit3
Bit 2
Bit 2
Bit 1
Bit 1
LSBit
LSBit
MSBit
Bit 6
Bit 6
Bit 5
Bit 5
MISO
(from master)
MSBit
Bit3
MOSI
(from slave)
SS
(to slave)
CAPTURE STROBE
Note: This figure should not be used as a replacement for parametric information.
Refer to the Electrical Characteristics chapter.
VR02131B
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SERIAL PERIPHERAL INTERFACE (Cont’d)
14.4.4.4 Write Collision Error
When the CPHA bit is reset:
A write collision occurs when the software tries to
write to the DR register while a data transfer is tak-
ing place with an external device. When this hap-
pens, the transfer continues uninterrupted; and
the software write will be unsuccessful.
Data is latched on the occurrence of the first clock
transition. The slave device does not have any
way of knowing when that transition will occur;
therefore, the slave device collision occurs when
software attempts to write the DR register after its
SS pin has been pulled low.
Write collisions can occur both in master and slave
mode.
For this reason, the SS pin must be high, between
each data byte transfer, to allow the CPU to write
in the DR register without generating a write colli-
sion.
Note: a "read collision" will never occur since the
received data byte is placed in a buffer in which
access is always synchronous with the MCU oper-
ation.
In Slave mode
In Master mode
When the CPHA bit is set:
Collision in the master device is defined as a write
of the DR register while the internal serial clock
(SCK) is in the process of transfer.
The slave device will receive a clock (SCK) edge
prior to the latch of the first data transfer. This first
clock edge will freeze the data in the slave device
DR register and output the MSBit on to the exter-
nal MISO pin of the slave device.
The SS pin signal must be always high on the
master device.
The SS pin low state enables the slave device but
the output of the MSBit onto the MISO pin does
not take place until the first data transfer clock
edge.
WCOL bit
The WCOL bit in the SR register is set if a write
collision occurs.
No SPI interrupt is generated when the WCOL bit
is set (the WCOL bit is a status flag only).
Clearing the WCOL bit is done through a software
sequence (see Figure 46).
Figure 46. Clearing the WCOL bit (Write Collision Flag) Software Sequence
Clearing sequence after SPIF = 1 (end of a data byte transfer)
Read SR
Read SR
1st Step
2nd Step
OR
THEN
THEN
SPIF =0
WCOL=0
SPIF =0
WCOL=0 if no transfer has started
WCOL=1 if a transfer has started
before the 2nd step
Read DR
Write DR
Clearing sequence before SPIF = 1 (during a data byte transfer)
Read SR
1st Step
THEN
Note: Writing to the DR register
2nd Step
Read DR
instead of reading in it does not
reset the WCOL bit
WCOL=0
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SERIAL PERIPHERAL INTERFACE (Cont’d)
14.4.4.5 Master Mode Fault
may be restored to their original state during or af-
ter this clearing sequence.
Master mode fault occurs when the master device
has its SS pin pulled low, then the MODF bit is set.
Hardware does not allow the user to set the SPE
and MSTR bits while the MODF bit is set except in
the MODF bit clearing sequence.
Master mode fault affects the SPI peripheral in the
following ways:
In a slave device the MODF bit can not be set, but
in a multi master configuration the device can be in
slave mode with this MODF bit set.
– The MODF bit is set and an SPI interrupt is
generated if the SPIE bit is set.
– The SPE bit is reset. This blocks all output
from the device and disables the SPI periph-
eral.
The MODF bit indicates that there might have
been a multi-master conflict for system control and
allows a proper exit from system operation to a re-
set or default system state using an interrupt rou-
tine.
– The MSTR bit is reset, thus forcing the device
into slave mode.
Clearing the MODF bit is done through a software
sequence:
14.4.4.6 Overrun Condition
An overrun condition occurs when the master de-
vice has sent several data bytes and the slave de-
vice has not cleared the SPIF bit issuing from the
previous data byte transmitted.
1. A read or write access to the SR register while
the MODF bit is set.
2. A write to the CR register.
In this case, the receiver buffer contains the byte
sent after the SPIF bit was last cleared. A read to
the DR register returns this byte. All other bytes
are lost.
Notes: To avoid any multiple slave conflicts in the
case of a system comprising several MCUs, the
SS pin must be pulled high during the clearing se-
quence of the MODF bit. The SPE and MSTR bits
This condition is not detected by the SPI peripher-
al.
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SERIAL PERIPHERAL INTERFACE (Cont’d)
14.4.4.7 Single Master and Multimaster Configurations
There are two types of SPI systems:
– Single Master System
For more security, the slave device may respond
to the master with the received data byte. Then the
master will receive the previous byte back from the
slave device if all MISO and MOSI pins are con-
nected and the slave has not written its DR regis-
ter.
– Multimaster System
Single Master System
Other transmission security methods can use
ports for handshake lines or data bytes with com-
mand fields.
A typical single master system may be configured,
using an MCU as the master and four MCUs as
slaves (see Figure 47).
Multi-master System
The master device selects the individual slave de-
vices by using four pins of a parallel port to control
the four SS pins of the slave devices.
A multi-master system may also be configured by
the user. Transfer of master control could be im-
plemented using a handshake method through the
I/O ports or by an exchange of code messages
through the serial peripheral interface system.
The SS pins are pulled high during reset since the
master device ports will be forced to be inputs at
that time, thus disabling the slave devices.
The multi-master system is principally handled by
the MSTR bit in the CR register and the MODF bit
in the SR register.
Note: To prevent a bus conflict on the MISO line
the master allows only one active slave device
during a transmission.
Figure 47. Single Master Configuration
SS
SS
SS
SS
SCK
Slave
MCU
SCK
Slave
MCU
SCK
Slave
SCK
Slave
MCU
MCU
MISO
MOSI MISO
MOSI MISO
MOSI MISO
MOSI
MOSI MISO
SCK
Master
MCU
5V
SS
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SERIAL PERIPHERAL INTERFACE (Cont’d)
14.4.5 Low Power Modes
Mode
Description
No effect on SPI.
WAIT
SPI interrupt events cause the device to exit from WAIT mode.
SPI registers are frozen.
HALT
In HALT mode, the SPI is inactive. SPI operation resumes when the MCU is woken up by an interrupt with
“exit from HALT mode” capability.
14.4.6 Interrupts
Enable
Control from
Bit
Exit
Exit
from
Halt
Event
Flag
Interrupt Event
Wait
Yes
Yes
SPI End of Transfer Event
Master Mode Fault Event
SPIF
No
No
SPIE
MODF
Note: The SPI interrupt events are connected to
the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding
Enable Control Bit is set and the interrupt mask in
the CC register is reset (RIM instruction).
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SERIAL PERIPHERAL INTERFACE (Cont’d)
14.4.7 Register Description
CONTROL REGISTER (CR)
Read/Write
Bit 3 = CPOL Clock polarity.
This bit is set and cleared by software. This bit de-
termines the steady state of the serial Clock. The
CPOL bit affects both the master and slave
modes.
0: The steady state is a low value at the SCK pin.
1: The steady state is a high value at the SCK pin.
Reset Value: 0000xxxx (0xh)
7
0
SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0
Bit 7 = SPIE Serial peripheral interrupt enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SPI interrupt is generated whenever SPIF=1
or MODF=1 in the SR register
Bit 2 = CPHA Clock phase.
This bit is set and cleared by software.
0: The first clock transition is the first data capture
edge.
1: The second clock transition is the first capture
edge.
Bit 6 = SPE Serial peripheral output enable.
This bit is set and cleared by software. It is also
cleared by hardware when, in master mode, SS=0
(see Section 14.4.4.5 "Master Mode Fault" on
page 79).
0: I/O port connected to pins
1: SPI alternate functions connected to pins
Bit 1:0 = SPR[1:0] Serial peripheral rate.
These bits are set and cleared by software.Used
with the SPR2 bit, they select one of six baud rates
to be used as the serial clock when the device is a
master.
The SPE bit is cleared by reset, so the SPI periph-
eral is not initially connected to the external pins.
These 2 bits have no effect in slave mode.
Table 16. Serial Peripheral Baud Rate
Bit 5 = SPR2 Divider Enable.
Serial Clock
SPR2 SPR1 SPR0
this bit is set and cleared by software and it is
cleared by reset. It is used with the SPR[1:0] bits to
set the baud rate. Refer to Table 16.
0: Divider by 2 enabled
f
f
/4
/8
1
0
0
1
0
0
0
0
0
1
1
1
0
0
1
0
0
1
CPU
CPU
f
f
f
/16
/32
/64
CPU
CPU
CPU
1: Divider by 2 disabled
f
/128
CPU
Bit 4 = MSTR Master.
This bit is set and cleared by software. It is also
cleared by hardware when, in master mode, SS=0
(see Section 14.4.4.5 "Master Mode Fault" on
page 79).
0: Slave mode is selected
1: Master mode is selected, the function of the
SCK pin changes from an input to an output and
the functions of the MISO and MOSI pins are re-
versed.
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SERIAL PERIPHERAL INTERFACE (Cont’d)
STATUS REGISTER (SR)
Read Only
DATA I/O REGISTER (DR)
Read/Write
Reset Value: 0000 0000 (00h)
Reset Value: Undefined
7
0
-
7
0
SPIF
WCOL
-
MODF
-
-
-
D7
D6
D5
D4
D3
D2
D1
D0
Bit 7 = SPIF Serial Peripheral data transfer flag.
This bit is set by hardware when a transfer has
been completed. An interrupt is generated if
SPIE=1 in the CR register. It is cleared by a soft-
ware sequence (an access to the SR register fol-
lowed by a read or write to the DR register).
0: Data transfer is in progress or has been ap-
proved by a clearing sequence.
The DR register is used to transmit and receive
data on the serial bus. In the master device only a
write to this register will initiate transmission/re-
ception of another byte.
Notes: During the last clock cycle the SPIF bit is
set, a copy of the received data byte in the shift
register is moved to a buffer. When the user reads
the serial peripheral data I/O register, the buffer is
actually being read.
1: Data transfer between the device and an exter-
nal device has been completed.
Warning:
Note: While the SPIF bit is set, all writes to the DR
register are inhibited.
A write to the DR register places data directly into
the shift register for transmission.
A read to the the DR register returns the value lo-
cated in the buffer and not the contents of the shift
register (See Figure 43 ).
Bit 6 = WCOL Write Collision status.
This bit is set by hardware when a write to the DR
register is done during a transmit sequence. It is
cleared by a software sequence (see Figure 46).
0: No write collision occurred
1: A write collision has been detected
Bit 5 = Unused.
Bit 4 = MODF Mode Fault flag.
This bit is set by hardware when the SS pin is
pulled low in master mode (see Section 14.4.4.5
"Master Mode Fault" on page 79). An SPI interrupt
can be generated if SPIE=1 in the CR register.
This bit is cleared by a software sequence (An ac-
cess to the SR register while MODF=1 followed by
a write to the CR register).
0: No master mode fault detected
1: A fault in master mode has been detected
Bits 3-0 = Unused.
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SERIAL PERIPHERAL INTERFACE (Cont’d)
Table 17. SPI Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
SPIDR
Reset Value
MSB
x
LSB
x
0021h
0022h
0023h
x
x
x
x
x
x
SPICR
Reset Value
SPIE
0
SPE
0
SPR2
0
MSTR
0
CPOL
x
CPHA
x
SPR1
x
SPR0
x
SPISR
Reset Value
SPIF
0
WCOL
0
MODF
0
0
0
0
0
0
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14.5.3 General Description
14.5 SERIAL COMMUNICATIONS INTERFACE (SCI)
14.5.1 Introduction
The Serial Communications Interface (SCI) offers
a flexible means of full-duplex data exchange with
external equipment requiring an industry standard
NRZ asynchronous
The interface is externally connected to another
device by two pins (see Figure 2.):
– TDO: Transmit Data Output. When the transmit-
ter is disabled, the output pin returns to its I/O
port configuration. When the transmitter is ena-
bled and nothing is to be transmitted, the TDO
pin is at high level.
serial data format. The SCI offers a very wide
range of baud rates using two baud rate generator
systems.
14.5.2 Main Features
– RDI: Receive Data Input is the serial data input.
Oversampling techniques are used for data re-
covery by discriminating between valid incoming
data and noise.
■ Full duplex, asynchronous communications
■ NRZ standard format (Mark/Space)
■ Dual baud rate generator systems
Through this pins, serial data is transmitted and re-
ceived as frames comprising:
■ Independently programmable transmit and
receive baud rates up to 250K baud using
conventional baud rate generator and up to
500K baud using the extended baud rate
generator.
– An Idle Line prior to transmission or reception
– A start bit
– A data word (8 or 9 bits) least significant bit first
– A Stop bit indicating that the frame is complete.
Thisinterfaceusestwotypesofbaudrategenerator:
■ Programmable data word length (8 or 9 bits)
■ Receive buffer full, Transmit buffer empty and
End of Transmission flags
– A conventional type for commonly-used baud
rates,
■ Two receiver wake-up modes:
– Address bit (MSB)
– An extended type with a prescaler offering a very
wide range of baud rates even with non-standard
oscillator frequencies.
– Idle line
■ Mutingfunctionformultiprocessorconfigurations
■ LIN compatible (if MCU clock frequency
tolerance ≤2%)
14.5.4 LIN Protocol support
For LIN applications where resynchronization is
not required (application clock tolerance less than
or equal to 2%) the LIN protocol can be efficiently
implemented with this standard SCI.
■ Separate enable bits for Transmitter and
Receiver
■ Three error detection flags:
– Overrun error
– Noise error
– Frame error
■ Five interrupt sources with flags:
– Transmit data register empty
– Transmission complete
– Receive data register full
– Idle line received
– Overrun error detected
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SERIAL COMMUNICATIONS INTERFACE (Cont’d)
Figure 48. SCI Block Diagram
Write
Read
(DATA REGISTER) DR
Received Data Register (RDR)
Received Shift Register
Transmit Data Register (TDR)
TDO
Transmit Shift Register
RDI
CR1
-
R8
-
T8
M
WAKE
-
-
WAKE
UP
TRANSMIT
RECEIVER
CLOCK
RECEIVER
CONTROL
CONTROL
UNIT
SR
CR2
TIE TCIE RIE ILIE TE RE RWU SBK
TDRE
RDRF
IDLE OR NF FE
TC
-
SCI
INTERRUPT
CONTROL
TRANSMITTER
CLOCK
TRANSMITTER RATE
CONTROL
f
CPU
/2
/PR
/16
BRR
SCP1SCP0 SCT2
SCT1SCT0SCR2 SCR1SCR0
RECEIVER RATE
CONTROL
CONVENTIONAL BAUD RATE GENERATOR
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14.5.5.1 Serial Data Format
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
14.5.5 Functional Description
The block diagram of the Serial Control Interface,
is shown in Figure 1.. It contains 6 dedicated reg-
isters:
Word length may be selected as being either 8 or 9
bits by programming the M bit in the CR1 register
(see Figure 1.).
– Two control registers (CR1 & CR2)
– A status register (SR)
The TDO pin is in low state during the start bit.
The TDO pin is in high state during the stop bit.
– A baud rate register (BRR)
An Idle character is interpreted as an entire frame
of “1”s followed by the start bit of the next frame
which contains data.
– An extended prescaler receiver register (ERPR)
–Anextendedprescalertransmitterregister(ETPR)
A Break character is interpreted on receiving “0”s
for some multiple of the frame period. At the end of
the last break frame the transmitter inserts an ex-
tra “1” bit to acknowledge the start bit.
Refer to the register descriptions in Section 0.1.8
for the definitions of each bit.
Transmission and reception are driven by their
own baud rate generator.
Figure 49. Word length programming
9-bit Word length (M bit is set)
Possible
Next Data Frame
Parity
Data Frame
Start
Bit
Next
Start
Bit
Stop
Bit
Bit2
Bit6
Bit1
Bit3
Bit5
Bit8
Bit0
Bit4
Bit7
Bit
Start
Bit
Idle Frame
Start
Bit
Extra
’1’
Break Frame
8-bit Word length (M bit is reset)
Possible
Parity
Next Data Frame
Data Frame
Start
Bit
Next
Start
Bit
Stop
Bit
Bit2
Bit1
Bit3
Bit5
Bit6
Bit0
Bit4
Bit7
Bit
Start
Bit
Idle Frame
Start
Bit
Extra
’1’
Break Frame
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SERIAL COMMUNICATIONS INTERFACE (Cont’d)
14.5.5.2 Transmitter
When a frame transmission is complete (after the
stop bit or after the break frame) the TC bit is set
and an interrupt is generated if the TCIE is set and
the I bit is cleared in the CCR register.
The transmitter can send data words of either 8 or
9 bits depending on the M bit status. When the M
bit is set, word length is 9 bits and the 9th bit (the
MSB) has to be stored in the T8 bit in the CR1 reg-
ister.
Clearing the TC bit is performed by the following
software sequence:
1. An access to the SR register
2. A write to the DR register
Character Transmission
During an SCI transmission, data shifts out least
significant bit first on the TDO pin. In this mode,
the DR register consists of a buffer (TDR) between
the internal bus and the transmit shift register (see
Figure 1.).
Note: The TDRE and TC bits are cleared by the
same software sequence.
Break Characters
Setting the SBK bit loads the shift register with a
break character. The break frame length depends
on the M bit (see Figure 2.).
Procedure
– Select the M bit to define the word length.
As long as the SBK bit is set, the SCI send break
frames to the TDO pin. After clearing this bit by
software the SCI insert a logic 1 bit at the end of
the last break frame to guarantee the recognition
of the start bit of the next frame.
– Select the desired baud rate using the BRR and
the ETPR registers.
– Set the TE bit to assign the TDO pin to the alter-
nate function and to send a idle frame as first
transmission.
Idle Characters
– Access the SR register and write the data to
send in the DR register (this sequence clears the
TDRE bit). Repeat this sequence for each data to
be transmitted.
Setting the TE bit drives the SCI to send an idle
frame before the first data frame.
Clearing and then setting the TE bit during a trans-
mission sends an idle frame after the current word.
Clearing the TDRE bit is always performed by the
following software sequence:
1. An access to the SR register
Note: Resetting and setting the TE bit causes the
data in the TDR register to be lost. Therefore the
best time to toggle the TE bit is when the TDRE bit
is set i.e. before writing the next byte in the DR.
2. A write to the DR register
The TDRE bit is set by hardware and it indicates:
– The TDR register is empty.
– The data transfer is beginning.
– The next data can be written in the DR register
without overwriting the previous data.
This flag generates an interrupt if the TIE bit is set
and the I bit is cleared in the CCR register.
When a transmission is taking place, a write in-
struction to the DR register stores the data in the
TDR register and which is copied in the shift regis-
ter at the end of the current transmission.
When no transmission is taking place, a write in-
struction to the DR register places the data directly
in the shift register, the data transmission starts,
and the TDRE bit is immediately set.
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SERIAL COMMUNICATIONS INTERFACE (Cont’d)
14.5.5.3 Receiver
Overrun Error
The SCI can receive data words of either 8 or 9
bits. When the M bit is set, word length is 9 bits
and the MSB is stored in the R8 bit in the CR1 reg-
ister.
An overrun error occurs when a character is re-
ceived when RDRF has not been reset. Data can
not be transferred from the shift register to the
TDR register as long as the RDRF bit is not
cleared.
Character reception
When a overrun error occurs:
– The OR bit is set.
During a SCI reception, data shifts in least signifi-
cant bit first through the RDI pin. In this mode, DR
register consists in a buffer (RDR) between the in-
ternal bus and the received shift register (see Fig-
ure 1.).
– The RDR content will not be lost.
– The shift register will be overwritten.
– An interrupt is generated if the RIE bit is set and
the I bit is cleared in the CCR register.
Procedure
– Select the M bit to define the word length.
The OR bit is reset by an access to the SR register
followed by a DR register read operation.
– Select the desired baud rate using the BRR and
the ERPR registers.
Noise Error
– Set the RE bit, this enables the receiver which
begins searching for a start bit.
Oversampling techniques are used for data recov-
ery by discriminating between valid incoming data
and noise.
When a character is received:
– The RDRF bit is set. It indicates that the content
of the shift register is transferred to the RDR.
When noise is detected in a frame:
– The NF is set at the rising edge of the RDRF bit.
– An interrupt is generated if the RIE bit is set and
the I bit is cleared in the CCR register.
– Data is transferred from the Shift register to the
DR register.
– The error flags can be set if a frame error, noise
or an overrun error has been detected during re-
ception.
– No interrupt is generated. However this bit rises
at the same time as the RDRF bit which itself
generates an interrupt.
Clearing the RDRF bit is performed by the following
software sequence done by:
The NF bit is reset by a SR register read operation
followed by a DR register read operation.
1. An access to the SR register
2. A read to the DR register.
Framing Error
A framing error is detected when:
The RDRF bit must be cleared before the end of the
reception of the next character to avoid an overrun
error.
– The stop bit is not recognized on reception at the
expected time, following either a de-synchroni-
zation or excessive noise.
Break Character
– A break is received.
When a break character is received, the SCI han-
dles it as a framing error.
When the framing error is detected:
– the FE bit is set by hardware
Idle Character
– Data is transferred from the Shift register to the
DR register.
When a idle frame is detected, there is the same
procedure as a data received character plus an in-
terrupt if the ILIE bit is set and the I bit is cleared in
the CCR register.
– No interrupt is generated. However this bit rises
at the same time as the RDRF bit which itself
generates an interrupt.
The FE bit is reset by a SR register read operation
followed by a DR register read operation.
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SERIAL COMMUNICATIONS INTERFACE (Cont’d)
Figure 50. SCI Baud Rate and Extended Prescaler Block Diagram
EXTENDED PRESCALER TRANSMITTER RATE CONTROL
ETPR
EXTENDED TRANSMITTER PRESCALER REGISTER
ERPR
EXTENDED RECEIVER PRESCALER REGISTER
EXTENDED PRESCALER RECEIVER RATE CONTROL
EXTENDED PRESCALER
f
TRANSMITTER
CLOCK
CPU
TRANSMITTER RATE
CONTROL
/PR
/2
/16
BRR
SCP1
SCT2
SCT1SCT0SCR2 SCR1SCR0
SCP0
RECEIVER
CLOCK
RECEIVER RATE
CONTROL
CONVENTIONAL BAUD RATE GENERATOR
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SERIAL COMMUNICATIONS INTERFACE (Cont’d)
14.5.5.4 Conventional Baud Rate Generation
than zero. The baud rates are calculated as fol-
lows:
The baud rate for the receiver and transmitter (Rx
and Tx) are set independently and calculated as
follows:
f
f
CPU
CPU
Rx =
Tx =
f
f
16 ERPR
16 ETPR
CPU
CPU
*
*
Rx =
Tx =
(32 PR) RR
(32 PR) TR
*
*
*
*
with:
with:
ETPR = 1,..,255 (see ETPR register)
PR = 1, 3, 4 or 13 (see SCP0 & SCP1 bits)
TR = 1, 2, 4, 8, 16, 32, 64,128
ERPR = 1,.. 255 (see ERPR register)
14.5.5.6 Receiver Muting and Wake-up Feature
(see SCT0, SCT1 & SCT2 bits)
RR = 1, 2, 4, 8, 16, 32, 64,128
In multiprocessor configurations it is often desira-
ble that only the intended message recipient
should actively receive the full message contents,
thus reducing redundant SCI service overhead for
all non addressed receivers.
(see SCR0,SCR1 & SCR2 bits)
All this bits are in the BRR register.
Example: If f
PR=13 and TR=RR=1, the transmit and receive
baud rates are 19200 baud.
is 8 MHz (normal mode) and if
CPU
The non addressed devices may be placed in
sleep mode by means of the muting function.
Setting the RWU bit by software puts the SCI in
sleep mode:
Caution: The baud rate register (SCIBRR) MUST
NOT be written to (changed or refreshed) while the
transmitter or the receiver is enabled.
All the reception status bits can not be set.
All the receive interrupt are inhibited.
14.5.5.5 Extended Baud Rate Generation
A muted receiver may be awakened by one of the
following two ways:
The extended prescaler option gives a very fine
tuning on the baud rate, using a 255 value prescal-
er, whereas the conventional Baud Rate Genera-
tor retains industry standard software compatibili-
ty.
– by Idle Line detection if the WAKE bit is reset,
– by Address Mark detection if the WAKE bit is set.
Receiver wakes-up by Idle Line detection when
the Receive line has recognised an Idle Frame.
Then the RWU bit is reset by hardware but the
IDLE bit is not set.
The extended baud rate generator block diagram
is described in the Figure 3..
The output clock rate sent to the transmitter or to
the receiver will be the output from the 16 divider
divided by a factor ranging from 1 to 255 set in the
ERPR or the ETPR register.
Receiver wakes-up by Address Mark detection
when it received a “1” as the most significant bit of
a word, thus indicating that the message is an ad-
dress. The reception of this particular word wakes
up the receiver, resets the RWU bit and sets the
RDRF bit, which allows the receiver to receive this
word normally and to use it as an address word.
Note: the extended prescaler is activated by set-
ting the ETPR or ERPR register to a value other
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SERIAL COMMUNICATIONS INTERFACE (Cont’d)
14.5.6 Low Power Modes
Mode
Description
No effect on SCI.
WAIT
SCI interrupts cause the device to exit from Wait mode.
SCI registers are frozen.
HALT
In Halt mode, the SCI stops transmitting/receiving until Halt mode is exited.
14.5.7 Interrupts
Enable
Control from
Bit
Exit
Exit
from
Halt
Event
Flag
Interrupt Event
Wait
Yes
Yes
Yes
Yes
Yes
Transmit Data Register Empty
Transmission Complete
TDRE
TC
TIE
No
No
No
No
No
TCIE
Received Data Ready to be Read
Overrrun Error Detected
Idle Line Detected
RDRF
OR
RIE
ILIE
IDLE
The SCI interrupt events are connected to the
same interrupt vector (see Interrupts chapter).
These events generate an interrupt if the corre-
sponding Enable Control Bit is set and the inter-
rupt mask in the CC register is reset (RIM instruc-
tion).
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SERIAL COMMUNICATIONS INTERFACE (Cont’d)
14.5.8 Register Description
STATUS REGISTER (SR)
Note: The IDLE bit will not be set again until the
RDRF bit has been set itself (i.e. a new idle line oc-
curs). This bit is not set by an idle line when the re-
ceiver wakes up from wake-up mode.
Read Only
Reset Value: 1100 0000 (C0h)
Bit 3 = OR Overrun error.
7
0
-
This bit is set by hardware when the word currently
being received in the shift register is ready to be
transferred into the RDR register while RDRF=1.
An interrupt is generated if RIE=1 in the CR2 reg-
ister. It is cleared by a software sequence (an ac-
cess to the SR register followed by a read to the
DR register).
TDRE
TC
RDRF IDLE
OR
NF
FE
Bit 7 = TDRE Transmit data register empty.
This bit is set by hardware when the content of the
TDR register has been transferred into the shift
register. An interrupt is generated if the TIE =1 in
the CR2 register. It is cleared by a software se-
quence (an access to the SR register followed by a
write to the DR register).
0: No Overrun error
1: Overrun error is detected
Note: When this bit is set RDR register content will
not be lost but the shift register will be overwritten.
0: Data is not transferred to the shift register
1: Data is transferred to the shift register
Bit 2 = NF Noise flag.
Note: data will not be transferred to the shift regis-
ter as long as the TDRE bit is not reset.
This bit is set by hardware when noise is detected
on a received frame. It is cleared by a software se-
quence (an access to the SR register followed by a
read to the DR register).
0: No noise is detected
1: Noise is detected
Bit 6 = TC Transmission complete.
This bit is set by hardware when transmission of a
frame containing Data, a Preamble or a Break is
complete. An interrupt is generated if TCIE=1 in
the CR2 register. It is cleared by a software se-
quence (an access to the SR register followed by a
write to the DR register).
Note: This bit does not generate interrupt as it ap-
pears at the same time as the RDRF bit which it-
self generates an interrupt.
0: Transmission is not complete
1: Transmission is complete
Bit 1 = FE Framing error.
This bit is set by hardware when a de-synchroniza-
tion, excessive noise or a break character is de-
tected. It is cleared by a software sequence (an
access to the SR register followed by a read to the
DR register).
0: No Framing error is detected
1: Framing error or break character is detected
Bit 5 = RDRF Received data ready flag.
This bit is set by hardware when the content of the
RDR register has been transferred into the DR
register. An interrupt is generated if RIE=1 in the
CR2 register. It is cleared by a software sequence
(an access to the SR register followed by a read to
the DR register).
Note: This bit does not generate interrupt as it ap-
pears at the same time as the RDRF bit which it-
self generates an interrupt. If the word currently
being transferred causes both frame error and
overrun error, it will be transferred and only the OR
bit will be set.
0: Data is not received
1: Received data is ready to be read
Bit 4 = IDLE Idle line detect.
This bit is set by hardware when a Idle Line is de-
tected. An interrupt is generated if the ILIE=1 in
the CR2 register. It is cleared by a software se-
quence (an access to the SR register followed by a
read to the DR register).
Bit 0 = Unused.
0: No Idle Line is detected
1: Idle Line is detected
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SERIAL COMMUNICATIONS INTERFACE (Cont’d)
CONTROL REGISTER 1 (CR1)
Read/Write
1: An SCI interrupt is generated whenever TC=1 in
the SR register
Reset Value: Undefined
Bit 5 = RIE Receiver interrupt enable.
This bit is set and cleared by software.
0: interrupt is inhibited
1: An SCI interrupt is generated whenever OR=1
or RDRF=1 in the SR register
7
0
-
R8
T8
-
M
WAKE
-
-
Bit 7 = R8 Receive data bit 8.
This bit is used to store the 9th bit of the received
word when M=1.
Bit 4 = ILIE Idle line interrupt enable.
This bit is set and cleared by software.
0: interrupt is inhibited
1: An SCI interrupt is generated whenever IDLE=1
in the SR register.
Bit 6 = T8 Transmit data bit 8.
This bit is used to store the 9th bit of the transmit-
ted word when M=1.
Bit 3 = TE Transmitter enable.
This bit enables the transmitter and assigns the
TDO pin to the alternate function. It is set and
cleared by software.
0: Transmitter is disabled, the TDO pin is back to
the I/O port configuration.
Bit 4 = M Word length.
This bit determines the word length. It is set or
cleared by software.
0: 1 Start bit, 8 Data bits, 1 Stop bit
1: 1 Start bit, 9 Data bits, 1 Stop bit
1: Transmitter is enabled
Note: during transmission, a “0” pulse on the TE
bit (“0” followed by “1”) sends a preamble after the
current word.
Bit 3 = WAKE Wake-Up method.
This bit determines the SCI Wake-Up method, it is
set or cleared by software.
0: Idle Line
Bit 2 = RE Receiver enable.
This bit enables the receiver. It is set and cleared
by software.
1: Address Mark
0: Receiver is disabled.
1: Receiver is enabled and begins searching for a
start bit.
CONTROL REGISTER 2 (CR2)
Read/Write
Reset Value: 0000 0000 (00h)
Bit 1 = RWU Receiver wake-up.
7
0
This bit determines if the SCI is in mute mode or
not. It is set and cleared by software and can be
cleared by hardware when a wake-up sequence is
recognized.
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
0: Receiver in active mode
1: Receiver in mute mode
Bit 7 = TIE Transmitter interrupt enable.
This bit is set and cleared by software.
0: interrupt is inhibited
1: An SCI interrupt is generated whenever
TDRE=1 in the SR register.
Bit 0 = SBK Send break.
This bit set is used to send break characters. It is
set and cleared by software.
0: No break character is transmitted
1: Break characters are transmitted
Bit 6 = TCIE Transmission complete interrupt ena-
ble
Note: If the SBK bit is set to “1” and then to “0”, the
transmitter will send a BREAK word at the end of
the current word.
This bit is set and cleared by software.
0: interrupt is inhibited
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SERIAL COMMUNICATIONS INTERFACE (Cont’d)
DATA REGISTER (DR)
Bit 5:3 = SCT[2:0] SCI Transmitter rate divisor
Read/Write
These 3 bits, in conjunction with the SCP1 & SCP0
bits define the total division applied to the bus
clock to yield the transmit rate clock in convention-
al Baud Rate Generator mode.
Reset Value: Undefined
Contains the Received or Transmitted data char-
acter, depending on whether it is read from or writ-
ten to.
TR dividing factor
SCT2
SCT1
SCT0
1
2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
7
0
4
DR7
DR6
DR5
DR4
DR3
DR2
DR1
DR0
8
The Data register performs a double function (read
and write) since it is composed of two registers,
one for transmission (TDR) and one for reception
(RDR).
The TDR register provides the parallel interface
between the internal bus and the output shift reg-
ister (see Figure 1.).
The RDR register provides the parallel interface
between the input shift register and the internal
bus (see Figure 1.).
16
32
64
128
Note: this TR factor is used only when the ETPR
fine tuning factor is equal to 00h; otherwise, TR is
replaced by the ETPR dividing factor.
Bit 2:0 = SCR[2:0] SCI Receiver rate divisor.
BAUD RATE REGISTER (BRR)
Read/Write
These 3 bits, in conjunction with the SCP1 & SCP0
bits define the total division applied to the bus
clock to yield the receive rate clock in conventional
Baud Rate Generator mode.
Reset Value: 00xx xxxx (XXh)
7
0
RR dividing factor
SCR2
SCR1
SCR0
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0
1
2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Bit 7:6= SCP[1:0] First SCI Prescaler
These 2 prescaling bits allow several standard
clock division ranges:
4
8
16
32
64
128
PR Prescaling factor
SCP1
SCP0
1
3
0
0
1
1
0
1
0
1
4
13
Note: this RR factor is used only when the ERPR
fine tuning factor is equal to 00h; otherwise, RR is
replaced by the ERPR dividing factor.
95/153
ST72334J/N, ST72314J/N, ST72124J
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
EXTENDED RECEIVE PRESCALER DIVISION
REGISTER (ERPR)
EXTENDED TRANSMIT PRESCALER DIVISION
REGISTER (ETPR)
Read/Write
Read/Write
Reset Value: 0000 0000 (00h)
Reset Value:0000 0000 (00h)
Allows setting of the Extended Prescaler rate divi-
sion factor for the receive circuit.
Allows setting of the External Prescaler rate divi-
sion factor for the transmit circuit.
7
0
7
0
ERPR ERPR ERPR ERPR ERPR ERPR ERPR ERPR
ETPR ETPR ETPR ETPR ETPR ETPR ETPR ETPR
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Bit 7:1 = ERPR[7:0] 8-bit Extended Receive Pres-
caler Register.
Bit 7:1 = ETPR[7:0] 8-bit Extended Transmit Pres-
caler Register.
The extended Baud Rate Generator is activated
when a value different from 00h is stored in this
register. Therefore the clock frequency issued
from the 16 divider (see Figure 3.) is divided by the
binary factor set in the ERPR register (in the range
1 to 255).
The extended Baud Rate Generator is activated
when a value different from 00h is stored in this
register. Therefore the clock frequency issued
from the 16 divider (see Figure 3.) is divided by the
binary factor set in the ETPR register (in the range
1 to 255).
The extended baud rate generator is not used af-
ter a reset.
The extended baud rate generator is not used af-
ter a reset.
Table 18. SCI Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
SCISR
Reset Value
TDRE
1
TC
1
RDRF
0
IDLE
0
OR
0
NF
0
FE
0
0050h
0051h
0052h
0053h
0054h
0055h
0057h
0
SCIDR
Reset Value
MSB
x
LSB
x
x
x
x
x
x
x
SCIBRR
Reset Value
SOG
0
VPOL
x
2FHDET HVSEL VCORDIS CLPINV
BLKINV
x
0
x
x
x
x
SCICR1
Reset Value
R8
x
T8
x
M
x
WAKE
x
0
0
0
0
SCICR2
Reset Value
TIE
0
TCIE
0
RIE
0
ILIE
0
TE
0
RE
0
RWU
0
SBK
0
SCIPBRR
Reset Value
MSB
0
LSB
0
0
0
0
0
0
0
0
0
0
0
0
0
SCIPBRT
Reset Value
MSB
0
LSB
0
96/153
ST72334J/N, ST72314J/N, ST72124J
14.6 8-BIT A/D CONVERTER (ADC)
14.6.1 Introduction
14.6.3 Functional Description
14.6.3.1 Analog Power Supply
The on-chip Analog to Digital Converter (ADC) pe-
ripheral is a 8-bit, successive approximation con-
verter with internal sample and hold circuitry. This
peripheral has up to 16 multiplexed analog input
channels (refer to device pin out description) that
allow the peripheral to convert the analog voltage
levels from up to 16 different sources.
V
and V
are the high and low level refer-
SSA
DDA
ence voltage pins. In some devices (refer to device
pin out description) they are internally connected
to the V and V pins.
DD
SS
Conversion accuracy may therefore be impacted
by voltage drops and noise in the event of heavily
loaded or badly decoupled power supply lines.
The result of the conversion is stored in a 8-bit
Data Register. The A/D converter is controlled
through a Control/Status Register.
See electrical characteristics section for more de-
tails.
14.6.2 Main Features
■ 8-bit conversion
■ Up to 16 channels with multiplexed input
■ Linear successive approximation
■ Data register (DR) which contains the results
■ Conversion complete status flag
■ On/off bit (to reduce consumption)
The block diagram is shown in Figure 51.
Figure 51. ADC Block Diagram
f
f
ADC
CPU
DIV 2
COCO
0
ADON
4
0
CH3 CH2 CH1 CH0
ADCCSR
AIN0
AIN1
HOLD CONTROL
R
ADC
ANALOG TO DIGITAL
CONVERTER
ANALOG
MUX
AINx
C
ADC
ADCDR
D7
D6
D5
D4
D3
D2
D1
D0
97/153
ST72334J/N, ST72314J/N, ST72124J
8-BIT A/D CONVERTER (ADC) (Cont’d)
14.6.3.2 Digital A/D Conversion Result
The analog input ports must be configured as in-
put, no pull-up, no interrupt. Refer to the «I/O
ports» chapter. Using these pins as analog inputs
does not affect the ability of the port to be read as
a logic input.
The conversion is monotonic, meaning that the re-
sult never decreases if the analog input does not
and never increases if the analog input does not.
If the input voltage (V ) is greater than or equal
AIN
In the CSR register:
to V
(high-level voltage reference) then the
DDA
conversion result in the DR register is FFh (full
– Select the CH[3:0] bits to assign the analog
channel to be converted.
scale) without overflow indication.
If input voltage (V ) is lower than or equal to
ADC Conversion
AIN
V
(low-level voltage reference) then the con-
SSA
In the CSR register:
version result in the DR register is 00h.
– Set the ADON bit to enable the A/D converter
and to start the first conversion. From this time
on, the ADC performs a continuous conver-
sion of the selected channel.
The A/D converter is linear and the digital result of
the conversion is stored in the ADCDR register.
The accuracy of the conversion is described in the
parametric section.
When a conversion is complete
R
is the maximum recommended impedance
– The COCO bit is set by hardware.
– No interrupt is generated.
– The result is in the DR register and remains
valid until the next conversion has ended.
AIN
for an analog input signal. If the impedance is too
high, this will result in a loss of accuracy due to
leakage and sampling not being completed in the
alloted time.
A write to the CSR register (with ADON set) aborts
the current conversion, resets the COCO bit and
starts a new conversion.
14.6.3.3 A/D Conversion Phases
The A/D conversion is based on two conversion
phases as shown in Figure 52:
■ Sample capacitor loading [duration: t
Figure 52. ADC Conversion Timings
]
LOAD
During this phase, the V
measured is loaded into the C
input voltage to be
AIN
ADON
sample
ADC
ADCCSR WRITE
OPERATION
t
CONV
capacitor.
■ A/D conversion [duration: t
]
CONV
During this phase, the A/D conversion is
computed (8 successive approximations cycles)
HOLD
CONTROL
and the C
sample capacitor is disconnected
ADC
from the analog input pin to get the optimum
t
LOAD
COCO BIT SET
analog to digital conversion accuracy.
While the ADC is on, these two phases are contin-
uously repeated.
14.6.4 Low Power Modes
At the end of each conversion, the sample capaci-
tor is kept loaded with the previous measurement
load. The advantage of this behaviour is that it
minimizes the current consumption on the analog
pin in case of single input channel measurement.
Mode
WAIT
Description
No effect on A/D Converter
A/D Converter disabled.
After wakeup from Halt mode, the A/D Con-
verter requires a stabilisation time before ac-
curate conversions can be performed.
HALT
14.6.3.4 Software Procedure
Refer to the control/status register (CSR) and data
register (DR) in Section 14.6.6 for the bit defini-
tions and to Figure 52 for the timings.
Note: The A/D converter may be disabled by reset-
ting the ADON bit. This feature allows reduced
power consumption when no conversion is needed
and between single shot conversions.
ADC Configuration
The total duration of the A/D conversion is 12 ADC
14.6.5 Interrupts
clock periods (1/f
=2/f
).
ADC
CPU
None
98/153
ST72334J/N, ST72314J/N, ST72124J
8-BIT A/D CONVERTER (ADC) (Cont’d)
14.6.6 Register Description
CONTROL/STATUS REGISTER (CSR)
Read/Write
DATA REGISTER (DR)
Read Only
Reset Value: 0000 0000 (00h)
Reset Value: 0000 0000 (00h)
7
0
7
0
COCO
0
ADON
0
CH3
CH2
CH1
CH0
D7
D6
D5
D4
D3
D2
D1
D0
Bit 7 = COCO Conversion Complete
This bit is set by hardware. It is cleared by soft-
ware reading the result in the DR register or writing
to the CSR register.
0: Conversion is not complete
1: Conversion can be read from the DR register
Bits 7:0 = D[7:0] Analog Converted Value
This register contains the converted analog value
in the range 00h to FFh.
Note: Reading this register reset the COCO flag.
Bit 6 = Reserved. must always be cleared.
Bit 5 = ADON A/D Converter On
This bit is set and cleared by software.
0: A/D converter is switched off
1: A/D converter is switched on
Bit 4 = Reserved. must always be cleared.
Bits 3:0 = CH[3:0] Channel Selection
These bits are set and cleared by software. They
select the analog input to convert.
Channel Pin*
CH3 CH2 CH1 CH0
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
AIN9
AIN10
AIN11
AIN12
AIN13
AIN14
AIN15
*Note: The number of pins AND the channel selec-
tion varies according to the device. Refer to the de-
vice pinout.
99/153
ST72334J/N, ST72314J/N, ST72124J
8-BIT A/D CONVERTER (ADC) (Cont’d)
Table 19. ADC Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
ADCDR
Reset Value
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
0070h
0071h
ADCCSR
Reset Value
COCO
0
ADON
0
CH3
0
CH2
0
CH1
0
CH0
0
0
0
100/153
ST72334J/N, ST72314J/N, ST72124J
15 INSTRUCTION SET
15.1 ST7 ADDRESSING MODES
so, most of the addressing modes may be subdi-
vided in two sub-modes called long and short:
The ST7 Core features 17 different addressing
modes which can be classified in 7 main groups:
– Long addressing mode is more powerful be-
cause it can use the full 64 Kbyte address space,
however it uses more bytes and more CPU cy-
cles.
Addressing Mode
Inherent
Example
nop
– Short addressing mode is less powerful because
it can generally only access page zero (0000h -
00FFh range), but the instruction size is more
compact, and faster. All memory to memory in-
structions use short addressing modes only
(CLR, CPL, NEG, BSET, BRES, BTJT, BTJF,
INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP)
Immediate
Direct
ld A,#$55
ld A,$55
Indexed
ld A,($55,X)
ld A,([$55],X)
jrne loop
Indirect
Relative
Bit operation
bset byte,#5
The ST7 Assembler optimizes the use of long and
short addressing modes.
The ST7 Instruction set is designed to minimize
the number of bytes required per instruction: To do
Table 20. ST7 Addressing Mode Overview
Pointer
Address
(Hex.)
Pointer
Size
(Hex.)
Destination/
Source
Length
(Bytes)
Mode
Syntax
Inherent
Immediate
Short
nop
+ 0
+ 1
+ 1
+ 2
ld A,#$55
ld A,$10
Direct
Direct
00..FF
Long
ld A,$1000
0000..FFFF
+ 0 (with X register)
+ 1 (with Y register)
No Offset
Direct
Indexed
ld A,(X)
00..FF
Short
Long
Short
Long
Short
Long
Relative
Relative
Bit
Direct
Indexed
Indexed
ld A,($10,X)
ld A,($1000,X)
ld A,[$10]
00..1FE
+ 1
+ 2
+ 2
+ 2
+ 2
+ 2
+ 1
+ 2
+ 1
+ 2
+ 2
+ 3
Direct
0000..FFFF
00..FF
Indirect
Indirect
00..FF
00..FF
00..FF
00..FF
byte
word
byte
word
ld A,[$10.w]
ld A,([$10],X)
0000..FFFF
00..1FE
Indirect Indexed
Indirect Indexed
Direct
ld A,([$10.w],X) 0000..FFFF
1)
1)
jrne loop
PC-128/PC+127
Indirect
jrne [$10]
PC-128/PC+127
00..FF
00..FF
00..FF
00..FF
byte
byte
byte
Direct
bset $10,#7
bset [$10],#7
Bit
Indirect
00..FF
Bit
Direct
Relative btjt $10,#7,skip 00..FF
Bit
Indirect Relative btjt [$10],#7,skip 00..FF
Note 1. At the time the instruction is executed, the Program Counter (PC) points to the instruction follow-
ing JRxx.
101/153
ST72334J/N, ST72314J/N, ST72124J
ST7 ADDRESSING MODES (Cont’d)
15.1.1 Inherent
15.1.3 Direct
All Inherent instructions consist of a single byte.
The opcode fully specifies all the required informa-
tion for the CPU to process the operation.
In Direct instructions, the operands are referenced
by their memory address.
The direct addressing mode consists of two sub-
modes:
Inherent Instruction
Function
No operation
Direct (short)
NOP
The address is a byte, thus requires only one byte
after the opcode, but only allows 00 - FF address-
ing space.
TRAP
S/W Interrupt
Wait For Interrupt (Low Power
Mode)
WFI
Direct (long)
Halt Oscillator (Lowest Power
Mode)
HALT
The address is a word, thus allowing 64 Kbyte ad-
dressing space, but requires 2 bytes after the op-
code.
RET
Sub-routine Return
Interrupt Sub-routine Return
Set Interrupt Mask
Reset Interrupt Mask
Set Carry Flag
IRET
SIM
15.1.4 Indexed (No Offset, Short, Long)
RIM
In this mode, the operand is referenced by its
memory address, which is defined by the unsigned
addition of an index register (X or Y) with an offset.
SCF
RCF
Reset Carry Flag
Reset Stack Pointer
Load
The indirect addressing mode consists of three
sub-modes:
RSP
LD
Indexed (No Offset)
CLR
Clear
There is no offset, (no extra byte after the opcode),
and allows 00 - FF addressing space.
PUSH/POP
INC/DEC
TNZ
Push/Pop to/from the stack
Increment/Decrement
Test Negative or Zero
1 or 2 Complement
Byte Multiplication
Indexed (Short)
The offset is a byte, thus requires only one byte af-
ter the opcode and allows 00 - 1FE addressing
space.
CPL, NEG
MUL
Indexed (long)
SLL, SRL, SRA, RLC,
RRC
Shift and Rotate Operations
Swap Nibbles
The offset is a word, thus allowing 64 Kbyte ad-
dressing space and requires 2 bytes after the op-
code.
SWAP
15.1.2 Immediate
Immediate instructions have two bytes, the first
byte contains the opcode, the second byte con-
tains the operand value.
15.1.5 Indirect (Short, Long)
The required data byte to do the operation is found
by its memory address, located in memory (point-
er).
Immediate Instruction
Function
The pointer address follows the opcode. The indi-
rect addressing mode consists of two sub-modes:
LD
Load
CP
Compare
Indirect (short)
BCP
Bit Compare
The pointer address is a byte, the pointer size is a
byte, thus allowing 00 - FF addressing space, and
requires 1 byte after the opcode.
AND, OR, XOR
ADC, ADD, SUB, SBC
Logical Operations
Arithmetic Operations
Indirect (long)
The pointer address is a byte, the pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.
102/153
ST72334J/N, ST72314J/N, ST72124J
ST7 ADDRESSING MODES (Cont’d)
15.1.6 Indirect Indexed (Short, Long)
SWAP
CALL, JP
Swap Nibbles
This is a combination of indirect and short indexed
addressing modes. The operand is referenced by
its memory address, which is defined by the un-
signed addition of an index register value (X or Y)
with a pointer value located in memory. The point-
er address follows the opcode.
Call or Jump subroutine
15.1.7 Relative Mode (Direct, Indirect)
This addressing mode is used to modify the PC
register value by adding an 8-bit signed offset to it.
Available Relative Direct/
Function
The indirect indexed addressing mode consists of
two sub-modes:
Indirect Instructions
JRxx
Conditional Jump
Call Relative
Indirect Indexed (Short)
CALLR
The pointer address is a byte, the pointer size is a
byte, thus allowing 00 - 1FE addressing space,
and requires 1 byte after the opcode.
The relative addressing mode consists of two sub-
modes:
Indirect Indexed (Long)
Relative (Direct)
The pointer address is a byte, the pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.
The offset follows the opcode.
Relative (Indirect)
The offset is defined in memory, of which the ad-
dress follows the opcode.
Table 21. Instructions Supporting Direct,
Indexed, Indirect and Indirect Indexed
Addressing Modes
Long and Short
Function
Instructions
LD
Load
CP
Compare
AND, OR, XOR
Logical Operations
Arithmetic Addition/subtrac-
tion operations
ADC, ADD, SUB, SBC
BCP
Bit Compare
Short Instructions Only
CLR
Function
Clear
INC, DEC
Increment/Decrement
Test Negative or Zero
1 or 2 Complement
Bit Operations
TNZ
CPL, NEG
BSET, BRES
Bit Test and Jump Opera-
tions
BTJT, BTJF
SLL, SRL, SRA, RLC,
RRC
Shift and Rotate Operations
103/153
ST72334J/N, ST72314J/N, ST72124J
15.2 INSTRUCTION GROUPS
The ST7 family devices use an Instruction Set
consisting of 63 instructions. The instructions may
be subdivided into 13 main groups as illustrated in
the following table:
Load and Transfer
LD
CLR
POP
DEC
TNZ
OR
Stack operation
PUSH
INC
RSP
BCP
Increment/Decrement
Compare and Tests
Logical operations
CP
AND
BSET
BTJT
ADC
SLL
XOR
CPL
NEG
Bit Operation
BRES
BTJF
ADD
SRL
JRT
Conditional Bit Test and Branch
Arithmetic operations
Shift and Rotates
SUB
SRA
JRF
SBC
RLC
JP
MUL
RRC
CALL
SWAP
CALLR
SLA
Unconditional Jump or Call
Conditional Branch
JRA
JRxx
TRAP
SIM
NOP
RET
Interruption management
Condition Code Flag modification
WFI
RIM
HALT
SCF
IRET
RCF
Using a pre-byte
The instructions are described with one to four
bytes.
These prebytes enable instruction in Y as well as
indirect addressing modes to be implemented.
They precede the opcode of the instruction in X or
the instruction using direct addressing mode. The
prebytes are:
In order to extend the number of available op-
codes for an 8-bit CPU (256 opcodes), three differ-
ent prebyte opcodes are defined. These prebytes
modify the meaning of the instruction they pre-
cede.
PDY 90 Replace an X based instruction using
immediate, direct, indexed, or inherent
addressing mode by a Y one.
The whole instruction becomes:
PC-2 End of previous instruction
PC-1 Prebyte
PIX 92 Replace an instruction using direct, di-
rect bit, or direct relative addressing
mode to an instruction using the corre-
sponding indirect addressing mode.
It also changes an instruction using X
indexed addressing mode to an instruc-
tion using indirect X indexed addressing
mode.
PC
Opcode
PC+1 Additional word (0 to 2) according to the
number of bytes required to compute the
effective address
PIY 91 Replace an instruction using X indirect
indexed addressing mode by a Y one.
104/153
ST72334J/N, ST72314J/N, ST72124J
INSTRUCTION GROUPS (Cont’d)
Mnemo
ADC
ADD
AND
BCP
Description
Add with Carry
Function/Example
A = A + M + C
A = A + M
Dst
Src
H
H
H
I
N
N
N
N
N
Z
Z
Z
Z
Z
C
C
C
A
M
M
M
M
Addition
A
Logical And
A = A . M
A
Bit compare A, Memory
Bit Reset
tst (A . M)
A
BRES
BSET
BTJF
BTJT
CALL
CALLR
CLR
bres Byte, #3
bset Byte, #3
btjf Byte, #3, Jmp1
btjt Byte, #3, Jmp1
M
M
M
M
Bit Set
Jump if bit is false (0)
Jump if bit is true (1)
Call subroutine
Call subroutine relative
Clear
C
C
reg, M
reg
0
N
N
N
1
Z
Z
Z
CP
Arithmetic Compare
One Complement
Decrement
tst(Reg - M)
A = FFH-A
dec Y
M
C
1
CPL
reg, M
reg, M
DEC
HALT
IRET
INC
Halt
0
I
Interrupt routine return
Increment
Pop CC, A, X, PC
inc X
H
N
N
Z
Z
C
reg, M
JP
Absolute Jump
Jump relative always
Jump relative
jp [TBL.w]
JRA
JRT
JRF
Never jump
jrf *
JRIH
JRIL
Jump if ext. interrupt = 1
Jump if ext. interrupt = 0
Jump if H = 1
JRH
H = 1 ?
JRNH
JRM
Jump if H = 0
H = 0 ?
Jump if I = 1
I = 1 ?
JRNM
JRMI
JRPL
JREQ
JRNE
JRC
Jump if I = 0
I = 0 ?
Jump if N = 1 (minus)
Jump if N = 0 (plus)
Jump if Z = 1 (equal)
Jump if Z = 0 (not equal)
Jump if C = 1
N = 1 ?
N = 0 ?
Z = 1 ?
Z = 0 ?
C = 1 ?
JRNC
JRULT
Jump if C = 0
C = 0 ?
Jump if C = 1
Unsigned <
Jmp if unsigned >=
Unsigned >
JRUGE Jump if C = 0
JRUGT Jump if (C + Z = 0)
105/153
ST72334J/N, ST72314J/N, ST72124J
INSTRUCTION GROUPS (Cont’d)
Mnemo
JRULE
LD
Description
Jump if (C + Z = 1)
Load
Function/Example
Unsigned <=
dst <= src
Dst
Src
H
I
N
N
N
N
N
Z
Z
Z
Z
Z
C
reg, M
A, X, Y
reg, M
M, reg
X, Y, A
MUL
NEG
NOP
OR
Multiply
X,A = X * A
0
0
Negate (2's compl)
No Operation
OR operation
Pop from the Stack
neg $10
C
A = A + M
pop reg
pop CC
push Y
C = 0
A
M
POP
reg
CC
M
M
M
H
I
C
0
PUSH
RCF
RET
RIM
Push onto the Stack
Reset carry flag
Subroutine Return
Enable Interrupts
Rotate left true C
Rotate right true C
Reset Stack Pointer
Subtract with Carry
Set carry flag
reg, CC
I = 0
0
RLC
RRC
RSP
SBC
SCF
SIM
C <= Dst <= C
C => Dst => C
S = Max allowed
A = A - M - C
C = 1
reg, M
reg, M
N
N
Z
Z
C
C
A
M
N
Z
C
1
Disable Interrupts
Shift left Arithmetic
Shift left Logic
I = 1
1
SLA
C <= Dst <= 0
C <= Dst <= 0
0 => Dst => C
Dst7 => Dst => C
A = A - M
reg, M
reg, M
reg, M
reg, M
A
N
N
0
Z
Z
Z
Z
Z
Z
Z
C
C
C
C
C
SLL
SRL
SRA
SUB
SWAP
TNZ
TRAP
WFI
Shift right Logic
Shift right Arithmetic
Subtraction
N
N
N
N
M
SWAP nibbles
Dst[7..4] <=> Dst[3..0] reg, M
tnz lbl1
Test for Neg & Zero
S/W trap
S/W interrupt
1
0
Wait for Interrupt
Exclusive OR
XOR
A = A XOR M
A
M
N
Z
106/153
ST72334J/N, ST72314J/N, ST72124J
16 ELECTRICAL CHARACTERISTICS
16.1 PARAMETER CONDITIONS
Unless otherwise specified, all voltages are re-
16.1.5 Pin input voltage
ferred to V
.
SS
The input voltage measurement on a pin of the de-
vice is described in Figure 54.
16.1.1 Minimum and Maximum values
Unless otherwise specified the minimum and max-
imum values are guaranteed in the worst condi-
tions of ambient temperature, supply voltage and
frequencies by tests in production on 100% of the
Figure 54. Pin input voltage
devices with an ambient temperature at T =25°C
A
ST7 PIN
and T =T max (given by the selected temperature
A
A
range).
V
Data based on characterization results, design
simulation and/or technology characteristics are
indicated in the table footnotes and are not tested
in production. Based on characterization, the min-
imum and maximum values refer to sample tests
and represent the mean value plus or minus three
times the standard deviation (mean±3Σ).
IN
16.1.2 Typical values
Unless otherwise specified, typical data are based
on T =25°C, V =5V (for the 4.5V≤V ≤5.5V
A
DD
DD
voltage range) and V =3.3V (for the 3V≤V ≤4V
DD
DD
voltage range). They are given only as design
guidelines and are not tested.
16.1.3 Typical curves
Unless otherwise specified, all typical curves are
given only as design guidelines and are not tested.
16.1.4 Loading capacitor
The loading conditions used for pin parameter
measurement are shown in Figure 53.
Figure 53. Pin loading conditions
ST7 PIN
C
L
107/153
ST72334J/N, ST72314J/N, ST72124J
16.2 ABSOLUTE MAXIMUM RATINGS
Stresses above those listed as “absolute maxi-
mum ratings” may cause permanent damage to
the device. This is a stress rating only and func-
tional operation of the device under these condi-
tions is not implied. Exposure to maximum rating
conditions for extended periods may affect device
reliability.
16.2.1 Voltage Characteristics
Symbol
Ratings
Maximum value
Unit
V
- V
- V
Supply voltage
6.5
6.5
DD
SS
V
Analog Reference Voltage
DDA
SSA
V
Input voltage on true open drain pin
Input voltage on any other pin
VSS-0.3 to 6.5
VSS-0.3 to VDD+0.3
50
1) & 2)
V
IN
|∆V
| and |∆V
|
Variations between different digital power pins
DDx
SSx
mV
V
|V
- V
DDA
DDX
SSA
Variations between digital and analog power pins
50
- V
|
SSx
V
Electro-static discharge voltage (Human Body Model)
Electro-static discharge voltage (Machine Model)
see Section 16.7.2 "Absolute Electri-
cal Sensitivity" on page 124
ESD(HBM)
V
ESD(MM)
16.2.2 Current Characteristics
Symbol
Ratings
Maximum value
Unit
3)
3)
I
Total current into V power lines (source)
150
150
25
VDD
DD
I
Total current out of V ground lines (sink)
SS
VSS
Output current sunk by any standard I/O and control pin
Output current sunk by any high sink I/O pin
Output current source by any I/Os and control pin
Injected current on ISPSEL pin
I
50
IO
- 25
± 5
± 5
± 5
± 5
± 20
mA
Injected current on RESET pin
2) & 4)
I
INJ(PIN)
Injected current on OSC1 and OSC2 pins
5) & 6)
Injected current on any other pin
2)
5)
ΣI
Total injected current (sum of all I/O and control pins)
INJ(PIN)
Notes:
1. Directly connecting the RESET and I/O pins to V or V could damage the device if an unintentional internal reset
DD
SS
is generated or an unexpected change of the I/O configuration occurs (for example, due to a corrupted program counter).
To guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7kΩ for
RESET, 10kΩ for I/Os). Unused I/O pins must be tied in the same way to V or V according to their reset configuration.
DD
SS
2. When the current limitation is not possible, the V absolute maximum rating must be respected, otherwise refer to
IN
I
specification. A positive injection is induced by V >V while a negative injection is induced by V <V
.
INJ(PIN)
IN
DD
IN
SS
3. All power (V ) and ground (V ) lines must always be connected to the external supply.
DD
SS
4. Negative injection disturbs the analog performance of the device. In particular, it induces leakage currents throughout
the device including the analog inputs. To avoid undesirable effects on the analog functions, care must be taken:
- Analog input pins must have a negative injection less than 0.8 mA (assuming that the impedance of the analog voltage
is lower than the specified limits)
- Pure digital pins must have a negative injection less than 1.6mA. In addition, it is recommended to inject the current as
far as possible from the analog input pins.
5. When several inputs are submitted to a current injection, the maximum ΣI
is the absolute sum of the positive
INJ(PIN)
and negative injected currents (instantaneous values). These results are based on characterisation with ΣI
maxi-
INJ(PIN)
mum current injection on four I/O port pins of the device.
6. True open drain I/O port pins do not accept positive injection.
108/153
ST72334J/N, ST72314J/N, ST72124J
ABSOLUTE MAXIMUM RATINGS (Cont’d)
16.2.3 Thermal Characteristics
Symbol
Ratings
Storage temperature range
Value
Unit
T
-65 to +150
°C
STG
Maximum junction temperature (see Section 18 "DEVICE CONFIGURATION AND ORDER-
ING INFORMATION" on page 144 )
T
J
109/153
ST72334J/N, ST72314J/N, ST72124J
16.3 OPERATING CONDITIONS
16.3.1 General Operating Conditions
Symbol
Parameter
Supply voltage
Conditions
Min
Max
Unit
V
see Figure 55 and Figure 56
3.2
5.5
V
DD
V
V
≥3.5V for ROM devices
≥4.5V for FLASH devices
1)
DD
DD
0
16
f
External clock frequency
MHz
OSC
1)
V
≥3.2V
0
8
DD
1 Suffix Version
6 Suffix Version
7 Suffix Version
3 Suffix Version
0
70
-40
-40
-40
85
T
Ambient temperature range
°C
2)
A
105
125
Figure 55. f
Maximum Operating Frequency Versus VDD Supply Voltage for ROM devices
OSC
FUNCTIONALITY
NOT GUARANTEED
f
[MHz]
FUNCTIONALITY
GUARANTEED
IN THIS AREA
OSC
IN THIS AREA AT T > 85°C
A
16
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
12
8
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
1)
WITH RESONATOR
4
1
0
SUPPLY VOLTAGE [V]
2)
2.5
3.2
3.5
3.85 4
4.5
5
5.5
Figure 56. f
Maximum Operating Frequency Versus VDD Supply Voltage for FLASH devices
OSC
FUNCTIONALITY
NOT GUARANTEED
f
[MHz]
IN THIS AREA AT T > 85°C
FUNCTIONALITY
GUARANTEED
OSC
A
3)
IN THIS AREA
16
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
12
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
8
4
1)
WITH RESONATOR
1
0
SUPPLY VOLTAGE [V]
2.5
3.2
3.5
3.85
4
4.5
5
5.5
Notes:
1. Guaranteed by construction. A/D operation and resonator oscillator start-up are not guaranteed below 1MHz.
2. Operating conditions with T =-40 to +125°C.
A
3. FLASH programming tested in production at maximum T with two different conditions: V =5.5V, f =6MHz and
CPU
A
DD
V
=3.2V, f
=4MHz.
CPU
DD
110/153
ST72334J/N, ST72314J/N, ST72124J
OPERATING CONDITIONS (Cont’d)
16.3.2 Operating Conditions with Low Voltage Detector (LVD)
Subject to general operating conditions for V , f
, and T .
DD OSC
A
1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
2)
High Threshold
Med. Threshold
Low Threshold
4.10
3.75
3.25
4.30
3.90
3.35
4.50
4.05
3.55
2)
2)
V
Reset release threshold (V rise)
IT+
DD
V
2)
2)
High Threshold
3.85
3.50
4.05
3.65
3.10
4.30
3.95
3.35
V
V
Reset generation threshold (V fall) Med. Threshold
IT-
DD
4)
Low Threshold
-V
3.00
200
0.2
LVD voltage threshold hysteresis
V
250
300
50
mV
V/ms
ns
hys
IT+ IT-
3)
Vt
V
rise time rate
POR
DD
2)
t
Filtered glitch delay on V
Not detected by the LVD
40
g(VDD)
DD
3)
Figure 57. High LVD Threshold Versus VDD and f
for FLASH devices
OSC
FUNCTIONALITY AND RESET NOT GUARANTEED IN THIS AREA
FOR TEMPERATURES HIGHER THAN 85°C
f
[MHz]
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
OSC
16
DEVICE UNDER
RESET
12
IN THIS AREA
FUNCTIONAL AREA
8
0
SUPPLY VOLTAGE [V]
V
≥3.85
IT-
2.5
3
3.5
4
4.5
5
5.5
3)
Figure 58. Medium LVD Threshold Versus VDD and f
for FLASH devices
OSC
FUNCTIONALITY AND RESET NOT GUARANTEED IN THIS AREA
FOR TEMPERATURES HIGHER THAN 85°C
f
[MHz]
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
OSC
16
DEVICE UNDER
RESET
12
IN THIS AREA
FUNCTIONAL AREA
8
0
SUPPLY VOLTAGE [V]
2.5
3
V
IT-≥3.5V
4
4.5
5
5.5
2)4)
Figure 59. Low LVD Threshold Versus VDD and f
for FLASH devices
OSC
FUNCTIONALITY NOT GUARANTEED IN THIS AREA
FOR TEMPERATURES HIGHER THAN 85°C
f
[MHz]
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
OSC
16
12
DEVICE UNDER
RESET
IN THIS AREA
FUNCTIONAL AREA
8
SEE NOTE 4
0
SUPPLY VOLTAGE [V]
2.5
V
IT-≥3V 3.2
3.5
4
4.5
5
5.5
Notes:
1. LVD typical data are based on T =25°C. They are given only as design guidelines and are not tested.
A
2. Data based on characterization results, not tested in production.
3. The V rise time rate condition is needed to insure a correct device power-on and LVD reset. Not tested in production.
DD
4.If the low LVD threshold is selected, when V falls below 3.2V, (V minimum operating voltage), the device is guar-
DD
DD
anteed to continue functioning until it goes into reset state. The specified V min. value is necessary in the device power
DD
on phase, but during a power down phase or voltage drop the device will function below this min. level.
111/153
ST72334J/N, ST72314J/N, ST72124J
FUNCTIONAL OPERATING CONDITIONS (Cont’d)
2)
Figure 60. High LVD Threshold Versus VDD and f
for ROM devices
OSC
f
[MHz]
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
OSC
16
DEVICE UNDER
RESET
IN THIS AREA
FUNCTIONAL AREA
8
0
SUPPLY VOLTAGE [V]
V
IT-
≥3.85
2.5
3
3.5
4
4.5
5
5.5
5.5
5.5
2)
Figure 61. Medium LVD Threshold Versus VDD and f
for ROM devices
OSC
f
[MHz]
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
OSC
16
DEVICE UNDER
RESET
IN THIS AREA
FUNCTIONAL AREA
8
0
SUPPLY VOLTAGE [V]
2.5
3
V
IT-≥3.5V
4
4.5
5
2)3)
Figure 62. Low LVD Threshold Versus VDD and f
for ROM devices
OSC
f
[MHz]
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
OSC
16
DEVICE UNDER
RESET
IN THIS AREA
FUNCTIONAL AREA
8
0
SUPPLY VOLTAGE [V]
2.5
V
IT-≥3.00V
3.5
4
4.5
5
Notes:
1. LVD typical data are based on T =25°C. They are given only as design guidelines and are not tested.
A
2. The minimum V rise time rate is needed to insure a correct device power-on and LVD reset. Not tested in production.
DD
3. If the low LVD threshold is selected, when V falls below 3.2V, (V minimum operating voltage), the device is guar-
DD
DD
anteed to continue functioning until it goes into reset state. The specified V min. value is necessary in the device power
DD
on phase, but during a power down phase or voltage drop the device will function below this min. level.
112/153
ST72334J/N, ST72314J/N, ST72124J
16.4 SUPPLY CURRENT CHARACTERISTICS
The following current consumption specified for
the ST7 functional operating modes over tempera-
ture range does not take into account the clock
source current consumption. To get the total de-
vice consumption, the two current values must be
added (except for HALT mode for which the clock
is stopped).
Symbol
∆I
Parameter
Conditions
Max
Unit
Supply current variation vs. temperature
Constant V and f
10
%
DD(∆Ta)
DD
CPU
16.4.1 RUN and SLOW Modes
1)
2)
Symbol
Parameter
Conditions
Typ
Max
Unit
f
f
f
f
=2MHz, f
=4MHz, f
=8MHz, f
=1MHz
=2MHz
=4MHz
1.2
2.1
3.9
7.4
1.8
3.5
7.0
OSC
OSC
OSC
OSC
CPU
CPU
CPU
3)
Supply current in RUN mode
(see Figure 63)
=16MHz, f
=8MHz
14.0
CPU
f
f
f
f
=2MHz, f
=4MHz, f
=8MHz, f
=62.5kHz
=125kHz
=250kHz
0.4
0.5
0.7
1.0
0.9
1.1
1.4
2.0
OSC
OSC
OSC
OSC
CPU
CPU
CPU
4)
Supply current in SLOW mode
(see Figure 64)
=16MHz, f
=500kHz
CPU
I
mA
DD
f
f
f
f
=2MHz, f
=4MHz, f
=8MHz, f
=1MHz
=2MHz
=4MHz
0.3
0.8
1.6
3.5
1
1.5
3
OSC
OSC
OSC
OSC
CPU
CPU
CPU
3)
Supply current in RUN mode
(see Figure 63)
=16MHz, f
=8MHz
7
CPU
f
f
f
f
=2MHz, f
=4MHz, f
=8MHz, f
=62.5kHz
=125kHz
=250kHz
0.1
0.2
0.3
0.5
0.3
0.5
0.6
1.0
OSC
OSC
OSC
OSC
CPU
CPU
CPU
4)
Supply current in SLOW mode
(see Figure 64)
=16MHz, f
=500kHz
CPU
Figure 63. Typical I in RUN vs. f
Figure 64. Typical I in SLOW vs. f
CPU
DD
CPU
DD
IDD [mA]
IDD [mA]
8
500kHz
250kHz
125kHz
62.5kHz
1.2
8MHz
4MHz
2MHz
1MHz
7
6
5
1
0.8
0.6
0.4
0.2
0
4
3
2
1
0
3.2
3.5
4
4.5
5
5.5
3.2
3.5
4
4.5
5
5.5
VDD [V]
VDD [V]
Notes:
1. Typical data are based on T =25°C, V =5V (4.5V≤V ≤5.5V range) and V =3.4V (3.2V≤V ≤3.6V range).
A
DD
DD
DD
DD
2. Data based on characterization results, tested in production at V max. and f
max.
DD
CPU
3. CPU running with memory access, all I/O pins in input mode with a static value at V or V (no load), all peripherals
DD
SS
in reset state; clock input (OSC1) driven by external square wave, CSS and LVD disabled.
4. SLOW mode selected with f
SS
based on f
divided by 32. All I/O pins in input mode with a static value at V or
CPU
OSC DD
V
(no load), all peripherals in reset state; clock input (OSC1) driven by external square wave, CSS and LVD disabled.
113/153
ST72334J/N, ST72314J/N, ST72124J
SUPPLY CURRENT CHARACTERISTICS (Cont’d)
16.4.2 WAIT and SLOW WAIT Modes
1)
2)
Symbol
Parameter
Conditions
Typ
Max
Unit
f
f
f
f
=2MHz, f
=4MHz, f
=8MHz, f
=1MHz
=2MHz
=4MHz
0.35
0.7
1.3
2.5
0.6
1.2
2.1
4.0
OSC
OSC
OSC
OSC
CPU
CPU
CPU
3)
Supply current in WAIT mode
(see Figure 65)
=16MHz, f
=8MHz
CPU
mA
f
f
f
f
=2MHz, f
=4MHz, f
=8MHz, f
=62.5kHz
=125kHz
=250kHz
0.05
0.1
0.2
0.5
0.1
0.2
0.4
1.0
OSC
OSC
OSC
OSC
CPU
CPU
CPU
4)
Supply current in SLOW WAIT mode
(see Figure 66)
=16MHz, f
=500kHz
CPU
I
DD
f
f
f
f
=2MHz, f
=4MHz, f
=8MHz, f
=1MHz
=2MHz
=4MHz
45
100
300
600
OSC
OSC
OSC
OSC
CPU
CPU
CPU
3)
Supply current in WAIT mode
(see Figure 65)
150
300
500
=16MHz, f
=8MHz
1000
CPU
µA
f
f
f
f
=2MHz, f
=4MHz, f
=8MHz, f
6
40
80
120
20
OSC
OSC
OSC
OSC
CPU
CPU
CPU
4)
Supply current in SLOW WAIT mode
(see Figure 66)
100
160
250
=16MHz, f
Figure 65. Typical I in WAIT vs. f
Figure 66. Typical I in SLOW-WAIT vs. f
CPU
DD
CPU
DD
IDD [mA]
IDD [mA]
8MHz
4MHz
2MHz
1MHz
500kHz
250kHz
125kHz
62.5kHz
3
2.5
2
0.35
0.3
0.25
0.2
1.5
1
0.15
0.1
0.5
0
0.05
0
3.2
3.5
4
4.5
5
5.5
3.2
3.5
4
4.5
5
5.5
VDD [V]
VDD [V]
Notes:
1. Typical data are based on T =25°C, V =5V (4.5V≤V ≤5.5V range) and V =3.4V (3.2V≤V ≤3.6V range).
A
DD
DD
DD
DD
2. Data based on characterization results, tested in production at V max. and f
max.
DD
CPU
3. All I/O pins in input mode with a static value at V or V (no load), all peripherals in reset state; clock input (OSC1)
DD
SS
driven by external square wave, CSS and LVD disabled.
4. SLOW-WAIT mode selected with f
based on f
divided by 32. All I/O pins in input mode with a static value at
CPU
OSC
V
or V (no load), all peripherals in reset state; clock input (OSC1) driven by external square wave, CSS and LVD
DD
SS
disabled.
114/153
ST72334J/N, ST72314J/N, ST72124J
SUPPLY CURRENT CHARACTERISTICS (Cont’d)
16.4.3 HALT and ACTIVE-HALT Modes
1)
Symbol
Parameter
Conditions
-40°C≤T ≤+85°C
Typ
<2
Max
10
Unit
A
V
V
=5.5V
=3.6V
DD
-40°C≤T ≤+125°C
150
6
A
2)
Supply current in HALT mode
I
-40°C≤T ≤+85°C
µA
DD
A
DD
-40°C≤T ≤+125°C
100
150
A
3)
Supply current in ACTIVE-HALT mode
50
16.4.4 Supply and Clock Managers
The previous current consumption specified for
the ST7 functional operating modes over tempera-
ture range does not take into account the clock
source current consumption. To get the total de-
vice consumption, the two current values must be
added (except for HALT mode).
1)
4)
Symbol
Parameter
Conditions
Typ
Max
Unit
Supply current of internal RC oscillator
Supply current of external RC oscillator
500
525
750
750
5)
200
300
450
700
400
550
750
LP: Low power oscillator
I
DD(CK)
MP: Medium power oscillator
MS: Medium speed oscillator
HS: High speed oscillator
5) & 6)
Supply current of resonator oscillator
µA
1000
Clock security system supply current
LVD supply current
150
100
350
150
I
HALT mode
DD(LVD)
16.4.5 On-Chip Peripherals
Symbol
Parameter
Conditions
Typ
50
Unit
V
V
V
V
V
V
=3.4V
=5.0V
=3.4V
=5.0V
=3.4V
=5.0V
DD
DD
DD
DD
DD
DD
7)
I
16-bit Timer supply current
f
f
f
=8MHz
=8MHz
=4MHz
DD(TIM)
CPU
CPU
ADC
150
250
350
800
1100
8)
I
SPI supply current
ADC supply current when converting
µA
DD(SPI)
9)
I
DD(ADC)
Notes:
1. Typical data are based on T =25°C.
A
2. All I/O pins in input mode with a static value at V or V (no load), CSS and LVD disabled. Data based on charac-
DD
SS
CPU
terization results, tested in production at V max. and f
max.
DD
3. Data based on design simulation and/or technology characteristics, not tested in production. All I/O pins in input mode
with a static value at V or V (no load); clock input (OSC1) driven by external square wave, LVD disabled.
DD
SS
4. Data based on characterization results, not tested in production.
5. Data based on characterization results done with the external components specified in Section 16.5.3 and Section
16.5.4, not tested in production.
6. As the oscillator is based on a current source, the consumption does not depend on the voltage.
7. Data based on a differential I measurement between reset configuration (timer counter running at f
/4) and timer
DD
CPU
counter stopped (selecting external clock capability). Data valid for one timer.
8. Data based on a differential I measurement between reset configuration and a permanent SPI master communica-
DD
tion (data sent equal to 55h).
9. Data based on a differential I measurement between reset configuration and continuous A/D conversions.
DD
115/153
ST72334J/N, ST72314J/N, ST72124J
16.5 CLOCK AND TIMING CHARACTERISTICS
Subject to general operating conditions for V , f
, and T .
DD OSC
A
16.5.1 General Timings
1)
Symbol
Parameter
Conditions
Min
2
Typ
Max
12
Unit
tCPU
ns
3
t
Instruction cycle time
c(INST)
f
f
=8MHz
250
10
375
1500
22
CPU
2)
tCPU
µs
Interrupt reaction time
t
v(IT)
t
= ∆t
+ 10
=8MHz
1.25
2.75
v(IT)
c(INST)
CPU
16.5.2 External Clock Source
Symbol
Parameter
Conditions
Min
0.7xV
Typ
Max
Unit
V
OSC1 input pin high level voltage
OSC1 input pin low level voltage
V
DD
OSC1H
DD
SS
V
V
V
0.3xV
OSC1L
DD
t
t
3)
w(OSC1H)
see Figure 67
OSC1 high or low time
15
w(OSC1L)
ns
t
t
3)
r(OSC1)
OSC1 rise or fall time
15
±1
f(OSC1)
I
OSCx Input leakage current
V
≤V ≤V
DD
µA
L
SS
IN
Figure 67. Typical Application with an External Clock Source
90%
VOSC1H
10%
VOSC1L
tf(OSC1)
tw(OSC1H)
tr(OSC1)
tw(OSC1L)
OSC2
Not connected internally
fOSC
EXTERNAL
CLOCK SOURCE
IL
OSC1
ST72XXX
Notes:
1. Data based on typical application software.
2. Time measured between interrupt event and interrupt vector fetch. ∆tc(INST) is the number of tCPU cycles needed to finish
the current instruction execution.
3. Data based on design simulation and/or technology characteristics, not tested in production.
116/153
ST72334J/N, ST72314J/N, ST72124J
CLOCK AND TIMING CHARACTERISTICS (Cont’d)
16.5.3 Crystal and Ceramic Resonator Oscillators
The ST7 internal clock can be supplied with four
different Crystal/Ceramic resonator oscillators. All
the information given in this paragraph are based
on characterization results with specified typical
external components. In the application, the reso-
nator and the load capacitors have to be placed as
close as possible to the oscillator pins in order to
minimize output distortion and start-up stabiliza-
tion time. Refer to the crystal/ceramic resonator
manufacturer for more details (frequency, pack-
age, accuracy...).
Symbol
Parameter
Conditions
Min
Max
Unit
MHz
kΩ
LP: Low power oscillator
1
2
4
8
MP: Medium power oscillator
MS: Medium speed oscillator
HS: High speed oscillator
>2
>4
>8
3)
f
Oscillator Frequency
OSC
16
R
Feedback resistor
20
40
F
R =200Ω
LP oscillator
MP oscillator
MS oscillator
HS oscillator
38
32
18
15
56
46
26
21
S
Recommended load capacitance ver-
sus equivalent serial resistance of the
C
C
R =200Ω
L1
L2
S
pF
R =200Ω
S
crystal or ceramic resonator (R )
S
R =100Ω
S
V
=5V
LP oscillator
MP oscillator
MS oscillator
HS oscillator
40
100
190
360
700
DD
V =V
110
180
400
IN
SS
i
OSC2 driving current
µA
2
16.5.3.1 Typical Crystal Resonators
Option
C
C
L2
t
L1
SU(osc)
1)
Byte
Reference
Freq.
Characteristic
2)
[ms]
[pF] [pF]
Config.
2MHz
4MHz
LP
MP
MS
HS
S-200-30-30/50
∆f
∆f
∆f
∆f
=[±30ppm
=[±30ppm
=[±30ppm
=[±30ppm
,±30ppm ], Typ. R =200Ω
33 34 10~15
33 34 7~10
OSC
OSC
OSC
OSC
25°C
25°C
25°C
25°C
∆Ta
S
SS3-400-30-30/30
SS3-800-30-30/30
SS3-1600-30-30/30
,±30ppm ], Typ. R =60Ω
∆Ta S
8MHz
,±30ppm ], Typ. R =25Ω
33 34 2.5~3
33 34 1~1.5
∆Ta
S
16MHz
,±30ppm ], Typ. R =15Ω
∆Ta
S
Figure 68. Application with a Crystal Resonator
i
2
fOSC
CL1
OSC1
RESONATOR
R
F
CL2
OSC2
ST72XXX
Notes:
1. Resonator characteristics given by the crystal manufacturer.
2. t is the typical oscillator start-up time measured between V =2.8V and the fetch of the first instruction (with a
SU(OSC)
DD
quick V ramp-up from 0 to 5V (<50µs).
DD
3. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small R value.
S
Refer to crystal manufacturer for more details.
117/153
ST72334J/N, ST72314J/N, ST72124J
CLOCK AND TIMING CHARACTERISTICS (Cont’d)
16.5.3.2 Typical Ceramic Resonators
Symbol
Parameter
Conditions
2MHz
Typ
4.2
2.1
1.1
0.7
Unit
LP
MP
MS
HS
4MHz
8MHz
t
Ceramic resonator start-up time
ms
SU(osc)
16MHz
Note:
t
is the typical oscillator start-up time measured between V =2.8V and the fetch of the first instruction (with a
DD
DD
SU(OSC)
quick V ramp-up from 0 to 5V (<50µs).
Figure 69. Application with Ceramic Resonator
WHEN RESONATOR WITH
INTEGRATED CAPACITORS
i
2
fOSC
CL1
OSC1
RESONATOR
R
R
F(EXT)
F
CL2
OSC2
ST72XXX
R
D
Notes:
1. Resonator characteristics given by the ceramic resonator manufacturer.
2. t is the typical oscillator start-up time measured between V =2.8V and the fetch of the first instruction (with a
SU(OSC)
DD
quick V ramp-up from 0 to 5V (<50µs).
DD
3. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small R value.
S
Refer to Table 22 and Table 23 and to the ceramic resonator manufacturer’s documentation for more details.
118/153
ST72334J/N, ST72314J/N, ST72124J
CLOCK AND TIMING CHARACTERISTICS (Cont’d)
Table 22. Typical Ceramic Resonators
f
C
C
R
R
D
Option Byte
Config.
OSC
L1
3
L2
3
FEXT
1)
Resonator Part Number
(MHz)
[pF]
[pF]
kΩ
[kΩ]
CSB1000JA
1
100
100
3.3
CSBF1000JA
LP
MP
MS
CSTS0200MGA06
CSTCC2.00MGA0H6
CSTS0200MGA06
CSTCC2.00MGA0H6
CSTS0400MGA06
CSTCC4.00MGA0H6
CSTS0400MGA06
CSTCC4.00MGA0H6
CSTS0800MGA06
CSTCC8.00MGA0H6
CSTS0800MGA06
CSTCC8.00MGA0H6
CST10.0MTWA
2
2
4
(47)
(47)
4
Open
8
0
8
30
(15)
30
30
(15)
30
10
12
CSTCC10.0MGA
CST12.0MTWA
HS
CSTCS12.0MTA
(30)
15
(30)
15
CSA16.00MXZA040
CST16.00MXWA0C3
CSACV16.00MXA040Q
CSTCV16.00MXA0H3Q
(15)
15
(15)
15
2)
16
10
(15)
(15)
Table 23. Resonator Frequency Correlation Factor
Option
Byte
Config.
Corre-
lation
%
Option
Byte
Config.
Corre-
lation
%
Refer-
ence IC
Refer-
ence IC
1)
1)
Resonator
Resonator
CSB1000JA
+0.03
-0.20
-0.16
-0.21
-0.19
0.02
4069UBE
CSTS0400MGA06
CSTCC4.00MGA0H6
CSTS0800MGA06
CSTCC4.00MGA0H6
CSTS0800MGA06
CSTCC8.00MGA0H6
CSTS10.0MTWA
CSTCC10.0MGA
CST12.0MTWA
-0.03
-0.05
+0.03
+0.02
+0.02
+0.01
+0.38
+0.61
+0.38
+0.42
+0.10
CSTS0200MGA06
CSTCC2.00MGA0H6
CSTS0200MGA06
CSTCC2.00MGA0H6
CSTS0400MGA06
CSTCC4.00MGA0H6
LP
MS
74HCU04
74HCU04
MP
-0.05
HS
4069UBE
74HCU04
CSTCS12.0MTA
CSA16.00MXZA040
CSACV16.00MXA040Q +0.08
Notes:
1. Murata Ceralock
2. V 4.5 to 5.5V
DD
3. Values in parentheses refer to the capacitors integrated in the resonator
119/153
ST72334J/N, ST72314J/N, ST72124J
CLOCK CHARACTERISTICS (Cont’d)
16.5.4 RC Oscillators
The ST7 internal clock can be supplied with an RC
oscillator. This oscillator can be used with internal
or external components (selectable by option
byte).
Symbol
Parameter
Conditions
see Figure 71
Min
3.60
1
Typ
Max
5.10
14
Unit
1)
Internal RC oscillator frequency
f
MHz
OSC
2)
External RC oscillator frequency
Internal RC Oscillator Start-up Time
3)
2.0
R
R
R
R
=47KΩ, C =”0”pF
1.0
6.5
0.7
3.0
EX
EX
EX
EX
EX
t
ms
=47KΩ, C =100pF
SU(OSC)
3)
EX
External RC Oscillator Start-up Time
=10KΩ, C =6.8pF
EX
=10KΩ, C =470pF
EX
4)
R
C
Oscillator external resistor
10
47
KΩ
EX
EX
see Figure 72
5)
Oscillator external capacitor
0
470
pF
Figure 70. Typical Application with RC oscillator
ST72XXX
VDD
INTERNAL RC
Current copy
fOSC
EXTERNAL RC
+
-
V
REF
REX
OSC1
OSC2
CEX
Voltage generator
CEX discharge
Figure 71. Typical Internal RC Oscillator
Figure 72. Typical External RC Oscillator
fosc [MHz]
Rex=10KOhm
fosc [MHz]
-40°C
+25°C
+85°C
20
15
10
5
Rex=15KOhm
Rex=22KOhm
Rex=33KOhm
Rex=39KOhm
Rex=47KOhm
4.3
4.2
4.1
4
+125°C
3.9
3.8
0
3.2
5.5
0
6.8
22
47
100
270
470
VDD [V]
Cex [pF]
Notes:
1. Data based on characterization results.
2. Guaranteed frequency range with the specified C and R ranges taking into account the device process variation.
EX
EX
Data based on design simulation.
3. Data based on characterization results done with V nominal at 5V, not tested in production.
DD
4. R must have a positive temperature coefficient (ppm/°C), carbon resistors should therefore not be used.
EX
5. Important: when no external C is applied, the capacitance to be considered is the global parasitic capacitance which
EX
is subject to high variation (package, application...). In this case, the RC oscillator frequency tuning has to be done by
trying out several resistor values.
120/153
ST72334J/N, ST72314J/N, ST72124J
CLOCK CHARACTERISTICS (Cont’d)
16.5.5 Clock Security System (CSS)
Symbol
Parameter
Conditions
T =25°C, V =5.0V
Min
250
190
Typ
340
260
30
Max
550
450
Unit
kHz
A
DD
1)
f
f
Safe Oscillator Frequency
SFOSC
GFOSC
T =25°C, V =3.4V
A
DD
2)
Glitch Filtered Frequency
MHz
Figure 73. Typical Safe Oscillator Frequencies
fosc [kHz]
400
-40°C
+25°C
+85°C
+125°C
350
300
250
200
3.2
5.5
VDD [V]
Note:
1. Data based on characterization results, tested in production between 90KHz and 600KHz.
2. Filtered glitch on the f signal. See functional description in Section 9.4 on page 31 for more details.
OSC
121/153
ST72334J/N, ST72314J/N, ST72124J
16.6 MEMORY CHARACTERISTICS
16.6.1 RAM and Hardware Registers
Symbol
Parameter
Conditions
Min
Typ
Typ
Max
Unit
1)
V
Data retention mode
HALT mode (or RESET)
1.6
V
RM
16.6.2 EEPROM Data Memory
Symbol
Parameter
Conditions
Min
Max
20
Unit
-40°C≤T ≤+85°C
A
3)
t
Programming time for 1~16 bytes
ms
prog
-40°C≤T ≤+125°C
25
A
5)
4)
t
Data retention
T =+55°C
20
Years
ret
A
5)
N
Write erase cycles
T =+25°C
300 000
Cycles
RW
A
16.6.3 FLASH Program Memory
Symbol
Parameter
Conditions
Min
Typ
25
8
Max
70
Unit
°C
2)
0
T
Programming temperature range
Programming time for 1~16 bytes
A(prog)
3)
T =+25°C
25
ms
A
t
prog
T =+25°C
2.1
6.4
Programming time for 4 or 8kBytes
sec
A
5)
4)
t
Data retention
T =+55°C
20
years
cycles
ret
A
5)
N
Write erase cycles
T =+25°C
100
RW
A
Notes:
1. Minimum V supply voltage without losing data stored in RAM (in HALT mode or under RESET) or in hardware reg-
DD
isters (only in HALT mode). Guaranteed by construction, not tested in production.
2. Data based on characterization results, tested in production at T =25°C.
A
3. Up to 16 bytes can be programmed at a time for a 4kBytes FLASH block (then up to 32 bytes at a time for an 8k device)
4. The data retention time increases when the T decreases.
A
5. Data based on reliability test results and monitored in production.
122/153
ST72334J/N, ST72314J/N, ST72124J
16.7 EMC CHARACTERISTICS
Susceptibility tests are performed on a sample ba-
sis during product characterization.
■ ESD: Electro-Static Discharge (positive and
negative) is applied on all pins of the device until
a functional disturbance occurs. This test
conforms with the IEC 1000-4-2 standard.
16.7.1 Functional EMS
(Electro Magnetic Susceptibility)
■ FTB: A Burst of Fast Transient voltage (positive
Based on a simple running application on the
product (toggling 2 LEDs through I/O ports), the
product is stressed by two electro magnetic events
until a failure occurs (indicated by the LEDs).
and negative) is applied to V and V through
DD
SS
a 100pF capacitor, until a functional disturbance
occurs. This test conforms with the IEC 1000-4-
4 standard.
A device reset allows normal operations to be re-
sumed.
1)
1)
Symbol
Parameter
Conditions
=5V, T =+25°C, f
conforms to IEC 1000-4-2
Neg
Pos
Unit
Voltage limits to be applied on any I/O pin
to induce a functional disturbance
V
=8MHz
OSC
DD
A
V
-1
1
FESD
kV
Fast transient voltage burst limits to be ap-
V
=5V, T =+25°C, f
=8MHz
OSC
DD
A
V
plied through 100pF on V and V pins
-4
4
FFTB
DD
DD
conforms to IEC 1000-4-4
to induce a functional disturbance
2)
Figure 74. EMC Recommended star network power supply connection
ST72XXX
10µF 0.1µF
VDD
ST7
DIGITAL NOISE
FILTERING
VSS
VDD
POWER
SUPPLY
SOURCE
VSSA
EXTERNAL
NOISE
FILTERING
VDDA
0.1µF
Notes:
1. Data based on characterization results, not tested in production.
2. The suggested 10µF and 0.1µF decoupling capacitors on the power supply lines are proposed as a good price vs. EMC
performance trade-off. They have to be put as close as possible to the device power supply pins. Other EMC recommen-
dations are given in other sections (I/Os, RESET, OSCx pin characteristics).
123/153
ST72334J/N, ST72314J/N, ST72124J
EMC CHARACTERISTICS (Cont’d)
16.7.2 Absolute Electrical Sensitivity
Machine Model Test Sequence
Based on three different tests (ESD, LU and DLU)
using specific measurement methods, the product
is stressed in order to determine its performance in
terms of electrical sensitivity. For more details, re-
fer to the AN1181 ST7 application note.
– C is loaded through S1 by the HV pulse gener-
ator.
L
– S1 switches position from generator to ST7.
– A discharge from C to the ST7 occurs.
L
– S2 must be closed 10 to 100ms after the pulse
delivery period to ensure the ST7 is not left in
charge state. S2 must be opened at least 10ms
prior to the delivery of the next pulse.
16.7.2.1 Electro-Static Discharge (ESD)
Electro-Static Discharges (3 positive then 3 nega-
tive pulses separated by 1 second) are applied to
the pins of each sample according to each pin
combination. The sample size depends of the
number of supply pins of the device (3 parts*(n+1)
supply pin). Two models are usually simulated:
Human Body Model and Machine Model. This test
conforms to the JESD22-A114A/A115A standard.
See Figure 75 and the following test sequences.
– R (machine resistance), in series with S2, en-
sures a slow discharge of the ST7.
Human Body Model Test Sequence
– C is loaded through S1 by the HV pulse gener-
L
ator.
– S1 switches position from generator to R.
– A discharge from C through R (body resistance)
L
to the ST7 occurs.
– S2 must be closed 10 to 100ms after the pulse
delivery period to ensure the ST7 is not left in
charge state. S2 must be opened at least 10ms
prior to the delivery of the next pulse.
Absolute Maximum Ratings
1)
Symbol
Ratings
Conditions
Maximum value
Unit
Electro-static discharge voltage
(Human Body Model)
T =+25°C
V
3000
A
ESD(HBM)
V
Electro-static discharge voltage
(Machine Model)
T =+25°C
V
400
A
ESD(MM)
Figure 75. Typical Equivalent ESD Circuits
S1
R=1500Ω
S1
HIGH VOLTAGE
PULSE
GENERATOR
HIGH VOLTAGE
PULSE
GENERATOR
ST7
ST7
CL=100pF
S2
S2
CL=200pF
HUMAN BODY MODEL
MACHINE MODEL
Notes:
1. Data based on characterization results, not tested in production.
124/153
ST72334J/N, ST72314J/N, ST72124J
EMC CHARACTERISTICS (Cont’d)
16.7.2.2 Static and Dynamic Latch-Up
should be noted that good EMC performance is
highly dependent on the user application and the
software in particular.
■ LU: 3 complementary static tests are required
on 10 parts to assess the latch-up performance.
A supply overvoltage (applied to each power
supply pin), a current injection (applied to each
input, output and configurable I/O pin) and a
power supply switch sequence are performed
on each sample. This test conforms to the EIA/
JESD 78 IC latch-up standard. For more details,
refer to the AN1181 ST7 application note.
■ DLU: Electro-Static Discharges (one positive
then one negative test) are applied to each pin
of 3 samples when the micro is running to
assess the latch-up performance in dynamic
mode. Power supplies are set to the typical
values, the oscillator is connected as near as
possible to the pins of the micro and the
component is put in reset mode. This test
conforms to the IEC1000-4-2 and SAEJ1752/3
standards and is described in Figure 76. For
more details, refer to the AN1181 ST7
application note.
Therefore it is recommended that the user applies
EMC software optimization and prequalification
tests in relation with the EMC level requested for
his application.
Software recommendations:
The software flowchart must include the manage-
ment of runaway conditions such as:
– Corrupted program counter
– Unexpected reset
– Critical Data corruption (control registers...)
Prequalification trials:
Most of the common failures (unexpected reset
and program counter corruption) can be repro-
duced by manually forcing a low state on the RE-
SET pin or the Oscillator pins for 1 second.
To complete these trials, ESD stress can be ap-
plied directly on the device, over the range of
specification values. When unexpected behaviour
is detected, the software can be hardened to pre-
vent unrecoverable errors occurring (see applica-
tion note AN1015).
16.7.2.3 Designing hardened software to avoid
noise problems
EMC characterization and optimization are per-
formed at component level with a typical applica-
tion environment and simplified MCU software. It
Electrical Sensitivities
1)
Symbol
LU
Parameter
Static latch-up class
Dynamic latch-up class
Conditions
Class
T =+25°C
A
A
A
T =+85°C
A
V
=5.5V, f
=4MHz, T =+25°C
DLU
A
DD
OSC
A
Figure 76. Simplified Diagram of the ESD Generator for DLU
RCH=50MΩ
RD=330Ω
DISCHARGE TIP
VDD
VSS
HV RELAY
CS=150pF
ST7
ESD
GENERATOR 2)
DISCHARGE
RETURN CONNECTION
Notes:
1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC spec-
ifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the
JEDEC criteria (international standard).
2. Schaffner NSG435 with a pointed test finger.
125/153
ST72334J/N, ST72314J/N, ST72124J
EMC CHARACTERISTICS (Cont’d)
16.7.3 ESD Pin Protection Strategy
Standard Pin Protection
To protect an integrated circuit against Electro-
Static Discharge the stress must be controlled to
prevent degradation or destruction of the circuit el-
ements. The stress generally affects the circuit el-
ements which are connected to the pads but can
also affect the internal devices when the supply
pads receive the stress. The elements to be pro-
tected must not receive excessive current, voltage
or heating within their structure.
To protect the output structure the following ele-
ments are added:
– A diode to V (3a) and a diode from V (3b)
DD
SS
– A protection device between V and V (4)
DD
SS
To protect the input structure the following ele-
ments are added:
– A resistor in series with the pad (1)
– A diode to V (2a) and a diode from V (2b)
DD
SS
– A protection device between V and V (4)
An ESD network combines the different input and
output ESD protections. This network works, by al-
lowing safe discharge paths for the pins subjected
to ESD stress. Two critical ESD stress cases are
presented in Figure 77 and Figure 78 for standard
pins and in Figure 79 and Figure 80 for true open
drain pins.
DD
SS
Figure 77. Positive Stress on a Standard Pad vs. V
SS
VDD
VDD
(3a)
(2a)
(1)
(4)
OUT
IN
Main path
(3b)
(2b)
Path to avoid
VSS
VSS
Figure 78. Negative Stress on a Standard Pad vs. V
DD
VDD
VDD
(3a)
(2a)
(1)
(4)
OUT
IN
Main path
(3b)
(2b)
VSS
VSS
126/153
ST72334J/N, ST72314J/N, ST72124J
Multisupply Configuration
EMC CHARACTERISTICS (Cont’d)
True Open Drain Pin Protection
The centralized protection (4) is not involved in the
discharge of the ESD stresses applied to true
open drain pads due to the fact that a P-Buffer and
When several types of ground (V , V
, ...) and
SSA
SS
power supply (V , V
, ...) are available for any
DD
DDA
reason (better noise immunity...), the structure
shown in Figure 81 is implemented to protect the
device against ESD.
diode to V
local protection between the pad and V
are not implemented. An additional
DD
(5a &
SS
5b) is implemented to completely absorb the posi-
tive ESD discharge.
Figure 79. Positive Stress on a True Open Drain Pad vs. V
SS
VDD
VDD
Main path
(1)
OUT
(4)
IN
Path to avoid
(5a)
(5b)
(3b)
(2b)
VSS
VSS
Figure 80. Negative Stress on a True Open Drain Pad vs. V
DD
VDD
VDD
Main path
(1)
OUT
(4)
IN
(3b)
(3b)
(3b)
(2b)
VSS
VSS
Figure 81. Multisupply Configuration
VDD
VDDA
VDDA
VSS
BACK TO BACK DIODE
BETWEEN GROUNDS
VSSA
VSSA
127/153
ST72334J/N, ST72314J/N, ST72124J
16.8 I/O PORT PIN CHARACTERISTICS
16.8.1 General Characteristics
Subject to general operating conditions for V , f
, and T unless otherwise specified.
DD OSC
A
1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
V
2)
V
Input low level voltage
Input high level voltage
0.3xVDD
IL
2)
V
0.7xVDD
IH
3)
V
Schmitt trigger voltage hysteresis
Input leakage current
400
mV
µA
hys
I
V
SS≤V ≤V
±1
L
IN
DD
4)
I
Static current consumption
Floating input mode
200
250
300
S
V
V
=5V
62
120
200
5
DD
DD
5)
R
Weak pull-up equivalent resistor
V =V
SS
kΩ
pF
ns
PU
IN
=3.3V
170
C
I/O pin capacitance
IO
6)
t
t
Output high to low level fall time
25
C =50pF
Between 10% and 90%
f(IO)out
r(IO)out
L
6)
Output low to high level rise time
25
7)
t
External interrupt pulse time
1
t
CPU
w(IT)in
Figure 82. Two typical Applications with unused I/O Pin
VDD
ST72XXX
UNUSED I/O PORT
10kΩ
10kΩ
UNUSED I/O PORT
ST72XXX
Figure 83. Typical I vs. V with V =V
PU
DD
IN
SS
Ipu [µA]
70
Ta=-40°C
Ta=25°C
Ta=85°C
60
Ta=125°C
50
40
30
20
10
0
3.2
3.5
4
4.5
5
5.5
Vdd [V]
Notes:
1. Unless otherwise specified, typical data are based on T =25°C and V =5V.
A
DD
2. Data based on characterization results, not tested in production.
3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
4. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for
example or an external pull-up or pull-down resistor (see Figure 82). Data based on design simulation and/or technology
characteristics, not tested in production.
5. The R pull-up equivalent resistor is based on a resistive transistor (corresponding I current characteristics de-
PU
PU
scribed in Figure 83). This data is based on characterization results, tested in production at V max.
DD
6. Data based on characterization results, not tested in production.
7. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external
interrupt source.
128/153
ST72334J/N, ST72314J/N, ST72124J
I/O PORT PIN CHARACTERISTICS (Cont’d)
16.8.2 Output Driving Current
Subject to general operating conditions for V , f
, and T unless otherwise specified.
A
DD OSC
Symbol
Parameter
Conditions
=+5mA T ≤85°C
Min
Max
Unit
I
I
I
I
I
I
1.3
1.5
IO
IO
IO
IO
IO
IO
A
Output low level voltage for a standard I/O pin
when 8 pins are sunk at same time
(see Figure 84 and Figure 87)
T ≥85°C
A
=+2mA T ≤85°C
0.65
0.75
A
T ≥85°C
A
1)
V
OL
=+20mA,T ≤85°C
1.5
1.7
A
Output low level voltage for a high sink I/O pin
when 4 pins are sunk at same time
(see Figure 85 and Figure 88)
T ≥85°C
A
V
=+8mA T ≤85°C
0.75
0.85
A
T ≥85°C
A
=-5mA, T ≤85°C
V
V
-1.6
-1.7
A
DD
DD
Output high level voltage for an I/O pin
when 4 pins are sourced at same time
(see Figure 86 and Figure 89)
T ≥85°C
A
2)
V
OH
V
V
-0.8
-1.0
=-2mA T ≤85°C
DD
A
T ≥85°C
A
DD
Figure 84. Typical V at V =5V (standard)
Figure 86. Typical V
at V =5V
OL
DD
OH
DD
Vol [V] at Vdd=5V
Voh [V] at Vdd=5V
6
2.5
Ta=-40°C
2
Ta=85°C
5
4
3
2
1
Ta=25°C
1.5
Ta=125°C
Ta=-40°C
Ta=25°C
Ta=85°C
Ta=125°C
1
0.5
0
-8
-6
-4
-2
0
0
2
4
6
8
10
Iio [mA]
Iio [mA]
Figure 85. Typical V at V =5V (high-sink)
OL
DD
Vol [V] at Vdd=5V
2
Ta=-40°C
Ta=85°C
1.5
Ta=25°C
Ta=125°C
1
0.5
0
0
5
10
15
Iio [mA]
20
25
30
Notes:
1. The I current sunk must always respect the absolute maximum rating specified in Section 16.2.2 and the sum of I
IO
IO
(I/O ports and control pins) must not exceed I
.
VSS
2. The I current sourced must always respect the absolute maximum rating specified in Section 16.2.2 and the sum of
IO
I
(I/O ports and control pins) must not exceed I
. True open drain I/O pins does not have V
.
IO
VDD
OH
129/153
ST72334J/N, ST72314J/N, ST72124J
I/O PORT PIN CHARACTERISTICS (Cont’d)
Figure 87. Typical V vs. V (standard I/Os)
OL
DD
Vol [V] at Iio=2mA
0.5
Ta=-40°C
Ta=25°C
Ta=85°C
Vol [V] at Iio=5mA
Ta=-40°C
Ta=25°C
Ta=85°C
1.4
1.3
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
Ta=125°C
Ta=125°C
0.45
0.4
0.35
0.3
0.25
0.2
3.2
3.5
4
Vdd [V]
4.5
5
5.5
3.2
3.5
4
4.5
5
5.5
Vdd [V]
Figure 88. Typical V vs. V (high-sink I/Os)
OL
DD
Ta=-40°C
Ta=25°C
Ta=85°C
Ta=-40°C
Ta=25°C
Ta=85°C
Vol [V] at Iio=8mA
Vol [V] at Iio=20mA
1.5
0.55
0.5
Ta=125°C
Ta=125°C
1.3
1.1
0.9
0.7
0.5
0.45
0.4
0.35
0.3
0.25
0.2
3.2
3.5
4
4.5
5
5.5
3.2
3.5
4
Vdd [V]
4.5
5
5.5
Vdd [V]
Figure 89. Typical V
vs. V
DD
OH
Voh [V] at Iio=-2mA
Voh [V] at Iio=-5mA
5
5.5
5
4
3
2
1
0
4.5
4
Ta=-40°C
Ta=85°C
3.5
3
Ta=-40°C
Ta=25°C
Ta=85°C
Ta=25°C
5
Ta=125°C
Ta=125°C
2.5
2
3.2
3.5
4
4.5
5
5.5
3.5
4
4.5
5.5
Vdd [V]
Vdd [V]
130/153
ST72334J/N, ST72314J/N, ST72124J
16.9 CONTROL PIN CHARACTERISTICS
16.9.1 Asynchronous RESET Pin
Subject to general operating conditions for V , f
, and T unless otherwise specified.
DD OSC
A
1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
V
2)
V
Input low level voltage
0.3xVDD
IL
2)
V
Input high level voltage
0.7xVDD
IH
3)
V
Schmitt trigger voltage hysteresis
400
0.68
0.28
40
mV
V
hys
4)
I
I
=+5mA
=+2mA
0.95
0.45
60
Output low level voltage
IO
IO
V
V
=5V
OL
ON
DD
(see Figure 92, Figure 93)
V
V
=5V
20
80
DD
DD
5)
R
Weak pull-up equivalent resistor
V =V
kΩ
IN
SS
=3.4V
100
120
External pin or
internal reset sources
6
30
1/f
SFOSC
t
Generated reset pulse duration
w(RSTL)out
µs
6)
t
t
External reset pulse hold time
20
µs
h(RSTL)in
g(RSTL)in
7)
Filtered glitch duration
100
ns
8)
Figure 90. Typical Application with RESET pin
ST72XXX
VDD
VDD
VDD
INTERNAL
RESET CONTROL
RON
RESET
0.1µF
0.1µF
4.7kΩ
USER
EXTERNAL
RESET
CIRCUIT 8)
WATCHDOG RESET
LVD RESET
Notes:
1. Unless otherwise specified, typical data are based on T =25°C and V =5V.
A
DD
2. Data based on characterization results, not tested in production.
3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
4. The I current sunk must always respect the absolute maximum rating specified in Section 16.2.2 and the sum of I
IO
IO
(I/O ports and control pins) must not exceed I
.
VSS
5. The R
pull-up equivalent resistor is based on a resistive transistor (corresponding I current characteristics de-
ON
ON
scribed in Figure 91). This data is based on characterization results, not tested in production.
6. To guarantee the reset of the device, a minimum pulse has to be applied to RESET pin. All short pulses applied on
RESET pin with a duration below t
can be ignored.
h(RSTL)in
7. The reset network (the resistor and two capacitors) protects the device against parasitic resets, especially in a noisy
environments.
8. The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device
can be damaged when the ST7 generates an internal reset (LVD or watchdog).
131/153
ST72334J/N, ST72314J/N, ST72124J
CONTROL PIN CHARACTERISTICS (Cont’d)
Figure 91. Typical I
vs. V with V =V
Figure 92. Typical V at V =5V (RESET)
OL DD
ON
DD
IN
SS
Ion [µA]
Vol [V] at Vdd=5V
2
Ta=-40°C
Ta=25°C
Ta=85°C
Ta=125°C
Ta=-40°C
Ta=25°C
Ta=85°C
200
150
100
50
Ta=125°C
1.5
1
0.5
0
0
0
1
2
3
4
5
6
7
8
3.2
3.5
4
4.5
5
5.5
Iio [mA]
Vdd [V]
Figure 93. Typical V vs. V (RESET)
OL
DD
Vol [V] at Iio=5mA
Ta=-40°C
Ta=25°C
Ta=85°C
Vol [V] at Iio=2mA
Ta=-40°C
Ta=25°C
Ta=85°C
0.55
0.5
Ta=125°C
Ta=125°C
1.2
1
0.45
0.4
0.35
0.3
0.8
0.6
0.4
0.25
0.2
0.15
3.2
3.5
4
4.5
5
5.5
3.2
3.5
4
4.5
5
5.5
Vdd [V]
Vdd [V]
132/153
ST72334J/N, ST72314J/N, ST72124J
CONTROL PIN CHARACTERISTICS (Cont’d)
16.9.2 ISPSEL Pin
Subject to general operating conditions for V , f
, and T unless otherwise specified.
A
DD OSC
Symbol
Parameter
Conditions
Min
Max
Unit
V
1)
V
Input low level voltage
V
0.2
IL
IH
L
SS
1)
V
I
Input high level voltage
Input leakage current
V
-0.1 12.6
±1
DD
V =V
µA
IN
SS
2)
Figure 94. Two typical Applications with ISPSEL Pin
ISPSEL
ISPSEL
PROGRAMMING
TOOL
10kΩ
ST72XXX
ST72XXX
Notes:
1. Data based on design simulation and/or technology characteristics, not tested in production.
2. When the ISP Remote mode is not required by the application ISPSEL pin must be tied to V
.
SS
133/153
ST72334J/N, ST72314J/N, ST72124J
16.10 TIMER PERIPHERAL CHARACTERISTICS
Subject to general operating conditions for V
,
Refer to I/O port characteristics for more details on
the input/output alternate function characteristics
(output compare, input capture, external clock,
PWM output...).
DD
f
, and T unless otherwise specified.
OSC
A
16.10.1 Watchdog Timer
Symbol
Parameter
Watchdog time-out duration
Conditions
Min
12,288
1.54
Typ
Max
786,432
98.3
Unit
tCPU
ms
t
w(WDG)
fCPU=8MHz
16.10.2 16-Bit Timer
Symbol
Parameter
Conditions
Min
1
Typ
Max
Unit
t
Input capture pulse time
t
t
w(ICAP)in
CPU
2
CPU
t
PWM resolution time
res(PWM)
f
=8MHz
250
0
ns
CPU
f
Timer external clock frequency
PWM repetition rate
f
f
/4
/4
MHz
MHz
bit
EXT
CPU
f
0
PWM
CPU
Res
PWM resolution
16
PWM
134/153
ST72334J/N, ST72314J/N, ST72124J
16.11 COMMUNICATION INTERFACE CHARACTERISTICS
16.11.1 SPI - Serial Peripheral Interface
Refer to I/O port characteristics for more details on
the input/output alternate function characteristics
(SS, SCK, MOSI, MISO).
Subject to general operating conditions for V
,
DD
f
, and T unless otherwise specified.
OSC
A
Symbol
Parameter
Conditions
Min
/128
0.0625
Max
Unit
Master
Slave
f
f
f
/4
CPU
2
CPU
f
=8MHz
=8MHz
f
CPU
SCK
SPI clock frequency
MHz
1/t
/2
c(SCK)
CPU
0
f
4
CPU
t
t
r(SCK)
SPI clock rise and fall time
see I/O port pin description
f(SCK)
t
SS setup time
SS hold time
Slave
Slave
120
120
su(SS)
t
h(SS)
t
t
Master
Slave
100
90
w(SCKH)
SCK high and low time
Data input setup time
Data input hold time
w(SCKL)
t
Master
Slave
100
100
su(MI)
t
su(SI)
ns
t
Master
Slave
100
100
h(MI)
t
h(SI)
t
Data output access time
Data output disable time
Data output valid time
Data output hold time
Data output valid time
Data output hold time
Slave
Slave
0
120
240
120
a(SO)
t
dis(SO)
t
v(SO)
h(SO)
v(MO)
h(MO)
Slave (after enable edge)
t
0
t
0.25
0.25
Master (before capture edge)
t
CPU
t
Figure 95. SPI Slave Timing Diagram with CPHA=0 3)
SS INPUT
tsu(SS)
tc(SCK)
th(SS)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
tw(SCKH)
tw(SCKL)
ta(SO)
tv(SO)
th(SO)
tdis(SO)
tr(SCK)
tf(SCK)
see
note 2
MISO OUTPUT
MSB OUT
see note 2
BIT6 OUT
LSB OUT
tsu(SI)
th(SI)
MSB IN
LSB IN
BIT1 IN
MOSI INPUT
Notes:
1. Data based on design simulation and/or characterisation results, not tested in production.
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has
its alternate function capability released. In this case, the pin status depends on the I/O port configuration.
3. Measurement points are done at CMOS levels: 0.3xV and 0.7xV
.
DD
DD
135/153
ST72334J/N, ST72314J/N, ST72124J
COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d)
Figure 96. SPI Slave Timing Diagram with CPHA=11)
SS INPUT
tsu(SS)
tc(SCK)
th(SS)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
tw(SCKH)
tw(SCKL)
ta(SO)
tdis(SO)
tv(SO)
th(SO)
tr(SCK)
tf(SCK)
see
note 2
see
note 2
MISO OUTPUT
MSB OUT
BIT6 OUT
HZ
LSB OUT
tsu(SI)
th(SI)
LSB IN
MSB IN
BIT1 IN
MOSI INPUT
Figure 97. SPI Master Timing Diagram 1)
SS INPUT
tc(SCK)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
CPHA=1
CPOL=0
CPHA=1
CPOL=1
tw(SCKH)
tw(SCKL)
tr(SCK)
tf(SCK)
th(MI)
tsu(MI)
MISO INPUT
MSB IN
BIT6 IN
LSB IN
tv(MO)
th(MO)
LSB OUT
MSB OUT
see note 2
BIT6 OUT
see note 2
MOSI OUTPUT
Notes:
1. Measurement points are done at CMOS levels: 0.3xV and 0.7xV
.
DD
DD
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has
its alternate function capability released. In this case, the pin status depends of the I/O port configuration.
136/153
ST72334J/N, ST72314J/N, ST72124J
COMMUNICATIONS INTERFACE CHARACTERISTICS (Cont’d)
16.11.2 SCI - Serial Communications Interface
Subject to general operating condition for V , f
DD O-
, and T unless otherwise specified.
SC
A
Refer to I/O port characteristics for more details on
the input/output alternate function characteristics
(RDI and TDO).
Conditions
Accuracy
Baud
Rate
Symbol
Parameter
Standard
Unit
Prescaler
f
CPU
vs. Standard
Conventional Mode
TR (or RR)=64, PR=13
TR (or RR)=16, PR=13
TR (or RR)= 8, PR=13
TR (or RR)= 4, PR=13
TR (or RR)= 2, PR=13
TR (or RR)= 8, PR= 3
TR (or RR)= 1, PR=13
300
~300.48
1200 ~1201.92
2400 ~2403.84
4800 ~4807.69
9600 ~9615.38
10400 ~10416.67
19200 ~19230.77
~0.16%
f
f
Tx
Communication frequency 8MHz
Hz
Rx
Extended Mode
ETPR (or ERPR) = 13
38400 ~38461.54
14400 ~14285.71
Extended Mode
ETPR (or ERPR) = 35
~0.79%
137/153
ST72334J/N, ST72314J/N, ST72124J
16.12 8-BIT ADC CHARACTERISTICS
Subject to general operating conditions for V , f
, and T unless otherwise specified.
DD OSC
A
1)
Symbol
Parameter
ADC clock frequency
Conversion range voltage
External input resistor
Conditions
Min
Typ
Max
Unit
MHz
V
f
4
ADC
2)
V
R
V
V
AIN
AIN
SSA
DDA
3)
10
kΩ
C
Internal sample and hold capacitor
Stabilization time after ADC enable
Conversion time (Sample+Hold)
6
pF
ADC
STAB
4)
t
0
µs
3
f
=8MHz, f
=4MHz
ADC
CPU
t
- Sample capacitor loading time
- Hold conversion time
4
8
ADC
1/f
ADC
Figure 98. Typical Application with ADC
VDD
VT
0.6V
RAIN
AINx
VAIN
ADC
VT
0.6V
CIO
~2pF
IL
±1µA
VDD
VDDA
0.1µF
VSSA
ST72XXX
Notes:
1. Unless otherwise specified, typical data are based on T =25°C and V -V =5V. They are given only as design guide-
A
DD SS
lines and are not tested.
2. When V and V
pins are not available on the pinout, the ADC refer to V and V .
SS
DDA
SSA
DD
3. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10kΩ). Data
based on characterization results, not tested in production.
4. The stabilization time of the AD converter is masked by the first t
always valid.
. The first conversion after the enable is then
LOAD
138/153
ST72334J/N, ST72314J/N, ST72124J
8-BIT ADC CHARACTERISTICS (Cont’d)
ADC Accuracy
2)
3)
3)
V
f
=5V,
V
f
=5.0V,
V
=3.3V,
DD
DD
DD
=1MHz
=8MHz
f
=8MHz
Symbol
|E |
Parameter
Unit
CPU
CPU
CPU
Typ.
Max
2.0
1.5
1.5
1.5
1.5
Typ.
Max
2.0
1.5
1.5
1.5
1.5
Typ
Max
2.0
1.5
1.5
1.5
1.5
1)
Total unadjusted error
T
1)
E
E
Offset error
O
G
1)
LSB
Gain Error
1)
|E |
Differential linearity error
D
1)
|E |
Integral linearity error
L
Figure 99. ADC Accuracy Characteristics
Digital Result ADCDR
EG
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line
255
V
V
254
253
DDA
SSA
1LSB
= ----------------------------------------
IDEAL
256
(2)
E =Total Unadjusted Error: maximum deviation
T
ET
between the actual and the ideal transfer curves.
(3)
7
6
5
4
3
2
1
E =Offset Error: deviation between the first actual
O
transition and the first ideal one.
(1)
E =Gain Error: deviation between the last ideal
G
transition and the last actual one.
EO
EL
E =Differential Linearity Error: maximum deviation
D
between actual steps and the ideal one.
E =Integral Linearity Error: maximum deviation
L
ED
between any actual transition and the end point
correlation line.
1 LSBIDEAL
V
(LSB
)
IDEAL
in
0
1
2
3
4
5
6
7
253 254 255 256
VDDA
VSSA
Notes:
1. ADC Accuracy vs. Negative Injection Current:
For I =0.8mA, the typical leakage induced inside the die is 1.6µA and the effect on the ADC accuracy is a loss of 1 LSB
INJ-
for each 10KΩ increase of the external analog source impedance. This effect on the ADC accuracy has been observed
under worst-case conditions for injection:
- negative injection
- injection to an Input with analog capability, adjacent to the enabled Analog Input
- at 5V V supply, and worst case temperature.
DD
2. Data based on characterization results with T =25°C.
A
3. Data based on characterization results over the whole temperature range.
139/153
ST72334J/N, ST72314J/N, ST72124J
17 PACKAGE CHARACTERISTICS
17.1 PACKAGE MECHANICAL DATA
Figure 100. 64-Pin Thin Quad Flat Package
A
mm
inches
D
Dim.
A2
Min Typ Max Min Typ Max
D1
A
1.60
0.063
0.006
A1
b
A1 0.05
0.15 0.002
A2 1.35 1.40 1.45 0.053 0.055 0.057
b
c
0.30 0.37 0.45 0.012 0.015 0.018
0.09 0.20 0.004 0.008
D
16.00
14.00
16.00
14.00
0.80
0.630
0.551
0.630
0.551
0.031
3.5°
e
D1
E
E1
E
E1
e
θ
0°
3.5°
7°
0°
7°
L
0.45 0.60 0.75 0.018 0.024 0.030
1.00 0.039
Number of Pins
64
L
L1
L1
c
N
h
Figure 101. 56-Pin Plastic Dual In-Line Package, Shrink 600-mil Width
mm
inches
Dim.
Min Typ Max Min Typ Max
E
A
6.35
0.250
0.195
A1 0.38
0.015
A
A2
A1
A2 3.18
4.95 0.125
C
E1
b
0.41
0.89
0.016
0.035
eA
eB
b
e
b2
b2
D
E
C
D
E
0.20
0.38 0.008
53.21 1.980
0.015
2.095
50.29
0.015
15.01
0.591
GAGE PLANE
E1 12.32
14.73 0.485
0.580
e
1.78
0.070
0.600
eA
eB
15.24
eB
17.78
0.700
0.200
L
2.92
5.08 0.115
Number of Pins
N
56
140/153
ST72334J/N, ST72314J/N, ST72124J
PACKAGE MECHANICAL DATA (Cont’d)
Figure 102. 44-Pin Thin Quad Flat Package
mm
inches
Dim.
A
D
Min Typ Max Min Typ Max
D1
A2
A
1.60
0.063
0.006
A1 0.05
0.15 0.002
A1
b
A2 1.35 1.40 1.45 0.053 0.055 0.057
b
C
0.30 0.37 0.45 0.012 0.015 0.018
0.09
0.20 0.004 0.000 0.008
D
12.00
10.00
12.00
10.00
0.80
0.472
0.394
0.472
0.394
0.031
e
D1
E
E1
E
E1
e
θ
0°
3.5°
7°
0°
3.5°
7°
L
0.45 0.60 0.75 0.018 0.024 0.030
1.00 0.039
Number of Pins
44
c
L1
L1
L
h
N
Figure 103. 42-Pin Plastic Dual In-Line Package, Shrink 600-mil Width
mm
Min Typ Max Min Typ Max
5.08 0.200
inches
Dim.
E
A
A
A2
A1 0.51
A2 3.05 3.81 4.57 0.120 0.150 0.180
0.38 0.46 0.56 0.015 0.018 0.022
b2 0.89 1.02 1.14 0.035 0.040 0.045
0.020
A1
L
c
E1
b
b2
e
b
eA
eB
E
D
c
D
E
0.23 0.25 0.38 0.009 0.010 0.015
36.58 36.83 37.08 1.440 1.450 1.460
0.015
15.24
16.00 0.600
0.630
GAGE PLANE
E1 12.70 13.72 14.48 0.500 0.540 0.570
e
1.78
0.070
0.600
eA
eB
eC
L
15.24
eC
18.54
0.730
0.060
eB
1.52 0.000
2.54 3.30 3.56 0.100 0.130 0.140
Number of Pins
N
42
Figure 104. THERMAL CHARACTERISTICS
Notes:
1. The power dissipation is obtained from the formula P =P +P
where P
is the chip internal power (I xV
)
D
INT
PORT
INT
DD DD
141/153
ST72334J/N, ST72314J/N, ST72124J
Symbol
Ratings
Package thermal resistance (junction to ambient)
TQFP64
Value
Unit
60
45
52
55
R
SDIP56
TQFP44
SDIP42
°C/W
thJA
1)
P
Power dissipation
Maximum junction temperature
500
150
mW
°C
D
2)
T
Jmax
and P
is the port power dissipation determined by the user.
PORT
2. The average chip-junction temperature can be obtained from the formula T = T + P x RthJA.
J
A
D
142/153
ST72334J/N, ST72314J/N, ST72124J
17.2 SOLDERING AND GLUEABILITY INFORMATION
Recommended soldering information given only
as design guidelines in Figure 105 and Figure 106.
Recommended glue for SMD plastic packages
dedicated to molding compound with silicone:
■ Heraeus: PD945, PD955
■ Loctite: 3615, 3298
Figure 105. Recommended Wave Soldering Profile (with 37% Sn and 63% Pb)
250
COOLING PHASE
(ROOM TEMPERATURE)
5 sec
200
150
100
50
SOLDERING
PHASE
80°C
Temp. [°C]
PREHEATING
PHASE
Time [sec]
0
20
60
40
80
100
140
120
160
Figure 106. Recommended Reflow Soldering Oven Profile (MID JEDEC)
250
Tmax=220+/-5°C
for 25 sec
200
150
100
50
150 sec above 183°C
90 sec at 125°C
Temp. [°C]
ramp down natural
2°C/sec max
ramp up
2°C/sec for 50sec
Time [sec]
0
100
200
300
400
143/153
ST72334J/N, ST72314J/N, ST72124J
18 DEVICE CONFIGURATION AND ORDERING INFORMATION
Each device is available for production in user pro-
grammable versions (FLASH) as well as in factory
coded versions (ROM). E PROM data memory
and FLASH devices are shipped to customers with
a default content (FFh), while ROM factory coded
parts contain the code supplied by the customer.
This implies that FLASH devices have to be con-
figured by the customer using the Option Bytes
while the ROM devices are factory-configured.
USER OPTION BYTE 1
Bit 7 = CSS Clock Security System disable
This option bit enables or disables the CSS fea-
tures.
0: CSS enabled
2
1: CSS disabled
Bit 6:4 = OSC[2:0] Oscillator selection
These three option bits can be used to select the
main oscillator as shown in Table 24.
Bit 3:2 = LVD[1:0] Low voltage detection selection
These option bits enable the LVD block with a se-
lected threshold as shown in Table 25.
18.1 OPTION BYTES
The two option bytes allow the hardware configu-
ration of the microcontroller to be selected.
The option bytes have no address in the memory
map and can be accessed only in programming
mode (for example using a standard ST7 program-
ming tool). The default content of the FLASH is
fixed to FFh.
In masked ROM devices, the option bytes are
fixed in hardware by the ROM code (see option
list).
Bit 1 = WDG HALT Watchdog Reset on HALTt
mode
This option bit determines if a RESET is generated
when entering HALT mode while the Watchdog is
active.
0: No Reset generation when entering Halt mode
1: Reset generation when entering Halt mode
Bit 0 = WDG SW Hardware or software watchdog
This option bit selects the watchdog type.
0: Hardware (watchdog always enabled)
USER OPTION BYTE 0
1: Software (watchdog to be enabled by software)
Table 24. Main Oscillator Configuration
Bit 7:2 = Reserved, must always be 1.
Bit 1 = 56/42 Package Configuration.
This option bit allows to configured the device ac-
cording to the package.
0: 42 or 44 pin packages
1: 56 or 64 pin packages
Selected Oscillator
External Clock (Stand-by)
~4 MHz Internal RC
OSC2 OSC1 OSC0
1
1
1
0
0
0
0
1
1
0
1
1
0
0
1
0
X
1
0
1
0
1~14 MHz External RC
Bit 0 = FMP Full memory protection.
This option bit enables or disables external access
to the internal program memory (read-out protec-
tion). Clearing this bit causes the erasing (by over-
writing with the currently latched values) of the
whole memory (not including the option bytes).
0: Program memory not read-out protected
1: Program memory read-out protected
Low Power Resonator (LP)
Medium Power Resonator (MP)
Medium Speed Resonator (MS)
High Speed Resonator (HS)
Table 25. LVD Threshold Configuration
Note: The data E2PROM is not protected by this
bit in flash devices. In ROM devices, a protection
can be selected in the Option List (see page 146).
Configuration
LVD1 LVD0
1
1
0
0
1
0
1
0
LVD Off
Highest Voltage Threshold ( 4.50V)
Medium Voltage Threshold ( 4.05V)
Lowest Voltage Threshold ( 3.45V)
USER OPTION BYTE 0
USER OPTION BYTE 1
7
0
7
0
OSC OSC OSC
WDG WDG
HALT SW
Reserved
56/42 FMP CSS
LVD1 LVD0
2
1
0
Default
Value
1
1
1
1
1
1
X
0
1
1
1
0
1
1
1
1
144/153
ST72334J/N, ST72314J/N, ST72124J
DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d)
18.2 TRANSFER OF CUSTOMER CODE
Customer code is made up of the ROM contents
and the list of the selected options (if any). The
ROM contents are to be sent on diskette, or by
electronic means, with the hexadecimal file in .S19
format generated by the development tool. All un-
used bytes must be set to FFh.
The selected options are communicated to STMi-
croelectronics using the correctly completed OP-
TION LIST appended.
The STMicroelectronics Sales Organization will be
pleased to provide detailed information on con-
tractual points.
Figure 107. ROM Factory Coded Device Types
TEMP.
PACKAGE RANGE
/
XXX
DEVICE
Code name (defined by STMicroelectronics)
1 = standard 0 to +70 °C
6 = industrial -40 to +85 °C
7 = automotive -40 to +105 °C
3 = automotive -40 to +125 °C
B = Plastic DIP
T = Plastic TQFP
ST72334J2, ST72334J4, ST72334N2, ST72334N4,
ST72314J2, ST72314J4, ST72314N2, ST72314N4,
ST72124J2
Figure 108. FLASH User Programmable Device Types
TEMP.
PACKAGE RANGE
DEVICE
XXX
Code name (defined by STMicroelectronics)
1 = standard 0 to +70 °C
6 = industrial -40 to +85 °C
7 = automotive -40 to +105 °C
3 = automotive -40 to +125 °C
B = Plastic DIP
T = Plastic TQFP
ST72C334J2, ST72C334J4, ST72C334N2, ST72C334N4,
ST72C314J2, ST72C314J4, ST72C314N2, ST72C314N4,
ST72C124J2
145/153
ST72334J/N, ST72314J/N, ST72124J
MICROCONTROLLER OPTION LIST
Customer:
Address:
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact:
Phone No:
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference/ROM code*:. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
*The ROM or FASTROM code name is assigned by STMicroelectronics.
ROM or FASTROM code must be sent in .S19 format. .Hex extension cannot be processed.
STMicroelectronics references
ROM Type/Memory Size/Package (check only 1 option):
-------------------------------------------------------------------------------------------
ROM DEVICE:
|
8K
|
16K
|
-------------------------------------------------------------------------------------------
SDIP42:
|
|
|
|
|
|
|
|
|
|
[ ] ST72124J2B
[ ] ST72314J2B
[ ] ST72334J2B
[ ] ST72124J2T
[ ] ST72314J2T
[ ] ST72334J2T
[ ] ST72314N2B
[ ] ST72334N2B
[ ] ST72314N2T
[ ] ST72334N2T
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
[ ] ST72314J4B
[ ] ST72334J4B
TQFP44:
[ ] ST72314J4T
[ ] ST72334J4T
[ ] ST72314N4B
[ ] ST72334N4B
[ ] ST72314N4T
[ ] ST72334N4T
SDIP56:
TQFP64:
-------------------------------------------------------------------------------------------
FASTROM DEVICE:| 8K 16K
|
|
-------------------------------------------------------------------------------------------
SDIP42:
|
|
|
|
|
|
|
|
|
|
[ ] ST72P124J2B |
|
|
|
|
|
|
|
|
|
|
[ ] ST72P314J2B | [ ] ST72P314J4B
[ ] ST72P334J2B | [ ] ST72P334J4B
[ ] ST72P124J2T |
[ ] ST72P314J2T | [ ] ST72P314J4T
[ ] ST72P334J2T | [ ] ST72P334J4T
[ ] ST72P314N2B | [ ] ST72P314N4B
[ ] ST72P334N2B | [ ] ST72P334N4B
[ ] ST72P314N2T | [ ] ST72P314N4T
[ ] ST72P334N2T | [ ] ST72P334N4T
TQFP44:
SDIP56:
TQFP64:
Conditioning (specify for TQFP only):
Marking: [ ] Standard marking
[ ] Tape & Reel
[ ] Special marking (ROM only):
[ ] Tray
TQFP (10 char. max) : _ _ _ _ _ _ _ _ _ _
SDIP (16 char. max) : _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
Authorized characters are letters, digits, '.', '-', '/' and spaces only.
Please consult your local STMicroelectronics sales office for other marking details if required.
Temperature Range: [ ] 0°C to +70°C
[ ] -40°C to +85°C
[ ] -40°C to +105°C
[ ] -40°C to +125°C
Clock Source Selection:
Resonator:
[ ] LP: Low power resonator (1 to 2 MHz)
[ ] MP: Medium power resonator (2 to 4 MHz)
[ ] MS: Medium speed resonator (4 to 8 MHz)
[ ] HS: High speed resonator (8 to 16 MHz)
[ ] Internal
[ ]
RC Network:
External Clock:
[ ] External
Clock Security System:
LVD Reset:
[ ] Disabled
[ ] Disabled
[ ] Enabled
[ ] Enabled:
[ ] Highest threshold
[ ] Medium threshold
[ ] Lowest threshold
Watchdog Selection:
Watchdog Reset on Halt:
[ ] Software Activation
[ ] Reset
[ ] Hardware Activation
[ ] No reset
Program Readout Protection:
Data E2PROM Readout Protection*:
*available on ST72334 only
[ ] Disabled
[ ] Disabled
[ ] Enabled
[ ] Enabled
Comments:
Supply Operating Range in the application:
Notes:
Date:
Signature:
146/153
ST72334J/N, ST72314J/N, ST72124J
18.3 DEVELOPMENT TOOLS
STMicroelectronics offers a range of hardware
and software development tools for the ST7 micro-
controller family. Full details of tools available for
the ST7 from third party manufacturers can be ob-
tain from the STMicroelectronics Internet site:
➟ http//mcu.st.com.
Tools from these manufacturers include C compli-
ers, emulators and gang programmers.
STMicroelectronics Tools
Three types of development tool are offered by
ST, all of them connect to a PC via a parallel (LPT)
port: see Table 26 and Table 27 for more details.
Table 26. STMicroelectronics Tool Features
1)
In-Circuit Emulation
Programming Capability
Software Included
ST7 CD ROM with:
Yes. (Same features as
ST7 Development Kit
ST7 HDS2 Emulator
HDS2 emulator but without Yes (DIP packages only)
logic analyzer)
– ST7 Assembly toolchain
– STVD7 and WGDB7 powerful
Source Level Debugger for Win
3.1, Win 95 and NT
– C compiler demo versions
– ST Realizer for Win 3.1 and Win
95.
Yes, powerful emulation
features including trace/
logic analyzer
No
ST7 Programming Board
No
Yes (All packages)
– Windows Programming Tools
for Win 3.1, Win 95 and NT
Table 27. Dedicated STMicroelectronics Development Tools
Supported Products
ST7 Development Kit
ST7 HDS2 Emulator
ST7 Programming Board
ST72(C)334J2,
ST72(C)334J4,
ST72(C)334N2,
ST72(C)334N4,
ST72(C)314J2,
ST72(C)314J4,
ST72(C)314N2,
ST72(C)314N4,
ST72(C)124J2
ST7MDT2-EPB2/EU
ST7MDT2-EPB2/US
ST7MDT2-EPB2/UK
ST7MDT2-DVP2
ST7MDT2-EMU2B
Note:
1. In-Situ Programming (ISP) interface for FLASH devices.
147/153
ST72334J/N, ST72314J/N, ST72124J
DEVELOPMENT TOOLS (Cont’d)
18.3.1 Suggested List Of Socket Types
Table 28. Suggested List of TQFP64 Socket Types
Package / Probe
TQFP64
EMU PROBE
Adaptor / Socket Reference
Socket type
Open Top
ENPLAS
OTQ-64-0.8-02
YAMAICHI
YAMAICHI
IC51-0644-1240.KS-14584
IC149-064-008-S5
Clamshell
SMC
Suggested List of TQFP44 Socket Types
Package / Probe
TQFP44
Adaptor / Socket Reference
OTQ-44-0.8-04
Socket type
ENPLAS
Open Top
Clamshell
YAMAICHI
IC51-0444-467-KS-11787
TQFP44
EMU PROBE
YAMAICHI
IC149-044-*52-S5
SMC
148/153
ST72334J/N, ST72314J/N, ST72124J
18.4 ST7 APPLICATION NOTES
IDENTIFICATION
DESCRIPTION
EXAMPLE DRIVERS
AN 969
AN 970
AN 971
AN 972
AN 973
AN 974
AN 976
AN 979
AN 980
AN1017
AN1041
AN1042
AN1044
AN1045
AN1046
AN1047
AN1048
AN1078
AN1082
AN1083
AN1105
AN1129
SCI COMMUNICATION BETWEEN ST7 AND PC
SPI COMMUNICATION BETWEEN ST7 AND EEPROM
I²C COMMUNICATING BETWEEN ST7 AND M24CXX EEPROM
ST7 SOFTWARE SPI MASTER COMMUNICATION
SCI SOFTWARE COMMUNICATION WITH A PC USING ST72251 16-BIT TIMER
REAL TIME CLOCK WITH ST7 TIMER OUTPUT COMPARE
DRIVING A BUZZER THROUGH ST7 TIMER PWM FUNCTION
DRIVING AN ANALOG KEYBOARD WITH THE ST7 ADC
ST7 KEYPAD DECODING TECHNIQUES, IMPLEMENTING WAKE-UP ON KEYSTROKE
USING THE ST7 UNIVERSAL SERIAL BUS MICROCONTROLLER
USING ST7 PWM SIGNAL TO GENERATE ANALOG OUTPUT (SINUSOID)
ST7 ROUTINE FOR I²C SLAVE MODE MANAGEMENT
MULTIPLE INTERRUPT SOURCES MANAGEMENT FOR ST7 MCUS
ST7 S/W IMPLEMENTATION OF I²C BUS MASTER
UART EMULATION SOFTWARE
MANAGING RECEPTION ERRORS WITH THE ST7 SCI PERIPHERALS
ST7 SOFTWARE LCD DRIVER
PWM DUTY CYCLE SWITCH IMPLEMENTING TRUE 0% & 100% DUTY CYCLE
DESCRIPTION OF THE ST72141 MOTOR CONTROL PERIPHERAL REGISTERS
ST72141 BLDC MOTOR CONTROL SOFTWARE AND FLOWCHART EXAMPLE
ST7 PCAN PERIPHERAL DRIVER
PERMANENT MAGNET DC MOTOR DRIVE.
AN INTRODUCTION TO SENSORLESS BRUSHLESS DC MOTOR DRIVE APPLICATIONS
WITH THE ST72141
AN1130
AN1148
AN1149
AN1180
AN1276
AN1321
AN1325
AN1445
AN1475
AN1504
USING THE ST7263 FOR DESIGNING A USB MOUSE
HANDLING SUSPEND MODE ON A USB MOUSE
USING THE ST7263 KIT TO IMPLEMENT A USB GAME PAD
BLDC MOTOR START ROUTINE FOR THE ST72141 MICROCONTROLLER
USING THE ST72141 MOTOR CONTROL MCU IN SENSOR MODE
USING THE ST7 USB LOW-SPEED FIRMWARE V4.X
USING THE ST7 SPI TO EMULATE A 16-BIT SLAVE
DEVELOPING AN ST7265X MASS STORAGE APPLICATION
STARTING A PWM SIGNAL DIRECTLY AT HIGH LEVEL USING THE ST7 16-BIT TIMER
PRODUCT EVALUATION
AN 910
AN 990
AN1077
AN1086
AN1150
AN1151
AN1278
PERFORMANCE BENCHMARKING
ST7 BENEFITS VERSUS INDUSTRY STANDARD
OVERVIEW OF ENHANCED CAN CONTROLLERS FOR ST7 AND ST9 MCUS
U435 CAN-DO SOLUTIONS FOR CAR MULTIPLEXING
BENCHMARK ST72 VS PC16
PERFORMANCE COMPARISON BETWEEN ST72254 & PC16F876
LIN (LOCAL INTERCONNECT NETWORK) SOLUTIONS
PRODUCT MIGRATION
AN1131
AN1322
AN1365
MIGRATING APPLICATIONS FROM ST72511/311/214/124 TO ST72521/321/324
MIGRATING AN APPLICATION FROM ST7263 REV.B TO ST7263B
GUIDELINES FOR MIGRATING ST72C254 APPLICATION TO ST72F264
PRODUCT OPTIMIZATION
149/153
ST72334J/N, ST72314J/N, ST72124J
IDENTIFICATION
DESCRIPTION
AN 982
AN1014
AN1015
AN1040
AN1070
AN1324
AN1477
AN1502
AN1529
USING ST7 WITH CERAMIC RESONATOR
HOW TO MINIMIZE THE ST7 POWER CONSUMPTION
SOFTWARE TECHNIQUES FOR IMPROVING MICROCONTROLLER EMC PERFORMANCE
MONITORING THE VBUS SIGNAL FOR USB SELF-POWERED DEVICES
ST7 CHECKSUM SELF-CHECKING CAPABILITY
CALIBRATING THE RC OSCILLATOR OF THE ST7FLITE0 MCU USING THE MAINS
EMULATED DATA EEPROM WITH XFLASH MEMORY
EMULATED DATA EEPROM WITH ST7 HDFLASH MEMORY
EXTENDING THE CURRENT & VOLTAGE CAPABILITY ON THE ST7265 VDDF SUPPLY
ACCURATE TIMEBASE FOR LOW-COST ST7 APPLICATIONS WITH INTERNAL RC OSCIL-
LATOR
AN1530
PROGRAMMING AND TOOLS
AN 978
AN 983
AN 985
AN 986
AN 987
AN 988
AN 989
AN1039
AN1064
AN1071
AN1106
KEY FEATURES OF THE STVD7 ST7 VISUAL DEBUG PACKAGE
KEY FEATURES OF THE COSMIC ST7 C-COMPILER PACKAGE
EXECUTING CODE IN ST7 RAM
USING THE INDIRECT ADDRESSING MODE WITH ST7
ST7 SERIAL TEST CONTROLLER PROGRAMMING
STARTING WITH ST7 ASSEMBLY TOOL CHAIN
GETTING STARTED WITH THE ST7 HIWARE C TOOLCHAIN
ST7 MATH UTILITY ROUTINES
WRITING OPTIMIZED HIWARE C LANGUAGE FOR ST7
HALF DUPLEX USB-TO-SERIAL BRIDGE USING THE ST72611 USB MICROCONTROLLER
TRANSLATING ASSEMBLY CODE FROM HC05 TO ST7
PROGRAMMING ST7 FLASH MICROCONTROLLERS IN REMOTE ISP MODE (IN-SITU PRO-
GRAMMING)
AN1179
AN1446
AN1478
AN1527
AN1575
USING THE ST72521 EMULATOR TO DEBUG A ST72324 TARGET APPLICATION
PORTING AN ST7 PANTA PROJECT TO CODEWARRIOR IDE
DEVELOPING A USB SMARTCARD READER WITH ST7SCR
ON-BOARD PROGRAMMING METHODS FOR XFLASH AND HDFLASH ST7 MCUS
150/153
ST72334J/N, ST72314J/N, ST72124J
19 IMPORTANT NOTES
19.1 SCI Baud rate registers
Caution: The SCI baud rate register (SCIBRR)
MUST NOT be written to (changed or refreshed)
while the transmitter or the receiver is enabled.
151/153
ST72334J/N, ST72314J/N, ST72124J
20 SUMMARY OF CHANGES
Description of the changes between the current release of the specification and the previous one.
Revision
Main changes
Date
Replaced Note by Caution in “Conventional Baud Rate Generation” on page 91
Changed Watchdog and Halt mode Option to read “Watchdog reset on Halt” in Section 18
Please read carefully the Section “IMPORTANT NOTES” on page 151
2.5
April-03
152/153
ST72334J/N, ST72314J/N, ST72124J
Notes:
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
2003 STMicroelectronics - All Rights Reserved.
Purchase of I2C Components by STMicroelectronics conveys a license under the Philips I2C Patent. Rights to use these components in an
I2C system is granted provided that the system conforms to the I2C Standard Specification as defined by Philips.
STMicroelectronics Group of Companies
Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan
Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A.
http://www.st.com
153/153
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8-BIT, FLASH, 8MHz, MICROCONTROLLER, PQFP64, 10 X 10 MM, PLASTIC, TQFP-64
STMICROELECTR
ST72P361AR4TA/XXXE
8-BIT, MROM, 8MHz, MICROCONTROLLER, PQFP64, 10 X 10 MM, ROHS COMPLIANT, LQFP-64
STMICROELECTR
ST72P361AR4TA/XXXR
8-BIT, MROM, 8MHz, MICROCONTROLLER, PQFP64, 10 X 10 MM, ROHS COMPLIANT, LQFP-64
STMICROELECTR
ST72P361AR4TA/XXXRE
8-BIT, MROM, 8MHz, MICROCONTROLLER, PQFP64, 10 X 10 MM, ROHS COMPLIANT, LQFP-64
STMICROELECTR
ST72P361AR4TA/XXXS
8-BIT, MROM, 8MHz, MICROCONTROLLER, PQFP64, 10 X 10 MM, ROHS COMPLIANT, LQFP-64
STMICROELECTR
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