ST72T141K2MARE_技术文档

ST72141K2-Auto

8-bit MCU for automotive with electric-motor control,

ADC, 16-bit timers, SPI interface

■ Memories

– 8 Kbytes Program memory (OTP/EPROM)

– 256 bytes RAM

■ Clock, Reset and Supply Management

– Enhanced reset system

– Low voltage supply supervisor

– 3 power saving modes

■ 14 I/O Ports

– 14 multifunctional bidirectional I/O lines with:

External interrupt capability (2 vectors), 13 al-

ternate function lines, 3 high sink outputs

SO34S

■ Motor Control peripheral

– 6 PWM output channels

– Emergency pin to force outputs to HiZ state

– 3 analog inputs for rotor position detection

with no need for additional sensors

– Comparator for current limitation

■ 3 Timers

■ Instruction Set

– Two 16-bit timers with: 2 input captures, 2 out-

put compares, external clock input, PWM and

Pulse generator modes

– 8-bit data manipulation

– 63 basic instructions

– 17 main addressing modes

– 8 x 8 unsigned multiply instruction

– True bit manipulation

– Watchdog timer for system integrity

■ Communications Interface

– SPI synchronous serial interface

■ Analog Peripheral

■ Development Tools

– Full hardware/software development package

– 8-bit ADC with 8 input pins

Device Summary

Features

Program memory - bytes

RAM (stack) - bytes

ST72141K2-Auto

8K

256 (64)

Motor control,

Watchdog, Two 16-bit timers,

SPI, ADC

Peripherals

Operating Supply

4V to 5.5V

CPU Frequency

Operating Temperature

Packages

4 or 8 MHz (with 8 or 16 MHz oscillator)

-40°C to +85°C

SO34

Rev. 1

November 2007

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1

Table of Contents

1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.3 EXTERNAL CONNECTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.4 REGISTER AND MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.5 EPROM PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.3 LOW VOLTAGE DETECTOR (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.4 RESET MANAGER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.5 LOW CONSUMPTION OSCILLATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.6 MAIN CLOCK CONTROLLER (MCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.2 NON-MASKABLE SOFTWARE INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.3 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.4 PERIPHERAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.2 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5.3 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.4 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6.2.1 Input Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6.2.2 Output Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6.2.3 Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

6.3.1 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7 MISCELLANEOUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7.2 I/O PORT INTERRUPT SENSITIVITY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7.3 I/O PORT ALTERNATE FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7.4 CLOCK PRESCALER SELECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

131

7.5 MISCELLANEOUS REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

8 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

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Table of Contents

8.1 MOTOR CONTROLLER (MTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

8.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

8.1.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

8.1.3 Application Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

8.1.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

8.1.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

8.1.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

8.1.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

8.2 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

8.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

8.2.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

8.2.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

8.2.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

8.2.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

8.2.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

8.3 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

8.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

8.3.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

8.3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

8.3.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

8.3.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

8.3.6 Summary of Timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

8.3.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

8.4 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

8.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

8.4.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

8.4.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

8.4.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

8.4.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

8.4.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

8.4.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

8.5 8-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

8.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

8.5.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

8.5.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

8.5.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

8.5.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

8.5.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

9 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

9.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

9.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

9.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

9.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

9.1.4 Indexed (No Offset, Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

9.1.5 Indirect (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

9.1.6 Indirect Indexed (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

9.1.7 Relative Mode (Direct, Indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

9.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

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Table of Contents

10 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

10.1 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

10.2 RECOMMENDED OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

10.3 DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

10.4 GENERAL TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

10.5 I/O PORT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

10.6 SUPPLY, RESET AND CLOCK CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . 120

10.6.1Supply Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

10.6.2RESET Sequence Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

10.6.3Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

10.7 MEMORY AND PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

11 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

11.1 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

11.1.1Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

11.2 ECOPACK® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

11.3 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

12 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

131

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ST72141K2-Auto

1 GENERAL DESCRIPTION

1.1 INTRODUCTION

The ST72141K2-Auto devices are members of the

ST7 microcontroller family designed specifically

for motor control applications and including A/D

conversion and SPI interface capabilities. They in-

clude an on-chip Motor Controller peripheral for

control of electric brushless motors with or without

sensors. An example application, for 6-step con-

trol of a Permanent Magnet DC motor, is shown in

Figure 1.

Figure 1. Example of a 6-step-controlled Motor

ST7

300V

6

MCO5-0

0

2

4

B

MCIB

I

6

I

1

MTC

I

4

I

3

A

MCIA

MCIC

The ST72141K2-Auto devices are based on a

common industry-standard 8-bit core, featuring an

enhanced instruction set.

C

I

5

2

3

5

1

2

Under software control, they can be placed in

WAIT, SLOW, or HALT mode, reducing power

consumption when the application is in idle or

standby state.

Net

Step

Σ

3

1

2

3

4

5

6

1

0

1

2

3

4

5

The enhanced instruction set and addressing

modes of the ST7 offer both power and flexibility to

software developers, enabling the design of highly

efficient and compact application code. In addition

to standard 8-bit data management, all ST7 micro-

controllers feature true bit manipulation, 8x8 un-

signed multiplication and indirect addressing

modes.

300V

150V

0

A

B

C

300V

150V

0

300V

150V

0

Figure 2. Device Block Diagram

Internal

OSC1

CLOCK

PORT A

OSC

DIV

OSC2

V_DD

8-BIT ADC

TIMER B

PA7:0

(8-bit)

POWER

SUPPLY

LVD

V_SS

TIMER A

OC1A

CONTROL

RESET

MCO5:0

8-bit CORE

ALU

MCIA:C

MCES

MOTOR CTRL

MCCFI

8 Kbyte EPROM

256 byte RAM

PORT B

SPI

PB5:0

(6-bit)

WATCHDOG

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ST72141K2-Auto

1.2 PIN DESCRIPTION

Figure 3. 34-Pin SO Package Pinout

MCIA

MCIB

MCIC

34

33

32

MCO5

1

MCO4

MCO3

2

3

MCCFI

MCO2

MCO1

31

30

29

28

27

26

25

24

23

22

21

20

19

18

4

V

5

DD

V

MCO0

6

SS

V

MCES

7

PP

OCMP1_A

MISO/PB5

8

NC

MOSI/PB4

SCK/PB3

9

PA7/AIN7/OCMP2_A

PA6/AIN6/ICAP1_A

10

11 EI1

12

SS/ (HS) PB2

EXTCLK_B/ (HS) PB1

EXTCLK_A/ (HS) PB0

OSC1

PA5/AIN5/ICAP2_A

PA4/AIN4/OCMP1_B

PA3/AIN3/OCMP2_B

13

14

EI0

PA2/AIN2/ICAP1_B

PA1/AIN1/ICAP2_B

PA0/AIN0

15

OSC2

16

17

RESET

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ST72141K2-Auto

PIN DESCRIPTION (Cont’d)

Legend / Abbreviations:

Type:

I = input, O = output, S = supply

A = Dedicated analog input

Input level:

In/Output level: C = CMOS 0.3V /0.7V

DD

C = CMOS 0.3V /0.7V with input trigger

T

DD

Output level:

HS = high sink (on N-buffer only),

R = 70Ω/100Ω ratio of logical levels.

Analog level if used as PWM filtered with an external capacitor

Port configuration capabilities:

– Input:

float = floating, wpu = weak pull-up, int = interrupt, ana = analog

OD = open drain, T = true open drain, PP = push-pull

– Output:

Note: The Reset configuration of each pin is shown in bold.

Table 1. SO34 Device Pin Description

Level

Port / Control

Main

Function

(after reset)

No.

Input

Output

Pin Name

Alternate Function

1

2

3

4

5

6

7

8

9

MCO5

O

I

C

X

Motor Control Output Channel 5

Motor Control Output Channel 4

Motor Control Output Channel 3

Motor Control Output Channel 2

Motor Control Output Channel 1

Motor Control Output Channel 0

Motor Control Emergency Stop Input

MCO4

MCO3

MCO2

MCO1

MCO0

MCES

PB5/MISO

NC

C

X

T

I/O

C

X

EI1

X

Port B5

SPI Master In / Slave Out Data

T

Not Connected

10 PB4/MOSI

11 PB3/SCK

12 PB2/SS

I/O

C

X

EI1

X

T

X

Port B4

Port B3

Port B2

Port B1

Port B0

SPI Master Out / Slave In Data

SPI Serial Clock

T

C

HS

SPI Slave Select (active low)

Timer B Input Clock

T

13 PB1/EXTCLK_B

14 PB0/EXTCLK_A

15 OSC1

HS

T

Timer A Input Clock

These pins connect a crystal or ceramic resona-

tor, or an external RC, or an external source to

the on-chip oscillator.

16 OSC2

17 RESET

I/O

C

X

Top priority non-maskable interrupt (active low)

18 PA0/AIN0

C

X

EI0

X

Port A0

Port A1

ADC Analog Input 0

T

Timer B Input Capture 2 or ADC

Analog Input 1

19 PA1/ICAP2_B/AIN1

20 PA2/ICAP1_B/AIN2

I/O

C

EI0

X

Timer B Input Capture 1 or ADC

Analog Input 2

X

Port A2

Port A3

T

Timer B Output Compare 2 or

ADC Analog Input 3

21 PA3/OCMP2_B/AIN3 I/O

7/131

6

ST72141K2-Auto

Level

Port / Control

Main

Function

(after reset)

Input

Output

Pin Name

No.

Alternate Function

Timer B Output Compare 1 or

ADC Analog Input 4

22 PA4/OCMP1_B/AIN4 I/O

C

X

EI0

X

Port A4

Port A5

Port A6

Port A7

T

Timer A Input Capture 2 or ADC

Analog Input 5

23 PA5/ICAP2_A/AIN5

24 PA6/ICAP1_A/AIN6

I/O

Timer A Input Capture 1 or ADC

Analog Input 6

Timer A Output Compare 2 or

ADC Analog Input 7

25 PA7/OCMP2_A/AIN7 I/O

26 NC

Not Connected

27 OCMP1_A

O

I

R

Timer A Output Compare 1

EPROM Programming voltage pin (must be tied

low during normal operating mode)

28

V

PP

29

30

V

S

I

Ground

SS

DD

Main power supply

31 MCCFI

32 MCIC

33 MCIB

34 MCIA

A

Motor Control Current Feedback Input

Motor Control Input C

Motor Control Input B

Motor Control Input A

I

8/131

ST72141K2-Auto

1.3 EXTERNAL CONNECTIONS

The following figure shows the recommended ex-

ternal connections for the device.

The external reset network is intended to protect

the device against parasitic resets, especially in

noisy environments.

The V pin is only used for programming OTP

PP

and EPROM devices and must be tied to ground in

user mode.

Unused I/Os should be tied high to avoid any un-

necessary power consumption on floating lines.

An alternative solution is to program the unused

ports as inputs with pull-up.

The 10nF and 0.1µF decoupling capacitors on the

power supply lines are a suggested EMC perform-

ance/cost tradeoff.

Figure 4. Recommended External Connections

V

PP

DD

SS

V

DD

+

0.1µF

10µF

V

Optional if Low Voltage

Detector (LVD) is used

V

DD

V

DD

4.7K

0.1µF

SS

RESET

EXTERNAL RESET CIRCUIT

See

Clocks

Section

OSC1

OSC2

Or configure unused I/O ports

by software as input with pull-up

10K

V

DD

Unused I/O

9/131

ST72141K2-Auto

1.4 REGISTER AND MEMORY MAP

As shown in Figure 5, the MCU is capable of ad-

dressing 64 Kbytes of memories and I/O registers.

space includes up to 64 bytes for the stack from

0140h to 017Fh.

The available memory locations consist of 128

bytes of register locations, 256 bytes of RAM and

8 Kbytes of user program memory. The RAM

The highest address bytes contain the user reset

and interrupt vectors.

Figure 5. Memory Map

0080h

0000h

HW Registers

Short Addressing

(see Table 3)

007Fh

RAM

0080h

“Zero page”

(128 bytes)

256 bytes RAM

017Fh

00FFh

0100h

0180h

16-bit Addressing

Reserved

DFFFh

E000h

Program Memory

(8 Kbytes)

FFDFh

RAM

(64 bytes)

013Fh

0140h

Stack or

16-bit Addressing

RAM

FFE0h

Interrupt & Reset Vectors

(64 bytes)

017Fh

(see Table 2)

FFFFh

Table 2. Interrupt Vector Map

Vector Address

Description

Remarks

FFE0-FFE1h

FFE2-FFE3h

FFE4-FFE5h

FFE6-FFE7h

FFE8-FFE9h

FFEA-FFEBh

FFEC-FFEDh

FFEE-FFEFh

FFF0-FFF1h

FFF2-FFF3h

FFF4-FFF5h

FFF6-FFF7h

FFF8-FFF9h

FFFA-FFFBh

FFFC-FFFDh

FFFE-FFFFh

Not used

TIMER B interrupt vector

TIMER A interrupt vector

SPI interrupt vector

Motor control interrupt vector (events: E, O)

Motor control interrupt vector (events: C, D)

Motor control interrupt vector (events: R, Z)

External interrupt vector EI1: port B7..0

External interrupt vector EI0: port A7..0

Not used

Internal Interrupt

External Interrupt

TRAP (software) interrupt vector

RESET vector

CPU Interrupt

10/131

ST72141K2-Auto

Table 3. Hardware Register Map

Register

Reset

Status

Address

Block

Register Name

Port A Data Register

Port A Data Direction Register

Port A Option Register

Remarks

R/W

Label

0000h

0001h

0002h

PADR

PADDR

PAOR

00h

Port A

0003h

Reserved Area (1 byte)

0004h

0005h

0006h

PBDR

PBDDR

PBOR

Port B Data Register

Port B Data Direction Register

Port B Option Register

00h

R/W

Port B

0007h

to

001F

Reserved Area (24 bytes)

Miscellaneous Register

0020h

MISCR

00h

R/W

0021h

0022h

0023h

SPIDR

SPICR

SPISR

SPI Data I/O Register

SPI Control Register

SPI Status Register

xxh

0xh

00h

R/W

Read Only

SPI

0024h

0025h

WDGCR

WDGSR

Watchdog Control Register

Watchdog Status Register

7Fh

00h

R/W

WATCHDOG

0026h

to

Reserved Area (11 bytes)

0030h

0031h

0032h

0033h

0034h

0035h

0036h

0037h

0038h

0039h

003Ah

003Bh

003Ch

003Dh

003Eh

003Fh

TACR2

TACR1

TASR

TAIC1HR

TAIC1LR

TAOC1HR

TAOC1LR

TACHR

Timer A Control Register 2

Timer A Control Register 1

Timer A Status Register

Timer A Input Capture 1 High Register

Timer A Input Capture 1 Low Register

Timer A Output Compare 1 High Register

Timer A Output Compare 1 Low Register

Timer A Counter High Register

00h

xxh

80h

00h

FFh

FCh

FFh

FCh

xxh

80h

00h

R/W

Read Only

R/W

TIMER A

Read Only

R/W

TACLR

Timer A Counter Low Register

TAACHR

TAACLR

TAIC2HR

TAIC2LR

TAOC2HR

TAOC2LR

Timer A Alternate Counter High Register

Timer A Alternate Counter Low Register

Timer A Input Capture 2 High Register

Timer A Input Capture 2 Low Register

Timer A Output Compare 2 High Register

Timer A Output Compare 2 Low Register

R/W

0040h

Reserved Area (1 byte)

11/131

ST72141K2-Auto

Register

Label

Reset

Status

Address

Block

Register Name

Remarks

R/W

0041h

0042h

0043h

0044h

0045h

0046h

0047h

0048h

0049h

004Ah

004Bh

004Ch

004Dh

004Eh

004Fh

TBCR2

TBCR1

TBSR

TBIC1HR

TBIC1LR

TBOC1HR

TBOC1LR

TBCHR

Timer B Control Register 2

Timer B Control Register 1

Timer B Status Register

Timer B Input Capture 1 High Register

Timer B Input Capture 1 Low Register

Timer B Output Compare 1 High Register

Timer B Output Compare 1 Low Register

Timer B Counter High Register

00h

xxh

80h

00h

FFh

FCh

FFh

FCh

xxh

80h

00h

R/W

Read Only

R/W

TIMER B

Read Only

R/W

TBCLR

Timer B Counter Low Register

TBACHR

TBACLR

TBIC2HR

TBIC2LR

TBOC2HR

TBOC2LR

Timer B Alternate Counter High Register

Timer B Alternate Counter Low Register

Timer B Input Capture 2 High Register

Timer B Input Capture 2 Low Register

Timer B Output Compare 2 High Register

Timer B Output Compare 2 Low Register

R/W

0050h

to

Reserved Area (16 bytes)

005Fh

0060h

0061h

0062h

0063h

0064h

0065h

0066h

0067h

0068h

0069h

006Ah

006Bh

006Ch

006Dh

MTIM

Timer Counter Register

Zn-1 Capture Register

Zn Capture Register

00h

R/W

MZPRV

MZREG

MCOMP

MDREG

MWGHT

MPRSR

MIMR

C

Compare Register

n+1

D capture/Compare Register

Weight Register

Prescaler and Ratio Register

Interrupt Mask Register

Interrupt Status Register

Control Register A

MOTOR

CONTROL

MISR

MCRA

MCRB

MPHST

MPAR

Control Register B

Phase State Register

Output Parity Register

Output Polarity Register

MPOL

006Eh

to

Reserved Area (2 bytes)

006Fh

0070h

0071h

ADCDR

ADCCSR

Data Register

Control/Status Register

00h

Read Only

R/W

ADC

0072h

to

Reserved Area (14 bytes)

007Fh

12/131

ST72141K2-Auto

1.5 EPROM PROGRAM MEMORY

The program memory of the OTP and EPROM de-

vices can be programmed with EPROM program-

ming tools available from STMicroelectronics.

It is recommended that the EPROM devices be

kept out of direct sunlight, since the UV content of

sunlight can be sufficient to cause functional fail-

ure. Extended exposure to room level fluorescent

lighting may also cause erasure.

EPROM Erasure

EPROM devices are erased by exposure to high

intensity UV light admitted through the transparent

window. This exposure discharges the floating

gate to its initial state through induced photo cur-

rent.

An opaque coating (paint, tape, label, etc.) should

be placed over the package window if the product

is to be operated under these lighting conditions.

Covering the window also reduces I

in power-

DD

saving modes due to photo-diode leakage cur-

rents.

13/131

ST72141K2-Auto

2 CENTRAL PROCESSING UNIT

2.1 INTRODUCTION

Accumulator (A)

The Accumulator is an 8-bit general purpose reg-

ister used to hold operands and the results of the

arithmetic and logic calculations and to manipulate

data.

This CPU has a full 8-bit architecture and contains

six internal registers allowing efficient 8-bit data

manipulation.

Index Registers (X and Y)

2.2 MAIN FEATURES

In indexed addressing modes, these 8-bit registers

are used to create either effective addresses or

temporary storage areas for data manipulation.

(The Cross-Assembler generates a precede in-

struction (PRE) to indicate that the following in-

struction refers to the Y register.)

■ 63 basic instructions

■ Fast 8-bit by 8-bit multiply

■ 17 main addressing modes

■ Two 8-bit index registers

■ 16-bit stack pointer

■ Low power modes

■ Maskable hardware interrupts

■ Non-maskable software interrupt

The Y register is not affected by the interrupt auto-

matic procedures (not pushed to and popped from

the stack).

Program Counter (PC)

The program counter is a 16-bit register containing

the address of the next instruction to be executed

by the CPU. It is made of two 8-bit registers PCL

(Program Counter Low which is the LSB) and PCH

(Program Counter High which is the MSB).

2.3 CPU REGISTERS

The six CPU registers shown in Figure 6 are not

present in the memory mapping and are accessed

by specific instructions.

Figure 6. CPU Registers

7

0

ACCUMULATOR

RESET VALUE = XXh

7

0

X INDEX REGISTER

Y INDEX REGISTER

RESET VALUE = XXh

7

RESET VALUE = XXh

PCL

PCH

7

8

15

0

PROGRAM COUNTER

RESET VALUE = RESET VECTOR @ FFFEh-FFFFh

7

1

0

H I N Z C

X 1 X X X

1

CONDITION CODE REGISTER

RESET VALUE =

8

1

15

7

0

STACK POINTER

RESET VALUE = STACK HIGHER ADDRESS

X = Undefined Value

14/131

ST72141K2-Auto

CPU REGISTERS (Cont’d)

CONDITION CODE REGISTER (CC)

Read/Write

because the I bit is set by hardware at the start of

the routine and reset by the IRET instruction at the

end of the routine. If the I bit is cleared by software

in the interrupt routine, pending interrupts are

serviced regardless of the priority level of the cur-

rent interrupt routine.

Reset Value: 111x1xxx

7

0

1

H

I

N

Z

C

Bit 2 = N Negative

The 8-bit Condition Code register contains the in-

terrupt mask and four flags representative of the

result of the instruction just executed. This register

can also be handled by the PUSH and POP in-

structions.

This bit is set and cleared by hardware. It is repre-

sentative of the result sign of the last arithmetic,

logical or data manipulation. It is a copy of the 7th

bit of the result.

0: The result of the last operation is positive or null.

1: The result of the last operation is negative

(that is, the most significant bit is a logic 1).

These bits can be individually tested and/or con-

trolled by specific instructions.

This bit is accessed by the JRMI and JRPL instruc-

tions.

Bit 4 = H Half carry

This bit is set by hardware when a carry occurs be-

tween bits 3 and 4 of the ALU during an ADD or

ADC instruction. It is reset by hardware during the

same instructions.

Bit 1 = Z Zero

This bit is set and cleared by hardware. This bit in-

dicates that the result of the last arithmetic, logical

or data manipulation is zero.

0: The result of the last operation is different from

zero.

1: The result of the last operation is zero.

0: No half carry has occurred.

1: A half carry has occurred.

This bit is tested using the JRH or JRNH instruc-

tion. The H bit is useful in BCD arithmetic subrou-

tines.

This bit is accessed by the JREQ and JRNE test

instructions.

Bit 3 = I Interrupt mask

This bit is set by hardware when entering in inter-

rupt or by software to disable all interrupts except

the TRAP software interrupt. This bit is cleared by

software.

Bit 0 = C Carry/borrow

This bit is set and cleared by hardware and soft-

ware. It indicates an overflow or an underflow has

occurred during the last arithmetic operation.

0: No overflow or underflow has occurred.

1: An overflow or underflow has occurred.

0: Interrupts are enabled.

1: Interrupts are disabled.

This bit is controlled by the RIM, SIM and IRET in-

structions and is tested by the JRM and JRNM in-

structions.

This bit is driven by the SCF and RCF instructions

and tested by the JRC and JRNC instructions. It is

also affected by the “bit test and branch”, shift and

rotate instructions.

Note: Interrupts requested while I is set are

latched and can be processed when I is cleared.

By default an interrupt routine is not interruptible

15/131

ST72141K2-Auto

CENTRAL PROCESSING UNIT (Cont’d)

Stack Pointer (SP)

The least significant byte of the Stack Pointer

(called S) can be directly accessed by a LD in-

struction.

Read/Write

Reset Value: 01 7Fh

Note: When the lower limit is exceeded, the Stack

Pointer wraps around to the stack upper limit, with-

out indicating the stack overflow. The previously

stored information is then overwritten and there-

fore lost. The stack also wraps in case of an under-

flow.

15

8

1

0

7

0

The stack is used to save the return address dur-

ing a subroutine call and the CPU context during

an interrupt. The user may also directly manipulate

the stack by means of the PUSH and POP instruc-

tions. In the case of an interrupt, the PCL is stored

at the first location pointed to by the SP. Then the

other registers are stored in the next locations as

shown in Figure 7.

SP6

SP5

SP4

SP3

SP2

SP1

SP0

The Stack Pointer is a 16-bit register which is al-

ways pointing to the next free location in the stack.

It is then decremented after data has been pushed

onto the stack and incremented before data is

popped from the stack (see Figure 7).

– When an interrupt is received, the SP is decre-

mented and the context is pushed on the stack.

Since the stack is 128 bytes deep, the 9th most

significant bits are forced by hardware. Following

an MCU Reset, or after a Reset Stack Pointer in-

struction (RSP), the Stack Pointer contains its re-

set value (the SP6 to SP0 bits are set) which is the

stack higher address.

– On return from interrupt, the SP is incremented

and the context is popped from the stack.

A subroutine call occupies two locations and an in-

terrupt five locations in the stack area.

Figure 7. Stack Manipulation Example

CALL

Subroutine

RET

or RSP

PUSH Y

POP Y

IRET

Interrupt

Event

@ 0100h

SP

Y

CC

A

CC

A

CC

A

X

PCH

PCL

PCH

PCL

PCH

PCL

PCH

PCL

PCH

PCL

PCH

PCL

SP

PCH

PCL

PCH

PCL

SP

@ 017Fh

Stack Higher Address = 017Fh

0100h

Stack Lower Address =

16/131

ST72141K2-Auto

3 SUPPLY, RESET AND CLOCK MANAGEMENT

3.1 INTRODUCTION

The ST72141K2-Auto includes a range of utility

features for securing the application in critical situ-

ations (for example in case of a power brown-out),

and reducing the number of external components.

An overview is shown in Figure 8.

3.2 Main Features

■ Main supply low voltage detection (LVD)

■ RESET Manager

■ Low consumption resonator oscillator

■ Main clock controller (MCC)

Figure 8. Clock, RESET, Option and Supply Management Overview

f_{MOTOR_CONTROL}

f_SPI

MAIN CLOCK

OSC2

OSC1

f_OSC

OSCILLATOR

CONTROLLER

(MCC)

f_CPU

FROM

WATCHDOG

PERIPHERAL

RESET

LOW VOLTAGE

DETECTOR

(LVD)

V_DD

V_SS

17/131

ST72141K2-Auto

3.3 LOW VOLTAGE DETECTOR (LVD)

To allow the integration of power management

features in the application, the Low Voltage Detec-

tor function (LVD) generates a static reset when

Provided the minimum V value (guaranteed for

DD

the oscillator frequency) is below V

can only be in two modes:

, the MCU

LVDf

the V supply voltage is below a V

reference

DD

LVDf

– under full software control

– in static safe reset

value. This means that it secures the power-up as

well as the power-down keeping the ST7 in reset.

In these conditions, secure operation is always en-

sured for the application without the need for ex-

ternal reset hardware.

The V

reference value for a voltage drop is

LVDf

lower than the V

reference value for power-on

LVDr

in order to avoid a parasitic reset when the MCU

starts running and sinks current on the supply

(hysteresis).

During a Low Voltage Detector Reset, the RESET

pin is held low, thus permitting the MCU to reset

other devices.

The LVD Reset circuitry generates a reset when

V

is below:

DD

– V

when V is rising

DD

Note:

LVDr

when V is falling

The LVD allows the device to be used without any

external RESET circuitry.

LVDf

DD

The LVD function is illustrated in Figure 9.

Figure 9. Low Voltage Detector vs Reset

V

DD

HYSTERISIS

V

LVDhyst

V

LVDr

LVDf

RESET

18/131

ST72141K2-Auto

3.4 RESET MANAGER

The RESET block includes three RESET sources

as shown in Figure 10:

The RESET service routine vector is fixed at ad-

dresses FFFEh-FFFFh in the ST7 memory map.

– External RESET source pulse

A 4096 CPU clock cycle delay allows the oscillator

to stabilize and ensures that recovery has taken

place from the Reset state.

– Internal LVD RESET (Low Voltage Detection)

– Internal WATCHDOG RESET

The RESET vector fetch phase duration is 2 clock

cycles.

Figure 10. Reset Block Diagram

INTERNAL

RESET

V_DD

f_CPU

R_ON

RESET

WATCHDOG RESET

LVD RESET

19/131

ST72141K2-Auto

RESET MANAGER (Cont’d)

External RESET pin

Generic Power-on RESET

The RESET pin is both an input and an open-drain

The function of the POR circuit consists of waking

up the MCU by detecting (at around 2V) a dynamic

output with integrated R

weak pull-up resistor

ON

(see Figure 10). This pull-up has no fixed value but

varies in accordance with the input voltage. It can

be pulled low by external circuitry to reset the de-

vice.

(rising edge) variation of the V supply. At the be-

DD

ginning of this sequence, the MCU is configured in

the RESET state. When the power supply voltage

rises to a sufficient level, the oscillator starts to op-

erate, whereupon an internal 4096 CPU cycles de-

lay is initiated, in order to allow the oscillator to ful-

ly stabilize before executing the first instruction.

The initialization sequence is executed immediate-

ly following the internal delay.

A RESET signal originating from an external

source must have a duration of at least t

in

PULSE

order to be recognized. Two RESET sequences

can be associated with this RESET source as

shown in Figure 11.

To ensure correct start-up, the user should take

When the RESET is generated by an internal

source, during the two first phases of the RESET

sequence, the device RESET pin acts as an out-

put that is pulled low.

care that the V supply is stabilized at a sufficient

DD

level for the chosen frequency (see Section 10

ELECTRICAL CHARACTERISTICS) before the

reset signal is released. In addition, supply rising

must start from 0V.

As a consequence, the POR does not allow to su-

pervise static, slowly rising, or falling, or noisy (os-

cillating) V supplies.

DD

An external RC network connected to the RESET

pin, or the LVD reset can be used instead to get

the best performance.

Figure 11. External RESET Sequences

V

DD

V

DD nominal

LVDf

RESET

RUN

INTERNAL RESET

4096 CLOCK CYCLES

FETCH

VECTOR

DELAY

t

PULSE

EXTERNAL RESET SOURCE

RESET PIN

WATCHDOG RESET

20/131

ST72141K2-Auto

RESET MANAGER (Cont’d)

Internal Low Voltage Detection RESET (option)

In the second sequence, a “delay” phase is used

to keep the device in RESET state until V rises

DD

Two different RESET sequences caused by the in-

ternal LVD circuitry can be distinguished:

up to V

(see Figure 12).

LVDr

- LVD Power-on RESET

- Voltage Drop RESET

Figure 12. LVD RESET Sequences

V

DD

V

DDnominal

LVDr

RESET

POWER-

OFF

RUN

INTERNAL RESET

4096 CLOCK CYCLES VECTOR

FETCH

EXTERNAL RESET SOURCE

RESET PIN

WATCHDOG RESET

V

DD

V

DDnominal

LVDr

LVDf

RESET

RUN

INTERNAL RESET

4096 CLOCK CYCLES VECTOR

FETCH

DELAY

EXTERNAL RESET SOURCE

RESET PIN

WATCHDOG RESET

21/131

ST72141K2-Auto

RESET MANAGER (Cont’d)

Internal Watchdog RESET

The RESET sequence generated by an internal

Watchdog counter overflow has the shortest reset

phase (see Figure 13).

Figure 13. Watchdog RESET Sequence

V

DD

V

DDnominal

V

LVDf

RESET

RUN

INTERNAL RESET

FETCH

4096 CLOCK CYCLES

VECTOR

EXTERNAL RESET SOURCE

t

WDGRST

RESET PIN

WATCHDOG RESET

WATCHDOG UNDERFLOW

22/131

ST72141K2-Auto

3.5 LOW CONSUMPTION OSCILLATOR

Crystal/Ceramic Oscillators

This oscillator (based on constant current source)

is optimized in terms of consumption and has the

advantage of producing a very accurate rate on

the main clock of the ST7.

The main clock of the ST7 can be generated by

two different sources:

– an external source

– a crystal or ceramic resonator oscillators

When using this oscillator, the resonator and the

load capacitances have to be connected as shown

in Figure 15 and have to be mounted as close as

possible to the oscillator pins in order to minimize

output distortion and start-up stabilization time.

External Clock Source

In this mode, a square clock signal with ~50% duty

cycle has to drive the OSC2 pin while the OSC1

pin is tied to V (see Figure 14).

SS

This oscillator is not stopped during the RESET

phase to avoid losing time in the oscillator start-up

phase.

Figure 15. Crystal/Ceramic Resonator

Figure 14. External Clock

ST7

OSC1

OSC2

OSC1

OSC2

EXTERNAL

SOURCE

C

L1

L0

LOAD

CAPACITANCES

23/131

ST72141K2-Auto

3.6 MAIN CLOCK CONTROLLER (MCC)

The MCC block supplies the clock for the ST7

CPU and its internal peripherals. It allows the

SLOW power saving mode and the Motor Control

and SPI peripheral clocks to be managed inde-

pendently. The MCC functionality is controlled by

two bits of the MISCR register: SMS and XT16.

The XT16 bit acts on the clock of the motor control

and SPI peripherals while the SMS bit acts on the

CPU and the other peripherals.

Figure 16. Main Clock Controller (MCC) Block Diagram

OSC2

OSCILLATOR

OSC1

MCC

f

DIV 2

DIV 16

OSC

f

CPU CLOCK

TO CPU AND

PERIPHERALS

CPU

MISCR

XT16

DIV 2

-

SMS

4MHz

MOTOR CONTROL

PERIPHERAL

DIV 2

4MHz

SPI

PERIPHERAL

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ST72141K2-Auto

4 INTERRUPTS

4.1 INTRODUCTION

4.2 NON-MASKABLE SOFTWARE INTERRUPT

The ST7 core may be interrupted by one of two dif-

ferent methods: maskable hardware interrupts as

listed in Table 4 Interrupt Mapping on page 26 and

a non-maskable software interrupt (TRAP). The

Interrupt processing flowchart is shown in Figure

17.

This interrupt is entered when the TRAP instruc-

tion is executed regardless of the state of the I bit.

It will be serviced according to the flowchart in Fig-

ure 17.

4.3 EXTERNAL INTERRUPTS

The maskable interrupts must be enabled by

clearing the I bit in order to be serviced. However,

disabled interrupts may be latched and processed

when they are enabled (see Section 4.3 EXTER-

NAL INTERRUPTS).

External interrupt vectors can be loaded into the

PC register if the corresponding external interrupt

occurred and if the I bit is cleared. These interrupts

allow the processor to leave the Halt low power

mode.

Note: After reset, all interrupts are disabled.

The external interrupt polarity is selected through

the miscellaneous register or interrupt register (if

available).

When an interrupt has to be serviced:

– Normal processing is suspended at the end of

the current instruction execution.

An external interrupt triggered on edge will be

latched and the interrupt request automatically

cleared upon entering the interrupt service routine.

– The PC, X, A and CC registers are saved onto

the stack.

If several input pins, connected to the same inter-

rupt vector, are configured as interrupts, their sig-

nals are logically NANDed before entering the

edge/level detection block.

– The I bit of the CC register is set to prevent addi-

tional interrupts.

– The PC is then loaded with the interrupt vector of

the interrupt to service and the first instruction of

the interrupt service routine is fetched (refer to

Table 4 Interrupt Mapping on page 26 for vector

addresses).

Caution: The type of sensitivity defined in the Mis-

cellaneous or Interrupt register (if available) ap-

plies to the ei source. In case of a NANDed source

(as described on the I/O ports section), a low level

on an I/O pin configured as input with interrupt,

masks the interrupt request even in case of rising-

edge sensitivity.

The interrupt service routine should finish with the

IRET instruction which causes the contents of the

saved registers to be recovered from the stack.

Note: As a consequence of the IRET instruction,

the I bit will be cleared and the main program will

resume.

4.4 PERIPHERAL INTERRUPTS

Different peripheral interrupt flags in the status

register are able to cause an interrupt when they

are active if both:

Priority Management

By default, a servicing interrupt cannot be inter-

rupted because the I bit is set by hardware enter-

ing in interrupt routine.

– The I bit of the CC register is cleared.

– The corresponding enable bit is set in the control

register.

In the case when several interrupts are simultane-

ously pending, a hardware priority defines which

one will be serviced first (see Table 4 Interrupt

Mapping on page 26).

If any of these two conditions is false, the interrupt

is latched and thus remains pending.

Interrupts and Low Power Mode

Clearing an interrupt request is done by:

All interrupts allow the processor to leave the

WAIT low power mode. Only external and specifi-

cally mentioned interrupts allow the processor to

leave the HALT low power mode (refer to the “Exit

from HALT” column in Table 4 Interrupt Mapping

on page 26).

– Writing “0” to the corresponding bit in the status

register or

– Access to the status register while the flag is set

followed by a read or write of an associated reg-

ister.

Note: The clearing sequence resets the internal

latch. A pending interrupt (that is, waiting to be en-

abled) will therefore be lost if the clear sequence is

executed.

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INTERRUPTS (Cont’d)

Figure 17. Interrupt Processing Flowchart

FROM RESET

N

I BIT SET?

Y

N

INTERRUPT

PENDING?

Y

FETCH NEXT INSTRUCTION

N

IRET?

STACK PC, X, A, CC

SET I BIT

Y

LOAD PC FROM INTERRUPT VECTOR

EXECUTE INSTRUCTION

RESTORE PC, X, A, CC FROM STACK

THIS CLEARS I BIT BY DEFAULT

Table 4. Interrupt Mapping

Exit

from

HALT

Source

Block

Register Priority

Address

Vector

No.

Description

Label

Order

RESET

TRAP

Reset

yes

no

FFFEh-FFFFh

FFFCh-FFFDh

FFFAh-FFFBh

FFF8h-FFF9h

FFF4h-FFF5h

FFF2h-FFF3h

FFF0h-FFF1h

FFEEh-FFEFh

FFECh-FFEDh

FFEAh-FFEBh

FFE8h-FFE9h

FFE6h-FFE7h

FFE4h-FFE5h

FFE2h-FFE3h

FFE0h-FFE1h

Highest

Priority

N/A

Software Interrupt

0

1

Not used

EI0

EI1

External Interrupt Port A7..0 (C5..0*)

External Interrupt Port B7..0 (C5..0*)

Motor Control Interrupt (events: R, Z)

Motor Control Interrupt (events: C, D)

Motor Control Interrupt (events: E, O)

SPI Peripheral Interrupts

TIMER A Peripheral Interrupts

TIMER B Peripheral Interrupts

Not used

yes

no

N/A

2

3

4

MTC

MISR

no

5

no

6

SPI

SPISR

TASR

TBSR

no

7

TIMER A

TIMER B

no

8

no

9

10

11

12

13

Not used

Not Used

Lowest

Priority

Not Used

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5 POWER SAVING MODES

5.1 INTRODUCTION

To give a large measure of flexibility to the applica-

tion in terms of power consumption, three main

power saving modes are implemented in the ST7

(see Figure 18).

After a RESET the normal operating mode is se-

lected by default (RUN mode). This mode drives

the device (CPU and embedded peripherals) by

means of a master clock which is based on the

main oscillator frequency divided by 2 (f

).

CPU

From Run mode, the different power saving

modes may be selected by setting the relevant

register bits or by calling the specific ST7 software

instruction whose action depends on the oscillator

status.

Figure 18. Power saving mode consumption / transitions

HALT

SLOW WAIT

WAIT

SLOW

RUN

High

Low

POWER CONSUMPTION

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POWER SAVING MODES (Cont’d)

5.2 HALT MODE

When entering HALT mode, the I bit in the CC

Register is forced to 0 to enable interrupts.

The HALT mode is the lowest power consumption

mode of the MCU. It is entered by executing the

ST7 “HALT” instruction (see Figure 20).

In the HALT mode the main oscillator is turned off

causing all internal processing to be stopped, in-

cluding the operation of the on-chip peripherals.

All peripherals are not clocked except the ones

which get their clock supply from another clock

generator (such as an external or auxiliary oscilla-

tor).

The MCU can exit HALT mode on reception of ei-

ther an external interrupt or a reset (see Table 2).

When exiting HALT mode by means of a RESET

or an interrupt, the oscillator is immediately turned

on and the 4096 CPU cycle delay is used to stabi-

lize the oscillator. After the start up delay, the CPU

resumes operation by servicing the interrupt or by

fetching the reset vector which woke it up (see Fig-

ure 19).

Figure 19. HALT Mode Timing Overview

4096 CPU CYCLE

RUN

HALT

RUN

DELAY

FETCH

VECTOR

RESET

OR

INTERRUPT

HALT

INSTRUCTION

Figure 20. HALT Mode Flowchart

HALT INSTRUCTION

N

Y

WATCHDOG

ENABLE

HALT

OSCILLATOR

PERIPHERALS

CPU

OFF

0

I BIT

N

4096 clock cycles delay

RESET

Y

N

EXTERNAL*

INTERRUPT

OSCILLATOR

PERIPHERALS

CPU

ON

OSCILLATOR

PERIPHERALS

CPU

ON

OFF

FETCH RESET VECTOR

OR SERVICE INTERRUPT**

Y

Notes:

External interrupt or internal interrupts with Exit from Halt Mode capability

Before servicing an interrupt, the CC register is pushed on the stack.

*

**

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POWER SAVING MODES (Cont’d)

5.3 WAIT MODE

5.4 SLOW MODE

WAIT mode places the MCU in a low power con-

sumption mode by stopping the CPU.

This mode has two targets:

– To reduce power consumption by decreasing the

internal clock in the device,

This power saving mode is selected by calling the

“WFI” ST7 software instruction.

– To adapt the internal clock frequency (f

the available supply voltage.

) to

CPU

All peripherals remain active. During WAIT mode,

the I bit of the CC register is forced to 0, to enable

all interrupts. All other registers and memory re-

main unchanged. The MCU remains in WAIT

mode until an interrupt or Reset occurs, whereup-

on the Program Counter branches to the starting

address of the interrupt or Reset service routine.

The MCU will remain in WAIT mode until a Reset

or an Interrupt occurs, causing it to wake up.

SLOW mode is controlled by the SMS bit in the

MISCR register. This bit enables or disables Slow

mode selecting the internal slow frequency (f

).

CPU

In this mode, the oscillator frequency can be divid-

ed by 32 instead of 2 in normal operating mode.

The CPU and peripherals are clocked at this lower

frequency except the Motor Control and the SPI

peripherals which have their own clock selection

bit (XT16) in the MISCR register.

Refer to Figure 21.

Figure 21. WAIT Mode Flowchart

OSCILLATOR

PERIPHERALS

CPU

I BIT

ON

OFF

0

WFI INSTRUCTION

N

RESET

If exit is caused by a RESET, a 4096 CPU

clock cycle delay is inserted.

Y

N

INTERRUPT

Y

OSCILLATOR

PERIPHERALS

CPU

ON

OSCILLATOR

PERIPHERALS

CPU

ON

OFF*

OFF

FETCH RESET VECTOR

OR SERVICE INTERRUPT**

Note:

The peripheral clock is stopped only when exit caused by RESET and not by an interrupt.

Before servicing an interrupt, the CC register is pushed on the stack.

*

**

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6 I/O PORTS

6.1 INTRODUCTION

programmable using the sensitivity bits in the Mis-

cellaneous register.

The I/O ports offer different functional modes:

– transfer of data through digital inputs and outputs

Each external interrupt vector is linked to a dedi-

cated group of I/O port pins (see pinout description

and interrupt section). If several input pins are se-

lected simultaneously as interrupt source, these

are logically NANDed. For this reason if one of the

interrupt pins is tied low, it masks the other ones.

and for specific pins:

– external interrupt generation

– alternate signal input/output for the on-chip pe-

ripherals.

An I/O port contains up to 8 pins. Each pin can be

programmed independently as digital input (with or

without interrupt generation) or digital output.

In case of a floating input with interrupt configura-

tion, special care must be taken when changing

the configuration (see Figure 23).

The external interrupts are hardware interrupts,

which means that the request latch (not accessible

directly by the application) is automatically cleared

when the corresponding interrupt vector is

fetched. To clear an unwanted pending interrupt

by software, the sensitivity bits in the Miscellane-

ous register must be modified.

6.2 FUNCTIONAL DESCRIPTION

Each port has two main registers:

– Data Register (DR)

– Data Direction Register (DDR)

and one optional register:

– Option Register (OR)

6.2.2 Output Modes

The output configuration is selected by setting the

corresponding DDR register bit. In this case, writ-

ing the DR register applies this digital value to the

I/O pin through the latch. Then reading the DR reg-

ister returns the previously stored value.

Each I/O pin may be programmed using the corre-

sponding register bits in the DDR and OR regis-

ters: bit X corresponding to pin X of the port. The

same correspondence is used for the DR register.

The following description takes into account the

OR register, (for specific ports which do not pro-

vide this register refer to Section 6.3 I/O PORT IM-

PLEMENTATION). The generic I/O block diagram

is shown in Figure 22.

Two different output modes can be selected by

software through the OR register: Output push-pull

and open-drain.

DR register value and output pin status:

6.2.1 Input Modes

DR

0

Push-pull

Open-drain

V

The input configuration is selected by clearing the

corresponding DDR register bit.

SS

1

V

Floating

DD

In this case, reading the DR register returns the

digital value applied to the external I/O pin.

6.2.3 Alternate Functions

When an on-chip peripheral is configured to use a

pin, the alternate function is automatically select-

ed. This alternate function takes priority over the

standard I/O programming.

Different input modes can be selected by software

through the OR register.

Notes:

1. Writing the DR register modifies the latch value

but does not affect the pin status.

When the signal is coming from an on-chip periph-

eral, the I/O pin is automatically configured in out-

put mode (push-pull or open drain according to the

peripheral).

2. When switching from input to output mode, the

DR register has to be written first to drive the cor-

rect level on the pin as soon as the port is config-

ured as an output.

When the signal is going to an on-chip peripheral,

the I/O pin must be configured in input mode. In

this case, the pin state is also digitally readable by

addressing the DR register.

3. Do not use read/modify/write instructions (BSET

or BRES) to modify the DR register.

External interrupt function

When an I/O is configured as Input with Interrupt,

an event on this I/O can generate an external inter-

rupt request to the CPU.

Note: Input pull-up configuration can cause unex-

pected value at the input of the alternate peripheral

input. When an on-chip peripheral use a pin as in-

put and output, this pin has to be configured in in-

put floating mode.

Each pin can independently generate an interrupt

request. The interrupt sensitivity is independently

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I/O PORTS (Cont’d)

Figure 22. I/O Port General Block Diagram

ALTERNATE

OUTPUT

1

0

REGISTER

ACCESS

P-BUFFER

(see table below)

V

DD

ALTERNATE

ENABLE

PULL-UP

(see table below)

DR

DDR

OR

V

DD

PULL-UP

CONFIGURATION

PAD

If implemented

OR SEL

DDR SEL

DR SEL

N-BUFFER

DIODES

(see table below)

ANALOG

INPUT

CMOS

SCHMITT

TRIGGER

1

0

ALTERNATE

INPUT

EXTERNAL

INTERRUPT

SOURCE (ei )

FROM

OTHER

BITS

x

POLARITY

SELECTION

Table 5. I/O Port Mode Options

Configuration Mode

Diodes

Pull-Up

P-Buffer

to V

SS

DD

Floating with/without Interrupt

Pull-up with/without Interrupt

Push-pull

Off

On

Input

Off

On

Off

On

Off

NI

Output

Open Drain (logic level)

True Open Drain

NI

NI (see note)

Legend: NI - not implemented

Off - implemented not activated

On - implemented and activated

Note: The diode to V is not implemented in the

DD

true open drain pads. A local protection between

the pad and V is implemented to protect the de-

SS

vice against positive stress.

31/131

ST72141K2-Auto

I/O PORTS (Cont’d)

Table 6. I/O Port Configurations

Hardware Configuration

DR REGISTER ACCESS

NOT IMPLEMENTED IN

TRUE OPEN DRAIN

I/O PORTS

V

DD

PULL-UP

CONFIGURATION

R

W

R

PU

DR

REGISTER

DATA BUS

PAD

ALTERNATE INPUT

FROM

OTHER

PINS

EXTERNAL INTERRUPT

SOURCE (ei )

x

INTERRUPT

CONFIGURATION

POLARITY

SELECTION

ANALOG INPUT

NOT IMPLEMENTED IN

TRUE OPEN DRAIN

I/O PORTS

DR REGISTER ACCESS

V

DD

R

PU

R/W

DR

REGISTER

DATA BUS

PAD

ALTERNATE

ENABLE

ALTERNATE

OUTPUT

NOT IMPLEMENTED IN

TRUE OPEN DRAIN

I/O PORTS

DR REGISTER ACCESS

V

DD

R

PU

R/W

DR

REGISTER

DATA BUS

PAD

ALTERNATE

ENABLE

ALTERNATE

OUTPUT

Notes:

1. When the I/O port is in input configuration and the associated alternate function is enabled as an output, reading the

DR register will read the alternate function output status.

2. When the I/O port is in output configuration and the associated alternate function is enabled as an input, the alternate

function reads the pin status given by the DR register content.

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ST72141K2-Auto

I/O PORTS (Cont’d)

CAUTION: The alternate function must not be ac-

tivated as long as the pin is configured as input

with interrupt, in order to avoid generating spurious

interrupts.

and specific feature of the I/O port such as ADC In-

put or true open drain.

Switching these I/O ports from one state to anoth-

er should be done in a sequence that prevents un-

wanted side effects. Recommended safe transi-

tions are illustrated in Figure 23. Other transitions

are potentially risky and should be avoided, since

they are likely to present unwanted side-effects

such as spurious interrupt generation.

Analog alternate function

When the pin is used as an ADC input, the I/O

must be configured as floating input. The analog

multiplexer (controlled by the ADC registers)

switches the analog voltage present on the select-

ed pin to the common analog rail which is connect-

ed to the ADC input.

Figure 23. Interrupt I/O Port State Transitions

It is recommended not to change the voltage level

or loading on any port pin while conversion is in

progress. Furthermore it is recommended not to

have clocking pins located close to a selected an-

alog pin.

01

00

10

11

INPUT

OUTPUT

open-drain

OUTPUT

push-pull

floating/pull-up floating

interrupt (reset state)

WARNING: The analog input voltage level must

be within the limits stated in the absolute maxi-

mum ratings.

= DDR, OR

XX

The I/O port register configurations are summa-

rized as follows.

6.3 I/O PORT IMPLEMENTATION

The hardware implementation on each I/O port de-

pends on the settings in the DDR and OR registers

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ST72141K2-Auto

I/O PORTS (Cont’d)

Interrupt Ports

PA7:0, PB5:3 (with pull-up)

MODE

DDR

OR

floating input

0

1

0

1

0

1

pull-up interrupt input

open drain output

push-pull output

True Open Drain Interrupt Ports

PB2:0 (without pull-up)

MODE

DDR

OR

floating input

0

1

0

1

floating interrupt input

true open drain (high sink ports)

X

Table 7. Port Configuration

Input

Output

Port

Pin name

OR = 0

OR = 1

OR = 0

OR = 1

Port A

Port B

PA7:0

PB5:3

PB2:0

floating

pull-up interrupt

open drain

push-pull

floating interrupt

true open drain

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ST72141K2-Auto

I/O PORTS (Cont’d)

6.3.1 Register Description

DATA REGISTER (DR)

OPTION REGISTER (OR)

Port x Data Register

PxDR with x = A or B.

Port x Option Register

PxOR with x = A or B.

Read/Write

Reset Value: 0000 0000 (00h)

7

0

7

0

D7

D6

D5

D4

D3

D2

D1

D0

O7

O6

O5

O4

O3

O2

O1

O0

Bit 7:0 = D[7:0] Data register 8 bits.

Bit 7:0 = O[7:0] Option register 8 bits.

The DR register has a specific behavior according

to the selected input/output configuration. Writing

the DR register is always taken into account even

if the pin is configured as an input; this allows to al-

ways have the expected level on the pin when tog-

gling to output mode. Reading the DR register re-

turns either the DR register latch content (pin con-

figured as output) or the digital value applied to the

I/O pin (pin configured as input).

For specific I/O pins, this register is not implement-

ed. In this case the DDR register is enough to se-

lect the I/O pin configuration.

The OR register allows to distinguish: in input

mode if the pull-up with interrupt capability or the

basic pull-up configuration is selected, in output

mode if the push-pull or open drain configuration is

selected.

Each bit is set and cleared by software.

Input mode:

DATA DIRECTION REGISTER (DDR)

Port x Data Direction Register

PxDDR with x = A or B.

0: Floating input

1: Pull-up input with or without interrupt

Output mode:

0: Output open drain (with P-Buffer unactivated)

1: Output push-pull (when available)

Read/Write

Reset Value: 0000 0000 (00h)

7

0

DD7

DD6

DD5

DD4

DD3

DD2

DD1

DD0

Bit 7:0 = DD[7:0] Data direction register 8 bits.

The DDR register gives the input/output direction

configuration of the pins. Each bits is set and

cleared by software.

0: Input mode

1: Output mode

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I/O PORTS (Cont’d)

Table 8. I/O Port Register Map and Reset Values

Address (Hex.)

Register Label

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset value of all I/O port registers

0000h

0001h

0002h

0004h

0005h

0006h

PADR

PADDR

PAOR

PBDR

PBDDR

PBOR

MSB

LSB

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ST72141K2-Auto

7 MISCELLANEOUS REGISTER

7.1 INTRODUCTION

7.3 I/O PORT ALTERNATE FUNCTIONS

The miscellaneous register allows control over

several different features such as the external in-

terrupts or the I/O alternate functions.

The MISCR register manages the SPI SS pin al-

ternate function configuration. This makes it possi-

ble to use the PB2 I/O port function while the SPI is

active.

These functions are described in detail in Section

7.5 MISCELLANEOUS REGISTER DESCRIP-

TION.

7.2 I/O PORT INTERRUPT SENSITIVITY

DESCRIPTION

The external interrupt sensitivity is controlled by

the ISxx bits of the Miscellaneous register. This

control allows to have two fully independent exter-

nal interrupt source sensitivities as shown in Fig-

ure 24.

7.4 CLOCK PRESCALER SELECTION

The MISCR register is used to select the SLOW

mode (see Section 5.4 SLOW MODE for more de-

tails) and the SPI and Motor Control peripheral

clock prescaler.

Each external interrupt source can be generated

on four different events on the pin:

– Falling edge

– Rising edge

– Falling and rising edge

– Falling edge and low level

To guaranty correct functionality, a modification of

the sensitivity in the MISCR register must be done

only when the I bit of the CC register is set to 1 (in-

terrupt masked). See I/O port register and Miscel-

laneous register descriptions for more details on

the programming.

Figure 24. External Interrupt Sensitivity

MISCR

IS01

IS00

EI0

PA7

PA0

INTERRUPT

SOURCE

SENSITIVITY

CONTROL

MISCR

IS11

IS10

EI1

PB7

PB0

INTERRUPT

SOURCE

SENSITIVITY

CONTROL

37/131

ST72141K2-Auto

MISCELLANEOUS REGISTER (Cont’d)

7.5

MISCELLANEOUS

REGISTER

DESCRIPTION

Bits 4:3 = IS1[1:0] EI1 sensitivity

The interrupt sensitivity defined using the IS1[1:0]

bits combination is applied to the EI1 external in-

terrupts. These two bits can be written only when

the I bit of the CC register is set to 1 (interrupt

masked).

MISCELLANEOUS REGISTER (MISCR)

Read/Write

Reset Value: 0000 0000 (00h)

EI1: Port B

7

0

IS11 IS10

External Interrupt Sensitivity

Falling edge & low level

Rising edge only

XT16 SSM SSI IS11 IS10 IS01 IS00 SMS

0

1

0

1

0

1

Bit 7 = XT16 MTC and SPI clock selection

This bit is set and cleared by software. The maxi-

mum allowed frequency is 4MHz.

Falling edge only

Rising and falling edge

0: MTC and SPI clock supplied with f

1: MTC and SPI clock supplied with f

/2

/4

OSC

Bits 2:1 = IS0[1:0] EI0 sensitivity

The interrupt sensitivity defined using the IS0[1:0]

bits combination is applied to the EI1 external in-

terrupts. These two bits can be written only when

the I bit of the CC register is set to 1 (interrupt

masked).

Bit 6 = SSM SS mode selection

This bit is set and cleared by software.

0: Normal mode - the level of the SPI SS signal is

the external SS pin.

1: I/O mode, the level of the SPI SS signal is read

from the SSI bit.

EI0: Port A

IS01 IS00

External Interrupt Sensitivity

Falling edge & low level

Rising edge only

Bit 5 = SSI SS internal mode

0

1

0

1

0

1

This bit replaces the SS pin of the SPI when the

SSM bit is set to 1. (see SPI description). It is set

and cleared by software.

Falling edge only

Rising and falling edge

Bit 0 = SMS Slow mode select

This bit is set and cleared by software.

0: Normal mode. f

= f_OSC/ 2

CPU

1: Slow mode. f

= f_OSC/ 32

CPU

See sections on low power consumption mode

and MCC for more details.

Table 9. Miscellaneous Register Map and Reset Values

Address

(Hex.)

Register

Label

7

6

5

4

3

2

1

0

MISCR

Reset Value

XT16

0

SSM

0

SSI

0

IS11

0

IS10

0

IS01

0

IS00

0

SMS

0

0020h

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ST72141K2-Auto

8 ON-CHIP PERIPHERALS

8.1 MOTOR CONTROLLER (MTC)

8.1.1 Introduction

– The output polarity is programmable channel

by channel.

The ST7 Motor Controller (MTC) can be seen as a

Pulse Width Modulator multiplexed on six output

channels, and a Back Electromotive Force

(BEMF) zero-crossing detector for sensorless con-

trol of Permanent Magnet Direct Current (PMDC)

brushless motors.

– An software enabled bit (active low) forces the

outputs in HiZ.

– An “emergency stop” input pin (active low)

asynchronously forces the outputs in HiZ.

Table 10. MTC Registers

The MTC is particularly suited to driving synchro-

nous motors and supports operating modes like:

Register Description

MTIM Timer Counter Register

MZPRV Capture Z Register

Page

66

67

68

69

70

– Commutation step control with motor voltage

regulation and current limitation

n-1

MZREG Capture Z Register

n

– Commutation step control with motor current

regulation, i.e. direct torque control

MCOMP Compare C

Register

n+1

MDREG Demagnetization Register

– Sensor or sensorless motor phase commutation

control

MWGHT A Weight Register

n

MPRSR Prescaler and Sampling Register

– BEMF zero-crossing detection with high sensitiv-

ity. The integrated phase voltage comparator is

directly referred to the full BEMF voltage without

any attenuation. A BEMF voltage down to

200mV can be detected, providing high noise im-

munity and self-commutated operation in a large

speed range.

MIMR

MISR

Interrupt Mask Register

Interrupt Status Register

Control Register A

MCRA

MCRB

Control Register B

MPHST Phase State Register

MPAR

MPOL

Parity Register

Polarity Register

– Realtime motor winding demagnetization detec-

tion for fine-tuning the phase voltage masking

time to be applied before BEMF monitoring.

8.1.3 Application Example

– Automatic and programmable delay between

BEMF zero-crossing detection and motor phase

commutation.

This example shows a six-step command se-

quence for a 3-phase permanent magnet DC

brushless motor (PMDC motor). Figure 26 shows

the phase steps and voltage, while Table 11

shows the relevant phase configurations.

8.1.2 Main Features

■ 2 on-chip analog comparators, one for BEMF

zero-crossing detection with 100mV hysteresis,

the other for current regulation or limitation

■ 4 selectable reference voltages for the

hysteresis comparator (0.2 V, 0.6 V, 1.2 V,

2.5 V)

To run this kind of motor efficiently, an autoswitch-

ing mode has to be used, that is, the position of the

rotor must self-generate the powered winding

commutation. The BEMF zero crossing (Z event)

on the non-excited winding is used by the MTC as

a rotor position sensor. The delay between this

event and the commutation is computed by the

■ 8-bit timer (MTIM) with two compare registers

and two capture features

MTC and the commutation event C is automati-

n

■ Measurement window generator for BEMF

cally generated after this delay.

zero-crossing detection

After the commutation occurs, the MTC waits until

the winding is completely demagnetized by the

free-wheeling diode: during this phase the winding

is tied to 0V or to the HV high voltage rail and no

BEMF can be read. At the end of this phase a new

BEMF zero-crossing detection is enabled.

■ Auto-calibrated prescaler with 16 division steps

■ 8x8-bit multiplier

■ Phase input multiplexer

■ Sophisticated output management:

– The six output channels can be split into two

The end of demagnetization event (D), is also de-

tected by the MTC or simulated with a timer com-

pare feature when no detection is possible.

groups (odd and even).

– The PWM signal can be multiplexed on even,

odd or both groups, alternatively or simultane-

ously.

39/131

ST72141K2-Auto

MOTOR CONTROLLER (Cont’d)

The MTC manages these three events always in

the same order: Z generates C after a delay com-

puted in realtime, then waits for D in order to ena-

ble the peripheral to detect another Z event.

All detections of Z events are done during a short

n

measurement window while the high side switch is

turned off. For this reason the PWM signal is ap-

plied on the high side switches.

The speed regulation is managed by the micro-

controller, by means of an adjustable reference

current level in case of current control, or by direct

PWM duty-cycle adjustment in case of voltage

control.

When the high side switch is off, the high side

winding is tied to 0V by the free-wheeling diode,

the low side winding voltage is also held at 0V by

the low side ON switch and the complete BEMF

voltage is present on the third winding: detection is

then possible.

Figure 25. Chronogram of Events (in Autoswitched Mode)

C event

Z event

D

event

H

D event

S

Cn processing

Wait for C

Wait for D

n

Wait for Z

Z > Z

T

Z

n min

C > C

n

n min

D

C

n

t

Voltage on phase A

Voltage on phase B

Voltage on phase C

BEMF

sampling

P signal when sampled

(Output of the

V

DD

analog MUX)

V

REF

V

(Threshold value for

SS

Input comparator)

40/131

ST72141K2-Auto

MOTOR CONTROLLER (Cont’d)

Figure 26. Example of Command Sequence for 6-step Mode (typical 3-phase PMDC Motor Control)

Σ

3

1

2

3

4

5

6

1

2

Step

HV

Switch

0

1

2

3

4

T0

T2

T4

B

I

6

1

I

4

I

3

I

A

5

2

C

I

5

Node

HV

HV/2

0

A

B

C

T3

T5

T1

HV

HV/2

0

HV

HV/2

0

Note: Control & sampling PWM influence is not represented on these simplified chronograms.

Σ

5

6

1

2

3

4

HV

C

2

C

4

D

2

HV/2

Superimposed voltage

(BEMF induced by rotor)

- approx. HV/2 (PWM on)

- approx. 0V (PWM off)

0V

Z

D

Z

5

2

t

PWM off pulses

Demagnetization

Commutation delay

Wait for BEMF = 0

41/131

ST72141K2-Auto

MOTOR CONTROLLER (Cont’d)

Table 11. Step Configuration Summary

Step

Configuration

Σ

6

1

2

3

4

5

Current direction

High side

A to B

T0

A to C

T0

B to C

T2

B to A

T2

C to A

T4

C to B

T4

Low side

T5

T1

T3

T5

OO[5:0] bits in MPHST register

Measurement done on:

IS[1:0] bits in MPHST register

Back EMF shape

100001

MCIC

10

000011

MCIB

01

000110

MCIA

00

001100

MCIC

10

011000

MCIB

01

110000

MCIA

00

Falling

Rising

Falling

Rising

Falling

Rising

CPB bit in MCRB register

(ZVD bit = 0)

0

1

0

1

0

1

Voltage on measured point at the

start of demagnetization

0V

HV

0V

HV

0V

HV

HDM-SDM bits in MCRB register

10

11

10

11

10

11

PWM side selection to accelerate de-

magnetization

Odd Side Even Side Odd Side Even Side Odd Side Even Side

Driver selection to accelerate de-

magnetization

T5

T0

T1

T2

T3

T4

For a detailed description of the MTC registers, see Section 8.1.7.

42/131

ST72141K2-Auto

MOTOR CONTROLLER (Cont’d)

8.1.4 Functional Description

– The CHANNEL MANAGER with the PWM multi-

plexer, polarity programming capability and

emergency HiZ configuration input

The MTC can be split into four main parts as

shown in the simplified block diagram in Figure 27.

8.1.4.1 Input Detection Block

– The BEMF ZERO-CROSSING DETECTOR with

a comparator and an input multiplexer

This block can operate in sensor mode or sensor-

less mode. The mode is selected via the SR bit in

the MCRA register. The block diagram is shown in

Figure 28.

– The DELAY MANAGER with an 8-bit timer

(MTIM) and an 8x8 bit multiplier

– The PWM MANAGER, including a measurement

window generator, a mode selector and a current

comparator

Figure 27. Simplified MTC Block Diagram

BEMF ZERO-CROSSING

DETECTOR

DELAY MANAGER

MCIA

BEMF=0

[Z]

MCIB

MCIC

MTIM

TIMER

DELAY

CAPTURE Zn

WEIGHT

Internal V

REF

=?

DELAY = WEIGHT x Zn

COMMUTE [C]

MCO5

MCO4

MCO3

MCO2

MCO1

MCO0

MEASUREMENT

WINDOW

GENERATOR

(I)

CURRENT

VOLTAGE

(V)

(I)

(V)

MODE

NMCES

MCCFI

OCP1A

(V)

(I)

1

PWM ( )

V

DD

C

ext

PWM MANAGER

CHANNEL MANAGER

(I)

R

1ext

(V)

Note 1: The PWM signal is generated by the ST7 16-bit Timer

[Z] : Back EMF Zero-crossing event

R

2ext

Z : Time elapsed between two consecutive Z events

n

[C] : Commutation event

C : Time delayed after Z event to generate C event

n

(I): Current mode

(V): Voltage mode

43/131

ST72141K2-Auto

MOTOR CONTROLLER (Cont’d)

Input Pins

connected to each motor phase through a single

resistor.

The MCIA, MCIB and MCIC input pins can be

used as analog pins in Sensorless mode or as dig-

ital pins in Sensor mode. In sensorless mode, the

analog inputs are used to measure the BEMF zero

crossing and to detect the end of demagnetization

if required. In Sensor mode, they are connected to

sensor outputs.

Note: In high voltage applications, in Sensorless

mode and for certain motors and power topologies

(with parasitic capacitance or other), it may be re-

quired to add external pull-up Schottky 0.4 V (e.g.

BAT48) diodes on the MCIA, MCIB and MCIC

pins.

A multiplexer, programmed by the IS[1:0] bits in

MPHST register selects the input pins and con-

nects them to the rotor position control logic in ei-

ther Sensorless or Sensor mode.

Due to the presence of diodes, these pins can per-

manently support an input current of 5 mA. In Sen-

sorless mode, this feature enables the inputs to be

Figure 28. Input Stage

Event Detection

Input Comparator Block

External Input Block

MPHST Register

IS[1:0]

Input Sel Reg

n

MCIA

MCIB

MCIC

A

B

C

00

C

P

01

10

+

Sample

D

Q

-

CP

V

REF

D

S,H

C

MCRB Register

VR[1:0]

Freq (T = 1.25µs) for demagnetization and sensors

Sampling frequency

I

* = Preload register,

changes taken into

16-bit Timer PWM

V

account at next C event.

MCRA Register

V0C1 bit

Notes:

Reg

Updated/Shifted on

R

MCRB Register MPAR Register

MPAR Register

REO bit

Updated with Reg

on C

n+1

Reg

n

CPB bit*

ZVD bit

n

I

Current Mode

D

C

S,H

Voltage Mode

20µs / D

V

events:

Commutation

BEFM Zero-crossing

or

Z

C

Z

2

1

Sample

D

S,H

End Of Demagnetization

Emergency Stop

Ratio Updated (+1 or -1)

Multiplier Overflow

MCRA Register

SR bit

20µs / C

E

+/-

R

O

or

1

Branch taken after C event

Branch taken after D event

D

H

2

CPB bit* HDM bit*

n

MCRB Register

44/131

ST72141K2-Auto

MOTOR CONTROLLER (Cont’d)

Sensorless Mode

During a short period after a phase commutation

(C event), the winding is no longer excited but

needs a demagnetization phase during which the

BEMF cannot be read. A demagnetization current

goes through the free-wheeling diodes and the

winding voltage is stuck at the high voltage or to

the ground terminal. For this reason an “end of de-

magnetization event” D must be detected on the

winding before the detector can sense a BEMF

zero crossing.

This mode is used to detect BEMF zero crossing

and end of demagnetization events.

The analog phase multiplexer connects the non-

excited motor winding to an analog 100mV hyster-

esis comparator referred to a selectable reference

voltage.

The VR[1:0] bits in the MCRB register select the

reference voltage from four internal values de-

pending on the noise level and the application volt-

age supply.

For the end-of-demagnetization detection, no spe-

cial PWM configuration is needed, the comparator

sensing is done at a fixed 800 kHz sampling fre-

quency.

BEMF detections are performed during the meas-

urement window, when the excited windings are

free-wheeling through the low side switches and

diodes. At this stage the common star connection

So, the three events C (commutation), D (demag-

netization) and Z (BEMF zero crossing) must al-

ways occur in this order.

voltage is near to ground voltage (instead of V /2

DD

when the excited windings are powered) and the

complete BEMF voltage is present on the non-ex-

cited winding terminal, referred to the ground ter-

minal.

The comparator output is processed by a detector

that automatically recognizes the D or Z event, de-

pending on the CPB or ZVD edge and level config-

uration bits as described in Table 12.

The zero crossing sampling frequency is then de-

fined, in current mode, by the measurement win-

dow generator frequency (SA[3:0] bits in the

MPRSR register) or, in voltage mode, by the 16-bit

Timer PWM frequency and duty cycle.

A 20µs filter after a C event disables a D event if

spurious spikes occur.

Another 20µs filter after a D event disables a Z

event if spurious spikes occur.

Table 12. ZVD and CPB Edge Selection Bits

ZVD bit

CPB bit

Event generation vs input data sampled

20-µs filter 20-µs filter

0

C

D

Z

H

20-µs filter 20-µs filter

0

1

0

1

C

D

Z

H

20-µs filter 20-µs filter

C

D

Z

H

20-µs filter 20-µs filter

C

D

H

Note: The ZVD bit is located in the MPAR register, the CPB bit is in the MCRB register.

45/131

ST72141K2-Auto

MOTOR CONTROLLER (Cont’d)

Demagnetization (D) Event

not precede a D event because the latter could

H

be detected as a Z event.

At the end of the demagnetization phase, current

no longer goes through the free-wheeling diodes.

The voltage on the non-excited winding terminal

goes from one of the power rail voltages to the

common star connection voltage plus the BEMF

voltage. In some cases (if the BEMF voltage is

positive and the free-wheeling diodes are at

ground for example) this end of demagnetization

can be seen as a voltage edge on the selected

MCIx input and it is called a hardware demagneti-

Software demagnetization can also be always

used if the HDM bit is reset and the SDM bit is set.

This mode works as a programmable masking

time between the C and Z events. To drive the mo-

tor securely, the masking time must be always

greater than the real demagnetization time in order

to avoid a spurious Z event.

When an event occurs, (either D or D ) the DI bit

H

S

in the MISR register is set and an interrupt request

is generated if the DIM bit of register MIMR is set.

zation event D . See Table 12.

H

If enabled by the HDM bit in the MCRB register,

the current value of the MTIM timer is captured in

register MDREG when this event occurs in order

to be able to simulate the demagnetization phase

for the next steps.

Warning 1: Due to the alternate automatic capture

and compare of the MTIM timer with MDREG reg-

ister by D and D events, the MDREG register

H

S

should be manipulated with special care.

Warning 2: To avoid a system stop, the value writ-

ten to the MDREG register in Soft Demagnetiza-

tion Mode (SDM = 1) should always be:

– Greater than the MCOMP value of the commuta-

tion before the related demagnetization

When enabled by the SDM bit in the MCRB regis-

ter, demagnetization can also be simulated by

comparing the MTIM timer with the MDREG regis-

ter. This kind of demagnetization is called software

demagnetization D .

S

– Greater than the value in the MTIM counter at

that moment (when writing to the MDREG regis-

ter).

If the HDM and SDM bits are both set, the first

event that occurs, triggers a demagnetization

event. For this to work correctly, a D event must

S

Figure 29. D Event Generation Mechanism

§

MTIM [8-bit Up Counter]

D

S,H

C

8

D

H

To Z event detection

MCRA Register

2

1

Sample

§

MDREG [D ]

n

20 µs / C

SR bit

or

Compare

MCRB Register

SDM bit

D

H

CPB bit* HDM bit*

n

MCRB Register

D

S

D

S

H

D = D & HDM bit + D & SDM bit

H

S

F(x)

HDM bit

SDM bit

D

To interrupt generator

§

Register updated on R event

* = Preload register, changes taken into account at next C event

46/131

ST72141K2-Auto

MOTOR CONTROLLER (Cont’d)

Table 13. Demagnetization (D) Event Generation (example for ZVD = 0)

CPB bit = 1

CPB bit = 0

HDM

bit

Meaning

(Even Σ)

(Odd Σ)

D = D = Output Compare [MDREG, MTIM registers]

S

Undershoot due to

Weak / null

motor parasite or first

sampling

undershoot and

BEMF positive

Σ

2

Σ

5

HVV

HV

HVV

D

C

S

C

Software Mode

D

S

0

(SDM bit = 1 and

HDM bit = 0)

D

(*)

S

C

HV/2

(*)

0V

Z

D = D

D = D + D

H

S

(Hardware detection only)

(Hardware detection or Output compare true)

Undershoot due to

motor parasite or first

Weak / null

undershoot and

sampling

BEMF positive

Σ

2

Σ

5

HV

C

Hardware/Simulat-

ed Mode

D

S

C

1

D

(*)

S

(SDM bit = 1 and

HDM bit = 1)

C

HV/2

(*)

0V

Z

D

H

Z

H

Z

(*) Note: This is a zoom to the additional voltage induced by the rotor (Back EMF)

47/131

ST72141K2-Auto

MOTOR CONTROLLER (Cont’d)

BEMF Zero Crossing (Z) Event

Consequently, BEMF reading (that is, comparison

with a voltage close to 0V) can only be done when

the PWM is applied on the high side drivers.

When both C and D events have occurred, the

PWM may be switched to another group of outputs

(depending on the OS[2:0] bits in the MCRB regis-

ter) and the real BEMF zero crossing sampling can

start (see Figure 31).

For this reason the MTC outputs can be split in two

groups called ODD and EVEN and the BEMF

reading will be done only when PWM is applied on

one of these two groups. The REO bit in the MPAR

register is used to select the group to be used for

BEMF sensing (high side group).

A BEMF voltage is present on the non-powered

terminal but referred to common star connection of

the motor whose voltage is equal to V /2.

DD

Refer to Table 15 for an overview of when a BEMF

can be read depending on REO bit, PWM mode

and function mode of peripheral.

When a winding is free-wheeling (during PWM off-

time) its terminal voltage changes to the other

power rail voltage, that means if the PWM is ap-

plied on the high side driver, free-wheeling will be

done through the high side diode and the terminal

will be 0V.

Depending on the edge and level selection (ZVD

and CPB) bits and when PWM is applied on the

correct group, a BEMF zero crossing detection

sets the ZI bit in the MISR register and generates

an interrupt if the ZIM bit is set.

This is used to force the common star connection

to 0V in order to read the BEMF referred to the

ground terminal.

The Z event also triggers some timer/multiplier op-

erations; for more details see Section 8.1.4.2.

Figure 30. Sampling and Zero Crossing Blocks

Sample

Output of hysteresis comparator

D

Q

Freq. (T = 1.25µs) for Demagnetization and Sensor

CP

1

2

Sampling frequency

I

16-bit Timer PWM

V

D_S,H

MCRA Register

Notes:

C

V0C1 bit

Updated/Shifted on

R

Reg

MCRB Register

MPAR Register

ZVD bit

Updated with Reg

on C

n+1

MPAR Register

REO bit

n

CPB bit*

n

I

Current Mode

D_S,H

V

Voltage Mode

20µs / D

C

events:

C

Z

or

Commutation

Z

BEFM

Zero-crossing

2

Sample

D

S,H

End Of

Demagnetization

E

Emergency Stop

Ratio Updated (+1 or -1)

SR bit

+/-

R

1

To D detection

O

1

Multiplier

Overflow

MCRA Register

Branch taken after C event

Branch taken after D event

2

* = Preload register, changes taken into account at next C event.

48/131

ST72141K2-Auto

MOTOR CONTROLLER (Cont’d)

Sensor Mode

The minimum off time for current control PWM is

also reduced to 1.25µs.

In sensor mode, the rotor position information is

given to the peripheral by means of logical data on

the three inputs MCIA, MCIB and MCIC.

Procedure for reading sensor inputs in Direct

Access mode: In Direct Access mode, the periph-

eral clock is disabled as shown in Table 25. As the

data present on the selected input is synchronized

by an 800 kHz clock, the sensor cannot be read di-

rectly (the value is latched). To read the sensor

data the following steps have to be performed:

For each step one of these three inputs is selected

(IS[1:0] bits in register MPHST) in order to detect

the Z event.

In this case Demagnetization has no meaning and

the relevant features such as the special PWM

configuration, D or D management, or 20µs filter

are not available (see Table 14).

1. Select the appropriate MCIx input pin by means

of the IS[1:0] bits in the MPHST register.

S

H

2. Switch from direct access mode to indirect

access mode in order to latch the sensor data

(DAC bit in MCRA register).

For this configuration the rotor detection does not

need a particular phase configuration to validate

the measurement and a Z event can be read from

any detection window. A fixed sampling frequency

(800 kHz) is used, that means the Z event and po-

sition sensoring is more precise than it is in sen-

sorless mode.

3. Switch back to direct access mode.

4. Read the comparator output (HST bit in the

MIMR register).

Table 14. Sensor mode selection

Event detection

Behavior of the output

SR bit

Mode

OS2 bit use

Filtering

PWM

sampling clock

Sensors not

used

D: Clock 1.25µs

Z: SA&OT config.

20µs after C for D event

20µs after D for Z event

“Before D” behavior

and “after D” behavior

0

1

Enabled

Sensors

used

Disabled

Z: Clock 1.25µs

20µs after C for Z event

Only “after D” behavior

49/131

ST72141K2-Auto

MOTOR CONTROLLER (Cont’d)

Figure 31. Functional Diagram of Z Detection after D Event

D or D

S

H

Begin

20µs Filter turned on

Switch Sampling Clock[D] -> Sampling Clock[Z]

No

Side change on

Output PWM

?

Yes

Change the side according to OS[2:0]

Wait for next sampling clock edge

No

Read enable

by REO

?

Yes

No

Filter

off

?

Yes

Read enabled

End

50/131

ST72141K2-Auto

MOTOR CONTROLLER (Cont’d)

Table 15. Modes permitting BEMF reading after Demagnetization (D event)

OS[2:0]

bits

REO bit

SR bit

V0C1 bit

Significant

PWM

Group

(Read

BEMF on

Even/Odd

group)

Demagnet-

ization

BEMF reading permitted after D event

when:

(Sensor/

Sensor-

less Mode)

(Voltage/

Current

Mode)

(PWM

Output

Config.)

Sensorless mode, Current Mode, PWM

output only on Even group and BEMF read

on Even group

x00

x01

x10

000

001

100

101

110

Even

Odd

0

1

0

1

0

1

0

1

0

1

Sensorless mode, Current Mode, PWM

output only on Odd group and BEMF read

on Odd group

1

Sensorless mode, Current Mode, PWM

output on alternate groups but BEMF read

only on Even group

Even

Odd

Sensorless mode, Current Mode, PWM

output on alternate groups but BEMF read

only on Odd group