ST7F10BY0M3TR [STMICROELECTRONICS]
8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, 5 TIMERS, SPI; 8位MCU单电压闪存存储器，数据EEPROM ， ADC ， 5个定时器， SPI
| 型号： | ST7F10BY0M3TR |
| 厂家： | 
ST |
| 描述： | 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, 5 TIMERS, SPI |
| 文件： | 总159页 (文件大小：2853K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ST7LITE1xB
8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY,
DATA EEPROM, ADC, 5 TIMERS, SPI
■ Memories
– up to 4 Kbytes single voltage extended Flash
(XFlash) Program memory with read-out pro-
tection, In-Circuit Programming and In-Appli-
cation programming (ICP and IAP). 10K write/
erase cycles guaranteed, data retention: 20
years at 55°C.
SO20
DIP20
DIP16
– 256 bytes RAM
QFN20
– 128 bytes data EEPROM with read-out pro-
tection. 300K write/erase cycles guaranteed,
data retention: 20 years at 55°C.
SO16
300”
outputs, 1 input capture, 4 output compare
■ Clock, Reset and Supply Management
and one pulse functions
– Enhanced reset system
■ Communication Interface
– SPI synchronous serial interface
■ Interrupt Management
– 12 interrupt vectors plus TRAP and RESET
– 15 external interrupt lines (on 4 vectors)
■ Analog Comparator
– Enhanced low voltage supervisor (LVD) for
main supply and an auxiliary voltage detector
(AVD) with interrupt capability for implement-
ing safe power-down procedures
– Clock sources: Internal 1% RC oscillator (on
ST7FLITE15B and ST7FLITE19B), crystal/
ceramic resonator or external clock
– Internal 32-MHz input clock for Auto-reload
timer
– Optional x4 or x8 PLL for 4 or 8 MHz internal
clock
■ A/D Converter
– 7 input channels
– Fixed gain Op-amp
– 13-bit precision for 0 to 430 mV (@ 5V V
)
DD
– 10-bit precision for 430 mV to 5V (@ 5V V
■ Instruction Set
)
– Five Power Saving Modes: Halt, Active-Halt,
Auto Wake-up from Halt, Wait and Slow
DD
■ I/O Ports
– 8-bit data manipulation
– Up to 17 multifunctional bidirectional I/O lines
– 7 high sink outputs
■ 5 Timers
– 63 basic instructions with illegal opcode de-
tection
– 17 main addressing modes
– 8 x 8 unsigned multiply instructions
■ Development Tools
– Configurable watchdog timer
– Two 8-bit Lite Timers with prescaler,
1 realtime base and 1 input capture
– Full hardware/software development package
– DM (Debug Module)
– Two 12-bit Auto-reload Timers with 4 PWM
Device Summary
Features
ST7LITE10B
ST7LITE15B
ST7LITE19B
Program memory - bytes
RAM (stack) - bytes
Data EEPROM - bytes
2K/4K
256 (128)
-
-
128
Lite Timer with Wdg, Autoreload
Timer, SPI, 10-bit ADC with Op-Amp
Lite Timer with Wdg, Autoreload Timer with 32-MHz input clock, SPI,
10-bit ADC with Op-Amp, Analog Comparator
Peripherals
Operating Supply
CPU Frequency
Operating Temperature
Packages
2.7V to 5.5V
Up to 8Mhz(w/ ext OSC at 16MHz)
SO20 300”, DIP20, SO16 300”, DIP16
Up to 8Mhz (w/ ext OSC at 16MHz or int 1MHz RC 1%, PLLx8/4MHz)
-40°C to +85°C / -40°C to +125°C
SO20 300”, DIP20, SO16 300”, DIP16, QFN20
Rev 6
1/159
1
June 2008
Table of Contents
1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.3 PROGRAMMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.4 ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.5 MEMORY PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.6 RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.7 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5 DATA EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.3 MEMORY ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.4 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.5 ACCESS ERROR HANDLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.6 DATA EEPROM READ-OUT PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.7 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.1 INTERNAL RC OSCILLATOR ADJUSTMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.2 PHASE LOCKED LOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.3 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.4 MULTI-OSCILLATOR (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.5 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.6 SYSTEM INTEGRITY MANAGEMENT (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
8 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
8.1 NON MASKABLE SOFTWARE INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
8.2 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
8.3 PERIPHERAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
9 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
9.2 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
9.3 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
9.4 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
9.5 ACTIVE-HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9.6 AUTO WAKE UP FROM HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
10 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
10.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
10.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
10.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
2/159
1
Table of Contents
10.4 UNUSED I/O PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
10.5 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
10.6 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
10.7 DEVICE-SPECIFIC I/O PORT CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
10.8 MULTIPLEXED INPUT/OUTPUT PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
11 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
11.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
11.2 DUAL 12-BIT AUTORELOAD TIMER 4 (AT4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
11.3 LITE TIMER 2 (LT2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
11.4 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
11.5 10-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
11.6 ANALOG COMPARATOR (CMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
12 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
12.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
12.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
13 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
13.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
13.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
13.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
13.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
13.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
13.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
13.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
13.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
13.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
13.10 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 137
13.11 10-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
13.12 ANALOG COMPARATOR CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
13.13 PROGRAMMABLE INTERNAL VOLTAGE REFERENCE CHARACTERISTICS . . . . . 143
13.14 CURRENT BIAS CHARACTERISTICS (FOR COMPARATOR AND INTERNAL VOLTAGE
REFERENCE) 143
14 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
14.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
14.2 SOLDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
15 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . 149
15.1 OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
15.2 DEVICE ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
15.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
15.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
16 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
3/159
ST7LITE1xB
1 INTRODUCTION
The ST7LITE1xB is a member of the ST7 micro-
controller family. All ST7 devices are based on a
common industry-standard 8-bit core, featuring an
enhanced instruction set.
software developers, enabling the design of highly
efficient and compact application code. In addition
to standard 8-bit data management, all ST7 micro-
controllers feature true bit manipulation, 8x8 un-
signed multiplication and indirect addressing
modes.
The ST7LITE1xB features FLASH memory with
byte-by-byte In-Circuit Programming (ICP) and In-
Application Programming (IAP) capability.
For easy reference, all parametric data are located
in section 13 on page 110. The ST7LITE1xB fea-
tures an on-chip Debug Module (DM) to support
In-Circuit Debugging (ICD). For a description of
the DM registers, refer to the ST7 ICC Protocol
Reference Manual.
Under software control, the ST7LITE1xB device
can be placed in WAIT, SLOW, or HALT mode, re-
ducing power consumption when the application is
in idle or standby state.
The enhanced instruction set and addressing
modes of the ST7 offer both power and flexibility to
Figure 1. General Block Diagram
Programmable
Internal Reference
Comparator
PLL
8MHz -> 32MHz
Int.
1% RC
1MHz
12-Bit
Auto-Reload
TIMER 2
PLL x 8
or PLL X4
CLKIN
8-Bit
LITE TIMER 2
/ 2
OSC1
OSC2
Ext.
OSC
Internal
CLOCK
1MHz
PA7:0
(8 bits)
PB6:0
(7 bits)
PC1:0
(2 bits)
to
PORT A
16MHz
PORT B
PORT C
LVD, AVD
V
POWER
SUPPLY
DD
V
SS
ADC
+ OpAmp
RESET
CONTROL
8-BIT CORE
ALU
SPI
PROGRAM
MEMORY
Debug Module
(up to 4K Bytes)
DATA EEPROM
(128 Bytes)
RAM
(256 Bytes)
WATCHDOG
4/159
1
ST7LITE1xB
2 PIN DESCRIPTION
Figure 2. 20-Pin SO and DIP Package Pinout
V
OSC1/CLKIN/PC0
1
20
19
18
17
16
15
14
13
12
11
SS
V
OSC2/PC1
2
DD
RESET
3
PA0 (HS)/LTIC
COMPIN+/SS/AIN0/PB0
PA1 (HS)/ATIC
4
ei0
ei1
ei3
ei2
PA2 (HS)/ATPWM0
PA3 (HS)/ATPWM1
PA4 (HS)/ATPWM2
5
SCK/AIN1/PB1
MISO/AIN2/PB2
MOSI/AIN3/PB3
COMPIN-/CLKIN/AIN4/PB4
AIN5/PB5
6
7
PA5 (HS)/ATPWM3/ICCDATA
PA6/MCO/ICCCLK/BREAK
PA7(HS)/COMPOUT
8
9
10
AIN6/PB6
(HS) 20mA High sink capability
eix associated external interrupt vector
Figure 3. 20-Pin QFN Package Pinout
20 19 18 17
16
15
PA0 (HS)/LTIC
1
RESET
PA1 (HS)/ATIC
COMPIN+/SS/AIN0/PB0
2
3
4
5
6
ei0
ei3
PA2 (HS)/ATPWM0
PA3 (HS)/ATPWM1
PA4 (HS)/ATPWM2
PA5 (HS)/ATPWM3/ICCDATA
14
13
12
11
SCK/AIN1/PB1
MISO/AIN2/PB2
MOSI/AIN3/PB3
ei2
ei1
10
COMPIN-/CLKIN/AIN4/PB4
7
8
9
(HS) 20mA High sink capability
eix associated external interrupt vector
5/159
1
ST7LITE1xB
PIN DESCRIPTION (Cont’d)
Figure 4. 16-Pin SO and DIP Package Pinout
V
OSC1/CLKIN/PC0
1
16
15
14
13
12
11
10
9
SS
V
OSC2/PC1
2
DD
RESET
3
PA0 (HS)/LTIC
PA2 (HS)/ATPWM0
PA4 (HS)/ATPWM2
PA5 (HS)/ATPWM3/ICCDATA
COMPIN+/SS/AIN0/PB0
SCK/AIN1/PB1
4
5
6
7
8
ei0
ei1
ei3
ei2
MISO/AIN2/PB2
PA6/MCO/ICCCLK/BREAK
PA7(HS)/COMPOUT
MOSI/AIN3/PB3
COMPIN-/CLKIN/AIN4/PB4
(HS) 20mA high sink capability
eix associated external interrupt vector
6/159
1
ST7LITE1xB
PIN DESCRIPTION (Cont’d)
Legend / Abbreviations for Table 1:
Type:
I = input, O = output, S = supply
In/Output level: C = CMOS 0.3V /0.7V with input trigger
T
DD
DD
Output level:
HS = 20mA high sink (on N-buffer only)
Port and control configuration:
– Input:
float = floating, wpu = weak pull-up, int = interrupt, ana = analog
OD = open drain, PP = push-pull
– Output:
The RESET configuration of each pin is shown in bold which is valid as long as the device is in reset state.
Table 1. Device Pin Description
Pin No.
Level
Port / Control
Main
Function
(after
Input
Output
Pin Name
Alternate Function
reset)
1)
1)
1
19
20
1
1
2
3
V
V
S
S
Ground
SS
DD
2
3
Main power supply
RESET
I/O C
X
X
X
Top priority non maskable interrupt (active low)
T
2)
ADC Analog Input 0 or SPI Slave
Select (active low) or Analog Com-
PB0/COMPIN+/
AIN0/SS
4
2
4
I/O
C
X
X
X
Port B0
parator Input
T
Caution: No negative current in-
jection allowed on this pin.
ei3
2)
ADC Analog Input 1 or SPI Serial
5
6
7
3
4
5
5
6
7
PB1/AIN1/SCK
PB2/AIN2/MISO
PB3/AIN3/MOSI
I/O
I/O
I/O
C
C
C
X
X
X
X
X
X
X
X
X
X
X
X
Port B1
Port B2
Port B3
T
T
T
Clock
2)
ADC Analog Input 2 or SPI Mas-
ter In/ Slave Out Data
2)
ADC Analog Input 3 or SPI Mas-
ter Out / Slave In Data
2)
ADC Analog Input 4 or External
PB4/AIN4/CLKIN/
COMPIN-
ei2
ei1
8
6
8
I/O
C
X
X
X
X
Port B4
clock input or Analog Comparator
External Reference Input
T
2)
9
7
8
9
-
-
PB5/AIN5
I/O
I/O
C
C
X
X
X
X
X
X
X
X
X
X
X
Port B5
Port B6
Port A7
ADC Analog Input 5
T
T
2)
10
11
PB6/AIN6
ADC Analog Input 6
9
PA7/COMPOUT
I/O C HS
Analog Comparator Output
T
7/159
1
ST7LITE1xB
Pin No.
Level
Port / Control
Input Output
Main
Function
(after
Pin Name
Alternate Function
reset)
Main Clock Output or In Circuit
Communication Clock or External
BREAK
Caution: During normal operation
this pin must be pulled- up, inter-
nally or externally (external pull-up
of 10k mandatory in noisy environ-
ment). This is to avoid entering ICC
mode unexpectedly during a reset.
In the application, even if the pin is
configured as output, any reset will
put it back in input pull-up
PA6 /MCO/
ICCCLK/BREAK
12 10 10
I/O
C
X
ei1
X
X
X
X
Port A6
Port A5
T
PA5 /ICCDATA/
ATPWM3
In Circuit Communication Data or
Auto-Reload Timer PWM3
13 11 11
I/O C HS
X
T
ei1
ei0
14 12 12 PA4/ATPWM2
15 13 PA3/ATPWM1
16 14 13 PA2/ATPWM0
17 15 PA1/ATIC
I/O C HS
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Port A4
Port A3
Port A2
Port A1
Port A0
Auto-Reload Timer PWM2
Auto-Reload Timer PWM1
Auto-Reload Timer PWM0
Auto-Reload Timer Input Capture
Lite Timer Input Capture
T
-
I/O C HS
T
I/O C HS
T
-
I/O C HS
T
18 16 14 PA0/LTIC
19 17 15 OSC2/PC1
I/O C HS
T
Resonator oscillator inverter out-
put
3)
I/O
X
X
X
X
Port C1
Resonator oscillator inverter input
or External clock input
3)
20 18 16 OSC1/CLKIN/PC0 I/O
Port C0
Notes:
1. It is mandatory to connect all available V and V
pins to the supply voltage and all V and V
SS SSA
DD
DDA
pins to ground.
2. When the pin is configured as analog input, positive and negative current injections are not allowed.
3. PCOR not implemented but p-transistor always active in output mode (refer to Figure 32 on page 50).
8/159
1
ST7LITE1xB
3 REGISTER & MEMORY MAP
As shown in Figure 5, the MCU is capable of ad-
dressing 64K bytes of memories and I/O registers.
dressing space so the reset and interrupt vectors
are located in Sector 0 (F000h-FFFFh).
The available memory locations consist of 128
bytes of register locations, 256 bytes of RAM, 128
bytes of data EEPROM and up to 4 Kbytes of flash
program memory. The RAM space includes up to
128 bytes for the stack from 180h to 1FFh.
The size of Flash Sector 0 and other device op-
tions are configurable by Option byte (refer to sec-
tion 15.1 on page 149).
IMPORTANT: Memory locations marked as “Re-
served” must never be accessed. Accessing a re-
served area can have unpredictable effects on the
device.
The highest address bytes contain the user reset
and interrupt vectors.
The Flash memory contains two sectors (see Fig-
ure 5) mapped in the upper part of the ST7 ad-
Figure 5. Memory Map
0000h
HW Registers
(see Table 2)
0080h
007Fh
0080h
Short Addressing
RAM (zero page)
RAM
(128 Bytes)
00FFh
0100h
00FFh
0100h
Reserved
Reserved
017Fh
0180h
017Fh
0180h
DEE0h
RCCRH0
128 Bytes Stack
DEE1h
RAM
01FFh
RCCRL0
DEE2h
(128 Bytes)
01FFh
0200h
RCCRH1
DEE3h
Reserved
RCCRL1
0FFFh
1000h
see section 7.1 on page 23
Data EEPROM
(128 Bytes)
2K FLASH
PROGRAM MEMORY
107Fh
1080h
F800h
1 Kbyte
(SECTOR 1)
Reserved
FBFFh
FC00h
EFFFh
F000h
1 Kbyte
(SECTOR 0)
FFFFh
Flash Memory
(2K or 4K)
4K FLASH
PROGRAM MEMORY
FFDFh
FFE0h
Interrupt & Reset Vectors
(see Table 5)
F000h
3 Kbytes
(SECTOR 1)
FFFFh
FBFFh
FC00h
1 Kbyte
(SECTOR 0)
FFFFh
9/159
1
ST7LITE1xB
Table 2. Hardware Register Map
Address
Block
Register Label
Register Name
Port A Data Register
Port A Data Direction Register
Port A Option Register
Reset Status
Remarks
R/W
R/W
R/W
1)
0000h
0001h
0002h
PADR
PADDR
PAOR
FFh
Port A
00h
40h
1)
0003h
0004h
0005h
PBDR
PBDDR
PBOR
Port B Data Register
Port B Data Direction Register
Port B Option Register
FFh
R/W
R/W
R/W
Port B
Port C
00h
00h
2)
0006h
0007h
PCDR
PCDDR
Port C Data Register
Port C Data Direction Register
0xh
00h
R/W
R/W
0008h
0009h
000Ah
000Bh
000Ch
LTCSR2
LTARR
LTCNTR
LTCSR1
LTICR
Lite Timer Control/Status Register 2
Lite Timer Auto-reload Register
Lite Timer Counter Register
Lite Timer Control/Status Register 1
Lite Timer Input Capture Register
00h
00h
00h
R/W
R/W
Read Only
R/W
LITE
TIMER 2
0X00 0000b
00h
Read Only
000Dh
000Eh
000Fh
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
0019h
001Ah
001Bh
001Ch
001Dh
001Eh
001Fh
0020h
0021h
0022h
0023h
0024h
0025h
0026h
ATCSR
CNTRH
CNTRL
ATRH
ATRL
PWMCR
PWM0CSR
PWM1CSR
PWM2CSR
PWM3CSR
DCR0H
DCR0L
DCR1H
DCR1L
DCR2H
DCR2L
Timer Control/Status Register
Counter Register High
Counter Register Low
Auto-Reload Register High
Auto-Reload Register Low
0X00 0000b
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
03h
00h
00h
00h
00h
03h
R/W
Read Only
Read Only
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Read Only
Read Only
R/W
R/W
R/W
R/W
R/W
R/W
PWM Output Control Register
PWM 0 Control/Status Register
PWM 1 Control/Status Register
PWM 2 Control/Status Register
PWM 3 Control/Status Register
PWM 0 Duty Cycle Register High
PWM 0 Duty Cycle Register Low
PWM 1 Duty Cycle Register High
PWM 1 Duty Cycle Register Low
PWM 2 Duty Cycle Register High
PWM 2 Duty Cycle Register Low
PWM 3 Duty Cycle Register High
PWM 3 Duty Cycle Register Low
Input Capture Register High
Input Capture Register Low
Timer Control/Status Register 2
Break Control Register
AUTO-
RELOAD
TIMER 2
DCR3H
DCR3L
ATICRH
ATICRL
ATCSR2
BREAKCR
ATR2H
ATR2L
DTGR
BREAKEN
Auto-Reload Register 2 High
Auto-Reload Register 2 Low
Dead Time Generation Register
Break Enable Register
0027h to
002Bh
Reserved area (5 bytes)
Comparator
Voltage
Reference
Internal Voltage Reference Control Reg-
ister
002Ch
VREFCR
00h
R/W
Comparator and Internal Reference Con-
trol Register
002Dh
002Eh
Comparator CMPCR
WDG WDGCR
00h
7Fh
R/W
R/W
Watchdog Control Register
10/159
1
ST7LITE1xB
Address
Block
Register Label
Register Name
Reset Status
Remarks
0002Fh
00030h
FLASH
FCSR
Flash Control/Status Register
00h
00h
R/W
R/W
EEPROM EECSR
SPIDR
Data EEPROM Control/Status Register
0031h
0032h
0033h
SPI Data I/O Register
SPI Control Register
SPI Control Status Register
xxh
0xh
00h
R/W
R/W
R/W
SPI
SPICR
SPICSR
0034h
0035h
0036h
ADCCSR
ADCDRH
ADCDRL
A/D Control Status Register
A/D Data Register High
A/D Amplifier Control/Data Low Register
00h
xxh
0xh
R/W
Read Only
R/W
ADC
0037h
0038h
ITC
EICR
External Interrupt Control Register
Main Clock Control/Status Register
00h
00h
R/W
R/W
MCC
MCCSR
0039h
003Ah
Clock and RCCR
RC oscillator Control Register
System Integrity Control/Status Register
FFh
0110 0xx0b
R/W
R/W
Reset
SICSR
PLLTST
EISR
PLL clock
select
003Bh
003Ch
PLL test register
00h
0Ch
R/W
R/W
ITC
External Interrupt Selection Register
Reserved area (12 bytes)
003Dh to
0048h
0049h
004Ah
AWUPR
AWUCSR
AWU Prescaler Register
AWU Control/Status Register
FFh
00h
R/W
R/W
AWU
004Bh
004Ch
004Dh
004Eh
004Fh
0050h
0051h
DMCR
DMSR
DM Control Register
DM Status Register
00h
00h
00h
00h
00h
00h
00h
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DMBK1H
DMBK1L
DMBK2H
DMBK2L
DMCR2
DM Breakpoint Register 1 High
DM Breakpoint Register 1 Low
DM Breakpoint Register 2 High
DM Breakpoint Register 2 Low
DM Control Register 2
3)
DM
0052h to
007Fh
Reserved area (46 bytes)
Legend: x=undefined, R/W=read/write
Notes:
1. The contents of the I/O port DR registers are readable only in output configuration. In input configura-
tion, the values of the I/O pins are returned instead of the DR register contents.
2. The bits associated with unavailable pins must always keep their reset value.
3. For a description of the Debug Module registers, see ICC protocol reference manual.
11/159
1
ST7LITE1xB
4 FLASH PROGRAM MEMORY
4.1 Introduction
4.3.1 In-Circuit Programming (ICP)
ICP uses a protocol called ICC (In-Circuit Commu-
nication) which allows an ST7 plugged on a print-
ed circuit board (PCB) to communicate with an ex-
ternal programming device connected via cable.
ICP is performed in three steps:
The ST7 single voltage extended Flash (XFlash) is
a non-volatile memory that can be electrically
erased and programmed either on a byte-by-byte
basis or up to 32 bytes in parallel.
The XFlash devices can be programmed off-board
(plugged in a programming tool) or on-board using
In-Circuit Programming or In-Application Program-
ming.
Switch the ST7 to ICC mode (In-Circuit Communi-
cations). This is done by driving a specific signal
sequence on the ICCCLK/DATA pins while the
RESET pin is pulled low. When the ST7 enters
ICC mode, it fetches a specific RESET vector
which points to the ST7 System Memory contain-
ing the ICC protocol routine. This routine enables
the ST7 to receive bytes from the ICC interface.
The array matrix organisation allows each sector
to be erased and reprogrammed without affecting
other sectors.
4.2 Main Features
– Download ICP Driver code in RAM from the
ICCDATA pin
■ ICP (In-Circuit Programming)
– Execute ICP Driver code in RAM to program
the FLASH memory
■ IAP (In-Application Programming)
■ ICT (In-Circuit Testing) for downloading and
Depending on the ICP Driver code downloaded in
RAM, FLASH memory programming can be fully
customized (number of bytes to program, program
locations, or selection of the serial communication
interface for downloading).
executing user application test patterns in RAM
■ Sector 0 size configurable by option byte
■ Read-out and write protection
4.3 PROGRAMMING MODES
4.3.2 In Application Programming (IAP)
This mode uses an IAP Driver program previously
programmed in Sector 0 by the user (in ICP
mode).
The ST7 can be programmed in three different
ways:
– Insertion in a programming tool. In this mode,
FLASH sectors 0 and 1, option byte row and
data EEPROM (if present) can be pro-
grammed or erased.
– In-Circuit Programming. In this mode, FLASH
sectors 0 and 1, option byte row and data
EEPROM (if present) can be programmed or
erased without removing the device from the
application board.
– In-Application Programming. In this mode,
sector 1 and data EEPROM (if present) can
be programmed or erased without removing
the device from the application board and
while the application is running.
This mode is fully controlled by user software. This
allows it to be adapted to the user application, (us-
er-defined strategy for entering programming
mode, choice of communications protocol used to
fetch the data to be stored etc.)
IAP mode can be used to program any memory ar-
eas except Sector 0, which is write/erase protect-
ed to allow recovery in case errors occur during
the programming operation.
12/159
1
ST7LITE1xB
FLASH PROGRAM MEMORY (Cont’d)
4.4 ICC interface
classical RC network with R>1K or a reset man-
agement IC with open drain output and pull-up re-
sistor>1K, no additional components are needed.
In all cases the user must ensure that no external
reset is generated by the application during the
ICC session.
ICP needs a minimum of 4 and up to 6 pins to be
connected to the programming tool. These pins
are:
– RESET: device reset
– V : device power supply ground
– ICCCLK: ICC output serial clock pin
– ICCDATA: ICC input serial data pin
– OSC1: main clock input for external source
(not required on devices without OSC1/OSC2
pins)
3. The use of pin 7 of the ICC connector depends
on the Programming Tool architecture. This pin
must be connected when using most ST Program-
ming Tools (it is used to monitor the application
power supply). Please refer to the Programming
Tool manual.
4. Pin 9 has to be connected to the OSC1 pin of
the ST7 when the clock is not available in the ap-
plication or if the selected clock option is not pro-
grammed in the option byte. ST7 devices with mul-
ti-oscillator capability need to have OSC2 ground-
ed in this case.
5. In 38-pulse ICC mode, the internal RC oscillator
is forced as a clock source, regardless of the se-
lection in the option byte. For ST7LITE10B devic-
es which do not support the internal RC oscillator,
the “option byte disabled” mode must be used (35-
pulse ICC mode entry, clock provided by the tool).
Caution: During normal operation the ICCCLK pin
must be pulled- up, internally or externally (exter-
nal pull-up of 10k mandatory in noisy environ-
ment). This is to avoid entering ICC mode unex-
pectedly during a reset. In the application, even if
the pin is configured as output, any reset will put it
back in input pull-up.
SS
– V : application board power supply (option-
DD
al, see Note 3)
Notes:
1. If the ICCCLK or ICCDATA pins are only used
as outputs in the application, no signal isolation is
necessary. As soon as the Programming Tool is
plugged to the board, even if an ICC session is not
in progress, the ICCCLK and ICCDATA pins are
not available for the application. If they are used as
inputs by the application, isolation such as a serial
resistor has to be implemented in case another de-
vice forces the signal. Refer to the Programming
Tool documentation for recommended resistor val-
ues.
2. During the ICP session, the programming tool
must control the RESET pin. This can lead to con-
flicts between the programming tool and the appli-
cation reset circuit if it drives more than 5mA at
high level (push pull output or pull-up resistor<1K).
A schottky diode can be used to isolate the appli-
cation RESET circuit in this case. When using a
Figure 6. Typical ICC Interface
PROGRAMMING TOOL
ICC CONNECTOR
ICC Cable
ICC CONNECTOR
HE10 CONNECTOR TYPE
(See Note 3)
OPTIONAL
(See Note 4)
APPLICATION BOARD
9
7
5
6
3
1
2
10
8
4
APPLICATION
RESET SOURCE
See Note 2
APPLICATION
POWER SUPPLY
C
C
L2
See Note 1 and Caution
See Note 1
L1
APPLICATION
I/O
ST7
13/159
1
ST7LITE1xB
FLASH PROGRAM MEMORY (Cont’d)
4.5 Memory Protection
Warning: Once set, Write/erase protection can
never be removed. A write-protected flash device
is no longer reprogrammable.
There are two different types of memory protec-
tion: Read Out Protection and Write/Erase Protec-
tion which can be applied individually.
Write/erase protection is enabled through the
FMP_W bit in the option byte.
4.5.1 Read out Protection
Readout protection, when selected provides a pro-
tection against program memory content extrac-
tion and against write access to Flash memory.
Even if no protection can be considered as totally
unbreakable, the feature provides a very high level
of protection for a general purpose microcontroller.
4.6 Related Documentation
For details on Flash programming and ICC proto-
col, refer to the ST7 Flash Programming Refer-
ence Manual and to the ST7 ICC Protocol Refer-
ence Manual.
2
Both program and data E memory are protected.
In flash devices, this protection is removed by re-
programming the option. In this case, both pro-
4.7 Register Description
2
FLASH CONTROL/STATUS REGISTER (FCSR)
Read/Write
Reset Value: 000 0000 (00h)
1st RASS Key: 0101 0110 (56h)
2nd RASS Key: 1010 1110 (AEh)
gram and data E memory are automatically
erased and the device can be reprogrammed.
Read-out protection selection depends on the de-
vice type:
– In Flash devices it is enabled and removed
through the FMP_R bit in the option byte.
7
0
0
– In ROM devices it is enabled by mask option
specified in the Option List.
0
0
0
0
OPT
LAT
PGM
4.5.2 Flash Write/Erase Protection
Write/erase protection, when set, makes it impos-
sible to both overwrite and erase program memo-
Note: This register is reserved for programming
using ICP, IAP or other programming methods. It
controls the XFlash programming and erasing op-
erations.
2
ry. It does not apply to E data. Its purpose is to
provide advanced security to applications and pre-
vent any change being made to the memory con-
tent.
When an EPB or another programming tool is
used (in socket or ICP mode), the RASS keys are
sent automatically.
14/159
1
ST7LITE1xB
5 DATA EEPROM
5.1 INTRODUCTION
5.2 MAIN FEATURES
The Electrically Erasable Programmable Read
Only Memory can be used as a non volatile back-
up for storing data. Using the EEPROM requires a
basic access protocol described in this chapter.
■ Up to 32 Bytes programmed in the same cycle
■ EEPROM mono-voltage (charge pump)
■ Chained erase and programming cycles
■ Internal control of the global programming cycle
duration
■ WAIT mode management
■ Readout protection
Figure 7. EEPROM Block Diagram
HIGH VOLTAGE
PUMP
EECSR
0
0
0
0
0
0
E2LAT E2PGM
EEPROM
ROW
ADDRESS
DECODER
4
MEMORY MATRIX
(1 ROW = 32 x 8 BITS)
DECODER
128
128
DATA
MULTIPLEXER
32 x 8 BITS
4
4
DATA LATCHES
ADDRESS BUS
DATA BUS
15/159
1
ST7LITE1xB
DATA EEPROM (Cont’d)
5.3 MEMORY ACCESS
the value is latched inside the 32 data latches ac-
cording to its address.
The Data EEPROM memory read/write access
modes are controlled by the E2LAT bit of the EEP-
ROM Control/Status register (EECSR). The flow-
chart in Figure 8 describes these different memory
access modes.
When PGM bit is set by the software, all the previ-
ous bytes written in the data latches (up to 32) are
programmed in the EEPROM cells. The effective
high address (row) is determined by the last EEP-
ROM write sequence. To avoid wrong program-
ming, the user must take care that all the bytes
written between two programming sequences
have the same high address: only the five Least
Significant Bits of the address can change.
Read Operation (E2LAT=0)
The EEPROM can be read as a normal ROM loca-
tion when the E2LAT bit of the EECSR register is
cleared.
At the end of the programming cycle, the PGM and
LAT bits are cleared simultaneously.
On this device, Data EEPROM can also be used to
execute machine code. Take care not to write to
the Data EEPROM while executing from it. This
would result in an unexpected code being execut-
ed.
Note: Care should be taken during the program-
ming cycle. Writing to the same memory location
will over-program the memory (logical AND be-
tween the two write access data result) because
the data latches are only cleared at the end of the
programming cycle and by the falling edge of the
E2LAT bit.
Write Operation (E2LAT=1)
To access the write mode, the E2LAT bit has to be
set by software (the E2PGM bit remains cleared).
When a write access to the EEPROM area occurs,
It is not possible to read the latched data.
This note is illustrated by the Figure 10.
Figure 8. Data EEPROM Programming Flowchart
READ MODE
E2LAT=0
WRITE MODE
E2LAT=1
E2PGM=0
E2PGM=0
WRITE UP TO 32 BYTES
IN EEPROM AREA
(with the same 11 MSB of the address)
READ BYTES
IN EEPROM AREA
START PROGRAMMING CYCLE
E2LAT=1
E2PGM=1 (set by software)
0
1
E2LAT
CLEARED BY HARDWARE
16/159
1
ST7LITE1xB
DATA EEPROM (Cont’d)
2
Figure 9. Data E PROM Write Operation
⇓ Row / Byte ⇒
0
1
2
3
...
30 31
Physical Address
00h...1Fh
0
1
ROW
DEFINITION
20h...3Fh
...
N
Nx20h...Nx20h+1Fh
Read operation impossible
Read operation possible
Programming cycle
Byte 1 Byte 2
PHASE 1
Byte 32
PHASE 2
Writing data latches
Waiting E2PGM and E2LAT to fall
E2LAT bit
Set by USER application
Cleared by hardware
E2PGM bit
Note: If a programming cycle is interrupted (by a reset action), the integrity of the data in memory is not
guaranteed.
17/159
1
ST7LITE1xB
DATA EEPROM (Cont’d)
5.4 POWER SAVING MODES
Wait mode
5.5 ACCESS ERROR HANDLING
If a read access occurs while E2LAT=1, then the
data bus will not be driven.
The DATA EEPROM can enter WAIT mode on ex-
ecution of the WFI instruction of the microcontrol-
ler or when the microcontroller enters Active-HALT
mode.The DATA EEPROM will immediately enter
this mode if there is no programming in progress,
otherwise the DATA EEPROM will finish the cycle
and then enter WAIT mode.
If a write access occurs while E2LAT=0, then the
data on the bus will not be latched.
If a programming cycle is interrupted (by a RESET
action), the integrity of the data in memory will not
be guaranteed.
5.6 Data EEPROM Read-out Protection
Active-Halt mode
The read-out protection is enabled through an op-
tion bit (see option byte section).
Refer to Wait mode.
When this option is selected, the programs and
data stored in the EEPROM memory are protected
against read-out (including a re-write protection).
In Flash devices, when this protection is removed
by reprogramming the Option Byte, the entire Pro-
gram memory and EEPROM is first automatically
erased.
Halt mode
The DATA EEPROM immediately enters HALT
mode if the microcontroller executes the HALT in-
struction. Therefore the EEPROM will stop the
function in progress, and data may be corrupted.
Note: Both Program Memory and data EEPROM
are protected using the same option bit.
Figure 10. Data EEPROM Programming Cycle
READ OPERATION NOT POSSIBLE
READ OPERATION POSSIBLE
INTERNAL
PROGRAMMING
VOLTAGE
ERASE CYCLE
WRITE CYCLE
WRITE OF
DATA LATCHES
tPROG
LAT
PGM
18/159
1
ST7LITE1xB
DATA EEPROM (Cont’d)
5.7 REGISTER DESCRIPTION
EEPROM CONTROL/STATUS REGISTER (EEC-
SR)
Read/Write
Reset Value: 0000 0000 (00h)
7
0
0
0
0
0
0
0
E2LAT E2PGM
Bits 7:2 = Reserved, forced by hardware to 0.
Bit 1 = E2LAT Latch Access Transfer
This bit is set by software. It is cleared by hard-
ware at the end of the programming cycle. It can
only be cleared by software if the E2PGM bit is
cleared.
0: Read mode
1: Write mode
Bit 0 = E2PGM Programming control and status
This bit is set by software to begin the programming
cycle. At the end of the programming cycle, this bit
is cleared by hardware.
0: Programming finished or not yet started
1: Programming cycle is in progress
Note: if the E2PGM bit is cleared during the pro-
gramming cycle, the memory data is not guaran-
teed
Table 3. DATA EEPROM Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
EECSR
E2LAT
0
E2PGM
0
0030h
0
0
0
0
0
0
Reset Value
19/159
1
ST7LITE1xB
6 CENTRAL PROCESSING UNIT
6.1 INTRODUCTION
Accumulator (A)
The Accumulator is an 8-bit general purpose reg-
ister used to hold operands and the results of the
arithmetic and logic calculations and to manipulate
data.
This CPU has a full 8-bit architecture and contains
six internal registers allowing efficient 8-bit data
manipulation.
Index Registers (X and Y)
6.2 MAIN FEATURES
In indexed addressing modes, these 8-bit registers
are used to create either effective addresses or
temporary storage areas for data manipulation.
(The Cross-Assembler generates a precede in-
struction (PRE) to indicate that the following in-
struction refers to the Y register.)
■ 63 basic instructions
■ Fast 8-bit by 8-bit multiply
■ 17 main addressing modes
■ Two 8-bit index registers
■ 16-bit stack pointer
■ Low power modes
■ Maskable hardware interrupts
■ Non-maskable software interrupt
The Y register is not affected by the interrupt auto-
matic procedures (not pushed to and popped from
the stack).
Program Counter (PC)
The program counter is a 16-bit register containing
the address of the next instruction to be executed
by the CPU. It is made of two 8-bit registers PCL
(Program Counter Low which is the LSB) and PCH
(Program Counter High which is the MSB).
6.3 CPU REGISTERS
The six CPU registers shown in Figure 1 are not
present in the memory mapping and are accessed
by specific instructions.
Figure 11. CPU Registers
7
0
ACCUMULATOR
RESET VALUE = XXh
7
0
0
X INDEX REGISTER
Y INDEX REGISTER
RESET VALUE = XXh
7
RESET VALUE = XXh
PCL
PCH
7
8
15
0
PROGRAM COUNTER
RESET VALUE = RESET VECTOR @ FFFEh-FFFFh
7
1
0
H I N Z C
X 1 X X X
1
1
1
1
CONDITION CODE REGISTER
RESET VALUE =
8
1
15
7
0
STACK POINTER
RESET VALUE = STACK HIGHER ADDRESS
X = Undefined Value
20/159
1
ST7LITE1xB
CPU REGISTERS (cont’d)
CONDITION CODE REGISTER (CC)
Read/Write
because the I bit is set by hardware at the start of
the routine and reset by the IRET instruction at the
end of the routine. If the I bit is cleared by software
in the interrupt routine, pending interrupts are
serviced regardless of the priority level of the cur-
rent interrupt routine.
Reset Value: 111x1xxx
7
0
1
1
1
H
I
N
Z
C
Bit 2 = N Negative
The 8-bit Condition Code register contains the in-
terrupt mask and four flags representative of the
result of the instruction just executed. This register
can also be handled by the PUSH and POP in-
structions.
This bit is set and cleared by hardware. It is repre-
sentative of the result sign of the last arithmetic,
logical or data manipulation. It is a copy of the 7
bit of the result.
0: The result of the last operation is positive or null.
1: The result of the last operation is negative
(that is, the most significant bit is a logic 1).
th
These bits can be individually tested and/or con-
trolled by specific instructions.
This bit is accessed by the JRMI and JRPL instruc-
tions.
Bit 4 = H Half carry
This bit is set by hardware when a carry occurs be-
tween bits 3 and 4 of the ALU during an ADD or
ADC instruction. It is reset by hardware during the
same instructions.
Bit 1 = Z Zero
This bit is set and cleared by hardware. This bit in-
dicates that the result of the last arithmetic, logical
or data manipulation is zero.
0: The result of the last operation is different from
zero.
1: The result of the last operation is zero.
0: No half carry has occurred.
1: A half carry has occurred.
This bit is tested using the JRH or JRNH instruc-
tion. The H bit is useful in BCD arithmetic subrou-
tines.
This bit is accessed by the JREQ and JRNE test
instructions.
Bit 3 = I Interrupt mask
This bit is set by hardware when entering in inter-
rupt or by software to disable all interrupts except
the TRAP software interrupt. This bit is cleared by
software.
Bit 0 = C Carry/borrow
This bit is set and cleared by hardware and soft-
ware. It indicates an overflow or an underflow has
occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.
0: Interrupts are enabled.
1: Interrupts are disabled.
This bit is controlled by the RIM, SIM and IRET in-
structions and is tested by the JRM and JRNM in-
structions.
This bit is driven by the SCF and RCF instructions
and tested by the JRC and JRNC instructions. It is
also affected by the “bit test and branch”, shift and
rotate instructions.
Note: Interrupts requested while I is set are
latched and can be processed when I is cleared.
By default an interrupt routine is not interruptible
21/159
1
ST7LITE1xB
CPU REGISTERS (Cont’d)
STACK POINTER (SP)
Read/Write
Note: When the lower limit is exceeded, the Stack
Pointer wraps around to the stack upper limit, with-
out indicating the stack overflow. The previously
stored information is then overwritten and there-
fore lost. The stack also wraps in case of an under-
flow.
Reset Value: 01FFh
15
8
1
0
The stack is used to save the return address dur-
ing a subroutine call and the CPU context during
an interrupt. The user may also directly manipulate
the stack by means of the PUSH and POP instruc-
tions. In the case of an interrupt, the PCL is stored
at the first location pointed to by the SP. Then the
other registers are stored in the next locations as
shown in Figure 12.
0
7
1
0
0
0
0
0
0
SP6 SP5 SP4 SP3 SP2 SP1 SP0
The Stack Pointer is a 16-bit register which is al-
ways pointing to the next free location in the stack.
It is then decremented after data has been pushed
onto the stack and incremented before data is
popped from the stack (see Figure 12).
– When an interrupt is received, the SP is decre-
mented and the context is pushed on the stack.
– On return from interrupt, the SP is incremented
and the context is popped from the stack.
A subroutine call occupies two locations and an in-
terrupt five locations in the stack area.
Since the stack is 128 bytes deep, the 9 most sig-
nificant bits are forced by hardware. Following an
MCU Reset, or after a Reset Stack Pointer instruc-
tion (RSP), the Stack Pointer contains its reset val-
ue (the SP6 to SP0 bits are set) which is the stack
higher address.
The least significant byte of the Stack Pointer
(called S) can be directly accessed by a LD in-
struction.
Figure 12. Stack Manipulation Example
CALL
Subroutine
RET
or RSP
PUSH Y
POP Y
IRET
Interrupt
Event
@ 0180h
SP
SP
SP
Y
CC
A
CC
A
CC
A
X
X
X
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
SP
SP
PCH
PCL
PCH
PCL
SP
@ 01FFh
Stack Higher Address = 01FFh
0180h
Stack Lower Address =
22/159
1
ST7LITE1xB
7 SUPPLY, RESET AND CLOCK MANAGEMENT
The device includes a range of utility features for
ST7LITE1xB
Address
DEE0h (CR[9:2])
RCCR
Conditions
securing the application in critical situations (for
example in case of a power brown-out), and re-
ducing the number of external components.
1)
RCCRH0 V =5V
DD
T =25°C
A
1)
RCCRL0
DEE1h (CR[1:0])
f
=1MHz
Main features
RC
1)
RCCRH1 V =3.3V
DEE2h (CR[9:2])
DD
■ Clock Management
T =25°C
A
1)
RCCRL1
DEE3h (CR[1:0])
– 1 MHz internal RC oscillator (enabled by op-
tion byte, available on ST7LITE15B and
ST7LITE19B devices only)
f
=1MHz
RC
1. DEE0h, DEE1h, DEE2h and DEE3h addresses
are located in a reserved area of non-volatile
memory. They are read-only bytes for the applica-
tion code. This area cannot be erased or pro-
grammed by any ICC operation.
For compatibility reasons with the SICSR register,
CR[1:0] bits are stored in the 5th and 6th position
of DEE1 and DEE3 addresses.
– 1 to 16 MHz External crystal/ceramic resona-
tor (selected by option byte)
– External Clock Input (enabled by option byte)
– PLL for multiplying the frequency by 8 or 4
(enabled by option byte)
– For clock ART counter only: PLL32 for multi-
plying the 8 MHz frequency by 4 (enabled by
option byte). The 8 MHz input frequency is
mandatory and can be obtained in the follow-
ing ways:
Notes:
– In 38-pulse ICC mode, the internal RC oscillator
is forced as a clock source, regardless of the se-
lection in the option byte. For ST7LITE10B devic-
es which do not support the internal RC
oscillator, the “option byte disabled” mode must
be used (35-pulse ICC mode entry, clock provid-
ed by the tool).
–1 MHz RC + PLLx8
–16 MHz external clock (internally divided
by 2)
–2 MHz. external clock (internally divided by
2) + PLLx8
–Crystal oscillator with 16 MHz output fre-
quency (internally divided by 2)
– See “ELECTRICAL CHARACTERISTICS” on
page 110. for more information on the frequency
and accuracy of the RC oscillator.
■ Reset Sequence Manager (RSM)
■ System Integrity Management (SI)
– To improve clock stability and frequency accura-
cy, it is recommended to place a decoupling ca-
– Main supply Low voltage detection (LVD) with
reset generation (enabled by option byte)
pacitor, typically 100nF, between the V and
DD
V
pins as close as possible to the ST7 device.
SS
– Auxiliary Voltage detector (AVD) with interrupt
capability for monitoring the main supply (en-
abled by option byte)
– These bytes are systematically programmed by
ST, including on FASTROM devices.
Caution: If the voltage or temperature conditions
change in the application, the frequency may need
to be recalibrated.
7.1 INTERNAL RC OSCILLATOR ADJUSTMENT
Refer to application note AN1324 for information
on how to calibrate the RC frequency using an ex-
ternal reference signal.
The device contains an internal RC oscillator with
an accuracy of 1% for a given device, temperature
and voltage range (4.5V-5.5V). It must be calibrat-
ed to obtain the frequency required in the applica-
tion. This is done by software writing a 10-bit cali-
bration value in the RCCR (RC Control Register)
and in the bits 6:5 in the SICSR (SI Control Status
Register).
7.2 PHASE LOCKED LOOP
The PLL can be used to multiply a 1MHz frequen-
cy from the RC oscillator or the external clock by 4
or 8 to obtain f
of 4 or 8 MHz. The PLL is ena-
OSC
Whenever the microcontroller is reset, the RCCR
returns to its default value (FFh), i.e. each time the
device is reset, the calibration value must be load-
ed in the RCCR. Predefined calibration values are
bled and the multiplication factor of 4 or 8 is select-
ed by 2 option bits.
– The x4 PLL is intended for operation with V in
DD
the 2.7V to 3.3V range
stored in EEPROM for 3 and 5V V supply volt-
DD
ages at 25°C, as shown in the following table.
23/159
1
ST7LITE1xB
– The x8 PLL is intended for operation with V in
When the PLL output signal reaches the operating
frequency, the LOCKED bit in the SICSCR register
DD
1)
the 3.3V to 5.5V range
is set. Full PLL accuracy (ACC ) is reached after
PLL
Refer to Section 15.1 for the option byte descrip-
tion.
a stabilization time of t
(see Figure 13 and
STAB
13.3.5 Internal RC Oscillator and PLL)
If the PLL is disabled and the RC oscillator is ena-
Refer to section 7.6.4 on page 35 for a description
of the LOCKED bit in the SICSR register.
bled, then f
1MHz.
OSC =
If both the RC oscillator and the PLL are disabled,
is driven by the external clock.
f
OSC
Note 1:
Figure 13. PLL Output Frequency Timing
Diagram
It is possible to obtain f
= 4MHz in the 3.3V to
OSC
5.5V range with internal RC and PLL enabled by
selecting 1MHz RC and x8 PLL and setting the
PLLdiv2 bit in the PLLTST register (see section
7.6.4 on page 35).
LOCKED bit set
4/8 x
input
freq.
t
STAB
t
LOCK
t
STARTUP
t
When the PLL is started, after reset or wake up
from Halt mode or AWUFH mode, it outputs the
clock after a delay of t
.
STARTUP
24/159
1
ST7LITE1xB
7.3 REGISTER DESCRIPTION
MAIN CLOCK CONTROL/STATUS REGISTER
(MCCSR)
RC CONTROL REGISTER (RCCR)
Read / Write
Read / Write
Reset Value: 1111 1111 (FFh)
Reset Value: 0000 0000 (00h)
7
0
7
0
0
CR2
CR9 CR8 CR7 CR6 CR5 CR4 CR3
MCO SMS
0
0
0
0
0
Bits 7:0 = CR[9:2] RC Oscillator Frequency Ad-
justment Bits
Bits 7:2 = Reserved, must be kept cleared.
These bits must be written immediately after reset
to adjust the RC oscillator frequency and to obtain
an accuracy of 1%. The application can store the
correct value for each voltage range in EEPROM
and write it to this register at start-up.
Bit 1 = MCO Main Clock Out enable
This bit is read/write by software and cleared by
hardware after a reset. This bit allows to enable
the MCO output clock.
0: MCO clock disabled, I/O port free for general
purpose I/O.
1: MCO clock enabled.
00h = maximum available frequency
FFh = lowest available frequency
These bits are used with the CR[1:0] bits in the
SICSR register. Refer to section 7.6.4 on page 35.
Note: To tune the oscillator, write a series of differ-
ent values in the register until the correct frequen-
cy is reached. The fastest method is to use a di-
chotomy starting with 80h.
Bit 0 = SMS Slow Mode select
This bit is read/write by software and cleared by
hardware after a reset. This bit selects the input
clock f
or f
/32.
OSC
OSC
0: Normal mode (f
f
CPU = OSC
1: Slow mode (f
f
/32)
CPU = OSC
25/159
1
ST7LITE1xB
Figure 14. Clock Management Block Diagram
7
0
PLLDIV2
7
0
PLLTST
CR9 CR8 CR7 CR6 CR5 CR4 CR3
CR2
RCCR
7
0
lock32 CR1 CR0
SICSR
PLL
12-BIT
AT TIMER 2
f
Tunable
1% RC Oscillator
CPU
8MHz -> 32MHz
OSC,PLLOFF,
CLKSEL[1:0]
Option bits
RC OSC
ck_pllx4x8
CLKIN
PLL 1MHz -> 8MHz
PLL 1MHz -> 4MHz
CLKIN
CLKIN
f
/2
OSC
/2
CLKIN/2
plldiv2
DIVIDER
CLKIN/2
OSC/2
CLKIN
/OSC1
OSC
1-16 MHZ
OSC
/2
DIVIDER
OSC2
OSC,PLLOFF,
CLKSEL[1:0]
Option bits
f
LTIMER
8-BIT
LITE TIMER 2 COUNTER
(1ms timebase @ 8 MHz f
)
OSC
f
f
/32
OSC
OSC
/32 DIVIDER
1
0
f
CPU
TO CPU AND
PERIPHERALS
f
OSC
MCCSR
SMS
MCO
MCO
f
CPU
Note: The PLL cannot be used with the external resonator oscillator
26/159
1
ST7LITE1xB
7.4 MULTI-OSCILLATOR (MO)
The main clock of the ST7 can be generated by
four different source types coming from the multi-
oscillator block (1 to 16MHz):
The calibration is done through the RCCR[7:0] and
SICSR[6:5] registers.
Table 4. ST7 Clock Sources
Hardware Configuration
■ an external source
■ 5 different configurations for crystal or ceramic
resonator oscillators
■ an internal high frequency RC oscillator
ST7
Each oscillator is optimized for a given frequency
range in terms of consumption and is selectable
through the option byte. The associated hardware
configurations are shown in Table 4. Refer to the
electrical characteristics section for more details.
OSC1
OSC2
EXTERNAL
SOURCE
External Clock Source
In this external clock mode, a clock signal (square,
sinus or triangle) with ~50% duty cycle has to drive
the OSC1 pin while the OSC2 pin is tied to ground.
ST7
OSC1
OSC2
Note: when the Multi-Oscillator is not used, PB4 is
selected by default as external clock.
Crystal/Ceramic Oscillators
In this mode, with a self-controlled gain feature,
oscillator of any frequency from 1 to 16MHz can be
placed on OSC1 and OSC2 pins. This family of os-
cillators has the advantage of producing a very ac-
curate rate on the main clock of the ST7. In this
mode of the multi-oscillator, the resonator and the
load capacitors have to be placed as close as pos-
sible to the oscillator pins in order to minimize out-
put distortion and start-up stabilization time. The
loading capacitance values must be adjusted ac-
cording to the selected oscillator.
C
C
L2
L1
LOAD
CAPACITORS
ST7
OSC1
OSC2
These oscillators are not stopped during the
RESET phase to avoid losing time in the oscillator
start-up phase.
Internal RC Oscillator
In this mode, the tunable 1%RC oscillator is used
as main clock source. The two oscillator pins have
to be tied to ground if dedicately using for oscillator
else can be found as general purpose IO.
27/159
1
ST7LITE1xB
7.5 RESET SEQUENCE MANAGER (RSM)
7.5.1 Introduction
CPU clock
cycle delay
Clock Source
Internal RC Oscillator
The reset sequence manager includes three RE-
SET sources as shown in Figure 16:
■ External RESET source pulse
256
256
External clock (connected to CLKIN pin)
External Crystal/Ceramic Oscillator
(connected to OSC1/OSC2 pins)
■ Internal LVD RESET (Low Voltage Detection)
■ Internal WATCHDOG RESET
4096
Note: A reset can also be triggered following the
detection of an illegal opcode or prebyte code. Re-
fer to section 12.2.1 on page 107 for further de-
tails.
If the PLL is enabled by option byte, it outputs the
clock after an additional delay of t
Figure 13).
(see
STARTUP
Figure 15. RESET Sequence Phases
These sources act on the RESET pin and it is al-
ways kept low during the delay phase.
The RESET service routine vector is fixed at ad-
dresses FFFEh-FFFFh in the ST7 memory map.
RESET
INTERNAL RESET
Active Phase
FETCH
VECTOR
The basic RESET sequence consists of 3 phases
as shown in Figure 15:
256 or 4096 CLOCK CYCLES
■ Active Phase depending on the RESET source
■ 256 or 4096 CPU clock cycle delay (see table
7.5.2 Asynchronous External RESET pin
The RESET pin is both an input and an open-drain
output with integrated R weak pull-up resistor.
below)
■ RESET vector fetch
ON
This pull-up has no fixed value but varies in ac-
cordance with the input voltage. It can be pulled
low by external circuitry to reset the device. See
Electrical Characteristic section for more details.
Caution: When the ST7 is unprogrammed or fully
erased, the Flash is blank and the RESET vector
is not programmed. For this reason, it is recom-
mended to keep the RESET pin in low state until
programming mode is entered, in order to avoid
unwanted behavior.
A RESET signal originating from an external
source must have a duration of at least t
in
h(RSTL)in
order to be recognized (see Figure 17). This de-
tection is asynchronous and therefore the MCU
can enter reset state even in HALT mode.
The 256 or 4096 CPU clock cycle delay allows the
oscillator to stabilise and ensures that recovery
has taken place from the Reset state. The shorter
or longer clock cycle delay is automatically select-
ed depending on the clock source chosen by op-
tion byte:
The RESET vector fetch phase duration is 2 clock
cycles.
28/159
1
ST7LITE1xB
Figure 16. Reset Block Diagram
V
DD
R
ON
INTERNAL
RESET
Filter
RESET
WATCHDOG RESET
PULSE
GENERATOR
ILLEGAL OPCODE RESET 1)
LVD RESET
Note 1: See “Illegal Opcode Reset” on page 107. for more details on illegal opcode reset conditions.
29/159
1
ST7LITE1xB
RESET SEQUENCE MANAGER (Cont’d)
The RESET pin is an asynchronous signal which
plays a major role in EMS performance. In a noisy
environment, it is recommended to follow the
guidelines mentioned in the electrical characteris-
tics section.
7.5.4 Internal Low Voltage Detector (LVD)
RESET
Two different RESET sequences caused by the in-
ternal LVD circuitry can be distinguished:
■ Power-On RESET
7.5.3 External Power-On RESET
■ Voltage Drop RESET
If the LVD is disabled by option byte, to start up the
microcontroller correctly, the user must ensure by
means of an external reset circuit that the reset
The device RESET pin acts as an output that is
pulled low when V <V
(rising edge) or
DD
IT+
V
<V (falling edge) as shown in Figure 17.
DD
IT-
signal is held low until V
is over the minimum
DD
The LVD filters spikes on V larger than t
to
level specified for the selected f
frequency.
DD
g(VDD)
OSC
avoid parasitic resets.
A proper reset signal for a slow rising V supply
DD
can generally be provided by an external RC net-
work connected to the RESET pin.
7.5.5 Internal Watchdog RESET
The RESET sequence generated by a internal
Watchdog counter overflow is shown in Figure 17.
Starting from the Watchdog counter underflow, the
device RESET pin acts as an output that is pulled
low during at least t
.
w(RSTL)out
Figure 17. RESET Sequences
V
DD
V
V
IT+(LVD)
IT-(LVD)
LVD
RESET
EXTERNAL
RESET
WATCHDOG
RESET
RUN
RUN
RUN
RUN
ACTIVE
PHASE
ACTIVE
PHASE
ACTIVE PHASE
t
w(RSTL)out
t
h(RSTL)in
EXTERNAL
RESET
SOURCE
RESET PIN
WATCHDOG
RESET
WATCHDOG UNDERFLOW
INTERNAL RESET (256 or 4096 TCPU
VECTOR FETCH
)
30/159
1
ST7LITE1xB
7.6 SYSTEM INTEGRITY MANAGEMENT (SI)
The System Integrity Management block contains
the Low voltage Detector (LVD) and Auxiliary Volt-
age Detector (AVD) functions. It is managed by
the SICSR register.
Provided the minimum V value (guaranteed for
DD
the oscillator frequency) is above V
MCU can only be in two modes:
, the
IT-(LVD)
– under full software control
– in static safe reset
Note: A reset can also be triggered following the
detection of an illegal opcode or prebyte code. Re-
fer to section 12.2.1 on page 107 for further de-
tails.
In these conditions, secure operation is always en-
sured for the application without the need for ex-
ternal reset hardware.
During a Low Voltage Detector Reset, the RESET
pin is held low, thus permitting the MCU to reset
other devices.
7.6.1 Low Voltage Detector (LVD)
The Low Voltage Detector function (LVD) gener-
ates a static reset when the V supply voltage is
DD
below a V
reference value. This means that
IT-(LVD)
Notes:
it secures the power-up as well as the power-down
keeping the ST7 in reset.
The LVD allows the device to be used without any
external RESET circuitry.
The V
reference value for a voltage drop is
IT-(LVD)
lower than the V
reference value for power-
The LVD is an optional function which can be se-
lected by option byte.
IT+(LVD)
on in order to avoid a parasitic reset when the
MCU starts running and sinks current on the sup-
ply (hysteresis).
Use of LVD with capacitive power supply: with this
type of power supply, if power cuts occur in the ap-
The LVD Reset circuitry generates a reset when
plication, it is recommended to pull V
down to
DD
V
is below:
0V to ensure optimum restart conditions. Refer to
circuit example in Figure 106 on page 136 and
note 4.
DD
– V
when V is rising
DD
IT+(LVD)
– V
when V is falling
DD
IT-(LVD)
It is recommended to make sure that the V sup-
DD
The LVD function is illustrated in Figure 18.
ply voltage rises monotonously when the device is
exiting from Reset, to ensure the application func-
tions properly.
The voltage threshold can be configured by option
byte to be low, medium or high.
Figure 18. Low Voltage Detector vs Reset
V
DD
V
hys
V
V
IT+
(LVD)
IT-
(LVD)
RESET
31/159
1
ST7LITE1xB
SYSTEM INTEGRITY MANAGEMENT (Cont’d)
Figure 19. Reset and Supply Management Block Diagram
WATCHDOG
TIMER (WDG)
STATUS FLAG
SYSTEM INTEGRITY MANAGEMENT
RESET SEQUENCE
MANAGER
AVD Interrupt Request
RESET
SICSR
(RSM)
0
0
0
WDGRFLOCKED LVDRFAVDFAVDIE
LOW VOLTAGE
DETECTOR
(LVD)
V
V
SS
DD
AUXILIARY VOLTAGE
DETECTOR
(AVD)
32/159
1
ST7LITE1xB
SYSTEM INTEGRITY MANAGEMENT (Cont’d)
7.6.2 Auxiliary Voltage Detector (AVD)
abled through the option byte.
7.6.2.1 Monitoring the V Main Supply
The Voltage Detector function (AVD) is based on
DD
an analog comparison between a V
and
IT-(AVD)
The AVD voltage threshold value is relative to the
selected LVD threshold configured by option byte
(see section 15.1 on page 149).
V
reference value and the V
main sup-
IT+(AVD)
DD
ply voltage (V
). The V
reference value
AVD
IT-(AVD)
for falling voltage is lower than the V
refer-
IT+(AVD)
If the AVD interrupt is enabled, an interrupt is gen-
ence value for rising voltage in order to avoid par-
asitic detection (hysteresis).
erated when the voltage crosses the V
IT-(AVD)
or
IT+(LVD)
V
threshold (AVDF bit is set).
The output of the AVD comparator is directly read-
able by the application software through a real
time status bit (AVDF) in the SICSR register. This
bit is read only.
In the case of a drop in voltage, the AVD interrupt
acts as an early warning, allowing software to shut
down safely before the LVD resets the microcon-
troller. See Figure 20.
Caution: The AVD functions only if the LVD is en-
Figure 20. Using the AVD to Monitor V
DD
V
DD
Early Warning Interrupt
(Power has dropped, MCU not
not yet in reset)
V
hyst
V
IT+(AVD)
V
IT-(AVD)
V
V
IT+(LVD)
IT-(LVD)
AVDF bit
0
1
RESET
1
0
AVD INTERRUPT
REQUEST
IF AVDIE bit = 1
INTERRUPT Cleared by
reset
INTERRUPT Cleared by
hardware
LVD RESET
33/159
1
ST7LITE1xB
SYSTEM INTEGRITY MANAGEMENT (Cont’d)
7.6.3 Low Power Modes
set and the interrupt mask in the CC register is re-
set (RIM instruction).
Mode
WAIT
HALT
Description
Enable Exit
Control from
Exit
from
Halt
No effect on SI. AVD interrupts cause the
device to exit from Wait mode.
Event
Flag
Interrupt Event
Bit
Wait
The SICSR register is frozen.
The AVD remains active.
AVD event
AVDF AVDIE
Yes
No
7.6.3.1 Interrupts
The AVD interrupt event generates an interrupt if
the corresponding Enable Control Bit (AVDIE) is
34/159
1
ST7LITE1xB
SYSTEM INTEGRITY MANAGEMENT (Cont’d)
7.6.4 Register Description
SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR)
Read/Write
the LVD is disabled by OPTION BYTE, the LVDRF
bit value is undefined.
Reset Value: 0110 0xx0 (6xh)
7
0
Bit 1 = AVDF Voltage Detector Flag
This read-only bit is set and cleared by hardware.
If the AVDIE bit is set, an interrupt request is gen-
erated when the AVDF bit is set. Refer to Figure
20 and to Section 7.6.2.1 for additional details.
LOCK
32
WDG
RF
CR1 CR0
LOCKED LVDRF AVDF AVDIE
Bit 7 = LOCK32 PLL 32Mhz Locked Flag
0: V over AVD threshold
DD
1: V under AVD threshold
DD
This bit is set and cleared by hardware. It is set au-
tomatically when the PLL 32Mhz reaches its oper-
ating frequency
Bit 0 = AVDIE Voltage Detector Interrupt Enable
This bit is set and cleared by software. It enables
an interrupt to be generated when the AVDF flag is
set. The pending interrupt information is automati-
cally cleared when software enters the AVD inter-
rupt routine.
0: PLL32 not locked
1: PLL32 locked
Bits 6:5 = CR[1:0] RC Oscillator Frequency Ad-
justment bits
0: AVD interrupt disabled
1: AVD interrupt enabled
These bits, as well as CR[9:2] bits in the RCCR
register must be written immediately after reset to
adjust the RC oscillator frequency and to obtain an
accuracy of 1%. Refer to section 7.3 on page 25.
Application notes
The LVDRF flag is not cleared when another RE-
SET type occurs (external or watchdog), the
LVDRF flag remains set to keep trace of the origi-
nal failure.
In this case, a watchdog reset can be detected by
software while an external reset can not.
Bit 4 = WDGRF Watchdog Reset flag
This bit indicates that the last Reset was generat-
ed by the Watchdog peripheral. It is set by hard-
ware (watchdog reset) and cleared by software
(reading the SICSR register or writing 0 to this bit)
or by an LVD Reset (to ensure a stable cleared
state of the WDGRF flag when the CPU starts).
Combined with the LVDRF flag information, the
flag description is given by the following table.
PLL TEST REGISTER (PLLTST)
Read/Write
Reset Value: 0000 0000 (00h)
7
0
0
RESET Sources
LVDRF WDGRF
External RESET pin
Watchdog
0
0
1
0
1
PLLdiv2
0
0
0
0
0
0
LVD
X
Bit 7 : PLLdiv2 PLL clock divide by 2
This bit is read or write by software and cleared by
hardware after reset. This bit will divide the PLL
output clock by 2.
Bit 3 = LOCKED PLL Locked Flag
This bit is set and cleared by hardware. It is set au-
tomatically when the PLL reaches its operating fre-
quency.
0: PLL not locked
1: PLL locked
0 : PLL output clock
1 : Divide by 2 of PLL output clock
Refer “Clock Management Block Diagram” on
page 26
Note : Write of this bit will be effective after 2 Tcpu
cycles (if system clock is 8mhz) else 1 cycle (if
system clock is 4mhz) i.e. effective time is 250ns.
Bit 2 = LVDRF LVD reset flag
This bit indicates that the last Reset was generat-
ed by the LVD block. It is set by hardware (LVD re-
set) and cleared by software (by reading). When
Bit 6:0 : Reserved , Must always be cleared
35/159
1
ST7LITE1xB
8 INTERRUPTS
The ST7 core may be interrupted by one of two dif-
ferent methods: Maskable hardware interrupts as
listed in the “interrupt mapping” table and a non-
maskable software interrupt (TRAP). The Interrupt
processing flowchart is shown in Figure 1.
8.1 NON MASKABLE SOFTWARE INTERRUPT
This interrupt is entered when the TRAP instruc-
tion is executed regardless of the state of the I bit.
It is serviced according to the flowchart in Figure 1.
The maskable interrupts must be enabled by
clearing the I bit in order to be serviced. However,
disabled interrupts may be latched and processed
when they are enabled (see external interrupts
subsection).
8.2 EXTERNAL INTERRUPTS
External interrupt vectors can be loaded into the
PC register if the corresponding external interrupt
occurred and if the I bit is cleared. These interrupts
allow the processor to leave the HALT low power
mode.
Note: After reset, all interrupts are disabled.
When an interrupt has to be serviced:
The external interrupt polarity is selected through
the miscellaneous register or interrupt register (if
available).
– Normal processing is suspended at the end of
the current instruction execution.
– The PC, X, A and CC registers are saved onto
the stack.
An external interrupt triggered on edge will be
latched and the interrupt request automatically
cleared upon entering the interrupt service routine.
– The I bit of the CC register is set to prevent addi-
tional interrupts.
Caution: The type of sensitivity defined in the Mis-
cellaneous or Interrupt register (if available) ap-
plies to the ei source. In case of a NANDed source
(as described in the I/O ports section), a low level
on an I/O pin, configured as input with interrupt,
masks the interrupt request even in case of rising-
edge sensitivity.
– The PC is then loaded with the interrupt vector of
the interrupt to service and the first instruction of
the interrupt service routine is fetched (refer to
the Interrupt Mapping table for vector address-
es).
The interrupt service routine should finish with the
IRET instruction which causes the contents of the
saved registers to be recovered from the stack.
8.3 PERIPHERAL INTERRUPTS
Note: As a consequence of the IRET instruction,
Different peripheral interrupt flags in the status
register are able to cause an interrupt when they
are active if both:
the I bit is cleared and the main program resumes.
Priority Management
By default, a servicing interrupt cannot be inter-
rupted because the I bit is set by hardware enter-
ing in interrupt routine.
– The I bit of the CC register is cleared.
– The corresponding enable bit is set in the control
register.
In the case when several interrupts are simultane-
ously pending, an hardware priority defines which
one will be serviced first (see the Interrupt Map-
ping table).
If any of these two conditions is false, the interrupt
is latched and thus remains pending.
Clearing an interrupt request is done by:
– Writing “0” to the corresponding bit in the status
register or
Interrupts and Low Power Mode
All interrupts allow the processor to leave the
WAIT low power mode. Only external and specifi-
cally mentioned interrupts allow the processor to
leave the HALT low power mode (refer to the “Exit
from HALT” column in the Interrupt Mapping ta-
ble).
– Access to the status register while the flag is set
followed by a read or write of an associated reg-
ister.
Note: The clearing sequence resets the internal
latch. A pending interrupt (that is, waiting for being
enabled) will therefore be lost if the clear se-
quence is executed.
36/159
1
ST7LITE1xB
INTERRUPTS (cont’d)
Figure 21. Interrupt Processing Flowchart
FROM RESET
N
I BIT SET?
Y
N
INTERRUPT
PENDING?
Y
FETCH NEXT INSTRUCTION
N
IRET?
STACK PC, X, A, CC
SET I BIT
Y
LOAD PC FROM INTERRUPT VECTOR
EXECUTE INSTRUCTION
RESTORE PC, X, A, CC FROM STACK
THIS CLEARS I BIT BY DEFAULT
Table 5. Interrupt Mapping
Exit
from
Order HALT or
AWUFH
Source
Block
Register Priority
Address
Vector
N°
Description
Label
RESET
TRAP
AWU
ei0
Reset
yes
FFFEh-FFFFh
FFFCh-FFFDh
FFFAh-FFFBh
FFF8h-FFF9h
FFF6h-FFF7h
FFF4h-FFF5h
FFF2h-FFF3h
FFF0h-FFF1h
FFEEh-FFEFh
FFECh-FFEDh
N/A
Highest
Priority
Software Interrupt
Auto Wake Up Interrupt
External Interrupt 0
External Interrupt 1
External Interrupt 2
External Interrupt 3
no
1)
0
1
2
3
4
5
6
7
AWUCSR
yes
ei1
N/A
yes
ei2
ei3
LITE TIMER LITE TIMER RTC2 interrupt
Comparator Comparator Interrupt
LTCSR2
CMPCR
SICSR
no
no
no
SI
AVD interrupt
AT TIMER Output Compare Interrupt
or Input Capture Interrupt
PWMxCSR
or ATCSR
8
no
FFEAh-FFEBh
AT TIMER
2)
9
AT TIMER Overflow Interrupt
LITE TIMER Input Capture Interrupt
LITE TIMER RTC1 Interrupt
SPI Peripheral Interrupts
ATCSR
LTCSR
LTCSR
SPICSR
ATCSR2
yes
FFE8h-FFE9h
FFE6h-FFE7h
FFE4h-FFE5h
FFE2h-FFE3h
FFE0h-FFE1h
10
11
12
13
no
LITE TIMER
SPI
2)
yes
Lowest
yes
Priority
no
AT TIMER AT TIMER Overflow Interrupt
Note 1: This interrupt exits the MCU from “Auto Wake-up from Halt” mode only.
Note 2 : These interrupts exit the MCU from “ACTIVE-HALT” mode only.
37/159
1
ST7LITE1xB
INTERRUPTS (Cont’d)
EXTERNAL INTERRUPT CONTROL REGISTER
(EICR)
EXTERNAL INTERRUPT SELECTION REGIS-
TER (EISR)
Read/Write
Read/Write
Reset Value: 0000 0000 (00h)
Reset Value: 0000 1100 (0Ch)
7
0
7
0
IS31 IS30 IS21 IS20 IS11 IS10 IS01 IS00
ei31 ei30 ei21 ei20 ei11 ei10 ei01 ei00
Bits 7:6 = IS3[1:0] ei3 sensitivity
These bits define the interrupt sensitivity for ei3
(Port B0) according to Table 6.
Bits 7:6 = ei3[1:0] ei3 pin selection
These bits are written by software. They select the
Port B I/O pin used for the ei3 external interrupt ac-
cording to the table below.
External Interrupt I/O pin selection
Bits 5:4 = IS2[1:0] ei2 sensitivity
These bits define the interrupt sensitivity for ei2
(Port B3) according to Table 6.
ei31
ei30
I/O Pin
1)
0
0
1
0
1
0
PB0
PB1
PB2
Bits 3:2 = IS1[1:0] ei1 sensitivity
These bits define the interrupt sensitivity for ei1
(Port A7) according to Table 6.
Note:
1. Reset State
Bits 1:0 = IS0[1:0] ei0 sensitivity
These bits define the interrupt sensitivity for ei0
(Port A0) according to Table 6.
Bits 5:4 = ei2[1:0] ei2 pin selection
These bits are written by software. They select the
Port B I/O pin used for the ei2 external interrupt ac-
cording to the table below.
Notes:
1. These 8 bits can be written only when the I bit in
the CC register is set.
External Interrupt I/O pin selection
2. Changing the sensitivity of a particular external
interrupt clears this pending interrupt. This can be
used to clear unwanted pending interrupts. Refer
to section “External Interrupt Function” on
page 48.
ei21
ei20
I/O Pin
1)
0
0
1
1
0
1
0
1
PB3
2)
PB4
PB5
PB6
Table 6. Interrupt Sensitivity Bits
ISx1 ISx0
External Interrupt Sensitivity
Notes:
0
0
1
1
0
1
0
1
Falling edge & low level
Rising edge only
1. Reset State
2. PB4 cannot be used as an external interrupt in
HALT mode.
Falling edge only
Rising and falling edge
38/159
1
ST7LITE1xB
INTERRUPTS (Cont’d)
Bit 3:2 = ei1[1:0] ei1 pin selection
Bit 1:0 = ei0[1:0] ei0 pin selection
These bits are written by software. They select the
Port A I/O pin used for the ei1 external interrupt ac-
cording to the table below.
These bits are written by software. They select the
Port A I/O pin used for the ei0 external interrupt ac-
cording to the table below.
External Interrupt I/O pin selection
External Interrupt I/O pin selection
ei11
ei10
I/O Pin
ei01
ei00
I/O Pin
0
0
1
1
0
1
0
1
PA4
PA5
PA6
PA7*
0
0
1
1
0
1
0
1
PA0 *
PA1
PA2
PA3
* Reset State
* Reset State
39/159
1
ST7LITE1xB
9 POWER SAVING MODES
9.1 INTRODUCTION
9.2 SLOW MODE
To give a large measure of flexibility to the applica-
tion in terms of power consumption, five main pow-
er saving modes are implemented in the ST7 (see
Figure 22):
■ Slow
■ Wait (and Slow-Wait)
■ Active Halt
This mode has two targets:
– To reduce power consumption by decreasing the
internal clock in the device,
– To adapt the internal clock frequency (f
the available supply voltage.
) to
CPU
SLOW mode is controlled by the SMS bit in the
MCCSR register which enables or disables Slow
mode.
■ Auto Wake up From Halt (AWUFH)
■ Halt
In this mode, the oscillator frequency is divided by
32. The CPU and peripherals are clocked at this
After a RESET the normal operating mode is se-
lected by default (RUN mode). This mode drives
the device (CPU and embedded peripherals) by
means of a master clock which is based on the
main oscillator frequency divided or multiplied by 2
lower frequency.
Note: SLOW-WAIT mode is activated when enter-
ing WAIT mode while the device is already in
SLOW mode.
(f
).
OSC2
Figure 23. SLOW Mode Clock Transition
From RUN mode, the different power saving
modes may be selected by setting the relevant
register bits or by calling the specific ST7 software
instruction whose action depends on the oscillator
status.
f
/32
f
OSC
OSC
f
CPU
Figure 22. Power Saving Mode Transitions
f
OSC
High
RUN
SMS
NORMAL RUN MODE
REQUEST
SLOW
WAIT
SLOW WAIT
ACTIVE HALT
AUTO WAKE UP FROM HALT
HALT
Low
POWER CONSUMPTION
40/159
1
ST7LITE1xB
POWER SAVING MODES (Cont’d)
9.3 WAIT MODE
Figure 24. WAIT Mode Flow-chart
WAIT mode places the MCU in a low power con-
sumption mode by stopping the CPU.
This power saving mode is selected by calling the
‘WFI’ instruction.
OSCILLATOR
PERIPHERALS
CPU
ON
ON
OFF
0
WFI INSTRUCTION
I BIT
All peripherals remain active. During WAIT mode,
the I bit of the CC register is cleared, to enable all
interrupts. All other registers and memory remain
unchanged. The MCU remains in WAIT mode until
an interrupt or RESET occurs, whereupon the Pro-
gram Counter branches to the starting address of
the interrupt or Reset service routine.
N
RESET
Y
N
INTERRUPT
The MCU will remain in WAIT mode until a Reset
or an Interrupt occurs, causing it to wake up.
Y
OSCILLATOR
PERIPHERALS
CPU
ON
OFF
ON
0
Refer to Figure 24.
I BIT
256 OR 4096 CPU CLOCK
CYCLE DELAY
OSCILLATOR
PERIPHERALS
CPU
ON
ON
ON
X 1)
I BIT
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Note:
1. Before servicing an interrupt, the CC register is
pushed on the stack. The I bit of the CC register is
set during the interrupt routine and cleared when
the CC register is popped.
41/159
1
ST7LITE1xB
POWER SAVING MODES (Cont’d)
9.4 HALT MODE
Figure 26. HALT Mode Flow-chart
The HALT mode is the lowest power consumption
mode of the MCU. It is entered by executing the
‘HALT’ instruction when ACTIVE-HALT is disabled
(see section 9.5 on page 43 for more details) and
when the AWUEN bit in the AWUCSR register is
cleared.
HALT INSTRUCTION
(Active Halt disabled)
(AWUCSR.AWUEN=0)
WATCHDOG
ENABLE
0
DISABLE
WDGHALT 1)
1
The MCU can exit HALT mode on reception of ei-
ther a specific interrupt (see Table 5, “Interrupt
Mapping,” on page 37) or a RESET. When exiting
HALT mode by means of a RESET or an interrupt,
the oscillator is immediately turned on and the 256
or 4096 CPU cycle delay is used to stabilize the
oscillator. After the start up delay, the CPU
resumes operation by servicing the interrupt or by
fetching the reset vector which woke it up (see Fig-
ure 26).
OSCILLATOR
OFF
WATCHDOG
RESET
PERIPHERALS 2)
OFF
OFF
0
CPU
I BIT
N
RESET
When entering HALT mode, the I bit in the CC reg-
ister is forced to 0 to enable interrupts. Therefore,
if an interrupt is pending, the MCU wakes up im-
mediately.
Y
N
INTERRUPT 3)
Y
OSCILLATOR
PERIPHERALS
CPU
ON
OFF
ON
In HALT mode, the main oscillator is turned off
causing all internal processing to be stopped, in-
cluding the operation of the on-chip peripherals.
All peripherals are not clocked except the ones
which get their clock supply from another clock
generator (such as an external or auxiliary oscilla-
tor).
I BIT
X 4)
256 OR 4096 CPU CLOCK
5)
CYCLE DELAY
The compatibility of Watchdog operation with
HALT mode is configured by the “WDGHALT” op-
tion bit of the option byte. The HALT instruction
when executed while the Watchdog system is en-
abled, can generate a Watchdog RESET (see sec-
tion 15.1 on page 149 for more details).
OSCILLATOR
PERIPHERALS
CPU
ON
ON
ON
X 4)
I BIT
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Figure 25. HALT Timing Overview
Notes:
256 OR 4096 CPU
CYCLE DELAY
RUN
HALT
RUN
1. WDGHALT is an option bit. See option byte sec-
tion for more details.
2. Peripheral clocked with an external clock source
RESET
OR
INTERRUPT
can still be active.
HALT
INSTRUCTION
[Active Halt disabled]
3. Only some specific interrupts can exit the MCU
from HALT mode (such as external interrupt). Re-
fer to Table 5 Interrupt Mapping for more details.
FETCH
VECTOR
4. Before servicing an interrupt, the CC register is
pushed on the stack. The I bit of the CC register is
set during the interrupt routine and cleared when
the CC register is popped.
5. If the PLL is enabled by option byte, it outputs
the clock after a delay of t
(see Figure 13).
STARTUP
42/159
1
ST7LITE1xB
POWER SAVING MODES (Cont’d)
9.4.1 Halt Mode Recommendations
9.5 ACTIVE-HALT MODE
– Make sure that an external event is available to
wake up the microcontroller from Halt mode.
ACTIVE-HALT mode is the lowest power con-
sumption mode of the MCU with a real time clock
available. It is entered by executing the ‘HALT’ in-
struction. The decision to enter either in ACTIVE-
HALT or HALT mode is given by the LTCSR/ATC-
SR register status as shown in the following table:
– When using an external interrupt to wake up the
microcontroller, re-initialize the corresponding I/
O as “Input Pull-up with Interrupt” before execut-
ing the HALT instruction. The main reason for
this is that the I/O may be wrongly configured
due to external interference or by an unforeseen
logical condition.
ATCSR
OVFIE
bit
LTCSR1
TB1IE bit
ATCSR ATCSR
CK1 bit CK0 bit
Meaning
– For the same reason, re-initialize the level sensi-
tiveness of each external interrupt as a precau-
tionary measure.
0
0
1
x
x
0
x
1
x
x
x
0
0
x
x
1
ACTIVE-HALT
mode disabled
– The opcode for the HALT instruction is 0x8E. To
avoid an unexpected HALT instruction due to a
program counter failure, it is advised to clear all
occurrences of the data value 0x8E from memo-
ry. For example, avoid defining a constant in pro-
gram memory with the value 0x8E.
ACTIVE-HALT
mode enabled
The MCU can exit ACTIVE-HALT mode on recep-
tion of a specific interrupt (see Table 5, “Interrupt
Mapping,” on page 37) or a RESET.
– As the HALT instruction clears the interrupt mask
in the CC register to allow interrupts, the user
may choose to clear all pending interrupt bits be-
fore executing the HALT instruction. This avoids
entering other peripheral interrupt routines after
executing the external interrupt routine corre-
sponding to the wake-up event (reset or external
interrupt).
– When exiting ACTIVE-HALT mode by means of
a RESET, a 256 or 4096 CPU cycle delay oc-
curs. After the start up delay, the CPU resumes
operation by fetching the reset vector which
woke it up (see Figure 28).
– When exiting ACTIVE-HALT mode by means of
an interrupt, the CPU immediately resumes oper-
ation by servicing the interrupt vector which woke
it up (see Figure 28).
When entering ACTIVE-HALT mode, the I bit in
the CC register is cleared to enable interrupts.
Therefore, if an interrupt is pending, the MCU
wakes up immediately (see Note 3).
In ACTIVE-HALT mode, only the main oscillator
and the selected timer counter (LT/AT) are running
to keep a wake-up time base. All other peripherals
are not clocked except those which get their clock
supply from another clock generator (such as ex-
ternal or auxiliary oscillator).
Note: As soon as ACTIVE-HALT is enabled, exe-
cuting a HALT instruction while the Watchdog is
active does not generate a RESET.
This means that the device cannot spend more
than a defined delay in this power saving mode.
43/159
1
ST7LITE1xB
POWER SAVING MODES (Cont’d)
Figure 27. ACTIVE-HALT Timing Overview
9.6 AUTO WAKE UP FROM HALT MODE
Auto Wake Up From Halt (AWUFH) mode is simi-
lar to Halt mode with the addition of a specific in-
ternal RC oscillator for wake-up (Auto Wake Up
from Halt Oscillator). Compared to ACTIVE-HALT
mode, AWUFH has lower power consumption (the
main clock is not kept running, but there is no ac-
curate realtime clock available.
ACTIVE
HALT
256 OR 4096 CPU
CYCLE DELAY
RUN
RUN
1)
RESET
OR
HALT
INSTRUCTION
[Active Halt Enabled]
INTERRUPT
FETCH
VECTOR
It is entered by executing the HALT instruction
when the AWUEN bit in the AWUCSR register has
been set.
Figure 28. ACTIVE-HALT Mode Flow-chart
OSCILLATOR
PERIPHERALS 2)
CPU
ON
OFF
OFF
0
Figure 29. AWUFH Mode Block Diagram
HALT INSTRUCTION
(Active Halt enabled)
(AWUCSR.AWUEN=0)
AWU RC
oscillator
I BIT
to Timer input capture
f
AWU_RC
N
RESET
Y
AWUFH
interrupt
N
INTERRUPT 3)
AWUFH
prescaler/1 .. 255
/64
divider
(ei0 source)
OSCILLATOR
PERIPHERALS 2)
CPU
Y
ON
OFF
ON
As soon as HALT mode is entered, and if the
AWUEN bit has been set in the AWUCSR register,
the AWU RC oscillator provides a clock signal
I BIT
X 4)
(f
). Its frequency is divided by a fixed divid-
AWU_RC
256 OR 4096 CPU CLOCK
CYCLE DELAY
er and a programmable prescaler controlled by the
AWUPR register. The output of this prescaler pro-
vides the delay time. When the delay has elapsed
the AWUF flag is set by hardware and an interrupt
wakes-up the MCU from Halt mode. At the same
time the main oscillator is immediately turned on
and a 256 or 4096 cycle delay is used to stabilize
it. After this start-up delay, the CPU resumes oper-
ation by servicing the AWUFH interrupt. The AWU
flag and its associated interrupt are cleared by
software reading the AWUCSR register.
OSCILLATOR
PERIPHERALS
CPU
ON
ON
ON
X 4)
I BIT
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Notes:
To compensate for any frequency dispersion of
the AWU RC oscillator, it can be calibrated by
1. This delay occurs only if the MCU exits ACTIVE-
HALT mode by means of a RESET.
2. Peripherals clocked with an external clock
source can still be active.
3. Only the RTC1 interrupt and some specific inter-
rupts can exit the MCU from ACTIVE-HALT mode.
Refer to Table 5, “Interrupt Mapping,” on page 37
for more details.
4. Before servicing an interrupt, the CC register is
pushed on the stack. The I bit of the CC register is
set during the interrupt routine and cleared when
the CC register is popped.
measuring the clock frequency f
and then
AWU_RC
calculating the right prescaler value. Measurement
mode is enabled by setting the AWUM bit in the
AWUCSR register in Run mode. This connects
f
to the input capture of the 12-bit Auto-Re-
AWU_RC
load timer, allowing the f
to be measured
AWU_RC
using the main oscillator clock as a reference time-
base.
44/159
1
ST7LITE1xB
POWER SAVING MODES (Cont’d)
Similarities with Halt mode
– In AWUFH mode, the main oscillator is turned off
causing all internal processing to be stopped, in-
cluding the operation of the on-chip peripherals.
None of the peripherals are clocked except those
which get their clock supply from another clock
generator (such as an external or auxiliary oscil-
lator like the AWU oscillator).
The following AWUFH mode behaviour is the
same as normal Halt mode:
– The MCU can exit AWUFH mode by means of
any interrupt with exit from Halt capability or a re-
set (see Section 9.4 HALT MODE).
– When entering AWUFH mode, the I bit in the CC
register is forced to 0 to enable interrupts. There-
fore, if an interrupt is pending, the MCU wakes
up immediately.
– The compatibility of Watchdog operation with
AWUFH mode is configured by the WDGHALT
option bit in the option byte. Depending on this
setting, the HALT instruction when executed
while the Watchdog system is enabled, can gen-
erate a Watchdog RESET.
Figure 30. AWUF Halt Timing Diagram
t
AWU
RUN MODE
HALT MODE
256 OR 4096 t
RUN MODE
CPU
f
CPU
f
AWU_RC
Clear
by software
AWUFH interrupt
45/159
1
ST7LITE1xB
POWER SAVING MODES (Cont’d)
Figure 31. AWUFH Mode Flow-chart
Notes:
1. WDGHALT is an option bit. See option byte sec-
tion for more details.
2. Peripheral clocked with an external clock source
can still be active.
HALT INSTRUCTION
(Active-Halt disabled)
(AWUCSR.AWUEN=1)
3. Only an AWUFH interrupt and some specific in-
terrupts can exit the MCU from HALT mode (such
as external interrupt). Refer to Table 5, “Interrupt
Mapping,” on page 37 for more details.
4. Before servicing an interrupt, the CC register is
pushed on the stack. The I[1:0] bits of the CC reg-
ister are set to the current software priority level of
the interrupt routine and recovered when the CC
register is popped.
ENABLE
WATCHDOG
0
DISABLE
WDGHALT 1)
1
AWU RC OSC
MAIN OSC
ON
OFF
OFF
OFF
10
WATCHDOG
RESET
PERIPHERALS 2)
CPU
5. If the PLL is enabled by option byte, it outputs
the clock after an additional delay of t
Figure 13).
(see
STARTUP
I[1:0] BITS
N
RESET
Y
N
INTERRUPT 3)
AWU RC OSC
MAIN OSC
OFF
ON
Y
PERIPHERALS
CPU
I[1:0] BITS
OFF
ON
XX 4)
256 OR 4096 CPU CLOCK
5)
CYCLE DELAY
AWU RC OSC
MAIN OSC
PERIPHERALS
CPU
OFF
ON
ON
ON
I[1:0] BITS
XX 4)
FETCH RESET VECTOR
OR SERVICE INTERRUPT
46/159
1
ST7LITE1xB
POWER SAVING MODES (Cont’d)
9.6.0.1 Register Description
7
0
AWUFH CONTROL/STATUS REGISTER
(AWUCSR)
AWU AWU AWU AWU AWU AWU AWU AWU
PR7 PR6 PR5 PR4 PR3 PR2 PR1 PR0
Read/Write
Reset Value: 0000 0000 (00h)
Bits 7:0= AWUPR[7:0] Auto Wake Up Prescaler
These 8 bits define the AWUPR Dividing factor (as
explained below:
7
0
AWU AWU AWU
EN
0
0
0
0
0
AWUPR[7:0]
Dividing factor
F
M
00h
01h
...
Forbidden
Bits 7:3 = Reserved.
1
...
FEh
FFh
254
255
Bit 1= AWUF Auto Wake Up Flag
This bit is set by hardware when the AWU module
generates an interrupt and cleared by software on
reading AWUCSR. Writing to this bit does not
change its value.
In AWU mode, the period that the MCU stays in
Halt Mode (t
fined by
in Figure 30 on page 45) is de-
AWU
0: No AWU interrupt occurred
1: AWU interrupt occurred
1
t
= 64 × AWUPR × ------------------------- + t
RCSTRT
AWU
f
AWURC
Bit 1= AWUM Auto Wake Up Measurement
This bit enables the AWU RC oscillator and con-
nects its output to the input capture of the 12-bit
Auto-Reload timer. This allows the timer to be
used to measure the AWU RC oscillator disper-
sion and then compensate this dispersion by pro-
viding the right value in the AWUPRE register.
0: Measurement disabled
This prescaler register can be programmed to
modify the time that the MCU stays in Halt mode
before waking up automatically.
Note: If 00h is written to AWUPR, depending on
the product, an interrupt is generated immediately
after a HALT instruction, or the AWUPR remains
unchanged.
1: Measurement enabled
Bit 0 = AWUEN Auto Wake Up From Halt Enabled
This bit enables the Auto Wake Up From Halt fea-
ture: once HALT mode is entered, the AWUFH
wakes up the microcontroller after a time delay de-
pendent on the AWU prescaler value. It is set and
cleared by software.
0: AWUFH (Auto Wake Up From Halt) mode disa-
bled
1: AWUFH (Auto Wake Up From Halt) mode ena-
bled
AWUFH PRESCALER REGISTER (AWUPR)
Read/Write
Table 7. AWU Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
AWUPR
Reset Value
AWUPR7 AWUPR6 AWUPR5 AWUPR4 AWUPR3 AWUPR2 AWUPR1 AWUPR0
0049h
004Ah
1
1
1
1
1
1
1
1
AWUCSR
Reset Value
0
0
0
0
0
AWUF
AWUM
AWUEN
47/159
1
ST7LITE1xB
10 I/O PORTS
10.1 INTRODUCTION
The I/O ports allow data transfer. An I/O port can
contain up to 8 pins. Each pin can be programmed
independently either as a digital input or digital
output. In addition, specific pins may have several
other functions. These functions can include exter-
nal interrupt, alternate signal input/output for on-
chip peripherals or analog input.
son if one of the interrupt pins is tied low, it may
mask the others.
External interrupts are hardware interrupts. Fetch-
ing the corresponding interrupt vector automatical-
ly clears the request latch. Changing the sensitivity
of a particular external interrupt clears this pending
interrupt. This can be used to clear unwanted
pending interrupts.
10.2 FUNCTIONAL DESCRIPTION
Spurious interrupts
A Data Register (DR) and a Data Direction Regis-
ter (DDR) are always associated with each port.
The Option Register (OR), which allows input/out-
put options, may or may not be implemented. The
following description takes into account the OR
register. Refer to the Port Configuration table for
device specific information.
When enabling/disabling an external interrupt by
setting/resetting the related OR register bit, a spu-
rious interrupt is generated if the pin level is low
and its edge sensitivity includes falling/rising edge.
This is due to the edge detector input which is
switched to '1' when the external interrupt is disa-
bled by the OR register.
An I/O pin is programmed using the corresponding
bits in the DDR, DR and OR registers: bit x corre-
sponding to pin x of the port.
To avoid this unwanted interrupt, a "safe" edge
sensitivity (rising edge for enabling and falling
edge for disabling) has to be selected before
changing the OR register bit and configuring the
appropriate sensitivity again.
Figure 32 shows the generic I/O block diagram.
10.2.1 Input Modes
Caution: In case a pin level change occurs during
these operations (asynchronous signal input), as
interrupts are generated according to the current
sensitivity, it is advised to disable all interrupts be-
fore and to reenable them after the complete pre-
vious sequence in order to avoid an external inter-
rupt occurring on the unwanted edge.
Clearing the DDRx bit selects input mode. In this
mode, reading its DR bit returns the digital value
from that I/O pin.
If an OR bit is available, different input modes can
be configured by software: floating or pull-up. Re-
fer to I/O Port Implementation section for configu-
ration.
This corresponds to the following steps:
1. To enable an external interrupt:
Notes:
1. Writing to the DR modifies the latch value but
does not change the state of the input pin.
2. Do not use read/modify/write instructions
(BSET/BRES) to modify the DR register.
– set the interrupt mask with the SIM instruction
(in cases where a pin level change could oc-
cur)
– select rising edge
– enable the external interrupt through the OR
register
– select the desired sensitivity if different from
rising edge
– reset the interrupt mask with the RIM instruc-
tion (in cases where a pin level change could
occur)
10.2.1.1 External Interrupt Function
Depending on the device, setting the ORx bit while
in input mode can configure an I/O as an input with
interrupt. In this configuration, a signal edge or lev-
el input on the I/O generates an interrupt request
via the corresponding interrupt vector (eix).
Falling or rising edge sensitivity is programmed in-
dependently for each interrupt vector. The Exter-
nal Interrupt Control Register (EICR) or the Miscel-
laneous Register controls this sensitivity, depend-
ing on the device.
2. To disable an external interrupt:
– set the interrupt mask with the SIM instruction
SIM (in cases where a pin level change could
occur)
– select falling edge
– disable the external interrupt through the OR
register
Each external interrupt vector is linked to a dedi-
cated group of I/O port pins (see pinout description
and interrupt section). If several I/O interrupt pins
on the same interrupt vector are selected simulta-
neously, they are logically combined. For this rea-
48/159
1
ST7LITE1xB
– select rising edge
Pin Description table describes which peripheral
signals can be input/output to which ports.
– reset the interrupt mask with the RIM instruc-
tion (in cases where a pin level change could
occur)
A signal coming from an on-chip peripheral can be
output on an I/O. To do this, enable the on-chip
peripheral as an output (enable bit in the peripher-
al’s control register). The peripheral configures the
I/O as an output and takes priority over standard I/
O programming. The I/O’s state is readable by ad-
dressing the corresponding I/O data register.
10.2.2 Output Modes
Setting the DDRx bit selects output mode. Writing
to the DR bits applies a digital value to the I/O
through the latch. Reading the DR bits returns the
previously stored value.
Configuring an I/O as floating enables alternate
function input. It is not recommended to configure
an I/O as pull-up as this will increase current con-
sumption. Before using an I/O as an alternate in-
put, configure it without interrupt. Otherwise spuri-
ous interrupts can occur.
If an OR bit is available, different output modes
can be selected by software: push-pull or open-
drain. Refer to I/O Port Implementation section for
configuration.
Configure an I/O as input floating for an on-chip
peripheral signal which can be input and output.
DR Value and Output Pin Status
DR
Push-Pull
Open-Drain
Caution:
0
1
V
V
V
OL
Floating
OL
I/Os which can be configured as both an analog
and digital alternate function need special atten-
tion. The user must control the peripherals so that
the signals do not arrive at the same time on the
same pin. If an external clock is used, only the
clock alternate function should be employed on
that I/O pin and not the other alternate function.
OH
10.2.3 Alternate Functions
Many ST7s I/Os have one or more alternate func-
tions. These may include output signals from, or
input signals to, on-chip peripherals. The Device
49/159
1
ST7LITE1xB
I/O PORTS (Cont’d)
Figure 32. I/O Port General Block Diagram
ALTERNATE
OUTPUT
From on-chip peripheral
1
0
REGISTER
ACCESS
P-BUFFER
(see table below)
V
DD
ALTERNATE
ENABLE
BIT
PULL-UP
(see table below)
DR
V
DD
DDR
OR
PULL-UP
CONDITION
PAD
If implemented
OR SEL
DDR SEL
DR SEL
N-BUFFER
DIODES
(see table below)
ANALOG
INPUT
CMOS
SCHMITT
TRIGGER
1
0
ALTERNATE
INPUT
To on-chip peripheral
EXTERNAL
INTERRUPT
REQUEST (ei )
Combinational
Logic
FROM
OTHER
BITS
x
SENSITIVITY
SELECTION
Note: Refer to the Port Configuration
table for device specific information.
Table 8. I/O Port Mode Options
Configuration Mode
Diodes
Pull-Up
P-Buffer
to V
to V
SS
DD
Floating with/without Interrupt
Input
Off
On
Off
Pull-up with/without Interrupt
On
On
Push-pull
Output
On
Off
Off
Open Drain (logic level)
Legend: Off - implemented not activated
On - implemented and activated
50/159
1
ST7LITE1xB
I/O PORTS (Cont’d)
Table 9. I/O Configurations
Hardware Configuration
DR REGISTER ACCESS
W
R
DR
REGISTER
DATA BUS
PAD
ALTERNATE INPUT
To on-chip peripheral
FROM
OTHER
PINS
EXTERNAL INTERRUPT
SOURCE (ei )
x
COMBINATIONAL
LOGIC
INTERRUPT
CONDITION
POLARITY
SELECTION
ANALOG INPUT
DR REGISTER ACCESS
PAD
R/W
DR
REGISTER
DATA BUS
DR REGISTER ACCESS
R/W
DR
REGISTER
DATA BUS
PAD
ALTERNATE
ENABLE
BIT
ALTERNATE
OUTPUT
From on-chip peripheral
Notes:
1. When the I/O port is in input configuration and the associated alternate function is enabled as an output,
reading the DR register will read the alternate function output status.
2. When the I/O port is in output configuration and the associated alternate function is enabled as an input,
the alternate function reads the pin status given by the DR register content.
51/159
1
ST7LITE1xB
I/O PORTS (Cont’d)
Analog alternate function
10.4 UNUSED I/O PINS
Configure the I/O as floating input to use an ADC
input. The analog multiplexer (controlled by the
ADC registers) switches the analog voltage
present on the selected pin to the common analog
rail, connected to the ADC input.
Unused I/O pins must be connected to fixed volt-
age levels. Refer to Section 13.8.
10.5 LOW POWER MODES
Analog Recommendations
Mode
WAIT
HALT
Description
Do not change the voltage level or loading on any
I/O while conversion is in progress. Do not have
clocking pins located close to a selected analog
pin.
No effect on I/O ports. External interrupts
cause the device to exit from WAIT mode.
No effect on I/O ports. External interrupts
cause the device to exit from HALT mode.
WARNING: The analog input voltage level must
be within the limits stated in the absolute maxi-
mum ratings.
10.6 INTERRUPTS
The external interrupt event generates an interrupt
if the corresponding configuration is selected with
DDR and OR registers and if the I bit in the CC
register is cleared (RIM instruction).
10.3 I/O PORT IMPLEMENTATION
The hardware implementation on each I/O port de-
pends on the settings in the DDR and OR registers
and specific I/O port features such as ADC input or
open drain.
Enable Exit
Control from
Exit
from
Halt
Event
Flag
Interrupt Event
Bit
Wait
Switching these I/O ports from one state to anoth-
er should be done in a sequence that prevents un-
wanted side effects. Recommended safe transi-
tions are illustrated in Figure 33. Other transitions
are potentially risky and should be avoided, since
they may present unwanted side-effects such as
spurious interrupt generation.
External interrupt on
selected external
event
DDRx
ORx
-
Yes
Yes
Related Documentation
AN 970: SPI Communication between ST7 and
EEPROM
Figure 33. Interrupt I/O Port State Transitions
AN1045: S/W implementation of I2C bus master
AN1048: Software LCD driver
01
00
10
11
INPUT
floating/pull-up
interrupt
INPUT
floating
(reset state)
OUTPUT
open-drain
OUTPUT
push-pull
= DDR, OR
XX
52/159
1
ST7LITE1xB
I/O PORTS (Cont’d)
10.7 DEVICE-SPECIFIC I/O PORT CONFIGURATION
The I/O port register configurations are summa-
rised as follows.
Interrupt Ports
Ports where the external interrupt capability is
selected using the EISR register
Standard Ports
PA7:0, PB6:0
MODE
DDR
OR
0
floating input
0
0
1
1
MODE
DDR
OR
0
pull-up interrupt input
open drain output
push-pull output
1
floating input
pull-up input
0
0
1
1
0
1
1
open drain output
push-pull output
0
1
PC1:0 (multiplexed with OSC1,OSC2)
MODE
floating input
DDR
0
1
push-pull output
The selection between OSC1 or PC0 and OSC2 or
PC1 is done by option byte. Refer to section 15.1
on page 149. Interrupt capability is not available
on PC1:0.
Note: PCOR not implemented but p-transistor al-
ways active in output mode (refer to Figure 32 on
page 50)
Table 10. Port Configuration (Standard ports)
Input
Output
Port
Pin name
PA7:0
OR = 0
floating
floating
OR = 1
OR = 0
open drain
open drain
OR = 1
push-pull
push-pull
Port A
Port B
pull-up
pull-up
PB6:0
Note: On ports where the external interrupt capability is selected using the EISR register, the configura-
tion will be as follows:
Input
Output
Port
Pin name
PA7:0
OR = 0
floating
floating
OR = 1
OR = 0
open drain
open drain
OR = 1
push-pull
push-pull
Port A
Port B
pull-up interrupt
pull-up interrupt
PB6:0
Table 11. I/O Port Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
PADR
MSB
1
LSB
1
0000h
0001h
Reset Value
1
1
0
1
0
1
0
1
0
1
0
PADDR
MSB
0
LSB
0
Reset Value
0
53/159
1
ST7LITE1xB
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
PAOR
MSB
0
LSB
0
0002h
0003h
0004h
0005h
0006h
0007h
Reset Value
1
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
1
0
PBDR
MSB
1
LSB
1
Reset Value
1
0
0
0
0
PBDDR
MSB
0
LSB
0
Reset Value
PBOR
MSB
0
LSB
0
Reset Value
PCDR
MSB
0
LSB
1
Reset Value
PCDDR
MSB
0
LSB
0
Reset Value
10.8 MULTIPLEXED INPUT/OUTPUT PORTS
OSC1/PC0 are multiplexed on one pin (pin20) and
OSC2/PC1 are multiplexed on another pin (pin
19).
54/159
1
ST7LITE1xB
11 ON-CHIP PERIPHERALS
11.1 WATCHDOG TIMER (WDG)
11.1.1 Introduction
■ Optional
reset
on
HALT
instruction
(configurable by option byte)
The Watchdog timer is used to detect the occur-
rence of a software fault, usually generated by ex-
ternal interference or by unforeseen logical condi-
tions, which causes the application program to
abandon its normal sequence. The Watchdog cir-
cuit generates an MCU reset on expiry of a pro-
grammed time period, unless the program refresh-
es the counter’s contents before the T6 bit be-
comes cleared.
■ Hardware Watchdog selectable by option byte
11.1.3 Functional Description
The counter value stored in the CR register (bits
T[6:0]), is decremented every 16000 machine cy-
cles, and the length of the timeout period can be
programmed by the user in 64 increments.
11.1.2 Main Features
If the watchdog is activated (the WDGA bit is set)
and when the 7-bit timer (bits T[6:0]) rolls over
from 40h to 3Fh (T6 becomes cleared), it initiates
a reset cycle pulling low the reset pin for typically
30µs.
■ Programmable free-running downcounter (64
increments of 16000 CPU cycles)
■ Programmable reset
■ Reset (if watchdog activated) when the T6 bit
reaches zero
Figure 34. Watchdog Block Diagram
RESET
WATCHDOG CONTROL REGISTER (CR)
T5
T0
WDGA T6
T1
T4
T2
T3
7-BIT DOWNCOUNTER
CLOCK DIVIDER
f
CPU
÷16000
55/159
1
ST7LITE1xB
WATCHDOG TIMER (Cont’d)
The application program must write in the CR reg-
ister at regular intervals during normal operation to
prevent an MCU reset. This downcounter is free-
running: it counts down even if the watchdog is
disabled. The value to be stored in the CR register
must be between FFh and C0h (see Table 12
.Watchdog Timing):
Refer to the Option Byte description in section 15
on page 149.
11.1.4.1 Using Halt Mode with the WDG
(WDGHALT option)
If Halt mode with Watchdog is enabled by option
byte (No watchdog reset on HALT instruction), it is
recommended before executing the HALT instruc-
tion to refresh the WDG counter, to avoid an unex-
pected WDG reset immediately after waking up
the microcontroller. Same behaviour in active-halt
mode.
– The WDGA bit is set (watchdog enabled)
– The T6 bit is set to prevent generating an imme-
diate reset
– The T[5:0] bits contain the number of increments
which represents the time delay before the
watchdog produces a reset.
11.1.5 Interrupts
Following a reset, the watchdog is disabled. Once
activated it cannot be disabled, except by a reset.
None.
The T6 bit can be used to generate a software re-
set (the WDGA bit is set and the T6 bit is cleared).
11.1.6 Register Description
CONTROL REGISTER (WDGCR)
Read/Write
If the watchdog is activated, the HALT instruction
will generate a Reset.
Reset Value: 0111 1111 (7Fh)
Table 12.Watchdog Timing
7
0
f
= 8MHz
CPU
WDG
Counter Code
min
[ms]
max
[ms]
WDGA T6
T5
T4
T3
T2
T1
T0
C0h
FFh
1
2
Bit 7 = WDGA Activation bit.
127
128
This bit is set by software and only cleared by
hardware after a reset. When WDGA = 1, the
watchdog can generate a reset.
Notes:
1. The timing variation shown in Table 12 is due to
the unknown status of the prescaler when writing
to the CR register.
2. The number of CPU clock cycles applied during
the RESET phase (256 or 4096) must be taken
into account in addition to these timings.
0: Watchdog disabled
1: Watchdog enabled
Note: This bit is not used if the hardware watch-
dog option is enabled by option byte.
Bit 6:0 = T[6:0] 7-bit timer (MSB to LSB).
These bits contain the decremented value. A reset
is produced when it rolls over from 40h to 3Fh (T6
becomes cleared).
11.1.4 Hardware Watchdog Option
If Hardware Watchdog is selected by option byte,
the watchdog is always active and the WDGA bit in
the CR is not used.
Table 13. Watchdog Timer Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
WDGCR
Reset Value
WDGA
0
T6
1
T5
1
T4
1
T3
1
T2
1
T1
1
T0
1
002Eh
56/159
1
ST7LITE1xB
11.2 DUAL 12-BIT AUTORELOAD TIMER 4 (AT4)
11.2.1 Introduction
– Generation of four independent PWMx signals
– Dead time generation for Half bridge driving
The 12-bit Autoreload Timer can be used for gen-
eral-purpose timing functions. It is based on one or
two free-running 12-bit upcounters with an input
capture register and four PWM output channels.
There are 7 external pins:
mode with programmable dead time
– Frequency 2 kHz - 4 MHz (@ 8 MHz f
– Programmable duty-cycles
– Polarity control
)
CPU
– Programmable output modes
■ Output Compare Mode
■ Input Capture Mode
– Four PWM outputs
– ATIC/LTIC pins for the Input Capture function
– BREAK pin for forcing a break condition on the
PWM outputs
– 12-bit input capture register (ATICR)
– Triggered by rising and falling edges
– Maskable IC interrupt
11.2.2 Main Features
■ Single Timer or Dual Timer mode with two 12-bit
upcounters (CNTR1/CNTR2) and two 12-bit
autoreload registers (ATR1/ATR2)
■ Maskable overflow interrupts
■ PWM mode
– Long range input capture
■ Internal/External Break control
■ Flexible Clock control
■ One Pulse mode on PWM2/3
■ Force Update
Figure 35. Single Timer Mode (ENCNTR2=0)
ATIC
12-bit Input Capture
Edge Detection Circuit
CMP
Interrupt
Output Compare
OE0
PWM0 Duty Cycle Generator
PWM1 Duty Cycle Generator
PWM0
PWM1
Dead Time
Generator
OE1
12-Bit Autoreload Register 1
DTE bit
OE2
OE3
PWM2 Duty Cycle Generator
PWM3 Duty Cycle Generator
PWM2
PWM3
12-Bit Upcounter 1
OVF1 interrupt
BPEN bit
OFF
Clock
f
CPU
Control
32MHz
1 ms from
Lite Timer
57/159
1
ST7LITE1xB
DUAL 12-BIT AUTORELOAD TIMER 4 (Cont’d)
Figure 36. Dual Timer Mode (ENCNTR2=1)
12-bit Input Capture
ATIC
Edge Detection Circuit
CMP
Interrupt
Output Compare
OE0
OE1
12-Bit Autoreload Register 1
PWM0 Duty Cycle Generator
PWM1 Duty Cycle Generator
PWM0
PWM1
Dead Time
Generator
12-Bit Upcounter 1
OVF1 interrupt
OVF2 interrupt
DTE bit
OE2
OE3
PWM2 Duty Cycle Generator
PWM2
PWM3
12-Bit Upcounter 2
One Pulse
mode
PWM3 Duty Cycle Generator
12-Bit Autoreload Register 2
BPEN bit
OP_EN bit
Output Compare
CMP Interrupt
OFF
Clock
f
CPU
Control
32MHz
1 ms from
Lite Timer
LTIC
58/159
1
ST7LITE1xB
DUAL 12-BIT AUTORELOAD TIMER 4 (Cont’d)
11.2.3 Functional Description
11.2.3.1 PWM Mode
The maximum available resolution for the PWMx
duty cycle is:
Resolution = 1 / (4096 - ATR)
This mode allows up to four Pulse Width Modulat-
ed signals to be generated on the PWMx output
pins.
where ATR is equal to 0. With this maximum reso-
lution, 0% and 100% duty cycle can be obtained
by changing the polarity.
PWM Frequency
At reset, the counter starts counting from 0.
The four PWM signals can have the same fre-
quency (f
) or can have two different frequen-
PWM
When a upcounter overflow occurs (OVF event),
the preloaded Duty cycle values are transferred to
the active Duty Cycle registers and the PWMx sig-
nals are set to a high level. When the upcounter
matches the active DCRx value the PWMx signals
are set to a low level. To obtain a signal on a
PWMx pin, the contents of the corresponding ac-
tive DCRx register must be greater than the con-
tents of the ATR register.
cies. This is selected by the ENCNTR2 bit which
enables single timer or dual timer mode (see Fig-
ure 1 and Figure 2).
The frequency is controlled by the counter period
and the ATR register value. In dual timer mode,
PWM2 and PWM3 can be generated with a differ-
ent frequency controlled by CNTR2 and ATR2.
f
= f
/ (4096 - ATR)
PWM
COUNTER
The maximum value of ATR is 4094 because it
must be lower than the DCR value which must be
4095 in this case.
Following the above formula,
– If f is 4 MHz the maximum value of
COUNTER
PWM
,
f
is 2 MHz (ATR register value = 4094), the
Polarity Inversion
minimum value is 1 kHz (ATR register value = 0).
The polarity bits can be used to invert any of the
four output signals. The inversion is synchronized
with the counter overflow if the corresponding
transfer bit in the ATCSR2 register is set (reset
value). See Figure 3.
– If f is 32 MHz the maximum value of
COUNTER
,
f
is 8 MHz (ATR register value = 4092), the
PWM
minimum value is 8 kHz (ATR register value = 0).
Notes:
1. The maximum value of ATR is 4094 because it
must be lower than the DC4R value which must be
4095 in this case.
Figure 37. PWM Polarity Inversion
inverter
PWMx
2. To update the DCRx registers at 32 MHz, the
following precautions must be taken:
PWMx
PIN
– if the PWM frequency is < 1 MHz and the TRANx
bit is set asynchronously, it should be set twice
after a write to the DCRx registers.
PWMxCSR Register
OPx
– if the PWM frequency is > 1 MHz, the TRANx bit
should be set along with FORCEx bit with the
same instruction (use a load instruction and not
2 bset instructions).
DFF
TRANx
ATCSR2 Register
Duty Cycle
counter
overflow
The duty cycle is selected by programming the
DCRx registers. These are preload registers. The
DCRx values are transferred in Active duty cycle
registers after an overflow event if the correspond-
ing transfer bit (TRANx bit) is set.
The Data Flip Flop (DFF) applies the polarity inver-
sion when triggered by the counter overflow input.
Output Control
The TRAN1 bit controls the PWMx outputs driven
by counter 1 and the TRAN2 bit controls the
PWMx outputs driven by counter 2.
The PWMx output signals can be enabled or disa-
bled using the OEx bits in the PWMCR register.
PWM generation and output compare are done by
comparing these active DCRx values with the
counter.
59/159
1
ST7LITE1xB
DUAL 12-BIT AUTORELOAD TIMER 4 (Cont’d)
Figure 38. PWM Function
4095
DUTY CYCLE
REGISTER
(DCRx)
AUTO-RELOAD
REGISTER
(ATR)
000
t
WITH OE=1
AND OPx=0
WITH OE=1
AND OPx=1
Figure 39. PWM Signal from 0% to 100% Duty Cycle
f
COUNTER
ATR= FFDh
FFFh
COUNTER
FFDh
FFEh
FFDh
FFEh
FFFh
FFDh
FFEh
DCRx=000h
DCRx=FFDh
DCRx=FFEh
DCRx=000h
t
60/159
1
ST7LITE1xB
DUAL 12-BIT AUTORELOAD TIMER 4 (Cont’d)
11.2.3.2 Dead Time Generation
Notes:
A dead time can be inserted between PWM0 and
PWM1 using the DTGR register. This is required
for half-bridge driving where PWM signals must
not be overlapped. The non-overlapping PWM0/
PWM1 signals are generated through a program-
mable dead time by setting the DTE bit.
1. Dead time is generated only when DTE=1 and
DT[6:0] ≠ 0. If DTE is set and DT[6:0]=0, PWM out-
put signals will be at their reset state.
2. Half Bridge driving is possible only if polarities of
PWM0 and PWM1 are not inverted, i.e. if OP0 and
OP1 are not set. If polarity is inverted, overlapping
PWM0/PWM1 signals will be generated.
Dead time value = DT[6:0] x Tcounter1
DTGR[7:0] is buffered inside so as to avoid de-
forming the current PWM cycle. The DTGR effect
will take place only after an overflow.
3. Dead Time generation does not work at 1 ms
timebase.
Figure 40. Dead Time Generation
T
counter1
CK_CNTR1
CNTR1
DCR0
DCR0+1
OVF
ATR1
counter = DCR0
PWM 0
PWM 1
counter = DCR1
T
dt
PWM 0
PWM 1
T
dt
T = DT[6:0] x T
dt
counter1
In the above example, when the DTE bit is set:
With this programmable delay (Tdt), the PWM0
and PWM1 signals which are generated are not
overlapped.
– PWM goes low at DCR0 match and goes high at
ATR1+Tdt
– PWM1 goes high at DCR0+Tdt and goes low at
ATR match.
61/159
1
ST7LITE1xB
DUAL 12-BIT AUTORELOAD TIMER 4 (Cont’d)
11.2.3.3 Break Function
counters respectively. In Dual Timer Mode, the
break for PWM2 and PWM3 is enabled by the
BREN2 bit. In Single Timer Mode, the BREN1 bit
enables the break for all PWM channels.
The break function can be used to perform an
emergency shutdown of the application being driv-
en by the PWM signals.
When a break function is activated (BA bit =1 and
BREN1/BREN2 =1):
The break function is activated by the external
BREAK pin or internal comparator output. This can
be selected by using the BRSEL bit in BREAKCR
Register. In order to use the break function it must
be previously enabled by software setting the
BPEN bit in the BREAKCR register.
– The break pattern (PWM[3:0] bits in the BREAK-
CR) is forced directly on the PWMx output pins if
respective OEx is set. (after the inverter).
– The 12-bit PWM counter CNTR1 is put to its re-
set value, i.e. 00h (if BREN1 = 1).
The Break active level can be programmed by the
BREDGE bit in the BREAKCR register. When an
active level is detected on the BREAK pin, the BA
bit is set and the break function is activated. In this
case, the PWM signals are forced to BREAK value
if respective OEx bit is set in PWMCR register.
– The 12-bit PWM counter CNTR2 is put to its re-
set value,i.e. 00h (if BREN2 = 1).
– ATR1, ATR2, Preload and Active DCRx are put
to their reset values.
– Counters stop counting.
Software can set the BA bit to activate the break
function without using the BREAK pin. The BREN1
and BREN2 bits in the BREAKEN Register are
used to enable the break activation on the 2
When the break function is deactivated after ap-
plying the break (BA bit goes from 1 to 0 by soft-
ware), Timer takes the control of PWM ports.
Figure 41. Block Diagram of Break Function
BREAK pin
BREDGE
BRSEL
BREAKCR Register
Level
Selection
Comparator
BREAKCR Register
OEx
BA
BPEN PWM3 PWM2 PWM1 PWM0
PWM0
PWM1
PWM2
PWM3
(Inverters)
PWM0
PWM1
PWM2
PWM3
BREAKEN Register
PWM0/1 Break Enable
PWM2/3 Break Enable
BREN2
BREN1
ENCNTR2 bit
62/159
1
ST7LITE1xB
DUAL 12-BIT AUTORELOAD TIMER 4 (Cont’d)
11.2.3.4 Output Compare Mode
CNTR1 is compared with DCR0 or DCR1 and
CNTR2 is compared with DCR2 or DCR3.
To use this function, load a 12-bit value in the
Preload DCRxH and DCRxL registers.
Notes:
When the 12-bit upcounter CNTR1 reaches the
value stored in the Active DCRxH and DCRxL reg-
isters, the CMPFx bit in the PWMxCSR register is
set and an interrupt request is generated if the
CMPIE bit is set.
1. The output compare function is only available
for DCRx values other than 0 (reset value).
2. Duty cycle registers are buffered internally. The
CPU writes in Preload Duty Cycle Registers and
these values are transferred in Active Duty Cycle
Registers after an overflow event if the corre-
sponding transfer bit (TRANx bit) is set. Output
compare is done by comparing these active DCRx
values with the counters.
In single Timer mode the output compare function
is performed only on CNTR1. The difference be-
tween both the modes is that, in Single Timer
mode, CNTR1 can be compared with any of the
four DCR registers, and in Dual Timer mode,
Figure 42. Block Diagram of Output Compare Mode (single timer)
DCRx
PRELOAD DUTY CYCLE REG0/1/2/3
(ATCSR2) TRAN1
(ATCSR)
OVF
ACTIVE DUTY CYCLE REGx
OUTPUT COMPARE CIRCUIT
CNTR1
COUNTER 1
CMPFx (PWMxCSR)
CMPIE (ATCSR)
CMP
INTERRUPT REQUEST
63/159
1
ST7LITE1xB
DUAL 12-BIT AUTORELOAD TIMER 4 (Cont’d)
11.2.3.5 Input Capture Mode
The 12-bit ATICR register is used to latch the val-
ue of the 12-bit free running upcounter CNTR1 af-
ter a rising or falling edge is detected on the ATIC
pin. When an input capture occurs, the ICF bit is
set and the ATICR register contains the value of
the free running upcounter. An IC interrupt is gen-
erated if the ICIE bit is set. The ICF bit is reset by
reading the ATICRH/ATICRL register when the
ICF bit is set. The ATICR is a read only register
and always contains the free running upcounter
value which corresponds to the most recent input
capture. Any further input capture is inhibited while
the ICF bit is set.
Figure 43. Block Diagram of Input Capture Mode
ATIC
12-BIT INPUT CAPTURE REGISTER
ATICR
ATCSR
IC INTERRUPT
REQUEST
ICF
ICIE
CK1
CK0
f
LTIMER
(1 ms
timebase
@ 8 MHz)
12-BIT UPCOUNTER1
12-BIT AUTORELOAD REGISTER
f
CPU
CNTR1
ATR1
32 MHz
OFF
Figure 44. Input Capture timing diagram
f
COUNTER
COUNTER1
ATIC PIN
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
INTERRUPT
ATICR READ
INTERRUPT
ICF FLAG
09h
xxh
04h
t
64/159
1
ST7LITE1xB
DUAL 12-BIT AUTORELOAD TIMER 4 (Cont’d)
■ Long Input Capture
– The signal to be captured is connected to LTIC
pin
Pulses that last more than 8μs can be measured
with an accuracy of 4μs if f
lowing conditions:
= 8 MHz in the fol-
– Input Capture registers LTICR, ATICRH and
ATICRL are read
OSC
– The 12-bit AT4 Timer is clocked by the Lite Timer
(RTC pulse: CK[1:0] = 01 in the ATCSR register)
This configuration allows to cascade the Lite Timer
and the 12-bit AT4 Timer to get a 20-bit input cap-
ture value. Refer to Figure 11.
– The ICS bit in the ATCSR2 register is set so that
the LTIC pin is used to trigger the AT4 Timer cap-
ture.
Figure 45. Long Range Input Capture Block Diagram
LTICR
8 LSB bits
8-bit Input Capture Register
f
OSC/32
8-bit Timebase Counter1
LITE TIMER
12-Bit ARTIMER
20
cascaded
bits
ATR1
12-bit AutoReload Register
fLTIMER
CNTR1
fcpu
32MHz
OFF
ICS
12-bit Upcounter1
LTIC
ATIC
ATICR
1
0
12 MSB bits
12-bit Input Capture Register
Notes:
– And then set the ICIE bit of desired interrupt.
1. Since the input capture flags (ICF) for both tim-
ers (AT4 Timer and LT Timer) are set when signal
transition occurs, software must mask one inter-
rupt by clearing the corresponding ICIE bit before
setting the ICS bit.
3. How to compute a pulse length with long input
capture feature.
As both timers are used, computing a pulse length
is not straight-forward. The procedure is as fol-
lows:
2. If the ICS bit changes (from 0 to 1 or from 1 to
0), a spurious transition might occur on the input
capture signal because of different values on LTIC
and ATIC. To avoid this situation, it is recommend-
ed to do as follows:
– At the first input capture on the rising edge of the
pulse, we assume that values in the registers are
as follows:
LTICR = LT1
ATICRH = ATH1
ATICRL = ATL1
Hence ATICR1 [11:0] = ATH1 & ATL1
– First, reset both ICIE bits.
– Then set the ICS bit.
– Reset both ICF bits.
Refer to Figure 12.
65/159
1
ST7LITE1xB
DUAL 12-BIT AUTORELOAD TIMER 4 (Cont’d)
– At the second input capture on the falling edge of
the pulse, we assume that the values in the reg-
isters are as follows:
Now pulse width P between first capture and sec-
ond capture will be:
P = decimal (F9 – LT1 + LT2 + 1) * 0.004ms + dec-
imal ((FFF * N) + N + ATICR2 - ATICR1 – 1) * 1ms
where N = No of overflows of 12-bit CNTR1.
LTICR = LT2
ATICRH = ATH2
ATICRL = ATL2
Hence ATICR2 [11:0] = ATH2 & ATL2
Figure 46. Long Range Input Capture Timing Diagram
f
OSC/32
_ _ _
_ _ _
_ _ _
_ _ _
_ _ _
TB Counter1
CNTR1
F9h
00h
LT1
F9h
00h
LT2
_ _ _
_ _ _
ATH1 & ATL1
ATH2 & ATL2
LTIC
00h
0h
LT1
LT2
LTICR
ATH2
ATH1
ATL1
ATICRH
ATICRL
00h
ATL2
ATICR = ATICRH[3:0] & ATICRL[7:0]
66/159
1
ST7LITE1xB
DUAL 12-BIT AUTORELOAD TIMER 4 (Cont’d)
11.2.3.6 One Pulse Mode
– One-pulse mode without active LTIC edge
One Pulse Mode can be used to control PWM2/3
signal with an external LTIC pin. This mode is
available only in dual timer mode i.e. only for
CNTR2, when the OP_EN bit in PWM3CSR regis-
ter is set.
– Normal PWM operation. (Lowest priority)
4. It is possible to synchronize the update of
DCR2/3 registers and OP2/3 bits with the CNTR2
reset. This is managed by the overflow interrupt
which is generated if CNTR2 is reset either due to
an ATR match or an active pulse on the LTIC pin.
One Pulse Mode is activated by the external LTIC
input. The active edge of the LTIC pin is selected
by the OPEDGE bit in the PWM3CSR register.
5. Updating the DCR2/3 registers and OP2/3 bits
in one-pulse mode is done dynamically by soft-
ware using force update (FORCE2 bit in the
ATCSR2 register).
After getting the active edge of the LTIC pin,
CNTR2 is reset (000h) and PWM3 is set to high.
CNTR2 starts counting from 000h, when it reaches
the active DCR3 value then the PWM3 output
goes low. Till this time, any further transitions on
the LTIC signal will have no effect. If there are
LTIC transitions after CNTR2 reaches the DCR3
value, CNTR2 is reset again and the PWM3 output
goes high.
6. DCR3 update in this mode is not synchronized
with any event. Consequently the next PWM3 cy-
cle just after the change may be longer than ex-
pected (refer to Figure 15).
7. In One Pulse Mode the ATR2 value must be
greater than the DCR2/3 value for the PWM2/3
outputs. (contrary to normal PWM mode)
If there is no LTIC active edge then CNTR2 will
count till it reaches the ATR2 value, and then it will
be reset again and the PWM3 output is set to high.
The counter again starts counting from 000h,
when it reaches the active DCR3 value the PWM3
output goes low, the counter counts till it reaches
the ATR2 value, it resets and the PWM3 output is
set to high and it goes on the same way.
8. If there is an active edge on the LTIC pin after
the CNTR2 has reset due to an ATR2 match, then
the timer gets reset again. The duty cycle may be
modified depending on whether the new DCR val-
ue is less than or more than the previous value.
9. The TRAN2 bit must be set simultaneously with
the FORCE2 bit in the same instruction after a
write to the DCR register.
The same operation applies for the PWM2 output,
but in this case the comparison is done on the
DCR2 value.
10. The ATR2 value should be changed after an
overflow in one pulse mode to avoid an irregular
PWM cycle.
The OP_EN and OPEDGE bits take effect on the
fly and are not synchronized with the CNTR2 over-
flow.
11. When exiting from one pulse mode, the
OP_EN bit in the PWM3CSR register must be re-
set first and then the ENCNTR2 bit (if CNTR2 is to
be stopped).
The OP2/3 bits can be used to inverse the polarity
of the PWM2/3 outputs in one-pulse mode. The
update of these bits (OP2/3) is synchronized with
the CNTR2 overflow, they will be updated if the
TRAN2 bit is set.
How to Enter One Pulse Mode:
1. Load the ATR2H/ATR2L registers with required
value.
Notes:
2. Load the DCR3H/DCR3L registers for PWM3
output. The ATR2 value must be greater than
DCR3.
1. If CNTR2 is running at 32 MHz, the time taken
from activation of LTIC input and CNTR2 reset is
between 2 and 3 t
cycles, i.e. 66 ns to 99 ns
CNTR2
3. Set the OP3 bit in the PWM3CSR register if po-
larity change is required.
(with 8 MHz f ).
cpu
2. The Lite Timer input capture interrupt must be
disabled while 12-bit ARTimer is in One Pulse
Mode. This is to avoid spurious interrupts.
4. Start the CNTR2 counter by setting the
ENCNTR2 bit in the ATCSR2 register.
5. Set TRAN2 bit in ATCSR2 to enable transfer.
3. The priority of various events affecting PWM3 is
as follows:
6. Wait for an overflow event by polling the OVF2
flag in the ATCSR2 register.
– Break (Highest priority)
7. Select the counter clock using the CK[1:0] bits in
the ATCSR register.
– One-pulse mode with active LTIC edge
– Forced overflow (by FORCE2 bit)
67/159
1
ST7LITE1xB
DUAL 12-BIT AUTORELOAD TIMER 4 (Cont’d)
8. Set the OP_EN bit in the PWM3CSR register to
enable one-pulse mode.
Follow the same procedure for PWM2 with the bits
corresponding to PWM2.
9. Enable the PWM3 output by setting the OE3 bit
in the PWMCR register.
Note: When break is applied in one-pulse mode,
the CNTR2, DCR2/3 & ATR2 registers are reset.
Consequently, these registers have to be initial-
ized again when break is removed.
The "Wait for Overflow event" in step 6 can be re-
placed by forced update (writing the FORCE2 bit).
Figure 47. Block Diagram of One Pulse Mode
LTIC pin
Edge
Selection
12-bit Upcounter 2
PWM
Generation
OPEDGE OP_EN
PWM2/3
12-bit AutoReload Register 2
12-bit Active DCR2/3
PWM3CSR Register
OP2/3
Figure 48. One Pulse Mode and PWM Timing Diagram
fcounter2
000
DCR2/3
ATR2 000
CNTR2
000
DCR2/3
LTIC
PWM2/3
fcounter2
OVF
ATR2
DCR2/3
OVF
ATR2
DCR2/3
ATR2
OVF
CNTR2
LTIC
PWM2/3
Note 1: When OP_EN=0, LTIC edges are not taken into account as the timer runs in PWM mode.
68/159
1
ST7LITE1xB
Figure 49. Dynamic DCR2/3 update in One Pulse Mode
fcounter2
(DCR3)old
(DCR3)new
000
FFF
000
CNTR2
ATR2 000
LTIC
FORCE2
TRAN2
DCR2/3
(DCR2/3)old
(DCR2/3)new
PWM2/3
extra PWM3 period due to DCR3
update dynamically in one-pulse
mode.
69/159
1
ST7LITE1xB
DUAL 12-BIT AUTORELOAD TIMER 4 (Cont’d)
11.2.3.7 Force Update
set by hardware after the respective counter over-
flow event has occurred.
In order not to wait for the counter overflow to
x
load the value into active DCRx registers, a pro-
This feature can be used at any time. All related
features such as PWM generation, Output Com-
pare, Input Capture, One-pulse (refer to Figure 15.
Dynamic DCR2/3 update in One Pulse Mode) can
be used this way.
grammable counter overflow is provided. For
x
both counters, a separate bit is provided which
when set, make the counters start with the over-
flow value, i.e. FFFh. After overflow, the counters
start counting from their respective auto reload
register values.
These bits are FORCE1 and FORCE2 in the
ATCSR2 register. FORCE1 is used to force an
overflow on Counter 1 and, FORCE2 is used for
Counter 2. These bits are set by software and re-
Figure 50. Force Overflow Timing Diagram
f
CNTRx
FORCEx
CNTRx
FFF
ATRx
E03
E04
FORCE2
FORCE1
ATCSR2 Register
70/159
1
ST7LITE1xB
DUAL 12-BIT AUTORELOAD TIMER 4 (Cont’d)
11.2.4 Low Power Modes
Mode
WAIT
HALT
Description
No effect on AT timer
AT timer halted.
11.2.5 Interrupts
Exit
from
Active-
Halt
Enable
Control from
Bit
Exit
Exit
from
Halt
Interrupt
Event
Event
Flag
Wait
Overflow
Event
OVF1
ICF
OVIE1
ICIE
Yes
No
Yes
AT4 IC Event
CMP Event
Yes
Yes
No
No
No
No
CMPFx CMPIE
Overflow
Event2
OVF2 OVIE2
Yes
No
No
Note: The CMP and AT4 IC events are connected
to the same interrupt vector.
The OVF event is mapped on a separate vector
(see Interrupts chapter).
They generate an interrupt if the enable bit is set in
the ATCSR register and the interrupt mask in the
CC register is reset (RIM instruction).
71/159
1
ST7LITE1xB
DUAL 12-BIT AUTORELOAD TIMER 4 (Cont’d)
11.2.6 Register Description
Bit 1 = OVFIE1 Overflow Interrupt Enable.
This bit is read/write by software and cleared by
hardware after a reset.
TIMER CONTROL STATUS REGISTER
(ATCSR)
Read / Write
Reset Value: 0x00 0000 (x0h)
0: Overflow interrupt disabled.
1: Overflow interrupt enabled.
7
0
Bit 0 = CMPIE Compare Interrupt Enable.
This bit is read/write by software and cleared by
hardware after a reset. It can be used to mask the
interrupt generated when any of the CMPFx bit is
set.
0: Output compare interrupt disabled.
1: Output Compare interrupt enabled.
0
ICF
ICIE
CK1
CK0 OVF1 OVFIE1 CMPIE
Bit 7 = Reserved.
Bit 6 = ICF Input Capture Flag.
This bit is set by hardware and cleared by software
by reading the ATICR register (a read access to
ATICRH or ATICRL will clear this flag). Writing to
this bit does not change the bit value.
0: No input capture
COUNTER REGISTER 1 HIGH (CNTR1H)
Read only
Reset Value: 0000 0000 (00h)
15
8
1: An input capture has occurred
CNTR1_ CNTR1_ CNTR1_ CNTR1_
0
0
0
0
11
10
9
8
Bit 5 = ICIE IC Interrupt Enable.
This bit is set and cleared by software.
0: Input capture interrupt disabled
1: Input capture interrupt enabled
COUNTER REGISTER 1 LOW (CNTR1L)
Read only
Reset Value: 0000 0000 (00h)
Bits 4:3 = CK[1:0] Counter Clock Selection.
These bits are set and cleared by software and
cleared by hardware after a reset. They select the
clock frequency of the counter.
7
0
CNTR1_ CNTR1_ CNTR1_ CNTR1_ CNTR1_ CNTR1_ CNTR1_ CNTR1_
7
6
5
4
3
2
1
0
Counter Clock Selection
CK1 CK0
Bits 15:12 = Reserved.
Bits 11:0 = CNTR1[11:0] Counter Value.
OFF
0
1
0
1
0
1
1
0
32 MHz
This 12-bit register is read by software and cleared
by hardware after a reset. The counter CNTR1 in-
crements continuously as soon as a counter clock
is selected. To obtain the 12-bit value, software
should read the counter value in two consecutive
read operations. As there is no latch, it is recom-
mended to read LSB first. In this case, CNTR1H
can be incremented between the two read opera-
tions and to have an accurate result when
f
(1 ms timebase @ 8 MHz)
LTIMER
f
CPU
Bit 2 = OVF1 Overflow Flag.
This bit is set by hardware and cleared by software
by reading the ATCSR register. It indicates the
transition of the counter1 CNTR1 from FFFh to
ATR1 value.
0: No counter overflow occurred
1: Counter overflow occurred
f
=f
, special care must be taken when
timer CPU
CNTR1L values close to FFh are read.
When a counter overflow occurs, the counter re-
starts from the value specified in the ATR1 regis-
ter.
72/159
1
ST7LITE1xB
DUAL 12-BIT AUTORELOAD TIMER 4 (Cont’d)
AUTORELOAD REGISTER (ATR1H)
Read / Write
PWMx CONTROL STATUS REGISTER
(PWMxCSR)
Reset Value: 0000 0000 (00h)
Read / Write
Reset Value: 0000 0000 (00h)
15
8
7
0
0
0
0
0
ATR11 ATR10 ATR9 ATR8
OPEDG
E
0
0
0
0
OP_EN
OPx CMPFx
AUTORELOAD REGISTER (ATR1L)
Read / Write
Reset Value: 0000 0000 (00h)
Bits 7:4= Reserved, must be kept cleared.
Bit 3 = OP_EN One Pulse Mode Enable
7
0
This bit is read/write by software and cleared by
hardware after a reset. This bit enables the One
Pulse feature for PWM2 and PWM3. (Only availa-
ble for PWM3CSR)
ATR7 ATR6 ATR5 ATR4 ATR3 ATR2 ATR1 ATR0
0: One Pulse mode disabled for PWM2/3.
1: One Pulse mode enabled for PWM2/3.
Bits 11:0 = ATR1[11:0] Autoreload Register 1.
This is a 12-bit register which is written by soft-
ware. The ATR1 register value is automatically
loaded into the upcounter CNTR1 when an over-
flow occurs. The register value is used to set the
PWM frequency.
Bit 2 = OPEDGE One Pulse Edge Selection.
This bit is read/write by software and cleared by
hardware after a reset. This bit selects the polarity
of the LTIC signal for One Pulse feature. This bit
will be effective only if OP_EN bit is set. (Only
available for PWM3CSR)
PWM OUTPUT CONTROL REGISTER
(PWMCR)
Read/Write
Reset Value: 0000 0000 (00h)
0: Falling edge of LTIC is selected.
1: Rising edge of LTIC is selected.
7
0
Bit 1 = OPx PWMx Output Polarity.
This bit is read/write by software and cleared by
hardware after a reset. This bit selects the polarity
of the PWM signal.
0
OE3
0
OE2
0
OE1
0
OE0
0: The PWM signal is not inverted.
1: The PWM signal is inverted.
Bits 7:0 = OE[3:0] PWMx output enable.
These bits are set and cleared by software and
cleared by hardware after a reset.
0: PWM mode disabled. PWMx Output Alternate
Function disabled (I/O pin free for general pur-
pose I/O)
Bit 0 = CMPFx PWMx Compare Flag.
This bit is set by hardware and cleared by software
by reading the PWMxCSR register. It indicates
that the upcounter value matches the Active DCRx
register value.
1: PWM mode enabled
0: Upcounter value does not match DCRx value.
1: Upcounter value matches DCRx value.
73/159
1
ST7LITE1xB
DUAL 12-BIT AUTORELOAD TIMER 4 (Cont’d)
BREAK CONTROL REGISTER (BREAKCR)
Read/Write
Reset Value: 0000 0000 (00h)
PWMx DUTY CYCLE REGISTER HIGH (DCRxH)
Read / Write
Reset Value: 0000 0000 (00h)
7
0
15
8
BRSEL BREDGE BA
BPEN PWM3 PWM2 PWM1 PWM0
0
0
0
0
DCR11 DCR10 DCR9 DCR8
Bit 7 = BRSEL Break Input Selection
This bit is read/write by software and cleared by
hardware after reset. It selects the active Break
signal from external BREAK pin and the output of
the comparator.
Bits 15:12 = Reserved.
PWMx DUTY CYCLE REGISTER LOW (DCRxL)
Read / Write
Reset Value: 0000 0000 (00h)
0: External BREAK pin is selected for break mode.
1: Comparator output is selected for break mode.
7
0
DCR7 DCR6 DCR5 DCR4 DCR3 DCR2 DCR1 DCR0
Bit 6 = BREDGE Break Input Edge Selection
This bit is read/write by software and cleared by
hardware after reset. It selects the active level of
Break signal.
Bits 11:0 = DCRx[11:0] PWMx Duty Cycle Value
This 12-bit value is written by software. It defines
the duty cycle of the corresponding PWM output
signal (see Figure 4).
0: Low level of Break selected as active level.
1: High level of Break selected as active level.
In PWM mode (OEx=1 in the PWMCR register)
the DCR[11:0] bits define the duty cycle of the
PWMx output signal (see Figure 4). In Output
Compare mode, they define the value to be com-
pared with the 12-bit upcounter value.
Bit 5 = BA Break Active.
This bit is read/write by software, cleared by hard-
ware after reset and set by hardware when the ac-
tive level defined by the BREDGE bit is applied on
the BREAK pin. It activates/deactivates the Break
function.
INPUT CAPTURE REGISTER HIGH (ATICRH)
Read only
Reset Value: 0000 0000 (00h)
0: Break not active
1: Break active
15
8
Bit 4 = BPEN Break Pin Enable.
This bit is read/write by software and cleared by
hardware after Reset.
0
0
0
0
ICR11 ICR10 ICR9 ICR8
0: Break pin disabled
Bits 15:12 = Reserved.
1: Break pin enabled
Bits 3:0 = PWM[3:0] Break Pattern.
INPUT CAPTURE REGISTER LOW (ATICRL)
Read only
These bits are read/write by software and cleared
by hardware after a reset. They are used to force
the four PWMx output signals into a stable state
when the Break function is active and correspond-
ing OEx bit is set.
Reset Value: 0000 0000 (00h)
7
0
ICR7 ICR6 ICR5 ICR4 ICR3 ICR2 ICR1 ICR0
74/159
1
ST7LITE1xB
DUAL 12-BIT AUTORELOAD TIMER 4 (Cont’d)
Bits 11:0 = ICR[11:0] Input Capture Data.
ware one CPU clock cycle after counter 2 overflow
has occurred.
This is a 12-bit register which is readable by soft-
ware and cleared by hardware after a reset. The
ATICR register contains captured the value of the
12-bit CNTR1 register when a rising or falling edge
occurs on the ATIC or LTIC pin (depending on
0 : No effect on CNTR2
1 : Loads FFFh in CNTR2
Note: This bit must not be reset by software
ICS). Capture will only be performed when the ICF
flag is cleared.
Bit 6 = FORCE1 Force Counter 1 Overflow
This bit is read/set by software. When set, it loads
FFFh in CNTR1 register. It is reset by hardware
one CPU clock cycle after counter 1 overflow has
occurred.
BREAK ENABLE REGISTER (BREAKEN)
Read/Write
Reset Value: 0000 0011 (03h)
0 : No effect on CNTR1
1 : Loads FFFh in CNTR1
7
0
Note: This bit must not be reset by software
0
0
0
0
0
0
BREN2 BREN1
Bit 5 = ICS Input Capture Shorted
This bit is read/write by software. It allows the AT-
timer CNTR1 to use the LTIC pin for long input
capture.
0 : ATIC for CNTR1 input capture
1 : LTIC for CNTR1 input capture
Bits 7:2 = Reserved, must be kept cleared.
Bit 1 = BREN2 Break Enable for Counter 2
This bit is read/write by software. It enables the
break functionality for Counter2 if BA bit is set in
BREAKCR. It controls PWM2/3 if ENCNTR2 bit is
set.
0: No Break applied for CNTR2
1: Break applied for CNTR2
Bit 4 = OVFIE2 Overflow interrupt 2 enable
This bit is read/write by software and controls the
overflow interrupt of counter2.
0: Overflow interrupt disabled.
1: Overflow interrupt enabled.
Bit 0 = BREN1 Break Enable for Counter 1
This bit is read/write by software. It enables the
break functionality for Counter1. If BA bit is set, it
controls PWM0/1 by default, and controls PWM2/3
also if ENCNTR2 bit is reset.
0: No Break applied for CNTR1
1: Break applied for CNTR1
Bit 3 = OVF2 Overflow Flag.
This bit is set by hardware and cleared by software
by reading the ATCSR2 register. It indicates the
transition of the counter2 from FFFh to ATR2 val-
ue.
0: No counter overflow occurred
1: Counter overflow occurred
TIMER CONTROL REGISTER2 (ATCSR2)
Read/Write
Reset Value: 0000 0011 (03h)
Bit 2 = ENCNTR2 Enable counter2 for PWM2/3
This bit is read/write by software and switches the
PWM2/3 operation to the CNTR2 counter. If this
bit is set, PWM2/3 will be generated using CNTR2.
0: PWM2/3 is generated using CNTR1.
7
0
FORCE FORCE
ENCNT
R2
ICS OVFIE2 OVF2
TRAN2 TRAN1
2
1
1: PWM2/3 is generated using CNTR2.
Bit 7 = FORCE2 Force Counter 2 Overflow
This bit is read/set by software. When set, it loads
FFFh in the CNTR2 register. It is reset by hard-
Note: Counter 2 gets frozen when the ENCNTR2
bit is reset. When ENCNTR2 is set again, the
counter will restart from the last value.
75/159
1
ST7LITE1xB
DUAL 12-BIT AUTORELOAD TIMER 4 (Cont’d)
Bit 1= TRAN2 Transfer enable2
AUTORELOAD REGISTER (ATR2L)
Read / Write
This bit is read/write by software, cleared by hard-
ware after each completed transfer and set by
hardware after reset. It controls the transfers on
CNTR2.
Reset Value: 0000 0000 (00h)
7
0
It allows the value of the Preload DCRx registers
to be transferred to the Active DCRx registers after
the next overflow event.
ATR7 ATR6 ATR5 ATR4 ATR3 ATR2 ATR1 ATR0
The OPx bits are transferred to the shadow OPx
bits in the same way.
Bits 11:0 = ATR2[11:0] Autoreload Register 2.
This is a 12-bit register which is written by soft-
ware. The ATR2 register value is automatically
loaded into the upcounter CNTR2 when an over-
flow of CNTR2 occurs. The register value is used
to set the PWM2/PWM3 frequency when
ENCNTR2 is set.
Notes:
1. DCR2/3 transfer will be controlled using this bit
if ENCNTR2 bit is set.
2. This bit must not be reset by software
Bit 0 = TRAN1 Transfer enable 1
This bit is read/write by software, cleared by hard-
ware after each completed transfer and set by
hardware after reset. It controls the transfers on
CNTR1. It allows the value of the Preload DCRx
registers to be transferred to the Active DCRx reg-
isters after the next overflow event.
DEAD TIME GENERATOR REGISTER (DTGR)
Read/Write
Reset Value: 0000 0000 (00h)
7
0
The OPx bits are transferred to the shadow OPx
bits in the same way.
DTE
DT6
DT5
DT4
DT3
DT2
DT1
DT0
Notes:
1. DCR0,1 transfers are always controlled using
this bit.
Bit 7 = DTE Dead Time Enable
This bit is read/write by software. It enables a dead
time generation on PWM0/PWM1.
0: No Dead time insertion.
2. DCR2/3 transfer will be controlled using this bit
if ENCNTR2 is reset.
1: Dead time insertion enabled.
3.This bit must not be reset by software
Bits 6:0 = DT[6:0] Dead Time Value
AUTORELOAD REGISTER2 (ATR2H)
Read / Write
Reset Value: 0000 0000 (00h)
These bits are read/write by software. They define
the dead time inserted between PWM0/PWM1.
Dead time is calculated as follows:
Dead Time = DT[6:0] x Tcounter1
15
8
Note:
0
0
0
0
ATR11 ATR10 ATR9 ATR8
1. If DTE is set and DT[6:0]=0, PWM output sig-
nals will be at their reset state.
76/159
1
ST7LITE1xB
DUAL 12-BIT AUTORELOAD TIMER 4 (Cont’d)
Table 14. Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
ATCSR
Reset Value
ICF
0
ICIE
0
CK1
0
CK0
0
OVF1
0
OVFIE1
0
CMPIE
0
0D
0E
0F
10
11
12
13
14
15
0
0
CNTR1H
Reset Value
CNTR1_11 CNTR1_10 CNTR1_9 CNTR1_8
0
0
0
0
0
0
0
CNTR1L
Reset Value
CNTR1_7 CNTR1_8 CNTR1_7 CNTR1_6 CNTR1_3 CNTR1_2 CNTR1_1 CNTR1_0
0
0
0
0
0
0
0
0
ATR1H
Reset Value
ATR11
0
ATR10
0
ATR9
0
ATR8
0
0
0
0
0
ATR1L
Reset Value
ATR7
0
ATR6
0
ATR5
0
ATR4
0
ATR3
0
ATR2
0
ATR1
0
ATR0
0
PWMCR
Reset Value
OE3
0
OE2
0
OE1
0
OE0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PWM0CSR
Reset Value
OP0
0
CMPF0
0
0
0
0
0
0
0
0
0
0
PWM1CSR
Reset Value
OP1
0
CMPF1
0
PWM2CSR
Reset Value
OP2
0
CMPF2
0
OP_EN
0
OPEDGE
0
PWM3CSR
Reset Value
OP3
0
CMPF3
0
16
0
0
0
0
0
0
0
0
DCR0H
Reset Value
DCR11
0
DCR10
0
DCR9
0
DCR8
0
17
18
19
1A
1B
1C
1D
1E
1F
20
DCR0L
Reset Value
DCR7
0
DCR6
0
DCR5
0
DCR4
0
DCR3
0
DCR2
0
DCR1
0
DCR0
0
DCR1H
Reset Value
DCR11
0
DCR10
0
DCR9
0
DCR8
0
0
0
0
0
DCR1L
Reset Value
DCR7
0
DCR6
0
DCR5
0
DCR4
0
DCR3
0
DCR2
0
DCR1
0
DCR0
0
DCR2H
Reset Value
DCR11
0
DCR10
0
DCR9
0
DCR8
0
0
0
0
0
DCR2L
Reset Value
DCR7
0
DCR6
0
DCR5
0
DCR4
0
DCR3
0
DCR2
0
DCR1
0
DCR0
0
DCR3H
Reset Value
DCR11
0
DCR10
0
DCR9
0
DCR8
0
0
0
0
0
DCR3L
Reset Value
DCR7
0
DCR6
0
DCR5
0
DCR4
0
DCR3
0
DCR2
0
DCR1
0
DCR0
0
ATICRH
Reset Value
ICR11
0
ICR10
0
ICR9
0
ICR8
0
0
0
0
0
ATICRL
Reset Value
ICR7
0
ICR6
0
ICR5
0
ICR4
0
ICR3
0
ICR2
0
ICR1
0
ICR0
0
77/159
1
ST7LITE1xB
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
FORCE2 FORCE1
ICS
0
OVFIE2
0
OVF2
0
ENCNTR2 TRAN2
TRAN1
1
ATCSR2
Reset Value
21
22
0
0
0
1
BRSEL BREDGE
BREAKCR
Reset Value
BA
0
BPEN
0
PWM3
0
PWM2
0
PWM1
0
PWM0
0
0
0
ATR2H
Reset Value
ATR11
0
ATR10
0
ATR9
0
ATR8
0
23
24
0
0
0
0
ATR2L
Reset Value
ATR7
0
ATR6
0
ATR5
0
ATR4
0
ATR3
0
ATR2
0
ATR1
0
ATR0
0
DTE
0
DT6
0
DT5
0
DT4
0
DT3
0
DT2
0
DT1
0
DT0
0
DTGR
Reset Value
25
26
BREN2
1
BREN1
1
BREAKEN
Reset Value
0
0
0
0
0
0
78/159
1
ST7LITE1xB
11.3 LITE TIMER 2 (LT2)
11.3.1 Introduction
– One 8-bit upcounter with autoreload and pro-
grammable timebase period from 4µs to
The Lite Timer can be used for general-purpose
timing functions. It is based on two free-running 8-
bit upcounters and an 8-bit input capture register.
1.024ms in 4µs increments (@ 8 MHz f
– 2 Maskable timebase interrupts
■ Input Capture
)
OSC
– 8-bit input capture register (LTICR)
– Maskable interrupt with wake-up from Halt
11.3.2 Main Features
■ Realtime Clock
mode capability
– One 8-bit upcounter 1 ms or 2 ms timebase
period (@ 8 MHz f
)
OSC
Figure 51. Lite Timer 2 Block Diagram
f
/32
OSC
LTTB2
LTCNTR
Interrupt request
LTCSR2
8-bit TIMEBASE
COUNTER 2
8
0
0
0
0
0
0
TB2IE TB2F
LTARR
f
LTIMER
To 12-bit AT TImer
8-bit AUTORELOAD
REGISTER
/2
1
0
8-bit TIMEBASE
COUNTER 1
Timebase
1 or 2 ms
(@ 8 MHz
f
LTIMER
f
)
OSC
8
LTICR
8-bit
LTIC
INPUT CAPTURE
REGISTER
LTCSR1
ICIE
ICF
TB
TB1IE TB1F
LTTB1 INTERRUPT REQUEST
LTIC INTERRUPT REQUEST
79/159
1
ST7LITE1xB
LITE TIMER (Cont’d)
11.3.3 Functional Description
11.3.3.1 Timebase Counter 1
terrupt is generated if the ICIE bit is set. The ICF
bit is cleared by reading the LTICR register.
The LTICR is a read-only register and always con-
tains the data from the last input capture. Input
capture is inhibited if the ICF bit is set.
The 8-bit value of Counter 1 cannot be read or
written by software. After an MCU reset, it starts
incrementing from 0 at a frequency of f
/32. An
OSC
overflow event occurs when the counter rolls over
from F9h to 00h. If f = 8 MHz, then the time pe-
11.3.3.3 Timebase Counter 2
OSC
Counter 2 is an 8-bit autoreload upcounter. It can
be read by accessing the LTCNTR register. After
an MCU reset, it increments at a frequency of
riod between two counter overflow events is 1 ms.
This period can be doubled by setting the TB bit in
the LTCSR1 register.
f
/32 starting from the value stored in the
OSC
When Counter 1 overflows, the TB1F bit is set by
hardware and an interrupt request is generated if
the TB1IE bit is set. The TB1F bit is cleared by
software reading the LTCSR1 register.
LTARR register. A counter overflow event occurs
when the counter rolls over from FFh to the
LTARR reload value. Software can write a new
value at any time in the LTARR register, this value
will be automatically loaded in the counter when
the next overflow occurs.
11.3.3.2 Input Capture
The 8-bit input capture register is used to latch the
free-running upcounter (Counter 1) 1 after a rising
or falling edge is detected on the LTIC pin. When
an input capture occurs, the ICF bit is set and the
LTICR register contains the counter 1 value. An in-
When Counter 2 overflows, the TB2F bit in the
LTCSR2 register is set by hardware and an inter-
rupt request is generated if the TB2IE bit is set.
The TB2F bit is cleared by software reading the
LTCSR2 register.
Figure 52. Input Capture Timing Diagram.
4µs
(@ 8 MHz f
)
OSC
f
CPU
f
/32
OSC
CLEARED
BY S/W
READING
LTIC REGISTER
01h
02h
03h
04h
05h
06h
07h
8-bit COUNTER 1
LTIC PIN
ICF FLAG
07h
xxh
04h
LTICR REGISTER
t
80/159
1
ST7LITE1xB
LITE TIMER (Cont’d)
11.3.4 Low Power Modes
reading the LTCSR register. Writing to this bit has
no effect.
Mode
SLOW
WAIT
Description
No effect on Lite timer
(this peripheral is driven directly
0: No Counter 2 overflow
1: A Counter 2 overflow has occurred
by f
/32)
OSC
LITE
TIMER
AUTORELOAD
REGISTER
No effect on Lite timer
(LTARR)
ACTIVE HALT No effect on Lite timer
Read / Write
Reset Value: 0000 0000 (00h)
HALT
Lite timer stops counting
7
0
11.3.5 Interrupts
Exit
AR7
AR6
AR5
AR4
AR3
AR2
AR1
AR0
Enable Exit
Control from
Exit
from
Halt
Interrupt Event
from
Active
Halt
Event
Flag
Bit
Wait
Bits 7:0 = AR[7:0] Counter 2 Reload Value
Timebase 1
Event
These bits register is read/write by software. The
LTARR value is automatically loaded into Counter
2 (LTCNTR) when an overflow occurs.
TB1F TB1IE
TB2F TB2IE
Yes
Timebase 2
Event
Yes
No
No
No
IC Event
ICF
ICIE
LITE TIMER COUNTER 2 (LTCNTR)
Read only
Note: The TBxF and ICF interrupt events are con-
nected to separate interrupt vectors (see Inter-
rupts chapter).
Reset Value: 0000 0000 (00h)
7
0
They generate an interrupt if the enable bit is set in
the LTCSR1 or LTCSR2 register and the interrupt
mask in the CC register is reset (RIM instruction).
CNT7 CNT6 CNT5 CNT4 CNT3 CNT2 CNT1 CNT0
11.3.6 Register Description
Bits 7:0 = CNT[7:0] Counter 2 Reload Value
This register is read by software. The LTARR val-
ue is automatically loaded into Counter 2 (LTCN-
TR) when an overflow occurs.
LITE TIMER CONTROL/STATUS REGISTER 2
(LTCSR2)
Read / Write
Reset Value: 0000 0000 (00h)
7
0
LITE TIMER CONTROL/STATUS REGISTER
(LTCSR1)
0
0
0
0
0
0
TB2IE TB2F
Read / Write
Reset Value: 0x00 0000 (x0h)
Bits 7:2 = Reserved, must be kept cleared.
7
0
-
ICIE
ICF
TB
TB1IE TB1F
-
-
Bit 1 = TB2IE Timebase 2 Interrupt enable
This bit is set and cleared by software.
0: Timebase (TB2) interrupt disabled
1: Timebase (TB2) interrupt enabled
Bit 7 = ICIE Interrupt Enable
This bit is set and cleared by software.
0: Input Capture (IC) interrupt disabled
1: Input Capture (IC) interrupt enabled
Bit 0 = TB2F Timebase 2 Interrupt Flag
This bit is set by hardware and cleared by software
81/159
1
ST7LITE1xB
LITE TIMER (Cont’d)
Bit 6 = ICF Input Capture Flag
This bit is set by hardware and cleared by software
by reading the LTICR register. Writing to this bit
does not change the bit value.
0: No input capture
1: An input capture has occurred
Note: After an MCU reset, software must initialize
the ICF bit by reading the LTICR register
Bit 5 = TB Timebase period selection
This bit is set and cleared by software.
0: Timebase period = t
1: Timebase period = t
MHz)
* 8000 (1ms @ 8 MHz)
* 16000 (2ms @ 8
OSC
OSC
Bit 4 = TB1IE Timebase Interrupt enable
This bit is set and cleared by software.
0: Timebase (TB1) interrupt disabled
1: Timebase (TB1) interrupt enabled
Bit 3 = TB1F Timebase Interrupt Flag
This bit is set by hardware and cleared by software
reading the LTCSR register. Writing to this bit has
no effect.
0: No counter overflow
1: A counter overflow has occurred
Bits 2:0 = Reserved
LITE TIMER INPUT CAPTURE REGISTER
(LTICR)
Read only
Reset Value: 0000 0000 (00h)
7
0
ICR7 ICR6 ICR5 ICR4 ICR3 ICR2 ICR1 ICR0
Bits 7:0 = ICR[7:0] Input Capture Value
These bits are read by software and cleared by
hardware after a reset. If the ICF bit in the LTCSR
is cleared, the value of the 8-bit up-counter will be
captured when a rising or falling edge occurs on
the LTIC pin.
82/159
1
ST7LITE1xB
LITE TIMER (Cont’d)
Table 15. Lite Timer Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
LTCSR2
Reset Value
TB2IE
0
TB2F
0
08
09
0A
0B
0C
0
0
0
0
0
0
LTARR
Reset Value
AR7
0
AR6
0
AR5
0
AR4
0
AR3
0
AR2
0
AR1
0
AR0
0
LTCNTR
Reset Value
CNT7
0
CNT6
0
CNT5
0
CNT4
0
CNT3
0
CNT2
0
CNT1
0
CNT0
0
LTCSR1
Reset Value
ICIE
0
ICF
x
TB
0
TB1IE
0
TB1F
0
0
0
0
LTICR
Reset Value
ICR7
0
ICR6
0
ICR5
0
ICR4
0
ICR3
0
ICR2
0
ICR1
0
ICR0
0
83/159
1
ST7LITE1xB
ON-CHIP PERIPHERALS (cont’d)
11.4 SERIAL PERIPHERAL INTERFACE (SPI)
11.4.1 Introduction
11.4.3 General Description
The Serial Peripheral Interface (SPI) allows full-
duplex, synchronous, serial communication with
external devices. An SPI system may consist of a
master and one or more slaves or a system in
which devices may be either masters or slaves.
Figure 1 on page 3 shows the serial peripheral in-
terface (SPI) block diagram. There are three regis-
ters:
– SPI Control Register (SPICR)
– SPI Control/Status Register (SPICSR)
– SPI Data Register (SPIDR)
11.4.2 Main Features
■ Full duplex synchronous transfers (on three
The SPI is connected to external devices through
four pins:
lines)
■ Simplex synchronous transfers (on two lines)
■ Master or slave operation
– MISO: Master In / Slave Out data
– MOSI: Master Out / Slave In data
■ 6 master mode frequencies (f
/4 max.)
CPU
– SCK: Serial Clock out by SPI masters and in-
put by SPI slaves
■ f
/2 max. slave mode frequency (see note)
CPU
■ SS Management by software or hardware
■ Programmable clock polarity and phase
■ End of transfer interrupt flag
– SS: Slave select:
This input signal acts as a ‘chip select’ to let
the SPI master communicate with slaves indi-
vidually and to avoid contention on the data
lines. Slave SS inputs can be driven by stand-
ard I/O ports on the master Device.
■ Write collision, Master Mode Fault and Overrun
flags
Note: In slave mode, continuous transmission is
not possible at maximum frequency due to the
software overhead for clearing status flags and to
initiate the next transmission sequence.
84/159
1
ST7LITE1xB
SERIAL PERIPHERAL INTERFACE (SPI) (cont’d)
Figure 53. Serial Peripheral Interface Block Diagram
Data/Address Bus
Read
SPIDR
Interrupt
request
Read Buffer
MOSI
7
0
SPICSR
MISO
8-bit Shift Register
SPIF WCOL OVR MODF
0
SOD SSM SSI
Write
SOD
bit
1
SS
SPI
STATE
0
SCK
CONTROL
7
0
SPICR
MSTR
SPR0
SPIE SPE SPR2
CPOL CPHA SPR1
MASTER
CONTROL
SERIAL CLOCK
GENERATOR
SS
85/159
1
ST7LITE1xB
SERIAL PERIPHERAL INTERFACE (cont’d)
11.4.3.1 Functional Description
the MISO pin. This implies full duplex communica-
tion with both data out and data in synchronized
with the same clock signal (which is provided by
the master device via the SCK pin).
A basic example of interconnections between a
single master and a single slave is illustrated in
Figure 2.
To use a single data line, the MISO and MOSI pins
must be connected at each node (in this case only
simplex communication is possible).
The MOSI pins are connected together and the
MISO pins are connected together. In this way
data is transferred serially between master and
slave (most significant bit first).
Four possible data/clock timing relationships may
be chosen (see Figure 5 on page 7) but master
and slave must be programmed with the same tim-
ing mode.
The communication is always initiated by the mas-
ter. When the master device transmits data to a
slave device via MOSI pin, the slave device re-
sponds by sending data to the master device via
Figure 54. Single Master/ Single Slave Application
SLAVE
MASTER
MSBit
LSBit
MSBit
LSBit
MISO
MOSI
MISO
MOSI
8-bit SHIFT REGISTER
8-bit SHIFT REGISTER
SPI
CLOCK
GENERATOR
SCK
SS
SCK
SS
+5V
Not used if SS is managed
by software
86/159
1
ST7LITE1xB
SERIAL PERIPHERAL INTERFACE (cont’d)
11.4.3.2 Slave Select Management
In Slave Mode:
As an alternative to using the SS pin to control the
Slave Select signal, the application can choose to
manage the Slave Select signal by software. This
is configured by the SSM bit in the SPICSR regis-
ter (see Figure 4).
There are two cases depending on the data/clock
timing relationship (see Figure 3):
If CPHA = 1 (data latched on second clock edge):
– SS internal must be held low during the entire
transmission. This implies that in single slave
applications the SS pin either can be tied to
In software management, the external SS pin is
free for other application uses and the internal SS
signal level is driven by writing to the SSI bit in the
SPICSR register.
V
, or made free for standard I/O by manag-
SS
ing the SS function by software (SSM = 1 and
SSI = 0 in the in the SPICSR register)
If CPHA = 0 (data latched on first clock edge):
In Master mode:
– SS internal must be held low during byte
transmission and pulled high between each
byte to allow the slave to write to the shift reg-
ister. If SS is not pulled high, a Write Collision
error will occur when the slave writes to the
shift register (see Section 0.1.5.3).
– SS internal must be held high continuously
Figure 55. Generic SS Timing Diagram
Byte 3
Byte 2
MOSI/MISO
Master SS
Byte 1
Slave SS
(if CPHA = 0)
Slave SS
(if CPHA = 1)
Figure 56. Hardware/Software Slave Select Management
SSM bit
SSI bit
1
0
SS internal
SS external pin
87/159
1
ST7LITE1xB
SERIAL PERIPHERAL INTERFACE (cont’d)
11.4.3.3 Master Mode Operation
Note: While the SPIF bit is set, all writes to the
SPIDR register are inhibited until the SPICSR reg-
ister is read.
In master mode, the serial clock is output on the
SCK pin. The clock frequency, polarity and phase
are configured by software (refer to the description
of the SPICSR register).
11.4.3.5 Slave Mode Operation
In slave mode, the serial clock is received on the
SCK pin from the master device.
Note: The idle state of SCK must correspond to
the polarity selected in the SPICSR register (by
pulling up SCK if CPOL = 1 or pulling down SCK if
CPOL = 0).
To operate the SPI in slave mode:
1. Write to the SPICSR register to perform the fol-
lowing actions:
How to operate the SPI in master mode
– Select the clock polarity and clock phase by
configuring the CPOL and CPHA bits (see
Figure 5).
To operate the SPI in master mode, perform the
following steps in order:
Note: The slave must have the same CPOL
1. Write to the SPICR register:
and CPHA settings as the master.
– Select the clock frequency by configuring the
– Manage the SS pin as described in Section
0.1.3.2 and Figure 3. If CPHA = 1 SS must be
held low continuously. If CPHA = 0 SS must
be held low during byte transmission and
pulled up between each byte to let the slave
write in the shift register.
SPR[2:0] bits.
– Select the clock polarity and clock phase by
configuring the CPOL and CPHA bits. Figure
5 shows the four possible configurations.
Note: The slave must have the same CPOL
and CPHA settings as the master.
2. Write to the SPICR register to clear the MSTR
bit and set the SPE bit to enable the SPI I/O
functions.
2. Write to the SPICSR register:
– Either set the SSM bit and set the SSI bit or
clear the SSM bit and tie the SS pin high for
the complete byte transmit sequence.
11.4.3.6 Slave Mode Transmit Sequence
When software writes to the SPIDR register, the
data byte is loaded into the 8-bit shift register and
then shifted out serially to the MISO pin most sig-
nificant bit first.
3. Write to the SPICR register:
– Set the MSTR and SPE bits
Note: MSTR and SPE bits remain set only if
SS is high).
The transmit sequence begins when the slave de-
vice receives the clock signal and the most signifi-
cant bit of the data on its MOSI pin.
Important note: if the SPICSR register is not writ-
ten first, the SPICR register setting (MSTR bit)
may be not taken into account.
When data transfer is complete:
– The SPIF bit is set by hardware.
The transmit sequence begins when software
writes a byte in the SPIDR register.
11.4.3.4 Master Mode Transmit Sequence
– An interrupt request is generated if SPIE bit is
set and interrupt mask in the CCR register is
cleared.
When software writes to the SPIDR register, the
data byte is loaded into the 8-bit shift register and
then shifted out serially to the MOSI pin most sig-
nificant bit first.
Clearing the SPIF bit is performed by the following
software sequence:
When data transfer is complete:
– The SPIF bit is set by hardware.
1. An access to the SPICSR register while the
SPIF bit is set
2. A write or a read to the SPIDR register
– An interrupt request is generated if the SPIE
bit is set and the interrupt mask in the CCR
register is cleared.
Notes: While the SPIF bit is set, all writes to the
SPIDR register are inhibited until the SPICSR reg-
ister is read.
Clearing the SPIF bit is performed by the following
software sequence:
The SPIF bit can be cleared during a second
transmission; however, it must be cleared before
the second SPIF bit in order to prevent an Overrun
condition (see Section 0.1.5.2).
1. An access to the SPICSR register while the
SPIF bit is set
2. A read to the SPIDR register
88/159
1
ST7LITE1xB
SERIAL PERIPHERAL INTERFACE (cont’d)
11.4.4 Clock Phase and Clock Polarity
Figure 5 shows an SPI transfer with the four com-
binations of the CPHA and CPOL bits. The dia-
gram may be interpreted as a master or slave tim-
ing diagram where the SCK pin, the MISO pin and
the MOSI pin are directly connected between the
master and the slave device.
Four possible timing relationships may be chosen
by software, using the CPOL and CPHA bits (See
Figure 5).
Note: The idle state of SCK must correspond to
the polarity selected in the SPICSR register (by
pulling up SCK if CPOL = 1 or pulling down SCK if
CPOL = 0).
Note: If CPOL is changed at the communication
byte boundaries, the SPI must be disabled by re-
setting the SPE bit.
The combination of the CPOL clock polarity and
CPHA (clock phase) bits selects the data capture
clock edge.
Figure 57. Data Clock Timing Diagram
CPHA = 1
SCK
(CPOL = 1)
SCK
(CPOL = 0)
Bit 4
Bit 4
Bit3
Bit3
Bit 2
Bit 2
Bit 1
Bit 1
LSBit
LSBit
MSBit
MSBit
Bit 6
Bit 6
Bit 5
Bit 5
MISO
(from master)
MOSI
(from slave)
SS
(to slave)
CAPTURE STROBE
CPHA = 0
SCK
(CPOL = 1)
SCK
(CPOL = 0)
Bit 4
Bit 4
Bit3
Bit3
Bit 2
Bit 2
Bit 1
Bit 1
LSBit
LSBit
MISO
(from master)
MSBit
Bit 6
Bit 6
Bit 5
Bit 5
MOSI
(from slave)
MSBit
SS
(to slave)
CAPTURE STROBE
Note: This figure should not be used as a replacement for parametric information.
Refer to the Electrical Characteristics chapter.
89/159
1
ST7LITE1xB
SERIAL PERIPHERAL INTERFACE (cont’d)
11.4.5 Error Flags
11.4.5.2 Overrun Condition (OVR)
11.4.5.1 Master Mode Fault (MODF)
An overrun condition occurs when the master de-
vice has sent a data byte and the slave device has
not cleared the SPIF bit issued from the previously
transmitted byte.
Master mode fault occurs when the master de-
vice’s SS pin is pulled low.
When a Master mode fault occurs:
When an Overrun occurs:
– The MODF bit is set and an SPI interrupt re-
quest is generated if the SPIE bit is set.
– The OVR bit is set and an interrupt request is
generated if the SPIE bit is set.
– The SPE bit is reset. This blocks all output
from the device and disables the SPI periph-
eral.
In this case, the receiver buffer contains the byte
sent after the SPIF bit was last cleared. A read to
the SPIDR register returns this byte. All other
bytes are lost.
– The MSTR bit is reset, thus forcing the device
into slave mode.
The OVR bit is cleared by reading the SPICSR
register.
Clearing the MODF bit is done through a software
sequence:
11.4.5.3 Write Collision Error (WCOL)
1. A read access to the SPICSR register while the
MODF bit is set.
A write collision occurs when the software tries to
write to the SPIDR register while a data transfer is
taking place with an external device. When this
happens, the transfer continues uninterrupted and
the software write will be unsuccessful.
2. A write to the SPICR register.
Notes: To avoid any conflicts in an application
with multiple slaves, the SS pin must be pulled
high during the MODF bit clearing sequence. The
SPE and MSTR bits may be restored to their orig-
inal state during or after this clearing sequence.
Write collisions can occur both in master and slave
mode. See also Section 0.1.3.2 Slave Select Man-
agement.
Hardware does not allow the user to set the SPE
and MSTR bits while the MODF bit is set except in
the MODF bit clearing sequence.
Note: A "read collision" will never occur since the
received data byte is placed in a buffer in which
access is always synchronous with the CPU oper-
ation.
In a slave device, the MODF bit can not be set, but
in a multimaster configuration the device can be in
slave mode with the MODF bit set.
The WCOL bit in the SPICSR register is set if a
write collision occurs.
The MODF bit indicates that there might have
been a multimaster conflict and allows software to
handle this using an interrupt routine and either
perform a reset or return to an application default
state.
No SPI interrupt is generated when the WCOL bit
is set (the WCOL bit is a status flag only).
Clearing the WCOL bit is done through a software
sequence (see Figure 6).
Figure 58. Clearing the WCOL Bit (Write Collision Flag) Software Sequence
Clearing sequence after SPIF = 1 (end of a data byte transfer)
Read SPICSR
1st Step
RESULT
SPIF = 0
WCOL = 0
2nd Step
Read SPIDR
Clearing sequence before SPIF = 1 (during a data byte transfer)
Read SPICSR
1st Step
RESULT
Note: Writing to the SPIDR register in-
stead of reading it does not reset the
WCOL bit.
2nd Step
Read SPIDR
WCOL = 0
90/159
1
ST7LITE1xB
SERIAL PERIPHERAL INTERFACE (cont’d)
11.4.5.4 Single Master and Multimaster
Configurations
For more security, the slave device may respond
to the master with the received data byte. Then the
master will receive the previous byte back from the
slave device if all MISO and MOSI pins are con-
nected and the slave has not written to its SPIDR
register.
There are two types of SPI systems:
– Single Master System
– Multimaster System
Other transmission security methods can use
ports for handshake lines or data bytes with com-
mand fields.
Single Master System
A typical single master system may be configured
using a device as the master and four devices as
slaves (see Figure 7).
Multimaster System
A multimaster system may also be configured by
the user. Transfer of master control could be im-
plemented using a handshake method through the
I/O ports or by an exchange of code messages
through the serial peripheral interface system.
The master device selects the individual slave de-
vices by using four pins of a parallel port to control
the four SS pins of the slave devices.
The SS pins are pulled high during reset since the
master device ports will be forced to be inputs at
that time, thus disabling the slave devices.
The multimaster system is principally handled by
the MSTR bit in the SPICR register and the MODF
bit in the SPICSR register.
Note: To prevent a bus conflict on the MISO line,
the master allows only one active slave device
during a transmission.
Figure 59. Single Master / Multiple Slave Configuration
SS
SS
SS
SS
SCK
Slave
SCK
Slave
Device
SCK
Slave
Device
SCK
Slave
Device
Device
MOSI MISO
MOSI MISO
MOSI MISO
MOSI MISO
MOSI MISO
SCK
Master
Device
5V
SS
91/159
1
ST7LITE1xB
SERIAL PERIPHERAL INTERFACE (cont’d)
11.4.6 Low Power Modes
the SPI from HALT mode state to normal state. If
the SPI exits from Slave mode, it returns to normal
state immediately.
Mode
Description
No effect on SPI.
Caution: The SPI can wake up the device from
HALT mode only if the Slave Select signal (exter-
nal SS pin or the SSI bit in the SPICSR register) is
low when the device enters HALT mode. So, if
Slave selection is configured as external (see Sec-
tion 0.1.3.2), make sure the master drives a low
level on the SS pin when the slave enters HALT
mode.
WAIT
SPI interrupt events cause the device to exit
from WAIT mode.
SPI registers are frozen.
In HALT mode, the SPI is inactive. SPI oper-
ation resumes when the device is woken up
by an interrupt with “exit from HALT mode”
capability. The data received is subsequently
read from the SPIDR register when the soft-
ware is running (interrupt vector fetching). If
several data are received before the wake-
up event, then an overrun error is generated.
This error can be detected after the fetch of
the interrupt routine that woke up the Device.
HALT
11.4.7 Interrupts
Enable
Control from
Bit
Exit
Exit
from
Halt
Event
Flag
Interrupt Event
Wait
SPI End of
Transfer Event
SPIF
Yes
11.4.6.1 Using the SPI to wake up the device
from Halt mode
Master Mode
Fault Event
SPIE
Yes
MODF
OVR
No
In slave configuration, the SPI is able to wake up
the device from HALT mode through a SPIF inter-
rupt. The data received is subsequently read from
the SPIDR register when the software is running
(interrupt vector fetch). If multiple data transfers
have been performed before software clears the
SPIF bit, then the OVR bit is set by hardware.
Overrun Error
Note: The SPI interrupt events are connected to
the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding
Enable Control Bit is set and the interrupt mask in
the CC register is reset (RIM instruction).
Note: When waking up from HALT mode, if the
SPI remains in Slave mode, it is recommended to
perform an extra communications cycle to bring
92/159
1
ST7LITE1xB
11.4.8 Register Description
SPI CONTROL REGISTER (SPICR)
Read/Write
Bit 3 = CPOL Clock Polarity
This bit is set and cleared by software. This bit de-
termines the idle state of the serial Clock. The
CPOL bit affects both the master and slave
modes.
Reset Value: 0000 xxxx (0xh)
7
0
0: SCK pin has a low level idle state
1: SCK pin has a high level idle state
SPIE
SPE SPR2 MSTR CPOL CPHA SPR1 SPR0
Note: If CPOL is changed at the communication
byte boundaries, the SPI must be disabled by re-
setting the SPE bit.
Bit 7 = SPIE Serial Peripheral Interrupt Enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SPI interrupt is generated whenever an End
of Transfer event, Master Mode Fault or Over-
run error occurs (SPIF = 1, MODF = 1 or
OVR = 1 in the SPICSR register)
Bit 2 = CPHA Clock Phase
This bit is set and cleared by software.
0: The first clock transition is the first data capture
edge.
1: The second clock transition is the first capture
edge.
Bit 6 = SPE Serial Peripheral Output Enable
This bit is set and cleared by software. It is also
cleared by hardware when, in master mode,
SS = 0 (see Section 0.1.5.1 Master Mode Fault
(MODF)). The SPE bit is cleared by reset, so the
SPI peripheral is not initially connected to the ex-
ternal pins.
Note: The slave must have the same CPOL and
CPHA settings as the master.
Bits 1:0 = SPR[1:0] Serial Clock Frequency
These bits are set and cleared by software. Used
with the SPR2 bit, they select the baud rate of the
SPI serial clock SCK output by the SPI in master
mode.
0: I/O pins free for general purpose I/O
1: SPI I/O pin alternate functions enabled
Note: These 2 bits have no effect in slave mode.
Bit 5 = SPR2 Divider Enable
Table 16. SPI Master Mode SCK Frequency
This bit is set and cleared by software and is
cleared by reset. It is used with the SPR[1:0] bits to
set the baud rate. Refer to Table 1 SPI Master
Mode SCK Frequency.
Serial Clock
SPR2
SPR1
SPR0
f
f
/4
/8
1
CPU
CPU
0
1
0
1
0
0: Divider by 2 enabled
1: Divider by 2 disabled
0
1
0
f
f
f
/16
/32
/64
CPU
CPU
CPU
Note: This bit has no effect in slave mode.
1
f
/128
CPU
Bit 4 = MSTR Master Mode
This bit is set and cleared by software. It is also
cleared by hardware when, in master mode,
SS = 0 (see Section 0.1.5.1 Master Mode Fault
(MODF)).
0: Slave mode
1: Master mode. The function of the SCK pin
changes from an input to an output and the func-
tions of the MISO and MOSI pins are reversed.
93/159
1
ST7LITE1xB
SERIAL PERIPHERAL INTERFACE (cont’d)
SPI CONTROL/STATUS REGISTER (SPICSR)
Read/Write (some bits Read Only)
Reset Value: 0000 0000 (00h)
Bit 2 = SOD SPI Output Disable
This bit is set and cleared by software. When set, it
disables the alternate function of the SPI output
(MOSI in master mode / MISO in slave mode)
0: SPI output enabled (if SPE = 1)
7
0
SPIF WCOL OVR MODF
-
SOD
SSM
SSI
1: SPI output disabled
Bit 7 = SPIF Serial Peripheral Data Transfer Flag
(Read only)
Bit 1 = SSM SS Management
This bit is set and cleared by software. When set, it
disables the alternate function of the SPI SS pin
and uses the SSI bit value instead. See Section
0.1.3.2 Slave Select Management.
This bit is set by hardware when a transfer has
been completed. An interrupt is generated if
SPIE = 1 in the SPICR register. It is cleared by
a software sequence (an access to the SPICSR
register followed by a write or a read to the
SPIDR register).
0: Hardware management (SS managed by exter-
nal pin)
1: Software management (internal SS signal con-
trolled by SSI bit. External SS pin free for gener-
al-purpose I/O)
0: Data transfer is in progress or the flag has been
cleared.
1: Data transfer between the device and an exter-
nal device has been completed.
Bit 0 = SSI SS Internal Mode
Note: While the SPIF bit is set, all writes to the
SPIDR register are inhibited until the SPICSR reg-
ister is read.
This bit is set and cleared by software. It acts as a
‘chip select’ by controlling the level of the SS slave
select signal when the SSM bit is set.
0: Slave selected
Bit 6 = WCOL Write Collision status (Read only)
This bit is set by hardware when a write to the
SPIDR register is done during a transmit se-
quence. It is cleared by a software sequence (see
Figure 6).
0: No write collision occurred
1: A write collision has been detected
1: Slave deselected
SPI DATA I/O REGISTER (SPIDR)
Read/Write
Reset Value: Undefined
7
0
D7
D6
D5
D4
D3
D2
D1
D0
Bit 5 = OVR SPI Overrun error (Read only)
This bit is set by hardware when the byte currently
being received in the shift register is ready to be
transferred into the SPIDR register while SPIF = 1
(See Section 0.1.5.2). An interrupt is generated if
SPIE = 1 in the SPICR register. The OVR bit is
cleared by software reading the SPICSR register.
0: No overrun error
The SPIDR register is used to transmit and receive
data on the serial bus. In a master device, a write
to this register will initiate transmission/reception
of another byte.
Notes: During the last clock cycle the SPIF bit is
set, a copy of the received data byte in the shift
register is moved to a buffer. When the user reads
the serial peripheral data I/O register, the buffer is
actually being read.
1: Overrun error detected
Bit 4 = MODF Mode Fault flag (Read only)
This bit is set by hardware when the SS pin is
pulled low in master mode (see Section 0.1.5.1
Master Mode Fault (MODF)). An SPI interrupt can
be generated if SPIE = 1 in the SPICR register.
This bit is cleared by a software sequence (An ac-
cess to the SPICSR register while MODF = 1 fol-
lowed by a write to the SPICR register).
While the SPIF bit is set, all writes to the SPIDR
register are inhibited until the SPICSR register is
read.
Warning: A write to the SPIDR register places
data directly into the shift register for transmission.
A read to the SPIDR register returns the value lo-
cated in the buffer and not the content of the shift
register (see Figure 1).
0: No master mode fault detected
1: A fault in master mode has been detected
Bit 3 = Reserved, must be kept cleared.
94/159
1
ST7LITE1xB
SERIAL PERIPHERAL INTERFACE (Cont’d)
Table 17. SPI Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
SPIDR
Reset Value
MSB
x
LSB
x
0031h
0032h
0033h
x
x
x
x
x
x
SPICR
Reset Value
SPIE
0
SPE
0
SPR2
0
MSTR
0
CPOL
x
CPHA
x
SPR1
x
SPR0
x
SPICSR
Reset Value
SPIF
0
WCOL
0
OVR
0
MODF
0
SOD
0
SSM
0
SSI
0
0
95/159
1
ST7LITE1xB
11.5 10-BIT A/D CONVERTER (ADC)
11.5.1 Introduction
■ Data register (DR) which contains the results
■ Conversion complete status flag
■ On/off bit (to reduce consumption)
The block diagram is shown in Figure 60.
The on-chip Analog to Digital Converter (ADC) pe-
ripheral is a 10-bit, successive approximation con-
verter with internal sample and hold circuitry. This
peripheral has up to 7 multiplexed analog input
channels (refer to device pin out description) that
allow the peripheral to convert the analog voltage
levels from up to 7 different sources.
11.5.3 Functional Description
11.5.3.1 Analog Power Supply
V
and V
are the high and low level refer-
SSA
DDA
The result of the conversion is stored in a 10-bit
Data Register. The A/D converter is controlled
through a Control/Status Register.
ence voltage pins. In some devices (refer to device
pin out description) they are internally connected
to the V and V pins.
DD
SS
11.5.2 Main Features
■ 10-bit conversion
■ Up to 7 channels with multiplexed input
■ Linear successive approximation
Conversion accuracy may therefore be impacted
by voltage drops and noise in the event of heavily
loaded or badly decoupled power supply lines.
Figure 60. ADC Block Diagram
DIV 4
1
f
f
ADC
CPU
DIV 2
0
1
0
SLOW
bit
0
EOC SPEEDADON
0
CH2 CH1 CH0
ADCCSR
3
AIN0
AIN1
HOLD CONTROL
R
ADC
ANALOG TO DIGITAL
CONVERTER
x 1 or
ANALOG
MUX
x 8
AIN6
C
ADC
AMPSEL
bit
ADCDRH
D9 D8 D7 D6 D5 D4
D3
D2
AMP
AMP
ADCDRL
0
0
0
SLOW
D1
D0
CAL
SEL
96/159
1
ST7LITE1xB
10-BIT A/D CONVERTER (ADC) (Cont’d)
11.5.3.2 Input Voltage Amplifier
ADC Conversion mode
The input voltage can be amplified by a factor of 8
by enabling the AMPSEL bit in the ADCDRL regis-
ter.
In the ADCCSR register:
Set the ADON bit to enable the A/D converter and
to start the conversion. From this time on, the ADC
performs a continuous conversion of the selected
channel.
When the amplifier is enabled, the input range is
0V to V /8.
DD
For example, if V = 5V, then the ADC can con-
When a conversion is complete:
DD
vert voltages in the range 0V to 430mV with an
ideal resolution of 0.6mV (equivalent to 13-bit res-
– The EOC bit is set by hardware.
– The result is in the ADCDR registers.
A read to the ADCDRH or a write to any bit of the
ADCCSR register resets the EOC bit.
olution with reference to a V to V range).
SS
DD
For more details, refer to the Electrical character-
istics section.
To read the 10 bits, perform the following steps:
1. Poll the EOC bit
Note: The amplifier is switched on by the ADON
bit in the ADCCSR register, so no additional start-
up time is required when the amplifier is selected
by the AMPSEL bit.
2. Read ADCDRL
3. Read ADCDRH. This clears EOC automati-
cally.
11.5.3.3 Digital A/D Conversion Result
The conversion is monotonic, meaning that the re-
sult never decreases if the analog input does not
and never increases if the analog input does not.
To read only 8 bits, perform the following steps:
1. Poll EOC bit
2. Read ADCDRH. This clears EOC automati-
cally.
If the input voltage (V ) is greater than V
AIN
DDA
(high-level voltage reference) then the conversion
result is FFh in the ADCDRH register and 03h in
the ADCDRL register (without overflow indication).
11.5.3.5 Changing the conversion channel
The application can change channels during con-
version.
If the input voltage (V ) is lower than V
level voltage reference) then the conversion result
in the ADCDRH and ADCDRL registers is 00 00h.
(low-
AIN
SSA
When software modifies the CH[2:0] bits in the
ADCCSR register, the current conversion is
stopped, the EOC bit is cleared, and the A/D con-
verter starts converting the newly selected chan-
nel.
The A/D converter is linear and the digital result of
the conversion is stored in the ADCDRH and AD-
CDRL registers. The accuracy of the conversion is
described in the Electrical Characteristics Section.
R
is the maximum recommended impedance
11.5.4 Low Power Modes
AIN
for an analog input signal. If the impedance is too
high, this will result in a loss of accuracy due to
leakage and sampling not being completed in the
alloted time.
Note: The A/D converter may be disabled by re-
setting the ADON bit. This feature allows reduced
power consumption when no conversion is need-
ed and between single shot conversions.
11.5.3.4 A/D Conversion
Mode
Description
The analog input ports must be configured as in-
put, no pull-up, no interrupt. Refer to the «I/O
ports» chapter. Using these pins as analog inputs
does not affect the ability of the port to be read as
a logic input.
WAIT
No effect on A/D Converter
A/D Converter disabled.
After wakeup from Halt mode, the A/D Con-
verter requires a stabilization time t
HALT
(see
STAB
Electrical Characteristics) before accurate
conversions can be performed.
In the ADCCSR register:
– Select the CH[2:0] bits to assign the analog
channel to convert.
11.5.5 Interrupts
None.
97/159
1
ST7LITE1xB
10-BIT A/D CONVERTER (ADC) (Cont’d)
11.5.6 Register Description
CONTROL/STATUS REGISTER (ADCCSR)
Read/Write (Except bit 7 read only)
Reset Value: 0000 0000 (00h)
DATA REGISTER HIGH (ADCDRH)
Read Only
Reset Value: xxxx xxxx (xxh)
7
0
7
0
EOC SPEED ADON
0
0
CH2
CH1
CH0
D9
D8
D7
D6
D5
D4
D3
D2
Bit 7 = EOC End of Conversion
This bit is set by hardware. It is cleared by hard-
ware when software reads the ADCDRH register
or writes to any bit of the ADCCSR register.
0: Conversion is not complete
Bits 7:0 = D[9:2] MSB of Analog Converted Value
AMP CONTROL/DATA REGISTER LOW (AD-
CDRL)
1: Conversion complete
Read/Write
Reset Value: 0000 00xx (0xh)
Bit 6 = SPEED ADC clock selection
This bit is set and cleared by software. It is used
together with the SLOW bit to configure the ADC
clock speed. Refer to the table in the SLOW bit de-
scription (ADCDRL register).
7
0
0
AMP
CAL
AMP-
SEL
0
0
SLOW
D1
D0
Bits 7:5 = Reserved. Forced by hardware to 0.
Bit 5 = ADON A/D Converter on
This bit is set and cleared by software.
0: A/D converter and amplifier are switched off
1: A/D converter and amplifier are switched on
Bit 4 = AMPCAL Amplifier Calibration Bit
This bit is set and cleared by software. It is advised
to use this bit to calibrate the ADC when amplifier
is ON. Setting this bit internally connects amplifier
input to 0V. Hence, corresponding ADC output can
be used in software to eliminate amplifier-offset er-
ror.
0: Calibration off
1: Calibration on. (The input voltage of the amplifi-
er is set to 0V)
Bits 4:3 = Reserved. Must be kept cleared.
Bits 2:0 = CH[2:0] Channel Selection
These bits are set and cleared by software. They
select the analog input to convert.
Channel Pin*
CH2 CH1 CH0
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
Bit 3 = SLOW Slow mode
This bit is set and cleared by software. It is used
together with the SPEED bit in the ADCCSR regis-
ter to configure the ADC clock speed as shown on
the table below.
f
SLOW SPEED
ADC
f
/2
0
0
1
0
1
x
*The number of channels is device dependent. Refer to
the device pinout description.
CPU
f
CPU
f
/4
CPU
Note: max f
allowed = 4MHz (see section
ADC
13.11 on page 139)
98/159
1
ST7LITE1xB
10-BIT A/D CONVERTER (ADC) (Cont’d)
Bit 2 = AMPSEL Amplifier Selection Bit
This bit is set and cleared by software.
0: Amplifier is not selected
1: Amplifier is selected
Note: When AMPSEL=1 it is mandatory that f
be less than or equal to 2 MHz.
ADC
Bits 1:0 = D[1:0] LSB of Analog Converted Value
Table 18. ADC Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
ADCCSR
Reset Value
EOC
0
SPEED
0
ADON
0
0
0
0
0
CH2
0
CH1
0
CH0
0
0034h
0035h
0036h
ADCDRH
Reset Value
D9
x
D8
x
D7
x
D6
x
D5
x
D4
x
D3
x
D2
x
ADCDRL
Reset Value
0
0
0
0
0
0
AMPCAL SLOW AMPSEL
D1
x
D0
x
0
0
0
99/159
ST7LITE1xB
11.6 ANALOG COMPARATOR (CMP)
11.6.1 Introduction
The internal voltage reference module can pro-
vide 16 distinct internally generated voltage lev-
els from 3.2V to 0.2V each at a step of 0.2V on
comparator pin VN. The voltage is selected
through the VR[3:0] bits in the VREFCR regis-
ter.
The CMP block consists of an analog comparator
and an internal voltage reference. The voltage ref-
erence can be external or internal, selectable un-
der program control. The comparator input pins
COMPIN+ and COMPIN- are also connected to
the A/D converter (ADC).
3) External Reference Voltage
If a reference voltage other than that generated
by the internal voltage reference module is
required, COMPIN- can be connected to an
external voltage source. This configuration can
be selected by setting the VCEXT bit in the
VREFCR register.
11.6.2 Main Features
11.6.2.1 On-chip Analog Comparator
The analog comparator compares the voltage at
two input pins COMPIN+ and COMPIN- which are
connected to VP and VN at the comparator input.
When the analog input at COMPIN+ is less than
the analog input at COMPIN-, the output of the
comparator is 0. When the analog input at
COMPIN+ is greater than the analog input at
COMPIN-, the output of the comparator is 1.
11.6.3 Functional Description
To make an analog comparison, the CMPON bit in
the CMPCR register must be set to power-on the
comparator and internal voltage reference mod-
ule.
The result of the comparison as 0 or 1 at COM-
POUT is shown in Figure 62 on page 101.
The VP comparator input is mapped on PB0 and is
also connected to ADC channel 0.
Note:
The VN comparator input is mapped on PB4 for
external voltage input, and is also connected to
ADC channel 4.
To obtain a stable result, the comparator requires
a stabilization time of 500ns. Please refer to sec-
tion 13.12 on page 143.
The internal voltage reference can provide a range
of different voltages to the comparator VN input,
selected by several bits in the VREFCR register,
as described in Table 20.
Table 19. Comparison Result
CINV
Input Conditions
VP > VN
COMPOUT
1
0
0
1
To select pins PB0 and PB4 for A/D conversion,
(default reset state), channel 0 or 4 must be select-
ed through the channel selection bits in the ADCC-
SR register (refer to Section 11.5.6)
0
VN > VP
VP > VN
1
VN > VP
The comparator output is connected to pin PA7
when the COUT bit in the CMPCR register is set.
11.6.2.2
Programmable
External/Internal
Voltage Reference
The comparator output is also connected internally
to the break function of the 12-bit Autoreload Tim-
er (refer to Section 11.2)
The voltage reference module can be configured
to connect the comparator pin COMPIN- to one of
the following:
When the Comparator is OFF, the output value of
comparator is ‘1’.
-
-
-
Fixed internal voltage bandgap
Programmable internal reference voltage
External voltage reference
Important note: To avoid spurious toggling of the
output of the comparator due to noise on the volt-
age reference, it is recommended to enable the
hysteresis through the CHYST bit in the CMPCR
register.
1) Fixed Internal Voltage Bandgap
The voltage reference module can generate a
fixed voltage reference of 1.2V on the VN input.
This is done by setting the VCBGR bit in the
VREFCR register.
2) Programmable Internal Voltage Reference
100/159
ST7LITE1xB
ANALOG COMPARATOR (Cont’d)
Figure 61. Analog Comparator and Internal Voltage Reference
ADC channel 0
COMPIN+
(PB0)
Comparator
COMP
+
-
Voltage Reference
VP
VN
1.2V Bandgap
COMPIN-
(PB4)
Break input
to 12-bit AutoreloadTimer
4
VR[3:0] bits
VCBGR bit
VCEXT bit
ADC Channel 4
Figure 62. Analog Comparator
Comparator
+
COMP
COMPOUT
Port PA7
-
CINV
Rising Edge
Falling Edge
0
1
CHYST
0
CINV CMPIF CMPIE CMP COUT CMPON
CMPCR
Comparator Interrupt
101/159
ST7LITE1xB
ANALOG COMPARATOR (Cont’d)
11.6.4 Register Description
Internal Voltage Reference Register (VREFCR)
Read/Write
VCEXT VCBGR VR3 VR2 VR1 VR0
VN Voltage
bit
0
bit
0
bit bit bit bit
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
1
0
0
1
0
1
0
1
0
1.2V
1V
0
0
Reset Value : 0000 0000 (00h)
0
0
0.8V
0.6V
0.4V
0.2V
0
0
7
0
0
0
0
0
0
VCEXT VCBGR VR3
VR2
VR1
VR0
0
Bits 1:0 = Reserved, Must be kept cleared.
Bit 7 = VCEXT External Voltage Reference for
Comparator
This bit is set or cleared by software. It is used to
connect the external reference voltage to the VN
comparator input.
Comparator Control Register (CMPCR)
Read/Write
Reset Value : 1000 0000 (80h)
0: External reference voltage not connected to VN
1: External reference voltage connected to VN
7
0
CHY-
ST
0
CINV CMPIF CMPIE CMP COUT CMPON
Bit 6 = VCBGR Bandgap Voltage for Comparator
This bit is set or cleared by software. It is used to
connect the bandgap voltage of 1.2V to the VN
comparator input.
0: Bandgap voltage not connected to VN
1: Bandgap voltage connected to VN
Bit 7= CHYST Comparator Hysteresis Enable
This bit is set or cleared by software and set by
hardware reset. When this bit is set, the compara-
tor hysteresis is enabled.
0: Hysteresis disabled
1: Hysteresis enabled
Note: To avoid spurious toggling of the output of
the comparator due to noise on the voltage refer-
ence, it is recommended to enable the hysteresis.
Bits 5:2 = VR[3:0] Programmable Internal Voltage
Reference Range Selection
These bits are set or cleared by software. They are
used to select one of 16 different voltages availa-
ble from the internal voltage reference module and
connect it to comparator input VN.
Bit 6 = Reserved, Must be kept cleared
Refer to Table 20.
Bit 5 = CINV Comparator Output Inversion Select
Table 20. Voltage Reference Programming
This bit is set or cleared by software and cleared
by hardware reset. When this bit is set, the compa-
rator output is inverted.
VCEXT VCBGR VR3 VR2 VR1 VR0
VN Voltage
bit
1
0
0
0
0
0
0
0
0
0
0
0
bit
x
bit bit bit bit
If interrupt enable bit CMPIE is set in the CMPCR
register, the CINV bit is also used to select which
type of level transition on the comparator output
will generate the interrupt. When this bit is reset,
interrupt will be generated at the rising edge of the
comparator output change (COMP signal, refer to
Figure 62 on page 101). When this bit is set, inter-
rupt will be generated at the falling edge of compa-
rator output change (COMP signal, refer to Figure
62 on page 101).
0: Comparator output not inverted and interrupt
generated at the rising edge of COMP
1: Comparator output inverted and interrupt gener-
ated at the falling edge of COMP
x
x
1
1
1
1
1
1
1
1
0
0
x
x
1
1
1
1
0
0
0
0
1
1
x
x
1
1
0
0
1
1
0
0
1
1
x
x
1
0
1
0
1
0
1
0
1
0
VEXT
1.2 bandgap
3.2V
1
0
0
0
0
0
0
0
0
0
0
3V
2.8V
2.6V
2.4V
2.2V
2V
1.8V
1.6V
1.4V
102/159
ST7LITE1xB
ANALOG COMPARATOR (Cont’d)
Bit 4 = CMPIF Comparator Interrupt Flag
This bit is set by hardware when interrupt is gener-
ated at the rising edge (CINV = 0) or falling edge
(CINV = 1) of comparator output. This bit is
cleared by reading the CMPCR register. Writing to
this bit does not change the value.
Bit 1 = COUT Comparator Output Enable on Port
This bit is set or cleared by software. When this bit
is set, the comparator output is available on PA7
port.
0 : Comparator output not connected to PA7
1 : Comparator output connected to PA7
0 : Comparator interrupt flag cleared
1 : Comparator interrupt flag set and can generate
interrupt if CMPIE is set.
Bit 0 : CMPON Comparator ON/OFF
This bit is set or cleared by software and reset by
hardware reset. This bit is used to switch ON/OFF
the comparator, internal voltage reference and
current bias which provides 4µA current to both.
0: Comparator, Internal Voltage Reference, Bias
OFF (in power-down state).
Bit 3 : CMPIE Comparator Interrupt Enable
This bit is set or reset by software and cleared by
hardware reset. This bit enables or disables the in-
terrupt generation depending on interrupt flag
0: Interrupt not generated
1: Comparator, Internal Voltage Reference, Bias
ON
1: Interrupt generated if interrupt flag is set
Note:
Note: For the comparator interrupt generation, it
takes 250ns delay from comparator output change
to rising or falling edge of interrupt generated.
This bit should be set to enable interrupt only after
the comparator has been switched ON, i.e. when
CMPON is set.
Once CMPON bit is set, it is recommended to wait
the specified stabilization time before setting
CMPIE bit in order to avoid a spurious interrupt
(see section 13.12 on page 143).
Bit 2 : CMP Comparator Output
This bit is set or reset by software and cleared by
hardware reset. It stores the value of comparator
output.
Table 21. Analog Comparator Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
VREFCR
VR2
0
VR1
0
-
VCEXT
0
VCBGR
0
VR3
0
VR0
0
-
0
002Ch
002Dh
Reset Value
0
CMPCR
-
CINV
0
CMPIF
0
CMPIE
0
CMP
0
COUT
0
CMPON
0
CHYST
1
Reset value
0
103/159
ST7LITE1xB
12 INSTRUCTION SET
12.1 ST7 ADDRESSING MODES
The ST7 Instruction set is designed to minimize
the number of bytes required per instruction: To do
so, most of the addressing modes may be subdi-
vided in two submodes called long and short:
The ST7 Core features 17 different addressing
modes which can be classified in seven main
groups:
– Long addressing mode is more powerful be-
cause it can use the full 64 Kbyte address space,
however it uses more bytes and more CPU cy-
cles.
Addressing Mode
Inherent
Example
nop
Immediate
Direct
ld A,#$55
ld A,$55
– Short addressing mode is less powerful because
it can generally only access page zero (0000h -
00FFh range), but the instruction size is more
compact, and faster. All memory to memory in-
structions use short addressing modes only
(CLR, CPL, NEG, BSET, BRES, BTJT, BTJF,
INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP)
Indexed
Indirect
ld A,($55,X)
ld A,([$55],X)
jrne loop
Relative
Bit operation
bset byte,#5
The ST7 Assembler optimizes the use of long and
short addressing modes.
Table 22. ST7 Addressing Mode Overview
Pointer
Address
(Hex.)
Pointer
Size
(Hex.)
Destination/
Source
Length
(Bytes)
Mode
Syntax
Inherent
Immediate
Short
nop
+ 0
+ 1
+ 1
+ 2
ld A,#$55
ld A,$10
Direct
Direct
00..FF
Long
ld A,$1000
0000..FFFF
+ 0 (with X register)
+ 1 (with Y register)
No Offset
Direct
Indexed
ld A,(X)
00..FF
Short
Long
Short
Long
Short
Long
Relative
Relative
Bit
Direct
Indexed
Indexed
ld A,($10,X)
ld A,($1000,X)
ld A,[$10]
00..1FE
+ 1
+ 2
+ 2
+ 2
+ 2
+ 2
+ 1
+ 2
+ 1
+ 2
+ 2
+ 3
Direct
0000..FFFF
00..FF
Indirect
Indirect
00..FF
00..FF
00..FF
00..FF
byte
word
byte
word
ld A,[$10.w]
ld A,([$10],X)
0000..FFFF
00..1FE
Indirect Indexed
Indirect Indexed
Direct
ld A,([$10.w],X) 0000..FFFF
1)
1)
jrne loop
PC-128/PC+127
Indirect
jrne [$10]
PC-128/PC+127
00..FF
00..FF
00..FF
00..FF
byte
byte
byte
Direct
bset $10,#7
bset [$10],#7
Bit
Indirect
00..FF
Bit
Direct
Relative btjt $10,#7,skip 00..FF
Bit
Indirect Relative btjt [$10],#7,skip 00..FF
Note:
1. At the time the instruction is executed, the Program Counter (PC) points to the instruction following JRxx.
104/159
ST7LITE1xB
ST7 ADDRESSING MODES (cont’d)
12.1.1 Inherent
12.1.3 Direct
All Inherent instructions consist of a single byte.
The opcode fully specifies all the required informa-
tion for the CPU to process the operation.
In Direct instructions, the operands are referenced
by their memory address.
The direct addressing mode consists of two sub-
modes:
Inherent Instruction
Function
No operation
Direct (Short)
NOP
The address is a byte, thus requires only 1 byte af-
ter the opcode, but only allows 00 - FF addressing
space.
TRAP
S/W Interrupt
Wait For Interrupt (Low Power
Mode)
WFI
Direct (Long)
Halt Oscillator (Lowest Power
Mode)
HALT
The address is a word, thus allowing 64 Kbyte ad-
dressing space, but requires 2 bytes after the op-
code.
RET
Subroutine Return
Interrupt Subroutine Return
Set Interrupt Mask
Reset Interrupt Mask
Set Carry Flag
IRET
12.1.4 Indexed (No Offset, Short, Long)
SIM
In this mode, the operand is referenced by its
memory address, which is defined by the unsigned
addition of an index register (X or Y) with an offset.
RIM
SCF
The indirect addressing mode consists of three
submodes:
RCF
Reset Carry Flag
Reset Stack Pointer
Load
RSP
Indexed (No Offset)
LD
There is no offset (no extra byte after the opcode),
and allows 00 - FF addressing space.
CLR
Clear
PUSH/POP
INC/DEC
TNZ
Push/Pop to/from the stack
Increment/Decrement
Test Negative or Zero
1 or 2 Complement
Byte Multiplication
Indexed (Short)
The offset is a byte, thus requires only 1 byte after
the opcode and allows 00 - 1FE addressing space.
CPL, NEG
MUL
Indexed (Long)
The offset is a word, thus allowing 64 Kbyte ad-
dressing space and requires 2 bytes after the op-
code.
SLL, SRL, SRA, RLC,
RRC
Shift and Rotate Operations
Swap Nibbles
12.1.5 Indirect (Short, Long)
SWAP
The required data byte to do the operation is found
by its memory address, located in memory (point-
er).
12.1.2 Immediate
Immediate instructions have 2 bytes, the first byte
contains the opcode, the second byte contains the
operand value.
The pointer address follows the opcode. The indi-
rect addressing mode consists of two submodes:
Indirect (Short)
Immediate Instruction
Function
The pointer address is a byte, the pointer size is a
byte, thus allowing 00 - FF addressing space, and
requires 1 byte after the opcode.
LD
Load
CP
Compare
BCP
Bit Compare
Indirect (Long)
AND, OR, XOR
ADC, ADD, SUB, SBC
Logical Operations
Arithmetic Operations
The pointer address is a byte, the pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.
105/159
ST7LITE1xB
ST7 ADDRESSING MODES (cont’d)
12.1.6 Indirect Indexed (Short, Long)
12.1.7 Relative Mode (Direct, Indirect)
This is a combination of indirect and short indexed
addressing modes. The operand is referenced by
its memory address, which is defined by the un-
signed addition of an index register value (X or Y)
with a pointer value located in memory. The point-
er address follows the opcode.
This addressing mode is used to modify the PC
register value by adding an 8-bit signed offset to it.
Available Relative Direct/
Function
Indirect Instructions
JRxx
Conditional Jump
Call Relative
The indirect indexed addressing mode consists of
two submodes:
CALLR
The relative addressing mode consists of two sub-
modes:
Indirect Indexed (Short)
The pointer address is a byte, the pointer size is a
byte, thus allowing 00 - 1FE addressing space,
and requires 1 byte after the opcode.
Relative (Direct)
The offset follows the opcode.
Relative (Indirect)
Indirect Indexed (Long)
The pointer address is a byte, the pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.
The offset is defined in memory, of which the ad-
dress follows the opcode.
Table 23. Instructions Supporting Direct,
Indexed, Indirect and Indirect Indexed
Addressing Modes
Long and Short
Function
Instructions
LD
Load
CP
Compare
AND, OR, XOR
Logical Operations
Arithmetic Addition/subtrac-
tion operations
ADC, ADD, SUB, SBC
BCP
Bit Compare
Short Instructions Only
CLR
Function
Clear
INC, DEC
Increment/Decrement
Test Negative or Zero
1 or 2 Complement
Bit Operations
TNZ
CPL, NEG
BSET, BRES
Bit Test and Jump Opera-
tions
BTJT, BTJF
SLL, SRL, SRA, RLC,
RRC
Shift and Rotate Operations
SWAP
Swap Nibbles
CALL, JP
Call or Jump subroutine
106/159
ST7LITE1xB
12.2 INSTRUCTION GROUPS
The ST7 family devices use an Instruction Set
consisting of 63 instructions. The instructions may
be subdivided into 13 main groups as illustrated in
the following table:
Load and Transfer
LD
CLR
POP
DEC
TNZ
OR
Stack operation
PUSH
INC
RSP
BCP
Increment/Decrement
Compare and Tests
Logical operations
CP
AND
BSET
BTJT
ADC
SLL
XOR
CPL
NEG
Bit Operation
BRES
BTJF
ADD
SRL
JRT
Conditional Bit Test and Branch
Arithmetic operations
Shift and Rotates
SUB
SRA
JRF
SBC
RLC
JP
MUL
RRC
CALL
SWAP
CALLR
SLA
Unconditional Jump or Call
Conditional Branch
JRA
JRxx
TRAP
SIM
NOP
RET
Interruption management
Condition Code Flag modification
WFI
RIM
HALT
SCF
IRET
RCF
Using a prebyte
PDY 90 Replace an X based instruction using
immediate, direct, indexed, or inherent
addressing mode by a Y one.
The instructions are described with 1 to 4 bytes.
In order to extend the number of available op-
codes for an 8-bit CPU (256 opcodes), three differ-
ent prebyte opcodes are defined. These prebytes
modify the meaning of the instruction they pre-
cede.
PIX 92 Replace an instruction using direct, di-
rect bit or direct relative addressing
mode to an instruction using the corre-
sponding indirect addressing mode.
It also changes an instruction using X
indexed addressing mode to an instruc-
tion using indirect X indexed addressing
mode.
The whole instruction becomes:
PC-2 End of previous instruction
PC-1 Prebyte
PIY 91 Replace an instruction using X indirect
indexed addressing mode by a Y one.
PC
Opcode
PC+1 Additional word (0 to 2) according to the
number of bytes required to compute the
effective address
12.2.1 Illegal Opcode Reset
In order to provide enhanced robustness to the de-
vice against unexpected behavior, a system of ille-
gal opcode detection is implemented. If a code to
be executed does not correspond to any opcode
or prebyte value, a reset is generated. This, com-
bined with the Watchdog, allows the detection and
recovery from an unexpected fault or interference.
These prebytes enable instruction in Y as well as
indirect addressing modes to be implemented.
They precede the opcode of the instruction in X or
the instruction using direct addressing mode. The
prebytes are:
Note: A valid prebyte associated with a valid op-
code forming an unauthorized combination does
not generate a reset.
107/159
ST7LITE1xB
INSTRUCTION GROUPS (cont’d)
Mnemo
ADC
ADD
AND
BCP
Description
Add with Carry
Function/Example
A = A + M + C
A = A + M
Dst
Src
H
H
H
I
N
N
N
N
N
Z
Z
Z
Z
Z
C
C
C
A
A
M
M
M
M
Addition
Logical And
A = A . M
A
Bit compare A, Memory
Bit Reset
tst (A . M)
A
BRES
BSET
BTJF
BTJT
CALL
CALLR
CLR
bres Byte, #3
bset Byte, #3
btjf Byte, #3, Jmp1
btjt Byte, #3, Jmp1
M
M
M
M
Bit Set
Jump if bit is false (0)
Jump if bit is true (1)
Call subroutine
Call subroutine relative
Clear
C
C
reg, M
reg
0
N
N
N
1
Z
Z
Z
CP
Arithmetic Compare
One Complement
Decrement
tst(Reg - M)
A = FFH-A
dec Y
M
C
1
CPL
reg, M
reg, M
DEC
HALT
IRET
INC
Halt
0
I
Interrupt routine return
Increment
Pop CC, A, X, PC
inc X
H
N
N
Z
Z
C
reg, M
JP
Absolute Jump
Jump relative always
Jump relative
jp [TBL.w]
JRA
JRT
JRF
Never jump
jrf *
JRIH
JRIL
Jump if ext. interrupt = 1
Jump if ext. interrupt = 0
Jump if H = 1
JRH
H = 1 ?
JRNH
JRM
Jump if H = 0
H = 0 ?
Jump if I = 1
I = 1 ?
JRNM
JRMI
JRPL
JREQ
JRNE
JRC
Jump if I = 0
I = 0 ?
Jump if N = 1 (minus)
Jump if N = 0 (plus)
Jump if Z = 1 (equal)
Jump if Z = 0 (not equal)
Jump if C = 1
N = 1 ?
N = 0 ?
Z = 1 ?
Z = 0 ?
C = 1 ?
JRNC
JRULT
Jump if C = 0
C = 0 ?
Jump if C = 1
Unsigned <
Jmp if unsigned >=
Unsigned >
JRUGE Jump if C = 0
JRUGT Jump if (C + Z = 0)
108/159
ST7LITE1xB
INSTRUCTION GROUPS (cont’d)
Mnemo
JRULE
LD
Description
Jump if (C + Z = 1)
Load
Function/Example
Unsigned <=
dst <= src
Dst
Src
H
I
N
N
N
N
N
Z
Z
Z
Z
Z
C
reg, M
A, X, Y
reg, M
M, reg
X, Y, A
MUL
NEG
NOP
OR
Multiply
X,A = X * A
0
0
Negate (2's compl)
No Operation
OR operation
Pop from the Stack
neg $10
C
A = A + M
pop reg
pop CC
push Y
C = 0
A
M
POP
reg
CC
M
M
M
H
I
C
0
PUSH
RCF
RET
RIM
Push onto the Stack
Reset carry flag
Subroutine Return
Enable Interrupts
Rotate left true C
Rotate right true C
Reset Stack Pointer
Subtract with Carry
Set carry flag
reg, CC
I = 0
0
RLC
RRC
RSP
SBC
SCF
SIM
C <= Dst <= C
C => Dst => C
S = Max allowed
A = A - M - C
C = 1
reg, M
reg, M
N
N
Z
Z
C
C
A
M
N
Z
C
1
Disable Interrupts
Shift left Arithmetic
Shift left Logic
I = 1
1
SLA
C <= Dst <= 0
C <= Dst <= 0
0 => Dst => C
Dst7 => Dst => C
A = A - M
reg, M
reg, M
reg, M
reg, M
A
N
N
0
Z
Z
Z
Z
Z
Z
Z
C
C
C
C
C
SLL
SRL
SRA
SUB
SWAP
TNZ
TRAP
WFI
Shift right Logic
Shift right Arithmetic
Subtraction
N
N
N
N
M
M
SWAP nibbles
Dst[7..4] <=> Dst[3..0] reg, M
tnz lbl1
Test for Neg & Zero
S/W trap
S/W interrupt
1
0
Wait for Interrupt
Exclusive OR
XOR
A = A XOR M
A
N
Z
109/159
ST7LITE1xB
13 ELECTRICAL CHARACTERISTICS
13.1 PARAMETER CONDITIONS
Unless otherwise specified, all voltages are re-
13.1.5 Pin input voltage
ferred to V
.
SS
The input voltage measurement on a pin of the de-
vice is described in Figure 64.
13.1.1 Minimum and Maximum values
Unless otherwise specified the minimum and max-
imum values are guaranteed in the worst condi-
tions of ambient temperature, supply voltage and
frequencies by tests in production on 100% of the
Figure 64. Pin input voltage
devices with an ambient temperature at T =25°C
A
ST7 PIN
and T =T max (given by the selected temperature
A
A
range).
V
Data based on characterization results, design
simulation and/or technology characteristics are
indicated in the table footnotes and are not tested
in production. Based on characterization, the min-
imum and maximum values refer to sample tests
and represent the mean value plus or minus three
times the standard deviation (mean 3Σ).
IN
13.1.2 Typical values
Unless otherwise specified, typical data are based
on T =25°C, V =5V (for the 4.5V≤V ≤5.5V
A
DD
DD
voltage range) and
V
=3.3V (for the
DD
3V≤V ≤3.6V voltage range). They are given only
DD
as design guidelines and are not tested.
13.1.3 Typical curves
Unless otherwise specified, all typical curves are
given only as design guidelines and are not tested.
13.1.4 Loading capacitor
The loading conditions used for pin parameter
measurement are shown in Figure 63.
Figure 63. Pin loading conditions
ST7 PIN
C
L
110/159
ST7LITE1xB
13.2 ABSOLUTE MAXIMUM RATINGS
Stresses above those listed as “absolute maxi-
mum ratings” may cause permanent damage to
the device. This is a stress rating only and func-
tional operation of the device under these condi-
tions is not implied. Exposure to maximum rating
conditions for extended periods may affect device
reliability.
13.2.1 Voltage Characteristics
Symbol
- V
Ratings
Maximum value
7.0
Unit
V
Supply voltage
DD
SS
V
1) & 2)
V
Input voltage on any pin
VSS-0.3 to VDD+0.3
IN
ESD(HBM)
V
Electrostatic discharge voltage (Human Body Model)
Electrostatic discharge voltage (Machine Model)
see section 13.7.3 on page 128
V
ESD(MM)
13.2.2 Current Characteristics
Symbol
Ratings
Maximum value
Unit
3)
3)
I
Total current into V power lines (source)
75
150
20
40
- 25
5
VDD
DD
I
Total current out of V ground lines (sink)
SS
VSS
Output current sunk by any standard I/O and control pin
Output current sunk by any high sink I/O pin
Output current source by any I/Os and control pin
Injected current on ISPSEL pin
I
IO
mA
Injected current on RESET pin
5
2) & 4)
I
Injected current on OSC1 and OSC2 pins
5
INJ(PIN)
5)
Injected current on PB0 pin
+5
5
6)
Injected current on any other pin
2)
6)
ΣI
Total injected current (sum of all I/O and control pins)
20
INJ(PIN)
13.2.3 Thermal Characteristics
Symbol
Ratings
Value
Unit
T
Storage temperature range
-65 to +150
°C
STG
Maximum junction temperature (see Table 24, “THERMAL CHARACTERISTICS,” on
page 147)
T
J
Notes:
1. Directly connecting the RESET and I/O pins to V or V could damage the device if an unintentional internal reset
DD
SS
is generated or an unexpected change of the I/O configuration occurs (for example, due to a corrupted program counter).
To guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7kΩ for
RESET, 10kΩ for I/Os). Unused I/O pins must be tied in the same way to V or V according to their reset configuration.
DD
SS
2. I
must never be exceeded. This is implicitly insured if V maximum is respected. If V maximum cannot be
INJ(PIN)
IN
INJ(PIN)
IN
respected, the injection current must be limited externally to the I
value. A positive injection is induced by V >V
IN DD
while a negative injection is induced by V <V . For true open-drain pads, there is no positive injection current, and the
IN
SS
corresponding V maximum must always be respected
IN
3. All power (V ) and ground (V ) lines must always be connected to the external supply.
DD
SS
4. Negative injection disturbs the analog performance of the device. In particular, it induces leakage currents throughout
the device including the analog inputs. To avoid undesirable effects on the analog functions, care must be taken:
- Analog input pins must have a negative injection less than 0.8 mA (assuming that the impedance of the analog voltage
is lower than the specified limits)
- Pure digital pins must have a negative injection less than 1.6mA. In addition, it is recommended to inject the current as
far as possible from the analog input pins.
5. No negative current injection allowed on PB0 pin.
6. When several inputs are submitted to a current injection, the maximum ΣI
is the absolute sum of the positive
INJ(PIN)
and negative injected currents (instantaneous values). These results are based on characterisation with ΣI
mum current injection on four I/O port pins of the device.
maxi-
INJ(PIN)
111/159
ST7LITE1xB
13.3 OPERATING CONDITIONS
13.3.1 General Operating Conditions: Suffix 6 Devices
T = -40 to +85°C unless otherwise specified.
A
Symbol
Parameter
Conditions
= 4 MHz. max., T = 0 to 85°C
Min
2.7
3.0
3.3
Max
5.5
5.5
5.5
Unit
f
f
CPU
A
V
Supply voltage
f
= 4 MHz. max.,T = -40 to 85°C
V
DD
CPU
CPU
A
= 8 MHz. max.
V
≥3.3V
up to 8
up to 4
DD
f
CPU clock frequency
MHz
CPU
2.7V≤V <3.3V
DD
13.3.2 General Operating Conditions: Suffix 3 Devices
T = -40 to +125°C unless otherwise specified.
A
Symbol
Parameter
Conditions
= 4 MHz. max., T = 0 to 125°C
Min
2.7
3.0
3.3
Max
Unit
f
5.5
5.5
5.5
CPU
A
V
Supply voltage
f
= 4 MHz. max.,T = -40 to 125°C
V
DD
CPU
A
f
= 8 MHz. max.
CPU
V
≥3.3V
up to 8
up to 4
DD
f
CPU clock frequency
MHz
CPU
2.7V≤V <3.3V
DD
Figure 65. f
Maximum Operating Frequency Versus VDD Supply Voltage
CPU
FUNCTIONALITY
GUARANTEED
IN THIS AREA
(UNLESS OTHERWISE
STATED IN THE
f
[MHz]
8
CPU
TABLES OF
PARAMETRIC DATA)
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
4
FUNCTIONALITY 2
GUARANTEED IN
THIS AREA ONLY FOR
SUPPLY VOLTAGE [V]
0
T
FROM 0°C to T max
A
A
5.5
3.0
2.0
2.7
3.3
3.5
4.0
4.5
5.0
112/159
ST7LITE1xB
13.3.3 Operating Conditions with Low Voltage Detector (LVD)
13.3.3.1 Operating Conditions with LVD at T = -40 to 125°C, unless otherwise specified
A
Symbol
Parameter
Conditions
High Threshold
Med. Threshold
Low Threshold
Min
Typ
Max
Unit
3.80
3.20
2.65
4.20
3.55
2.85
4.60
3.90
3.10
Reset release threshold
V
IT+
(LVD)
(V rise)
DD
V
High Threshold
Med. Threshold
Low Threshold
3.70
3.10
2.50
4.00
3.35
2.70
4.35
3.70
2.90
Reset generation threshold
V
V
IT-
(LVD)
(V fall)
DD
LVD voltage threshold hysteresis
V
-V
IT-
(LVD)
200
mV
ms/V
ns
hys
IT+
(LVD)
1)2)
Vt
V
rise time rate
DD
100
POR
1)
t
I
Filtered glitch delay on V
Not detected by the LVD
150
200
g(VDD)
DD(LVD
DD
)
LVD/AVD current consumption
µA
Notes:
1. The V rise time rate condition is needed to insure a correct device power-on and LVD reset. Not tested in production.
DD
2. Use of LVD with capacitive power supply: with this type of power supply, if power cuts occur in the application, it is rec-
ommended to pull V
down to 0V to ensure optimum restart conditions. Refer to circuit example in Figure 106 on
DD
page 136 and note 4.
113/159
ST7LITE1xB
13.3.4 Auxiliary Voltage Detector (AVD) Thresholds
T = -40 to 125°C, unless otherwise specified
A
Symbol
Parameter
Conditions
High Threshold
Med. Threshold
Low Threshold
Typ
Unit
4.50
4.00
3.35
1=>0 AVDF flag toggle threshold
V
IT+
(AVD)
(V rise)
DD
V
High Threshold
Med. Threshold
Low Threshold
4.40
3.85
3.20
0=>1 AVDF flag toggle threshold
V
V
IT-
(AVD)
(V fall)
DD
AVD voltage threshold hysteresis
V
-V
IT-
(AVD)
170
mV
V
hys
IT+
(AVD)
fall
Voltage drop between AVD flag set and
LVD reset activation
ΔV
V
0.15
IT-
DD
13.3.5 Internal RC Oscillator and PLL
The ST7 internal clock can be supplied by an internal RC oscillator and PLL (selectable by option byte).
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
V
Internal RC Oscillator operating voltage
Refer to operating range
2.7
5.5
DD(RC)
of V with T section
13.3.1 on page 112
DD
A,
V
V
x4 PLL operating voltage
x8 PLL operating voltage
2.7
3.3
3.7
5.5
V
DD(x4PLL)
DD(x8PLL)
PLL
input
clock
t
PLL Startup time
60
STARTUP
(f
)
PLL
cycles
114/159
ST7LITE1xB
OPERATING CONDITIONS (Cont’d)
The RC oscillator and PLL characteristics are temperature-dependent and are grouped in four tables.
13.3.5.1 Devices with ‘”6” or “3”order code suffix (tested for T = -40 to +125°C) @ V = 5V
A
DD
Symbol
Parameter
Conditions
RCCR = FF (reset value), T =25°C,V =5V
Min
Typ
700
Max
Unit
Internal RC oscillator fre-
A
DD
f
kHz
1)
RC
2 )
quency
RCCR = RCCR0 ,T =25°C,V =5V
992
-0.8
-1
1000
1008
+0.8
+1
A
DD
T =25°C,V =5V
%
%
%
%
%
%
%
A
DD
3)
T =25°C, V =4.5 to 5.5V
A
DD
T =25°C to +85°C,V =5V
-3
+3
A
DD
Accuracy of Internal RC
oscillator with
3)
ACC
T =25°C to +85°C,V =4.5 to 5.5V
-3.5
-3.5
-3.5
-3
+3.5
+5
RC
A
DD
2)
RCCR=RCCR0
T =85°C to +125°C,V =5V
A
DD
3)
T =85°C to +125°C,V =4.5 to 5.5V
+6
A
DD
3)
T =-40 to +25°C, V =5V
+7
A
DD
RC oscillator current con-
sumption
3)
I
T =25°C,V =5V
600
μA
DD(RC)
A
DD
2)
t
f
t
t
RC oscillator setup time T =25°C,V =5V
10
μs
MHz
ms
ms
%
su(RC)
PLL
A
DD
3)
x8 PLL input clock
1
5)
PLL Lock time
2
4
LOCK
STAB
5)
PLL Stabilization time
x8 PLL Accuracy
4)
f
f
f
= 1MHz@T =25°C,V =4.5 to 5.5V
0.1
RC
RC
RC
A
DD
ACC
PLL
4)
= 1MHz@T =-40 to +85°C,V =5V
0.1
%
A
DD
6)
t
PLL jitter period
= 1MHz
120
7)
µs
w(JIT)
JIT
PLL jitter (Δf
/f )
1
%
PLL
CPU CPU
3)
I
PLL current consumption T =25°C
600
μA
DD(PLL)
A
Notes:
1. If the RC oscillator clock is selected, to improve clock stability and frequency accuracy, it is recommended to place a
decoupling capacitor, typically 100nF, between the V and V pins as close as possible to the ST7 device.
DD
SS
2. See “INTERNAL RC OSCILLATOR ADJUSTMENT” on page 23
3. Data based on characterization results, not tested in production
4. Averaged over a 4ms period. After the LOCKED bit is set, a period of t
is required to reach ACC
accuracy.
PLL
STAB
5. After the LOCKED bit is set ACC
is max. 10% until t
has elapsed. See Figure 13 on page 24.
PLL
STAB
6. This period is the phase servo loop period. During this period, the frequency remains unchanged.
7. Guaranteed by design.
115/159
ST7LITE1xB
Figure 66. Typical accuracy with RCCR=RCCR0 vs V = 4.5-5.5V and Temperature
DD
3.50%
3.00%
2.50%
2.00%
-45
-10
0
1.50%
1.00%
0.50%
0.00%
-0.50%
-1.00%
25
90
110
130
4.5
4.6
4.7
4.8
4.9
5
5.1
5.2
5.3
5.4
5.5
Vdd (V)
Figure 67. Typical RCCR0 vs V and Temperature
DD
1.025
1.02
1.015
1.01
1.005
1
-45
-10
0
25
90
110
130
0.995
0.99
0.985
0.98
4.5
4.6
4.7
4.8
4.9
5
5.1
5.2
5.3
5.4
5.5
Vdd (V)
116/159
ST7LITE1xB
OPERATING CONDITIONS (Cont’d)
13.3.5.2 Devices with ‘”6” or “3” order code suffix (tested for T = -40 to +125°C) @ V = 3.0 to 3.6V
A
DD
Typ
700
Symbol
Parameter
Conditions
RCCR = FF (reset value), T =25°C, V = 3.3V
Min
Max
Unit
Internal RC oscillator fre-
quency
A
DD
f
kHz
1)
RC
2)
RCCR=RCCR1 ,T =25°C,V = 3.3V
992
-0.8
-1
1000 1008
A
DD
T =25°C,V =3.3V
+0.8
+1
%
%
%
%
%
%
A
DD
3)
T =25°C,V =3.0 to 3.6V
A
DD
Accuracy of Internal RC
oscillator when calibrated
with RCCR=RCCR1
T =25 to +85°C,V =3.3V
-3
+3
A
DD
ACC
RC
3)
T =25 to +85°C,V =3.0 to 3.6V
-3.5
-5
+3.5
+6.5
+4
2)
A
DD
3)
T =25 to +125°C,V =3.0 to 3.6V
A
DD
3)
T =-40 to +25°C,V =3.0 to 3.6V
-3.5
A
DD
RC oscillator current con-
sumption
3)
I
T =25°C,V =3.3V
400
μA
DD(RC)
A
DD
2)
t
f
t
t
RC oscillator setup time T =25°C,V =3.3V
10
μs
MHz
ms
ms
%
su(RC)
PLL
A
DD
3)
x4 PLL input clock
0.7
5)
PLL Lock time
2
4
LOCK
STAB
5)
PLL Stabilization time
x4 PLL Accuracy
4)
f
f
f
= 1MHz@T =25°C, V =2.7 to 3.3V
0.1
RC
RC
RC
A
DD
ACC
PLL
4)
= 1MHz@T =40 to +85°C, V = 3.3V
0.1
%
A
DD
6)
t
PLL jitter period
= 1MHz
120
7)
µs
w(JIT)
JIT
PLL jitter (Δf
/f )
1
%
PLL
CPU CPU
3)
I
PLL current consumption T =25°C
190
μA
DD(PLL)
A
Notes:
1. If the RC oscillator clock is selected, to improve clock stability and frequency accuracy, it is recommended to place a
decoupling capacitor, typically 100nF, between the V and V pins as close as possible to the ST7 device.
DD
SS
2. See “INTERNAL RC OSCILLATOR ADJUSTMENT” on page 23.
3. Data based on characterization results, not tested in production
4. Averaged over a 4ms period. After the LOCKED bit is set, a period of t
is required to reach ACC
accuracy
PLL
STAB
5. After the LOCKED bit is set ACC
is max. 10% until t
has elapsed. See Figure 13 on page 24.
PLL
STAB
6. This period is the PLL servoing period. During this period, the frequency remains unchanged.
7. Guaranteed by design.
117/159
ST7LITE1xB
OPERATING CONDITIONS (Cont’d)
Figure 68. Typical accuracy with RCCR=RCCR1 vs V = 3-3.6V and Temperature
DD
1.50%
1.00%
-45
0.50%
0.00%
-0.50%
-1.00%
-10
0
25
90
110
130
3
3.1
3.2
3.3
3.4
3.5
3.6
Vdd (V)
Figure 69. Typical RCCR1 vs V and Temperature
DD
1.01
1.005
1
-45
-10
0
0.995
0.99
0.985
0.98
25
90
110
130
3
3.1
3.2
3.3
3.4
3.5
3.6
Vdd (V)
118/159
ST7LITE1xB
OPERATING CONDITIONS (Cont’d)
Figure 70. PLL Δf /f versus time
CPU CPU
/f
Δf
CPU CPU
Max
0
t
Min
t
t
w(JIT)
w(JIT)
13.3.5.3 32MHz PLL
T = -40 to 125°C, unless otherwise specified
A
Symbol
Parameter
Min
Typ
5
Max
Unit
V
1)
V
Voltage
Frequency
4.5
5.5
DD
1)
f
f
32
8
MHz
MHz
PLL32
INPUT
7
Input Frequency
9
Note:
1. 32 MHz is guaranteed within this voltage range.
119/159
ST7LITE1xB
13.3.6 Operating conditions with ADC
T = -40 to 125°C, unless otherwise specified
A
Symbol
Parameter
Injected current on any analog pin
Typ
Unit
1)
I
0
mA
INJ(ANA)
Note:
1. Current injection (negative or positive) not allowed on any analog pin.
120/159
ST7LITE1xB
13.4 SUPPLY CURRENT CHARACTERISTICS
The following current consumption specified for
the ST7 functional operating modes over tempera-
ture range does not take into account the clock
source current consumption. To get the total de-
vice consumption, the two current values must be
added (except for HALT mode for which the clock
is stopped).
13.4.1 Supply Current
T = -40 to +85°C unless otherwise specified
A
Symbol
Parameter
Conditions
Typ
Max
Unit
1)
9
Supply current in RUN mode
Supply current in WAIT mode
Supply current in SLOW mode
Supply current in SLOW WAIT mode7
f
f
f
f
=8MHz
7
3
CPU
CPU
CPU
CPU
2)
3.6
0.9
0.8
6
=8MHz
mA
3)
4)
0.7
0.5
<1
=250kHz
=250kHz
I
DD
5)
Supply current in HALT mode
-40°C≤T ≤+125°C
A
μA
6)7)
20
Supply current in AWUFH mode
-40°C≤T ≤+125°C
A
Notes:
1. CPU running with memory access, all I/O pins in input mode with a static value at V or V (no load), all peripherals
DD
SS
in reset state; clock input (CLKIN) driven by external square wave, LVD disabled.
2. All I/O pins in input mode with a static value at V or V (no load), all peripherals in reset state; clock input (CLKIN)
DD
SS
driven by external square wave, LVD disabled.
3. SLOW mode selected with f
SS
based on f
divided by 32. All I/O pins in input mode with a static value at V or
CPU
OSC DD
V
(no load), all peripherals in reset state; clock input (CLKIN) driven by external square wave, LVD disabled.
4. SLOW-WAIT mode selected with f
based on f
divided by 32. All I/O pins in input mode with a static value at
CPU
OSC
V
or V (no load), all peripherals in reset state; clock input (CLKIN) driven by external square wave, LVD disabled.
DD
SS
5. All I/O pins in output mode with a static value at V (no load), LVD disabled. Data based on characterization results,
SS
tested in production at V max and f
max.
DD
CPU
6. All I/O pins in input mode with a static value at V or V (no load). Data tested in production at V max. and f
DD
SS
DD
CPU
max.
7. This consumption refers to the Halt period only and not the associated run period which is software dependent.
Figure 71. Typical I in RUN vs. f
Figure 72. Typical I in RUN at f
= 8MHz
CPU
DD
CPU
DD
9
.5
8
9
8
7
6
5
4
3
2
1
0
1
2
7
4
6
5
4
3
2
1
0
6
8
140°C
90°C
25°C
-5°C
-45°C
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
Vdd (V)
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
Note: Graph displays data beyond the normal operating range of 3V - 5.5V
Vdd (V)
Note: Graph displays data beyond the normal operating range of 3V - 5.5V
121/159
ST7LITE1xB
Figure 73. Typical I in SLOW vs. f
Figure 76. Typical I in SLOW-WAIT vs. f
CPU
DD
CPU
DD
0.90
0.60
250KHz
125KHz
62KHz
0.80
0.70
0.60
0.50
0.40
0.30
0.20
0.10
0.00
250KHz
0.50
125KHz
62KHz
0.40
0.30
0.20
0.10
0.00
2.7
3.3
4
5
6
2.7
3.3
4
5
6
VDD (V)
VDD (V)
Note: Graph displays data beyond the normal operating range of 3V - 5.5V
Note: Graph displays data beyond the normal operating range of 3V - 5.5V
Figure 74. Typical I in WAIT vs. f
DD
CPU
Figure 77. Typical I vs. Temperature
DD
4
at V = 5V and f
= 8MHz
DD
CPU
3.5
3
0.5
1
6.00
5.00
4.00
3.00
2.00
1.00
2
4
2.5
2
RUN
6
8
WAIT
SLOW
1.5
1
SLOW-WAIT
0.5
0.00
0
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
-45
25
90
110
Note: Graph displays data beyond thVeddn(Vo) rmal operating range of 3V - 5.5V
Temperature (°C)
Figure 75. Typical I in WAIT at f
= 8MHz
DD
CPU
4
3.5
3
0.5
1
2
4
2.5
2
6
8
1.5
1
0.5
0
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
Note: Graph displays data beyond thVeddn(Vo) rmal operating range of 3V - 5.5V
122/159
ST7LITE1xB
13.4.2 On-chip peripherals
Symbol
Parameter
Conditions
Typ
150
1000
50
Unit
f
f
f
f
=4MHz
=8MHz
=4MHz
=8MHz
V
V
V
V
V
V
=3.0V
=5.0V
=3.0V
=5.0V
=3.0V
=5.0V
CPU
CPU
CPU
CPU
DD
DD
DD
DD
DD
DD
1)
I
12-bit Auto-Reload Timer supply current
DD(AT)
2)
I
SPI supply current
μA
DD(SPI)
200
250
1100
3)
I
ADC supply current when converting
f
=4MHz
DD(ADC)
ADC
Notes:
1. Data based on a differential I measurement between reset configuration (timer stopped) and a timer running in PWM
DD
mode at f =8MHz.
cpu
2. Data based on a differential I measurement between reset configuration and a permanent SPI master communica-
DD
tion (data sent equal to 55h).
3. Data based on a differential I measurement between reset configuration and continuous A/D conversions with am-
DD
plifier disabled.
123/159
ST7LITE1xB
13.5 CLOCK AND TIMING CHARACTERISTICS
Subject to general operating conditions for V , f
, and T .
DD OSC
A
13.5.1 General Timings
1)
3)
2)
Symbol
Parameter
Conditions
Min
2
Typ
Max
12
Unit
tCPU
ns
3
t
Instruction cycle time
f
f
=8MHz
c(INST)
CPU
250
10
375
1500
22
tCPU
μs
Interrupt reaction time
t
=8MHz
v(IT)
CPU
t
= Δt
+ 10
1.25
2.75
v(IT)
c(INST)
Notes:
1. Guaranteed by Design. Not tested in production.
2. Data based on typical application software.
3. Time measured between interrupt event and interrupt vector fetch. Δt
ish the current instruction execution.
is the number of t
cycles needed to fin-
c(INST)
CPU
4. Data based on design simulation and/or technology characteristics, not tested in production.
13.5.2 External Clock Source
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
V
or V
or V
t
OSC1/CLKIN input pin high level voltage
OSC1/CLKIN input pin low level voltage
0.7xV
V
DD
OSC1H
CLKIN_H
CLKIN_L
DD
V
V
V
0.3xV
DD
OSC1L
SS
t
4)
w(OSC1H) or w(CLKINH)
see Figure 78
OSC1/CLKIN high or low time
15
t
t
w(OSC1L) or w(CLKINL)
ns
t
t
t
t
4)
r(OSC1) or r(CLKIN)
OSC1/CLKIN rise or fall time
15
1
f(OSC1) or f(CLKIN)
I
OSCx/CLKIN Input leakage current
V
≤V ≤V
μA
L
SS
IN
DD
Figure 78. Typical Application with an External Clock Source
90%
V
or V
OSC1H
OSC1L
CLKINH
10%
V
or V
CLKINL
t
t
w(OSC1H or CLKINH))
t
t
f(OSC1 or CLKIN)
r(OSC1 or CLKIN))
w(OSC1L or CLKINL)
OSC2
Not connected internally
f
OSC
EXTERNAL
CLOCK SOURCE
I
L
OSC1/CLKIN
ST72XXX
13.5.3 Auto Wakeup from Halt Oscillator (AWU)
1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
f
t
AWU Oscillator Frequency
AWU Oscillator startup time
50
125
250
50
kHz
µs
AWU
RCSRT
Note: 1. Guaranteed by Design. Not tested in production.
124/159
ST7LITE1xB
CLOCK AND TIMING CHARACTERISTICS (Cont’d)
13.5.4 Crystal and Ceramic Resonator Oscillators
The ST7 internal clock can be supplied with ten
different Crystal/Ceramic resonator oscillators. All
the information given in this paragraph are based
on characterization results with specified typical
external components. In the application, the reso-
nator and the load capacitors have to be placed as
close as possible to the oscillator pins in order to
minimize output distortion and start-up stabiliza-
tion time. Refer to the crystal/ceramic resonator
manufacturer for more details (frequency, pack-
age, accuracy...).
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
f
Crystal Oscillator Frequency
2
16
MHz
CrOSC
Recommended load capacitance ver-
sus equivalent serial resistance of the
C
C
L1
L2
See table below
pF
crystal or ceramic resonator (R )
S
1)
3)
3)
Typical Ceramic Resonators
f
CL1
CL2
[pF]
Rd Supply Voltage Temperature
CrOSC
Supplier
2)
[pF]
[Ω]
Range [V]
Range [°C]
(MHz)
Type
SMD
LEAD
SMD
SMD
LEAD
SMD
LEAD
SMD
SMD
LEAD
Reference
CSBFB1M00J58-R0
CSBLA1M00J58-B0
CSTCC2M00G56Z-R0
CSTCR4M00G53Z-R0
CSTLS4M00G53Z-B0
CSTCE8M00G52Z-R0
CSTLS8M00G53Z-B0
CSTCE12M0G52Z-R0
CSTCE16M0V51Z-R0
CSTLS16M0X51Z-B0
220
220
(47)
(15)
(15)
(10)
(15)
(10)
(5)
220
220
(47)
(15)
(15)
(10)
(15)
(10)
(5)
2.2k
1
2
4
3.3V to 5.5V
2.2k
0
0
3.0V to 5.5V
3.3V to 5.5V
0
-40 to 85
0
8
0
12
16
0
0
(5)
(5)
0
Notes:
1. Resonator characteristics given by the ceramic resonator manufacturer. For more information on these resonators,
please consult www.murata.com
2. SMD = [-R0: Plastic tape package (∅ =180mm)]
LEAD = [-B0: Bulk]
3. () means load capacitor built in resonator
Figure 79. Typical Application with a Crystal or Ceramic Resonator
WHEN RESONATOR WITH
INTEGRATED CAPACITORS
i
2
f
OSC
C
L1
OSC1
OSC2
RESONATOR
C
L2
ST7LITE1xB
R
d
125/159
ST7LITE1xB
13.6 MEMORY CHARACTERISTICS
T = -40°C to 125°C, unless otherwise specified
A
13.6.1 RAM and Hardware Registers
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
1)
V
Data retention mode
HALT mode (or RESET)
1.6
V
RM
13.6.2 FLASH Program Memory
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Refer to operating range of
with T section 13.3.1
V
2.7
5.5
V
Operating voltage for Flash write/erase
V
DD
A,
DD
on page 112
2)
T =−40 to +125°C
5
10
Programming time for 1~32 bytes
ms
s
A
t
t
prog
RET
T =+25°C
0.24
0.48
Programming time for 1.5 kBytes
A
4)
3)
Data retention
T =+55°C
20
years
cycles
A
N
Write erase cycles
T =+25°C
10K
RW
A
Read / Write / Erase modes
2.6
mA
f
= 8MHz, V = 5.5V
CPU
DD
6)
I
Supply current
DD
No Read/No Write Mode
Power down mode / HALT
100
0.1
μA
μA
0
13.6.3 EEPROM Data Memory
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Refer to operating range of V with
Operating voltage for EEPROM
write/erase
DD
5.5
10
V
t
2.7
V
DD
T
section 13.3.1 on page 112
A,
Programming time for 1~32
bytes
T =−40 to +125°C
5
ms
A
prog
4)
3)
t
Data retention
T =+55°C
20
years
ret
A
N
Write erase cycles
T =+25°C
300K
cycles
RW
A
Notes:
1. Minimum V supply voltage without losing data stored in RAM (in HALT mode or under RESET) or in hardware reg-
DD
isters (only in HALT mode). Guaranteed by construction, not tested in production.
2. Up to 32 bytes can be programmed at a time.
3. The data retention time increases when the T decreases.
A
4. Data based on reliability test results and monitored in production.
5. Data based on characterization results, not tested in production.
6. Guaranteed by Design. Not tested in production.
126/159
ST7LITE1xB
13.7 EMC CHARACTERISTICS
tion environment and simplified MCU software. It
should be noted that good EMC performance is
highly dependent on the user application and the
software in particular.
Susceptibility tests are performed on a sample ba-
sis during product characterization.
13.7.1 Functional EMS (Electro Magnetic
Susceptibility)
Therefore it is recommended that the user applies
EMC software optimization and prequalification
tests in relation with the EMC level requested for
his application.
Based on a simple running application on the
product (toggling 2 LEDs through I/O ports), the
product is stressed by two electro magnetic events
until a failure occurs (indicated by the LEDs).
■ ESD: Electro-Static Discharge (positive and
negative) is applied on all pins of the device until
a functional disturbance occurs. This test
conforms with the IEC 1000-4-2 standard.
Software recommendations:
The software flowchart must include the manage-
ment of runaway conditions such as:
– Corrupted program counter
– Unexpected reset
■ FTB: A Burst of Fast Transient voltage (positive
– Critical Data corruption (control registers...)
Prequalification trials:
and negative) is applied to V and V through
DD
SS
a 100pF capacitor, until a functional disturbance
occurs. This test conforms with the IEC 1000-4-
4 standard.
Most of the common failures (unexpected reset
and program counter corruption) can be repro-
duced by manually forcing a low state on the RE-
SET pin or the Oscillator pins for 1 second.
A device reset allows normal operations to be re-
sumed. The test results are given in the table be-
low based on the EMS levels and classes defined
in application note AN1709.
To complete these trials, ESD stress can be ap-
plied directly on the device, over the range of
specification values. When unexpected behaviour
is detected, the software can be hardened to pre-
vent unrecoverable errors occurring (see applica-
tion note AN1015).
13.7.1.1 Designing hardened software to avoid
noise problems
EMC characterization and optimization are per-
formed at component level with a typical applica-
Level/
Symbol
Parameter
Conditions
Class
Voltage limits to be applied on any I/O pin to induce a
functional disturbance
V
=5V, T =+25°C, f
=8MHz
OSC
DD
A
V
2B
FESD
conforms to IEC 1000-4-2
Fast transient voltage burst limits to be applied
V
=5V, T =+25°C, f =8MHz
DD
A
OSC
V
through 100pF on V and V pins to induce a func-
3B
FFTB
DD SS
conforms to IEC 1000-4-4
tional disturbance
13.7.2 Electro Magnetic Interference (EMI)
Based on a simple application running on the
product (toggling 2 LEDs through the I/O ports),
the product is monitored in terms of emission. This
emission test is in line with the norm SAE J 1752/
3 which specifies the board and the loading of
each pin.
Max vs. [f
/f
]
Unit
Monitored
Frequency Band
OSC CPU
Symbol
Parameter
Conditions
8/4MHz 16/8MHz
0.1MHz to 30MHz
30MHz to 130MHz
130MHz to 1GHz
SAE EMI Level
15
22
17
3.5
21
29
22
3.5
V
=5V, T =+25°C,
A
DD
dBμV
S
Peak level
SO20 package,
conforming to SAE J 1752/3
EMI
-
Note:
1. Data based on characterization results, not tested in production.
127/159
ST7LITE1xB
EMC CHARACTERISTICS (Cont’d)
13.7.3 Absolute Maximum Ratings (Electrical
Sensitivity)
13.7.3.1 Electro-Static Discharge (ESD)
Electro-Static Discharges (a positive then a nega-
tive pulse separated by 1 second) are applied to
the pins of each sample according to each pin
combination. The sample size depends on the
number of supply pins in the device (3 parts*(n+1)
supply pin). Two models can be simulated: Human
Body Model and Machine Model. This test con-
forms to the JESD22-A114A/A115A standard.
Based on two different tests (ESD and LU) using
specific measurement methods, the product is
stressed in order to determine its performance in
terms of electrical sensitivity. For more details, re-
fer to the application note AN1181.
Absolute Maximum Ratings
1)
Symbol
Ratings
Conditions
Maximum value
Unit
Electro-static discharge voltage
(Human Body Model)
T =+25°C
V
8000
A
ESD(HBM)
V
Electro-static discharge voltage
(Machine Model)
T =+25°C
V
400
A
ESD(MM)
Note:
1. Data based on characterization results, not tested in production.
13.7.3.2 Static Latch-Up
each input, output and configurable I/O pin) are
performed on each sample. This test conforms
to the EIA/JESD 78 IC latch-up standard. For
more details, refer to the application note
AN1181.
■ LU: 3 complementary static tests are required
on 6 parts to assess the latch-up performance.
A supply overvoltage (applied to each power
supply pin) and a current injection (applied to
Electrical Sensitivities
Symbol
Parameter
Static latch-up class
Conditions
Class
T =+25°C
A
A
A
LU
T =+85°C
A
128/159
ST7LITE1xB
13.8 I/O PORT PIN CHARACTERISTICS
13.8.1 General Characteristics
Subject to general operating conditions for V , f
, and T unless otherwise specified.
A
DD OSC
Symbol
Parameter
Input low level voltage
Input high level voltage
Schmitt trigger voltage
Conditions
Min
Typ
Max
Unit
V
VSS - 0.3
0.7xVDD
0.3xVDD
VDD + 0.3
IL
V
V
IH
V
400
400
mV
1)
hys
hysteresis
I
Input leakage current
V
SS≤V ≤V
DD
1
L
IN
Static current consumption in-
μA
I
duced by each floating input Floating input mode
S
2)
pin
V
V
=5V
=3V
50
120
160
5
250
Weak pull-up equivalent
DD
DD
R
V =V
SS
kΩ
3)
PU
IN
resistor
C
I/O pin capacitance
pF
IO
Output high to low level fall
t
t
25
25
1)
f(IO)out
time
C =50pF
Between 10% and 90%
L
ns
Output low to high level rise
1)
r(IO)out
time
4)
t
External interrupt pulse time
1
t
CPU
w(IT)in
Notes:
1. Data based on validation/design results.
2. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for
example or an external pull-up or pull-down resistor (see Figure 80). Static peak current value taken at a fixed V value,
IN
based on design simulation and technology characteristics, not tested in production. This value depends on V and tem-
DD
perature values.
3. The R pull-up equivalent resistor is based on a resistive transistor.
PU
4. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external
interrupt source.
Figure 80. Two typical Applications with unused I/O Pin
V
ST7XXX
DD
UNUSED I/O PORT
10kΩ
10kΩ
UNUSED I/O PORT
ST7XXX
Caution: During normal operation the ICCCLK pin must be pulled-up, internally or externally
(external pull-up of 10k mandatory in noisy environment). This is to avoid entering ICC mode unexpectedly during a reset.
Note: I/O can be left unconnected if it is configured as output (0 or 1) by the software. This has the advantage of greater EMC
robustness and lower cost.
129/159
ST7LITE1xB
I/O PORT PIN CHARACTERISTICS (Cont’d)
13.8.2 Output Driving Current
Subject to general operating conditions for V , f
, and T unless otherwise specified.
A
DD CPU
Symbol
Parameter
Conditions
Min
Max
Unit
I
I
I
I
I
I
=+5mA T ≤125°C
Output low level voltage for a standard I/O pin
when 8 pins are sunk at same time
(see Figure 83)
1.0
IO
IO
IO
IO
IO
IO
A
=+2mA T ≤125°C
0.4
1.3
A
1)
V
OL
=+20mA,T ≤125°C
Output low level voltage for a high sink I/O pin
when 4 pins are sunk at same time
(see Figure 89)
A
=+8mA T ≤125°C
0.75
A
=-5mA, T ≤125°C
Output high level voltage for an I/O pin
when 4 pins are sourced at same time
(see Figure 95)
V
V
-1.5
A
DD
DD
2)
V
OH
=-2mA T ≤125°C
-0.8
A
Output low level voltage for a standard I/O pin
when 8 pins are sunk at same time
(see Figure 82)
I
=+2mA T ≤125°C
0.5
0.5
IO
A
1)3)
2)3)
1)3)
V
OL
V
Output low level voltage for a high sink I/O pin
when 4 pins are sunk at same time
I
I
=+8mA T ≤125°C
IO
IO
A
Output high level voltage for an I/O pin
when 4 pins are sourced at same time (Figure 94)
=-2mA T ≤125°C
V
V
-0.8
A
OH
DD
Output low level voltage for a standard I/O pin
when 8 pins are sunk at same time
(see Figure 87)
I
I
I
=+2mA T ≤125°C
0.6
0.6
IO
IO
IO
A
V
OL
Output low level voltage for a high sink I/O pin
when 4 pins are sunk at same time
=+8mA T ≤125°C
A
Output high level voltage for an I/O pin
when 4 pins are sourced at same time
(see Figure 101)
2)3)
=-2mA T ≤125°C
V
V
-0.9
DD
A
OH
Notes:
1. The I current sunk must always respect the absolute maximum rating specified in Section 13.2.2 and the sum of I
IO
IO
(I/O ports and control pins) must not exceed I
.
VSS
2. The I current sourced must always respect the absolute maximum rating specified in Section 13.2.2 and the sum of
IO
I
(I/O ports and control pins) must not exceed I
.
IO
VDD
3. Not tested in production, based on characterization results.
130/159
ST7LITE1xB
I/O PORT PIN CHARACTERISTICS (Cont’d)
Figure 81. Typical V at V =2.7V (standard)
Figure 84. Typical V at V =2.7V (Port C)
OL DD
OL
DD
140°C
90°C
25°C
-5°C
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
140°C
90°C
25°C
-5°C
0.4
0.35
0.3
0.25
0.2
-45°C
-45°C
0.15
0.1
0.05
0
0
0.5
1
1.5
2
2.5
3
3.5
Iol (mA)
0
1
2
3
4
5
6
7
Iol (mA)
Figure 85. Typical V at V =3.3V (Port C)
Figure 82. Typical V at V =3.3V (standard)
OL
DD
OL
DD
0.6
0.5
0.4
0.3
0.2
0.1
0
140°C
90°C
25°C
-5°C
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
140°C
90°C
25°C
-5°C
-45°C
-45°C
0
0.5
1
1.5
2
2.5
3
3.5
0
0.5
1
1.5
2
2.5
3
3.5
Iol (mA)
Iol (mA)
Figure 83. Typical V at V =5V (standard)
Figure 86. Typical V at V =5V (Port C)
OL
DD
OL
DD
140°C
90°C
25°C
-5°C
1.2
1.2
140°C
90°C
25°C
-5°C
1
1
0.8
0.6
0.4
0.2
0
0.8
0.6
0.4
0.2
0
-45°C
-45°C
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
Iol (mA)
Iol (mA)
131/159
ST7LITE1xB
I/O PORT PIN CHARACTERISTICS (Cont’d)
Figure 87. Typical V at V =2.7V (High-sink)
Figure 90. Typical V vs. V (standard I/Os)
OL DD
OL
DD
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
140°C
90°C
25°C
-5°C
140°C
90°C
25°C
-5°C
0.6
0.5
0.4
0.3
0.2
0.1
0
-45°C
-45°C
0
2
4
6
8
10
12
Iol (mA)
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
VDD (V)
Figure 88. Typical V at V =3.3V (High-sink)
OL
DD
Figure 91. Typical V vs V (High-sink)
OL
DD
0.6
0.5
0.4
0.3
0.2
0.1
0
140°C
90°C
25°C
-5°C
140°C
90°C
25°C
-5°C
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
-45°C
-45°C
0
2
4
6
8
10
12
Iol (mA)
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
Vdd (V)
Figure 89. Typical V at V =5V (High-sink)
OL
DD
Figure 92. Typical V vs V (Port C)
OL
DD
140°C
90°C
25°C
-5°C
1.6
1.4
1.2
1
140°C
90°C
25°C
-5°C
0.6
0.5
0.4
0.3
0.2
0.1
0
-45°C
0.8
0.6
0.4
0.2
0
-45°C
0
5
10
15
20
25
30
35
Iol (mA)
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
Vdd (V)
132/159
ST7LITE1xB
I/O PORT PIN CHARACTERISTICS (Cont’d)
Figure 93. Typical V -V at V =2.7V
Figure 96. Typical V -V at V =2.7V (HS)
DD OH DD
DD OH
DD
1.2
140°C
90°C
25°C
-5°C
140°C
90°C
25°C
-5°C
1
1.2
1
0.8
0.6
0.4
0.2
0
0.8
0.6
0.4
0.2
0
-45°C
-45°C
0
0.5
1
1.5
2
2.5
3
3.5
Iol (mA)
0
0.5
1
1.5
2
2.5
3
3.5
Iol (mA)
Figure 94. Typical V -V at V =3.3V
DD OH
DD
Figure 97. Typical V -V at V =3.3V (HS)
DD OH
DD
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
140°C
90°C
25°C
-5°C
140°C
90°C
25°C
-5°C
-45°C
-45°C
0
0.5
1
1.5
2
2.5
3
3.5
0
0.5
1
1.5
2
2.5
3
3.5
Iol (mA)
Iol (mA)
Figure 95. Typical V -V at V =5V
DD OH
DD
Figure 98. Typical V -V at V =5V (HS)
DD OH
DD
1.6
1.4
1.2
1
1.6
1.4
1.2
1
140°C
90°C
25°C
-5°C
140°C
90°C
25°C
-5°C
0.8
0.6
0.4
0.2
0
0.8
0.6
0.4
0.2
0
-45°C
-45°C
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
Iol (mA)
Iol (mA)
133/159
ST7LITE1xB
I/O PORT PIN CHARACTERISTICS (Cont’d)
Figure 99. Typical VDD-VOH at VDD=2.7V (Port C)
Figure 102. Typical V -V vs. V (Standard)
DD OH
DD
0.8
140°C
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
140°C
90°C
25°C
-5°C
0.7
90°C
0.6
25°C
0.5
-5°C
0.4
0.3
0.2
0.1
0
-45°C
-45°C
0
0.5
1
1.5
2
2.5
3
3.5
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
Iol (mA)
vdd (V)
Figure 103. Typical V -V
vs. V
(High
DD
DD OH
Figure 100. Typical VDD-VOH at VDD=3.3V (Port
C)
Sink)
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
140°C
90°C
25°C
-5°C
1.2
140°C
90°C
25°C
-5°C
1
0.8
0.6
0.4
0.2
0
-45°C
-45°C
0
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
vdd (V)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
Iol (mA)
Figure 104. Typical V -V vs. V (PORT C)
DD OH
DD
Figure 101. Typical V -V at V =5V (Port C)
DD OH
DD
140°C
90°C
25°C
-5°C
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1.4
1.2
1
140°C
90°C
25°C
-5°C
-45°C
0.8
0.6
0.4
0.2
0
-45°C
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
vdd (V)
0
1
2
3
4
5
6
7
8
Iol (mA)
134/159
ST7LITE1xB
13.9 CONTROL PIN CHARACTERISTICS
13.9.1 Asynchronous RESET Pin
T = -40°C to 125°C, unless otherwise specified
A
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
V
1)
V
Input low level voltage
Vss - 0.3
0.7xVDD
0.3xVDD
VDD + 0.3
IL
1)
V
Input high level voltage
IH
1)
V
Schmitt trigger voltage hysteresis
2
V
hys
I =+5mA T ≤85°C
0.5
0.2
40
70
30
1.0
0.4
80
IO
A
1)2)
V
R
Output low level voltage
V
=5V
V
OL
DD
I =+2mA T ≤85°C
IO
A
V
V
=5V
=3V
20
40
DD
DD
3)
Pull-up equivalent resistor
kΩ
ON
1)
120
t
Generated reset pulse duration
Internal reset sources
μs
μs
ns
w(RSTL)out
4)
t
t
External reset pulse hold time
20
h(RSTL)in
g(RSTL)in
Filtered glitch duration
200
Notes:
1. Data based on characterization results, not tested in production.
2. The I current sunk must always respect the absolute maximum rating specified in Section 13.2.2 and the sum of I
IO
IO
(I/O ports and control pins) must not exceed I
.
VSS
3. The R
ILmax
pull-up equivalent resistor is based on a resistive transistor. Specified for voltages on RESET pin between
DD
ON
V
and V
4. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on
RESET pin with a duration below t can be ignored.
h(RSTL)in
135/159
ST7LITE1xB
CONTROL PIN CHARACTERISTICS (Cont’d)
1)2)3)4)
Figure 105. RESET pin protection when LVD is enabled.
V
ST72XXX
DD
Optional
(note 3)
Required
R
ON
Filter
INTERNAL
RESET
EXTERNAL
RESET
0.01μF
1MΩ
WATCHDOG
ILLEGALOPCODE 5)
LVD RESET
PULSE
GENERATOR
1)
Figure 106. RESET pin protection when LVD is disabled.
V
ST72XXX
DD
R
ON
Filter
INTERNAL
RESET
USER
EXTERNAL
RESET
CIRCUIT
0.01μF
WATCHDOG
PULSE
GENERATOR
ILLEGALOPCODE 5)
Required
Note 1:
– The reset network protects the device against parasitic resets.
– The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the
device can be damaged when the ST7 generates an internal reset (LVD or watchdog).
– Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin can go
below the V max. level specified in section 13.9.1 on page 135. Otherwise the reset will not be taken into account
IL
internally.
– Because the reset circuit is designed to allow the internal RESET to be output in the RESET pin, the user must en-
sure that the current sunk on the RESET pin is less than the absolute maximum value specified for I
section 13.2.2 on page 111.
in
INJ(RESET)
Note 2: When the LVD is enabled, it is recommended not to connect a pull-up resistor or capacitor. A 10nF pull-down
capacitor is required to filter noise on the reset line.
Note 3: In case a capacitive power supply is used, it is recommended to connect a 1MΩ pull-down resistor to the RESET
pin to discharge any residual voltage induced by the capacitive effect of the power supply (this will add 5µA to the power
consumption of the MCU).
Note 4: Tips when using the LVD:
– 1. Check that all recommendations related to ICCCLK and reset circuit have been applied (see caution in Table 1
on page 7 and notes above)
– 2. Check that the power supply is properly decoupled (100nF + 10µF close to the MCU). Refer to AN1709 and
AN2017. If this cannot be done, it is recommended to put a 100nF + 1MΩ pull-down on the RESET pin.
– 3. The capacitors connected on the RESET pin and also the power supply are key to avoid any start-up marginality.
In most cases, steps 1 and 2 above are sufficient for a robust solution. Otherwise: replace 10nF pull-down on the
RESET pin with a 5µF to 20µF capacitor.”
Note 5: Please refer to “Illegal Opcode Reset” on page 107 for more details on illegal opcode reset conditions.
136/159
ST7LITE1xB
13.10 COMMUNICATION INTERFACE CHARACTERISTICS
13.10.1 SPI - Serial Peripheral Interface
Refer to I/O port characteristics for more details on
the input/output alternate function characteristics
(SS, SCK, MOSI, MISO).
Subject to general operating conditions for V
,
DD
f
, and T unless otherwise specified.
OSC
A
Symbol
Parameter
Conditions
Master
=8MHz
Min
/128
0.0625
Max
Unit
f
f
/4
CPU
2
CPU
f
f
CPU
SCK
MHz
SPI clock frequency
1/t
Slave
=8MHz
f
/2
c(SCK)
CPU
0
f
4
CPU
t
t
r(SCK)
SPI clock rise and fall time
see I/O port pin description
f(SCK)
1)
4)
t
SS setup time
Slave
Slave
(4 x T
) + 50
CPU
su(SS)
1)
t
SS hold time
120
h(SS)
1)
1)
t
t
Master
Slave
100
90
w(SCKH)
SCK high and low time
w(SCKL)
1)
t
Master
Slave
100
100
su(MI)
Data input setup time
Data input hold time
1)
t
su(SI)
1)
1)
t
Master
Slave
100
100
h(MI)
ns
t
h(SI)
1)
t
Data output access time
Data output disable time
Data output valid time
Data output hold time
Data output valid time
Data output hold time
Slave
Slave
0
120
240
120
a(SO)
1)
t
dis(SO)
1)
t
v(SO)
h(SO)
v(MO)
h(MO)
Slave (after enable edge)
1)
t
0
0
1)
1)
t
120
Master (after enable
edge)
t
Figure 107. SPI Slave Timing Diagram with CPHA=0 3)
SS
INPUT
t
t
su(SS)
c(SCK)
t
h(SS)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
t
t
w(SCKH)
w(SCKL)
t
t
t
t
dis(SO)
a(SO)
v(SO)
h(SO)
t
t
r(SCK)
f(SCK)
see
note 2
MISO
OUTPUT
INPUT
MSB OUT
see note 2
BIT6 OUT
LSB OUT
t
t
h(SI)
su(SI)
LSB IN
MSB IN
BIT1 IN
MOSI
Notes:
1. Data based on design simulation, not tested in production.
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has
its alternate function capability released. In this case, the pin status depends on the I/O port configuration.
3. Measurement points are done at CMOS levels: 0.3xV and 0.7xV
.
DD
DD
4. Depends on f
. For example, if f
=8MHz, then T
= 1/f
=125ns and t
=550ns
su(SS)
CPU
CPU
CPU
CPU
137/159
ST7LITE1xB
COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d)
Figure 108. SPI Slave Timing Diagram with CPHA=1 1)
SS
INPUT
t
t
su(SS)
c(SCK)
t
h(SS)
CPHA=1
CPOL=0
CPHA=1
CPOL=1
t
t
w(SCKH)
w(SCKL)
t
t
dis(SO)
a(SO)
t
t
h(SO)
v(SO)
t
t
r(SCK)
f(SCK)
see
note 2
see
note 2
MISO
OUTPUT
MSB OUT
BIT6 OUT
HZ
LSB OUT
t
t
h(SI)
su(SI)
MSB IN
LSB IN
BIT1 IN
MOSI
INPUT
Figure 109. SPI Master Timing Diagram 1)
SS
INPUT
t
c(SCK)
CPHA = 0
CPOL = 0
CPHA = 0
CPOL = 1
CPHA = 1
CPOL = 0
CPHA = 1
CPOL = 1
t
t
w(SCKH)
w(SCKL)
t
t
r(SCK)
f(SCK)
t
t
h(MI)
su(MI)
MISO
INPUT
MSB IN
BIT6 IN
LSB IN
t
t
v(MO)
h(MO)
LSB OUT
See note 2
MSB OUT
BIT6 OUT
See note 2
MOSI
OUTPUT
Notes:
1. Measurement points are done at CMOS levels: 0.3xV and 0.7xV
.
DD
DD
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has
its alternate function capability released. In this case, the pin status depends of the I/O port configuration.
138/159
ST7LITE1xB
13.11 10-BIT ADC CHARACTERISTICS
Subject to general operating condition for V , f
, and T unless otherwise specified.
DD OSC
A
1)
Symbol
Parameter
ADC clock frequency
Conversion voltage range
External input resistor
Conditions
Min
Typ
Max
Unit
MHz
V
f
4
ADC
2)
V
R
V
V
AIN
SSA
DDA
3)
10
kΩ
AIN
C
Internal sample and hold capacitor
Stabilization time after ADC enable
Conversion time (Sample+Hold)
6
pF
ADC
STAB
4)
t
0
µs
3.5
f
=8MHz, f
=4MHz
CPU
ADC
t
- Sample capacitor loading time
- Hold conversion time
4
10
ADC
1/f
ADC
Analog Part
Digital Part
1
I
mA
ADC
0.2
Figure 110. Typical Application with ADC
V
DD
V
T
0.6V
R
AIN
AINx
10-Bit A/D
Conversion
V
AIN
V
0.6V
T
I
C
ADC
6pF
L
1μA
ST72XXX
Notes:
1. Unless otherwise specified, typical data are based on T =25°C and V -V =5V. They are given only as design guide-
A
DD SS
lines and are not tested.
2. When V and V
pins are not available on the pinout, the ADC refers to V and V .
SS
DDA
SSA
DD
3. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10kΩ). Data
based on characterization results, not tested in production.
4. The stabilization time of the AD converter is masked by the first t
always valid.
. The first conversion after the enable is then
LOAD
Related application notes:
Understanding and minimizing ADC conversion errors (AN1636)
Software techniques for compensating ST7 ADC errors (AN1711)
139/159
ST7LITE1xB
ADC CHARACTERISTICS (Cont’d)
ADC Accuracy with V =5.0V
DD
Parameter
Total unadjusted error
Symbol
Conditions
Typ
4
Max
Unit
1)
E
6
T
O
G
D
1)
E
E
E
Offset error
3
5
1)
Gain Error
f
=8MHz, f
=4MHz
0.5
1.5
1.5
4
LSB
CPU
ADC
3)
2)
Differential linearity error
3
3)
2)
E
Integral linearity error
3
L
Notes:
1. Data based on characterization results. Not tested in production.
2. Injecting negative current on any of the analog input pins significantly reduces the accuracy of any conversion being
performed on any analog input.
Analog pins can be protected against negative injection by adding a Schottky diode (pin to ground). Injecting negative
current on digital input pins degrades ADC accuracy especially if performed on a pin close to the analog input pins.
Any positive injection current within the limits specified for I (PIN) and ΣI (PIN) in Section 13.8 does not affect the
INJ
INJ
ADC accuracy.
3. Data based on characterization results over the whole temperature range, monitored in production.
Figure 111. ADC Accuracy Characteristics with amplifier disabled
Digital Result ADCDR
E
G
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line
1023
1022
1021
V
– V
DD
SS
1LSB
= -------------------------------
IDEAL
1024
(2)
E =Total Unadjusted Error: maximum deviation
T
E
between the actual and the ideal transfer curves.
T
(3)
7
6
5
4
3
2
1
E =Offset Error: deviation between the first actual
O
transition and the first ideal one.
(1)
E =Gain Error: deviation between the last ideal
G
transition and the last actual one.
E
E
O
L
E =Differential Linearity Error: maximum deviation
D
between actual steps and the ideal one.
E =Integral Linearity Error: maximum deviation
L
E
between any actual transition and the end point
correlation line.
D
1 LSB
IDEAL
V
(LSB
)
in
IDEAL
0
1
2
3
4
5
6
7
1021 1022 1023 1024
V
V
DD
SS
140/159
ST7LITE1xB
ADC CHARACTERISTICS (Cont’d)
Figure 112. ADC Accuracy Characteristics with amplifier enabled
Digital Result ADCDR
E
G
(1) Example of an actual transfer curve
704
(2) The ideal transfer curve
(3) End point correlation line
V
– V
DD
SS
1LSB
= -------------------------------
IDEAL
1024
(2)
E =Total Unadjusted Error: maximum deviation
T
E
between the actual and the ideal transfer curves.
T
(3)
E =Offset Error: deviation between the first actual
O
transition and the first ideal one.
(1)
E =Gain Error: deviation between the last ideal
G
transition and the last actual one.
E
E
O
L
E =Differential Linearity Error: maximum deviation
D
between actual steps and the ideal one.
E =Integral Linearity Error: maximum deviation
L
E
between any actual transition and the end point
correlation line.
D
1 LSB
IDEAL
108
V
(LSB
)
in
IDEAL
0
1
2
3
4
5
6
7
701 702 703 704
430mV
V
SS
V
(OPAMP)
in
62.5mV
Note:
1. When the AMPSEL bit in the ADCDRL register is set, it is mandatory that f
be less than or equal to 2 MHz. (if
ADC
f
=8MHz. then SPEED=0, SLOW=1).
CPU
Vout (ADC input)
Vmax
Noise
Vmin
Vin
(OPAMP input)
0V
430mV
141/159
ST7LITE1xB
ADC CHARACTERISTICS (Cont’d)
Symbol
Parameter
Conditions
=3.6V
Min
3.6
0
Typ
Max
5.5
Unit
V
V
V
V
Amplifier operating voltage
V
DD(AMP)
V
V
V
V
V
350
500
DD
DD
DD
DD
DD
4)
Amplifier input voltage
mV
mV
mV
IN
=5V
0
1)
5)
Amplifier output offset voltage
=5V
200
OFFSET
=3.6V
=5V
3.5
1)
3)
Step size for monotonicity
STEP
4.89
1)
Output Voltage Response
Linearity
Linear
1)
2)
Gain factor
Amplified Analog input Gain
8
1)
Vmax
Output Linearity Max Voltage
Output Linearity Min Voltage
3.65
200
V
V
V
= 430mV,
=5V
INmax
1)
Vmin
mV
DD
Notes:
1. Data based on characterization results over the whole temperature range, not tested in production.
2. For precise conversion results it is recommended to calibrate the amplifier at the following two points:
– offset at V = 0V
INmin
– gain at full scale (for example V =430mV)
IN
3. Monotonicity guaranteed if V increases or decreases in steps of min. 5mV.
IN
4. Please refer to the Application Note AN1830 for details of TE% vs Vin.
5. Refer to the offset variation in temperature below
Amplifier output offset variation
The offset is quite sensitive to temperature varia-
tions. In order to ensure a good reliability in meas-
urements, the offset must be recalibrated periodi-
cally i.e. during power on or whenever the device
is reset depending on the customer application
and during temperature variation. The table below
gives the typical offset variation over temperature:
Typical Offset Variation (LSB)
UNIT
°C
-45
-12
-20
-7
+25
-
+90
+13
LSB
142/159
ST7LITE1xB
13.12 ANALOG COMPARATOR CHARACTERISTICS
1)
Symbol
Parameter
Conditions
Min
4.5
0
Typ
Max
Unit
V
V
Supply range
5.5
DDA
V
Comparator input voltage range
Temperature range
V
V
IN
DDA
Temp
-40
125
°C
mV
µA
V
Comparator offset error
20
offset
Analog Comparator Consumption
120
200
40
I
Analog Comparator Consumption
during power-down
DD(CMP)
pA
t
Comparator propagation delay
Startup filter duration
Stabilisation time
ns
ns
ns
propag
2)
t
500
500
startup
t
stab
13.13 PROGRAMMABLE INTERNAL VOLTAGE REFERENCE CHARACTERISTICS
1)
Symbol
Parameter
Supply range
Conditions
Min
4
Typ
Max
5.5
Unit
V
V
5
DDA
Temp
Temperature range
-40
27
125
°C
Internal Voltage
Reference Consumption
50
µA
I
t
DD(VOLTREF) Internal Voltage
Reference Consumption
during power-down
200
pA
µs
2)
Startup duration
1
startup
13.14 CURRENT BIAS CHARACTERISTICS (for Comparator and Internal Voltage Reference)
1)
Symbol
Parameter
Supply range
Conditions
Min
4.5
-40
Typ
5
Max Unit
V
5.5
V
DDA
Temp
Temperature range
27
50
125
°C
µA
Bias Consumption in run mode
IDD (Bias)
Bias Consumption during power-
down
36
pA
µs
2)
t
Startup time
1
startup
Notes:
1. Unless otherwise specified, typical data are based on T =25°C and V -V =5V. They are given only as design guide-
A
DD SS
lines and are not tested.
2. Since startup time for internal voltage reference and bias is 1 µs, comparator correct output should not be expected
before 1 µs during startup.
143/159
ST7LITE1xB
14 PACKAGE CHARACTERISTICS
In order to meet environmental requirements, ST
offers these devices in ECOPACK® packages.
These packages have a Lead-free second level in-
terconnect. The category of second Level Inter-
connect is marked on the package and on the in-
ner box label, in compliance with JEDEC Standard
JESD97. The maximum ratings related to solder-
ing conditions are also marked on the inner box la-
bel.
ECOPACK is an ST trademark. ECOPACK speci-
fications are available at: www.st.com.
14.1 PACKAGE MECHANICAL DATA
Figure 113. 16-Pin Plastic Dual In-Line Package, 300-mil Width
)
mm
Min Typ Max Min Typ Max
5.33 0.210
inches
Dim.
E
A
A1 0.38
0.015
A2
A
A1
A2 2.92 3.30 4.95 0.115 0.130 0.195
0.36 0.46 0.56 0.014 0.018 0.022
b
L
c
E1
b2 1.14 1.52 1.78 0.045 0.060 0.070
b3 0.76 0.99 1.14 0.030 0.039 0.045
b2
b
eB
e
D1
b3
c
0.20 0.25 0.36 0.008 0.010 0.014
18.67 19.18 19.69 0.735 0.755 0.775
D
D
D1 0.13
0.005
e
2.54
7.62 7.87 8.26 0.300 0.310 0.325
E1 6.10 6.35 7.11 0.240 0.250 0.280
0.100
E
L
2.92 3.30 3.81 0.115 0.130 0.150
eB
10.92
0.430
Number of Pins
16
N
Note . Values in inches are converted from mm
and rounded to 3 decimal digits.
144/159
ST7LITE1xB
PACKAGE CHARACTERISTICS (Cont’d)
Figure 114. 16-Pin Plastic Small Outline Package, 300-mil Width
D
mm
inches
h x 45°
Dim.
A
L
Min Typ Max Min Typ Max
A
2.35
2.65 0.093
0.30 0.004
0.51 0.013
0.32 0.009
10.50 0.398
7.60 0.291
10.65 0.394
0.104
0.012
0.020
0.013
0.413
0.299
0.419
C
A1
A1 0.10
a
B
C
D
E
H
e
0.33
0.23
e
B
10.10
7.40
10.00
1.27
0.050
h
α
L
0.25
0°
0.75 0.010
0.030
8°
H
E
8°
0°
0.40
1.27 0.016
0.050
Number of Pins
N
16
Figure 115. 20-Pin Plastic Dual In-Line Package, 300-mil Width
)
mm
inches
Typ
Dim.
A
A2
A
Min Typ Max
Min
M
5.33
0.2
A1
c
L
A1 0.38
0.0150
A2 2.92 3.30 4.95 0.1150 0.1299 0.1
0.36 0.46 0.56 0.0142 0.0181 0.0
b2 1.14 1.52 1.78 0.0449 0.0598 0.0
b
eB
b
D1
e
b2
c
0.20 0.25 0.36 0.0079 0.0098 0.0
24.89 26.16 26.92 0.9799 1.0299 1.0
D
D
D1 0.13
0.0051
e
2.54
0.1000
11
10
20
1
eB
10.92
0.4
E1
E1 6.10 6.35 7.11 0.2402 0.2500 0.2
L
2.92 3.30 3.81 0.1150 0.1299 0.1
Number of Pins
N
20
Note . Values in inches are converted from mm
rounded to 4 decimal digits.
145/159
ST7LITE1xB
PACKAGE CHARACTERISTICS (Cont’d)
Figure 116. 20-Pin Plastic Small Outline Package, 300-mil Width
)
mm
inches
Typ
D
h x 45×
Dim.
Min Typ Max Min
Max
L
A
2.35
2.65 0.0925
0.30 0.0039
0.51 0.0130
0.32 0.0091
13.00 0.4961
7.60 0.2913
0.1043
0.0118
0.0201
0.0126
0.5118
0.2992
A
c
A1
A1 0.10
a
B
C
D
E
e
0.33
0.23
e
B
12.60
7.40
1.27
0.0500
H
h
α
L
10.00
0.25
0°
10.65 0.3937
0.75 0.0098
0.4193
0.0295
8°
E
H
8°
0°
0.40
1.27 0.0157
0.0500
Number of Pins
N
20
Note . Values in inches are converted from mm
and rounded to 4 decimal digits.
Figure 117. 20-Lead Very thin Fine pitch Quad Flat No-Lead Package
)
mm
inches
Typ
Dim.
A
Min Typ Max Min
Ma
0.80 0.85 0.90 0.0315 0.0335 0.03
A1
A3
b
0.00 0.02 0.05
0.02
0.0008 0.002
0.0008
0.25 0.30 0.35 0.0098 0.0118 0.013
5.00 0.1969
3.10 3.25 3.35 0.1220 0.1280 0.13
6.00 0.2362
4.10 4.25 4.35 0.1614 0.1673 0.17
0.80 0.0315
0.45 0.50 0.55 0.0177 0.0197 0.02
0.08 0.0031
Number of Pins
20
D
D2
E
E2
e
L
ddd
N
Note . Values in inches are converted from mm a
rounded to 4 decimal digits.
146/159
ST7LITE1xB
Table 24. THERMAL CHARACTERISTICS
Symbol
Ratings
Value
85
Unit
DIP16/SO16
DIP20/SO20
Package thermal resistance
(junction to ambient)
85
R
°C/W
thJA
QFN20 (on 4-layer PCB)
QFN20 (on 2-layer PCB)
43
95
1)
T
Maximum junction temperature
150
300
300
°C
Jmax
DIP16/SO16
DIP20/SO20
2)
P
Power dissipation
mW
Dmax
Notes:
1. The maximum chip-junction temperature is based on technology characteristics.
2. The maximum power dissipation is obtained from the formula P = (T -T ) / R .
thJA
D
J
A
The power dissipation of an application can be defined by the user with the formula: P =P +P
where P
is the
INT
D
INT
PORT
chip internal power (I xV ) and P
is the port power dissipation depending on the ports used in the application.
PORT
DD DD
147/159
ST7LITE1xB
14.2 SOLDERING INFORMATION
In accordance with the RoHS European directive,
all STMicroelectronics packages have been con-
Backward and forward compatibility:
The main difference between Pb and Pb-free sol-
dering process is the temperature range.
verted to lead-free technology, named ECO-
TM
PACK
.
TM
– ECOPACK TQFP, SDIP, SO and QFN20
TM
■ ECOPACK packages are qualified according
to the JEDEC STD-020C compliant soldering
profile.
packages are fully compatible with Lead (Pb)
containing soldering process (see application
note AN2034)
■ Detailed information on the STMicroelectronics
– TQFP, SDIP and SO Pb-packages are compati-
ble with Lead-free soldering process, neverthe-
less it's the customer's duty to verify that the Pb-
packages maximum temperature (mentioned on
the Inner box label) is compatible with their Lead-
free soldering temperature.
TM
ECOPACK transition program is available on
www.st.com/stonline/leadfree/, with specific
technical Application notes covering the main
technical aspects related to lead-free
conversion (AN2033, AN2034, AN2035,
AN2036).
Table 25. Soldering Compatibility (wave and reflow soldering process)
Package
SDIP & PDIP
QFN
Plating material devices
Sn (pure Tin)
Pb solder paste
Pb-free solder paste
Yes
Yes
Yes
Yes *
Yes *
Yes *
Sn (pure Tin)
TQFP and SO
NiPdAu (Nickel-palladium-Gold)
* Assemblers must verify that the Pb-package maximum temperature (mentioned on the Inner box label)
is compatible with their Lead-free soldering process.
148/159
ST7LITE1xB
15 DEVICE CONFIGURATION AND ORDERING INFORMATION
Each device is available for production in user pro-
grammable versions (FLASH).
ST7FLITE1xB devices are shipped to customers
with a default program memory content (FFh).
This implies that FLASH devices have to be con-
figured by the customer using the Option Bytes.
15.1 OPTION BYTES
The two option bytes allow the hardware configu-
ration of the microcontroller to be selected.
OPT3:2 = SEC[1:0] Sector 0 size definition
These option bits indicate the size of sector 0 ac-
cording to the following table.
The option bytes can be accessed only in pro-
gramming mode (for example using a standard
ST7 programming tool).
Sector 0 Size
SEC1
SEC0
0.5k
1k
0
0
1
1
0
1
0
1
OPTION BYTE 0
2k
OPT7 = Reserved, must always be 1.
4k
OPT6 = PKG Package selection
0: 16-pin package
OPT1 = FMP_R Read-out protection
Readout protection, when selected provides a pro-
tection against program memory content extrac-
tion and against write access to Flash memory.
Erasing the option bytes when the FMP_R option
is selected will cause the whole memory to be
erased first and the device can be reprogrammed.
Refer to the ST7 Flash Programming Reference
Manual and section 4.5 on page 14 for more de-
tails
1: 20-pin package
OPT5:4 = CLKSEL Clock Source Selection
When the internal RC oscillator is not selected
(Option OSC=1), these option bits select the clock
source: resonator oscillator or external clock
Clock Source
Port C
CLKSEL
0: Read-out protection off
1: Read-out protection on
Ext. Osc Disabled/
Port C Enabled
Resonator
0
0
on PB4 Ext. Osc Enabled/
Port C Disabled
on PC0
0
1
1
1
1
0
Ext.
Clock source:
CLKIN
OPT0 = FMP_W FLASH write protection
This option indicates if the FLASH program mem-
ory is write protected.
Reserved
Warning: When this option is selected, the pro-
gram memory (and the option bit itself) can never
be erased or programmed again.
0: Write protection off
Note: When the internal RC oscillator is selected,
the CLKSEL option bits must be kept at their de-
fault value in order to select the 256 clock cycle
delay (see Section 7.5).
1: Write protection on
OPTION BYTE 0
OPTION BYTE 1
7
0
7
0
FMP FMP PLL PLL PLL32
WDG WDG
SW HALT
Res. PKG CLKSEL SEC1 SEC0
OSC LVD1 LVD0
R
W
x4x8 OFF OFF
Default
Value
1
1
1
1
0
1
0
0
1
1
1
0
1
1
1
1
149/159
ST7LITE1xB
OPTION BYTES (Cont’d)
OPTION BYTE 1
OPT3:2 = LVD[1:0] Low voltage detection selec-
tion
These option bits enable the LVD block with a se-
lected threshold as shown in Table 26.
OPT7 = PLLx4x8 PLL Factor selection.
0: PLLx4
1: PLLx8
Table 26. LVD Threshold Configuration
Configuration
LVD1 LVD0
OPT6 = PLLOFF PLL disable.
0: PLL enabled
1
1
0
0
1
0
1
0
LVD Off
1: PLL disabled (by-passed)
Highest Voltage Threshold (∼4.1V)
Medium Voltage Threshold (∼3.5V)
Lowest Voltage Threshold (∼2.8V)
OPT5 = PLL32OFF 32MHz PLL disable.
0: PLL32 enabled
1: PLL32 disabled (by-passed)
OPT1 = WDG SW Hardware or Software
Watchdog
This option bit selects the watchdog type.
0: Hardware (watchdog always enabled)
1: Software (watchdog to be enabled by software)
OPT4 = OSC RC Oscillator selection
0: RC oscillator on
1: RC oscillator off
Notes:
– 1% RC oscillator available on ST7LITE15B and
ST7LITE19B devices only
OPT0 = WDG HALT Watchdog Reset on Halt
This option bit determines if a RESET is generated
when entering HALT mode while the Watchdog is
active.
0: No Reset generation when entering Halt mode
1: Reset generation when entering Halt mode
– If the RC oscillator is selected, then to improve
clock stability and frequency accuracy, it is rec-
ommended to place a decoupling capacitor, typ-
ically 100nF, between the V and V pins as
DD
SS
close as possible to the ST7 device.
Table 27. List of valid option combinations
Operating conditions
Option Bits
V
range Clock Source
PLL
off
x4
x8
off
x4
x8
off
x4
x8
off
x4
x8
Typ f
1MHz @3.3V
OSC
PLLOFF
PLLx4x8
DD
CPU
0
0
-
1
0
-
1
0
-
1)
Internal RC 1%
4MHz @3.3V
-
2.7V - 3.3V
3.3V - 5.5V
0-4MHz
1
1
-
1
0
-
1
0
-
External clock
Internal RC 1%
External clock
4MHz
-
1MHz @5V
0
-
1
-
1
-
1)
-
8MHz @5V
0-8MHz
-
0
1
-
0
1
-
1
1
-
8 MHz
1
0
1
Note 1: Configuration available on ST7LITE15B and ST7LITE19B devices only
Note: see Clock Management Block diagram in Figure 14
150/159
ST7LITE1xB
15.2 DEVICE ORDERING INFORMATION
Figure 118. Ordering information scheme
Example:
ST7
F
LIT1xB
F
0
M
3
TR
Family
ST7 Microcontroller Family
Memory type
F: Flash
P: FASTROM
Version
10B, 15B or 19B
No. of pins
F = 20
Y = 16
Memory size
0 = 2K
1 = 4K
Package
B = DIP
M = SO
U = VFQFPN
Temperature range
6 = -40 °C to 85 °C
3 = -40 °C to 125 °C
Shipping Option
TR = Tape & Reel packing
Blank = Tube (DIP or SO) or Tray (VFQFPN)
For a list of available options (e.g. data EEPROM, package) and orderable part numbers or for
further information on any aspect of this device, please contact the ST Sales Office nearest to you.
151/159
ST7LITE1xB
ST7LITE1xB FASTROM microcontroller option list
Customer
Address
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact
Phone No
Reference/FASTROM Code*: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
*FASTROM code name is assigned by STMicroelectronics.
FASTROM code must be sent in .S19 format. .Hex extension cannot be processed.
Device Type/Memory Size/Package (check only one option):
--------------------------------- ----------------------------------------- -----------------------------------------
|
|
|
|
FASTROM DEVICE:
2K
4K
|
|
--------------------------------- ----------------------------------------- -----------------------------------------
VFQFPN20:
SO20:
PDIP20:
SO16:
|
|
|
|
|
[ ] ST7PLIT19BF0Ux
[ ] ST7PLIT19BF0Mx
[ ] ST7PLIT19BF0Bx
[ ] ST7PLIT19BY0Mx
[ ] ST7PLIT19BY0Bx
|
|
|
|
|
[ ] ST7PLIT19BF1Ux
[ ] ST7PLIT19BF1Mx
[ ] ST7PLIT19BF1Bx
[ ] ST7PLIT19BY1Mx
[ ] ST7PLIT19BY1Bx
|
|
|
|
|
PDIP16:
Warning: Addresses DEE0h, DEE1h, DEE2h and DEE3h are reserved areas for ST to program RCCR0
and RCCR1 (see section 7.1 on page 23).
Conditioning (check only one option, do not specify for DIP package) :
VFQFPN
[ ] Tape & Reel
[ ] Tray
SO
[ ] Tape & Reel
[ ] Tube
Special marking:
[ ] No
[ ] Yes "_ _ _ _ _ _ _ _ "
Authorized characters are letters, digits, '.', '-', '/' and spaces only.
Maximum character count: 8 char. max _ _ _ _ _ _ _ _
Temperature range:
[ ] -40°C to +85°C
[ ] -40°C to +125°C
[ ] Hardware activation
[ ] No Reset
Watchdog selection (WDG_SW):
[ ] Software activation
Watchdog reset on Halt (WDG_HALT): [ ] Reset
LVD reset (LVD):
[ ] Disabled
[ ] Enabled
[ ] Highest threshold
[ ] Medium threshold
[ ] Lowest threshold
Sector 0 size (SEC):
[ ] 0.5K
[ ] Disabled
[ ] 1K
[ ] 2K
[ ] 4K
Readout protection (FMP_R):
[ ] Enabled
[ ] Enabled
Flash write protection (FMP_W): [ ] Disabled
RC oscillator (OSC) :
[ ] Disabled
[ ] Enabled
Clock source selection (CKSEL):
(if OSC disabled)
[ ] External crystal / ceramic resonator:
[ ] External Clock on PB4
[ ] External Clock on PC0
PLL (PLLOFF):
[ ] Disabled
[ ] PLLx4
[ ] Enabled
[ ] PLLx8
PLL factor (PLLx4x8):
PLL32 (PLL32OFF):
[ ] Disabled
[ ] Enabled
Comments : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply operating range in the application : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Notes
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Date :
Signature :
Important note : Not all configurations are available. See Table 27 on page 150 for authorized option byte
combinations.
152/159
ST7LITE1xB
15.3 DEVELOPMENT TOOLS
Development tools for the ST7 microcontrollers in-
clude a complete range of hardware systems and
software tools from STMicroelectronics and third-
party tool suppliers. The range of tools includes
solutions to help you evaluate microcontroller pe-
ripherals, develop and debug your application, and
program your microcontrollers.
guage debugger, editor, project manager and inte-
grated programming interface.
15.3.3 Programming tools
During the development cycle, the ST7-DVP3 and
and ST7-EMU3 series emulators and the RLink
provide in-circuit programming capability for pro-
gramming the Flash microcontroller on your appli-
cation board.
15.3.1 Starter kits
ST offers complete, affordable starter kits. Starter
kits are complete hardware/software tool packag-
es that include features and samples to help you
quickly start developing your application.
ST also provides a low-cost dedicated in-circuit
programmer, the ST7-STICK, as well as ST7
Socket Boards which provide all the sockets re-
quired for programming any of the devices in a
specific ST7 sub-family on a platform that can be
used with any tool with in-circuit programming ca-
pability for ST7.
15.3.2 Development and debugging tools
Application development for ST7 is supported by
fully optimizing C Compilers and the ST7 Assem-
bler-Linker toolchain, which are all seamlessly in-
tegrated in the ST7 integrated development envi-
ronments in order to facilitate the debugging and
fine-tuning of your application. The Cosmic C
Compiler is available in a free version that outputs
up to 16KBytes of code.
For production programming of ST7 devices, ST’s
third-party tool partners also provide a complete
range of gang and automated programming solu-
tions, which are ready to integrate into your pro-
duction environment.
15.3.4 Order Codes for Development and
Programming Tools
The range of hardware tools includes full-featured
ST7-EMU3 series emulators, cost effective ST7-
DVP3 series emulators and the low-cost RLink
in-circuit debugger/programmer. These tools are
supported by the ST7 Toolset from STMicroelec-
tronics, which includes the STVD7 integrated de-
velopment environment (IDE) with high-level lan-
Table 28 below lists the ordering codes for the
ST7LITE1xB development and programming
tools. For additional ordering codes for spare parts
and accessories, refer to the online product selec-
tor at www.st.com/mcu.
15.3.5 Order codes for ST7LITE1xB development tools
Table 28. Development tool order codes for the ST7LITE1xB family
1)
MCU
In-circuit Debugger, RLink Series
Emulator
Programming Tool
ST Socket
Boards and
EPBs
Starter Kit without Starter Kit with
In-circuit
Programmer
ST7FLIT1xBF0
ST7FLIT1xBF1
ST7FLIT1xBY0
ST7FLIT1xBY1
DVP Series
EMU Series
Demo Board
Demo Board
ST7FLITE-
SK/RAIS
ST7MDT10-
ST7MDT10-
EMU3
STX-RLINK
ST7SB10-
2)
STX-RLINK
2)
4)
3)5)
3)
DVP3
ST7-STICK
123
Notes:
1. Available from ST or from Raisonance, www.raisonance.com
2. USB connection to PC
3. Add suffix /EU, /UK or /US for the power supply for your region
4. Includes connection kit for DIP16/SO16 only. See “How to order an EMU or DVP” in ST product and tool selection guide
for connection kit ordering information
5. Parallel port connection to PC
153/159
ST7LITE1xB
15.4 ST7 APPLICATION NOTES
Table 29. ST7 Application Notes
IDENTIFICATION DESCRIPTION
APPLICATION EXAMPLES
AN1658
AN1720
AN1755
AN1756
SERIAL NUMBERING IMPLEMENTATION
MANAGING THE READ-OUT PROTECTION IN FLASH MICROCONTROLLERS
A HIGH RESOLUTION/PRECISION THERMOMETER USING ST7 AND NE555
CHOOSING A DALI IMPLEMENTATION STRATEGY WITH ST7DALI
A HIGH PRECISION, LOW COST, SINGLE SUPPLY ADC FOR POSITIVE AND NEGATIVE IN-
PUT VOLTAGES
AN1812
EXAMPLE DRIVERS
SCI COMMUNICATION BETWEEN ST7 AND PC
AN 969
AN 970
AN 971
AN 972
AN 973
AN 974
AN 976
AN 979
AN 980
AN1017
AN1041
AN1042
AN1044
AN1045
AN1046
AN1047
AN1048
AN1078
AN1082
AN1083
AN1105
AN1129
SPI COMMUNICATION BETWEEN ST7 AND EEPROM
I²C COMMUNICATION BETWEEN ST7 AND M24CXX EEPROM
ST7 SOFTWARE SPI MASTER COMMUNICATION
SCI SOFTWARE COMMUNICATION WITH A PC USING ST72251 16-BIT TIMER
REAL TIME CLOCK WITH ST7 TIMER OUTPUT COMPARE
DRIVING A BUZZER THROUGH ST7 TIMER PWM FUNCTION
DRIVING AN ANALOG KEYBOARD WITH THE ST7 ADC
ST7 KEYPAD DECODING TECHNIQUES, IMPLEMENTING WAKE-UP ON KEYSTROKE
USING THE ST7 UNIVERSAL SERIAL BUS MICROCONTROLLER
USING ST7 PWM SIGNAL TO GENERATE ANALOG OUTPUT (SINUSOÏD)
ST7 ROUTINE FOR I²C SLAVE MODE MANAGEMENT
MULTIPLE INTERRUPT SOURCES MANAGEMENT FOR ST7 MCUS
ST7 S/W IMPLEMENTATION OF I²C BUS MASTER
UART EMULATION SOFTWARE
MANAGING RECEPTION ERRORS WITH THE ST7 SCI PERIPHERALS
ST7 SOFTWARE LCD DRIVER
PWM DUTY CYCLE SWITCH IMPLEMENTING TRUE 0% & 100% DUTY CYCLE
DESCRIPTION OF THE ST72141 MOTOR CONTROL PERIPHERALS REGISTERS
ST72141 BLDC MOTOR CONTROL SOFTWARE AND FLOWCHART EXAMPLE
ST7 PCAN PERIPHERAL DRIVER
PWM MANAGEMENT FOR BLDC MOTOR DRIVES USING THE ST72141
AN INTRODUCTION TO SENSORLESS BRUSHLESS DC MOTOR DRIVE APPLICATIONS
WITH THE ST72141
AN1130
AN1148
AN1149
AN1180
AN1276
AN1321
AN1325
AN1445
AN1475
AN1504
AN1602
AN1633
AN1712
AN1713
AN1753
USING THE ST7263 FOR DESIGNING A USB MOUSE
HANDLING SUSPEND MODE ON A USB MOUSE
USING THE ST7263 KIT TO IMPLEMENT A USB GAME PAD
BLDC MOTOR START ROUTINE FOR THE ST72141 MICROCONTROLLER
USING THE ST72141 MOTOR CONTROL MCU IN SENSOR MODE
USING THE ST7 USB LOW-SPEED FIRMWARE V4.X
EMULATED 16 BIT SLAVE SPI
DEVELOPING AN ST7265X MASS STORAGE APPLICATION
STARTING A PWM SIGNAL DIRECTLY AT HIGH LEVEL USING THE ST7 16-BIT TIMER
16-BIT TIMING OPERATIONS USING ST7262 OR ST7263B ST7 USB MCUS
DEVICE FIRMWARE UPGRADE (DFU) IMPLEMENTATION IN ST7 NON-USB APPLICATIONS
GENERATING A HIGH RESOLUTION SINEWAVE USING ST7 PWMART
SMBUS SLAVE DRIVER FOR ST7 I2C PERIPHERALS
SOFTWARE UART USING 12-BIT ART
154/159
ST7LITE1xB
Table 29. ST7 Application Notes
IDENTIFICATION DESCRIPTION
AN1947
ST7MC PMAC SINE WAVE MOTOR CONTROL SOFTWARE LIBRARY
GENERAL PURPOSE
AN1476
AN1526
AN1709
AN1752
LOW COST POWER SUPPLY FOR HOME APPLIANCES
ST7FLITE0 QUICK REFERENCE NOTE
EMC DESIGN FOR ST MICROCONTROLLERS
ST72324 QUICK REFERENCE NOTE
PRODUCT EVALUATION
AN 910
AN 990
AN1077
AN1086
AN1103
AN1150
AN1151
AN1278
PERFORMANCE BENCHMARKING
ST7 BENEFITS VERSUS INDUSTRY STANDARD
OVERVIEW OF ENHANCED CAN CONTROLLERS FOR ST7 AND ST9 MCUS
U435 CAN-DO SOLUTIONS FOR CAR MULTIPLEXING
IMPROVED B-EMF DETECTION FOR LOW SPEED, LOW VOLTAGE WITH ST72141
BENCHMARK ST72 VS PC16
PERFORMANCE COMPARISON BETWEEN ST72254 & PC16F876
LIN (LOCAL INTERCONNECT NETWORK) SOLUTIONS
PRODUCT MIGRATION
AN1131
AN1322
AN1365
AN1604
AN2200
MIGRATING APPLICATIONS FROM ST72511/311/214/124 TO ST72521/321/324
MIGRATING AN APPLICATION FROM ST7263 REV.B TO ST7263B
GUIDELINES FOR MIGRATING ST72C254 APPLICATIONS TO ST72F264
HOW TO USE ST7MDT1-TRAIN WITH ST72F264
GUIDELINES FOR MIGRATING ST7LITE1X APPLICATIONS TO ST7FLITE1XB
PRODUCT OPTIMIZATION
AN 982
AN1014
AN1015
AN1040
AN1070
AN1181
AN1324
AN1502
AN1529
USING ST7 WITH CERAMIC RESONATOR
HOW TO MINIMIZE THE ST7 POWER CONSUMPTION
SOFTWARE TECHNIQUES FOR IMPROVING MICROCONTROLLER EMC PERFORMANCE
MONITORING THE VBUS SIGNAL FOR USB SELF-POWERED DEVICES
ST7 CHECKSUM SELF-CHECKING CAPABILITY
ELECTROSTATIC DISCHARGE SENSITIVE MEASUREMENT
CALIBRATING THE RC OSCILLATOR OF THE ST7FLITE0 MCU USING THE MAINS
EMULATED DATA EEPROM WITH ST7 HDFLASH MEMORY
EXTENDING THE CURRENT & VOLTAGE CAPABILITY ON THE ST7265 VDDF SUPPLY
ACCURATE TIMEBASE FOR LOW-COST ST7 APPLICATIONS WITH INTERNAL RC OSCILLA-
TOR
AN1530
AN1605
AN1636
AN1828
AN1946
AN1953
AN1971
USING AN ACTIVE RC TO WAKEUP THE ST7LITE0 FROM POWER SAVING MODE
UNDERSTANDING AND MINIMIZING ADC CONVERSION ERRORS
PIR (PASSIVE INFRARED) DETECTOR USING THE ST7FLITE05/09/SUPERLITE
SENSORLESS BLDC MOTOR CONTROL AND BEMF SAMPLING METHODS WITH ST7MC
PFC FOR ST7MC STARTER KIT
ST7LITE0 MICROCONTROLLED BALLAST
PROGRAMMING AND TOOLS
AN 978
AN 983
AN 985
AN 986
AN 987
AN 988
AN 989
ST7 VISUAL DEVELOP SOFTWARE KEY DEBUGGING FEATURES
KEY FEATURES OF THE COSMIC ST7 C-COMPILER PACKAGE
EXECUTING CODE IN ST7 RAM
USING THE INDIRECT ADDRESSING MODE WITH ST7
ST7 SERIAL TEST CONTROLLER PROGRAMMING
STARTING WITH ST7 ASSEMBLY TOOL CHAIN
GETTING STARTED WITH THE ST7 HIWARE C TOOLCHAIN
155/159
ST7LITE1xB
Table 29. ST7 Application Notes
IDENTIFICATION DESCRIPTION
AN1039
AN1064
AN1071
AN1106
ST7 MATH UTILITY ROUTINES
WRITING OPTIMIZED HIWARE C LANGUAGE FOR ST7
HALF DUPLEX USB-TO-SERIAL BRIDGE USING THE ST72611 USB MICROCONTROLLER
TRANSLATING ASSEMBLY CODE FROM HC05 TO ST7
PROGRAMMING ST7 FLASH MICROCONTROLLERS IN REMOTE ISP MODE (IN-SITU PRO-
GRAMMING)
AN1179
AN1446
AN1477
AN1478
AN1527
AN1575
AN1576
AN1577
AN1601
AN1603
AN1635
AN1754
AN1796
AN1900
AN1904
AN1905
USING THE ST72521 EMULATOR TO DEBUG A ST72324 TARGET APPLICATION
EMULATED DATA EEPROM WITH XFLASH MEMORY
PORTING AN ST7 PANTA PROJECT TO CODEWARRIOR IDE
DEVELOPING A USB SMARTCARD READER WITH ST7SCR
ON-BOARD PROGRAMMING METHODS FOR XFLASH AND HDFLASH ST7 MCUS
IN-APPLICATION PROGRAMMING (IAP) DRIVERS FOR ST7 HDFLASH OR XFLASH MCUS
DEVICE FIRMWARE UPGRADE (DFU) IMPLEMENTATION FOR ST7 USB APPLICATIONS
SOFTWARE IMPLEMENTATION FOR ST7DALI-EVAL
USING THE ST7 USB DEVICE FIRMWARE UPGRADE DEVELOPMENT KIT (DFU-DK)
ST7 CUSTOMER ROM CODE RELEASE INFORMATION
DATA LOGGING PROGRAM FOR TESTING ST7 APPLICATIONS VIA ICC
FIELD UPDATES FOR FLASH BASED ST7 APPLICATIONS USING A PC COMM PORT
HARDWARE IMPLEMENTATION FOR ST7DALI-EVAL
ST7MC THREE-PHASE AC INDUCTION MOTOR CONTROL SOFTWARE LIBRARY
ST7MC THREE-PHASE BLDC MOTOR CONTROL SOFTWARE LIBRARY
SYSTEM OPTIMIZATION
AN1711
AN1827
AN2009
AN2030
SOFTWARE TECHNIQUES FOR COMPENSATING ST7 ADC ERRORS
IMPLEMENTATION OF SIGMA-DELTA ADC WITH ST7FLITE05/09
PWM MANAGEMENT FOR 3-PHASE BLDC MOTOR DRIVES USING THE ST7FMC
BACK EMF DETECTION DURING PWM ON TIME BY ST7MC
156/159
ST7LITE1xB
16 REVISION HISTORY
Date
Revision
Main changes
20-Dec-05
1
Initial release on internet
Added reset default state in bold for RESET, PC0 and PC1 in Table 1, “Device Pin Descrip-
tion,” on page 7
Changed note below Figure 9 on page 17 and the last paragraph of “ACCESS ERROR HAN-
DLING” on page 18
Modified note 3 in Table 2, “Hardware Register Map,” on page 10, changed LTICR reset val-
ue and replaced h by b for LTCSR1, ATCSR and SICSR reset values
Added note to Figure 14 on page 26
Modified caution in section 7.2 on page 23
Added note 2 in “EXTERNAL INTERRUPT CONTROL REGISTER (EICR)” on page 38 and
changed “External Interrupt Function” on page 48
Removed references to true open drain in Table 8 on page 50, Table 9 on page 51 and notes
Replaced Auto reload timer 3 by Auto reload timer 4 in section 11.2 on page 57
Modified the BA bit description in the BREAKCR register in section 11.2.6 on page 70
Changed order of Section 11.3.3.2 and section 11.3.3.3 on page 80 and removed two para-
graphs before section 11.3.4 on page 81
Modified Section 11.3.3.2
Modified bit names in the description of LTARR and LTCNTR registers in section 11.3.6 on
page 81
Added important note in section 11.6.3 on page 100 and added note to CHYST bit descrip-
tion in section 11.6.4 on page 102
Modified CINV bit description in section 11.6.4 on page 102 and Figure 62 on page 101
Changed LTCSR2 reset values in Table 2 on page 10 and in section 11.3.6 on page 81
Modified section 13.2.2 on page 111 (I values)
IO
Modified Section 13.3.1 and section 13.3.2 on page 112
Removed Vt
Modified section 13.3.4 on page 114
min value in section 13.3.3.1 on page 113
POR
20-July-06
2
Modified section 13.3.5 on page 114
Modified section 13.3.5.1 on page 115 and section 13.3.5.2 on page 117
Modified temperature range in section 13.3.5.3 on page 119
Modified section 13.4.1 on page 121
Added note in section 13.5.3 on page 124
Removed figures “PLLx4 and PLLx8 Output vs CLKIN frequency”
Updated section 13.5.4 on page 125
Modified section 13.6 on page 126
Modified Section 13.7.1 and section 13.7.2 on page 127
Modified section 13.10.1 on page 137 (t
t
t
)
su(SS), v(MO) and h(MO)
Modified Figure 108 (CPHA=1) and Figure 109 on page 138 (t
t
)
v(MO) , h(MO)
Removed empty figure “Typical I vs. V with V =V in section 13.8.1 on page 129 and
PU
DD
IN
SS”
modified note 3
Modified temperature range in section 13.8.2 on page 130
Modified section 13.9.1 on page 135
Added “related Application notes” in section 13.11 on page 139
Removed EMC protection circuitry in Figure 106 on page 136 (device works correctly without
these components)
Modified ADC accuracy table in section 13.11 on page 139
Modified temperature range in Section 13.12, Section 13.13 and section 13.14 on page 143
Modified Table 27 on page 150
Added note 3 to E and E in Table “ADC Accuracy with VDD=5.0V” on page 140
D
L
Modified section 14.2 on page 148
Modified section 15.2 on page 151 (part numbers in QFN20 package)
Updated section 15.3 on page 153
Removed QFN20 pinout and mechanical data.
Modified description of CNTR[11:0] bits in section 11.2.6 on page 72
Added “External Clock Source” on page 124 and Figure 78 on page 124
Modified Table 1.
15-Sept-06
3
157/159
ST7LITE1xB
Date
Revision
Main changes
Added QFN20 pinout with new mechanical data (Figure 3 on page 5 and Figure 117 on
page 145)
Added ST7FLI19BY1M3TR sales type in Table 1, “Supported Flash part numbers,”
27-Nov-06
4
Modifed “DEVELOPMENT TOOLS” on page 153
Added note 1 to Table 1 on page 7
Modified note 1 in section 7.1 on page 23
Added caution to section 7.5.1 on page 28
Modified section 11.2.3.6 on page 67
Modified title of Figure 48 on page 68 and added note 1
Modified Figure 49 on page 69
Modified section 11.5.3.4 on page 97 and added section 11.5.3.5 on page 97
23-April-07
5
6
Modified EOC bit description in section 11.5.6 on page 98
Modified V
parameter in section 13.7.1 on page 127
FFTB
Modified Table 28 on page 153
Modified first page
Added note 2 in Table 1, “Device Pin Description,” on page 7
Modified WDGRF bit description in section 7.6.4 on page 35
Modified note 1 in section 11.2.3.6 on page 67
Added section 13.3.6 on page 120
17-June-08
Modified CLKSEL option bits description in section 15.1 on page 149
Modified section 15.2 on page 151 and option list
158/159
ST7LITE1xB
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
liability whatsoever relating to the choice, selection or use of the ST products and services described herein.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this
document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products
or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such
third party products or services or any intellectual property contained therein.
UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS
OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT
RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE
SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN
PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT
SPECIFIED AS "AUTOMOTIVE GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK.
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
liability of ST.
ST and the ST logo are trademarks or registered trademarks of ST in various countries.
Information in this document supersedes and replaces all information previously supplied.
The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.
© 2008 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -
Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com
159/159
相关型号：
ST7F10BY0M6
8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, 5 TIMERS, SPI
STMICROELECTR
ST7F10BY0M6TR
8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, 5 TIMERS, SPI
STMICROELECTR
ST7F10BY0U3
8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, 5 TIMERS, SPI
STMICROELECTR
ST7F10BY0U3TR
8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, 5 TIMERS, SPI
STMICROELECTR
ST7F10BY0U6
8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, 5 TIMERS, SPI
STMICROELECTR
ST7F10BY0U6TR
8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, 5 TIMERS, SPI
STMICROELECTR
ST7F10BY1B3
8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, 5 TIMERS, SPI
STMICROELECTR
ST7F10BY1B3TR
8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, 5 TIMERS, SPI
STMICROELECTR
ST7F10BY1B6
8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, 5 TIMERS, SPI
STMICROELECTR
ST7F10BY1B6TR
8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, 5 TIMERS, SPI
STMICROELECTR
ST7F10BY1M3
8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, 5 TIMERS, SPI
STMICROELECTR
ST7F10BY1M3TR
8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, 5 TIMERS, SPI
STMICROELECTR
©2020 ICPDF网 联系我们和版权申明