ST7FMC2R6T6_技术文档

ST7MC1/ST7MC2

8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC,

BRUSHLESS MOTOR CONTROL, FIVE TIMERS, SPI, LINSCI

PRODUCT PREVIEW

ꢀ

Memories

– 8K to 60K dual voltage FLASH Program mem-

ory or ROM with read-out protection capabili-

ty. In-Application Programming and In-Circuit

Programming.

– 384 to 1.5K RAM

– HDFlash endurance: 100 cycles, data reten-

tion: 20 years

TQFP64

14 x 14

TQFP44

10 x 10

TQFP80

14 x 14

ꢀ

Clock, Reset And Supply Management

– Enhanced reset system

TQFP32

7 x 7

– Enhanced low voltage supervisor (LVD) for

main supply and auxiliary voltage detector

(AVD) with interrupt capability

– Clock sources: crystal/ceramic resonator os-

cillators and by-pass for external clock, clock

security system.

– Four power saving modes: Halt, Active-Halt,

Wait and Slow

Interrupt Management

– Nested interrupt controller

– 14 interrupt vectors plus TRAP and RESET

– MCES top level interrupt pin

– 16 external interrupt lines (on 3 vectors)

Up to 60 I/O Ports

– up to 60 multifunctional bidirectional I/O lines

– up to 41 alternate function lines

– up to 11 high sink outputs

SDIP56

SDIP32

ꢀ

2 Communication Interfaces

– SPI synchronous serial interface

LINSCI asynchronous serial interface

Brushless Motor Control Peripheral

– 6 high sink PWM output channels for sine-

wave or trapezoidal inverter control

– Motor safety including asynchronous emer-

gency stop and write-once registers

– 4 analog inputs for rotor position detection

(sensorless/hall/tacho/encoder)

– Permanent magnet motor coprocessor includ-

ing multiplier, programmable filters, blanking

windows and event counters

–

ꢀ

– Operational amplifier and comparator for cur-

rent/voltage mode regulation and limitation

ꢀ

Analog peripheral

5 Timers

– 10-bit ADC with 16 input pins

– Main Clock Controller with: Real time base,

Beep and Clock-out capabilities

– Configurable window watchdog timer

ꢀ

In-circuit Debug

Instruction Set

– 8-bit Data Manipulation

– Two 16-bit timers with: 2 input captures, 2 out-

put compares, external clock input, PWM and

pulse generator modes

– 8-bit PWM Auto-Reload timer with: 2 input

captures, 4 PWM outputs, output compare

and time base interrupt, external clock with

event detector

– 63 Basic Instructions

– 17 main Addressing Modes

– 8 x 8 Unsigned Multiply Instruction

– True Bit Manipulation

Development Tools

– Full hardware/software development package

ꢀ

Device Summary

Features

ST7MC1

8K

ST7MC2

Program memory - bytes

RAM (stack) - bytes

16K

24K

1024 (256)

32K

48K

60K

384 (256)

768 (256)

1024 (256)

1536 (256)

Watchdog, 16-bit Timer A, LINSCI



, 10-bit ADC, MTC, 8-bit PWM ART, ICD

SPI, 16-bit Timer B

Peripherals

-

Operating

Supply vs. Frequency

4.5 to 5.5V with f

≤8MHz

CPU

-40°C to +85°C

/ -40°C to +125°C

Temperature Range

Package

-40°C to +85 °C

TQFP64

SDIP32/TQFP32

TQFP44

SDIP56/TQFP64

TQFP80

Rev. 2.1

April 2004

1/294

This is preliminary information on a new product now in development. Details are subject to change without notice.

1

Table of Contents

1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.3 STRUCTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.4 ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.5 ICP (IN-CIRCUIT PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.6 IAP (IN-APPLICATION PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.7 RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.8 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.1 OSCILLATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.2 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.3 SYSTEM INTEGRITY MANAGEMENT (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.4 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK AND BEEPER (MCC/RTC) . 32

6 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

6.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

6.2 MASKING AND PROCESSING FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

6.3 INTERRUPTS AND LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

6.4 CONCURRENT & NESTED MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

6.5 INTERRUPT REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

6.6 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

6.7 EXTERNAL INTERRUPT CONTROL REGISTER (EICR) . . . . . . . . . . . . . . . . . . . . . . . 43

7 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

7.2 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

7.3 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

7.4 ACTIVE-HALT AND HALT MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

8 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

8.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

8.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

8.4 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

8.5 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

9 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

9.1 WINDOW WATCHDOG (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

9.2 PWM AUTO-RELOAD TIMER (ART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

9.3 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

294

9.4 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

9.5 LINSCI SERIAL COMMUNICATION INTERFACE (LIN MASTER/SLAVE) . . . . . . . . . 103

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Table of Contents

9.6 MOTOR CONTROLLER (MTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

9.7 OPERATIONAL AMPLIFIER (OA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

9.8 10-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232

10 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

10.1 CPU ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

10.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

11 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

11.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

11.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

11.3 6OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

11.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248

11.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252

11.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256

11.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257

11.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260

11.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263

11.10 TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265

11.11 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 266

11.12 MOTOR CONTROL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268

11.13 OPERATIONAL AMPLIFIER CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . 274

11.14 10-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275

12 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279

12.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279

12.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282

12.3 SOLDERING AND GLUEABILITY INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283

13 ST7MC DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . 284

13.1 FLASH OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284

13.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . 286

13.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288

13.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290

14 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293

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ST7MC1/ST7MC2

1 INTRODUCTION

The ST7MCx device is member of the ST7 micro-

controller family designed for mid-range applica-

tions with a Motor Control dedicated peripheral.

The enhanced instruction set and addressing

modes of the ST7 offer both power and flexibility to

software developers, enabling the design of highly

efficient and compact application code. In addition

to standard 8-bit data management, all ST7 micro-

controllers feature true bit manipulation, 8x8 un-

signed multiplication and indirect addressing

modes.

All devices are based on a common industry-

standard 8-bit core, featuring an enhanced instruc-

tion set and are available with FLASH, ROM or

FASTROM program memory.

Under software control, all devices can be placed

in WAIT, SLOW, ACTIVE-HALT or HALT mode,

reducing power consumption when the application

is in idle or stand-by state.

The devices feature an on-chip Debug Module

(DM) to support in-circuit debugging (ICD). For a

description of the DM registers, refer to the ST7

ICC Protocol Reference Manual.

Figure 1. Device Block Diagram

PROGRAM

MEMORY

(8K - 60K Bytes)

8-BIT CORE

ALU

RESET

CONTROL

V

PP

RAM

(384 - 1536Bytes)

V

SS

DD

LVD

AVD

OSC

1)

PH7:0

1)

PORT H

PORT G

(8-bits)

1)

OSC1

OSC2

PG7:0

(8-bits)

SCI/LIN

WATCHDOG

PWM ART

PORT A

PORT D

TIMER A

1)

PD7:0

(8-bits)

PA7:0

(8-bits)

10-BIT ADC

PORT B

V

AREF

V

SSA

PB7:0

(8-bits)

MTC VOLT INPUT

1

PORT E

1

SPI

PE5:0

(6-bits)

1

TIMER B

PORT C

PC7:0

(8-bits)

1

PORT F

MOTOR CONTROL

MCES

PF5:0

(6-bits)

1

MCC/RTC/BEEP

DEBUG MODULE

On some devices only, see Table 1, “ST7MC Device Pin Description,” on page 11

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1

ST7MC1/ST7MC2

2 PIN DESCRIPTION

Figure 2. 80-Pin TQFP 14x14 Package Pinout

PD3 / ICAP1_A / AIN13

PD2 / ICAP2_A / AIN12

PD1 (HS) / OCMP1_A

PD0 / OCMP2_A / AIN11

PH3

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

1

(HS) MCO3

(HS) MCO4

(HS) MCO5

MCES

2

ei0

3

4

PG0

5

PH2

PH1

PH0

PG1

6

PG2

7

PG3

8

PF5 (HS)

PF4 (HS)

9

OSC1

10

11

12

13

14

15

16

17

18

19

20

OSC2

VSS_1

VDD_1

PF3 (HS) / BEEP

PF2 / MCO / AIN10

PF1 / MCZEM / AIN9

PWM3 / PA0

PWM2 / (HS) PA1

PWM1 / PA2

PF0 / MCDEM / AIN8

RESET

V

AIN0 / PWM0 / PA3

ARTCLK / (HS) PA4

AIN1 / ARTIC1 / PA5

ARTIC2 / PA6

ei1

DD_0

VSS_0

VSSA

VAREF

ei2

PC7 / MCPWMW / AIN7

AIN2 / PA7

(HS) 20mA high sink capability

eix associated external interrupt vector

* Once the MTC peripheral is ON, the pin PC4 is configured to an alternate function. PC4 is no longer usable as a digital I/O

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1

ST7MC1/ST7MC2

Figure 3. 64-Pin TQFP 14x14 Package Pinout

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

PD3 / ICAP1_A / AIN13

PD2 / ICAP2_A / AIN12

PD1 (HS) / OCMP1_A

PD0 / OCMP2_A / AIN11

PF5 (HS)

(HS) MCO3

(HS) MCO4

(HS) MCO5

MCES

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

1

2

3

ei0

4

OSC1

5

PF4 (HS)

OSC2

6

V

_1

PF3 (HS) / BEEP

PF2 / MCO / AIN10

PF1 / MCZEM / AIN9

PF0 / MCDEM / AIN8

RESET

7

SS

_1

DD

8

PWM3 / PA0

PWM2 / (HS) PA1

PWM1 / PA2

9

10

11

12

13

14

15

16

V

AIN0 / PWM0 / PA3

ARTCLK / (HS) PA4

AIN1 / ARTIC1 / PA5

DD_0

ei1

V

SS_0

V

SSA

ei2

AREF

ARTIC2 / PA6

AIN2 / PA7

PC7 / MCPWMW / AIN7

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

(HS) 20mA high sink capability

eix associated external interrupt vector

* Once the MTC peripheral is ON, the pin PC4 is configured to an alternate function. PC4 is no longer usable as a digital I/O

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1

ST7MC1/ST7MC2

Figure 4. 32-Pin SDIP Package Pinouts

ICCSEL / V_PP

MCO0

1

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

PD7 (HS) / TDO

2

PD6 (HS) / RDI

MCO1

3

PD5 / AIN15 / ICCDATA

MCO2

4

PD4 / EXTCLK_A / AIN14 / ICCCLK

MCO3

5

ei0

PD3 / ICAP1_A / AIN13

MCO4

6

PD2 / ICAP2_A / MCZEM / AIN12

MCO5

7

PD1 (HS) / OCMP1_A / MCPWMV / MCDEM

MCES

8

PD0 / OCMP2_A / MCPWMW / AIN11

OSC1

9

RESET

OSC2

10

11

12

13

14

15

16

V_{DD_0}

AIN0 / PWM0 / PA3

AIN1 / ARTIC1 / PA5

MCVREF / PB0

MCIA / PB1

MCIB / PB2

MCIC / PB3

V_{SS_0}

ei1

V_AREF

PC4 / MCCREF *

OAZ / MCCFI1 / AIN6

PC3 / OAN

PC2 / OAP

ei2

(HS) 20mA high sink capability

eix associated external interrupt vector

* Once the MTC peripheral is ON, the pin PC4 is configured to an alternate function. PC4 is no longer usable as a digital I/O

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1

ST7MC1/ST7MC2

Figure 5. 56-Pin SDIP Package Pinouts

1

OCMP1_B / PE1

ICAP2_B / PE2

ICAP1_B / PE3

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

PE0 (HS) / OCMP2_B

2

V

_2

DD

3

_2

SS

4

V

/ICCSEL

PD7 (HS) / TDO

PP

5

(HS) MCO0

(HS) MCO1

(HS) MCO2

(HS) MCO3

(HS) MCO4

(HS) MCO5

PD6 (HS) / RDI

6

PD5 / AIN15 / ICCDATA

PD4 /EXTCLK_A / AIN14 / ICCCLK

7

ei0

8

PD3 / ICAP1_A / AIN13

PD2 / ICAP2_A / AIN12

PD1 (HS) / OCMP1_A

PD0 / OCMP2_A / AIN11

PF3 (HS) / BEEP

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

MCES

OSC1

PF1 / MCZEM / AIN9

PF0 / MCDEM / AIN8

RESET

OSC2

Vss_1

Vdd_1

V

PWM2 / (HS) PA1

AIN0 / PWM0 / PA3

ARTCLK / (HS) PA4

AIN1 / ARTIC1 / PA5

ARTIC2 / PA6

DD_0

V

SS_0

ei1

V

SSA

V

AREF

PC7 / MCPWMW / AIN7

PC6 / MCPWMV

MCVREF / PB0

MCIA / PB1

PC5 / MCPWMU

MCIB / PB2

PC4 / MCCREF *

OAZ / MCCFI1 / AIN6

PC3 / OAN

MCIC / PB3

MISO / PB4

AIN3 / MOSI / PB5

SCK / (HS) PB6

AIN4 / SS /(HS) PB7

PC2 / OAP

ei2

PC1 / MCCFI0/AIN5

PC0(HS)

ei2

(HS) 20mA high sink capability

eix associated external interrupt vector

* Once the MTC peripheral is ON, the pin PC4 is configured to an alternate function. PC4 is no longer usable as a digital I/O

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1

ST7MC1/ST7MC2

Figure 6. 44-Pin TQFP Package Pinouts

44 43 42 41 40 39 38 37 36 35 34

(HS) MCO3

(HS) MCO4

(HS) MCO5

MCES

PD4 /EXTCLK_A / AIN14 / ICCCLK

1

33

32

31

30

29

28

27

26

25

24

23

PD3 / ICAP1_A / AIN13

2

ei0

PD2 / ICAP2_A / MCZEM / AIN12

PD1 (HS) / OCMP1_A / MCPWMV/MCDEM

PD0 / OCMP2_A / AIN11

RESET

3

4

OSC1

5

OSC2

6

V

_1

SS

V

7

DD_0

V

_1

DD

V

8

SS_0

AIN0 / PWM0 / PA3

AIN1 / ARTIC1 / PA5

MCVREF / PB0

V

9

SSA

ei1

10

11

V

ei2

AREF

PC7 / MCPWMW / AIN7

12 13 14 15 16 17 18 19 20 21 22

(HS) 20mA high sink capability

eix associated external interrupt vector

* Once the MTC peripheral is ON, the pin PC4 is configured to an alternate function. PC4 is no longer usable as a digital I/O

9/294

1

ST7MC1/ST7MC2

Figure 7. 32-Pin TQFP 7x7 Package Pinout

32 31 30 29 28 27 26 25

(HS) MCO3

(HS) MCO4

24

23

22

21

20

19

18

17

PD3 / ICAP1_A / AIN13

1

2

3

4

5

6

7

8

PD2 / ICAP2_A / MCZEM / AIN12

PD1 (HS) / OCMP1_A / MCPWMV / MCDEM

PD0 / OCMP2_A / MCPWMW /AIN11

RESET

ei0

(HS) MCO5

MCES

OSC1

OSC2

V

DD_0

AIN0 / PWM0 / PA3

AIN1 / ARTIC1 / PA5

V

ei2

SS_0

ei1

9 10 11 12 13 14 15 16

V

AREF

(HS) 20mA high sink capability

eix associated external interrupt vector

* Once the MTC peripheral is ON, the pin PC4 is configured to an alternate function. PC4 is no longer usable as a digital I/O

10/294

1

ST7MC1/ST7MC2

PIN DESCRIPTION (Cont’d)

For external pin connection guidelines, See “ELECTRICAL CHARACTERISTICS” on page 243.

Legend / Abbreviations for Table 1:

Type:

I = input, O = output, S = supply

A = Dedicated analog input

Input level:

In/Output level: C = CMOS 0.3V /0.7V with Schmitt trigger

T

DD

T = Refer to the G&H ports Characteristics in section 11.8.1 on page 260

T

Output level:

HS = 20mA high sink (on N-buffer only)

Port and control configuration:

1)

– Input:

float = floating, wpu = weak pull-up, wpd = weak pull-down, int = interrupt , ana = analog

OD = open drain, PP = push-pull

– Output:

Refer to “I/O PORTS” on page 50 for more details on the software configuration of the I/O ports.

The RESET configuration of each pin is shown in bold which is valid as long as the device is in reset state.

Table 1. ST7MC Device Pin Description

Pin n°

Level

Port

Input

Main

function

(after

Outp

ut

2)

Pin Name

Alternate function

reset)

1

2

3

4

5

6

7

8

1

2

3

4

-

8

9

1

2

3

4

-

5

6

7

8

-

1

2

3

4

-

MCO3 (HS)

MCO4 (HS)

MCO5 (HS)

O

I

HS

X

Motor Control Output 3

Motor Control Output 4

Motor Control Output 5

MTC Emergency Stop

Port G0

HS

10

11

-

3)

MCES

C

input wpd + int

T

PG0

PG1

PG2

PG3

I/O T

X

-

Port G1

-

Port G2

-

Port G3

External clock input or Resonator os-

cillator inverter input

4)

9

5

12

5

9

5

OSC1

I

4)

10

11

12

13

6

7

8

9

13

14

15

-

6

7

8

-

10

-

6

-

OSC2

I/O

S

Resonator oscillator inverter output

Digital Ground Voltage

V

ss_1

dd_1

-

S

Digital Main Supply Voltage

Port A0 PWM Output 3

Port A1 PWM Output 2

Port A2 PWM Output 1

-

PA0/PWM3

PA1/PWM2

PA2PWM1

I/O C

X

T

14 10 16

15 11

-

I/O C HS

T

-

I/O C

T

PA3/PWM0/

AIN0

PWM Out-

put 0

ADC Ana-

log Input 0

16 12 17

17 13 18

9

-

11

-

7

-

I/O C

X

ei1

X

Port A3

PA4 (HS)/ART-

CLK

I/O C

HS

X

Port A4 PWM-ART External Clock

T

PWM-ART

ADC Analog

Port A5 Input Cap-

Input 1

PA5 / ARTIC1/

AIN1

18 14 19 10 12

8

X

ei1 X

X

T

ture 1

19 15 20

20 16

-

PA6 / ARTIC2 I/O C

X

ei1

ei1 X

X

Port A6 PWM-ART Input Capture 2

Port A7 ADC Analog Input 2

T

-

PA7/AIN2

I/O C

T

11/294

1

ST7MC1/ST7MC2

Pin n°

Level

Port

Input

Main

function

(after

Outp

ut

2)

Pin Name

Alternate function

reset)

21 17 21 11 13

9

PB0/MCVREF I/O C

X

Port B0 MTC Voltage Reference

Port B1 MTC Input A

T

22 18 22 12 14 10 PB1/MCIA

23 19 23 13 15 11 PB2/MCIB

24 20 24 14 16 12 PB3/MCIC

I/O C

Port B2 MTC Input B

Port B3 MTC Input C

SPI Master In / Slave Out

25 21 25 15

-

PB4/MISO

I/O C

X

Port B4

Data

T

SPI Master

ADC Ana-

PB5/MOSI/

AIN3

26 22 26 16

27 23 27 17

28 24 28 18

-

I/O C

X

Port B5 Out / Slave

log Input 3

T

In Data

PB6/SCK

HS

ei2

Port B6 SPI Serial Clock

T

SPI Slave

ADC Ana-

PB7/SS/AIN4 I/O C

HS

Port B7 Select (ac-

log Input 4

T

tive low)

29

30

31

32

-

PG4

PG5

PG6

PG7

PC0

I/O T

X

Port G4

Port G5

Port G6

Port G7

Port C0

MTC Cur-

T

33 25 29

I/O C

HS

ei2

T

5)

PC1/MCCFI0

/AIN5

rent Feed-

back Input

ADC Ana-

log Input 5

34 26 30

-

I/O C

X

ei2

X

Port C1

T

5)

0

35 27 31 19 17 13 PC2/OAP

36 28 32 20 18 14 PC3/OAN

I/O C

X

ei2 X

X

Port C2 OPAMP Positive Input

Port C3 OPAMP Negative Input

MTC Cur-

T

ei2

X

T

OAZ/

Opamp rent Feed-

Output back Input

ADC analog

Input 6

5)

37 29 33 21 19 15 MCCFI1 /

I/O

X

AIN6

5)

1

MTC Current Feedback

Reference

38 30 34 22 20 16 PC4/MCCREF I/O C

PC5/MCPW-

X

Port C4

9)

T

39 31 35

-

I/O C

Port C5 MTC PWM Output U

Port C6 MTC PWM Output V

MU

PC6/

MCPWMV

7)

40 32 36

-

I/O C

7)

PC7/

MTC PWM ADC Analog

7)

41 33 37 23

-

MCPWMW / I/O C

AIN7

X

Port C7

7)

T

Output W

Input 7

42 34 38 24 21 17

43 35 39 25

V

I

Analog Reference Voltage for ADC

Analog Ground Voltage

AREF

SSA

-

S

44 36 40 26 22 18

45 37 41 27 23 19

S

Digital Ground Voltage

SS_0

DD_0

S

Digital Main Supply Voltage

Top priority non maskable interrupt

46 38 42 28 24 20 RESET

I/O C

T

12/294

1

ST7MC1/ST7MC2

Pin n°

Level

Port

Input

Main

function

(after

Outp

ut

2)

Pin Name

Alternate function

reset)

PF0/

MCDEM /

AIN8

MTC De-

Port F0 magnetiza-

ADC Ana-

log Input 8

6)

47 39 43

-

I/O C

X

T

6)

tion Output

6)

PF1/MCZEM /

AIN9

MTC BEMF ADC Ana-

48 40 44

49 41

50 42 45

-

I/O C

X

Port F1

Port F2

6)

T

Output

Main Clock ADC Ana-

Out (f /2) log Input 10

log Input 9

PF2/MCO/

AIN10

-

T

osc

-

PF3/BEEP

PF4

I/O C HS

X

Port F3 Beep Signal Output

T

51 43

52 44

-

I/O C HS

Port F4

Port F5

Port H0

Port H1

Port H2

Port H3

T

PF5

I/O C HS

T

53

54

55

56

-

PH0

I/O T

T

PH1

PH2

PH3

PD0/

Timer A Output Compare 2

7)

OCMP2_A/

MCPWMW /

AIN11

MTC PWM Output W

ADC Analog Input 11

57 45 46 29 25 21

58 46 47 30 26 22

I/O C

X

Port D0

Port D1

7)

T

PD1 (HS)/

Timer A Output Compare 1

7)

OCMP1_A/

MTC PWM Output V

HS

ei0

7)

T

MCPWMV /

6)

MTC Demagnetization

MCDEM

Timer A Input Capture 2

PD2/ICAP2_A/

59 47 48 31 27 23 MCZEM5) /

AIN12

6)

I/O C

X

ei0

X

Port D2 MTC BEMF

T

ADC Analog Input 12

Timer A In-

Port D3 put Capture

1

PD3/ICAP1_A/

60 48 49 32 28 24

AIN13

ADC Analog

Input 13

ei0 X

T

Timer A External Clock

source

PD4/

61 49 50 33 29 25 EXTCLK_A/IC- I/O C

CCLK/AIN14

X

ei0

X

Port D4

T

ICC Clock Output

ADC Analog Input 14

ICC Data Input

PD5/ICCDA-

TA/AIN15

62 50 51 34 30 26

I/O C

ei0

Port D5

T

ADC Analog Input 15

63 51 52 35 31 27 PD6/RDI

64 52 53 36 32 28 PD7/TDO

I/O C

S

HS

X

Port D6 SCI Receive Data In

Port D7 SCI Transmit Data Output

Digital Ground Voltage

Digital Main Supply Voltage

Port H0

T

X

T

65 53 54

66 54 55

-

V

SS_2

DD_2

S

67

68

69

70

-

PH4

PH5

PH6

PH7

I/O T

X

T

Port H1

Port H2

Port H3

0

13/294

1

ST7MC1/ST7MC2

Pin n°

Level

Port

Input

Main

function

(after

Outp

ut

2)

Pin Name

Alternate function

reset)

PE0/

OCMP2_B

71 55 56 37

-

I/O C

HS

X

Port E0 Timer B Output Compare 2

Port E1 Timer B Output Compare 1

T

PE1/

OCMP1_B

72 56

1

38

X

T

73 57

74 58

2

3

39

40

-

PE2/ICAP2_B I/O C

PE3/ICAP1_B/ I/O C

X

Port E2 Timer B Input Capture 2

Port E3 Timer B Input Capture 1

T

PE4/

EXTCLK_B

Timer B External Clock

75 59

76 60

-

I/O C

X

Port E4

source

T

PE5

I/O C

X

Port E5

T

Must be tied low. In the programming

mode when available, this pin acts as

77 61

4

41

1

29

I

the programming voltage input V ./

V

/ICCSEL

PP

ICC mode pin. See section 11.9.2 on

page 264

78 62

79 63

80 64

5

6

7

42

43

44

2

3

4

30 MCO0 (HS)

31 MCO1 (HS)

32 MCO2 (HS)

O

HS

X

MTC Output Channel 0

MTC Output Channel 1

MTC Output Channel 2

Notes:

1. In the interrupt input column, “eiX” defines the associated external interrupt vector. If the weak pull-up

column (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input,

else the configuration is floating interrupt input.

2. If two alternate function outputs are enabled at the same time on a given pin (for instance, MCPWMV

and MCDEM on PD1 on TQFP32), the two signals will be ORed on the output pin.

4. OSC1 and OSC2 pins connect a crystal/ceramic resonator or an external source to the on-chip oscilla-

tor; see Section 1 INTRODUCTION and Section 11.5 CLOCK AND TIMING CHARACTERISTICS for

more details.

5. MCCFI can be mapped on 2 different pins on 80 ,64 and 56-pin packages. This allows:

- either to use PC1 as a standard I/O and map MCCFI on AOZ with or without using the operational am-

plifier (selected case after reset),

- or to map MCCFI on PC1 and use the amplifier for another function.

The mapping can be selected in MREF register of motor control cell. See section MOTOR CONTROL for

more details.

6. MCZEM is mapped on PF1 on 80, 64 and 56-pin packages and on PD2 on 44 and 32-pins.

MCDEM is mapped on PF0 on 80, 64 and 56-pin packages and on PD1 on 44 and 32-pin packages.

7. MCPWMV is mapped on PC6 on 80 and 64-pin packages and on PD1 on 44,and 32-pins packages.

MCPWMW is mapped on PC7 on 80, 64 and 44-pin packages and on PD0 on 32-pins package.

8. On the chip, each I/O port has 8 pads. Pads that are not bonded to external pins are in input pull-up

configuration after reset. The configuration of these pads must be kept at reset state to avoid added cur-

rent consumption.

9. Once the MTC peripheral is ON (bits CKE=1 or DAC=1 in the register MCRA), the pin PC4 is configured

to an alternate function. PC4 is no longer usable as a digital I/O.

14/294

1

ST7MC1/ST7MC2

3 REGISTER & MEMORY MAP

As shown in Figure 8, the MCU is capable of ad-

dressing 64K bytes of memories and I/O registers.

The highest address bytes contain the user reset

and interrupt vectors.

The available memory locations consist of 128

bytes of register locations, up to 2Kbytes of RAM

and up to 60Kbytes of user program memory. The

RAM space includes up to 256 bytes for the stack

from 0100h to 01FFh.

IMPORTANT: Memory locations marked as “Re-

served” must never be accessed. Accessing a re-

seved area can have unpredictable effects on the

device.

Figure 8. Memory Map

0000h

0080h

HW Registers

(see Table 2)

Short Addressing

RAM (zero page)

007Fh

0080h

00FFh

0100h

RAM

(1536/1024

768/384 Bytes)

1000h

4000h

256 Bytes Stack

60 KBytes

48 KBytes

01FFh

0200h

067Fh

0680h

16-bit Addressing

RAM

Reserved

01FFh

or 037Fh

or 047Fh

or 067Fh

0FFFh

1000h

8000h

A000h

32 KBytes

24 KBytes

Program Memory

(60K, 48K, 32K, 24K, 8K)

FFDFh

FFE0h

E000h

FFFFh

Interrupt & Reset Vectors

(see Table 8)

8 KBytes

FFFFh

As shown in Figure 9, the MCU is capable of ad-

dressing 64K bytes of memories and I/O registers.

ry. The RAM space includes up to 256 bytes for

the stack from 0100h to 01FFh.

The available memory locations consist of 128

bytes of register locations, up to 1536 bytes of

RAM and up to 60 Kbytes of user program memo-

The highest address bytes contain the user reset

and interrupt vectors.

15/294

1

ST7MC1/ST7MC2

Table 2. Hardware Register Map

Register

Label

Reset

Status

Address

Block

Register Name

Remarks

1)

0000h

0001h

0002h

PADR

PADDR

PAOR

Port A Data Register

Port A Data Direction Register

Port A Option Register

00h

R/W

Port A

00h

2)

1)

0003h

0004h

0005h

PBDR

PBDDR

PBOR

Port B Data Register

Port B Data Direction Register

Port B Option Register

00h

R/W

Port B

Port C

Port D

Port E

Port F

Port G

Port H

00h

1)

0006h

0007h

0008h

PCDR

PCDDR

PCOR

Port C Data Register

Port C Data Direction Register

Port C Option Register

00h

R/W

00h

1)

0009h

000Ah

000Bh

PDDR

PDDDR

PDOR

Port D Data Register

Port D Data Direction Register

Port D Option Register

00h

R/W

00h

1)

000Ch

000Dh

000Eh

PEDR

PEDDR

PEOR

Port E Data Register

Port E Data Direction Register

Port E Option Register

00h

R/W

2)

00h

1)

000Fh

0010h

0011h

PFDR

PFDDR

PFOR

Port F Data Register

Port F Data Direction Register

Port F Option Register

00h

R/W

00h

1)

0012h

0013h

0014h

PGDR

PGDDR

PGOR

Port G Data Register

Port G Data Direction Register

Port G Option Register

00h

R/W

00h

1)

0015h

0016h

0017h

PHDR

PHDDR

PHOR

Port H Data Register

Port H Data Direction Register

Port H Option Register

00h

R/W

00h

0018h

0019h

001Ah

001Bh

001Ch

001Dh

001Eh

001Fh

SCISR

SCIDR

SCI Status Register

SCI Data Register

SCI Baud Rate Register

SCI Control Register 1

SCI Control Register 2

SCI Control Register 3

SCI Extended Receive Prescaler Register

SCI Extended Transmit Prescaler Register

C0h

xxh

00h

xxh

00h

Read Only

R/W

SCIBRR

SCICR1

SCICR2

SCICR3

SCIERPR

SCIETPR

LINSCI

0020h

Reserved Area (1 Byte)

0021h

0022h

0023h

SPIDR

SPICR

SPICSR

SPI Data I/O Register

SPI Control Register

SPI Control/Status Register

xxh

0xh

00h

R/W

SPI

ITC

0024h

0025h

0026h

0027h

0028h

ITSPR0

ITSPR1

ITSPR2

ITSPR3

EICR

Interrupt Software Priority Register 0

Interrupt Software Priority Register 1

Interrupt Software Priority Register 2

Interrupt Software Priority Register 3

External Interrupt Control Register

FFh

00h

R/W

16/294

1

ST7MC1/ST7MC2

Register

Label

Reset

Address

Block

Register Name

Remarks

Status

0029h

FLASH

FSCR

WWDGCR

Flash Control/Status Register

00h

7Fh

R/W

Window Watchdog Control Register

002Ah

002Bh

WATCHDOG

MCC

WWDGWR Window Watchdog Window Register

002Ch

002Dh

MCCSR

MCCBCR

Main Clock Control / Status Register

Main Clock Controller: Beep Control Register

00h

R/W

002Eh

002Fh

0030h

ADCCSR

ADCDRMSB Data Register MSB

ADCDRLSB Data Register LSB

Control/Status Register

00h

R/W

Read Only

ADC

0031h

0032h

0033h

0034h

0035h

0036h

0037h

0038h

0039h

003Ah

003Bh

003Ch

003Dh

003Eh

003Fh

TACR2

TACR1

TACSR

TAIC1HR

TAIC1LR

TAOC1HR

TAOC1LR

TACHR

Timer A Control Register 2

Timer A Control Register 1

Timer A Control/Status Register

Timer A Input Capture 1 High Register

Timer A Input Capture 1 Low Register

Timer A Output Compare 1 High Register

Timer A Output Compare 1 Low Register

Timer A Counter High Register

00h

xxh

80h

00h

FFh

FCh

FFh

FCh

xxh

80h

00h

R/W

Read Only

R/W

TIMER A

Read Only

R/W

TACLR

Timer A Counter Low Register

TAACHR

TAACLR

TAIC2HR

TAIC2LR

TAOC2HR

TAOC2LR

Timer A Alternate Counter High Register

Timer A Alternate Counter Low Register

Timer A Input Capture 2 High Register

Timer A Input Capture 2 Low Register

Timer A Output Compare 2 High Register

Timer A Output Compare 2 Low Register

R/W

0040h

SIM

SICSR

System Integrity Control/Status Register

000x000x b R/W

0041h

0042h

0043h

0044h

0045h

0046h

0047h

0048h

0049h

004Ah

004Bh

004Ch

004Dh

004Eh

004Fh

TBCR2

TBCR1

TBCSR

TBIC1HR

TBIC1LR

TBOC1HR

TBOC1LR

TBCHR

Timer B Control Register 2

Timer B Control Register 1

Timer B Control/Status Register

Timer B Input Capture 1 High Register

Timer B Input Capture 1 Low Register

Timer B Output Compare 1 High Register

Timer B Output Compare 1 Low Register

Timer B Counter High Register

00h

xxh

80h

00h

FFh

FCh

FFh

FCh

xxh

80h

00h

R/W

Read Only

R/W

TIMER B

Read Only

R/W

TBCLR

Timer B Counter Low Register

TBACHR

TBACLR

TBIC2HR

TBIC2LR

TBOC2HR

TBOC2LR

Timer B Alternate Counter High Register

Timer B Alternate Counter Low Register

Timer B Input Capture 2 High Register

Timer B Input Capture 2 Low Register

Timer B Output Compare 2 High Register

Timer B Output Compare 2 Low Register

R/W

17/294

1

ST7MC1/ST7MC2

Register

Label

Reset

Status

Address

Block

Register Name

Remarks

0050h

0051h

0052h

0053h

0054h

0055h

0056h

0057h

0058h

0059h

005Ah

005Bh

005Ch

005Dh

005Eh

005Fh

0060h

0061h

0062h

0063h

0064h

0065h

0066h

0067h

0068h

0069h

006Ah

MTIM

Timer Counter High Register

Timer Counter Low Register

Capture Z_n-1Register

Capture Z_nRegister

Compare C_n+1Register

Demagnetization Register

A_nWeight Register

Prescaler & Sampling Register

Interrupt Mask Register

Interrupt Status Register

Control Register A

Control Register B

Control Register C

Phase State Register

D event Filter Register

Current feedback Filter Register

Reference Register

00h

0Fh

00h

0Fh

FFh

R/W

MTIML

MZPRV

MZREG

MCOMP

MDREG

MWGHT

MPRSR

MIMR

MISR

MCRA

MCRB

MCRC

MPHST

MDFR

MCFR

MREF

MPCR

R/W

MTC

(page 0)

PWM Control Register

MREP

Repetition Counter Register

Compare Phase W Preload Register High

Compare Phase W Preload Register Low

Compare Phase V Preload Register High

Compare Phase V Preload Register Low

Compare Phase U Preload Register High

Compare Phase U Preload Register Low

Compare Phase 0 Preload Register High

Compare Phase 0 Preload Register Low

MCPWH

MCPWL

MCPVH

MCPVL

MCPUH

MCPUL

MCP0H

MCP0L

0050h

0051h

0052h

0053h

0054h

0055h

0056h

MDTG

MPOL

MPWME

MCONF

MPAR

MZRF

Dead Time Generator Enable

Polarity Register

PWM Register

Configuration Register

Parity Register

Z event Filter Register

Sampling Clock Register

FFh

3Fh

00h

02h

00h

0Fh

00h

MTC

(page 1)

see MTC

description

MSCR

0057h to

006Ah

Reserved Area (4 Bytes)

006Bh

006Ch

006Dh

006Eh

006Fh

0070h

DMCR

DMSR

DMBK1H

DMBK1L

DMBK2H

DMBK2L

Debug Control Register

Debug Status Register

Debug Breakpoint 1 MSB Register

Debug Breakpoint 1 LSB Register

Debug Breakpoint 2 MSB Register

Debug Breakpoint 2 LSB Register

00h

10h

FFh

R/W

Read Only

R/W

DM

R/W

18/294

1

ST7MC1/ST7MC2

Register

Label

Reset

Address

Block

Register Name

Remarks

Status

0074h

0075h

0076h

0077h

0078h

PWMDCR3 PWM AR Timer Duty Cycle Register 3

PWMDCR2 PWM AR Timer Duty Cycle Register 2

PWMDCR1 PWM AR Timer Duty Cycle Register 1

PWMDCR0 PWM AR Timer Duty Cycle Register 0

00h

R/W

PWMCR

PWM AR Timer Control Register

0079h

007Ah

007Bh

PWM ART

ARTCSR

ARTCAR

ARTARR

Auto-Reload Timer Control/Status Register

Auto-Reload Timer Counter Access Register

Auto-Reload Timer Auto-Reload Register

00h

R/W

007Ch

007Dh

007Eh

ARTICCSR AR Timer Input Capture Control/Status Reg.

00h

R/W

Read Only

ARTICR1

ARTICR2

AR Timer Input Capture Register 1

AR Timer Input Capture Register 2

007Fh

OPAMP

OACSR

OPAMP Control/Status Register

00h

R/W

Legend: x=undefined, R/W=read/write

Notes:

1. The contents of the I/O port DR registers are readable only in output configuration. In input configura-

tion, the values of the I/O pins are returned instead of the DR register contents.

2. The bits associated with unavailable pins must always keep their reset value.

19/294

1

ST7MC1/ST7MC2

4 FLASH PROGRAM MEMORY

4.1 Introduction

Depending on the overall Flash memory size in the

microcontroller device, there are up to three user

sectors (see Table 3). Each of these sectors can

be erased independently to avoid unnecessary

erasing of the whole Flash memory when only a

partial erasing is required.

The ST7 dual voltage High Density Flash

(HDFlash) is a non-volatile memory that can be

electrically erased as a single block or by individu-

al sectors and programmed on a Byte-by-Byte ba-

sis using an external V supply.

PP

The first two sectors have a fixed size of 4 Kbytes

(see Figure 9). They are mapped in the upper part

of the ST7 addressing space so the reset and in-

terrupt vectors are located in Sector 0 (F000h-

FFFFh).

The HDFlash devices can be programmed and

erased off-board (plugged in a programming tool)

or on-board using ICP (In-Circuit Programming) or

IAP (In-Application Programming).

The array matrix organisation allows each sector

to be erased and reprogrammed without affecting

other sectors.

Table 3. Sectors available in Flash devices

Flash Size (bytes)

Available Sectors

4K

8K

Sector 0

Sectors 0,1

Sectors 0,1, 2

4.2 Main Features

ꢀ

Three Flash programming modes:

> 8K

– Insertion in a programming tool. In this mode,

all sectors including option bytes can be pro-

grammed or erased.

4.3.1 Read-out Protection

– ICP (In-Circuit Programming). In this mode, all

sectors including option bytes can be pro-

grammed or erased without removing the de-

vice from the application board.

– IAP (In-Application Programming) In this

mode, all sectors except Sector 0, can be pro-

grammed or erased without removing the de-

vice from the application board and while the

application is running.

ICT (In-Circuit Testing) for downloading and

executing user application test patterns in RAM

Read-out protection against piracy

Read-out protection, when selected, provides a

protection against Program Memory content ex-

traction and against write access to Flash memo-

ry.

In Flash devices, this protection is removed by re-

programming the option. In this case, the entire

program memory is first automatically erased and

the device can be reprogrammed.

ꢀ

Read-out protection selection depends on the de-

vice type:

ꢀ

– In Flash devices it is enabled and removed

through the FMP_R bit in the option byte.

Register Access Security System (RASS) to

prevent accidental programming or erasing

– In ROM devices it is enabled by mask option

specified in the Option List.

4.3 Structure

The Flash memory is organised in sectors and can

be used for both code and data storage.

Figure 9. Memory Map and Sector Address

4K

8K

10K

16K

24K

32K

48K

60K

FLASH

MEMORY SIZE

1000h

3FFFh

7FFFh

9FFFh

BFFFh

D7FFh

DFFFh

EFFFh

FFFFh

SECTOR 2

52 Kbytes

2 Kbytes 8 Kbytes 16 Kbytes 24 Kbytes 40 Kbytes

4 Kbytes

SECTOR 1

SECTOR 0

20/294

1

ST7MC1/ST7MC2

FLASH PROGRAM MEMORY (Cont’d)

4.4 ICC Interface

– ICCCLK: ICC output serial clock pin

– ICCDATA: ICC input/output serial data pin

ICC needs a minimum of 4 and up to 6 pins to be

connected to the programming tool (see Figure

10). These pins are:

– ICCSEL/V : programming voltage

PP

– OSC1(or OSCIN): main clock input for exter-

nal source (optional)

– RESET: device reset

– V : application board power supply (option-

DD

– V : device power supply ground

al, see Figure 10, Note 3)

SS

Figure 10. Typical ICC Interface

PROGRAMMING TOOL

ICC CONNECTOR

ICC Cable

APPLICATION BOARD

ICC CONNECTOR

(See Note 3)

OPTIONAL

HE10 CONNECTOR TYPE

9

7

5

6

3

1

2

(See Note 4)

10

8

4

APPLICATION

RESET SOURCE

See Note 2

10kΩ

APPLICATION

POWER SUPPLY

C

L2

L1

See Note 1

APPLICATION

I/O

ST7

Notes:

1. If the ICCCLK or ICCDATA pins are only used

as outputs in the application, no signal isolation is

necessary. As soon as the Programming Tool is

plugged to the board, even if an ICC session is not

in progress, the ICCCLK and ICCDATA pins are

not available for the application. If they are used as

inputs by the application, isolation such as a serial

resistor has to implemented in case another de-

vice forces the signal. Refer to the Programming

Tool documentation for recommended resistor val-

ues.

agement IC with open drain output and pull-up re-

sistor>1K, no additional components are needed.

In all cases the user must ensure that no external

reset is generated by the application during the

ICC session.

3. The use of Pin 7 of the ICC connector depends

on the Programming Tool architecture. This pin

must be connected when using most ST Program-

ming Tools (it is used to monitor the application

power supply). Please refer to the Programming

Tool manual.

2. During the ICC session, the programming tool

must control the RESET pin. This can lead to con-

flicts between the programming tool and the appli-

cation reset circuit if it drives more than 5mA at

high level (push pull output or pull-up resistor<1K).

A schottky diode can be used to isolate the appli-

cation RESET circuit in this case. When using a

classical RC network with R>1K or a reset man-

4. Pin 9 has to be connected to the OSC1 or OS-

CIN pin of the ST7 when the clock is not available

in the application or if the selected clock option is

not programmed in the option byte. ST7 devices

with multi-oscillator capability need to have OSC2

grounded in this case.

21/294

1

ST7MC1/ST7MC2

FLASH PROGRAM MEMORY (Cont’d)

4.5 ICP (In-Circuit Programming)

4.7 Related Documentation

To perform ICP the microcontroller must be

switched to ICC (In-Circuit Communication) mode

by an external controller or programming tool.

For details on Flash programming and ICC proto-

col, refer to the ST7 Flash Programming Refer-

ence Manual and to the ST7 ICC Protocol Refer-

ence Manual

.

Depending on the ICP code downloaded in RAM,

Flash memory programming can be fully custom-

ized (number of bytes to program, program loca-

tions, or selection serial communication interface

for downloading).

4.8 Register Description

FLASH CONTROL/STATUS REGISTER (FCSR)

When using an STMicroelectronics or third-party

programming tool that supports ICP and the spe-

cific microcontroller device, the user needs only to

implement the ICP hardware interface on the ap-

plication board (see Figure 10). For more details

on the pin locations, refer to the device pinout de-

scription.

Read/Write

Reset Value: 0000 0000 (00h)

7

0

4.6 IAP (In-Application Programming)

This register is reserved for use by Programming

Tool software. It controls the Flash programming

and erasing operations.

This mode uses a BootLoader program previously

stored in Sector 0 by the user (in ICP mode or by

plugging the device in a programming tool).

This mode is fully controlled by user software. This

allows it to be adapted to the user application, (us-

er-defined strategy for entering programming

mode, choice of communications protocol used to

fetch the data to be stored, etc.). For example, it is

possible to download code from the SPI, SCI, USB

or CAN interface and program it in the Flash. IAP

mode can be used to program any of the Flash

sectors except Sector 0, which is write/erase pro-

tected to allow recovery in case errors occur dur-

ing the programming operation.

22/294

1

ST7MC1/ST7MC2

5 SUPPLY, RESET AND CLOCK MANAGEMENT

The device includes a range of utility features for

securing the application in critical situations (for

example in case of a power brown-out), and re-

ducing the number of external components. An

overview is shown in Figure 11.

ꢀ

Reset Sequence Manager (RSM)

1 Crystal/Ceramic resonator oscillator

System Integrity Management (SI)

– Main supply Low voltage detection (LVD)

– Auxiliary Voltage detector (AVD) with interrupt

For more details, refer to dedicated parametric

section.

capability for monitoring the main supply

– Clock Security System (CSS) with the VCO of

the PLL, providing a backup safe oscillator

– Clock Detector

– PLL which can be used to multiply the fre-

quency by 2 if the clock frequency input is

8MHz

Main features

Figure 11. Clock, Reset and Supply Block Diagram

SYSTEM INTEGRITY MANAGEMENT

f

OSC

f

CLOCK SECURITY SYSTEM

f

MAIN CLOCK

CONTROLLER

WITH REALTIME

CPU

CLK

PLL

f

MTC

8Mhz

16Mhz

lock

OSC2

OSC1

CLOCK (MCC/RTC)

1/2

Safeosc

OSCILLATOR

f

OSC

DIV2 OPT

CKSEL

SICSR, page 1

VCO

EN

LO PLL

CK EN

CK

SEL

PA

GE

0

Clock Detector

RESET SEQUENCE

MANAGER

WATCHDOG

TIMER (WDG)

AVD Interrupt Request

RESET

SICSR, page 0

PA

GE

CSS

IE

AVD AVD

CSS WDG

RF

LVD

RF

(RSM)

0

IE

F

D

CSS Interrupt Request

LOW VOLTAGE

DETECTOR

(LVD)

V

SS

V

DD

AUXILIARY VOLTAGE

DETECTOR

(AVD)

23/294

1

ST7MC1/ST7MC2

5.1 OSCILLATOR

The main clock of the ST7 can be generated by a

crystal or ceramic resonator oscillator or an exter-

nal source.

Table 4. ST7 Clock Sources

Hardware Configuration

The associated hardware configurations are

shown in Table 4. Refer to the electrical character-

istics section for more details.

ST7

OSC1

OSC2

NC

External Clock Source

In this external clock mode, a clock signal (square,

sinus or triangle) with ~50% duty cycle has to drive

the OSC1 pin while the OSC2 pin is not connect-

ed.

EXTERNAL

SOURCE

Crystal/Ceramic Oscillators

This family of oscillators has the advantage of pro-

ducing a very accurate rate on the main clock of

the ST7. In this mode, the resonator and the load

capacitors have to be placed as close as possible

to the oscillator pins in order to minimize output

distortion and start-up stabilization time.

ST7

OSC1

OSC2

This oscillator is not stopped during the RESET

phase to avoid losing time in its start-up phase.

C

L2

L1

LOAD

CAPACITORS

See Electrical Characteristics for more details.

24/294

1

ST7MC1/ST7MC2

5.2 RESET SEQUENCE MANAGER (RSM)

5.2.1 Introduction

The RESET vector fetch phase duration is 2 clock

cycles.

The reset sequence manager includes three RE-

SET sources as shown in Figure 13:

Figure 12. RESET Sequence Phases

ꢀ

External RESET source pulse

Internal LVD RESET (Low Voltage Detection)

Internal WATCHDOG RESET

RESET

These sources act on the RESET pin and it is al-

ways kept low during the delay phase.

INTERNAL RESET

FETCH

Active Phase

256 or 4096 CLOCK CYCLES

VECTOR

The RESET service routine vector is fixed at ad-

dresses FFFEh-FFFFh in the ST7 memory map.

5.2.2 Asynchronous External RESET pin

The basic RESET sequence consists of 3 phases

as shown in Figure 12:

The RESET pin is both an input and an open-drain

output with integrated R

weak pull-up resistor.

ON

ꢀ

Active Phase depending on the RESET source

This pull-up has no fixed value but varies in ac-

cordance with the input voltage. It can be pulled

low by external circuitry to reset the device. See

Electrical Characteristic section for more details.

ꢀ

256 or 4096 CPU clock cycle delay (selected by

option byte)

ꢀ

RESET vector fetch

A RESET signal originating from an external

The 256 or 4096 CPU clock cycle delay allows the

oscillator to stabilise and ensures that recovery

has taken place from the Reset state. The shorter

or longer clock cycle delay should be selected by

option byte to correspond to the stabilization time

of the external oscillator used in the application.

source must have a duration of at least t

in

h(RSTL)in

order to be recognized (see Figure 14). This de-

tection is asynchronous and therefore the MCU

can enter reset state even in HALT mode.

Figure 13. Reset Block Diagram

V

DD

R

ON

INTERNAL

RESET

Filter

RESET

PULSE

GENERATOR

WATCHDOG RESET

LVD RESET

25/294

1

ST7MC1/ST7MC2

RESET SEQUENCE MANAGER (Cont’d)

The RESET pin is an asynchronous signal which

plays a major role in EMS performance. In a noisy

environment, it is recommended to follow the

guidelines mentioned in the electrical characteris-

tics section.

5.2.4 Internal Low Voltage Detector (LVD)

RESET

Two different RESET sequences caused by the in-

ternal LVD circuitry can be distinguished:

ꢀ

Power-On RESET

5.2.3 External Power-On RESET

ꢀ

Voltage Drop RESET

If the LVD is disabled by option byte, to start up the

microcontroller correctly, the user must ensure by

means of an external reset circuit that the reset

The device RESET pin acts as an output that is

pulled low when V <V (rising edge) or

DD

IT+

V

<V (falling edge) as shown in Figure 14.

DD

IT-

signal is held low until V

level specified for the selected f

is over the minimum

DD

The LVD filters spikes on V larger than t

avoid parasitic resets.

to

g(VDD)

frequency.

DD

OSC

A proper reset signal for a slow rising V

can generally be provided by an external RC net-

supply

DD

5.2.5 Internal Watchdog RESET

work connected to the RESET pin.

The RESET sequence generated by a internal

Watchdog counter overflow is shown in Figure 14.

Starting from the Watchdog counter underflow, the

device RESET pin acts as an output that is pulled

low during at least t

.

w(RSTL)out

Figure 14. RESET Sequences

V

DD

V

IT+(LVD)

IT-(LVD)

LVD

RESET

EXTERNAL

RESET

WATCHDOG

RESET

RUN

ACTIVE

PHASE

ACTIVE

PHASE

ACTIVE PHASE

t

w(RSTL)out

t

h(RSTL)in

EXTERNAL

RESET

SOURCE

RESET PIN

WATCHDOG

RESET

WATCHDOG UNDERFLOW

INTERNAL RESET (256 or 4096 T_CPU

VECTOR FETCH

)

26/294

1

ST7MC1/ST7MC2

5.3 SYSTEM INTEGRITY MANAGEMENT (SI)

The System Integrity Management block contains

the Low Voltage Detector (LVD), Auxiliary Voltage

Detector (AVD) and Clock Security System (CSS)

functions. It is managed by the SICSR register.

The LVD function is illustrated in Figure 15.

Provided the minimum V value (guaranteed for

DD

the oscillator frequency) is above V , the MCU

IT-

can only be in two modes:

5.3.1 Low Voltage Detector (LVD)

– under full software control

– in static safe reset

In these conditions, secure operation is always en-

sured for the application without the need for ex-

ternal reset hardware.

The Low Voltage Detector function (LVD) gener-

ates a static reset when the V supply voltage is

DD

below a V reference value. This means that it

IT-

secures the power-up as well as the power-down

keeping the ST7 in reset.

During a Low Voltage Detector Reset, the RESET

pin is held low, thus permitting the MCU to reset

other devices.

The V reference value for a voltage drop is lower

IT-

than the V reference value for power-on in order

IT+

to avoid a parasitic reset when the MCU starts run-

ning and sinks current on the supply (hysteresis).

Notes:

The LVD Reset circuitry generates a reset when

V

is below:

The LVD allows the device to be used without any

external RESET circuitry.

DD

– V when V is rising

IT+

DD

The LVD is an optional function which can be se-

lected by option byte.

– V when V is falling

IT-

DD

Figure 15. Low Voltage Detector vs Reset

V

DD

V

hys

V

IT+

IT-

RESET

27/294

1

ST7MC1/ST7MC2

SYSTEM INTEGRITY MANAGEMENT (Cont’d)

5.3.2 Auxiliary Voltage Detector (AVD)

In the case of a drop in voltage, the AVD interrupt

acts as an early warning, allowing software to shut

down safely before the LVD resets the microcon-

troller. See Figure 16.

The Voltage Detector function (AVD) is based on

an analog comparison between a V

and

main sup-

IT-(AVD)

V

reference value and the V

IT+(AVD)

DD

ply. The V reference value for falling voltage is

lower than the V

The interrupt on the rising edge is used to inform

IT-

reference value for rising volt-

the application that the V warning state is over.

IT+

DD

age in order to avoid parasitic detection (hystere-

sis).

If the voltage rise time t is less than 256 or 4096

CPU cycles (depending on the reset delay select-

ed by option byte), no AVD interrupt will be gener-

rv

The output of the AVD comparator is directly read-

able by the application software through a real

time status bit (AVDF) in the SICSR register. This

bit is read only.

Caution: The AVD function is active only if the

LVD is enabled through the option byte (see sec-

tion 13.1 on page 284).

ated when V

is reached.

IT+(AVD)

If t is greater than 256 or 4096 cycles then:

rv

– If the AVD interrupt is enabled before the

V

threshold is reached, then 2 AVD inter-

IT+(AVD)

rupts will be received: the first when the AVDIE

bit is set, and the second when the threshold is

reached.

5.3.2.1 Monitoring the V Main Supply

DD

If the AVD interrupt is enabled, an interrupt is gen-

– If the AVD interrupt is enabled after the V

threshold is reached then only one AVD interrupt

will occur.

IT+(AVD)

erated when the voltage crosses the V

or

IT+(AVD)

V

threshold (AVDF bit toggles).

IT-(AVD)

Figure 16. Using the AVD to Monitor V

DD

V

DD

Early Warning Interrupt

(Power has dropped, MCU not

not yet in reset)

V

hyst

V

IT+(AVD)

V

IT-(AVD)

V

IT+(LVD)

t

VOLTAGE RISE TIME

rv

IT-(LVD)

AVDF bit

0

1

0

AVD INTERRUPT

REQUEST

IF AVDIE bit = 1

INTERRUPT PROCESS

LVD RESET

28/294

1

ST7MC1/ST7MC2

SYSTEM INTEGRITY MANAGEMENT (Cont’d)

5.3.3 Clock Security System (CSS)

5.3.4 Low Power Modes

The Clock Security System (CSS) protects the

ST7 against main clock problems. To allow the in-

tegration of the security features in the applica-

tions, it is based on a PLL which can provide a

backup clock. The PLL can be enabled or disabled

by option byte or by software. It requires an 8-MHz

input clock and provides a 16-MHz output clock.

Mode

WAIT

Description

No effect on SI. CSS and AVD interrupts

cause the device to exit from Wait mode.

The CRSR register is frozen.

The CSS (including the safe oscillator) is

disabled until HALT mode is exited. The

previous CSS configuration resumes when

the MCU is woken up by an interrupt with

“exit from HALT mode” capability or from

the counter reset value when the MCU is

woken up by a RESET. The AVD remains

active, and an AVD interrupt can be used to

exit from Halt mode.

5.3.3.1 Safe Oscillator Control

HALT

The safe oscillator of the CSS block is made of a

PLL.

If the clock signal disappears (due to a broken or

disconnected resonator...) the PLL continues to

provide a lower frequency, which allows the ST7 to

perform some rescue operations.

5.3.4.1 Interrupts

Automatically, the ST7 clock source switches back

from the safe oscillator if the original clock source

recovers.

The CSS or AVD interrupt events generate an in-

terrupt if the corresponding Enable Control Bit

(CSSIE or AVDIE) is set and the interrupt mask in

the CC register is reset (RIM instruction).

5.3.3.2 Limitation detection

The automatic safe oscillator selection is notified

by hardware setting the CSSD bit of the SICSR

register. An interrupt can be generated if the CS-

SIE bit has been previously set.

Enable Exit

Control from

Exit

from

Halt

Event

Flag

Interrupt Event

Bit

Wait

These two bits are described in the SICSR register

description.

CSS event detection

(safe oscillator acti- CSSD CSSIE

vated as main clock)

1)

Yes

No

AVD event

AVDF AVDIE

Yes

Note 1: This interrupt allows to exit from active-

halt mode.

29/294

1

ST7MC1/ST7MC2

SYSTEM INTEGRITY MANAGEMENT (Cont’d)

5.3.5 Register Description

SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR, page 0)

Read/Write

is detected by the Clock Security System (CSSD

bit set). It is set and cleared by software.

0: Clock security system interrupt disabled

1: Clock security system interrupt enabled

When the PLL is disabled (PLLEN=0), the CSSIE

bit has no effect.

Reset Value: 000x 000x (00h)

7

0

AVD

IE

PAG

E

AVD LVD

RF

CSS CSS WDG

0

F

IE

D

RF

Bit 1 = CSSD Clock security system detection

This bit indicates a disturbance on the main clock

Bit 7 = PAGE SICSR Register Page Selection

This bit selects the SICSR register page. It is set

and cleared by software

0: Access to SICSR register mapped in page 0.

1: Access to SICSR register mapped in page 1.

signal (f

): the clock stops (at least for a few cy-

OSC

cles). It is set by hardware and cleared by reading

the SICSR register when the original oscillator re-

covers.

0: Safe oscillator is not active

1: Safe oscillator has been activated

When the PLL is disabled (PLLEN=0), the CSSD

bit value is forced to 0.

Bit 6 = AVDIE Voltage Detector interrupt enable

This bit is set and cleared by software. It enables

an interrupt to be generated when the AVDF flag

changes (toggles). The pending interrupt informa-

tion is automatically cleared when software enters

the AVD interrupt routine.

Bit 0 = WDGRF Watchdog reset flag

This bit indicates that the last Reset was generat-

ed by the Watchdog peripheral. It is set by hard-

ware (watchdog reset) and cleared by software

(writing zero) or an LVD Reset (to ensure a stable

cleared state of the WDGRF flag when CPU

starts).

0: AVD interrupt disabled

1: AVD interrupt enabled

Bit 5 = AVDF Voltage Detector flag

This read-only bit is set and cleared by hardware.

If the VDIE bit is set, an interrupt request is gener-

ated when the AVDF bit changes value.

Combined with the LVDRF flag information, the

flag description is given by the following table.

RESET Sources

LVDRF WDGRF

0: V over V

threshold

IT-(AVD)

DD

IT+ (AVD)

1: V under V

External RESET pin

Watchdog

0

1

0

1

X

DD

LVD

Bit 4 = LVDRF LVD reset flag

This bit indicates that the last Reset was generat-

ed by the LVD block. It is set by hardware (LVD re-

set) and cleared by software (writing zero). See

WDGRF flag description for more details. When

the LVD is disabled by OPTION BYTE, the LVDRF

bit value is undefined.

Application notes

The LVDRF flag is not cleared when another RE-

SET type occurs (external or watchdog), the

LVDRF flag remains set to keep trace of the origi-

nal failure.

In this case, a watchdog reset can be detected by

software while an external reset can not.

Bit 3 = Reserved, must be kept cleared.

Bit 2 = CSSIE Clock security syst interrupt enable

.

This bit enables the interrupt when a disturbance

30/294

1

ST7MC1/ST7MC2

SYSTEM INTEGRITY MANAGEMENT (Cont’d)

SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR, page 1)

Reset Value: 00000000 (00h)

Bit 3 = PLLEN PLL Enable

This bit enables the PLL and the clock detector. It

is set and cleared by software.

0: PLL and Clock Detector (CKD) disabled

1: PLL and Clock Detector (CKD) enabled

7

0

VCO LO

EN CK

PLL

EN

PA

GE

CK-

SEL

0

Notes:

1. During ICC session, this bit is set to 1.

2. PLL cannot be disabled if PLL clock source is

selected (CKSEL= 1).

Bit 7 = PAGE SICSR Register Page Selection

This bit selects the SICSR register page. It is set

and cleared by software

0: Access to SICSR register mapped in page 0.

1: Access to SICSR register mapped in page 1.

Bit 2 = Reserved, must be kept cleared.

Bit 6 = Reserved, must be kept cleared.

Bit 1 = CKSELClock Source Selection

This bit selects the clock source: oscillator clock or

clock from the PLL. It is set and cleared by soft-

ware. It can also be set by option byte (PLL opt)

0: Oscillator clock selected

Bit 5 = VCOEN VCO Enable

This bit is set and cleared by software.

0: VCO (Voltage Controlled Oscillator) connected

to the output of the PLL charge pump (default

mode), to obtain a 16-MHz output frequency

(with an 8-MHz input frequency).

1: PLL clock selected

Notes:

1. During ICC session, this bit is set to 1. Then,

1: VCO tied to ground in order to obtain a 10-MHz

CKSEL can be reset in order to run with f

.

OSC

frequency (f

)

vco

2. Clock from the PLL cannot be selected if the

PLL is disabled (PLLEN =0)

3. If the clock source is selected by PLL option bit,

CKSEL bit selection has no effect.

Notes:

1. During ICC session, this bit is set to 1 in order to

have an internal frequency which does not depend

on the input clock. Then, it can be reset in order to

run faster with an external oscillator.

Bit 0 = Reserved, must be kept cleared.

Bit 4 = LOCK PLL Locked

This bit is read only. It is set by hardware. It is set

automatically when the PLL reaches its operating

frequency.

0: PLL not locked

1: PLL locked

31/294

1

ST7MC1/ST7MC2

5.4

MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK AND BEEPER (MCC/RTC)

The Main Clock Controller consists of three differ-

ent functions:

external devices. It is controlled by the MCO bit in

the MCCSR register.

CAUTION: When selected, the clock out pin sus-

ꢀ

a programmable CPU clock prescaler

pends the clock during ACTIVE-HALT mode.

ꢀ

a clock-out signal to supply external devices

5.4.3

Real Time Clock Timer (RTC)

ꢀ

a real time clock timer with interrupt capability

The counter of the real time clock timer allows an

interrupt to be generated based on an accurate

real time clock. Four different time bases depend-

Each function can be used independently and si-

multaneously.

5.4.1

Programmable CPU Clock Prescaler

ing directly on f

are available. The whole

OSC2

functionality is controlled by four bits of the MCC-

SR register: TB[1:0], OIE and OIF.

The programmable CPU clock prescaler supplies

the clock for the ST7 CPU and its internal periph-

erals. It manages SLOW power saving mode (See

Section 7.2 SLOW MODE for more details).

When the RTC interrupt is enabled (OIE bit set),

the ST7 enters ACTIVE-HALT mode when the

HALT instruction is executed. See Section 7.4 AC-

TIVE-HALT AND HALT MODES for more details.

The prescaler selects the f

main clock frequen-

CPU

cy and is controlled by three bits in the MCCSR

register: CP[1:0] and SMS.

5.4.4

Beeper

5.4.2

Clock-out Capability

The clock-out capability is an alternate function of

an I/O port pin that outputs a f clock to drive

The beep function is controlled by the MCCBCR

register. It can output three selectable frequencies

on the BEEP pin (I/O port alternate function).

OSC2

Figure 17.

Main Clock Controller (MCC/RTC) Block Diagram

BC1 BC0

MCCBCR

BEEP

MCO

BEEP SIGNAL

GENERATOR

RTC

COUNTER

DIV128

MCCSR

MCO

CP0 SMS TB1 TB0 OIE OIF

MCC/RTC INTERRUPT

(AND TO MTC

PERIPHERAL)

f

CLK

OSC2

DIV 2, 4, 8, 16

DIV 2

CPU CLOCK

TO CPU AND

f

CPU

PERIPHERALS

DIV 2

f

ADC

TO MOTOR

CONTROL

PERIPHERAL

f

DIV 2, 4, 8, 16

MTC

32/294

1

ST7MC1/ST7MC2

MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont’d)

5.4.5

Low Power Modes

Bit 6:5 = CP[1:0] CPU clock prescaler

Mode

Description

These bits select the CPU clock prescaler which is

applied in the different slow modes. Their action is

conditioned by the setting of the SMS bit. These

two bits are set and cleared by software

No effect on MCC/RTC peripheral.

MCC/RTC interrupt cause the device to exit

from WAIT mode.

WAIT

No effect on MCC/RTC counter (OIE bit is

ACTIVE- set), the registers are frozen.

f

in SLOW mode

CP1

CP0

CPU

HALT

MCC/RTC interrupt cause the device to exit

from ACTIVE-HALT mode.

f

/ 2

/ 4

0

1

0

1

0

1

OSC2

MCC/RTC counter and registers are frozen.

MCC/RTC operation resumes when the

MCU is woken up by an interrupt with “exit

from HALT” capability.

/ 8

HALT

f

/ 16

OSC2

5.4.6

Bit 4 = SMS Slow mode select

This bit is set and cleared by software.

0: Normal mode. f

Interrupts

The MCC/RTC interrupt event generates an inter-

rupt if the OIE bit of the MCCSR register is set and

the interrupt mask in the CC register is not active

(RIM instruction).

=

f

OSC2

CPU

1: Slow mode. f

is given by CP1, CP0

CPU

See Section 7.2 SLOW MODE and Section 5.4

MAIN CLOCK CONTROLLER WITH REAL TIME

CLOCK AND BEEPER (MCC/RTC) for more de-

tails.

Enable Exit

Control from

Exit

from

Halt

Event

Flag

Interrupt Event

Bit

Wait

Time base overflow

event

1)

Bit 3:2 = TB[1:0] Time base control

OIF

OIE

Yes

No

These bits select the programmable divider time

base. They are set and cleared by software.

Note:

The MCC/RTC interrupt wakes up the MCU from

ACTIVE-HALT mode, not from HALT mode.

Time Base

Counter

TB1 TB0

Prescaler

f

=4MHz

f

=8MHz

OSC2

16000

32000

80000

200000

4ms

2ms

4ms

0

1

0

1

0

1

8ms

20ms

50ms

5.4.7

Register Description

10ms

25ms

MCC CONTROL/STATUS REGISTER (MCCSR)

Read/Write

Reset Value: 0000 0000 (00h

)

A modification of the time base is taken into ac-

count at the end of the current period (previously

set) to avoid an unwanted time shift. This allows to

use this time base as a real time clock.

7

0

MCO CP1 CP0 SMS TB1 TB0 OIE

OIF

Bit 1 = OIE Oscillator interrupt enable

This bit set and cleared by software.

0: Oscillator interrupt disabled

1: Oscillator interrupt enabled

This interrupt can be used to exit from ACTIVE-

HALT mode.

Bit 7 = MCO Main clock out selection

This bit enables the MCO alternate function on the

PF0 I/O port. It is set and cleared by software.

0: MCO alternate function disabled (I/O pin free for

general-purpose I/O)

1: MCO alternate function enabled (f

port)

on I/O

OSC2

When this bit is set, calling the ST7 software HALT

instruction enters the ACTIVE-HALT power saving

mode

.

Note: To reduce power consumption, the MCO

function is not active in ACTIVE-HALT mode.

33/294

1

ST7MC1/ST7MC2

MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont’d)

MCC BEEP CONTROL REGISTER (MCCBCR)

Bit 0 = OIF Oscillator interrupt flag

This bit is set by hardware and cleared by software

reading the CSR register. It indicates when set

that the main oscillator has reached the selected

elapsed time (TB1:0).

Read/Write

Reset Value: 0000 0000 (00h)

7

0

0: Timeout not reached

1: Timeout reached

AD- ADC

STS IE

0

BC1 BC0

CAUTION: The BRES and BSET instructions

must not be used on the MCCSR register to avoid

unintentionally clearing the OIF bit.

Bit 7:4 = Reserved, must be kept cleared.

Bit 3 = ADSTS A/D Converter Sample Time

Stretch

This bit is set and cleared by software to enable or

disable the A/D Converter sample time stretch fea-

ture.

0: AD sample time stretch disabled (for standard

impedance analog inputs)

1 AD sample time stretch enabled (for high imped-

ance analog inputs)

Bit 2 = ADCIE A/D Converter Interrupt Enable

This bit is set and cleared by software to enable or

disable the A/D Converter interrupt.

0: AD Interrupt disabled

1 AD Interrupt enabled

Bit 1:0 = BC[1:0] Beep control

These 2 bits select the PF1 pin beep capability.

BC1

BC0

Beep mode with f

=8MHz

OSC2

0

1

0

1

0

1

Off

~2-KHz

Output

Beep signal

~50% duty cycle

~1-KHz

~500-Hz

The beep output signal is available in ACTIVE-

HALT mode but has to be disabled to reduce the

consumption.

Table 5. Main Clock Controller Register Map and Reset Values

Address

(Hex.)

Register

Label

7

6

5

4

3

2

1

0

SICSR, page0

Reset Value

PAGE

0

VDIE

0

VDF

0

LVDRF

x

CFIE

0

CSSD

0

WDGRF

x

0040h

002Ch

002Dh

0

SICSR, page1

Reset Value

PAGE

0

VCOEN

0

LOCK

x

PLLEN

0

CKSEL

0

MCCSR

Reset Value

MCO

0

CP1

0

CP0

0

SMS

0

TB1

0

TB0

0

OIE

0

OIF

0

MCCBCR

Reset Value

ADSTS

0

ADCIE

0

BC1

0

BC0

0

34/294

1

ST7MC1/ST7MC2

6 INTERRUPTS

6.1 INTRODUCTION

each interrupt vector (see Table 6). The process-

ing flow is shown in Figure 18

The ST7 enhanced interrupt management pro-

vides the following features:

When an interrupt request has to be serviced:

– Normal processing is suspended at the end of

ꢀ

Hardware interrupts

Software interrupt (TRAP)

Nested or concurrent interrupt management

with flexible interrupt priority and level

management:

the current instruction execution.

– The PC, X, A and CC registers are saved onto

the stack.

– I1 and I0 bits of CC register are set according to

the corresponding values in the ISPRx registers

of the serviced interrupt vector.

– Up to 4 software programmable nesting levels

– Up to 16 interrupt vectors fixed by hardware

– 2 non maskable events: RESET, TRAP

– 1 maskable top level event: MCES

– The PC is then loaded with the interrupt vector of

the interrupt to service and the first instruction of

the interrupt service routine is fetched (refer to

“Interrupt Mapping” table for vector addresses).

This interrupt management is based on:

– Bit 5 and bit 3 of the CPU CC register (I1:0),

– Interrupt software priority registers (ISPRx),

The interrupt service routine should end with the

IRET instruction which causes the contents of the

saved registers to be recovered from the stack.

– Fixed interrupt vector addresses located at the

high addresses of the memory map (FFE0h to

FFFFh) sorted by hardware priority order.

Note: As a consequence of the IRET instruction,

the I1 and I0 bits will be restored from the stack

and the program in the previous level will resume.

This enhanced interrupt controller guarantees full

upward compatibility with the standard (not nest-

ed) ST7 interrupt controller.

Table 6. Interrupt Software Priority Levels

Interrupt software priority Level

I1

1

I0

0

6.2 MASKING AND PROCESSING FLOW

Level 0 (main)

Level 1

Low

0

1

The interrupt masking is managed by the I1 and I0

bits of the CC register and the ISPRx registers

which give the interrupt software priority level of

Level 2

0

Level 3 (= interrupt disable)

High

1

Figure 18. Interrupt Processing Flowchart

PENDING

INTERRUPT

Y

RESET

MCES

N

Interrupt has the same or a

lower software priority

than current one

N

I1:0

FETCH NEXT

INSTRUCTION

THE INTERRUPT

STAYS PENDING

Y

“IRET”

N

RESTORE PC, X, A, CC

FROM STACK

EXECUTE

INSTRUCTION

STACK PC, X, A, CC

LOAD I1:0 FROM INTERRUPT SW REG.

LOAD PC FROM INTERRUPT VECTOR

35/294

1

ST7MC1/ST7MC2

INTERRUPTS (Cont’d)

Servicing Pending Interrupts

This software interrupt is serviced when the TRAP

instruction is executed. It will be serviced accord-

ing to the flowchart in Figure 18 as a MCES top

level interrupt.

As several interrupts can be pending at the same

time, the interrupt to be taken into account is deter-

mined by the following two-step process:

– the highest software priority interrupt is serviced,

ꢀ

RESET

– if several interrupts have the same software pri-

ority then the interrupt with the highest hardware

priority is serviced first.

The RESET source has the highest priority in the

ST7. This means that the first current routine has

the highest software priority (level 3) and the high-

est hardware priority.

Figure 19 describes this decision process.

See the RESET chapter for more details.

Figure 19. Priority Decision Process

PENDING

INTERRUPTS

Maskable Sources

Maskable interrupt vector sources can be serviced

if the corresponding interrupt is enabled and if its

own interrupt software priority (in ISPRx registers)

is higher than the one currently being serviced (I1

and I0 in CC register). If any of these two condi-

tions is false, the interrupt is latched and thus re-

mains pending.

Different

Same

SOFTWARE

PRIORITY

HIGHEST SOFTWARE

PRIORITY SERVICED

ꢀ

MCES (MTC Emergency Stop)

HIGHEST HARDWARE

PRIORITY SERVICED

This hardware interrupt occurs when a specific

edge is detected on the dedicated MCES pin or

when an error is detected by the micro in the motor

speed measurement.

When an interrupt request is not serviced immedi-

ately, it is latched and then processed when its

software priority combined with the hardware pri-

ority becomes the highest one.

ꢀ

External Interrupts

External interrupts allow the processor to exit from

HALT low power mode.

External interrupt sensitivity is software selectable

through the External Interrupt Control register

(EICR).

External interrupt triggered on edge will be latched

and the interrupt request automatically cleared

upon entering the interrupt service routine.

If several input pins of a group connected to the

same interrupt line are selected simultaneously,

these will be logically ORed.

Note 1: The hardware priority is exclusive while

the software one is not. This allows the previous

process to succeed with only one interrupt.

Note 2: RESET, TRAP and MCES can be consid-

ered as having the highest software priority in the

decision process.

Different Interrupt Vector Sources

Two interrupt source types are managed by the

ST7 interrupt controller: the non-maskable type

(RESET, TRAP) and the maskable type (external

or from internal peripherals).

ꢀ

Peripheral Interrupts

Usually the peripheral interrupts cause the MCU to

exit from HALT mode except those mentioned in

the “Interrupt Mapping” table.

A peripheral interrupt occurs when a specific flag

is set in the peripheral status registers and if the

corresponding enable bit is set in the peripheral

control register.

The general sequence for clearing an interrupt is

based on an access to the status register followed

by a read or write to an associated register.

Note: The clearing sequence resets the internal

latch. A pending interrupt (i.e. waiting for being

serviced) will therefore be lost if the clear se-

quence is executed.

Non-Maskable Sources

These sources are processed regardless of the

state of the I1 and I0 bits of the CC register (see

Figure 18). After stacking the PC, X, A and CC

registers (except for RESET), the corresponding

vector is loaded in the PC register and the I1 and

I0 bits of the CC are set to disable interrupts (level

3). These sources allow the processor to exit

HALT mode.

ꢀ

TRAP (Non Maskable Software Interrupt)

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1

ST7MC1/ST7MC2

INTERRUPTS (Cont’d)

6.3 INTERRUPTS AND LOW POWER MODES

6.4 CONCURRENT & NESTED MANAGEMENT

All interrupts allow the processor to exit the WAIT

low power mode. On the contrary, only external

and other specified interrupts allow the processor

to exit from the HALT modes (see column “Exit

from HALT” in “Interrupt Mapping” table). When

several pending interrupts are present while exit-

ing HALT mode, the first one serviced can only be

an interrupt with exit from HALT mode capability

and it is selected through the same decision proc-

ess shown in Figure 19.

The following Figure 20 and Figure 21 show two

different interrupt management modes. The first is

called concurrent mode and does not allow an in-

terrupt to be interrupted, unlike the nested mode in

Figure 21. The interrupt hardware priority is given

in this order from the lowest to the highest: MAIN,

IT4, IT3, IT2, IT1, IT0, MCES. The software priority

is given for each interrupt.

Warning: A stack overflow may occur without no-

tifying the software of the failure.

Note: If an interrupt, that is not able to Exit from

HALT mode, is pending with the highest priority

when exiting HALT mode, this interrupt is serviced

after the first one serviced.

Figure 20. Concurrent Interrupt Management

SOFTWARE

PRIORITY

LEVEL

I1

I0

MCES

3

1 1

IT0

3

IT1

3

IT2

3

IT3

3

RIM

IT4

3

MAIN

3/0

11 / 10

10

Figure 21. Nested Interrupt Management

SOFTWARE

PRIORITY

LEVEL

I1

I0

MCES

3

1 1

0 0

0 1

1 1

IT0

3

IT1

IT2

2

IT2

1

IT3

3

RIM

IT4

3

MAIN

3/0

11 / 10

10

37/294

1

ST7MC1/ST7MC2

INTERRUPTS (Cont’d)

6.5 INTERRUPT REGISTER DESCRIPTION

INTERRUPT SOFTWARE PRIORITY REGIS-

TERS (ISPRX)

CPU CC REGISTER INTERRUPT BITS

Read/Write

Read/Write (bit 7:4 of ISPR3 are read only)

Reset Value: 1111 1111 (FFh)

Reset Value: 111x 1010 (xAh)

7

0

7

0

ISPR0

ISPR1

I1_3 I0_3 I1_2 I0_2 I1_1 I0_1 I1_0 I0_0

I1_7 I0_7 I1_6 I0_6 I1_5 I0_5 I1_4 I0_4

1

I1

H

I0

N

Z

C

Bit 5, 3 = I1, I0 Software Interrupt Priority

ISPR2 I1_11 I0_11 I1_10 I0_10 I1_9 I0_9 I1_8 I0_8

These two bits indicate the current interrupt soft-

ware priority.

ISPR3

1

I1_13 I0_13 I1_12 I0_12

Interrupt Software Priority Level

I1

1

I0

0

Level 0 (main)

Level 1

Low

These four registers contain the interrupt software

priority of each interrupt vector.

0

1

Level 2

0

– Each interrupt vector (except RESET and TRAP)

has corresponding bits in these registers where

its own software priority is stored. This corre-

spondance is shown in the following table.

Level 3 (= interrupt disable*)

High

1

These two bits are set/cleared by hardware when

entering in interrupt. The loaded value is given by

the corresponding bits in the interrupt software pri-

ority registers (ISPRx).

Vector address

ISPRx bits

FFFBh-FFFAh

FFF9h-FFF8h

...

I1_0 and I0_0 bits*

I1_1 and I0_1 bits

...

They can be also set/cleared by software with the

RIM, SIM, HALT, WFI, IRET and PUSH/POP in-

structions (see “Interrupt Dedicated Instruction

Set” table).

FFE1h-FFE0h

I1_13 and I0_13 bits

*Note: MCES, TRAP and RESET events can in-

terrupt a level 3 program.

– Each I1_x and I0_x bit value in the ISPRx regis-

ters has the same meaning as the I1 and I0 bits

in the CC register.

– Level 0 can not be written (I1_x=1, I0_x=0). In

this case, the previously stored value is kept. (ex-

ample: previous=CFh, write=64h, result=44h)

The RESET, TRAP and MCES vectors have no

software priorities. When one is serviced, the I1

and I0 bits of the CC register are both set.

*Note: Bits in the ISPRx registers which corre-

spond to the MCES can be read and written but

they are not significant in the interrupt process

management.

Caution: If the I1_x and I0_x bits are modified

while the interrupt x is executed the following be-

haviour has to be considered: If the interrupt x is

still pending (new interrupt or flag not cleared) and

the new software priority is higher than the previ-

ous one, the interrupt x is re-entered. Otherwise,

the software priority stays unchanged up to the

next interrupt request (after the IRET of the inter-

rupt x).

38/294

1

ST7MC1/ST7MC2

INTERRUPTS (Cont’d)

Table 7. Dedicated Interrupt Instruction Set

Instruction

New Description

Entering Halt mode

Function/Example

I1

H

I0

N

Z

C

HALT

IRET

JRM

1

0

Interrupt routine return

Jump if I1:0=11 (level 3)

Jump if I1:0<>11

Pop CC, A, X, PC

I1:0=11 ?

I1

H

I0

N

Z

C

JRNM

POP CC

RIM

I1:0<>11 ?

Pop CC from the Stack

Enable interrupt (level 0 set)

Disable interrupt (level 3 set)

Software trap

Mem => CC

I1

1

H

I0

0

N

Z

C

Load 10 in I1:0 of CC

Load 11 in I1:0 of CC

Software NMI

SIM

1

TRAP

WFI

1

Wait for interrupt

1

0

Note: During the execution of an interrupt routine, the HALT, POPCC, RIM, SIM and WFI instructions change the current

software priority up to the next IRET instruction or one of the previously mentioned instructions.

39/294

1

ST7MC1/ST7MC2

INTERRUPTS (Cont’d)

Table 8. Interrupt Mapping

Exit

Source

Block

Register Priority

Address

Vector

N°

Description

from

Label

Order

1)

HALT

RESET

TRAP

Reset

yes

no

FFFEh-FFFFh

FFFCh-FFFDh

N/A

Software interrupt

Motor Control Emergency Stop

or Speed error interrupt

MISR

MCRC

0

1

MCES

no

FFFAh-FFFBh

FFF8h-FFF9h

Highest

Priority

MCC/RTC

CSS

Main clock controller time base interrupt

Safe oscillator activation interrupt

MCCSR

SICSR

yes

2

3

ei0

ei1

ei2

External interrupt port

yes

no

FFF6h-FFF7h

FFF4h-FFF5h

FFF2h-FFF3h

FFF0h-FFF1h

FFEEh-FFEFh

FFECh-FFEDh

FFEAh-FFEBh

FFE8h-FFE9h

FFE6h-FFE7h

FFE4h-FFE5h

External interrupt port

N/A

4

External interrupt port

5

Event U or Current Loop or Sampling Out

Event R or Event Z

6

MTC

MISR

no

7

Event C or Event D

no

8

SPI

SPI peripheral interrupts

TIMER A peripheral interrupts

TIMER B peripheral interrupts

LINSCI Peripheral interrupts

SPICSR

TASR

yes

no

9

TIMER A

TIMER B

LINSCI

10

11

TBSR

no

Lowest

Priority

SCISR

no

AVD/

ADC

Auxiliary Voltage detector interrupt

ADC End of conversion interrupt

SICSR

ADCSR

12

13

yes

no

FFE2h-FFE3h

FFE0h-FFE1h

PWM ART

PWM ART overflow interrupt

ARTCSR

Note 1. Valid for HALT and ACTIVE-HALT modes except for the MCC/RTC or CSS interrupt source which exits from

ACTIVE-HALT mode only.

40/294

1

ST7MC1/ST7MC2

INTERRUPTS (Cont’d)

6.6 EXTERNAL INTERRUPTS

The pending interrupts are cleared writing a differ-

ent value in the ISx[1:0], IPA or IPB bits of the

EICR.

Each external interrupt source can be generated

on four (or five) different events on the pin:

ꢀ

Falling edge

Rising edge

Falling and rising edge

Falling edge and low level

Rising edge and high level (only for ei0 and ei2)

Note: External interrupts are masked when an I/O

(configured as input interrupt) of the same inter-

rupt vector is forced to V

.

SS

6.6.1 I/O PORT INTERRUPT SENSITIVITY

The external interrupt sensitivity is controlled by

the IPA, IPB and ISxx bits of the EICR register

(Figure 22). This control allows to have up to 4 fully

independent external interrupt source sensitivities.

To guarantee correct functionality, the sensitivity

bits in the EICR register can be modified only

when the I1 and I0 bits of the CC register are both

set to 1 (level 3).

41/294

1

ST7MC1/ST7MC2

INTERRUPTS (Cont’d)

Figure 22. External Interrupt Control bits

EICR

IS30 IS31

PORT D [6:4] INTERRUPTS

PDOR.6

PDDDR.6

SENSITIVITY

CONTROL

PD6

PD5

PD6

ei0 INTERRUPT SOURCE

PD4

IPA BIT

EICR

PORT D [3:1] INTERRUPTS

IS30

IS31

PDOR.3

PDDDR.3

SENSITIVITY

CONTROL

PD3

PD2

PD1

ei0 INTERRUPT SOURCE

PD3

EICR

PORT A [7:3] INTERRUPTS

IS20

IS21

PAOR.7

PADDR.7

SENSITIVITY

CONTROL

PA7

ei1 INTERRUPT SOURCE

PA6

PA5

PA3

EICR

PORT C [3:1] INTERRUPTS

IS10

IS11

PCOR.3

PCDDR.3

SENSITIVITY

CONTROL

PC3

ei2 INTERRUPT SOURCE

PC2

PC1

IPB BIT

EICR

PORT C0, PB[7:6] INTERRUPTS

IS10

IS11

PCOR.0

PCDDR.0

SENSITIVITY

CONTROL

PC0

ei2 INTERRUPT SOURCE

PC0

PB7

PB6

42/294

1

ST7MC1/ST7MC2

INTERRUPTS (Cont’d)

6.7 EXTERNAL INTERRUPT CONTROL REGISTER (EICR)

Read/Write

These 2 bits can be written only when I1 and I0 of

the CC register are both set to 1 (level 3).

Reset Value: 0000 0000 (00h)

Bit 5 = IPB Interrupt polarity for port C

This bit is used to invert the sensitivity of the port B

[3:0] external interrupts. It can be set and cleared

by software only when I1 and I0 of the CC register

are both set to 1 (level 3).

7

0

IS11 IS10 IPB IS21 IS20 IS31 IS30 IPA

0: No sensitivity inversion

1: Sensitivity inversion

Bit 7:6 = IS1[1:0] ei2 sensitivity

The interrupt sensitivity, defined using the IS1[1:0]

bits, is applied to the following external interrupts:

- ei2 (port C3..1)

Bit 4:3= IS2[1:0] ei1sensitivity

The interrupt sensitivity, defined using the IS2[1:0]

bits, is applied to the following external interrupts:

- ei1 (port A3, A5...A7)

External Interrupt Sensitivity

IS11 IS10

IPB bit =0

IPB bit =1

Falling edge &

low level

Rising edge

& high level

0

IS21 IS20

External Interrupt Sensitivity

0

1

0

1

Rising edge only

Falling edge only

Rising edge only

0

1

0

1

0

1

Falling edge & low level

Rising edge only

Rising and falling edge

Falling edge only

Rising and falling edge

- ei2 (port C0, B7..6)

IS11 IS10

External Interrupt Sensitivity

Bit 2:1= IS3[1:0] ei0sensitivity

The interrupt sensitivity, defined using the IS2[1:0]

bits, is applied to the following external interrupts:

0

1

0

1

0

1

Falling edge & low level

Rising edge only

Falling edge only

Rising and falling edge

43/294

1

ST7MC1/ST7MC2

EXTERNAL INTERRUPT CONTROL REGISTER (EICR) (Cont’d)

- ei0 (port D5..3)

Bit 0= IPA Interrupt polarity for port A

External Interrupt Sensitivity

This bit is used to invert the sensitivity of the port A

[3:0] external interrupts. It can be set and cleared

by software only when I1 and I0 of the CC register

are both set to 1 (level 3).

IS31 IS30

IPA bit =0

IPA bit =1

Falling edge &

low level

Rising edge

& high level

0

0: No sensitivity inversion

1: Sensitivity inversion

0

1

0

1

Rising edge only

Falling edge only

Rising edge only

Rising and falling edge

- ei0 (port D2..0)

IS31 IS30

External Interrupt Sensitivity

0

1

0

1

0

1

Falling edge & low level

Rising edge only

Falling edge only

Rising and falling edge

These 2 bits can be written only when I1 and I0 of

the CC register are both set to 1 (level 3).

44/294

1

ST7MC1/ST7MC2

INTERRUPTS (Cont’d)

Table 9. Nested Interrupts Register Map and Reset Values

Address

(Hex.)

Register

Label

7

6

5

4

3

2

1

0

ei1

ei0

MCC + SI

MCES

ei2

0024h

0025h

0026h

I1_3

1

I0_3

1

I1_2

1

I0_2

1

I1_1

1

I0_1

1

ISPR0

Reset Value

1

MTC C/D

MTC R/Z

MTC U/CL

I1_7

1

I0_7

1

I1_6

1

I0_6

1

I1_5

1

I0_5

1

I1_4

1

I0_4

1

ISPR1

Reset Value

SCI

TIMER B

TIMER A

SPI

I1_11

1

I0_11

1

I1_10

1

I0_10

1

I1_9

1

I0_9

1

I1_8

1

I0_8

1

ISPR2

Reset Value

PWMART

AVD

0027h

0028h

I1_15

1

I0_15

1

I1_14

1

I0_14

1

I1_13

1

I0_13

1

I1_12

1

I0_12

1

ISPR3

Reset Value

EICR

Reset Value

IS11

0

IS10

0

IPB

0

IS21

0

IS20

0

IPA

0

45/294

1

ST7MC1/ST7MC2

7 POWER SAVING MODES

7.1 INTRODUCTION

7.2 SLOW MODE

To give a large measure of flexibility to the applica-

tion in terms of power consumption, four main

power saving modes are implemented in the ST7

(see Figure 23): SLOW, WAIT (SLOW WAIT), AC-

TIVE HALT and HALT.

This mode has two targets:

– To reduce power consumption by decreasing the

internal clock in the device,

– To adapt the internal clock frequency (f

the available supply voltage.

) to

CPU

After a RESET the normal operating mode is se-

lected by default (RUN mode). This mode drives

the device (CPU and embedded peripherals) by

means of a master clock which is based on the

main oscillator frequency divided or multiplied by 2

SLOW mode is controlled by three bits in the

MCCSR register: the SMS bit which enables or

disables Slow mode and two CPx bits which select

the internal slow frequency (f

).

CPU

(f

).

In this mode, the master clock frequency (f

can be divided by 2, 4, 8 or 16. The CPU and pe-

ripherals are clocked at this lower frequency

)

OSC2

From RUN mode, the different power saving

modes may be selected by setting the relevant

register bits or by calling the specific ST7 software

instruction whose action depends on the oscillator

status.

(f

).

CPU

Note: SLOW-WAIT mode is activated when enter-

ing the WAIT mode while the device is already in

SLOW mode.

Figure 23. Power Saving Mode Transitions

Figure 24. SLOW Mode Clock Transitions

High

RUN

f

/2

f

/4

f

OSC2

f

CPU

f

OSC2

SLOW

WAIT

00

01

CP1:0

SMS

SLOW WAIT

ACTIVE HALT

HALT

NORMAL RUN MODE

REQUEST

NEW SLOW

FREQUENCY

REQUEST

Low

POWER CONSUMPTION

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1

ST7MC1/ST7MC2

POWER SAVING MODES (Cont’d)

7.3 WAIT MODE

Figure 25. WAIT Mode Flow-chart

WAIT mode places the MCU in a low power con-

sumption mode by stopping the CPU.

This power saving mode is selected by calling the

‘WFI’ instruction.

OSCILLATOR

PERIPHERALS

CPU

ON

OFF

10

WFI INSTRUCTION

I[1:0] BITS

All peripherals remain active. During WAIT mode,

the I[1:0] bits of the CC register are forced to ‘10’,

to enable all interrupts. All other registers and

memory remain unchanged. The MCU remains in

WAIT mode until an interrupt or RESET occurs,

whereupon the Program Counter branches to the

starting address of the interrupt or Reset service

routine.

N

RESET

Y

N

INTERRUPT

The MCU will remain in WAIT mode until a Reset

or an Interrupt occurs, causing it to wake up.

Y

OSCILLATOR

PERIPHERALS

CPU

ON

OFF

ON

10

Refer to Figure 25.

I[1:0] BITS

256 OR 4096 CPU CLOCK

CYCLE DELAY

OSCILLATOR

PERIPHERALS

CPU

ON

I[1:0] BITS

XX ¹⁾

FETCH RESET VECTOR

OR SERVICE INTERRUPT

Note:

1. Before servicing an interrupt, the CC register is

pushed on the stack. The I[1:0] bits of the CC reg-

ister are set to the current software priority level of

the interrupt routine and recovered when the CC

register is popped.

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1

ST7MC1/ST7MC2

POWER SAVING MODES (Cont’d)

7.4 ACTIVE-HALT AND HALT MODES

Figure 26. ACTIVE-HALT Timing Overview

ACTIVE-HALT and HALT modes are the two low-

est power consumption modes of the MCU. They

are both entered by executing the ‘HALT’ instruc-

tion. The decision to enter either in ACTIVE-HALT

or HALT mode is given by the MCC/RTC interrupt

enable flag (OIE bit in MCCSR register).

ACTIVE

HALT

256 OR 4096 CPU

CYCLE DELAY

RUN

1)

RESET

OR

HALT

INSTRUCTION

[MCCSR.OIE=1]

INTERRUPT

FETCH

VECTOR

MCCSR Power Saving Mode entered when HALT

OIE bit

instruction is executed

HALT mode

ACTIVE-HALT mode

Figure 27. ACTIVE-HALT Mode Flow-chart

0

1

OSCILLATOR

PERIPHERALS

CPU

ON

OFF

10

2)

HALT INSTRUCTION

(MCCSR.OIE=1)

7.4.1 ACTIVE-HALT MODE

I[1:0] BITS

ACTIVE-HALT mode is the lowest power con-

sumption mode of the MCU with a real time clock

available. It is entered by executing the ‘HALT’ in-

struction when the OIE bit of the Main Clock Con-

troller Status register (MCCSR) is set (see section

5.4 on page 32 for more details on the MCCSR

register).

N

RESET

N

Y

INTERRUPT ³⁾

OSCILLATOR

PERIPHERALS

CPU

ON

OFF

ON

The MCU can exit ACTIVE-HALT mode on recep-

tion of either an MCC/RTC interrupt, a specific in-

terrupt (see Table 8, “Interrupt Mapping,” on

page 40) or a RESET. When exiting ACTIVE-

HALT mode by means of an interrupt, no 256 or

4096 CPU cycle delay occurs. The CPU resumes

operation by servicing the interrupt or by fetching

the reset vector which woke it up (see Figure 27).

When entering ACTIVE-HALT mode, the I[1:0] bits

in the CC register are forced to ‘10b’ to enable in-

terrupts. Therefore, if an interrupt is pending, the

MCU wakes up immediately.

Y

I[1:0] BITS

XX ⁴⁾

256 OR 4096 CPU CLOCK

CYCLE DELAY

OSCILLATOR

PERIPHERALS

CPU

ON

I[1:0] BITS

XX ⁴⁾

In ACTIVE-HALT mode, only the main oscillator

and its associated counter (MCC/RTC) are run-

ning to keep a wake-up time base. All other periph-

erals are not clocked except those which get their

clock supply from another clock generator (such

as external or auxiliary oscillator).

FETCH RESET VECTOR

OR SERVICE INTERRUPT

Notes:

1. This delay occurs only if the MCU exits ACTIVE-

HALT mode by means of a RESET.

The safeguard against staying locked in ACTIVE-

HALT mode is provided by the oscillator interrupt.

2. Peripheral clocked with an external clock source

can still be active.

Note: As soon as the interrupt capability of one of

the oscillators is selected (MCCSR.OIE bit set),

entering ACTIVE-HALT mode while the Watchdog

is active does not generate a RESET.

This means that the device cannot spend more

than a defined delay in this power saving mode.

3. Only the MCC/RTC interrupt and some specific

interrupts can exit the MCU from ACTIVE-HALT

mode (such as external interrupt). Refer to

Table 8, “Interrupt Mapping,” on page 40 for more

details.

4. Before servicing an interrupt, the CC register is

pushed on the stack. The I[1:0] bits of the CC reg-

ister are set to the current software priority level of

the interrupt routine and restored when the CC

register is popped.

48/294

1

ST7MC1/ST7MC2

POWER SAVING MODES (Cont’d)

7.4.2 HALT MODE

Figure 29. HALT Mode Flow-chart

The HALT mode is the lowest power consumption

mode of the MCU. It is entered by executing the

‘HALT’ instruction when the OIE bit of the Main

Clock Controller Status register (MCCSR) is

cleared (see section 5.4 on page 32 for more de-

tails on the MCCSR register).

HALT INSTRUCTION

(MCCSR.OIE=0)

ENABLE

WATCHDOG

DISABLE

0

WDGHALT ¹⁾

1

The MCU can exit HALT mode on reception of ei-

ther a specific interrupt (see Table 8, “Interrupt

Mapping,” on page 40) or a RESET. When exiting

HALT mode by means of a RESET or an interrupt,

the oscillator is immediately turned on and the 256

or 4096 CPU cycle delay is used to stabilize the

oscillator. After the start up delay, the CPU

resumes operation by servicing the interrupt or by

fetching the reset vector which woke it up (see Fig-

ure 29).

When entering HALT mode, the I[1:0] bits in the

CC register are forced to ‘10b’to enable interrupts.

Therefore, if an interrupt is pending, the MCU

wakes up immediately.

WATCHDOG

RESET

OSCILLATOR

OFF

10

PERIPHERALS ²⁾

CPU

I[1:0] BITS

N

RESET

Y

N

INTERRUPT ³⁾

In HALT mode, the main oscillator is turned off

causing all internal processing to be stopped, in-

cluding the operation of the on-chip peripherals.

All peripherals are not clocked except the ones

which get their clock supply from another clock

generator (such as an external or auxiliary oscilla-

tor).

OSCILLATOR

PERIPHERALS

CPU

Y

ON

OFF

ON

I[1:0] BITS

XX ⁴⁾

256 OR 4096 CPU CLOCK

CYCLE DELAY

The compatibility of Watchdog operation with

HALT mode is configured by the “WDGHALT” op-

tion bit of the option byte. The HALT instruction

when executed while the Watchdog system is en-

abled, can generate a Watchdog RESET (see sec-

tion 13.1 on page 284 for more details).

OSCILLATOR

PERIPHERALS

CPU

ON

I[1:0] BITS

XX ⁴⁾

Figure 28. HALT Timing Overview

FETCH RESET VECTOR

OR SERVICE INTERRUPT

256 OR 4096 CPU

CYCLE DELAY

RUN

HALT

RUN

Notes:

RESET

OR

INTERRUPT

1. WDGHALT is an option bit. See option byte sec-

tion for more details.

HALT

INSTRUCTION

2. Peripheral clocked with an external clock source

can still be active.

FETCH

VECTOR

[MCCSR.OIE=0]

3. Only some specific interrupts can exit the MCU

from HALT mode (such as external interrupt). Re-

fer to Table 8, “Interrupt Mapping,” on page 40 for

more details.

4. Before servicing an interrupt, the CC register is

pushed on the stack. The I[1:0] bits of the CC reg-

ister are set to the current software priority level of

the interrupt routine and recovered when the CC

register is popped.

49/294

1

ST7MC1/ST7MC2

8 I/O PORTS

8.1 INTRODUCTION

Each pin can independently generate an interrupt

request. The interrupt sensitivity is independently

programmable using the sensitivity bits in the

EICR register.

The I/O ports offer different functional modes:

– transfer of data through digital inputs and outputs

and for specific pins:

Each external interrupt vector is linked to a dedi-

cated group of I/O port pins (see pinout description

and interrupt section). If several input pins are se-

lected simultaneously as interrupt sources, these

are first detected according to the sensitivity bits in

the EICR register and then logically ORed.

– external interrupt generation

– alternate signal input/output for the on-chip pe-

ripherals.

An I/O port contains up to 8 pins. Each pin can be

programmed independently as digital input (with or

without interrupt generation) or digital output.

The external interrupts are hardware interrupts,

which means that the request latch (not accessible

directly by the application) is automatically cleared

when the corresponding interrupt vector is

fetched. To clear an unwanted pending interrupt

by software, the sensitivity bits in the EICR register

must be modified.

8.2 FUNCTIONAL DESCRIPTION

Each port has 2 main registers:

– Data Register (DR)

– Data Direction Register (DDR)

and one optional register:

– Option Register (OR)

8.2.2 Output Modes

The output configuration is selected by setting the

corresponding DDR register bit. In this case, writ-

ing the DR register applies this digital value to the

I/O pin through the latch. Then reading the DR reg-

ister returns the previously stored value.

Each I/O pin may be programmed using the corre-

sponding register bits in the DDR and OR regis-

ters: bit X corresponding to pin X of the port. The

same correspondence is used for the DR register.

Two different output modes can be selected by

software through the OR register: Output push-pull

and open-drain.

The following description takes into account the

OR register, (for specific ports which do not pro-

vide this register refer to the I/O Port Implementa-

tion section). The generic I/O block diagram is

shown in Figure 30

DR register value and output pin status:

DR

0

Push-pull

Open-drain

Vss

V

8.2.1 Input Modes

SS

1

V

Floating

DD

The input configuration is selected by clearing the

corresponding DDR register bit.

8.2.3 Alternate Functions

In this case, reading the DR register returns the

digital value applied to the external I/O pin.

When an on-chip peripheral is configured to use a

pin, the alternate function is automatically select-

ed. This alternate function takes priority over the

standard I/O programming.

Different input modes can be selected by software

through the OR register.

Notes:

When the signal is coming from an on-chip periph-

eral, the I/O pin is automatically configured in out-

put mode (push-pull or open drain according to the

peripheral).

1. Writing the DR register modifies the latch value

but does not affect the pin status.

2. When switching from input to output mode, the

DR register has to be written first to drive the cor-

rect level on the pin as soon as the port is config-

ured as an output.

When the signal is going to an on-chip peripheral,

the I/O pin must be configured in input mode. In

this case, the pin state is also digitally readable by

addressing the DR register.

3. Do not use read/modify/write instructions (BSET

or BRES) to modify the DR register

External interrupt function

Note: Input pull-up configuration can cause unex-

pected value at the input of the alternate peripheral

input. When an on-chip peripheral use a pin as in-

put and output, this pin has to be configured in in-

put floating mode.

When an I/O is configured as Input with Interrupt,

an event on this I/O can generate an external inter-

rupt request to the CPU.

50/294

1

ST7MC1/ST7MC2

I/O PORTS (Cont’d)

Figure 30. I/O Port General Block Diagram

ALTERNATE

OUTPUT

1

0

REGISTER

ACCESS

P-BUFFER

(see table below)

V

DD

ALTERNATE

ENABLE

PULL-UP

(see table below)

DR

DDR

OR

V

DD

PULL-UP

CONDITION

PAD

If implemented

OR SEL

DDR SEL

DR SEL

N-BUFFER

DIODES

(see table below)

ANALOG

INPUT

CMOS

SCHMITT

TRIGGER

1

0

ALTERNATE

INPUT

EXTERNAL

INTERRUPT

SOURCE (ei )

x

Table 10. I/O Port Mode Options

Configuration Mode

Diodes

Pull-Up

P-Buffer

to V

SS

DD

Floating with/without Interrupt

Input

Off

On

Off

Pull-up with/without Interrupt

On

Push-pull

On

Off

NI

On

Off

NI

Output

Open Drain (logic level)

True Open Drain

NI (see note)

Legend: NI - not implemented

Off - implemented not activated

On - implemented and activated

Note: The diode to V

is not implemented in the

DD

true open drain pads. A local protection between

the pad and V is implemented to protect the de-

SS

vice against positive stress.

51/294

1

ST7MC1/ST7MC2

I/O PORTS (Cont’d)

Table 11. I/O Port Configurations

Hardware Configuration

DR REGISTER ACCESS

NOT IMPLEMENTED IN

TRUE OPEN DRAIN

I/O PORTS

V

DD

PULL-UP

CONDITION

R

W

R

PU

DR

REGISTER

DATA BUS

PAD

ALTERNATE INPUT

EXTERNAL INTERRUPT

SOURCE (ei )

x

INTERRUPT

CONDITION

ANALOG INPUT

NOT IMPLEMENTED IN

TRUE OPEN DRAIN

I/O PORTS

DR REGISTER ACCESS

V

DD

R

PU

R/W

DR

REGISTER

DATA BUS

PAD

ALTERNATE

ENABLE

ALTERNATE

OUTPUT

NOT IMPLEMENTED IN

TRUE OPEN DRAIN

I/O PORTS

DR REGISTER ACCESS

V

DD

R

PU

R/W

DR

REGISTER

DATA BUS

PAD

ALTERNATE

ENABLE

ALTERNATE

OUTPUT

Notes:

1. When the I/O port is in input configuration and the associated alternate function is enabled as an output,

reading the DR register will read the alternate function output status.

2. When the I/O port is in output configuration and the associated alternate function is enabled as an input,

the alternate function reads the pin status given by the DR register content.

52/294

1

ST7MC1/ST7MC2

I/O PORTS (Cont’d)

CAUTION: The alternate function must not be ac-

tivated as long as the pin is configured as input

with interrupt, in order to avoid generating spurious

interrupts.

Figure 31. Interrupt I/O Port State Transitions

01

00

10

11

Analog alternate function

INPUT

floating/pull-up

interrupt

INPUT

floating

(reset state)

OUTPUT

open-drain

OUTPUT

push-pull

When the pin is used as an ADC input, the I/O

must be configured as floating input. The analog

multiplexer (controlled by the ADC registers)

switches the analog voltage present on the select-

ed pin to the common analog rail which is connect-

ed to the ADC input.

= DDR, OR

XX

8.4 LOW POWER MODES

It is recommended not to change the voltage level

or loading on any port pin while conversion is in

progress. Furthermore it is recommended not to

have clocking pins located close to a selected an-

alog pin.

Mode

WAIT

HALT

Description

No effect on I/O ports. External interrupts

cause the device to exit from WAIT mode.

No effect on I/O ports. External interrupts

cause the device to exit from HALT mode.

WARNING: The analog input voltage level must

be within the limits stated in the absolute maxi-

mum ratings.

8.5 INTERRUPTS

8.3 I/O PORT IMPLEMENTATION

The external interrupt event generates an interrupt

if the corresponding configuration is selected with

DDR and OR registers and the interrupt mask in

the CC register is not active (RIM instruction).

The hardware implementation on each I/O port de-

pends on the settings in the DDR and OR registers

and specific feature of the I/O port such as ADC In-

put or true open drain.

Enable Exit

Control from

Exit

from

Halt

Event

Flag

Interrupt Event

Switching these I/O ports from one state to anoth-

er should be done in a sequence that prevents un-

wanted side effects. Recommended safe transi-

tions are illustrated in Figure 31 Other transitions

are potentially risky and should be avoided, since

they are likely to present unwanted side-effects

such as spurious interrupt generation.

Bit

Wait

External interrupt on

selected external

event

DDRx

ORx

-

Yes

53/294

1

ST7MC1/ST7MC2

I/O PORTS (Cont’d)

8.5.1 I/O Port Implementation

Interrupt Ports

The I/O port register configurations are summa-

rised as follows.

PA6, PA3, PB6, PC3, PC1, PD5, PD4, PD2 (with

pull-up)

MODE

DDR

OR

0

Standard Ports

floating input

0

1

PA4, PA2:0, PB5:0, PC7:4,

PD7:6, PE5:0, PF5:0, PG7:0, PH7:0

pull-up interrupt input

open drain output

push-pull output

1

0

MODE

DDR

OR

0

1

floating input

pull-up input

0

1

open drain output

push-pull output

0

PA7, PA5, PB7, PC2, PC0, PD6, PD3, PD1 (with-

1

out pull-up)

MODE

DDR

OR

0

floating input

0

1

floating interrupt input

open drain output

push-pull output

1

0

1

Table 12. Port Configuration

Input

Output

Port

Pin name

PA7, PA5

OR = 0

OR = 1

floating interrupt

pull-up interrupt

pull-up

OR = 0

OR = 1

floating

open drain

push-pull

Port A

PA6, PA3

PA2:0

PB7

floating interrupt

pull-up interrupt

pull-up

Port B

Port C

Port D

PB6

PB5:0

PC7:4

pull-up

PC3, PC1

PC2, PC0

PD7, PD0

PD6, PD3, PD1

PD5, PD4, PD2

PE5:0

pull-up interrupt

floating interrupt

pull-up

floating interrupt

pull-up interrupt

pull-up

Port E

Port F

Port G

Port H

PF5:0

pull-up

PG7:0

pull-up

PH7:0

pull-up

54/294

1

ST7MC1/ST7MC2

I/O PORTS (Cont’d)

Table 13. I/O Port Register Map and Reset Values

Address

(Hex.)

Register

Label

7

6

5

4

3

2

1

0

Reset Value

of all I/O port registers

0

0000h

0001h

0002h

0003h

0004h

0005h

0006h

0007h

0008h

0009h

000Ah

000Bh

000Ch

000Dh

000Eh

000Fh

0010h

0011h

0012h

0013h

0014h

0015h

0016h

0017h

PADR

PADDR

PAOR

PBDR

PBDDR

PBOR

PCDR

PCDDR

PCOR

PDDR

PDDDR

PDOR

PEDR

MSB

LSB

PEDDR

PEOR

PFDR

PFDDR

PFOR

PGDR

PGDDR

PGOR

PHDR

PHDDR

PHOR

55/294

1

ST7MC1/ST7MC2

9 ON-CHIP PERIPHERALS

9.1 WINDOW WATCHDOG (WWDG)

9.1.1 Introduction

counter is reloaded outside the window (see

Figure 35)

The Window Watchdog is used to detect the oc-

currence of a software fault, usually generated by

external interference or by unforeseen logical con-

ditions, which causes the application program to

abandon its normal sequence. The Watchdog cir-

cuit generates an MCU reset on expiry of a pro-

grammed time period, unless the program refresh-

es the contents of the downcounter before the T6

bit becomes cleared. An MCU reset is also gener-

ated if the 7-bit downcounter value (in the control

register) is refreshed before the downcounter has

reached the window register value. This implies

that the counter must be refreshed in a limited win-

dow.

– Hardware/Software Watchdog activation (se-

lectable by option byte)

– Optional reset on HALT instruction (configurable

by option byte)

9.1.3 Functional Description

The counter value stored in the WDGCR register

(bits T[6:0]), is decremented every 16384 f

OSC2

cycles (approx.), and the length of the timeout pe-

riod can be programmed by the user in 64 incre-

ments.

If the watchdog is activated (the WDGA bit is set)

and when the 7-bit downcounter (T[6:0] bits) rolls

over from 40h to 3Fh (T6 becomes cleared), it ini-

tiates a reset cycle pulling low the reset pin for typ-

ically 30µs. If the software reloads the counter

while the counter is greater than the value stored

in the window register, then a reset is generated.

9.1.2 Main Features

– Programmable free-running downcounter

– Conditional reset

– Reset (if watchdog activated) when the down-

counter value becomes less than 40h

– Reset (if watchdog activated) if the down-

Figure 32. Watchdog Block Diagram

RESET

WATCHDOG WINDOW REGISTER (WDGWR)

-

W5

W0

W6

W1

W4

W2

W3

comparator

=1 when

T6:0 > W6:0

CMP

Write WDGCR

WATCHDOG CONTROL REGISTER (WDGCR)

T5

T0

WDGA T6

T1

T4

T2

T3

6-BIT DOWNCOUNTER (CNT)

MCC/RTC

f

OSC2

DIV 64

WDG PRESCALER

DIV 4

12-BIT MCC

RTC COUNTER

TB[1:0] bits

(MCCSR

Register)

MSB

LSB

0

6 5

11

56/294

1

ST7MC1/ST7MC2

WINDOW WATCHDOG (Cont’d)

The application program must write in the

WDGCR register at regular intervals during normal

operation to prevent an MCU reset. This operation

must occur only when the counter value is lower

than the window register value. The value to be

stored in the WDGCR register must be between

FFh and C0h (see Figure 33):

between a minimum and a maximum value due

to the unknown status of the prescaler when writ-

ing to the WDGCR register (see Figure 34).

The window register (WDGWR) contains the

high limit of the window: to prevent a reset, the

downcounter must be reloaded when its value is

lower than the window register value and greater

than 3Fh. Figure 35 describes the window watch-

dog process.

– Enabling the watchdog:

When Software Watchdog is selected (by option

byte), the watchdog is disabled after a reset. It is

enabled by setting the WDGA bit in the WDGCR

register, then it cannot be disabled again except

by a reset.

Note: The T6 bit can be used to generate a soft-

ware reset (the WDGA bit is set and the T6 bit is

cleared).

– Watchdog Reset on Halt option

When Hardware Watchdog is selected (by option

byte), the watchdog is always active and the

WDGA bit is not used.

If the watchdog is activated and the watchdog re-

set on halt option is selected, then the HALT in-

struction will generate a Reset.

– Controlling the downcounter :

9.1.4 Using Halt Mode with the WDG

This downcounter is free-running: it counts down

even if the watchdog is disabled. When the

watchdog is enabled, the T6 bit must be set to

prevent generating an immediate reset.

The T[5:0] bits contain the number of increments

which represents the time delay before the

watchdog produces a reset (see Figure 33. Ap-

proximate Timeout Duration). The timing varies

If Halt mode with Watchdog is enabled by option

byte (No watchdog reset on HALT instruction), it is

recommended before executing the HALT instruc-

tion to refresh the WDG counter, to avoid an unex-

pected WDG reset immediately after waking up

the microcontroller.

57/294

1

ST7MC1/ST7MC2

WINDOW WATCHDOG (Cont’d)

9.1.5 How to Program the Watchdog Timeout

more precision is needed, use the formulae in Fig-

ure 34.

Figure 33 shows the linear relationship between

the 6-bit value to be loaded in the Watchdog Coun-

ter (CNT) and the resulting timeout duration in mil-

liseconds. This can be used for a quick calculation

without taking the timing variations into account. If

Caution: When writing to the WDGCR register, al-

ways write 1 in the T6 bit to avoid generating an

immediate reset.

Figure 33. Approximate Timeout Duration

3F

38

30

28

20

18

10

08

00

1.5

18

34

50

65

82

98

114

128

Watchdog timeout (ms) @ 8 MHz. f

OSC2

58/294

1

ST7MC1/ST7MC2

WATCHDOG TIMER (Cont’d)

Figure 34. Exact Timeout Duration (t

and t

)

max

min

WHERE:

t

= (LSB + 128) x 64 x t

min0

OSC2

= 16384 x t

= 125ns if f

max0

OSC2

=8 MHz

OSC2

CNT = Value of T[5:0] bits in the WDGCR register (6 bits)

MSB and LSB are values from the table below depending on the timebase selected by the TB[1:0] bits

in the MCCSR register

TB1 Bit

TB0 Bit

Selected MCCSR

Timebase

MSB

LSB

(MCCSR Reg.) (MCCSR Reg.)

0

1

0

1

0

1

2ms

4ms

4

8

59

53

35

54

10ms

25ms

20

49

To calculate the minimum Watchdog Timeout (t ):

min

MSB

4

IF

-------------

THEN

ELSE

CNT <

t

= t

+ 16384 × CNT × t

min0 osc2

min

4CNT

----------------

MSB

4CNT

----------------

MSB







t

= t

+

16384 × CNT –

+

(192 + LSB) × 64 ×

× t

osc2

min

min0



To calculate the maximum Watchdog Timeout (t

):

max

MSB

4

IF

THEN

ELSE

-------------

CNT

≤

t

= t

+

16384

×

CNT

×

t

max

max0

osc2

4CNT

----------------

4CNT

----------------





t

= t

+

16384 × CNT –

+

(192 + LSB) × 64 ×

×

t

max

max0





osc2

MSB

Note: In the above formulae, division results must be rounded down to the next integer value.

Example:

With 2ms timeout selected in MCCSR register

Min. Watchdog

Timeout (ms)

Max. Watchdog

Timeout (ms)

Value of T[5:0] Bits in

WDGCR Register (Hex.)

t

min

max

00

3F

1.496

128

2.048

128.552

59/294

1

ST7MC1/ST7MC2

WINDOW WATCHDOG (Cont’d)

Figure 35. Window Watchdog Timing Diagram

T[5:0] CNT downcounter

WDGWR

3Fh

time

(step = 16384/f

)

Refresh not allowed Refresh Window

OSC2

T6 bit

Reset

9.1.6 Low Power Modes

Mode Description

SLOW No effect on Watchdog : the downcounter continues to decrement at normal speed.

WAIT No effect on Watchdog : the downcounter continues to decrement.

OIE bit in

MCCSR

register

WDGHALT bit

in Option

Byte

No Watchdog reset is generated. The MCU enters Halt mode. The Watch-

dog counter is decremented once and then stops counting and is no longer

able to generate a watchdog reset until the MCU receives an external inter-

rupt or a reset.

HALT

0

If an interrupt is received (refer to interrupt table mapping to see interrupts

which can occur in halt mode), the Watchdog restarts counting after 256 or

4096 CPU clocks. If a reset is generated, the Watchdog is disabled (reset

state) unless Hardware Watchdog is selected by option byte. For applica-

tion recommendations see Section 9.1.8 below.

0

1

x

A reset is generated instead of entering halt mode.

No reset is generated. The MCU enters Active Halt mode. The Watchdog

counter is not decremented. It stop counting. When the MCU receives an

oscillator interrupt or external interrupt, the Watchdog restarts counting im-

mediately. When the MCU receives a reset the Watchdog restarts counting

after 256 or 4096 CPU clocks.

ACTIVE

HALT

9.1.7 Hardware Watchdog Option

9.1.8 Using Halt Mode with the WDG

(WDGHALT option)

If Hardware Watchdog is selected by option byte,

the watchdog is always active and the WDGA bit in

the WDGCR is not used. Refer to the Option Byte

description.

The following recommendation applies if Halt

mode is used when the watchdog is enabled.

– Before executing the HALT instruction, refresh

the WDG counter, to avoid an unexpected WDG

reset immediately after waking up the microcon-

troller.

60/294

1

ST7MC1/ST7MC2

WINDOW WATCHDOG (Cont’d)

9.1.9 Interrupts

Note: This bit is not used if the hardware watch-

dog option is enabled by option byte.

None.

Bits 6:0 = T[6:0] 7-bit counter (MSB to LSB).

These bits contain the value of the watchdog

9.1.10 Register Description

CONTROL REGISTER (WDGCR)

Read/Write

counter. It is decremented every 16384 f

cy-

OSC2

cles (approx.). A reset is produced when it rolls

over from 40h to 3Fh (T6 becomes cleared).

Reset Value: 0111 1111 (7Fh)

7

0

WINDOW REGISTER (WDGWR)

Read/Write

WDGA T6

T5

T4

T3

T2

T1

T0

Reset Value: 0111 1111 (7Fh)

Bit 7 = WDGA Activation bit.

7

-

0

This bit is set by software and only cleared by

hardware after a reset. When WDGA = 1, the

watchdog can generate a reset.

W6

W5

W4

W3 W2 W1

W0

0: Watchdog disabled

1: Watchdog enabled

Bit 7 = Reserved

Bits 6:0 = W[6:0] 7-bit window value

These bits contain the window value to be com-

pared to the downcounter.

61/294

1

ST7MC1/ST7MC2

Table 14. Watchdog Timer Register Map and Reset Values

Address

(Hex.)

Register

Label

7

6

5

4

3

2

1

0

WDGCR

Reset Value

WDGA

0

T6

1

T5

1

T4

1

T3

1

T2

1

T1

1

T0

1

002Ah

002Bh

WDGWR

Reset Value

0

W6

1

W5

1

W4

1

W3

1

W2

1

W1

1

W0

1

62/294

1

ST7MC1/ST7MC2

9.2 PWM AUTO-RELOAD TIMER (ART)

9.2.1 Introduction

The Pulse Width Modulated Auto-Reload Timer

on-chip peripheral consists of an 8-bit auto reload

counter with compare/capture capabilities and of a

7-bit prescaler clock source.

– Up to two input capture functions

– External event detector

– Up to two external interrupt sources

The three first modes can be used together with a

single counter frequency.

These resources allow five possible operating

modes:

The timer can be used to wake up the MCU from

WAIT and HALT modes.

– Generation of up to 4 independent PWM signals

– Output compare and Time base interrupt

Figure 36. PWM Auto-Reload Timer Block Diagram

OCRx

DCRx

OEx

OPx

PWMCR

REGISTER

LOAD

PORT

ALTERNATE

FUNCTION

POLARITY

CONTROL

PWMx

COMPARE

8-BIT COUNTER

(CAR REGISTER)

ARR

REGISTER

LOAD

ICRx

INPUT CAPTURE

CONTROL

LOAD

ARTICx

REGISTER

ICSx

ICIEx

ICFx

ICCSR

ICx INTERRUPT

f

EXT

ARTCLK

f

COUNTER

f

CPU

MUX

f

INPUT

PROGRAMMABLE

PRESCALER

ARTCSR

EXCL CC2

CC1

CC0

TCE FCRL OIE

OVF

OVF INTERRUPT

63/294

1

ST7MC1/ST7MC2

PWM AUTO-RELOAD TIMER (Cont’d)

9.2.2 Functional Description

Counter

Counter and Prescaler Initialization

The free running 8-bit counter is fed by the output

of the prescaler, and is incremented on every ris-

ing edge of the clock signal.

After RESET, the counter and the prescaler are

cleared and f

= f

.

INPUT

CPU

The counter can be initialized by:

It is possible to read or write the contents of the

counter on the fly by reading or writing the Counter

Access register (ARTCAR).

– Writing to the ARTARR register and then setting

the FCRL (Force Counter Re-Load) and the TCE

(Timer Counter Enable) bits in the ARTCSR reg-

ister.

When a counter overflow occurs, the counter is

automatically reloaded with the contents of the

ARTARR register (the prescaler is not affected).

– Writing to the ARTCAR counter access register,

In both cases the 7-bit prescaler is also cleared,

whereupon counting will start from a known value.

Counter clock and prescaler

The counter clock frequency is given by:

Direct access to the prescaler is not possible.

CC[2:0]

f

= f

/ 2

COUNTER

INPUT

Output compare control

The timer counter’s input clock (f

) feeds the

INPUT

The timer compare function is based on four differ-

ent comparisons with the counter (one for each

PWMx output). Each comparison is made be-

tween the counter value and an output compare

register (OCRx) value. This OCRx register can not

be accessed directly, it is loaded from the duty cy-

cle register (PWMDCRx) at each overflow of the

counter.

7-bit programmable prescaler, which selects one

of the 8 available taps of the prescaler, as defined

by CC[2:0] bits in the Control/Status Register

(ARTCSR). Thus the division factor of the prescal-

n

er can be set to 2 (where n = 0, 1,..7).

This f

frequency source is selected through

INPUT

the EXCL bit of the ARTCSR register and can be

either the f or an external input frequency f

.

EXT

CPU

This double buffering method avoids glitch gener-

ation when changing the duty cycle on the fly.

The clock input to the counter is enabled by the

TCE (Timer Counter Enable) bit in the ARTCSR

register. When TCE is reset, the counter is

stopped and the prescaler and counter contents

are frozen. When TCE is set, the counter runs at

the rate of the selected clock source.

Figure 37. Output compare control

f_COUNTER

ARTARR=FDh

COUNTER

OCRx

FDh

FEh

FFh

FDh

FEh

FFh

FDh

FEh

FFh

FEh

FDh

PWMDCRx

FEh

FDh

PWMx

64/294

1

ST7MC1/ST7MC2

PWM AUTO-RELOAD TIMER (Cont’d)

Independent PWM signal generation

When the counter reaches the value contained in

one of the output compare register (OCRx) the

corresponding PWMx pin level is restored.

This mode allows up to four Pulse Width Modulat-

ed signals to be generated on the PWMx output

pins with minimum core processing overhead.

This function is stopped during HALT mode.

It should be noted that the reload values will also

affect the value and the resolution of the duty cycle

of the PWM output signal. To obtain a signal on a

PWMx pin, the contents of the OCRx register must

be greater than the contents of the ARTARR reg-

ister.

Each PWMx output signal can be selected inde-

pendently using the corresponding OEx bit in the

PWM Control register (PWMCR). When this bit is

set, the corresponding I/O pin is configured as out-

put push-pull alternate function.

The maximum available resolution for the PWMx

duty cycle is:

The PWM signals all have the same frequency

which is controlled by the counter period and the

ARTARR register value.

Resolution = 1 / (256 - ARTARR)

Note: To get the maximum resolution (1/256), the

ARTARR register must be 0. With this maximum

resolution, 0% and 100% can be obtained by

changing the polarity.

f

= f

/ (256 - ARTARR)

COUNTER

PWM

When a counter overflow occurs, the PWMx pin

level is changed depending on the corresponding

OPx (output polarity) bit in the PWMCR register.

Figure 38. PWM Auto-reload Timer Function

255

DUTY CYCLE

REGISTER

(PWMDCRx)

AUTO-RELOAD

REGISTER

(ARTARR)

000

t

WITH OEx=1

AND OPx=0

WITH OEx=1

AND OPx=1

Figure 39. PWM Signal from 0% to 100% Duty Cycle

f_COUNTER

ARTARR=FDh

FFh

COUNTER

FDh

FEh

FDh

FEh

FFh

FDh

FEh

OCRx=FCh

OCRx=FDh

OCRx=FEh

OCRx=FFh

t

65/294

1

ST7MC1/ST7MC2

PWM AUTO-RELOAD TIMER (Cont’d)

Output compare and Time base interrupt

External clock and event detector mode

Using the f external prescaler input clock, the

auto-reload timer can be used as an external clock

event detector. In this mode, the ARTARR register

On overflow, the OVF flag of the ARTCSR register

is set and an overflow interrupt request is generat-

ed if the overflow interrupt enable bit, OIE, in the

ARTCSR register, is set. The OVF flag must be re-

set by the user software. This interrupt can be

used as a time base in the application.

EXT

is used to select the n

be counted before setting the OVF flag.

number of events to

EVENT

n

= 256 - ARTARR

EVENT

Caution: The external clock function is not availa-

ble in HALT mode. If HALT mode is used in the ap-

plication, prior to executing the HALT instruction,

the counter must be disabled by clearing the TCE

bit in the ARTCSR register to avoid spurious coun-

ter increments.

Figure 40. External Event Detector Example (3 counts)

f_EXT=f_COUNTER

ARTARR=FDh

COUNTER

FDh

FEh

FFh

FDh

FEh

FFh

FDh

OVF

ARTCSR READ

INTERRUPT

IF OIE=1

INTERRUPT

IF OIE=1

t

66/294

1

ST7MC1/ST7MC2

PWM AUTO-RELOAD TIMER (Cont’d)

Input capture function

This mode allows the measurement of external

signal pulse widths through ARTICRx registers.

External interrupt capability

This mode allows the Input capture capabilities to

be used as external interrupt sources. The inter-

rupts are generated on the edge of the ARTICx

signal.

Each input capture can generate an interrupt inde-

pendently on a selected input signal transition.

This event is flagged by a set of the corresponding

CFx bits of the Input Capture Control/Status regis-

ter (ARTICCSR).

The edge sensitivity of the external interrupts is

programmable (CSx bit of ARTICCSR register)

and they are independently enabled through CIEx

bits of the ARTICCSR register. After fetching the

interrupt vector, the CFx flags can be read to iden-

tify the interrupt source.

These input capture interrupts are enabled

through the CIEx bits of the ARTICCSR register.

The active transition (falling or rising edge) is soft-

ware programmable through the CSx bits of the

ARTICCSR register.

During HALT mode, the external interrupts can be

used to wake up the micro (if the CIEx bit is set).

The read only input capture registers (ARTICRx)

are used to latch the auto-reload counter value

when a transition is detected on the ARTICx pin

(CFx bit set in ARTICCSR register). After fetching

the interrupt vector, the CFx flags can be read to

identify the interrupt source.

Note: After a capture detection, data transfer in

the ARTICRx register is inhibited until it is read

(clearing the CFx bit).

The timer interrupt remains pending while the CFx

flag is set when the interrupt is enabled (CIEx bit

set). This means, the ARTICRx register has to be

read at each capture event to clear the CFx flag.

The timing resolution is given by auto-reload coun-

ter cycle time (1/f

).

COUNTER

Note: During HALT mode, if both input capture

and external clock are enabled, the ARTICRx reg-

ister value is not guaranteed if the input capture

pin and the external clock change simultaneously.

Figure 41. Input Capture Timing Diagram

f_COUNTER

COUNTER

01h

02h

03h

04h

05h

06h

07h

INTERRUPT

04h

ARTICx PIN

CFx FLAG

xxh

ICRx REGISTER

t

67/294

1

ST7MC1/ST7MC2

PWM AUTO-RELOAD TIMER (Cont’d)

9.2.3 Register Description

CONTROL / STATUS REGISTER (ARTCSR)

Read/Write

0: New transition not yet reached

1: Transition reached

COUNTER ACCESS REGISTER (ARTCAR)

Read/Write

Reset Value: 0000 0000 (00h)

7

0

Reset Value: 0000 0000 (00h)

EXCL CC2

CC1

CC0

TCE FCRL

OIE

OVF

7

0

Bit 7 = EXCLExternal Clock

CA7

CA6

CA5

CA4

CA3

CA2

CA1

CA0

This bit is set and cleared by software. It selects the

input clock for the 7-bit prescaler.

0: CPU clock.

Bit 7:0 = CA[7:0] Counter Access Data

1: External clock.

These bits can be set and cleared either by hard-

ware or by software. The ARTCAR register is used

to read or write the auto-reload counter “on the fly”

(while it is counting).

Bit 6:4 = CC[2:0] Counter Clock Control

These bits are set and cleared by software. They

determine the prescaler division ratio from f

.

INPUT

f

With f

INPUT

=8 MHz CC2 CC1 CC0

COUNTER

f

8 MHz

4 MHz

2 MHz

1 MHz

500 KHz

250 KHz

125 KHz

62.5 KHz

0

1

0

1

0

1

0

1

0

1

0

1

0

1

INPUT

AUTO-RELOAD REGISTER (ARTARR)

Read/Write

f

/ 2

/ 4

/ 8

/ 16

/ 32

/ 64

/ 128

INPUT

Reset Value: 0000 0000 (00h)

f

INPUT

7

0

f

INPUT

AR7

AR6

AR5

AR4

AR3

AR2

AR1

AR0

Bit 3 = TCE Timer Counter Enable

Bit 7:0 = AR[7:0]Counter Auto-Reload Data

This bit is set and cleared by software. It puts the

timer in the lowest power consumption mode.

0: Counter stopped (prescaler and counter frozen).

1: Counter running.

These bits are set and cleared by software. They

are used to hold the auto-reload value which is au-

tomatically loaded in the counter when an overflow

occurs. At the same time, the PWM output levels

are changed according to the corresponding OPx

bit in the PWMCR register.

Bit 2 = FCRLForce Counter Re-Load

This bit is write-only and any attempt to read it will

yielda logicalzero. When set, itcausesthecontents

of ARTARR register to be loaded into the counter,

and the content of the prescaler register to be

cleared in order to initialize the timer before starting

to count.

This register has two PWM management func-

tions:

– Adjusting the PWM frequency

– Setting the PWM duty cycle resolution

Bit 1 = OIEOverflow Interrupt Enable

This bit is set and cleared by software. It allows to

enable/disable the interrupt which is generated

when the OVF bit is set.

0: Overflow Interrupt disable.

1: Overflow Interrupt enable.

PWM Frequency vs. Resolution:

f

PWM

ARTARR

value

Resolution

Min

Max

0

8-bit

~0.244-KHz 31.25-KHz

Bit 0 = OVFOverflow Flag

This bit is set by hardware and cleared by software

reading the ARTCSR register. It indicates the tran-

sition of the counter from FFh to the ARTARR val-

[ 0..127 ]

> 7-bit

> 6-bit

> 5-bit

> 4-bit

~0.244-KHz

~0.488-KHz

~0.977-KHz

~1.953-KHz

62.5-KHz

125-KHz

250-KHz

500-KHz

[ 128..191 ]

[ 192..223 ]

[ 224..239 ]

ue

.

68/294

1

ST7MC1/ST7MC2

PWM AUTO-RELOAD TIMER (Cont’d)

PWM CONTROL REGISTER (PWMCR)

Read/Write

DUTY CYCLE REGISTERS (PWMDCRx)

Read/Write

Reset Value: 0000 0000 (00h)

7

0

7

0

OE3

OE2

OE1

OE0

OP3

OP2

OP1

OP0

DC7

DC6

DC5

DC4

DC3

DC2

DC1

DC0

Bit 7:4 = OE[3:0] PWM Output Enable

Bit 7:0 = DC[7:0] Duty Cycle Data

These bits are set and cleared by software.

These bits are set and cleared by software. They

enable or disable the PWM output channels inde-

pendently acting on the corresponding I/O pin.

0: PWM output disabled.

A PWMDCRx register is associated with the OCRx

register of each PWM channel to determine the

second edge location of the PWM signal (the first

edge location is common to all channels and given

by the ARTARR register). These PWMDCR regis-

ters allow the duty cycle to be set independently

for each PWM channel.

1: PWM output enabled.

Bit 3:0 = OP[3:0] PWM Output Polarity

These bits are set and cleared by software. They

independently select the polarity of the four PWM

output signals.

PWMx output level

OPx

Counter <= OCRx

Counter > OCRx

1

0

1

0

1

Note: When an OPx bit is modified, the PWMx out-

put signal polarity is immediately reversed.

69/294

1

ST7MC1/ST7MC2

PWM AUTO-RELOAD TIMER (Cont’d)

INPUT CAPTURE

CONTROL / STATUS REGISTER (ARTICCSR)

INPUT CAPTURE REGISTERS (ARTICRx)

Read only

Read/Write

Reset Value: 0000 0000 (00h)

7

0

7

0

IC7

IC6

IC5

IC4

IC3

IC2

IC1

IC0

0

CS2

CS1

CIE2 CIE1

CF2

CF1

Bit 7:0 = IC[7:0] Input Capture Data

Bit 7:6 = Reserved, always read as 0.

These read only bits are set and cleared by hard-

ware. An ARTICRx register contains the 8-bit

auto-reload counter value transferred by the input

capture channel x event.

Bit 5:4 = CS[2:1] Capture Sensitivity

These bits are set and cleared by software. They

determine the trigger event polarity on the corre-

sponding input capture channel.

0: Falling edge triggers capture on channel x.

1: Rising edge triggers capture on channel x.

Bit 3:2 = CIE[2:1] Capture Interrupt Enable

These bits are set and cleared by software. They

enable or disable the Input capture channel inter-

rupts independently.

0: Input capture channel x interrupt disabled.

1: Input capture channel x interrupt enabled.

Bit 1:0 = CF[2:1] Capture Flag

These bits are set by hardware and cleared by

software reading the corresponding ARTICRx reg-

ister. Each CFx bit indicates that an input capture x

has occurred.

0: No input capture on channel x.

1: An input capture has occured on channel x.

70/294

1

ST7MC1/ST7MC2

PWM AUTO-RELOAD TIMER (Cont’d)

Table 15. PWM Auto-Reload Timer Register Map and Reset Values

Address

(Hex.)

Register

Label

7

6

5

4

3

2

1

0

PWMDCR3

DC7

0

DC6

0

DC5

0

DC4

0

DC3

0

DC2

0

DC1

0

DC0

0

0073h

0074h

0075h

0076h

0077h

0078h

0079h

007Ah

007Bh

007Ch

007Dh

Reset Value

PWMDCR2

DC7

0

DC6

0

DC5

0

DC4

0

DC3

0

DC2

0

DC1

0

DC0

0

Reset Value

PWMDCR1

DC7

0

DC6

0

DC5

0

DC4

0

DC3

0

DC2

0

DC1

0

DC0

0

Reset Value

PWMDCR0

DC7

0

DC6

0

DC5

0

DC4

0

DC3

0

DC2

0

DC1

0

DC0

0

Reset Value

PWMCR

OE3

0

OE2

0

OE1

0

OE0

0

OP3

0

OP2

0

OP1

0

OP0

0

Reset Value

ARTCSR

EXCL

0

CC2

0

CC1

0

CC0

0

TCE

0

FCRL

0

OIE

0

OVF

0

Reset Value

ARTCAR

CA7

0

CA6

0

CA5

0

CA4

0

CA3

0

CA2

0

CA1

0

CA0

0

Reset Value

ARTARR

AR7

0

AR6

0

AR5

0

AR4

0

AR3

0

AR2

0

AR1

0

AR0

0

Reset Value

ARTICCSR

CS2

0

CS1

0

CIE2

0

CIE1

0

CF2

0

CF1

0

Reset Value

ARTICR1

IC7

0

IC6

0

IC5

0

IC4

0

IC3

0

IC2

0

IC1

0

IC0

0

Reset Value

ARTICR2

IC7

0

IC6

0

IC5

0

IC4

0

IC3

0

IC2

0

IC1

0

IC0

0

Reset Value

71/294

1

ST7MC1/ST7MC2

9.3 16-BIT TIMER

9.3.1 Introduction

When reading an input signal on a non-bonded

pin, the value will always be ‘1’.

The timer consists of a 16-bit free-running counter

driven by a programmable prescaler.

9.3.3 Functional Description

9.3.3.1 Counter

It may be used for a variety of purposes, including

pulse length measurement of up to two input sig-

nals (input capture) or generation of up to two out-

put waveforms (output compare and PWM).

The main block of the Programmable Timer is a

16-bit free running upcounter and its associated

16-bit registers. The 16-bit registers are made up

of two 8-bit registers called high & low.

Pulse lengths and waveform periods can be mod-

ulated from a few microseconds to several milli-

seconds using the timer prescaler and the CPU

clock prescaler.

Counter Register (CR):

– Counter High Register (CHR) is the most sig-

nificant byte (MS Byte).

Some devices of the ST7 family have two on-chip

16-bit timers. They are completely independent,

and do not share any resources. They are syn-

chronized after a Device reset as long as the timer

clock frequencies are not modified.

– Counter Low Register (CLR) is the least sig-

nificant byte (LS Byte).

Alternate Counter Register (ACR)

– Alternate Counter High Register (ACHR) is the

most significant byte (MS Byte).

This description covers one or two 16-bit timers. In

the devices with two timers, register names are

prefixed with TA (Timer A) or TB (Timer B).

– Alternate Counter Low Register (ACLR) is the

least significant byte (LS Byte).

9.3.2 Main Features

These two read-only 16-bit registers contain the

same value but with the difference that reading the

ACLR register does not clear the TOF bit (Timer

overflow flag), located in the Status register, (SR),

(see note at the end of paragraph titled 16-bit read

sequence).

ꢀ

Programmableprescaler:f_CPUdividedby2, 4or8.

Overflow status flag and maskable interrupt

External clock input (must be at least 4 times

slowerthan theCPUclockspeed)with thechoice

of active edge

Writing in the CLR register or ACLR register resets

the free running counter to the FFFCh value.

Both counters have a reset value of FFFCh (this is

the only value which is reloaded in the 16-bit tim-

er). The reset value of both counters is also

FFFCh in One Pulse mode and PWM mode.

ꢀ

Output compare functions with

– 2 dedicated 16-bit registers

– 2 dedicated programmable signals

– 2 dedicated status flags

– 1 dedicated maskable interrupt

Input capture functions with

– 2 dedicated 16-bit registers

– 2 dedicated active edge selection signals

– 2 dedicated status flags

ꢀ

The timer clock depends on the clock control bits

of the CR2 register, as illustrated in Table 16 Clock

Control Bits. The value in the counter register re-

peats every 131.072, 262.144 or 524.288 CPU

clock cycles depending on the CC[1:0] bits.

– 1 dedicated maskable interrupt

Pulse width modulation mode (PWM)

One pulse mode

Reduced Power Mode

5 alternate functionson I/O ports (ICAP1, ICAP2,

OCMP1, OCMP2, EXTCLK)*

The timer frequency can be f

or an external frequency.

/2, f

/4, f

/8

CPU

ꢀ

The Block Diagram is shown in Figure 42.

*Note: Some timer pins may not available (not

bonded) in some devices. Refer to the device pin

out description.

72/294

1

ST7MC1/ST7MC2

16-BIT TIMER (Cont’d)

Figure 42. Timer Block Diagram

INTERNAL BUS

f

CPU

16-BIT TIMER PERIPHERAL INTERFACE

8 low

8-bit

8 high

8

buffer

EXEDG

16

INPUT

CAPTURE

REGISTER

INPUT

CAPTURE

REGISTER

OUTPUT

COMPARE

REGISTER

OUTPUT

COMPARE

REGISTER

1/2

1/4

1/8

COUNTER

REGISTER

1

2

ALTERNATE

COUNTER

REGISTER

EXTCLK

16

CC[1:0]

TIMER INTERNAL BUS

16 16

OVERFLOW

DETECT

EDGE DETECT

CIRCUIT1

OUTPUT COMPARE

CIRCUIT

ICAP1

CIRCUIT

6

EDGE DETECT

CIRCUIT2

ICAP2

OCMP1

LATCH1

LATCH2

0

ICF1 OCF1 TOF ICF2 OCF2

0

TIMD

(Control/Status Register)

OCMP2

CSR

EXEDG

ICIE OCIE TOIE FOLV2 FOLV1OLVL2 IEDG1 OLVL1

OC1E

OPM PWM CC1 CC0 IEDG2

OC2E

(Control Register 1) CR1

(Control Register 2) CR2

(See note)

Note: If IC, OC and TO interrupt requests have separate vectors

then the last OR is not present (See Device Interrupt Vector Table)

TIMER INTERRUPT

73/294

1

ST7MC1/ST7MC2

16-BIT TIMER (Cont’d)

16-bit read sequence: (from either the Counter

Register or the Alternate Counter Register).

Clearing the overflow interrupt request is done in

two steps:

1. Reading the SR register while the TOF bit is set.

2. An access (read or write) to the CLR register.

Beginning of the sequence

Read

LS Byte

is buffered

Notes: The TOF bit is not cleared by accesses to

ACLR register. The advantage of accessing the

ACLR register rather than the CLR register is that

it allows simultaneous use of the overflow function

and reading the free running counter at random

times (for example, to measure elapsed time) with-

out the risk of clearing the TOF bit erroneously.

MS Byte

At t0

Other

instructions

Returns the buffered

LS Byte value at t0

Read

LS Byte

At t0 +∆t

The timer is not affected by WAIT mode.

In HALT mode, the counter stops counting until the

mode is exited. Counting then resumes from the

previous count (Device awakened by an interrupt)

or from the reset count (Device awakened by a

Reset).

Sequence completed

The user must read the MS Byte first, then the LS

Byte value is buffered automatically.

This buffered value remains unchanged until the

16-bit read sequence is completed, even if the

user reads the MS Byte several times.

9.3.3.2 External Clock

After a complete reading sequence, if only the

CLR register or ACLR register are read, they re-

turn the LS Byte of the count value at the time of

the read.

The external clock (where available) is selected if

CC0=1 and CC1=1 in CR2 register.

The status of the EXEDG bit in the CR2 register

determines the type of level transition on the exter-

nal clock pin EXTCLK that will trigger the free run-

ning counter.

Whatever the timer mode used (input capture, out-

put compare, one pulse mode or PWM mode) an

overflow occurs when the counter rolls over from

FFFFh to 0000h then:

The counter is synchronised with the falling edge

of the internal CPU clock.

– The TOF bit of the SR register is set.

– A timer interrupt is generated if:

– TOIE bit of the CR1 register is set and

– I bit of the CC register is cleared.

A minimum of four falling edges of the CPU clock

must occur between two consecutive active edges

of the external clock; thus the external clock fre-

quency must be less than a quarter of the CPU

clock frequency.

If one of these conditions is false, the interrupt re-

mains pending to be issued as soon as they are

both true.

74/294

1

ST7MC1/ST7MC2

16-BIT TIMER (Cont’d)

Figure 43. Counter Timing Diagram, internal clock divided by 2

CPU CLOCK

INTERNAL RESET

TIMER CLOCK

FFFD FFFE FFFF 0000 0001 0002 0003

COUNTER REGISTER

TIMER OVERFLOW FLAG (TOF)

Figure 44. Counter Timing Diagram, internal clock divided by 4

CPU CLOCK

INTERNAL RESET

TIMER CLOCK

FFFC

FFFD

0000

0001

COUNTER REGISTER

TIMER OVERFLOW FLAG (TOF)

Figure 45. Counter Timing Diagram, internal clock divided by 8

CPU CLOCK

INTERNAL RESET

TIMER CLOCK

0000

FFFC

FFFD

COUNTER REGISTER

TIMER OVERFLOW FLAG (TOF)

Note: The Device is in reset state when the internal reset signal is high, when it is low the Device is run-

ning.

75/294

1

ST7MC1/ST7MC2

16-BIT TIMER (Cont’d)

9.3.3.3 Input Capture

When an input capture occurs:

In this section, the index, i, may be 1 or 2 because

there are 2 input capture functions in the 16-bit

timer.

– ICFi bit is set.

– The ICiR register contains the value of the free

running counter on the active transition on the

ICAPi pin (see Figure 47).

The two input capture 16-bit registers (IC1R and

IC2R) are used to latch the value of the free run-

ning counter after a transition detected by the

ICAPi pin (see figure 5).

– A timer interrupt is generated if the ICIE bit is set

and the I bit is cleared in the CC register. Other-

wise, the interrupt remains pending until both

conditions become true.

MS Byte

LS Byte

Clearing the Input Capture interrupt request (i.e.

ICiR

ICiHR

ICiLR

clearing the ICFi bit) is done in two steps:

ICiR register is a read-only register.

1. Reading the SR register while the ICFi bit is set.

2. An access (read or write) to the ICiLR register.

The active transition is software programmable

through the IEDGi bit of Control Registers (CRi).

Timing resolution is one count of the free running

Notes:

counter: (

f

/CC[1:0]).

CPU

1. After reading the ICiHR register, transfer of

input capture data is inhibited and ICFi will

never be set until the ICiLR register is also

read.

Procedure:

To use the input capture function select the follow-

ing in the CR2 register:

2. The ICiR register contains the free running

counter value which corresponds to the most

recent input capture.

– Select the timer clock (CC[1:0]) (see Table 16

Clock Control Bits).

3. The 2 input capture functions can be used

together even if the timer also uses the 2 output

compare functions.

– Select the edge of the active transition on the

ICAP2 pin with the IEDG2 bit (the ICAP2 pin

must be configured as floating input).

4. In One pulse Mode and PWM mode only the

input capture 2 can be used.

And select the following in the CR1 register:

– Set the ICIE bit to generate an interrupt after an

input capture coming from either the ICAP1 pin

or the ICAP2 pin

5. The alternate inputs (ICAP1 & ICAP2) are

always directly connected to the timer. So any

transitions on these pins activate the input cap-

ture function.

– Select the edge of the active transition on the

ICAP1 pin with the IEDG1 bit (the ICAP1pin must

be configured as floating input).

Moreover if one of the ICAPi pin is configured

as an input and the second one as an output,

an interrupt can be generated if the user toggle

the output pin and if the ICIE bit is set.

This can be avoided if the input capture func-

tion i is disabled by reading the ICiHR (see note

1).

6. The TOF bit can be used with interrupt in order

to measure event that go beyond the timer

range (FFFFh).

76/294

1

ST7MC1/ST7MC2

16-BIT TIMER (Cont’d)

Figure 46. Input Capture Block Diagram

ICAP1

(Control Register 1) CR1

EDGE DETECT

CIRCUIT2

EDGE DETECT

CIRCUIT1

ICIE

IEDG1

ICAP2

(Status Register) SR

ICF1

ICF2

0

IC2R Register

IC1R Register

(Control Register 2) CR2

16-BIT

16-BIT FREE RUNNING

COUNTER

IEDG2

CC0

CC1

Figure 47. Input Capture Timing Diagram

TIMER CLOCK

FF01

FF02

FF03

COUNTER REGISTER

ICAPi PIN

ICAPi FLAG

FF03

ICAPi REGISTER

Note: The active edge is the rising edge.

Note: The time between an event on the ICAPi pin

and the appearance of the corresponding flag is

from 2 to 3 CPU clock cycles. This depends on the

moment when the ICAP event happens relative to

the timer clock.

77/294

1

ST7MC1/ST7MC2

16-BIT TIMER (Cont’d)

9.3.3.4 Output Compare

– The OCMPi pin takes OLVLi bit value (OCMPi

pin latch is forced low during reset).

In this section, the index, i, may be 1 or 2 because

there are 2 output compare functions in the 16-bit

timer.

– A timer interrupt is generated if the OCIE bit is

set in the CR2 register and the I bit is cleared in

the CC register (CC).

This function can be used to control an output

waveform or indicate when a period of time has

elapsed.

The OCiR register value required for a specific tim-

When a match is found between the Output Com-

pare register and the free running counter, the out-

put compare function:

ing application can be calculated using the follow-

ing formula:

– Assigns pins with a programmable value if the

OCIE bit is set

∆t f

* CPU

PRESC

∆

OCiR =

– Sets a flag in the status register

– Generates an interrupt if enabled

Where:

∆

t

= Output compare period (in seconds)

= CPU clock frequency (in hertz)

Two 16-bit registers Output Compare Register 1

(OC1R) and Output Compare Register 2 (OC2R)

contain the value to be compared to the counter

register each timer clock cycle.

f

CPU

= Timer prescaler factor (2, 4 or 8 de-

pending on CC[1:0] bits, see Table 16

Clock Control Bits)

PRESC

MS Byte

LS Byte

OCiR

OCiHR

OCiLR

If the timer clock is an external clock, the formula

is:

These registers are readable and writable and are

not affected by the timer hardware. A reset event

∆

OCiR = ∆t f

* EXT

changes the OC

Timing resolution is one count of the free running

counter: ( ).

iR value to 8000h.

Where:

f

CC[1:0]

CPU/

∆

t

= Output compare period (in seconds)

= External timer clock frequency (in hertz)

f

EXT

Procedure:

To use the output compare function, select the fol-

lowing in the CR2 register:

Clearing the output compare interrupt request (i.e.

clearing the OCFi bit) is done by:

– Set the OCiE bit if an output is needed then the

OCMPi pin is dedicated to the output compare i

signal.

1. Reading the SR register while the OCFi bit is

set.

2. An access (read or write) to the OCiLR register.

– Select the timer clock (CC[1:0]) (see Table 16

Clock Control Bits).

The following procedure is recommended to pre-

vent the OCFi bit from being set between the time

it is read and the write to the OCiR register:

And select the following in the CR1 register:

– Select the OLVLi bit to applied to the OCMPi pins

after the match occurs.

– Write to the OCiHR register (further compares

are inhibited).

– Set the OCIE bit to generate an interrupt if it is

needed.

– Read the SR register (first step of the clearance

of the OCFi bit, which may be already set).

When a match is found between OCRi register

and CR register:

– Write to the OCiLR register (enables the output

compare function and clears the OCFi bit).

– OCFi bit is set.

78/294

1

ST7MC1/ST7MC2

16-BIT TIMER (Cont’d)

Notes:

1. After a processor write cycle to the OCiHR reg-

ister, the output compare function is inhibited

until the OCiLR register is also written.

Forced Compare Output capability

When the FOLVi bit is set by software, the OLVLi

bit is copied to the OCMPi pin. The OLVi bit has to

be toggled in order to toggle the OCMPi pin when

it is enabled (OCiE bit=1). The OCFi bit is then not

set by hardware, and thus no interrupt request is

generated.

2. If the OCiE bit is not set, the OCMPi pin is a

general I/O port and the OLVLi bit will not

appear when a match is found but an interrupt

could be generated if the OCIE bit is set.

3. When the timer clock is f

/2, OCFi and

FOLVLi bits have no effect in both one pulse mode

CPU

OCMPi are set while the counter value equals

the OCiR register value (see Figure 49 on page

80). This behaviour is the same in OPM or

PWM mode.

and PWM mode.

When the timer clock is f

/4, f

/8 or in

CPU

external clock mode, OCFi and OCMPi are set

while the counter value equals the OCiR regis-

ter value plus 1 (see Figure 50 on page 80).

4. The output compare functions can be used both

for generating external events on the OCMPi

pins even if the input capture mode is also

used.

5. The value in the 16-bit OCiR register and the

OLVi bit should be changed after each suc-

cessful comparison in order to control an output

waveform or establish a new elapsed timeout.

Figure 48. Output Compare Block Diagram

16 BIT FREE RUNNING

OC1E

CC1 CC0

OC2E

COUNTER

(Control Register 2) CR2

16-bit

(Control Register 1) CR1

OUTPUT COMPARE

CIRCUIT

Latch

1

OCIE

FOLV2 FOLV1OLVL2

OLVL1

OCMP1

16-bit

Latch

2

OCMP2

OC1R Register

OCF1

OCF2

0

OC2R Register

(Status Register) SR

79/294

1

ST7MC1/ST7MC2

16-BIT TIMER (Cont’d)

Figure 49. Output Compare Timing Diagram, f

=f

/2

TIMER

CPU

INTERNAL CPU CLOCK

TIMER CLOCK

COUNTER REGISTER

2ECF 2ED0 2ED1 2ED2

2ED3

2ED4

2ED3

OUTPUT COMPARE REGISTER i (OCRi)

OUTPUT COMPARE FLAG i (OCFi)

OCMPi PIN (OLVLi=1)

Figure 50. Output Compare Timing Diagram, f

=f

/4

TIMER

CPU

INTERNAL CPU CLOCK

TIMER CLOCK

2ECF 2ED0 2ED1 2ED2

2ED3

2ED4

2ED3

COUNTER REGISTER

OUTPUT COMPARE REGISTER i (OCRi)

COMPARE REGISTER i LATCH

OUTPUT COMPARE FLAG i (OCFi)

OCMPi PIN (OLVLi=1)

80/294

1

ST7MC1/ST7MC2

16-BIT TIMER (Cont’d)

9.3.3.5 One Pulse Mode

Clearing the Input Capture interrupt request (i.e.

clearing the ICFi bit) is done in two steps:

One Pulse mode enables the generation of a

pulse when an external event occurs. This mode is

selected via the OPM bit in the CR2 register.

1. Reading the SR register while the ICFi bit is set.

2. An access (read or write) to the ICiLR register.

The one pulse mode uses the Input Capture1

function and the Output Compare1 function.

The OC1R register value required for a specific

timing application can be calculated using the fol-

lowing formula:

Procedure:

t _*f

To use one pulse mode:

CPU

- 5

OCiR Value =

1. Load the OC1R register with the value corre-

sponding to the length of the pulse (see the for-

mula in the opposite column).

PRESC

Where:

t

= Pulse period (in seconds)

2. Select the following in the CR1 register:

f

= CPU clock frequency (in hertz)

CPU

PRESC

– Using the OLVL1 bit, select the level to be ap-

plied to the OCMP1 pin after the pulse.

= Timer prescaler factor (2, 4 or 8 depend-

ing on the CC[1:0] bits, see Table 16

Clock Control Bits)

– Using the OLVL2 bit, select the level to be ap-

plied to the OCMP1 pin during the pulse.

If the timer clock is an external clock the formula is:

– Select the edge of the active transition on the

ICAP1 pin with the IEDG1 bit (the ICAP1 pin

must be configured as floating input).

OCiR = t f

-5

* EXT

Where:

t

3. Select the following in the CR2 register:

= Pulse period (in seconds)

– Set the OC1E bit, the OCMP1 pin is then ded-

icated to the Output Compare 1 function.

f

= External timer clock frequency (in hertz)

EXT

– Set the OPM bit.

When the value of the counter is equal to the value

of the contents of the OC1R register, the OLVL1

bit is output on the OCMP1 pin, (See Figure 51).

– Select the timer clock CC[1:0] (see Table 16

Clock Control Bits).

One pulse mode cycle

Notes:

ICR1 = Counter

When

1. The OCF1 bit cannot be set by hardware in one

pulse mode but the OCF2 bit can generate an

Output Compare interrupt.

OCMP1 = OLVL2

event occurs

on ICAP1

Counter is reset

2. When the Pulse Width Modulation (PWM) and

One Pulse Mode (OPM) bits are both set, the

PWM mode is the only active one.

to FFFCh

ICF1 bit is set

3. If OLVL1=OLVL2 a continuous signal will be

seen on the OCMP1 pin.

When

Counter

OCMP1 = OLVL1

= OC1R

4. The ICAP1 pin can not be used to perform input

capture. The ICAP2 pin can be used to perform

input capture (ICF2 can be set and IC2R can be

loaded) but the user must take care that the

counter is reset each time a valid edge occurs

on the ICAP1 pin and ICF1 can also generates

interrupt if ICIE is set.

When a valid event occurs on the ICAP1 pin, the

counter value is loaded in the ICR1 register. The

counter is then initialized to FFFCh, the OLVL2 bit

is output on the OCMP1 pin and the ICF1 bit is set.

5. When one pulse mode is used OC1R is dedi-

cated to this mode. Nevertheless OC2R and

OCF2 can be used to indicate a period of time

has been elapsed but cannot generate an out-

put waveform because the level OLVL2 is dedi-

cated to the one pulse mode.

Because the ICF1 bit is set when an active edge

occurs, an interrupt can be generated if the ICIE

bit is set.

81/294

1

ST7MC1/ST7MC2

16-BIT TIMER (Cont’d)

Figure 51. One Pulse Mode Timing Example

2ED3

01F8

IC1R

FFFC FFFD FFFE

2ED0 2ED1 2ED2

2ED3

FFFC FFFD

01F8

COUNTER

ICAP1

OLVL2

OLVL1

OLVL2

OCMP1

compare1

Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1

Figure 52. Pulse Width Modulation Mode Timing Example

2ED0 2ED1 2ED2

34E2 FFFC

FFFC FFFD FFFE

34E2

COUNTER

OCMP1

OLVL2

OLVL1

OLVL2

compare2

compare1

compare2

Note: OC1R=2ED0h, OC2R=34E2, OLVL1=0, OLVL2= 1

82/294

1

ST7MC1/ST7MC2

16-BIT TIMER (Cont’d)

9.3.3.6 Pulse Width Modulation Mode

Clock Control Bits).

Pulse Width Modulation (PWM) mode enables the

generation of a signal with a frequency and pulse

length determined by the value of the OC1R and

OC2R registers.

Pulse Width Modulation cycle

When

Counter

= OC1R

OCMP1 = OLVL1

Pulse Width Modulation mode uses the complete

Output Compare 1 function plus the OC2R regis-

ter, and so this functionality can not be used when

PWM mode is activated.

OCMP1 = OLVL2

When

Counter

= OC2R

In PWM mode, double buffering is implemented on

the output compare registers. Any new values writ-

ten in the OC1R and OC2R registers are loaded in

their respective shadow registers (double buffer)

only at the end of the PWM period (OC2) to avoid

spikes on the PWM output pin (OCMP1). The

shadow registers contain the reference values for

comparison in PWM “double buffering” mode.

Counter is reset

to FFFCh

ICF1 bit is set

If OLVL1=1 and OLVL2=0 the length of the posi-

tive pulse is the difference between the OC2R and

OC1R registers.

If OLVL1=OLVL2 a continuous signal will be seen

on the OCMP1 pin.

Note: There is a locking mechanism for transfer-

ring the OCiR value to the buffer. After a write to

the OCiHR register, transfer of the new compare

value to the buffer is inhibited until OCiLR is also

written.

The OCiR register value required for a specific tim-

ing application can be calculated using the follow-

ing formula:

t _*f

Unlike in Output Compare mode, the compare

function is always enabled in PWM mode.

CPU

- 5

OCiR Value =

PRESC

Where:

t

Procedure

= Signal or pulse period (in seconds)

= CPU clock frequency (in hertz)

f

To use pulse width modulation mode:

CPU

1. Load the OC2R register with the value corre-

sponding to the period of the signal using the

formula in the opposite column.

= Timer prescaler factor (2, 4 or 8 depend-

ing on CC[1:0] bits, see Table 16 Clock

Control Bits)

PRESC

If the timer clock is an external clock the formula is:

2. Load the OC1R register with the value corre-

sponding to the period of the pulse if (OLVL1=0

and OLVL2=1) using the formula in the oppo-

site column.

OCiR = t f

-5

* EXT

Where:

t

3. Select the following in the CR1 register:

= Signal or pulse period (in seconds)

– Using the OLVL1 bit, select the level to be ap-

plied to the OCMP1 pin after a successful

comparison with OC1R register.

f

= External timer clock frequency (in hertz)

EXT

– Using the OLVL2 bit, select the level to be ap-

plied to the OCMP1 pin after a successful

comparison with OC2R register.

The Output Compare 2 event causes the counter

to be initialized to FFFCh (See Figure 52)

Notes:

4. Select the following in the CR2 register:

1. The OCF1 and OCF2 bits cannot be set by

hardware in PWM mode therefore the Output

Compare interrupt is inhibited.

– Set OC1E bit: the OCMP1 pin is then dedicat-

ed to the output compare 1 function.

– Set the PWM bit.

2. The ICF1 bit is set by hardware when the coun-

ter reaches the OC2R value and can produce a

timer interrupt if the ICIE bit is set and the I bit is

cleared.

– Select the timer clock (CC[1:0]) (see Table 16

83/294

1

ST7MC1/ST7MC2

16-BIT TIMER (Cont’d)

3. In PWM mode the ICAP1 pin can not be used

to perform input capture because it is discon-

nected to the timer. The ICAP2 pin can be used

to perform input capture (ICF2 can be set and

IC2R can be loaded) but the user must take

care that the counter is reset each period and

ICF1 can also generates interrupt if ICIE is set.

4. When the Pulse Width Modulation (PWM) and

One Pulse Mode (OPM) bits are both set, the

PWM mode is the only active one.

9.3.4 Low Power Modes

Mode

Description

No effect on 16-bit Timer.

WAIT

Timer interrupts cause the Device to exit from WAIT mode.

16-bit Timer registers are frozen.

In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous

count when the Device is woken up by an interrupt with “exit from HALT mode” capability or from the counter

reset value when the Device is woken up by a RESET.

HALT

If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is armed. Consequent-

ly, when the Device is woken up by an interrupt with “exit from HALT mode” capability, the ICFi bit is set, and

the counter value present when exiting from HALT mode is captured into the ICiR register.

9.3.5 Interrupts

Enable

Control from

Bit

Exit

from

Halt

Event

Flag

Interrupt Event

Wait

Yes

Input Capture 1 event/Counter reset in PWM mode

Input Capture 2 event

ICF1

ICF2

No

ICIE

Output Compare 1 event (not available in PWM mode)

Output Compare 2 event (not available in PWM mode)

Timer Overflow event

OCF1

OCF2

TOF

OCIE

TOIE

Note: The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts chap-

ter). These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt

mask in the CC register is reset (RIM instruction).

9.3.6 Summary of Timer modes

AVAILABLE RESOURCES

MODES

Input Capture 1

Input Capture 2

Yes

Output Compare 1 Output Compare 2

Input Capture (1 and/or 2)

Output Compare (1 and/or 2)

One Pulse Mode

Yes

No

Yes

No

Yes

1)

3)

2)

Not Recommended

Partially

No

PWM Mode

No

1)

2)

3)

See note 4 in Section 9.3.3.5 One Pulse Mode

See note 5 in Section 9.3.3.5 One Pulse Mode

See note 4 in Section 9.3.3.6 Pulse Width Modulation Mode

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ST7MC1/ST7MC2

16-BIT TIMER (Cont’d)

9.3.7 Register Description

Bit 4 = FOLV2 Forced Output Compare 2.

This bit is set and cleared by software.

0: No effect on the OCMP2 pin.

1: Forces the OLVL2 bit to be copied to the

OCMP2 pin, if the OC2E bit is set and even if

there is no successful comparison.

Each Timer is associated with three control and

status registers, and with six pairs of data registers

(16-bit values) relating to the two input captures,

the two output compares, the counter and the al-

ternate counter.

Bit 3 = FOLV1 Forced Output Compare 1.

This bit is set and cleared by software.

0: No effect on the OCMP1 pin.

CONTROL REGISTER 1 (CR1)

Read/Write

1: Forces OLVL1 to be copied to the OCMP1 pin, if

the OC1E bit is set and even if there is no suc-

cessful comparison.

Reset Value: 0000 0000 (00h)

7

0

ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1

Bit 2 = OLVL2 Output Level 2.

This bit is copied to the OCMP2 pin whenever a

successful comparison occurs with the OC2R reg-

ister and OCxE is set in the CR2 register. This val-

ue is copied to the OCMP1 pin in One Pulse Mode

and Pulse Width Modulation mode.

Bit 7 = ICIE Input Capture Interrupt Enable.

0: Interrupt is inhibited.

1: A timer interrupt is generated whenever the

ICF1 or ICF2 bit of the SR register is set.

Bit 6 = OCIE Output Compare Interrupt Enable.

0: Interrupt is inhibited.

1: A timer interrupt is generated whenever the

Bit 1 = IEDG1 Input Edge 1.

This bit determines which type of level transition

on the ICAP1 pin will trigger the capture.

0: A falling edge triggers the capture.

1: A rising edge triggers the capture.

OCF1 or OCF2 bit of the SR register is set.

Bit 5 = TOIE Timer Overflow Interrupt Enable.

0: Interrupt is inhibited.

1: A timer interrupt is enabled whenever the TOF

Bit 0 = OLVL1 Output Level 1.

The OLVL1 bit is copied to the OCMP1 pin when-

ever a successful comparison occurs with the

OC1R register and the OC1E bit is set in the CR2

register.

bit of the SR register is set.

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ST7MC1/ST7MC2

16-BIT TIMER (Cont’d)

CONTROL REGISTER 2 (CR2)

Read/Write

Bit 4 = PWM Pulse Width Modulation.

0: PWM mode is not active.

1: PWM mode is active, the OCMP1 pin outputs a

programmable cyclic signal; the length of the

pulse depends on the value of OC1R register;

the period depends on the value of OC2R regis-

ter.

Reset Value: 0000 0000 (00h)

7

0

OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG

Bit 3, 2 = CC[1:0] Clock Control.

Bit 7 = OC1E Output Compare 1 Pin Enable.

This bit is used only to output the signal from the

timer on the OCMP1 pin (OLV1 in Output Com-

pare mode, both OLV1 and OLV2 in PWM and

one-pulse mode). Whatever the value of the OC1E

bit, the Output Compare 1 function of the timer re-

mains active.

0: OCMP1 pin alternate function disabled (I/O pin

free for general-purpose I/O).

1: OCMP1 pin alternate function enabled.

The timer clock mode depends on these bits:

Table 16. Clock Control Bits

Timer Clock

f_CPU/ 4

CC1

CC0

0

1

0

1

0

f_CPU/ 2

f_CPU/ 8

External Clock (where

available)

1

Bit 6 = OC2E Output Compare 2 Pin Enable.

This bit is used only to output the signal from the

timer on the OCMP2 pin (OLV2 in Output Com-

pare mode). Whatever the value of the OC2E bit,

the Output Compare 2 function of the timer re-

mains active.

0: OCMP2 pin alternate function disabled (I/O pin

free for general-purpose I/O).

1: OCMP2 pin alternate function enabled.

Note: If the external clock pin is not available, pro-

gramming the external clock configuration stops

the counter.

Bit 1 = IEDG2 Input Edge 2.

This bit determines which type of level transition

on the ICAP2 pin will trigger the capture.

0: A falling edge triggers the capture.

1: A rising edge triggers the capture.

Bit 5 = OPM One Pulse Mode.

0: One Pulse Mode is not active.

Bit 0 = EXEDG External Clock Edge.

1: One Pulse Mode is active, the ICAP1 pin can be

used to trigger one pulse on the OCMP1 pin; the

active transition is given by the IEDG1 bit. The

length of the generated pulse depends on the

contents of the OC1R register.

This bit determines which type of level transition

on the external clock pin EXTCLK will trigger the

counter register.

0: A falling edge triggers the counter register.

1: A rising edge triggers the counter register.

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ST7MC1/ST7MC2

16-BIT TIMER (Cont’d)

CONTROL/STATUS REGISTER (CSR)

Read Only

Note: Reading or writing the ACLR register does

not clear TOF.

Reset Value: 0000 0000 (00h)

The three least significant bits are not used.

7

Bit 4 = ICF2 Input Capture Flag 2.

0: No input capture (reset value).

1: An input capture has occurred on the ICAP2

pin. To clear this bit, first read the SR register,

then read or write the low byte of the IC2R

(IC2LR) register.

0

ICF1 OCF1 TOF ICF2 OCF2 TIMD

0

Bit 7 = ICF1 Input Capture Flag 1.

0: No input capture (reset value).

1: An input capture has occurred on the ICAP1 pin

or the counter has reached the OC2R value in

PWM mode. To clear this bit, first read the SR

register, then read or write the low byte of the

IC1R (IC1LR) register.

Bit 3 = OCF2 Output Compare Flag 2.

0: No match (reset value).

1: The content of the free running counter has

matched the content of the OC2R register. To

clear this bit, first read the SR register, then read

or write the low byte of the OC2R (OC2LR) reg-

ister.

Bit 6 = OCF1 Output Compare Flag 1.

0: No match (reset value).

1: The content of the free running counter has

matched the content of the OC1R register. To

clear this bit, first read the SR register, then read

or write the low byte of the OC1R (OC1LR) reg-

ister.

Bit 2 = TIMD Timer disable.

This bit is set and cleared by software. When set, it

freezes the timer prescaler and counter and disa-

bled the output functions (OCMP1 and OCMP2

pins) to reduce power consumption. Access to the

timer registers is still available, allowing the timer

configuration to be changed while it is disabled.

0: Timer enabled

Bit 5 = TOF Timer Overflow Flag.

0: No timer overflow (reset value).

1: Timer prescaler, counter and outputs disabled

1:The free running counter rolled over from FFFFh

to 0000h. To clear this bit, first read the SR reg-

ister, then read or write the low byte of the CR

(CLR) register.

Bits 1:0 = Reserved, must be kept cleared.

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ST7MC1/ST7MC2

16-BIT TIMER (Cont’d)

INPUT CAPTURE 1 HIGH REGISTER (IC1HR)

OUTPUT COMPARE

(OC1HR)

1

HIGH REGISTER

Read Only

Reset Value: Undefined

Read/Write

Reset Value: 1000 0000 (80h)

This is an 8-bit read only register that contains the

high part of the counter value (transferred by the

input capture 1 event).

This is an 8-bit register that contains the high part

of the value to be compared to the CHR register.

7

0

7

0

MSB

LSB

MSB

LSB

INPUT CAPTURE 1 LOW REGISTER (IC1LR)

OUTPUT COMPARE

(OC1LR)

1

LOW REGISTER

Read Only

Reset Value: Undefined

Read/Write

Reset Value: 0000 0000 (00h)

This is an 8-bit read only register that contains the

low part of the counter value (transferred by the in-

put capture 1 event).

This is an 8-bit register that contains the low part of

the value to be compared to the CLR register.

7

0

7

0

MSB

LSB

MSB

LSB

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1

ST7MC1/ST7MC2

16-BIT TIMER (Cont’d)

OUTPUT COMPARE

(OC2HR)

2

HIGH REGISTER

ALTERNATE COUNTER HIGH REGISTER

(ACHR)

Read/Write

Reset Value: 1000 0000 (80h)

Read Only

Reset Value: 1111 1111 (FFh)

This is an 8-bit register that contains the high part

of the value to be compared to the CHR register.

This is an 8-bit register that contains the high part

of the counter value.

7

0

7

0

MSB

LSB

MSB

LSB

OUTPUT COMPARE

(OC2LR)

2

LOW REGISTER

ALTERNATE COUNTER LOW REGISTER

(ACLR)

Read/Write

Reset Value: 0000 0000 (00h)

Read Only

Reset Value: 1111 1100 (FCh)

This is an 8-bit register that contains the low part of

the value to be compared to the CLR register.

This is an 8-bit register that contains the low part of

the counter value. A write to this register resets the

counter. An access to this register after an access

to CSR register does not clear the TOF bit in the

CSR register.

7

0

MSB

LSB

7

0

COUNTER HIGH REGISTER (CHR)

MSB

LSB

Read Only

Reset Value: 1111 1111 (FFh)

INPUT CAPTURE 2 HIGH REGISTER (IC2HR)

This is an 8-bit register that contains the high part

of the counter value.

Read Only

Reset Value: Undefined

7

0

This is an 8-bit read only register that contains the

high part of the counter value (transferred by the

Input Capture 2 event).

MSB

LSB

7

0

MSB

LSB

COUNTER LOW REGISTER (CLR)

Read Only

Reset Value: 1111 1100 (FCh)

This is an 8-bit register that contains the low part of

the counter value. A write to this register resets the

counter. An access to this register after accessing

the CSR register clears the TOF bit.

INPUT CAPTURE 2 LOW REGISTER (IC2LR)

Read Only

Reset Value: Undefined

This is an 8-bit read only register that contains the

low part of the counter value (transferred by the In-

put Capture 2 event).

7

0

MSB

LSB

7

0

MSB

LSB

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ST7MC1/ST7MC2

16-BIT TIMER (Cont’d)

Table 17. 16-Bit Timer Register Map and Reset Values

Address

(Hex.)

Register

Label

7

6

5

4

3

2

1

0

Timer A: 32 CR1

Timer B: 42 Reset Value

ICIE

0

OCIE

0

TOIE

0

FOLV2

0

FOLV1

0

OLVL2

0

IEDG1

0

OLVL1

0

Timer A: 31 CR2

Timer B: 41 Reset Value

OC1E

0

OC2E

0

OPM

0

PWM

0

CC1

0

CC0

0

IEDG2

0

EXEDG

0

OCF1

0

Timer A: 33 CSR

Timer B: 43 Reset Value

ICF1

0

TOF

0

ICF2

0

OCF2

0

TIMD

0

-

0

-

0

Timer A: 34 ICHR1

Timer B: 44 Reset Value

MSB

-

LSB

-

Timer A: 35 ICLR1

Timer B: 45 Reset Value

MSB

-

LSB

-

Timer A: 36 OCHR1

Timer B: 46 Reset Value

MSB

-

LSB

-

Timer A: 37 OCLR1

Timer B: 47 Reset Value

MSB

-

LSB

-

Timer A: 3E OCHR2

Timer B: 4E Reset Value

MSB

-

LSB

-

Timer A: 3F OCLR2

Timer B: 4F Reset Value

MSB

-

LSB

-

Timer A: 38 CHR

Timer B: 48 Reset Value

MSB

1

LSB

1

0

1

Timer A: 39 CLR

Timer B: 49 Reset Value

MSB

1

LSB

0

Timer A: 3A ACHR

Timer B: 4A Reset Value

MSB

1

LSB

1

Timer A: 3B ACLR

Timer B: 4B Reset Value

MSB

1

LSB

0

1

-

1

-

1

-

1

-

1

-

0

-

Timer A: 3C ICHR2

Timer B: 4C Reset Value

MSB

-

LSB

-

Timer A: 3D ICLR2

Timer B: 4D Reset Value

MSB

-

LSB

-

90/294

1

ST7MC1/ST7MC2

9.4 SERIAL PERIPHERAL INTERFACE (SPI)

9.4.1 Introduction

9.4.3 General Description

The Serial Peripheral Interface (SPI) allows full-

duplex, synchronous, serial communication with

external devices. An SPI system may consist of a

master and one or more slaves or a system in

which devices may be either masters or slaves.

Figure 53 shows the serial peripheral interface

(SPI) block diagram. There are 3 registers:

– SPI Control Register (SPICR)

– SPI Control/Status Register (SPICSR)

– SPI Data Register (SPIDR)

9.4.2 Main Features

ꢀ

Full duplex synchronous transfers (on 3 lines)

Simplex synchronous transfers (on 2 lines)

Master or slave operation

The SPI is connected to external devices through

4 pins:

– MISO: Master In / Slave Out data

– MOSI: Master Out / Slave In data

Six master mode frequencies (f

/4 max.)

CPU

f

/2 max. slave mode frequency (see note)

CPU

– SCK: Serial Clock out by SPI masters and in-

put by SPI slaves

SS Management by software or hardware

Programmable clock polarity and phase

End of transfer interrupt flag

– SS: Slave select:

This input signal acts as a ‘chip select’ to let

the SPI master communicate with slaves indi-

vidually and to avoid contention on the data

lines. Slave SS inputs can be driven by stand-

Write collision, Master Mode Fault and Overrun

flags

Note: In slave mode, continuous transmission is

not possible at maximum frequency due to the

software overhead for clearing status flags and to

initiate the next transmission sequence.

ard I/O ports on the master Device

.

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1

ST7MC1/ST7MC2

Figure 53. Serial Peripheral Interface Block Diagram

Data/Address Bus

Read

SPIDR

Interrupt

request

Read Buffer

MOSI

7

0

SPICSR

MISO

8-Bit Shift Register

SPIF WCOL OVR MODF

SOD SSM SSI

0

Write

SOD

bit

1

SS

SPI

STATE

0

SCK

CONTROL

7

0

SPICR

MSTR

SPR0

CPHA SPR1

SPR2

SPIE SPE

CPOL

MASTER

CONTROL

SERIAL CLOCK

GENERATOR

SS

92/294

1

ST7MC1/ST7MC2

SERIAL PERIPHERAL INTERFACE (Cont’d)

9.4.3.1 Functional Description

sponds by sending data to the master device via

the MISO pin. This implies full duplex communica-

tion with both data out and data in synchronized

with the same clock signal (which is provided by

the master device via the SCK pin).

A basic example of interconnections between a

single master and a single slave is illustrated in

Figure 54.

The MOSI pins are connected together and the

MISO pins are connected together. In this way

data is transferred serially between master and

slave (most significant bit first).

To use a single data line, the MISO and MOSI pins

must be connected at each node ( in this case only

simplex communication is possible).

Four possible data/clock timing relationships may

be chosen (see Figure 57) but master and slave

must be programmed with the same timing mode.

The communication is always initiated by the mas-

ter. When the master device transmits data to a

slave device via MOSI pin, the slave device re-

Figure 54. Single Master/ Single Slave Application

SLAVE

MASTER

MSBit

LSBit

MSBit

LSBit

MISO

MOSI

MISO

MOSI

8-BIT SHIFT REGISTER

SPI

CLOCK

GENERATOR

SCK

SS

SCK

SS

+5V

Not used if SS is managed

by software

93/294

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ST7MC1/ST7MC2

SERIAL PERIPHERAL INTERFACE (Cont’d)

9.4.3.2 Slave Select Management

In Slave Mode:

As an alternative to using the SS pin to control the

Slave Select signal, the application can choose to

manage the Slave Select signal by software. This

is configured by the SSM bit in the SPICSR regis-

ter (see Figure 56)

There are two cases depending on the data/clock

timing relationship (see Figure 55):

If CPHA=1 (data latched on 2nd clock edge):

– SS internal must be held low during the entire

transmission. This implies that in single slave

applications the SS pin either can be tied to

In software management, the external SS pin is

free for other application uses and the internal SS

signal level is driven by writing to the SSI bit in the

SPICSR register.

V

, or made free for standard I/O by manag-

SS

ing the SS function by software (SSM= 1 and

SSI=0 in the in the SPICSR register)

If CPHA=0 (data latched on 1st clock edge):

In Master mode:

– SS internal must be held low during byte

transmission and pulled high between each

byte to allow the slave to write to the shift reg-

ister. If SS is not pulled high, a Write Collision

error will occur when the slave writes to the

shift register (see Section 9.4.5.3).

– SS internal must be held high continuously

Figure 55. Generic SS Timing Diagram

Byte 3

Byte 2

MOSI/MISO

Master SS

Byte 1

Slave SS

(if CPHA=0)

Slave SS

(if CPHA=1)

Figure 56. Hardware/Software Slave Select Management

SSM bit

SSI bit

1

0

SS internal

SS external pin

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ST7MC1/ST7MC2

SERIAL PERIPHERAL INTERFACE (Cont’d)

9.4.3.3 Master Mode Operation

Note: While the SPIF bit is set, all writes to the

SPIDR register are inhibited until the SPICSR reg-

ister is read.

In master mode, the serial clock is output on the

SCK pin. The clock frequency, polarity and phase

are configured by software (refer to the description

of the SPICSR register).

9.4.3.5 Slave Mode Operation

In slave mode, the serial clock is received on the

SCK pin from the master device.

Note: The idle state of SCK must correspond to

the polarity selected in the SPICSR register (by

pulling up SCK if CPOL=1 or pulling down SCK if

CPOL=0).

To operate the SPI in slave mode:

1. Write to the SPICSR register to perform the fol-

lowing actions:

To operate the SPI in master mode, perform the

following steps in order (if the SPICSR register is

not written first, the SPICR register setting (MSTR

bit ) may be not taken into account):

– Select the clock polarity and clock phase by

configuring the CPOL and CPHA bits (see

Figure 57).

Note: The slave must have the same CPOL

and CPHA settings as the master.

1. Write to the SPICR register:

– Manage the SS pin as described in Section

9.4.3.2 and Figure 55. If CPHA=1 SS must be

held low continuously. If CPHA=0 SS must be

held low during byte transmission and pulled

up between each byte to let the slave write in

the shift register.

– Select the clock frequency by configuring the

SPR[2:0] bits.

– Select the clock polarity and clock phase by

configuring the CPOL and CPHA bits. Figure

57 shows the four possible configurations.

Note: The slave must have the same CPOL

and CPHA settings as the master.

2. Write to the SPICR register to clear the MSTR

bit and set the SPE bit to enable the SPI I/O

functions.

2. Write to the SPICSR register:

– Either set the SSM bit and set the SSI bit or

clear the SSM bit and tie the SS pin high for

the complete byte transmit sequence.

9.4.3.6 Slave Mode Transmit Sequence

When software writes to the SPIDR register, the

data byte is loaded into the 8-bit shift register and

then shifted out serially to the MISO pin most sig-

nificant bit first.

3. Write to the SPICR register:

– Set the MSTR and SPE bits

Note: MSTR and SPE bits remain set only if

SS is high).

The transmit sequence begins when the slave de-

vice receives the clock signal and the most signifi-

cant bit of the data on its MOSI pin.

The transmit sequence begins when software

writes a byte in the SPIDR register.

9.4.3.4 Master Mode Transmit Sequence

When data transfer is complete:

When software writes to the SPIDR register, the

data byte is loaded into the 8-bit shift register and

then shifted out serially to the MOSI pin most sig-

nificant bit first.

– The SPIF bit is set by hardware

– An interrupt request is generated if SPIE bit is

set and interrupt mask in the CCR register is

cleared.

When data transfer is complete:

Clearing the SPIF bit is performed by the following

software sequence:

– The SPIF bit is set by hardware

– An interrupt request is generated if the SPIE

bit is set and the interrupt mask in the CCR

register is cleared.

1. An access to the SPICSR register while the

SPIF bit is set.

2. A write or a read to the SPIDR register.

Clearing the SPIF bit is performed by the following

software sequence:

Notes: While the SPIF bit is set, all writes to the

SPIDR register are inhibited until the SPICSR reg-

ister is read.

1. An access to the SPICSR register while the

SPIF bit is set

The SPIF bit can be cleared during a second

transmission; however, it must be cleared before

the second SPIF bit in order to prevent an Overrun

condition (see Section 9.4.5.2).

2. A read to the SPIDR register.

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ST7MC1/ST7MC2

SERIAL PERIPHERAL INTERFACE (Cont’d)

9.4.4 Clock Phase and Clock Polarity

Figure 57, shows an SPI transfer with the four

combinations of the CPHA and CPOL bits. The di-

agram may be interpreted as a master or slave

timing diagram where the SCK pin, the MISO pin,

the MOSI pin are directly connected between the

master and the slave device.

Four possible timing relationships may be chosen

by software, using the CPOL and CPHA bits (See

Figure 57).

Note: The idle state of SCK must correspond to

the polarity selected in the SPICSR register (by

pulling up SCK if CPOL=1 or pulling down SCK if

CPOL=0).

Note: If CPOL is changed at the communication

byte boundaries, the SPI must be disabled by re-

setting the SPE bit.

The combination of the CPOL clock polarity and

CPHA (clock phase) bits selects the data capture

clock edge

Figure 57. Data Clock Timing Diagram

CPHA =1

SCK

(CPOL = 1)

SCK

(CPOL = 0)

Bit 4

Bit3

Bit 2

Bit 1

LSBit

MSBit Bit 6

Bit 5

MISO

(from master)

MOSI

(from slave)

SS

(to slave)

CAPTURE STROBE

CPHA =0

SCK

(CPOL = 1)

SCK

(CPOL = 0)

Bit 4

Bit3

Bit 2

Bit 1

LSBit

MISO

(from master)

MSBit Bit 6

Bit 5

Bit3

MOSI

(from slave)

SS

(to slave)

CAPTURE STROBE

Note: This figure should not be used as a replacement for parametric information.

Refer to the Electrical Characteristics chapter.

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ST7MC1/ST7MC2

SERIAL PERIPHERAL INTERFACE (Cont’d)

9.4.5 Error Flags

9.4.5.2 Overrun Condition (OVR)

9.4.5.1 Master Mode Fault (MODF)

An overrun condition occurs, when the master de-

vice has sent a data byte and the slave device has

not cleared the SPIF bit issued from the previously

transmitted byte.

Master mode fault occurs when the master device

has its SS pin pulled low.

When a Master mode fault occurs:

When an Overrun occurs:

– The MODF bit is set and an SPI interrupt re-

quest is generated if the SPIE bit is set.

– The OVR bit is set and an interrupt request is

generated if the SPIE bit is set.

– The SPE bit is reset. This blocks all output

from the Device and disables the SPI periph-

eral.

In this case, the receiver buffer contains the byte

sent after the SPIF bit was last cleared. A read to

the SPIDR register returns this byte. All other

bytes are lost.

– The MSTR bit is reset, thus forcing the Device

into slave mode.

The OVR bit is cleared by reading the SPICSR

register.

Clearing the MODF bit is done through a software

sequence:

9.4.5.3 Write Collision Error (WCOL)

1. A read access to the SPICSR register while the

MODF bit is set.

A write collision occurs when the software tries to

write to the SPIDR register while a data transfer is

taking place with an external device. When this

happens, the transfer continues uninterrupted;

and the software write will be unsuccessful.

2. A write to the SPICR register.

Notes: To avoid any conflicts in an application

with multiple slaves, the SS pin must be pulled

high during the MODF bit clearing sequence. The

SPE and MSTR bits may be restored to their orig-

inal state during or after this clearing sequence.

Write collisions can occur both in master and slave

mode. See also Section 9.4.3.2 Slave Select Man-

agement.

Hardware does not allow the user to set the SPE

and MSTR bits while the MODF bit is set except in

the MODF bit clearing sequence.

Note: a "read collision" will never occur since the

received data byte is placed in a buffer in which

access is always synchronous with the CPU oper-

ation.

In a slave device, the MODF bit can not be set, but

in a multi master configuration the Device can be in

slave mode with the MODF bit set.

The WCOL bit in the SPICSR register is set if a

write collision occurs.

The MODF bit indicates that there might have

been a multi-master conflict and allows software to

handle this using an interrupt routine and either

perform to a reset or return to an application de-

fault state.

No SPI interrupt is generated when the WCOL bit

is set (the WCOL bit is a status flag only).

Clearing the WCOL bit is done through a software

sequence (see Figure 58).

Figure 58. Clearing the WCOL bit (Write Collision Flag) Software Sequence

Clearing sequence after SPIF = 1 (end of a data byte transfer)

Read SPICSR

1st Step

RESULT

SPIF =0

WCOL=0

2nd Step

Read SPIDR

Clearing sequence before SPIF = 1 (during a data byte transfer)

Read SPICSR

1st Step

Note: Writing to the SPIDR regis-

RESULT

ter instead of reading it does not

reset the WCOL bit

2nd Step

Read SPIDR

WCOL=0

97/294

1

ST7MC1/ST7MC2

SERIAL PERIPHERAL INTERFACE (Cont’d)

9.4.5.4 Single Master and Multimaster

Configurations

For more security, the slave device may respond

to the master with the received data byte. Then the

master will receive the previous byte back from the

slave device if all MISO and MOSI pins are con-

nected and the slave has not written to its SPIDR

register.

There are two types of SPI systems:

– Single Master System

– Multimaster System

Other transmission security methods can use

ports for handshake lines or data bytes with com-

mand fields.

Single Master System

A typical single master system may be configured,

using a device as the master and four devices as

slaves (see Figure 59).

Multi-Master System

A multi-master system may also be configured by

the user. Transfer of master control could be im-

plemented using a handshake method through the

I/O ports or by an exchange of code messages

through the serial peripheral interface system.

The master device selects the individual slave de-

vices by using four pins of a parallel port to control

the four SS pins of the slave devices.

The SS pins are pulled high during reset since the

master device ports will be forced to be inputs at

that time, thus disabling the slave devices.

The multi-master system is principally handled by

the MSTR bit in the SPICR register and the MODF

bit in the SPICSR register.

Note: To prevent a bus conflict on the MISO line

the master allows only one active slave device

during a transmission.

Figure 59. Single Master / Multiple Slave Configuration

SS

SCK

Slave

SCK

Slave

SCK

Slave

Device

MOSI MISO

SCK

Master

Device

5V

SS

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1

ST7MC1/ST7MC2

SERIAL PERIPHERAL INTERFACE (Cont’d)

9.4.6 Low Power Modes

SS pin or the SSI bit in the SPICSR register) is low

when the Device enters Halt mode. So if Slave se-

lection is configured as external (see Section

9.4.3.2), make sure the master drives a low level

on the SS pin when the slave enters Halt mode.

Mode

Description

No effect on SPI.

WAIT

SPI interrupt events cause the Device to exit

from WAIT mode.

9.4.7 Interrupts

SPI registers are frozen.

In HALT mode, the SPI is inactive. SPI oper-

ation resumes when the Device is woken up

by an interrupt with “exit from HALT mode”

capability. The data received is subsequently

read from the SPIDR register when the soft-

ware is running (interrupt vector fetching). If

several data are received before the wake-

up event, then an overrun error is generated.

This error can be detected after the fetch of

the interrupt routine that woke up the Device.

Enable

Control from

Bit

Exit

from

Halt

Event

Flag

Interrupt Event

Wait

SPI End of Trans-

fer Event

HALT

SPIF

Yes

Master Mode

Fault Event

SPIE

MODF

OVR

Yes

No

Overrun Error

Note: The SPI interrupt events are connected to

the same interrupt vector (see Interrupts chapter).

They generate an interrupt if the corresponding

Enable Control Bit is set and the interrupt mask in

the CC register is reset (RIM instruction).

9.4.6.1 Using the SPI to wake-up the Device

from Halt mode

In slave configuration, the SPI is able to wake-up

the Device from HALT mode through a SPIF inter-

rupt. The data received is subsequently read from

the SPIDR register when the software is running

(interrupt vector fetch). If multiple data transfers

have been performed before software clears the

SPIF bit, then the OVR bit is set by hardware.

Note: When waking up from Halt mode, if the SPI

remains in Slave mode, it is recommended to per-

form an extra communications cycle to bring the

SPI from Halt mode state to normal state. If the

SPI exits from Slave mode, it returns to normal

state immediately.

Caution: The SPI can wake-up the Device from

Halt mode only if the Slave Select signal (external

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1

ST7MC1/ST7MC2

SERIAL PERIPHERAL INTERFACE (Cont’d)

9.4.8 Register Description

CONTROL REGISTER (SPICR)

Read/Write

Bit 3 = CPOL Clock Polarity.

This bit is set and cleared by software. This bit de-

termines the idle state of the serial Clock. The

CPOL bit affects both the master and slave

modes.

Reset Value: 0000 xxxx (0xh)

7

0

0: SCK pin has a low level idle state

1: SCK pin has a high level idle state

SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0

Note: If CPOL is changed at the communication

byte boundaries, the SPI must be disabled by re-

setting the SPE bit.

Bit 7 = SPIE Serial Peripheral Interrupt Enable.

This bit is set and cleared by software.

0: Interrupt is inhibited

1: An SPI interrupt is generated whenever an End

of Transfer event, Master Mode Fault or Over-

run error occurs (SPIF=1, MODF=1 or OVR=1

in the SPICSR register)

Bit 2 = CPHA Clock Phase.

This bit is set and cleared by software.

0: The first clock transition is the first data capture

edge.

1: The second clock transition is the first capture

edge.

Note: The slave must have the same CPOL and

CPHA settings as the master.

Bit 6 = SPE Serial Peripheral Output Enable.

This bit is set and cleared by software. It is also

cleared by hardware when, in master mode, SS=0

(see Section 9.4.5.1 Master Mode Fault (MODF)).

The SPE bit is cleared by reset, so the SPI periph-

eral is not initially connected to the external pins.

0: I/O pins free for general purpose I/O

Bits 1:0 = SPR[1:0] Serial Clock Frequency.

These bits are set and cleared by software. Used

with the SPR2 bit, they select the baud rate of the

SPI serial clock SCK output by the SPI in master

mode.

1: SPI I/O pin alternate functions enabled

Note: These 2 bits have no effect in slave mode.

Bit 5 = SPR2 Divider Enable.

Table 18. SPI Master mode SCK Frequency

This bit is set and cleared by software and is

cleared by reset. It is used with the SPR[1:0] bits to

set the baud rate. Refer to Table 18 SPI Master

mode SCK Frequency.

0: Divider by 2 enabled

1: Divider by 2 disabled

Serial Clock

SPR2 SPR1 SPR0

f

/4

/8

1

0

1

0

1

0

1

0

1

CPU

f

/16

/32

/64

CPU

Note: This bit has no effect in slave mode.

Bit 4 = MSTR Master Mode.

f

/128

This bit is set and cleared by software. It is also

cleared by hardware when, in master mode, SS=0

(see Section 9.4.5.1 Master Mode Fault (MODF)).

0: Slave mode

CPU

1: Master mode. The function of the SCK pin

changes from an input to an output and the func-

tions of the MISO and MOSI pins are reversed.

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1

ST7MC1/ST7MC2

SERIAL PERIPHERAL INTERFACE (Cont’d)

CONTROL/STATUS REGISTER (SPICSR)

Read/Write (some bits Read Only)

Reset Value: 0000 0000 (00h)

Bit 2 = SOD SPI Output Disable.

This bit is set and cleared by software. When set, it

disables the alternate function of the SPI output

(MOSI in master mode / MISO in slave mode)

0: SPI output enabled (if SPE=1)

7

0

SPIF

WCOL OVR MODF

-

SOD SSM SSI

1: SPI output disabled

Bit 7 = SPIF Serial Peripheral Data Transfer Flag

(Read only).

Bit 1 = SSM SS Management.

This bit is set and cleared by software. When set, it

disables the alternate function of the SPI SS pin

and uses the SSI bit value instead. See Section

9.4.3.2 Slave Select Management.

0: Hardware management (SS managed by exter-

nal pin)

1: Software management (internal SS signal con-

trolled by SSI bit. External SS pin free for gener-

al-purpose I/O)

This bit is set by hardware when a transfer has

been completed. An interrupt is generated if

SPIE=1 in the SPICR register. It is cleared by a

software sequence (an access to the SPICSR

register followed by a write or a read to the

SPIDR register).

0: Data transfer is in progress or the flag has been

cleared.

1: Data transfer between the Device and an exter-

nal device has been completed.

Bit 0 = SSI SS Internal Mode.

Note: While the SPIF bit is set, all writes to the

SPIDR register are inhibited until the SPICSR reg-

ister is read.

This bit is set and cleared by software. It acts as a

‘chip select’ by controlling the level of the SS slave

select signal when the SSM bit is set.

0 : Slave selected

Bit 6 = WCOL Write Collision status (Read only).

This bit is set by hardware when a write to the

SPIDR register is done during a transmit se-

quence. It is cleared by a software sequence (see

Figure 58).

1 : Slave deselected

DATA I/O REGISTER (SPIDR)

Read/Write

Reset Value: Undefined

0: No write collision occurred

1: A write collision has been detected

7

0

D7

D6

D5

D4

D3

D2

D1

D0

Bit 5 = OVR SPI Overrun error (Read only).

This bit is set by hardware when the byte currently

being received in the shift register is ready to be

transferred into the SPIDR register while SPIF = 1

(See Section 9.4.5.2). An interrupt is generated if

SPIE = 1 in the SPICR register. The OVR bit is

cleared by software reading the SPICSR register.

0: No overrun error

The SPIDR register is used to transmit and receive

data on the serial bus. In a master device, a write

to this register will initiate transmission/reception

of another byte.

Notes: During the last clock cycle the SPIF bit is

set, a copy of the received data byte in the shift

register is moved to a buffer. When the user reads

the serial peripheral data I/O register, the buffer is

actually being read.

1: Overrun error detected

Bit 4 = MODF Mode Fault flag (Read only).

This bit is set by hardware when the SS pin is

pulled low in master mode (see Section 9.4.5.1

Master Mode Fault (MODF)). An SPI interrupt can

be generated if SPIE=1 in the SPICR register. This

bit is cleared by a software sequence (An access

to the SPICSR register while MODF=1 followed by

a write to the SPICR register).

While the SPIF bit is set, all writes to the SPIDR

register are inhibited until the SPICSR register is

read.

Warning: A write to the SPIDR register places

data directly into the shift register for transmission.

A read to the SPIDR register returns the value lo-

cated in the buffer and not the content of the shift

register (see Figure 53).

0: No master mode fault detected

1: A fault in master mode has been detected

Bit 3 = Reserved, must be kept cleared.

101/294

1

ST7MC1/ST7MC2

SERIAL PERIPHERAL INTERFACE (Cont’d)

Table 19. SPI Register Map and Reset Values

Address

(Hex.)

Register

Label

7

6

5

4

3

2

1

0

SPIDR

Reset Value

MSB

x

LSB

x

0021h

0022h

0023h

x

SPICR

Reset Value

SPIE

0

SPE

0

SPR2

0

MSTR

0

CPOL

x

CPHA

x

SPR1

x

SPR0

x

SPICSR

Reset Value

SPIF

0

WCOL

0

OR

0

MODF

0

SOD

0

SSM

0

SSI

0

102/294

1

ST7MC1/ST7MC2

9.5 LINSCI SERIAL COMMUNICATION INTERFACE (LIN MASTER/SLAVE)

9.5.1 Introduction

ꢀ

Six interrupt sources

The Serial Communications Interface (SCI) offers

a flexible means of full-duplex data exchange with

external equipment requiring an industry standard

NRZ asynchronous serial data format. The SCI of-

fers a very wide range of baud rates using two

baud rate generator systems.

– Transmit data register empty

– Transmission complete

– Receive data register full

– Idle line received

– Overrun error

The LIN-dedicated features support the LIN (Local

Interconnect Network) protocol for both master

and slave nodes.

– Parity interrupt

Parity control:

ꢀ

– Transmits parity bit

This chapter is divided into SCI Mode and LIN

mode sections. For information on general SCI

communications, refer to the SCI mode section.

For LIN applications, refer to both the SCI mode

and LIN mode sections.

– Checks parity of received data byte

Reduced power consumption mode

9.5.3 LIN Features

– LIN Master

9.5.2 SCI Features

– 13-bit LIN Synch Break generation

– LIN Slave

ꢀ

Full duplex, asynchronous communications

NRZ standard format (Mark/Space)

Independently programmable transmit and

receive baud rates up to 500K baud.

– Automatic Header Handling

– Automatic baud rate re-synchronization

based on recognition and measurement of the

LIN Synch Field (for LIN slave nodes)

ꢀ

Programmable data word length (8 or 9 bits)

Receive buffer full, Transmit buffer empty and

End of Transmission flags

Two receiver wake-up modes:

– Address bit (MSB)

– Automatic baud rate adjustment (at CPU fre-

quency precision)

ꢀ

– 11-bit LIN Synch Break detection capability

– LIN Parity check on the LIN Identifier Field

(only in reception)

– Idle line

ꢀ

Mutingfunctionformultiprocessorconfigurations

– LIN Error management

– LIN Header Timeout

– Hot plugging support

Separate enable bits for Transmitter and

Receiver

Overrun, Noise and Frame error detection

ꢀ

103/294

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ST7MC1/ST7MC2

LINSCI SERIAL COMMUNICATION INTERFACE (Cont’d)

9.5.4 General Description

– A conventional type for commonly-used baud

rates.

The interface is externally connected to another

device by two pins:

– An extended type with a prescaler offering a very

wide range of baud rates even with non-standard

oscillator frequencies.

– TDO: Transmit Data Output. When the transmit-

ter is disabled, the output pin returns to its I/O

port configuration. When the transmitter is ena-

bled and nothing is to be transmitted, the TDO

pin is at high level.

– A LIN baud rate generator with automatic resyn-

chronization.

– RDI: Receive Data Input is the serial data input.

Oversampling techniques are used for data re-

covery by discriminating between valid incoming

data and noise.

Through these pins, serial data is transmitted and

received as characters comprising:

– An Idle Line prior to transmission or reception

– A start bit

– A data word (8 or 9 bits) least significant bit first

– A Stop bit indicating that the character is com-

plete.

This interface uses three types of baud rate gener-

ator:

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ST7MC1/ST7MC2

LINSCI SERIAL COMMUNICATION INTERFACE (SCI Mode) (Cont’d)

Figure 60. SCI Block Diagram (in Conventional Baud Rate Generator Mode)

Write

Read

(DATA REGISTER) SCIDR

Received Data Register (RDR)

Receive Shift Register

Transmit Data Register (TDR)

TDO

RDI

Transmit Shift Register

SCICR1

PCE

R8

SCID

T8

M

WAKE

PS PIE

WAKE

UP

UNIT

TRANSMIT

CONTROL

RECEIVER

CLOCK

RECEIVER

CONTROL

SCISR

SCICR2

OR/

LHE

TIE TCIE RIE ILIE TE RE RWU SBK

NF

TDRE

RDRF

IDLE

TC

FE

PE

SCI

INTERRUPT

CONTROL

TRANSMITTER

CLOCK

TRANSMITTER RATE

CONTROL

f

CPU

/PR

/16

SCIBRR

SCP1SCP0 SCT2

SCT1SCT0SCR2 SCR1SCR0

RECEIVER RATE

CONTROL

CONVENTIONAL BAUD RATE GENERATOR

105/294

1

ST7MC1/ST7MC2

LINSCI SERIAL COMMUNICATION INTERFACE (SCI Mode) (Cont’d)

9.5.5 SCI Mode - Functional Description

9.5.5.1 Serial Data Format

Conventional Baud Rate Generator Mode

Word length may be selected as being either 8 or 9

bits by programming the M bit in the SCICR1 reg-

ister (see Figure 61).

The block diagram of the Serial Control Interface

in conventional baud rate generator mode is

shown in Figure 60.

The TDO pin is in low state during the start bit.

The TDO pin is in high state during the stop bit.

It uses 4 registers:

– Two control registers (SCICR1 and SCICR2)

– A status register (SCISR)

An Idle character is interpreted as a continuous

logic high level for 10 (or 11) full bit times.

A Break character is a character with a sufficient

number of low level bits to break the normal data

format followed by an extra “1” bit to acknowledge

the start bit.

– A baud rate register (SCIBRR)

Extended Prescaler Mode

Two additional prescalers are available in extend-

ed prescaler mode. They are shown in Figure 62.

– An extended prescaler receiver register (SCIER-

PR)

– An extended prescaler transmitter register (SCI-

ETPR)

Figure 61. Word length programming

9-bit Word length (M bit is set)

Possible

Next Data Character

Parity

Data Character

Bit

Start

Bit

Stop

Bit

Bit2

Bit5

Bit6

Bit8

Bit0

Bit1

Bit3

Bit4

Bit7

Start

Bit

Idle Line

Start

Bit

Extra

’1’

Break Character

8-bit Word length (M bit is reset)

Possible

Parity

Next Data Character

Data Character

Bit

Start

Bit

Stop

Bit

Bit2

Bit5

Bit6

Bit0

Bit1

Bit3

Bit4

Bit7

Bit

Start

Bit

Idle Line

Start

Bit

Extra

’1’

Break Character

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ST7MC1/ST7MC2

LINSCI SERIAL COMMUNICATION INTERFACE (SCI Mode) (Cont’d)

9.5.5.2 Transmitter

When no transmission is taking place, a write in-

struction to the SCIDR register places the data di-

rectly in the shift register, the data transmission

starts, and the TDRE bit is immediately set.

The transmitter can send data words of either 8 or

9 bits depending on the M bit status. When the M

bit is set, word length is 9 bits and the 9th bit (the

MSB) has to be stored in the T8 bit in the SCICR1

register.

When a character transmission is complete (after

the stop bit or after the break character) the TC bit

is set and an interrupt is generated if the TCIE is

set and the I[1:0] bits are cleared in the CCR reg-

ister.

Character Transmission

During an SCI transmission, data shifts out least

significant bit first on the TDO pin. In this mode,

the SCIDR register consists of a buffer (TDR) be-

tween the internal bus and the transmit shift regis-

ter (see Figure 60).

Clearing the TC bit is performed by the following

software sequence:

1. An access to the SCISR register

2. A write to the SCIDR register

Procedure

Note: The TDRE and TC bits are cleared by the

same software sequence.

– Select the M bit to define the word length.

– Select the desired baud rate using the SCIBRR

and the SCIETPR registers.

Break Characters

Setting the SBK bit loads the shift register with a

break character. The break character length de-

pends on the M bit (see Figure 61)

– Set the TE bit to send a preamble of 10 (M=0) or

11 (M=1) consecutive ones (Idle Line) as first

transmission.

As long as the SBK bit is set, the SCI sends break

characters to the TDO pin. After clearing this bit by

software, the SCI inserts a logic 1 bit at the end of

the last break character to guarantee the recogni-

tion of the start bit of the next character.

– Access the SCISR register and write the data to

send in the SCIDR register (this sequence clears

the TDRE bit). Repeat this sequence for each

data to be transmitted.

Clearing the TDRE bit is always performed by the

following software sequence:

1. An access to the SCISR register

2. A write to the SCIDR register

Idle Line

Setting the TE bit drives the SCI to send a pream-

ble of 10 (M=0) or 11 (M=1) consecutive ‘1’s (idle

line) before the first character.

The TDRE bit is set by hardware and it indicates:

– The TDR register is empty.

In this case, clearing and then setting the TE bit

during a transmission sends a preamble (idle line)

after the current word. Note that the preamble du-

ration (10 or 11 consecutive ‘1’s depending on the

M bit) does not take into account the stop bit of the

previous character.

– The data transfer is beginning.

– The next data can be written in the SCIDR regis-

ter without overwriting the previous data.

This flag generates an interrupt if the TIE bit is set

and the I[|1:0] bits are cleared in the CCR register.

Note: Resetting and setting the TE bit causes the

data in the TDR register to be lost. Therefore the

best time to toggle the TE bit is when the TDRE bit

is set i.e. before writing the next byte in the SCIDR.

When a transmission is taking place, a write in-

struction to the SCIDR register stores the data in

the TDR register and which is copied in the shift

register at the end of the current transmission.

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ST7MC1/ST7MC2

LINSCI SERIAL COMMUNICATION INTERFACE (SCI Mode) (Cont’d)

9.5.5.3 Receiver

– The OR bit is set.

The SCI can receive data words of either 8 or 9

bits. When the M bit is set, word length is 9 bits

and the MSB is stored in the R8 bit in the SCICR1

register.

– The RDR content will not be lost.

– The shift register will be overwritten.

– An interrupt is generated if the RIE bit is set and

the I[|1:0] bits are cleared in the CCR register.

Character reception

The OR bit is reset by an access to the SCISR reg-

ister followed by a SCIDR register read operation.

During a SCI reception, data shifts in least signifi-

cant bit first through the RDI pin. In this mode, the

SCIDR register consists or a buffer (RDR) be-

tween the internal bus and the received shift regis-

ter (see Figure 60).

Noise Error

Oversampling techniques are used for data recov-

ery by discriminating between valid incoming data

and noise.

Procedure

When noise is detected in a character:

– Select the M bit to define the word length.

– The NF bit is set at the rising edge of the RDRF

bit.

– Select the desired baud rate using the SCIBRR

and the SCIERPR registers.

– Data is transferred from the Shift register to the

SCIDR register.

– Set the RE bit, this enables the receiver which

begins searching for a start bit.

– No interrupt is generated. However this bit rises

at the same time as the RDRF bit which itself

generates an interrupt.

When a character is received:

– The RDRF bit is set. It indicates that the content

of the shift register is transferred to the RDR.

The NF bit is reset by a SCISR register read oper-

ation followed by a SCIDR register read operation.

– An interrupt is generated if the RIE bit is set and

the I[1:0] bits are cleared in the CCR register.

Framing Error

– The error flags can be set if a frame error, noise

or an overrun error has been detected during re-

ception.

A framing error is detected when:

– The stop bit is not recognized on reception at the

expected time, following either a de-synchroni-

zation or excessive noise.

Clearing the RDRF bit is performed by the following

software sequence done by:

– A break is received.

1. An access to the SCISR register

2. A read to the SCIDR register.

When the framing error is detected:

– the FE bit is set by hardware

The RDRF bit must be cleared before the end of the

reception of the next character to avoid an overrun

error.

– Data is transferred from the Shift register to the

SCIDR register.

Idle Line

– No interrupt is generated. However this bit rises

at the same time as the RDRF bit which itself

generates an interrupt.

When an idle line is detected, there is the same

procedure as a data received character plus an in-

terrupt if the ILIE bit is set and the I[|1:0] bits are

cleared in the CCR register.

The FE bit is reset by a SCISR register read oper-

ation followed by a SCIDR register read operation.

Overrun Error

Break Character

An overrun error occurs when a character is re-

ceived when RDRF has not been reset. Data can

not be transferred from the shift register to the

TDR register as long as the RDRF bit is not

cleared.

– When a break character is received, the SCI

handles it as a framing error. To differentiate a

break character from a framing error, it is neces-

sary to read the SCIDR. If the received value is

00h, it is a break character. Otherwise it is a

framing error.

When an overrun error occurs:

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ST7MC1/ST7MC2

LINSCI SERIAL COMMUNICATION INTERFACE (SCI Mode) (Cont’d)

9.5.5.4 Conventional Baud Rate Generation

9.5.5.5 Extended Baud Rate Generation

The baud rate for the receiver and transmitter (Rx

and Tx) are set independently and calculated as

follows:

The extended prescaler option gives a very fine

tuning on the baud rate, using a 255 value prescal-

er, whereas the conventional Baud Rate Genera-

tor retains industry standard software compatibili-

ty.

f

CPU

Rx =

Tx =

The extended baud rate generator block diagram

is described in Figure 62.

(16 PR) RR

(16 PR) TR

*

with:

The output clock rate sent to the transmitter or to

the receiver will be the output from the 16 divider

divided by a factor ranging from 1 to 255 set in the

SCIERPR or the SCIETPR register.

PR = 1, 3, 4 or 13 (see SCP[1:0] bits)

TR = 1, 2, 4, 8, 16, 32, 64,128

(see SCT[2:0] bits)

Note: the extended prescaler is activated by set-

ting the SCIETPR or SCIERPR register to a value

other than zero. The baud rates are calculated as

follows:

RR = 1, 2, 4, 8, 16, 32, 64,128

(see SCR[2:0] bits)

All these bits are in the SCIBRR register.

Example: If f is 8 MHz (normal mode) and if

PR=13 and TR=RR=1, the transmit and receive

baud rates are 38400 baud.

CPU

f

CPU

Rx =

16 ERPR*(PR*TR)

Tx =

16 ETPR*(PR*TR)

*

Note: the baud rate registers MUST NOT be

changed while the transmitter or the receiver is en-

abled.

with:

ETPR = 1,..,255 (see SCIETPR register)

ERPR = 1,.. 255 (see SCIERPR register)

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ST7MC1/ST7MC2

LINSCI SERIAL COMMUNICATION INTERFACE (SCI Mode) (Cont’d)

Figure 62. SCI Baud Rate and Extended Prescaler Block Diagram

TRANSMITTER

CLOCK

EXTENDED PRESCALER TRANSMITTER RATE CONTROL

SCIETPR

EXTENDED TRANSMITTER PRESCALER REGISTER

SCIERPR

EXTENDED RECEIVER PRESCALER REGISTER

RECEIVER

CLOCK

EXTENDED PRESCALER RECEIVER RATE CONTROL

EXTENDED PRESCALER

f

CPU

TRANSMITTER RATE

CONTROL

/PR

/16

SCIBRR

SCP1

SCT2

SCT1SCT0 SCR2 SCR1SCR0

SCP0

RECEIVER RATE

CONTROL

CONVENTIONAL BAUD RATE GENERATOR

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1

ST7MC1/ST7MC2

LINSCI SERIAL COMMUNICATION INTERFACE (SCI Mode) (Cont’d)

9.5.5.6 Receiver Muting and Wake-up Feature

ceived an address character (most significant bit

=’1’), the receivers are waken up. The receivers

which are not addressed set RWU bit to enter in

mute mode. Consequently, they will not treat the

next characters constituting the next part of the

message.

In multiprocessor configurations it is often desira-

ble that only the intended message recipient

should actively receive the full message contents,

thus reducing redundant SCI service overhead for

all non-addressed receivers.

9.5.5.7 Parity Control

The non-addressed devices may be placed in

sleep mode by means of the muting function.

Hardware byte Parity control (generation of parity

bit in transmission and parity checking in recep-

tion) can be enabled by setting the PCE bit in the

SCICR1 register. Depending on the character for-

mat defined by the M bit, the possible SCI charac-

ter formats are as listed in Table 20.

Setting the RWU bit by software puts the SCI in

sleep mode:

All the reception status bits can not be set.

All the receive interrupts are inhibited.

Note: In case of wake up by an address mark, the

MSB bit of the data is taken into account and not

the parity bit

A muted receiver may be woken up in one of the

following ways:

– by Idle Line detection if the WAKE bit is reset,

– by Address Mark detection if the WAKE bit is set.

Idle Line Detection

Table 20. Character Formats

M bit PCE bit

Character format

| SB | 8 bit data | STB |

| SB | 7-bit data | PB | STB |

| SB | 9-bit data | STB |

| SB | 8-bit data | PB | STB |

Receiver wakes-up by Idle Line detection when

the Receive line has recognised an Idle Line. Then

the RWU bit is reset by hardware but the IDLE bit

is not set.

0

1

0

1

0

1

This feature is useful in a multiprocessor system

when the first characters of the message deter-

mine the address and when each message ends

by an idle line: As soon as the line becomes idle,

every receivers is waken up and analyse the first

characters of the message which indicates the ad-

dressed receiver. The receivers which are not ad-

dressed set RWU bit to enter in mute mode. Con-

sequently, they will not treat the next characters

constituting the next part of the message. At the

end of the message, an idle line is sent by the

transmitter: this wakes up every receivers which

are ready to analyse the addressing characters of

the new message.

Legend: SB = Start Bit, STB = Stop Bit,

PB = Parity Bit

Even parity: the parity bit is calculated to obtain

an even number of “1s” inside the character made

of the 7 or 8 LSB bits (depending on whether M is

equal to 0 or 1) and the parity bit.

Ex: data=00110101; 4 bits set => parity bit will be

0 if even parity is selected (PS bit = 0).

Odd parity: the parity bit is calculated to obtain an

odd number of “1s” inside the character made of

the 7 or 8 LSB bits (depending on whether M is

equal to 0 or 1) and the parity bit.

Ex: data=00110101; 4 bits set => parity bit will be

1 if odd parity is selected (PS bit = 1).

In such a system, the inter-characters space must

be smaller than the idle time.

Transmission mode: If the PCE bit is set then the

MSB bit of the data written in the data register is

not transmitted but is changed by the parity bit.

Address Mark Detection

Receiver wakes-up by Address Mark detection

when it received a “1” as the most significant bit of

a word, thus indicating that the message is an ad-

dress. The reception of this particular word wakes

up the receiver, resets the RWU bit and sets the

RDRF bit, which allows the receiver to receive this

word normally and to use it as an address word.

Reception mode: If the PCE bit is set then the in-

terface checks if the received data byte has an

even number of “1s” if even parity is selected

(PS=0) or an odd number of “1s” if odd parity is se-

lected (PS=1). If the parity check fails, the PE flag

is set in the SCISR register and an interrupt is gen-

erated if PCIE is set in the SCICR1 register.

This feature is useful in a multiprocessor system

when the most significant bit of each character

(except for the break character) is reserved for Ad-

dress Detection. As soon as the receivers re-

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1

ST7MC1/ST7MC2

LINSCI SERIAL COMMUNICATION INTERFACE (SCI Mode) (Cont’d)

9.5.6 Low Power Modes

9.5.7 Interrupts

Enable Exit

Control from from

Exit

Mode

Description

Event

Flag

Interrupt Event

No effect on SCI.

Bit

Wait

Halt

WAIT

SCI interrupts cause the device to exit

from Wait mode.

Transmit Data Register

Empty

TDRE

TC

TIE

Yes

No

SCI registers are frozen.

Transmission Com-

plete

TCIE

RIE

Yes

No

In Halt mode, the SCI stops transmit-

ting/receiving until Halt mode is exit-

ed.

HALT

Received Data Ready

to be Read

RDRF

Overrun Error or LIN

Synch Error Detected

OR/

LHE

Idle Line Detected

Parity Error

IDLE

PE

ILIE

PIE

Yes

No

LIN Header Detection

LHDF LHIE

The SCI interrupt events are connected to the

same interrupt vector (see Interrupts chapter).

These events generate an interrupt if the corre-

sponding Enable Control Bit is set and the inter-

rupt mask in the CC register is reset (RIM instruc-

tion).

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1

ST7MC1/ST7MC2

LINSCI SERIAL COMMUNICATION INTERFACE (SCI Mode) (Cont’d)

9.5.8 SCI Mode Register Description

Bit 3 = OR Overrun error

STATUS REGISTER (SCISR)

Read Only

Reset Value: 1100 0000 (C0h)

The OR bit is set by hardware when the word cur-

rently being received in the shift register is ready to

be transferred into the RDR register whereas

RDRF is still set. An interrupt is generated if RIE=1

in the SCICR2 register. It is cleared by a software

sequence (an access to the SCISR register fol-

lowed by a read to the SCIDR register).

0: No Overrun error

7

0

1)

TDRE

TC

RDRF IDLE

OR

NF

FE

PE

1: Overrun error detected

Bit 7 = TDRE Transmit data register empty.

Note: When this bit is set, RDR register contents

will not be lost but the shift register will be overwrit-

ten.

This bit is set by hardware when the content of the

TDR register has been transferred into the shift

register. An interrupt is generated if the TIE =1 in

the SCICR2 register. It is cleared by a software se-

quence (an access to the SCISR register followed

by a write to the SCIDR register).

Bit 2 = NF Character Noise flag

0: Data is not transferred to the shift register

1: Data is transferred to the shift register

This bit is set by hardware when noise is detected

on a received character. It is cleared by a software

sequence (an access to the SCISR register fol-

lowed by a read to the SCIDR register).

0: No noise

Bit 6 = TC Transmission complete.

This bit is set by hardware when transmission of a

character containing Data is complete. An inter-

rupt is generated if TCIE=1 in the SCICR2 regis-

ter. It is cleared by a software sequence (an ac-

cess to the SCISR register followed by a write to

the SCIDR register).

1: Noise is detected

Note: This bit does not generate interrupt as it ap-

pears at the same time as the RDRF bit which it-

self generates an interrupt.

0: Transmission is not complete

1: Transmission is complete

Bit 1 = FE Framing error.

This bit is set by hardware when a de-synchroniza-

tion, excessive noise or a break character is de-

tected. It is cleared by a software sequence (an

access to the SCISR register followed by a read to

the SCIDR register).

0: No Framing error

1: Framing error or break character detected

Note: TC is not set after the transmission of a Pre-

amble or a Break.

Bit 5 = RDRF Received data ready flag.

This bit is set by hardware when the content of the

RDR register has been transferred to the SCIDR

register. An interrupt is generated if RIE=1 in the

SCICR2 register. It is cleared by a software se-

quence (an access to the SCISR register followed

by a read to the SCIDR register).

Notes:

– This bit does not generate an interrupt as it ap-

pears at the same time as the RDRF bit which it-

self generates an interrupt. If the word currently

being transferred causes both a frame error and

an overrun error, it will be transferred and only

the OR bit will be set.

0: Data is not received

1: Received data is ready to be read

Bit 4 = IDLE Idle line detected.

Bit 0 = PE Parity error.

This bit is set by hardware when an Idle Line is de-

tected. An interrupt is generated if the ILIE=1 in

the SCICR2 register. It is cleared by a software se-

quence (an access to the SCISR register followed

by a read to the SCIDR register).

0: No Idle Line is detected

1: Idle Line is detected

This bit is set by hardware when a byte parity error

occurs (if the PCE bit is set) in receiver mode. It is

cleared by a software sequence (a read to the sta-

tus register followed by an access to the SCIDR

data register). An interrupt is generated if PIE=1 in

the SCICR1 register.

0: No parity error

1: Parity error detected

Note: The IDLE bit will not be set again until the

RDRF bit has been set itself (i.e. a new idle line oc-

curs).

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1

ST7MC1/ST7MC2

LINSCI SERIAL COMMUNICATION INTERFACE (SCI Mode) (Cont’d)

CONTROL REGISTER 1 (SCICR1)

Read/Write

Reset Value: x000 0000 (x0h)

Bit 3 = WAKE Wake-Up method.

This bit determines the SCI Wake-Up method, it is

set or cleared by software.

0: Idle Line

7

0

1: Address Mark

1)

R8

T8

SCID

M

WAKE

PS

PIE

PCE

Note: If the LINE bit is set, the WAKE bit is de-ac-

tivated and replaced by the LHDM bit

1)

This bit has a different function in LIN mode, please

refer to the LIN mode register description.

Bit 2 = PCE Parity control enable.

Bit 7 = R8 Receive data bit 8.

This bit is used to store the 9th bit of the received

word when M=1.

This bit is set and cleared by software. It selects

the hardware parity control (generation and detec-

tion for byte parity, detection only for LIN parity).

0: Parity control disabled

1: Parity control enabled

Bit 6 = T8 Transmit data bit 8.

This bit is used to store the 9th bit of the transmit-

ted word when M=1.

Bit 1 = PS Parity selection.

This bit selects the odd or even parity when the

parity generation/detection is enabled (PCE bit

set). It is set and cleared by software. The parity

will be selected after the current byte.

0: Even parity

Bit 5 = SCID Disabled for low power consumption

When this bit is set the SCI prescalers and outputs

are stopped and the end of the current byte trans-

fer in order to reduce power consumption.This bit

is set and cleared by software.

1: Odd parity

0: SCI enabled

1: SCI prescaler and outputs disabled

Bit 0 = PIE Parity interrupt enable.

This bit enables the interrupt capability of the hard-

ware parity control when a parity error is detected

(PE bit set). The parity error involved can be a byte

parity error (if bit PCE is set and bit LPE is reset) or

a LIN parity error (if bit PCE is set and bit LPE is

set).

Bit 4 = M Word length.

This bit determines the word length. It is set or

cleared by software.

0: 1 Start bit, 8 Data bits, 1 Stop bit

1: 1 Start bit, 9 Data bits, 1 Stop bit

0: Parity error interrupt disabled

1: Parity error interrupt enabled

Note: The M bit must not be modified during a data

transfer (both transmission and reception).

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1

ST7MC1/ST7MC2

LINSCI SERIAL COMMUNICATION INTERFACE (SCI Mode) (Cont’d)

CONTROL REGISTER 2 (SCICR2)

Read/Write

1: Receiver is enabled and begins searching for a

start bit

Reset Value: 0000 0000 (00h)

Bit 1 = RWU Receiver wake-up.

7

0

This bit determines if the SCI is in mute mode or

not. It is set and cleared by software and can be

cleared by hardware when a wake-up sequence is

recognized.

1)

RWU

TIE

TCIE

RIE

ILIE

TE

RE

SBK

1)

0: Receiver in active mode

This bit has a different function in LIN mode, please

1: Receiver in mute mode

refer to the LIN mode register description.

Notes:

Bit 7 = TIE Transmitter interrupt enable.

This bit is set and cleared by software.

0: Interrupt is inhibited

1: In SCI interrupt is generated whenever TDRE=1

in the SCISR register

– Before selecting Mute mode (by setting the RWU

bit) the SCI must first receive a data byte, other-

wise it cannot function in Mute mode with wake-

up by Idle line detection.

– In Address Mark Detection Wake-Up configura-

tion (WAKE bit=1) the RWU bit cannot be modi-

fied by software while the RDRF bit is set.

Bit 6 = TCIE Transmission complete interrupt ena-

ble

This bit is set and cleared by software.

0: Interrupt is inhibited

1: An SCI interrupt is generated whenever TC=1 in

the SCISR register

Bit 0 = SBK Send break.

This bit set is used to send break characters. It is

set and cleared by software.

0: No break character is transmitted

1: Break characters are transmitted

Bit 5 = RIE Receiver interrupt enable.

This bit is set and cleared by software.

0: Interrupt is inhibited

1: An SCI interrupt is generated whenever OR=1

or RDRF=1 in the SCISR register

Note: If the SBK bit is set to “1” and then to “0”, the

transmitter will send a BREAK word at the end of

the current word.

Bit 4 = ILIE Idle line interrupt enable.

This bit is set and cleared by software.

0: Interrupt is inhibited

DATA REGISTER (SCIDR)

Read/Write

Reset Value: Undefined

1: An SCI interrupt is generated whenever IDLE=1

in the SCISR register.

Contains the Received or Transmitted data char-

acter, depending on whether it is read from or writ-

ten to.

Bit 3 = TE Transmitter enable.

This bit enables the transmitter. It is set and

cleared by software.

7

0

DR7

DR6

DR5

DR4

DR3

DR2

DR1

DR0

0: Transmitter is disabled

1: Transmitter is enabled

Notes:

The Data register performs a double function (read

and write) since it is composed of two registers,

one for transmission (TDR) and one for reception

(RDR).

The TDR register provides the parallel interface

between the internal bus and the output shift reg-

ister (see Figure 60).

– During transmission, a “0” pulse on the TE bit

(“0” followed by “1”) sends a preamble (idle line)

after the current word.

– When TE is set there is a 1 bit-time delay before

the transmission starts.

The RDR register provides the parallel interface

between the input shift register and the internal

bus (see Figure 60).

Bit 2 = RE Receiver enable.

This bit enables the receiver. It is set and cleared

by software.

0: Receiver is disabled in the SCISR register

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ST7MC1/ST7MC2

LINSCI SERIAL COMMUNICATION INTERFACE (SCI Mode) (Cont’d)

BAUD RATE REGISTER (SCIBRR)

Read/Write

Reset Value: 0000 0000 (00h)

TR dividing factor

SCT2

SCT1

SCT0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

7

0

4

8

SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0

16

32

64

128

Note: When LIN slave mode is disabled, the SCI-

BRR register controls the conventional baud rate

generator.

Bit 7:6= SCP[1:0] First SCI Prescaler

These 2 prescaling bits allow several standard

clock division ranges:

Bit 2:0 = SCR[2:0] SCI Receiver rate divider.

These 3 bits, in conjunction with the SCP[1:0] bits

define the total division applied to the bus clock to

yield the receive rate clock in conventional Baud

Rate Generator mode.

PR Prescaling factor

SCP1

SCP0

1

3

0

1

0

1

0

1

RR dividing factor

SCR2

SCR1

SCR0

4

1

2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

13

4

Bit 5:3 = SCT[2:0] SCI Transmitter rate divisor

These 3 bits, in conjunction with the SCP1 & SCP0

bits define the total division applied to the bus

clock to yield the transmit rate clock in convention-

al Baud Rate Generator mode.

8

16

32

64

128

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1

ST7MC1/ST7MC2

LINSCI SERIAL COMMUNICATION INTERFACE (SCI Mode) (Cont’d)

EXTENDED RECEIVE PRESCALER DIVISION

REGISTER (SCIERPR)

EXTENDED TRANSMIT PRESCALER DIVISION

REGISTER (SCIETPR)

Read/Write

Reset Value: 0000 0000 (00h)

Reset Value:0000 0000 (00h)

7

0

7

0

ERPR ERPR ERPR ERPR ERPR ERPR ERPR ERPR

ETPR ETPR ETPR ETPR ETPR ETPR ETPR ETPR

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

Bit 7:0 = ERPR[7:0] 8-bit Extended Receive Pres-

caler Register.

Bit 7:0 = ETPR[7:0] 8-bit Extended Transmit Pres-

caler Register.

The extended Baud Rate Generator is activated

when a value other than 00h is stored in this regis-

ter. The clock frequency from the 16 divider (see

Figure 62) is divided by the binary factor set in the

SCIERPR register (in the range 1 to 255).

The extended Baud Rate Generator is activated

when a value other than 00h is stored in this regis-

ter. The clock frequency from the 16 divider (see

Figure 62) is divided by the binary factor set in the

SCIETPR register (in the range 1 to 255).

The extended baud rate generator is not active af-

ter a reset.

The extended baud rate generator is not active af-

ter a reset.

Note: In LIN slave mode, the Conventional and

Extended Baud Rate Generators are disabled.

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1

ST7MC1/ST7MC2

LINSCI SERIAL COMMUNICATION INTERFACE (LIN Mode)

9.5.9 LIN Mode - Functional Description.

Slave

The block diagram of the Serial Control Interface,

in LIN slave mode is shown in Figure 64.

Set the LSLV bit in the SCICR3 register to enter

LIN slave mode. In this case, setting the SBK bit

will have no effect.

It uses 6 registers:

In LIN Slave mode the LIN baud rate generator is

selected instead of the Conventional or Extended

Prescaler. The LIN baud rate generator is com-

mon to the transmitter and the receiver.

– Three control registers: SCICR1, SCICR2 and

SCICR3

– Two status registers: the SCISR register and the

LHLR register mapped at the SCIERPR address

Then the baud rate can be programmed using

LPR and LPRF registers.

– A baud rate register: LPR mapped at the SCI-

BRR address and an associated fraction register

LPFR mapped at the SCIETPR address

Note: It is mandatory to set the LIN configuration

first before programming LPR and LPRF, because

the LIN configuration uses a different baud rate

generator from the standard one.

The bits dedicated to LIN are located in the

SCICR3. Refer to the register descriptions in Sec-

tion 9.5.10for the definitions of each bit.

9.5.9.1 Entering LIN Mode

9.5.9.2 LIN Transmission

To use the LINSCI in LIN mode the following con-

figuration must be set in SCICR3 register:

In LIN mode the same procedure as in SCI mode

has to be applied for a LIN transmission.

– Clear the M bit to configure 8-bit word length.

To transmit the LIN Header the proceed as fol-

lows:

– Set the LINE bit.

Master

– First set the SBK bit in the SCICR2 register to

start transmitting a 13-bit LIN Synch Break

To enter master mode the LSLV bit must be reset

In this case, setting the SBK bit will send 13 low

bits.

– reset the SBK bit

– Load the LIN Synch Field (0x55) in the SCIDR

register to request Synch Field transmission

Then the baud rate can programmed using the

SCIBRR, SCIERPR and SCIETPR registers.

– Wait until the SCIDR is empty (TDRE bit set in

the SCISR register)

In LIN master mode, the Conventional and / or Ex-

tended Prescaler define the baud rate (as in stand-

ard SCI mode)

– Load the LIN message Identifier in the SCIDR

register to request Identifier transmission.

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1

ST7MC1/ST7MC2

Figure 63. LIN characters

8-bit Word length (M bit is reset)

Next Data Character

Data Character

Bit2

Bit

Start

Bit

Stop

Bit

Bit5 Bit6

Bit7

Bit0 Bit1

Bit3 Bit4

Start

Bit

Idle Line

LIN Synch Field

Start

’1’

LIN Synch Break = 13 low bits

Extra

Bit

LIN Synch Field

Bit2 Bit6

Bit5

Bit4

Bit

Start

Bit

Stop

Bit

Bit1

Bit3

Bit0

Bit7

Measurement for baud rate autosynchronization

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1

ST7MC1/ST7MC2

LINSCI SERIAL COMMUNICATION INTERFACE (LIN Mode) (Cont’d)

Figure 64. SCI Block Diagram in LIN Slave Mode

Write

Read

(DATA REGISTER) SCIDR

Received Data Register (RDR)

Receive Shift Register

Transmit Data Register (TDR)

TDO

RDI

Transmit Shift Register

SCICR1

PCE

R8 T8 SCID

M

WAKE

PS PIE

WAKE

UP

UNIT

TRANSMIT

CONTROL

RECEIVER

CONTROL

RECEIVER

CLOCK

SCISR

SCICR2

OR/

LHE

TIE TCIE RIE ILIE TE RE RWU SBK

TDRE

RDRF

IDLE

TC

FE

PE

NF

SCI

INTERRUPT

CONTROL

TRANSMITTER

CLOCK

f_CPU

SCICR3

LDUM LINE LSLV LASE LHDM LHIE LHDF LSF

LIN SLAVE BAUD RATE

AUTO SYNCHRONIZATION

UNIT

SCIBRR

CONVENTIONAL BAUD RATE

LPR7

LPR0

GENERATOR

+

EXTENDED PRESCALER

0

f_CPU

1

/ LDIV

/16

LIN SLAVE BAUD RATE GENERATOR

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1

ST7MC1/ST7MC2

LINSCI SERIAL COMMUNICATION INTERFACE (LIN Mode) (Cont’d)

9.5.9.3 LIN Reception

Note:

In LIN mode the reception of a byte is the same as

in SCI mode but the LINSCI has features for han-

dling the LIN Header automatically (identifier de-

tection) or semiautomatically (Synch Break detec-

tion) depending on the LIN Header detection

mode. The detection mode is selected by the

LHDM bit in the SCICR3.

In LIN slave mode, the FE bit detects all frame er-

ror which does not correspond to a break.

Identifier Detection (LHDM = 1):

This case is the same as the previous one except

that the LHDF and the RDRF flags are set only af-

ter the entire header has been received (this is

true whether automatic resynchronization is ena-

bled or not). This indicates that the LIN Identifier is

available in the SCIDR register.

Additionally, an automatic resynchronization fea-

ture can be activated to compensate for any clock

deviation, for more details please refer to Section

9.5.9.5 LIN Baudrate.

Notes:

During LIN Synch Field measurement, the SCI

state machine is switched off: no characters are

transferred to the data register.

LIN Header Handling by a Slave

Depending on the LIN Header detection method

the LINSCI will signal the detection of a LIN Head-

er after the LIN Synch Break or after the Identifier

has been successfully received.

LIN Slave parity

In LIN Slave mode (LINE and LSLV bits are set)

LIN parity checking can be enabled by setting the

PCE bit.

Note:

It is recommended to combine the Header detec-

tion function with Mute mode. Putting the LINSCI

in Mute mode allows the detection of Headers only

and prevents the reception of any other charac-

ters.

In this case, the parity bits of the LIN Identifier

Field are checked. The identifier character is rec-

rd

ognised as the 3 received character after a break

character (included):

parity bits

This mode can be used to wait for the next Header

without being interrupted by the data bytes of the

current message in case this message is not rele-

vant for the application.

Synch Break Detection (LHDM = 0):

When a LIN Synch Break is received:

LIN Synch

Break

LIN Synch

Field

Identifier

Field

– The RDRF bit in the SCISR register is set. It in-

dicates that the content of the shift register is

transferred to the SCIDR register, a value of

0x00 is expected for a Break.

th

The bits involved are the two MSB positions (7

th

and 8 bits if M=0; 8 and 9 bits if M=0) of the

identifier character. The check is performed as

specified by the LIN specification:

– The LHDF flag in the SCICR3 register indicates

that a LIN Synch Break Field has been detected.

– An interrupt is generated if the LHIE bit in the

SCICR3 register is set and the I[1:0] bits are

cleared in the CCR register.

stop bit

parity bits

start bit

– Then the LIN Synch Field is received and meas-

identifier bits

ured.

ID0 ID1 ID2 ID3 ID4 ID5 P0 P1

– If automatic resynchronization is enabled (LA-

SE bit = 1), the LIN Synch Field is not trans-

ferred to the shift register: there is no need to

clear the RDRF bit.

Identifier Field

P0= ID0 ID1 ID2 ID4

P1= ID1 ID3 ID4 ID5

M=0

– If automatic resynchronization is disabled (LA-

SE bit =0), the LIN Synch Field is received as

a normal character and transferred to the

SCIDR register and RDRF is set.

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1

ST7MC1/ST7MC2

LINSCI SERIAL COMMUNICATION INTERFACE (LIN Mode) (Cont’d)

9.5.9.4 LIN Error Detection

edge of the Synch Field. Let’s refer to this period

deviation as D:

LIN Header Error Flag

If the LHE flag is set, it means that:

D > 15.625%

The LIN Header Error Flag indicates that an invalid

LIN Header has been detected.

When a LIN Header Error occurs:

If LHE flag is not set, it means that:

D < 16.40625%

– The LHE flag is set

– An interrupt is generated if the RIE bit is set and

the I[1:0] bits are cleared in the CCR register.

If 15.625% ≤ D < 16.40625%, then the flag can

be either set or reset depending on the dephas-

ing between the signal on the RDI line and the

CPU clock.

If autosynchronization is enabled (LASE bit =1),

this can mean that the LIN Synch Field is corrupt-

ed, and that the SCI is in a blocked state (LSF bit is

set). The only way to recover is to reset the LSF bit

and then to clear the LHE bit.

– The second check is based on the measurement

of each bit time between both edges of the Synch

Field: this checks that each of these bit times is

large enough compared to the bit time of the cur-

rent baud rate.

– The LHE bit is reset by an access to the SCISR

register followed by a read of the SCIDR register.

When LHE is set due to this error then the SCI

goes into a blocked state (LSF bit is set).

LHE/OVR Error Conditions

When Auto Resynchronization is disabled (LASE

bit =0), the LHE flag detects:

LIN Header Time-out Error

When the LIN Identifier Field Detection Method is

used (by configuring LHDM to 1) or when LIN

auto-resynchronization is enabled (LASE bit=1),

– That the received LIN Synch Field is not equal to

55h.

– That an overrun occurred (as in standard SCI

mode)

the

LINSCI

automatically

condition given by the LIN protocol.

monitors

the

T

HEADER_MAX

– Furthermore, if LHDM is set it also detects that a

LIN Header Reception Timeout occurred (only if

LHDM is set).

If the entire Header (up to and including the STOP

bit of the LIN Identifier Field) is not received within

the maximum time limit of 57 bit times then a LIN

Header Error is signalled and the LHE bit is set in

the SCISR register.

When the LIN auto-resynchronization is enabled

(LASE bit=1), the LHE flag detects:

– That the deviation error on the Synch Field is

outside the LIN specification which allows up to

+/-15.5% of period deviation between the slave

and master oscillators.

Figure 65. LIN Header Reception Timeout

LIN Synch

Break

LIN Synch

Field

Identifier

Field

– A LIN Header Reception Timeout occurred.

If T

> T

then the LHE flag is

HEADER

HEADER_MAX

set. Refer to Figure 65. (only if LHDM is set to 1)

T

HEADER

– An overflow during the Synch Field Measure-

ment, which leads to an overflow of the divider

registers. If LHE is set due to this error then the

SCI goes into a blocked state (LSF bit is set).

The time-out counter is enabled at each break de-

tection. It is stopped in the following conditions:

- A LIN Identifier Field has been received

- An LHE error occurred (other than a timeout er-

ror).

– That an overrun occurred on Fields other than

the Synch Field (as in standard SCI mode)

Deviation Error on the Synch Field

- A software reset of LSF bit (transition from high to

low) occurred during the analysis of the LIN Synch

Field or

The deviation error is checking by comparing the

current baud rate (relative to the slave oscillator)

with the received LIN Synch Field (relative to the

master oscillator). Two checks are performed in

parallel:

If LHE bit is set due to this error during the LIN

Synchr Field (if LASE bit = 1) then the SCI goes

into a blocked state (LSF bit is set).

– The first check is based on a measurement be-

tween the first falling edge and the last falling

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1

ST7MC1/ST7MC2

LINSCI SERIAL COMMUNICATION INTERFACE (LIN Mode) (Cont’d)

If LHE bit is set due to this error during Fields other

than LIN Synch Field or if LASE bit is reset then

the current received Header is discarded and the

SCI searches for a new Break Field.

Even if no timeout occurs on the LIN Header, it is

possible to have access to the effective LIN head-

er Length (T

) through the LHL register.

HEADER

This allows monitoring at software level the

condition given by the LIN protocol.

T

FRAME_MAX

Note on LIN Header Time-out Limit

This feature is only available when LHDM bit =1 or

when LASE bit =1.

According to the LIN specification, the maximum

length of a LIN Header which does not cause a

timeout is equal to 1.4*(34 + 1) = 49 T

.

Mute Mode and Errors

BIT_MASTER

T

refers to the master baud rate.

In mute mode when LHDM bit =1, if an LHE error

occurs during the analysis of the LIN Synch Field

or if a LIN Header Time-out occurs then the LHE

bit is set but it doesn’t wake up from mute mode. In

this case, the current header analysis is discarded.

If needed, the software has to reset LSF bit. Then

the SCI searches for a new LIN header.

BIT_MASTER

When checking this timeout, the slave node is de-

synchronized for the reception of the LIN Break

and Synch fields. Consequently, a margin must be

allowed, taking into account the worst case: this

occurs when the LIN identifier lasts exactly 10

T

periods. In this case, the LIN Break

BIT_MASTER

and Synch fields last 49-10 = 39T

ods.

peri-

In mute mode, if a framing error occurs on a data

(which is not a break), it is discarded and the FE bit

is not set.

BIT_MASTER

Assuming the slave measures these first 39 bits

with a desynchronized clock of 15.5%. This leads

to a maximum allowed Header Length of:

When LHDM bit =1, any LIN header which re-

spects the following conditions causes a wake up

from mute mode:

39 x (1/0.845) T

+ 10T

BIT_MASTER

BIT_SLAVE

- A valid LIN Break Field (at least 11 dominant bits

followed by a recessive bit)

= 56.15 T

A margin is provided so that the time-out occurs

when the header length is greater than 57

- A valid LIN Synch Field (without deviation error)

T

periods. If it is less than or equal to 57

periods, then no timeout occurs.

- A LIN Identifier Field without framing error. Note

that a LIN parity error on the LIN Identifier Field

does not prevent wake up from mute mode.

BIT_SLAVE

LIN Header Length

- No LIN Header Time-out should occur during

Header reception.

Figure 66. LIN Synch Field Measurement

t

= CPU period

= Baud Rate period

CPU

t

= 16.LP.t

CPU

t

BR

SM=Synch Measurement Register (15 bits)

t

BR

LIN Synch Field

Bit2

Bit

LIN Synch Break

Extra

’1’

Start

Bit

Stop

Bit

Bit5 Bit6

Bit7

Bit0 Bit1

Bit3 Bit4

Measurement = 8.T = SM.t

BR

CPU

LPR(n+1)

LPR(n)

LPR = t / (16.t

) = Rounding (SM / 128)

CPU

BR

123/294

1

ST7MC1/ST7MC2

LINSCI SERIAL COMMUNICATION INTERFACE (LIN Mode) (Cont’d)

9.5.9.5 LIN Baudrate

mitter are both set to the same value, depending

on the LIN Slave baud rate generator:

Baud rate programming is done by writing a value

in the LPR prescaler or performing an automatic

resynchronization as described below.

f

CPU

Automatic Resynchronization

Tx = Rx =

(16 LDIV)

*

To automatically adjust the baud rate based on

measurement of the LIN Synch Field:

with:

– Write the nominal LIN Prescaler value (usually

depending on the nominal baud rate) in the

LPFR / LPR registers.

LDIV is an unsigned fixed point number. The man-

tissa is coded on 8 bits in the LPR register and the

fraction is coded on 4 bits in the LPFR register.

– Set the LASE bit to enable the Auto Synchroni-

zation Unit.

If LASE bit = 1 then LDIV is automatically updated

at the end of each LIN Synch Field.

When Auto Synchronization is enabled, after each

LIN Synch Break, the time duration between 5 fall-

Three registers are used internally to manage the

auto-update of the LIN divider (LDIV):

ing edges on RDI is sampled on f

and the re-

CPU

- LDIV_NOM (nominal value written by software at

LPR/LPFR addresses)

sult of this measurement is stored in an internal

15-bit register called SM (not user accessible)

(See Figure 66). Then the LDIV value (and its as-

sociated LPFR and LPR registers) are automati-

cally updated at the end of the fifth falling edge.

During LIN Synch field measurement, the SCI

state machine is stopped and no data is trans-

ferred to the data register.

- LDIV_MEAS (results of the Field Synch meas-

urement)

- LDIV (used to generate the local baud rate)

The control and interactions of these registers is

explained in Figure 67 and Figure 68. It depends

on the LDUM bit setting (LIN Divider Update Meth-

od)

9.5.9.6 LIN Slave Baud Rate Generation

In LIN mode, transmission and reception are driv-

en by the LIN baud rate generator

Note:

As explained in Figure 67 and Figure 68, LDIV

can be updated by two concurrent actions: a

transfer from LDIV_MEAS at the end of the LIN

Sync Field and a transfer from LDIV_NOM due

to a software write of LPR. If both operations

occur at the same time, the transfer from

LDIV_NOM has priority.

Note: LIN Master mode uses the Extended or

Conventional prescaler register to generate the

baud rate.

If LINE bit = 1 and LSLV bit = 1 then the Conven-

tional and Extended Baud Rate Generators are

disabled: the baud rate for the receiver and trans-

124/294

1

ST7MC1/ST7MC2

LINSCI SERIAL COMMUNICATION INTERFACE (LIN Mode) (Cont’d)

Figure 67. LDIV Read / Write operations when LDUM=0

Write LPFR

Write LPR

LIN Sync Field

Measurement

MANT(7:0) FRAC(3:0)

Write LPR

LDIV_NOM

LDIV_MEAS

MANT(7:0) FRAC(3:0)

Update

at end of

Synch Field

Baud Rate

Generarion

MANT(7:0) FRAC(3:0)

LDIV

Read LPR

Read LPFR

Figure 68. LDIV Read / Write operations when LDUM=1

Write LPFR

Write LPR

LIN Sync Field

Measurement

MANT(7:0) FRAC(3:0)

RDRF=1

LDIV_NOM

LDIV_MEAS

MANT(7:0) FRAC(3:0)

Update

at end of

Synch Field

Baud Rate

Generarion

MANT(7:0) FRAC(3:0)

LDIV

Read LPR

Read LPFR

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1

ST7MC1/ST7MC2

LINSCI SERIAL COMMUNICATION INTERFACE (LIN Mode) (Cont’d)

9.5.9.7 LINSCI Clock Tolerance

Consequently, the clock frequency should not vary

more than 6/16 (37.5%) within one bit.

LINSCI Clock Tolerance when unsynchronized

The sampling clock is resynchronized at each start

bit, so that when receiving 10 bits (one start bit, 1

data byte, 1 stop bit), the clock deviation should

not exceed 3.75%.

When LIN slaves are unsynchronized (meaning no

characters have been transmitted for a relatively

long time), the maximum tolerated deviation of the

LINSCI clock is +/-15%.

9.5.9.8 Clock Deviation Causes

If the deviation is within this range then the LIN

Synch Break is detected properly when a new re-

ception occurs.

The causes which contribute to the total deviation

are:

This is made possible by the fact that masters

send 13 low bits for the LIN Synch Break, which

can be interpreted as 11 low bits (13 bits -15% =

11.05) by a “fast” slave and then considered as a

LIN Synch Break. According to the LIN specifica-

tion, a LIN Synch Break is valid when its duration

– D

: Deviation due to transmitter error.

TRA

Note: the transmitter can be either a master or

a slave (in case of a slave listening to the re-

sponse of another slave).

– D

: Error due to the LIN Synch measure-

MEAS

ment performed by the receiver.

is greater than t

LIN Synch Break must last at least 11 low bits.

= 10. This means that the

SBRKTS

– D : Error due to the baud rate quantisa-

tion of the receiver.

QUANT

Note: If the period desynchronization of the slave

is +15% (slave too slow), the character “00h”

which represents a sequence of 9 low bits must

not be interpreted as a break character (9 bits +

15% = 10.35). Consequently, a valid LIN Synch

break must last at least 11 low bits.

– D

: Deviation of the local oscillator of the

REC

receiver: This deviation can occur during the

reception of one complete LIN message as-

suming that the deviation has been compen-

sated at the beginning of the message.

– D

: Deviation due to the transmission line

TCL

LINSCI Clock Tolerance when Synchronized

(generally due to the transceivers)

When synchronization has been performed, fol-

lowing reception of a LIN Synch Break, the LINSCI,

in LIN mode, has the same clock deviation toler-

ance as in SCI mode, which is explained below:

All the deviations of the system should be added

and compared to the LINSCI clock tolerance:

D

+ D

+D

+ D

< 3.75%

TCL

TRA

MEAS

QUANT

REC

During reception, each bit is oversampled 16

th th

th

times. The mean of the 8 , 9 and 10 samples is

considered as the bit value.

Figure 69. Bit Sampling in Reception Mode

RDI LINE

sampled values

Sample

clock

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16

6/16

7/16

One bit time

126/294

1

ST7MC1/ST7MC2

LINSCI SERIAL COMMUNICATION INTERFACE (LIN Mode) (Cont’d)

9.5.9.9 Error due to LIN Synch measurement

Consequently, at a given CPU frequency, the

maximum possible nominal baud rate (LPR

should be chosen with respect to the maximum tol-

erated deviation given by the equation:

)

MIN

The LIN Synch Field is measured over eight bit

times.

This measurement is performed using a counter

clocked by the CPU clock. The edge detections

are performed using the CPU clock cycle.

D

+ 2 / (128*LDIV

) + 1 / (2*16*LDIV

)

MIN

TRA

MIN

+ D

< 3.75%

TCL

REC

This leads to a precision of 2 CPU clock cycles for

the measurement which lasts 16*8*LDIV clock cy-

cles.

Example:

A nominal baud rate of 20Kbits/s at T

= 125ns

CPU

Consequently, this error (D

) is equal to:

MEAS

(8MHz) leads to LDIV

= 25d.

NOM

2 / (128*LDIV

).

MIN

LDIV

= 25 - 0.15*25 = 21.25

MIN

LDIV

corresponds to the minimum LIN prescal-

MIN

D

= 2 / (128*LDIV ) * 100 = 0.00073%

MIN

MEAS

er content, leading to the maximum baud rate, tak-

ing into account the maximum deviation of +/-15%.

= 1 / (2*16*LDIV ) * 100 = 0.0015%

QUANT

MIN

9.5.9.10 Error due to Baud Rate Quantisation

LIN Slave systems

The baud rate can be adjusted in steps of 1 / (16 *

LDIV). The worst case occurs when the “real”

baud rate is in the middle of the step.

For LIN Slave systems (the LINE and LSLV bits

are set), receivers wake up by LIN Synch Break or

LIN Identifier detection (depending on the LHDM

bit).

This leads to a quantization error (D

) equal

QUANT

to 1 / (2*16*LDIV

).

MIN

Hot Plugging Feature for LIN Slave Nodes

9.5.9.11 Impact of Clock Deviation on

Maximum Baud Rate

In LIN Slave Mute Mode (the LINE, LSLV and

RWU bits are set) it is possible to hot plug to a net-

work during an ongoing communication flow. In

this case the SCI monitors the bus on the RDI line

until 11 consecutive dominant bits have been de-

tected and discards all the other bits received.

The choice of the nominal baud rate (LDIV

)

NOM

will influence both the quantisation error (D

QUANT

and the measurement error (D

). The worst

MEAS

case occurs for LDIV

.

MIN

127/294

1

ST7MC1/ST7MC2

LINSCI SERIAL COMMUNICATION INTERFACE (LIN Mode) (Cont’d)

9.5.10 LIN Mode Register Description

framing error is detected (if the stop bit is dominant

(0) and at least one of the other bits is recessive

(1). It is not set when a break occurs, the LHDF bit

is used instead as a break flag (if the LHDM bit=0).

It is cleared by a software sequence (an access to

the SCISR register followed by a read to the

SCIDR register).

STATUS REGISTER (SCISR)

Read Only

Reset Value: 1100 0000 (C0h)

7

0

0: No Framing error

TDRE

TC

RDRF IDLE

LHE

NF

FE

PE

1: Framing error detected

Bits 7:4 = Same function as in SCI mode, please

refer to Section 9.5.8 SCI Mode Register Descrip-

tion.

Bit 0 = PE Parity error.

This bit is set by hardware when a LIN parity error

occurs (if the PCE bit is set) in receiver mode. It is

cleared by a software sequence (a read to the sta-

tus register followed by an access to the SCIDR

data register). An interrupt is generated if PIE=1 in

the SCICR1 register.

Bit 3 = LHE LIN Header Error.

During LIN Header this bit signals three error

types:

0: No LIN parity error

1: LIN Parity error detected

– The LIN Synch Field is corrupted and the SCI is

blocked in LIN Synch State (LSF bit=1).

– A timeout occurred during LIN Header reception

CONTROL REGISTER 1 (SCICR1)

Read/Write

Reset Value: x000 0000 (x0h)

– An overrun error was detected on one of the

header field (see OR bit description in Section

9.5.8 SCI Mode Register Description)).

An interrupt is generated if RIE=1 in the SCICR2

register. If blocked in the LIN Synch State, the LSF

bit must first be reset (to exit LIN Synch Field state

and then to be able to clear LHE flag). Then it is

cleared by the following software sequence : an

access to the SCISR register followed by a read to

the SCIDR register.

7

0

R8

T8

SCID

M

WAKE PCE

PS

PIE

Bits 7:3 = Same function as in SCI mode, please

refer to Section 9.5.8 SCI Mode Register Descrip-

tion.

0: No LIN Header error

1: LIN Header error detected

Bit 2 = PCE Parity control enable.

This bit is set and cleared by software. It selects

the hardware parity control for LIN identifier parity

check.

Note:

Apart from the LIN Header this bit signals an Over-

run Error as in SCI mode, (see description in Sec-

tion 9.5.8 SCI Mode Register Description)

0: Parity control disabled

1: Parity control enabled

When a parity error occurs, the PE bit in the

SCISR register is set.

Bit 2 = NF Noise flag

In LIN Master mode (LINE bit = 1 and LSLV bit = 0)

this bit has the same function as in SCI mode,

please refer to Section 9.5.8 SCI Mode Register

Description

Bit 1 = Reserved

In LIN Slave mode (LINE bit = 1 and LSLV bit = 1)

this bit has no meaning.

Bit 0 = Same function as in SCI mode, please refer

to Section 9.5.8 SCI Mode Register Description.

Bit 1 = Bit 1 = FE Framing error.

In LIN slave mode, this bit is set only when a real

128/294

1

ST7MC1/ST7MC2

LINSCI SERIAL COMMUNICATION INTERFACE (LIN Mode) (Cont’d)

CONTROL REGISTER 2 (SCICR2)

Read/Write

1: LDIV is updated at the next received character

(when RDRF=1) after a write to the LPR register

Reset Value: 0000 0000 (00h)

Notes:

7

0

- If no write to LPR is performed between the set-

ting of LDUM bit and the reception of the next

character, LDIV will be updated with the old value.

TIE

TCIE

RIE

ILIE

TE

RE

RWU

SBK

- After LDUM has been set, it is possible to reset

the LDUM bit by software. In this case, LDIV can

be modified by writing into LPR / LPFR registers.

Bits 7:2 Same function as in SCI mode, please re-

fer to Section 9.5.8 SCI Mode Register Descrip-

tion.

Bit 6:5 = LINE, LSLV LIN Mode Enable Bits.

These bits configure the LIN mode:

Bit 1 = RWU Receiver wake-up.

This bit determines if the SCI is in mute mode or

not. It is set and cleared by software and can be

cleared by hardware when a wake-up sequence is

recognized.

0: Receiver in active mode

1: Receiver in mute mode

LINE

LSLV

Meaning

0

1

x

0

1

LIN mode disabled

LIN Master Mode

LIN Slave Mode

Notes:

The LIN Master configuration enables:

– Mute mode is recommended for detecting only

the Header and avoiding the reception of any

other characters. For more details please refer to

Section 9.5.9.3 LIN Reception.

The capability to send LIN Synch Breaks (13 low

bits) using the SBK bit in the SCICR2 register.

The LIN Slave configuration enables:

– In LIN slave mode, when RDRF is set, the soft-

ware can not set or clear the RWU bit.

– The LIN Slave Baud Rate generator. The LIN

Divider (LDIV) is then represented by the LPR

and LPFR registers. The LPR and LPFR reg-

isters are read/write accessible at the address

of the SCIBRR register and the address of the

SCIETPR register

Bit 0 = SBK Send break.

This bit set is used to send break characters. It is

set and cleared by software.

0: No break character is transmitted

1: Break characters are transmitted

– Management of LIN Headers.

– LIN Synch Break detection (11-bit dominant).

Note: If the SBK bit is set to “1” and then to “0”, the

transmitter will send a BREAK word at the end of

the current word.

– LIN Wake-Up method (see LHDM bit) instead

of the normal SCI Wake-Up method.

– Inhibition of Break transmission capability

(SBK has no effect)

CONTROL REGISTER 3 (SCICR3)

Read/Write

Reset Value: 0000 0000 (00h)

– LIN Parity Checking (in conjunction with the

PCE bit)

7

0

Bit 4 = LASE LIN Auto Synch Enable.

This bit enables the Auto Synch Unit (ASU). It is

set and cleared by software. It is only usable in LIN

Slave mode.

LDUM LINE LSLV

LASE

LHDM LHIE LHDF LSF

Bit 7= LDUM LIN Divider Update Method.

This bit is set and cleared by software and is also

cleared by hardware (when RDRF=1). It is only

used in LIN Slave mode. It determines how the LIN

Divider can be updated by software.

0: LDIV is updated as soon as LPR is written (if no

Auto Synchronization update occurs at the

same time).

0: Auto Synch Unit disabled

1: Auto Synch Unit enabled.

Bit 3 = LHDM LIN Header Detection Method

This bit is set and cleared by software. It is only us-

able in LIN Slave mode. It enables the Header De-

tection Method. In addition if the RWU bit in the

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ST7MC1/ST7MC2

LINSCI SERIAL COMMUNICATION INTERFACE (LIN Mode) (Cont’d)

SCICR2 register is set, the LHDM bit selects the

Wake-Up method (replacing the WAKE bit).

0: LIN Synch Break Detection Method

Figure 70. LSF bit set and clear

11 dominant bits

parity bits

1: LIN Identifier Field Detection Method

LSF bit

Bit 2 = LHIE LIN Header Interrupt Enable

This bit is set and cleared by software. It is only us-

able in LIN Slave mode.

LIN Synch

Break

LIN Synch

Field

Identifier

Field

0: LIN Header Interrupt is inhibited.

1: An SCI interrupt is generated whenever

LHDF=1.

LIN DIVIDER REGISTERS

Bit 1= LHDF LIN Header Detection Flag

This bit is set by hardware when a LIN Header is

detected and cleared by a software sequence (an

access to the SCISR register followed by a read of

the SCICR3 register). It is only usable in LIN Slave

mode.

LDIV is coded using the two registers LPR and LP-

FR. In LIN Slave mode, the LPR register is acces-

sible at the address of the SCIBRR register and

the LPFR register is accessible at the address of

the SCIETPR register.

0: No LIN Header detected.

1: LIN Header detected.

LIN PRESCALER REGISTER (LPR)

Read/Write

Reset Value: 0000 0000 (00h)

Notes: The header detection method depends on

the LHDM bit:

7

0

– If LHDM=0, a header is detected as a LIN

Synch Break.

LPR7 LPR6 LPR5 LPR4 LPR3 LPR2 LPR1 LPR0

– If LHDM=1, a header is detected as a LIN

Identifier, meaning that a LIN Synch Break

Field + a LIN Synch Field + a LIN Identifier

Field have been consecutively received.

LPR[7:0] LIN Prescaler (mantissa of LDIV)

These 8 bits define the value of the mantissa of the

LIN Divider (LDIV):

Bit 0= LSF LIN Synch Field State

LPR[7:0]

00h

Rounded Mantissa (LDIV)

This bit indicates that the LIN Synch Field is being

analyzed. It is only used in LIN Slave mode. In

Auto Synchronization Mode (LASE bit=1), when

the SCI is in the LIN Synch Field State it waits or

counts the falling edges on the RDI line.

SCI clock disabled

01h

1

...

FEh

FFh

254

255

It is set by hardware as soon as a LIN Synch Break

is detected and cleared by hardware when the LIN

Synch Field analysis is finished (See Figure 70).

This bit can also be cleared by software to exit LIN

Synch State and return to idle mode.

0: The current character is not the LIN Synch Field

1: LIN Synch Field State (LIN Synch Field under-

going analysis)

Caution: LPR and LPFR registers have different

meanings when reading or writing to them. Conse-

quently bit manipulation instructions (BRES or

BSET) should never be used to modify the

LPR[7:0] bits, or the LPFR[3:0] bits.

130/294

1

ST7MC1/ST7MC2

LINSCI SERIAL COMMUNICATION INTERFACE (LIN Mode) (Cont’d)

LIN PRESCALER FRACTION REGISTER

(LPFR)

will effectively update LDIV and so the clock gen-

eration.

Read/Write

Reset Value: 0000 0000 (00h)

2. In LIN Slave mode, if the LPR[7:0] register is

equal to 00h, the transceiver and receiver input

clocks are switched off.

7

0

LPFR LPFR LPFR LPFR

Examples of LDIV coding:

Example 1: LPR = 27d and LPFR = 12d

This leads to:

0

3

2

1

0

Mantissa (LDIV) = 27d

Bits 7:4= Reserved.

Bits 3:0 = LPFR[3:0] Fraction of LDIV

Fraction (LDIV) = 12/16 = 0.75d

Therefore LDIV = 27.75d

These 4 bits define the fraction of the LIN Divider

(LDIV):

Example 2: LDIV = 25.62d

This leads to:

LPFR[3:0]

Fraction (LDIV)

0h

1h

...

0

LPFR = rounded(16*0.62d)

= rounded(9.92d) = 10d = Ah

LPR = mantissa (25.620d) = 25d = 1Bh

1/16

...

Eh

Fh

14/16

15/16

Example 3: LDIV = 25.99d

This leads to:

1. When initializing LDIV, the LPFR register must

be written first. Then, the write to the LPR register

LPFR = rounded(16*0.99d)

= rounded(15.84d) = 16d

131/294

1

ST7MC1/ST7MC2

LINSCI SERIAL COMMUNICATION INTERFACE (LIN Mode) (Cont’d)

LIN HEADER LENGTH REGISTER (LHLR)

Read Only

Reset Value: 0000 0000 (00h).

LHL[1:0]

Fraction (57 -

T

)

HEADER

0h

0

1h

1/4

1/2

3/4

7

0

2h

3h

LHL7 LHL6 LHL5 LHL4 LHL3 LHL2 LHL1 LHL0

Example of LHL coding:

Note: In LIN Slave mode when LASE = 1 or LHDM

= 1, the LHLR register is accessible at the address

of the SCIERPR register.

Example 1: LHL = 33h = 001100 11b

LHL(7:3) = 1100b = 12d

LHL(1:0) = 11b = 3d

Otherwise this register is always read as 00h.

This leads to:

Bit 7:0 = LHL[7:0] LIN Header Length.

Mantissa (57 - T

) = 12d

HEADER

This is a read-only register, which is updated by

hardware if one of the following conditions occurs:

- After each break detection, it is loaded with

“FFh”.

Fraction (57 - T

Therefore:

) = 3/4 = 0.75

HEADER

(57 - T

and T

) = 12.75d

= 44.25d

HEADER

- If a timeout occurs on T

00h.

, it is loaded with

HEADER

- After every successful LIN Header reception (at

the same time than the setting of LHDF bit), it is

loaded with a value (LHL) which gives access to

the number of bit times of the LIN header length

Example 2:

57 - T

= 36.21d

HEADER

LHL(1:0) = rounded(4*0.21d) = 1d

(T

below:

). The coding of this value is explained

HEADER

LHL(7:2) = Mantissa (36.21d) = 36d = 24h

Therefore LHL(7:0) = 10010001 = 91h

LHL Coding:

T

= 57

HEADER_MAX

LHL(7:2) represents the mantissa of (57 - T

Example 3:

HEAD-

)

ER

57 - T

= 36.90d

HEADER

LHL(1:0) represents the fraction (57 - T

)

HEADER

LHL(1:0) = rounded(4*0.90d) = 4d

Mantissa

The carry must be propagated to the matissa :

LHL(7:2) = Mantissa (36.90d) + 1= 37d =

Therefore LHL(7:0) = 10110000= A0h

Mantissa

LHL[7:2]

(

T

)

(57 -

T

)

HEADER

0h

1h

0

57

56

...

1

...

39h

3Ah

3Bh

...

56

57

58

...

0

Never Occurs

...

3Eh

3Fh

62

63

Never Occurs

Initial value

132/294

1

ST7MC1/ST7MC2

SERIAL COMMUNICATION INTERFACE (Cont’d)

Table 21. SCI Register Map and Reset Values

Addr.

Register Name

SCI1SR

7

6

5

4

3

2

1

0

(Hex.)

TDRE

TC

1

RDRF

0

IDLE

OR/LHE

NF

0

FE

0

PE

0

0018h

Reset Value

SCI1DR

1

DR7

-

0

DR4

-

0

DR3

-

DR6

-

DR5

-

DR2

-

DR1

-

DR0

-

0019h

001Ah

Reset Value

SCP1

LPR7

0

SCP0

LPR6

0

SCT2

LPR5

0

SCT1

LPR4

0

SCT0

LPR3

0

SCR2

LPR2

0

SCR1

LPR1

0

SCR0

LPR0

0

SCI1BRR

LPR (LIN Slave Mode)

Reset Value

SCI1CR1

R8

T8

SCID

0

M

WAKE

0

PCE

0

PS

0

PIE

0

001Bh

001Ch

001Dh

Reset Value

SCI1CR2

x

0

TIE

0

TCIE

0

RIE

0

ILIE

0

TE

RE

0

RWU

0

SBK

0

Reset Value

SCI1CR3

0

LDUM

0

LINE

0

LSLV

0

LASE

0

LHDM

0

LHIE

0

LHDF

0

LSF

0

Reset Value

SCI1ERPR

ERPR7 ERPR6 ERPR5 ERPR4 ERPR3 ERPR2 ERPR1 ERPR0

LHL7

LHL6

LHL5

LHL4

LHL3

LHL2

LHL1

LHL0

001Eh

001Fh

LHLR (LIN Slave Mode)

Reset Value

0

ETPR7 ETPR6 ETPR5 ETPR4 ETPR3 ETPR2 ETPR1 ETPR0

SCI1TPR

0

LPRF3

0

LPRF2 LPRF1 LPRF0

LPRF (LIN Slave Mode)

Reset Value

0

133/294

1

ST7MC1/ST7MC2

9.6 MOTOR CONTROLLER (MTC)

9.6.1 Introduction

Table 22. MTC Functional Blocks

The ST7 Motor Controller (MTC) can be seen as a

Three-Phase Pulse Width Modulator multiplexed

on six output channels and a Back Electromotive

Force (BEMF) zero-crossing detector for sensor-

less control of Permanent Magnet Direct Current

(PM BLDC) brushless motors.

Section

Input Detection Block

Input Pins

Page

142

145

146

147

149

Sensorless Mode

D Event detection

The MTC is particularly suited to driving brushless

motors (either induction or permanent magnet

types) and supports operating modes like:

Z Event Detection

Demagnetization (D) Event

Z Event Generation (BEMF Zero Crossing) 151

– Commutation step control with motor voltage

regulation and current limitation

Protection for ZH event detection

Position Sensor Mode

Sampling block

153

154

155

158

160

161

162

164

165

167

168

171

176

181

182

184

186

187

190

195

196

197

201

202

– Commutation step control with motor current

regulation, i.e. direct torque control

Commutation Noise Filter

Speed Sensor Mode

Tachogenerator Mode

Encoder Mode

– Position Sensor or sensorless motor phase com-

mutation control (six-step mode)

– BEMF zero-crossing detection with high sensitiv-

ity. The integrated phase voltage comparator is

directly referred to the full BEMF voltage without

any attenuation. A BEMF voltage down to

200 mV can be detected, providing high noise

immunity and self-commutated operation in a

large speed range.

Summary

Delay Manager

Switched Mode

Autoswitched Mode

Debug Option

– Realtime motor winding demagnetization detec-

tion for fine-tuning the phase voltage masking

time to be applied before BEMF monitoring.

Checks and Controls for simulated events

Speed Measurement Mode

Summary

– Automatic and programmable delay between

BEMF zero-crossing detection and motor phase

commutation.

PWM Manager

Voltage Mode

Over Current Handling in Voltage mode

Current Mode

– PWM generation for three-phase sinewave or

three-channel independent PWM signals.

Current Feedback Comparator

Current feedback amplifier

Measurement Window

Channel Manager

MPHST Phase State Register

Emergency Feature

Dead Time Generator

Programmable Chopper

PWM Generator Block

Main Features

Functional Description

Prescaler

PWM Operating mode

Repetition Down-Counter

PWM interrupt generation

Timer Re-synchronisation

PWM generator initialization and start-up

134/294

1

ST7MC1/ST7MC2

MOTOR CONTROLLER (Cont’d)

Table 23. MTC Registers

9.6.2 Main Features

ꢀ

Two on-chip analog comparators, one for BEMF

zero-crossing detection, the other for current

regulation or limitation

Register

page

(RPGS

bit)

Register

Description

Page

ꢀ

Seven selectable reference voltages for the

hysteresis comparator (0.2 V, 0.6 V, 1 V, 1.5 V,

2 V, 2.5 V, 3.5 V) and the possibility to select an

external reference pin (MCVREF).

MTIM

Timer Counter Register

0

203

Timer LSB (mode depend-

ent)

MTIML

0

ꢀ

8-bit timer (MTIM) with three compare registers

and two capture features, which may be used as

the Delay manager of a speed measurement

unit

Measurement window generator for BEMF

zero-crossing detection

Filter option for the zero-crossing detection.

Auto-calibrated prescaler with 16 division steps

8x8-bit multiplier

MZPRV Capture Z Register

0

203

204

205

206

208

209

210

212

n-1

MZREG Capture Z Register

n

MCOMP Compare C

Register

n+1

MDREG Demagnetization Reg.

MWGHT A Weight Register

n

MPRSR Prescaler & Sampling Reg.

ꢀ

MIMR

MISR

Interrupt Mask Register

Interrupt Status Register

Control Register A

MCRA

MCRB

MCRC

Phase input multiplexer

Sophisticated output management:

Control Register B

Control Register C

– The six output channels can be split into two

groups (high & low)

– The PWM signal can be multiplexed on high,

low or both groups, alternatively or simultane-

ously, for six-step motor drives

MPHST Phase State Register

MDFR

D Event Filter Register

Current Feedback Filter

Register

MCFR

0

211

– 12-bit PWM generator with full modulation ca-

pability (0 and 100% duty cycle), edge or cent-

er-aligned patterns

– Dedicated interrupt for PWM duty cycles up-

dating and associated PWM repetition coun-

ter.

MREF

MPCR

MREP

Reference register

0

1

213

214

215

216

217

218

219

220

221

222

223

PWM Control Register

Repetition Counter Reg.

MCPWH Compare W Register High

MCPWL Compare W Register Low

MCPVH Compare V Register High

MCPVL Compare V Register Low

MCPUH Compare U Register High

MCPUL Compare U Register Low

MCP0H Compare 0 Register High

MCP0L Compare 0 Register Low

– Programmable deadtime insertion unit.

– Programmable High frequency Chopper in-

sertion and high current PWM outputs for di-

rect optocoupler drives.

– The output polarity is programmable channel

by channel.

– A programmable bit (active low) forces the

outputs in HiZ, Low or High state, depending

on option byte 1 (refer to “ST7FMC Device

Configuration And Ordering Information” sec-

tion).

– An “emergency stop” input pin (active low)

asynchronously forces the outputs in HiZ, Low

or High state, depending on option byte 1 (re-

fer to “ST7FMC Device Configuration And Or-

dering Information” section).

MDTG

MPOL

Dead Time Generator reg.

Polarity Register

MPWME PWM register

MCONF Configuration register

MPAR

MZFR

MSCR

Parity register

Z Event Filter Register

Sampling Clock Register

135/294

1

ST7MC1/ST7MC2

MOTOR CONTROLLER (Cont’d)

9.6.3 Application Example: PM BLDC motor

drive

The end of demagnetization event (D), is also de-

tected by the MTC or simulated with a timer com-

pare feature when no detection is possible.

This example shows a six-step command se-

quence for a 3-phase permanent magnet DC

brushless motor (PM BLDC motor). Figure 72

shows the phase steps and voltage, while Table

24 shows the relevant phase configurations.

The MTC manages these three events always in

the same order: Z generates C after a delay com-

puted in realtime, then waits for D in order to ena-

ble the peripheral to detect another Z event.

To run this kind of motor efficiently, an autoswitch-

ing mode has to be used, i.e. the position of the ro-

tor must self-generate the powered winding com-

mutation. The BEMF zero crossing (Z event) on

the non-excited winding is used by the MTC as a

rotor position sensor. The delay between this

event and the commutation is computed by the

The BEMF zero-crossing event (Z), can also be

detected by the MTC or simulated with a timer

compare feature when no detection is possible.

The speed regulation is managed by the micro-

controller, by means of an adjustable reference

current level in case of current control, or by direct

PWM duty-cycle adjustment in case of voltage

control.

MTC and the hardware commutation event C is

n

automatically generated after this delay.

After the commutation occurs, the MTC waits until

the winding is completely demagnetized by the

free-wheeling diode: during this phase the winding

is tied to 0V or to the HV high voltage rail and no

BEMF can be read. At the end of this phase a new

BEMF zero-crossing detection is enabled.

136/294

1

ST7MC1/ST7MC2

MOTOR CONTROLLER (Cont’d)

Figure 71. Chronogram of Events (in Autoswitched Mode)

.

C

event

H

Z

or Z event

S

H

D

event

H

S

Cn processing

Wait for C

Wait for D

n

Wait for Z

T

Z

n

D

C

n

t

Voltage on phase A

Voltage on phase B

Voltage on phase C

BEMF

sampling

P signal when sampled

(Output of the

V

DD

analog MUX)

V

REF

V

(Threshold value for

Input comparator)

SS

137/294

1

ST7MC1/ST7MC2

MOTOR CONTROLLER (Cont’d)

Figure 72. Example of Command Sequence for 6-step Mode (typical 3-phase PM BLDC Motor

Control)

Σ

3

1

2

3

4

5

6

1

2

Step

HV

Switch

0

T0

T2

T4

B

1

2

3

4

I

6

1

I

4

I

3

5

I

A

2

C

I

5

Node

HV

HV/2

0

A

B

C

T1

T3

T5

HV

HV/2

0

HV

HV/2

0

Note: Control & sampling PWM influence is not represented on these simplified chronograms.

Σ

5

6

1

2

3

4

HV

C

2

C

4

D

2

HV/2

Superimposed voltage

(BEMF induced by rotor)

- approx. HV/2 (PWM on)

- approx. 0V (PWM off)

0V

Z

D

Z

5

2

t

PWM off pulses

Demagnetization

Commutation delay

Wait for BEMF = 0

138/294

1

ST7MC1/ST7MC2

MOTOR CONTROLLER (Cont’d)

All detections of Z events are done during a short

the low side winding voltage is also held at 0V by

the low side ON switch and the complete BEMF

voltage is present on the third winding: detection is

then possible.

n

measurement window while the high side switch is

turned off. For this reason the PWM signal is ap-

plied on the high side switches.

When the high side switch is off, the high side

winding is tied to 0V by the free-wheeling diode,

Table 24. Step Configuration Summary

Configuration

Step

Σ

6

1

2

3

4

5

Current direction

High side

A to B

T0

A to C

T0

B to C

T2

B to A

T2

C to A

T4

C to B

T4

Low side

T3

T5

T1

T3

OO[5:0] bits in MPHST register

001001

100001

100100

000110

010010

011000

Measurement done on:

IS[1:0] bits in MPHST register

Back EMF shape

MCIC

10

MCIB

01

MCIA

00

MCIC

10

MCIB

01

MCIA

00

Falling

Rising

Falling

Rising

Falling

Rising

CPB bit in MCRB register

(ZVD bit = 0)

0

1

0

1

0

1

Voltage on measured point at the

start of demagnetization

0V

HV

0V

HV

0V

HV

HDM-SDM bits in MCRB register

10

11

10

11

10

11

PWM side selection to accelerate

demagnetization

Low Side High Side Low Side High Side Low Side High Side

Driver selection to accelerate de-

magnetization

T3

T0

T5

T2

T1

T4

For a detailed description of the MTC registers,

see Section 9.6.13.

The variable voltage levels to be applied on the

motor terminals come from continuously varying

duty cycle, from one PWM period to the other (re-

fer to Figure 73 on page 140). The PWM counter

generates a dedicated Update event (U event)

which:

9.6.4 Application Example: AC Induction Motor

Drive

Although the command sequence is rather differ-

ent between a PM BLDC and an AC three-phase

induction motor, the Motor Controller can be con-

figured to generate three-phase sinusoidal voltag-

es.

– updates automatically the compare registers set-

ting the duty cycle to avoid time critical issues

and ensure glitchless PWM operation.

– generates a dedicated U interrupt in which the

values for the next coming update event are

loaded in compare preload registers.

A timer with three independent PWM channels is

available for this purpose. Based on each of the

PWM reference signal, two complemented PWM

signals with deadtime are generated on the output

pins (6 in total), to drive directly an inverter with tri-

ple half bridge topology.

The shape of the output voltage (voltage, frequen-

cy, sinewave, trapezoid, ...) is completely man-

aged by the applicative software, in charge of

computing the compare values to be loaded for a

given PWM duty-cycle (refer to Figure 74).

139/294

1

ST7MC1/ST7MC2

MOTOR CONTROLLER (Cont’d)

Finally, the PWM modulated voltage generated by

the power stage is smoothed by the motor induct-

ance to get sinusoidal currents in the stator wind-

ings.

perform speed acquisition of the most common

speed sensor, without the need of an additional

standard timer.

This speed measurement timer with clear-on-cap-

ture and clock prescaler auto-setting allows to

keep the CPU load to a minimum level while taking

benefit of the embedded input comparator and

edge detector.

The induction motor being asynchronous, there is

no need to synchronize the rotor position to the

sinewave generation phase in most of the applica-

tions.

Part of the MTC dedicated to delay computation

and event sampling can thus be reconfigured to

Figure 73. Complementary PWM generation for three-phase induction motor (1 phase represented)

U event

Compare preload

register processing

MCMP0

MCMPU

PWM generator

counter

PWM Ref

Signal

T0

T1

Dead time

insertion

140/294

1

ST7MC1/ST7MC2

MOTOR CONTROLLER (Cont’d)

Figure 74. Typical command signals of a three-phase induction motor

HV

Phase A *

Phase B *

T0

T2

T4

B

Phase C *

A

C

PWM

period

PWM output

Duty Cycle

T1

T3

T5

PWM output

Duty Cycle

99% 100% 99%

51%

50%

49%

PWM output

Duty Cycle

1%

0%

1%

* These simplified chronograms represent the phase voltages after low-pass filtering of the

PWM outputs reference signals

141/294

1

ST7MC1/ST7MC2

MOTOR CONTROLLER (Cont’d)

9.6.5 Functional Description

to Table 35 for set-up information). The block dia-

gram is shown in Figure 76 for the Position Sen-

sor/Sensorless modes (TES[1:0] = 00) and in Fig-

ure 86 for the Speed Sensor mode (TES[1:0] = 01,

10, 11).

The MTC can be split into five main parts as

shown in the simplified block diagram in Figure 75.

Each of these parts may be configured for different

purposes:

9.6.6.1 Input Pins

ꢀ

INPUT DETECTION BLOCK with a comparator,

an input multiplexer and an incremental encoder

interface, which may work as:

The MCIA, MCIB and MCIC input pins can be

used as analog or as digital pins.

– A BEMF zero-crossing detector

– A Speed Sensor Interface

The DELAY MANAGER with an 8/16-bit timer

and an 8x8 bit multiplier, which may work as a:

– In sensorless mode, the analog inputs are used

to measure the BEMF zero crossing and to de-

tect the end of demagnetization if required.

– In sensor mode, the analog inputs are used to

get the Hall sensor information.

– 8-bit delay manager

– Speed Measurement unit

– In speed sensor mode (e.g. tachogenerator), the

inputs are used as digital pins. When using an

AC tachogenerator, a small external circuit may

be needed to convert the incoming signal into a

square wave signal which can be treated by the

MTC.

ꢀ

The

PWM

MANAGER,

including

a

measurement window generator,

selector and a current comparator.

The CHANNEL MANAGER with the PWM

multiplexer, polarity programming, deadtime

insertion and high frequency chopping

capability and emergency HiZ configuration

input.

a

mode

Due to the presence of diodes, these pins can per-

manently support an input current of 5mA. In sen-

sorless mode, this feature enables the inputs to be

connected to each motor phase through a single

resistor.

ꢀ

The THREE-PHASE PWM GENERATOR with

12-bit free-running counter and repetition

counter.

A multiplexer, programmed by the IS[1:0] bits in

the MPHST register selects the input pins and

connects them to the control logic in either sensor-

less or tachogenerator mode. In encoder mode, it

is mandatory to connect sensor digital outputs to

the MCIA and MCIB pins.

9.6.6 Input Detection Block

This block can operate in Position sensor mode, in

sensorless mode or in Speed Sensor mode. The

mode is selected via the SR bit in the MCRA reg-

ister and the TES[1:0] bits in MPAR register (refer

142/294

1

ST7MC1/ST7MC2

MOTOR CONTROLLER (Cont’d)

Figure 75. Simplified MTC Block Diagram

BEMF ZERO-CROSSING

DETECTOR

DELAY MANAGER

or SPEED MEASURE UNIT (not represented)

MCIA

MCIB

MCIC

BEMF=0

[Z]

MTIM

TIMER

DELAY

WEIGHT

CAPTURE Zn

MCVREF

TACHO

Int/Ext

Encoder Unit

=?

DELAY = WEIGHT x Zn

INPUT DETECTION

COMMUTE [C]

MCO5

MCO4

MCO3

MCO2

MCO1

MCO0

MEASUREMENT

WINDOW

GENERATOR

(I)

CURRENT

VOLTAGE

(V)

(I)

(V)

MODE

U, V, W

NMCES

OAP

OAON bit

Phases

+

-

CFAV bit

OAN

OAZ

PWM MANAGER

MCCFI

V

DD

ADC

R

1

MCCREF

(V)

(I)

Phase U

CHANNEL

MANAGER

R

2

C

12-bit THREE-PHASE

PWM GENERATOR

R

3

1

12-bit counter

(V)

PCN bit

Phase U

Phase V

Phase W

MCPWMU

MCPWMV

MCPWMW

[Z] : Back EMF Zero-crossing event

Z : Time elapsed between two consecutive Z events

n

[C] : Commutation event

C : Time delayed after Z event to generate C event

n

(I): Current mode

(V): Voltage mode

143/294

1

ST7MC1/ST7MC2

MOTOR CONTROLLER (Cont’d)

Figure 76. Input Stage in Sensorless or Sensor Mode (bits TES[1:0] = 00)

Event Detection

Input Comparator Block

Input Block

MPHST Register

Input Sel Reg

IS[1:0]

MDFR Register

DWF[3:0]

n

1

2

SR bit

MCIA

MCIB

C

MZFR Register

ZWF[3:0]

S,H

A

B

C

00

MCRA Register

01

10

+

-

Sample

D

Q

MCIC

CP

D

S,H

C

MCVREF

S,H

111

V

REF

MCRC Register

MCONF Register

SPLG bit

DS[3:0] bits

VR[2:0]

MCRC Register

f

SCF

Sampling frequency

I

12-bit PWM generator Signal U

V

MCRA Register

V0C1 bit

Notes

:

Updated/Shifted on R

Reg

MCRA Register

PZ bit

MCRB Register MPOL Register

Updated with Reg

on C

n+1

Reg

n

CPB bit*

ZVD bit

n

I

C

urrent Mode

V

Voltage Mode

events:

Z Event Generation

C

Z

Commutation

BEFM Zero-crossing

MPOL Register

REO bit

D

S,H

End Of Demagnetization

Emergency Stop

D

S,H

E

C

+/-

Ratio Updated (+1 or -1)

Multiplier Overflow

S,H

R

O

or

to Z Generation

H

1

2

Branch taken after C event

Branch taken after D event

Sample

2

1

D Event Generation

MCRA Register

SR bit

or

to D Generation

H

CPB bit* HDM bit*

n

MCRB Register

* = Preload register, changes taken into account at next C event

144/294

1

ST7MC1/ST7MC2

MOTOR CONTROLLER (Cont’d)

9.6.6.2 Sensorless Mode

voltage is near to ground voltage (instead of V /2

DD

when the excited windings are powered) and the

complete BEMF voltage is present on the non-ex-

cited winding terminal, referred to the ground ter-

minal.

This mode is used to detect BEMF zero crossing

and end of demagnetization events.

The analog phase multiplexer connects the non-

excited motor winding to an analog 100mV hyster-

esis comparator referred to a selectable reference

voltage.

The zero crossing sampling frequency is then de-

fined, in current mode, by the measurement win-

dow generator frequency (SA[3:0] bits in the

MPRSR register) or, in voltage mode, by the PWM

generator frequency and phase U duty cycle.

IS[1:0] bits in MPHST register allow to select the

input which will be drive to the comparator (either

MCIA, B or C). Be careful that the comparator is

OFF until CKE and/or DAC bit are set in MCRA

register.

During a short period after a phase commutation

(C event), the winding where the back-emf will be

read is no longer excited but needs a demagneti-

sation phase during which the BEMF cannot be

read. A demagnetization current goes through the

free-wheeling diodes and the winding voltage is

stuck at the high voltage or to the ground terminal.

For this reason an “end of demagnetization event”

D must be detected on the winding before the de-

tector can sense a BEMF zero crossing.

The VR[2:0] bits in the MCRC register select the

reference voltage from seven internal values de-

pending on the noise level and the application volt-

age supply. The reference voltage can also be set

externally through the MCVREF pin when the

VR[2:0] bits are set.

Table 25. Threshold voltage setting

For the end-of-demagnetization detection, no spe-

cial PWM configuration is needed, the comparator

VR2

VR1

VR0

Vref voltage threshold

Threshold voltage set by

external MCVREF pin

sensing is done at a selectable frequency (f

see Table 83.

),

SCF

1

So, the three events: C (commutation), D (demag-

netization) and Z (BEMF zero crossing) must al-

ways occur in this order in autoswitched mode

when hard commutation is selected.

1

0

1

0

1

0

1

0

1

0

1

0

3.5V*

2.5V*

2V*

The comparator output is processed by a detector

that automatically recognizes the D or Z event, de-

pending on the CPB or ZVD edge and level config-

uration bits as described in Table 30.

1.5V*

1V*

0.6V*

0.2V*

To avoid wrong detection of D and Z events, a

blanking window filter is implemented for spike fil-

tering. In addition, by means of an event counter,

software can filter several consecutive events up

to a programmed limit before generating the D or Z

event internally. This is shown in Figure 77 and

Figure 78.

*Typical value for V =5V.

DD

BEMF detections are performed during the meas-

urement window, when the excited windings are

free-wheeling through the low side switches and

diodes. At this stage the common star connection

145/294

1

ST7MC1/ST7MC2

MOTOR CONTROLLER (Cont’d)

9.6.6.3 D Event detection

C to D window fil-

DWF3 DWF2 DWF1 DWF0 ter in Sensorless SR=1

Mode (SR=0)

In sensorless mode, the D Window Filter becomes

active after each C event. It blanks out the D event

during the time window defined by the DWF[3:0]

bits in the MDFR register (see Table 26). The reset

value is 200µs.

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

5 µs

10 µs

15 µs

20 µs

25 µs

30 µs

35 µs

40 µs

60 µs

80 µs

100 µs

120 µs

140 µs

160 µs

180 µs

200 µs

This Window Filter becomes active after both

hardware and software C events.

The D Event Filter becomes active after the D Win-

dow Filter. It counts the number of consecutive D

events up to a limit defined by the DEF[3:0] bits in

the MDFR register. The reset value is 1. The D bit

is set when the counter limit is reached.

Sampling is done at a selectable frequency

(f

), see Table 83.

SCF

The D event filter is active only for a hardware D

event (D ). For a simulated (D ) event, it is forced

H

S

to 1.

Figure 77. D Window and Event Filter Flowchart

C

Note: Times are indicated for 4 MHz f

PERIPH

Table 27. D Event filter Setting

WINDOW

FILTER

DEF3 DEF2 DEF1 DEF0 D event Limit SR=1

End of

No

Blanking Window

?

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

3

Yes

4

Sampling

5

EVENT

FILTER

6

7

D

Event

?

No

Yes

8

9

10

11

12

13

14

15

16

No

Reset counter

Limit=1?

Yes

Increment counter

Counter=Limit?

No

Yes

Set the D bit

146/294

1

ST7MC1/ST7MC2

MOTOR CONTROLLER (Cont’d)

9.6.6.4 Z Event Detection

Table 28. Z Window filter Setting

In sensorless mode, the Z window filter becomes

active after each D event. It blanks out the Z event

during the time window defined by the ZWF[3:0]

bits in the MZFR register (see Table 28). The reset

value is 200µs. This Window Filter becomes active

after both hardware and software C events.

D to Z window fil-

ZWF3 ZWF2 ZWF1 ZWF0 ter in Sensorless SR=1

Mode (SR=0)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

5 µs

10 µs

15 µs

20 µs

25 µs

30 µs

35 µs

40 µs

60 µs

80 µs

100 µs

120 µs

140 µs

160 µs

180 µs

200 µs

The Z Event Filter becomes active after the Z Win-

dow Filter. It counts the number of consecutive Z

events up to a limit defined by the ZEF[3:0] bits in

the MZFR register. The reset value is 1. The Z bit

is set when the counter limit is reached.

No

Win-

dow

Filter

after

D

Sampling is done at a selectable frequency

(f

), see Table 83.

SCF

The Z event filter is active only for a hardware Z

event (Z ). For a simulated (Z ) event, it is forced

event

H

S

to 1.

Figure 78. Z Window and Event Filter Flowchart

D

WINDOW

Note: Times are indicated for 4 MHz f

PERIPH

End of

Blanking

Window

FILTER

No

Table 29. Z Event filter Setting

ZEF3 ZEF2 ZEF1 ZEF0

Z event Limit

?

Yes

Sampling

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

EVENT

FILTER

Yes

3

Z

Event

?

No

4

5

6

No

Reset counter

Limit=1?

Yes

7

8

Increment counter

9

10

11

12

13

14

15

16

No

Counter=Limit?

Yes

Set the Z bit

147/294

1

ST7MC1/ST7MC2

MOTOR CONTROLLER (Cont’d)

Table 30 shows the event control selected by the

ZVD and CPB bits. In most cases, the D and Z

events have opposite edge polarity, so the ZVD bit

is usually 0.

Table 30. ZVD and CPB Edge Selection Bits

ZVD bit

CPB bit

Event generation vs input data sampled

DWF

ZWF

ZEF

DEF

0

C

D

Z

H

ZEF

ZWF

0

1

0

1

C

D

H

ZEF

DWF

ZWF

DEF

C

D

Z

H

DWF

ZWF

C

D

H

Note: The ZVD bit is located in the MPOL register, the CPB bit is in the MCRB register.

Legend:

DWF= D window filter

DEF= D event filter

ZWF = Z window filter

ZEF = Z event filter

Refer also to Table 34 on page 158.

148/294

1

ST7MC1/ST7MC2

MOTOR CONTROLLER (Cont’d)

9.6.6.5 Demagnetization (D) Event

not precede a D event because the latter could

be detected as a Z event.

H

At the end of the demagnetization phase, current

no longer goes through the free-wheeling diodes.

The voltage on the non-excited winding terminal

goes from one of the power rail voltages to the

common star connection voltage plus the BEMF

voltage. In some cases (if the BEMF voltage is

positive and the free-wheeling diodes are at

ground for example) this end of demagnetization

can be seen as a voltage edge on the selected

MCIx input and it is called a hardware demagneti-

Simulated demagnetization can also be always

used if the HDM bit is reset and the SDM bit is set.

This mode works as a programmable masking

time between the C and Z events. To drive the

H

motor securely, the masking time must be always

greater than the real demagnetization time in order

to avoid a spurious Z event.

When an event occurs, (either D or D ) the DI bit

H

S

in the MISR register is set and an interrupt request

is generated if the DIM bit of register MIMR is set.

zation event D . See Table 30.

H

The D event filter can be used to select the

number of consecutive D events needed to gener-

Caution 1: Due to the alternate automatic capture

and compare of the MTIM timer with MDREG reg-

ate the D event.

H

ister by D and D events, the MDREG register

H S

should be manipulated with special care.

If enabled by the HDM bit in the MCRB register,

the current value of the MTIM timer is captured in

register MDREG when this event occurs in order

to be able to simulate the demagnetization phase

for the next steps.

Caution 2: Due to the event generation protection

in the MZREG, MCOMP and MDREG registers for

Soft Event generation ( See “Built-in Checks and

Controls for simulated events” on page 171.), the

value written in the MDREG register in soft demag-

netisation mode (SDM=1) is checked by hardware

after the C event. If this value is less than or equal

to the MTIM counter value at this moment, the

Software demagnetisation event is generated im-

mediately and the MTIM current value overwrites

the value in the MDREG register to be able to re-

use the right demagnetisation time for another

simulated event generation.

When enabled by the SDM bit in the MCRB regis-

ter, demagnetization can also be simulated by

comparing the MTIM timer with the MDREG regis-

ter. This kind of demagnetization is called simulat-

ed demagnetization D .

S

If the HDM and SDM bits are both set, the first

event that occurs, triggers a demagnetization

event. For this to work correctly, a D event must

S

Figure 79. D Event Generation Mechanism

D

S,H

§

MTIM [8-bit Up Counter]

C

To Z event detection

8

2

1

D

Sample

H

§

MDREG [D ]

n

SPLG bit

MCRC

or

Register

Compare

MCRB Register

CPB bit

*

HDM bit*

n

SDM* bit

SR bit

MCRB Register

MCRA Register

DWF[3:0]

DEF[3:0]

D

S

MDFR Register

D

H

D

S

H

D = D & HDM bit + D & SDM bit

H

S

F(x)

To interrupt generator

HDM bit

SDM bit

§

Register updated on R event

* = Preload register, changes taken into account at next C event

149/294

1

ST7MC1/ST7MC2

MOTOR CONTROLLER (Cont’d)

Table

31.

Demagnetisation

(D) Event

HDM

bit

Meaning

CPB bit = 1

CPB bit = 0

D = D = Output Compare [MDREG, MTIM registers]

S

Undershoot due to

motor parasite or first

sampling

Weak / null

undershoot and

BEMF positive

Σ

2

Σ

5

HVV

HV

HVV

D

C

S

C

H

Simulated Mode

D

H

S

0

(SDM bit =1 and

HDM bit = 0)

D

(*)

S

C

H

HV/2

(*)

0V

Z

D = D

D = D + D

H

S

(Hardware detection only)

(Hardware detection or Output compare true)

Undershoot due to

motor parasite or first

Weak / null

undershoot and

sampling

BEMF positive

Σ

2

Σ

5

HV

C

H

Hardware/Simulat-

ed Mode

D

S

C

H

1

D

(*)

S

(SDM bit = 1 and

HDM bit = 1)

C

H

HV/2

(*)

0V

Z

D

H

Z

H

Z

(*) Note: This is a zoom to the additional voltage induced by the rotor (Back EMF)

Generation (example for ZVD=0)

150/294

1

ST7MC1/ST7MC2

MOTOR CONTROLLER (Cont’d)

9.6.6.6 Event Generation (BEMF Zero

Crossing)

Z

BEMF sensing (high side group). It has to be con-

figured whatever the sampling mode.

When both C and D events have occurred, the

PWM may be switched to another group of outputs

(depending on the OS[2:0] bits in the MCRB regis-

ter) and the real BEMF zero crossing sampling can

start (see Figure 85). After Z event, the PWM can

also be switched to another group of outputs be-

fore the next C event.

When enabled by the HZ bit in MCRC register, the

current value of the MTIM timer is captured in reg-

ister MZREG when this event occurs in order to be

able to compute the real delay in the delay manag-

er part for hardware commutation but also to be

able to simulate zero-crossing events for other

steps.

A BEMF voltage is present on the non-powered

terminal but referred to the common star connec-

When enabled by the SZ bit set in the MCRC reg-

ister, a zero-crossing event can also be simulated

by comparing the MTIM timer value with the

MZREG register. This kind of zero-crossing event

tion of the motor whose voltage is equal to V /2.

DD

When a winding is free-wheeling (during PWM off-

time) its terminal voltage changes to the other

power rail voltage, this means if the PWM is ap-

plied on the high side driver, free-wheeling will be

done through the low side diode and the terminal

will be 0V.

is called simulated zero-crossing Z .

S

If both HZ and SZ bits are set in MCRC register,

the first event that occurs, triggers a zero-crossing

event.

Depending on the edge and level selection (ZVD

and CPB) bits and when PWM is applied on the

correct group, a BEMF zero crossing detection (ei-

This is used to force the common star connection

to 0V in order to read the BEMF referred to the

ground terminal.

ther Z or Z ) sets the ZI bit in the MISR register

H

S

and generates an interrupt if the ZIM bit is set in

the MIMR register.

Consequently, BEMF reading (i.e. comparison

with a voltage close to 0V) can only be done when

the PWM is applied on the high side drivers. When

the BEMF signal crosses the threshold voltage

close to zero, it is called a hardware zero-crossing

Caution 1: Due to the alternate automatic capture

and compare of the MTIM timer with MZREG reg-

ister by Z and Z events, the MZREG register

H

S

should be manipulated with special care.

event Z . A filter can be implemented on the Z

event detection (see Figure 81).

H

Caution 2: Due to the event generation protection

in the MZREG, MCOMP and MDREG registers for

Soft Event generation, the value written in the

MZREG register in simuated zero-crossing mode

(SZ=1) is checked by hardware after the D (either

The Z event filter register (MZFR) is used to select

the number of consecutive Z events needed to

generate the Z event. Alternatively, the PZ bit

H

can be used to enable protection as described in

Figure 81. on page 153

D or D ) event. If this value is less than or equal

H

S

to the MTIM counter value at this moment, the sim-

ulated zero-crossing event is generated immedi-

ately and the MTIM current value overwrites the

value in the MZREG register. See “Built-in Checks

and Controls for simulated events” on page 171.

For this reason the MTC outputs can be split in two

groups called LOW and HIGH and the BEMF read-

ing will be done only when PWM is applied on one

of these two groups. The REO bit in the MPOL

register is used to select the group to be used for

The Z event also triggers some timer/multiplier op-

erations, for more details see Section 9.6.7

151/294

1

ST7MC1/ST7MC2

MOTOR CONTROLLER (Cont’d)

Figure 80. Z Event Generation

MCRA Register

PZ bit

MCRB Register MPOL Register

CPB bit*

ZVD bit

n

§

MTIM [8-bit Up Counter] (MSB)

8

MPOL Register

REO bit

Z

H

D

S,H

§

MZREG [Z ]

n

C

or

2

1

Sample

Compare

MCRC Register

HZ bit

MCRC Register

SZ bit

MZFR register

ZWF[3:0]

To D detection

SPLG bit

DS[3:0]

bits

ZWF[3:0]

ZEF[3:0]

Z

MZFR register

S

Z

H

S

Z = Z & HZ bit+ Z & SZ bit

H

S

Z

H

F(x)

SZ bit

HZ bit

To interrupt generator

§

Register updated on R event

* = Preload register, changes taken into account at next C event

152/294

1

ST7MC1/ST7MC2

MOTOR CONTROLLER (Cont’d)

9.6.6.7 Protection for Z event detection

once this state is detected, the Z event is gener-

H

ated without any verification that the state at the

comparator output of the previous sample was 1.

The purpose of this protection filter is to be sure

that the state of the comparator output at the sam-

ple before was really the opposite of the current

To avoid an erroneous detection of a hardware

zero-crossing event, a filter can be enabled by set-

ting the PZ bit in the MCRA register. This filter will

ensure the detection of a Z event on an edge

H

transition between D event and Z event.

H

state which is generating the Z event. With this

H

Without this protection, Z event detection is done

H

filter, the Z event generation is done on edge

H

directly on the current sample in comparison with

the expected state at the output of the phase com-

parator. For example, if a falling edge transition

(meaning a transition from 1 to 0 at the output of

transition level comparison.

This filter is not needed in sensor mode (SR=1)

and for simulated zero-crossing event (Z ) gener-

S

ation.

the phase comparator) is configured for Z event

H

through the CPB bit in MCRB register, then, the

state 0 is expected at the comparator output and

When the PZ bit is set, the Z event filter ZEF[3:0] in

the MZFR register is ignored.

Figure 81. Protection of Z event detection.

H

V Voltage mode

I Current mode

Rz Rising edge zero-crossing

Fz Falling edge zero-crossing

C Commutation event

Current sample

Fz

Previous sample

C

Falling/Rising Edge

MCRB register MPOL register

+

R

S

R

Q

D

ZVD bit

CPB* bit

-

CP

Phase

Comparator

Fz

S

Direct/Filter PZ

MCRA register

bit 1

F

C Rz

Z

Rz

D

R

Q

D

V

Instantaneous

edge

Sampling clock

CP

S

I

153/294

1

ST7MC1/ST7MC2

MOTOR CONTROLLER (Cont’d)

9.6.6.8 Position Sensor Mode

done at a selectable frequency (f

83. This means that Z event position sensoring is

more precise than it is in sensorless mode.

), see Table

SCF

In position sensor mode (SR=1 in MCRA register),

the rotor position information is given to the periph-

eral by means of logical data on the three inputs

MCIA, MCIB and MCIC (Hall sensors).

There is no minimum off time required for current

control PWM in sensor mode so the minimum off

time is set automatically to 0µs as soon as the SR

bit is set in the MCRA register and a true 100%

duty cycle can be set in the PWM compare U reg-

ister for the PWM generation in voltage mode.

For each step one of these three inputs is selected

(IS[1:0] bits in register MPHST) in order to detect

the Z event. Be careful that the phase comparator

is OFF until CKE and /or DAC bits are set in MCRA

register.

In Sensor mode, the ZEF[3:0] bits in the MZFR

register are active and can be used to define the

number of consecutive Z samples needed to gen-

erate the active event.

In sensor mode, Demagnetization and the related

features (such as the special PWM configuration,

D

or D management, programmable filter) are

S

H

not available (see Table 32)

Procedure for reading sensor inputs in Direct

Access mode: In Direct Access mode, the sen-

sors can be read either when the clock are ena-

bled or disabled (depending on CKE it in MCRA

register). To read the sensor data the following

steps have to be performed:

Table 32. Demagnetisation access

SR bit

Demagnetisation feature

availabilty

MCRA register

1

0

NO

1. Select Direct Access Mode (DAC bit in MCRA

register)

YES

2. Select the appropriate MCIx input pin by means

of the IS[1:0] bits in the MPHST register

In sensor mode configuration the rotor detection

doesn’t need a particular phase configuration to

perform the measurement and a Z event can be

read from any detection window. The sampling is

3. Read the comparator output (HST bit in the

MREF register)

154/294

1

ST7MC1/ST7MC2

MOTOR CONTROLLER (Cont’d)

9.6.6.9 Sampling block

cycle can be set in the 12-bit PWM generator com-

pare register in voltage mode.

For a full digital solution, the phase comparator

output sampling frequency is the frequency of the

PWM signal applied to the switches and the sam-

pling for the Z event detection in sensorless mode

is done at the end of the off time of this PWM sig-

nal to avoid to have to re-create a virtual ground

because when the PWM signal is off, the star point

is at ground due to the free-wheeling diode. That’s

why, the sampling for Z event detection is done by

default during the OFF-state of the PWM signal

and therefore at the PWM frequency.

Specific applications can require sampling for the

Z event detection only during the ON time of the

PWM signal. This can happen when the PWM sig-

nal is applied only on the low side switches for Z

event detection. In this case, during the OFF time

of the PWM signal, the phase voltage is tied to the

application voltage V and no back-EMF signal can

be seen. During the ON time of the PWM signal,

the phase voltage can be compared to the neutral

point voltage and the Z event can be detected.

Therefore, it is possible to add a programmable

delay before sampling (which is normally done

when the PWM signal is switched ON) to perform

the sampling during the ON time of the PWM sig-

nal. This delay is set with the DS [3:0] bits in the

MCONF register.

In current mode, this PWM signal is generated by

a combination of the output of the measurement

window generator (SA[3:0] bits), the output of the

current comparator and a minimum OFF time set

by the OT[3:0] bits for system stabilisation.

In voltage mode, this PWM signal is generated by

the 12-bit PWM generator signal in the compare U

register with still a minimum OFF time required if

the sampling is done at the end of the OFF time of

the PWM signal for system stabilisation. The PWM

signal is put OFF as soon as the current feedback

reaches the current input limitation. This can add

an OFF time to the one programmed with the 12-

bit Timer.

Table 33. Delay length before sampling

Delay added to

DS3

DS2

DS1

DS0

sample at Ton

No delay added.

Sample during

Toff

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2.5 µs

5 µs

For D event detection in sensorless mode, no spe-

cific PWM configuration is needed and the sam-

pling frequency (f

independent from the PWM signal.

see Table 83) is completely

SCF,

7.5 µs

10 µs

In sensor mode, the D event detection is not need-

ed as the MCIA, MCIB and MCIC pins are the dig-

ital signals coming from the hall sensors so no

specific PWM configuration is needed and the

sampling for the Z detection event is done at

12.5 µs

15 µs

17.5 µs

20 µs

f

, completely independent from the PWM sig-

22.5 µs

25 µs

SCF

nal.

In sensorless mode, if a virtual ground is created

by the addition of an external circuit, sampling for

the Z event detection can be completely independ-

ent from the PWM signal applied to the switches.

Setting the SPLG bit in the MCRC register allows a

27.5 µs

30 µs

32.5 µs

35 µs

37.5 µs

sampling frequency of f

for Z event detection

SCF

Note: Times are indicated for 4 MHz f

independent from the PWM signal after getting the

D (end of demagnetisation) event. This means that

the sampling order is given either during the ON

time or the OFF time of the PWM signal. As soon

as the SPLG bit is set in the MCRC register, the

minimum OFF time needed for the PWM signal in

current mode is set to 0µs and a true 100% duty

PERIPH

As soon as a delay is set in the DS[3:0] bits, the

minimum OFF time for the PWM signal is no long-

er required and it is automatically set to 0µs in cur-

rent mode in the internal sampling clock and a true

100% duty cycle can be set in the 12-bit PWM

generator compare U register if needed.

155/294

1

ST7MC1/ST7MC2

MOTOR CONTROLLER (Cont’d)

Depending on the frequency and the duty cycle of

the PWM signal, the delay inserted before sam-

pling could cause it sample the signal OFF time in-

stead of the ON time. In this case an interrupt can

be generated and the sample will not be taken into

acount. When a sample occurs outside the PWM

signal ON time, the SOI bit in the MCONF register

is set and an interrupt request is generated if the

SOM bit is set in the MCONF register. This inter-

rupt is enabled only if a delay value has been set in

the DS[3:0] bits. In this case, the sampling is done

at the PWM frequency but only during the ON time

of the PWM signal. Figure 82 and Figure 83 shows

in detail the generation of the sampling order when

the delay is added.

For complete flexibility, the possibility of sampling

at 1 MHz frequency during the ON time of the

PWM signal is also available when the SPLG bit is

set as if there is a delay value in the DS[3:0] bits.

This means that when the sampling is to be per-

formed, after the delay a 1 MHz sampling window

is opened until the next OFF time of the PWM sig-

nal. The Sampling Out interrupt will be generated if

the delay added is longer than the duty cycle of the

PWM signal. As the SPLG bit is set and a value

has been put in the DS[3:0] bits, no minimum off

time is required for the PWM signal and it is auto-

matically set to 0µs in current mode. A true 100%

duty cycle can be also set in the 12-bit Timer in

voltage mode. Figure 84 shows in detail the sam-

pling at 1 MHz during ON time.

Figure 82. Adding the Delay to sample during ON time for Z detection

New

sample

T

Sampling

DS[3:0]

PWM signal

PWM OFF

time

Current

sample

Figure 83. Sampling Out interrupt generation

T

Sampling

To interrupt generator

SO

DS[3:0]

PWM signal

PWM OFF

time

New sample during next

OFF time. Sample not taken into

account. SO interrupt generated.

SO

Current

sample

156/294

1

ST7MC1/ST7MC2

MOTOR CONTROLLER (Cont’d)

In conclusion, there are 4 sampling types that are

available for Z event detection in sensorless

mode.

always done at the selected f

frequency (see

SCF

Table 83), independently of the PWM signal (ei-

ther during ON or OFF time). Table 34 explains the

different sampling types in sensorless and in sen-

sor mode.

1. Sampling at the end of the OFF time of the

PWM signal at the PWM frequency

Note 2: When the MOE bit in the MCRA register is

reset (MCOx outputs in reset state), and the SR bit

in the MCRA register is reset (sensorless mode)

and the SPLG bit in the MCRC register is reset

(sampling at PWM frequency) then, depending on

the state of the ZSV bit in the MSCR register, Z

event sampling can run or be stopped (and D

event is sampled).

2. Sampling, at a programmable frequency inde-

pendent of the PWM state (either during ON

time or OFF time of the signal). Sampling is

done at f

, see Table 83.

SCF

3. Sampling during the ON time of the PWM sig-

nal by adding a delay at PWM frequency

4. Sampling, at a programmable frequency during

the ON time (addition of a programmable delay)

Note 3: When BEMF sampling is performed at the

end of the PWM signal off-time, the inputs in OFF-

state are grounded or put in HiZ as selected by the

DISS bit in the MSCR register.

of the PWM signal. Sampling is done at f

see Table 83.

,

SCF

Note 1: The sampling type is applied only for Z

event detection after the D event has occured.

Whatever the sampling type for Z event detection,

the sampling of the signal for D event detection is

Note 4: The ZEF[3:0] event counter in the MZFR

register is active in all configurations.

Figure 84. Sampling during ON time at f

SCF

f

SCF

during

ON time

DS[3:0]

PWM signal

PWM OFF

state

Current

sample

157/294

1

ST7MC1/ST7MC2

MOTOR CONTROLLER (Cont’d)

9.6.6.10 Commutation Noise Filter

means that, with sampling at 1MHz (1µs), due to

this filter, 1 sample are ignored directly after the

commutation.

For D event detection and for Z event detection

(when SPLG bit is set while DS[3:0] bits are reset),

sampling is done at f

either during the PWM

This filter is active all the time for the D event and

it is active for the Z event when the SPLG bit is set

and DS[3:0] bits are cleared (meaning that the Z

event is sampled at high frequency either during

the PWM ON or OFF time).

SCF

ON or OFF time (“Sampling block” on page 155).

To avoid any erroneous detection due to PWM

commutation noise, an hardware filter of 1µs (for

f

= 4Mhz) when PWM is put ON and when

PERIPH

PWM is put OFF has been implemented. This

Table 34. Sensor/sensorless mode and D & Z event selection

Sampling

DS[3:0]

SR SPLG

bit bit

Event detection behaviour for

Window and

Event Filters

Behaviour of the

output PWM

Mode OS[2:0]

bits use

sampling clock

Z event

bits

detection

At the end of

the off time of

the PWM sig-

nal

“Before D” behaviour,

“between D and Z” be-

haviour and “after Z”

behaviour

D:

f

SCF

Sensors

not used

0

1

0

1

0

1

x

000

Enabled Z: SA&OT config.

PWM frequency

Either during

off time or ON

time of the

“Before D” behaviour,

“between D and Z” be-

haviour and “after Z”

behaviour

D:

Z:

f

Sensors

not used

SCF

Enabled

f

SCF

PWM signal

“Before D” behaviour,

“between D and Z” be-

haviour and “after Z”

behaviour

D:

f

SCF

Not

equal to

000

During ON

time of the

PWM signal

Sensors

not used

Enabled Z: SA&OT config.

PWM frequency

“Before D” behaviour,

“between D and Z” be-

haviour and “after Z”

behaviour

Not

equal to

000

During ON

time of the

PWM signal

D:

Z:

f

Sensors

not used

SCF

Enabled

f

SCF

Either during

Position

Sensors

used

OS1 dis-

abled

OFF time or No filter in Sensor “Before Z” behaviour

ON time of the

PWM signal

xxx

Z:

f

SCF

mode

and “after Z” behaviour

Note: For f

selection, see Table 83

SCF

158/294

1

ST7MC1/ST7MC2

MOTOR CONTROLLER (Cont’d)

Figure 85. Functional Diagram of Z Detection after D Event

D

or D

H

S

Begin

Z Window Filter turned on

ZWF[3:0] bits in MZFR register

Switch Sampling Clock[D] -> Sampling Clock[Z]

No

Side change on

Output PWM

?

Yes

Change the side according to OS[2:0]

Wait for next sampling clock edge

No

Read enable

by REO

?

Yes

No

Filter

off

?

Yes

Read enabled

End

159/294

1

ST7MC1/ST7MC2

MOTOR CONTROLLER (Cont’d)

9.6.6.11 Speed Sensor Mode

tive; set-up is done with the TES[1:0] bits (keeping

in mind that TES[1:0] = 00 configuration is re-

served for Position Sensor / Sensorless Modes).

This mode is entered whenever the Tacho Edge

Selection bits in the MPAR register are not both re-

set (TES[1:0] = 10, 01, 11). The corresponding

block diagram is shown in Figure 86.

Having only one edge selected eliminates any in-

coming signal dissymmetry, which may due to

pole-to-pole magnet dissymmetry or from a com-

parator threshold with low level signals.

Either Incremental Encoder or Tachogenerator-

type speed sensor can be selected with the IS[1:0]

bits in the MPHST register.

Figure 87 presents the signals generated internal-

ly with different tacho input and TES bit settings.

9.6.6.12 Tachogenerator Mode (IS[1:0] = 00, 01

or 10)

Note on Hall Sensors: This configuration is also

suitable for motors using 3 hall sensors for position

detection and not driven in six-step mode (refer to

“Speed Measurement Mode” on page 176).

Any of the MCIx input pins can be used as a tacho-

generator input, with a digital signal (externally

amplified for instance); the two remaining pins can

be used as standard I/O ports.

Note on initializing the Input Stage: As the

IS[1:0] bits in the MPHST register are preload bits

(new values taken into account at C event), the in-

itialization value of the IS[1:0] bits has to be en-

tered in Direct Access mode. This is done by set-

ting the DAC bit in the MCRA register during the

speed sensor input initialization routine.

A digital multiplexer connects the chosen MCIx in-

put to an edge detection block. Input selection is

done with the IS[1:0] bits in the MPHST register.

An edge selection block is used to select one of

three ways to trigger capture events: rising edge,

falling edge or both rising and falling edge sensi-

Figure 86. Input Stage in Speed Sensor Mode (TES[1:0] bits = 01, 10, 11)

Event Detection

Input Comparator Block

Input Block

Encoder

Clock

In1 Incremental

Encoder

Clk

D

Direction

In2

interface

MPHST Register

IS[1:0]

EDIR bit

MCRC Register

Input Sel

n

MCIA

MCIB

MCIC

MPAR Register

TES[1:0]

§

Tacho or

00

01

10

Encoder

Tacho

Capture

§

Tacho or

or

Encoder

§

Tacho or

Free I/O

§

= According to IS[1:0] bits setting

160/294

1

ST7MC1/ST7MC2

MOTOR CONTROLLER (Cont’d)

9.6.6.13 Encoder Mode (IS[1:0] = 11)

The Incremental Encoder Interface block aims at

extracting these signals. As input logic is both ris-

ing and falling edge sensitive (independently from

TES[1:0] bits setting), resulting clock frequency is

four times the one of the input signals, thus in-

creasing resolution for measurements.

Figure 88 shows the signals delivered by a stand-

ard digital incremental encoder and associated in-

formation:

– Two 90° phased square signals with variable

frequency proportional to the speed; they

must be connected to MCIA and MCIB input

pins,

– Clock derived from incoming signal edges,

– Direction information determined by the rela-

tive phase shift of input signals ( + or -90°).

It may be noticed that Direction bit (EDIR bit in

MCRC register) is read only and that it does’nt af-

fect counting direction of clocked timer (cf Section

). As a result, one cannot extract position informa-

tion from encoder inputs during speed reversal.

Figure 87. Tacho Capture events configured by the TES[1:0] bits

Tacho

input

TES[1:0]=11

TES[1:0]=01

TES[1:0]=10

Tacho

Capture

Figure 88. Incremental Encoder output signals and derived information

MCIA

Encoder

inputs

MCIB

Encoder

Clock

Direction

(EDIR bit)

Sampling of MCIA to determine direction

161/294

1

ST7MC1/ST7MC2

MOTOR CONTROLLER (Cont’d)

Note

given by the sampling of MCIA with MCIB falling

edges.

If only one encoder output is available, it may be

input either on MCIA or MCIB and an encoder

clock signal will still be generated (in this case the

frequency will be 50% less than with two inputs.

9.6.6.14 Summary

Input Detection block set-up for the different avail-

able modes is summarized in the Table 35.

The state of EDIR bit will depend on signals

present on MCIA and MCIB pins, the result will be

Table 35. Input Detection Block set-up

TES[1:0] bits

SR

bit

IS[1:0] bits

Input Detection

Block Mode

Sensor Type

Edge sensitivity

(Tacho Edge

Selection)

(Input Selection)

00

01

10

Position Sensor

Hall, Optical,... Both rising and falling edges

1

0

00

01

10

Sensorless

N/A

Any configuration dif-

ferent from 00:

Incremental

Encoder

Both rising and falling edges

(imposed)

11

01 10 11

00

01

10

Rising edge

Falling edge

01

Speed Sensor

x

00

01

10

Tachogenerator,

Hall, Optical...

10

11

00

01

10

Both rising and falling edges

162/294

1

ST7MC1/ST7MC2

MOTOR CONTROLLER (Cont’d)

Note on using the 3 MCIx pins as standard

I/Os: When none of the MCIx pins are needed in

the application (for instance when driving an in-

duction motor in open loop), they can be used as

standard I/O ports, by configuring the Motor Con-

troller as follows: PCN=1, TES≠0 and IS=11. This

disables the MCIx alternate functions and switch-

es off the phase comparator. The state of the MCIx

pins is summarized in Table 36.

Table 36. MCIx pin configuration summary

Input

PCN TES SR IS[1:0]

MCIA

MCIB

MCIC

Detection

Comments

Block Mode

00 Analog Input Hi-Z or GND Hi-Z or GND

All MCIx pins are reserved

for the MTC peripheral

01

10

11

00

Hi-Z or GND Analog Input Hi-Z or GND

Hi-Z or GND Hi-Z or GND Analog input

Sensorless

NA

0

NA

00

0

Digital Input Standard I/O Standard I/O

Position

Sensor

01 Standard I/O Digital Input Standard I/O

10 Standard I/O Standard I/O Digital Input

From 1 to 3 MCIx pins reserved

depending on sensor

1

x

11

xx

NA

≠0

00 Analog Input Standard I/O Standard I/O

01 Standard I/O Analog Input Standard I/O

Phase comparator is ON.

The IS[1:0] bits must not be modified

to avoid spurious event detection

in Motor Controller

NA

10 Standard I/O Standard I/O Analog Input

00

x

All MCIx pins are standard I/Os.

Recommended configuration:

phase comparator OFF

11 Standard I/O Standard I/O Standard I/O

1

00

Digital Input Standard I/O Standard I/O

Speed Sensor

Tachogenerator

01 Standard I/O Digital Input Standard I/O

10 Standard I/O Standard I/O Digital Input

≠00

Speed Sensor

Encoder

11

Digital Input Digital Input Standard I/O

*When PCN=0, TES=0 SR=0, inputs in OFF-state are put in HiZ or grounded depending on the value of

the DISS bit in the MSCR register.

163/294

1

ST7MC1/ST7MC2

MOTOR CONTROLLER (Cont’d)

9.6.7 Delay Manager

Figure 89. Overview of MTIM Timer in Switched and Autoswitched Mode

MCRA register

T

ratio

SWA bit

ck

Z

1

0

§

clr

8-bit Up Counter MTIM

8

C

Z

D

H

§

MDREG [D ]

MZREG [Z ]

n

Z

/ Z

H

S

Compare

MCRB register

SDM* bit

MCRC register

SZ bit

Filter /C

MDFR register

DWF[3:0]

Filter /D

MZFR register

ZWF[3:0]

D

Z

S

§

MZPRV [Z

]

n-1

To interrupt generator

C

H,S

D

S,H

§

MCOMP [C

]

n+1

Z

H,S

Compare

MCRC register

SC bit

§

C

/ C

S

= Register updated on R event

H

This part of the MTC contains all the time-related

functions, its architecture is based on an 8-bit shift

left/shift right timer shown in Figure 89. The MTIM

timer includes:

The MTIM timer module can work in two main

modes when driving synchronous motors in six-

steps mode.

In switched mode the user must process the step

duration and commutation time by software.

– An auto-updated prescaler

– A capture/compare register for simulated de-

magnetization simulation (MDREG)

In autoswitched mode the commutation action is

performed automatically depending on the rotor

position information and register contents. This is

– Two cascaded capture and one compare regis-

ters (MZREG and MZPRV) for storing the times

between two consecutive BEMF zero crossings

called the hardware commutation event C . When

H

enabled by the SC bit in the MCRC register, com-

mutation can also be simulated by writing a value

directly in the MCOMP register that is compared

with the MTIM value. This is called simulated com-

(Z events) and for zero-crossing event simula-

H

tion (Z )

S

– An 8x8 bit multiplier for auto computing the next

commutation time

mutation C (See “Built-in Checks and Controls for

S

simulated events” on page 171.).

– One compare register for phase commutation

generation (MCOMP)

Both in switched mode and autoswitched mode , if

the SC bit in the MCRC register is set (software

commutation enabled), no comparison between

164/294

1

ST7MC1/ST7MC2

MOTOR CONTROLLER (Cont’d)

the MCOMP and MTIM register is enabled before

a write access in the MCOMP register. This means

that if the SC bit is set and no write access is done

MCOMP. When the MTIM timer reaches this value

a commutation occurs (C event) and the MTIM

timer is reset.

after in the MCOMP register, no C commutation

event will occur.

S

At this time all registers with a preload function are

loaded (registers marked with (*) in Section

9.6.13). The CI bit of MISR is set and if the CIM bit

in the MISR register is set an interrupt is generat-

ed.

In Speed Measurement mode, when using encod-

er or tachogenerator speed sensors (i.e. both

TES[1:0] bits in the MPAR register are not reset

The MTIM timer prescaler (Step ratio bits ST[3:0]

in the MPRSR register) is user programmable. Ac-

cess to this register is not allowed while the MTIM

timer is running (access is possible only before the

starting the timer by means of the CKE bit) but the

prescaler contents can be incremented/decre-

mented at the next commutation event by setting

the RMI (decrement) or RPI (increment) bits in the

MISR register. When this method is used, at the

next commutation event the prescaler value will be

updated but also all the MTIM timer-related regis-

ters will be shifted in the appropriate direction to

keep their value. After it has been taken into ac-

count, (at commutation) the RPI or RMI bit is reset

by hardware. See Table 38.

Only one update per step is allowed, so if both RPI

and RMI bits are set together by software, this

does not affect the MISR register: the write access

to these two bits together is not taken into account

and the previous state is kept. This means that if

either RPI or RMI bit was set before the write ac-

cess of both bits at the same time, this bit (RPI or

RMI) is kept at 1. If none of them was set before

the simultaneous write access, none of them will

be set after the write access.

and the input detection block is set-up to process

sensor signals), motor speed can be measured

but it is not possible drive a motor in six-step

mode, either sensored or sensorless.

Speed Measurement mode is useful for motors

supplied with 3-phase sinewave-modulated PWM

signals:

– AC induction motors,

– Permanent Magnet AC (PMAC) motors (al-

though it needs three position sensors, they

can be handled just like tachogenerator sig-

nals).

This mode uses only part of the Delay Manager’s

resources. For more details refer to “Speed Meas-

urement Mode” on page 176.

Table 37. Switched and Autoswitched modes

SWA

bit

MCOMP User

access

Commutation Type

0

1

Switched mode

Read/Write

Autoswitched mode

9.6.7.1 Switched Mode

In switched mode, BEMF and demagnetization de-

tection are already possible in order to pass in au-

toswitched mode as soon as possible but Z and D

events do not affect the timer contents.

In this mode, if an MTIM overflow occurs, it re-

starts counting from 0x00h and the OI overflow

flag in the MCRC register is set if the TES[1:0] bits

= 00.

This feature allows the motor to be run step-by-

step. This is useful when the rotor speed is still too

low to generate a BEMF. It can also run other

kinds of motor without BEMF generation such as

induction motors or switch reluctance motors. This

mode can also be used for autoswitching with all

computation for the next commutation time done

by software (hardware multiplier not used) and us-

ing the powerful interrupt set of the peripheral.

Caution: In this mode, MCOMP must never be

written to 0.

In this mode, the step time is directly written by

software in the commutation compare register

Table 38. Step Update

CKE SWA Clock

Ratio Increment

(Slow Down)

Ratio Decrement

(Speed-Up)

Mode

x

TES[1:0]

Read

bit

State

xx

00

0

x

Disabled

Write the ST[3:0] value directly in the MPRSR register

Set RPI bit in the MISR reg- Set RMI bit in the MISR reg-

ister till next commutation ister till next commutation

Switched

1

0

1

Enabled

Always

possible

Autoswitched

Speed

Automatically updated according to MZREG value

01 10 11

1

x

Enabled

measure

165/294

1

ST7MC1/ST7MC2

MOTOR CONTROLLER (Cont’d)

Figure 90. Step Ratio Functional Diagram

f

PERIPH

R+

MTIM Timer = 100h?

+1

1 / 2

4

MPRSR Register

ST[3:0] Bits

1 / 2Ratio

Tratio

ck

-1

Zn < 55h?

R-

2 MHz - 62.5 Hz

MTIM Timer control over T

and register operation

ratio

MTIM Timer Overflow

Z Capture with MTIM Timer Underflow (Zn < 55h)

Begin

No

Ratio < Fh?

Ratio > 0?

Yes

Ratio = Ratio + 1

Ratio = Ratio - 1

MZREG = MZREG x 2

MZPRV = MZPRV x 2

MDREG = MDREG x 2

Counter = Counter x 2

MZREG = MZREG / 2

MZPRV = MZPRV/2

MDREG = MDREG/2

MCOMP = MCOMP/2**

Counter = Counter/2

Compute MCOMP

End

Slow-down control

Speed-up control

** Only in Auto-switched mode (SWA=1 in MCRA register)

166/294

1

ST7MC1/ST7MC2

MOTOR CONTROLLER (Cont’d)

9.6.7.2 Autoswitched Mode

cur because no comparison will be done between

MCOMP and MTIM. Therefore, it is recommended

in autoswitched mode, when using software com-

mutation feature (SC bit is set) and for a normal

event sequence, the corresponding value to be

put in MCOMP has to be written during the Z inter-

rupt routine (because MTIM has just been reset),

so that there is no spurious comparison. If the SC

bit is set during a Z event interrupt, then , the result

of the 8*8 bits hardware multiplication can be over-

written by software in the MCOMP register. When

simulated commutation mode is enabled, the

event sequence is no longer respected, meaning

that the peripheral will accept consecutive commu-

tation events and not necessarily wait for a D

In this mode, using the hardware commutation

event C (SC bit reset in MCRC register), the

H

MCOMP register content is automatically comput-

ed in real time as described below and in Figure

91.

The C (either C or C ) event has no effect on the

S

H

contents of the MTIM timer.

When a Z event occurs the MTIM timer value is

H

captured in the MZREG register, the previous cap-

tured value is shifted into the MZPRV register and

the MTIM timer is reset. See Figure 71.

When a Z event occurs, the value written in the

S

MZREG register is shifted into the MZPRV register

event after a C event. In this case the MCOMP

s

and the MTIM timer is reset.

register can be written immediately after the previ-

ous C event, in the C interrupt service routine for

example.

One of these two registers, (when the SC bit = 0 in

the MCRC register and depending on the DCB bit

in the MCRA register), is multiplied with the con-

tents of the MWGHT register and divided by 256.

The result is loaded in the MCOMP compare reg-

ister, which automatically triggers the next hard-

Figure 91. C Processor Block

H

§

MZREG [Z ]

n

ware commutation (C event).

H

Note: The result of the 8*8 bit multiplication, once

written in the MCOMP register is compared with

the current MTIM value to check that the MCOMP

value is not already less than the MTIM value due

Z /Z

H

S

§

MZPRV [Z

]

n-1

to the multiplication time. If MCOMP<=MTIM, a C

event is generated immediately and the MCOMP

value is overwritten by the MTIM value.

H

MCRA Register

DCB bit

n-1

n

Table 39. Multiplier Result

MWGHT [a

]

n+1

DCB bit

Commutation Delay

8

0

1

MCOMP = MWGHT x MZPRV / 256

MCOMP = MWGHT x MZREG / 256

MCRA Register

MCRC register

A x B / 256

After each shift operation the multiply is recomput-

ed for greater precision.

SWA bit =1 &

SC bit =0

Using either the MZREG or MZPRV register de-

pends on the motor symmetry and type.

8

§

MCOMP [C

]

n+1

The MWGHT register gives directly the phase shift

between the motor driven voltage and the BEMF.

This parameter generally depends on the motor

and on the speed.

§

= Register updated on R event

Setting the SC bit in the MCRC register enables

Note 1: An overflow of the MTIM timer generates

an RPI interrupt if the RIM bit is set.

Note 2: When simulated commutation mode is en-

abled, the D and Z event are not ignored by the

peripheral, this means that if a Z event happens,

the MTIM 8 bit internal counter will be reset.

the simulated commutation event (C ) generation.

S

This means that a write access is possible to the

MCOMP register and the MTIM value will be com-

pared directly with the value written by software in

the MCOMP register to generate the C event.

S

The comparison is enabled as soon as a write ac-

cess is done to the MCOMP register. This means

that if the SC bit is set and no write access is done

to the MCOMP register, the C event will never oc-

Caution: MCOMP must never be written to 0 for a

C event generation.

S

167/294

1

ST7MC1/ST7MC2

MOTOR CONTROLLER (Cont’d)

Auto-updated Step Ratio Register:

bits = 00, the OI bit in the MCRC register is set at

each overflow (it has to be reset by software).

The RPI bit is no longer set. The PWM is still gen-

erated and the D and Z detection circuitry still

work, enabling the capture of the maximum timer

value.

a) In switched mode: the MTIM timer is driven by

software only and any prescaler change has to be

done by software (see page 165 for more details).

b) In autoswitched mode: an auto-updated pres-

caler always configures the MTIM timer for best

accuracy. Figure 90 shows the process of updat-

ing the Step Ratio bits:

The automatically updated registers are: MTIM,

MZREG, MZPRV, MCOMP and MDREG. Access

to these registers is summarized in Table 41.

– When the MTIM timer value reaches FFh, the

prescaler is automatically incremented in order

to slow down the MTIM timer and avoid an over-

flow. To keep consistent values, the MTIM regis-

ter and all the relevant registers are shifted right

(divided by two). The RPI bit in the MISR register

is set and an interrupt is generated (if RIM is set).

The timer restarts counting from its median value

0x80h and if the TES[1:0] bits = 00, the OI bit in

the MCRC register is set.

9.6.7.3 Debug Option

In both Switched Mode and Autoswitched Mode,

setting the bit DG in MPWME register enables the

Debug Option. This option consists of outputting

the C, D and Z signals in real time on pins MCZEM

and MCDEM. This is very useful during the debug

phase of the application. Figure 92 shows the sig-

nals output on pins MCDEM and MCZEM with the

debug option.

– When a Z-event occurs, if the MTIM timer value

is below 55h, the prescaler is automatically dec-

remented in order to speed up the MTIM timer

and keep precision better than 1.2%. The MTIM

register and all the relevant registers are shifted

left (multiplied by two). The RMI bit in the MISR

register is set and an interrupt is generated if RIM

is set.

Note 1: When the delay coefficient equals 0/256

(C event immediately after Z event), a glitch ap-

pears on MCZEM pin to be able to see the event

even in this case.

This option is also available in Speed measure-

ment mode with different signal outputs (see Fig-

ure 92):

– MCDEM toggles when a capture event is gener-

ated,

– If the prescaler contents reach the value 0, it can

no longer be automatically decremented, the

MTC continues working with the same prescaler

value, i.e. with a lower accuracy. No RMI in-

terrrupt can be generated.

– MCZEM toggles every time a U event is gener-

ated.

These signals are only available if the TES[1:0]

bits = 10, 01 or 11.

– If the prescaler contents reach the value 15, it

can no longer be automatically incremented.

When the timer reaches the value FFh, the pres-

caler and all the relevant registers remain un-

changed and no interrupt is generated, the timer

restarts counting from 0x00h and if the TES[1:0]

Note 2: In sensor mode, the MCDEM output pin

toggles at each C event. The MCZEM pin outputs

the Z event.

168/294

1

ST7MC1/ST7MC2

MOTOR CONTROLLER (Cont’d)

Figure 92. Output on pins MCDEM and MCZEM with debug option (DG bit=1)

MCDEM

MCZEM

C

Z

D

Z

D

Debug outputs in Sensorless mode

MCDEM

MCZEM

C

Z

C

Z

C

Z

C

Z

C

Z

Debug outputs in Sensor mode

MCDEM

C

MCZEM

U events

Debug outputs in Speed Measurement mode (TES[1:0] bits equal to 00, 01, 10).

169/294

1

ST7MC1/ST7MC2

MOTOR CONTROLLER (Cont’d)

Note on using the auto-updated MTIM timer:

The auto-updated MTIM timer works accurately

within its operating range but some care has to be

taken when processing timer-dependent data such

as the step duration for regulation or demagnetiza-

tion.

These configuration bits are:

CPB, HDM, SDM and OS2 in the MCRB register

and IS[1:0], OO[5:0] in the MPHST register.

Note on initializing the MTC: As shown in Table 41

all the MTIM timer registers are in read-write mode

until the MTC clock is enabled (with the CKE bit).

This allows the timer, prescaler and compare reg-

isters to be properly initialized for start-up.

For example if an overflow occurs when calculat-

ing

a

simulated end of demagnetization

(MCOMP+demagnetisation_time>FFh), the value

that is stored in MDREG will be:

80h+(MCOMP+demagnetization_time-FFh)/2.

In sensorless mode, the motor has to be started in

switched mode until a BEMF voltage is present on

the inputs. This means the prescaler ST[3:0] bits

and MCOMP register have to be modified by soft-

ware. When running the ST[3:0] bits can only be

incremented / decremented, so the initial value is

very important.

Note on commutation interrupts: It is good prac-

tice to modify the configuration for the next step as

soon as possible, i.e within the commutation inter-

rupt routine.

All registers that need to be changed at each step

have a preload register that enables the modifica-

tions for a complete new configuration to be per-

formed at the same time (at C event in normal

mode or when writing the MPHST register in direct

access mode).

When starting directly in autoswitched mode (in

sensor mode for example), write an appropriate

value in the MZREG and MZPRV register to per-

form a step calculation as soon as the clock is en-

abled.

170/294

1

ST7MC1/ST7MC2

MOTOR CONTROLLER (Cont’d)

9.6.7.4 Built-in Checks and Controls for

simulated events

the register has to be greater than the current val-

ue of the MTIM timer when writing in the registers.

If the value written in the registers (MDREG,

MZREG or MCOMP) is already less than the cur-

rent value of MTIM, the simulated event will never

be generated and the system will be stopped.

As described in Figure 89. on page 164, MZREG,

MDREG and MCOMP registers are capture/com-

pare registers. The Compare registers are write

accessible and can be used to generate simulated

events. The value of the MTIM timer is compared

with the value written in the registers and when the

MTIM value reaches the corresponding register

value, the simulated event is generated. Simulated

event generation is enabled when the correspond-

ing bits are set:

For this reason, built-in checks and controls have

been implemented in the MTIM timer.

If the value written in one of those registers in sim-

ulated event generation mode is less than or equal

to the current value of the timer when it is com-

pared, the simulated event is generated immedi-

ately and the value of the MTIM timer at the time

the simulated event occurs overwrites the value in

the registers. Like that the value in the register re-

ally corresponds to the simulated event generation

and can be re-used to generate the next simulated

event.

– In the MCRB register for simulated demagneti-

sation

– SDM for simulated demagnetisation

– In the MCRC register for simulated zero-crossing

and commutation.

– SC for simulated commutation

– SZ for simulated zero-crossing event.

To avoid a system stop, special attention is need-

ed when writing in the register to generate the cor-

responding simulated event. The value written in

So, the value written in the registers able to gener-

ate simulated events is checked by hardware and

compare to the current MTIM value to verify that it

is greater.

Figure 93. Simulated demagnetisation / zero-crossing event generation (SC=0)

After C interrupt

After D interrupt

MDREG value checked

MZREG value checked

if MDREG<=MTIM

if MZREG<=MTIM

Immediate Z generation

S

Immediate D generation

S

Z

H

Z

S

Z

S

D

S

D

H

D

S

C

H

C

H

During C interrupt

Z

Simulated zero-crossing

S

D

Simulated demagnetisation

Hardware zero-crossing

Hardware commutation

Simulated or Hardware D/Z events

Value written in MDREG/MZREG if

simulated event generation

S

H

Z

C

t

171/294

1

ST7MC1/ST7MC2

MOTOR CONTROLLER (Cont’d)

When using hardware commutation C , the se-

Z event occurs, the MTIM timer is reset. In Simu-

lated Commutation mode, the sequence D -> Z is

expected, and this order must be repected.

H

quence of events needed is C then D and finally

H

Z events and the value written in the registers are

checked at different times.

As the sequence of events may not be the same

when using simulated commutation, as soon as

the SC bit is set, the capture/compare feature and

protection on MCOMP register is reestablished

only after a write to the MCOMP register. This

means that as soon as the SC bit is set, if no write

access is done to the MCOMP register, no com-

mutation event will be generated, whatever the

value of MCOMP compared to MTIM at the time

SC is set. This does not depend on the running

mode: switched or autoswitched mode (SWA bit).

If software commutation event is used with a nor-

mal sequence of events C-->D-->Z, it is recom-

mended to write the MCOMP register during the Z

interrupt routine to avoid any spurious comparison

If SDM bit is set, meaning simulated demagnetisa-

tion, a value must be written in the MDREG regis-

ter to generate the simulated demagnetisation.

This value must be written after the C (either C or

s

C ) event preceding the simulated demagnetisa-

H

tion.

If SZ bit is set, meaning simulated zero-crossing

event, a value must be written in the MZREG reg-

ister to generate the simulated zero-crossing. This

value must be written after the D event (D or D )

H

S

preceding the simulated zero-crossing.

When using simulated commutation (C ), the re-

S

sult of the 8*8 hardware multiplication of the delay

manager is not taken in account and must be over-

written if the SC bit has been set in a Z event inter-

rupt and the sequence of events is broken mean-

ing that several consecutive simulated commuta-

tions can be implemented.

as several consecutive C events can be generat-

s

ed.

Note that two different simulated events can be

used in the same step (like D followed by Z ).

S

Note also that for more precision, it is recommend-

ed to use the value captured from the preceding

hardware event to compute the value used to gen-

erate simulated events.

As soon as the SC bit is set in the MCRC register,

the system won’t necessarily expect a D event af-

ter a C event. This can be used for an application

in sensor mode with only one Hall Effect sensor for

example.

Figure 93, Figure 94 and Figure 95 shows details

of simulated event generation.

Be careful that the D and Z events are not ignored

by the peripheral, this means that for example if a

172/294

1

ST7MC1/ST7MC2

MOTOR CONTROLLER (Cont’d)

Figure 94. Simulated commutation event generation with only 1 Hall effect sensor (SC bit =1)

After C interrupt

C interrupt

MCOMP is written for C_sevent

SC reset in MCRB

if MCOMP<=MTIM

Immediate C_Sgeneration

Next C event = C_Hwith 8*8 bit multiplication

Z

D

C_S

C_H

C interrupt

SC set in MCRC

Z zero-crossing event

D Demagnetisation event

C

Hardware commutation

Simulated commutation

H

S

t

Note: If the SC bit is set during Z event interrupt,

then the 8*8 bit hardware multiplication result can

be overwritten in the MCOMP register. Otherwise,

when the SC bit is set, the result of the multiplica-

tion is not taken into account after a Z event.

Figure 95. Simulated commutation and Z event

SC bit is reset

the result of the

hardware multiplication is put

in MCOMP-->C and compared

H

SC bit is set during Z IT

SC bit is already set when Z IT

the hardware multiplication is taken

into account but the value in MCOMP

can be overwritten

occurs. The hardware multipli-

-cation is not taken into account

A value has to be written

in the MCOMP register

with MTIM once written

Z

D

C

H

C

s

C

s

MCOMP

register

Z zero-crossing event

D Demagnetisation event

C

Hardware commutation

Simulated commutation

H

S

t

173/294

1

ST7MC1/ST7MC2

MOTOR CONTROLLER (Cont’d)

The Figure 96 gives the step ratio register value

(left axis) and the number of BEMF sampling dur-

ing one electrical step with the corresponding ac-

curacy on the measure (right axis) as a function of

the mechanical frequency.

At f =4MHz, the range covered by the Step Ra-

cpu

tio mechanism goes from 2.39 to 235000 (pole

pair x rpm) with a minimum accuracy of 1.2% on

the step period.

To read the number of samples for Zn within one

step (right Y axis), select the mechanical frequen-

cy on the X axis and the sampling frequency curve

used for BEMF detection (PWM frequency or

measurement window frequency). For example,

for N.Frpm = 15,000 and a sampling frequency of

20kHz, there are approximately 10 samples in one

step and there is a 10% error rate on the measure-

ment.

For a given prescaler value (step ratio register) the

mechanical frequency can vary between two fixed

values shown on the graph as the segment ends.

In autoswitched mode, this register is automatical-

ly incremented/decremented when the step fre-

quency goes out of this segment.

Figure 96. Step Ratio Bits decoding and accuracy results and BEMF Sampling Rate

avg Zn ~ 55h ± 1.2%

avg Zn ~ 7Fh ± 0.6%

ST[3:0]

avg Zn ~ FFh ± 0.4%

Step Ratio (Decimal)

BEMF

samples

∆Zn/Zn

0

1

2

1

100%

3

Fn+1 = 2.Fn

4

200 Hz

avg Zn ~ 55h ± 1.2%

5

20 kHz

6

3.Fn+1 = 6.Fn

avg Zn ~ 7Fh ± 0.6%

avg Zn ~ FFh ± 0.4%

7

2

4

50%

3.Fn

8

Fn

9

10

11

12

13

14

15

10 10%

0%

N.Frpm

F

= 6.N.F

= N.F / 10

N.F = 10.F

step

rpm

F

: Electrical step frequency

step

N: Pole pair number

174/294

1

ST7MC1/ST7MC2

MOTOR CONTROLLER (Cont’d)

Table 40. Step Frequency/Period Range (4MHz)

Step Ratio Bits

Maximum

Minimum

Step Period

Maximum

Step Period

ST[3:0] in MPRSR

Register

Step Frequency

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

23.5 kHz

11.7 kHz

5.88 kHz

2.94 kHz

1.47 kHz

735 Hz

7.85 kHz

3.93 kHz

1.96 kHz

980 Hz

42.5

µ

s

127.5 µs

85

µ

255

510

µ

s

170

340

680

µ

s

1.02 ms

2.04 ms

4.08 ms

8.16 ms

16.32 ms

32.6 ms

65.2 ms

130 ms

261 ms

522 ms

1.04 s

490 Hz

245 Hz

1.36 ms

2.72 ms

5.44 ms

10.9 ms

21.8 ms

43.6 ms

87 ms

367 Hz

123 Hz

183 Hz

61.3 Hz

30.7 Hz

15.4 Hz

7.66 Hz

3.83 Hz

1.92 Hz

0.958 Hz

0.479 Hz

0.240 Hz

91.9 Hz

45.9 Hz

22.9 Hz

11.4 Hz

5.74 Hz

2.87 Hz

1.43 Hz

0.718 Hz

174 ms

349 ms

697 ms

1.40 s

2.08 s

4.17 s

Table 41. Modes of Accessing MTIM Timer-Related Registers

State of MCRA / MCRB / MPAR Register Bits

Access to MTIM Timer Related Registers

Read Only

Access

RST bit TES[1:0] SWA bit CKE bit

Mode

Read / Write Access

MTIM, MTIML, MZPRV, MZREG,

MCOMP, MDREG, ST[3:0]

0

xx

x

0

1

Configuration Mode

MCOMP, MDREG, MZREG, MZPRV

RMI bit of MISR:

0: No action

1: Decrement ST[3:0]

0

00

0

Switched Mode

MTIM, ST[3:0]

RPI bit of MISR:

0: No action

1: Increment ST[3:0]

MDREG, MCOMP, MZREG, MZPRV,

RMI, RPI bit of MISR:

Set by hardware, (increment ST[3:0])

Cleared by software

0

00

1

x

1

Autoswitched Mode MTIM, ST[3:0]

MDREG,MZREG, MZPRV,

01

10

11

MTIM, MTIML,

Speed Sensor Mode

ST[3:0]

RMI, RPI bit of MISR, :

Set by hardware, (increment or decre-

ment ST[3:0]), cleared by software.

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1

ST7MC1/ST7MC2

MOTOR CONTROLLER (Cont’d)

9.6.7.5 Speed Measurement Mode

counting the number of clock cycles issued by the

Incremental Encoder Interface (Encoder Clock)

during a fixed time window (refer to Figure 98).

Motor speed can be measured using two methods

depending on sensor type: period measurement or

pulse counting. Typical sensor handling is de-

scribed here.

The tachogenerator has a much lower ppr rate

than the encoder (typically factor 10). In this con-

text, it is more meaningful to measure the period

between Tacho Captures (i.e. relevant transitions

of the incoming signals). Accuracy is imposed by

the reference clock, i.e. the CPU clock (refer to

Figure 97).

Incremental encoders allows accurate speed

measurement by providing a large number of puls-

es per revolution (ppr) with ppr rates up to several

thousands; the higher the ppr rate, the higher the

resolution. The proposed method consists of

Figure 97. Tachogenerator period acquisition using MTIM timer

Decreasing Speed

Comparator

Output

Tacho

Capture

Compare

Value

S

MTIM Counter

Value

Interrupts

C

To interrupt generator

(Capture Event)

To interrupt generator

(Speed Error Event)

S

C

Figure 98. Encoder Clock frequency measure using MTIM timer

Decreasing Speed

Encoder

Clock

Capture

(triggered by software

or Real Time Clock)

MTIM Counter

Value

Interrupts

C

To interrupt generator

(Capture Event)

C

176/294

1

ST7MC1/ST7MC2

MOTOR CONTROLLER (Cont’d)

Hall sensors (or equivalent sensors providing posi-

tion information) are widely used for motor control.

There are two cases to be considered:

[MTIM:MTIML] is cleared. The counting direction

is not affected by the EDIR bit when using an en-

coder sensor.

– BLDC motor or six-step synchronous motor

drive; “Sensor Mode” is recommended in this

case, as most tasks are performed by hardware

in the Delay Manager

A 16-bit capture register is used to store the cap-

tured value of the extended MTIM counter: the

speed result will be either a period in clock cycles

or a number of encoder pulses. This 16-bit register

is mapped in the MZREG and MZPRV register ad-

dresses. To ensure that the read value is not cor-

rupted between the high and low byte accesses, a

read access to the MSB of this register (MZREG)

locks the LSB (ie MZPRV content is locked) until it

is read and any other capture event in between

these two accesses is discarded.

– BLAC, asynchronous or motors supplied with 3-

phase sinewave-modulated PWM signals in gen-

eral; in this case “Speed Sensor Mode” allows

high accuracy speed measurement (the Sensor

Mode of the Delay Manager being unsuitable for

sinewave generation). Position information is

handled by software to lock the statoric field to

the rotoric one for driving synchronous motors.

A compare unit allows a maximum value to be en-

tered for the tacho periods. If the 16-bit counter

[MTIM:MTIML] exceeds this value, a Speed Error

interrupt is generated. This may be used to warn

the user that the tachogenerator signal is lost

(wires disconnected, motor stalled,...). As 8-bit ac-

curacy is sufficient for this purpose, only the MS-

Byte of the counter (i.e. MTIM) is compared to 8-bit

compare register, mapped in the MDREG register

location. The LSByte is nevertheless compared

with a fixed FFh value. Available values for com-

parison are therefore FFFFh, FEFFh, FDFFh, ...,

01FFh, 00FFh.

Hall sensors are usually arranged in a 120° config-

uration. In that case they provide 3 ppr with both

rising and falling edge triggering; the tachogenera-

tor measurement method can therefore be ap-

plied. The main difference lies in the fact that one

must use the position information they provide.

This can be done using the three MCIx pins and

the analog multiplexer to know which of the 3 sen-

sors toggled; an interrupt is generated just after

the expected transition (refer to Figure 99).

As described in Figure 100, the MTIM Timer is re-

configured depending on the selected sensor. This

means that most of Delay Manager registers are

used for a different purpose, with modified func-

tionalities.

Note: This functionality is not useful when using

an encoder. With an encoder, user must monitor

the captured values by software during the period-

ic capture interrupts: for instance, when driving an

AC motor, if the values are too low compared to

the stator frequency, a software interrupt may be

triggered.

For greater precision, the MTIM Up-counter is ex-

tended to 16 bits using MTIM and an additional

MTIML register. On a capture event, the current

counter value is captured and the counter

Figure 99. Hall sensor period acquisition using MTIM timer

1 mechanical cycle

MCIA: Hall Sensor 1

MCIB: Hall Sensor 2

MCIC: Hall Sensor 3

Period measurements

1-2

2-3

3-1

1-2

2-3

3-1

Tacho Capture

Interrupts

C

177/294

1

ST7MC1/ST7MC2

MOTOR CONTROLLER (Cont’d)

Figure 100. Overview of MTIM Timer in Speed Measurement Mode

f

Registers: MZFR* MPHST* MPAR*

MTC

PERIPH

(4MHz)

(16MHz)

Bits:

TES[1:0]

C

ECM IS[1:0]

Encoder

Clock

MPAR* and MPHST*

Registers

Tacho Capture

MTIM Read access

RTC interrupt

IS[1:0] bits

TES[1:0] bits

RPI

MTIM Register = FFh?

+1

4

Ratio

MPRSR Register

ST[3:0] Bits

1 / 2

Tratio

-1

MZREG < 55h?

RMI

16 MHz - 500 Hz

Clock

§

MTIM

MTIML

C

clr

16-bit Up Counter

LSbits

MSbits

C

MZREG

MZPRV

16-bit Capture Register

FFh (Fixed)

MDREG

Compare

S

Notes:

§

= Register updated on R event

To interrupt generator

(Capture Event)

To interrupt generator

(Ratio Increment Event)

C

S

RPI

RMI

*

= Register set-up described in

Speed Sensor Mode Section

To interrupt generator

(Speed Error Event)

To interrupt generator

(Ratio Decrement Event)

178/294

1

ST7MC1/ST7MC2

MOTOR CONTROLLER (Cont’d)

A logic block manages capture operations de-

pending on the sensor type. A capture is initiated

on an active edge (“Tacho capture” event) when

using a tachogenerator.

vided by two). The RPI bit in the MISR register is

set and an interrupt is generated (if RIM is set).

– When a capture event occurs, if the

[MTIM:MTIML] timer value is below 5500h, the

prescaler is automatically decremented in order

to speed up the counter and keep precision bet-

ter than 0.005% (1/5500h). The MTIM and

MTIML registers are shifted left (multiplied by

two). The RMI bit in the MISR register is set and

an interrupt is generated if RIM is set.

If an encoder is used, the capture is triggered on

two events depending on the Encoder Capture

Mode bit (ECM) in the MZFR register:

– Reading the MSB of the counter in manual

mode (ECM = 1)

– Interrupt from the Real Time Clock in automat-

ic mode (ECM = 0)

– If the prescaler contents reach the value 0, it can

no longer be automatically decremented, the

[MTIM:MTIML] timer continues working with the

same prescaler value, i.e. with a lower accuracy.

No RMI interrrupt can be generated.

The clock source of the counter is selected de-

pending on sensor type:

– Motor Control Peripheral clock (16 MHz) with

tachogenerator or Hall sensors

– Encoder Clock

– If the prescaler contents reach the value 15, it

can no longer be automatically incremented.

When the timer reaches the value FFFFh, the

prescaler and all the relevant registers remain

unchanged and no interrupt is generated, the

timer clock is disabled, and its contents stay at

FFFFh. The capture logic block still works, ena-

bling the capture of the maximum timer value.

In order to optimize the accuracy of the measure-

ment for a wide speed range, the auto-updated

prescaler functionality is used with slight modifica-

tions compared to Sensor/Sensorless Modes (re-

fer to Figure 101 and Table 38).

– When the [MTIM:MTIML] timer value reaches

FFFFh, the prescaler is automatically increment-

ed in order to slow down the counter and avoid

an overflow. To keep consistent values, the

MTIM and MTIML registers are shifted right (di-

The only automatically updated registers for the

Speed Sensor Mode are MTIM and MTIML. Ac-

cess to Delay manager registers in Speed Sensor

Mode is summarised in Table 41.

Figure 101. Auto-updated prescaler functional diagram

[MTIM:MTIML] Timer Overflow

(MTIM = MTIML = FFh)

Capture with [MTIM:MTIML] Timer < 5500h

(MZREG < 55h)

Begin

No

Ratio < Fh?

Ratio > 0?

Yes

Ratio = Ratio + 1

Ratio = Ratio - 1

Counter = Counter/2

Counter = 0

End

Slow-down control

Speed-up control

179/294

1

ST7MC1/ST7MC2

MOTOR CONTROLLER (Cont’d)

Three kinds of interrupt can be generated in

Speed Sensor Mode, as summarized in Figure

102:

Measurement Mode: In order to set-up the

[MTIM:MTIML] counter properly before any speed

measurement, the following procedure must be

applied:

– C interrupt, when a capture event occurs; this in-

terrupt shares resources (Mask bit and Flag) with

the Commutation event in Switched/Au-

toswitched Mode, as these modes are mutually

exclusive.

– The peripheral clock must be disabled (resetting

the CKE bit in the MCRA register) to allow write

access to ST[3:0], MTIM and MTIML (refer to Ta-

ble 41),

– MTIM, MTIML must be reset and appropriate val-

ues must be written in the ST[3:0] prescaler

adapt to the frequency of the signal being meas-

ured and to allow speed measurement with suffi-

cient resolution.

– RPI/RMI interrupts occur when the ST[3:0] bits of

the MPSR register are changed, either automat-

ically or by hardware.

– S interrupt occurs when a Speed Error happens

(i.e. a successful comparison between

Note on MTIML: The Least Significant Byte of the

counter (MTIML) is not used when working in Po-

sition Sensor or Sensorless Modes.

[MTIM:MTIML] and [MDREG:FF]). This interrupt

has the same channel as the Emergency Stop in-

terrupt (MCES), as it also warns the user about

abnormal system operation. The respective Flag

bits have to be tested in the interrupt service rou-

tine to differentiate Speed Errors from Emergen-

cy Stop events.

Debug option: a signal reflecting the capture

events may be output on a standard I/O port for de-

bugging purposes. Refer to section9.6.7.3 on page

168 for more details.

These interrupts may be masked individually.

Note on Delay Manager Initialization in Speed

Figure 102. Prescaler auto-change example

C

E

APTURE

VENTS

[MTIM:MTIML]

FFFFh

FAFFh

USUAL

WORKING

RANGE

8000h

5500h

C

S

RPI

RMI

Notes:

Events:

[MTIM:MTIML] Input Clock:

F_x(ST[3:0] = n)

F_x/ 2 (ST[3:0] = n+1)

Capture

C

S

RPI

RMI

Speed Error

Ratio Increment

Ratio Decrement

180/294

1

ST7MC1/ST7MC2

MOTOR CONTROLLER (Cont’d)

9.6.7.6 Summary

The use of the Delay manager registers for the

various available modes is summarized in Table

42.

Table 42. MTIM Timer-related Registers

Name

MTIM

Reset Value

00h

Switched / Auto Switched Mode

Timer Value

Speed Measurement Mode

16-bit Timer MSB Value

16-bit Timer LSB Value

Capture of 16-bit Timer MSB

Capture of 16-bit Timer LSB

N/A

MTIML

MZREG

MZPRV

MCOMP

00h

N/A

00h

Capture/compare Zn

Capture Zn-1

00h

Compare Cn+1

Compare for Speed Error

interrupt generation

MDREG

00h

Demagnetization Dn

age reference depending on the maximum current

acceptable for the motor. This current limitation is

9.6.8 PWM Manager

generated with the V

voltage by means of an

DD

The PWM manager controls the motor via the six

output channels in voltage mode or current mode

depending on the V0C1 bit in the MCRA register.

A block diagram of this part is given in Figure 104.

external resistor divider but can also be adjusted

with an external reference voltage (≤ 5 V). The ex-

ternal components are adjusted by the user de-

pending on the application needs. In Voltage

mode, it is mandatory to set a current limitation. As

this limitation is set for safety purposes, an inter-

rupt can be generated when the motor current

feedback reaches the current limitation in voltage

mode. This is the current limitation interrupt and it

is enabled by setting the corresponding CLM bit in

the MIMR register. This is useful in voltage mode

for security purposes.

9.6.8.1 Voltage Mode

In Voltage mode (V0C1 bit = ”0”), the PWM signal

which is applied to the switches is generated by

the 12-bit PWM Generator compare U.

Its duty cycle is programmed by software (refer to

the PWM Generator section) as required by the

application (speed regulation for example).

The current comparator is used for safety purpos-

es as a current limitation. For this feature, the de-

tected current must be present on the MCCFI pin

and the current limitation must be present on pin

MCCREF. This current limitation is fixed by a volt-

The PWM signal is directed to the channel manag-

er that connects it to the programmed outputs (see

Figure 104).

181/294

1

ST7MC1/ST7MC2

MOTOR CONTROLLER (Cont’d)

9.6.8.2 Over Current Handling in Voltage mode

The detected current input must be present on the

MCCFI pin.

When the current limitation interrupt is enabled by

setting the CLIM bit in the MIMR register (available

only in Voltage mode), the OCV bit in MCRB reg-

ister will determine the effect of this interrupt on

the MCOx outputs as shown in Table 43.

9.6.8.4 Current Feedback Comparator

Two programmable filters are implemented:

– A blanking window ( Current Window Filter) after

PWM has been switched ON to avoid spurious

PWM OFF states caused by parasitic noise

Table 43. OCV bit effect

– An event counter (Current Feedback Filter) to

prevent PWM being turned OFF when the first

comparator edge is detected.

CLIM bit CLI bit OCV bit Output effect Interrupt

Normal running

0

1

0

1

0

1

x

0

No

mode

PWM is put OFF

on Current loop

effect

Figure 103. Current Window and Feedback

Filters

No

Normal running

mode

PWM on

No

PWM is put OFF

on Current loop

effect

Yes

CURRENT

WINDOW

FILTER

End of

Blanking Window

?

No

All MCOx outputs

are put in reset

1

Yes

state (MOE reset)

For safety purposes, it can be necessary to put all

MCOx outputs in reset state (high impedance or

low state depending on the DISS bit in the MSCR

register) on a current limitation interrupt. This is

the purpose of the OCV bit. When a current limita-

tion interrupt occurs, if the OCV bit is reset, the ef-

fect on the MCOx outputs is only to put the PWM

signal OFF on the concerned outputs. If the OCV

bit is set, when the current limitation interrupt oc-

curs, all the MCOx outputs are put in reset state.

Yes

CURRENT

FEEDBACK

FILTER

Yes

Current >

Limit

?

No

Reset counter

Limit=1?

9.6.8.3 Current Mode

In current mode, the PWM output signal is gener-

ated by a combination of the output of the meas-

urement window generator (see Figure 105) and

the output of the current comparator, and is direct-

ed to the output channel manager as well (Figure

106).

Increment counter

Yes

No

Counter=

Limit?

The current reference is provided to the compara-

tor by Phase U, V or W of the PWM Generator (up

to 12-bit accuracy) the signal from the three com-

pare registers U, V or W can be output by setting

the PWMU, PWMV or PWMW bits in the MPWME

register. The PWM signal is filtered through an ex-

ternal RC filter on pin MCCREF.

Yes

Set the CL bit

182/294

1

ST7MC1/ST7MC2

MOTOR CONTROLLER (Cont’d)

Table 44. Current Window filter Setting

Table 45. Current Feedback Filter Setting

CFW2 CFW1 CFW0

Blanking window length

Nb of Feedback Samples

needed to turn OFF PWM

CFF2 CFF1 CFF0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Blanking window off

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

3

4

5

6

7

8

0.5 µs

1 µs

1.5 µs

2 µs

2.5 µs

3 µs

3.5 µs

Note: Times are indicated for 4 MHz f

PERIPH

The Current Window filter is activated each time

the PWM is turned ON. It blanks the output of the

current comparator during the time set by the

CFW[2:0] bits in the MCFR register. The reset val-

ue is 000b (blanking window off).

The ON time of the resulting PWM starts at the

end of the measurement window (rising edge),

and ends either at the beginning of the next meas-

urement window (falling edge), or when the cur-

rent level is reached.

The Current feedback filter sets the number of

consecutive valid samples (when current is above

the limit) needed to generate the active CL event

used to turn OFF the PWM. The reset value is 1.

Note: Be careful that the current comparator is

OFF until the CKE and/or DAC bits are set in the

MCRA register.

The sampling of the current comparator is done at

f

/4.

PERIPH

183/294

1

ST7MC1/ST7MC2

MOTOR CONTROLLER (Cont’d)

9.6.8.5 Current feedback amplifier

MCCFI pin to be directly connected to the compa-

rator and the OAP, OAN and OAZ pins can be

used to amplify another signal. Both the OAZ and

MCCFI pins can be connected to an ADC entry.

See (Figure 104).

In both current and voltage mode, the current

feedback from the motor can be amplified before

entering the comparator. This is done by an inte-

grated Op-amp that can be used when the OAON

bit is set in the OACSR register and the CFAV bit

in the MREF register is reset. This allows the three

points of the Op-amp to be accessed for a pro-

grammable gain. The CFAV bit in the MREF regis-

ter selects the MCCFI or OAZ pin as the compara-

tor input as shown in the following table.

Note: The MCCFI pin is not available in TQFP32;

SDIP32 and TQFP44 devices. In this case, the

CFAV bit must be reset. The choice to use the Op-

amp or not is made with the OAON bit.

9.6.8.6 Measurement Window

In current mode, the measurement window fre-

quency can be programmed between 390Hz and

50KHz by the means of the SA[3:0] bits in the

MPRSR register.

Table 46. Comparator input selection

CFAV bit

Meaning

Select OAZ as the current comparator in-

put

Note: These frequencies are given for a 4 MHz

peripheral input frequency for a BLDC drive

(XT16, XT8 bits in MCONF register).

0

Select MCCCFI as the current compara-

tor input

1

In sensorless mode this measurement window can

be used to detect BEMF zero crossing events. Its

width can be defined between 2.5µs and 40µs as a

minimum in sensorless mode by the OT[3:0] bits in

the MPWME register.

If the amplifier is not used for current feedback, it

can be used for other purposes. In this case, the

OAON bit in the OACSR register and the CFAV bit

in the MREF register both have to be set. This

means that the current feedback has to be on the

Figure 104. Current Feedback

MREF Register

PWME[U:V:W] bit

MCPWMU/V/W

12-Bit PWM generator

LEGEND:

(I): Current mode

(V): Voltage mode

CLI: Current limitation inter-

rupt

MREF

Register

OACSR

Register

CFAV bit

OAON bit

OAP

OAN

+

-

MCFR register

V

DD

CFF[2:0] bits

OAZ

R

1ext

(I)

C

+

-

CLI

MCCFI

(V)

Filter

V

R

ADC

CREF

2ext

MCCREF

To Phase State

Control

R

D

EXT

CFW[2:0] bits

MCFR register

V

MAX = V

Q

CREF

DD

Power down mode

CP

S

Internal clock

Sampling frequency

I

12-bit PWM generator/Compare U

V

MCRA Register

V0C1 bit

184/294

1

ST7MC1/ST7MC2

MOTOR CONTROLLER (Cont’d)

This sets the minimum off time of the PWM signal

generated by this internal clock. This off time can

vary depending on the output of the current feed-

back comparator. In sensor mode (SR=1) and

when the sampling for the Z event is done during

the PWM ON time in sensorless mode (SPLG bit is

set in MCRC register and /or DS[3:0] bits with a

value other than 000 in MCONF register), there is

no minimum OFF time required anymore, the min-

imum off time is set automatically to 0µs and the

OFF time of the PWM signal is controlled only by

the current regulation loop.

Warning: If the off time value set is superior than

the period of the PWM signal (for example 40µs off

time for a 50KHz(25µs period) PWM frequency),

then the signal output on MCOx pins selected is a

100% duty cycle signal (always at 1).

Table 48. Off time table

Sensor Mode

(SR=1) or sam-

Off Time sen-

pling during ON

sorless mode

OT3 OT2 OT1 OT0

time in sensor-

less (SPLG =1

and/or DS[3:0]

bits)

(SR=0)

Table 47. Sampling Frequency Selection

(DS[3:0]=0)

SA3 SA2 SA1 SA0

Sampling Frequency

50.0 KHz

40.0 KHz

33.33 KHz

25.0 KHz

20.0 KHz

18.1 KHz

15.4 KHz

12.5 KHz

10 KHz

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2.5 µs

5 µs

7.5 µs

10 µs

12.5 µs

15 µs

17.5 µs

20 µs

No minimum off

time

22.5 µs

25 µs

6.25 KHz

3.13 KHz

1.56 KHz

1.25 KHz

961 Hz

27.5 µs

30 µs

32.5 µs

35 µs

37.5 µs

40 µs

625 Hz

390 Hz

Note: Times are indicated for 4 MHz f

PERIPH

Figure 105. Sampling clock generation block

MPRSR Register

SA[3:0] bits

4

T

f

sampling

PERIPH

Frequency logic

Off-Time logic

2

R

S

Q

(measurement window)

T

off

Note: The MTC controller input frequency (

.

f

) is 4 MHz in this example,

PERIPH

It can be configured to 8MHz with the XT16: XT8 bits in the MCONF register

OT[3:0] bits

MPWME Register

185/294

1

ST7MC1/ST7MC2

MOTOR CONTROLLER (Cont’d)

9.6.9 Channel Manager

– A multiplexer to direct the PWM to the low and/

or high channel group

The channel manager consists of:

– A tristate buffer asynchronously driven by an

emergency input

– A Phase State register with preload and polarity

function

The block diagram is shown in Figure 106.

Figure 106. Channel Manager Block Diagram

MCRA Register

V0C1 bit

Notes:

Reg

Updated/Shifted on

Updated with Reg

R

PWM generator

on

C

n+1

Reg

n

PWM Generator

V

I

V

I

C

urrent Mode

Voltage Mode

V

S Q

Sampling frequency

events:

C

Z

Commutation

BEFM

Zero-crossing

D

Current comparator

output

S,H

End Of

Demagnetization

E

Emergency Stop

Filter

+/-

Ratio Updated (+1 or -1)

R

O

MCFR Register

CFF[2:0] bits

Multiplier

Overflow

R

1

Branch taken after C event

Branch taken after D event

2

MCRA Register

DAC bit

MCRA Register

SR bit

C

MPHST Register

OO bits*

Phase Register*

6

MCRB Register

OS[2:0] bits*

n

3

MPAR Register

OE[5:0] bits

6

Channel [5:0]

8

Dead

Time

Dead

Time

Dead

Time

MDTG Register

2

Channel [5:0]

6

MREF Register

High frequency chopper

HFE[1:0] bits

HFRQ[2:0] bits

5

MPOL Register

OP[5:0] bits

x6

OCV bit

CLIM bit

6

1

MCRA Register

MOE bit

x6

1

CLI bit

1

* = Preload register, changes taken into account at next C event.

186/294

1

ST7MC1/ST7MC2

MOTOR CONTROLLER (Cont’d)

9.6.9.1 MPHST Phase State Register

grammed using the OE[5:0] bits in the MPAR reg-

ister.

A preload register enables software to asynchro-

nously update the channel configuration for the

next step (during the previous commutation inter-

rupt routine for example): the OO[5:0] bits in the

MPHST register are copied to the Phase register

on a C event.

Table 51. Meaning of the OE[5:0] Bits

OE[5:0]

Channel group

High channel

Low channel

0

1

Table 49. Output State

The multiplexer directs the PWM to the upper

channel, the lower channel or both of them alter-

natively or simultaneously according to the periph-

eral state.

OP[5:0] bit

OO[5:0] bit

MCO[5:0] Pin

1 (OFF)

0

1

0

1

0

1

0-(PWM allowed)

0 (OFF)

This means that the PWM can affect any of the up-

per or lower channels allowing the selection of the

most appropriate reference potential when free-

wheeling the motor in order to:

1-(PWM allowed)

Direct access to the phase register is also possible

when the DAC bit in the MCRA register is set.

– Improve system efficiency

– Speed up the demagnetization phase

– Enable Back EMF zero crossing detection.

Note 1: In Direct Access Mode (DAC bit is set in

MCRA register), a C event is generated as soon

as there is a write access to OO[5:0] bits in

MPHST register.

The OS[2:0] bits in the MCRB register allow the

PWM configuration to be configured for each case

as shown in Figure 108 and Figure 107.

Note 2: In Direct Access mode (DAC bit is set in

MCRA register) the PWM application is selected

by the OS0 bit in the MCRB register.

During demagnetization, the OS2 bit is used to

control PWM mode, and it is latched in a preload

register so it can be modified when a commutation

event occurs and the configuration is active imme-

diately.

Table 50. DAC and MOE Bit Meaning

MOE

bit

DAC

bit

Effect on Output

The OS1 bit is used to control the PWM between

the D and Z events to control back-emf detection.

0

x

Reset state*

Standard

OS0 bit will allow to control the PWM signal be-

tween Z event and next C event.

1

0

running mode

Note about demagnetization speed-up: during

demagnetization the voltage on the winding has to

be as high as possible in order to reduce the de-

magnetization time. Software can apply a different

PWM configuration on the outputs between the C

and D events, to force the free wheeling on the ap-

propriate diodes to maximize the demagnetization

voltage.

MPHST register value (depending on

MPOL, MPAR register values and

PWM setting) see Table 75

1

*Note: The reset state of the outputs can be either

high impedance, low or high state depending on

the corresponding option bit.

The polarity register is used to match the polarity

of the power drivers keeping the same control log-

ic and software. If one of the OPx bits in the MPOL

register is set, this means the switch x is ON when

9.6.9.2 Emergency Feature

When the NMCES pin goes low

– The tristate output buffer is put in reset state

asynchronously

MCOx is V

.

DD

Each output status depends also on the momen-

tary state of the PWM, its group (low or high), and

the peripheral state.

– The MOE bit in the MCRA register is reset

– An interrupt request is sent to the CPU if the EIM

bit in the MIMR register is set

PWM Features

This bit can be connected to an alarm signal from

the drivers, thermal sensor or any other security

component.

The outputs can be split in two PWM groups in or-

der to differentiate the high side and the low side

switches. This output property can be pro-

This feature functions even if the MCU oscillator is

off.

187/294

1

ST7MC1/ST7MC2

MOTOR CONTROLLER (Cont’d)

Figure 107. PWM application in Voltage or Current sensorless mode (see Table 62)

OS0 PWM behaviour after Z

OS2 PWM behaviour after C

and before D

OS1 PWM behaviour after D

and before Z

and before next C

0

1

High Channels

Low Channels

0

1

High Channels

Low Channels

0

1

High Channels

Low Channels

E

v

Step

O

e

S

n

t

O

E

M

OS2

[

OS1

OS0

[

2

:

[

5

:

o

d

5

:

0

]

0

e

]

Demagnetization

DeWmaaitgZneetivzeantiton

Delay

]

1

0

1

High

Low

000

001

0

1

High

Low

High

Low

0

1

010

011

High

Low

High

0

1

0

1

100

101

Low

High

0

1

Low

High

0

1

110

111

Low

High

0

1

Low

188/294

1

ST7MC1/ST7MC2

MOTOR CONTROLLER (Cont’d)

Figure 108. PWM application in Voltage or Current Sensor Mode (see Table 63)

(sensor mode: SR=1)

OS1 Not Used

OS0 PWM behaviour after Z

and before next C

OS2 PWM behaviour after C

and before Z

-

0

1

High Channels

Low Channels

0

1

High Channels

Low Channels

E

v

O

]

O

e

Step

O

S

E

n

t

M

OS2

Wait Z event

OS0

[

5

:

[

2

:

5

o

d

:

0

]

0

]

Delay

e

1

0

xx

0

1

High

Low

0x0

0x1

0

High

Low

High

Low

1

0

1x0

1x1

1

0

1

High

Low

In sensor mode, there is no demagnetisation event and the PWM behaviour can be

changed before and after Z event

189/294

1

ST7MC1/ST7MC2

MOTOR CONTROLLER (Cont’d)

9.6.9.3 Dead Time Generator

For each of the three PWM channels, there is one

6-bit Dead Time generator available.

When using typical triple half bridge topology for

power converters, precautions must be taken to

avoid short circuits in half bridges. This is ensured

by driving high and low side switches with comple-

mentary signals and by managing the time be-

tween the switching-off and the switching-on in-

stants of the adjacent switches.

It generates two output signals: A and B.

The A output signal is the same as the input phase

signal except for the rising edge, which is delayed

relative to the input signal rising edge.

The B output signal is the opposite of the input

phase signal except the rising edge which is de-

layed relative to the input signal falling edge.

This time is usually known as deadtime and has to

be adjusted depending on the devices connected

to the PWM outputs and their characteristics (in-

trinsic delays of level-shifters, delays due to power

switches,...).

Figure 109 shows the relationship between the

output signals of the deadtime register and its in-

puts.

If the delay is greater than the width of the active

phase (A or B) then the corresponding pulse is not

generated (see Figure 110 and Figure 111).

When driving motors in six-step mode, the dead-

time generator function also allows synchronous

rectification to be performed on the switch adja-

cent to the one where PWM is applied to reduce

conduction losses.

Figure 109. Dead Time waveforms

Reference

5V

0V

5V

Input signal

Output A

0V

Delay

5V

0V

Output B

Delay

Figure 110. Dead time waveform with delay greater than the negative PWM pulse

5V

Input

0V

5V

Output A

Delay

0V

5V

0V

Output B

190/294

1

ST7MC1/ST7MC2

MOTOR CONTROLLER (Cont’d)

Figure 111. Dead Time waveform with delay greater than the positive PWM pulse

5V

Input

0V

5V

Output A

0V

5V

0V

Output B

Delay

Table 52. Dead time programming and example

T

Dead time range

dtg

DTG5 DTG4

T

Deadtime expression Deadtime value

dtg

@16MHz F

125ns

@ 16MHz F

mtc

0

1

X

0

1

2xT

4xT

8xT

(DTG[4..0]+1) x T

(DTG[3..0]+1) x T

From 1 to 32 T

dtg

0.125µs to 4µs

4.25µs to 8µs

8.5µs to 16µs

mtc

dtg

250ns

From 17 to 31 T

dtg

500ns

The deadtime delay is the same for each of the

channels and is programmable with the DTG[5..0]

bits in the MDTG register.

The dead time generator is enabled/disabled us-

ing the DTE bit.

The resolution is variable and depends on the

DTG5 and DTG4 bits. Table 52 summarizes the

set-up of the deadtime generator.

The effect of the DTE bit depends on the PCN bit

value.

If the PCN bit is set:

IT

is the period of the Dead Time Generator in-

mtc

ꢀ

DTE is read only. To reset it, first reset the PCN

bit, then reset DTE and set PCN to 1 again.

put clock (F

= 16 MHz in most cases, not affect-

mtc

ed by the XT16:XT8 prescaler bits in the MCONF

ꢀ

If DTE=0, the high and low side outputs are

simply complemented (no deadtime insertion,

DTG[5:0] bits are not significant); this is to allow

the use of an external dead time generator.

register).

For safety reasons and since the deadtime de-

pends only on external component characteristics

(level-shifter delay, power components switching

duration,...) the register used to set-up deadtime

duration can be written only once after the MCU

reset. This prevents a corrupted program counter

modifying this system critical set-up, which may

cause excessive power dissipation or destructive

shoot-through in the power stage half bridges.

Note: The reset value of the MDTG register is FFh

so when configuring the dead time, it is mandatory

to follow one the two following sequences:

ꢀ

To use dead t imes while the PCN bit is set; from

reset state write the MDTG value at once. The

DTE bit will be read back as 1 whatever the

programming value (read only if PCN=1)

ꢀ

To use dead times while the PCN bit is reset,

write first the dead time value in DTG[5:0], then

reset the PCN bit, or do both actions at the same

time.

When using the three independent U, V and W

PWM signals (PCN bit set) (see Figure 112) to

drive the MCOx outputs, deadtime is added as

shown in Figure 109.

191/294

1

ST7MC1/ST7MC2

MOTOR CONTROLLER (Cont’d)

Figure 112. Channel Manager Output Block Diagram with PWM generator delivering 3 PWM signals

PWM generator signals

W

V

U

MDTG Register

PCN bit = 1

8

Dead

Time

Dead

Time

Dead

Time

Channel [5:4] Channel [3:2] Channel [1:0]

High frequency chopper

MREF Register

2

HFE[1:0] bits

HFRQ[2:0] bits

5

MPOL Register

OP[5:0] bits

x6

OCV bit

CLIM bit

6

1

MRCA Register

MOE bit

1

CLI bit

1

192/294

1

ST7MC1/ST7MC2

MOTOR CONTROLLER (Cont’d)

If the PCN bit is reset, one of the three PWM sig-

nals (the one set by the compare U register pair) or

the output of the measurement window generator

(depending on if the driving mode is voltage or cur-

rent) is used to provide six-step signals through

the PWM manager (to drive a PM BLDC motor for

instance).

Table 53. Dead Time generator outputs

PCN = 0; DTE =1; x= 0, 2, 4

On/Off x

On/Off x+1

MCOx+1

output

MCOx output

(OOx bit) (OOx+1 bit)

0

1 (pwm*)

PWM

1 (pwm*)

0

PWM

In that case, DTE behaves like a standard bit (with

multiple write capability). When the deadtime gen-

erator is enabled (bit DTE=1), some restrictions

are applied, summarized in Table 53:

1

1 (pwm*)

0

1

0

1

0

1 (pwm*)

1

0

1

0

1

0

ꢀ

Channels are now grouped by pairs:

Channel[0:1], Channel[2:3], Channel[4:5]; a

deadtime generator is allocated to each of these

pairs (see cautions below);

The input signal of the deadtime generator is the

active output of the PWM manager for the

corresponding channel. For instance, if we

consider the Channel[0:1] pair, it may be either

Channel0 or Channel1.

* PWM generation enabled

Warning: Grouping channels by pairs imposes the

external connections between the MCO outputs

and power devices; the user must therefore pay at-

tention to respect the “recommended schematics”

described in Figure 121. on page 224 and Figure

122

ꢀ

When both channels of a pair are inactive, the

corresponding outputs will also stay inactive

(this is mandatory to allow BEMF zero-crossing

detection).

Note: As soon as the channels are grouped in

pairs, special care has to be taken in configuring

the MPAR register for a PM BLDC drive. If both

channels of the same pair are both labelled “high”

for example and if the PWM is applied on high

channels, the active MCO output x (OOx=1 bit in

the MPHST register) outputs PWM and the paired

MCO output x+1 (OOx+1bit in the MPHST regis-

ter) outputs PWM and vice versa.

Table 53 summarizes the functionality of the dead-

time generator when the PCN bit is reset. 1(pwm*)

means that the corresponding channel is active (1

in the corresponding bit in the MPHST register),

and a PWM signal is applied on it (using the MPAR

register and the OS[2:0] bits in MCRB register).

PWM represents the complementary signals (al-

though the duty cycle is slightly different due to

deadtime insertion). 0 means that the channel is

inactive and 1 means that the channel is active

and a logic level 1 is applied on it (no PWM signal).

Caution: When PCN=0 and a complementary

PWM is applied (DTE=1) on one channel of a pair,

if both channels are active, this corresponds in

output to both channels OFF. This is for security

purpose to avoid cross-conduction.

Caution: To clear the DTE bit from reset state of

MDTG register (FFh), the PCN bit must be cleared

before.

193/294

1

ST7MC1/ST7MC2

MOTOR CONTROLLER (Cont’d)

Figure 113. Channel Manager Output Block Diagram with PWM generator delivering 1 PWM signal

PWM generator

U channel

V

S

Q

I

Sampling frequency

R

Current comparator

output

Phase Register*

n

MPAR Register

OE[5:0] bits

6

Ch5

Ch4

Ch3

Ch2

Ch1

Ch0

MDTG Register

PCN bit = 0

8

Dead

Time

Dead

Time

Dead

Time

Channel [5:4] Channel [3:2] Channel [1:0]

High frequency chopper

6

MREF Register

2

HFE[1:0] bits

HFRQ[2:0] bits

5

MPOL Register

x6

OP[5:0] bits

OCV bit

CLIM bit

6

1

MCRA Register

MOE bit

1

CLI bit

1

194/294

1

ST7MC1/ST7MC2

MOTOR CONTROLLER (Cont’d)

9.6.9.4 Programmable Chopper

Table 55. Chopping frequency

Depending on the application hardware, a chopper

may be needed for the PWM signal. The MREF

register allows the chopping frequency and mode

to be programmed.

Chopping

frequency

= 16MHz

Chopping

frequency

HFRQ2 HFRQ1 HFRQ0

F

mtc

F

= 4MHz

mtc

F

= 8MHz

mtc

The HFE[1:0] bits program the channels on which

chopping is to be applied. The chopped PWM sig-

nal may be needed for high side switches only, low

side switches or both of them in the same time

(see Table 54).

0

1

0

1

0

1

0

1

0

1

0

1

0

1

100 KHz

200 KHz

400 KHz

500 KHz

800 KHz

1 MHz

50 KHz

100 KHz

200 KHz

250 KHz

400 KHz

500 KHz

Table 54. Chopping mode

HFE[1:0] bits

HFE1 HFE0

Chopping mode

1.33 MHz

2 MHz

666.66 MHz

1 MHz

PCN bit =0

PCN bit =1

OFF

0

OFF

Low side switches

MCO1, 3, 5

Note: When the PCN bit = 0:

0

1

Low channels only

– If complementary PWM signals are not applied

(DTE bit = 0), the high and low drivers are fixed

by the MPAR register. Figure 106, Figure 112

and Figure 113 indicate where the HFE[1:0] bits

are taken into account depending on the PWM

application.

High side switches

MCO0, 2, 4

1

0

1

High channels only

Both Low and High Both high and low

channels sides

The chopping frequency can any of the 8 values

from 100KHz to 2MHz selected by the HFRQ[2:0]

bits in the MREF register (see Table 55).

– If complementary PWM signals are applied (DTE

bit = 1), the channels are paired as explained in

“Dead Time Generator” on page 190. This

means that the high and low channels are fixed

and the HFE[1:0] bits indicate where to apply the

chopper. Figure 114 shows typical complemen-

tary PWM signals with high frequency chopping

enabled on both high and low drivers.

Figure 114. Complementary PWM signals with chopping frequency on high and low side drivers.

Reference

5V

Input signal

0V

Output A

5V

0V

Delay

5V

0V

Output B

Delay

195/294

1

ST7MC1/ST7MC2

MOTOR CONTROLLER (Cont’d)

9.6.10 PWM Generator Block

frequency carrier may be added. This is the case

of AC induction motors or PMAC motors for in-

stance, supplied with 120° shifted sinewaves in

voltage mode.

The PWM generator block produces three inde-

pendent PWM signals based on a single carrier

frequency with individually adjustable duty cycles.

9.6.10.1 Main Features

Depending on the motor driving method, one or

three of these signals may be redirected to the oth-

er functional blocks of the motor control peripheral,

using the PCN bit in the MDTG register.

ꢀ

12-bit PWM free-running Up/Down Counter with

up to 16MHz input clock (F ).

mtc

Edge-aligned

and

center-aligned

PWM

operating modes

Possibility to re-load compare registers twice

per PWM period in center-aligned mode

When driving PM BLDC motors in six-step mode

(voltage mode only, either sensored or sensor-

less) a single PWM signal (Phase U) is used to

supply the Input Stage, PWM and Channel Man-

ager blocks according to the selected modes.

ꢀ

Full-scale PWM generation

PWM update interrupt generation

8-bit repetition counter

8-bit PWM mode

Timer re-synchronisation feature

For other kind of motors requiring independent

PWM control for each of the three phases, all

PWM signals (Phases U, V and W) are directed to

the channel manager, in which deadtime or a high

Figure 115. PWM generator block diagram

MREP Register

U

12-bit Compare 0 Register

Repetition

counter

U

Clear or Up/Down

MPCR Register

CMS bit

F

Prescaler

PCP[2:0] bits

mtc

Up to 16MHz

12-bit PWM Counter

U

13-bit Compare U Register

13-bit Compare V Register

13-bit Compare W Register

Notes:

Preload registers transferred

to active registers on U event

Reg

event:

U

Update of compare registers

PWM interrupt generation

196/294

1

ST7MC1/ST7MC2

MOTOR CONTROLLER (Cont’d)

9.6.10.2 Functional Description

9.6.10.4 PWM Operating mode

The 3 PWM signals are generated using a free-

running 12-bit PWM Counter and three 13-bit

Compare registers for phase U, V and W: MCM-

PU, MCMPV and MCMPW registers.

The PWM generator can work in center-aligned or

edge-aligned mode depending on the CMS bit set-

ting in the MPCR register.

Figure 116 shows the corresponding counting se-

quence .

A fourth 12-bit register is needed to set-up the

PWM carrier frequency: MCMP0 register.

It offers also an 8-bit mode to get a full 8-bit range

with a single compare register write access by set-

ting the PMS bit in MPCR register.

Each of these compare registers is buffered with a

preload register. Transfer from preload to active

registers is done synchronously with PWM counter

underflow or overflow depending on configuration.

This allows to write compare values without risks

of spurious PWM transitions.

The comparisons described here are performed

between the PWM Counter value extended to 13

bits and the 13-bit Compare register. Having a

compare range greater than the counter range is

mandatory to get a full PWM range (i.e. up to

100% modulation). This principle is maintained for

8-bit PWM operations.

The block diagram of the PWM generator is shown

on Figure 115.

ꢀ

Center-aligned Mode (CMS bit = 1)

9.6.10.3 Prescaler

In this operating mode, the PWM Counter counts

up to the value loaded in the 12-bit Compare 0 reg-

ister then counts down until it reaches zero and re-

starts counting up.

The 12-bit PWM Counter clock is supplied through

a 3-bit prescaler to allow the generation of lower

PWM carrier frequencies. It divides F

by 1, 2, 3,

mtc

..., 8 to get F

.

mtc-pwm

The PWM signals are set to ‘0’ when the PWM

Counter reaches, in up-counting, the correspond-

ing 13-bit Compare register value and they are set

to ‘1’ when the PWM Counter reaches the 13-bit

Compare value again in down-counting.

This prescaler is accessed through three bits

PCP[2:0] in MPCR register; this register is buff-

ered: the new value is taken into account after a

PWM update event.

Figure 116. Counting sequence in center-aligned and edge-aligned mode

center-aligned

0

1

2

....

15

16

15

....

2

1

0

1

mode

T

edge-aligned

mode

.....

0

1

.....

16

T

T = PWM period, Value of 12-bit Compare 0 Register= 16

197/294

1

ST7MC1/ST7MC2

MOTOR CONTROLLER (Cont’d)

If the 13-bit Compare register value is greater than

the extended Compare 0 Register (the 13 bit is

If the 13-bit Compare register value is 0, the corre-

sponding PWM output signal is held at ‘0’.

th

set to ‘0’), the corresponding PWM output signal is

held at ‘1’.

Figure 117 shows some center-aligned PWM

waveforms in an example where the Compare 0

register value = 8.

Figure 117. Center-aligned PWM Waveforms (Compare 0 Register = 8)

0

1

2

3

4

5

6

7

8

7

6

5

4

3

2

1

0

1

2

3

4

‘1’

‘0’

1 Compare Register value = 4

2 Compare Register value = 7

3 Compare Register value > = 8

4 Compare Register value = 0

198/294

1

ST7MC1/ST7MC2

MOTOR CONTROLLER (Cont’d)

Edge-aligned Mode (CMS bit = 0)

ꢀ

If the 13-bit Compare register value is greater than

the extended Compare 0 register (the 13 bit is

set to ‘0’), the corresponding PWM output signal is

held at ‘1’.

th

In this operating mode, the PWM Counter counts

up to the value loaded in the 12-bit Compare Reg-

ister. Then the PWM Counter is cleared and it re-

starts counting up.

If the 13-bit Compare register value = 0, the corre-

sponding PWM output signal is held at ‘0’.

The PWM signals are set to ‘0’ when the PWM

Counter reaches, in up-counting, the correspond-

ing 13-bit Compare register value and they are set

to ‘1’ when the PWM Counter is cleared.

Figure 118 shows some edge-aligned PWM wave-

forms in an example where the Compare 0 register

value = 8.

Figure 118. Edge-aligned PWM Waveforms (Compare 0 Register = 8)

0

1

2

3

4

5

6

7

8

0

1

2

3

4

‘1’

‘0’

1 Compare Register value = 4

2 Compare Register value = 8

3 Compare Register value > 8

4 Compare Register value = 0

199/294

1

ST7MC1/ST7MC2

MOTOR CONTROLLER (Cont’d)

ꢀ

12-bit Mode (PMS bit = 0 in the MPCR register)

source savings when computing three-phase duty

cycles during PWM interrupt routines. In this

mode, the Compare 0 and Compare U, V, W reg-

isters have the same size (8 bits). The extension of

the MCMPx registers is done in using the OVFx

bits in the MPCR register (refer to Figure 119).

These bits force the related duty-cycles to 100%

and are reset by hardware on occurence of a

PWM update event.

This mode is useful for MCMP0 values ranging

from 9 bits to 12 bits. Figure 119 presents the way

Compare 0 and Compare U, V, W should be load-

ed). It requires loading two bytes in the MCMPxH

and MCMPxL registers (i.e. MCMP0, MCMPU,

MCMPV and MCMPW 16-bit registers) following

the sequence described below:

– write to the MCMPxL register (LSB) first

– then write to the MCMPxH register (MSB).

Note about read access to registers with

preload: during read accesses, values read are

the content of the preload registers, not the active

registers.

The 16-bit value is then ready to be transferred in

the active register as soon as an update event oc-

curs. This sequence is necessary to avoid poten-

tial conflicts with update interrupts causing the

hardware transfer from preload to active registers:

if an update event occurs in the middle of the

above sequence, the update is effective only when

the MSB has been written.

Note about compare register active bit loca-

tions: the 13 active bits of the MCMPx registers

are left-aligned. This allows temporary calculations

to be done with 16-bit precision, round-up is done

automatically to the 13-bit format when loading the

values of the MCMPx registers.

Note about MCMP0x registers: the configuration

MCMP0H=MCMP0L=0 is not allowed

ꢀ

8-bit PWM mode (PMS bit = 1 in MPCR register)

This mode is useful whenever the MCMP0 value is

less or equal to 8-bits. It allows significant CPU re-

Figure 119. Comparison between 12-bit and 8-bit PWM mode

b7

b0

PWM frequency

set-up

MCMP0H

b7

MCMP0L

12-bit PWM mode

(PMS bit = 0)

b0 b7

Phase x duty

cycle set-up

Ext

MCMPxH

MCMPxL

b7

b0

PWM frequency

set-up

8-bit PWM mode

(PMS bit = 1)

MCMP0H

b7

MCMP0L

b0 b7

Phase x duty

cycle set-up

OvfX

MCMPxH

b7

MCMPxL

b0

OvfU OvfV OvfW

Equivalent bit location

Bit extending comparison range

Bit not available

MPCR

Ext

200/294

1

ST7MC1/ST7MC2

MOTOR CONTROLLER (Cont’d)

9.6.10.5 Repetition Down-Counter

aligned mode, i.e. one T

ing compare registers only once per PWM period

in center-aligned mode, maximum resolution is

period. When refresh-

mtc

Both in center-aligned and edge-aligned modes,

the four Compare registers (one Compare 0 and

three for the U, V and W phases) are updated

when the PWM counter underflow or overflow and

the 8-bit Repetition down-counter has reached ze-

ro.

2xT

, due to the symmetry of the pattern.

mtc

The repetition down counter is an auto-reload

type; the repetition rate will be maintained as de-

fined by the MREP register value (refer to Figure

120).

This means that data are transferred from the

preload compare registers to the compare regis-

ters every N cycles of the PWM Counter, where N

is the value of the 8-bit Repetition register in edge

-aligned mode. When using center-aligned mode,

the repetition down-counter is decremented every

time the PWM counter overflows or underflows. Al-

though this limits the maximum number of repeti-

tion to 128 PWM cycles, this makes it possible to

update the duty cycle twice per PWM period. As a

result, the effective PWM resolution in that case is

equal to the resolution we can get using edge-

9.6.10.6 PWM interrupt generation

A PWM interrupt is generated synchronously with

the “U” update event, which allows to refresh com-

pare values by software before the next update

event. As a result, the refresh rate for phases duty

cycles is directly linked to MREP register setting.

A signal reflecting the update events may be out-

put on a standard I/O port for debugging purposes.

Refer to section9.6.7.3 on page 168 for more de-

tails.

Figure 120. Update rate examples depending on mode and MREP register settings

Center-aligned mode

Edge-aligned mode

12-bit PWM

Counter

U

MREP = 0

MREP = 1

U

MREP = 2

MREP = 3

U

MREP = 3

and

re-synchronization

U

(by SW)

U

U Event: Preload registers transferred to active registers and PWM interrupt generated

U Event if transition from MREP = 0 to MREP = 1 occurs when 12-bit counter is equal

to MCP0.

201/294

1

ST7MC1/ST7MC2

MOTOR CONTROLLER (Cont’d)

9.6.10.7 Timer Re-synchronisation

MCMPxH must have been written, following the

mandatory LSB/MSB sequence, before setting

CKE bit). It consequently generates a U

interrupt.

The 12-bit timer can be re-synchronized by a sim-

ple write access with FFh value in the MISR regis-

ter. Re-synchronization means that the 12-bit

counter is reset and all the compare preload regis-

ters MCP0, MCPU, MCPV, MCPW are transferred

to the active registers.

9.6.11 Low Power Modes

Before executing a HALT or WFI instruction, soft-

ware must stop the motor, and may choose to put

the outputs in high impedance.

To re-synchronize the 12-bit timer properly , the

following procedure must be applied:

Mode

Description

– 1. Load the new values in the preload compare

registers

No effect on MTC interface.

WAIT

MTC interrupts exit from Wait mode.

MTC registers are frozen.

– 2. Load FFh value in the MISR register (this will

reset the counter and transfer the compare

preload registers in the active registers: U event)

In Halt mode, the MTC interface is in-

active. The MTC interface becomes

operational again when the MCU is

woken up by an interrupt with “exit

from Halt mode” capability.

– 3. Reset the PUI flag by loading 7Fh in the MISR

register. Refer to Note 2 on page 205

HALT

Note: Loading FFh value in the MISR register will

have no effect on any other flag than the PUI flag

and will generate a PWM update interrupt if the

PUM bit is set.

9.6.12 Interrupts

Interrupt Event

Enable Exit Exit

Control from from

Warning: In switched mode (SWA bit is reset), the

procedure is the same and loading FFh in the

MISR register will have no effect on flags except

on the PUI flag. As a consequence, it is recom-

mended to avoid setting RMI and RPI flags at the

same time in switched mode because none of

them will be taken into account.

Event

Flag

Bit

Wait Halt

Yes No

Ratio increment

Ratio decrement

Speed Error

RPI

RMI

SEI

EI

RIM

SEM

EIM

Emergency Stop

Current Limitation

BEMF Zero-Crossing

CLI

ZI

CLIM

ZIM

9.6.10.8 PWM generator initialization and start-

up

End of Demagnetization DI

DIM

Commutation or

CI

The three-phase generator counter stays in reset

state (i.e. stopped and equal to 0), as long as MTC

peripheral clock is disabled (CKE = 0).

CIM

Yes No

Capture

PWM Update

PUI

PUM

Setting the CKE bit has two actions on the PWM

generator:

The MTC interrupt events are connected to the

three interrupt vectors (see Interrupts chapter).

ꢀ

It starts the PWM counter

They generate an interrupt if the corresponding

Enable Control Bit is set and the interrupt mask in

the CC register is reset (RIM instruction).

ꢀ

It forces the update of all registers with preload

registers transferred on U update event, i.e.

MREP, MPCR, MCMP0, MCMPU, MCMPV,

MCMPW (in 12-bit mode, both MCMPxL and

202/294

1

ST7MC1/ST7MC2

MOTOR CONTROLLER (Cont’d)

9.6.13 Register Description

CAPTURE Z REGISTER (MZREG)

n

Read/Write

Reset Value: 0000 0000 (00h)

TIMER COUNTER REGISTER (MTIM)

Read /Write

Reset Value: 0000 0000 (00h)

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

ZC7

ZC6

ZC5

ZC4

ZC3

ZC2

ZC1

ZC0

T7

T6

T5

T4

T3

T2

T1

T0

Bits 7:0 = ZC[7:0]: Current Z Value or Speed cap-

ture MSB.

These bits contain the current captured BEMF val-

Bits 7:0 = T[7:0]: MTIM Counter Value.

These bits contain the current value of the 8-bit up

counter. In Speed Measurement Mode, when us-

ing Encoder sensor and MTIM captures triggered

by SW (refer to Figure 100) a read access to MTIM

register causes a capture of the [MTIM:MTIML]

register pair to the [MZREG: MZPRV] registers.

ue (Z ) in Switched and Autoswitched mode or the

N

MSB of the captured value of the [MTIM:MTIML]

registers in Speed Sensor Mode. A read access to

MZREG in this case disable the Speed captures

up to MZPRV reading (refer to Section 9.6.7.5

Speed Measurement Mode on page 176).

TIMER COUNTER REGISTER LSB (MTIML)

Read /Write

Reset Value: 0000 0000 (00h)

COMPARE C

Read/Write

Reset Value: 0000 0000 (00h)

REGISTER (MCOMP)

n+1

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

TL7

TL6

TL5

TL4

TL3

TL2

TL1

TL0

DC7

DC6

DC5

DC4

DC3

DC2

DC1

DC0

Bits 7:0 = TL[7:0]: MTIM Counter Value LSB.

These bits contain the current value of the least

significant byte of the MTIM up counter, when

used in Speed Measurement Mode (i.e. as a 16-bit

timer)

Bits 7:0 = DC[7:0]: Next Compare Value.

These bits contain the compare value for the next

commutation (C ).

N+1

DEMAGNETIZATION REGISTER (MDREG)

Read/Write

Reset Value: 0000 0000 (00h)

CAPTURE Z

Read /Write

Reset Value: 0000 0000 (00h)

REGISTER (MZPRV)

n-1

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

DN7

DN6

DN5

DN4

DN3

DN2

DN1

DN0

ZP7

ZP6

ZP5

ZP4

ZP3

ZP2

ZP1

ZP0

Bits 7:0 = DN[7:0]: D Value.

These bits contain the compare value for simulat-

ed demagnetization (D ) and the captured value

Bits 7:0 = ZP[7:0]: Previous Z Value or Speed

capture LSB.

These bits contain the previous captured BEMF

N

for hardware demagnetization (D ) in Switched

H

value (Z ) in Switched and Autoswitched mode

and Autoswitched mode.

N-1

or the LSB of the captured value of the

In Speed Sensor Mode, the register contains the

value used for comparison with MTIM registers to

generate a Speed Error event.

[MTIM:MTIML] registers in Speed Sensor Mode.

203/294

1

ST7MC1/ST7MC2

MOTOR CONTROLLER (Cont’d)

A WEIGHT REGISTER (MWGHT)

Read/Write

INTERRUPT MASK REGISTER (MIMR)

Read/Write

N

Reset Value: 0000 0000 (00h)

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

AN7

AN6

AN5

AN4

AN3

AN2

AN1

AN0

PUM

SEM

RIM

CLIM

EIM

ZIM

DIM

CIM

Bits 7:0 = AN[7:0]: A Weight Value.

Bit 7 = PUM: PWM Update Mask bit.

0: PWM Update interrupt disabled

1: PWM Update interrupt enabled

These bits contain the A weight value for the mul-

N

tiplier. In autoswitched mode the MCOMP register

is automatically loaded with:

Z x MWGHT

Z_Nx MWGHT

n

-1

or

(*)

Bit 6 = SEM: Speed Error Mask bit.

0: Speed Error interrupt disabled

1: Speed Error interrupt enabled

256(d)

when a Z event occurs.

(*) depending on the DCB bit in the MCRA regis-

ter.

Bit 5 = RIM: Ratio update Interrupt Mask bit.

0: Ratio update interrupts (R+ and R-) disabled

1: Ratio update interrupts (R+ and R-) enabled

PRESCALER & SAMPLING REGISTER

(MPRSR)

Read/Write

Reset Value: 0000 0000 (00h)

Bit 4 = CLIM: Current Limitation Interrupt Mask bit.

0: Current Limitation interrupt disabled

1: Current Limitation interrupt enabled

7

6

5

4

3

2

1

0

This interrupt is available only in Voltage Mode

(VOC1 bit=0 in MCRA register) and occurs when

the Motor current feedback reaches the external

current limitation value.

SA3

SA2

SA1

SA0

ST3

ST2

ST1

ST0

Bits 7:4 = SA[3:0]: Sampling Ratio.

These bits contain the sampling ratio value for cur-

rent mode. Refer to Table 47, “Sampling Frequen-

cy Selection,” on page 185.

Bit 3 = EIM: Emergency stop Interrupt Mask bit.

0: Emergency stop interrupt disabled

1: Emergency stop interrupt enabled

Bits 3:0 = ST[3:0]: Step Ratio.

These bits contain the step ratio value. It acts as a

prescaler for the MTIM timer and is auto incre-

mented/decremented with each R+ or R- event.

Refer to Table 40, “Step Frequency/Period Range

(4MHz),” on page 175 and Table 41, “Modes of

Accessing MTIM Timer-Related Registers,” on

page 175.

Bit 2 = ZIM: Back EMF Zero-crossing Interrupt

Mask bit.

0: BEMF Zero-crossing Interrupt disabled

1: BEMF Zero-crossing Interrupt enabled

Bit 1 = DIM: End of Demagnetization Interrupt

Mask bit.

0: End of Demagnetization interrupt disabled

1: End of Demagnetization interrupt enabled if the

HDM or SDM bit in the MCRB register is set

Bit 0 = CIM: Commutation / Capture Interrupt

Mask bit

0: Commutation / Capture Interrupt disabled

1: Commutation / Capture Interrupt enabled

204/294

1

ST7MC1/ST7MC2

MOTOR CONTROLLER (Cont’d)

INTERRUPT STATUS REGISTER (MISR)

Read/Write

1: Emergency stop interrupt pending

Reset Value: 0000 0000 (00h)

Bit 2 = ZI: BEMF Zero-crossing interrupt flag.

0: No BEMF Zero-crossing Interrupt pending

1: BEMF Zero-crossing Interrupt pending

7

6

5

4

3

2

1

0

PUI

RPI

RMI

CLI

EI

ZI

DI

CI

Bit 1 = DI: End of Demagnetization interrupt flag.

0: No End of Demagnetization interrupt pending

1: End of Demagnetization interrupt pending

Bit 7 = PUI: PWM Update Interrupt flag.

This bit is set by hardware when all the PWM

Compare register are transferred from the preload

to the active registers. The corresponding interrupt

allows the user to refresh the preload registers be-

fore the next PWM update event defined with

MREP register.

Bit 0 = CI: Commutation / Capture interrupt flag

0: No Commutation / Capture Interrupt pending

1: Commutation / Capture Interrupt pending

0: No PWM Update interrupt pending

1: PWM Update Interrupt pending

Note 1: Loading value FFh in the MISR register

will reset the PWM generator counter and transfer

the compare preload registers in the active regis-

ters by generating a U event (PUI bit set to 1). Re-

fer to “Timer Re-synchronisation” on page 202.

Bit 6 = RPI: Ratio Increment interrupt flag.

Autoswitched mode (SWA bit =1):

0: No R+ interrupt pending

1: R+ Interrupt pending

Note 2: In Autoswitched mode (SWA=1 in the

MRCA register): As all bits in the MISR register are

status flags, they are set by internal hardware sig-

nals and must be cleared by software. Any attempt

to write them to 1 will have no effect (they will be

read as 0) without interrupt generation.

Switched mode (SWA bit =0):

0: No R+ action

1: The hardware will increment the ST[3:0] bits

when the next commutation occurs and shift all

timer registers right.

Speed Sensor mode (SWA bit =x, TES[1:0] bits

=01, 10, 11):

0: No R+ interrupt pending

1: R+ Interrupt pending

When several MTC interrupts are enabled at the

same time the BRES instruction must not be used

to avoid unwanted clearing of status flags: if a sec-

ond interrupt occurs while BRES is executed

(which performs a read-modify-write sequence) to

clear the flag of a first interrupt, the flag of the sec-

ond interrupt may also be cleared and the corre-

sponding interrupt routine will not be serviced. It is

thus recommended to use a load instruction to

clear the flag, with a value equal to the logical

complement of the bit. For instance, to clear the

PUI flag:

Bit 5 = RMI: Ratio Decrement interrupt flag.

Autoswitched mode (SWA bit =1):

0: No R- interrupt pending

1: R- Interrupt pending

Switched mode (SWA bit =0):

0: No R- action

1: The hardware will decrement the ST[3:0] bits

when the next commutation occurs and shift all

timer registers left.

ld MISR, # 0x7F.

In Switched mode (SWA=0 in the MRCA regis-

ter):

Speed Sensor mode (SWA bit =x, TES[1:0] bits

=01, 10, 11):

0: No R- interrupt pending

1: R- Interrupt pending

To avoid any losing any interrupts when modifying

the RMI and RPI bits the following instruction se-

quence is recommended:

ld MISR, # 0x9F ; reset both RMI & RPI bits

ld MISR, # 0xBF ; set RMI bit

Bit 4 = CLI: Current Limitation interrupt flag.

0: No Current Limitation interrupt pending

1: Current Limitation interrupt pending

ld MISR, # 0xDF ; set RPI bit

Bit 3 = EI: Emergency stop Interrupt flag.

0: No Emergency stop interrupt pending

205/294

1

ST7MC1/ST7MC2

MOTOR CONTROLLER (Cont’d)

CONTROL REGISTER A (MCRA)

Read/Write

Reset Value: 0000 0000 (00h)

Table 56. Output configuration summary

CKE MOE DAC Peripheral

Effect on MCOx

Output

bit bit

bit

Clock

0

x

Disabled

Reset state

7

6

5

4

3

2

1

0

Peripheral frozen (see

note 1 below)

0

1

0

Disabled

MOE CKE

SR

DAC V0C1 SWA

PZ

DCB

Direct access via

MPHST

0

1

Disabled

Bit 7 = MOE: Output Enable bit.

0: Outputs disabled

1: Outputs enabled

(only logical level)

Reset state

1

0

1

x

Enabled

Standard

0

MCO[5:0] Output pin

State

running mode.

MOE bit

Direct access via

MPHST (PWM can be

applied)

0

1

Reset state

1

Enabled

Output enabled

Note 1: “Peripheral frozen” configuration is not

recommended, as the peripheral may be stopped

in a unknown state (depending on PWM generator

outputs,etc.). It is better practice to exit from run

mode by first setting output state (by toggling ei-

ther MOE or DAC bits) and then to disabling the

clock if needed.

Notes:

– The reset state is either high impedance, high or

low state depending on the corresponding option

bit.

– When the MOE bit in the MCRA register is reset

(MCOx outputs in reset state), and the SR bit in

the MCRA register is reset (sensorless mode)

and the SPLG bit in the MCRC register is reset

(sampling at PWM frequency) then, depending

on the state of the ZSV bit in the MSCR register,

Z event sampling can run or be stopped (and D

event is sampled).

Note 2: In Direct Access Mode (DAC=1), when

CKE=0 (Peripheral Clock disabled) only logical

level can be applied on the MCOx outputs when

they are enabled whereas when CKE=1 (Peripher-

al Clock enabled), a PWM signal can be applied

on them. Refer to Table 75, “DeadTime generator

set-up,” on page 217

Bit 6 = CKE: Clock Enable Bit.

0: Motor Control peripheral Clocks disabled

1: Motor Control peripheral Clocks enabled

Note 3: When clocks are disabled (CKE bit reset)

while outputs are enabled (MOE bit set), the ef-

fects on the MCOx outputs where PWM signal is

applied depend on the running mode selected:

Note: Clocks disabled means that all peripheral in-

ternal clocks (Delay manager, internal sampling

clock, PWM generator) are disabled. Therefore,

the peripheral can no longer detect events and the

preload registers do not operate.

– in voltage mode (VOC1 bit=0), the MCOx out-

puts where PWM signal is applied stay at level 1.

– in current mode (VOC1 bit=1), the MCOx outputs

where PWM signal is applied are put to level 0.

When Clocks are disabled, write accesses are al-

lowed, so for example, MTIM counter register can

be reset by software.

In all cases, MCOx outputs where a level 1 was

applied before disabling the clocks stay at level 1.

That is why it is recommended to disable the

MCOx outputs (reset MOE bit) before disabling the

clocks. This will put all the MCOx outputs under re-

set state defined by the corresponding option bit.

206/294

1

ST7MC1/ST7MC2

MOTOR CONTROLLER (Cont’d)

Effect on PWM generator: the PWM generator

12-bit counter is reset as soon as CKE = 0; this en-

sures that the PWM signals start properly in all

cases. When these bits are set, all registers with

preload on Update event are transferred to active

registers.

Table 58. DAC Bit Meaning

MOE

bit

DAC

bit

Effect on Output

Reset state depending on the option

bit

0

1

x

Standard

0

running mode.

Bit 5 = SR: Sensor ON/OFF.

0: Sensorless mode

1: Position Sensor mode

MPHST register value (depending on

MPOL, MPAR register values and

PWM setting) see Table 75

1

Table 57. Sensor Mode Selection

Bit 3 = V0C1: Voltage/Current Mode

0: Voltage Mode

1: Current Mode

SR

bit

OS[2:0]

bits

Behaviour of the output

PWM

Mode

“Between C &D” behaviour,

n

OS[2:0]

bits

enabled

Sensors

not used

“between D&Z” behaviour

0

1

and “between Z&C ” be-

n+1

Bit 2 = SWA: Switched/Autoswitched Mode

0: Switched Mode

1: Autoswitched Mode

haviour

“Between C &Z” behaviour

n

Sensors

used

OS1

disabled

and “between Z&C ” be-

n+1

Table 59. Switched and Autoswitched Modes

haviour

SWA

bit

MCOMP Register

access


型号：	ST7FMC2R6T6
厂家：	ST
描述：	8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, BRUSHLESS MOTOR CONTROL, FIVE TIMERS, SPI, LINSCI 8位MCU嵌套中断，闪存， 10位ADC ，无刷电机控制， 5个定时器， SPI ， LINSCI 闪存电动机控制电机
文件：	总294页 (文件大小：4989K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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