ST7FOXF1M6 [STMICROELECTRONICS]
Low cost flash 8bit micro;
| 型号： | ST7FOXF1M6 |
| 厂家： | 
ST |
| 描述： | Low cost flash 8bit micro 时钟 微控制器 光电二极管 外围集成电路 |
| 文件： | 总226页 (文件大小：1917K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ST7FOXF1, ST7FOXK1, ST7FOXK2
8-bit MCU with single voltage Flash memory,
SPI, I²C, ADC, timers
Features
■ Memories
– 4 to 8 Kbytes single voltage extended Flash
(XFlash) Program memory with
Read-Out Protection
In-Circuit Programming and In-Application
programming (ICP and IAP)
Endurance: 1K write/erase cycles
guaranteed
LQFP32
SDIP32
DIP20
SO20
■ 6 timers
– Configurable watchdog timer
Data retention: 20 years at 55 °C
– Dual 8-bit Lite timers with prescaler,
1 real time base and 1 input capture
– 384 bytes RAM
– Dual 12-bit Auto-reload timers with 4 PWM
outputs, input capture, output compare,
dead-time generation and enhanced one
pulse mode functions
■ Clock, Reset and Supply Management
– Low voltage supervisor (LVD) for safe
power-on/off
– Clock sources: Internal trimmable 8 MHz
RC oscillator, auto wakeup internal low
power - low frequency oscillator,
– One 16-bit timer
■ Communication interfaces:
– I²C multimaster interface
crystal/ceramic resonator or external clock
– External reset source and watchdog reset
– SPI synchronous serial interface
– Five power saving modes: Halt, Active-Halt,
Auto Wakeup from Halt, Wait and Slow
■ A/D converter: up to 10 input channels
■ Interrupt management
■ I/O Ports
– 13 interrupt vectors plus TRAP and RESET
– Up to 24 multifunctional bidirectional I/Os
– Up to 8 high sink outputs
■ Instruction set
– 8-bit data manipulation
– 63 basic instructions with illegal opcode
detection
– 17 main addressing modes
– 8 x 8 unsigned multiply instructions
■ Development tools
– Full HW/SW development package
– DM (Debug Module)
February 2008
Rev 4
1/226
www.st.com
1
Contents
ST7FOXF1, ST7FOXK1, ST7FOXK2
Contents
1
2
3
4
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Register and memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Flash programmable memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.1
4.2
4.3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Programming modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.3.1
4.3.2
In-Circuit Programming (ICP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
In Application Programming (IAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.4
4.5
ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.5.1
4.5.2
Read-out protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Flash write/erase protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.6
4.7
Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Description of Flash Control/Status register (FCSR) . . . . . . . . . . . . . . . . 28
5
Central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.1
5.2
5.3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Index registers (X and Y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Condition Code register (CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6
Supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.1
RC oscillator adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.1.1
6.1.2
6.1.3
Internal RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Customized RC calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Auto wakeup RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
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Contents
6.2
Multi-oscillator (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.2.1
6.2.2
6.2.3
External clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Crystal/ceramic oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Internal RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.3
Reset sequence manager (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Asynchronous external RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
External power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Internal Low Voltage Detector (LVD) reset . . . . . . . . . . . . . . . . . . . . . . . 42
Internal watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
6.4
6.5
System Integrity management (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6.4.1
Low Voltage Detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
6.5.1
6.5.2
6.5.3
6.5.4
6.5.5
6.5.6
RC calibration control/status register (RCC_CSR) . . . . . . . . . . . . . . . . 46
Main Clock Control/Status Register (MCCSR) . . . . . . . . . . . . . . . . . . . 46
RC Control Register High (RCCRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
RC Control Register Low (RCCRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Prescaler register (PSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Clock controller control/status register (CKCNTCSR) . . . . . . . . . . . . . . 49
7
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
7.1
7.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Masking and processing flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
7.2.1
7.2.2
Servicing pending interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Interrupt vector sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
7.3
7.4
7.5
Interrupts and low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Concurrent and nested management . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Description of interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
7.5.1
7.5.2
7.5.3
CPU CC register interrupt bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Interrupt software priority registers (ISPRx) . . . . . . . . . . . . . . . . . . . . . . 56
External Interrupt Control register (EICR) . . . . . . . . . . . . . . . . . . . . . . . 60
8
Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
8.1
8.2
8.3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
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8.4
8.5
Active-halt and halt modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
8.4.1
8.4.2
Active-halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Auto-wakeup from Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
8.5.1
8.5.2
8.5.3
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
AWUFH Control/Status Register (AWUCSR) . . . . . . . . . . . . . . . . . . . . 70
AWUFH prescaler register (AWUPR) . . . . . . . . . . . . . . . . . . . . . . . . . . 71
9
I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
9.1
9.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
9.2.1
9.2.2
9.2.3
9.2.4
Input modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Analog alternate function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
9.3
9.4
9.5
9.6
9.7
I/O port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Unused I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Device-specific I/O port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
9.7.1
9.7.2
Standard ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Other ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
10
On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
10.1 Watchdog timer (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
10.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
10.1.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
10.1.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
10.1.4 Hardware watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
10.1.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
10.1.6 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
10.2 Dual 12-bit autoreload timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
10.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
10.2.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
10.2.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
10.2.4 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
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10.2.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
10.2.6 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
10.3 Lite timer 2 (LT2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
10.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
10.3.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
10.3.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
10.3.4 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
10.3.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
10.3.6 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
10.4 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
10.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
10.4.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
10.4.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
10.4.4 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
10.4.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
10.4.6 Summary of 16-bit timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
10.4.7 16-bit timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
10.4.8 16-bit timer register map and reset values . . . . . . . . . . . . . . . . . . . . . . 139
10.5 I2C bus interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
10.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
10.5.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
10.5.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
10.5.4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
10.5.5 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
10.5.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
10.5.7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
10.6 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
10.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
10.6.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
10.6.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
10.6.4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
10.6.5 Clock phase and clock polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
10.6.6 Error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
10.6.7 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
10.6.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
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10.6.9 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
10.7 10-bit A/D converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
10.7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
10.7.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
10.7.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
10.7.4 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
10.7.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
10.7.6 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
11
Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
11.1 ST7 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
11.1.1 Inherent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
11.1.2 Immediate mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
11.1.3 Direct modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
11.1.4 Indexed modes (No Offset, Short, Long) . . . . . . . . . . . . . . . . . . . . . . . 180
11.1.5 Indirect modes (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
11.1.6 Indirect indexed modes (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . 181
11.1.7 Relative modes (direct, indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
11.2 Instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
11.2.1 Illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
12
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
12.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
12.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
12.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
12.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
12.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
12.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
12.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
12.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
12.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
12.3.2 Operating conditions with Low Voltage Detector (LVD) . . . . . . . . . . . . 190
12.3.3 Internal RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
12.4 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
12.4.1 Supply current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
12.4.2 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
6/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
Contents
12.5 Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . 194
2
12.5.1 I C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
12.5.2 SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
12.6 Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
12.6.1 Auto wakeup from Halt oscillator (AWU) . . . . . . . . . . . . . . . . . . . . . . . 198
12.6.2 Crystal and ceramic resonator oscillators . . . . . . . . . . . . . . . . . . . . . . 199
12.7 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
12.8 EMC (electromagnetic compatibility) characteristics . . . . . . . . . . . . . . . 201
12.8.1 Functional EMS (electromagnetic susceptibility) . . . . . . . . . . . . . . . . . 201
12.8.2 EMI (Electromagnetic interference) . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
12.8.3 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 203
12.9 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
12.9.1 General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
12.9.2 Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
12.10 Control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
12.10.1 Asynchronous RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
12.11 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
13
Device configuration and ordering information . . . . . . . . . . . . . . . . . 211
13.1 Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
13.1.1 Option byte 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
13.1.2 Option byte 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
13.2 Device ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
ST7FOX failure analysis service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
13.3 Development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
13.3.1 Starter kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
13.3.2 Development and debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
13.3.3 Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
13.3.4 Order codes for development and programming tools . . . . . . . . . . . . . 215
13.4 ST7 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
14
15
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
14.1 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
7/226
List of tables
ST7FOXF1, ST7FOXK1, ST7FOXK2
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Device pin description (32-pin packages). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Device pin description (20-pin package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Flash register mapping and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Interrupt software priority truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Predefined RC oscillator calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
ST7 clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
CPU clock delay during Reset sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Reset source selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Internal RC prescaler selection bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Clock register mapping and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Interrupt software priority levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Setting the interrupt software priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Interrupt vector vs ISPRx bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Dedicated interrupt instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
ST7FOXF1/ST7FOXK1 Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
ST7FOXK2 interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Interrupt sensitivity bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Enabling/disabling active-halt and halt modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Configuring the dividing factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
AWU register mapping and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
DR Value and output pin status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
I/O port mode options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
ST7FOXF1/ST7FOXK1/ST7FOXK2 I/O port configuration . . . . . . . . . . . . . . . . . . . . . . . . 75
Effect of low power modes on I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Description of interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
PA5:0, PB7:0, PC7:4 and PC2:0 pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
PA7:6 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
PC3 pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
I/O port register mapping and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Watchdog timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Watchdog timer register mapping and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Effect of low power modes on autoreload timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Description of interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Counter clock selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Register mapping and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Effect of low power modes on Lite timer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Description of interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Lite Timer register mapping and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Effect of low power modes on 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
16-bit timer interrupt control/wakeup capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Summary of 16-bit timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
16-bit timer register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
2
Effect of low power modes on the I C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Description of interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
2
Configuration of I C delay times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
8/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
List of tables
2
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
Table 82.
Table 83.
Table 84.
Table 85.
Table 86.
Table 87.
Table 88.
Table 89.
Table 90.
Table 91.
Table 92.
Table 93.
Table 94.
Table 95.
Table 96.
Table 97.
Table 98.
Table 99.
I C register mapping and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Low power mode descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Interrupt events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
SPI Master mode SCK Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
SPI Register Map and Reset Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Effect of low power modes on the A/D converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Channel selection using CH[3:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Configuring the ADC clock speed. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
ADC register mapping and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Description of addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
ST7 addressing mode overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Instructions supporting inherent addressing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Instructions supporting inherent immediate addressing mode . . . . . . . . . . . . . . . . . . . . . 180
Instructions supporting direct, indexed, indirect and indirect indexed addressing modes 181
Instructions supporting relative modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
ST7 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Illegal opcode detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Operating characteristics with LVD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Internal RC oscillator characteristics (5.0 V calibration) . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Supply current characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
On-chip peripheral characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
2
I C interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
2
SCL frequency (multimaster I C interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
SPI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
General timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
AWU from Halt characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Crystal/ceramic resonator oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
RAM and hardware registers characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Flash program memory characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
EMS test results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
EMI emissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
General characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Output driving current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Asynchronous RESET pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
ADC accuracy with VDD = 4.5 to 5.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Startup clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Selection of the resonator oscillator range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Configuration of sector size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Development tool order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
ST7 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
20-pin plastic small outline package, 300-mil width, mechanical data . . . . . . . . . . . . . . . 220
20-pin plastic dual in-line package, 300-mil width, mechanical data . . . . . . . . . . . . . . . . 221
32-pin plastic dual in-line package, shrink 400-mil width, mechanical data . . . . . . . . . . . 222
Table 100. 32-pin low profile quad flat package (7x7), package mechanical data . . . . . . . . . . . . . . . 223
9/226
List of tables
ST7FOXF1, ST7FOXK1, ST7FOXK2
Table 101. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Table 102. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
10/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
General block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
32-pin SDIP package pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
32-pin LQFP 7x7 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
20-pin SO and DIP package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
ST7FOXF1/ST7FOXK1/ST7FOXK2 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Typical ICC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Stack manipulation example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
RCCRH_USER and RCCRL_USER programming flowchart. . . . . . . . . . . . . . . . . . . . . . . 35
Figure 10. RC user calibration programming cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 11. Clock switching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 12. Clock management block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 13. Reset sequence phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 14. Reset block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 15. Reset sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 16. Low voltage detector vs reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 17. Reset and supply management block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 18. Interrupt processing flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 19. Priority decision process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 20. Concurrent interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 21. Nested interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 22. Power saving mode transitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 23. Slow mode clock transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 24. Wait mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 25. Active-halt timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 26. Active-halt mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 27. Halt timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 28. Halt mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 29. AWUFH mode block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 30. AWUF halt timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 31. AWUFH mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 32. I/O port general block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 33. Interrupt I/O port state transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 34. Watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 35. Single timer mode (ENCNTR2=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 36. Dual timer mode (ENCNTR2=1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 37. PWM polarity inversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 38. PWM function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 39. PWM signal from 0% to 100% duty cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 40. Dead time generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 41. ST7FOXF1/ST7FOXK1 Block diagram of break function. . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 42. ST7FOXK2 Block diagram of break function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 43. Block diagram of output compare mode (single timer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 44. Block diagram of input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 45. Input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 46. Long range input capture block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 47. Long range input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 48. Block diagram of one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
11/226
List of figures
ST7FOXF1, ST7FOXK1, ST7FOXK2
Figure 49. One pulse mode and PWM timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 50. Dynamic DCR2/3 update in one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 51. Force overflow timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 52. Lite timer 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Figure 53. Input Capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 54. Watchdog timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Figure 55. Timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Figure 56. 16-bit read sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Figure 57. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Figure 58. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Figure 59. Counter timing diagram, internal clock divided by 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Figure 60. Input capture block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Figure 61. Input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Figure 62. Output compare block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Figure 63. Output compare timing diagram, f
Figure 64. Output compare timing diagram, f
= f
= f
/2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
/4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
TIMER
CPU
TIMER
CPU
Figure 65. One pulse mode sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Figure 66. One pulse mode timing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Figure 67. Pulse width modulation mode timing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Figure 68. Pulse width modulation cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
2
Figure 69. I C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
2
Figure 70. I C interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Figure 71. Transfer sequencing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Figure 72. Event flags and interrupt generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Figure 73. Serial peripheral interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Figure 74. Single master/ single slave application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Figure 75. Generic SS timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Figure 76. Hardware/software slave select management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Figure 77. Data clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Figure 78. Clearing the WCOL bit (write collision flag) software sequence . . . . . . . . . . . . . . . . . . . . 166
Figure 79. Single master / multiple slave configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Figure 80. ADC block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Figure 81. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Figure 82. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Figure 83. SPI slave timing diagram with CPHA=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Figure 84. SPI slave timing diagram with CPHA=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Figure 85. SPI master timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Figure 86. Typical application with an external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Figure 87. Typical application with a crystal or ceramic resonator. . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Figure 88. Two typical applications with unused I/O pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Figure 89. RESET pin protection when LVD is enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Figure 90. RESET pin protection when LVD is disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Figure 91. Typical application with ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Figure 92. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Figure 93. ST7FOXF1/ST7FOXK1/ST7FOXK2 ordering information scheme . . . . . . . . . . . . . . . . . 214
Figure 94. 20-pin plastic small outline package, 300-mil width, package outline. . . . . . . . . . . . . . . . 220
Figure 95. 20-pin plastic dual in-line package, 300-mil width, package outline . . . . . . . . . . . . . . . . . 221
Figure 96. 32-pin plastic dual in-line package, shrink 400-mil width, package outline. . . . . . . . . . . . 222
Figure 97. 32-pin low profile quad flat package (7x7), package outline. . . . . . . . . . . . . . . . . . . . . . . 223
12/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
Description
1
Description
The ST7FOX is a member of the ST7 microcontroller family. All ST7 devices are based on a
common industry-standard 8-bit core, featuring an enhanced instruction set.
The device is positioned at the entry level of the 8-bit microcontroller range providing an
attractive cost while at the same time embedding the most advanced features.
The ST7FOX features Flash memory with byte-by-byte In-Circuit Programming (ICP) and In-
Application Programming (IAP) capability.
Under software control, the ST7FOX device can be placed in Wait, Slow, or Halt mode,
reducing power consumption when the application is in idle or standby state.
The enhanced instruction set and addressing modes of the ST7 offer both power and
flexibility to software developers, enabling the design of highly efficient and compact
application code. In addition to standard 8-bit data management, all ST7 microcontrollers
feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes.
The ST7FOX features an on-chip Debug Module (DM) to support In-Circuit Debugging
(ICD). For a description of the DM registers, refer to the ST7 ICC Protocol Reference
Manual.
Table 1.
Device summary
Features
ST7FOXF1 / ST7FOXK1
ST7FOXK2
Program memory - bytes
RAM (stack) - bytes
4K
8K
384 (128)
Dual 8-bit timer,
dual 12-bit AT (4 PWM)
Dual 8-bit timer, dual 12-bit AT
(4 PWM), 1 x 16-bit timer
Timers
ADC
1 x 10-bit
Peripherals
Packages
I²C
I²C and SPI
DIP20, SO20, LQFP32, SDIP32
LQFP32, SDIP32
13/226
Description
ST7FOXF1, ST7FOXK1, ST7FOXK2
Figure 1.
General block diagram
CLKIN
OSC1
/ 2
16-bit timer 1)
Ext.
OSC
1 MHz
to
/ 2
12-bit
Auto-reload
dual timer
OSC2
Internal
clock
16 MHz
Int.
8 MHz
RC OSC
8-bit
dual Lite timer
Int.
32 kHz
RC OSC
PA7:0
Port A
(8 bits)
PB7:0
Port B
(8 bits)
LVD
PC7:0
Port C
(8 bits)
VDD
VSS
Power
Supply
10-bit ADC
SPI 1)
RESET
Control
8-bit core
ALU
I2C
Flash
Program
Memory
Watchdog
(4 to 8 Kbytes)
Debug module
RAM
(384 bytes)
Note 1 : available on 8K version only
14/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
Pin description
2
Pin description
Figure 2.
32-pin SDIP package pinout
1
ei2
32
31
30
29
28
BREAK1/PC7
OCMP1_A1)/PA0(HS)
ATIC/PA1(HS)
PC6
PC5/BREAK2
PC4/LTIC
2
ei2
3
4
ATPWM0/PA2(HS)
ATPWM1/PA3(HS)
ATPWM2/MCO/PA4(HS)
ATPWM3/PA5(HS)
I2CDATA/PA6(HS)
I2CCLK/PA7(HS)
RESET
PC3/ICCCLK
PC2/ICCDATA
PC1/AIN9/ICAP2_A1)
PC0/AIN8/ICAP1_A1)
5
ei0
6
ei2 27
26
7
PB7/AIN7/SS/OCMP2_A1)
PB6/AIN6/SCK1)
8
25
9
24
PB5/AIN5/EXTCLK_A1)
10
11
12
13
14
15
16
23
NC
VDD
VSS
PB4/AIN4/MISO1)
PB3/AIN3/MOSI1)
PB2/AIN2
22
ei1
21
20
19
18
17
OSC1/CLKIN
OSC2
PB1/AIN1/CLKIN
PB0/AIN0
VDDA
VSSA
(HS) 20mA high sink capability
eix associated external interrupt vector
Note 1: Available on 8K version only
Figure 3.
32-pin LQFP 7x7 package pinout
32 31 30 29 28 27 26 25
24
1
2
3
4
5
6
7
8
ATPWM1/PA3(HS)
PC2/ICCDATA
23
22
21
20
19
18
17
ei2
ATPWM2/MCO/PA4(HS)
ATPWM3/PA5(HS)
I2CDATA/PA6(HS)
PC1/AIN9/ICAP2_A
PC0/AIN8/ICAP1_A
PB7/AIN7/SS/OCMP2_A
PB6/AIN6/SCK
ei0
I2CCLK/PA7(HS)
ei1
PB5/AIN5/EXTCLK_A
PB4/AIN4/MISO
PB3/AIN3/MOSI
RESET
NC
VDD
9
10 11 12 13 14 15 16
(HS) 20mA high sink capability
eix associated external interrupt vector
15/226
Pin description
ST7FOXF1, ST7FOXK1, ST7FOXK2
Legend / Abbreviations for Table 2:
Type: I = input, O = output, S = supply
In/Output level: C = CMOS 0.3V /0.7V with input trigger
T
DD
DD
Output level: HS = 20 mA high sink (on N-buffer only)
Port and control configuration:
■
■
Input: float = floating, wpu = weak pull-up, int = interrupt, ana = analog
Output: OD = open drain, PP = push-pull
The RESET configuration of each pin is shown in bold which is valid as long as the device is
in reset state.
Table 2.
Device pin description (32-pin packages)
Pin
number
Level
Port/control
Input
Main
function
(after
Alternate
function
Pin name
Output
reset)
Port A3
(HS)
1
2
3
4
5
6
7
8
PA3(HS)/ATPWM1
I/O CT HS
I/O CT HS
I/O CT HS
I/O CT HS
x
x
x
x
x
x
x
T
x
x
x
ATPWM1
PA4(HS)/
ATPWM2/MCO
Port A4
(HS)
ATPWM2/
MCO
ei0
Port A5
(HS)
PA5 (HS)ATPWM3
ATPWM3
PA6(HS)/
Port A6
(HS)
I2CDATA/SPI
serial clock
I2CDATA/SCK(2)
ei0
I2CCLK/SPI
slave select
(active low)
PA7(HS)/I2CCLK/SS
Port A7
(HS)
5
9
I/O CT HS
x
T
x
(2)
6
8
9
10
12
13
RESET
x
Reset
(3)
VDD
S
S
Digital Supply Voltage
Digital Ground Voltage
(3)
VSS
Resonator oscillator
inverter input or External
clock input
10
14
OSC1/CLKIN
I
11
12
13
15
16
17
OSC2
O
S
S
Resonator oscillator output
Analog Ground Voltage
Analog Supply Voltage
(3)
VSSA
(3)
VDDA
16/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
Pin description
Table 2.
Device pin description (32-pin packages) (continued)
Level Port/control
Input
Pin
number
Main
function
(after
Alternate
function
Pin name
Output
reset)
14
15
16
18
19
20
PB0/AIN0
PB1/AIN1/CLKIN
PB2/AIN2
I/O CT
x
x
x
x
x
x
x
x
x
x
x
x
Port B0
Port B1
Port B2
AIN0
AIN1/Externa
l clock source
I/O CT
I/O CT
AIN2
AIN3/SPI
Master out
/Slave in data
17
18
21
22
PB3/AIN3/MOSI(2)
I/O CT
x
x
x
x
x
x
x
x
Port B3
Port B4
AIN4/SPI
Master
in/Slave out
data
PB4/AIN4/MISO(2)
I/O CT
ei1
PB5/AIN5/
AIN5/TimerA
input clock
19
20
23
24
I/O CT
I/O CT
x
x
x
x
x
x
x
x
Port B5
Port B6
EXTCLK_A(2)
AIN6/SPI
serial clock
PB6/AIN6/SCK(2)
AIN7/SPI
slave select
(active low)/
Timer A
PB7/AIN7/SS(2)
OCMP2_A(2)
/
21
25
I/O CT
x
x
x
x
Port B7
Output
Compare 2
AIN8/TimerA
Input
Capture 1
PC0/AIN8/
ICAP1_A(2)
22
23
26
27
I/O CT
I/O CT
x
x
x
x
x
x
x
x
Port C0
Port C1
ei2
AIN9/TimerA
Input
Capture 2
PC1/AIN9/
ICAP2_A(2)
24
25
26
27
28
29
28
29
30
31
32
1
PC2/ICCDATA
PC3/ICCCLK
PC4/LTIC
I/O CT
I/O CT
I/O CT
I/O CT
I/O CT
I/O CT
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Port C2
Port C3
Port C4
Port C5
ICCDATA
ICCCLK
LTIC
x
PC5/BREAK2(4)
BREAK2
PC6
ei2
Port C6
Port C7 BREAK1
PC7/BREAK1
17/226
Pin description
ST7FOXF1, ST7FOXK1, ST7FOXK2
Table 2.
Device pin description (32-pin packages) (continued)
Level Port/control
Pin
number
Main
function
(after
Alternate
function
Pin name
Input
Output
reset)
PA0
HS
Port A0 (HS)(5)/ Timer A
30
31
32
2
3
4
I/O CT
x
x
x
x
x
x
x
x
x
(5)
(HS)(5)/OCMP1_A(2)
Output Compare 1
Port A1
ATIC
PA1 (HS)/ATIC
I/O CT HS
ei0
(HS)
Port A2
ATPWM0
(HS)
PA2 (HS)/ATPWM0 I/O CT HS
1. In the open-drain output column, T defines a true open-drain I/O (P-Buffer and protection diode to VDD are not
implemented).
2. Available on ST7FOXK2 only.
3. It is mandatory to connect all available VDD and VDDA pins to the supply voltage and all VSS and VSSA pins to ground.
4. BREAK2 available on ST7FOXK2 only
5. Available on ST7FOXK1 only.
Figure 4.
20-pin SO and DIP package pinout
ei2
ei2
ei2
PC6
ATIC/PA1(HS)
ATPWM0/PA2(HS)
ATPWM1/PA3(HS)
ATPWM2/MCO/PA4(HS)
ATPWM3/PA5(HS)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
PC4/LTIC
PC3/ICCCLK
PC2/ICCDATA
PB5/AIN5
PB4/AIN4
PB3/AIN3
ei0
ei1
I2CDATA/PA6(HS)
I2CCLK/PA7(HS)
PB2/AIN2
PB1/AIN1/CLKIN
RESET
VSS
PB0/AIN0
VDD
(HS) 20mA high sink capability
eix associated external interrupt vector
Legend / Abbreviations for Table 3: Type: I = input, O = output, S = supply
In/Output level:C = CMOS 0.3V /0.7V with input trigger
T
DD
DD
Output level: HS = 20mA high sink (on N-buffer only)
Port and control configuration:
■
■
Input: float = floating, wpu = weak pull-up, int = interrupt, ana = analog
Output: OD = open drain, PP = push-pull
Note:
The RESET configuration of each pin is shown in bold which is valid as long as the device is
in reset state.
18/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
Pin description
Table 3.
Device pin description (20-pin package)
Level Port / Control
Output (1)
Main
function
(after reset)
Pin
Number
Alternate
function
Input
Pin Name
1
2
3
4
PC6
PA1 (HS)/ATIC
I/O CT
I/O CT HS
x
x
x
x
ei2
ei0
x
x
x
x
x
x
x
x
Port C6
Port A1 (HS)
Port A2 (HS)
Port A3 (HS)
ATIC
PA2 (HS)/ATPWM0 I/O CT HS
PA3 (HS)/ATPWM1 I/O CT HS
ATPWM0
ATPWM1
PA4
5
I/O CT HS
(HS)ATPWM2/MCO
x
x
x
x
Port A4 (HS) ATPWM2/MCO
6
7
PA5 (HS)ATPWM3
PA6 (HS)/I2CDATA
PA7 (HS)/ I2CCLK
RESET
I/O CT HS
I/O CT HS
I/O CT HS
x
x
x
x
T
T
x
Port A5 (HS)
Port A6 (HS)
Port A7 (HS)
ATPWM3
I2CDATA
I2CCLK
8
9
x
Reset
(3)
10
11
12
VSS
S
Digital Ground Voltage
Digital Supply Voltage
(2)
VDD
S
PB0/AIN0
I/O CT
x
x
x
x
x
x
x
x
Port B0
Port B1
AIN0
AIN1/External
clock source
13
PB1/AIN1/CLKIN
I/O CT
14
15
16
17
18
19
20
PB2/AIN2
I/O CT
I/O CT
I/O CT
I/O CT
I/O CT
I/O CT
I/O CT
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Port B2
Port B3
Port B4
Port B5
Port C2
Port C3
Port C4
AIN2
AIN3
ei1
PB3/AIN3
PB4/AIN4
AIN4
PB5/AIN5
AIN5
PC2/ICCDATA
PC3/ICCCLK
PC4/LTIC
ei2
ei2
ICCDATA
ICCCLK
LTIC
1. In the open-drain output column, T defines a true open-drain I/O (P-Buffer and protection diode to VDD not implemented).
2. It is mandatory to connect all available VDD and VDDA pins to the supply voltage and all VSS and VSSA pins to ground.
19/226
Register and memory mapping
ST7FOXF1, ST7FOXK1, ST7FOXK2
3
Register and memory mapping
As shown in Figure 5, the MCU is capable of addressing 64 Kbytes of memories and I/O
registers.
The available memory locations consist of 128 bytes of register locations, 384 bytes of RAM
and 4 to 8 Kbytes of Flash program memory. The RAM space includes up to 128 bytes for
the stack from 180h to 1FFh.
The highest address bytes contain the user reset and interrupt vectors.
The Flash memory contains two sectors (see Figure 5) mapped in the upper part of the ST7
addressing space so the reset and interrupt vectors are located in Sector 0 (FFE0h-FFFFh).
The size of Flash Sector 0 and other device options are configurable by option bytes (refer
to Section 13.1 on page 211).
Caution:
Memory locations marked as “Reserved” must never be accessed. Accessing a reserved
area can have unpredictable effects on the device.
Figure 5.
ST7FOXF1/ST7FOXK1/ST7FOXK2 memory map
0000h
HW registers
(seeTable 8)
0080h
007Fh
0080h
Short Addressing
RAM (zero page)
00FFh
RAM
(384 bytes)
0100h
RAM
017Fh
0180h
1000h
1001h
01FFh
0200h
RCCRH_USER
RCCRL_USER
128 bytes Stack
01FFh
Reserved
DEE0h
DEE1h
RCCRH
RCCRL
Reserved
DFFFh
E000h
see Section 6.1.1
8 or 4 Kbytes
Flash program memory
Flash Memory
(8 Kbytes)
EFFFh
F000h
E000h
Sector 1
Sector 0
(4 Kbytes)
F7FFh
F800h
(4 Kbytes)
(2 Kbytes)
(1 Kbyte)
FFDFh
FFE0h
Interrupt & Reset Vectors
(see Table 17)
FFFFh
(0.5 Kbyte)
FFFFh
20/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
Register and memory mapping
(1)
Table 4.
Address
Hardware register map
Block
Register label
Register name
Reset status
Remarks
0000h
0001h
0002h
PADR
PADDR
PAOR
Port A Data register
Port A Data Direction register
Port A Option register
00h
00h
00h
R/W
R/W
R/W
Port A
0003h
0004h
0005h
PBDR
PBDDR
PBOR
Port B Data register
Port B Data Direction register
Port B Option register
00h
00h
00h
R/W
R/W
R/W
Port B
Port C
0006h
0007h
0008h
PCDR
PCDDR
PCOR
Port C Data register
Port C Data Direction register
Port C Option register
00h
00h
08h
R/W
R/W
R/W
0009h to
000Bh
Reserved area (3 bytes)
000Ch
000Dh
000Eh
000Fh
0010h
LTCSR2
LTARR
LTCNTR
LTCSR1
LTICR
Lite Timer Control/Status register 2
Lite Timer Auto-reload register
Lite Timer Counter register
Lite Timer Control/Status register 1
Lite Timer Input Capture register
0Fh
00h
00h
R/W
R/W
Read Only
R/W
LITE
TIMER
0x00 0000b
xxh
Read Only
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
0019h
001Ah
001Bh
001Ch
001Dh
001Eh
001Fh
0020h
0021h
0022h
0023h
0024h
0025h
0026h
0027h
0028h
0029h
002Ah
ATCSR
CNTR1H
CNTR1L
ATR1H
Timer Control/Status register
Counter register 1 High
0x00 0000b
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
03h
00h
00h
00h
00h
03h
R/W
Read Only
Read Only
R/W
Counter register 1 Low
Auto-Reload register 1 High
Auto-Reload register 1 Low
PWM Output Control register
PWM 0 Control/Status register
PWM 1 Control/Status register
PWM 2 Control/Status register
PWM 3 Control/Status register
PWM 0 Duty Cycle register High
PWM 0 Duty Cycle register Low
PWM 1 Duty Cycle register High
PWM 1 Duty Cycle register Low
PWM 2 Duty Cycle register High
PWM 2 Duty Cycle register Low
PWM 3 Duty Cycle register High
PWM 3 Duty Cycle register Low
Input Capture register High
Input Capture register Low
Timer Control/Status register 2
Break Control register
ATR1L
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PWMCR
PWM0CSR
PWM1CSR
PWM2CSR
PWM3CSR
DCR0H
DCR0L
DCR1H
DCR1L
DCR2H
DCR2L
DCR3H
DCR3L
ATICRH
ATICRL
ATCSR2
BREAKCR1
ATR2H
AUTO-
RELOAD
TIMER
Read Only
Read Only
R/W
R/W
R/W
R/W
R/W
Auto-Reload register 2 High
Auto-Reload register 2 Low
Dead Time Generation register
Break Enable register
ATR2L
DTGR
BREAKEN
R/W
002Bh
Reserved area (1 byte)
AUTO-
RELOAD
TIMER
002Ch
BREAKCR2 (4)
Break Control register 2 (4)
00h
R/W
21/226
Register and memory mapping
ST7FOXF1, ST7FOXK1, ST7FOXK2
(1)
Table 4.
Address
Hardware register map (continued)
Block
Register label
Register name
Reset status
Remarks
002Dh
002Eh
002Fh
0030h
0031h
ISPR0
ISPR1
ISPR2
ISPR3
EICR
Interrupt Software Priority register 0
Interrupt Software Priority register 1
Interrupt Software Priority register 2
Interrupt Software Priority register 3
External Interrupt Control register
FFh
FFh
FFh
FFh
00h
R/W
R/W
R/W
R/W
R/W
ITC
0032h
0033h
0034h
Reserved area (1 byte)
Watchdog Control register
Flash Control/Status register
WDG
WDGCR
FCSR
7Fh
00h
R/W
R/W
FLASH
RC
Calibration
0035h
RCC_CSR
RC calibration Control/Status register
00h
R/W
0036h
0037h
0038h
ADCCSR
ADCDRH
ADCDRL
A/D Control Status register
A/D Data register High
A/D Data Low / test register
00h
xxh
0xh
R/W
Read Only
R/W
ADC
0039h
003Ah
Reserved area (1 byte)
MCC
MCCSR
Main Clock Control/Status register
00h
R/W
003Bh
003Ch
003Dh
RCCRH
RCCRL
PSCR
RC oscillator Control register High
RC oscillator Control register Low
Prescaler register
FFh
R/W
R/W
R/W
Clock and
Reset
011x 0x00b
00h or 03h(2)
003Eh to
0047h
Reserved area (10 bytes)
0048h
0049h
AWUCSR
AWUPR
AWU Control/Status register
AWU Preload register
FFh
00h
R/W
R/W
AWU
004Ah
004Bh
004Ch
004Dh
004Eh
004Fh
0050h
DMCR
DMSR
DM Control register
DM Status register
00h
00h
00h
00h
00h
00h
00h
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DMBK1H
DMBK1L
DMBK2H
DMBK2L
DMCR2
DM Breakpoint register 1 High
DM Breakpoint register 1 Low
DM Breakpoint register 2 High
DM Breakpoint register 2 Low
DM Control register 2
DM(3)
Clock
Controller
0051h
CKCNTCSR
Clock Controller Status register
Reserved area (3 bytes)
09h
R/W
0052h to
0054h
22/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
Register and memory mapping
(1)
Table 4.
Address
Hardware register map (continued)
Block
Register label
Register name
Reset status
Remarks
TACR2
TACR1
TACSR
TAICHR1
TAICLR1
TAOCHR1
TAOCLR1
TACHR
0055h
0056h
0057h
0058h
0059h
005Ah
005Bh
005Ch
005Dh
005Eh
005Fh
0060h
0061h
0062h
0063h
Timer A Control register 2
Timer A Control register 1
Timer A Control/status register
00h
00h
00h
xxh
xxh
80h
00h
FFh
FCh
FFh
FCh
xxh
xxh
80h
00h
R/W
R/W
Read Only
Read Only
Read Only
R/W
Timer A Input capture 1 high register
Timer A Input capture 1 low register
Timer A Output compare 1 high register
Timer A Output compare 1 low register
Timer A Output counter high register
Timer A Output counter low register
Timer A Alternate counter high register
Timer A Alternate counter low register
Timer A Input capture 2 high register
Timer A Input capture 2 low register
Timer A Output compare 2 high register
Timer A Output compare 2 low register
R/W
16-bit
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
R/W
Timer(4)
TACLR
TAACHR
TAACLR
TAICHR2
TAICLR2
TAOCHR2
TAOCLR2
R/W
R/W
Read only
Read only
R/W
0064h
0065h
0066h
0067h
0068h
0069h
006Ah
I2CCR
I2CSR1
I2CSR2
I2CCCR
I2COAR1
I2COAR2
I2CDR
I2C Control register
I2C Status register 1
00h
00h
00h
00h
00h
40h
00h
I2C Status register 2
I2C
I2C Clock Control register
I2C Own Address register 1
I2C Own Address register 2
I2C Data register
R/W
R/W
R/W
0070h
0071h
0072h
SPIDR
SPICR
SPISR
SPI Data register
SPI Control register
SPI Status register
0xh
00h
xxh
R/W
R/W
R/W
SPI(4)
1. Legend: x=undefined, R/W=read/write.
2. Reset status is 03h for ST7FOXK2 and 00h for ST7FOXF1 and ST7FOXK1
3. For a description of the Debug Module registers, see ICC protocol reference manual.
4. Available on ST7FOXK2 only
23/226
Flash programmable memory
ST7FOXF1, ST7FOXK1, ST7FOXK2
4
Flash programmable memory
4.1
Introduction
The ST7 single voltage extended Flash (XFlash) is a non-volatile memory that can be
electrically erased and programmed either on a byte-by-byte basis or up to 32 bytes in
parallel.
The XFlash devices can be programmed off-board (plugged in a programming tool) or on-
board using In-Circuit Programming or In-Application Programming.
The array matrix organization allows each sector to be erased and reprogrammed without
affecting other sectors.
4.2
4.3
Main features
■
■
■
ICP (In-Circuit Programming)
IAP (In-Application Programming)
ICT (In-Circuit Testing) for downloading and executing user application test patterns in
RAM
■
■
Sector 0 size configurable by option byte
Read-out and write protection
Programming modes
The ST7 can be programmed in three different ways:
■
■
■
Insertion in a programming tool. In this mode, Flash sectors 0 and 1, option byte row
can be programmed or erased.
In-Circuit Programming. In this mode, Flash sectors 0 and 1, option byte row can be
programmed or erased without removing the device from the application board.
In-Application Programming. In this mode, sector 1 can be programmed or erased
without removing the device from the application board and while the application is
running.
4.3.1
In-Circuit Programming (ICP)
ICP uses a protocol called ICC (In-Circuit Communication) which allows an ST7 plugged on
a printed circuit board (PCB) to communicate with an external programming device
connected via cable. ICP is performed in three steps:
Switch the ST7 to ICC mode (In-Circuit Communications). This is done by driving a specific
signal sequence on the ICCCLK/DATA pins while the RESET pin is pulled low. When the
ST7 enters ICC mode, it fetches a specific Reset vector which points to the ST7 System
Memory containing the ICC protocol routine. This routine enables the ST7 to receive bytes
from the ICC interface.
■
■
Download ICP Driver code in RAM from the ICCDATA pin
Execute ICP Driver code in RAM to program the Flash memory
24/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
Flash programmable memory
Depending on the ICP Driver code downloaded in RAM, Flash memory programming can
be fully customized (number of bytes to program, program locations, or selection of the
serial communication interface for downloading).
4.3.2
In Application Programming (IAP)
This mode uses an IAP Driver program previously programmed in Sector 0 by the user (in
ICP mode).
This mode is fully controlled by user software. This allows it to be adapted to the user
application, (user-defined strategy for entering programming mode, choice of
communications protocol used to fetch the data to be stored etc.)
IAP mode can be used to program any memory areas except Sector 0, which is Write/Erase
protected to allow recovery in case errors occur during the programming operation.
4.4
ICC interface
ICP needs a minimum of 4 and up to 6 pins to be connected to the programming tool. These
pins are:
■
■
■
■
■
■
RESET: device reset
: device power supply ground
V
SS
ICCCLK: ICC output serial clock pin
ICCDATA: ICC input serial data pin
OSC1: main clock input for external source
V
: application board power supply (optional, see Note 3)
DD
Note:
1
2
If the ICCCLK or ICCDATA pins are only used as outputs in the application, no signal
isolation is necessary. As soon as the Programming Tool is plugged to the board, even if an
ICC session is not in progress, the ICCCLK and ICCDATA pins are not available for the
application. If they are used as inputs by the application, isolation such as a serial resistor
has to be implemented in case another device forces the signal. Refer to the Programming
Tool documentation for recommended resistor values.
During the ICP session, the programming tool must control the RESET pin. This can lead to
conflicts between the programming tool and the application reset circuit if it drives more than
5mA at high level (push pull output or pull-up resistor<1 kΩ). A schottky diode can be used
to isolate the application RESET circuit in this case. When using a classical RC network with
R>1 kΩ or a reset management IC with open drain output and pull-up resistor>1 kΩ, no
additional components are needed. In all cases the user must ensure that no external reset
is generated by the application during the ICC session.
3
4
The use of pin 7 of the ICC connector depends on the Programming Tool architecture. This
pin must be connected when using most ST Programming Tools (it is used to monitor the
application power supply). Please refer to the Programming Tool manual.
In “enabled option byte” mode (38-pulse ICC mode), the internal RC oscillator is forced as a
clock source, regardless of the selection in the option byte. In “disabled option byte” mode
(35-pulse ICC mode), pin 9 has to be connected to the PB1/CLKIN pin of the ST7 when the
clock is not available in the application or if the selected clock option is not programmed in
the option byte.
Caution:
During normal operation the ICCCLK pin must be internally or externally pulled- up (external
pull-up of 10 kΩ mandatory in noisy environment) to avoid entering ICC mode unexpectedly
25/226
Flash programmable memory
ST7FOXF1, ST7FOXK1, ST7FOXK2
during a reset. In the application, even if the pin is configured as output, any reset will put it
back in input pull-up.
Figure 6.
Typical ICC Interface
PROGRAMMING TOOL
ICC CONNECTOR
ICC Cable
ICC CONNECTOR
HE10 CONNECTOR TYPE
(See Note 3)
OPTIONAL
APPLICATION BOARD
(See Note 4)
9
7
5
6
3
1
2
10
8
4
APPLICATION
RESET SOURCE
See Note 2
APPLICATION
POWER SUPPLY
See Note 1 and Caution
APPLICATION
I/O
See Note 1
ST7
26/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
Flash programmable memory
4.5
Memory protection
There are two different types of memory protection: Read-Out Protection and Write/Erase
Protection which can be applied individually.
4.5.1
Read-out protection
Read-Out Protection, when selected provides a protection against program memory content
extraction and against write access to Flash memory. Even if no protection can be
considered as totally unbreakable, the feature provides a very high level of protection for a
general purpose microcontroller.
■
In Flash devices, this protection is removed by reprogramming the option. In this case,
the program memory is automatically erased and the device can be reprogrammed.
The read-out protection is enabled and removed through the FMP_R bit in the option
byte.
4.5.2
Flash write/erase protection
Write/Erase Protection, when set, makes it impossible to both overwrite and erase program
memory. Its purpose is to provide advanced security to applications and prevent any change
being made to the memory content. Write/Erase Protection is enabled through the FMP_W
bit in the option byte.
Caution:
Once set, Write/Erase Protection can never be removed. A write-protected Flash
device is no longer reprogrammable.
4.6
Related documentation
For details on Flash programming and ICC protocol, refer to the ST7 Flash Programming
Reference Manual and to the ST7 ICC Protocol Reference Manual.
27/226
Flash programmable memory
ST7FOXF1, ST7FOXK1, ST7FOXK2
4.7
Description of Flash Control/Status register (FCSR)
This register controls the XFlash erasing and programming using ICP, IAP or other
programming methods.
1st RASS Key: 0101 0110 (56h)
2nd RASS Key: 1010 1110 (AEh)
When an EPB or another programming tool is used (in socket or ICP mode), the RASS keys
are sent automatically.
Reset value: 000 0000 (00h)
7
0
0
0
0
0
0
OPT
LAT
PGM
Read/write
Table 5.
Flash register mapping and reset values
Register
Address
(Hex.)
7
6
5
4
3
2
1
0
label
FCSR
-
0
-
0
-
0
-
0
-
0
OPT
0
LAT
0
PGM
0
0034
Reset Value
28/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
Central processing unit
5
Central processing unit
5.1
Introduction
This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-
bit data manipulation.
5.2
Main features
■
■
■
■
■
■
■
■
63 basic instructions
Fast 8-bit by 8-bit multiply
17 main addressing modes
Two 8-bit index registers
16-bit stack pointer
Low power modes
Maskable hardware interrupts
Non-maskable software interrupt
5.3
CPU registers
The six CPU registers shown in Figure 7. They are not present in the memory mapping and
are accessed by specific instructions.
Figure 7.
CPU registers
7
0
ACCUMULATOR
RESET VALUE = XXh
7
0
0
X INDEX REGISTER
Y INDEX REGISTER
RESET VALUE = XXh
7
RESET VALUE = XXh
PCL
PCH
7
8
15
0
PROGRAM COUNTER
CONDITION CODE REGISTER
STACK POINTER
RESET VALUE = RESET VECTOR @ FFFEh-FFFFh
7
1
0
1
1
1
1
H
X
I
N
X
Z
X
C
X
RESET VALUE =
8
1
1
15
7
0
RESET VALUE = STACK HIGHER ADDRESS
X = Undefined Value
29/226
Central processing unit
ST7FOXF1, ST7FOXK1, ST7FOXK2
5.3.1
5.3.2
Accumulator (A)
The Accumulator is an 8-bit general purpose register used to hold operands and the results
of the arithmetic and logic calculations and to manipulate data.
Index registers (X and Y)
In indexed addressing modes, these 8-bit registers are used to create either effective
addresses or temporary storage areas for data manipulation. (The Cross-Assembler
generates a precede instruction (PRE) to indicate that the following instruction refers to the
Y register.)
The Y register is not affected by the interrupt automatic procedures (not pushed to and
popped from the stack).
5.3.3
5.3.4
Program Counter (PC)
The Program Counter is a 16-bit register containing the address of the next instruction to be
executed by the CPU. It is made of two 8-bit registers PCL (Program Counter low which is
the LSB) and PCH (Program Counter high which is the MSB).
Condition Code register (CC)
The 8-bit Condition Code register contains the interrupt mask and four flags representative
of the result of the instruction just executed. This register can also be handled by the PUSH
and POP instructions.
Reset value: 111x 1xxx
7
1
0
1
I1
H
I0
Read/write
N
Z
C
These bits can be individually tested and/or controlled by specific instructions.
Arithmetic management bits
Bit 4 = H Half carry bit
This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during
an ADD or ADC instruction. It is reset by hardware during the same instructions.
0: No half carry has occurred.
1: A half carry has occurred.
This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD
arithmetic subroutines.
30/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
Central processing unit
Bit 3 = I Interrupt mask
bit
This bit is set by hardware when entering in interrupt or by software to disable all
interrupts except the TRAP software interrupt. This bit is cleared by software.
0: Interrupts are enabled.
1: Interrupts are disabled.
This bit is controlled by the RIM, SIM and IRET instructions and is tested by the JRM
and JRNM instructions.
Note:
Interrupts requested while I is set are latched and can be processed when I is cleared. By
default an interrupt routine is not interruptible because the I bit is set by hardware at the start
of the routine and reset by the IRET instruction at the end of the routine. If the I bit is cleared
by software in the interrupt routine, pending interrupts are serviced regardless of the priority
level of the current interrupt routine.
Bit 2 = N Negative bit
This bit is set and cleared by hardware. It is representative of the result sign of the last
th
arithmetic, logical or data manipulation. It is a copy of the 7 bit of the result.
0: The result of the last operation is positive or null.
1: The result of the last operation is negative (that is, the most significant bit is a logic
1).
This bit is accessed by the JRMI and JRPL instructions.
Bit 1 = Z Zero bit
This bit is set and cleared by hardware. This bit indicates that the result of the last
arithmetic, logical or data manipulation is zero.
0: The result of the last operation is different from zero.
1: The result of the last operation is zero.
This bit is accessed by the JREQ and JRNE test instructions.
bit
Bit 0 = C Carry/borrow
This bit is set and cleared by hardware and software. It indicates an overflow or an
underflow has occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.
This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC
instructions. It is also affected by the “bit test and branch”, shift and rotate instructions.
Interrupt management bits
Bits 5,3 = I1, I0 Interrupt bits
The combination of the I1 and I0 bits gives the current interrupt software priority.
These two bits are set/cleared by hardware when entering in interrupt. The loaded
value is given by the corresponding bits in the interrupt software priority registers
(IxSPR). They can be also set/cleared by software with the RIM, SIM, IRET, HALT, WFI
and PUSH/POP instructions. See Section 9.6: Interrupts for more details.
31/226
Central processing unit
ST7FOXF1, ST7FOXK1, ST7FOXK2
*
Table 6.
Interrupt software priority truth table
Interrupt software priority
I1
I0
Level 0 (main)
Level 1
1
0
0
1
0
1
0
1
Level 2
Level 3 (= interrupt disable)
5.3.5
Stack Pointer (SP)
Reset value: 01FFh
15
0
8
1
7
1
0
0
0
0
0
0
0
SP6 SP5 SP4 SP3 SP2 SP1 SP0
Read/write
The Stack Pointer is a 16-bit register which is always pointing to the next free location in the
stack. It is then decremented after data has been pushed onto the stack and incremented
before data is popped from the stack (see Figure 8).
Since the stack is 128 bytes deep, the 9 most significant bits are forced by hardware.
Following an MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer
contains its reset value (the SP6 to SP0 bits are set) which is the stack higher address.
The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD
instruction.
Note:
When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit,
without indicating the stack overflow. The previously stored information is then overwritten
and therefore lost. The stack also wraps in case of an underflow.
The stack is used to save the return address during a subroutine call and the CPU context
during an interrupt. The user may also directly manipulate the stack by means of the PUSH
and POP instructions. In the case of an interrupt, the PCL is stored at the first location
pointed to by the SP. Then the other registers are stored in the next locations as shown in
Figure 8.
■
When an interrupt is received, the SP is decremented and the context is pushed on the
stack.
■
On return from interrupt, the SP is incremented and the context is popped from the
stack.
A subroutine call occupies two locations and an interrupt five locations in the stack area.
32/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
Central processing unit
Figure 8.
Stack manipulation example
CALL
Subroutine
RET
or RSP
PUSH Y
POP Y
IRET
Interrupt
Event
@ 0180h
SP
SP
SP
Y
CC
A
CC
A
CC
A
X
X
X
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
SP
SP
PCH
PCL
PCH
PCL
SP
@ 01FFh
Stack Higher Address = 01FFh
0180h
Stack Lower Address =
33/226
Supply, reset and clock management
ST7FOXF1, ST7FOXK1, ST7FOXK2
6
Supply, reset and clock management
The device includes a range of utility features for securing the application in critical
situations (for example in case of a power brown-out), and reducing the number of external
components. The main features are the following:
■
Clock management
–
–
–
–
8 MHz internal RC oscillator (enabled by option byte)
Auto wakeup RC oscillator (enabled by option byte)
1 to 16 MHz or 32 kHz External crystal/ceramic resonator (selected by option byte)
External clock input (enabled by option byte)
■
■
Reset Sequence Manager (RSM)
System Integrity management (SI)
–
Main supply Low voltage detection (LVD) with reset generation (enabled by option
byte)
6.1
RC oscillator adjustment
6.1.1
Internal RC oscillator
The device contains an internal RC oscillator with a specific accuracy for a given device,
temperature and voltage range (4.5 V - 5.5 V). It must be calibrated to obtain the frequency
required in the application. This is done by software writing a 10-bit calibration value in the
RCCRH (RC Control register High) and in the bits 6:5 in the RCCRL (RC Control register
Low).
Whenever the microcontroller is reset, the RCCR returns to its default value (FFh), i.e. each
time the device is reset, the calibration value must be loaded in the RCCR. Predefined
calibration values are stored for 5 V V supply voltage at 25 °C (see Table 7).
DD
Table 7.
RCCR
Predefined RC oscillator calibration values
Conditions
ST7FOX
Address
RCCRH
RCCRL
V
DD= 5V
DEE0h(1) (CR[9:2])
DEE1h(1) (CR[1:0])
TA= 25°C
fRC = 8 MHz
1. The DEE0h and DEE1h addresses are located in a reserved area in non-volatile memory. They are read-
only bytes for the application code. This area cannot be erased or programmed by any ICC operations.
For compatibility reasons with the RCCRL register, CR[1:0] bits are stored in the 5th and 6th position of
DEE1 address.
In 38-pulse ICC mode, the internal RC oscillator is forced as a clock source, regardless of
the selection in the option byte.
Section 12: Electrical characteristics on page 187 for more information on the frequency
and accuracy of the RC oscillator.
To improve clock stability and frequency accuracy, it is recommended to place a decoupling
capacitor, typically 100 nF, between the V and V pins and also between the V and
DD
SS
DDA
V
pins as close as possible to the ST7 device.
SSA
34/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
Supply, reset and clock management
These bytes are systematically programmed by ST.
6.1.2
Customized RC calibration
If the application requires a higher frequency accuracy or if the voltage or temperature
conditions change in the application, the frequency may need to be recalibrated. Two non-
volatile bytes (RCCRH_USER and RCCRL_USER) are reserved for storing these new
values. These two-byte area is Electrically Erasable Programmable Read Only Memory.
Note:
Refer to application note AN1324 for information on how to calibrate the RC frequency using
an external reference signal.
How to program RCCRH_USER and RCCRL_USER
To access the write mode, the RCCLAT bit has to be set by software (the RCCPGM bit
remains cleared). When a write access to this two-byte area occurs, the values are latched.
When RCCPGM bit is set by the software, the latched data are programmed in the
EEPROM cells. To avoid wrong programming, the user must take care to only access these
two-byte addresses.
At the end of the programming cycle, the RCCPGM and RCCLAT bits are cleared
simultaneously.
Note:
During the programming cycle, it is forbidden to access the latched data (see Figure 9).
Figure 9.
RCCRH_USER and RCCRL_USER programming flowchart
READ MODE
RCCLAT=0
RCCPGM=0
WRITE MODE
RCCLAT=1
RCCPGM=0
WRITE THE 2 BYTES
AT THEIR ADDRESS
READ BYTES
START PROGRAMMING CYCLE
RCCLAT=1
RCCPGM=1 (set by software)
0
1
RCCLAT
CLEARED BY HARDWARE
Note:
If a programming cycle is interrupted (by a reset action), the integrity of the data in memory
is not guaranteed.
Access error handling
If a read access occurs while RCCLAT=1, then the data bus will not be driven.
If a write access occurs while RCCLAT=0, then the data on the bus will not be latched.
35/226
Supply, reset and clock management
ST7FOXF1, ST7FOXK1, ST7FOXK2
If a programming cycle is interrupted (by a RESET action), the integrity of the data in
memory will not be guaranteed.
Caution:
When the Read-Out Protection is enabled through an option bit (see Section 13.1: Option
bytes), these two bytes are protected against Read-out (including a re-write protection). In
Flash devices, when this protection is removed by reprogramming the option byte, these two
bytes are automatically erased.
Figure 10. RC user calibration programming cycle
READ OPERATION POSSIBLE
READ OPERATION NOT POSSIBLE
Internal
Programming
voltage
ERASE CYCLE
tPROG
WRITE CYCLE
WRITE OF
DATA LATCHES
Byte 1 Byte 2
RCCLAT
RCCPGM
tPROG is typically 5 ms and max 10 ms
6.1.3
Auto wakeup RC oscillator
The ST7FOX also contains an Auto wakeup RC oscillator. This RC oscillator should be
enabled to enter Auto wakeup from halt mode.
The Auto wakeup (AWU) RC oscillator can also be configured as the startup clock through
the CKSEL[1:0] option bits (see Section 13.1: Option bytes on page 211).
This is recommended for applications where very low power consumption is required.
Switching from one startup clock to another can be done in run mode as follows (see
Figure 11):
Case 1 Switching from internal RC to AWU
1. Set the RC/AWU bit in the CKCNTCSR register to enable the AWU RC oscillator
2. The RC_FLAG is cleared and the clock output is at 1.
3. Wait 3 AWU RC cycles till the AWU_FLAG is set
4. The switch to the AWU clock is made at the positive edge of the AWU clock signal
5. Once the switch is made, the internal RC is stopped
36/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
Supply, reset and clock management
Case 2 Switching from AWU RC to internal RC
1. Reset the RC/AWU bit to enable the internal RC oscillator
2. Using a 4-bit counter, wait until 8 internal RC cycles have elapsed. The counter is
running on internal RC clock.
3. Wait till the AWU_FLAG is cleared (1AWU RC cycle) and the RC_FLAG is set (2 RC
cycles)
4. The switch to the internal RC clock is made at the positive edge of the internal RC clock
signal
5. Once the switch is made, the AWU RC is stopped
Note:
1
2
When the internal RC is not selected, it is stopped so as to save power consumption.
When the internal RC is selected, the AWU RC is turned on by hardware when entering
Auto wakeup from Halt mode.
3
When the external clock is selected, the AWU RC oscillator is always on.
Figure 11. Clock switching
Set RC/AWU
Internal RC
AWU RC
AWU RC
Poll AWU_FLAG until set
Reset RC/AWU
Internal RC
Poll RC_FLAG until set
37/226
Supply, reset and clock management
ST7FOXF1, ST7FOXK1, ST7FOXK2
Figure 12. Clock management block diagram
PSCR
CK2 CK1 CK0
RCCRH
CR9 CR8 CR7 CR6 CR5 CR4 CR3
CR2
RCCRL
CR1 CR0
Tunable
RC Oscillator
CKCNTCSR
RC/AWU
8 MHz (f
)
RC
8 MHz
4 MHz
2 MHz
1 MHz
12-BIT
AT TIMER 2
f
CPU
Prescaler
AWU RC OSC
500 kHz
CLKSEL[1:0]
Option bits
Clock controller
RC OSC
CLKIN
CLKIN
CLKIN
f
OSC
/2
CLKIN/2
DIVIDER
CLKIN/2
OSC/2
CLKIN
/OSC1
OSC
1-16 MHz
or 32kHz
OSC
/2
DIVIDER
OSC2
CLKSEL[1:0]
Option bits
f
LTIMER
8-BIT
LITE TIMER 2 COUNTER
(1ms timebase @ 8 MHz f
)
OSC
f
f
/32
OSC
OSC
/32 DIVIDER
1
0
f
CPU
TO CPU AND
PERIPHERALS
f
OSC
MCCSR
MCO SMS
MCO
f
CPU
6.2
Multi-oscillator (MO)
The main clock of the ST7 can be generated by four different source types coming from the
multi-oscillator block (1 to 16 MHz):
■
■
■
An external source
5 different configurations for crystal or ceramic resonator oscillators
An internal high frequency RC oscillator
Each oscillator is optimized for a given frequency range in terms of consumption and is
selectable through the option byte. The associated hardware configurations are shown in
Table 8. Refer to the electrical characteristics section for more details.
38/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
Supply, reset and clock management
6.2.1
External clock source
In this external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle
has to drive the OSC1 pin while the OSC2 pin is tied to ground.
Note:
When the Multi-Oscillator is not used OSCI1 and OSCI2 must be tied to ground, and PB1 is
selected by default as the external clock.
6.2.2
Crystal/ceramic oscillators
In this mode, with a self-controlled gain feature, oscillator of any frequency from 1 to 16 MHz
can be placed on OSC1 and OSC2 pins. This family of oscillators has the advantage of
producing a very accurate rate on the main clock of the ST7. In this mode of the multi-
oscillator, the resonator and the load capacitors have to be placed as close as possible to
the oscillator pins in order to minimize output distortion and start-up stabilization time. The
loading capacitance values must be adjusted according to the selected oscillator.
These oscillators are not stopped during the RESET phase to avoid losing time in the
oscillator start-up phase.
6.2.3
Internal RC oscillator
In this mode, the tunable RC oscillator is used as main clock source. The two oscillator pins
have to be tied to ground.
The calibration is done through the RCCRH[7:0] and RCCRL[6:5] registers.
Table 8.
ST7 clock sources
Hardware configuration
ST7
OSC1
OSC2
EXTERNAL
SOURCE
39/226
Supply, reset and clock management
ST7FOXF1, ST7FOXK1, ST7FOXK2
Table 8.
ST7 clock sources
Hardware configuration
ST7
OSC1
OSC2
CL1
CL2
LOAD
CAPACITORS
ST7
OSC1
OSC2
6.3
Reset sequence manager (RSM)
6.3.1
Introduction
The reset sequence manager includes three RESET sources as shown in Figure 14:
■
■
■
External RESET source pulse
Internal LVD RESET (Low Voltage Detection)
Internal WATCHDOG RESET
Note:
A reset can also be triggered following the detection of an illegal opcode or prebyte code.
Refer to Section 11.2.1 on page 184 for further details.
These sources act on the RESET pin and it is always kept low during the delay phase.
The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory
mapping.
The basic RESET sequence consists of 3 phases as shown in Figure 13:
■
■
Active Phase depending on the RESET source
256 or 4096 CPU clock cycle delay (see Table 13)
Caution:
When the ST7 is unprogrammed or fully erased, the Flash is blank and the Reset vector is
not programmed. For this reason, it is recommended to keep the RESET pin in low state
until programming mode is entered, in order to avoid unwanted behavior.
The 256 or 4096 CPU clock cycle delay allows the oscillator to stabilize and ensures that
recovery has taken place from the Reset state. The shorter or longer clock cycle delay is
automatically selected depending on the clock source chosen by option byte.
The Reset vector fetch phase duration is 2 clock cycles.
40/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
Supply, reset and clock management
CPU clock cycle delay
Table 9.
CPU clock delay during Reset sequence
Clock source
Internal RC 8 MHz Oscillator
Internal RC 32 kHz Oscillator
4096
256
External clock (connected to CLKIN/PB1 pin)
4096
External Crystal/Ceramic Oscillator (connected to OSC1/OSC2 pins)
External Crystal/Ceramic 1-16 MHz Oscillator
4096
4096
256
External Crystal/Ceramic 32 kHz Oscillator
Figure 13. Reset sequence phases
RESET
Internal reset
Fetch
vector
active phase
256 or 4096 clock cycles
41/226
Supply, reset and clock management
ST7FOXF1, ST7FOXK1, ST7FOXK2
6.3.2
Asynchronous external RESET pin
The RESET pin is both an input and an open-drain output with integrated R weak pull-up
ON
resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It
can be pulled low by external circuitry to reset the device. See Electrical Characteristic
section for more details.
A RESET signal originating from an external source must have a duration of at least
t
in order to be recognized (see Figure 15: Reset sequences). This detection is
h(RSTL)in
asynchronous and therefore the MCU can enter reset state even in Halt mode.
The RESET pin is an asynchronous signal which plays a major role in EMS performance. In
a noisy environment, it is recommended to follow the guidelines mentioned in the electrical
characteristics section.
Figure 14. Reset block diagram
VDD
RON
INTERNAL
RESET
Filter
RESET
___
WATCHDOG RESET
PULSE
GENERATOR
___
___
ILLEGAL OPCODE RESET 1)
LVD RESET
1. See Section 11.2.1: Illegal opcode reset on page 184 for more details on illegal opcode reset conditions.
6.3.3
6.3.4
External power-on reset
If the LVD is disabled by option byte, to start up the microcontroller correctly, the user must
ensure by means of an external reset circuit that the reset signal is held low until V is over
the minimum level specified for the selected f
DD
frequency.
OSC
A proper reset signal for a slow rising V supply can generally be provided by an external
RC network connected to the RESET pin.
DD
Internal Low Voltage Detector (LVD) reset
Two different Reset sequences caused by the internal LVD circuitry can be distinguished:
■
■
Power-On reset
Voltage Drop reset
The device RESET pin acts as an output that is pulled low when V is lower than V
DD
IT+
(rising edge) or V lower than V (falling edge) as shown in Figure 15.
DD
IT-
The LVD filters spikes on V larger than t
to avoid parasitic resets.
g(VDD)
DD
42/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
Supply, reset and clock management
6.3.5
Internal watchdog reset
The Reset sequence generated by an internal watchdog counter overflow is shown in
Figure 15: Reset sequences
Starting from the watchdog counter underflow, the device RESET pin acts as an output that
is pulled low during at least t
.
w(RSTL)out
Figure 15. Reset sequences
VDD
VIT+(LVD)
VIT-(LVD)
LVD
RESET
EXTERNAL
RESET
WATCHDOG
RESET
RUN
RUN
RUN
RUN
ACTIVE
PHASE
ACTIVE
PHASE
ACTIVE PHASE
tw(RSTL)out
th(RSTL)in
EXTERNAL
RESET
SOURCE
RESET PIN
WATCHDOG
RESET
WATCHDOG UNDERFLOW
INTERNAL RESET (256 or 4096 T
VECTOR FETCH
)
CPU
43/226
Supply, reset and clock management
ST7FOXF1, ST7FOXK1, ST7FOXK2
6.4
System Integrity management (SI)
The System Integrity Management block contains the Low voltage Detector (LVD).
Note:
6.4.1
A reset can also be triggered following the detection of an illegal opcode or prebyte code.
Refer to Section 11.2.1 on page 184 for further details.
Low Voltage Detector (LVD)
The Low Voltage Detector function (LVD) generates a static reset when the V supply
DD
voltage is below a V
reference value. This means that it secures the power-up as well
IT-(LVD)
as the power-down keeping the ST7 in reset.
The V reference value for a voltage drop is lower than the V
reference value
IT+(LVD)
IT-(LVD)
for power-on in order to avoid a parasitic reset when the MCU starts running and sinks
current on the supply (hysteresis).
The LVD Reset circuitry generates a reset when V is below:
DD
■
■
V
V
when V is rising
DD
IT+(LVD)
IT-(LVD)
when V is falling
DD
The LVD function is illustrated in Figure 16.
The voltage threshold can be enabled/disabled by option byte. See Section 13.1 on page
211.
Provided the minimum V value (guaranteed for the oscillator frequency) is above V
,
DD
IT-(LVD)
the MCU can only be in two modes:
■
■
Under full software control
In static safe reset
In these conditions, secure operation is always ensured for the application without the need
for external reset hardware.
During a Low Voltage Detector Reset, the RESET pin is held low, thus permitting the MCU
to reset other devices.
Note:
Use of LVD with capacitive power supply: with this type of power supply, if power cuts occur
in the application, it is recommended to pull V down to 0 V to ensure optimum restart
DD
conditions. Refer to circuit example in Figure 89 on page 207 and note 4.
The LVD is an optional function which can be selected by option byte. See Section 13.1 on
page 211.
It allows the device to be used without any external RESET circuitry.
If the LVD is disabled, an external circuitry must be used to ensure a proper power-on reset.
It is recommended to make sure that the V supply voltage rises monotonously when the
DD
device is exiting from Reset, to ensure the application functions properly.
Caution:
If an LVD reset occurs after a watchdog reset has occurred, the LVD will take priority and will
clear the watchdog flag.
44/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
Supply, reset and clock management
Figure 16. Low voltage detector vs reset
VDD
Vhys
VIT+(LVD)
VIT-(LVD)
RESET
Figure 17. Reset and supply management block diagram
WATCHDOG
TIMER (WDG)
STATUS FLAG
SYSTEM INTEGRITY MANAGEMENT
RESET SEQUENCE
MANAGER
RCCRL
RESET
(RSM)
0
0
0
CR1 CR0 WDGF
0
LVDRF
LOW VOLTAGE
DETECTOR
(LVD)
VSS
VDD
45/226
Supply, reset and clock management
ST7FOXF1, ST7FOXK1, ST7FOXK2
6.5
Register description
6.5.1
RC calibration control/status register (RCC_CSR)
Reset value: 0000 0000 (00h)
7
0
0
0
0
0
0
0
RCCLAT RCCPGM
Read/write
Bits 7:2 = Reserved, forced by hardware to 0
0: Read mode
1: Write mode
Bit 1 = RCCLAT Latch Access Transfer bit: this bit is set by software.
It is cleared by hardware at the end of the programming cycle. It can only be cleared by
software if the RCCPGM bit is cleared
Bit 0 = RCCPGM Programming Control and Status bit
This bit is set by software to begin the programming cycle. At the end of the
programming cycle, this bit is cleared by hardware.
0: Programming finished or not yet started
1: Programming cycle is in progress
Note:
6.5.2
If the RCCPGM bit is cleared during the programming cycle, the memory data is not
guaranteed.
Main Clock Control/Status Register (MCCSR)
Reset value: 0000 0000 (00h)
7
0
0
0
0
0
0
0
MCO
SMS
Read/write
Bits 7:2 = Reserved, must be kept cleared.
Bit 1 = MCO Main Clock Out enable
bit
This bit is read/write by software and cleared by hardware after a reset. This bit allows
to enable the MCO output clock.
0: MCO clock disabled, I/O port free for general purpose I/O.
1: MCO clock enabled.
Bit 0 = SMS Slow mode selection
bit
This bit is read/write by software and cleared by hardware after a reset. This bit selects
the input clock f or f /32.
OSC
OSC
0: Normal mode (f
f
CPU = OSC
1: Slow mode (f
f
/32)
CPU = OSC
46/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
Supply, reset and clock management
6.5.3
RC Control Register High (RCCRH)
Reset value: 1111 1111 (FFh)
7
0
CR9
CR8
CR7
CR6
CR5
CR4
CR3
CR2
Read/write
Bits 7:0 = CR[9:2] RC Oscillator Frequency Adjustment bits
These bits must be written immediately after reset to adjust the RC oscillator
frequency. The application can store the correct value for each voltage range in Flash
memory and write it to this register at start-up.
00h = maximum available frequency
FFh = lowest available frequency
These bits are used with the CR[1:0] bits in the RCCRL register. Refer to
Chapter 6.5.4.
Note:
To tune the oscillator, write a series of different values in the register until the correct
frequency is reached. The fastest method is to use a dichotomy starting with 80h.
47/226
Supply, reset and clock management
ST7FOXF1, ST7FOXK1, ST7FOXK2
6.5.4
RC Control Register Low (RCCRL)
Reset value: 011x 0x00 (xxh)
7
0
0
CR1
CR0
WDGRF
0
LVDRF
0
0
Read/write
Bit 7 = Reserved, must be kept cleared
Bits 6:5 = CR[1:0] RC Oscillator Frequency Adjustment bits
These bits, as well as CR[9:2] bits in the RCCRH register must be written immediately
after reset to adjust the RC oscillator frequency. Refer to Section 6.1.1: Internal RC
oscillator on page 34.
Bit 4 = WDGRF Watchdog Reset flag
This bit indicates that the last reset was generated by the watchdog peripheral. It is set by
hardware (watchdog reset) and cleared by software (writing zero) or an LVD Reset (to
ensure a stable cleared state of the WDGRF flag when CPU starts). The WDGRF and the
LVDRF flags areis used to select the reset source (see Table 10: Reset source selection on
page 48).
Table 10. Reset source selection
RESET source
LVDRF
WDGRF
External RESET pin
Watchdog
0
0
1
0
1
LVD
X
Bit 3 = Reserved, must be kept cleared
Bit 2 = LVDRF LVD reset flag
This bit indicates that the last Reset was generated by the LVD block. It is set by
hardware (LVD reset) and cleared by software (by reading). When the LVD is disabled
by option byte, the LVDRF bit value is undefined.
The LVDRF flag is not cleared when another RESET type occurs (external or
watchdog), the LVDRF flag remains set to keep trace of the original failure.
In this case, a watchdog reset can be detected by software while an external reset can
not.
Bits 1:0 = Reserved, must be kept cleared
48/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
Supply, reset and clock management
6.5.5
Prescaler register (PSCR)
Reset value: 0000 0000 (00h) for ST7FOXF1 and ST7FOXK1
Reset value: 0000 0011 (03h) for ST7FOXK2
7
0
CK2
CK1
CK0
0
0
0
0 or 1
0 or 1
Read/write
Bits 7:5 = CK[2:0] internal RC Prescaler Selection
These bits are set by software and cleared by hardware after a reset. These bits select
the prescaler of the internal RC oscillator. See Table 11.
If the internal RC is used with a supply operating range below 3.3 V, a division ratio of
at least 2 must be enabled in the RC prescaler.
Table 11. Internal RC prescaler selection bits
CK2
CK1
CK0
fOSC
0
0
0
1
0
1
0
1
0
fRC/2
fRC/4
fRC/8
fRC/16
fRC
1
1
0
others
Bits 4:2 = Reserved, must be cleared.
Bits 1:0 = Must be set.
Caution:
For ST7FOXF1 and ST7FOXK1 devices, PRSC[1:0] bits must be forced to 1 by software in
order to reduce current consumption.
6.5.6
Clock controller control/status register (CKCNTCSR)
Reset value: 0000 1001 (09h)
7
0
0
0
0
0
AWU_FLAG
Read/write
RC_FLAG
0
RC/AWU
Bits 7:4 = Reserved, must be kept cleared.
Bit 3 = AWU_FLAG AWU Selection
bit
This bit is set and cleared by hardware.
0: No switch from AWU to RC requested
1: AWU clock activated and temporization completed
49/226
Supply, reset and clock management
ST7FOXF1, ST7FOXK1, ST7FOXK2
Bit 2 = RC_FLAG RC Selection
bit
This bit is set and cleared by hardware.
0: No switch from RC to AWU requested
1: RC clock activated and temporization completed
Bit 1 = Reserved, must be kept cleared.
Bit 0 = RC/AWU RC/AWU Selection
0: RC enabled
bit
1: AWU enabled (default value)
Table 12. Clock register mapping and reset values
Addre
ss
Register
label
7
6
5
4
3
2
1
0
(Hex.)
-
0
-
0
-
0
-
0
-
0
-
0
RCCLAT RCCPGM
0035h
003Ah
003Bh
003Ch
003Dh
RCC_CSR
0
0
MCCSR
-
0
-
0
-
0
-
0
-
0
-
0
MCO
0
SMS
0
Reset Value
RCCRH
CR9
1
CR8
1
CR7
1
CR6
1
CR5
1
CR4
1
CR3
1
CR2
1
Reset Value
RCCRL
-
0
CR1
1
CR0
1
WDGRF
0
-
0
LVDRF
x
-
-
0
0
Reset Value
PSCR
CK2
0
CK1
0
CK0
0
-
0
-
0
-
0
-
-
0 or 1
0 or 1
Reset Value
AWU_
FLAG
1
RC_FLA
CKCNTCSR
Reset Value
-
0
-
0
-
0
-
0
-
0
RC/AWU
1
0051h
G
0
50/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
Interrupts
7
Interrupts
7.1
Introduction
The ST7 enhanced interrupt management provides the following features:
■
■
■
Hardware interrupts
Software interrupt (TRAP)
Nested or concurrent interrupt management with flexible interrupt priority and level
management:
–
–
–
Up to 4 software programmable nesting levels
13 interrupt vectors fixed by hardware
2 non maskable events: RESET, TRAP
This interrupt management is based on:
■
■
■
Bit 5 and bit 3 of the CPU CC register (I1:0),
Interrupt software priority registers (ISPRx),
Fixed interrupt vector addresses located at the high addresses of the memory mapping
(FFE0h to FFFFh) sorted by hardware priority order.
This enhanced interrupt controller guarantees full upward compatibility with the standard
(not nested) ST7 interrupt controller.
7.2
Masking and processing flow
The interrupt masking is managed by the I1 and I0 bits of the CC register and the ISPRx
registers which give the interrupt software priority level of each interrupt vector (see
Table 13). The processing flow is shown in Figure 18.
When an interrupt request has to be serviced:
■
■
■
Normal processing is suspended at the end of the current instruction execution.
The PC, X, A and CC registers are saved onto the stack.
I1 and I0 bits of CC register are set according to the corresponding values in the ISPRx
registers of the serviced interrupt vector.
■
The PC is then loaded with the interrupt vector of the interrupt to service and the first
instruction of the interrupt service routine is fetched (refer to interrupt mapping table for
vector addresses).
The interrupt service routine should end with the IRET instruction which causes the
contents of the saved registers to be recovered from the stack.
Note:
As a consequence of the IRET instruction, the I1 and I0 bits will be restored from the stack
and the program in the previous level will resume.
51/226
Interrupts
ST7FOXF1, ST7FOXK1, ST7FOXK2
Table 13. Interrupt software priority levels
Interrupt software priority
Level
I1
I0
Level 0 (main)
Level 1
1
0
1
0
1
Low
0
1
Level 2
High
Level 3 (= interrupt disable)
Figure 18. Interrupt processing flowchart
PENDING
INTERRUPT
Y
Y
RESET
TLI
N
Interrupt has the same or a
lower software priority
than current one
N
I1:0
FETCH NEXT
INSTRUCTION
THE INTERRUPT
STAYS PENDING
Y
“IRET”
N
RESTORE PC, X, A, CC
FROM STACK
EXECUTE
INSTRUCTION
STACK PC, X, A, CC
LOAD I1:0 FROM INTERRUPT SW REG.
LOAD PC FROM INTERRUPT VECTOR
52/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
Interrupts
7.2.1
Servicing pending interrupts
As several interrupts can be pending at the same time, the interrupt to be taken into account
is determined by the following two-step process:
■
■
The highest software priority interrupt is serviced,
If several interrupts have the same software priority then the interrupt with the highest
hardware priority is serviced first.
Figure 19 describes this decision process.
Figure 19. Priority decision process
PENDING
INTERRUPTS
Different
Same
SOFTWARE
PRIORITY
HIGHEST SOFTWARE
PRIORITY SERVICED
HIGHEST HARDWARE
PRIORITY SERVICED
When an interrupt request is not serviced immediately, it is latched and then processed
when its software priority combined with the hardware priority becomes the highest one.
Note:
1
2
The hardware priority is exclusive while the software one is not. This allows the previous
process to succeed with only one interrupt.
RESET and TRAP can be considered as having the highest software priority in the decision
process.
7.2.2
Interrupt vector sources
Two interrupt source types are managed by the ST7 interrupt controller: the non-maskable
type (RESET, TRAP) and the maskable type (external or from internal peripherals).
Non-maskable sources
These sources are processed regardless of the state of the I1 and I0 bits of the CC register
(see Figure 18). After stacking the PC, X, A and CC registers (except for RESET), the
corresponding vector is loaded in the PC register and the I1 and I0 bits of the CC are set to
disable interrupts (level 3). These sources allow the processor to exit Halt mode.
■
TRAP (non maskable software interrupt)
This software interrupt is serviced when the TRAP instruction is executed. It will be
serviced according to the flowchart in Figure 18.
■
RESET
The RESET source has the highest priority in the ST7. This means that the first current
routine has the highest software priority (level 3) and the highest hardware priority.
See the RESET chapter for more details.
53/226
Interrupts
ST7FOXF1, ST7FOXK1, ST7FOXK2
Maskable sources
Maskable interrupt vector sources can be serviced if the corresponding interrupt is enabled
and if its own interrupt software priority (in ISPRx registers) is higher than the one currently
being serviced (I1 and I0 in CC register). If any of these two conditions is false, the interrupt
is latched and thus remains pending.
■
External interrupts
External interrupts allow the processor to exit from Halt low power mode.
External interrupt sensitivity is software selectable through the External Interrupt
Control register (EICR).
External interrupt triggered on edge will be latched and the interrupt request
automatically cleared upon entering the interrupt service routine.
If several input pins of a group connected to the same interrupt line are selected
simultaneously, these will be logically ORed.
■
Peripheral interrupts
Usually the peripheral interrupts cause the MCU to exit from Halt mode except those
mentioned in Table 17: ST7FOXF1/ST7FOXK1 Interrupt mapping.
A peripheral interrupt occurs when a specific flag is set in the peripheral status
registers and if the corresponding enable bit is set in the peripheral control register.
The general sequence for clearing an interrupt is based on an access to the status
register followed by a read or write to an associated register.
Note:
The clearing sequence resets the internal latch. A pending interrupt (that is, waiting for
being serviced) will therefore be lost if the clear sequence is executed.
7.3
Interrupts and low power modes
All interrupts allow the processor to exit the Wait low power mode. On the contrary, only
external and other specified interrupts allow the processor to exit from the Halt modes (see
column “Exit from Halt” in Table 17: ST7FOXF1/ST7FOXK1 Interrupt mapping). When
several pending interrupts are present while exiting Halt mode, the first one serviced can
only be an interrupt with exit from Halt mode capability and it is selected through the same
decision process shown in Figure 19.
Note:
If an interrupt, that is not able to Exit from Halt mode, is pending with the highest priority
when exiting Halt mode, this interrupt is serviced after the first one serviced.
54/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
Interrupts
7.4
Concurrent and nested management
The following Figure 20 and Figure 21 show two different interrupt management modes. The
first is called concurrent mode and does not allow an interrupt to be interrupted, unlike the
nested mode in Figure 21. The interrupt hardware priority is given in this order from the
lowest to the highest: MAIN, IT5, IT4, IT3, IT2, IT1, IT0. The software priority is given for
each interrupt.
Caution:
A stack overflow may occur without notifying the software of the failure.
Figure 20. Concurrent interrupt management
SOFTWARE
PRIORITY
LEVEL
I1
I0
IT0
3
1
1
1
1
1
1
1
1
1
1
1
1
IT1
3
IT2
IT2
3
IT3
3
IT4
3
RIM
IT5
3
MAIN
MAIN
3/0
11 / 10
10
Figure 21. Nested interrupt management
SOFTWARE
PRIORITY
LEVEL
I1
I0
TLI
3
3
2
1
3
3
1
1
0
0
1
1
1
1
0
1
1
1
IT0
IT1
IT1
IT2
IT2
IT3
RIM
IT4
IT4
MAIN
MAIN
3/0
11 / 10
10
55/226
Interrupts
ST7FOXF1, ST7FOXK1, ST7FOXK2
7.5
Description of interrupt registers
7.5.1
CPU CC register interrupt bits
Reset value: 111x 1010(xAh)
7
0
1
1
I1
H
I0
Read/write
N
Z
C
Bits 5, 3 = I1, I0 Software Interrupt Priority
bits
These two bits indicate the current interrupt software priority (see Table 14).
These two bits are set/cleared by hardware when entering in interrupt. The loaded
value is given by the corresponding bits in the interrupt software priority registers
(ISPRx).
They can be also set/cleared by software with the RIM, SIM, HALT, WFI, IRET and
PUSH/POP instructions (see Table 16: Dedicated interrupt instruction set).
TRAP and RESET events can interrupt a level 3 program.
Table 14. Setting the interrupt software priority
Interrupt software priority
Level
I1
I0
Level 0 (main)
Level 1
1
0
1
0
1
Low
0
1
Level 2
High
Level 3 (= interrupt disable*)
7.5.2
Interrupt software priority registers (ISPRx)
All ISPRx register bits are read/write except bit 7:4 of ISPR3 which are read only.
Reset value: 1111 1111 (FFh)
7
0
ISPR0
ISPR1
ISPR2
ISPR3
I1_3
I1_7
I1_11
1
I0_3
I0_7
I0_11
1
I1_2
I1_6
I1_10
1
I0_2
I0_6
I0_10
1
I1_1
I1_5
I1_9
1
I0_1
I0_5
I0_9
1
I1_0
I1_4
I0_0
I0_4
I1_8
I0_8
I1_12
I0_12
ISPRx registers contain the interrupt software priority of each interrupt vector. Each interrupt
vector (except RESET and TRAP) has corresponding bits in these registers to define its
software priority. This correspondence is shown in Table 15.
Each I1_x and I0_x bit value in the ISPRx registers has the same meaning as the I1 and I0
bits in the CC register.
56/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
Interrupts
The RESET and TRAP vectors have no software priorities. When one is serviced, the I1 and
I0 bits of the CC register are both set.
Level 0 cannot be written (I1_x = 1, I0_x = 0). In this case, the previously stored value is
kept (Example: previous = CFh, write = 64h, result = 44h).
Table 15. Interrupt vector vs ISPRx bits
Vector address
ISPRx bits
FFFBh-FFFAh
FFF9h-FFF8h
...
I1_0 and I0_0 bits(1)
I1_1 and I0_1 bits
...
FFE1h-FFE0h
I1_13 and I0_13 bits
1. Bits in the ISPRx registers can be read and written but they are not significant in the interrupt process
management.
Caution:
If the I1_x and I0_x bits are modified while the interrupt x is executed the following behavior
has to be considered: If the interrupt x is still pending (new interrupt or flag not cleared) and
the new software priority is higher than the previous one, the interrupt x is re-entered.
Otherwise, the software priority stays unchanged up to the next interrupt request (after the
IRET of the interrupt x).
(1)
Table 16. Dedicated interrupt instruction set
Instruction
New description
Function/Example
I1
H
I0
N
Z
C
HALT
IRET
JRM
Entering Halt mode
Interrupt routine return
Jump if I1:0 = 11 (level 3)
Jump if I1:0 <> 11
1
0
Pop CC, A, X, PC
I1:0 = 11
I1
H
I0
N
Z
C
JRNM
POP CC
RIM
I1:0 <> 11
Pop CC from the Stack
Mem => CC
I1
1
1
1
1
H
I0
0
N
Z
C
Enable interrupt (level 0 set) Load 10 in I1:0 of CC
Disable interrupt (level 3 set) Load 11 in I1:0 of CC
SIM
1
TRAP
WFI
Software trap
Software NMI
1
Wait for interrupt
0
1. During the execution of an interrupt routine, the HALT, POPCC, RIM, SIM and WFI instructions change the
current software priority up to the next IRET instruction or one of the previously mentioned instructions.
57/226
Interrupts
ST7FOXF1, ST7FOXK1, ST7FOXK2
Table 17. ST7FOXF1/ST7FOXK1 Interrupt mapping
Exit
from
Source
block
Register Priority HALT
Address
vector
Number
Description
label
order
or
AWUFH
(1)
RESET
TRAP
AWU
Reset
yes
no
FFFEh-FFFFh
FFFCh-FFFDh
FFFAh-FFFBh
FFF8h-FFF9h
FFF6h-FFF7
N/A
Software interrupt
0
1
Auto Wake Up interrupt
Reserved
AWUCSR
yes(2)
Highest
Priority
-
2
ei0
ei1
ei2
External interrupt 0 (Port A)
External interrupt 1 (Port B)
External interrupt 2 (Port C)
AT timer Output Compare interrupt
AT timer input Capture interrupt
AT timer overflow 1 interrupt
AT timer Overflow 2 interrupt
I2C interrupt
N/A
3
yes
FFF4h-FFF5h
FFF2h-FFF3h
FFF0h-FFF1h
FFEEh-FFEFh
FFECh-FFEDh
FFEAh-FFEBh
FFE8h-FFE9h
FFE6h-FFE7h
FFE4h-FFE5h
FFE2h-FFE3h
4
5
no
no
no
no
no
yes
no
no
6
AT TIMER
ATCSR
7(3)
8
9
I2C
N/A
10 (3)
11
12
Lite timer RTC interrupt
Lite timer Input Capture interrupt
Lite timer RTC2 interrupt
Lowest
Priority
LITE TIMER
LTCSR2
1. For an interrupt, all events do not have the same capability to wake up the MCU from Halt, Active-Halt or Auto Wake-up
from Halt modes. Refer to the description of interrupt events for more details.
2. This interrupt exits the MCU from Auto Wake-up from Halt mode only.
3. These interrupts exit the MCU from Active-Halt mode only.
58/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
Interrupts
Table 18. ST7FOXK2 interrupt mapping
Exit
from
Source
block
Register Priority HALT
Address
vector
Number
Description
label
order
or
AWUFH
(1)
RESET
TRAP
AWU
Reset
yes
FFFEh-FFFFh
FFFCh-FFFDh
FFFAh-FFFBh
FFF8h-FFF9h
FFF6h-FFF7h
FFF4h-FFF5h
FFF2h-FFF3h
FFF0h-FFF1h
FFEEh-FFEFh
N/A
Software interrupt
Auto Wake Up interrupt
Reserved
no
0
1
2
3
4
5
6
AWUCSR
yes (2)
-
-
-
Reserved
Highest
Priority
Reserved
ei0
ei1
ei2
External interrupt 0 (Port A)
External interrupt 1 (Port B)
External interrupt 2 (Port C)
N/A
yes
AT timer input Capture/Output
Compare interrupt
7
no
FFECh-FFEDh
AT TIMER
I2C
ATCSR
8(3)
9
AT timer overflow 1 interrupt
AT timer Overflow 2 interrupt
no
no
FFEAh-FFEBh
FFE8h-FFE9h
I2CSR1/
I2CSR2
10
I2C interrupt
no
FFE6h-FFE7h
Lowest
Priority
11
12
SPI
SPI interrupt
SPICSR
TACSR
no
no
FFE4h-FFE5h
FFE2h-FFE3h
FFE0h-FFE1h
TIM16
16-bit timer peripheral interrupt
Lite timer RTC/IC/RTC2 interrupt
13(3)
LITE TIMER
LTCSR2
yes
1. For an interrupt, all events do not have the same capability to wake up the MCU from Halt, Active-Halt or Auto-wakeup from
Halt modes. Refer to the description of interrupt events for more details.
2. This interrupt exits the MCU from Auto-wakeup from Halt mode only.
3. These interrupts exit the MCU from Active-Halt mode only.
59/226
Interrupts
ST7FOXF1, ST7FOXK1, ST7FOXK2
7.5.3
External Interrupt Control register (EICR)
Reset value: 0000 0000 (00h)
7
0
0
0
IS21
IS20
IS11
IS10
IS01
IS00
Read/write
Bits 7:6 = Reserved, must be kept cleared.
Bits 5:4 = IS2[1:0] ei2 sensitivity
bits
These bits define the interrupt sensitivity for ei2 (Port C) according to Table 19.
Bits 3:2 = IS1[1:0] ei1 sensitivity
bits
These bits define the interrupt sensitivity for ei1 (Port B) according to Table 19.
Bits 1:0 = IS0[1:0] ei0 sensitivity
bits
These bits define the interrupt sensitivity for ei0 (Port A) according to Table 19.
Note:
1
2
These 8 bits can be written only when the I bit in the CC register is set.
Changing the sensitivity of a particular external interrupt clears this pending interrupt. This
can be used to clear unwanted pending interrupts. Refer to Section : External interrupt
function.
Table 19. Interrupt sensitivity bits
ISx1
ISx0
External interrupt sensitivity
0
0
1
1
0
1
0
1
Falling edge & low level
Rising edge only
Falling edge only
Rising and falling edge
60/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
Power saving modes
8
Power saving modes
8.1
Introduction
To give a large measure of flexibility to the application in terms of power consumption, four
main power saving modes are implemented in the ST7 (see Figure 22):
■
■
■
■
■
Slow
Wait (and Slow-Wait)
Active Halt
Auto wakeup From Halt (AWUFH)
Halt
After a reset the normal operating mode is selected by default (Run mode). This mode
drives the device (CPU and embedded peripherals) by means of a master clock which is
based on the main oscillator frequency (f
).
OSC
From Run mode, the different power saving modes may be selected by setting the relevant
register bits or by calling the specific ST7 software instruction whose action depends on the
oscillator status.
Figure 22. Power saving mode transitions
High
Run
Slow
Wait
Slow Wait
Active Halt
Halt
Low
POWER CONSUMPTION
61/226
Power saving modes
ST7FOXF1, ST7FOXK1, ST7FOXK2
8.2
Slow mode
This mode has two targets:
■
■
To reduce power consumption by decreasing the internal clock in the device,
To adapt the internal clock frequency (f ) to the available supply voltage.
CPU
Slow mode is controlled by the SMS bit in the MCCSR register which enables or disables
Slow mode.
In this mode, the oscillator frequency is divided by 32. The CPU and peripherals are clocked
at this lower frequency.
Note:
Slow-Wait mode is activated when entering Wait mode while the device is already in Slow
mode.
Figure 23. Slow mode clock transition
fOSC/32
fOSC
fCPU
fOSC
SMS
NORMAL RUN MODE
REQUEST
8.3
Wait mode
Wait mode places the MCU in a low power consumption mode by stopping the CPU.
This power saving mode is selected by calling the ‘WFI’ instruction.
All peripherals remain active. During Wait mode, the I bit of the CC register is cleared, to
enable all interrupts. All other registers and memory remain unchanged. The MCU remains
in Wait mode until an interrupt or Reset occurs, whereupon the Program Counter branches
to the starting address of the interrupt or Reset service routine.
The MCU will remain in Wait mode until a Reset or an Interrupt occurs, causing it to wake
up.
Refer to Figure 24 for a description of the Wait mode flowchart.
62/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
Power saving modes
Figure 24. Wait mode flowchart
OSCILLATOR
PERIPHERALS
CPU
ON
ON
OFF
0
WFI INSTRUCTION
I BIT
N
RESET
Y
N
INTERRUPT
Y
OSCILLATOR
PERIPHERALS
CPU
ON
OFF
ON
0
I BIT
256 CPU CLOCK CYCLE
DELAY
OSCILLATOR
PERIPHERALS
CPU
ON
ON
ON
1)
X
I BIT
FETCH RESET VECTOR
OR SERVICE INTERRUPT
1. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set
during the interrupt routine and cleared when the CC register is popped.
8.4
Active-halt and halt modes
Active-Halt and Halt modes are the two lowest power consumption modes of the MCU. They
are both entered by executing the ‘HALT’ instruction. The decision to enter either in Active-
Halt or Halt mode is given by the LTCSR/ATCSR register status as shown in the following
table:
Table 20. Enabling/disabling active-halt and halt modes
LTCSR TBIE ATCSR OVFIE
ATCSRCK1 bit ATCSRCK0 bit
Meaning
bit
bit
0
0
0
1
x
x
0
1
x
1
x
x
1
x
0
0
x
1
x
1
Active-Halt mode disabled
Active-Halt mode enabled
63/226
Power saving modes
ST7FOXF1, ST7FOXK1, ST7FOXK2
8.4.1
Active-halt mode
Active-Halt mode is the lowest power consumption mode of the MCU with a real-time clock
available. It is entered by executing the ‘HALT’ instruction when active halt mode is enabled.
The MCU can exit Active-Halt mode on reception of a Lite timer/ AT timer interrupt or a
Reset.
■
When exiting Active-Halt mode by means of a Reset, a 256 CPU cycle delay occurs.
After the start up delay, the CPU resumes operation by fetching the Reset vector which
woke it up (see Figure 26).
■
When exiting Active-Halt mode by means of an interrupt, the CPU immediately
resumes operation by servicing the interrupt vector which woke it up (see Figure 26).
When entering Active-Halt mode, the I bit in the CC register is cleared to enable interrupts.
Therefore, if an interrupt is pending, the MCU wakes up immediately.
In Active-Halt mode, only the main oscillator and the selected timer counter (LT/AT) are
running to keep a wakeup time base. All other peripherals are not clocked except those
which get their clock supply from another clock generator (such as external or auxiliary
oscillator).
Caution:
As soon as Active-Halt is enabled, executing a HALT instruction while the Watchdog is
active does not generate a Reset if the WDGHALT bit is reset.
This means that the device cannot spend more than a defined delay in this power saving
mode.
Figure 25. Active-halt timing overview
ACTIVE
HALT
256 CPU
RUN
RUN
CYCLE DELAY 1)
RESET
OR
INTERRUPT
HALT
INSTRUCTION
[Active Halt Enabled]
FETCH
VECTOR
1. This delay occurs only if the MCU exits Active-Halt mode by means of a RESET.
64/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
Power saving modes
Figure 26. Active-halt mode flowchart
OSCILLATOR
PERIPHERALS 2)
CPU
ON
OFF
OFF
0
HALT INSTRUCTION
(Active Halt enabled)
I BIT
N
RESET
Y
N
INTERRUPT 3)
Y
OSCILLATOR
PERIPHERALS 2)
CPU
ON
OFF
ON
I BIT
X 4)
256 CPU CLOCK CYCLE
DELAY
OSCILLATOR
PERIPHERALS
CPU
ON
ON
ON
X 4)
I BITS
FETCH RESET VECTOR
OR SERVICE INTERRUPT
1. This delay occurs only if the MCU exits Active-Halt mode by means of a RESET.
2. Peripherals clocked with an external clock source can still be active.
3. Only the Lite timer RTC and AT timer interrupts can exit the MCU from Active-Halt mode.
4. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set
during the interrupt routine and cleared when the CC register is popped.
8.4.2
Halt mode
The Halt mode is the lowest power consumption mode of the MCU. It is entered by
executing the HALT instruction when active halt mode is disabled.
The MCU can exit Halt mode on reception of either a specific interrupt (seeTable 17:
ST7FOXF1/ST7FOXK1 Interrupt mapping) or a Reset. When exiting Halt mode by means of
a Reset or an interrupt, the main oscillator is immediately turned on and the 256 CPU cycle
delay is used to stabilize it. After the start up delay, the CPU resumes operation by servicing
the interrupt or by fetching the Reset vector which woke it up (see Figure 28).
When entering Halt mode, the I bit in the CC register is forced to 0 to enable interrupts.
Therefore, if an interrupt is pending, the MCU wakes immediately.
In Halt mode, the main oscillator is turned off causing all internal processing to be stopped,
including the operation of the on-chip peripherals. All peripherals are not clocked except the
ones which get their clock supply from another clock generator (such as an external or
auxiliary oscillator).
The compatibility of Watchdog operation with Halt mode is configured by the “WDGHALT”
option bit of the option byte. The HALT instruction when executed while the Watchdog
system is enabled, can generate a Watchdog Reset (see Section 13.1: Option bytes for
more details).
65/226
Power saving modes
ST7FOXF1, ST7FOXK1, ST7FOXK2
Figure 27. Halt timing overview
256 CPU CYCLE
DELAY
RUN
HALT
RUN
RESET
OR
INTERRUPT
HALT
INSTRUCTION
FETCH
VECTOR
[Active Halt disabled]
1. A reset pulse of at least 42 µs must be applied when exiting from Halt mode.
Figure 28. Halt mode flowchart
HALT INSTRUCTION
(Active Halt disabled)
ENABLE
WATCHDOG
0
DISABLE
WDGHALT 1)
1
WATCHDOG
RESET
OSCILLATOR
OFF
PERIPHERALS 2)
OFF
OFF
0
CPU
I BIT
N
RESET
Y
N
INTERRUPT 3)
Y
OSCILLATOR
PERIPHERALS
CPU
ON
OFF
ON
I BIT
X 4)
256 CPU CLOCK CYCLE
DELAY 5)
OSCILLATOR
PERIPHERALS
CPU
ON
ON
ON
X 4)
I BITS
FETCH RESET VECTOR
OR SERVICE INTERRUPT
1. WDGHALT is an option bit. See option byte section for more details.
2. Peripheral clocked with an external clock source can still be active.
3. Only some specific interrupts can exit the MCU from Halt mode (such as external interrupt). Refer to
Table 17: ST7FOXF1/ST7FOXK1 Interrupt mappingfor more details.
4. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set
during the interrupt routine and cleared when the CC register is popped.
5. The CPU clock must be switched to 1 MHz (RC/8) or AWU RC before entering Halt mode.
66/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
Power saving modes
Halt mode recommendations
■
Make sure that an external event is available to wake up the microcontroller from Halt
mode.
■
When using an external interrupt to wake up the microcontroller, reinitialize the
corresponding I/O as “Input Pull-up with Interrupt” before executing the HALT
instruction. The main reason for this is that the I/O may be wrongly configured due to
external interference or by an unforeseen logical condition.
■
■
For the same reason, reinitialize the level sensitiveness of each external interrupt as a
precautionary measure.
The opcode for the HALT instruction is 0x8E. To avoid an unexpected HALT instruction
due to a Program Counter failure, it is advised to clear all occurrences of the data value
0x8E from memory. For example, avoid defining a constant in ROM with the value
0x8E.
■
As the HALT instruction clears the I bit in the CC register to allow interrupts, the user
may choose to clear all pending interrupt bits before executing the HALT instruction.
This avoids entering other peripheral interrupt routines after executing the external
interrupt routine corresponding to the wakeup event (reset or external interrupt).
8.5
Auto-wakeup from Halt mode
Auto wakeup from Halt (AWUFH) mode is similar to Halt mode with the addition of a specific
internal RC oscillator for wakeup (Auto-wakeup from Halt oscillator) which replaces the main
clock which was active before entering Halt mode. Compared to Active-Halt mode, AWUFH
has lower power consumption (the main clock is not kept running), but there is no accurate
real-time clock available.
It is entered by executing the HALT instruction when the AWUEN bit in the AWUCSR
register has been set.
Figure 29. AWUFH mode block diagram
AWU RC
oscillator
to 8-bit timer Input Capture
fAWU_RC
AWUFH
interrupt
AWUFH
prescaler/1 .. 255
/64
divider
(ei0 source)
67/226
Power saving modes
ST7FOXF1, ST7FOXK1, ST7FOXK2
As soon as Halt mode is entered, and if the AWUEN bit has been set in the AWUCSR
register, the AWU RC oscillator provides a clock signal (f ). Its frequency is divided by
AWU_RC
a fixed divider and a programmable prescaler controlled by the AWUPR register. The output
of this prescaler provides the delay time. When the delay has elapsed, the following actions
are performed:
■
■
■
the AWUF flag is set by hardware,
an interrupt wakes-up the MCU from Halt mode,
the main oscillator is immediately turned on and the 256 CPU cycle delay is used to
stabilize it.
After this start-up delay, the CPU resumes operation by servicing the AWUFH interrupt. The
AWU flag and its associated interrupt are cleared by software reading the AWUCSR
register.
To compensate for any frequency dispersion of the AWU RC oscillator, it can be calibrated
by measuring the clock frequency f
and then calculating the right prescaler value.
AWU_RC
Measurement mode is enabled by setting the AWUM bit in the AWUCSR register in Run
mode. This connects f to the Input Capture of the 8-bit Lite timer, allowing the
AWU_RC
f
to be measured using the main oscillator clock as a reference timebase.
AWU_RC
Similarities with halt mode
The following AWUFH mode behavior is the same as normal Halt mode:
■
■
■
The MCU can exit AWUFH mode by means of any interrupt with exit from Halt
capability or a reset (see Section 8.4: Active-halt and halt modes).
When entering AWUFH mode, the I bit in the CC register is forced to 0 to enable
interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately.
In AWUFH mode, the main oscillator is turned off causing all internal processing to be
stopped, including the operation of the on-chip peripherals. None of the peripherals are
clocked except those which get their clock supply from another clock generator (such
as an external or auxiliary oscillator like the AWU oscillator).
■
The compatibility of watchdog operation with AWUFH mode is configured by the
WDGHALT option bit in the option byte. Depending on this setting, the HALT instruction
when executed while the watchdog system is enabled, can generate a watchdog Reset.
Figure 30. AWUF halt timing diagram
tAWU
RUN MODE
HALT MODE
256 tCPU
RUN MODE
Clear
fCPU
fAWU_RC
by software
AWUFH interrupt
68/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
Power saving modes
Figure 31. AWUFH mode flowchart
HALT INSTRUCTION
(Active-Halt disabled)
(AWUCSR.AWUEN=1)
ENABLE
WATCHDOG
DISABLE
0
WDGHALT 1)
1
AWU RC OSC
MAIN OSC
PERIPHERALS 2)
CPU
ON
OFF
OFF
OFF
10
WATCHDOG
RESET
I[1:0] BITS
N
RESET
Y
N
INTERRUPT 3)
AWU RC OSC
MAIN OSC
OFF
ON
Y
PERIPHERALS
CPU
I[1:0] BITS
OFF
ON
XX 4)
256 CPU CLOCK
CYCLE DELAY
AWU RC OSC
MAIN OSC
PERIPHERALS
CPU
OFF
ON
ON
ON
I[1:0] BITS
XX 4)
FETCH RESET VECTOR
OR SERVICE INTERRUPT
1. WDGHALT is an option bit. See option byte section for more details.
2. Peripheral clocked with an external clock source can still be active.
3. Only an AWUFH interrupt and some specific interrupts can exit the MCU from Halt mode (such as external
interrupt). Refer to Table 17: ST7FOXF1/ST7FOXK1 Interrupt mapping for more details.
4. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are
set to the current software priority level of the interrupt routine and recovered when the CC register is
popped.
69/226
Power saving modes
ST7FOXF1, ST7FOXK1, ST7FOXK2
8.5.1
8.5.2
Register description
AWUFH Control/Status Register (AWUCSR)
Reset value: 0000 0000 (00h)
7
0
AWU
F
0
0
0
0
0
AWUM
AWUEN
Read/Write
Bits 7:3 = Reserved
Bit 2 = AWUF Auto wakeup flag
This bit is set by hardware when the AWU module generates an interrupt and cleared
by software on reading AWUCSR. Writing to this bit does not change its value.
0: No AWU interrupt occurred
1: AWU interrupt occurred
Bit 1 = AWUM Auto wakeup Measurement
bit
This bit enables the AWU RC oscillator and connects its output to the Input Capture of
the 8-bit Lite timer. This allows the timer to be used to measure the AWU RC oscillator
dispersion and then compensate this dispersion by providing the right value in the
AWUPRE register.
0: Measurement disabled
1: Measurement enabled
Bit 0 = AWUEN Auto wakeup From Halt Enabled
bit
This bit enables the Auto wakeup from halt feature: once Halt mode is entered, the
AWUFH wakes up the microcontroller after a time delay dependent on the AWU
prescaler value. It is set and cleared by software.
0: AWUFH (Auto wakeup from Halt) mode disabled
1: AWUFH (Auto wakeup from Halt) mode enabled
Note:
Whatever the clock source, this bit should be set to enable the AWUFH mode once the
HALT instruction has been executed.
70/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
Power saving modes
8.5.3
AWUFH prescaler register (AWUPR)
Reset value: 1111 1111 (FFh)
7
0
AWUPR7 AWUPR6 AWUPR5 AWUPR4 AWUPR3 AWUPR2 AWUPR1 AWUPR0
Read/Write
Bits 7:0= AWUPR[7:0] Auto wakeup Prescaler
These 8 bits define the AWUPR Dividing factor (see Table 21).
Table 21. Configuring the dividing factor
AWUPR[7:0]
Dividing factor
00h
01h
...
Forbidden
1
...
FEh
FFh
254
255
In AWU mode, the time during which the MCU stays in Halt mode, t
, is given by the
AWU
equation below. See also Figure 30 on page 68.
1
--------------------
tAWU = 64 × AWUPR ×
+ tRCSTRT
fAWURC
The AWUPR prescaler register can be programmed to modify the time during which the
MCU stays in Halt mode before waking up automatically.
Note:
If 00h is written to AWUPR, the AWUPR remains unchanged.
Table 22. AWU register mapping and reset values
Address Register
7
6
5
4
3
2
1
0
(Hex.)
label
AWUCSR
Reset
0048h
0
0
0
0
0
AWUF
AWUM
AWUEN
Value
AWUPR
Reset
Value
AWUPR7 AWUPR6 AWUPR5 AWUPR4 AWUPR3 AWUPR2 AWUPR1 AWUPR0
0049h
1
1
1
1
1
1
1
1
71/226
I/O ports
ST7FOXF1, ST7FOXK1, ST7FOXK2
9
I/O ports
9.1
9.2
Introduction
The I/O ports allow data transfer. An I/O port can contain up to 8 pins. Each pin can be
programmed independently either as a digital input or digital output. In addition, specific pins
may have several other functions. These functions can include external interrupt, alternate
signal input/output for on-chip peripherals or analog input.
Functional description
A Data register (DR) and a Data Direction register (DDR) are always associated with each
port. The Option register (OR), which allows input/output options, may or may not be
implemented. The following description takes into account the OR register. Refer to the Port
Configuration table for device specific information.
An I/O pin is programmed using the corresponding bits in the DDR, DR and OR registers: bit
x corresponding to pin x of the port.
Figure 32 shows the generic I/O block diagram.
9.2.1
Input modes
Clearing the DDRx bit selects input mode. In this mode, reading its DR bit returns the digital
value from that I/O pin.
If an OR bit is available, different input modes can be configured by software: floating or pull-
up. Refer to I/O Port Implementation section for configuration.
Note:
1
Writing to the DR modifies the latch value but does not change the state of the input pin.
Do not use read/modify/write instructions (BSET/BRES) to modify the DR register.
2
External interrupt function
Depending on the device, setting the ORx bit while in input mode can configure an I/O as an
input with interrupt. In this configuration, a signal edge or level input on the I/O generates an
interrupt request via the corresponding interrupt vector (eix).
Falling or rising edge sensitivity is programmed independently for each interrupt vector. The
External Interrupt Control register (EICR) or the Miscellaneous register controls this
sensitivity, depending on the device.
Each external interrupt vector is linked to a dedicated group of I/O port pins (see pinout
description and interrupt section). If several I/O interrupt pins on the same interrupt vector
are selected simultaneously, they are logically combined. For this reason if one of the
interrupt pins is tied low, it may mask the others.
External interrupts are hardware interrupts. Fetching the corresponding interrupt vector
automatically clears the request latch. Changing the sensitivity of a particular external
interrupt clears this pending interrupt. This can be used to clear unwanted pending
interrupts.
72/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
Spurious interrupts
I/O ports
When enabling/disabling an external interrupt by setting/resetting the related OR register bit,
a spurious interrupt is generated if the pin level is low and its edge sensitivity includes
falling/rising edge. This is due to the edge detector input which is switched to '1' when the
external interrupt is disabled by the OR register.
To avoid this unwanted interrupt, a "safe" edge sensitivity (rising edge for enabling and
falling edge for disabling) has to be selected before changing the OR register bit and
configuring the appropriate sensitivity again.
Caution:
In case a pin level change occurs during these operations (asynchronous signal input), as
interrupts are generated according to the current sensitivity, it is advised to disable all
interrupts before and to reenable them after the complete previous sequence in order to
avoid an external interrupt occurring on the unwanted edge.
This corresponds to the following steps:
a) Set the interrupt mask with the SIM instruction (in cases where a pin level change
could occur)
b) Select rising edge
c) Enable the external interrupt through the OR register
d) Select the desired sensitivity if different from rising edge
e) Reset the interrupt mask with the RIM instruction (in cases where a pin level
change could occur)
2. To disable an external interrupt:
a) Set the interrupt mask with the SIM instruction SIM (in cases where a pin level
change could occur)
b) Select falling edge
c) Disable the external interrupt through the OR register
d) Select rising edge
e) Reset the interrupt mask with the RIM instruction (in cases where a pin level
change could occur)
9.2.2
Output modes
Setting the DDRx bit selects output mode. Writing to the DR bits applies a digital value to the
I/O through the latch. Reading the DR bits returns the previously stored value.
If an OR bit is available, different output modes can be selected by software: push-pull or
open-drain. Refer to I/O Port Implementation section for configuration.
Table 23. DR Value and output pin status
DR
Push-Pull
Open-Drain
0
1
VOL
VOH
VOL
Floating
73/226
I/O ports
ST7FOXF1, ST7FOXK1, ST7FOXK2
9.2.3
Alternate functions
Many ST7s I/Os have one or more alternate functions. These may include output signals
from, or input signals to, on-chip peripherals.Table 2 and Table 3 describe which peripheral
signals can be input/output to which ports.
A signal coming from an on-chip peripheral can be output on an I/O. To do this, enable the
on-chip peripheral as an output (enable bit in the peripheral’s control register). The
peripheral configures the I/O as an output and takes priority over standard I/O programming.
The I/O’s state is readable by addressing the corresponding I/O data register.
Configuring an I/O as floating enables alternate function input. It is not recommended to
configure an I/O as pull-up as this will increase current consumption. Before using an I/O as
an alternate input, configure it without interrupt. Otherwise spurious interrupts can occur.
Configure an I/O as input floating for an on-chip peripheral signal which can be input and
output.
Caution:
I/Os which can be configured as both an analog and digital alternate function need special
attention. The user must control the peripherals so that the signals do not arrive at the same
time on the same pin. If an external clock is used, only the clock alternate function should be
employed on that I/O pin and not the other alternate function.
Figure 32. I/O port general block diagram
ALTERNATE
OUTPUT
From on-chip peripheral
1
0
REGISTER
ACCESS
P-BUFFER
(see table below)
V
DD
ALTERNATE
ENABLE
BIT
PULL-UP
(see table below)
DR
V
DD
DDR
OR
PULL-UP
CONDITION
PAD
If implemented
OR SEL
DDR SEL
DR SEL
N-BUFFER
DIODES
(see table below)
ANALOG
INPUT
CMOS
SCHMITT
TRIGGER
1
0
ALTERNATE
INPUT
To on-chip peripheral
EXTERNAL
INTERRUPT
REQUEST (ei )
Combinational
Logic
FROM
OTHER
BITS
x
SENSITIVITY
SELECTION
Note: Refer to the Port Configuration
table for device specific information.
74/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
I/O ports
(1)
Table 24. I/O port mode options
Configuration mode
Diodes
Pull-Up
P-Buffer
to VDD
to VSS
Floating with/without Interrupt
Pull-up with Interrupt
Push-pull
Off
On
Input
Off
On
On
On
Off
Output
Off
Open Drain (logic level)
1. Off means implemented not activated, On means implemented and activated.
Table 25. ST7FOXF1/ST7FOXK1/ST7FOXK2 I/O port configuration
Hardware configuration
DR REGISTER ACCESS
W
R
DR
REGISTER
DATA BUS
PAD
ALTERNATE INPUT
To on-chip peripheral
FROM
OTHER
PINS
EXTERNAL INTERRUPT
SOURCE (ei )
x
COMBINATIONAL
LOGIC
INTERRUPT
CONDITION
POLARITY
SELECTION
ANALOG INPUT
DR REGISTER ACCESS
PAD
R/W
DR
REGISTER
DATA BUS
DR REGISTER ACCESS
R/W
DR
REGISTER
DATA BUS
PAD
ALTERNATE
ENABLE
BIT
ALTERNATE
OUTPUT
From on-chip peripheral
1. When the I/O port is in input configuration and the associated alternate function is enabled as an output,
reading the DR register will read the alternate function output status.
2. When the I/O port is in output configuration and the associated alternate function is enabled as an input,
the alternate function reads the pin status given by the DR register content.
75/226
I/O ports
ST7FOXF1, ST7FOXK1, ST7FOXK2
9.2.4
Analog alternate function
Configure the I/O as floating input to use an ADC input. The analog multiplexer (controlled
by the ADC registers) switches the analog voltage present on the selected pin to the
common analog rail, connected to the ADC input.
Analog Recommendations
Do not change the voltage level or loading on any I/O while conversion is in progress. Do not
have clocking pins located close to a selected analog pin.
Caution:
The analog input voltage level must be within the limits stated in the absolute maximum
ratings.
9.3
I/O port implementation
The hardware implementation on each I/O port depends on the settings in the DDR and OR
registers and specific I/O port features such as ADC input or open drain.
Switching these I/O ports from one state to another should be done in a sequence that
prevents unwanted side effects. Recommended safe transitions are illustrated in Figure 33.
Other transitions are potentially risky and should be avoided, since they may present
unwanted side-effects such as spurious interrupt generation.
Figure 33. Interrupt I/O port state transitions
01
00
10
11
INPUT
floating/pull-up
interrupt
INPUT
floating
(reset state)
OUTPUT
open-drain
OUTPUT
push-pull
= DDR, OR
XX
9.4
9.5
Unused I/O pins
Unused I/O pins must be connected to fixed voltage levels. Refer to Section 12.9: I/O port
pin characteristics.
Low power modes
s
Table 26. Effect of low power modes on I/O ports
Mode
Description
No effect on I/O ports. External interrupts cause the device to exit from Wait
mode.
Wait
No effect on I/O ports. External interrupts cause the device to exit from Halt
mode.
Halt
76/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
I/O ports
9.6
Interrupts
The external interrupt event generates an interrupt if the corresponding configuration is
selected with DDR and OR registers and if the I bit in the CC register is cleared (RIM
instruction).
Table 27. Description of interrupt events
Enable
Control bit
Exit from
Wait
Exit from
Halt
Interrupt Event
Event flag
External interrupt on selected
external event
DDRx
ORx
-
Yes
Yes
See application notes AN1045 software implementation of I2C bus master, and AN1048 -
software LCD driver
9.7
Device-specific I/O port configuration
The I/O port register configurations are summarized in Section 9.7.1: Standard ports and
Section 9.7.2: Other ports.
9.7.1
Standard ports
Table 28. PA5:0, PB7:0, PC7:4 and PC2:0 pins
Mode
DDR
OR
floating input
pull-up interrupt input
open drain output
push-pull output
0
0
1
1
0
1
0
1
9.7.2
Other ports
Table 29. PA7:6 pins
Mode
DDR
OR
floating input
interrupt input
0
0
1
1
0
1
0
1
open drain output
push-pull output
77/226
I/O ports
ST7FOXF1, ST7FOXK1, ST7FOXK2
M
Table 30. PC3 pin
Mode
DDR
OR
floating input
pull-up input
0
0
1
1
0
1
0
1
open drain output
push-pull output
Table 31. Port configuration
Input
Output
Port
Pin name
OR = 0
OR = 1
OR = 0
OR = 1
PA5:0
PA7:6
PB7:0
floating
floating
floating
pull-up interrupt
interrupt
open drain
push-pull
Port A
Port B
true open drain
pull-up interrupt
open drain
push-pull
push-pull
push-pull
PC7:4,
PC2:0
floating
floating
pull-up interrupt
pull-up
open drain
open drain
Port C
PC3
Table 32. I/O port register mapping and reset values
Address
(Hex.)
Register
label
7
6
5
4
3
2
1
0
PADR
MSB
0
LSB
0
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
Reset Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PADDR
MSB
0
LSB
0
Reset Value
PAOR
MSB
0
LSB
0
Reset Value
PBDR
MSB
0
LSB
0
Reset Value
PBDDR
MSB
0
LSB
0
Reset Value
PBOR
MSB
0
LSB
0
Reset Value
PCDR
MSB
0
LSB
0
Reset Value
PCDDR
MSB
0
LSB
0
Reset Value
PCOR
MSB
0
LSB
0
Reset Value
78/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
On-chip peripherals
10
On-chip peripherals
10.1
Watchdog timer (WDG)
10.1.1
Introduction
The Watchdog timer is used to detect the occurrence of a software fault, usually generated
by external interference or by unforeseen logical conditions, which causes the application
program to abandon its normal sequence. The Watchdog circuit generates an MCU reset on
expiry of a programmed time period, unless the program refreshes the counter’s contents
before the T6 bit becomes cleared.
10.1.2
10.1.3
Main features
■
■
■
■
■
Programmable free-running downcounter (64 increments of 16000 CPU cycles)
Programmable reset
Reset (if watchdog activated) when the T6 bit reaches zero
Optional reset on HALT instruction (configurable by option byte)
Hardware Watchdog selectable by option byte
Functional description
The counter value stored in the CR register (bits T[6:0]), is decremented every 16000
machine cycles, and the length of the timeout period can be programmed by the user in 64
increments.
If the watchdog is activated (the WDGA bit is set) and when the 7-bit timer (bits T[6:0]) rolls
over from 40h to 3Fh (T6 becomes cleared), it initiates a reset cycle pulling low the RESET
pin for typically 30µs.
Figure 34. Watchdog block diagram
RESET
WATCHDOG CONTROL REGISTER (CR)
T5
T0
WDGA T6
T1
T4
T2
T3
7-BIT DOWNCOUNTER
CLOCK DIVIDER
fCPU
÷16000
79/226
On-chip peripherals
ST7FOXF1, ST7FOXK1, ST7FOXK2
The application program must write in the CR register at regular intervals during normal
operation to prevent an MCU reset. This downcounter is free-running: it counts down even if
the watchdog is disabled. The value to be stored in the CR register must be between FFh
and C0h (see Table 33: Watchdog timing):
■
■
■
The WDGA bit is set (watchdog enabled)
The T6 bit is set to prevent generating an immediate reset
The T[5:0] bits contain the number of increments which represents the time delay
before the watchdog produces a reset.
Following a reset, the watchdog is disabled. Once activated it cannot be disabled, except by
a reset.
The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is
cleared).
If the watchdog is activated, the HALT instruction will generate a Reset.
(1)(2)
Table 33. Watchdog timing
fCPU = 8 MHz
WDG
counter code
min
[ms]
max
[ms]
C0h
FFh
1
2
127
128
1. The timing variation shown in Table 33 is due to the unknown status of the prescaler when writing to the
CR register.
2. The number of CPU clock cycles applied during the Reset phase (256 or 4096) must be taken into account
in addition to these timings.
10.1.4
Hardware watchdog option
If Hardware Watchdog is selected by option byte, the watchdog is always active and the
WDGA bit in the CR is not used.
Refer to the option byte description in Section 13 on page 211.
Using Halt mode with the WDG (WDGHALT option)
If Halt mode with Watchdog is enabled by option byte (No watchdog reset on HALT
instruction), it is recommended before executing the HALT instruction to refresh the WDG
counter, to avoid an unexpected WDG reset immediately after waking up the microcontroller.
Same behavior in active-halt mode.
10.1.5
Interrupts
None.
80/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
On-chip peripherals
10.1.6
Register description
Control register (WDGCR)
Reset value: 0111 1111 (7Fh)
7
0
WDGA
T6
T5
T4
T3
T2
T1
T0
Read/Write
Bit 7 = WDGA Activation bit
This bit is set by software and only cleared by hardware after a reset. When WDGA = 1,
the watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled
Note:
This bit is not used if the hardware watchdog option is enabled by option byte.
Bits 6:0 = T[6:0] 7-bit timer (MSB to LSB)
These bits contain the decremented value. A reset is produced when it rolls over from
40h to 3Fh (T6 becomes cleared).
Table 34. Watchdog timer register mapping and reset values
Address
(Hex.)
Register
label
7
6
5
4
3
2
1
0
WDGCR
Reset
Value
WDGA
0
T6
1
T5
1
T4
1
T3
1
T2
1
T1
1
T0
1
0033h
81/226
On-chip peripherals
ST7FOXF1, ST7FOXK1, ST7FOXK2
10.2
Dual 12-bit autoreload timer
10.2.1
Introduction
The 12-bit Autoreload timer can be used for general-purpose timing functions. It is based on
one or two free-running 12-bit upcounters with an Input Capture register and four PWM
output channels. There are 7 external pins:
■
■
■
Four PWM outputs
ATIC/LTIC pins for the Input Capture function
BREAK pins for forcing a break condition on the PWM outputs
10.2.2
Main features
■
Single Timer or Dual Timer mode with two 12-bit upcounters (CNTR1/CNTR2) and two
12-bit autoreload registers (ATR1/ATR2)
Maskable overflow interrupts
PWM mode
■
■
–
–
–
–
–
–
Generation of four independent PWMx signals
Dead time generation for Half bridge driving mode with programmable dead time
Frequency 2 kHz - 4 MHz (@ 8 MHz f
Programmable duty-cycles
Polarity control
)
CPU
Programmable output modes
■
■
Output Compare mode
Input Capture mode
–
–
–
–
12-bit Input Capture register (ATICR)
Triggered by rising and falling edges
Maskable IC interrupt
Long range Input Capture
■
■
■
■
Internal/External Break control
Flexible Clock control
One Pulse mode on PWM2/3
Force update
82/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
On-chip peripherals
Figure 35. Single timer mode (ENCNTR2=0)
ATIC
12-bit Input Capture
Edge Detection Circuit
CMP
Interrupt
Output Compare
OE0
OE1
PWM0 Duty Cycle Generator
PWM0
PWM1
Dead Time
Generator
PWM1 Duty Cycle Generator
12-Bit Autoreload register 1
DTE bit
OE2
OE3
PWM2 Duty Cycle Generator
PWM3 Duty Cycle Generator
PWM2
PWM3
12-Bit Upcounter 1
OVF1 interrupt
BPEN bit
OFF
fCPU
Clock
Control
1 ms from
Lite timer
Figure 36. Dual timer mode (ENCNTR2=1)
12-bit Input Capture
Edge Detection Circuit
ATIC
CMP
Interrupt
Output Compare
OE0
12-Bit Autoreload register 1
PWM0 Duty Cycle Generator
PWM1 Duty Cycle Generator
PWM0
Dead Time
Generator
OE1
PWM1
12-Bit Upcounter 1
OVF1 interrupt
OVF2 interrupt
DTE bit
OE2
OE3
PWM2 Duty Cycle Generator
PWM2
PWM3
12-Bit Upcounter 2
One Pulse
mode
PWM3 Duty Cycle Generator
12-Bit Autoreload register 2
BPEN bit
Output Compare
CMP Interrupt
OP_EN bit
OFF
Clock
Control
fCPU
1 ms from
Lite timer
LTIC
83/226
On-chip peripherals
ST7FOXF1, ST7FOXK1, ST7FOXK2
10.2.3
Functional description
PWM mode
This mode allows up to four Pulse Width Modulated signals to be generated on the PWMx
output pins.
■
PWM frequency
The four PWM signals can have the same frequency (f
) or can have two different
PWM
frequencies. This is selected by the ENCNTR2 bit which enables Single Timer or Dual
Timer mode (see Figure 35 and Figure 36). The frequency is controlled by the counter
period and the ATR register value. In Dual Timer mode, PWM2 and PWM3 can be
generated with a different frequency controlled by CNTR2 and ATR2.
fPWM = fCOUNTER ⁄ (4096 – ATR)
Following the above formula, if f
equals 4 MHz the maximum value of f
is
COUNTER
,
PWM
2 MHz (ATR register value = 4094), and the minimum value is 1 kHz (ATR register
value = 0).
The maximum value of ATR is 4094 because it must be lower than the DC4R value
which must be 4095 in this case.
■
Duty cycle
The duty cycle is selected by programming the DCRx registers. These are preload
registers. The DCRx values are transferred in Active duty cycle registers after an
overflow event if the corresponding transfer bit (TRANx bit) is set.
The TRAN1 bit controls the PWMx outputs driven by counter 1 and the TRAN2 bit
controls the PWMx outputs driven by counter 2.
PWM generation and output compare are done by comparing these active DCRx
values with the counter.
The maximum available resolution for the PWMx duty cycle is:
Resolution = 1 ⁄ (4096 – ATR)
where ATR is equal to 0. With this maximum resolution, 0% and 100% duty cycle can
be obtained by changing the polarity.
At reset, the counter starts counting from 0.
When a upcounter overflow occurs (OVF event), the preloaded Duty cycle values are
transferred to the active Duty Cycle registers and the PWMx signals are set to a high
level. When the upcounter matches the active DCRx value the PWMx signals are set to
a low level. To obtain a signal on a PWMx pin, the contents of the corresponding active
DCRx register must be greater than the contents of the ATR register.
The maximum value of ATR is 4094 because it must be lower than the DCR value
which must be 4095 in this case.
■
Polarity inversion
The polarity bits can be used to invert any of the four output signals. The inversion is
synchronized with the counter overflow if the corresponding transfer bit in the ATCSR2
register is set (reset value). See Figure 37.
84/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
On-chip peripherals
Figure 37. PWM polarity inversion
inverter
PWMx
PIN
PWMx
PWMxCSR register
OPx
DFF
TRANx
ATCSR2 register
counter
overflow
The Data Flip Flop (DFF) applies the polarity inversion when triggered by the counter
overflow input.
■
Output control
The PWMx output signals can be enabled or disabled using the OEx bits in the
PWMCR register.
Figure 38. PWM function
4095
DUTY CYCLE
REGISTER
(DCRx)
AUTO-RELOAD
REGISTER
(ATR)
000
t
WITH OE=1
AND OPx=0
WITH OE=1
AND OPx=1
85/226
On-chip peripherals
ST7FOXF1, ST7FOXK1, ST7FOXK2
Figure 39. PWM signal from 0% to 100% duty cycle
fCOUNTER
ATR= FFDh
FFFh
COUNTER
FFDh
FFEh
FFDh
FFEh
FFFh
FFDh
FFEh
DCRx=000h
DCRx=FFDh
DCRx=FFEh
DCRx=000h
t
Dead time generation
A dead time can be inserted between PWM0 and PWM1 using the DTGR register. This is
required for half-bridge driving where PWM signals must not be overlapped. The non-
overlapping PWM0/PWM1 signals are generated through a programmable dead time by
setting the DTE bit.
Dead time = DT[6:0] × Tcounter1
DTGR[7:0] is buffered inside so as to avoid deforming the current PWM cycle. The DTGR
effect will take place only after an overflow.
Note:
1
2
Dead time is generated only when DTE=1 and DT[6:0] ≠ 0. If DTE is set and DT[6:0]=0,
PWM output signals will be at their reset state.
Half Bridge driving is possible only if polarities of PWM0 and PWM1 are not inverted, i.e. if
OP0 and OP1 are not set. If polarity is inverted, overlapping PWM0/PWM1 signals will be
generated.
3
Dead Time generation does not work at 1msec timebase.
86/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
On-chip peripherals
Figure 40. Dead time generation
Tcounter1
CK_CNTR1
CNTR1
DCR0
DCR0+1
OVF
ATR1
counter = DCR0
PWM 0
PWM 1
counter = DCR1
Tdt
PWM 0
PWM 1
Tdt
Tdt = DT[6:0] x Tcounter1
In the above example, when the DTE bit is set:
■
■
PWM goes low at DCR0 match and goes high at ATR1+Tdt
PWM1 goes high at DCR0+Tdt and goes low at ATR match.
With this programmable delay (Tdt), the PWM0 and PWM1 signals which are generated are
not overlapped.
Break function
The break function can be used to perform an emergency shutdown of the application being
driven by the PWM signals.
The break function is activated by the external BREAK pin. This can be selected by using
the BRSEL bit in BREAKCR register. In order to use the break function it must be previously
enabled by software setting the BPEN bit in the BREAKCR register.
The Break active level can be programmed by the BREDGE bit in the BREAKCR register.
When an active level is detected on the BREAK pin, the BA bit is set and the break function
is activated. In this case, the PWM signals are forced to BREAK value if respective OEx bit
is set in PWMCR register.
Software can set the BA bit to activate the break function without using the BREAK pin. The
BREN1 and BREN2 bits in the BREAKEN register are used to enable the break activation
on the 2 counters respectively. In Dual Timer mode, the break for PWM2 and PWM3 is
enabled by the BREN2 bit. In Single Timer mode, the BREN1 bit enables the break for all
PWM channels.
87/226
On-chip peripherals
ST7FOXF1, ST7FOXK1, ST7FOXK2
When a break function is activated (BA bit =1 and BREN1/BREN2 =1):
■
The break pattern (PWM[3:0] bits in the BREAKCR) is forced directly on the PWMx
output pins if respective OEx is set. (after the inverter).
■
■
■
■
The 12-bit PWM counter CNTR1 is put to its reset value, i.e. 00h (if BREN1 = 1).
The 12-bit PWM counter CNTR2 is put to its reset value,i.e. 00h (if BREN2 = 1).
ATR1, ATR2, Preload and Active DCRx are put to their reset values.
Counters stop counting.
When the break function is deactivated after applying the break (BA bit goes from 1 to 0 by
software), Timer takes the control of PWM ports.
Note:
The break function of the ST7FOXK2 is different from the break function of the
ST7FOXF1/ST7FOXK1. Refer to Figure 41: ST7FOXF1/ST7FOXK1 Block diagram of break
function on page 88 and Figure 42: ST7FOXK2 Block diagram of break function on page 89
Figure 41. ST7FOXF1/ST7FOXK1 Block diagram of break function
BRSEL BREDGE
BREAKCR register
BREAK pin
Level
Selection
BREAKCR register
OEx
BA
BPEN PWM3 PWM2 PWM1 PWM0
PWM0
PWM1
PWM2
PWM3
(Inverters)
PWM0
PWM1
PWM2
PWM3
BREAKEN register
PWM0/1 Break Enable
PWM2/3 Break Enable
BREN2 BREN1
ENCNTR2 bit
88/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
On-chip peripherals
Figure 42. ST7FOXK2 Block diagram of break function
BREAK1 pin
Level
Selection
Comparator1
BREAKCR1 register
OEx
BR1EDGE
BA1 BP1EN PWM3 PWM2 PWM1 PWM0
BR1SEL
PWM0
PWM1
(Inverters)
PWM2
PWM3
PWM0
PWM1
PWM2
PWM3
BREN1 bit
BREN2 bit
0
1
PWM0/1 Break Enable
PWM2/3 Break Enable
0
1
ENCNTR2 bit
BREAKCR2 register
BR2EDGE BA2 BP2EN
-
-
SWBR2SWBR1
BR2SEL
BREAK2 pin
Comparator2
Level
Selection
Output compare mode
To use this function, load a 12-bit value in the Preload DCRxH and DCRxL registers.
When the 12-bit upcounter CNTR1 reaches the value stored in the Active DCRxH and
DCRxL registers, the CMPFx bit in the PWMxCSR register is set and an interrupt request is
generated if the CMPIE bit is set.
In Single Timer mode the output compare function is performed only on CNTR1. The
difference between both the modes is that, in Single Timer mode, CNTR1 can be compared
with any of the four DCR registers, and in Dual Timer mode, CNTR1 is compared with DCR0
or DCR1 and CNTR2 is compared with DCR2 or DCR3.
Note:
1
2
The output compare function is only available for DCRx values other than 0 (reset value).
Duty cycle registers are buffered internally. The CPU writes in Preload Duty Cycle registers
and these values are transferred in Active Duty Cycle registers after an overflow event if the
corresponding transfer bit (TRANx bit) is set. Output compare is done by comparing these
active DCRx values with the counters.
89/226
On-chip peripherals
ST7FOXF1, ST7FOXK1, ST7FOXK2
Figure 43. Block diagram of output compare mode (single timer)
DCRx
PRELOAD DUTY CYCLE REG0/1/2/3
(ATCSR2) TRAN1
(ATCSR)
OVF
ACTIVE DUTY CYCLE REGx
CNTR1
OUTPUT COMPARE CIRCUIT
COUNTER 1
CMPFx (PWMxCSR)
CMPIE (ATCSR)
CMP
INTERRUPT REQUEST
Input capture mode
The 12-bit ATICR register is used to latch the value of the 12-bit free running upcounter
CNTR1 after a rising or falling edge is detected on the ATIC pin. When an Input Capture
occurs, the ICF bit is set and the ATICR register contains the value of the free running
upcounter. An IC interrupt is generated if the ICIE bit is set. The ICF bit is reset by reading
the ATICRH/ATICRL register when the ICF bit is set. The ATICR is a read only register and
always contains the free running upcounter value which corresponds to the most recent
Input Capture. Any further Input Capture is inhibited while the ICF bit is set.
Figure 44. Block diagram of input capture mode
ATIC
12-BIT INPUT CAPTURE REGISTER
IC INTERRUPT
ATICR
ATCSR
REQUEST
ICF
ICIE
CK1
CK0
fLTIMER
(1 ms
timebase
@ 8MHz)
12-BIT UPCOUNTER1
12-BIT AUTORELOAD REGISTER
CNTR1
ATR1
fCPU
OFF
90/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
On-chip peripherals
Figure 45. Input capture timing diagram
fCOUNTER
COUNTER1
ATIC PIN
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
INTERRUPT
ATICR READ
INTERRUPT
ICF FLAG
09h
xxh
04h
t
Long range input capture
Pulses that last more than 8 µs can be measured with an accuracy of 4 µs if f
MHz in the following conditions:
equals 8
OSC
■
The 12-bit AT4 timer is clocked by the Lite timer (RTC pulse: CK[1:0] = 01 in the ATCSR
register)
■
The ICS bit in the ATCSR2 register is set so that the LTIC pin is used to trigger the AT4
timer capture.
■
■
The signal to be captured is connected to LTIC pin
Input Capture registers LTICR, ATICRH and ATICRL are read
This configuration allows to cascade the Lite timer and the 12-bit AT4 timer to get a 20-bit
Input Capture value. Refer to Figure 46.
Figure 46. Long range input capture block diagram
LTICR
8 LSB bits
8-bit Input Capture register
8-bit Timebase Counter1
f
OSC/32
LITE TIMER
12-bit ARTIMER
20
cascaded
bits
ATR1
12-bit AutoReload register
f
CNTR1
LTIMER
f
ICS
cpu
12-bit Upcounter1
OFF
LTIC
ATIC
ATICR
1
0
12 MSB bits
12-bit Input Capture register
91/226
On-chip peripherals
ST7FOXF1, ST7FOXK1, ST7FOXK2
Since the Input Capture flags (ICF) for both timers (AT4 timer and LT timer) are set when
signal transition occurs, software must mask one interrupt by clearing the corresponding
ICIE bit before setting the ICS bit.
If the ICS bit changes (from 0 to 1 or from 1 to 0), a spurious transition might occur on the
Input Capture signal because of different values on LTIC and ATIC. To avoid this situation, it
is recommended to do as follows:
1. First, reset both ICIE bits.
2. Then set the ICS bit.
3. Reset both ICF bits.
4. And then set the ICIE bit of desired interrupt.
Computing a pulse length in long Input Capture mode is not straightforward since both
timers are used. The following steps are required:
1. At the first Input Capture on the rising edge of the pulse, we assume that values in the
registers are the following:
–
–
–
–
LTICR = LT1
ATICRH = ATH1
ATICRL = ATL1
Hence ATICR1 [11:0] = ATH1 & ATL1. Refer to Figure 47 on page 93.
2. At the second Input Capture on the falling edge of the pulse, we assume that the values
in the registers are as follows:
–
–
–
–
LTICR = LT2
ATICRH = ATH2
ATICRL = ATL2
Hence ATICR2 [11:0] = ATH2 & ATL2.
Now pulse width P between first capture and second capture is given by:
P = decimal × (F9 – LT1 + LT2 + 1) × 0.004ms
+ decimal((FFF × N) + N + ATICR2 – ATICR1 – 1) × 1ms
where N is the number of overflows of 12-bit CNTR1.
92/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
On-chip peripherals
Figure 47. Long range input capture timing diagram
fOSC/32
_ _ _
_ _ _
_ _ _
_ _ _
_ _ _
TB Counter1
F9h
00h
LT1
F9h
00h
LT2
_ _ _
_ _ _
CNTR1
ATH1 & ATL1
ATH2 & ATL2
LTIC
00h
0h
LT1
LT2
LTICR
ATH2
ATH1
ATL1
ATICRH
ATICRL
00h
ATL2
ATICR = ATICRH[3:0] & ATICRL[7:0]
93/226
On-chip peripherals
ST7FOXF1, ST7FOXK1, ST7FOXK2
One pulse mode
One Pulse mode can be used to control PWM2/3 signal with an external LTIC pin. This
mode is available only in Dual Timer mode i.e. only for CNTR2, when the OP_EN bit in
PWM3CSR register is set.
One Pulse mode is activated by the external LTIC input. The active edge of the LTIC pin is
selected by the OPEDGE bit in the PWM3CSR register.
After getting the active edge of the LTIC pin, CNTR2 is reset (000h) and PWM3 is set to
high. CNTR2 starts counting from 000h, when it reaches the active DCR3 value then PWM3
goes low. Till this time, any further transitions on the LTIC signal will have no effect. If there
are LTIC transitions after CNTR2 reaches DCR3 value, CNTR2 is reset again and PWM3
goes high.
If there is no LTIC active edge, CNTR2 counts until it reaches the ATR2 value, then it is reset
again and PWM3 is set to high. The counter again starts counting from 000h, when it
reaches the active DCR3 value PWM3 goes low, the counter counts until it reaches ATR2, it
resets and PWM3 is set to high and so on.
The same operation applies for PWM2, but in this case the comparison is done on DCR2.
OP_EN and OPEDGE bits take effect on the fly and are not synchronized with Counter 2
overflow. The output bit OP2/3 can be used to inverse the polarity of PWM2/3 in one-pulse
mode. The update of these bits (OP2/3) is synchronized with the counter 2 overflow, they
will be updated if the TRAN2 bit is set.
The time taken from activation of LTIC input and CNTR2 reset is between 1 and 2 t
CPU
cycles, that is, 125 ns to 250 ns (with 8-MHz f
).
CPU
Lite timer Input Capture interrupt should be disabled while 12-bit ARtimer is in One Pulse
mode. This is to avoid spurious interrupts.
The priority of the various conditions for PWM3 is the following: Break > one-pulse mode
with active LTIC edge > Forced overflow by s/w > one-pulse mode without active LTIC edge
> normal PWM operation.
It is possible to update DCR2/3 and OP2/3 at the counter 2 reset, the update is
synchronized with the counter reset. This is managed by the overflow interrupt which is
generated if counter is reset either due to ATR match or active pulse at LTIC pin. DCR2/3
and OP2/3 update in one-pulse mode is performed dynamically using a software force
update. DCR3 update in this mode is not synchronized with any event. That may lead to a
longer next PWM3 cycle duration than expected just after the change.
In One Pulse mode ATR2 value must be greater than DCR2/3 value for PWM2/3. (opposite
to normal PWM mode).
If there is an active edge on the LTIC pin after the counter has reset due to an ATR2 match,
then the timer again gets reset and appears as modified Duty cycle depending on whether
the new DCR value is less than or more than the previous value.
The TRAN2 bit should be set along with the FORCE2 bit with the same instruction after a
write to the DCR register.
ATR2 value should be changed after an overflow in one pulse mode to avoid any irregular
PWM cycle.
When exiting from one pulse mode, the OP_EN bit in the PWM3CSR register should be
reset first and then the ENCNTR2 bit (if counter 2 must be stopped).
94/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
On-chip peripherals
How to enter one pulse mode
The steps required to enter One Pulse mode are the following:
1. Load ATR2H/ATR2L with required value.
2. Load DCR3H/DCR3L for PWM3. ATR2 value must be greater than DCR3.
3. Set OP3 in PWM3CSR if polarity change is required.
4. Select CNTR2 by setting ENCNTR2 bit in ATCSR2.
5. Set TRAN2 bit in ATCSR2 to enable transfer.
6. "Wait for Overflow" by checking the OVF2 flag in ATCSR2.
7. Select counter clock using CK<1:0> bits in ATCSR.
8. Set OP_EN bit in PWM3CSR to enable one-pulse mode.
9. Enable PWM3 by OE3 bit of PWMCR.
The "Wait for Overflow" in step 6 can be replaced by a forced update.
Follow the same procedure for PWM2 with the bits corresponding to PWM2.
Note:
When break is applied in one-pulse mode, CNTR2, DCR2/3 & ATR2 registers are reset. So,
these registers have to be initialized again when break is removed.
Figure 48. Block diagram of one pulse mode
LTIC pin
Edge
Selection
12-bit Upcounter 2
PWM
Generation
OPEDGE OP_EN
PWM2/3
12-bit AutoReload register 2
12-bit Active DCR2/3
PWM3CSR register
OP2/3
Figure 49. One pulse mode and PWM timing diagram
fcounter2
000
DCR2/3
ATR2 000
CNTR2
000
DCR2/3
LTIC
PWM2/3
fcounter2
OVF
ATR2
DCR2/3
OVF
ATR2
DCR2/3
ATR2
OVF
CNTR2
LTIC
PWM2/3
Note 1: When OP_EN=0, LTIC edges are not taken into account as the timer runs in PWM mode.
95/226
On-chip peripherals
ST7FOXF1, ST7FOXK1, ST7FOXK2
Figure 50. Dynamic DCR2/3 update in one pulse mode
fcounter2
(DCR3)
old
(DCR3)
new
CNTR2
000
ATR2 000
000
FFF
LTIC
FORCE2
TRAN2
DCR2/3
(DCR2/3)old
(DCR2/3)new
PWM2/3
extra PWM3 period due to DCR3
update dynamically in one-pulse
mode.
96/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
Force update
On-chip peripherals
In order not to wait for the counter overflow to load the value into active DCRx registers, a
x
programmable counter overflow is provided. For both counters, a separate bit is provided
x
which when set, make the counters start with the overflow value, i.e. FFFh. After overflow,
the counters start counting from their respective auto reload register values.
These bits are FORCE1 and FORCE2 in the ATCSR2 register. FORCE1 is used to force an
overflow on Counter 1 and, FORCE2 is used for Counter 2. These bits are set by software
and reset by hardware after the respective counter overflow event has occurred.
This feature can be used at any time. All related features such as PWM generation, Output
Compare, Input Capture, One-pulse (refer to Figure 50: Dynamic DCR2/3 update in one
pulse mode) etc. can be used this way.
Figure 51. Force overflow timing diagram
fCNTRx
FORCEx
CNTRx
FFF
ARRx
E03
E04
FORCE2
FORCE1
ATCSR2 register
10.2.4
10.2.5
Low power modes
Table 35. Effect of low power modes on autoreload timer
Mode
Description
Wait
Halt
No effect on AT timer
AT timer halted.
Interrupts
Table 36. Description of interrupt events
Event
Flag
Enable
Control bit
Exit from
Wait
Exit from
Exit from
Active-Halt
Interrupt Event
Halt
Overflow Event
AT4 IC Event
OVF1
ICF
OVIE1
ICIE
Yes
Yes
Yes
No
No
No
Yes
No
No
Overflow Event2
OVF2
OVIE2
Note:
The AT4 IC is connected to an interrupt vector. The OVF event is mapped on a separate
vector (see Interrupts chapter).
They generate an interrupt if the enable bit is set in the ATCSR register and the interrupt
mask in the CC register is reset (RIM instruction).
97/226
On-chip peripherals
ST7FOXF1, ST7FOXK1, ST7FOXK2
10.2.6
Register description
Timer control status register (ATCSR)
Reset value: 0x00 0000 (x0h)
7
0
0
ICF
ICIE
CK1
CK0
OVF1
OVFIE1
CMPIE
Read / Write
Bit 7 = Reserved
Bit 6 = ICF Input Capture flag
This Bit is set by hardware and cleared by software by reading the ATICR register (a
read access to ATICRH or ATICRL clears this flag). Writing to this bit does not change
the bit value.
0: No input capture
1: An input capture has occurred
Bit 5 = ICIE IC Interrupt Enable
bit
This bit is set and cleared by software.
0: Input Capture Interrupt Disabled
1: Input Capture Interrupt Enabled
Bits 4:3 = CK[1:0] Counter Clock Selection
bits
These bits are set and cleared by software and cleared by hardware after a reset. they
select the clock frequency of the counter.
Table 37. Counter clock selection
Counter clock selection
CK1
CK0
OFF
selection forbidden
fLTIMER (1 ms timebase @ 8 MHz)
fCPU
0
1
0
1
0
1
1
0
Bit 2 = OVF1 Overflow flag
This bit is set by hardware and cleared by software by reading the ATCSR register. It
indicates the transition of the Counter1 CNTR1 from FFFh to ATR1 value.
0: No Counter Overflow Occurred
1: Counter Overflow Occurred
Bit 1 = OVFIE1 Overflow Interrupt Enable
bit
This bit is read/write by software and cleared by hardware after a reset.
0: Overflow Interrupt Disabled.
1: Overflow Interrupt Enabled.
98/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
On-chip peripherals
Bit 0 = CMPIE Compare Interrupt Enable
bit
This bit is read/write by software and cleared by hardware after a reset. it can be used
to mask the interrupt generated when any of the cmpfx bit is set.
0: Output Compare Interrupt Disabled.
1: Output Compare Interrupt Enabled.
Counter register 1 High (CNTR1H)
Reset value: 0000 0000 (00h)
15
0
8
CNTR1_
11
CNTR1_
10
0
0
0
CNTR1_9 CNTR1_8
Read only
Counter register 1 Low (CNTR1L)
Reset value: 0000 0000 (00h)
7
0
CNTR1_7 CNTR1_6 CNTR1_5 CNTR1_4 CNTR1_3 CNTR1_2 CNTR1_1 CNTR1_0
Read only
Bits 15:12 = Reserved
Bits 11:0 = CNTR1[11:0] Counter value
This 12-bit register is read by software and cleared by hardware after a reset. The
counter CNTR1 increments continuously as soon as a counter clock is selected. To
obtain the 12-bit value, software should read the counter value in two consecutive read
operations. As there is no latch, it is recommended to read LSB first. In this case,
CNTR1H can be incremented between the two read operations and to have an
accurate result when f
=f
, special care must be taken when CNTR1L values
timer CPU
close to FFh are read.
When a counter overflow occurs, the counter restarts from the value specified in the
ATR1 register.
99/226
On-chip peripherals
ST7FOXF1, ST7FOXK1, ST7FOXK2
Autoreload register (ATR1H)
Reset value: 0000 0000 (00h)
15
8
0
0
0
0
ATR11
Read/write
ATR10
ATR9
ATR8
Autoreload register (ATR1L)
Reset value: 0000 0000 (00h)
7
0
ATR7
ATR6
ATR5
ATR4
ATR3
ATR2
ATR1
ATR0
Read/write
Bits 11:0 = ATR1[11:0] Autoreload register 1:
This is a 12-bit register which is written by software. The ATR1 register value is
automatically loaded into the upcounter CNTR1 when an overflow occurs. The register
value is used to set the PWM frequency.
PWM output control register (PWMCR)
Reset value: 0000 0000 (00h)
7
0
0
OE3
0
OE2
Read/write
Bits 7:0 = OE[3:0] PWMx output enable bits
0
OE1
0
OE0
These bits are set and cleared by software and cleared by hardware after a reset.
0: PWM mode disabled. PWMx Output Alternate function disabled (I/O pin free for
general purpose I/O)
1: PWM mode enabled
PWMX control status register (PWMxCSR)
Reset value: 0000 0000 (00h)
7
0
0
0
0
0
OP_EN
Read/write
OPEDGE
OPx
CMPFx
Bits 7:4= Reserved, must be kept cleared.
Bit 3 = OP_EN One Pulse Mode Enable
bit
100/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
On-chip peripherals
This bit is read/write by software and cleared by hardware after a reset. This bit enables
the One Pulse feature for PWM2 and PWM3 (only available for PWM3CSR)
0: One Pulse mode disable for PWM2/3.
1: One Pulse mode enable for PWM2/3.
Bit 2 = OPEDGE One Pulse Edge Selection
bit
This bit is read/write by software and cleared by hardware after a reset. This bit selects
the polarity of the LTIC signal for One Pulse feature. This bit will be effective only if
OP_EN bit is set (only available for PWM3CSR)
0: Falling edge of LTIC is selected.
1: Rising edge of LTIC is selected.
Bit 1 = OPx PWMx Output Polarity
bit
This bit is read/write by software and cleared by hardware after a reset. This bit selects
the polarity of the PWM signal.
0: The PWM signal is not inverted.
1: The PWM signal is inverted.
Bit 0 = CMPFx PWMx Compare flag
This bit is set by hardware and cleared by software by reading the PWMxCSR register.
It indicates that the upcounter value matches the Active DCRx register value.
0: Upcounter value does not match DCRx value.
1: Upcounter value matches DCRx value.
Break control register 1 (BREAKCR1)
Reset value: 0000 0000 (00h)
7
0
BR1SEL BR1EDGE
BA1
BP1EN
PWM3
PWM2
PWM1
PWM0
Read/write
Bit 7 = BR1SEL Break 1 input selection bit (only available on ST7FOXK2, reserved for
ST7FOXF1/ST7FOXK1)
This bit is read/write by software and cleared by hardware after reset. It selects the
active Break 1 signal from external BREAK1 pin and the output of the comparator.
0: External BREAK1 pin is selected for break mode.
1: Comparator 1 output is selected for break mode.
Bit 6 = BR1EDGE Break 1 input edge selection
ST7FOXF1/ST7FOXK1)
bit (BREDGE on
This bit is read/write by software and cleared by hardware after reset. It selects the
active level of Break 1 signal.
0: Low level of Break 1selected as active level
1: High level of Break 1selected as active level
101/226
On-chip peripherals
ST7FOXF1, ST7FOXK1, ST7FOXK2
Bit 5 = BA1 Break 1 Active
ST7FOXF1/ST7FOXK1)
bit (BA on
This bit is read/write by software, cleared by hardware after reset and set by hardware
when the active level defined by the BR1EDGE bit is applied on the BREAK1 pin. It
activates/deactivates the Break 1function.
0: Break 1not active
1: Break 1active
Bit 4 = BP1EN Break 1Pin Enable
ST7FOXF1/ST7FOXK1)
bit (BPEN on
This bit is read/write by software and cleared by hardware after Reset.
0: Break 1pin disabled
1: Break 1pin enabled
Bits 3:0 = PWM[3:0] Break Pattern
bits
These bits are read/write by software and cleared by hardware after a reset. They are
used to force the four PWMx output signals into a stable state when the Break function
is active and corresponding OEx bit is set.
102/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
On-chip peripherals
Break control register 2 (BREAKCR2)
Reset value: 0000 0000 (00h)
7
0
BR2SEL BR2EDGE
BA2
BP2EN
Read/write
-
-
SWBR2
SWBR1
Note:
This register is available on ST7FOXK2 only
Bit 7 = BR2SEL Break 2 input selection bit
This bit is read/write by software and cleared by hardware after reset. It selects the
active Break 2 signal from external BREAK2 pin and the output of the comparator.
0: External BREAK2 pin is selected for break mode.
1: Comparator 2 output is selected for break mode.
Bit 6 = BR2EDGE Break 2 input edge selection
bit
This bit is read/write by software and cleared by hardware after reset. It selects the
active level of Break 2 signal.
0: Low level of Break 2 selected as active level
1: High level of Break 2 selected as active level
Bit 5 = BA2 Break 2 Active
bit
This bit is read/write by software, cleared by hardware after reset and set by hardware
when the active level defined by the BR2EDGE bit is applied on the BREAK2 pin. It
activates/deactivates the Break 2 function.
0: Break 2 not active
1: Break 2 active
Bit 4 = BP2EN Break 2 pin enable
bit
This bit is read/write by software and cleared by hardware after Reset.
0: BREAK2 pin disabled
1: BREAK2 pin enabled
Bits 3:2 = Reserved, must be kept cleared
Bit 1 = SWBR2 Switch Break for counter 2
bit
This bit is read/write by software. While BREN2 is set, it selects BA1 or BA2 to control
PWM2/3 if ENCNTR2 bit is set.
0: BA1 selected
1: BA2 selected
Bit 0 = SWBR1 Switch Break for counter 1
bit
This bit is read/write by software. While BREN1 is set, it selects BA1 or BA2 to control
PWM0/1 by default and also PWM2/3 if ENCNTR2 bit is reset.
0: BA1 selected
1: BA2 selected
103/226
On-chip peripherals
ST7FOXF1, ST7FOXK1, ST7FOXK2
PWMx Duty Cycle register High (DCRxH)
Reset value: 0000 0000 (00h)
15
8
0
0
0
0
DCR11
Read/write
DCR10
DCR9
DCR8
Bits 15:12 = Reserved.
PWMx Duty Cycle register Low (DCRxL)
Reset value: 0000 0000 (00h)
7
0
DCR7
DCR6
DCR5
DCR4
DCR3
DCR2
DCR1
DCR0
Read/write
Bits 11:0 = DCRx[11:0] PWMx Duty Cycle Value: this 12-bit value is written by software. It
defines the duty cycle of the corresponding PWM output signal (see Figure 38).
In PWM mode (OEx=1 in the PWMCR register) the DCR[11:0] bits define the duty cycle of
the PWMx output signal (see Figure 38). In Output Compare mode, they define the value to
be compared with the 12-bit upcounter value.
Input Capture register High (ATICRH)
Reset value: 0000 0000 (00h)
15
0
8
0
0
0
ICR11
Read only
ICR10
ICR9
ICR8
Bits 15:12 = Reserved.
104/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
On-chip peripherals
Input Capture register Low (ATICRL)
Reset value: 0000 0000 (00h)
7
0
ICR7
ICR6
ICR5
ICR4
Read only
Bits 11:0 = ICR[11:0] Input Capture Data.
ICR3
ICR2
ICR1
ICR0
This is a 12-bit register which is readable by software and cleared by hardware after a
reset. The ATICR register contains captured the value of the 12-bit CNTR1 register
when a rising or falling edge occurs on the ATIC or LTIC pin (depending on ICS).
Capture will only be performed when the ICF flag is cleared.
Break Enable register (BREAKEN)
Reset value: 0000 0011 (03h)
7
0
0
0
0
0
0
0
BREN2
BREN1
Read/write
Bits 7:2 = Reserved, must be kept cleared.
Bit 1 = BREN2 Break Enable for Counter 2 bit
This bit is read/write by software. It enables the break functionality for Counter2 if BA bit
is set in BREAKCR. It controls PWM2/3 if ENCNTR2 bit is set.
0: No Break applied for CNTR2
1: Break applied for CNTR2
Bit 0 = BREN1 Break Enable for Counter 1
bit
This bit is read/write by software. It enables the break functionality for Counter1. If BA
bit is set, it controls PWM0/1 by default, and controls PWM2/3 also if ENCNTR2 bit is
reset.
0: No Break applied for CNTR1
1: Break applied for CNTR1
105/226
On-chip peripherals
ST7FOXF1, ST7FOXK1, ST7FOXK2
Timer Control register 2 (ATCSR2)
Reset value: 0000 0011 (03h)
7
0
FORCE2
FORCE1
ICS
OVFIE2
Read/write
Bit 7 = FORCE2 Force Counter 2 Overflow
OVF2
ENCNTR2
TRAN2
TRAN1
bit
This bit is read/set by software. When set, it loads FFFh in the CNTR2 register. It is
reset by hardware one CPU clock cycle after counter 2 overflow has occurred.
0 : No effect on CNTR2
1 : Loads FFFh in CNTR2
Note:
Note:
This bit must not be reset by software
Bit 6 = FORCE1 Force Counter 1 Overflow
bit
This bit is read/set by software. When set, it loads FFFh in CNTR1 register. It is reset
by hardware one CPU clock cycle after counter 1 overflow has occurred.
0 : No effect on CNTR1
1 : Loads FFFh in CNTR1
This bit must not be reset by software
Bit 5 = ICS Input Capture Shorted
bit
This bit is read/write by software. It allows the ATtimer CNTR1 to use the LTIC pin for
long Input Capture.
0 : ATIC for CNTR1 Input Capture
1 : LTIC for CNTR1 Input Capture
Bit 4 = OVFIE2 Overflow interrupt 2 enable
bit
This bit is read/write by software and controls the overflow interrupt of counter2.
0: Overflow interrupt disabled.
1: Overflow interrupt enabled.
Bit 3 = OVF2 Overflow flag
This bit is set by hardware and cleared by software by reading the ATCSR2 register. It
indicates the transition of the counter2 from FFFh to ATR2 value.
0: No counter overflow occurred
1: Counter overflow occurred
Bit 2 = ENCNTR2 Enable counter2 for PWM2/3
This bit is read/write by software and switches the PWM2/3 operation to the CNTR2
counter. If this bit is set, PWM2/3 will be generated using CNTR2.
0: PWM2/3 is generated using CNTR1.
1: PWM2/3 is generated using CNTR2.
Note:
Counter 2 gets frozen when the ENCNTR2 bit is reset. When ENCNTR2 is set again, the
counter will restart from the last value.
106/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
On-chip peripherals
Bit 1= TRAN2 Transfer enable2
bit
This bit is read/write by software, cleared by hardware after each completed transfer
and set by hardware after reset. It controls the transfers on CNTR2.
It allows the value of the Preload DCRx registers to be transferred to the Active DCRx
registers after the next overflow event.
The OPx bits are transferred to the shadow OPx bits in the same way.
Note:
1
2
DCR2/3 transfer will be controlled using this bit if ENCNTR2 bit is set.
This bit must not be reset by software
Bit 0 = TRAN1 Transfer enable 1
bit
This bit is read/write by software, cleared by hardware after each completed transfer
and set by hardware after reset. It controls the transfers on CNTR1. It allows the value
of the Preload DCRx registers to be transferred to the Active DCRx registers after the
next overflow event.
The OPx bits are transferred to the shadow OPx bits in the same way.
Note:
1
2
3
DCR0,1 transfers are always controlled using this bit.
DCR2/3 transfer will be controlled using this bit if ENCNTR2 is reset.
This bit must not be reset by software
Autoreload register 2 (ATR2H)
Reset value: 0000 0000 (00h)
15
0
8
0
0
0
ATR11
Read/write
ATR10
ATR9
ATR8
Autoreload register (ATR2L)
Reset value: 0000 0000 (00h)
7
0
ATR7
ATR6
ATR5
ATR4
ATR3
ATR2
ATR1
ATR0
Read/write
Bits 11:0 = ATR2[11:0] Autoreload register 2
This is a 12-bit register which is written by software. The ATR2 register value is
automatically loaded into the upcounter CNTR2 when an overflow of CNTR2 occurs. The
register value is used to set the PWM2/PWM3 frequency when ENCNTR2 is set.
107/226
On-chip peripherals
ST7FOXF1, ST7FOXK1, ST7FOXK2
Dead Time Generator register (DTGR)
Reset value: 0000 0000 (00h)
7
0
DTE
DT6
DT5
DT4
DT3
DT2
DT1
DT0
Read/write
Bit 7 = DTE Dead Time Enable
bit
This bit is read/write by software. It enables a dead time generation on PWM0/PWM1.
0: No Dead time insertion.
1: Dead time insertion enabled.
Bits 6:0 = DT[6:0] Dead Time value
These bits are read/write by software. They define the dead time inserted between
PWM0/PWM1. Dead time is calculated as follows:
Dead Time = DT[6:0] x Tcounter1
Note:
If DTE is set and DT[6:0]=0, PWM output signals will be at their reset state.
Table 38. Register mapping and reset values
Add.
(Hex)
Register
label
7
6
5
4
3
2
1
0
ATCSR
Reset Value
ICF
0
ICIE
0
CK1
0
CK0
0
OVF1
0
OVFIE1 CMPIE
0011
0012
0
0
0
CNTR1_1 CNTR1_1
CNTR1_
CNTR1H
Reset Value
CNTR1_9
0
0
0
0
0
1
0
0
0
8
0
CNTR1_
CNTR1_
CNTR1L
Reset Value
CNTR1_7 CNTR1_8
CNTR1_6 CNTR1_3 CNTR1_2 CNTR1_1
0013
7
0
0
0
0
0
0
0
0
0
ATR1H
Reset Value
ATR11
0
ATR10
0
ATR9
0
ATR8
0
0014
0015
0016
0017
0018
0019
001A
001B
0
0
0
0
ATR1L
Reset Value
ATR7
0
ATR6
0
ATR5
0
ATR4
0
ATR3
0
ATR2
0
ATR1
0
ATR0
0
PWMCR
Reset Value
OE3
0
OE2
0
OE1
0
OE0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PWM0CSR
Reset Value
OP0
0
CMPF0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PWM1CSR
Reset Value
OP1
0
CMPF1
0
PWM2CSR
Reset Value
OP2
0
CMPF2
0
OP_EN
0
OPEDGE
0
PWM3CSR
Reset Value
OP3
0
CMPF3
0
DCR0H
Reset Value
DCR11
0
DCR10
0
DCR9
0
DCR8
0
108/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
On-chip peripherals
Table 38. Register mapping and reset values (continued)
Add.
(Hex)
Register
label
7
6
5
4
3
2
1
0
DCR0L
Reset Value
DCR7
0
DCR6
0
DCR5
0
DCR4
0
DCR3
0
DCR2
0
DCR1
0
DCR0
0
001C
001D
001E
001F
0020
0021
0022
0023
0024
0025
DCR1H
Reset Value
DCR11
0
DCR10
0
DCR9
0
DCR8
0
0
0
0
0
DCR1L
Reset Value
DCR7
0
DCR6
0
DCR5
0
DCR4
0
DCR3
0
DCR2
0
DCR1
0
DCR0
0
DCR2H
Reset Value
DCR11
0
DCR10
0
DCR9
0
DCR8
0
0
0
0
0
DCR2L
Reset Value
DCR7
0
DCR6
0
DCR5
0
DCR4
0
DCR3
0
DCR2
0
DCR1
0
DCR0
0
DCR3H
Reset Value
DCR11
0
DCR10
0
DCR9
0
DCR8
0
0
0
0
0
DCR3L
Reset Value
DCR7
0
DCR6
0
DCR5
0
DCR4
0
DCR3
0
DCR2
0
DCR1
0
DCR0
0
ATICRH
Reset Value
ICR11
0
ICR10
0
ICR9
0
ICR8
0
0
0
0
0
ATICRL
Reset Value
ICR7
0
ICR6
0
ICR5
0
ICR4
0
ICR3
0
ICR2
0
ICR1
0
ICR0
0
FORCE2 FORCE1
ICS
0
OVFIE2
0
OVF2
0
ENCNTR2 TRAN2
TRAN1
1
ATCSR2
Reset Value
0
0
0
1
BREAKCR1
BREDGE
0
BA
0
BPEN
0
PWM3
0
PWM2
0
PWM1
0
PWM0
0
(1)
0026
0
Reset Value
ATR2H
Reset Value
ATR11
0
ATR10
0
ATR9
0
ATR8
0
0027
0028
0029
0
0
0
0
ATR2L
Reset Value
ATR7
0
ATR6
0
ATR5
0
ATR4
0
ATR3
0
ATR2
0
ATR1
0
ATR0
0
DTE
0
DT6
0
DT5
0
DT4
0
DT3
0
DT2
0
DT1
0
DT0
0
DTGR
Reset Value
BREN2 BREN1
BREAKEN
Reset Value
002A
002B
0
0
0
0
0
0
1
1
Reserved area
BREAKCR2
BR2EDGE
0
BR2SEL
0
BA2
0
BP2EN
0
SWBR2 SWBR1
(2)
002C
0
0
0
0
Reset Value
1.
2.
109/226
On-chip peripherals
ST7FOXF1, ST7FOXK1, ST7FOXK2
10.3
Lite timer 2 (LT2)
10.3.1
Introduction
The Lite timer can be used for general-purpose timing functions. It is based on two free-
running 8-bit upcounters, a watchdog function and an 8-bit Input Capture register.
10.3.2
Main features
■
Real-time Clock
–
–
One 8-bit upcounter 1 ms or 2 ms timebase period (@ 8 MHz f
)
OSC
One 8-bit upcounter with autoreload and programmable timebase period from 4µs
to 1.024 ms in 4 µs increments (@ 8 MHz f
)
OSC
–
2 Maskable timebase interrupts
■
Input Capture
8-bit Input Capture register (LTICR)
–
■
■
Maskable interrupt with wakeup from Halt mode capability
Watchdog
– Enabled by hardware or software (configurable by option byte)
– Optional reset on HALT instruction (configurable by option byte)
– Automatically resets the device unless disable bit is refreshed
– Software reset (Forced Watchdog reset)
– Watchdog reset status flag
110/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
On-chip peripherals
Figure 52. Lite timer 2 block diagram
f
/32
OSC
LTTB2
LTCNTR
Interrupt request
LTCSR2
8-bit TIMEBASE
COUNTER 2
8
0
0
0
0
0
0
TB2IE TB2F
LTARR
f
LTIMER
To 12-bit AT TImer
8-bit AUTORELOAD
REGISTER
/2
1
0
8-bit TIMEBASE
COUNTER 1
Timebase
1 or 2 ms
(@ 8 MHz
f
LTIMER
f
)
OSC
8
LTICR
8-bit
LTIC
INPUT CAPTURE
REGISTER
LTCSR1
ICIE ICF
TB
TB1IE TB1F
LTTB1 INTERRUPT REQUEST
LTIC INTERRUPT REQUEST
10.3.3
Functional description
Timebase Counter 1
The 8-bit value of Counter 1 cannot be read or written by software. After an MCU reset, it
starts incrementing from 0 at a frequency of f /32. An overflow event occurs when the
OSC
counter rolls over from F9h to 00h. If f
= 8 MHz, then the time period between two
OSC
counter overflow events is 1 ms. This period can be doubled by setting the TB bit in the
LTCSR1 register.
When Counter 1 overflows, the TB1F bit is set by hardware and an interrupt request is
generated if the TB1IE bit is set. The TB1F bit is cleared by software reading the LTCSR1
register.
Input Capture
The 8-bit Input Capture register is used to latch the free-running upcounter (Counter 1) 1
after a rising or falling edge is detected on the LTIC pin. When an Input Capture occurs, the
ICF bit is set and the LTICR register contains the counter 1 value. An interrupt is generated
if the ICIE bit is set. The ICF bit is cleared by reading the LTICR register.
The LTICR is a read-only register and always contains the data from the last Input Capture.
Input Capture is inhibited if the ICF bit is set.
111/226
On-chip peripherals
ST7FOXF1, ST7FOXK1, ST7FOXK2
Timebase Counter 2
Counter 2 is an 8-bit autoreload upcounter. It can be read by accessing the LTCNTR
register. After an MCU reset, it increments at a frequency of f /32 starting from the value
OSC
stored in the LTARR register. A counter overflow event occurs when the counter rolls over
from FFh to the LTARR reload value. Software can write a new value at any time in the
LTARR register, this value will be automatically loaded in the counter when the next overflow
occurs.
When Counter 2 overflows, the TB2F bit in the LTCSR2 register is set by hardware and an
interrupt request is generated if the TB2IE bit is set. The TB2F bit is cleared by software
reading the LTCSR2 register.
Figure 53. Input Capture timing diagram
4µs
(@ 8 MHz fOSC
)
fCPU
fOSC/32
CLEARED
BY S/W
READING
LTIC REGISTER
01h
02h
03h
04h
05h
06h
07h
8-bit COUNTER 1
LTIC PIN
ICF FLAG
07h
xxh
04h
LTICR REGISTER
t
Watchdog
When enabled using the WDGE bit, the Watchdog generates a reset after 2 ms (@ = 8 MHz
).
f
OSC
To prevent this watchdog reset occurring, software must set the WDGD bit. The WDGD bit is
cleared by hardware after t . This means that software must write to the WDGD bit at
WDG
regular intervals to prevent a watchdog reset occurring. Refer to Figure 54.
Note: Software can use the timebase feature to set the WDGD bit at 1 or 2 ms intervals.
A Watchdog reset can be forced at any time by setting the WDGRF bit.
The WDGRF bit also acts as a flag, indicating that the Watchdog was the source of the
reset. It is automatically cleared after it has been read.
Hardware Watchdog Option
If Hardware Watchdog is selected by option byte, the watchdog is always active and the
WDGE bit in the LTCSR1 is not used.
Refer to the Option byte description.
Using Halt mode with the Watchdog (option)
If the Watchdog reset on HALT option is not selected by option byte, the Halt mode can be
used when the watchdog is enabled.
112/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
On-chip peripherals
In this case, the HALT instruction stops the oscillator. When the oscillator is stopped, the Lite
timer stops counting and is no longer able to generate a Watchdog reset until the
microcontroller receives an external interrupt or a reset.
If an external interrupt is received, the WDG restarts counting after 4096 CPU clocks. If a
reset is generated, the Watchdog is disabled (reset state).
Recommendations
■
■
■
Make sure that an external event is available to wake up the microcontroller from Halt
mode.
Before executing the HALT instruction, refresh the WDGD bit, to avoid an unexpected
Watchdog reset immediately after waking up the microcontroller.
When using an external interrupt to wake up the microcontroller, reinitialize the
corresponding I/O as “Input Pull-up with Interrupt” before executing the HALT
instruction. The main reason for this is that the I/O may be wrongly configured due to
external interference or by an unforeseen logical condition.
■
For the same reason, reinitialize the level sensitiveness of each external interrupt as a
precautionary measure.
Figure 54. Watchdog timing diagram
HARDWARE CLEARS
WDGD BIT
t
WDG
(2ms @ 8MHz f
)
OSC
f
WDG
WDGD BIT
INTERNAL
WATCHDOG
RESET
SOFTWARE SETS
WDGD BIT
WATCHDOG RESET
10.3.4
Low power modes
Table 39. Effect of low power modes on Lite timer 2
Mode
Description
No effect on Lite timer
Slow
(this peripheral is driven directly by fOSC/32)
No effect on Lite timer
Wait
Active Halt
Halt
No effect on Lite timer
Lite timer stops counting
113/226
On-chip peripherals
ST7FOXF1, ST7FOXK1, ST7FOXK2
10.3.5
Interrupts
Table 40. Description of interrupt events
Exit
Enable
Event
Flag
Exit
from
Wait
Exit
from
Halt
from
Active
Halt
Interrupt Event
Control
Bit
Timebase 1 Event
Timebase 2 Event
IC Event
TB1F
TB2F
ICF
TB1IE
TB2IE
ICIE
Yes
No
No
Yes
No
The TBxF and ICF interrupt events are connected to separate interrupt vectors (see
Section 7: Interrupts).
They generate an interrupt if the enable bit is set in the LTCSR1 or LTCSR2 register and the
interrupt mask in the CC register is reset (RIM instruction).
10.3.6
Register description
Lite Timer Control/Status register 2 (LTCSR2)
Reset value: 0000 0000 (00h)
7
0
0
0
0
0
0
0
TB2IE
TB2F
Read / Write
Bits 7:2 = Reserved, must be kept cleared.
Bit 1 = TB2IE Timebase 2 Interrupt enable
This bit is set and cleared by software.
0: Timebase (TB2) interrupt disabled
1: Timebase (TB2) interrupt enabled
bit
Bit 0 = TB2F Timebase 2 Interrupt flag
This bit is set by hardware and cleared by software reading the LTCSR register. Writing
to this bit has no effect.
0: No Counter 2 overflow
1: A Counter 2 overflow has occurred
114/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
On-chip peripherals
Lite Timer Autoreload register (LTARR)
Reset value: 0000 0000 (00h)
7
0
AR7
AR6
AR5
AR4
Read / Write
Bits 7:0 = AR[7:0] Counter 2 Reload value
AR3
AR2
AR1
AR0
These bits register is read/write by software. The LTARR value is automatically loaded into
Counter 2 (LTCNTR) when an overflow occurs.
Lite Timer Counter 2 (LTCNTR)
Reset value: 0000 0000 (00h)
7
0
CNT7
CNT6
CNT5
CNT4
Read only
Bits 7:0 = CNT[7:0] Counter 2 Reload value
CNT3
CNT2
CNT1
CNT0
This register is read by software. The LTARR value is automatically loaded into Counter
2 (LTCNTR) when an overflow occurs.
Lite Timer Control/status register (LTCSR1)
Reset value: 0x00 0000 (x0h)
7
0
ICIE
ICF
TB
TB1IE
TB1F
Read / Write
Bit 7 = ICIE Interrupt Enable
bit
This bit is set and cleared by software.
0: Input Capture (IC) interrupt disabled
1: Input Capture (IC) interrupt enabled
Bit 6 = ICF Input Capture flag
This bit is set by hardware and cleared by software by reading the LTICR register.
Writing to this bit does not change the bit value.
0: No Input Capture
1: An Input Capture has occurred
Note:
After an MCU reset, software must initialize the ICF bit by reading the LTICR register
115/226
On-chip peripherals
ST7FOXF1, ST7FOXK1, ST7FOXK2
Bit 5 = TB Timebase period selection
bit
This bit is set and cleared by software.
0: Timebase period = t
1: Timebase period = t
* 8000 (1 ms @ 8 MHz)
OSC
OSC
* 16000 (2 ms @ 8 MHz)
Bit 4 = TB1IE Timebase Interrupt enable
bit
This bit is set and cleared by software.
0: Timebase (TB1) interrupt disabled
1: Timebase (TB1) interrupt enabled
Bit 3 = TB1F Timebase Interrupt flag
This bit is set by hardware and cleared by software reading the LTCSR register. Writing
to this bit has no effect.
0: No counter overflow
1: A counter overflow has occurred
Bits 2:0 = Reserved, must be kept cleared.
Lite Timer Input Capture register (LTICR)
Reset value: 0000 0000 (00h)
7
0
ICR7
ICR6
ICR5
ICR4
ICR3
ICR2
ICR1
ICR0
Read only
Bits 7:0 = ICR[7:0] Input Capture value
These bits are read by software and cleared by hardware after a reset. If the ICF bit in the
LTCSR is cleared, the value of the 8-bit up-counter will be captured when a rising or falling
edge occurs on the LTIC pin.
Table 41. Lite Timer register mapping and reset values
Address
(Hex.)
Register
label
7
6
5
4
3
2
1
0
LTCSR2
Reset Value
TB2IE
0
TB2F
0
0C
0D
0E
0F
10
0
0
0
0
0
0
LTARR
Reset Value
AR7
0
AR6
0
AR5
0
AR4
0
AR3
0
AR2
0
AR1
0
AR0
0
LTCNTR
Reset Value
CNT7
0
CNT6
0
CNT5
0
CNT4
0
CNT3
0
CNT2
0
CNT1
0
CNT0
0
LTCSR1
Reset Value
ICIE
0
ICF
x
TB
0
TB1IE
0
TB1F
0
0
0
0
LTICR
Reset Value
ICR7
0
ICR6
0
ICR5
0
ICR4
0
ICR3
0
ICR2
0
ICR1
0
ICR0
0
116/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
On-chip peripherals
10.4
16-bit timer
10.4.1
Introduction
The timer consists of a 16-bit free-running counter driven by a programmable prescaler.
It may be used for a variety of purposes, including pulse length measurement of up to two
input signals (input capture) or generation of up to two output waveforms (output compare
and PWM).
Pulse lengths and waveform periods can be modulated from a few microseconds to several
milliseconds using the timer prescaler and the CPU clock prescaler.
10.4.2
Main features
■
■
■
Programmable prescaler: f
divided by 2, 4 or 8.
CPU
Overflow status flag and maskable interrupt
External clock input (must be at least 4 times slower than the CPU clock speed) with
the choice of active edge
■
■
Output compare functions with
–
–
–
–
2 dedicated 16-bit registers
2 dedicated programmable signals
2 dedicated status flags
1 dedicated maskable interrupt
Input capture functions with
–
–
–
–
2 dedicated 16-bit registers
2 dedicated active edge selection signals
2 dedicated status flags
1 dedicated maskable interrupt
■
■
■
■
Pulse width modulation mode (PWM)
One pulse mode
Reduced power mode
5 alternate functions on I/O ports (ICAP1, ICAP2, OCMP1, OCMP2, EXTCLK)
Note:
Some timer pins may not be available (not bonded) in some devices. Refer to Section 2: Pin
description on page 15.
The block diagram is shown in Figure 55.
When reading an input signal on a non-bonded pin, the value is always ‘1’.
10.4.3
Functional description
Counter
The main block of the programmable timer is a 16-bit free running upcounter and its
associated 16-bit registers. The 16-bit registers are made up of two 8-bit registers called
high and low.
117/226
On-chip peripherals
ST7FOXF1, ST7FOXK1, ST7FOXK2
Counter register (CR)
■
■
Counter high register (CHR) is the most significant byte (MSB).
Counter low register (CLR) is the least significant byte (LSB).
Alternate counter register (ACR)
■
■
Alternate counter high register (ACHR) is the MSB.
Alternate counter low register (ACLR) is the LSB.
These two read-only 16-bit registers contain the same value but with the difference that
reading the ACLR register does not clear the TOF bit (timer overflow flag), located in the
status register, (SR), (see16-bit read sequence (from either the counter register or the
alternate counter register) on page 120).
Writing in the CLR register or ACLR register resets the free running counter to the FFFCh
value. Both counters have a reset value of FFFCh (this is the only value which is reloaded in
the 16-bit timer). The reset value of both counters is also FFFCh in One Pulse mode and
PWM mode.
The timer clock depends on the clock control bits of the CR2 register, as illustrated in
Table 37. The value in the counter register repeats every 131 072, 262 144 or 524 288 CPU
clock cycles depending on the CC[1:0] bits. The timer frequency can be f
/2, f
/4,
CPU
CPU
f
/8 or an external frequency.
CPU
118/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
Figure 55. Timer block diagram
On-chip peripherals
Internal bus
f
CPU
16-bit timer peripheral interface
8 low
8 high
8-bit
buffer
8
8
8
Low
8
Low
8
high
8
8
8
high
Low
high
high Low
EXEDG
16
1/2
1/4
1/8
Input
capture
register 1
Input
capture
register 2
Output
compare
register 1
Output
compare
register 2
Counter
register
EXTCLK
pin
Alternate
counter
register
16
16
16
CC[1:0]
Timer internal bus
16 16
Overflow
detect
circuit
ICAP1
pin
Edge detect circuit 1
Edge detect circuit 2
Output compare circuit
6
ICAP2
pin
OCMP1
pin
LATCH1
LATCH2
0
ICF1 OCF1 TOF ICF2 OCF2
0
TIMD
OCMP2
pin
CSR (control/status register)
EXEDG
OPM PWM CC1 CC0 IEDG2
OC2E
ICIE OCIE TOIE FOLV2 FOLV1OLVL2 IEDG1 OLVL1
CR1 (control register 1)
OC1E
CR 2 (control register 2)
(1)
Timer interrupt
1. If IC, OC and TO interrupt requests have separate vectors then the last OR is not present (see Table 17:
ST7FOXF1/ST7FOXK1 Interrupt mapping)
119/226
On-chip peripherals
ST7FOXF1, ST7FOXK1, ST7FOXK2
16-bit read sequence (from either the counter register or the alternate counter register)
Figure 56. 16-bit read sequence
Beginning of the sequence
Read MSB
At t0
LSB is buffered
Other
instructions
Returns the buffered
LSB value at t0
Read LSB
At t0 +∆t
Sequence completed
The user must read the MSB first, then the LSB value is buffered automatically.
This buffered value remains unchanged until the 16-bit read sequence is completed, even if
the user reads the MSB several times.
After a complete reading sequence, if only the CLR register or ACLR register are read, they
return the LSB of the count value at the time of the read.
Whatever the timer mode used (input capture, output compare, one pulse mode or PWM
mode) an overflow occurs when the counter rolls over from FFFFh to 0000h then:
■
■
The TOF bit of the SR register is set.
A timer interrupt is generated if:
–
–
TOIE bit of the CR1 register is set and
I bit of the CC register is cleared.
If one of these conditions is false, the interrupt remains pending to be issued as soon as
they are both true.
Clearing the overflow interrupt request is done in two steps:
1. Reading the SR register while the TOF bit is set.
2. An access (read or write) to the CLR register.
Note:
The TOF bit is not cleared by accesses to ACLR register. The advantage of accessing the
ACLR register rather than the CLR register is that it allows simultaneous use of the overflow
function and reading the free running counter at random times (for example, to measure
elapsed time) without the risk of clearing the TOF bit erroneously.
The timer is not affected by Wait mode.
In Halt mode, the counter stops counting until the mode is exited. Counting then resumes
from the previous count (device awakened by an interrupt) or from the reset count (device
awakened by a reset).
External clock
The external clock (where available) is selected if CC0 = 1 and CC1 = 1 in CR2 register.
The status of the EXEDG bit in the CR2 register determines the type of level transition on
the external clock pin EXTCLK that triggers the free running counter.
The counter is synchronized with the falling edge of the internal CPU clock.
120/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
On-chip peripherals
A minimum of four falling edges of the CPU clock must occur between two consecutive
active edges of the external clock; thus the external clock frequency must be less than a
quarter of the CPU clock frequency.
Figure 57. Counter timing diagram, internal clock divided by 2
CPU clock
Internal reset
Timer clock
FFFD
FFFF 0000 0001 0002
0003
FFFE
Counter register
Timer overflow flag (TOF)
Figure 58. Counter timing diagram, internal clock divided by 4
CPU clock
Internal reset
Timer clock
FFFC
FFFD
0000
0001
Counter register
Timer overflow flag (TOF)
Figure 59. Counter timing diagram, internal clock divided by 8
CPU clock
Internal reset
Timer clock
FFFC
FFFD
0000
Counter register
Timer overflow flag (TOF)
Note:
The device is in reset state when the internal reset signal is high, when it is low the device is
running.
121/226
On-chip peripherals
ST7FOXF1, ST7FOXK1, ST7FOXK2
Input capture
In this section, the index, i, may be 1 or 2 because there are two input capture functions in
the 16-bit timer.
The two input capture 16-bit registers (IC1R and IC2R) are used to latch the value of the
free-running counter after a transition detected by the ICAPi pin (see below).
MSB
LSB
ICiR
ICiHR
ICiLR
ICiR register is a read-only register.
The active transition is software programmable through the IEDGi bit of control registers
(CRi).
Timing resolution is one count of the free running counter: (fCPU/CC[1:0]).
Procedure
To use the input capture function, select the following in the CR2 register:
■
■
Select the timer clock (CC[1:0]).
Select the edge of the active transition on the ICAP2 pin with the IEDG2 bit (the ICAP2
pin must be configured as floating input).
Select the following in the CR1 register:
■
Set the ICIE bit to generate an interrupt after an input capture coming from either the
ICAP1 pin or the ICAP2 pin
■
Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the
ICAP1pin must be configured as floating input).
When an input capture occurs:
■
■
The ICFi bit is set
The ICiR register contains the value of the free running counter on the active transition
on the ICAPi pin (see Figure 61).
■
A timer interrupt is generated if the ICIE bit is set and the I bit is cleared in the CC
register. Otherwise, the interrupt remains pending until both conditions become true.
Clearing the input capture interrupt request (that is, clearing the ICFi bit) is done in two
steps:
1. By reading the SR register while the ICFi bit is set.
2. By accessing (reading or writing) the ICiLR register.
Note:
1
2
3
After reading the ICiHR register, transfer of input capture data is inhibited and ICFi is never
set until the ICiLR register is also read.
The ICiR register contains the free running counter value which corresponds to the most
recent input capture.
The two input capture functions can be used together even if the timer also uses the two
output compare functions.
4
5
In One Pulse mode and PWM mode only the input capture 2 can be used.
The alternate inputs (ICAP1 and ICAP2) are always directly connected to the timer. So any
transitions on these pins activate the input capture function. Moreover if one of the ICAPi pin
is configured as an input and the second one as an output, an interrupt can be generated if
122/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
On-chip peripherals
the user toggle the output pin and if the ICIE bit is set. This can be avoided if the input
capture function i is disabled by reading the ICiHR (see note 1).
6
The TOF bit can be used with interrupt in order to measure event that go beyond the timer
range (FFFFh).
Figure 60. Input capture block diagram
ICAP1
pin
CR1 (control register 1)
IEDG1
ICAP2
pin
Edge detect
circuit 2
Edge detect
circuit 1
ICIE
SR (status register)
IC2R register
IC1R register
ICF1
ICF2
0
0
0
CR2 (control register 2)
IEDG2
16-bit
CC0
CC1
16-bit free running counter
Figure 61. Input capture timing diagram
Timer clock
FF01
FF02
FF03
Counter register
ICAPi pin
ICAPi flag
FF03
ICAPi register
1. The active edge is the rising edge.
2. The time between an event on the ICAPi pin and the appearance of the corresponding flag is from 2 to 3 CPU clock cycles.
This depends on the moment when the ICAP event happens relative to the timer clock.
123/226
On-chip peripherals
ST7FOXF1, ST7FOXK1, ST7FOXK2
Output compare
In this section, the index, i, may be 1 or 2 because there are two output compare functions in
the 16-bit timer.
This function can be used to control an output waveform or indicate when a period of time
has elapsed.
When a match is found between the output compare register and the free running counter,
the output compare function:
■
■
■
Assigns pins with a programmable value if the OCIE bit is set
Sets a flag in the status register
Generates an interrupt if enabled
Two 16-bit registers output compare register 1 (OC1R) and output compare register 2
(OC2R) contain the value to be compared to the counter register each timer clock cycle.
MSB
LSB
OCiR
OCiHR
OCiLR
These registers are readable and writable and are not affected by the timer hardware. A
reset event changes the OCiR value to 8000h.
Timing resolution is one count of the free running counter: (fCPU/
).
CC[1:0]
Procedure:
To use the output compare function, select the following in the CR2 register:
■
Set the OCiE bit if an output is needed then the OCMPi pin is dedicated to the output
compare i signal.
■
Select the timer clock (CC[1:0]) (see : Timer A Control register 2 (TACR2) on
page 134).
In the CR1 register select the following:
■
■
Select the OLVLi bit to be applied to the OCMPi pins after the match occurs.
Set the OCIE bit to generate an interrupt if it is needed.
When a match is found between OCRi register and CR register:
■
■
■
Set the OCFi bit.
The OCMPi pin takes OLVLi bit value (OCMPi pin latch is forced low during reset).
A timer interrupt is generated if the OCIE bit is set in the CR2 register and the I bit is
cleared in the CC register (CC).
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ST7FOXF1, ST7FOXK1, ST7FOXK2
On-chip peripherals
The OCiR register value required for a specific timing application can be calculated using
the following formula:
Equation 1
∆t * fCPU
∆ OCiR =
PRESC
Where:
∆t =
output compare period (in seconds)
CPU clock frequency (in hertz)
f
=
CPU
=
timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits, see : Timer A
Control register 2 (TACR2) on page 134)
PRESC
If the timer clock is an external clock, the formula is:
Equation 2
∆ OCiR = ∆t * fEXT
Where:
∆t =
output compare period (in seconds)
f
=
external timer clock frequency (in hertz)
EXT
Clearing the output compare interrupt request (that is, clearing the OCFi bit) is done by:
1. Reading the SR register while the OCFi bit is set.
2. Accessing (reading or writing) the OCiLR register.
The following procedure is recommended to prevent the OCFi bit from being set between
the time it is read and the time it is written to the OCiR register:
■
■
Write to the OCiHR register (further compares are inhibited).
Read the SR register (first step in the clearance of the OCFi bit, which may be already
set).
■
Write to the OCiLR register (enables the output compare function and clears the OCFi
bit).
Note:
1
2
3
After a processor write cycle to the OCiHR register, the output compare function is inhibited
until the OCiLR register is also written.
If the OCiE bit is not set, the OCMPi pin is a general I/O port and the OLVLi bit does not
appear when a match is found but an interrupt could be generated if the OCIE bit is set.
In both internal and external clock modes, OCFi and OCMPi are set while the counter value
equals the OCiR register value (see Figure 63 for an example with f
/2 and Figure 64 for
CPU
an example with f
/4). This behavior is the same in OPM or PWM mode.
CPU
4
5
The output compare functions can be used both for generating external events on the
OCMPi pins even if the input capture mode is also used.
The value in the 16-bit OCiR register and the OLVi bit should be changed after each
successful comparison in order to control an output waveform or establish a new elapsed
timeout.
125/226
On-chip peripherals
ST7FOXF1, ST7FOXK1, ST7FOXK2
Forced compare output capability
When the FOLVi bit is set by software, the OLVLi bit is copied to the OCMPi pin. The OLVi bit has to be
toggled in order to toggle the OCMPi pin when it is enabled (OCiE bit = 1). The OCFi bit is then not set by
hardware, and thus no interrupt request is generated.
FOLVLi bits have no effect in both one pulse mode and PWM mode.
Figure 62. Output compare block diagram
16-bit free running counter
16-bit
OC1E
CC1 CC0
CR2 (control register 2)
OC2E
CR1 (control register 1)
FOLV1OLVL2
OLVL1
Output compare circuit
OCMP1
pin
FOLV2
OCIE
Latch
1
16-bit
OC1R register
16-bit
OCMP2
pin
Latch
2
OCF1
OCF2
0
0
0
OC2R register
SR (status register)
Figure 63. Output compare timing diagram, f
= f
/2
TIMER
CPU
Internal CPU clock
Timer clock
2ECF
2ED0
2ED1 2ED2
2ED3
2ED4
2ED3
Counter register
Output compare register i (OCRi)
Output compare flag i (OCFi)
OCMPi pin (OLVLi = 1)
126/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
On-chip peripherals
Figure 64. Output compare timing diagram, f
= f
/4
CPU
TIMER
Internal CPU clock
Timer clock
2ECF 2ED0 2ED1
2ED2
2ED4
2ED3
Counter register
2ED3
Output compare register i (OCRi)
Output compare flag i (OCFi)
OCMPi pin (OLVLi = 1)
One pulse mode
One pulse mode enables the generation of a pulse when an external event occurs. This
mode is selected via the OPM bit in the CR2 register.
The one pulse mode uses the input capture1 function and the output compare1 function.
Procedure
1. Load the OC1R register with the value corresponding to the length of the pulse (see
Equation 3 below).
2. Select the following in the CR1 register:
–
–
–
Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after the
pulse.
Using the OLVL2 bit, select the level to be applied to the OCMP1 pin during the
pulse.
Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the
ICAP1 pin must be configured as floating input).
3. Select the following in the CR2 register:
–
Set the OC1E bit, the OCMP1 pin is then dedicated to the output compare 1
function.
–
–
Set the OPM bit.
Select the timer clock CC[1:0] (see : Timer A Control register 2 (TACR2) on
page 134).
127/226
On-chip peripherals
ST7FOXF1, ST7FOXK1, ST7FOXK2
Figure 65. One pulse mode sequence
One pulse mode cycle
ICR1 = counter
OCMP1 = OLVL2
When event
occurs on
ICAP1
to FFFCh
Counter is reset
ICF1 bit is set
When
counter
= OC1R
OCMP1 = OLVL1
When a valid event occurs on the ICAP1 pin, the counter value is loaded in the ICR1
register. The counter is then initialized to FFFCh, the OLVL2 bit is output on the OCMP1 pin
and the ICF1 bit is set.
Because the ICF1 bit is set when an active edge occurs, an interrupt can be generated if the
ICIE bit is set.
Clearing the input capture interrupt request (that is, clearing the ICFi bit) is done in two
steps:
1. Reading the SR register while the ICFi bit is set.
2. Accessing (reading or writing) the ICiLR register.
The OC1R register value required for a specific timing application can be calculated using
the following formula:
Equation 3
t * fCPU
- 5
OCiR value =
PRESC
Where:
t =
pulse period (in seconds)
CPU clock frequency (in hertz)
f
=
CPU
=
timer prescaler factor (2, 4 or 8 depending on the CC[1:0] bits, see : Timer A
Control register 2 (TACR2) on page 134)
PRESC
If the timer clock is an external clock the formula is:
Equation 4
OCiR = t * fEXT -5
Where:
t =
pulse period (in seconds)
f
=
external timer clock frequency (in hertz)
EXT
When the value of the counter is equal to the value of the contents of the OC1R register, the
OLVL1 bit is output on the OCMP1 pin, (see Figure 66).
128/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
On-chip peripherals
Note:
1
2
The OCF1 bit cannot be set by hardware in one pulse mode but the OCF2 bit can generate
an output compare interrupt.
When the pulse width modulation (PWM) and one pulse mode (OPM) bits are both set, the
PWM mode is the only active one.
3
4
If OLVL1 = OLVL2 a continuous signal is seen on the OCMP1 pin.
The ICAP1 pin can not be used to perform input capture. The ICAP2 pin can be used to
perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take
care that the counter is reset each time a valid edge occurs on the ICAP1 pin and ICF1 can
also generates interrupt if ICIE is set.
5
When one pulse mode is used OC1R is dedicated to this mode. Nevertheless OC2R and
OCF2 can be used to indicate a period of time has been elapsed but cannot generate an
output waveform because the level OLVL2 is dedicated to the one pulse mode.
Figure 66. One pulse mode timing example
01F8
IC1R
2ED3
2ED0 2ED1 2ED2
2ED3
FFFC FFFD
Counter 01F8
FFFC FFFD FFFE
ICAP1
OLVL2
OLVL2
OLVL1
Compare1
OCMP1
1. IEDG1 = 1, OC1R = 2ED0h, OLVL1 = 0, OLVL2 = 1
Figure 67. Pulse width modulation mode timing example
2ED2
34E2
FFFC
2ED0
2ED1
Counter
OCMP1
FFFE
34E2
FFFC FFFD
OLVL2
OLVL2
OLVL1
Compare1
Compare2
Compare2
1. OC1R = 2ED0h, OC2R = 34E2, OLVL1 = 0, OLVL2 = 1
Pulse width modulation mode
Pulse width modulation (PWM) mode enables the generation of a signal with a frequency
and pulse length determined by the value of the OC1R and OC2R registers.
Pulse width modulation mode uses the complete output compare 1 function plus the OC2R
register, and so this functionality can not be used when PWM mode is activated.
In PWM mode, double buffering is implemented on the output compare registers. Any new
values written in the OC1R and OC2R registers are loaded in their respective shadow
registers (double buffer) only at the end of the PWM period (OC2) to avoid spikes on the
PWM output pin (OCMP1). The shadow registers contain the reference values for
comparison in PWM ‘double buffering’ mode.
129/226
On-chip peripherals
ST7FOXF1, ST7FOXK1, ST7FOXK2
Note:
There is a locking mechanism for transferring the OCiR value to the buffer. After a write to
the OCiHR register, transfer of the new compare value to the buffer is inhibited until OCiLR
is also written.
Unlike in output compare mode, the compare function is always enabled in PWM mode.
Procedure
To use pulse width modulation mode:
1. Load the OC2R register with the value corresponding to the period of the signal using
the formula in the opposite column.
2. Load the OC1R register with the value corresponding to the period of the pulse if
(OLVL1 = 0 and OLVL2 = 1) using Equation 5.
3. Select the following in the CR1 register:
Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after a successful
comparison with OC1R register.
Using the OLVL2 bit, select the level to be applied to the OCMP1 pin after a successful
comparison with OC2R register.
4. Select the following in the CR2 register:
Set OC1E bit: the OCMP1 pin is then dedicated to the output compare 1 function.
Set the PWM bit.
Select the timer clock (CC[1:0]) (see: Timer A Control register 2 (TACR2) on page 134).
Figure 68. Pulse width modulation cycle
Pulse width modulation cycle
When
counter
= OC1R
OCMP1 = OLVL1
OCMP1 = OLVL2
When
counter
= OC2R
Counter is reset
to FFFCh
ICF1 bit is set
If OLVL = 1 and OLVL2 = 0 the length of the positive pulse is the difference between the
OC2R and OC1R registers.
If OLVL1 = OLVL2 a continuous signal is seen on the OCMP1 pin.
130/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
On-chip peripherals
The OCiR register value required for a specific timing application can be calculated using
the following formula:
Equation 5
t * fCPU
- 5
OCiR value =
PRESC
Where:
t =
signal or pulse period (in seconds)
CPU clock frequency (in hertz)
f
=
CPU
=
timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits, see : Timer A Control
register 2 (TACR2) on page 134)
PRESC
If the timer clock is an external clock the formula is:
Equation 6
OCiR = t * fEXT -5
Where:
t =
signal or pulse period (in seconds)
f
=
external timer clock frequency (in hertz)
EXT
The output compare 2 event causes the counter to be initialized to FFFCh (see Figure 67)
Note:
1
2
3
The OCF1 and OCF2 bits cannot be set by hardware in PWM mode therefore the output
compare interrupt is inhibited.
The ICF1 bit is set by hardware when the counter reaches the OC2R value and can produce
a timer interrupt if the ICIE bit is set and the I bit is cleared.
In PWM mode the ICAP1 pin can not be used to perform input capture because it is
disconnected to the timer. The ICAP2 pin can be used to perform input capture (ICF2 can be
set and IC2R can be loaded) but the user must take care that the counter is reset each
period and ICF1 can also generates interrupt if ICIE is set.
4
When the pulse width modulation (PWM) and one pulse mode (OPM) bits are both set, the
PWM mode is the only active one.
10.4.4
Low power modes
Table 42. Effect of low power modes on 16-bit timer
Mode
Description
No effect on 16-bit timer.
Wait
Timer interrupts cause the device to exit from Wait mode.
16-bit timer registers are frozen.
In Halt mode, the counter stops counting until Halt mode is exited. Counting resumes from
the previous count when the device is woken up by an interrupt with ‘exit from Halt mode’
capability or from the counter reset value when the device is woken up by a reset.
Halt
If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is
armed. Consequently, when the device is woken up by an interrupt with ‘exit from Halt
mode’ capability, the ICFi bit is set, and the counter value present when exiting from Halt
mode is captured into the ICiR register.
131/226
On-chip peripherals
ST7FOXF1, ST7FOXK1, ST7FOXK2
10.4.5
Interrupts
(1)
Table 43. 16-bit timer interrupt control/wakeup capability
Event
flag
Enable
control bit
Exitfrom Exitfrom
Interrupt event
WAIT
HALT
Input capture 1 event/counter reset in PWM mode
Input capture 2 event
ICF1
ICF2
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
ICIE
Output compare 1 event (not available in PWM mode) OCF1
Output compare 2 event (not available in PWM mode) OCF2
OCIE
TOIE
Timer overflow event
TOF
1. The 16-bit timer interrupt events are connected to the same interrupt vector (see Section 7: Interrupts).
These events generate an interrupt if the corresponding enable control bit is set and the interrupt mask in
the CC register is reset (RIM instruction).
10.4.6
Summary of 16-bit timer modes
Table 44. Summary of 16-bit timer modes
Available resources
Modes
Input
Input
Output
Output
capture 1
capture 2
compare 1
compare 2
Input capture (1) and/or (2)
Output compare (1) and/or (2)
One pulse mode
Yes
Yes
No
Yes
Yes
Yes
No
Yes
Yes
Yes
Not recommended(1)
Not recommended(3)
Partially(2)
PWM mode
No
No
No
1. See note 4 in One pulse mode on page 127.
2. See note 5 in One pulse mode on page 127.
3. See note 4 in Pulse width modulation mode on page 129.
132/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
On-chip peripherals
10.4.7
16-bit timer registers
Each timer is associated with three control and status registers, and with six pairs of data
registers (16-bit values) relating to the two input captures, the two output compares, the
counter and the alternate counter.
TIMA Control register 1 (TACR1)
Reset value: 0000 0000 (00h)
7
0
ICIE
OCIE
TOIE
FOLV2
FOLV1
OLVL2
IEDG1
OLVL1
Read / Write
Bit 7 = ICIE Input capture interrupt enable
0: Interrupt is inhibited
1: A timer interrupt is generated whenever the ICF1 or ICF2 bit of the SR register is
set
Bit 6 = OCIE Output compare interrupt enable
0: Interrupt is inhibited
1: A timer interrupt is generated whenever the OCF1 or OCF2 bit of the SR register is
set
Bit 5 = TOIE Timer overflow interrupt enable
0: Interrupt is inhibited
1: A timer interrupt is enabled whenever the TOF bit of the SR register is set
Bit 4 = FOLV2 Forced output compare 2
This bit is set and cleared by software.
0: No effect on the OCMP2 pin
1: Forces the OLVL2 bit to be copied to the OCMP2 pin, if the OC2E bit is set and
even if there is no successful comparison
Bit 3 = FOLV1 Forced output compare 1
This bit is set and cleared by software.
0: No effect on the OCMP1 pin
1: Forces OLVL1 to be copied to the OCMP1 pin, if the OC1E bit is set and even if
there is no successful comparison
Bit 2 = OLVL2 Output level 2
This bit is copied to the OCMP2 pin whenever a successful comparison occurs with the
OC2R register and OCxE is set in the CR2 register. This value is copied to the OCMP1
pin in one pulse mode and pulse width modulation mode.
133/226
On-chip peripherals
ST7FOXF1, ST7FOXK1, ST7FOXK2
Bit 1 = IEDG1 Input edge 1
This bit determines which type of level transition on the ICAP1 pin triggers the capture.
0: A falling edge triggers the capture
1: A rising edge triggers the capture
Bit 0 = OLVL1 Output level 1
The OLVL1 bit is copied to the OCMP1 pin whenever a successful comparison occurs
with the OC1R register and the OC1E bit is set in the CR2 register.
Timer A Control register 2 (TACR2)
Reset value: 0000 0000 (00h)
7
0
OC1E
OC2E
OPM
PWM
Read / Write
OC1E Output compare 1 pin enable
CC[1:0]
IEDG2
EXEDG
Bit 7 =
This bit is used only to output the signal from the timer on the OCMP1 pin (OLV1 in
output compare mode, both OLV1 and OLV2 in PWM and one-pulse mode). Whatever
the value of the OC1E bit, the output compare 1 function of the timer remains active.
0: OCMP1 pin alternate function disabled (I/O pin free for general-purpose I/O)
1: OCMP1 pin alternate function enabled
Bit 6 = 0C2E Output compare 2 pin enable
This bit is used only to output the signal from the timer on the OCMP2 pin (OLV2 in
output compare mode). Whatever the value of the OC2E bit, the output compare 2
function of the timer remains active.
0: OCMP2 pin alternate function disabled (I/O pin free for general-purpose I/O)
1: OCMP2 pin alternate function enabled
Bit 5 = OPM One pulse mode
0: One pulse mode is not active
1: One pulse mode is active, the ICAP1 pin can be used to trigger one pulse on
the OCMP1 pin; the active transition is given by the IEDG1 bit. The length of
the generated pulse depends on the contents of the OC1R register.
Bit 4 = PWM Pulse width modulation
0: PWM mode is not active
1: PWM mode is active, the OCMP1 pin outputs a programmable cyclic signal;
the length of the pulse depends on the value of OC1R register; the period
depends on the value of OC2R register.
Bits 3:2 CC[1:0] Clock control
The timer clock mode depends on the following bits:
00: Timer clock = f
01: Timer clock = f
/4
/2
CPU
CPU
134/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
On-chip peripherals
10: Timer clock = f
/8
CPU
11: Timer clock = external clock (where available)
Note:
If the external clock pin is not available, programming the external clock configuration stops
the counter.
Bit 1 = IEDG2 Input edge 2
This bit determines which type of level transition on the ICAP2 pin triggers the capture.
0: A falling edge triggers the capture
1: A rising edge triggers the capture
Bit 0 = EXEDG External clock edge
This bit determines which type of level transition on the external clock pin EXTCLK
triggers the counter register.
0: A falling edge triggers the counter register
1: A rising edge triggers the counter register
Timer A Control/status register (TACSR)
Reset value: 0000 0000 (00h)
The 3 least significant bits are not used.
7
0
ICF1
OCF1
TOF
ICF2
OCF2
TIMD
Reserved
Read Only
Bit 7 = ICF1 Input capture flag 1
0: No input capture (reset value)
1: An input capture has occurred on the ICAP1 pin or the counter has reached the
OC2R value in PWM mode. To clear this bit, first read the SR register, then read or
write the low byte of the IC1R (IC1LR) register.
Bit 6 = OCF1 Output compare flag 1
0: No match (reset value)
1: The content of the free running counter has matched the content of the OC1R
register. To clear this bit, first read the SR register, then read or write the low byte of
the OC1R (OC1LR) register.
Bit 5 = TOF Timer overflow flag
0: No timer overflow (reset value)
1: The free running counter rolled over from FFFFh to 0000h. To clear this bit, first
read the SR register, then read or write the low byte of the CR (CLR) register.
Note:
Reading or writing the ACLR register does not clear TOF.
135/226
On-chip peripherals
ST7FOXF1, ST7FOXK1, ST7FOXK2
Bit 4 = ICF2 Input capture flag 2
0: No input capture (reset value)
1: An input capture has occurred on the ICAP2 pin. To clear this bit, first read the SR
register, then read or write the low byte of the IC2R (IC2LR) register.
Bit 3 = OCF2 Output compare flag 2
0: No match (reset value)
1: The content of the free running counter has matched the content of the OC2R
register. To clear this bit, first read the SR register, then read or write the low byte of
the OC2R (OC2LR) register.
Bit 2 = TIMD Timer disable
This bit is set and cleared by software. When set, it freezes the timer prescaler and
counter and disables the output functions (OCMP1 and OCMP2 pins) to reduce power
consumption. Access to the timer registers is still available, allowing the timer
configuration to be changed while it is disabled.
0: Timer enabled
1: Timer prescaler, counter and outputs disabled
Bits 1:0 = Reserved, must be kept cleared
Timer A Input capture 1 high register (TAIC1HR)
Reset value: undefined
This is an 8-bit read-only register that contains the high part of the counter value (transferred
by the input capture 1 event).
7
0
MSB
LSB
Read Only
Timer A Input capture 1 low register (TAIC1LR)
Reset value: undefined
This is an 8-bit read-only register that contains the low part of the counter value (transferred
by the input capture 1 event).
7
0
MSB
LSB
Read Only
136/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
On-chip peripherals
Timer A Output compare 1 high register (TAOC1HR)
Reset value: 1000 0000 (80h)
This is an 8-bit register that contains the high part of the value to be compared to the CHR
register.
7
0
MSB
LSB
Read / Write
Timer A Output compare 1 low register (TAOC1LR)
Reset value: 0000 0000 (00h)
This is an 8-bit register that contains the low part of the value to be compared to the CLR
register.
7
0
MSB
LSB
Read / Write
Output compare 2 high register (OC2HR)
Reset value: 1000 0000 (80h)
This is an 8-bit register that contains the high part of the value to be compared to the CHR
register.
7
0
MSB
LSB
Read / Write
Output compare 2 low register (OC2LR)
Reset value: 0000 0000 (00h)
This is an 8-bit register that contains the low part of the value to be compared to the CLR
register.
7
0
MSB
LSB
Read / Write
137/226
On-chip peripherals
ST7FOXF1, ST7FOXK1, ST7FOXK2
Counter high register (CHR)
Reset value: 1111 1111 (FFh)
This is an 8-bit read-only register that contains the high part of the counter value.
7
0
MSB
LSB
Read Only
Counter low register (CLR)
Reset value: 1111 1100 (FCh)
This is an 8-bit read-only register that contains the low part of the counter value. A write to
this register resets the counter. An access to this register after accessing the CSR register
clears the TOF bit.
7
0
MSB
LSB
Read Only
Alternate counter high register (ACHR)
Reset value: 1111 1111 (FFh)
This is an 8-bit read-only register that contains the high part of the counter value.
7
0
MSB
LSB
Read Only
Alternate counter low register (ACLR)
Reset value: 1111 1100 (FCh)
This is an 8-bit read-only register that contains the low part of the counter value. A write to
this register resets the counter. An access to this register after an access to CSR register
does not clear the TOF bit in the CSR register.
7
0
MSB
LSB
Read Only
138/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
On-chip peripherals
Input capture 2 high register (IC2HR)
Reset value: undefined
This is an 8-bit read-only register that contains the high part of the counter value (transferred
by the input capture 2 event).
7
0
MSB
LSB
Read Only
Input capture 2 low register (IC2LR)
Reset value: undefined
This is an 8-bit read-only register that contains the low part of the counter value (transferred
by the input capture 2 event).
7
0
MSB
LSB
Read Only
10.4.8
16-bit timer register map and reset values
Table 45. 16-bit timer register map and reset values
Address (Hex.) Register label
7
6
5
4
3
2
1
0
TACR2
55
OC1E OC2E OPM PWM
CC1
0
CC0 IEDG2 EXEDG
Reset value
0
0
0
0
0
0
0
TACR1
56
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
Reset value
0
0
0
0
0
0
0
0
TACSR
57
ICF1 OCF1 TOF
ICF2 OCF2 TIMD
-
0
-
0
Reset value
0
0
0
0
0
0
TAICHR1
58
MSB
-
LSB
-
-
-
-
-
-
-
-
-
-
Reset value
TAICLR1
59
MSB
-
LSB
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Reset value
TAOCHR1
5A
MSB
-
LSB
-
Reset value
TAOCLR1
5B
MSB
-
LSB
-
Reset value
TACHR
5C
MSB
1
LSB
1
Reset value
1
1
1
1
1
1
1
1
1
1
1
0
TACLR
5D
MSB
1
LSB
0
Reset value
139/226
On-chip peripherals
ST7FOXF1, ST7FOXK1, ST7FOXK2
Table 45. 16-bit timer register map and reset values (continued)
Address (Hex.) Register label
7
6
5
4
3
2
1
0
TAACHR
Reset value
MSB
1
LSB
1
5E
5F
60
61
62
63
1
1
1
1
1
1
TAACLR
Reset value
MSB
1
LSB
0
1
-
1
-
1
-
1
-
1
-
0
-
TAICHR2
Reset value
MSB
-
LSB
-
TAICLR2
Reset value
MSB
-
LSB
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TAOCHR2
Reset value
MSB
-
LSB
-
TAOCLR2
Reset value
MSB
-
LSB
-
140/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
On-chip peripherals
10.5
I2C bus interface (I2C)
10.5.1
Introduction
2
2
The I C Bus Interface serves as an interface between the microcontroller and the serial I C
2
bus. It provides both multimaster and slave functions, and controls all I C bus-specific
sequencing, protocol, arbitration and timing. It supports fast I C mode (400 kHz).
2
10.5.2
Main features
2
■
■
■
■
■
■
2
Parallel-bus/I C protocol converter
Multi-master capability
7-bit/10-bit Addressing
Transmitter/Receiver flag
End-of-byte transmission flag
Transfer problem detection
I C master features:
■
■
■
■
■
■
■
2
Clock generation
2
I C bus busy flag
Arbitration Lost Flag
End of byte transmission flag
Transmitter/Receiver Flag
Start bit detection flag
Start and Stop generation
I C slave features:
■
■
■
■
■
■
■
Stop bit detection
2
I C bus busy flag
Detection of misplaced start or stop condition
2
Programmable I C Address detection
Transfer problem detection
End-of-byte transmission flag
Transmitter/Receiver flag
10.5.3
General description
In addition to receiving and transmitting data, this interface converts it from serial to parallel
format and vice versa, using either an interrupt or polled handshake. The interrupts are
2
enabled or disabled by software. The interface is connected to the I C bus by a data pin
2
(SDAI) and by a clock pin (SCLI). It can be connected both with a standard I C bus and a
2
Fast I C bus. This selection is made by software.
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On-chip peripherals
ST7FOXF1, ST7FOXK1, ST7FOXK2
Mode selection
The interface can operate in the four following modes:
■
■
Slave transmitter/receiver
Master transmitter/receiver
By default, it operates in slave mode.
The interface automatically switches from slave to master after it generates a START
condition and from master to slave in case of arbitration loss or a STOP generation, allowing
then Multi-Master capability.
Communication flow
In Master mode, it initiates a data transfer and generates the clock signal. A serial data
transfer always begins with a start condition and ends with a stop condition. Both start and
stop conditions are generated in master mode by software.
In Slave mode, the interface is capable of recognizing its own address (7 or 10-bit), and the
General Call address. The General Call address detection may be enabled or disabled by
software.
Data and addresses are transferred as 8-bit bytes, MSB first. The first byte(s) following the
start condition contain the address (one in 7-bit mode, two in 10-bit mode). The address is
always transmitted in Master mode.
A 9th clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver must
send an acknowledge bit to the transmitter. Refer to Figure 69.
2
Figure 69. I C bus protocol
SDA
ACK
9
MSB
1
SCL
2
8
START
STOP
CONDITION
CONDITION
Acknowledge may be enabled and disabled by software.
2
The I C interface address and/or general call address can be selected by software.
2
The speed of the I C interface may be selected between Standard (up to 100 kHz) and Fast
2
I C (up to 400 kHz).
SDA/SCL line control
Transmitter mode: the interface holds the clock line low before transmission to wait for the
microcontroller to write the byte in the Data register.
Receiver mode: the interface holds the clock line low after reception to wait for the
microcontroller to read the byte in the Data register.
The SCL frequency (F ) is controlled by a programmable clock divider which depends on
scl
2
the I C bus mode.
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ST7FOXF1, ST7FOXK1, ST7FOXK2
On-chip peripherals
2
When the I C cell is enabled, the SDA and SCL ports must be configured as floating inputs.
In this case, the value of the external pull-up resistor used depends on the application.
2
When the I C cell is disabled, the SDA and SCL ports revert to being standard I/O port pins.
2
Figure 70. I C interface block diagram
DATA REGISTER (DR)
DATA CONTROL
SDA or SDAI
DATA SHIFT REGISTER
COMPARATOR
OWN ADDRESS REGISTER 1 (OAR1)
OWN ADDRESS REGISTER 2 (OAR2)
CLOCK CONTROL
SCL or SCLI
CLOCK CONTROL REGISTER (CCR)
CONTROL REGISTER (CR)
STATUS REGISTER 1 (SR1)
STATUS REGISTER 2 (SR2)
CONTROL LOGIC
INTERRUPT
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On-chip peripherals
ST7FOXF1, ST7FOXK1, ST7FOXK2
10.5.4
Functional description
Refer to the CR, SR1 and SR2 registers in Section 10.5.7. for the bit definitions.
2
By default the I C interface operates in Slave mode (M/SL bit is cleared) except when it
initiates a transmit or receive sequence.
First the interface frequency must be configured using the FRi bits in the OAR2 register.
Slave mode
As soon as a start condition is detected, the address is received from the SDA line and sent
to the shift register; then it is compared with the address of the interface or the General Call
address (if selected by software).
Note:
In 10-bit addressing mode, the comparison includes the header sequence (11110xx0) and
the two most significant bits of the address.
■
Header matched (10-bit mode only): the interface generates an acknowledge pulse if
the ACK bit is set.
■
■
Address not matched: the interface ignores it and waits for another Start condition.
Address matched: the interface generates in sequence:
–
–
Acknowledge pulse if the ACK bit is set.
EVF and ADSL bits are set with an interrupt if the ITE bit is set.
Then the interface waits for a read of the SR1 register, holding the SCL line low (see
Figure 71 Transfer sequencing EV1).
Next, in 7-bit mode read the DR register to determine from the least significant bit (Data
Direction Bit) if the slave must enter Receiver or Transmitter mode.
In 10-bit mode, after receiving the address sequence the slave is always in receive mode. It
will enter transmit mode on receiving a repeated Start condition followed by the header
sequence with matching address bits and the least significant bit set (11110xx1).
Slave receiver
Following the address reception and after SR1 register has been read, the slave receives
bytes from the SDA line into the DR register via the internal shift register. After each byte
the interface generates in sequence:
■
■
Acknowledge pulse if the ACK bit is set
EVF and BTF bits are set with an interrupt if the ITE bit is set.
Then the interface waits for a read of the SR1 register followed by a read of the DR register,
holding the SCL line low (see Figure 71 Transfer sequencing EV2).
Slave transmitter
Following the address reception and after SR1 register has been read, the slave sends
bytes from the DR register to the SDA line via the internal shift register.
The slave waits for a read of the SR1 register followed by a write in the DR register, holding
the SCL line low (see Figure 71 Transfer sequencing EV3).
When the acknowledge pulse is received the EVF and BTF bits are set by hardware with an
interrupt if the ITE bit is set.
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ST7FOXF1, ST7FOXK1, ST7FOXK2
On-chip peripherals
Closing slave communication
After the last data byte is transferred a Stop Condition is generated by the master. The
interface detects this condition and sets:
EVF and STOPF bits with an interrupt if the ITE bit is set.
Then the interface waits for a read of the SR2 register (see Figure 71 Transfer sequencing
EV4).
Error cases
■
BERR: Detection of a Stop or a Start condition during a byte transfer. In this case, the
EVF and the BERR bits are set with an interrupt if the ITE bit is set.
If it is a Stop then the interface discards the data, released the lines and waits for
another Start condition.
If it is a Start then the interface discards the data and waits for the next slave address
on the bus.
■
AF: Detection of a non-acknowledge bit. In this case, the EVF and AF bits are set with
an interrupt if the ITE bit is set.
The AF bit is cleared by reading the I2CSR2 register. However, if read before the
completion of the transmission, the AF flag will be set again, thus possibly generating a
new interrupt. Software must ensure either that the SCL line is back at 0 before reading
the SR2 register, or be able to correctly handle a second interrupt during the 9th pulse
of a transmitted byte.
Note:
In both cases, SCL line is not held low; however, the SDA line can remain low if the last bits
transmitted are all 0. It is then necessary to release both lines by software. The SCL line is
not held low while AF=1 but by other flags (SB or BTF) that are set at the same time.
How to release the SDA / SCL lines
Set and subsequently clear the STOP bit while BTF is set. The SDA/SCL lines are released
after the transfer of the current byte.
SMBus compatibility
2
ST7 I C is compatible with SMBus V1.1 protocol. It supports all SMBus addressing modes,
SMBus bus protocols and CRC-8 packet error checking. Refer to AN1713: SMBus Slave
2
Driver For ST7 I C Peripheral.
145/226
On-chip peripherals
ST7FOXF1, ST7FOXK1, ST7FOXK2
Master mode
To switch from default Slave mode to Master mode a Start condition generation is needed.
Start condition
Setting the START bit while the BUSY bit is cleared causes the interface to switch to Master
mode (M/SL bit set) and generates a Start condition.
Once the Start condition is sent, the EVF and SB bits are set by hardware with an interrupt if
the ITE bit is set.
The master then waits for a read of the SR1 register followed by a write in the DR register
with the Slave address, holding the SCL line low (see Figure 71 Transfer sequencing
EV5).
Slave address transmission
1. The slave address is then sent to the SDA line via the internal shift register.
–
–
In 7-bit addressing mode, one address byte is sent.
In 10-bit addressing mode, sending the first byte including the header sequence
causes the following event. The EVF bit is set by hardware with interrupt
generation if the ITE bit is set.
2. The master then waits for a read of the SR1 register followed by a write in the DR
register, holding the SCL line low (see Figure 71 Transfer sequencing EV9).
3. Then the second address byte is sent by the interface.
4. After completion of this transfer (and acknowledge from the slave if the ACK bit is set),
the EVF bit is set by hardware with interrupt generation if the ITE bit is set.
5. The master waits for a read of the SR1 register followed by a write in the CR register
(for example set PE bit), holding the SCL line low (see Figure 71 Transfer sequencing
EV6).
6. Next the master must enter Receiver or Transmitter mode.
Note:
In 10-bit addressing mode, to switch the master to Receiver mode, software must generate
a repeated Start condition and resend the header sequence with the least significant bit set
(11110xx1).
Master receiver
Following the address transmission and after SR1 and CR registers have been accessed,
the master receives bytes from the SDA line into the DR register via the internal shift
register. After each byte the interface generates in sequence:
■
■
Acknowledge pulse if the ACK bit is set
EVF and BTF bits are set by hardware with an interrupt if the ITE bit is set.
Then the interface waits for a read of the SR1 register followed by a read of the DR register,
holding the SCL line low (see Figure 71 Transfer sequencing EV7).
To close the communication: before reading the last byte from the DR register, set the STOP
bit to generate the Stop condition. The interface goes automatically back to slave mode
(M/SL bit cleared).
Note:
In order to generate the non-acknowledge pulse after the last received data byte, the ACK
bit must be cleared just before reading the second last data byte.
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ST7FOXF1, ST7FOXK1, ST7FOXK2
Master transmitter
On-chip peripherals
Following the address transmission and after SR1 register has been read, the master
sends bytes from the DR register to the SDA line via the internal shift register.
The master waits for a read of the SR1 register followed by a write in the DR register,
holding the SCL line low (see Figure 71 Transfer sequencing EV8).
When the acknowledge bit is received, the interface sets EVF and BTF bits with an interrupt
if the ITE bit is set.
To close the communication: after writing the last byte to the DR register, set the STOP bit to
generate the Stop condition. The interface goes automatically back to slave mode (M/SL bit
cleared).
Error cases
■
BERR: Detection of a Stop or a Start condition during a byte transfer. In this case, the
EVF and BERR bits are set by hardware with an interrupt if ITE is set.
Note that BERR will not be set if an error is detected during the first pulse of each 9-bit
transaction:
Single Master mode
If a Start or Stop is issued during the first pulse of a 9-bit transaction, the BERR flag will
not be set and transfer will continue however the BUSY flag will be reset. To work
around this, slave devices should issue a NACK when they receive a misplaced Start or
Stop. The reception of a NACK or BUSY by the master in the middle of communication
gives the possibility to reinitiate transmission.
Multimaster mode
Normally the BERR bit would be set whenever unauthorized transmission takes place
while transfer is already in progress. However, an issue will arise if an external master
2
generates an unauthorized Start or Stop while the I C master is on the first pulse of a
2
9-bit transaction. It is possible to work around this by polling the BUSY bit during I C
master mode transmission. The resetting of the BUSY bit can then be handled in a
similar manner as the BERR flag being set.
■
AF: Detection of a non-acknowledge bit. In this case, the EVF and AF bits are set by
hardware with an interrupt if the ITE bit is set. To resume, set the Start or Stop bit.
The AF bit is cleared by reading the I2CSR2 register. However, if read before the
completion of the transmission, the AF flag will be set again, thus possibly generating a
new interrupt. Software must ensure either that the SCL line is back at 0 before reading
the SR2 register, or be able to correctly handle a second interrupt during the 9th pulse
of a transmitted byte.
■
ARLO: Detection of an arbitration lost condition.
In this case the ARLO bit is set by hardware (with an interrupt if the ITE bit is set and
the interface goes automatically back to slave mode (the M/SL bit is cleared).
Note:
In all these cases, the SCL line is not held low; however, the SDA line can remain low if the
last bits transmitted are all 0. It is then necessary to release both lines by software. The SCL
line is not held low while AF=1 but by other flags (SB or BTF) that are set at the same time.
147/226
On-chip peripherals
ST7FOXF1, ST7FOXK1, ST7FOXK2
Figure 71. Transfer sequencing
7-bit slave receiver
S Address
A
Data1
A
Data2
A
DataN
A
P
.....
EV1
7-bit slave transmitter
S Address
EV2
EV2
EV2
EV4
Data
N
A
Data1 A
Data2
A
NA
P
....
.
EV3-
1
EV1 EV3
EV3
EV3
EV4
P
7-bit master receiver
Address
S
A
Data1
A
Data2
A
DataN NA
....
.
EV5
7-bit master transmitter
Address
EV6
EV7
A
EV7
A
EV7
Data
S
A
Data1
Data2
A
P
....
.
N
EV5
EV6 EV8
EV8
A
EV8
EV8
P
10-bit slave receiver
Header Address
S
A
A
Data1
DataN
A
.....
EV1
A
EV2
A
EV2
EV4
10-bit slave transmitter
Data
N
Sr Header
Data1
A
P
...
EV3-
1
EV1 EV3
EV3
A
EV4
P
10-bit master transmitter
S
Header
A
Address A
Data1
Data1
DataN
DataN
A
....
EV5
EV9
EV6 EV8
EV8
EV8
10-bit master receiver
Sr
Header
A
A
A
P
.....
EV5
EV6
EV7
EV7
1. S=Start, Sr = Repeated Start, P=Stop, A=Acknowledge, NA=Non-acknowledge, EVx=Event (with interrupt
if ITE=1).
2. EV1: EVF=1, ADSL=1, cleared by reading SR1 register.
3. EV2: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register.
4. EV3: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register.
5. EV3-1: EVF=1, AF=1, BTF=1; AF is cleared by reading SR1 register. BTF is cleared by releasing the lines
(STOP=1, STOP=0) or by writing DR register (DR=FFh). If lines are released by STOP=1, STOP=0, the
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ST7FOXF1, ST7FOXK1, ST7FOXK2
On-chip peripherals
subsequent EV4 is not seen.
6. EV4: EVF=1, STOPF=1, cleared by reading SR2 register.
7. EV5: EVF=1, SB=1, cleared by reading SR1 register followed by writing DR register.
8. EV6: EVF=1, cleared by reading SR1 register followed by writing CR register (for example PE=1).
9. EV7: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register.
10. EV8: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register.
11. EV9: EVF=1, ADD10=1, cleared by reading SR1 register followed by writing DR register.
10.5.5
Low power modes
2
Table 46. Effect of low power modes on the I C interface
Mode
Description
No effect on I2C interface.
Wait
I2C interrupts cause the device to exit from Wait mode.
I2C registers are frozen.
In Halt mode, the I2C interface is inactive and does not acknowledge data on the bus. The
I2C interface resumes operation when the MCU is woken up by an interrupt with “exit from
Halt mode” capability.
Halt
10.5.6
Interrupts
Figure 72. Event flags and interrupt generation
ADD10
ITE
BTF
ADSL
SB
INTERRUPT
EVF
AF
STOPF
ARLO
BERR
*
* EVF can also be set by EV6 or an error from the SR2 register.
Table 47. Description of interrupt events
Interrupt Event(1)
Enable
Control
Bit
Exit
from
Wait
Exit
from
Halt
Event
Flag
10-bit Address Sent Event (Master mode)
End of byte Transfer Event
ADD10
BTF
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
No
Address Matched Event (Slave mode)
Start Bit Generation Event (Master mode)
Acknowledge Failure Event
ADSL
SB
ITE
AF
Stop Detection Event (Slave mode)
Arbitration Lost Event (Multimaster configuration)
Bus Error Event
STOPF
ARLO
BERR
1. The I2C interrupt events are connected to the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding Enable Control Bit is set and the I-bit in the CC register is
reset (RIM instruction).
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On-chip peripherals
ST7FOXF1, ST7FOXK1, ST7FOXK2
10.5.7
Register description
I2C Control register (I2CCR)
Reset value: 0000 0000 (00h)
7
0
0
0
PE
ENGC
START
ACK
STOP
ITE
Read / Write
Bits 7:6 = Reserved. Forced to 0 by hardware.
Bit 5 = PE Peripheral Enable bit
This bit is set and cleared by software.
0: Peripheral disabled
1: Master/Slave capability
Note:
When PE=0, all the bits of the CR register and the SR register except the Stop bit are reset.
All outputs are released while PE=0
When PE=1, the corresponding I/O pins are selected by hardware as alternate functions.
2
To enable the I C interface, write the CR register TWICE with PE=1 as the first write only
activates the interface (only PE is set).
Bit 4 = ENGC Enable General Call bit
This bit is set and cleared by software. It is also cleared by hardware when the interface
is disabled (PE=0). The 00h General Call address is acknowledged (01h ignored).
0: General Call disabled
1: General Call enabled
2
2
Note:
In accordance with the I C standard, when GCAL addressing is enabled, an I C slave can
only receive data. It will not transmit data to the master.
Bit 3 = START Generation of a Start condition bit. This bit is set and cleared by software. It
is also cleared by hardware when the interface is disabled (PE=0) or when the Start
condition is sent (with interrupt generation if ITE=1).
■
In master mode:
0: No start generation
1: Repeated start generation
In slave mode:
■
0: No start generation
1: Start generation when the bus is free
Bit 2 = ACK Acknowledge enable bit
This bit is set and cleared by software. It is also cleared by hardware when the interface
is disabled (PE=0).
0: No acknowledge returned
1: Acknowledge returned after an address byte or a data byte is received
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ST7FOXF1, ST7FOXK1, ST7FOXK2
On-chip peripherals
Bit 1 = STOP Generation of a Stop condition bit
This bit is set and cleared by software. It is also cleared by hardware in master mode.
Note: This bit is not cleared when the interface is disabled (PE=0).
■
■
In master mode:
0: No stop generation
1: Stop generation after the current byte transfer or after the current Start condition is
sent. The STOP bit is cleared by hardware when the Stop condition is sent.
In slave mode:
0: No stop generation
1: Release the SCL and SDA lines after the current byte transfer (BTF=1). In this mode
the STOP bit has to be cleared by software.
Bit 0 = ITE Interrupt Enable bit
This bit is set and cleared by software and cleared by hardware when the interface is
disabled (PE=0).
0: Interrupts disabled
1: Interrupts enabled
Refer to Figure 72 for the relationship between the events and the interrupt.
SCL is held low when the ADD10, SB, BTF or ADSL flags or an EV6 event (See
Figure 71) is detected.
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On-chip peripherals
ST7FOXF1, ST7FOXK1, ST7FOXK2
I2C Status register 1 (I2CSR1)
Reset value: 0000 0000 (00h)
7
0
EVF
ADD10
TRA
BUSY
BTF
ADSL
M/SL
SB
Read Only
Bit 7 = EVF Event flag
This bit is set by hardware as soon as an event occurs. It is cleared by software reading
SR2 register in case of error event or as described in Figure 71. It is also cleared by
hardware when the interface is disabled (PE=0).
0: No event
1: One of the following events has occurred:
–
–
–
–
–
–
–
–
–
BTF=1 (byte received or transmitted)
ADSL=1 (Address matched in Slave mode while ACK=1)
SB=1 (Start condition generated in Master mode)
AF=1 (No acknowledge received after byte transmission)
STOPF=1 (Stop condition detected in Slave mode)
ARLO=1 (Arbitration lost in Master mode)
BERR=1 (Bus error, misplaced Start or Stop condition detected)
ADD10=1 (Master has sent header byte)
Address byte successfully transmitted in Master mode.
Bit 6 = ADD10 10-bit addressing in Master mode
This bit is set by hardware when the master has sent the first byte in 10-bit address
mode. It is cleared by software reading SR2 register followed by a write in the DR
register of the second address byte. It is also cleared by hardware when the peripheral
is disabled (PE=0).
0: No ADD10 event occurred.
1: Master has sent first address byte (header)
Bit 5 = TRA Transmitter/Receiver bit
When BTF is set, TRA=1 if a data byte has been transmitted. It is cleared automatically
when BTF is cleared. It is also cleared by hardware after detection of Stop condition
(STOPF=1), loss of bus arbitration (ARLO=1) or when the interface is disabled (PE=0).
0: Data byte received (if BTF=1)
1: Data byte transmitted
Bit 4 = BUSY Bus busy bit
This bit is set by hardware on detection of a Start condition and cleared by hardware on
detection of a Stop condition. It indicates a communication in progress on the bus. The
BUSY flag of the I2CSR1 register is cleared if a Bus Error occurs.
0: No communication on the bus
1: Communication ongoing on the bus
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ST7FOXF1, ST7FOXK1, ST7FOXK2
On-chip peripherals
Bit 3 = BTF Byte Transfer Finished bit
This bit is set by hardware as soon as a byte is correctly received or transmitted with
interrupt generation if ITE=1. It is cleared by software reading SR1 register followed by
a read or write of DR register. It is also cleared by hardware when the interface is
disabled (PE=0).
–
Following a byte transmission, this bit is set after reception of the acknowledge
clock pulse. In case an address byte is sent, this bit is set only after the EV6 event
(See Figure 71). BTF is cleared by reading SR1 register followed by writing the
next byte in DR register.
–
Following a byte reception, this bit is set after transmission of the acknowledge
clock pulse if ACK=1. BTF is cleared by reading SR1 register followed by reading
the byte from DR register.
The SCL line is held low while BTF=1.
0: byte transfer not done
1: byte transfer succeeded
Bit 2 = ADSL Address matched bit (slave mode). This bit is set by hardware as soon as the
received slave address matched with the OAR register content or a general call is
recognized. An interrupt is generated if ITE=1. It is cleared by software reading SR1 register
or by hardware when the interface is disabled (PE=0).
The SCL line is held low while ADSL=1.
0: Address mismatched or not received
1: Received address matched
Bit 1 = M/SL Master/Slave bit
This bit is set by hardware as soon as the interface is in Master mode (writing
START=1). It is cleared by hardware after detecting a Stop condition on the bus or a
loss of arbitration (ARLO=1). It is also cleared when the interface is disabled (PE=0).
0: Slave mode
1: Master mode
Bit 0 = SB Start bit (master mode).
This bit is set by hardware as soon as the Start condition is generated (following a write
START=1). An interrupt is generated if ITE=1. It is cleared by software reading SR1
register followed by writing the address byte in DR register. It is also cleared by
hardware when the interface is disabled (PE=0).
0: No Start condition
1: Start condition generated
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On-chip peripherals
ST7FOXF1, ST7FOXK1, ST7FOXK2
I2C Status register 2 (I2CSR2)
Reset value: 0000 0000 (00h)
7
0
0
0
0
AF
STOPF
ARLO
BERR
GCAL
Read Only
Bits 7:5 = Reserved. Forced to 0 by hardware.
Bit 4 = AF Acknowledge failure bit
This bit is set by hardware when no acknowledge is returned. An interrupt is generated
if ITE=1. It is cleared by software reading SR2 register or by hardware when the
interface is disabled (PE=0).
The SCL line is not held low while AF=1 but by other flags (SB or BTF) that are set at
the same time.
0: No acknowledge failure
1: Acknowledge failure
Bit 3 = STOPF Stop detection bit (slave mode)
This bit is set by hardware when a Stop condition is detected on the bus after an
acknowledge (if ACK=1). An interrupt is generated if ITE=1. It is cleared by software
reading SR2 register or by hardware when the interface is disabled (PE=0).
The SCL line is not held low while STOPF=1.
0: No Stop condition detected
1: Stop condition detected
Bit 2 = ARLO Arbitration lost bit
This bit is set by hardware when the interface loses the arbitration of the bus to another
master. An interrupt is generated if ITE=1. It is cleared by software reading SR2
register or by hardware when the interface is disabled (PE=0).
After an ARLO event the interface switches back automatically to Slave mode
(M/SL=0).
The SCL line is not held low while ARLO=1.
0: No arbitration lost detected
1: Arbitration lost detected
Note:
In a Multimaster environment, when the interface is configured in Master Receive mode it
does not perform arbitration during the reception of the Acknowledge Bit. Mishandling of the
ARLO bit from the I2CSR2 register may occur when a second master simultaneously
2
requests the same data from the same slave and the I C master does not acknowledge the
data. The ARLO bit is then left at 0 instead of being set.
Bit 1 = BERR Bus error bit
This bit is set by hardware when the interface detects a misplaced Start or Stop
condition. An interrupt is generated if ITE=1. It is cleared by software reading SR2
register or by hardware when the interface is disabled (PE=0).
The SCL line is not held low while BERR=1.
0: No misplaced Start or Stop condition
1: Misplaced Start or Stop condition
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ST7FOXF1, ST7FOXK1, ST7FOXK2
On-chip peripherals
Note:
If a Bus Error occurs, a Stop or a repeated Start condition should be generated by the
Master to re-synchronize communication, get the transmission acknowledged and the bus
released for further communication
Bit 0 = GCAL General Call bit (slave mode).
This bit is set by hardware when a general call address is detected on the bus while
ENGC=1. It is cleared by hardware detecting a Stop condition (STOPF=1) or when the
interface is disabled (PE=0).
0: No general call address detected on bus
1: general call address detected on bus
I2C Clock Control register (I2CCCR)
Reset value: 0000 0000 (00h)
7
0
FM/SM
CC6
CC5
CC4
Read / Write
Bit 7 = FM/SM Fast/Standard I C mode bit
CC3
CC2
CC1
CC0
2
This bit is set and cleared by software. It is not cleared when the interface is disabled
(PE=0).
2
0: Standard I C mode
2
1: Fast I C mode
Bits 6:0 = CC[6:0] 7-bit clock divider bits
2
These bits select the speed of the bus (F
) depending on the I C mode. They are not
SCL
cleared when the interface is disabled (PE=0).
Refer to the Electrical Characteristics section for the table of values.
Note:
The programmed F
assumes no load on SCL and SDA lines.
SCL
I2C Data register (I2CDR)
Reset Value: 0000 0000 (00h)
7
0
D7
D6
D5
D4
D3
D2
D1
D0
Read / Write
Bits 7:0 = D[7:0] 8-bit Data register
These bits contain the byte to be received or transmitted on the bus.
–
Transmitter mode: byte transmission start automatically when the software writes
in the DR register.
–
Receiver mode: the first data byte is received automatically in the DR register
using the least significant bit of the address. Then, the following data bytes are
received one by one after reading the DR register.
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On-chip peripherals
ST7FOXF1, ST7FOXK1, ST7FOXK2
I2C Own Address register (I2COAR1)
Reset value: 0000 0000 (00h)
7
0
ADD7
ADD6
ADD5
ADD4
ADD3
ADD2
ADD1
ADD0
Read / Write
■
In 7-bit addressing mode
2
Bits 7:1 = ADD[7:1] Interface address. These bits define the I C bus address of the
interface. They are not cleared when the interface is disabled (PE=0).
Bit 0 = ADD0 Address direction bit.
This bit is don’t care, the interface acknowledges either 0 or 1. It is not cleared when
the interface is disabled (PE=0).
Note:
Address 01h is always ignored.
In 10-bit addressing mode
■
2
Bits 7:0 = ADD[7:0] Interface address. These are the least significant bits of the I C
bus address of the interface. They are not cleared when the interface is disabled
(PE=0).
I2C Own Address register (I2COAR2)
Reset value: 0100 0000 (40h)
7
0
0
FR1
FR0
0
0
0
ADD9
ADD8
Read / Write
Bits 7:6 = FR[1:0] Frequency bits
These bits are set by software only when the interface is disabled (PE=0). To configure
2
the interface to I C specified delays select the value corresponding to the
microcontroller frequency f
.
CPU
2
Table 48. Configuration of I C delay times
fCPU
FR1
FR0
< 6 MHz
0
0
0
1
6 to 8 MHz
Bits 5:3 = Reserved
Bits 2:1 = ADD[9:8] Interface address
2
These are the most significant bits of the I C bus address of the interface (10-bit mode
only). They are not cleared when the interface is disabled (PE=0).
Bit 0 = Reserved.
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On-chip peripherals
2
Table 49. I C register mapping and reset values
Address
(Hex.)
Register
label
7
6
5
4
3
2
1
0
I2CCR
Reset Value
PE
0
ENGC
0
START
0
ACK
0
STOP
0
ITE
0
0064h
0065h
0066h
0067h
0068h
0069h
006Ah
0
0
I2CSR1
Reset Value
EVF ADD10 TRA
BUSY
0
BTF
0
ADSL
0
M/SL
0
SB
0
0
0
0
0
0
I2CSR2
Reset Value
AF
0
STOPF ARLO
BERR
0
GCAL
0
0
0
0
I2CCCR
Reset Value
FM/SM CC6
CC5
0
CC4
0
CC3
0
CC2
0
CC1
0
CC0
0
0
0
I2COAR1
Reset Value
ADD7 ADD6 ADD5
ADD4
0
ADD3
0
ADD2
0
ADD1
0
ADD0
0
0
0
0
0
0
I2COAR2
Reset Value
FR1
0
FR0
1
ADD9
0
ADD8
0
0
0
0
0
0
I2CDR
Reset Value
MSB
0
LSB
0
0
0
0
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ST7FOXF1, ST7FOXK1, ST7FOXK2
10.6
Serial peripheral interface (SPI)
10.6.1
Introduction
The Serial Peripheral Interface (SPI) allows full-duplex, synchronous, serial communication
with external devices. An SPI system may consist of a master and one or more slaves or a
system in which devices may be either masters or slaves.
10.6.2
Main features
■
■
■
■
■
■
■
■
■
Full duplex synchronous transfers (on three lines)
Simplex synchronous transfers (on two lines)
Master or slave operation
6 master mode frequencies (f
/4 max.)
CPU
f
/2 max. slave mode frequency (see note)
CPU
SS Management by software or hardware
Programmable clock polarity and phase
End of transfer interrupt flag
Write collision, Master Mode Fault and Overrun flags
Note:
In slave mode, continuous transmission is not possible at maximum frequency due to the
software overhead for clearing status flags and to initiate the next transmission sequence.
10.6.3
General description
Figure 73 on page 159 shows the serial peripheral interface (SPI) block diagram. There are
three registers:
■
■
■
SPI Control Register (SPICR)
SPI Control/Status Register (SPICSR)
SPI Data Register (SPIDR)
The SPI is connected to external devices through four pins:
■
■
■
■
MISO: Master In / Slave Out data
MOSI: Master Out / Slave In data
SCK: Serial Clock out by SPI masters and input by SPI slaves
SS: Slave select: This input signal acts as a ‘chip select’ to let the SPI master
communicate with slaves individually and to avoid contention on the data lines. Slave
SS inputs can be driven by standard I/O ports on the master Device.
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On-chip peripherals
Figure 73. Serial peripheral interface block diagram
Data/Address Bus
Read
SPIDR
Interrupt
request
Read Buffer
MOSI
7
0
SPICSR
MISO
8-Bit Shift Register
SPIF WCOL OVR MODF
0
SOD SSM SSI
Write
SOD
bit
1
SS
SPI
STATE
0
SCK
CONTROL
7
0
SPICR
MSTR
SPR0
SPIE SPE SPR2
CPOL CPHA SPR1
MASTER
CONTROL
SERIAL CLOCK
GENERATOR
SS
10.6.4
Functional description
A basic example of interconnections between a single master and a single slave is
illustrated in Figure 74.
The MOSI pins are connected together and the MISO pins are connected together. In this
way data is transferred serially between master and slave (most significant bit first).
The communication is always initiated by the master. When the master device transmits
data to a slave device via MOSI pin, the slave device responds by sending data to the
master device via the MISO pin. This implies full duplex communication with both data out
and data in synchronized with the same clock signal (which is provided by the master device
via the SCK pin).
To use a single data line, the MISO and MOSI pins must be connected at each node (in this
case only simplex communication is possible).
Four possible data/clock timing relationships may be chosen (see Figure 77 on page 164)
but master and slave must be programmed with the same timing mode.
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On-chip peripherals
ST7FOXF1, ST7FOXK1, ST7FOXK2
Figure 74. Single master/ single slave application
SLAVE
MASTER
MSBit
LSBit
MSBit
LSBit
MISO
MOSI
MISO
MOSI
8-BIT SHIFT REGISTER
8-BIT SHIFT REGISTER
SPI
CLOCK
GENERATOR
SCK
SS
SCK
SS
+5V
Not used if SS is managed
by software
Slave select management
As an alternative to using the SS pin to control the Slave Select signal, the application can
choose to manage the Slave Select signal by software. This is configured by the SSM bit in
the SPICSR register (see Figure 76).
In software management, the external SS pin is free for other application uses and the
internal SS signal level is driven by writing to the SSI bit in the SPICSR register.
In Master mode:
■
SS internal must be held high continuously
In Slave mode:
There are two cases depending on the data/clock timing relationship (see Figure 75):
If CPHA = 1 (data latched on second clock edge):
■
SS internal must be held low during the entire transmission. This implies that in single
slave applications the SS pin either can be tied to V , or made free for standard I/O by
SS
managing the SS function by software (SSM = 1 and SSI = 0 in the SPICSR register)
If CPHA = 0 (data latched on first clock edge):
■
SS internal must be held low during byte transmission and pulled high between each
byte to allow the slave to write to the shift register. If SS is not pulled high, a Write
Collision error will occur when the slave writes to the shift register (see Section : Write
collision error (WCOL)).
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On-chip peripherals
Figure 75. Generic SS timing diagram
Byte 3
Byte 1
Byte 2
MOSI/MISO
Master SS
Slave SS
(if CPHA = 0)
Slave SS
(if CPHA = 1)
Figure 76. Hardware/software slave select management
SSM bit
SSI bit
1
0
SS internal
SS external pin
Master mode operation
In master mode, the serial clock is output on the SCK pin. The clock frequency, polarity and
phase are configured by software (refer to the description of the SPICSR register).
Note:
The idle state of SCK must correspond to the polarity selected in the SPICSR register (by
pulling up SCK if CPOL = 1 or pulling down SCK if CPOL = 0).
How to operate the SPI in master mode
To operate the SPI in master mode, perform the following steps in order:
1. Write to the SPICR register:
–
–
Select the clock frequency by configuring the SPR[2:0] bits.
Select the clock polarity and clock phase by configuring the CPOL and CPHA bits.
Figure 77 shows the four possible configurations.
Note:
The slave must have the same CPOL and CPHA settings as the master.
2. Write to the SPICSR register:
–
Either set the SSM bit and set the SSI bit or clear the SSM bit and tie the SS pin
high for the complete byte transmit sequence.
3. Write to the SPICR register:
Set the MSTR and SPE bits
–
Note:
MSTR and SPE bits remain set only if SS is high).
Caution:
if the SPICSR register is not written first, the SPICR register setting (MSTR bit) may be not
taken into account.
The transmit sequence begins when software writes a byte in the SPIDR register.
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On-chip peripherals
ST7FOXF1, ST7FOXK1, ST7FOXK2
Master mode transmit sequence
When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift
register and then shifted out serially to the MOSI pin most significant bit first.
When data transfer is complete:
■
■
The SPIF bit is set by hardware.
An interrupt request is generated if the SPIE bit is set and the interrupt mask in the
CCR register is cleared.
Clearing the SPIF bit is performed by the following software sequence:
1. An access to the SPICSR register while the SPIF bit is set
2. A read to the SPIDR register
Note:
While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR
register is read.
Slave mode operation
In slave mode, the serial clock is received on the SCK pin from the master device.
To operate the SPI in slave mode:
1. Write to the SPICSR register to perform the following actions:
–
Select the clock polarity and clock phase by configuring the CPOL and CPHA bits
(see Figure 77).
Note:
The slave must have the same CPOL and CPHA settings as the master.
–
Manage the SS pin as described in Section : Slave select management and
Figure 75. If CPHA = 1 SS must be held low continuously. If CPHA = 0 SS must be
held low during byte transmission and pulled up between each byte to let the slave
write in the shift register.
2. Write to the SPICR register to clear the MSTR bit and set the SPE bit to enable the SPI
I/O functions.
Slave mode transmit sequence
When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift
register and then shifted out serially to the MISO pin most significant bit first.
The transmit sequence begins when the slave device receives the clock signal and the most
significant bit of the data on its MOSI pin.
When data transfer is complete:
■
■
The SPIF bit is set by hardware.
An interrupt request is generated if SPIE bit is set and interrupt mask in the CCR
register is cleared.
Clearing the SPIF bit is performed by the following software sequence:
1. An access to the SPICSR register while the SPIF bit is set
2. A write or a read to the SPIDR register
Note:
While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR
register is read.
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On-chip peripherals
The SPIF bit can be cleared during a second transmission; however, it must be cleared
before the second SPIF bit in order to prevent an Overrun condition (see Section : Overrun
condition (OVR)).
10.6.5
Clock phase and clock polarity
Four possible timing relationships may be chosen by software, using the CPOL and CPHA
bits (See Figure 77).
Note:
The idle state of SCK must correspond to the polarity selected in the SPICSR register (by
pulling up SCK if CPOL = 1 or pulling down SCK if CPOL = 0).
The combination of the CPOL clock polarity and CPHA (clock phase) bits selects the data
capture clock edge.
Figure 77 shows an SPI transfer with the four combinations of the CPHA and CPOL bits.
The diagram may be interpreted as a master or slave timing diagram where the SCK pin, the
MISO pin and the MOSI pin are directly connected between the master and the slave
device.
Note:
If CPOL is changed at the communication byte boundaries, the SPI must be disabled by
resetting the SPE bit.
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On-chip peripherals
ST7FOXF1, ST7FOXK1, ST7FOXK2
Figure 77. Data clock timing diagram
CPHA = 1
SCK
(CPOL = 1)
SCK
(CPOL = 0)
Bit 4
Bit 4
Bit3
Bit 2
Bit 2
Bit 1
Bit 1
LSBit
LSBit
MSBit
MSBit
Bit 6
Bit 6
Bit 5
Bit 5
MISO
(from master)
Bit3
MOSI
(from slave)
SS
(to slave)
CAPTURE STROBE
CPHA = 0
SCK
(CPOL = 1)
SCK
(CPOL = 0)
Bit 4
Bit 4
Bit3
Bit 2
Bit 2
Bit 1
Bit 1
LSBit
LSBit
MISO
(from master)
MSBit
Bit 6
Bit 6
Bit 5
Bit 5
Bit3
MOSI
(from slave)
MSBit
SS
(to slave)
CAPTURE STROBE
Note: This figure should not be used as a replacement for parametric information.
Refer to the Electrical Characteristics chapter.
10.6.6
Error flags
Master mode fault (MODF)
Master mode fault occurs when the master device’s SS pin is pulled low.
When a Master mode fault occurs:
■
■
The MODF bit is set and an SPI interrupt request is generated if the SPIE bit is set.
The SPE bit is reset. This blocks all output from the device and disables the SPI
peripheral.
■
The MSTR bit is reset, thus forcing the device into slave mode.
Clearing the MODF bit is done through a software sequence:
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On-chip peripherals
1. A read access to the SPICSR register while the MODF bit is set.
2. A write to the SPICR register.
Note:
To avoid any conflicts in an application with multiple slaves, the SS pin must be pulled high
during the MODF bit clearing sequence. The SPE and MSTR bits may be restored to their
original state during or after this clearing sequence.
Hardware does not allow the user to set the SPE and MSTR bits while the MODF bit is set
except in the MODF bit clearing sequence.
In a slave device, the MODF bit can not be set, but in a multimaster configuration the device
can be in slave mode with the MODF bit set.
The MODF bit indicates that there might have been a multimaster conflict and allows
software to handle this using an interrupt routine and either perform a reset or return to an
application default state.
Overrun condition (OVR)
An overrun condition occurs when the master device has sent a data byte and the slave
device has not cleared the SPIF bit issued from the previously transmitted byte.
When an Overrun occurs:
The OVR bit is set and an interrupt request is generated if the SPIE bit is set.
In this case, the receiver buffer contains the byte sent after the SPIF bit was last cleared. A
read to the SPIDR register returns this byte. All other bytes are lost.
The OVR bit is cleared by reading the SPICSR register.
Write collision error (WCOL)
A write collision occurs when the software tries to write to the SPIDR register while a data
transfer is taking place with an external device. When this happens, the transfer continues
uninterrupted and the software write will be unsuccessful.
Write collisions can occur both in master and slave mode. See also Section : Slave select
management.
Note:
A "read collision" will never occur since the received data byte is placed in a buffer in which
access is always synchronous with the CPU operation.
The WCOL bit in the SPICSR register is set if a write collision occurs.
No SPI interrupt is generated when the WCOL bit is set (the WCOL bit is a status flag only).
Clearing the WCOL bit is done through a software sequence (see Figure 78).
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On-chip peripherals
ST7FOXF1, ST7FOXK1, ST7FOXK2
Figure 78. Clearing the WCOL bit (write collision flag) software sequence
Clearing sequence after SPIF = 1 (end of a data byte transfer)
Read SPICSR
1st Step
RESULT
SPIF = 0
WCOL = 0
2nd Step
Read SPIDR
Clearing sequence before SPIF = 1 (during a data byte transfer)
Read SPICSR
1st Step
Note: Writing to the SPIDR register
instead of reading it does not reset
the WCOL bit
RESULT
2nd Step
Read SPIDR
WCOL = 0
Single master and multimaster configurations
There are two types of SPI systems:
■
■
Single Master System
Multimaster System
Single Master System
A typical single master system may be configured using a device as the master and four
devices as slaves (see Figure 79).
The master device selects the individual slave devices by using four pins of a parallel port to
control the four SS pins of the slave devices.
The SS pins are pulled high during reset since the master device ports will be forced to be
inputs at that time, thus disabling the slave devices.
Note:
To prevent a bus conflict on the MISO line, the master allows only one active slave device
during a transmission.
For more security, the slave device may respond to the master with the received data byte.
Then the master will receive the previous byte back from the slave device if all MISO and
MOSI pins are connected and the slave has not written to its SPIDR register.
Other transmission security methods can use ports for handshake lines or data bytes with
command fields.
Multimaster system
A multimaster system may also be configured by the user. Transfer of master control could
be implemented using a handshake method through the I/O ports or by an exchange of
code messages through the serial peripheral interface system.
The multimaster system is principally handled by the MSTR bit in the SPICR register and
the MODF bit in the SPICSR register.
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On-chip peripherals
Figure 79. Single master / multiple slave configuration
SS
SS
SS
SS
SCK
SCK
SCK
Slave
SCK
Slave
Slave
Slave
Device
Device
Device
Device
MOSI MISO
MOSI MISO
MOSI MISO
MOSI MISO
MOSI MISO
SCK
Master
Device
5V
SS
10.6.7
Low power modes
Table 50. Low power mode descriptions
Mode
Description
No effect on SPI.
WAIT
SPI interrupt events cause the device to exit from WAIT mode.
SPI registers are frozen.
In HALT mode, the SPI is inactive. SPI operation resumes when the device is
woken up by an interrupt with “exit from HALT mode” capability. The data
received is subsequently read from the SPIDR register when the software is
running (interrupt vector fetching). If several data are received before the
wakeup event, then an overrun error is generated. This error can be detected
after the fetch of the interrupt routine that woke up the Device.
HALT
10.6.8
Interrupts
Table 51. Interrupt events
Interrupt event
Event
flag
Enable control
bit
Exit from Wait
Exit from Halt
SPI End of Transfer Event
Master Mode Fault Event
Overrun Error
SPIF
MODF
OVR
No
No
SPIE
Yes
Note:
The SPI interrupt events are connected to the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding Enable Control Bit is set and the interrupt
mask in the CC register is reset (RIM instruction).
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On-chip peripherals
ST7FOXF1, ST7FOXK1, ST7FOXK2
10.6.9
Register description
SPI Control register (SPICR)
Reset value: 0000 xxxx (0xh)
7
0
SPIE
SPE
SPR2
MSTR
CPOL
CPHA
SPR1
SPR0
Read / Write
Bit 7 = SPIE Serial Peripheral interrupt enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SPI interrupt is generated whenever an End of Transfer event, Master Mode Fault
or Overrun error occurs (SPIF = 1, MODF = 1 or OVR = 1 in the SPICSR register)
Bit 6 = SPE Serial Peripheral output enable.
This bit is set and cleared by software. It is also cleared by hardware when, in master
mode, SS = 0 (see Section : Master mode fault (MODF)). The SPE bit is cleared by
reset, so the SPI peripheral is not initially connected to the external pins.
0: I/O pins free for general purpose I/O
1: SPI I/O pin alternate functions enabled
Bit 5 = SPR2 Divider enable.
This bit is set and cleared by software and is cleared by reset. It is used with the
SPR[1:0] bits to set the baud rate. Refer to Table 52: SPI Master mode SCK Frequency.
0: Divider by 2 enabled
1: Divider by 2 disabled
This bit has no effect in slave mode.
Bit 4 = MSTR Master mode.
This bit is set and cleared by software. It is also cleared by hardware when, in master
mode, SS = 0 (see Section : Master mode fault (MODF)).
0: Slave mode
1: Master mode. The function of the SCK pin changes from an input to an output and
the functions of the MISO and MOSI pins are reversed.
Bit 3 = CPOL Clock polarity.
This bit is set and cleared by software. This bit determines the idle state of the serial
Clock. The CPOL bit affects both the master and slave modes.
0: SCK pin has a low level idle state
1: SCK pin has a high level idle state
If CPOL is changed at the communication byte boundaries, the SPI must be disabled
by resetting the SPE bit.
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Bit 2 = CPHA Clock phase.
This bit is set and cleared by software.
0: The first clock transition is the first data capture edge.
1: The second clock transition is the first capture edge.
The slave must have the same CPOL and CPHA settings as the master.
Bits 1:0 = SPR[1:0] Serial clock frequency.
These bits are set and cleared by software. Used with the SPR2 bit, they select the
baud rate of the SPI serial clock SCK output by the SPI in master mode.
These 2 bits have no effect in slave mode.
Table 52. SPI master mode SCK frequency
Serial Clock
SPR2
SPR1
SPR0
fCPU/4
1
0
0
1
0
0
0
0
0
1
1
1
0
0
1
0
0
1
f
CPU/8
fCPU/16
CPU/32
f
fCPU/64
fCPU/128
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On-chip peripherals
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SPI control/status register (SPICSR)
Reset Value: 0000 0000 (00h)
7
0
SPIF
WCOL
OVR
MODF
-
SOD
SSM
SSI
Read / Write (some bits Read only)
Bit 7 = SPIF Serial Peripheral Data Transfer Flag (Read only).
This bit is set by hardware when a transfer has been completed. An interrupt is
generated if SPIE = 1 in the SPICR register. It is cleared by a software sequence (an
access to the SPICSR register followed by a write or a read to the SPIDR register).
0: Data transfer is in progress or the flag has been cleared.
1: Data transfer between the device and an external device has been completed.
While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR
register is read.
Bit 6 = WCOL Write Collision status (Read only).
This bit is set by hardware when a write to the SPIDR register is done during a transmit
sequence. It is cleared by a software sequence (see Figure 75).
0: No write collision occurred
1: A write collision has been detected
Bit 5 = OVR SPI Overrun error (Read only).
This bit is set by hardware when the byte currently being received in the shift register is
ready to be transferred into the SPIDR register while SPIF = 1 (See Section Overrun
condition (OVR)). An interrupt is generated if SPIE = 1 in the SPICR register. The OVR
bit is cleared by software reading the SPICSR register.
0: No overrun error
1: Overrun error detected
Bit 4 = MODF Mode Fault flag (Read only).
This bit is set by hardware when the SS pin is pulled low in master mode (see Section
Master mode fault (MODF)). An SPI interrupt can be generated if SPIE = 1 in the
SPICR register. This bit is cleared by a software sequence (An access to the SPICSR
register while MODF = 1 followed by a write to the SPICR register).
0: No master mode fault detected
1: A fault in master mode has been detected
Bit 3 = Reserved, must be kept cleared.
Bit 2 = SOD SPI Output Disable.
This bit is set and cleared by software. When set, it disables the alternate function of
the SPI output (MOSI in master mode / MISO in slave mode)
0: SPI output enabled (if SPE = 1)
1: SPI output disabled
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On-chip peripherals
Bit 1 = SSM SS Management.
This bit is set and cleared by software. When set, it disables the alternate function of
the SPI SS pin and uses the SSI bit value instead. See Section Slave select
management.
0: Hardware management (SS managed by external pin)
1: Software management (internal SS signal controlled by SSI bit. External SS pin free
for general-purpose I/O)
Bit 0 = SSI SS Internal Mode.
This bit is set and cleared by software. It acts as a ‘chip select’ by controlling the level of
the SS slave select signal when the SSM bit is set.
0: Slave selected
1: Slave deselected
SPI data I/O register (SPIDR)
Reset Value: Undefined
7
0
D7
D6
D5
D4
D3
D2
D1
D0
Read / Write
The SPIDR register is used to transmit and receive data on the serial bus. In a master
device, a write to this register will initiate transmission/reception of another byte.
Note:
During the last clock cycle the SPIF bit is set, a copy of the received data byte in the shift
register is moved to a buffer. When the user reads the serial peripheral data I/O register, the
buffer is actually being read.
While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR
register is read.
Warning: A write to the SPIDR register places data directly into the
shift register for transmission.
A read to the SPIDR register returns the value located in the buffer and not the content
of the shift register (see Figure 73).
171/226
On-chip peripherals
ST7FOXF1, ST7FOXK1, ST7FOXK2
Table 53. SPI register map and reset values
Address
Register label
7
6
5
4
3
2
1
0
(Hex.)
SPIDR
Reset Value
MSB
x
LSB
x
70
x
x
x
x
x
x
SPICR
Reset Value
SPIE
0
SPE
0
SPR2
0
MSTR
0
CPOL
x
CPHA
x
SPR1
x
SPR0
x
71
72
SPICSR
Reset Value
SPIF
0
WCOL
0
OVR
0
MODF
0
SOD
0
SSM
0
SSI
0
0
172/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
On-chip peripherals
10.7
10-bit A/D converter (ADC)
10.7.1
Introduction
The on-chip Analog to Digital Converter (ADC) peripheral is a 10-bit, successive
approximation converter with internal sample and hold circuitry. This peripheral has up to 10
multiplexed analog input channels (refer to device pin out description) that allow the
peripheral to convert the analog voltage levels from up to 10 different sources.
The result of the conversion is stored in a 10-bit Data register. The A/D converter is
controlled through a Control/Status register.
10.7.2
Main features
■
■
■
■
■
■
10-bit conversion
Up to 10 channels with multiplexed input
Linear successive approximation
Data register (DR) which contains the results
Conversion complete status flag
On/off bit (to reduce consumption)
The block diagram is shown in Figure 80.
10.7.3
Functional description
Analog power supply
V
and V
are the high and low level reference voltage pins. In some devices (refer to
SSA
DDA
device pin out description) they are internally connected to the V and V pins.
DD
SS
Conversion accuracy may therefore be impacted by voltage drops and noise in the event of
heavily loaded or badly decoupled power supply lines.
173/226
On-chip peripherals
ST7FOXF1, ST7FOXK1, ST7FOXK2
Figure 80. ADC block diagram
DIV 4
1
0
f
f
ADC
CPU
DIV 2
0
1
SLOW
bit
EOC SPEEDADON
0
CH3 CH2 CH1 CH0
ADCCSR
4
AIN0
AIN1
HOLD CONTROL
R
ADC
ANALOG TO DIGITAL
CONVERTER
ANALOG
MUX
AINx
C
ADC
ADCDRH
D9 D8
D7 D6 D5 D4 D3 D2
ADCDRL
0
0
0
0
0
SLOW
D1
D0
Digital A/D conversion result
The conversion is monotonic, meaning that the result never decreases if the analog input
does not and never increases if the analog input does not.
If the input voltage (V ) is greater than V
(high-level voltage reference) then the
AIN
DDA
conversion result is FFh in the ADCDRH register and 03h in the ADCDRL register (without
overflow indication).
If the input voltage (V ) is lower than V
(low-level voltage reference) then the
SSA
AIN
conversion result in the ADCDRH and ADCDRL registers is 00 00h.
The A/D converter is linear and the digital result of the conversion is stored in the ADCDRH
and ADCDRL registers. The accuracy of the conversion is described in the Electrical
Characteristics Section.
R
is the maximum recommended impedance for an analog input signal. If the impedance
AIN
is too high, this will result in a loss of accuracy due to leakage and sampling not being
completed in the alloted time.
174/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
On-chip peripherals
Configuring the A/D conversion
The analog input ports must be configured as input, no pull-up, no interrupt (see Section 9:
I/O ports). Using these pins as analog inputs does not affect the ability of the port to be read
as a logic input.
To assign the analog channel to convert, select the CH[2:0] bits in the ADCCSR register.
Set the ADON bit to enable the A/D converter and to start the conversion. From this time on,
the ADC performs a continuous conversion of the selected channel.
When a conversion is complete:
■
■
The EOC bit is set by hardware.
The result is in the ADCDR registers.
A read to the ADCDRH or a write to any bit of the ADCCSR register resets the EOC bit.
To read the 10 bits, perform the following steps:
1. Poll the EOC bit
2. Read ADCDRL
3. Read ADCDRH. This clears EOC automatically.
To read only 8 bits, perform the following steps:
1. Poll EOC bit
2. Read ADCDRH. This clears EOC automatically.
Changing the conversion channel
The application can change channels during conversion. When software modifies the
CH[3:0] bits in the ADCCSR register, the current conversion is stopped, the EOC bit is
cleared, and the A/D converter starts converting the newly selected channel.
10.7.4
Low power modes
The A/D converter may be disabled by resetting the ADON bit. This feature allows reduced
power consumption when no conversion is needed and between single shot conversions.
Table 54. Effect of low power modes on the A/D converter
Mode
Description
Wait
No effect on A/D Converter
A/D Converter disabled.
After wakeup from Halt mode, the A/D Converter requires a stabilization time
tSTAB (see Electrical Characteristics) before accurate conversions can be
performed.
Halt
10.7.5
Interrupts
None.
175/226
On-chip peripherals
ST7FOXF1, ST7FOXK1, ST7FOXK2
10.7.6
Register description
Control/status register (ADCCSR)
Reset value: 0000 0000 (00h)
7
0
EOC
SPEED
ADON
0
CH3
CH2
CH1
CH0
Read only
Read/write
Bit 7 = EOC End of Conversion bit
This bit is set by hardware. It is cleared by hardware when software reads the ADCDRH
register or writes to any bit of the ADCCSR register.
0: Conversion is not complete
1: Conversion complete
Bit 6 = SPEED ADC clock selection bit
This bit is set and cleared by software. It is used together with the SLOW bit to
configure the ADC clock speed. Refer to the table in the SLOW bit description
(ADCDRL register).
Bit 5 = ADON A/D Converter on bit
This bit is set and cleared by software.
0: A/D converter is switched off
1: A/D converter is switched on
Bit 4 = Reserved, must be kept cleared.
Bits 3:0 = CH[3:0] Channel Selection
These bits select the analog input to convert. They are set and cleared by software.
Table 55. Channel selection using CH[3:0]
Channel Pin(1)
CH3
CH2
CH1
CH0
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
1. The number of channels is device dependent. Refer to the device pinout description.
176/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
On-chip peripherals
Data register High (ADCDRH)
Reset value: xxxx xxxx (xxh)
7
0
D9
D8
D7
D6
D5
D4
D3
D2
Read only
Bits 7:0 = D[9:2] MSB of Analog Converted Value
ADC Control/data register Low (ADCDRL)
Reset value: 0000 00xx (0xh)
7
0
0
0
0
0
SLOW
Read/write
0
D1
D0
Bits 7:4 = Reserved. Forced by hardware to 0.
Bit 3 = SLOW Slow mode bit
This bit is set and cleared by software. It is used together with the SPEED bit in the
ADCCSR register to configure the ADC clock speed as shown on the table below.
Table 56. Configuring the ADC clock speed
(1)
fADC
SLOW
SPEED
fCPU/2
0
0
1
0
1
x
fCPU
fCPU/4
1. The maximum allowed value of fADC is 4 MHz (see Section 12.11 on page 209)
Bit 2 = Reserved. Forced by hardware to 0.
Bits 1:0 = D[1:0] LSB of Analog Converted value
Table 57. ADC register mapping and reset values
Address
(Hex.)
Register
label
7
6
5
4
3
2
1
0
ADCCSR
Reset Value
EOC SPEED ADON
0
0
CH3
0
CH2
0
CH1
0
CH0
0
0036h
0037h
0038h
0
0
0
ADCDRH
Reset Value
D9
x
D8
x
D7
x
D6
x
D5
x
D4
x
D3
x
D2
x
ADCDRL
Reset Value
0
0
0
0
0
0
SLOW
0
D1
x
D0
x
0
0
177/226
Instruction set
ST7FOXF1, ST7FOXK1, ST7FOXK2
11
Instruction set
11.1
ST7 addressing modes
The ST7 core features 17 different addressing modes which can be classified in seven main
groups:
Table 58. Description of addressing modes
Addressing mode
Example
Inherent
Immediate
Direct
nop
ld A,#$55
ld A,$55
Indexed
ld A,($55,X)
ld A,([$55],X)
jrne loop
Indirect
Relative
Bit operation
bset byte,#5
The ST7 instruction set is designed to minimize the number of bytes required per
instruction: To do so, most of the addressing modes may be subdivided in two submodes
called long and short:
■
Long addressing mode is more powerful because it can use the full 64 Kbyte address
space, however it uses more bytes and more CPU cycles.
■
Short addressing mode is less powerful because it can generally only access page
zero (0000h - 00FFh range), but the instruction size is more compact, and faster. All
memory to memory instructions use short addressing modes only (CLR, CPL, NEG,
BSET, BRES, BTJT, BTJF, INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP)
The ST7 Assembler optimizes the use of long and short addressing modes.
Table 59. ST7 addressing mode overview
Destination/
source
Pointer
address
Pointer
size
Length
(bytes)
Mode
Syntax
Inherent
Immediate
Short
nop
+ 0
+ 1
+ 1
+ 2
ld A,#$55
ld A,$10
ld A,$1000
Direct
Direct
00..FF
Long
0000..FFFF
+ 0 (with X register)
+ 1 (with Y register)
No Offset
Direct
Indexed
Indexed
ld A,(X)
00..FF
Short
Long
Short
Long
Short
Direct
Direct
ld A,($10,X)
00..1FE
0000..FFFF
00..FF
+ 1
+ 2
+ 2
+ 2
+ 2
Indexed ld A,($1000,X)
ld A,[$10]
Indirect
Indirect
Indirect
00..FF
00..FF
00..FF
byte
word
byte
ld A,[$10.w]
0000..FFFF
00..1FE
Indexed
ld A,([$10],X)
178/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
Instruction set
Table 59. ST7 addressing mode overview (continued)
Destination/
source
Pointer
address
Pointer
size
Length
(bytes)
Mode
Syntax
ld
Long
Indirect
Direct
Indexed
0000..FFFF
00..FF
word
+ 2
+ 1
+ 2
A,([$10.w],X)
PC-
Relative
Relative
jrne loop
jrne [$10]
128/PC+127(1)
PC-
Indirect
00..FF
00..FF
byte
byte
128/PC+127(1)
Bit
Bit
Direct
bset $10,#7
00..FF
00..FF
+ 1
+ 2
Indirect
bset [$10],#7
btjt
$10,#7,skip
Bit
Bit
Direct
Relative
Relative
00..FF
00..FF
+ 2
+ 3
btjt
Indirect
00..FF
byte
[$10],#7,skip
1. At the time the instruction is executed, the Program Counter (PC) points to the instruction following JRxx.
11.1.1
Inherent mode
All Inherent instructions consist of a single byte. The opcode fully specifies all the required
information for the CPU to process the operation.
Table 60. Instructions supporting inherent addressing mode
Instruction
Function
NOP
TRAP
WFI
No operation
S/W interrupt
Wait for interrupt (low power mode)
Halt oscillator (lowest power mode)
Subroutine return
HALT
RET
IRET
Interrupt subroutine return
Set interrupt mask
Reset interrupt mask
Set carry flag
SIM
RIM
SCF
RCF
Reset carry flag
RSP
Reset stack pointer
Load
LD
CLR
Clear
PUSH/POP
INC/DEC
TNZ
Push/Pop to/from the stack
Increment/decrement
Test negative or zero
1 or 2 complement
CPL, NEG
179/226
Instruction set
ST7FOXF1, ST7FOXK1, ST7FOXK2
Table 60. Instructions supporting inherent addressing mode (continued)
Instruction
Function
MUL
SLL, SRL, SRA, RLC, RRC
SWAP
Byte multiplication
Shift and rotate operations
Swap nibbles
11.1.2
Immediate mode
Immediate instructions have 2 bytes, the first byte contains the opcode, the second byte
contains the operand value.
Imm
Table 61. Instructions supporting inherent immediate addressing mode
Immediate Instruction
Function
LD
CP
Load
Compare
BCP
Bit compare
AND, OR, XOR
ADC, ADD, SUB, SBC
Logical operations
Arithmetic operations
11.1.3
Direct modes
In Direct instructions, the operands are referenced by their memory address.
The direct addressing mode consists of two submodes:
Direct (Short) addressing mode
The address is a byte, thus requires only 1 byte after the opcode, but only allows 00 - FF
addressing space.
Direct (Long) addressing mode
The address is a word, thus allowing 64 Kbyte addressing space, but requires 2 bytes after
the opcode.
11.1.4
Indexed modes (No Offset, Short, Long)
In this mode, the operand is referenced by its memory address, which is defined by the
unsigned addition of an index register (X or Y) with an offset.
The indirect addressing mode consists of three submodes:
Indexed mode (No Offset)
There is no offset (no extra byte after the opcode), and allows 00 - FF addressing space.
Indexed mode (Short)
The offset is a byte, thus requires only 1 byte after the opcode and allows 00 - 1FE
addressing space.
180/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
Indexed mode (long)
Instruction set
The offset is a word, thus allowing 64 Kbyte addressing space and requires 2 bytes after the
opcode.
11.1.5
Indirect modes (short, long)
The required data byte to do the operation is found by its memory address, located in
memory (pointer).
The pointer address follows the opcode. The indirect addressing mode consists of two
submodes:
Indirect mode (short)
The pointer address is a byte, the pointer size is a byte, thus allowing 00 - FF addressing
space, and requires 1 byte after the opcode.
Indirect mode (long)
The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing
space, and requires 1 byte after the opcode.
11.1.6
Indirect indexed modes (short, long)
This is a combination of indirect and short indexed addressing modes. The operand is
referenced by its memory address, which is defined by the unsigned addition of an index
register value (X or Y) with a pointer value located in memory. The pointer address follows
the opcode.
The indirect indexed addressing mode consists of two submodes:
Indirect indexed mode (short)
The pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1FE addressing
space, and requires 1 byte after the opcode.
Indirect indexed mode (long)
The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing
space, and requires 1 byte after the opcode.
Table 62. Instructions supporting direct, indexed, indirect and indirect indexed
addressing modes
Instructions
Function
Long and short instructions
LD
CP
Load
Compare
AND, OR, XOR
ADC, ADD, SUB, SBC
BCP
Logical operations
Arithmetic addition/subtraction operations
Bit compare
181/226
Instruction set
ST7FOXF1, ST7FOXK1, ST7FOXK2
Table 62. Instructions supporting direct, indexed, indirect and indirect indexed
addressing modes (continued)
Instructions
Short instructions only
Function
CLR
INC, DEC
Clear
Increment/decrement
Test negative or zero
1 or 2 complement
Bit operations
TNZ
CPL, NEG
BSET, BRES
BTJT, BTJF
SLL, SRL, SRA, RLC, RRC
SWAP
Bit test and jump operations
Shift and rotate operations
Swap nibbles
CALL, JP
Call or jump subroutine
11.1.7
Relative modes (direct, indirect)
This addressing mode is used to modify the PC register value by adding an 8-bit signed
offset to it.
Table 63. Instructions supporting relative modes
Available Relative Direct/Indirect instructions
Function
JRxx
Conditional jump
Call relative
CALLR
The relative addressing mode consists of two submodes:
Relative mode (Direct)
The offset follows the opcode.
Relative mode (Indirect)
The offset is defined in memory, of which the address follows the opcode.
182/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
Instruction set
11.2
Instruction groups
The ST7 family devices use an Instruction Set consisting of 63 instructions. The instructions
may be subdivided into 13 main groups as illustrated in the following table:
Table 64. ST7 instruction set
Load and Transfer
Stack operation
LD
CLR
PUSH POP
RSP
Increment/decrement
Compare and tests
INC
CP
DEC
TNZ
OR
BCP
Logical operations
AND
XOR CPL NEG
Bit operation
BSET BRES
BTJT BTJF
Conditional bit test and branch
Arithmetic operations
Shift and rotate
ADC
SLL
ADD
SRL
JRT
SUB SBC MUL
SRA RLC RRC SWAP SLA
Unconditional jump or call
Conditional branch
JRA
JRF
JP
CALL CALLR NOP RET
JRxx
TRAP
SIM
Interruption management
Condition Code Flag modification
WFI
RIM
HALT IRET
SCF RCF
Using a prebyte
The instructions are described with 1 to 4 bytes.
In order to extend the number of available opcodes for an 8-bit CPU (256 opcodes), three
different prebyte opcodes are defined. These prebytes modify the meaning of the instruction
they precede.
The whole instruction becomes by:
PC-2 End of previous instruction
PC-1 Prebyte
PC Opcode
PC+1 Additional word (0 to 2) according to the number of bytes required to compute
the effective address
These prebytes enable instruction in Y as well as indirect addressing modes to be
implemented. They precede the opcode of the instruction in X or the instruction using direct
addressing mode. The prebytes are:
PDY 90 Replace an X based instruction using immediate, direct, indexed, or inherent
addressing mode by a Y one.
PIX 92 Replace an instruction using direct, direct bit or direct relative addressing mode
to an instruction using the corresponding indirect addressing mode.
It also changes an instruction using X indexed addressing mode to an instruction using
indirect X indexed addressing mode.
PIY 91 Replace an instruction using X indirect indexed addressing mode by a Y one.
183/226
Instruction set
ST7FOXF1, ST7FOXK1, ST7FOXK2
11.2.1
Illegal opcode reset
In order to provide enhanced robustness to the device against unexpected behavior, a
system of illegal opcode detection is implemented: a reset is generated if the code to be
executed does not correspond to any opcode or prebyte value. This, combined with the
Watchdog, allows the detection and recovery from an unexpected fault or interference.
A valid prebyte associated with a valid opcode forming an unauthorized combination does
not generate a reset.
I
Table 65. Illegal opcode detection
Mnemo
Description
Function/Example
Dst
Src
H
I
N
Z
C
ADC
ADD
AND
BCP
BRES
BSET
BTJF
BTJT
CALL
CALLR
CLR
CP
Add with Carry
Addition
A = A + M + C
A = A + M
A
A
M
M
M
M
H
H
N
N
N
N
Z
Z
Z
Z
C
C
Logical And
A = A . M
A
Bit compare A, Memory
Bit Reset
tst (A . M)
A
bres Byte, #3
bset Byte, #3
btjf Byte, #3, Jmp1
btjt Byte, #3, Jmp1
M
M
M
M
Bit Set
Jump if bit is false (0)
Jump if bit is true (1)
Call subroutine
Call subroutine relative
Clear
C
C
reg, M
reg
0
N
N
N
1
Z
Z
Z
Arithmetic Compare
One Complement
Decrement
tst(Reg - M)
A = FFH-A
dec Y
M
C
1
CPL
reg, M
reg, M
DEC
HALT
IRET
INC
Halt
0
I
Interrupt routine return
Increment
Pop CC, A, X, PC
inc X
H
N
N
Z
Z
C
reg, M
JP
Absolute Jump
Jump relative always
Jump relative
jp [TBL.w]
JRA
JRT
JRF
Never jump
jrf *
JRIH
JRIL
JRH
Jump if ext. interrupt = 1
Jump if ext. interrupt = 0
Jump if H = 1
H = 1 ?
H = 0 ?
I = 1 ?
I = 0 ?
N = 1 ?
JRNH
JRM
JRNM
JRMI
Jump if H = 0
Jump if I = 1
Jump if I = 0
Jump if N = 1 (minus)
184/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
Instruction set
Table 65. Illegal opcode detection (continued)
Mnemo
Description
Function/Example
Dst
Src
H
I
N
Z
C
JRPL
JREQ
JRNE
JRC
Jump if N = 0 (plus)
Jump if Z = 1 (equal)
Jump if Z = 0 (not equal)
Jump if C = 1
N = 0 ?
Z = 1 ?
Z = 0 ?
C = 1 ?
JRNC
JRULT
JRUGE
JRUGT
JRULE
LD
Jump if C = 0
C = 0 ?
Jump if C = 1
Unsigned <
Jmp if unsigned >=
Unsigned >
Unsigned <=
dst <= src
X,A = X * A
neg $10
Jump if C = 0
Jump if (C + Z = 0)
Jump if (C + Z = 1)
Load
reg, M
A, X, Y
reg, M
M, reg
X, Y, A
N
N
N
N
Z
Z
Z
Z
MUL
Multiply
0
0
NEG
Negate (2's compl)
No Operation
C
NOP
OR
OR operation
A = A + M
pop reg
pop CC
push Y
C = 0
A
M
M
POP
Pop from the Stack
reg
CC
M
M
H
I
C
0
PUSH
RCF
RET
RIM
Push onto the Stack
Reset carry flag
Subroutine Return
Enable Interrupts
Rotate left true C
Rotate right true C
Reset Stack Pointer
Subtract with Carry
Set carry flag
reg, CC
I = 0
0
RLC
RRC
RSP
SBC
SCF
SIM
C <= Dst <= C
C => Dst => C
S = Max allowed
A = A - M - C
C = 1
reg, M
reg, M
N
N
Z
Z
C
C
A
M
N
Z
C
1
Disable Interrupts
Shift left Arithmetic
Shift left Logic
I = 1
1
SLA
C <= Dst <= 0
C <= Dst <= 0
0 => Dst => C
Dst7 => Dst => C
A = A - M
reg, M
reg, M
reg, M
reg, M
A
N
N
0
Z
Z
Z
Z
Z
Z
Z
C
C
C
C
C
SLL
SRL
SRA
SUB
SWAP
TNZ
TRAP
Shift right Logic
Shift right Arithmetic
Subtraction
N
N
N
N
M
SWAP nibbles
Dst[7..4]<=>Dst[3..0] reg, M
tnz lbl1
Test for Neg & Zero
S/W trap
S/W interrupt
1
185/226
Instruction set
ST7FOXF1, ST7FOXK1, ST7FOXK2
Table 65. Illegal opcode detection (continued)
Mnemo
Description
Function/Example
Dst
Src
H
I
N
Z
C
WFI
Wait for Interrupt
Exclusive OR
0
XOR
A = A XOR M
A
M
N
Z
186/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
Electrical characteristics
12
Electrical characteristics
12.1
Parameter conditions
Unless otherwise specified, all voltages are referred to V
.
SS
12.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at T = 25 °C and T = T max (given by
A
A
A
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean±3Σ).
12.1.2
Typical values
Unless otherwise specified, typical data are based on T = 25 °C, V = 5 V (for the
A
DD
4.5 V≤ V ≤ 5.5 V voltage range). They are given only as design guidelines and are not
DD
tested.
12.1.3
12.1.4
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 81.
Figure 81. Pin loading conditions
ST7 PIN
C
L
12.1.5
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 82.
187/226
Electrical characteristics
ST7FOXF1, ST7FOXK1, ST7FOXK2
Figure 82. Pin input voltage
ST7 PIN
V
IN
12.2
Absolute maximum ratings
Stresses above those listed as “absolute maximum ratings” may cause permanent damage
to the device. This is a stress rating only and functional operation of the device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
Table 66. Voltage characteristics
Symbol
DD - VSS
VIN
Ratings
Maximum value
Unit
V
Supply voltage
7.0
V
Input voltage on any pin(1)(2)
VSS-0.3 to VDD+0.3
Electrostatic discharge voltage (Human Body
model)
VESD(HBM)
VESD(CDM)
see Section 12.8.3 on page
203
Electrostatic discharge voltage (Charge Device
model)
1. Directly connecting the RESET and I/O pins to VDD or VSS could damage the device if an unintentional
internal reset is generated or an unexpected change of the I/O configuration occurs (for example, due to a
corrupted Program Counter). To guarantee safe operation, this connection has to be done through a pull-
up or pull-down resistor (typical: 4.7 kΩ for RESET, 10 kΩ for I/Os). Unused I/O pins must be tied in the
same way to VDD or VSS according to their reset configuration.
2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. For true open-drain
pads, there is no positive injection current, and the corresponding VIN maximum must always be respected
188/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
Electrical characteristics
Table 67. Current characteristics
Symbol
Ratings
Maximum value
Unit
IVDD
IVSS
Total current into VDD power lines (source)(1)
Total current out of VSS ground lines (sink)(1)
75
150
Output current sunk by any standard I/O and control
pin
20
IIO
Output current sunk by any high sink I/O pin
Output current source by any I/Os and control pin
Injected current on RESET pin
40
- 25
± 5
± 5
± 5
mA
(2)(3)
IINJ(PIN)
Injected current on OSC1/CLKIN and OSC2 pins
Injected current on any other pin(4)
Total injected current (sum of all I/O and control
pins)(4)
(2)
ΣIINJ(PIN)
± 20
1. All power (VDD) and ground (VSS) lines must always be connected to the external supply.
2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. For true open-drain
pads, there is no positive injection current, and the corresponding VIN maximum must always be respected
3. Negative injection disturbs the analog performance of the device. In particular, it induces leakage currents
throughout the device including the analog inputs. To avoid undesirable effects on the analog functions,
care must be taken:
- Analog input pins must have a negative injection less than 0.8 mA (assuming that the impedance of the
analog voltage is lower than the specified limits)
- Pure digital pins must have a negative injection less than 1.6 mA. In addition, it is recommended to inject
the current as far as possible from the analog input pins.
4. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values). These results are based on
characterization with ΣIINJ(PIN) maximum current injection on four I/O port pins of the device.
Table 68. Thermal characteristics
Symbol
Ratings
Value
Unit
TSTG
Storage temperature range
-65 to +150
°C
Maximum junction temperature (see Table 101: Thermal characteristics on
page 224)
TJ
189/226
Electrical characteristics
ST7FOXF1, ST7FOXK1, ST7FOXK2
12.3
Operating conditions
12.3.1
General operating conditions
T = -40 to +85 °C unless otherwise specified.
A
Table 69. General operating conditions
Symbol
Parameter
Conditions
Min
Max
Unit
VDD
fCPU
Supply voltage
fCPU = 8 MHz max.
4.5
5.5
V
CPU clock frequency
4.5 V≤ VDD≤5.5 V
up to 8
MHz
12.3.2
Operating conditions with Low Voltage Detector (LVD)
T = -40 to 85 °C unless otherwise specified.
A
,
Table 70. Operating characteristics with LVD
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Reset release threshold
(VDD rise)
VIT+
3.9
4.2
4.5
(LVD)
V
Reset generation threshold
(VDD fall)
VIT-
3.7
2
4.0
4.3
(LVD)
Vhys
VtPOR
LVD voltage threshold hysteresis
VDD rise time rate(1)(2)
VIT+(LVD)-VIT-
150
mV
µs/V
µA
(LVD)
IDD(LVD)
LVD current consumption
VDD = 5 V
80
140
1. Not tested in production. The VDD rise time rate condition is needed to ensure a correct device power-on
and LVD reset release. When the VDD slope is outside these values, the LVD may not release properly the
reset of the MCU.
2. Use of LVD with capacitive power supply: with this type of power supply, if power cuts occur in the
application, it is recommended to pull VDD down to 0 V to ensure optimum restart conditions. Refer to
circuit example in Figure 89 on page 207.
190/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
Electrical characteristics
12.3.3
Internal RC oscillator
To improve clock stability and frequency accuracy, it is recommended to place a decoupling
capacitor, typically 100 nF, between the V and V pins as close as possible to the ST7
DD
SS
device
Internal RC oscillator calibrated at 5.0 V
The ST7 internal clock can be supplied by an internal RC oscillator (selectable by option
byte).
Table 71. Internal RC oscillator characteristics (5.0 V calibration)
Symbol
Parameter
Conditions
Min
Typ
Max Unit
RCCR = FF (reset value),
TA = 25 °C, VDD = 5 V
5.5
Internal RC oscillator
frequency
fRC
MHz
RCCR=RCCR0(1)
,
8
6
TA = 25 °C, VDD = 5 V
RC trimming
granularity
fG(RC)
ACCRC
tsu(RC)
TA = 25 °C, VDD = 5 V
kHz
%
TA = 25 °C, VDD = 5 V (2)
without user calibration
±7
TA = 25 °C, VDD = 4.5 to 5.5 V (2)
with user calibration
-2
2
4
%
%
Accuracy of Internal
RC oscillator with
RCCR=RCCR01)
TA= 0 to +85 °C,
VDD = 4.5 to 5.5 V(2)
with user calibration
-2.5
TA = -40 to 0 °C,
VDD = 4.5 to 5.5 V(2)
with user calibration
-4
2.5
%
RC oscillator setup
time
TA = 25 °C, VDD = 5 V
4 (3)
µs
1. See Section 6.1.1: Internal RC oscillator
2. Guaranteed by characterization
3. Not tested in production
191/226
Electrical characteristics
ST7FOXF1, ST7FOXK1, ST7FOXK2
12.4
Supply current characteristics
The following current consumption specified for the ST7 functional operating modes over
temperature range does not take into account the clock source current consumption. To get
the total device consumption, the two current values must be added (except for Halt mode
for which the clock is stopped).
12.4.1
Supply current
T = -40 to +85 °C unless otherwise specified.
A
Table 72. Supply current characteristics
Symbol
Parameter
Conditions
Typ
Max
Unit
fCPU = 4 MHz
2.5
5.0
1.1
2
4.5(2)
Supply current in Run mode(1)
fCPU = 8 MHz
9
mA
fCPU = 4 MHz
fCPU = 8 MHz
2(2)
3.5
Supply current in Wait mode(3)
IDD
Supply current in Slow mode(4)
Supply current in Slow-Wait mode(5)
Supply current in AWUFH mode(6)(7)
Supply current in Active Halt mode
Supply current in Halt mode(8)
fCPU/32 = 250 kHz
fCPU/32 = 250 kHz
550
450
50
950
750
100(2)
250
5
µA
120
0.5
TA = 85 °C
1. CPU running with memory access, all I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals in
reset state; clock input (CLKIN) driven by external square wave, LVD disabled.
2. Data based on characterization, not tested in production.
3. All I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals in reset state; clock input (CLKIN)
driven by external square wave, LVD disabled.
4. Slow mode selected with fCPU based on fOSC divided by 32. All I/O pins in input mode with a static value at VDD or VSS (no
load), all peripherals in reset state; clock input (CLKIN) driven by external square wave, LVD disabled.
5. Slow-Wait mode selected with fCPU based on fOSC divided by 32. All I/O pins in input mode with a static value at VDD or
VSS (no load), all peripherals in reset state; clock input (CLKIN) driven by external square wave, LVD disabled.
6. All I/O pins in input mode with a static value at VDD or VSS (no load). Data tested in production at VDD max. and fCPU max.
7. This consumption refers to the Halt period only and not the associated run period which is software dependent.
8. All I/O pins in output mode with a static value at VSS (no load), LVD disabled. Data based on characterization results,
tested in production at VDD max and fCPU max.
192/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
Electrical characteristics
12.4.2
On-chip peripherals
Table 73. On-chip peripheral characteristics
Symbol
Parameter
Conditions
Typ
Unit
IDD(SPI)
IDD(AT)
IDD(I2C)
IDD(ADC)
SPI supply current(1)
12-bit Auto-Reload timer supply current(2)
I2C supply current(3)
fCPU=8 MHz
VDD=5.0 V
VDD=5.0 V
VDD=5.0 V
VDD=5.0 V
200
50
µA
µA
µA
µA
fCPU=8 MHz
fCPU=8 MHz
fADC=4 MHz
1000
600
ADC supply current when converting(4)
1. Data based on a differential IDD measurement between reset configuration and a permanent SPI master
communication (data sent equal to 55h).
2. Data based on a differential IDD measurement between reset configuration (timer stopped) and a timer
running in PWM mode at fcpu= 8 MHz.
3. Data based on a differential IDD measurement between reset configuration (I2C disabled) and a permanent
I2C master communication at 100 kHz (data sent equal to 55h). This measurement include the pad
toggling consumption (4.7 kOhm external pull-up on clock and data lines).
4. Data based on a differential IDD measurement between reset configuration and continuous A/D
conversions.
193/226
Electrical characteristics
ST7FOXF1, ST7FOXK1, ST7FOXK2
12.5
Communication interface characteristics
2
12.5.1
I C interface
Subject to general operating conditions for V , f
, and T unless otherwise specified.
A
DD OSC
Refer to I/O port characteristics for more details on the input/output alternate function
2
characteristics (SDAI and SCLI). The ST7 I C interface meets the electrical and timing
2
requirements of the Standard I C communication protocol.
T = -40°C to 85 °C, unless otherwise specified.
A
2
Table 74. I C interface characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
f
CPU=4 MHz to 8 MHz,
VDD= 4.5 to 5.5 V
(1)
fSCL
I²C SCL frequency
400
kHz
1. The I2C interface will not function below the minimum clock speed of 4 MHz (see Table 75).
2
Table 102 gives the values to be written in the I2CCCR register to obtain the required I C
SCL line frequency.
2
(1)(2)(3)
Table 75. SCL frequency (multimaster I C interface)
I2CCCR Value
fCPU = 4 MHz, VDD = 5 V
RP=3.3kΩ RP=4.7kΩ
fCPU = 8 MHz, VDD = 5 V
fSCL
RP=3.3kΩ
RP=4.7kΩ
400
300
200
100
50
NA
NA
NA
NA
84h
86h
8Ah
25h
4Dh
FFh
84h
86h
8Ah
24h
4Ch
FFh
84h
11h
25h
61h
84h
11h
25h
62h
20
1. RP = External pull-up resistance, fSCL = I2C speed.
2. For fast mode speeds, achieved speed can have ±5% tolerance. For other speed ranges, achieved speed can have ±2%
tolerance.
3. The above variations depend on the accuracy of the external components used.
194/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
Electrical characteristics
12.5.2
SPI interface
Subject to general operating conditions for V , f
, and T unless otherwise specified.
A
DD OSC
Refer to I/O port characteristics for more details on the input/output alternate function
characteristics (SS, SCK, MOSI, MISO).
Table 76. SPI interface characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
Master
CPU=8MHz
f
CPU/128
0.0625
fCPU/4
2
f
fSCK
1/tc(SCK)
SPI clock frequency
MHz
Slave
f
CPU/2
4
0
fCPU=8MHz
tr(SCK)
tf(SCK)
SPI clock rise and fall time
see I/O port pin description
(1)
tsu(SS)
SS setup time (2)
SS hold time
Slave
Slave
(4 x TCPU) + 50
120
(1)
th(SS)
(1)
tw(SCKH)
tw(SCKL)
Master
Slave
100
90
SCK high and low time
Data input setup time
Data input hold time
(1)
(1)
tsu(MI)
tsu(SI)
Master
Slave
100
100
(1)
(1)
(1)
th(MI)
th(SI)
Master
Slave
100
100
ns
(1)
ta(SO)
Data output access time
Data output disable time
Data output valid time
Data output hold time
Data output valid time
Data output hold time
Slave
Slave
0
120
240
120
(1)
tdis(SO)
(1)
tv(SO)
th(SO)
tv(MO)
th(MO)
Slave (after
enable edge)
(1)
0
0
(1)
(1)
120
Master (after
enable edge)
1. Data based on design simulation, not tested in production.
2. Depends on fCPU. For example, if fCPU=8 MHz, then TCPU = 1/fCPU =125 ns and tsu(SS)=550 ns
195/226
Electrical characteristics
ST7FOXF1, ST7FOXK1, ST7FOXK2
Figure 83. SPI slave timing diagram with CPHA=0
SS
INPUT
t
t
su(SS)
c(SCK)
t
h(SS)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
t
t
w(SCKH)
w(SCKL)
t
t
t
t
dis(SO)
a(SO)
v(SO)
h(SO)
t
t
r(SCK)
f(SCK)
see
note 2
LSB OUT
MISO
OUTPUT
INPUT
MSB OUT
see note 2
BIT6 OUT
t
t
h(SI)
su(SI)
MSB IN
LSB IN
BIT1 IN
MOSI
1. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave
mode) has its alternate function capability released. In this case, the pin status depends on the I/O port
configuration.
Figure 84. SPI slave timing diagram with CPHA=1
SS
INPUT
t
t
su(SS)
c(SCK)
t
h(SS)
CPHA=1
CPOL=0
CPHA=1
CPOL=1
t
t
w(SCKH)
w(SCKL)
t
t
dis(SO)
a(SO)
t
t
h(SO)
v(SO)
t
t
r(SCK)
f(SCK)
see
note 2
see
note 2
MISO
OUTPUT
INPUT
MSB OUT
BIT6 OUT
HZ
LSB OUT
t
t
h(SI)
su(SI)
MSB IN
BIT1 IN
LSB IN
MOSI
1. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave
mode) has its alternate function capability released. In this case, the pin status depends on the I/O port
configuration.
196/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
Electrical characteristics
Figure 85. SPI master timing diagram
SS
INPUT
t
c(SCK)
CPHA = 0
CPOL = 0
CPHA = 0
CPOL = 1
CPHA = 1
CPOL = 0
CPHA = 1
CPOL = 1
t
t
w(SCKH)
w(SCKL)
t
t
r(SCK)
f(SCK)
t
t
h(MI)
su(MI)
MISO
INPUT
MSB IN
BIT6 IN
LSB IN
t
t
v(MO)
h(MO)
MSB OUT
LSB OUT
See note 2
BIT6 OUT
See note 2
MOSI
OUTPUT
1. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD
.
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave
mode) has its alternate function capability released. In this case, the pin status depends of the I/O port
configuration.
12.6
Clock and timing characteristics
Subject to general operating conditions for V , f
, and T .
A
DD OSC
Table 77. General timings
Symbol
Parameter(1)
Conditions
Min
Typ(2)
Max
Unit
2
3
12
1500
22
tCPU
ns
tc(INST)
Instruction cycle time
fCPU = 8 MHz
fCPU = 8 MHz
250
10
375
Interrupt reaction time(3)
tv(IT) = ∆tc(INST) + 10
tCPU
µs
tv(IT)
1.25
2.75
1. Guaranteed by Design. Not tested in production.
2. Data based on typical application software.
3. Time measured between interrupt event and interrupt vector fetch. ∆tc(INST) is the number of tCPU cycles
needed to finish the current instruction execution.
197/226
Electrical characteristics
ST7FOXF1, ST7FOXK1, ST7FOXK2
Table 78. External clock source characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
V
OSC1H or
OSC1/CLKIN input pin high
level voltage
0.7xVDD
VDD
VCLKIN_H
V
VOSC1L or
VCLKIN_L
OSC1/CLKIN input pin low
level voltage
VSS
15
0.3xVDD
tw(OSC1H) or
tw(CLKINH)
tw(OSC1L) or
tw(CLKINL)
see Figure 86
OSC1/CLKIN high or low
time(1)
ns
tr(OSC1) or r(CLKIN)
t
OSC1/CLKIN rise or fall time(1)
15
±1
tf(OSC1) or f(CLKIN)
t
OSCx/CLKIN Input leakage
current
IL
VSS≤VIN≤VDD
µA
1. Data based on design simulation and/or technology characteristics, not tested in production.
Figure 86. Typical application with an external clock source
90%
V
V
or V
OSC1H
OSC1L
CLKINH
10%
or V
CLKINL
t
t
w(OSC1H or CLKINH))
t
t
w(OSC1L or CLKINL)
f(OSC1 or CLKIN)
r(OSC1 or CLKIN))
OSC2
Not connected internally
f
OSC
EXTERNAL
CLOCK SOURCE
I
L
OSC1/CLKIN
ST7xxx
12.6.1
Auto wakeup from Halt oscillator (AWU)
Table 79. AWU from Halt characteristics
Symbol
Parameter(1)
Conditions
Min
Typ
32
Max
Unit
AWU Oscillator
Frequency
fAWU
16
64
kHz
µs
AWU Oscillator startup
time
tRCSRT
50
1. Guaranteed by Design. Not tested in production.
198/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
Electrical characteristics
12.6.2
Crystal and ceramic resonator oscillators
The ST7 internal clock can be supplied with ten different Crystal/Ceramic resonator
oscillators. All the information given in this paragraph are based on characterization results
with specified typical external components. In the application, the resonator and the load
capacitors have to be placed as close as possible to the oscillator pins in order to minimize
output distortion and start-up stabilization time. Refer to the crystal/ceramic resonator
manufacturer for more details (frequency, package, accuracy...).
Table 80. Crystal/ceramic resonator oscillator characteristics
Symbol
Parameter
Conditions
Min Typ Max Unit
fCrOSC
Crystal oscillator frequency
2
16 MHz
Recommended load capacitance
versus equivalent serial
CL1
CL2
TBD
pF
resistance of the crystal or
ceramic resonator (RS)
Figure 87. Typical application with a crystal or ceramic resonator
WHEN RESONATOR WITH
INTEGRATED CAPACITORS
i
2
fOSC
CL1
OSC1
OSC2
RESONATOR
CL2
ST7FOX
R
d
199/226
Electrical characteristics
ST7FOXF1, ST7FOXK1, ST7FOXK2
12.7
Memory characteristics
T = -40 °C to 85 °C, unless otherwise specified.
A
Table 81. RAM and hardware registers characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VRM
Data retention mode(1)
Halt mode (or Reset)
1.6
V
1. Minimum VDD supply voltage without losing data stored in RAM (in Halt mode or under Reset) or in
hardware registers (only in Halt mode). Guaranteed by construction, not tested in production.
Table 82. Flash program memory characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Refer to operating
range of VDD with TA,
Section 12.3.1 on
page 190
Operating voltage for Flash
Write/Erase
VDD
4.5
5.5
V
Programming time for 1~32
bytes(1)
TA=−40 to +85 °C
5
10
ms
tprog
Programming time for 4 kbytes
Data retention(2)
TA=+25 °C
TA=+55 °C(3)
TA=+25 °C
0.64 1.28
s
tRET
NRW
20
years
cycles
Write erase cycles
1k
Read / Write / Erase
modes
2.6
mA
fCPU = 8 MHz,
VDD = 5.5 V
IDD
Supply current(4)
No Read/No Write
mode
100
µA
µA
Power down mode /
Halt
0
0.1
1. Up to 32 bytes can be programmed at a time.
2. Data based on reliability test results and monitored in production.
3. The data retention time increases when the TA decreases.
4. Guaranteed by Design. Not tested in production.
200/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
Electrical characteristics
12.8
EMC (electromagnetic compatibility) characteristics
Susceptibility tests are performed on a sample basis during product characterization.
12.8.1
Functional EMS (electromagnetic susceptibility)
Based on a simple running application on the product (toggling two LEDs through I/O ports),
the product is stressed by two electromagnetic events until a failure occurs (indicated by the
LEDs).
■
ESD: Electrostatic Discharge (positive and negative) is applied on all pins of the device
until a functional disturbance occurs. This test conforms with the IEC 1000-4-2
standard.
■
FTB: A Burst of Fast Transient voltage (positive and negative) is applied to V and
DD
V
through a 100 pF capacitor, until a functional disturbance occurs. This test
SS
conforms with the IEC 1000-4-4 standard.
A device reset allows normal operations to be resumed. The test results are given in the
table below based on the EMS levels and classes defined in application note AN1709.
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
■
Software recommendations
The software flowchart must include the management of runaway conditions such as:
–
–
–
Corrupted Program Counter
Unexpected reset
Critical Data corruption (control registers...)
■
Prequalification trials
Most of the common failures (unexpected reset and Program Counter corruption) can
be reproduced by manually forcing a low state on the RESET pin or the Oscillator pins
for 1 second.
To complete these trials, ESD stress can be applied directly on the device, over the
range of specification values. When unexpected behavior is detected, the software can
be hardened to prevent unrecoverable errors occurring (see application note AN1015).
Table 83. EMS test results
Level/
Class
Symbol
Parameter
Conditions
Voltage limits to be applied on any I/O pin VDD=5 V, TA=+25 °C, fOSC=8 MHz
VFESD
2B
3B
to induce a functional disturbance
conforms to IEC 1000-4-2
Fast transient voltage burst limits to be
applied through 100pF on VDD and VSS
pins to induce a functional disturbance
VDD=5 V, TA=+25 °C, fOSC=8 MHz
VFFTB
conforms to IEC 1000-4-4
201/226
Electrical characteristics
ST7FOXF1, ST7FOXK1, ST7FOXK2
12.8.2
EMI (Electromagnetic interference)
Based on a simple application running on the product (toggling two LEDs through the I/O
ports), the product is monitored in terms of emission. This emission test is in line with the
norm SAE J 1752/3 which specifies the board and the loading of each pin.
Table 84. EMI emissions
Max vs.
Unit
Monitored
[fOSC/fCPU
]
Symbol Parameter
Conditions
frequency band
8/4MHz 16/8MHz
0.1 MHz to 30 MHz
30 MHz to 130 MHz
130 MHz to 1 GHz
SAE EMI Level
28
31
18
3
32
34
26
3.5
VDD=5 V, TA = +25 °C,
conforming to SAE
J 1752/3
dBµV
SEMI
Peak level
-
202/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
Electrical characteristics
12.8.3
Absolute maximum ratings (electrical sensitivity)
Based on two different tests (ESD and LU) using specific measurement methods, the
product is stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts*(n+1) supply pin). Two models
can be simulated: Human Body model and Machine model. This test conforms to the
JESD22-A114A/A115A standard. For more details, refer to the application note AN1181.
Table 85. ESD absolute maximum ratings
Maximum
Symbol
Ratings
Conditions
Unit
value(1)
Electrostatic discharge voltage (Human Body
model)
VESD(HBM)
VESD(CDM)
TA=+25 °C
TA=+25 °C
4000
V
Electrostatic discharge voltage (Charge Device
model)
500
1. Data based on characterization results, not tested in production.
Static latch-up (LU)
Two complementary static tests are required on six parts to assess the latch-up
performance.
■
■
A supply overvoltage is applied to each power supply pin
A current injection is applied to each input, output and configurable I/O pin.
These tests are compliant with the EIA/JESD 78 IC latch-up standard.
Table 86. Electrical sensitivities
Symbol
Parameter
Conditions
Class
LU
Static latch-up class
TA = +85 °C
A
203/226
Electrical characteristics
ST7FOXF1, ST7FOXK1, ST7FOXK2
12.9
I/O port pin characteristics
12.9.1
General characteristics
Subject to general operating conditions for V , f
, and T unless otherwise specified.
A
DD OSC
Table 87. General characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIL
VIH
Input low level voltage
Input high level voltage
VSS - 0.3
0.7VDD
0.3VDD
V
VDD+0.3
Schmitt trigger voltage
hysteresis(1)
Vhys
IL
400
400
mV
Input leakage current
VSS ≤ VIN ≤ VDD
±1
Static current consumption
induced by each floating
input pin(2)
µA
IS
Floating input mode
Weak pull-up equivalent
resistor(3)
RPU
CIO
VIN=VSS
VDD=5 V
100
120
5
140
kΩ
I/O pin capacitance
pF
Output high to low level fall
time(1)
tf(IO)out
25
CL= 50 pF
Between 10% and 90%
ns
Output low to high level rise
time(1)
tr(IO)out
tw(IT)in
25
External interrupt pulse
time(4)
1
tCPU
1. Data based on validation/design results.
2. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for
example or an external pull-up or pull-down resistor (see Figure 88). Static peak current value taken at a fixed VIN value,
based on design simulation and technology characteristics, not tested in production. This value depends on VDD and
temperature values.
3. The RPU pull-up equivalent resistor is based on a resistive transistor.
4. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external
interrupt source.
Figure 88. Two typical applications with unused I/O pin
VDD
ST7XXX
UNUSED I/O PORT
10kΩ
10kΩ
UNUSED I/O PORT
ST7XXX
1. During normal operation the ICCCLK pin must be pulled-up, internally or externally (external pull-up of 10k
mandatory in noisy environment). This is to avoid entering ICC mode unexpectedly during a reset.
2. I/O can be left unconnected if it is configured as output (0 or 1) by the software. This has the advantage of
greater EMC robustness and lower cost.
204/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
Electrical characteristics
12.9.2
Output driving current
Subject to general operating conditions for V , f
, and T unless otherwise specified.
A
DD CPU
Table 88. Output driving current characteristics
Symbol
Parameter
Conditions
Min
Max
1.0
Unit
Output low level voltage for a standard I/O pin
when 8 pins are sunk at same time
IIO=+5 mA, TA≤ 85°C
IIO=+2mA, TA≤ 85°C
IIO=+20mA,TA≤ 85°C
IIO=+8mATA≤ 85°C
0.4
(1)
VOL
Output low level voltage for a high sink I/O pin
when 4 pins are sunk at same time
1.3
V
0.75
Output high level voltage for an I/O pin
when 4 pins are sourced at same time
IIO=-5mA,TA≤ 85°C VDD-1.5
IIO=-2mATA≤ 85°C VDD-0.8
(2)
VOH
1. The IIO current sunk must always respect the absolute maximum rating specified in Section Table 67. and the sum of IIO
(I/O ports and control pins) must not exceed IVSS
.
2. The IIO current sourced must always respect the absolute maximum rating specified in Section Table 67. and the sum of IIO
(I/O ports and control pins) must not exceed IVDD
.
205/226
Electrical characteristics
ST7FOXF1, ST7FOXK1, ST7FOXK2
12.10
Control pin characteristics
12.10.1 Asynchronous RESET pin
T = -40 to 85 °C, unless otherwise specified.
A
Table 89. Asynchronous RESET pin characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIL
VIH
Input low level voltage
Input high level voltage
VSS - 0.3
0.7VDD
0.3VDD
V
VDD+0.3
Vhys
Schmitt trigger voltage hysteresis(1)
Output low level voltage (2)
Pull-up equivalent resistor(3)
Generated reset pulse duration
External reset pulse hold time(4)
Filtered glitch duration
2
V
mV
kΩ
µs
µs
ns
VOL
VDD= 5 V IIO = +2 mA
200
RON
VIN=VSS
VDD = 5 V
30
20
50
70
tw(RSTL)out
th(RSTL)in
tg(RSTL)in
Internal reset sources
90(1)
200
1. Data based on characterization results, not tested in production
2. The IIO current sunk must always respect the absolute maximum rating specified in Section Table 67. on page 189 and the
sum of IIO (I/O ports and control pins) must not exceed IVSS
.
3. The RON pull-up equivalent resistor is based on a resistive transistor. Specified for voltages on RESET pin between VILmax
and VDD
4. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on
RESET pin with a duration below th(RSTL)in can be ignored.
206/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
Electrical characteristics
Figure 89. RESET pin protection when LVD is enabled
VDD
ST7xxx
Optional
(note 3)
Required
R
ON
INTERNAL
RESET
EXTERNAL
RESET
Filter
0.01µF
1MΩ
WATCHDOG
ILLEGALOPCODE
LVD RESET
PULSE
GENERATOR
1. The reset network protects the device against parasitic resets. The output of the external reset circuit must
have an open-drain output to drive the ST7 reset pad. Otherwise the device can be damaged when the
ST7 generates an internal reset (LVD or watchdog). Whatever the reset source is (internal or external), the
user must ensure that the level on the RESET pin can go below the VIL max. level specified in
Section 12.10.1 on page 206. Otherwise the reset will not be taken into account internally. Because the
reset circuit is designed to allow the internal Reset to be output in the RESET pin, the user must ensure
that the current sunk on the RESET pin is less than the absolute maximum value specified for IINJ(RESET) in
Section Table 67. on page 189.
2. When the LVD is enabled, it is recommended not to connect a pull-up resistor or capacitor. A 10nF pull-
down capacitor is required to filter noise on the reset line.
3. In case a capacitive power supply is used, it is recommended to connect a 1MΩ pull-down resistor to the
RESET pin to discharge any residual voltage induced by the capacitive effect of the power supply (this will
add 5µA to the power consumption of the MCU).
Tips when using the LVD
■
Check that all recommendations related to ICCCLK and reset circuit have been applied
(see caution in Table 2 on page 16 and notes above).
■
Check that the power supply is properly decoupled (100nF + 10µF close to the MCU).
Refer to AN1709 and AN2017. If this cannot be done, it is recommended to put a
100nF + 1MΩ pull-down on the RESET pin.
■
The capacitors connected on the RESET pin and also the power supply are key to
avoid any start-up marginality. In most cases, steps 1 and 2 above are sufficient for a
robust solution. Otherwise: replace 10nF pull-down on the RESET pin with a 5µF to
20µF capacitor.”
207/226
Electrical characteristics
ST7FOXF1, ST7FOXK1, ST7FOXK2
Figure 90. RESET pin protection when LVD is disabled
VDD
ST7XXX
R
ON
Filter
INTERNAL
RESET
USER
EXTERNAL
RESET
CIRCUIT
0.01µF
WATCHDOG
PULSE
GENERATOR
ILLEGALOPCODE
Required
1. The reset network protects the device against parasitic resets.
The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad.
Otherwise the device can be damaged when the ST7 generates an internal reset (LVD or watchdog).
Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin
can go below the VIL max. level specified in Section 12.10.1 on page 206. Otherwise the reset will not be
taken into account internally.
Because the reset circuit is designed to allow the internal Reset to be output in the RESET pin, the user
must ensure that the current sunk on the RESET pin is less than the absolute maximum value specified for
I
INJ(RESET) in Section Table 67. on page 189.
2. Please refer to Section 11.2.1 on page 184 for more details on illegal opcode reset conditions.
208/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
Electrical characteristics
12.11
10-bit ADC characteristics
Subject to general operating condition for V , f
, and T unless otherwise specified.
A
DD OSC
Table 90. ADC characteristics
Symbol
Parameter
Conditions
Min
Typ(1)
Max
Unit
fADC
VAIN
ADC clock frequency
4
MHz
V
Conversion voltage range
VSSA
VDDA
8k(2)
10k(2)
VDD = 5 V, fADC = 4 MHz
RAIN
External input resistor
Ω
4.5 V ≤ VDD ≤ 5.5 V, fADC = 2 MHz
Internal sample and hold
capacitor
CADC
tSTAB
6
pF
Stabilization time after ADC
enable
0(3)
3.5
µs
Conversion time (Sample+Hold)
fCPU = 8 MHz, fADC = 4 MHz
tADC
- Sample capacitor loading time
- Hold conversion time
4
10
1/fADC
1. Unless otherwise specified, typical data are based on TA = 25 °C and VDD-VSS = 5 V. They are given only as design
guidelines and are not tested.
2. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than the maximum
value). Data guaranteed by Design, not tested in production.
3. The stabilization time of the A/D converter is masked by the first tLOAD. The first conversion after the enable is then always
valid.
Figure 91. Typical application with ADC
VDD
VT
0.6 V
RAIN
AINx
10-Bit A/D
Conversion
VAIN
VT
0.6 V
IL
±1 µA
CADC
ST7xxx
209/226
Electrical characteristics
ST7FOXF1, ST7FOXK1, ST7FOXK2
Table 91. ADC accuracy with V = 4.5 to 5.5 V
DD
Symbol
Parameter
Conditions
Typ
Max
Unit
(1)
|ET|
|EO|
|EG|
|ED|
|EL|
Total unadjusted error
Offset error
2.0
0.9
1.0
1.2
1.1
5.0
2.5
1.5
3.5
4.5
fCPU=8 MHz,
Gain Error
LSB
fADC=4 MHz(1)
Differential linearity error
Integral linearity error
1. Data based on characterization results over the whole temperature range.
Figure 92. ADC accuracy characteristics
(1) Example of an actual transfer curve
(2) The ideal transfer curve
Digital Result
EG
1023
1022
1021
(3) End point correlation line
V
– V
DD
SS
1024
1LSB
= -------------------------------
ET=Total Unadjusted Error: maximum deviation
between the actual and the ideal transfer
curves.
IDEAL
(2)
ET
EO=Offset Error: deviation between the first
actual transition and the first ideal one.
(3)
7
6
5
4
3
2
1
(1)
EG=Gain Error: deviation between the last
ideal transition and the last actual one.
EO
EL
ED=Differential Linearity Error: maximum
deviation between actual steps and the ideal
one.
ED
EL=Integral Linearity Error: maximum deviation
between any actual transition and the end point
correlation line.
1 LSBIDEAL
0
1
2
3
4
5
6
7
Vin (LSBIDEAL)
1021 1022 1023 1024
VDD
VSS
210/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
Device configuration and ordering information
13
Device configuration and ordering information
This device is available for production in user programmable version (Flash).
ST7FOX XFlash devices are shipped to customers with a default program memory content
(FFh).
13.1
Option bytes
The two option bytes allow the hardware configuration of the microcontroller to be selected.
The option bytes can be accessed only in programming mode (for example using a standard
ST7 programming tool).
13.1.1
Option byte 1
Bits 7:6 = CKSEL[1:0] Start-up clock selection.
These bits are used to select the startup frequency. By default, the internal RC is
selected.
Table 92. Startup clock selection
Configuration
CKSEL1
CKSEL0
Internal RC as Startup Clock
AWU RC as a Startup Clock
External crystal/ceramic resonator
External Clock
0
0
1
1
0
1
0
1
Bits 5:3 = Reserved, must always be 1.
Bit 2 = LVD Low Voltage Detection selection.
This option bit enables the low voltage detection block (LVD).
0: LVD on
1: LVD off (default value)
Bit 1 = WDG SW Hardware or software watchdog
This option bit selects the watchdog type.
0: Hardware (watchdog always enabled)
1: Software (watchdog to be enabled by software)
Bit 0 = WDG HALT Watchdog Reset on Halt
This option bit determines if a Reset is generated when entering Halt mode while the
Watchdog is active.
0: No Reset generation when entering Halt mode
1: Reset generation when entering Halt mode
211/226
Device configuration and ordering information
ST7FOXF1, ST7FOXK1, ST7FOXK2
13.1.2
Option byte 0
OPT 7 = AWUCK Auto Wake Up Clock Selection
0: 32-kHz Oscillator (VLP) selected as AWU clock
1: AWU RC Oscillator selected as AWU clock.
Note:
If this bit is reset, OSCRANGE[2:0] must be set to 100.
OPT6:4 = OSCRANGE[2:0] Oscillator Range
When the internal RC oscillator is not selected (CKSEL1=1), these option bits (and
CKSEL0) select the range of the resonator oscillator current source or the external
clock source.
Table 93. Selection of the resonator oscillator range
OSCRANGE(1)
2
1
0
LP
MP
MS
HS
1~2 MHz
2~4 MHz
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Typ. frequency range
with Resonator
4~8 MHz
8~16 MHz
32.768 kHz
VLP
External Clock on OSC1/CLKIN
Reserved
External Clock on PB1
1. When the internal RC oscillator is selected, the CLKSEL option bits must be kept at their default value in
order to select the 256 clock cycle delay (see Section 6.3).
OPT 3:2 = SEC[1:0] Sector 0 size definition
These option bits indicate the size of sector 0 according to Table 94.
Table 94. Configuration of sector size
Sector 0 Size
SEC1
SEC0
0.5k
1k
0
0
1
1
0
1
0
1
2k
4k
Bit 1 = FMP_R Read-Out Protection
Read-Out Protection, when selected provides a protection against program memory
content extraction and against write access to Flash memory. Erasing the option bytes
when the FMP_R option is selected will cause the whole memory to be erased first,
and the device can be reprogrammed. Refer to Section 4.5 on page 27 and the ST7
Flash Programming Reference Manual for more details.
0: Read-Out Protection off
1: Read-Out Protection on
212/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
Device configuration and ordering information
Bit 0 = FMP_W Flash write protection
This option indicates if the Flash program memory is write protected.
0: Write protection off
1: Write protection on
Warning: When the Flash write protection is selected, the program
memory (and the option bit itself) can never be erased or
programmed again.
Option byte 0
SEC SEC FMP FMP CK CK
Option byte 1
7
0
7
0
AWU
CK
WDG WDG
SW HALT
OSCRANGE[2:0]
Res Res Res LVD
1
0
R
W
SEL1 SEL0
Default value
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
213/226
Device configuration and ordering information
ST7FOXF1, ST7FOXK1, ST7FOXK2
13.2
Device ordering information
Figure 93. ST7FOXF1/ST7FOXK1/ST7FOXK2 ordering information scheme
Example:
ST7 FOX
K
1
B
6
TR
Family
ST7 Microcontroller Family
Sub-family
FOX
No. of pins
F = 20
K = 32
Memory size
1 = 4K
2 = 8K
Package
B = DIP
M = SO
T = LQFP
Temperature range
6 = -40 °C to 85 °C
Shipping
TR = Tape and Reel (available on LQFP32 and SO20 packages only)
Blank = Tube (DIP and SO packages) or Tray (available on LQFP32 only)
For a list of available options (e.g. memory size, package) and orderable part numbers or for fur-
ther information on any aspect of this device, please contact the ST Sales Office nearest to you.
ST7FOX failure analysis service
For ST7FOX family devices, STMicroelectronics agrees to accept return of defective parts
subject to the FAR (Failure Analysis Report ) procedure only if the customer reject rate
exceeds 0.35 % for each delivered batch.
A batch is identified with a single trace code located on the top side marking.
214/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
Device configuration and ordering information
13.3
Development tools
Development tools for the ST7 microcontrollers include a complete range of hardware
systems and software tools from STMicroelectronics and third-party tool suppliers. The
range of tools includes solutions to help you evaluate microcontroller peripherals, develop
and debug your application, and program your microcontrollers.
13.3.1
13.3.2
Starter kits
ST offers complete, affordable starter kits. Starter kits are complete hardware/software tool
packages that include features and samples to help you quickly start developing your
application.
Development and debugging tools
Application development for ST7 is supported by fully optimizing C Compilers and the ST7
Assembler-Linker toolchain, which are all seamlessly integrated in the ST7 integrated
development environments in order to facilitate the debugging and fine-tuning of your
application. The Cosmic C Compiler is available in a free version that outputs up to
16Kbytes of code.
The range of hardware tools includes a full-featured STiceEmulator, the low-cost RLink and
the ST7-STICK in-circuit debugger/programmer. These tools are supported by the ST7
Toolset from STMicroelectronics, which includes the STVD7 integrated development
environment (IDE) with high-level language debugger, editor, project manager and
integrated programming interface.
13.3.3
Programming tools
During the development cycle, the STice emulator, the ST7-STICK and the RLink provide
in-circuit programming capability for programming the Flash microcontroller on your
application board.
ST also provides a low-cost dedicated in-circuit programmer and ST7 Socket Boards,
which provide all the sockets required for programming any of the devices in a specific ST7
sub-family with any tool with in-circuit programming capability for ST7.
For production programming of ST7 devices, ST’s third-party tool partners also provide a
complete range of gang and automated programming solutions, which are ready to integrate
into your production environment.
13.3.4
Order codes for development and programming tools
Table 95 below lists the ordering codes for the ST7FOX development and programming
tools. For additional ordering codes for spare parts and accessories, refer to the online
product selector at www.st.com/mcu.
215/226
Device configuration and ordering information
Table 95. Development tool order codes
ST7FOXF1, ST7FOXK1, ST7FOXK2
ST socket boards
Debugging and
programming tool
MCU
STX-RLINK(1)(2)
ST7-STICK(3)(4)
STice emulator(5)
,
ST7FOXF1
ST7FOXK1
ST7FOXK2
SBX-SO20BE, SBX-DI8-20ZZ,
SBX-DIP32CD,
,
and SBX-QP32BC socket boards (3)
1. USB connection to PC.
2. Available from ST or from Raisonance, www.raisonance.com.
3. Add suffix /EU, /UK or /US for the power supply for your region.
4. Parallel port connection to PC.
5. Contact local ST sales office for sales types.
13.4
ST7 application notes
Table 96. ST7 application notes
Identification
Description
Application examples
Serial numbering implementation
AN1658
AN1720
AN1755
AN1756
AN1812
managing the Read-Out Protection in Flash microcontrollers
A high resolution/precision thermometer using ST7 and NE555
Choosing a DALI implementation strategy with ST7DALI
A high precision, low cost, single supply ADC for positive and negative input voltages
Example drivers
AN 969
AN 970
AN 971
AN 972
AN 973
AN 974
AN 976
AN 979
AN 980
AN1017
AN1041
AN1042
AN1044
AN1045
SCI communication between ST7 and PC
SPI communication between ST7 and EEPROM
I²C communication between ST7 and M24Cxx EEPROM
ST7 software SPI master communication
SCI software communication with a PC using ST72251 16-bit timer
Real time clock with ST7 timer Output Compare
Driving a buzzer through ST7 timer PWM function
Driving an analog keyboard with the ST7 ADC
ST7 keypad decoding techniques, implementing wakeup on keystroke
Using the ST7 Universal Serial Bus microcontroller
Using ST7 PWM signal to generate analog output (sinusoïd)
ST7 routine for I²C Slave mode Management
Multiple interrupt sources management for ST7 MCUs
ST7 S/W implementation of I²C bus master
216/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
Device configuration and ordering information
Description
Table 96. ST7 application notes (continued)
Identification
AN1046
AN1047
AN1048
AN1078
AN1082
AN1083
AN1105
AN1129
AN1130
AN1148
AN1149
AN1180
AN1276
AN1321
AN1325
AN1445
AN1475
AN1504
AN1602
AN1633
AN1712
AN1713
AN1753
AN1947
UART emulation software
Managing reception errors with the ST7 SCI peripherals
ST7 software LCD Driver
PWM duty cycle switch implementing true 0% & 100% duty cycle
Description of the ST72141 motor control peripherals registers
ST72141 BLDC motor control software and flowchart example
ST7 pCAN peripheral driver
PWM management for BLDC motor drives using the ST72141
An introduction to sensorless brushless DC motor drive applications with the ST72141
Using the ST7263 for designing a USB mouse
Handling Suspend mode on a USB mouse
Using the ST7263 kit to implement a USB game pad
BLDC motor start routine for the ST72141 microcontroller
Using the ST72141 motor control MCU in Sensor mode
Using the ST7 USB low-speed firmware V4.x
Emulated 16-bit slave SPI
Developing an ST7265X mass storage application
Starting a PWM signal directly at high level using the ST7 16-bit timer
16-bit timing operations using ST7262 or ST7263B ST7 USB MCUs
Device firmware upgrade (DFU) implementation in ST7 non-USB applications
Generating a high resolution sinewave using ST7 PWMART
SMBus slave driver for ST7 I2C peripherals
Software UART using 12-bit ART
ST7MC PMAC sine wave motor control software library
General purpose
AN1476
AN1526
AN1709
AN1752
Low cost power supply for home appliances
ST7FLITE0 quick reference note
EMC design for ST microcontrollers
ST72324 quick reference note
Product evaluation
AN 910
AN 990
AN1077
AN1086
Performance benchmarking
ST7 benefits vs industry standard
Overview of enhanced CAN controllers for ST7 and ST9 MCUs
U435 can-do solutions for car multiplexing
217/226
Device configuration and ordering information
ST7FOXF1, ST7FOXK1, ST7FOXK2
Table 96. ST7 application notes (continued)
Identification
Description
AN1103
AN1150
AN1151
AN1278
Improved B-EMF detection for low speed, low voltage with ST72141
Benchmark ST72 vs PC16
Performance comparison between ST72254 & PC16F876
LIN (Local Interconnect Network) solutions
Product migration
AN1131
AN1322
AN1365
AN1604
AN2200
Migrating applications from ST72511/311/214/124 to ST72521/321/324
Migrating an application from ST7263 Rev.B to ST7263B
Guidelines for migrating ST72C254 applications to ST72F264
How to use ST7MDT1-TRAIN with ST72F264
Guidelines for migrating ST7LITE1x applications to ST7FLITE1xB
Product optimization
AN 982
AN1014
AN1015
AN1040
AN1070
AN1181
AN1324
AN1502
AN1529
AN1530
AN1605
AN1636
AN1828
AN1946
AN1953
AN1971
Using ST7 with ceramic resonator
How to minimize the ST7 power consumption
Software techniques for improving microcontroller EMC performance
Monitoring the Vbus signal for USB self-powered devices
ST7 checksum self-checking capability
Electrostatic discharge sensitive measurement
Calibrating the RC oscillator of the ST7FLITE0 MCU using the mains
Emulated data EEPROM with ST7 HD Flash memory
Extending the current & voltage capability on the ST7265 VDDF supply
Accurate timebase for low-cost ST7 applications with internal RC oscillator
Using an active RC to wake up the ST7LITE0 from power saving mode
Understanding and minimizing ADC conversion errors
PIR (passive infrared) detector using the ST7FLITE05/09/SUPERLITE
Sensorless BLDC motor control and BEMF sampling methods with ST7MC
PFC for ST7MC starter kit
ST7LITE0 microcontrolled ballast
Programming and tools
AN 978
AN 983
AN 985
AN 986
AN 987
AN 988
ST7 Visual DeVELOP software key debugging features
Key features of the Cosmic ST7 C-compiler package
Executing code In ST7 RAM
Using the indirect addressing mode with ST7
ST7 serial test controller programming
Starting with ST7 assembly tool chain
218/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
Device configuration and ordering information
Description
Table 96. ST7 application notes (continued)
Identification
AN1039
AN1071
AN1106
AN1179
AN1446
AN1477
AN1527
AN1575
AN1576
AN1577
AN1601
AN1603
AN1635
AN1754
AN1796
AN1900
AN1904
AN1905
ST7 math utility routines
Half duplex USB-to-serial bridge using the ST72611 USB microcontroller
Translating assembly code from HC05 to ST7
Programming ST7 Flash microcontrollers in remote ISP mode (In-situ programming)
Using the ST72521 emulator to debug an ST72324 target application
Emulated data EEPROM with XFlash memory
Developing a USB smartcard reader with ST7SCR
On-board programming methods for XFlash and HD Flash ST7 MCUs
In-application programming (IAP) drivers for ST7 HD Flash or XFlash MCUs
Device firmware upgrade (DFU) Implementation for ST7 USB applications
Software implementation for ST7DALI-EVAL
Using the ST7 USB device firmware upgrade development kit (DFU-DK)
ST7 customer ROM code release information
Data logging program for testing ST7 applications via ICC
Field updates for Flash memory based ST7 applications using a PC comm port
Hardware implementation for ST7DALI-EVAL
ST7MC three-phase AC induction motor control software library
ST7MC three-phase BLDC motor control software library
System optimization
AN1711
AN1827
AN2009
AN2030
Software techniques for compensating ST7 ADC errors
Implementation of SIGMA-DELTA ADC with ST7FLITE05/09
PWM management for 3-phase BLDC motor drives using the ST7FMC
Back EMF detection during PWM on time by ST7MC
219/226
Package mechanical data
ST7FOXF1, ST7FOXK1, ST7FOXK2
14
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
Figure 94. 20-pin plastic small outline package, 300-mil width, package outline
D
h x 45×
L
A
c
A1
a
e
B
E
H
Table 97. 20-pin plastic small outline package, 300-mil width, mechanical data
mm
Typ
inches(1)
Dim.
Min
Max
Min
Typ
Max
A
A1
B
C
D
E
e
2.35
0.10
0.33
0.23
12.60
7.40
2.65
0.30
0.51
0.32
13.00
7.60
0.0925
0.0039
0.0130
0.0091
0.4961
0.2913
0.1043
0.0118
0.0201
0.0126
0.5118
0.2992
1.27
0.0500
H
h
10.00
0.25
0°
10.65
0.75
8°
0.3937
0.0098
0°
0.4193
0.0295
8°
α
L
0.40
1.27
0.0157
0.0500
Number of Pins
20
N
1. Values in inches are converted from mm and rounded to 4 decimal digits.
220/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
Package mechanical data
Figure 95. 20-pin plastic dual in-line package, 300-mil width, package outline
A2
A1
A
L
c
b
eB
D1
e
b2
D
11
10
20
1
E1
Table 98. 20-pin plastic dual in-line package, 300-mil width, mechanical data
mm
Typ
inches(1)
Dim.
Min
Max
Min
Typ
Max
A
A1
A2
b
5.33
0.2098
0.38
2.92
0.36
1.14
0.20
24.89
0.13
0.0150
0.1150
0.0142
0.0449
0.0079
0.9799
0.0051
3.30
0.46
1.52
0.25
26.16
4.95
0.56
1.78
0.36
26.92
0.1299
0.0181
0.0598
0.0098
1.0299
0.1949
0.0220
0.0701
0.0142
1.0598
b2
c
D
D1
e
2.54
0.1000
eB
E1
L
10.92
7.11
3.81
0.4299
0.2799
0.1500
6.10
2.92
6.35
3.30
0.2402
0.1150
0.2500
0.1299
Number of Pins
20
N
1. Values in inches are converted from mm and rounded to 4 decimal digits.
221/226
Package mechanical data
ST7FOXF1, ST7FOXK1, ST7FOXK2
Figure 96. 32-pin plastic dual in-line package, shrink 400-mil width, package outline
E
eC
A2
A
L
A1
E1
C
eA
eB
b
b2
e
D
Table 99. 32-pin plastic dual in-line package, shrink 400-mil width, mechanical data
mm
inches(1)
Dim.
Min
Typ
Max
Min
Typ
Max
A
A1
A2
b
3.56
0.51
3.05
0.36
0.76
0.20
27.43
9.91
7.62
3.76
5.08
0.1402
0.0201
0.1201
0.0142
0.0299
0.0079
1.0799
0.3902
0.3000
0.1480
0.2000
3.56
0.46
1.02
0.25
4.57
0.58
0.1402
0.0181
0.0402
0.0098
0.1799
0.0228
0.0551
0.0142
1.1201
0.4350
0.3701
b1
C
1.40
0.36
D
28.45
11.05
9.40
E
10.41
8.89
0.4098
0.3500
0.0701
0.4000
E1
e
1.78
eA
eB
eC
L
10.16
12.70
1.40
3.81
0.5000
0.0551
0.1500
2.54
3.05
0.1000
0.1201
Number of pins
32
N
1. Values in inches are converted from mm and rounded to 4 decimal digits.
222/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
Package mechanical data
Figure 97. 32-pin low profile quad flat package (7x7), package outline
D
A
D1
A2
A1
e
b
E
E1
c
L1
L
h
Table 100. 32-pin low profile quad flat package (7x7), package mechanical data
mm
Typ
inches(1)
Dim.
Min
Max
Min
Typ
Max
A
A1
A2
b
1.60
0.15
1.45
0.45
0.20
0.0630
0.0059
0.0571
0.0177
0.0079
0.05
1.35
0.30
0.09
0.0020
0.0531
0.0118
0.0035
1.40
0.37
0.0551
0.0146
C
D
9.00
7.00
9.00
7.00
0.80
3.5°
0.60
1.00
0.3543
0.2756
0.3543
0.2756
0.0315
3.5°
D1
E
E1
e
θ
0°
7°
0°
7°
L
0.45
0.75
0.0177
0.0236
0.0394
0.0295
L1
Number of pins
32
N
1. Values in inches are converted from mm and rounded to 4 decimal digits.
223/226
Package mechanical data
ST7FOXF1, ST7FOXK1, ST7FOXK2
14.1
Thermal characteristics
Table 101. Thermal characteristics
Symbol
Ratings
Value
Unit
LQFP32
SDIP32
SO20
55
58
76
63
Package thermal resistance
(junction to ambient)
RthJA
°C/W
DIP20
Maximum junction
temperature(1)
TJmax
PDmax
150
160
°C
Power dissipation(2)
mW
1. The maximum chip-junction temperature is based on technology characteristics.
2. The maximum power dissipation is obtained from the formula PD = (TJ -TA) / RthJA
.
The power dissipation of an application can be defined by the user with the formula: PD=PINT+PPORT
where PINT is the chip internal power (IDDxVDD) and PPORT is the port power dissipation depending on the
ports used in the application.
224/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
Revision history
15
Revision history
Table 102. Document revision history
Date
Revision
Changes
15-Oct-2007
1
Initial release
Interrupt mapping modified (Table 17 on page 58 and Table 18 on
page 59)
23-Oct-2007
2
Section 12.8: EMC (electromagnetic compatibility) characteristics on
page 201 modified
Added LVD function
Modified Figure 5: ST7FOXF1/ST7FOXK1/ST7FOXK2 memory map
on page 20
Modified reset configuration for ICCCLK pin (Table 2: Device pin
description (32-pin packages) on page 16
Modified Table 3 on page 19 (added AIN5 on pin n°17)
Modified information on eix in Figure 4: 20-pin SO and DIP package
pinout on page 18 and Table 3 on page 19
Added BREAK2 (Table 2: Device pin description (32-pin packages)
on page 16 and Section 10.2: Dual 12-bit autoreload timer on
page 82)
Added PB5 in Table 3 on page 19
Modified note on SPI in Table 4: Hardware register map on page 21
Modified Figure 44.: Block diagram of input capture mode on
page 90
Modified Figure 46.: Long range input capture block diagram on
page 91
23-Nov-2007
3
Modified note 4 in Section 4.4: ICC interface on page 25
Modified Figure 6: Typical ICC Interface on page 26
Modified Figure 52: Lite timer 2 block diagram on page 111
Removed bits 2:0 in LTCSR1 register in : Lite Timer Control/status
register (LTCSR1) on page 115
Modified Figure 12: Clock management block diagram on page 38
Added RCC_CSR in Table 4: Hardware register map on page 21
Added Customized RC calibration section
Modified Section 10.2.3: Functional description on page 84 (32 MHz
references removed from PWM frequency and one pulse mode
paragraphs)
Modified Table 73: On-chip peripheral characteristics on page 193
Modified Section 10.7.1: Introduction on page 173
Modified Section 13.3: Development tools on page 215
Modified Section 13.2: Device ordering information on page 214
Added DIP20 package
Added LVD in Figure 1: General block diagram on page 14
Modified Figure 93: ST7FOXF1/ST7FOXK1/ST7FOXK2 ordering
information scheme on page 214
07-Feb-08
4
Modified Table 95: Development tool order codes on page 216
Modified Table 101: Thermal characteristics on page 224
225/226
ST7FOXF1, ST7FOXK1, ST7FOXK2
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226/226
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