ST7L34F2UCRE/XXX [STMICROELECTRONICS]
8-BIT, MROM, 8MHz, MICROCONTROLLER, QCC20, 5 X 6 MM, LEAD FREE, QFN-20;
| 型号： | ST7L34F2UCRE/XXX |
| 厂家： | 
ST |
| 描述： | 8-BIT, MROM, 8MHz, MICROCONTROLLER, QCC20, 5 X 6 MM, LEAD FREE, QFN-20 |
| 文件： | 总168页 (文件大小：2615K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ST7L34, ST7L35, ST7L38, ST7L39
8-bit MCU for automotive with single voltage Flash/ROM,
data EEPROM, ADC, timers, SPI, LINSCI™
Features
■ Memories
– 8 Kbytes program memory: Single voltage ex-
tended Flash (XFlash) or ROM with readout
protection capability. In-Application program-
ming and In-Circuit Programming for XFlash
devices
SO20
300mil
QFN20
– 384 bytes RAM
– 256 bytes data EEPROM (XFlash and ROM
devices) with readout protection, 300K write/
erase cycles guaranteed
– XFlash and EEPROM data retention 20 years
at 55°C
■ 2 Communication Interfaces
– Master/slave LINSCI™ asynchronous serial
interface
– SPI synchronous serial interface
■ Clock, Reset and Supply Management
■ Interrupt Management
– Enhanced reset system
– 10 interrupt vectors plus TRAP and RESET
– 12 external interrupt lines (on 4 vectors)
– Enhanced low voltage supervisor (LVD) for
main supply and an auxiliary voltage detector
(AVD) with interrupt capability for implement-
ing safe power-down procedures
– Clock sources: High precision internal RC os-
cillator, crystal/ceramic resonator or external
clock
■ A/D Converter
– 7 input channels
– 10-bit resolution
■ Instruction Set
– Optional x8 PLL for 8 MHz internal clock
– 8-bit data manipulation
– 5 power saving modes: Halt, Active Halt, Wait
and Slow, Auto Wake Up From Halt
– 63 basic instructions with illegal opcode
detection
– 17 main addressing modes
■ I/O Ports
– 8 x 8 unsigned multiply instructions
– Up to 15 multifunctional bidirectional I/O lines
– 7 high sink outputs
■ Development Tools
– Full hardware/software development package
– DM (Debug module)
■ 5 Timers
– Configurable Watchdog Timer
– Two 8-bit Lite Timers with prescaler, 1 real-
time base and 1 input capture
– Two 12-bit Autoreload Timers with 4 PWM
outputs, input capture and output compare
functions
Rev. 5
December 2006
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1
Table of Contents
1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1 DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2 PARAMETRIC DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.3 DEBUG MODULE (DM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3 REGISTER AND MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.3 PROGRAMMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.4 ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.5 MEMORY PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.6 RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.7 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5 DATA EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.3 MEMORY ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.4 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.5 ACCESS ERROR HANDLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.6 DATA EEPROM READOUT PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.7 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.1 INTERNAL RC OSCILLATOR ADJUSTMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.2 PHASE LOCKED LOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.3 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.4 MULTI-OSCILLATOR (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.5 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.6 SYSTEM INTEGRITY MANAGEMENT (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
8 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
8.1 NON-MASKABLE SOFTWARE INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
8.2 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
8.3 PERIPHERAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
9 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
9.2 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
9.3 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
9.4 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
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9.5 ACTIVE HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
9.6 AUTO WAKE UP FROM HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
10 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
10.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
10.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
10.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
10.4 UNUSED I/O PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
10.5 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
10.6 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
11 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
11.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
11.2 DUAL 12-BIT AUTORELOAD TIMER 3 (AT3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
11.3 LITE TIMER 2 (LT2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
11.4 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
11.5 LINSCI SERIAL COMMUNICATION INTERFACE (LIN MASTER/SLAVE) . . . . . . . . . . 86
11.6 10-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
12 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
12.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
12.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
13 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
13.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
13.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
13.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
13.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
13.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
13.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
13.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
13.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
13.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
13.10 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 147
13.11 10-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
14 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
14.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
14.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
14.3 SOLDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
15 DEVICE CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
15.1 OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
15.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . 157
15.3 FLASH DEVICE ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
15.4 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
16 IMPORTANT NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
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Table of Contents
16.1 CLEARING ACTIVE INTERRUPTS OUTSIDE INTERRUPT ROUTINE . . . . . . . . . . . . 163
16.2 LINSCI LIMITATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
17 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
To obtain the most recent version of this datasheet,
please check at www.st.com>products>technical literature>datasheet
Please also pay special attention to the Section “IMPORTANT NOTES” on page 163.
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ST7L34, ST7L35, ST7L38, ST7L39
1 INTRODUCTION
1.1 DESCRIPTION
The ST7L3x is a member of the ST7 microcontrol-
ler family suitable for automotive applications. All
ST7 devices are based on a common industry-
standard 8-bit core, featuring an enhanced instruc-
tion set.
signed multiplication and indirect addressing
modes.
1.2 PARAMETRIC DATA
For easy reference, all parametric data is located
in section 13 on page 127.
The ST7L3x features Flash memory with byte-by-
byte In-Circuit Programming (ICP) and In-Applica-
tion Programming (IAP) capability.
1.3 DEBUG MODULE (DM)
Under software control, the ST7L3x devices can
be placed in WAIT, SLOW or HALT mode, reduc-
ing power consumption when the application is in
idle or standby state.
The devices feature an on-chip Debug Module
(DM) to support in-circuit debugging (ICD). For a
description of the DM registers, refer to the ST7
ICC Protocol Reference Manual.
The enhanced instruction set and addressing
modes of the ST7 offer both power and flexibility to
software developers, enabling the design of highly
efficient and compact application code. In addition
to standard 8-bit data management, all ST7 micro-
controllers feature true bit manipulation, 8x8 un-
Table 1. Device Summary
Feature
Program Memory
RAM (stack)
ST7L34
ST7L35
ST7L38
ST7L39
8 Kbytes
384 bytes (128 bytes)
Data EEPROM
-
256 bytes
Lite Timer, Autoreload
Timer, SPI, 10-bit
ADC, LINSCI
Lite Timer, Autoreload
Timer, SPI, 10-bit
ADC, LINSCI
Lite Timer, Autoreload
Timer, SPI, 10-bit ADC
Lite Timer, Autoreload
Timer, SPI, 10-bit ADC
Peripherals
Operating Supply
CPU Frequency
Operating Temperature
Packages
3.0V to 5.5V
Up to 8 MHz (with external resonator/clock or internal RC oscillator)
Up to -40 to 85°C / -40 to 125°C
SO20 300mil, QFN20
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ST7L34, ST7L35, ST7L38, ST7L39
Figure 1. General Block Diagram
Int.
1% RC
1MHz
12-bit
AUTORELOAD
TIMER 3
PLL x 8
CLKIN
8-bit
LITE TIMER 2
/ 2
OSC1
OSC2
Ext.
OSC
Internal
CLOCK
PA7:0
(8 bits)
PB6:0
(7 bits)
1MHz
to
PORT A
PORT B
16 MHz
LVD
V
POWER
SUPPLY
ADC
DD
V
SS
DEBUG MODULE
SPI
RESET
CONTROL
8-bit CORE
ALU
LINSCI
WDG
PROGRAM
MEMORY
(8 Kbytes)
RAM
(384 bytes)
DATA EEPROM
(256 bytes)
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ST7L34, ST7L35, ST7L38, ST7L39
2 PIN DESCRIPTION
Figure 2. 20-Pin SO Package Pinout
V
OSC1/CLKIN
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
SS
V
OSC2
DD
RESET
PA0 (HS)/LTIC
SS/AIN0/PB0
PA1 (HS)/ATIC
ei3
ei2
PA2 (HS)/ATPWM0
PA3 (HS)/ATPWM1
PA4 (HS)/ATPWM2
PA5 (HS)/ATPWM3/ICCDATA
PA6/MCO/ICCCLK/BREAK
PA7 (HS)/TDO
SCK/AIN1/PB1
MISO/AIN2/PB2
MOSI/AIN3/PB3
CLKIN/AIN4/PB4
AIN5/PB5
ei0
ei1 13
12
ei2
11
RDI/AIN6/PB6
(HS) 20mA high sink capability
eix associated external interrupt vector
Figure 3. 20-Pin QFN Package Pinout
VDD
20
OSC1/CLKIN
18
19
17
VSS
OSC2
16
15
14
RESET
SS/AIN0/PB0
SCK/AIN1/PB1
PA0 (HS)/LTIC
1
2
PA1 (HS)/ATIC
ei0
3
PA2 (HS)/ATPWM0
PA3 (HS)/ATPWM1
PA4 (HS)/ATPWM2
ei3
ei2
MISO/AIN2/PB2
MOSI/AIN3/PB3
13
12
4
5
6
ei1
11 PA5 (HS)/ATPWM3/ICCDATA
ei2
CLKIN/AIN4/PB4
RDI/AIN6/PB6
8
7
9
10
PA6/MCO/ICCCLK/BREAK
AIN5/PB5
PA7(HS)/TDO
(HS) 20mA high sink capability
eix associated external interrupt vector
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ST7L34, ST7L35, ST7L38, ST7L39
PIN DESCRIPTION (cont’d)
Legend / Abbreviations for Table 2:
Type:
I = input, O = output, S = supply
In/Output level: C CMOS 0.3V /0.7V with input trigger
T =
DD
DD
Output level:
HS = 20mA high sink (on N-buffer only)
Port and control configuration:
– Input:
float = floating, wpu = weak pull-up, int = interrupt, ana = analog
OD = open drain, PP = push-pull
– Output:
The RESET configuration of each pin is shown in bold which is valid as long as the device is in reset state.
Table 2. Device Pin Description
Pin No.
Level
Port / Control
Main
Function
(after
Input
Output
Pin Name
Alternate Function
reset)
1
2
3
19
20
1
V
V
S
S
Ground
SS
DD
Main power supply
RESET
I/O C
I/O
X
X
X
Top priority non-maskable interrupt (active low)
T
ADC Analog Input 0 or SPI Slave Se-
lect (active low)
4
5
6
7
8
2
3
4
5
6
PB0/AIN0/SS
C
C
C
C
C
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Port B0
T
T
T
T
T
ei3
ADC Analog Input 1 or SPI Serial
Clock
PB1/AIN1/SCK I/O
PB2/AIN2/MISO I/O
PB3/AIN3/MOSI I/O
X
X
X
X
Port B1
ADC Analog Input 2 or SPI Master In/
Slave Out Data
Port B2
ADC Analog Input 3 or SPI Master
Port B3
ei2
X
Out / Slave In Data
PB4/AIN4/
I/O
ADC Analog Input 4 or External clock
input
Port B4
CLKIN
9
7
8
9
PB5/AIN5
I/O
I/O
C
C
X
X
X
X
X
X
X
X
X
X
X
Port B5 ADC Analog Input 5
T
T
ei2
X
10
11
PB6/AIN6/RDI
PA7/TDO
Port B6 ADC Analog Input 6 or LINSCI Input
Port A7 LINSCI Output
I/O C HS
T
Main Clock Output or In-Circuit Com-
munication Clock or External BREAK
Caution: During normal operation
this pin must be pulled- up, internally
or externally (external pull-up of 10k
mandatory in noisy environment).
This is to avoid entering ICC mode
unexpectedly during a reset. In the
application, even if the pin is config-
ured as output, any reset will put it
back in input pull-up.
PA6 /MCO/
ICCCLK/BREAK
12 10
I/O
C
X
X
X
Port A6
T
ei1
PA5 /ATPWM3/
ICCDATA
Autoreload Timer PWM3 or In-Circuit
Communication Data
13 11
I/O C HS
X
X
X
X
X
X
Port A5
T
14 12 PA4/ATPWM2 I/O C HS
Port A4 Autoreload Timer PWM2
T
8/168
1
ST7L34, ST7L35, ST7L38, ST7L39
Pin No.
Level
Port / Control
Main
Function
Input
Output
Pin Name
Alternate Function
(after
reset)
15 13 PA3/ATPWM1 I/O C HS
X
X
X
X
X
X
X
X
X
X
X
X
Port A3 Autoreload Timer PWM1
Port A2 Autoreload Timer PWM0
Port A1 Autoreload Timer Input Capture
Port A0 Lite Timer Input Capture
Resonator oscillator inverter output
T
16 14 PA2/ATPWM0 I/O C HS
ei0
X
T
17 15 PA1/ATIC
18 16 PA0/LTIC
19 17 OSC2
I/O C HS
T
I/O C HS
T
O
I
Resonator oscillator inverter input or External
clock input
20 18 OSC1/CLKIN
Note:
For input with interrupt possibility “ei ” defines the associated external interrupt vector which can be assigned to one of
x
the I/O pins using the EISR register. Each interrupt can be either weak pull-up or floating defined through option register
OR.
9/168
1
ST7L34, ST7L35, ST7L38, ST7L39
3 REGISTER AND MEMORY MAP
As shown in Figure 4, the MCU is capable of ad-
dressing 64 Kbytes of memories and I/O registers.
The Flash memory contains two sectors (see Fig-
ure 4) mapped in the upper part of the ST7 ad-
dressing space so the reset and interrupt vectors
are located in Sector 0 (F000h-FFFFh).
The available memory locations consist of 128
bytes of register locations, 384 bytes of RAM, 256
bytes of data EEPROM and 8 Kbytes of user pro-
gram memory. The RAM space includes up to 128
bytes for the stack from 180h to 1FFh.
The size of Flash Sector 0 and other device op-
tions are configurable by Option byte.
IMPORTANT: Memory locations marked as “Re-
served” must never be accessed. Accessing a re-
served area can have unpredictable effects on the
device.
The highest address bytes contain the user reset
and interrupt vectors.
Figure 4. Memory Map
0080h
Short Addressing
RAM (zero page)
00FFh
0100h
0000h
HW Registers
(see Table 3)
16-bit Addressing
RAM
007Fh
0080h
017Fh
0180h
RAM
(384 bytes)
01FFh
0200h
128 bytes Stack
01FFh
Reserved
0FFFh
1000h
DEE0h
RCCRH0
Data EEPROM
(256 bytes)
DEE1h
RCCRL0
DEE2h
10FFh
1100h
RCCRH1
DEE3h
RCCRL1
DEE4h
Reserved
8K FLASH
PROGRAM MEMORY
See section 7.1 on page 24
DFFFh
E000h
and note 1.
E000h
7 Kbytes
SECTOR 1
FBFFh
FC00h
Flash Memory
(8K)
1 Kbyte
SECTOR 0
FFFFh
FFDFh
FFE0h
Interrupt & Reset Vectors
(see Table 6)
FFFFh
Notes:
1. DEE0h, DEE1h, DEE2h and DEE3h addresses are located in a reserved area but are special bytes containing also
the RC calibration values which are read-accessible only in user mode. If all the EEPROM data or Flash space (including
the RC calibration values locations) has been erased (after the readout protection removal), then the RC calibration val-
ues can still be obtained through these four addresses.
10/168
1
ST7L34, ST7L35, ST7L38, ST7L39
Table 3. Hardware Register Map
Register
Address
Block
Register Name
Port A Data Register
Port A Data Direction Register
Port A Option Register
Reset Status
Remarks
R/W
R/W
R/W
Label
1)
0000h
0001h
0002h
PADR
PADDR
PAOR
FFh
Port A
00h
40h
1)
0003h
0004h
0005h
PBDR
PBDDR
PBOR
Port B Data Register
Port B Data Direction Register
Port B Option Register
FFh
R/W
R/W
R/W
Port B
00h
00h
2)
0006h
0007h
Reserved area (2 bytes)
0008h
0009h
000Ah
000Bh
000Ch
LTCSR2
LTARR
LTCNTR
LTCSR1
LTICR
Lite Timer Control/Status Register 2
Lite Timer Autoreload Register
Lite Timer Counter 2 Register
Lite Timer Control/Status Register 1
Lite Timer Input Capture Register
0Fh
00h
00h
R/W
R/W
Read Only
R/W
LITE
TIMER 2
0x00 0000b
xxh
Read Only
000Dh
000Eh
000Fh
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
0019h
001Ah
001Bh
001Ch
001Dh
001Eh
001Fh
0020h
0021h
0022h
0023h
0024h
0025h
ATCSR
CNTR1H
CNTR1L
ATR1H
ATR1L
Timer Control/Status Register
Counter Register 1 High
Counter Register 1 Low
Autoreload Register 1 High
Autoreload Register 1 Low
PWM Output Control Register
0x00 0000b
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
03h
00h
00h
00h
00h
R/W
Read Only
Read Only
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PWMCR
PWM0CSR PWM 0 Control/Status Register
PWM1CSR PWM 1 Control/Status Register
PWM2CSR PWM 2 Control/Status Register
PWM3CSR PWM 3 Control/Status Register
DCR0H
DCR0L
PWM 0 Duty Cycle Register High
PWM 0 Duty Cycle Register Low
PWM 1 Duty Cycle Register High
PWM 1 Duty Cycle Register Low
PWM 2 Duty Cycle Register High
PWM 2 Duty Cycle Register Low
PWM 3 Duty Cycle Register High
PWM 3 Duty Cycle Register Low
Input Capture Register High
Input Capture Register Low
Timer Control/Status Register 2
Break Control Register
Autoreload Register 2 High
Autoreload Register 2 Low
Dead Time Generator Register
AUTO-
RELOAD DCR1H
TIMER 3 DCR1L
DCR2H
DCR2L
DCR3H
DCR3L
ATICRH
Read Only
Read Only
R/W
R/W
R/W
ATICRL
ATCSR2
BREAKCR
ATR2H
ATR2L
DTGR
R/W
R/W
0026h to
002Dh
Reserved area (8 bytes)
002Eh
WDG
WDGCR
FCSR
Watchdog Control Register
7Fh
00h
00h
R/W
R/W
R/W
0002Fh
FLASH
Flash Control/Status Register
Data EEPROM Control/Status Register
00030h EEPROM EECSR
11/168
1
ST7L34, ST7L35, ST7L38, ST7L39
Register
Label
Address
Block
Register Name
SPI Data I/O Register
SPI Control Register
SPI Control/Status Register
Reset Status
Remarks
R/W
R/W
R/W
0031h
0032h
0033h
SPIDR
SPICR
SPICSR
xxh
0xh
00h
SPI
0034h
0035h
0036h
ADCCSR
ADCDRH
ADCDRL
A/D Control/Status Register
A/D Data Register High
A/D control and Data Register Low
00h
xxh
x0h
R/W
Read Only
R/W
ADC
0037h
0038h
ITC
EICR
External Interrupt Control Register
Main Clock Control/Status Register
00h
00h
R/W
R/W
MCC
MCCSR
0039h
003Ah
Clock and RCCR
RC Oscillator Control Register
System Integrity Control/Status Register
FFh
0110 0xx0b
R/W
R/W
Reset
SICSR
003Bh
003Ch
Reserved area (1 byte)
ITC
EISR
External Interrupt Selection Register
00h
R/W
003Dh to
003Fh
Reserved area (3 bytes)
0040h
0041h
0042h
0043h
0044h
0045h
0046h
0047h
SCISR
SCIDR
SCI Status Register
SCI Data Register
SCI Baud Rate Register
SCI Control Register 1
SCI Control Register 2
SCI Control Register 3
SCI Extended Receive Prescaler Register
SCI Extended Transmit Prescaler Register
C0h
xxh
00xx xxxxb
xxh
Read Only
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SCIBRR
SCICR1
SCICR2
SCICR3
SCIERPR
SCIETPR
LINSCI
(LIN Mas-
ter/Slave)
00h
00h
00h
00h
0048h
Reserved area (1 byte)
0049h
004Ah
AWUPR
AWUCSR
AWU Prescaler Register
AWU Control/Status Register
FFh
00h
R/W
R/W
AWU
004Bh
004Ch
004Dh
004Eh
004Fh
0050h
DMCR
DMSR
DMBK1H
DMBK1L
DMBK2H
DMBK2L
DM Control Register
DM Status Register
DM Breakpoint Register 1 High
DM Breakpoint Register 1 Low
DM Breakpoint Register 2 High
DM Breakpoint Register 2 Low
00h
00h
00h
00h
00h
00h
R/W
R/W
R/W
R/W
R/W
R/W
3)
DM
0051h to
007Fh
Reserved area (47 bytes)
Legend: x = undefined, R/W = read/write
Notes:
1. The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of
the I/O pins are returned instead of the DR register contents.
2. The bits associated with unavailable pins must always keep their reset value.
3. For a description of the DM registers, see the ST7 ICC Protocol Reference Manual.
12/168
1
ST7L34, ST7L35, ST7L38, ST7L39
4.3.1 In-Circuit Programming (ICP)
4 FLASH PROGRAM MEMORY
ICP uses a protocol called ICC (In-Circuit Commu-
nication) which allows an ST7 plugged on a print-
ed circuit board (PCB) to communicate with an ex-
ternal programming device connected via cable.
ICP is performed in three steps:
4.1 INTRODUCTION
The ST7 single voltage extended Flash (XFlash) is
a non-volatile memory that can be electrically
erased and programmed either on a byte-by-byte
basis or up to 32 bytes in parallel.
Switch the ST7 to ICC mode (In-Circuit Communi-
cations). This is done by driving a specific signal
sequence on the ICCCLK/DATA pins while the
RESET pin is pulled low. When the ST7 enters
ICC mode, it fetches a specific RESET vector
which points to the ST7 System Memory contain-
ing the ICC protocol routine. This routine enables
the ST7 to receive bytes from the ICC interface.
The XFlash devices can be programmed off-board
(plugged in a programming tool) or on-board using
In-Circuit Programming or In-Application Program-
ming.
The array matrix organization allows each sector
to be erased and reprogrammed without affecting
other sectors.
– Download ICP Driver code in RAM from the
ICCDATA pin
4.2 MAIN FEATURES
– Execute ICP Driver code in RAM to program
the Flash memory
■ ICP (In-Circuit Programming)
■ IAP (In-Application Programming)
Depending on the ICP Driver code downloaded in
RAM, Flash memory programming can be fully
customized (number of bytes to program, program
locations, or selection of the serial communication
interface for downloading).
■ ICT (In-Circuit Testing) for downloading and
executing user application test patterns in RAM
■ Sector 0 size configurable by option byte
■ Readout and write protection
4.3.2 In-Application Programming (IAP)
This mode uses an IAP Driver program previously
programmed in Sector 0 by the user (in ICP
mode).
4.3 PROGRAMMING MODES
The ST7 can be programmed in three different
ways:
This mode is fully controlled by user software, al-
lowing it to be adapted to the user application
(such as user-defined strategy for entering pro-
gramming mode, choice of communications proto-
col used to fetch the data to be stored).
– Insertion in a programming tool. In this mode,
Flash sectors 0 and 1, option byte row and
data EEPROM (if present) can be pro-
grammed or erased.
– In-Circuit Programming. In this mode, Flash
sectors 0 and 1, option byte row and data
EEPROM (if present) can be programmed or
erased without removing the device from the
application board.
IAP mode can be used to program any memory ar-
eas except Sector 0, which is write/erase protect-
ed to allow recovery in case errors occur during
the programming operation.
– In-Application Programming. In this mode,
sector 1 and data EEPROM (if present) can
be programmed or erased without removing
the device from the application board and
while the application is running.
13/168
1
ST7L34, ST7L35, ST7L38, ST7L39
FLASH PROGRAM MEMORY (cont’d)
4.4 ICC INTERFACE
ICP needs a minimum of four and up to six pins to
be connected to the programming tool. These pins
are:
– ICCCLK: ICC output serial clock pin
– ICCDATA: ICC input serial data pin
– CLKIN/PB4: main clock input for external
source
– RESET: device reset
– V : application board power supply (option-
– V : device power supply ground
DD
SS
al, see Note 3)
Figure 5. Typical ICC Interface
PROGRAMMING TOOL
ICC CONNECTOR
ICC Cable
ICC CONNECTOR
HE10 CONNECTOR TYPE
(See Note 3)
APPLICATION BOARD
9
7
5
6
3
1
2
OPTIONAL
(See Note 4)
10
8
4
APPLICATION
RESET SOURCE
See Note 2
APPLICATION
POWER SUPPLY
See Note 1 and caution
See Note 1
APPLICATION
I/O
ST7
Notes:
on the Programming Tool architecture. This pin
must be connected when using most ST Program-
ming Tools (it is used to monitor the application
power supply). Please refer to the Programming
Tool Manual.
4. Pin 9 must be connected to the PB4 pin of the
ST7 when the clock is not available in the applica-
tion or if the selected clock option is not pro-
grammed in the option byte. ST7 devices with
multi-oscillator capability must have OSC2
grounded in this case.
5. With any programming tool, while the ICP option
is disabled, the external clock must be provided on
PB4.
6. In ICC mode, the internal RC oscillator is forced
as a clock source, regardless of the selection in the
option byte.
Caution: During normal operation ICCCLK pin
must be pulled- up, internally or externally (exter-
nal pull-up of 10k mandatory in noisy environ-
ment). This avoids entering ICC mode
unexpectedly during a reset. In the application,
even if the pin is configured as output, any reset
puts it back in input pull-up.
1. If the ICCCLK or ICCDATA pins are only used
as outputs in the application, no signal isolation is
necessary. As soon as the Programming Tool is
plugged to the board, even if an ICC session is not
in progress, the ICCCLK and ICCDATA pins are
not available for the application. If they are used as
inputs by the application, isolation such as a serial
resistor has to be implemented if another device
forces the signal. Refer to the Programming Tool
documentation for recommended resistor values.
2. During the ICP session, the programming tool
must control the RESET pin. This can lead to con-
flicts between the programming tool and the appli-
cation reset circuit if it drives more than 5mA at
high level (push pull output or pull-up resistor<1K).
A schottky diode can be used to isolate the appli-
cation RESET circuit in this case. When using a
classical RC network with R>1K or a reset man-
agement IC with open drain output and pull-up
resistor > 1K, no additional components are need-
ed. In all cases the user must ensure that no exter-
nal reset is generated by the application during the
ICC session.
3. The use of Pin 7 of the ICC connector depends
14/168
1
ST7L34, ST7L35, ST7L38, ST7L39
4.5 MEMORY PROTECTION
4.6 RELATED DOCUMENTATION
There are two different types of memory protec-
tion: Readout Protection and Write/Erase Protec-
tion which can be applied individually.
For details on Flash programming and ICC proto-
col, refer to the ST7 Flash Programming Refer-
ence Manual and to the ST7 ICC Protocol Refer-
ence Manual.
4.5.1 Readout Protection
Readout protection, when selected provides a pro-
tection against program memory content extrac-
tion and against write access to Flash memory.
Even if no protection can be considered as totally
unbreakable, the feature provides a very high level
of protection for a general purpose microcontroller.
4.7 REGISTER DESCRIPTION
FLASH CONTROL/STATUS REGISTER (FCSR)
Read/Write
Reset Value: 000 0000 (00h)
1st RASS Key: 0101 0110 (56h)
2nd RASS Key: 1010 1110 (AEh)
2
Both program and data E memory are protected.
In Flash devices, this protection is removed by re-
programming the option. In this case, both pro-
7
0
0
2
gram and data E memory are automatically
erased and the device can be reprogrammed.
0
0
0
0
OPT LAT PGM
– Readout protection selection is enabled and re-
moved through the FMP_R bit in the option byte.
Note: This register is reserved for programming
using ICP, IAP or other programming methods. It
controls the XFlash programming and erasing op-
erations.
4.5.2 Flash Write/Erase Protection
Write/erase protection, when set, makes it impos-
sible to both overwrite and erase program memo-
2
ry. It does not apply to E data. Its purpose is to
When an EPB or another programming tool is
used (in socket or ICP mode), the RASS keys are
sent automatically.
provide advanced security to applications and pre-
vent any change being made to the memory con-
tent.
Warning: Once set, Write/erase protection can
never be removed. A write-protected Flash device
is no longer reprogrammable.
Write/erase protection is enabled through the
FMP_W bit in the option byte.
15/168
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ST7L34, ST7L35, ST7L38, ST7L39
5 DATA EEPROM
5.1 INTRODUCTION
5.2 MAIN FEATURES
The Electrically Erasable Programmable Read
Only Memory can be used as a non-volatile back-
up for storing data. Using the EEPROM requires a
basic access protocol described in this chapter.
■ Up to 32 bytes programmed in the same cycle
■ EEPROM mono-voltage (charge pump)
■ Chained erase and programming cycles
■ Internal control of the global programming cycle
duration
■ WAIT mode management
■ Readout protection
Figure 6. EEPROM Block Diagram
HIGH VOLTAGE
PUMP
EECSR
0
0
0
0
0
0
E2LAT E2PGM
EEPROM
ROW
ADDRESS
DECODER
4
MEMORY MATRIX
(1 ROW = 32 x 8 BITS)
DECODER
128
128
DATA
MULTIPLEXER
32 x 8 BITS
4
4
DATA LATCHES
ADDRESS BUS
DATA BUS
16/168
1
ST7L34, ST7L35, ST7L38, ST7L39
DATA EEPROM (cont’d)
5.3 MEMORY ACCESS
the value is latched inside the 32 data latches ac-
cording to its address.
The data EEPROM memory read/write access
modes are controlled by the E2LAT bit of the EEP-
ROM Control/Status register (EECSR). The flow-
chart in Figure 7 describes these different memory
access modes.
When PGM bit is set by the software, all the previ-
ous bytes written in the data latches (up to 32) are
programmed in the EEPROM cells. The effective
high address (row) is determined by the last EEP-
ROM write sequence. To avoid wrong program-
ming, the user must take care that all the bytes
written between two programming sequences
have the same high address: Only the 5 Least Sig-
nificant Bits of the address can change.
Read Operation (E2LAT = 0)
The EEPROM can be read as a normal ROM loca-
tion when the E2LAT bit of the EECSR register is
cleared.
At the end of the programming cycle, the PGM and
LAT bits are cleared simultaneously.
On this device, data EEPROM can also be used to
execute machine code. Take care not to write to
the data EEPROM while executing from it. This
would result in an unexpected code being execut-
ed.
Note: Care should be taken during the program-
ming cycle. Writing to the same memory location
will over-program the memory (logical AND be-
tween the two write access data results) because
the data latches are only cleared at the end of the
programming cycle and by the falling edge of the
E2LAT bit.
Write Operation (E2LAT = 1)
To access the write mode, the E2LAT bit has to be
set by software (the E2PGM bit remains cleared).
When a write access to the EEPROM area occurs,
It is not possible to read the latched data.
This note is illustrated by the Figure 9.
Figure 7. Data EEPROM Programming Flowchart
READ MODE
E2LAT = 0
WRITE MODE
E2LAT = 1
E2PGM = 0
E2PGM = 0
WRITE UP TO 32 BYTES
IN EEPROM AREA
(with the same 11 MSB of the address)
READ BYTES
IN EEPROM AREA
START PROGRAMMING CYCLE
E2LAT = 1
E2PGM = 1 (set by software)
0
1
E2LAT
CLEARED BY HARDWARE
17/168
1
ST7L34, ST7L35, ST7L38, ST7L39
DATA EEPROM (cont’d)
2
Figure 8. Data E PROM Write Operation
⇓ Row / Byte ⇒
0
1
2
3
...
30 31
Physical Address
00h...1Fh
0
1
ROW
DEFINITION
20h...3Fh
...
N
Nx20h...Nx20h+1Fh
Read operation impossible
Read operation possible
Programming cycle
PHASE 2
Byte 1 Byte 2
PHASE 1
Byte 32
Writing data latches
Waiting E2PGM and E2LAT to fall
E2LAT bit
Set by USER application
Cleared by hardware
E2PGM bit
Note: If a programming cycle is interrupted (by a RESET action), the integrity of the data in memory is not
guaranteed.
18/168
1
ST7L34, ST7L35, ST7L38, ST7L39
DATA EEPROM (cont’d)
5.4 POWER SAVING MODES
Wait mode
5.5 ACCESS ERROR HANDLING
If a read access occurs while E2LAT = 1, then the
data bus will not be driven.
The data EEPROM can enter WAIT mode on exe-
cution of the WFI instruction of the microcontroller
or when the microcontroller enters ACTIVE HALT
mode.The data EEPROM will immediately enter
this mode if there is no programming in progress,
otherwise the data EEPROM will finish the cycle
and then enter WAIT mode.
If a write access occurs while E2LAT = 0, then the
data on the bus will not be latched.
If a programming cycle is interrupted (by RESET
action), the integrity of the data in memory is not
guaranteed.
5.6 DATA EEPROM READOUT PROTECTION
Active Halt mode
The readout protection is enabled through an op-
tion bit (see section 15.1 on page 154).
Refer to Wait mode.
When this option is selected, the programs and
data stored in the EEPROM memory are protected
against readout (including a rewrite protection). In
Flash devices, when this protection is removed by
reprogramming the Option Byte, the entire Pro-
gram memory and EEPROM is first automatically
erased.
Halt mode
The data EEPROM immediately enters HALT
mode if the microcontroller executes the HALT in-
struction. Therefore the EEPROM will stop the
function in progress and data may be corrupted.
Note: Both Program Memory and data EEPROM
are protected using the same option bit.
Figure 9. Data EEPROM Programming Cycle
READ OPERATION NOT POSSIBLE
READ OPERATION POSSIBLE
INTERNAL
PROGRAMMING
VOLTAGE
ERASE CYCLE
WRITE CYCLE
WRITE OF
DATA LATCHES
tPROG
LAT
PGM
19/168
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ST7L34, ST7L35, ST7L38, ST7L39
DATA EEPROM (cont’d)
5.7 REGISTER DESCRIPTION
EEPROM CONTROL/STATUS REGISTER
(EECSR)
Read/Write
Reset Value: 0000 0000 (00h)
7
0
0
0
0
0
0
0
E2LAT E2PGM
Bits 7:2 = Reserved. Forced by hardware to 0.
Bit 1 = E2LAT Latch Access Transfer
This bit is set by software. It is cleared by hard-
ware at the end of the programming cycle. It can
only be cleared by software if the E2PGM bit is
cleared.
0: Read mode
1: Write mode
Bit 0 = E2PGM Programming control and status
This bit is set by software to begin the programming
cycle. At the end of the programming cycle, this bit
is cleared by hardware.
0: Programming finished or not yet started
1: Programming cycle is in progress
Note: If the E2PGM bit is cleared during the pro-
gramming cycle, the memory data is not guaran-
teed.
Table 4. Data EEPROM Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
EECSR
Reset Value
E2LAT
0
E2PGM
0
0030h
0
0
0
0
0
0
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ST7L34, ST7L35, ST7L38, ST7L39
6 CENTRAL PROCESSING UNIT
6.1 INTRODUCTION
Accumulator (A)
The Accumulator is an 8-bit general purpose reg-
ister used to hold operands and the results of the
arithmetic and logic calculations and to manipulate
data.
This CPU has a full 8-bit architecture and contains
six internal registers allowing efficient 8-bit data
manipulation.
Index Registers (X and Y)
6.2 MAIN FEATURES
In indexed addressing modes, these 8-bit registers
are used to create either effective addresses or
temporary storage areas for data manipulation.
(The Cross-Assembler generates a precede in-
struction (PRE) to indicate that the following in-
struction refers to the Y register.)
■ 63 basic instructions
■ Fast 8-bit by 8-bit multiply
■ 17 main addressing modes
■ Two 8-bit index registers
■ 16-bit stack pointer
■ Low power modes
■ Maskable hardware interrupts
■ Non-maskable software interrupt
The Y register is not affected by the interrupt auto-
matic procedures (not pushed to and popped from
the stack).
Program Counter (PC)
The program counter is a 16-bit register containing
the address of the next instruction to be executed
by the CPU. It is made of two 8-bit registers PCL
(Program Counter Low which is the LSB) and PCH
(Program Counter High which is the MSB).
6.3 CPU REGISTERS
The six CPU registers shown in Figure 10 are not
present in the memory mapping and are accessed
by specific instructions.
Figure 10. CPU Registers
7
0
ACCUMULATOR
RESET VALUE = XXh
7
0
0
X INDEX REGISTER
Y INDEX REGISTER
RESET VALUE = XXh
7
RESET VALUE = XXh
PCL
PCH
7
8
15
0
PROGRAM COUNTER
RESET VALUE = RESET VECTOR @ FFFEh-FFFFh
7
1
0
H I N Z C
X 1 X X X
1
1
1
1
CONDITION CODE REGISTER
RESET VALUE =
8
1
15
7
0
STACK POINTER
RESET VALUE = STACK HIGHER ADDRESS
X = Undefined Value
21/168
1
ST7L34, ST7L35, ST7L38, ST7L39
CPU REGISTERS (cont’d)
CONDITION CODE REGISTER (CC)
Read/Write
because the I bit is set by hardware at the start of
the routine and reset by the IRET instruction at the
end of the routine. If the I bit is cleared by software
in the interrupt routine, pending interrupts are
serviced regardless of the priority level of the cur-
rent interrupt routine.
Reset Value: 111x1xxx
7
0
1
1
1
H
I
N
Z
C
Bit 2 = N Negative
The 8-bit Condition Code register contains the in-
terrupt mask and four flags representative of the
result of the instruction just executed. This register
can also be handled by the PUSH and POP in-
structions.
This bit is set and cleared by hardware. It is repre-
sentative of the result sign of the last arithmetic,
logical or data manipulation. It is a copy of the 7
bit of the result.
0: The result of the last operation is positive or null.
1: The result of the last operation is negative
(that is, the most significant bit is a logic 1).
th
These bits can be individually tested and/or con-
trolled by specific instructions.
This bit is accessed by the JRMI and JRPL instruc-
tions.
Bit 4 = H Half carry
This bit is set by hardware when a carry occurs be-
tween bits 3 and 4 of the ALU during an ADD or
ADC instruction. It is reset by hardware during the
same instructions.
Bit 1 = Z Zero
This bit is set and cleared by hardware. This bit in-
dicates that the result of the last arithmetic, logical
or data manipulation is zero.
0: The result of the last operation is different from
zero.
1: The result of the last operation is zero.
0: No half carry has occurred.
1: A half carry has occurred.
This bit is tested using the JRH or JRNH instruc-
tion. The H bit is useful in BCD arithmetic subrou-
tines.
This bit is accessed by the JREQ and JRNE test
instructions.
Bit 3 = I Interrupt mask
This bit is set by hardware when entering in inter-
rupt or by software to disable all interrupts except
the TRAP software interrupt. This bit is cleared by
software.
Bit 0 = C Carry/borrow
This bit is set and cleared by hardware and soft-
ware. It indicates an overflow or an underflow has
occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.
0: Interrupts are enabled.
1: Interrupts are disabled.
This bit is controlled by the RIM, SIM and IRET in-
structions and is tested by the JRM and JRNM in-
structions.
This bit is driven by the SCF and RCF instructions
and tested by the JRC and JRNC instructions. It is
also affected by the “bit test and branch”, shift and
rotate instructions.
Note: Interrupts requested while I is set are
latched and can be processed when I is cleared.
By default an interrupt routine is not interruptible
22/168
1
ST7L34, ST7L35, ST7L38, ST7L39
CPU REGISTERS (cont’d)
STACK POINTER (SP)
Read/Write
Note: When the lower limit is exceeded, the Stack
Pointer wraps around to the stack upper limit, with-
out indicating the stack overflow. The previously
stored information is then overwritten and there-
fore lost. The stack also wraps in case of an under-
flow.
Reset Value: 01FFh
15
8
1
0
The stack is used to save the return address dur-
ing a subroutine call and the CPU context during
an interrupt. The user may also directly manipulate
the stack by means of the PUSH and POP instruc-
tions. In the case of an interrupt, the PCL is stored
at the first location pointed to by the SP. Then the
other registers are stored in the next locations as
shown in Figure 11.
0
7
1
0
0
0
0
0
0
SP6 SP5 SP4 SP3 SP2 SP1 SP0
The Stack Pointer is a 16-bit register which is al-
ways pointing to the next free location in the stack.
It is then decremented after data has been pushed
onto the stack and incremented before data is
popped from the stack (see Figure 11).
– When an interrupt is received, the SP is decre-
mented and the context is pushed on the stack.
– On return from interrupt, the SP is incremented
and the context is popped from the stack.
A subroutine call occupies two locations and an in-
terrupt five locations in the stack area.
Since the stack is 128 bytes deep, the 9 most sig-
nificant bits are forced by hardware. Following an
MCU Reset or after a Reset Stack Pointer instruc-
tion (RSP), the Stack Pointer contains its reset val-
ue (the SP6 to SP0 bits are set) which is the stack
higher address.
The least significant byte of the Stack Pointer
(called S) can be directly accessed by a LD in-
struction.
Figure 11. Stack Manipulation Example
CALL
Subroutine
RET
or RSP
PUSH Y
POP Y
IRET
Interrupt
Event
@ 0180h
SP
SP
SP
Y
CC
A
CC
A
CC
A
X
X
X
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
SP
SP
PCH
PCL
PCH
PCL
SP
@ 01FFh
Stack Higher Address = 01FFh
0180h
Stack Lower Address =
23/168
1
ST7L34, ST7L35, ST7L38, ST7L39
7 SUPPLY, RESET AND CLOCK MANAGEMENT
calibration values can still be obtained through these four
The device includes a range of utility features for
securing the application in critical situations (for
example in case of a power brown-out) and reduc-
ing the number of external components.
addresses.
For compatibility reasons with the SICSR register, CR[1:0]
bits are stored in the fifth and sixth positions of DEE1 and
DEE3 addresses.
Main features
Notes:
■ Clock Management
– In ICC mode, the internal RC oscillator is forced
as a clock source, regardless of the selection in
the option byte.
– 1 MHz internal RC oscillator (enabled by op-
tion byte)
– 1 to 16 MHz or 32 kHz External crystal/ceram-
ic resonator (selected by option byte)
– See “ELECTRICAL CHARACTERISTICS” on
page 127 for more information on the frequency
and accuracy of the RC oscillator.
– External Clock Input (enabled by option byte)
– PLL for multiplying the frequency by 8
– To improve clock stability and frequency accura-
cy, it is recommended to place a decoupling ca-
■ Reset Sequence Manager (RSM)
■ System Integrity Management (SI)
pacitor, typically 100nF, between the V
SS
and
DD
V
pins as close as possible to the ST7 device.
– Main supply Low voltage detection (LVD) with
reset generation (enabled by option byte)
– These bytes are systematically programmed by
ST, including on FASTROM devices. Conse-
quently, customers intending to use FASTROM
service must not use these bytes.
– Auxiliary Voltage detector (AVD) with interrupt
capability for monitoring the main supply (en-
abled by option byte)
– RCCR0 and RCCR1 calibration values will not
be erased if the readout protection bit is reset af-
ter it has been set. See “Readout Protection” on
page 15.
7.1 INTERNAL RC OSCILLATOR ADJUSTMENT
The device contains an internal RC oscillator with
high accuracy for a given device, temperature and
voltage range (4.5V to 5.5V). It must be calibrated
to obtain the frequency required in the application.
This is done by software writing an 8-bit calibration
value in the RCCR (RC Control Register) and in
the bits [6:5] in the SICSR (SI Control/Status Reg-
ister).
Caution: If the voltage or temperature conditions
change in the application, the frequency might
need recalibration.
Refer to application note AN1324 for information
on how to calibrate the RC frequency using an ex-
ternal reference signal.
7.2 PHASE LOCKED LOOP
Whenever the microcontroller is reset, the RCCR
returns to its default value (FFh), that is, each time
the device is reset, the calibration value must be
loaded in the RCCR. Predefined calibration values
The PLL can be used to multiply a 1 MHz frequen-
cy from the RC oscillator or the external clock by 8
to obtain f
of 8 MHz. The PLL is enabled (by 1
OSC
are stored in EEPROM for 3V and 5V V supply
option bit) and the multiplication factor is 8.
DD
voltages at 25°C, as shown in the following table.
The x8 PLL is intended for operation with V in
DD
ST7L3
the 3.6V to 5.5V range (refer to Section 15.1 for
the option byte description).
RCCR
RCCRH0
RCCRL0
RCCRH1
RCCRL1
Conditions
Addresses
1)
V
DD = 5V
DEE0h (CR[9:2] bits)
If the PLL is disabled and the RC oscillator is ena-
T = 25°C
A
bled, then f
= 1 MHz.
1)
OSC
DEE1h (CR[1:0] bits)
f
RC = 1 MHz
DD = 3.3V
T = 25°C
If both the RC oscillator and the PLL are disabled,
is driven by the external clock.
1)
V
DEE2h (CR[9:2] bits)
f
OSC
A
1)
DEE3h (CR[1:0] bits)
f
RC = 1 MHz
1. DEE0h, DEE1h, DEE2h and DEE3h addresses are lo-
cated in a reserved area but are special bytes containing
also the RC calibration values which are read-accessible
only in user mode. If all the EEPROM data or Flash space
(including the RC calibration values locations) has been
erased (after the readout protection removal), then the RC
24/168
1
ST7L34, ST7L35, ST7L38, ST7L39
PHASE LOCKED LOOP (cont’d)
Figure 12. PLL Output Frequency Timing
Diagram
7.3 REGISTER DESCRIPTION
MAIN CLOCK CONTROL/STATUS REGISTER
(MCCSR)
Read / Write
Reset Value: 0000 0000 (00h)
LOCKED bit set
8 x
input
freq.
7
0
0
t
STAB
MCO SMS
0
0
0
0
0
t
LOCK
Bits 7:2 = Reserved. Must be kept cleared.
t
STARTUP
Bit 1 = MCO Main Clock Out enable
This bit is read/write by software and cleared by
hardware after a reset. This bit allows to enable
the MCO output clock.
t
0: MCO clock disabled, I/O port free for general
purpose I/O.
1: MCO clock enabled.
When the PLL is started, after reset or wake-up
from Halt mode or AWUFH mode, it outputs the
clock after a delay of t
.
STARTUP
When the PLL output signal reaches the operating
frequency, the LOCKED bit in the SICSCR register
Bit 0 = SMS Slow Mode select
This bit is read/write by software and cleared by
hardware after a reset. This bit selects the input
is set. Full PLL accuracy (ACC ) is reached after
PLL
a stabilization time of t
(see Figure 12 and
STAB
clock f
or f
/32.
CPU
= f
Section 13.3.4 Internal RC Oscillator and PLL).
OSC
OSC
0: Normal mode (f
= f
)
OSC
Refer to section 7.6.4 on page 34 for a description
of the LOCKED bit in the SICSR register.
1: Slow mode (f
/32)
CPU
OSC
RC CONTROL REGISTER (RCCR)
Read / Write
Reset Value: 1111 1111 (FFh)
7
0
CR9 CR8 CR7 CR6 CR5 CR4 CR3 CR2
Bits 7:0 = CR[9:2] RC Oscillator Frequency Ad-
justment Bits
These bits must be written immediately after reset
to adjust the RC oscillator frequency and to obtain
high accuracy. The application can store the cor-
rect value for each voltage range in EEPROM and
write it to this register at start-up.
00h = maximum available frequency
FFh = lowest available frequency
These bits are used with the CR[1:0] bits in the
SICSR register. Refer to section 7.6.4 on page 34.
Note: To tune the oscillator, write a series of differ-
ent values in the register until the correct frequen-
cy is reached. The fastest method is to use a di-
chotomy starting with 80h.
25/168
1
ST7L34, ST7L35, ST7L38, ST7L39
SUPPLY, RESET AND CLOCK MANAGEMENT (cont’d)
Figure 13. Clock Management Block Diagram
CR9 CR8 CR7 CR6 CR5 CR4 CR3
CR2
RCCR
CR1 CR0
SICSR
CLKIN/2 (Ext Clock)
RC OSC
Tunable
1% RC Oscillator
1 MHz
f
OSC
PLL Clock 8 MHz
PLL 1 MHz -> 8 MHz
OSC Option bit
OSCRANGE[2:0]
Option bits
CLKIN
CLKIN
/2
CLKIN
OSC,PLLOFF,
f
DIVIDER
CLKIN
OSCRANGE[2:0]
Option bits
CLKIN/
OSC1
OSC2
OSC
1-16 MHZ
or 32 kHz
Crystal OSC /2
/2
DIVIDER
f
LTIMER
8-bit
(1ms timebase @ 8 MHz f
)
LITE TIMER 2 COUNTER
OSC
f
f
/32
OSC
OSC
/32 DIVIDER
1
0
f
CPU
TO CPU AND
PERIPHERALS
f
OSC
MCCSR
SMS
MCO
f
CPU
MCO
26/168
1
ST7L34, ST7L35, ST7L38, ST7L39
SUPPLY, RESET AND CLOCK MANAGEMENT (cont’d)
7.4 MULTI-OSCILLATOR (MO)
The main clock of the ST7 can be generated by
four different source types coming from the multi-
oscillator block (1 to 16 MHz or 32 kHz):
■ an external source
■ 5 crystal or ceramic resonator oscillators
■ an internal high frequency RC oscillator
The calibration is done through the RCCR[7:0] and
SICSR[6:5] registers.
Table 5. ST7 Clock Sources
Hardware Configuration
Each oscillator is optimized for a given frequency
range in terms of consumption and is selectable
through the option byte. The associated hardware
configurations are shown in Table 5. Refer to the
electrical characteristics section for more details.
ST7
OSC1
OSC2
EXTERNAL
SOURCE
External Clock Source
In this external clock mode, a clock signal (square,
sinus or triangle) with ~50% duty cycle has to drive
the OSC1 pin while the OSC2 pin is tied to ground.
ST7
Note: When the Multi-Oscillator is not used, PB4
is selected by default as external clock.
OSC1
OSC2
Crystal/Ceramic Oscillators
This family of oscillators has the advantage of pro-
ducing a very accurate rate on the main clock of
the ST7. The selection within a list of four oscilla-
tors with different frequency ranges has to be done
by option byte in order to reduce consumption (re-
fer to section 15.1 on page 154 for more details on
the frequency ranges). In this mode of the multi-
oscillator, the resonator and the load capacitors
have to be placed as close as possible to the oscil-
lator pins to minimize output distortion and start-up
stabilization time. The loading capacitance values
must be adjusted according to the selected oscilla-
tor.
C
C
L2
L1
LOAD
CAPACITORS
ST7
OSC1
OSC2
These oscillators are not stopped during the
RESET phase to avoid losing time in the oscillator
start-up phase.
Internal RC Oscillator
In this mode, the tunable high precision RC oscil-
lator is used as main clock source. The two oscil-
lator pins have to be tied to ground.
27/168
1
ST7L34, ST7L35, ST7L38, ST7L39
SUPPLY, RESET AND CLOCK MANAGEMENT (cont’d)
7.5 RESET SEQUENCE MANAGER (RSM)
7.5.1 Introduction
The RESET vector fetch phase duration is two
clock cycles.
The reset sequence manager includes three RE-
SET sources as shown in Figure 15:
■ External RESET source pulse
■ Internal LVD RESET (Low Voltage Detection)
■ Internal WATCHDOG RESET
If the PLL is enabled by option byte, it outputs the
clock after an additional delay of t
Figure 12).
(see
STARTUP
Figure 14. RESET Sequence Phases
Note: A reset can also be triggered following the
detection of an illegal opcode or prebyte code. Re-
fer to section 12.2.1 on page 124 for further de-
tails.
RESET
INTERNAL RESET
FETCH
VECTOR
256 or 4096
Active Phase
These sources act on the RESET pin and it is al-
ways kept low during the delay phase.
CLOCK CYCLES
The RESET service routine vector is fixed at ad-
dresses FFFEh-FFFFh in the ST7 memory map.
7.5.2 Asynchronous External RESET pin
The basic RESET sequence consists of three
phases as shown in Figure 14:
■ Active Phase depending on the RESET source
■ 256 or 4096 CPU clock cycle delay (see table
below)
■ RESET vector fetch
The RESET pin is both an input and an open-drain
output with integrated R
weak pull-up resistor.
ON
This pull-up has no fixed value but varies in ac-
cordance with the input voltage. It can be pulled
low by external circuitry to reset the device. See
the Electrical Characteristics section for more de-
tails.
Caution: When the ST7 is unprogrammed or fully
erased, the Flash is blank and the RESET vector
is not programmed. For this reason, it is recom-
mended to keep the RESET pin in low state until
programming mode is entered, in order to avoid
unwanted behavior.
A RESET signal originating from an external
source must have a duration of at least t
in
h(RSTL)in
order to be recognized (see Figure 16). This de-
tection is asynchronous and therefore the MCU
can enter reset state even in HALT mode.
The 256 or 4096 CPU clock cycle delay allows the
oscillator to stabilize and ensures that recovery
has taken place from the Reset state. The shorter
or longer clock cycle delay is automatically select-
ed depending on the clock source chosen by op-
tion byte:
CPU Clock
Clock Source
Cycle Delay
Internal RC Oscillator
256
External clock (connected to CLKIN pin)
External Crystal/Ceramic Oscillator
4096
(connected to OSC1/OSC2 pins)
28/168
1
ST7L34, ST7L35, ST7L38, ST7L39
RESET SEQUENCE MANAGER (RSM) (cont’d)
Figure 15. Reset Block Diagram
V
DD
R
ON
INTERNAL
RESET
Filter
RESET
WATCHDOG RESET
PULSE
GENERATOR
ILLEGAL OPCODE RESET1)
LVD RESET
Note 1: See “Illegal Opcode Reset” on page 124 for more details on illegal opcode reset conditions.
29/168
1
ST7L34, ST7L35, ST7L38, ST7L39
RESET SEQUENCE MANAGER (cont’d)
The RESET pin is an asynchronous signal which
plays a major role in EMS performance. In a noisy
environment, it is recommended to follow the
guidelines mentioned in the Electrical Characteris-
tics section.
■ Power-On RESET
■ Voltage Drop RESET
The device RESET pin acts as an output that is
pulled low when V < V
(rising edge) or
DD
IT+
V
< V (falling edge) as shown in Figure 16.
DD
IT-
7.5.3 External Power-On RESET
The LVD filters spikes on V larger than t
avoid parasitic resets.
to
DD
g(VDD)
If the LVD is disabled by option byte, to start up the
microcontroller correctly, the user must ensure by
means of an external reset circuit that the reset
7.5.5 Internal Watchdog RESET
signal is held low until V
is over the minimum
DD
The RESET sequence generated by an internal
Watchdog counter overflow is shown in Figure 16.
level specified for the selected f
frequency.
OSC
A proper reset signal for a slow rising V supply
can generally be provided by an external RC net-
work connected to the RESET pin.
DD
Starting from the Watchdog counter underflow, the
device RESET pin acts as an output that is pulled
low during at least t
.
w(RSTL)out
7.5.4 Internal Low Voltage Detector (LVD)
RESET
Two different RESET sequences caused by the in-
ternal LVD circuitry can be distinguished:
Figure 16. RESET Sequences
V
DD
V
V
IT+(LVD)
IT-(LVD)
LVD
RESET
EXTERNAL
RESET
WATCHDOG
RESET
RUN
RUN
RUN
RUN
ACTIVE
PHASE
ACTIVE
PHASE
ACTIVE PHASE
t
w(RSTL)out
t
h(RSTL)in
EXTERNAL
RESET
SOURCE
RESET PIN
WATCHDOG
RESET
WATCHDOG UNDERFLOW
INTERNAL RESET (256 or 4096 tCPU
VECTOR FETCH
)
30/168
1
ST7L34, ST7L35, ST7L38, ST7L39
SUPPLY, CLOCK AND RESET MANAGEMENT (cont’d)
7.6 SYSTEM INTEGRITY MANAGEMENT (SI)
The System Integrity Management block contains
the Low voltage Detector (LVD) and Auxiliary Volt-
age Detector (AVD) functions. It is managed by
the SICSR register.
Provided the minimum V value (guaranteed for
DD
the oscillator frequency) is above V
MCU can only be in two modes:
, the
IT-(LVD)
– Under full software control
– In static safe reset
Note: A reset can also be triggered following the
detection of an illegal opcode or prebyte code. Re-
fer to section 12.2.1 on page 124 for further de-
tails.
In these conditions, secure operation is always en-
sured for the application without the need for ex-
ternal reset hardware.
7.6.1 Low Voltage Detector (LVD)
During a Low Voltage Detector Reset, the RESET
pin is held low, thus permitting the MCU to reset
other devices.
The Low Voltage Detector function (LVD) gener-
ates a static reset when the V supply voltage is
DD
below a V
reference value. This means that
IT-(LVD)
Notes:
it secures the power-up as well as the power-down
keeping the ST7 in reset.
The LVD allows the device to be used without any
external RESET circuitry.
The V
reference value for a voltage drop is
IT-(LVD)
lower than the V
reference value for power-
Use of LVD with capacitive power supply: With this
type of power supply, if power cuts occur in the ap-
IT+(LVD)
on in order to avoid a parasitic reset when the
MCU starts running and sinks current on the sup-
ply (hysteresis).
plication, it is recommended to pull V
down to
DD
0V to ensure optimum restart conditions. Refer to
circuit example in Figure 96 on page 146 and note
4.
The LVD Reset circuitry generates a reset when
DD
V
is below:
The LVD is an optional function which can be se-
lected by option byte.
– V
when V is rising
DD
IT+(LVD)
– V
when V is falling
DD
IT-(LVD)
It is recommended to make sure that the V sup-
DD
The LVD function is illustrated in Figure 17.
ply voltage rises monotonously when the device is
exiting from Reset, to ensure the application func-
tions properly.
The voltage threshold can be configured by option
byte to be low, medium or high.
Figure 17. Low Voltage Detector vs Reset
V
DD
V
hys
V
V
IT+
(LVD)
IT-
(LVD)
RESET
31/168
1
ST7L34, ST7L35, ST7L38, ST7L39
SYSTEM INTEGRITY MANAGEMENT (SI) (cont’d)
Figure 18. Reset and Supply Management Block Diagram
WATCHDOG
TIMER (WDG)
STATUS FLAG
SYSTEM INTEGRITY MANAGEMENT
RESET SEQUENCE
MANAGER
AVD Interrupt Request
RESET
SICSR
(RSM)
WDGRFLOCKED LVDRFAVDFAVDIE
LOW VOLTAGE
DETECTOR
(LVD)
V
V
SS
DD
AUXILIARY VOLTAGE
DETECTOR
(AVD)
32/168
1
ST7L34, ST7L35, ST7L38, ST7L39
SYSTEM INTEGRITY MANAGEMENT (SI) (cont’d)
7.6.2 Auxiliary Voltage Detector (AVD)
abled through the option byte.
7.6.2.1 Monitoring the V Main Supply
The Voltage Detector function (AVD) is based on
DD
an analog comparison between a V
and
IT-(AVD)
The AVD voltage threshold value is relative to the
selected LVD threshold configured by option byte
(see section 15.1 on page 154).
V
reference value and the V
main sup-
IT+(AVD)
DD
ply voltage (V
). The V
reference value
AVD
IT-(AVD)
for falling voltage is lower than the V
refer-
IT+(AVD)
If the AVD interrupt is enabled, an interrupt is gen-
ence value for rising voltage in order to avoid par-
asitic detection (hysteresis).
erated when the voltage crosses the V
IT-(AVD)
or
IT+(LVD)
V
threshold (AVDF bit is set).
The output of the AVD comparator is directly read-
able by the application software through a real
time status bit (AVDF) in the SICSR register. This
bit is read only.
In the case of a drop in voltage, the AVD interrupt
acts as an early warning, allowing software to shut
down safely before the LVD resets the microcon-
troller. See Figure 19.
Caution: The AVD functions only if the LVD is en-
Figure 19. Using the AVD to Monitor V
DD
V
DD
Early Warning Interrupt
(Power has dropped, MCU not
not yet in reset)
V
hyst
V
IT+(AVD)
V
IT-(AVD)
V
V
IT+(LVD)
IT-(LVD)
AVDF bit
0
1
RESET
1
0
AVD INTERRUPT
REQUEST
IF AVDIE bit = 1
INTERRUPT Cleared by
reset
INTERRUPT Cleared by
hardware
LVD RESET
7.6.3 Low Power Modes
7.6.3.1 Interrupts
The AVD interrupt event generates an interrupt if
the corresponding Enable Control Bit (AVDIE) is
set and the interrupt mask in the CC register is re-
set (RIM instruction).
Mode
Description
No effect on SI. AVD interrupts cause the
device to exit from Wait mode.
WAIT
The SICSR register is frozen.
The AVD becomes inactive and the AVD in-
terrupt cannot be used to exit from Halt
mode.
Enable Exit
Control from
Exit
from
Halt
Event
Flag
HALT
Interrupt Event
Bit
Wait
AVD event
AVDF AVDIE
Yes
No
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1
ST7L34, ST7L35, ST7L38, ST7L39
SYSTEM INTEGRITY MANAGEMENT (cont’d)
7.6.4 Register Description
SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR)
Read/Write
Reset Value: 0110 0xx0 (6xh)
Bit 2 = LVDRF LVD reset flag
This bit indicates that the last Reset was generat-
ed by the LVD block. It is set by hardware (LVD re-
set) and cleared by software (by reading). When
the LVD is disabled by OPTION BYTE, the LVDRF
bit value is undefined.
7
0
WDG
RF
LVD
RF
0
CR1 CR0
LOCKED
AVDF AVDIE
Bit 7 = Reserved. Must be kept cleared.
Bit 1 = AVDF Voltage Detector flag
This read-only bit is set and cleared by hardware.
If the AVDIE bit is set, an interrupt request is gen-
erated when the AVDF bit is set. Refer to Figure
19 and to Section 7.6.2.1 for additional details.
Bits 6:5 = CR[1:0] RC Oscillator Frequency Ad-
justment bits
These bits, as well as CR[9:2] bits in the RCCR
register, must be written immediately after reset to
adjust the RC oscillator frequency and to obtain
high accuracy. Refer to section 7.3 on page 25.
0: V over AVD threshold
DD
1: V under AVD threshold
DD
Bit 4 = WDGRF Watchdog reset flag
Bit 0 = AVDIE Voltage Detector interrupt enable
This bit is set and cleared by software. It enables
an interrupt to be generated when the AVDF flag is
set. The pending interrupt information is automati-
cally cleared when software enters the AVD inter-
rupt routine.
This bit indicates that the last Reset was generat-
ed by the Watchdog peripheral. It is set by hard-
ware (watchdog reset) and cleared by software (by
reading SICSR register) or an LVD Reset (to en-
sure a stable cleared state of the WDGRF flag
when CPU starts).
0: AVD interrupt disabled
Combined with the LVDRF flag information, the
flag description is given by the following table.
1: AVD interrupt enabled
RESET Sources
LVDRF WDGRF
Application notes
External RESET pin
Watchdog
0
0
1
0
1
The LVDRF flag is not cleared when another RE-
SET type occurs (external or watchdog), the
LVDRF flag remains set to keep trace of the origi-
nal failure.
LVD
X
In this case, a watchdog reset can be detected by
software while an external reset can not.
Bit 3 = LOCKED PLL Locked Flag
This bit is set and cleared by hardware. It is set au-
tomatically when the PLL reaches its operating fre-
quency.
0: PLL not locked
1: PLL locked
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ST7L34, ST7L35, ST7L38, ST7L39
8 INTERRUPTS
The ST7 core may be interrupted by one of two dif-
ferent methods: Maskable hardware interrupts as
listed in Table 6, “Interrupt Mapping,” on page 36
and a non-maskable software interrupt (TRAP).
The Interrupt processing flowchart is shown in Fig-
ure 20.
8.1 NON-MASKABLE SOFTWARE INTERRUPT
This interrupt is entered when the TRAP instruc-
tion is executed regardless of the state of the I bit.
It is serviced according to the flowchart in Figure
20.
The maskable interrupts must be enabled by
clearing the I bit in order to be serviced. However,
disabled interrupts may be latched and processed
when they are enabled (see external interrupts
subsection).
8.2 EXTERNAL INTERRUPTS
External interrupt vectors can be loaded into the
PC register if the corresponding external interrupt
occurred and if the I bit is cleared. These interrupts
allow the processor to leave the HALT low power
mode.
Note: After reset, all interrupts are disabled.
When an interrupt has to be serviced:
The external interrupt polarity is selected through
the miscellaneous register or interrupt register (if
available).
– Normal processing is suspended at the end of
the current instruction execution.
– The PC, X, A and CC registers are saved onto
the stack.
An external interrupt triggered on edge will be
latched and the interrupt request automatically
cleared upon entering the interrupt service routine.
– The I bit of the CC register is set to prevent addi-
tional interrupts.
Caution: The type of sensitivity defined in the Mis-
cellaneous or Interrupt register (if available) ap-
plies to the ei source. In case of a NANDed source
(as described in the I/O ports section), a low level
on an I/O pin, configured as input with interrupt,
masks the interrupt request even in case of rising-
edge sensitivity.
– The PC is then loaded with the interrupt vector of
the interrupt to service and the first instruction of
the interrupt service routine is fetched (refer to
the Interrupt Mapping table for vector address-
es).
The interrupt service routine should finish with the
IRET instruction which causes the contents of the
saved registers to be recovered from the stack.
8.3 PERIPHERAL INTERRUPTS
Note: As a consequence of the IRET instruction,
Different peripheral interrupt flags in the status
register are able to cause an interrupt when they
are active if both:
the I bit is cleared and the main program resumes.
Priority Management
By default, a servicing interrupt cannot be inter-
rupted because the I bit is set by hardware enter-
ing in interrupt routine.
– The I bit of the CC register is cleared.
– The corresponding enable bit is set in the control
register.
In the case when several interrupts are simultane-
ously pending, an hardware priority defines which
one will be serviced first (see the Interrupt Map-
ping table).
If any of these two conditions is false, the interrupt
is latched and thus remains pending.
Clearing an interrupt request is done by:
– Writing “0” to the corresponding bit in the status
register or
Interrupts and Low Power Mode
All interrupts allow the processor to leave the
WAIT low power mode. Only external and specifi-
cally mentioned interrupts allow the processor to
leave the HALT low power mode (refer to the “Exit
from HALT” column in the Interrupt Mapping ta-
ble).
– Access to the status register while the flag is set
followed by a read or write of an associated reg-
ister.
Note: The clearing sequence resets the internal
latch. A pending interrupt (that is, waiting for being
enabled) will therefore be lost if the clear se-
quence is executed.
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ST7L34, ST7L35, ST7L38, ST7L39
INTERRUPTS (cont’d)
Figure 20. Interrupt Processing Flowchart
FROM RESET
N
I BIT SET?
Y
N
INTERRUPT
PENDING?
Y
FETCH NEXT INSTRUCTION
N
IRET?
STACK PC, X, A, CC
SET I BIT
Y
LOAD PC FROM INTERRUPT VECTOR
EXECUTE INSTRUCTION
RESTORE PC, X, A, CC FROM STACK
THIS CLEARS I BIT BY DEFAULT
Table 6. Interrupt Mapping
Exit
from
HALT
Source
No.
Register
Label
Priority
Order
Address
Vector
Description
Block
RESET
TRAP
AWU
ei0
Reset
yes
no
FFFEh-FFFFh
FFFCh-FFFDh
FFFAh-FFFBh
FFF8h-FFF9h
FFF6h-FFF7h
FFF4h-FFF5h
FFF2h-FFF3h
FFF0h-FFF1h
FFEEh-FFEFh
FFECh-FFEDh
N/A
Highest
Priority
Software Interrupt
7 Interrupt
1)
0
1
2
3
4
5
6
7
AWUCSR
yes
External Interrupt 0
External Interrupt 1
External Interrupt 2
External Interrupt 3
ei1
N/A
yes
ei2
ei3
LITE TIMER LITE TIMER RTC2 interrupt
LTCSR2
SCICR1/SCICR2
SICSR
no
no
no
LINSCI
SI
LINSCI Interrupt
AVD interrupt
AT TIMER Output Compare Interrupt
or Input Capture Interrupt
PWMxCSR or
ATCSR
8
no
FFEAh-FFEBh
AT TIMER
2)
9
10
AT TIMER Overflow Interrupt
LITE TIMER Input Capture Interrupt
LITE TIMER RTC1 Interrupt
SPI Peripheral Interrupts
ATCSR
LTCSR
LTCSR
SPICSR
ATCSR2
yes
FFE8h-FFE9h
FFE6h-FFE7h
FFE4h-FFE5h
FFE2h-FFE3h
FFE0h-FFE1h
no
LITE TIMER
SPI
2)
11
yes
Lowest
Priority
12
yes
no
13
AT TIMER AT TIMER Overflow Interrupt 2
Notes:
1. This interrupt exits the MCU from “Auto Wake-up from Halt” mode only.
2. These interrupts exit the MCU from “ACTIVE HALT” mode only.
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ST7L34, ST7L35, ST7L38, ST7L39
INTERRUPTS (cont’d)
EXTERNAL INTERRUPT CONTROL REGISTER
(EICR)
External Interrupt I/O pin selection
ei31
ei30
I/O Pin
Read/Write
Reset Value: 0000 0000 (00h)
0
0
1
1
0
1
0
1
No interrupt *
PB0
7
0
PB1
PB2
IS31 IS30 IS21 IS20 IS11 IS10 IS01 IS00
* Reset State
Bits 7:6 = IS3[1:0] ei3 sensitivity
These bits define the interrupt sensitivity for ei3
(Port B0) according to Table 7.
Bits 5:4 = ei2[1:0] ei2 pin selection
These bits are written by software. They select the
Port B I/O pin used for the ei2 external interrupt ac-
cording to the table below.
Bits 5:4 = IS2[1:0] ei2 sensitivity
These bits define the interrupt sensitivity for ei2
(Port B3) according to Table 7.
External Interrupt I/O pin selection
ei21
ei20
I/O Pin
No interrupt *
PB3
Bits 3:2 = IS1[1:0] ei1 sensitivity
0
0
1
1
0
1
0
1
These bits define the interrupt sensitivity for ei1
(Port A7) according to Table 7.
PB5
Bits 1:0 = IS0[1:0] ei0 sensitivity
These bits define the interrupt sensitivity for ei0
(Port A0) according to Table 7.
PB6
* Reset State
Bits 3:2 = ei1[1:0] ei1 pin selection
Note: These 8 bits can be written only when the I
These bits are written by software. They select the
Port A I/O pin used for the ei1 external interrupt ac-
cording to the table below.
bit in the CC register is set.
Table 7. Interrupt Sensitivity Bits
External Interrupt I/O pin selection
ISx1 ISx0
External Interrupt Sensitivity
Falling edge and low level
Rising edge only
ei11
ei10
I/O Pin
No interrupt *
PA4
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
Falling edge only
PA5
Rising and falling edge
PA6
* Reset State
EXTERNAL INTERRUPT SELECTION REGIS-
TER (EISR)
Bits 1:0 = ei0[1:0] ei0 pin selection
These bits are written by software. They select the
Port A I/O pin used for the ei0 external interrupt ac-
cording to the table below.
Read/Write
Reset Value: 0000 0000 (00h)
External Interrupt I/O pin selection
7
0
ei01
ei00
I/O Pin
No Interrupt*
PA1
ei31 ei30 ei21 ei20 ei11 ei10 ei01 ei00
0
0
1
1
0
1
0
1
Bits 7:6 = ei3[1:0] ei3 pin selection
PA2
These bits are written by software. They select the
Port B I/O pin used for the ei3 external interrupt ac-
cording to the following table.
PA3
* Reset State
Bits 1:0 = Reserved
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ST7L34, ST7L35, ST7L38, ST7L39
9 POWER SAVING MODES
9.1 INTRODUCTION
9.2 SLOW MODE
To give a large measure of flexibility to the applica-
tion in terms of power consumption, five main pow-
er saving modes are implemented in the ST7 (see
Figure 21):
■ Slow
■ Wait (and Slow-Wait)
■ Active Halt
This mode has two targets:
– To reduce power consumption by decreasing the
internal clock in the device,
– To adapt the internal clock frequency (f
the available supply voltage.
) to
CPU
SLOW mode is controlled by the SMS bit in the
MCCSR register which enables or disables Slow
mode.
■ Auto Wake up From Halt (AWUFH)
■ Halt
In this mode, the oscillator frequency is divided by
32. The CPU and peripherals are clocked at this
lower frequency.
After a RESET the normal operating mode is se-
lected by default (RUN mode). This mode drives
the device (CPU and embedded peripherals) by
means of a master clock which is based on the
main oscillator frequency divided or multiplied by 2
Note: SLOW-WAIT mode is activated when enter-
ing WAIT mode while the device is already in
SLOW mode.
(f
).
OSC2
Figure 22. SLOW Mode Clock Transition
From RUN mode, the different power saving
modes may be selected by setting the relevant
register bits or by calling the specific ST7 software
instruction whose action depends on the oscillator
status.
f
/32
f
OSC
OSC
f
CPU
Figure 21. Power Saving Mode Transitions
f
OSC
High
RUN
SMS
NORMAL RUN MODE
REQUEST
SLOW
WAIT
SLOW WAIT
ACTIVE HALT
AUTO WAKE UP FROM HALT
HALT
Low
POWER CONSUMPTION
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ST7L34, ST7L35, ST7L38, ST7L39
POWER SAVING MODES (cont’d)
9.3 WAIT MODE
Figure 23. WAIT Mode Flowchart
WAIT mode places the MCU in a low power con-
sumption mode by stopping the CPU.
This power saving mode is selected by calling the
‘WFI’ instruction.
All peripherals remain active. During WAIT mode,
the I bit of the CC register is cleared, to enable all
interrupts. All other registers and memory remain
unchanged. The MCU remains in WAIT mode until
an interrupt or RESET occurs, whereupon the Pro-
gram Counter branches to the starting address of
the interrupt or Reset service routine.
OSCILLATOR
PERIPHERALS
CPU
ON
ON
OFF
0
WFI INSTRUCTION
I BIT
N
RESET
Y
N
The MCU will remain in WAIT mode until a Reset
or an Interrupt occurs, causing it to wake up.
INTERRUPT
Y
Refer to Figure 23.
OSCILLATOR
PERIPHERALS
CPU
ON
OFF
ON
0
I BIT
256 OR 4096 CPU CLOCK
CYCLE DELAY
OSCILLATOR
PERIPHERALS
CPU
ON
ON
ON
X 1)
I BIT
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Note:
1. Before servicing an interrupt, the CC register is pushed
on the stack. The I bit of the CC register is set during the
interrupt routine and cleared when the CC register is
popped.
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ST7L34, ST7L35, ST7L38, ST7L39
POWER SAVING MODES (cont’d)
9.4 HALT MODE
Figure 25. HALT Mode Flowchart
The HALT mode is the lowest power consumption
mode of the MCU. It is entered by executing the
‘HALT’ instruction when ACTIVE HALT is disabled
(see section 9.5 on page 41 for more details) and
when the AWUEN bit in the AWUCSR register is
cleared.
HALT INSTRUCTION
(Active Halt disabled)
(AWUCSR.AWUEN=0)
WATCHDOG
ENABLE
0
DISABLE
The MCU can exit HALT mode on reception of ei-
ther a specific interrupt (see Table 6, “Interrupt
Mapping,” on page 36) or a RESET. When exiting
HALT mode by means of a RESET or an interrupt,
the oscillator is immediately turned on and the 256
CPU cycle delay is used to stabilize the oscillator.
After the start up delay, the CPU resumes opera-
tion by servicing the interrupt or by fetching the re-
set vector which woke it up (see Figure 25).
WDGHALT 1)
1
WATCHDOG
RESET
OSCILLATOR
OFF
PERIPHERALS 2)
OFF
OFF
0
CPU
I BIT
When entering HALT mode, the I bit in the CC reg-
ister is forced to 0 to enable interrupts. Therefore,
if an interrupt is pending, the MCU wakes up im-
mediately.
N
RESET
Y
N
In HALT mode, the main oscillator is turned off
causing all internal processing to be stopped, in-
cluding the operation of the on-chip peripherals.
All peripherals are not clocked except the ones
which get their clock supply from another clock
generator (such as an external or auxiliary oscilla-
tor).
INTERRUPT 3)
OSCILLATOR
PERIPHERALS
CPU
Y
ON
OFF
ON
I BIT
X 4)
The compatibility of Watchdog operation with
HALT mode is configured by the “WDGHALT” op-
tion bit of the option byte. The HALT instruction
when executed while the Watchdog system is en-
abled, can generate a Watchdog RESET (see sec-
tion 15.1 on page 154 for more details).
256 OR 4096 CPU CLOCK
CYCLE DELAY
OSCILLATOR
PERIPHERALS
CPU
ON
ON
ON
X 4)
Figure 24. HALT Timing Overview
I BIT
256 or 4096 CPU
CYCLE DELAY
FETCH RESET VECTOR
OR SERVICE INTERRUPT
RUN
HALT
RUN
RESET
OR
INTERRUPT
Notes:
HALT
INSTRUCTION
[Active Halt disabled]
1. WDGHALT is an option bit. See option byte section for
more details.
2. Peripheral clocked with an external clock source can
still be active.
FETCH
VECTOR
3. Only some specific interrupts can exit the MCU from
HALT mode (such as external interrupt). Refer to Table 6,
“Interrupt Mapping,” on page 36 for more details.
4. Before servicing an interrupt, the CC register is pushed
on the stack. The I bit of the CC register is set during the
interrupt routine and cleared when the CC register is
popped.
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ST7L34, ST7L35, ST7L38, ST7L39
POWER SAVING MODES (cont’d)
9.4.0.1 Halt Mode Recommendations
9.5 ACTIVE HALT MODE
– Make sure that an external event is available to
wake up the microcontroller from Halt mode.
ACTIVE HALT mode is the lowest power con-
sumption mode of the MCU with a real time clock
(RTC) available. It is entered by executing the
‘HALT’ instruction. The decision to enter either in
ACTIVE HALT or HALT mode is given by the LTC-
SR/ATCSR register status as shown in the follow-
ing table:.
– When using an external interrupt to wake up the
microcontroller, reinitialize the corresponding I/O
as “Input Pull-up with Interrupt” or “floating inter-
rupt” before executing the HALT instruction. The
main reason for this is that the I/O may be wrong-
ly configured due to external interference or by
an unforeseen logical condition.
ATCSR
OVFIE1
bit
LTCSR1
TB1IE bit
ATCSR ATCSR
CK1 bit CK0 bit
Meaning
– For the same reason, reinitialize the level sensi-
tiveness of each external interrupt as a precau-
tionary measure.
0
0
1
x
x
0
x
1
x
x
x
0
0
x
x
1
ACTIVE HALT
mode disabled
– The opcode for the HALT instruction is 0x8E. To
avoid an unexpected HALT instruction due to a
program counter failure, it is advised to clear all
occurrences of the data value 0x8E from memo-
ry. For example, avoid defining a constant in pro-
gram memory with the value 0x8E.
ACTIVE HALT
mode enabled
The MCU can exit ACTIVE HALT mode on recep-
tion of a specific interrupt (see Table 6, “Interrupt
Mapping,” on page 36) or a RESET.
– As the HALT instruction clears the interrupt mask
in the CC register to allow interrupts, the user
may choose to clear all pending interrupt bits be-
fore executing the HALT instruction. This avoids
entering other peripheral interrupt routines after
executing the external interrupt routine corre-
sponding to the wake-up event (reset or external
interrupt).
– When exiting ACTIVE HALT mode by means of
a RESET, a 256 CPU cycle delay occurs. After
the start up delay, the CPU resumes operation
by fetching the reset vector which woke it up (see
Figure 27).
– When exiting ACTIVE HALT mode by means of
an interrupt, the CPU immediately resumes oper-
ation by servicing the interrupt vector which woke
it up (see Figure 27).
When entering ACTIVE HALT mode, the I bit in the
CC register is cleared to enable interrupts. There-
fore, if an interrupt is pending, the MCU wakes up
immediately (see Note 3).
In ACTIVE HALT mode, only the main oscillator
and the selected timer counter (LT/AT) are running
to keep a wake-up time base. All other peripherals
are not clocked except those which get their clock
supply from another clock generator (such as ex-
ternal or auxiliary oscillator).
Note: As soon as ACTIVE HALT is enabled, exe-
cuting a HALT instruction while the Watchdog is
active does not generate a RESET.
This means that the device cannot spend more
than a defined delay in this power saving mode.
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ST7L34, ST7L35, ST7L38, ST7L39
POWER SAVING MODES (cont’d)
Figure 26. ACTIVE HALT Timing Overview
9.6 AUTO WAKE UP FROM HALT MODE
Auto Wake Up From Halt (AWUFH) mode is simi-
lar to Halt mode with the additional of an internal
RC oscillator for wake-up. Compared to ACTIVE
HALT mode, AWUFH has lower power consump-
tion (the main clock is not kept running), but there
is no accurate realtime clock available.
ACTIVE
256 OR 4096 CPU
CYCLE DELAY
RUN
HALT
RUN
1)
RESET
OR
HALT
INSTRUCTION
[Active Halt Enabled]
INTERRUPT
FETCH
VECTOR
It is entered by executing the HALT instruction
when the AWUEN bit in the AWUCSR register has
been set.
Figure 28. AWUFH Mode Block Diagram
Figure 27. ACTIVE HALT Mode Flowchart
AWUCK Opt bit
OSCILLATOR
PERIPHERALS 2)
CPU
ON
OFF
OFF
0
AWU RC
1
HALT INSTRUCTION
(Active Halt enabled)
(AWUCSR.AWUEN=0)
Oscillator
to
Autoreload Timer
Input Capture
I BIT
32 kHz
0
Oscillator
N
f
AWU_RC
RESET
Y
N
AWUFH
interrupt
INTERRUPT 3)
AWUFH
prescaler/1 .. 255
/64
OSCILLATOR
PERIPHERALS 2)
CPU
Y
divider
ON
OFF
ON
(ei0 source)
I BIT
X 4)
As soon as HALT mode is entered and if the
AWUEN bit has been set in the AWUCSR register,
the AWU RC oscillator provides a clock signal
256 OR 4096 CPU
CLOCK CYCLE
DELAY
(f
). Its frequency is divided by a fixed divid-
AWU_RC
er and a programmable prescaler controlled by the
AWUPR register. The output of this prescaler pro-
vides the delay time. When the delay has elapsed
the AWUF flag is set by hardware and an interrupt
wakes-up the MCU from Halt mode. At the same
time the main oscillator is immediately turned on
and a 256 cycle delay is used to stabilize it. After
this start-up delay, the CPU resumes operation by
servicing the AWUFH interrupt. The AWU flag and
its associated interrupt are cleared by software
reading the AWUCSR register.
OSCILLATOR
PERIPHERALS
CPU
ON
ON
ON
X 4)
I BIT
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Notes:
1. This delay occurs only if the MCU exits ACTIVE HALT
mode by means of a RESET.
2. Peripherals clocked with an external clock source can
still be active.
3. Only the RTC1 interrupt and some specific interrupts
can exit the MCU from ACTIVE HALT mode. Refer to
Table 6, “Interrupt Mapping,” on page 36 for more details.
4. Before servicing an interrupt, the CC register is pushed
on the stack. The I bit of the CC register is set during the
interrupt routine and cleared when the CC register is
popped.
To compensate for any frequency dispersion of
the AWU RC oscillator, it can be calibrated by
measuring the clock frequency f
and then
AWU_RC
calculating the right prescaler value. Measurement
mode is enabled by setting the AWUM bit in the
AWUCSR register in Run mode. This connects
f
to the input capture of the 12-bit Autore-
AWU_RC
load timer, allowing the f
to be measured
AWU_RC
using the main oscillator clock as a reference time-
base.
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ST7L34, ST7L35, ST7L38, ST7L39
POWER SAVING MODES (cont’d)
Similarities with Halt mode
– In AWUFH mode, the main oscillator is turned off
causing all internal processing to be stopped, in-
cluding the operation of the on-chip peripherals.
None of the peripherals are clocked except those
which get their clock supply from another clock
generator (such as an external or auxiliary oscil-
lator like the AWU oscillator).
The following AWUFH mode behavior is the same
as normal Halt mode:
– The MCU can exit AWUFH mode by means of
any interrupt with exit from Halt capability or a re-
set (see Section 9.4 HALT MODE).
– When entering AWUFH mode, the I bit in the CC
register is forced to 0 to enable interrupts. There-
fore, if an interrupt is pending, the MCU wakes
up immediately.
– The compatibility of Watchdog operation with
AWUFH mode is configured by the WDGHALT
option bit in the option byte. Depending on this
setting, the HALT instruction when executed
while the Watchdog system is enabled, can gen-
erate a Watchdog RESET.
Figure 29. AWUF Halt Timing Diagram
t
AWU
RUN MODE
HALT MODE
256 OR 4096 t
RUN MODE
Clear
CPU
f
CPU
f
AWU_RC
by software
AWUFH interrupt
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ST7L34, ST7L35, ST7L38, ST7L39
POWER SAVING MODES (cont’d)
Notes:
Figure 30. AWUFH Mode Flowchart
1. WDGHALT is an option bit. See option byte section for
more details.
2. Peripheral clocked with an external clock source can
still be active.
3. Only an AWUFH interrupt and some specific interrupts
can exit the MCU from HALT mode (such as external in-
terrupt). Refer to Table 6, “Interrupt Mapping,” on page 36
for more details.
HALT INSTRUCTION
(Active Halt disabled)
(AWUCSR.AWUEN=1)
ENABLE
WATCHDOG
4. Before servicing an interrupt, the CC register is pushed
on the stack. The I[1:0] bits of the CC register are set to
the current software priority level of the interrupt routine
and recovered when the CC register is popped.
0
DISABLE
WDGHALT1)
1
AWU RC OSC
MAIN OSC
ON
OFF
OFF
OFF
10
WATCHDOG
RESET
PERIPHERALS2)
CPU
I[1:0] BITS
N
RESET
Y
N
INTERRUPT3)
AWU RC OSC
MAIN OSC
OFF
ON
Y
PERIPHERALS
CPU
I[1:0] BITS
OFF
ON
XX4)
256 CPU CLOCK
CYCLE DELAY
AWU RC OSC
MAIN OSC
PERIPHERALS
CPU
OFF
ON
ON
ON
I[1:0] BITS
XX4)
FETCH RESET VECTOR
OR SERVICE INTERRUPT
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ST7L34, ST7L35, ST7L38, ST7L39
POWER SAVING MODES (cont’d)
9.6.0.1 Register Description
AWUFH PRESCALER REGISTER (AWUPR)
Read/Write
AWUFH CONTROL/STATUS REGISTER
(AWUCSR)
Read/Write
Reset Value: 0000 0000 (00h)
Reset Value: 1111 1111 (FFh)
7
0
AWU AWU AWU AWU AWU AWU AWU AWU
PR7 PR6 PR5 PR4 PR3 PR2 PR1 PR0
7
0
Bits 7:0 = AWUPR[7:0] Auto Wake Up Prescaler
These 8 bits define the AWUPR Dividing factor (as
explained below
0
0
0
0
0
AWUF AWUM AWUEN
Bits 7:3 = Reserved
AWUPR[7:0]
Dividing factor
00h
01h
...
Forbidden
Bit 1 = AWUF Auto Wake Up Flag
This bit is set by hardware when the AWU module
generates an interrupt and cleared by software on
reading AWUCSR. Writing to this bit does not
change its value.
1
...
FEh
FFh
254
255
0: No AWU interrupt occurred
1: AWU interrupt occurred
In AWU mode, the period that the MCU stays in
Halt Mode (t
fined by
in Figure 29 on page 43) is de-
AWU
Bit 2 = AWUM Auto Wake Up Measurement
This bit enables the AWU RC oscillator and con-
nects its output to the input capture of the 12-bit
autoreload timer. This allows the timer to be used
to measure the AWU RC oscillator dispersion and
then compensate this dispersion by providing the
right value in the AWUPR register.
1
t
= 64 × AWUPR × ------------------------- + t
RCSTRT
AWU
f
AWURC
This prescaler register can be programmed to
modify the time that the MCU stays in Halt mode
before waking up automatically.
0: Measurement disabled
1: Measurement enabled
Note: If 00h is written to AWUPR, depending on
the product, an interrupt is generated immediately
after a HALT instruction, or the AWUPR remains
unchanged.
Bit 0 = AWUEN Auto Wake Up From Halt Enabled
This bit enables the Auto Wake Up From Halt fea-
ture: Once HALT mode is entered, the AWUFH
wakes up the microcontroller after a time delay de-
pendent on the AWU prescaler value. It is set and
cleared by software.
0: AWUFH (Auto Wake Up From Halt) mode disa-
bled
1: AWUFH (Auto Wake Up From Halt) mode ena-
bled
Table 8. AWU Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
AWUPR
Reset Value
AWUPR7 AWUPR6 AWUPR5 AWUPR4 AWUPR3 AWUPR2 AWUPR1 AWUPR0
0049h
004Ah
1
1
1
1
1
1
1
1
AWUCSR
Reset Value
0
0
0
0
0
AWUF
AWUM
AWUEN
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ST7L34, ST7L35, ST7L38, ST7L39
10 I/O PORTS
10.1 INTRODUCTION
If several I/O interrupt pins on the same interrupt
vector are selected simultaneously, they are logi-
cally combined. For this reason if one of the inter-
rupt pins is tied low, it may mask the others.
The I/O ports allow data transfer. An I/O port can
contain up to 8 pins. Each pin can be programmed
independently either as a digital input or digital
output. In addition, specific pins may have several
other functions. These functions can include exter-
nal interrupt, alternate signal input/output for on-
chip peripherals or analog input.
External interrupts are hardware interrupts. Fetch-
ing the corresponding interrupt vector automatical-
ly clears the request latch. Modifying the sensitivity
bits will clear any pending interrupts.
10.2.2 Output Modes
10.2 FUNCTIONAL DESCRIPTION
Setting the DDRx bit selects output mode. Writing
to the DR bits applies a digital value to the I/O
through the latch. Reading the DR bits returns the
previously stored value.
A Data Register (DR) and a Data Direction Regis-
ter (DDR) are always associated with each port.
The Option Register (OR), which allows input/out-
put options, may or may not be implemented. The
following description takes into account the OR
register. Refer to the Port Configuration table for
device specific information.
If an OR bit is available, different output modes
can be selected by software: Push-pull or open-
drain. Refer to I/O Port Implementation section for
configuration.
DR Value and Output Pin Status
An I/O pin is programmed using the corresponding
bits in the DDR, DR and OR registers: Bit x corre-
sponding to pin x of the port.
DR
Push-Pull
Open-Drain
0
1
V
V
OL
Floating
OL
Figure 31 shows the generic I/O block diagram.
V
OH
10.2.1 Input Modes
10.2.3 Alternate Functions
Clearing the DDRx bit selects input mode. In this
mode, reading its DR bit returns the digital value
from that I/O pin.
Many ST7s I/Os have one or more alternate func-
tions. These may include output signals from, or
input signals to, on-chip peripherals. The Device
Pin Description table describes which peripheral
signals can be input/output to which ports.
If an OR bit is available, different input modes can
be configured by software: Floating or pull-up. Re-
fer to I/O Port Implementation section for configu-
ration.
A signal coming from an on-chip peripheral can be
output on an I/O. To do this, enable the on-chip
peripheral as an output (enable bit in the peripher-
al’s control register). The peripheral configures the
I/O as an output and takes priority over standard I/
O programming. The I/O’s state is readable by ad-
dressing the corresponding I/O data register.
Notes:
1. Writing to the DR modifies the latch value but
does not change the state of the input pin.
2. Do not use read/modify/write instructions
(BSET/BRES) to modify the DR register.
External Interrupt Function
Configuring an I/O as floating enables alternate
function input. It is not recommended to configure
an I/O as pull-up as this will increase current con-
sumption. Before using an I/O as an alternate in-
put, configure it without interrupt. Otherwise spuri-
ous interrupts can occur.
Depending on the device, setting the ORx bit while
in input mode can configure an I/O as an input with
interrupt. In this configuration, a signal edge or lev-
el input on the I/O generates an interrupt request
via the corresponding interrupt vector (eix).
Falling or rising edge sensitivity is programmed in-
dependently for each interrupt vector. The Exter-
nal Interrupt Control Register (EICR) or the Miscel-
laneous Register controls this sensitivity, depend-
ing on the device.
Configure an I/O as input floating for an on-chip
peripheral signal which can be input and output.
Caution: I/Os which can be configured as both an
analog and digital alternate function need special
attention. The user must control the peripherals so
that the signals do not arrive at the same time on
the same pin. If an external clock is used, only the
clock alternate function should be employed on
that I/O pin and not the other alternate function.
Each external interrupt vector is linked to a dedi-
cated group of I/O port pins (see pinout description
in section 2 on page 7 and interrupt section).
46/168
1
ST7L34, ST7L35, ST7L38, ST7L39
I/O PORTS (cont’d)
Figure 31. I/O Port General Block Diagram
ALTERNATE
OUTPUT
From on-chip peripheral
1
0
REGISTER
ACCESS
P-BUFFER
(see table below)
V
DD
ALTERNATE
ENABLE
BIT
PULL-UP
(see table below)
DR
V
DD
DDR
OR
PULL-UP
CONDITION
PAD
If implemented
OR SEL
DDR SEL
DR SEL
N-BUFFER
DIODES
(see table below)
ANALOG
INPUT
CMOS
SCHMITT
TRIGGER
1
0
ALTERNATE
INPUT
To on-chip peripheral
EXTERNAL
INTERRUPT
REQUEST (ei )
Combinational
Logic
FROM
OTHER
BITS
x
SENSITIVITY
SELECTION
Note: Refer to the Port Configuration
table for device specific information.
Table 9. I/O Port Mode Options
Configuration Mode
Diodes
Pull-Up
P-Buffer
to V
to V
SS
DD
Floating with/without Interrupt
Input
Off
On
Off
Pull-up with/without Interrupt
On
Push-pull
On
Off
NI
On
Off
NI
Output
Open Drain (logic level)
True Open Drain
NI (see note 1)
Legend: NI - not implemented
Off - implemented not activated
the pad and V is implemented to protect the de-
OL
vice against positive stress.
On - implemented and activated
Note 2: For further details on port configuration,
please refer to Table 11 and Table 12 on page 50.
Note 1: The diode to V is not implemented in the
DD
true open drain pads. A local protection between
47/168
1
ST7L34, ST7L35, ST7L38, ST7L39
I/O PORTS (cont’d)
Table 10. I/O Configurations
Hardware Configuration
DR REGISTER ACCESS
V
DD
NOTE 3
PULL-UP
CONDITION
R
W
R
PU
DR
REGISTER
DATA BUS
PAD
ALTERNATE INPUT
To on-chip peripheral
FROM
OTHER
PINS
EXTERNAL INTERRUPT
SOURCE (ei )
x
COMBINATIONAL
LOGIC
INTERRUPT
CONDITION
POLARITY
SELECTION
ANALOG INPUT
V
NOTE 3
DD
DR REGISTER ACCESS
R
PU
PAD
R/W
DR
REGISTER
DATA BUS
DR REGISTER ACCESS
NOTE 3
V
DD
R
PU
R/W
DR
REGISTER
DATA BUS
PAD
ALTERNATE
ENABLE
BIT
ALTERNATE
OUTPUT
From on-chip peripheral
Notes:
1. When the I/O port is in input configuration and the associated alternate function is enabled as an output, reading the
DR register will read the alternate function output status.
2. When the I/O port is in output configuration and the associated alternate function is enabled as an input, the alternate
function reads the pin status given by the DR register content.
3. For true open drain, these elements are not implemented.
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ST7L34, ST7L35, ST7L38, ST7L39
I/O PORTS (cont’d)
Analog alternate function
10.4 UNUSED I/O PINS
Configure the I/O as floating input to use an ADC
input. The analog multiplexer (controlled by the
ADC registers) switches the analog voltage
present on the selected pin to the common analog
rail, connected to the ADC input.
Unused I/O pins must be connected to fixed volt-
age levels. Refer to Section 13.8.
10.5 LOW POWER MODES
Mode
Description
Analog recommendations
No effect on I/O ports. External interrupts
cause the device to exit from WAIT mode.
Do not change the voltage level or loading on any
I/O while conversion is in progress. Do not have
clocking pins located close to a selected analog
pin.
WAIT
No effect on I/O ports. External interrupts
cause the device to exit from HALT mode.
HALT
WARNING: The analog input voltage level must
be within the limits stated in the absolute maxi-
mum ratings.
10.6 INTERRUPTS
The external interrupt event generates an interrupt
if the corresponding configuration is selected with
DDR and OR registers and if the I bit in the CC
register is cleared (RIM instruction).
10.3 I/O PORT IMPLEMENTATION
The hardware implementation on each I/O port de-
pends on the settings in the DDR and OR registers
and specific I/O port features such as ADC input or
open drain.
Enable Exit
Control from
Exit
from
Halt
Event
Flag
Interrupt Event
Bit
Wait
Switching these I/O ports from one state to anoth-
er should be done in a sequence that prevents un-
wanted side effects. Recommended safe transi-
tions are illustrated in Figure 32. Other transitions
are potentially risky and should be avoided, since
they may present unwanted side-effects such as
spurious interrupt generation.
External interrupt on
selected external
event
DDRx
ORx
-
Yes
Yes
Related Documentation
SPI Communication between ST7 and EEPROM
(AN970)
Figure 32. Interrupt I/O Port State Transitions
S/W implementation of I2C bus master (AN1045)
Software LCD driver (AN1048)
01
00
10
11
INPUT
floating/pull-up
interrupt
INPUT
floating
(reset state)
OUTPUT
open-drain
OUTPUT
push-pull
= DDR, OR
XX
49/168
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ST7L34, ST7L35, ST7L38, ST7L39
I/O PORTS (cont’d)
The I/O port register configurations are summa-
rized as follows.
Interrupt Ports
Ports where the external interrupt capability is
selected using the EISR register
Standard Ports
PA7:0, PB6:0
MODE
DDR
OR
0
floating input
pull-up interrupt input
0
0
MODE
DDR
OR
0
1
floating input
pull-up input
0
0
1
1
1
open drain output
push-pull output
0
1
Table 11. Port Configuration (Standard Ports)
Input (DDR = 0)
Output (DDR = 1)
Port
Pin name
OR = 0
OR = 1
OR = 0
OR = 1
Port A
Port B
PA7:0
PB6:0
floating
pull-up
open drain
push-pull
Note: On ports where the external interrupt capability is selected using the EISR register, the configura-
tion will be as follows:
Table 12. Port Configuration (External Interrupts)
Input with interrupt (DDR = 0 ; EISR ≠ 00)
Port
Pin name
OR = 0
OR = 1
Port A
Port B
PA6:1
PB5:0
floating
pull-up
Table 13. I/O Port Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
PADR
MSB
1
LSB
1
0000h
0001h
0002h
0003h
0004h
0005h
Reset Value
1
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
PADDR
MSB
0
LSB
0
Reset Value
0
1
1
0
0
PAOR
MSB
0
LSB
0
Reset Value
PBDR
MSB
1
LSB
1
Reset Value
PBDDR
MSB
0
LSB
0
Reset Value
PBOR
MSB
0
LSB
0
Reset Value
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ST7L34, ST7L35, ST7L38, ST7L39
11 ON-CHIP PERIPHERALS
11.1 WATCHDOG TIMER (WDG)
11.1.1 Introduction
■ Optional
reset
on
HALT
instruction
(configurable by option byte)
The Watchdog timer is used to detect the occur-
rence of a software fault, usually generated by ex-
ternal interference or by unforeseen logical condi-
tions, which causes the application program to
abandon its normal sequence. The Watchdog cir-
cuit generates an MCU reset on expiry of a pro-
grammed time period, unless the program refresh-
es the counter’s contents before the T6 bit be-
comes cleared.
■ Hardware Watchdog selectable by option byte
11.1.3 Functional Description
The counter value stored in the CR register (bits
T[6:0]), is decremented every 16000 machine cy-
cles and the length of the time-out period can be
programmed by the user in 64 increments.
11.1.2 Main Features
If the watchdog is activated (the WDGA bit is set)
and when the 7-bit timer (bits T[6:0]) rolls over
from 40h to 3Fh (T6 becomes cleared), it initiates
a reset cycle pulling low the reset pin for typically
30µs.
■ Programmable free-running downcounter (64
increments of 16000 CPU cycles)
■ Programmable reset
■ Reset (if watchdog activated) when the T6 bit
reaches zero
Figure 33. Watchdog Block Diagram
RESET
WATCHDOG CONTROL REGISTER (WDGCR)
T5
WDGA T6
T1
T0
T4
T2
T3
7-bit DOWNCOUNTER
CLOCK DIVIDER
f
CPU
÷16000
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ST7L34, ST7L35, ST7L38, ST7L39
WATCHDOG TIMER (cont’d)
The application program must write in the CR reg-
ister at regular intervals during normal operation to
prevent an MCU reset. This downcounter is free-
running: It counts down even if the watchdog is
disabled. The value to be stored in the CR register
must be between FFh and C0h (see Table 14
.Watchdog Timing):
Refer to the Option Byte description in section
15.1 on page 154.
11.1.4.1 Using Halt Mode with the WDG
(WDGHALT option)
If Halt mode with Watchdog is enabled by option
byte (No watchdog reset on HALT instruction), it is
recommended before executing the HALT instruc-
tion to refresh the WDG counter, to avoid an unex-
pected WDG reset immediately after waking up
the microcontroller.
– The WDGA bit is set (watchdog enabled)
– The T6 bit is set to prevent generating an imme-
diate reset
– The T[5:0] bits contain the number of increments
which represents the time delay before the
watchdog produces a reset.
11.1.5 Interrupts
None.
11.1.6 Register Description
WATCHDOG CONTROL REGISTER (WDGCR)
Read/Write
Following a reset, the watchdog is disabled. Once
activated it cannot be disabled, except by a reset.
The T6 bit can be used to generate a software re-
set (the WDGA bit is set and the T6 bit is cleared).
Reset Value: 0111 1111 (7Fh)
If the watchdog is activated, the HALT instruction
will generate a Reset.
7
0
WDGA T6
T5
T4
T3
T2
T1
T0
Table 14.Watchdog Timing
f
= 8 MHz
CPU
Bit 7 = WDGA Activation bit.
WDG
Counter
Code
min
(ms)
max
(ms)
This bit is set by software and only cleared by
hardware after a reset. When WDGA = 1, the
watchdog can generate a reset.
C0h
FFh
1
2
0: Watchdog disabled
1: Watchdog enabled
127
128
Note: This bit is not used if the hardware watch-
dog option is enabled by option byte.
Note: The timing variation shown in Table 14 is
due to the unknown status of the prescaler when
writing to the CR register.
Bits 6:0 = T[6:0] 7-bit timer (MSB to LSB).
These bits contain the decremented value. A reset
is produced when it rolls over from 40h to 3Fh (T6
becomes cleared).
11.1.4 Hardware Watchdog Option
If Hardware Watchdog is selected by option byte,
the watchdog is always active and the WDGA bit in
the CR is not used.
Table 15. Watchdog Timer Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
WDGCR
Reset Value
WDGA
0
T6
1
T5
1
T4
1
T3
1
T2
1
T1
1
T0
1
002Eh
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ST7L34, ST7L35, ST7L38, ST7L39
ON-CHIP PERIPHERALS (cont’d)
11.2 DUAL 12-BIT AUTORELOAD TIMER 3 (AT3)
11.2.1 Introduction
■ PWM mode
– Generation of four independent PWMx signals
The 12-bit Autoreload Timer can be used for gen-
eral-purpose timing functions. It is based on one or
two free-running 12-bit upcounters with an input
capture register and four PWM output channels.
There are six external pins:
– Dead time generation for half-bridge driving
mode with programmable dead time
– Frequency 2 kHz to 4 MHz (@ 8 MHz f
– Programmable duty-cycles
– Polarity control
)
CPU
– 4 PWM outputs
– Programmable output modes
■ Output Compare Mode
■ Input Capture Mode
– ATIC/LTIC pin for the Input Capture function
– BREAK pin for forcing a break condition on the
PWM outputs
– 12-bit input capture register (ATICR)
– Triggered by rising and falling edges
– Maskable IC interrupt
11.2.2 Main Features
■ Single Timer or Dual Timer mode with two 12-bit
upcounters (CNTR1/CNTR2) and two 12-bit
autoreload registers (ATR1/ATR2)
– Long range input capture
■ Break control
■ Flexible Clock control
■ Maskable overflow interrupts
Figure 34. Single Timer Mode (ENCNTR2 = 0)
12-bit Input Capture
ATIC
Edge Detection Circuit
CMP
Interrupt
Output Compare
OE0
PWM0
PWM1
PWM0 Duty Cycle Generator
Dead Time
Generator
12-bit Autoreload Register 1
12-bit Upcounter 1
OE1
PWM1 Duty Cycle Generator
Clock
Control
DTE bit
OE2
OE3
PWM2 Duty Cycle Generator
PWM3 Duty Cycle Generator
PWM2
PWM3
BPEN bit
OVF1 Interrupt
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ST7L34, ST7L35, ST7L38, ST7L39
DUAL 12-BIT AUTORELOAD TIMER 3 (cont’d)
Figure 35. Dual Timer Mode (ENCNTR2 = 1)
12-bit Input Capture
ATIC
Edge Detection Circuit
CMP
Interrupt
Output Compare
OE0
OE1
12-bit Autoreload Register 1
PWM0 Duty Cycle Generator
PWM1 Duty Cycle Generator
PWM0
PWM1
Dead Time
Generator
12-bit Upcounter 1
OVF1 interrupt
OVF2 interrupt
Clock
Control
DTE bit
OE2
OE3
PWM2 Duty Cycle Generator
PWM3 Duty Cycle Generator
PWM2
PWM3
12-bit Upcounter 2
12-bit Autoreload Register 2
BPEN bit
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ST7L34, ST7L35, ST7L38, ST7L39
DUAL 12-BIT AUTORELOAD TIMER 3 (cont’d)
11.2.3 Functional Description
11.2.3.1 PWM Mode
matches the active DCRx value the PWMx signals
are set to a low level. To obtain a signal on a
PWMx pin, the contents of the corresponding ac-
tive DCRx register must be greater than the con-
tents of the ATR register.
This mode allows up to four Pulse Width Modulat-
ed signals to be generated on the PWMx output
pins.
Note for ROM devices only: The PWM can be
enabled/disabled only in overflow ISR, otherwise
the first pulse of PWM can be different from ex-
pected one because no force overflow function is
present.
The maximum value of ATR is 4094 because it
must be lower than the DCR value which must be
4095 in this case.
PWM Frequency
The four PWM signals can have the same fre-
quency (f
) or can have two different frequen-
PWM
cies. This is selected by the ENCNTR2 bit which
enables single timer or dual timer mode (see Fig-
ure 34 on page 53 and Figure 35 on page 54).
The frequency is controlled by the counter period
and the ATR register value. In dual timer mode,
PWM2 and PWM3 can be generated with a differ-
ent frequency controlled by CNTR2 and ATR2.
Polarity Inversion
The polarity bits can be used to invert any of the
four output signals. The inversion is synchronized
with the counter overflow if the corresponding
transfer bit in the ATCSR2 register is set (reset
value). See Figure 36.
f
= f
/ (4096 - ATR)
PWM
COUNTER
Following the above formula,
– If f
f
is 4 MHz, the maximum value of
COUNTER
PWM
is 2 MHz (ATR register value = 4094), the
Figure 36. PWM Polarity Inversion
minimum value is 1 kHz (ATR register value = 0).
inverter
PWMx
Duty Cycle
PWMx
PIN
The duty cycle is selected by programming the
DCRx registers. These are preload registers. The
DCRx values are transferred in Active duty cycle
registers after an overflow event if the correspond-
ing transfer bit (TRANx bit) is set.
PWMxCSR Register
OPx
The TRAN1 bit controls the PWMx outputs driven
by counter 1 and the TRAN2 bit controls the
PWMx outputs driven by counter 2.
DFF
TRANx
ATCSR2 Register
PWM generation and output compare are done by
comparing these active DCRx values with the
counter.
counter
overflow
The Data Flip Flop (DFF) applies the polarity inver-
sion when triggered by the counter overflow input.
The maximum available resolution for the PWMx
duty cycle is:
Output Control
Resolution = 1 / (4096 - ATR)
The PWMx output signals can be enabled or disa-
bled using the OEx bits in the PWMCR register.
where ATR is equal to 0. With this maximum reso-
lution, 0% and 100% duty cycle can be obtained
by changing the polarity.
At reset, the counter starts counting from 0.
When an upcounter overflow occurs (OVF event),
the preloaded Duty cycle values are transferred to
the active Duty Cycle registers and the PWMx sig-
nals are set to a high level. When the upcounter
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ST7L34, ST7L35, ST7L38, ST7L39
DUAL 12-BIT AUTORELOAD TIMER 3 (cont’d)
Figure 37. PWM Function
4095
DUTY CYCLE
REGISTER
(DCRx)
AUTORELOAD
REGISTER
(ATR)
000
t
WITH OE = 1
AND OPx = 0
WITH OE = 1
AND OPx = 1
Figure 38. PWM Signal from 0% to 100% Duty Cycle
f
COUNTER
ATR= FFDh
FFFh
COUNTER
FFDh
FFEh
FFDh
FFEh
FFFh
FFDh
FFEh
DCRx=000h
DCRx=FFDh
DCRx=FFEh
DCRx=000h
t
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ST7L34, ST7L35, ST7L38, ST7L39
DUAL 12-BIT AUTORELOAD TIMER 3 (cont’d)
Dead Time Generation
Notes:
A dead time can be inserted between PWM0 and
PWM1 using the DTGR register. This is required
for half-bridge driving where PWM signals must
not be overlapped. The non-overlapping PWM0/
PWM1 signals are generated through a program-
mable dead time by setting the DTE bit.
1. Dead time is generated only when DTE = 1 and
DT[6:0] ≠ 0. If DTE is set and DT[6:0] = 0, PWM
output signals will be at their reset state.
2. Half-bridge driving is possible only if polarities of
PWM0 and PWM1 are not inverted, that is, if OP0
and OP1 are not set. If polarity is inverted, overlap-
ping PWM0/PWM1 signals will be generated.
Dead time value = DT[6:0] x Tcounter1
DTGR[7:0] is buffered inside so as to avoid de-
forming the current PWM cycle. The DTGR effect
will take place only after an overflow.
Figure 39. Dead Time Generation
T
counter1
CK_CNTR1
CNTR1
DCR0
DCR0+1
OVF
ATR1
counter = DCR0
PWM 0
PWM 1
counter = DCR1
T
dt
PWM 0
PWM 1
T
dt
T = DT[6:0] x T
dt
counter1
In the above example, when the DTE bit is set:
With this programmable delay (Tdt), the PWM0
and PWM1 signals which are generated are not
overlapped.
– PWM goes low at DCR0 match and goes high at
ATR1+Tdt
– PWM1 goes high at DCR0+Tdt and goes low at
ATR match.
57/168
1
ST7L34, ST7L35, ST7L38, ST7L39
DUAL 12-BIT AUTORELOAD TIMER 3 (cont’d)
Break Function
– The break pattern (PWM[3:0] bits in the BREAK-
CR) is forced directly on the PWMx output pins
(after the inverter).
The break function can be used to perform an
emergency shutdown of the application being driv-
en by the PWM signals.
– The 12-bit PWM counter CNTR1 is put to its re-
set value, that is, 00h.
The break function is activated by the external
BREAK pin (active low). In order to use the
BREAK pin it must be previously enabled by soft-
ware setting the BPEN bit in the BREAKCR regis-
ter.
– The 12-bit PWM counter CNTR2 is put to its re-
set value, that is, 00h.
– ATR1, ATR2, Preload and Active DCRx are put
to their reset values.
When a low level is detected on the BREAK pin,
the BA bit is set and the break function is activat-
ed. In this case, the four PWM signals are
stopped.
– The PWMCR register is reset.
– Counters stop counting.
When the break function is deactivated after ap-
plying the break (BA bit goes from 1 to 0 by soft-
ware):
Software can set the BA bit to activate the break
function without using the BREAK pin.
– The control of the four PWM outputs is trans-
ferred to the port registers.
When the break function is activated (BA bit = 1):
Figure 40. Block Diagram of Break Function
BREAK pin (Active Low)
BREAKCR Register
BPEN PWM3 PWM2 PWM1 PWM0
BA
PWM0
PWM1
PWM2
PWM3
1
PWM0
PWM1
PWM2
PWM3
0
When BA is set:
(Inverters)
PWM counter -> Reset value
ATRx & DCRx -> Reset value
PWM Mode -> Reset value
Note:
The BREAK pin value is latched by the BA bit.
58/168
1
ST7L34, ST7L35, ST7L38, ST7L39
DUAL 12-BIT AUTORELOAD TIMER 3 (cont’d)
11.2.3.2 Output Compare Mode
in Dual Timer mode, the counter 1 is compared
with DCR0 or DCR1.
To use this function, load a 12-bit value in the
Preload DCRxH and DCRxL registers.
Notes:
When the 12-bit upcounter (CNTR1) reaches the
value stored in the Active DCRxH and DCRxL reg-
isters, the CMPFx bit in the PWMxCSR register is
set and an interrupt request is generated if the
CMPIE bit is set.
1. The output compare function is only available
for DCRx values other than 0 (reset value).
2. Duty cycle registers are buffered internally. The
CPU writes in Preload Duty Cycle Registers and
these values are transferred in Active Duty Cycle
Registers after an overflow event if the corre-
sponding transfer bit (TRAN1 bit) is set. Output
compare is done by comparing these active DCRx
values with the counter.
The output compare function is always performed
on CNTR1 in both Single Timer mode and Dual
Timer mode and never on CNTR2. The difference
is that in Single Timer mode the counter 1 can be
compared with any of the four DCR registers and
Figure 41. Block Diagram of Output Compare Mode (Single Timer)
DCRx
PRELOAD DUTY CYCLE REGx
(ATCSR2) TRAN1
(ATCSR)
OVF
ACTIVE DUTY CYCLE REGx
CNTR1
OUTPUT COMPARE CIRCUIT
COUNTER 1
CMPFx (PWMxCSR)
CMPIE (ATCSR)
CMP
INTERRUPT REQUEST
59/168
1
ST7L34, ST7L35, ST7L38, ST7L39
DUAL 12-BIT AUTORELOAD TIMER 3 (cont’d)
11.2.3.3 Input Capture Mode
The 12-bit ATICR register is used to latch the val-
ue of the 12-bit free running upcounter CNTR1 af-
ter a rising or falling edge is detected on the ATIC
pin. When an input capture occurs, the ICF bit is
set and the ATICR register contains the value of
the free running upcounter. An IC interrupt is gen-
erated if the ICIE bit is set. The ICF bit is reset by
reading the ATICRH/ATICRL register when the
ICF bit is set. The ATICR is a read only register
and always contains the free running upcounter
value which corresponds to the most recent input
capture. Any further input capture is inhibited while
the ICF bit is set.
Figure 42. Block Diagram of Input Capture Mode
ATIC
12-bit INPUT CAPTURE REGISTER
ATICR
ATCSR
IC INTERRUPT
REQUEST
ICF
ICIE
CK1
CK0
f
LTIMER
(1ms
timebase
@ 8 MHz)
12-bit UPCOUNTER1
12-bit AUTORELOAD REGISTER
CNTR1
ATR1
f
CPU
OFF
Figure 43. Input Capture Timing Diagram
f
COUNTER
COUNTER1
ATIC PIN
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
INTERRUPT
ATICR READ
INTERRUPT
ICF FLAG
09h
xxh
04h
t
60/168
1
ST7L34, ST7L35, ST7L38, ST7L39
DUAL 12-BIT AUTORELOAD TIMER 3 (cont’d)
■ Long input capture
– The signal to be captured is connected to LTIC
pin
Pulses that last between 8µs and 2s can be meas-
ured with an accuracy of 4µs if f
following conditions:
= 8 MHz in the
– Input Capture registers LTICR, ATICRH and
ATICRL are read
OSC
– The 12-bit AT3 Timer is clocked by the Lite Timer
(RTC pulse: CK[1:0] = 01 in the ATCSR register)
This configuration allows to cascade the Lite Timer
and the 12-bit AT3 Timer to get a 20-bit input cap-
ture value. Refer to Figure 44.
– The ICS bit in the ATCSR2 register is set so that
the LTIC pin is used to trigger the AT3 Timer cap-
ture.
Figure 44. Long Range Input Capture Block Diagram
LTICR
8 LSB bits
8-bit Input Capture Register
fOSC/32
8-bit Timebase Counter1
LITE TIMER
20
12-bit ARTIMER
cascaded
bits
ATR1
12-bit AutoReload Register
fLTIMER
CNTR1
fCPU
OFF
ICS
12-bit Upcounter1
LTIC
ATIC
ATICR
1
0
12 MSB bits
12-bit Input Capture Register
Notes:
And then set the ICIE bit of desired interrupt.
1. Since the input capture flags (ICF) for both tim-
ers (AT3 Timer and LT Timer) are set when signal
transition occurs, software must mask one inter-
rupt by clearing the corresponding ICIE bit before
setting the ICS bit.
3. How to compute a pulse length with long input
capture feature.
As both timers are used, computing a pulse length
is not straight-forward. The procedure is as fol-
lows:
2. If the ICS bit changes (from 0 to 1 or from 1 to
0), a spurious transition might occur on the input
capture signal because of different values on LTIC
and ATIC. To avoid this situation, it is recommend-
ed to do as follows:
– At the first input capture on the rising edge of the
pulse, we assume that values in the registers are
as follows:
LTICR = LT1
ATICRH = ATH1
ATICRL = ATL1
Hence ATICR1 [11:0] = ATH1 & ATL1
First, reset both ICIE bits.
Then set the ICS bit.
Reset both ICF bits.
Refer to Figure 45.
61/168
1
ST7L34, ST7L35, ST7L38, ST7L39
DUAL 12-BIT AUTORELOAD TIMER 3 (cont’d)
– At the second input capture on the falling edge of
the pulse, we assume that the values in the reg-
isters are as follows:
ATICRL = ATL2
Hence ATICR2 [11:0] = ATH2 & ATL2
Now pulse width P between first capture and sec-
ond capture will be:
P = decimal (F9 – LT1 + LT2 + 1) * 0.004ms + dec-
imal (ATICR2 - ATICR1 – 1) * 1ms
LTICR = LT2
ATICRH = ATH2
Figure 45. Long Range Input Capture Timing Diagram
f
OSC/32
_ _ _
_ _ _
_ _ _
_ _ _
_ _ _
TB Counter1
CNTR1
F9h
00h
LT1
F9h
00h
LT2
_ _ _
_ _ _
ATH1 & ATL1
ATH2 & ATL2
LTIC
00h
0h
LT1
LT2
LTICR
ATH2
ATH1
ATL1
ATICRH
ATICRL
00h
ATL2
ATICR = ATICRH[3:0] & ATICRL[7:0]
11.2.4 Low Power Modes
11.2.5 Interrupts
Mode
SLOW
WAIT
Description
Exit
from
ACTIVE
HALT
Enable Exit
Control from from
Exit
Interrupt Event
The input frequency is divided by 32
No effect on AT timer
1)
Event
Flag
Bit
OVF1 OVFIE1 Yes
ICF ICIE Yes
WAIT HALT
ACTIVE
HALT
AT timer halted except if CK0 = 1,
CK1 = 0 and OVFIE = 1
Overflow
Event
2)
No
Yes
HALT
AT timer halted
AT3 IC
Event
No
No
No
No
CMP Event CMPFx CMPIE Yes
Notes:
1. The CMP and AT3 IC events are connected to the
same interrupt vector. The OVF event is mapped on a
separate vector (see Interrupts chapter). They generate
an interrupt if the enable bit is set in the ATCSR register
and the interrupt mask in the CC register is reset (RIM in-
struction).
2. Only if CK0 = 1 and CK1 = 0 (f
= f
)
COUNTER
LTIMER
62/168
1
ST7L34, ST7L35, ST7L38, ST7L39
DUAL 12-BIT AUTORELOAD TIMER 3 (cont’d)
11.2.6 Register Description
Bit 1 = OVFIE1 Overflow Interrupt Enable
This bit is read/write by software and cleared by
hardware after a reset.
TIMER CONTROL/STATUS REGISTER
(ATCSR)
Read / Write
Reset Value: 0x00 0000 (x0h)
0: Overflow interrupt disabled
1: Overflow interrupt enabled
7
6
0
Bit 0 = CMPIE Compare Interrupt Enable
This bit is read/write by software and cleared by
hardware after a reset. It can be used to mask the
interrupt generated when any of the CMPFx bit is
set.
0: Output compare interrupt disabled
1: Output compare interrupt enabled
0
ICF
ICIE
CK1
CK0 OVF1 OVFIE1 CMPIE
Bit 7 = Reserved
Bit 6 = ICF Input Capture Flag
This bit is set by hardware and cleared by software
by reading the ATICR register (a read access to
ATICRH or ATICRL will clear this flag). Writing to
this bit does not change the bit value.
0: No input capture
COUNTER REGISTER 1 HIGH (CNTR1H)
Read only
Reset Value: 0000 0000 (000h)
15
8
1: An input capture has occurred
CNTR1_ CNTR1_ CNTR1_ CNTR1_
0
0
0
0
11
10
9
8
Bit 5 = ICIE IC Interrupt Enable
This bit is set and cleared by software.
0: Input capture interrupt disabled
1: Input capture interrupt enabled
COUNTER REGISTER 1 LOW (CNTR1L)
Read only
Reset Value: 0000 0000 (000h)
7
0
Bits 4:3 = CK[1:0] Counter Clock Selection
These bits are set and cleared by software and
cleared by hardware after a reset. They select the
clock frequency of the counter.
CNTR1_ CNTR1_ CNTR1_ CNTR1_ CNTR1_ CNTR1_ CNTR1_ CNTR1_
7
6
5
4
3
2
1
0
Bits 15:12 = Reserved
Counter Clock Selection
CK1 CK0
OFF
OFF
0
1
0
1
0
1
1
0
Bits 11:0 = CNTR1[11:0] Counter Value
This 12-bit register is read by software and cleared
by hardware after a reset. The counter is incre-
mented continuously as soon as a counter clock is
selected. To obtain the 12-bit value, software
should read the counter value in two consecutive
read operations. The CNTR1H register can be in-
cremented between the two reads, and in order to
f
(1ms timebase @ 8 MHz)
LTIMER
f
CPU
Bit 2 = OVF1 Overflow Flag
This bit is set by hardware and cleared by software
by reading the TCSR register. It indicates the tran-
sition of the counter1 CNTR1 from FFh to ATR1
value.
be accurate when f
= f
, the software
TIMER
CPU
should take this into account when CNTR1L and
CNTR1H are read. If CNTR1L is close to its high-
est value, CNTR1H could be incremented before it
is read.
0: No counter overflow occurred
1: Counter overflow occurred
When a counter overflow occurs, the counter re-
starts from the value specified in the ATR1 regis-
ter.
63/168
1
ST7L34, ST7L35, ST7L38, ST7L39
DUAL 12-BIT AUTORELOAD TIMER 3 (cont’d)
AUTORELOAD REGISTER 1 HIGH (ATR1H)
Read / Write
PWMx CONTROL/STATUS REGISTER
(PWMxCSR)
Reset Value: 0000 0000 (00h)
Read / Write
Reset Value: 0000 0000 (00h)
15
8
7
0
0
0
0
0
ATR11 ATR10 ATR9 ATR8
0
0
0
0
0
0
OPx CMPFx
AUTORELOAD REGISTER 1 LOW (ATR1L)
Read / Write
Reset Value: 0000 0000 (00h)
Bits 7:2 = Reserved. Must be kept cleared.
7
0
Bit 1 = OPx PWMx Output Polarity
This bit is read/write by software and cleared by
hardware after a reset. This bit selects the polarity
of the PWM signal.
ATR7 ATR6 ATR5 ATR4 ATR3 ATR2 ATR1 ATR0
0: The PWM signal is not inverted.
1: The PWM signal is inverted.
Bits 11:0 = ATR1[11:0] Autoreload Register 1
This is a 12-bit register which is written by soft-
ware. The ATR1 register value is automatically
loaded into the upcounter CNTR1 when an over-
flow occurs. The register value is used to set the
PWM frequency.
Bit 0 = CMPFx PWMx Compare Flag
This bit is set by hardware and cleared by software
by reading the PWMxCSR register. It indicates
that the upcounter value matches the Active DCRx
register value.
0: Upcounter value does not match DCRx value.
1: Upcounter value matches DCRx value.
PWM OUTPUT CONTROL REGISTER
(PWMCR)
Read/Write
Reset Value: 0000 0000 (00h)
BREAK CONTROL REGISTER (BREAKCR)
Read/Write
Reset Value: 0000 0000 (00h)
7
0
0
OE3
0
OE2
0
OE1
0
OE0
7
0
0
0
BA
BPEN PWM3 PWM2 PWM1 PWM0
Bits 7:0 = OE[3:0] PWMx output enable
These bits are set and cleared by software and
cleared by hardware after a reset.
0: PWM mode disabled. PWMx Output Alternate
Function disabled (I/O pin free for general pur-
pose I/O)
Bits 7:6 = Reserved. Forced by hardware to 0.
Bit 5 = BA Break Active
1: PWM mode enabled
This bit is read/write by software, cleared by hard-
ware after reset and set by hardware when the
BREAK pin is low. It activates/deactivates the
Break function.
0: Break not active
1: Break active
64/168
1
ST7L34, ST7L35, ST7L38, ST7L39
DUAL 12-BIT AUTORELOAD TIMER 3 (cont’d)
Bit 4 = BPEN Break Pin Enable
This bit is read/write by software and cleared by
hardware after Reset.
INPUT CAPTURE REGISTER HIGH (ATICRH)
Read only
Reset Value: 0000 0000 (00h)
0: Break pin disabled
15
8
1: Break pin enabled
0
0
0
0
ICR11 ICR10 ICR9 ICR8
Bits 3:0 = PWM[3:0] Break Pattern
These bits are read/write by software and cleared
by hardware after a reset. They are used to force
the four PWMx output signals into a stable state
when the Break function is active.
INPUT CAPTURE REGISTER LOW (ATICRL)
Read only
Reset Value: 0000 0000 (00h)
7
0
PWMx DUTY CYCLE REGISTER HIGH (DCRxH)
Read / Write
Reset Value: 0000 0000 (00h)
ICR7 ICR6 ICR5 ICR4 ICR3 ICR2 ICR1 ICR0
15
8
Bits 15:12 = Reserved
0
0
0
0
DCR11 DCR10 DCR9 DCR8
Bits 11:0 = ICR[11:0] Input Capture Data
This is a 12-bit register which is readable by soft-
ware and cleared by hardware after a reset. The
ATICR register contains captured the value of the
12-bit CNTR1 register when a rising or falling edge
occurs on the ATIC or LTIC pin (depending on
ICS). Capture will only be performed when the ICF
flag is cleared.
PWMx DUTY CYCLE REGISTER LOW (DCRxL)
Read / Write
Reset Value: 0000 0000 (00h)
7
0
TIMER CONTROL/STATUS REGISTER
(ATCSR2)
2
DCR7 DCR6 DCR5 DCR4 DCR3 DCR2 DCR1 DCR0
Read/Write
Reset Value: 0000 0011 (03h)
Bits 15:12 = Reserved
7
0
Bits 11:0 = DCRx[11:0] PWMx Duty Cycle Value
This 12-bit value is written by software. It defines
the duty cycle of the corresponding PWM output
signal (see Figure 37).
ENCNT
R2
0
0
ICS OVFIE2 OVF2
TRAN2 TRAN1
Bits 7:6 = Reserved. Forced by hardware to 0.
In PWM mode (OEx = 1 in the PWMCR register)
the DCR[11:0] bits define the duty cycle of the
PWMx output signal (see Figure 37). In Output
Compare mode, they define the value to be com-
pared with the 12-bit upcounter value.
Bit 5 = ICS Input Capture Shorted
This bit is read/write by software. It allows the AT-
timer CNTR1 to use the LTIC pin for long input
capture.
0 : ATIC for CNTR1 input capture
1 : LTIC for CNTR1 input capture
65/168
1
ST7L34, ST7L35, ST7L38, ST7L39
DUAL 12-BIT AUTORELOAD TIMER 3 (cont’d)
Bit 4 = OVFIE2 Overflow interrupt 2 enable
This bit is read/write by software and controls the
overflow interrupt of counter2.
AUTORELOAD REGISTER 2 HIGH (ATR2H)
Read / Write
Reset Value: 0000 0000 (00h)
0: Overflow interrupt disabled
15
8
1: Overflow interrupt enabled
0
0
0
0
ATR11 ATR10 ATR9 ATR8
Bit 3 = OVF2 Overflow Flag.
This bit is set by hardware and cleared by software
by reading the ATCSR2 register. It indicates the
transition of the counter2 from FFFh to ATR2 val-
ue.
0: No counter overflow occurred
1: Counter overflow occurred
AUTORELOAD REGISTER 2 LOW (ATR2L)
Read / Write
Reset Value: 0000 0000 (00h)
7
0
Bit 2 = ENCNTR2 Enable counter2
ATR7 ATR6 ATR5 ATR4 ATR3 ATR2 ATR1 ATR0
This bit is read/write by software and switches the
second counter CNTR2. If this bit is set, PWM2
and PWM3 will be generated using CNTR2.
0: CNTR2 stopped
Bits 11:0 = ATR2[11:0] Autoreload Register 2
This is a 12-bit register which is written by soft-
ware. The ATR2 register value is automatically
loaded into the upcounter CNTR2 when an over-
flow of CNTR2 occurs. The register value is used
to set the PWM2/PWM3 frequency when
ENCNTR2 is set.
1: CNTR2 starts running
Bit 1 = TRAN2 Transfer enable2
This bit is read/write by software, cleared by hard-
ware after each completed transfer and set by
hardware after reset. It controls the transfers on
CNTR2.
DEAD TIME GENERATOR REGISTER (DTGR)
It allows the value of the Preload DCRx registers
to be transferred to the Active DCRx registers after
the next overflow event.
Read/Write
Reset Value: 0000 0000 (00h)
The OPx bits are transferred to the shadow OPx
bits in the same way.
7
0
(Only DCR2/DCR3 can be controlled with this bit)
DTE
DT6
DT5
DT4
DT3
DT2
DT1
DT0
Bit 0 = TRAN1 Transfer enable1
Bit 7 = DTE Dead Time Enable
This bit is read/write by software, cleared by hard-
ware after each completed transfer and set by
hardware after reset. It controls the transfers on
CNTR1. It allows the value of the Preload DCRx
registers to be transferred to the Active DCRx reg-
isters after the next overflow event.
This bit is read/write by software. It enables a dead
time generation on PWM0/PWM1.
0: No dead time insertion
1: Dead time insertion enabled
The OPx bits are transferred to the shadow OPx
bits in the same way.
Bits 6:0 = DT[6:0] Dead Time Value
These bits are read/write by software. They define
the dead time inserted between PWM0/PWM1.
Dead time is calculated as follows:
Dead Time = DT[6:0] x Tcounter1
66/168
1
ST7L34, ST7L35, ST7L38, ST7L39
DUAL 12-BIT AUTORELOAD TIMER 3 (cont’d)
Table 16. Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
ATCSR
Reset Value
ICF
0
ICIE
0
CK1
0
CK0
0
OVF1
0
OVFIE1
0
CMPIE
0
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
0
0
CNTR1H
Reset Value
CNTR1_11 CNTR1_10 CNTR1_9 CNTR1_8
0
0
0
0
0
0
0
CNTR1L
Reset Value
CNTR1_7 CNTR1_6 CNTR1_5 CNTR1_4 CNTR1_3 CNTR1_2 CNTR1_1 CNTR1_0
0
0
0
0
0
0
0
0
ATR1H
Reset Value
ATR11
0
ATR10
0
ATR9
0
ATR8
0
0
0
0
0
ATR1L
Reset Value
ATR7
0
ATR6
0
ATR5
0
ATR4
0
ATR3
0
ATR2
0
ATR1
0
ATR0
0
PWMCR
Reset Value
OE3
0
OE2
0
OE1
0
OE0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PWM0CSR
Reset Value
OP0
0
CMPF0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PWM1CSR
Reset Value
OP1
0
CMPF1
0
PWM2CSR
Reset Value
OP2
0
CMPF2
0
PWM3CSR
Reset Value
OP3
0
CMPF3
0
DCR0H
Reset Value
DCR11
0
DCR10
0
DCR9
0
DCR8
0
DCR0L
Reset Value
DCR7
0
DCR6
0
DCR5
0
DCR4
0
DCR3
0
DCR2
0
DCR1
0
DCR0
0
DCR1H
Reset Value
DCR11
0
DCR10
0
DCR9
0
DCR8
0
0
0
0
0
DCR1L
Reset Value
DCR7
0
DCR6
0
DCR5
0
DCR4
0
DCR3
0
DCR2
0
DCR1
0
DCR0
0
DCR2H
Reset Value
DCR11
0
DCR10
0
DCR9
0
DCR8
0
0
0
0
0
DCR2L
Reset Value
DCR7
0
DCR6
0
DCR5
0
DCR4
0
DCR3
0
DCR2
0
DCR1
0
DCR0
0
DCR3H
Reset Value
DCR11
0
DCR10
0
DCR9
0
DCR8
0
0
0
0
0
DCR3L
Reset Value
DCR7
0
DCR6
0
DCR5
0
DCR4
0
DCR3
0
DCR2
0
DCR1
0
DCR0
0
ATICRH
Reset Value
ICR11
0
ICR10
0
ICR9
0
ICR8
0
0
0
0
0
ATICRL
Reset Value
ICR7
0
ICR6
0
ICR5
0
ICR4
0
ICR3
0
ICR2
0
ICR1
0
ICR0
0
67/168
1
ST7L34, ST7L35, ST7L38, ST7L39
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
ICS
0
OVFIE2
0
OVF2
0
ENCNTR2 TRAN2
TRAN1
1
ATCSR2
Reset Value
21
0
0
0
1
BREAKCR
Reset Value
BA
0
BPEN
0
PWM3
0
PWM2
0
PWM1
0
PWM0
0
22
23
24
0
0
0
0
ATR2H
Reset Value
ATR11
0
ATR10
0
ATR9
0
ATR8
0
0
0
ATR2L
Reset Value
ATR7
0
ATR6
0
ATR5
0
ATR4
0
ATR3
0
ATR2
0
ATR1
0
ATR0
0
DTE
0
DT6
0
DT5
0
DT4
0
DT3
0
DT2
0
DT1
0
DT0
0
DTGR
Reset Value
25
68/168
1
ST7L34, ST7L35, ST7L38, ST7L39
ON-CHIP PERIPHERALS (cont’d)
11.3 LITE TIMER 2 (LT2)
11.3.1 Introduction
– One 8-bit upcounter with autoreload and pro-
grammable timebase period from 4µs to
The Lite Timer is used for general-purpose timing
functions. It is based on two free-running 8-bit up-
counters and an 8-bit input capture register.
1.024ms in 4µs increments (@ 8 MHz f
– 2 Maskable timebase interrupts
■ Input Capture
)
OSC
– 8-bit input capture register (LTICR)
– Maskable interrupt with wakeup from Halt
11.3.2 Main Features
■ Realtime Clock (RTC)
Mode capability
– One 8-bit upcounter 1ms or 2ms timebase pe-
riod (@ 8 MHz f
)
OSC
Figure 46. Lite Timer 2 Block Diagram
f
/32
OSC
LTTB2
LTCNTR
Interrupt request
LTCSR2
8-bit TIMEBASE
COUNTER 2
8
0
0
0
0
0
0
TB2IE TB2F
LTARR
f
LTIMER
To 12-bit AT TImer
8-bit AUTORELOAD
REGISTER
/2
1
0
8-bit TIMEBASE
COUNTER 1
Timebase
1 or 2 ms
(@ 8 MHz
f
LTIMER
f
)
OSC
8
LTICR
8-bit
LTIC
INPUT CAPTURE
REGISTER
LTCSR1
ICIE
ICF
TB
TB1IE TB1F
LTTB1 INTERRUPT REQUEST
LTIC INTERRUPT REQUEST
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ST7L34, ST7L35, ST7L38, ST7L39
LITE TIMER 2 (LT2) (cont’d)
11.3.3 Functional Description
11.3.3.1 Timebase Counter 1
LTARR reload value. Software can write a new
value at anytime in the LTARR register, this value
will be automatically loaded in the counter when
the next overflow occurs.
The 8-bit value of Counter 1 cannot be read or
written by software. After an MCU reset, it starts
incrementing from 0 at a frequency of f
When Counter 2 overflows, the TB2F bit in the
LTCSR2 register is set by hardware and an inter-
rupt request is generated if the TB2IE bit is set.
The TB2F bit is cleared by software reading the
LTCSR2 register.
/32. An
OSC
overflow event occurs when the counter rolls over
from F9h to 00h. If f = 8 MHz, then the time pe-
OSC
riod between two counter overflow events is 1ms.
This period can be doubled by setting the TB bit in
the LTCSR1 register.
11.3.3.3 Input Capture
When Counter 1 overflows, the TB1F bit is set by
hardware and an interrupt request is generated if
the TB1IE bit is set. The TB1F bit is cleared by
software reading the LTCSR1 register.
The 8-bit input capture register is used to latch the
free-running upcounter (Counter 1) 1 after a rising
or falling edge is detected on the LTIC pin. When
an input capture occurs, the ICF bit is set and the
LTICR register contains the value of Counter 1. An
interrupt is generated if the ICIE bit is set. The ICF
bit is cleared by reading the LTICR register.
11.3.3.2 Timebase Counter 2
Counter 2 is an 8-bit autoreload upcounter. It can
be read by accessing the LTCNTR register. After
an MCU reset, it increments at a frequency of
The LTICR is a read-only register and always con-
tains the data from the last input capture. Input
capture is inhibited if the ICF bit is set.
f
/32 starting from the value stored in the
OSC
LTARR register. A counter overflow event occurs
when the counter rolls over from FFh to the
Figure 47. Input Capture Timing Diagram
4µs
(@ 8 MHz f
)
OSC
f
CPU
f
/32
OSC
CLEARED
BY S/W
READING
LTIC REGISTER
8-bit COUNTER 1
LTIC PIN
01h
02h
03h
04h
05h
06h
07h
ICF FLAG
07h
xxh
04h
LTICR REGISTER
t
70/168
1
ST7L34, ST7L35, ST7L38, ST7L39
LITE TIMER 2 (LT2) (cont’d)
11.3.4 Low Power Modes
11.3.6 Register Description
Mode
Description
No effect on Lite timer
(this peripheral is driven directly by
LITE TIMER CONTROL/STATUS REGISTER 2
(LTCSR2)
Read / Write
SLOW
Reset Value: 0x00 0000 (x0h)
f
/32)
OSC
WAIT
No effect on Lite timer
7
0
ACTIVE HALT
HALT
Lite timer stops counting
0
0
0
0
0
0
TB2IE TB2F
11.3.5 Interrupts
Bits 7:2 = Reserved. Must be kept cleared.
Exit
Enable Exit
Control from
Exit
from
Halt
Interrupt Event
from
Active
Halt
Event
Flag
Bit
Wait
Bit 1 = TB2IE Timebase 2 Interrupt enable
This bit is set and cleared by software.
0: Timebase (TB2) interrupt disabled
1: Timebase (TB2) interrupt enabled
Timebase 1
Event
TB1F TB1IE
TB2F TB2IE
Yes
Timebase 2
Event
Yes
No
No
IC Event
ICF
ICIE
Bit 0 = TB2F Timebase 2 Interrupt Flag
This bit is set by hardware and cleared by software
reading the LTCSR2 register. Writing to this bit
has no effect.
Note: The TBxF and ICF interrupt events are con-
nected to separate interrupt vectors (see Inter-
rupts chapter).
0: No Counter 2 overflow
1: A Counter 2 overflow has occurred
They generate an interrupt if the enable bit is set in
the LTCSR1 or LTCSR2 register and the interrupt
mask in the CC register is reset (RIM instruction).
LITE
TIMER
AUTORELOAD
REGISTER
(LTARR)
Read / Write
Reset Value: 0000 0000 (00h)
7
0
AR7
AR7
AR7
AR7
AR3
AR2
AR1
AR0
Bits 7:0 = AR[7:0] Counter 2 Reload Value
These bits register is read/write by software. The
LTARR value is automatically loaded into Counter
2 (LTCNTR) when an overflow occurs.
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1
ST7L34, ST7L35, ST7L38, ST7L39
LITE TIMER 2 (LT2) (cont’d)
LITE TIMER COUNTER 2 REGISTER (LTCNTR)
Read only
Bit 5 = TB Timebase period selection
This bit is set and cleared by software.
Reset Value: 0000 0000 (00h)
0: Timebase period = t
* 8000 (1ms @ 8 MHz)
OSC
1: Timebase period = t
MHz)
* 16000 (2ms @ 8
OSC
7
0
CNT7 CNT7 CNT7 CNT7 CNT3 CNT2 CNT1 CNT0
Bit 4 = TB1IE Timebase Interrupt enable
This bit is set and cleared by software.
0: Timebase (TB1) interrupt disabled
1: Timebase (TB1) interrupt enabled
Bits 7:0 = CNT[7:0] Counter 2 Reload Value
This register is read by software. The LTARR val-
ue is automatically loaded into Counter 2 (LTCN-
TR) when an overflow occurs.
Bit 3 = TB1F Timebase Interrupt Flag
This bit is set by hardware and cleared by software
reading the LTCSR register. Writing to this bit has
no effect.
0: No counter overflow
1: A counter overflow has occurred
LITE TIMER CONTROL/STATUS REGISTER 1
(LTCSR1)
Read / Write
Reset Value: 0x00 0000 (x0h)
7
0
-
Bits 2:0 = Reserved
ICIE
ICF
TB
TB1IE TB1F
-
-
LITE TIMER INPUT CAPTURE REGISTER
(LTICR)
Bit 7 = ICIE Interrupt Enable.
Read only
This bit is set and cleared by software.
0: Input Capture (IC) interrupt disabled
1: Input Capture (IC) interrupt enabled
Reset Value: 0000 0000 (00h)
7
0
ICR7 ICR6 ICR5 ICR4 ICR3 ICR2 ICR1 ICR0
Bit 6 = ICF Input Capture Flag
This bit is set by hardware and cleared by software
by reading the LTICR register. Writing to this bit
does not change the bit value.
Bits 7:0 = ICR[7:0] Input Capture Value
These bits are read by software and cleared by
hardware after a reset. If the ICF bit in the LTCSR
is cleared, the value of the 8-bit up-counter will be
captured when a rising or falling edge occurs on
the LTIC pin.
0: No input capture
1: An input capture has occurred
Note: After an MCU reset, software must initialize
the ICF bit by reading the LTICR register
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1
ST7L34, ST7L35, ST7L38, ST7L39
LITE TIMER 2 (LT2) (cont’d)
Table 17. Lite Timer Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
LTCSR2
Reset Value
TB2IE
0
TB2F
0
08
09
0A
0B
0C
0
0
0
0
0
0
LTARR
Reset Value
AR7
0
AR6
0
AR5
0
AR4
0
AR3
0
AR2
0
AR1
0
AR0
0
LTCNTR
Reset Value
CNT7
0
CNT6
0
CNT5
0
CNT4
0
CNT3
0
CNT2
0
CNT1
0
CNT0
0
LTCSR1
Reset Value
ICIE
0
ICF
x
TB
0
TB1IE
0
TB1F
0
0
0
0
LTICR
Reset Value
ICR7
0
ICR6
0
ICR5
0
ICR4
0
ICR3
0
ICR2
0
ICR1
0
ICR0
0
73/168
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ST7L34, ST7L35, ST7L38, ST7L39
ON-CHIP PERIPHERALS (cont’d)
11.4 SERIAL PERIPHERAL INTERFACE (SPI)
11.4.1 Introduction
11.4.3 General Description
The Serial Peripheral Interface (SPI) allows full-
duplex, synchronous, serial communication with
external devices. An SPI system may consist of a
master and one or more slaves or a system in
which devices may be either masters or slaves.
Figure 48 on page 75 shows the serial peripheral
interface (SPI) block diagram. There are three reg-
isters:
– SPI Control Register (SPICR)
– SPI Control/Status Register (SPICSR)
– SPI Data Register (SPIDR)
11.4.2 Main Features
■ Full duplex synchronous transfers (on three
The SPI is connected to external devices through
four pins:
lines)
■ Simplex synchronous transfers (on two lines)
■ Master or slave operation
– MISO: Master In / Slave Out data
– MOSI: Master Out / Slave In data
■ 6 master mode frequencies (f
/4 max.)
CPU
– SCK: Serial Clock out by SPI masters and in-
put by SPI slaves
■ f
/2 max. slave mode frequency (see note)
CPU
■ SS Management by software or hardware
■ Programmable clock polarity and phase
■ End of transfer interrupt flag
– SS: Slave select:
This input signal acts as a ‘chip select’ to let
the SPI master communicate with slaves indi-
vidually and to avoid contention on the data
lines. Slave SS inputs can be driven by stand-
ard I/O ports on the master Device.
■ Write collision, Master Mode Fault and Overrun
flags
Note: In slave mode, continuous transmission is
not possible at maximum frequency due to the
software overhead for clearing status flags and to
initiate the next transmission sequence.
74/168
1
ST7L34, ST7L35, ST7L38, ST7L39
SERIAL PERIPHERAL INTERFACE (SPI) (cont’d)
Figure 48. Serial Peripheral Interface Block Diagram
Data/Address Bus
Read
SPIDR
Interrupt
request
Read Buffer
MOSI
7
0
SPICSR
MISO
8-bit Shift Register
SPIF WCOL OVR MODF
0
SOD SSM SSI
Write
SOD
bit
1
SS
SPI
STATE
0
SCK
CONTROL
7
0
SPICR
MSTR
SPR0
SPIE SPE SPR2
CPOL CPHA SPR1
MASTER
CONTROL
SERIAL CLOCK
GENERATOR
SS
75/168
1
ST7L34, ST7L35, ST7L38, ST7L39
SERIAL PERIPHERAL INTERFACE (cont’d)
11.4.3.1 Functional Description
the MISO pin. This implies full duplex communica-
tion with both data out and data in synchronized
with the same clock signal (which is provided by
the master device via the SCK pin).
A basic example of interconnections between a
single master and a single slave is illustrated in
Figure 49.
To use a single data line, the MISO and MOSI pins
must be connected at each node (in this case only
simplex communication is possible).
The MOSI pins are connected together and the
MISO pins are connected together. In this way
data is transferred serially between master and
slave (most significant bit first).
Four possible data/clock timing relationships may
be chosen (see Figure 52 on page 79) but master
and slave must be programmed with the same tim-
ing mode.
The communication is always initiated by the mas-
ter. When the master device transmits data to a
slave device via MOSI pin, the slave device re-
sponds by sending data to the master device via
Figure 49. Single Master/ Single Slave Application
SLAVE
MASTER
MSBit
LSBit
MSBit
LSBit
MISO
MOSI
MISO
MOSI
8-bit SHIFT REGISTER
8-bit SHIFT REGISTER
SPI
CLOCK
GENERATOR
SCK
SS
SCK
SS
+5V
Not used if SS is managed
by software
76/168
1
ST7L34, ST7L35, ST7L38, ST7L39
SERIAL PERIPHERAL INTERFACE (cont’d)
11.4.3.2 Slave Select Management
In Slave Mode:
As an alternative to using the SS pin to control the
Slave Select signal, the application can choose to
manage the Slave Select signal by software. This
is configured by the SSM bit in the SPICSR regis-
ter (see Figure 51).
There are two cases depending on the data/clock
timing relationship (see Figure 50):
If CPHA = 1 (data latched on second clock edge):
– SS internal must be held low during the entire
transmission. This implies that in single slave
applications the SS pin either can be tied to
In software management, the external SS pin is
free for other application uses and the internal SS
signal level is driven by writing to the SSI bit in the
SPICSR register.
V
, or made free for standard I/O by manag-
SS
ing the SS function by software (SSM = 1 and
SSI = 0 in the in the SPICSR register)
If CPHA = 0 (data latched on first clock edge):
In Master mode:
– SS internal must be held low during byte
transmission and pulled high between each
byte to allow the slave to write to the shift reg-
ister. If SS is not pulled high, a Write Collision
error will occur when the slave writes to the
shift register (see Section 11.4.5.3).
– SS internal must be held high continuously
Figure 50. Generic SS Timing Diagram
Byte 3
Byte 2
MOSI/MISO
Master SS
Byte 1
Slave SS
(if CPHA = 0)
Slave SS
(if CPHA = 1)
Figure 51. Hardware/Software Slave Select Management
SSM bit
SSI bit
1
0
SS internal
SS external pin
77/168
1
ST7L34, ST7L35, ST7L38, ST7L39
SERIAL PERIPHERAL INTERFACE (cont’d)
11.4.3.3 Master Mode Operation
Note: While the SPIF bit is set, all writes to the
SPIDR register are inhibited until the SPICSR reg-
ister is read.
In master mode, the serial clock is output on the
SCK pin. The clock frequency, polarity and phase
are configured by software (refer to the description
of the SPICSR register).
11.4.3.5 Slave Mode Operation
In slave mode, the serial clock is received on the
SCK pin from the master device.
Note: The idle state of SCK must correspond to
the polarity selected in the SPICSR register (by
pulling up SCK if CPOL = 1 or pulling down SCK if
CPOL = 0).
To operate the SPI in slave mode:
1. Write to the SPICSR register to perform the fol-
lowing actions:
How to operate the SPI in master mode
– Select the clock polarity and clock phase by
configuring the CPOL and CPHA bits (see
Figure 52).
To operate the SPI in master mode, perform the
following steps in order:
Note: The slave must have the same CPOL
1. Write to the SPICR register:
and CPHA settings as the master.
– Select the clock frequency by configuring the
– Manage the SS pin as described in Section
11.4.3.2 and Figure 50. If CPHA = 1 SS must
be held low continuously. If CPHA = 0 SS
must be held low during byte transmission and
pulled up between each byte to let the slave
write in the shift register.
SPR[2:0] bits.
– Select the clock polarity and clock phase by
configuring the CPOL and CPHA bits. Figure
52 shows the four possible configurations.
Note: The slave must have the same CPOL
and CPHA settings as the master.
2. Write to the SPICR register to clear the MSTR
bit and set the SPE bit to enable the SPI I/O
functions.
2. Write to the SPICSR register:
– Either set the SSM bit and set the SSI bit or
clear the SSM bit and tie the SS pin high for
the complete byte transmit sequence.
11.4.3.6 Slave Mode Transmit Sequence
When software writes to the SPIDR register, the
data byte is loaded into the 8-bit shift register and
then shifted out serially to the MISO pin most sig-
nificant bit first.
3. Write to the SPICR register:
– Set the MSTR and SPE bits
Note: MSTR and SPE bits remain set only if
SS is high).
The transmit sequence begins when the slave de-
vice receives the clock signal and the most signifi-
cant bit of the data on its MOSI pin.
Important note: if the SPICSR register is not writ-
ten first, the SPICR register setting (MSTR bit)
may be not taken into account.
When data transfer is complete:
– The SPIF bit is set by hardware.
The transmit sequence begins when software
writes a byte in the SPIDR register.
11.4.3.4 Master Mode Transmit Sequence
– An interrupt request is generated if SPIE bit is
set and interrupt mask in the CCR register is
cleared.
When software writes to the SPIDR register, the
data byte is loaded into the 8-bit shift register and
then shifted out serially to the MOSI pin most sig-
nificant bit first.
Clearing the SPIF bit is performed by the following
software sequence:
When data transfer is complete:
– The SPIF bit is set by hardware.
1. An access to the SPICSR register while the
SPIF bit is set
2. A write or a read to the SPIDR register
– An interrupt request is generated if the SPIE
bit is set and the interrupt mask in the CCR
register is cleared.
Notes: While the SPIF bit is set, all writes to the
SPIDR register are inhibited until the SPICSR reg-
ister is read.
Clearing the SPIF bit is performed by the following
software sequence:
The SPIF bit can be cleared during a second
transmission; however, it must be cleared before
the second SPIF bit in order to prevent an Overrun
condition (see Section 11.4.5.2).
1. An access to the SPICSR register while the
SPIF bit is set
2. A read to the SPIDR register
78/168
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ST7L34, ST7L35, ST7L38, ST7L39
SERIAL PERIPHERAL INTERFACE (cont’d)
11.4.4 Clock Phase and Clock Polarity
Figure 52 shows an SPI transfer with the four com-
binations of the CPHA and CPOL bits. The dia-
gram may be interpreted as a master or slave tim-
ing diagram where the SCK pin, the MISO pin and
the MOSI pin are directly connected between the
master and the slave device.
Four possible timing relationships may be chosen
by software, using the CPOL and CPHA bits (See
Figure 52).
Note: The idle state of SCK must correspond to
the polarity selected in the SPICSR register (by
pulling up SCK if CPOL = 1 or pulling down SCK if
CPOL = 0).
Note: If CPOL is changed at the communication
byte boundaries, the SPI must be disabled by re-
setting the SPE bit.
The combination of the CPOL clock polarity and
CPHA (clock phase) bits selects the data capture
clock edge.
Figure 52. Data Clock Timing Diagram
CPHA = 1
SCK
(CPOL = 1)
SCK
(CPOL = 0)
Bit 4
Bit 4
Bit3
Bit3
Bit 2
Bit 2
Bit 1
Bit 1
LSBit
LSBit
MSBit
MSBit
Bit 6
Bit 6
Bit 5
Bit 5
MISO
(from master)
MOSI
(from slave)
SS
(to slave)
CAPTURE STROBE
CPHA = 0
SCK
(CPOL = 1)
SCK
(CPOL = 0)
Bit 4
Bit 4
Bit3
Bit3
Bit 2
Bit 2
Bit 1
Bit 1
LSBit
LSBit
MISO
(from master)
MSBit
Bit 6
Bit 6
Bit 5
Bit 5
MOSI
(from slave)
MSBit
SS
(to slave)
CAPTURE STROBE
Note: This figure should not be used as a replacement for parametric information.
Refer to the Electrical Characteristics chapter.
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ST7L34, ST7L35, ST7L38, ST7L39
SERIAL PERIPHERAL INTERFACE (cont’d)
11.4.5 Error Flags
11.4.5.2 Overrun Condition (OVR)
11.4.5.1 Master Mode Fault (MODF)
An overrun condition occurs when the master de-
vice has sent a data byte and the slave device has
not cleared the SPIF bit issued from the previously
transmitted byte.
Master mode fault occurs when the master de-
vice’s SS pin is pulled low.
When a Master mode fault occurs:
When an Overrun occurs:
– The MODF bit is set and an SPI interrupt re-
quest is generated if the SPIE bit is set.
– The OVR bit is set and an interrupt request is
generated if the SPIE bit is set.
– The SPE bit is reset. This blocks all output
from the device and disables the SPI periph-
eral.
In this case, the receiver buffer contains the byte
sent after the SPIF bit was last cleared. A read to
the SPIDR register returns this byte. All other
bytes are lost.
– The MSTR bit is reset, thus forcing the device
into slave mode.
The OVR bit is cleared by reading the SPICSR
register.
Clearing the MODF bit is done through a software
sequence:
11.4.5.3 Write Collision Error (WCOL)
1. A read access to the SPICSR register while the
MODF bit is set.
A write collision occurs when the software tries to
write to the SPIDR register while a data transfer is
taking place with an external device. When this
happens, the transfer continues uninterrupted and
the software write will be unsuccessful.
2. A write to the SPICR register.
Notes: To avoid any conflicts in an application
with multiple slaves, the SS pin must be pulled
high during the MODF bit clearing sequence. The
SPE and MSTR bits may be restored to their orig-
inal state during or after this clearing sequence.
Write collisions can occur both in master and slave
mode. See also Section 11.4.3.2 Slave Select
Management.
Hardware does not allow the user to set the SPE
and MSTR bits while the MODF bit is set except in
the MODF bit clearing sequence.
Note: A "read collision" will never occur since the
received data byte is placed in a buffer in which
access is always synchronous with the CPU oper-
ation.
In a slave device, the MODF bit can not be set, but
in a multimaster configuration the device can be in
slave mode with the MODF bit set.
The WCOL bit in the SPICSR register is set if a
write collision occurs.
The MODF bit indicates that there might have
been a multimaster conflict and allows software to
handle this using an interrupt routine and either
perform a reset or return to an application default
state.
No SPI interrupt is generated when the WCOL bit
is set (the WCOL bit is a status flag only).
Clearing the WCOL bit is done through a software
sequence (see Figure 53).
Figure 53. Clearing the WCOL Bit (Write Collision Flag) Software Sequence
Clearing sequence after SPIF = 1 (end of a data byte transfer)
Read SPICSR
1st Step
RESULT
SPIF = 0
WCOL = 0
2nd Step
Read SPIDR
Clearing sequence before SPIF = 1 (during a data byte transfer)
Read SPICSR
1st Step
RESULT
Note: Writing to the SPIDR register in-
stead of reading it does not reset the
WCOL bit.
2nd Step
Read SPIDR
WCOL = 0
80/168
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ST7L34, ST7L35, ST7L38, ST7L39
SERIAL PERIPHERAL INTERFACE (cont’d)
11.4.5.4 Single Master and Multimaster
Configurations
For more security, the slave device may respond
to the master with the received data byte. Then the
master will receive the previous byte back from the
slave device if all MISO and MOSI pins are con-
nected and the slave has not written to its SPIDR
register.
There are two types of SPI systems:
– Single Master System
– Multimaster System
Other transmission security methods can use
ports for handshake lines or data bytes with com-
mand fields.
Single Master System
A typical single master system may be configured
using a device as the master and four devices as
slaves (see Figure 54).
Multimaster System
A multimaster system may also be configured by
the user. Transfer of master control could be im-
plemented using a handshake method through the
I/O ports or by an exchange of code messages
through the serial peripheral interface system.
The master device selects the individual slave de-
vices by using four pins of a parallel port to control
the four SS pins of the slave devices.
The SS pins are pulled high during reset since the
master device ports will be forced to be inputs at
that time, thus disabling the slave devices.
The multimaster system is principally handled by
the MSTR bit in the SPICR register and the MODF
bit in the SPICSR register.
Note: To prevent a bus conflict on the MISO line,
the master allows only one active slave device
during a transmission.
Figure 54. Single Master / Multiple Slave Configuration
SS
SS
SS
SS
SCK
Slave
SCK
Slave
Device
SCK
Slave
Device
SCK
Slave
Device
Device
MOSI MISO
MOSI MISO
MOSI MISO
MOSI MISO
MOSI MISO
SCK
Master
Device
5V
SS
81/168
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ST7L34, ST7L35, ST7L38, ST7L39
SERIAL PERIPHERAL INTERFACE (cont’d)
11.4.6 Low Power Modes
the SPI from HALT mode state to normal state. If
the SPI exits from Slave mode, it returns to normal
state immediately.
Mode
Description
No effect on SPI.
Caution: The SPI can wake up the device from
HALT mode only if the Slave Select signal (exter-
nal SS pin or the SSI bit in the SPICSR register) is
low when the device enters HALT mode. So, if
Slave selection is configured as external (see Sec-
tion 11.4.3.2), make sure the master drives a low
level on the SS pin when the slave enters HALT
mode.
WAIT
SPI interrupt events cause the device to exit
from WAIT mode.
SPI registers are frozen.
In HALT mode, the SPI is inactive. SPI oper-
ation resumes when the device is woken up
by an interrupt with “exit from HALT mode”
capability. The data received is subsequently
read from the SPIDR register when the soft-
ware is running (interrupt vector fetching). If
several data are received before the wake-
up event, then an overrun error is generated.
This error can be detected after the fetch of
the interrupt routine that woke up the Device.
HALT
11.4.7 Interrupts
Enable
Control from
Bit
Exit
Exit
from
Halt
Event
Flag
Interrupt Event
Wait
SPI End of
Transfer Event
SPIF
Yes
11.4.6.1 Using the SPI to wake up the device
from Halt mode
Master Mode
Fault Event
SPIE
Yes
MODF
OVR
No
In slave configuration, the SPI is able to wake up
the device from HALT mode through a SPIF inter-
rupt. The data received is subsequently read from
the SPIDR register when the software is running
(interrupt vector fetch). If multiple data transfers
have been performed before software clears the
SPIF bit, then the OVR bit is set by hardware.
Overrun Error
Note: The SPI interrupt events are connected to
the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding
Enable Control Bit is set and the interrupt mask in
the CC register is reset (RIM instruction).
Note: When waking up from HALT mode, if the
SPI remains in Slave mode, it is recommended to
perform an extra communications cycle to bring
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11.4.8 Register Description
SPI CONTROL REGISTER (SPICR)
Read/Write
Bit 3 = CPOL Clock Polarity
This bit is set and cleared by software. This bit de-
termines the idle state of the serial Clock. The
CPOL bit affects both the master and slave
modes.
Reset Value: 0000 xxxx (0xh)
7
0
0: SCK pin has a low level idle state
1: SCK pin has a high level idle state
SPIE
SPE SPR2 MSTR CPOL CPHA SPR1 SPR0
Note: If CPOL is changed at the communication
byte boundaries, the SPI must be disabled by re-
setting the SPE bit.
Bit 7 = SPIE Serial Peripheral Interrupt Enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SPI interrupt is generated whenever an End
of Transfer event, Master Mode Fault or Over-
run error occurs (SPIF = 1, MODF = 1 or
OVR = 1 in the SPICSR register)
Bit 2 = CPHA Clock Phase
This bit is set and cleared by software.
0: The first clock transition is the first data capture
edge.
1: The second clock transition is the first capture
edge.
Bit 6 = SPE Serial Peripheral Output Enable
This bit is set and cleared by software. It is also
cleared by hardware when, in master mode,
SS = 0 (see Section 11.4.5.1 Master Mode Fault
(MODF)). The SPE bit is cleared by reset, so the
SPI peripheral is not initially connected to the ex-
ternal pins.
Note: The slave must have the same CPOL and
CPHA settings as the master.
Bits 1:0 = SPR[1:0] Serial Clock Frequency
These bits are set and cleared by software. Used
with the SPR2 bit, they select the baud rate of the
SPI serial clock SCK output by the SPI in master
mode.
0: I/O pins free for general purpose I/O
1: SPI I/O pin alternate functions enabled
Note: These 2 bits have no effect in slave mode.
Bit 5 = SPR2 Divider Enable
Table 18. SPI Master Mode SCK Frequency
This bit is set and cleared by software and is
cleared by reset. It is used with the SPR[1:0] bits to
set the baud rate. Refer to Table 18 SPI Master
Mode SCK Frequency.
Serial Clock
SPR2
SPR1
SPR0
f
f
/4
/8
1
CPU
CPU
0
1
0
1
0
0: Divider by 2 enabled
1: Divider by 2 disabled
0
1
0
f
f
f
/16
/32
/64
CPU
CPU
CPU
Note: This bit has no effect in slave mode.
1
f
/128
CPU
Bit 4 = MSTR Master Mode
This bit is set and cleared by software. It is also
cleared by hardware when, in master mode,
SS = 0 (see Section 11.4.5.1 Master Mode Fault
(MODF)).
0: Slave mode
1: Master mode. The function of the SCK pin
changes from an input to an output and the func-
tions of the MISO and MOSI pins are reversed.
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SERIAL PERIPHERAL INTERFACE (cont’d)
SPI CONTROL/STATUS REGISTER (SPICSR)
Read/Write (some bits Read Only)
Reset Value: 0000 0000 (00h)
Bit 2 = SOD SPI Output Disable
This bit is set and cleared by software. When set, it
disables the alternate function of the SPI output
(MOSI in master mode / MISO in slave mode)
0: SPI output enabled (if SPE = 1)
7
0
SPIF WCOL OVR MODF
-
SOD
SSM
SSI
1: SPI output disabled
Bit 7 = SPIF Serial Peripheral Data Transfer Flag
(Read only)
Bit 1 = SSM SS Management
This bit is set and cleared by software. When set, it
disables the alternate function of the SPI SS pin
and uses the SSI bit value instead. See Section
11.4.3.2 Slave Select Management.
0: Hardware management (SS managed by exter-
nal pin)
This bit is set by hardware when a transfer has
been completed. An interrupt is generated if
SPIE = 1 in the SPICR register. It is cleared by
a software sequence (an access to the SPICSR
register followed by a write or a read to the
SPIDR register).
1: Software management (internal SS signal con-
trolled by SSI bit. External SS pin free for gener-
al-purpose I/O)
0: Data transfer is in progress or the flag has been
cleared.
1: Data transfer between the device and an exter-
nal device has been completed.
Bit 0 = SSI SS Internal Mode
Note: While the SPIF bit is set, all writes to the
SPIDR register are inhibited until the SPICSR reg-
ister is read.
This bit is set and cleared by software. It acts as a
‘chip select’ by controlling the level of the SS slave
select signal when the SSM bit is set.
0: Slave selected
Bit 6 = WCOL Write Collision status (Read only)
This bit is set by hardware when a write to the
SPIDR register is done during a transmit se-
quence. It is cleared by a software sequence (see
Figure 53).
0: No write collision occurred
1: A write collision has been detected
1: Slave deselected
SPI DATA I/O REGISTER (SPIDR)
Read/Write
Reset Value: Undefined
7
0
D7
D6
D5
D4
D3
D2
D1
D0
Bit 5 = OVR SPI Overrun error (Read only)
This bit is set by hardware when the byte currently
being received in the shift register is ready to be
transferred into the SPIDR register while SPIF = 1
(see Section 11.4.5.2). An interrupt is generated if
SPIE = 1 in the SPICR register. The OVR bit is
cleared by software reading the SPICSR register.
0: No overrun error
The SPIDR register is used to transmit and receive
data on the serial bus. In a master device, a write
to this register will initiate transmission/reception
of another byte.
Notes: During the last clock cycle the SPIF bit is
set, a copy of the received data byte in the shift
register is moved to a buffer. When the user reads
the serial peripheral data I/O register, the buffer is
actually being read.
1: Overrun error detected
Bit 4 = MODF Mode Fault flag (Read only)
This bit is set by hardware when the SS pin is
pulled low in master mode (see Section 11.4.5.1
Master Mode Fault (MODF)). An SPI interrupt can
be generated if SPIE = 1 in the SPICR register.
This bit is cleared by a software sequence (An ac-
cess to the SPICSR register while MODF = 1 fol-
lowed by a write to the SPICR register).
While the SPIF bit is set, all writes to the SPIDR
register are inhibited until the SPICSR register is
read.
Warning: A write to the SPIDR register places
data directly into the shift register for transmission.
A read to the SPIDR register returns the value lo-
cated in the buffer and not the content of the shift
register (see Figure 48).
0: No master mode fault detected
1: A fault in master mode has been detected
Bit 3 = Reserved, must be kept cleared.
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Table 19. SPI Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
SPIDR
Reset Value
MSB
x
LSB
x
0031h
0032h
0033h
x
x
x
x
x
x
SPICR
Reset Value
SPIE
0
SPE
0
SPR2
0
MSTR
0
CPOL
x
CPHA
x
SPR1
x
SPR0
x
SPICSR
Reset Value
SPIF
0
WCOL
0
OVR
0
MODF
0
SOD
0
SSM
0
SSI
0
0
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11.5 LINSCI SERIAL COMMUNICATION INTERFACE (LIN MASTER/SLAVE)
11.5.1 Introduction
■ 6 interrupt sources
The Serial Communications Interface (SCI) offers
a flexible means of full-duplex data exchange with
external equipment requiring an industry standard
NRZ asynchronous serial data format. The SCI of-
fers a very wide range of baud rates using two
baud rate generator systems.
– Transmit data register empty
– Transmission complete
– Receive data register full
– Idle line received
– Overrun error
The LIN-dedicated features support the LIN (Local
Interconnect Network) protocol for both master
and slave nodes.
– Parity interrupt
■ Parity control:
– Transmits parity bit
This chapter is divided into SCI Mode and LIN
mode sections. For information on general SCI
communications, refer to the SCI mode section.
For LIN applications, refer to both the SCI mode
and LIN mode sections.
– Checks parity of received data byte
■ Reduced power consumption mode
11.5.3 LIN Features
– LIN Master
11.5.2 SCI Features
– 13-bit LIN Synch Break generation
– LIN Slave
■ Full duplex, asynchronous communications
■ NRZ standard format (Mark/Space)
– Automatic Header Handling
■ Independently programmable transmit and
receive baud rates up to 500K baud
– Automatic baud rate resynchronization based
on recognition and measurement of the LIN
Synch Field (for LIN slave nodes)
■ Programmable data word length (8 or 9 bits)
■ Receive buffer full, Transmit buffer empty and
End of Transmission flags
■ 2 receiver wake-up modes:
– Address bit (MSB)
– Automatic baud rate adjustment (at CPU fre-
quency precision)
– 11-bit LIN Synch Break detection capability
– LIN Parity check on the LIN Identifier Field
(only in reception)
– Idle line
■ Mutingfunctionformultiprocessorconfigurations
– LIN Error management
– LIN Header Timeout
– Hot plugging support
■ Separate enable bits for Transmitter and
Receiver
■ Overrun, Noise and Frame error detection
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LINSCI™ SERIAL COMMUNICATION INTERFACE (cont’d)
11.5.4 General Description
– A conventional type for commonly-used baud
rates
The interface is externally connected to another
device by two pins:
– An extended type with a prescaler offering a very
wide range of baud rates even with non-standard
oscillator frequencies
– TDO: Transmit Data Output. When the transmit-
ter is disabled, the output pin returns to its I/O
port configuration. When the transmitter is ena-
bled and nothing is to be transmitted, the TDO
pin is at high level.
– A LIN baud rate generator with automatic resyn-
chronization
– RDI: Receive Data Input is the serial data input.
Oversampling techniques are used for data re-
covery by discriminating between valid incoming
data and noise.
Through these pins, serial data is transmitted and
received as characters comprising:
– An Idle Line prior to transmission or reception
– A start bit
– A data word (8 or 9 bits) least significant bit first
– A Stop bit indicating that the character is com-
plete
This interface uses three types of baud rate gener-
ator:
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LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d)
Figure 55. SCI Block Diagram (in Conventional Baud Rate Generator Mode)
Write
Read
(DATA REGISTER) SCIDR
Received Data Register (RDR)
Receive Shift Register
Transmit Data Register (TDR)
TDO
RDI
Transmit Shift Register
SCICR1
R8
SCID
PCE
WAKE
T8
M
PS PIE
WAKE
UP
UNIT
TRANSMIT
CONTROL
RECEIVER
CLOCK
RECEIVER
CONTROL
SCISR
SCICR2
OR/
LHE
NF
TIE TCIE RIE ILIE TE RE RWU SBK
TDRE
RDRF
IDLE
TC
FE
PE
SCI
INTERRUPT
CONTROL
TRANSMITTER
CLOCK
TRANSMITTER RATE
CONTROL
f
CPU
/PR
/16
SCIBRR
SCP1
SCT2
SCT1SCT0SCR2 SCR1SCR0
SCP0
RECEIVER RATE
CONTROL
CONVENTIONAL BAUD RATE GENERATOR
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LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d)
11.5.5 SCI Mode - Functional Description
Conventional Baud Rate Generator Mode
11.5.5.1 Serial Data Format
Word length may be selected as being either 8 or 9
bits by programming the M bit in the SCICR1 reg-
ister (see Figure 56).
The block diagram of the Serial Control Interface
in conventional baud rate generator mode is
shown in Figure 55.
The TDO pin is in low state during the start bit.
The TDO pin is in high state during the stop bit.
It uses four registers:
– 2 control registers (SCICR1 and SCICR2)
– A status register (SCISR)
An Idle character is interpreted as a continuous
logic high level for 10 (or 11) full bit times.
A Break character is a character with a sufficient
number of low level bits to break the normal data
format followed by an extra “1” bit to acknowledge
the start bit.
– A baud rate register (SCIBRR)
Extended Prescaler Mode
Two additional prescalers are available in extend-
ed prescaler mode. They are shown in Figure 57.
– An extended prescaler receiver register (SCIER-
PR)
– An extended prescaler transmitter register (SCI-
ETPR)
Figure 56. Word Length Programming
9-bit Word length (M bit is set)
Possible
Next Data Character
Parity
Data Character
Start
Bit
Next
Start
Bit
Stop
Bit
Bit2
Bit6
Bit1
Bit3
Bit4
Bit5
Bit7
Bit8
Bit0
Bit
Start
Bit
Idle Line
Start
Bit
Extra
’1’
Break Character
8-bit Word length (M bit is reset)
Possible
Parity
Next Data Character
Data Character
Bit
Next
Start
Bit
Start
Bit
Stop
Bit
Bit2
Bit1
Bit3
Bit4
Bit5
Bit6
Bit7
Bit0
Start
Bit
Idle Line
Start
Bit
Extra
’1’
Break Character
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LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d)
11.5.5.2 Transmitter
When no transmission is taking place, a write in-
struction to the SCIDR register places the data di-
rectly in the shift register, the data transmission
starts, and the TDRE bit is immediately set.
The transmitter can send data words of either 8 or
9 bits depending on the M bit status. When the M
bit is set, word length is 9 bits and the 9th bit (the
MSB) has to be stored in the T8 bit in the SCICR1
register.
When a character transmission is complete (after
the stop bit) the TC bit is set and an interrupt is
generated if the TCIE is set and the I[1:0] bits are
cleared in the CCR register.
Character Transmission
During an SCI transmission, data shifts out least
significant bit first on the TDO pin. In this mode,
the SCIDR register consists of a buffer (TDR) be-
tween the internal bus and the transmit shift regis-
ter (see Figure 55).
Clearing the TC bit is performed by the following
software sequence:
1. An access to the SCISR register
2. A write to the SCIDR register
Note: The TDRE and TC bits are cleared by the
same software sequence.
Procedure
– Select the M bit to define the word length.
Break Characters
– Select the desired baud rate using the SCIBRR
and the SCIETPR registers.
Setting the SBK bit loads the shift register with a
break character. The break character length de-
pends on the M bit (see Figure 56).
– Set the TE bit to send a preamble of 10 (M = 0)
or 11 (M = 1) consecutive ones (Idle Line) as first
transmission.
As long as the SBK bit is set, the SCI sends break
characters to the TDO pin. After clearing this bit by
software, the SCI inserts a logic 1 bit at the end of
the last break character to guarantee the recogni-
tion of the start bit of the next character.
– Access the SCISR register and write the data to
send in the SCIDR register (this sequence clears
the TDRE bit). Repeat this sequence for each
data to be transmitted.
Idle Line
Clearing the TDRE bit is always performed by the
following software sequence:
1. An access to the SCISR register
2. A write to the SCIDR register
Setting the TE bit drives the SCI to send a pream-
ble of 10 (M = 0) or 11 (M = 1) consecutive ‘1’s
(idle line) before the first character.
In this case, clearing and then setting the TE bit
during a transmission sends a preamble (idle line)
after the current word. Note that the preamble du-
ration (10 or 11 consecutive ‘1’s depending on the
M bit) does not take into account the stop bit of the
previous character.
The TDRE bit is set by hardware and it indicates:
– The TDR register is empty.
– The data transfer is beginning.
– The next data can be written in the SCIDR regis-
ter without overwriting the previous data.
Note: Resetting and setting the TE bit causes the
data in the TDR register to be lost. Therefore the
best time to toggle the TE bit is when the TDRE bit
is set, that is, before writing the next byte in the
SCIDR.
This flag generates an interrupt if the TIE bit is set
and the I[|1:0] bits are cleared in the CCR register.
When a transmission is taking place, a write in-
struction to the SCIDR register stores the data in
the TDR register and which is copied in the shift
register at the end of the current transmission.
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LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d)
11.5.5.3 Receiver
– The OR bit is set.
The SCI can receive data words of either 8 or 9
bits. When the M bit is set, word length is 9 bits
and the MSB is stored in the R8 bit in the SCICR1
register.
– The RDR content will not be lost.
– The shift register will be overwritten.
– An interrupt is generated if the RIE bit is set and
the I[|1:0] bits are cleared in the CCR register.
Character reception
The OR bit is reset by an access to the SCISR reg-
ister followed by a SCIDR register read operation.
During a SCI reception, data shifts in least signifi-
cant bit first through the RDI pin. In this mode, the
SCIDR register consists or a buffer (RDR) be-
tween the internal bus and the received shift regis-
ter (see Figure 55).
Noise Error
Oversampling techniques are used for data recov-
ery by discriminating between valid incoming data
and noise.
Procedure
When noise is detected in a character:
– Select the M bit to define the word length.
– The NF bit is set at the rising edge of the RDRF
bit.
– Select the desired baud rate using the SCIBRR
and the SCIERPR registers.
– Data is transferred from the Shift register to the
SCIDR register.
– Set the RE bit, this enables the receiver which
begins searching for a start bit.
– No interrupt is generated. However this bit rises
at the same time as the RDRF bit which itself
generates an interrupt.
When a character is received:
– The RDRF bit is set. It indicates that the content
of the shift register is transferred to the RDR.
The NF bit is reset by a SCISR register read oper-
ation followed by a SCIDR register read operation.
– An interrupt is generated if the RIE bit is set and
the I[1:0] bits are cleared in the CCR register.
Framing Error
– The error flags can be set if a frame error, noise
or an overrun error has been detected during re-
ception.
A framing error is detected when:
– The stop bit is not recognized on reception at the
expected time, following either a desynchroniza-
tion or excessive noise.
Clearing the RDRF bit is performed by the following
software sequence done by:
– A break is received.
1. An access to the SCISR register
2. A read to the SCIDR register.
When the framing error is detected:
– the FE bit is set by hardware
The RDRF bit must be cleared before the end of the
reception of the next character to avoid an overrun
error.
– Data is transferred from the Shift register to the
SCIDR register.
Idle Line
– No interrupt is generated. However this bit rises
at the same time as the RDRF bit which itself
generates an interrupt.
When an idle line is detected, there is the same
procedure as a data received character plus an in-
terrupt if the ILIE bit is set and the I[|1:0] bits are
cleared in the CCR register.
The FE bit is reset by a SCISR register read oper-
ation followed by a SCIDR register read operation.
Overrun Error
Break Character
An overrun error occurs when a character is re-
ceived when RDRF has not been reset. Data can
not be transferred from the shift register to the
TDR register as long as the RDRF bit is not
cleared.
– When a break character is received, the SCI
handles it as a framing error. To differentiate a
break character from a framing error, it is neces-
sary to read the SCIDR. If the received value is
00h, it is a break character. Otherwise it is a
framing error.
When an overrun error occurs:
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LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d)
11.5.5.4 Conventional Baud Rate Generation
11.5.5.5 Extended Baud Rate Generation
The baud rates for the receiver and transmitter (Rx
and Tx) are set independently and calculated as
follows:
The extended prescaler option gives a very fine
tuning on the baud rate, using a 255 value prescal-
er, whereas the conventional Baud Rate Genera-
tor retains industry standard software compatibili-
ty.
f
f
CPU
CPU
Rx =
Tx =
The extended baud rate generator block diagram
is described in Figure 57.
(16 PR) RR
(16 PR) TR
*
*
*
*
with:
The output clock rate sent to the transmitter or to
the receiver will be the output from the 16 divider
divided by a factor ranging from 1 to 255 set in the
SCIERPR or the SCIETPR register.
PR = 1, 3, 4 or 13 (see SCP[1:0] bits)
TR = 1, 2, 4, 8, 16, 32, 64,128
(see SCT[2:0] bits)
Note: The extended prescaler is activated by set-
ting the SCIETPR or SCIERPR register to a value
other than zero. The baud rates are calculated as
follows:
RR = 1, 2, 4, 8, 16, 32, 64,128
(see SCR[2:0] bits)
All these bits are in the SCIBRR register.
Example: If f is 8 MHz (normal mode) and if
CPU
f
f
CPU
CPU
PR = 13 and TR = RR = 1, the transmit and re-
ceive baud rates are 38400 baud.
Rx =
16 ERPR*(PR*RR)
Tx =
16 ETPR*(PR*TR)
*
*
Note: The baud rate registers MUST NOT be
changed while the transmitter or the receiver is en-
abled.
with:
ETPR = 1, ..., 255 (see SCIETPR register)
ERPR = 1, ..., 255 (see SCIERPR register)
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LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d)
Figure 57. SCI Baud Rate and Extended Prescaler Block Diagram
TRANSMITTER
CLOCK
EXTENDED PRESCALER TRANSMITTER RATE CONTROL
SCIETPR
EXTENDED TRANSMITTER PRESCALER REGISTER
SCIERPR
EXTENDED RECEIVER PRESCALER REGISTER
RECEIVER
CLOCK
EXTENDED PRESCALER RECEIVER RATE CONTROL
EXTENDED PRESCALER
f
CPU
TRANSMITTER RATE
CONTROL
/PR
/16
SCIBRR
SCP1
SCT2
SCT1SCT0SCR2 SCR1SCR0
SCP0
RECEIVER RATE
CONTROL
CONVENTIONAL BAUD RATE GENERATOR
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LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d)
11.5.5.6 Receiver Muting and Wake-up Feature
ceived an address character (most significant bit
= ’1’), the receivers are waken up. The receivers
which are not addressed set RWU bit to enter in
mute mode. Consequently, they will not treat the
next characters constituting the next part of the
message.
In multiprocessor configurations it is often desira-
ble that only the intended message recipient
should actively receive the full message contents,
thus reducing redundant SCI service overhead for
all non-addressed receivers.
11.5.5.7 Parity Control
The non-addressed devices may be placed in
sleep mode by means of the muting function.
Hardware byte Parity control (generation of parity
bit in transmission and parity checking in recep-
tion) can be enabled by setting the PCE bit in the
SCICR1 register. Depending on the character for-
mat defined by the M bit, the possible SCI charac-
ter formats are as listed in Table 20.
Setting the RWU bit by software puts the SCI in
sleep mode:
All the reception status bits can not be set.
All the receive interrupts are inhibited.
Note: In case of wake-up by an address mark, the
MSB bit of the data is taken into account and not
the parity bit
A muted receiver may be woken up in one of the
following ways:
– by Idle Line detection if the WAKE bit is reset,
– by Address Mark detection if the WAKE bit is set.
Idle Line Detection
Table 20. Character Formats
M bit
PCE bit
Character format
| SB | 8 bit data | STB |
| SB | 7-bit data | PB | STB |
| SB | 9-bit data | STB |
| SB | 8-bit data | PB | STB |
Receiver wakes up by Idle Line detection when the
Receive line has recognized an Idle Line. Then the
RWU bit is reset by hardware but the IDLE bit is
not set.
0
1
0
1
0
1
This feature is useful in a multiprocessor system
when the first characters of the message deter-
mine the address and when each message ends
by an idle line: As soon as the line becomes idle,
every receivers is waken up and analyse the first
characters of the message which indicates the ad-
dressed receiver. The receivers which are not ad-
dressed set RWU bit to enter in mute mode. Con-
sequently, they will not treat the next characters
constituting the next part of the message. At the
end of the message, an idle line is sent by the
transmitter: this wakes up every receivers which
are ready to analyse the addressing characters of
the new message.
Legend: SB = Start Bit, STB = Stop Bit,
PB = Parity Bit
Even parity: The parity bit is calculated to obtain
an even number of “1s” inside the character made
of the 7 or 8 LSB bits (depending on whether M is
equal to 0 or 1) and the parity bit.
Example: data = 00110101; 4 bits set => parity bit
will be 0 if even parity is selected (PS bit = 0).
Odd parity: The parity bit is calculated to obtain
an odd number of “1s” inside the character made
of the 7 or 8 LSB bits (depending on whether M is
equal to 0 or 1) and the parity bit.
Example: data = 00110101; 4 bits set => parity bit
will be 1 if odd parity is selected (PS bit = 1).
In such a system, the inter-characters space must
be smaller than the idle time.
Transmission mode: If the PCE bit is set then the
MSB bit of the data written in the data register is
not transmitted but is changed by the parity bit.
Address Mark Detection
Receiver wakes up by Address Mark detection
when it received a “1” as the most significant bit of
a word, thus indicating that the message is an ad-
dress. The reception of this particular word wakes
up the receiver, resets the RWU bit and sets the
RDRF bit, which allows the receiver to receive this
word normally and to use it as an address word.
Reception mode: If the PCE bit is set then the in-
terface checks if the received data byte has an
even number of “1s” if even parity is selected
(PS = 0) or an odd number of “1s” if odd parity is
selected (PS = 1). If the parity check fails, the PE
flag is set in the SCISR register and an interrupt is
generated if PCIE is set in the SCICR1 register.
This feature is useful in a multiprocessor system
when the most significant bit of each character
(except for the break character) is reserved for Ad-
dress Detection. As soon as the receivers re-
94/168
1
ST7L34, ST7L35, ST7L38, ST7L39
LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d)
11.5.6 Low Power Modes
11.5.7 Interrupts
Mode
Description
No effect on SCI.
SCI interrupts cause the device to exit from
Wait mode.
Enable Exit
Control from from
Exit
Event
Flag
Interrupt Event
Bit
Wait
Halt
WAIT
TransmitDataRegister
Empty
TDRE
TC
TIE
SCI registers are frozen.
In Halt mode, the SCI stops transmitting/re-
ceiving until Halt mode is exited.
HALT
Transmission Com-
plete
TCIE
RIE
Received Data Ready
to be Read
RDRF
Yes
No
Overrun Error or LIN
Synch Error Detected
OR/
LHE
Idle Line Detected
Parity Error
IDLE
PE
ILIE
PIE
LIN Header Detection LHDF LHIE
The SCI interrupt events are connected to the
same interrupt vector (see Interrupts chapter).
These events generate an interrupt if the corre-
sponding Enable Control Bit is set and the inter-
rupt mask in the CC register is reset (RIM instruc-
tion).
95/168
1
ST7L34, ST7L35, ST7L38, ST7L39
LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d)
11.5.8 SCI Mode Register Description
STATUS REGISTER (SCISR)
Read Only
Bit 3 = OR Overrun error
The OR bit is set by hardware when the word cur-
rently being received in the shift register is ready to
be transferred into the RDR register whereas
RDRF is still set. An interrupt is generated if
RIE = 1 in the SCICR2 register. It is cleared by a
software sequence (an access to the SCISR regis-
ter followed by a read to the SCIDR register).
0: No Overrun error
Reset Value: 1100 0000 (C0h)
7
0
1)
1)
1)
1)
TDRE
TC
RDRF IDLE
OR
NF
FE
PE
Bit 7 = TDRE Transmit data register empty
1: Overrun error detected
This bit is set by hardware when the content of the
TDR register has been transferred into the shift
register. An interrupt is generated if the TIE = 1 in
the SCICR2 register. It is cleared by a software se-
quence (an access to the SCISR register followed
by a write to the SCIDR register).
Note: When this bit is set, RDR register contents
will not be lost but the shift register will be overwrit-
ten.
0: Data is not transferred to the shift register
1: Data is transferred to the shift register
Bit 2 = NF Character Noise flag
This bit is set by hardware when noise is detected
on a received character. It is cleared by a software
sequence (an access to the SCISR register fol-
lowed by a read to the SCIDR register).
0: No noise
Bit 6 = TC Transmission complete
This bit is set by hardware when transmission of a
character containing Data is complete. An inter-
rupt is generated if TCIE = 1 in the SCICR2 regis-
ter. It is cleared by a software sequence (an ac-
cess to the SCISR register followed by a write to
the SCIDR register).
1: Noise is detected
Note: This bit does not generate interrupt as it ap-
pears at the same time as the RDRF bit which it-
self generates an interrupt.
0: Transmission is not complete
1: Transmission is complete
Bit 1 = FE Framing error
Note: TC is not set after the transmission of a Pre-
amble or a Break.
This bit is set by hardware when a desynchroniza-
tion, excessive noise or a break character is de-
tected. It is cleared by a software sequence (an
access to the SCISR register followed by a read to
the SCIDR register).
Bit 5 = RDRF Received data ready flag
This bit is set by hardware when the content of the
RDR register has been transferred to the SCIDR
register. An interrupt is generated if RIE = 1 in the
SCICR2 register. It is cleared by a software se-
quence (an access to the SCISR register followed
by a read to the SCIDR register).
0: No Framing error
1: Framing error or break character detected
Note: This bit does not generate an interrupt as it
appears at the same time as the RDRF bit which it-
self generates an interrupt. If the word currently
being transferred causes both a frame error and
an overrun error, it will be transferred and only the
OR bit will be set.
0: Data is not received
1: Received data is ready to be read
Bit 4 = IDLE Idle line detected
This bit is set by hardware when an Idle Line is de-
tected. An interrupt is generated if the ILIE = 1 in
the SCICR2 register. It is cleared by a software se-
quence (an access to the SCISR register followed
by a read to the SCIDR register).
Bit 0 = PE Parity error
This bit is set by hardware when a byte parity error
occurs (if the PCE bit is set) in receiver mode. It is
cleared by a software sequence (a read to the sta-
tus register followed by an access to the SCIDR
data register). An interrupt is generated if PIE = 1
in the SCICR1 register.
0: No Idle Line is detected
1: Idle Line is detected
0: No parity error
1: Parity error detected
Note: The IDLE bit will not be set again until the
RDRF bit has been set itself (that is, a new idle line
occurs).
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1
ST7L34, ST7L35, ST7L38, ST7L39
LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d)
CONTROL REGISTER 1 (SCICR1)
Read/Write
Bit 3 = WAKE Wake-Up method
This bit determines the SCI Wake-Up method, it is
set or cleared by software.
0: Idle Line
Reset Value: x000 0000 (x0h)
7
0
1: Address Mark
1)
R8
T8
SCID
M
WAKE
PS
PIE
PCE
Note: If the LINE bit is set, the WAKE bit is deacti-
vated and replaced by the LHDM bit.
1)
This bit has a different function in LIN mode, please
refer to the LIN mode register description.
Bit 2 = PCE Parity control enable
Bit 7 = R8 Receive data bit 8
This bit is set and cleared by software. It selects
the hardware parity control (generation and detec-
tion for byte parity, detection only for LIN parity).
0: Parity control disabled
This bit is used to store the 9th bit of the received
word when M = 1.
1: Parity control enabled
Bit 6 = T8 Transmit data bit 8
This bit is used to store the 9th bit of the transmit-
ted word when M = 1.
Bit 1 = PS Parity selection
This bit selects the odd or even parity when the
parity generation/detection is enabled (PCE bit
set). It is set and cleared by software. The parity
will be selected after the current byte.
0: Even parity
Bit 5 = SCID Disabled for low power consumption
When this bit is set the SCI prescalers and outputs
are stopped and the end of the current byte trans-
fer in order to reduce power consumption.This bit
is set and cleared by software.
1: Odd parity
0: SCI enabled
1: SCI prescaler and outputs disabled
Bit 0 = PIE Parity interrupt enable
This bit enables the interrupt capability of the hard-
ware parity control when a parity error is detected
(PE bit set). The parity error involved can be a byte
parity error (if bit PCE is set and bit LPE is reset) or
a LIN parity error (if bit PCE is set and bit LPE is
set).
Bit 4 = M Word length
This bit determines the word length. It is set or
cleared by software.
0: 1 Start bit, 8 Data bits, 1 Stop bit
1: 1 Start bit, 9 Data bits, 1 Stop bit
0: Parity error interrupt disabled
Note: The M bit must not be modified during a data
transfer (both transmission and reception).
1: Parity error interrupt enabled
97/168
1
ST7L34, ST7L35, ST7L38, ST7L39
LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d)
CONTROL REGISTER 2 (SCICR2)
Read/Write
Reset Value: 0000 0000 (00h)
1: Receiver is enabled and begins searching for a
start bit
Bit 1 = RWU Receiver wake-up
7
0
This bit determines if the SCI is in mute mode or
not. It is set and cleared by software and can be
cleared by hardware when a wake-up sequence is
recognized.
1)
1)
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
1)
0: Receiver in active mode
This bit has a different function in LIN mode, please
1: Receiver in mute mode
refer to the LIN mode register description.
Notes:
Bit 7 = TIE Transmitter interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: In SCI interrupt is generated whenever
TDRE = 1 in the SCISR register
– Before selecting Mute mode (by setting the RWU
bit) the SCI must first receive a data byte, other-
wise it cannot function in Mute mode with wake-
up by Idle line detection.
– In Address Mark Detection Wake-Up configura-
tion (WAKE bit = 1) the RWU bit cannot be mod-
ified by software while the RDRF bit is set.
Bit 6 = TCIE Transmission complete interrupt ena-
ble
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever TC = 1
in the SCISR register
Bit 0 = SBK Send break
This bit set is used to send break characters. It is
set and cleared by software.
0: No break character is transmitted
1: Break characters are transmitted
Bit 5 = RIE Receiver interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever OR = 1
or RDRF = 1 in the SCISR register
Note: If the SBK bit is set to “1” and then to “0”, the
transmitter will send a BREAK word at the end of
the current word.
DATA REGISTER (SCIDR)
Read/Write
Reset Value: Undefined
Bit 4 = ILIE Idle line interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever
IDLE = 1 in the SCISR register.
Contains the Received or Transmitted data char-
acter, depending on whether it is read from or writ-
ten to.
Bit 3 = TE Transmitter enable
This bit enables the transmitter. It is set and
cleared by software.
7
0
DR7
DR6
DR5
DR4
DR3
DR2
DR1
DR0
0: Transmitter is disabled
1: Transmitter is enabled
Notes:
The Data register performs a double function (read
and write) since it is composed of two registers,
one for transmission (TDR) and one for reception
(RDR).
The TDR register provides the parallel interface
between the internal bus and the output shift reg-
ister (see Figure 55).
– During transmission, a “0” pulse on the TE bit
(“0” followed by “1”) sends a preamble (idle line)
after the current word.
– When TE is set there is a 1 bit-time delay before
the transmission starts.
The RDR register provides the parallel interface
between the input shift register and the internal
bus (see Figure 55).
Bit 2 = RE Receiver enable
This bit enables the receiver. It is set and cleared
by software.
0: Receiver is disabled in the SCISR register
98/168
1
ST7L34, ST7L35, ST7L38, ST7L39
LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d)
BAUD RATE REGISTER (SCIBRR)
Read/Write
TR dividing factor
SCT2
SCT1
SCT0
1
2
0
1
0
1
0
1
0
1
Reset Value: 0000 0000 (00h)
0
0
7
0
4
1
0
1
8
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0
16
32
64
128
Note: When LIN slave mode is disabled, the SCI-
BRR register controls the conventional baud rate
generator.
1
Bits 7:6 = SCP[1:0] First SCI Prescaler
These 2 prescaling bits allow several standard
clock division ranges:
Bits 2:0 = SCR[2:0] SCI Receiver rate divider
These 3 bits, in conjunction with the SCP[1:0] bits
define the total division applied to the bus clock to
yield the receive rate clock in conventional Baud
Rate Generator mode.
PR Prescaling factor
SCP1
SCP0
1
3
0
1
0
1
0
RR dividing factor
SCR2
SCR1
SCR0
4
1
1
2
0
1
0
1
0
1
0
1
13
0
0
4
Bits 5:3 = SCT[2:0] SCI Transmitter rate divisor
These 3 bits, in conjunction with the SCP1 and
SCP0 bits define the total division applied to the
bus clock to yield the transmit rate clock in conven-
tional Baud Rate Generator mode.
1
0
1
8
16
32
64
128
1
99/168
1
ST7L34, ST7L35, ST7L38, ST7L39
LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d)
EXTENDED RECEIVE PRESCALER DIVISION
REGISTER (SCIERPR)
EXTENDED TRANSMIT PRESCALER DIVISION
REGISTER (SCIETPR)
Read/Write
Read/Write
Reset Value: 0000 0000 (00h)
Reset Value:0000 0000 (00h)
7
0
7
0
ERPR ERPR ERPR ERPR ERPR ERPR ERPR ERPR
ETPR ETPR ETPR ETPR ETPR ETPR ETPR ETPR
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Bits 7:0 = ERPR[7:0] 8-bit Extended Receive
Prescaler Register
Bits 7:0 = ETPR[7:0] 8-bit Extended Transmit
Prescaler Register
The extended Baud Rate Generator is activated
when a value other than 00h is stored in this regis-
ter. The clock frequency from the 16 divider (see
Figure 57) is divided by the binary factor set in the
SCIERPR register (in the range 1 to 255).
The extended Baud Rate Generator is activated
when a value other than 00h is stored in this regis-
ter. The clock frequency from the 16 divider (see
Figure 57) is divided by the binary factor set in the
SCIETPR register (in the range 1 to 255).
The extended baud rate generator is not active af-
ter a reset.
The extended baud rate generator is not active af-
ter a reset.
Note: In LIN slave mode, the Conventional and
Extended Baud Rate Generators are disabled.
100/168
ST7L34, ST7L35, ST7L38, ST7L39
LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode)
11.5.9 LIN Mode - Functional Description.
Slave
The block diagram of the Serial Control Interface,
in LIN slave mode is shown in Figure 59.
Set the LSLV bit in the SCICR3 register to enter
LIN slave mode. In this case, setting the SBK bit
will have no effect.
It uses six registers:
In LIN Slave mode the LIN baud rate generator is
selected instead of the Conventional or Extended
Prescaler. The LIN baud rate generator is com-
mon to the transmitter and the receiver.
– 3 control registers: SCICR1, SCICR2 and
SCICR3
– 2 status registers: the SCISR register and the
LHLR register mapped at the SCIERPR address
Then the baud rate can be programmed using
LPR and LPRF registers.
– A baud rate register: LPR mapped at the SCI-
BRR address and an associated fraction register
LPFR mapped at the SCIETPR address
Note: It is mandatory to set the LIN configuration
first before programming LPR and LPRF, because
the LIN configuration uses a different baud rate
generator from the standard one.
The bits dedicated to LIN are located in the
SCICR3. Refer to the register descriptions in Sec-
tion 11.5.10 for the definitions of each bit.
11.5.9.1 Entering LIN Mode
11.5.9.2 LIN Transmission
To use the LINSCI in LIN mode the following con-
figuration must be set in SCICR3 register:
In LIN mode the same procedure as in SCI mode
has to be applied for a LIN transmission.
– Clear the M bit to configure 8-bit word length.
To transmit the LIN Header the proceed as fol-
lows:
– Set the LINE bit.
Master
– First set the SBK bit in the SCICR2 register to
start transmitting a 13-bit LIN Synch Break
To enter master mode the LSLV bit must be reset
In this case, setting the SBK bit will send 13 low
bits.
– reset the SBK bit
– Load the LIN Synch Field (0x55) in the SCIDR
register to request Synch Field transmission
Then the baud rate can programmed using the
SCIBRR, SCIERPR and SCIETPR registers.
– Wait until the SCIDR is empty (TDRE bit set in
the SCISR register)
In LIN master mode, the Conventional and / or Ex-
tended Prescaler define the baud rate (as in stand-
ard SCI mode)
– Load the LIN message Identifier in the SCIDR
register to request Identifier transmission.
101/168
ST7L34, ST7L35, ST7L38, ST7L39
LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d)
Figure 58. LIN Characters
8-bit Word length (M bit is reset)
Next Data Character
Data Character
Next
Start
Bit
Start
Bit
Stop
Bit2
Bit3 Bit4
Bit5 Bit6
Bit7
Bit0 Bit1
Bit
Start
Bit
Idle Line
LIN Synch Field
LIN Synch Break = 13 low bits
Start
Bit
Extra
‘1’
LIN Synch Field
Bit2
Next
Start
Bit
Start
Bit
Stop
Bit
Bit0 Bit1
Bit3 Bit4
Bit5 Bit6
Bit7
Measurement for baud rate autosynchronization
102/168
ST7L34, ST7L35, ST7L38, ST7L39
LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d)
Figure 59. SCI Block Diagram in LIN Slave Mode
Write
Read
(DATA REGISTER) SCIDR
Received Data Register (RDR)
Receive Shift Register
Transmit Data Register (TDR)
TDO
Transmit Shift Register
RDI
SCICR1
R8
SCID
PCE
WAKE
T8
M
PS PIE
WAKE
TRANSMIT
UP
RECEIVER
CONTROL
CONTROL
UNIT
RECEIVER
CLOCK
SCISR
SCICR2
OR/
LHE
TIE TCIE RIE ILIE TE RE RWU SBK
TDRE
RDRF
IDLE
TC
NF FE
PE
SCI
INTERRUPT
CONTROL
TRANSMITTER
CLOCK
f
CPU
LIN SLAVE BAUD RATE
SCICR3
LDUM LINE
LASE LHDM LHIE LHDF LSF
LSLV
AUTO SYNCHRONIZATION
UNIT
SCIBRR
CONVENTIONAL BAUD RATE
LPR7
LPR0
GENERATOR
+
EXTENDED PRESCALER
0
f
CPU
1
/ LDIV
/16
LIN SLAVE BAUD RATE GENERATOR
103/168
ST7L34, ST7L35, ST7L38, ST7L39
LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d)
11.5.9.3 LIN Reception
Note:
In LIN mode the reception of a byte is the same as
in SCI mode but the LINSCI has features for han-
dling the LIN Header automatically (identifier de-
tection) or semiautomatically (Synch Break detec-
tion) depending on the LIN Header detection
mode. The detection mode is selected by the
LHDM bit in the SCICR3.
In LIN slave mode, the FE bit detects all frame er-
ror which does not correspond to a break.
Identifier Detection (LHDM = 1):
This case is the same as the previous one except
that the LHDF and the RDRF flags are set only af-
ter the entire header has been received (this is
true whether automatic resynchronization is ena-
bled or not). This indicates that the LIN Identifier is
available in the SCIDR register.
Additionally, an automatic resynchronization fea-
ture can be activated to compensate for any clock
deviation, for more details please refer to Section
11.5.9.5 LIN Baud Rate.
Notes:
During LIN Synch Field measurement, the SCI
state machine is switched off: No characters are
transferred to the data register.
LIN Header Handling by a Slave
Depending on the LIN Header detection method
the LINSCI will signal the detection of a LIN Head-
er after the LIN Synch Break or after the Identifier
has been successfully received.
LIN Slave parity
In LIN Slave mode (LINE and LSLV bits are set)
LIN parity checking can be enabled by setting the
PCE bit.
Note:
It is recommended to combine the Header detec-
tion function with Mute mode. Putting the LINSCI
in Mute mode allows the detection of Headers only
and prevents the reception of any other charac-
ters.
In this case, the parity bits of the LIN Identifier
Field are checked. The identifier character is rec-
ognized as the third received character after a
break character (included):
This mode can be used to wait for the next Header
without being interrupted by the data bytes of the
current message in case this message is not rele-
vant for the application.
parity bits
Synch Break Detection (LHDM = 0):
When a LIN Synch Break is received:
LIN Synch
Break
LIN Synch
Field
Identifier
Field
– The RDRF bit in the SCISR register is set. It in-
dicates that the content of the shift register is
transferred to the SCIDR register, a value of
0x00 is expected for a Break.
The bits involved are the two MSB positions (7th
and 8th bits if M = 0; 8th and 9th bits if M = 0) of
the identifier character. The check is performed as
specified by the LIN specification:
– The LHDF flag in the SCICR3 register indicates
that a LIN Synch Break Field has been detected.
– An interrupt is generated if the LHIE bit in the
SCICR3 register is set and the I[1:0] bits are
cleared in the CCR register.
stop bit
parity bits
start bit
– Then the LIN Synch Field is received and meas-
ured.
identifier bits
ID0 ID1 ID2 ID3 ID4 ID5 P0 P1
– If automatic resynchronization is enabled (LA-
SE bit = 1), the LIN Synch Field is not trans-
ferred to the shift register: There is no need to
clear the RDRF bit.
Identifier Field
P0= ID0 ⊕ ID1 ⊕ ID2 ⊕ ID4
P1= ID1 ⊕ ID3 ⊕ ID4 ⊕ ID5
M = 0
– If automatic resynchronization is disabled (LA-
SE bit = 0), the LIN Synch Field is received as
a normal character and transferred to the
SCIDR register and RDRF is set.
104/168
ST7L34, ST7L35, ST7L38, ST7L39
LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d)
11.5.9.4 LIN Error Detection
LIN Header Error Flag
edge of the Synch Field. Let us refer to this peri-
od deviation as D:
If the LHE flag is set, it means that:
D > 15.625%
The LIN Header Error Flag indicates that an invalid
LIN Header has been detected.
When a LIN Header Error occurs:
– The LHE flag is set
If LHE flag is not set, it means that:
D < 16.40625%
– An interrupt is generated if the RIE bit is set and
the I[1:0] bits are cleared in the CCR register.
If 15.625% ≤ D < 16.40625%, then the flag can
be either set or reset depending on the dephas-
ing between the signal on the RDI line and the
CPU clock.
If autosynchronization is enabled (LASE bit = 1),
this can mean that the LIN Synch Field is corrupt-
ed, and that the SCI is in a blocked state (LSF bit is
set). The only way to recover is to reset the LSF bit
and then to clear the LHE bit.
– The second check is based on the measurement
of each bit time between both edges of the Synch
Field: this checks that each of these bit times is
large enough compared to the bit time of the cur-
rent baud rate.
– The LHE bit is reset by an access to the SCISR
register followed by a read of the SCIDR register.
When LHE is set due to this error then the SCI
goes into a blocked state (LSF bit is set).
LHE/OVR Error Conditions
When Auto Resynchronization is disabled (LASE
bit = 0), the LHE flag detects:
LIN Header Time-out Error
When the LIN Identifier Field Detection Method is
used (by configuring LHDM to 1) or when LIN
auto-resynchronization is enabled (LASE bit = 1),
– That the received LIN Synch Field is not equal to
55h.
– That an overrun occurred (as in standard SCI
mode)
the
LINSCI
automatically
monitors
the
T
condition given by the LIN protocol.
HEADER_MAX
– Furthermore, if LHDM is set it also detects that a
LIN Header Reception Timeout occurred (only if
LHDM is set).
If the entire Header (up to and including the STOP
bit of the LIN Identifier Field) is not received within
the maximum time limit of 57 bit times then a LIN
Header Error is signalled and the LHE bit is set in
the SCISR register.
When the LIN auto-resynchronization is enabled
(LASE bit = 1), the LHE flag detects:
– That the deviation error on the Synch Field is
outside the LIN specification which allows up to
+/-15.5% of period deviation between the slave
and master oscillators.
Figure 60. LIN Header Reception Timeout
– A LIN Header Reception Timeout occurred.
LIN Synch
Break
LIN Synch
Field
Identifier
Field
If T
> T
then the LHE flag is
HEADER
HEADER_MAX
set. Refer to Figure 60. (only if LHDM is set to 1)
– An overflow during the Synch Field Measure-
ment, which leads to an overflow of the divider
registers. If LHE is set due to this error then the
SCI goes into a blocked state (LSF bit is set).
T
HEADER
The time-out counter is enabled at each break de-
tection. It is stopped in the following conditions:
- A LIN Identifier Field has been received
- An LHE error occurred (other than a timeout er-
ror).
– That an overrun occurred on Fields other than
the Synch Field (as in standard SCI mode)
Deviation Error on the Synch Field
- A software reset of LSF bit (transition from high to
low) occurred during the analysis of the LIN Synch
Field or
The deviation error is checking by comparing the
current baud rate (relative to the slave oscillator)
with the received LIN Synch Field (relative to the
master oscillator). Two checks are performed in
parallel:
If LHE bit is set due to this error during the LIN
Synchr Field (if LASE bit = 1) then the SCI goes
into a blocked state (LSF bit is set).
– The first check is based on a measurement be-
tween the first falling edge and the last falling
105/168
ST7L34, ST7L35, ST7L38, ST7L39
LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d)
If LHE bit is set due to this error during Fields other
than LIN Synch Field or if LASE bit is reset then
the current received Header is discarded and the
SCI searches for a new Break Field.
LIN Header Length
Even if no timeout occurs on the LIN Header, it is
possible to have access to the effective LIN head-
er Length (T
) through the LHL register.
HEADER
Note on LIN Header Time-out Limit
This allows monitoring at software level the
condition given by the LIN protocol.
T
FRAME_MAX
According to the LIN specification, the maximum
length of a LIN Header which does not cause a
This feature is only available when LHDM bit = 1
or when LASE bit = 1.
timeout
BIT_MASTER
is
equal
to
1.4 * (34 + 1) = 49
T
.
Mute Mode and Errors
T
refers to the master baud rate.
BIT_MASTER
In mute mode when LHDM bit = 1, if an LHE error
occurs during the analysis of the LIN Synch Field
or if a LIN Header Time-out occurs then the LHE
bit is set but it does not wake up from mute mode.
In this case, the current header analysis is discard-
ed. If needed, the software has to reset LSF bit.
Then the SCI searches for a new LIN header.
When checking this timeout, the slave node is de-
synchronized for the reception of the LIN Break
and Synch fields. Consequently, a margin must be
allowed, taking into account the worst case: This
occurs when the LIN identifier lasts exactly 10
T
periods. In this case, the LIN Break
BIT_MASTER
and Synch fields last 49 - 10 = 39T
riods.
pe-
BIT_MASTER
In mute mode, if a framing error occurs on a data
(which is not a break), it is discarded and the FE bit
is not set.
Assuming the slave measures these first 39 bits
with a desynchronized clock of 15.5%. This leads
to a maximum allowed Header Length of:
When LHDM bit = 1, any LIN header which re-
spects the following conditions causes a wake-up
from mute mode:
39 x (1/0.845) T
+ 10T
BIT_MASTER
BIT_MASTER
= 56.15 T
- A valid LIN Break Field (at least 11 dominant bits
followed by a recessive bit)
BIT_SLAVE
A margin is provided so that the time-out occurs
when the header length is greater than 57
- A valid LIN Synch Field (without deviation error)
T
T
periods. If it is less than or equal to 57
periods, then no timeout occurs.
BIT_SLAVE
BIT_SLAVE
- A LIN Identifier Field without framing error. Note
that a LIN parity error on the LIN Identifier Field
does not prevent wake-up from mute mode.
- No LIN Header Time-out should occur during
Header reception.
Figure 61. LIN Synch Field Measurement
T
T
= CPU period
= Baud Rate period
CPU
T
= 16.LP.T
CPU
BR
BR
SM = Synch Measurement Register (15 bits)
T
BR
LIN Synch Field
Bit2
Measurement = 8.T = SM.T
Next
Start
Bit
LIN Synch Break
Start
Bit
Extra
‘1’
Stop
Bit
Bit5
Bit6
Bit0
Bit1
Bit3 Bit4
Bit7
BR
CPU
LPR(n+1)
LPR(n)
LPR = T / (16.T
) = Rounding (SM / 128)
CPU
BR
106/168
ST7L34, ST7L35, ST7L38, ST7L39
LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d)
11.5.9.5 LIN Baud Rate
mitter are both set to the same value, depending
on the LIN Slave baud rate generator:
Baud rate programming is done by writing a value
in the LPR prescaler or performing an automatic
resynchronization as described below.
f
CPU
Automatic Resynchronization
Tx = Rx =
(16 LDIV)
*
To automatically adjust the baud rate based on
measurement of the LIN Synch Field:
with:
– Write the nominal LIN Prescaler value (usually
depending on the nominal baud rate) in the
LPFR / LPR registers.
LDIV is an unsigned fixed point number. The man-
tissa is coded on 8 bits in the LPR register and the
fraction is coded on 4 bits in the LPFR register.
– Set the LASE bit to enable the Auto Synchroni-
zation Unit.
If LASE bit = 1 then LDIV is automatically updated
at the end of each LIN Synch Field.
When Auto Synchronization is enabled, after each
LIN Synch Break, the time duration between five
Three registers are used internally to manage the
auto-update of the LIN divider (LDIV):
falling edges on RDI is sampled on f
and the
CPU
- LDIV_NOM (nominal value written by software at
LPR/LPFR addresses)
result of this measurement is stored in an internal
15-bit register called SM (not user accessible)
(see Figure 61). Then the LDIV value (and its as-
sociated LPFR and LPR registers) are automati-
cally updated at the end of the fifth falling edge.
During LIN Synch field measurement, the SCI
state machine is stopped and no data is trans-
ferred to the data register.
- LDIV_MEAS (results of the Field Synch meas-
urement)
- LDIV (used to generate the local baud rate)
The control and interactions of these registers, ex-
plained in Figure 62 and Figure 63, depend on the
LDUM bit setting (LIN Divider Update Method).
11.5.9.6 LIN Slave Baud Rate Generation
Note:
In LIN mode, transmission and reception are driv-
en by the LIN baud rate generator
As explained in Figure 62 and Figure 63, LDIV can
be updated by two concurrent actions: a transfer
from LDIV_MEAS at the end of the LIN Sync Field
and a transfer from LDIV_NOM due to a software
write of LPR. If both operations occur at the same
time, the transfer from LDIV_NOM has priority.
Note: LIN Master mode uses the Extended or
Conventional prescaler register to generate the
baud rate.
If LINE bit = 1 and LSLV bit = 1 then the Conven-
tional and Extended Baud Rate Generators are
disabled: the baud rate for the receiver and trans-
107/168
ST7L34, ST7L35, ST7L38, ST7L39
LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d)
Figure 62. LDIV Read / Write Operations When LDUM = 0
Write LPFR
Write LPR
LIN Sync Field
Measurement
MANT(7:0) FRAC(3:0)
Write LPR
LDIV_NOM
LDIV_MEAS
MANT(7:0) FRAC(3:0)
Update
at end of
Synch Field
Baud Rate
Generation
MANT(7:0) FRAC(3:0)
LDIV
Read LPR
Read LPFR
Figure 63. LDIV Read / Write Operations When LDUM = 1
Write LPFR
Write LPR
LIN Sync Field
Measurement
MANT(7:0) FRAC(3:0)
RDRF = 1
LDIV_NOM
LDIV_MEAS
MANT(7:0) FRAC(3:0)
Update
at end of
Synch Field
Baud Rate
Generation
MANT(7:0) FRAC(3:0)
LDIV
Read LPR
Read LPFR
108/168
ST7L34, ST7L35, ST7L38, ST7L39
LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d)
11.5.9.7 LINSCI Clock Tolerance
Consequently, the clock frequency should not vary
more than 6/16 (37.5%) within one bit.
LINSCI Clock Tolerance when unsynchronized
The sampling clock is resynchronized at each start
bit, so that when receiving 10 bits (one start bit, 1
data byte, 1 stop bit), the clock deviation should
not exceed 3.75%.
When LIN slaves are unsynchronized (meaning no
characters have been transmitted for a relatively
long time), the maximum tolerated deviation of the
LINSCI clock is +/-15%.
11.5.9.8 Clock Deviation Causes
If the deviation is within this range then the LIN
Synch Break is detected properly when a new re-
ception occurs.
The causes which contribute to the total deviation
are:
This is made possible by the fact that masters
send 13 low bits for the LIN Synch Break, which
can be interpreted as 11 low bits (13 bits -15% =
11.05) by a “fast” slave and then considered as a
LIN Synch Break. According to the LIN specifica-
tion, a LIN Synch Break is valid when its duration
– D
: Deviation due to transmitter error.
TRA
Note: The transmitter can be either a master
or a slave (in case of a slave listening to the
response of another slave).
– D
: Error due to the LIN Synch measure-
MEAS
ment performed by the receiver.
is greater than t
= 10. This means that the
SBRKTS
– D : Error due to the baud rate quantiza-
tion of the receiver.
QUANT
LIN Synch Break must last at least 11 low bits.
Note: If the period desynchronization of the slave
is +15% (slave too slow), the character “00h”
which represents a sequence of 9 low bits must
not be interpreted as a break character (9 bits +
15% = 10.35). Consequently, a valid LIN Synch
break must last at least 11 low bits.
– D
: Deviation of the local oscillator of the
REC
receiver: This deviation can occur during the
reception of one complete LIN message as-
suming that the deviation has been compen-
sated at the beginning of the message.
– D
: Deviation due to the transmission line
TCL
LINSCI Clock Tolerance when Synchronized
(generally due to the transceivers)
When synchronization has been performed, fol-
lowing reception of a LIN Synch Break, the LINS-
CI, in LIN mode, has the same clock deviation tol-
erance as in SCI mode, which is explained below:
All the deviations of the system should be added
and compared to the LINSCI clock tolerance:
D
+ D
+D
+ D
+ D
< 3.75%
TCL
TRA
MEAS
QUANT
REC
During reception, each bit is oversampled 16
times. The mean of the 8th, 9th and 10th samples
is considered as the bit value.
Figure 64.Bit Sampling in Reception Mode
RDI LINE
sampled values
Sample
clock
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
6/16
7/16
7/16
One bit time
109/168
ST7L34, ST7L35, ST7L38, ST7L39
LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d)
11.5.9.9 Error due to LIN Synch measurement
Consequently, at a given CPU frequency, the
maximum possible nominal baud rate (LPR
should be chosen with respect to the maximum tol-
erated deviation given by the equation:
)
MIN
The LIN Synch Field is measured over eight bit
times.
This measurement is performed using a counter
clocked by the CPU clock. The edge detections
are performed using the CPU clock cycle.
D
+ 2 / (128*LDIV ) + 1 / (2*16*LDIV
)
TRA
MIN
MIN
+ D
+ D
< 3.75%
TCL
REC
This leads to a precision of 2 CPU clock cycles for
the measurement which lasts 16*8*LDIV clock cy-
cles.
Example:
A nominal baud rate of 20Kbits/s at T
= 125ns
CPU
Consequently, this error (D
) is equal to:
MEAS
(8 MHz) leads to LDIV
= 25d.
NOM
2 / (128*LDIV ).
MIN
LDIV
= 25 - 0.15*25 = 21.25
MIN
LDIV
corresponds to the minimum LIN prescal-
MIN
D
D
= 2 / (128*LDIV ) * 100 = 0.00073%
MIN
MEAS
er content, leading to the maximum baud rate, tak-
ing into account the maximum deviation of +/-15%.
= 1 / (2*16*LDIV ) * 100 = 0.0015%
QUANT
MIN
11.5.9.10 Error due to Baud Rate Quantization
LIN Slave systems
The baud rate can be adjusted in steps of 1 / (16 *
LDIV). The worst case occurs when the “real”
baud rate is in the middle of the step.
For LIN Slave systems (the LINE and LSLV bits
are set), receivers wake up by LIN Synch Break or
LIN Identifier detection (depending on the LHDM
bit).
This leads to a quantization error (D
) equal
QUANT
to 1 / (2*16*LDIV ).
MIN
Hot Plugging Feature for LIN Slave Nodes
11.5.9.11 Impact of Clock Deviation on
Maximum Baud Rate
In LIN Slave Mute Mode (the LINE, LSLV and
RWU bits are set) it is possible to hot plug to a net-
work during an ongoing communication flow. In
this case the SCI monitors the bus on the RDI line
until 11 consecutive dominant bits have been de-
tected and discards all the other bits received.
The choice of the nominal baud rate (LDIV
)
)
NOM
will influence both the quantization error (D
QUANT
and the measurement error (D
). The worst
MEAS
case occurs for LDIV
.
MIN
110/168
ST7L34, ST7L35, ST7L38, ST7L39
LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d)
11.5.10 LIN Mode Register Description
framing error is detected (if the stop bit is dominant
(0) and at least one of the other bits is recessive
(1). It is not set when a break occurs, the LHDF bit
is used instead as a break flag (if the LHDM
bit = 0). It is cleared by a software sequence (an
access to the SCISR register followed by a read to
the SCIDR register).
STATUS REGISTER (SCISR)
Read Only
Reset Value: 1100 0000 (C0h)
7
0
0: No Framing error
TDRE
TC
RDRF IDLE
LHE
NF
FE
PE
1: Framing error detected
Bits 7:4 = Same function as in SCI mode, please
refer to Section 11.5.8 SCI Mode Register De-
scription.
Bit 0 = PE Parity error.
This bit is set by hardware when a LIN parity error
occurs (if the PCE bit is set) in receiver mode. It is
cleared by a software sequence (a read to the sta-
tus register followed by an access to the SCIDR
data register). An interrupt is generated if PIE = 1
in the SCICR1 register.
Bit 3 = LHE LIN Header Error.
During LIN Header this bit signals three error
types:
0: No LIN parity error
1: LIN Parity error detected
– The LIN Synch Field is corrupted and the SCI is
blocked in LIN Synch State (LSF bit = 1).
– A timeout occurred during LIN Header reception
CONTROL REGISTER 1 (SCICR1)
Read/Write
Reset Value: x000 0000 (x0h)
– An overrun error was detected on one of the
header field (see OR bit description in Section
11.5.8 SCI Mode Register Description).
An interrupt is generated if RIE = 1 in the SCICR2
register. If blocked in the LIN Synch State, the LSF
bit must first be reset (to exit LIN Synch Field state
and then to be able to clear LHE flag). Then it is
cleared by the following software sequence: An
access to the SCISR register followed by a read to
the SCIDR register.
7
0
R8
T8
SCID
M
WAKE PCE
PS
PIE
Bits 7:3 = Same function as in SCI mode; please
refer to Section 11.5.8 SCI Mode Register De-
scription.
0: No LIN Header error
1: LIN Header error detected
Bit 2 = PCE Parity control enable.
This bit is set and cleared by software. It selects
the hardware parity control for LIN identifier parity
check.
Note:
Apart from the LIN Header this bit signals an Over-
run Error as in SCI mode; see description in Sec-
tion 11.5.8 SCI Mode Register Description.
0: Parity control disabled
1: Parity control enabled
When a parity error occurs, the PE bit in the
SCISR register is set.
Bit 2 = NF Noise flag
In LIN Master mode (LINE bit = 1 and LSLV bit = 0)
this bit has the same function as in SCI mode;
please refer to Section 11.5.8 SCI Mode Register
Description.
Bit 1 = Reserved
In LIN Slave mode (LINE bit = 1 and LSLV bit = 1)
this bit has no meaning.
Bit 0 = Same function as in SCI mode; please refer
to Section 11.5.8 SCI Mode Register Description.
Bit 1 = FE Framing error.
In LIN slave mode, this bit is set only when a real
111/168
ST7L34, ST7L35, ST7L38, ST7L39
LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d)
CONTROL REGISTER 2 (SCICR2)
Read/Write
Reset Value: 0000 0000 (00h)
1: LDIV is updated at the next received character
(when RDRF = 1) after a write to the LPR regis-
ter.
Notes:
7
0
- If no write to LPR is performed between the set-
ting of LDUM bit and the reception of the next
character, LDIV will be updated with the old value.
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
- After LDUM has been set, it is possible to reset
the LDUM bit by software. In this case, LDIV can
be modified by writing into LPR / LPFR registers.
Bits 7:2 Same function as in SCI mode; please re-
fer to Section 11.5.8 SCI Mode Register Descrip-
tion.
Bit 1 = RWU Receiver wake-up.
Bits 6:5 = LINE, LSLV LIN Mode Enable Bits.
This bit determines if the SCI is in mute mode or
not. It is set and cleared by software and can be
cleared by hardware when a wake-up sequence is
recognized.
These bits configure the LIN mode:
LINE
LSLV
Meaning
0
x
0
1
LIN mode disabled
LIN Master Mode
LIN Slave Mode
0: Receiver in active mode
1: Receiver in mute mode
1
Notes:
– Mute mode is recommended for detecting only
the Header and avoiding the reception of any
other characters. For more details, please refer
to Section 11.5.9.3 LIN Reception.
The LIN Master configuration enables:
The capability to send LIN Synch Breaks (13 low
bits) using the SBK bit in the SCICR2 register.
The LIN Slave configuration enables:
– In LIN slave mode, when RDRF is set, the soft-
ware can not set or clear the RWU bit.
– The LIN Slave Baud Rate generator. The LIN
Divider (LDIV) is then represented by the LPR
and LPFR registers. The LPR and LPFR reg-
isters are read/write accessible at the address
of the SCIBRR register and the address of the
SCIETPR register
Bit 0 = SBK Send break.
This bit set is used to send break characters. It is
set and cleared by software.
0: No break character is transmitted
1: Break characters are transmitted
– Management of LIN Headers.
Note: If the SBK bit is set to “1” and then to “0”, the
transmitter will send a BREAK word at the end of
the current word.
– LIN Synch Break detection (11-bit dominant).
– LIN Wake-Up method (see LHDM bit) instead
of the normal SCI Wake-Up method.
– Inhibition of Break transmission capability
(SBK has no effect)
CONTROL REGISTER 3 (SCICR3)
Read/Write
Reset Value: 0000 0000 (00h)
– LIN Parity Checking (in conjunction with the
PCE bit)
7
0
Bit 4 = LASE LIN Auto Synch Enable.
This bit enables the Auto Synch Unit (ASU). It is
set and cleared by software. It is only usable in LIN
Slave mode.
LDUM LINE LSLV
LASE
LHDM LHIE LHDF LSF
Bit 7 = LDUM LIN Divider Update Method.
This bit is set and cleared by software and is also
cleared by hardware (when RDRF = 1). It is only
used in LIN Slave mode. It determines how the LIN
Divider can be updated by software.
0: LDIV is updated as soon as LPR is written (if no
Auto Synchronization update occurs at the
same time).
0: Auto Synch Unit disabled
1: Auto Synch Unit enabled.
Bit 3 = LHDM LIN Header Detection Method
This bit is set and cleared by software. It is only us-
able in LIN Slave mode. It enables the Header De-
tection Method. In addition if the RWU bit in the
112/168
ST7L34, ST7L35, ST7L38, ST7L39
LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d)
SCICR2 register is set, the LHDM bit selects the
Wake-Up method (replacing the WAKE bit).
0: LIN Synch Break Detection Method
Figure 65. LSF Bit Set and Clear
11 dominant bits
parity bits
1: LIN Identifier Field Detection Method
LSF bit
Bit 2 = LHIE LIN Header Interrupt Enable
This bit is set and cleared by software. It is only us-
able in LIN Slave mode.
LIN Synch
Break
LIN Synch
Field
Identifier
Field
0: LIN Header Interrupt is inhibited.
1: An SCI interrupt is generated whenever
LHDF = 1.
LIN DIVIDER REGISTERS
Bit 1 = LHDF LIN Header Detection Flag
This bit is set by hardware when a LIN Header is
detected and cleared by a software sequence (an
access to the SCISR register followed by a read of
the SCICR3 register). It is only usable in LIN Slave
mode.
LDIV is coded using the two registers LPR and LP-
FR. In LIN Slave mode, the LPR register is acces-
sible at the address of the SCIBRR register and
the LPFR register is accessible at the address of
the SCIETPR register.
0: No LIN Header detected.
LIN PRESCALER REGISTER (LPR)
Read/Write
Reset Value: 0000 0000 (00h)
1: LIN Header detected.
Notes: The header detection method depends on
the LHDM bit:
7
0
– If LHDM = 0, a header is detected as a LIN
Synch Break.
LPR7 LPR6 LPR5 LPR4 LPR3 LPR2 LPR1 LPR0
– If LHDM = 1, a header is detected as a LIN
Identifier, meaning that a LIN Synch Break
Field + a LIN Synch Field + a LIN Identifier
Field have been consecutively received.
LPR[7:0] LIN Prescaler (mantissa of LDIV)
These 8 bits define the value of the mantissa of the
LIN Divider (LDIV):
Bit 0 = LSF LIN Synch Field State
LPR[7:0]
00h
Rounded Mantissa (LDIV)
This bit indicates that the LIN Synch Field is being
analyzed. It is only used in LIN Slave mode. In
Auto Synchronization Mode (LASE bit = 1), when
the SCI is in the LIN Synch Field State it waits or
counts the falling edges on the RDI line.
SCI clock disabled
01h
1
...
...
FEh
FFh
254
255
It is set by hardware as soon as a LIN Synch Break
is detected and cleared by hardware when the LIN
Synch Field analysis is finished (see Figure 65).
This bit can also be cleared by software to exit LIN
Synch State and return to idle mode.
0: The current character is not the LIN Synch Field
1: LIN Synch Field State (LIN Synch Field under-
going analysis)
Caution: LPR and LPFR registers have different
meanings when reading or writing to them. Conse-
quently bit manipulation instructions (BRES or
BSET) should never be used to modify the
LPR[7:0] bits, or the LPFR[3:0] bits.
113/168
ST7L34, ST7L35, ST7L38, ST7L39
LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d)
LIN PRESCALER FRACTION REGISTER
(LPFR)
will effectively update LDIV and so the clock gen-
eration.
Read/Write
2. In LIN Slave mode, if the LPR[7:0] register is
equal to 00h, the transceiver and receiver input
clocks are switched off.
Reset Value: 0000 0000 (00h)
7
0
LPFR LPFR LPFR LPFR
Examples of LDIV coding:
Example 1: LPR = 27d and LPFR = 12d
This leads to:
0
0
0
0
3
2
1
0
Mantissa (LDIV) = 27d
Bits 7:4 = Reserved.
Bits 3:0 = LPFR[3:0] Fraction of LDIV
Fraction (LDIV) = 12/16 = 0.75d
Therefore LDIV = 27.75d
These 4 bits define the fraction of the LIN Divider
(LDIV):
Example 2: LDIV = 25.62d
This leads to:
LPFR[3:0]
Fraction (LDIV)
0h
1h
...
0
LPFR = rounded(16*0.62d)
= rounded(9.92d) = 10d = Ah
LPR = mantissa (25.620d) = 25d = 1Bh
1/16
...
Eh
Fh
14/16
15/16
Example 3: LDIV = 25.99d
This leads to:
1. When initializing LDIV, the LPFR register must
be written first. Then, the write to the LPR register
LPFR = rounded(16*0.99d)
= rounded(15.84d) = 16d
114/168
ST7L34, ST7L35, ST7L38, ST7L39
LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d)
LIN HEADER LENGTH REGISTER (LHLR)
Read Only
LHL[1:0]
Fraction (57 - T
)
HEADER
0h
1h
2h
3h
0
Reset Value: 0000 0000 (00h).
1/4
1/2
3/4
7
0
LHL7 LHL6 LHL5 LHL4 LHL3 LHL2 LHL1 LHL0
Example of LHL coding:
Note: In LIN Slave mode when LASE = 1 or LHDM
= 1, the LHLR register is accessible at the address
of the SCIERPR register.
Example 1: LHL = 33h = 001100 11b
LHL(7:3) = 1100b = 12d
LHL(1:0) = 11b = 3d
Otherwise this register is always read as 00h.
This leads to:
Bits 7:0 = LHL[7:0] LIN Header Length.
Mantissa (57 - T
) = 12d
HEADER
This is a read-only register, which is updated by
hardware if one of the following conditions occurs:
- After each break detection, it is loaded with
“FFh”.
Fraction (57 - T
Therefore:
) = 3/4 = 0.75
HEADER
(57 - T
and T
) = 12.75d
= 44.25d
HEADER
- If a timeout occurs on T
00h.
, it is loaded with
HEADER
HEADER
- After every successful LIN Header reception (at
the same time than the setting of LHDF bit), it is
loaded with a value (LHL) which gives access to
the number of bit times of the LIN header length
HEADER
below:
Example 2:
57 - T
= 36.21d
HEADER
LHL(1:0) = rounded(4*0.21d) = 1d
(T
). The coding of this value is explained
LHL(7:2) = Mantissa (36.21d) = 36d = 24h
Therefore LHL(7:0) = 10010001 = 91h
LHL Coding:
T
= 57
HEADER_MAX
LHL(7:2) represents the mantissa of (57 - T
ER
Example 3:
HEAD-
)
57 - T
= 36.90d
HEADER
LHL(1:0) represents the fraction (57 - T
)
HEADER
LHL(1:0) = rounded(4*0.90d) = 4d
Mantissa
(57 - T
Mantissa
The carry must be propagated to the matissa:
LHL(7:2) = Mantissa (36.90d) + 1 = 37d =
Therefore LHL(7:0) = 10110000 = A0h
LHL[7:2]
)
(T
)
HEADER
HEADER
0h
1h
0
57
1
56
...
1
...
...
39h
3Ah
3Bh
...
56
57
58
...
0
Never Occurs
...
3Eh
3Fh
62
63
Never Occurs
Initial value
115/168
ST7L34, ST7L35, ST7L38, ST7L39
LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Master/Slave) (cont’d)
Table 21. LINSCI1 Register Map and Reset Values
Addr.
Register Name
7
6
5
4
3
2
1
0
(Hex.)
SCISR
TDRE
TC
1
RDRF
0
IDLE
OR/LHE
NF
0
FE
0
PE
0
40
Reset Value
SCIDR
1
DR7
-
0
DR4
-
0
DR3
-
DR6
-
DR5
-
DR2
-
DR1
-
DR0
-
41
42
Reset Value
SCP1
LPR7
0
SCP0
LPR6
0
SCT2
LPR5
0
SCT1
LPR4
0
SCT0
LPR3
0
SCR2
LPR2
0
SCR1
LPR1
0
SCR0
LPR0
0
SCIBRR
LPR (LIN Slave Mode)
Reset Value
SCICR1
R8
x
T8
SCID
0
M
WAKE
0
PCE
0
PS
0
PIE
0
43
44
45
Reset Value
SCICR2
0
0
TIE
0
TCIE
0
RIE
0
ILIE
0
TE
RE
0
RWU
0
SBK
0
Reset Value
SCICR3
0
NP
0
LINE
0
LSLV
0
LASE
0
LHDM
0
LHIE
0
LHDF
0
LSF
0
Reset Value
SCIERPR
ERPR7 ERPR6 ERPR5 ERPR4 ERPR3 ERPR2 ERPR1 ERPR0
46
47
LHLR (LIN Slave Mode)
Reset Value
LHL7
0
LHL6
0
LHL5
0
LHL4
0
LHL3
0
LHL2
0
LHL1
0
LHL0
0
ETPR7 ETPR6 ETPR5 ETPR4 ETPR3 ETPR2 ETPR1 ETPR0
SCITPR
LDUM
0
0
0
0
0
0
0
LPFR3
0
LPFR2 LPFR1 LPFR0
LPFR (LIN Slave Mode)
Reset Value
0
0
0
116/168
ST7L34, ST7L35, ST7L38, ST7L39
11.6 10-BIT A/D CONVERTER (ADC)
11.6.1 Introduction
■ Data register (DR) which contains the results
■ Conversion complete status flag
■ On/off bit (to reduce consumption)
The block diagram is shown in Figure 66.
The on-chip Analog to Digital Converter (ADC) pe-
ripheral is a 10-bit, successive approximation con-
verter with internal sample and hold circuitry. This
peripheral has up to seven multiplexed analog in-
put channels (refer to device pin out description)
that allow the peripheral to convert the analog volt-
age levels from up to seven different sources.
11.6.3 Functional Description
11.6.3.1 Analog Power Supply
V
and V
are the high and low level refer-
SSA
DDA
The result of the conversion is stored in a 10-bit
Data Register. The A/D converter is controlled
through a Control/Status Register.
ence voltage pins. In some devices (refer to device
pin out description) they are internally connected
to the V and V pins.
DD
SS
11.6.2 Main Features
■ 10-bit conversion
■ Up to 7 channels with multiplexed input
■ Linear successive approximation
Conversion accuracy may therefore be impacted
by voltage drops and noise in the event of heavily
loaded or badly decoupled power supply lines.
Figure 66. ADC Block Diagram
DIV 4
1
f
f
ADC
CPU
DIV 2
0
1
0
SLOW
bit
0
EOC SPEEDADON
0
CH2 CH1 CH0
ADCCSR
3
AIN0
AIN1
HOLD CONTROL
R
ADC
ANALOG TO DIGITAL
CONVERTER
ANALOG
MUX
AINx
C
ADC
ADCDRH
D9
D8
D7
D6
D5 D4 D3 D2
0
0
0
ADCDRL
0
0
SLOW
D1
D0
117/168
ST7L34, ST7L35, ST7L38, ST7L39
10-BIT A/D CONVERTER (ADC) (cont’d)
11.6.3.2 Digital A/D Conversion Result
When a conversion is complete:
The conversion is monotonic, meaning that the re-
sult never decreases if the analog input does not
and never increases if the analog input does not.
– The EOC bit is set by hardware.
– The result is in the ADCDR registers.
A read to the ADCDRH resets the EOC bit.
If the input voltage (V ) is greater than V
AIN
DDA
(high-level voltage reference) then the conversion
result is FFh in the ADCDRH register and 03h in
the ADCDRL register (without overflow indication).
To read the 10 bits, perform the following steps:
1. Poll EOC bit
If the input voltage (V ) is lower than V
level voltage reference) then the conversion result
in the ADCDRH and ADCDRL registers is 00 00h.
(low-
2. Read ADCDRL
AIN
SSA
3. Read ADCDRH. This clears EOC automati-
cally.
The A/D converter is linear and the digital result of
the conversion is stored in the ADCDRH and AD-
CDRL registers. The accuracy of the conversion is
described in the Electrical Characteristics Section.
To read only 8 bits, perform the following steps:
1. Poll EOC bit
R
is the maximum recommended impedance
2. Read ADCDRH. This clears EOC automati-
cally.
AIN
for an analog input signal. If the impedance is too
high, this will result in a loss of accuracy due to
leakage and sampling not being completed in the
alloted time.
11.6.4 Low Power Modes
11.6.3.3 A/D Conversion
Note: The A/D converter may be disabled by re-
setting the ADON bit. This feature allows reduced
power consumption when no conversion is need-
ed and between single shot conversions.
The analog input ports must be configured as in-
put, no pull-up, no interrupt. Refer to the “I/O ports”
chapter. Using these pins as analog inputs does
not affect the ability of the port to be read as a logic
input.
Mode
Description
WAIT
No effect on A/D Converter
A/D Converter disabled.
In the ADCCSR register:
– Select the CS[2:0] bits to assign the analog
channel to convert.
After wakeup from Halt mode, the A/D
Converter requires a stabilization time
ADC Conversion mode
HALT
t
(see Electrical Characteristics)
STAB
In the ADCCSR register:
before accurate conversions are per-
formed.
Set the ADON bit to enable the A/D converter and
to start the conversion. From this time on, the
ADC performs a continuous conversion of the
selected channel.
11.6.5 Interrupts
None.
118/168
ST7L34, ST7L35, ST7L38, ST7L39
10-BIT A/D CONVERTER (ADC) (cont’d)
11.6.6 Register Description
CONTROL/STATUS REGISTER (ADCCSR)
Read/Write (Except bit 7 read only)
Reset Value: 0000 0000 (00h)
DATA REGISTER HIGH (ADCDRH)
Read Only
Reset Value: 0000 0000 (00h)
7
0
7
0
EOC SPEED ADON
0
0
CH2
CH1
CH0
D9
D8
D7
D6
D5
D4
D3
D2
Bit 7 = EOC End of Conversion
This bit is set by hardware. It is cleared by soft-
ware reading the ADCDRH register.
0: Conversion is not complete
Bits 7:0 = D[9:2] MSB of Analog Converted Value
CONTROL AND DATA REGISTER LOW (AD-
CDRL)
1: Conversion complete
Read/Write
Bit 6 = SPEED ADC clock selection
This bit is set and cleared by software. It is used
together with the SLOW bit to configure the ADC
clock speed. Refer to the table in the SLOW bit de-
scription.
Reset Value: 0000 0000 (00h)
7
0
0
0
0
0
SLOW
0
D1
D0
Bit 5 = ADON A/D Converter on
This bit is set and cleared by software.
0: A/D converter is switched off
1: A/D converter is switched on
Bits 7:5 = Reserved. Forced by hardware to 0.
Bit 4 = Reserved. Forced by hardware to 0.
Bits 4:3 = Reserved. Must be kept cleared.
Bit 3 = SLOW Slow mode
This bit is set and cleared by software. It is used
together with the SPEED bit to configure the ADC
clock speed as shown on the table below.
Bits 2:0 = CH[2:0] Channel Selection
These bits are set and cleared by software. They
select the analog input to convert.
f
SLOW SPEED
ADC
Channel Pin*
AIN0
CH2 CH1 CH0
f
/2
0
0
1
0
1
x
CPU
f
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
CPU
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
f
/4
CPU
Bit 2 = Reserved. Forced by hardware to 0.
Bits 1:0 = D[1:0] LSB of Analog Converted Value
*The number of channels is device dependent. Refer to
the device pinout description.
119/168
ST7L34, ST7L35, ST7L38, ST7L39
10-BIT A/D CONVERTER (ADC) (cont’d)
Table 22. ADC Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
ADCCSR
Reset Value
EOC
0
SPEED
0
ADON
0
0
0
0
0
CH2
0
CH1
0
CH0
0
0034h
0035h
0036h
ADCDRH
Reset Value
D9
0
D8
0
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
ADCDRL
Reset Value
0
0
0
0
0
0
0
0
SLOW
0
0
0
D1
0
D0
0
120/168
ST7L34, ST7L35, ST7L38, ST7L39
12 INSTRUCTION SET
12.1 ST7 ADDRESSING MODES
The ST7 Instruction set is designed to minimize
the number of bytes required per instruction: To do
so, most of the addressing modes may be subdi-
vided in two submodes called long and short:
The ST7 Core features 17 different addressing
modes which can be classified in seven main
groups:
– Long addressing mode is more powerful be-
cause it can use the full 64 Kbyte address space,
however it uses more bytes and more CPU cy-
cles.
Addressing Mode
Inherent
Example
nop
Immediate
Direct
ld A,#$55
ld A,$55
– Short addressing mode is less powerful because
it can generally only access page zero (0000h -
00FFh range), but the instruction size is more
compact, and faster. All memory to memory in-
structions use short addressing modes only
(CLR, CPL, NEG, BSET, BRES, BTJT, BTJF,
INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP)
Indexed
Indirect
ld A,($55,X)
ld A,([$55],X)
jrne loop
Relative
Bit operation
bset byte,#5
The ST7 Assembler optimizes the use of long and
short addressing modes.
Table 23. ST7 Addressing Mode Overview
Pointer
Address
(Hex.)
Pointer
Size
(Hex.)
Destination/
Source
Length
(Bytes)
Mode
Syntax
Inherent
Immediate
Short
nop
+ 0
+ 1
+ 1
+ 2
ld A,#$55
ld A,$10
Direct
Direct
00..FF
Long
ld A,$1000
0000..FFFF
+ 0 (with X register)
+ 1 (with Y register)
No Offset
Direct
Indexed
ld A,(X)
00..FF
Short
Long
Short
Long
Short
Long
Relative
Relative
Bit
Direct
Indexed
Indexed
ld A,($10,X)
ld A,($1000,X)
ld A,[$10]
00..1FE
+ 1
+ 2
+ 2
+ 2
+ 2
+ 2
+ 1
+ 2
+ 1
+ 2
+ 2
+ 3
Direct
0000..FFFF
00..FF
Indirect
Indirect
00..FF
00..FF
00..FF
00..FF
byte
word
byte
word
ld A,[$10.w]
ld A,([$10],X)
0000..FFFF
00..1FE
Indirect Indexed
Indirect Indexed
Direct
ld A,([$10.w],X) 0000..FFFF
1)
1)
jrne loop
PC-128/PC+127
Indirect
jrne [$10]
PC-128/PC+127
00..FF
00..FF
00..FF
00..FF
byte
byte
byte
Direct
bset $10,#7
bset [$10],#7
Bit
Indirect
00..FF
Bit
Direct
Relative btjt $10,#7,skip 00..FF
Bit
Indirect Relative btjt [$10],#7,skip 00..FF
Note:
1. At the time the instruction is executed, the Program Counter (PC) points to the instruction following JRxx.
121/168
ST7L34, ST7L35, ST7L38, ST7L39
ST7 ADDRESSING MODES (cont’d)
12.1.1 Inherent
12.1.3 Direct
All Inherent instructions consist of a single byte.
The opcode fully specifies all the required informa-
tion for the CPU to process the operation.
In Direct instructions, the operands are referenced
by their memory address.
The direct addressing mode consists of two sub-
modes:
Inherent Instruction
Function
No operation
Direct (Short)
NOP
The address is a byte, thus requires only 1 byte af-
ter the opcode, but only allows 00 - FF addressing
space.
TRAP
S/W Interrupt
Wait For Interrupt (Low Power
Mode)
WFI
Direct (Long)
Halt Oscillator (Lowest Power
Mode)
HALT
The address is a word, thus allowing 64 Kbyte ad-
dressing space, but requires 2 bytes after the op-
code.
RET
Subroutine Return
Interrupt Subroutine Return
Set Interrupt Mask
Reset Interrupt Mask
Set Carry Flag
IRET
12.1.4 Indexed (No Offset, Short, Long)
SIM
In this mode, the operand is referenced by its
memory address, which is defined by the unsigned
addition of an index register (X or Y) with an offset.
RIM
SCF
The indirect addressing mode consists of three
submodes:
RCF
Reset Carry Flag
Reset Stack Pointer
Load
RSP
Indexed (No Offset)
LD
There is no offset (no extra byte after the opcode),
and allows 00 - FF addressing space.
CLR
Clear
PUSH/POP
INC/DEC
TNZ
Push/Pop to/from the stack
Increment/Decrement
Test Negative or Zero
1 or 2 Complement
Byte Multiplication
Indexed (Short)
The offset is a byte, thus requires only 1 byte after
the opcode and allows 00 - 1FE addressing space.
CPL, NEG
MUL
Indexed (Long)
The offset is a word, thus allowing 64 Kbyte ad-
dressing space and requires 2 bytes after the op-
code.
SLL, SRL, SRA, RLC,
RRC
Shift and Rotate Operations
Swap Nibbles
12.1.5 Indirect (Short, Long)
SWAP
The required data byte to do the operation is found
by its memory address, located in memory (point-
er).
12.1.2 Immediate
Immediate instructions have 2 bytes, the first byte
contains the opcode, the second byte contains the
operand value.
The pointer address follows the opcode. The indi-
rect addressing mode consists of two submodes:
Indirect (Short)
Immediate Instruction
Function
The pointer address is a byte, the pointer size is a
byte, thus allowing 00 - FF addressing space, and
requires 1 byte after the opcode.
LD
Load
CP
Compare
BCP
Bit Compare
Indirect (Long)
AND, OR, XOR
ADC, ADD, SUB, SBC
Logical Operations
Arithmetic Operations
The pointer address is a byte, the pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.
122/168
ST7L34, ST7L35, ST7L38, ST7L39
12.1.7 Relative Mode (Direct, Indirect)
ST7 ADDRESSING MODES (cont’d)
12.1.6 Indirect Indexed (Short, Long)
This is a combination of indirect and short indexed
addressing modes. The operand is referenced by
its memory address, which is defined by the un-
signed addition of an index register value (X or Y)
with a pointer value located in memory. The point-
er address follows the opcode.
This addressing mode is used to modify the PC
register value by adding an 8-bit signed offset to it.
Available Relative Direct/
Function
Indirect Instructions
JRxx
Conditional Jump
Call Relative
The indirect indexed addressing mode consists of
two submodes:
CALLR
The relative addressing mode consists of two sub-
modes:
Indirect Indexed (Short)
The pointer address is a byte, the pointer size is a
byte, thus allowing 00 - 1FE addressing space,
and requires 1 byte after the opcode.
Relative (Direct)
The offset follows the opcode.
Relative (Indirect)
Indirect Indexed (Long)
The pointer address is a byte, the pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.
The offset is defined in memory, of which the ad-
dress follows the opcode.
Table 24. Instructions Supporting Direct,
Indexed, Indirect and Indirect Indexed
Addressing Modes
Long and Short
Function
Instructions
LD
Load
CP
Compare
AND, OR, XOR
Logical Operations
Arithmetic Addition/subtrac-
tion operations
ADC, ADD, SUB, SBC
BCP
Bit Compare
Short Instructions Only
CLR
Function
Clear
INC, DEC
Increment/Decrement
Test Negative or Zero
1 or 2 Complement
Bit Operations
TNZ
CPL, NEG
BSET, BRES
Bit Test and Jump Opera-
tions
BTJT, BTJF
SLL, SRL, SRA, RLC,
RRC
Shift and Rotate Operations
SWAP
Swap Nibbles
CALL, JP
Call or Jump subroutine
123/168
ST7L34, ST7L35, ST7L38, ST7L39
12.2 INSTRUCTION GROUPS
The ST7 family devices use an Instruction Set
consisting of 63 instructions. The instructions may
be subdivided into 13 main groups as illustrated in
the following table:
Load and Transfer
LD
CLR
POP
DEC
TNZ
OR
Stack operation
PUSH
INC
RSP
BCP
Increment/Decrement
Compare and Tests
Logical operations
CP
AND
BSET
BTJT
ADC
SLL
XOR
CPL
NEG
Bit Operation
BRES
BTJF
ADD
SRL
JRT
Conditional Bit Test and Branch
Arithmetic operations
Shift and Rotates
SUB
SRA
JRF
SBC
RLC
JP
MUL
RRC
CALL
SWAP
CALLR
SLA
Unconditional Jump or Call
Conditional Branch
JRA
JRxx
TRAP
SIM
NOP
RET
Interruption management
Condition Code Flag modification
WFI
RIM
HALT
SCF
IRET
RCF
Using a prebyte
PDY 90 Replace an X based instruction using
immediate, direct, indexed, or inherent
addressing mode by a Y one.
The instructions are described with 1 to 4 bytes.
In order to extend the number of available op-
codes for an 8-bit CPU (256 opcodes), three differ-
ent prebyte opcodes are defined. These prebytes
modify the meaning of the instruction they pre-
cede.
PIX 92 Replace an instruction using direct, di-
rect bit or direct relative addressing
mode to an instruction using the corre-
sponding indirect addressing mode.
It also changes an instruction using X
indexed addressing mode to an instruc-
tion using indirect X indexed addressing
mode.
The whole instruction becomes:
PC-2 End of previous instruction
PC-1 Prebyte
PIY 91 Replace an instruction using X indirect
indexed addressing mode by a Y one.
PC
Opcode
PC+1 Additional word (0 to 2) according to the
number of bytes required to compute the
effective address
12.2.1 Illegal Opcode Reset
In order to provide enhanced robustness to the de-
vice against unexpected behavior, a system of ille-
gal opcode detection is implemented. If a code to
be executed does not correspond to any opcode
or prebyte value, a reset is generated. This, com-
bined with the Watchdog, allows the detection and
recovery from an unexpected fault or interference.
These prebytes enable instruction in Y as well as
indirect addressing modes to be implemented.
They precede the opcode of the instruction in X or
the instruction using direct addressing mode. The
prebytes are:
Note: A valid prebyte associated with a valid op-
code forming an unauthorized combination does
not generate a reset.
124/168
ST7L34, ST7L35, ST7L38, ST7L39
INSTRUCTION GROUPS (cont’d)
Mnemo
ADC
ADD
AND
BCP
Description
Add with Carry
Function/Example
A = A + M + C
A = A + M
Dst
Src
H
H
H
I
N
N
N
N
N
Z
Z
Z
Z
Z
C
C
C
A
A
M
M
M
M
Addition
Logical And
A = A . M
A
Bit compare A, Memory
Bit Reset
tst (A . M)
A
BRES
BSET
BTJF
BTJT
CALL
CALLR
CLR
bres Byte, #3
bset Byte, #3
btjf Byte, #3, Jmp1
btjt Byte, #3, Jmp1
M
M
M
M
Bit Set
Jump if bit is false (0)
Jump if bit is true (1)
Call subroutine
Call subroutine relative
Clear
C
C
reg, M
reg
0
N
N
N
1
Z
Z
Z
CP
Arithmetic Compare
One Complement
Decrement
tst(Reg - M)
A = FFH-A
dec Y
M
C
1
CPL
reg, M
reg, M
DEC
HALT
IRET
INC
Halt
0
I
Interrupt routine return
Increment
Pop CC, A, X, PC
inc X
H
N
N
Z
Z
C
reg, M
JP
Absolute Jump
Jump relative always
Jump relative
jp [TBL.w]
JRA
JRT
JRF
Never jump
jrf *
JRIH
JRIL
Jump if ext. interrupt = 1
Jump if ext. interrupt = 0
Jump if H = 1
JRH
H = 1 ?
JRNH
JRM
Jump if H = 0
H = 0 ?
Jump if I = 1
I = 1 ?
JRNM
JRMI
JRPL
JREQ
JRNE
JRC
Jump if I = 0
I = 0 ?
Jump if N = 1 (minus)
Jump if N = 0 (plus)
Jump if Z = 1 (equal)
Jump if Z = 0 (not equal)
Jump if C = 1
N = 1 ?
N = 0 ?
Z = 1 ?
Z = 0 ?
C = 1 ?
JRNC
JRULT
Jump if C = 0
C = 0 ?
Jump if C = 1
Unsigned <
Jmp if unsigned >=
Unsigned >
JRUGE Jump if C = 0
JRUGT Jump if (C + Z = 0)
125/168
ST7L34, ST7L35, ST7L38, ST7L39
INSTRUCTION GROUPS (cont’d)
Mnemo
JRULE
LD
Description
Jump if (C + Z = 1)
Load
Function/Example
Unsigned <=
dst <= src
Dst
Src
H
I
N
N
N
N
N
Z
Z
Z
Z
Z
C
reg, M
A, X, Y
reg, M
M, reg
X, Y, A
MUL
NEG
NOP
OR
Multiply
X,A = X * A
0
0
Negate (2's compl)
No Operation
OR operation
Pop from the Stack
neg $10
C
A = A + M
pop reg
pop CC
push Y
C = 0
A
M
POP
reg
CC
M
M
M
H
I
C
0
PUSH
RCF
RET
RIM
Push onto the Stack
Reset carry flag
Subroutine Return
Enable Interrupts
Rotate left true C
Rotate right true C
Reset Stack Pointer
Subtract with Carry
Set carry flag
reg, CC
I = 0
0
RLC
RRC
RSP
SBC
SCF
SIM
C <= Dst <= C
C => Dst => C
S = Max allowed
A = A - M - C
C = 1
reg, M
reg, M
N
N
Z
Z
C
C
A
M
N
Z
C
1
Disable Interrupts
Shift left Arithmetic
Shift left Logic
I = 1
1
SLA
C <= Dst <= 0
C <= Dst <= 0
0 => Dst => C
Dst7 => Dst => C
A = A - M
reg, M
reg, M
reg, M
reg, M
A
N
N
0
Z
Z
Z
Z
Z
Z
Z
C
C
C
C
C
SLL
SRL
SRA
SUB
SWAP
TNZ
TRAP
WFI
Shift right Logic
Shift right Arithmetic
Subtraction
N
N
N
N
M
M
SWAP nibbles
Dst[7..4] <=> Dst[3..0] reg, M
tnz lbl1
Test for Neg & Zero
S/W trap
S/W interrupt
1
0
Wait for Interrupt
Exclusive OR
XOR
A = A XOR M
A
N
Z
126/168
ST7L34, ST7L35, ST7L38, ST7L39
13 ELECTRICAL CHARACTERISTICS
13.1 PARAMETER CONDITIONS
Unless otherwise specified, all voltages are re-
13.1.5 Pin Input Voltage
ferred to V
.
SS
The input voltage measurement on a pin of the de-
vice is described in Figure 68.
13.1.1 Minimum and Maximum Values
Unless otherwise specified, the minimum and
maximum values are guaranteed in the worst con-
ditions of ambient temperature, supply voltage and
frequencies by tests in production on 100% of the
Figure 68. Pin Input Voltage
ST7 PIN
devices with an ambient temperature at T = 25°C
A
and T = T max (given by the selected tempera-
A
A
ture range).
V
IN
Data based on characterization results, design
simulation and/or technology characteristics are
indicated in the table footnotes and are not tested
in production. Based on characterization, the min-
imum and maximum values refer to sample tests
and represent the mean value plus or minus three
times the standard deviation (mean 3Σ).
13.1.2 Typical Values
Unless otherwise specified, typical data is based
on T = 25°C, V = 5V (for the 4.5V ≤ V ≤ 5.5V
A
DD
DD
voltage range) and V = 3.3V (for the 3V ≤ V
≤
DD
DD
3.6V voltage range). They are given only as de-
sign guidelines and are not tested.
13.1.3 Typical Curves
Unless otherwise specified, all typical curves are
given only as design guidelines and are not tested.
13.1.4 Loading Capacitor
The loading conditions used for pin parameter
measurement are shown in Figure 67.
Figure 67. Pin Loading Conditions
ST7 PIN
C
L
127/168
ST7L34, ST7L35, ST7L38, ST7L39
ELECTRICAL CHARACTERISTICS (cont’d)
13.2 ABSOLUTE MAXIMUM RATINGS
Stresses above those listed as “absolute maxi-
mum ratings” may cause permanent damage to
the device. This is a stress rating only and func-
tional operation of the device under these condi-
tions is not implied. Exposure to maximum rating
conditions for extended periods may affect device
reliability.
13.2.1 Voltage Characteristics
Symbol
- V
Ratings
Maximum value
7.0
Unit
V
Supply voltage
DD
SS
V
1) and 2)
V
Input voltage on any pin
VSS - 0.3 to VDD + 0.3
IN
ESD(HBM)
see section 13.7.3 on page 140
see section 13.7.3 on page 140
V
Electrostatic discharge voltage (Human Body Model)
Electrostatic discharge voltage (Machine Model)
V
ESD(MM)
13.2.2 Current Characteristics
Symbol
Ratings
Maximum value
Unit
3)
3)
I
Total current into V power lines (source)
150
150
20
40
-25
5
VDD
DD
I
Total current out of V ground lines (sink)
SS
VSS
Output current sunk by any standard I/O and control pin
Output current sunk by any high sink I/O pin
Output current source by any I/Os and control pin
Injected current on RESET pin
I
IO
mA
2)4)
2)
I
Injected current on OSC1 and OSC2 pins
5
INJ(PIN)
5)
Injected current on any other pin
5
5)
ΣI
Total injected current (sum of all I/O and control pins)
20
INJ(PIN)
13.2.3 Thermal Characteristics
Symbol
Ratings
Value
Unit
T
Storage temperature range
-65 to +150
°C
STG
T
Maximum junction temperature (see section 14.2 on page 153)
J
Notes:
1. Directly connecting the RESET and I/O pins to V or V could damage the device if an unintentional internal reset
DD
SS
is generated or an unexpected change of the I/O configuration occurs (for example, due to a corrupted program counter).
To guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typically 4.7kΩ for
RESET, 10kΩ for I/Os). Unused I/O pins must be tied in the same way to V or V according to their reset configuration.
DD
SS
2. I
must never be exceeded. This is implicitly insured if V maximum is respected. If V maximum cannot be
INJ(PIN)
IN
INJ(PIN)
IN
respected, the injection current must be limited externally to the I
value. A positive injection is induced by V >V
IN DD
while a negative injection is induced by V < V . For true open-drain pads, there is no positive injection current and the
IN
SS
corresponding V maximum must always be respected
IN
3. All power (V ) and ground (V ) lines must always be connected to the external supply.
DD
SS
4. Negative injection disturbs the analog performance of the device. In particular, it induces leakage currents throughout
the device including the analog inputs. To avoid undesirable effects on the analog functions, care must be taken:
- Analog input pins must have a negative injection less than 0.8 mA (assuming that the impedance of the analog voltage
is lower than the specified limits)
- Pure digital pins must have a negative injection less than 1.6mA. In addition, it is recommended to inject the current as
far as possible from the analog input pins.
5. When several inputs are submitted to a current injection, the maximum ΣI
is the absolute sum of the positive
INJ(PIN)
and negative injected currents (instantaneous values). These results are based on characterization with ΣI
maxi-
INJ(PIN)
mum current injection on four I/O port pins of the device.
128/168
ST7L34, ST7L35, ST7L38, ST7L39
ELECTRICAL CHARACTERISTICS (cont’d)
13.3 OPERATING CONDITIONS
13.3.1 General Operating Conditions
T = -40 to +125°C, unless otherwise specified.
A
Symbol
Parameter
Supply voltage
Conditions
= 16 MHz max
Min
Max
Unit
f
OSC
V
3.0
5.5
V
DD
T = -40°C to T max
A
A
External clock frequency on
CLKIN pin
f
V
≥ 3V
DD
0
16
MHz
°C
CLKIN
A Suffix version
C Suffix version
+85
T
Ambient temperature range
-40
A
+125
Figure 69. f
Maximum Operating Frequency vs VDD Supply Voltage
CLKIN
FUNCTIONALITY
GUARANTEED
IN THIS AREA
f
[MHz]
CLKIN
(UNLESS OTHERWISE
STATED IN THE
TABLES OF
PARAMETRIC DATA).
REFER TO
section 13.3.4 on page
134 FOR PLL OPER-
ATING RANGE
16
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
8
4
1
0
SUPPLY VOLTAGE [V]
5.5
3.0
2.0
2.7
3.3
3.5
4.0
4.5
5.0
Note: For further information on clock management block diagram for f
13 in section 7 on page 24.
description, refer to Figure
CLKIN
129/168
ST7L34, ST7L35, ST7L38, ST7L39
OPERATING CONDITIONS (cont’d)
The RC oscillator and PLL characteristics are temperature-dependent.
13.3.1.1 Operating Conditions (Tested for T = -40 to +125°C) @ V = 4.5 to 5.5V
A
DD
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
RCCR = FF (reset value),
630
T = 25°C, VDD = 5V
Internal RC oscillator
frequency
A
1)
f
kHz
RC
2)
RCCR = RCCR0 ,
995
1000
1005
T = 25°C, VDD = 5V
A
T = 25°C, VDD = 5V
-0.5
-1
+0.5
+1
A
Accuracy of Internal RC oscil-
lator with
RCCR = RCCR0
4)
ACC
I
T = 25°C, VDD = 4.5 to 5.5V
%
RC
A
2)3)
4)
T = -40 to +125°C, VDD = 4.5 to 5.5V
-3
+5
A
RC oscillator current con-
sumption
4)5)
T = 25°C, VDD = 5V
600
µA
DD(RC)
A
2)
t
f
t
t
RC oscillator setup time
x8 PLL input clock
T = 25°C, VDD = 5V
10
µs
su(RC)
PLL
A
1
2
MHz
8)
PLL lock time
LOCK
STAB
ms
8)
PLL stabilization time
4
7)
4)
ACC
x8 PLL accuracy
f
= 1 MHz @ T = -40 to +125°C
0.1
PLL
RC
A
%
6)
JIT
I
PLL jitter (∆f
/f )
CPU CPU
1
PLL
PLL current consumption
T = 25°C
550
µA
DD(PLL)
A
Notes:
1. If the RC oscillator clock is selected, to improve clock stability and frequency accuracy, it is recommended to place a
decoupling capacitor, typically 100nF, between the V and V pins as close as possible to the ST7 device.
DD
SS
2. See “INTERNAL RC OSCILLATOR ADJUSTMENT” on page 24.
3. Min value is obtained for hot temperature and max value is obtained for cold temperature.
4. Data based on characterization results, not tested in production.
5. Measurement made with RC calibrated at 1 MHz.
6. Guaranteed by design.
7. Averaged over a 4ms period. After the LOCKED bit is set, a period of t
is required to reach ACC
accuracy.
PLL
STAB
8. After the LOCKED bit is set ACC
is max. 10% until t
has elapsed. See Figure 12 on page 25.
PLL
STAB
130/168
ST7L34, ST7L35, ST7L38, ST7L39
OPERATING CONDITIONS (cont’d)
Figure 70. Typical Accuracy with RCCR = RCCR0 vs V = 4.5 to 5.5V and Temperature
DD
3.00%
2.50%
2.00%
1.50%
-45°C
0°C
25°C
90°C
110°C
130°C
1.00%
0.50%
0.00%
-0.50%
-1.00%
4.5
5
5.5
VDD (V)
Figure 71. f vs V and Temperature for Calibrated RCCR0
RC
DD
RCCR0 Typical behavior
1.1
1.05
1
-45°C'
0°C'
25°C'
90°C'
110°C'
130°C'
0.95
0.9
2.7
2.9
3.1
3.3
3.5
3.7
3.9
4.1
4.3
4.5
4.7
4.9
5.1
5.3
5.5
5.7
5.9
VDD supply (V)
131/168
ST7L34, ST7L35, ST7L38, ST7L39
OPERATING CONDITIONS (cont’d)
13.3.1.2 Operating Conditions (Tested for T = -40 to +125°C) @ V = 3.0 to 3.6V1)
A
DD
1)
Symbol
Parameter
Conditions
Min Typ Max Unit
RCCR = FF (reset value), T = 25°C, VDD = 3.3V
630
kHz
Internal RC oscillator
frequency
A
2)
f
RC
3)
RCCR = RCCR1 , T = 25°C, VDD = 3.3V
995 1000 1005
A
Accuracy of Internal RC T = 25°C
-1
+1
A
ACC
I
oscillator when calibrated
%
RC
T = -40 to +125°C
-3
+3
3)4)
A
with RCCR = RCCR1
RC oscillator current
consumption
5)
T = 25°C, VDD = 3.3V
500
µA
µs
DD(RC)
su(RC)
A
3)
t
RC oscillator setup time
T = 25°C, VDD = 3.3V
10
A
Notes:
1. Data based on characterization results, not tested in production
2. If the RC oscillator clock is selected, to improve clock stability and frequency accuracy, it is recommended to place a
decoupling capacitor, typically 100nF, between the V and V pins as close as possible to the ST7 device.
DD
SS
3. See “INTERNAL RC OSCILLATOR ADJUSTMENT” on page 24.
4. Min value is obtained for hot temperature and max value is obtained for cold temperature.
5. Measurement made with RC calibrated at 1 MHz.
Figure 72. Typical Accuracy with RCCR = RCCR1 vs V = 3 to 3.6V and Temperature
DD
1.50%
1.00%
-45°C
0°C
0.50%
0.00%
-0.50%
-1.00%
25°C
90°C
110°C
130°C
3
3.3
3.6
VDD (V)
132/168
ST7L34, ST7L35, ST7L38, ST7L39
OPERATING CONDITIONS (cont’d)
Figure 73. f vs V and Temperature for Calibrated RCCR1
RC
DD
RCCR1 Typical behavior
1.1
1.05
-45°C'
0°C'
25°C'
90°C'
110°C'
130°C'
1
0.95
0.9
2.7
2.9
3.1
3.3
3.5
3.7
3.9
4.1
4.3
4.5
4.7
4.9
5.1
5.3
5.5
5.7
5.9
VDD supply (V)
Figure 74. PLLx8 Output vs CLKIN Frequency
11.00
9.00
7.00
5.00
3.00
1.00
5.5
5
4.5
4
0.85
0.9
1
1.5
2
2.5
External Input Clock Frequency (MHz)
Note: f
= f
/2*PLL8
OSC
CLKIN
133/168
ST7L34, ST7L35, ST7L38, ST7L39
OPERATING CONDITIONS (cont’d)
13.3.2 Operating Conditions with Low Voltage Detector (LVD)
T = -40 to +125°C, unless otherwise specified
A
1)
Symbol
Parameter
Conditions
High Threshold
Min
Typ
Max
Unit
Reset release threshold
2)
V
3.60
4.15
4.50
IT +
(LVD)
(LVD)
(V rise)
DD
V
Reset generation threshold
2)
V
V
High Threshold
- V
3.40
3.95
200
4.40
IT -
hys
(V fall)
DD
LVD voltage threshold hysteresis
V
mV
µs/V
ns
IT +
IT -
(LVD)
(LVD)
3)5)
2)
2)
Vt
V
rise time rate
DD
20
100000
POR
4)
t
I
Filtered glitch delay on V
Not detected by the LVD
150
g(VDD)
DD
)
LVD/AVD current consumption
220
µA
DD(LVD
Notes:
1. LVD functionality guaranteed only within the V operating range specified in section 13.3.1 on page 129
DD
2. Not tested in production
3. Not tested in production. The V rise time rate condition is needed to insure a correct device power-on and LVD reset.
DD
When the V slope is outside these values, the LVD may not ensure a proper reset of the MCU.
DD
4. Based on design simulation
5. Use of LVD with capacitive power supply: With this type of power supply, if power cuts occur in the application, it is
recommended to pull V
page 146 and note 4.
down to 0V to ensure optimum restart conditions. Refer to circuit example in Figure 96 on
DD
13.3.3 Auxiliary Voltage Detector (AVD) Thresholds
T = -40 to +125°C, unless otherwise specified
A
1)
Symbol
Parameter
Conditions
High Threshold
Min
Typ
Max
Unit
1 = >0 AVDF flag toggle threshold
2)
V
3.85
4.45
4.90
IT +
(AVD)
(AVD)
(V rise)
DD
V
0 = >1 AVDF flag toggle threshold
2)
V
V
High Threshold
3.80
4.40
150
4.85
IT -
hys
(V fall)
DD
AVD voltage threshold hysteresis
V
V
- V
mV
V
IT +
DD
IT -
(AVD)
(AVD)
fall
Voltage drop between AVD flag set
and LVD reset activation
∆V
0.45
IT-
Notes:
1. LVD functionality guaranteed only within the V operating range specified in section 13.3.1 on page 129
DD
2. Not tested in production
13.3.4 Internal RC Oscillator and PLL
The ST7 internal clock are supplied by an internal RC oscillator and PLL (selectable by option byte).
Symbol
Parameter
Conditions
Min
Typ
Max Unit
V
Internal RC Oscillator operating voltage
Refer to operating range
3.0
5.5
DD(RC)
of V with T section
13.3.1 on page 129
V
DD
A,
V
x8 PLL operating voltage
3.6
5.5
DD(x8PLL)
134/168
ST7L34, ST7L35, ST7L38, ST7L39
ELECTRICAL CHARACTERISTICS (cont’d)
13.4 SUPPLY CURRENT CHARACTERISTICS
The following current consumption specified for
the ST7 functional operating modes over tempera-
ture range does not take into account the clock
source current consumption. To get the total de-
vice consumption, the two current values must be
added (except for HALT mode for which the clock
is stopped).
13.4.1 Supply Current
T = -40 to +125°C, unless otherwise specified
A
Symbol
Parameter
Conditions
Typ
6.0
2.4
0.7
0.6
Max
9.0
4.0
1.1
1.0
Unit
1)
2)
Supply current in RUN mode
Supply current in WAIT mode
Supply current in SLOW mode
Supply current in SLOW WAIT mode
f
f
f
f
= 8 MHz
= 8 MHz
CPU
CPU
CPU
CPU
mA
3)
= 250 kHz
4)
= 250 kHz
V
= 5.5V
I
DD
DD
10
50
-40°C ≤ T ≤ +85°C
5)
A
<1
Supply current in HALT mode
-40°C ≤ T ≤ +125°C
A
µA
-40°C ≤ T ≤ +85°C
50
300
6)7)8)
A
20
Supply current in AWUFH mode
-40°C ≤ T ≤ +125°C
A
0.7
Supply current in ACTIVE HALT mode
-40°C ≤ T ≤ +125°C
1
mA
A
Notes:
1. CPU running with memory access, all I/O pins in input mode with a static value at V or V (no load), all peripherals
DD
SS
in reset state; clock input (CLKIN) driven by external square wave, LVD disabled.
2. All I/O pins in input mode with a static value at V or V (no load), all peripherals in reset state; clock input (CLKIN)
DD
SS
driven by external square wave, LVD disabled.
3. SLOW mode selected with f
SS
based on f
divided by 32. All I/O pins in input mode with a static value at V or
OSC DD
CPU
V
(no load), all peripherals in reset state; clock input (CLKIN) driven by external square wave, LVD disabled.
4. SLOW-WAIT mode selected with f
based on f
divided by 32. All I/O pins in input mode with a static value at
CPU
OSC
V
or V (no load), all peripherals in reset state; clock input (CLKIN) driven by external square wave, LVD disabled.
DD
SS
5. All I/O pins in output mode with a static value at V (no load), LVD disabled. Data based on characterization results,
SS
tested in production at V max and f
max.
DD
CPU
6. All I/O pins in input mode with a static value at V or V (no load). Data tested in production at V max. and f
CPU
DD
SS
DD
max.
7. This consumption refers to the Halt period only and not the associated run period which is software dependent.
8. If low consumption is required, AWUFH mode is recommended.
Figure 75. Typical I in RUN vs f
Figure 76. Typical I in SLOW vs f
DD CPU
DD
CPU
8MHz
7.0
8MHz
4MHz
1MHz
1000.00
800.00
600.00
400.00
200.00
0.00
4MHz
6.0
5.0
4.0
3.0
2.0
1.0
0.0
1MHz
2.4
2.7
3.3
4
5
6
2.4
2.7
3.3
Vdd (V)
4
5
6
Vdd (V)
135/168
ST7L34, ST7L35, ST7L38, ST7L39
SUPPLY CURRENT CHARACTERISTICS (cont’d)
Figure 79. Typical I vs Temperature
DD
at V = 5V and f
= 16 MHz
Figure 77. Typical I in WAIT vs f
DD
CLKIN
DD
CPU
6.00
5.00
4.00
3.00
2.00
1.00
8MHz
2.5
RUN
4MHz
WAIT
2.0
SLOW
1MHz
1.5
SLOW WAIT
1.0
0.5
0.0
0.00
-45
2.4
2.7
3.3
4
5
6
25
90
130
Vdd (V)
Temperature (°C)
Figure 80. Typical I vs Temperature and V
DD
DD
Figure 78. Typical I in SLOW-WAIT vs f
at f
= 16 MHz
DD
CPU
CLKIN
6.00
5.00
4.00
3.00
2.00
1.00
0.00
8MHz
800.00
700.00
600.00
500.00
400.00
300.00
200.00
100.00
0.00
4MHz
1MHz
5
3.3
2.7
2.4
2.7
3.3
Vdd (V)
4
5
6
-45
25
90
130
Temperature (°C)
13.4.2 On-chip Peripherals
Symbol
Parameter
Conditions
Typ
Unit
f
f
f
f
= 4 MHz
= 8 MHz
= 4 MHz
= 8 MHz
V
V
V
V
V
V
V
= 3.0V
= 5.0V
= 3.0V
= 5.0V
= 3.0V
= 5.0V
= 5.0V
150
1000
50
CPU
CPU
CPU
CPU
DD
DD
DD
DD
DD
DD
DD
1)
I
I
12-bit Autoreload Timer supply current
DD(AT)
DD(SPI)
2)
SPI supply current
200
250
1100
650
µA
3)
I
I
f
= 4 MHz
= 8 MHz
ADC supply current when converting
DD(ADC)
ADC
CPU
4)
f
LINSCI supply current when transmitting
DD(LINSCI)
Notes:
1. Data based on a differential I measurement between reset configuration (timer stopped) and a timer running in PWM
DD
mode at f
= 8 MHz.
CPU
2. Data based on a differential I measurement between reset configuration and a permanent SPI master communica-
DD
tion (data sent equal to 55h).
3. Data based on a differential I measurement between reset configuration and continuous A/D conversions.
DD
4. Data based on a differential I measurement between LINSCI running at maximum speed configuration (500 Kbaud,
DD
continuous transmission of AA +RE enabled and LINSCI off. This measurement includes the pad toggling consumption.
136/168
ST7L34, ST7L35, ST7L38, ST7L39
ELECTRICAL CHARACTERISTICS (cont’d)
13.5 CLOCK AND TIMING CHARACTERISTICS
Subject to general operating conditions for V , f
and T .
DD OSC
A
13.5.1 General Timings
1)
3)
2)
Symbol
Parameter
Conditions
Min
2
Typ
3
Max
12
Unit
tCPU
ns
t
Instruction cycle time
c(INST)
250
10
375
1500
22
f
= 8 MHz
CPU
tCPU
µs
Interrupt reaction time
t
v(IT)
t
= ∆t
+ 10
1.25
2.75
v(IT)
c(INST)
Notes:
1. Guaranteed by Design. Not tested in production.
2. Data based on typical application software.
3. Time measured between interrupt event and interrupt vector fetch. Dt
ish the current instruction execution.
is the number of t
cycles needed to fin-
c(INST)
CPU
13.5.2 Crystal and Ceramic Resonator Oscillators
The ST7 internal clock can be supplied with four
different Crystal/Ceramic resonator oscillators. All
the information given in this paragraph are based
on characterization results with specified typical
external components. In the application, the reso-
nator and the load capacitors have to be placed as
close as possible to the oscillator pins in order to
minimize output distortion and start-up stabiliza-
tion time. Refer to the crystal/ceramic resonator
manufacturer for more details (frequency, pack-
age, accuracy...).
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
1)
f
Crystal oscillator frequency
2
16
MHz
CrOSC
Recommended load capacitance ver-
sus equivalent serial resistance of the
C
C
L1
L2
See table below
pF
crystal or ceramic resonator (R )
S
2)
Typical Ceramic Resonators
f
CL1
[pF]
CL2
[pF]
Supply Voltage
Range (V)
CrOSC
Supplier
Murata
3)
(MHz)
Reference
Oscillator Modes
LP or MP
MP or MS
MS or HS
HS
2
4
CSTCC2M00G56-R0
CSTCR4M00G55-R0
CSTCE8M00G55-R0
CSTCE16M0V53-R0
(47)
(39)
(33)
(15)
(47)
(39)
(33)
(15)
3.0V to 5.5V
8
16
Notes:
1. When PLL is used, please refer to the PLL characteristics chapter and to “SUPPLY, RESET AND CLOCK MANAGE-
MENT” on page 24 (f min. is 8 MHz with PLL).
CrOSC
2. Resonator characteristics given by the ceramic resonator manufacturer. For more information on these resonators,
please consult www.murata.com
3. SMD = [-R0: Plastic tape package (∅ = 180mm), -B0: Bulk]
137/168
ST7L34, ST7L35, ST7L38, ST7L39
ELECTRICAL CHARACTERISTICS (cont’d)
13.6 MEMORY CHARACTERISTICS
13.6.1 RAM and Hardware Registers
T = -40 to +125°C, unless otherwise specified
A
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
1)
V
Data retention mode
HALT mode (or RESET)
1.6
V
RM
13.6.2 Flash Program Memory
T = -40 to +85°C, unless otherwise specified
A
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Refer to operating range of
Operating voltage for
Flash write/erase
V
with T section 13.3.1
3.0
5.5
V
V
DD
A,
DD
on page 129
2)
T = −40 to +85°C
5
10
Programming time for 1~32 bytes
Programming time for 1.5 Kbytes
Data retention
ms
s
A
t
PROG
T = 25°C
0.24
0.48
A
4)
3)
t
T = 55°C
20
1K
years
RET
A
T
T
= 25°C
= 85°C
PROG
N
Write erase cycles
cycles
mA
RW
300
PROG
Read / Write / Erase modes
= 8 MHz, V = 5.5V
5)
2.6
f
CPU
DD
I
Supply current
DD
No Read/No Write Mode
Power down mode / HALT
100
0.1
µA
0
13.6.3 EEPROM Data Memory
T = -40 to +125°C, unless otherwise specified
A
Symbol
Parameter
Conditions
Min
Typ
Max
5.5
10
Unit
V
Refer to operating range of
Operating voltage for
EEPROM write/erase
V
with T section 13.3.1
V
3.0
DD
A,
DD
on page 129
T = −40 to +125°C
5
t
Programming time for 1~32 bytes
Data retention with 1k cycling
ms
A
PROG
20
10
1
(T
= −40 to +125°C
PROG
Data retention with 10k cycling
(T = −40 to +125°C)
4)
3)
t
T = 55°C
years
RET
A
PROG
Data retention with 100k cycling
(T = −40 to +125°C)
PROG
Notes:
1. Minimum V supply voltage without losing data stored in RAM (in HALT mode or under RESET) or in hardware reg-
DD
isters (only in HALT mode). Guaranteed by construction, not tested in production.
2. Up to 32 bytes can be programmed at a time.
3. The data retention time increases when the T decreases.
A
4. Data based on reliability test results and monitored in production.
5. Guaranteed by Design. Not tested in production.
138/168
ST7L34, ST7L35, ST7L38, ST7L39
ELECTRICAL CHARACTERISTICS (cont’d)
13.7 EMC CHARACTERISTICS
Susceptibility tests are performed on a sample ba-
sis during product characterization.
Therefore it is recommended that the user applies
EMC software optimization and prequalification
tests in relation with the EMC level requested for
his application.
13.7.1 Functional EMS (Electro Magnetic
Susceptibility)
Software recommendations:
Based on a simple running application on the
product (toggling 2 LEDs through I/O ports), the
product is stressed by two electro magnetic events
until a failure occurs (indicated by the LEDs). See
Table 25.
■ ESD: Electro-Static Discharge (positive and
negative) is applied on all pins of the device until
a functional disturbance occurs. This test
conforms with the IEC 1000-4-2 standard.
The software flowchart must include the manage-
ment of runaway conditions such as:
– Corrupted program counter
– Unexpected reset
– Critical Data corruption (control registers...)
Prequalification trials:
Most of the common failures (unexpected reset
and program counter corruption) are reproduced
by manually forcing a low state on the RESET pin
or the Oscillator pins for 1 second.
■ FTB: A Burst of Fast Transient voltage (positive
and negative) is applied to V and V through
DD
SS
a 100pF capacitor, until a functional disturbance
occurs. This test conforms with the IEC 1000-4-
4 standard.
To complete these trials, ESD stress is applied di-
rectly on the device, over the range of specification
values. When unexpected behavior is detected,
the software is hardened to prevent unrecoverable
errors occurring (see application note AN1015).
A device reset allows normal operations to be re-
sumed. The test results are given in the table be-
low based on the EMS levels and classes defined
in application note AN1709.
13.7.2 Electro Magnetic Interference (EMI)
13.7.1.1 Designing hardened software
to avoid noise problems
Based on a simple application running on the
product (toggling two LEDs through the I/O ports),
the product is monitored in terms of emission. This
emission test is in line with the norm SAE J 1752/
3 which specifies the board and the loading of
each pin. See Table 26.
EMC characterization and optimization are per-
formed at component level with a typical applica-
tion environment and simplified MCU software. It
should be noted that good EMC performance is
highly dependent on the user application and the
software in particular.
Table 25. EMS Characteristics
Level/
Symbol
Parameter
Conditions
Class
Voltage limits to be applied on any I/O pin to induce a functional
disturbance
V
= 5V, T = 25°C, f
OSC
= 8 MHz
DD
A
V
FESD
conforms to IEC 1000-4-2
V = 5V, T = 25°C, f
DD
conforms to IEC 1000-4-4
3B
Fast transient voltage burst limits to be applied through 100pF
= 8 MHz
A
OSC
V
FFTB
on V and V pins to induce a functional disturbance
DD
DD
Table 26. EMI Characteristics
Symbol Parameter
Max vs. [f
/f
]
Unit
Monitored
Frequency Band
OSC CPU
Conditions
8/4 MHz 16/8 MHz
0.1 MHz to 30 MHz
30 MHz to 130 MHz
130 MHz to 1 GHz
SAE EMI Level
15
13
9
15
19
13
3
dBµV
-
V
= 5V, T = 25°C, SO20 package,
A
1)
DD
Peak level
S
EMI
conforming to SAE J 1752/3
2.5
Note:
1. Data based on characterization results, not tested in production.
139/168
ST7L34, ST7L35, ST7L38, ST7L39
EMC CHARACTERISTICS (cont’d)
13.7.3 Absolute Maximum Ratings (Electrical
Sensitivity)
13.7.3.1 Electro-Static Discharge (ESD)
Electro-Static Discharges (a positive then a nega-
tive pulse separated by 1 second) are applied to
the pins of each sample according to each pin
combination. The sample size depends on the
number of supply pins in the device (3 parts*(n+1)
supply pin). Two models can be simulated: Human
Body Model and Machine Model. This test con-
forms to the JESD22-A114A/A115A standard.
Based on three different tests (ESD, LU and DLU)
using specific measurement methods, the product
is stressed in order to determine its performance in
terms of electrical sensitivity. For more details, re-
fer to the application note AN1181.
Absolute Maximum Ratings
1)
Symbol
Ratings
Conditions
Maximum value
Unit
Electro-static discharge voltage
(Human Body Model)
V
6000
ESD(HBM)
Electro-static discharge voltage
(Machine Model)
T = 25°C
V
600
V
A
ESD(MM)
Electro-static discharge voltage
(Charge Device Model)
V
1000
ESD(CDM)
Notes:
1. Data based on characterization results, not tested in production.
13.7.3.2 Static and Dynamic Latch-Up
■ LU: Three complementary static tests are
required on 10 parts to assess the latch-up
performance. A supply overvoltage (applied to
each power supply pin) and a current injection
(applied to each input, output and configurable I/
O pin) are performed on each sample. This test
conforms to the EIA/JESD 78 IC latch-up
standard. For more details, refer to the
application note AN1181.
■ DLU: Electro-Static Discharges (one positive
then one negative test) are applied to each pin
of three samples when the micro is running to
assess the latch-up performance in dynamic
mode. Power supplies are set to the typical
values, the oscillator is connected as near as
possible to the pins of the micro and the
component is put in reset mode. This test
conforms to the IEC1000-4-2 and SAEJ1752/3
standards. For more details, refer to the
application note AN1181.
Electrical Sensitivities
1)
Symbol
LU
Parameter
Static latch-up class
Dynamic latch-up class
Conditions
Class
T = 25°C
A
T = 125°C
A
A
V
= 5.5V, f
= 4 MHz, T = 25°C
OSC A
DLU
DD
Notes:
1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC spec-
ifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the
JEDEC criteria (international standard).
140/168
ST7L34, ST7L35, ST7L38, ST7L39
ELECTRICAL CHARACTERISTICS (cont’d)
13.8 I/O PORT PIN CHARACTERISTICS
13.8.1 General Characteristics
Subject to general operating conditions for V , f
and T (-40 to +125°C), unless otherwise specified.
A
DD OSC
Symbol
Parameter
Input low level voltage
Input high level voltage
Schmitt trigger voltage
Conditions
Min
Typ
Max
Unit
V
VSS - 0.3
0.7 x VDD
0.3 x VDD
VDD + 0.3
IL
V
V
IH
V
400
400
mV
µA
1)
hys
hysteresis
I
Input leakage current
V
SS ≤ VIN ≤ V
1
L
DD
Static current consumption induced by
I
Floating input mode
IN = V DD = 5V
2)
S
each floating input pin
3)
R
Weak pull-up equivalent resistor
V
V
SS,
50
1
100
5
170
kΩ
PU
C
I/O pin capacitance
pF
IO
1)
t
Output high to low level fall time
C = 50pF
Between 10% and 90%
f(IO)out
r(IO)out
L
25
ns
1)
t
Output low to high level rise time
4)
t
External interrupt pulse time
t
CPU
w(IT)in
Notes:
1. Data based on characterization results, not tested in production.
2. Configuration not recommended, all unused pins must be kept at a fixed voltage: Using the output mode of the I/O for
example or an external pull-up or pull-down resistor (see Figure 81). Static peak current value taken at a fixed V value,
IN
based on design simulation and technology characteristics, not tested in production. This value depends on V and tem-
DD
perature values.
3. The R pull-up equivalent resistor is based on a resistive transistor (corresponding I current characteristics de-
PU
PU
scribed in Figure 81).
4. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external
interrupt source.
Figure 81. Two Typical Applications with Unused I/O Pin
V
ST7
DD
UNUSED I/O PORT
10kΩ
10kΩ
UNUSED I/O PORT
ST7
Caution: During normal operation the ICCCLK pin must be pulled up, internally or externally (external pull-up of 10k mandatory in
oisy environment). This is to avoid entering ICC mode unexpectedly during a reset.
n
Note: I/O can be left unconnected if it is configured as output (0 or 1) by the software. This has the advantage of greater EMC
robustness and lower cost.
l
141/168
ST7L34, ST7L35, ST7L38, ST7L39
I/O PORT PIN CHARACTERISTICS (cont’d)
Figure 82. Typical I vs V with V = V
SS
PU
DD
IN
90
80
70
60
50
40
30
20
10
0
Ta=140°C
Ta=95°C
Ta=25°C
Ta=-45°C
2
2.5
3
3.5
4
4.5
5
5.5
6
Vdd(V)
13.8.2 Output Driving Current
Subject to general operating conditions for V , f
and T (-40 to +125°C), unless otherwise specified.
DD OSC
A
Table 27. Output Driving Current Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Output low level voltage for a standard
I/O pin when 8 pins are sunk at same
time (see Figure 85)
I
I
I
I
I
I
= +5mA
= +2mA
= +20mA
= +8mA
= -5mA
= -2mA
0.65
1.0
IO
IO
IO
IO
IO
IO
0.25
1.05
0.4
0.4
1.4
1)
V
OL
Output low level voltage for a high sink
I/O pin when 4 pins are sunk at same
time (see Figure 88)
V
= 5V
V
DD
0.75
Output high level voltage for an I/O pin
when 4 pins are sourced at same time
(see Figure 91)
V
V
-1.5 4.30
-1.0 4.70
DD
DD
2)
V
OH
Notes:
1. The I current sunk must always respect the absolute maximum rating specified in Section 13.2.2 and the sum of I
IO
IO
(I/O ports and control pins) must not exceed I
.
VSS
2. The I current sourced must always respect the absolute maximum rating specified in Section 13.2.2 and the sum of
IO
I
(I/O ports and control pins) must not exceed I
.
IO
VDD
3. Not tested in production, based on characterization results.
142/168
ST7L34, ST7L35, ST7L38, ST7L39
Figure 83. Typical V at V = 3V
Figure 87. Typical V at V = 4V (high-sink)
OL DD
OL
DD
-45°C
25°C
-45°C
25°C
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
90°C
90°C
110°C
130°C
110°C
130°C
0.01
1
2
3
4
5
6
5
8
10
15
lio (mA)
lio (mA)
Figure 84. Typical V at V = 4V
Figure 88. Typical V at V = 5V (high-sink)
OL DD
OL
DD
-45°C
25°C
-45°C
25°C
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
90°C
90°C
110°C
130°C
110°C
130°C
0.01
1
2
3
4
5
6
5
8
10
15
lio (mA)
lio (mA)
Figure 85. Typical V at V = 5V
Figure 89. Typical V -V at V = 3V
DD OH DD
OL
DD
-45°C
25°C
-45°C
25°C
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
90°C
90°C
110°C
130°C
110°C
130°C
-0.01
-1
-2
-3
-4
0.01
1
2
3
4
5
6
lio (mA)
lio (mA)
Figure 86. Typical V at V = 3V (high-sink)
Figure 90. Typical V -V at V = 4V
DD OH DD
OL
DD
-45°C
25°C
-45°C
25°C
1.2
1.0
0.8
0.6
0.4
0.2
0.0
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
90°C
90°C
110°C
130°C
110°C
130°C
5
8
10
15
-0.01
-1
-2
-3
-4
-5
-6
lio (mA)
lio (mA)
143/168
ST7L34, ST7L35, ST7L38, ST7L39
Figure 91. Typical V - V at V = 5V
Figure 92. Typical V vs V (Standard I/Os)
OL DD
DD
OH
DD
-45°C
25°C
-45°C
25°C
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0.5
0.4
0.4
0.3
0.3
0.2
0.2
0.1
0.1
0.0
90°C
90°C
110°C
130°C
110°C
130°C
-0.01
-1
-2
-3
lio (mA)
-4
-5
-6
3
4
5
VDD (V)
Figure 93. Typical V vs V (High-sink I/Os)
OL
DD
-45°C
25°C
-45°C
25°C
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0.4
0.3
0.3
0.2
0.2
0.1
0.1
0.0
90°C
90°C
110°C
130°C
110°C
130°C
3
4
5
3
4
5
VDD (V)
VDD (V)
Figure 94. Typical V - V vs V
DD
DD
OH
-45°C
25°C
-45°C
25°C
0.7
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
90°C
90°C
0.6
0.5
0.4
0.3
0.2
0.1
0.0
110°C
130°C
110°C
130°C
3
4
5
3
4
5
VDD (V)
VDD (V)
144/168
ST7L34, ST7L35, ST7L38, ST7L39
ELECTRICAL CHARACTERISTICS (cont’d)
13.9 CONTROL PIN CHARACTERISTICS
13.9.1 Asynchronous RESET Pin
T = -40 to +125°C, unless otherwise specified
A
Table 28. Asynchronous RESET Pin Characteristics
Symbol
Parameter
Input low level voltage
Input high level voltage
Schmitt trigger voltage
Conditions
Min
Typ
Max
Unit
V
VSS - 0.3
0.7 x VDD
0.3 x VDD
VDD + 0.3
IL
V
IH
V
1
1)
hys
hysteresis
V
5)
I
IO = +5mA T ≤ +85°C
1.0
A
0.5
5)
T ≤ +125°C
1.2
A
2)
V
R
Output low level voltage
VDD = 5V
OL
5)
I
IO = +2mA T ≤ +85°C
0.7
A
0.45
5)
T ≤ +125°C
0.9
A
1)3)
Pull-up equivalent resistor
V
DD = 5V
10
20
39
30
70
kΩ
µs
ns
ON
t
Generated reset pulse duration
Internal reset sources
w(RSTL)out
4)
t
t
External reset pulse hold time
h(RSTL)in
g(RSTL)in
Filtered glitch duration
200
Notes:
1. Data based on characterization results, not tested in production.
2. The I current sunk must always respect the absolute maximum rating specified in section 13.2.2 on page 128 and
IO
the sum of I (I/O ports and control pins) must not exceed I
.
IO
VSS
3. The R
ILmax
pull-up equivalent resistor is based on a resistive transistor. Specified for voltages on RESET pin between
DD
ON
V
and V
4. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on
RESET pin with a duration below t can be ignored.
h(RSTL)in
5. Guaranteed by design. Not tested in production.
1)2)3)4)
Figure 95. RESET Pin Protection When LVD Is Enabled
V
ST7
DD
Optional
(note 3)
Required
R
ON
INTERNAL
RESET
EXTERNAL
RESET
Filter
0.01µF
1MΩ
WATCHDOG
ILLEGALOPCODE5)
LVD RESET
PULSE
GENERATOR
145/168
ST7L34, ST7L35, ST7L38, ST7L39
CONTROL PIN CHARACTERISTICS (cont’d)
1)
Figure 96. RESET Pin Protection When LVD Is Disabled
V
ST7
DD
R
ON
INTERNAL
RESET
USER
EXTERNAL
RESET
Filter
CIRCUIT
0.01µF
WATCHDOG
ILLEGALOPCODE5)
PULSE
GENERATOR
Required
Notes:
1. The reset network protects the device against parasitic resets. The output of the external reset circuit must have an
open-drain output to drive the ST7 reset pad. Otherwise the device can be damaged when the ST7 generates an in-
ternal reset (LVD or watchdog).
Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin can go below
the V max. level specified in section 13.9.1 on page 145. Otherwise the reset will not be taken into account internally.
IL
Because the reset circuit is designed to allow the internal RESET to be output in the RESET pin, the user must ensure
that the current sunk on the RESET pin is less than the absolute maximum value specified for I
13.2.2 on page 128.
in section
INJ(RESET)
2. When the LVD is enabled, it is recommended not to connect a pull-up resistor or capacitor. A 10nF pull-down capacitor
is required to filter noise on the reset line.
3. In case a capacitive power supply is used, it is recommended to connect a 1MΩ pull-down resistor to the RESET pin
to discharge any residual voltage induced by the capacitive effect of the power supply (this will add 5µA to the power
consumption of the MCU).
4. Tips when using the LVD:
- Step 1: Check that all recommendations related to ICCCLK and reset circuit have been applied (see caution in Table 2
on page 8 and notes above)
- Step 2: Check that the power supply is properly decoupled (100nF + 10µF close to the MCU). Refer to AN1709 and
AN2017. If this cannot be done, it is recommended to put a 100nF + 1MΩ pull-down on the RESET pin.
- Step 3: The capacitors connected on the RESET pin and also the power supply are key to avoid any start-up marginality.
In most cases, steps 1 and 2 above are sufficient for a robust solution. Otherwise: Replace 10nF pull-down on the
RESET pin with a 5µF to 20µF capacitor.
5. Please refer to “Illegal Opcode Reset” on page 124 for more details on illegal opcode reset conditions
146/168
ST7L34, ST7L35, ST7L38, ST7L39
ELECTRICAL CHARACTERISTICS (cont’d)
13.10
CHARACTERISTICS
COMMUNICATION
INTERFACE
Refer to I/O port characteristics for more details on
the input/output alternate function characteristics
(SS, SCK, MOSI, MISO).
13.10.1 SPI - Serial Peripheral Interface
Subject to general operating conditions for V
,
DD
f
and T , unless otherwise specified.
OSC
A
Symbol
Parameter
Conditions
Master, fCPU = 8 MHz
Slave, fCPU = 8 MHz
Min
Max
Unit
f
/ 128 = 0.0625
0
f
f
/ 4 = 2
CPU
CPU
CPU
f
SCK = 1 / t
SPI clock frequency
MHz
c(SCK)
/ 2 = 4
t
t
r(SCK)
f(SCK)
SPI clock rise and fall time
see I/O port pin description
1)
4)
t
t
SS setup time
(4 x T
) + 50
CPU
su(SS)
Slave
1)
SS hold time
120
h(SS)
1)
t
t
100
90
Master
Slave
w(SCKH)
SCK high and low time
1)
w(SCKL)
1)
su(MI)
1)
t
t
100
100
Master
Slave
Data input setup time
Data input hold time
su(SI)
ns
1)
h(MI)
1)
t
t
100
100
Master
Slave
h(SI)
1)
t
t
t
t
t
t
Data output access time
Data output disable time
Data output valid time
Data output hold time
Data output valid time
Data output hold time
0
120
240
120
Slave
Slave
a(SO)
1)
dis(SO)
1)
v(SO)
Slave (after enable edge)
Master (after enable edge)
1)
0
0
h(SO)
1)
120
v(MO)
t
CPU
1)
h(MO)
Figure 97. SPI Slave Timing Diagram with CPHA = 03)
SS
INPUT
t
t
su(SS)
c(SCK)
t
h(SS)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
t
t
w(SCKH)
w(SCKL)
t
t
t
t
dis(SO)
a(SO)
v(SO)
h(SO)
t
t
r(SCK)
f(SCK)
See
note 2
MISO
OUTPUT
INPUT
MSB OUT
See note 2
BIT6 OUT
LSB OUT
t
t
h(SI)
su(SI)
LSB IN
MSB IN
BIT1 IN
MOSI
Notes:
1. Data based on design simulation and/or characterization results, not tested in production.
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has
its alternate function capability released. In this case, the pin status depends on the I/O port configuration.
3. Measurement points are done at CMOS levels: 0.3 x V and 0.7 x V
.
DD
DD
4. Depends on f
. For example, if f
= 8 MHz, then T
= 1 / f
= 125ns and t
= 550ns.
su(SS)
CPU
CPU
CPU
CPU
147/168
ST7L34, ST7L35, ST7L38, ST7L39
COMMUNICATION INTERFACE CHARACTERISTICS (cont’d)
Figure 98. SPI Slave Timing Diagram with CPHA = 11)
SS
INPUT
t
t
su(SS)
c(SCK)
t
h(SS)
CPHA=1
CPOL=0
CPHA=1
CPOL=1
t
t
w(SCKH)
w(SCKL)
t
t
dis(SO)
a(SO)
t
t
h(SO)
v(SO)
t
t
r(SCK)
f(SCK)
See
note 2
See
note 2
MISO
OUTPUT
INPUT
MSB OUT
BIT6 OUT
HZ
LSB OUT
t
t
h(SI)
su(SI)
MSB IN
LSB IN
BIT1 IN
MOSI
Figure 99. SPI Master Timing Diagram1)
SS
INPUT
t
c(SCK)
CPHA = 0
CPOL = 0
CPHA = 0
CPOL = 1
CPHA = 1
CPOL = 0
CPHA = 1
CPOL = 1
t
t
w(SCKH)
w(SCKL)
t
t
r(SCK)
f(SCK)
t
t
h(MI)
su(MI)
MISO
INPUT
MSB IN
BIT6 IN
LSB IN
t
t
v(MO)
h(MO)
LSB OUT
MSB OUT
See note 2
BIT6 OUT
See note 2
MOSI
OUTPUT
Notes:
1. Measurement points are done at CMOS levels: 0.3xV and 0.7xV
.
DD
DD
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has
its alternate function capability released. In this case, the pin status depends of the I/O port configuration.
148/168
ST7L34, ST7L35, ST7L38, ST7L39
ELECTRICAL CHARACTERISTICS (cont’d)
13.11 10-BIT ADC CHARACTERISTICS
Subject to general operating conditions for V , f
and T , unless otherwise specified.
DD OSC
A
Table 29. 10-bit ADC Characteristics
1)
2)
1)
Symbol
Parameter
ADC clock frequency
Conversion voltage range
External input resistor
Conditions
Min
0.5
Typ
Max
Unit
MHz
V
f
4
ADC
3)
V
R
V
V
AIN
AIN
SSA
DDA
4)
10
kΩ
C
Internal sample and hold capacitor
Stabilization time after ADC enable
Conversion time (Sample + Hold)
6
pF
ADC
STAB
5)
t
0
µs
3.5
fCPU = 8 MHz, fADC = 4 MHz
t
- Sample capacitor loading time
- Hold conversion time
4
10
ADC
1/f
ADC
Notes:
1. Data based on characterization results, not tested in production.
2. Unless otherwise specified, typical data is based on T = 25°C and V - V = 5V. They are given only as design
A
DD
SS
guidelines and are not tested.
3. When V and V pins are not available on the pinout, the ADC refers to V and V .
SS
DDA
SSA
DD
4. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance g(reater than10kΩ).
Data based on characterization results, not tested in production.
5. The stabilization time of the AD converter is masked by the first t
always valid.
. The first conversion after the enable is then
LOAD
Figure 100. Typical Application with ADC
V
DD
V
T
0.6V
R
AIN
AINx
10-bit A/D
Conversion
V
AIN
V
0.6V
T
I
C
ADC
L
1µA
ST7
149/168
ST7L34, ST7L35, ST7L38, ST7L39
10-BIT ADC CHARACTERISTICS (cont’d)
Table 30. ADC Accuracy with 3V ≤ V ≤ 3.6V
DD
3)
Symbol
|E |
Parameter
Total unadjusted error
Offset error
Conditions
Typ
1.9
0.3
0.3
1.8
1.7
Max
Unit
3.1
1.2
1
T
|E |
O
1)2)
|E |
Gain error
fCPU = 4 MHz, fADC = 2 MHz
LSB
G
|E |
Differential linearity error
Integral linearity error
3
D
|E |
2.8
L
Table 31. ADC Accuracy with 4.5V ≤ V ≤ 5.5V
DD
3)
Symbol
|E |
Parameter
Total unadjusted error
Offset error
Conditions
Typ
2.0
0.4
0.4
1.9
1.8
Max
3.4
1.7
1.5
3.1
2.9
Unit
T
|E |
O
1)2)
|E |
Gain error
f
CPU = 8 MHz, fADC = 4 MHz
LSB
G
|E |
Differential linearity error
Integral linearity error
D
|E |
L
Notes:
1. Data based on characterization results over the whole temperature range, monitored in production.
2. ADC accuracy vs negative injection current: Injecting negative current on any of the analog input pins may reduce the
accuracy of the conversion being performed on another analog input.
The effect of negative injection current on robust pins is specified in section 13.11 on page 149.
Any positive injection current within the limits specified for I
accuracy.
and ΣI
in Section 13.8 does not affect the ADC
INJ(PIN)
INJ(PIN)
3. Data based on characterization results, monitored in production to guarantee 99.73% within max value from -40°C
to +125°C ( 3σ distribution limits).
Figure 101. ADC Accuracy Characteristics
Digital Result ADCDR
E
G
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line
1023
1022
1021
V
– V
DD
SS
1LSB
= -------------------------------
IDEAL
1024
(2)
E = Total Unadjusted Error: maximum deviation
T
E
between the actual and the ideal transfer curves.
T
(3)
7
6
5
4
3
2
1
E =Offset Error: deviation between the first actu-
O
al transition and the first ideal one.
(1)
E
= Gain Error: deviation between the last ideal
G
transition and the last actual one.
E
E
O
L
E = Differential Linearity Error: maximum devia-
D
tion between actual steps and the ideal one.
E = Integral Linearity Error: maximum deviation
L
E
between any actual transition and the end point
correlation line.
D
1 LSB
IDEAL
V
(LSB
)
in
IDEAL
0
1
2
3
4
5
6
7
1021 1022 1023 1024
V
V
DD
SS
150/168
ST7L34, ST7L35, ST7L38, ST7L39
14 PACKAGE CHARACTERISTICS
14.1 PACKAGE MECHANICAL DATA
In order to meet environmental requirements, ST
offers these devices in ECOPACK® packages.
These packages have a lead-free second level in-
terconnect. The category of Second Level Inter-
connect is marked on the package and on the in-
ner box label, in compliance with JEDEC Standard
JESD97. The maximum ratings related to solder-
ing conditions are also marked on the inner box la-
bel.
ECOPACK is an ST trademark. ECOPACK speci-
fications are available at www.st.com.
Figure 102. 20-Pin Plastic Small Outline Package, 300-mil Width
mm
inches
D
h x 45×
Dim.
Min Typ Max Min Typ Max
L
A
2.35
2.65 0.093
0.30 0.004
0.51 0.013
0.32 0.009
13.00 0.496
7.60 0.291
0.104
0.012
0.020
0.013
0.512
0.299
A
c
A1
A1 0.10
a
B
C
D
E
e
0.33
0.23
e
B
12.60
7.40
1.27
0.050
H
h
α
L
10.00
0.25
0°
10.65 0.394
0.75 0.010
0.419
0.030
8°
E
H
8°
0°
0.40
1.27 0.016
0.050
Number of Pins
N
20
151/168
ST7L34, ST7L35, ST7L38, ST7L39
Figure 103. QFN 5x6: 20-Lead Very Thin Fine Pitch Quad Flat No-Lead Package
mm
1)
Dimension
Minimum
Typical
0.80 BSC
20
Maximum
e
3)
N
5.
5.
ND
NE
L
4
6
0.45
0.25
3.30
4.30
0.50
0.55
0.35
3.50
4.50
4.
b
0.30
D2
E2
D
3.40
4.40
5.00 BSC
6.00 BSC
0.85
E
A
0.80
0.00
0.90
0.05
A1
A3
K
0.02
0.02 REF
0.20 MIN
2)
θ
0
12
Notes:
1. All dimensions are in millimeters.
2. θ is in degrees.
3. N is the total number of terminals.
4. Dimension b applies to metallized terminals and is measured between 0.15 and 0.30mm from terminal TIP. If the terminal has
the optional radius on the other end of the terminal the dimension b should not be measured in that radius area.
5. ND and NE refer to the number of terminals on each D and E side respectively.
152/168
ST7L34, ST7L35, ST7L38, ST7L39
PACKAGE CHARACTERISTICS (cont’d)
14.2 THERMAL CHARACTERISTICS
Symbol
Parameter
Package
SO20
Value
70
Unit
Package thermal resistance (junction to ambient)
°C/W
R
thJA
Jmax
Dmax
QFN20
SO20
30
1)
Maximum junction temperature
150
°C
T
QFN20
SO20
< 350
< 800
2)
Maximum power dissipation
mW
P
QFN20
Notes:
1. The maximum chip-junction temperature is based on technology characteristics.
2. The maximum power dissipation is obtained from the formula P = (T -T ) / R
. The power dissipation of an appli-
D
J
A
thJA
cation is defined by the user with the formula: P = P
+ P
where P
is the chip internal power (I x V ) and
D
INT
PORT
INT
DD
DD
P
is the port power dissipation depending on the ports used in the application.
PORT
14.3 SOLDERING INFORMATION
In accordance with the RoHS European directive,
all STMicroelectronics packages have been con-
verted to lead-free technology, named ECO-
PACK™.
■ ECOPACK™ packages are qualified according
to the JEDEC STD-020C compliant soldering
profile.
Forward compatibility
ECOPACK™ SO and QFN packages are fully
compatible with a lead (Pb) containing soldering
process (see application note AN2034).
■ Detailed information on the STMicroelectronics
ECOPACK™ transition program is available on
www.st.com/stonline/leadfree/, with specific
technical application notes covering the main
technical aspects related to lead-free
conversion (AN2033, AN2034, AN2035,
AN2036).
Table 32. Soldering Compatibility (wave and reflow soldering process)
Package
SO
Plating material
Pb solder paste
Pb-free solder paste
NiPdAu (Nickel-Palladium-Gold)
Yes
Yes
QFN
153/168
ST7L34, ST7L35, ST7L38, ST7L39
15 DEVICE CONFIGURATION
Each device is available for production in user pro-
grammable versions (Flash) as well as in factory
coded versions (ROM). ST7L3x devices are ROM
versions.
ST7FL3 Flash devices are shipped to customers
with a default program memory content (FFh),
while ROM/FASTROM factory coded parts contain
the code supplied by the customer. This implies
that Flash devices have to be configured by the
customer using the Option Bytes while the ROM/
FASTROM devices are factory-configured.
ST7PL3x devices are Factory Advanced Service
Technique ROM (FASTROM) versions: They are
factory programmed Flash devices.
15.1 OPTION BYTES
The 2 option bytes allow the hardware configura-
tion of the microcontroller to be selected. Differ-
ences in configuration between Flash and ROM
devices for OPTION BYTE 0 are presented in the
following table and are defined in Section 15.1.1
Option Byte 0.
OPTION BYTE 0
OPTION BYTE 1
7
6
5
4
3
2
1
0
7
6
1
5
4
3
2
1
1
0
1
FMP FMP
R
Flash
ROM
W
Name
OSCRANGE 2:0
Res
Res OSC LVD 1:0
ROP ROP
_R
Reserved
_D
1)
1)
Default value
1
1
1
1
1
1
0
0
1
0
0
1
1
Notes:
1. Contact your STMicroelectronics support.
154/168
ST7L34, ST7L35, ST7L38, ST7L39
OPTION BYTES (cont’d)
15.1.1 Option Byte 0
For Flash devices
OPT 3:2 = SEC[1:0] Sector 0 size definition
These option bits indicate the size of sector 0 ac-
cording to the following table.
OPT7 = AWUCK Auto Wake Up Clock Selection
0: 32 kHz oscillator (VLP) selected as AWU clock
1: AWU RC oscillator selected as AWU clock.
Sector 0 Size
SEC1
SEC0
Note: If this bit is reset, internal RC oscillator must
be selected (Option OSC = 0).
0.5k
1k
0
0
1
1
0
1
0
1
2k
4k
OPT6:4 = OSCRANGE[2:0] Oscillator Range
When the internal RC oscillator is not selected
(Option OSC = 1), these option bits select the
range of the resonator oscillator current source or
the external clock source.
OPT1 = FMP_R Readout protection
Readout protection, when selected provides a pro-
tection against program memory content extrac-
tion and against write access to Flash memory.
Erasing the option bytes when the FMP_R option
is selected will cause the whole memory to be
erased first and the device can be reprogrammed.
Refer to the ST7 Flash Programming Reference
Manual and section 4.5 on page 15 for more de-
tails
OSCRANGE
2
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
LP
1~2 MHz
2~4 MHz
4~8 MHz
MP
MS
Typ.
frequency
range with
Resonator
0: Readout protection off
1: Readout protection on
HS 8~16 MHz
VLP 32.768 kHz
OPT 0 = FMP_W Flash write protection
This option indicates if the Flash program memory
is write protected.
External Clock on OSC1
Reserved
Warning: When this option is selected, the pro-
gram memory (and the option bit itself) can never
be erased or programmed again.
0: Write protection off
External Clock on PB4
Note: OSCRANGE[2:0] has no effect when
AWUCK option is set to 0. In this case, the VLP os-
cillator range is automatically selected as AWU
clock.
1: Write protection on
The option bytes have no address in the memory
map and are accessed only in programming mode
(for example using a standard ST7 programming
tool). The default content of the Flash is fixed to
FFh.
For ROM devices
OPT 3:2 = Reserved [1:1]
OPT1 = ROP_R Readout protection for ROM
This option is for read protection of ROM
0: Readout protection off
1: Readout protection on
OPT 0 = ROP_D Readout protection for Data
EEPROM
This option is for read protection of EEPROM
memory.
0: Readout protection off
1: Readout protection on
155/168
ST7L34, ST7L35, ST7L38, ST7L39
OPTION BYTES (cont’d)
15.1.2 Option Byte 1
1)
OPT 7 = Reserved
OPT 1 = WDGSW Hardware or Software Watch-
dog
0: Hardware (watchdog always enabled)
1: Software (watchdog to be enabled by software)
OPT 6 = PLLOFF PLL Disable
This option bit enables or disables the PLL.
0: PLL enabled
1: PLL disabled (bypassed)
OPT 0 = WDG HALT Watchdog Reset on Halt
0: No reset generation when entering HALT mode
1: Reset generation when entering HALT mode
1)
OPT 5 = Reserved
Notes:
2)
OPT 4 = OSC RC Oscillator Selection
1. Contact your STMicroelectronics support
The internal RC oscillator can be selected with this
option bit.
2. If the RC oscillator is selected, to then improve clock
stability and frequency accuracy it is recommended to
place a decoupling capacitor, typically 100nF, between
0: RC oscillator on
1: RC oscillator off
the V and V pins as close as possible to the ST7 de-
DD
SS
vice.
OPT 3:2 = LVD[1:0] Low Voltage Selection
These option bits enable the voltage detection
block (LVD and AVD) with a selected threshold to
the LVD and AVD.
Configuration
VD1 VD0
1
1
1
0
LVD Off
LVD On (Highest Voltage Threshold)
156/168
ST7L34, ST7L35, ST7L38, ST7L39
DEVICE CONFIGURATION (cont’d)
15.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE
Customer code is made up of the ROM/FAS-
TROM contents and the list of the selected options
(if any). The ROM/FASTROM contents are to be
sent on a diskette or by electronic means, with the
S19 hexadecimal file generated by the develop-
ment tool. All unused bytes must be set to FFh.
The selected options are communicated to
STMicroelectronics using the correctly completed
OPTION LIST appended on page 161.
Refer to application note AN1635 for information
on the counter listing returned by ST after code
has been transferred.
The STMicroelectronics Sales Organization will be
pleased to provide detailed information on con-
tractual points.
15.3 FLASH DEVICE ORDERING INFORMATION
Figure 104. Flash Device Types
DEVICE E2DATA PINOUT PROG MEM PACKAGE VERSION TR E
E = Leadfree (ECOPACK™ option)
Conditioning options:
TR = Tape and Reel (left blank if Tube)
A = -40 to +85°C
C = -40 to +125°C
M = Plastic Small Outline
U = Quad Flat No-lead
2 = 8 Kbytes
F = 20 pins
2
2
4 = No E data / No LIN
5 = No E data / LIN
2
2
8 = E data / No LIN
9 = E data / LIN
ST7FL3
157/168
ST7L34, ST7L35, ST7L38, ST7L39
DEVICE CONFIGURATION (cont’d)
Table 33. Flash User Programmable Device Types
Program
Data EEPROM
(bytes)
RAM
Temperature
Range
Part Number
Memory
(bytes)
LINSCI
Package
(bytes)
ST7FL34F2MA
ST7FL35F2MA
ST7FL38F2MA
ST7FL39F2MA
ST7FL34F2MC
ST7FL35F2MC
ST7FL38F2MC
ST7FL39F2MC
ST7FL34F2UA
ST7FL35F2UA
ST7FL38F2UA
ST7FL39F2UA
ST7FL34F2UC
ST7FL35F2UC
ST7FL38F2UC
ST7FL39F2UC
-
yes
-
-
256
-
-40 to +85°C
-40 to +125°C
-40 to +85°C
-40 to +125°C
yes
-
SO20
yes
-
256
-
yes
-
8K Flash
384
yes
-
256
-
yes
-
QFN20
yes
-
256
yes
158/168
ST7L34, ST7L35, ST7L38, ST7L39
DEVICE CONFIGURATION (cont’d)
Figure 105. FASTROM Commercial Product Code Structure
DEVICE E2DATA PINOUT PROG MEM PACKAGE VERSION XXX R E
/
E = Leadfree (ECOPACK™ option)
Conditioning options:
R = Tape and Reel (left blank if Tube)
Code name
(defined by STMicrolectronics)
Not present if Tape and Reel
A = -40 to +85°C
C = -40 to +125°C
M = Plastic Small Outline
U = Quad Flat No-lead
2 = 8 Kbytes
F = 20 pins
2
2
4 = No E data / No LIN
5 = No E data / LIN
2
2
8 = E data / No LIN
9 = E data / LIN
ST7PL3
Table 34. FASTROM Factory Coded Device Types
Program
Data EEPROM
(bytes)
RAM
Temperature
1)
Part Number
Memory
(bytes)
LINSCI
Package
(bytes)
Range
ST7PL34F2MA
ST7PL35F2MA
ST7PL38F2MA
ST7PL39F2MA
ST7PL34F2MC
ST7PL35F2MC
ST7PL38F2MC
ST7PL39F2MC
ST7PL34F2UA
ST7PL35F2UA
ST7PL38F2UA
ST7PL39F2UA
ST7PL34F2UC
ST7PL35F2UC
ST7PL38F2UC
ST7PL39F2UC
-
yes
-
-
256
-
-40 to +85°C
yes
-
SO20
yes
-
-40 to +125°C
-40 to +85°C
-40 to +125°C
256
-
yes
-
8K FASTROM
384
yes
-
256
-
yes
-
QFN20
yes
-
256
yes
1. Contact ST sales office for product availability
159/168
ST7L34, ST7L35, ST7L38, ST7L39
DEVICE CONFIGURATION (cont’d)
Figure 106. ROM Commercial Product Code Structure
DEVICE E2DATA PINOUT PROG MEM PACKAGE / XXX R E
E = Leadfree (ECOPACK™ option)
Conditioning options:
R = Tape and Reel (left blank if Tray)
Code name (defined by STMicroelectronics)
M = Plastic Small Outline
U = Quad Flat No-lead
2 = 8 Kbytes
F = 20 pins
2
2
4 = No E data / No LIN
5 = No E data / LIN
2
2
8 = E data / No LIN
9 = E data / LIN
ST7L3
Table 35. ROM Factory Coded Device Types
Program
DataEEPROM
(bytes)
RAM
(bytes)
Temperature
1)
Part Number
Memory
(bytes)
LINSCI
Package
Range
ST7L34F2UA
ST7L35F2UA
ST7L38F2UA
ST7L39F2UA
ST7L34F2UC
ST7L35F2UC
ST7L38F2UC
ST7L39F2UC
ST7L34F2MA
ST7L35F2MA
ST7L38F2MA
ST7L39F2MA
ST7L34F2MC
ST7L35F2MC
ST7L38F2MC
ST7L39F2MC
-
yes
-
-
256
-
-40 to +85°C
yes
-
SO20
yes
-
-40 to +125°C
-40 to +85°C
-40 to +125°C
256
-
yes
-
8K ROM
384
yes
-
256
-
yes
-
QFN20
yes
-
256
yes
1. Contact ST sales office for product availability
160/168
ST7L34, ST7L35, ST7L38, ST7L39
ST7L3 FASTROM & ROM MICROCONTROLLER OPTION LIST
(Last update: December 2006)
Customer
Address
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact
Phone No
Reference FASTROM Code*: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
*FASTROM code name is assigned by STMicroelectronics.
FASTROM code must be sent in .S19 format. .Hex extension cannot be processed.
Device Type/Memory Size/Package (check only one option):
------------------------------------ ------------------------------------
FASTROM DEVICE 8K: SO20
------------------------------------
QFN20
----------------------------------- ------------------------------------
-----------------------------------
[ ] ST7PL34F2U
[ ] ST7PL35F2U
[ ] ST7PL38F2U
[ ] ST7PL39F2U
------------------------------------
QFN20
[ ] ST7PL34F2M
[ ] ST7PL35F2M
[ ] ST7PL38F2M
[ ] ST7PL39F2M
------------------------------------ ------------------------------------
ROM DEVICE 8K:
SO20
----------------------------------- ------------------------------------
-----------------------------------
[ ] ST7L34F2M
[ ] ST7L35F2M
[ ] ST7L38F2M
[ ] ST7L39F2M
[ ] ST7L34F2U
[ ] ST7L35F2U
[ ] ST7L38F2U
[ ] ST7L39F2U
Conditioning (check only one option):[ ] Tape & Reel
[ ] Tube
[ ] Yes "_ _ _ _ _ _ _ _ "
Special Marking:
[ ] No
Authorized characters are letters, digits, '.', '-', '/' and spaces only.
Maximum character count:
SO20 (8 char. max): _ _ _ _ _ _ _ _
QFN20 (8 char. max): _ _ _ _ _ _ _ _
Temperature range:
[ ] A (-40°C to +85°C)
[ ] C (-40°C to +125°C°)
AWUCK Selection:
[ ] 32 kHz Oscillator
[ ] Resonator:
[ ] AWU RC Oscillator
Clock Source Selection:
[ ] VLP: Very Low power resonator (32 to 100 kHz)
[ ] LP: Low power resonator (1 to 2 MHz)
[ ] MP: Medium power resonator (2 to 4 MHz)
[ ] MS: Medium speed resonator (4 to 8 MHz)
[ ] HS: High speed resonator (8 to 16 MHz)
[ ] External Clock:
[ ] on PB4
[ ] on OSC1
[ ] Internal RC Oscillator
PLL:
[ ] Disabled
[ ] Enabled
LVD Reset:
[ ] Disabled
[ ] Enabled (Highest voltage threshold)
[ ] Hardware Activation
[ ] Enabled
Watchdog Selection:
Watchdog Reset on Halt:
[ ] Software Activation
[ ] Disabled
Flash Devices only
Sector 0 size:
Readout Protection:
Flash Write Protection:
[ ] 0.5K
[ ] Disabled
[ ] Disabled
[ ] 1K
[ ] Enabled
[ ] Enabled
[ ] 2K
[ ] 4K
ROM Devices only
Readout Protection for ROM:
Readout Protection for E2data:
[ ] Disabled
[ ] Disabled
[ ] Enabled
[ ] Enabled
Comments:
Supply Operating Range in the application: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Notes:
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Date:
Signature:
Important note: Not all configurations are available. See section 15.1 on page 154 for authorized option byte combinations.
161/168
ST7L34, ST7L35, ST7L38, ST7L39
DEVICE CONFIGURATION (cont’d)
15.4 DEVELOPMENT TOOLS
Development tools for the ST7 microcontrollers in-
clude a complete range of hardware systems and
software tools from STMicroelectronics and third-
party tool suppliers. The range of tools includes
solutions to help you evaluate microcontroller pe-
ripherals, develop and debug your application, and
program your microcontrollers.
guage debugger, editor, project manager and inte-
grated programming interface.
15.4.3 Programming Tools
During the development cycle, the ST7-DVP3 and
ST7-EMU3 series emulators and the RLink pro-
vide in-circuit programming capability for program-
ming the Flash microcontroller on your application
board.
15.4.1 Starter Kits
ST offers complete, affordable starter kits. Starter
kits are complete, affordable hardware/software
tool packages that include features and samples
to help you quickly start developing your applica-
tion.
ST also provides dedicated a low-cost dedicated
in-circuit programmer, the ST7-STICK, as well as
ST7 Socket Boards which provide all the sockets
required for programming any of the devices in a
specific ST7 subfamily on a platform that can be
used with any tool with in-circuit programming ca-
pability for ST7.
15.4.2 Development and Debugging Tools
Application development for ST7 is supported by
fully optimizing C Compilers and the ST7 Assem-
bler-Linker toolchain, which are all seamlessly in-
tegrated in the ST7 integrated development envi-
ronments in order to facilitate the debugging and
fine-tuning of your application. The Cosmic C
Compiler is available in a free version that outputs
up to 16 Kbytes of code.
For production programming of ST7 devices, ST’s
third-party tool partners also provide a complete
range of gang and automated programming solu-
tions, which are ready to integrate into your pro-
duction environment.
15.4.4 Order Codes for Development and
Programming Tools
The range of hardware tools includes full-featured
ST7-EMU3 series emulators, cost effective ST7-
DVP3 series emulators and the low-cost RLink
in-circuit debugger/programmer. These tools are
supported by the ST7 Toolset from STMicroelec-
tronics, which includes the STVD7 integrated de-
velopment environment (IDE) with high-level lan-
Table 36 below lists the ordering codes for the
ST7L3x development and programming tools. For
additional ordering codes for spare parts and ac-
cessories, refer to the online product selector at
www.st.com/mcu.
Table 36. ST7L3x Development and Programming Tools
In-circuit Debugger,
Emulator
Programming Tool
1)
RLink Series
Supported
Products
Starter Kit
with
Starter Kit
without
ST Socket
Boards and
EPBs
In-circuit
DVP Series
EMU Series
Programmer
Demo Board Demo Board
ST7FL34
ST7FL35
ST7FL38
ST7FL39
ST7FLITE-SK/
ST7-STICK
STX-RLINK
2)6)
3)
3)
STX-RLINK
ST7MDT10-DVP3 ST7MDT10-EMU3
ST7SB10-123
3)5)
2)6)
RAIS
Notes:
1. Available from ST or from Raisonance, www.raiso-
nance.com
2. USB connection to PC
3. Add suffix /EU, /UK or /US for the power supply for your
region
4. Includes connection kit for DIP16/SO16 only. See “How
to order an EMU or DVP” in ST product and tool selection
guide for connection kit ordering information
5. Parallel port connection to PC
162/168
ST7L34, ST7L35, ST7L38, ST7L39
16 IMPORTANT NOTES
16.1
CLEARING
ACTIVE
INTERRUPTS
16.2 LINSCI LIMITATIONS
OUTSIDE INTERRUPT ROUTINE
16.2.1 Header Time-out Does Not Prevent
Wake-up from Mute Mode
When an active interrupt request occurs at the
same time as the related flag or interrupt mask is
being cleared, the CC register may be corrupted.
Normally, when LINSCI is configured in LIN slave
mode, if a header time-out occurs during a LIN
header reception (that is, header length > 57 bits),
the LIN Header Error bit (LHE) is set, an interrupt
occurs to inform the application but the LINSCI
should stay in mute mode, waiting for the next
header reception.
Concurrent interrupt context
The symptom does not occur when the interrupts
are handled normally, that is, when:
– The interrupt request is cleared (flag reset or in-
terrupt mask) within its own interrupt routine
Problem Description
– The interrupt request is cleared (flag reset or in-
terrupt mask) within any interrupt routine
The LINSCI sampling period is Tbit / 16. If a LIN
Header time-out occurs between the 9th and the
15th sample of the Identifier Field Stop Bit (refer to
Figure 107), the LINSCI wakes up from mute
mode. Nevertheless, LHE is set and LIN Header
Detection Flag (LHDF) is kept cleared.
– The interrupt request is cleared (flag reset or in-
terrupt mask) in any part of the code while this in-
terrupt is disabled
If these conditions are not met, the symptom is
avoided by implementing the following sequence:
In addition, if LHE is reset by software before this
15th sample (by accessing the SCISR register and
reading the SCIDR register in the LINSCI interrupt
routine), the LINSCI will generate another LINSCI
interrupt (due to the RDRF flag setting).
Perform SIM and RIM operation before and after
resetting an active interrupt request.
Example:
SIM
reset flag or interrupt mask
RIM
Figure 107. Header Reception Event Sequence
LIN Synch
Break
LIN Synch
Field
Identifier
Field
T
HEADER
ID field STOP bit
Critical
Window
Active mode is set
(RWU is cleared)
RDRF flag is set
163/168
ST7L34, ST7L35, ST7L38, ST7L39
IMPORTANT NOTES (cont’d)
Impact on application
Workaround
Software may execute the interrupt routine twice
after header reception.
The problem can be detected in the LINSCI inter-
rupt routine. In case of time-out error (LHE is set
and LHLR is loaded with 00h), the software can
check the RWU bit in the SCICR2 register. If RWU
is cleared, it can be set by software (refer to Figure
108). The workaround is shown in bold characters.
Moreover, in reception mode, as the receiver is no
longer in mute mode, an interrupt is generated on
each data byte reception.
Figure 108. LINSCI Interrupt Routine
@interrupt void LINSCI_IT ( void ) /* LINSCI interrupt routine */
{
/* clear flags */
SCISR_buffer = SCISR;
SCIDR_buffer = SCIDR;
if ( SCISR_buffer & LHE )/* header error ? */
{
if (!LHLR)/* header time-out? */
{
if ( !(SCICR2 & RWU) )/* active mode ? */
{
_asm("sim");/* disable interrupts */
SCISR;
SCIDR;/* Clear RDRF flag */
SCICR2 |= RWU;/* set mute mode */
SCISR;
SCIDR;/* Clear RDRF flag */
SCICR2 |= RWU;/* set mute mode */
_asm("rim");/* enable interrupts */
}
}
}
}
Example using Cosmic compiler syntax
164/168
ST7L34, ST7L35, ST7L38, ST7L39
17 REVISION HISTORY
Date
Revision
Main changes
June-2004
1.0
First Release
Changed status of the document; Changed device summary
Added ROM/FASTROM versions; Changed first page description
Changed temperature range (added -40 to +125°C)
Removed references to 1% internal RC accuracy; Changed “Memory Map” on page 10
Removed reference to amplifier for ADCDRL in Table 3, “Hardware Register Map,” on
page 11 and in section 11.6.6 on page 119 and replaced “Data Register Low” By “Control and
Data Register Low”; Changed section 4.4 on page 14 and added note 6
Modified note on clock stability and on ICC mode in section 7.1 on page 24
Added text in note 1 in “INTERNAL RC OSCILLATOR ADJUSTMENT” on page 24
Added RCCR1 (Figure 4 on page 10 and section 7 on page 24)
Added note to section 7.5 on page 28; Added note 2 after Table 9 on page 47
Exit from HALT mode during an overflow event set to “No” in section 11.2.4 on page 62
Removed Watchdog section in section 11.3 on page 69
Low Power Modes (Section 11.3.4) and Interrupts (Section 11.3.5) tables expanded
Added important note in section 11.4.3.3 on page 81
23-Dec-2005
2
Changed procedure description in section 11.5.5.2 on page 90
In section 11.5.5.5 on page 92: Correct equation for Rx to read: Rx = f
/(16 x ERPR x PR
CPU
x RR), {instead of Rx = f
/(16 x ERPR x PR x TR)}
CPU
Added note on illegal opcode reset to section 12.2.1 on page 124; Changed Section 13.1.2
Changed electrical characteristics section: section 13.3 on page 129, section 13.4 on page
135, section 13.6 on page 138, section 13.7.3 on page 140, section 13.8 on page 141, section
13.9 on page 145, section 13.10 on page 147 and section 13.11 on page 149
Modified section 14 on page 151
Changed section 15.1 on page 154 (OPT 5 of option byte 1), section 15.2 on page 157 and
section 15.4 on page 162
Changed option list, Added “IMPORTANT NOTES” on page 163
Removed all x4 PLL option references from document
Changed Read operation section in section 5.3 on page 17
Changed note Figure 8 on page 18
Changed section 5.5 on page 19
Replaced 3.3V with 3.6V in section 7.2 on page 24
Changed “Master Mode Operation” on page 78: added important note
Changed section 13.1.2 on page 127
Changed section 13.3.1 on page 129 and added note on clock stability and frequency accu-
racy; removed the following figure: PLL ∆f
/f
versus time
CPU CPU
Changed section 13.3.2 on page 134 and section 13.3.4 on page 134
Changed section 13.4.1 on page 135 and added notes
Changed “EEPROM Data Memory” on page 138
Removed note 6 section 13.6 on page 138
Changed section 13.6.2 on page 138; Changed section 13.6.3 on page 138
Changed values in section 13.7.2 on page 139
06-Mar-2006
3
Changed Absolute Maximum Ratings in section 13.7.3 on page 140
Changed section 13.8.1 on page 141 and section 13.8.2 on page 142
Changed section 13.9.1 on page 145 (changed values, removed references to 3V and added
note 5)
Changed section 13.11 on page 149: changed values in ADC accuracy tables and added note
3
Changed notes in section 14.2 on page 153
Changed section 14.3 on page 153
Changed Table 32, “Soldering Compatibility (wave and reflow soldering process),” on
page 153
Added note to OSC option bit in section 15.1 on page 154
165/168
ST7L34, ST7L35, ST7L38, ST7L39
Date
Revision
Main changes
Changed OPT 7 configuration “Option Byte 1” on page 156
06-Mar-2006
3
Changed Device Type/Memory Size/Package table and PLL Options in “ST7L3 FASTROM
MICROCONTROLLER OPTION LIST (Last update: March 2006)” on page 160
Changed Caution text in section 8.2 on page 35
Changed External Interrupt Function in section 10.2.1 on page 46
Changed section 13.3.1.1 on page 130
Changed section 13.3.1.2 on page 132
Changed Figure 95 on page 145
17-Mar-2006
4
Removed EMC protective circuitry in Figure 96 on page 146 (device works correctly without
these components)
Removed section “LINSCI Wrong break duration” from section 16 on page 163
Replaced “ST7L3” with “ST7L34, ST7L35, ST7L38, ST7L39” in document name on page 1
Added QFN20 package to package outline on page 1
Changed section 1 on page 5
Transferred Device Summary from cover page to section 1 on page 5
Added QFN20 package to Table 1, “Device Summary,” on page 5
Figure 1 on page 6: Replaced Autoreload Timer 2 with Autoreload Timer 3
Added QFN20 package pinout (Figure 3 on page 7) to Section 2
Table 2 on page 8:
- Added QFN20 package pin numbers
- Removed caution about PB0 and PB1 negative current injection restriction
“Memory Map” on page 10: Removed references to note 2 (note 2 does not exist)
Table 3 on page 11:
- Changed register name for LTCNTR
- Changed reset status of registers LTCSR1, ATCSR and SICSR
- Changed note 3
Changed last paragraph of section 5.5 on page 19
Added caution about avoiding unwanted behavior during Reset sequence in section 7.5.1 on
page 28
Figure 16 on page 30: Replaced “T
” with “t
” at bottom of figure
CPU
CPU
Changed notes in section 7.6.1 on page 31
Figure 18 on page 32: Removed names from SICSR bits 7:5
Changed reset value of bits CR0 and CR1 from 0 to 1 in section 7.6.4 on page 34
Table 7 on page 37: Restored table number (inadvertantly removed in Rev. 3)
Figure 33 on page 51: Changed register label
20-Dec-2006
5
Changed register name and label in section 11.1.6 on page 52
Added note for ROM devices only to section 11.2.3.1 on page 55
Replaced bit name OVIE1 with OVFIE1 in section 11.2.5 on page 62
Changed description of bits 11:0 of CNTR1 register in section 11.2.6 on page 63
Changed name of register ATR1H and ATR1L in section 11.2.6 on page 63
Changed name of register ATR2H and ATR2L in section 11.2.6 on page 63
Changed name of register ATCSR2 in section 11.2.6 on page 63
Changed name of register LTCSR1 in section 11.3.6 on page 71
Changed names of registers SPIDR, SPICR and SPICSR in section 11.4.8 on page 83
Figure 61 on page 106:
- replaced “t
” with “T
”
CPU
CPU
- replaced “t ” with “T
”
BR
BR
Modified section 13.2.2 on page 128:
- Changed I values
IO
- Removed “Injected current on PB0 and PB1 pins” from table
- Removed note 5 “No negative current injection allowed on PB0 and PB1 pins”
Restored symbol for PLL jitter in section 13.3.1.1 on page 130 (inadvertantly changed in Rev.
4)
Added note 5 to section 13.3.2 on page 134
Specified applicable T in section 13.6.1 on page 138, section 13.6.2 on page 138 and section
A
13.6.3 on page 138
166/168
ST7L34, ST7L35, ST7L38, ST7L39
Date
Revision
Main changes
Changed T for Programming time for 1~32 bytes and changed T
from 125°C to 85°C
A
PROG
for write erase cycles in section 13.6.2 on page 138
Figure 81 on page 141: Replaced ST7XXX with ST7
Table 27 on page 142: Added table number and title
Table 28 on page 145: Added table number and title
Replaced ST72XXX with ST7 in Figure 95 on page 145 and Figure 96 on page 146
Changed section 13.10.1 on page 147
Figure 98 on page 148: Replaced CPHA = 0 with CPHA = 1
Figure 99 on page 148: Repositioned t
and t
v(MO)
h(MO)
Table 29 on page 149: Added table number and title
Figure 100 on page 149: Replaced ST72XXX with ST7
Changed typical and maximum values and added table number and title to Table 30 on
page 150 and to Table 31 on page 150
Added Figure 103. QFN 5x6: 20-Lead Very Thin Fine Pitch Quad Flat No-Lead Package on
page 152
Added QFN20 package to section 14.2 on page 153
Changed P
value for SO20 package in section 14.2 on page 153
Dmax
Removed text concerning LQFP, TQFP and SDIP packages from section 14.3 on page 153
Removed text concerning Pb-containing packages from section 14.3 on page 153
Table 32 on page 153:
20-Dec-2006
5
- Changed title of “Plating Material” column
- Added QFN package
- Removed note concerning Pb-package temperature for leadfree soldering compatibility
Changed Section 15.1 OPTION BYTES to add different configurations between Flash and
ROM devices for OPTION BYTE 0
Removed “AUTOMOTIVE” from title of section 15.2 on page 157
Removed Table 26, “Supported Part Numbers”, from Section 15.2 DEVICE ORDERING IN-
FORMATION AND TRANSFER OF CUSTOMER CODE
Added Figure 104. Flash Device Types on page 157
Added Table 33, “Flash User Programmable Device Types,” on page 158
Added Figure 105. FASTROM Commercial Product Code Structure on page 159
Added Table 34, “FASTROM Factory Coded Device Types,” on page 159
Added Figure 106. ROM Commercial Product Code Structure on page 160
Added Table 35, “ROM Factory Coded Device Types,” on page 160
Updated option list on page 161
Changed Section 15.4 and Table 36 on page 162
Updated disclaimer (last page) to include a mention about the use of ST products in automo-
tive applications
167/168
ST7L34, ST7L35, ST7L38, ST7L39
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its
subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this docu-
ment, and the products and services described herein at any time, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described
herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and
services described herein.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this
document. If any part of this document refers to any third party products or services it shall not be deemed a li-
cense grant by ST for the use of such third party products or services, or any intellectual property contained
therein or considered as a warranty covering the use in any manner whatsoever of such third party products or
services or any intellectual property contained therein.
UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EX-
PRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS IN-
CLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PAR-
TICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR IN-
FRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PROD-
UCTS ARE NOT RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT,
SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE
FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR
ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE GRADE"
MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK.
Resale of ST products with provisions different from the statements and/or technical features set forth in this doc-
ument shall immediately void any warranty granted by ST for the ST product or service described herein and
shall not create or extend in any manner whatsoever, any liability of ST.
ST and the ST logo are trademarks or registered trademarks of ST in various countries.
Information in this document supersedes and replaces all information previously supplied.
The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective
owners.
© 2006 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India
- Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom
- United States of America
www.st.com
168/168
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